From ca2fb05cb7e41d7f8b7399adbc2e71016483efad Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 2 May 2023 12:02:42 -0500 Subject: ARM: dts: allwinner: Use quoted #include In preparation to move .dts files into subdirectories, include sunxi-h3-h5-emlid-neutis.dtsi from the current directory rather than the symlinked include path. Reviewed-by: Andre Przywara Signed-off-by: Rob Herring --- arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi index eedd5da5dc2f..35e71f46c197 100644 --- a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi @@ -8,4 +8,4 @@ /dts-v1/; #include "sun8i-h3.dtsi" -#include +#include "sunxi-h3-h5-emlid-neutis.dtsi" -- cgit v1.2.3 From 86684c2481b6e6a46c2282acee13554e34e66071 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 2 May 2023 12:25:29 -0500 Subject: ARM: dts: Add .dts files missing from the build Comparing .dts files to built .dtb files yielded a few .dts files which are never built. Add them to the build. Signed-off-by: Rob Herring --- arch/arm/boot/dts/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8e1b1f2cfb27..c6798925fe45 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -368,6 +368,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-iconnect.dtb \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ + kirkwood-km_fixedeth.dtb \ kirkwood-km_kirkwood.dtb \ kirkwood-l-50.dtb \ kirkwood-laplug.dtb \ @@ -914,7 +915,10 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ am3517-craneboard.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ + logicpd-torpedo-35xx-devkit.dtb \ logicpd-torpedo-37xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit-28.dtb \ + logicpd-som-lv-35xx-devkit.dtb \ logicpd-som-lv-37xx-devkit.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ @@ -1599,6 +1603,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-388-helios4.dtb \ armada-388-rd.dtb dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-390-db.dtb \ + armada-395-gp.dtb \ armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ @@ -1628,6 +1634,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt2701-evb.dtb \ mt6580-evbp1.dtb \ + mt6582-prestigio-pmt5008-3g.dtb \ mt6589-aquaris5.dtb \ mt6589-fairphone-fp1.dtb \ mt6592-evb.dtb \ @@ -1683,6 +1690,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-inspur-nf5280m6.dtb \ + aspeed-bmc-inspur-on5263m5.dtb \ aspeed-bmc-lenovo-hr630.dtb \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ -- cgit v1.2.3 From 6a1d798feb65d2a67e6e2cafb0b0e4f430603226 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Dec 2018 10:29:51 -0600 Subject: kbuild: Support flat DTBs install In preparation to move Arm .dts files into sub-directories grouped by vendor/family, the current flat tree of DTBs generated by dtbs_install needs to be maintained. Moving the installed DTBs to sub-directories would break various consumers using 'make dtbs_install'. This is a NOP until sub-directories are introduced. Signed-off-by: Rob Herring --- arch/arm/Kconfig | 3 +++ scripts/Makefile.dtbinst | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0fb4b218f665..47c1845f0b1b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1460,6 +1460,9 @@ config USE_OF help Include support for flattened device tree machine descriptions. +config ARCH_WANT_FLAT_DTB_INSTALL + def_bool y + config ATAGS bool "Support for the traditional ATAGS boot data passing" default y diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 2ab936e4179d..4405d5b67578 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -34,6 +34,6 @@ $(dst)/%.dtbo: $(obj)/%.dtbo PHONY += $(subdirs) $(subdirs): - $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) + $(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@)) .PHONY: $(PHONY) -- cgit v1.2.3 From 724ba6751532055db75992fc6ae21c3e322e94a7 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 4 May 2023 18:38:52 -0500 Subject: ARM: dts: Move .dts files to vendor sub-directories The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar Acked-by: Michal Simek #Xilinx Acked-by: Krzysztof Kozlowski Acked-by: Neil Armstrong Acked-by: Paul Barker Acked-by: Tony Lindgren Acked-by: Gregory CLEMENT Acked-by: Heiko Stuebner Acked-by: Wei Xu #hisilicon Acked-by: Geert Uytterhoeven Acked-by: Nick Hawkins Acked-by: Baruch Siach Reviewed-by: Linus Walleij Reviewed-by: Andre Przywara Acked-by: Andre Przywara Reviewed-by: Claudiu Beznea Acked-by: Peter Rosin Acked-by: Jesper Nilsson Acked-by: Sudeep Holla Acked-by: Florian Fainelli #broadcom Acked-by: Manivannan Sadhasivam Reviewed-by: Jisheng Zhang Acked-by: Patrice Chotard Acked-by: Romain Perier Acked-by: Alexandre TORGUE Acked-by: Shawn Guo Acked-by: Kunihiko Hayashi Acked-by: Enric Balletbo i Serra Signed-off-by: Rob Herring --- MAINTAINERS | 186 +- arch/arm/boot/dts/Makefile | 1757 +---- arch/arm/boot/dts/actions/Makefile | 7 + arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts | 36 + .../boot/dts/actions/owl-s500-guitar-bb-rev-b.dts | 25 + arch/arm/boot/dts/actions/owl-s500-guitar.dtsi | 21 + .../boot/dts/actions/owl-s500-labrador-base-m.dts | 28 + .../arm/boot/dts/actions/owl-s500-labrador-v2.dtsi | 22 + arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts | 299 + arch/arm/boot/dts/actions/owl-s500-sparky.dts | 36 + arch/arm/boot/dts/actions/owl-s500.dtsi | 338 + arch/arm/boot/dts/airoha/Makefile | 3 + arch/arm/boot/dts/airoha/en7523-evb.dts | 43 + arch/arm/boot/dts/airoha/en7523.dtsi | 206 + arch/arm/boot/dts/aks-cdu.dts | 122 - arch/arm/boot/dts/allwinner/Makefile | 315 + arch/arm/boot/dts/allwinner/axp152.dtsi | 49 + arch/arm/boot/dts/allwinner/axp209.dtsi | 126 + arch/arm/boot/dts/allwinner/axp223.dtsi | 58 + arch/arm/boot/dts/allwinner/axp22x.dtsi | 176 + arch/arm/boot/dts/allwinner/axp809.dtsi | 60 + arch/arm/boot/dts/allwinner/axp81x.dtsi | 164 + arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts | 255 + .../boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts | 151 + .../dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts | 159 + .../boot/dts/allwinner/sun4i-a10-cubieboard.dts | 255 + .../dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts | 218 + arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts | 192 + .../arm/boot/dts/allwinner/sun4i-a10-hackberry.dts | 140 + .../boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts | 115 + arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts | 229 + .../arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts | 203 + .../boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts | 357 ++ .../allwinner/sun4i-a10-itead-iteaduino-plus.dts | 126 + .../boot/dts/allwinner/sun4i-a10-jesurun-q5.dts | 181 + .../arm/boot/dts/allwinner/sun4i-a10-marsboard.dts | 182 + .../boot/dts/allwinner/sun4i-a10-mini-xplus.dts | 144 + arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts | 144 + arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts | 111 + .../dts/allwinner/sun4i-a10-olinuxino-lime.dts | 225 + arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts | 200 + arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts | 67 + .../dts/allwinner/sun4i-a10-pov-protab2-ips9.dts | 206 + .../boot/dts/allwinner/sun4i-a10-topwise-a721.dts | 242 + arch/arm/boot/dts/allwinner/sun4i-a10.dtsi | 1271 ++++ .../boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts | 137 + .../boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts | 149 + arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts | 127 + .../dts/allwinner/sun5i-a10s-olinuxino-micro.dts | 272 + .../boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts | 118 + arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts | 195 + arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi | 173 + .../dts/allwinner/sun5i-a13-difrnce-dit4350.dts | 50 + .../allwinner/sun5i-a13-empire-electronix-d709.dts | 190 + .../allwinner/sun5i-a13-empire-electronix-m712.dts | 51 + arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts | 182 + .../boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts | 50 + .../boot/dts/allwinner/sun5i-a13-licheepi-one.dts | 214 + .../dts/allwinner/sun5i-a13-olinuxino-micro.dts | 141 + .../arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts | 247 + .../allwinner/sun5i-a13-pocketbook-touch-lux-3.dts | 258 + .../arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts | 80 + arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts | 116 + arch/arm/boot/dts/allwinner/sun5i-a13.dtsi | 118 + arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts | 238 + arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts | 333 + arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi | 126 + arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts | 282 + arch/arm/boot/dts/allwinner/sun5i-r8.dtsi | 47 + .../allwinner/sun5i-reference-design-tablet.dtsi | 194 + arch/arm/boot/dts/allwinner/sun5i.dtsi | 819 +++ .../arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts | 82 + arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts | 130 + .../boot/dts/allwinner/sun6i-a31-hummingbird.dts | 338 + arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts | 178 + arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts | 212 + .../dts/allwinner/sun6i-a31-mele-a1000g-quad.dts | 217 + arch/arm/boot/dts/allwinner/sun6i-a31.dtsi | 1422 +++++ .../dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts | 72 + arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts | 104 + .../boot/dts/allwinner/sun6i-a31s-inet-q972.dts | 98 + arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts | 267 + .../dts/allwinner/sun6i-a31s-sina31s-core.dtsi | 141 + arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts | 195 + .../dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts | 334 + .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 182 + arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi | 61 + .../allwinner/sun6i-reference-design-tablet.dtsi | 173 + .../dts/allwinner/sun7i-a20-bananapi-m1-plus.dts | 264 + arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts | 333 + .../arm/boot/dts/allwinner/sun7i-a20-bananapro.dts | 219 + .../boot/dts/allwinner/sun7i-a20-cubieboard2.dts | 237 + .../boot/dts/allwinner/sun7i-a20-cubietruck.dts | 345 + .../dts/allwinner/sun7i-a20-haoyu-marsboard.dts | 182 + .../boot/dts/allwinner/sun7i-a20-hummingbird.dts | 233 + .../arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts | 198 + .../dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts | 137 + .../boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi | 62 + .../boot/dts/allwinner/sun7i-a20-icnova-swac.dts | 164 + .../boot/dts/allwinner/sun7i-a20-itead-ibox.dts | 147 + .../arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts | 320 + .../allwinner/sun7i-a20-linutronix-testbox-v2.dts | 47 + arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts | 156 + arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts | 184 + .../allwinner/sun7i-a20-olimex-som-evb-emmc.dts | 35 + .../dts/allwinner/sun7i-a20-olimex-som-evb.dts | 329 + .../allwinner/sun7i-a20-olimex-som204-evb-emmc.dts | 34 + .../dts/allwinner/sun7i-a20-olimex-som204-evb.dts | 326 + .../allwinner/sun7i-a20-olinuxino-lime-emmc.dts | 32 + .../dts/allwinner/sun7i-a20-olinuxino-lime.dts | 216 + .../allwinner/sun7i-a20-olinuxino-lime2-emmc.dts | 69 + .../dts/allwinner/sun7i-a20-olinuxino-lime2.dts | 280 + .../allwinner/sun7i-a20-olinuxino-micro-emmc.dts | 68 + .../dts/allwinner/sun7i-a20-olinuxino-micro.dts | 354 ++ .../boot/dts/allwinner/sun7i-a20-orangepi-mini.dts | 242 + arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts | 201 + .../boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts | 225 + arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts | 227 + .../dts/allwinner/sun7i-a20-wexler-tab7200.dts | 225 + .../dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts | 209 + arch/arm/boot/dts/allwinner/sun7i-a20.dtsi | 1710 +++++ arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi | 855 +++ arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts | 117 + arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts | 76 + arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts | 67 + .../boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts | 1 + .../boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts | 1 + .../allwinner/sun8i-a23-polaroid-mid2407pxe03.dts | 96 + .../allwinner/sun8i-a23-polaroid-mid2809pxe04.dts | 86 + .../arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts | 73 + arch/arm/boot/dts/allwinner/sun8i-a23.dtsi | 104 + .../boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts | 1 + .../boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts | 95 + .../dts/allwinner/sun8i-a33-inet-d978-rev2.dts | 103 + .../boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts | 1 + .../arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts | 226 + .../arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts | 57 + .../dts/allwinner/sun8i-a33-sinlinx-sina33.dts | 275 + arch/arm/boot/dts/allwinner/sun8i-a33.dtsi | 432 ++ .../allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts | 281 + .../boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts | 422 ++ .../dts/allwinner/sun8i-a83t-cubietruck-plus.dts | 464 ++ .../arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 506 ++ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 1274 ++++ .../allwinner/sun8i-h2-plus-bananapi-m2-zero.dts | 273 + .../sun8i-h2-plus-libretech-all-h3-cc.dts | 13 + .../dts/allwinner/sun8i-h2-plus-orangepi-r1.dts | 99 + .../dts/allwinner/sun8i-h2-plus-orangepi-zero.dts | 209 + .../allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts | 13 + .../dts/allwinner/sun8i-h3-bananapi-m2-plus.dts | 50 + .../arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts | 238 + .../sun8i-h3-emlid-neutis-n5h3-devboard.dts | 72 + .../dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi | 11 + .../dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts | 14 + .../dts/allwinner/sun8i-h3-mapleboard-mp130.dts | 152 + .../boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 173 + .../boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts | 166 + arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts | 106 + .../boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts | 143 + .../arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts | 76 + arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts | 169 + arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi | 111 + .../arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts | 209 + .../boot/dts/allwinner/sun8i-h3-orangepi-lite.dts | 168 + .../boot/dts/allwinner/sun8i-h3-orangepi-one.dts | 203 + .../dts/allwinner/sun8i-h3-orangepi-pc-plus.dts | 86 + .../boot/dts/allwinner/sun8i-h3-orangepi-pc.dts | 242 + .../boot/dts/allwinner/sun8i-h3-orangepi-plus.dts | 135 + .../dts/allwinner/sun8i-h3-orangepi-plus2e.dts | 79 + .../dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts | 177 + .../boot/dts/allwinner/sun8i-h3-rervision-dvk.dts | 114 + arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts | 85 + arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 335 + arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi | 118 + .../boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts | 311 + .../allwinner/sun8i-r16-nintendo-nes-classic.dts | 54 + .../sun8i-r16-nintendo-super-nes-classic.dts | 11 + arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts | 313 + .../dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts | 340 + arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi | 52 + arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi | 111 + arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts | 203 + arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 1326 ++++ .../allwinner/sun8i-reference-design-tablet.dtsi | 224 + .../boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi | 44 + .../boot/dts/allwinner/sun8i-s3-elimo-initium.dts | 29 + .../dts/allwinner/sun8i-s3-lichee-zero-plus.dts | 53 + arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts | 228 + .../allwinner/sun8i-t113s-mangopi-mq-r-t113.dts | 35 + arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 59 + arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts | 231 + .../boot/dts/allwinner/sun8i-v3-sl631-imx179.dts | 12 + arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi | 138 + arch/arm/boot/dts/allwinner/sun8i-v3.dtsi | 63 + .../dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts | 105 + .../boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts | 101 + arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 621 ++ .../dts/allwinner/sun8i-v40-bananapi-m2-berry.dts | 310 + .../boot/dts/allwinner/sun9i-a80-cubieboard4.dts | 508 ++ arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts | 510 ++ arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 1253 ++++ .../dts/allwinner/suniv-f1c100s-licheepi-nano.dts | 73 + arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi | 330 + .../boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts | 76 + .../dts/allwinner/suniv-f1c200s-popstick-v1.1.dts | 81 + .../dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi | 42 + .../boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi | 244 + .../dts/allwinner/sunxi-common-regulators.dtsi | 111 + .../dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 + .../dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi | 170 + arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 979 +++ .../dts/allwinner/sunxi-itead-core-common.dtsi | 132 + .../dts/allwinner/sunxi-libretech-all-h3-cc.dtsi | 237 + .../dts/allwinner/sunxi-libretech-all-h3-it.dtsi | 180 + .../allwinner/sunxi-reference-design-tablet.dtsi | 82 + arch/arm/boot/dts/alphascale-asm9260-devkit.dts | 13 - arch/arm/boot/dts/alphascale-asm9260.dtsi | 64 - arch/arm/boot/dts/alphascale/Makefile | 5 + .../dts/alphascale/alphascale-asm9260-devkit.dts | 13 + .../boot/dts/alphascale/alphascale-asm9260.dtsi | 64 + arch/arm/boot/dts/alpine-db.dts | 35 - arch/arm/boot/dts/alpine.dtsi | 176 - arch/arm/boot/dts/am335x-baltos-ir2110.dts | 227 - arch/arm/boot/dts/am335x-baltos-ir3220.dts | 273 - arch/arm/boot/dts/am335x-baltos-ir5221.dts | 297 - arch/arm/boot/dts/am335x-baltos-leds.dtsi | 47 - arch/arm/boot/dts/am335x-baltos.dtsi | 401 -- arch/arm/boot/dts/am335x-base0033.dts | 92 - arch/arm/boot/dts/am335x-bone-common.dtsi | 411 -- arch/arm/boot/dts/am335x-bone.dts | 23 - arch/arm/boot/dts/am335x-boneblack-common.dtsi | 30 - arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi | 146 - arch/arm/boot/dts/am335x-boneblack-wireless.dts | 111 - arch/arm/boot/dts/am335x-boneblack.dts | 174 - arch/arm/boot/dts/am335x-boneblue.dts | 616 -- arch/arm/boot/dts/am335x-bonegreen-common.dtsi | 41 - arch/arm/boot/dts/am335x-bonegreen-wireless.dts | 127 - arch/arm/boot/dts/am335x-bonegreen.dts | 14 - arch/arm/boot/dts/am335x-chiliboard.dts | 186 - arch/arm/boot/dts/am335x-chilisom.dtsi | 175 - arch/arm/boot/dts/am335x-cm-t335.dts | 516 -- arch/arm/boot/dts/am335x-evm.dts | 786 --- arch/arm/boot/dts/am335x-evmsk.dts | 725 --- arch/arm/boot/dts/am335x-guardian.dts | 745 --- arch/arm/boot/dts/am335x-icev2.dts | 518 -- arch/arm/boot/dts/am335x-igep0033.dtsi | 300 - arch/arm/boot/dts/am335x-lxm.dts | 347 - arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 225 - arch/arm/boot/dts/am335x-moxa-uc-2101.dts | 68 - arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi | 421 -- arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 101 - arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 277 - arch/arm/boot/dts/am335x-myirtech-myd.dts | 549 -- arch/arm/boot/dts/am335x-nano.dts | 492 -- arch/arm/boot/dts/am335x-netcan-plus-1xx.dts | 231 - arch/arm/boot/dts/am335x-netcom-plus-2xx.dts | 239 - arch/arm/boot/dts/am335x-netcom-plus-8xx.dts | 271 - arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 434 -- arch/arm/boot/dts/am335x-osd335x-common.dtsi | 124 - arch/arm/boot/dts/am335x-pcm-953.dtsi | 236 - arch/arm/boot/dts/am335x-pdu001.dts | 573 -- arch/arm/boot/dts/am335x-pepper.dts | 637 -- arch/arm/boot/dts/am335x-phycore-rdk.dts | 28 - arch/arm/boot/dts/am335x-phycore-som.dtsi | 343 - arch/arm/boot/dts/am335x-pocketbeagle.dts | 484 -- arch/arm/boot/dts/am335x-regor-rdk.dts | 24 - arch/arm/boot/dts/am335x-regor.dtsi | 201 - arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi | 67 - .../boot/dts/am335x-sancloud-bbe-extended-wifi.dts | 113 - arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts | 50 - arch/arm/boot/dts/am335x-sancloud-bbe.dts | 53 - arch/arm/boot/dts/am335x-sbc-t335.dts | 176 - arch/arm/boot/dts/am335x-shc.dts | 559 -- arch/arm/boot/dts/am335x-sl50.dts | 721 --- arch/arm/boot/dts/am335x-wega-rdk.dts | 23 - arch/arm/boot/dts/am335x-wega.dtsi | 210 - arch/arm/boot/dts/am33xx-clocks.dtsi | 779 --- arch/arm/boot/dts/am33xx-l4.dtsi | 2322 ------- arch/arm/boot/dts/am33xx.dtsi | 714 --- arch/arm/boot/dts/am3517-craneboard.dts | 171 - arch/arm/boot/dts/am3517-evm-ui.dtsi | 217 - arch/arm/boot/dts/am3517-evm.dts | 357 -- arch/arm/boot/dts/am3517-som.dtsi | 243 - arch/arm/boot/dts/am3517.dtsi | 216 - arch/arm/boot/dts/am3517_mt_ventoux.dts | 24 - arch/arm/boot/dts/am35xx-clocks.dtsi | 139 - arch/arm/boot/dts/am3703.dtsi | 14 - arch/arm/boot/dts/am3715.dtsi | 10 - arch/arm/boot/dts/am3874-iceboard.dts | 489 -- arch/arm/boot/dts/am4372.dtsi | 801 --- arch/arm/boot/dts/am437x-cm-t43.dts | 422 -- arch/arm/boot/dts/am437x-gp-evm.dts | 1137 ---- arch/arm/boot/dts/am437x-idk-evm.dts | 541 -- arch/arm/boot/dts/am437x-l4.dtsi | 2584 -------- arch/arm/boot/dts/am437x-sbc-t43.dts | 177 - arch/arm/boot/dts/am437x-sk-evm.dts | 902 --- arch/arm/boot/dts/am43x-epos-evm.dts | 1028 --- arch/arm/boot/dts/am43xx-clocks.dtsi | 1003 --- arch/arm/boot/dts/am57-pruss.dtsi | 226 - arch/arm/boot/dts/am5718.dtsi | 29 - arch/arm/boot/dts/am571x-idk-touchscreen.dtso | 32 - arch/arm/boot/dts/am571x-idk.dts | 218 - arch/arm/boot/dts/am5728.dtsi | 34 - arch/arm/boot/dts/am5729-beagleboneai.dts | 704 -- arch/arm/boot/dts/am572x-idk-common.dtsi | 203 - arch/arm/boot/dts/am572x-idk-touchscreen.dtso | 32 - arch/arm/boot/dts/am572x-idk.dts | 37 - arch/arm/boot/dts/am5748.dtsi | 34 - arch/arm/boot/dts/am574x-idk.dts | 49 - arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 647 -- arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 36 - arch/arm/boot/dts/am57xx-beagle-x15-revc.dts | 31 - arch/arm/boot/dts/am57xx-beagle-x15.dts | 38 - arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 628 -- arch/arm/boot/dts/am57xx-commercial-grade.dtsi | 24 - arch/arm/boot/dts/am57xx-evm.dtso | 127 - arch/arm/boot/dts/am57xx-idk-common.dtsi | 608 -- arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso | 63 - arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso | 66 - arch/arm/boot/dts/am57xx-industrial-grade.dtsi | 24 - arch/arm/boot/dts/am57xx-sbc-am57x.dts | 176 - arch/arm/boot/dts/amazon/Makefile | 5 + arch/arm/boot/dts/amazon/alpine-db.dts | 35 + arch/arm/boot/dts/amazon/alpine.dtsi | 176 + arch/arm/boot/dts/amlogic/Makefile | 9 + arch/arm/boot/dts/amlogic/meson.dtsi | 334 + arch/arm/boot/dts/amlogic/meson6-atv1200.dts | 33 + arch/arm/boot/dts/amlogic/meson6.dtsi | 73 + arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts | 97 + arch/arm/boot/dts/amlogic/meson8.dtsi | 806 +++ arch/arm/boot/dts/amlogic/meson8b-ec100.dts | 479 ++ arch/arm/boot/dts/amlogic/meson8b-mxq.dts | 189 + arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts | 383 ++ arch/arm/boot/dts/amlogic/meson8b.dtsi | 781 +++ arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts | 293 + arch/arm/boot/dts/amlogic/meson8m2.dtsi | 101 + arch/arm/boot/dts/animeo_ip.dts | 195 - .../dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts | 32 - arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts | 28 - arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts | 93 - arch/arm/boot/dts/arm-realview-eb-11mp.dts | 74 - arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts | 28 - arch/arm/boot/dts/arm-realview-eb-a9mp.dts | 70 - arch/arm/boot/dts/arm-realview-eb-bbrevd.dts | 29 - arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi | 45 - arch/arm/boot/dts/arm-realview-eb-mp.dtsi | 220 - arch/arm/boot/dts/arm-realview-eb.dts | 166 - arch/arm/boot/dts/arm-realview-eb.dtsi | 484 -- arch/arm/boot/dts/arm-realview-pb1176.dts | 608 -- arch/arm/boot/dts/arm-realview-pb11mp.dts | 736 --- arch/arm/boot/dts/arm-realview-pba8.dts | 178 - arch/arm/boot/dts/arm-realview-pbx-a9.dts | 228 - arch/arm/boot/dts/arm-realview-pbx.dtsi | 593 -- arch/arm/boot/dts/arm/Makefile | 30 + .../dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts | 32 + .../boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts | 28 + .../boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts | 93 + arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts | 74 + .../boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts | 28 + arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts | 70 + arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts | 29 + arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi | 45 + arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi | 220 + arch/arm/boot/dts/arm/arm-realview-eb.dts | 166 + arch/arm/boot/dts/arm/arm-realview-eb.dtsi | 484 ++ arch/arm/boot/dts/arm/arm-realview-pb1176.dts | 608 ++ arch/arm/boot/dts/arm/arm-realview-pb11mp.dts | 736 +++ arch/arm/boot/dts/arm/arm-realview-pba8.dts | 178 + arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts | 228 + arch/arm/boot/dts/arm/arm-realview-pbx.dtsi | 593 ++ arch/arm/boot/dts/arm/integrator.dtsi | 154 + arch/arm/boot/dts/arm/integratorap-im-pd1.dts | 276 + arch/arm/boot/dts/arm/integratorap.dts | 295 + arch/arm/boot/dts/arm/integratorcp.dts | 322 + arch/arm/boot/dts/arm/mps2-an385.dts | 92 + arch/arm/boot/dts/arm/mps2-an399.dts | 92 + arch/arm/boot/dts/arm/mps2.dtsi | 252 + arch/arm/boot/dts/arm/versatile-ab-ib2.dts | 30 + arch/arm/boot/dts/arm/versatile-ab.dts | 450 ++ arch/arm/boot/dts/arm/versatile-pb.dts | 114 + arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi | 494 ++ arch/arm/boot/dts/arm/vexpress-v2m.dtsi | 509 ++ arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts | 255 + arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts | 636 ++ arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts | 225 + arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts | 310 + arch/arm/boot/dts/armada-370-c200-v2.dts | 388 -- arch/arm/boot/dts/armada-370-db.dts | 244 - arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 330 - arch/arm/boot/dts/armada-370-mirabox.dts | 184 - arch/arm/boot/dts/armada-370-netgear-rn102.dts | 276 - arch/arm/boot/dts/armada-370-netgear-rn104.dts | 302 - arch/arm/boot/dts/armada-370-rd.dts | 268 - arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts | 33 - arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts | 131 - arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 237 - .../dts/armada-370-seagate-personal-cloud-2bay.dts | 48 - .../boot/dts/armada-370-seagate-personal-cloud.dts | 34 - .../dts/armada-370-seagate-personal-cloud.dtsi | 173 - arch/arm/boot/dts/armada-370-synology-ds213j.dts | 312 - arch/arm/boot/dts/armada-370-xp.dtsi | 313 - arch/arm/boot/dts/armada-370.dtsi | 439 -- arch/arm/boot/dts/armada-375-db.dts | 182 - arch/arm/boot/dts/armada-375.dtsi | 645 -- arch/arm/boot/dts/armada-380.dtsi | 148 - arch/arm/boot/dts/armada-381-netgear-gs110emx.dts | 295 - arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts | 112 - arch/arm/boot/dts/armada-385-atl-x530.dts | 235 - arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts | 120 - arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts | 84 - arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi | 450 -- arch/arm/boot/dts/armada-385-db-88f6820-amc.dts | 155 - arch/arm/boot/dts/armada-385-db-ap.dts | 238 - arch/arm/boot/dts/armada-385-linksys-caiman.dts | 144 - arch/arm/boot/dts/armada-385-linksys-cobra.dts | 144 - arch/arm/boot/dts/armada-385-linksys-rango.dts | 176 - arch/arm/boot/dts/armada-385-linksys-shelby.dts | 144 - arch/arm/boot/dts/armada-385-linksys.dtsi | 265 - arch/arm/boot/dts/armada-385-synology-ds116.dts | 292 - arch/arm/boot/dts/armada-385-turris-omnia.dts | 571 -- arch/arm/boot/dts/armada-385.dtsi | 185 - arch/arm/boot/dts/armada-388-clearfog-base.dts | 68 - arch/arm/boot/dts/armada-388-clearfog-pro.dts | 14 - arch/arm/boot/dts/armada-388-clearfog.dts | 185 - arch/arm/boot/dts/armada-388-clearfog.dtsi | 245 - arch/arm/boot/dts/armada-388-db.dts | 245 - arch/arm/boot/dts/armada-388-gp.dts | 406 -- arch/arm/boot/dts/armada-388-helios4.dts | 324 - arch/arm/boot/dts/armada-388-rd.dts | 108 - arch/arm/boot/dts/armada-388.dtsi | 37 - .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 117 - arch/arm/boot/dts/armada-38x.dtsi | 733 --- arch/arm/boot/dts/armada-390-db.dts | 142 - arch/arm/boot/dts/armada-390.dtsi | 23 - arch/arm/boot/dts/armada-395-gp.dts | 136 - arch/arm/boot/dts/armada-395.dtsi | 39 - arch/arm/boot/dts/armada-398-db.dts | 134 - arch/arm/boot/dts/armada-398.dtsi | 31 - arch/arm/boot/dts/armada-39x.dtsi | 594 -- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 359 -- arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 39 - arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 54 - arch/arm/boot/dts/armada-xp-axpwifiap.dts | 142 - arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts | 43 - arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts | 17 - arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi | 104 - arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts | 43 - arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts | 17 - arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi | 104 - .../boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts | 43 - arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts | 17 - arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi | 104 - arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 118 - arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 114 - arch/arm/boot/dts/armada-xp-db.dts | 245 - arch/arm/boot/dts/armada-xp-gp.dts | 230 - arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 293 - arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 397 -- arch/arm/boot/dts/armada-xp-matrix.dts | 79 - arch/arm/boot/dts/armada-xp-mv78230.dtsi | 257 - arch/arm/boot/dts/armada-xp-mv78260.dtsi | 404 -- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 453 -- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 357 -- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 209 - arch/arm/boot/dts/armada-xp-synology-ds414.dts | 328 - arch/arm/boot/dts/armada-xp.dtsi | 345 - arch/arm/boot/dts/artpec6-devboard.dts | 64 - arch/arm/boot/dts/artpec6.dtsi | 388 -- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 135 - arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts | 16 - arch/arm/boot/dts/aspeed-ast2600-evb.dts | 350 - arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts | 319 - arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 346 - arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 808 --- arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts | 585 -- .../dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 220 - arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 208 - arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 261 - arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 940 --- arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts | 418 -- .../arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 1077 ---- .../boot/dts/aspeed-bmc-facebook-cloudripper.dts | 544 -- arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts | 1590 ----- arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts | 203 - arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts | 1251 ---- .../arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts | 53 - .../boot/dts/aspeed-bmc-facebook-greatlakes.dts | 294 - arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts | 1339 ---- .../arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 549 -- arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts | 63 - arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 53 - arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts | 374 -- arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts | 127 - .../boot/dts/aspeed-bmc-facebook-yosemitev2.dts | 236 - arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 915 --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 3723 ----------- arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts | 14 - arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts | 21 - arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 2420 ------- arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts | 912 --- arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts | 691 -- arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts | 148 - arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts | 132 - .../boot/dts/aspeed-bmc-inventec-transformers.dts | 328 - arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 569 -- arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts | 666 -- arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts | 207 - arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts | 329 - arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts | 667 -- arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts | 326 - arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 373 -- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 354 -- arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 978 --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 887 --- arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 248 - arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 704 -- arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 578 -- arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts | 167 - arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts | 190 - arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 518 -- arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts | 610 -- arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts | 137 - arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 528 -- arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts | 471 -- arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts | 360 -- arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts | 149 - arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts | 255 - arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts | 154 - arch/arm/boot/dts/aspeed-bmc-vegman.dtsi | 311 - arch/arm/boot/dts/aspeed-g4.dtsi | 1453 ----- arch/arm/boot/dts/aspeed-g5.dtsi | 1661 ----- arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 1184 ---- arch/arm/boot/dts/aspeed-g6.dtsi | 1121 ---- arch/arm/boot/dts/aspeed/Makefile | 62 + arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts | 135 + arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts | 16 + arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts | 350 + .../boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts | 319 + .../boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts | 346 + .../boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts | 808 +++ .../dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts | 585 ++ .../aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts | 220 + .../dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts | 208 + .../dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts | 261 + .../boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts | 940 +++ .../boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts | 418 ++ .../dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 1077 ++++ .../dts/aspeed/aspeed-bmc-facebook-cloudripper.dts | 544 ++ .../boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts | 1590 +++++ .../boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts | 203 + .../boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts | 1251 ++++ .../dts/aspeed/aspeed-bmc-facebook-galaxy100.dts | 53 + .../dts/aspeed/aspeed-bmc-facebook-greatlakes.dts | 294 + .../dts/aspeed/aspeed-bmc-facebook-minipack.dts | 1339 ++++ .../dts/aspeed/aspeed-bmc-facebook-tiogapass.dts | 549 ++ .../dts/aspeed/aspeed-bmc-facebook-wedge100.dts | 63 + .../dts/aspeed/aspeed-bmc-facebook-wedge40.dts | 53 + .../dts/aspeed/aspeed-bmc-facebook-wedge400.dts | 374 ++ .../boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts | 127 + .../dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts | 236 + .../arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts | 915 +++ .../arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts | 3723 +++++++++++ .../dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts | 14 + .../boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts | 21 + .../arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts | 2420 +++++++ .../boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts | 912 +++ .../boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts | 691 ++ .../boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts | 148 + .../boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts | 132 + .../aspeed/aspeed-bmc-inventec-transformers.dts | 328 + .../boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts | 569 ++ .../boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts | 666 ++ .../dts/aspeed/aspeed-bmc-microsoft-olympus.dts | 207 + .../arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts | 329 + arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts | 667 ++ arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts | 326 + .../boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts | 373 ++ .../arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts | 354 ++ arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts | 978 +++ arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts | 887 +++ arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts | 248 + .../boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts | 704 ++ arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts | 578 ++ .../dts/aspeed/aspeed-bmc-portwell-neptune.dts | 167 + .../boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts | 190 + .../arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts | 518 ++ arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts | 610 ++ .../dts/aspeed/aspeed-bmc-supermicro-x11spi.dts | 137 + arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts | 528 ++ arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts | 471 ++ .../dts/aspeed/aspeed-bmc-ufispace-ncplite.dts | 360 ++ .../arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts | 149 + .../arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts | 255 + .../arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts | 154 + arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi | 311 + arch/arm/boot/dts/aspeed/aspeed-g4.dtsi | 1453 +++++ arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 1661 +++++ arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 1184 ++++ arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 1121 ++++ .../dts/aspeed/ast2400-facebook-netbmc-common.dtsi | 121 + .../dts/aspeed/ast2500-facebook-netbmc-common.dtsi | 82 + .../dts/aspeed/ast2600-facebook-netbmc-common.dtsi | 169 + .../dts/aspeed/facebook-bmc-flash-layout-128.dtsi | 60 + .../boot/dts/aspeed/facebook-bmc-flash-layout.dtsi | 42 + arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi | 248 + .../boot/dts/aspeed/openbmc-flash-layout-128.dtsi | 32 + .../dts/aspeed/openbmc-flash-layout-64-alt.dtsi | 35 + .../boot/dts/aspeed/openbmc-flash-layout-64.dtsi | 35 + arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi | 32 + .../boot/dts/ast2400-facebook-netbmc-common.dtsi | 121 - .../boot/dts/ast2500-facebook-netbmc-common.dtsi | 82 - .../boot/dts/ast2600-facebook-netbmc-common.dtsi | 169 - arch/arm/boot/dts/at91-ariag25.dts | 183 - arch/arm/boot/dts/at91-ariettag25.dts | 87 - arch/arm/boot/dts/at91-cosino.dtsi | 152 - arch/arm/boot/dts/at91-cosino_mega2560.dts | 75 - arch/arm/boot/dts/at91-dvk_som60.dts | 95 - arch/arm/boot/dts/at91-dvk_su60_somc.dtsi | 159 - arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi | 90 - arch/arm/boot/dts/at91-foxg20.dts | 168 - arch/arm/boot/dts/at91-gatwick.dts | 121 - arch/arm/boot/dts/at91-kizbox.dts | 190 - arch/arm/boot/dts/at91-kizbox2-2.dts | 26 - arch/arm/boot/dts/at91-kizbox2-common.dtsi | 256 - arch/arm/boot/dts/at91-kizbox3-hs.dts | 309 - arch/arm/boot/dts/at91-kizbox3_common.dtsi | 371 -- arch/arm/boot/dts/at91-kizboxmini-base.dts | 24 - arch/arm/boot/dts/at91-kizboxmini-common.dtsi | 168 - arch/arm/boot/dts/at91-kizboxmini-mb.dts | 26 - arch/arm/boot/dts/at91-kizboxmini-rd.dts | 49 - arch/arm/boot/dts/at91-linea.dtsi | 71 - arch/arm/boot/dts/at91-lmu5000.dts | 147 - arch/arm/boot/dts/at91-natte.dtsi | 244 - arch/arm/boot/dts/at91-nattis-2-natte-2.dts | 306 - arch/arm/boot/dts/at91-q5xr5.dts | 181 - arch/arm/boot/dts/at91-qil_a9260.dts | 213 - arch/arm/boot/dts/at91-sam9_l9260.dts | 133 - arch/arm/boot/dts/at91-sam9x60_curiosity.dts | 503 -- arch/arm/boot/dts/at91-sam9x60ek.dts | 669 -- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 166 - arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 552 -- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 386 -- arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts | 269 - arch/arm/boot/dts/at91-sama5d2_icp.dts | 790 --- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 435 -- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 745 --- arch/arm/boot/dts/at91-sama5d3_eds.dts | 307 - arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts | 214 - arch/arm/boot/dts/at91-sama5d3_xplained.dts | 406 -- arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 136 - arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts | 164 - arch/arm/boot/dts/at91-sama5d4_xplained.dts | 298 - arch/arm/boot/dts/at91-sama5d4ek.dts | 323 - arch/arm/boot/dts/at91-sama7g5ek.dts | 834 --- arch/arm/boot/dts/at91-smartkiz.dts | 107 - arch/arm/boot/dts/at91-som60.dtsi | 230 - arch/arm/boot/dts/at91-tse850-3.dts | 362 -- arch/arm/boot/dts/at91-vinco.dts | 231 - arch/arm/boot/dts/at91-wb45n.dts | 61 - arch/arm/boot/dts/at91-wb45n.dtsi | 166 - arch/arm/boot/dts/at91-wb50n.dts | 102 - arch/arm/boot/dts/at91-wb50n.dtsi | 194 - arch/arm/boot/dts/at91rm9200.dtsi | 729 --- arch/arm/boot/dts/at91rm9200_pqfp.dtsi | 16 - arch/arm/boot/dts/at91rm9200ek.dts | 147 - arch/arm/boot/dts/at91sam9260.dtsi | 796 --- arch/arm/boot/dts/at91sam9260ek.dts | 188 - arch/arm/boot/dts/at91sam9261.dtsi | 667 -- arch/arm/boot/dts/at91sam9261ek.dts | 245 - arch/arm/boot/dts/at91sam9263.dtsi | 839 --- arch/arm/boot/dts/at91sam9263ek.dts | 262 - arch/arm/boot/dts/at91sam9g15.dtsi | 28 - arch/arm/boot/dts/at91sam9g15ek.dts | 36 - arch/arm/boot/dts/at91sam9g20.dtsi | 49 - arch/arm/boot/dts/at91sam9g20ek.dts | 28 - arch/arm/boot/dts/at91sam9g20ek_2mmc.dts | 54 - arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 309 - .../boot/dts/at91sam9g25-gardena-smart-gateway.dts | 158 - arch/arm/boot/dts/at91sam9g25.dtsi | 34 - arch/arm/boot/dts/at91sam9g25ek.dts | 65 - arch/arm/boot/dts/at91sam9g35.dtsi | 33 - arch/arm/boot/dts/at91sam9g35ek.dts | 41 - arch/arm/boot/dts/at91sam9g45.dtsi | 1023 --- arch/arm/boot/dts/at91sam9m10g45ek.dts | 393 -- arch/arm/boot/dts/at91sam9n12.dtsi | 799 --- arch/arm/boot/dts/at91sam9n12ek.dts | 285 - arch/arm/boot/dts/at91sam9rl.dtsi | 861 --- arch/arm/boot/dts/at91sam9rlek.dts | 276 - arch/arm/boot/dts/at91sam9x25.dtsi | 35 - arch/arm/boot/dts/at91sam9x25ek.dts | 35 - arch/arm/boot/dts/at91sam9x35.dtsi | 34 - arch/arm/boot/dts/at91sam9x35ek.dts | 41 - arch/arm/boot/dts/at91sam9x5.dtsi | 978 --- arch/arm/boot/dts/at91sam9x5_can.dtsi | 56 - arch/arm/boot/dts/at91sam9x5_isi.dtsi | 62 - arch/arm/boot/dts/at91sam9x5_lcd.dtsi | 147 - arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 57 - arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 45 - arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 61 - arch/arm/boot/dts/at91sam9x5cm.dtsi | 144 - arch/arm/boot/dts/at91sam9x5dm.dtsi | 96 - arch/arm/boot/dts/at91sam9x5ek.dtsi | 167 - arch/arm/boot/dts/at91sam9xe.dtsi | 26 - arch/arm/boot/dts/axis/Makefile | 5 + arch/arm/boot/dts/axis/artpec6-devboard.dts | 64 + arch/arm/boot/dts/axis/artpec6.dtsi | 388 ++ arch/arm/boot/dts/axm5516-amarillo.dts | 47 - arch/arm/boot/dts/axm5516-cpus.dtsi | 200 - arch/arm/boot/dts/axm55xx.dtsi | 200 - arch/arm/boot/dts/axp152.dtsi | 49 - arch/arm/boot/dts/axp209.dtsi | 126 - arch/arm/boot/dts/axp223.dtsi | 58 - arch/arm/boot/dts/axp22x.dtsi | 176 - arch/arm/boot/dts/axp809.dtsi | 60 - arch/arm/boot/dts/axp81x.dtsi | 164 - arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 133 - arch/arm/boot/dts/bcm-cygnus.dtsi | 623 -- arch/arm/boot/dts/bcm-hr2.dtsi | 368 -- arch/arm/boot/dts/bcm-ns.dtsi | 464 -- arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 - arch/arm/boot/dts/bcm-nsp.dtsi | 695 -- arch/arm/boot/dts/bcm11351.dtsi | 413 -- arch/arm/boot/dts/bcm21664-garnet.dts | 47 - arch/arm/boot/dts/bcm21664.dtsi | 346 - arch/arm/boot/dts/bcm23550-sparrow.dts | 81 - arch/arm/boot/dts/bcm23550.dtsi | 414 -- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 243 - arch/arm/boot/dts/bcm2711-rpi-400.dts | 45 - arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts | 139 - arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi | 113 - arch/arm/boot/dts/bcm2711-rpi.dtsi | 78 - arch/arm/boot/dts/bcm2711.dtsi | 1172 ---- arch/arm/boot/dts/bcm28155-ap.dts | 112 - arch/arm/boot/dts/bcm2835-common.dtsi | 208 - arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 129 - arch/arm/boot/dts/bcm2835-rpi-a.dts | 122 - arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 131 - arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 122 - arch/arm/boot/dts/bcm2835-rpi-b.dts | 116 - arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts | 96 - arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi | 45 - arch/arm/boot/dts/bcm2835-rpi-common.dtsi | 29 - arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 137 - arch/arm/boot/dts/bcm2835-rpi-zero.dts | 118 - arch/arm/boot/dts/bcm2835-rpi.dtsi | 71 - arch/arm/boot/dts/bcm2835.dtsi | 54 - arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 130 - arch/arm/boot/dts/bcm2836-rpi.dtsi | 7 - arch/arm/boot/dts/bcm2836.dtsi | 142 - arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 158 - arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 163 - arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 154 - arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts | 95 - arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 53 - arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts | 135 - arch/arm/boot/dts/bcm2837.dtsi | 144 - arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi | 41 - arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi | 18 - arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi | 20 - arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi | 19 - arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi | 3 - arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi | 11 - arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi | 7 - arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi | 34 - arch/arm/boot/dts/bcm283x.dtsi | 501 -- arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 94 - arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 85 - .../dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi | 185 - arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts | 26 - arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts | 26 - arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 151 - arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts | 48 - arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts | 44 - arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 89 - arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 92 - arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 126 - arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 88 - arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 153 - arch/arm/boot/dts/bcm4708.dtsi | 48 - arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 79 - arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 149 - arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 109 - arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 85 - arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 152 - arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 113 - arch/arm/boot/dts/bcm47081.dtsi | 37 - arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 98 - arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 132 - arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 49 - arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 106 - arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 234 - arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 122 - arch/arm/boot/dts/bcm4709.dtsi | 15 - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 271 - arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 150 - arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts | 199 - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 302 - arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 111 - arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 87 - arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 111 - arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 79 - arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 151 - arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 126 - arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 96 - arch/arm/boot/dts/bcm47094-phicomm-k3.dts | 70 - arch/arm/boot/dts/bcm47094.dtsi | 31 - arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 48 - arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 85 - arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 144 - arch/arm/boot/dts/bcm47622.dtsi | 150 - arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 159 - arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts | 131 - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 217 - arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi | 14 - arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi | 12 - arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi | 17 - arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 21 - arch/arm/boot/dts/bcm5301x.dtsi | 170 - arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts | 86 - arch/arm/boot/dts/bcm53573.dtsi | 219 - arch/arm/boot/dts/bcm59056.dtsi | 91 - arch/arm/boot/dts/bcm63138.dtsi | 247 - arch/arm/boot/dts/bcm63148.dtsi | 123 - arch/arm/boot/dts/bcm63178.dtsi | 141 - arch/arm/boot/dts/bcm6756.dtsi | 151 - arch/arm/boot/dts/bcm6846.dtsi | 123 - arch/arm/boot/dts/bcm6855.dtsi | 141 - arch/arm/boot/dts/bcm6878.dtsi | 132 - arch/arm/boot/dts/bcm7445-bcm97445svmb.dts | 38 - arch/arm/boot/dts/bcm7445.dtsi | 315 - arch/arm/boot/dts/bcm911360_entphn.dts | 99 - arch/arm/boot/dts/bcm911360k.dts | 52 - arch/arm/boot/dts/bcm94708.dts | 49 - arch/arm/boot/dts/bcm94709.dts | 49 - arch/arm/boot/dts/bcm947189acdbmr.dts | 96 - arch/arm/boot/dts/bcm947622.dts | 34 - arch/arm/boot/dts/bcm953012er.dts | 92 - arch/arm/boot/dts/bcm953012hr.dts | 102 - arch/arm/boot/dts/bcm953012k.dts | 120 - arch/arm/boot/dts/bcm958300k.dts | 77 - arch/arm/boot/dts/bcm958305k.dts | 85 - arch/arm/boot/dts/bcm958522er.dts | 185 - arch/arm/boot/dts/bcm958525er.dts | 197 - arch/arm/boot/dts/bcm958525xmc.dts | 217 - arch/arm/boot/dts/bcm958622hr.dts | 227 - arch/arm/boot/dts/bcm958623hr.dts | 231 - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 284 - arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi | 162 - arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 - arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 - arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 - arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 - arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 - arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 - .../arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 137 - arch/arm/boot/dts/bcm958625hr.dts | 254 - arch/arm/boot/dts/bcm958625k.dts | 271 - arch/arm/boot/dts/bcm963138.dts | 31 - arch/arm/boot/dts/bcm963138dvt.dts | 56 - arch/arm/boot/dts/bcm963148.dts | 34 - arch/arm/boot/dts/bcm963178.dts | 34 - arch/arm/boot/dts/bcm96756.dts | 34 - arch/arm/boot/dts/bcm96846.dts | 34 - arch/arm/boot/dts/bcm96855.dts | 34 - arch/arm/boot/dts/bcm96878.dts | 34 - arch/arm/boot/dts/bcm988312hr.dts | 231 - arch/arm/boot/dts/bcm9hmidc.dtsi | 42 - arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 43 - arch/arm/boot/dts/berlin2.dtsi | 540 -- arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 77 - arch/arm/boot/dts/berlin2cd-valve-steamlink.dts | 79 - arch/arm/boot/dts/berlin2cd.dtsi | 583 -- arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 144 - arch/arm/boot/dts/berlin2q.dtsi | 666 -- arch/arm/boot/dts/broadcom/Makefile | 125 + arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi | 133 + arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi | 623 ++ arch/arm/boot/dts/broadcom/bcm-hr2.dtsi | 368 ++ arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 464 ++ arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi | 70 + arch/arm/boot/dts/broadcom/bcm-nsp.dtsi | 695 ++ arch/arm/boot/dts/broadcom/bcm11351.dtsi | 413 ++ arch/arm/boot/dts/broadcom/bcm21664-garnet.dts | 47 + arch/arm/boot/dts/broadcom/bcm21664.dtsi | 346 + arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts | 81 + arch/arm/boot/dts/broadcom/bcm23550.dtsi | 414 ++ arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 243 + arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts | 45 + arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 139 + arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi | 113 + arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 78 + arch/arm/boot/dts/broadcom/bcm2711.dtsi | 1172 ++++ arch/arm/boot/dts/broadcom/bcm28155-ap.dts | 112 + arch/arm/boot/dts/broadcom/bcm2835-common.dtsi | 208 + arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts | 129 + arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts | 122 + arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts | 131 + arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts | 122 + arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts | 116 + arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts | 96 + arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi | 45 + arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi | 29 + arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts | 137 + arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts | 118 + arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 71 + arch/arm/boot/dts/broadcom/bcm2835.dtsi | 54 + arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts | 130 + arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi | 7 + arch/arm/boot/dts/broadcom/bcm2836.dtsi | 142 + .../arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts | 158 + .../arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts | 163 + arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 154 + arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts | 95 + arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi | 53 + .../arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts | 135 + arch/arm/boot/dts/broadcom/bcm2837.dtsi | 144 + .../arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi | 41 + .../dts/broadcom/bcm283x-rpi-led-deprecated.dtsi | 18 + .../boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi | 20 + .../boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi | 19 + .../boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi | 3 + .../arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi | 11 + .../dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi | 7 + .../arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi | 34 + arch/arm/boot/dts/broadcom/bcm283x.dtsi | 501 ++ .../boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts | 94 + .../boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts | 85 + .../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 185 + .../dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts | 26 + .../dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts | 26 + .../dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts | 151 + .../dts/broadcom/bcm4708-linksys-ea6300-v1.dts | 48 + .../dts/broadcom/bcm4708-linksys-ea6500-v2.dts | 44 + .../boot/dts/broadcom/bcm4708-luxul-xap-1510.dts | 89 + .../boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts | 92 + .../boot/dts/broadcom/bcm4708-netgear-r6250.dts | 126 + .../boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts | 88 + .../boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts | 153 + arch/arm/boot/dts/broadcom/bcm4708.dtsi | 48 + .../boot/dts/broadcom/bcm47081-asus-rt-n18u.dts | 79 + .../dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts | 149 + .../dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts | 109 + .../boot/dts/broadcom/bcm47081-luxul-xap-1410.dts | 85 + .../boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts | 152 + .../dts/broadcom/bcm47081-tplink-archer-c5-v2.dts | 113 + arch/arm/boot/dts/broadcom/bcm47081.dtsi | 37 + .../boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts | 98 + .../dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts | 132 + .../boot/dts/broadcom/bcm4709-linksys-ea9200.dts | 49 + .../boot/dts/broadcom/bcm4709-netgear-r7000.dts | 106 + .../boot/dts/broadcom/bcm4709-netgear-r8000.dts | 234 + .../dts/broadcom/bcm4709-tplink-archer-c9-v1.dts | 122 + arch/arm/boot/dts/broadcom/bcm4709.dtsi | 15 + .../boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts | 271 + .../boot/dts/broadcom/bcm47094-dlink-dir-885l.dts | 150 + .../boot/dts/broadcom/bcm47094-dlink-dir-890l.dts | 199 + .../dts/broadcom/bcm47094-linksys-panamera.dts | 302 + .../boot/dts/broadcom/bcm47094-luxul-abr-4500.dts | 111 + .../boot/dts/broadcom/bcm47094-luxul-xap-1610.dts | 87 + .../boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts | 111 + .../boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts | 79 + .../boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts | 151 + .../dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts | 126 + .../boot/dts/broadcom/bcm47094-netgear-r8500.dts | 96 + arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts | 70 + arch/arm/boot/dts/broadcom/bcm47094.dtsi | 31 + .../boot/dts/broadcom/bcm47189-luxul-xap-1440.dts | 48 + .../boot/dts/broadcom/bcm47189-luxul-xap-810.dts | 85 + arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts | 144 + arch/arm/boot/dts/broadcom/bcm47622.dtsi | 150 + .../arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts | 159 + .../dts/broadcom/bcm53016-dlink-dwl-8610ap.dts | 131 + .../arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts | 217 + .../boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi | 14 + .../boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi | 12 + .../boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi | 17 + arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi | 21 + arch/arm/boot/dts/broadcom/bcm5301x.dtsi | 170 + .../dts/broadcom/bcm53340-ubnt-unifi-switch8.dts | 86 + arch/arm/boot/dts/broadcom/bcm53573.dtsi | 219 + arch/arm/boot/dts/broadcom/bcm59056.dtsi | 91 + arch/arm/boot/dts/broadcom/bcm63138.dtsi | 247 + arch/arm/boot/dts/broadcom/bcm63148.dtsi | 123 + arch/arm/boot/dts/broadcom/bcm63178.dtsi | 141 + arch/arm/boot/dts/broadcom/bcm6756.dtsi | 151 + arch/arm/boot/dts/broadcom/bcm6846.dtsi | 123 + arch/arm/boot/dts/broadcom/bcm6855.dtsi | 141 + arch/arm/boot/dts/broadcom/bcm6878.dtsi | 132 + .../arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts | 38 + arch/arm/boot/dts/broadcom/bcm7445.dtsi | 315 + arch/arm/boot/dts/broadcom/bcm911360_entphn.dts | 99 + arch/arm/boot/dts/broadcom/bcm911360k.dts | 52 + arch/arm/boot/dts/broadcom/bcm94708.dts | 49 + arch/arm/boot/dts/broadcom/bcm94709.dts | 49 + arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts | 96 + arch/arm/boot/dts/broadcom/bcm947622.dts | 34 + arch/arm/boot/dts/broadcom/bcm953012er.dts | 92 + arch/arm/boot/dts/broadcom/bcm953012hr.dts | 102 + arch/arm/boot/dts/broadcom/bcm953012k.dts | 120 + arch/arm/boot/dts/broadcom/bcm958300k.dts | 77 + arch/arm/boot/dts/broadcom/bcm958305k.dts | 85 + arch/arm/boot/dts/broadcom/bcm958522er.dts | 185 + arch/arm/boot/dts/broadcom/bcm958525er.dts | 197 + arch/arm/boot/dts/broadcom/bcm958525xmc.dts | 217 + arch/arm/boot/dts/broadcom/bcm958622hr.dts | 227 + arch/arm/boot/dts/broadcom/bcm958623hr.dts | 231 + .../boot/dts/broadcom/bcm958625-meraki-alamo.dtsi | 284 + .../dts/broadcom/bcm958625-meraki-kingpin.dtsi | 162 + .../boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts | 25 + .../boot/dts/broadcom/bcm958625-meraki-mx64.dts | 24 + .../dts/broadcom/bcm958625-meraki-mx64w-a0.dts | 33 + .../boot/dts/broadcom/bcm958625-meraki-mx64w.dts | 32 + .../boot/dts/broadcom/bcm958625-meraki-mx65.dts | 24 + .../boot/dts/broadcom/bcm958625-meraki-mx65w.dts | 32 + .../dts/broadcom/bcm958625-meraki-mx6x-common.dtsi | 137 + arch/arm/boot/dts/broadcom/bcm958625hr.dts | 254 + arch/arm/boot/dts/broadcom/bcm958625k.dts | 271 + arch/arm/boot/dts/broadcom/bcm963138.dts | 31 + arch/arm/boot/dts/broadcom/bcm963138dvt.dts | 56 + arch/arm/boot/dts/broadcom/bcm963148.dts | 34 + arch/arm/boot/dts/broadcom/bcm963178.dts | 34 + arch/arm/boot/dts/broadcom/bcm96756.dts | 34 + arch/arm/boot/dts/broadcom/bcm96846.dts | 34 + arch/arm/boot/dts/broadcom/bcm96855.dts | 34 + arch/arm/boot/dts/broadcom/bcm96878.dts | 34 + arch/arm/boot/dts/broadcom/bcm988312hr.dts | 231 + arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi | 42 + arch/arm/boot/dts/calxeda/Makefile | 7 + arch/arm/boot/dts/calxeda/ecx-2000.dts | 101 + arch/arm/boot/dts/calxeda/ecx-common.dtsi | 231 + arch/arm/boot/dts/calxeda/highbank.dts | 158 + arch/arm/boot/dts/cirrus/Makefile | 5 + arch/arm/boot/dts/cirrus/ep7209.dtsi | 201 + arch/arm/boot/dts/cirrus/ep7211-edb7211.dts | 97 + arch/arm/boot/dts/cirrus/ep7211.dtsi | 8 + arch/arm/boot/dts/cnxt/Makefile | 5 + arch/arm/boot/dts/cnxt/cx92755.dtsi | 144 + arch/arm/boot/dts/cnxt/cx92755_equinox.dts | 86 + arch/arm/boot/dts/compulab-sb-som.dtsi | 46 - arch/arm/boot/dts/cx92755.dtsi | 144 - arch/arm/boot/dts/cx92755_equinox.dts | 86 - arch/arm/boot/dts/da850-enbw-cmc.dts | 44 - arch/arm/boot/dts/da850-evm.dts | 466 -- arch/arm/boot/dts/da850-lcdk.dts | 425 -- arch/arm/boot/dts/da850-lego-ev3.dts | 466 -- arch/arm/boot/dts/da850.dtsi | 964 --- arch/arm/boot/dts/dm3725.dtsi | 10 - arch/arm/boot/dts/dm8148-evm.dts | 155 - arch/arm/boot/dts/dm8148-t410.dts | 113 - arch/arm/boot/dts/dm814x-clocks.dtsi | 379 -- arch/arm/boot/dts/dm814x.dtsi | 788 --- arch/arm/boot/dts/dm8168-evm.dts | 213 - arch/arm/boot/dts/dm816x-clocks.dtsi | 276 - arch/arm/boot/dts/dm816x.dtsi | 691 -- arch/arm/boot/dts/dove-cm-a510.dtsi | 203 - arch/arm/boot/dts/dove-cubox-es.dts | 13 - arch/arm/boot/dts/dove-cubox.dts | 150 - arch/arm/boot/dts/dove-d2plug.dts | 70 - arch/arm/boot/dts/dove-d3plug.dts | 104 - arch/arm/boot/dts/dove-dove-db.dts | 39 - arch/arm/boot/dts/dove-sbc-a510.dts | 183 - arch/arm/boot/dts/dove.dtsi | 820 --- arch/arm/boot/dts/dra62x-clocks.dtsi | 45 - arch/arm/boot/dts/dra62x-j5eco-evm.dts | 144 - arch/arm/boot/dts/dra62x.dtsi | 19 - arch/arm/boot/dts/dra7-dspeve-thermal.dtsi | 24 - arch/arm/boot/dts/dra7-evm-common.dtsi | 265 - arch/arm/boot/dts/dra7-evm.dts | 592 -- arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi | 39 - arch/arm/boot/dts/dra7-iva-thermal.dtsi | 24 - arch/arm/boot/dts/dra7-l4.dtsi | 4606 -------------- arch/arm/boot/dts/dra7-mmc-iodelay.dtsi | 19 - arch/arm/boot/dts/dra7.dtsi | 1358 ---- arch/arm/boot/dts/dra71-evm.dts | 316 - arch/arm/boot/dts/dra71x.dtsi | 13 - arch/arm/boot/dts/dra72-evm-common.dtsi | 593 -- arch/arm/boot/dts/dra72-evm-revc.dts | 157 - arch/arm/boot/dts/dra72-evm-tps65917.dtsi | 151 - arch/arm/boot/dts/dra72-evm.dts | 127 - arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi | 353 -- arch/arm/boot/dts/dra72x.dtsi | 110 - arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi | 18 - arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi | 639 -- arch/arm/boot/dts/dra74x-p.dtsi | 27 - arch/arm/boot/dts/dra74x.dtsi | 232 - arch/arm/boot/dts/dra76-evm.dts | 567 -- arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 285 - arch/arm/boot/dts/dra76x.dtsi | 159 - arch/arm/boot/dts/dra7xx-clocks.dtsi | 2094 ------ arch/arm/boot/dts/e60k02.dtsi | 320 - arch/arm/boot/dts/e70k02.dtsi | 330 - arch/arm/boot/dts/ecx-2000.dts | 101 - arch/arm/boot/dts/ecx-common.dtsi | 231 - arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 68 - arch/arm/boot/dts/emev2-kzm9d.dts | 115 - arch/arm/boot/dts/emev2.dtsi | 289 - arch/arm/boot/dts/en7523-evb.dts | 43 - arch/arm/boot/dts/en7523.dtsi | 206 - arch/arm/boot/dts/ep7209.dtsi | 201 - arch/arm/boot/dts/ep7211-edb7211.dts | 97 - arch/arm/boot/dts/ep7211.dtsi | 8 - arch/arm/boot/dts/ethernut5.dts | 118 - arch/arm/boot/dts/evk-pro3.dts | 58 - arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi | 32 - arch/arm/boot/dts/exynos-pinctrl.h | 55 - arch/arm/boot/dts/exynos-syscon-restart.dtsi | 20 - arch/arm/boot/dts/exynos3250-artik5-eval.dts | 69 - arch/arm/boot/dts/exynos3250-artik5.dtsi | 432 -- arch/arm/boot/dts/exynos3250-monk.dts | 644 -- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 543 -- arch/arm/boot/dts/exynos3250-rinato.dts | 921 --- arch/arm/boot/dts/exynos3250.dtsi | 950 --- arch/arm/boot/dts/exynos4-cpu-thermal.dtsi | 48 - arch/arm/boot/dts/exynos4.dtsi | 1007 --- arch/arm/boot/dts/exynos4210-i9100.dts | 860 --- arch/arm/boot/dts/exynos4210-origen.dts | 372 -- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 863 --- arch/arm/boot/dts/exynos4210-smdkv310.dts | 229 - arch/arm/boot/dts/exynos4210-trats.dts | 567 -- arch/arm/boot/dts/exynos4210-universal_c210.dts | 689 -- arch/arm/boot/dts/exynos4210.dtsi | 531 -- arch/arm/boot/dts/exynos4212.dtsi | 157 - arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 216 - arch/arm/boot/dts/exynos4412-i9300.dts | 27 - arch/arm/boot/dts/exynos4412-i9305.dts | 21 - arch/arm/boot/dts/exynos4412-itop-elite.dts | 234 - arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 509 -- arch/arm/boot/dts/exynos4412-midas.dtsi | 1459 ----- arch/arm/boot/dts/exynos4412-n710x.dts | 116 - arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 574 -- arch/arm/boot/dts/exynos4412-odroidu3.dts | 155 - arch/arm/boot/dts/exynos4412-odroidx.dts | 143 - arch/arm/boot/dts/exynos4412-odroidx2.dts | 22 - arch/arm/boot/dts/exynos4412-origen.dts | 558 -- arch/arm/boot/dts/exynos4412-p4note-n8010.dts | 18 - arch/arm/boot/dts/exynos4412-p4note.dtsi | 1229 ---- arch/arm/boot/dts/exynos4412-ppmu-common.dtsi | 47 - arch/arm/boot/dts/exynos4412-prime.dtsi | 47 - arch/arm/boot/dts/exynos4412-smdk4412.dts | 182 - arch/arm/boot/dts/exynos4412-tiny4412.dts | 160 - arch/arm/boot/dts/exynos4412-trats2.dts | 29 - arch/arm/boot/dts/exynos4412.dtsi | 183 - arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 979 --- arch/arm/boot/dts/exynos4x12.dtsi | 664 -- arch/arm/boot/dts/exynos5.dtsi | 230 - arch/arm/boot/dts/exynos5250-arndale.dts | 643 -- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 833 --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 430 -- arch/arm/boot/dts/exynos5250-snow-common.dtsi | 718 --- arch/arm/boot/dts/exynos5250-snow-rev5.dts | 56 - arch/arm/boot/dts/exynos5250-snow.dts | 52 - arch/arm/boot/dts/exynos5250-spring.dts | 567 -- arch/arm/boot/dts/exynos5250.dtsi | 1225 ---- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 585 -- arch/arm/boot/dts/exynos5260-xyref5260.dts | 117 - arch/arm/boot/dts/exynos5260.dtsi | 554 -- arch/arm/boot/dts/exynos5410-odroidxu.dts | 664 -- arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 652 -- arch/arm/boot/dts/exynos5410-smdk5410.dts | 152 - arch/arm/boot/dts/exynos5410.dtsi | 440 -- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 843 --- arch/arm/boot/dts/exynos5420-chagall-wifi.dts | 75 - arch/arm/boot/dts/exynos5420-cpus.dtsi | 163 - .../arm/boot/dts/exynos5420-galaxy-tab-common.dtsi | 696 -- arch/arm/boot/dts/exynos5420-klimt-wifi.dts | 75 - arch/arm/boot/dts/exynos5420-peach-pit.dts | 1126 ---- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 734 --- arch/arm/boot/dts/exynos5420-smdk5420.dts | 435 -- arch/arm/boot/dts/exynos5420-trip-points.dtsi | 31 - arch/arm/boot/dts/exynos5420.dtsi | 1397 ---- arch/arm/boot/dts/exynos5422-cpus.dtsi | 170 - arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1072 ---- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 266 - arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 83 - arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 510 -- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 127 - arch/arm/boot/dts/exynos5422-odroidxu3.dts | 94 - arch/arm/boot/dts/exynos5422-odroidxu4.dts | 94 - arch/arm/boot/dts/exynos5422-samsung-k3g.dts | 679 -- arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 54 - arch/arm/boot/dts/exynos54xx.dtsi | 210 - arch/arm/boot/dts/exynos5800-peach-pi.dts | 1108 ---- arch/arm/boot/dts/exynos5800.dtsi | 166 - .../boot/dts/facebook-bmc-flash-layout-128.dtsi | 60 - arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi | 42 - arch/arm/boot/dts/ge863-pro3.dtsi | 77 - arch/arm/boot/dts/gemini-dlink-dir-685.dts | 492 -- arch/arm/boot/dts/gemini-dlink-dns-313.dts | 323 - arch/arm/boot/dts/gemini-nas4220b.dts | 189 - arch/arm/boot/dts/gemini-ns2502.dts | 123 - arch/arm/boot/dts/gemini-rut1xx.dts | 136 - arch/arm/boot/dts/gemini-sl93512r.dts | 294 - arch/arm/boot/dts/gemini-sq201.dts | 286 - arch/arm/boot/dts/gemini-ssi1328.dts | 134 - arch/arm/boot/dts/gemini-wbd111.dts | 142 - arch/arm/boot/dts/gemini-wbd222.dts | 154 - arch/arm/boot/dts/gemini.dtsi | 475 -- arch/arm/boot/dts/gemini/Makefile | 12 + arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 492 ++ arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts | 323 + arch/arm/boot/dts/gemini/gemini-nas4220b.dts | 189 + arch/arm/boot/dts/gemini/gemini-ns2502.dts | 123 + arch/arm/boot/dts/gemini/gemini-rut1xx.dts | 136 + arch/arm/boot/dts/gemini/gemini-sl93512r.dts | 294 + arch/arm/boot/dts/gemini/gemini-sq201.dts | 286 + arch/arm/boot/dts/gemini/gemini-ssi1328.dts | 134 + arch/arm/boot/dts/gemini/gemini-wbd111.dts | 142 + arch/arm/boot/dts/gemini/gemini-wbd222.dts | 154 + arch/arm/boot/dts/gemini/gemini.dtsi | 475 ++ arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi | 75 - arch/arm/boot/dts/hi3519-demb.dts | 29 - arch/arm/boot/dts/hi3519.dtsi | 174 - arch/arm/boot/dts/hi3620-hi4511.dts | 647 -- arch/arm/boot/dts/hi3620.dtsi | 575 -- arch/arm/boot/dts/highbank.dts | 158 - arch/arm/boot/dts/hip01-ca9x2.dts | 48 - arch/arm/boot/dts/hip01.dtsi | 105 - arch/arm/boot/dts/hip04-d01.dts | 29 - arch/arm/boot/dts/hip04.dtsi | 986 --- arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 83 - arch/arm/boot/dts/hisi-x5hd2.dtsi | 558 -- arch/arm/boot/dts/hisilicon/Makefile | 13 + arch/arm/boot/dts/hisilicon/hi3519-demb.dts | 29 + arch/arm/boot/dts/hisilicon/hi3519.dtsi | 174 + arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts | 647 ++ arch/arm/boot/dts/hisilicon/hi3620.dtsi | 575 ++ arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts | 48 + arch/arm/boot/dts/hisilicon/hip01.dtsi | 105 + arch/arm/boot/dts/hisilicon/hip04-d01.dts | 29 + arch/arm/boot/dts/hisilicon/hip04.dtsi | 986 +++ arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts | 83 + arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi | 558 ++ arch/arm/boot/dts/hisilicon/sd5203.dts | 96 + arch/arm/boot/dts/hpe-bmc-dl360gen10.dts | 26 - arch/arm/boot/dts/hpe-gxp.dtsi | 127 - arch/arm/boot/dts/hpe/Makefile | 3 + arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts | 26 + arch/arm/boot/dts/hpe/hpe-gxp.dtsi | 127 + arch/arm/boot/dts/ibm-power9-dual.dtsi | 248 - arch/arm/boot/dts/imx1-ads.dts | 135 - arch/arm/boot/dts/imx1-apf9328.dts | 124 - arch/arm/boot/dts/imx1-pinfunc.h | 296 - arch/arm/boot/dts/imx1.dtsi | 276 - arch/arm/boot/dts/imx23-evk.dts | 144 - arch/arm/boot/dts/imx23-olinuxino.dts | 131 - arch/arm/boot/dts/imx23-pinfunc.h | 327 - arch/arm/boot/dts/imx23-sansa.dts | 207 - arch/arm/boot/dts/imx23-stmp378x_devb.dts | 76 - arch/arm/boot/dts/imx23-xfi3.dts | 180 - arch/arm/boot/dts/imx23.dtsi | 634 -- arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 66 - .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 65 - .../imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 37 - .../imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 37 - .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 174 - arch/arm/boot/dts/imx25-karo-tx25.dts | 108 - arch/arm/boot/dts/imx25-pdk.dts | 313 - arch/arm/boot/dts/imx25-pinfunc.h | 652 -- arch/arm/boot/dts/imx25.dtsi | 637 -- arch/arm/boot/dts/imx27-apf27.dts | 112 - arch/arm/boot/dts/imx27-apf27dev.dts | 256 - arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi | 284 - .../boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts | 266 - arch/arm/boot/dts/imx27-pdk.dts | 191 - arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 162 - arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | 97 - arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 319 - arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 344 - arch/arm/boot/dts/imx27-pinfunc.h | 474 -- arch/arm/boot/dts/imx27.dtsi | 593 -- arch/arm/boot/dts/imx28-apf28.dts | 72 - arch/arm/boot/dts/imx28-apf28dev.dts | 217 - arch/arm/boot/dts/imx28-apx4devkit.dts | 232 - arch/arm/boot/dts/imx28-cfa10036.dts | 131 - arch/arm/boot/dts/imx28-cfa10037.dts | 83 - arch/arm/boot/dts/imx28-cfa10049.dts | 418 -- arch/arm/boot/dts/imx28-cfa10055.dts | 155 - arch/arm/boot/dts/imx28-cfa10056.dts | 109 - arch/arm/boot/dts/imx28-cfa10057.dts | 161 - arch/arm/boot/dts/imx28-cfa10058.dts | 128 - arch/arm/boot/dts/imx28-duckbill-2-485.dts | 38 - arch/arm/boot/dts/imx28-duckbill-2-enocean.dts | 69 - arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 63 - arch/arm/boot/dts/imx28-duckbill-2.dts | 170 - arch/arm/boot/dts/imx28-duckbill.dts | 139 - arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts | 64 - arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 43 - arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi | 323 - arch/arm/boot/dts/imx28-evk.dts | 352 - arch/arm/boot/dts/imx28-lwe.dtsi | 170 - arch/arm/boot/dts/imx28-m28.dtsi | 50 - arch/arm/boot/dts/imx28-m28cu3.dts | 258 - arch/arm/boot/dts/imx28-m28evk.dts | 263 - arch/arm/boot/dts/imx28-pinfunc.h | 500 -- arch/arm/boot/dts/imx28-sps1.dts | 157 - arch/arm/boot/dts/imx28-ts4600.dts | 66 - arch/arm/boot/dts/imx28-tx28.dts | 677 -- arch/arm/boot/dts/imx28-xea.dts | 99 - arch/arm/boot/dts/imx28.dtsi | 1334 ---- arch/arm/boot/dts/imx31-bug.dts | 22 - arch/arm/boot/dts/imx31-lite.dts | 178 - arch/arm/boot/dts/imx31.dtsi | 371 -- arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | 89 - .../boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 156 - arch/arm/boot/dts/imx35-pdk.dts | 62 - arch/arm/boot/dts/imx35-pinfunc.h | 966 --- arch/arm/boot/dts/imx35.dtsi | 413 -- arch/arm/boot/dts/imx50-evk.dts | 104 - arch/arm/boot/dts/imx50-kobo-aura.dts | 287 - arch/arm/boot/dts/imx50-pinfunc.h | 919 --- arch/arm/boot/dts/imx50.dtsi | 499 -- arch/arm/boot/dts/imx51-apf51.dts | 84 - arch/arm/boot/dts/imx51-apf51dev.dts | 217 - arch/arm/boot/dts/imx51-babbage.dts | 726 --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 126 - arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 376 -- arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 92 - .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 274 - arch/arm/boot/dts/imx51-pinfunc.h | 768 --- arch/arm/boot/dts/imx51-ts4800.dts | 331 - arch/arm/boot/dts/imx51-zii-rdu1.dts | 894 --- arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 457 -- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 471 -- arch/arm/boot/dts/imx51.dtsi | 663 -- arch/arm/boot/dts/imx53-ard.dts | 179 - arch/arm/boot/dts/imx53-cx9020.dts | 295 - arch/arm/boot/dts/imx53-kp-ddc.dts | 146 - arch/arm/boot/dts/imx53-kp-hsc.dts | 52 - arch/arm/boot/dts/imx53-kp.dtsi | 197 - arch/arm/boot/dts/imx53-m53.dtsi | 132 - arch/arm/boot/dts/imx53-m53evk.dts | 371 -- arch/arm/boot/dts/imx53-m53menlo.dts | 517 -- arch/arm/boot/dts/imx53-mba53.dts | 249 - arch/arm/boot/dts/imx53-pinfunc.h | 1189 ---- arch/arm/boot/dts/imx53-ppd.dts | 1122 ---- arch/arm/boot/dts/imx53-qsb-common.dtsi | 387 -- arch/arm/boot/dts/imx53-qsb.dts | 111 - arch/arm/boot/dts/imx53-qsrb.dts | 149 - arch/arm/boot/dts/imx53-sk-imx53.dts | 357 -- arch/arm/boot/dts/imx53-smd.dts | 346 - arch/arm/boot/dts/imx53-tqma53.dtsi | 289 - arch/arm/boot/dts/imx53-tx53-x03x.dts | 351 - arch/arm/boot/dts/imx53-tx53-x13x.dts | 262 - arch/arm/boot/dts/imx53-tx53.dtsi | 584 -- arch/arm/boot/dts/imx53-usbarmory.dts | 225 - arch/arm/boot/dts/imx53-voipac-bsb.dts | 153 - arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 267 - arch/arm/boot/dts/imx53.dtsi | 859 --- arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi | 561 -- arch/arm/boot/dts/imx6-logicpd-som.dtsi | 369 -- arch/arm/boot/dts/imx6dl-alti6p.dts | 578 -- arch/arm/boot/dts/imx6dl-apf6dev.dts | 18 - arch/arm/boot/dts/imx6dl-aristainetos2_4.dts | 158 - arch/arm/boot/dts/imx6dl-aristainetos2_7.dts | 98 - arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 84 - arch/arm/boot/dts/imx6dl-aristainetos_7.dts | 74 - arch/arm/boot/dts/imx6dl-b105pv2.dts | 32 - arch/arm/boot/dts/imx6dl-b105v2.dts | 32 - arch/arm/boot/dts/imx6dl-b125pv2.dts | 30 - arch/arm/boot/dts/imx6dl-b125v2.dts | 30 - arch/arm/boot/dts/imx6dl-b155v2.dts | 32 - arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi | 413 -- arch/arm/boot/dts/imx6dl-b1x5v2.dtsi | 57 - arch/arm/boot/dts/imx6dl-colibri-aster.dts | 114 - arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 158 - arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts | 46 - arch/arm/boot/dts/imx6dl-colibri-iris.dts | 153 - arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts | 52 - arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts | 51 - arch/arm/boot/dts/imx6dl-cubox-i.dts | 51 - arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts | 23 - arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts | 20 - arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 388 -- arch/arm/boot/dts/imx6dl-emcon-avari.dts | 14 - arch/arm/boot/dts/imx6dl-gw51xx.dts | 13 - arch/arm/boot/dts/imx6dl-gw52xx.dts | 71 - arch/arm/boot/dts/imx6dl-gw53xx.dts | 71 - arch/arm/boot/dts/imx6dl-gw54xx.dts | 71 - arch/arm/boot/dts/imx6dl-gw551x.dts | 55 - arch/arm/boot/dts/imx6dl-gw552x.dts | 14 - arch/arm/boot/dts/imx6dl-gw553x.dts | 55 - arch/arm/boot/dts/imx6dl-gw560x.dts | 55 - arch/arm/boot/dts/imx6dl-gw5903.dts | 55 - arch/arm/boot/dts/imx6dl-gw5904.dts | 55 - arch/arm/boot/dts/imx6dl-gw5907.dts | 14 - arch/arm/boot/dts/imx6dl-gw5910.dts | 14 - arch/arm/boot/dts/imx6dl-gw5912.dts | 13 - arch/arm/boot/dts/imx6dl-gw5913.dts | 14 - .../boot/dts/imx6dl-hummingboard-emmc-som-v15.dts | 53 - arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts | 52 - arch/arm/boot/dts/imx6dl-hummingboard.dts | 52 - .../boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts | 55 - arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts | 54 - arch/arm/boot/dts/imx6dl-hummingboard2.dts | 53 - arch/arm/boot/dts/imx6dl-icore-mipi.dts | 25 - arch/arm/boot/dts/imx6dl-icore-rqs.dts | 15 - arch/arm/boot/dts/imx6dl-icore.dts | 32 - arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi | 12 - arch/arm/boot/dts/imx6dl-lanmcu.dts | 483 -- arch/arm/boot/dts/imx6dl-mamoj.dts | 496 -- arch/arm/boot/dts/imx6dl-mba6.dtsi | 22 - arch/arm/boot/dts/imx6dl-mba6a.dts | 21 - arch/arm/boot/dts/imx6dl-mba6b.dts | 21 - arch/arm/boot/dts/imx6dl-nit6xlite.dts | 13 - arch/arm/boot/dts/imx6dl-nitrogen6x.dts | 15 - arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 67 - arch/arm/boot/dts/imx6dl-phytec-pbab01.dts | 13 - arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi | 17 - arch/arm/boot/dts/imx6dl-pico-dwarf.dts | 17 - arch/arm/boot/dts/imx6dl-pico-hobbit.dts | 17 - arch/arm/boot/dts/imx6dl-pico-nymph.dts | 17 - arch/arm/boot/dts/imx6dl-pico-pi.dts | 17 - arch/arm/boot/dts/imx6dl-pinfunc.h | 1088 ---- arch/arm/boot/dts/imx6dl-plybas.dts | 396 -- arch/arm/boot/dts/imx6dl-plym2m.dts | 573 -- arch/arm/boot/dts/imx6dl-prtmvt.dts | 860 --- arch/arm/boot/dts/imx6dl-prtrvt.dts | 186 - arch/arm/boot/dts/imx6dl-prtvt7.dts | 612 -- arch/arm/boot/dts/imx6dl-qmx6.dtsi | 612 -- arch/arm/boot/dts/imx6dl-rex-basic.dts | 27 - arch/arm/boot/dts/imx6dl-riotboard.dts | 597 -- arch/arm/boot/dts/imx6dl-sabreauto.dts | 28 - arch/arm/boot/dts/imx6dl-sabrelite.dts | 55 - arch/arm/boot/dts/imx6dl-sabresd.dts | 18 - arch/arm/boot/dts/imx6dl-savageboard.dts | 51 - arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts | 14 - arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts | 106 - arch/arm/boot/dts/imx6dl-solidsense.dts | 54 - arch/arm/boot/dts/imx6dl-tqma6a.dtsi | 16 - arch/arm/boot/dts/imx6dl-tqma6b.dtsi | 16 - arch/arm/boot/dts/imx6dl-ts4900.dts | 55 - arch/arm/boot/dts/imx6dl-ts7970.dts | 56 - arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts | 79 - arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts | 48 - arch/arm/boot/dts/imx6dl-tx6s-8034.dts | 70 - arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts | 48 - arch/arm/boot/dts/imx6dl-tx6s-8035.dts | 86 - arch/arm/boot/dts/imx6dl-tx6u-801x.dts | 50 - arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts | 48 - arch/arm/boot/dts/imx6dl-tx6u-8033.dts | 82 - arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts | 48 - arch/arm/boot/dts/imx6dl-tx6u-811x.dts | 50 - arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts | 48 - arch/arm/boot/dts/imx6dl-udoo.dts | 14 - arch/arm/boot/dts/imx6dl-victgo.dts | 360 -- arch/arm/boot/dts/imx6dl-vicut1.dts | 14 - arch/arm/boot/dts/imx6dl-wandboard-revb1.dts | 19 - arch/arm/boot/dts/imx6dl-wandboard-revd1.dts | 19 - arch/arm/boot/dts/imx6dl-wandboard.dts | 19 - arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 648 -- arch/arm/boot/dts/imx6dl-yapp4-draco.dts | 58 - arch/arm/boot/dts/imx6dl-yapp4-hydra.dts | 54 - arch/arm/boot/dts/imx6dl-yapp4-lynx.dts | 58 - arch/arm/boot/dts/imx6dl-yapp4-orion.dts | 54 - arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts | 42 - arch/arm/boot/dts/imx6dl-yapp4-ursa.dts | 58 - arch/arm/boot/dts/imx6dl-yapp43-common.dtsi | 615 -- arch/arm/boot/dts/imx6dl.dtsi | 397 -- arch/arm/boot/dts/imx6q-apalis-eval.dts | 172 - arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 37 - arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts | 278 - arch/arm/boot/dts/imx6q-apalis-ixora.dts | 182 - arch/arm/boot/dts/imx6q-apf6dev.dts | 22 - arch/arm/boot/dts/imx6q-arm2.dts | 226 - arch/arm/boot/dts/imx6q-b450v3.dts | 157 - arch/arm/boot/dts/imx6q-b650v3.dts | 156 - arch/arm/boot/dts/imx6q-b850v3.dts | 295 - arch/arm/boot/dts/imx6q-ba16.dtsi | 661 -- arch/arm/boot/dts/imx6q-bosch-acc.dts | 779 --- arch/arm/boot/dts/imx6q-bx50v3.dtsi | 409 -- arch/arm/boot/dts/imx6q-cm-fx6.dts | 491 -- arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts | 60 - arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts | 59 - arch/arm/boot/dts/imx6q-cubox-i.dts | 59 - arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts | 23 - arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 25 - .../dts/imx6q-display5-tianma-tm070-1280x768.dts | 51 - arch/arm/boot/dts/imx6q-display5.dtsi | 596 -- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 481 -- arch/arm/boot/dts/imx6q-dms-ba16.dts | 139 - arch/arm/boot/dts/imx6q-ds.dts | 17 - arch/arm/boot/dts/imx6q-emcon-avari.dts | 14 - arch/arm/boot/dts/imx6q-evi.dts | 518 -- arch/arm/boot/dts/imx6q-gk802.dts | 174 - arch/arm/boot/dts/imx6q-gw51xx.dts | 13 - arch/arm/boot/dts/imx6q-gw52xx.dts | 75 - arch/arm/boot/dts/imx6q-gw53xx.dts | 75 - arch/arm/boot/dts/imx6q-gw5400-a.dts | 510 -- arch/arm/boot/dts/imx6q-gw54xx.dts | 177 - arch/arm/boot/dts/imx6q-gw551x.dts | 55 - arch/arm/boot/dts/imx6q-gw552x.dts | 18 - arch/arm/boot/dts/imx6q-gw553x.dts | 55 - arch/arm/boot/dts/imx6q-gw560x.dts | 59 - arch/arm/boot/dts/imx6q-gw5903.dts | 55 - arch/arm/boot/dts/imx6q-gw5904.dts | 59 - arch/arm/boot/dts/imx6q-gw5907.dts | 14 - arch/arm/boot/dts/imx6q-gw5910.dts | 14 - arch/arm/boot/dts/imx6q-gw5912.dts | 13 - arch/arm/boot/dts/imx6q-gw5913.dts | 14 - arch/arm/boot/dts/imx6q-h100.dts | 382 -- .../boot/dts/imx6q-hummingboard-emmc-som-v15.dts | 61 - arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts | 60 - arch/arm/boot/dts/imx6q-hummingboard.dts | 60 - .../boot/dts/imx6q-hummingboard2-emmc-som-v15.dts | 63 - arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts | 62 - arch/arm/boot/dts/imx6q-hummingboard2.dts | 61 - arch/arm/boot/dts/imx6q-icore-mipi.dts | 33 - arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 44 - arch/arm/boot/dts/imx6q-icore-ofcap12.dts | 43 - arch/arm/boot/dts/imx6q-icore-rqs.dts | 19 - arch/arm/boot/dts/imx6q-icore.dts | 57 - arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 35 - arch/arm/boot/dts/imx6q-kp-tpc.dts | 23 - arch/arm/boot/dts/imx6q-kp.dtsi | 434 -- arch/arm/boot/dts/imx6q-logicpd.dts | 130 - arch/arm/boot/dts/imx6q-marsboard.dts | 417 -- arch/arm/boot/dts/imx6q-mba6.dtsi | 44 - arch/arm/boot/dts/imx6q-mba6a.dts | 20 - arch/arm/boot/dts/imx6q-mba6b.dts | 20 - arch/arm/boot/dts/imx6q-mccmon6.dts | 471 -- arch/arm/boot/dts/imx6q-nitrogen6_max.dts | 17 - arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 17 - arch/arm/boot/dts/imx6q-nitrogen6x.dts | 19 - arch/arm/boot/dts/imx6q-novena.dts | 803 --- arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 75 - arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts | 75 - arch/arm/boot/dts/imx6q-phytec-pbab01.dts | 21 - arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 17 - arch/arm/boot/dts/imx6q-pico-dwarf.dts | 17 - arch/arm/boot/dts/imx6q-pico-hobbit.dts | 17 - arch/arm/boot/dts/imx6q-pico-nymph.dts | 17 - arch/arm/boot/dts/imx6q-pico-pi.dts | 17 - arch/arm/boot/dts/imx6q-pinfunc.h | 1044 --- arch/arm/boot/dts/imx6q-pistachio.dts | 695 -- arch/arm/boot/dts/imx6q-prti6q.dts | 543 -- arch/arm/boot/dts/imx6q-prtwd2.dts | 196 - arch/arm/boot/dts/imx6q-rex-pro.dts | 31 - arch/arm/boot/dts/imx6q-sabreauto.dts | 18 - arch/arm/boot/dts/imx6q-sabrelite.dts | 24 - arch/arm/boot/dts/imx6q-sabresd.dts | 23 - arch/arm/boot/dts/imx6q-savageboard.dts | 55 - arch/arm/boot/dts/imx6q-sbc6x.dts | 93 - arch/arm/boot/dts/imx6q-skov-revc-lt2.dts | 37 - arch/arm/boot/dts/imx6q-skov-revc-lt6.dts | 128 - .../boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts | 133 - arch/arm/boot/dts/imx6q-solidsense.dts | 54 - arch/arm/boot/dts/imx6q-tbs2910.dts | 407 -- arch/arm/boot/dts/imx6q-tqma6a.dtsi | 16 - arch/arm/boot/dts/imx6q-tqma6b.dtsi | 15 - arch/arm/boot/dts/imx6q-ts4900.dts | 59 - arch/arm/boot/dts/imx6q-ts7970.dts | 60 - arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts | 79 - arch/arm/boot/dts/imx6q-tx6q-1010.dts | 54 - arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts | 110 - arch/arm/boot/dts/imx6q-tx6q-1020.dts | 86 - arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts | 48 - arch/arm/boot/dts/imx6q-tx6q-1036.dts | 86 - arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts | 48 - arch/arm/boot/dts/imx6q-tx6q-1110.dts | 58 - arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts | 48 - arch/arm/boot/dts/imx6q-udoo.dts | 18 - arch/arm/boot/dts/imx6q-utilite-pro.dts | 355 -- arch/arm/boot/dts/imx6q-var-dt6customboard.dts | 235 - arch/arm/boot/dts/imx6q-vicut1.dts | 14 - arch/arm/boot/dts/imx6q-wandboard-revb1.dts | 23 - arch/arm/boot/dts/imx6q-wandboard-revd1.dts | 23 - arch/arm/boot/dts/imx6q-wandboard.dts | 23 - arch/arm/boot/dts/imx6q-yapp4-crux.dts | 58 - arch/arm/boot/dts/imx6q-yapp4-pegasus.dts | 58 - arch/arm/boot/dts/imx6q-zii-rdu2.dts | 20 - arch/arm/boot/dts/imx6q.dtsi | 553 -- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 1371 ---- arch/arm/boot/dts/imx6qdl-apf6.dtsi | 152 - arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 451 -- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 408 -- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 637 -- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 1309 ---- arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 270 - arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 201 - arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi | 143 - arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi | 335 - arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi | 69 - arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 850 --- arch/arm/boot/dts/imx6qdl-ds.dtsi | 458 -- arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi | 177 - arch/arm/boot/dts/imx6qdl-emcon.dtsi | 834 --- arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 638 -- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 795 --- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 784 --- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 877 --- arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 695 -- arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 519 -- arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 738 --- arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 931 --- arch/arm/boot/dts/imx6qdl-gw5903.dtsi | 793 --- arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 820 --- arch/arm/boot/dts/imx6qdl-gw5907.dtsi | 536 -- arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 664 -- arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 604 -- arch/arm/boot/dts/imx6qdl-gw5913.dtsi | 498 -- arch/arm/boot/dts/imx6qdl-hummingboard.dtsi | 368 -- arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi | 72 - arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi | 577 -- arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi | 32 - arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 466 -- arch/arm/boot/dts/imx6qdl-icore.dtsi | 431 -- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 821 --- arch/arm/boot/dts/imx6qdl-mba6.dtsi | 592 -- arch/arm/boot/dts/imx6qdl-mba6a.dtsi | 36 - arch/arm/boot/dts/imx6qdl-mba6b.dtsi | 55 - arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 583 -- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 849 --- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 736 --- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 693 -- .../boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 - .../boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi | 71 - .../boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 85 - arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi | 412 -- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 177 - arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 466 -- arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 311 - arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi | 45 - arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi | 37 - arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi | 54 - arch/arm/boot/dts/imx6qdl-pico-pi.dtsi | 31 - arch/arm/boot/dts/imx6qdl-pico.dtsi | 627 -- arch/arm/boot/dts/imx6qdl-prti6q.dtsi | 175 - arch/arm/boot/dts/imx6qdl-rex.dtsi | 367 -- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 864 --- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 748 --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 851 --- arch/arm/boot/dts/imx6qdl-savageboard.dtsi | 256 - arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi | 79 - arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi | 491 -- arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi | 99 - arch/arm/boot/dts/imx6qdl-solidsense.dtsi | 160 - arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi | 144 - arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi | 70 - arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi | 171 - arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 158 - arch/arm/boot/dts/imx6qdl-tqma6.dtsi | 215 - arch/arm/boot/dts/imx6qdl-tqma6a.dtsi | 55 - arch/arm/boot/dts/imx6qdl-tqma6b.dtsi | 34 - arch/arm/boot/dts/imx6qdl-ts4900.dtsi | 479 -- arch/arm/boot/dts/imx6qdl-ts7970.dtsi | 594 -- arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi | 251 - arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi | 286 - arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi | 96 - arch/arm/boot/dts/imx6qdl-tx6.dtsi | 792 --- arch/arm/boot/dts/imx6qdl-udoo.dtsi | 327 - arch/arm/boot/dts/imx6qdl-var-dart.dtsi | 504 -- arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi | 128 - arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 712 --- arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 36 - arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi | 35 - arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi | 193 - arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 378 -- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 1142 ---- arch/arm/boot/dts/imx6qdl.dtsi | 1393 ---- arch/arm/boot/dts/imx6qp-mba6b.dts | 18 - arch/arm/boot/dts/imx6qp-nitrogen6_max.dts | 22 - arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts | 18 - arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 75 - arch/arm/boot/dts/imx6qp-prtwd3.dts | 557 -- arch/arm/boot/dts/imx6qp-sabreauto.dts | 60 - arch/arm/boot/dts/imx6qp-sabresd.dts | 63 - arch/arm/boot/dts/imx6qp-tqma6b.dtsi | 16 - arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts | 48 - arch/arm/boot/dts/imx6qp-tx6qp-8037.dts | 86 - arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts | 57 - arch/arm/boot/dts/imx6qp-tx6qp-8137.dts | 90 - arch/arm/boot/dts/imx6qp-vicutp.dts | 14 - arch/arm/boot/dts/imx6qp-wandboard-revd1.dts | 23 - arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts | 58 - arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts | 58 - arch/arm/boot/dts/imx6qp-zii-rdu2.dts | 25 - arch/arm/boot/dts/imx6qp.dtsi | 120 - arch/arm/boot/dts/imx6s-dhcom-drc02.dts | 30 - arch/arm/boot/dts/imx6sl-evk.dts | 658 -- arch/arm/boot/dts/imx6sl-kobo-aura2.dts | 555 -- arch/arm/boot/dts/imx6sl-pinfunc.h | 1073 ---- arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts | 634 -- arch/arm/boot/dts/imx6sl-tolino-shine3.dts | 340 - arch/arm/boot/dts/imx6sl-tolino-vision.dts | 490 -- arch/arm/boot/dts/imx6sl-tolino-vision5.dts | 356 -- arch/arm/boot/dts/imx6sl-warp.dts | 234 - arch/arm/boot/dts/imx6sl.dtsi | 1008 --- arch/arm/boot/dts/imx6sll-evk.dts | 643 -- arch/arm/boot/dts/imx6sll-kobo-clarahd.dts | 342 - arch/arm/boot/dts/imx6sll-kobo-librah2o.dts | 346 - arch/arm/boot/dts/imx6sll-pinfunc.h | 880 --- arch/arm/boot/dts/imx6sll.dtsi | 839 --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 603 -- arch/arm/boot/dts/imx6sx-pinfunc.h | 1668 ----- arch/arm/boot/dts/imx6sx-sabreauto.dts | 557 -- arch/arm/boot/dts/imx6sx-sdb-mqs.dts | 48 - arch/arm/boot/dts/imx6sx-sdb-reva.dts | 169 - arch/arm/boot/dts/imx6sx-sdb-sai.dts | 30 - arch/arm/boot/dts/imx6sx-sdb.dts | 155 - arch/arm/boot/dts/imx6sx-sdb.dtsi | 718 --- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 587 -- arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts | 33 - arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts | 26 - arch/arm/boot/dts/imx6sx-udoo-neo-full.dts | 41 - arch/arm/boot/dts/imx6sx-udoo-neo.dtsi | 482 -- arch/arm/boot/dts/imx6sx.dtsi | 1469 ----- arch/arm/boot/dts/imx6ul-14x14-evk.dts | 13 - arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 651 -- arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts | 200 - arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts | 428 -- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 270 - arch/arm/boot/dts/imx6ul-geam.dts | 447 -- arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi | 148 - arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi | 327 - arch/arm/boot/dts/imx6ul-isiot-emmc.dts | 18 - arch/arm/boot/dts/imx6ul-isiot-nand.dts | 18 - arch/arm/boot/dts/imx6ul-isiot.dtsi | 387 -- arch/arm/boot/dts/imx6ul-kontron-bl-43.dts | 103 - arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi | 405 -- arch/arm/boot/dts/imx6ul-kontron-bl.dts | 16 - arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi | 137 - arch/arm/boot/dts/imx6ul-kontron-sl.dtsi | 14 - arch/arm/boot/dts/imx6ul-liteboard.dts | 151 - arch/arm/boot/dts/imx6ul-litesom.dtsi | 83 - arch/arm/boot/dts/imx6ul-opos6ul.dtsi | 6 - arch/arm/boot/dts/imx6ul-opos6uldev.dts | 41 - arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 186 - .../boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 94 - .../boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 95 - .../boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 150 - .../boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 57 - .../boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 90 - arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 299 - arch/arm/boot/dts/imx6ul-pico-dwarf.dts | 52 - arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 100 - arch/arm/boot/dts/imx6ul-pico-pi.dts | 97 - arch/arm/boot/dts/imx6ul-pico.dtsi | 453 -- arch/arm/boot/dts/imx6ul-pinfunc.h | 959 --- arch/arm/boot/dts/imx6ul-prti6g.dts | 353 -- arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi | 211 - arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts | 55 - arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi | 37 - arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts | 15 - arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi | 71 - arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts | 15 - arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi | 71 - arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi | 43 - arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi | 48 - arch/arm/boot/dts/imx6ul-tx6ul-0010.dts | 53 - arch/arm/boot/dts/imx6ul-tx6ul-0011.dts | 68 - arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts | 271 - arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 947 --- arch/arm/boot/dts/imx6ul.dtsi | 1124 ---- arch/arm/boot/dts/imx6ull-14x14-evk.dts | 18 - arch/arm/boot/dts/imx6ull-colibri-aster.dts | 60 - arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 147 - arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts | 17 - arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts | 17 - arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 - arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts | 17 - .../arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi | 187 - arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 38 - arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 123 - arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 105 - arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 - arch/arm/boot/dts/imx6ull-colibri-iris.dts | 40 - arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 134 - arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 161 - arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts | 60 - arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 38 - arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 89 - arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts | 40 - arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 189 - arch/arm/boot/dts/imx6ull-colibri.dtsi | 773 --- arch/arm/boot/dts/imx6ull-dhcom-drc02.dts | 99 - arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts | 222 - arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts | 101 - .../arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi | 97 - arch/arm/boot/dts/imx6ull-dhcom-som.dtsi | 631 -- arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts | 359 -- arch/arm/boot/dts/imx6ull-dhcor-som.dtsi | 260 - arch/arm/boot/dts/imx6ull-jozacp.dts | 456 -- arch/arm/boot/dts/imx6ull-kontron-bl.dts | 15 - arch/arm/boot/dts/imx6ull-kontron-sl.dtsi | 13 - arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts | 19 - arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi | 238 - arch/arm/boot/dts/imx6ull-opos6ul.dtsi | 6 - arch/arm/boot/dts/imx6ull-opos6uldev.dts | 42 - arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 - .../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 94 - .../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 95 - .../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 46 - .../boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi | 26 - .../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 - .../boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 - arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 31 - arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 - arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts | 20 - arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 587 -- arch/arm/boot/dts/imx6ull-pinfunc-snvs.h | 26 - arch/arm/boot/dts/imx6ull-pinfunc.h | 87 - arch/arm/boot/dts/imx6ull-tarragon-common.dtsi | 852 --- arch/arm/boot/dts/imx6ull-tarragon-master.dts | 82 - arch/arm/boot/dts/imx6ull-tarragon-micro.dts | 10 - arch/arm/boot/dts/imx6ull-tarragon-slave.dts | 32 - arch/arm/boot/dts/imx6ull-tarragon-slavext.dts | 64 - arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts | 15 - arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi | 76 - arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts | 15 - arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi | 76 - arch/arm/boot/dts/imx6ull.dtsi | 95 - arch/arm/boot/dts/imx6ulz-14x14-evk.dts | 22 - arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts | 150 - arch/arm/boot/dts/imx6ulz.dtsi | 36 - arch/arm/boot/dts/imx7-colibri-aster.dtsi | 80 - arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 111 - arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi | 113 - arch/arm/boot/dts/imx7-colibri-iris.dtsi | 109 - arch/arm/boot/dts/imx7-colibri.dtsi | 1142 ---- arch/arm/boot/dts/imx7-mba7.dtsi | 640 -- arch/arm/boot/dts/imx7-tqma7.dtsi | 292 - arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 294 - arch/arm/boot/dts/imx7d-colibri-aster.dts | 41 - arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts | 23 - arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts | 22 - arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts | 22 - arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts | 22 - arch/arm/boot/dts/imx7d-colibri-emmc.dtsi | 62 - arch/arm/boot/dts/imx7d-colibri-eval-v3.dts | 57 - arch/arm/boot/dts/imx7d-colibri-iris-v2.dts | 84 - arch/arm/boot/dts/imx7d-colibri-iris.dts | 57 - arch/arm/boot/dts/imx7d-colibri.dtsi | 35 - arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts | 25 - arch/arm/boot/dts/imx7d-flex-concentrator.dts | 313 - arch/arm/boot/dts/imx7d-mba7.dts | 113 - arch/arm/boot/dts/imx7d-meerkat96.dts | 375 -- arch/arm/boot/dts/imx7d-nitrogen7.dts | 699 -- arch/arm/boot/dts/imx7d-pico-dwarf.dts | 87 - arch/arm/boot/dts/imx7d-pico-hobbit.dts | 105 - arch/arm/boot/dts/imx7d-pico-nymph.dts | 84 - arch/arm/boot/dts/imx7d-pico-pi.dts | 93 - arch/arm/boot/dts/imx7d-pico.dtsi | 675 -- arch/arm/boot/dts/imx7d-pinfunc.h | 1154 ---- arch/arm/boot/dts/imx7d-remarkable2.dts | 595 -- arch/arm/boot/dts/imx7d-sbc-imx7.dts | 42 - arch/arm/boot/dts/imx7d-sdb-reva.dts | 43 - arch/arm/boot/dts/imx7d-sdb-sht11.dts | 36 - arch/arm/boot/dts/imx7d-sdb.dts | 904 --- arch/arm/boot/dts/imx7d-smegw01.dts | 468 -- arch/arm/boot/dts/imx7d-tqma7.dtsi | 15 - arch/arm/boot/dts/imx7d-zii-rmu2.dts | 357 -- arch/arm/boot/dts/imx7d-zii-rpu2.dts | 923 --- arch/arm/boot/dts/imx7d.dtsi | 229 - arch/arm/boot/dts/imx7s-colibri-aster.dts | 36 - arch/arm/boot/dts/imx7s-colibri-eval-v3.dts | 51 - arch/arm/boot/dts/imx7s-colibri-iris-v2.dts | 78 - arch/arm/boot/dts/imx7s-colibri-iris.dts | 51 - arch/arm/boot/dts/imx7s-colibri.dtsi | 19 - arch/arm/boot/dts/imx7s-mba7.dts | 18 - arch/arm/boot/dts/imx7s-tqma7.dtsi | 11 - arch/arm/boot/dts/imx7s-warp.dts | 500 -- arch/arm/boot/dts/imx7s.dtsi | 1290 ---- arch/arm/boot/dts/imx7ulp-com.dts | 79 - arch/arm/boot/dts/imx7ulp-evk.dts | 133 - arch/arm/boot/dts/imx7ulp-pinfunc.h | 478 -- arch/arm/boot/dts/imx7ulp.dtsi | 466 -- arch/arm/boot/dts/imxrt1050-evk.dts | 72 - arch/arm/boot/dts/imxrt1050-pinfunc.h | 993 --- arch/arm/boot/dts/imxrt1050.dtsi | 160 - arch/arm/boot/dts/imxrt1170-pinfunc.h | 1561 ----- arch/arm/boot/dts/integrator.dtsi | 154 - arch/arm/boot/dts/integratorap-im-pd1.dts | 276 - arch/arm/boot/dts/integratorap.dts | 295 - arch/arm/boot/dts/integratorcp.dts | 322 - arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts | 112 - arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts | 169 - arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts | 147 - arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts | 219 - arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts | 110 - .../arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts | 174 - .../arm/boot/dts/intel-ixp42x-goramo-multilink.dts | 180 - arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts | 148 - arch/arm/boot/dts/intel-ixp42x-ixdp425.dts | 72 - arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts | 127 - arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 162 - arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts | 175 - arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts | 96 - .../arm/boot/dts/intel-ixp42x-welltech-epbx100.dts | 98 - arch/arm/boot/dts/intel-ixp42x.dtsi | 34 - .../arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts | 199 - arch/arm/boot/dts/intel-ixp43x-kixrp435.dts | 68 - arch/arm/boot/dts/intel-ixp43x.dtsi | 25 - arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi | 86 - arch/arm/boot/dts/intel-ixp46x-ixdp465.dts | 38 - .../boot/dts/intel-ixp4xx-reference-design.dtsi | 134 - arch/arm/boot/dts/intel-ixp4xx.dtsi | 202 - arch/arm/boot/dts/intel/Makefile | 5 + arch/arm/boot/dts/intel/axm/Makefile | 5 + arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts | 47 + arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi | 200 + arch/arm/boot/dts/intel/axm/axm55xx.dtsi | 200 + arch/arm/boot/dts/intel/ixp/Makefile | 19 + .../boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts | 112 + .../dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts | 169 + .../dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 147 + .../dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts | 219 + .../dts/intel/ixp/intel-ixp42x-gateway-7001.dts | 110 + .../intel/ixp/intel-ixp42x-gateworks-gw2348.dts | 174 + .../intel/ixp/intel-ixp42x-goramo-multilink.dts | 180 + .../dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 148 + .../boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts | 72 + .../boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts | 127 + .../dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 162 + .../dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts | 175 + .../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 96 + .../intel/ixp/intel-ixp42x-welltech-epbx100.dts | 98 + arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi | 34 + .../intel/ixp/intel-ixp43x-gateworks-gw2358.dts | 199 + .../boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts | 68 + arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi | 25 + .../boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi | 86 + .../boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts | 38 + .../intel/ixp/intel-ixp4xx-reference-design.dtsi | 134 + arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi | 202 + arch/arm/boot/dts/intel/pxa/Makefile | 8 + arch/arm/boot/dts/intel/pxa/pxa25x.dtsi | 118 + arch/arm/boot/dts/intel/pxa/pxa27x.dtsi | 188 + arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi | 162 + .../boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi | 405 ++ .../dts/intel/pxa/pxa300-raumfeld-connector.dts | 73 + .../dts/intel/pxa/pxa300-raumfeld-controller.dts | 285 + .../dts/intel/pxa/pxa300-raumfeld-speaker-l.dts | 11 + .../dts/intel/pxa/pxa300-raumfeld-speaker-m.dts | 11 + .../dts/intel/pxa/pxa300-raumfeld-speaker-one.dts | 140 + .../dts/intel/pxa/pxa300-raumfeld-speaker-s.dts | 11 + .../intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi | 85 + arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi | 320 + arch/arm/boot/dts/intel/socfpga/Makefile | 17 + arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 984 +++ .../boot/dts/intel/socfpga/socfpga_arria10.dtsi | 920 +++ .../intel/socfpga/socfpga_arria10_chameleonv3.dts | 90 + .../intel/socfpga/socfpga_arria10_mercury_aa1.dtsi | 81 + .../intel/socfpga/socfpga_arria10_mercury_pe1.dts | 55 + .../dts/intel/socfpga/socfpga_arria10_socdk.dtsi | 183 + .../intel/socfpga/socfpga_arria10_socdk_nand.dts | 26 + .../intel/socfpga/socfpga_arria10_socdk_qspi.dts | 38 + .../intel/socfpga/socfpga_arria10_socdk_sdmmc.dts | 28 + .../arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi | 37 + .../dts/intel/socfpga/socfpga_arria5_socdk.dts | 151 + .../boot/dts/intel/socfpga/socfpga_cyclone5.dtsi | 37 + .../intel/socfpga/socfpga_cyclone5_chameleon96.dts | 130 + .../socfpga/socfpga_cyclone5_de0_nano_soc.dts | 101 + .../dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi | 23 + .../dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts | 81 + .../dts/intel/socfpga/socfpga_cyclone5_socdk.dts | 166 + .../dts/intel/socfpga/socfpga_cyclone5_sockit.dts | 189 + .../intel/socfpga/socfpga_cyclone5_socrates.dts | 94 + .../dts/intel/socfpga/socfpga_cyclone5_sodia.dts | 132 + .../intel/socfpga/socfpga_cyclone5_vining_fpga.dts | 267 + arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts | 77 + arch/arm/boot/dts/iwg20d-q7-common.dtsi | 375 -- arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi | 124 - arch/arm/boot/dts/keystone-clocks.dtsi | 438 -- arch/arm/boot/dts/keystone-k2e-clocks.dtsi | 94 - arch/arm/boot/dts/keystone-k2e-evm.dts | 177 - arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 264 - arch/arm/boot/dts/keystone-k2e.dtsi | 198 - arch/arm/boot/dts/keystone-k2g-evm.dts | 567 -- arch/arm/boot/dts/keystone-k2g-ice.dts | 447 -- arch/arm/boot/dts/keystone-k2g-netcp.dtsi | 147 - arch/arm/boot/dts/keystone-k2g.dtsi | 644 -- arch/arm/boot/dts/keystone-k2hk-clocks.dtsi | 422 -- arch/arm/boot/dts/keystone-k2hk-evm.dts | 236 - arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | 266 - arch/arm/boot/dts/keystone-k2hk.dtsi | 295 - arch/arm/boot/dts/keystone-k2l-clocks.dtsi | 263 - arch/arm/boot/dts/keystone-k2l-evm.dts | 165 - arch/arm/boot/dts/keystone-k2l-netcp.dtsi | 246 - arch/arm/boot/dts/keystone-k2l.dtsi | 415 -- arch/arm/boot/dts/keystone.dtsi | 354 -- arch/arm/boot/dts/kirkwood-4i-edge-200.dts | 205 - arch/arm/boot/dts/kirkwood-6192.dtsi | 98 - arch/arm/boot/dts/kirkwood-6281.dtsi | 100 - arch/arm/boot/dts/kirkwood-6282.dtsi | 161 - arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 63 - arch/arm/boot/dts/kirkwood-b3.dts | 195 - arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts | 172 - arch/arm/boot/dts/kirkwood-c200-v1.dts | 310 - arch/arm/boot/dts/kirkwood-cloudbox.dts | 103 - arch/arm/boot/dts/kirkwood-d2net.dts | 45 - arch/arm/boot/dts/kirkwood-db-88f6281.dts | 26 - arch/arm/boot/dts/kirkwood-db-88f6282.dts | 30 - arch/arm/boot/dts/kirkwood-db.dtsi | 89 - arch/arm/boot/dts/kirkwood-dir665.dts | 277 - arch/arm/boot/dts/kirkwood-dns320.dts | 59 - arch/arm/boot/dts/kirkwood-dns325.dts | 63 - arch/arm/boot/dts/kirkwood-dnskw.dtsi | 235 - arch/arm/boot/dts/kirkwood-dockstar.dts | 110 - arch/arm/boot/dts/kirkwood-dreamplug.dts | 127 - arch/arm/boot/dts/kirkwood-ds109.dts | 40 - arch/arm/boot/dts/kirkwood-ds110jv10.dts | 40 - arch/arm/boot/dts/kirkwood-ds111.dts | 43 - arch/arm/boot/dts/kirkwood-ds112.dts | 51 - arch/arm/boot/dts/kirkwood-ds209.dts | 43 - arch/arm/boot/dts/kirkwood-ds210.dts | 45 - arch/arm/boot/dts/kirkwood-ds212.dts | 46 - arch/arm/boot/dts/kirkwood-ds212j.dts | 40 - arch/arm/boot/dts/kirkwood-ds409.dts | 47 - arch/arm/boot/dts/kirkwood-ds409slim.dts | 39 - arch/arm/boot/dts/kirkwood-ds411.dts | 55 - arch/arm/boot/dts/kirkwood-ds411j.dts | 47 - arch/arm/boot/dts/kirkwood-ds411slim.dts | 47 - arch/arm/boot/dts/kirkwood-goflexnet.dts | 190 - .../arm/boot/dts/kirkwood-guruplug-server-plus.dts | 133 - arch/arm/boot/dts/kirkwood-ib62x0.dts | 146 - arch/arm/boot/dts/kirkwood-iconnect.dts | 195 - arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 226 - arch/arm/boot/dts/kirkwood-is2.dts | 40 - arch/arm/boot/dts/kirkwood-km_common.dtsi | 47 - arch/arm/boot/dts/kirkwood-km_fixedeth.dts | 24 - arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 31 - arch/arm/boot/dts/kirkwood-l-50.dts | 438 -- arch/arm/boot/dts/kirkwood-laplug.dts | 168 - arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi | 155 - .../boot/dts/kirkwood-linkstation-duo-6281.dtsi | 149 - arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts | 98 - arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts | 20 - arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts | 20 - arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts | 75 - arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts | 79 - arch/arm/boot/dts/kirkwood-linkstation.dtsi | 164 - arch/arm/boot/dts/kirkwood-linksys-viper.dts | 241 - arch/arm/boot/dts/kirkwood-lschlv2.dts | 20 - arch/arm/boot/dts/kirkwood-lsxhl.dts | 20 - arch/arm/boot/dts/kirkwood-lsxl.dtsi | 231 - arch/arm/boot/dts/kirkwood-mplcec4.dts | 216 - arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 179 - arch/arm/boot/dts/kirkwood-nas2big.dts | 139 - arch/arm/boot/dts/kirkwood-net2big.dts | 63 - arch/arm/boot/dts/kirkwood-net5big.dts | 169 - .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 247 - .../boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 274 - arch/arm/boot/dts/kirkwood-netxbig.dtsi | 232 - arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 97 - arch/arm/boot/dts/kirkwood-ns2.dts | 40 - arch/arm/boot/dts/kirkwood-ns2lite.dts | 35 - arch/arm/boot/dts/kirkwood-ns2max.dts | 59 - arch/arm/boot/dts/kirkwood-ns2mini.dts | 60 - arch/arm/boot/dts/kirkwood-nsa310.dts | 139 - arch/arm/boot/dts/kirkwood-nsa310a.dts | 115 - arch/arm/boot/dts/kirkwood-nsa310s.dts | 259 - arch/arm/boot/dts/kirkwood-nsa320.dts | 219 - arch/arm/boot/dts/kirkwood-nsa325.dts | 232 - arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi | 158 - arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 184 - arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 209 - arch/arm/boot/dts/kirkwood-openrd-base.dts | 39 - arch/arm/boot/dts/kirkwood-openrd-client.dts | 74 - arch/arm/boot/dts/kirkwood-openrd-ultimate.dts | 55 - arch/arm/boot/dts/kirkwood-openrd.dtsi | 122 - arch/arm/boot/dts/kirkwood-pogo_e02.dts | 132 - arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts | 180 - arch/arm/boot/dts/kirkwood-rd88f6192.dts | 106 - arch/arm/boot/dts/kirkwood-rd88f6281-a.dts | 39 - arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts | 34 - arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 134 - arch/arm/boot/dts/kirkwood-rs212.dts | 51 - arch/arm/boot/dts/kirkwood-rs409.dts | 43 - arch/arm/boot/dts/kirkwood-rs411.dts | 43 - arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 104 - arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts | 42 - arch/arm/boot/dts/kirkwood-sheevaplug.dts | 42 - arch/arm/boot/dts/kirkwood-synology.dtsi | 855 --- arch/arm/boot/dts/kirkwood-t5325.dts | 227 - arch/arm/boot/dts/kirkwood-topkick.dts | 216 - arch/arm/boot/dts/kirkwood-ts219-6281.dts | 56 - arch/arm/boot/dts/kirkwood-ts219-6282.dts | 58 - arch/arm/boot/dts/kirkwood-ts219.dtsi | 114 - arch/arm/boot/dts/kirkwood-ts419-6281.dts | 16 - arch/arm/boot/dts/kirkwood-ts419-6282.dts | 19 - arch/arm/boot/dts/kirkwood-ts419.dtsi | 71 - arch/arm/boot/dts/kirkwood.dtsi | 394 -- .../dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 94 - .../dts/lan966x-kontron-kswitch-d10-mmt-8g.dts | 39 - .../boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 203 - arch/arm/boot/dts/lan966x-pcb8290.dts | 195 - arch/arm/boot/dts/lan966x-pcb8291.dts | 147 - arch/arm/boot/dts/lan966x-pcb8309.dts | 230 - arch/arm/boot/dts/lan966x.dtsi | 615 -- arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts | 28 - arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts | 28 - arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi | 237 - arch/arm/boot/dts/logicpd-som-lv.dtsi | 296 - arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts | 21 - .../boot/dts/logicpd-torpedo-37xx-devkit-28.dts | 15 - arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 96 - arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi | 420 -- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 203 - arch/arm/boot/dts/lpc18xx.dtsi | 537 -- arch/arm/boot/dts/lpc3250-ea3250.dts | 273 - arch/arm/boot/dts/lpc3250-phy3250.dts | 236 - arch/arm/boot/dts/lpc32xx.dtsi | 508 -- arch/arm/boot/dts/lpc4337-ciaa.dts | 221 - arch/arm/boot/dts/lpc4350-hitex-eval.dts | 481 -- arch/arm/boot/dts/lpc4350.dtsi | 39 - arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 623 -- arch/arm/boot/dts/lpc4357-myd-lpc4357.dts | 619 -- arch/arm/boot/dts/lpc4357.dtsi | 43 - arch/arm/boot/dts/ls1021a-iot.dts | 227 - arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 237 - arch/arm/boot/dts/ls1021a-qds.dts | 326 - arch/arm/boot/dts/ls1021a-tsn.dts | 295 - arch/arm/boot/dts/ls1021a-twr.dts | 240 - arch/arm/boot/dts/ls1021a.dtsi | 987 --- arch/arm/boot/dts/marvell/Makefile | 165 + arch/arm/boot/dts/marvell/armada-370-c200-v2.dts | 388 ++ arch/arm/boot/dts/marvell/armada-370-db.dts | 244 + .../boot/dts/marvell/armada-370-dlink-dns327l.dts | 330 + arch/arm/boot/dts/marvell/armada-370-mirabox.dts | 184 + .../boot/dts/marvell/armada-370-netgear-rn102.dts | 276 + .../boot/dts/marvell/armada-370-netgear-rn104.dts | 302 + arch/arm/boot/dts/marvell/armada-370-rd.dts | 268 + .../dts/marvell/armada-370-seagate-nas-2bay.dts | 33 + .../dts/marvell/armada-370-seagate-nas-4bay.dts | 131 + .../dts/marvell/armada-370-seagate-nas-xbay.dtsi | 237 + .../armada-370-seagate-personal-cloud-2bay.dts | 48 + .../marvell/armada-370-seagate-personal-cloud.dts | 34 + .../marvell/armada-370-seagate-personal-cloud.dtsi | 173 + .../dts/marvell/armada-370-synology-ds213j.dts | 312 + arch/arm/boot/dts/marvell/armada-370-xp.dtsi | 313 + arch/arm/boot/dts/marvell/armada-370.dtsi | 439 ++ arch/arm/boot/dts/marvell/armada-375-db.dts | 182 + arch/arm/boot/dts/marvell/armada-375.dtsi | 645 ++ arch/arm/boot/dts/marvell/armada-380.dtsi | 148 + .../dts/marvell/armada-381-netgear-gs110emx.dts | 295 + .../dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts | 112 + arch/arm/boot/dts/marvell/armada-385-atl-x530.dts | 235 + .../dts/marvell/armada-385-clearfog-gtr-l8.dts | 120 + .../dts/marvell/armada-385-clearfog-gtr-s4.dts | 84 + .../boot/dts/marvell/armada-385-clearfog-gtr.dtsi | 450 ++ .../boot/dts/marvell/armada-385-db-88f6820-amc.dts | 155 + arch/arm/boot/dts/marvell/armada-385-db-ap.dts | 238 + .../boot/dts/marvell/armada-385-linksys-caiman.dts | 144 + .../boot/dts/marvell/armada-385-linksys-cobra.dts | 144 + .../boot/dts/marvell/armada-385-linksys-rango.dts | 176 + .../boot/dts/marvell/armada-385-linksys-shelby.dts | 144 + arch/arm/boot/dts/marvell/armada-385-linksys.dtsi | 265 + .../boot/dts/marvell/armada-385-synology-ds116.dts | 292 + .../boot/dts/marvell/armada-385-turris-omnia.dts | 571 ++ arch/arm/boot/dts/marvell/armada-385.dtsi | 185 + .../boot/dts/marvell/armada-388-clearfog-base.dts | 68 + .../boot/dts/marvell/armada-388-clearfog-pro.dts | 14 + arch/arm/boot/dts/marvell/armada-388-clearfog.dts | 185 + arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi | 245 + arch/arm/boot/dts/marvell/armada-388-db.dts | 245 + arch/arm/boot/dts/marvell/armada-388-gp.dts | 406 ++ arch/arm/boot/dts/marvell/armada-388-helios4.dts | 324 + arch/arm/boot/dts/marvell/armada-388-rd.dts | 108 + arch/arm/boot/dts/marvell/armada-388.dtsi | 37 + .../dts/marvell/armada-38x-solidrun-microsom.dtsi | 117 + arch/arm/boot/dts/marvell/armada-38x.dtsi | 733 +++ arch/arm/boot/dts/marvell/armada-390-db.dts | 142 + arch/arm/boot/dts/marvell/armada-390.dtsi | 23 + arch/arm/boot/dts/marvell/armada-395-gp.dts | 136 + arch/arm/boot/dts/marvell/armada-395.dtsi | 39 + arch/arm/boot/dts/marvell/armada-398-db.dts | 134 + arch/arm/boot/dts/marvell/armada-398.dtsi | 31 + arch/arm/boot/dts/marvell/armada-39x.dtsi | 594 ++ arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi | 359 ++ arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi | 39 + arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi | 54 + arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts | 142 + .../dts/marvell/armada-xp-crs305-1g-4s-bit.dts | 43 + .../boot/dts/marvell/armada-xp-crs305-1g-4s.dts | 17 + .../boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi | 104 + .../dts/marvell/armada-xp-crs326-24g-2s-bit.dts | 43 + .../boot/dts/marvell/armada-xp-crs326-24g-2s.dts | 17 + .../boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi | 104 + .../dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts | 43 + .../dts/marvell/armada-xp-crs328-4c-20s-4s.dts | 17 + .../dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi | 104 + arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts | 118 + .../boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts | 114 + arch/arm/boot/dts/marvell/armada-xp-db.dts | 245 + arch/arm/boot/dts/marvell/armada-xp-gp.dts | 230 + .../boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts | 293 + .../boot/dts/marvell/armada-xp-linksys-mamba.dts | 397 ++ arch/arm/boot/dts/marvell/armada-xp-matrix.dts | 79 + arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi | 257 + arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi | 404 ++ arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi | 453 ++ .../boot/dts/marvell/armada-xp-netgear-rn2120.dts | 357 ++ .../dts/marvell/armada-xp-openblocks-ax3-4.dts | 209 + .../boot/dts/marvell/armada-xp-synology-ds414.dts | 328 + arch/arm/boot/dts/marvell/armada-xp.dtsi | 345 + arch/arm/boot/dts/marvell/dove-cm-a510.dtsi | 203 + arch/arm/boot/dts/marvell/dove-cubox-es.dts | 13 + arch/arm/boot/dts/marvell/dove-cubox.dts | 150 + arch/arm/boot/dts/marvell/dove-d2plug.dts | 70 + arch/arm/boot/dts/marvell/dove-d3plug.dts | 104 + arch/arm/boot/dts/marvell/dove-dove-db.dts | 39 + arch/arm/boot/dts/marvell/dove-sbc-a510.dts | 183 + arch/arm/boot/dts/marvell/dove.dtsi | 820 +++ arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts | 205 + arch/arm/boot/dts/marvell/kirkwood-6192.dtsi | 98 + arch/arm/boot/dts/marvell/kirkwood-6281.dtsi | 100 + arch/arm/boot/dts/marvell/kirkwood-6282.dtsi | 161 + arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi | 63 + arch/arm/boot/dts/marvell/kirkwood-b3.dts | 195 + .../dts/marvell/kirkwood-blackarmor-nas220.dts | 172 + arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts | 310 + arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts | 103 + arch/arm/boot/dts/marvell/kirkwood-d2net.dts | 45 + arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts | 26 + arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts | 30 + arch/arm/boot/dts/marvell/kirkwood-db.dtsi | 89 + arch/arm/boot/dts/marvell/kirkwood-dir665.dts | 277 + arch/arm/boot/dts/marvell/kirkwood-dns320.dts | 59 + arch/arm/boot/dts/marvell/kirkwood-dns325.dts | 63 + arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi | 235 + arch/arm/boot/dts/marvell/kirkwood-dockstar.dts | 110 + arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts | 127 + arch/arm/boot/dts/marvell/kirkwood-ds109.dts | 40 + arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts | 40 + arch/arm/boot/dts/marvell/kirkwood-ds111.dts | 43 + arch/arm/boot/dts/marvell/kirkwood-ds112.dts | 51 + arch/arm/boot/dts/marvell/kirkwood-ds209.dts | 43 + arch/arm/boot/dts/marvell/kirkwood-ds210.dts | 45 + arch/arm/boot/dts/marvell/kirkwood-ds212.dts | 46 + arch/arm/boot/dts/marvell/kirkwood-ds212j.dts | 40 + arch/arm/boot/dts/marvell/kirkwood-ds409.dts | 47 + arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts | 39 + arch/arm/boot/dts/marvell/kirkwood-ds411.dts | 55 + arch/arm/boot/dts/marvell/kirkwood-ds411j.dts | 47 + arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts | 47 + arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts | 190 + .../dts/marvell/kirkwood-guruplug-server-plus.dts | 133 + arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts | 146 + arch/arm/boot/dts/marvell/kirkwood-iconnect.dts | 195 + .../boot/dts/marvell/kirkwood-iomega_ix2_200.dts | 226 + arch/arm/boot/dts/marvell/kirkwood-is2.dts | 40 + arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi | 47 + arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts | 24 + arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts | 31 + arch/arm/boot/dts/marvell/kirkwood-l-50.dts | 438 ++ arch/arm/boot/dts/marvell/kirkwood-laplug.dts | 168 + .../dts/marvell/kirkwood-linkstation-6282.dtsi | 155 + .../dts/marvell/kirkwood-linkstation-duo-6281.dtsi | 149 + .../dts/marvell/kirkwood-linkstation-lsqvl.dts | 98 + .../boot/dts/marvell/kirkwood-linkstation-lsvl.dts | 20 + .../dts/marvell/kirkwood-linkstation-lswsxl.dts | 20 + .../dts/marvell/kirkwood-linkstation-lswvl.dts | 75 + .../dts/marvell/kirkwood-linkstation-lswxl.dts | 79 + .../arm/boot/dts/marvell/kirkwood-linkstation.dtsi | 164 + .../boot/dts/marvell/kirkwood-linksys-viper.dts | 241 + arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts | 20 + arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts | 20 + arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi | 231 + arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts | 216 + .../boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts | 179 + arch/arm/boot/dts/marvell/kirkwood-nas2big.dts | 139 + arch/arm/boot/dts/marvell/kirkwood-net2big.dts | 63 + arch/arm/boot/dts/marvell/kirkwood-net5big.dts | 169 + .../marvell/kirkwood-netgear_readynas_duo_v2.dts | 247 + .../marvell/kirkwood-netgear_readynas_nv+_v2.dts | 274 + arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi | 232 + arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi | 97 + arch/arm/boot/dts/marvell/kirkwood-ns2.dts | 40 + arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts | 35 + arch/arm/boot/dts/marvell/kirkwood-ns2max.dts | 59 + arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts | 60 + arch/arm/boot/dts/marvell/kirkwood-nsa310.dts | 139 + arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts | 115 + arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts | 259 + arch/arm/boot/dts/marvell/kirkwood-nsa320.dts | 219 + arch/arm/boot/dts/marvell/kirkwood-nsa325.dts | 232 + .../boot/dts/marvell/kirkwood-nsa3x0-common.dtsi | 158 + .../boot/dts/marvell/kirkwood-openblocks_a6.dts | 184 + .../boot/dts/marvell/kirkwood-openblocks_a7.dts | 209 + arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts | 39 + .../boot/dts/marvell/kirkwood-openrd-client.dts | 74 + .../boot/dts/marvell/kirkwood-openrd-ultimate.dts | 55 + arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi | 122 + arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts | 132 + .../dts/marvell/kirkwood-pogoplug-series-4.dts | 180 + arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts | 106 + arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts | 39 + .../arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts | 34 + arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi | 134 + arch/arm/boot/dts/marvell/kirkwood-rs212.dts | 51 + arch/arm/boot/dts/marvell/kirkwood-rs409.dts | 43 + arch/arm/boot/dts/marvell/kirkwood-rs411.dts | 43 + .../dts/marvell/kirkwood-sheevaplug-common.dtsi | 104 + .../boot/dts/marvell/kirkwood-sheevaplug-esata.dts | 42 + arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts | 42 + arch/arm/boot/dts/marvell/kirkwood-synology.dtsi | 855 +++ arch/arm/boot/dts/marvell/kirkwood-t5325.dts | 227 + arch/arm/boot/dts/marvell/kirkwood-topkick.dts | 216 + arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts | 56 + arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts | 58 + arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi | 114 + arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts | 16 + arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts | 19 + arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi | 71 + arch/arm/boot/dts/marvell/kirkwood.dtsi | 394 ++ arch/arm/boot/dts/marvell/mmp2-brownstone.dts | 192 + arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts | 277 + arch/arm/boot/dts/marvell/mmp2.dtsi | 516 ++ arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts | 151 + arch/arm/boot/dts/marvell/mmp3.dtsi | 608 ++ .../boot/dts/marvell/mvebu-linkstation-fan.dtsi | 72 + .../dts/marvell/mvebu-linkstation-gpio-simple.dtsi | 105 + arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts | 127 + .../boot/dts/marvell/orion5x-lacie-d2-network.dts | 234 + .../orion5x-lacie-ethernet-disk-mini-v2.dts | 170 + .../boot/dts/marvell/orion5x-linkstation-lschl.dts | 171 + .../boot/dts/marvell/orion5x-linkstation-lsgl.dts | 91 + .../dts/marvell/orion5x-linkstation-lswtgl.dts | 151 + arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi | 180 + arch/arm/boot/dts/marvell/orion5x-lswsgl.dts | 277 + .../marvell/orion5x-maxtor-shared-storage-2.dts | 176 + arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi | 44 + arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi | 40 + .../boot/dts/marvell/orion5x-netgear-wnr854t.dts | 252 + .../arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts | 173 + arch/arm/boot/dts/marvell/orion5x.dtsi | 236 + arch/arm/boot/dts/marvell/pxa168-aspenite.dts | 33 + arch/arm/boot/dts/marvell/pxa168.dtsi | 166 + arch/arm/boot/dts/marvell/pxa910-dkb.dts | 170 + arch/arm/boot/dts/marvell/pxa910.dtsi | 177 + arch/arm/boot/dts/mba6ulx.dtsi | 573 -- arch/arm/boot/dts/mediatek/Makefile | 15 + arch/arm/boot/dts/mediatek/mt2701-evb.dts | 253 + arch/arm/boot/dts/mediatek/mt2701-pinfunc.h | 727 +++ arch/arm/boot/dts/mediatek/mt2701.dtsi | 756 +++ arch/arm/boot/dts/mediatek/mt6323.dtsi | 269 + arch/arm/boot/dts/mediatek/mt6580-evbp1.dts | 32 + arch/arm/boot/dts/mediatek/mt6580.dtsi | 108 + .../dts/mediatek/mt6582-prestigio-pmt5008-3g.dts | 43 + arch/arm/boot/dts/mediatek/mt6582.dtsi | 128 + arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts | 33 + .../arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts | 30 + arch/arm/boot/dts/mediatek/mt6589.dtsi | 141 + arch/arm/boot/dts/mediatek/mt6592-evb.dts | 19 + arch/arm/boot/dts/mediatek/mt6592.dtsi | 137 + arch/arm/boot/dts/mediatek/mt7623.dtsi | 1313 ++++ arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts | 247 + arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts | 293 + arch/arm/boot/dts/mediatek/mt7623a.dtsi | 147 + .../boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts | 471 ++ arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts | 398 ++ arch/arm/boot/dts/mediatek/mt7623n.dtsi | 301 + arch/arm/boot/dts/mediatek/mt7629-rfb.dts | 275 + arch/arm/boot/dts/mediatek/mt7629.dtsi | 491 ++ arch/arm/boot/dts/mediatek/mt8127-moose.dts | 23 + arch/arm/boot/dts/mediatek/mt8127.dtsi | 163 + arch/arm/boot/dts/mediatek/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mediatek/mt8135.dtsi | 259 + arch/arm/boot/dts/meson.dtsi | 334 - arch/arm/boot/dts/meson6-atv1200.dts | 33 - arch/arm/boot/dts/meson6.dtsi | 73 - arch/arm/boot/dts/meson8-minix-neo-x8.dts | 97 - arch/arm/boot/dts/meson8.dtsi | 806 --- arch/arm/boot/dts/meson8b-ec100.dts | 479 -- arch/arm/boot/dts/meson8b-mxq.dts | 189 - arch/arm/boot/dts/meson8b-odroidc1.dts | 383 -- arch/arm/boot/dts/meson8b.dtsi | 781 --- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 293 - arch/arm/boot/dts/meson8m2.dtsi | 101 - arch/arm/boot/dts/microchip/Makefile | 108 + arch/arm/boot/dts/microchip/aks-cdu.dts | 122 + arch/arm/boot/dts/microchip/animeo_ip.dts | 195 + arch/arm/boot/dts/microchip/at91-ariag25.dts | 183 + arch/arm/boot/dts/microchip/at91-ariettag25.dts | 87 + arch/arm/boot/dts/microchip/at91-cosino.dtsi | 152 + .../boot/dts/microchip/at91-cosino_mega2560.dts | 75 + arch/arm/boot/dts/microchip/at91-dvk_som60.dts | 95 + .../arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi | 159 + .../boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi | 90 + arch/arm/boot/dts/microchip/at91-foxg20.dts | 168 + arch/arm/boot/dts/microchip/at91-gatwick.dts | 121 + arch/arm/boot/dts/microchip/at91-kizbox.dts | 190 + arch/arm/boot/dts/microchip/at91-kizbox2-2.dts | 26 + .../boot/dts/microchip/at91-kizbox2-common.dtsi | 256 + arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts | 309 + .../boot/dts/microchip/at91-kizbox3_common.dtsi | 371 ++ .../boot/dts/microchip/at91-kizboxmini-base.dts | 24 + .../boot/dts/microchip/at91-kizboxmini-common.dtsi | 168 + arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts | 26 + arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts | 49 + arch/arm/boot/dts/microchip/at91-linea.dtsi | 71 + arch/arm/boot/dts/microchip/at91-lmu5000.dts | 147 + arch/arm/boot/dts/microchip/at91-natte.dtsi | 244 + .../boot/dts/microchip/at91-nattis-2-natte-2.dts | 306 + arch/arm/boot/dts/microchip/at91-q5xr5.dts | 181 + arch/arm/boot/dts/microchip/at91-qil_a9260.dts | 213 + arch/arm/boot/dts/microchip/at91-sam9_l9260.dts | 133 + .../boot/dts/microchip/at91-sam9x60_curiosity.dts | 503 ++ arch/arm/boot/dts/microchip/at91-sam9x60ek.dts | 669 ++ .../arm/boot/dts/microchip/at91-sama5d27_som1.dtsi | 166 + .../boot/dts/microchip/at91-sama5d27_som1_ek.dts | 552 ++ .../boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | 386 ++ .../boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts | 269 + arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts | 790 +++ .../arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts | 435 ++ .../boot/dts/microchip/at91-sama5d2_xplained.dts | 745 +++ arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts | 307 + .../dts/microchip/at91-sama5d3_ksz9477_evb.dts | 214 + .../boot/dts/microchip/at91-sama5d3_xplained.dts | 406 ++ .../arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi | 136 + .../boot/dts/microchip/at91-sama5d4_ma5d4evk.dts | 164 + .../boot/dts/microchip/at91-sama5d4_xplained.dts | 298 + arch/arm/boot/dts/microchip/at91-sama5d4ek.dts | 323 + arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 834 +++ arch/arm/boot/dts/microchip/at91-smartkiz.dts | 107 + arch/arm/boot/dts/microchip/at91-som60.dtsi | 230 + arch/arm/boot/dts/microchip/at91-tse850-3.dts | 362 ++ arch/arm/boot/dts/microchip/at91-vinco.dts | 231 + arch/arm/boot/dts/microchip/at91-wb45n.dts | 61 + arch/arm/boot/dts/microchip/at91-wb45n.dtsi | 166 + arch/arm/boot/dts/microchip/at91-wb50n.dts | 102 + arch/arm/boot/dts/microchip/at91-wb50n.dtsi | 194 + arch/arm/boot/dts/microchip/at91rm9200.dtsi | 729 +++ arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi | 16 + arch/arm/boot/dts/microchip/at91rm9200ek.dts | 147 + arch/arm/boot/dts/microchip/at91sam9260.dtsi | 796 +++ arch/arm/boot/dts/microchip/at91sam9260ek.dts | 188 + arch/arm/boot/dts/microchip/at91sam9261.dtsi | 667 ++ arch/arm/boot/dts/microchip/at91sam9261ek.dts | 245 + arch/arm/boot/dts/microchip/at91sam9263.dtsi | 839 +++ arch/arm/boot/dts/microchip/at91sam9263ek.dts | 262 + arch/arm/boot/dts/microchip/at91sam9g15.dtsi | 28 + arch/arm/boot/dts/microchip/at91sam9g15ek.dts | 36 + arch/arm/boot/dts/microchip/at91sam9g20.dtsi | 49 + arch/arm/boot/dts/microchip/at91sam9g20ek.dts | 28 + arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts | 54 + .../boot/dts/microchip/at91sam9g20ek_common.dtsi | 309 + .../at91sam9g25-gardena-smart-gateway.dts | 158 + arch/arm/boot/dts/microchip/at91sam9g25.dtsi | 34 + arch/arm/boot/dts/microchip/at91sam9g25ek.dts | 65 + arch/arm/boot/dts/microchip/at91sam9g35.dtsi | 33 + arch/arm/boot/dts/microchip/at91sam9g35ek.dts | 41 + arch/arm/boot/dts/microchip/at91sam9g45.dtsi | 1023 +++ arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts | 393 ++ arch/arm/boot/dts/microchip/at91sam9n12.dtsi | 799 +++ arch/arm/boot/dts/microchip/at91sam9n12ek.dts | 285 + arch/arm/boot/dts/microchip/at91sam9rl.dtsi | 861 +++ arch/arm/boot/dts/microchip/at91sam9rlek.dts | 276 + arch/arm/boot/dts/microchip/at91sam9x25.dtsi | 35 + arch/arm/boot/dts/microchip/at91sam9x25ek.dts | 35 + arch/arm/boot/dts/microchip/at91sam9x35.dtsi | 34 + arch/arm/boot/dts/microchip/at91sam9x35ek.dts | 41 + arch/arm/boot/dts/microchip/at91sam9x5.dtsi | 978 +++ arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi | 56 + arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi | 62 + arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi | 147 + arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi | 57 + arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi | 45 + arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi | 61 + arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi | 144 + arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi | 96 + arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi | 167 + arch/arm/boot/dts/microchip/at91sam9xe.dtsi | 26 + arch/arm/boot/dts/microchip/ethernut5.dts | 118 + arch/arm/boot/dts/microchip/evk-pro3.dts | 58 + arch/arm/boot/dts/microchip/ge863-pro3.dtsi | 77 + .../lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 94 + .../lan966x-kontron-kswitch-d10-mmt-8g.dts | 39 + .../microchip/lan966x-kontron-kswitch-d10-mmt.dtsi | 203 + arch/arm/boot/dts/microchip/lan966x-pcb8290.dts | 195 + arch/arm/boot/dts/microchip/lan966x-pcb8291.dts | 147 + arch/arm/boot/dts/microchip/lan966x-pcb8309.dts | 230 + arch/arm/boot/dts/microchip/lan966x.dtsi | 615 ++ arch/arm/boot/dts/microchip/mpa1600.dts | 79 + arch/arm/boot/dts/microchip/pm9g45.dts | 185 + arch/arm/boot/dts/microchip/sam9x60.dtsi | 1353 ++++ arch/arm/boot/dts/microchip/sama5d2-pinfunc.h | 881 +++ arch/arm/boot/dts/microchip/sama5d2.dtsi | 1166 ++++ arch/arm/boot/dts/microchip/sama5d29.dtsi | 16 + arch/arm/boot/dts/microchip/sama5d3.dtsi | 1126 ++++ arch/arm/boot/dts/microchip/sama5d31.dtsi | 15 + arch/arm/boot/dts/microchip/sama5d31ek.dts | 52 + arch/arm/boot/dts/microchip/sama5d33.dtsi | 13 + arch/arm/boot/dts/microchip/sama5d33ek.dts | 45 + arch/arm/boot/dts/microchip/sama5d34.dtsi | 15 + arch/arm/boot/dts/microchip/sama5d34ek.dts | 62 + arch/arm/boot/dts/microchip/sama5d35.dtsi | 17 + arch/arm/boot/dts/microchip/sama5d35ek.dts | 56 + arch/arm/boot/dts/microchip/sama5d36.dtsi | 19 + arch/arm/boot/dts/microchip/sama5d36ek.dts | 54 + arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts | 50 + arch/arm/boot/dts/microchip/sama5d3_can.dtsi | 57 + arch/arm/boot/dts/microchip/sama5d3_emac.dtsi | 48 + arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi | 78 + arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi | 197 + arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi | 49 + arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi | 31 + arch/arm/boot/dts/microchip/sama5d3_uart.dtsi | 65 + arch/arm/boot/dts/microchip/sama5d3xcm.dtsi | 139 + arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi | 193 + arch/arm/boot/dts/microchip/sama5d3xdm.dtsi | 40 + arch/arm/boot/dts/microchip/sama5d3xmb.dtsi | 208 + arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi | 264 + arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi | 25 + arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi | 47 + arch/arm/boot/dts/microchip/sama5d4.dtsi | 1453 +++++ arch/arm/boot/dts/microchip/sama7g5-pinfunc.h | 923 +++ arch/arm/boot/dts/microchip/sama7g5.dtsi | 1016 +++ arch/arm/boot/dts/microchip/tny_a9260.dts | 14 + arch/arm/boot/dts/microchip/tny_a9260_common.dtsi | 112 + arch/arm/boot/dts/microchip/tny_a9263.dts | 126 + arch/arm/boot/dts/microchip/tny_a9g20.dts | 14 + arch/arm/boot/dts/microchip/usb_a9260.dts | 31 + arch/arm/boot/dts/microchip/usb_a9260_common.dtsi | 146 + arch/arm/boot/dts/microchip/usb_a9263.dts | 174 + arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi | 95 + arch/arm/boot/dts/microchip/usb_a9g20.dts | 13 + arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi | 27 + arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts | 30 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 - arch/arm/boot/dts/milbeaut-m10v.dtsi | 104 - arch/arm/boot/dts/mmp2-brownstone.dts | 192 - arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts | 277 - arch/arm/boot/dts/mmp2.dtsi | 516 -- arch/arm/boot/dts/mmp3-dell-ariel.dts | 151 - arch/arm/boot/dts/mmp3.dtsi | 608 -- arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi | 272 - arch/arm/boot/dts/motorola-mapphone-common.dtsi | 737 --- arch/arm/boot/dts/moxa/Makefile | 3 + arch/arm/boot/dts/moxa/moxart-uc7112lx.dts | 116 + arch/arm/boot/dts/moxa/moxart.dtsi | 151 + arch/arm/boot/dts/moxart-uc7112lx.dts | 116 - arch/arm/boot/dts/moxart.dtsi | 151 - arch/arm/boot/dts/mpa1600.dts | 79 - arch/arm/boot/dts/mps2-an385.dts | 92 - arch/arm/boot/dts/mps2-an399.dts | 92 - arch/arm/boot/dts/mps2.dtsi | 252 - .../boot/dts/mstar-infinity-breadbee-common.dtsi | 49 - .../dts/mstar-infinity-msc313-breadbee_crust.dts | 26 - arch/arm/boot/dts/mstar-infinity-msc313.dtsi | 14 - arch/arm/boot/dts/mstar-infinity.dtsi | 52 - .../boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi | 20 - ...tar-infinity2m-ssd202d-100ask-dongshanpione.dts | 25 - .../dts/mstar-infinity2m-ssd202d-miyoo-mini.dts | 25 - .../dts/mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 - .../boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 25 - ...y2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts | 23 - ...infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi | 28 - arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 - arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 17 - arch/arm/boot/dts/mstar-infinity2m.dtsi | 39 - .../boot/dts/mstar-infinity3-msc313e-breadbee.dts | 26 - arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi | 14 - arch/arm/boot/dts/mstar-infinity3.dtsi | 69 - .../dts/mstar-mercury5-ssc8336n-midrived08.dts | 25 - arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi | 14 - arch/arm/boot/dts/mstar-mercury5.dtsi | 11 - arch/arm/boot/dts/mstar-v7.dtsi | 192 - arch/arm/boot/dts/mt2701-evb.dts | 253 - arch/arm/boot/dts/mt2701-pinfunc.h | 727 --- arch/arm/boot/dts/mt2701.dtsi | 756 --- arch/arm/boot/dts/mt6323.dtsi | 269 - arch/arm/boot/dts/mt6580-evbp1.dts | 32 - arch/arm/boot/dts/mt6580.dtsi | 108 - arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts | 43 - arch/arm/boot/dts/mt6582.dtsi | 128 - arch/arm/boot/dts/mt6589-aquaris5.dts | 33 - arch/arm/boot/dts/mt6589-fairphone-fp1.dts | 30 - arch/arm/boot/dts/mt6589.dtsi | 141 - arch/arm/boot/dts/mt6592-evb.dts | 19 - arch/arm/boot/dts/mt6592.dtsi | 137 - arch/arm/boot/dts/mt7623.dtsi | 1313 ---- arch/arm/boot/dts/mt7623a-rfb-emmc.dts | 247 - arch/arm/boot/dts/mt7623a-rfb-nand.dts | 293 - arch/arm/boot/dts/mt7623a.dtsi | 147 - arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 471 -- arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 398 -- arch/arm/boot/dts/mt7623n.dtsi | 301 - arch/arm/boot/dts/mt7629-rfb.dts | 275 - arch/arm/boot/dts/mt7629.dtsi | 491 -- arch/arm/boot/dts/mt8127-moose.dts | 23 - arch/arm/boot/dts/mt8127.dtsi | 163 - arch/arm/boot/dts/mt8135-evbp1.dts | 193 - arch/arm/boot/dts/mt8135.dtsi | 259 - arch/arm/boot/dts/mvebu-linkstation-fan.dtsi | 72 - .../boot/dts/mvebu-linkstation-gpio-simple.dtsi | 105 - arch/arm/boot/dts/mxs-pinfunc.h | 25 - arch/arm/boot/dts/nspire-classic.dtsi | 88 - arch/arm/boot/dts/nspire-clp.dts | 41 - arch/arm/boot/dts/nspire-cx.dts | 125 - arch/arm/boot/dts/nspire-tp.dts | 40 - arch/arm/boot/dts/nspire.dtsi | 203 - arch/arm/boot/dts/nspire/Makefile | 5 + arch/arm/boot/dts/nspire/nspire-classic.dtsi | 88 + arch/arm/boot/dts/nspire/nspire-clp.dts | 41 + arch/arm/boot/dts/nspire/nspire-cx.dts | 125 + arch/arm/boot/dts/nspire/nspire-tp.dts | 40 + arch/arm/boot/dts/nspire/nspire.dtsi | 203 + arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 1123 ---- arch/arm/boot/dts/nuvoton-npcm730-gbs.dts | 1135 ---- arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi | 477 -- arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 490 -- arch/arm/boot/dts/nuvoton-npcm730-kudo.dts | 826 --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 - arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 404 -- arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 - .../dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi | 517 -- .../boot/dts/nuvoton-npcm750-runbmc-olympus.dts | 1052 --- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 62 - .../dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 111 - arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 493 -- arch/arm/boot/dts/nuvoton/Makefile | 9 + .../boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 1123 ++++ arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts | 1135 ++++ .../boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi | 477 ++ arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts | 490 ++ arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts | 826 +++ arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi | 44 + arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts | 404 ++ .../dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi | 157 + .../nuvoton-npcm750-runbmc-olympus-pincfg.dtsi | 517 ++ .../dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts | 1052 +++ arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi | 62 + .../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 111 + arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 493 ++ arch/arm/boot/dts/nvidia/Makefile | 43 + arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 807 +++ arch/arm/boot/dts/nvidia/tegra114-dalmore.dts | 1287 ++++ arch/arm/boot/dts/nvidia/tegra114-roth.dts | 1108 ++++ arch/arm/boot/dts/nvidia/tegra114-tn7.dts | 336 + arch/arm/boot/dts/nvidia/tegra114.dtsi | 850 +++ arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi | 1487 +++++ arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts | 255 + .../boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts | 257 + arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi | 2076 ++++++ arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi | 2068 ++++++ .../boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi | 2443 +++++++ arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts | 2080 ++++++ .../arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi | 6694 ++++++++++++++++++++ arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts | 17 + arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts | 1348 ++++ .../boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi | 2071 ++++++ arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts | 1346 ++++ arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi | 836 +++ .../boot/dts/nvidia/tegra124-peripherals-opp.dtsi | 424 ++ arch/arm/boot/dts/nvidia/tegra124-venice2.dts | 1256 ++++ arch/arm/boot/dts/nvidia/tegra124.dtsi | 1366 ++++ .../boot/dts/nvidia/tegra20-acer-a500-picasso.dts | 1525 +++++ arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts | 1291 ++++ .../boot/dts/nvidia/tegra20-colibri-eval-v3.dts | 262 + arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts | 244 + arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi | 776 +++ .../boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi | 165 + arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi | 253 + arch/arm/boot/dts/nvidia/tegra20-harmony.dts | 761 +++ arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts | 132 + arch/arm/boot/dts/nvidia/tegra20-paz00.dts | 721 +++ .../boot/dts/nvidia/tegra20-peripherals-opp.dtsi | 1022 +++ arch/arm/boot/dts/nvidia/tegra20-plutux.dts | 97 + arch/arm/boot/dts/nvidia/tegra20-seaboard.dts | 920 +++ arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi | 520 ++ arch/arm/boot/dts/nvidia/tegra20-tec.dts | 106 + arch/arm/boot/dts/nvidia/tegra20-trimslice.dts | 475 ++ arch/arm/boot/dts/nvidia/tegra20-ventana.dts | 755 +++ arch/arm/boot/dts/nvidia/tegra20.dtsi | 1061 ++++ arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts | 248 + .../boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts | 266 + arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi | 1202 ++++ arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi | 1185 ++++ .../boot/dts/nvidia/tegra30-asus-lvds-display.dtsi | 63 + .../nvidia/tegra30-asus-nexus7-grouper-E1565.dts | 9 + .../nvidia/tegra30-asus-nexus7-grouper-PM269.dts | 9 + .../nvidia/tegra30-asus-nexus7-grouper-common.dtsi | 1320 ++++ .../tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 194 + ...tegra30-asus-nexus7-grouper-memory-timings.dtsi | 1577 +++++ .../tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 159 + .../dts/nvidia/tegra30-asus-nexus7-grouper.dtsi | 148 + .../nvidia/tegra30-asus-nexus7-tilapia-E1565.dts | 9 + ...tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 325 + .../dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi | 233 + arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts | 644 ++ arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts | 1032 +++ arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts | 1104 ++++ arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts | 840 +++ .../nvidia/tegra30-asus-transformer-common.dtsi | 1788 ++++++ arch/arm/boot/dts/nvidia/tegra30-beaver.dts | 2138 +++++++ arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts | 83 + arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts | 93 + arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi | 711 +++ .../boot/dts/nvidia/tegra30-colibri-eval-v3.dts | 198 + arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi | 1064 ++++ .../boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi | 289 + arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi | 499 ++ arch/arm/boot/dts/nvidia/tegra30-ouya.dts | 4795 ++++++++++++++ .../boot/dts/nvidia/tegra30-pegatron-chagall.dts | 2858 +++++++++ .../boot/dts/nvidia/tegra30-peripherals-opp.dtsi | 1648 +++++ arch/arm/boot/dts/nvidia/tegra30.dtsi | 1348 ++++ arch/arm/boot/dts/nxp/Makefile | 6 + arch/arm/boot/dts/nxp/imx/Makefile | 388 ++ arch/arm/boot/dts/nxp/imx/e60k02.dtsi | 320 + arch/arm/boot/dts/nxp/imx/e70k02.dtsi | 330 + arch/arm/boot/dts/nxp/imx/imx1-ads.dts | 135 + arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts | 124 + arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h | 296 + arch/arm/boot/dts/nxp/imx/imx1.dtsi | 276 + .../boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi | 66 + .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 65 + .../imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 37 + .../imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 37 + .../nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts | 174 + arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts | 108 + arch/arm/boot/dts/nxp/imx/imx25-pdk.dts | 313 + arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h | 652 ++ arch/arm/boot/dts/nxp/imx/imx25.dtsi | 637 ++ arch/arm/boot/dts/nxp/imx/imx27-apf27.dts | 112 + arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts | 256 + .../boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi | 284 + .../nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts | 266 + arch/arm/boot/dts/nxp/imx/imx27-pdk.dts | 191 + .../dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts | 162 + .../dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi | 97 + .../boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts | 319 + .../boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi | 344 + arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h | 474 ++ arch/arm/boot/dts/nxp/imx/imx27.dtsi | 593 ++ arch/arm/boot/dts/nxp/imx/imx31-bug.dts | 22 + arch/arm/boot/dts/nxp/imx/imx31-lite.dts | 178 + arch/arm/boot/dts/nxp/imx/imx31.dtsi | 371 ++ .../boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi | 89 + .../nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts | 156 + arch/arm/boot/dts/nxp/imx/imx35-pdk.dts | 62 + arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h | 966 +++ arch/arm/boot/dts/nxp/imx/imx35.dtsi | 413 ++ arch/arm/boot/dts/nxp/imx/imx50-evk.dts | 104 + arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts | 287 + arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h | 919 +++ arch/arm/boot/dts/nxp/imx/imx50.dtsi | 499 ++ arch/arm/boot/dts/nxp/imx/imx51-apf51.dts | 84 + arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts | 217 + arch/arm/boot/dts/nxp/imx/imx51-babbage.dts | 726 +++ .../dts/nxp/imx/imx51-digi-connectcore-jsk.dts | 126 + .../dts/nxp/imx/imx51-digi-connectcore-som.dtsi | 376 ++ .../boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi | 92 + .../nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts | 274 + arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h | 768 +++ arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts | 331 + arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts | 894 +++ arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts | 457 ++ arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts | 471 ++ arch/arm/boot/dts/nxp/imx/imx51.dtsi | 663 ++ arch/arm/boot/dts/nxp/imx/imx53-ard.dts | 179 + arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts | 295 + arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts | 146 + arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts | 52 + arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi | 197 + arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi | 132 + arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts | 371 ++ arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts | 517 ++ arch/arm/boot/dts/nxp/imx/imx53-mba53.dts | 249 + arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h | 1189 ++++ arch/arm/boot/dts/nxp/imx/imx53-ppd.dts | 1122 ++++ arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi | 387 ++ arch/arm/boot/dts/nxp/imx/imx53-qsb.dts | 111 + arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts | 149 + arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts | 357 ++ arch/arm/boot/dts/nxp/imx/imx53-smd.dts | 346 + arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi | 289 + arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts | 351 + arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts | 262 + arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi | 584 ++ arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts | 225 + arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts | 153 + .../arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi | 267 + arch/arm/boot/dts/nxp/imx/imx53.dtsi | 859 +++ .../boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi | 561 ++ arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi | 369 ++ arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts | 578 ++ arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts | 18 + .../boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts | 158 + .../boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts | 98 + .../arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts | 84 + .../arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts | 74 + arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts | 32 + arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts | 32 + arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts | 30 + arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts | 30 + arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts | 32 + arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi | 413 ++ arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi | 57 + arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts | 114 + .../boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts | 158 + .../boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts | 46 + arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts | 153 + .../dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts | 52 + .../boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts | 51 + arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts | 51 + arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts | 23 + arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts | 20 + .../boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts | 388 ++ arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts | 71 + arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts | 71 + arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts | 71 + arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts | 14 + .../nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts | 53 + .../dts/nxp/imx/imx6dl-hummingboard-som-v15.dts | 52 + arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts | 52 + .../nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts | 55 + .../dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts | 54 + arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts | 53 + arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts | 25 + arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts | 15 + arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts | 32 + .../boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi | 12 + arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts | 483 ++ arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts | 496 ++ arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi | 22 + arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts | 21 + arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts | 21 + arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts | 15 + .../dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts | 67 + arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts | 13 + .../arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi | 17 + arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h | 1088 ++++ arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts | 396 ++ arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts | 573 ++ arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts | 860 +++ arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts | 186 + arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts | 612 ++ arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi | 612 ++ arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts | 27 + arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts | 597 ++ arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts | 28 + arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts | 51 + arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts | 106 + arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts | 54 + arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi | 16 + arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi | 16 + arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts | 56 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts | 79 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts | 70 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts | 86 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts | 50 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts | 82 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts | 50 + arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts | 360 ++ arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts | 14 + .../boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts | 19 + .../boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts | 19 + arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts | 19 + arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi | 648 ++ arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts | 58 + arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts | 54 + arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts | 58 + arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts | 54 + arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts | 42 + arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts | 58 + .../arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi | 615 ++ arch/arm/boot/dts/nxp/imx/imx6dl.dtsi | 397 ++ arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts | 172 + .../boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 37 + .../boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts | 278 + arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts | 182 + arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts | 22 + arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts | 226 + arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts | 157 + arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts | 156 + arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 295 + arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi | 661 ++ arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts | 779 +++ arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi | 409 ++ arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts | 491 ++ .../dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts | 60 + .../arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts | 59 + arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts | 59 + arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts | 23 + arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts | 25 + .../imx/imx6q-display5-tianma-tm070-1280x768.dts | 51 + arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi | 596 ++ arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts | 481 ++ arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts | 139 + arch/arm/boot/dts/nxp/imx/imx6q-ds.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6q-evi.dts | 518 ++ arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts | 174 + arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts | 75 + arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts | 75 + arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts | 510 ++ arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts | 177 + arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts | 59 + arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts | 59 + arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6q-h100.dts | 382 ++ .../nxp/imx/imx6q-hummingboard-emmc-som-v15.dts | 61 + .../dts/nxp/imx/imx6q-hummingboard-som-v15.dts | 60 + arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts | 60 + .../nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts | 63 + .../dts/nxp/imx/imx6q-hummingboard2-som-v15.dts | 62 + arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts | 61 + arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts | 33 + arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts | 44 + arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts | 43 + arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts | 19 + arch/arm/boot/dts/nxp/imx/imx6q-icore.dts | 57 + .../arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi | 35 + arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts | 23 + arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi | 434 ++ arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts | 130 + arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts | 417 ++ arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi | 44 + arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts | 20 + arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts | 20 + arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts | 471 ++ arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts | 19 + arch/arm/boot/dts/nxp/imx/imx6q-novena.dts | 803 +++ .../dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts | 75 + .../dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts | 75 + arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts | 21 + arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi | 17 + arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts | 17 + arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h | 1044 +++ arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts | 695 ++ arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts | 543 ++ arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts | 196 + arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts | 31 + arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts | 24 + arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts | 23 + arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts | 93 + arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts | 37 + arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts | 128 + .../dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts | 133 + arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts | 54 + arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts | 407 ++ arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi | 16 + arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi | 15 + arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts | 59 + arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts | 60 + .../boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts | 79 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts | 54 + .../boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts | 110 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts | 86 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts | 86 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts | 58 + arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts | 355 ++ .../boot/dts/nxp/imx/imx6q-var-dt6customboard.dts | 235 + arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts | 14 + .../arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts | 23 + .../arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts | 23 + arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts | 23 + arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts | 58 + arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts | 58 + arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts | 20 + arch/arm/boot/dts/nxp/imx/imx6q.dtsi | 553 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi | 1371 ++++ arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi | 152 + arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi | 451 ++ .../arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi | 408 ++ .../boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi | 637 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi | 1309 ++++ arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi | 270 + .../boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi | 201 + arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi | 143 + arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi | 335 + .../boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi | 69 + arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi | 850 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi | 458 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi | 177 + arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi | 834 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi | 638 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi | 795 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi | 784 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi | 877 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi | 695 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi | 519 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi | 738 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi | 931 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi | 793 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi | 820 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi | 536 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi | 664 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi | 604 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi | 498 ++ .../arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi | 368 ++ .../dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi | 72 + .../boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi | 577 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi | 32 + arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi | 466 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi | 431 ++ .../boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 821 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi | 592 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi | 36 + arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi | 55 + arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi | 583 ++ .../boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi | 849 +++ .../boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi | 736 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi | 693 ++ .../dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 + .../nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi | 71 + .../nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 85 + arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi | 412 ++ .../boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi | 177 + .../boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi | 466 ++ .../dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 311 + arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi | 45 + arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi | 37 + arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi | 54 + arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi | 31 + arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi | 627 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi | 175 + arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi | 367 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 864 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi | 748 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 851 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi | 256 + .../boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi | 79 + arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi | 491 ++ .../boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi | 99 + arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi | 160 + arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi | 144 + arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi | 70 + arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi | 171 + arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi | 158 + arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi | 215 + arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi | 55 + arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi | 34 + arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi | 479 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 594 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi | 251 + arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi | 286 + arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi | 96 + arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 792 +++ arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi | 327 + arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi | 504 ++ .../boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi | 128 + arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi | 712 +++ .../boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi | 36 + .../boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi | 35 + .../boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi | 193 + arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi | 378 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi | 1142 ++++ arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 1393 ++++ arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts | 22 + .../arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts | 18 + .../dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts | 75 + arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts | 557 ++ arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 60 + arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts | 63 + arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi | 16 + .../arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts | 86 + .../arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts | 57 + arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts | 90 + arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts | 14 + .../boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts | 23 + .../boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts | 58 + .../boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts | 58 + arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts | 25 + arch/arm/boot/dts/nxp/imx/imx6qp.dtsi | 120 + arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts | 30 + arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts | 658 ++ arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts | 555 ++ arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h | 1073 ++++ .../boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts | 634 ++ arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts | 340 + arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts | 490 ++ .../arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts | 356 ++ arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts | 234 + arch/arm/boot/dts/nxp/imx/imx6sl.dtsi | 1008 +++ arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts | 643 ++ arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts | 342 + .../arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts | 346 + arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h | 880 +++ arch/arm/boot/dts/nxp/imx/imx6sll.dtsi | 839 +++ arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts | 603 ++ arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h | 1668 +++++ arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts | 557 ++ arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts | 48 + arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts | 169 + arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts | 30 + arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts | 155 + arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 718 +++ .../dts/nxp/imx/imx6sx-softing-vining-2000.dts | 587 ++ .../arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts | 33 + .../boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts | 26 + arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts | 41 + arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi | 482 ++ arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 1469 +++++ arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi | 651 ++ .../boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts | 200 + .../arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts | 428 ++ arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi | 270 + arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts | 447 ++ .../boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi | 148 + .../dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi | 327 + arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi | 387 ++ arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts | 103 + .../boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi | 405 ++ arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts | 16 + .../boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi | 137 + arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi | 14 + arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts | 151 + arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi | 83 + arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi | 6 + arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts | 41 + .../dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi | 186 + .../nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts | 94 + .../nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts | 95 + .../dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi | 150 + .../nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi | 57 + .../nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 90 + arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi | 299 + arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts | 52 + arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts | 100 + arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts | 97 + arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi | 453 ++ arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h | 959 +++ arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts | 353 ++ .../boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi | 211 + .../boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts | 55 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi | 37 + .../boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts | 15 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi | 71 + .../boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts | 15 + arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi | 71 + .../boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi | 43 + .../boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi | 48 + arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts | 53 + arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts | 68 + .../boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts | 271 + arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 947 +++ arch/arm/boot/dts/nxp/imx/imx6ul.dtsi | 1124 ++++ arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts | 18 + .../arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts | 60 + .../boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi | 147 + .../dts/nxp/imx/imx6ull-colibri-emmc-aster.dts | 17 + .../dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts | 17 + .../dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts | 17 + .../boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts | 17 + .../dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi | 187 + .../boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts | 38 + .../boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi | 123 + .../boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts | 105 + .../boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi | 27 + arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts | 40 + .../arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi | 134 + .../boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi | 161 + .../dts/nxp/imx/imx6ull-colibri-wifi-aster.dts | 60 + .../dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts | 38 + .../dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts | 89 + .../boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts | 40 + .../arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi | 189 + arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi | 773 +++ arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts | 99 + arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts | 222 + .../arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts | 101 + .../dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi | 97 + arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi | 631 ++ .../boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts | 359 ++ arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi | 260 + arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts | 456 ++ arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts | 15 + arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi | 13 + .../dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts | 19 + .../boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi | 238 + arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi | 6 + arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts | 42 + .../dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi | 24 + .../nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts | 94 + .../nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts | 95 + .../nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts | 46 + .../nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi | 26 + .../nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 + .../nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 + .../arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi | 31 + .../boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts | 20 + .../arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi | 587 ++ arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h | 26 + arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h | 87 + .../boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi | 852 +++ .../boot/dts/nxp/imx/imx6ull-tarragon-master.dts | 82 + .../boot/dts/nxp/imx/imx6ull-tarragon-micro.dts | 10 + .../boot/dts/nxp/imx/imx6ull-tarragon-slave.dts | 32 + .../boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts | 64 + .../boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts | 15 + arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi | 76 + .../dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts | 15 + arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi | 76 + arch/arm/boot/dts/nxp/imx/imx6ull.dtsi | 95 + arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts | 22 + arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts | 150 + arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi | 36 + arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi | 80 + .../arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi | 111 + .../arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi | 113 + arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi | 109 + arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi | 1142 ++++ arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi | 640 ++ arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi | 292 + arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts | 294 + arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts | 41 + .../boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts | 23 + .../dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts | 22 + .../dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts | 22 + .../boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts | 22 + arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi | 62 + .../arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts | 57 + .../arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts | 84 + arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts | 57 + arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi | 35 + .../dts/nxp/imx/imx7d-flex-concentrator-mfg.dts | 25 + .../boot/dts/nxp/imx/imx7d-flex-concentrator.dts | 313 + arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts | 113 + arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts | 375 ++ arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts | 699 ++ arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts | 87 + arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts | 105 + arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts | 84 + arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 93 + arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi | 675 ++ arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h | 1154 ++++ arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts | 595 ++ arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts | 42 + arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts | 43 + arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts | 36 + arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts | 904 +++ arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts | 468 ++ arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi | 15 + arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts | 357 ++ arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts | 923 +++ arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 229 + arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts | 36 + .../arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts | 51 + .../arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts | 78 + arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts | 51 + arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi | 19 + arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts | 18 + arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi | 11 + arch/arm/boot/dts/nxp/imx/imx7s-warp.dts | 500 ++ arch/arm/boot/dts/nxp/imx/imx7s.dtsi | 1290 ++++ arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts | 79 + arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts | 133 + arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h | 478 ++ arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi | 466 ++ arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 + arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 +++ arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 + arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 +++++ arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi | 573 ++ arch/arm/boot/dts/nxp/lpc/Makefile | 9 + arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 537 ++ arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 273 + arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 236 + arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 508 ++ arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 + arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 481 ++ arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 39 + .../arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 623 ++ arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 619 ++ arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 43 + arch/arm/boot/dts/nxp/ls/Makefile | 7 + arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts | 227 + arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts | 237 + arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts | 326 + arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts | 295 + arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts | 240 + arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 987 +++ arch/arm/boot/dts/nxp/mxs/Makefile | 31 + arch/arm/boot/dts/nxp/mxs/imx23-evk.dts | 144 + arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts | 131 + arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h | 327 + arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts | 207 + arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts | 76 + arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts | 180 + arch/arm/boot/dts/nxp/mxs/imx23.dtsi | 634 ++ arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts | 72 + arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts | 217 + arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts | 232 + arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts | 131 + arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts | 83 + arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts | 418 ++ arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts | 155 + arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts | 109 + arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts | 161 + arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts | 128 + arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts | 38 + .../boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts | 69 + arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts | 63 + arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts | 170 + arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts | 139 + .../boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts | 64 + .../boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts | 43 + .../boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi | 323 + arch/arm/boot/dts/nxp/mxs/imx28-evk.dts | 352 + arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi | 170 + arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi | 50 + arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts | 258 + arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts | 263 + arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h | 500 ++ arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts | 157 + arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts | 66 + arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts | 677 ++ arch/arm/boot/dts/nxp/mxs/imx28-xea.dts | 99 + arch/arm/boot/dts/nxp/mxs/imx28.dtsi | 1334 ++++ arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h | 25 + arch/arm/boot/dts/nxp/vf/Makefile | 16 + arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi | 152 + arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi | 350 + arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts | 18 + arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi | 69 + arch/arm/boot/dts/nxp/vf/vf500.dtsi | 64 + arch/arm/boot/dts/nxp/vf/vf610-bk4.dts | 537 ++ arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts | 13 + arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi | 22 + arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts | 90 + arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h | 856 +++ arch/arm/boot/dts/nxp/vf/vf610-twr.dts | 373 ++ arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts | 368 ++ arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts | 444 ++ arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts | 466 ++ arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi | 450 ++ arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts | 876 +++ arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts | 379 ++ arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts | 325 + arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts | 372 ++ arch/arm/boot/dts/nxp/vf/vf610.dtsi | 20 + arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 63 + arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 90 + arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 57 + arch/arm/boot/dts/nxp/vf/vfxxx.dtsi | 751 +++ arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi | 55 - arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi | 59 - arch/arm/boot/dts/omap-zoom-common.dtsi | 92 - arch/arm/boot/dts/omap2.dtsi | 334 - arch/arm/boot/dts/omap2420-clocks.dtsi | 267 - arch/arm/boot/dts/omap2420-h4.dts | 63 - arch/arm/boot/dts/omap2420-n800.dts | 9 - arch/arm/boot/dts/omap2420-n810-wimax.dts | 9 - arch/arm/boot/dts/omap2420-n810.dts | 75 - arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 111 - arch/arm/boot/dts/omap2420.dtsi | 262 - arch/arm/boot/dts/omap2430-clocks.dtsi | 341 - arch/arm/boot/dts/omap2430-sdp.dts | 70 - arch/arm/boot/dts/omap2430.dtsi | 366 -- arch/arm/boot/dts/omap24xx-clocks.dtsi | 1241 ---- arch/arm/boot/dts/omap3-beagle-ab4.dts | 47 - arch/arm/boot/dts/omap3-beagle-xm-ab.dts | 13 - arch/arm/boot/dts/omap3-beagle-xm.dts | 419 -- arch/arm/boot/dts/omap3-beagle.dts | 436 -- arch/arm/boot/dts/omap3-cm-t3517.dts | 158 - arch/arm/boot/dts/omap3-cm-t3530.dts | 60 - arch/arm/boot/dts/omap3-cm-t3730.dts | 98 - arch/arm/boot/dts/omap3-cm-t3x.dtsi | 326 - arch/arm/boot/dts/omap3-cm-t3x30.dtsi | 131 - arch/arm/boot/dts/omap3-cpu-thermal.dtsi | 38 - arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 392 -- arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi | 73 - arch/arm/boot/dts/omap3-devkit8000-lcd43.dts | 34 - arch/arm/boot/dts/omap3-devkit8000-lcd70.dts | 34 - arch/arm/boot/dts/omap3-devkit8000.dts | 16 - arch/arm/boot/dts/omap3-echo.dts | 724 --- arch/arm/boot/dts/omap3-evm-37xx.dts | 107 - arch/arm/boot/dts/omap3-evm-common.dtsi | 198 - arch/arm/boot/dts/omap3-evm-processor-common.dtsi | 224 - arch/arm/boot/dts/omap3-evm.dts | 86 - arch/arm/boot/dts/omap3-gta04.dtsi | 893 --- arch/arm/boot/dts/omap3-gta04a3.dts | 45 - arch/arm/boot/dts/omap3-gta04a4.dts | 10 - arch/arm/boot/dts/omap3-gta04a5.dts | 152 - arch/arm/boot/dts/omap3-gta04a5one.dts | 113 - arch/arm/boot/dts/omap3-ha-common.dtsi | 85 - arch/arm/boot/dts/omap3-ha-lcd.dts | 162 - arch/arm/boot/dts/omap3-ha.dts | 25 - arch/arm/boot/dts/omap3-igep.dtsi | 247 - arch/arm/boot/dts/omap3-igep0020-common.dtsi | 261 - arch/arm/boot/dts/omap3-igep0020-rev-f.dts | 59 - arch/arm/boot/dts/omap3-igep0020.dts | 47 - arch/arm/boot/dts/omap3-igep0030-common.dtsi | 103 - arch/arm/boot/dts/omap3-igep0030-rev-g.dts | 81 - arch/arm/boot/dts/omap3-igep0030.dts | 59 - arch/arm/boot/dts/omap3-ldp.dts | 305 - arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 459 -- arch/arm/boot/dts/omap3-lilly-dbb056.dts | 166 - arch/arm/boot/dts/omap3-n9.dts | 84 - arch/arm/boot/dts/omap3-n900.dts | 1159 ---- arch/arm/boot/dts/omap3-n950-n9.dtsi | 504 -- arch/arm/boot/dts/omap3-n950.dts | 273 - arch/arm/boot/dts/omap3-overo-alto35-common.dtsi | 75 - arch/arm/boot/dts/omap3-overo-alto35.dts | 19 - arch/arm/boot/dts/omap3-overo-base.dtsi | 274 - .../boot/dts/omap3-overo-chestnut43-common.dtsi | 65 - arch/arm/boot/dts/omap3-overo-chestnut43.dts | 35 - arch/arm/boot/dts/omap3-overo-common-dvi.dtsi | 108 - arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi | 163 - arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi | 175 - .../boot/dts/omap3-overo-common-peripherals.dtsi | 92 - arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi | 55 - arch/arm/boot/dts/omap3-overo-gallop43.dts | 35 - arch/arm/boot/dts/omap3-overo-palo35-common.dtsi | 50 - arch/arm/boot/dts/omap3-overo-palo35.dts | 34 - arch/arm/boot/dts/omap3-overo-palo43-common.dtsi | 51 - arch/arm/boot/dts/omap3-overo-palo43.dts | 35 - arch/arm/boot/dts/omap3-overo-storm-alto35.dts | 18 - arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts | 35 - arch/arm/boot/dts/omap3-overo-storm-gallop43.dts | 35 - arch/arm/boot/dts/omap3-overo-storm-palo35.dts | 34 - arch/arm/boot/dts/omap3-overo-storm-palo43.dts | 35 - arch/arm/boot/dts/omap3-overo-storm-summit.dts | 27 - arch/arm/boot/dts/omap3-overo-storm-tobi.dts | 19 - arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts | 18 - arch/arm/boot/dts/omap3-overo-storm.dtsi | 32 - arch/arm/boot/dts/omap3-overo-summit-common.dtsi | 29 - arch/arm/boot/dts/omap3-overo-summit.dts | 27 - arch/arm/boot/dts/omap3-overo-tobi-common.dtsi | 37 - arch/arm/boot/dts/omap3-overo-tobi.dts | 19 - arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi | 59 - arch/arm/boot/dts/omap3-overo-tobiduo.dts | 18 - arch/arm/boot/dts/omap3-overo.dtsi | 31 - arch/arm/boot/dts/omap3-pandora-1ghz.dts | 67 - arch/arm/boot/dts/omap3-pandora-600mhz.dts | 62 - arch/arm/boot/dts/omap3-pandora-common.dtsi | 730 --- .../boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi | 73 - arch/arm/boot/dts/omap3-sb-t35.dtsi | 138 - arch/arm/boot/dts/omap3-sbc-t3517.dts | 76 - arch/arm/boot/dts/omap3-sbc-t3530.dts | 48 - arch/arm/boot/dts/omap3-sbc-t3730.dts | 44 - arch/arm/boot/dts/omap3-sniper.dts | 251 - arch/arm/boot/dts/omap3-tao3530.dtsi | 336 - arch/arm/boot/dts/omap3-thunder.dts | 126 - arch/arm/boot/dts/omap3-zoom3.dts | 231 - arch/arm/boot/dts/omap3.dtsi | 1039 --- arch/arm/boot/dts/omap3430-sdp.dts | 195 - arch/arm/boot/dts/omap3430es1-clocks.dtsi | 233 - arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi | 310 - arch/arm/boot/dts/omap34xx.dtsi | 198 - .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 268 - arch/arm/boot/dts/omap36xx-clocks.dtsi | 118 - .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 237 - arch/arm/boot/dts/omap36xx.dtsi | 250 - arch/arm/boot/dts/omap3xxx-clocks.dtsi | 1790 ------ arch/arm/boot/dts/omap4-cpu-thermal.dtsi | 38 - arch/arm/boot/dts/omap4-droid-bionic-xt875.dts | 55 - arch/arm/boot/dts/omap4-droid4-xt894.dts | 157 - arch/arm/boot/dts/omap4-duovero-parlor.dts | 194 - arch/arm/boot/dts/omap4-duovero.dtsi | 249 - arch/arm/boot/dts/omap4-epson-embt2ws.dts | 450 -- arch/arm/boot/dts/omap4-kc1.dts | 179 - arch/arm/boot/dts/omap4-l4-abe.dtsi | 497 -- arch/arm/boot/dts/omap4-l4.dtsi | 2483 -------- arch/arm/boot/dts/omap4-mcpdm.dtsi | 44 - arch/arm/boot/dts/omap4-panda-a4.dts | 17 - arch/arm/boot/dts/omap4-panda-common.dtsi | 607 -- arch/arm/boot/dts/omap4-panda-es.dts | 114 - arch/arm/boot/dts/omap4-panda.dts | 13 - arch/arm/boot/dts/omap4-sdp-es23plus.dts | 14 - arch/arm/boot/dts/omap4-sdp.dts | 717 --- arch/arm/boot/dts/omap4-var-dvk-om44.dts | 68 - arch/arm/boot/dts/omap4-var-om44customboard.dtsi | 232 - arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi | 75 - arch/arm/boot/dts/omap4-var-som-om44.dtsi | 325 - arch/arm/boot/dts/omap4-var-stk-om44.dts | 14 - arch/arm/boot/dts/omap4.dtsi | 868 --- arch/arm/boot/dts/omap443x-clocks.dtsi | 16 - arch/arm/boot/dts/omap443x.dtsi | 85 - arch/arm/boot/dts/omap4460.dtsi | 127 - arch/arm/boot/dts/omap446x-clocks.dtsi | 26 - arch/arm/boot/dts/omap44xx-clocks.dtsi | 1483 ----- arch/arm/boot/dts/omap5-board-common.dtsi | 755 --- arch/arm/boot/dts/omap5-cm-t54.dts | 697 -- arch/arm/boot/dts/omap5-core-thermal.dtsi | 25 - arch/arm/boot/dts/omap5-gpu-thermal.dtsi | 25 - arch/arm/boot/dts/omap5-igep0050.dts | 136 - arch/arm/boot/dts/omap5-l4-abe.dtsi | 456 -- arch/arm/boot/dts/omap5-l4.dtsi | 2502 -------- arch/arm/boot/dts/omap5-sbc-t54.dts | 52 - arch/arm/boot/dts/omap5-uevm.dts | 234 - arch/arm/boot/dts/omap5.dtsi | 831 --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 1362 ---- arch/arm/boot/dts/openbmc-flash-layout-128.dtsi | 32 - arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi | 35 - arch/arm/boot/dts/openbmc-flash-layout-64.dtsi | 35 - arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 - arch/arm/boot/dts/orion5x-kuroboxpro.dts | 127 - arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 234 - .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 170 - arch/arm/boot/dts/orion5x-linkstation-lschl.dts | 171 - arch/arm/boot/dts/orion5x-linkstation-lsgl.dts | 91 - arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts | 151 - arch/arm/boot/dts/orion5x-linkstation.dtsi | 180 - arch/arm/boot/dts/orion5x-lswsgl.dts | 277 - .../boot/dts/orion5x-maxtor-shared-storage-2.dts | 176 - arch/arm/boot/dts/orion5x-mv88f5181.dtsi | 44 - arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 40 - arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 252 - arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 173 - arch/arm/boot/dts/orion5x.dtsi | 236 - arch/arm/boot/dts/owl-s500-cubieboard6.dts | 36 - arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 25 - arch/arm/boot/dts/owl-s500-guitar.dtsi | 21 - arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 28 - arch/arm/boot/dts/owl-s500-labrador-v2.dtsi | 22 - arch/arm/boot/dts/owl-s500-roseapplepi.dts | 299 - arch/arm/boot/dts/owl-s500-sparky.dts | 36 - arch/arm/boot/dts/owl-s500.dtsi | 338 - arch/arm/boot/dts/pm9g45.dts | 185 - arch/arm/boot/dts/pxa168-aspenite.dts | 33 - arch/arm/boot/dts/pxa168.dtsi | 166 - arch/arm/boot/dts/pxa25x.dtsi | 118 - arch/arm/boot/dts/pxa27x.dtsi | 188 - arch/arm/boot/dts/pxa2xx.dtsi | 162 - arch/arm/boot/dts/pxa300-raumfeld-common.dtsi | 405 -- arch/arm/boot/dts/pxa300-raumfeld-connector.dts | 73 - arch/arm/boot/dts/pxa300-raumfeld-controller.dts | 285 - arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts | 11 - arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts | 11 - arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts | 140 - arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts | 11 - .../boot/dts/pxa300-raumfeld-tuneable-clock.dtsi | 85 - arch/arm/boot/dts/pxa3xx.dtsi | 320 - arch/arm/boot/dts/pxa910-dkb.dts | 170 - arch/arm/boot/dts/pxa910.dtsi | 177 - arch/arm/boot/dts/qcom-apq8016-sbc.dts | 2 - arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts | 300 - arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts | 404 -- arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts | 359 -- .../boot/dts/qcom-apq8026-samsung-matisse-wifi.dts | 519 -- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 973 --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 348 - arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 230 - arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 359 -- arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 325 - .../dts/qcom-apq8064-sony-xperia-lagan-yuga.dts | 389 -- arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 2 - arch/arm/boot/dts/qcom-apq8064.dtsi | 1895 ------ arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 456 -- arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 34 - arch/arm/boot/dts/qcom-apq8084-mtp.dts | 23 - arch/arm/boot/dts/qcom-apq8084.dtsi | 852 --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts | 34 - arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts | 34 - arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 277 - arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts | 214 - arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 - arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 113 - arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 - arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 - arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 - arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 - arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 - arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 - arch/arm/boot/dts/qcom-ipq4019.dtsi | 697 -- arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 - arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 - arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 28 - arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 474 -- arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 - arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 130 - arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 - arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1376 ---- arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 - arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 - .../boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts | 244 - arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 134 - arch/arm/boot/dts/qcom-mdm9615.dtsi | 507 -- arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts | 24 - arch/arm/boot/dts/qcom-msm8226.dtsi | 857 --- arch/arm/boot/dts/qcom-msm8660-surf.dts | 75 - arch/arm/boot/dts/qcom-msm8660.dtsi | 650 -- arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts | 3 - arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts | 3 - .../arm/boot/dts/qcom-msm8916-samsung-grandmax.dts | 3 - .../boot/dts/qcom-msm8916-samsung-serranove.dts | 3 - arch/arm/boot/dts/qcom-msm8916-smp.dtsi | 62 - arch/arm/boot/dts/qcom-msm8960-cdp.dts | 348 - .../boot/dts/qcom-msm8960-samsung-expressatt.dts | 331 - arch/arm/boot/dts/qcom-msm8960.dtsi | 406 -- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 698 -- .../dts/qcom-msm8974-sony-xperia-rhine-amami.dts | 14 - .../dts/qcom-msm8974-sony-xperia-rhine-honami.dts | 8 - .../boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi | 496 -- arch/arm/boot/dts/qcom-msm8974.dtsi | 2405 ------- .../arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 463 -- .../arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts | 513 -- arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts | 814 --- .../qcom-msm8974pro-sony-xperia-shinano-castor.dts | 675 -- arch/arm/boot/dts/qcom-msm8974pro.dtsi | 19 - arch/arm/boot/dts/qcom-pm8226.dtsi | 180 - arch/arm/boot/dts/qcom-pm8841.dtsi | 68 - arch/arm/boot/dts/qcom-pm8941.dtsi | 242 - arch/arm/boot/dts/qcom-pma8084.dtsi | 99 - arch/arm/boot/dts/qcom-pmx55.dtsi | 85 - arch/arm/boot/dts/qcom-pmx65.dtsi | 33 - arch/arm/boot/dts/qcom-sdx55-mtp.dts | 255 - arch/arm/boot/dts/qcom-sdx55-t55.dts | 331 - arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 331 - arch/arm/boot/dts/qcom-sdx55.dtsi | 881 --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 338 - arch/arm/boot/dts/qcom-sdx65.dtsi | 811 --- arch/arm/boot/dts/qcom/Makefile | 45 + arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts | 2 + .../boot/dts/qcom/qcom-apq8026-asus-sparrow.dts | 300 + .../boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts | 404 ++ arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts | 359 ++ .../dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts | 519 ++ .../arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts | 973 +++ .../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 348 + arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 230 + arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts | 359 ++ arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 325 + .../qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts | 389 ++ arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi | 2 + arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 1895 ++++++ .../arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts | 456 ++ arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts | 34 + arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts | 23 + arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 852 +++ .../boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts | 34 + arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts | 34 + arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 277 + arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts | 214 + .../boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts | 22 + arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 113 + .../boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts | 19 + .../boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts | 9 + arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 111 + .../boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts | 65 + .../boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts | 25 + arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi | 75 + arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 697 ++ arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi | 37 + arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 8 + arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts | 28 + arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts | 474 ++ arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi | 37 + arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi | 130 + .../boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi | 37 + arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi | 69 + arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 1376 ++++ arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi | 37 + arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 8 + .../dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts | 244 + arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi | 134 + arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 507 ++ .../boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts | 24 + arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 857 +++ arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts | 75 + arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 650 ++ arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts | 3 + arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts | 3 + .../dts/qcom/qcom-msm8916-samsung-grandmax.dts | 3 + .../dts/qcom/qcom-msm8916-samsung-serranove.dts | 3 + arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi | 62 + arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 348 + .../dts/qcom/qcom-msm8960-samsung-expressatt.dts | 331 + arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 406 ++ .../qcom/qcom-msm8974-lge-nexus5-hammerhead.dts | 698 ++ .../qcom/qcom-msm8974-sony-xperia-rhine-amami.dts | 14 + .../qcom/qcom-msm8974-sony-xperia-rhine-honami.dts | 8 + .../dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi | 496 ++ arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2405 +++++++ .../dts/qcom/qcom-msm8974pro-fairphone-fp2.dts | 463 ++ .../dts/qcom/qcom-msm8974pro-oneplus-bacon.dts | 513 ++ .../boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts | 814 +++ .../qcom-msm8974pro-sony-xperia-shinano-castor.dts | 675 ++ arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi | 19 + arch/arm/boot/dts/qcom/qcom-pm8226.dtsi | 180 + arch/arm/boot/dts/qcom/qcom-pm8841.dtsi | 68 + arch/arm/boot/dts/qcom/qcom-pm8941.dtsi | 242 + arch/arm/boot/dts/qcom/qcom-pma8084.dtsi | 99 + arch/arm/boot/dts/qcom/qcom-pmx55.dtsi | 85 + arch/arm/boot/dts/qcom/qcom-pmx65.dtsi | 33 + arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts | 255 + arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 331 + .../boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts | 331 + arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 881 +++ arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts | 338 + arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 811 +++ arch/arm/boot/dts/r7s72100-genmai.dts | 150 - arch/arm/boot/dts/r7s72100-gr-peach.dts | 139 - arch/arm/boot/dts/r7s72100-rskrza1.dts | 224 - arch/arm/boot/dts/r7s72100.dtsi | 733 --- arch/arm/boot/dts/r7s9210-rza2mevb.dts | 249 - arch/arm/boot/dts/r7s9210.dtsi | 509 -- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 273 - arch/arm/boot/dts/r8a73a4.dtsi | 861 --- arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 325 - arch/arm/boot/dts/r8a7740.dtsi | 736 --- arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 350 - .../dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi | 37 - .../dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi | 31 - arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 445 -- arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 124 - arch/arm/boot/dts/r8a7742.dtsi | 1891 ------ arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 20 - arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 19 - arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 95 - arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 81 - arch/arm/boot/dts/r8a7743.dtsi | 1799 ------ arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 - arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 - arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 90 - arch/arm/boot/dts/r8a7744.dtsi | 1785 ------ .../arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts | 159 - arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 329 - arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 117 - arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 76 - arch/arm/boot/dts/r8a7745.dtsi | 1589 ----- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 321 - arch/arm/boot/dts/r8a77470.dtsi | 1028 --- arch/arm/boot/dts/r8a7778-bockw.dts | 229 - arch/arm/boot/dts/r8a7778.dtsi | 671 -- arch/arm/boot/dts/r8a7779-marzen.dts | 333 - arch/arm/boot/dts/r8a7779.dtsi | 717 --- arch/arm/boot/dts/r8a7790-lager.dts | 947 --- arch/arm/boot/dts/r8a7790-stout.dts | 382 -- arch/arm/boot/dts/r8a7790.dtsi | 1965 ------ arch/arm/boot/dts/r8a7791-koelsch.dts | 912 --- arch/arm/boot/dts/r8a7791-porter.dts | 523 -- arch/arm/boot/dts/r8a7791.dtsi | 1891 ------ arch/arm/boot/dts/r8a7792-blanche.dts | 364 -- arch/arm/boot/dts/r8a7792-wheat.dts | 329 - arch/arm/boot/dts/r8a7792.dtsi | 928 --- arch/arm/boot/dts/r8a7793-gose.dts | 818 --- arch/arm/boot/dts/r8a7793.dtsi | 1470 ----- arch/arm/boot/dts/r8a7794-alt.dts | 533 -- arch/arm/boot/dts/r8a7794-silk.dts | 578 -- arch/arm/boot/dts/r8a7794.dtsi | 1437 ----- arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi | 39 - arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 180 - arch/arm/boot/dts/r9a06g032.dtsi | 477 -- arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts | 50 - arch/arm/boot/dts/rda8810pl-orangepi-i96.dts | 50 - arch/arm/boot/dts/rda8810pl.dtsi | 147 - arch/arm/boot/dts/realtek/Makefile | 4 + arch/arm/boot/dts/realtek/rtd1195-horseradish.dts | 32 + arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts | 32 + arch/arm/boot/dts/realtek/rtd1195.dtsi | 217 + arch/arm/boot/dts/renesas/Makefile | 33 + arch/arm/boot/dts/renesas/emev2-kzm9d.dts | 115 + arch/arm/boot/dts/renesas/emev2.dtsi | 289 + .../dts/renesas/gr-peach-audiocamerashield.dtsi | 75 + arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi | 375 ++ arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi | 124 + arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 150 + arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts | 139 + arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 224 + arch/arm/boot/dts/renesas/r7s72100.dtsi | 733 +++ arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts | 249 + arch/arm/boot/dts/renesas/r7s9210.dtsi | 509 ++ arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts | 273 + arch/arm/boot/dts/renesas/r8a73a4.dtsi | 861 +++ .../boot/dts/renesas/r8a7740-armadillo800eva.dts | 325 + arch/arm/boot/dts/renesas/r8a7740.dtsi | 736 +++ .../boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts | 350 + .../r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi | 37 + .../r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi | 31 + arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts | 445 ++ arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi | 124 + arch/arm/boot/dts/renesas/r8a7742.dtsi | 1891 ++++++ .../boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts | 20 + arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts | 19 + arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi | 95 + arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts | 81 + arch/arm/boot/dts/renesas/r8a7743.dtsi | 1799 ++++++ .../boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 + arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts | 15 + arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi | 90 + arch/arm/boot/dts/renesas/r8a7744.dtsi | 1785 ++++++ .../dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts | 159 + .../arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts | 329 + arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi | 117 + arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts | 76 + arch/arm/boot/dts/renesas/r8a7745.dtsi | 1589 +++++ arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts | 321 + arch/arm/boot/dts/renesas/r8a77470.dtsi | 1028 +++ arch/arm/boot/dts/renesas/r8a7778-bockw.dts | 229 + arch/arm/boot/dts/renesas/r8a7778.dtsi | 671 ++ arch/arm/boot/dts/renesas/r8a7779-marzen.dts | 333 + arch/arm/boot/dts/renesas/r8a7779.dtsi | 717 +++ arch/arm/boot/dts/renesas/r8a7790-lager.dts | 947 +++ arch/arm/boot/dts/renesas/r8a7790-stout.dts | 382 ++ arch/arm/boot/dts/renesas/r8a7790.dtsi | 1965 ++++++ arch/arm/boot/dts/renesas/r8a7791-koelsch.dts | 912 +++ arch/arm/boot/dts/renesas/r8a7791-porter.dts | 523 ++ arch/arm/boot/dts/renesas/r8a7791.dtsi | 1891 ++++++ arch/arm/boot/dts/renesas/r8a7792-blanche.dts | 364 ++ arch/arm/boot/dts/renesas/r8a7792-wheat.dts | 329 + arch/arm/boot/dts/renesas/r8a7792.dtsi | 928 +++ arch/arm/boot/dts/renesas/r8a7793-gose.dts | 818 +++ arch/arm/boot/dts/renesas/r8a7793.dtsi | 1470 +++++ arch/arm/boot/dts/renesas/r8a7794-alt.dts | 533 ++ arch/arm/boot/dts/renesas/r8a7794-silk.dts | 578 ++ arch/arm/boot/dts/renesas/r8a7794.dtsi | 1437 +++++ .../boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi | 39 + .../arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts | 180 + arch/arm/boot/dts/renesas/r9a06g032.dtsi | 477 ++ arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts | 403 ++ arch/arm/boot/dts/renesas/sh73a0.dtsi | 949 +++ arch/arm/boot/dts/rk3036-evb.dts | 48 - arch/arm/boot/dts/rk3036-kylin.dts | 402 -- arch/arm/boot/dts/rk3036.dtsi | 871 --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 207 - arch/arm/boot/dts/rk3066a-marsboard.dts | 221 - arch/arm/boot/dts/rk3066a-mk808.dts | 241 - arch/arm/boot/dts/rk3066a-rayeager.dts | 462 -- arch/arm/boot/dts/rk3066a.dtsi | 880 --- arch/arm/boot/dts/rk3128-evb.dts | 109 - arch/arm/boot/dts/rk3128.dtsi | 916 --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 739 --- arch/arm/boot/dts/rk3188-px3-evb.dts | 305 - arch/arm/boot/dts/rk3188-radxarock.dts | 389 -- arch/arm/boot/dts/rk3188.dtsi | 815 --- arch/arm/boot/dts/rk3228-evb.dts | 72 - arch/arm/boot/dts/rk3229-evb.dts | 256 - arch/arm/boot/dts/rk3229-xms6.dts | 304 - arch/arm/boot/dts/rk3229.dtsi | 52 - arch/arm/boot/dts/rk322x.dtsi | 1295 ---- arch/arm/boot/dts/rk3288-evb-act8846.dts | 188 - arch/arm/boot/dts/rk3288-evb-rk808.dts | 202 - arch/arm/boot/dts/rk3288-evb.dtsi | 403 -- arch/arm/boot/dts/rk3288-firefly-beta.dts | 34 - arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 274 - arch/arm/boot/dts/rk3288-firefly-reload.dts | 392 -- arch/arm/boot/dts/rk3288-firefly.dts | 34 - arch/arm/boot/dts/rk3288-firefly.dtsi | 573 -- arch/arm/boot/dts/rk3288-miqi.dts | 440 -- arch/arm/boot/dts/rk3288-phycore-rdk.dts | 264 - arch/arm/boot/dts/rk3288-phycore-som.dtsi | 439 -- arch/arm/boot/dts/rk3288-popmetal.dts | 513 -- arch/arm/boot/dts/rk3288-r89.dts | 400 -- arch/arm/boot/dts/rk3288-rock-pi-n8.dts | 17 - arch/arm/boot/dts/rk3288-rock2-som.dtsi | 273 - arch/arm/boot/dts/rk3288-rock2-square.dts | 287 - arch/arm/boot/dts/rk3288-tinker-s.dts | 30 - arch/arm/boot/dts/rk3288-tinker.dts | 13 - arch/arm/boot/dts/rk3288-tinker.dtsi | 546 -- arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 99 - arch/arm/boot/dts/rk3288-veyron-brain.dts | 111 - .../boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi | 22 - arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 184 - arch/arm/boot/dts/rk3288-veyron-edp.dtsi | 141 - arch/arm/boot/dts/rk3288-veyron-fievel.dts | 528 -- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 334 - arch/arm/boot/dts/rk3288-veyron-jerry.dts | 494 -- arch/arm/boot/dts/rk3288-veyron-mickey.dts | 453 -- arch/arm/boot/dts/rk3288-veyron-mighty.dts | 34 - arch/arm/boot/dts/rk3288-veyron-minnie.dts | 415 -- arch/arm/boot/dts/rk3288-veyron-pinky.dts | 137 - arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 95 - arch/arm/boot/dts/rk3288-veyron-speedy.dts | 324 - arch/arm/boot/dts/rk3288-veyron-tiger.dts | 87 - arch/arm/boot/dts/rk3288-veyron.dtsi | 597 -- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 361 -- arch/arm/boot/dts/rk3288-vyasa.dts | 500 -- arch/arm/boot/dts/rk3288.dtsi | 2026 ------ arch/arm/boot/dts/rk3xxx.dtsi | 488 -- .../boot/dts/rockchip-radxa-dalang-carrier.dtsi | 137 - arch/arm/boot/dts/rockchip/Makefile | 42 + arch/arm/boot/dts/rockchip/rk3036-evb.dts | 48 + arch/arm/boot/dts/rockchip/rk3036-kylin.dts | 402 ++ arch/arm/boot/dts/rockchip/rk3036.dtsi | 871 +++ arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts | 207 + arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts | 221 + arch/arm/boot/dts/rockchip/rk3066a-mk808.dts | 241 + arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts | 462 ++ arch/arm/boot/dts/rockchip/rk3066a.dtsi | 880 +++ arch/arm/boot/dts/rockchip/rk3128-evb.dts | 109 + arch/arm/boot/dts/rockchip/rk3128.dtsi | 916 +++ arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts | 739 +++ arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts | 305 + arch/arm/boot/dts/rockchip/rk3188-radxarock.dts | 389 ++ arch/arm/boot/dts/rockchip/rk3188.dtsi | 815 +++ arch/arm/boot/dts/rockchip/rk3228-evb.dts | 72 + arch/arm/boot/dts/rockchip/rk3229-evb.dts | 256 + arch/arm/boot/dts/rockchip/rk3229-xms6.dts | 304 + arch/arm/boot/dts/rockchip/rk3229.dtsi | 52 + arch/arm/boot/dts/rockchip/rk322x.dtsi | 1295 ++++ arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts | 188 + arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts | 202 + arch/arm/boot/dts/rockchip/rk3288-evb.dtsi | 403 ++ arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts | 34 + .../dts/rockchip/rk3288-firefly-reload-core.dtsi | 274 + .../boot/dts/rockchip/rk3288-firefly-reload.dts | 392 ++ arch/arm/boot/dts/rockchip/rk3288-firefly.dts | 34 + arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi | 573 ++ arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 440 ++ arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts | 264 + arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi | 439 ++ arch/arm/boot/dts/rockchip/rk3288-popmetal.dts | 513 ++ arch/arm/boot/dts/rockchip/rk3288-r89.dts | 400 ++ arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts | 17 + arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi | 273 + arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts | 287 + arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts | 30 + arch/arm/boot/dts/rockchip/rk3288-tinker.dts | 13 + arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 546 ++ .../dts/rockchip/rk3288-veyron-analog-audio.dtsi | 99 + arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts | 111 + .../rockchip/rk3288-veyron-broadcom-bluetooth.dtsi | 22 + .../dts/rockchip/rk3288-veyron-chromebook.dtsi | 184 + arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi | 141 + .../arm/boot/dts/rockchip/rk3288-veyron-fievel.dts | 528 ++ arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts | 334 + arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts | 494 ++ .../arm/boot/dts/rockchip/rk3288-veyron-mickey.dts | 453 ++ .../arm/boot/dts/rockchip/rk3288-veyron-mighty.dts | 34 + .../arm/boot/dts/rockchip/rk3288-veyron-minnie.dts | 415 ++ arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts | 137 + .../arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi | 95 + .../arm/boot/dts/rockchip/rk3288-veyron-speedy.dts | 324 + arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts | 87 + arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi | 597 ++ arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi | 361 ++ arch/arm/boot/dts/rockchip/rk3288-vyasa.dts | 500 ++ arch/arm/boot/dts/rockchip/rk3288.dtsi | 2026 ++++++ arch/arm/boot/dts/rockchip/rk3xxx.dtsi | 488 ++ .../rockchip/rockchip-radxa-dalang-carrier.dtsi | 137 + arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts | 212 + arch/arm/boot/dts/rockchip/rv1108-evb.dts | 230 + arch/arm/boot/dts/rockchip/rv1108.dtsi | 986 +++ .../boot/dts/rockchip/rv1126-edgeble-neu2-io.dts | 79 + .../arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi | 338 + arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 253 + arch/arm/boot/dts/rockchip/rv1126.dtsi | 487 ++ arch/arm/boot/dts/rtd1195-horseradish.dts | 32 - arch/arm/boot/dts/rtd1195-mele-x1000.dts | 32 - arch/arm/boot/dts/rtd1195.dtsi | 217 - arch/arm/boot/dts/rv1108-elgin-r1.dts | 212 - arch/arm/boot/dts/rv1108-evb.dts | 230 - arch/arm/boot/dts/rv1108.dtsi | 986 --- arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts | 79 - arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi | 338 - arch/arm/boot/dts/rv1126-pinctrl.dtsi | 253 - arch/arm/boot/dts/rv1126.dtsi | 487 -- arch/arm/boot/dts/s3c6400.dtsi | 38 - arch/arm/boot/dts/s3c6410-mini6410.dts | 218 - arch/arm/boot/dts/s3c6410-smdk6410.dts | 97 - arch/arm/boot/dts/s3c6410.dtsi | 54 - arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 682 -- arch/arm/boot/dts/s3c64xx-pinctrl.h | 27 - arch/arm/boot/dts/s3c64xx.dtsi | 192 - arch/arm/boot/dts/s5pv210-aquila.dts | 398 -- arch/arm/boot/dts/s5pv210-aries.dtsi | 916 --- arch/arm/boot/dts/s5pv210-fascinate4g.dts | 403 -- arch/arm/boot/dts/s5pv210-galaxys.dts | 448 -- arch/arm/boot/dts/s5pv210-goni.dts | 447 -- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 845 --- arch/arm/boot/dts/s5pv210-pinctrl.h | 39 - arch/arm/boot/dts/s5pv210-smdkc110.dts | 84 - arch/arm/boot/dts/s5pv210-smdkv210.dts | 254 - arch/arm/boot/dts/s5pv210-torbreck.dts | 98 - arch/arm/boot/dts/s5pv210.dtsi | 632 -- arch/arm/boot/dts/sam9x60.dtsi | 1353 ---- arch/arm/boot/dts/sama5d2-pinfunc.h | 881 --- arch/arm/boot/dts/sama5d2.dtsi | 1166 ---- arch/arm/boot/dts/sama5d29.dtsi | 16 - arch/arm/boot/dts/sama5d3.dtsi | 1126 ---- arch/arm/boot/dts/sama5d31.dtsi | 15 - arch/arm/boot/dts/sama5d31ek.dts | 52 - arch/arm/boot/dts/sama5d33.dtsi | 13 - arch/arm/boot/dts/sama5d33ek.dts | 45 - arch/arm/boot/dts/sama5d34.dtsi | 15 - arch/arm/boot/dts/sama5d34ek.dts | 62 - arch/arm/boot/dts/sama5d35.dtsi | 17 - arch/arm/boot/dts/sama5d35ek.dts | 56 - arch/arm/boot/dts/sama5d36.dtsi | 19 - arch/arm/boot/dts/sama5d36ek.dts | 54 - arch/arm/boot/dts/sama5d36ek_cmp.dts | 50 - arch/arm/boot/dts/sama5d3_can.dtsi | 57 - arch/arm/boot/dts/sama5d3_emac.dtsi | 48 - arch/arm/boot/dts/sama5d3_gmac.dtsi | 78 - arch/arm/boot/dts/sama5d3_lcd.dtsi | 197 - arch/arm/boot/dts/sama5d3_mci2.dtsi | 49 - arch/arm/boot/dts/sama5d3_tcb1.dtsi | 31 - arch/arm/boot/dts/sama5d3_uart.dtsi | 65 - arch/arm/boot/dts/sama5d3xcm.dtsi | 139 - arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 193 - arch/arm/boot/dts/sama5d3xdm.dtsi | 40 - arch/arm/boot/dts/sama5d3xmb.dtsi | 208 - arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 264 - arch/arm/boot/dts/sama5d3xmb_emac.dtsi | 25 - arch/arm/boot/dts/sama5d3xmb_gmac.dtsi | 47 - arch/arm/boot/dts/sama5d4.dtsi | 1453 ----- arch/arm/boot/dts/sama7g5-pinfunc.h | 923 --- arch/arm/boot/dts/sama7g5.dtsi | 1016 --- arch/arm/boot/dts/samsung/Makefile | 54 + .../dts/samsung/exynos-mfc-reserved-memory.dtsi | 32 + arch/arm/boot/dts/samsung/exynos-pinctrl.h | 55 + .../boot/dts/samsung/exynos-syscon-restart.dtsi | 20 + .../boot/dts/samsung/exynos3250-artik5-eval.dts | 69 + arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi | 432 ++ arch/arm/boot/dts/samsung/exynos3250-monk.dts | 644 ++ arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi | 543 ++ arch/arm/boot/dts/samsung/exynos3250-rinato.dts | 921 +++ arch/arm/boot/dts/samsung/exynos3250.dtsi | 950 +++ arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi | 48 + arch/arm/boot/dts/samsung/exynos4.dtsi | 1007 +++ arch/arm/boot/dts/samsung/exynos4210-i9100.dts | 860 +++ arch/arm/boot/dts/samsung/exynos4210-origen.dts | 372 ++ arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi | 863 +++ arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts | 229 + arch/arm/boot/dts/samsung/exynos4210-trats.dts | 567 ++ .../boot/dts/samsung/exynos4210-universal_c210.dts | 689 ++ arch/arm/boot/dts/samsung/exynos4210.dtsi | 531 ++ arch/arm/boot/dts/samsung/exynos4212.dtsi | 157 + .../arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi | 216 + arch/arm/boot/dts/samsung/exynos4412-i9300.dts | 27 + arch/arm/boot/dts/samsung/exynos4412-i9305.dts | 21 + .../arm/boot/dts/samsung/exynos4412-itop-elite.dts | 234 + .../boot/dts/samsung/exynos4412-itop-scp-core.dtsi | 509 ++ arch/arm/boot/dts/samsung/exynos4412-midas.dtsi | 1459 +++++ arch/arm/boot/dts/samsung/exynos4412-n710x.dts | 116 + .../boot/dts/samsung/exynos4412-odroid-common.dtsi | 574 ++ arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts | 155 + arch/arm/boot/dts/samsung/exynos4412-odroidx.dts | 143 + arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts | 22 + arch/arm/boot/dts/samsung/exynos4412-origen.dts | 558 ++ .../boot/dts/samsung/exynos4412-p4note-n8010.dts | 18 + arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi | 1229 ++++ .../boot/dts/samsung/exynos4412-ppmu-common.dtsi | 47 + arch/arm/boot/dts/samsung/exynos4412-prime.dtsi | 47 + arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts | 182 + arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts | 160 + arch/arm/boot/dts/samsung/exynos4412-trats2.dts | 29 + arch/arm/boot/dts/samsung/exynos4412.dtsi | 183 + arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi | 979 +++ arch/arm/boot/dts/samsung/exynos4x12.dtsi | 664 ++ arch/arm/boot/dts/samsung/exynos5.dtsi | 230 + arch/arm/boot/dts/samsung/exynos5250-arndale.dts | 643 ++ arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi | 833 +++ arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts | 430 ++ .../boot/dts/samsung/exynos5250-snow-common.dtsi | 718 +++ arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts | 56 + arch/arm/boot/dts/samsung/exynos5250-snow.dts | 52 + arch/arm/boot/dts/samsung/exynos5250-spring.dts | 567 ++ arch/arm/boot/dts/samsung/exynos5250.dtsi | 1225 ++++ arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi | 585 ++ arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts | 117 + arch/arm/boot/dts/samsung/exynos5260.dtsi | 554 ++ arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts | 664 ++ arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi | 652 ++ arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts | 152 + arch/arm/boot/dts/samsung/exynos5410.dtsi | 440 ++ .../boot/dts/samsung/exynos5420-arndale-octa.dts | 843 +++ .../boot/dts/samsung/exynos5420-chagall-wifi.dts | 75 + arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi | 163 + .../dts/samsung/exynos5420-galaxy-tab-common.dtsi | 696 ++ .../arm/boot/dts/samsung/exynos5420-klimt-wifi.dts | 75 + arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts | 1126 ++++ arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi | 734 +++ arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts | 435 ++ .../boot/dts/samsung/exynos5420-trip-points.dtsi | 31 + arch/arm/boot/dts/samsung/exynos5420.dtsi | 1397 ++++ arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi | 170 + .../boot/dts/samsung/exynos5422-odroid-core.dtsi | 1072 ++++ arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts | 266 + .../dts/samsung/exynos5422-odroidxu3-audio.dtsi | 83 + .../dts/samsung/exynos5422-odroidxu3-common.dtsi | 510 ++ .../boot/dts/samsung/exynos5422-odroidxu3-lite.dts | 127 + arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts | 94 + arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts | 94 + .../boot/dts/samsung/exynos5422-samsung-k3g.dts | 679 ++ .../boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi | 54 + arch/arm/boot/dts/samsung/exynos54xx.dtsi | 210 + arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts | 1108 ++++ arch/arm/boot/dts/samsung/exynos5800.dtsi | 166 + arch/arm/boot/dts/samsung/s3c6400.dtsi | 38 + arch/arm/boot/dts/samsung/s3c6410-mini6410.dts | 218 + arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts | 97 + arch/arm/boot/dts/samsung/s3c6410.dtsi | 54 + arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi | 682 ++ arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h | 27 + arch/arm/boot/dts/samsung/s3c64xx.dtsi | 192 + arch/arm/boot/dts/samsung/s5pv210-aquila.dts | 398 ++ arch/arm/boot/dts/samsung/s5pv210-aries.dtsi | 916 +++ arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts | 403 ++ arch/arm/boot/dts/samsung/s5pv210-galaxys.dts | 448 ++ arch/arm/boot/dts/samsung/s5pv210-goni.dts | 447 ++ arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi | 845 +++ arch/arm/boot/dts/samsung/s5pv210-pinctrl.h | 39 + arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts | 84 + arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts | 254 + arch/arm/boot/dts/samsung/s5pv210-torbreck.dts | 98 + arch/arm/boot/dts/samsung/s5pv210.dtsi | 632 ++ arch/arm/boot/dts/sd5203.dts | 96 - arch/arm/boot/dts/sh73a0-kzm9g.dts | 403 -- arch/arm/boot/dts/sh73a0.dtsi | 949 --- arch/arm/boot/dts/sigmastar/Makefile | 10 + .../sigmastar/mstar-infinity-breadbee-common.dtsi | 49 + .../mstar-infinity-msc313-breadbee_crust.dts | 26 + .../boot/dts/sigmastar/mstar-infinity-msc313.dtsi | 14 + arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi | 52 + .../sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi | 20 + ...tar-infinity2m-ssd202d-100ask-dongshanpione.dts | 25 + .../mstar-infinity2m-ssd202d-miyoo-mini.dts | 25 + .../mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 + .../sigmastar/mstar-infinity2m-ssd202d-unitv2.dts | 25 + ...y2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts | 23 + ...infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi | 28 + .../dts/sigmastar/mstar-infinity2m-ssd202d.dtsi | 14 + .../dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi | 17 + arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi | 39 + .../sigmastar/mstar-infinity3-msc313e-breadbee.dts | 26 + .../dts/sigmastar/mstar-infinity3-msc313e.dtsi | 14 + arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi | 69 + .../mstar-mercury5-ssc8336n-midrived08.dts | 25 + .../dts/sigmastar/mstar-mercury5-ssc8336n.dtsi | 14 + arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi | 11 + arch/arm/boot/dts/sigmastar/mstar-v7.dtsi | 192 + arch/arm/boot/dts/socfpga.dtsi | 984 --- arch/arm/boot/dts/socfpga_arria10.dtsi | 920 --- arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts | 90 - arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 81 - arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts | 55 - arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 183 - arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 26 - arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 38 - arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 28 - arch/arm/boot/dts/socfpga_arria5.dtsi | 37 - arch/arm/boot/dts/socfpga_arria5_socdk.dts | 151 - arch/arm/boot/dts/socfpga_cyclone5.dtsi | 37 - arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts | 130 - .../arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts | 101 - arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 23 - arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 81 - arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 166 - arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 189 - arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 94 - arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 132 - arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 267 - arch/arm/boot/dts/socfpga_vt.dts | 77 - arch/arm/boot/dts/socionext/Makefile | 13 + arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts | 32 + arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi | 104 + arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts | 88 + arch/arm/boot/dts/socionext/uniphier-ld4.dtsi | 431 ++ arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts | 103 + arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi | 30 + arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi | 223 + arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts | 109 + arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts | 118 + .../arm/boot/dts/socionext/uniphier-pro4-sanji.dts | 96 + arch/arm/boot/dts/socionext/uniphier-pro4.dtsi | 734 +++ .../boot/dts/socionext/uniphier-pro5-epcore.dts | 76 + .../arm/boot/dts/socionext/uniphier-pro5-proex.dts | 59 + arch/arm/boot/dts/socionext/uniphier-pro5.dtsi | 707 +++ .../boot/dts/socionext/uniphier-pxs2-gentil.dts | 105 + .../arm/boot/dts/socionext/uniphier-pxs2-vodka.dts | 98 + arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi | 845 +++ .../boot/dts/socionext/uniphier-ref-daughter.dtsi | 14 + arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts | 92 + arch/arm/boot/dts/socionext/uniphier-sld8.dtsi | 436 ++ .../boot/dts/socionext/uniphier-support-card.dtsi | 27 + arch/arm/boot/dts/spear1310-evb.dts | 405 -- arch/arm/boot/dts/spear1310.dtsi | 307 - arch/arm/boot/dts/spear1340-evb.dts | 503 -- arch/arm/boot/dts/spear1340.dtsi | 167 - arch/arm/boot/dts/spear13xx.dtsi | 339 - arch/arm/boot/dts/spear300-evb.dts | 249 - arch/arm/boot/dts/spear300.dtsi | 83 - arch/arm/boot/dts/spear310-evb.dts | 202 - arch/arm/boot/dts/spear310.dtsi | 113 - arch/arm/boot/dts/spear320-evb.dts | 201 - arch/arm/boot/dts/spear320-hmi.dts | 298 - arch/arm/boot/dts/spear320.dtsi | 142 - arch/arm/boot/dts/spear320s.dtsi | 24 - arch/arm/boot/dts/spear3xx.dtsi | 151 - arch/arm/boot/dts/spear600-evb.dts | 106 - arch/arm/boot/dts/spear600.dtsi | 242 - arch/arm/boot/dts/st-pincfg.h | 72 - arch/arm/boot/dts/st/Makefile | 74 + arch/arm/boot/dts/st/spear1310-evb.dts | 405 ++ arch/arm/boot/dts/st/spear1310.dtsi | 307 + arch/arm/boot/dts/st/spear1340-evb.dts | 503 ++ arch/arm/boot/dts/st/spear1340.dtsi | 167 + arch/arm/boot/dts/st/spear13xx.dtsi | 339 + arch/arm/boot/dts/st/spear300-evb.dts | 249 + arch/arm/boot/dts/st/spear300.dtsi | 83 + arch/arm/boot/dts/st/spear310-evb.dts | 202 + arch/arm/boot/dts/st/spear310.dtsi | 113 + arch/arm/boot/dts/st/spear320-evb.dts | 201 + arch/arm/boot/dts/st/spear320-hmi.dts | 298 + arch/arm/boot/dts/st/spear320.dtsi | 142 + arch/arm/boot/dts/st/spear320s.dtsi | 24 + arch/arm/boot/dts/st/spear3xx.dtsi | 151 + arch/arm/boot/dts/st/spear600-evb.dts | 106 + arch/arm/boot/dts/st/spear600.dtsi | 242 + arch/arm/boot/dts/st/st-pincfg.h | 72 + arch/arm/boot/dts/st/ste-ab8500.dtsi | 392 ++ arch/arm/boot/dts/st/ste-ab8505.dtsi | 329 + arch/arm/boot/dts/st/ste-db8500.dtsi | 52 + arch/arm/boot/dts/st/ste-db8520.dtsi | 52 + arch/arm/boot/dts/st/ste-db9500.dtsi | 34 + arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi | 650 ++ arch/arm/boot/dts/st/ste-dbx5x0.dtsi | 1238 ++++ arch/arm/boot/dts/st/ste-href-ab8500.dtsi | 442 ++ arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi | 212 + arch/arm/boot/dts/st/ste-href-stuib.dtsi | 211 + arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi | 289 + arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi | 220 + arch/arm/boot/dts/st/ste-href.dtsi | 314 + arch/arm/boot/dts/st/ste-href520-tvk.dts | 54 + arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts | 52 + arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts | 33 + arch/arm/boot/dts/st/ste-hrefprev60.dtsi | 122 + arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts | 74 + arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts | 55 + arch/arm/boot/dts/st/ste-hrefv60plus.dtsi | 377 ++ arch/arm/boot/dts/st/ste-nomadik-nhk15.dts | 264 + arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi | 174 + arch/arm/boot/dts/st/ste-nomadik-s8815.dts | 172 + arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi | 884 +++ arch/arm/boot/dts/st/ste-snowball.dts | 657 ++ .../boot/dts/st/ste-ux500-samsung-codina-tmo.dts | 793 +++ arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts | 953 +++ arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts | 887 +++ arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts | 733 +++ arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts | 998 +++ arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts | 727 +++ arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts | 714 +++ arch/arm/boot/dts/st/stih407-b2120.dts | 27 + arch/arm/boot/dts/st/stih407-clock.dtsi | 210 + arch/arm/boot/dts/st/stih407-family.dtsi | 991 +++ arch/arm/boot/dts/st/stih407-pinctrl.dtsi | 1262 ++++ arch/arm/boot/dts/st/stih407.dtsi | 145 + arch/arm/boot/dts/st/stih410-b2120.dts | 66 + arch/arm/boot/dts/st/stih410-b2260.dts | 210 + arch/arm/boot/dts/st/stih410-clock.dtsi | 215 + arch/arm/boot/dts/st/stih410-pinctrl.dtsi | 31 + arch/arm/boot/dts/st/stih410.dtsi | 288 + arch/arm/boot/dts/st/stih418-b2199.dts | 109 + arch/arm/boot/dts/st/stih418-b2264.dts | 151 + arch/arm/boot/dts/st/stih418-clock.dtsi | 215 + arch/arm/boot/dts/st/stih418.dtsi | 118 + arch/arm/boot/dts/st/stihxxx-b2120.dtsi | 206 + arch/arm/boot/dts/st/stm32429i-eval.dts | 337 + arch/arm/boot/dts/st/stm32746g-eval.dts | 222 + arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 482 ++ arch/arm/boot/dts/st/stm32f429-disco.dts | 232 + arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi | 91 + arch/arm/boot/dts/st/stm32f429.dtsi | 799 +++ arch/arm/boot/dts/st/stm32f469-disco.dts | 254 + arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi | 92 + arch/arm/boot/dts/st/stm32f469.dtsi | 18 + arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 370 ++ arch/arm/boot/dts/st/stm32f746-disco.dts | 144 + arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi | 11 + arch/arm/boot/dts/st/stm32f746.dtsi | 592 ++ arch/arm/boot/dts/st/stm32f769-disco.dts | 165 + arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi | 11 + arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi | 275 + arch/arm/boot/dts/st/stm32h743.dtsi | 730 +++ arch/arm/boot/dts/st/stm32h743i-disco.dts | 111 + arch/arm/boot/dts/st/stm32h743i-eval.dts | 160 + arch/arm/boot/dts/st/stm32h750.dtsi | 6 + arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 229 + arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 390 ++ arch/arm/boot/dts/st/stm32mp131.dtsi | 1510 +++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 68 + arch/arm/boot/dts/st/stm32mp135.dtsi | 12 + arch/arm/boot/dts/st/stm32mp135f-dk.dts | 370 ++ arch/arm/boot/dts/st/stm32mp13xc.dtsi | 18 + arch/arm/boot/dts/st/stm32mp13xf.dtsi | 18 + arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 2697 ++++++++ arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 105 + arch/arm/boot/dts/st/stm32mp151.dtsi | 1846 ++++++ .../boot/dts/st/stm32mp151a-dhcor-testbench.dts | 17 + arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts | 52 + arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts | 304 + arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi | 233 + arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts | 63 + arch/arm/boot/dts/st/stm32mp153.dtsi | 59 + arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts | 39 + .../boot/dts/st/stm32mp153c-dhcor-drc-compact.dts | 30 + arch/arm/boot/dts/st/stm32mp157.dtsi | 30 + arch/arm/boot/dts/st/stm32mp157a-avenger96.dts | 11 + .../boot/dts/st/stm32mp157a-dhcor-avenger96.dts | 37 + arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 82 + arch/arm/boot/dts/st/stm32mp157a-dk1.dts | 25 + .../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 134 + .../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 49 + .../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 136 + .../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 196 + arch/arm/boot/dts/st/stm32mp157a-iot-box.dts | 70 + ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 157 + .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 59 + .../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 148 + arch/arm/boot/dts/st/stm32mp157a-stinger96.dts | 12 + arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi | 341 + arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts | 32 + arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts | 39 + arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 88 + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 106 + arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 87 + arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 403 ++ arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts | 53 + .../arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi | 543 ++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 93 + arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 426 ++ arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 253 + arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 263 + arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 88 + .../boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts | 60 + .../dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi | 577 ++ arch/arm/boot/dts/st/stm32mp15xc.dtsi | 18 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi | 169 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 332 + .../arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi | 151 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 546 ++ .../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 516 ++ .../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 348 + arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi | 28 + arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 271 + .../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 199 + arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 741 +++ arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi | 222 + arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi | 85 + arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi | 57 + arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi | 73 + arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi | 57 + arch/arm/boot/dts/ste-ab8500.dtsi | 392 -- arch/arm/boot/dts/ste-ab8505.dtsi | 329 - arch/arm/boot/dts/ste-db8500.dtsi | 52 - arch/arm/boot/dts/ste-db8520.dtsi | 52 - arch/arm/boot/dts/ste-db9500.dtsi | 34 - arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | 650 -- arch/arm/boot/dts/ste-dbx5x0.dtsi | 1238 ---- arch/arm/boot/dts/ste-href-ab8500.dtsi | 442 -- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 212 - arch/arm/boot/dts/ste-href-stuib.dtsi | 211 - arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi | 289 - arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi | 220 - arch/arm/boot/dts/ste-href.dtsi | 314 - arch/arm/boot/dts/ste-href520-tvk.dts | 54 - arch/arm/boot/dts/ste-hrefprev60-stuib.dts | 52 - arch/arm/boot/dts/ste-hrefprev60-tvk.dts | 33 - arch/arm/boot/dts/ste-hrefprev60.dtsi | 122 - arch/arm/boot/dts/ste-hrefv60plus-stuib.dts | 74 - arch/arm/boot/dts/ste-hrefv60plus-tvk.dts | 55 - arch/arm/boot/dts/ste-hrefv60plus.dtsi | 377 -- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 264 - arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 174 - arch/arm/boot/dts/ste-nomadik-s8815.dts | 172 - arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 884 --- arch/arm/boot/dts/ste-snowball.dts | 657 -- arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts | 793 --- arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 953 --- arch/arm/boot/dts/ste-ux500-samsung-gavini.dts | 887 --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 733 --- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 998 --- arch/arm/boot/dts/ste-ux500-samsung-kyle.dts | 727 --- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 714 --- arch/arm/boot/dts/stih407-b2120.dts | 27 - arch/arm/boot/dts/stih407-clock.dtsi | 210 - arch/arm/boot/dts/stih407-family.dtsi | 991 --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 1262 ---- arch/arm/boot/dts/stih407.dtsi | 145 - arch/arm/boot/dts/stih410-b2120.dts | 66 - arch/arm/boot/dts/stih410-b2260.dts | 210 - arch/arm/boot/dts/stih410-clock.dtsi | 215 - arch/arm/boot/dts/stih410-pinctrl.dtsi | 31 - arch/arm/boot/dts/stih410.dtsi | 288 - arch/arm/boot/dts/stih418-b2199.dts | 109 - arch/arm/boot/dts/stih418-b2264.dts | 151 - arch/arm/boot/dts/stih418-clock.dtsi | 215 - arch/arm/boot/dts/stih418.dtsi | 118 - arch/arm/boot/dts/stihxxx-b2120.dtsi | 206 - arch/arm/boot/dts/stm32429i-eval.dts | 337 - arch/arm/boot/dts/stm32746g-eval.dts | 222 - arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 482 -- arch/arm/boot/dts/stm32f429-disco.dts | 232 - arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 91 - arch/arm/boot/dts/stm32f429.dtsi | 799 --- arch/arm/boot/dts/stm32f469-disco.dts | 254 - arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 92 - arch/arm/boot/dts/stm32f469.dtsi | 18 - arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 370 -- arch/arm/boot/dts/stm32f746-disco.dts | 144 - arch/arm/boot/dts/stm32f746-pinctrl.dtsi | 11 - arch/arm/boot/dts/stm32f746.dtsi | 592 -- arch/arm/boot/dts/stm32f769-disco.dts | 165 - arch/arm/boot/dts/stm32f769-pinctrl.dtsi | 11 - arch/arm/boot/dts/stm32h7-pinctrl.dtsi | 275 - arch/arm/boot/dts/stm32h743.dtsi | 730 --- arch/arm/boot/dts/stm32h743i-disco.dts | 111 - arch/arm/boot/dts/stm32h743i-eval.dts | 160 - arch/arm/boot/dts/stm32h750.dtsi | 6 - arch/arm/boot/dts/stm32h750i-art-pi.dts | 229 - arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 390 -- arch/arm/boot/dts/stm32mp131.dtsi | 1510 ----- arch/arm/boot/dts/stm32mp133.dtsi | 68 - arch/arm/boot/dts/stm32mp135.dtsi | 12 - arch/arm/boot/dts/stm32mp135f-dk.dts | 370 -- arch/arm/boot/dts/stm32mp13xc.dtsi | 18 - arch/arm/boot/dts/stm32mp13xf.dtsi | 18 - arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 2697 -------- arch/arm/boot/dts/stm32mp15-scmi.dtsi | 105 - arch/arm/boot/dts/stm32mp151.dtsi | 1846 ------ arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts | 17 - arch/arm/boot/dts/stm32mp151a-prtt1a.dts | 52 - arch/arm/boot/dts/stm32mp151a-prtt1c.dts | 304 - arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi | 233 - arch/arm/boot/dts/stm32mp151a-prtt1s.dts | 63 - arch/arm/boot/dts/stm32mp153.dtsi | 59 - arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts | 39 - .../arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts | 30 - arch/arm/boot/dts/stm32mp157.dtsi | 30 - arch/arm/boot/dts/stm32mp157a-avenger96.dts | 11 - arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts | 37 - arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 82 - arch/arm/boot/dts/stm32mp157a-dk1.dts | 25 - .../stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 134 - .../dts/stm32mp157a-icore-stm32mp1-ctouch2.dts | 49 - .../dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 136 - arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 - arch/arm/boot/dts/stm32mp157a-iot-box.dts | 70 - ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 157 - .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 59 - .../boot/dts/stm32mp157a-microgea-stm32mp1.dtsi | 148 - arch/arm/boot/dts/stm32mp157a-stinger96.dts | 12 - arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 341 - arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 32 - arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts | 39 - arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 88 - arch/arm/boot/dts/stm32mp157c-dk2.dts | 106 - arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 87 - arch/arm/boot/dts/stm32mp157c-ed1.dts | 403 -- arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts | 53 - arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 543 -- arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 93 - arch/arm/boot/dts/stm32mp157c-ev1.dts | 426 -- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 253 - arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 263 - arch/arm/boot/dts/stm32mp157c-odyssey.dts | 88 - .../boot/dts/stm32mp157c-phycore-stm32mp1-3.dts | 60 - .../dts/stm32mp157c-phycore-stm32mp15-som.dtsi | 577 -- arch/arm/boot/dts/stm32mp15xc.dtsi | 18 - arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi | 169 - arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 332 - arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi | 151 - arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 546 -- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 516 -- .../boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi | 348 - arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi | 28 - arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 271 - arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 199 - arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 741 --- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 222 - arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi | 85 - arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi | 57 - arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi | 73 - arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi | 57 - arch/arm/boot/dts/sun4i-a10-a1000.dts | 255 - arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 151 - arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 159 - arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 255 - arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 218 - arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 192 - arch/arm/boot/dts/sun4i-a10-hackberry.dts | 140 - arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 115 - arch/arm/boot/dts/sun4i-a10-inet1.dts | 229 - arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 203 - arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 357 -- .../boot/dts/sun4i-a10-itead-iteaduino-plus.dts | 126 - arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 181 - arch/arm/boot/dts/sun4i-a10-marsboard.dts | 182 - arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 144 - arch/arm/boot/dts/sun4i-a10-mk802.dts | 144 - arch/arm/boot/dts/sun4i-a10-mk802ii.dts | 111 - arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 225 - arch/arm/boot/dts/sun4i-a10-pcduino.dts | 200 - arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 67 - arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 206 - arch/arm/boot/dts/sun4i-a10-topwise-a721.dts | 242 - arch/arm/boot/dts/sun4i-a10.dtsi | 1271 ---- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 137 - arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 149 - arch/arm/boot/dts/sun5i-a10s-mk802.dts | 127 - arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 272 - arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 118 - arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 195 - arch/arm/boot/dts/sun5i-a10s.dtsi | 173 - arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts | 50 - .../boot/dts/sun5i-a13-empire-electronix-d709.dts | 190 - .../boot/dts/sun5i-a13-empire-electronix-m712.dts | 51 - arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 182 - arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts | 50 - arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 214 - arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 141 - arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 247 - .../boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 - arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 80 - arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 116 - arch/arm/boot/dts/sun5i-a13.dtsi | 118 - arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 238 - arch/arm/boot/dts/sun5i-gr8-evb.dts | 333 - arch/arm/boot/dts/sun5i-gr8.dtsi | 126 - arch/arm/boot/dts/sun5i-r8-chip.dts | 282 - arch/arm/boot/dts/sun5i-r8.dtsi | 47 - .../boot/dts/sun5i-reference-design-tablet.dtsi | 194 - arch/arm/boot/dts/sun5i.dtsi | 819 --- arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 82 - arch/arm/boot/dts/sun6i-a31-colombus.dts | 130 - arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 338 - arch/arm/boot/dts/sun6i-a31-i7.dts | 178 - arch/arm/boot/dts/sun6i-a31-m9.dts | 212 - arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 217 - arch/arm/boot/dts/sun6i-a31.dtsi | 1422 ----- arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts | 72 - arch/arm/boot/dts/sun6i-a31s-cs908.dts | 104 - arch/arm/boot/dts/sun6i-a31s-inet-q972.dts | 98 - arch/arm/boot/dts/sun6i-a31s-primo81.dts | 267 - arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 141 - arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 195 - arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 334 - .../dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 182 - arch/arm/boot/dts/sun6i-a31s.dtsi | 61 - .../boot/dts/sun6i-reference-design-tablet.dtsi | 173 - arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 264 - arch/arm/boot/dts/sun7i-a20-bananapi.dts | 333 - arch/arm/boot/dts/sun7i-a20-bananapro.dts | 219 - arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 237 - arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 345 - arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts | 182 - arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 233 - arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 198 - arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts | 137 - arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi | 62 - arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 164 - arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 147 - arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 320 - .../boot/dts/sun7i-a20-linutronix-testbox-v2.dts | 47 - arch/arm/boot/dts/sun7i-a20-m3.dts | 156 - arch/arm/boot/dts/sun7i-a20-mk808c.dts | 184 - .../arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts | 35 - arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 329 - .../boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 34 - arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 326 - .../arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 - arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 216 - .../boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 69 - arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 280 - .../boot/dts/sun7i-a20-olinuxino-micro-emmc.dts | 68 - arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 354 -- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 242 - arch/arm/boot/dts/sun7i-a20-orangepi.dts | 201 - arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 225 - arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 227 - arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 225 - arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 209 - arch/arm/boot/dts/sun7i-a20.dtsi | 1710 ----- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 855 --- arch/arm/boot/dts/sun8i-a23-evb.dts | 117 - arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts | 76 - arch/arm/boot/dts/sun8i-a23-inet86dz.dts | 67 - arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 1 - arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 1 - .../boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 96 - .../boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 86 - arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 73 - arch/arm/boot/dts/sun8i-a23.dtsi | 104 - arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts | 1 - arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 95 - arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 103 - arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts | 1 - arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 226 - arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 57 - arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 275 - arch/arm/boot/dts/sun8i-a33.dtsi | 432 -- .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 281 - arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 422 -- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 464 -- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 506 -- arch/arm/boot/dts/sun8i-a83t.dtsi | 1274 ---- .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 273 - .../boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts | 13 - arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 99 - arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 209 - .../boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts | 13 - arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 50 - arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 238 - .../dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts | 72 - arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi | 11 - arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 14 - arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts | 152 - arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts | 173 - arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 166 - arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 106 - arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 143 - arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 76 - arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 169 - arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 111 - arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 209 - arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 168 - arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 203 - arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 86 - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 242 - arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 135 - arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 79 - arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts | 177 - arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts | 114 - arch/arm/boot/dts/sun8i-h3-zeropi.dts | 85 - arch/arm/boot/dts/sun8i-h3.dtsi | 335 - arch/arm/boot/dts/sun8i-q8-common.dtsi | 118 - arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 311 - .../boot/dts/sun8i-r16-nintendo-nes-classic.dts | 54 - .../dts/sun8i-r16-nintendo-super-nes-classic.dts | 11 - arch/arm/boot/dts/sun8i-r16-parrot.dts | 313 - arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 340 - arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi | 52 - arch/arm/boot/dts/sun8i-r40-feta40i.dtsi | 111 - arch/arm/boot/dts/sun8i-r40-oka40i-c.dts | 203 - arch/arm/boot/dts/sun8i-r40.dtsi | 1326 ---- .../boot/dts/sun8i-reference-design-tablet.dtsi | 224 - arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi | 44 - arch/arm/boot/dts/sun8i-s3-elimo-initium.dts | 29 - arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts | 53 - arch/arm/boot/dts/sun8i-s3-pinecube.dts | 228 - .../arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 - arch/arm/boot/dts/sun8i-t113s.dtsi | 59 - arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts | 231 - arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts | 12 - arch/arm/boot/dts/sun8i-v3-sl631.dtsi | 138 - arch/arm/boot/dts/sun8i-v3.dtsi | 63 - arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 105 - arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 101 - arch/arm/boot/dts/sun8i-v3s.dtsi | 621 -- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 310 - arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 508 -- arch/arm/boot/dts/sun9i-a80-optimus.dts | 510 -- arch/arm/boot/dts/sun9i-a80.dtsi | 1253 ---- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 73 - arch/arm/boot/dts/suniv-f1c100s.dtsi | 330 - arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 76 - arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts | 81 - arch/arm/boot/dts/sunplus-sp7021-achip.dtsi | 84 - arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts | 30 - arch/arm/boot/dts/sunplus-sp7021.dtsi | 307 - arch/arm/boot/dts/sunplus/Makefile | 5 + .../arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi | 84 + .../boot/dts/sunplus/sunplus-sp7021-demo-v3.dts | 30 + arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi | 307 + arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 42 - arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 244 - arch/arm/boot/dts/sunxi-common-regulators.dtsi | 111 - arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 - arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi | 170 - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 979 --- arch/arm/boot/dts/sunxi-itead-core-common.dtsi | 132 - arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 237 - arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi | 180 - .../boot/dts/sunxi-reference-design-tablet.dtsi | 82 - arch/arm/boot/dts/synaptics/Makefile | 6 + .../boot/dts/synaptics/berlin2-sony-nsz-gs7.dts | 43 + arch/arm/boot/dts/synaptics/berlin2.dtsi | 540 ++ .../dts/synaptics/berlin2cd-google-chromecast.dts | 77 + .../dts/synaptics/berlin2cd-valve-steamlink.dts | 79 + arch/arm/boot/dts/synaptics/berlin2cd.dtsi | 583 ++ .../boot/dts/synaptics/berlin2q-marvell-dmp.dts | 144 + arch/arm/boot/dts/synaptics/berlin2q.dtsi | 666 ++ arch/arm/boot/dts/tegra114-asus-tf701t.dts | 807 --- arch/arm/boot/dts/tegra114-dalmore.dts | 1287 ---- arch/arm/boot/dts/tegra114-roth.dts | 1108 ---- arch/arm/boot/dts/tegra114-tn7.dts | 336 - arch/arm/boot/dts/tegra114.dtsi | 850 --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 1487 ----- arch/arm/boot/dts/tegra124-apalis-eval.dts | 255 - arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 257 - arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2076 ------ arch/arm/boot/dts/tegra124-apalis.dtsi | 2068 ------ arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2443 ------- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2080 ------ arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 6694 -------------------- arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 17 - arch/arm/boot/dts/tegra124-nyan-big.dts | 1348 ---- arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 2071 ------ arch/arm/boot/dts/tegra124-nyan-blaze.dts | 1346 ---- arch/arm/boot/dts/tegra124-nyan.dtsi | 836 --- arch/arm/boot/dts/tegra124-peripherals-opp.dtsi | 424 -- arch/arm/boot/dts/tegra124-venice2.dts | 1256 ---- arch/arm/boot/dts/tegra124.dtsi | 1366 ---- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 1525 ----- arch/arm/boot/dts/tegra20-asus-tf101.dts | 1291 ---- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 262 - arch/arm/boot/dts/tegra20-colibri-iris.dts | 244 - arch/arm/boot/dts/tegra20-colibri.dtsi | 776 --- arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi | 165 - arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 253 - arch/arm/boot/dts/tegra20-harmony.dts | 761 --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 132 - arch/arm/boot/dts/tegra20-paz00.dts | 721 --- arch/arm/boot/dts/tegra20-peripherals-opp.dtsi | 1022 --- arch/arm/boot/dts/tegra20-plutux.dts | 97 - arch/arm/boot/dts/tegra20-seaboard.dts | 920 --- arch/arm/boot/dts/tegra20-tamonten.dtsi | 520 -- arch/arm/boot/dts/tegra20-tec.dts | 106 - arch/arm/boot/dts/tegra20-trimslice.dts | 475 -- arch/arm/boot/dts/tegra20-ventana.dts | 755 --- arch/arm/boot/dts/tegra20.dtsi | 1061 ---- arch/arm/boot/dts/tegra30-apalis-eval.dts | 248 - arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 266 - arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 1202 ---- arch/arm/boot/dts/tegra30-apalis.dtsi | 1185 ---- arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi | 63 - .../boot/dts/tegra30-asus-nexus7-grouper-E1565.dts | 9 - .../boot/dts/tegra30-asus-nexus7-grouper-PM269.dts | 9 - .../dts/tegra30-asus-nexus7-grouper-common.dtsi | 1320 ---- .../tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 194 - ...tegra30-asus-nexus7-grouper-memory-timings.dtsi | 1577 ----- .../dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 159 - arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi | 148 - .../boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts | 9 - ...tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 325 - arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 233 - arch/arm/boot/dts/tegra30-asus-tf201.dts | 644 -- arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1032 --- arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1104 ---- arch/arm/boot/dts/tegra30-asus-tf700t.dts | 840 --- .../boot/dts/tegra30-asus-transformer-common.dtsi | 1788 ------ arch/arm/boot/dts/tegra30-beaver.dts | 2138 ------- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 83 - arch/arm/boot/dts/tegra30-cardhu-a04.dts | 93 - arch/arm/boot/dts/tegra30-cardhu.dtsi | 711 --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 198 - arch/arm/boot/dts/tegra30-colibri.dtsi | 1064 ---- arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi | 289 - arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 499 -- arch/arm/boot/dts/tegra30-ouya.dts | 4795 -------------- arch/arm/boot/dts/tegra30-pegatron-chagall.dts | 2858 --------- arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 1648 ----- arch/arm/boot/dts/tegra30.dtsi | 1348 ---- arch/arm/boot/dts/ti/Makefile | 4 + arch/arm/boot/dts/ti/davinci/Makefile | 6 + arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts | 44 + arch/arm/boot/dts/ti/davinci/da850-evm.dts | 466 ++ arch/arm/boot/dts/ti/davinci/da850-lcdk.dts | 425 ++ arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts | 466 ++ arch/arm/boot/dts/ti/davinci/da850.dtsi | 964 +++ arch/arm/boot/dts/ti/keystone/Makefile | 7 + arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi | 438 ++ .../boot/dts/ti/keystone/keystone-k2e-clocks.dtsi | 94 + arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts | 177 + .../boot/dts/ti/keystone/keystone-k2e-netcp.dtsi | 264 + arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi | 198 + arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts | 567 ++ arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts | 447 ++ .../boot/dts/ti/keystone/keystone-k2g-netcp.dtsi | 147 + arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi | 644 ++ .../boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi | 422 ++ .../arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts | 236 + .../boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi | 266 + arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi | 295 + .../boot/dts/ti/keystone/keystone-k2l-clocks.dtsi | 263 + arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts | 165 + .../boot/dts/ti/keystone/keystone-k2l-netcp.dtsi | 246 + arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi | 415 ++ arch/arm/boot/dts/ti/keystone/keystone.dtsi | 354 ++ arch/arm/boot/dts/ti/omap/Makefile | 163 + arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts | 227 + arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts | 273 + arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts | 297 + arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi | 47 + arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi | 401 ++ arch/arm/boot/dts/ti/omap/am335x-base0033.dts | 92 + arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi | 411 ++ arch/arm/boot/dts/ti/omap/am335x-bone.dts | 23 + .../boot/dts/ti/omap/am335x-boneblack-common.dtsi | 30 + .../boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi | 146 + .../boot/dts/ti/omap/am335x-boneblack-wireless.dts | 111 + arch/arm/boot/dts/ti/omap/am335x-boneblack.dts | 174 + arch/arm/boot/dts/ti/omap/am335x-boneblue.dts | 616 ++ .../boot/dts/ti/omap/am335x-bonegreen-common.dtsi | 41 + .../boot/dts/ti/omap/am335x-bonegreen-wireless.dts | 127 + arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts | 14 + arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts | 186 + arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi | 175 + arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts | 516 ++ arch/arm/boot/dts/ti/omap/am335x-evm.dts | 786 +++ arch/arm/boot/dts/ti/omap/am335x-evmsk.dts | 725 +++ arch/arm/boot/dts/ti/omap/am335x-guardian.dts | 745 +++ arch/arm/boot/dts/ti/omap/am335x-icev2.dts | 518 ++ arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi | 300 + arch/arm/boot/dts/ti/omap/am335x-lxm.dts | 347 + .../dts/ti/omap/am335x-moxa-uc-2100-common.dtsi | 225 + arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts | 68 + .../dts/ti/omap/am335x-moxa-uc-8100-common.dtsi | 421 ++ .../boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts | 101 + arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi | 277 + arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts | 549 ++ arch/arm/boot/dts/ti/omap/am335x-nano.dts | 492 ++ .../boot/dts/ti/omap/am335x-netcan-plus-1xx.dts | 231 + .../boot/dts/ti/omap/am335x-netcom-plus-2xx.dts | 239 + .../boot/dts/ti/omap/am335x-netcom-plus-8xx.dts | 271 + .../arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts | 434 ++ .../boot/dts/ti/omap/am335x-osd335x-common.dtsi | 124 + arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi | 236 + arch/arm/boot/dts/ti/omap/am335x-pdu001.dts | 573 ++ arch/arm/boot/dts/ti/omap/am335x-pepper.dts | 637 ++ arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts | 28 + arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi | 343 + arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts | 484 ++ arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts | 24 + arch/arm/boot/dts/ti/omap/am335x-regor.dtsi | 201 + .../dts/ti/omap/am335x-sancloud-bbe-common.dtsi | 67 + .../ti/omap/am335x-sancloud-bbe-extended-wifi.dts | 113 + .../boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts | 50 + arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts | 53 + arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts | 176 + arch/arm/boot/dts/ti/omap/am335x-shc.dts | 559 ++ arch/arm/boot/dts/ti/omap/am335x-sl50.dts | 721 +++ arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts | 23 + arch/arm/boot/dts/ti/omap/am335x-wega.dtsi | 210 + arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi | 779 +++ arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 2322 +++++++ arch/arm/boot/dts/ti/omap/am33xx.dtsi | 714 +++ arch/arm/boot/dts/ti/omap/am3517-craneboard.dts | 171 + arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi | 217 + arch/arm/boot/dts/ti/omap/am3517-evm.dts | 357 ++ arch/arm/boot/dts/ti/omap/am3517-som.dtsi | 243 + arch/arm/boot/dts/ti/omap/am3517.dtsi | 216 + arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts | 24 + arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi | 139 + arch/arm/boot/dts/ti/omap/am3703.dtsi | 14 + arch/arm/boot/dts/ti/omap/am3715.dtsi | 10 + arch/arm/boot/dts/ti/omap/am3874-iceboard.dts | 489 ++ arch/arm/boot/dts/ti/omap/am4372.dtsi | 801 +++ arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts | 422 ++ arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts | 1137 ++++ arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts | 541 ++ arch/arm/boot/dts/ti/omap/am437x-l4.dtsi | 2584 ++++++++ arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts | 177 + arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts | 902 +++ arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts | 1028 +++ arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi | 1003 +++ arch/arm/boot/dts/ti/omap/am57-pruss.dtsi | 226 + arch/arm/boot/dts/ti/omap/am5718.dtsi | 29 + .../boot/dts/ti/omap/am571x-idk-touchscreen.dtso | 32 + arch/arm/boot/dts/ti/omap/am571x-idk.dts | 218 + arch/arm/boot/dts/ti/omap/am5728.dtsi | 34 + arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts | 704 ++ arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi | 203 + .../boot/dts/ti/omap/am572x-idk-touchscreen.dtso | 32 + arch/arm/boot/dts/ti/omap/am572x-idk.dts | 37 + arch/arm/boot/dts/ti/omap/am5748.dtsi | 34 + arch/arm/boot/dts/ti/omap/am574x-idk.dts | 49 + .../boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi | 647 ++ .../boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts | 36 + .../boot/dts/ti/omap/am57xx-beagle-x15-revc.dts | 31 + arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts | 38 + arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts | 628 ++ .../boot/dts/ti/omap/am57xx-commercial-grade.dtsi | 24 + arch/arm/boot/dts/ti/omap/am57xx-evm.dtso | 127 + arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi | 608 ++ .../dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso | 63 + .../dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso | 66 + .../boot/dts/ti/omap/am57xx-industrial-grade.dtsi | 24 + arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts | 176 + arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi | 46 + arch/arm/boot/dts/ti/omap/dm3725.dtsi | 10 + arch/arm/boot/dts/ti/omap/dm8148-evm.dts | 155 + arch/arm/boot/dts/ti/omap/dm8148-t410.dts | 113 + arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi | 379 ++ arch/arm/boot/dts/ti/omap/dm814x.dtsi | 788 +++ arch/arm/boot/dts/ti/omap/dm8168-evm.dts | 213 + arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi | 276 + arch/arm/boot/dts/ti/omap/dm816x.dtsi | 691 ++ arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi | 45 + arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts | 144 + arch/arm/boot/dts/ti/omap/dra62x.dtsi | 19 + arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi | 24 + arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi | 265 + arch/arm/boot/dts/ti/omap/dra7-evm.dts | 592 ++ arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi | 39 + arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi | 24 + arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 4606 ++++++++++++++ arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi | 19 + arch/arm/boot/dts/ti/omap/dra7.dtsi | 1358 ++++ arch/arm/boot/dts/ti/omap/dra71-evm.dts | 316 + arch/arm/boot/dts/ti/omap/dra71x.dtsi | 13 + arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi | 593 ++ arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts | 157 + arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi | 151 + arch/arm/boot/dts/ti/omap/dra72-evm.dts | 127 + arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi | 353 ++ arch/arm/boot/dts/ti/omap/dra72x.dtsi | 110 + .../arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi | 18 + arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi | 639 ++ arch/arm/boot/dts/ti/omap/dra74x-p.dtsi | 27 + arch/arm/boot/dts/ti/omap/dra74x.dtsi | 232 + arch/arm/boot/dts/ti/omap/dra76-evm.dts | 567 ++ arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi | 285 + arch/arm/boot/dts/ti/omap/dra76x.dtsi | 159 + arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 2094 ++++++ arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi | 68 + .../dts/ti/omap/logicpd-som-lv-35xx-devkit.dts | 28 + .../dts/ti/omap/logicpd-som-lv-37xx-devkit.dts | 28 + .../boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi | 237 + arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi | 296 + .../dts/ti/omap/logicpd-torpedo-35xx-devkit.dts | 21 + .../dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts | 15 + .../dts/ti/omap/logicpd-torpedo-37xx-devkit.dts | 96 + .../dts/ti/omap/logicpd-torpedo-baseboard.dtsi | 420 ++ arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi | 203 + .../boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi | 272 + .../boot/dts/ti/omap/motorola-mapphone-common.dtsi | 737 +++ arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi | 55 + arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi | 59 + arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi | 92 + arch/arm/boot/dts/ti/omap/omap2.dtsi | 334 + arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi | 267 + arch/arm/boot/dts/ti/omap/omap2420-h4.dts | 63 + arch/arm/boot/dts/ti/omap/omap2420-n800.dts | 9 + arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts | 9 + arch/arm/boot/dts/ti/omap/omap2420-n810.dts | 75 + .../arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi | 111 + arch/arm/boot/dts/ti/omap/omap2420.dtsi | 262 + arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi | 341 + arch/arm/boot/dts/ti/omap/omap2430-sdp.dts | 70 + arch/arm/boot/dts/ti/omap/omap2430.dtsi | 366 ++ arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi | 1241 ++++ arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts | 47 + arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts | 13 + arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts | 419 ++ arch/arm/boot/dts/ti/omap/omap3-beagle.dts | 436 ++ arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts | 158 + arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts | 60 + arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts | 98 + arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi | 326 + arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi | 131 + arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi | 38 + .../boot/dts/ti/omap/omap3-devkit8000-common.dtsi | 392 ++ .../dts/ti/omap/omap3-devkit8000-lcd-common.dtsi | 73 + .../boot/dts/ti/omap/omap3-devkit8000-lcd43.dts | 34 + .../boot/dts/ti/omap/omap3-devkit8000-lcd70.dts | 34 + arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts | 16 + arch/arm/boot/dts/ti/omap/omap3-echo.dts | 724 +++ arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts | 107 + arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi | 198 + .../dts/ti/omap/omap3-evm-processor-common.dtsi | 224 + arch/arm/boot/dts/ti/omap/omap3-evm.dts | 86 + arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi | 893 +++ arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts | 45 + arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts | 10 + arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts | 152 + arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts | 113 + arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi | 85 + arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts | 162 + arch/arm/boot/dts/ti/omap/omap3-ha.dts | 25 + arch/arm/boot/dts/ti/omap/omap3-igep.dtsi | 247 + .../boot/dts/ti/omap/omap3-igep0020-common.dtsi | 261 + arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts | 59 + arch/arm/boot/dts/ti/omap/omap3-igep0020.dts | 47 + .../boot/dts/ti/omap/omap3-igep0030-common.dtsi | 103 + arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts | 81 + arch/arm/boot/dts/ti/omap/omap3-igep0030.dts | 59 + arch/arm/boot/dts/ti/omap/omap3-ldp.dts | 305 + arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi | 459 ++ arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts | 166 + arch/arm/boot/dts/ti/omap/omap3-n9.dts | 84 + arch/arm/boot/dts/ti/omap/omap3-n900.dts | 1159 ++++ arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi | 504 ++ arch/arm/boot/dts/ti/omap/omap3-n950.dts | 273 + .../dts/ti/omap/omap3-overo-alto35-common.dtsi | 75 + arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts | 19 + arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi | 274 + .../dts/ti/omap/omap3-overo-chestnut43-common.dtsi | 65 + .../boot/dts/ti/omap/omap3-overo-chestnut43.dts | 35 + .../boot/dts/ti/omap/omap3-overo-common-dvi.dtsi | 108 + .../boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi | 163 + .../boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi | 175 + .../ti/omap/omap3-overo-common-peripherals.dtsi | 92 + .../dts/ti/omap/omap3-overo-gallop43-common.dtsi | 55 + arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts | 35 + .../dts/ti/omap/omap3-overo-palo35-common.dtsi | 50 + arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts | 34 + .../dts/ti/omap/omap3-overo-palo43-common.dtsi | 51 + arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts | 35 + .../boot/dts/ti/omap/omap3-overo-storm-alto35.dts | 18 + .../dts/ti/omap/omap3-overo-storm-chestnut43.dts | 35 + .../dts/ti/omap/omap3-overo-storm-gallop43.dts | 35 + .../boot/dts/ti/omap/omap3-overo-storm-palo35.dts | 34 + .../boot/dts/ti/omap/omap3-overo-storm-palo43.dts | 35 + .../boot/dts/ti/omap/omap3-overo-storm-summit.dts | 27 + .../boot/dts/ti/omap/omap3-overo-storm-tobi.dts | 19 + .../boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts | 18 + arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi | 32 + .../dts/ti/omap/omap3-overo-summit-common.dtsi | 29 + arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts | 27 + .../boot/dts/ti/omap/omap3-overo-tobi-common.dtsi | 37 + arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts | 19 + .../dts/ti/omap/omap3-overo-tobiduo-common.dtsi | 59 + arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts | 18 + arch/arm/boot/dts/ti/omap/omap3-overo.dtsi | 31 + arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts | 67 + arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts | 62 + .../arm/boot/dts/ti/omap/omap3-pandora-common.dtsi | 730 +++ .../dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi | 73 + arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi | 138 + arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts | 76 + arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts | 48 + arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts | 44 + arch/arm/boot/dts/ti/omap/omap3-sniper.dts | 251 + arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi | 336 + arch/arm/boot/dts/ti/omap/omap3-thunder.dts | 126 + arch/arm/boot/dts/ti/omap/omap3-zoom3.dts | 231 + arch/arm/boot/dts/ti/omap/omap3.dtsi | 1039 +++ arch/arm/boot/dts/ti/omap/omap3430-sdp.dts | 195 + arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi | 233 + .../boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi | 310 + arch/arm/boot/dts/ti/omap/omap34xx.dtsi | 198 + .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 268 + arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi | 118 + .../ti/omap/omap36xx-omap3430es2plus-clocks.dtsi | 237 + arch/arm/boot/dts/ti/omap/omap36xx.dtsi | 250 + arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi | 1790 ++++++ arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi | 38 + .../boot/dts/ti/omap/omap4-droid-bionic-xt875.dts | 55 + arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts | 157 + arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts | 194 + arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi | 249 + arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts | 450 ++ arch/arm/boot/dts/ti/omap/omap4-kc1.dts | 179 + arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi | 497 ++ arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 2483 ++++++++ arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi | 44 + arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts | 17 + arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi | 607 ++ arch/arm/boot/dts/ti/omap/omap4-panda-es.dts | 114 + arch/arm/boot/dts/ti/omap/omap4-panda.dts | 13 + arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts | 14 + arch/arm/boot/dts/ti/omap/omap4-sdp.dts | 717 +++ arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts | 68 + .../dts/ti/omap/omap4-var-om44customboard.dtsi | 232 + .../boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi | 75 + arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi | 325 + arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts | 14 + arch/arm/boot/dts/ti/omap/omap4.dtsi | 868 +++ arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi | 16 + arch/arm/boot/dts/ti/omap/omap443x.dtsi | 85 + arch/arm/boot/dts/ti/omap/omap4460.dtsi | 127 + arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi | 26 + arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi | 1483 +++++ arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi | 755 +++ arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts | 697 ++ arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi | 25 + arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi | 25 + arch/arm/boot/dts/ti/omap/omap5-igep0050.dts | 136 + arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi | 456 ++ arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2502 ++++++++ arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts | 52 + arch/arm/boot/dts/ti/omap/omap5-uevm.dts | 234 + arch/arm/boot/dts/ti/omap/omap5.dtsi | 831 +++ arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi | 1362 ++++ arch/arm/boot/dts/ti/omap/twl4030.dtsi | 160 + arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi | 39 + arch/arm/boot/dts/ti/omap/twl6030.dtsi | 105 + arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi | 35 + arch/arm/boot/dts/tny_a9260.dts | 14 - arch/arm/boot/dts/tny_a9260_common.dtsi | 112 - arch/arm/boot/dts/tny_a9263.dts | 126 - arch/arm/boot/dts/tny_a9g20.dts | 14 - arch/arm/boot/dts/twl4030.dtsi | 160 - arch/arm/boot/dts/twl4030_omap3.dtsi | 39 - arch/arm/boot/dts/twl6030.dtsi | 105 - arch/arm/boot/dts/twl6030_omap4.dtsi | 35 - arch/arm/boot/dts/uniphier-ld4-ref.dts | 88 - arch/arm/boot/dts/uniphier-ld4.dtsi | 431 -- arch/arm/boot/dts/uniphier-ld6b-ref.dts | 103 - arch/arm/boot/dts/uniphier-ld6b.dtsi | 30 - arch/arm/boot/dts/uniphier-pinctrl.dtsi | 223 - arch/arm/boot/dts/uniphier-pro4-ace.dts | 109 - arch/arm/boot/dts/uniphier-pro4-ref.dts | 118 - arch/arm/boot/dts/uniphier-pro4-sanji.dts | 96 - arch/arm/boot/dts/uniphier-pro4.dtsi | 734 --- arch/arm/boot/dts/uniphier-pro5-epcore.dts | 76 - arch/arm/boot/dts/uniphier-pro5-proex.dts | 59 - arch/arm/boot/dts/uniphier-pro5.dtsi | 707 --- arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 105 - arch/arm/boot/dts/uniphier-pxs2-vodka.dts | 98 - arch/arm/boot/dts/uniphier-pxs2.dtsi | 845 --- arch/arm/boot/dts/uniphier-ref-daughter.dtsi | 14 - arch/arm/boot/dts/uniphier-sld8-ref.dts | 92 - arch/arm/boot/dts/uniphier-sld8.dtsi | 436 -- arch/arm/boot/dts/uniphier-support-card.dtsi | 27 - arch/arm/boot/dts/unisoc/Makefile | 4 + .../boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts | 50 + .../arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts | 50 + arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 147 + arch/arm/boot/dts/usb_a9260.dts | 31 - arch/arm/boot/dts/usb_a9260_common.dtsi | 146 - arch/arm/boot/dts/usb_a9263.dts | 174 - arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi | 95 - arch/arm/boot/dts/usb_a9g20.dts | 13 - arch/arm/boot/dts/usb_a9g20_common.dtsi | 27 - arch/arm/boot/dts/usb_a9g20_lpw.dts | 30 - arch/arm/boot/dts/versatile-ab-ib2.dts | 30 - arch/arm/boot/dts/versatile-ab.dts | 450 -- arch/arm/boot/dts/versatile-pb.dts | 114 - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 494 -- arch/arm/boot/dts/vexpress-v2m.dtsi | 509 -- arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 255 - arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 636 -- arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 225 - arch/arm/boot/dts/vexpress-v2p-ca9.dts | 310 - arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 152 - arch/arm/boot/dts/vf-colibri.dtsi | 350 - arch/arm/boot/dts/vf500-colibri-eval-v3.dts | 18 - arch/arm/boot/dts/vf500-colibri.dtsi | 69 - arch/arm/boot/dts/vf500.dtsi | 64 - arch/arm/boot/dts/vf610-bk4.dts | 537 -- arch/arm/boot/dts/vf610-colibri-eval-v3.dts | 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arch/arm/boot/dts/vt8500/wm8505-ref.dts | 35 + arch/arm/boot/dts/vt8500/wm8505.dtsi | 294 + arch/arm/boot/dts/vt8500/wm8650-mid.dts | 36 + arch/arm/boot/dts/vt8500/wm8650.dtsi | 241 + arch/arm/boot/dts/vt8500/wm8750-apc8750.dts | 29 + arch/arm/boot/dts/vt8500/wm8750.dtsi | 351 + arch/arm/boot/dts/vt8500/wm8850-w70v2.dts | 47 + arch/arm/boot/dts/vt8500/wm8850.dtsi | 312 + arch/arm/boot/dts/wm8505-ref.dts | 35 - arch/arm/boot/dts/wm8505.dtsi | 294 - arch/arm/boot/dts/wm8650-mid.dts | 36 - arch/arm/boot/dts/wm8650.dtsi | 241 - arch/arm/boot/dts/wm8750-apc8750.dts | 29 - arch/arm/boot/dts/wm8750.dtsi | 351 - arch/arm/boot/dts/wm8850-w70v2.dts | 47 - arch/arm/boot/dts/wm8850.dtsi | 312 - arch/arm/boot/dts/xen/Makefile | 3 + arch/arm/boot/dts/xen/xenvm-4.2.dts | 82 + arch/arm/boot/dts/xenvm-4.2.dts | 82 - arch/arm/boot/dts/xilinx/Makefile | 17 + arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 539 ++ arch/arm/boot/dts/xilinx/zynq-cc108.dts | 75 + arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts | 144 + arch/arm/boot/dts/xilinx/zynq-microzed.dts | 88 + arch/arm/boot/dts/xilinx/zynq-parallella.dts | 88 + arch/arm/boot/dts/xilinx/zynq-zc702.dts | 424 ++ arch/arm/boot/dts/xilinx/zynq-zc706.dts | 324 + arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts | 95 + arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts | 64 + arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts | 64 + arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts | 77 + arch/arm/boot/dts/xilinx/zynq-zed.dts | 62 + arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi | 112 + arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts | 15 + arch/arm/boot/dts/xilinx/zynq-zturn.dts | 15 + arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts | 68 + arch/arm/boot/dts/xilinx/zynq-zybo.dts | 63 + arch/arm/boot/dts/zynq-7000.dtsi | 539 -- arch/arm/boot/dts/zynq-cc108.dts | 75 - arch/arm/boot/dts/zynq-ebaz4205.dts | 144 - arch/arm/boot/dts/zynq-microzed.dts | 88 - arch/arm/boot/dts/zynq-parallella.dts | 88 - arch/arm/boot/dts/zynq-zc702.dts | 424 -- arch/arm/boot/dts/zynq-zc706.dts | 324 - arch/arm/boot/dts/zynq-zc770-xm010.dts | 95 - arch/arm/boot/dts/zynq-zc770-xm011.dts | 64 - arch/arm/boot/dts/zynq-zc770-xm012.dts | 64 - arch/arm/boot/dts/zynq-zc770-xm013.dts | 77 - arch/arm/boot/dts/zynq-zed.dts | 62 - arch/arm/boot/dts/zynq-zturn-common.dtsi | 112 - arch/arm/boot/dts/zynq-zturn-v5.dts | 15 - arch/arm/boot/dts/zynq-zturn.dts | 15 - arch/arm/boot/dts/zynq-zybo-z7.dts | 68 - arch/arm/boot/dts/zynq-zybo.dts | 63 - .../allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts | 2 +- .../dts/allwinner/sun50i-h5-bananapi-m2-plus.dts | 2 +- .../dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi | 2 +- .../allwinner/sun50i-h5-libretech-all-h3-cc.dts | 2 +- .../allwinner/sun50i-h5-libretech-all-h3-it.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 2 +- .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 2 +- arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts | 2 +- .../arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 2 +- .../boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts | 2 +- .../boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts | 2 +- arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 2 +- .../boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts | 2 +- .../boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts | 2 +- arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- .../boot/dts/rockchip/rk3399pro-rock-pi-n10.dts | 2 +- .../arm64/boot/dts/socionext/uniphier-pinctrl.dtsi | 2 +- .../boot/dts/socionext/uniphier-ref-daughter.dtsi | 2 +- .../boot/dts/socionext/uniphier-support-card.dtsi | 2 +- 5257 files changed, 730092 insertions(+), 729826 deletions(-) create mode 100644 arch/arm/boot/dts/actions/Makefile create mode 100644 arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts create mode 100644 arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts create mode 100644 arch/arm/boot/dts/actions/owl-s500-guitar.dtsi create mode 100644 arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts create mode 100644 arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi create mode 100644 arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts create mode 100644 arch/arm/boot/dts/actions/owl-s500-sparky.dts create mode 100644 arch/arm/boot/dts/actions/owl-s500.dtsi create mode 100644 arch/arm/boot/dts/airoha/Makefile create mode 100644 arch/arm/boot/dts/airoha/en7523-evb.dts create mode 100644 arch/arm/boot/dts/airoha/en7523.dtsi delete mode 100644 arch/arm/boot/dts/aks-cdu.dts create mode 100644 arch/arm/boot/dts/allwinner/Makefile create mode 100644 arch/arm/boot/dts/allwinner/axp152.dtsi create mode 100644 arch/arm/boot/dts/allwinner/axp209.dtsi create mode 100644 arch/arm/boot/dts/allwinner/axp223.dtsi create mode 100644 arch/arm/boot/dts/allwinner/axp22x.dtsi create mode 100644 arch/arm/boot/dts/allwinner/axp809.dtsi create mode 100644 arch/arm/boot/dts/allwinner/axp81x.dtsi create mode 100644 arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts create mode 100644 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arch/arm/boot/dts/zynq-zed.dts delete mode 100644 arch/arm/boot/dts/zynq-zturn-common.dtsi delete mode 100644 arch/arm/boot/dts/zynq-zturn-v5.dts delete mode 100644 arch/arm/boot/dts/zynq-zturn.dts delete mode 100644 arch/arm/boot/dts/zynq-zybo-z7.dts delete mode 100644 arch/arm/boot/dts/zynq-zybo.dts diff --git a/MAINTAINERS b/MAINTAINERS index 9b7d23efc270..f304b54e33d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1664,9 +1664,9 @@ F: Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml F: Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml F: Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml -F: arch/arm/boot/dts/arm-realview-* -F: arch/arm/boot/dts/integrator* -F: arch/arm/boot/dts/versatile* +F: arch/arm/boot/dts/arm/arm-realview-* +F: arch/arm/boot/dts/arm/integrator* +F: arch/arm/boot/dts/arm/versatile* F: arch/arm/mach-versatile/ F: drivers/bus/arm-integrator-lm.c F: drivers/clk/versatile/ @@ -1837,7 +1837,7 @@ F: Documentation/devicetree/bindings/net/actions,owl-emac.yaml F: Documentation/devicetree/bindings/pinctrl/actions,* F: Documentation/devicetree/bindings/power/actions,owl-sps.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt -F: arch/arm/boot/dts/owl-* +F: arch/arm/boot/dts/actions/ F: arch/arm/mach-actions/ F: arch/arm64/boot/dts/actions/ F: drivers/clk/actions/ @@ -1910,7 +1910,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-amlogic@lists.infradead.org S: Maintained W: http://linux-meson.com/ -F: arch/arm/boot/dts/meson* +F: arch/arm/boot/dts/amlogic/ F: arch/arm/mach-meson/ F: arch/arm64/boot/dts/amlogic/ F: drivers/mmc/host/meson* @@ -1924,7 +1924,7 @@ M: Tsahee Zidenberg M: Antoine Tenart L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/alpine* +F: arch/arm/boot/dts/amazon/ F: arch/arm/mach-alpine/ F: arch/arm64/boot/dts/amazon/ F: drivers/*/*alpine* @@ -1995,7 +1995,7 @@ M: Lars Persson L: linux-arm-kernel@axis.com S: Maintained F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt -F: arch/arm/boot/dts/artpec6* +F: arch/arm/boot/dts/axis/ F: arch/arm/mach-artpec F: drivers/clk/axis F: drivers/crypto/axis @@ -2023,7 +2023,7 @@ S: Supported Q: https://patchwork.ozlabs.org/project/linux-aspeed/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git F: Documentation/devicetree/bindings/arm/aspeed/ -F: arch/arm/boot/dts/aspeed-* +F: arch/arm/boot/dts/aspeed/ F: arch/arm/mach-aspeed/ N: aspeed @@ -2042,8 +2042,7 @@ ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/ecx-*.dts* -F: arch/arm/boot/dts/highbank.dts +F: arch/arm/boot/dts/calxeda/ F: arch/arm/mach-highbank/ ARM/CAVIUM THUNDER NETWORK DRIVER @@ -2091,7 +2090,7 @@ ARM/CONEXANT DIGICOLOR MACHINE SUPPORT M: Baruch Siach L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/cx92755* +F: arch/arm/boot/dts/cnxt/ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS @@ -2130,7 +2129,7 @@ F: Documentation/devicetree/bindings/arm/gemini.yaml F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.yaml -F: arch/arm/boot/dts/gemini* +F: arch/arm/boot/dts/gemini/ F: arch/arm/mach-gemini/ F: drivers/crypto/gemini/ F: drivers/net/ethernet/cortina/ @@ -2183,7 +2182,8 @@ R: NXP Linux Team L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm64/boot/dts/freescale/ +F: arch/arm/boot/dts/nxp/imx/ +F: arch/arm/boot/dts/nxp/mxs/ X: arch/arm64/boot/dts/freescale/fsl-* X: arch/arm64/boot/dts/freescale/qoriq-* X: drivers/media/i2c/ @@ -2196,7 +2196,7 @@ M: Li Yang L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm/boot/dts/ls1021a* +F: arch/arm/boot/dts/nxp/ls/ F: arch/arm64/boot/dts/freescale/fsl-* F: arch/arm64/boot/dts/freescale/qoriq-* @@ -2208,7 +2208,7 @@ R: Stefan Agner L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm/boot/dts/vf* +F: arch/arm/boot/dts/nxp/vf/ F: arch/arm/mach-imx/*vf610* ARM/GUMSTIX MACHINE SUPPORT @@ -2222,9 +2222,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported W: http://www.hisilicon.com T: git https://github.com/hisilicon/linux-hisi.git -F: arch/arm/boot/dts/hi3* -F: arch/arm/boot/dts/hip* -F: arch/arm/boot/dts/hisi* +F: arch/arm/boot/dts/hisilicon/ F: arch/arm/mach-hisi/ F: arch/arm64/boot/dts/hisilicon/ @@ -2246,8 +2244,7 @@ F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst -F: arch/arm/boot/dts/hpe-bmc* -F: arch/arm/boot/dts/hpe-gxp* +F: arch/arm/boot/dts/hpe/ F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c @@ -2261,7 +2258,7 @@ M: Javier Martinez Canillas L: linux-omap@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/omap3-igep* +F: arch/arm/boot/dts/ti/omap/omap3-igep* ARM/INTEL IXP4XX ARM ARCHITECTURE M: Linus Walleij @@ -2274,7 +2271,7 @@ F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml -F: arch/arm/boot/dts/intel-ixp* +F: arch/arm/boot/dts/intel/ixp/ F: arch/arm/mach-ixp4xx/ F: drivers/bus/intel-ixp4xx-eb.c F: drivers/clocksource/timer-ixp4xx.c @@ -2306,7 +2303,7 @@ M: Vladimir Zapolskiy L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt -F: arch/arm/boot/dts/lpc43* +F: arch/arm/boot/dts/nxp/lpc/lpc43* F: drivers/i2c/busses/i2c-lpc2k.c F: drivers/memory/pl172.c F: drivers/mtd/spi-nor/controllers/nxp-spifi.c @@ -2319,7 +2316,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/vzapolskiy/linux-lpc32xx.git F: Documentation/devicetree/bindings/i2c/i2c-pnx.txt -F: arch/arm/boot/dts/lpc32* +F: arch/arm/boot/dts/nxp/lpc/lpc32* F: arch/arm/mach-lpc32xx/ F: drivers/i2c/busses/i2c-pnx.c F: drivers/net/ethernet/nxp/lpc_eth.c @@ -2337,8 +2334,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt F: Documentation/devicetree/bindings/soc/dove/ -F: arch/arm/boot/dts/dove* -F: arch/arm/boot/dts/orion5x* +F: arch/arm/boot/dts/marvell/dove* +F: arch/arm/boot/dts/marvell/orion5x* F: arch/arm/mach-dove/ F: arch/arm/mach-mv78xx0/ F: arch/arm/mach-orion5x/ @@ -2353,8 +2350,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ -F: arch/arm/boot/dts/armada* -F: arch/arm/boot/dts/kirkwood* +F: arch/arm/boot/dts/marvell/armada* +F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ F: arch/arm64/boot/dts/marvell/armada* @@ -2388,10 +2385,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained W: https://mtk.wiki.kernel.org/ C: irc://irc.libera.chat/linux-mediatek -F: arch/arm/boot/dts/mt2* -F: arch/arm/boot/dts/mt6* -F: arch/arm/boot/dts/mt7* -F: arch/arm/boot/dts/mt8* +F: arch/arm/boot/dts/mediatek/ F: arch/arm/mach-mediatek/ F: arch/arm64/boot/dts/mediatek/ F: drivers/soc/mediatek/ @@ -2415,10 +2409,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported W: http://www.linux4sam.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git -F: arch/arm/boot/dts/at91*.dts -F: arch/arm/boot/dts/at91*.dtsi -F: arch/arm/boot/dts/sama*.dts -F: arch/arm/boot/dts/sama*.dtsi +F: arch/arm/boot/dts/microchip/at91* +F: arch/arm/boot/dts/microchip/sama* F: arch/arm/include/debug/at91.S F: arch/arm/mach-at91/ F: drivers/memory/atmel* @@ -2447,7 +2439,7 @@ M: Taichi Sugaya M: Takao Orito L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/milbeaut* +F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut @@ -2461,7 +2453,7 @@ T: git git://github.com/linux-chenxing/linux.git F: Documentation/devicetree/bindings/arm/mstar/* F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml -F: arch/arm/boot/dts/mstar-* +F: arch/arm/boot/dts/sigmastar/ F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/clocksource/timer-msc313e.c @@ -2480,7 +2472,7 @@ F: Documentation/devicetree/bindings/arm/ste-* F: Documentation/devicetree/bindings/arm/ux500.yaml F: Documentation/devicetree/bindings/arm/ux500/ F: Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml -F: arch/arm/boot/dts/ste-* +F: arch/arm/boot/dts/st/ste-* F: arch/arm/mach-nomadik/ F: arch/arm/mach-ux500/ F: drivers/clk/clk-nomadik.c @@ -2510,7 +2502,7 @@ F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* F: Documentation/devicetree/bindings/arm/npcm/* F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml -F: arch/arm/boot/dts/nuvoton-npcm* +F: arch/arm/boot/dts/nuvoton/nuvoton-npcm* F: arch/arm/mach-npcm/ F: arch/arm64/boot/dts/nuvoton/ F: drivers/*/*/*npcm* @@ -2525,7 +2517,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* -F: arch/arm/boot/dts/nuvoton-wpcm450* +F: arch/arm/boot/dts/nuvoton/nuvoton-wpcm450* F: arch/arm/configs/wpcm450_defconfig F: arch/arm/mach-npcm/wpcm450.c F: drivers/*/*/*wpcm* @@ -2572,8 +2564,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git F: Documentation/devicetree/bindings/*/qcom* F: Documentation/devicetree/bindings/soc/qcom/ -F: arch/arm/boot/dts/qcom-*.dts -F: arch/arm/boot/dts/qcom-*.dtsi +F: arch/arm/boot/dts/qcom/ F: arch/arm/configs/qcom_defconfig F: arch/arm/mach-qcom/ F: arch/arm64/boot/dts/qcom/ @@ -2616,7 +2607,7 @@ F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.yaml -F: arch/arm/boot/dts/rda8810pl-* +F: arch/arm/boot/dts/unisoc/ F: drivers/clocksource/timer-rda.c F: drivers/gpio/gpio-rda.c F: drivers/irqchip/irq-rda-intc.c @@ -2628,7 +2619,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/realtek.yaml -F: arch/arm/boot/dts/rtd* +F: arch/arm/boot/dts/realtek/ F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ @@ -2642,13 +2633,7 @@ C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml F: Documentation/devicetree/bindings/soc/renesas/ -F: arch/arm/boot/dts/emev2* -F: arch/arm/boot/dts/gr-peach* -F: arch/arm/boot/dts/iwg20d-q7* -F: arch/arm/boot/dts/r7s* -F: arch/arm/boot/dts/r8a* -F: arch/arm/boot/dts/r9a* -F: arch/arm/boot/dts/sh* +F: arch/arm/boot/dts/renesas/ F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ @@ -2681,8 +2666,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml -F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv11* +F: arch/arm/boot/dts/rockchip/ F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* @@ -2706,9 +2690,7 @@ F: Documentation/devicetree/bindings/arm/samsung/ F: Documentation/devicetree/bindings/hwinfo/samsung,* F: Documentation/devicetree/bindings/power/pd-samsung.yaml F: Documentation/devicetree/bindings/soc/samsung/ -F: arch/arm/boot/dts/exynos* -F: arch/arm/boot/dts/s3c* -F: arch/arm/boot/dts/s5p* +F: arch/arm/boot/dts/samsung/ F: arch/arm/mach-exynos*/ F: arch/arm/mach-s3c/ F: arch/arm/mach-s5p*/ @@ -2768,7 +2750,7 @@ M: Dinh Nguyen S: Maintained W: http://www.rocketboards.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git -F: arch/arm/boot/dts/socfpga* +F: arch/arm/boot/dts/intel/socfpga/ F: arch/arm/configs/socfpga_defconfig F: arch/arm/mach-socfpga/ F: arch/arm64/boot/dts/altera/ @@ -2801,7 +2783,7 @@ S: Maintained W: http://www.stlinux.com F: Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml -F: arch/arm/boot/dts/sti* +F: arch/arm/boot/dts/st/sti* F: arch/arm/mach-sti/ F: drivers/ata/ahci_st.c F: drivers/char/hw_random/st-rng.c @@ -2834,7 +2816,7 @@ L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-next -F: arch/arm/boot/dts/stm32* +F: arch/arm/boot/dts/st/stm32* F: arch/arm/mach-stm32/ F: drivers/clocksource/armv7m_systick.c N: stm32 @@ -2849,7 +2831,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml -F: arch/arm/boot/dts/sunplus-sp7021*.dts* +F: arch/arm/boot/dts/sunplus/ F: arch/arm/configs/sp7021_*defconfig F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c @@ -2863,7 +2845,7 @@ M: Jisheng Zhang M: Sebastian Hesselbarth L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/berlin* +F: arch/arm/boot/dts/synaptics/ F: arch/arm/mach-berlin/ F: arch/arm64/boot/dts/synaptics/ @@ -2905,7 +2887,7 @@ M: Santosh Shilimkar L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -F: arch/arm/boot/dts/keystone-* +F: arch/arm/boot/dts/ti/keystone/ F: arch/arm/mach-keystone/ ARM/TEXAS INSTRUMENT KEYSTONE CLOCK FRAMEWORK @@ -2970,7 +2952,7 @@ F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml -F: arch/arm/boot/dts/uniphier* +F: arch/arm/boot/dts/socionext/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ F: arch/arm/mm/cache-uniphier.c @@ -2995,7 +2977,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: */*/*/vexpress* F: */*/vexpress* -F: arch/arm/boot/dts/vexpress* +F: arch/arm/boot/dts/arm/vexpress* F: arch/arm/mach-versatile/ F: arch/arm64/boot/dts/arm/ F: drivers/clk/versatile/clk-vexpress-osc.c @@ -3402,10 +3384,10 @@ AXENTIA ARM DEVICES M: Peter Rosin L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/at91-linea.dtsi -F: arch/arm/boot/dts/at91-natte.dtsi -F: arch/arm/boot/dts/at91-nattis-2-natte-2.dts -F: arch/arm/boot/dts/at91-tse850-3.dts +F: arch/arm/boot/dts/microchip/at91-linea.dtsi +F: arch/arm/boot/dts/microchip/at91-natte.dtsi +F: arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts +F: arch/arm/boot/dts/microchip/at91-tse850-3.dts AXENTIA ASOC DRIVERS M: Peter Rosin @@ -3961,10 +3943,10 @@ M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/bcm-ns.dtsi -F: arch/arm/boot/dts/bcm470* -F: arch/arm/boot/dts/bcm5301* -F: arch/arm/boot/dts/bcm953012* +F: arch/arm/boot/dts/broadcom/bcm-ns.dtsi +F: arch/arm/boot/dts/broadcom/bcm470* +F: arch/arm/boot/dts/broadcom/bcm5301* +F: arch/arm/boot/dts/broadcom/bcm953012* F: arch/arm/mach-bcm/bcm_5301x.c BROADCOM BCM53573 ARM ARCHITECTURE @@ -3973,8 +3955,8 @@ M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/bcm47189* -F: arch/arm/boot/dts/bcm53573* +F: arch/arm/boot/dts/broadcom/bcm47189* +F: arch/arm/boot/dts/broadcom/bcm53573* BROADCOM BCM63XX/BCM33XX UDC DRIVER M: Kevin Cernekee @@ -3989,7 +3971,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git https://github.com/broadcom/stblinux.git F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml -F: arch/arm/boot/dts/bcm7*.dts* +F: arch/arm/boot/dts/broadcom/bcm7*.dts* F: arch/arm/include/asm/hardware/cache-b15-rac.h F: arch/arm/mach-bcm/*brcmstb* F: arch/arm/mm/cache-b15-rac.c @@ -5990,15 +5972,15 @@ DH ELECTRONICS IMX6 DHCOM/DHCOR BOARD SUPPORT M: Christoph Niedermaier L: kernel@dh-electronics.com S: Maintained -F: arch/arm/boot/dts/imx6*-dhcom-* -F: arch/arm/boot/dts/imx6*-dhcor-* +F: arch/arm/boot/dts/nxp/imx/imx6*-dhcom-* +F: arch/arm/boot/dts/nxp/imx/imx6*-dhcor-* DH ELECTRONICS STM32MP1 DHCOM/DHCOR BOARD SUPPORT M: Marek Vasut L: kernel@dh-electronics.com S: Maintained -F: arch/arm/boot/dts/stm32mp1*-dhcom-* -F: arch/arm/boot/dts/stm32mp1*-dhcor-* +F: arch/arm/boot/dts/st/stm32mp1*-dhcom-* +F: arch/arm/boot/dts/st/stm32mp1*-dhcor-* DIALOG SEMICONDUCTOR DRIVERS M: Support Opensource @@ -11732,7 +11714,7 @@ LEGO MINDSTORMS EV3 R: David Lechner S: Maintained F: Documentation/devicetree/bindings/power/supply/lego,ev3-battery.yaml -F: arch/arm/boot/dts/da850-lego-ev3.dts +F: arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts F: drivers/power/supply/lego_ev3_battery.c LEGO USB Tower driver @@ -14026,12 +14008,12 @@ MIKROTIK CRS3XX 98DX3236 BOARD SUPPORT M: Luka Kovacic M: Luka Perkov S: Maintained -F: arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts -F: arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts -F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER M: Sakari Ailus @@ -14134,7 +14116,7 @@ R: Lubomir Rintel L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd Fixes T: git git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp.git -F: arch/arm/boot/dts/mmp* +F: arch/arm/boot/dts/marvell/mmp* F: arch/arm/mach-mmp/ F: include/linux/soc/mmp/ @@ -15265,13 +15247,7 @@ M: Tony Lindgren L: linux-omap@vger.kernel.org L: devicetree@vger.kernel.org S: Maintained -F: arch/arm/boot/dts/*am3* -F: arch/arm/boot/dts/*am4* -F: arch/arm/boot/dts/*am5* -F: arch/arm/boot/dts/*dra7* -F: arch/arm/boot/dts/*omap* -F: arch/arm/boot/dts/logicpd-som-lv* -F: arch/arm/boot/dts/logicpd-torpedo* +F: arch/arm/boot/dts/ti/omap/ OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) L: linux-omap@vger.kernel.org @@ -15379,7 +15355,7 @@ OMAP/NEWFLOW NANOBONE MACHINE SUPPORT M: Mark Jackson L: linux-omap@vger.kernel.org S: Maintained -F: arch/arm/boot/dts/am335x-nano.dts +F: arch/arm/boot/dts/ti/omap/am335x-nano.dts OMAP1 SUPPORT M: Aaro Koskinen @@ -17126,7 +17102,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/hzhuang1/linux.git T: git git://github.com/rjarzmik/linux.git -F: arch/arm/boot/dts/pxa* +F: arch/arm/boot/dts/intel/pxa/ F: arch/arm/mach-pxa/ F: drivers/dma/pxa* F: drivers/pcmcia/pxa2xx* @@ -18755,7 +18731,7 @@ SANCLOUD BEAGLEBONE ENHANCED DEVICE TREE M: Paul Barker R: Marc Murphy S: Supported -F: arch/arm/boot/dts/am335x-sancloud* +F: arch/arm/boot/dts/ti/omap/am335x-sancloud* SC1200 WDT DRIVER M: Zwane Mwaikambo @@ -19581,15 +19557,15 @@ F: include/uapi/linux/raid/ SOLIDRUN CLEARFOG SUPPORT M: Russell King S: Maintained -F: arch/arm/boot/dts/armada-388-clearfog* -F: arch/arm/boot/dts/armada-38x-solidrun-* +F: arch/arm/boot/dts/marvell/armada-388-clearfog* +F: arch/arm/boot/dts/marvell/armada-38x-solidrun-* SOLIDRUN CUBOX-I/HUMMINGBOARD SUPPORT M: Russell King S: Maintained -F: arch/arm/boot/dts/imx6*-cubox-i* -F: arch/arm/boot/dts/imx6*-hummingboard* -F: arch/arm/boot/dts/imx6*-sr-* +F: arch/arm/boot/dts/nxp/imx/imx6*-cubox-i* +F: arch/arm/boot/dts/nxp/imx/imx6*-hummingboard* +F: arch/arm/boot/dts/nxp/imx/imx6*-sr-* SONIC NETWORK DRIVER M: Thomas Bogendoerfer @@ -19874,7 +19850,7 @@ M: soc@kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://www.st.com/spear -F: arch/arm/boot/dts/spear* +F: arch/arm/boot/dts/st/spear* F: arch/arm/mach-spear/ F: drivers/clk/spear/ F: drivers/pinctrl/spear/ @@ -21082,7 +21058,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git F: Documentation/devicetree/bindings/i2c/i2c-davinci.txt -F: arch/arm/boot/dts/da850* +F: arch/arm/boot/dts/ti/davinci/ F: arch/arm/mach-davinci/ F: drivers/i2c/busses/i2c-davinci.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c6798925fe45..efe38eb25301 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,1718 +1,41 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_ALPINE) += \ - alpine-db.dtb -dtb-$(CONFIG_MACH_ARTPEC6) += \ - artpec6-devboard.dtb -dtb-$(CONFIG_MACH_ASM9260) += \ - alphascale-asm9260-devkit.dtb -# Keep at91 dtb files sorted alphabetically for each SoC -dtb-$(CONFIG_SOC_AT91RM9200) += \ - at91rm9200ek.dtb \ - mpa1600.dtb -dtb-$(CONFIG_SOC_AT91SAM9) += \ - animeo_ip.dtb \ - at91-qil_a9260.dtb \ - aks-cdu.dtb \ - ethernut5.dtb \ - evk-pro3.dtb \ - tny_a9260.dtb \ - usb_a9260.dtb \ - at91sam9260ek.dtb \ - at91sam9261ek.dtb \ - at91sam9263ek.dtb \ - at91-sam9_l9260.dtb \ - tny_a9263.dtb \ - usb_a9263.dtb \ - at91-foxg20.dtb \ - at91-kizbox.dtb \ - at91-lmu5000.dtb \ - at91sam9g20ek.dtb \ - at91sam9g20ek_2mmc.dtb \ - tny_a9g20.dtb \ - usb_a9g20.dtb \ - usb_a9g20_lpw.dtb \ - at91sam9m10g45ek.dtb \ - pm9g45.dtb \ - at91sam9n12ek.dtb \ - at91sam9rlek.dtb \ - at91-ariag25.dtb \ - at91-ariettag25.dtb \ - at91-cosino_mega2560.dtb \ - at91-kizboxmini-base.dtb \ - at91-kizboxmini-mb.dtb \ - at91-kizboxmini-rd.dtb \ - at91-q5xr5.dtb \ - at91-smartkiz.dtb \ - at91-wb45n.dtb \ - at91sam9g15ek.dtb \ - at91sam9g25-gardena-smart-gateway.dtb \ - at91sam9g25ek.dtb \ - at91sam9g35ek.dtb \ - at91sam9x25ek.dtb \ - at91sam9x35ek.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sam9x60_curiosity := -@ -DTC_FLAGS_at91-sam9x60ek := -@ -dtb-$(CONFIG_SOC_SAM9X60) += \ - at91-sam9x60_curiosity.dtb \ - at91-sam9x60ek.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sama5d27_som1_ek := -@ -DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ -DTC_FLAGS_at91-sama5d2_icp := -@ -DTC_FLAGS_at91-sama5d2_ptc_ek := -@ -DTC_FLAGS_at91-sama5d2_xplained := -@ -DTC_FLAGS_at91-sama5d3_eds := -@ -DTC_FLAGS_at91-sama5d3_xplained := -@ -DTC_FLAGS_at91-sama5d4_xplained := -@ -dtb-$(CONFIG_SOC_SAM_V7) += \ - at91-kizbox2-2.dtb \ - at91-kizbox3-hs.dtb \ - at91-nattis-2-natte-2.dtb \ - at91-sama5d27_som1_ek.dtb \ - at91-sama5d27_wlsom1_ek.dtb \ - at91-sama5d2_icp.dtb \ - at91-sama5d2_ptc_ek.dtb \ - at91-sama5d2_xplained.dtb \ - at91-sama5d3_eds.dtb \ - at91-sama5d3_ksz9477_evb.dtb \ - at91-sama5d3_xplained.dtb \ - at91-dvk_som60.dtb \ - at91-gatwick.dtb \ - at91-tse850-3.dtb \ - at91-wb50n.dtb \ - sama5d31ek.dtb \ - sama5d33ek.dtb \ - sama5d34ek.dtb \ - sama5d35ek.dtb \ - sama5d36ek.dtb \ - sama5d36ek_cmp.dtb \ - at91-sama5d4_ma5d4evk.dtb \ - at91-sama5d4_xplained.dtb \ - at91-sama5d4ek.dtb \ - at91-vinco.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sama7g5ek := -@ -dtb-$(CONFIG_SOC_SAMA7G5) += \ - at91-sama7g5ek.dtb -dtb-$(CONFIG_SOC_SP7021) += \ - sunplus-sp7021-demo-v3.dtb -dtb-$(CONFIG_ARCH_AXXIA) += \ - axm5516-amarillo.dtb -# Enables support for device-tree overlays -DTC_FLAGS_bcm2835-rpi-b := -@ -DTC_FLAGS_bcm2835-rpi-a := -@ -DTC_FLAGS_bcm2835-rpi-b-rev2 := -@ -DTC_FLAGS_bcm2835-rpi-b-plus := -@ -DTC_FLAGS_bcm2835-rpi-a-plus := -@ -DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ -DTC_FLAGS_bcm2836-rpi-2-b := -@ -DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ -DTC_FLAGS_bcm2837-rpi-3-b := -@ -DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ -DTC_FLAGS_bcm2837-rpi-cm3-io3 := -@ -DTC_FLAGS_bcm2837-rpi-zero-2-w := -@ -DTC_FLAGS_bcm2711-rpi-400 := -@ -DTC_FLAGS_bcm2711-rpi-4-b := -@ -DTC_FLAGS_bcm2711-rpi-cm4-io := -@ -DTC_FLAGS_bcm2835-rpi-zero := -@ -DTC_FLAGS_bcm2835-rpi-zero-w := -@ -dtb-$(CONFIG_ARCH_BCM2835) += \ - bcm2835-rpi-b.dtb \ - bcm2835-rpi-a.dtb \ - bcm2835-rpi-b-rev2.dtb \ - bcm2835-rpi-b-plus.dtb \ - bcm2835-rpi-a-plus.dtb \ - bcm2835-rpi-cm1-io1.dtb \ - bcm2836-rpi-2-b.dtb \ - bcm2837-rpi-3-a-plus.dtb \ - bcm2837-rpi-3-b.dtb \ - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb \ - bcm2837-rpi-zero-2-w.dtb \ - bcm2711-rpi-400.dtb \ - bcm2711-rpi-4-b.dtb \ - bcm2711-rpi-cm4-io.dtb \ - bcm2835-rpi-zero.dtb \ - bcm2835-rpi-zero-w.dtb -dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4708-asus-rt-ac56u.dtb \ - bcm4708-asus-rt-ac68u.dtb \ - bcm4708-buffalo-wzr-1750dhp.dtb \ - bcm4708-buffalo-wzr-1166dhp.dtb \ - bcm4708-buffalo-wzr-1166dhp2.dtb \ - bcm4708-linksys-ea6300-v1.dtb \ - bcm4708-linksys-ea6500-v2.dtb \ - bcm4708-luxul-xap-1510.dtb \ - bcm4708-luxul-xwc-1000.dtb \ - bcm4708-netgear-r6250.dtb \ - bcm4708-netgear-r6300-v2.dtb \ - bcm4708-smartrg-sr400ac.dtb \ - bcm47081-asus-rt-n18u.dtb \ - bcm47081-buffalo-wzr-600dhp2.dtb \ - bcm47081-buffalo-wzr-900dhp.dtb \ - bcm47081-luxul-xap-1410.dtb \ - bcm47081-luxul-xwr-1200.dtb \ - bcm47081-tplink-archer-c5-v2.dtb \ - bcm4709-asus-rt-ac87u.dtb \ - bcm4709-buffalo-wxr-1900dhp.dtb \ - bcm4709-linksys-ea9200.dtb \ - bcm4709-netgear-r7000.dtb \ - bcm4709-netgear-r8000.dtb \ - bcm4709-tplink-archer-c9-v1.dtb \ - bcm47094-asus-rt-ac88u.dtb \ - bcm47094-dlink-dir-885l.dtb \ - bcm47094-dlink-dir-890l.dtb \ - bcm47094-linksys-panamera.dtb \ - bcm47094-luxul-abr-4500.dtb \ - bcm47094-luxul-xap-1610.dtb \ - bcm47094-luxul-xbr-4500.dtb \ - bcm47094-luxul-xwc-2000.dtb \ - bcm47094-luxul-xwr-3100.dtb \ - bcm47094-luxul-xwr-3150-v1.dtb \ - bcm47094-netgear-r8500.dtb \ - bcm47094-phicomm-k3.dtb \ - bcm53015-meraki-mr26.dtb \ - bcm53016-dlink-dwl-8610ap.dtb \ - bcm53016-meraki-mr32.dtb \ - bcm94708.dtb \ - bcm94709.dtb \ - bcm953012er.dtb \ - bcm953012hr.dtb \ - bcm953012k.dtb -dtb-$(CONFIG_ARCH_BCM_53573) += \ - bcm47189-luxul-xap-1440.dtb \ - bcm47189-luxul-xap-810.dtb \ - bcm47189-tenda-ac9.dtb \ - bcm947189acdbmr.dtb -dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ - bcm911360_entphn.dtb \ - bcm911360k.dtb \ - bcm958300k.dtb \ - bcm958305k.dtb -dtb-$(CONFIG_ARCH_BCM_HR2) += \ - bcm53340-ubnt-unifi-switch8.dtb -dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ - bcm28155-ap.dtb \ - bcm21664-garnet.dtb \ - bcm23550-sparrow.dtb -dtb-$(CONFIG_ARCH_BCM_NSP) += \ - bcm958522er.dtb \ - bcm958525er.dtb \ - bcm958525xmc.dtb \ - bcm958622hr.dtb \ - bcm958623hr.dtb \ - bcm958625-meraki-mx64.dtb \ - bcm958625-meraki-mx64-a0.dtb \ - bcm958625-meraki-mx64w.dtb \ - bcm958625-meraki-mx64w-a0.dtb \ - bcm958625-meraki-mx65.dtb \ - bcm958625-meraki-mx65w.dtb \ - bcm958625hr.dtb \ - bcm988312hr.dtb \ - bcm958625k.dtb -dtb-$(CONFIG_ARCH_BERLIN) += \ - berlin2-sony-nsz-gs7.dtb \ - berlin2cd-google-chromecast.dtb \ - berlin2cd-valve-steamlink.dtb \ - berlin2q-marvell-dmp.dtb -dtb-$(CONFIG_ARCH_BRCMSTB) += \ - bcm7445-bcm97445svmb.dtb -dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb \ - bcm963138.dtb \ - bcm963138dvt.dtb \ - bcm963148.dtb \ - bcm963178.dtb \ - bcm96756.dtb \ - bcm96846.dtb \ - bcm96855.dtb \ - bcm96878.dtb -dtb-$(CONFIG_ARCH_CLPS711X) += \ - ep7211-edb7211.dtb -dtb-$(CONFIG_ARCH_DAVINCI) += \ - da850-lcdk.dtb \ - da850-enbw-cmc.dtb \ - da850-evm.dtb \ - da850-lego-ev3.dtb -dtb-$(CONFIG_ARCH_DIGICOLOR) += \ - cx92755_equinox.dtb -dtb-$(CONFIG_ARCH_AIROHA) += \ - en7523-evb.dtb -dtb-$(CONFIG_ARCH_EXYNOS3) += \ - exynos3250-artik5-eval.dtb \ - exynos3250-monk.dtb \ - exynos3250-rinato.dtb -dtb-$(CONFIG_ARCH_EXYNOS4) += \ - exynos4210-i9100.dtb \ - exynos4210-origen.dtb \ - exynos4210-smdkv310.dtb \ - exynos4210-trats.dtb \ - exynos4210-universal_c210.dtb \ - exynos4412-i9300.dtb \ - exynos4412-i9305.dtb \ - exynos4412-itop-elite.dtb \ - exynos4412-n710x.dtb \ - exynos4412-odroidu3.dtb \ - exynos4412-odroidx.dtb \ - exynos4412-odroidx2.dtb \ - exynos4412-origen.dtb \ - exynos4412-p4note-n8010.dtb \ - exynos4412-smdk4412.dtb \ - exynos4412-tiny4412.dtb \ - exynos4412-trats2.dtb -dtb-$(CONFIG_ARCH_EXYNOS5) += \ - exynos5250-arndale.dtb \ - exynos5250-smdk5250.dtb \ - exynos5250-snow.dtb \ - exynos5250-snow-rev5.dtb \ - exynos5250-spring.dtb \ - exynos5260-xyref5260.dtb \ - exynos5410-odroidxu.dtb \ - exynos5410-smdk5410.dtb \ - exynos5420-arndale-octa.dtb \ - exynos5420-peach-pit.dtb \ - exynos5420-smdk5420.dtb \ - exynos5420-chagall-wifi.dtb \ - exynos5420-klimt-wifi.dtb \ - exynos5422-odroidhc1.dtb \ - exynos5422-odroidxu3.dtb \ - exynos5422-odroidxu3-lite.dtb \ - exynos5422-odroidxu4.dtb \ - exynos5422-samsung-k3g.dtb \ - exynos5800-peach-pi.dtb -dtb-$(CONFIG_ARCH_GEMINI) += \ - gemini-dlink-dir-685.dtb \ - gemini-dlink-dns-313.dtb \ - gemini-nas4220b.dtb \ - gemini-ns2502.dtb \ - gemini-rut1xx.dtb \ - gemini-sl93512r.dtb \ - gemini-sq201.dtb \ - gemini-ssi1328.dtb \ - gemini-wbd111.dtb \ - gemini-wbd222.dtb -dtb-$(CONFIG_ARCH_HI3xxx) += \ - hi3620-hi4511.dtb -dtb-$(CONFIG_ARCH_HIGHBANK) += \ - highbank.dtb \ - ecx-2000.dtb -dtb-$(CONFIG_ARCH_HIP01) += \ - hip01-ca9x2.dtb -dtb-$(CONFIG_ARCH_HIP04) += \ - hip04-d01.dtb -dtb-$(CONFIG_ARCH_HISI) += \ - hi3519-demb.dtb -dtb-$(CONFIG_ARCH_HIX5HD2) += \ - hisi-x5hd2-dkb.dtb -dtb-$(CONFIG_ARCH_HPE_GXP) += \ - hpe-bmc-dl360gen10.dtb -dtb-$(CONFIG_ARCH_INTEGRATOR) += \ - integratorap.dtb \ - integratorap-im-pd1.dtb \ - integratorcp.dtb -dtb-$(CONFIG_ARCH_IXP4XX) += \ - intel-ixp42x-linksys-nslu2.dtb \ - intel-ixp42x-linksys-wrv54g.dtb \ - intel-ixp42x-freecom-fsg-3.dtb \ - intel-ixp42x-welltech-epbx100.dtb \ - intel-ixp42x-ixdp425.dtb \ - intel-ixp43x-kixrp435.dtb \ - intel-ixp46x-ixdp465.dtb \ - intel-ixp42x-adi-coyote.dtb \ - intel-ixp42x-ixdpg425.dtb \ - intel-ixp42x-goramo-multilink.dtb \ - intel-ixp42x-iomega-nas100d.dtb \ - intel-ixp42x-dlink-dsm-g600.dtb \ - intel-ixp42x-gateworks-gw2348.dtb \ - intel-ixp43x-gateworks-gw2358.dtb \ - intel-ixp42x-netgear-wg302v1.dtb \ - intel-ixp42x-arcom-vulcan.dtb \ - intel-ixp42x-gateway-7001.dtb -dtb-$(CONFIG_ARCH_KEYSTONE) += \ - keystone-k2hk-evm.dtb \ - keystone-k2l-evm.dtb \ - keystone-k2e-evm.dtb \ - keystone-k2g-evm.dtb \ - keystone-k2g-ice.dtb -dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-4i-edge-200.dtb \ - kirkwood-b3.dtb \ - kirkwood-blackarmor-nas220.dtb \ - kirkwood-c200-v1.dtb \ - kirkwood-cloudbox.dtb \ - kirkwood-d2net.dtb \ - kirkwood-db-88f6281.dtb \ - kirkwood-db-88f6282.dtb \ - kirkwood-dir665.dtb \ - kirkwood-dns320.dtb \ - kirkwood-dns325.dtb \ - kirkwood-dockstar.dtb \ - kirkwood-dreamplug.dtb \ - kirkwood-ds109.dtb \ - kirkwood-ds110jv10.dtb \ - kirkwood-ds111.dtb \ - kirkwood-ds112.dtb \ - kirkwood-ds209.dtb \ - kirkwood-ds210.dtb \ - kirkwood-ds212.dtb \ - kirkwood-ds212j.dtb \ - kirkwood-ds409.dtb \ - kirkwood-ds409slim.dtb \ - kirkwood-ds411.dtb \ - kirkwood-ds411j.dtb \ - kirkwood-ds411slim.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ - kirkwood-iconnect.dtb \ - kirkwood-iomega_ix2_200.dtb \ - kirkwood-is2.dtb \ - kirkwood-km_fixedeth.dtb \ - kirkwood-km_kirkwood.dtb \ - kirkwood-l-50.dtb \ - kirkwood-laplug.dtb \ - kirkwood-linkstation-lsqvl.dtb \ - kirkwood-linkstation-lsvl.dtb \ - kirkwood-linkstation-lswsxl.dtb \ - kirkwood-linkstation-lswvl.dtb \ - kirkwood-linkstation-lswxl.dtb \ - kirkwood-linksys-viper.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-lsxhl.dtb \ - kirkwood-mplcec4.dtb \ - kirkwood-mv88f6281gtw-ge.dtb \ - kirkwood-nas2big.dtb \ - kirkwood-net2big.dtb \ - kirkwood-net5big.dtb \ - kirkwood-netgear_readynas_duo_v2.dtb \ - kirkwood-netgear_readynas_nv+_v2.dtb \ - kirkwood-ns2.dtb \ - kirkwood-ns2lite.dtb \ - kirkwood-ns2max.dtb \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310.dtb \ - kirkwood-nsa310a.dtb \ - kirkwood-nsa310s.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openblocks_a6.dtb \ - kirkwood-openblocks_a7.dtb \ - kirkwood-openrd-base.dtb \ - kirkwood-openrd-client.dtb \ - kirkwood-openrd-ultimate.dtb \ - kirkwood-pogo_e02.dtb \ - kirkwood-pogoplug-series-4.dtb \ - kirkwood-rd88f6192.dtb \ - kirkwood-rd88f6281-z0.dtb \ - kirkwood-rd88f6281-a.dtb \ - kirkwood-rs212.dtb \ - kirkwood-rs409.dtb \ - kirkwood-rs411.dtb \ - kirkwood-sheevaplug.dtb \ - kirkwood-sheevaplug-esata.dtb \ - kirkwood-t5325.dtb \ - kirkwood-topkick.dtb \ - kirkwood-ts219-6281.dtb \ - kirkwood-ts219-6282.dtb \ - kirkwood-ts419-6281.dtb \ - kirkwood-ts419-6282.dtb -dtb-$(CONFIG_ARCH_LPC18XX) += \ - lpc4337-ciaa.dtb \ - lpc4350-hitex-eval.dtb \ - lpc4357-ea4357-devkit.dtb \ - lpc4357-myd-lpc4357.dtb -dtb-$(CONFIG_ARCH_LPC32XX) += \ - lpc3250-ea3250.dtb \ - lpc3250-phy3250.dtb -dtb-$(CONFIG_ARCH_WPCM450) += \ - nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb -dtb-$(CONFIG_ARCH_NPCM7XX) += \ - nuvoton-npcm730-gsj.dtb \ - nuvoton-npcm730-gbs.dtb \ - nuvoton-npcm730-kudo.dtb \ - nuvoton-npcm750-evb.dtb \ - nuvoton-npcm750-runbmc-olympus.dtb -dtb-$(CONFIG_MACH_MESON6) += \ - meson6-atv1200.dtb -dtb-$(CONFIG_MACH_MESON8) += \ - meson8-minix-neo-x8.dtb \ - meson8b-ec100.dtb \ - meson8b-mxq.dtb \ - meson8b-odroidc1.dtb \ - meson8m2-mxiii-plus.dtb -dtb-$(CONFIG_ARCH_MMP) += \ - pxa168-aspenite.dtb \ - pxa910-dkb.dtb \ - mmp2-brownstone.dtb \ - mmp2-olpc-xo-1-75.dtb \ - mmp3-dell-ariel.dtb -dtb-$(CONFIG_ARCH_MPS2) += \ - mps2-an385.dtb \ - mps2-an399.dtb -dtb-$(CONFIG_ARCH_MOXART) += \ - moxart-uc7112lx.dtb -dtb-$(CONFIG_ARCH_SD5203) += \ - sd5203.dtb -dtb-$(CONFIG_SOC_IMX1) += \ - imx1-ads.dtb \ - imx1-apf9328.dtb -dtb-$(CONFIG_SOC_IMX25) += \ - imx25-eukrea-mbimxsd25-baseboard.dtb \ - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ - imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ - imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ - imx25-karo-tx25.dtb \ - imx25-pdk.dtb -dtb-$(CONFIG_SOC_IMX27) += \ - imx27-apf27.dtb \ - imx27-apf27dev.dtb \ - imx27-eukrea-mbimxsd27-baseboard.dtb \ - imx27-pdk.dtb \ - imx27-phytec-phycore-rdk.dtb \ - imx27-phytec-phycard-s-rdk.dtb -dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb \ - imx31-lite.dtb -dtb-$(CONFIG_SOC_IMX35) += \ - imx35-eukrea-mbimxsd35-baseboard.dtb \ - imx35-pdk.dtb -dtb-$(CONFIG_SOC_IMX50) += \ - imx50-evk.dtb \ - imx50-kobo-aura.dtb -dtb-$(CONFIG_SOC_IMX51) += \ - imx51-apf51.dtb \ - imx51-apf51dev.dtb \ - imx51-babbage.dtb \ - imx51-digi-connectcore-jsk.dtb \ - imx51-eukrea-mbimxsd51-baseboard.dtb \ - imx51-ts4800.dtb \ - imx51-zii-rdu1.dtb \ - imx51-zii-scu2-mezz.dtb \ - imx51-zii-scu3-esb.dtb -dtb-$(CONFIG_SOC_IMX53) += \ - imx53-ard.dtb \ - imx53-cx9020.dtb \ - imx53-kp-ddc.dtb \ - imx53-kp-hsc.dtb \ - imx53-m53evk.dtb \ - imx53-m53menlo.dtb \ - imx53-mba53.dtb \ - imx53-ppd.dtb \ - imx53-qsb.dtb \ - imx53-qsrb.dtb \ - imx53-sk-imx53.dtb \ - imx53-smd.dtb \ - imx53-tx53-x03x.dtb \ - imx53-tx53-x13x.dtb \ - imx53-usbarmory.dtb \ - imx53-voipac-bsb.dtb -dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6dl-alti6p.dtb \ - imx6dl-apf6dev.dtb \ - imx6dl-aristainetos_4.dtb \ - imx6dl-aristainetos_7.dtb \ - imx6dl-aristainetos2_4.dtb \ - imx6dl-aristainetos2_7.dtb \ - imx6dl-colibri-aster.dtb \ - imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-iris.dtb \ - imx6dl-colibri-iris-v2.dtb \ - imx6dl-cubox-i.dtb \ - imx6dl-cubox-i-emmc-som-v15.dtb \ - imx6dl-cubox-i-som-v15.dtb \ - imx6dl-dfi-fs700-m60.dtb \ - imx6dl-dhcom-picoitx.dtb \ - imx6dl-eckelmann-ci4x10.dtb \ - imx6dl-emcon-avari.dtb \ - imx6dl-gw51xx.dtb \ - imx6dl-gw52xx.dtb \ - imx6dl-gw53xx.dtb \ - imx6dl-gw54xx.dtb \ - imx6dl-gw551x.dtb \ - imx6dl-gw552x.dtb \ - imx6dl-gw553x.dtb \ - imx6dl-gw560x.dtb \ - imx6dl-gw5903.dtb \ - imx6dl-gw5904.dtb \ - imx6dl-gw5907.dtb \ - imx6dl-gw5910.dtb \ - imx6dl-gw5912.dtb \ - imx6dl-gw5913.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-hummingboard-emmc-som-v15.dtb \ - imx6dl-hummingboard-som-v15.dtb \ - imx6dl-hummingboard2.dtb \ - imx6dl-hummingboard2-emmc-som-v15.dtb \ - imx6dl-hummingboard2-som-v15.dtb \ - imx6dl-icore.dtb \ - imx6dl-icore-mipi.dtb \ - imx6dl-icore-rqs.dtb \ - imx6dl-lanmcu.dtb \ - imx6dl-mamoj.dtb \ - imx6dl-mba6a.dtb \ - imx6dl-mba6b.dtb \ - imx6dl-nit6xlite.dtb \ - imx6dl-nitrogen6x.dtb \ - imx6dl-phytec-mira-rdk-nand.dtb \ - imx6dl-phytec-pbab01.dtb \ - imx6dl-pico-dwarf.dtb \ - imx6dl-pico-hobbit.dtb \ - imx6dl-pico-nymph.dtb \ - imx6dl-pico-pi.dtb \ - imx6dl-plybas.dtb \ - imx6dl-plym2m.dtb \ - imx6dl-prtmvt.dtb \ - imx6dl-prtrvt.dtb \ - imx6dl-prtvt7.dtb \ - imx6dl-rex-basic.dtb \ - imx6dl-riotboard.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabrelite.dtb \ - imx6dl-sabresd.dtb \ - imx6dl-savageboard.dtb \ - imx6dl-skov-revc-lt2.dtb \ - imx6dl-skov-revc-lt6.dtb \ - imx6dl-solidsense.dtb \ - imx6dl-ts4900.dtb \ - imx6dl-ts7970.dtb \ - imx6dl-tx6dl-comtft.dtb \ - imx6dl-tx6s-8034.dtb \ - imx6dl-tx6s-8034-mb7.dtb \ - imx6dl-tx6s-8035.dtb \ - imx6dl-tx6s-8035-mb7.dtb \ - imx6dl-tx6u-801x.dtb \ - imx6dl-tx6u-80xx-mb7.dtb \ - imx6dl-tx6u-8033.dtb \ - imx6dl-tx6u-8033-mb7.dtb \ - imx6dl-tx6u-811x.dtb \ - imx6dl-tx6u-81xx-mb7.dtb \ - imx6dl-udoo.dtb \ - imx6dl-victgo.dtb \ - imx6dl-vicut1.dtb \ - imx6dl-wandboard.dtb \ - imx6dl-wandboard-revb1.dtb \ - imx6dl-wandboard-revd1.dtb \ - imx6dl-yapp4-draco.dtb \ - imx6dl-yapp4-hydra.dtb \ - imx6dl-yapp4-lynx.dtb \ - imx6dl-yapp4-orion.dtb \ - imx6dl-yapp4-phoenix.dtb \ - imx6dl-yapp4-ursa.dtb \ - imx6q-apalis-eval.dtb \ - imx6q-apalis-ixora.dtb \ - imx6q-apalis-ixora-v1.1.dtb \ - imx6q-apalis-ixora-v1.2.dtb \ - imx6q-apf6dev.dtb \ - imx6q-arm2.dtb \ - imx6q-b450v3.dtb \ - imx6q-b650v3.dtb \ - imx6q-b850v3.dtb \ - imx6q-bosch-acc.dtb \ - imx6q-cm-fx6.dtb \ - imx6q-cubox-i.dtb \ - imx6q-cubox-i-emmc-som-v15.dtb \ - imx6q-cubox-i-som-v15.dtb \ - imx6q-dfi-fs700-m60.dtb \ - imx6q-dhcom-pdk2.dtb \ - imx6q-display5-tianma-tm070-1280x768.dtb \ - imx6q-dmo-edmqmx6.dtb \ - imx6q-dms-ba16.dtb \ - imx6q-ds.dtb \ - imx6q-emcon-avari.dtb \ - imx6q-evi.dtb \ - imx6dl-b105pv2.dtb \ - imx6dl-b105v2.dtb \ - imx6dl-b125v2.dtb \ - imx6dl-b125pv2.dtb \ - imx6dl-b155v2.dtb \ - imx6q-gk802.dtb \ - imx6q-gw51xx.dtb \ - imx6q-gw52xx.dtb \ - imx6q-gw53xx.dtb \ - imx6q-gw5400-a.dtb \ - imx6q-gw54xx.dtb \ - imx6q-gw551x.dtb \ - imx6q-gw552x.dtb \ - imx6q-gw553x.dtb \ - imx6q-gw560x.dtb \ - imx6q-gw5903.dtb \ - imx6q-gw5904.dtb \ - imx6q-gw5907.dtb \ - imx6q-gw5910.dtb \ - imx6q-gw5912.dtb \ - imx6q-gw5913.dtb \ - imx6q-h100.dtb \ - imx6q-hummingboard.dtb \ - imx6q-hummingboard-emmc-som-v15.dtb \ - imx6q-hummingboard-som-v15.dtb \ - imx6q-hummingboard2.dtb \ - imx6q-hummingboard2-emmc-som-v15.dtb \ - imx6q-hummingboard2-som-v15.dtb \ - imx6q-icore.dtb \ - imx6q-icore-mipi.dtb \ - imx6q-icore-ofcap10.dtb \ - imx6q-icore-ofcap12.dtb \ - imx6q-icore-rqs.dtb \ - imx6q-kp-tpc.dtb \ - imx6q-logicpd.dtb \ - imx6q-marsboard.dtb \ - imx6q-mba6a.dtb \ - imx6q-mba6b.dtb \ - imx6q-mccmon6.dtb \ - imx6q-nitrogen6x.dtb \ - imx6q-nitrogen6_max.dtb \ - imx6q-nitrogen6_som2.dtb \ - imx6q-novena.dtb \ - imx6q-phytec-mira-rdk-emmc.dtb \ - imx6q-phytec-mira-rdk-nand.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6q-pico-dwarf.dtb \ - imx6q-pico-hobbit.dtb \ - imx6q-pico-nymph.dtb \ - imx6q-pico-pi.dtb \ - imx6q-pistachio.dtb \ - imx6q-prti6q.dtb \ - imx6q-prtwd2.dtb \ - imx6q-rex-pro.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb \ - imx6q-savageboard.dtb \ - imx6q-sbc6x.dtb \ - imx6q-skov-revc-lt2.dtb \ - imx6q-skov-revc-lt6.dtb \ - imx6q-skov-reve-mi1010ait-1cp1.dtb \ - imx6q-solidsense.dtb \ - imx6q-tbs2910.dtb \ - imx6q-ts4900.dtb \ - imx6q-ts7970.dtb \ - imx6q-tx6q-1010.dtb \ - imx6q-tx6q-1010-comtft.dtb \ - imx6q-tx6q-1020.dtb \ - imx6q-tx6q-1020-comtft.dtb \ - imx6q-tx6q-1036.dtb \ - imx6q-tx6q-1036-mb7.dtb \ - imx6q-tx6q-10x0-mb7.dtb \ - imx6q-tx6q-1110.dtb \ - imx6q-tx6q-11x0-mb7.dtb \ - imx6q-udoo.dtb \ - imx6q-utilite-pro.dtb \ - imx6q-var-dt6customboard.dtb \ - imx6q-vicut1.dtb \ - imx6q-wandboard.dtb \ - imx6q-wandboard-revb1.dtb \ - imx6q-wandboard-revd1.dtb \ - imx6q-yapp4-crux.dtb \ - imx6q-yapp4-pegasus.dtb \ - imx6q-zii-rdu2.dtb \ - imx6qp-mba6b.dtb \ - imx6qp-nitrogen6_max.dtb \ - imx6qp-nitrogen6_som2.dtb \ - imx6qp-phytec-mira-rdk-nand.dtb \ - imx6qp-prtwd3.dtb \ - imx6qp-sabreauto.dtb \ - imx6qp-sabresd.dtb \ - imx6qp-tx6qp-8037.dtb \ - imx6qp-tx6qp-8037-mb7.dtb \ - imx6qp-tx6qp-8137.dtb \ - imx6qp-tx6qp-8137-mb7.dtb \ - imx6qp-vicutp.dtb \ - imx6qp-wandboard-revd1.dtb \ - imx6qp-yapp4-crux-plus.dtb \ - imx6qp-yapp4-pegasus-plus.dtb \ - imx6qp-zii-rdu2.dtb \ - imx6s-dhcom-drc02.dtb -dtb-$(CONFIG_SOC_IMX6SL) += \ - imx6sl-evk.dtb \ - imx6sl-kobo-aura2.dtb \ - imx6sl-tolino-shine2hd.dtb \ - imx6sl-tolino-shine3.dtb \ - imx6sl-tolino-vision.dtb \ - imx6sl-tolino-vision5.dtb \ - imx6sl-warp.dtb -dtb-$(CONFIG_SOC_IMX6SLL) += \ - imx6sll-evk.dtb \ - imx6sll-kobo-clarahd.dtb \ - imx6sll-kobo-librah2o.dtb -dtb-$(CONFIG_SOC_IMX6SX) += \ - imx6sx-nitrogen6sx.dtb \ - imx6sx-sabreauto.dtb \ - imx6sx-sdb-reva.dtb \ - imx6sx-sdb-sai.dtb \ - imx6sx-sdb.dtb \ - imx6sx-sdb-mqs.dtb \ - imx6sx-softing-vining-2000.dtb \ - imx6sx-udoo-neo-basic.dtb \ - imx6sx-udoo-neo-extended.dtb \ - imx6sx-udoo-neo-full.dtb -dtb-$(CONFIG_SOC_IMX6UL) += \ - imx6ul-14x14-evk.dtb \ - imx6ul-ccimx6ulsbcexpress.dtb \ - imx6ul-ccimx6ulsbcpro.dtb \ - imx6ul-geam.dtb \ - imx6ul-isiot-emmc.dtb \ - imx6ul-isiot-nand.dtb \ - imx6ul-kontron-bl.dtb \ - imx6ul-kontron-bl-43.dtb \ - imx6ul-liteboard.dtb \ - imx6ul-tqma6ul1-mba6ulx.dtb \ - imx6ul-tqma6ul2-mba6ulx.dtb \ - imx6ul-tqma6ul2l-mba6ulx.dtb \ - imx6ul-opos6uldev.dtb \ - imx6ul-pico-dwarf.dtb \ - imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb \ - imx6ul-phytec-segin-ff-rdk-emmc.dtb \ - imx6ul-phytec-segin-ff-rdk-nand.dtb \ - imx6ul-prti6g.dtb \ - imx6ul-tx6ul-0010.dtb \ - imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb \ - imx6ull-14x14-evk.dtb \ - imx6ull-colibri-aster.dtb \ - imx6ull-colibri-emmc-aster.dtb \ - imx6ull-colibri-emmc-eval-v3.dtb \ - imx6ull-colibri-emmc-iris.dtb \ - imx6ull-colibri-emmc-iris-v2.dtb \ - imx6ull-colibri-eval-v3.dtb \ - imx6ull-colibri-iris.dtb \ - imx6ull-colibri-iris-v2.dtb \ - imx6ull-colibri-wifi-aster.dtb \ - imx6ull-colibri-wifi-eval-v3.dtb \ - imx6ull-colibri-wifi-iris.dtb \ - imx6ull-colibri-wifi-iris-v2.dtb \ - imx6ull-dhcom-drc02.dtb \ - imx6ull-dhcom-pdk2.dtb \ - imx6ull-dhcom-picoitx.dtb \ - imx6ull-dhcor-maveo-box.dtb \ - imx6ull-jozacp.dtb \ - imx6ull-kontron-bl.dtb \ - imx6ull-myir-mys-6ulx-eval.dtb \ - imx6ull-opos6uldev.dtb \ - imx6ull-phytec-segin-ff-rdk-nand.dtb \ - imx6ull-phytec-segin-ff-rdk-emmc.dtb \ - imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ull-phytec-tauri-emmc.dtb \ - imx6ull-phytec-tauri-nand.dtb \ - imx6ull-tarragon-master.dtb \ - imx6ull-tarragon-micro.dtb \ - imx6ull-tarragon-slave.dtb \ - imx6ull-tarragon-slavext.dtb \ - imx6ull-tqma6ull2-mba6ulx.dtb \ - imx6ull-tqma6ull2l-mba6ulx.dtb \ - imx6ulz-14x14-evk.dtb \ - imx6ulz-bsh-smm-m2.dtb -dtb-$(CONFIG_SOC_IMX7D) += \ - imx7d-cl-som-imx7.dtb \ - imx7d-colibri-aster.dtb \ - imx7d-colibri-emmc-aster.dtb \ - imx7d-colibri-emmc-iris.dtb \ - imx7d-colibri-emmc-iris-v2.dtb \ - imx7d-colibri-emmc-eval-v3.dtb \ - imx7d-colibri-eval-v3.dtb \ - imx7d-colibri-iris.dtb \ - imx7d-colibri-iris-v2.dtb \ - imx7d-flex-concentrator.dtb \ - imx7d-flex-concentrator-mfg.dtb \ - imx7d-mba7.dtb \ - imx7d-meerkat96.dtb \ - imx7d-nitrogen7.dtb \ - imx7d-pico-dwarf.dtb \ - imx7d-pico-hobbit.dtb \ - imx7d-pico-nymph.dtb \ - imx7d-pico-pi.dtb \ - imx7d-remarkable2.dtb \ - imx7d-sbc-imx7.dtb \ - imx7d-sdb.dtb \ - imx7d-sdb-reva.dtb \ - imx7d-sdb-sht11.dtb \ - imx7d-smegw01.dtb \ - imx7d-zii-rmu2.dtb \ - imx7d-zii-rpu2.dtb \ - imx7s-colibri-aster.dtb \ - imx7s-colibri-eval-v3.dtb \ - imx7s-colibri-iris.dtb \ - imx7s-colibri-iris-v2.dtb \ - imx7s-mba7.dtb \ - imx7s-warp.dtb -dtb-$(CONFIG_SOC_IMX7ULP) += \ - imx7ulp-com.dtb \ - imx7ulp-evk.dtb -dtb-$(CONFIG_SOC_IMXRT) += \ - imxrt1050-evk.dtb -dtb-$(CONFIG_SOC_LAN966) += \ - lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ - lan966x-kontron-kswitch-d10-mmt-8g.dtb \ - lan966x-pcb8290.dtb \ - lan966x-pcb8291.dtb \ - lan966x-pcb8309.dtb -dtb-$(CONFIG_SOC_LS1021A) += \ - ls1021a-iot.dtb \ - ls1021a-moxa-uc-8410a.dtb \ - ls1021a-qds.dtb \ - ls1021a-tsn.dtb \ - ls1021a-twr.dtb -dtb-$(CONFIG_SOC_VF610) += \ - vf500-colibri-eval-v3.dtb \ - vf610-bk4.dtb \ - vf610-colibri-eval-v3.dtb \ - vf610m4-colibri.dtb \ - vf610-cosmic.dtb \ - vf610m4-cosmic.dtb \ - vf610-twr.dtb \ - vf610-zii-cfu1.dtb \ - vf610-zii-dev-rev-b.dtb \ - vf610-zii-dev-rev-c.dtb \ - vf610-zii-scu4-aib.dtb \ - vf610-zii-spb4.dtb \ - vf610-zii-ssmb-dtu.dtb \ - vf610-zii-ssmb-spu3.dtb -dtb-$(CONFIG_ARCH_MXS) += \ - imx23-evk.dtb \ - imx23-olinuxino.dtb \ - imx23-sansa.dtb \ - imx23-stmp378x_devb.dtb \ - imx23-xfi3.dtb \ - imx28-apf28.dtb \ - imx28-apf28dev.dtb \ - imx28-apx4devkit.dtb \ - imx28-cfa10036.dtb \ - imx28-cfa10037.dtb \ - imx28-cfa10049.dtb \ - imx28-cfa10055.dtb \ - imx28-cfa10056.dtb \ - imx28-cfa10057.dtb \ - imx28-cfa10058.dtb \ - imx28-duckbill-2-485.dtb \ - imx28-duckbill-2.dtb \ - imx28-duckbill-2-enocean.dtb \ - imx28-duckbill-2-spi.dtb \ - imx28-duckbill.dtb \ - imx28-eukrea-mbmx283lc.dtb \ - imx28-eukrea-mbmx287lc.dtb \ - imx28-evk.dtb \ - imx28-m28cu3.dtb \ - imx28-m28evk.dtb \ - imx28-sps1.dtb \ - imx28-ts4600.dtb \ - imx28-tx28.dtb \ - imx28-xea.dtb -dtb-$(CONFIG_ARCH_NOMADIK) += \ - ste-nomadik-s8815.dtb \ - ste-nomadik-nhk15.dtb -dtb-$(CONFIG_ARCH_NSPIRE) += \ - nspire-cx.dtb \ - nspire-tp.dtb \ - nspire-clp.dtb -dtb-$(CONFIG_ARCH_OMAP2) += \ - omap2420-h4.dtb \ - omap2420-n800.dtb \ - omap2420-n810.dtb \ - omap2420-n810-wimax.dtb \ - omap2430-sdp.dtb -dtb-$(CONFIG_ARCH_OMAP3) += \ - am3517-craneboard.dtb \ - am3517-evm.dtb \ - am3517_mt_ventoux.dtb \ - logicpd-torpedo-35xx-devkit.dtb \ - logicpd-torpedo-37xx-devkit.dtb \ - logicpd-torpedo-37xx-devkit-28.dtb \ - logicpd-som-lv-35xx-devkit.dtb \ - logicpd-som-lv-37xx-devkit.dtb \ - omap3430-sdp.dtb \ - omap3-beagle.dtb \ - omap3-beagle-ab4.dtb \ - omap3-beagle-xm.dtb \ - omap3-beagle-xm-ab.dtb \ - omap3-cm-t3517.dtb \ - omap3-cm-t3530.dtb \ - omap3-cm-t3730.dtb \ - omap3-devkit8000.dtb \ - omap3-devkit8000-lcd43.dtb \ - omap3-devkit8000-lcd70.dtb \ - omap3-echo.dtb \ - omap3-evm.dtb \ - omap3-evm-37xx.dtb \ - omap3-gta04a3.dtb \ - omap3-gta04a4.dtb \ - omap3-gta04a5.dtb \ - omap3-gta04a5one.dtb \ - omap3-ha.dtb \ - omap3-ha-lcd.dtb \ - omap3-igep0020.dtb \ - omap3-igep0020-rev-f.dtb \ - omap3-igep0030.dtb \ - omap3-igep0030-rev-g.dtb \ - omap3-ldp.dtb \ - omap3-lilly-dbb056.dtb \ - omap3-n900.dtb \ - omap3-n9.dtb \ - omap3-n950.dtb \ - omap3-overo-alto35.dtb \ - omap3-overo-chestnut43.dtb \ - omap3-overo-gallop43.dtb \ - omap3-overo-palo35.dtb \ - omap3-overo-palo43.dtb \ - omap3-overo-storm-alto35.dtb \ - omap3-overo-storm-chestnut43.dtb \ - omap3-overo-storm-gallop43.dtb \ - omap3-overo-storm-palo35.dtb \ - omap3-overo-storm-palo43.dtb \ - omap3-overo-storm-summit.dtb \ - omap3-overo-storm-tobi.dtb \ - omap3-overo-storm-tobiduo.dtb \ - omap3-overo-summit.dtb \ - omap3-overo-tobi.dtb \ - omap3-overo-tobiduo.dtb \ - omap3-pandora-600mhz.dtb \ - omap3-pandora-1ghz.dtb \ - omap3-sbc-t3517.dtb \ - omap3-sbc-t3530.dtb \ - omap3-sbc-t3730.dtb \ - omap3-sniper.dtb \ - omap3-thunder.dtb \ - omap3-zoom3.dtb -dtb-$(CONFIG_SOC_TI81XX) += \ - am3874-iceboard.dtb \ - dm8148-evm.dtb \ - dm8148-t410.dtb \ - dm8168-evm.dtb \ - dra62x-j5eco-evm.dtb -dtb-$(CONFIG_SOC_AM33XX) += \ - am335x-baltos-ir2110.dtb \ - am335x-baltos-ir3220.dtb \ - am335x-baltos-ir5221.dtb \ - am335x-base0033.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-boneblack-wireless.dtb \ - am335x-boneblue.dtb \ - am335x-bonegreen.dtb \ - am335x-bonegreen-wireless.dtb \ - am335x-chiliboard.dtb \ - am335x-cm-t335.dtb \ - am335x-evm.dtb \ - am335x-evmsk.dtb \ - am335x-guardian.dtb \ - am335x-icev2.dtb \ - am335x-lxm.dtb \ - am335x-moxa-uc-2101.dtb \ - am335x-moxa-uc-8100-me-t.dtb \ - am335x-myirtech-myd.dtb \ - am335x-nano.dtb \ - am335x-netcan-plus-1xx.dtb \ - am335x-netcom-plus-2xx.dtb \ - am335x-netcom-plus-8xx.dtb \ - am335x-pdu001.dtb \ - am335x-pepper.dtb \ - am335x-phycore-rdk.dtb \ - am335x-pocketbeagle.dtb \ - am335x-regor-rdk.dtb \ - am335x-sancloud-bbe.dtb \ - am335x-sancloud-bbe-lite.dtb \ - am335x-sancloud-bbe-extended-wifi.dtb \ - am335x-shc.dtb \ - am335x-sbc-t335.dtb \ - am335x-sl50.dtb \ - am335x-wega-rdk.dtb \ - am335x-osd3358-sm-red.dtb -dtb-$(CONFIG_ARCH_OMAP4) += \ - omap4-droid-bionic-xt875.dtb \ - omap4-droid4-xt894.dtb \ - omap4-duovero-parlor.dtb \ - omap4-epson-embt2ws.dtb \ - omap4-kc1.dtb \ - omap4-panda.dtb \ - omap4-panda-a4.dtb \ - omap4-panda-es.dtb \ - omap4-sdp.dtb \ - omap4-sdp-es23plus.dtb \ - omap4-var-dvk-om44.dtb \ - omap4-var-stk-om44.dtb -dtb-$(CONFIG_SOC_AM43XX) += \ - am43x-epos-evm.dtb \ - am437x-cm-t43.dtb \ - am437x-gp-evm.dtb \ - am437x-idk-evm.dtb \ - am437x-sbc-t43.dtb \ - am437x-sk-evm.dtb -dtb-$(CONFIG_SOC_OMAP5) += \ - omap5-cm-t54.dtb \ - omap5-igep0050.dtb \ - omap5-sbc-t54.dtb \ - omap5-uevm.dtb -am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo -am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo -dtb-$(CONFIG_SOC_DRA7XX) += \ - am57xx-beagle-x15.dtb \ - am57xx-beagle-x15-revb1.dtb \ - am57xx-beagle-x15-revc.dtb \ - am57xx-evm.dtb \ - am57xx-evm-reva3.dtb \ - am5729-beagleboneai.dtb \ - am57xx-cl-som-am57x.dtb \ - am57xx-sbc-am57x.dtb \ - am572x-idk.dtb \ - am572x-idk-touchscreen.dtbo \ - am571x-idk.dtb \ - am571x-idk-touchscreen.dtbo \ - am574x-idk.dtb \ - am57xx-idk-lcd-osd101t2045.dtbo \ - am57xx-idk-lcd-osd101t2587.dtbo \ - dra7-evm.dtb \ - dra72-evm.dtb \ - dra72-evm-revc.dtb \ - dra71-evm.dtb \ - dra76-evm.dtb -dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-kuroboxpro.dtb \ - orion5x-lacie-d2-network.dtb \ - orion5x-lacie-ethernet-disk-mini-v2.dtb \ - orion5x-linkstation-lsgl.dtb \ - orion5x-linkstation-lswtgl.dtb \ - orion5x-linkstation-lschl.dtb \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-netgear-wnr854t.dtb \ - orion5x-rd88f5182-nas.dtb -dtb-$(CONFIG_ARCH_ACTIONS) += \ - owl-s500-cubieboard6.dtb \ - owl-s500-guitar-bb-rev-b.dtb \ - owl-s500-labrador-base-m.dtb \ - owl-s500-roseapplepi.dtb \ - owl-s500-sparky.dtb -dtb-$(CONFIG_ARCH_PXA) += \ - pxa300-raumfeld-connector.dtb \ - pxa300-raumfeld-controller.dtb \ - pxa300-raumfeld-speaker-l.dtb \ - pxa300-raumfeld-speaker-m.dtb \ - pxa300-raumfeld-speaker-one.dtb \ - pxa300-raumfeld-speaker-s.dtb -dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8016-sbc.dtb \ - qcom-apq8026-asus-sparrow.dtb \ - qcom-apq8026-huawei-sturgeon.dtb \ - qcom-apq8026-lg-lenok.dtb \ - qcom-apq8026-samsung-matisse-wifi.dtb \ - qcom-apq8060-dragonboard.dtb \ - qcom-apq8064-cm-qs600.dtb \ - qcom-apq8064-ifc6410.dtb \ - qcom-apq8064-sony-xperia-lagan-yuga.dtb \ - qcom-apq8064-asus-nexus7-flo.dtb \ - qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ - qcom-ipq4018-ap120c-ac.dtb \ - qcom-ipq4018-ap120c-ac-bit.dtb \ - qcom-ipq4018-jalapeno.dtb \ - qcom-ipq4019-ap.dk01.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c3.dtb \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ - qcom-ipq8064-ap148.dtb \ - qcom-ipq8064-rb3011.dtb \ - qcom-msm8226-samsung-s3ve3g.dtb \ - qcom-msm8660-surf.dtb \ - qcom-msm8916-samsung-e5.dtb \ - qcom-msm8916-samsung-e7.dtb \ - qcom-msm8916-samsung-grandmax.dtb \ - qcom-msm8916-samsung-serranove.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-msm8960-samsung-expressatt.dtb \ - qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-sony-xperia-rhine-amami.dtb \ - qcom-msm8974-sony-xperia-rhine-honami.dtb \ - qcom-msm8974pro-fairphone-fp2.dtb \ - qcom-msm8974pro-oneplus-bacon.dtb \ - qcom-msm8974pro-samsung-klte.dtb \ - qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ - qcom-mdm9615-wp8548-mangoh-green.dtb \ - qcom-sdx55-mtp.dtb \ - qcom-sdx55-t55.dtb \ - qcom-sdx55-telit-fn980-tlb.dtb \ - qcom-sdx65-mtp.dtb -dtb-$(CONFIG_ARCH_RDA) += \ - rda8810pl-orangepi-2g-iot.dtb \ - rda8810pl-orangepi-i96.dtb -dtb-$(CONFIG_ARCH_REALTEK) += \ - rtd1195-horseradish.dtb \ - rtd1195-mele-x1000.dtb -dtb-$(CONFIG_ARCH_REALVIEW) += \ - arm-realview-pb1176.dtb \ - arm-realview-pb11mp.dtb \ - arm-realview-eb.dtb \ - arm-realview-eb-bbrevd.dtb \ - arm-realview-eb-11mp.dtb \ - arm-realview-eb-11mp-bbrevd.dtb \ - arm-realview-eb-11mp-ctrevb.dtb \ - arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ - arm-realview-eb-a9mp.dtb \ - arm-realview-eb-a9mp-bbrevd.dtb \ - arm-realview-pba8.dtb \ - arm-realview-pbx-a9.dtb -dtb-$(CONFIG_ARCH_RENESAS) += \ - emev2-kzm9d.dtb \ - r7s72100-genmai.dtb \ - r7s72100-gr-peach.dtb \ - r7s72100-rskrza1.dtb \ - r7s9210-rza2mevb.dtb \ - r8a73a4-ape6evm.dtb \ - r8a7740-armadillo800eva.dtb \ - r8a7742-iwg21d-q7.dtb \ - r8a7742-iwg21d-q7-dbcm-ca.dtb \ - r8a7743-iwg20d-q7.dtb \ - r8a7743-iwg20d-q7-dbcm-ca.dtb \ - r8a7743-sk-rzg1m.dtb \ - r8a7744-iwg20d-q7.dtb \ - r8a7744-iwg20d-q7-dbcm-ca.dtb \ - r8a7745-iwg22d-sodimm.dtb \ - r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ - r8a7745-sk-rzg1e.dtb \ - r8a77470-iwg23s-sbc.dtb \ - r8a7778-bockw.dtb \ - r8a7779-marzen.dtb \ - r8a7790-lager.dtb \ - r8a7790-stout.dtb \ - r8a7791-koelsch.dtb \ - r8a7791-porter.dtb \ - r8a7792-blanche.dtb \ - r8a7792-wheat.dtb \ - r8a7793-gose.dtb \ - r8a7794-alt.dtb \ - r8a7794-silk.dtb \ - r9a06g032-rzn1d400-db.dtb \ - sh73a0-kzm9g.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rv1108-elgin-r1.dtb \ - rv1108-evb.dtb \ - rv1126-edgeble-neu2-io.dtb \ - rk3036-evb.dtb \ - rk3036-kylin.dtb \ - rk3066a-bqcurie2.dtb \ - rk3066a-marsboard.dtb \ - rk3066a-mk808.dtb \ - rk3066a-rayeager.dtb \ - rk3128-evb.dtb \ - rk3188-bqedison2qc.dtb \ - rk3188-px3-evb.dtb \ - rk3188-radxarock.dtb \ - rk3228-evb.dtb \ - rk3229-evb.dtb \ - rk3229-xms6.dtb \ - rk3288-evb-act8846.dtb \ - rk3288-evb-rk808.dtb \ - rk3288-firefly-beta.dtb \ - rk3288-firefly.dtb \ - rk3288-firefly-reload.dtb \ - rk3288-miqi.dtb \ - rk3288-phycore-rdk.dtb \ - rk3288-popmetal.dtb \ - rk3288-r89.dtb \ - rk3288-rock2-square.dtb \ - rk3288-rock-pi-n8.dtb \ - rk3288-tinker.dtb \ - rk3288-tinker-s.dtb \ - rk3288-veyron-brain.dtb \ - rk3288-veyron-fievel.dtb \ - rk3288-veyron-jaq.dtb \ - rk3288-veyron-jerry.dtb \ - rk3288-veyron-mickey.dtb \ - rk3288-veyron-mighty.dtb \ - rk3288-veyron-minnie.dtb \ - rk3288-veyron-pinky.dtb \ - rk3288-veyron-speedy.dtb \ - rk3288-veyron-tiger.dtb \ - rk3288-vyasa.dtb -dtb-$(CONFIG_ARCH_S3C64XX) += \ - s3c6410-mini6410.dtb \ - s3c6410-smdk6410.dtb -dtb-$(CONFIG_ARCH_S5PV210) += \ - s5pv210-aquila.dtb \ - s5pv210-fascinate4g.dtb \ - s5pv210-galaxys.dtb \ - s5pv210-goni.dtb \ - s5pv210-smdkc110.dtb \ - s5pv210-smdkv210.dtb \ - s5pv210-torbreck.dtb -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ - socfpga_arria5_socdk.dtb \ - socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ - socfpga_arria10_socdk_nand.dtb \ - socfpga_arria10_socdk_qspi.dtb \ - socfpga_arria10_socdk_sdmmc.dtb \ - socfpga_cyclone5_chameleon96.dtb \ - socfpga_cyclone5_mcvevk.dtb \ - socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ - socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sodia.dtb \ - socfpga_cyclone5_vining_fpga.dtb \ - socfpga_vt.dtb -dtb-$(CONFIG_ARCH_SPEAR13XX) += \ - spear1310-evb.dtb \ - spear1340-evb.dtb -dtb-$(CONFIG_ARCH_SPEAR3XX) += \ - spear300-evb.dtb \ - spear310-evb.dtb \ - spear320-evb.dtb \ - spear320-hmi.dtb -dtb-$(CONFIG_ARCH_SPEAR6XX) += \ - spear600-evb.dtb -dtb-$(CONFIG_ARCH_STI) += \ - stih407-b2120.dtb \ - stih410-b2120.dtb \ - stih410-b2260.dtb \ - stih418-b2199.dtb \ - stih418-b2264.dtb -dtb-$(CONFIG_ARCH_STM32) += \ - stm32f429-disco.dtb \ - stm32f469-disco.dtb \ - stm32f746-disco.dtb \ - stm32f769-disco.dtb \ - stm32429i-eval.dtb \ - stm32746g-eval.dtb \ - stm32h743i-eval.dtb \ - stm32h743i-disco.dtb \ - stm32h750i-art-pi.dtb \ - stm32mp135f-dk.dtb \ - stm32mp151a-prtt1a.dtb \ - stm32mp151a-prtt1c.dtb \ - stm32mp151a-prtt1s.dtb \ - stm32mp151a-dhcor-testbench.dtb \ - stm32mp153c-dhcom-drc02.dtb \ - stm32mp153c-dhcor-drc-compact.dtb \ - stm32mp157a-avenger96.dtb \ - stm32mp157a-dhcor-avenger96.dtb \ - stm32mp157a-dk1.dtb \ - stm32mp157a-dk1-scmi.dtb \ - stm32mp157a-iot-box.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ - stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ - stm32mp157a-stinger96.dtb \ - stm32mp157c-dhcom-pdk2.dtb \ - stm32mp157c-dhcom-picoitx.dtb \ - stm32mp157c-dk2.dtb \ - stm32mp157c-dk2-scmi.dtb \ - stm32mp157c-ed1.dtb \ - stm32mp157c-ed1-scmi.dtb \ - stm32mp157c-emsbc-argon.dtb \ - stm32mp157c-ev1.dtb \ - stm32mp157c-ev1-scmi.dtb \ - stm32mp157c-lxa-mc1.dtb \ - stm32mp157c-odyssey.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb -dtb-$(CONFIG_MACH_SUN4I) += \ - sun4i-a10-a1000.dtb \ - sun4i-a10-ba10-tvbox.dtb \ - sun4i-a10-chuwi-v7-cw0825.dtb \ - sun4i-a10-cubieboard.dtb \ - sun4i-a10-dserve-dsrv9703c.dtb \ - sun4i-a10-gemei-g9.dtb \ - sun4i-a10-hackberry.dtb \ - sun4i-a10-hyundai-a7hd.dtb \ - sun4i-a10-inet1.dtb \ - sun4i-a10-inet97fv2.dtb \ - sun4i-a10-inet9f-rev03.dtb \ - sun4i-a10-itead-iteaduino-plus.dtb \ - sun4i-a10-jesurun-q5.dtb \ - sun4i-a10-marsboard.dtb \ - sun4i-a10-mini-xplus.dtb \ - sun4i-a10-mk802.dtb \ - sun4i-a10-mk802ii.dtb \ - sun4i-a10-olinuxino-lime.dtb \ - sun4i-a10-pcduino.dtb \ - sun4i-a10-pcduino2.dtb \ - sun4i-a10-pov-protab2-ips9.dtb \ - sun4i-a10-topwise-a721.dtb -dtb-$(CONFIG_MACH_SUN5I) += \ - sun5i-a10s-auxtek-t003.dtb \ - sun5i-a10s-auxtek-t004.dtb \ - sun5i-a10s-mk802.dtb \ - sun5i-a10s-olinuxino-micro.dtb \ - sun5i-a10s-r7-tv-dongle.dtb \ - sun5i-a10s-wobo-i5.dtb \ - sun5i-a13-difrnce-dit4350.dtb \ - sun5i-a13-empire-electronix-d709.dtb \ - sun5i-a13-empire-electronix-m712.dtb \ - sun5i-a13-hsg-h702.dtb \ - sun5i-a13-inet-98v-rev2.dtb \ - sun5i-a13-licheepi-one.dtb \ - sun5i-a13-olinuxino.dtb \ - sun5i-a13-olinuxino-micro.dtb \ - sun5i-a13-pocketbook-touch-lux-3.dtb \ - sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb \ - sun5i-gr8-chip-pro.dtb \ - sun5i-gr8-evb.dtb \ - sun5i-r8-chip.dtb -dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-app4-evb1.dtb \ - sun6i-a31-colombus.dtb \ - sun6i-a31-hummingbird.dtb \ - sun6i-a31-i7.dtb \ - sun6i-a31-m9.dtb \ - sun6i-a31-mele-a1000g-quad.dtb \ - sun6i-a31s-colorfly-e708-q1.dtb \ - sun6i-a31s-cs908.dtb \ - sun6i-a31s-inet-q972.dtb \ - sun6i-a31s-primo81.dtb \ - sun6i-a31s-sina31s.dtb \ - sun6i-a31s-sinovoip-bpi-m2.dtb \ - sun6i-a31s-yones-toptech-bs1078-v2.dtb -dtb-$(CONFIG_MACH_SUN7I) += \ - sun7i-a20-bananapi.dtb \ - sun7i-a20-bananapi-m1-plus.dtb \ - sun7i-a20-bananapro.dtb \ - sun7i-a20-cubieboard2.dtb \ - sun7i-a20-cubietruck.dtb \ - sun7i-a20-haoyu-marsboard.dtb \ - sun7i-a20-hummingbird.dtb \ - sun7i-a20-itead-ibox.dtb \ - sun7i-a20-i12-tvbox.dtb \ - sun7i-a20-icnova-a20-adb4006.dtb \ - sun7i-a20-icnova-swac.dtb \ - sun7i-a20-lamobo-r1.dtb \ - sun7i-a20-linutronix-testbox-v2.dtb \ - sun7i-a20-m3.dtb \ - sun7i-a20-mk808c.dtb \ - sun7i-a20-olimex-som-evb.dtb \ - sun7i-a20-olimex-som-evb-emmc.dtb \ - sun7i-a20-olimex-som204-evb.dtb \ - sun7i-a20-olimex-som204-evb-emmc.dtb \ - sun7i-a20-olinuxino-lime.dtb \ - sun7i-a20-olinuxino-lime-emmc.dtb \ - sun7i-a20-olinuxino-lime2.dtb \ - sun7i-a20-olinuxino-lime2-emmc.dtb \ - sun7i-a20-olinuxino-micro.dtb \ - sun7i-a20-olinuxino-micro-emmc.dtb \ - sun7i-a20-orangepi.dtb \ - sun7i-a20-orangepi-mini.dtb \ - sun7i-a20-pcduino3.dtb \ - sun7i-a20-pcduino3-nano.dtb \ - sun7i-a20-wexler-tab7200.dtb \ - sun7i-a20-wits-pro-a20-dkt.dtb -dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a23-evb.dtb \ - sun8i-a23-gt90h-v4.dtb \ - sun8i-a23-inet86dz.dtb \ - sun8i-a23-ippo-q8h-v5.dtb \ - sun8i-a23-ippo-q8h-v1.2.dtb \ - sun8i-a23-polaroid-mid2407pxe03.dtb \ - sun8i-a23-polaroid-mid2809pxe04.dtb \ - sun8i-a23-q8-tablet.dtb \ - sun8i-a33-et-q8-v1.6.dtb \ - sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-inet-d978-rev2.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-olinuxino.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-tbs-a711.dtb \ - sun8i-h2-plus-bananapi-m2-zero.dtb \ - sun8i-h2-plus-libretech-all-h3-cc.dtb \ - sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ - sun8i-h3-bananapi-m2-plus-v1.2.dtb \ - sun8i-h3-beelink-x2.dtb \ - sun8i-h3-libretech-all-h3-cc.dtb \ - sun8i-h3-mapleboard-mp130.dtb \ - sun8i-h3-nanopi-duo2.dtb \ - sun8i-h3-nanopi-m1.dtb \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ - sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ - sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-pc-plus.dtb \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ - sun8i-h3-zeropi.dtb \ - sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ - sun8i-r16-parrot.dtb \ - sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-r40-oka40i-c.dtb \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-lichee-zero-plus.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-t113s-mangopi-mq-r-t113.dtb \ - sun8i-t3-cqa3t-bv3.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb \ - sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ - sun9i-a80-cubieboard4.dtb -dtb-$(CONFIG_MACH_SUNIV) += \ - suniv-f1c100s-licheepi-nano.dtb \ - suniv-f1c200s-lctech-pi.dtb \ - suniv-f1c200s-popstick-v1.1.dtb -dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ - tegra20-acer-a500-picasso.dtb \ - tegra20-asus-tf101.dtb \ - tegra20-harmony.dtb \ - tegra20-colibri-eval-v3.dtb \ - tegra20-colibri-iris.dtb \ - tegra20-medcom-wide.dtb \ - tegra20-paz00.dtb \ - tegra20-plutux.dtb \ - tegra20-seaboard.dtb \ - tegra20-tec.dtb \ - tegra20-trimslice.dtb \ - tegra20-ventana.dtb -dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ - tegra30-apalis-eval.dtb \ - tegra30-apalis-v1.1-eval.dtb \ - tegra30-asus-nexus7-grouper-PM269.dtb \ - tegra30-asus-nexus7-grouper-E1565.dtb \ - tegra30-asus-nexus7-tilapia-E1565.dtb \ - tegra30-asus-tf201.dtb \ - tegra30-asus-tf300t.dtb \ - tegra30-asus-tf300tg.dtb \ - tegra30-asus-tf700t.dtb \ - tegra30-beaver.dtb \ - tegra30-cardhu-a02.dtb \ - tegra30-cardhu-a04.dtb \ - tegra30-colibri-eval-v3.dtb \ - tegra30-ouya.dtb \ - tegra30-pegatron-chagall.dtb -dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ - tegra114-asus-tf701t.dtb \ - tegra114-dalmore.dtb \ - tegra114-roth.dtb \ - tegra114-tn7.dtb -dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ - tegra124-apalis-eval.dtb \ - tegra124-apalis-v1.2-eval.dtb \ - tegra124-jetson-tk1.dtb \ - tegra124-nyan-big.dtb \ - tegra124-nyan-big-fhd.dtb \ - tegra124-nyan-blaze.dtb \ - tegra124-venice2.dtb -dtb-$(CONFIG_ARCH_U8500) += \ - ste-snowball.dtb \ - ste-hrefprev60-stuib.dtb \ - ste-hrefprev60-tvk.dtb \ - ste-hrefv60plus-stuib.dtb \ - ste-hrefv60plus-tvk.dtb \ - ste-href520-tvk.dtb \ - ste-ux500-samsung-golden.dtb \ - ste-ux500-samsung-janice.dtb \ - ste-ux500-samsung-gavini.dtb \ - ste-ux500-samsung-codina.dtb \ - ste-ux500-samsung-codina-tmo.dtb \ - ste-ux500-samsung-skomer.dtb \ - ste-ux500-samsung-kyle.dtb -dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ld4-ref.dtb \ - uniphier-ld6b-ref.dtb \ - uniphier-pro4-ace.dtb \ - uniphier-pro4-ref.dtb \ - uniphier-pro4-sanji.dtb \ - uniphier-pro5-epcore.dtb \ - uniphier-pro5-proex.dtb \ - uniphier-pxs2-gentil.dtb \ - uniphier-pxs2-vodka.dtb \ - uniphier-sld8-ref.dtb -dtb-$(CONFIG_ARCH_VERSATILE) += \ - versatile-ab.dtb \ - versatile-ab-ib2.dtb \ - versatile-pb.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += \ - vexpress-v2p-ca5s.dtb \ - vexpress-v2p-ca9.dtb \ - vexpress-v2p-ca15-tc1.dtb \ - vexpress-v2p-ca15_a7.dtb -dtb-$(CONFIG_ARCH_VIRT) += \ - xenvm-4.2.dtb -dtb-$(CONFIG_ARCH_VT8500) += \ - vt8500-bv07.dtb \ - wm8505-ref.dtb \ - wm8650-mid.dtb \ - wm8750-apc8750.dtb \ - wm8850-w70v2.dtb -dtb-$(CONFIG_ARCH_ZYNQ) += \ - zynq-cc108.dtb \ - zynq-ebaz4205.dtb \ - zynq-microzed.dtb \ - zynq-parallella.dtb \ - zynq-zc702.dtb \ - zynq-zc706.dtb \ - zynq-zc770-xm010.dtb \ - zynq-zc770-xm011.dtb \ - zynq-zc770-xm012.dtb \ - zynq-zc770-xm013.dtb \ - zynq-zed.dtb \ - zynq-zturn.dtb \ - zynq-zturn-v5.dtb \ - zynq-zybo.dtb \ - zynq-zybo-z7.dtb -dtb-$(CONFIG_MACH_ARMADA_370) += \ - armada-370-c200-v2.dtb \ - armada-370-db.dtb \ - armada-370-dlink-dns327l.dtb \ - armada-370-mirabox.dtb \ - armada-370-netgear-rn102.dtb \ - armada-370-netgear-rn104.dtb \ - armada-370-rd.dtb \ - armada-370-seagate-nas-2bay.dtb \ - armada-370-seagate-nas-4bay.dtb \ - armada-370-seagate-personal-cloud.dtb \ - armada-370-seagate-personal-cloud-2bay.dtb \ - armada-370-synology-ds213j.dtb -dtb-$(CONFIG_MACH_ARMADA_375) += \ - armada-375-db.dtb -dtb-$(CONFIG_MACH_ARMADA_38X) += \ - armada-381-netgear-gs110emx.dtb \ - armada-382-rd-ac3x-48g4x2xl.dtb \ - armada-385-atl-x530.dtb\ - armada-385-clearfog-gtr-s4.dtb \ - armada-385-clearfog-gtr-l8.dtb \ - armada-385-db-88f6820-amc.dtb \ - armada-385-db-ap.dtb \ - armada-385-linksys-caiman.dtb \ - armada-385-linksys-cobra.dtb \ - armada-385-linksys-rango.dtb \ - armada-385-linksys-shelby.dtb \ - armada-385-synology-ds116.dtb \ - armada-385-turris-omnia.dtb \ - armada-388-clearfog.dtb \ - armada-388-clearfog-base.dtb \ - armada-388-clearfog-pro.dtb \ - armada-388-db.dtb \ - armada-388-gp.dtb \ - armada-388-helios4.dtb \ - armada-388-rd.dtb -dtb-$(CONFIG_MACH_ARMADA_39X) += \ - armada-390-db.dtb \ - armada-395-gp.dtb \ - armada-398-db.dtb -dtb-$(CONFIG_MACH_ARMADA_XP) += \ - armada-xp-axpwifiap.dtb \ - armada-xp-crs305-1g-4s.dtb \ - armada-xp-crs305-1g-4s-bit.dtb \ - armada-xp-crs326-24g-2s.dtb \ - armada-xp-crs326-24g-2s-bit.dtb \ - armada-xp-crs328-4c-20s-4s.dtb \ - armada-xp-crs328-4c-20s-4s-bit.dtb \ - armada-xp-db.dtb \ - armada-xp-db-dxbc2.dtb \ - armada-xp-db-xc3-24g4xg.dtb \ - armada-xp-gp.dtb \ - armada-xp-lenovo-ix4-300d.dtb \ - armada-xp-linksys-mamba.dtb \ - armada-xp-matrix.dtb \ - armada-xp-netgear-rn2120.dtb \ - armada-xp-openblocks-ax3-4.dtb \ - armada-xp-synology-ds414.dtb -dtb-$(CONFIG_MACH_DOVE) += \ - dove-cubox.dtb \ - dove-cubox-es.dtb \ - dove-d2plug.dtb \ - dove-d3plug.dtb \ - dove-dove-db.dtb \ - dove-sbc-a510.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt2701-evb.dtb \ - mt6580-evbp1.dtb \ - mt6582-prestigio-pmt5008-3g.dtb \ - mt6589-aquaris5.dtb \ - mt6589-fairphone-fp1.dtb \ - mt6592-evb.dtb \ - mt7623a-rfb-emmc.dtb \ - mt7623a-rfb-nand.dtb \ - mt7623n-rfb-emmc.dtb \ - mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ - mt8127-moose.dtb \ - mt8135-evbp1.dtb -dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb -dtb-$(CONFIG_ARCH_MSTARV7) += \ - mstar-infinity-msc313-breadbee_crust.dtb \ - mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ - mstar-infinity2m-ssd202d-miyoo-mini.dtb \ - mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ - mstar-infinity2m-ssd202d-ssd201htv2.dtb \ - mstar-infinity2m-ssd202d-unitv2.dtb \ - mstar-infinity3-msc313e-breadbee.dtb \ - mstar-mercury5-ssc8336n-midrived08.dtb -dtb-$(CONFIG_ARCH_ASPEED) += \ - aspeed-ast2500-evb.dtb \ - aspeed-ast2600-evb-a1.dtb \ - aspeed-ast2600-evb.dtb \ - aspeed-bmc-amd-daytonax.dtb \ - aspeed-bmc-amd-ethanolx.dtb \ - aspeed-bmc-ampere-mtjade.dtb \ - aspeed-bmc-ampere-mtmitchell.dtb \ - aspeed-bmc-arm-stardragon4800-rep2.dtb \ - aspeed-bmc-asrock-e3c246d4i.dtb \ - aspeed-bmc-asrock-romed8hm3.dtb \ - aspeed-bmc-bytedance-g220a.dtb \ - aspeed-bmc-delta-ahe50dc.dtb \ - aspeed-bmc-facebook-bletchley.dtb \ - aspeed-bmc-facebook-cloudripper.dtb \ - aspeed-bmc-facebook-cmm.dtb \ - aspeed-bmc-facebook-elbert.dtb \ - aspeed-bmc-facebook-fuji.dtb \ - aspeed-bmc-facebook-galaxy100.dtb \ - aspeed-bmc-facebook-greatlakes.dtb \ - aspeed-bmc-facebook-minipack.dtb \ - aspeed-bmc-facebook-tiogapass.dtb \ - aspeed-bmc-facebook-wedge40.dtb \ - aspeed-bmc-facebook-wedge100.dtb \ - aspeed-bmc-facebook-wedge400.dtb \ - aspeed-bmc-facebook-yamp.dtb \ - aspeed-bmc-facebook-yosemitev2.dtb \ - aspeed-bmc-ibm-bonnell.dtb \ - aspeed-bmc-ibm-everest.dtb \ - aspeed-bmc-ibm-rainier.dtb \ - aspeed-bmc-ibm-rainier-1s4u.dtb \ - aspeed-bmc-ibm-rainier-4u.dtb \ - aspeed-bmc-intel-s2600wf.dtb \ - aspeed-bmc-inspur-fp5280g2.dtb \ - aspeed-bmc-inspur-nf5280m6.dtb \ - aspeed-bmc-inspur-on5263m5.dtb \ - aspeed-bmc-lenovo-hr630.dtb \ - aspeed-bmc-lenovo-hr855xg2.dtb \ - aspeed-bmc-microsoft-olympus.dtb \ - aspeed-bmc-opp-lanyang.dtb \ - aspeed-bmc-opp-mowgli.dtb \ - aspeed-bmc-opp-nicole.dtb \ - aspeed-bmc-opp-palmetto.dtb \ - aspeed-bmc-opp-romulus.dtb \ - aspeed-bmc-opp-swift.dtb \ - aspeed-bmc-opp-tacoma.dtb \ - aspeed-bmc-opp-vesnin.dtb \ - aspeed-bmc-opp-witherspoon.dtb \ - aspeed-bmc-opp-zaius.dtb \ - aspeed-bmc-portwell-neptune.dtb \ - aspeed-bmc-qcom-dc-scm-v1.dtb \ - aspeed-bmc-quanta-q71l.dtb \ - aspeed-bmc-quanta-s6q.dtb \ - aspeed-bmc-supermicro-x11spi.dtb \ - aspeed-bmc-inventec-transformers.dtb \ - aspeed-bmc-tyan-s7106.dtb \ - aspeed-bmc-tyan-s8036.dtb \ - aspeed-bmc-ufispace-ncplite.dtb \ - aspeed-bmc-vegman-n110.dtb \ - aspeed-bmc-vegman-rx20.dtb \ - aspeed-bmc-vegman-sx20.dtb +subdir-y += actions +subdir-y += airoha +subdir-y += allwinner +subdir-y += alphascale +subdir-y += amazon +subdir-y += amlogic +subdir-y += arm +subdir-y += aspeed +subdir-y += axis +subdir-y += broadcom +subdir-y += calxeda +subdir-y += cirrus +subdir-y += cnxt +subdir-y += gemini +subdir-y += hisilicon +subdir-y += hpe +subdir-y += intel +subdir-y += marvell +subdir-y += mediatek +subdir-y += microchip +subdir-y += moxa +subdir-y += nspire +subdir-y += nuvoton +subdir-y += nvidia +subdir-y += nxp +subdir-y += qcom +subdir-y += realtek +subdir-y += renesas +subdir-y += rockchip +subdir-y += samsung +subdir-y += sigmastar +subdir-y += socionext +subdir-y += st +subdir-y += sunplus +subdir-y += synaptics +subdir-y += ti +subdir-y += unisoc +subdir-y += vt8500 +subdir-y += xen +subdir-y += xilinx diff --git a/arch/arm/boot/dts/actions/Makefile b/arch/arm/boot/dts/actions/Makefile new file mode 100644 index 000000000000..f384e4a48e6f --- /dev/null +++ b/arch/arm/boot/dts/actions/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ACTIONS) += \ + owl-s500-cubieboard6.dtb \ + owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-labrador-base-m.dtb \ + owl-s500-roseapplepi.dtb \ + owl-s500-sparky.dtb diff --git a/arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts new file mode 100644 index 000000000000..c2b02895910c --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Cubietech CubieBoard6 + * + * Copyright (c) 2017 Andreas Färber + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "cubietech,cubieboard6", "actions,s500"; + model = "CubieBoard6"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts new file mode 100644 index 000000000000..7ae34a23e320 --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Andreas Färber + */ + +/dts-v1/; + +#include "owl-s500-guitar.dtsi" + +/ { + compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500"; + model = "LeMaker Guitar Base Board rev. B"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500-guitar.dtsi b/arch/arm/boot/dts/actions/owl-s500-guitar.dtsi new file mode 100644 index 000000000000..81cc39871f17 --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-guitar.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * LeMaker Guitar SoM + * + * Copyright (c) 2016-2017 Andreas Färber + */ + +#include "owl-s500.dtsi" + +/ { + compatible = "lemaker,guitar", "actions,s500"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts new file mode 100644 index 000000000000..1585e33f703b --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Caninos Labrador Base Board + * + * Copyright (c) 2019-2020 Matheus Castello + */ + +/dts-v1/; + +#include "owl-s500-labrador-v2.dtsi" + +/ { + model = "Caninos Labrador Core v2 on Labrador Base-M v1"; + compatible = "caninos,labrador-base-m", + "caninos,labrador-v2", "actions,s500"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi new file mode 100644 index 000000000000..883ff2f9886d --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Caninos Labrador SoM V2 + * + * Copyright (c) 2019-2020 Matheus Castello + */ + +#include "owl-s500.dtsi" + +/ { + model = "Caninos Labrador Core V2.1"; + compatible = "caninos,labrador-v2", "actions,s500"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts new file mode 100644 index 000000000000..eb555f385283 --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Roseapple Pi + * + * Copyright (C) 2020-2021 Cristian Ciocaltea + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "roseapplepi,roseapplepi", "actions,s500"; + model = "Roseapple Pi"; + + aliases { + mmc0 = &mmc0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + syspwr: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "SYSPWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + atc260x: pmic@65 { + compatible = "actions,atc2603c"; + reg = <0x65>; + interrupt-parent = <&sirq>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + + reset-time-sec = <6>; + + regulators { + compatible = "actions,atc2603c-regulator"; + + dcdc1-supply = <&syspwr>; + dcdc2-supply = <&syspwr>; + dcdc3-supply = <&syspwr>; + ldo1-supply = <&syspwr>; + ldo2-supply = <&syspwr>; + ldo3-supply = <&syspwr>; + ldo5-supply = <&syspwr>; + ldo6-supply = <&syspwr>; + ldo7-supply = <&syspwr>; + ldo8-supply = <&syspwr>; + ldo11-supply = <&syspwr>; + ldo12-supply = <&syspwr>; + switchldo1-supply = <&vcc>; + + vdd_cpu: dcdc1 { + regulator-name = "VDD_CPU"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + vddq: dcdc2 { + regulator-name = "VDDQ"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <2150000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc: dcdc3 { + regulator-name = "VCC"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_3v3: ldo1 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + avcc: ldo2 { + regulator-name = "AVCC"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8: ldo3 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vcc_3v1: ldo5 { + regulator-name = "VCC_3V1"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + }; + + avdd: ldo6 { + regulator-name = "AVDD"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + sens_1v8: ldo7 { + regulator-name = "SENS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8: ldo8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3300000>; + }; + + svcc: ldo11 { + regulator-name = "SVCC"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + rtc_vdd: ldo12 { + regulator-name = "RTC_VDD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sd_vcc: switchldo1 { + regulator-name = "SD_VCC"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&pinctrl { + i2c0_pins: i2c0-pins { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2-pins { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; + + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias0-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + + bias1-pinconf { + pins = "sd0_clk"; + bias-pull-down; + }; + }; + + ethernet_pins: ethernet-pins { + eth_rmii-pinmux { + groups = "rmii_txd0_mfp", "rmii_txd1_mfp", + "rmii_rxd0_mfp", "rmii_rxd1_mfp", + "rmii_txen_mfp", "rmii_rxen_mfp", + "rmii_crs_dv_mfp", "rmii_ref_clk_mfp"; + function = "eth_rmii"; + }; + + phy_clk-pinmux { + groups = "clko_25m_mfp"; + function = "clko_25m"; + }; + + ref_clk-pinconf { + groups = "rmii_ref_clk_drv"; + drive-strength = <2>; + }; + + }; +}; + +/* uSD */ +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + no-sdio; + no-mmc; + no-1-8-v; + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <&sd_vcc>; + vqmmc-supply = <&sd_vcc>; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + phy-mode = "rmii"; + phy-handle = <ð_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&pinctrl 88 GPIO_ACTIVE_LOW>; /* GPIOC24 */ + reset-delay-us = <10000>; + reset-post-delay-us = <150000>; + + eth_phy: ethernet-phy@3 { + reg = <0x3>; + max-speed = <100>; + interrupt-parent = <&sirq>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&twd_timer { + status = "okay"; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500-sparky.dts b/arch/arm/boot/dts/actions/owl-s500-sparky.dts new file mode 100644 index 000000000000..9d8f7336bec0 --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500-sparky.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Allo.com Sparky + * + * Copyright (c) 2017 Andreas Färber + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "allo,sparky", "actions,s500"; + model = "Allo.com Sparky"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 or 2 GiB */ + }; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/actions/owl-s500.dtsi b/arch/arm/boot/dts/actions/owl-s500.dtsi new file mode 100644 index 000000000000..739b4b9cec8c --- /dev/null +++ b/arch/arm/boot/dts/actions/owl-s500.dtsi @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Actions Semi S500 SoC + * + * Copyright (c) 2016-2017 Andreas Färber + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "actions,s500"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + enable-method = "actions,s500-smp"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x1>; + enable-method = "actions,s500-smp"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x2>; + enable-method = "actions,s500-smp"; + power-domains = <&sps S500_PD_CPU2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x3>; + enable-method = "actions,s500-smp"; + power-domains = <&sps S500_PD_CPU3>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + hosc: hosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + scu: scu@b0020000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xb0020000 0x100>; + }; + + global_timer: timer@b0020200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xb0020200 0x100>; + interrupts = ; + status = "disabled"; + }; + + twd_timer: timer@b0020600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xb0020600 0x20>; + interrupts = ; + status = "disabled"; + }; + + twd_wdt: wdt@b0020620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xb0020620 0xe0>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@b0021000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xb0021000 0x1000>, + <0xb0020100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + l2: cache-controller@b0022000 { + compatible = "arm,pl310-cache"; + reg = <0xb0022000 0x1000>; + cache-unified; + cache-level = <2>; + interrupts = ; + arm,tag-latency = <3 3 2>; + arm,data-latency = <5 3 3>; + }; + + uart0: serial@b0120000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0120000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART0>; + status = "disabled"; + }; + + uart1: serial@b0122000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0122000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART1>; + status = "disabled"; + }; + + uart2: serial@b0124000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0124000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART2>; + status = "disabled"; + }; + + uart3: serial@b0126000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0126000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART3>; + status = "disabled"; + }; + + uart4: serial@b0128000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0128000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART4>; + status = "disabled"; + }; + + uart5: serial@b012a000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb012a000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART5>; + status = "disabled"; + }; + + uart6: serial@b012c000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb012c000 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART6>; + status = "disabled"; + }; + + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@b0170000 { + compatible = "actions,s500-i2c"; + reg = <0xb0170000 0x4000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b0174000 { + compatible = "actions,s500-i2c"; + reg = <0xb0174000 0x4000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b0178000 { + compatible = "actions,s500-i2c"; + reg = <0xb0178000 0x4000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b017c000 { + compatible = "actions,s500-i2c"; + reg = <0xb017c000 0x4000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sirq: interrupt-controller@b01b0200 { + compatible = "actions,s500-sirq"; + reg = <0xb01b0200 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* SIRQ0 */ + , /* SIRQ1 */ + ; /* SIRQ2 */ + }; + + timer: timer@b0168000 { + compatible = "actions,s500-timer"; + reg = <0xb0168000 0x8000>; + interrupts = , + , + , + ; + interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; + }; + + sps: power-controller@b01b0100 { + compatible = "actions,s500-sps"; + reg = <0xb01b0100 0x100>; + #power-domain-cells = <1>; + }; + + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, /* GPIO */ + <0xb01b0040 0x10>, /* Multiplexing Control */ + <0xb01b0060 0x18>, /* PAD Control */ + <0xb01b0080 0xc>; /* PAD Drive Capacity */ + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* GPIOA */ + , /* GPIOB */ + , /* GPIOC */ + , /* GPIOD */ + ; /* GPIOE */ + }; + + dma: dma-controller@b0260000 { + compatible = "actions,s500-dma"; + reg = <0xb0260000 0xd00>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&cmu CLK_DMAC>; + power-domains = <&sps S500_PD_DMA>; + }; + + mmc0: mmc@b0230000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0230000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD0>; + resets = <&cmu RESET_SD0>; + dmas = <&dma 2>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc1: mmc@b0234000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0234000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD1>; + resets = <&cmu RESET_SD1>; + dmas = <&dma 3>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc2: mmc@b0238000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0238000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD2>; + resets = <&cmu RESET_SD2>; + dmas = <&dma 4>; + dma-names = "mmc"; + status = "disabled"; + }; + + ethernet: ethernet@b0310000 { + compatible = "actions,s500-emac", "actions,owl-emac"; + reg = <0xb0310000 0x10000>; + interrupts = ; + clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>; + clock-names = "eth", "rmii"; + resets = <&cmu RESET_ETHERNET>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/airoha/Makefile b/arch/arm/boot/dts/airoha/Makefile new file mode 100644 index 000000000000..00c31389f622 --- /dev/null +++ b/arch/arm/boot/dts/airoha/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AIROHA) += \ + en7523-evb.dtb diff --git a/arch/arm/boot/dts/airoha/en7523-evb.dts b/arch/arm/boot/dts/airoha/en7523-evb.dts new file mode 100644 index 000000000000..f23a25cce119 --- /dev/null +++ b/arch/arm/boot/dts/airoha/en7523-evb.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7523.dtsi" + +/ { + model = "Airoha EN7523 Evaluation Board"; + compatible = "airoha,en7523-evb", "airoha,en7523"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x80200000 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/airoha/en7523.dtsi b/arch/arm/boot/dts/airoha/en7523.dtsi new file mode 100644 index 000000000000..b523a868c4ad --- /dev/null +++ b/arch/arm/boot/dts/airoha/en7523.dtsi @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + npu_binary@84000000 { + no-map; + reg = <0x84000000 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x84B00000 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x85000000 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x86B00000 0x100000>; + }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x86D00000 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x09000000 0x20000>, + <0x09080000 0x80000>, + <0x09400000 0x2000>, + <0x09500000 0x2000>, + <0x09600000 0x20000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <1843200>; + status = "okay"; + }; + + gpio0: gpio@1fbf0200 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0204 0x4>, + <0x1fbf0200 0x4>, + <0x1fbf0220 0x4>, + <0x1fbf0214 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio@1fbf0270 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0270 0x4>, + <0x1fbf0260 0x4>, + <0x1fbf0264 0x4>, + <0x1fbf0278 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts deleted file mode 100644 index 742fcf525e1b..000000000000 --- a/arch/arm/boot/dts/aks-cdu.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * aks-cdu.dts - Device Tree file for AK signal CDU - * - * Copyright (C) 2012 AK signal Brno a.s. - * 2012 Jiri Prchal - */ - -/dts-v1/; - -#include "ge863-pro3.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - }; - - ahb { - apb { - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - usart2: serial@fffb8000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - usart3: serial@fffd0000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - ebi: ebi@10000000 { - nand_controller: nand-controller { - nand: nand@3 { - partitions { - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "ubootenv"; - reg = <0xc0000 0x40000>; - }; - - kernel@100000 { - label = "kernel"; - reg = <0x100000 0x400000>; - }; - - rootfs@500000 { - label = "rootfs"; - reg = <0x500000 0x7b00000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - red { - gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - green { - gpios = <&pioA 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "on"; - }; - - yellow { - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - blue { - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - }; -}; diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile new file mode 100644 index 000000000000..589a1ce1120a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som-evb-emmc.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som-evb-emmc.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb\ + \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ + suniv-f1c200s-popstick-v1.1.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ + suniv-f1c200s-popstick-v1.1.dtb diff --git a/arch/arm/boot/dts/allwinner/axp152.dtsi b/arch/arm/boot/dts/allwinner/axp152.dtsi new file mode 100644 index 000000000000..f90ad6c64a07 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/axp152.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&axp152 { + compatible = "x-powers,axp152"; + interrupt-controller; + #interrupt-cells = <1>; +}; diff --git a/arch/arm/boot/dts/allwinner/axp209.dtsi b/arch/arm/boot/dts/allwinner/axp209.dtsi new file mode 100644 index 000000000000..469d0f7d5185 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/axp209.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP202/209 Integrated Power Management Chip + * http://www.x-powers.com/product/AXP20X.php + * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf + */ + +/ { + pmic-temp { + compatible = "iio-hwmon"; + io-channels = <&axp_adc 4>; /* Internal temperature */ + }; +}; + +&axp209 { + compatible = "x-powers,axp209"; + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp202-ac-power-supply"; + status = "disabled"; + }; + + axp_adc: adc { + compatible = "x-powers,axp209-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp209-battery-power-supply"; + status = "disabled"; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <1500>; + + reg_dcdc2: dcdc2 { + regulator-name = "dcdc2"; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "dcdc3"; + }; + + reg_ldo1: ldo1 { + /* LDO1 is a fixed output regulator */ + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "ldo1"; + }; + + reg_ldo2: ldo2 { + regulator-name = "ldo2"; + }; + + reg_ldo3: ldo3 { + regulator-name = "ldo3"; + }; + + reg_ldo4: ldo4 { + regulator-name = "ldo4"; + }; + + reg_ldo5: ldo5 { + regulator-name = "ldo5"; + status = "disabled"; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp202-usb-power-supply"; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/axp223.dtsi b/arch/arm/boot/dts/allwinner/axp223.dtsi new file mode 100644 index 000000000000..b91b6c1278c7 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/axp223.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright 2016 Free Electrons + * + * Quentin Schulz + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP223 Integrated Power Management Chip + * http://www.x-powers.com/product/AXP22X.php + * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf + * + * The AXP223 shares most of its logic with the AXP221 but it has some + * differences, for the VBUS driver for example. + */ + +#include "axp22x.dtsi" + +&usb_power_supply { + compatible = "x-powers,axp223-usb-power-supply"; +}; diff --git a/arch/arm/boot/dts/allwinner/axp22x.dtsi b/arch/arm/boot/dts/allwinner/axp22x.dtsi new file mode 100644 index 000000000000..f79650afd0a7 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/axp22x.dtsi @@ -0,0 +1,176 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP221/221s/223 Integrated Power Management Chip + * http://www.x-powers.com/product/AXP22X.php + * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf + */ + +&axp22x { + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp221-ac-power-supply"; + status = "disabled"; + }; + + axp_adc: adc { + compatible = "x-powers,axp221-adc"; + #io-channel-cells = <1>; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp221-battery-power-supply"; + status = "disabled"; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp221-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + regulator-name = "dcdc1"; + }; + + reg_dcdc2: dcdc2 { + regulator-name = "dcdc2"; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "dcdc3"; + }; + + reg_dcdc4: dcdc4 { + regulator-name = "dcdc4"; + }; + + reg_dcdc5: dcdc5 { + regulator-name = "dcdc5"; + }; + + reg_dc1sw: dc1sw { + regulator-name = "dc1sw"; + }; + + reg_dc5ldo: dc5ldo { + regulator-name = "dc5ldo"; + }; + + reg_aldo1: aldo1 { + regulator-name = "aldo1"; + }; + + reg_aldo2: aldo2 { + regulator-name = "aldo2"; + }; + + reg_aldo3: aldo3 { + regulator-name = "aldo3"; + }; + + reg_dldo1: dldo1 { + regulator-name = "dldo1"; + }; + + reg_dldo2: dldo2 { + regulator-name = "dldo2"; + }; + + reg_dldo3: dldo3 { + regulator-name = "dldo3"; + }; + + reg_dldo4: dldo4 { + regulator-name = "dldo4"; + }; + + reg_eldo1: eldo1 { + regulator-name = "eldo1"; + }; + + reg_eldo2: eldo2 { + regulator-name = "eldo2"; + }; + + reg_eldo3: eldo3 { + regulator-name = "eldo3"; + }; + + reg_ldo_io0: ldo_io0 { + regulator-name = "ldo_io0"; + status = "disabled"; + }; + + reg_ldo_io1: ldo_io1 { + regulator-name = "ldo_io1"; + status = "disabled"; + }; + + reg_rtc_ldo: rtc_ldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "rtc_ldo"; + }; + + reg_drivevbus: drivevbus { + regulator-name = "drivevbus"; + status = "disabled"; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp221-usb-power-supply"; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/axp809.dtsi b/arch/arm/boot/dts/allwinner/axp809.dtsi new file mode 100644 index 000000000000..d134d4c00bd8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/axp809.dtsi @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP809 Integrated Power Management Chip + */ + +&axp809 { + compatible = "x-powers,axp809"; + interrupt-controller; + #interrupt-cells = <1>; + + axp_gpio: gpio { + compatible = "x-powers,axp809-gpio", + "x-powers,axp221-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi new file mode 100644 index 000000000000..ebaf1c3ce8db --- /dev/null +++ b/arch/arm/boot/dts/allwinner/axp81x.dtsi @@ -0,0 +1,164 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* AXP813/818 Integrated Power Management Chip */ + +&axp81x { + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp813-ac-power-supply"; + status = "disabled"; + }; + + axp_adc: adc { + compatible = "x-powers,axp813-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp813-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp813-battery-power-supply"; + status = "disabled"; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + }; + + reg_dcdc2: dcdc2 { + }; + + reg_dcdc3: dcdc3 { + }; + + reg_dcdc4: dcdc4 { + }; + + reg_dcdc5: dcdc5 { + }; + + reg_dcdc6: dcdc6 { + }; + + reg_dcdc7: dcdc7 { + }; + + reg_aldo1: aldo1 { + }; + + reg_aldo2: aldo2 { + }; + + reg_aldo3: aldo3 { + }; + + reg_dldo1: dldo1 { + }; + + reg_dldo2: dldo2 { + }; + + reg_dldo3: dldo3 { + }; + + reg_dldo4: dldo4 { + }; + + reg_eldo1: eldo1 { + }; + + reg_eldo2: eldo2 { + }; + + reg_eldo3: eldo3 { + }; + + reg_fldo1: fldo1 { + }; + + reg_fldo2: fldo2 { + }; + + reg_fldo3: fldo3 { + }; + + reg_ldo_io0: ldo-io0 { + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_ldo_io1: ldo-io1 { + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_rtc_ldo: rtc-ldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sw: sw { + }; + + reg_drivevbus: drivevbus { + status = "disabled"; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp813-usb-power-supply"; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts new file mode 100644 index 000000000000..20f9ed244851 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts @@ -0,0 +1,255 @@ +/* + * Copyright 2013 Emilio López + * + * Emilio López + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Mele A1000"; + compatible = "mele,a1000", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "a1000:red:usr"; + gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "a1000:blue:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + enable-active-high; + gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts new file mode 100644 index 000000000000..816d534ac093 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts @@ -0,0 +1,151 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "BA10 tvbox"; + compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts new file mode 100644 index 000000000000..74262988881c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts @@ -0,0 +1,159 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include + +/ { + model = "Chuwi V7 CW0825"; + compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + ft5306de4: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-800 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button-1000 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; + + button-1200 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts new file mode 100644 index 000000000000..0645d6064235 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts @@ -0,0 +1,255 @@ +/* + * Copyright 2012 Stefan Roese + * Stefan Roese + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Cubietech Cubieboard"; + compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_cubieboard>; + + led-0 { + label = "cubieboard:blue:usr"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */ + }; + + led-1 { + label = "cubieboard:green:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_cubieboard: led-pins { + pins = "PH20", "PH21"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts new file mode 100644 index 000000000000..63e77c05bfda --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts @@ -0,0 +1,218 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include +#include + +/ { + model = "Dserve DSRV9703C"; + compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_vcc3v3>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + haptics { + compatible = "regulator-haptic"; + haptic-supply = <®_motor>; + min-microvolt = <3000000>; + max-microvolt = <3000000>; + }; + + reg_motor: reg-motor { + compatible = "regulator-fixed"; + regulator-name = "vcc-motor"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + }; +}; + +&codec { + allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + /* pull-ups and devices require AXP209 LDO3 */ + status = "failed"; +}; + +&i2c2 { + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; + + button-800 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts new file mode 100644 index 000000000000..ea7a59dcf8f9 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts @@ -0,0 +1,192 @@ +/* + * Copyright 2015 Priit Laes + * + * Priit Laes + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include + +/ { + model = "Gemei G9 Tablet"; + compatible = "gemei,g9", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* + * TODO: + * 2x cameras via CSI + * AXP battery management + * NAND + * OTG + * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 + */ +&codec { + /* PH15 controls power to external amplifier (ft2012q) */ + allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + /* Accelerometer */ + bma250@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&pio>; + interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */ + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + + status = "okay"; + + button-158 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <158730>; + }; + + button-349 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <349206>; + }; + + button-1142 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1142856>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts new file mode 100644 index 000000000000..47dea0922501 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts @@ -0,0 +1,140 @@ +/* + * Copyright 2012 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Miniand Hackberry"; + compatible = "miniand,hackberry", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + enable-active-high; + gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy0>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts new file mode 100644 index 000000000000..bf2044bac42f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts @@ -0,0 +1,115 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include + +/ { + model = "Hyundai A7HD"; + compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts new file mode 100644 index 000000000000..60e432a0ef1c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts @@ -0,0 +1,229 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include +#include + +/ { + model = "iNet-1"; + compatible = "inet-tek,inet1", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_vcc3v3>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + /* Accelerometer */ + bma250@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&pio>; + interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ + }; +}; + +&i2c2 { + status = "okay"; + + ft5x: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ + touchscreen-size-x = <600>; + touchscreen-size-y = <1024>; + touchscreen-swapped-x-y; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-1000 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; + + button-1200 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts new file mode 100644 index 000000000000..76016f2ca29d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts @@ -0,0 +1,203 @@ +/* + * Copyright 2014 Open Source Support GmbH + * + * David Lanzendörfer + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "INet-97F Rev 02"; + compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-600 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button-800 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button-1000 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; + + button-1200 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts new file mode 100644 index 000000000000..62e7aa587f89 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts @@ -0,0 +1,357 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include + +/ { + model = "iNet-9F Rev 03"; + compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + event-left-joystick-left { + label = "Left Joystick Left"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ + }; + + event-left-joystick-right { + label = "Left Joystick Right"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ + }; + + event-left-joystick-up { + label = "Left Joystick Up"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ + }; + + event-left-joystick-down { + label = "Left Joystick Down"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ + }; + + event-right-joystick-left { + label = "Right Joystick Left"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ + }; + + event-right-joystick-right { + label = "Right Joystick Right"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ + }; + + event-right-joystick-up { + label = "Right Joystick Up"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ + }; + + event-right-joystick-down { + label = "Right Joystick Down"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ + }; + + event-dpad-left { + label = "DPad Left"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ + }; + + event-dpad-right { + label = "DPad Right"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ + }; + + event-dpad-up { + label = "DPad Up"; + linux,code = ; + linux,input-type = ; + linux,input-value = <0xffffffff>; /* -1 */ + gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ + }; + + event-dpad-down { + label = "DPad Down"; + linux,code = ; + linux,input-type = ; + linux,input-value = <1>; + gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ + }; + + event-x { + label = "Button X"; + linux,code = ; + gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ + }; + + event-y { + label = "Button Y"; + linux,code = ; + gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ + }; + + event-a { + label = "Button A"; + linux,code = ; + gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ + }; + + event-b { + label = "Button B"; + linux,code = ; + gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ + }; + + event-select { + label = "Select Button"; + linux,code = ; + gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ + }; + + event-start { + label = "Start Button"; + linux,code = ; + gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ + }; + + event-top-left { + label = "Top Left Button"; + linux,code = ; + gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ + }; + + event-top-right { + label = "Top Right Button"; + linux,code = ; + gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ + }; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + /* Accelerometer */ + bma250@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&pio>; + interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ + }; +}; + +&i2c2 { + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-600 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button-800 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button-1000 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; + + button-1200 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts new file mode 100644 index 000000000000..d4e319d16aae --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Josef Gajdusek + * Copyright 2015 - Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-itead-core-common.dtsi" + +/ { + model = "Iteaduino Plus A10"; + compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + axp209: pmic@34 { + interrupts = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts new file mode 100644 index 000000000000..1aeb0bd5519e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts @@ -0,0 +1,181 @@ +/* + * Copyright 2015 Gábor Nyers + * + * Gábor Nyers + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Jesurun Q5"; + compatible = "jesurun,q5", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "q5:green:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ + }; + + }; + + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + enable-active-high; + gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ + }; +}; + +&ahci { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts new file mode 100644 index 000000000000..81fdb217d339 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts @@ -0,0 +1,182 @@ +/* + * Copyright 2015 Aleksei Mamlin + * Aleksei Mamlin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "HAOYU Electronics Marsboard A10"; + compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "marsboard:red1:usr"; + gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "marsboard:red2:usr"; + gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "marsboard:red3:usr"; + gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "marsboard:red4:usr"; + gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts new file mode 100644 index 000000000000..f9d74e21031d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts @@ -0,0 +1,144 @@ +/* + * Copyright 2012 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "PineRiver Mini X-Plus"; + compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins>; + status = "okay"; +}; + +&ir0_rx_pins { + /* The ir receiver is not always populated */ + bias-pull-up; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts new file mode 100644 index 000000000000..059fe9c5d024 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts @@ -0,0 +1,144 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include + +/ { + model = "MK802"; + compatible = "allwinner,mk802", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts new file mode 100644 index 000000000000..17dcdf031118 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts @@ -0,0 +1,111 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include + +/ { + model = "MK802ii"; + compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts new file mode 100644 index 000000000000..83d283cf6633 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts @@ -0,0 +1,225 @@ +/* + * Copyright 2014 - Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Olimex A10-OLinuXino-LIME"; + compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + led { + label = "a10-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + /* + * The A10-Lime is known to be unstable when running at 1008 MHz + */ + operating-points = + /* kHz uV */ + <912000 1350000>, + <864000 1300000>, + <624000 1250000>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_olinuxinolime: led-pin { + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts new file mode 100644 index 000000000000..a332d61fd561 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts @@ -0,0 +1,200 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "LinkSprite pcDuino"; + compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "pcduino:green:tx"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "pcduino:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Key Back"; + linux,code = ; + gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; + }; + + key-home { + label = "Key Home"; + linux,code = ; + gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; + }; + + key-menu { + label = "Key Menu"; + linux,code = ; + gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ + usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts new file mode 100644 index 000000000000..bc4f128965ed --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts @@ -0,0 +1,67 @@ +/* + * Copyright 2015 Siarhei Siamashka + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The LinkSprite pcDuino2 board is almost identical to the older + * LinkSprite pcDuino1 board. The only software visible difference + * is that the pcDuino2 board got a USB VBUS voltage regulator, which + * is controlled by the PD2 pin (pulled-up by default). Also one of + * the USB host ports has been replaced with a USB WIFI chip. + */ + +#include "sun4i-a10-pcduino.dts" + +/ { + model = "LinkSprite pcDuino2"; + compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; +}; + +®_usb2_vbus { + gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */ + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts new file mode 100644 index 000000000000..c32596947647 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts @@ -0,0 +1,206 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include +#include + +/ { + model = "Point of View Protab2-IPS9"; + compatible = "pov,protab2-ips9", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_vcc3v3>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&codec { + allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + /* pull-ups and devices require AXP209 LDO3 */ + status = "failed"; +}; + +&i2c2 { + status = "okay"; + + touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ + attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ + enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; + wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-400 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; + + button-800 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts new file mode 100644 index 000000000000..3628f12d2521 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Pascal Roeleven + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include +#include + +/ { + model = "Topwise A721"; + compatible = "topwise,a721", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>; + power-supply = <®_vbat>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + brightness-levels = <0 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "starry,kr070pe2t"; + backlight = <&backlight>; + power-supply = <®_lcd_power>; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_panel>; + }; + }; + }; + + reg_lcd_power: reg-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "reg-lcd-power"; + gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + enable-active-high; + }; + + reg_vbat: reg-vbat { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + accelerometer@4c { + compatible = "fsl,mma7660"; + reg = <0x4c>; + }; +}; + +&i2c2 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + vcc-supply = <®_vcc3v3>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-571 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <571428>; + }; + + button-761 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <761904>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-ph-supply = <®_vcc3v3>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&tcon0_out { + tcon0_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi new file mode 100644 index 000000000000..51a6464aab9a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi @@ -0,0 +1,1271 @@ +/* + * Copyright 2012 Stefan Roese + * Stefan Roese + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + ethernet0 = &emac; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd0-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; + status = "disabled"; + }; + + framebuffer-fe0-lcd0-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; + status = "disabled"; + }; + + framebuffer-fe0-lcd0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_fe0-de_be0-lcd0"; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; + status = "disabled"; + }; + + framebuffer-fe0-lcd0-tve0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <1008000 1400000>, + <912000 1350000>, + <864000 1300000>, + <624000 1250000>; + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&rtp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu-alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + de: display-engine { + compatible = "allwinner,sun4i-a10-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + default-pool { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + system-control@1c00000 { + compatible = "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ccu CLK_AHB_DMA>; + #dma-cells = <2>; + }; + + nfc: nand-controller@1c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <55>; + clocks = <&ccu CLK_AHB_EMAC>; + allwinner,sram = <&emac_sram 1>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "disabled"; + }; + + mdio: mdio@1c0b080 { + compatible = "allwinner,sun4i-a10-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <45>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + #clock-cells = <0>; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun4i-a10-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + interrupts = <53>; + allwinner,sram = <&ve_sram 1>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + interrupts = <35>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@1c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_AHB_OTG>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-phy"; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&ccu CLK_USB_PHY>; + clock-names = "usb_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@1c14000 { + compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ccu CLK_AHB_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c14400 { + compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <64>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <86>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + }; + + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun4i-a10-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; + status = "disabled"; + }; + + ehci1: usb@1c1c000 { + compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <40>; + clocks = <&ccu CLK_AHB_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c1c400 { + compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <65>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + csi1: csi@1c1d000 { + compatible = "allwinner,sun4i-a10-csi1"; + reg = <0x01c1d000 0x1000>; + interrupts = <43>; + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "ram"; + resets = <&ccu RST_CSI1>; + status = "disabled"; + }; + + spi3: spi@1c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <50>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 31>, + <&dma SUN4I_DMA_DEDICATED 30>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun4i-a10-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,sun4i-a10-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun4i-a10-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + can0_ph_pins: can0-ph-pins { + pins = "PH20", "PH21"; + function = "can"; + }; + + /omit-if-no-ref/ + csi1_8bits_pg_pins: csi1-8bits-pg-pins { + pins = "PG0", "PG2", "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8", "PG9", "PG10", + "PG11"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_24bits_ph_pins: csi1-24bits-ph-pins { + pins = "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH8", "PH9", + "PH10", "PH11", "PH12", "PH13", "PH14", + "PH15", "PH16", "PH17", "PH18", "PH19", + "PH20", "PH21", "PH22", "PH23", "PH24", + "PH25", "PH26", "PH27"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_clk_pg_pin: csi1-clk-pg-pin { + pins = "PG1"; + function = "csi1"; + }; + + emac_pins: emac0-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "emac"; + }; + + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; + }; + + ir0_rx_pins: ir0-rx-pin { + pins = "PB4"; + function = "ir0"; + }; + + ir0_tx_pins: ir0-tx-pin { + pins = "PB3"; + function = "ir0"; + }; + + ir1_rx_pins: ir1-rx-pin { + pins = "PB23"; + function = "ir1"; + }; + + ir1_tx_pins: ir1-tx-pin { + pins = "PB22"; + function = "ir1"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + ps2_ch0_pins: ps2-ch0-pins { + pins = "PI20", "PI21"; + function = "ps2"; + }; + + ps2_ch1_ph_pins: ps2-ch1-ph-pins { + pins = "PH12", "PH13"; + function = "ps2"; + }; + + pwm0_pin: pwm0-pin { + pins = "PB2"; + function = "pwm"; + }; + + pwm1_pin: pwm1-pin { + pins = "PI3"; + function = "pwm"; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PB13"; + function = "spdif"; + bias-pull-up; + }; + + spi0_pi_pins: spi0-pi-pins { + pins = "PI11", "PI12", "PI13"; + function = "spi0"; + }; + + spi0_cs0_pi_pin: spi0-cs0-pi-pin { + pins = "PI10"; + function = "spi0"; + }; + + spi1_pins: spi1-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + spi1_cs0_pin: spi1-cs0-pin { + pins = "PI16"; + function = "spi1"; + }; + + spi2_pb_pins: spi2-pb-pins { + pins = "PB15", "PB16", "PB17"; + function = "spi2"; + }; + + spi2_pc_pins: spi2-pc-pins { + pins = "PC20", "PC21", "PC22"; + function = "spi2"; + }; + + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB14"; + function = "spi2"; + }; + + spi2_cs0_pc_pins: spi2-cs0-pc-pin { + pins = "PC19"; + function = "spi2"; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; + }; + + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; + }; + + uart1_pins: uart1-pins { + pins = "PA10", "PA11"; + function = "uart1"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>, + <23>, + <24>, + <25>, + <67>, + <68>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + interrupts = <24>; + clocks = <&osc24M>; + }; + + rtc: rtc@1c20d00 { + compatible = "allwinner,sun4i-a10-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = <24>; + }; + + pwm: pwm@1c20e00 { + compatible = "allwinner,sun4i-a10-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <13>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ir0: ir@1c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = <6>; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + + i2s0: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = <31>; + status = "disabled"; + }; + + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-codec"; + reg = <0x01c22c00 0x40>; + interrupts = <30>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sid: eeprom@1c23800 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c23800 0x10>; + }; + + rtp: rtp@1c25000 { + compatible = "allwinner,sun4i-a10-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + #thermal-sensor-cells = <0>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <17>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <18>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <19>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <20>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART7>; + status = "disabled"; + }; + + ps20: ps2@1c2a000 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a000 0x400>; + interrupts = <62>; + clocks = <&ccu CLK_APB1_PS20>; + status = "disabled"; + }; + + ps21: ps2@1c2a400 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a400 0x400>; + interrupts = <63>; + clocks = <&ccu CLK_APB1_PS21>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + can0: can@1c2bc00 { + compatible = "allwinner,sun4i-a10-can"; + reg = <0x01c2bc00 0x400>; + interrupts = <26>; + clocks = <&ccu CLK_APB1_CAN>; + status = "disabled"; + }; + + mali: gpu@1c40000 { + compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <69>, + <70>, + <71>, + <72>, + <73>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be1>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts new file mode 100644 index 000000000000..04b0e6d28769 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts @@ -0,0 +1,137 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" +#include + +/ { + model = "Auxtek t003 A10s hdmi tv-stick"; + compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_t003>; + + led { + label = "t003-tv-dongle:red:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + default-state = "on"; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp152: pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_t003: led-pin { + pins = "PB2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_usb0_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts new file mode 100644 index 000000000000..667bc2dc1ea9 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts @@ -0,0 +1,149 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" +#include + +/ { + model = "Auxtek t004 A10s hdmi tv-stick"; + compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_t004>; + + led { + label = "t004-tv-dongle:red:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + default-state = "on"; + }; + }; + + reg_vmmc1: vmmc1 { + compatible = "regulator-fixed"; + regulator-name = "vmmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp152: pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vmmc1>; + bus-width = <4>; + non-removable; + cap-sdio-irq; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_t004: led-pin { + pins = "PB2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts new file mode 100644 index 000000000000..d0219404c231 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts @@ -0,0 +1,127 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" +#include + +/ { + model = "MK802-A10s"; + compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "mk802:red:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp152: pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts new file mode 100644 index 000000000000..5832bb31fc51 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts @@ -0,0 +1,272 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Olimex A10s-Olinuxino Micro"; + compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; + + led { + label = "a10s-olinuxino-micro:green:usr"; + gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&be0 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pa_pins>; + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp152: pmic@30 { + reg = <0x30>; + interrupts = <0>; + }; +}; + +#include "axp152.dtsi" + +&i2c1 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c16"; + pagesize = <16>; + reg = <0x50>; + read-only; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-191 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191274>; + }; + + button-392 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <392644>; + }; + + button-601 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <601151>; + }; + + button-795 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <795090>; + }; + + button-987 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <987387>; + }; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_olinuxino: led-pin { + pins = "PE3"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_usb0_vbus { + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pb_pins>, + <&spi2_cs0_pb_pin>; + status = "okay"; +}; + +&tcon0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pc_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts new file mode 100644 index 000000000000..964360f0610a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "R7 A10s hdmi tv-stick"; + compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_r7>; + + led { + label = "r7-tv-dongle:green:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + led_pins_r7: led-pin { + pins = "PB2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts new file mode 100644 index 000000000000..ef8baa992687 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts @@ -0,0 +1,195 @@ +/* + * Copyright 2015 Jelle van der Waa + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "A10s-Wobo i5"; + compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "a10s-wobo-i5:blue:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + enable-active-high; + gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pd_pins>; + phy-handle = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_ldo4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi2"; +}; + +®_usb1_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi new file mode 100644 index 000000000000..09c486b608b2 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun5i.dtsi" + +#include + +/ { + aliases { + ethernet0 = &emac; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd0-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, + <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, + <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; + status = "disabled"; + }; + }; + + display-engine { + compatible = "allwinner,sun5i-a10s-display-engine"; + allwinner,pipelines = <&fe0>; + }; + + soc { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + pwm: pwm@1c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&ccu CLK_HOSC>; + #pwm-cells = <3>; + status = "disabled"; + }; + }; +}; + +&ccu { + compatible = "allwinner,sun5i-a10s-ccu"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&pio { + compatible = "allwinner,sun5i-a10s-pinctrl"; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB19", "PB20"; + function = "uart0"; + }; + + uart2_pc_pins: uart2-pc-pins { + pins = "PC18", "PC19"; + function = "uart2"; + }; + + emac_pa_pins: emac-pa-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "emac"; + }; + + mmc1_pins: mmc1-pins { + pins = "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8"; + function = "mmc1"; + drive-strength = <30>; + }; + + spi2_pb_pins: spi2-pb-pins { + pins = "PB12", "PB13", "PB14"; + function = "spi2"; + }; + + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB11"; + function = "spi2"; + }; +}; + +&tcon0_out { + tcon0_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts new file mode 100644 index 000000000000..894c4c4f9a1f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" + +/ { + model = "Difrnce DIT4350"; + compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts new file mode 100644 index 000000000000..d059388d7252 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts @@ -0,0 +1,190 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include +#include + +/ { + model = "Empire Electronix D709 tablet"; + compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + power-supply = <®_vcc3v3>; + /* TODO: backlight uses axp gpio1 as enable pin */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts new file mode 100644 index 000000000000..b1e2afd9de52 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" +#include + +/ { + model = "Empire Electronix M712 tablet"; + compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts new file mode 100644 index 000000000000..9b9f2a574851 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts @@ -0,0 +1,182 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "HSG H702"; + compatible = "hsg,h702", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts new file mode 100644 index 000000000000..439ae3b537df --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" + +/ { + model = "INet-98V Rev 02"; + compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts new file mode 100644 index 000000000000..3a6c4bd0a44f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts @@ -0,0 +1,214 @@ +/* + * Copyright 2016 Icenowy Zheng + * + * Based on sun5i-a13-olinuxino.dts, which is + * Copyright 2012 Maxime Ripard + * Copyright 2013 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Lichee Pi One"; + compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "licheepi:red:usr"; + gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "licheepi:green:usr"; + gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-2 { + label = "licheepi:blue:usr"; + gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; + }; + + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-984 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <984126>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pc_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "csi-1.8v"; +}; + +®_ldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "csi-2.8v"; +}; + +®_usb0_vbus { + gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts new file mode 100644 index 000000000000..bfe1075e62cc --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts @@ -0,0 +1,141 @@ +/* + * Copyright 2012 Maxime Ripard + * Copyright 2013 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Olimex A13-Olinuxino Micro"; + compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinom>; + + led { + label = "a13-olinuxino-micro:green:power"; + gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_olinuxinom: led-pin { + pins = "PG9"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts new file mode 100644 index 000000000000..fadeae3cd8bb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts @@ -0,0 +1,247 @@ +/* + * Copyright 2012 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Olimex A13-Olinuxino"; + compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; + + led { + gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + bridge { + compatible = "dumb-vga-dac"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; +}; + +&be0 { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-191 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191274>; + }; + + button-392 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <392644>; + }; + + button-601 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <601151>; + }; + + button-795 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <795090>; + }; + + button-987 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <987387>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_olinuxino: led-pin { + pins = "PG9"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_usb0_vbus { + status = "okay"; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; + +®_usb1_vbus { + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts new file mode 100644 index 000000000000..d60407772e5d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2019 Ondrej Jirman + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include +#include + +/ { + model = "PocketBook Touch Lux 3"; + compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + power-supply = <®_vcc3v3>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + label = "GPIO Keys"; + + key-right { + label = "Right"; + linux,code = ; + gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */ + }; + + key-left { + label = "Left"; + linux,code = ; + gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */ + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd-1v8-nor-ctp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1v8_nor: regulator-nor { + compatible = "regulator-fixed"; + regulator-name = "vdd-nor"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v8>; + regulator-always-on; + }; + + reg_1v8_ctp: regulator-ctp { + compatible = "regulator-fixed"; + regulator-name = "vdd-ctp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v8>; + }; + + reg_3v3_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-mmc0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */ + vin-supply = <®_vcc3v3>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + status = "okay"; + + /* Touchpanel is connected here. */ +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_3v3_mmc0>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pc_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + /* We need this otherwise the LDO3 would overload */ + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; + status = "okay"; + + epd_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25u4033", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts new file mode 100644 index 000000000000..f9fc1c8b60b8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts @@ -0,0 +1,80 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" + +/ { + model = "Q8 A13 Tablet"; + compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; + + panel: panel { + compatible = "bananapi,s070wv20-ct16"; + power-supply = <®_vcc3v3>; + enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; +}; + +&be0 { + status = "okay"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts new file mode 100644 index 000000000000..be486d28d04f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts @@ -0,0 +1,116 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" +#include + +/ { + model = "Utoo P66"; + compatible = "utoo,p66", "allwinner,sun5i-a13"; + + /* The P66 uses the uart pins as gpios */ + aliases { + /delete-property/serial0; + }; + + chosen { + /delete-property/stdout-path; + }; + + i2c_lcd: i2c { + /* The lcd panel i2c interface is hooked up via gpios */ + compatible = "i2c-gpio"; + sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ + scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */ + i2c-gpio,delay-us = <5>; + }; +}; + +&backlight { + /* Note levels of 10 / 20% result in backlight off */ + brightness-levels = <0 30 40 50 60 70 80 90 100>; + default-brightness-level = <6>; +}; + +&codec { + allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; + +®_usb0_vbus { + gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ +}; + +&touchscreen { + compatible = "chipone,icn8318"; + reg = <0x40>; + /* The P66 uses a different EINT then the reference design */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + /* The icn8318 binding expects wake-gpios instead of power-gpios */ + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + status = "okay"; +}; + +&uart1 { + /* The P66 uses the uart pins as gpios */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi new file mode 100644 index 000000000000..3325ab07094a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright 2012 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun5i.dtsi" + +#include + +/ { + thermal-zones { + cpu-thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&rtp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; + + soc { + pwm: pwm@1c20e00 { + compatible = "allwinner,sun5i-a13-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&ccu CLK_HOSC>; + #pwm-cells = <3>; + status = "disabled"; + }; + + }; +}; + +&ccu { + compatible = "allwinner,sun5i-a13-ccu"; +}; + +&cpu0 { + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <1008000 1400000>, + <912000 1350000>, + <864000 1300000>, + <624000 1200000>, + <576000 1200000>, + <432000 1200000>; + #cooling-cells = <2>; +}; + +&pio { + compatible = "allwinner,sun5i-a13-pinctrl"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts new file mode 100644 index 000000000000..5c3562b85a5b --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts @@ -0,0 +1,238 @@ +/* + * Copyright 2016 Free Electrons + * Copyright 2016 NextThing Co + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-gr8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "NextThing C.H.I.P. Pro"; + compatible = "nextthing,chip-pro", "nextthing,gr8"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "chip-pro:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "disabled"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; + status = "disabled"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; + status = "okay"; + + nand@0 { + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>; + status = "disabled"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +/* + * Both LDO3 and LDO4 are used in parallel to power up the + * WiFi/BT chip. + */ +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + regulator-always-on; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + regulator-always-on; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * The CHIP Pro doesn't have a controllable VBUS, nor does it + * have any 5v rail on the board itself. + * + * If one wants to use it as a true OTG port, it should be + * done in the baseboard, and its DT / overlay will add it. + */ + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts new file mode 100644 index 000000000000..f4fe258ef06d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts @@ -0,0 +1,333 @@ +/* + * Copyright 2016 Free Electrons + * Copyright 2016 NextThing Co + * + * Mylène Josserand + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-gr8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "NextThing GR8-EVB"; + compatible = "nextthing,gr8-evb", "nextthing,gr8"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 10000 0>; + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + power-supply = <®_vcc3v3>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + }; + + sound-analog { + compatible = "simple-audio-card"; + simple-audio-card,name = "gr8-evb-wm8978"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + }; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&be0 { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + wm8978: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-190 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button-390 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + + button-600 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button-800 { + label = "Search"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button-980 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <980000>; + }; + + button-1180 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1180000>; + }; + + button-1400 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <1400000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; + + /* MLC Support sucks for now */ + status = "disabled"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&rtp { + allwinner,ts-attached; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&tve0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * The GR8-EVB has a somewhat interesting design. There's a + * pin supposed to control VBUS, an ID pin, a VBUS detect pin, + * so everything should work just fine. + * + * Except that the pin supposed to control VBUS is not + * connected to any controllable output, neither to the SoC + * through a GPIO or to the PMIC, and it is pulled down, + * meaning that we will never be able to enable VBUS on this + * board. + */ + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi b/arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi new file mode 100644 index 000000000000..98a8fd5e89e8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright 2016 Mylène Josserand + * + * Mylène Josserand + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun5i.dtsi" + +#include +#include +#include + +/ { + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; + + soc { + pwm: pwm@1c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&ccu CLK_HOSC>; + #pwm-cells = <3>; + status = "disabled"; + }; + + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <13>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s0: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; +}; + +&ccu { + compatible = "nextthing,gr8-ccu"; +}; + +&pio { + compatible = "nextthing,gr8-pinctrl"; + + i2s0_data_pins: i2s0-data-pins { + pins = "PB6", "PB7", "PB8", "PB9"; + function = "i2s0"; + }; + + i2s0_mclk_pin: i2s0-mclk-pin { + pins = "PB5"; + function = "i2s0"; + }; + + pwm1_pins: pwm1-pin { + pins = "PG13"; + function = "pwm1"; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PB10"; + function = "spdif"; + bias-pull-up; + }; + + uart1_cts_rts_pins: uart1-cts-rts-pins { + pins = "PG5", "PG6"; + function = "uart1"; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts new file mode 100644 index 000000000000..4192c23848c3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts @@ -0,0 +1,282 @@ +/* + * Copyright 2015 Free Electrons + * Copyright 2015 NextThing Co + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-r8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "NextThing C.H.I.P."; + compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart1; + serial1 = &uart3; + spi0 = &spi2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "chip:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ + }; + + onewire { + compatible = "w1-gpio"; + gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */ + }; +}; + +&be0 { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + xio: gpio@38 { + compatible = "nxp,pcf8574a"; + reg = <0x38>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&pio>; + interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&mmc0_pins { + bias-pull-up; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "cpuvdd"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "corevdd"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "rtcvdd"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +/* + * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT + * Chip. + * + * If those are not enabled, the SDIO part will not enumerate, and + * since there's no way currently to pass DT infos to an SDIO device, + * we cannot really do better than this ugly hack for now. + */ +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + regulator-always-on; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + regulator-always-on; +}; + +®_ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_usb0_vbus { + vin-supply = <®_vcc5v0>; + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pe_pins>; + status = "disabled"; +}; + +&tcon0 { + status = "okay"; +}; + +&tve0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, + <&uart3_cts_rts_pg_pins>; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + status = "okay"; + + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_vcc5v0>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i-r8.dtsi b/arch/arm/boot/dts/allwinner/sun5i-r8.dtsi new file mode 100644 index 000000000000..de35dbcd1191 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-r8.dtsi @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Free Electrons + * Copyright 2015 NextThing Co + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun5i-a13.dtsi" + diff --git a/arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi new file mode 100644 index 000000000000..6847f66699ac --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi @@ -0,0 +1,194 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "sunxi-reference-design-tablet.dtsi" + +#include +#include + +/ { + aliases { + serial0 = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ + power-supply = <®_vcc3v0>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&codec { + allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * All other devices on this bus are also rated for 400KHz. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen@40 { + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&lradc { + vref-supply = <®_ldo2>; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi new file mode 100644 index 000000000000..d7c7b454a11a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi @@ -0,0 +1,819 @@ +/* + * Copyright 2012-2015 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&ccu CLK_CPU>; + }; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; + status = "disabled"; + }; + + framebuffer-lcd0-tve0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; + clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, + <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; + status = "disabled"; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + default-pool { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges; + ranges; + + system-control@1c00000 { + compatible = "allwinner,sun5i-a13-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun5i-a13-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,sun5i-a13-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun5i-a13-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu CLK_MBUS>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ccu CLK_AHB_DMA>; + #dma-cells = <2>; + }; + + nfc: nand-controller@1c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tve0: tv-encoder@1c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ccu CLK_AHB_TVE>; + resets = <&ccu RST_TVE>; + status = "disabled"; + + port { + + tve0_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + + emac: ethernet@1c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <55>; + clocks = <&ccu CLK_AHB_EMAC>; + allwinner,sram = <&emac_sram 1>; + status = "disabled"; + }; + + mdio: mdio@1c0b080 { + compatible = "allwinner,sun4i-a10-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + resets = <&ccu RST_LCD>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD>, + <&ccu CLK_TCON_CH0>, + <&ccu CLK_TCON_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-data-clock"; + #clock-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_be0: endpoint { + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun5i-a13-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + interrupts = <53>; + allwinner,sram = <&ve_sram 1>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@1c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_AHB_OTG>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb_phy"; + resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@1c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ccu CLK_AHB_EHCI>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun5i-a13-crypto", + "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <54>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + }; + + spi2: spi@1c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ccu: clock@1c20000 { + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,sun4i-a10-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + emac_pd_pins: emac-pd-pins { + pins = "PD6", "PD7", "PD10", + "PD11", "PD12", "PD13", "PD14", + "PD15", "PD18", "PD19", "PD20", + "PD21", "PD22", "PD23", "PD24", + "PD25", "PD26", "PD27"; + function = "emac"; + }; + + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PB15", "PB16"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PB17", "PB18"; + function = "i2c2"; + }; + + ir0_rx_pin: ir0-rx-pin { + pins = "PB4"; + function = "ir0"; + }; + + lcd_rgb565_pins: lcd-rgb565-pins { + pins = "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc2_4bit_pe_pins: mmc2-4bit-pe-pins { + pins = "PE4", "PE5", "PE6", "PE7", + "PE8", "PE9"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_pins: mmc2-8bit-pins { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + nand_pins: nand-pins { + pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + function = "nand0"; + }; + + nand_cs0_pin: nand-cs0-pin { + pins = "PC4"; + function = "nand0"; + }; + + nand_rb0_pin: nand-rb0-pin { + pins = "PC6"; + function = "nand0"; + }; + + pwm0_pin: pwm0-pin { + pins = "PB2"; + function = "pwm"; + }; + + spi2_pe_pins: spi2-pe-pins { + pins = "PE1", "PE2", "PE3"; + function = "spi2"; + }; + + spi2_cs0_pe_pin: spi2-cs0-pe-pin { + pins = "PE0"; + function = "spi2"; + }; + + uart1_pe_pins: uart1-pe-pins { + pins = "PE10", "PE11"; + function = "uart1"; + }; + + uart1_pg_pins: uart1-pg-pins { + pins = "PG3", "PG4"; + function = "uart1"; + }; + + uart2_pd_pins: uart2-pd-pins { + pins = "PD2", "PD3"; + function = "uart2"; + }; + + uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { + pins = "PD4", "PD5"; + function = "uart2"; + }; + + uart3_pg_pins: uart3-pg-pins { + pins = "PG9", "PG10"; + function = "uart3"; + }; + + uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { + pins = "PG11", "PG12"; + function = "uart3"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>, + <23>, + <24>, + <25>, + <67>, + <68>; + clocks = <&ccu CLK_HOSC>; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + interrupts = <24>; + clocks = <&osc24M>; + }; + + ir0: ir@1c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = <31>; + status = "disabled"; + }; + + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-codec"; + reg = <0x01c22c00 0x40>; + interrupts = <30>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sid: eeprom@1c23800 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c23800 0x10>; + }; + + rtp: rtp@1c25000 { + compatible = "allwinner,sun5i-a13-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + #thermal-sensor-cells = <0>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART3>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mali: gpu@1c40000 { + compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <69>, <70>, <71>, <72>, <73>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <320000000>; + }; + + timer@1c60000 { + compatible = "allwinner,sun5i-a13-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <82>, <83>; + clocks = <&ccu CLK_AHB_HSTIMER>; + }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE>; + interconnects = <&mbus 19>; + interconnect-names = "dma-mem"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + reg = <1>; + + fe0_out_be0: endpoint { + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE>; + interconnects = <&mbus 18>; + interconnect-names = "dma-mem"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + reg = <0>; + + be0_in_fe0: endpoint { + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + reg = <1>; + + be0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts new file mode 100644 index 000000000000..32d22025ac99 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts @@ -0,0 +1,82 @@ +/* + * Copyright 2014 Boris Brezillon + * + * Boris Brezillon + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Allwinner A31 APP4 EVB1 Evaluation Board"; + compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts new file mode 100644 index 000000000000..93a15eaaa8cb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts @@ -0,0 +1,130 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "WITS A31 Colombus Evaluation Board"; + compatible = "wits,colombus", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2c_lcd: i2c { + /* The lcd panel i2c interface is hooked up via gpios */ + compatible = "i2c-gpio"; + sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */ + scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */ + i2c-gpio,delay-us = <5>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&i2c0 { + status = "fail"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + mma8452: mma8452@1d { + compatible = "fsl,mma8452"; + reg = <0x1d>; + interrupt-parent = <&pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PA9 */ + }; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy { + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts new file mode 100644 index 000000000000..236ebfc06192 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts @@ -0,0 +1,338 @@ +/* + * Copyright 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Merrii A31 Hummingbird"; + compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; + + aliases { + rtc0 = &pcf8563; + rtc1 = &rtc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vga-connector { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_dac_out>; + }; + }; + }; + + vga-dac { + compatible = "dumb-vga-dac"; + vdd-supply = <®_vga_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_dac_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_dac_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + reg_vga_3v3: vga_3v3_regulator { + compatible = "regulator-fixed"; + regulator-name = "vga-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ + }; +}; + +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Speaker", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + /* pull-ups and devices require AXP221 DLDO3 */ + status = "failed"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ + status = "okay"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_dac_in>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts new file mode 100644 index 000000000000..744723d956f0 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts @@ -0,0 +1,178 @@ +/* + * Copyright 2015 Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Mele I7 Quad top set box"; + compatible = "mele,i7", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "i7:blue:usr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&codec { + allwinner,audio-routing = + "Headphone", "HP"; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&tcon0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts new file mode 100644 index 000000000000..7d2eaaf5c33e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts @@ -0,0 +1,212 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Mele M9 top set box"; + compatible = "mele,m9", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "m9:blue:pwr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + phy-supply = <®_dldo1>; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ + status = "okay"; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ethernet-phy"; +}; + +/* + * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached + * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is + * marked as regulator-always-on. + */ +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-hub"; +}; + +®_usb1_vbus { + gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_aldo1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts new file mode 100644 index 000000000000..83611434270c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts @@ -0,0 +1,217 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Mele A1000G Quad top set box"; + compatible = "mele,a1000g-quad", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "a1000g:blue:pwr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + phy-supply = <®_dldo1>; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ + status = "okay"; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ethernet-phy"; +}; + +/* + * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached + * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is + * marked as regulator-always-on. + */ +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-hub"; +}; + +®_usb1_vbus { + gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_aldo1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi new file mode 100644 index 000000000000..5cce4918f84c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi @@ -0,0 +1,1422 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + simplefb_hdmi: framebuffer-lcd0-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, + <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, + <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; + status = "disabled"; + }; + + simplefb_lcd: framebuffer-lcd0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + cpus { + enable-method = "allwinner,sun6i-a31"; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <1008000 1200000>, + <864000 1200000>, + <720000 1100000>, + <480000 1000000>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <1008000 1200000>, + <864000 1200000>, + <720000 1100000>, + <480000 1000000>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <1008000 1200000>, + <864000 1200000>, + <720000 1100000>, + <480000 1000000>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <1008000 1200000>, + <864000 1200000>, + <720000 1100000>, + <480000 1000000>; + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&rtp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-accuracy = <50000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-accuracy = <50000>; + clock-output-names = "ext_osc32k"; + }; + + /* + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. + */ + mii_phy_tx_clk: clk-mii-phy-tx { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk-gmac-int-tx { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@1c200d0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c200d0 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + }; + + de: display-engine { + compatible = "allwinner,sun6i-a31-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun6i-a31-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DMA>; + resets = <&ccu RST_AHB1_DMA>; + #dma-cells = <1>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + dmas = <&dma 11>; + resets = <&ccu RST_AHB1_LCD0>, + <&ccu RST_AHB1_LVDS>; + reset-names = "lcd", + "lvds"; + clocks = <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_LCD0_CH0>, + <&ccu CLK_LCD0_CH1>, + <&ccu 15>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1", + "lvds-alt"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + + tcon0_in_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + dmas = <&dma 12>; + resets = <&ccu RST_AHB1_LCD1>, + <&ccu RST_AHB1_LVDS>; + reset-names = "lcd", "lvds"; + clocks = <&ccu CLK_AHB1_LCD1>, + <&ccu CLK_LCD1_CH0>, + <&ccu CLK_LCD1_CH1>, + <&ccu 15>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1", + "lvds-alt"; + clock-output-names = "tcon1-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon1>; + }; + + tcon1_in_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_AHB1_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_AHB1_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_AHB1_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_AHB1_MMC1>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_AHB1_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_AHB1_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_AHB1_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_AHB1_MMC3>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun6i-a31-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, + <&ccu CLK_HDMI_DDC>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; + resets = <&ccu RST_AHB1_HDMI>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + dmas = <&dma 13>, <&dma 13>, <&dma 14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + usb_otg: usb@1c19000 { + compatible = "allwinner,sun6i-a31-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_AHB1_OTG>; + resets = <&ccu RST_AHB1_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + compatible = "allwinner,sun6i-a31-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB1_EHCI0>; + resets = <&ccu RST_AHB1_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_AHB1_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@1c1b000 { + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB1_EHCI1>; + resets = <&ccu RST_AHB1_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c1b400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_AHB1_OHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_AHB1_OHCI2>; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun6i-a31-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun6i-a31-pinctrl"; + reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + gmac_gmii_pins: gmac-gmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27"; + function = "gmac"; + /* + * data lines in GMII mode run at 125MHz and + * might need a higher signal drive strength + */ + drive-strength = <30>; + }; + + gmac_mii_pins: gmac-mii-pins { + pins = "PA0", "PA1", "PA2", "PA3", + "PA8", "PA9", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA26", "PA27"; + function = "gmac"; + }; + + gmac_rgmii_pins: gmac-rgmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", + "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA25", "PA26", "PA27"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + i2c0_pins: i2c0-pins { + pins = "PH14", "PH15"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH16", "PH17"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PH18", "PH19"; + function = "i2c2"; + }; + + lcd0_rgb888_pins: lcd0-rgb888-pins { + pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_4bit_pins: mmc2-4bit-pins { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC24"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC24"; + function = "mmc3"; + drive-strength = <40>; + bias-pull-up; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PH28"; + function = "spdif"; + }; + + uart0_ph_pins: uart0-ph-pins { + pins = "PH20", "PH21"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + , + , + , + , + ; + clocks = <&osc24M>; + }; + + wdt1: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-spdif"; + reg = <0x01c21000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_APB1_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>, <&dma 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; + resets = <&ccu RST_APB1_DAUDIO0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22400 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; + resets = <&ccu RST_APB1_DAUDIO1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupt-parent = <&r_intc>; + interrupts = ; + status = "disabled"; + }; + + rtp: rtp@1c25000 { + compatible = "allwinner,sun6i-a31-ts"; + reg = <0x01c25000 0x100>; + interrupts = ; + #thermal-sensor-cells = <0>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB2_UART0>; + resets = <&ccu RST_APB2_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB2_UART1>; + resets = <&ccu RST_APB2_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB2_UART2>; + resets = <&ccu RST_APB2_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB2_UART3>; + resets = <&ccu RST_APB2_UART3>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB2_UART4>; + resets = <&ccu RST_APB2_UART4>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB2_UART5>; + resets = <&ccu RST_APB2_UART5>; + dmas = <&dma 22>, <&dma 22>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB2_I2C0>; + resets = <&ccu RST_APB2_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB2_I2C1>; + resets = <&ccu RST_APB2_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB2_I2C2>; + resets = <&ccu RST_APB2_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB2_I2C3>; + resets = <&ccu RST_APB2_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac: ethernet@1c30000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c30000 0x1054>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + resets = <&ccu RST_AHB1_EMAC>; + reset-names = "stmmaceth"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun6i-a31-crypto", + "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_AHB1_SS>; + reset-names = "ahb"; + }; + + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + resets = <&ccu RST_APB1_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timer@1c60000 { + compatible = "allwinner,sun6i-a31-hstimer", + "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_AHB1_HSTIMER>; + resets = <&ccu RST_AHB1_HSTIMER>; + }; + + spi0: spi@1c68000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_AHB1_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c69000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c69000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + resets = <&ccu RST_AHB1_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@1c6a000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c6a000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + dmas = <&dma 25>, <&dma 25>; + dma-names = "rx", "tx"; + resets = <&ccu RST_AHB1_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi3: spi@1c6b000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c6b000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + dmas = <&dma 26>, <&dma 26>; + dma-names = "rx", "tx"; + resets = <&ccu RST_AHB1_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, + <&ccu CLK_DRAM_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, + <&ccu CLK_DRAM_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, + <&ccu CLK_DRAM_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_in_be1>; + }; + }; + }; + }; + + drc1: drc@1e50000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e50000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, + <&ccu CLK_DRAM_DRC1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_drc1>; + }; + }; + + drc1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc1>; + }; + + drc1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, + <&ccu CLK_DRAM_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + reg = <1>; + + be0_out_drc0: endpoint { + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@1e70000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e70000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_DRAM_DRC0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + reg = <0>; + + drc0_in_be0: endpoint { + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + + drc0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc0>; + }; + }; + }; + }; + + rtc: rtc@1f00000 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupt-parent = <&r_intc>; + interrupts = , + ; + clocks = <&osc32k>; + clock-output-names = "osc32k"; + }; + + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + + prcm@1f01400 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "allwinner,sun6i-a31-ar100-clk"; + #clock-cells = <0>; + clocks = <&rtc CLK_OSC32K>, <&osc24M>, + <&ccu CLK_PLL_PERIPH>, + <&ccu CLK_PLL_PERIPH>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun6i-a31-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun6i-a31-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_ir", + "apb0_timer", "apb0_p2wi", + "apb0_uart", "apb0_1wire", + "apb0_i2c"; + }; + + ir_clk: ir_clk { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&rtc CLK_OSC32K>, <&osc24M>; + clock-output-names = "ir"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + + cpucfg@1f01c00 { + compatible = "allwinner,sun6i-a31-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; + + ir: ir@1f02000 { + compatible = "allwinner,sun6i-a31-ir"; + clocks = <&apb0_gates 1>, <&ir_clk>; + clock-names = "apb", "ir"; + resets = <&apb0_rst 1>; + interrupts = ; + reg = <0x01f02000 0x40>; + status = "disabled"; + }; + + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun6i-a31-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; + interrupts = , + ; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + s_ir_rx_pin: s-ir-rx-pin { + pins = "PL4"; + function = "s_ir"; + }; + + s_p2wi_pins: s-p2wi-pins { + pins = "PL0", "PL1"; + function = "s_p2wi"; + }; + }; + + p2wi: i2c@1f03400 { + compatible = "allwinner,sun6i-a31-p2wi"; + reg = <0x01f03400 0x400>; + interrupts = ; + clocks = <&apb0_gates 3>; + clock-frequency = <100000>; + resets = <&apb0_rst 3>; + pinctrl-names = "default"; + pinctrl-0 = <&s_p2wi_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts new file mode 100644 index 000000000000..a2ef7846e2c8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sun6i-reference-design-tablet.dtsi" + +/ { + model = "Colorfly E708 Q1 tablet"; + compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-1000 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; +}; + +®_dldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg"; +}; + +&simplefb_lcd { + vcc-pg-supply = <®_dldo2>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts new file mode 100644 index 000000000000..1d15e15011c6 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts @@ -0,0 +1,104 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" + +/ { + model = "CSQ CS908 top set box"; + compatible = "csq,cs908", "allwinner,sun6i-a31s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts new file mode 100644 index 000000000000..c5e2c55cdc63 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts @@ -0,0 +1,98 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sun6i-reference-design-tablet.dtsi" + +/ { + model = "iNet Q972 tablet"; + compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ + touchscreen-size-x = <768>; + touchscreen-size-y = <1024>; + touchscreen-swapped-x-y; + }; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-200 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-900 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <900000>; + }; + + button-1200 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts new file mode 100644 index 000000000000..b32b70ada7fd --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts @@ -0,0 +1,267 @@ +/* + * Copyright 2014 Siarhei Siamashka + * Copyright 2015 Karsten Merker + * Copyright 2015 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "MSI Primo81 tablet"; + compatible = "msi,primo81", "allwinner,sun6i-a31s"; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + /* rtl8188etv wifi is connected here */ + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + /* pull-ups and device VDDIO use AXP221 DLDO3 */ + status = "failed"; +}; + +&i2c1 { + status = "okay"; + + ctp@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ + touchscreen-swapped-x-y; + }; +}; + +&i2c2 { + status = "okay"; + + accelerometer@1c { + pinctrl-names = "default"; + pinctrl-0 = <&mma8452_int_primo81>; + compatible = "fsl,mma8452"; + reg = <0x1c>; + interrupt-parent = <&pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */ + }; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-158 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <158730>; + }; + + button-349 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <349206>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + status = "okay"; +}; + +&pio { + mma8452_int_primo81: mma8452-int-pin { + pins = "PA9"; + function = "gpio_in"; + bias-pull-up; + }; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo3 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-mipi-bridge"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; + vdd-mipi-bridge-supply = <®_eldo3>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_dldo1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi new file mode 100644 index 000000000000..227ad489731c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi @@ -0,0 +1,141 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Sinlinx SinA31s Core Board"; + compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s"; + + aliases { + serial0 = &uart0; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +/* eMMC on core board */ +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +/* AXP221s PMIC on core board */ +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* UART0 pads available on core board */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts new file mode 100644 index 000000000000..56956352914d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts @@ -0,0 +1,195 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The SinA31s development board has the SinA31s core board soldered on */ +#include "sun6i-a31s-sina31s-core.dtsi" + +#include + +/ { + model = "Sinlinx SinA31s Development Board"; + compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "sina31s:status:usr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + /* USB 2.0 4 port hub IC */ + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + phy-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-158 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <158730>; + }; + + button-349 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <349206>; + }; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts new file mode 100644 index 000000000000..96554ab4f6d3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts @@ -0,0 +1,334 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include + +/ { + model = "Sinovoip BPI-M2"; + compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bpi-m2:blue:usr"; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + }; + + led-1 { + label = "bpi-m2:green:usr"; + gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ + }; + + led-2 { + label = "bpi-m2:red:usr"; + gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */ + }; + }; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_dldo1>; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&s_ir_rx_pin>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */ + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins>; + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-gmac"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vdd-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-mac"; +}; + +®_dldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pb"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd-csi"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pm-cpus"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&pio { + gpio-line-names = + /* PA */ + "ETXD0", "ETXD1", "ETXD2", "ETXD3", "SDC0-DET", "", "", + "", "ETXCLK", "ETXEN", "EGTXCLK", "ERXD0", "ERXD1", + "ERXD2", "ERXD3", "", "", "", "", "ERXDV", "ERXCK", + "ETXERR", "ERXERR", "ECOL", "ECRS", "ECLKIN", "EMDC", + "EMDIO", "", "", "", "", + + /* PB */ + "CN7-P29", "CN7-P31", "CN7-P33", "CN7-P35", "CN7-P37", + "CN7-P28", "CN7-P27", "CN7-P32", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", + + /* PC */ + "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK", + "WL-SDIO-D0", "WL-SDIO-D2", "WL-SDIO-D2", "WL-SDIO-D3", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "USB-DRV", "", "", "", "", + + /* PD */ + "CN9-P09", "CN9-P11", "CN9-P13", "CN9-P15", "CN9-P17", + "CN9-P19", "CN9-P21", "CN9-P23", "CN9-P25", "CN9-P27", + "CN9-P29", "CN9-P31", "CN9-P33", "CN9-P35", "CN9-P37", + "CN9-P39", "CN9-P40", "CN9-P38", "CN9-P36", "CN9-P34", + "CN9-P32", "CN9-P30", "CN9-P28", "CN9-P26", "CN9-P22", + "CN9-P14", "CN9-P18", "CN9-P16", "", "", "", "", + + /* PE */ + "CN6-P20", "CN6-P24", "CN6-P30", "CN6-P28", "CN7-P08", + "CN7-P10", "CN7-P36", "CN7-P38", "CN6-P17", "CN6-P19", + "CN6-P21", "CN6-P23", "CN6-P25", "CN6-P27", "CN6-P29", + "CN6-P31", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", + + /* PF */ + "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", + "SDC0-D2", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", + + /* PG */ + "CN9-P06", "CN9-P08", "CN9-P20", "CN9-P12", "CN9-P07", + "LED-PWR", "CN7-P13", "CN7-P11", "CN7-P22", "CN7-P15", + "LED-G", "LED-B", "CN7-P26", "CN7-P24", "CN7-P23", + "CN7-P19", "CN7-P21", "HCEC", "CN6-P22", "", "", "", "", + "", "", "", "", "", "", "", "", "", + + /* PH */ + "", "", "", "", "", "", "", "", "", "CN7-P07", + "CN7-P12", "CN7-P16", "CN7-P18", "CN9-P10", "CN6-P16", + "CN6-P14", "CN9-P04", "CN9-P02", "CN7-P05", "CN7-P03", + "CN8-P03", "CN8-P02", "", "", "CN6-P34", "CN6-P32", + "CN6-P26", "CN6-P18", "", "", "", ""; +}; + +&r_pio { + gpio-line-names = + /* PL */ + "PMU-SCK", "PMU-SDA", "VBAT-EN", "", "IR-RX", + "WL-WAKE-HOST", "BT-WAKE_HOST", "BT-ENABLE", + "WL-PMU-EN", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", + + /* PM */ + "CN6-P12", "CN6-P35", "CN7-P40", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", ""; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts new file mode 100644 index 000000000000..0b61f5368d44 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -0,0 +1,182 @@ +/* + * Copyright 2015 Lawrence Yu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "Yones TopTech BS1078 v2 Tablet"; + compatible = "yones-toptech,bs1078-v2", "allwinner,sun6i-a31s"; + + aliases { + serial0 = &uart0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + status = "okay"; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd-usb2"; +}; + +®_dc5ldo { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +/* Voltage source for I2C pullup resistors for I2C Bus 0 */ +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; + usb2_vbus-supply = <®_dc1sw>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi new file mode 100644 index 000000000000..97e2c51d0aea --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The A31s is the same die as the A31 in a different package, this is + * reflected by it having different pinctrl compatible everything else is + * identical. + */ + +#include "sun6i-a31.dtsi" + +&de { + compatible = "allwinner,sun6i-a31s-display-engine"; +}; + +&pio { + compatible = "allwinner,sun6i-a31s-pinctrl"; +}; + +&tcon0 { + compatible = "allwinner,sun6i-a31s-tcon"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi new file mode 100644 index 000000000000..f38d19c6be8c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + /* Wifi is connected here */ + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + status = "okay"; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&r_intc>; + interrupts = ; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_dldo1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts new file mode 100644 index 000000000000..caa935ca4f19 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts @@ -0,0 +1,264 @@ +/* + * Copyright 2016 Luo Yi + * + * Thanks to the original work by Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "Banana Pi BPI-M1-Plus"; + compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bananapi-m1-plus:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "bananapi-m1-plus:pwr:usr"; + gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&mmc3 { + #address-cells = <1>; + #size-cells = <0>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; + bus-width = <4>; + non-removable; + wakeup-source; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on usb host ports are tied to DC5V and therefore always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts new file mode 100644 index 000000000000..46ecf9db2324 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts @@ -0,0 +1,333 @@ +/* + * Copyright 2014 Hans de Goede + * + * Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "LeMaker Banana Pi"; + compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart3; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "bananapi:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; + operating-points = + /* kHz uV */ + <960000 1400000>, + <912000 1400000>, + <864000 1350000>, + <720000 1250000>, + <528000 1150000>, + <312000 1100000>, + <144000 1050000>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + vcc-pa-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + gpio-line-names = + /* PA */ + "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", + "ETXD2", "ETXD1", "ETXD0", + "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", + "ETXEN", "ETXCK", "ECRS", + "ECOL", "ETXERR", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PB */ + "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", + "", "USB0-DRV", "", "", "", "", "", "", + "", "", "", "", "SCL", "SDA", "", "", + "", "", "", "", "", "", "", "", + /* PC */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PE */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PF */ + "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", + "SD0-D2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PG */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PH */ + "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", + "", "", "SD0-DET", "", "", "", "", "", + "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", + "LED1", "", "", "", "", "", "", "", + /* PI */ + "", "", "", "IO-GCLK", "", "", "", "", + "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", + "SPI-MISO", "SPI-CE1", "", + "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>, + <&spi0_cs1_pi_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts new file mode 100644 index 000000000000..e22f0e8bb17a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts @@ -0,0 +1,219 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "LeMaker Banana Pro"; + compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart4; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bananapro:blue:usr"; + gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "bananapro:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>, + <&spi0_cs1_pi_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts new file mode 100644 index 000000000000..e35e6990c4b2 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts @@ -0,0 +1,237 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Cubietech Cubieboard2"; + compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "cubieboard2:blue:usr"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "cubieboard2:green:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts new file mode 100644 index 000000000000..52160e368304 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts @@ -0,0 +1,345 @@ +/* + * Copyright 2013 Oliver Schinagl + * + * Oliver Schinagl + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Cubietech Cubietruck"; + compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "cubietruck:blue:usr"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "cubietruck:orange:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "cubietruck:white:usr"; + gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "cubietruck:green:usr"; + gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; + }; + }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ + clocks = <&ccu CLK_OUT_A>; + clock-names = "ext_clock"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + /* Pin outputs low power clock for WiFi and BT */ + pinctrl-0 = <&clk_out_a_pin>; + pinctrl-names = "default"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm20702a1"; + clocks = <&ccu CLK_OUT_A>; + clock-names = "lpo"; + device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ + host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ + shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ + max-speed = <1500000>; + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ + usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts new file mode 100644 index 000000000000..097e479c2772 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Conley Lee + * Conley Lee + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "HAOYU Electronics Marsboard A20"; + compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; + phy-handle = <&phy0>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&gmac_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + gmac_txerr: gmac-txerr-pin { + pins = "PA17"; + function = "gmac"; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts new file mode 100644 index 000000000000..3def2a330598 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts @@ -0,0 +1,233 @@ +/* + * Copyright 2013 Wills Wang + * + * Wills Wang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Merrii A20 Hummingbird"; + compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_mmc3_vdd: mmc3_vdd { + compatible = "regulator-fixed"; + regulator-name = "mmc3_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + }; + + reg_gmac_vdd: gmac_vdd { + compatible = "regulator-fixed"; + regulator-name = "gmac_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_vdd>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ + reset-assert-us = <10000>; + /* wait 1s after reset, otherwise fail to read phy id */ + reset-deassert-us = <1000000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_mmc3_vdd>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pb_pins>, + <&spi2_cs0_pb_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts new file mode 100644 index 000000000000..b21ddd0ec1c2 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts @@ -0,0 +1,198 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "I12 / Q5 / QT840A A20 tvbox"; + compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "i12_tvbox:red:usr"; + gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "i12_tvbox:blue:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vmmc3: vmmc3 { + compatible = "regulator-fixed"; + regulator-name = "vmmc3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; + }; + + reg_vmmc3_io: vmmc3-io { + compatible = "regulator-fixed"; + regulator-name = "vmmc3-io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* This controls VCC-PI, must be always on! */ + regulator-always-on; + enable-active-high; + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + enable-active-high; + gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vmmc3>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts new file mode 100644 index 000000000000..577ead1d02a0 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +/dts-v1/; + +#include "sun7i-a20-icnova-a20.dtsi" + +#include +#include + +/ { + model = "In-Circuit ICnova A20 ADB4006"; + compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +&ac_power_supply { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi new file mode 100644 index 000000000000..46616c6bc899 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts new file mode 100644 index 000000000000..413505f45a81 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts @@ -0,0 +1,164 @@ +/* + * Copyright 2015 Stefan Roese + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "ICnova-A20 SWAC"; + compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts new file mode 100644 index 000000000000..8ff83016ff5a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts @@ -0,0 +1,147 @@ +/* + * Copyright 2015 - Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-itead-core-common.dtsi" + +/ { + model = "Itead Ibox A20"; + compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_itead_core>; + + led-0 { + label = "itead_core:green:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "itead_core:blue:usr"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + axp209: pmic@34 { + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&pio { + led_pins_itead_core: led-pins { + pins = "PH20","PH21"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts new file mode 100644 index 000000000000..97518afe4658 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts @@ -0,0 +1,320 @@ +/* + * Copyright 2015 Jelle de Jong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Lamobo R1"; + compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart3; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "lamobo_r1:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + switch: ethernet-switch@1e { + compatible = "brcm,bcm53125"; + reg = <30>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + label = "lan2"; + }; + + port1: port@1 { + reg = <1>; + label = "lan3"; + }; + + port2: port@2 { + reg = <2>; + label = "lan4"; + }; + + port3: port@3 { + reg = <3>; + label = "wan"; + }; + + port4: port@4 { + reg = <4>; + label = "lan1"; + }; + + port8: port@8 { + reg = <8>; + label = "cpu"; + ethernet = <&gmac>; + phy-mode = "rgmii-txid"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>, + <&spi0_cs1_pi_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts new file mode 100644 index 000000000000..da5a2eea4ce3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2020 Linutronix GmbH + * Author: Benedikt Spranger + */ + +/dts-v1/; +#include "sun7i-a20-lamobo-r1.dts" + +/ { + model = "Lamobo R1"; + compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20"; + + leds { + led-opto1 { + label = "lamobo_r1:opto:powerswitch"; + gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>; + }; + + led-opto2 { + label = "lamobo_r1:opto:relay"; + gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + status = "okay"; + }; + + atecc508a@60 { + compatible = "atmel,atecc508a"; + reg = <0x60>; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts new file mode 100644 index 000000000000..f161d5238860 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts @@ -0,0 +1,156 @@ +/* + * Copyright 2014 Hans de Goede + * + * Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Mele M3"; + compatible = "mele,m3", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "m3:blue:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts new file mode 100644 index 000000000000..1491c603f661 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts @@ -0,0 +1,184 @@ +/* + * Copyright 2015 Marcus Cooper + * + * Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "mk808c"; + compatible = "allwinner,mk808c", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts new file mode 100644 index 000000000000..20bf09b2226c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +/dts-v1/; +#include "sun7i-a20-olimex-som-evb.dts" + +/ { + + model = "Olimex A20-Olimex-SOM-EVB-eMMC"; + compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts new file mode 100644 index 000000000000..f05ee32bc9cb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts @@ -0,0 +1,329 @@ +/* + * Copyright 2015 - Marcus Cooper + * Copyright 2015 - Karsten Merker + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Olimex A20-Olimex-SOM-EVB"; + compatible = "olimex,a20-olimex-som-evb", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "a20-olimex-som-evb:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&codec { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-190 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button-390 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + + button-600 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button-800 { + label = "Search"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button-980 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <980000>; + }; + + button-1180 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1180000>; + }; + + button-1400 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <1400000>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_olimex_som_evb: led-pins { + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pi_pins>, + <&spi1_cs0_pi_pin>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pc_pins>, + <&spi2_cs0_pc_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pi_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts new file mode 100644 index 000000000000..a59755a2e7a9 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-SOM204-EVB-eMMC Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +/dts-v1/; +#include "sun7i-a20-olimex-som204-evb.dts" + +/ { + model = "Olimex A20-SOM204-EVB-eMMC"; + compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts new file mode 100644 index 000000000000..54af6c18075b --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-SOM204-EVB Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + + +#include +#include +#include + +/ { + model = "Olimex A20-SOM204-EVB"; + compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart4; + serial2 = &uart7; + spi0 = &spi1; + spi1 = &spi2; + ethernet1 = &rtl8723bs; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "a20-som204-evb:green:stat"; + gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "a20-som204-evb:green:led1"; + gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-2 { + label = "a20-som204-evb:yellow:led2"; + gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + rtl_pwrseq: rtl_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can_ph_pins>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy3>; + phy-mode = "rgmii"; + phy-supply = <®_vcc3v3>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Exposed to UEXT1 */ +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Exposed to UEXT2 */ +&i2c2 { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy3: ethernet-phy@3 { + reg = <3>; + reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ + reset-assert-us = <10000>; + /* wait 1s after reset, otherwise fail to read phy id */ + reset-deassert-us = <1000000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&rtl_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + uart3_rts_pin: uart3-rts-pin { + pins = "PG8"; + function = "uart3"; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pg"; +}; + +®_usb0_vbus { + gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +/* Exposed to UEXT1 */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pi_pins>, + <&spi1_cs0_pi_pin>; + status = "okay"; +}; + +/* Exposed to UEXT2 */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pc_pins>, + <&spi2_cs0_pc_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* Used for RTL8723BS bluetooth */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>; + status = "okay"; +}; + +/* Exposed to UEXT1 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +/* Exposed to UEXT2 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts new file mode 100644 index 000000000000..033cab3443f8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +#include "sun7i-a20-olinuxino-lime.dts" + +/ { + model = "Olimex A20-OLinuXino-LIME-eMMC"; + compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts new file mode 100644 index 000000000000..92938d022295 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts @@ -0,0 +1,216 @@ +/* + * This is based on sun4i-a10-olinuxino-lime.dts + * + * Copyright 2014 - Hans de Goede + * Copyright (c) 2014 FUKAUMI Naoki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Olimex A20-OLinuXino-LIME"; + compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + led { + label = "a20-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + led_pins_olinuxinolime: led-pins { + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts new file mode 100644 index 000000000000..decb014a382b --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts @@ -0,0 +1,69 @@ + /* + * Copyright 2015 - Ultimaker B.V. + * Author Olliver Schinagl + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun7i-a20-olinuxino-lime2.dts" + +/ { + model = "Olimex A20-OLinuXino-LIME2-eMMC"; + compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts new file mode 100644 index 000000000000..ecb91fb899ff --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts @@ -0,0 +1,280 @@ +/* + * Copyright 2014 - Iain Paton + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Olimex A20-OLinuXino-LIME2"; + compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + led { + label = "a20-olinuxino-lime2:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_axp_ipsout: axp_ipsout { + compatible = "regulator-fixed"; + regulator-name = "axp-ipsout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + vcc-pa-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_ldo3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_ldo4>; + + led_pins_olinuxinolime: led-pins { + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +®_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi0"; + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +®_ldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi1"; +}; + +®_usb0_vbus { + gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts new file mode 100644 index 000000000000..2337b44a88aa --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts @@ -0,0 +1,68 @@ + /* + * Copyright 2017 Olimex Ltd. + * Stefan Mavrodiev + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun7i-a20-olinuxino-micro.dts" + +/ { + model = "Olimex A20-OLinuXino-MICRO-eMMC"; + compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts new file mode 100644 index 000000000000..a1b89b2a2999 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts @@ -0,0 +1,354 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Olimex A20-Olinuxino Micro"; + compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart6; + serial2 = &uart7; + spi0 = &spi1; + spi1 = &spi2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; + + led { + label = "a20-olinuxino-micro:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-191 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191274>; + }; + + button-392 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <392644>; + }; + + button-601 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <601151>; + }; + + button-795 { + label = "Search"; + linux,code = ; + channel = <0>; + voltage = <795090>; + }; + + button-987 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <987387>; + }; + + button-1184 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1184678>; + }; + + button-1398 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <1398804>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + gmac_txerr: gmac-txerr-pin { + pins = "PA17"; + function = "gmac"; + }; + + led_pins_olinuxino: led-pins { + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ahci_5v { + status = "okay"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pi_pins>, + <&spi1_cs0_pi_pin>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pc_pins>, + <&spi2_cs0_pc_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pi_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts new file mode 100644 index 000000000000..84efa01e7cba --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts @@ -0,0 +1,242 @@ +/* + * Copyright 2015 Hans de Goede + * + * Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Orange Pi Mini"; + compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "orangepi:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ + }; + + led-1 { + label = "orangepi:blue:usr"; + gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts new file mode 100644 index 000000000000..5d77f1d9818f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts @@ -0,0 +1,201 @@ +/* + * Copyright 2015 Hans de Goede + * + * Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Orange Pi"; + compatible = "xunlong,orangepi", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "orangepi:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts new file mode 100644 index 000000000000..e40ecb48d726 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts @@ -0,0 +1,225 @@ +/* + * Copyright 2015-2020 Adam Sampson + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "LinkSprite pcDuino3 Nano"; + compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-3 { + label = "pcduino3-nano:green:usr1"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ + }; + + led-4 { + label = "pcduino3-nano:green:usr2"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +/* A single regulator (U24) powers both USB host ports. */ +®_usb1_vbus { + gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts new file mode 100644 index 000000000000..928b86a95f34 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts @@ -0,0 +1,227 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "LinkSprite pcDuino3"; + compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "pcduino3:green:tx"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "pcduino3:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Key Back"; + linux,code = ; + gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; + }; + + key-home { + label = "Key Home"; + linux,code = ; + gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; + }; + + key-menu { + label = "Key Menu"; + linux,code = ; + gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts new file mode 100644 index 000000000000..fef02fcbbdf8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts @@ -0,0 +1,225 @@ +/* + * Copyright 2015 Aleksei Mamlin + * Aleksei Mamlin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include +#include + +/ { + model = "Wexler TAB7200"; + compatible = "wexler,tab7200", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_vcc3v3>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&codec { + allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + gt911: touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ + irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */ + reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */ + touchscreen-swapped-x-y; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-571 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <571428>; + }; + + button-761 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <761904>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts new file mode 100644 index 000000000000..3bfae98f3cc3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts @@ -0,0 +1,209 @@ +/* + * Copyright 2015 Jelle de Jong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Wits Pro A20 DKT"; + compatible = "wits,pro-a20-dkt", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +#include "axp209.dtsi" + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi new file mode 100644 index 000000000000..5574299685ab --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi @@ -0,0 +1,1710 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd0-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, + <&ccu CLK_HDMI>; + status = "disabled"; + }; + + framebuffer-lcd0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_BE0>; + status = "disabled"; + }; + + framebuffer-lcd0-tve0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, + <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <960000 1400000>, + <912000 1400000>, + <864000 1300000>, + <720000 1200000>, + <528000 1100000>, + <312000 1000000>, + <144000 1000000>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = + /* kHz uV */ + <960000 1400000>, + <912000 1400000>, + <864000 1300000>, + <720000 1200000>, + <528000 1100000>, + <312000 1000000>, + <144000 1000000>; + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&rtp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + default-pool { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + /* + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. + */ + mii_phy_tx_clk: clk-mii-phy-tx { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk-gmac-int-tx { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@1c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + }; + + + de: display-engine { + compatible = "allwinner,sun7i-a20-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + system-control@1c00000 { + compatible = "allwinner,sun7i-a20-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun7i-a20-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,sun7i-a20-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun7i-a20-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + + nmi_intc: interrupt-controller@1c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = ; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_DMA>; + #dma-cells = <2>; + }; + + nfc: nand-controller@1c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + }; + + csi0: csi@1c09000 { + compatible = "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; + resets = <&ccu RST_CSI0>; + status = "disabled"; + }; + + emac: ethernet@1c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_EMAC>; + allwinner,sram = <&emac_sram 1>; + status = "disabled"; + }; + + mdio: mdio@1c0b080 { + compatible = "allwinner,sun4i-a10-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun7i-a20-tcon0", + "allwinner,sun7i-a20-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>; + reset-names = "lcd", "lvds"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun7i-a20-tcon1", + "allwinner,sun7i-a20-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + #clock-cells = <0>; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun7i-a20-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_AHB_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_AHB_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_AHB_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_AHB_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@1c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_AHB_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun7i-a20-usb-phy"; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&ccu CLK_USB_PHY>; + clock-names = "usb_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@1c14000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c14400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = ; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun7i-a20-crypto", + "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + }; + + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun7i-a20-hdmi", + "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; + status = "disabled"; + }; + + ehci1: usb@1c1c000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = <&ccu CLK_AHB_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c1c400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + csi1: csi@1c1d000 { + compatible = "allwinner,sun7i-a20-csi1", + "allwinner,sun4i-a10-csi1"; + reg = <0x01c1d000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "ram"; + resets = <&ccu RST_CSI1>; + status = "disabled"; + }; + + spi3: spi@1c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 31>, + <&dma SUN4I_DMA_DEDICATED 30>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun7i-a20-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun7i-a20-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + /omit-if-no-ref/ + can_pa_pins: can-pa-pins { + pins = "PA16", "PA17"; + function = "can"; + }; + + /omit-if-no-ref/ + can_ph_pins: can-ph-pins { + pins = "PH20", "PH21"; + function = "can"; + }; + + /omit-if-no-ref/ + clk_out_a_pin: clk-out-a-pin { + pins = "PI12"; + function = "clk_out_a"; + }; + + /omit-if-no-ref/ + clk_out_b_pin: clk-out-b-pin { + pins = "PI13"; + function = "clk_out_b"; + }; + + /omit-if-no-ref/ + csi0_8bits_pins: csi-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_clk_pin: csi-clk-pin { + pins = "PE1"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi1_8bits_pg_pins: csi1-8bits-pg-pins { + pins = "PG0", "PG2", "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8", "PG9", "PG10", + "PG11"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_24bits_ph_pins: csi1-24bits-ph-pins { + pins = "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH8", "PH9", + "PH10", "PH11", "PH12", "PH13", "PH14", + "PH15", "PH16", "PH17", "PH18", "PH19", + "PH20", "PH21", "PH22", "PH23", "PH24", + "PH25", "PH26", "PH27"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_clk_pg_pin: csi1-clk-pg-pin { + pins = "PG1"; + function = "csi1"; + }; + + /omit-if-no-ref/ + emac_pa_pins: emac-pa-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "emac"; + }; + + /omit-if-no-ref/ + emac_ph_pins: emac-ph-pins { + pins = "PH8", "PH9", "PH10", "PH11", + "PH14", "PH15", "PH16", "PH17", + "PH18", "PH19", "PH20", "PH21", + "PH22", "PH23", "PH24", "PH25", + "PH26"; + function = "emac"; + }; + + /omit-if-no-ref/ + gmac_mii_pins: gmac-mii-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "gmac"; + }; + + /omit-if-no-ref/ + gmac_rgmii_pins: gmac-rgmii-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + /omit-if-no-ref/ + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + /omit-if-no-ref/ + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; + }; + + /omit-if-no-ref/ + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + i2c3_pins: i2c3-pins { + pins = "PI0", "PI1"; + function = "i2c3"; + }; + + /omit-if-no-ref/ + ir0_rx_pin: ir0-rx-pin { + pins = "PB4"; + function = "ir0"; + }; + + /omit-if-no-ref/ + ir0_tx_pin: ir0-tx-pin { + pins = "PB3"; + function = "ir0"; + }; + + /omit-if-no-ref/ + ir1_rx_pin: ir1-rx-pin { + pins = "PB23"; + function = "ir1"; + }; + + /omit-if-no-ref/ + ir1_tx_pin: ir1-tx-pin { + pins = "PB22"; + function = "ir1"; + }; + + /omit-if-no-ref/ + lcd_lvds0_pins: lcd-lvds0-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD6", "PD7", "PD8", "PD9"; + function = "lvds0"; + }; + + /omit-if-no-ref/ + lcd_lvds1_pins: lcd-lvds1-pins { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", + "PD15", "PD16", "PD17", "PD18", "PD19"; + function = "lvds1"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins = "PC6", "PC7", "PC8", + "PC9", "PC10", "PC11"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc3_pins: mmc3-pins { + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + ps2_0_pins: ps2-0-pins { + pins = "PI20", "PI21"; + function = "ps2"; + }; + + /omit-if-no-ref/ + ps2_1_ph_pins: ps2-1-ph-pins { + pins = "PH12", "PH13"; + function = "ps2"; + }; + + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB2"; + function = "pwm"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PI3"; + function = "pwm"; + }; + + /omit-if-no-ref/ + spdif_tx_pin: spdif-tx-pin { + pins = "PB13"; + function = "spdif"; + bias-pull-up; + }; + + /omit-if-no-ref/ + spi0_pi_pins: spi0-pi-pins { + pins = "PI11", "PI12", "PI13"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pi_pin: spi0-cs0-pi-pin { + pins = "PI10"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs1_pi_pin: spi0-cs1-pi-pin { + pins = "PI14"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pi_pins: spi1-pi-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pi_pin: spi1-cs0-pi-pin { + pins = "PI16"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi2_pb_pins: spi2-pb-pins { + pins = "PB15", "PB16", "PB17"; + function = "spi2"; + }; + + /omit-if-no-ref/ + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB14"; + function = "spi2"; + }; + + /omit-if-no-ref/ + spi2_pc_pins: spi2-pc-pins { + pins = "PC20", "PC21", "PC22"; + function = "spi2"; + }; + + /omit-if-no-ref/ + spi2_cs0_pc_pin: spi2-cs0-pc-pin { + pins = "PC19"; + function = "spi2"; + }; + + /omit-if-no-ref/ + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pa_pins: uart1-pa-pins { + pins = "PA10", "PA11"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { + pins = "PA12", "PA13"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart2_pa_pins: uart2-pa-pins { + pins = "PA2", "PA3"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { + pins = "PA0", "PA1"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI18", "PI19"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { + pins = "PI16", "PI17"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart3_pg_pins: uart3-pg-pins { + pins = "PG6", "PG7"; + function = "uart3"; + }; + + /omit-if-no-ref/ + uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { + pins = "PG8", "PG9"; + function = "uart3"; + }; + + /omit-if-no-ref/ + uart3_ph_pins: uart3-ph-pins { + pins = "PH0", "PH1"; + function = "uart3"; + }; + + /omit-if-no-ref/ + uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { + pins = "PH2", "PH3"; + function = "uart3"; + }; + + /omit-if-no-ref/ + uart4_pg_pins: uart4-pg-pins { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart4_ph_pins: uart4-ph-pins { + pins = "PH4", "PH5"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart5_pi_pins: uart5-pi-pins { + pins = "PI10", "PI11"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart6_pa_pins: uart6-pa-pins { + pins = "PA12", "PA13"; + function = "uart6"; + }; + + /omit-if-no-ref/ + uart6_pi_pins: uart6-pi-pins { + pins = "PI12", "PI13"; + function = "uart6"; + }; + + /omit-if-no-ref/ + uart7_pa_pins: uart7-pa-pins { + pins = "PA14", "PA15"; + function = "uart7"; + }; + + /omit-if-no-ref/ + uart7_pi_pins: uart7-pi-pins { + pins = "PI20", "PI21"; + function = "uart7"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = , + , + , + , + , + ; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + interrupts = ; + clocks = <&osc24M>; + }; + + rtc: rtc@1c20d00 { + compatible = "allwinner,sun7i-a20-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = ; + }; + + pwm: pwm@1c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ir0: ir@1c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = ; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = ; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + + i2s1: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 4>, + <&dma SUN4I_DMA_NORMAL 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s0: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = ; + status = "disabled"; + }; + + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun7i-a20-codec"; + reg = <0x01c22c00 0x40>; + interrupts = ; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sid: eeprom@1c23800 { + compatible = "allwinner,sun7i-a20-sid"; + reg = <0x01c23800 0x200>; + }; + + i2s2: i2s@1c24400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c24400 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 6>, + <&dma SUN4I_DMA_NORMAL 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtp: rtp@1c25000 { + compatible = "allwinner,sun5i-a13-ts"; + reg = <0x01c25000 0x100>; + interrupts = ; + #thermal-sensor-cells = <0>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART7>; + status = "disabled"; + }; + + ps20: ps2@1c2a000 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_PS20>; + status = "disabled"; + }; + + ps21: ps2@1c2a400 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a400 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_PS21>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + can0: can@1c2bc00 { + compatible = "allwinner,sun7i-a20-can", + "allwinner,sun4i-a10-can"; + reg = <0x01c2bc00 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_CAN>; + status = "disabled"; + }; + + i2c4: i2c@1c2c000 { + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mali: gpu@1c40000 { + compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + + gmac: ethernet@1c50000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c50000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + + gmac_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + hstimer@1c60000 { + compatible = "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_AHB_HSTIMER>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be1>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi new file mode 100644 index 000000000000..cd4bf60dbb3c --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi @@ -0,0 +1,855 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + simplefb_lcd: framebuffer-lcd0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, + <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; + status = "disabled"; + }; + }; + + de: display-engine { + /* compatible gets set in SoC specific dtsi file */ + allwinner,pipelines = <&fe0>; + status = "disabled"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + cpus { + enable-method = "allwinner,sun8i-a23"; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-accuracy = <50000>; + clock-output-names = "osc24M"; + }; + + ext_osc32k: ext_osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-accuracy = <50000>; + clock-output-names = "ext-osc32k"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + system-control@1c00000 { + compatible = "allwinner,sun8i-a23-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-a23-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-a23-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + nfc: nand-controller@1c03000 { + compatible = "allwinner,sun8i-a23-nand-controller"; + reg = <0x01c03000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + dmas = <&dma 5>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tcon0: lcd-controller@1c0c000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c0c000 0x1000>; + interrupts = ; + dmas = <&dma 12>; + clocks = <&ccu CLK_BUS_LCD>, + <&ccu CLK_LCD_CH0>, + <&ccu 13>; + clock-names = "ahb", + "tcon-ch0", + "lvds-alt"; + clock-output-names = "tcon-data-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_LCD>, + <&ccu RST_BUS_LVDS>; + reset-names = "lcd", + "lvds"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_drc0: endpoint { + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + reg = <1>; + }; + }; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@1c19000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + /* + * compatible and address regions get set in + * SoC specific dtsi file + */ + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI>; + resets = <&ccu RST_BUS_EHCI>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; + resets = <&ccu RST_BUS_OHCI>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; + /* interrupts get set in SoC specific dtsi file */ + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins: i2c0-pins { + pins = "PH2", "PH3"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH4", "PH5"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PE12", "PE13"; + function = "i2c2"; + }; + + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pg_pins: mmc1-pg-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_pins: mmc2-8bit-pins { + pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + nand_pins: nand-pins { + pins = "PC0", "PC1", "PC2", "PC5", + "PC8", "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", "PC15"; + function = "nand0"; + }; + + nand_cs0_pin: nand-cs0-pin { + pins = "PC4"; + function = "nand0"; + bias-pull-up; + }; + + nand_cs1_pin: nand-cs1-pin { + pins = "PC3"; + function = "nand0"; + bias-pull-up; + }; + + nand_rb0_pin: nand-rb0-pin { + pins = "PC6"; + function = "nand0"; + bias-pull-up; + }; + + nand_rb1_pin: nand-rb1-pin { + pins = "PC7"; + function = "nand0"; + bias-pull-up; + }; + + pwm0_pin: pwm0-pin { + pins = "PH0"; + function = "pwm0"; + }; + + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; + }; + + uart1_pg_pins: uart1-pg-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun8i-a23-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupt-parent = <&r_intc>; + interrupts = ; + status = "disabled"; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-a23-mali", + "allwinner,sun7i-a20-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + #cooling-cells = <2>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + fe0: display-frontend@1e00000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e00000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_FE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + reg = <1>; + + fe0_out_be0: endpoint { + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e60000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_BE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + reg = <0>; + + be0_in_fe0: endpoint { + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + reg = <1>; + + be0_out_drc0: endpoint { + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@1e70000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e70000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, + <&ccu CLK_DRAM_DRC>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_DRC>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + reg = <0>; + + drc0_in_be0: endpoint { + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + reg = <1>; + + drc0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + + rtc: rtc@1f00000 { + compatible = "allwinner,sun8i-a23-rtc"; + reg = <0x01f00000 0x400>; + interrupt-parent = <&r_intc>; + interrupts = , + ; + clock-output-names = "osc32k", "osc32k-out"; + clocks = <&ext_osc32k>; + #clock-cells = <1>; + }; + + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + + prcm@1f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + + codec_analog: codec-analog { + compatible = "allwinner,sun8i-a23-codec-analog"; + }; + }; + + cpucfg@1f01c00 { + compatible = "allwinner,sun8i-a23-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; + + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb0_gates 4>; + resets = <&apb0_rst 4>; + status = "disabled"; + }; + + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun8i-a23-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + clocks = <&apb0_gates 6>; + resets = <&apb0_rst 6>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun8i-a23-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + function = "s_i2c"; + bias-pull-up; + }; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + + r_uart_pins_a: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; + }; + + r_rsb: rsb@1f03400 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = ; + clocks = <&apb0_gates 3>; + clock-frequency = <3000000>; + resets = <&apb0_rst 3>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts new file mode 100644 index 000000000000..53fb1be0401a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts @@ -0,0 +1,117 @@ +/* + * Copyright 2015 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Allwinner A23 Evaluation Board"; + compatible = "allwinner,sun8i-a23-evb", "allwinner,sun8i-a23"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &r_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-190 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button-390 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + + button-600 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ + status = "okay"; +}; + +/* + * The RX line has a non-populated resistance. In order to use it, you + * need to solder R207 on the back of the board in order to close the + * line and get a working UART. + */ +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts new file mode 100644 index 000000000000..bcbc9b0758f9 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "Allwinner GT90H Dual Core Tablet (v4)"; + compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; +}; + +&ehci0 { + status = "okay"; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3675"; + firmware-name = "gsl3675-gt90h.fw"; + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + status = "okay"; +}; + +&lradc { + button-600 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts new file mode 100644 index 000000000000..d4405752a414 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts @@ -0,0 +1,67 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-86DZ Rev 01"; + compatible = "primux,inet86dz", "allwinner,sun8i-a23"; +}; + +&ehci0 { + status = "okay"; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-inet86dz.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts new file mode 120000 index 000000000000..c2f22fc33811 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts @@ -0,0 +1 @@ +sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts new file mode 120000 index 000000000000..c2f22fc33811 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts @@ -0,0 +1 @@ +sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts new file mode 100644 index 000000000000..d5f6aebd7216 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "Polaroid MID2407PXE03 tablet"; + compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&i2c1 { + mma7660: accelerometer@4c { + reg = <0x4c>; + compatible = "fsl,mma7660"; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vddio-supply = <®_ldo_io1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts new file mode 100644 index 000000000000..9f9232a2fefb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "Polaroid MID2809PXE04 tablet"; + compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3670"; + firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; + touchscreen-size-x = <1660>; + touchscreen-size-y = <890>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts new file mode 100644 index 000000000000..51097c77a152 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts @@ -0,0 +1,73 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A23 Tablet"; + compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; +}; + +&codec { + allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "Speaker", "HP", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + status = "okay"; +}; + +&panel { + compatible = "bananapi,s070wv20-ct16"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint { + remote-endpoint = <&panel_input>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23.dtsi new file mode 100644 index 000000000000..a5e884a8b2ae --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a23.dtsi @@ -0,0 +1,104 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-a23-a33.dtsi" + +/ { + soc { + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a23-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + }; +}; + +&be0 { + compatible = "allwinner,sun8i-a23-display-backend"; +}; + +&ccu { + compatible = "allwinner,sun8i-a23-ccu"; +}; + +&de { + compatible = "allwinner,sun8i-a23-display-engine"; +}; + +&drc0 { + compatible = "allwinner,sun8i-a23-drc"; +}; + +&fe0 { + compatible = "allwinner,sun8i-a23-display-frontend"; +}; + +&pio { + compatible = "allwinner,sun8i-a23-pinctrl"; + interrupts = , + , + ; +}; + +&tcon0 { + compatible = "allwinner,sun8i-a23-tcon"; +}; + +&usb_otg { + compatible = "allwinner,sun6i-a31-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts new file mode 120000 index 000000000000..4519fd791a8f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts @@ -0,0 +1 @@ +sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts new file mode 100644 index 000000000000..2dfdd0a3151e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts @@ -0,0 +1,95 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "Allwinner GA10H Quad Core Tablet (v1.1)"; + compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; + + aliases { + /* Make u-boot set mac-address for rtl8703as (no eeprom) */ + ethernet0 = &rtl8703as; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3675"; + firmware-name = "gsl3675-ga10h.fw"; + touchscreen-size-x = <1630>; + touchscreen-size-y = <990>; + touchscreen-inverted-y; + status = "okay"; +}; + +&lradc { + button-600 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8703as: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts new file mode 100644 index 000000000000..065cb620aa99 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts @@ -0,0 +1,103 @@ +/* + * Copyright 2015 Hans de Goede + * Copyright 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-D978 Rev 02"; + compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart1; + }; + + chosen { + /* Delete debug UART as serial0 is the UART for bluetooth */ + /delete-property/stdout-path; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_d978>; + + led { + label = "d978:blue:home"; + gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&r_pio { + led_pin_d978: led-pin { + pins = "PL5"; + function = "gpio_out"; + drive-strength = <20>; + }; +}; + +&r_uart { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>, + <&uart1_cts_rts_pg_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts new file mode 120000 index 000000000000..4519fd791a8f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts @@ -0,0 +1 @@ +sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts new file mode 100644 index 000000000000..6fee8f133508 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2016 - Stefan Mavrodiev + * Olimex LTD. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" + +#include +#include + +/ { + model = "Olimex A33-OLinuXino"; + compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "a33-olinuxino:green:usr"; + gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&codec { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&sound { + /* Board level jack widgets */ + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + /* Board level routing. First 2 routes copied from SoC level */ + simple-audio-card,routing = + "Left DAC", "DACL", + "Right DAC", "DACR", + "HP", "HPCOM", + "Headphone Jack", "HP", + "MIC1", "Microphone Jack", + "Microphone Jack", "MBIAS"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts new file mode 100644 index 000000000000..9c5750c25613 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A33 Tablet"; + compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts new file mode 100644 index 000000000000..0c82ff3c7cb4 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts @@ -0,0 +1,275 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Sinlinx SinA33"; + compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "netron-dy,e231732"; + power-supply = <®_vcc3v3>; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_panel>; + }; + }; + }; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&cpu0_opp_table { + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; +}; + +&de { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&lradc { + vref-supply = <®_dcdc1>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191011>; + }; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <391304>; + }; + + button-600 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + }; +}; + +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; + usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi new file mode 100644 index 000000000000..30fdd2703b1f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi @@ -0,0 +1,432 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-a23-a33.dtsi" +#include + +/ { + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + + cpus { + cpu@0 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&ths>; + }; + + mali_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-144000000 { + opp-hz = /bits/ 64 <144000000>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + }; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun8i-a33-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&link_codec>; + simple-audio-card,bitclock-master = <&link_codec>; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,routing = + "Left DAC", "DACL", + "Right DAC", "DACR"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&dai>; + }; + + link_codec: simple-audio-card,codec { + sound-dai = <&codec 0>; + }; + }; + + soc { + video-codec@1c0e000 { + compatible = "allwinner,sun8i-a33-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun8i-a33-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SS>; + reset-names = "ahb"; + }; + + dai: dai@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22c00 0x200>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec: codec@1c22e00 { + #sound-dai-cells = <1>; + compatible = "allwinner,sun8i-a33-codec"; + reg = <0x01c22e00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "bus", "mod"; + status = "disabled"; + }; + + ths: ths@1c25000 { + compatible = "allwinner,sun8i-a33-ths"; + reg = <0x01c25000 0x100>; + #thermal-sensor-cells = <0>; + #io-channel-cells = <0>; + }; + + dsi: dsi@1ca0000 { + compatible = "allwinner,sun6i-a31-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + }; + + thermal-zones { + cpu-thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&gpu_alert0>; + cooling-device = <&mali 1 THERMAL_NO_LIMIT>; + }; + + map3 { + trip = <&gpu_alert1>; + cooling-device = <&mali 2 THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert0: gpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpu_alert1: gpu_alert1 { + /* milliCelsius */ + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&be0 { + compatible = "allwinner,sun8i-a33-display-backend"; + /* A33 has an extra "SAT" module packed inside the display backend */ + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; +}; + +&ccu { + compatible = "allwinner,sun8i-a33-ccu"; +}; + +&de { + compatible = "allwinner,sun8i-a33-display-engine"; +}; + +&drc0 { + compatible = "allwinner,sun8i-a33-drc"; +}; + +&fe0 { + compatible = "allwinner,sun8i-a33-display-frontend"; +}; + +&mali { + operating-points-v2 = <&mali_opp_table>; +}; + +&pio { + compatible = "allwinner,sun8i-a33-pinctrl"; + interrupts = , + ; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB0", "PB1"; + function = "uart0"; + }; + +}; + +&tcon0 { + compatible = "allwinner,sun8i-a33-tcon"; +}; + +&tcon0_out { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + }; +}; + +&usb_otg { + compatible = "allwinner,sun8i-a33-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts new file mode 100644 index 000000000000..c31c97d16024 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -0,0 +1,281 @@ +/* + * Copyright 2015 Vishnu Patekar + * Vishnu Patekar + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +#include + +/ { + model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; + compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb0_vbus: reg-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp818", "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp81x.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ephy"; +}; + +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + regulator-name = "vcc-wifi"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts new file mode 100644 index 000000000000..8d56b103f063 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts @@ -0,0 +1,422 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +#include + +/ { + model = "Banana Pi BPI-M3"; + compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bananapi-m3:blue:usr"; + gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "bananapi-m3:green:usr"; + gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; + + /* + * Power supply for the SATA disk, behind a USB-SATA bridge. + * Since it is a USB device, there is no consumer in the DT, so we + * have to keep this always on. + */ + regulator-sata-disk-pwr { + compatible = "regulator-fixed"; + regulator-name = "sata-disk-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + enable-active-high; + gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ + status = "okay"; + + /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_sw>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + allwinner,rx-delay-ps = <700>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_cir { + clock-frequency = <3000000>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + fldoin-supply = <®_dcdc5>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp81x.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* schematics says 3.1V but FEX file says 3.3V */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + /* + * This powers both the WiFi/BT module's main power, I/O supply, + * and external pull-ups on all the data lines. It should be set + * to the same voltage as the I/O supply (DCDC1 in this case) to + * avoid any leakage or mismatch. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pd"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-name = "vcc-ephy"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ac100_rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo1>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts new file mode 100644 index 000000000000..870993393fc2 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts @@ -0,0 +1,464 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +#include + +/ { + model = "Cubietech Cubietruck Plus"; + compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "cubietruck-plus:blue:usr"; + gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ + }; + + led-1 { + label = "cubietruck-plus:orange:usr"; + gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ + }; + + led-2 { + label = "cubietruck-plus:white:usr"; + gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ + }; + + led-3 { + label = "cubietruck-plus:green:usr"; + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + }; + }; + + usb-hub { + /* I2C is not connected */ + compatible = "smsc,usb3503"; + initial-mode = <1>; /* initialize in HUB mode */ + disabled-ports = <1>; + intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ + connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + refclk-frequency = <19200000>; + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ + }; + + reg_usb2_vbus: reg-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + /* GL830 USB-to-SATA bridge here */ + status = "okay"; +}; + +&ehci1 { + /* USB3503 HSIC USB 2.0 hub here */ + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_dldo4>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_sw>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp818", "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp81x.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* + * The schematics say this should be 3.3V, but the FEX file says + * it should be 3V. The latter makes sense, as the WiFi module's + * I/O is indirectly powered from DCDC1, through SW. It is rated + * at 2.98V maximum. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "dp-pwr"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "ephy-io"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ephy"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-1"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-2"; +}; + +®_fldo1 { + /* TODO should be handled by USB PHY */ + regulator-always-on; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + regulator-name = "vcc-wifi-io"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + clocks = <&ac100_rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dcdc1>; + vddio-supply = <®_sw>; + device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts new file mode 100644 index 000000000000..a7d4ca308990 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts @@ -0,0 +1,506 @@ +/* + * Copyright (C) 2017 Touchless Biometric Systems AG + * Tomas Novotny + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +#include +#include +#include + +/ { + model = "TBS A711 Tablet"; + compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_sw>; + brightness-levels = <0 1 2 4 8 16 32 64 128 255>; + default-brightness-level = <9>; + }; + + panel { + compatible = "tbs,a711-panel", "panel-lvds"; + backlight = <&backlight>; + power-supply = <®_sw>; + + width-mm = <153>; + height-mm = <90>; + data-mapping = "vesa-24"; + + panel-timing { + /* 1024x600 @60Hz */ + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hsync-len = <20>; + hfront-porch = <180>; + hback-porch = <160>; + vfront-porch = <12>; + vback-porch = <23>; + vsync-len = <5>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + + reg_gps: reg-gps { + compatible = "regulator-fixed"; + regulator-name = "gps"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + reg_vbat: reg-vbat { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reg_vmain: reg-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vbat>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + + /* + * This is actually Bluetooth's clock, but we have to + * hook it up somewheere + */ + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + +&de { + status = "okay"; +}; + +/* + * An USB-2 hub is connected here, which also means we don't need to + * enable the OHCI controller. + */ +&ehci0 { + status = "okay"; +}; + +/* + * There's a modem connected here that needs to be initialised before + * being able to be enumerated. + */ +&ehci1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */ + reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */ + vcc-supply = <®_ldo_io0>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&pio>; + interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */ + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + non-removable; + wakeup-source; + keep-power-in-suspend; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pin>; + status = "okay"; +}; + +&r_lradc { + vref-supply = <®_aldo2>; + status = "okay"; + + button-210 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <210000>; + }; + + button-410 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <410000>; + }; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; + +}; + +#include "axp81x.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1.8"; +}; + +®_aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-name = "vdd-drampll"; +}; + +®_aldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-A"; +}; + +®_dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-B"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <4200000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-r"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dsi"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-f"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-hsic"; +}; + +®_fldo2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-vb"; + status = "okay"; +}; + +®_sw { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-lcd"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_lvds_pins>; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint { + remote-endpoint = <&panel_input>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* There's the BT part of the AP6210 connected to that UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm20702a1"; + clocks = <&ac100_rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vbat>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + max-speed = <1500000>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pb_pins>; + status = "okay"; + + gnss { + compatible = "u-blox,neo-6m"; + + v-bckp-supply = <®_rtc_ldo>; + vcc-supply = <®_gps>; + current-speed = <9600>; + }; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_vmain>; + usb2_vbus-supply = <®_vmain>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi new file mode 100644 index 000000000000..94eb3bfc989e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -0,0 +1,1274 @@ +/* + * Copyright 2015 Vishnu Patekar + * + * Vishnu Patekar + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <1>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C0CPUX>; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <3>; + #cooling-cells = <2>; + }; + + cpu100: cpu@100 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <0x100>; + #cooling-cells = <2>; + }; + + cpu101: cpu@101 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <0x101>; + #cooling-cells = <2>; + }; + + cpu102: cpu@102 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <0x102>; + #cooling-cells = <2>; + }; + + cpu103: cpu@103 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + clocks = <&ccu CLK_C1CPUX>; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; + reg = <0x103>; + #cooling-cells = <2>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* TODO: PRCM block has a mux for this. */ + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-accuracy = <50000>; + clock-output-names = "osc24M"; + }; + + /* + * This is called "internal OSC" in some places. + * It is an internal RC-based oscillator. + * TODO: Its controls are in the PRCM block. + */ + osc16M: osc16M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-output-names = "osc16M"; + }; + + osc16Md512: osc16Md512_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <512>; + clock-mult = <1>; + clocks = <&osc16M>; + clock-output-names = "osc16M-d512"; + }; + }; + + de: display-engine { + compatible = "allwinner,sun8i-a83t-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + cpu0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1128000000 { + opp-hz = /bits/ 64 <1128000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + + cpu1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1128000000 { + opp-hz = /bits/ 64 <1128000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-a83t-de2-clk"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_PLL_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rotate: rotate@1020000 { + compatible = "allwinner,sun8i-a83t-de2-rotate"; + reg = <0x1020000 0x10000>; + interrupts = ; + clocks = <&display_clocks CLK_BUS_ROT>, + <&display_clocks CLK_ROT>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_ROT>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + + mixer0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer1>; + }; + + mixer1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; + }; + }; + + cpucfg@1700000 { + compatible = "allwinner,sun8i-a83t-cpucfg"; + reg = <0x01700000 0x400>; + }; + + cci@1790000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01790000 0x10000>; + ranges = <0x0 0x01790000 0x10000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + , + , + , + ; + }; + }; + + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-a83t-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-a83t-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-data-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + + tcon0_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + reg = <1>; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon1>; + }; + + tcon1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-a83t-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + sid: eeprom@1c14000 { + compatible = "allwinner,sun8i-a83t-sid"; + reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 8>; + }; + }; + + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-a83t-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + resets = <&ccu RST_BUS_SS>; + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; + clock-names = "bus", "mod"; + }; + + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-a83t-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + + usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-a83t-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + compatible = "allwinner,sun8i-a83t-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x14>, + <0x01c1b800 0x14>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_HSIC>, + <&ccu CLK_USB_HSIC_12M>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb2_hsic_12M"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_HSIC>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>; + resets = <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-a83t-ohci", + "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@1c1b000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-a83t-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc16Md512>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-a83t-pinctrl"; + interrupt-parent = <&r_intc>; + interrupts = , + , + ; + reg = <0x01c20800 0x400>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + /omit-if-no-ref/ + csi_8bit_parallel_pins: csi-8bit-parallel-pins { + pins = "PE0", "PE2", "PE3", "PE6", "PE7", + "PE8", "PE9", "PE10", "PE11", + "PE12", "PE13"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi_mclk_pin: csi-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + + emac_rgmii_pins: emac-rgmii-pins { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD11", "PD12", "PD13", "PD14", "PD18", + "PD19", "PD21", "PD22", "PD23"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + hdmi_pins: hdmi-pins { + pins = "PH6", "PH7", "PH8"; + function = "hdmi"; + }; + + i2c0_pins: i2c0-pins { + pins = "PH0", "PH1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + + /omit-if-no-ref/ + i2c2_pe_pins: i2c2-pe-pins { + pins = "PE14", "PE15"; + function = "i2c2"; + }; + + i2c2_ph_pins: i2c2-ph-pins { + pins = "PH4", "PH5"; + function = "i2c2"; + }; + + i2s1_pins: i2s1-pins { + /* I2S1 does not have external MCLK pin */ + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s1"; + }; + + lcd_lvds_pins: lcd-lvds-pins { + pins = "PD18", "PD19", "PD20", "PD21", "PD22", + "PD23", "PD24", "PD25", "PD26", "PD27"; + function = "lvds0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { + pins = "PC5", "PC6", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + pwm_pin: pwm-pin { + pins = "PD28"; + function = "pwm"; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PE18"; + function = "spdif"; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB9", "PB10"; + function = "uart0"; + }; + + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; + }; + + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart2_pb_pins: uart2-pb-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun8i-a23-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + + watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-spdif", + "allwinner,sun8i-h3-spdif"; + reg = <0x01c21000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_BUS_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_pins>; + status = "disabled"; + }; + + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-a83t-pwm", + "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + csi: camera@1cb0000 { + compatible = "allwinner,sun8i-a83t-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon1: endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-a83t-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-a83t-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-a83t-r-ccu"; + reg = <0x01f01400 0x400>; + clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, + <&ccu CLK_PLL_PERIPH>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + r_cpucfg@1f01c00 { + compatible = "allwinner,sun8i-a83t-r-cpucfg"; + reg = <0x1f01c00 0x400>; + }; + + r_cir: ir@1f02000 { + compatible = "allwinner,sun8i-a83t-ir", + "allwinner,sun6i-a31-ir"; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; + interrupts = ; + reg = <0x01f02000 0x400>; + pinctrl-names = "default"; + pinctrl-0 = <&r_cir_pin>; + status = "disabled"; + }; + + r_lradc: lradc@1f03c00 { + compatible = "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01f03c00 0x100>; + interrupt-parent = <&r_intc>; + interrupts = ; + status = "disabled"; + }; + + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun8i-a83t-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_cir_pin: r-cir-pin { + pins = "PL12"; + function = "s_cir_rx"; + }; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + }; + + r_rsb: rsb@1f03400 { + compatible = "allwinner,sun8i-a83t-rsb", + "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_APB0_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ths: thermal-sensor@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = ; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + + trips { + cpu0_hot: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_very_hot: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu0_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + + trips { + cpu1_hot: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_very_hot: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu1_hot>; + cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index 000000000000..d729b7c705db --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-4 { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + + gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ + enable-active-high; + gpios-states = <0x1>; + states = <1100000 0>, <1300000 1>; + }; + + reg_vcc_dram: vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + vin-supply = <®_vcc5v0>; + }; + + reg_vcc1v2: vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + vin-supply = <®_vcc5v0>; + }; + + poweroff { + compatible = "regulator-poweroff"; + cpu-supply = <®_vcc1v2>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + /* + * On the production batch of this board the card detect GPIO is + * high active (card inserted), although on the early samples it's + * low active. + */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <1500000>; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + }; + +}; + +&pio { + gpio-line-names = + /* PA */ + "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", + "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", + "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", + "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", + "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", + "CON2-P40", "CON2-P38", "", "", + "", "", "", "", "", "", "", "", + + /* PB */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PC */ + "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", + "CON2-P18", "", "", "CON2-P26", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "CSI-PWR-EN", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PE */ + "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", + "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", + "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", + "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PF */ + "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", + "SDC0-D2", "SDC0-DET", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PG */ + "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", + "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", + "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", + "BT-RST-N", "AP-WAKE-BT", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&r_pio { + gpio-line-names = + /* PL */ + "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", + "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", + "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + /* + * There're two micro-USB connectors, one is power-only and another is + * OTG. The Vbus of these two connectors are connected together, so + * the external USB device will be powered just by the power input + * from the power-only USB port. + */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts new file mode 100644 index 000000000000..4db0d4bb65eb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Chen-Yu Tsai + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-libretech-all-h3-cc.dtsi" + +/ { + model = "Libre Computer Board ALL-H3-CC H2+"; + compatible = "libretech,all-h3-cc-h2-plus", "allwinner,sun8i-h2-plus"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts new file mode 100644 index 000000000000..3356f4210d45 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* Orange Pi R1 is based on Orange Pi Zero design */ +#include "sun8i-h2-plus-orangepi-zero.dts" + +/ { + model = "Xunlong Orange Pi R1"; + compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; + + /delete-node/ reg_vcc_wifi; + + /* + * Ths pin of this regulator is the same with the Wi-Fi extra + * regulator on the original Zero. However it's used for USB + * Ethernet rather than the Wi-Fi now. + */ + reg_vcc_usb_eth: reg-vcc-usb-ethernet { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-ethernet"; + enable-active-high; + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; + + aliases { + ethernet1 = &rtl8189etv; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; + }; +}; + +&ohci1 { + /* + * RTL8152B USB-Ethernet adapter is connected to USB1, + * and it's a USB 2.0 device. So the OHCI1 controller + * can be left disabled. + */ + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc_usb_eth>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts new file mode 100644 index 000000000000..3706216ffb40 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * Based on sun8i-h3-orangepi-one.dts, which is: + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Xunlong Orange Pi Zero"; + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; + ethernet1 = &xr819; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc_wifi: reg_vcc_wifi { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + enable-active-high; + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; + + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + enable-active-high; + gpios-states = <1>; + states = <1100000 0>, <1300000 1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + xr819: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&spi0 { + /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* + * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only + * power up the board; when it's used as OTG port, this VBUS is + * always off even if the board is powered via GPIO pins. + */ + status = "okay"; + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts new file mode 100644 index 000000000000..fc4a8c3d084d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Chen-Yu Tsai + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-bananapi-m2-plus-v1.2.dtsi" + +/ { + model = "Banana Pi BPI-M2-Plus v1.2 H3"; + compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts new file mode 100644 index 000000000000..195a75da13f1 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-bananapi-m2-plus.dtsi" + +/ { + model = "Banana Pi BPI-M2-Plus H3"; + compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts new file mode 100644 index 000000000000..a6d38ecee141 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2017 Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Beelink X2"; + compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + ethernet1 = &sdiowifi; + }; + + cec { + compatible = "cec-gpio"; + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ + hdmi-phandle = <&hdmi>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "beelink-x2:blue:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + led-1 { + label = "beelink-x2:red:standby"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + sound_spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + linux,rc-map-name = "rc-tanix-tx3mini"; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + sdiowifi: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on except for the OTG port */ + status = "okay"; + usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ + usb0_vbus-supply = <®_usb0_vbus>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts new file mode 100644 index 000000000000..02fbe00cde97 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTS for Emlid Neutis N5 Dev board. + * + * Copyright (C) 2019 Georgii Staroselskii + */ + +/dts-v1/; + +#include "sun8i-h3-emlid-neutis-n5h3.dtsi" + +/ { + model = "Emlid Neutis N5H3 Developer board"; + compatible = "emlid,neutis-n5h3-devboard", + "emlid,neutis-n5h3", + "allwinner,sun8i-h3"; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&codec { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi new file mode 100644 index 000000000000..35e71f46c197 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTSI for Emlid Neutis N5 SoM. + * + * Copyright (C) 2019 Georgii Staroselskii + */ + +/dts-v1/; + +#include "sun8i-h3.dtsi" +#include "sunxi-h3-h5-emlid-neutis.dtsi" diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts new file mode 100644 index 000000000000..a8b2f0f1c11d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-libretech-all-h3-cc.dtsi" + +/ { + model = "Libre Computer Board ALL-H3-CC H3"; + compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts new file mode 100644 index 000000000000..f5c8ccc5b872 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Centrum Embedded Systems, Jia-Bin Huang + * Copyright (C) 2018 Jonathan McDowell + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "MapleBoard MP130"; + compatible = "mapleboard,mp130", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "mp130:orange:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "mp130:orange:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ + }; + + key-user { + label = "user"; + linux,code = ; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "LINEIN", "Line In"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts new file mode 100644 index 000000000000..343b02b97155 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Karl Palsson + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "FriendlyARM NanoPi Duo2"; + compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "nanopi:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + led-1 { + label = "nanopi:green:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "k1"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ + }; + }; + + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <50>; /* 4ms */ + + enable-active-high; + enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0>, <1300000 1>; + }; + + reg_vcc_dram: vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + vin-supply = <®_vcc5v0>; + }; + + reg_vdd_sys: vdd-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd-sys"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + vin-supply = <®_vcc5v0>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; + +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + +&usb_otg { + status = "okay"; + dr_mode = "otg"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts new file mode 100644 index 000000000000..4ba533b0340f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1 Plus"; + compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; + + aliases { + serial1 = &uart3; + ethernet0 = &emac; + ethernet1 = &sdio_wifi; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts new file mode 100644 index 000000000000..69243dcb30a6 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1"; + compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts new file mode 100644 index 000000000000..9e1a33f94cad --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2017 Jelle van der Waa + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + model = "FriendlyARM NanoPi NEO Air"; + compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + led-1 { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts new file mode 100644 index 000000000000..df71fab3cf4e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 James Pettigrew + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyARM NanoPi NEO"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts new file mode 100644 index 000000000000..42cd1131adf3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Igor Pecovnik + * Copyright (C) 2020 Jayantajit Gogoi + * Copyright (C) 2020 Yu-Tung Chang +*/ + +#include "sun8i-h3-nanopi.dtsi" +#include + +/ { + model = "FriendlyARM NanoPi R1"; + compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; + + aliases { + serial1 = &uart1; + ethernet0 = &emac; + ethernet1 = &wifi; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; + + reg_vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0x0>, + <1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; + + leds { + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + }; + + led-3 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */ + }; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + +&usb_otg { + status = "okay"; + dr_mode = "otg"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi new file mode 100644 index 000000000000..cf8413fba6c1 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2016 James Pettigrew + * Copyright (C) 2016 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "k1"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts new file mode 100644 index 000000000000..f1f9dbead32a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Xunlong Orange Pi 2"; + compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; + ethernet1 = &rtl8189; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-2 { + label = "sw2"; + linux,code = ; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; + }; + + switch-4 { + label = "sw4"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ + }; +}; + +&codec { + allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + allwinner,audio-routing = + "Speaker", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189: sdio_wifi@1 { + reg = <1>; + }; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts new file mode 100644 index 000000000000..305b34a321f5 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Xunlong Orange Pi Lite"; + compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; + + aliases { + /* The H3 emac is not used so the wifi is ethernet0 */ + ethernet0 = &rtl8189ftv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-4 { + label = "sw4"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts new file mode 100644 index 000000000000..59f6f6d5e7ca --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Xunlong Orange Pi One"; + compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-4 { + label = "sw4"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + enable-active-high; + gpios-states = <0x1>; + states = <1100000 0>, <1300000 1>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts new file mode 100644 index 000000000000..babf4cf1b2f6 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The Orange Pi PC Plus is an extended version of the regular PC */ +#include "sun8i-h3-orangepi-pc.dts" + +/ { + model = "Xunlong Orange Pi PC Plus"; + compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; + + aliases { + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; + }; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; + /* eMMC is missing pull-ups */ + bias-pull-up; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts new file mode 100644 index 000000000000..b96e015f54ee --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2015 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Xunlong Orange Pi PC"; + compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-4 { + label = "sw4"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + reg_vdd_cpux: regulator@65 { + compatible = "silergy,sy8106a"; + reg = <0x65>; + regulator-name = "vdd-cpux"; + silergy,fixed-microvolt = <1200000>; + /* + * The datasheet uses 1.1V as the minimum value of VDD-CPUX, + * however both the Armbian DVFS table and the official one + * have operating points with voltage under 1.1V, and both + * DVFS table are known to work properly at the lowest + * operating point. + * + * Use 1.0V as the minimum voltage instead. + */ + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on USB host ports are always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts new file mode 100644 index 000000000000..d05fa679dcd3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ +#include "sun8i-h3-orangepi-2.dts" + +/ { + model = "Xunlong Orange Pi Plus / Plus 2"; + compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; + /* eMMC is missing pull-ups */ + bias-pull-up; +}; + +&r_i2c { + status = "okay"; + + reg_vdd_cpux: regulator@65 { + compatible = "silergy,sy8106a"; + reg = <0x65>; + regulator-name = "vdd-cpux"; + silergy,fixed-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <200>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&usbphy { + usb3_vbus-supply = <®_usb3_vbus>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts new file mode 100644 index 000000000000..b6ca45d18e51 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, + * with 2G RAM and an external gbit ethernet phy. + */ + +#include "sun8i-h3-orangepi-pc-plus.dts" + +/ { + model = "Xunlong Orange Pi Plus 2E"; + compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts new file mode 100644 index 000000000000..561ea1d2f861 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2017 Jagan Teki + * Copyright (C) 2018 Diego Rondini + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun8i-h3.dtsi" + +#include + +/ { + model = "OrangePi Zero Plus2 H3"; + compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "orangepi:red:status"; + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + post-power-on-delay-ms = <200>; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * According to schematics CN1 MicroUSB port can be used to take + * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB + * port cannot provide power externally even if the board is powered + * via GPIO pins. It thus makes sense to force peripheral mode. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts new file mode 100644 index 000000000000..4738f3a9efe4 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Bootlin + * Author: Paul Kocialkowski + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "RerVision H3-DVK"; + compatible = "rervision,h3-dvk", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts new file mode 100644 index 000000000000..7d3e7323b661 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2020 Yu-Tung Chang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyARM ZeroPi"; + compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi new file mode 100644 index 000000000000..eac2349a2380 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-h3-h5.dtsi" +#include + +/ { + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000 1040000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + soc { + deinterlace: deinterlace@1400000 { + compatible = "allwinner,sun8i-h3-deinterlace"; + reg = <0x01400000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + <&ccu CLK_DRAM_DEINTERLACE>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = ; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-h3-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun8i-h3-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-h3-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + operating-points-v2 = <&gpu_opp_table>; + }; + + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&ccu { + compatible = "allwinner,sun8i-h3-ccu"; +}; + +&display_clocks { + compatible = "allwinner,sun8i-h3-de2-clk"; +}; + +&mbus { + compatible = "allwinner,sun8i-h3-mbus"; +}; + +&mmc0 { + compatible = "allwinner,sun7i-a20-mmc"; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; +}; + +&mmc1 { + compatible = "allwinner,sun7i-a20-mmc"; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; +}; + +&mmc2 { + compatible = "allwinner,sun7i-a20-mmc"; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; +}; + +&pio { + compatible = "allwinner,sun8i-h3-pinctrl"; +}; + +&rtc { + compatible = "allwinner,sun8i-h3-rtc"; +}; + +&sid { + compatible = "allwinner,sun8i-h3-sid"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi b/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi new file mode 100644 index 000000000000..3d9a1524e17e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "sunxi-reference-design-tablet.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + aliases { + serial0 = &r_uart; + /* Make u-boot set mac-address for wifi without an eeprom */ + ethernet0 = &sdio_wifi; + }; + + panel: panel { + /* Tablet dts should provide panel compatible */ + backlight = <&backlight>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_dc1sw>; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + /* + * Q8 boards use various PL# pins as wifi-en. On other boards + * these may be connected to a wifi module output pin. To avoid + * short-circuits we configure these as inputs with pull-ups via + * pinctrl, instead of listing them as active-low reset-gpios. + */ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_q8>; + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + }; +}; + +&r_pio { + wifi_pwrseq_pin_q8: wifi-pwrseq-pins { + pins = "PL6", "PL7", "PL11"; + function = "gpio_in"; + bias-pull-up; + }; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts new file mode 100644 index 000000000000..bc394686fedb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2017 Free Electrons + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" + +#include + +/ { + model = "BananaPi M2 Magic"; + compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bpi-m2m:blue:usr"; + gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "bpi-m2m:green:usr"; + gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "bpi-m2m:red:power"; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&cpu0_opp_table { + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* + * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same + * time, with the two being in sync. Since this is not really + * supported right now, just use the two as always on, and we will fix + * it later. + */ +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi0"; +}; + +®_dldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_dldo1>; + vddio-supply = <®_aldo3>; + device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts new file mode 100644 index 000000000000..246dec5846a4 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* Copyright (c) 2016 FUKAUMI Naoki */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Nintendo NES Classic Edition"; + compatible = "nintendo,nes-classic", "allwinner,sun8i-r16", + "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + /* + * UART0 is available on two ports: PB and PF, both are accessible. + * PF can also be used for the SD card so PB is preferred. + */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pf_pins>; + status = "okay"; +}; + +&nfc { + status = "okay"; + + /* 2Gb Macronix MX30LF2G18AC (3V) */ + nand@0 { + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&usb_otg { + status = "okay"; + dr_mode = "otg"; +}; + +&usbphy { + /* VBUS is always on because it is wired to the power supply */ + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts new file mode 100644 index 000000000000..80761d7904ec --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* Copyright (c) 2018 Miquèl RAYNAL */ + +/dts-v1/; +#include "sun8i-r16-nintendo-nes-classic.dts" + +/ { + model = "Nintendo SuperNES Classic Edition"; + compatible = "nintendo,super-nes-classic", "nintendo,nes-classic", + "allwinner,sun8i-r16", "allwinner,sun8i-a33"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts new file mode 100644 index 000000000000..95543a9c2118 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts @@ -0,0 +1,313 @@ +/* + * Copyright 2016 Quentin Schulz + * + * Quentin Schulz + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Allwinner R16 EVB (Parrot)"; + compatible = "allwinner,parrot", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + label = "parrot:led1:usr"; + gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + }; + + led-2 { + label = "parrot:led2:usr"; + gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ + }; + +}; + +&codec { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + /* + * FIXME: An as-yet-unknown accelerometer is connected to this + * i2c bus. + */ +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-190 { + label = "V+"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button-390 { + label = "V-"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + drive-strength = <40>; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + /* + * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. + * Remove next line once it is possible to sync two regulators. + */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi0"; +}; + +®_dldo2 { + /* + * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. + * Remove next line once it is possible to sync two regulators. + */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_dldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_eldo2 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-dsp"; +}; + +®_eldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "eldo3"; +}; + +®_usb1_vbus { + gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + status = "okay"; + usb0_vbus-supply = <®_drivevbus>; + usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_usb1_vbus>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts new file mode 100644 index 000000000000..28197bbcb1d5 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +#include + +/ { + model = "Banana Pi BPI-M2-Ultra"; + compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led-green { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + + user-led-blue { + label = "bananapi:blue:user"; + gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dc1sw>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&ir0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +/* + * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same + * time, with the two being in sync, to be able to meet maximum power + * consumption during transmits. Since this is not really supported + * right now, just use the two as always on, and we will fix it later. + */ + +®_dldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +}; + +®_dldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ccu CLK_OUTA>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + /* TODO host wake line connected to PMIC GPIO pins */ + shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + max-speed = <1500000>; + }; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi new file mode 100644 index 000000000000..649928b361af --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi @@ -0,0 +1,52 @@ +/{ + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1000000 1000000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1160000 1160000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1240000 1240000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <2000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi new file mode 100644 index 000000000000..9f39b5a2bb35 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai +// Copyright (C) 2017 Icenowy Zheng + +#include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_aldo2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_dcdc1>; + vcc-pc-supply = <®_aldo2>; + vcc-pd-supply = <®_dcdc1>; + vcc-pf-supply = <®_dldo4>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts new file mode 100644 index 000000000000..0bd1336206b8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai +// Copyright (C) 2017 Icenowy Zheng + +/dts-v1/; +#include "sun8i-r40-feta40i.dtsi" + +#include +#include + +/ { + model = "Forlinx OKA40i-C"; + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; /* RS485 */ + serial7 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5 { /* this is how the leds are labeled on the board */ + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + + led-6 { + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo2>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dcdc1>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-lcd"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +&uart5 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart5_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi new file mode 100644 index 000000000000..4ef26d8f5340 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi @@ -0,0 +1,1326 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * Copyright 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-accuracy = <50000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-accuracy = <20000>; + clock-output-names = "ext-osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; + }; + }; + + de: display-engine { + compatible = "allwinner,sun8i-r40-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-r40-de2-clk", + "allwinner,sun8i-h3-de2-clk"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-r40-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + mixer0_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-r40-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + mixer1_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + deinterlace: deinterlace@1400000 { + compatible = "allwinner,sun8i-r40-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01400000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + /* + * NOTE: Contrary to what datasheet claims, + * DRAM deinterlace gate doesn't exist and + * it's shared with CSI1. + */ + <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = ; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-r40-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-r40-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + + nmi_intc: interrupt-controller@1c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = ; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-r40-dma", + "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <16>; + dma-requests = <31>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csi0: csi@1c09000 { + compatible = "allwinner,sun8i-r40-csi0", + "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; + resets = <&ccu RST_BUS_CSI0>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun8i-r40-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-r40-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + pinctrl-0 = <&mmc3_pins>; + pinctrl-names = "default"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-r40-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + + spi2: spi@1c17000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c17000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; + resets = <&ccu RST_BUS_SATA>; + reset-names = "ahci"; + status = "disabled"; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI2>; + resets = <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + spi3: spi@1c1f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-r40-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@1c20400 { + compatible = "allwinner,sun8i-r40-rtc"; + reg = <0x01c20400 0x400>; + interrupts = ; + clock-output-names = "osc32k", "osc32k-out"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-r40-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + can_ph_pins: can-ph-pins { + pins = "PH20", "PH21"; + function = "can"; + }; + + can_pa_pins: can-pa-pins { + pins = "PA16", "PA17"; + function = "can"; + }; + + clk_out_a_pin: clk-out-a-pin { + pins = "PI12"; + function = "clk_out_a"; + }; + + /omit-if-no-ref/ + csi0_8bits_pins: csi0-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE1"; + function = "csi0"; + }; + + gmac_rgmii_pins: gmac-rgmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA10", "PA11", "PA12", + "PA13", "PA15", "PA16"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; + }; + + i2c3_pins: i2c3-pins { + pins = "PI0", "PI1"; + function = "i2c3"; + }; + + i2c4_pins: i2c4-pins { + pins = "PI2", "PI3"; + function = "i2c4"; + }; + + ir0_pins: ir0-pins { + pins = "PB4"; + function = "ir0"; + }; + + ir1_pins: ir1-pins { + pins = "PB23"; + function = "ir1"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pg_pins: mmc1-pg-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC5", "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC24"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc3_pins: mmc3-pins { + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins = "PC23"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pi_pins: spi1-pi-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pi_pin: spi1-cs0-pi-pin { + pins = "PI16"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs1_pi_pin: spi1-cs1-pi-pin { + pins = "PI15"; + function = "spi1"; + }; + + /omit-if-no-ref/ + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI18", "PI19"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ + pins = "PI16", "PI17"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart3_pg_pins: uart3-pg-pins { + pins = "PG6", "PG7"; + function = "uart3"; + }; + + /omit-if-no-ref/ + uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { + pins = "PG8", "PG9"; + function = "uart3"; + }; + + /omit-if-no-ref/ + uart4_pg_pins: uart4-pg-pins { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart7_pi_pins: uart7-pi-pins { + pins = "PI20", "PI21"; + function = "uart7"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = , + , + , + , + , + ; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + interrupts = ; + clocks = <&osc24M>; + }; + + ir0: ir@1c21800 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21800 0x400>; + pinctrl-0 = <&ir0_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = ; + resets = <&ccu RST_BUS_IR0>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21c00 0x400>; + pinctrl-0 = <&ir1_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = ; + resets = <&ccu RST_BUS_IR1>; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-r40-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S0>; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-r40-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S1>; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + }; + + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-r40-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + }; + + ths: thermal-sensor@1c24c00 { + compatible = "allwinner,sun8i-r40-ths"; + reg = <0x01c24c00 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + /* TODO: add nvmem-cells for calibration */ + #thermal-sensor-cells = <1>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + can0: can@1c2bc00 { + compatible = "allwinner,sun8i-r40-can"; + reg = <0x01c2bc00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CAN>; + resets = <&ccu RST_BUS_CAN>; + status = "disabled"; + }; + + i2c4: i2c@1c2c000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + }; + + gmac: ethernet@1c50000 { + compatible = "allwinner,sun8i-r40-gmac"; + syscon = <&ccu>; + reg = <0x01c50000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_GMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_GMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + + gmac_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun8i-r40-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 155>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0x80000000>; + #interconnect-cells = <1>; + }; + + tcon_top: tcon-top@1c70000 { + compatible = "allwinner,sun8i-r40-tcon-top"; + reg = <0x01c70000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>, + <&ccu CLK_TVE0>, + <&ccu CLK_TCON_TV1>, + <&ccu CLK_TVE1>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "tcon-tv1", + "tve1", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-tv1", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon_top>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top>; + }; + }; + + tcon_top_mixer1_out: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv0_out_tcon_top>; + }; + + tcon_top_hdmi_in_tcon_tv1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_tv1_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@1c73000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c73000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv0_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + tcon_tv1: lcd-controller@1c74000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c74000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV1>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_tv1_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; + }; + + tcon_tv1_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; + }; + }; + + tcon_tv1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv1_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; + }; + }; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-r40-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; + clock-names = "iahb", "isfr", "tmds", "cec"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-r40-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; + clock-names = "bus", "mod", "pll-0", "pll-1"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi new file mode 100644 index 000000000000..872d56caa9ce --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi @@ -0,0 +1,224 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "sunxi-reference-design-tablet.dtsi" + +#include + +/ { + aliases { + serial0 = &r_uart; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + power-supply = <®_dc1sw>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * The gsl1680 is the only device on this bus. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen@40 { + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ + power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + eldoin-supply = <®_dcdc1>; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi new file mode 100644 index 000000000000..052b010a5607 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Matteo Scordino + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Elimo Impetus SoM"; + compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts new file mode 100644 index 000000000000..039677c2cc65 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Matteo Scordino + */ + +/dts-v1/; +#include "sun8i-s3-elimo-impetus.dtsi" + +/ { + model = "Elimo Initium"; + compatible = "elimo,initium", "elimo,impetus", "sochip,s3", + "allwinner,sun8i-v3"; + + aliases { + serial1 = &uart1; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts new file mode 100644 index 000000000000..d18192d51d1b --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" + +#include + +/ { + model = "Sipeed Lichee Zero Plus"; + compatible = "sipeed,lichee-zero-plus", "sochip,s3", + "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts new file mode 100644 index 000000000000..20966e954eda --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2019 Icenowy Zheng + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include +#include + +/ { + model = "PineCube IP Camera"; + compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "pine64:ir:led1"; + gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; + + led2 { + label = "pine64:ir:led2"; + gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_wifi: vcc-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ + vin-supply = <®_dcdc3>; + startup-delay-us = <200000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ + post-power-on-delay-ms = <200>; + }; +}; + +&csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_8bit_pins>; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pe_pins>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi1_mclk_pin>; + clocks = <&ccu CLK_CSI1_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_ldo3>; + DOVDD-supply = <®_ldo3>; + DVDD-supply = <®_ldo4>; + reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ + powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Setup"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc_wifi>; + vqmmc-supply = <®_dcdc3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_dcdc3>; + vcc-pe-supply = <®_ldo3>; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-sys-cpu-ephy"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-dovdd-2v8-csi"; + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +®_ldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts new file mode 100644 index 000000000000..94e24b5926dd --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#include + +/dts-v1/; + +#include "sun8i-t113s.dtsi" +#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" + +/ { + model = "MangoPi MQ-R-T113"; + compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; + + aliases { + ethernet0 = &rtl8189ftv; + }; +}; + +&cpu0 { + cpu-supply = <®_vcc_core>; +}; + +&cpu1 { + cpu-supply = <®_vcc_core>; +}; + +&mmc1 { + rtl8189ftv: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi new file mode 100644 index 000000000000..804aa197a24f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts new file mode 100644 index 000000000000..9f472521f4a4 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2017 Chen-Yu Tsai + * Copyright (C) 2017 Icenowy Zheng + * Copyright (C) 2018 Hao Zhang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +#include + +/ { + model = "t3-cqa3t-bv3"; + compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3", + "allwinner,sun8i-r40"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pg"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-dldo3"; +}; + +®_eldo3 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts new file mode 100644 index 000000000000..117aeece4e55 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2020 Paul Kocialkowski + */ + +#include "sun8i-v3-sl631.dtsi" + +/ { + model = "SL631 Action Camera with IMX179"; + compatible = "allwinner,sl631-imx179", "allwinner,sl631", + "allwinner,sun8i-v3"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi new file mode 100644 index 000000000000..6f93f8c49f84 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2020 Paul Kocialkowski + */ + +/dts-v1/; + +#include "sun8i-v3.dtsi" + +#include +#include + +/ { + model = "SL631 Action Camera"; + compatible = "allwinner,sl631", "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pb_pins>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-174 { + label = "Down"; + linux,code = ; + channel = <0>; + voltage = <174603>; + }; + + button-384 { + label = "Up"; + linux,code = ; + channel = <0>; + voltage = <384126>; + }; + + button-593 { + label = "OK"; + linux,code = ; + channel = <0>; + voltage = <593650>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + vmmc-supply = <®_dcdc3>; + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_dcdc3>; + vcc-pe-supply = <®_dcdc3>; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-sys-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vdd-3v3"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3.dtsi new file mode 100644 index 000000000000..186c30cbe6ee --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng + * Copyright (C) 2021 Tobias Schramm + */ + +#include "sun8i-v3s.dtsi" + +/ { + soc { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins>; + resets = <&ccu RST_BUS_I2S0>; + status = "disabled"; + }; + }; +}; + +&ccu { + compatible = "allwinner,sun8i-v3-ccu"; +}; + +&codec_analog { + compatible = "allwinner,sun8i-v3-codec-analog", + "allwinner,sun8i-h3-codec-analog"; +}; + +&emac { + /delete-property/ phy-handle; + /delete-property/ phy-mode; +}; + +&mdio_mux { + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&pio { + compatible = "allwinner,sun8i-v3-pinctrl"; + + i2s0_pins: i2s0-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s"; + }; + + uart1_pg_pins: uart1-pg-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts new file mode 100644 index 000000000000..752ad05c8f83 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-v3s-licheepi-zero.dts" + +#include + +/ { + model = "Lichee Pi Zero with Dock"; + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", + "allwinner,sun8i-v3s"; + + aliases { + ethernet0 = &emac; + }; + + leds { + /* The LEDs use PG0~2 pins, which conflict with MMC1 */ + status = "disabled"; + }; +}; + +&emac { + allwinner,leds-active-low; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; + + button-600 { + label = "Select"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button-800 { + label = "Start"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; +}; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts new file mode 100644 index 000000000000..2e4587d26ce5 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Lichee Pi Zero"; + compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + blue_led { + label = "licheepi:blue:usr"; + gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ + }; + + green_led { + label = "licheepi:green:usr"; + gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + default-state = "on"; + }; + + red_led { + label = "licheepi:red:usr"; + gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ + }; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi new file mode 100644 index 000000000000..3b9a282c2746 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -0,0 +1,621 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * Copyright (C) 2021 Tobias Schramm + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPU>; + }; + }; + + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-accuracy = <50000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-accuracy = <50000>; + clock-output-names = "ext-osc32k"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-v3s-de2-clk"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks 0>, + <&display_clocks 6>; + clock-names = "bus", + "mod"; + resets = <&display_clocks 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-v3s-system-control", + "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0xd0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-v3s-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = ; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-v3s-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-data-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + crypto@1c15000 { + compatible = "allwinner,sun8i-v3s-crypto", + "allwinner,sun8i-a33-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "ahb", "mod"; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_CE>; + reset-names = "ahb"; + }; + + usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-h3-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + compatible = "allwinner,sun8i-v3s-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu0"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-v3s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@1c20400 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-v3-rtc"; + reg = <0x01c20400 0x54>; + interrupts = , + ; + clocks = <&osc32k>; + clock-output-names = "osc32k", "osc32k-out"; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-v3s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE20"; + function = "csi_mipi"; + }; + + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + + i2c0_pins: i2c0-pins { + pins = "PB6", "PB7"; + function = "i2c0"; + }; + + /omit-if-no-ref/ + i2c1_pb_pins: i2c1-pb-pins { + pins = "PB8", "PB9"; + function = "i2c1"; + }; + + /omit-if-no-ref/ + i2c1_pe_pins: i2c1-pe-pins { + pins = "PE21", "PE22"; + function = "i2c1"; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB8", "PB9"; + function = "uart0"; + }; + + uart2_pins: uart2-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + spi0_pins: spi0-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun8i-v3s-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + , + ; + clocks = <&osc24M>; + }; + + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-v3s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x400>; + interrupts = ; + status = "disabled"; + }; + + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3s-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + + codec_analog: codec-analog@1c23000 { + compatible = "allwinner,sun8i-v3s-codec-analog"; + reg = <0x01c23000 0x4>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "tx", "rx"; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "tx", "rx"; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "tx", "rx"; + resets = <&ccu RST_BUS_UART2>; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-v3s-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio_mux: mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + }; + + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + csi1: camera@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x3000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts new file mode 100644 index 000000000000..434871040aca --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +#include + +/ { + model = "Banana Pi M2 Berry"; + compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dc1sw>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +/* + * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same + * time, with the two being in sync, to be able to meet maximum power + * consumption during transmits. Since this is not really supported + * right now, just use the two as always on, and we will fix it later. + */ + +®_dldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +}; + +®_dldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ccu CLK_OUTA>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + /* TODO host wake line connected to PMIC GPIO pins */ + shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + max-speed = <1500000>; + }; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts new file mode 100644 index 000000000000..c8ca8cb7f5c9 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts @@ -0,0 +1,508 @@ +/* + * Copyright 2015 Tyler Baker + * + * Tyler Baker + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun9i-a80.dtsi" + +#include + +/ { + model = "Cubietech Cubieboard4"; + compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "cubieboard4:green:usr"; + gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ + }; + + led-1 { + label = "cubieboard4:red:usr"; + gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + }; + }; + + vga-connector { + compatible = "vga-connector"; + label = "vga"; + ddc-i2c-bus = <&i2c3>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_dac_out>; + }; + }; + }; + + vga-dac { + compatible = "corpro,gm7123", "adi,adv7123"; + vdd-supply = <®_dcdc1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_dac_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_dac_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; +}; + +&de { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_cldo1>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_cldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc1_pins { + bias-pull-up; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; +}; + +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dc1sw>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_ir { + status = "okay"; +}; + +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + +&r_rsb { + status = "okay"; + + axp809: pmic@3a3 { + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_aldo1: aldo1 { + /* + * TODO: This should be handled by the + * USB PHY driver. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc33-usbh"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pb-io-cam"; + }; + + aldo3 { + /* unused */ + }; + + reg_dc1sw: dc1sw { + regulator-name = "vcc-pd"; + }; + + reg_dc5ldo: dc5ldo { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus-09-usbh"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; + }; + + reg_dcdc2: dcdc2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys-usb0-hdmi"; + }; + + reg_dcdc5: dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1425000>; + regulator-max-microvolt = <1575000>; + regulator-name = "vcc-dram"; + }; + + reg_dldo1: dldo1 { + /* + * The WiFi chip supports a wide range + * (3.0 ~ 4.8V) of voltages, and so does + * this regulator (3.0 ~ 4.2V), but + * Allwinner SDK always sets it to 3.3V. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_dldo2: dldo2 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pl"; + }; + + reg_eldo1: eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dvdd-cam"; + }; + + reg_eldo2: eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; + }; + + reg_eldo3: eldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pm-codec-io1"; + }; + + reg_ldo_io0: ldo_io0 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pg"; + }; + + reg_ldo_io1: ldo_io1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa-gmac-2v5"; + }; + + reg_rtc_ldo: rtc_ldo { + regulator-name = "vcc-rtc-vdd1v8-io"; + }; + + sw { + /* unused */ + }; + }; + }; + + axp806: pmic@745 { + compatible = "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + bldoin-supply = <®_dcdce>; + + regulators { + reg_s_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + aldo2 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo2"; + }; + + aldo3 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo3"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = "vcc18-efuse-adc-display-csi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = + "vdd18-drampll-vcc18-pll-cpvdd"; + }; + + bldo3 { + /* unused */ + }; + + reg_bldo4: bldo4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vcc12-hsic"; + }; + + reg_cldo1: cldo1 { + /* + * This was 3V in the original design, but + * 3.3V is the recommended supply voltage + * for the Ethernet PHY. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-name = "vcc-gmac-phy"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-cam"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io-wifi-codec-io2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-vpu"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-name = "vcc-bldo-codec-ldoin"; + }; + + sw { + /* + * unused, but use a different name to + * avoid name clash with axp809's sw + */ + regulator-name = "s_sw"; + }; + }; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp809.dtsi" + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; +}; + +&tcon0_out { + tcon0_out_vga: endpoint { + remote-endpoint = <&vga_dac_in>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts b/arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts new file mode 100644 index 000000000000..5c3580d712e4 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts @@ -0,0 +1,510 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun9i-a80.dtsi" + +#include + +/ { + model = "Merrii A80 Optimus Board"; + compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; + + aliases { + serial0 = &uart0; + serial1 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + /* The LED names match those found on the board */ + led2 { + label = "optimus:led2:usr"; + gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; + }; + + led3 { + label = "optimus:led3:usr"; + gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ + }; + + led4 { + label = "optimus:led4:usr"; + gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + /* Enable if HSIC peripheral is connected */ + status = "disabled"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_cldo1>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_cldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc1_pins { + bias-pull-up; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_ir { + status = "okay"; +}; + +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + +&r_rsb { + status = "okay"; + + axp809: pmic@3a3 { + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_aldo1: aldo1 { + /* + * TODO: This should be handled by the + * USB PHY driver. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc33-usbh"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pb-io-cam"; + }; + + aldo3 { + /* unused */ + }; + + reg_dc5ldo: dc5ldo { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus-09-usbh"; + }; + + dc1sw { + /* unused */ + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; + }; + + reg_dcdc2: dcdc2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys-usb0-hdmi"; + }; + + reg_dcdc5: dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1425000>; + regulator-max-microvolt = <1575000>; + regulator-name = "vcc-dram"; + }; + + reg_dldo1: dldo1 { + /* + * The WiFi chip supports a wide range + * (3.0 ~ 4.8V) of voltages, and so does + * this regulator (3.0 ~ 4.2V), but + * Allwinner SDK always sets it to 3.3V. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_dldo2: dldo2 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pl"; + }; + + reg_eldo1: eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dvdd-cam"; + }; + + reg_eldo2: eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; + }; + + reg_eldo3: eldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pm-codec-io1"; + }; + + reg_ldo_io0: ldo_io0 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pg"; + }; + + reg_ldo_io1: ldo_io1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa-gmac-2v5"; + }; + + reg_rtc_ldo: rtc_ldo { + regulator-name = "vcc-rtc-vdd1v8-io"; + }; + + sw { + /* unused */ + }; + }; + }; + + axp806: pmic@745 { + compatible = "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + bldoin-supply = <®_dcdce>; + + regulators { + reg_s_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + aldo2 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo2"; + }; + + aldo3 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo3"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = "vcc18-efuse-adc-display-csi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = + "vdd18-drampll-vcc18-pll-cpvdd"; + }; + + bldo3 { + /* unused */ + }; + + reg_bldo4: bldo4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vcc12-hsic"; + }; + + reg_cldo1: cldo1 { + /* + * This was 3V in the original design, but + * 3.3V is the recommended supply voltage + * for the Ethernet PHY. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-name = "vcc-gmac-phy"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-cam"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io-wifi-codec-io2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-vpu"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-name = "vcc-bldo-codec-ldoin"; + }; + + sw { + /* + * unused, but use a different name to + * avoid name clash with axp809's sw + */ + regulator-name = "s_sw"; + }; + }; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp809.dtsi" + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbphy1 { + phy-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbphy2 { + phy-supply = <®_bldo4>; + /* Enable if HSIC peripheral is connected */ + status = "disabled"; +}; + +&usbphy3 { + phy-supply = <®_usb3_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi new file mode 100644 index 000000000000..7d3f3300f431 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi @@ -0,0 +1,1253 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + ethernet0 = &gmac; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x3>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; + reg = <0x103>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + /* + * map 64 bit address range down to 32 bits, + * as the peripherals are all under 512MB. + */ + ranges = <0 0 0 0x20000000>; + + /* + * This clock is actually configurable from the PRCM address + * space. The external 24M oscillator can be turned off, and + * the clock switched to an internal 16M RC oscillator. Under + * normal operation there's no reason to do this, and the + * default is to use the external good one, so just model this + * as a fixed clock. Also it is not entirely clear if the + * osc24M mux in the PRCM affects the entire clock tree, which + * would also throw all the PLL clock rates off, or just the + * downstream clocks in the PRCM. + */ + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + /* + * The 32k clock is from an external source, normally the + * AC100 codec/RTC chip. This serves as a placeholder for + * board dts files to specify the source. + */ + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "osc32k"; + }; + + /* + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. + */ + mii_phy_tx_clk: mii_phy_tx_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: gmac_int_tx_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@800030 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x00800030 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + + cpus_clk: clk@8001410 { + compatible = "allwinner,sun9i-a80-cpus-clk"; + reg = <0x08001410 0x4>; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, + <&ccu CLK_PLL_PERIPH0>, + <&ccu CLK_PLL_AUDIO>; + clock-output-names = "cpus"; + }; + + ahbs: clk-ahbs { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&cpus_clk>; + clock-output-names = "ahbs"; + }; + + apbs: clk@800141c { + compatible = "allwinner,sun8i-a23-apb0-clk"; + reg = <0x0800141c 0x4>; + #clock-cells = <0>; + clocks = <&ahbs>; + clock-output-names = "apbs"; + }; + + apbs_gates: clk@8001428 { + compatible = "allwinner,sun9i-a80-apbs-gates-clk"; + reg = <0x08001428 0x4>; + #clock-cells = <1>; + clocks = <&apbs>; + clock-indices = <0>, <1>, + <2>, <3>, + <4>, <5>, + <6>, <7>, + <12>, <13>, + <16>, <17>, + <18>, <20>; + clock-output-names = "apbs_pio", "apbs_ir", + "apbs_timer", "apbs_rsb", + "apbs_uart", "apbs_1wire", + "apbs_i2c0", "apbs_i2c1", + "apbs_ps2_0", "apbs_ps2_1", + "apbs_dma", "apbs_i2s0", + "apbs_i2s1", "apbs_twd"; + }; + + r_1wire_clk: clk@8001450 { + reg = <0x08001450 0x4>; + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_1wire"; + }; + + r_ir_clk: clk@8001454 { + reg = <0x08001454 0x4>; + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_ir"; + }; + }; + + de: display-engine { + compatible = "allwinner,sun9i-a80-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; + }; + + soc@20000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* + * map 64 bit address range down to 32 bits, + * as the peripherals are all under 512MB. + */ + ranges = <0 0 0 0x20000000>; + + sram_b: sram@20000 { + /* 256 KiB secure SRAM at 0x20000 */ + compatible = "mmio-sram"; + reg = <0x00020000 0x40000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00020000 0x40000>; + + smp-sram@1000 { + /* + * This is checked by BROM to determine if + * cpu0 should jump to SMP entry vector + */ + compatible = "allwinner,sun9i-a80-smp-sram"; + reg = <0x1000 0x8>; + }; + }; + + gmac: ethernet@830000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x00830000 0x1054>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + resets = <&ccu RST_BUS_GMAC>; + reset-names = "stmmaceth"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ehci0: usb@a00000 { + compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; + reg = <0x00a00000 0x100>; + interrupts = ; + clocks = <&usb_clocks CLK_BUS_HCI0>; + resets = <&usb_clocks RST_USB0_HCI>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@a00400 { + compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; + reg = <0x00a00400 0x100>; + interrupts = ; + clocks = <&usb_clocks CLK_BUS_HCI0>, + <&usb_clocks CLK_USB_OHCI0>; + resets = <&usb_clocks RST_USB0_HCI>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy1: phy@a00800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a00800 0x4>; + clocks = <&usb_clocks CLK_USB0_PHY>; + clock-names = "phy"; + resets = <&usb_clocks RST_USB0_PHY>; + reset-names = "phy"; + status = "disabled"; + #phy-cells = <0>; + }; + + ehci1: usb@a01000 { + compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; + reg = <0x00a01000 0x100>; + interrupts = ; + clocks = <&usb_clocks CLK_BUS_HCI1>; + resets = <&usb_clocks RST_USB1_HCI>; + phys = <&usbphy2>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy2: phy@a01800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a01800 0x4>; + clocks = <&usb_clocks CLK_USB1_PHY>, + <&usb_clocks CLK_USB_HSIC>, + <&usb_clocks CLK_USB1_HSIC>; + clock-names = "phy", + "hsic_12M", + "hsic_480M"; + resets = <&usb_clocks RST_USB1_PHY>, + <&usb_clocks RST_USB1_HSIC>; + reset-names = "phy", + "hsic"; + status = "disabled"; + #phy-cells = <0>; + /* usb1 is always used with HSIC */ + phy_type = "hsic"; + }; + + ehci2: usb@a02000 { + compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; + reg = <0x00a02000 0x100>; + interrupts = ; + clocks = <&usb_clocks CLK_BUS_HCI2>; + resets = <&usb_clocks RST_USB2_HCI>; + phys = <&usbphy3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@a02400 { + compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; + reg = <0x00a02400 0x100>; + interrupts = ; + clocks = <&usb_clocks CLK_BUS_HCI2>, + <&usb_clocks CLK_USB_OHCI2>; + resets = <&usb_clocks RST_USB2_HCI>; + phys = <&usbphy3>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy3: phy@a02800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a02800 0x4>; + clocks = <&usb_clocks CLK_USB2_PHY>, + <&usb_clocks CLK_USB_HSIC>, + <&usb_clocks CLK_USB2_HSIC>; + clock-names = "phy", + "hsic_12M", + "hsic_480M"; + resets = <&usb_clocks RST_USB2_PHY>, + <&usb_clocks RST_USB2_HSIC>; + reset-names = "phy", + "hsic"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb_clocks: clock@a08000 { + compatible = "allwinner,sun9i-a80-usb-clks"; + reg = <0x00a08000 0x8>; + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; + clock-names = "bus", "hosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cpucfg@1700000 { + compatible = "allwinner,sun9i-a80-cpucfg"; + reg = <0x01700000 0x100>; + }; + + crypto: crypto@1c02000 { + compatible = "allwinner,sun9i-a80-crypto"; + reg = <0x01c02000 0x1000>; + interrupts = ; + resets = <&ccu RST_BUS_SS>; + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; + clock-names = "bus", "mod"; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun9i-a80-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun9i-a80-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun9i-a80-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun9i-a80-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 3>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc_config_clk: clk@1c13000 { + compatible = "allwinner,sun9i-a80-mmc-config-clk"; + reg = <0x01c13000 0x10>; + clocks = <&ccu CLK_BUS_MMC>; + resets = <&ccu RST_BUS_MMC>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-output-names = "mmc0_config", "mmc1_config", + "mmc2_config", "mmc3_config"; + }; + + gic: interrupt-controller@1c41000 { + compatible = "arm,gic-400"; + reg = <0x01c41000 0x1000>, + <0x01c42000 0x2000>, + <0x01c44000 0x2000>, + <0x01c46000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + cci: cci@1c90000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01c90000 0x1000>; + ranges = <0x0 0x01c90000 0x10000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + ; + }; + }; + + de_clocks: clock@3000000 { + compatible = "allwinner,sun9i-a80-de-clks"; + reg = <0x03000000 0x30>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_SDRAM>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "dram", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + fe0: display-frontend@3100000 { + compatible = "allwinner,sun9i-a80-display-frontend"; + reg = <0x03100000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, + <&de_clocks CLK_DRAM_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + reg = <1>; + + fe0_out_deu0: endpoint { + remote-endpoint = <&deu0_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@3140000 { + compatible = "allwinner,sun9i-a80-display-frontend"; + reg = <0x03140000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, + <&de_clocks CLK_DRAM_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + reg = <1>; + + fe1_out_deu1: endpoint { + remote-endpoint = <&deu1_in_fe1>; + }; + }; + }; + }; + + be0: display-backend@3200000 { + compatible = "allwinner,sun9i-a80-display-backend"; + reg = <0x03200000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, + <&de_clocks CLK_DRAM_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_deu0: endpoint@0 { + reg = <0>; + remote-endpoint = <&deu0_out_be0>; + }; + + be0_in_deu1: endpoint@1 { + reg = <1>; + remote-endpoint = <&deu1_out_be0>; + }; + }; + + be0_out: port@1 { + reg = <1>; + + be0_out_drc0: endpoint { + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + be1: display-backend@3240000 { + compatible = "allwinner,sun9i-a80-display-backend"; + reg = <0x03240000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, + <&de_clocks CLK_DRAM_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_deu0: endpoint@0 { + reg = <0>; + remote-endpoint = <&deu0_out_be1>; + }; + + be1_in_deu1: endpoint@1 { + reg = <1>; + remote-endpoint = <&deu1_out_be1>; + }; + }; + + be1_out: port@1 { + reg = <1>; + + be1_out_drc1: endpoint { + remote-endpoint = <&drc1_in_be1>; + }; + }; + }; + }; + + deu0: deu@3300000 { + compatible = "allwinner,sun9i-a80-deu"; + reg = <0x03300000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DEU0>, + <&de_clocks CLK_IEP_DEU0>, + <&de_clocks CLK_DRAM_DEU0>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DEU0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + deu0_in: port@0 { + reg = <0>; + + deu0_in_fe0: endpoint { + remote-endpoint = <&fe0_out_deu0>; + }; + }; + + deu0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deu0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_deu0>; + }; + + deu0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_deu0>; + }; + }; + }; + }; + + deu1: deu@3340000 { + compatible = "allwinner,sun9i-a80-deu"; + reg = <0x03340000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DEU1>, + <&de_clocks CLK_IEP_DEU1>, + <&de_clocks CLK_DRAM_DEU1>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DEU1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + deu1_in: port@0 { + reg = <0>; + + deu1_in_fe1: endpoint { + remote-endpoint = <&fe1_out_deu1>; + }; + }; + + deu1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deu1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_deu1>; + }; + + deu1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_deu1>; + }; + }; + }; + }; + + drc0: drc@3400000 { + compatible = "allwinner,sun9i-a80-drc"; + reg = <0x03400000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DRC0>, + <&de_clocks CLK_IEP_DRC0>, + <&de_clocks CLK_DRAM_DRC0>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DRC0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + reg = <0>; + + drc0_in_be0: endpoint { + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + reg = <1>; + + drc0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + + drc1: drc@3440000 { + compatible = "allwinner,sun9i-a80-drc"; + reg = <0x03440000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DRC1>, + <&de_clocks CLK_IEP_DRC1>, + <&de_clocks CLK_DRAM_DRC1>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DRC1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc1_in: port@0 { + reg = <0>; + + drc1_in_be1: endpoint { + remote-endpoint = <&be1_out_drc1>; + }; + }; + + drc1_out: port@1 { + reg = <1>; + + drc1_out_tcon1: endpoint { + remote-endpoint = <&tcon1_in_drc1>; + }; + }; + }; + }; + + tcon0: lcd-controller@3c00000 { + compatible = "allwinner,sun9i-a80-tcon-lcd"; + reg = <0x03c00000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; + clock-names = "ahb", "tcon-ch0"; + resets = <&ccu RST_BUS_LCD0>, + <&ccu RST_BUS_EDP>, + <&ccu RST_BUS_LVDS>; + reset-names = "lcd", + "edp", + "lvds"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_drc0: endpoint { + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + reg = <1>; + }; + }; + }; + + tcon1: lcd-controller@3c10000 { + compatible = "allwinner,sun9i-a80-tcon-tv"; + reg = <0x03c10000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; + reset-names = "lcd", "edp"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + reg = <0>; + + tcon1_in_drc1: endpoint { + remote-endpoint = <&drc1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + reg = <1>; + }; + }; + }; + + ccu: clock@6000000 { + compatible = "allwinner,sun9i-a80-ccu"; + reg = <0x06000000 0x800>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + timer@6000c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x06000c00 0xa0>; + interrupts = , + , + , + , + , + ; + + clocks = <&osc24M>; + }; + + wdt: watchdog@6000ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x06000ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + pio: pinctrl@6000800 { + compatible = "allwinner,sun9i-a80-pinctrl"; + reg = <0x06000800 0x400>; + interrupts = , + , + , + , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + gmac_rgmii_pins: gmac-rgmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", + "PA7", "PA8", "PA9", "PA10", "PA12", + "PA13", "PA15", "PA16", "PA17"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + i2c3_pins: i2c3-pins { + pins = "PG10", "PG11"; + function = "i2c3"; + }; + + lcd0_rgb888_pins: lcd0-rgb888-pins { + pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1" ,"PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1" ,"PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_pins: mmc2-8bit-pins { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_ph_pins: uart0-ph-pins { + pins = "PH12", "PH13"; + function = "uart0"; + }; + + uart4_pins: uart4-pins { + pins = "PG12", "PG13", "PG14", "PG15"; + function = "uart4"; + }; + }; + + uart0: serial@7000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@7000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@7000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@7000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@7001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07001000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@7001400 { + compatible = "snps,dw-apb-uart"; + reg = <0x07001400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + i2c0: i2c@7002800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07002800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@7002c00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07002c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@7003000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07003000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@7003400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07003400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@7003800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07003800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_wdt: watchdog@8001000 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x08001000 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + prcm@8001400 { + compatible = "allwinner,sun9i-a80-prcm"; + reg = <0x08001400 0x200>; + }; + + apbs_rst: reset@80014b0 { + reg = <0x080014b0 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + + nmi_intc: interrupt-controller@80015a0 { + compatible = "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x080015a0 0xc>; + interrupts = ; + }; + + r_ir: ir@8002000 { + compatible = "allwinner,sun6i-a31-ir"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_pins>; + clocks = <&apbs_gates 1>, <&r_ir_clk>; + clock-names = "apb", "ir"; + resets = <&apbs_rst 1>; + reg = <0x08002000 0x40>; + status = "disabled"; + }; + + r_uart: serial@8002800 { + compatible = "snps,dw-apb-uart"; + reg = <0x08002800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apbs_gates 4>; + resets = <&apbs_rst 4>; + status = "disabled"; + }; + + r_pio: pinctrl@8002c00 { + compatible = "allwinner,sun9i-a80-r-pinctrl"; + reg = <0x08002c00 0x400>; + interrupts = , + ; + clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + r_ir_pins: r-ir-pins { + pins = "PL6"; + function = "s_cir_rx"; + }; + + r_rsb_pins: r-rsb-pins { + pins = "PN0", "PN1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + }; + + r_rsb: rsb@8003400 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x08003400 0x400>; + interrupts = ; + clocks = <&apbs_gates 3>; + clock-frequency = <3000000>; + resets = <&apbs_rst 3>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts new file mode 100644 index 000000000000..43896723a994 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include + +/ { + model = "Lichee Pi Nano"; + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; + + aliases { + mmc0 = &mmc0; + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&otg_sram { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pe_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi b/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi new file mode 100644 index 000000000000..3c61d59ab5f8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + * Copyright 2018 Mesih Kilinc + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,suniv-f1c100s-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,suniv-f1c100s-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@1c13000 { + compatible = "allwinner,suniv-f1c100s-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <26>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + + /omit-if-no-ref/ + i2c0_pd_pins: i2c0-pd-pins { + pins = "PD0", "PD12"; + function = "i2c0"; + }; + + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + + uart0_pe_pins: uart0-pe-pins { + pins = "PE0", "PE1"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pa_pins: uart1-pa-pins { + pins = "PA2", "PA3"; + function = "uart1"; + }; + }; + + i2c0: i2c@1c27000 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27000 0x400>; + interrupts = <7>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1c27400 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27400 0x400>; + interrupts = <8>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1c27800 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27800 0x400>; + interrupts = <9>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>, <14>, <15>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,suniv-f1c100s-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <16>; + clocks = <&osc32k>; + }; + + pwm: pwm@1c21000 { + compatible = "allwinner,suniv-f1c100s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21000 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@1c22c00 { + compatible = "allwinner,suniv-f1c100s-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c22c00 0x400>; + clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR>; + interrupts = <6>; + status = "disabled"; + }; + + lradc: lradc@1c23400 { + compatible = "allwinner,suniv-f1c100s-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c23400 0x400>; + interrupts = <22>; + status = "disabled"; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts new file mode 100644 index 000000000000..2d2a3f026df3 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Arm Ltd, + * based on work: + * Copyright 2022 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include + +/ { + model = "Lctech Pi F1C200s"; + compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", + "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pa_pins>; + status = "okay"; +}; + +/* + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected + * to Vin, which supplies the board. Host mode works (if the board is powered + * otherwise), but peripheral is probably the intention. + */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts new file mode 100644 index 000000000000..184c245041a6 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include +#include + +/ { + model = "Popcorn Computer PopStick v1.1"; + compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick", + "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */ + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pe_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi new file mode 100644 index 000000000000..235994a4a2eb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Chen-Yu Tsai + */ + +#include "sunxi-bananapi-m2-plus.dtsi" + +/ { + /* + * Bananapi M2+ v1.2 uses a GPIO line to change the effective + * resistance on the CPU regulator's feedback pin. + */ + reg_vdd_cpux: vdd-cpux { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1108475>; + regulator-max-microvolt = <1308475>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ + gpios-states = <0x1>; + states = <1108475 0>, <1308475 1>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu1 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu2 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu3 { + cpu-supply = <®_vdd_cpux>; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi new file mode 100644 index 000000000000..1d1d127cf38f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + aliases { + ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "bananapi-m2-plus:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-4 { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <1500000>; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + usb0_vbus-supply = <®_usb0_vbus>; + /* USB host VBUS is on as long as VCC-IO is on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi new file mode 100644 index 000000000000..d8e5826fb3de --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi @@ -0,0 +1,111 @@ +/* + * sunxi boards common regulator (ahci target power supply, usb-vbus) code + * + * Copyright 2014 - Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + reg_ahci_5v: ahci-5v { + compatible = "regulator-fixed"; + regulator-name = "ahci-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_usb2_vbus: usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_vcc3v0: vcc3v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi new file mode 100644 index 000000000000..e9bc749488bb --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. +/* + * Common peripherals and configurations for MangoPi MQ-R boards. + */ + +#include +#include + +/ { + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ + }; + }; + + /* board wide 5V supply directly from the USB-C socket */ + reg_vcc5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <®_vcc5v>; + }; + + /* XC6206 LDO on the board */ + reg_avdd2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_3v3>; + vcc-pd-supply = <®_3v3>; + vcc-pe-supply = <®_avdd2v8>; + vcc-pf-supply = <®_3v3>; + vcc-pg-supply = <®_3v3>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pb_pins>; + status = "okay"; +}; + +/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi new file mode 100644 index 000000000000..60804b0e6c56 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTSI for Emlid Neutis SoMs. + * + * Copyright (C) 2019 Georgii Staroselskii + */ + +#include "sunxi-common-regulators.dtsi" + +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ + post-power-on-delay-ms = <200>; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + status = "okay"; +}; + + +&de { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ + device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "Mic", + "MIC2", "Mic", + "Mic", "MBIAS"; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi new file mode 100644 index 000000000000..ade1cd50e445 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi @@ -0,0 +1,979 @@ +/* + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0-hdmi"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; + status = "disabled"; + }; + + framebuffer-tve { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-tve"; + clocks = <&display_clocks CLK_MIXER1>, + <&ccu CLK_TVE>; + status = "disabled"; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-accuracy = <50000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-accuracy = <50000>; + clock-output-names = "ext_osc32k"; + }; + }; + + de: display-engine { + compatible = "allwinner,sun8i-h3-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges; + ranges; + + display_clocks: clock@1000000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-h3-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-h3-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg = <0x01c0f000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg = <0x01c10000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg = <0x01c11000 0x1000>; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + sid: eeprom@1c14000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 4>; + }; + }; + + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-h3-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + + usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-h3-musb"; + reg = <0x01c19000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + dr_mode = "otg"; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@1c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; + resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c1b400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; + resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@1c1d000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1d000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; + resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@1c1d400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1d400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + csi_pins: csi-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi"; + }; + + emac_rgmii_pins: emac-rgmii-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD7", "PD8", "PD9", "PD10", + "PD12", "PD13", "PD15", "PD16", "PD17"; + function = "emac"; + drive-strength = <40>; + }; + + i2c0_pins: i2c0-pins { + pins = "PA11", "PA12"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PA18", "PA19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PE12", "PE13"; + function = "i2c2"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_pins: mmc2-8bit-pins { + pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PA17"; + function = "spdif"; + }; + + spi0_pins: spi0-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + + spi1_pins: spi1-pins { + pins = "PA15", "PA16", "PA14", "PA13"; + function = "spi1"; + }; + + uart0_pa_pins: uart0-pa-pins { + pins = "PA4", "PA5"; + function = "uart0"; + }; + + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + + uart2_pins: uart2-pins { + pins = "PA0", "PA1"; + function = "uart2"; + }; + + uart2_rts_cts_pins: uart2-rts-cts-pins { + pins = "PA2", "PA3"; + function = "uart2"; + }; + + uart3_pins: uart3-pins { + pins = "PA13", "PA14"; + function = "uart3"; + }; + + uart3_rts_cts_pins: uart3-rts-cts-pins { + pins = "PA15", "PA16"; + function = "uart3"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun8i-a23-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + mbus: dram-controller@1c62000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c69000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c69000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-spdif"; + reg = <0x01c21000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_BUS_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>; + dma-names = "tx"; + status = "disabled"; + }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x8>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + csi: camera@1cb0000 { + compatible = "allwinner,sun8i-h3-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-h3-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; + clock-names = "iahb", "isfr", "tmds", "cec"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-h3-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu CLK_PLL_VIDEO>; + clock-names = "bus", "mod", "pll-0"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + + rtc: rtc@1f00000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01f00000 0x400>; + interrupt-parent = <&r_intc>; + interrupts = , + ; + clock-output-names = "osc32k", "osc32k-out", "iosc"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; + + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-h3-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-h3-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + codec_analog: codec-analog@1f015c0 { + compatible = "allwinner,sun8i-h3-codec-analog"; + reg = <0x01f015c0 0x4>; + }; + + ir: ir@1f02000 { + compatible = "allwinner,sun6i-a31-ir"; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; + interrupts = ; + reg = <0x01f02000 0x400>; + status = "disabled"; + }; + + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + clocks = <&r_ccu CLK_APB0_I2C>; + resets = <&r_ccu RST_APB0_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_APB0_UART>; + resets = <&r_ccu RST_APB0_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; + }; + + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun8i-h3-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_ir_rx_pin: r-ir-rx-pin { + pins = "PL11"; + function = "s_cir_rx"; + }; + + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + function = "s_i2c"; + }; + + r_pwm_pin: r-pwm-pin { + pins = "PL10"; + function = "s_pwm"; + }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; + }; + + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01f03800 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi new file mode 100644 index 000000000000..0d002f83a259 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi @@ -0,0 +1,132 @@ +/* + * Copyright 2015 - Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-common-regulators.dtsi" + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi new file mode 100644 index 000000000000..89731bb34c6b --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Chen-Yu Tsai + */ + +#include +#include + +/ { + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "librecomputer:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status_led { + label = "librecomputer:blue:status"; + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + wakeup-source; + }; + }; + + reg_vcc1v2: vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v0>; + }; + + /* This represents the board's 5V input */ + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_dram: vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + enable-active-high; + }; + + reg_vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc-io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc3v3>; + gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + }; + + reg_vdd_cpux: vdd-cpux { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpux"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu1 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu2 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu3 { + cpu-supply = <®_vdd_cpux>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc_io>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc_io>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + /* VBUS on USB ports are always on */ + usb0_vbus-supply = <®_vcc5v0>; + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + usb3_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi new file mode 100644 index 000000000000..50d328c2a84d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2019 Chen-Yu Tsai + +#include +#include + +/ { + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_led { + label = "librecomputer:blue:status"; + gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + }; + + /* This represents the board's 5V input */ + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vcc_dram: vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + enable-active-high; + }; + + reg_vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc-io"; + /* This is simply a MOSFET switch */ + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc3v3>; + gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + }; + + reg_vcc_usbwifi: vcc-usbwifi { + compatible = "regulator-fixed"; + regulator-name = "vcc-usbwifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v0>; + gpio = <&pio 6 4 GPIO_ACTIVE_HIGH>; /* PG4 */ + enable-active-high; + }; + + reg_vdd_cpux: vdd-cpux { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpux"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vcc5v0>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu1 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu2 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu3 { + cpu-supply = <®_vdd_cpux>; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc_io>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&pio { + vcc-pa-supply = <®_vcc_io>; + vcc-pc-supply = <®_vcc_io>; + vcc-pd-supply = <®_vcc_io>; + vcc-pe-supply = <®_vcc_io>; + vcc-pf-supply = <®_vcc_io>; + vcc-pg-supply = <®_vcc_io>; +}; + +&r_pio { + vcc-pl-supply = <®_vcc3v3>; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc_usbwifi>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi new file mode 100644 index 000000000000..117198c52e1f --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "sunxi-common-regulators.dtsi" + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/alphascale-asm9260-devkit.dts b/arch/arm/boot/dts/alphascale-asm9260-devkit.dts deleted file mode 100644 index c77e2c902fb6..000000000000 --- a/arch/arm/boot/dts/alphascale-asm9260-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "alphascale-asm9260.dtsi" - -/ { - model = "Alphascale asm9260 Development Kit"; - compatible = "alphascale,asm9260devkit", "alphascale,asm9260"; -}; diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale-asm9260.dtsi deleted file mode 100644 index 2ce6038536fd..000000000000 --- a/arch/arm/boot/dts/alphascale-asm9260.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&icoll>; - - memory { - device_type = "memory"; - reg = <0x20000000 0x2000000>; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - clocks = <&acc CLKID_SYS_CPU>; - }; - }; - - osc24m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-accuracy = <30000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - acc: clock-controller@80040000 { - compatible = "alphascale,asm9260-clock-controller"; - #clock-cells = <1>; - clocks = <&osc24m>; - reg = <0x80040000 0x204>; - }; - - icoll: interrupt-controller@80054000 { - compatible = "alphascale,asm9260-icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80054000 0x200>; - }; - - timer0: timer@80088000 { - compatible = "alphascale,asm9260-timer"; - reg = <0x80088000 0x4000>; - clocks = <&acc CLKID_AHB_TIMER0>; - interrupts = <29>; - }; - }; -}; diff --git a/arch/arm/boot/dts/alphascale/Makefile b/arch/arm/boot/dts/alphascale/Makefile new file mode 100644 index 000000000000..8d1314fc79d0 --- /dev/null +++ b/arch/arm/boot/dts/alphascale/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_ASM9260) += \ + alphascale-asm9260-devkit.dtb +dtb-$(CONFIG_MACH_ASM9260) += \ + alphascale-asm9260-devkit.dtb diff --git a/arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts b/arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts new file mode 100644 index 000000000000..c77e2c902fb6 --- /dev/null +++ b/arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Oleksij Rempel + * + * Licensed under the X11 license or the GPL v2 (or later) + */ + +/dts-v1/; +#include "alphascale-asm9260.dtsi" + +/ { + model = "Alphascale asm9260 Development Kit"; + compatible = "alphascale,asm9260devkit", "alphascale,asm9260"; +}; diff --git a/arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi new file mode 100644 index 000000000000..2ce6038536fd --- /dev/null +++ b/arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi @@ -0,0 +1,64 @@ +/* + * Copyright 2014 Oleksij Rempel + * + * Licensed under the X11 license or the GPL v2 (or later) + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&icoll>; + + memory { + device_type = "memory"; + reg = <0x20000000 0x2000000>; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + clocks = <&acc CLKID_SYS_CPU>; + }; + }; + + osc24m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-accuracy = <30000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + acc: clock-controller@80040000 { + compatible = "alphascale,asm9260-clock-controller"; + #clock-cells = <1>; + clocks = <&osc24m>; + reg = <0x80040000 0x204>; + }; + + icoll: interrupt-controller@80054000 { + compatible = "alphascale,asm9260-icoll"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x80054000 0x200>; + }; + + timer0: timer@80088000 { + compatible = "alphascale,asm9260-timer"; + reg = <0x80088000 0x4000>; + clocks = <&acc CLKID_AHB_TIMER0>; + interrupts = <29>; + }; + }; +}; diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/alpine-db.dts deleted file mode 100644 index dfb5a0802273..000000000000 --- a/arch/arm/boot/dts/alpine-db.dts +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2015 Annapurna Labs Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * Alternatively, redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/dts-v1/; - -#include "alpine.dtsi" - -/ { - model = "Annapurna Labs Alpine Dev Board"; - /* no need for anything outside SOC */ -}; - diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi deleted file mode 100644 index ff68dfb4eb78..000000000000 --- a/arch/arm/boot/dts/alpine.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2015 Annapurna Labs Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * Alternatively, redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - /* SOC compatibility */ - compatible = "al,alpine"; - - memory { - device_type = "memory"; - reg = <0 0 0 0>; - }; - - /* CPU Configuration */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "al,alpine-smp"; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <1700000000>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <1700000000>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clock-frequency = <1700000000>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clock-frequency = <1700000000>; - }; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - arch-timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = - , - , - , - ; - clock-frequency = <50000000>; - }; - - /* Interrupt Controller */ - gic: interrupt-controller@fb001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xfb001000 0x0 0x1000>, - <0x0 0xfb002000 0x0 0x2000>, - <0x0 0xfb004000 0x0 0x2000>, - <0x0 0xfb006000 0x0 0x2000>; - interrupts = - ; - }; - - /* CPU Resume registers */ - cpu-resume@fbff5ec0 { - compatible = "al,alpine-cpu-resume"; - reg = <0x0 0xfbff5ec0 0x0 0x30>; - }; - - /* North Bridge Service Registers */ - sysfabric-service@fb070000 { - compatible = "al,alpine-sysfabric-service", "syscon"; - reg = <0x0 0xfb070000 0x0 0x10000>; - }; - - /* Performance Monitor Unit */ - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - uart0: serial@fd883000 { - compatible = "ns16550a"; - reg = <0x0 0xfd883000 0x0 0x1000>; - clock-frequency = <375000000>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: serial@fd884000 { - compatible = "ns16550a"; - reg = <0x0 0xfd884000 0x0 0x1000>; - clock-frequency = <375000000>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - /* Internal PCIe Controller */ - pcie@fbc00000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - #interrupt-cells = <1>; - reg = <0x0 0xfbc00000 0x0 0x100000>; - interrupt-map-mask = <0xf800 0 0 7>; - /* Add legacy interrupts for SATA devices only */ - interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, - <0x4800 0 0 1 &gic 0 44 4>; - - /* 32 bit non prefetchable memory space */ - ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; - - bus-range = <0x00 0x00>; - msi-parent = <&msix>; - }; - - msix: msix@fbe00000 { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <96>; - al,msi-num-spis = <64>; - }; - }; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts deleted file mode 100644 index ea5882ed7010..000000000000 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "OnRISC Baltos iR 2110"; -}; - -&am33xx_pinmux { - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&davinci_mdio_sw { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - phy-handle = <&phy1>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -}; - -&gpio0 { - gpio-line-names = - "MDIO", - "MDC", - "NC", - "NC", - "I2C1_SDA", - "I2C1_SCL", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "UART1_CTSN", - "UART1_RTSN", - "UART1_RX", - "UART1_TX", - "onrisc:blue:wlan", - "onrisc:green:app", - "USB0_DRVVBUS", - "ETH2_INT", - "NC", - "RMII1_TXD1", - "MMC1_DAT0", - "MMC1_DAT1", - "NC", - "NC", - "MMC1_DAT2", - "MMC1_DAT3", - "RMII1_TXD0", - "NC", - "GPMC_WAIT0", - "GPMC_WP_N"; -}; - -&gpio1 { - gpio-line-names = - "GPMC_AD0", - "GPMC_AD1", - "GPMC_AD2", - "GPMC_AD3", - "GPMC_AD4", - "GPMC_AD5", - "GPMC_AD6", - "GPMC_AD7", - "NC", - "NC", - "CONSOLE_RX", - "CONSOLE_TX", - "NC", - "NC", - "NC", - "SD_CD", - "RGMII2_TCTL", - "RGMII2_RCTL", - "RGMII2_TD3", - "RGMII2_TD2", - "RGMII2_TD1", - "RGMII2_TD0", - "RGMII2_TCLK", - "RGMII2_RCLK", - "RGMII2_RD3", - "RGMII2_RD2", - "RGMII2_RD1", - "RGMII2_RD0", - "PMIC_INT1", - "GPMC_CSN0_Flash", - "MMC1_CLK", - "MMC1_CMD"; -}; - -&gpio2 { - gpio-line-names = - "GPMC_CSN3_BUS", - "GPMC_CLK", - "GPMC_ADVN_ALE", - "GPMC_OEN_RE_N", - "GPMC_WE_N", - "GPMC_BEN0_CLE", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "SW2_0", - "SW2_1", - "RMII1_RXD1", - "RMII1_RXD0", - "UART1_DTR", - "UART1_DSR", - "UART1_DCD", - "UART1_RI", - "MMC0_DAT3", - "MMC0_DAT2", - "MMC0_DAT1", - "MMC0_DAT0", - "MMC0_CLK", - "MMC0_CMD"; -}; - -&gpio3 { - gpio-line-names = - "onrisc:red:power", - "RMII1_CRS_DV", - "RMII1_RXER", - "RMII1_TXEN", - "NC", - "NC", - "NC", - "WLAN_IRQ", - "WLAN_EN", - "SW2_2", - "SW2_3", - "NC", - "NC", - "NC", - "ModeA0", - "ModeA1", - "ModeA2", - "ModeA3", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts deleted file mode 100644 index ea4f8dde6424..000000000000 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "OnRISC Baltos iR 3220"; -}; - -&am33xx_pinmux { - tca6416_pins: tca6416-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&i2c1 { - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", - "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", - "ModeA0", "ModeA1", "ModeA2", "ModeA3", - "ModeB0", "ModeB1", "ModeB2", "ModeB3"; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&cpsw_port1 { - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&cpsw_port2 { - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - phy-handle = <&phy1>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; -}; - -&gpio0 { - gpio-line-names = - "MDIO", - "MDC", - "UART2_RX", - "UART2_TX", - "I2C1_SDA", - "I2C1_SCL", - "WLAN_BTN", - "W_DISABLE", - "NC", - "NC", - "NC", - "NC", - "UART1_CTSN", - "UART1_RTSN", - "UART1_RX", - "UART1_TX", - "onrisc:blue:wlan", - "onrisc:green:app", - "USB0_DRVVBUS", - "ETH2_INT", - "TCA6416_INT", - "RMII1_TXD1", - "MMC1_DAT0", - "MMC1_DAT1", - "NC", - "NC", - "MMC1_DAT2", - "MMC1_DAT3", - "RMII1_TXD0", - "NC", - "GPMC_WAIT0", - "GPMC_WP_N"; -}; - -&gpio1 { - gpio-line-names = - "GPMC_AD0", - "GPMC_AD1", - "GPMC_AD2", - "GPMC_AD3", - "GPMC_AD4", - "GPMC_AD5", - "GPMC_AD6", - "GPMC_AD7", - "NC", - "NC", - "CONSOLE_RX", - "CONSOLE_TX", - "UART2_DTR", - "UART2_DSR", - "UART2_DCD", - "UART2_RI", - "RGMII2_TCTL", - "RGMII2_RCTL", - "RGMII2_TD3", - "RGMII2_TD2", - "RGMII2_TD1", - "RGMII2_TD0", - "RGMII2_TCLK", - "RGMII2_RCLK", - "RGMII2_RD3", - "RGMII2_RD2", - "RGMII2_RD1", - "RGMII2_RD0", - "PMIC_INT1", - "GPMC_CSN0_Flash", - "MMC1_CLK", - "MMC1_CMD"; -}; - -&gpio2 { - gpio-line-names = - "GPMC_CSN3_BUS", - "GPMC_CLK", - "GPMC_ADVN_ALE", - "GPMC_OEN_RE_N", - "GPMC_WE_N", - "GPMC_BEN0_CLE", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "SD_CD", - "SD_WP", - "RMII1_RXD1", - "RMII1_RXD0", - "UART1_DTR", - "UART1_DSR", - "UART1_DCD", - "UART1_RI", - "MMC0_DAT3", - "MMC0_DAT2", - "MMC0_DAT1", - "MMC0_DAT0", - "MMC0_CLK", - "MMC0_CMD"; -}; - -&gpio3 { - gpio-line-names = - "onrisc:red:power", - "RMII1_CRS_DV", - "RMII1_RXER", - "RMII1_TXEN", - "3G_PWR_EN", - "UART2_CTSN", - "UART2_RTSN", - "WLAN_IRQ", - "WLAN_EN", - "NC", - "NC", - "NC", - "NC", - "USB1_DRVVBUS", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts deleted file mode 100644 index ec914f27d11d..000000000000 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ /dev/null @@ -1,297 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "OnRISC Baltos iR 5221"; -}; - -&am33xx_pinmux { - tca6416_pins: tca6416-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ - >; - }; - - - dcan1_pins: dcan1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&i2c1 { - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", - "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", - "ModeA0", "ModeA1", "ModeA2", "ModeA3", - "ModeB0", "ModeB1", "ModeB2", "ModeB3"; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cpsw_port1 { - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&cpsw_port2 { - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - phy-handle = <&phy1>; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; -}; - -&gpio0 { - gpio-line-names = - "MDIO", - "MDC", - "UART2_RX", - "UART2_TX", - "I2C1_SDA", - "I2C1_SCL", - "WLAN_BTN", - "W_DISABLE", - "NC", - "NC", - "NC", - "NC", - "UART1_CTSN", - "UART1_RTSN", - "UART1_RX", - "UART1_TX", - "onrisc:blue:wlan", - "onrisc:green:app", - "USB0_DRVVBUS", - "ETH2_INT", - "TCA6416_INT", - "RMII1_TXD1", - "MMC1_DAT0", - "MMC1_DAT1", - "NC", - "NC", - "MMC1_DAT2", - "MMC1_DAT3", - "RMII1_TXD0", - "NC", - "GPMC_WAIT0", - "GPMC_WP_N"; -}; - -&gpio1 { - gpio-line-names = - "GPMC_AD0", - "GPMC_AD1", - "GPMC_AD2", - "GPMC_AD3", - "GPMC_AD4", - "GPMC_AD5", - "GPMC_AD6", - "GPMC_AD7", - "DCAN1_TX", - "DCAN1_RX", - "CONSOLE_RX", - "CONSOLE_TX", - "UART2_DTR", - "UART2_DSR", - "UART2_DCD", - "UART2_RI", - "RGMII2_TCTL", - "RGMII2_RCTL", - "RGMII2_TD3", - "RGMII2_TD2", - "RGMII2_TD1", - "RGMII2_TD0", - "RGMII2_TCLK", - "RGMII2_RCLK", - "RGMII2_RD3", - "RGMII2_RD2", - "RGMII2_RD1", - "RGMII2_RD0", - "PMIC_INT1", - "GPMC_CSN0_Flash", - "MMC1_CLK", - "MMC1_CMD"; -}; - -&gpio2 { - gpio-line-names = - "GPMC_CSN3_BUS", - "GPMC_CLK", - "GPMC_ADVN_ALE", - "GPMC_OEN_RE_N", - "GPMC_WE_N", - "GPMC_BEN0_CLE", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "SD_CD", - "SD_WP", - "RMII1_RXD1", - "RMII1_RXD0", - "UART1_DTR", - "UART1_DSR", - "UART1_DCD", - "UART1_RI", - "MMC0_DAT3", - "MMC0_DAT2", - "MMC0_DAT1", - "MMC0_DAT0", - "MMC0_CLK", - "MMC0_CMD"; -}; - -&gpio3 { - gpio-line-names = - "onrisc:red:power", - "RMII1_CRS_DV", - "RMII1_RXER", - "RMII1_TXEN", - "3G_PWR_EN", - "UART2_CTSN", - "UART2_RTSN", - "WLAN_IRQ", - "WLAN_EN", - "NC", - "NC", - "NC", - "NC", - "USB1_DRVVBUS", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi deleted file mode 100644 index 6a52e42b9e81..000000000000 --- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/*#include "am33xx.dtsi"*/ - -/ { - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - compatible = "gpio-leds"; - - led-power { - label = "onrisc:red:power"; - linux,default-trigger = "default-on"; - gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - led-wlan { - label = "onrisc:blue:wlan"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-app { - label = "onrisc:green:app"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - user_leds: user-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */ - >; - }; -}; diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi deleted file mode 100644 index c56087048cc1..000000000000 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -#include "am33xx.dtsi" -#include -#include - -/ { - compatible = "vscom,onrisc", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 8 0>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ - AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ - >; - }; - - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ - >; - }; - - tps65910_pins: tps65910-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ - - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - nandflash_pins_s0: nandflash-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - status = "okay"; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "prefetch-dma"; - - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - ti,elm-id = <&elm>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tps65910_pins>; - }; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <8>; - reg = <0x50>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - ti,en-ck32k-xtal = <1>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - - status = "okay"; -}; - -&davinci_mdio_sw { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - phy1: ethernet-phy@1 { - reg = <7>; - eee-broken-100tx; - eee-broken-1000t; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc_reg>; - status = "okay"; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0_target { - ti,no-reset-on-init; -}; - -&gpio3_target { - ti,no-reset-on-init; -}; diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts deleted file mode 100644 index eba843e22ea1..000000000000 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - */ - -#include "am335x-igep0033.dtsi" - -/ { - model = "IGEP COM AM335x on AQUILA Expansion"; - compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_pins>; - pinctrl-1 = <&nxp_hdmi_off_pins>; - status = "okay"; - }; - - leds_base { - pinctrl-names = "default"; - pinctrl-0 = <&leds_base_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "base:red:user"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ - default-state = "off"; - }; - - led1 { - label = "base:green:user"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - nxp_hdmi_pins: nxp-hdmi-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - nxp_hdmi_off_pins: nxp-hdmi-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - >; - }; - - leds_base_pins: leds-base-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi deleted file mode 100644 index 0b073f290abc..000000000000 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ /dev/null @@ -1,411 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led2 { - label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led3 { - label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user-leds-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: clkout2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - emmc_pins: emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - baseboard_eeprom: baseboard_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - - #address-cells = <1>; - #size-cells = <1>; - baseboard_data: baseboard_data@0 { - reg = <0 0x100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <100000>; - - cape_eeprom0: cape_eeprom0@54 { - compatible = "atmel,24c256"; - reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; - cape0_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom1: cape_eeprom1@55 { - compatible = "atmel,24c256"; - reg = <0x55>; - #address-cells = <1>; - #size-cells = <1>; - cape1_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom2: cape_eeprom2@56 { - compatible = "atmel,24c256"; - reg = <0x56>; - #address-cells = <1>; - #size-cells = <1>; - cape2_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom3: cape_eeprom3@57 { - compatible = "atmel,24c256"; - reg = <0x57>; - #address-cells = <1>; - #size-cells = <1>; - cape3_data: cape_data@0 { - reg = <0 0x100>; - }; - }; -}; - - -/include/ "tps65217.dtsi" - -&tps { - /* - * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only - * mode") at poweroff. Most BeagleBone versions do not support RTC-only - * mode and risk hardware damage if this mode is entered. - * - * For details, see linux-omap mailing list May 2015 thread - * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller - * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html - * - * You can override this later with - * &tps { /delete-property/ ti,pmic-shutdown-controller; } - * if you want to use RTC-only mode and made sure you are not affected - * by the hardware problems. (Tip: double-check by performing a current - * measurement after shutdown: it should be less than 1 mA.) - */ - - interrupts = <7>; /* NMI */ - interrupt-parent = <&intc>; - - ti,pmic-shutdown-controller; - - charger { - status = "okay"; - }; - - pwrbutton { - status = "okay"; - }; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "mii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mmc1 { - status = "okay"; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; - system-power-controller; -}; - -&pruss_tm { - status = "okay"; -}; - -&wkup_m3_ipc { - firmware-name = "am335x-bone-scale-data.bin"; -}; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts deleted file mode 100644 index b5d85ef51a02..000000000000 --- a/arch/arm/boot/dts/am335x-bone.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" - -/ { - model = "TI AM335x BeagleBone"; - compatible = "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&ldo3_reg>; -}; diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi deleted file mode 100644 index a7a8c61ef9b2..000000000000 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; - non-removable; -}; - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi deleted file mode 100644 index 109f08fd174d..000000000000 --- a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include - -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; -}; - -&lcdc { - status = "okay"; - - /* If you want to get 24 bit RGB and 16 BGR mode instead of - * current 16 bit RGB and 24 BGR modes, set the propety - * below to "crossed" and uncomment the video-ports -property - * in tda19988 node. - */ - blue-and-red-wiring = "straight"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - nxp,calib-gpios = <&gpio1 25 0>; - interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ - /* video-ports = <0x234501>; */ - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_0: endpoint { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -/ { - clk_mcasp0_fixed: clk_mcasp0_fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk_mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; -}; diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts deleted file mode 100644 index b4b4b80df08c..000000000000 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-boneblack-hdmi.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Black Wireless"; - compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - /* WL_EN */ - gpio = <&gpio3 9 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - bt_pins: bt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: wl18xx-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ - >; - }; -}; - -&mac_sw { - status = "disabled"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio3 { - ls-buf-en-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts deleted file mode 100644 index b956e2f60fe0..000000000000 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-boneblack-hdmi.dtsi" - -/ { - model = "TI AM335x BeagleBone Black"; - compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&cpu0_opp_table { - /* - * All PG 2.0 silicon may not support 1GHz but some of the early - * BeagleBone Blacks have PG 2.0 silicon which is guaranteed - * to support 1GHz OPP so enable it for PG 2.0 on this board. - */ - oppnitro-1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; - -&gpio0 { - gpio-line-names = - "[mdio_data]", - "[mdio_clk]", - "P9_22 [spi0_sclk]", - "P9_21 [spi0_d0]", - "P9_18 [spi0_d1]", - "P9_17 [spi0_cs0]", - "[mmc0_cd]", - "P8_42A [ecappwm0]", - "P8_35 [lcd d12]", - "P8_33 [lcd d13]", - "P8_31 [lcd d14]", - "P8_32 [lcd d15]", - "P9_20 [i2c2_sda]", - "P9_19 [i2c2_scl]", - "P9_26 [uart1_rxd]", - "P9_24 [uart1_txd]", - "[rmii1_txd3]", - "[rmii1_txd2]", - "[usb0_drvvbus]", - "[hdmi cec]", - "P9_41B", - "[rmii1_txd1]", - "P8_19 [ehrpwm2a]", - "P8_13 [ehrpwm2b]", - "NC", - "NC", - "P8_14", - "P8_17", - "[rmii1_txd0]", - "[rmii1_refclk]", - "P9_11 [uart4_rxd]", - "P9_13 [uart4_txd]"; -}; - -&gpio1 { - gpio-line-names = - "P8_25 [mmc1_dat0]", - "[mmc1_dat1]", - "P8_5 [mmc1_dat2]", - "P8_6 [mmc1_dat3]", - "P8_23 [mmc1_dat4]", - "P8_22 [mmc1_dat5]", - "P8_3 [mmc1_dat6]", - "P8_4 [mmc1_dat7]", - "NC", - "NC", - "NC", - "NC", - "P8_12", - "P8_11", - "P8_16", - "P8_15", - "P9_15A", - "P9_23", - "P9_14 [ehrpwm1a]", - "P9_16 [ehrpwm1b]", - "[emmc rst]", - "[usr0 led]", - "[usr1 led]", - "[usr2 led]", - "[usr3 led]", - "[hdmi irq]", - "[usb vbus oc]", - "[hdmi audio]", - "P9_12", - "P8_26", - "P8_21 [emmc]", - "P8_20 [emmc]"; -}; - -&gpio2 { - gpio-line-names = - "P9_15B", - "P8_18", - "P8_7", - "P8_8", - "P8_10", - "P8_9", - "P8_45 [hdmi]", - "P8_46 [hdmi]", - "P8_43 [hdmi]", - "P8_44 [hdmi]", - "P8_41 [hdmi]", - "P8_42 [hdmi]", - "P8_39 [hdmi]", - "P8_40 [hdmi]", - "P8_37 [hdmi]", - "P8_38 [hdmi]", - "P8_36 [hdmi]", - "P8_34 [hdmi]", - "[rmii1_rxd3]", - "[rmii1_rxd2]", - "[rmii1_rxd1]", - "[rmii1_rxd0]", - "P8_27 [hdmi]", - "P8_29 [hdmi]", - "P8_28 [hdmi]", - "P8_30 [hdmi]", - "[mmc0_dat3]", - "[mmc0_dat2]", - "[mmc0_dat1]", - "[mmc0_dat0]", - "[mmc0_clk]", - "[mmc0_cmd]"; -}; - -&gpio3 { - gpio-line-names = - "[mii col]", - "[mii crs]", - "[mii rx err]", - "[mii tx en]", - "[mii rx dv]", - "[i2c0 sda]", - "[i2c0 scl]", - "[jtag emu0]", - "[jtag emu1]", - "[mii tx clk]", - "[mii rx clk]", - "NC", - "NC", - "[usb vbus en]", - "P9_31 [spi1_sclk]", - "P9_29 [spi1_d0]", - "P9_30 [spi1_d1]", - "P9_28 [spi1_cs0]", - "P9_42B [ecappwm0]", - "P9_27", - "P9_41A", - "P9_25", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; - -&baseboard_eeprom { - vcc-supply = <&ldo4_reg>; -}; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts deleted file mode 100644 index b78e38f87892..000000000000 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ /dev/null @@ -1,616 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Blue"; - compatible = "ti,am335x-bone-blue", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - usr_0_led { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - usr_1_led { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - usr_2_led { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - usr_3_led { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - wifi_led { - label = "wifi"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "phy0assoc"; - }; - - red_led { - label = "red"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green_led { - label = "green"; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_1_led { - label = "bat25"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_2_led { - label = "bat50"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_3_led { - label = "bat75"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_4_led { - label = "bat100"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - /* WL_EN */ - gpio = <&gpio3 9 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - user_leds_s0: user-leds-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ - - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - >; - }; - - /* UT0 */ - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - /* UT1 */ - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - /* GPS */ - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ - >; - }; - - /* DSM2 */ - uart4_pins: uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - >; - }; - - /* UT5 */ - uart5_pins: uart5-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ - >; - }; - - bt_pins: bt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: wl18xx-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ - >; - }; - - /* DCAN */ - dcan1_pins: dcan1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ - >; - }; - - /* E1 */ - eqep0_pins: eqep0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ - >; - }; - - /* E2 */ - eqep1_pins: eqep1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ - >; - }; - - /* E3 */ - eqep2_pins: eqep2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&i2c0 { - baseboard_eeprom: baseboard_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - - #address-cells = <1>; - #size-cells = <1>; - baseboard_data: baseboard_data@0 { - reg = <0 0x100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; - - mpu9250@68 { - compatible = "invensense,mpu9250"; - reg = <0x68>; - interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ax8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - }; - }; - }; - - pressure@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - }; -}; - -/include/ "tps65217.dtsi" - -&tps { - /delete-property/ ti,pmic-shutdown-controller; - - charger { - interrupts = <0>, <1>; - interrupt-names = "USB", "AC"; - status = "okay"; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&rtc { - system-power-controller; - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - "UART3_CTS", /* M17 */ - "UART3_RTS", /* M18 */ - "UART2_RX", /* A17 */ - "UART2_TX", /* B17 */ - "I2C1_SDA", /* B16 */ - "I2C1_SCL", /* A16 */ - "MMC0_CD", /* C15 */ - "SPI1_SS2", /* C18 */ - "EQEP_1A", /* V2 */ - "EQEP_1B", /* V3 */ - "MDIR_2B", /* V4 */ - "BATT_LED_2", /* T5 */ - "I2C2_SDA", /* D18 */ - "I2C2_SCL", /* D17 */ - "UART1_RX", /* D16 */ - "UART1_TX", /* D15 */ - "MMC2_DAT1", /* J18 */ - "MMC2_DAT2", /* K15 */ - "NC", /* F16 */ - "WIFI_LED", /* A15 */ - "MOT_STBY", /* D14 */ - "WLAN_IRQ", /* K16 */ - "PWM_2A", /* U10 */ - "PWM_2B", /* T10 */ - "", - "", - "BATT_LED_4", /* T11 */ - "BATT_LED_1", /* U12 */ - "BT_EN", /* K17 */ - "SPI1_SS1", /* H18 */ - "UART4_RX", /* T17 */ - "MDIR_1B"; /* U17 */ -}; - -&gpio1 { - gpio-line-names = - "MMC1_DAT0", /* U7 */ - "MMC1_DAT1", /* V7 */ - "MMC1_DAT2", /* R8 */ - "MMC1_DAT3", /* T8 */ - "MMC1_DAT4", /* U8 */ - "MMC1_DAT5", /* V8 */ - "MMC1_DAT6", /* R9 */ - "MMC1_DAT7", /* T9 */ - "DCAN1_TX", /* E18 */ - "DCAN1_RX", /* E17 */ - "UART0_RX", /* E15 */ - "UART0_TX", /* E16 */ - "EQEP_2A", /* T12 */ - "EQEP_2B", /* R12 */ - "PRU_E_A", /* V13 */ - "PRU_E_B", /* U13 */ - "MDIR_2A", /* R13 */ - "GPIO1_17", /* V14 */ - "PWM_1A", /* U14 */ - "PWM_1B", /* T14 */ - "EMMC_RST", /* R14 */ - "USR_LED_0", /* V15 */ - "USR_LED_1", /* U15 */ - "USR_LED_2", /* T15 */ - "USR_LED_3", /* V16 */ - "GPIO1_25", /* U16 */ - "MCASP0_AXR0", /* T16 */ - "MCASP0_AXR1", /* V17 */ - "MCASP0_ACLKR", /* U18 */ - "BATT_LED_3", /* V6 */ - "MMC1_CLK", /* U9 */ - "MMC1_CMD"; /* V9 */ -}; - -&gpio2 { - gpio-line-names = - "MDIR_1A", /* T13 */ - "MCASP0_FSR", /* V12 */ - "LED_RED", /* R7 */ - "LED_GREEN", /* T7 */ - "MODE_BTN", /* U6 */ - "PAUSE_BTN", /* T6 */ - "MDIR_4A", /* R1 */ - "MDIR_4B", /* R2 */ - "MDIR_3B", /* R3 */ - "MDIR_3A", /* R4 */ - "SVO7", /* T1 */ - "SVO8", /* T2 */ - "SVO5", /* T3 */ - "SVO6", /* T4 */ - "UART5_TX", /* U1 */ - "UART5_RX", /* U2 */ - "SERVO_EN", /* U3 */ - "NC", /* U4 */ - "UART3_RX", /* L17 */ - "UART3_TX", /* L16 */ - "MMC2_CLK", /* L15 */ - "DCAN1_SILENT", /* M16 */ - "SVO1", /* U5 */ - "SVO3", /* R5 */ - "SVO2", /* V5 */ - "SVO4", /* R6 */ - "MMC0_DAT3", /* F17 */ - "MMC0_DAT2", /* F18 */ - "MMC0_DAT1", /* G15 */ - "MMC0_DAT0", /* G16 */ - "MMC0_CLK", /* G17 */ - "MMC0_CMD"; /* G18 */ -}; - -&gpio3 { - gpio-line-names = - "MMC2_DAT3", /* H16 */ - "GPIO3_1", /* H17 */ - "GPIO3_2", /* J15 */ - "MMC2_CMD", /* J16 */ - "MMC2_DAT0", /* J17 */ - "I2C0_SDA", /* C17 */ - "I2C0_SCL", /* C16 */ - "EMU1", /* C14 */ - "EMU0", /* B14 */ - "WL_EN", /* K18 */ - "WL_BT_OE", /* L18 */ - "", - "", - "NC", /* F15 */ - "SPI1_SCK", /* A13 */ - "SPI1_MISO", /* B13 */ - "SPI1_MOSI", /* D12 */ - "GPIO3_17", /* C12 */ - "EQEP_0A", /* B12 */ - "EQEP_0B", /* C13 */ - "GPIO3_20", /* D13 */ - "IMU_INT", /* A14 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; - - ls-buf-en-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&eqep0 { - pinctrl-names = "default"; - pinctrl-0 = <&eqep0_pins>; - status = "okay"; -}; - -&epwmss1 { - status = "okay"; -}; - -&eqep1 { - pinctrl-names = "default"; - pinctrl-0 = <&eqep1_pins>; - status = "okay"; -}; - -&epwmss2 { - status = "okay"; -}; - -&eqep2 { - pinctrl-names = "default"; - pinctrl-0 = <&eqep2_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi deleted file mode 100644 index 383beeddf595..000000000000 --- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&am33xx_pinmux { - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&rtc { - system-power-controller; -}; diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts deleted file mode 100644 index a4f5b5262645..000000000000 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Green Wireless"; - compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - /* WL_EN */ - gpio = <&gpio0 26 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - bt_pins: bt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: wl18xx-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ - >; - }; -}; - -&mac_sw { - status = "disabled"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio1 { - ls-buf-en-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; - -/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/ -/* in case it isn't, wilink8 ends up in one of the test modes that */ -/* intruces various issues (elp wkaeup timeouts etc.) */ -/* On the BBGW this pin is routed through the level shifter (U21) that */ -/* introduces a pullup on the line and wilink8 ends up in a bad state. */ -/* use a gpio hog to force this pin low. An alternative may be adding */ -/* an external pulldown on U21 pin 4. */ - -&gpio3 { - bt-aud-in-hog { - gpio-hog; - gpios = <16 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP0_AHCLKR"; - }; -}; diff --git a/arch/arm/boot/dts/am335x-bonegreen.dts b/arch/arm/boot/dts/am335x-bonegreen.dts deleted file mode 100644 index 18cc0f49e999..000000000000 --- a/arch/arm/boot/dts/am335x-bonegreen.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" - -/ { - model = "TI AM335x BeagleBone Green"; - compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts deleted file mode 100644 index 648e97fe1dfd..000000000000 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ - * Author: Rostislav Lisovy - */ -/dts-v1/; -#include "am335x-chilisom.dtsi" - -/ { - model = "AM335x Chiliboard"; - compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", - "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_gpio_pins>; - - led0 { - label = "led0"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "led1"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -&am33xx_pinmux { - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb1_drvvbus: usb1-drvvbus-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - sd_pins: sd-card-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - led_gpio_pins: led-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&ldo4_reg { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -/* Ethernet */ -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -/* USB */ -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_drvvbus>; - dr_mode = "host"; -}; - -/* microSD */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins>; - vmmc-supply = <&ldo4_reg>; - bus-width = <0x4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&tps { - interrupt-parent = <&intc>; - interrupts = <7>; /* NNMI */ - - charger { - status = "okay"; - }; - - pwrbutton { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi deleted file mode 100644 index 51021d582214..000000000000 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ - * Author: Rostislav Lisovy - */ -#include "am33xx.dtsi" -#include - -/ { - model = "Grinn AM335x ChiliSOM"; - compatible = "grinn,am335x-chilisom", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - nandflash_pins: nandflash-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - -}; - -/include/ "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3d"; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&rtc { - system-power-controller; - - pinctrl-0 = <&ext_wakeup>; - pinctrl-names = "default"; - - ext_wakeup: ext-wakeup { - pins = "ext_wakeup0"; - input-enable; - }; -}; - -/* NAND Flash */ -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts deleted file mode 100644 index 72990e7ffe10..000000000000 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 - * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "CompuLab CM-T335"; - compatible = "compulab,cm-t335", "ti,am33xx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_led_pins>; - led0 { - label = "cm_t335:green"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ - linux,default-trigger = "heartbeat"; - }; - }; - - /* regulator for mmc */ - vmmc_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* Regulator for WiFi */ - vwlan_fixed: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "vwlan_fixed"; - gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ - enable-active-high; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "cm-t335"; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Headphone", "Headphone Jack"; - - simple-audio-card,routing = - "Headphone Jack", "LHPOUT", - "Headphone Jack", "RHPOUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic Jack"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic23>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_pins>; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - /* uart0_ctsn.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) - /* uart0_rtsn.i2c1_scl */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) - >; - }; - - gpio_led_pins: gpio-led-pins { - pinctrl-single,pins = < - /* gpmc_csn3.gpio2_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) - >; - }; - - nandflash_pins: nandflash-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - dcan0_pins: dcan0-pins { - pinctrl-single,pins = < - /* uart1_ctsn.dcan0_tx */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) - /* uart1_rtsn.dcan0_rx */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) - >; - }; - - dcan1_pins: dcan1-pins { - pinctrl-single,pins = < - /* uart1_rxd.dcan1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) - /* uart1_txd.dcan1_rx */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) - >; - }; - - ecap0_pins: ecap0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - /* mii1_tx_en.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd0.rgmii1_rd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - spi0_pins: spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) - >; - }; - - /* wl1271 bluetooth */ - bluetooth_pins: bluetooth-pins { - pinctrl-single,pins = < - /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) - >; - }; - - /* TLV320AIC23B codec */ - mcasp1_pins: mcasp1-pins { - pinctrl-single,pins = < - /* MII1_CRS.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) - /* MII1_RX_ER.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) - /* MII1_COL.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) - /* RMII1_REF_CLK.mcasp1_axr3 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) - >; - }; - - /* wl1271 WiFi */ - wifi_pins: wifi-pins { - pinctrl-single,pins = < - /* EMU1.gpio3_8 - WiFi IRQ */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) - /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -/* WLS1271 bluetooth */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - -status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - /* CM-T335 board EEPROM */ - eeprom: 24c02@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - /* Real Time Clock */ - ext_rtc: em3027@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - /* Audio codec */ - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells = <0>; - status = "okay"; - }; -}; - -&epwmss0 { - status = "okay"; - - ecap0: pwm@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "spl"; - reg = <0x00000000 0x00200000>; - }; - partition@1 { - label = "uboot"; - reg = <0x00200000 0x00100000>; - }; - partition@2 { - label = "uboot environment"; - reg = <0x00300000 0x00100000>; - }; - partition@3 { - label = "dtb"; - reg = <0x00400000 0x00100000>; - }; - partition@4 { - label = "splash"; - reg = <0x00500000 0x00400000>; - }; - partition@5 { - label = "linux"; - reg = <0x00900000 0x00600000>; - }; - partition@6 { - label = "rootfs"; - reg = <0x00F00000 0>; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&dcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; -}; - -/* Touschscreen and analog digital converter */ -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x01 0x10 0x23 0x32>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -/* CPU audio */ -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp1_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 16 serializers */ - num-serializer = <16>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; - - #sound-dai-cells = <0>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in; - /* WLS1271 WiFi */ - wlcore: wlcore@1 { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pins>; - reg = <1>; - spi-max-frequency = <48000000>; - clock-xtal; - ref-clock-frequency = <38400000>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts deleted file mode 100644 index 6560db1dcdbe..000000000000 --- a/arch/arm/boot/dts/am335x-evm.dts +++ /dev/null @@ -1,786 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "TI AM335x EVM"; - compatible = "ti,am335x-evm", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wlan_en_reg: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* WLAN_EN GPIO for this board - Bank1, pin16 */ - gpio = <&gpio1 16 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* TPS79501 */ - v1_8d_reg: fixedregulator-v1_8d { - compatible = "regulator-fixed"; - regulator-name = "v1_8d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* TPS79501 */ - v3_3d_reg: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "v3_3d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ - &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ - &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ - - col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ - &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ - - linux,keymap = <0x0000008b /* MENU */ - 0x0100009e /* BACK */ - 0x02000069 /* LEFT */ - 0x0001006a /* RIGHT */ - 0x0101001c /* ENTER */ - 0x0201006c>; /* DOWN */ - }; - - gpio_keys: volume-keys { - compatible = "gpio-keys"; - autorepeat; - - switch-9 { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - switch-10 { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - panel { - compatible = "tfc,s9700rtwv43tr-01b"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - backlight = <&backlight>; - - port { - panel_0: endpoint { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - - matrix_keypad_s0: matrix-keypad-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - volume_keys_s0: volume-keys-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: clkout2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - nandflash_pins_s0: nandflash-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - ecap0_pins: backlight-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ - >; - }; - - wlan_pins: wlan-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ - >; - }; - - lcd_pins_s0: lcd-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - mcasp1_pins: mcasp1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - dcan1_pins_default: dcan1-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&usb1 { - dr_mode = "host"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tsl2550: tsl2550@39 { - compatible = "taos,tsl2550"; - reg = <0x39>; - }; - - tmp275: tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&v3_3d_reg>; - IOVDD-supply = <&v3_3d_reg>; - DRVDD-supply = <&v3_3d_reg>; - DVDD-supply = <&v1_8d_reg>; - }; -}; - -&lcdc { - status = "okay"; - - blue-and-red-wiring = "crossed"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&panel_0>; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: pwm@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000C0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001C0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001E0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00A00000 0x0F600000>; - }; - }; -}; - -#include "tps65910.dtsi" - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wlan_pins>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&dcan1 { - status = "disabled"; /* Enable only if Profile 1 is selected */ - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins_default>; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; - -&pruss_tm { - status = "okay"; -}; - -&wkup_m3_ipc { - firmware-name = "am335x-evm-scale-data.bin"; -}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts deleted file mode 100644 index 332f6c8ae68b..000000000000 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ /dev/null @@ -1,725 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "TI AM335x EVM-SK"; - compatible = "ti,am335x-evmsk", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 29 0>; - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator3 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - /* TPS79518 */ - v1_8d_reg: fixedregulator-v1_8d { - compatible = "regulator-fixed"; - regulator-name = "v1_8d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* TPS78633 */ - v3_3d_reg: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "v3_3d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "evmsk:green:usr0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "evmsk:green:usr1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "evmsk:green:mmc0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "evmsk:green:heartbeat"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio_buttons: gpio_buttons0 { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - switch1 { - label = "button0"; - linux,code = <0x100>; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - }; - - switch2 { - label = "button1"; - linux,code = <0x101>; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - - switch3 { - label = "button2"; - linux,code = <0x102>; - gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - switch4 { - label = "button3"; - linux,code = <0x103>; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - }; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 58 61 66 75 90 125 170 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVMSK"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - panel { - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - backlight = <&lcd_bl>; - - port { - panel_0: endpoint { - remote-endpoint = <&lcdc_0>; - }; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - - lcd_pins_default: lcd-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - - user_leds_s0: user-leds-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - >; - }; - - gpio_keys_s0: gpio-keys-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: clkout2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - ecap2_pins: backlight-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ - >; - }; - - mcasp1_pins: mcasp1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - >; - }; - - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&v3_3d_reg>; - IOVDD-supply = <&v3_3d_reg>; - DRVDD-supply = <&v3_3d_reg>; - DVDD-supply = <&v1_8d_reg>; - }; -}; - -&usb1 { - dr_mode = "host"; -}; - -&epwmss2 { - status = "okay"; - - ecap2: pwm@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0_target { - ti,no-reset-on-init; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ - ref-clock-frequency = <38400000>; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; -}; - -&lcdc { - status = "okay"; - - blue-and-red-wiring = "crossed"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&panel_0>; - }; - }; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; - -&pruss_tm { - status = "okay"; -}; - -&wkup_m3_ipc { - firmware-name = "am335x-evm-scale-data.bin"; -}; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts deleted file mode 100644 index 3031fc9061a4..000000000000 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ /dev/null @@ -1,745 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2018 Robert Bosch Power Tools GmbH - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "Bosch AM335x Guardian"; - compatible = "bosch,am335x-guardian", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - tick-timer = &timer2; - }; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - guardian_buttons: gpio-keys { - pinctrl-names = "default"; - pinctrl-0 = <&guardian_button_pins>; - compatible = "gpio-keys"; - - select-button { - label = "guardian-select-button"; - linux,code = ; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - power-button { - label = "guardian-power-button"; - linux,code = ; - gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - guardian_leds: gpio-leds { - pinctrl-names = "default"; - pinctrl-0 = <&guardian_led_pins>; - compatible = "gpio-leds"; - - life-led { - label = "guardian:life-led"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; - pinctrl-1 = <&lcd_pins_sleep>; - - display-timings { - 320x240 { - hactive = <320>; - vactive = <240>; - hback-porch = <68>; - hfront-porch = <20>; - hsync-len = <1>; - vback-porch = <18>; - vfront-porch = <4>; - vsync-len = <1>; - clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <24>; - bus-width = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - }; - - guardian_beeper: pwm-7 { - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer7>; - pinctrl-names = "default"; - pinctrl-0 = <&guardian_beeper_pins>; - ti,clock-source = <0x01>; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mt_keypad: mt_keypad@0 { - compatible = "gpio-mt-keypad"; - debounce-delay-ms = <10>; - col-scan-delay-us = <2>; - keypad,num-lines = <5>; - linux,no-autorepeat; - gpio-activelow; - line-gpios = < - &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/ - &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/ - &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/ - &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/ - &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/ - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - status = "okay"; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <30>; - gpmc,cs-wr-off-ns = <30>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <15>; - gpmc,oe-on-ns = <1>; - gpmc,oe-off-ns = <15>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <30>; - gpmc,wr-cycle-ns = <30>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - - /* - * MTD partition table - * - * All SPL-* partitions are sized to minimal length which can - * be independently programmable. For NAND flash this is equal - * to size of erase-block. - */ - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0x0 0x40000>; - }; - - partition@1 { - label = "SPL.backup1"; - reg = <0x40000 0x40000>; - }; - - partition@2 { - label = "SPL.backup2"; - reg = <0x80000 0x40000>; - }; - - partition@3 { - label = "SPL.backup3"; - reg = <0xc0000 0x40000>; - }; - - partition@4 { - label = "u-boot"; - reg = <0x100000 0x100000>; - }; - - partition@5 { - label = "u-boot.backup1"; - reg = <0x200000 0x100000>; - }; - - partition@6 { - label = "u-boot-2"; - reg = <0x300000 0x100000>; - }; - - partition@7 { - label = "u-boot-2.backup1"; - reg = <0x400000 0x100000>; - }; - - partition@8 { - label = "u-boot-env"; - reg = <0x500000 0x40000>; - }; - - partition@9 { - label = "u-boot-env.backup1"; - reg = <0x540000 0x40000>; - }; - - partition@10 { - label = "splash-screen"; - reg = <0x580000 0x40000>; - }; - - partition@11 { - label = "UBI"; - reg = <0x5c0000 0x1fa40000>; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - tps: tps@24 { - reg = <0x24>; - }; -}; - -&lcdc { - blue-and-red-wiring = "crossed"; - status = "okay"; - port { - lcdc_0: endpoint@0 { - remote-endpoint = <0>; - }; - }; -}; - -&mmc1 { - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; - -&spi0 { - ti,pindir-d0-out-d1-in; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; -}; - -#include "tps65217.dtsi" - -&tps { - /* - * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only - * mode") at poweroff. Most BeagleBone versions do not support RTC-only - * mode and risk hardware damage if this mode is entered. - * - * For details, see linux-omap mailing list May 2015 thread - * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller - * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html - * - * You can override this later with - * &tps { /delete-property/ ti,pmic-shutdown-controller; } - * if you want to use RTC-only mode and made sure you are not affected - * by the hardware problems. (Tip: double-check by performing a current - * measurement after shutdown: it should be less than 1 mA.) - */ - ti,pmic-shutdown-controller; - interrupt-parent = <&intc>; - interrupts = <7>; /* NMI */ - - backlight { - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <500>; /* TPS65217_BL_FDIM_500HZ */ - default-brightness = <50>; - /* 1(on) - enable current sink, while initialization */ - /* 0(off) - disable current sink, while initialization */ - isink-en = <1>; - }; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6>; - }; -}; - -&gpio0 { - gpio-line-names = - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "MirxWakeup", - "", - ""; -}; - -&gpio3 { - ti,gpio-always-on; - ti,no-reset-on-init; - gpio-line-names = - "", - "MirxBtReset", - "", - "CcVolAdcEn", - "MirxBlePause", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "AspEn", - "", - "", - "", - "", - "", - "", - "BatVolAdcEn", - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; -}; - -&usb1 { - dr_mode = "host"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; - - clkout2_pin: clkout2-pins { - pinctrl-single,pins = < - /* xdma_event_intr1.clkout2 */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) - >; - }; - - guardian_interface_pins: interface-pins { - pinctrl-single,pins = < - /* ADC_BATSENSE_EN */ - /* (A14) MCASP0_AHCLKx.gpio3[21] */ - AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) - /* ADC_COINCELL_EN */ - /* (J16) MII1_TX_EN.gpio3[3] */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) - /* ASP_ENABLE */ - /* (A13) MCASP0_ACLKx.gpio3[14] */ - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) - /* (D16) uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) - /* (D15) uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) - /*SWITCH-OFF_3V6*/ - /* (M18) gpio0[1] */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) - /* MIRACULIX */ - /* (H17) gmii1_crs.gpio3[1] */ - AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) - /* (H18) rmii1_refclk.gpio0[29] */ - AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) - /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 ) - /* (J17) gmii1_rxdv.gpio3[4] */ - AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) - >; - }; - - guardian_beeper_pins: dmtimer7-pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ - >; - }; - - guardian_button_pins: guardian-button-pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ - AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ - >; - }; - - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - led_bl_pins: gpio-led-bl-pins { - pinctrl-single,pins = < - /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) - >; - }; - - lcd_disen_pins: lcd-disen-pins { - pinctrl-single,pins = < - /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ - AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) - >; - }; - - lcd_pins_default: lcd-default-pins { - pinctrl-single,pins = < - /* (U10) gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (T10) gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (T11) gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (U12) gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (T12) gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (R12) gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (V13) gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* (U13) gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - /* lcd_ac_bias_en.lcd_ac_bias_en */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd-sleep-pins { - pinctrl-single,pins = < - /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - /* lcd_ac_bias_en.lcd_ac_bias_en */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - >; - }; - - guardian_led_pins: guardian-led-pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ - >; - }; - - spi0_pins: spi0-pins { - pinctrl-single,pins = < - /* SPI0_CLK - spi0_clk.spi */ - AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - /* SPI0_MOSI - spi0_d0.spi0 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) - /* SPI0_MISO - spi0_d1.spi0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) - /* SPI0_CS0 - spi */ - AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) - /* uart0_txd.uart0_txd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - /* K18 uart2_rxd.mirx_txd */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) - /* L18 uart2_txd.mirx_rxd */ - AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) - >; - }; - - nandflash_pins: nandflash-pins { - pinctrl-single,pins = < - /* (U7) gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) - /* (V7) gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) - /* (R8) gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) - /* (T8) gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) - /* (U8) gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) - /* (V8) gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) - /* (R9) gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) - /* (T9) gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) - /* (T17) gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) - /* (U17) gpmc_wpn.gpmc_wpn */ - AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) - /* (V6) gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) - /* (R7) gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) - /* (T7) gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) - /* (U6) gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) - /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) - >; - }; -}; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts deleted file mode 100644 index 7ed2321a8b40..000000000000 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ /dev/null @@ -1,518 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 - */ - -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "TI AM3359 ICE-V2"; - compatible = "ti,am3359-icev2", "ti,am33xx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - leds-iio { - status = "disabled"; - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - /* Tricolor status LEDs */ - leds1 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - led0 { - label = "status0:red:cpu0"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - led1 { - label = "status0:green:usr"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "status0:yellow:usr"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "status1:red:mmc0"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led4 { - label = "status1:green:usr"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "status1:yellow:usr"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - gpio-decoder { - compatible = "gpio-decoder"; - gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, - <&pca9536 2 GPIO_ACTIVE_HIGH>, - <&pca9536 1 GPIO_ACTIVE_HIGH>, - <&pca9536 0 GPIO_ACTIVE_HIGH>; - linux,axis = <0>; /* ABS_X */ - decoder-max-value = <9>; - }; -}; - -&am33xx_pinmux { - user_leds: user-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ - >; - }; - - mmc0_pins_default: mmc0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c0_pins_default: i2c0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - spi0_pins_default: spi0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ - >; - }; - - uart3_pins_default: uart3-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1, RMII mode */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ - /* Slave 2, RMII mode */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_default>; - - status = "okay"; - clock-frequency = <400000>; - - tps: power-controller@2d { - reg = <0x2d>; - }; - - tpic2810: gpio@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9536: gpio@41 { - compatible = "ti,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* osd9616p0899-10 */ - display@3c { - compatible = "solomon,ssd1306fb-i2c"; - reg = <0x3c>; - solomon,height = <16>; - solomon,width = <96>; - solomon,com-seq; - solomon,com-invdir; - solomon,page-offset = <0>; - solomon,prechargep1 = <2>; - solomon,prechargep2 = <13>; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_default>; - - sn65hvs882@1 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - - reg = <1>; - spi-max-frequency = <1000000>; - spi-cpol; - }; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64", "jedec,spi-nor"; - spi-max-frequency = <80000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "u-boot"; - reg = <0x80000 0x100000>; - read-only; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - read-only; - }; - - partition@3 { - label = "misc"; - reg = <0x1A0000 0x660000>; - }; - }; - -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <1 2 3 4 5 6 7>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1326000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_default>; -}; - -&gpio0_target { - /* Do not idle the GPIO used for holding the VTT regulator */ - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; - status = "okay"; -}; - -&gpio3 { - pr1-mii-ctl-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PR1_MII_CTRL"; - }; - - mux-mii-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ - output-high; - line-name = "MUX_MII_CTL1"; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <2>; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; /* PHY datasheet states 1uS min */ - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@3 { - reg = <3>; - }; -}; - -&pruss_tm { - status = "okay"; -}; - -&rtc { - system-power-controller; -}; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi deleted file mode 100644 index 4aed73655401..000000000000 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "com:green:user"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vmmc: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - nandflash_pins: nandflash-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - leds_pins: leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - >; - }; -}; - -&mac_sw { - status = "okay"; -}; - -&davinci_mdio_sw { - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <2>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - ti,elm-id = <&elm>; - - /* MTD partition table */ - partition@0 { - label = "SPL"; - reg = <0x00000000 0x00080000>; - }; - - partition@1 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; - - partition@2 { - label = "U-Boot Env"; - reg = <0x00260000 0x00020000>; - }; - - partition@3 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; - - partition@4 { - label = "File System"; - reg = <0x00780000 0x07880000>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc>; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&usb1 { - dr_mode = "host"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-always-on; - }; - }; -}; - diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts deleted file mode 100644 index 008be696327a..000000000000 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ /dev/null @@ -1,347 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "NovaTech OrionLXm"; - compatible = "novatech,am335x-lxm", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - /* Power supply provides a fixed 5V @2A */ - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -&am33xx_pinmux { - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - emmc_pins: emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - serial_config1: serial_config1@20 { - compatible = "nxp,pca9539"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - serial_config2: serial_config2@21 { - compatible = "nxp,pca9539"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; -}; - -/include/ "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - /* vrtc - unused */ - - vio_reg: regulator@1 { - regulator-name = "vio_1v5,ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd1,mpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd2_1v1,core"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd3 - unused */ - - /* vdig1 - unused */ - - vdig2_reg: regulator@6 { - regulator-name = "vdig2_1v8,vdds_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vpll - unused */ - - vdac_reg: regulator@8 { - regulator-name = "vdac_1v8,vdds"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-name = "vaux1_1v8,usb"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-name = "vaux2_3v3,io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-name = "vaux33_3v3,usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-name = "vmmc_3v3,io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <2>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <3>; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@5 { - reg = <5>; - }; - - ethphy1: ethernet-phy@4 { - reg = <4>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi deleted file mode 100644 index b8730aa52ce6..000000000000 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ - * - * Authors: SZ Lin (林上智) - * Wes Huang (黃淵河) - * Fero JD Zhou (周俊達) - */ - -#include "am33xx.dtsi" - -/ { - vbat: vbat-regulator { - compatible = "regulator-fixed"; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buttons: push_button { - compatible = "gpio-keys"; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - push_button_pins: push-button-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc1_pins_default: mmc1-pins { - pinctrl-single,pins = < - /* eMMC */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - >; - }; - - spi0_pins: spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&uart0 { - /* Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_wdt: rtc_wdt@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; -}; - -&usb0 { - dr_mode = "host"; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; -}; - -&cpsw_port1 { - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - ti,dual-emac-pvid = <2>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0_target { - ti,no-reset-on-init; -}; - -&mmc2 { - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-0 = <&mmc1_pins_default>; - non-removable; - status = "okay"; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins>; - - button-0 { - label = "push_button"; - linux,code = <0x100>; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - flash@0 { - compatible = "mx25l6405d"; - spi-max-frequency = <40000000>; - - reg = <0>; - spi-cpol; - spi-cpha; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* reg : The partition's offset and size within the mtd bank. */ - partitions@0 { - label = "MLO"; - reg = <0x0 0x80000>; - }; - - partitions@1 { - label = "U-Boot"; - reg = <0x80000 0x100000>; - }; - - partitions@2 { - label = "U-Boot Env"; - reg = <0x180000 0x40000>; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - - tpm_spi_tis@0 { - compatible = "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <500000>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts deleted file mode 100644 index e986945ac1b5..000000000000 --- a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ - * - * Authors: SZ Lin (林上智) - * Wes Huang (黃淵河) - * Fero JD Zhou (周俊達) - */ - -/dts-v1/; - -#include "am335x-moxa-uc-2100-common.dtsi" - -/ { - model = "Moxa UC-2101"; - compatible = "moxa,uc-2101", "ti,am33xx"; - - leds { - compatible = "gpio-leds"; - led1 { - label = "UC2100:GREEN:USER"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - spi1_pins: spi1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ - >; - }; -}; - -&davinci_mdio_sw { - phy0: ethernet-phy@4 { - reg = <4>; - }; -}; - -&cpsw_port1 { - phy-handle = <&phy0>; - phy-mode = "rmii"; -}; - -&cpsw_port2 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi deleted file mode 100644 index c16f3cff1e4b..000000000000 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/ - * - * Author: Johnson Chen - */ - -#include "am33xx.dtsi" - -/ { - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - vbat: vbat-regulator { - compatible = "regulator-fixed"; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buttons: push_button { - compatible = "gpio-keys"; - }; - -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_pins>; - - minipcie_pins: minipcie-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ - >; - }; - - push_button_pins: push-button-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ - - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc0_pins_default: mmc0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ - >; - }; - - mmc2_pins_default: mmc2-pins { - pinctrl-single,pins = < - /* eMMC */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - spi0_pins: spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - -}; - -&uart0 { - /* Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* UART 1 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart5 { - /* UART 2 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_wdt: rtc_wdt@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - gpio_xten: gpio_xten@27 { - compatible = "nxp,pca9535"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x27>; - }; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1 { - dr_mode = "host"; -}; - - -#include "tps65910.dtsi" -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - - ethphy1: ethernet-phy@5 { - reg = <5>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <2>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0_target { - ti,no-reset-on-init; -}; - -&mmc1 { - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-0 = <&mmc0_pins_default>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-0 = <&mmc2_pins_default>; - ti,non-removable; - status = "okay"; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins>; - - button-0 { - label = "push_button"; - linux,code = <0x100>; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - flash@0 { - compatible = "mx25l6405d"; - spi-max-frequency = <40000000>; - - reg = <0>; - spi-cpol; - spi-cpha; - #address-cells = <1>; - #size-cells = <1>; - - /* reg : The partition's offset and size within the mtd bank. */ - partitions@0 { - label = "MLO"; - reg = <0x0 0x80000>; - }; - - partitions@1 { - label = "U-Boot"; - reg = <0x80000 0x100000>; - }; - - partitions@2 { - label = "U-Boot Env"; - reg = <0x180000 0x20000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts deleted file mode 100644 index 0c7949d21bd9..000000000000 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ - * - * Author: SZ Lin (林上智) - */ -/dts-v1/; - -#include "am335x-moxa-uc-8100-common.dtsi" - -/ { - model = "Moxa UC-8100-ME-T"; - compatible = "moxa,uc-8100-me-t", "ti,am33xx"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "uc8100me:CEL1"; - gpios = <&gpio_xten 8 0>; - default-state = "off"; - }; - - led2 { - label = "uc8100me:CEL2"; - gpios = <&gpio_xten 9 0>; - default-state = "off"; - }; - - led3 { - label = "uc8100me:CEL3"; - gpios = <&gpio_xten 10 0>; - default-state = "off"; - }; - - led4 { - label = "uc8100me:DIA1"; - gpios = <&gpio_xten 11 0>; - default-state = "off"; - }; - led5 { - label = "uc8100me:DIA2"; - gpios = <&gpio_xten 12 0>; - default-state = "off"; - }; - led6 { - label = "uc8100me:DIA3"; - gpios = <&gpio_xten 13 0>; - default-state = "off"; - }; - led7 { - label = "uc8100me:SD"; - gpios = <&gpio_xten 14 0>; - default-state = "off"; - }; - led8 { - label = "uc8100me:USB"; - gpios = <&gpio_xten 15 0>; - default-state = "off"; - }; - led9 { - label = "uc8100me:USER"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&i2c0 { - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; -}; - -&tps { - regulators { - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi deleted file mode 100644 index 584599269217..000000000000 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* SPDX-FileCopyrightText: Alexander Shiyan, */ - -/* Based on code by myc_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ - -/dts-v1/; - -#include "am33xx.dtsi" - -#include -#include - -/ { - model = "MYIR MYC-AM335X"; - compatible = "myir,myc-am335x", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd_core>; - voltage-tolerance = <2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - clk32k: clk32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - - #clock-cells = <0>; - }; - - vdd_mod: vdd_mod_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd-mod"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_core: vdd_core_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd-core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mod>; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_mod_pins>; - - led_mod: led_mod { - label = "module:user"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - color = ; - default-state = "off"; - panic-indicator; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ð_slave1_pins_default>; - pinctrl-1 = <ð_slave1_pins_sleep>; - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdio_pins_default>; - pinctrl-1 = <&mdio_pins_sleep>; - - phy0: ethernet-phy@4 { - reg = <4>; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&nand_pins_default>; - pinctrl-1 = <&nand_pins_sleep>; - ranges = <0 0 0x8000000 0x1000000>; - status = "okay"; - - nand0: nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>; - nand-bus-width = <8>; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-pin = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - ti,elm-id = <&elm>; - ti,nand-ecc-opt = "bch8"; - }; -}; - -&i2c0 { - pinctrl-names = "default", "gpio", "sleep"; - pinctrl-0 = <&i2c0_pins_default>; - pinctrl-1 = <&i2c0_pins_gpio>; - pinctrl-2 = <&i2c0_pins_sleep>; - clock-frequency = <400000>; - scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <&vdd_mod>; - }; -}; - -&rtc { - clocks = <&clk32k>; - clock-names = "ext-clk"; - system-power-controller; -}; - -&am33xx_pinmux { - mdio_pins_default: mdio-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */ - >; - }; - - mdio_pins_sleep: mdio-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - eth_slave1_pins_default: eth-slave1-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */ - >; - }; - - eth_slave1_pins_sleep: eth-slave1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - i2c0_pins_default: i2c0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */ - >; - }; - - i2c0_pins_gpio: i2c0-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */ - >; - }; - - i2c0_pins_sleep: i2c0-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - led_mod_pins: led-mod-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */ - >; - }; - - nand_pins_default: nand-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */ - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */ - >; - }; - - nand_pins_sleep: nand-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; -}; diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts deleted file mode 100644 index d3bba79b9358..000000000000 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ /dev/null @@ -1,549 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* SPDX-FileCopyrightText: Alexander Shiyan, */ -/* Based on code by myd_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ - -/dts-v1/; - -#include "am335x-myirtech-myc.dtsi" - -#include -#include - -/ { - model = "MYIR MYD-AM335X"; - compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - clk12m: clk12m { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - - #clock-cells = <0>; - }; - - gpio_buttons: gpio_buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_buttons_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button1: button@0 { - reg = <0>; - label = "button1"; - linux,code = ; - gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - }; - - button2: button@1 { - reg = <1>; - label = "button2"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&master_codec>; - simple-audio-card,frame-master = <&master_codec>; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - }; - - master_codec: simple-audio-card,codec@1 { - sound-dai = <&sgtl5000>; - }; - - simple-audio-card,codec@2 { - sound-dai = <&tda9988>; - }; - }; - - vdd_5v0: vdd_5v0_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3: vdd_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v0>; - }; -}; - -&cpsw_port2 { - status = "okay"; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - phy1: ethernet-phy@6 { - reg = <6>; - eee-broken-1000t; - }; -}; - -&mac_sw { - pinctrl-0 = <ð_slave1_pins_default>, <ð_slave2_pins_default>; - pinctrl-1 = <ð_slave1_pins_sleep>, <ð_slave2_pins_sleep>; - slaves = <2>; -}; - -&dcan0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan0_pins_default>; - pinctrl-1 = <&dcan0_pins_sleep>; - status = "okay"; -}; - -&dcan1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan1_pins_default>; - pinctrl-1 = <&dcan1_pins_sleep>; - status = "okay"; -}; - -&ehrpwm0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&ehrpwm0_pins_default>; - pinctrl-1 = <&ehrpwm0_pins_sleep>; - status = "okay"; -}; - -&epwmss0 { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio", "sleep"; - pinctrl-0 = <&i2c1_pins_default>; - pinctrl-1 = <&i2c1_pins_gpio>; - pinctrl-2 = <&i2c1_pins_sleep>; - clock-frequency = <400000>; - scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg =<0xa>; - clocks = <&clk12m>; - micbias-resistor-k-ohms = <4>; - micbias-voltage-m-volts = <2250>; - VDDA-supply = <&vdd_3v3>; - VDDIO-supply = <&vdd_3v3>; - - #sound-dai-cells = <0>; - }; - - tda9988: tda9988@70 { - compatible = "nxp,tda998x"; - reg =<0x70>; - audio-ports = ; - - #sound-dai-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_0: endpoint { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - }; -}; - -&lcdc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcdc_pins_default>; - pinctrl-1 = <&lcdc_pins_sleep>; - blue-and-red-wiring = "straight"; - status = "okay"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&leds { - pinctrl-0 = <&led_mod_pins &leds_pins>; - - led1: led1 { - label = "base:user1"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - color = ; - default-state = "off"; - }; - - led2: led2 { - label = "base:user2"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - color = ; - default-state = "off"; - }; -}; - -&mcasp0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp0_pins_default>; - pinctrl-1 = <&mcasp0_pins_sleep>; - op-mode = <0>; - tdm-slots = <2>; - serial-dir = <0 1 2 0>; - tx-num-evt = <32>; - rx-num-evt = <32>; - status = "okay"; - - #sound-dai-cells = <0>; -}; - -&mmc1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_sleep>; - cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <&vdd_3v3>; - status = "okay"; -}; - -&nand0 { - nand_parts: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "MLO"; - reg = <0x00000 0x20000>; - }; - - partition@80000 { - label = "boot"; - reg = <0x80000 0x100000>; - }; - }; -}; - -&tscadc { - status = "okay"; - - adc: adc { - ti,adc-channels = <0 1 2 3 4 5 6>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_pins_default>; - pinctrl-1 = <&uart1_pins_sleep>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart2_pins_default>; - pinctrl-1 = <&uart2_pins_sleep>; - status = "okay"; -}; - -&usb { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; -}; - -&usb0 { - dr_mode = "otg"; -}; - -&usb0_phy { - vcc-supply = <&vdd_5v0>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&usb1_phy { - vcc-supply = <&vdd_5v0>; -}; - -&vdd_mod { - vin-supply = <&vdd_3v3>; -}; - -&am33xx_pinmux { - dcan0_pins_default: dcan0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ - >; - }; - - dcan0_pins_sleep: dcan0-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - dcan1_pins_default: dcan1-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ - >; - }; - - dcan1_pins_sleep: dcan1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - ehrpwm0_pins_default: ehrpwm0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ - >; - }; - - ehrpwm0_pins_sleep: ehrpwm0-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - eth_slave2_pins_default: eth-slave2-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */) - >; - }; - - eth_slave2_pins_sleep: eth-slave2-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - gpio_buttons_pins: gpio-buttons-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ - >; - }; - - i2c1_pins_default: i2c1-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ - >; - }; - - i2c1_pins_gpio: i2c1-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ - >; - }; - - i2c1_pins_sleep: i2c1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - lcdc_pins_default: lcdc-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */ - >; - }; - - lcdc_pins_sleep: lcdc-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - leds_pins: leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ - >; - }; - - mcasp0_pins_default: mcasp0-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */ - >; - }; - - mcasp0_pins_sleep: mcasp0-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */ - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */ - >; - }; - - mmc1_pins_sleep: mmc1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ - >; - }; - - uart1_pins_default: uart1-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ - >; - }; - - uart1_pins_sleep: uart1-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - uart2_pins_default: uart2-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ - >; - }; - - uart2_pins_sleep: uart2-sleep-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb_pins: usb-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ - AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ - >; - }; -}; diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts deleted file mode 100644 index 9305ba9d85ef..000000000000 --- a/arch/arm/boot/dts/am335x-nano.dts +++ /dev/null @@ -1,492 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "Newflow AM335x NanoBone"; - compatible = "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "nanobone:green:usr1"; - gpios = <&gpio1 5 0>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&misc_pins>; - - misc_pins: misc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ - >; - }; - - gpmc_pins: gpmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ - - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ - >; - }; - - uart4_pins: uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ - >; - }; - - uart5_pins: uart5-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rx-during-tx; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; - rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rx-during-tx; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rx-during-tx; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - - tps: tps@24 { - reg = <0x24>; - }; - - temperature-sensor@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - eeprom@53 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x53>; - pagesize = <8>; - }; - - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - compatible = "ti,am3352-gpmc"; - status = "okay"; - gpmc,num-waitpins = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */ - <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */ - - nor@0,0 { - reg = <0 0x00000000 0x08000000>; - compatible = "cfi-flash"; - linux,mtd-name = "spansion,s29gl010p11t"; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <10>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,oe-on-ns = <40>; - gpmc,oe-off-ns = <160>; - gpmc,we-on-ns = <40>; - gpmc,we-off-ns = <160>; - gpmc,rd-cycle-ns = <160>; - gpmc,wr-cycle-ns = <160>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wr-data-mux-bus-ns = <70>; - gpmc,wr-access-ns = <80>; - - #address-cells = <1>; - #size-cells = <1>; - - /* - MTD partition table - =================== - +------------+-->0x00000000-> U-Boot start - | | - | |-->0x000BFFFF-> U-Boot end - | |-->0x000C0000-> ENV1 start - | | - | |-->0x000DFFFF-> ENV1 end - | |-->0x000E0000-> ENV2 start - | | - | |-->0x000FFFFF-> ENV2 end - | |-->0x00100000-> Kernel start - | | - | |-->0x004FFFFF-> Kernel end - | |-->0x00500000-> File system start - | | - | |-->0x01FFFFFF-> File system end - | |-->0x02000000-> User data start - | | - | |-->0x03FFFFFF-> User data end - | |-->0x04000000-> Data storage start - | | - +------------+-->0x08000000-> NOR end (Free end) - */ - partition@0 { - label = "boot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@1 { - label = "env1"; - reg = <0x000c0000 0x00020000>; /* 128KB */ - }; - - partition@2 { - label = "env2"; - reg = <0x000e0000 0x00020000>; /* 128KB */ - }; - - partition@3 { - label = "kernel"; - reg = <0x00100000 0x00400000>; /* 4MB */ - }; - - partition@4 { - label = "rootfs"; - reg = <0x00500000 0x01b00000>; /* 27MB */ - }; - - partition@5 { - label = "user"; - reg = <0x02000000 0x02000000>; /* 32MB */ - }; - - partition@6 { - label = "data"; - reg = <0x04000000 0x04000000>; /* 64MB */ - }; - }; - - fram@1,0 { - reg = <1 0x00000000 0x01000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <10>; - gpmc,adv-rd-off-ns = <20>; - gpmc,adv-wr-off-ns = <20>; - gpmc,oe-on-ns = <30>; - gpmc,oe-off-ns = <150>; - gpmc,we-on-ns = <30>; - gpmc,we-off-ns = <150>; - gpmc,rd-cycle-ns = <160>; - gpmc,wr-cycle-ns = <160>; - gpmc,access-ns = <130>; - gpmc,page-burst-access-ns = <10>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cycle2cycle-delay-ns = <10>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <0>; - }; -}; - -&mac_sw { - status = "okay"; -}; - -&davinci_mdio_sw { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "mii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "mii"; - ti,dual-emac-pvid = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&ldo4_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-debounce-delay-ms = <5>; - cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; -}; - -&usb0 { - dr_mode = "host"; -}; - -#include "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - /* +1.5V voltage with ±4% tolerance */ - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts deleted file mode 100644 index f7fad48e36ed..000000000000 --- a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "NetCAN"; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led@1 { - label = "can_data"; - linux,default-trigger = "netdev"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - led@2 { - label = "can_error"; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - user_leds_s0: user-leds-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */ - >; - }; - - dcan1_pins: dcan1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */ - >; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&davinci_mdio_sw { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - phy-handle = <&phy1>; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - "MDIO", - "MDC", - "NC", - "NC", - "I2C1_SDA", - "I2C1_SCL", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "can_data", - "can_error", - "onrisc:blue:wlan", - "onrisc:green:app", - "USB0_DRVVBUS", - "ETH2_INT", - "NC", - "NC", - "MMC1_DAT0", - "MMC1_DAT1", - "NC", - "NC", - "MMC1_DAT2", - "MMC1_DAT3", - "NC", - "NC", - "GPMC_WAIT0", - "GPMC_WP_N"; -}; - -&gpio1 { - gpio-line-names = - "GPMC_AD0", - "GPMC_AD1", - "GPMC_AD2", - "GPMC_AD3", - "GPMC_AD4", - "GPMC_AD5", - "GPMC_AD6", - "GPMC_AD7", - "DCAN1_TX", - "DCAN1_RX", - "CONSOLE_RX", - "CONSOLE_TX", - "NC", - "NC", - "NC", - "NC", - "RGMII2_TCTL", - "RGMII2_RCTL", - "RGMII2_TD3", - "RGMII2_TD2", - "RGMII2_TD1", - "RGMII2_TD0", - "RGMII2_TCLK", - "RGMII2_RCLK", - "RGMII2_RD3", - "RGMII2_RD2", - "RGMII2_RD1", - "RGMII2_RD0", - "PMIC_INT1", - "GPMC_CSN0_Flash", - "MMC1_CLK", - "MMC1_CMD"; -}; - -&gpio2 { - gpio-line-names = - "GPMC_CSN3_BUS", - "GPMC_CLK", - "GPMC_ADVN_ALE", - "GPMC_OEN_RE_N", - "GPMC_WE_N", - "GPMC_BEN0_CLE", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "SW2_0", - "SW2_1", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "MMC0_DAT3", - "MMC0_DAT2", - "MMC0_DAT1", - "MMC0_DAT0", - "MMC0_CLK", - "MMC0_CMD"; -}; - -&gpio3 { - gpio-line-names = - "onrisc:red:power", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "WLAN_IRQ", - "WLAN_EN", - "SW2_2", - "SW2_3", - "NC", - "NC", - "NC", - "ModeA0", - "ModeA1", - "ModeA2", - "ModeA3", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts deleted file mode 100644 index 76751a324ad7..000000000000 --- a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "NetCom Plus"; -}; - -&am33xx_pinmux { - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ - >; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&davinci_mdio_sw { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - phy-handle = <&phy1>; -}; - -&gpio0 { - gpio-line-names = - "MDIO", - "MDC", - "UART2_RX", - "UART2_TX", - "I2C1_SDA", - "I2C1_SCL", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "UART1_CTSN", - "UART1_RTSN", - "UART1_RX", - "UART1_TX", - "onrisc:blue:wlan", - "onrisc:green:app", - "USB0_DRVVBUS", - "ETH2_INT", - "NC", - "NC", - "MMC1_DAT0", - "MMC1_DAT1", - "NC", - "NC", - "MMC1_DAT2", - "MMC1_DAT3", - "NC", - "NC", - "GPMC_WAIT0", - "GPMC_WP_N"; -}; - -&gpio1 { - gpio-line-names = - "GPMC_AD0", - "GPMC_AD1", - "GPMC_AD2", - "GPMC_AD3", - "GPMC_AD4", - "GPMC_AD5", - "GPMC_AD6", - "GPMC_AD7", - "NC", - "NC", - "CONSOLE_RX", - "CONSOLE_TX", - "UART2_DTR", - "UART2_DSR", - "UART2_DCD", - "UART2_RI", - "RGMII2_TCTL", - "RGMII2_RCTL", - "RGMII2_TD3", - "RGMII2_TD2", - "RGMII2_TD1", - "RGMII2_TD0", - "RGMII2_TCLK", - "RGMII2_RCLK", - "RGMII2_RD3", - "RGMII2_RD2", - "RGMII2_RD1", - "RGMII2_RD0", - "PMIC_INT1", - "GPMC_CSN0_Flash", - "MMC1_CLK", - "MMC1_CMD"; -}; - -&gpio2 { - gpio-line-names = - "GPMC_CSN3_BUS", - "GPMC_CLK", - "GPMC_ADVN_ALE", - "GPMC_OEN_RE_N", - "GPMC_WE_N", - "GPMC_BEN0_CLE", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "SW2_0", - "SW2_1", - "NC", - "NC", - "UART1_DTR", - "UART1_DSR", - "UART1_DCD", - "UART1_RI", - "MMC0_DAT3", - "MMC0_DAT2", - "MMC0_DAT1", - "MMC0_DAT0", - "MMC0_CLK", - "MMC0_CMD"; -}; - -&gpio3 { - gpio-line-names = - "onrisc:red:power", - "NC", - "NC", - "NC", - "NC", - "UART2_CTSN", - "UART2_RTSN", - "WLAN_IRQ", - "WLAN_EN", - "SW2_2", - "SW2_3", - "NC", - "NC", - "NC", - "ModeA0", - "ModeA1", - "ModeA2", - "ModeA3", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts deleted file mode 100644 index 5a9fcec040fa..000000000000 --- a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" - -/ { - model = "NetCom Plus"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&dip_switches>; - - dip_switches: dip-switches-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - tca6416_pins: tca6416-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) - >; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&i2c1 { - tca6416a: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", - "GP_IN4", "GP_IN5", "GP_IN6", "GP_IN7", - "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", - "GP_OUT4", "GP_OUT5", "GP_OUT6", "GP_OUT7"; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tca6416b: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "CH1_M0", "CH1_M1", "CH1_M2", "CH1_M3", - "CH2_M0", "CH2_M1", "CH2_M2", "CH2_M3", - "CH3_M0", "CH3_M1", "CH3_M2", "CH3_M3", - "CH4_M0", "CH4_M1", "CH4_M2", "CH4_M3"; - }; - - tca6416c: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "CH5_M0", "CH5_M1", "CH5_M2", "CH5_M3", - "CH6_M0", "CH6_M1", "CH6_M2", "CH6_M3", - "CH7_M0", "CH7_M1", "CH7_M2", "CH7_M3", - "CH8_M0", "CH8_M1", "CH8_M2", "CH8_M3"; - }; -}; - -&davinci_mdio_sw { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - phy-handle = <&phy1>; -}; - -&gpio0 { - gpio-line-names = - "MDIO", - "MDC", - "NC", - "NC", - "I2C1_SDA", - "I2C1_SCL", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "I2C2_SDA", - "I2C2_SCL", - "NC", - "NC", - "onrisc:blue:wlan", - "onrisc:green:app", - "USB0_DRVVBUS", - "ETH2_INT", - "NC", - "NC", - "MMC1_DAT0", - "MMC1_DAT1", - "NC", - "NC", - "MMC1_DAT2", - "MMC1_DAT3", - "NC", - "NC", - "GPMC_WAIT0", - "GPMC_WP_N"; -}; - -&gpio1 { - gpio-line-names = - "GPMC_AD0", - "GPMC_AD1", - "GPMC_AD2", - "GPMC_AD3", - "GPMC_AD4", - "GPMC_AD5", - "GPMC_AD6", - "GPMC_AD7", - "NC", - "NC", - "CONSOLE_RX", - "CONSOLE_TX", - "SW2_0_alt", - "SW2_1_alt", - "SW2_2_alt", - "SW2_3_alt", - "RGMII2_TCTL", - "RGMII2_RCTL", - "RGMII2_TD3", - "RGMII2_TD2", - "RGMII2_TD1", - "RGMII2_TD0", - "RGMII2_TCLK", - "RGMII2_RCLK", - "RGMII2_RD3", - "RGMII2_RD2", - "RGMII2_RD1", - "RGMII2_RD0", - "PMIC_INT1", - "GPMC_CSN0_Flash", - "MMC1_CLK", - "MMC1_CMD"; -}; - -&gpio2 { - gpio-line-names = - "GPMC_CSN3_BUS", - "GPMC_CLK", - "GPMC_ADVN_ALE", - "GPMC_OEN_RE_N", - "GPMC_WE_N", - "GPMC_BEN0_CLE", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "SW2_0", - "SW2_1", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "MMC0_DAT3", - "MMC0_DAT2", - "MMC0_DAT1", - "MMC0_DAT0", - "MMC0_CLK", - "MMC0_CMD"; -}; - -&gpio3 { - gpio-line-names = - "onrisc:red:power", - "NC", - "NC", - "NC", - "3G_PWR_EN", - "NC", - "NC", - "WLAN_IRQ", - "WLAN_EN", - "SW2_2", - "SW2_3", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts deleted file mode 100644 index d28d39728847..000000000000 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ /dev/null @@ -1,434 +0,0 @@ -//SPDX-License-Identifier: GPL-2.0 -/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" -#include - -#include - -/ { - model = "Octavo Systems OSD3358-SM-RED"; - compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&lcdc { - status = "okay"; - - /* If you want to get 24 bit RGB and 16 BGR mode instead of - * current 16 bit RGB and 24 BGR modes, set the propety - * below to "crossed" and uncomment the video-ports -property - * in tda19988 node. - * AM335x errata for wiring: - * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf - */ - - blue-and-red-wiring = "straight"; - - port { - lcdc_0: endpoint { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: hdmi-encoder@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ - /* video-ports = <0x234501>; */ - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - port { - hdmi_0: endpoint { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - - mpu9250: imu@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ax8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - }; - }; - /*invensense,int_config = <0x10>; - invensense,level_shifter = <0>; - invensense,orientation = [01 00 00 00 01 00 00 00 01]; - invensense,sec_slave_type = <0>; - invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ - }; - - bmp280: pressure@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -/ { - clk_mcasp0_fixed: clk-mcasp0-fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk-mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led2 { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led3 { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; - - flash_enable: flash-enable-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ - >; - }; - - imu_interrupt: imu-interrupt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ - >; - }; - - ethernet_interrupt: ethernet-interrupt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; - - user_leds_s0: user-leds-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c2_pins: pinmux-i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux-clkout2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux-mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - emmc_pins: pinmux-emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; - clock-frequency = <100000>; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&rtc { - system-power-controller; - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/am335x-osd335x-common.dtsi deleted file mode 100644 index 2888b15999ee..000000000000 --- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * Author: Robert Nelson - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&cpu0_opp_table { - /* - * Octavo Systems: - * The EFUSE_SMA register is not programmed for any of the AM335x wafers - * we get and we are not programming them during our production test. - * Therefore, from a DEVICE_ID revision point of view, the silicon looks - * like it is Revision 2.1. However, from an EFUSE_SMA point of view for - * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the - * EFUSE_SMA register reads as all zeros). - */ - oppnitro-1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux-i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; -}; - -/include/ "tps65217.dtsi" - -&tps { - interrupts = <7>; /* NMI */ - interrupt-parent = <&intc>; - - ti,pmic-shutdown-controller; - - pwrbutton { - interrupts = <2>; - status = "okay"; - }; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi deleted file mode 100644 index 75efe1cf1dd2..000000000000 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2017 Phytec Messtechnik GmbH - * Author: Wadim Egorov - * Teresa Remmet - */ - -#include - -/ { - model = "Phytec AM335x PCM-953"; - compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"; - - /* Power */ - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vcc1v8: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* User IO */ - user_leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - user-led0 { - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user-led1 { - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - user_buttons: user-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&user_buttons_pins>; - - button-0 { - label = "home"; - linux,code = ; - gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - button-1 { - label = "menu"; - linux,code = ; - gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - }; -}; - -&am33xx_pinmux { - user_buttons_pins: pinmux-user-buttons-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ - >; - }; - - user_leds_pins: pinmux-user-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ - >; - }; -}; - -/* CAN */ -&am33xx_pinmux { - dcan1_pins: pinmux-dcan1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: ethernet1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; -}; - -&cpsw_port2 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; - status = "okay"; -}; - -&davinci_mdio_sw { - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; -}; - -/* Misc */ -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&cb_gpio_pins>; - - cb_gpio_pins: pinmux-cb-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ - >; - }; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux-mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux-uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart2_pins: pinmux-uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ - >; - }; - - uart3_pins: pinmux-uart3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -/* USB */ -&usb1 { - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts deleted file mode 100644 index 92a1d5fea850..000000000000 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ /dev/null @@ -1,573 +0,0 @@ -/* - * pdu001.dts - * - * EETS GmbH PDU001 board device tree file - * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ - * - * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "EETS,PDU001"; - compatible = "ti,am33xx"; - - chosen { - stdout-path = &uart3; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - 240x320p16 { - clock-frequency = <6500000>; - hactive = <240>; - vactive = <320>; - hfront-porch = <6>; - hback-porch = <6>; - hsync-len = <1>; - vback-porch = <6>; - vfront-porch = <6>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <1>; - de-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ - >; - }; - - spi1_pins: spi1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ - >; - }; - - clkout2_pin: clkout2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Port 1 (emac0) */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) - - /* Port 2 (emac1) */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc1_pins: mmc1-pins { - /* eMMC */ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc2_pins: mmc2-pins { - /* SD cardcage */ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - /* card change signal for frontpanel SD cardcage */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - >; - }; - - lcd_pins_s0: lcd-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - dcan0_pins: dcan0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rts-delay = <0 0>; - linux,rs485-enabled-at-boot-time; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - m2_eeprom: m2_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - status = "okay"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - board_24aa025e48: board_24aa025e48@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - backplane_24aa025e48: backplane_24aa025e48@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - reg = <0x60>; - psc0 = <0x97>; - pwm0 = <0x80>; - psc1 = <0x97>; - pwm1 = <0x10>; - - run.red@0 { - type = ; - }; - run.green@1 { - type = ; - default-state = "on"; - }; - s2.red@2 { - type = ; - }; - s2.green@3 { - type = ; - }; - s1.yellow@4 { - type = ; - }; - s1.green@5 { - type = ; - }; - }; - - pca9530: pca9530@61 { - compatible = "nxp,pca9530"; - reg = <0x61>; - - tft-panel@0 { - type = ; - linux,default-trigger = "backlight"; - default-state = "on"; - }; - }; - - mcp79400: rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <100000>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - ti,pindir-d0-out-d1-in; - status = "okay"; - - display-controller@0 { - compatible = "orisetech,otm3225a"; - reg = <0>; - spi-max-frequency = <1000000>; - // SPI mode 3 - spi-cpol; - spi-cpha; - status = "okay"; - }; -}; - -/* - * Disable soc's rtc as we have no VBAT for it. This makes the board - * rtc (Microchip MCP79400) the default rtc device 'rtc0'. - */ -&rtc { - status = "disabled"; -}; - -&lcdc { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-name = "ldo_vrtc"; - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-name = "buck_vdd_ddr"; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits */ - regulator-name = "buck_vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits */ - regulator-name = "buck_vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-name = "boost_res"; - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-name = "ldo_vdig1"; - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-name = "ldo_vdig2"; - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-name = "ldo_vpll"; - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-name = "ldo_vdac"; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-name = "ldo_vaux1"; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-name = "ldo_vaux2"; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-name = "ldo_vaux33"; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-name = "ldo_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vbb_reg: regulator@13 { - regulator-name = "bat_vbb"; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "mii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "mii"; - ti,dual-emac-pvid = <2>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x01 0x10 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - non-removable; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&dcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; -}; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts deleted file mode 100644 index 5a87b25a983b..000000000000 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ /dev/null @@ -1,637 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ - */ -/dts-v1/; - -#include -#include "am33xx.dtsi" - -/ { - model = "Gumstix Pepper"; - compatible = "gumstix,am335x-pepper", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc3_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - buttons: user_buttons { - compatible = "gpio-keys"; - }; - - leds: user-leds-pins { - compatible = "gpio-leds"; - }; - - panel: lcd_panel { - compatible = "ti,tilcdc,panel"; - }; - - sound: sound_iface { - compatible = "ti,da830-evm-audio"; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - }; - - v3v3c_reg: fixedregulator1 { - compatible = "regulator-fixed"; - }; - - vdd5_reg: fixedregulator2 { - compatible = "regulator-fixed"; - }; -}; - -/* I2C Busses */ -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - audio_codec: tlv320aic3106@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - ai3x-micbias-vg = <0x2>; - }; - - accel: lis331dlh@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; -}; - -&am33xx_pinmux { - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ - >; - }; -}; - -/* Accelerometer */ -&accel { - pinctrl-names = "default"; - pinctrl-0 = <&accel_pins>; - - Vdd-supply = <&ldo3_reg>; - Vdd_IO-supply = <&ldo3_reg>; - st,irq1-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <92>; - st,max-limit-x = <14>; - st,min-limit-y = <14>; - st,max-limit-y = <92>; - st,min-limit-z = <92>; - st,max-limit-z = <14>; -}; - -&am33xx_pinmux { - accel_pins: accel-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ - >; - }; -}; - -/* Audio */ -&audio_codec { - status = "okay"; - - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - AVDD-supply = <&ldo3_reg>; - IOVDD-supply = <&ldo3_reg>; - DRVDD-supply = <&ldo3_reg>; - DVDD-supply = <&dcdc1_reg>; -}; - -&sound { - ti,model = "AM335x-EVM"; - ti,audio-codec = <&audio_codec>; - ti,mcasp-controller = <&mcasp0>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "MIC3L", "Mic3L Switch"; -}; - -&mcasp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pins>; - - op-mode = <0>; /* MCASP_ISS_MODE */ - tdm-slots = <2>; - serial-dir = < - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&am33xx_pinmux { - audio_pins: audio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) /* gpmc_a0.gpio1_16 */ - >; - }; -}; - -/* Display: 24-bit LCD Screen */ -&panel { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <18400000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vfront-porch = <4>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; -}; - -&lcdc { - status = "okay"; -}; - -&am33xx_pinmux { - lcd_pins: lcd-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - /* Display Enable */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; -}; - -/* Ethernet */ -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mac_sw { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; -}; - -&am33xx_pinmux { - ethernet_pins: ethernet-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2) - /* ethernet interrupt */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7) /* rmii2_refclk.gpio0_29 */ - /* ethernet PHY nReset */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; - - mdio_pins: mdio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -/* MMC */ -&mmc1 { - /* Bootable SD card slot */ - status = "okay"; - vmmc-supply = <&ldo3_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - /* eMMC (not populated) on MMC #2 */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&ldo3_reg>; - bus-width = <8>; - non-removable; -}; - -&mmc3 { - /* Wifi & Bluetooth on MMC #3 */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wireless_pins>; - vmmmc-supply = <&v3v3c_reg>; - bus-width = <4>; - non-removable; - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; -}; - - -&am33xx_pinmux { - sd_pins: sd-card-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - emmc_pins: emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - /* EMMC nReset */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - >; - }; - wireless_pins: wireless-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc1_clk */ - /* WLAN nReset */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - /* WLAN nPower down */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - /* 32kHz Clock */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&v3v3c_reg { - regulator-name = "v3v3c_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; -}; - -&vdd5_reg { - regulator-name = "vdd5_reg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vbat>; -}; - -/include/ "tps65217.dtsi" - -&tps { - backlight { - isel = <1>; /* ISET1 */ - fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ - default-brightness = <80>; - }; - - regulators { - dcdc1_reg: regulator@0 { - /* VDD_1V8 system supply */ - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* VRTC 1.8V always-on supply */ - regulator-name = "vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* 3.3V rail */ - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* VDD_3V3A 3.3V rail */ - regulator-name = "vdd_3v3a"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4_reg: regulator@6 { - /* VDD_3V3B 3.3V rail */ - regulator-name = "vdd_3v3b"; - regulator-always-on; - }; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -}; - -&am33xx_pinmux { - spi0_pins: spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -/* Touch Screen */ -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -/* UARTs */ -&uart0 { - /* Serial Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* Broken out to J6 header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&am33xx_pinmux { - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -/* USB */ -&usb { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&am33xx_pinmux { - usb_pins: usb-pins { - pinctrl-single,pins = < - /* USB0 Over-Current (active low) */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ - /* USB1 Over-Current (active low) */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; -}; - -/* User IO */ -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - led0 { - label = "pepper:user0:blue"; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - led1 { - label = "pepper:user1:red"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&user_buttons_pins>; - - button-0 { - label = "home"; - linux,code = ; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-1 { - label = "menu"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-2 { - label = "power"; - linux,code = ; - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - wakeup-source; - }; -}; - -&am33xx_pinmux { - user_leds_pins: user-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - >; - }; - - user_buttons_pins: user-buttons-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio0_7 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/am335x-phycore-rdk.dts b/arch/arm/boot/dts/am335x-phycore-rdk.dts deleted file mode 100644 index 43907d03e675..000000000000 --- a/arch/arm/boot/dts/am335x-phycore-rdk.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-pcm-953.dtsi" - -/* SoM */ -&gpmc { - status = "okay"; -}; - -&i2c_eeprom { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&serial_flash { - status = "okay"; - -}; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi deleted file mode 100644 index feb3f4c24978..000000000000 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include "am33xx.dtsi" -#include - -/ { - model = "Phytec AM335x phyCORE"; - compatible = "phytec,am335x-phycore-som", "ti,am33xx"; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &rtc; - rtc2 = &tps; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -/* Crypto Module */ -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -/* EMMC */ -&am33xx_pinmux { - emmc_pins: pinmux-emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmc_reg>; - bus-width = <8>; - non-removable; - status = "disabled"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet0_pins: ethernet0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - mdio_pins: mdio-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&cpsw_port1 { - phy-handle = <&phy0>; - phy-mode = "rmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins>; - status = "okay"; -}; - -/* I2C Busses */ -&am33xx_pinmux { - i2c0_pins: pinmux-i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - tps: pmic@2d { - reg = <0x2d>; - }; - - i2c_tmp102: temp@4b { - compatible = "ti,tmp102"; - reg = <0x4b>; - status = "disabled"; - }; - - i2c_eeprom: eeprom@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - status = "disabled"; - }; - - i2c_rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - status = "disabled"; - }; -}; - -/* NAND memory */ -&am33xx_pinmux { - nandflash_pins: pinmux-nandflash-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ - nandflash: nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <30>; - gpmc,cs-wr-off-ns = <30>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <20>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <30>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <30>; - gpmc,wr-cycle-ns = <30>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <50>; - gpmc,cycle2cycle-diffcsen; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <30>; - gpmc,wr-data-mux-bus-ns = <0>; - - ti,elm-id = <&elm>; - - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -/* Power */ -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vcc5v>; - vcc2-supply = <&vcc5v>; - vcc3-supply = <&vcc5v>; - vcc4-supply = <&vcc5v>; - vcc5-supply = <&vcc5v>; - vcc6-supply = <&vcc5v>; - vcc7-supply = <&vcc5v>; - vccio-supply = <&vcc5v>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-name = "vdig1_1p8v"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* SPI Busses */ -&am33xx_pinmux { - spi0_pins: pinmux-spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - serial_flash: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <48000000>; - reg = <0x0>; - m25p,fast-read; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts deleted file mode 100644 index 5dfe4d4bab93..000000000000 --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts +++ /dev/null @@ -1,484 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * Author: Robert Nelson - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" - -/ { - model = "TI AM335x PocketBeagle"; - compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&usr_leds_pins>; - - compatible = "gpio-leds"; - - led-usr0 { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led-usr1 { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led-usr2 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led-usr3 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gpio0 { - gpio-line-names = - "NC", - "NC", - "P1.08 [SPI0_CLK]", - "P1.10 [SPI0_MISO]", - "P1.12 [SPI0_MOSI]", - "P1.06 [SPI0_CS]", - "[MMC0_CD]", - "P2.29 [SPI1_CLK]", - "[SYSBOOT 12]", - "[SYSBOOT 13]", - "[SYSBOOT 14]", - "[SYSBOOT 15]", - "P1.26 [I2C2_SDA]", - "P1.28 [I2C2_SCL]", - "P2.11 [I2C1_SDA]", - "P2.09 [I2C1_SCL]", - "NC", - "NC", - "NC", - "P2.31 [SPI1_CS]", - "P1.20 [PRU0.16]", - "NC", - "NC", - "P2.03", - "NC", - "NC", - "P1.34", - "P2.19", - "NC", - "NC", - "P2.05 [UART4_RX]", - "P2.07 [UART4_TX]"; -}; - -&gpio1 { - gpio-line-names = - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "P2.25 [SPI1_MOSI]", - "P1.32 [UART0_RX]", - "P1.30 [UART0_TX]", - "P2.24", - "P2.33", - "P2.22", - "P2.18", - "NC", - "NC", - "P2.01 [PWM1A]", - "NC", - "P2.10", - "[USR LED 0]", - "[USR LED 1]", - "[USR LED 2]", - "[USR LED 3]", - "P2.06", - "P2.04", - "P2.02", - "P2.08", - "NC", - "NC", - "NC"; -}; - -&gpio2 { - gpio-line-names = - "P2.20", - "P2.17", - "NC", - "NC", - "NC", - "[EEPROM_WP]", - "[SYSBOOT 0]", - "[SYSBOOT 1]", - "[SYSBOOT 2]", - "[SYSBOOT 3]", - "[SYSBOOT 4]", - "[SYSBOOT 5]", - "[SYSBOOT 6]", - "[SYSBOOT 7]", - "[SYSBOOT 8]", - "[SYSBOOT 9]", - "[SYSBOOT 10]", - "[SYSBOOT 11]", - "NC", - "NC", - "NC", - "NC", - "P2.35 [AIN5]", - "P1.02 [AIN6]", - "P1.35 [PRU1.10]", - "P1.04 [PRU1.11]", - "[MMC0_DAT3]", - "[MMC0_DAT2]", - "[MMC0_DAT1]", - "[MMC0_DAT0]", - "[MMC0_CLK]", - "[MMC0_CMD]"; -}; - -&gpio3 { - gpio-line-names = - "NC", - "NC", - "NC", - "NC", - "NC", - "[I2C0_SDA]", - "[I2C0_SCL]", - "[JTAG EMU0]", - "[JTAG EMU1]", - "NC", - "NC", - "NC", - "NC", - "P1.03 [USB1]", - "P1.36 [PWM0A]", - "P1.33 [PRU0.1]", - "P2.32 [PRU0.2]", - "P2.30 [PRU0.3]", - "P1.31 [PRU0.4]", - "P2.34 [PRU0.5]", - "P2.28 [PRU0.6]", - "P1.29 [PRU0.7]", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; - -&am33xx_pinmux { - - compatible = "pinconf-single"; - pinctrl-names = "default"; - - pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio - &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio - &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio - &P2_17_gpio >; - - /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ - P2_03_gpio: P2-03-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ - P1_34_gpio: P1-34-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ - P2_19_gpio: P2-19-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ - P2_24_gpio: P2-24-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ - P2_33_gpio: P2-33-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ - P2_22_gpio: P2-22-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ - P2_18_gpio: P2-18-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ - P2_10_gpio: P2-10-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ - P2_06_gpio: P2-06-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ - P2_04_gpio: P2-04-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ - P2_02_gpio: P2-02-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ - P2_08_gpio: P2-08-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>; - }; - - /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ - P2_17_gpio: P2-17-gpio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) - >; - pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; - pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; - }; - - i2c2_pins: pinmux-i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - >; - }; - - ehrpwm0_pins: pinmux-ehrpwm0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ - >; - }; - - ehrpwm1_pins: pinmux-ehrpwm1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ - >; - }; - - mmc0_pins: pinmux-mmc0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - spi0_pins: pinmux-spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - spi1_pins: pinmux-spi1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ - >; - }; - - usr_leds_pins: pinmux-usr-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - >; - }; - - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart4_pins: pinmux-uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ - >; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ehrpwm0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm0_pins>; -}; - -&epwmss1 { - status = "okay"; -}; - -&ehrpwm1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&rtc { - system-power-controller; -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - ti,chan-step-avg = <16 16 16 16 16 16 16 16>; - ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; - ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - status = "okay"; -}; - -&usb0 { - dr_mode = "otg"; -}; - -&usb1 { - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/am335x-regor-rdk.dts b/arch/arm/boot/dts/am335x-regor-rdk.dts deleted file mode 100644 index 66a1360b83d5..000000000000 --- a/arch/arm/boot/dts/am335x-regor-rdk.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-regor.dtsi" - -/* SoM */ -&gpmc { - status = "okay"; -}; - -&i2c_eeprom { - status = "okay"; -}; - -&serial_flash { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/am335x-regor.dtsi deleted file mode 100644 index 625db3bcd365..000000000000 --- a/arch/arm/boot/dts/am335x-regor.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - */ - -/ { - model = "Phytec AM335x phyBOARD-REGOR"; - compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; - - vcc3v3: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - /* User IO */ - user_leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - run_stop-led { - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - error-led { - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - }; -}; - -/* User Leds */ -&am33xx_pinmux { - user_leds_pins: pinmux-user-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ - >; - }; -}; - -/* CAN Busses */ -&am33xx_pinmux { - dcan1_pins: pinmux-dcan1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: pinmux-ethernet1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ - >; - }; -}; - -&cpsw_port2 { - status = "okay"; - phy-handle = <&phy1>; - phy-mode = "mii"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; -}; - -/* GPIOs */ -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&user_gpios_pins>; - - user_gpios_pins: pinmux-user-gpios-pins { - pinctrl-single,pins = < - /* DIGIN 1-4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ - /* DIGOUT 1-4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ - >; - }; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux-mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* RTC */ -&i2c_rtc { - status = "okay"; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart2_pins: pinmux-uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -/* RS485 - UART1 */ -&am33xx_pinmux { - uart1_rs485_pins: pinmux-uart1-rs485-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_rs485_pins>; - status = "okay"; - linux,rs485-enabled-at-boot-time; -}; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi deleted file mode 100644 index a138eb356874..000000000000 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&am33xx_pinmux { - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb_hub_ctrl: usb-hub-ctrl-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ - >; - }; -}; - -&mac_sw { - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&cpsw_port1 { - phy-mode = "rgmii-id"; -}; - -&i2c0 { - usb2512b: usb-hub@2c { - pinctrl-names = "default"; - pinctrl-0 = <&usb_hub_ctrl>; - compatible = "microchip,usb2512b"; - reg = <0x2c>; - reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts deleted file mode 100644 index 5522759def26..000000000000 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2021 Sancloud Ltd - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-sancloud-bbe-common.dtsi" -#include - -/ { - model = "SanCloud BeagleBone Enhanced Extended WiFi"; - compatible = "sancloud,am335x-boneenhanced", - "ti,am335x-bone-black", - "ti,am335x-bone", - "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - }; -}; - -&am33xx_pinmux { - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - /* gpmc_a9.gpio1_25: RADIO_EN */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) - - /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_clk.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) - >; - }; - - bluetooth_pins: bluetooth-pins { - pinctrl-single,pins = < - /* event_intr0.gpio0_19 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - /* uart1_rxd */ - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - - /* uart1_txd */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - - /* uart1_ctsn */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* uart1_rtsn */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&i2c2 { - status = "disabled"; -}; - -&mmc3 { - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - ti,needs-special-hs-handling; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - clock-frequency = <50000000>; - max-frequency = <50000000>; -}; - -&uart1 { - status = "okay"; - - bluetooth { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins &bluetooth_pins>; - compatible = "qcom,qca6174-bt"; - enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; - interrupt-parent = <&gpio0>; - interrupts = <19 IRQ_TYPE_EDGE_RISING>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts deleted file mode 100644 index b1b400226d83..000000000000 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2021 SanCloud Ltd - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-sancloud-bbe-common.dtsi" - -/ { - model = "SanCloud BeagleBone Enhanced Lite"; - compatible = "sancloud,am335x-boneenhanced", - "ti,am335x-bone-black", - "ti,am335x-bone", - "ti,am33xx"; -}; - -&am33xx_pinmux { - bb_spi0_pins: bb-spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) - >; - }; -}; - -&spi0 { - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&bb_spi0_pins>; - - channel@0 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "micron,spi-authenta"; - - reg = <0>; - spi-max-frequency = <16000000>; - spi-cpha; - }; -}; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts deleted file mode 100644 index 32669346cefe..000000000000 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-boneblack-hdmi.dtsi" -#include "am335x-sancloud-bbe-common.dtsi" -#include - -/ { - model = "SanCloud BeagleBone Enhanced"; - compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&am33xx_pinmux { - mpu6050_pins: mpu6050-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - >; - }; - - lps3331ap_pins: lps3331ap-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; -}; - -&i2c0 { - lps331ap: barometer@5c { - pinctrl-names = "default"; - pinctrl-0 = <&lps3331ap_pins>; - compatible = "st,lps331ap-press"; - st,drdy-int-pin = <1>; - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - }; - - mpu6050: accelerometer@68 { - pinctrl-names = "default"; - pinctrl-0 = <&mpu6050_pins>; - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - orientation = <0xff 0 0 0 1 0 0 0 0xff>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts deleted file mode 100644 index 596774c84744..000000000000 --- a/arch/arm/boot/dts/am335x-sbc-t335.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 - * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ - */ - -#include "am335x-cm-t335.dts" - -/ { - model = "CompuLab CM-T335 on SB-T335"; - compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"; - - /* DRM display driver */ - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - /* Timing selection performed by U-Boot */ - timing0: lcd {/* 800x480p62 */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - timing1: dvi { /* 1024x768p60 */ - clock-frequency = <65000000>; - hactive = <1024>; - hfront-porch = <24>; - hback-porch = <160>; - hsync-len = <136>; - vactive = <768>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - /* Display */ - lcd_pins_default: lcd-default-pins { - pinctrl-single,pins = < - /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd-sleep-pins { - pinctrl-single,pins = < - /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; -}; - -&i2c0 { - /* GPIO extender */ - gpio_ext: pca9555@26 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x26>; - dvi-ena-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "dvi-enable"; - }; - lcd-ena-hog { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "lcd-enable"; - }; - }; -}; - -/* Display */ -&lcdc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts deleted file mode 100644 index 9297cb1efcd4..000000000000 --- a/arch/arm/boot/dts/am335x-shc.dts +++ /dev/null @@ -1,559 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * support for the bosch am335x based shc c3 board - * - * Copyright, C) 2015 Heiko Schocher - * - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "Bosch SHC"; - compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx"; - - aliases { - mmcblk0 = &mmc1; - mmcblk1 = &mmc2; - }; - - cpus { - cpu@0 { - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 594000 1225000 - 294000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ - cpu0-supply = <&dcdc2_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back-button { - label = "Back Button"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <1000>; - wakeup-source; - }; - - front-button { - label = "Front Button"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <1000>; - wakeup-source; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "shc:power:red"; - gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "shc:power:bl"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - default-state = "on"; - }; - - led3 { - label = "shc:lan:red"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led4 { - label = "shc:lan:bl"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "shc:cloud:red"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led6 { - label = "shc:cloud:bl"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&aes { - status = "okay"; -}; - -&epwmss1 { - status = "okay"; - - ehrpwm1: pwm@200 { - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; - status = "okay"; - }; -}; - -&gpio1 { - hmtc-rst-hog { - gpio-hog; - gpios = <24 GPIO_ACTIVE_LOW>; - output-high; - line-name = "homematic_reset"; - }; - - hmtc-prog-hog { - gpio-hog; - gpios = <27 GPIO_ACTIVE_LOW>; - output-high; - line-name = "homematic_program"; - }; -}; - -&gpio3 { - zgb-rst-hog { - gpio-hog; - gpios = <18 GPIO_ACTIVE_LOW>; - output-low; - line-name = "zigbee_reset"; - }; - - zgb-boot-hog { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "zigbee_boot"; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - at24@50 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&cpsw_port1 { - phy-mode = "mii"; - phy-handle = <ðernetphy0>; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethernetphy0: ethernet-phy@0 { - reg = <0>; - smsc,disable-energy-detect; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <0x4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - cd-inverted; - max-frequency = <26000000>; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - max-frequency = <26000000>; - sd-uhs-sdr25; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - bus-width = <4>; - cap-power-off-card; - max-frequency = <26000000>; - sd-uhs-sdr25; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&rtc { - ti,no-init; -}; - -&sham { - status = "okay"; -}; - -&tps { - compatible = "ti,tps65217"; - ti,pmic-shutdown-controller; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - dcdc1_reg: regulator@0 { - reg = <0>; - regulator-name = "vdds_dpr"; - regulator-compatible = "dcdc1"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1450000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - reg = <1>; - /* - * VDD_MPU voltage limits 0.95V - 1.26V with - * +/-4% tolerance - */ - regulator-compatible = "dcdc2"; - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <70000>; - }; - - dcdc3_reg: regulator@2 { - reg = <2>; - /* - * VDD_CORE voltage limits 0.95V - 1.1V with - * +/-4% tolerance - */ - regulator-name = "vdd_core"; - regulator-compatible = "dcdc3"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1125000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-name = "vio,vrtc,vdds"; - regulator-compatible = "ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-name = "vdd_3v3aux"; - regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - reg = <5>; - regulator-name = "vdd_1v8"; - regulator-compatible = "ldo3"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - reg = <6>; - regulator-name = "vdd_3v3a"; - regulator-compatible = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - clkout2_pin: clkout2-pins { - pinctrl-single,pins = < - /* xdma_event_intr1.clkout2 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - ehrpwm1_pins: ehrpwm1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ - >; - }; - - emmc_pins: emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) - >; - }; - - uart4_pins: uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) - >; - }; - - user_leds_s0: user-leds-s0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) - >; - }; -}; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts deleted file mode 100644 index d35ed80de0f0..000000000000 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ /dev/null @@ -1,721 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "Toby Churchill SL50 Series"; - compatible = "tcl,am335x-sl50", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led0 { - label = "sl50:red:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "sl50:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "sl50:red:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "sl50:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - backlight0: disp0 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight0_pins>; - pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_sys_reg>; - }; - - backlight1: disp1 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight1_pins>; - pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_sys_reg>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* audio external oscillator */ - audio_mclk_fixed: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; /* 24.576MHz */ - }; - - audio_mclk: audio_mclk_gate@0 { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&audio_mclk_pins>; - clocks = <&audio_mclk_fixed>; - enable-gpios = <&gpio1 27 0>; - }; - }; - - panel: lcd_panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - tft-alt-mode = <0>; - mono-8bit-mode = <0>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: 960x128 { - clock-frequency = <18000000>; - hactive = <960>; - vactive = <272>; - - hback-porch = <40>; - hfront-porch = <16>; - hsync-len = <24>; - hsync-active = <0>; - - vback-porch = <3>; - vfront-porch = <8>; - vsync-len = <4>; - vsync-active = <0>; - }; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "sound-card"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pa_pins>; - - widgets = "Headphone", "Headphone Jack", - "Speaker", "Speaker External", - "Line", "Line In", - "Microphone", "Microphone Jack"; - - routing = "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Amplifier", "MONO_LOUT", - "Speaker External", "Amplifier", - "LINE1R", "Line In", - "LINE1L", "Line In", - "MIC3L", "Microphone Jack", - "MIC3R", "Microphone Jack", - "Microphone Jack", "Mic Bias"; - - dais = <&cpu_port>; - - pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - }; - - emmc_pwrseq: pwrseq@0 { - compatible = "mmc-pwrseq-emmc"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pwrseq_pins>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; - - vdd_sys_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_sys_reg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&lwb_pins>; - - audio_pins: audio-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - >; - }; - - audio_pa_pins: audio-pa-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ - >; - }; - - audio_mclk_pins: audio-mclk-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - backlight0_pins: backlight0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ - >; - }; - - backlight1_pins: backlight1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ - >; - }; - - lcd_pins: lcd-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - led_pins: led-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - uart0_pins: uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart4_pins: uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - /* Ethernet */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ - >; - }; - - emmc_pwrseq_pins: emmc-pwrseq-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ - >; - }; - - emmc_pins: emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - - ehrpwm1_pins: ehrpwm1a-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ - >; - }; - - rtc0_irq_pins: rtc0-irq-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ - >; - }; - - spi0_pins: spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ - >; - }; - - lwb_pins: lwb-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ - /* PDI Bus - Battery system */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ - /* FPGA */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc0_irq_pins>; - interrupt-parent = <&gpio0>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ - wakeup-source; - trickle-resistor-ohms = <2000>; - reg = <0x68>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - gpio_exp: mcp23017@20 { - compatible = "microchip,mcp23017"; - reg = <0x20>; - }; - -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; - - audio_codec: tlv320aic3106@1b { - status = "okay"; - compatible = "ti,tlv320aic3106"; - #sound-dai-cells = <0>; - reg = <0x1b>; - ai3x-micbias-vg = <2>; /* 2.5V */ - - AVDD-supply = <&ldo4_reg>; - IOVDD-supply = <&ldo4_reg>; - DRVDD-supply = <&ldo4_reg>; - DVDD-supply = <&ldo3_reg>; - - codec_port: port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - clocks = <&audio_mclk>; - }; - }; - }; - - /* Ambient Light Sensor */ - als: isl29023@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - }; -}; - -&rtc { - status = "disabled"; -}; - -&usb0 { - dr_mode = "otg"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - vmmc-supply = <&vmmcsd_fixed>; - mmc-pwrseq = <&emmc_pwrseq>; -}; - -&mcasp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pins>; - #sound-dai-cells = <0>; - op-mode = <0>; /* MCASP_ISS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; - - cpu_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - - dai-format = "dsp_b"; - bitclock-master = <&codec_port>; - frame-master = <&codec_port>; - bitclock-inversion; - clocks = <&audio_mclk>; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - flash: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q032"; - reg = <1>; - spi-max-frequency = <5000000>; - }; -}; - -#include "tps65217.dtsi" - -&tps { - ti,pmic-shutdown-controller; - - interrupt-parent = <&intc>; - interrupts = <7>; /* NNMI */ - - regulators { - dcdc1_reg: regulator@0 { - /* VDDS_DDR */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* VRTC / VIO / VDDS*/ - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: regulator@4 { - /* VDD_3V3AUX */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3_reg: regulator@5 { - /* VDD_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* VDD_3V3A */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&cpsw_port1 { - phy-mode = "mii"; - phy-handle = <ðphy0>; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&mac_sw { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - reset-delay-us = <100>; /* PHY datasheet states 100us min */ - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&epwmss1 { - status = "okay"; -}; - -&ehrpwm1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; -}; - -&lcdc { - status = "okay"; -}; - -&tscadc { - status = "okay"; -}; - -&am335x_adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; -}; diff --git a/arch/arm/boot/dts/am335x-wega-rdk.dts b/arch/arm/boot/dts/am335x-wega-rdk.dts deleted file mode 100644 index 866b5f0cbfbc..000000000000 --- a/arch/arm/boot/dts/am335x-wega-rdk.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-wega.dtsi" - -/* SoM */ -&gpmc { - status = "okay"; -}; - -&i2c_eeprom { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi deleted file mode 100644 index cb27ff464dbe..000000000000 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - */ - -/ { - model = "Phytec AM335x phyBOARD-WEGA"; - compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "snd-wega"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_iface_main>; - simple-audio-card,frame-master = <&sound_iface_main>; - simple-audio-card,mclk-fs = <32>; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "Speaker", "SPOP", - "Speaker", "SPOM", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - }; - - sound_iface_main: simple-audio-card,codec { - sound-dai = <&tlv320aic3007>; - clocks = <&mcasp0_fck>; - }; - - }; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -/* Audio */ -&am33xx_pinmux { - mcasp0_pins: pinmux-mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&i2c0 { - tlv320aic3007: tlv320aic3007@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - AVDD-supply = <&vcc3v3>; - IOVDD-supply = <&vcc3v3>; - DRVDD-supply = <&vcc3v3>; - DVDD-supply = <&vdig1_reg>; - status = "okay"; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < - 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ - >; - tx-num-evt = <16>; - rx-num-evt = <16>; - status = "okay"; -}; - - -/* CAN Busses */ -&am33xx_pinmux { - dcan1_pins: pinmux-dcan1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: pinmux-ethernet1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ - >; - }; -}; - -&cpsw_port2 { - status = "okay"; - phy-handle = <&phy1>; - phy-mode = "mii"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux-mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* Power */ -&vdig1_reg { - regulator-boot-on; - regulator-always-on; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux-uart1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi deleted file mode 100644 index d34483ae1778..000000000000 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ /dev/null @@ -1,779 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM33xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - sys_clkin_ck: clock-sys-clkin-22@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sys_clkin_ck"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: clock-adc-tsc-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "adc_tsc_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: clock-dcan0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dcan0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: clock-dcan1-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dcan1_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: clock-mcasp0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mcasp0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: clock-mcasp1-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mcasp1_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: clock-smartreflex0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "smartreflex0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: clock-smartreflex1-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "smartreflex1_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: clock-sha0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "sha0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: clock-aes0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "aes0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: clock-rng-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "rng_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - clock@664 { - compatible = "ti,clksel"; - reg = <0x664>; - #clock-cells = <2>; - #address-cells = <0>; - - ehrpwm0_tbclk: clock-ehrpwm0-tbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm0_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - }; - - ehrpwm1_tbclk: clock-ehrpwm1-tbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm1_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - }; - - ehrpwm2_tbclk: clock-ehrpwm2-tbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm2_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - }; - }; -}; -&prcm_clocks { - clk_32768_ck: clock-clk-32768 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "clk_32768_ck"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clock-clk-rc32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "clk_rc32k_ck"; - clock-frequency = <32000>; - }; - - virt_19200000_ck: clock-virt-19200000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_19200000_ck"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: clock-virt-24000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_24000000_ck"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: clock-virt-25000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_25000000_ck"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: clock-virt-26000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_26000000_ck"; - clock-frequency = <26000000>; - }; - - tclkin_ck: clock-tclkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "tclkin_ck"; - clock-frequency = <12000000>; - }; - - dpll_core_ck: clock@490 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clock-output-names = "dpll_core_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; - }; - - dpll_core_x2_ck: clock-dpll-core-x2 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clock-output-names = "dpll_core_x2_ck"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: clock-dpll-core-m4@480 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m4_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0480>; - ti,index-starts-at-one; - }; - - dpll_core_m5_ck: clock-dpll-core-m5@484 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m5_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0484>; - ti,index-starts-at-one; - }; - - dpll_core_m6_ck: clock-dpll-core-m6@4d8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m6_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x04d8>; - ti,index-starts-at-one; - }; - - dpll_mpu_ck: clock@488 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clock-output-names = "dpll_mpu_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; - }; - - dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_mpu_m2_ck"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x04a8>; - ti,index-starts-at-one; - }; - - dpll_ddr_ck: clock@494 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-clock"; - clock-output-names = "dpll_ddr_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; - }; - - dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_ddr_m2_ck"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - reg = <0x04a0>; - ti,index-starts-at-one; - }; - - dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_ddr_m2_div2_ck"; - clocks = <&dpll_ddr_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_disp_ck: clock@498 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-clock"; - clock-output-names = "dpll_disp_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; - }; - - dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_disp_m2_ck"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - reg = <0x04a4>; - ti,index-starts-at-one; - ti,set-rate-parent; - }; - - dpll_per_ck: clock@48c { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-j-type-clock"; - clock-output-names = "dpll_per_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; - }; - - dpll_per_m2_ck: clock-dpll-per-m2@4ac { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2_ck"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x04ac>; - ti,index-starts-at-one; - }; - - dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_per_m2_div4_ck"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - clk_24mhz: clock-clk-24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "clk_24mhz"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clock-clkdiv32k { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "clkdiv32k_ck"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - l3_gclk: clock-l3-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l3_gclk"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "pruss_ocp_gclk"; - clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; - reg = <0x0530>; - }; - - mmu_fck: clock-mmu-fck-1@914 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "mmu_fck"; - clocks = <&dpll_core_m4_ck>; - ti,bit-shift = <1>; - reg = <0x0914>; - }; - - timer1_fck: clock-timer1-fck@528 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer1_fck"; - clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; - reg = <0x0528>; - }; - - timer2_fck: clock-timer2-fck@508 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer2_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0508>; - }; - - timer3_fck: clock-timer3-fck@50c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer3_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x050c>; - }; - - timer4_fck: clock-timer4-fck@510 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer4_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0510>; - }; - - timer5_fck: clock-timer5-fck@518 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer5_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0518>; - }; - - timer6_fck: clock-timer6-fck@51c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer6_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x051c>; - }; - - timer7_fck: clock-timer7-fck@504 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer7_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0504>; - }; - - usbotg_fck: clock-usbotg-fck-8@47c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usbotg_fck"; - clocks = <&dpll_per_ck>; - ti,bit-shift = <8>; - reg = <0x047c>; - }; - - dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_core_m4_div2_ck"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - ieee5000_fck: clock-ieee5000-fck-1@e4 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ieee5000_fck"; - clocks = <&dpll_core_m4_div2_ck>; - ti,bit-shift = <1>; - reg = <0x00e4>; - }; - - wdt1_fck: clock-wdt1-fck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "wdt1_fck"; - clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0538>; - }; - - l4_rtc_gclk: clock-l4-rtc-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4_rtc_gclk"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: clock-l4hs-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4hs_gclk"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: clock-l3s-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l3s_gclk"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4fw_gclk: clock-l4fw-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4fw_gclk"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: clock-l4ls-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4ls_gclk"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sysclk_div_ck: clock-sysclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "sysclk_div_ck"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "cpsw_125mhz_gclk"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "cpsw_cpts_rft_clk"; - clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; - reg = <0x0520>; - }; - - gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gpio0_dbclk_mux_ck"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x053c>; - }; - - lcd_gclk: clock-lcd-gclk@534 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "lcd_gclk"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x0534>; - ti,set-rate-parent; - }; - - mmc_clk: clock-mmc { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mmc_clk"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - clock@52c { - compatible = "ti,clksel"; - reg = <0x52c>; - #clock-cells = <2>; - #address-cells = <0>; - - gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gfx_fclk_clksel_ck"; - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - }; - - gfx_fck_div_ck: clock-gfx-fck-div { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "gfx_fck_div_ck"; - clocks = <&gfx_fclk_clksel_ck>; - ti,max-div = <2>; - }; - }; - - clock@700 { - compatible = "ti,clksel"; - reg = <0x700>; - #clock-cells = <2>; - #address-cells = <0>; - - sysclkout_pre_ck: clock-sysclkout-pre { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sysclkout_pre_ck"; - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; - }; - - clkout2_div_ck: clock-clkout2-div { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "clkout2_div_ck"; - clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - }; - - clkout2_ck: clock-clkout2 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "clkout2_ck"; - clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; - }; - }; -}; - -&prcm { - per_cm: clock@0 { - compatible = "ti,omap4-cm"; - clock-output-names = "per_cm"; - reg = <0x0 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x400>; - - l4ls_clkctrl: clock@38 { - compatible = "ti,clkctrl"; - clock-output-names = "l4ls_clkctrl"; - reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; - #clock-cells = <2>; - }; - - l3s_clkctrl: clock@1c { - compatible = "ti,clkctrl"; - clock-output-names = "l3s_clkctrl"; - reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; - #clock-cells = <2>; - }; - - l3_clkctrl: clock@24 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_clkctrl"; - reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; - #clock-cells = <2>; - }; - - l4hs_clkctrl: clock@120 { - compatible = "ti,clkctrl"; - clock-output-names = "l4hs_clkctrl"; - reg = <0x120 0x4>; - #clock-cells = <2>; - }; - - pruss_ocp_clkctrl: clock@e8 { - compatible = "ti,clkctrl"; - clock-output-names = "pruss_ocp_clkctrl"; - reg = <0xe8 0x4>; - #clock-cells = <2>; - }; - - cpsw_125mhz_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "cpsw_125mhz_clkctrl"; - reg = <0x0 0x18>; - #clock-cells = <2>; - }; - - lcdc_clkctrl: clock@18 { - compatible = "ti,clkctrl"; - clock-output-names = "lcdc_clkctrl"; - reg = <0x18 0x4>; - #clock-cells = <2>; - }; - - clk_24mhz_clkctrl: clock@14c { - compatible = "ti,clkctrl"; - clock-output-names = "clk_24mhz_clkctrl"; - reg = <0x14c 0x4>; - #clock-cells = <2>; - }; - }; - - wkup_cm: clock@400 { - compatible = "ti,omap4-cm"; - clock-output-names = "wkup_cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - l4_wkup_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_wkup_clkctrl"; - reg = <0x0 0x10>, <0xb4 0x24>; - #clock-cells = <2>; - }; - - l3_aon_clkctrl: clock@14 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_aon_clkctrl"; - reg = <0x14 0x4>; - #clock-cells = <2>; - }; - - l4_wkup_aon_clkctrl: clock@b0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_wkup_aon_clkctrl"; - reg = <0xb0 0x4>; - #clock-cells = <2>; - }; - }; - - mpu_cm: clock@600 { - compatible = "ti,omap4-cm"; - clock-output-names = "mpu_cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - mpu_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "mpu_clkctrl"; - reg = <0x0 0x8>; - #clock-cells = <2>; - }; - }; - - l4_rtc_cm: clock@800 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_rtc_cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l4_rtc_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_rtc_clkctrl"; - reg = <0x0 0x4>; - #clock-cells = <2>; - }; - }; - - gfx_l3_cm: clock@900 { - compatible = "ti,omap4-cm"; - clock-output-names = "gfx_l3_cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - gfx_l3_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "gfx_l3_clkctrl"; - reg = <0x0 0x8>; - #clock-cells = <2>; - }; - }; - - l4_cefuse_cm: clock@a00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_cefuse_cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - l4_cefuse_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_cefuse_clkctrl"; - reg = <0x0 0x24>; - #clock-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi deleted file mode 100644 index 7e50fe633d8a..000000000000 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ /dev/null @@ -1,2322 +0,0 @@ -&l4_wkup { /* 0x44c00000 */ - compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; - power-domains = <&prm_wkup>; - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x44c00000 0x800>, - <0x44c00800 0x800>, - <0x44c01000 0x400>, - <0x44c01400 0x400>; - reg-names = "ap", "la", "ia0", "ia1"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ - <0x00100000 0x44d00000 0x100000>, /* segment 1 */ - <0x00200000 0x44e00000 0x100000>; /* segment 2 */ - - segment@0 { /* 0x44c00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>; /* ap 3 */ - }; - - segment@100000 { /* 0x44d00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ - <0x00004000 0x00104000 0x001000>, /* ap 5 */ - <0x00080000 0x00180000 0x002000>, /* ap 6 */ - <0x00082000 0x00182000 0x001000>; /* ap 7 */ - - target-module@0 { /* 0x44d00000, ap 4 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x0 0x4>; - reg-names = "rev"; - clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x4000>, - <0x00080000 0x00080000 0x2000>; - - wkup_m3: cpu@0 { - compatible = "ti,am3352-wkup-m3"; - reg = <0x00000000 0x4000>, - <0x00080000 0x2000>; - reg-names = "umem", "dmem"; - resets = <&prm_wkup 3>; - reset-names = "rstctrl"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - }; - }; - - segment@200000 { /* 0x44e00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ - <0x00002000 0x00202000 0x001000>, /* ap 9 */ - <0x00003000 0x00203000 0x001000>, /* ap 10 */ - <0x00004000 0x00204000 0x001000>, /* ap 11 */ - <0x00005000 0x00205000 0x001000>, /* ap 12 */ - <0x00006000 0x00206000 0x001000>, /* ap 13 */ - <0x00007000 0x00207000 0x001000>, /* ap 14 */ - <0x00008000 0x00208000 0x001000>, /* ap 15 */ - <0x00009000 0x00209000 0x001000>, /* ap 16 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ - <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ - <0x00010000 0x00210000 0x010000>, /* ap 22 */ - <0x00020000 0x00220000 0x010000>, /* ap 23 */ - <0x00030000 0x00230000 0x001000>, /* ap 24 */ - <0x00031000 0x00231000 0x001000>, /* ap 25 */ - <0x00032000 0x00232000 0x001000>, /* ap 26 */ - <0x00033000 0x00233000 0x001000>, /* ap 27 */ - <0x00034000 0x00234000 0x001000>, /* ap 28 */ - <0x00035000 0x00235000 0x001000>, /* ap 29 */ - <0x00036000 0x00236000 0x001000>, /* ap 30 */ - <0x00037000 0x00237000 0x001000>, /* ap 31 */ - <0x00038000 0x00238000 0x001000>, /* ap 32 */ - <0x00039000 0x00239000 0x001000>, /* ap 33 */ - <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ - <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ - <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ - <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ - <0x00040000 0x00240000 0x040000>, /* ap 38 */ - <0x00080000 0x00280000 0x001000>; /* ap 39 */ - - target-module@0 { /* 0x44e00000, ap 8 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x2000>; - - prcm: prcm@0 { - compatible = "ti,am3-prcm", "simple-bus"; - reg = <0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - }; - - target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - - target-module@5000 { /* 0x44e05000, ap 12 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - }; - - gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7000 0x4>, - <0x7010 0x4>, - <0x7114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, - <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - - gpio0: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-ranges = <&am33xx_pinmux 0 82 8>, - <&am33xx_pinmux 8 52 4>, - <&am33xx_pinmux 12 94 4>, - <&am33xx_pinmux 16 71 2>, - <&am33xx_pinmux 18 135 1>, - <&am33xx_pinmux 19 108 2>, - <&am33xx_pinmux 21 73 1>, - <&am33xx_pinmux 22 8 2>, - <&am33xx_pinmux 26 10 2>, - <&am33xx_pinmux 28 74 1>, - <&am33xx_pinmux 29 81 1>, - <&am33xx_pinmux 30 28 2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <96>; - }; - }; - - target-module@9000 { /* 0x44e09000, ap 16 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9050 0x4>, - <0x9054 0x4>, - <0x9058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9000 0x1000>; - - uart0: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <72>; - status = "disabled"; - dmas = <&edma 26 0>, <&edma 27 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xb000 0x8>, - <0xb010 0x8>, - <0xb090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb000 0x1000>; - - i2c0: i2c@0 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1000>; - interrupts = <70>; - status = "disabled"; - }; - }; - - target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd000 0x4>, - <0xd010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x0000d000 0x00001000>, - <0x00001000 0x0000e000 0x00001000>; - - tscadc: tscadc@0 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x1000>; - interrupts = <16>; - clocks = <&adc_tsc_fck>; - clock-names = "fck"; - status = "disabled"; - dmas = <&edma 53 0>, <&edma 57 0>; - dma-names = "fifo0", "fifo1"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - am335x_adc: adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - }; - - target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x10000 0x4>; - reg-names = "rev"; - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x00010000>, - <0x00010000 0x00020000 0x00010000>; - - scm: scm@0 { - compatible = "ti,am3-scm", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0 0x2000>; - - am33xx_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x238>; - #pinctrl-cells = <2>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,am3352-phy-gmii-sel"; - reg = <0x650 0x4>; - #phy-cells = <2>; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb_ctrl_mod: control@620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x620 0x10>, - <0x648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am3352-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; - }; - - timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x31000 0x4>, - <0x31010 0x4>, - <0x31014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x31000 0x1000>; - - timer1: timer@0 { - compatible = "ti,am335x-timer-1ms"; - reg = <0x0 0x400>; - interrupts = <67>; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - }; - - target-module@33000 { /* 0x44e33000, ap 27 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x33000 0x1000>; - }; - - target-module@35000 { /* 0x44e35000, ap 29 50.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x35000 0x4>, - <0x35010 0x4>, - <0x35014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x35000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap3-wdt"; - reg = <0x0 0x1000>; - interrupts = <91>; - }; - }; - - target-module@37000 { /* 0x44e37000, ap 31 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x37000 0x1000>; - }; - - target-module@39000 { /* 0x44e39000, ap 33 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x39000 0x1000>; - }; - - target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x3e074 0x4>, - <0x3e078 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ - power-domains = <&prm_rtc>; - clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - rtc: rtc@0 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x0 0x1000>; - interrupts = <75 - 76>; - }; - }; - - target-module@40000 { /* 0x44e40000, ap 38 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x40000>; - }; - }; -}; - -&l4_fw { /* 0x47c00000 */ - compatible = "ti,am33xx-l4-fw", "simple-bus"; - reg = <0x47c00000 0x800>, - <0x47c00800 0x800>, - <0x47c01000 0x400>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ - - segment@0 { /* 0x47c00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ - <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ - <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ - <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ - <0x00010000 0x00010000 0x001000>, /* ap 7 */ - <0x00011000 0x00011000 0x001000>, /* ap 8 */ - <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ - <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ - <0x00024000 0x00024000 0x001000>, /* ap 11 */ - <0x00025000 0x00025000 0x001000>, /* ap 12 */ - <0x00026000 0x00026000 0x001000>, /* ap 13 */ - <0x00027000 0x00027000 0x001000>, /* ap 14 */ - <0x00030000 0x00030000 0x001000>, /* ap 15 */ - <0x00031000 0x00031000 0x001000>, /* ap 16 */ - <0x00038000 0x00038000 0x001000>, /* ap 17 */ - <0x00039000 0x00039000 0x001000>, /* ap 18 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ - <0x00040000 0x00040000 0x001000>, /* ap 24 */ - <0x00046000 0x00046000 0x001000>, /* ap 25 */ - <0x00047000 0x00047000 0x001000>, /* ap 26 */ - <0x00044000 0x00044000 0x001000>, /* ap 27 */ - <0x00045000 0x00045000 0x001000>, /* ap 28 */ - <0x00028000 0x00028000 0x001000>, /* ap 29 */ - <0x00029000 0x00029000 0x001000>, /* ap 30 */ - <0x00032000 0x00032000 0x001000>, /* ap 31 */ - <0x00033000 0x00033000 0x001000>, /* ap 32 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ - <0x00041000 0x00041000 0x001000>, /* ap 34 */ - <0x00042000 0x00042000 0x001000>, /* ap 35 */ - <0x00043000 0x00043000 0x001000>, /* ap 36 */ - <0x00014000 0x00014000 0x001000>, /* ap 37 */ - <0x00015000 0x00015000 0x001000>; /* ap 38 */ - - target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - }; - - target-module@10000 { /* 0x47c10000, ap 7 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@24000 { /* 0x47c24000, ap 11 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x47c26000, ap 13 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x47c28000, ap 29 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@30000 { /* 0x47c30000, ap 15 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - }; - - target-module@32000 { /* 0x47c32000, ap 31 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - }; - - target-module@38000 { /* 0x47c38000, ap 17 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>; - }; - - target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>; - }; - - target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>; - }; - - target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - }; - - target-module@40000 { /* 0x47c40000, ap 24 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - }; - - target-module@42000 { /* 0x47c42000, ap 35 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - }; - - target-module@44000 { /* 0x47c44000, ap 27 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - }; - - target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - }; - }; -}; - -&l4_fast { /* 0x4a000000 */ - compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; - power-domains = <&prm_per>; - clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x400>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00100000 0x00100000 0x008000>, /* ap 3 */ - <0x00108000 0x00108000 0x001000>, /* ap 4 */ - <0x00180000 0x00180000 0x020000>, /* ap 5 */ - <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ - <0x00200000 0x00200000 0x080000>, /* ap 7 */ - <0x00280000 0x00280000 0x001000>, /* ap 8 */ - <0x00300000 0x00300000 0x080000>, /* ap 9 */ - <0x00380000 0x00380000 0x001000>; /* ap 10 */ - - target-module@100000 { /* 0x4a100000, ap 3 08.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x101200 0x4>, - <0x101208 0x4>, - <0x101204 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x8000>; - - mac: ethernet@0 { - compatible = "ti,am335x-cpsw","ti,cpsw"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x0 0x800 - 0x1200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges = <0 0 0x8000>; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - status = "disabled"; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 1>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 1>; - }; - }; - - mac_sw: switch@0 { - compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; - reg = <0x0 0x4000>; - ranges = <0 0 0x4000>; - clocks = <&cpsw_125mhz_gclk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - syscon = <&scm_conf>; - status = "disabled"; - - interrupts = <40 41 42 43>; - interrupt-names = "rx_thresh", "rx", "tx", "misc"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - label = "port1"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 1>; - }; - - cpsw_port2: port@2 { - reg = <2>; - label = "port2"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 1>; - }; - }; - - davinci_mdio_sw: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&cpsw_125mhz_gclk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpts { - clocks = <&cpsw_cpts_rft_clk>; - clock-names = "cpts"; - }; - }; - }; - - target-module@180000 { /* 0x4a180000, ap 5 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x180000 0x20000>; - }; - - target-module@200000 { /* 0x4a200000, ap 7 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x200000 0x80000>; - }; - - pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ - compatible = "ti,sysc-pruss", "ti,sysc"; - reg = <0x326000 0x4>, - <0x326004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | - SYSC_PRUSS_SUB_MWAIT)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_per 1>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x300000 0x80000>; - status = "disabled"; - - pruss: pruss@0 { - compatible = "ti,am3356-pruss"; - reg = <0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pruss_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x3000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - pruss_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - pruss_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&l3_gclk>, /* icss_iep_gclk */ - <&pruss_ocp_gclk>; /* icss_ocp_gclk */ - }; - }; - }; - - pruss_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x58>; - }; - - pruss_intc: interrupt-controller@20000 { - compatible = "ti,pruss-intc"; - reg = <0x20000 0x2000>; - interrupts = <20 21 22 23 24 25 26 27>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - interrupt-controller; - #interrupt-cells = <3>; - }; - - pru0: pru@34000 { - compatible = "ti,am3356-pru"; - reg = <0x34000 0x2000>, - <0x22000 0x400>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am335x-pru0-fw"; - }; - - pru1: pru@38000 { - compatible = "ti,am3356-pru"; - reg = <0x38000 0x2000>, - <0x24000 0x400>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am335x-pru1-fw"; - }; - - pruss_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x90>; - clocks = <&dpll_core_m4_ck>; - clock-names = "fck"; - bus_freq = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - }; - }; -}; - -&l4_mpuss { /* 0x4b140000 */ - compatible = "ti,am33xx-l4-mpuss", "simple-bus"; - reg = <0x4b144400 0x100>, - <0x4b144800 0x400>; - reg-names = "la", "ap"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ - - segment@0 { /* 0x4b140000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00002000 0x00002000 0x001000>, /* ap 2 */ - <0x00004000 0x00004000 0x000400>, /* ap 3 */ - <0x00005000 0x00005000 0x000400>, /* ap 4 */ - <0x00000000 0x00000000 0x001000>, /* ap 5 */ - <0x00003000 0x00003000 0x001000>, /* ap 6 */ - <0x00000800 0x00000800 0x000800>; /* ap 7 */ - - target-module@0 { /* 0x4b140000, ap 5 02.2 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00001000>, - <0x00001000 0x00001000 0x00001000>, - <0x00002000 0x00002000 0x00001000>; - }; - - target-module@3000 { /* 0x4b143000, ap 6 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,am33xx-l4-per", "simple-pm-bus"; - power-domains = <&prm_per>; - clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ - <0x00100000 0x48100000 0x100000>, /* segment 1 */ - <0x00200000 0x48200000 0x100000>, /* segment 2 */ - <0x00300000 0x48300000 0x100000>, /* segment 3 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>, /* ap 3 */ - <0x00001800 0x00001800 0x000400>, /* ap 4 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ - <0x00008000 0x00008000 0x001000>, /* ap 6 */ - <0x00009000 0x00009000 0x001000>, /* ap 7 */ - <0x00016000 0x00016000 0x001000>, /* ap 8 */ - <0x00017000 0x00017000 0x001000>, /* ap 9 */ - <0x00022000 0x00022000 0x001000>, /* ap 10 */ - <0x00023000 0x00023000 0x001000>, /* ap 11 */ - <0x00024000 0x00024000 0x001000>, /* ap 12 */ - <0x00025000 0x00025000 0x001000>, /* ap 13 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ - <0x00038000 0x00038000 0x002000>, /* ap 16 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ - <0x00014000 0x00014000 0x001000>, /* ap 18 */ - <0x00015000 0x00015000 0x001000>, /* ap 19 */ - <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ - <0x00040000 0x00040000 0x001000>, /* ap 22 */ - <0x00041000 0x00041000 0x001000>, /* ap 23 */ - <0x00042000 0x00042000 0x001000>, /* ap 24 */ - <0x00043000 0x00043000 0x001000>, /* ap 25 */ - <0x00044000 0x00044000 0x001000>, /* ap 26 */ - <0x00045000 0x00045000 0x001000>, /* ap 27 */ - <0x00046000 0x00046000 0x001000>, /* ap 28 */ - <0x00047000 0x00047000 0x001000>, /* ap 29 */ - <0x00048000 0x00048000 0x001000>, /* ap 30 */ - <0x00049000 0x00049000 0x001000>, /* ap 31 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ - <0x00050000 0x00050000 0x002000>, /* ap 34 */ - <0x00052000 0x00052000 0x001000>, /* ap 35 */ - <0x00060000 0x00060000 0x001000>, /* ap 36 */ - <0x00061000 0x00061000 0x001000>, /* ap 37 */ - <0x00080000 0x00080000 0x010000>, /* ap 38 */ - <0x00090000 0x00090000 0x001000>, /* ap 39 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ - <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ - <0x00030000 0x00030000 0x001000>, /* ap 77 */ - <0x00031000 0x00031000 0x001000>, /* ap 78 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ - <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ - <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ - <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ - <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ - <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ - <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - target-module@8000 { /* 0x48008000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@14000 { /* 0x48014000, ap 18 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x48016000, ap 8 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@22000 { /* 0x48022000, ap 10 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x22050 0x4>, - <0x22054 0x4>, - <0x22058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - uart1: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <73>; - status = "disabled"; - dmas = <&edma 28 0>, <&edma 29 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@24000 { /* 0x48024000, ap 12 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x24050 0x4>, - <0x24054 0x4>, - <0x24058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - uart2: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <74>; - status = "disabled"; - dmas = <&edma 30 0>, <&edma 31 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2a000 0x8>, - <0x2a010 0x8>, - <0x2a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1000>; - interrupts = <71>; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x48030000, ap 77 08.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x30000 0x4>, - <0x30110 0x4>, - <0x30114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - - spi0: spi@0 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x400>; - interrupts = <65>; - ti,spi-num-cs = <2>; - dmas = <&edma 16 0 - &edma 17 0 - &edma 18 0 - &edma 19 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - }; - - target-module@38000 { /* 0x48038000, ap 16 02.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x38000 0x4>, - <0x38004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x2000>, - <0x46000000 0x46000000 0x400000>; - - mcasp0: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - }; - - target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x2000>, - <0x46400000 0x46400000 0x400000>; - - mcasp1: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - }; - - timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>, - <0x40014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - timer2: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <68>; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - }; - - target-module@42000 { /* 0x48042000, ap 24 1c.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x42000 0x4>, - <0x42010 0x4>, - <0x42014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - timer3: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <69>; - }; - }; - - target-module@44000 { /* 0x48044000, ap 26 26.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x44000 0x4>, - <0x44010 0x4>, - <0x44014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - - timer4: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <92>; - ti,timer-pwm; - }; - }; - - target-module@46000 { /* 0x48046000, ap 28 28.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x46000 0x4>, - <0x46010 0x4>, - <0x46014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - - timer5: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <93>; - ti,timer-pwm; - }; - }; - - target-module@48000 { /* 0x48048000, ap 30 22.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x48000 0x4>, - <0x48010 0x4>, - <0x48014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - - timer6: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <94>; - ti,timer-pwm; - }; - }; - - target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x4a000 0x4>, - <0x4a010 0x4>, - <0x4a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - - timer7: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <95>; - ti,timer-pwm; - }; - }; - - target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4c000 0x4>, - <0x4c010 0x4>, - <0x4c114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-ranges = <&am33xx_pinmux 0 0 8>, - <&am33xx_pinmux 8 90 4>, - <&am33xx_pinmux 12 12 16>, - <&am33xx_pinmux 28 30 4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <98>; - }; - }; - - target-module@50000 { /* 0x48050000, ap 34 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000 0x2000>; - }; - - target-module@60000 { /* 0x48060000, ap 36 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x602fc 0x4>, - <0x60110 0x4>, - <0x60114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,am335-sdhci"; - ti,needs-special-reset; - dmas = <&edma 24 0>, <&edma 25 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48080000, ap 38 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x80000 0x4>, - <0x80010 0x4>, - <0x80014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0x2000>; - interrupts = <4>; - status = "disabled"; - }; - }; - - target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>; - }; - - target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc8000 0x4>, - <0xc8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = <77>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: mbox-wkup-m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - }; - - target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xca000 0x4>, - <0xca010 0x4>, - <0xca014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xca000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - - target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xcc000 0x1000>; - }; - }; - - segment@100000 { /* 0x48100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ - <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ - <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ - <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ - <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ - <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ - <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ - <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ - <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ - <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ - <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ - <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ - <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ - <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ - <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ - <0x000af000 0x001af000 0x001000>, /* ap 57 */ - <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ - <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ - <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ - <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ - <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ - <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ - <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ - <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ - <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ - <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ - <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ - <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ - <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ - <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ - - target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8c000 0x1000>; - }; - - target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8e000 0x1000>; - }; - - target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9c000 0x8>, - <0x9c010 0x8>, - <0x9c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - }; - - target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa0000 0x4>, - <0xa0110 0x4>, - <0xa0114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x1000>; - - spi1: spi@0 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x400>; - interrupts = <125>; - ti,spi-num-cs = <2>; - dmas = <&edma 42 0 - &edma 43 0 - &edma 44 0 - &edma 45 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - }; - - target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa4000 0x1000>; - }; - - target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa6050 0x4>, - <0xa6054 0x4>, - <0xa6058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa6000 0x1000>; - - uart3: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <44>; - status = "disabled"; - }; - }; - - target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa8050 0x4>, - <0xa8054 0x4>, - <0xa8058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x1000>; - - uart4: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <45>; - status = "disabled"; - }; - }; - - target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xaa050 0x4>, - <0xaa054 0x4>, - <0xaa058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xaa000 0x1000>; - - uart5: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <46>; - status = "disabled"; - }; - }; - - target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xac000 0x4>, - <0xac010 0x4>, - <0xac114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xac000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-ranges = <&am33xx_pinmux 0 34 18>, - <&am33xx_pinmux 18 77 4>, - <&am33xx_pinmux 22 56 10>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <32>; - }; - }; - - gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xae000 0x4>, - <0xae010 0x4>, - <0xae114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xae000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-ranges = <&am33xx_pinmux 0 66 5>, - <&am33xx_pinmux 5 98 2>, - <&am33xx_pinmux 7 75 2>, - <&am33xx_pinmux 13 141 1>, - <&am33xx_pinmux 14 100 8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <62>; - }; - }; - - target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb0000 0x10000>; - }; - - target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xcc020 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, - <&dcan0_fck>; - clock-names = "fck", "osc"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xcc000 0x2000>; - - dcan0: can@0 { - compatible = "ti,am3352-d_can"; - reg = <0x0 0x2000>; - clocks = <&dcan0_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = <52>; - status = "disabled"; - }; - }; - - target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd0020 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, - <&dcan1_fck>; - clock-names = "fck", "osc"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000 0x2000>; - - dcan1: can@0 { - compatible = "ti,am3352-d_can"; - reg = <0x0 0x2000>; - clocks = <&dcan1_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = <55>; - status = "disabled"; - }; - }; - - target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xd82fc 0x4>, - <0xd8110 0x4>, - <0xd8114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd8000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,am335-sdhci"; - ti,needs-special-reset; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00200000 0x010000>; - - target-module@0 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - power-domains = <&prm_mpu>; - clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x10000>; - - mpu@0 { - compatible = "ti,omap3-mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; - }; - }; - }; - - segment@300000 { /* 0x48300000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ - <0x00001000 0x00301000 0x001000>, /* ap 67 */ - <0x00002000 0x00302000 0x001000>, /* ap 68 */ - <0x00003000 0x00303000 0x001000>, /* ap 69 */ - <0x00004000 0x00304000 0x001000>, /* ap 70 */ - <0x00005000 0x00305000 0x001000>, /* ap 71 */ - <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ - <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ - <0x00018000 0x00318000 0x004000>, /* ap 74 */ - <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ - <0x00010000 0x00310000 0x002000>, /* ap 76 */ - <0x00012000 0x00312000 0x001000>, /* ap 93 */ - <0x00015000 0x00315000 0x001000>, /* ap 94 */ - <0x00016000 0x00316000 0x001000>, /* ap 95 */ - <0x00017000 0x00317000 0x001000>, /* ap 96 */ - <0x00013000 0x00313000 0x001000>, /* ap 97 */ - <0x00014000 0x00314000 0x001000>, /* ap 98 */ - <0x00020000 0x00320000 0x001000>, /* ap 99 */ - <0x00021000 0x00321000 0x001000>, /* ap 100 */ - <0x00022000 0x00322000 0x001000>, /* ap 101 */ - <0x00023000 0x00323000 0x001000>, /* ap 102 */ - <0x00024000 0x00324000 0x001000>, /* ap 103 */ - <0x00025000 0x00325000 0x001000>; /* ap 104 */ - - target-module@0 { /* 0x48300000, ap 66 48.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x0 0x4>, - <0x4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - epwmss0: epwmss@0 { - compatible = "ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap0: pwm@100 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - eqep0: counter@180 { - compatible = "ti,am3352-eqep"; - reg = <0x180 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "sysclkout"; - interrupts = <79>; - status = "disabled"; - }; - - ehrpwm0: pwm@200 { - compatible = "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@2000 { /* 0x48302000, ap 68 52.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - epwmss1: epwmss@0 { - compatible = "ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap1: pwm@100 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - eqep1: counter@180 { - compatible = "ti,am3352-eqep"; - reg = <0x180 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "sysclkout"; - interrupts = <88>; - status = "disabled"; - }; - - ehrpwm1: pwm@200 { - compatible = "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@4000 { /* 0x48304000, ap 70 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - epwmss2: epwmss@0 { - compatible = "ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap2: pwm@100 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - eqep2: counter@180 { - compatible = "ti,am3352-eqep"; - reg = <0x180 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "sysclkout"; - interrupts = <89>; - status = "disabled"; - }; - - ehrpwm2: pwm@200 { - compatible = "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xe000 0x4>, - <0xe054 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, lcdc_clkdm */ - clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - - lcdc: lcdc@0 { - compatible = "ti,am33xx-tilcdc"; - reg = <0x0 0x1000>; - interrupts = <36>; - status = "disabled"; - }; - }; - - target-module@10000 { /* 0x48310000, ap 76 4e.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x11fe0 0x4>, - <0x11fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = <111>; - }; - }; - - target-module@13000 { /* 0x48313000, ap 97 62.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x13000 0x1000>; - }; - - target-module@15000 { /* 0x48315000, ap 94 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00015000 0x00001000>, - <0x00001000 0x00016000 0x00001000>; - }; - - target-module@18000 { /* 0x48318000, ap 74 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x4000>; - }; - - target-module@20000 { /* 0x48320000, ap 99 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@22000 { /* 0x48322000, ap 101 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - }; - - target-module@24000 { /* 0x48324000, ap 103 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi deleted file mode 100644 index 32d397b3950b..000000000000 --- a/arch/arm/boot/dts/am33xx.dtsi +++ /dev/null @@ -1,714 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM33XX SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - compatible = "ti,am33xx"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - d-can0 = &dcan0; - d-can1 = &dcan1; - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - spi0 = &spi0; - spi1 = &spi1; - mmc0 = &mmc1; - mmc1 = &mmc2; - mmc2 = &mmc3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - enable-method = "ti,am3352"; - device_type = "cpu"; - reg = <0>; - - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - cpu-idle-states = <&mpu_gate>; - }; - - idle-states { - mpu_gate: mpu_gate { - compatible = "arm,idle-state"; - entry-latency-us = <40>; - exit-latency-us = <90>; - min-residency-us = <300>; - ti,idle-wkup-m3; - }; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - /* - * The three following nodes are marked with opp-suspend - * because the can not be enabled simultaneously on a - * single SoC. - */ - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0x06 0x0010>; - opp-suspend; - }; - - opp100-275000000 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0x00FF>; - opp-suspend; - }; - - opp100-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0020>; - opp-suspend; - }; - - opp100-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0040>; - }; - - opp120-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp120-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x06 0x0080>; - }; - - oppturbo-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - oppturbo-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x06 0x0100>; - }; - - oppnitro-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0x04 0x0200>; - }; - }; - - target-module@4b000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b000000 0x1000000>; - - target-module@140000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x140000 0xec0000>; - - pmu@0 { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - }; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - }; - - /* - * XXX: Use a flat representation of the AM33XX interconnect. - * The real AM33XX interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp: ocp { - compatible = "simple-pm-bus"; - power-domains = <&prm_per>; - clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l4_wkup: interconnect@44c00000 { - }; - l4_per: interconnect@48000000 { - }; - l4_fw: interconnect@47c00000 { - }; - l4_fast: interconnect@4a000000 { - }; - l4_mpuss: interconnect@4b140000 { - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,am33xx-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - target-module@49000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49000000 0x4>; - reg-names = "rev"; - clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49000000 0x10000>; - - edma: dma@0 { - compatible = "ti,edma3-tpcc"; - reg = <0 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - }; - - target-module@49800000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49800000 0x4>, - <0x49800010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49800000 0x100000>; - - edma_tptc0: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49900000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49900000 0x4>, - <0x49900010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49900000 0x100000>; - - edma_tptc1: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49a00000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49a00000 0x4>, - <0x49a00010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49a00000 0x100000>; - - edma_tptc2: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@47810000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x478102fc 0x4>, - <0x47810110 0x4>, - <0x47810114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47810000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,am335-sdhci"; - ti,needs-special-reset; - interrupts = <29>; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - - usb: target-module@47400000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x47400000 0x4>, - <0x47400010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47400000 0x8000>; - - usb0_phy: usb-phy@1300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x1300 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - - usb0: usb@1400 { - compatible = "ti,musb-am33xx"; - reg = <0x1400 0x400>, - <0x1000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1_phy: usb-phy@1b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x1b00 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - - usb1: usb@1800 { - compatible = "ti,musb-am33xx"; - reg = <0x1c00 0x400>, - <0x1800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@2000 { - compatible = "ti,am3359-cppi41"; - reg = <0x0000 0x1000>, - <0x2000 0x1000>, - <0x3000 0x1000>, - <0x4000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <30>; - dma-channels = <30>; - #dma-requests = <256>; - dma-requests = <256>; - }; - }; - - target-module@40300000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40300000 0x10000>; - - ocmcram: sram@0 { - compatible = "mmio-sram"; - reg = <0 0x10000>; /* 64k */ - ranges = <0 0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - pm_sram_code: pm-code-sram@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; - - pm_sram_data: pm-data-sram@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; - }; - }; - }; - - target-module@4c000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x4c000000 0x4>; - reg-names = "rev"; - clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000000 0x1000000>; - - emif: emif@0 { - compatible = "ti,emif-am3352"; - reg = <0 0x1000000>; - interrupts = <101>; - sram = <&pm_sram_code - &pm_sram_data>; - }; - }; - - target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000000 4>, - <0x50000010 4>, - <0x50000014 4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ - <0x00000000 0x00000000 0x40000000>; /* data */ - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - }; - - sham_target: target-module@53100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x53100100 0x4>, - <0x53100110 0x4>, - <0x53100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap4-sham"; - reg = <0 0x200>; - interrupts = <109>; - dmas = <&edma 36 0>; - dma-names = "rx"; - }; - }; - - aes_target: target-module@53500000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53500080 0x4>, - <0x53500084 0x4>, - <0x53500088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53500000 0x1000>; - - aes: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = <103>; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; - clock-names = "fck"; - power-domains = <&prm_gfx>; - resets = <&prm_gfx 0>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x1000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; -}; - -#include "am33xx-l4.dtsi" -#include "am33xx-clocks.dtsi" - -&prcm { - prm_per: prm@c00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xc00 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_wkup: prm@d00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xd00 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_mpu: prm@e00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xe00 0x100>; - #power-domain-cells = <0>; - }; - - prm_device: prm@f00 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0xf00 0x100>; - #reset-cells = <1>; - }; - - prm_rtc: prm@1000 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0x1000 0x100>; - #power-domain-cells = <0>; - }; - - prm_gfx: prm@1100 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0x1100 0x100>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - prm_cefuse: prm@1200 { - compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #power-domain-cells = <0>; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer1_target { - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>, - <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; - clock-names = "fck", "ick"; - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&timer1_fck>; - assigned-clock-parents = <&sys_clkin_ck>; - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; - clock-names = "fck", "ick"; - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&timer2_fck>; - assigned-clock-parents = <&sys_clkin_ck>; - }; -}; diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts deleted file mode 100644 index afae7a4d232e..000000000000 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * See craneboard.org for more details - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am3517.dtsi" - -/ { - model = "TI AM3517 CraneBoard (TMDSEVM3517)"; - compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <2600000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - /* goes to expansion connector */ - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - /* goes to expansion connector */ - status = "disabled"; -}; - -&mmc1 { - vmmc-supply = <&vdd2_reg>; - bus-width = <8>; -}; - -&mmc2 { - /* goes to expansion connector */ - status = "disabled"; -}; - -&mmc3 { - /* goes to expansion connector */ - status = "disabled"; -}; - -#include "tps65910.dtsi" - -&omap3_pmx_core { - tps_pins: tps-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; -}; - -&tps { - pinctrl-names = "default"; - pinctrl-0 = <&tps_pins>; - - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - ti,en-ck32k-xtal; - - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - /* - * Unused: - * VDIG1=2.7V,300mA max - * VDIG2=1.8V,300mA max - */ - - vpll_reg: regulator@7 { - /* VDDS_DPLL_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - /* VDDS_SRAM_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - /* VDDA1P8V_USBPHY */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* VAUX33 unused */ - - vdac_reg: regulator@8 { - /* VDDA_DAC_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - /* VDDA3P3V_USBPHY */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_CORE */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDDSHV_3V3 */ - regulator-name = "vdd_shv"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* VDD3 unused */ - }; -}; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi deleted file mode 100644 index 16b8968d5be8..000000000000 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/ - */ - -#include - -/ { - codec1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "tlv320aic23-hifi"; - - simple-audio-card,widgets = - "Microphone", "Mic In", - "Line", "Line In", - "Line", "Line Out"; - - simple-audio-card,routing = - "Line Out", "LOUT", - "Line Out", "ROUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic In"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - - simple-audio-card,cpu { - sound-dai = <&mcbsp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic23_1>; - system-clock-frequency = <12000000>; - }; - }; - - codec2 { - compatible = "simple-audio-card"; - simple-audio-card,name = "tlv320aic23-hifi"; - - simple-audio-card,widgets = - "Microphone", "Mic In", - "Line", "Line In", - "Line", "Line Out"; - - simple-audio-card,routing = - "Line Out", "LOUT", - "Line Out", "ROUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic In"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master2>; - simple-audio-card,frame-master = <&sound_master2>; - - simple-audio-card,cpu { - sound-dai = <&mcbsp2>; - }; - - sound_master2: simple-audio-card,codec { - sound-dai = <&tlv320aic23_2>; - system-clock-frequency = <12000000>; - }; - }; - - expander-keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - key-record { - label = "Record"; - /* linux,code = ; */ - gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; - }; - - key-play { - label = "Play"; - linux,code = ; - gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; - }; - - key-stop { - label = "Stop"; - linux,code = ; - gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; - }; - - key-fwd { - label = "FWD"; - linux,code = ; - gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; - }; - - key-rwd { - label = "RWD"; - linux,code = ; - gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; - }; - - key-shift { - label = "Shift"; - linux,code = ; - gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; - }; - - key-mode { - label = "Mode"; - linux,code = ; - gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; - }; - - key-menu { - label = "Menu"; - linux,code = ; - gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; - }; - - key-up { - label = "Up"; - linux,code = ; - gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; - }; - - key-down { - label = "Down"; - linux,code = ; - gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c2 { - /* Audio codecs */ - tlv320aic23_1: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells = <0>; - status = "okay"; - }; - - tlv320aic23_2: codec@1b { - compatible = "ti,tlv320aic23"; - reg = <0x1b>; - #sound-dai-cells = <0>; - status = "okay"; - }; -}; - -&i2c3 { - /* Audio codecs */ - tlv320aic23_3: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells = <0>; - status = "okay"; - }; - - /* GPIO Expanders */ - tca6416_2: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; - - tca6416_3: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; - - /* TVP5146 Analog Video decoder input */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&mcbsp1 { - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; -}; - -&mcbsp2 { - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&omap3_pmx_core { - mcbsp1_pins: mcbsp1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ - OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ - >; - }; -}; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts deleted file mode 100644 index af9df15274be..000000000000 --- a/arch/arm/boot/dts/am3517-evm.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am3517.dtsi" -#include "am3517-som.dtsi" -#include "am3517-evm-ui.dtsi" -#include - -/ { - model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; - compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vmmc_fixed: vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - button-user { - label = "User Push Button"; - linux,code = ; - gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; - }; - - switch-1 { - label = "User Switch 1"; - linux,code = ; - gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; - }; - - switch-2 { - label = "User Switch 2"; - linux,code = ; - gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; - }; - - switch-3 { - label = "User Switch 3"; - linux,code = ; - gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; - }; - - switch-4 { - label = "User Switch 4"; - linux,code = ; - gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; - }; - - switch-5 { - label = "User Switch 5"; - linux,code = ; - gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; - }; - - switch-6 { - label = "User Switch 6"; - linux,code = ; - gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; - }; - - switch-7 { - label = "User Switch 7"; - linux,code = ; - gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; - }; - - switch-8 { - label = "User Switch 8"; - linux,code = ; - gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - user_led_1 { - label = "am3517evm:green:user_led_1"; - gpios = <&tca6416 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led_2 { - label = "am3517evm:green:user_led_2"; - gpios = <&tca6416 6 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led_3 { - label = "am3517evm:green:user_led_3"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; /* SD/MMC card activity */ - }; - - user_led_4 { - label = "am3517evm:green:user_led_4"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - lcd0: display@0 { - /* This isn't the exact LCD, but the timings meet spec */ - /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - label = "15"; - backlight = <&bl>; - enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ - vcc-supply = <&vdd_io_reg>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - power-supply = <&vdd_io_reg>; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm11 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ - }; - - pwm11: pwm-11 { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer11>; - #pwm-cells = <3>; - ti,clock-source = <0x01>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_rst_pins>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ - #phy-cells = <0>; - }; -}; - -&davinci_emac { - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - vdds_dsi-supply = <&vdd_io_reg>; - vdda_video-supply = <&vdd_io_reg>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; - /* User DIP swithes [1:8] / User LEDS [1:2] */ - tca6416: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */ -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&omap3_pmx_core { - - ethernet_pins: ethernet-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ - OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ - OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */ - OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */ - OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */ - OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */ - OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */ - OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */ - OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */ - OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - leds_pins: leds-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ - OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */ - >; - }; - - pwm_pins: pwm-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; - - hsusb1_rst_pins: hsusb1-rst-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; -}; - -&omap3_pmx_core2 { - - hsusb1_pins: hsusb1-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi deleted file mode 100644 index bd0a6c95afa1..000000000000 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ /dev/null @@ -1,243 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Derald D. Woods - * - * Based on am3517-evm.dts - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd_core_reg>; - }; - }; - - wl12xx_buffer: wl12xx_buf { - compatible = "regulator-fixed"; - regulator-name = "wl1271_buf"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_buffer_pins>; - gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ - regulator-always-on; - vin-supply = <&vdd_1v8_reg>; - }; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_wkup_pins>; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - vin-supply = <&wl12xx_buffer>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name = "micron,mt29f4g16abchch"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - - pinctrl-names = "default"; - pinctrl-0 = <&rtc_pins>; - interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */ - }; - - tps: tps65023@48 { - compatible = "ti,tps65023"; - reg = <0x48>; - - regulators { - vdd_core_reg: VDCDC1 { - regulator-name = "vdd_core"; - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vdd_io_reg: VDCDC2 { - regulator-name = "vdd_io"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_1v8_reg: VDCDC3 { - regulator-name = "vdd_1v8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_usb18_reg: LDO1 { - regulator-name = "vdd_usb18"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_usb33_reg: LDO2 { - regulator-name = "vdd_usb33"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - touchscreen: tsc2004@4b { - compatible = "ti,tsc2004"; - reg = <0x4b>; - - vio-supply = <&vdd_io_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mmc2 { - interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; - - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "ti,wl1271-st"; - enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ - max-speed = <3000000>; - }; -}; - -&omap3_pmx_core { - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - wl12xx_buffer_pins: wl12xx-buffer-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - rtc_pins: rtc-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ - >; - }; - - tsc2004_pins: tsc2004-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ - >; - }; -}; - -&omap3_pmx_wkup { - - wl12xx_wkup_pins: wl12xx-wkup-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi deleted file mode 100644 index 823f63502e9f..000000000000 --- a/arch/arm/boot/dts/am3517.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for am3517 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "omap3.dtsi" - -/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ -/delete-node/ &aes1_target; -/delete-node/ &aes2_target; - -/ { - aliases { - serial3 = &uart4; - can = &hecc; - }; - - cpus { - cpu: cpu@0 { - /* Based on OMAP3630 variants OPP50 and OPP100 */ - operating-points-v2 = <&cpu0_opp_table>; - - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - /* - * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx - * appear to operate at 300MHz as well. Since AM3517 only - * lists one operating voltage, it will remain fixed at 1.2V - */ - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1200000>; - opp-supported-hw = <0xffffffff 0xffffffff>; - opp-suspend; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000>; - opp-supported-hw = <0xffffffff 0xffffffff>; - }; - }; - - ocp@68000000 { - target-module@5c040000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5c040400 0x4>, - <0x5c040404 0x4>, - <0x5c040408 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&hsotgusb_ick_am35xx>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5c040000 0x1000>; - - am35x_otg_hs: am35x_otg_hs@0 { - compatible = "ti,omap3-musb"; - status = "disabled"; - reg = <0 0x1000>; - interrupts = <71>; - interrupt-names = "mc"; - }; - }; - - davinci_emac: ethernet@5c000000 { - compatible = "ti,am3517-emac"; - ti,hwmods = "davinci_emac"; - status = "disabled"; - reg = <0x5c000000 0x30000>; - interrupts = <67 68 69 70>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0x10000>; - ti,davinci-ctrl-mod-reg-offset = <0>; - ti,davinci-ctrl-ram-offset = <0x20000>; - ti,davinci-ctrl-ram-size = <0x2000>; - ti,davinci-rmii-en = /bits/ 8 <1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - clocks = <&emac_ick>; - clock-names = "ick"; - }; - - davinci_mdio: mdio@5c030000 { - compatible = "ti,davinci_mdio"; - ti,hwmods = "davinci_mdio"; - status = "disabled"; - reg = <0x5c030000 0x1000>; - bus_freq = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&emac_fck>; - clock-names = "fck"; - }; - - uart4: serial@4809e000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - status = "disabled"; - reg = <0x4809e000 0x400>; - interrupts = <84>; - dmas = <&sdma 55 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - hecc: can@5c050000 { - compatible = "ti,am3517-hecc"; - status = "disabled"; - reg = <0x5c050000 0x80>, - <0x5c053000 0x180>, - <0x5c052000 0x200>; - reg-names = "hecc", "hecc-ram", "mbx"; - interrupts = <24>; - clocks = <&hecc_ck>; - }; - - /* - * On am3517 the OCP registers do not seem to be accessible - * similar to the omap34xx. Maybe SGX is permanently set to - * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is - * write-only at 0x50000e10. We detect SGX based on the SGX - * revision register instead of the unreadable OCP revision - * register. - */ - sgx_module: target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000014 0x4>; - reg-names = "rev"; - clocks = <&sgx_fck>, <&sgx_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; -}; - -/* Not currently working, probably needs at least different clocks */ -&rng_target { - status = "disabled"; - /delete-property/ clocks; -}; - -/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ -&usb_otg_target { - status = "disabled"; -}; - -&iva { - status = "disabled"; -}; - -&mailbox { - status = "disabled"; -}; - -&mmu_isp { - status = "disabled"; -}; - -#include "am35xx-clocks.dtsi" -#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" - -/* Preferred always-on timer for clocksource */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt1_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt2_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts deleted file mode 100644 index e7d7124a34ba..000000000000 --- a/arch/arm/boot/dts/am3517_mt_ventoux.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Ilya Yanok, EmCraft Systems - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TeeJet Mt.Ventoux"; - compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - /* AM35xx doesn't have IVA */ - soc { - iva { - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi deleted file mode 100644 index 0ee7afaa0e8e..000000000000 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - emac_ick: emac_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <1>; - }; - - emac_fck: emac_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&rmii_ck>; - reg = <0x032c>; - ti,bit-shift = <9>; - }; - - vpfe_ick: vpfe_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <2>; - }; - - vpfe_fck: vpfe_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pclk_ck>; - reg = <0x032c>; - ti,bit-shift = <10>; - }; - - hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <0>; - }; - - hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <8>; - }; - - hecc_ck: hecc_ck@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <3>; - }; -}; -&cm_clocks { - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <0>; - - ipss_ick: clock-ipss-ick { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clock-output-names = "ipss_ick"; - clocks = <&core_l3_ick>; - ti,bit-shift = <4>; - }; - - uart4_ick_am35xx: clock-uart4-ick-am35xx { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "uart4_ick_am35xx"; - clocks = <&core_l4_ick>; - ti,bit-shift = <23>; - }; - }; - - rmii_ck: rmii_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - pclk_ck: pclk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <0>; - - uart4_fck_am35xx: clock-uart4-fck-am35xx { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "uart4_fck_am35xx"; - clocks = <&core_48m_fck>; - ti,bit-shift = <23>; - }; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, - <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, - <&hecc_ck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; - }; -}; diff --git a/arch/arm/boot/dts/am3703.dtsi b/arch/arm/boot/dts/am3703.dtsi deleted file mode 100644 index 2b994ae790c9..000000000000 --- a/arch/arm/boot/dts/am3703.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; - -&sgx_module { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am3715.dtsi b/arch/arm/boot/dts/am3715.dtsi deleted file mode 100644 index ab328e8c0bd8..000000000000 --- a/arch/arm/boot/dts/am3715.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts deleted file mode 100644 index ac082e83a9a2..000000000000 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for Winterland IceBoard - * - * https://mcgillcosmology.com - * https://threespeedlogic.com - * - * This is an ARM + FPGA instrumentation board used at telescopes in - * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO - * observatory in British Columbia (CHIME). - * - * Copyright (c) 2019 Three-Speed Logic, Inc. - */ - -/dts-v1/; - -#include "dm814x.dtsi" -#include - -/ { - model = "Winterland IceBoard"; - compatible = "ti,dm8148", "ti,dm814"; - - chosen { - stdout-path = "serial1:115200n8"; - bootargs = "earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -/* The MAC provides internal delay for the transmit path ONLY, which is enabled - * provided no -id/-txid/-rxid suffix is provided to "phy-mode". - * - * The receive path is delayed at the PHY. The recommended register settings - * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the - * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, - * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to - * obtain the correct register settings. - */ -&mac { dual_emac = <1>; }; -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0x2>; - - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - - rxd3-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd0-skew-ps = <0>; - - phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0x1>; - - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - - rxd3-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd0-skew-ps = <0>; - - phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc1 { status = "disabled"; }; -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; -}; -&mmc3 { status = "disabled"; }; - -&i2c1 { - /* Most I2C activity happens through this port, with the sole exception - * of the backplane. Since there are multiply assigned addresses, the - * "i2c-mux-idle-disconnect" is important. - */ - - i2c-mux@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c@0 { - /* FMC A */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - /* FMC B */ - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - /* QSFP A */ - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - /* QSFP B */ - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c@4 { - /* SFP */ - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; - ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; - ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; - - ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; - ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; - ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; - - ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; - ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; - ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; - ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; - ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; - ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; - ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; - ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; - ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; - }; - - i2c@6 { - /* Backplane */ - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - u41: pca9575@20 { - compatible = "nxp,pca9575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", - "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", - "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", - "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; - reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - u42: pca9575@21 { - compatible = "nxp,pca9575"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", - "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", - "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", - "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; - reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - u48: pca9575@22 { - compatible = "nxp,pca9575"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, - <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; - led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, - <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; - - gpio-line-names = - "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", - "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", - "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", - "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; - reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - u59: pca9575@23 { - compatible = "nxp,pca9575"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", - "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", - "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", - "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; - reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; - tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; - tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; - tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; - - /* EEPROM bank and serial number are treated as separate devices */ - at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; - at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; - }; - }; -}; - -&i2c2 { - i2c-mux@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@6 { - /* Backplane */ - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - multi-master; - - /* All backplanes should have this -- it's how we know they're there. */ - at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; - at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; - - /* 16 slot backplane */ - tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; - tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; - ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; - amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; - - /* Single slot backplane */ - }; - }; -}; - -&pincntl { - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ - DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ - >; - }; - - usb0_pins: usb0-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: usb1-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; - - gpio1_pins: gpio1-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ - DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ - DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ - - DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ - DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ - DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ - DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ - DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ - - DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ - DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ - DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ - DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ - DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ - - DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ - DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ - DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ - DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ - >; - }; - - gpio2_pins: gpio2-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ - DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ - DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ - DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ - - //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ - //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ - DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ - >; - }; - - gpio4_pins: gpio4-pins { - pinctrl-single,pins = < - /* The PLL doesn't react well to the SPI controller reset, so - * we force the CS lines to pull up as GPIOs until we're ready. - * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 - */ - DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ - DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ - DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ - DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ - DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ - DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ - >; - }; - - spi2_pins: spi2-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ - DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ - >; - }; - - spi4_pins: spi4-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0a7c, 0x20) - DM814X_IOPAD(0x0b74, 0x20) - DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) - DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) - DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) - >; - }; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; - gpio-line-names = - "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ - "", "", "", "", /* 4-7 */ - "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ - "", "", "", "FMCA_TRST", /* 12-15 */ - "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ - "FMCB_TRST", "", "", "", /* 20-23 */ - "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ - "", "", "", ""; /* 28-31 */ -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_pins>; - gpio-line-names = - "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ - "", "", "", "PHYB_IRQ_N", /* 4-7 */ - "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ -}; - -&gpio3 { - pinctrl-names = "default"; - /*pinctrl-0 = <&gpio3_pins>;*/ - gpio-line-names = - "", "", "ARMClkSel0", "", /* 0-3 */ - "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio4_pins>; - gpio-line-names = - "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", - "BP_ARM_GPIO4", "BP_ARM_GPIO5"; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; - -&mcspi1 { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - - fsbl@0 { - /* 256 kB */ - label = "U-Boot-min"; - reg = <0 0x40000>; - }; - ssbl@1 { - /* 512 kB */ - label = "U-Boot"; - reg = <0x40000 0x80000>; - }; - bootenv@2 { - /* 256 kB */ - label = "U-Boot Env"; - reg = <0xc0000 0x40000>; - }; - kernel@3 { - /* 4 MB */ - label = "Kernel"; - reg = <0x100000 0x400000>; - }; - ipmi@4 { - label = "IPMI FRU"; - reg = <0x500000 0x40000>; - }; - fs@5 { - label = "File System"; - reg = <0x540000 0x1ac0000>; - }; - }; -}; - -&mcspi3 { - /* DMA event numbers stolen from MCASP */ - dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 - &edma_xbar 10 0 18 &edma_xbar 11 0 19>; - dma-names = "tx0", "rx0", "tx1", "rx1"; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - - /* DMA event numbers stolen from MCASP, MCBSP */ - dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; - dma-names = "tx0", "rx0"; -}; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi deleted file mode 100644 index 8613355bbd5e..000000000000 --- a/arch/arm/boot/dts/am4372.dtsi +++ /dev/null @@ -1,801 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM4372 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - compatible = "ti,am4372", "ti,am43"; - interrupt-parent = <&wakeupgen>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - spi0 = &qspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu: cpu@0 { - compatible = "arm,cortex-a9"; - enable-method = "ti,am4372"; - device_type = "cpu"; - reg = <0>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - operating-points-v2 = <&cpu0_opp_table>; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - cpu-idle-states = <&mpu_gate>; - }; - - idle-states { - mpu_gate: mpu_gate { - compatible = "arm,idle-state"; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <300>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0xFF 0x04>; - }; - - opp120-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0xFF 0x08>; - }; - - oppturbo-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0xFF 0x10>; - }; - - oppnitro-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0xFF 0x20>; - }; - }; - - soc { - compatible = "ti,omap-infra"; - }; - - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; - - scu: scu@48240000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x48240000 0x100>; - }; - - global_timer: timer@48240200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x48240200 0x100>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&mpu_periphclk>; - }; - - local_timer: timer@48240600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x48240600 0x100>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&mpu_periphclk>; - }; - - cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - ocp@44000000 { - compatible = "simple-pm-bus"; - power-domains = <&prm_per>; - clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,no-idle; - - l3-noc@44000000 { - compatible = "ti,am4372-l3-noc"; - reg = <0x44000000 0x400000>, - <0x44800000 0x400000>; - interrupts = , - ; - }; - - l4_wkup: interconnect@44c00000 { - }; - l4_per: interconnect@48000000 { - }; - l4_fast: interconnect@4a000000 { - }; - - target-module@4c000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x4c000000 0x4>; - reg-names = "rev"; - clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000000 0x1000000>; - - emif: emif@0 { - compatible = "ti,emif-am4372"; - reg = <0 0x1000000>; - interrupts = ; - sram = <&pm_sram_code - &pm_sram_data>; - }; - }; - - target-module@49000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49000000 0x4>; - reg-names = "rev"; - clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49000000 0x10000>; - - edma: dma@0 { - compatible = "ti,edma3-tpcc"; - reg = <0 0x10000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <58 59>; - }; - }; - - target-module@49800000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49800000 0x4>, - <0x49800010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49800000 0x100000>; - - edma_tptc0: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49900000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49900000 0x4>, - <0x49900010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49900000 0x100000>; - - edma_tptc1: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49a00000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49a00000 0x4>, - <0x49a00010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49a00000 0x100000>; - - edma_tptc2: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@47810000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x478102fc 0x4>, - <0x47810110 0x4>, - <0x47810114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47810000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,am437-sdhci"; - ti,needs-special-reset; - interrupts = ; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - - sham_target: target-module@53100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x53100100 0x4>, - <0x53100110 0x4>, - <0x53100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap5-sham"; - reg = <0 0x300>; - dmas = <&edma 36 0>; - dma-names = "rx"; - interrupts = ; - }; - }; - - aes_target: target-module@53501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53501080 0x4>, - <0x53501084 0x4>, - <0x53501088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53501000 0x1000>; - - aes: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; - }; - - des_target: target-module@53701000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53701030 0x4>, - <0x53701034 0x4>, - <0x53701038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l3_clkdm */ - clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x53701000 0x1000>; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma 34 0>, - <&edma 33 0>; - dma-names = "tx", "rx"; - }; - }; - - pruss_tm: target-module@54400000 { - compatible = "ti,sysc-pruss", "ti,sysc"; - reg = <0x54426000 0x4>, - <0x54426004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | - SYSC_PRUSS_SUB_MWAIT)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_per 1>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x54400000 0x80000>; - - pruss1: pruss@0 { - compatible = "ti,am4376-pruss1"; - reg = <0x0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pruss1_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x8000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - pruss1_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - pruss1_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&sysclk_div>, /* icss_iep_gclk */ - <&pruss_ocp_gclk>; /* icss_ocp_gclk */ - }; - }; - }; - - pruss1_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x58>; - }; - - pruss1_intc: interrupt-controller@20000 { - compatible = "ti,pruss-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", - "host_intr6", "host_intr7"; - ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ - }; - - pru1_0: pru@34000 { - compatible = "ti,am4376-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x400>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am437x-pru1_0-fw"; - }; - - pru1_1: pru@38000 { - compatible = "ti,am4376-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x400>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am437x-pru1_1-fw"; - }; - - pruss1_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x90>; - clocks = <&dpll_core_m4_ck>; - clock-names = "fck"; - bus_freq = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pruss0: pruss@40000 { - compatible = "ti,am4376-pruss0"; - reg = <0x40000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pruss0_mem: memories@40000 { - reg = <0x40000 0x1000>, - <0x42000 0x1000>; - reg-names = "dram0", "dram1"; - }; - - pruss0_cfg: cfg@66000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x66000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - pruss0_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&sysclk_div>, /* icss_iep_gclk */ - <&pruss_ocp_gclk>; /* icss_ocp_gclk */ - }; - }; - }; - - pruss0_mii_rt: mii-rt@72000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x72000 0x58>; - status = "disabled"; - }; - - pruss0_intc: interrupt-controller@60000 { - compatible = "ti,pruss-intc"; - reg = <0x60000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", - "host_intr6", "host_intr7"; - ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ - }; - - pru0_0: pru@74000 { - compatible = "ti,am4376-pru"; - reg = <0x74000 0x1000>, - <0x62000 0x400>, - <0x62400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am437x-pru0_0-fw"; - }; - - pru0_1: pru@78000 { - compatible = "ti,am4376-pru"; - reg = <0x78000 0x1000>, - <0x64000 0x400>, - <0x64400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am437x-pru0_1-fw"; - }; - }; - }; - - target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000000 4>, - <0x50000010 4>, - <0x50000014 4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ - <0x00000000 0x00000000 0x40000000>; /* data */ - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - clocks = <&l3s_gclk>; - clock-names = "fck"; - reg = <0x50000000 0x2000>; - interrupts = ; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - }; - - target-module@47900000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x47900000 0x4>, - <0x47900010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47900000 0x1000>, - <0x30000000 0x30000000 0x4000000>; - - qspi: spi@0 { - compatible = "ti,am4372-qspi"; - reg = <0 0x100>, - <0x30000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - clocks = <&dpll_per_m2_div4_ck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 138 0x4>; - num-cs = <4>; - }; - }; - - target-module@40300000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40300000 0x40000>; - - ocmcram: sram@0 { - compatible = "mmio-sram"; - reg = <0 0x40000>; /* 256k */ - ranges = <0 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - - pm_sram_code: pm-code-sram@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; - - pm_sram_data: pm-data-sram@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; - }; - }; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; - clock-names = "fck"; - power-domains = <&prm_gfx>; - resets = <&prm_gfx 0>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x1000000>; - }; - }; -}; - -#include "am437x-l4.dtsi" -#include "am43xx-clocks.dtsi" - -&prcm { - prm_mpu: prm@300 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x300 0x100>; - #power-domain-cells = <0>; - }; - - prm_gfx: prm@400 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - prm_rtc: prm@500 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x500 0x100>; - #power-domain-cells = <0>; - }; - - prm_tamper: prm@600 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x600 0x100>; - #power-domain-cells = <0>; - }; - - prm_cefuse: prm@700 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #power-domain-cells = <0>; - }; - - prm_per: prm@800 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x800 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_wkup: prm@2000 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x2000 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_device: prm@4000 { - compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; - reg = <0x4000 0x100>; - #reset-cells = <1>; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, - <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; - clock-names = "fck", "ick"; - timer@0 { - assigned-clocks = <&timer1_fck>; - assigned-clock-parents = <&sys_clkin_ck>; - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; - clock-names = "fck", "ick"; - timer@0 { - assigned-clocks = <&timer2_fck>; - assigned-clock-parents = <&sys_clkin_ck>; - }; -}; diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts deleted file mode 100644 index 9ec75d03eaff..000000000000 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - */ - -/dts-v1/; - -#include -#include -#include -#include "am4372.dtsi" - -/ { - model = "CompuLab CM-T43"; - compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; - - leds { - compatible = "gpio-leds"; - - ledb { - label = "cm-t43:green"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vmmc_3v3: fixedregulator-v3_3 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&cm_t43_led_pins>; - - cm_t43_led_pins: cm-t43-led-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa78, MUX_MODE7) - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - emmc_pins: emmc-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ - AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ - AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */ - AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */ - AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */ - AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */ - AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */ - AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - >; - }; - - spi0_pins: spi0-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; - - nand_flash_x8: nand-flash-x8-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - AM4372_IOPAD(0xa74, MUX_MODE3) - /* Slave 2 */ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */ - AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */ - AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */ - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */ - AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */ - AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */ - AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */ - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */ - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */ - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */ - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */ - AM4372_IOPAD(0xa38, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x1000000>; - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - /* MTD partition table */ - partition@0 { - label = "kernel"; - reg = <0x0 0x00980000>; - }; - partition@980000 { - label = "dtb"; - reg = <0x00980000 0x00080000>; - }; - partition@a00000 { - label = "rootfs"; - reg = <0x00a00000 0x0>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - compatible = "ti,tps65218"; - reg = <0x24>; - interrupts = ; /* NMIn */ - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-suspend-enable; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - eeprom_module: at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmc_3v3>; - bus-width = <8>; - non-removable; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - dmas = <&edma 16 0 - &edma 17 0>; - dma-names = "tx0", "rx0"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - partition@0 { - label = "uboot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "uboot environment"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x100000>; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-txid"; - ti,dual-emac-pvid = <2>; -}; - -&dwc3_1 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&dwc3_2 { - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; - interrupts = , - , - ; - interrupt-names = "peripheral", "host", "otg"; -}; - -&elm { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&cpu { - cpu0-supply = <&dcdc2>; - operating-points = <1000000 1330000>, - <800000 1260000>, - <720000 1200000>, - <600000 1100000>, - <300000 950000>; -}; - -&pruss1_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts deleted file mode 100644 index f7aad0323d19..000000000000 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ /dev/null @@ -1,1137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* AM437x GP EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include - -/ { - model = "TI AM437x GP EVM"; - compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart0; - }; - - evm_v3_3d: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "evm_v3_3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&matrix_keypad_default>; - pinctrl-1 = <&matrix_keypad_sleep>; - - wakeup-source; - - row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ - &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ - &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ - - col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ - &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x00010202 /* P2 */ - 0x01000067 /* UP */ - 0x0101006a /* RIGHT */ - 0x02000069 /* LEFT */ - 0x0201006c>; /* DOWN */ - }; - - lcd0: display { - compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; - label = "lcd"; - - backlight = <&lcd_bl>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - /* fixed 12MHz oscillator */ - refclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM437x-GP-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-frequency = <12000000>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <12000000>; - }; - }; - - beeper: beeper { - compatible = "gpio-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&beeper_pins_default>; - pinctrl-1 = <&beeper_pins_sleep>; - gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; - pinctrl-1 = <&wlan_pins_sleep>; - - ddr3_vtt_toggle_default: ddr-vtt-toggle-default-pins { - pinctrl-single,pins = < - 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - ecap0_pins: backlight-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - pixcir_ts_pins: pixcir-ts-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - nand_flash_x8: nand-flash-x8-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - dss_pins: dss-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - - >; - }; - - display_mux_pins: display-mux-pins { - pinctrl-single,pins = < - /* GPIO 5_8 to select LCD / HDMI */ - AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - dcan0_default: dcan0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ - >; - }; - - dcan0_sleep: dcan0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ - >; - }; - - dcan1_default: dcan1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ - >; - }; - - dcan1_sleep: dcan1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ - >; - }; - - vpfe0_pins_default: vpfe0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ - >; - }; - - vpfe0_pins_sleep: vpfe0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ - >; - }; - - vpfe1_pins_default: vpfe1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ - AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ - AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ - AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ - AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ - >; - }; - - vpfe1_pins_sleep: vpfe1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ - AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ - AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ - AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ - AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ - AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ - AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ - AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ - AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ - AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ - AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ - AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ - AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ - >; - }; - - mmc3_pins_default: mmc3-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ - AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ - >; - }; - - mmc3_pins_sleep: mmc3-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ - AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ - AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ - AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ - AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ - >; - }; - - wlan_pins_default: wlan-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ - >; - }; - - wlan_pins_sleep: wlan-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ - AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ - AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ - AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ - >; - }; - - mcasp1_pins: mcasp1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_sleep_pins: mcasp1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - gpio0_pins: gpio0-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ - >; - }; - - emmc_pins_default: emmc-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - >; - }; - - emmc_pins_sleep: emmc-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ - >; - }; - - beeper_pins_default: beeper-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ - >; - }; - - beeper_pins_sleep: beeper-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ - >; - }; - - unused_pins: unused-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) - AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) - AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) - AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) - AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - debugss_pins: debugss-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) - >; - }; - - uart0_pins_default: uart0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart0_pins_sleep: uart0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - matrix_keypad_default: matrix-keypad-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) - AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) - AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - matrix_keypad_sleep: matrix-keypad-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) - AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) - AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_pins_default>; - pinctrl-1 = <&uart0_pins_sleep>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&refclk 0>; - clock-names = "xvclk"; - - port { - ov2659_0: endpoint { - remote-endpoint = <&vpfe1_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - pixcir_ts@5c { - compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default"; - pinctrl-0 = <&pixcir_ts_pins>; - reg = <0x5c>; - - attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - - /* - * 0x264 represents the offset of padconf register of - * gpio3_22 from am43xx_pinmux base. - */ - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, - <&am43xx_pinmux 0x264>; - interrupt-names = "tsc", "wakeup"; - - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - wakeup-source; - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&refclk 0>; - clock-names = "xvclk"; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> EN: V1_8D -> VBAT */ - AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ - DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ - DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&magadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_pins>; - status = "okay"; - - sel-emmc-nand-hog { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - /* SelEMMCorNAND selects between eMMC and NAND: - * Low: NAND - * High: eMMC - * When changing this line make sure the newly - * selected device node is enabled and the previously - * selected device node is disabled. - */ - output-low; - line-name = "SelEMMCorNAND"; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5_target { - ti,no-reset-on-init; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&display_mux_pins>; - status = "okay"; - - sel-lcd-hdmi-hog { - /* - * SelLCDorHDMI selects between display and audio paths: - * Low: HDMI display with audio via HDMI - * High: LCD display with analog audio via aic3111 codec - */ - gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "SelLCDorHDMI"; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&evm_v3_3d>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -/* eMMC sits on mmc2 */ -&mmc2 { - /* - * When enabling eMMC, disable GPMC/NAND and set - * SelEMMCorNAND to output-high - */ - status = "disabled"; - vmmc-supply = <&evm_v3_3d>; - bus-width = <8>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_sleep>; - non-removable; -}; - -&mmc3 { - status = "okay"; - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma_xbar 30 0 1>, - <&edma_xbar 31 0 2>; - dma-names = "tx", "rx"; - vmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc3_pins_default>; - pinctrl-1 = <&mmc3_pins_sleep>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * When enabling GPMC, disable eMMC and set - * SelEMMCorNAND to output-low - */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <40>; - gpmc,cs-wr-off-ns = <40>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <25>; - gpmc,adv-wr-off-ns = <25>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <20>; - gpmc,oe-on-ns = <3>; - gpmc,oe-off-ns = <30>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <40>; - gpmc,wr-cycle-ns = <40>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00040000 0x00040000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x000c0000 0x00040000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00100000 0x00080000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x00180000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x00280000 0x00040000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x002c0000 0x00040000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00300000 0x00700000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x1f600000>; - }; - }; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dcan0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan0_default>; - pinctrl-1 = <&dcan0_sleep>; - status = "okay"; -}; - -&dcan1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan1_default>; - pinctrl-1 = <&dcan1_sleep>; - status = "okay"; -}; - -&vpfe0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe0_pins_default>; - pinctrl-1 = <&vpfe0_pins_sleep>; - - port { - vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&vpfe1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe1_pins_default>; - pinctrl-1 = <&vpfe1_pins_sleep>; - - port { - vpfe1_ep: endpoint { - remote-endpoint = <&ov2659_0>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_sleep_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; - -&wkup_m3_ipc { - ti,set-io-isolation; - firmware-name = "am43x-evm-scale-data.bin"; -}; - -&pruss1_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts deleted file mode 100644 index 863552393c07..000000000000 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ /dev/null @@ -1,541 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM437x Industrial Development Kit"; - compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; - - chosen { - stdout-path = &uart0; - }; - - v24_0d: fixed-regulator-v24_0d { - compatible = "regulator-fixed"; - regulator-name = "V24_0D"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - regulator-boot-on; - }; - - v3_3d: fixed-regulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "V3_3D"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - vdd_corereg: fixed-regulator-vdd_corereg { - compatible = "regulator-fixed"; - regulator-name = "VDD_COREREG"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - vdd_core: fixed-regulator-vdd_core { - compatible = "regulator-fixed"; - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_corereg>; - }; - - v1_8dreg: fixed-regulator-v1_8dreg{ - compatible = "regulator-fixed"; - regulator-name = "V1_8DREG"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - v1_8d: fixed-regulator-v1_8d{ - compatible = "regulator-fixed"; - regulator-name = "V1_8D"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v1_8dreg>; - }; - - v1_5dreg: fixed-regulator-v1_5dreg{ - compatible = "regulator-fixed"; - regulator-name = "V1_5DREG"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - v1_5d: fixed-regulator-v1_5d{ - compatible = "regulator-fixed"; - regulator-name = "V1_5D"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v1_5dreg>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins_default>; - - switch-0 { - label = "power-button"; - linux,code = ; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - }; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - leds-iio { - status = "disabled"; - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am43xx_pinmux { - gpio_keys_pins_default: gpio-keys-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ - >; - }; - - i2c0_pins_default: i2c0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c0_pins_sleep: i2c0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c2_pins_default: i2c2-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ - AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ - >; - }; - - i2c2_pins_sleep: i2c2-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc1_pins_sleep: mmc1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - spi1_pins_default: spi1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ - AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ - AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ - AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ - >; - }; - - spi1_pins_sleep: spi1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - ecap0_pins_default: backlight-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - qspi_pins_default: qspi-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ - >; - }; - - qspi_pins_sleep: qspi-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_pins_default>; - pinctrl-1 = <&i2c0_pins_sleep>; - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - tps: tps62362@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - regulator-name = "VDD_MPU"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1330000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - vin-supply = <&v3_3d>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_default>; - pinctrl-1 = <&i2c2_pins_sleep>; - clock-frequency = <100000>; - - tpic2810: tpic2810@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_default>; - pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in; - - sn65hvs882: sn65hvs882@0 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; - - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_sleep>; - vmmc-supply = <&v3_3d>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_pins_default>; - pinctrl-1 = <&qspi_pins_sleep>; - - spi-max-frequency = <48000000>; - flash@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * MTD partition table. The ROM checks the first 512KiB for a - * valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x00080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&cpu { - cpu0-supply = <&tps>; -}; - -&cpu0_opp_table { - /* - * Supply voltage supervisor on board will not allow opp50 so - * disable it and set opp100 as suspend OPP. - */ - opp50-300000000 { - status = "disabled"; - }; - - opp100-600000000 { - opp-suspend; - }; -}; - -&pruss1_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi deleted file mode 100644 index 415210b034ef..000000000000 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ /dev/null @@ -1,2584 +0,0 @@ -&l4_wkup { /* 0x44c00000 */ - compatible = "ti,am4-l4-wkup", "simple-pm-bus"; - power-domains = <&prm_wkup>; - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x44c00000 0x800>, - <0x44c00800 0x800>, - <0x44c01000 0x400>, - <0x44c01400 0x400>; - reg-names = "ap", "la", "ia0", "ia1"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ - <0x00100000 0x44d00000 0x100000>, /* segment 1 */ - <0x00200000 0x44e00000 0x100000>; /* segment 2 */ - - segment@0 { /* 0x44c00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>; /* ap 3 */ - }; - - segment@100000 { /* 0x44d00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ - <0x00004000 0x00104000 0x001000>, /* ap 5 */ - <0x00080000 0x00180000 0x002000>, /* ap 6 */ - <0x00082000 0x00182000 0x001000>, /* ap 7 */ - <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ - - target-module@0 { /* 0x44d00000, ap 4 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x0 0x4>; - reg-names = "rev"; - clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x4000>, - <0x00080000 0x00080000 0x2000>; - - wkup_m3: cpu@0 { - compatible = "ti,am4372-wkup-m3"; - reg = <0x00000000 0x4000>, - <0x00080000 0x2000>; - reg-names = "umem", "dmem"; - resets = <&prm_wkup 3>; - reset-names = "rstctrl"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - }; - - target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf0000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0000 0x10000>; - - prcm: prcm@0 { - compatible = "ti,am4-prcm", "simple-bus"; - reg = <0x0 0x11000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - }; - }; - - segment@200000 { /* 0x44e00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ - <0x00003000 0x00203000 0x001000>, /* ap 10 */ - <0x00004000 0x00204000 0x001000>, /* ap 11 */ - <0x00005000 0x00205000 0x001000>, /* ap 12 */ - <0x00006000 0x00206000 0x001000>, /* ap 13 */ - <0x00007000 0x00207000 0x001000>, /* ap 14 */ - <0x00008000 0x00208000 0x001000>, /* ap 15 */ - <0x00009000 0x00209000 0x001000>, /* ap 16 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ - <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ - <0x00010000 0x00210000 0x010000>, /* ap 22 */ - <0x00030000 0x00230000 0x001000>, /* ap 23 */ - <0x00031000 0x00231000 0x001000>, /* ap 24 */ - <0x00032000 0x00232000 0x001000>, /* ap 25 */ - <0x00033000 0x00233000 0x001000>, /* ap 26 */ - <0x00034000 0x00234000 0x001000>, /* ap 27 */ - <0x00035000 0x00235000 0x001000>, /* ap 28 */ - <0x00036000 0x00236000 0x001000>, /* ap 29 */ - <0x00037000 0x00237000 0x001000>, /* ap 30 */ - <0x00038000 0x00238000 0x001000>, /* ap 31 */ - <0x00039000 0x00239000 0x001000>, /* ap 32 */ - <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ - <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ - <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ - <0x00040000 0x00240000 0x040000>, /* ap 36 */ - <0x00080000 0x00280000 0x001000>, /* ap 37 */ - <0x00088000 0x00288000 0x008000>, /* ap 38 */ - <0x00092000 0x00292000 0x001000>, /* ap 39 */ - <0x00086000 0x00286000 0x001000>, /* ap 40 */ - <0x00087000 0x00287000 0x001000>, /* ap 41 */ - <0x00090000 0x00290000 0x001000>, /* ap 42 */ - <0x00091000 0x00291000 0x001000>; /* ap 43 */ - - target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - - target-module@5000 { /* 0x44e05000, ap 12 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - }; - - target-module@7000 { /* 0x44e07000, ap 14 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7000 0x4>, - <0x7010 0x4>, - <0x7114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, - <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - - gpio0: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@9000 { /* 0x44e09000, ap 16 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9050 0x4>, - <0x9054 0x4>, - <0x9058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9000 0x1000>; - - uart0: serial@0 { - compatible = "ti,am4372-uart"; - reg = <0x0 0x2000>; - interrupts = ; - }; - }; - - target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xb000 0x8>, - <0xb010 0x8>, - <0xb090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb000 0x1000>; - - i2c0: i2c@0 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd000 0x4>, - <0xd010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ - clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd000 0x1000>; - - tscadc: tscadc@0 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x1000>; - interrupts = ; - clocks = <&adc_tsc_fck>; - clock-names = "fck"; - status = "disabled"; - dmas = <&edma 53 0>, <&edma 57 0>; - dma-names = "fifo0", "fifo1"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - - }; - }; - - target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x10000 0x4>; - reg-names = "rev"; - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x10000>; - - scm: scm@0 { - compatible = "ti,am4-scm", "simple-bus"; - reg = <0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x4000>; - - am43xx_pinmux: pinmux@800 { - compatible = "ti,am437-padconf", - "pinctrl-single"; - reg = <0x800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,am43xx-phy-gmii-sel"; - reg = <0x650 0x4>; - #phy-cells = <2>; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am4372-wkup-m3-ipc"; - reg = <0x1324 0x44>; - interrupts = ; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; - }; - - timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x31000 0x4>, - <0x31010 0x4>, - <0x31014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x31000 0x1000>; - - timer1: timer@0 { - compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - }; - - target-module@33000 { /* 0x44e33000, ap 26 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x33000 0x1000>; - }; - - target-module@35000 { /* 0x44e35000, ap 28 50.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x35000 0x4>, - <0x35010 0x4>, - <0x35014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x35000 0x1000>; - - wdt: wdt@0 { - compatible = "ti,am4372-wdt","ti,omap3-wdt"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@37000 { /* 0x44e37000, ap 30 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x37000 0x1000>; - }; - - target-module@39000 { /* 0x44e39000, ap 32 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x39000 0x1000>; - }; - - rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x3e074 0x4>, - <0x3e078 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ - power-domains = <&prm_rtc>; - clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - rtc: rtc@0 { - compatible = "ti,am4372-rtc", "ti,am3352-rtc", - "ti,da830-rtc"; - reg = <0x0 0x1000>; - interrupts = ; - clocks = <&clk_32768_ck>; - clock-names = "int-clk"; - system-power-controller; - status = "disabled"; - }; - }; - - target-module@40000 { /* 0x44e40000, ap 36 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x40000>; - }; - - target-module@86000 { /* 0x44e86000, ap 40 70.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x86000 0x4>, - <0x86004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ - clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,am4372-counter32k","ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@88000 { /* 0x44e88000, ap 38 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00088000 0x00008000>, - <0x00008000 0x00090000 0x00001000>, - <0x00009000 0x00091000 0x00001000>; - }; - }; -}; - -&l4_fast { /* 0x4a000000 */ - compatible = "ti,am4-l4-fast", "simple-pm-bus"; - power-domains = <&prm_per>; - clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x400>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00100000 0x00100000 0x008000>, /* ap 3 */ - <0x00108000 0x00108000 0x001000>, /* ap 4 */ - <0x00400000 0x00400000 0x002000>, /* ap 5 */ - <0x00402000 0x00402000 0x001000>, /* ap 6 */ - <0x00200000 0x00200000 0x080000>, /* ap 7 */ - <0x00280000 0x00280000 0x001000>; /* ap 8 */ - - target-module@100000 { /* 0x4a100000, ap 3 04.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x101200 0x4>, - <0x101208 0x4>, - <0x101204 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x8000>; - - mac_sw: switch@0 { - compatible = "ti,am4372-cpsw-switch", "ti,cpsw-switch"; - reg = <0x0 0x4000>; - ranges = <0 0 0x4000>; - clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>; - clock-names = "fck", "50mclk"; - assigned-clocks = <&dpll_clksel_mac_clk>; - assigned-clock-rates = <50000000>; - #address-cells = <1>; - #size-cells = <1>; - syscon = <&scm_conf>; - status = "disabled"; - - interrupts = ; - interrupt-names = "rx_thresh", "rx", "tx", "misc"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - label = "port1"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 0>; - }; - - cpsw_port2: port@2 { - reg = <2>; - label = "port2"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 0>; - }; - }; - - davinci_mdio_sw: mdio@1000 { - compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&cpsw_125mhz_gclk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpts { - clocks = <&cpsw_cpts_rft_clk>; - clock-names = "cpts"; - }; - }; - }; - - target-module@200000 { /* 0x4a200000, ap 7 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x200000 0x80000>; - }; - - target-module@400000 { /* 0x4a400000, ap 5 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x400000 0x2000>; - }; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,am4-l4-per", "simple-pm-bus"; - power-domains = <&prm_per>; - clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ - <0x00100000 0x48100000 0x100000>, /* segment 1 */ - <0x00200000 0x48200000 0x100000>, /* segment 2 */ - <0x00300000 0x48300000 0x100000>, /* segment 3 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>, /* ap 3 */ - <0x00001800 0x00001800 0x000400>, /* ap 4 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ - <0x00008000 0x00008000 0x001000>, /* ap 6 */ - <0x00009000 0x00009000 0x001000>, /* ap 7 */ - <0x00022000 0x00022000 0x001000>, /* ap 8 */ - <0x00023000 0x00023000 0x001000>, /* ap 9 */ - <0x00024000 0x00024000 0x001000>, /* ap 10 */ - <0x00025000 0x00025000 0x001000>, /* ap 11 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ - <0x00038000 0x00038000 0x002000>, /* ap 14 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ - <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ - <0x00040000 0x00040000 0x001000>, /* ap 18 */ - <0x00041000 0x00041000 0x001000>, /* ap 19 */ - <0x00042000 0x00042000 0x001000>, /* ap 20 */ - <0x00043000 0x00043000 0x001000>, /* ap 21 */ - <0x00044000 0x00044000 0x001000>, /* ap 22 */ - <0x00045000 0x00045000 0x001000>, /* ap 23 */ - <0x00046000 0x00046000 0x001000>, /* ap 24 */ - <0x00047000 0x00047000 0x001000>, /* ap 25 */ - <0x00048000 0x00048000 0x001000>, /* ap 26 */ - <0x00049000 0x00049000 0x001000>, /* ap 27 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ - <0x00060000 0x00060000 0x001000>, /* ap 30 */ - <0x00061000 0x00061000 0x001000>, /* ap 31 */ - <0x00080000 0x00080000 0x010000>, /* ap 32 */ - <0x00090000 0x00090000 0x001000>, /* ap 33 */ - <0x00030000 0x00030000 0x001000>, /* ap 65 */ - <0x00031000 0x00031000 0x001000>, /* ap 66 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ - <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ - <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ - <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ - <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ - <0x00034000 0x00034000 0x001000>, /* ap 80 */ - <0x00035000 0x00035000 0x001000>, /* ap 81 */ - <0x00036000 0x00036000 0x001000>, /* ap 84 */ - <0x00037000 0x00037000 0x001000>, /* ap 85 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - target-module@8000 { /* 0x48008000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@22000 { /* 0x48022000, ap 8 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x22050 0x4>, - <0x22054 0x4>, - <0x22058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - uart1: serial@0 { - compatible = "ti,am4372-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x48024000, ap 10 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x24050 0x4>, - <0x24054 0x4>, - <0x24058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - uart2: serial@0 { - compatible = "ti,am4372-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2a000 0x8>, - <0x2a010 0x8>, - <0x2a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x48030000, ap 65 08.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x30000 0x4>, - <0x30110 0x4>, - <0x30114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - - spi0: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@34000 { /* 0x48034000, ap 80 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - }; - - target-module@36000 { /* 0x48036000, ap 84 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@38000 { /* 0x48038000, ap 14 04.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x38000 0x4>, - <0x38004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x2000>, - <0x46000000 0x46000000 0x400000>; - - mcasp0: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - }; - - target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x2000>, - <0x46400000 0x46400000 0x400000>; - - mcasp1: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - }; - - timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>, - <0x40014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - timer2: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - }; - - target-module@42000 { /* 0x48042000, ap 20 24.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x42000 0x4>, - <0x42010 0x4>, - <0x42014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - timer3: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@44000 { /* 0x48044000, ap 22 26.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x44000 0x4>, - <0x44010 0x4>, - <0x44014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - - timer4: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@46000 { /* 0x48046000, ap 24 28.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x46000 0x4>, - <0x46010 0x4>, - <0x46014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - - timer5: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@48000 { /* 0x48048000, ap 26 1a.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x48000 0x4>, - <0x48010 0x4>, - <0x48014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - - timer6: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x4a000 0x4>, - <0x4a010 0x4>, - <0x4a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - - timer7: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4c000 0x4>, - <0x4c010 0x4>, - <0x4c114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@60000 { /* 0x48060000, ap 30 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x602fc 0x4>, - <0x60110 0x4>, - <0x60114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,am437-sdhci"; - reg = <0x0 0x1000>; - ti,needs-special-reset; - dmas = <&edma 24 0>, - <&edma 25 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48080000, ap 32 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x80000 0x4>, - <0x80010 0x4>, - <0x80014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0x2000>; - interrupts = ; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc8000 0x4>, - <0xc8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: mbox-wkup-m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - }; - - target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xca000 0x4>, - <0xca010 0x4>, - <0xca014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xca000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x48100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ - <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ - <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ - <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ - <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ - <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ - <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ - <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ - <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ - <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ - <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ - <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ - <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ - <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ - <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ - <0x000af000 0x001af000 0x001000>, /* ap 49 */ - <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ - <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ - <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ - <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ - <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ - <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ - <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ - <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ - <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ - <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ - <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ - <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ - <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ - <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ - - target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8c000 0x1000>; - }; - - target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8e000 0x1000>; - }; - - target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9c000 0x8>, - <0x9c010 0x8>, - <0x9c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa0000 0x4>, - <0xa0110 0x4>, - <0xa0114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x1000>; - - spi1: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa2000 0x4>, - <0xa2110 0x4>, - <0xa2114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - - spi2: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa4000 0x4>, - <0xa4110 0x4>, - <0xa4114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa4000 0x1000>; - - spi3: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa6050 0x4>, - <0xa6054 0x4>, - <0xa6058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa6000 0x1000>; - - uart3: serial@0 { - compatible = "ti,am4372-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa8050 0x4>, - <0xa8054 0x4>, - <0xa8058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x1000>; - - uart4: serial@0 { - compatible = "ti,am4372-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xaa050 0x4>, - <0xaa054 0x4>, - <0xaa058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xaa000 0x1000>; - - uart5: serial@0 { - compatible = "ti,am4372-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xac000 0x4>, - <0xac010 0x4>, - <0xac114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xac000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xae000 0x4>, - <0xae010 0x4>, - <0xae114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xae000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0xc1000 0x4>, - <0xc1010 0x4>, - <0xc1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc1000 0x1000>; - - timer8: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xcc020 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, - <&dcan0_fck>; - clock-names = "fck", "osc"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xcc000 0x2000>; - - dcan0: can@0 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0 0x2000>; - clocks = <&dcan0_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd0020 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, - <&dcan1_fck>; - clock-names = "fck", "osc"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000 0x2000>; - - dcan1: can@0 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0 0x2000>; - clocks = <&dcan1_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xd82fc 0x4>, - <0xd8110 0x4>, - <0xd8114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd8000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,am437-sdhci"; - reg = <0x0 0x1000>; - ti,needs-special-reset; - dmas = <&edma 2 0>, - <&edma 3 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00200000 0x010000>; - - target-module@0 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - power-domains = <&prm_mpu>; - clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x10000>; - - mpu@0 { - compatible = "ti,omap4-mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; - }; - }; - }; - - segment@300000 { /* 0x48300000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ - <0x00001000 0x00301000 0x001000>, /* ap 57 */ - <0x00002000 0x00302000 0x001000>, /* ap 58 */ - <0x00003000 0x00303000 0x001000>, /* ap 59 */ - <0x00004000 0x00304000 0x001000>, /* ap 60 */ - <0x00005000 0x00305000 0x001000>, /* ap 61 */ - <0x00018000 0x00318000 0x004000>, /* ap 62 */ - <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ - <0x00010000 0x00310000 0x002000>, /* ap 64 */ - <0x00028000 0x00328000 0x001000>, /* ap 75 */ - <0x00029000 0x00329000 0x001000>, /* ap 76 */ - <0x00012000 0x00312000 0x001000>, /* ap 79 */ - <0x00020000 0x00320000 0x001000>, /* ap 82 */ - <0x00021000 0x00321000 0x001000>, /* ap 83 */ - <0x00026000 0x00326000 0x001000>, /* ap 86 */ - <0x00027000 0x00327000 0x001000>, /* ap 87 */ - <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ - <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ - <0x00013000 0x00313000 0x001000>, /* ap 90 */ - <0x00014000 0x00314000 0x001000>, /* ap 91 */ - <0x00006000 0x00306000 0x001000>, /* ap 96 */ - <0x00007000 0x00307000 0x001000>, /* ap 97 */ - <0x00008000 0x00308000 0x001000>, /* ap 98 */ - <0x00009000 0x00309000 0x001000>, /* ap 99 */ - <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ - <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ - <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ - <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ - <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ - <0x00040000 0x00340000 0x001000>, /* ap 105 */ - <0x00041000 0x00341000 0x001000>, /* ap 106 */ - <0x00042000 0x00342000 0x001000>, /* ap 107 */ - <0x00045000 0x00345000 0x001000>, /* ap 108 */ - <0x00046000 0x00346000 0x001000>, /* ap 109 */ - <0x00047000 0x00347000 0x001000>, /* ap 110 */ - <0x00048000 0x00348000 0x001000>, /* ap 111 */ - <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ - <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ - <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ - <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ - <0x00022000 0x00322000 0x001000>, /* ap 116 */ - <0x00023000 0x00323000 0x001000>, /* ap 117 */ - <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ - <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ - <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ - <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ - <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ - <0x00080000 0x00380000 0x020000>, /* ap 123 */ - <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ - <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ - <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ - <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ - <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ - <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ - - target-module@0 { /* 0x48300000, ap 56 40.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x0 0x4>, - <0x4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - epwmss0: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ecap0: pwm@100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm0: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@2000 { /* 0x48302000, ap 58 4a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - epwmss1: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ecap1: pwm@100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm1: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@4000 { /* 0x48304000, ap 60 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - epwmss2: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ecap2: pwm@100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm2: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@6000 { /* 0x48306000, ap 96 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>, - <0x6004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - - epwmss3: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ehrpwm3: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@8000 { /* 0x48308000, ap 98 54.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>, - <0x8004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - epwmss4: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ehrpwm4: pwm@48308200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@a000 { /* 0x4830a000, ap 100 60.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>, - <0xa004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - epwmss5: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ehrpwm5: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@10000 { /* 0x48310000, ap 64 4e.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x11fe0 0x4>, - <0x11fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - }; - }; - - target-module@13000 { /* 0x48313000, ap 90 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x13000 0x1000>; - }; - - target-module@18000 { /* 0x48318000, ap 62 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x4000>; - }; - - target-module@20000 { /* 0x48320000, ap 82 34.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20000 0x4>, - <0x20010 0x4>, - <0x20114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x22000 0x4>, - <0x22010 0x4>, - <0x22114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x48326000, ap 86 66.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x26000 0x4>, - <0x26104 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - - vpfe0: vpfe@0 { - compatible = "ti,am437x-vpfe"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x48328000, ap 75 0e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x28000 0x4>, - <0x28104 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - - vpfe1: vpfe@0 { - compatible = "ti,am437x-vpfe"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2a000 0x4>, - <0x2a010 0x4>, - <0x2a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, dss_clkdm */ - clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x0002a000 0x00000400>, - <0x00000400 0x0002a400 0x00000400>, - <0x00000800 0x0002a800 0x00000400>, - <0x00000c00 0x0002ac00 0x00000400>, - <0x00001000 0x0002b000 0x00001000>; - - dss: dss@0 { - compatible = "ti,omap3-dss"; - reg = <0 0x200>; - status = "disabled"; - clocks = <&disp_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00000400>, - <0x00000400 0x00000400 0x00000400>, - <0x00000800 0x00000800 0x00000400>, - <0x00000c00 0x00000c00 0x00000400>, - <0x00001000 0x00001000 0x00001000>; - - target-module@400 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x400 0x4>, - <0x410 0x4>, - <0x414 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-midle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x400>; - - dispc: dispc@0 { - compatible = "ti,omap3-dispc"; - reg = <0 0x400>; - interrupts = ; - clocks = <&disp_clk>; - clock-names = "fck"; - - max-memory-bandwidth = <230000000>; - }; - }; - - target-module@800 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x800 0x4>, - <0x810 0x4>, - <0x814 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x400>; - - rfbi: rfbi@0 { - compatible = "ti,omap3-rfbi"; - reg = <0 0x100>; - clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; - clock-names = "fck"; - status = "disabled"; - }; - }; - }; - }; - - target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3d000 0x4>, - <0x3d010 0x4>, - <0x3d014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3d000 0x1000>; - - timer9: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3f000 0x4>, - <0x3f010 0x4>, - <0x3f014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3f000 0x1000>; - - timer10: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@41000 { /* 0x48341000, ap 106 76.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x41000 0x4>, - <0x41010 0x4>, - <0x41014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x41000 0x1000>; - - timer11: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@45000 { /* 0x48345000, ap 108 6a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x45000 0x4>, - <0x45110 0x4>, - <0x45114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x45000 0x1000>; - - spi4: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@47000 { /* 0x48347000, ap 110 70.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x47000 0x4>, - <0x47014 0x4>, - <0x47018 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47000 0x1000>; - - hdq: hdq@0 { - compatible = "ti,am4372-hdq"; - reg = <0x0 0x1000>; - interrupts = ; - clocks = <&func_12m_clk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4c000 0x4>, - <0x4c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x2000>; - - magadc: magadc@0 { - compatible = "ti,am4372-magadc"; - reg = <0x0 0x2000>; - interrupts = ; - clocks = <&adc_mag_fck>; - clock-names = "fck"; - dmas = <&edma 54 0>, <&edma 55 0>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - mag { - compatible = "ti,am4372-mag"; - }; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am4372-adc"; - }; - }; - }; - - target-module@80000 { /* 0x48380000, ap 123 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x80000 0x4>, - <0x80010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x20000>; - - dwc3_1: omap_dwc3@0 { - compatible = "ti,am437x-dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges = <0 0 0x20000>; - - usb1: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa8000 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x8000>; - - ocp2scp0: ocp2scp@0 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - - usb2_phy1: phy@8000 { - compatible = "ti,am437x-usb2"; - reg = <0x0 0x8000>; - syscon-phy-power = <&scm_conf 0x620>; - clocks = <&usb_phy0_always_on_clk32k>, - <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc0000 0x4>, - <0xc0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x20000>; - - dwc3_2: omap_dwc3@0 { - compatible = "ti,am437x-dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges = <0 0 0x20000>; - - usb2: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xe8000 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe8000 0x8000>; - - ocp2scp1: ocp2scp@0 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - - usb2_phy2: phy@8000 { - compatible = "ti,am437x-usb2"; - reg = <0x0 0x8000>; - syscon-phy-power = <&scm_conf 0x628>; - clocks = <&usb_phy1_always_on_clk32k>, - <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf2000 0x2000>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts deleted file mode 100644 index 34a5407bee15..000000000000 --- a/arch/arm/boot/dts/am437x-sbc-t43.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - */ - -#include "am437x-cm-t43.dts" -#include "compulab-sb-som.dtsi" - -/ { - model = "CompuLab CM-T43 on SB-SOM-T43"; - compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; - - aliases { - display0 = &lcd0; - }; -}; - -&am43xx_pinmux { - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ - >; - }; - - dss_pinctrl_default: dss-pinctrl-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ - AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9b8, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9bc, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c0, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c4, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c8, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam1 data 9 -> DSS DATA 16 */ - - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - uart0_pins_default: uart0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ - AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - usb2_phy1_default: usb2-phy1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy2_default: usb2-phy2-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom_base: at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&mmc1 { - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vsb_3v3>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pinctrl_default>; - - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_default>; -}; - -&dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_phy1_default>; -}; - -&dwc3_2 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_phy2_default>; -}; - -&lcd0 { - enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH - &gpio4 28 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - data-lines = <24>; - }; - }; -}; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts deleted file mode 100644 index 9c97006ffd5b..000000000000 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ /dev/null @@ -1,902 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* AM437x SK EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "TI AM437x SK EVM"; - compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart0; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM437x-SK-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_pins>; - - debounce-delay-ms = <5>; - col-scan-delay-us = <5>; - - row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ - &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ - - col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ - &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ - - linux,keymap = < - MATRIX_KEY(0, 0, KEY_DOWN) - MATRIX_KEY(0, 1, KEY_RIGHT) - MATRIX_KEY(1, 0, KEY_LEFT) - MATRIX_KEY(1, 1, KEY_UP) - >; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - led0 { - label = "am437x-sk:red:heartbeat"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "am437x-sk:green:mmc1"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "am437x-sk:blue:cpu0"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led3 { - label = "am437x-sk:blue:usr3"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ - default-state = "off"; - }; - }; - - lcd0: display { - compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - backlight = <&lcd_bl>; - - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - /* - * WL_EN is not SDIO standard compliant. It is an out of band - * signal and hard to be dealt with in a standard way by the - * SDIO core driver. - * So modelling the WL_EN line as a regulator was a natural - * choice as the MMC core already deals with MMC supplies. - */ - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&am43xx_pinmux { - matrix_keypad_pins: matrix-keypad-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ - AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ - AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ - AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ - >; - }; - - leds_pins: leds-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ - AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ - AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ - AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - ecap0_pins: backlight-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ - >; - }; - - edt_ft5306_ts_pins: edt-ft5306-ts-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ - >; - }; - - vpfe0_pins_default: vpfe0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ - AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ - >; - }; - - vpfe0_pins_sleep: vpfe0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - >; - }; - - clkout1_pin: clkout1-pins { - pinctrl-single,pins = < - 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ - - /* Slave 2 */ - AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ - AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value */ - AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - dss_pins: dss-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ - - >; - }; - - qspi_pins: qspi-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ - >; - }; - - mcasp1_pins: mcasp1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - lcd_pins: lcd-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ - >; - }; - - usb1_pins: usb1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - >; - }; - - usb2_pins: usb2-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - >; - }; - - mmc3_pins_default: mmc3-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */ - >; - }; - - mmc3_pins_sleep: mmc3-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */ - >; - }; - - wlan_pins_default: wlan-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ - AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ - >; - }; - - wlan_pins_sleep: wlan-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ - AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ - >; - }; - - uart1_bt_pins_default: uart1-bt-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ - >; - }; - - uart1_bt_pins_sleep: uart1-bt-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ - AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ - AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ - AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps@24 { - compatible = "ti,tps65218"; - reg = <0x24>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - /* VDD_CORE limits min of OPP50 and max of OPP100 */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdds_ddr"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc4: regulator-dcdc4 { - regulator-name = "v3_3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1: regulator-ldo1 { - regulator-name = "v1_8d"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - power-button { - compatible = "ti,tps65218-pwrbutton"; - status = "okay"; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&clkout1_pin>; - - clocks = <&clkout1_mux_ck>; - clock-names = "xvclk"; - assigned-clocks = <&clkout1_mux_ck>; - assigned-clock-parents = <&clkout1_osc_div_ck>; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; - - edt-ft5306@38 { - status = "okay"; - compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; - pinctrl-names = "default"; - pinctrl-0 = <&edt_ft5306_ts_pins>; - - reg = <0x38>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - - reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - - wakeup-source; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&dcdc4>; - IOVDD-supply = <&dcdc4>; - DRVDD-supply = <&dcdc4>; - DVDD-supply = <&ldo1>; - }; - - lis331dlh@18 { - compatible = "st,lis331dlh"; - reg = <0x18>; - status = "okay"; - - Vdd-supply = <&dcdc4>; - Vdd_IO-supply = <&dcdc4>; - interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - vmmc-supply = <&dcdc4>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_bt_pins_default>; - pinctrl-1 = <&uart1_bt_pins_sleep>; -}; - -&mmc3 { - status = "okay"; - /* - * these are on the crossbar and are outlined in the - * xbar-event-map element - */ - dmas = <&edma_xbar 30 0 1>, - <&edma_xbar 31 0 2>; - dma-names = "tx", "rx"; - vmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc3_pins_default>; - pinctrl-1 = <&mmc3_pins_sleep>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default>; - pinctrl-1 = <&wlan_pins_sleep>; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - - spi-max-frequency = <48000000>; - flash@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first 512KiB - * for a valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x00080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - - ethphy1: ethernet-phy@5 { - reg = <5>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <2>; -}; - -&elm { - status = "okay"; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; - tdm-slots = <2>; - serial-dir = < - 0 0 1 2 - >; - - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint@0 { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; - -&vpfe0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe0_pins_default>; - pinctrl-1 = <&vpfe0_pins_sleep>; - - /* Camera port */ - port { - vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&wkup_m3_ipc { - firmware-name = "am43x-evm-scale-data.bin"; -}; - -&pruss1_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts deleted file mode 100644 index 9193a4cfba78..000000000000 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ /dev/null @@ -1,1028 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* AM43x EPOS EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM43x EPOS EVM"; - compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart0; - }; - - vmmcsd_fixed: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lcd0: display { - compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; - label = "lcd"; - - backlight = <&lcd_bl>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&matrix_keypad_default>; - pinctrl-1 = <&matrix_keypad_sleep>; - wakeup-source; - - row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ - &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ - &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ - &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ - - col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ - &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ - &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ - &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x01000204 /* P4 */ - 0x02000207 /* P7 */ - 0x0300020a /* NUMERIC_STAR */ - 0x00010202 /* P2 */ - 0x01010205 /* P5 */ - 0x02010208 /* P8 */ - 0x03010200 /* P0 */ - 0x00020203 /* P3 */ - 0x01020206 /* P6 */ - 0x02020209 /* P9 */ - 0x0302020b /* NUMERIC_POUND */ - 0x00030067 /* UP */ - 0x0103006a /* RIGHT */ - 0x0203006c /* DOWN */ - 0x03030069>; /* LEFT */ - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM43-EPOS-EVM"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MIC1LP", "Microphone Jack", - "MIC1RP", "Microphone Jack", - "MIC1LP", "MICBIAS", - "MIC1RP", "MICBIAS", - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Speaker", "SPL", - "Speaker", "SPR"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-frequency = <12000000>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3111>; - system-clock-frequency = <12000000>; - }; - }; - - audio_mstrclk: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&unused_pins>; - - unused_pins: unused-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - cpsw_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ - >; - }; - - cpsw_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - nand_flash_x8_default: nand-flash-x8-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ - AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - nand_flash_x8_sleep: nand-flash-x8-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - ecap0_pins_default: backlight-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - ecap0_pins_sleep: backlight-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ - >; - }; - - spi0_pins_default: spi0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ - AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; - - spi0_pins_sleep: spi0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - spi1_pins_default: spi1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ - AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ - >; - }; - - spi1_pins_sleep: spi1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc1_pins_sleep: mmc1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) - >; - }; - - matrix_keypad_default: matrix-keypad-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ - AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ - AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ - AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ - AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ - AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ - AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ - >; - }; - - matrix_keypad_sleep: matrix-keypad-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - qspi1_pins_default: qspi1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - qspi1_pins_sleep: qspi1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - pixcir_ts_pins_default: pixcir-ts-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ - >; - }; - - pixcir_ts_pins_sleep: pixcir-ts-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ - >; - }; - - hdq_pins: hdq-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ - >; - }; - - dss_pins: dss-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - >; - }; - - display_mux_pins: display-mux-pins { - pinctrl-single,pins = < - /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ - AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - vpfe1_pins_default: vpfe1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ - AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ - AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ - AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ - AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ - >; - }; - - vpfe1_pins_sleep: vpfe1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - >; - }; - - uart0_pins_default: uart0-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart0_pins_sleep: uart0-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) - AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) - >; - }; - - usb2_phy1_default: usb2-phy1-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy1_sleep: usb2-phy1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - usb2_phy2_default: usb2-phy2-default-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy2_sleep: usb2-phy2-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mcasp1_pins: mcasp1-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ - AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ - AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ - AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ - >; - }; - - mcasp1_sleep_pins: mcasp1-sleep-pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_sleep>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mac_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethphy0: ethernet-phy@16 { - reg = <16>; - }; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - phys = <&phy_gmii_sel 1 1>; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc4: regulator-dcdc4 { - regulator-name = "vdcdc4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - pixcir_ts@5c { - compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pixcir_ts_pins_default>; - pinctrl-1 = <&pixcir_ts_pins_sleep>; - - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - - attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; - - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - }; - - tlv320aic3111: tlv320aic3111@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3111"; - reg = <0x18>; - status = "okay"; - - ai31xx-micbias-vg = ; - - /* Regulators */ - HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ - SPRVDD-supply = <&vbat>; /* vbat */ - SPLVDD-supply = <&vbat>; /* vbat */ - AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ - IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ - DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&audio_mstrclk>; - clock-names = "xvclk"; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe1_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&display_mux_pins>; - status = "okay"; - - sel-lcd-hdmi-hog { - /* - * SelLCDorHDMI selects between display and audio paths: - * Low: HDMI display with audio via HDMI - * High: LCD display with analog audio via aic3111 codec - */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "SelLCDorHDMI"; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&nand_flash_x8_default>; - pinctrl-1 = <&nand_flash_x8_sleep>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ - gpmc,cs-wr-off-ns = <40>; - gpmc,adv-on-ns = <0>; /* cs-on-ns */ - gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ - gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ - gpmc,we-on-ns = <0>; /* cs-on-ns */ - gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ - gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ - gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ - gpmc,access-ns = <30>; /* tCEA + 4*/ - gpmc,rd-cycle-ns = <40>; - gpmc,wr-cycle-ns = <40>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00040000 0x00040000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x000C0000 0x00040000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00100000 0x00080000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x00180000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x00280000 0x00040000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x002C0000 0x00040000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00300000 0x00700000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x1f600000>; - }; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&rtc_target { - status = "disabled"; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&ecap0_pins_default>; - pinctrl-1 = <&ecap0_pins_sleep>; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi0_pins_default>; - pinctrl-1 = <&spi0_pins_sleep>; - ti,pindir-d0-out-d1-in; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_default>; - pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in; -}; - -&usb2_phy1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb2_phy1_default>; - pinctrl-1 = <&usb2_phy1_sleep>; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb2_phy2_default>; - pinctrl-1 = <&usb2_phy2_sleep>; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; -}; - -&qspi { - status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi1_pins_default>; - pinctrl-1 = <&qspi1_pins_sleep>; - - spi-max-frequency = <48000000>; - flash@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first 512KiB - * for a valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x00080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&hdq { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&vpfe1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe1_pins_default>; - pinctrl-1 = <&vpfe1_pins_sleep>; - - port { - vpfe1_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_pins_default>; - pinctrl-1 = <&uart0_pins_sleep>; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_sleep_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mux_synctimer32k_ck { - assigned-clocks = <&mux_synctimer32k_ck>; - assigned-clock-parents = <&clkdiv32k_ick>; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; - -&wkup_m3_ipc { - firmware-name = "am43x-evm-scale-data.bin"; -}; - -&pruss1_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi deleted file mode 100644 index 9a5437b3d6a8..000000000000 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ /dev/null @@ -1,1003 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM43xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - sys_clkin_ck: clock-sys-clkin-31@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sys_clkin_ck"; - clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; - ti,bit-shift = <31>; - reg = <0x0040>; - }; - - crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "crystal_freq_sel_ck"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <29>; - reg = <0x0040>; - }; - - sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sysboot_freq_sel_ck"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: clock-adc-tsc-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "adc_tsc_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: clock-dcan0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dcan0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: clock-dcan1-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dcan1_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: clock-mcasp0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mcasp0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: clock-mcasp1-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mcasp1_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: clock-smartreflex0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "smartreflex0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: clock-smartreflex1-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "smartreflex1_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: clock-sha0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "sha0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: clock-aes0-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "aes0_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: clock-rng-fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "rng_fck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm0_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm1_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm2_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; - - ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm3_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <4>; - reg = <0x0664>; - }; - - ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm4_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <5>; - reg = <0x0664>; - }; - - ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm5_tbclk"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <6>; - reg = <0x0664>; - }; -}; -&prcm_clocks { - clk_32768_ck: clock-clk-32768 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "clk_32768_ck"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clock-clk-rc32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "clk_rc32k_ck"; - clock-frequency = <32768>; - }; - - virt_19200000_ck: clock-virt-19200000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_19200000_ck"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: clock-virt-24000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_24000000_ck"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: clock-virt-25000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_25000000_ck"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: clock-virt-26000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_26000000_ck"; - clock-frequency = <26000000>; - }; - - tclkin_ck: clock-tclkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "tclkin_ck"; - clock-frequency = <26000000>; - }; - - dpll_core_ck: clock@2d20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clock-output-names = "dpll_core_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; - }; - - dpll_core_x2_ck: clock-dpll-core-x2 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clock-output-names = "dpll_core_x2_ck"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m4_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d38>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m5_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d3c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m6_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d40>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_mpu_ck: clock@2d60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clock-output-names = "dpll_mpu_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; - }; - - dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_mpu_m2_ck"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_periphclk: clock-mpu-periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mpu_periphclk"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_ddr_ck: clock@2da0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clock-output-names = "dpll_ddr_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; - }; - - dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_ddr_m2_ck"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_disp_ck: clock@2e20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clock-output-names = "dpll_disp_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; - }; - - dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_disp_m2_ck"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2e30>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - ti,set-rate-parent; - }; - - dpll_per_ck: clock@2de0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-j-type-clock"; - clock-output-names = "dpll_per_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; - }; - - dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2_ck"; - clocks = <&dpll_per_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2df0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_per_m2_div4_ck"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - clk_24mhz: clock-clk-24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "clk_24mhz"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clock-clkdiv32k { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "clkdiv32k_ck"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "clkdiv32k_ick"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <8>; - reg = <0x2a38>; - }; - - sysclk_div: clock-sysclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "sysclk_div"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "pruss_ocp_gclk"; - clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; - reg = <0x4248>; - }; - - clk_32k_tpm_ck: clock-clk-32k-tpm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "clk_32k_tpm_ck"; - clock-frequency = <32768>; - }; - - timer1_fck: clock-timer1-fck@4200 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer1_fck"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4200>; - }; - - timer2_fck: clock-timer2-fck@4204 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer2_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4204>; - }; - - timer3_fck: clock-timer3-fck@4208 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer3_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4208>; - }; - - timer4_fck: clock-timer4-fck@420c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer4_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x420c>; - }; - - timer5_fck: clock-timer5-fck@4210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer5_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4210>; - }; - - timer6_fck: clock-timer6-fck@4214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer6_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4214>; - }; - - timer7_fck: clock-timer7-fck@4218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer7_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4218>; - }; - - wdt1_fck: clock-wdt1-fck@422c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "wdt1_fck"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; - reg = <0x422c>; - }; - - adc_mag_fck: adc_mag_fck@424c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; - reg = <0x424c>; - }; - - l3_gclk: clock-l3-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l3_gclk"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_core_m4_div2_ck"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: clock-l4hs-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4hs_gclk"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: clock-l3s-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l3s_gclk"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: clock-l4ls-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4ls_gclk"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "cpsw_125mhz_gclk"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "cpsw_cpts_rft_clk"; - clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; - reg = <0x4238>; - }; - - dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_clksel_mac_clk"; - clocks = <&dpll_core_m5_ck>; - reg = <0x4234>; - ti,bit-shift = <2>; - ti,dividers = <2>, <5>; - }; - - clk_32k_mosc_ck: clock-clk-32k-mosc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "clk_32k_mosc_ck"; - clock-frequency = <32768>; - }; - - gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gpio0_dbclk_mux_ck"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; - reg = <0x4240>; - }; - - mmc_clk: clock-mmc { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mmc_clk"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gfx_fclk_clksel_ck"; - clocks = <&sysclk_div>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x423c>; - }; - - gfx_fck_div_ck: clock-gfx-fck-div@423c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "gfx_fck_div_ck"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x423c>; - ti,max-div = <2>; - }; - - disp_clk: clock-disp@4244 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "disp_clk"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x4244>; - ti,set-rate-parent; - }; - - dpll_extdev_ck: clock@2e60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clock-output-names = "dpll_extdev_ck"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; - }; - - dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_extdev_m2_ck"; - clocks = <&dpll_extdev_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2e70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "mux_synctimer32k_ck"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; - reg = <0x4230>; - }; - - timer8_fck: clock-timer8-fck@421c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer8_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x421c>; - }; - - timer9_fck: clock-timer9-fck@4220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer9_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4220>; - }; - - timer10_fck: clock-timer10-fck@4224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer10_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4224>; - }; - - timer11_fck: clock-timer11-fck@4228 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "timer11_fck"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4228>; - }; - - cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "cpsw_50m_clkdiv"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "cpsw_5m_clkdiv"; - clocks = <&cpsw_50m_clkdiv>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll_ddr_x2_ck: clock-dpll-ddr-x2 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clock-output-names = "dpll_ddr_x2_ck"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_ddr_m4_ck"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clock-output-names = "dpll_per_clkdcoldo"; - clocks = <&dpll_per_ck>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x2e14>; - ti,invert-autoidle-bit; - }; - - dll_aging_clk_div: clock-dll-aging-clk-div@4250 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dll_aging_clk_div"; - clocks = <&sys_clkin_ck>; - reg = <0x4250>; - ti,dividers = <8>, <16>, <32>; - }; - - div_core_25m_ck: clock-div-core-25m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "div_core_25m_ck"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_12m_clk: clock-func-12m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_12m_clk"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - vtp_clk_div: clock-vtp-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "vtp_clk_div"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "usbphy_32khz_clkmux"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4260>; - }; - - usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy0_always_on_clk32k"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a40>; - }; - - usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy1_always_on_clk32k"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a48>; - }; - - clkout1_osc_div_ck: clock-clkout1-osc-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "clkout1_osc_div_ck"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <20>; - ti,max-div = <4>; - reg = <0x4100>; - }; - - clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "clkout1_src2_mux_ck"; - clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, - <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, - <&dpll_mpu_m2_ck>; - reg = <0x4100>; - }; - - clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "clkout1_src2_pre_div_ck"; - clocks = <&clkout1_src2_mux_ck>; - ti,bit-shift = <4>; - ti,max-div = <8>; - reg = <0x4100>; - }; - - clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "clkout1_src2_post_div_ck"; - clocks = <&clkout1_src2_pre_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-power-of-two; - reg = <0x4100>; - }; - - clkout1_mux_ck: clock-clkout1-mux-ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "clkout1_mux_ck"; - clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, - <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; - ti,bit-shift = <16>; - reg = <0x4100>; - }; - - clkout1_ck: clock-clkout1-ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "clkout1_ck"; - clocks = <&clkout1_mux_ck>; - ti,bit-shift = <23>; - reg = <0x4100>; - }; -}; - -&prcm { - wkup_cm: clock@2800 { - compatible = "ti,omap4-cm"; - clock-output-names = "wkup_cm"; - reg = <0x2800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2800 0x400>; - - l3s_tsc_clkctrl: clock@120 { - compatible = "ti,clkctrl"; - clock-output-names = "l3s_tsc_clkctrl"; - reg = <0x120 0x4>; - #clock-cells = <2>; - }; - - l4_wkup_aon_clkctrl: clock@228 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_wkup_aon_clkctrl"; - reg = <0x228 0xc>; - #clock-cells = <2>; - }; - - l4_wkup_clkctrl: clock@220 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_wkup_clkctrl"; - reg = <0x220 0x4>, <0x328 0x44>; - #clock-cells = <2>; - }; - - }; - - mpu_cm: clock@8300 { - compatible = "ti,omap4-cm"; - clock-output-names = "mpu_cm"; - reg = <0x8300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8300 0x100>; - - mpu_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "mpu_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gfx_l3_cm: clock@8400 { - compatible = "ti,omap4-cm"; - clock-output-names = "gfx_l3_cm"; - reg = <0x8400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8400 0x100>; - - gfx_l3_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "gfx_l3_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l4_rtc_cm: clock@8500 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_rtc_cm"; - reg = <0x8500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8500 0x100>; - - l4_rtc_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_rtc_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - per_cm: clock@8800 { - compatible = "ti,omap4-cm"; - clock-output-names = "per_cm"; - reg = <0x8800 0xc00>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8800 0xc00>; - - l3_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_clkctrl"; - reg = <0x20 0x3c>, <0x78 0x2c>; - #clock-cells = <2>; - }; - - l3s_clkctrl: clock@68 { - compatible = "ti,clkctrl"; - clock-output-names = "l3s_clkctrl"; - reg = <0x68 0xc>, <0x220 0x4c>; - #clock-cells = <2>; - }; - - pruss_ocp_clkctrl: clock@320 { - compatible = "ti,clkctrl"; - clock-output-names = "pruss_ocp_clkctrl"; - reg = <0x320 0x4>; - #clock-cells = <2>; - }; - - l4ls_clkctrl: clock@420 { - compatible = "ti,clkctrl"; - clock-output-names = "l4ls_clkctrl"; - reg = <0x420 0x1a4>; - #clock-cells = <2>; - }; - - emif_clkctrl: clock@720 { - compatible = "ti,clkctrl"; - clock-output-names = "emif_clkctrl"; - reg = <0x720 0x4>; - #clock-cells = <2>; - }; - - dss_clkctrl: clock@a20 { - compatible = "ti,clkctrl"; - clock-output-names = "dss_clkctrl"; - reg = <0xa20 0x4>; - #clock-cells = <2>; - }; - - cpsw_125mhz_clkctrl: clock@b20 { - compatible = "ti,clkctrl"; - clock-output-names = "cpsw_125mhz_clkctrl"; - reg = <0xb20 0x4>; - #clock-cells = <2>; - }; - - }; -}; diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi deleted file mode 100644 index 46c5383f0eee..000000000000 --- a/arch/arm/boot/dts/am57-pruss.dtsi +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * Common PRUSS data for TI AM57xx platforms - */ - -&ocp { - pruss1_tm: target-module@4b226000 { - compatible = "ti,sysc-pruss", "ti,sysc"; - reg = <0x4b226000 0x4>, - <0x4b226004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | - SYSC_PRUSS_SUB_MWAIT)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4b200000 0x80000>; - - pruss1: pruss@0 { - compatible = "ti,am5728-pruss"; - reg = <0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pruss1_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x8000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - pruss1_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - pruss1_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ - <&dpll_gmac_h13x2_ck>; /* icss_clk */ - }; - }; - }; - - pruss1_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x58>; - }; - - pruss1_intc: interrupt-controller@20000 { - compatible = "ti,pruss-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru1_0: pru@34000 { - compatible = "ti,am5728-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x400>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am57xx-pru1_0-fw"; - }; - - pru1_1: pru@38000 { - compatible = "ti,am5728-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x400>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am57xx-pru1_1-fw"; - }; - - pruss1_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&dpll_gmac_h13x2_ck>; - clock-names = "fck"; - bus_freq = <1000000>; - reg = <0x32400 0x90>; - }; - }; - }; - - pruss2_tm: target-module@4b2a6000 { - compatible = "ti,sysc-pruss", "ti,sysc"; - reg = <0x4b2a6000 0x4>, - <0x4b2a6004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | - SYSC_PRUSS_SUB_MWAIT)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4b280000 0x80000>; - - pruss2: pruss@0 { - compatible = "ti,am5728-pruss"; - reg = <0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pruss2_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x8000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - pruss2_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - pruss2_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ - <&dpll_gmac_h13x2_ck>; /* icss_clk */ - }; - }; - }; - - pruss2_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x58>; - }; - - pruss2_intc: interrupt-controller@20000 { - compatible = "ti,pruss-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru2_0: pru@34000 { - compatible = "ti,am5728-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x400>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am57xx-pru2_0-fw"; - }; - - pru2_1: pru@38000 { - compatible = "ti,am5728-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x400>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am57xx-pru2_1-fw"; - }; - - pruss2_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&dpll_gmac_h13x2_ck>; - clock-names = "fck"; - bus_freq = <1000000>; - reg = <0x32400 0x90>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi deleted file mode 100644 index 6d7530a48c73..000000000000 --- a/arch/arm/boot/dts/am5718.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "dra72x.dtsi" -#include "am57-pruss.dtsi" - -/ { - compatible = "ti,am5718", "ti,dra7"; -}; - -/* - * These modules are not present on AM5718 - * - * ATL - * VCP1, VCP2 - * MLB - * ISS - * USB3 - */ - -&usb3_tm { - status = "disabled"; -}; - -&atl_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am571x-idk-touchscreen.dtso b/arch/arm/boot/dts/am571x-idk-touchscreen.dtso deleted file mode 100644 index c051ee6c1130..000000000000 --- a/arch/arm/boot/dts/am571x-idk-touchscreen.dtso +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; -/plugin/; - -#include -#include - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - - touchscreen: edt-ft5506@38 { - compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; - - reg = <0x38>; - - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - - /* GPIO line is inverted before going to touch panel */ - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <1920>; - touchscreen-size-y = <1200>; - - wakeup-source; - }; -}; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts deleted file mode 100644 index 48425020281a..000000000000 --- a/arch/arm/boot/dts/am571x-idk.dts +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am5718.dtsi" -#include -#include -#include "dra7-mmc-iodelay.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -#include "am57xx-idk-common.dtsi" -#include "dra7-ipu-dsp-common.dtsi" - -/ { - model = "TI AM5718 IDK"; - compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - usr1-led { - label = "status1:red:usr"; - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - usr2-led { - label = "status1:green:usr"; - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - idk-leds { - status = "disabled"; - compatible = "gpio-leds"; - red0-led { - label = "idk:red0"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green0-led { - label = "idk:green0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue0-led { - label = "idk:blue0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red1-led { - label = "idk:red1"; - gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green1-led { - label = "idk:green1"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue1-led { - label = "idk:blue1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red2-led { - label = "idk:red2"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green2-led { - label = "idk:green2"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue2-led { - label = "idk:blue2"; - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red3-led { - label = "idk:red3"; - gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green3-led { - label = "idk:green3"; - gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue3-led { - label = "idk:blue3"; - gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&extcon_usb2 { - id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; -}; - -&pruss1_mdio { - status = "disabled"; -}; - -&pruss2_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/am5728.dtsi deleted file mode 100644 index 5e0bdf16d485..000000000000 --- a/arch/arm/boot/dts/am5728.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "dra74x.dtsi" -#include "am57-pruss.dtsi" - -/ { - compatible = "ti,am5728", "ti,dra7"; -}; - -/* - * These modules are not present on AM5728 - * - * EVE1, EVE2 - * ATL - * VCP1, VCP2 - * MLB - * ISS - * USB3, USB4 - */ - -&usb3_tm { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; - -&atl_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/am5729-beagleboneai.dts deleted file mode 100644 index 149cfafb90bf..000000000000 --- a/arch/arm/boot/dts/am5729-beagleboneai.dts +++ /dev/null @@ -1,704 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/dts-v1/; - -#include "dra74x.dtsi" -#include "am57xx-commercial-grade.dtsi" -#include "dra74x-mmc-iodelay.dtsi" -#include "dra74-ipu-dsp-common.dtsi" -#include -#include -#include - -/ { - model = "BeagleBoard.org BeagleBone AI"; - compatible = "beagle,am5729-beagleboneai", "ti,am5728", - "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &tps659038_rtc; - rtc1 = &rtc; - display0 = &hdmi_conn; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - - dsp2_memory_region: dsp2-memory@9f000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9f000000 0x0 0x800000>; - reusable; - status = "okay"; - }; - - }; - - vdd_adc: gpioregulator-vdd_adc { - compatible = "regulator-gpio"; - regulator-name = "vdd_adc"; - vin-supply = <&vdd_5v>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; - states = <1800000 0 - 3300000 1>; - }; - - vdd_5v: fixedregulator-vdd_5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&vdd_ddr>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "beaglebone:green:usr0"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "beaglebone:green:usr1"; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "beaglebone:green:usr2"; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu"; - default-state = "off"; - }; - - led3 { - label = "beaglebone:green:usr3"; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "beaglebone:green:usr4"; - gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "netdev"; - default-state = "off"; - }; - }; - - hdmi_conn: connector@0 { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_encoder_out>; - }; - }; - }; - - hdmi_enc: encoder@0 { - /* "ti,tpd12s016" software compatible with "ti,tpd12s015" - * no need for individual driver - */ - compatible = "ti,tpd12s015"; - gpios = <0>, - <0>, - <&gpio7 12 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <0x1>; - #size-cells = <0x0>; - - port@0 { - reg = <0x0>; - - hdmi_encoder_in: endpoint@0 { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <0x1>; - - hdmi_encoder_out: endpoint@0 { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - emmc_pwrseq: emmc_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; - }; - - brcmf_pwrseq: brcmf_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ - <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - ti,enable-id-detection; - id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - ti,palmas-override-powerhold; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - smps12-in-supply = <&vdd_5v>; - smps3-in-supply = <&vdd_5v>; - smps45-in-supply = <&vdd_5v>; - smps6-in-supply = <&vdd_5v>; - smps7-in-supply = <&vdd_5v>; - mps3-in-supply = <&vdd_5v>; - smps8-in-supply = <&vdd_5v>; - smps9-in-supply = <&vdd_5v>; - ldo1-in-supply = <&vdd_5v>; - ldo2-in-supply = <&vdd_5v>; - ldo3-in-supply = <&vdd_5v>; - ldo4-in-supply = <&vdd_5v>; - ldo9-in-supply = <&vdd_5v>; - ldoln-in-supply = <&vdd_5v>; - ldousb-in-supply = <&vdd_5v>; - ldortc-in-supply = <&vdd_5v>; - - regulators { - vdd_mpu: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ddr: smps3 { - /* VDD_DDR EMIF1 EMIF2 */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_dspeve: smps45 { - /* VDD_DSPEVE on AM572 */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_gpu: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_core: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = < 850000>; /*** 1.15V */ - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_iva: smps8 { - /* VDD_IVAHD */ /*** 1.06V */ - regulator-name = "smps8"; - }; - - vdd_3v3: smps9 { - /* VDD_3V3 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_sd: ldo1 { - /* VDDSHV8 - VSDMMC */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_1v8: ldo2 { - /* VDDSH18V */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8_phy_ldo3: ldo3 { - /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8_phy_ldo4: ldo4 { - /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* LDO5-8 unused */ - - vdd_rtc: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = < 840000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8_pll: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldortc_reg: ldortc { - /* VDDA_RTC */ - regulator-name = "ldortc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - - regen2: regen2 { - /* Needed for PMIC internal resource */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio2>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - st,mod-12b = <1>; /* 12-bit ADC */ - st,ref-sel = <0>; /* internal ADC reference */ - st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ - st,sample-time = <4>; /* ADC converstion time: 80 clocks */ - - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */ - adc0: iio-device@0 { - #io-channel-cells = <1>; - iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>; - iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38", - "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35"; - }; - }; - - stmpe_touchscreen { - status = "disabled"; - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_gpio { - compatible = "st,stmpe-gpio"; - }; - - stmpe_pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; - }; - }; -}; - -&mcspi3 { - status = "okay"; - ti,pindir-d0-out-d1-in; - - sn65hvs882: sn65hvs882@0 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - }; -}; - -&cpu0 { - vdd-supply = <&vdd_mpu>; - voltage-tolerance = <1>; -}; - -&uart1 { - status = "okay"; -}; - -&davinci_mdio_sw { - reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - phy0: ethernet-phy@4 { - reg = <4>; - eee-broken-100tx; - eee-broken-1000t; - }; -}; - -&mac_sw { - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&ocp { - pruss1_shmem: pruss_shmem@4b200000 { - status = "okay"; - compatible = "ti,pruss-shmem"; - reg = <0x4b200000 0x020000>; - }; - - pruss2_shmem: pruss_shmem@4b280000 { - status = "okay"; - compatible = "ti,pruss-shmem"; - reg = <0x4b280000 0x020000>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&vdd_sd>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vdd_1v8>; - vqmmc-supply = <&vdd_1v8>; - bus-width = <8>; - ti,non-removable; - non-removable; - mmc-pwrseq = <&emmc_pwrseq>; - - ti,needs-special-reset; - dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; - dma-names = "tx", "rx"; - -}; - -&mmc4 { - /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ - /* HS: High speed up to 50 MHz (3.3 V signaling). */ - /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ - /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ - /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ - /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ - /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ - status = "okay"; - - ti,needs-special-reset; - vmmc-supply = <&vdd_3v3>; - cap-power-off-card; - keep-power-in-suspend; - bus-width = <4>; - ti,non-removable; - non-removable; - no-1-8-v; - max-frequency = <24000000>; - - #address-cells = <1>; - #size-cells = <0>; - mmc-pwrseq = <&brcmf_pwrseq>; - - brcmf: wifi@1 { - status = "okay"; - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - - brcm,sd-head-align = <4>; - brcm,sd_head_align = <4>; - brcm,sd_sgentry_align = <512>; - - interrupt-parent = <&gpio3>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - status = "okay"; - dr_mode = "otg"; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&usb2 { - status = "okay"; - dr_mode = "host"; -}; - -&dss { - status = "okay"; - vdda_video-supply = <&vdd_1v8_pll>; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&vdd_1v8_phy_ldo4>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_encoder_in>; - }; - }; -}; - -&bandgap { - status = "okay"; -}; - -&cpu_alert0 { - temperature = <55000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <85000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <85000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <85000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <85000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <85000>; /* milliCelsius */ -}; - -&sata { - status = "disabled"; -}; - -&sata_phy { - status = "disabled"; -}; - -/* bluetooth */ -&uart6 { - status = "okay"; -}; - -/* cape header stuff */ -&i2c4 { - status = "okay"; - clock-frequency = <100000>; -}; - -&cpu0_opp_table { - opp_slow-500000000 { - opp-shared; - }; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; - -&dsp2 { - status = "okay"; - memory-region = <&dsp2_memory_region>; -}; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi deleted file mode 100644 index 1d66278c3a72..000000000000 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include "am57xx-idk-common.dtsi" -#include "dra74-ipu-dsp-common.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - - dsp2_memory_region: dsp2-memory@9f000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9f000000 0x0 0x800000>; - reusable; - status = "okay"; - }; - }; - - status-leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - cpu1-led { - label = "status1:red:cpu1"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu1"; - }; - - usr1-led { - label = "status1:green:usr"; - gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - idk-leds { - status = "disabled"; - compatible = "gpio-leds"; - red0-led { - label = "idk:red0"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green0-led { - label = "idk:green0"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue0-led { - label = "idk:blue0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red1-led { - label = "idk:red1"; - gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green1-led { - label = "idk:green1"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue1-led { - label = "idk:blue1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red2-led { - label = "idk:red2"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green2-led { - label = "idk:green2"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue2-led { - label = "idk:blue2"; - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red3-led { - label = "idk:red3"; - gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green3-led { - label = "idk:green3"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue3-led { - label = "idk:blue3"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&extcon_usb2 { - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; - -&dsp2 { - status = "okay"; - memory-region = <&dsp2_memory_region>; -}; diff --git a/arch/arm/boot/dts/am572x-idk-touchscreen.dtso b/arch/arm/boot/dts/am572x-idk-touchscreen.dtso deleted file mode 100644 index 573e932b1239..000000000000 --- a/arch/arm/boot/dts/am572x-idk-touchscreen.dtso +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; -/plugin/; - -#include -#include - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - - touchscreen: edt-ft5506@38 { - compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; - - reg = <0x38>; - - interrupt-parent = <&gpio3>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - - /* GPIO line is inverted before going to touch panel */ - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <1920>; - touchscreen-size-y = <1200>; - - wakeup-source; - }; -}; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts deleted file mode 100644 index 94a738cb0a4d..000000000000 --- a/arch/arm/boot/dts/am572x-idk.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "am5728.dtsi" -#include "dra7-mmc-iodelay.dtsi" -#include "dra74x-mmc-iodelay.dtsi" -#include "am572x-idk-common.dtsi" - -/ { - model = "TI AM5728 IDK"; - compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7"; -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20>; -}; - -&pruss1_mdio { - status = "disabled"; -}; - -&pruss2_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi deleted file mode 100644 index a1f029e9d1f3..000000000000 --- a/arch/arm/boot/dts/am5748.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "dra74x-p.dtsi" -#include "am57-pruss.dtsi" - -/ { - compatible = "ti,am5748", "ti,dra762", "ti,dra7"; -}; - -/* - * These modules are not present on AM5748 - * - * EVE1, EVE2 - * ATL - * VCP1, VCP2 - * MLB - * ISS - * USB3, USB4 - */ - -&usb3_tm { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; - -&atl_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts deleted file mode 100644 index 47b9174d2353..000000000000 --- a/arch/arm/boot/dts/am574x-idk.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - - -/dts-v1/; - -#include "am5748.dtsi" -#include "dra7-mmc-iodelay.dtsi" -#include "dra76x-mmc-iodelay.dtsi" -#include "am572x-idk-common.dtsi" - -/ { - model = "TI AM5748 IDK"; - compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; -}; - -&qspi { - spi-max-frequency = <96000000>; - flash@0 { - spi-max-frequency = <96000000>; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_default>; - pinctrl-2 = <&mmc2_pins_default>; -}; - -&emif1 { - status = "okay"; -}; - -&pruss1_mdio { - status = "disabled"; -}; - -&pruss2_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi deleted file mode 100644 index 994e69ab38d7..000000000000 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am5728.dtsi" -#include "am57xx-commercial-grade.dtsi" -#include "dra74x-mmc-iodelay.dtsi" -#include "dra74-ipu-dsp-common.dtsi" -#include -#include - -/ { - compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &mcp_rtc; - rtc1 = &tps659038_rtc; - rtc2 = &rtc; - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - main_12v0: fixedregulator-main_12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "main_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - evm_5v0: fixedregulator-evm_5v0 { - /* Output of TPS54531D */ - compatible = "regulator-fixed"; - regulator-name = "evm_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - - dsp2_memory_region: dsp2-memory@9f000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9f000000 0x0 0x800000>; - reusable; - status = "okay"; - }; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <®en1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd_fixed"; - vin-supply = <&vdd_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&smps3_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "beagle-x15:usr0"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "beagle-x15:usr1"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led2 { - label = "beagle-x15:usr2"; - gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "beagle-x15:usr3"; - gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - default-state = "off"; - }; - }; - - gpio_fan: gpio_fan { - /* Based on 5v 500mA AFB02505HHB */ - compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, - <13000 1>; - #cooling-cells = <2>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "BeagleBoard-X15"; - simple-audio-card,widgets = - "Line", "Line Out", - "Line", "Line In"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC2L", "Line In", - "MIC2R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3104>; - clocks = <&clkout2_clk>; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - ti,palmas-override-powerhold; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_CORE */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS7 unused */ - - smps8_reg: smps8 { - /* VDD_1V8 */ - regulator-name = "smps8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS9 unused */ - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_SHV5 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - }; - - tmp102: tmp102@48 { - compatible = "ti,tmp102"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - tlv320aic3104: tlv320aic3104@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3104"; - reg = <0x18>; - assigned-clocks = <&clkoutmux2_clk_mux>; - assigned-clock-parents = <&sys_clk2_dclk_div>; - - status = "okay"; - adc-settle-ms = <40>; - - AVDD-supply = <&vdd_3v3>; - IOVDD-supply = <&vdd_3v3>; - DRVDD-supply = <&vdd_3v3>; - DVDD-supply = <&aic_dvdd>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - - mcp_rtc: rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, - <&dra7_pmx_core 0x424>; - interrupt-names = "irq", "wakeup"; - - vcc-supply = <&vdd_3v3>; - wakeup-source; - }; -}; - -&gpio7_target { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&cpu0 { - vdd-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; -}; - -&davinci_mdio_sw { - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&mac_sw { - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <&phy1>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <2>; -}; - -&mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ - no-1-8-v; -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&vdd_3v3>; - bus-width = <8>; - non-removable; - no-1-8-v; -}; - -&sata { - status = "okay"; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - /* - * Stand alone usage is peripheral only. - * However, with some resistor modifications - * this port can be used via expansion connectors - * as "host" or "dual-role". If so, provide - * the necessary dr_mode override in the expansion - * board's DT. - */ - dr_mode = "peripheral"; -}; - -&cpu_trips { - cpu_alert1: cpu_alert1 { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; -}; - -&cpu_cooling_maps { - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&thermal_zones { - board_thermal: board_thermal { - polling-delay-passive = <1250>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tmp102 0>; - - board_trips: trips { - board_alert0: board_alert { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - board_crit: board_crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - board_cooling_maps: cooling-maps { - map0 { - trip = <&board_alert0>; - cooling-device = - <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&dss { - status = "okay"; - - vdda_video-supply = <&ldoln_reg>; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&ldo4_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin2>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; - -&dsp2 { - status = "okay"; - memory-region = <&dsp2_memory_region>; -}; - -&pruss1_mdio { - status = "disabled"; -}; - -&pruss2_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts deleted file mode 100644 index 83e174e053c7..000000000000 --- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - model = "TI AM5728 BeagleBoard-X15 rev B1"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; -}; - -/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ -&phy1 { - max-speed = <100>; -}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts deleted file mode 100644 index 656dd84460d2..000000000000 --- a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - model = "TI AM5728 BeagleBoard-X15 rev C"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20>; -}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts deleted file mode 100644 index 0a8b16505ed9..000000000000 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - /* NOTE: This describes the "original" pre-production A2 revision */ - model = "TI AM5728 BeagleBoard-X15"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - - vmmc-supply = <&ldo1_reg>; - no-1-8-v; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; -}; - -/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ -&phy1 { - max-speed = <100>; -}; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts deleted file mode 100644 index 4774aa05f101..000000000000 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ /dev/null @@ -1,628 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Support for CompuLab CL-SOM-AM57x System-on-Module - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Dmitry Lifshitz - */ - -/dts-v1/; - -#include -#include -#include "am5728.dtsi" - -/ { - model = "CompuLab CL-SOM-AM57x"; - compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; - - led0 { - label = "cl-som-am57x:green"; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ads7846reg: fixedregulator-ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "CL-SOM-AM57x-Sound-Card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Line", "Line Jack"; - simple-audio-card,routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line Jack", - "MICIN", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8731>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&dra7_pmx_core { - leds_pins_default: leds-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ - >; - }; - - i2c1_pins_default: i2c1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ - >; - }; - - i2c3_pins_default: i2c3-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ - >; - }; - - i2c4_pins_default: i2c4-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ - DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ - >; - }; - - tps659038_pins_default: tps659038-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ - >; - }; - - mmc2_pins_default: mmc2-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - qspi1_pins: qspi1-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ - DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */ - DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ - >; - }; - - cpsw_pins_default: cpsw-default-pins { - pinctrl-single,pins = < - /* Slave at addr 0x0 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */ - - /* Slave at addr 0x1 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - }; - - cpsw_pins_sleep: cpsw-sleep-pins { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) - >; - }; - - davinci_mdio_pins_default: davinci-mdio-default-pins { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ - DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */ - >; - }; - - davinci_mdio_pins_sleep: davinci-mdio-sleep-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) - >; - }; - - ads7846_pins: ads7846-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ - >; - }; - - mcasp3_pins_default: mcasp3-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ - >; - }; - - mcasp3_pins_sleep: mcasp3-sleep-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_default>; - clock-frequency = <400000>; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_default>; - clock-frequency = <400000>; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_default>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps659038_pins_default>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVA */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* PMIC_3V3 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_1V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* regen1 not used */ - }; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - rtc0: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - - eeprom_module: atmel@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; - - wm8731: wm8731@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8731"; - reg = <0x1a>; - status = "okay"; - }; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&sata { - status = "okay"; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { - status = "okay"; - }; -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <48000000>; - - spi_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80", "jedec,spi-nor"; - reg = <0>; /* CS0 */ - spi-max-frequency = <48000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "uboot environment"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x0>; - }; - }; - - /* touch controller */ - touchscreen@1 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <1>; /* CS1 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <31 0>; - pendown-gpio = <&gpio1 31 0>; - - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&mac_sw { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_pins_default>; - pinctrl-1 = <&cpsw_pins_sleep>; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-txid"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_pins_default>; - pinctrl-1 = <&davinci_mdio_pins_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&usb2 { - dr_mode = "host"; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins_default>; - pinctrl-1 = <&mcasp3_pins_sleep>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; -}; - -&gpio3_target { - ti,no-reset-on-init; -}; - -&gpio2_target { - status = "okay"; - ti,no-reset-on-init; -}; - -&pruss1_mdio { - status = "disabled"; -}; - -&pruss2_mdio { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi b/arch/arm/boot/dts/am57xx-commercial-grade.dtsi deleted file mode 100644 index 3eed6e09c884..000000000000 --- a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&cpu_alert0 { - temperature = <80000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <90000>; /* milliCelsius */ -}; diff --git a/arch/arm/boot/dts/am57xx-evm.dtso b/arch/arm/boot/dts/am57xx-evm.dtso deleted file mode 100644 index 12385a31061e..000000000000 --- a/arch/arm/boot/dts/am57xx-evm.dtso +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DT overlay for AM57xx GP EVM boards - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&{/} { - compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - model = "TI AM5728 EVM"; - - aliases { - display0 = "/display"; - display1 = "/connector"; // Fixme: &lcd0 and &hdmi0 could be - // resolved here correcly based on - // information in the base dtb symbol - // table with a fix in dtc - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-user1 { - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - label = "USER1"; - linux,code = ; - }; - - button-user2 { - gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - label = "USER2"; - linux,code = ; - }; - - button-user3 { - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - label = "USER3"; - linux,code = ; - }; - - button-user4 { - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - label = "USER4"; - linux,code = ; - }; - - button-user5 { - gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - label = "USER5"; - linux,code = ; - }; - }; - - lcd0: display { - compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; - backlight = <&lcd_bl>; - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - label = "lcd"; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 243 245 247 249 251 252 253 255>; - default-brightness-level = <8>; - pwms = <&ehrpwm1 0 50000 0>; - }; -}; - -&ehrpwm1 { - status = "okay"; -}; - -&epwmss1 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - #address-cells = <1>; - #size-cells = <0>; - - touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - attb-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - reg = <0x5c>; - reset-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - }; -}; - -&uart8 { - status = "okay"; -}; - -&dss { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpi_out: endpoint { - data-lines = <24>; - remote-endpoint = <&lcd_in>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi deleted file mode 100644 index 43e3623f079c..000000000000 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ /dev/null @@ -1,608 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "am57xx-industrial-grade.dtsi" - -/ { - aliases { - rtc0 = &tps659038_rtc; - rtc1 = &rtc; - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "VMAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - v3_3d: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "V3_3D"; - vin-supply = <&smps9_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - v1_2d: fixedregulator-v1_2d { - compatible = "regulator-fixed"; - regulator-name = "V1_2D"; - vin-supply = <&vmain>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&v3_3d>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - leds-iio { - status = "disabled"; - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - hdmi0: connector@0 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder@0 { - compatible = "ti,tpd12s016", "ti,tpd12s015"; - - gpios = <0>, /* optional CT_CP_HPD */ - <0>, /* optional LS_OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint@0 { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint@0 { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - src_clk_x1: src_clk_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; -}; - -&dra7_pmx_core { - dcan1_pins_default: dcan1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1-sleep-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ - >; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH - &dra7_pmx_core 0x418>; - #interrupt-cells = <2>; - interrupt-controller; - ti,system-power-controller; - ti,palmas-override-powerhold; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - smps12-in-supply = <&vmain>; - smps3-in-supply = <&vmain>; - smps45-in-supply = <&vmain>; - smps6-in-supply = <&vmain>; - smps7-in-supply = <&vmain>; - smps8-in-supply = <&vmain>; - smps9-in-supply = <&vmain>; - ldo1-in-supply = <&vmain>; - ldo2-in-supply = <&vmain>; - ldo3-in-supply = <&vmain>; - ldo4-in-supply = <&vmain>; - ldo9-in-supply = <&vmain>; - ldoln-in-supply = <&vmain>; - ldousb-in-supply = <&vmain>; - ldortc-in-supply = <&vmain>; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR EMIF1 EMIF2 */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE on AM572 */ - /* VDD_IVA + VDD_DSP on AM571 */ - regulator-name = "smps45"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* 5728 - VDD_IVAHD */ - /* 5718 - N.C. test point */ - regulator-name = "smps8"; - }; - - smps9_reg: smps9 { - /* VDD_3_3D */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* VDDSHV8 - VSDMMC */ - /* NOTE: on rev 1.3a, data supply */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDDSH18V */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* LDO5-8 unused */ - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <840000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldortc_reg: ldortc { - /* VDDA_RTC */ - regulator-name = "ldortc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - - regen2: regen2 { - /* Needed for PMIC internal resource */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - /* ID & VBUS GPIOs provided in board dts */ - }; - }; - - tpic2810: tpic2810@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; - - dsi_bridge: tc358778@e { - compatible = "toshiba,tc358778", "toshiba,tc358768"; - reg = <0xe>; - status = "disabled"; - - clocks = <&src_clk_x1>; - clock-names = "refclk"; - - vddc-supply = <&v1_2d>; - vddmipi-supply = <&v1_2d>; - vddio-supply = <&v3_3d>; - - dsi_bridge_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - rgb_in: endpoint { - remote-endpoint = <&dpi_out>; - data-lines = <24>; - }; - }; - }; - }; -}; - -&mcspi3 { - status = "okay"; - ti,pindir-d0-out-d1-in; - - sn65hvs882: sn65hvs882@0 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - }; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH - &dra7_pmx_core 0x248>; -}; - -&rtc { - status = "okay"; - ext-clk-src; -}; - -&mac_sw { - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - extcon = <&extcon_usb2>; - dr_mode = "otg"; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&v3_3d>; - vqmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ - no-1-8-v; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&v3_3d>; - vqmmc-supply = <&v3_3d>; - bus-width = <8>; - non-removable; - max-frequency = <96000000>; - no-1-8-v; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - flash@0 { - compatible = "s25fl256s1", "jedec,spi-nor"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@2 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@3 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@5 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@6 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&cpu0 { - vdd-supply = <&smps12_reg>; -}; - -&hdmi { - status = "okay"; - - vdda-supply = <&ldo4_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&dss { - status = "okay"; - - vdda_video-supply = <&ldoln_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpi_out: endpoint { - remote-endpoint = <&rgb_in>; - data-lines = <24>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso deleted file mode 100644 index 25d74e9f3c9e..000000000000 --- a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; -/plugin/; - -&{/} { - aliases { - display0 = "/display"; - display1 = "/connector"; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 1>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; -}; - -&dsi_bridge { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - lcd: display { - compatible = "osddisplays,osd101t2045-53ts"; - reg = <0>; - - label = "lcd"; - - backlight = <&lcd_bl>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_bridge_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&lcd_in>; - }; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso deleted file mode 100644 index 8cea7ba32487..000000000000 --- a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; -/plugin/; - -#include -#include - -&{/} { - aliases { - display0 = "/display"; - display1 = "/connector"; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 1>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; -}; - -&dsi_bridge { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - lcd: display { - compatible = "osddisplays,osd101t2587-53ts"; - reg = <0>; - - label = "lcd"; - - backlight = <&lcd_bl>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_bridge_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&lcd_in>; - }; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi b/arch/arm/boot/dts/am57xx-industrial-grade.dtsi deleted file mode 100644 index 422f953fc8d8..000000000000 --- a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&cpu_alert0 { - temperature = <90000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <105000>; /* milliCelsius */ -}; diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts deleted file mode 100644 index 363115afb0a4..000000000000 --- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Support for CompuLab SBC-AM57x single board computer - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Dmitry Lifshitz - */ - -#include "am57xx-cl-som-am57x.dts" -#include "compulab-sb-som.dtsi" - -/ { - model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x"; - compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - display0 = &lcd0; - display1 = &hdmi; - }; -}; - -&dra7_pmx_core { - uart3_pins_default: uart3-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ - >; - }; - - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */ - DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */ - >; - }; - - usb1_pins: usb1-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - i2c5_pins_default: i2c5-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - lcd_pins_default: lcd-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ - >; - }; - - hdmi_pins: hdmi-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - hdmi_conn_pins: hdmi-conn-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ - >; - }; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; -}; - -&mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_default>; - clock-frequency = <400000>; - - eeprom_base: atmel@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - pagesize = <16>; - }; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&dss { - status = "okay"; - - vdda_video-supply = <&ldoln_reg>; - - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&lcd0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_default>; - - enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH - &gpio4 0 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - data-lines = <24>; - }; - }; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; - -&hdmi_conn { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_conn_pins>; - - hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; -}; diff --git a/arch/arm/boot/dts/amazon/Makefile b/arch/arm/boot/dts/amazon/Makefile new file mode 100644 index 000000000000..58af5c4846ef --- /dev/null +++ b/arch/arm/boot/dts/amazon/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb diff --git a/arch/arm/boot/dts/amazon/alpine-db.dts b/arch/arm/boot/dts/amazon/alpine-db.dts new file mode 100644 index 000000000000..dfb5a0802273 --- /dev/null +++ b/arch/arm/boot/dts/amazon/alpine-db.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Alternatively, redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "alpine.dtsi" + +/ { + model = "Annapurna Labs Alpine Dev Board"; + /* no need for anything outside SOC */ +}; + diff --git a/arch/arm/boot/dts/amazon/alpine.dtsi b/arch/arm/boot/dts/amazon/alpine.dtsi new file mode 100644 index 000000000000..ff68dfb4eb78 --- /dev/null +++ b/arch/arm/boot/dts/amazon/alpine.dtsi @@ -0,0 +1,176 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Alternatively, redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + /* SOC compatibility */ + compatible = "al,alpine"; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + /* CPU Configuration */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <1700000000>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <1700000000>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + clock-frequency = <1700000000>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + clock-frequency = <1700000000>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + arch-timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = + , + , + , + ; + clock-frequency = <50000000>; + }; + + /* Interrupt Controller */ + gic: interrupt-controller@fb001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xfb002000 0x0 0x2000>, + <0x0 0xfb004000 0x0 0x2000>, + <0x0 0xfb006000 0x0 0x2000>; + interrupts = + ; + }; + + /* CPU Resume registers */ + cpu-resume@fbff5ec0 { + compatible = "al,alpine-cpu-resume"; + reg = <0x0 0xfbff5ec0 0x0 0x30>; + }; + + /* North Bridge Service Registers */ + sysfabric-service@fb070000 { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0x0 0xfb070000 0x0 0x10000>; + }; + + /* Performance Monitor Unit */ + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + }; + + uart0: serial@fd883000 { + compatible = "ns16550a"; + reg = <0x0 0xfd883000 0x0 0x1000>; + clock-frequency = <375000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: serial@fd884000 { + compatible = "ns16550a"; + reg = <0x0 0xfd884000 0x0 0x1000>; + clock-frequency = <375000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + /* Internal PCIe Controller */ + pcie@fbc00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + reg = <0x0 0xfbc00000 0x0 0x100000>; + interrupt-map-mask = <0xf800 0 0 7>; + /* Add legacy interrupts for SATA devices only */ + interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, + <0x4800 0 0 1 &gic 0 44 4>; + + /* 32 bit non prefetchable memory space */ + ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; + + bus-range = <0x00 0x00>; + msi-parent = <&msix>; + }; + + msix: msix@fbe00000 { + compatible = "al,alpine-msix"; + reg = <0x0 0xfbe00000 0x0 0x100000>; + interrupt-controller; + msi-controller; + al,msi-base-spi = <96>; + al,msi-num-spis = <64>; + }; + }; +}; diff --git a/arch/arm/boot/dts/amlogic/Makefile b/arch/arm/boot/dts/amlogic/Makefile new file mode 100644 index 000000000000..a84310780ea3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_MESON6) += \ + meson6-atv1200.dtb +dtb-$(CONFIG_MACH_MESON8) += \ + meson8-minix-neo-x8.dtb \ + meson8b-ec100.dtb \ + meson8b-mxq.dtb \ + meson8b-odroidc1.dtb \ + meson8m2-mxiii-plus.dtb diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi new file mode 100644 index 000000000000..8e3860d5d916 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2014 Carlo Caione + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0xc1100000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc1100000 0x200000>; + + hhi: system-controller@4000 { + compatible = "amlogic,meson-hhi-sysctrl", + "simple-mfd", + "syscon"; + reg = <0x4000 0x400>; + }; + + aiu: audio-controller@5400 { + compatible = "amlogic,aiu"; + #sound-dai-cells = <2>; + sound-name-prefix = "AIU"; + reg = <0x5400 0x2ac>; + interrupts = , + ; + interrupt-names = "i2s", "spdif"; + status = "disabled"; + }; + + assist: assist@7c00 { + compatible = "amlogic,meson-mx-assist", "syscon"; + reg = <0x7c00 0x200>; + }; + + hwrng: rng@8100 { + compatible = "amlogic,meson-rng"; + reg = <0x8100 0x8>; + }; + + uart_A: serial@84c0 { + compatible = "amlogic,meson6-uart"; + reg = <0x84c0 0x18>; + interrupts = ; + fifo-size = <128>; + status = "disabled"; + }; + + uart_B: serial@84dc { + compatible = "amlogic,meson6-uart"; + reg = <0x84dc 0x18>; + interrupts = ; + status = "disabled"; + }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson6-i2c"; + reg = <0x8500 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm_ab: pwm@8550 { + compatible = "amlogic,meson-pwm"; + reg = <0x8550 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson-pwm"; + reg = <0x8650 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + saradc: adc@8680 { + compatible = "amlogic,meson-saradc"; + reg = <0x8680 0x34>; + #io-channel-cells = <1>; + interrupts = ; + status = "disabled"; + }; + + uart_C: serial@8700 { + compatible = "amlogic,meson6-uart"; + reg = <0x8700 0x18>; + interrupts = ; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson6-i2c"; + reg = <0x87c0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb0_phy: phy@8800 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8800 0x20>; + status = "disabled"; + }; + + usb1_phy: phy@8820 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8820 0x20>; + status = "disabled"; + }; + + sdio: mmc@8c20 { + compatible = "amlogic,meson-mx-sdio"; + reg = <0x8c20 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@8c80 { + compatible = "amlogic,meson6-spifc"; + reg = <0x8c80 0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhc: mmc@8e00 { + compatible = "amlogic,meson-mx-sdhc"; + reg = <0x8e00 0x42>; + interrupts = ; + status = "disabled"; + }; + + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0x9880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + + wdt: watchdog@9900 { + compatible = "amlogic,meson6-wdt"; + reg = <0x9900 0x8>; + interrupts = ; + }; + + timer_abcde: timer@9940 { + compatible = "amlogic,meson6-timer"; + reg = <0x9940 0x18>; + interrupts = , + , + , + ; + }; + }; + + L2: cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + periph: bus@c4300000 { + compatible = "simple-bus"; + reg = <0xc4300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc4300000 0x10000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1000 0x1000>, + <0x100 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + ao_arc_rproc: remoteproc@1c { + compatible = "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + status = "disabled"; + }; + + ir_receiver: ir-receiver@480 { + compatible = "amlogic,meson6-ir"; + reg = <0x480 0x20>; + interrupts = ; + status = "disabled"; + }; + + uart_AO: serial@4c0 { + compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart"; + reg = <0x4c0 0x18>; + interrupts = ; + status = "disabled"; + }; + + i2c_AO: i2c@500 { + compatible = "amlogic,meson6-i2c"; + reg = <0x500 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc: rtc@740 { + compatible = "amlogic,meson6-rtc"; + reg = <0x740 0x14>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + }; + + usb0: usb@c9040000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc9040000 0x40000>; + interrupts = ; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <500>; + g-tx-fifo-size = <256 192 128 128 128>; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb@c90c0000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90c0000 0x40000>; + interrupts = ; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + ethmac: ethernet@c9410000 { + compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + reg = <0xc9410000 0x10000 + 0xc1108108 0x4>; + interrupts = ; + interrupt-names = "macirq"; + status = "disabled"; + }; + + ahb_sram: sram@d9000000 { + compatible = "mmio-sram"; + reg = <0xd9000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd9000000 0x20000>; + }; + + bootrom: bootrom@d9040000 { + compatible = "amlogic,meson-mx-bootrom", "syscon"; + reg = <0xd9040000 0x10000>; + }; + + secbus: secbus@da000000 { + compatible = "simple-bus"; + reg = <0xda000000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xda000000 0x6000>; + + efuse: nvmem@0 { + compatible = "amlogic,meson6-efuse"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + }; + + thermal_sensor: thermal-sensor { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&saradc 8>; + io-channel-names = "sensor-channel"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; +}; /* end of / */ diff --git a/arch/arm/boot/dts/amlogic/meson6-atv1200.dts b/arch/arm/boot/dts/amlogic/meson6-atv1200.dts new file mode 100644 index 000000000000..98e1c94c0261 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson6-atv1200.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2014 Carlo Caione + */ + +/dts-v1/; +#include "meson6.dtsi" + +/ { + model = "Geniatech ATV1200"; + compatible = "geniatech,atv1200", "amlogic,meson6"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson6.dtsi b/arch/arm/boot/dts/amlogic/meson6.dtsi new file mode 100644 index 000000000000..4716030a48d0 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson6.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2014 Carlo Caione + */ + +#include "meson.dtsi" + +/ { + model = "Amlogic Meson6 SoC"; + compatible = "amlogic,meson6"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x201>; + }; + }; + + apb2: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x40000>; + }; + + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; +}; /* end of / */ + +&efuse { + status = "disabled"; +}; + +&timer_abcde { + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "pclk"; +}; + +&uart_AO { + clocks = <&xtal>, <&clk81>, <&clk81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_A { + clocks = <&xtal>, <&clk81>, <&clk81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + clocks = <&xtal>, <&clk81>, <&clk81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_C { + clocks = <&xtal>, <&clk81>, <&clk81>; + clock-names = "xtal", "pclk", "baud"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts new file mode 100644 index 000000000000..c6d1c5a8a3bf --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2014 Beniamino Galvani + */ + +/dts-v1/; +#include +#include "meson8.dtsi" + +/ { + model = "MINIX NEO-X8"; + compatible = "minix,neo-x8", "amlogic,meson8"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + label = "x8:blue:power"; + gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_pins>; + pinctrl-names = "default"; + + pmic@32 { + compatible = "ricoh,rn5t618"; + reg = <0x32>; + system-power-controller; + + regulators { + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&spi_nor_pins>; + pinctrl-names = "default"; + + flash@0 { + compatible = "mxicy,mx25l1606e"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <30000000>; + + partition@0 { + label = "boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x10000>; + }; + }; +}; + +&ir_receiver { + status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pnictrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi new file mode 100644 index 000000000000..59932fbfd5d5 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -0,0 +1,806 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2014 Carlo Caione + */ + +#include +#include +#include +#include +#include +#include +#include +#include "meson.dtsi" + +/ { + model = "Amlogic Meson8 SoC"; + compatible = "amlogic,meson8"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x200>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x201>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu2: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x202>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu3: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x203>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-96000000 { + opp-hz = /bits/ 64 <96000000>; + opp-microvolt = <825000>; + }; + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <825000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <825000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <825000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000>; + }; + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <850000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <875000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <975000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp-1800000000 { + status = "disabled"; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1125000>; + }; + opp-1992000000 { + status = "disabled"; + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000>; + }; + }; + + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-182142857 { + opp-hz = /bits/ 64 <182142857>; + opp-microvolt = <1150000>; + }; + opp-318750000 { + opp-hz = /bits/ 64 <318750000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom@0 { + reg = <0x0 0x200000>; + no-map; + }; + + /* + * 1 MiB reserved for the "ARM Power Firmware": this is ARM + * code which is responsible for system suspend. It loads a + * piece of ARC code ("arc_power" in the vendor u-boot tree) + * into SRAM, executes that and shuts down the (last) ARM core. + * The arc_power firmware then checks various wakeup sources + * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or + * simply the power key) and re-starts the ARM core once it + * detects a wakeup request. + */ + power-firmware@4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; + }; + + thermal-zones { + soc { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermal_sensor>; + + cooling-maps { + map0 { + trip = <&soc_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&soc_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + soc_passive: soc-passive { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + soc_hot: soc-hot { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + soc_critical: soc-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + }; + }; + + mmcbus: bus@c8000000 { + compatible = "simple-bus"; + reg = <0xc8000000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000000 0x8000>; + + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + + dmcbus: bus@6000 { + compatible = "simple-bus"; + reg = <0x6000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x400>; + + canvas: video-lut@20 { + compatible = "amlogic,meson8-canvas", + "amlogic,canvas"; + reg = <0x20 0x14>; + }; + }; + }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2", "pp4", "ppmmu4", + "pp5", "ppmmu5", "pp6", "ppmmu6"; + resets = <&reset RESET_MALI>; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_MALI>; + assigned-clock-rates = <318750000>; + + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; +}; /* end of / */ + +&aiu { + compatible = "amlogic,aiu-meson8", "amlogic,aiu"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; +}; + +&aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8-pmu", "syscon"; + reg = <0xe0 0x18>; + }; + + pinctrl_aobus: pinctrl@84 { + compatible = "amlogic,meson8-aobus-pinctrl"; + reg = <0x84 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: ao-bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; + }; + + i2s_am_clk_pins: i2s-am-clk-out { + mux { + groups = "i2s_am_clk_out_ao"; + function = "i2s_ao"; + bias-disable; + }; + }; + + i2s_out_ao_clk_pins: i2s-ao-clk-out { + mux { + groups = "i2s_ao_clk_out_ao"; + function = "i2s_ao"; + bias-disable; + }; + }; + + i2s_out_lr_clk_pins: i2s-lr-clk-out { + mux { + groups = "i2s_lr_clk_out_ao"; + function = "i2s_ao"; + bias-disable; + }; + }; + + i2s_out_ch01_ao_pins: i2s-out-ch01 { + mux { + groups = "i2s_out_ch01_ao"; + function = "i2s_ao"; + bias-disable; + }; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + bias-disable; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + bias-disable; + }; + }; + + ir_recv_pins: remote { + mux { + groups = "remote_input"; + function = "remote"; + bias-disable; + }; + }; + + pwm_f_ao_pins: pwm-f-ao { + mux { + groups = "pwm_f_ao"; + function = "pwm_f_ao"; + bias-disable; + }; + }; + }; +}; + +&ao_arc_rproc { + compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + amlogic,secbus2 = <&secbus2>; + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; +}; + +&cbus { + reset: reset-controller@4404 { + compatible = "amlogic,meson8b-reset"; + reg = <0x4404 0x9c>; + #reset-cells = <1>; + }; + + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + reg = <0x86c0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + clock-measure@8758 { + compatible = "amlogic,meson8-clk-measure"; + reg = <0x8758 0x1c>; + }; + + pinctrl_cbus: pinctrl@9880 { + compatible = "amlogic,meson8-cbus-pinctrl"; + reg = <0x9880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x30>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 120>; + }; + + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", + "sd_d3_a", "sd_clk_a", "sd_cmd_a"; + function = "sd_a"; + bias-disable; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + bias-disable; + }; + }; + + sd_c_pins: sd-c { + mux { + groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", + "sd_d3_c", "sd_clk_c", "sd_cmd_c"; + function = "sd_c"; + bias-disable; + }; + }; + + sdxc_a_pins: sdxc-a { + mux { + groups = "sdxc_d0_a", "sdxc_d13_a", + "sdxc_clk_a", "sdxc_cmd_a"; + function = "sdxc_a"; + bias-pull-up; + }; + }; + + sdxc_b_pins: sdxc-b { + mux { + groups = "sdxc_d0_b", "sdxc_d13_b", + "sdxc_clk_b", "sdxc_cmd_b"; + function = "sdxc_b"; + bias-pull-up; + }; + }; + + spdif_out_pins: spdif-out { + mux { + groups = "spdif_out"; + function = "spdif"; + bias-disable; + }; + }; + + spi_nor_pins: nor { + mux { + groups = "nor_d", "nor_q", "nor_c", "nor_cs"; + function = "nor"; + bias-disable; + }; + }; + + eth_pins: ethernet { + mux { + groups = "eth_tx_clk_50m", "eth_tx_en", + "eth_txd1", "eth_txd0", + "eth_rx_clk_in", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio", + "eth_mdc"; + function = "ethernet"; + bias-disable; + }; + }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + bias-disable; + }; + }; + + uart_a1_pins: uart-a1 { + mux { + groups = "uart_tx_a1", + "uart_rx_a1"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_a1_cts_rts_pins: uart-a1-cts-rts { + mux { + groups = "uart_cts_a1", + "uart_rts_a1"; + function = "uart_a"; + bias-disable; + }; + }; + + xtal_32k_out_pins: xtal-32k-out { + mux { + groups = "xtal_32k_out"; + function = "xtal"; + bias-disable; + }; + }; + }; +}; + +&ahb_sram { + ao_arc_sram: ao-arc-sram@0 { + compatible = "amlogic,meson8-ao-arc-sram"; + reg = <0x0 0x8000>; + pool; + }; + + smp-sram@1ff80 { + compatible = "amlogic,meson8-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + +&efuse { + compatible = "amlogic,meson8-efuse"; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; +}; + +ðmac { + clocks = <&clkc CLKID_ETH>; + clock-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; +}; + +&gpio_intc { + compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; + status = "okay"; +}; + +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pwrc: power-controller { + compatible = "amlogic,meson8-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364285714>; + }; +}; + +&hwrng { + compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + +&i2c_AO { + clocks = <&clkc CLKID_CLK81>; +}; + +&i2c_A { + clocks = <&clkc CLKID_CLK81>; +}; + +&i2c_B { + clocks = <&clkc CLKID_CLK81>; +}; + +&L2 { + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,prefetch-offset = <7>; + arm,double-linefill = <1>; + arm,prefetch-drop = <1>; + arm,shared-override; +}; + +&periph { + scu@0 { + compatible = "arm,cortex-a9-scu"; + reg = <0x0 0x100>; + }; + + timer@200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x200 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + + /* + * the arm_global_timer driver currently does not handle clock + * rate changes. Keep it disabled for now. + */ + status = "disabled"; + }; + + timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + }; +}; + +&pwm_ab { + compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; +}; + +&pwm_cd { + compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; +}; + +&rtc { + compatible = "amlogic,meson8-rtc"; + resets = <&reset RESET_RTC>; +}; + +&saradc { + compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; + clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; +}; + +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + +&secbus { + secbus2: system-controller@4000 { + compatible = "amlogic,meson8-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; +}; + +&sdio { + compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; +}; + +&spifc { + clocks = <&clkc CLKID_CLK81>; +}; + +&timer_abcde { + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk"; +}; + +&uart_AO { + compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_A { + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_C { + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&usb0 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&usb1_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts new file mode 100644 index 000000000000..3da47349eaaf --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Martin Blumenstingl . + */ + +/dts-v1/; + +#include +#include + +#include "meson8b.dtsi" + +/ { + model = "Endless Computers Endless Mini"; + compatible = "endless,ec100", "amlogic,meson8b"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + pal-switch { + label = "pal"; + linux,input-type = ; + linux,code = ; + gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; + }; + + ntsc-switch { + label = "ntsc"; + linux,input-type = ; + linux,code = ; + gpios = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>; + }; + + power-button { + label = "power"; + linux,code = ; + gpios = <&gpio GPIOH_9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + /* + * shutdown is managed by the EC (embedded micro-controller) + * which is configured through GPIOAO_2 (poweroff GPIO) and + * GPIOAO_7 (power LED, which has to go LOW as well). + */ + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + timeout-ms = <20000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "ec100:red:power"; + /* + * Needs to go LOW (together with the poweroff GPIO) + * during shutdown to allow the EC (embedded + * micro-controller) to shutdown the system. Setting + * the output to LOW signals the EC to start a + * "breathing"/pulsing effect until the power is fully + * turned off. + */ + gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + rtc32k_xtal: rtc32k-xtal-clk { + /* X2 in the schematics */ + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "RTC32K"; + #clock-cells = <0>; + }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "M8B-EC100"; + + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-rates = <270950400>, + <294912000>, + <393216000>; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&rt5640>; + }; + }; + }; + + usb_vbus: regulator-usb-vbus { + /* + * Silergy SY6288CCAC-GP 2A Power Distribution Switch. + */ + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vcc_5v>; + + /* + * signal name from the schematics: USB_PWR_EN + */ + gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v: regulator-vcc5v { + /* + * supplied by the main power input which called PWR_5V_STB + * in the schematics + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC5V"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + /* + * signal name from the schematics: 3V3_5V_EN + */ + gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; + + regulator-boot-on; + regulator-always-on; + }; + + vcck: regulator-vcck { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VCCK"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&vcc_5v>; + + pwms = <&pwm_cd 0 1148 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc1v8 { + /* + * ABLIC S-1339D18-M5001-GP + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-vcc3v3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * VDDIO_AO3.3V in the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v>; + }; + + vcc_ddr3: regulator-vcc-ddr3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * DDR3_1.5V in the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_DDR3_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&vcc_5v>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_rtc: regulator-vcc-rtc { + /* + * Global Mixed-mode Technology Inc. G918T12U-GP + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_RTC"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + /* + * When the board is powered then the input is VCC3V3, + * otherwise power is taken from the coin cell battery. + */ + vin-supply = <&vcc_3v3>; + }; + + vddee: regulator-vddee { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called VDDAO + * in a part of the schematics. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDEE"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&vcc_5v>; + + pwms = <&pwm_cd 1 1148 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&aiu { + status = "okay"; + + pinctrl-0 = <&i2s_am_clk_pins>, <&i2s_out_ao_clk_pins>, + <&i2s_out_lr_clk_pins>, <&i2s_out_ch01_ao_pins>; + pinctrl-names = "default"; +}; + +&cpu0 { + cpu-supply = <&vcck>; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* IC Plus IP101A/G (0x02430c54) */ + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; + + rt5640: codec@1c { + compatible = "realtek,rt5640"; + + reg = <0x1c>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&gpio_intc>; + interrupts = <13 IRQ_TYPE_EDGE_BOTH>; /* GPIOAO_13 */ + + /* + * TODO: realtek,ldo1-en-gpios is connected to GPIO_BSD_EN. + * We currently cannot configure this pin correctly. + * Luckily for us it's in the "right" state by default. + */ + realtek,in1-differential; + }; +}; + +&mali { + mali-supply = <&vddee>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <50000000>; + + cap-mmc-highspeed; + disable-wp; + non-removable; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vcc_3v3>; + }; +}; + +&gpio_ao { + gpio-line-names = "Linux_TX", "Linux_RX", + "SLP_S5_N", "USB2_OC_FLAG#", + "HUB_RST", "USB_PWR_EN", + "I2S_IN", "SLP_S1_N", + "TCK", "TMS", "TDI", "TDO", + "HDMI_CEC", "5640_IRQ", + "MUTE", "S805_TEST#"; +}; + +&gpio { + gpio-line-names = /* Bank GPIOX */ + "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", + "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", + "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", + "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", + "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", + "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", + /* Bank GPIOY */ + "", "", "", "", "", "", "", "", "", "", + "", "", + /* Bank GPIODV */ + "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", + "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", + "VDDEE_PWM 3V3_5V_EN", + /* Bank GPIOH */ + "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", + "RMII_IRQ", "RMII_RST#", "RMII_TXD1", + "RMII_TXD0", "AV_select_1", "AV_select_2", + "MCU_Control_S", + /* Bank CARD */ + "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", + "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", + "CARD_EN_DET (CARD_DET)", + /* Bank BOOT */ + "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", + "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", + "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", + "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", + "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", + "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", + "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", + "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", + /* Bank DIF */ + "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", + "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", + "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", + "RMII_MDIO"; +}; + +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; + pinctrl-names = "default"; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; +}; + +&rtc { + status = "okay"; + clocks = <&rtc32k_xtal>; + vdd-supply = <&vcc_rtc>; +}; + +/* exposed through the pin headers labeled "URDUG1" on the top of the PCB */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +/* + * connected to the Bluetooth part of the RTL8723BS SDIO wifi / Bluetooth + * combo chip. This is only available on the variant with 2GB RAM. + */ +&uart_B { + status = "okay"; + pinctrl-0 = <&uart_b0_pins>, <&uart_b0_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts new file mode 100644 index 000000000000..7adedd3258c3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2015 Endless Mobile, Inc. + * Author: Carlo Caione + */ + +/dts-v1/; + +#include + +#include "meson8b.dtsi" + +/ { + model = "TRONFY MXQ S805"; + compatible = "tronfy,mxq", "amlogic,meson8b"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + vcck: regulator-vcck { + compatible = "pwm-regulator"; + + regulator-name = "VCCK"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&vcc_5v>; + + pwms = <&pwm_cd 0 1148 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v>; + }; + + vcc_5v: regulator-vcc5v { + compatible = "regulator-fixed"; + + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-boot-on; + regulator-always-on; + }; + + vddee: regulator-vddee { + compatible = "pwm-regulator"; + + regulator-name = "VDDEE"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&vcc_5v>; + + pwms = <&pwm_cd 1 1148 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <&vcck>; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* IC Plus IP101A/G (0x02430c54) */ + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&mali { + mali-supply = <&vddee>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vcc_3v3>; + }; +}; + +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; + pinctrl-names = "default"; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts new file mode 100644 index 000000000000..941682844faf --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2015 Endless Mobile, Inc. + * Author: Carlo Caione + */ + +/dts-v1/; +#include "meson8b.dtsi" +#include + +/ { + model = "Hardkernel ODROID-C1"; + compatible = "hardkernel,odroid-c1", "amlogic,meson8b"; + + aliases { + serial0 = &uart_AO; + mmc0 = &sd_card_slot; + mmc1 = &sdhc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + led-blue { + label = "c1:blue:alive"; + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + p5v0: regulator-p5v0 { + compatible = "regulator-fixed"; + + regulator-name = "P5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + tflash_vdd: regulator-tflash_vdd { + /* + * signal name from schematics: TFLASH_VDD_EN + */ + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_3v3>; + + gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_3v3>; + + /* + * signal name from schematics: TF_3V3N_1V8_EN + */ + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0 + 1800000 1>; + }; + + rtc32k_xtal: rtc32k-xtal-clk { + /* X3 in the schematics */ + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "RTC32K"; + #clock-cells = <0>; + }; + + vcc_1v8: regulator-vcc-1v8 { + /* + * RICHTEK RT9179 configured for a fixed output voltage of + * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and + * VDD1V8 according to the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&p5v0>; + }; + + vcc_3v3: regulator-vcc-3v3 { + /* + * Monolithic Power Systems MP2161 configured for a fixed + * output voltage of 3.3V. This supplies not only VCC3V3 but + * also VDD3V3 and VDDIO_AO3V3 according to the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&p5v0>; + }; + + vcck: regulator-vcck { + /* Monolithic Power Systems MP2161 */ + compatible = "pwm-regulator"; + + regulator-name = "VCCK"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&p5v0>; + + pwms = <&pwm_cd 0 12218 0>; + pwm-dutycycle-range = <91 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddc_ddr: regulator-vddc-ddr { + /* + * Monolithic Power Systems MP2161 configured for a fixed + * output voltage of 1.5V. This supplies not only DDR_VDDC but + * also DDR3_1V5 according to the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "DDR_VDDC"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&p5v0>; + }; + + vddee: regulator-vddee { + /* Monolithic Power Systems MP2161 */ + compatible = "pwm-regulator"; + + regulator-name = "VDDEE"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&p5v0>; + + pwms = <&pwm_cd 1 12218 0>; + pwm-dutycycle-range = <91 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vdd_rtc: regulator-vdd-rtc { + /* + * Torex Semiconductor XC6215 configured for a fixed output of + * 0.9V. + */ + compatible = "regulator-fixed"; + + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&vcc_3v3>; + }; +}; + +&cpu0 { + cpu-supply = <&vcck>; +}; + +&efuse { + ethernet_mac_address: mac@1b4 { + reg = <0x1b4 0x6>; + }; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy>; + phy-mode = "rgmii-id"; + + nvmem-cells = <ðernet_mac_address>; + nvmem-cell-names = "mac-address"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Realtek RTL8211F (0x001cc916) */ + eth_phy: ethernet-phy@0 { + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&gpio { + gpio-line-names = /* Bank GPIOX */ + "J2 Header Pin 35", "J2 Header Pin 36", + "J2 Header Pin 32", "J2 Header Pin 31", + "J2 Header Pin 29", "J2 Header Pin 18", + "J2 Header Pin 22", "J2 Header Pin 16", + "J2 Header Pin 23", "J2 Header Pin 21", + "J2 Header Pin 19", "J2 Header Pin 33", + "J2 Header Pin 8", "J2 Header Pin 10", + "J2 Header Pin 15", "J2 Header Pin 13", + "J2 Header Pin 24", "J2 Header Pin 26", + /* Bank GPIOY */ + "Revision (upper)", "Revision (lower)", + "J2 Header Pin 7", "", "J2 Header Pin 12", + "J2 Header Pin 11", "", "", "", + "TFLASH_VDD_EN", "", "", + /* Bank GPIODV */ + "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL", + "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)", + "", + /* Bank GPIOH */ + "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", + "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1", + "ETH_TXD0", "ETH_TXD3", "ETH_TXD2", + "ETH_RGMII_TX_CLK", + /* Bank CARD */ + "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)", + "SD_CLK", "SD_CMD", "SD_DATA3 (SDB_D3)", + "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)", + /* Bank BOOT */ + "SDC_D0 (EMMC)", "SDC_D1 (EMMC)", + "SDC_D2 (EMMC)", "SDC_D3 (EMMC)", + "SDC_D4 (EMMC)", "SDC_D5 (EMMC)", + "SDC_D6 (EMMC)", "SDC_D7 (EMMC)", + "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)", + "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "", + "", "", "", "", + /* Bank DIF */ + "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV", + "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2", + "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", + "ETH_MDC", "ETH_MDIO"; +}; + +&gpio_ao { + gpio-line-names = "UART TX", "UART RX", "", + "TF_3V3N_1V8_EN", "USB_HUB_RST_N", + "USB_OTG_PWREN", "J7 Header Pin 2", + "IR_IN", "J7 Header Pin 4", + "J7 Header Pin 6", "J7 Header Pin 5", + "J7 Header Pin 7", "HDMI_CEC", + "SYS_LED", "", ""; +}; + +&ir_receiver { + status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; +}; + +&mali { + mali-supply = <&vddee>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <100000000>; + + disable-wp; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; +}; + +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; + }; +}; + +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; + pinctrl-names = "default"; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; +}; + +&rtc { + /* needs to be enabled manually when a battery is connected */ + clocks = <&rtc32k_xtal>; + vdd-supply = <&vdd_rtc>; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub@1 { + /* Genesys Logic GL852G usb hub */ + compatible = "usb5e3,610"; + reg = <1>; + vdd-supply = <&p5v0>; + reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi new file mode 100644 index 000000000000..5198f5177c2c --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2015 Endless Mobile, Inc. + * Author: Carlo Caione + */ + +#include +#include +#include +#include +#include +#include +#include +#include "meson.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x200>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x201>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu2: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x202>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu3: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + next-level-cache = <&L2>; + reg = <0x203>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-96000000 { + opp-hz = /bits/ 64 <96000000>; + opp-microvolt = <860000>; + }; + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <860000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <860000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <860000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <860000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <860000>; + }; + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <860000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1140000>; + }; + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <1140000>; + }; + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <1140000>; + }; + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-microvolt = <1140000>; + }; + }; + + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-255000000 { + opp-hz = /bits/ 64 <255000000>; + opp-microvolt = <1100000>; + }; + opp-364285714 { + opp-hz = /bits/ 64 <364285714>; + opp-microvolt = <1100000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1100000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1100000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1100000>; + turbo-mode; + }; + }; + + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom@0 { + reg = <0x0 0x200000>; + no-map; + }; + }; + + thermal-zones { + soc { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermal_sensor>; + + cooling-maps { + map0 { + trip = <&soc_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&soc_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + soc_passive: soc-passive { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + soc_hot: soc-hot { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + soc_critical: soc-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + }; + }; + + mmcbus: bus@c8000000 { + compatible = "simple-bus"; + reg = <0xc8000000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000000 0x8000>; + + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8b-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + + dmcbus: bus@6000 { + compatible = "simple-bus"; + reg = <0x6000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x400>; + + canvas: video-lut@48 { + compatible = "amlogic,meson8b-canvas", + "amlogic,canvas"; + reg = <0x48 0x14>; + }; + }; + }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8b-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; +}; /* end of / */ + +&aiu { + compatible = "amlogic,aiu-meson8b", "amlogic,aiu"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; +}; + +&aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xe0 0x18>; + }; + + pinctrl_aobus: pinctrl@84 { + compatible = "amlogic,meson8b-aobus-pinctrl"; + reg = <0x84 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: ao-bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; + }; + + i2s_am_clk_pins: i2s-am-clk-out { + mux { + groups = "i2s_am_clk_out"; + function = "i2s"; + bias-disable; + }; + }; + + i2s_out_ao_clk_pins: i2s-ao-clk-out { + mux { + groups = "i2s_ao_clk_out"; + function = "i2s"; + bias-disable; + }; + }; + + i2s_out_lr_clk_pins: i2s-lr-clk-out { + mux { + groups = "i2s_lr_clk_out"; + function = "i2s"; + bias-disable; + }; + }; + + i2s_out_ch01_ao_pins: i2s-out-ch01 { + mux { + groups = "i2s_out_01"; + function = "i2s"; + bias-disable; + }; + }; + + spdif_out_1_pins: spdif-out-1 { + mux { + groups = "spdif_out_1"; + function = "spdif_1"; + bias-disable; + }; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + bias-disable; + }; + }; + + ir_recv_pins: remote { + mux { + groups = "remote_input"; + function = "remote"; + bias-disable; + }; + }; + }; +}; + +&ao_arc_rproc { + compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; + amlogic,secbus2 = <&secbus2>; + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; +}; + +&cbus { + reset: reset-controller@4404 { + compatible = "amlogic,meson8b-reset"; + reg = <0x4404 0x9c>; + #reset-cells = <1>; + }; + + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8b-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x86c0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + clock-measure@8758 { + compatible = "amlogic,meson8b-clk-measure"; + reg = <0x8758 0x1c>; + }; + + pinctrl_cbus: pinctrl@9880 { + compatible = "amlogic,meson8b-cbus-pinctrl"; + reg = <0x9880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x38>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 83>; + }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_tx_clk", + "eth_tx_en", + "eth_txd1_0", + "eth_txd0_0", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd1", + "eth_rxd0", + "eth_mdio_en", + "eth_mdc", + "eth_ref_clk", + "eth_txd2", + "eth_txd3", + "eth_rxd3", + "eth_rxd2"; + function = "ethernet"; + bias-disable; + }; + }; + + eth_rmii_pins: eth-rmii { + mux { + groups = "eth_tx_en", + "eth_txd1_0", + "eth_txd0_0", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd1", + "eth_rxd0", + "eth_mdio_en", + "eth_mdc"; + function = "ethernet"; + bias-disable; + }; + }; + + i2c_a_pins: i2c-a { + mux { + groups = "i2c_sda_a", "i2c_sck_a"; + function = "i2c_a"; + bias-disable; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + bias-disable; + }; + }; + + sdxc_c_pins: sdxc-c { + mux { + groups = "sdxc_d0_c", "sdxc_d13_c", + "sdxc_d47_c", "sdxc_clk_c", + "sdxc_cmd_c"; + function = "sdxc_c"; + bias-pull-up; + }; + }; + + pwm_c1_pins: pwm-c1 { + mux { + groups = "pwm_c1"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_d_pins: pwm-d { + mux { + groups = "pwm_d"; + function = "pwm_d"; + bias-disable; + }; + }; + + uart_b0_pins: uart-b0 { + mux { + groups = "uart_tx_b0", + "uart_rx_b0"; + function = "uart_b"; + bias-disable; + }; + }; + + uart_b0_cts_rts_pins: uart-b0-cts-rts { + mux { + groups = "uart_cts_b0", + "uart_rts_b0"; + function = "uart_b"; + bias-disable; + }; + }; + }; +}; + +&ahb_sram { + ao_arc_sram: ao-arc-sram@0 { + compatible = "amlogic,meson8b-ao-arc-sram"; + reg = <0x0 0x8000>; + pool; + }; + + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + + +&efuse { + compatible = "amlogic,meson8b-efuse"; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; +}; + +ðmac { + compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; + + reg = <0xc9410000 0x10000 + 0xc1108140 0x4>; + + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; + rx-fifo-depth = <4096>; + tx-fifo-depth = <2048>; + + resets = <&reset RESET_ETHERNET>; + reset-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; +}; + +&gpio_intc { + compatible = "amlogic,meson8b-gpio-intc", + "amlogic,meson-gpio-intc"; + status = "okay"; +}; + +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8b-clkc"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pwrc: power-controller { + compatible = "amlogic,meson8b-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", + "venci", "vencp", "vdac", "vencl", "viu", + "venc", "rdma"; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <182142857>; + }; +}; + +&hwrng { + compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + +&i2c_AO { + clocks = <&clkc CLKID_CLK81>; +}; + +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + +&L2 { + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,prefetch-offset = <7>; + arm,double-linefill = <1>; + arm,prefetch-drop = <1>; + arm,shared-override; +}; + +&periph { + scu@0 { + compatible = "arm,cortex-a5-scu"; + reg = <0x0 0x100>; + }; + + timer@200 { + compatible = "arm,cortex-a5-global-timer"; + reg = <0x200 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + + /* + * the arm_global_timer driver currently does not handle clock + * rate changes. Keep it disabled for now. + */ + status = "disabled"; + }; + + timer@600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + }; +}; + +&pwm_ab { + compatible = "amlogic,meson8b-pwm"; +}; + +&pwm_cd { + compatible = "amlogic,meson8b-pwm"; +}; + +&rtc { + compatible = "amlogic,meson8b-rtc"; + resets = <&reset RESET_RTC>; +}; + +&saradc { + compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; + clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; +}; + +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + +&secbus { + secbus2: system-controller@4000 { + compatible = "amlogic,meson8b-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; +}; + +&sdio { + compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; +}; + +&timer_abcde { + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk"; +}; + +&uart_AO { + compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_A { + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_C { + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; +}; + +&usb0 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&usb1_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&wdt { + compatible = "amlogic,meson8b-wdt"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts new file mode 100644 index 000000000000..aa4d4bf70629 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Oleg Ivanov + * Copyright (c) 2018 Martin Blumenstingl + */ + +/dts-v1/; + +#include "meson8m2.dtsi" + +#include +#include + +/ { + model = "Tronsmart MXIII Plus"; + compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2"; + + aliases { + ethernet0 = ðmac; + i2c0 = &i2c_AO; + serial0 = &uart_AO; + mmc0 = &sd_card_slot; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Function"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + + pinctrl-0 = <&xtal_32k_out_pins>; + pinctrl-names = "default"; + + reset-gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>, + <&gpio_ao GPIOAO_6 GPIO_ACTIVE_LOW>; + + clocks = <&xtal_32k_out>; + clock-names = "ext_clock"; + }; + + vcc_3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + xtal_32k_out: xtal-32k-out-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32k_out"; + }; +}; + +&cpu0 { + cpu-supply = <&vcck>; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rgmii-id"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ir_receiver { + status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_pins>; + pinctrl-names = "default"; + + pmic@32 { + compatible = "ricoh,rn5t618"; + reg = <0x32>; + system-power-controller; + + regulators { + vcck: DCDC1 { + regulator-name = "VCCK"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vddee: DCDC2 { + /* the output is also used as VDDAO */ + regulator-name = "VDD_EE"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + DCDC3 { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "VDDIO_AO28"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + + vddio_ao1v8: LDO2 { + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "VCC2V8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "AVDD1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDORTC1 { + regulator-name = "VDD_LDO"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-boot-on; + regulator-always-on; + }; + + LDORTC2 { + regulator-name = "RTC_0V9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&mali { + mali-supply = <&vddee>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO wifi */ +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_a_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + max-frequency = <50000000>; + + disable-wp; + non-removable; + cap-mmc-highspeed; + cap-sd-highspeed; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vcc_3v3>; + }; +}; + +/* connected to the Bluetooth module */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm20702a1"; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi new file mode 100644 index 000000000000..6725dd9fd825 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8m2.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Martin Blumenstingl . + */ + +#include "meson8.dtsi" + +/ { + model = "Amlogic Meson8m2 SoC"; + compatible = "amlogic,meson8m2"; +}; /* end of / */ + +&clkc { + compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc"; +}; + +&dmcbus { + /* the offset of the canvas registers has changed compared to Meson8 */ + /delete-node/ video-lut@20; + + canvas: video-lut@48 { + compatible = "amlogic,meson8m2-canvas", "amlogic,canvas"; + reg = <0x48 0x14>; + }; +}; + +ðmac { + compatible = "amlogic,meson8m2-dwmac", "snps,dwmac"; + reg = <0xc9410000 0x10000 + 0xc1108140 0x8>; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; + resets = <&reset RESET_ETHERNET>; + reset-names = "stmmaceth"; +}; + +&pinctrl_aobus { + compatible = "amlogic,meson8m2-aobus-pinctrl", + "amlogic,meson8-aobus-pinctrl"; +}; + +&pinctrl_cbus { + compatible = "amlogic,meson8m2-cbus-pinctrl", + "amlogic,meson8-cbus-pinctrl"; + + eth_rgmii_pins: ethernet { + mux { + groups = "eth_tx_clk_50m", "eth_tx_en", + "eth_txd3", "eth_txd2", + "eth_txd1", "eth_txd0", + "eth_rx_clk_in", "eth_rx_dv", + "eth_rxd3", "eth_rxd2", + "eth_rxd1", "eth_rxd0", + "eth_mdio", "eth_mdc"; + function = "ethernet"; + bias-disable; + }; + }; +}; + +&pwrc { + compatible = "amlogic,meson8m2-pwrc"; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci", + "vencp", "vdac", "vencl", "viu", "venc", "rdma"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364000000>; +}; + +&saradc { + compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; +}; + +&sdhc { + compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; +}; + +&usb0_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + +&usb1_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + +&wdt { + compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; +}; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts deleted file mode 100644 index 29936bfbeeb7..000000000000 --- a/arch/arm/boot/dts/animeo_ip.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Somfy Animeo IP"; - compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9"; - - aliases { - serial0 = &usart1; - serial1 = &usart2; - serial2 = &usart0; - serial3 = &dbgu; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - }; - - chosen { - stdout-path = &usart2; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - usart1: serial@fffb4000 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - usart2: serial@fffb8000 { - pinctrl-0 = <&pinctrl_usart2>; - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>; - phy-mode = "mii"; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = <&pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - barebox@0 { - label = "barebox"; - reg = <0x0 0x58000>; - }; - - u_boot_env@58000 { - label = "u_boot_env"; - reg = <0x58000 0x8000>; - }; - - ubi@60000 { - label = "ubi"; - reg = <0x60000 0x1FA0000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green { - label = "power_green"; - gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - power_red { - label = "power_red"; - gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; - }; - - tx_green { - label = "tx_green"; - gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; - }; - - tx_red { - label = "tx_red"; - gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-switch-in { - label = "keyswitch_in"; - gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; - linux,code = <28>; - wakeup-source; - }; - - key-error-in { - label = "error_in"; - gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; - linux,code = <29>; - wakeup-source; - }; - - key-s { - label = "btn"; - gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; - linux,code = <31>; - wakeup-source; - }; - }; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts deleted file mode 100644 index e18769df9fd9..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp-ctrevb.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/* - * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and - * the Rev B core tile. - */ -/ { - model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts deleted file mode 100644 index 26b1c69e9f43..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts deleted file mode 100644 index e68527b0d552..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; -}; - -/* - * The revision B has a distinctly different layout of the syscon, so - * append a specific compatible-string. - */ -&syscon { - compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; -}; - -&intc { - reg = <0x10101000 0x1000>, - <0x10100100 0x100>; -}; - -&L2 { - reg = <0x10102000 0x1000>; -}; - -&scu { - reg = <0x10100000 0x100>; -}; - -&twd_timer { - reg = <0x10100600 0x20>; -}; - -&twd_wdog { - reg = <0x10100620 0x20>; -}; - -/* - * On revision B, we cannot reach the secondary interrupt - * controller, as a result, some peripherals that are dependent - * on their IRQ cannot be reached, so disable them. - */ -&intc_second { - status = "disabled"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&serial2 { - status = "disabled"; -}; - -&serial3 { - status = "disabled"; -}; - -&ssp { - status = "disabled"; -}; - -&wdog { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm-realview-eb-11mp.dts deleted file mode 100644 index aac1edd4b227..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-11mp.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-eb-mp.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; - arm,hbi = <0x146>; - - /* - * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB. - * Reference: ARM DUI 0318F - * - * To run this machine with QEMU, specify the following: - * qemu-system-arm -M realview-eb-mpcore -smp cpus=4 - */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - MP11_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <0>; - next-level-cache = <&L2>; - }; - - MP11_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <1>; - next-level-cache = <&L2>; - }; - - MP11_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <2>; - next-level-cache = <&L2>; - }; - - MP11_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; -}; - -&pmu { - interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts b/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts deleted file mode 100644 index 42efac7496ef..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-a9mp.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp.dts b/arch/arm/boot/dts/arm-realview-eb-a9mp.dts deleted file mode 100644 index 967684b3636c..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-a9mp.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-eb-mp.dtsi" - -/ { - model = "ARM RealView EB Cortex A9 MPCore"; - - /* - * This is the Cortex A9 MPCore tile used with the - * RealView EB. - */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; -}; - -&pmu { - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts b/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts deleted file mode 100644 index f533c8b49d97..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* This derives from the Realview Baseboard, and overlays the new ethernet */ -#include "arm-realview-eb.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard Rev D"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi deleted file mode 100644 index a79e1d1d30a7..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/ { - /* Introduce a fixed regulator for the new ethernet controller */ - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -/* - * The revision D has a different ethernet controller that the elder boards: - * the older board uses LAN91C111 but the new one uses LAN9118. - */ -ðernet { - compatible = "smsc,lan9118", "smsc,lan9115"; - phy-mode = "mii"; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi deleted file mode 100644 index 26783d053ac7..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include "arm-realview-eb.dtsi" - -/* - * This is the common include file for all MPCore variants of the - * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B - * and Cortex-A9 MPCore. - */ -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - /* Primary interrupt controller in the test chip */ - intc: interrupt-controller@1f000100 { - compatible = "arm,eb11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; - - /* Secondary interrupt controller on the FPGA */ - intc_second: interrupt-controller@10040000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - L2: cache-controller { - compatible = "arm,l220-cache"; - reg = <0x1f002000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s), probably for safety - * since th outer sync operation can cause the - * cache to hang unless disabled. - */ - cache-size = <1048576>; // 1MB - cache-sets = <4096>; - cache-line-size = <32>; - arm,shared-override; - arm,parity-enable; - arm,outer-sync-disable; - }; - - scu: scu@1f000000 { - compatible = "arm,arm11mp-scu"; - reg = <0x1f000000 0x100>; - }; - - twd_timer: timer@1f000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 13 0xf04>; - }; - - twd_wdog: watchdog@1f000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 14 0xf04>; - }; - - /* PMU with one IRQ line per core */ - pmu: pmu@0 { - compatible = "arm,arm11mpcore-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; - -/* - * This adapts all the peripherals to the interrupt routing - * to the GIC on the core tile. - */ - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -/* - * On revision A, these peripherals does not have their IRQ lines - * routed to the core tile, but they can be reached on the secondary - * GIC. - */ -&gpio0 { - interrupt-parent = <&intc_second>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc_second>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc_second>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc_second>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&serial3 { - interrupt-parent = <&intc_second>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&ssp { - interrupt-parent = <&intc_second>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&wdog { - interrupt-parent = <&intc_second>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb.dts b/arch/arm/boot/dts/arm-realview-eb.dts deleted file mode 100644 index 15431077f00c..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "arm-realview-eb.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard"; - compatible = "arm,realview-eb"; - arm,hbi = <0x140>; - - /* - * This is the core tile with the CPU and GIC etc for the - * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache - * or PMU. - * - * To run this machine with QEMU, specify the following: - * qemu-system-arm -M realview-eb - * Unless specified, QEMU will emulate an ARM926EJ-S core tile. - * Switches -cpu arm1136 or -cpu arm1176 emulates the other - * core tiles. - */ - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - intc: interrupt-controller@10040000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - }; - }; -}; - -/* - * This adapts all the peripherals to the interrupt routing - * to the GIC on the core tile. - */ - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&charlcd { - interrupt-parent = <&intc>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi deleted file mode 100644 index fbb2258b451f..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb"; - - chosen { }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c; - }; - - memory { - device_type = "memory"; - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - flash1@44000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - /* SMSC LAN91C111 ethernet with PHY and EEPROM */ - ethernet: ethernet@4e000000 { - compatible = "smsc,lan91c111"; - reg = <0x4e000000 0x10000>; - /* - * This means the adapter can be accessed with 8, 16 or - * 32 bit reads/writes. - */ - reg-io-width = <7>; - }; - - usb: usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - dr_mode = "peripheral"; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - /* These peripherals are inside the FPGA */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - ranges = <0x0 0x10000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - led@8,0 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8,1 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8,2 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8,3 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8,4 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8,5 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8,6 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8,7 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: clock-controller@c { - compatible = "arm,syscon-icst307"; - reg = <0x0c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: clock-controller@10 { - compatible = "arm,syscon-icst307"; - reg = <0x10 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: clock-controller@14 { - compatible = "arm,syscon-icst307"; - reg = <0x14 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: clock-controller@18 { - compatible = "arm,syscon-icst307"; - reg = <0x18 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: clock-controller@1c { - compatible = "arm,syscon-icst307"; - reg = <0x1c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - i2c: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mmc: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - charlcd: fpga_charlcd: charlcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp: spi@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - clocks = <&sspclk>, <&pclk>; - clock-names = "sspclk", "apb_pclk"; - }; - - wdog: watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdog_clk", "apb_pclk"; - status = "disabled"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - clcd: clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - clocks = <&oscclk0>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts deleted file mode 100644 index efed325af88d..000000000000 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ /dev/null @@ -1,608 +0,0 @@ -/* - * Copyright 2014 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "ARM RealView PB1176"; - compatible = "arm,realview-pb1176"; - - chosen { }; - - aliases { - serial0 = &pb1176_serial0; - serial1 = &pb1176_serial1; - serial2 = &pb1176_serial2; - serial3 = &pb1176_serial3; - serial4 = &fpga_serial; - }; - - memory { - device_type = "memory"; - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: regulator-veth { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash@30000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x30000000 0x4000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - fpga_flash@38000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x38000000 0x800000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - /* - * The "secure flash" contains things like the boot - * monitor so we don't want people to accidentally - * screw this up. Mark the device tree node disabled - * by default. - */ - secflash@3c000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x3c000000 0x4000000>; - bank-width = <4>; - status = "disabled"; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet@3a000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x3a000000 0x10000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb@3b000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x3b000000 0x20000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "peripheral"; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb1176-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - ranges = <0x0 0x10000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - led@8,0 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8,1 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8,2 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8,3 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8,4 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8,5 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8,6 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8,7 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: clock-controller@c { - compatible = "arm,syscon-icst307"; - reg = <0x0c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: clock-controller@10 { - compatible = "arm,syscon-icst307"; - reg = <0x10 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: clock-controller@14 { - compatible = "arm,syscon-icst307"; - reg = <0x14 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: clock-controller@18 { - compatible = "arm,syscon-icst307"; - reg = <0x18 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: clock-controller@1c { - compatible = "arm,syscon-icst307"; - reg = <0x1c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - /* Primary DevChip GIC synthesized with the CPU */ - intc_dc1176: interrupt-controller@10120000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10121000 0x1000>, - <0x10120000 0x100>; - }; - - L2: cache-controller { - compatible = "arm,l220-cache"; - reg = <0x10110000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s). - */ - arm,override-auxreg; - cache-size = <131072>; // 128kB - cache-sets = <512>; - cache-line-size = <32>; - }; - - pmu { - compatible = "arm,arm1176-pmu"; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer01: timer@10104000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10104000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer23: timer@10105000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10105000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - pb1176_rtc: rtc@10108000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10108000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pb1176_gpio0: gpio@1010a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x1010a000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pb1176_ssp: spi@1010b000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1010b000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sspclk>, <&pclk>; - clock-names = "sspclk", "apb_pclk"; - }; - - pb1176_serial0: serial@1010c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010c000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial1: serial@1010d000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010d000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial2: serial@1010e000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010e000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial3: serial@1010f000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010f000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - /* Direct-mapped development chip ROM */ - pb1176_rom@10200000 { - compatible = "direct-mapped"; - reg = <0x10200000 0x4000>; - bank-width = <1>; - }; - - clcd@10112000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10112000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupt-names = "combined"; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&oscclk0>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - /* These peripherals are inside the FPGA rather than the DevChip */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - fpga_aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_mci: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>; - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - fpga_kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - fpga_kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - fpga_charlcd: charlcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_serial: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - /* This GIC on the board is cascaded off the DevChip GIC */ - intc_fpga1176: interrupt-controller@10040000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - }; - - fpga_gpio0: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_gpio1: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts deleted file mode 100644 index 89103d54ecc1..000000000000 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ /dev/null @@ -1,736 +0,0 @@ -/* - * Copyright 2015 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "ARM RealView PB11MPcore"; - compatible = "arm,realview-pb11mp"; - - chosen { }; - - aliases { - serial0 = &pb11mp_serial0; - serial1 = &pb11mp_serial1; - serial2 = &pb11mp_serial2; - serial3 = &pb11mp_serial3; - }; - - memory { - device_type = "memory"; - /* - * The PB11MPCore has 512 MiB memory @ 0x70000000 - * and the first 256 are also remapped @ 0x00000000 - */ - reg = <0x70000000 0x20000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - MP11_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <0>; - next-level-cache = <&L2>; - }; - - MP11_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <1>; - next-level-cache = <&L2>; - }; - - MP11_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <2>; - next-level-cache = <&L2>; - }; - - MP11_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - /* Primary TestChip GIC synthesized with the CPU */ - intc_tc11mp: interrupt-controller@1f000100 { - compatible = "arm,tc11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; - - L2: cache-controller { - compatible = "arm,l220-cache"; - reg = <0x1f002000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s), probably for safety - * since th outer sync operation can cause the - * cache to hang unless disabled. - */ - cache-size = <1048576>; // 1MB - cache-sets = <4096>; - cache-line-size = <32>; - arm,shared-override; - arm,parity-enable; - arm,outer-sync-disable; - }; - - scu@1f000000 { - compatible = "arm,arm11mp-scu"; - reg = <0x1f000000 0x100>; - }; - - timer@1f000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1f000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <1 14 0xf04>; - }; - - /* PMU with one IRQ line per core */ - pmu { - compatible = "arm,arm11mpcore-pmu"; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: regulator-veth { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - flash1@44000000 { - // 2 * 32MiB NOR Flash memory - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - /* - * This DDC I2C is connected directly to the DVI portions - * of the connector, so it's not really working when the - * monitor is connected to the VGA connector. - */ - compatible = "vga-connector"; - ddc-i2c-bus = <&i2c1>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb11mp-soc", "simple-bus"; - regmap = <&pb11mp_syscon>; - ranges; - - pb11mp_syscon: syscon@10000000 { - compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - ranges = <0x0 0x10000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - led@8,0 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8,1 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8,2 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8,3 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - linux,default-trigger = "cpu1"; - default-state = "off"; - }; - led@8,4 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - linux,default-trigger = "cpu2"; - default-state = "off"; - }; - led@8,5 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - linux,default-trigger = "cpu3"; - default-state = "off"; - }; - led@8,6 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8,7 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - - oscclk0: clock-controller@c { - compatible = "arm,syscon-icst307"; - reg = <0x0c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: clock-controller@10 { - compatible = "arm,syscon-icst307"; - reg = <0x10 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: clock-controller@14 { - compatible = "arm,syscon-icst307"; - reg = <0x14 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: clock-controller@18 { - compatible = "arm,syscon-icst307"; - reg = <0x18 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: clock-controller@1c { - compatible = "arm,syscon-icst307"; - reg = <0x1c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - oscclk5: clock-controller@d4 { - compatible = "arm,syscon-icst307"; - reg = <0xd4 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0xd4>; - clocks = <&xtal24mhz>; - }; - oscclk6: clock-controller@d8 { - compatible = "arm,syscon-icst307"; - reg = <0xd8 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0xd8>; - clocks = <&xtal24mhz>; - }; - }; - - sp810_syscon: sysctl@10001000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x10001000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk0", - "timerclk1", - "timerclk2", - "timerclk3"; - assigned-clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, - <&sp810_syscon 2>, - <&sp810_syscon 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mci: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - pb11mp_serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - spi@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sspclk>, <&pclk>; - clock-names = "sspclk", "apb_pclk"; - }; - - watchdog@1000f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x1000f000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdog_clk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, - <&pclk>; - clock-names = "timer0clk", - "timer1clk", - "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&sp810_syscon 2>, - <&sp810_syscon 3>, - <&pclk>; - clock-names = "timer0clk", - "timer1clk", - "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - i2c1: i2c@10016000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10016000 0x1000>; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer45: timer@10018000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - timer67: timer@10019000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupt-names = "combined"; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&oscclk4>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - /* - * This GIC on the Platform Baseboard is cascaded off the - * TestChip GIC - */ - intc_pb11mp: interrupt-controller@1e000000 { - compatible = "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000000 0x100>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x4e000000 0x10000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "peripheral"; - }; - }; -}; diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm-realview-pba8.dts deleted file mode 100644 index d3238c252b59..000000000000 --- a/arch/arm/boot/dts/arm-realview-pba8.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-pbx.dtsi" - -/ { - model = "ARM RealView Platform Baseboard for Cortex-A8"; - compatible = "arm,realview-pba8"; - arm,hbi = <0x178>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - }; - }; - - pmu: pmu@0 { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; - }; - - /* Primary GIC PL390 interrupt controller in the test chip */ - intc: interrupt-controller@1e000000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000000 0x100>; - }; -}; - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&soc { - compatible = "arm,realview-pba8-soc", "simple-bus"; -}; - -&syscon { - compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog0 { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog1 { - interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer45 { - interrupt-parent = <&intc>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer67 { - interrupt-parent = <&intc>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts deleted file mode 100644 index 85d3968fbb91..000000000000 --- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-pbx.dtsi" - -/ { - /* - * This is the RealView Platform Baseboard Explore for Cortex-A9 - * (HBI0182 + HBI0183) as described in ARM DUI 0440B - */ - model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; - arm,hbi = <0x182>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - }; - }; - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x1>; - next-level-cache = <&L2>; - }; - }; - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0x1f002000 0x1000>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s). - */ - cache-size = <131072>; // 128KB - cache-sets = <512>; - cache-line-size = <32>; - arm,parity-disable; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - }; - - scu: scu@1f000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1f000000 0x100>; - }; - - twd_timer: timer@1f000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 13 0xf04>; - }; - - twd_wdog: watchdog@1f000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 14 0xf04>; - }; - - pmu: pmu@0 { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, - <0 45 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CPU0>, <&CPU1>; - }; - - /* Primary GIC PL390 interrupt controller in the test chip */ - intc: interrupt-controller@1f000000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; -}; - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog0 { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog1 { - interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer45 { - interrupt-parent = <&intc>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer67 { - interrupt-parent = <&intc>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi deleted file mode 100644 index ec1507c5147c..000000000000 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ /dev/null @@ -1,593 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pbx"; - - chosen { }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - memory { - device_type = "memory"; - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: regulator-veth { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - refclk32khz: refclk32khz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - flash1@44000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet: ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x4e000000 0x10000>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb: usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - dr_mode = "peripheral"; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - /* - * This DDC I2C is connected directly to the DVI portions - * of the connector, so it's not really working when the - * monitor is connected to the VGA connector. - */ - compatible = "vga-connector"; - ddc-i2c-bus = <&i2c1>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - soc: soc { - compatible = "arm,realview-pbx-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - regmap = <&syscon>; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - ranges = <0x0 0x10000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - led@8,0 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8,1 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8,2 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8,3 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8,4 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8,5 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8,6 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8,7 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: clock-controller@c { - compatible = "arm,syscon-icst307"; - reg = <0x0c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: clock-controller@10 { - compatible = "arm,syscon-icst307"; - reg = <0x10 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: clock-controller@14 { - compatible = "arm,syscon-icst307"; - reg = <0x14 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: clock-controller@18 { - compatible = "arm,syscon-icst307"; - reg = <0x18 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: clock-controller@1c { - compatible = "arm,syscon-icst307"; - reg = <0x1c 0x04>; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - sp810_syscon0: sysctl@10001000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x10001000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk0", - "timerclk1", - "timerclk2", - "timerclk3"; - assigned-clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, - <&sp810_syscon0 2>, - <&sp810_syscon0 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp: spi@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - clocks = <&sspclk>, <&pclk>; - clock-names = "sspclk", "apb_pclk"; - }; - - wdog0: watchdog@1000f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x1000f000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdog_clk", "apb_pclk"; - status = "disabled"; - }; - - wdog1: watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdog_clk", "apb_pclk"; - status = "disabled"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, - <&pclk>; - clock-names = "timerclk0", - "timerclk1", - "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - clocks = <&sp810_syscon0 2>, - <&sp810_syscon0 3>, - <&pclk>; - clock-names = "timerclk2", - "timerclk3", - "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - i2c1: i2c@10016000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10016000 0x1000>; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer45: timer@10018000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timerclk4", "timerclk5", "apb_pclk"; - }; - - timer67: timer@10019000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timerclk6", "timerclk7", "apb_pclk"; - }; - - sp810_syscon1: sysctl@1001a000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x1001a000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk4", - "timerclk5", - "timerclk6", - "timerclk7"; - assigned-clocks = <&sp810_syscon1 0>, - <&sp810_syscon1 1>, - <&sp810_syscon1 2>, - <&sp810_syscon1 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - }; - - - /* These peripherals are inside the FPGA */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mmc: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - }; - - /* These peripherals are inside the NEC ISSP */ - issp { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - clcd: clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - clocks = <&oscclk4>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/arm/Makefile b/arch/arm/boot/dts/arm/Makefile new file mode 100644 index 000000000000..07ebb64e2cd0 --- /dev/null +++ b/arch/arm/boot/dts/arm/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_INTEGRATOR) += \ + integratorap.dtb \ + integratorap-im-pd1.dtb \ + integratorcp.dtb +dtb-$(CONFIG_ARCH_MPS2) += \ + mps2-an385.dtb \ + mps2-an399.dtb +dtb-$(CONFIG_ARCH_REALVIEW) += \ + arm-realview-pb1176.dtb \ + arm-realview-pb11mp.dtb \ + arm-realview-eb.dtb \ + arm-realview-eb-bbrevd.dtb \ + arm-realview-eb-11mp.dtb \ + arm-realview-eb-11mp-bbrevd.dtb \ + arm-realview-eb-11mp-ctrevb.dtb \ + arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ + arm-realview-eb-a9mp.dtb \ + arm-realview-eb-a9mp-bbrevd.dtb \ + arm-realview-pba8.dtb \ + arm-realview-pbx-a9.dtb +dtb-$(CONFIG_ARCH_VERSATILE) += \ + versatile-ab.dtb \ + versatile-ab-ib2.dtb \ + versatile-pb.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += \ + vexpress-v2p-ca5s.dtb \ + vexpress-v2p-ca9.dtb \ + vexpress-v2p-ca15-tc1.dtb \ + vexpress-v2p-ca15_a7.dtb diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts new file mode 100644 index 000000000000..e18769df9fd9 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp-ctrevb.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/* + * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and + * the Rev B core tile. + */ +/ { + model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts new file mode 100644 index 000000000000..26b1c69e9f43 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts new file mode 100644 index 000000000000..e68527b0d552 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts @@ -0,0 +1,93 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp.dts" + +/ { + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; +}; + +/* + * The revision B has a distinctly different layout of the syscon, so + * append a specific compatible-string. + */ +&syscon { + compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; +}; + +&intc { + reg = <0x10101000 0x1000>, + <0x10100100 0x100>; +}; + +&L2 { + reg = <0x10102000 0x1000>; +}; + +&scu { + reg = <0x10100000 0x100>; +}; + +&twd_timer { + reg = <0x10100600 0x20>; +}; + +&twd_wdog { + reg = <0x10100620 0x20>; +}; + +/* + * On revision B, we cannot reach the secondary interrupt + * controller, as a result, some peripherals that are dependent + * on their IRQ cannot be reached, so disable them. + */ +&intc_second { + status = "disabled"; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&serial2 { + status = "disabled"; +}; + +&serial3 { + status = "disabled"; +}; + +&ssp { + status = "disabled"; +}; + +&wdog { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts new file mode 100644 index 000000000000..aac1edd4b227 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts @@ -0,0 +1,74 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-eb-mp.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; + arm,hbi = <0x146>; + + /* + * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB. + * Reference: ARM DUI 0318F + * + * To run this machine with QEMU, specify the following: + * qemu-system-arm -M realview-eb-mpcore -smp cpus=4 + */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + MP11_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <0>; + next-level-cache = <&L2>; + }; + + MP11_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <1>; + next-level-cache = <&L2>; + }; + + MP11_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <2>; + next-level-cache = <&L2>; + }; + + MP11_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; +}; + +&pmu { + interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts new file mode 100644 index 000000000000..42efac7496ef --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-a9mp.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts new file mode 100644 index 000000000000..967684b3636c --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-eb-mp.dtsi" + +/ { + model = "ARM RealView EB Cortex A9 MPCore"; + + /* + * This is the Cortex A9 MPCore tile used with the + * RealView EB. + */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + A9_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + A9_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + A9_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + A9_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; +}; + +&pmu { + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts new file mode 100644 index 000000000000..f533c8b49d97 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* This derives from the Realview Baseboard, and overlays the new ethernet */ +#include "arm-realview-eb.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard Rev D"; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi new file mode 100644 index 000000000000..a79e1d1d30a7 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/ { + /* Introduce a fixed regulator for the new ethernet controller */ + veth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +/* + * The revision D has a different ethernet controller that the elder boards: + * the older board uses LAN91C111 but the new one uses LAN9118. + */ +ðernet { + compatible = "smsc,lan9118", "smsc,lan9115"; + phy-mode = "mii"; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi new file mode 100644 index 000000000000..26783d053ac7 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi @@ -0,0 +1,220 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include "arm-realview-eb.dtsi" + +/* + * This is the common include file for all MPCore variants of the + * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B + * and Cortex-A9 MPCore. + */ +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-eb-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + /* Primary interrupt controller in the test chip */ + intc: interrupt-controller@1f000100 { + compatible = "arm,eb11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1f001000 0x1000>, + <0x1f000100 0x100>; + }; + + /* Secondary interrupt controller on the FPGA */ + intc_second: interrupt-controller@10040000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + L2: cache-controller { + compatible = "arm,l220-cache"; + reg = <0x1f002000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s), probably for safety + * since th outer sync operation can cause the + * cache to hang unless disabled. + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,shared-override; + arm,parity-enable; + arm,outer-sync-disable; + }; + + scu: scu@1f000000 { + compatible = "arm,arm11mp-scu"; + reg = <0x1f000000 0x100>; + }; + + twd_timer: timer@1f000600 { + compatible = "arm,arm11mp-twd-timer"; + reg = <0x1f000600 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 13 0xf04>; + }; + + twd_wdog: watchdog@1f000620 { + compatible = "arm,arm11mp-twd-wdt"; + reg = <0x1f000620 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 14 0xf04>; + }; + + /* PMU with one IRQ line per core */ + pmu: pmu@0 { + compatible = "arm,arm11mpcore-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; + +/* + * This adapts all the peripherals to the interrupt routing + * to the GIC on the core tile. + */ + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +/* + * On revision A, these peripherals does not have their IRQ lines + * routed to the core tile, but they can be reached on the secondary + * GIC. + */ +&gpio0 { + interrupt-parent = <&intc_second>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc_second>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc_second>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc_second>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&serial3 { + interrupt-parent = <&intc_second>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&ssp { + interrupt-parent = <&intc_second>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&wdog { + interrupt-parent = <&intc_second>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dts b/arch/arm/boot/dts/arm/arm-realview-eb.dts new file mode 100644 index 000000000000..15431077f00c --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dts @@ -0,0 +1,166 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "arm-realview-eb.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard"; + compatible = "arm,realview-eb"; + arm,hbi = <0x140>; + + /* + * This is the core tile with the CPU and GIC etc for the + * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache + * or PMU. + * + * To run this machine with QEMU, specify the following: + * qemu-system-arm -M realview-eb + * Unless specified, QEMU will emulate an ARM926EJ-S core tile. + * Switches -cpu arm1136 or -cpu arm1176 emulates the other + * core tiles. + */ + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-eb-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + intc: interrupt-controller@10040000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + }; + }; +}; + +/* + * This adapts all the peripherals to the interrupt routing + * to the GIC on the core tile. + */ + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&charlcd { + interrupt-parent = <&intc>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi new file mode 100644 index 000000000000..fbb2258b451f --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi @@ -0,0 +1,484 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-eb"; + + chosen { }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c; + }; + + memory { + device_type = "memory"; + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + wdogclk: wdogclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash0@40000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x40000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + flash1@44000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x44000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + /* SMSC LAN91C111 ethernet with PHY and EEPROM */ + ethernet: ethernet@4e000000 { + compatible = "smsc,lan91c111"; + reg = <0x4e000000 0x10000>; + /* + * This means the adapter can be accessed with 8, 16 or + * 32 bit reads/writes. + */ + reg-io-width = <7>; + }; + + usb: usb@4f000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x4f000000 0x20000>; + dr_mode = "peripheral"; + }; + + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + /* These peripherals are inside the FPGA */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@8,3 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@8,4 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@8,5 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@8,6 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@8,7 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + oscclk0: clock-controller@c { + compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: clock-controller@10 { + compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: clock-controller@14 { + compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: clock-controller@18 { + compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: clock-controller@1c { + compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + }; + + i2c: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + mmc: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + charlcd: fpga_charlcd: charlcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + serial0: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@1000a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000a000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial2: serial@1000b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000b000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial3: serial@1000c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000c000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp: spi@1000d000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1000d000 0x1000>; + clocks = <&sspclk>, <&pclk>; + clock-names = "sspclk", "apb_pclk"; + }; + + wdog: watchdog@10010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x10010000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; + }; + + timer01: timer@10011000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10011000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer23: timer@10012000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10012000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + gpio0: gpio@10013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10013000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + clcd: clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + clocks = <&oscclk0>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts new file mode 100644 index 000000000000..efed325af88d --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -0,0 +1,608 @@ +/* + * Copyright 2014 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "ARM RealView PB1176"; + compatible = "arm,realview-pb1176"; + + chosen { }; + + aliases { + serial0 = &pb1176_serial0; + serial1 = &pb1176_serial1; + serial2 = &pb1176_serial2; + serial3 = &pb1176_serial3; + serial4 = &fpga_serial; + }; + + memory { + device_type = "memory"; + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + veth: regulator-veth { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash@30000000 { + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x30000000 0x4000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + fpga_flash@38000000 { + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x38000000 0x800000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + /* + * The "secure flash" contains things like the boot + * monitor so we don't want people to accidentally + * screw this up. Mark the device tree node disabled + * by default. + */ + secflash@3c000000 { + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x3c000000 0x4000000>; + bank-width = <4>; + status = "disabled"; + }; + + /* SMSC 9118 ethernet with PHY and EEPROM */ + ethernet@3a000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x3a000000 0x10000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; + }; + + usb@3b000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x3b000000 0x20000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "peripheral"; + }; + + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pb1176-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@8,3 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@8,4 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@8,5 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@8,6 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@8,7 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + oscclk0: clock-controller@c { + compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: clock-controller@10 { + compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: clock-controller@14 { + compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: clock-controller@18 { + compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: clock-controller@1c { + compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + }; + + /* Primary DevChip GIC synthesized with the CPU */ + intc_dc1176: interrupt-controller@10120000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10121000 0x1000>, + <0x10120000 0x100>; + }; + + L2: cache-controller { + compatible = "arm,l220-cache"; + reg = <0x10110000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s). + */ + arm,override-auxreg; + cache-size = <131072>; // 128kB + cache-sets = <512>; + cache-line-size = <32>; + }; + + pmu { + compatible = "arm,arm1176-pmu"; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer01: timer@10104000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10104000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer23: timer@10105000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10105000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + arm,sp804-has-irq = <1>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + pb1176_rtc: rtc@10108000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10108000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pb1176_gpio0: gpio@1010a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1010a000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pb1176_ssp: spi@1010b000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1010b000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sspclk>, <&pclk>; + clock-names = "sspclk", "apb_pclk"; + }; + + pb1176_serial0: serial@1010c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010c000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial1: serial@1010d000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010d000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial2: serial@1010e000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010e000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial3: serial@1010f000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010f000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + /* Direct-mapped development chip ROM */ + pb1176_rom@10200000 { + compatible = "direct-mapped"; + reg = <0x10200000 0x4000>; + bank-width = <1>; + }; + + clcd@10112000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10112000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupt-names = "combined"; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&oscclk0>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; + + /* These peripherals are inside the FPGA rather than the DevChip */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + i2c0: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + fpga_aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_mci: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>; + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + fpga_kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + fpga_kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + fpga_charlcd: charlcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_serial: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + /* This GIC on the board is cascaded off the DevChip GIC */ + intc_fpga1176: interrupt-controller@10040000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + }; + + fpga_gpio0: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_gpio1: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts new file mode 100644 index 000000000000..89103d54ecc1 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts @@ -0,0 +1,736 @@ +/* + * Copyright 2015 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "ARM RealView PB11MPcore"; + compatible = "arm,realview-pb11mp"; + + chosen { }; + + aliases { + serial0 = &pb11mp_serial0; + serial1 = &pb11mp_serial1; + serial2 = &pb11mp_serial2; + serial3 = &pb11mp_serial3; + }; + + memory { + device_type = "memory"; + /* + * The PB11MPCore has 512 MiB memory @ 0x70000000 + * and the first 256 are also remapped @ 0x00000000 + */ + reg = <0x70000000 0x20000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + MP11_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <0>; + next-level-cache = <&L2>; + }; + + MP11_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <1>; + next-level-cache = <&L2>; + }; + + MP11_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <2>; + next-level-cache = <&L2>; + }; + + MP11_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + /* Primary TestChip GIC synthesized with the CPU */ + intc_tc11mp: interrupt-controller@1f000100 { + compatible = "arm,tc11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1f001000 0x1000>, + <0x1f000100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,l220-cache"; + reg = <0x1f002000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s), probably for safety + * since th outer sync operation can cause the + * cache to hang unless disabled. + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,shared-override; + arm,parity-enable; + arm,outer-sync-disable; + }; + + scu@1f000000 { + compatible = "arm,arm11mp-scu"; + reg = <0x1f000000 0x100>; + }; + + timer@1f000600 { + compatible = "arm,arm11mp-twd-timer"; + reg = <0x1f000600 0x20>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1f000620 { + compatible = "arm,arm11mp-twd-wdt"; + reg = <0x1f000620 0x20>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <1 14 0xf04>; + }; + + /* PMU with one IRQ line per core */ + pmu { + compatible = "arm,arm11mpcore-pmu"; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + veth: regulator-veth { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + wdogclk: wdogclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash0@40000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x40000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + flash1@44000000 { + // 2 * 32MiB NOR Flash memory + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x44000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + /* + * This DDC I2C is connected directly to the DVI portions + * of the connector, so it's not really working when the + * monitor is connected to the VGA connector. + */ + compatible = "vga-connector"; + ddc-i2c-bus = <&i2c1>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pb11mp-soc", "simple-bus"; + regmap = <&pb11mp_syscon>; + ranges; + + pb11mp_syscon: syscon@10000000 { + compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@8,3 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + linux,default-trigger = "cpu1"; + default-state = "off"; + }; + led@8,4 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + linux,default-trigger = "cpu2"; + default-state = "off"; + }; + led@8,5 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + linux,default-trigger = "cpu3"; + default-state = "off"; + }; + led@8,6 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@8,7 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + + oscclk0: clock-controller@c { + compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: clock-controller@10 { + compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: clock-controller@14 { + compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: clock-controller@18 { + compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: clock-controller@1c { + compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + oscclk5: clock-controller@d4 { + compatible = "arm,syscon-icst307"; + reg = <0xd4 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0xd4>; + clocks = <&xtal24mhz>; + }; + oscclk6: clock-controller@d8 { + compatible = "arm,syscon-icst307"; + reg = <0xd8 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0xd8>; + clocks = <&xtal24mhz>; + }; + }; + + sp810_syscon: sysctl@10001000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x10001000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk0", + "timerclk1", + "timerclk2", + "timerclk3"; + assigned-clocks = <&sp810_syscon 0>, + <&sp810_syscon 1>, + <&sp810_syscon 2>, + <&sp810_syscon 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + + i2c0: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + mci: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>; + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + + kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + pb11mp_serial0: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb11mp_serial1: serial@1000a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000a000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb11mp_serial2: serial@1000b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000b000 0x1000>; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb11mp_serial3: serial@1000c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000c000 0x1000>; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + spi@1000d000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1000d000 0x1000>; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sspclk>, <&pclk>; + clock-names = "sspclk", "apb_pclk"; + }; + + watchdog@1000f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x1000f000 0x1000>; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; + }; + + watchdog@10010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x10010000 0x1000>; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + timer01: timer@10011000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10011000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; + arm,sp804-has-irq = <1>; + clocks = <&sp810_syscon 0>, + <&sp810_syscon 1>, + <&pclk>; + clock-names = "timer0clk", + "timer1clk", + "apb_pclk"; + }; + + timer23: timer@10012000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10012000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; + arm,sp804-has-irq = <1>; + clocks = <&sp810_syscon 2>, + <&sp810_syscon 3>, + <&pclk>; + clock-names = "timer0clk", + "timer1clk", + "apb_pclk"; + }; + + gpio0: gpio@10013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10013000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_pb11mp>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + i2c1: i2c@10016000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10016000 0x1000>; + }; + + rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + timer45: timer@10018000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10018000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + timer67: timer@10019000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10019000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-parent = <&intc_pb11mp>; + interrupt-names = "combined"; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&oscclk4>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + /* + * This GIC on the Platform Baseboard is cascaded off the + * TestChip GIC + */ + intc_pb11mp: interrupt-controller@1e000000 { + compatible = "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000000 0x100>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* SMSC 9118 ethernet with PHY and EEPROM */ + ethernet@4e000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x4e000000 0x10000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; + }; + + usb@4f000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x4f000000 0x20000>; + interrupt-parent = <&intc_tc11mp>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "peripheral"; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-pba8.dts b/arch/arm/boot/dts/arm/arm-realview-pba8.dts new file mode 100644 index 000000000000..d3238c252b59 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-pba8.dts @@ -0,0 +1,178 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-pbx.dtsi" + +/ { + model = "ARM RealView Platform Baseboard for Cortex-A8"; + compatible = "arm,realview-pba8"; + arm,hbi = <0x178>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0>; + }; + }; + + pmu: pmu@0 { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + /* Primary GIC PL390 interrupt controller in the test chip */ + intc: interrupt-controller@1e000000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000000 0x100>; + }; +}; + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&soc { + compatible = "arm,realview-pba8-soc", "simple-bus"; +}; + +&syscon { + compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog0 { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog1 { + interrupt-parent = <&intc>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer45 { + interrupt-parent = <&intc>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer67 { + interrupt-parent = <&intc>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts new file mode 100644 index 000000000000..85d3968fbb91 --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts @@ -0,0 +1,228 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-pbx.dtsi" + +/ { + /* + * This is the RealView Platform Baseboard Explore for Cortex-A9 + * (HBI0182 + HBI0183) as described in ARM DUI 0440B + */ + model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; + arm,hbi = <0x182>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x1>; + next-level-cache = <&L2>; + }; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0x1f002000 0x1000>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s). + */ + cache-size = <131072>; // 128KB + cache-sets = <512>; + cache-line-size = <32>; + arm,parity-disable; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + }; + + scu: scu@1f000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1f000000 0x100>; + }; + + twd_timer: timer@1f000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1f000600 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 13 0xf04>; + }; + + twd_wdog: watchdog@1f000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1f000620 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 14 0xf04>; + }; + + pmu: pmu@0 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, + <0 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU0>, <&CPU1>; + }; + + /* Primary GIC PL390 interrupt controller in the test chip */ + intc: interrupt-controller@1f000000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1f001000 0x1000>, + <0x1f000100 0x100>; + }; +}; + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog0 { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog1 { + interrupt-parent = <&intc>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer45 { + interrupt-parent = <&intc>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer67 { + interrupt-parent = <&intc>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi new file mode 100644 index 000000000000..ec1507c5147c --- /dev/null +++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi @@ -0,0 +1,593 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pbx"; + + chosen { }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + memory { + device_type = "memory"; + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + veth: regulator-veth { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + refclk32khz: refclk32khz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + wdogclk: wdogclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash0@40000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x40000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + flash1@44000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x44000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + /* SMSC 9118 ethernet with PHY and EEPROM */ + ethernet: ethernet@4e000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x4e000000 0x10000>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; + }; + + usb: usb@4f000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x4f000000 0x20000>; + dr_mode = "peripheral"; + }; + + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + /* + * This DDC I2C is connected directly to the DVI portions + * of the connector, so it's not really working when the + * monitor is connected to the VGA connector. + */ + compatible = "vga-connector"; + ddc-i2c-bus = <&i2c1>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + soc: soc { + compatible = "arm,realview-pbx-soc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + regmap = <&syscon>; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@8,3 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@8,4 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@8,5 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@8,6 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@8,7 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + oscclk0: clock-controller@c { + compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: clock-controller@10 { + compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: clock-controller@14 { + compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: clock-controller@18 { + compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: clock-controller@1c { + compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + }; + + sp810_syscon0: sysctl@10001000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x10001000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk0", + "timerclk1", + "timerclk2", + "timerclk3"; + assigned-clocks = <&sp810_syscon0 0>, + <&sp810_syscon0 1>, + <&sp810_syscon0 2>, + <&sp810_syscon0 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + + i2c0: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + serial0: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@1000a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000a000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial2: serial@1000b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000b000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp: spi@1000d000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1000d000 0x1000>; + clocks = <&sspclk>, <&pclk>; + clock-names = "sspclk", "apb_pclk"; + }; + + wdog0: watchdog@1000f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x1000f000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; + }; + + wdog1: watchdog@10010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x10010000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; + }; + + timer01: timer@10011000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10011000 0x1000>; + clocks = <&sp810_syscon0 0>, + <&sp810_syscon0 1>, + <&pclk>; + clock-names = "timerclk0", + "timerclk1", + "apb_pclk"; + }; + + timer23: timer@10012000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10012000 0x1000>; + clocks = <&sp810_syscon0 2>, + <&sp810_syscon0 3>, + <&pclk>; + clock-names = "timerclk2", + "timerclk3", + "apb_pclk"; + }; + + gpio0: gpio@10013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10013000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + i2c1: i2c@10016000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10016000 0x1000>; + }; + + rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + timer45: timer@10018000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10018000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timerclk4", "timerclk5", "apb_pclk"; + }; + + timer67: timer@10019000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10019000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timerclk6", "timerclk7", "apb_pclk"; + }; + + sp810_syscon1: sysctl@1001a000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x1001a000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk4", + "timerclk5", + "timerclk6", + "timerclk7"; + assigned-clocks = <&sp810_syscon1 0>, + <&sp810_syscon1 1>, + <&sp810_syscon1 2>, + <&sp810_syscon1 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + }; + + + /* These peripherals are inside the FPGA */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + mmc: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + + kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + serial3: serial@1000c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000c000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + }; + + /* These peripherals are inside the NEC ISSP */ + issp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + clcd: clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + clocks = <&oscclk4>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/integrator.dtsi b/arch/arm/boot/dts/arm/integrator.dtsi new file mode 100644 index 000000000000..7f1c8ee9dd8a --- /dev/null +++ b/arch/arm/boot/dts/arm/integrator.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SoC core Device Tree for the ARM Integrator platforms + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + core-module@10000000 { + compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; + reg = <0x10000000 0x200>; + ranges = <0x0 0x10000000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + + /* Use core module LED to indicate CPU load */ + led@c,0 { + compatible = "register-bit-led"; + reg = <0x0c 0x04>; + offset = <0x0c>; + mask = <0x01>; + label = "integrator:core_module"; + linux,default-trigger = "cpu0"; + default-state = "on"; + }; + }; + + ebi@12000000 { + compatible = "arm,external-bus-interface"; + reg = <0x12000000 0x100>; + }; + + timer@13000000 { + reg = <0x13000000 0x100>; + interrupt-parent = <&pic>; + interrupts = <5>; + }; + + timer@13000100 { + reg = <0x13000100 0x100>; + interrupt-parent = <&pic>; + interrupts = <6>; + }; + + timer@13000200 { + reg = <0x13000200 0x100>; + interrupt-parent = <&pic>; + interrupts = <7>; + }; + + pic@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + }; + + flash@24000000 { + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x24000000 0x02000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&pic>; + + /* + * These PrimeCells are in the same locations and using the + * same interrupts in all Integrators, however the silicon + * version deployed is different. + */ + rtc@15000000 { + reg = <0x15000000 0x1000>; + interrupts = <8>; + }; + + serial@16000000 { + reg = <0x16000000 0x1000>; + interrupts = <1>; + }; + + serial@17000000 { + reg = <0x17000000 0x1000>; + interrupts = <2>; + }; + + kmi@18000000 { + reg = <0x18000000 0x1000>; + interrupts = <3>; + }; + + kmi@19000000 { + reg = <0x19000000 0x1000>; + interrupts = <4>; + }; + + syscon@1a000000 { + /* Debug registers mapped as syscon */ + compatible = "syscon", "simple-mfd"; + reg = <0x1a000000 0x10>; + ranges = <0x0 0x1a000000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + + led@4,0 { + compatible = "register-bit-led"; + reg = <0x04 0x04>; + offset = <0x04>; + mask = <0x01>; + label = "integrator:green0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@4,1 { + compatible = "register-bit-led"; + reg = <0x04 0x04>; + offset = <0x04>; + mask = <0x02>; + label = "integrator:yellow"; + default-state = "off"; + }; + led@4,2 { + compatible = "register-bit-led"; + reg = <0x04 0x04>; + offset = <0x04>; + mask = <0x04>; + label = "integrator:red"; + default-state = "off"; + }; + led@4,3 { + compatible = "register-bit-led"; + reg = <0x04 0x04>; + offset = <0x04>; + mask = <0x08>; + label = "integrator:green1"; + default-state = "off"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts new file mode 100644 index 000000000000..7072a70da00d --- /dev/null +++ b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ARM Integrator/AP platform + * with the IM-PD1 example logical module mounted. + */ + +#include "integratorap.dts" + +/ { + model = "ARM Integrator/AP with IM-PD1"; + compatible = "arm,integrator-ap"; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + impd1_ram: vram@c2000000 { + /* 1 MB of designated video RAM on the IM-PD1 */ + compatible = "shared-dma-pool"; + reg = <0xc2000000 0x00100000>; + no-map; + }; + }; +}; + +&lm0 { + syscon@0 { + compatible = "arm,im-pd1-syscon", "syscon"; + reg = <0x00000000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + vco1: clock-controller@0 { + compatible = "arm,impd1-vco1"; + reg = <0x00 0x04>; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + + vco2: clock-controller@4 { + compatible = "arm,impd1-vco2"; + reg = <0x04 0x04>; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x04>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO2"; + }; + }; + + /* Also used for the Smart Card Interface SCI */ + impd1_uartclk: clock@1_4 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV4"; + }; + + /* For the SSP the clock is divided by 64 */ + impd1_sspclk: clock@1_64 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <64>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV64"; + }; + + /* Fixed regulator for the MMC */ + impd1_3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Push buttons on the IM-PD1 */ + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + debounce-interval = <50>; + linux,code = ; + label = "UP"; + gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; + }; + button@1 { + debounce-interval = <50>; + linux,code = ; + label = "DOWN"; + gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce-interval = <50>; + linux,code = ; + label = "LEFT"; + gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce-interval = <50>; + linux,code = ; + label = "UP"; + gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce-interval = <50>; + linux,code = ; + label = "ESC"; + gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; + }; + button@5 { + debounce-interval = <50>; + linux,code = ; + label = "ENTER"; + gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; + }; + }; + + + bridge { + compatible = "ti,ths8134b", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + serial@100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00100000 0x1000>; + interrupts-extended = <&impd1_vic 1>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial@200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00200000 0x1000>; + interrupts-extended = <&impd1_vic 2>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + spi@300000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00300000 0x1000>; + interrupts-extended = <&impd1_vic 3>; + clocks = <&impd1_sspclk>, <&sysclk>; + clock-names = "sspclk", "apb_pclk"; + }; + + impd1_gpio0: gpio@400000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00400000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 4>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + impd1_gpio1: gpio@500000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00500000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 5>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + rtc@600000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x00600000 0x1000>; + interrupts-extended = <&impd1_vic 6>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + mmc@700000 { + compatible = "arm,pl181", "arm,primecell"; + reg = <0x00700000 0x1000>; + interrupts-extended = <&impd1_vic 7>, + <&impd1_vic 8>; + clocks = <&sysclk>, <&sysclk>; + clock-names = "mclk", "apb_pclk"; + bus-width = <1>; + max-frequency = <515633>; + vmmc-supply = <&impd1_3v3>; + wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; + cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; + }; + + aaci@800000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x00800000 0x1000>; + interrupts-extended = <&impd1_vic 9>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + display@1000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x01000000 0x1000>; + interrupts-extended = <&impd1_vic 11>; + clocks = <&vco1>, <&sysclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; + memory-region = <&impd1_ram>; + dma-ranges; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + clcd_pads_vga_dac: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + impd1_vic: interrupt-controller@3000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x03000000 0x1000>; + /* Valid interrupts, 0-9 and 11 */ + valid-mask = <0x00000bff>; + /* LM site 0 has IRQ 9 on the PIC */ + interrupts-extended = <&pic 9>; + }; +}; diff --git a/arch/arm/boot/dts/arm/integratorap.dts b/arch/arm/boot/dts/arm/integratorap.dts new file mode 100644 index 000000000000..5b52d75bc6be --- /dev/null +++ b/arch/arm/boot/dts/arm/integratorap.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ARM Integrator/AP platform + */ + +/dts-v1/; +#include "integrator.dtsi" +#include +#include + +/ { + model = "ARM Integrator/AP"; + compatible = "arm,integrator-ap"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm926ej-s"; */ + reg = <0>; + /* + * The documentation in ARM DUI 0138E page 3-12 states + * that the maximum frequency for this clock is 200 MHz + * but painful trial-and-error has proved to me that it + * is actually just hanging the system above 71 MHz. + * Sad but true. + */ + /* kHz uV */ + operating-points = <71000 0 + 66000 0 + 60000 0 + 48000 0 + 36000 0 + 24000 0 + 12000 0>; + clocks = <&cmosc>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + + aliases { + arm,timer-primary = &timer2; + arm,timer-secondary = &timer1; + }; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; + }; + + /* 24 MHz chrystal on the Integrator/AP development board */ + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* The UART clock is 14.74 MHz divided by an ICS525 */ + uartclk: uartclk@14.74M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <14745600>; + clocks = <&xtal24mhz>; + }; + + core-module@10000000 { + /* 24 MHz chrystal on the core module */ + cm24mhz: cm24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + /* Oscillator on the core module, clocks the CPU core */ + cmosc: clock-controller@8 { + compatible = "arm,syscon-icst525-integratorap-cm"; + reg = <0x08 0x04>; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x08>; + clocks = <&cm24mhz>; + }; + + /* Auxilary oscillator on the core module, 32.369MHz at boot */ + auxosc: clock-controller@1c { + compatible = "arm,syscon-icst525"; + reg = <0x1c 0x04>; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x1c>; + clocks = <&cm24mhz>; + }; + }; + + syscon { + compatible = "arm,integrator-ap-syscon", "syscon"; + reg = <0x11000000 0x100>; + ranges = <0x0 0x11000000 0x100>; + #size-cells = <1>; + #address-cells = <1>; + + /* + * SYSCLK clocks PCIv3 bridge, system controller and the + * logic modules. + */ + sysclk: clock-controller@4 { + compatible = "arm,syscon-icst525-integratorap-sys"; + reg = <0x04 0x04>; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; + + /* One-bit control for the PCI bus clock (33 or 25 MHz) */ + pciclk: clock-controller@4,8 { + compatible = "arm,syscon-icst525-integratorap-pci"; + reg = <0x04 0x04>; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; + }; + + timer0: timer@13000000 { + compatible = "arm,integrator-timer"; + clocks = <&xtal24mhz>; + }; + + timer1: timer@13000100 { + compatible = "arm,integrator-timer"; + clocks = <&xtal24mhz>; + }; + + timer2: timer@13000200 { + compatible = "arm,integrator-timer"; + clocks = <&xtal24mhz>; + }; + + pic: pic@14000000 { + valid-mask = <0x003fffff>; + }; + + pci: pciv3@62000000 { + compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + /* Bridge registers and config access space */ + reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + clocks = <&pciclk>; + bus-range = <0x00 0xff>; + ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ + 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ + 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ + 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ + 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ + dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ + 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ + 0x02000000 0 0x80000000 /* Core module alias memory */ + 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; + }; + + fpga { + /* + * The Integator/AP predates the idea to have magic numbers + * identifying the PrimeCell in hardware, thus we have to + * supply these from the device tree. + */ + rtc: rtc@15000000 { + compatible = "arm,pl030", "arm,primecell"; + arm,primecell-periphid = <0x00041030>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + uart0: serial@16000000 { + compatible = "arm,pl010", "arm,primecell"; + arm,primecell-periphid = <0x00041010>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@17000000 { + compatible = "arm,pl010", "arm,primecell"; + arm,primecell-periphid = <0x00041010>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + kmi0: kmi@18000000 { + compatible = "arm,pl050", "arm,primecell"; + arm,primecell-periphid = <0x00041050>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi1: kmi@19000000 { + compatible = "arm,pl050", "arm,primecell"; + arm,primecell-periphid = <0x00041050>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + }; + + /* + * Logic module bus, we support up to 4 logical modules + * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 + * and use interrupts 9, 10, 11 and 12 respectively. + */ + bus@c0000000 { + compatible = "arm,integrator-ap-lm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc0000000 0xc0000000 0x40000000>; + dma-ranges; + + lm0: bus@c0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xc0000000 0x10000000>; + dma-ranges = <0x00000000 0xc0000000 0x10000000>; + reg = <0xc0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm1: bus@d0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xd0000000 0x10000000>; + dma-ranges = <0x00000000 0xd0000000 0x10000000>; + reg = <0xd0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm2: bus@e0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xe0000000 0x10000000>; + dma-ranges = <0x00000000 0xe0000000 0x10000000>; + reg = <0xe0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm3: bus@f0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + dma-ranges = <0x00000000 0xf0000000 0x10000000>; + reg = <0xf0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/integratorcp.dts b/arch/arm/boot/dts/arm/integratorcp.dts new file mode 100644 index 000000000000..c011333eb165 --- /dev/null +++ b/arch/arm/boot/dts/arm/integratorcp.dts @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ARM Integrator/CP platform + */ + +/dts-v1/; +/include/ "integrator.dtsi" + +/ { + model = "ARM Integrator/CP"; + compatible = "arm,integrator-cp"; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm920t"; */ + reg = <0>; + /* + * TBD comment. + */ + /* kHz uV */ + operating-points = <50000 0 + 48000 0>; + clocks = <&cmcore>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + + /* + * The Integrator/CP overall clocking architecture can be found in + * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which + * appear to illustrate the layout used in most configurations. + */ + + /* The codec chrystal operates at 24.576 MHz */ + xtal_codec: xtal24.576@24.576M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + /* The chrystal is divided by 2 by the codec for the AACI bit clock */ + aaci_bitclk: aaci_bitclk@12.288M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&xtal_codec>; + }; + + /* This is a 25MHz chrystal on the base board */ + xtal25mhz: xtal25mhz@25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ + uartclk: uartclk@14.74M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <14745600>; + }; + + /* Actually sysclk I think */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + core-module@10000000 { + /* 24 MHz chrystal on the core module */ + cm24mhz: cm24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + /* Oscillator on the core module, clocks the CPU core */ + cmcore: clock-controller@8 { + compatible = "arm,syscon-icst525-integratorcp-cm-core"; + reg = <0x08 0x04>; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x08>; + clocks = <&cm24mhz>; + }; + + /* Oscillator on the core module, clocks the memory bus */ + cmmem: clock-controller@8,12 { + compatible = "arm,syscon-icst525-integratorcp-cm-mem"; + reg = <0x08 0x04>; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x08>; + clocks = <&cm24mhz>; + }; + + /* Auxilary oscillator on the core module, clocks the CLCD */ + auxosc: clock-controller@1c { + compatible = "arm,syscon-icst525"; + reg = <0x1c 0x04>; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x1c>; + clocks = <&cm24mhz>; + }; + + /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ + kmiclk: kmiclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <3>; + clock-mult = <1>; + clocks = <&cm24mhz>; + }; + + /* The timer clock is the 24 MHz oscillator divided to 1MHz */ + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&cm24mhz>; + }; + }; + + syscon { + compatible = "arm,integrator-cp-syscon", "syscon"; + reg = <0xcb000000 0x100>; + }; + + timer0: timer@13000000 { + /* TIMER0 runs directly on the 25MHz chrystal */ + compatible = "arm,integrator-cp-timer"; + clocks = <&xtal25mhz>; + }; + + timer1: timer@13000100 { + /* TIMER1 runs @ 1MHz */ + compatible = "arm,integrator-cp-timer"; + clocks = <&timclk>; + }; + + timer2: timer@13000200 { + /* TIMER2 runs @ 1MHz */ + compatible = "arm,integrator-cp-timer"; + clocks = <&timclk>; + }; + + pic: pic@14000000 { + valid-mask = <0x1fc003ff>; + }; + + cic: cic@10000040 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x10000040 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x00000007>; + }; + + /* The SIC is cascaded off IRQ 26 on the PIC */ + sic: sic@ca000000 { + compatible = "arm,versatile-fpga-irq"; + interrupt-parent = <&pic>; + interrupts = <26>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xca000000 0x100>; + clear-mask = <0x00000fff>; + valid-mask = <0x00000fff>; + }; + + ethernet@c8000000 { + compatible = "smsc,lan91c111"; + reg = <0xc8000000 0x10>; + interrupt-parent = <&pic>; + interrupts = <27>; + }; + + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + fpga { + /* + * These PrimeCells are at the same location and using + * the same interrupts in all Integrators, but in the CP + * slightly newer versions are deployed. + */ + rtc@15000000 { + compatible = "arm,pl031", "arm,primecell"; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + serial@16000000 { + compatible = "arm,pl011", "arm,primecell"; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial@17000000 { + compatible = "arm,pl011", "arm,primecell"; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + kmi@18000000 { + compatible = "arm,pl050", "arm,primecell"; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@19000000 { + compatible = "arm,pl050", "arm,primecell"; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + /* + * These PrimeCells are only available on the Integrator/CP + */ + mmc@1c000000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x1c000000 0x1000>; + interrupts = <23 24>; + max-frequency = <515633>; + clocks = <&uartclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + }; + + aaci@1d000000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x1d000000 0x1000>; + interrupts = <25>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + clcd@c0000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0xC0000000 0x1000>; + interrupts = <22>; + clocks = <&auxosc>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; + + /* + * This port is routed through a PLD (Programmable + * Logic Device) that routes the output from the CLCD + * (after transformations) to the VGA DAC and also an + * external panel connector. The PLD is essential for + * supporting RGB565/BGR565. + * + * The signals from the port thus reaches two endpoints. + * The PLD is managed through a few special bits in the + * FPGA "sysreg". + * + * This arrangement can be clearly seen in + * ARM DUI 0225D, page 3-41, figure 3-19. + */ + port@0 { + clcd_pads_vga_dac: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/mps2-an385.dts b/arch/arm/boot/dts/arm/mps2-an385.dts new file mode 100644 index 000000000000..aebbebfc25d1 --- /dev/null +++ b/arch/arm/boot/dts/arm/mps2-an385.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "mps2.dtsi" + +/ { + model = "ARM MPS2 Application Note 385/386"; + compatible = "arm,mps2"; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:9600n8"; + }; + + memory@21000000 { + device_type = "memory"; + reg = <0x21000000 0x1000000>; + }; + + smb { + ethernet@0,0 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0 0x0 0x10000>; + interrupts = <13>; + interrupt-parent = <&nvic>; + smsc,irq-active-high; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/arm/mps2-an399.dts b/arch/arm/boot/dts/arm/mps2-an399.dts new file mode 100644 index 000000000000..349abf70b2a5 --- /dev/null +++ b/arch/arm/boot/dts/arm/mps2-an399.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "mps2.dtsi" + +/ { + model = "ARM MPS2 Application Note 399/400"; + compatible = "arm,mps2"; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:9600n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x1000000>; + }; + + smb { + ethernet@1,0 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <1 0x0 0x10000>; + interrupts = <13>; + interrupt-parent = <&nvic>; + smsc,irq-active-high; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/arm/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi new file mode 100644 index 000000000000..ce308820765b --- /dev/null +++ b/arch/arm/boot/dts/arm/mps2.dtsi @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "../armv7-m.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + oscclk0: clk-osc0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + oscclk1: clk-osc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + oscclk2: clk-osc2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + cfgclk: clk-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; + + spicfgclk: clk-spicfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + }; + + sysclk: clk-sys { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + audmclk: clk-audm { + compatible = "fixed-factor-clock"; + clocks = <&oscclk1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + audsclk: clk-auds { + compatible = "fixed-factor-clock"; + clocks = <&oscclk1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + + spiclcd: clk-cpiclcd { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + spicon: clk-spicon { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + i2cclcd: clk-i2cclcd { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + i2caud: clk-i2caud { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + soc { + compatible = "simple-bus"; + ranges; + + apb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x10000>; + + timer0: mps2-timer0@0 { + compatible = "arm,mps2-timer"; + reg = <0x0 0x1000>; + interrupts = <8>; + clocks = <&sysclk>; + status = "disabled"; + }; + + timer1: mps2-timer1@1000 { + compatible = "arm,mps2-timer"; + reg = <0x1000 0x1000>; + interrupts = <9>; + clocks = <&sysclk>; + status = "disabled"; + }; + + timer2: dual-timer@2000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x2000 0x1000>; + clocks = <&sysclk>, <&sysclk>, <&sysclk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; + interrupts = <10>; + status = "disabled"; + }; + + uart0: serial@4000 { + compatible = "arm,mps2-uart"; + reg = <0x4000 0x1000>; + interrupts = <0>, <1>, <12>; + clocks = <&sysclk>; + status = "disabled"; + }; + + uart1: serial@5000 { + compatible = "arm,mps2-uart"; + reg = <0x5000 0x1000>; + interrupts = <2>, <3>, <12>; + clocks = <&sysclk>; + status = "disabled"; + }; + + uart2: serial@6000 { + compatible = "arm,mps2-uart"; + reg = <0x6000 0x1000>; + interrupts = <4>, <5>, <12>; + clocks = <&sysclk>; + status = "disabled"; + }; + + wdt: watchdog@8000 { + compatible = "arm,sp805", "arm,primecell"; + arm,primecell-periphid = <0x00141805>; + reg = <0x8000 0x1000>; + interrupts = <0>; + clocks = <&sysclk>, <&sysclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; + }; + }; + }; + + fpga@40020000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x10000>; + + fpgaio@8000 { + compatible = "syscon", "simple-mfd"; + reg = <0x8000 0x10>; + + ranges = <0x0 0x8000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + + led@0,0 { + compatible = "register-bit-led"; + reg = <0x00 0x04>; + offset = <0x0>; + mask = <0x01>; + label = "userled:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@0,1 { + compatible = "register-bit-led"; + reg = <0x00 0x04>; + offset = <0x0>; + mask = <0x02>; + label = "userled:1"; + linux,default-trigger = "usr"; + default-state = "off"; + }; + }; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40200000 0x10000>, + <1 0 0xa0000000 0x10000>; + }; +}; diff --git a/arch/arm/boot/dts/arm/versatile-ab-ib2.dts b/arch/arm/boot/dts/arm/versatile-ab-ib2.dts new file mode 100644 index 000000000000..7ebb0dfd0467 --- /dev/null +++ b/arch/arm/boot/dts/arm/versatile-ab-ib2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The Versatile AB with the IB2 expansion board mounted. + * This works as a superset of the Versatile AB. + */ + +#include "versatile-ab.dts" + +/ { + model = "ARM Versatile AB + IB2 board"; + + /* Special IB2 control register */ + syscon@27000000 { + compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; + reg = <0x27000000 0x4>; + ranges = <0x0 0x27000000 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + led@0,4 { + compatible = "register-bit-led"; + reg = <0x00 0x04>; + offset = <0x00>; + mask = <0x10>; + label = "versatile-ib2:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/versatile-ab.dts b/arch/arm/boot/dts/arm/versatile-ab.dts new file mode 100644 index 000000000000..f31dcf7e5862 --- /dev/null +++ b/arch/arm/boot/dts/arm/versatile-ab.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { + model = "ARM Versatile AB"; + compatible = "arm,versatile-ab"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + bridge { + compatible = "ti,ths8134b", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + core-module@10000000 { + compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; + reg = <0x10000000 0x200>; + ranges = <0x0 0x10000000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@8,3 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@8,4 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@8,5 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@8,6 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@8,7 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + + /* OSC1 on AB, OSC4 on PB */ + osc1: cm_aux_osc@24M { + #clock-cells = <0>; + compatible = "arm,versatile-cm-auxosc"; + clocks = <&xtal24mhz>; + }; + + /* The timer clock is the 24 MHz oscillator divided to 1MHz */ + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + pclk: pclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + }; + + flash@34000000 { + /* 64 MiB NOR flash in non-interleaved chips */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x34000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + i2c0: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + net@10010000 { + compatible = "smsc,lan91c111"; + reg = <0x10010000 0x10000>; + interrupts = <25>; + }; + + lcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@10140000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10140000 0x1000>; + valid-mask = <0xffffffff>; + }; + + sic: interrupt-controller@10003000 { + compatible = "arm,versatile-sic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10003000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <31>; /* Cascaded to vic */ + clear-mask = <0xffffffff>; + /* + * Valid interrupt lines mask according to + * table 4-36 page 4-50 of ARM DUI 0225D + */ + valid-mask = <0x0760031b>; + }; + + dma@10130000 { + compatible = "arm,pl081", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupts = <17>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + uart0: serial@101f1000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f1000 0x1000>; + interrupts = <12>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@101f2000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f2000 0x1000>; + interrupts = <13>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@101f3000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f3000 0x1000>; + interrupts = <14>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + smc@10100000 { + compatible = "arm,primecell"; + reg = <0x10100000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + mpmc@10110000 { + compatible = "arm,primecell"; + reg = <0x10110000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + display@10120000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x10120000 0x1000>; + interrupts = <16>; + clocks = <&osc1>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 800x600 16bpp @ 36MHz works fine */ + max-memory-bandwidth = <54000000>; + + /* + * This port is routed through a PLD (Programmable + * Logic Device) that routes the output from the CLCD + * (after transformations) to the VGA DAC and also an + * external panel connector. The PLD is essential for + * supporting RGB565/BGR565. + * + * The signals from the port thus reaches two endpoints. + * The PLD is managed through a few special bits in the + * FPGA "sysreg". + * + * This arrangement can be clearly seen in + * ARM DUI 0225D, page 3-41, figure 3-19. + */ + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + clcd_pads_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + clcd_pads_vga_dac: endpoint@1 { + reg = <1>; + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + sctl@101e0000 { + compatible = "arm,primecell"; + reg = <0x101e0000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + watchdog@101e1000 { + compatible = "arm,primecell"; + reg = <0x101e1000 0x1000>; + interrupts = <0>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + timer@101e2000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x101e2000 0x1000>; + interrupts = <4>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0", "timer1", "apb_pclk"; + }; + + timer@101e3000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x101e3000 0x1000>; + interrupts = <5>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0", "timer1", "apb_pclk"; + }; + + gpio0: gpio@101e4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e4000 0x1000>; + gpio-controller; + interrupts = <6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@101e5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e5000 0x1000>; + interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + rtc@101e8000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x101e8000 0x1000>; + interrupts = <10>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + sci@101f0000 { + compatible = "arm,primecell"; + reg = <0x101f0000 0x1000>; + interrupts = <15>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + spi@101f4000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x101f4000 0x1000>; + interrupts = <11>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "sspclk", "apb_pclk"; + }; + + fpga { + compatible = "arm,versatile-fpga", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10000000 0x10000>; + + sysreg@0 { + compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; + reg = <0x00000 0x1000>; + + panel: display@0 { + compatible = "arm,versatile-tft-panel"; + + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads_panel>; + }; + }; + }; + }; + + aaci@4000 { + compatible = "arm,primecell"; + reg = <0x4000 0x1000>; + interrupts = <24>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + mmc@5000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x5000 0x1000>; + interrupts-extended = <&vic 22 &sic 1>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + }; + kmi@6000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x6000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <3>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + kmi@7000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x7000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <4>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/versatile-pb.dts b/arch/arm/boot/dts/arm/versatile-pb.dts new file mode 100644 index 000000000000..fc21ce54b33a --- /dev/null +++ b/arch/arm/boot/dts/arm/versatile-pb.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "versatile-ab.dts" + +/ { + model = "ARM Versatile PB"; + compatible = "arm,versatile-pb"; + + amba { + /* The Versatile PB is using more SIC IRQ lines than the AB */ + sic: interrupt-controller@10003000 { + clear-mask = <0xffffffff>; + /* + * Valid interrupt lines mask according to + * figure 3-30 page 3-74 of ARM DUI 0224B + */ + valid-mask = <0x7fe003ff>; + }; + + gpio2: gpio@101e6000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e6000 0x1000>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@101e7000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e7000 0x1000>; + interrupts = <9>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pci@10001000 { + compatible = "arm,versatile-pci"; + device_type = "pci"; + reg = <0x10001000 0x1000 + 0x41000000 0x10000 + 0x42000000 0x100000>; + bus-range = <0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ + 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ + 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ + + interrupt-map-mask = <0x1800 0 0 7>; + interrupt-map = <0x1800 0 0 1 &sic 28 + 0x1800 0 0 2 &sic 29 + 0x1800 0 0 3 &sic 30 + 0x1800 0 0 4 &sic 27 + + 0x1000 0 0 1 &sic 27 + 0x1000 0 0 2 &sic 28 + 0x1000 0 0 3 &sic 29 + 0x1000 0 0 4 &sic 30 + + 0x0800 0 0 1 &sic 30 + 0x0800 0 0 2 &sic 27 + 0x0800 0 0 3 &sic 28 + 0x0800 0 0 4 &sic 29 + + 0x0000 0 0 1 &sic 29 + 0x0000 0 0 2 &sic 30 + 0x0000 0 0 3 &sic 27 + 0x0000 0 0 4 &sic 28>; + }; + + fpga { + mmc@5000 { + /* + * Overrides the interrupt assignment from + * the Versatile AB board file. + */ + interrupts-extended = <&sic 22 &sic 23>; + }; + serial@9000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x9000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <6>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + sci@a000 { + compatible = "arm,primecell"; + reg = <0xa000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <5>; + clocks = <&xtal24mhz>; + clock-names = "apb_pclk"; + }; + mmc@b000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0xb000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <1>, <2>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi new file mode 100644 index 000000000000..8af4b77fe655 --- /dev/null +++ b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * RS1 memory map ("ARM Cortex-A Series memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * original variant (vexpress-v2m.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m.dtsi! + */ +#include + +/ { + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "disk-activity"; + }; + + led-3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + led-4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + led-5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + led-6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + led-7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + led-8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + bus@8000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 63>; + interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + + motherboard-bus@8000000 { + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + ranges = <0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>, + <3 0 0x1c000000 0x04000000>, + <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>; + + nor_flash: flash@0 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + psram@100000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <1 0x00000000 0x02000000>; + bank-width = <4>; + }; + + ethernet@202000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@203000000 { + compatible = "nxp,usb-isp1761"; + reg = <2 0x03000000 0x20000>; + interrupts = <16>; + dr_mode = "peripheral"; + }; + + iofpga-bus@300000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@10000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10000 0x1000>; + + v2m_led_gpios: gpio@8 { + compatible = "arm,vexpress-sysreg,sys_led"; + reg = <0x008 4>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: gpio@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + reg = <0x048 4>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: gpio@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + reg = <0x04c 4>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@30000 { + compatible = "arm,versatile-i2c"; + reg = <0x030000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@40000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmc@50000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9>, <10>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@60000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@70000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: serial@90000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: serial@a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: serial@b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: serial@c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + watchdog@f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@160000 { + compatible = "arm,versatile-i2c"; + reg = <0x160000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dvi_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a0000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a0000 0x100 + 0x1a0100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 800x600 16bpp @36MHz works fine */ + max-memory-bandwidth = <54000000>; + memory-region = <&vram>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&dvi_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi new file mode 100644 index 000000000000..c5e92f6d2fcd --- /dev/null +++ b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi @@ -0,0 +1,509 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ +#include + +/ { + bus@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x10000000>, + <0x10000000 0x10000000 0x00020000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 63>; + interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + + motherboard-bus@40000000 { + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + dr_mode = "peripheral"; + }; + + iofpga@7,00000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + v2m_sysreg: sysreg@0 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + v2m_led_gpios: gpio@8 { + compatible = "arm,vexpress-sysreg,sys_led"; + reg = <0x008 4>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: gpio@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + reg = <0x048 4>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: gpio@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + reg = <0x04c 4>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + v2m_sysctl: sysctl@1000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@2000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@4000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@5000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9>, <10>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@6000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@7000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: serial@9000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: serial@a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: serial@b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: serial@c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Both the core tile and the motherboard routes their output + * pads to this transmitter. The motherboard system controller + * can select one of them as input using a mux register in + * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is + * the only platform with this specific set-up. + */ + port@0 { + reg = <0>; + dvi_bridge_in_ct: endpoint { + remote-endpoint = <&clcd_pads_ct>; + }; + }; + port@1 { + reg = <1>; + dvi_bridge_in_mb: endpoint { + remote-endpoint = <&clcd_pads_mb>; + }; + }; + }; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 800x600 16bpp @36MHz works fine */ + max-memory-bandwidth = <54000000>; + memory-region = <&vram>; + + port { + clcd_pads_mb: endpoint { + remote-endpoint = <&dvi_bridge_in_mb>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; + + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + led-user1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + led-user2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + + led-user3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + led-user4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + led-user5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + led-user6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + led-user7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + led-user8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts new file mode 100644 index 000000000000..679537e17ff5 --- /dev/null +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A15x2 (version with Test Chip 1) + * Cortex-A15 MPCore (V2P-CA15) + * + * HBI-0237A + */ + +/dts-v1/; +#include "vexpress-v2m-rs1.dtsi" + +/ { + model = "V2P-CA15"; + arm,hbi = <0x237>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0 0x00800000>; + no-map; + }; + }; + + hdlcd@2b000000 { + compatible = "arm,hdlcd"; + reg = <0 0x2b000000 0 0x1000>; + interrupts = <0 85 4>; + clocks = <&hdlcd_clk>; + clock-names = "pxlclk"; + }; + + memory-controller@2b0a0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0 0x2b0a0000 0 0x1000>; + clocks = <&sys_pll>; + clock-names = "apb_pclk"; + }; + + wdt@2b060000 { + compatible = "arm,sp805", "arm,primecell"; + status = "disabled"; + reg = <0 0x2b060000 0 0x1000>; + interrupts = <0 98 4>; + clocks = <&sys_pll>, <&sys_pll>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x2000>, + <0 0x2c004000 0 0x2000>, + <0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&sys_pll>; + clock-names = "apb_pclk"; + }; + + dma@7ffb0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0 0x7ffb0000 0 0x1000>; + interrupts = <0 92 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>; + clocks = <&sys_pll>; + clock-names = "apb_pclk"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* CPU PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <50000000 60000000>; + #clock-cells = <0>; + clock-output-names = "oscclk0"; + }; + + oscclk4 { + /* Multiplexed AXI master clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 4>; + freq-range = <20000000 40000000>; + #clock-cells = <0>; + clock-output-names = "oscclk4"; + }; + + hdlcd_clk: oscclk5 { + /* HDLCD PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 5>; + freq-range = <23750000 165000000>; + #clock-cells = <0>; + clock-output-names = "oscclk5"; + }; + + smbclk: oscclk6 { + /* SMB clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 6>; + freq-range = <20000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk6"; + }; + + sys_pll: oscclk7 { + /* SYS PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 7>; + freq-range = <20000000 60000000>; + #clock-cells = <0>; + clock-output-names = "oscclk7"; + }; + + oscclk8 { + /* DDR2 PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 8>; + freq-range = <40000000 40000000>; + #clock-cells = <0>; + clock-output-names = "oscclk8"; + }; + + volt-cores { + /* CPU core voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "Cores"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + label = "Cores"; + }; + + amp-cores { + /* Total current for the two cores */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "Cores"; + }; + + temp-dcc { + /* DCC internal temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "DCC"; + }; + + power-cores { + /* Total power */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "Cores"; + }; + + energy { + /* Total energy */ + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 0>; + label = "Cores"; + }; + }; + + bus@8000000 { + ranges = <0x8000000 0 0x8000000 0x18000000>; + }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x3fef0000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts new file mode 100644 index 000000000000..511e87cc2bc5 --- /dev/null +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts @@ -0,0 +1,636 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A15x2 A7x3 + * Cortex-A15_A7 MPCore (V2P-CA15_A7) + * + * HBI-0249A + */ + +/dts-v1/; +#include "vexpress-v2m-rs1.dtsi" + +/ { + model = "V2P-CA15_CA7"; + arm,hbi = <0x249>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + cci-control-port = <&cci_control1>; + cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <990>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + cci-control-port = <&cci_control1>; + cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <990>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; + }; + + idle-states { + CLUSTER_SLEEP_BIG: cluster-sleep-big { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_LITTLE: cluster-sleep-little { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <500>; + min-residency-us = <2500>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0 0x00800000>; + no-map; + }; + }; + + wdt@2a490000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0 0x2a490000 0 0x1000>; + interrupts = <0 98 4>; + clocks = <&oscclk6a>, <&oscclk6a>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + hdlcd@2b000000 { + compatible = "arm,hdlcd"; + reg = <0 0x2b000000 0 0x1000>; + interrupts = <0 85 4>; + clocks = <&hdlcd_clk>; + clock-names = "pxlclk"; + }; + + memory-controller@2b0a0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0 0x2b0a0000 0 0x1000>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x2000>, + <0 0x2c004000 0 0x2000>, + <0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r0"; + reg = <0x9000 0x5000>; + interrupts = <0 105 4>, + <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>; + }; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + }; + + dma@7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0 0x7ff00000 0 0x1000>; + interrupts = <0 92 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + }; + + scc@7fff0000 { + compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; + reg = <0 0x7fff0000 0 0x1000>; + interrupts = <0 95 4>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + pmu-a15 { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>; + }; + + pmu-a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0 128 4>, + <0 129 4>, + <0 130 4>; + interrupt-affinity = <&cpu2>, + <&cpu3>, + <&cpu4>; + }; + + oscclk6a: oscclk6a { + /* Reference 24MHz clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "oscclk6a"; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* A15 PLL 0 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk0"; + }; + + oscclk1 { + /* A15 PLL 1 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk1"; + }; + + oscclk2 { + /* A7 PLL 0 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk2"; + }; + + oscclk3 { + /* A7 PLL 1 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 3>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk3"; + }; + + oscclk4 { + /* External AXI master clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 4>; + freq-range = <20000000 40000000>; + #clock-cells = <0>; + clock-output-names = "oscclk4"; + }; + + hdlcd_clk: oscclk5 { + /* HDLCD PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 5>; + freq-range = <23750000 165000000>; + #clock-cells = <0>; + clock-output-names = "oscclk5"; + }; + + smbclk: oscclk6 { + /* Static memory controller clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 6>; + freq-range = <20000000 40000000>; + #clock-cells = <0>; + clock-output-names = "oscclk6"; + }; + + oscclk7 { + /* SYS PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 7>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk7"; + }; + + oscclk8 { + /* DDR2 PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 8>; + freq-range = <20000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk8"; + }; + + volt-a15 { + /* A15 CPU core voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "A15 Vcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + label = "A15 Vcore"; + }; + + volt-a7 { + /* A7 CPU core voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "A7 Vcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + label = "A7 Vcore"; + }; + + amp-a15 { + /* Total current for the two A15 cores */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "A15 Icore"; + }; + + amp-a7 { + /* Total current for the three A7 cores */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "A7 Icore"; + }; + + temp-dcc { + /* DCC internal temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "DCC"; + }; + + power-a15 { + /* Total power for the two A15 cores */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "A15 Pcore"; + }; + + power-a7 { + /* Total power for the three A7 cores */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "A7 Pcore"; + }; + + energy-a15 { + /* Total energy for the two A15 cores */ + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 0>, <13 1>; + label = "A15 Jcore"; + }; + + energy-a7 { + /* Total energy for the three A7 cores */ + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 2>, <13 3>; + label = "A7 Jcore"; + }; + }; + + etb@20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + replicator { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; + + funnel@20040000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel_out_port0: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* Input port #3 is for ITM, not supported here */ + + port@4 { + reg = <4>; + funnel_in_port4: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@5 { + reg = <5>; + funnel_in_port5: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + }; + }; + + ptm@2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201c000 0 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201d000 0 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + + etm@2203c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203c000 0 0x1000>; + + cpu = <&cpu2>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; + }; + }; + }; + + etm@2203d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203d000 0 0x1000>; + + cpu = <&cpu3>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port4>; + }; + }; + }; + }; + + etm@2203e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203e000 0 0x1000>; + + cpu = <&cpu4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel_in_port5>; + }; + }; + }; + }; + + smb: bus@8000000 { + ranges = <0x8000000 0 0x8000000 0x18000000>; + }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x3fef0000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; + +&nor_flash { + /* + * Unfortunately, accessing the flash disturbs the CPU idle states + * (suspend) and CPU hotplug of this platform. For this reason, flash + * hardware access is disabled by default on this platform alone. + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts new file mode 100644 index 000000000000..3b88209bacea --- /dev/null +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A5x2 + * Cortex-A5 MPCore (V2P-CA5s) + * + * HBI-0225B + */ + +/dts-v1/; +#include "vexpress-v2m-rs1.dtsi" + +/ { + model = "V2P-CA5s"; + arm,hbi = <0x225>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x18000000 0x00800000>; + no-map; + }; + }; + + hdlcd@2a110000 { + compatible = "arm,hdlcd"; + reg = <0x2a110000 0x1000>; + interrupts = <0 85 4>; + clocks = <&hdlcd_clk>; + clock-names = "pxlclk"; + }; + + memory-controller@2a150000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x2a150000 0x1000>; + clocks = <&axi_clk>; + clock-names = "apb_pclk"; + }; + + memory-controller@2a190000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x2a190000 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&axi_clk>; + clock-names = "apb_pclk"; + }; + + scu@2c000000 { + compatible = "arm,cortex-a5-scu"; + reg = <0x2c000000 0x58>; + }; + + timer@2c000600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0x2c000600 0x20>; + interrupts = <1 13 0x304>; + }; + + timer@2c000200 { + compatible = "arm,cortex-a5-global-timer", + "arm,cortex-a9-global-timer"; + reg = <0x2c000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&cpu_clk>; + }; + + watchdog@2c000620 { + compatible = "arm,cortex-a5-twd-wdt"; + reg = <0x2c000620 0x20>; + interrupts = <1 14 0x304>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c000100 0x100>; + }; + + L2: cache-controller@2c0f0000 { + compatible = "arm,pl310-cache"; + reg = <0x2c0f0000 0x1000>; + interrupts = <0 84 4>; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + cpu_clk: oscclk0 { + /* CPU and internal AXI reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <50000000 100000000>; + #clock-cells = <0>; + clock-output-names = "oscclk0"; + }; + + axi_clk: oscclk1 { + /* Multiplexed AXI master clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <5000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk1"; + }; + + oscclk2 { + /* DDR2 */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <80000000 120000000>; + #clock-cells = <0>; + clock-output-names = "oscclk2"; + }; + + hdlcd_clk: oscclk3 { + /* HDLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 3>; + freq-range = <23750000 165000000>; + #clock-cells = <0>; + clock-output-names = "oscclk3"; + }; + + oscclk4 { + /* Test chip gate configuration */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 4>; + freq-range = <80000000 80000000>; + #clock-cells = <0>; + clock-output-names = "oscclk4"; + }; + + smbclk: oscclk5 { + /* SMB clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 5>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "oscclk5"; + }; + + temp-dcc { + /* DCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "DCC"; + }; + }; + + smb: bus@8000000 { + ranges = <0 0x8000000 0x18000000>; + }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts new file mode 100644 index 000000000000..5916e4877eac --- /dev/null +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; +#include "vexpress-v2m.dtsi" + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A9_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + A9_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + A9_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + A9_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Chipselect 3 is physically at 0x4c000000 */ + vram: vram@4c000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x4c000000 0x00800000>; + no-map; + }; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + interrupts = <0 44 4>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz */ + max-memory-bandwidth = <95000000>; + + port { + clcd_pads_ct: endpoint { + remote-endpoint = <&dvi_bridge_in_ct>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1e000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e000620 0x20>; + interrupts = <1 14 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; + + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0: extsaxiclk { + /* ACLK clock to the AXI master port on the test chip */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <30000000 50000000>; + #clock-cells = <0>; + clock-output-names = "extsaxiclk"; + }; + + oscclk1: clcdclk { + /* Reference clock for the CLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <10000000 80000000>; + #clock-cells = <0>; + clock-output-names = "clcdclk"; + }; + + smbclk: oscclk2: tcrefclk { + /* Reference clock for the test chip internal PLLs */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <33000000 100000000>; + #clock-cells = <0>; + clock-output-names = "tcrefclk"; + }; + + volt-vd10 { + /* Test Chip internal logic voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VD10"; + regulator-always-on; + label = "VD10"; + }; + + volt-vd10-s2 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "VD10_S2"; + regulator-always-on; + label = "VD10_S2"; + }; + + volt-vd10-s3 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 2>; + regulator-name = "VD10_S3"; + regulator-always-on; + label = "VD10_S3"; + }; + + volt-vcc1v8 { + /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 3>; + regulator-name = "VCC1V8"; + regulator-always-on; + label = "VCC1V8"; + }; + + volt-ddr2vtt { + /* DDR2 SDRAM VTT termination voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 4>; + regulator-name = "DDR2VTT"; + regulator-always-on; + label = "DDR2VTT"; + }; + + volt-vcc3v3 { + /* Local board supply for miscellaneous logic external to the Test Chip */ + arm,vexpress-sysreg,func = <2 5>; + compatible = "arm,vexpress-volt"; + regulator-name = "VCC3V3"; + regulator-always-on; + label = "VCC3V3"; + }; + + amp-vd10-s2 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "VD10_S2"; + }; + + amp-vd10-s3 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "VD10_S3"; + }; + + power-vd10-s2 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "PVD10_S2"; + }; + + power-vd10-s3 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "PVD10_S3"; + }; + }; + + site2: hsb@e0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000000 0x20000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/armada-370-c200-v2.dts deleted file mode 100644 index 84d40e1d70ef..000000000000 --- a/arch/arm/boot/dts/armada-370-c200-v2.dts +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Device Tree file for Ctera C200-V2 - * - * Copyright (C) 2022 Pawel Dembicki - */ - -/dts-v1/; - -#include "armada-370.dtsi" -#include -#include -#include -#include - -/ { - model = "Ctera C200 V2"; - compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1024 MB */ - }; - - soc { - ranges = ; - }; - - thermal-zones { - ethphy-thermal { - polling-delay = <20000>; - polling-delay-passive = <2000>; - - thermal-sensors = <ðphy0>; - - trips { - ethphy_alert1: trip1 { - temperature = <65000>; - hysteresis = <4000>; - type = "passive"; - }; - - ethphy_crit: trip2 { - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - beeper { - compatible = "pwm-beeper"; - pinctrl-0 = <&pmx_beeper>; - pinctrl-names = "default"; - pwms = <&gpio1 31 4000>; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - - button-power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - }; - - button-reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - - button-usb1 { - label = "USB1 Button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - button-usb2 { - label = "USB2 Button"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds1 &pmx_leds2>; - pinctrl-names = "default"; - - led-0 { - function = LED_FUNCTION_USB; - function-enumerator = <2>; - color = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - - led-1 { - function = LED_FUNCTION_USB; - function-enumerator = <2>; - color = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - led-2 { - function = LED_FUNCTION_USB; - function-enumerator = <1>; - color = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - led-3 { - function = LED_FUNCTION_USB; - function-enumerator = <1>; - color = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - - led-4 { - function = LED_FUNCTION_DISK; - function-enumerator = <2>; - color = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - led-5 { - function = LED_FUNCTION_DISK; - function-enumerator = <1>; - color = ; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - }; - - led-6 { - function = LED_FUNCTION_DISK; - function-enumerator = <2>; - color = ; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - }; - - led-7 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - }; - - led-8 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - }; - - led-9 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - }; - - led-10 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - - led-11 { - function = LED_FUNCTION_DISK; - function-enumerator = <1>; - color = ; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - - led-12 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&coherencyfab { - broken-idle; -}; - -ð1 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - - hwmon@2a { - compatible = "nuvoton,nct7802"; - reg = <0x2a>; - }; - - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - #thermal-sensor-cells = <0>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "certificate"; - reg = <0x0200000 0x100000>; - read-only; - }; - - partition@300000 { - label = "preset_cfg"; - reg = <0x0300000 0x100000>; - read-only; - }; - - partition@400000 { - label = "dev_params"; - reg = <0x0400000 0x100000>; - read-only; - }; - partition@500000 { - label = "active_bank"; - reg = <0x0500000 0x0100000>; - }; - - partition@600000 { - label = "magic"; - reg = <0x0600000 0x0100000>; - read-only; - }; - - partition@700000 { - label = "bank1"; - reg = <0x0700000 0x2800000>; - }; - - partition@2f00000 { - label = "bank2"; - reg = <0x2f00000 0x2800000>; - }; - - /* 0x5700000-0x5a00000 undefined in vendor firmware */ - - partition@5a00000 { - label = "reserved"; - reg = <0x5a00000 0x2000000>; - }; - - partition@7a00000 { - label = "rootfs"; - reg = <0x7a00000 0x8600000>; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - pcie@1,0 { /* Renesas uPD720202 USB 3.0 controller */ - pinctrl-0 = <&pmx_pcie>; - pinctrl-names = "default"; - status = "okay"; - reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_power_cpu: pmx-power-cpu { - marvell,pins = "mpp4"; - marvell,function = "vdd"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32"; - marvell,function = "gpio"; - }; - - pmx_leds1: pmx-leds1 { - marvell,pins = "mpp47"; - marvell,function = "gpo"; - }; - - pmx_leds2: pmx-leds2 { - marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51", - "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58"; - marvell,function = "gpio"; - }; - - pmx_pcie: pmx-pcie { - marvell,pins = "mpp59"; - marvell,function = "gpio"; - }; - - pmx_beeper: pmx-beeper { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; -}; - -&pmsu { - pinctrl-0 = <&pmx_power_cpu>; - pinctrl-names = "default"; -}; - -&rtc { - status = "disabled"; -}; - -&sata { - nr-ports = <2>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - hdd0_temp: sata-port@0 { - reg = <0>; - #thermal-sensor-cells = <0>; - }; - - hdd1_temp: sata-port@1 { - reg = <1>; - #thermal-sensor-cells = <0>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts deleted file mode 100644 index a7dc4c04d10b..000000000000 --- a/arch/arm/boot/dts/armada-370-db.dts +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 370 evaluation board - * (DB-88F6710-BP-DDR3) - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-370.dtsi" - -/ { - model = "Marvell Armada 370 Evaluation Board"; - compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - audio_codec: audio-codec@4a { - #sound-dai-cells = <0>; - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - - audio-controller@30000 { - pinctrl-0 = <&i2s_pins2>; - pinctrl-names = "default"; - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - /* - * This device is disabled by default, because - * using the SD card connector requires - * changing the default CON40 connector - * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a - * different connector - * "DB-88F6710_MPP_RGMII_SD_Jumper". - */ - status = "disabled"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Armada 370 DB Audio"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Headphone", "Out Jack", - "Line", "In Jack"; - simple-audio-card,routing = - "Out Jack", "HPL", - "Out Jack", "HPR", - "AIN1L", "In Jack", - "AIN1L", "In Jack"; - status = "okay"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 0>; - }; - - codec { - sound-dai = <&audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_out>; - }; - }; - - simple-audio-card,dai-link@2 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_in>; - }; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - spdif_in: spdif-in { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - }; -}; - -&pciec { - status = "okay"; - /* - * The two PCIe units are accessible through - * both standard PCIe slots and mini-PCIe - * slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - - -&spi0 { - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l25635e", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts deleted file mode 100644 index 561195b749eb..000000000000 --- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for D-Link DNS-327L - * - * Copyright (C) 2015, Andrew Andrianov - */ - -/* Remaining unsolved: - * There's still some unknown device on i2c address 0x13 - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "D-Link DNS-327L"; - compatible = "dlink,dns327l", - "marvell,armada370", - "marvell,armada-370-xp"; - - chosen { - stdout-path = &uart0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MiB */ - }; - - soc { - ranges = ; - - internal-regs { - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = < - &backup_button_pin - &power_button_pin - &reset_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < - &sata_l_amber_pin - &sata_r_amber_pin - &backup_led_pin - /* Ensure these are managed by hardware */ - &sata_l_white_pin - &sata_r_white_pin>; - - pinctrl-names = "default"; - - led-sata-r-amber { - label = "dns327l:amber:sata-r"; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - led-sata-l-amber { - label = "dns327l:amber:sata-l"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - led-backup { - label = "dns327l:white:usb"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-0 = <&xhci_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "USB3.0 Port Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - - sata_r_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-0 = <&sata_r_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-R Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - - sata_l_power: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-0 = <&sata_l_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-L Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&pinctrl { - sata_l_white_pin: sata-l-white-pin { - marvell,pins = "mpp57"; - marvell,function = "sata0"; - }; - - sata_r_white_pin: sata-r-white-pin { - marvell,pins = "mpp55"; - marvell,function = "sata1"; - }; - - sata_r_amber_pin: sata-r-amber-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - sata_l_amber_pin: sata-l-amber-pin { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp61"; - marvell,function = "gpo"; - }; - - xhci_pwr_pin: xhci-pwr-pin { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - sata_r_pwr_pin: sata-r-pwr-pin { - marvell,pins = "mpp54"; - marvell,function = "gpio"; - }; - - sata_l_pwr_pin: sata-l-pwr-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp60", "mpp61"; - marvell,function = "uart1"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; -}; - -/* Serial console */ -&uart0 { - status = "okay"; -}; - -/* Connected to Weltrend MCU */ -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - marvell,reg-init = <0x2 0x19 0x0 0x0077>, - <0x2 0x18 0x0 0x5747>; - }; -}; - -ð1 { - phy = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <100000>; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - /* 1.0 MiB */ - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - /* 128 KiB */ - reg = <0x100000 0x20000>; - read-only; - }; - - partition@120000 { - label = "uImage"; - /* 7 MiB */ - reg = <0x120000 0x700000>; - }; - - partition@820000 { - label = "ubifs"; - /* ~ 84 MiB */ - reg = <0x820000 0x54e0000>; - }; - - /* Hardcoded into stock bootloader */ - partition@5d00000 { - label = "failsafe-uImage"; - /* 5 MiB */ - reg = <0x5d00000 0x500000>; - }; - - partition@6200000 { - label = "failsafe-fs"; - /* 29 MiB */ - reg = <0x6200000 0x1d00000>; - }; - - partition@7f00000 { - label = "bbt"; - /* 1 MiB for BBT */ - reg = <0x7f00000 0x100000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts deleted file mode 100644 index 7c2f5a79b50d..000000000000 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Mirabox - * - * Gregory CLEMENT - */ - -/dts-v1/; -#include -#include "armada-370.dtsi" - -/ { - model = "Globalscale Mirabox"; - compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - timer@20300 { - clock-frequency = <600000000>; - status = "okay"; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_pin &stat_led_pins>; - - green_pwr_led { - label = "mirabox:green:pwr"; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - blue_stat_led { - label = "mirabox:blue:stat"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green_stat_led { - label = "mirabox:green:stat"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - crypto@90000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins3>; - pinctrl-names = "default"; - status = "okay"; - /* - * No CD or WP GPIOs: SDIO interface used for - * Wifi/Bluetooth chip - */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - pca9505: pca9505@25 { - compatible = "nxp,pca9505"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x25>; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&pinctrl { - pwr_led_pin: pwr-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - stat_led_pins: stat-led-pins { - marvell,pins = "mpp64", "mpp65"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Linux"; - reg = <0x400000 0x400000>; - }; - partition@800000 { - label = "Filesystem"; - reg = <0x800000 0x3f800000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts deleted file mode 100644 index 079b37cf148a..000000000000 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NETGEAR ReadyNAS 102 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 102"; - compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - serial@12000 { - status = "okay"; - }; - - /* eSATA interface */ - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <100000>; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - isl12057: rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin - &sata1_led_pin - &sata2_led_pin - &backup_led_pin>; - pinctrl-names = "default"; - - blue-power-led { - label = "rn102:blue:pwr"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - blue-sata1-led { - label = "rn102:blue:sata1"; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue-sata2-led { - label = "rn102:blue:sata2"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue-backup-led { - label = "rn102:blue:backup"; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin - &reset_button_pin - &backup_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* Connected to Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; -}; - -&pinctrl { - power_led_pin: power-led-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - poweroff: poweroff { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts deleted file mode 100644 index d752ac1d7b58..000000000000 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NETGEAR ReadyNAS 104 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 104"; - compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <100000>; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - isl12057: rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - pca9554: pca9554@23 { - compatible = "nxp,pca9554"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x23>; - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&backup_led_pin &power_led_pin>; - pinctrl-names = "default"; - - blue-backup-led { - label = "rn104:blue:backup"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue-power-led { - label = "rn104:blue:pwr"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "keep"; - }; - - blue-sata1-led { - label = "rn104:blue:sata1"; - gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata2-led { - label = "rn104:blue:sata2"; - gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata3-led { - label = "rn104:blue:sata3"; - gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata4-led { - label = "rn104:blue:sata4"; - gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - auxdisplay { - compatible = "hit,hd44780"; - data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>, - <&gpio1 26 GPIO_ACTIVE_HIGH>, - <&gpio1 27 GPIO_ACTIVE_HIGH>, - <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - display-height-chars = <2>; - display-width-chars = <16>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&backup_button_pin - &power_button_pin - &reset_button_pin>; - pinctrl-names = "default"; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to Marvell 88SE9215 SATA controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; -}; - -&pinctrl { - poweroff: poweroff { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts deleted file mode 100644 index b459a670f615..000000000000 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 370 Reference Design board - * (RD-88F6710-A1) - * - * Copied from arch/arm/boot/dts/armada-370-db.dts - * - * Copyright (C) 2013 Florian Fainelli - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include -#include -#include -#include -#include "armada-370.dtsi" - -/ { - model = "Marvell Armada 370 Reference Design"; - compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - button { - label = "Software Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 3000 1>; - pinctrl-0 = <&fan_pins>; - pinctrl-names = "default"; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - sw_led { - label = "370rd:green:sw"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Internal mini-PCIe connector */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_WAN; - default-state = "keep"; - }; - }; - }; - - switch: switch@10 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - ethernet = <ð1>; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; - - -&pinctrl { - fan_pins: fan-pins { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - led_pins: led-pins { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts deleted file mode 100644 index 8dd242e668e6..000000000000 --- a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate NAS 2-Bay - * Code name (board/PCB) : Dart 2-Bay - * Model name (case sticker) : SRPD20 - * Material desc (product spec) : STCTxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-nas-xbay.dtsi" - -/ { - model = "Seagate NAS 2-Bay (Dart, SRPD20)"; - compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp"; - - gpio-fan { - gpio-fan,speed-map = - < 0 3 - 950 2 - 1400 1 - 1800 0>; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts deleted file mode 100644 index 9cb69999b1db..000000000000 --- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate NAS 4-Bay - * Code name (board/PCB) : Dart 4-Bay - * Model name (case sticker) : SRPD40 - * Material desc (product spec) : STCUxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-nas-xbay.dtsi" -#include - -/ { - model = "Seagate NAS 4-Bay (Dart, SRPD40)"; - compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - ethernet@74000 { - status = "okay"; - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - /* I2C GPIO expander (PCA9554A) */ - pca9554: pca9554@21 { - compatible = "nxp,pca9554"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - }; - }; - - regulators { - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA2 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; - }; - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA3 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - led-red-sata2 { - label = "dart:red:sata2"; - gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; - }; - led-red-sata3 { - label = "dart:red:sata3"; - gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; - }; - }; - - leds-ns2 { - compatible = "lacie,ns2-leds"; - - white-sata2 { - label = "dart:white:sata2"; - cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>; - slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>; - num-modes = <4>; - modes-map = ; - }; - white-sata3 { - label = "dart:white:sata3"; - cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; - slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>; - num-modes = <4>; - modes-map = ; - }; - }; - - gpio-fan { - gpio-fan,speed-map = - < 0 3 - 800 2 - 1050 1 - 1300 0>; - }; -}; - -&pciec { - /* SATA AHCI controller 88SE9170 */ - pcie@1,0 { - status = "okay"; - }; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi deleted file mode 100644 index 822f10734946..000000000000 --- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - */ - -/* - * TODO: add support for the white SATA LEDs associated with HDD 0 and 1. - */ - -#include "armada-370.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - status = "okay"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - - /* RTC - NXP 8563T (second source) */ - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - interrupts = <110>; - }; - /* RTC - MCP7940NT */ - rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts = <110>; - }; - }; - }; - - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH - &gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button-backup { - label = "Backup button"; - linux,code = ; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button-reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-white-power { - label = "dart:white:power"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - - }; - led-red-power { - label = "dart:red:power"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - }; - led-red-sata0 { - label = "dart:red:sata0"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - led-red-sata1 { - label = "dart:red:sata1"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* USB 3.0 bridge ASM1042A */ - pcie@2,0 { - status = "okay"; - }; -}; - - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pinctrl { - pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; - pinctrl-names = "default"; - - hdd0_led_sata_pin: hdd0-led-sata-pin { - marvell,pins = "mpp48"; - marvell,function = "sata1"; - }; - hdd0_led_gpio_pin: hdd0-led-gpio-pin { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - hdd1_led_sata_pin: hdd1-led-sata-pin { - marvell,pins = "mpp57"; - marvell,function = "sata0"; - }; - hdd1_led_gpio_pin: hdd1-led-gpio-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; - partition@300000 { - label = "device-tree"; - reg = <0x300000 0x20000>; - }; - partition@320000 { - label = "linux"; - reg = <0x320000 0x2000000>; - }; - partition@2320000 { - label = "rootfs"; - reg = <0x2320000 0xdce0000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts deleted file mode 100644 index 5ee572dc9242..000000000000 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate Personal Cloud 2-Bay - * Code name (board/PCB) : Cumulus Max - * Model name (case sticker) : SRN22C - * Material desc (product spec) : STCSxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-personal-cloud.dtsi" - -/ { - model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)"; - compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - sata@a0000 { - status = "okay"; - nr-ports = <2>; - }; - }; - }; - - regulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts deleted file mode 100644 index 578b54b39c8f..000000000000 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate Personal Cloud - * Code name (board/PCB) : Cumulus - * Model name (case sticker) : SRN21C - * Material desc (product spec) : STCRxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-personal-cloud.dtsi" - -/ { - model = "Seagate Personal Cloud (Cumulus, SRN21C)"; - compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - sata@a0000 { - status = "okay"; - nr-ports = <1>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi deleted file mode 100644 index 124a8ba279e3..000000000000 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay - * (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - */ - -/* - * TODO: add support for the white SATA LED. - */ - -#include "armada-370.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - coherency-fabric@20200 { - broken-idle; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@74000 { - status = "okay"; - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - debounce-interval = <100>; - }; - button-reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button-usb { - label = "USB VBUS error"; - linux,code = ; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-red-sata0 { - label = "cumulus:red:sata0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - }; -}; - -&pciec { - status = "okay"; - - /* USB 3.0 Bridge ASM1042A */ - pcie@1,0 { - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pinctrl { - pinctrl-0 = <&sata_led_pin>; - pinctrl-names = "default"; - - sata_led_pin: sata-led-pin { - marvell,pins = "mpp60"; - marvell,function = "sata0"; - }; - gpio_led_pin: gpio-led-pin { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - /* MX25L8006E */ - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts deleted file mode 100644 index f0893cc06607..000000000000 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Synology DS213j - * - * Copyright (C) 2014, Arnaud EBALARD - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the old 0xd0000000). - * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot - * bootloaders provided by Marvell. It is used in recent versions of - * DSM software provided by Synology. Nonetheless, some earlier boards - * were delivered with an older version of u-boot that left internal - * registers mapped at 0xd0000000. If you have such a device you will - * not be able to directly boot a kernel based on this Device Tree. In - * that case, the preferred solution is to update your bootloader (e.g. - * by upgrading to latest version of DSM, or building a new one and - * installing it from u-boot prompt) or adjust the Devive Tree - * (s/0xf1000000/0xd0000000/ in 'ranges' below). - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "Synology DS213j"; - compatible = "synology,ds213j", "marvell,armada370", - "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC provided by Seiko S-35390A I2C RTC chip below */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - /* Main device RTC chip */ - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - /* Connected to a header on device's PCB */ - serial@12000 { - status = "okay"; - }; - - /* Connected to a TI MSP430F2111 for power control */ - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - /* rear USB port, near reset button */ - usb@50000 { - status = "okay"; - }; - - /* rear USB port, near RJ45 port */ - usb@51000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - }; - }; - - gpio-fan-32-38 { - status = "okay"; - compatible = "gpio-fan"; - pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin - &fan_ctrl_high_pin &fan_alarm_pin>; - pinctrl-names = "default"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH - &gpio2 0 GPIO_ACTIVE_HIGH - &gpio2 1 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1000 1 - 1150 2 - 1350 4 - 1500 3 - 1650 5 - 1750 6 - 1900 7 >; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&disk1_led_pin - &disk2_led_pin>; - pinctrl-names = "default"; - - disk1-led-amber { - label = "synology:amber:disk1"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - disk2-led-amber { - label = "synology:amber:disk2"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; - pinctrl-names = "default"; - - sata1_regulator: sata1-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; -}; - -&pinctrl { - disk1_led_pin: disk1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - disk2_led_pin: disk2-led-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata1_pwr_pin: sata1-pwr-pin { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - sata2_pwr_pin: sata2-pwr-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - syno_id_bit0_pin: syno-id-bit0-pin { - marvell,pins = "mpp55"; - marvell,function = "gpio"; - }; - - syno_id_bit1_pin: syno-id-bit1-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - syno_id_bit2_pin: syno-id-bit2-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - syno_id_bit3_pin: syno-id-bit3-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - fan_ctrl_low_pin: fan-ctrl-low-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - - fan_ctrl_mid_pin: fan-ctrl-mid-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - fan_ctrl_high_pin: fan-ctrl-high-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - fan_alarm_pin: fan-alarm-pin { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@0 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@c0000 { /* uImage */ - label = "zImage"; - reg = <0x000c0000 0x002d0000>; /* 2880KB */ - }; - - partition@390000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x00390000 0x00440000>; /* 4250KB */ - }; - - partition@7d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi deleted file mode 100644 index 0b8c2a64b36f..000000000000 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 370 and Armada XP SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * Ben Dooks - * - * This file contains the definitions that are common to the Armada - * 370 and Armada XP SoC. - */ - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Armada 370 and XP SoC"; - compatible = "marvell,armada-370-xp"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "marvell,sheeva-v7"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&mpic>; - pcie-mem-aperture = <0xf8000000 0x7e00000>; - pcie-io-aperture = <0xffe00000 0x100000>; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs3: devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - rtc: rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <50>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <31>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <41>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <42>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pin-ctrl@18000 { - reg = <0x18000 0x38>; - }; - - coredivclk: corediv-clock@18740 { - compatible = "marvell,armada-370-corediv-clock"; - reg = <0x18740 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, - <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - }; - - coherencyfab: coherency-fabric@20200 { - compatible = "marvell,coherency-fabric"; - reg = <0x20200 0xb0>, <0x21010 0x1c>; - }; - - timer: timer@20300 { - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - }; - - watchdog: watchdog@20300 { - reg = <0x20300 0x34>, <0x20704 0x4>; - }; - - cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x8>; - }; - - pmsu: pmsu@22000 { - compatible = "marvell,armada-370-pmsu"; - reg = <0x22000 0x1000>; - }; - - usb0: usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = <45>; - status = "disabled"; - }; - - usb1: usb@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x500>; - interrupts = <46>; - status = "disabled"; - }; - - eth0: ethernet@70000 { - reg = <0x70000 0x4000>; - interrupts = <8>; - clocks = <&gateclk 4>; - status = "disabled"; - }; - - mdio: mdio@72004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; - clocks = <&gateclk 4>; - }; - - eth1: ethernet@74000 { - reg = <0x74000 0x4000>; - interrupts = <10>; - clocks = <&gateclk 3>; - status = "disabled"; - }; - - sata: sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = <55>; - clocks = <&gateclk 15>, <&gateclk 30>; - clock-names = "0", "1"; - status = "disabled"; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <113>; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdio: mvsdio@d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd4000 0x200>; - interrupts = <54>; - clocks = <&gateclk 17>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; - - spi0: spi@10600 { - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - }; - }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi deleted file mode 100644 index 2013a5ccecd3..000000000000 --- a/arch/arm/boot/dts/armada-370.dtsi +++ /dev/null @@ -1,439 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 370 family SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * Contains definitions specific to the Armada 370 SoC that are not - * common to all Armada SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Marvell Armada 370 family SoC"; - compatible = "marvell,armada370", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - soc { - compatible = "marvell,armada370-mbus", "simple-bus"; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - pciec: pcie@82000000 { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 58>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 62>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - L2: l2-cache@8000 { - compatible = "marvell,aurora-outer-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - clocks = <&coreclk 0>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - - systemc: system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-370-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18230 { - compatible = "marvell,armada-370-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - - thermal: thermal@18300 { - compatible = "marvell,armada370-thermal"; - reg = <0x18300 0x4 - 0x18304 0x4>; - status = "okay"; - }; - - sscg: sscg@18330 { - reg = <0x18330 0x4>; - }; - - cpuconf: cpu-config@21000 { - compatible = "marvell,armada-370-cpu-config"; - reg = <0x21000 0x8>; - }; - - audio_controller: audio-controller@30000 { - #sound-dai-cells = <1>; - compatible = "marvell,armada370-audio"; - reg = <0x30000 0x4000>; - interrupts = <93>; - clocks = <&gateclk 0>; - clock-names = "internal"; - status = "disabled"; - }; - - xor0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - - xor00 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; - - xor10 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-370-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>; - clocks = <&gateclk 23>; - clock-names = "cesa0"; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x7e0>; - }; - }; - - crypto_sram: sa-sram { - compatible = "mmio-sram"; - reg = ; - reg-names = "sram"; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; - - /* - * The Armada 370 has an erratum preventing the use of - * the standard workflow for CPU idle support (relying - * on the BootROM code to enter/exit idle state). - * Reserve some amount of the crypto SRAM to put the - * cpuidle workaround. - */ - idle-sram@0 { - reg = <0x0 0x20>; - }; - }; - }; -}; - -/* - * Default UART pinctrl setting without RTS/CTS, can be overwritten on - * board level if a different configuration is used. - */ - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; -}; - -&i2c0 { - reg = <0x11000 0x20>; -}; - -&i2c1 { - reg = <0x11100 0x20>; -}; - -&mpic { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; -}; - -&timer { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; -}; - -&watchdog { - compatible = "marvell,armada-370-wdt"; - clocks = <&coreclk 2>; -}; - -&usb0 { - clocks = <&coreclk 0>; -}; - -&usb1 { - clocks = <&coreclk 0>; -}; - -ð0 { - compatible = "marvell,armada-370-neta"; -}; - -ð1 { - compatible = "marvell,armada-370-neta"; -}; - -&pinctrl { - compatible = "marvell,mv88f6710-pinctrl"; - - spi0_pins1: spi0-pins1 { - marvell,pins = "mpp33", "mpp34", - "mpp35", "mpp36"; - marvell,function = "spi0"; - }; - - spi0_pins2: spi0_pins2 { - marvell,pins = "mpp32", "mpp63", - "mpp64", "mpp65"; - marvell,function = "spi0"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp49", "mpp50", - "mpp51", "mpp52"; - marvell,function = "spi1"; - }; - - uart0_pins: uart0-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "uart0"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp41", "mpp42"; - marvell,function = "uart1"; - }; - - sdio_pins1: sdio-pins1 { - marvell,pins = "mpp9", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15"; - marvell,function = "sd0"; - }; - - sdio_pins2: sdio-pins2 { - marvell,pins = "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52"; - marvell,function = "sd0"; - }; - - sdio_pins3: sdio-pins3 { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp51", "mpp52", "mpp53"; - marvell,function = "sd0"; - }; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - i2s_pins1: i2s-pins1 { - marvell,pins = "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", - "mpp12", "mpp13"; - marvell,function = "audio"; - }; - - i2s_pins2: i2s-pins2 { - marvell,pins = "mpp49", "mpp47", "mpp50", - "mpp59", "mpp57", "mpp61", - "mpp62", "mpp60", "mpp58"; - marvell,function = "audio"; - }; - - mdio_pins: mdio-pins { - marvell,pins = "mpp17", "mpp18"; - marvell,function = "ge"; - }; - - ge0_rgmii_pins: ge0-rgmii-pins { - marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge1-rgmii-pins { - marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27", "mpp28", "mpp29", "mpp30"; - marvell,function = "ge1"; - }; -}; - -/* - * Default SPI pinctrl setting, can be overwritten on - * board level if a different configuration is used. - */ -&spi0 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins1>; - pinctrl-names = "default"; -}; - -&spi1 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts deleted file mode 100644 index 4c4092790a20..000000000000 --- a/arch/arm/boot/dts/armada-375-db.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 375 evaluation board - * (DB-88F6720) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include "armada-375.dtsi" - -/ { - model = "Marvell Armada 375 Development Board"; - compatible = "marvell,a375-db", "marvell,armada375"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - }; -}; -&pciec { - status = "okay"; -}; - -/* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ -&pcie0 { - /* Port 0, Lane 0 */ - status = "okay"; -}; - -&pcie1 { - /* Port 1, Lane 0 */ - status = "okay"; -}; - - -&spi0 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - - /* - * SPI conflicts with NAND, so we disable it here, and - * select NAND as the enabled device by default. - */ - - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; -}; - -&uart0 { - status = "okay"; -}; - -&pinctrl { - sdio_st_pins: sdio-st-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&sdio { - pinctrl-0 = <&sdio_pins &sdio_st_pins>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; -}; - -ðernet { - status = "okay"; -}; - - -ð0 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -ð1 { - status = "okay"; - phy = <&phy3>; - phy-mode = "gmii"; -}; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi deleted file mode 100644 index ddc49547d786..000000000000 --- a/arch/arm/boot/dts/armada-375.dtsi +++ /dev/null @@ -1,645 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 375 family SoC - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Marvell Armada 375 family SoC"; - compatible = "marvell,armada375"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - serial0 = &uart0; - serial1 = &uart1; - }; - - clocks { - /* 1 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-375-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada375-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs3: devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu: scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x58>; - }; - - timer0: timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - mdio: mdio@c0054 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0xc0054 0x4>; - clocks = <&gateclk 19>; - }; - - /* Network controller */ - ethernet: ethernet@f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,armada-375-pp2"; - reg = <0xf0000 0xa000>, /* Packet Processor regs */ - <0xc0000 0x3060>, /* LMS regs */ - <0xc4000 0x100>, /* eth0 regs */ - <0xc5000 0x100>; /* eth1 regs */ - clocks = <&gateclk 3>, <&gateclk 19>; - clock-names = "pp_clk", "gop_clk"; - status = "disabled"; - - eth0: ethernet-port@0 { - interrupts = ; - reg = <0>; - port-id = <0>; /* For backward compatibility. */ - status = "disabled"; - }; - - eth1: ethernet-port@1 { - interrupts = ; - reg = <1>; - port-id = <1>; /* For backward compatibility. */ - status = "disabled"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = ; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-375-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-375-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pinctrl@18000 { - compatible = "marvell,mv88f6720-pinctrl"; - reg = <0x18000 0x24>; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - marvell,pins = "mpp61", "mpp62"; - marvell,function = "i2c1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13"; - marvell,function = "nand"; - }; - - sdio_pins: sdio-pins { - marvell,pins = "mpp24", "mpp25", "mpp26", - "mpp27", "mpp28", "mpp29"; - marvell,function = "sd"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp0", "mpp1", "mpp4", - "mpp5", "mpp8", "mpp9"; - marvell,function = "spi0"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-375-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-375-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - usbcluster: usb-cluster@18400 { - compatible = "marvell,armada-375-usb-cluster"; - reg = <0x18400 0x4>; - #phy-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer1: timer@20300 { - compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 0>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog: watchdog@20300 { - compatible = "marvell,armada-375-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; - clocks = <&coreclk 0>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - coherencyfab: coherency-fabric@21010 { - compatible = "marvell,armada-375-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - usb0: usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = ; - clocks = <&gateclk 18>; - phys = <&usbcluster PHY_TYPE_USB2>; - phy-names = "usb"; - status = "disabled"; - }; - - usb1: usb@54000 { - compatible = "marvell,orion-ehci"; - reg = <0x54000 0x500>; - interrupts = ; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - usb2: usb@58000 { - compatible = "marvell,armada-375-xhci"; - reg = <0x58000 0x20000>,<0x5b880 0x80>; - interrupts = ; - clocks = <&gateclk 16>; - phys = <&usbcluster PHY_TYPE_USB3>; - phy-names = "usb"; - status = "disabled"; - }; - - xor0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 23>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-375-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = , - ; - clocks = <&gateclk 30>, <&gateclk 31>, - <&gateclk 28>, <&gateclk 29>; - clock-names = "cesa0", "cesa1", - "cesaz0", "cesaz1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - sata: sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = ; - clocks = <&gateclk 14>, <&gateclk 20>; - clock-names = "0", "1"; - status = "disabled"; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - sdio: mvsdio@d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd4000 0x200>; - interrupts = ; - clocks = <&gateclk 17>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - - thermal: thermal@e8078 { - compatible = "marvell,armada375-thermal"; - reg = <0xe8078 0x4>, <0xe807c 0x8>; - status = "okay"; - }; - - coreclk: mvebu-sar@e8204 { - compatible = "marvell,armada-375-core-clock"; - reg = <0xe8204 0x04>; - #clock-cells = <1>; - }; - - coredivclk: corediv-clock@e8250 { - compatible = "marvell,armada-375-corediv-clock"; - reg = <0xe8250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - }; - - pciec: pcie@82000000 { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 30>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 31>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi deleted file mode 100644 index e94f22b0e9b5..000000000000 --- a/arch/arm/boot/dts/armada-380.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 380 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 380 family SoC"; - compatible = "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6810-pinctrl"; - }; - }; - - pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; - - /* x1 port */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts deleted file mode 100644 index f4c4b213ef4e..000000000000 --- a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* Copyright (c) 2021, Marcel Ziswiler */ - -/dts-v1/; -#include "armada-385.dtsi" -#include -#include - -/ { - model = "Netgear GS110EMX"; - compatible = "netgear,gs110emx", "marvell,armada380"; - - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&front_button_pins>; - pinctrl-names = "default"; - - key-factory-default { - label = "Factory Default"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; /* 128 MB */ - }; - - soc { - ranges = ; - - internal-regs { - rtc@a3800 { - /* - * If the rtc doesn't work, run "date reset" - * twice in u-boot. - */ - status = "okay"; - }; - }; - }; -}; - -ð0 { - /* ethernet@70000 */ - bm,pool-long = <0>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - - fixed-link { - full-duplex; - pause; - speed = <1000>; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6190"; - #address-cells = <1>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&switch_interrupt_pins>; - pinctrl-names = "default"; - #size-cells = <0>; - reg = <0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: switch0phy1@1 { - reg = <0x1>; - }; - - switch0phy2: switch0phy2@2 { - reg = <0x2>; - }; - - switch0phy3: switch0phy3@3 { - reg = <0x3>; - }; - - switch0phy4: switch0phy4@4 { - reg = <0x4>; - }; - - switch0phy5: switch0phy5@5 { - reg = <0x5>; - }; - - switch0phy6: switch0phy6@6 { - reg = <0x6>; - }; - - switch0phy7: switch0phy7@7 { - reg = <0x7>; - }; - - switch0phy8: switch0phy8@8 { - reg = <0x8>; - }; - }; - - mdio-external { - compatible = "marvell,mv88e6xxx-mdio-external"; - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@b { - reg = <0xb>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - phy2: ethernet-phy@c { - reg = <0xc>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - ethernet = <ð0>; - phy-mode = "rgmii"; - reg = <0>; - - fixed-link { - full-duplex; - pause; - speed = <1000>; - }; - }; - - port@1 { - label = "lan1"; - phy-handle = <&switch0phy1>; - reg = <1>; - }; - - port@2 { - label = "lan2"; - phy-handle = <&switch0phy2>; - reg = <2>; - }; - - port@3 { - label = "lan3"; - phy-handle = <&switch0phy3>; - reg = <3>; - }; - - port@4 { - label = "lan4"; - phy-handle = <&switch0phy4>; - reg = <4>; - }; - - port@5 { - label = "lan5"; - phy-handle = <&switch0phy5>; - reg = <5>; - }; - - port@6 { - label = "lan6"; - phy-handle = <&switch0phy6>; - reg = <6>; - }; - - port@7 { - label = "lan7"; - phy-handle = <&switch0phy7>; - reg = <7>; - }; - - port@8 { - label = "lan8"; - phy-handle = <&switch0phy8>; - reg = <8>; - }; - - port@9 { - /* 88X3310P external phy */ - label = "lan9"; - phy-handle = <&phy1>; - phy-mode = "xaui"; - reg = <9>; - }; - - port@a { - /* 88X3310P external phy */ - label = "lan10"; - phy-handle = <&phy2>; - phy-mode = "xaui"; - reg = <0xa>; - }; - }; - }; -}; - -&pinctrl { - front_button_pins: front-button-pins { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - switch_interrupt_pins: switch-interrupt-pins { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - read-only; - reg = <0x00000000 0x00100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x00100000 0x00010000>; - }; - - partition@200000 { - label = "rsv"; - reg = <0x00110000 0x00010000>; - }; - - partition@300000 { - label = "image0"; - reg = <0x00120000 0x00900000>; - }; - - partition@400000 { - label = "config"; - reg = <0x00a20000 0x00300000>; - }; - - partition@480000 { - label = "debug"; - reg = <0x00d20000 0x002e0000>; - }; - }; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts deleted file mode 100644 index 584f0d0398a5..000000000000 --- a/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 382 reference board - * (RD-AC3X-48G4X2XL) - * - * Copyright (C) 2020 Allied Telesis Labs - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "Marvell Armada 382 RD-AC3X"; - compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x", - "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = ð1; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512MB */ - }; - - soc { - ranges = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - eeprom@53{ - compatible = "atmel,24c64"; - reg = <0x53>; - }; - - /* CPLD device present at 0x3c. Function unknown */ -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -ð1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - /* Port 0, Lane 0 */ - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x00500000>; - label = "u-boot"; - }; - partition@500000{ - reg = <0x00500000 0x00400000>; - label = "u-boot env"; - }; - partition@900000{ - reg = <0x00900000 0x3F700000>; - label = "user"; - }; - }; - }; -}; - -&refclk { - clock-frequency = <200000000>; -}; diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/armada-385-atl-x530.dts deleted file mode 100644 index 5a9ab8410b7b..000000000000 --- a/arch/arm/boot/dts/armada-385-atl-x530.dts +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board. - (x530/AT-GS980MX) - * - Copyright (C) 2020 Allied Telesis Labs - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "x530/AT-GS980MX"; - compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c0: i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - }; - - uart0: serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - reset-delay-us = <400000>; -}; - -&pcie2 { - status = "okay"; -}; - -&devbus_cs1 { - compatible = "marvell,mvebu-devbus"; - status = "okay"; - - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - nvs@0 { - status = "okay"; - - compatible = "mtd-ram"; - reg = <0 0x00080000>; - bank-width = <1>; - label = "nvs"; - }; -}; - -&pinctrl { - i2c0_gpio_pins: i2c-gpio-pins-0 { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "gpio"; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-1 = <&i2c0_gpio_pins>; - scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - i2c0mux: mux@71 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,pca9544"; - reg = <0x71>; - i2c-mux-idle-disconnect; - - i2c@0 { /* POE devices MUX */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adt7476_2e: hwmon@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; - - adt7476_2d: hwmon@2d { - compatible = "adi,adt7476"; - reg = <0x2d>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - rtc@68 { - compatible = "dallas,ds1340"; - reg = <0x68>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - gpio@20 { - compatible = "nxp,pca9554"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; -}; - -&usb0 { - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <54000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@100000 { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - partition@140000 { - reg = <0x00140000 0x00e80000>; - label = "unused"; - }; - partition@fc0000 { - reg = <0x00fc0000 0x00040000>; - label = "idprom"; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - marvell,nand-enable-arbiter; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x0f000000>; - label = "user"; - }; - partition@f000000 { - /* Maximum mtdoops size is 8MB, so set to that. */ - reg = <0x0f000000 0x00800000>; - label = "errlog"; - }; - partition@f800000 { - reg = <0x0f800000 0x00800000>; - label = "nand-bbt"; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts deleted file mode 100644 index 1990f7d0cc79..000000000000 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -#include "armada-385-clearfog-gtr.dtsi" - -/ { - model = "SolidRun Clearfog GTR L8"; -}; - -&mdio { - switch0: switch0@4 { - compatible = "marvell,mv88e6190"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cf_gtr_switch_reset_pins>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan8"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan7"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan6"; - phy-handle = <&switch0phy2>; - }; - - port@4 { - reg = <4>; - label = "lan5"; - phy-handle = <&switch0phy3>; - }; - - port@5 { - reg = <5>; - label = "lan4"; - phy-handle = <&switch0phy4>; - }; - - port@6 { - reg = <6>; - label = "lan3"; - phy-handle = <&switch0phy5>; - }; - - port@7 { - reg = <7>; - label = "lan2"; - phy-handle = <&switch0phy6>; - }; - - port@8 { - reg = <8>; - label = "lan1"; - phy-handle = <&switch0phy7>; - }; - - port@10 { - reg = <10>; - phy-mode = "2500base-x"; - - ethernet = <ð1>; - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@1 { - reg = <0x1>; - }; - - switch0phy1: switch0phy1@2 { - reg = <0x2>; - }; - - switch0phy2: switch0phy2@3 { - reg = <0x3>; - }; - - switch0phy3: switch0phy3@4 { - reg = <0x4>; - }; - - switch0phy4: switch0phy4@5 { - reg = <0x5>; - }; - - switch0phy5: switch0phy5@6 { - reg = <0x6>; - }; - - switch0phy6: switch0phy6@7 { - reg = <0x7>; - }; - - switch0phy7: switch0phy7@8 { - reg = <0x8>; - }; - }; - - }; -}; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts deleted file mode 100644 index b795ad573891..000000000000 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -#include "armada-385-clearfog-gtr.dtsi" - -/ { - model = "SolidRun Clearfog GTR S4"; -}; - -&sfp0 { - tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; -}; - -&mdio { - switch0: switch0@4 { - compatible = "marvell,mv88e6085"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cf_gtr_switch_reset_pins>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan2"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan4"; - phy-handle = <&switch0phy2>; - }; - - port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@5 { - reg = <5>; - phy-mode = "2500base-x"; - ethernet = <ð1>; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - - switch0phy3: switch0phy3@14 { - reg = <0x14>; - }; - }; - - }; -}; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi deleted file mode 100644 index d1452a04e904..000000000000 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825) - * - * Rabeeh Khoury , based on Russell King clearfog work - */ - -/* - SERDES mapping - - 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0 - 1. 6141 switch (2.5Gbps capable) - 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1 - 3. USB 3.0 Host - 4. mini PCIe CON2 - PCIe2 - 5. SFP connector, or optionally SGMII Ethernet 1512 PHY - - USB 2.0 mapping - - 0. USB 2.0 - 0 USB pins header CON12 - 1. USB 2.0 - 1 mini PCIe CON2 - 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3) - - Pin mapping - - 0,1 - console UART - 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors, - front panel and PSE controller - 4,5 - MDC/MDIO - 6..17 - RGMII - 18 - Topaz switch reset (active low) - 19 - 1512 phy reset - 20 - 1512 phy reset (eth2, optional) - 21,28,37,38,39,40 - SD0 - 22 - USB 3.0 current limiter enable (active high) - 24 - SFP TX fault (input active high) - 25 - SFP present (input active low) - 26,27 - I2C1 - connected to SFP - 29 - Fan PWM - 30 - CON4 mini PCIe wifi disable - 31 - CON3 mini PCIe wifi disable - 32 - Fuse programming power toggle (1.8v) - 33 - CON4 mini PCIe reset - 34 - CON2 mini PCIe wifi disable - 35 - CON3 mini PCIe reset - 36 - Rear button (GPIO active low) - 41 - CON1 front panel connector - 42 - Front LED1, or front panel CON1 - 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS - 44 - CON2 mini PCIe reset - 45 - TPM PIRQ signal, or front panel CON1 - 46 - SFP TX disable - 47 - Control isolation of boot sensitive SAR signals - 48 - PSE reset - 49 - PSE OSS signal - 50 - PSE interrupt - 52 - Front LED2, or front panel - 53 - Front button - 54 - SFP LOS (input active high) - 55 - Fan sense - 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM - 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable) -*/ - -/dts-v1/; -#include -#include -#include -#include "armada-385.dtsi" - -/ { - compatible = "marvell,armada385", "marvell,armada380"; - - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - ethernet2 = ð1; - ethernet3 = ð2; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - v_usb3_con: regulator-v-usb3-con { - compatible = "regulator-fixed"; - gpio = <&gpio0 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cf_gtr_usb3_con_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb3_con"; - vin-supply = <®_5p0v>; - regulator-boot-on; - regulator-always-on; - }; - - soc { - ranges = ; - - internal-regs { - - rtc@a3800 { - status = "okay"; - }; - - i2c@11000 { /* ROM, temp sensor and front panel */ - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - i2c@11100 { /* SFP (CON5/CON6) */ - pinctrl-0 = <&cf_gtr_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - pinctrl@18000 { - cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - cf_gtr_i2c1_pins: i2c1-pins { - /* SFP */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - - cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - - cf_gtr_isolation_pins: cf-gtr-isolation-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - cf_gtr_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp59"; - marvell,function = "spi1"; - }; - - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - }; - - sdhci@d8000 { - bus-width = <4>; - no-1-8-v; - non-removable; - pinctrl-0 = <&cf_gtr_sdhci_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc = <®_3p3v>; - wp-inverted; - }; - - usb@58000 { - status = "okay"; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - vbus-supply = <&v_usb3_con>; - status = "okay"; - }; - }; - - pcie { - status = "okay"; - /* - * The PCIe units are accessible through - * the mini-PCIe connectors on the board. - */ - pcie@1,0 { - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - pcie@2,0 { - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - pcie@3,0 { - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - sfp0: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>; - pinctrl-names = "default"; - - button-0 { - label = "Rear Button"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - - button-1 { - label = "Front Button"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led1 { - function = LED_FUNCTION_CPU; - color = ; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led2 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - /* ethernet@70000 */ - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy_dedicated>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - status = "okay"; -}; - -ð1 { - /* ethernet@30000 */ - bm,pool-long = <2>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - phys = <&comphy1 1>; - phy-mode = "2500base-x"; - status = "okay"; - - fixed-link { - speed = <2500>; - full-duplex; - }; -}; - -ð2 { - /* ethernet@34000 */ - bm,pool-long = <3>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - managed = "in-band-status"; - phys = <&comphy5 1>; - phy-mode = "sgmii"; - sfp = <&sfp0>; - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver configures the LED - * register, rather than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x1017>; - reg = <0>; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spi1 { - /* - * CS0: W25Q32 flash - */ - pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - status = "okay"; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* U26 temperature sensor placed near SoC */ - temp1: nct75@4c { - compatible = "lm75"; - reg = <0x4c>; - }; - - /* U27 temperature sensor placed near RTC battery */ - temp2: nct75@4d { - compatible = "lm75"; - reg = <0x4d>; - }; - - /* 2Kb eeprom */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; -}; - -&ahci0 { - status = "okay"; -}; - -&ahci1 { - status = "okay"; -}; - -&gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; - pinctrl-names = "default"; - - wifi-disable { - gpio-hog; - gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; - output-low; - line-name = "wifi-disable"; - }; -}; - -&gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; - pinctrl-names = "default"; - - lte-disable { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - line-name = "lte-disable"; - }; - - /* - * This signal, when asserted, isolates Armada 38x sample at reset pins - * from control of external devices. Should be de-asserted after reset. - */ - sar-isolation { - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - output-low; - line-name = "sar-isolation"; - }; - - poe-reset { - gpio-hog; - gpios = <16 GPIO_ACTIVE_LOW>; - output-low; - line-name = "poe-reset"; - }; -}; diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts deleted file mode 100644 index 389d9c75d546..000000000000 --- a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 385 AMC board - * (DB-88F6820-AMC) - * - * Copyright (C) 2017 Allied Telesis Labs - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "Marvell Armada 385 AMC"; - compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = ð0; - ethernet1 = ð1; - spi1 = &spi1; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&uart0 { - /* - * Exported on the micro USB connector CON3 - * through an FTDI - */ - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - - -ð0 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -ð2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; -}; - -&usb0 { - status = "okay"; -}; - - - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@0 { - reg = <0>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x40000000>; - label = "user"; - }; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - /* Port 0, Lane 0 */ - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@100000 { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - }; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts deleted file mode 100644 index 332f8fce77dc..000000000000 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 385 Access Point Development board - * (DB-88F6820-AP) - * - * Copyright (C) 2014 Marvell - * - * Nadav Haklai - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "Marvell Armada 385 Access Point Development Board"; - compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c0: i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - /* - * This bus is wired to two EEPROM - * sockets, one of which holding the - * board ID used by the bootloader. - * Erasing this EEPROM's content will - * brick the board. - * Use this bus with caution. - */ - }; - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@4 { - reg = <4>; - }; - - phy2: ethernet-phy@6 { - reg = <6>; - }; - }; - - /* UART0 is exposed through the JP8 connector */ - uart0: serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - /* - * UART1 is exposed through a FTDI chip - * wired to the mini-USB connector - */ - uart1: serial@12100 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - pinctrl@18000 { - xhci0_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - - /* CON3 */ - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - bm,pool-short = <3>; - }; - - /* CON2 */ - ethernet@34000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - usb@58000 { - status = "okay"; - }; - - /* CON4 */ - ethernet@70000 { - pinctrl-names = "default"; - - /* - * The Reference Clock 0 is used to - * provide a clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <3>; - }; - - bm@c8000 { - status = "okay"; - }; - - usb3@f0000 { - status = "okay"; - usb-phy = <&usb3_phy>; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie { - status = "okay"; - - /* - * The three PCIe units are accessible through - * standard mini-PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_xhci0_vbus>; - #phy-cells = <0>; - }; - - reg_xhci0_vbus: xhci0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-name = "xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <54000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x00000000 0x00800000>; - read-only; - }; - - partition@800000 { - label = "uImage"; - reg = <0x00800000 0x00400000>; - read-only; - }; - - partition@c00000 { - label = "Root"; - reg = <0x00c00000 0x3f400000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts deleted file mode 100644 index 88b2921fed55..000000000000 --- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree include for the Linksys WRT1200AC (Caiman) - * - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1200AC"; - compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "caiman:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "caiman:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "caiman:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "caiman:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "caiman:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "caiman:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "caiman:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "caiman:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "caiman:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - led-power { - label = "caiman:white:power"; - }; - - led-sata { - label = "caiman:white:sata"; - }; -}; - -&nand { - /* 128MiB */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts deleted file mode 100644 index 88200f930d0d..000000000000 --- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT1900ACv2 (Cobra) - * - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1900ACv2"; - compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "cobra:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "cobra:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "cobra:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "cobra:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "cobra:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "cobra:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "cobra:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "cobra:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "cobra:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - led-power { - label = "cobra:white:power"; - }; - - led-sata { - label = "cobra:white:sata"; - }; -}; - -&nand { - /* 128MiB */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/armada-385-linksys-rango.dts deleted file mode 100644 index 4ab45f294de2..000000000000 --- a/arch/arm/boot/dts/armada-385-linksys-rango.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT3200ACM (Rango) - * - * Copyright (C) 2016 Imre Kaloz - */ - -/dts-v1/; -#include -#include -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT3200ACM"; - compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "rango:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "rango:white:wan"; - reg = <0x1>; - }; - - usb2@5 { - label = "rango:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "rango:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "rango:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "rango:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "rango:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - led-power { - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - label = "rango:white:power"; - }; - - led-sata { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "rango:white:sata"; - }; - - led-wlan_2g { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - label = "rango:white:wlan_2g"; - }; - - led-wlan_5g { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - label = "rango:white:wlan_5g"; - }; -}; - -&gpio_leds_pins { - marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; -}; - -&nand { - /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@200000 { - label = "u_env"; - reg = <0x200000 0x20000>; /* 128KiB */ - }; - - partition@220000 { - label = "s_env"; - reg = <0x220000 0x40000>; /* 256KiB */ - }; - - partition@7e0000 { - label = "devinfo"; - reg = <0x7e0000 0x40000>; /* 256KiB */ - read-only; - }; - - partition@820000 { - label = "sysdiag"; - reg = <0x820000 0x1e0000>; /* 1920KiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x5000000>; /* 80MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x4a00000>; /* 74MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@5a00000 { - label = "kernel2"; - reg = <0x5a00000 0x5000000>; /* 80MiB */ - }; - - partition@6000000 { - label = "rootfs2"; - reg = <0x6000000 0x4a00000>; /* 74MiB */ - }; - - /* - * 86MiB, last MiB is for the BBT, not writable - */ - partition@aa00000 { - label = "syscfg"; - reg = <0xaa00000 0x5600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x260000 0x5c0000>; /* 5.75MiB */ - }; - }; -}; - -&sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - non-removable; - wp-inverted; - bus-width = <8>; - status = "okay"; -}; - -&usb3_1_vbus { - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; -}; - -&usb3_1_vbus_pins { - marvell,pins = "mpp44"; -}; diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts deleted file mode 100644 index f1b1f22413f1..000000000000 --- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT1900ACS (Shelby) - * - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1900ACS"; - compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "shelby:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "shelby:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "shelby:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "shelby:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "shelby:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "shelby:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "shelby:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "shelby:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "shelby:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - led-power { - label = "shelby:white:power"; - }; - - led-sata { - label = "shelby:white:sata"; - }; -}; - -&nand { - /* 128MiB */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi deleted file mode 100644 index fc8216fd9f60..000000000000 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree include file for Armada 385 based Linksys boards - * - * Copyright (C) 2015 Imre Kaloz - */ - -#include -#include -#include "armada-385.dtsi" - -/ { - model = "Linksys boards based on Armada 385"; - compatible = "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MiB */ - }; - - soc { - ranges = ; - }; - - usb3_1_phy: usb3_1-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&usb3_1_vbus>; - #phy-cells = <0>; - }; - - usb3_1_vbus: usb3_1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_1_vbus_pins>; - regulator-name = "usb3_1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&gpio_keys_pins>; - pinctrl-names = "default"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - button-reset { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&gpio_leds_pins>; - pinctrl-names = "default"; - - led-power { - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-sata { - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -&ahci0 { - status = "okay"; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -ð2 { - status = "okay"; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - expander0: pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,pca9635"; - reg = <0x68>; - }; -}; - -&nand_controller { - /* 128MiB or 256MiB */ - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - nand: nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - marvell,nand-keep-config; - nand-on-flash-bbt; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - phy-mode = "sgmii"; - ethernet = <ð2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; -}; - -&pcie2 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; -}; - -&pinctrl { - gpio_keys_pins: gpio-keys-pins { - /* mpp24: wps, mpp29: reset */ - marvell,pins = "mpp24", "mpp29"; - marvell,function = "gpio"; - }; - - gpio_leds_pins: gpio-leds-pins { - /* mpp54: sata, mpp55: power */ - marvell,pins = "mpp54", "mpp55"; - marvell,function = "gpio"; - }; - - usb3_1_vbus_pins: usb3_1-vbus-pins { - marvell,pins = "mpp50"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "disabled"; -}; - -&uart0 { - /* J10: VCC, NC, RX, NC, TX, GND */ - status = "okay"; -}; - -&usb0 { - /* USB part of the eSATA/USB 2.0 port */ - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - usb-phy = <&usb3_1_phy>; -}; - -&rtc { - /* No crystal connected to the internal RTC */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts deleted file mode 100644 index ea91ff964d94..000000000000 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Synology DS116 NAS - * - * Copyright (C) 2017 Willy Tarreau - */ - -/dts-v1/; -#include "armada-385.dtsi" -#include - -/ { - model = "Synology DS116"; - compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - serial@12100 { - /* A PIC16F1829 is connected to uart1 at 9600 bps, - * and takes single-character orders : - * "1" : power off // already handled by the poweroff node - * "2" : short beep - * "3" : long beep - * "4" : turn the power LED ON - * "5" : flash the power LED - * "6" : turn the power LED OFF - * "7" : turn the status LED OFF - * "8" : turn the status LED ON - * "9" : flash the status LED - * "A" : flash the motherboard LED (D8) - * "B" : turn the motherboard LED OFF - * "C" : hard reset - */ - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - ethernet@70000 { - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - status = "okay"; - }; - - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata0>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - usb3@f0000 { - usb-phy = <&usb3_0_phy>; - status = "okay"; - }; - - usb3@f8000 { - usb-phy = <&usb3_1_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>, - <&gpio1 17 GPIO_ACTIVE_HIGH>, - <&gpio1 16 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1500 1 - 2500 2 - 3000 3 - 3400 4 - 3700 5 - 3900 6 - 4000 7>; - #cooling-cells = <2>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - /* The green part is on gpio0.20 which is also used by - * sata0, and accesses to SATA disk 0 make it blink so it - * doesn't need to be declared here. - */ - led-orange { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - label = "ds116:orange:disk"; - default-state = "off"; - }; - }; - }; - - usb3_0_phy: usb3_0_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_0_vbus>; - #phy-cells = <0>; - }; - - usb3_1_phy: usb3_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_1_vbus>; - #phy-cells = <0>; - }; - - reg_usb3_0_vbus: usb3-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus0"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_usb3_1_vbus: usb3-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus1"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci1_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata0>; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "macronix,mx25l6405d", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - - /* Note: there is a redboot partition table despite u-boot - * being used. The names presented here are the same as those - * found in the FIS directory. There is also a small device - * tree in the last 64kB of the RedBoot partition which is not - * enumerated. The MAC address and the serial number are listed - * in the "vendor" partition. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x000f0000>; - read-only; - }; - - partition@c0000 { - label = "zImage"; - reg = <0x000f0000 0x002d0000>; - }; - - partition@390000 { - label = "rd.gz"; - reg = <0x003c0000 0x00410000>; - }; - - partition@7d0000 { - label = "vendor"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; - read-only; - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&pinctrl { - /* use only one pin for UART1, as mpp20 is used by sata0 */ - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "ua1"; - }; - - xhci0_vbus_pins: xhci0_vbus_pins { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - xhci1_vbus_pins: xhci1_vbus_pins { - marvell,pins = "mpp59"; - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts deleted file mode 100644 index 2d8d319bec83..000000000000 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ /dev/null @@ -1,571 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Turris Omnia - * - * Copyright (C) 2016 Uwe Kleine-König - * Copyright (C) 2016 Tomas Hlavacek - * - * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf - */ - -/dts-v1/; - -#include -#include -#include -#include "armada-385.dtsi" - -/ { - model = "Turris Omnia"; - compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = &uart0; - }; - - aliases { - ethernet0 = ð0; - ethernet1 = ð1; - ethernet2 = ð2; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1024 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* USB part of the PCIe2/USB 2.0 port */ - usb@58000 { - status = "okay"; - }; - - sata@a8000 { - status = "okay"; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - status = "okay"; - - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - slot-power-limit-milliwatt = <10000>; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - slot-power-limit-milliwatt = <10000>; - }; - - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - slot-power-limit-milliwatt = <10000>; - }; - }; - }; - - sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&sfp_i2c>; - tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>; - los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - - /* - * For now this has to be enabled at boot time by U-Boot when - * a SFP module is present. Read more in the comment in the - * eth2 node below. - */ - status = "disabled"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&audio_controller 1>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&audio_controller { - /* Pin header U16, GPIO51 in SPDIFO mode */ - pinctrl-0 = <&spdif_pins>; - pinctrl-names = "default"; - spdif-mode; - status = "okay"; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -/* Connected to 88E6176 switch, port 6 */ -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&ge0_rgmii_pins>; - status = "okay"; - phy-mode = "rgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <3>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -/* Connected to 88E6176 switch, port 5 */ -ð1 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy-mode = "rgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - bm,pool-short = <3>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -/* WAN port */ -ð2 { - /* - * eth2 is connected via a multiplexor to both the SFP cage and to - * ethernet-phy@1. The multiplexor switches the signal to SFP cage when - * a SFP module is present, as determined by the mode-def0 GPIO. - * - * Until kernel supports this configuration properly, in case SFP module - * is present, U-Boot has to enable the sfp node above, remove phy - * handle and add managed = "in-band-status" property. - */ - status = "okay"; - phy-mode = "sgmii"; - phy-handle = <&phy1>; - phys = <&comphy5 2>; - sfp = <&sfp>; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - label = "wan"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - i2cmux@70 { - compatible = "nxp,pca9547"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - /* STM32F0 command interface at address 0x2a */ - - led-controller@2b { - compatible = "cznic,turris-omnia-leds"; - reg = <0x2b>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* - * LEDs are controlled by MCU (STM32F0) at - * address 0x2b. - * - * LED functions are not stable yet: - * - there are 3 LEDs connected via MCU to PCIe - * ports. One of these ports supports mSATA. - * There is no mSATA nor PCIe function. - * For now we use LED_FUNCTION_WLAN, since - * in most cases users have wifi cards in - * these slots - * - there are 2 LEDs dedicated for user: A and - * B. Again there is no such function defined. - * For now we use LED_FUNCTION_INDICATOR - */ - - multi-led@0 { - reg = <0x0>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - multi-led@1 { - reg = <0x1>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - multi-led@2 { - reg = <0x2>; - color = ; - function = LED_FUNCTION_WLAN; - function-enumerator = <3>; - }; - - multi-led@3 { - reg = <0x3>; - color = ; - function = LED_FUNCTION_WLAN; - function-enumerator = <2>; - }; - - multi-led@4 { - reg = <0x4>; - color = ; - function = LED_FUNCTION_WLAN; - function-enumerator = <1>; - }; - - multi-led@5 { - reg = <0x5>; - color = ; - function = LED_FUNCTION_WAN; - }; - - multi-led@6 { - reg = <0x6>; - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <4>; - }; - - multi-led@7 { - reg = <0x7>; - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <3>; - }; - - multi-led@8 { - reg = <0x8>; - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <2>; - }; - - multi-led@9 { - reg = <0x9>; - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <1>; - }; - - multi-led@a { - reg = <0xa>; - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <0>; - }; - - multi-led@b { - reg = <0xb>; - color = ; - function = LED_FUNCTION_POWER; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - - /* The EEPROM contains data for bootloader. - * Contents: - * struct omnia_eeprom { - * u32 magic; (=0x0341a034 in LE) - * u32 ramsize; (in GiB) - * char regdomain[4]; - * u32 crc32; - * }; - */ - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - /* routed to PCIe0/mSATA connector (CN7A) */ - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - /* routed to PCIe1/USB2 connector (CN61A) */ - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - /* routed to PCIe2 connector (CN62A) */ - }; - - sfp_i2c: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - /* routed to SFP+ */ - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - /* ATSHA204A-MAHDA-T crypto module */ - crypto@64 { - compatible = "atmel,atsha204a"; - reg = <0x64>; - }; - }; - - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - /* exposed on pin header */ - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - pcawan: gpio@71 { - /* - * GPIO expander for SFP+ signals and - * and phy irq - */ - compatible = "nxp,pca9538"; - reg = <0x71>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcawan_pins>; - - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - marvell,reg-init = <3 18 0 0x4985>, - <3 16 0xfff0 0x0001>; - - /* irq is connected to &pcawan pin 7 */ - }; - - /* Switch MV88E6176 at address 0x10 */ - switch@10 { - pinctrl-names = "default"; - pinctrl-0 = <&swint_pins>; - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - - dsa,member = <0 0>; - reg = <0x10>; - - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - ports@0 { - reg = <0>; - label = "lan0"; - }; - - ports@1 { - reg = <1>; - label = "lan1"; - }; - - ports@2 { - reg = <2>; - label = "lan2"; - }; - - ports@3 { - reg = <3>; - label = "lan3"; - }; - - ports@4 { - reg = <4>; - label = "lan4"; - }; - - ports@5 { - reg = <5>; - ethernet = <ð1>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ports@6 { - reg = <6>; - ethernet = <ð0>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&pinctrl { - pcawan_pins: pcawan-pins { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - swint_pins: swint-pins { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - spi0cs0_pins: spi0cs0-pins { - marvell,pins = "mpp25"; - marvell,function = "spi0"; - }; - - spi0cs2_pins: spi0cs2-pins { - marvell,pins = "mpp26"; - marvell,function = "spi0"; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins &spi0cs0_pins>; - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl164k", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x00100000>; - label = "U-Boot"; - }; - - partition@100000 { - reg = <0x00100000 0x00700000>; - label = "Rescue system"; - }; - }; - }; - - /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ -}; - -&uart0 { - /* Pin header CN10 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - /* Pin header CN11 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi deleted file mode 100644 index be8d607c59b2..000000000000 --- a/arch/arm/boot/dts/armada-385.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 385 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 385 family SoC"; - compatible = "marvell,armada385", "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - soc { - pciec: pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie4_intc 0>, - <0 0 0 2 &pcie4_intc 1>, - <0 0 0 3 &pcie4_intc 2>, - <0 0 0 4 &pcie4_intc 3>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - pcie4_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv88f6820-pinctrl"; -}; diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts deleted file mode 100644 index f7daa3bc707e..000000000000 --- a/arch/arm/boot/dts/armada-388-clearfog-base.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - */ - -/dts-v1/; -#include "armada-388-clearfog.dtsi" - -/ { - model = "SolidRun Clearfog Base A1"; - compatible = "solidrun,clearfog-base-a1", - "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&rear_button_pins>; - pinctrl-names = "default"; - - button-0 { - /* The rear SW3 button */ - label = "Rear Button"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -ð1 { - phy = <&phy1>; -}; - -&gpio0 { - phy1_reset { - gpio-hog; - gpios = <19 GPIO_ACTIVE_LOW>; - output-low; - line-name = "phy1-reset"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>; - phy1: ethernet-phy@1 { - /* - * Annoyingly, the marvell phy driver configures the LED - * register, rather than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <1>; - }; -}; - -&pinctrl { - /* phy1 reset */ - clearfog_phy_pins: clearfog-phy-pins { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - rear_button_pins: rear-button-pins { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/armada-388-clearfog-pro.dts deleted file mode 100644 index ff890c09c3ed..000000000000 --- a/arch/arm/boot/dts/armada-388-clearfog-pro.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - */ -#include "armada-388-clearfog.dts" - -/ { - model = "SolidRun Clearfog Pro A1"; - compatible = "solidrun,clearfog-pro-a1", - "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; -}; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts deleted file mode 100644 index 32c569df142f..000000000000 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - */ - -/dts-v1/; -#include "armada-388-clearfog.dtsi" - -/ { - model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - soc { - internal-regs { - usb3@f0000 { - /* CON2, nearest CPU, USB2 only. */ - status = "okay"; - }; - }; - - pcie { - pcie@3,0 { - /* Port 2, Lane 0. CON2, nearest CPU. */ - reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&rear_button_pins>; - pinctrl-names = "default"; - - button-0 { - /* The rear SW3 button */ - label = "Rear Button"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -ð1 { - /* ethernet@30000 */ - phy-mode = "1000base-x"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&expander0 { - /* - * PCA9655 GPIO expander: - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2-CON2 PERST# - * 3-CON3 W_DISABLE - * 4-CON2 CLKREQ# - * 5-USB3 overcurrent - * 6-USB3 power - * 7-CON2 W_DISABLE - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - pcie2-0-clkreq-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie2.0-clkreq"; - }; - pcie2-0-w-disable-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie2.0-w-disable"; - }; -}; - -&mdio { - status = "okay"; - - switch@4 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; - pinctrl-names = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - ethernet = <ð1>; - phy-mode = "1000base-x"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&pinctrl { - clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - clearfog_dsa0_pins: clearfog-dsa0-pins { - marvell,pins = "mpp23", "mpp41"; - marvell,function = "gpio"; - }; - clearfog_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp55"; - marvell,function = "spi1"; - }; - rear_button_pins: rear-button-pins { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; -}; - -&spi1 { - /* - * Add SPI CS pins for clearfog: - * CS0: W25Q32 - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; -}; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi deleted file mode 100644 index f8a06ae4a3c9..000000000000 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree include file for SolidRun Clearfog 88F6828 based boards - * - * Copyright (C) 2015 Russell King - */ - -#include "armada-388.dtsi" -#include "armada-38x-solidrun-microsom.dtsi" - -/ { - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - ethernet2 = ð1; - ethernet3 = ð2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - soc { - internal-regs { - sata@a8000 { - /* pinctrl? */ - status = "okay"; - }; - - sata@e0000 { - /* pinctrl? */ - status = "okay"; - }; - - sdhci@d8000 { - bus-width = <4>; - cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-0 = <µsom_sdhci_pins - &clearfog_sdhci_cd_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc-supply = <®_3p3v>; - wp-inverted; - }; - - usb@58000 { - /* CON3, nearest power. */ - status = "okay"; - }; - - usb3@f8000 { - /* CON7 */ - status = "okay"; - }; - }; - - pcie { - status = "okay"; - /* - * The two PCIe units are accessible through - * the mini-PCIe connectors on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0. CON3, nearest power. */ - reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; -}; - -ð1 { - /* ethernet@30000 */ - bm,pool-long = <2>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - phys = <&comphy1 1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -ð2 { - /* ethernet@34000 */ - bm,pool-long = <3>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - managed = "in-band-status"; - phys = <&comphy5 2>; - phy-mode = "sgmii"; - sfp = <&sfp>; - status = "okay"; -}; - -&i2c0 { - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2- - * 3-CON3 W_DISABLE - * 4- - * 5-USB3 overcurrent - * 6-USB3 power - * 7- - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - expander0: gpio-expander@20 { - /* - * This is how it should be: - * compatible = "onnn,pca9655", "nxp,pca9555"; - * but you can't do this because of the way I2C works. - */ - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - pcie1-0-clkreq-hog { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie1.0-clkreq"; - }; - pcie1-0-w-disable-hog { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie1.0-w-disable"; - }; - usb3-ilimit-hog { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - input; - line-name = "usb3-current-limit"; - }; - usb3-power-hog { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb3-power"; - }; - m2-devslp-hog { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "m.2 devslp"; - }; - }; - - /* The MCP3021 supports standard and fast modes */ - mikrobus_adc: mcp3021@4c { - compatible = "microchip,mcp3021"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; -}; - -&i2c1 { - /* - * Routed to SFP, mikrobus, and PCIe. - * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with - * address pins tied low, which takes addresses 0x50 and 0x51. - * Mikrobus doesn't specify beyond an I2C bus being present. - * PCIe uses ARP to assign addresses, or 0x63-0x64. - */ - clock-frequency = <100000>; - pinctrl-0 = <&clearfog_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pinctrl { - clearfog_i2c1_pins: i2c1-pins { - /* SFP, PCIe, mSATA, mikrobus */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - mikro_pins: mikro-pins { - /* int: mpp22 rst: mpp29 */ - marvell,pins = "mpp22", "mpp29"; - marvell,function = "gpio"; - }; - mikro_spi_pins: mikro-spi-pins { - marvell,pins = "mpp43"; - marvell,function = "spi1"; - }; - mikro_uart_pins: mikro-uart-pins { - marvell,pins = "mpp24", "mpp25"; - marvell,function = "ua1"; - }; -}; - -&spi1 { - /* - * Add SPI CS pins for clearfog: - * CS0: W25Q32 - * CS1: PIC microcontroller (Pro models) - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - /* mikrobus uart */ - pinctrl-0 = <&mikro_uart_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts deleted file mode 100644 index 45cc784659fd..000000000000 --- a/arch/arm/boot/dts/armada-388-db.dts +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 388 evaluation board - * (DB-88F6820) - * - * Copyright (C) 2014 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include "armada-388.dtsi" - -/ { - model = "Marvell Armada 385 Development Board"; - compatible = "marvell,a385-db", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - audio_codec: audio-codec@4a { - #sound-dai-cells = <0>; - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - - i2c@11100 { - status = "okay"; - clock-frequency = <100000>; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - usb@58000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - }; - - mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - status = "okay"; - }; - - sata@e0000 { - status = "okay"; - }; - - bm@c8000 { - status = "okay"; - }; - - sdhci@d8000 { - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - no-1-8-v; - }; - - audio-controller@e8000 { - pinctrl-0 = <&i2s_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie { - status = "okay"; - /* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Armada 385 DB Audio"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Headphone", "Out Jack", - "Line", "In Jack"; - simple-audio-card,routing = - "Out Jack", "HPL", - "Out Jack", "HPR", - "AIN1L", "In Jack", - "AIN1R", "In Jack"; - status = "disabled"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 0>; - }; - - codec { - sound-dai = <&audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_out>; - }; - }; - - simple-audio-card,dai-link@2 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_in>; - }; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - spdif_in: spdif-in { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts deleted file mode 100644 index e2ba50520b6b..000000000000 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 385 development board - * (RD-88F6820-GP) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - */ - -/dts-v1/; -#include "armada-388.dtsi" -#include - -/ { - model = "Marvell Armada 388 DB-88F6820-GP"; - compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - expander0: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca0_pins>; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - - expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x21>; - }; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON16 - * through an FTDI - */ - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - /* GE1 CON15 */ - ethernet@30000 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - /* CON4 */ - usb@58000 { - vcc-supply = <®_usb2_0_vbus>; - status = "okay"; - }; - - /* GE0 CON1 */ - ethernet@70000 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - }; - - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>, <&sata1_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata0>; - }; - - sata1: sata-port@1 { - reg = <1>; - target-supply = <®_5v_sata1>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - sata@e0000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata2_pins>, <&sata3_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata2: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata2>; - }; - - sata3: sata-port@1 { - reg = <1>; - target-supply = <®_5v_sata3>; - }; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - /* - * A388-GP board v1.5 and higher replace - * hitherto card detection method based on GPIO - * with the one using DAT3 pin. As they are - * incompatible, software-based polling is - * enabled with 'broken-cd' property. For boards - * older than v1.5 it can be replaced with: - * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', - * whereas for the newer ones following can be - * used instead: - * 'dat3-cd;' - * 'cd-inverted;' - */ - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - /* CON5 */ - usb3@f0000 { - usb-phy = <&usb2_1_phy>; - status = "okay"; - }; - - /* CON7 */ - usb3@f8000 { - usb-phy = <&usb3_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * The two other PCIe units are accessible - * through mini PCIe slot on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 3000 1>; - }; - }; - - usb2_1_phy: usb2_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb2_1_vbus>; - #phy-cells = <0>; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_vbus>; - #phy-cells = <0>; - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_0_vbus: v5-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-vbus0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_1_vbus: v5-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata0>; - }; - - reg_sata1: pwr-sata1 { - regulator-name = "pwr_en_sata1"; - compatible = "regulator-fixed"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata1: v5-sata1 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata1>; - }; - - reg_12v_sata1: v12-sata1 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata1>; - }; - - reg_sata2: pwr-sata2 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata2"; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata2: v5-sata2 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata2>; - }; - - reg_12v_sata2: v12-sata2 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata2"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata2>; - }; - - reg_sata3: pwr-sata3 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata3"; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata3: v5-sata3 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata3>; - }; - - reg_12v_sata3: v12-sata3 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata3"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata3>; - }; -}; - -&pinctrl { - pca0_pins: pca0_pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; -}; diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts deleted file mode 100644 index ec134e22bae3..000000000000 --- a/arch/arm/boot/dts/armada-388-helios4.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Helios4 - * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2017 Aditya Prayoga - * - */ - -/dts-v1/; -#include "armada-388.dtsi" -#include "armada-38x-solidrun-microsom.dtsi" - -/ { - model = "Helios4"; - compatible = "kobol,helios4", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_12v: regulator-12v { - compatible = "regulator-fixed"; - regulator-name = "power_brick_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_12v>; - }; - - reg_5p0v_hdd: regulator-5v-hdd { - compatible = "regulator-fixed"; - regulator-name = "5V_HDD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <®_12v>; - }; - - reg_5p0v_usb: regulator-5v-usb { - compatible = "regulator-fixed"; - regulator-name = "USB-PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_12v>; - }; - - system-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&helios_system_led_pins>; - - status-led { - label = "helios4:green:status"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - fault-led { - label = "helios4:red:fault"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - io-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&helios_io_led_pins>; - - sata1-led { - label = "helios4:green:ata1"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata1"; - default-state = "off"; - }; - sata2-led { - label = "helios4:green:ata2"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata2"; - default-state = "off"; - }; - sata3-led { - label = "helios4:green:ata3"; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata3"; - default-state = "off"; - }; - sata4-led { - label = "helios4:green:ata4"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata4"; - default-state = "off"; - }; - usb-led { - label = "helios4:green:usb"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usb-host"; - default-state = "off"; - }; - }; - - fan1: j10-pwm { - compatible = "pwm-fan"; - pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ - pinctrl-names = "default"; - pinctrl-0 = <&helios_fan1_pins>; - }; - - fan2: j17-pwm { - compatible = "pwm-fan"; - pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ - pinctrl-names = "default"; - pinctrl-0 = <&helios_fan2_pins>; - }; - - usb2_phy: usb2-phy { - compatible = "usb-nop-xceiv"; - vbus-regulator = <®_5p0v_usb>; - }; - - usb3_phy: usb3-phy { - compatible = "usb-nop-xceiv"; - }; - - soc { - internal-regs { - i2c@11000 { - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-Board Revision bit 0 # - * 1-Board Revision bit 1 # - * 5-USB3 overcurrent - * 6-USB3 power - */ - expander0: gpio-expander@20 { - /* - * This is how it should be: - * compatible = "onnn,pca9655", - * "nxp,pca9555"; - * but you can't do this because of - * the way I2C works. - */ - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pca0_pins>; - interrupt-parent = <&gpio0>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - board-rev-bit-0-hog { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "board-rev-0"; - }; - board-rev-bit-1-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - input; - line-name = "board-rev-1"; - }; - usb3-ilimit-hog { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - input; - line-name = "usb-overcurrent-status"; - }; - }; - - temp_sensor: temp@4c { - compatible = "ti,lm75"; - reg = <0x4c>; - vcc-supply = <®_3p3v>; - }; - }; - - i2c@11100 { - /* - * External I2C Bus for user peripheral - */ - clock-frequency = <400000>; - pinctrl-0 = <&helios_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - sata@a8000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - }; - - sata1: sata-port@1 { - reg = <1>; - }; - }; - - sata@e0000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata2: sata-port@0 { - reg = <0>; - }; - - sata3: sata-port@1 { - reg = <1>; - }; - }; - - spi@10680 { - pinctrl-0 = <&spi1_pins - µsom_spi1_cs_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - sdhci@d8000 { - bus-width = <4>; - cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-0 = <&helios_sdhci_pins - &helios_sdhci_cd_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc = <®_3p3v>; - wp-inverted; - }; - - usb@58000 { - usb-phy = <&usb2_phy>; - status = "okay"; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - - pinctrl@18000 { - pca0_pins: pca0-pins { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - microsom_phy0_int_pins: microsom-phy0-int-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - helios_i2c1_pins: i2c1-pins { - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - helios_sdhci_cd_pins: helios-sdhci-cd-pins { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - helios_sdhci_pins: helios-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - helios_system_led_pins: helios-system-led-pins { - marvell,pins = "mpp24", "mpp25"; - marvell,function = "gpio"; - }; - helios_io_led_pins: helios-io-led-pins { - marvell,pins = "mpp49", "mpp50", - "mpp52", "mpp53", - "mpp54"; - marvell,function = "gpio"; - }; - helios_fan1_pins: helios_fan1_pins { - marvell,pins = "mpp41", "mpp43"; - marvell,function = "gpio"; - }; - helios_fan2_pins: helios_fan2_pins { - marvell,pins = "mpp48", "mpp55"; - marvell,function = "gpio"; - }; - microsom_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp59"; - marvell,function = "spi1"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts deleted file mode 100644 index c0efafd45b33..000000000000 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 388 Reference Design board - * (RD-88F6820-AP) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - */ - -/dts-v1/; -#include "armada-388.dtsi" - -/ { - model = "Marvell Armada 385 Reference Design"; - compatible = "marvell,a385-rd", "marvell,armada388", - "marvell,armada385","marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - broken-cd; - no-1-8-v; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - - mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - usb3@f0000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi deleted file mode 100644 index f3a020ff577e..000000000000 --- a/arch/arm/boot/dts/armada-388.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 388 SoC. - * - * Copyright (C) 2015 Marvell - * - * Gregory CLEMENT - * - * The main difference with the Armada 385 is that the 388 can handle two more - * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl - * property and the name of the SoC, and add the second SATA host which control - * the 2 other ports. - */ - -#include "armada-385.dtsi" - -/ { - model = "Marvell Armada 388 family SoC"; - compatible = "marvell,armada388", "marvell,armada385", - "marvell,armada380"; - soc { - internal-regs { - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv88f6828-pinctrl"; -}; diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi deleted file mode 100644 index 2c64bc6e5a17..000000000000 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Armada 38x Microsom - * - * Copyright (C) 2015 Russell King - */ -#include -#include - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - rtc@a3800 { - /* - * If the rtc doesn't work, run "date reset" - * twice in u-boot. - */ - status = "okay"; - }; - }; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - /* ethernet@70000 */ - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy_dedicated>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - status = "okay"; -}; - -&mdio { - /* - * Add the phy clock here, so the phy can be accessed to read its - * IDs prior to binding with the driver. - */ - pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; - pinctrl-names = "default"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver configures the LED - * register, rather than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <0>; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&pinctrl { - microsom_phy_clk_pins: microsom-phy-clk-pins { - marvell,pins = "mpp45"; - marvell,function = "ref"; - }; - /* Optional eMMC */ - microsom_sdhci_pins: microsom-sdhci-pins { - marvell,pins = "mpp21", "mpp28", "mpp37", - "mpp38", "mpp39", "mpp40"; - marvell,function = "sd0"; - }; -}; - -&spi1 { - /* The microsom has an optional W25Q32 on board, connected to CS0 */ - pinctrl-0 = <&spi1_pins>; - - w25q32: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi deleted file mode 100644 index 446861b6b17b..000000000000 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 38x family of SoCs. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Marvell Armada 38x family SoC"; - compatible = "marvell,armada380"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - serial0 = &uart0; - serial1 = &uart1; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada380-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs3: devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - sdramc: sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x58>; - }; - - timer@c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xc200 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "marvell,armada-38x-uart", "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "marvell,armada-38x-uart", "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pinctrl@18000 { - reg = <0x18000 0x20>; - - ge0_rgmii_pins: ge-rgmii-pins-0 { - marvell,pins = "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge-rgmii-pins-1 { - marvell,pins = "mpp21", "mpp27", "mpp28", - "mpp29", "mpp30", "mpp31", - "mpp32", "mpp37", "mpp38", - "mpp39", "mpp40", "mpp41"; - marvell,function = "ge1"; - }; - - i2c0_pins: i2c-pins-0 { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - mdio_pins: mdio-pins { - marvell,pins = "mpp4", "mpp5"; - marvell,function = "ge"; - }; - - ref_clk0_pins: ref-clk-pins-0 { - marvell,pins = "mpp45"; - marvell,function = "ref"; - }; - - ref_clk1_pins: ref-clk-pins-1 { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - - spi0_pins: spi-pins-0 { - marvell,pins = "mpp22", "mpp23", "mpp24", - "mpp25"; - marvell,function = "spi0"; - }; - - spi1_pins: spi-pins-1 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59"; - marvell,function = "spi1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", - "mpp33", "mpp38", "mpp28", - "mpp40", "mpp42", "mpp35", - "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp41"; - marvell,function = "nand"; - }; - - uart0_pins: uart-pins-0 { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "ua0"; - }; - - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19", "mpp20"; - marvell,function = "ua1"; - }; - - sdhci_pins: sdhci-pins { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp52", "mpp53", "mpp54", - "mpp55", "mpp57", "mpp58", - "mpp59"; - marvell,function = "sd0"; - }; - - sata0_pins: sata-pins-0 { - marvell,pins = "mpp20"; - marvell,function = "sata0"; - }; - - sata1_pins: sata-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "sata1"; - }; - - sata2_pins: sata-pins-2 { - marvell,pins = "mpp47"; - marvell,function = "sata2"; - }; - - sata3_pins: sata-pins-3 { - marvell,pins = "mpp44"; - marvell,function = "sata3"; - }; - - i2s_pins: i2s-pins { - marvell,pins = "mpp48", "mpp49", - "mpp50", "mpp51", - "mpp52", "mpp53"; - marvell,function = "audio"; - }; - - spdif_pins: spdif-pins { - marvell,pins = "mpp51"; - marvell,function = "audio"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <28>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 28>; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - clocks = <&coreclk 0>; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-380-system-controller", - "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-380-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - comphy: phy@18300 { - compatible = "marvell,armada-380-comphy"; - reg-names = "comphy", "conf"; - reg = <0x18300 0x100>, <0x18460 4>; - #address-cells = <1>; - #size-cells = <0>; - - comphy0: phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - comphy1: phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - - comphy2: phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - - comphy3: phy@3 { - reg = <3>; - #phy-cells = <1>; - }; - - comphy4: phy@4 { - reg = <4>; - #phy-cells = <1>; - }; - - comphy5: phy@5 { - reg = <5>; - #phy-cells = <1>; - }; - }; - - coreclk: mvebu-sar@18600 { - compatible = "marvell,armada-380-core-clock"; - reg = <0x18600 0x04>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, - <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer: timer@20300 { - compatible = "marvell,armada-380-timer", - "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog: watchdog@20300 { - compatible = "marvell,armada-380-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - - cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; - }; - - coherencyfab: coherency-fabric@21010 { - compatible = "marvell,armada-380-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - pmsu: pmsu@22000 { - compatible = "marvell,armada-380-pmsu"; - reg = <0x22000 0x1000>; - }; - - /* - * As a special exception to the "order by - * register address" rule, the eth0 node is - * placed here to ensure that it gets - * registered as the first interface, since - * the network subsystem doesn't allow naming - * interfaces using DT aliases. Without this, - * the ordering of interfaces is different - * from the one used in U-Boot and the - * labeling of interfaces on the boards, which - * is very confusing for users. - */ - eth0: ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x4000>; - interrupts-extended = <&mpic 8>; - clocks = <&gateclk 4>; - tx-csum-limit = <9800>; - status = "disabled"; - }; - - eth1: ethernet@30000 { - compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x4000>; - interrupts-extended = <&mpic 10>; - clocks = <&gateclk 3>; - status = "disabled"; - }; - - eth2: ethernet@34000 { - compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x4000>; - interrupts-extended = <&mpic 12>; - clocks = <&gateclk 2>; - status = "disabled"; - }; - - usb0: usb@58000 { - compatible = "marvell,orion-ehci"; - reg = <0x58000 0x500>; - interrupts = ; - clocks = <&gateclk 18>; - status = "disabled"; - }; - - xor0: xor@60800 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor1: xor@60900 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - mdio: mdio@72004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; - clocks = <&gateclk 4>; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-38x-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = , - ; - clocks = <&gateclk 23>, <&gateclk 21>, - <&gateclk 14>, <&gateclk 16>; - clock-names = "cesa0", "cesa1", - "cesaz0", "cesaz1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - rtc: rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; - }; - - ahci0: sata@a8000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xa8000 0x2000>; - interrupts = ; - clocks = <&gateclk 15>; - status = "disabled"; - }; - - bm: bm@c8000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc8000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - status = "disabled"; - }; - - ahci1: sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - - coredivclk: clock@e4250 { - compatible = "marvell,armada-380-corediv-clock"; - reg = <0xe4250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - thermal: thermal@e8078 { - compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4070 0x8>; - status = "okay"; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdhci: sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>, - <0x18454 0x4>; - interrupts = ; - clocks = <&gateclk 17>; - mrvl,clk-delay-cycles = <0x1F>; - status = "disabled"; - }; - - audio_controller: audio-controller@e8000 { - #sound-dai-cells = <1>; - compatible = "marvell,armada-380-audio"; - reg = <0xe8000 0x4000>, <0x18410 0xc>, - <0x18204 0x4>; - reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; - interrupts = ; - clocks = <&gateclk 0>; - clock-names = "internal"; - status = "disabled"; - }; - - usb3_0: usb3@f0000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf0000 0x4000>,<0xf4000 0x4000>; - interrupts = ; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - usb3_1: usb3@f8000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf8000 0x4000>,<0xfc000 0x4000>; - interrupts = ; - clocks = <&gateclk 10>; - status = "disabled"; - }; - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 21>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; - }; - - bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; - no-memory-wc; - status = "disabled"; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 1 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts deleted file mode 100644 index 792d0a0184e8..000000000000 --- a/arch/arm/boot/dts/armada-390-db.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 390 Development Board - * (DB-88F6920) - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - */ - -/dts-v1/; -#include "armada-390.dtsi" - -/ { - model = "Marvell Armada 390 Development Board"; - compatible = "marvell,a390-db", "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - /* CON104 */ - serial@12000 { - status = "okay"; - }; - - /* CON97 */ - usb@58000 { - status = "okay"; - }; - - /* CON98 */ - usb3@f8000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - /* CON30 */ - pcie@1,0 { - status = "okay"; - }; - - /* CON44 */ - pcie@2,0 { - status = "okay"; - }; - - /* CON61 */ - pcie@3,0 { - status = "okay"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", - "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0xc00000>; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi deleted file mode 100644 index aa2057d4d6f8..000000000000 --- a/arch/arm/boot/dts/armada-390.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 390 SoC. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -#include "armada-39x.dtsi" - -/ { - compatible = "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6920-pinctrl"; - reg = <0x18000 0x20>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/armada-395-gp.dts deleted file mode 100644 index 6dd9e9077f84..000000000000 --- a/arch/arm/boot/dts/armada-395-gp.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 395 GP board - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - */ - -/dts-v1/; -#include "armada-395.dtsi" - -/ { - model = "Marvell Armada 395 GP Board"; - compatible = "marvell,a395-gp", "marvell,armada395", - "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON17 - * through an FTDI - */ - status = "okay"; - }; - - /* CON1 */ - usb@58000 { - status = "okay"; - }; - - /* CON2 */ - sata@a8000 { - status = "okay"; - }; - - /* CON18 */ - sdhci@d8000 { - clock-frequency = <200000000>; - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - no-1-8-v; - }; - - /* CON4 */ - usb3@f0000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - /* - * The two PCIe units are accessible through - * mini PCIe slot on the board. - */ - - /* CON7 */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - /* CON8 */ - pcie@4,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x00000000 0x00600000>; - read-only; - }; - - partition@800000 { - label = "uImage"; - reg = <0x00600000 0x00400000>; - read-only; - }; - - partition@1000000 { - label = "Root"; - reg = <0x00a00000 0x3f600000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-395.dtsi b/arch/arm/boot/dts/armada-395.dtsi deleted file mode 100644 index e18a7d9cd7d4..000000000000 --- a/arch/arm/boot/dts/armada-395.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 395 SoC. - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - */ - -#include "armada-39x.dtsi" - -/ { - compatible = "marvell,armada395", "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6925-pinctrl"; - reg = <0x18000 0x20>; - }; - - sata@a8000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xa8000 0x2000>; - interrupts = ; - clocks = <&gateclk 15>; - status = "disabled"; - }; - - usb3@f0000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf0000 0x4000>,<0xf4000 0x4000>; - interrupts = ; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts deleted file mode 100644 index ec6cdbeedde7..000000000000 --- a/arch/arm/boot/dts/armada-398-db.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 398 Development Board - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include "armada-398.dtsi" - -/ { - model = "Marvell Armada 398 Development Board"; - compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = <100000>; - }; - - serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - serial@12100 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - usb@58000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - - pcie@2,0 { - status = "okay"; - }; - - pcie@3,0 { - status = "okay"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0x1000000>; - }; - }; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi deleted file mode 100644 index c5ac89399ce1..000000000000 --- a/arch/arm/boot/dts/armada-398.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 398 SoC. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -#include "armada-395.dtsi" - -/ { - compatible = "marvell,armada398", "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6928-pinctrl"; - reg = <0x18000 0x20>; - }; - - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi deleted file mode 100644 index 9d1cac49c022..000000000000 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ /dev/null @@ -1,594 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 39x family of SoCs. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Marvell Armada 39x family SoC"; - compatible = "marvell,armada390"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-390-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", - "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x100>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c2: i2c@11200 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11200 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c3: i2c@11300 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11300 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "snps,dw-apb-uart"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "snps,dw-apb-uart"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl@18000 { - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - uart0_pins: uart0-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "ua0"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp19", "mpp20"; - marvell,function = "ua1"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; - marvell,function = "spi1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", - "mpp38", "mpp28", "mpp40", "mpp42", - "mpp35", "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <28>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - system-controller@18200 { - compatible = "marvell,armada-390-system-controller", - "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-390-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18600 { - compatible = "marvell,armada-390-core-clock"; - reg = <0x18600 0x04>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer@20300 { - compatible = "marvell,armada-380-timer", - "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 2>, <&coreclk 5>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-380-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, - <0x18260 0x4>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; - }; - - coherency-fabric@21010 { - compatible = "marvell,armada-380-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - pmsu@22000 { - compatible = "marvell,armada-390-pmsu", - "marvell,armada-380-pmsu"; - reg = <0x22000 0x1000>; - }; - - xor@60800 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor@60900 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>, - <0x18454 0x4>; - interrupts = ; - clocks = <&gateclk 17>; - mrvl,clk-delay-cycles = <0x1F>; - status = "disabled"; - }; - - coredivclk: clock@e4250 { - compatible = "marvell,armada-390-corediv-clock", - "marvell,armada-380-corediv-clock"; - reg = <0xe4250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - thermal@e8078 { - compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4074 0x4>; - status = "okay"; - }; - }; - - pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie4_intc 0>, - <0 0 0 2 &pcie4_intc 1>, - <0 0 0 3 &pcie4_intc 2>, - <0 0 0 4 &pcie4_intc 3>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - - pcie4_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 1 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi deleted file mode 100644 index 7a7e2066c498..000000000000 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell 98dx3236 family SoC - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Contains definitions specific to the 98dx3236 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <2>; - - model = "Marvell 98DX3236 SoC"; - compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,98dx3236-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - }; - - soc { - compatible = "marvell,armadaxp-mbus", "simple-bus"; - - ranges = ; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - /* - * 98DX3236 has 1 x1 PCIe unit Gen2.0 - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 58>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - sdramc: sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: l2-cache@8000 { - compatible = "marvell,aurora-system-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - - /* does not exist */ - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - status = "disabled"; - }; - - gpio2: gpio@18180 { /* rework some properties */ - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <1>; /* only gpio #32 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,mv98dx3236-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - cpuclk: clock-complex@18700 { - #clock-cells = <1>; - compatible = "marvell,mv98dx3236-cpu-clock"; - reg = <0x18700 0x24>, <0x1c054 0x10>; - clocks = <&coreclk 1>; - }; - - corediv-clock@18740 { - status = "disabled"; - }; - - cpu-config@21000 { - compatible = "marvell,armada-xp-cpu-config"; - reg = <0x21000 0x8>; - }; - - ethernet@70000 { - compatible = "marvell,armada-xp-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-xp-neta"; - }; - - xor1: xor@f0800 { - compatible = "marvell,orion-xor"; - reg = <0xf0800 0x100 - 0xf0a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor10 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - nand_controller: nand-controller@d0000 { - clocks = <&dfx_coredivclk 0>; - }; - - xor0: xor@f0900 { - compatible = "marvell,orion-xor"; - reg = <0xF0900 0x100 - 0xF0B00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor00 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - }; - - dfx: dfx-server@ac000000 { - compatible = "marvell,dfx-server", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; - reg = ; - - coreclk: mvebu-sar@f8204 { - compatible = "marvell,mv98dx3236-core-clock"; - reg = <0xf8204 0x4>; - #clock-cells = <1>; - }; - - dfx_coredivclk: corediv-clock@f8268 { - compatible = "marvell,mv98dx3236-corediv-clock"; - reg = <0xf8268 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - }; - - switch: switch@a8000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; - - pp0: packet-processor@0 { - compatible = "marvell,prestera-98dx3236", "marvell,prestera"; - reg = <0 0x4000000>; - interrupts = <33>, <34>, <35>; - dfx = <&dfx>; - }; - }; - }; - - clocks { - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; - -&i2c0 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -}; - -&mpic { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; -}; - -&rtc { - status = "disabled"; -}; - -&timer { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; -}; - -&watchdog { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - interrupts = <93>, <38>; -}; - -&cpurst { - reg = <0x20800 0x20>; -}; - -&usb0 { - clocks = <&gateclk 18>; -}; - -&usb1 { - clocks = <&gateclk 19>; -}; - -&pinctrl { - compatible = "marvell,98dx3236-pinctrl"; - - nand_pins: nand-pins { - marvell,pins = "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", - "mpp26", "mpp27", "mpp28", - "mpp29", "mpp30"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp19"; - marvell,function = "nand"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp0", "mpp1", - "mpp2", "mpp3"; - marvell,function = "spi0"; - }; - - i2c0_pins: i2c-pins-0 { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "i2c0"; - }; -}; - -&spi0 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; -}; - -&sdio { - status = "disabled"; -}; - -&uart0 { - compatible = "marvell,armada-38x-uart"; -}; - -&uart1 { - compatible = "marvell,armada-38x-uart"; -}; - diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi deleted file mode 100644 index 1d9d8a8ea60c..000000000000 --- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell 98dx3336 family SoC - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Contains definitions specific to the 98dx3236 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "Marvell 98DX3336 SoC"; - compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - internal-regs { - resume@20980 { - compatible = "marvell,98dx3336-resume-ctrl"; - reg = <0x20980 0x10>; - }; - }; - }; -}; - -&pp0 { - compatible = "marvell,prestera-98dx3336", "marvell,prestera"; -}; diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi deleted file mode 100644 index 48ffdc72bfc7..000000000000 --- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell 98dx4521 family SoC - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Contains definitions specific to the 98dx4521 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "Marvell 98DX4251 SoC"; - compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - internal-regs { - resume@20980 { - compatible = "marvell,98dx3336-resume-ctrl"; - reg = <0x20980 0x10>; - }; - }; - }; -}; - -&sdio { - status = "okay"; -}; - -&pinctrl { - compatible = "marvell,98dx4251-pinctrl"; - - sdio_pins: sdio-pins { - marvell,pins = "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10"; - marvell,function = "sd0"; - }; -}; - -&pp0 { - compatible = "marvell,prestera-98dx4251", "marvell,prestera"; - interrupts = <33>, <34>, <35>, <36>; -}; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts deleted file mode 100644 index 5a74197be0ad..000000000000 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell RD-AXPWiFiAP. - * - * Note: this board is shipped with a new generation boot loader that - * remaps internal registers at 0xf1000000. Therefore, if earlyprintk - * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the - * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. - * - * Copyright (C) 2013 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Marvell RD-AXPWiFiAP"; - compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - internal-regs { - /* UART0 */ - serial@12000 { - status = "okay"; - }; - - /* UART1 */ - serial@12100 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - button-reset { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&pciec { - status = "okay"; - - /* First mini-PCIe port */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Renesas uPD720202 USB 3.0 controller */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; -}; - -&pinctrl { - pinctrl-0 = <&phy_int_pin>; - pinctrl-names = "default"; - - keys_pin: keys-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - phy_int_pin: phy-int-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts deleted file mode 100644 index c28e140b4afc..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for MikroTik CRS305-1G-4S+ Bit board - * - * Copyright (C) 2020 Sartura Ltd. - * Author: Luka Kovacic - */ - -#include "armada-xp-crs305-1g-4s.dtsi" - -/ { - model = "MikroTik CRS305-1G-4S+ Bit"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x001f0000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x001f0000 0x00010000>; - label = "u-boot-env"; - }; - partition@ubi1 { - reg = <0x00200000 0x03f00000>; - label = "ubi1"; - }; - partition@ubi2 { - reg = <0x04100000 0x03f00000>; - label = "ubi2"; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts deleted file mode 100644 index 010b83b54212..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for MikroTik CRS305-1G-4S+ board - * - * Copyright (C) 2020 Sartura Ltd. - * Author: Luka Kovacic - */ - -#include "armada-xp-crs305-1g-4s.dtsi" - -/ { - model = "MikroTik CRS305-1G-4S+"; -}; - -&spi0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi deleted file mode 100644 index 47b003a81bd4..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for CRS305-1G-4S board - * - * Copyright (C) 2016 Allied Telesis Labs - * Copyright (C) 2020 Sartura Ltd. - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "CRS305-1G-4S+"; - compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ - }; -}; - -&L2 { - arm,parity-enable; - marvell,ecc-enable; -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x001f0000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x001f0000 0x00010000>; - label = "u-boot-env"; - }; - partition@ubi1 { - reg = <0x00200000 0x00e00000>; - label = "ubi1"; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts deleted file mode 100644 index 20ba5c823bb2..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for MikroTik CRS326-24G-2S+ Bit board - * - * Copyright (C) 2020 Sartura Ltd. - * Author: Luka Kovacic - */ - -#include "armada-xp-crs326-24g-2s.dtsi" - -/ { - model = "MikroTik CRS326-24G-2S+ Bit"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x001f0000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x001f0000 0x00010000>; - label = "u-boot-env"; - }; - partition@ubi1 { - reg = <0x00200000 0x03f00000>; - label = "ubi1"; - }; - partition@ubi2 { - reg = <0x04100000 0x03f00000>; - label = "ubi2"; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts deleted file mode 100644 index 83aef43f66d5..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for MikroTik CRS326-24G-2S+ board - * - * Copyright (C) 2020 Sartura Ltd. - * Author: Luka Kovacic - */ - -#include "armada-xp-crs326-24g-2s.dtsi" - -/ { - model = "MikroTik CRS326-24G-2S+"; -}; - -&spi0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi deleted file mode 100644 index cab99d8e2911..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for CRS326-24G-2S board - * - * Copyright (C) 2016 Allied Telesis Labs - * Copyright (C) 2020 Sartura Ltd. - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "CRS326-24G-2S+"; - compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ - }; -}; - -&L2 { - arm,parity-enable; - marvell,ecc-enable; -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x001f0000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x001f0000 0x00010000>; - label = "u-boot-env"; - }; - partition@ubi1 { - reg = <0x00200000 0x00e00000>; - label = "ubi1"; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts deleted file mode 100644 index 2caa3980fdf6..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board - * - * Copyright (C) 2020 Sartura Ltd. - * Author: Luka Kovacic - */ - -#include "armada-xp-crs328-4c-20s-4s.dtsi" - -/ { - model = "MikroTik CRS328-4C-20S-4S+ Bit"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x001f0000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x001f0000 0x00010000>; - label = "u-boot-env"; - }; - partition@ubi1 { - reg = <0x00200000 0x03f00000>; - label = "ubi1"; - }; - partition@ubi2 { - reg = <0x04100000 0x03f00000>; - label = "ubi2"; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts deleted file mode 100644 index 665757f6e18e..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for MikroTik CRS328-4C-20S-4S+ board - * - * Copyright (C) 2020 Sartura Ltd. - * Author: Luka Kovacic - */ - -#include "armada-xp-crs328-4c-20s-4s.dtsi" - -/ { - model = "MikroTik CRS328-4C-20S-4S+"; -}; - -&spi0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi deleted file mode 100644 index 7028482ce4b2..000000000000 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for CRS328-4C-20S-4S+ board - * - * Copyright (C) 2016 Allied Telesis Labs - * Copyright (C) 2020 Sartura Ltd. - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "CRS328-4C-20S-4S+"; - compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ - }; -}; - -&L2 { - arm,parity-enable; - marvell,ecc-enable; -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x001f0000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x001f0000 0x00010000>; - label = "u-boot-env"; - }; - partition@ubi1 { - reg = <0x00200000 0x00e00000>; - label = "ubi1"; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts deleted file mode 100644 index 02bef8dc4270..000000000000 --- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for DB-DXBC2 board - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx4251.dtsi" - -/ { - model = "Marvell Bobcat2 Evaluation Board"; - compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ - }; - -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - }; -}; - -&sdio { - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - partition@unused { - reg = <0x00140000 0x00ec0000>; - label = "unused"; - }; - - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts deleted file mode 100644 index d1b61dad0c46..000000000000 --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for DB-XC3-24G4XG board - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx3336.dtsi" - -/ { - model = "DB-XC3-24G4XG"; - compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ - }; -}; - -&L2 { - arm,parity-enable; - marvell,ecc-enable; -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - partition@unused { - reg = <0x00140000 0x00ec0000>; - label = "unused"; - }; - - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts deleted file mode 100644 index 75318fd0fc11..000000000000 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada XP evaluation board - * (DB-78460-BP) - * - * Copyright (C) 2012-2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Evaluation Board"; - compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - - bm@c0000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - usb@52000 { - status = "okay"; - }; - - nand-controller@d0000 { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pciec { - status = "okay"; - - /* - * All 6 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 0, Lane 2 */ - status = "okay"; - }; - pcie@4,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@a,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <25>; - }; - - phy3: ethernet-phy@3 { - reg = <27>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts deleted file mode 100644 index d1d348b91c0a..000000000000 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada XP development board - * (DB-MV784MP-GP) - * - * Copyright (C) 2013-2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Development Board DB-MV784MP-GP"; - compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* - * 8 GB of plug-in RAM modules by default.The amount - * of memory available can be changed by the - * bootloader according the size of the module - * actually plugged. However, memory between - * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is - * the address range used for I/O (internal registers, - * MBus windows). - */ - reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, - <0x00000001 0x00000000 0x00000001 0x00000000>; - }; - - cpus { - pm_pic { - ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, - <&gpio0 17 GPIO_ACTIVE_LOW>, - <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - pinctrl { - pinctrl-0 = <&pic_pins>; - pinctrl-names = "default"; - pic_pins: pic-pins-0 { - marvell,pins = "mpp16", "mpp17", - "mpp18"; - marvell,function = "gpio"; - }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - - /* Front-side USB slot */ - usb@50000 { - status = "okay"; - }; - - /* Back-side USB slot */ - usb@51000 { - status = "okay"; - }; - - bm@c0000 { - status = "okay"; - }; - - nand-controller@d0000 { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - }; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pciec { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@a,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <16>; - }; - - phy1: ethernet-phy@1 { - reg = <17>; - }; - - phy2: ethernet-phy@2 { - reg = <18>; - }; - - phy3: ethernet-phy@3 { - reg = <19>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts deleted file mode 100644 index 21b95578fe95..000000000000 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Lenovo Iomega ix4-300d - * - * Copyright (C) 2014, Benoit Masson - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Lenovo Iomega ix4-300d"; - compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - adt7473@2e { - compatible = "adi,adt7473"; - reg = <0x2e>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - }; - - nand-controller@d0000 { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x000e0000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x000e0000 0x00020000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env2"; - reg = <0x00100000 0x00020000>; - read-only; - }; - - partition@120000 { - label = "zImage"; - reg = <0x00120000 0x00400000>; - }; - - partition@520000 { - label = "initrd"; - reg = <0x00520000 0x00400000>; - }; - - partition@e00000 { - label = "boot"; - reg = <0x00e00000 0x3f200000>; - }; - }; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin &reset_button_pin - &select_button_pin &scroll_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - select-button { - label = "Select Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - scroll-button { - label = "Scroll Button"; - linux,code = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - }; - - spi-3 { - compatible = "spi-gpio"; - status = "okay"; - sck-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - mosi-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ - cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&hdd_led_pin>; - pinctrl-names = "default"; - - hdd-led { - label = "ix4-300d:hdd:blue"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - power-led { - label = "ix4-300d:power:white"; - gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; - /* init blinking while booting */ - linux,default-trigger = "timer"; - default-state = "on"; - }; - - sysfail-led { - label = "ix4-300d:sysfail:red"; - gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - sys-led { - label = "ix4-300d:sys:blue"; - gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - hddfail-led { - label = "ix4-300d:hddfail:red"; - gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; - - /* - * Warning: you need both eth1 & 0 PHY initialized (i.e having - * them up does the tweak) for poweroff to shutdown otherwise it - * reboots - */ - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff_pin>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; -&pciec { - status = "okay"; - - /* Quad port sata: Marvell 88SX7042 */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* USB 3.0 xHCI controller: NEC D720200F1 */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; -}; - -&pinctrl { - poweroff_pin: poweroff-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - select_button_pin: select-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - scroll_button_pin: scroll-button-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - hdd_led_pin: hdd-led-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts deleted file mode 100644 index 7a0614fd0c93..000000000000 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ /dev/null @@ -1,397 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT1900AC (Mamba). - * - * Note: this board is shipped with a new generation boot loader that - * remaps internal registers at 0xf1000000. Therefore, if earlyprintk - * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be - * used. - * - * Copyright (C) 2014 Imre Kaloz - * - * Based on armada-xp-axpwifiap.dts: - * - * Copyright (C) 2013 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Linksys WRT1900AC"; - compatible = "linksys,mamba", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ - }; - - soc { - ranges = ; - - internal-regs { - - rtc@10300 { - /* No crystal connected to the internal RTC */ - status = "disabled"; - }; - - /* J10: VCC, NC, RX, NC, TX, GND */ - serial@12000 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - /* USB part of the eSATA/USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - tlc59116@68 { - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <2>; - compatible = "ti,tlc59116"; - reg = <0x68>; - - wan_amber@0 { - label = "mamba:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "mamba:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "mamba:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "mamba:white:wlan_5g"; - reg = <0x3>; - }; - - esata@4 { - label = "mamba:white:esata"; - reg = <0x4>; - linux,default-trigger = "disk-activity"; - }; - - usb2@5 { - label = "mamba:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "mamba:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "mamba:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "mamba:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "mamba:amber:wps"; - reg = <0x9>; - }; - }; - }; - - bm@c8000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - button-reset { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin>; - pinctrl-names = "default"; - - led-power { - label = "mamba:white:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - pwm_fan { - /* SUNON HA4010V4-0000-C99 */ - - compatible = "pwm-fan"; - pwms = <&gpio0 24 4000>; - }; -}; - -&pciec { - status = "okay"; - - /* Etron EJ168 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* First mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; -}; - -&pinctrl { - - keys_pin: keys-pin { - marvell,pins = "mpp32", "mpp33"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - gpio_fan_pin: gpio-fan-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <40000000>; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - phy-mode = "rgmii-id"; - ethernet = <ð0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; /* 1MB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x100000 0x40000>; /* 256KB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x140000 0x40000>; /* 256KB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - - partition@d00000 { - label = "rootfs1"; - reg = <0xd00000 0x2500000>; /* 37MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - - partition@3500000 { - label = "rootfs2"; - reg = <0x3500000 0x2500000>; /* 37MB */ - }; - - /* - * 38MB, last MB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x180000 0x780000>; /* 7.5MB */ - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts deleted file mode 100644 index 1395cea12759..000000000000 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada XP Matrix board - * - * Copyright (C) 2013 Marvell - * - * Lior Amsalem - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Matrix Board"; - compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* - * This board has 4 GB of RAM, but the last 256 MB of - * RAM are not usable due to the overlap with the MBus - * Window address range - */ - reg = <0 0x00000000 0 0xf0000000>; - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy-mode = "sgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi deleted file mode 100644 index 5ea9d509cd30..000000000000 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * Contains definitions specific to the Armada XP MV78230 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78230 SoC"; - compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78230 has 2 PCIe units Gen2.0: One unit can be - * configured as x4 or quad x1 lanes. One unit is - * x1 only. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 58>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 59>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 60>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 61>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie4_intc 0>, - <0 0 0 2 &pcie4_intc 1>, - <0 0 0 3 &pcie4_intc 2>, - <0 0 0 4 &pcie4_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie4_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 62>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie5_intc 0>, - <0 0 0 2 &pcie5_intc 1>, - <0 0 0 3 &pcie5_intc 2>, - <0 0 0 4 &pcie5_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - - pcie5_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <17>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>; - clocks = <&coreclk 0>; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78230-pinctrl"; -}; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi deleted file mode 100644 index 6c6fbb9faf5a..000000000000 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * Contains definitions specific to the Armada XP MV78260 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78260 SoC"; - compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78260 has 3 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. One unit is - * x4 only. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 58>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 59>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 60>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 61>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie4_intc 0>, - <0 0 0 2 &pcie4_intc 1>, - <0 0 0 3 &pcie4_intc 2>, - <0 0 0 4 &pcie4_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie4_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 62>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie5_intc 0>, - <0 0 0 2 &pcie5_intc 1>, - <0 0 0 3 &pcie5_intc 2>, - <0 0 0 4 &pcie5_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - - pcie5_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie6: pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 63>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie6_intc 0>, - <0 0 0 2 &pcie6_intc 1>, - <0 0 0 3 &pcie6_intc 2>, - <0 0 0 4 &pcie6_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - - pcie6_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie7: pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 64>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie7_intc 0>, - <0 0 0 2 &pcie7_intc 1>, - <0 0 0 3 &pcie7_intc 2>, - <0 0 0 4 &pcie7_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - - pcie7_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie8: pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 65>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie8_intc 0>, - <0 0 0 2 &pcie8_intc 1>, - <0 0 0 3 &pcie8_intc 2>, - <0 0 0 4 &pcie8_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - - pcie8_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie9: pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 99>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie9_intc 0>, - <0 0 0 2 &pcie9_intc 1>, - <0 0 0 3 &pcie9_intc 2>, - <0 0 0 4 &pcie9_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - - pcie9_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - clocks = <&coreclk 0>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - eth3: ethernet@34000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x34000 0x4000>; - interrupts = <14>; - clocks = <&gateclk 1>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78260-pinctrl"; -}; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi deleted file mode 100644 index 16185edf9aa5..000000000000 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ /dev/null @@ -1,453 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * Contains definitions specific to the Armada XP MV78460 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78460 SoC"; - compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <2>; - clocks = <&cpuclk 2>; - clock-latency = <1000000>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <3>; - clocks = <&cpuclk 3>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78460 has 4 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. Two units are - * x4/x1. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ - - 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ - 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 58>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 59>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 60>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 61>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie4_intc 0>, - <0 0 0 2 &pcie4_intc 1>, - <0 0 0 3 &pcie4_intc 2>, - <0 0 0 4 &pcie4_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie4_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 62>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie5_intc 0>, - <0 0 0 2 &pcie5_intc 1>, - <0 0 0 3 &pcie5_intc 2>, - <0 0 0 4 &pcie5_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - - pcie5_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie6: pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 63>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie6_intc 0>, - <0 0 0 2 &pcie6_intc 1>, - <0 0 0 3 &pcie6_intc 2>, - <0 0 0 4 &pcie6_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - - pcie6_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie7: pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 64>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie7_intc 0>, - <0 0 0 2 &pcie7_intc 1>, - <0 0 0 3 &pcie7_intc 2>, - <0 0 0 4 &pcie7_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - - pcie7_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie8: pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 65>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie8_intc 0>, - <0 0 0 2 &pcie8_intc 1>, - <0 0 0 3 &pcie8_intc 2>, - <0 0 0 4 &pcie8_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - - pcie8_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie9: pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 99>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie9_intc 0>, - <0 0 0 2 &pcie9_intc 1>, - <0 0 0 3 &pcie9_intc 2>, - <0 0 0 4 &pcie9_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - - pcie9_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie10: pcie@a,0 { - device_type = "pci"; - assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&mpic 103>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 - 0x81000000 0 0 0x81000000 0xa 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie10_intc 0>, - <0 0 0 2 &pcie10_intc 1>, - <0 0 0 3 &pcie10_intc 2>, - <0 0 0 4 &pcie10_intc 3>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 27>; - status = "disabled"; - - pcie10_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - clocks = <&coreclk 0>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - eth3: ethernet@34000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x34000 0x4000>; - interrupts = <14>; - clocks = <&gateclk 1>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78460-pinctrl"; -}; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts deleted file mode 100644 index 31933f81144e..000000000000 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NETGEAR ReadyNAS 2120 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "NETGEAR ReadyNAS 2120"; - compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - /* Controller for rear fan #1 of 3 (Protechnic - * MGT4012XB-O20, 8000RPM) near eSATA port */ - g762_fan1: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Controller for rear (center) fan #2 of 3 */ - g762_fan2: g762@48 { - compatible = "gmt,g762"; - reg = <0x48>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Controller for rear fan #3 of 3 */ - g762_fan3: g762@49 { - compatible = "gmt,g762"; - reg = <0x49>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Temperature sensor */ - g751: g751@4c { - compatible = "gmt,g751"; - reg = <0x4c>; - }; - - isl12057: rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - }; - - serial@12000 { - status = "okay"; - }; - - /* Front USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - /* Two rear eSATA ports */ - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin - &sata3_led_pin &sata4_led_pin>; - pinctrl-names = "default"; - - red-sata1-led { - label = "rn2120:red:sata1"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata2-led { - label = "rn2120:red:sata2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata3-led { - label = "rn2120:red:sata3"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata4-led { - label = "rn2120:red:sata4"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-err-led { - label = "rn2120:red:err"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin &reset_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* Connected to first Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to second Marvell 88SE9170 SATA controller */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Connected to Fresco Logic FL1009 USB 3.0 controller */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; -}; - - -&pinctrl { - poweroff: poweroff { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata3_led_pin: sata3-led-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata4_led_pin: sata4-led-pin { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - sata1_power_pin: sata1-power-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - sata2_power_pin: sata2-power-pin { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - sata3_power_pin: sata3-power-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - sata4_power_pin: sata4-power-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - err_led_pin: err-led-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts deleted file mode 100644 index 1ecf72a61bca..000000000000 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for OpenBlocks AX3-4 board - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78260.dtsi" - -/ { - model = "PlatHome OpenBlocks AX3-4 board"; - compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 128 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; - }; - }; - - internal-regs { - rtc@10300 { - /* No crystal connected to the internal RTC */ - status = "disabled"; - }; - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - red_led { - label = "red_led"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yellow_led { - label = "yellow_led"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green_led { - label = "green_led"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-init { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - }; - i2c@11100 { - status = "okay"; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - /* Front side USB 0 */ - usb@50000 { - status = "okay"; - }; - - /* Front side USB 1 */ - usb@51000 { - status = "okay"; - }; - - bm@c0000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pciec { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; -}; - -&pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts deleted file mode 100644 index 5551bac1962c..000000000000 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ /dev/null @@ -1,328 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Synology DS414 - * - * Copyright (C) 2014, Arnaud EBALARD - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the old 0xd0000000). - * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot - * bootloaders provided by Marvell. It is used in recent versions of - * DSM software provided by Synology. Nonetheless, some earlier boards - * were delivered with an older version of u-boot that left internal - * registers mapped at 0xd0000000. If you have such a device you will - * not be able to directly boot a kernel based on this Device Tree. In - * that case, the preferred solution is to update your bootloader (e.g. - * by upgrading to latest version of DSM, or building a new one and - * installing it from u-boot prompt) or adjust the Devive Tree - * (s/0xf1000000/0xd0000000/ in 'ranges' below). - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Synology DS414"; - compatible = "synology,ds414", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Seiko S-35390A below */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - /* Connected to a header on device's PCB. This - * provides the main console for the device. - * - * Warning: the device may not boot with a 3.3V - * USB-serial converter connected when the power - * button is pressed. The converter needs to be - * connected a few seconds after pressing the - * power button. This is possibly due to UART0_TXD - * pin being sampled at reset (bit 0 of SAR). - */ - serial@12000 { - status = "okay"; - }; - - /* Connected to a Microchip PIC16F883 for power control */ - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - /* Front USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin - &sata3_pwr_pin &sata4_pwr_pin>; - pinctrl-names = "default"; - - sata1_regulator: sata1-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - sata3_regulator: sata3-regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA3 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <6000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - - sata4_regulator: sata4-regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA4 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <8000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1512 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; -}; - -&pinctrl { - sata1_pwr_pin: sata1-pwr-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - sata2_pwr_pin: sata2-pwr-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata3_pwr_pin: sata3-pwr-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - sata4_pwr_pin: sata4-pwr-pin { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - syno_id_bit0_pin: syno-id-bit0-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - syno_id_bit1_pin: syno-id-bit1-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - syno_id_bit2_pin: syno-id-bit2-pin { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - fan1_alarm_pin: fan1-alarm-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - fan2_alarm_pin: fan2-alarm-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@0 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000d0000>; /* 832KB */ - }; - - partition@c0000 { /* uImage */ - label = "zImage"; - reg = <0x000d0000 0x002d0000>; /* 2880KB */ - }; - - partition@3a0000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x003a0000 0x00430000>; /* 4250KB */ - }; - - partition@7d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi deleted file mode 100644 index 4297482da62f..000000000000 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ /dev/null @@ -1,345 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * Ben Dooks - * - * Contains definitions specific to the Armada XP SoC that are not - * common to all Armada SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <2>; - - model = "Marvell Armada XP family SoC"; - compatible = "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - compatible = "marvell,armadaxp-mbus", "simple-bus"; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - internal-regs { - sdramc: sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: l2-cache@8000 { - compatible = "marvell,aurora-system-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - uart2: serial@12200 { - compatible = "snps,dw-apb-uart"; - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = <43>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "snps,dw-apb-uart"; - pinctrl-0 = <&uart3_pins>; - pinctrl-names = "default"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = <44>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18230 { - compatible = "marvell,armada-xp-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - - thermal: thermal@182b0 { - compatible = "marvell,armadaxp-thermal"; - reg = <0x182b0 0x4 - 0x184d0 0x4>; - status = "okay"; - }; - - cpuclk: clock-complex@18700 { - #clock-cells = <1>; - compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0x24>, <0x1c054 0x10>; - clocks = <&coreclk 1>; - }; - - cpu-config@21000 { - compatible = "marvell,armada-xp-cpu-config"; - reg = <0x21000 0x8>; - }; - - eth2: ethernet@30000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x30000 0x4000>; - interrupts = <12>; - clocks = <&gateclk 2>; - status = "disabled"; - }; - - usb2: usb@52000 { - compatible = "marvell,orion-ehci"; - reg = <0x52000 0x500>; - interrupts = <47>; - clocks = <&gateclk 20>; - status = "disabled"; - }; - - xor1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor10 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - ethernet@70000 { - compatible = "marvell,armada-xp-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-xp-neta"; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-xp-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>, <49>; - clocks = <&gateclk 23>, <&gateclk 23>; - clock-names = "cesa0", "cesa1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - bm: bm@c0000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc0000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - status = "disabled"; - }; - - xor0: xor@f0900 { - compatible = "marvell,orion-xor"; - reg = <0xF0900 0x100 - 0xF0B00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor00 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; - }; - - bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; - no-memory-wc; - status = "disabled"; - }; - }; - - clocks { - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; - -&i2c0 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; -}; - -&i2c1 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; -}; - -&mpic { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; -}; - -&timer { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; -}; - -&watchdog { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - interrupts = <93>, <38>; -}; - -&cpurst { - reg = <0x20800 0x20>; -}; - -&usb0 { - clocks = <&gateclk 18>; -}; - -&usb1 { - clocks = <&gateclk 19>; -}; - -&pinctrl { - ge0_gmii_pins: ge0-gmii-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge0"; - }; - - ge0_rgmii_pins: ge0-rgmii-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge1-rgmii-pins { - marvell,pins = - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge1"; - }; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp36", "mpp37", - "mpp38", "mpp39"; - marvell,function = "spi0"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp13", "mpp14", - "mpp16", "mpp17"; - marvell,function = "spi1"; - }; - - uart2_pins: uart2-pins { - marvell,pins = "mpp42", "mpp43"; - marvell,function = "uart2"; - }; - - uart3_pins: uart3-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "uart3"; - }; -}; - -&spi0 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; -}; - -&spi1 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts deleted file mode 100644 index 042a9cc920c6..000000000000 --- a/arch/arm/boot/dts/artpec6-devboard.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Axis ARTPEC-6 development board. - -/dts-v1/; -#include "artpec6.dtsi" - -/ { - model = "ARTPEC-6 development board"; - compatible = "axis,artpec6-dev-board", "axis,artpec6"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -ðernet { - status = "okay"; - - phy-handle = <&phy1>; - phy-mode = "gmii"; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; - phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi deleted file mode 100644 index 037157e6c5ee..000000000000 --- a/arch/arm/boot/dts/artpec6.dtsi +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Device Tree Source for the Axis ARTPEC-6 SoC - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "axis,artpec6"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&pl310>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&pl310>; - }; - }; - - syscon: syscon@f8000000 { - compatible = "axis,artpec6-syscon", "syscon"; - reg = <0xf8000000 0x48>; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - psci_version = <0x84000000>; - cpu_on = <0x84000003>; - system_reset = <0x84000009>; - }; - - scu@faf00000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfaf00000 0x58>; - }; - - /* Main external clock driving CPU and peripherals */ - ext_clk: ext_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - eth_phy_ref_clk: eth_phy_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - }; - - clkctrl: clkctrl@f8000000 { - #clock-cells = <1>; - compatible = "axis,artpec6-clkctrl"; - reg = <0xf8000000 0x48>; - clocks = <&ext_clk>; - clock-names = "sys_refclk"; - }; - - gtimer@faf00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfaf00200 0x20>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; - }; - - timer@faf00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfaf00600 0x20>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; - status = "disabled"; - }; - - intc: interrupt-controller@faf01000 { - interrupt-controller; - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; - }; - - pl310: cache-controller@faf10000 { - compatible = "arm,pl310-cache"; - cache-unified; - cache-level = <2>; - reg = <0xfaf10000 0x1000>; - interrupts = ; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - arm,filter-ranges = <0x0 0x80000000>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,prefetch-offset = <0>; - arm,prefetch-drop = <1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* - * Both pci nodes cannot be enabled at the same time, - * leave the unwanted node as disabled. - */ - pcie: pcie@f8050000 { - compatible = "axis,artpec6-pcie", "snps,dw-pcie"; - reg = <0xf8050000 0x2000 - 0xf8040000 0x1000 - 0xc0000000 0x2000>; - reg-names = "dbi", "phy", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - /* downstream I/O */ - ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; - num-lanes = <2>; - bus-range = <0x00 0xff>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - axis,syscon-pcie = <&syscon>; - status = "disabled"; - }; - - pcie_ep: pcie_ep@f8050000 { - compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie"; - reg = <0xf8050000 0x2000 - 0xf8051000 0x2000 - 0xf8040000 0x1000 - 0xc0000000 0x20000000>; - reg-names = "dbi", "dbi2", "phy", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <2>; - axis,syscon-pcie = <&syscon>; - status = "disabled"; - }; - - pinctrl: pinctrl@f801d000 { - compatible = "axis,artpec6-pinctrl"; - reg = <0xf801d000 0x400>; - - pinctrl_uart0: uart0grp { - function = "uart0"; - groups = "uart0grp2"; - bias-pull-up; - }; - pinctrl_uart1: uart1grp { - function = "uart1"; - groups = "uart1grp0"; - bias-pull-up; - }; - pinctrl_uart2: uart2grp { - function = "uart2"; - groups = "uart2grp1"; - bias-pull-up; - }; - pinctrl_uart3: uart3grp { - function = "uart3"; - groups = "uart3grp0"; - bias-pull-up; - }; - }; - - amba@0 { - compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - dma-ranges; - - crypto@f4264000 { - compatible = "axis,artpec6-crypto"; - reg = <0xf4264000 0x4000>; - interrupts = ; - }; - - dma0: dma@f8019000 { - compatible = "renesas,nbpfaxi64dmac8b16"; - reg = <0xf8019000 0x400>; - interrupts = , /* error */ - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch12", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <8>; - }; - dma1: dma@f8019400 { - compatible = "renesas,nbpfaxi64dmac8b16"; - reg = <0xf8019400 0x400>; - interrupts = , /* error */ - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch12", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <8>; - }; - - ethernet: ethernet@f8010000 { - clock-names = "stmmaceth", "ptp_ref"; - clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>, - <&clkctrl ARTPEC6_CLK_PTP_REF>; - compatible = "snps,dwmac-4.10a", "snps,dwmac"; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - reg = <0xf8010000 0x4000>; - - snps,axi-config = <&stmmac_axi_setup>; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - snps,txpbl = <8>; - snps,rxpbl = <2>; - snps,aal; - snps,tso; - - status = "disabled"; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <1>; - snps,rd_osr_lmt = <15>; - /* If FB is disabled, the AXI master chooses - * a burst length of any value less than the - * maximum enabled burst length - * (all lesser burst length enables are redundant). - */ - snps,blen = <0 0 0 0 16 0 0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - uart0: serial@f8036000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8036000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart1: serial@f8037000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8037000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart2: serial@f8038000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8038000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart3: serial@f8039000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8039000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts deleted file mode 100644 index a497dd135491..000000000000 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" - -/ { - model = "AST2500 EVB"; - compatible = "aspeed,ast2500-evb", "aspeed,ast2500"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&spi2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c3 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c7 { - status = "okay"; - - lm75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_default>; -}; - -/* - * Enable port A as device (via the virtual hub) and port B as - * host by default on the eval board. This can be easily changed - * by replacing the override below with &ehci0 { ... } to enable - * host on both ports. - */ -&vhub { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts deleted file mode 100644 index f34a2b1ec2f0..000000000000 --- a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2021 IBM Corp. - -#include "aspeed-ast2600-evb.dts" - -/ { - model = "AST2600 A1 EVB"; - compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600-evb", "aspeed,ast2600"; - - /delete-node/regulator-vcc-sdhci0; - /delete-node/regulator-vcc-sdhci1; - /delete-node/regulator-vccq-sdhci0; - /delete-node/regulator-vccq-sdhci1; -}; - -/delete-node/ &sdc; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts deleted file mode 100644 index de83c0eb1d6e..000000000000 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ /dev/null @@ -1,350 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. - -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include - -/ { - model = "AST2600 EVB"; - compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - video_engine_memory: video { - size = <0x04000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - vcc_sdhci0: regulator-vcc-sdhci0 { - compatible = "regulator-fixed"; - regulator-name = "SDHCI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhci0: regulator-vccq-sdhci0 { - compatible = "regulator-gpio"; - regulator-name = "SDHCI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, - <1800000 0>; - }; - - vcc_sdhci1: regulator-vcc-sdhci1 { - compatible = "regulator-fixed"; - regulator-name = "SDHCI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhci1: regulator-vccq-sdhci1 { - compatible = "regulator-gpio"; - regulator-name = "SDHCI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, - <1800000 0>; - }; -}; - -&mdio0 { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mdio1 { - status = "okay"; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mdio2 { - status = "okay"; - - ethphy2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mdio3 { - status = "okay"; - - ethphy3: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mac0 { - status = "okay"; - - phy-mode = "rgmii-rxid"; - phy-handle = <ðphy0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default>; -}; - - -&mac1 { - status = "okay"; - - phy-mode = "rgmii-rxid"; - phy-handle = <ðphy1>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default>; -}; - -&mac2 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii3_default>; -}; - -&mac3 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy3>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - non-removable; - bus-width = <4>; - max-frequency = <100000000>; - clk-phase-mmc-hs200 = <9>, <225>; -}; - -&rtc { - status = "okay"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-rx-bus-width = <4>; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-rx-bus-width = <4>; - spi-max-frequency = <100000000>; - }; -}; - -&uart5 { - // Workaround for A0 - compatible = "snps,dw-apb-uart"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - temp@2e { - compatible = "adi,adt7490"; - reg = <0x2e>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c8 { - status = "okay"; - - lm75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&i2c14 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; - -&fsim0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&sdc { - status = "okay"; -}; - -/* - * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be - * toggled by GPIO pins. - * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the - * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to - * a 1.8v and a 3.3v power load switch that provides signal voltage to - * sdhci0 bus. - * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled. - * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal - * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled, - * sdhci0 signal voltage becomes 1.8v. - * AST2600-A2 EVB also supports toggling signal voltage for sdhci1. - * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3 - * as power-switch-gpio. - */ -&sdhci0 { - status = "okay"; - bus-width = <4>; - max-frequency = <100000000>; - sdhci-drive-type = /bits/ 8 <3>; - sdhci-caps-mask = <0x7 0x0>; - sdhci,wp-inverted; - vmmc-supply = <&vcc_sdhci0>; - vqmmc-supply = <&vccq_sdhci0>; - clk-phase-sd-hs = <7>, <200>; -}; - -&sdhci1 { - status = "okay"; - bus-width = <4>; - max-frequency = <100000000>; - sdhci-drive-type = /bits/ 8 <3>; - sdhci-caps-mask = <0x7 0x0>; - sdhci,wp-inverted; - vmmc-supply = <&vcc_sdhci1>; - vqmmc-supply = <&vccq_sdhci1>; - clk-phase-sd-hs = <7>, <200>; -}; - -&vhub { - status = "okay"; - pinctrl-names = "default"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts b/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts deleted file mode 100644 index 64bb9bf92de2..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "AMD DaytonaX BMC"; - compatible = "amd,daytonax-bmc", "aspeed,ast2500"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - aliases { - serial0 = &uart1; - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200"; - }; - - leds { - compatible = "gpio-leds"; - - led-fault { - gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; - }; - - led-identify { - gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, - <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>, - <&adc 15>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - #include "openbmc-flash-layout.dtsi" - }; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&uart1 { - //Host Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - //BMC Console - status = "okay"; -}; - -&vuart { - status = "okay"; - aspeed,lpc-io-reg = <0x3f8>; - aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "","","led-fault","led-identify","","","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "id-button","","","","","","","", - /*D0-D7*/ "","","ASSERT_BMC_READY","","","","","", - /*E0-E7*/ "reset-button","reset-control","power-button","power-control","", - "power-good","power-ok","", - /*F0-F7*/ "","","","","","","BATTERY_DETECT","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "FM_BMC_READ_SPD_TEMP","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>, <0x81>; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default - &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@12 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@13 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; - - fan@14 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e>; - }; - - fan@15 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0f>; - }; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&vhub { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts deleted file mode 100644 index 6bded774c457..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 AMD Inc. -// Author: Supreeth Venkatesh -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "AMD EthanolX BMC"; - compatible = "amd,ethanolx-bmc", "aspeed,ast2500"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - - aliases { - serial0 = &uart1; - serial4 = &uart5; - }; - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - leds { - compatible = "gpio-leds"; - - fault { - gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; - }; - }; - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - #include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bios"; - spi-max-frequency = <100000000>; - }; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&uart1 { - //Host Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ncts1_default>; -}; - -&uart5 { - //BMC Console - status = "okay"; -}; - -&adc { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default>; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","", - /*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S", - "JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD", - /*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN", - "MON_P0_PWR_GOOD","MON_PWROK","MON_RESET", - /*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP", - "MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","", - /*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0", - "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","", - /*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3", - "PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN", - "ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT", - "ASSERT_CLR_CMOS","ASSERT_BMC_READY", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT", - "P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT", - "P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT", - "P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","SENSOR THERM","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -//APML for P0 -&i2c0 { - status = "okay"; -}; - -//APML for P1 -&i2c1 { - status = "okay"; -}; - -//FPGA -&i2c2 { - status = "okay"; -}; - -//24LC128 EEPROM -&i2c3 { - status = "okay"; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -//P0 Power regulators -&i2c4 { - status = "okay"; -}; - -//P1 Power regulators -&i2c5 { - status = "okay"; -}; - -//P0/P1 Thermal diode -&i2c6 { - status = "okay"; -}; - -// Thermal Sensors -&i2c7 { - status = "okay"; - - lm75a@48 { - compatible = "national,lm75a"; - reg = <0x48>; - }; - - lm75a@49 { - compatible = "national,lm75a"; - reg = <0x49>; - }; - - lm75a@4a { - compatible = "national,lm75a"; - reg = <0x4a>; - }; - - lm75a@4b { - compatible = "national,lm75a"; - reg = <0x4b>; - }; - - lm75a@4c { - compatible = "national,lm75a"; - reg = <0x4c>; - }; - - lm75a@4d { - compatible = "national,lm75a"; - reg = <0x4d>; - }; - - lm75a@4e { - compatible = "national,lm75a"; - reg = <0x4e>; - }; - - lm75a@4f { - compatible = "national,lm75a"; - reg = <0x4f>; - }; -}; - -//BMC I2C -&i2c8 { - status = "okay"; -}; - -&kcs1 { - status = "okay"; - aspeed,lpc-io-reg = <0x60>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0x62>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xCA2>; -}; - -&kcs4 { - status = "okay"; - aspeed,lpc-io-reg = <0x97DE>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>, <0x81>; -}; - -&lpc_ctrl { - //Enable lpc clock - status = "okay"; -}; - -&vuart { - status = "okay"; - aspeed,lpc-io-reg = <0x3f8>; - aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default - &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&vhub { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts deleted file mode 100644 index 0a51d2e32fab..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ /dev/null @@ -1,808 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Ampere Mt. Jade BMC"; - compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; - - aliases { - /* - * i2c bus 50-57 assigned to NVMe slot 0-7 - */ - i2c50 = &nvmeslot_0; - i2c51 = &nvmeslot_1; - i2c52 = &nvmeslot_2; - i2c53 = &nvmeslot_3; - i2c54 = &nvmeslot_4; - i2c55 = &nvmeslot_5; - i2c56 = &nvmeslot_6; - i2c57 = &nvmeslot_7; - - /* - * i2c bus 60-67 assigned to NVMe slot 8-15 - */ - i2c60 = &nvmeslot_8; - i2c61 = &nvmeslot_9; - i2c62 = &nvmeslot_10; - i2c63 = &nvmeslot_11; - i2c64 = &nvmeslot_12; - i2c65 = &nvmeslot_13; - i2c66 = &nvmeslot_14; - i2c67 = &nvmeslot_15; - - /* - * i2c bus 70-77 assigned to NVMe slot 16-23 - */ - i2c70 = &nvmeslot_16; - i2c71 = &nvmeslot_17; - i2c72 = &nvmeslot_18; - i2c73 = &nvmeslot_19; - i2c74 = &nvmeslot_20; - i2c75 = &nvmeslot_21; - i2c76 = &nvmeslot_22; - i2c77 = &nvmeslot_23; - - /* - * i2c bus 80-81 assigned to NVMe M2 slot 0-1 - */ - i2c80 = &nvme_m2_0; - i2c81 = &nvme_m2_1; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - fault { - gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>; - }; - }; - - gpioA0mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>; - }; - - adc0mux: adc0mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc1mux: adc1mux { - compatible = "io-channel-mux"; - io-channels = <&adc 1>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc2mux: adc2mux { - compatible = "io-channel-mux"; - io-channels = <&adc 2>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc3mux: adc3mux { - compatible = "io-channel-mux"; - io-channels = <&adc 3>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc4mux: adc4mux { - compatible = "io-channel-mux"; - io-channels = <&adc 4>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc5mux: adc5mux { - compatible = "io-channel-mux"; - io-channels = <&adc 5>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc6mux: adc6mux { - compatible = "io-channel-mux"; - io-channels = <&adc 6>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc7mux: adc7mux { - compatible = "io-channel-mux"; - io-channels = <&adc 7>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc8mux: adc8mux { - compatible = "io-channel-mux"; - io-channels = <&adc 8>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc9mux: adc9mux { - compatible = "io-channel-mux"; - io-channels = <&adc 9>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc10mux: adc10mux { - compatible = "io-channel-mux"; - io-channels = <&adc 10>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc11mux: adc11mux { - compatible = "io-channel-mux"; - io-channels = <&adc 11>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc12mux: adc12mux { - compatible = "io-channel-mux"; - io-channels = <&adc 12>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - adc13mux: adc13mux { - compatible = "io-channel-mux"; - io-channels = <&adc 13>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioA0mux>; - channels = "s0", "s1"; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0mux 0>, <&adc0mux 1>, - <&adc1mux 0>, <&adc1mux 1>, - <&adc2mux 0>, <&adc2mux 1>, - <&adc3mux 0>, <&adc3mux 1>, - <&adc4mux 0>, <&adc4mux 1>, - <&adc5mux 0>, <&adc5mux 1>, - <&adc6mux 0>, <&adc6mux 1>, - <&adc7mux 0>, <&adc7mux 1>, - <&adc8mux 0>, <&adc8mux 1>, - <&adc9mux 0>, <&adc9mux 1>, - <&adc10mux 0>, <&adc10mux 1>, - <&adc11mux 0>, <&adc11mux 1>, - <&adc12mux 0>, <&adc12mux 1>, - <&adc13mux 0>, <&adc13mux 1>, - <&adc 14>, <&adc 15>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - /* spi-max-frequency = <50000000>; */ -#include "openbmc-flash-layout-64.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; -#include "openbmc-flash-layout-64-alt.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - /* spi-max-frequency = <100000000>; */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - uefi@400000 { - reg = <0x400000 0x1C00000>; - label = "pnor-uefi"; - }; - }; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_ncts1_default - &pinctrl_nrts1_default>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -/* The BMC's uart */ -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - ssif-bmc@10 { - compatible = "ssif-bmc"; - reg = <0x10>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - smpro@4f { - compatible = "ampere,smpro"; - reg = <0x4f>; - }; - smpro@4e { - compatible = "ampere,smpro"; - reg = <0x4e>; - }; -}; - -&i2c3 { - status = "okay"; - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - inlet_mem2: tmp175@28 { - compatible = "ti,tmp175"; - reg = <0x28>; - }; - - inlet_cpu: tmp175@29 { - compatible = "ti,tmp175"; - reg = <0x29>; - }; - - inlet_mem1: tmp175@2a { - compatible = "ti,tmp175"; - reg = <0x2a>; - }; - - outlet_cpu: tmp175@2b { - compatible = "ti,tmp175"; - reg = <0x2b>; - }; - - outlet1: tmp175@2c { - compatible = "ti,tmp175"; - reg = <0x2c>; - }; - - outlet2: tmp175@2d { - compatible = "ti,tmp175"; - reg = <0x2d>; - }; -}; - -&i2c4 { - status = "okay"; - rtc@51 { - compatible = "nxp,pcf85063a"; - reg = <0x51>; - }; -}; - -&i2c5 { - status = "okay"; - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - nvmeslot_0_7: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - }; - - i2c-mux@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - nvmeslot_8_15: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - - nvmeslot_16_23: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - - }; - - i2c-mux@72 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - i2c-mux-idle-disconnect; - - nvme_m2_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - - nvme_m2_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - }; -}; - -&nvmeslot_0_7 { - status = "okay"; - - i2c-mux@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - nvmeslot_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - nvmeslot_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - nvmeslot_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - nvmeslot_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - nvmeslot_4: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - nvmeslot_5: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - nvmeslot_6: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - nvmeslot_7: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - - }; -}; - -&nvmeslot_8_15 { - status = "okay"; - - i2c-mux@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - nvmeslot_8: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - nvmeslot_9: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - nvmeslot_10: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - nvmeslot_11: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - nvmeslot_12: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - nvmeslot_13: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - nvmeslot_14: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - nvmeslot_15: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&nvmeslot_16_23 { - status = "okay"; - - i2c-mux@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - nvmeslot_16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - nvmeslot_17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - nvmeslot_18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - nvmeslot_19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - nvmeslot_20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - nvmeslot_21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - nvmeslot_22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - nvmeslot_23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&i2c6 { - status = "okay"; - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - psu@59 { - compatible = "pmbus"; - reg = <0x59>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - }; - - adm1278@11 { - compatible = "adi,adm1278"; - reg = <0x11>; - }; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@1 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@2 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@5 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@6 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@7 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@8 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@9 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; - - fan@10 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e>; - }; - - fan@11 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0f>; - }; - -}; - -&vhub { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&gpio { - gpio-line-names = - /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","", - /*B0-B7*/ "BMC_SELECT_EEPROM","","","", - "POWER_BUTTON","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", - "S1_DDR_SAVE","","", - /*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","", - "","", - /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", - /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", - "","","","","", - /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", - "","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","UID_BUTTON","","", - /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", - "OCP_MAIN_PWREN","RESET_BUTTON","","", - /*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","", - "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR", - "S1_BMC_DDR_ADR","","","","", - /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", - "BMC_OCP_PG"; - - i2c4-o-en-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_I2C4_O_EN"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts deleted file mode 100644 index 1e0e88465254..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (c) 2022, Ampere Computing LLC - -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include - -/ { - model = "Ampere Mt.Mitchell BMC"; - compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600"; - - chosen { - stdout-path = &uart5; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: video { - size = <0x04000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - vga_memory: region@bf000000 { - no-map; - compatible = "shared-dma-pool"; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; - }; - - voltage_mon_reg: voltage-mon-regulator { - compatible = "regulator-fixed"; - regulator-name = "ltc2497_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpioI5mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>; - }; - - adc0mux: adc0mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 0>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc1mux: adc1mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 1>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc2mux: adc2mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 2>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc3mux: adc3mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 3>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc4mux: adc4mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 4>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc5mux: adc5mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 5>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc6mux: adc6mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 6>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc7mux: adc7mux { - compatible = "io-channel-mux"; - io-channels = <&adc0 7>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc8mux: adc8mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 0>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc9mux: adc9mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 1>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc10mux: adc10mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 2>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc11mux: adc11mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 3>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc12mux: adc12mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 4>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc13mux: adc13mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 5>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc14mux: adc14mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 6>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - adc15mux: adc15mux { - compatible = "io-channel-mux"; - io-channels = <&adc1 7>; - #io-channel-cells = <1>; - io-channel-names = "parent"; - mux-controls = <&gpioI5mux>; - channels = "s0", "s1"; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0mux 0>, <&adc0mux 1>, - <&adc1mux 0>, <&adc1mux 1>, - <&adc2mux 0>, <&adc2mux 1>, - <&adc3mux 0>, <&adc3mux 1>, - <&adc4mux 0>, <&adc4mux 1>, - <&adc5mux 0>, <&adc5mux 1>, - <&adc6mux 0>, <&adc6mux 1>, - <&adc7mux 0>, <&adc7mux 1>, - <&adc8mux 0>, <&adc8mux 1>, - <&adc9mux 0>, <&adc9mux 1>, - <&adc10mux 0>, <&adc10mux 1>, - <&adc11mux 0>, <&adc11mux 1>, - <&adc12mux 0>, <&adc12mux 1>, - <&adc13mux 0>, <&adc13mux 1>, - <&adc14mux 0>, <&adc14mux 1>, - <&adc15mux 0>, <&adc15mux 1>, - <&adc_i2c 0>, <&adc_i2c 1>, - <&adc_i2c 2>, <&adc_i2c 3>, - <&adc_i2c 4>, <&adc_i2c 5>, - <&adc_i2c 6>, <&adc_i2c 7>, - <&adc_i2c 8>, <&adc_i2c 9>, - <&adc_i2c 10>, <&adc_i2c 11>, - <&adc_i2c 12>, <&adc_i2c 13>, - <&adc_i2c 14>, <&adc_i2c 15>; - }; -}; - -&mdio0 { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mac0 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default>; -}; - -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64-alt.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <20000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@2e { - compatible = "adi,adt7490"; - reg = <0x2e>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - psu@59 { - compatible = "pmbus"; - reg = <0x59>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - adc_i2c: adc@16 { - compatible = "lltc,ltc2497"; - reg = <0x16>; - vref-supply = <&voltage_mon_reg>; - #io-channel-cells = <1>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-mux@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - i2c4_bus70_chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - outlet_temp1: temperature-sensor@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - psu1_inlet_temp2: temperature-sensor@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - }; - - i2c4_bus70_chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - - pcie_zone_temp1: temperature-sensor@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - psu0_inlet_temp2: temperature-sensor@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - }; - - i2c4_bus70_chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - pcie_zone_temp2: temperature-sensor@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - outlet_temp2: temperature-sensor@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - }; - - i2c4_bus70_chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - mb_inlet_temp1: temperature-sensor@7c { - compatible = "microchip,emc1413"; - reg = <0x7c>; - }; - mb_inlet_temp2: temperature-sensor@4c { - compatible = "microchip,emc1413"; - reg = <0x4c>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - }; -}; - -&i2c6 { - status = "okay"; - rtc@51 { - compatible = "nxp,pcf85063a"; - reg = <0x51>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - gpio@77 { - compatible = "nxp,pca9539"; - reg = <0x77>; - gpio-controller; - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <2>; - - bmc-ocp0-en-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-high; - line-name = "bmc-ocp0-en-n"; - }; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - ssif-bmc@10 { - compatible = "ssif-bmc"; - reg = <0x10>; - }; -}; - -&i2c14 { - status = "okay"; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - bmc_ast2600_cpu: temperature-sensor@35 { - compatible = "ti,tmp175"; - reg = <0x35>; - }; -}; - -&adc0 { - ref_voltage = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; -}; - -&adc1 { - ref_voltage = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&gpio0 { - gpio-line-names = - /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n", - /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","", - /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","", - "irq-n","","vrd-sel","spd-sel", - /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n", - "","bmc-ncsi-txen","","", - /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","", - /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control", - "cpu-bios-recover","s0-heartbeat","hs-csout-prochot", - "s0-vr-hot-n","s1-vr-hot-n", - /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","", - /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","", - /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0", - "s0-rtc-lock","","","", - /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb", - "jtag-dbgr-prsnt-n","s1-heartbeat","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","", - "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","identify-button","led-identify", - "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", - "host0-reboot-ack-n","host0-ready","host0-shd-req-n", - "host0-shd-ack-n","s0-overtemp-n", - /*W0-W7*/ "","ocp-main-pwren","ocp-pgood","", - "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", - /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", - "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", - "s1-overtemp-n","s1-spi-auth-fail-n", - /*Y0-Y7*/ "","","","","","","","host0-special-boot", - /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; - - ocp-aux-pwren-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "ocp-aux-pwren"; - }; -}; - -&gpio1 { - gpio-line-names = - /*18A0-18A7*/ "","","","","","","","", - /*18B0-18B7*/ "","","","","","","s0-soc-pgood","", - /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1", - "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1", - /*18D0-18D7*/ "","","","","","","","", - /*18E0-18E3*/ "","","",""; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts deleted file mode 100644 index 7c6af7f226e7..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ /dev/null @@ -1,220 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "HXT StarDragon 4800 REP2 AST2520"; - compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - leds { - compatible = "gpio-leds"; - - system_fault1 { - label = "System_fault1"; - gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>; - }; - - system_fault2 { - label = "System_fault2"; - gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default - &pinctrl_spi2cs0_default>; -}; - -&uart3 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - current-speed = <115200>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii2_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, - <&syscon ASPEED_CLK_MAC2RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@1e { - compatible = "ti,tmp421"; - reg = <0x1e>; - }; - tmp421@2a { - compatible = "ti,tmp421"; - reg = <0x2a>; - }; - tmp421@1c { - compatible = "ti,tmp421"; - reg = <0x1c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - nvt210@4c { - compatible = "nvt210"; - reg = <0x4c>; - }; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <128>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - pca9641@70 { - compatible = "nxp,pca9641"; - reg = <0x70>; - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - dps650ab@58 { - compatible = "dps650ab"; - reg = <0x58>; - }; - }; - }; - - dps650ab@58 { - compatible = "delta,dps650ab"; - reg = <0x58>; - }; - - dps650ab@59 { - compatible = "delta,dps650ab"; - reg = <0x59>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_c7 { - gpio-hog; - gpios = ; - output-low; - line-name = "BIOS_SPI_MUX_S"; - }; - pin_gpio_d1 { - gpio-hog; - gpios = ; - output-high; - line-name = "PHY2_RESET_N"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts deleted file mode 100644 index c4b2efbfdf56..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include -#include - -/{ - model = "ASRock E3C246D4I BMC"; - compatible = "asrock,e3c246d4i-bmc", "aspeed,ast2500"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - /* BMC_HB_LED_N */ - gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - system-fault { - /* SYSTEM_FAULT_LED_N */ - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; - panic-indicator; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - uid-button { - label = "uid-button"; - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, - <&adc 10>, <&adc 11>, <&adc 12>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; /* 50 MHz */ -#include "openbmc-flash-layout.dtsi" - }; -}; - -&uart5 { - status = "okay"; -}; - -&vuart { - status = "okay"; - aspeed,lpc-io-reg = <0x2f8>; - aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c1 { - status = "okay"; - - /* thermal sensor, one diode run to a disconnected header */ - w83773g@4c { - compatible = "nuvoton,w83773g"; - reg = <0x4c>; - }; -}; - -&i2c3 { - status = "okay"; - - /* FRU EEPROM */ - eeprom@57 { - compatible = "st,24c128", "atmel,24c128"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -&video { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /* A */ "BMC_MAC1_INTB", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", - "", "", "", "", - /* B */ "", "", "", "", "", "IRQ_BMC_PCH_SMI_LPC_N", "", "", - /* C */ "", "", "", "", "", "", "", "", - /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", - "", "", "", "", - /* E */ "", "", "", "", "", "", "", "", - /* F */ "LOCATORLED_STATUS_N", "LOCATORBTN", "", "", - "", "", "BMC_PCH_SCI_LPC", "BMC_NCSI_MUX_CTL", - /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", - "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "SML0ALERT", - /* H */ "FM_ME_RCVR_N", "O_PWROK", "SKL_CNL_R", "D4_DIMM_EVENT_3V_N", - "MFG_MODE_N", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", - /* I */ "", "", "", "", "", "", "", "", - /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "BMC_SMI", "", - "", "", "", "", - /* K */ "", "", "", "", "", "", "", "", - /* L */ "BMC_CTS1", "BMC_DCD1", "BMC_DSR1", "BMC_RI1", - "BMC_DTR1", "BMC_RTS1", "BMC_TXD1", "BMC_RXD1", - /* M */ "BMC_LAN0_DIS_N", "BMC_LAN1_DIS_N", "", "", - "", "", "", "", - /* N */ "", "", "", "", "", "", "", "", - /* O */ "", "", "", "", "", "", "", "", - /* P */ "", "", "", "", "", "", "", "", - /* Q */ "", "", "", "", - "BMC_SBM_PRESENT_1_N", "BMC_SBM_PRESENT_2_N", - "BMC_SBM_PRESENT_3_N", "BMC_PCIE_WAKE_N", - /* R */ "", "", "", "", "", "", "", "", - /* S */ "PCHHOT_BMC_N", "", "RSMRST", - "", "", "", "", "", - /* T */ "", "", "", "", "", "", "", "", - /* U */ "", "", "", "", "", "", "", "", - /* V */ "", "", "", "", "", "", "", "", - /* W */ "PS_PWROK", /* dummy always-high signal */ - "", "", "", "", "", "", "", - /* X */ "", "", "", "", "", "", "", "", - /* Y */ "SLP_S3", "SLP_S5", "", "", "", "", "", "", - /* Z */ "CPU_CATERR_BMC_PCH_N", "", "SYSTEM_FAULT_LED_N", "BMC_THROTTLE_N", - "", "", "", "", - /* AA */ "CPU1_THERMTRIP_LATCH_N", "", "CPU1_PROCHOT_N", "", - "", "", "IRQ_SMI_ACTIVE_N", "FM_BIOS_POST_CMPLT_N", - /* AB */ "", "", "ME_OVERRIDE", "BMC_DMI_MODIFY", - "", "", "", "", - /* AC */ "LAD0", "LAD1", "LAD2", "LAD3", - "CK_33M_BMC", "LFRAME", "SERIRQ", "S_PLTRST"; - - /* Assert BMC_READY so BIOS doesn't sit around waiting for it */ - bmc-ready { - gpio-hog; - gpios = ; - output-high; - }; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&peci0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts deleted file mode 100644 index 4554abf0c7cd..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts +++ /dev/null @@ -1,261 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include - -/{ - model = "ASRock ROMED8HM3 BMC v1.00"; - compatible = "asrock,romed8hm3-bmc", "aspeed,ast2500"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - system-fault { - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - panic-indicator; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; /* 50 MHz */ -#include "openbmc-flash-layout-64.dtsi" - }; -}; - -&uart5 { - status = "okay"; -}; - -&vuart { - status = "okay"; - aspeed,lpc-io-reg = <0x2f8>; - aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c0 { - status = "okay"; - - /* inlet temp sensor */ - w83773g@4c { - compatible = "nuvoton,w83773g"; - reg = <0x4c>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - /* IPB temp sensor */ - w83773g@4c { - compatible = "nuvoton,w83773g"; - reg = <0x4c>; - }; - - /* IPB PMIC */ - lm25066@40 { - compatible = "lm25066"; - reg = <0x40>; - shunt-resistor-micro-ohms = <1000>; - }; - - /* 12VSB PMIC */ - lm25066@41 { - compatible = "lm25066"; - reg = <0x41>; - shunt-resistor-micro-ohms = <10000>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - /* Baseboard FRU eeprom */ - eeprom@50 { - compatible = "st,24c128", "atmel,24c128"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&video { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; - }; - - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; - }; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", - "", "", "", "", - /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "", - /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "", - /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", - "", "", "", "PSU_FAN_FAIL_N", - /* E */ "", "", "", "", "", "", "", "", - /* F */ "NIC_PWR_GOOD", "PRSNTB0", "PRSNTB1", "PRSNTB2", - "PRSNTB3", "", "3VSB_PCIE1_PG", "12V_PCIE1_PG", - /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", - "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "BMC_ALERT4_N", - /* H */ "X24_C1_PRSNT", "X24_C2_PRSNT", "X24_C3_PRSNT", "FM_MEM_THERM_EVENT_BMC_R_N", - "FACMODE", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", - /* I */ "", "", "", "", "", "", "", "", - /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "", "P0_MA_DDR_QS_CS_N", - "", "", "", "", - /* K */ "", "", "", "", "", "", "", "", - /* L */ "", "", "", "", "", "", "", "", - /* M */ "", "", "MEZZ_PWRBRK_N", "OCP_HP_RST_EN", - "MAIN_PWR_EN_G", "BMC_MAIN_EN", "AUX_PWR_EN_G", "BMC_AUX_EN", - /* N */ "", "", "", "", "", "", "", "", - /* O */ "", "", "", "", "", "", "", "", - /* P */ "", "", "", "", "", "", "", "", - /* Q */ "", "", "", "", - "BMC_SMB_PRESENT_1_N", "BMC_SMB_PRESENT_2_N", - "BMC_SMB_PRESENT_3_N", "BMC_PCIE_WAKE_N", - /* R */ "", "", "THERMALTRIP_CLEAR_N", "", "", "", "", "", - /* S */ "", "", "", "", "", "", "", "", - /* T */ "", "", "", "", "", "", "", "", - /* U */ "", "", "", "", "", "", "", "", - /* V */ "", "", "", "", "", "", "", "", - /* W */ "", "", "", "", "", "", "", "", - /* X */ "", "", "", "", "", "", "", "", - /* Y */ "SLP_S3", "SLP_S4_S5", "NODE_ID_1", "NODE_ID_2", "", "", "", "", - /* Z */ "", "", "SYSTEM_FAULT_LED_N", "FAST_THROTTLE_N", - "", "", "", "", - /* AA */ "FM_CPU0_IBMC_THERMTRIP_N", "", "PROCHOT_L_G", "", - "", "", "", "", - /* AB */ "BMC_FORCE_SELFREFRESH", "PWRGD_OUT", "", "IRQ_BMC_PCH_SMI_LPC_N", - "", "", "", "", - /* AC */ "", "", "", "", "", "", "", ""; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts deleted file mode 100644 index f75cad41ae6f..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ /dev/null @@ -1,940 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (C) 2020 Bytedance. -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include -#include - -/ { - model = "Bytedance G220A BMC"; - compatible = "bytedance,g220a-bmc", "aspeed,ast2500"; - - aliases { - serial4 = &uart5; - i2c14 = &channel_3_0; - i2c15 = &channel_3_1; - i2c16 = &channel_3_2; - i2c17 = &channel_3_3; - i2c18 = &channel_6_0; - i2c19 = &channel_6_1; - i2c20 = &channel_6_2; - i2c21 = &channel_6_3; - i2c22 = &channel_6_4; - i2c23 = &channel_6_5; - i2c24 = &channel_6_6; - i2c25 = &channel_6_7; - i2c26 = &channel_6_8; - i2c27 = &channel_6_9; - i2c28 = &channel_6_10; - i2c29 = &channel_6_11; - i2c30 = &channel_6_12; - i2c31 = &channel_6_13; - i2c32 = &channel_6_14; - i2c33 = &channel_6_15; - i2c34 = &channel_6_16; - i2c35 = &channel_6_17; - i2c36 = &channel_6_18; - i2c37 = &channel_6_19; - i2c38 = &channel_6_20; - i2c39 = &channel_6_21; - i2c40 = &channel_6_22; - i2c41 = &channel_6_23; - i2c42 = &channel_6_24; - i2c43 = &channel_6_25; - i2c44 = &channel_10_0; - i2c45 = &channel_10_1; - i2c46 = &channel_10_2; - i2c47 = &channel_10_3; - i2c48 = &channel_10_4; - i2c49 = &channel_10_5; - i2c50 = &channel_10_6; - i2c51 = &channel_10_7; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@bc000000 { - no-map; - reg = <0xbc000000 0x04000000>; /* 64M */ - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; - - leds { - compatible = "gpio-leds"; - bmc_alive { - label = "bmc_alive"; - gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - led-pattern = <1000 1000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - event-burn-in-signal { - label = "burn-in"; - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-rear-riser1-presence { - label = "rear-riser1-presence"; - gpios = <&pca0 1 GPIO_ACTIVE_LOW>; - linux,code = <1>; - }; - - event-alrt-pvddq-cpu0 { - label = "alrt-pvddq-cpu0"; - gpios = <&pca0 8 GPIO_ACTIVE_LOW>; - linux,code = <2>; - }; - - event-rear-riser0-presence { - label = "rear-riser0-presence"; - gpios = <&pca0 9 GPIO_ACTIVE_LOW>; - linux,code = <3>; - }; - - event-fault-pvddq-cpu0 { - label = "fault-pvddq-cpu0"; - gpios = <&pca0 10 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - event-alrt-pvddq-cpu1 { - label = "alrt-pvddq-cpu1"; - gpios = <&pca0 11 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - event-fault-pvddq-cpu1 { - label = "alrt-pvddq-cpu1"; - gpios = <&pca0 12 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-fault-pvccin-cpu1 { - label = "fault-pvccin-cpuq"; - gpios = <&pca0 13 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - event-bmc-rom0-wp { - label = "bmc-rom0-wp"; - gpios = <&pca1 0 GPIO_ACTIVE_LOW>; - linux,code = <8>; - }; - - event-bmc-rom1-wp { - label = "bmc-rom1-wp"; - gpios = <&pca1 1 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca1 2 GPIO_ACTIVE_LOW>; - linux,code = <10>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca1 3 GPIO_ACTIVE_LOW>; - linux,code = <11>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca1 4 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca1 5 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - - event-fan4-presence { - label = "fan4-presence"; - gpios = <&pca1 6 GPIO_ACTIVE_LOW>; - linux,code = <14>; - }; - - event-fan5-presence { - label = "fan5-presence"; - gpios = <&pca1 7 GPIO_ACTIVE_LOW>; - linux,code = <15>; - }; - - event-front-bp1-presence { - label = "front-bp1-presence"; - gpios = <&pca1 8 GPIO_ACTIVE_LOW>; - linux,code = <16>; - }; - - event-rear-bp-presence { - label = "rear-bp-presence"; - gpios = <&pca1 9 GPIO_ACTIVE_LOW>; - linux,code = <17>; - }; - - event-fault-pvccin-cpu0 { - label = "fault-pvccin-cpu0"; - gpios = <&pca1 10 GPIO_ACTIVE_LOW>; - linux,code = <18>; - }; - - event-alrt-p1v05-pvcc { - label = "alrt-p1v05-pvcc1"; - gpios = <&pca1 11 GPIO_ACTIVE_LOW>; - linux,code = <19>; - }; - - event-fault-p1v05-pvccio { - label = "alrt-p1v05-pvcc1"; - gpios = <&pca1 12 GPIO_ACTIVE_LOW>; - linux,code = <20>; - }; - - event-alrt-p1v8-pvccio { - label = "alrt-p1v8-pvccio"; - gpios = <&pca1 13 GPIO_ACTIVE_LOW>; - linux,code = <21>; - }; - - event-fault-p1v8-pvccio { - label = "fault-p1v8-pvccio"; - gpios = <&pca1 14 GPIO_ACTIVE_LOW>; - linux,code = <22>; - }; - - event-front-bp0-presence { - label = "front-bp0-presence"; - gpios = <&pca1 15 GPIO_ACTIVE_LOW>; - linux,code = <23>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64-alt.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bios"; - spi-max-frequency = <100000000>; - }; -}; - -&adc { - status = "okay"; -}; - -&wdt2 { - status = "okay"; - aspeed,alt-boot; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "SMRST_OCP_N","MAC2_LINK","BMC_CPLD_SMB_RST_R_N","BMC_CPLD_GPIO0", - "","","","", - /*B0-B7*/ "BMC_INIT_R_OK","FM_BOARD_REV_ID2","FM_PROJECT_ID7","FAULT_P12V_STBY_N", - "","CPU0_PROCHOT_LVT3_N","","BIOS_LOAD_DEFAULT_R_N", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "FM_PROJECT_ID0","FM_PROJECT_ID1","FM_PROJECT_ID2","FM_PROJECT_ID3", - "FM_PROJECT_ID4","FM_PROJECT_ID5","","", - /*F0-F7*/ "PSU0_PRSNT_N","PSU1_PRSNT_N","","FAULT_P12V_NVME_N", - "BIOS_DEBUG_MODE_R_N","DISABLE_CPU_DDR_R_SPD","COOLING_STRATEGY", - "PCH_GLB_RST_N", - /*G0-G7*/ "P12V_PMBUS_ALERT_N","CPLD_ALERT_N","BMC_RELOAD_N", - "P12V_PVDDQ_PMBUS_ALERT_N","BMC_JTAG_TCK_MUX_R_SEL","","NMI_OUT", - "NMI_BUTTON", - /*H0-H7*/ "BMC_CPLD_JTAG_TDI","BMC_CPLD_JTAG_TDO","BMC_CPLD_JTAG_TCK", - "BMC_CPLD_JTAG_TMS","FM_PROJECT_ID6","FM_BOARD_REV_ID0", - "PCA9546_U70_RST_N","IRQ_SML0_ALERT_N", - /*I0-I7*/ "FAULT_FRONT_RISER_P12V_N","FAULT_OCP_P12V_N","FM_BMC_PCH_SCI_R_N", - "","","","","", - /*J0-J7*/ "FM_CPU0_SKTOCC_N","FM_CPU1_SKTOCC_N","FM_CPU1_DISABLE_COD_N", - "","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "P12V_FAULT_N","PWRGD_P12V_PCIE_RISER","","LEAKAGE_DETECT_INPUT_N", - "","IRQ_SML1_PMBUS_ALERT_N","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","CHASSIS_INTRUSION", - /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", - "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", - /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", - "FM_BMC_XDP_DEBUG_EN","","STRAP_BMC_BATTERY_GPIOS5","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","PWRGD_PSU0_PWROK","CPU1_PROCHOT_LVT3_N","IRQ_BMC_PCH_SMI_LPC_N", - "","","","", - /*Z0-Z7*/ "XDP_PRSNT_N","BMC_XDP_SYS_PWROK","BMC_XDP_JTAG_SEL", - "PCH_BMC_SMI_ACTIVE_R_N","","","","", - /*AA0-AA7*/ "PWRGD_P12V_STBY_OCP","PS_PWROK","RST_PLTRST_BMC_R_N","HDA_SDO_R", - "FM_SLPS4_R_N","PWRGD_PSU1_PWROK","POWER_BUTTON","POWER_OUT", - /*AB0-AB7*/ "","RESET_OUT","SPI_BIOS_MODE_SELECT","POST_COMPLETE","","","","", - /*AC0-AC7*/ "","","","","","","","CPLD_PLTRST_B_N"; -}; - -&kcs3 { - aspeed,lpc-io-reg = <0xCA2>; - status = "okay"; -}; - -&kcs4 { - aspeed,lpc-io-reg = <0xCA4>; - status = "okay"; -}; - -&lpc_snoop { - snoop-ports = <0x80>; - status = "okay"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default - &pinctrl_nrts2_default - &pinctrl_ndtr2_default - &pinctrl_ndsr2_default - &pinctrl_ncts2_default - &pinctrl_ndcd2_default - &pinctrl_nri2_default>; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - channel_3_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_3_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_3_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_3_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c4 { - status = "okay"; - ipmb0@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - i2c-switch@72 { - compatible = "nxp,pca9548"; - reg = <0x72>; - #address-cells = <1>; - #size-cells = <0>; - channel_6_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_6_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_6_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_6_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - channel_6_4: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - channel_6_5: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - channel_6_6: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - channel_6_7: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - channel_6_8: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - channel_6_12: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - }; - - channel_6_13: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_6_14: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_6_15: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - channel_6_9: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - channel_6_16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - }; - - channel_6_17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_6_18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_6_19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - channel_6_10: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - channel_6_20: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_6_21: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_6_22: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_6_23: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - channel_6_11: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - channel_6_24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_6_25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - pca0:pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - }; - - pca1:pca9555@25 { - compatible = "nxp,pca9555"; - reg = <0x25>; - - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - channel_10_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_10_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_10_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_10_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - channel_10_4: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_10_5: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_10_6: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_10_7: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; - }; - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; - }; - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; - }; - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; - }; -}; - -&gpio { - pin_gpio_i3 { - gpio-hog; - gpios = ; - output-low; - line-name = "NCSI_BMC_R_SEL"; - }; - - pin_gpio_b6 { - gpio-hog; - gpios = ; - output-low; - line-name = "EN_NCSI_SWITCH_N"; - }; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&vhub { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts deleted file mode 100644 index 6600f7e9bf5e..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -#define EFUSE_OUTPUT(n) \ - efuse##n { \ - compatible = "regulator-output"; \ - vout-supply = <&efuse##n>; \ - } - -#define __stringify(x) #x - -#define EFUSE(hexaddr, num) \ - efuse@##hexaddr { \ - compatible = "lm25066"; \ - reg = <0x##hexaddr>; \ - shunt-resistor-micro-ohms = <675>; \ - regulators { \ - efuse##num: vout0 { \ - regulator-name = __stringify(efuse##num##-reg); \ - }; \ - }; \ - } - -/{ - model = "Delta Power AHE-50DC"; - compatible = "delta,ahe50dc-bmc", "aspeed,ast2400"; - - aliases { - serial4 = &uart5; - - /* - * pca9541-arbitrated logical i2c buses are numbered as the - * corresponding physical bus plus 20 - */ - i2c20 = &i2carb0; - i2c21 = &i2carb1; - i2c22 = &i2carb2; - i2c23 = &i2carb3; - i2c24 = &i2carb4; - i2c26 = &i2carb6; - i2c27 = &i2carb7; - i2c28 = &i2carb8; - i2c32 = &i2carb12; - }; - - chosen { - stdout-path = &uart3; - bootargs = "console=ttyS2,115200n8 earlycon"; - }; - - memory@40000000 { - reg = <0x40000000 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - panic { - gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "panic"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; - }; - - EFUSE_OUTPUT(01); - EFUSE_OUTPUT(02); - EFUSE_OUTPUT(03); - EFUSE_OUTPUT(04); - EFUSE_OUTPUT(05); - EFUSE_OUTPUT(06); - EFUSE_OUTPUT(07); - EFUSE_OUTPUT(08); - EFUSE_OUTPUT(09); - EFUSE_OUTPUT(10); - EFUSE_OUTPUT(11); - EFUSE_OUTPUT(12); - EFUSE_OUTPUT(13); - EFUSE_OUTPUT(14); - EFUSE_OUTPUT(15); - EFUSE_OUTPUT(16); - EFUSE_OUTPUT(17); - EFUSE_OUTPUT(18); - EFUSE_OUTPUT(19); - EFUSE_OUTPUT(20); - EFUSE_OUTPUT(21); - EFUSE_OUTPUT(22); - EFUSE_OUTPUT(23); - EFUSE_OUTPUT(24); - EFUSE_OUTPUT(25); - EFUSE_OUTPUT(26); - EFUSE_OUTPUT(27); - EFUSE_OUTPUT(28); - EFUSE_OUTPUT(29); - EFUSE_OUTPUT(30); - EFUSE_OUTPUT(31); - EFUSE_OUTPUT(32); - EFUSE_OUTPUT(33); - EFUSE_OUTPUT(34); - EFUSE_OUTPUT(35); - EFUSE_OUTPUT(36); - EFUSE_OUTPUT(37); - EFUSE_OUTPUT(38); - EFUSE_OUTPUT(39); - EFUSE_OUTPUT(40); - EFUSE_OUTPUT(41); - EFUSE_OUTPUT(42); - EFUSE_OUTPUT(43); - EFUSE_OUTPUT(44); - EFUSE_OUTPUT(45); - EFUSE_OUTPUT(46); - EFUSE_OUTPUT(47); - EFUSE_OUTPUT(48); - EFUSE_OUTPUT(49); - EFUSE_OUTPUT(50); - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "flash0"; - spi-max-frequency = <50000000>; // 50 MHz -#include "openbmc-flash-layout.dtsi" - }; -}; - -&uart3 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@79 { - compatible = "nxp,pca9541"; - reg = <0x79>; - - i2carb0: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - /* lm25066 efuses @ 10-17, 40-47, 50-57 */ - EFUSE(10, 03); - EFUSE(11, 04); - EFUSE(12, 01); - EFUSE(13, 02); - EFUSE(14, 13); - EFUSE(15, 14); - EFUSE(16, 15); - EFUSE(17, 16); - EFUSE(40, 12); - EFUSE(41, 11); - EFUSE(42, 10); - EFUSE(43, 09); - EFUSE(44, 08); - EFUSE(45, 07); - EFUSE(46, 05); - EFUSE(47, 06); - EFUSE(50, 17); - EFUSE(51, 18); - EFUSE(52, 20); - EFUSE(53, 19); - EFUSE(54, 22); - EFUSE(55, 21); - EFUSE(56, 24); - EFUSE(57, 23); - }; - }; -}; - -&i2c1 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@72 { - compatible = "nxp,pca9541"; - reg = <0x72>; - - i2carb1: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c2 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@73 { - compatible = "nxp,pca9541"; - reg = <0x73>; - - i2carb2: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c3 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@74 { - compatible = "nxp,pca9541"; - reg = <0x74>; - - i2carb3: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c4 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@7a { - compatible = "nxp,pca9541"; - reg = <0x7a>; - - i2carb4: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* lm25066 efuses @ 10-17, 40-47, 50-57, 59, 5a */ - EFUSE(10, 27); - EFUSE(11, 28); - EFUSE(12, 25); - EFUSE(13, 26); - EFUSE(14, 37); - EFUSE(15, 38); - EFUSE(16, 39); - EFUSE(17, 40); - EFUSE(40, 36); - EFUSE(41, 35); - EFUSE(42, 34); - EFUSE(43, 33); - EFUSE(44, 32); - EFUSE(45, 31); - EFUSE(46, 29); - EFUSE(47, 30); - EFUSE(50, 41); - EFUSE(51, 42); - EFUSE(52, 44); - EFUSE(53, 43); - EFUSE(54, 46); - EFUSE(55, 45); - EFUSE(56, 48); - EFUSE(57, 47); - EFUSE(59, 49); - EFUSE(5a, 50); - }; - }; -}; - -&i2c6 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@75 { - compatible = "nxp,pca9541"; - reg = <0x75>; - - i2carb6: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c7 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@76 { - compatible = "nxp,pca9541"; - reg = <0x76>; - - i2carb7: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c8 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@7c { - compatible = "nxp,pca9541"; - reg = <0x7c>; - - i2carb8: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - fancontrol@30 { - compatible = "delta,ahe50dc-fan"; - reg = <0x30>; - }; - - /* Baseboard FRU eeprom */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - }; -}; - -&i2c12 { - status = "okay"; - bus-frequency = <200000>; - - pca9541@71 { - compatible = "nxp,pca9541"; - reg = <0x71>; - - i2carb12: i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /* A */ "", "", "", "", "", "", "", "", - /* B */ "", "", "", "", "", "", "", "", - /* C */ "RESET_PEER_N", "HEARTBEAT_OUT", "", "", "", "", "", "", - /* D */ "", "", "", "", "", "", "", "", - /* E */ "DOOM_N", "", "", "", "", "LED_PWR_BLUE", "", "", - /* F */ "", "", "", "", "", "", "", "", - /* G */ "", "", "", "", "", "", "", "", - /* H */ "", "", "", "", "", "", "", "", - /* I */ "", "", "", "", "", "", "", "", - /* J */ "", "", "BMC_ID", "", "", "", "", "", - /* K */ "", "", "", "", "", "", "", "", - /* L */ "", "", "", "", "", "", "", "", - /* M */ "", "", "", "", "", "", "", "", - /* N */ "", "", "", "", "", "", "", "", - /* O */ "", "", "", "", "", "", "", "", - /* P */ "LED_GREEN", "", "LED_RED", "", "", "", "", "", - /* Q */ "", "", "", "", "", "", "", "", - /* R */ "", "", "", "", "", "", "", "", - /* S */ "", "", "", "", "", "", "", "", - /* T */ "", "", "", "", "", "", "", "", - /* U */ "", "", "", "", "", "", "", "", - /* V */ "", "", "", "", "", "", "", "", - /* W */ "", "", "", "", "", "", "", "", - /* X */ "", "", "", "", "", "", "", "", - /* Y */ "HEARTBEAT_IN", "BOARDREV0", "BOARDREV1", "", - /* Z */ "", "", "", "", "", "", "", "", - /* AA */ "", "", "", "", "", "", "", "", - /* AB */ "", "", "", ""; - - /* - * I don't rightly know what this GPIO really *is*, but setting it to - * zero causes the fans to run at full speed, after which setting it - * back to one causes a power output glitch, so install a hog to keep - * it at one as a failsafe to ensure nothing accidentally touches it. - */ - doom-guardrail { - gpio-hog; - gpios = ; - output-low; - }; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts deleted file mode 100644 index e899de681f47..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ /dev/null @@ -1,1077 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2021 Facebook Inc. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Facebook Bletchley BMC"; - compatible = "facebook,bletchley-bmc", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - bootargs = "console=ttyS4,57600n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, - <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; - }; - - spi1_gpio: spi1-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; - spi-max-frequency = <33000000>; - reg = <0>; - }; - }; - - switchphy: ethernet-phy@0 { - // Fixed link - }; - - front_gpio_leds { - compatible = "gpio-leds"; - sys_log_id { - default-state = "off"; - gpios = <&front_leds 0 GPIO_ACTIVE_LOW>; - }; - }; - - fan_gpio_leds { - compatible = "gpio-leds"; - fan0_blue { - retain-state-shutdown; - default-state = "on"; - gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>; - }; - fan1_blue { - retain-state-shutdown; - default-state = "on"; - gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>; - }; - fan2_blue { - retain-state-shutdown; - default-state = "on"; - gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>; - }; - fan3_blue { - retain-state-shutdown; - default-state = "on"; - gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>; - }; - fan0_amber { - retain-state-shutdown; - default-state = "off"; - gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>; - }; - fan1_amber { - retain-state-shutdown; - default-state = "off"; - gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>; - }; - fan2_amber { - retain-state-shutdown; - default-state = "off"; - gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>; - }; - fan3_amber { - retain-state-shutdown; - default-state = "off"; - gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>; - }; - }; - - sled1_gpio_leds { - compatible = "gpio-leds"; - sled1_amber { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; - }; - sled1_blue { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; - }; - }; - - sled2_gpio_leds { - compatible = "gpio-leds"; - sled2_amber { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; - }; - sled2_blue { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; - }; - }; - - sled3_gpio_leds { - compatible = "gpio-leds"; - sled3_amber { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; - }; - sled3_blue { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; - }; - }; - - sled4_gpio_leds { - compatible = "gpio-leds"; - sled4_amber { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; - }; - sled4_blue { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; - }; - }; - - sled5_gpio_leds { - compatible = "gpio-leds"; - sled5_amber { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; - }; - sled5_blue { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; - }; - }; - - sled6_gpio_leds { - compatible = "gpio-leds"; - sled6_amber { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>; - }; - sled6_blue { - retain-state-shutdown; - default-state = "keep"; - gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - presence-sled1 { - label = "presence-sled1"; - gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - presence-sled2 { - label = "presence-sled2"; - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - presence-sled3 { - label = "presence-sled3"; - gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - presence-sled4 { - label = "presence-sled4"; - gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - presence-sled5 { - label = "presence-sled5"; - gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - presence-sled6 { - label = "presence-sled6"; - gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - vbus_sled1: vbus_sled1 { - compatible = "regulator-fixed"; - regulator-name = "vbus_sled1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&sled1_ioexp 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_sled2: vbus_sled2 { - compatible = "regulator-fixed"; - regulator-name = "vbus_sled2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&sled2_ioexp 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_sled3: vbus_sled3 { - compatible = "regulator-fixed"; - regulator-name = "vbus_sled3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&sled3_ioexp 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_sled4: vbus_sled4 { - compatible = "regulator-fixed"; - regulator-name = "vbus_sled4"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&sled4_ioexp 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_sled5: vbus_sled5 { - compatible = "regulator-fixed"; - regulator-name = "vbus_sled5"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&sled5_ioexp 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_sled6: vbus_sled6 { - compatible = "regulator-fixed"; - regulator-name = "vbus_sled6"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&sled6_ioexp 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&mac2 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&switchphy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii3_default>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; - }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <50000000>; - }; -}; - -&i2c0 { - status = "okay"; - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; - }; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled1_ioexp41: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED1_SWD_MUX", "SLED1_XRES_SWD_N", - "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN"; - }; - - sled1_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - gpio-line-names = - "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", - "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", - "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", - "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; - }; - - sled1_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","SLED1_MD_REF_PWM", - "","","","", - "","","","", - "","","",""; - }; - - sled1_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - interrupt-parent = <&gpio0>; - interrupts = ; - vbus-supply = <&vbus_sled1>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - pd-disable; - typec-power-opmode = "default"; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; - }; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled2_ioexp41: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED2_SWD_MUX", "SLED2_XRES_SWD_N", - "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN"; - }; - - sled2_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - gpio-line-names = - "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", - "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", - "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", - "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; - }; - - sled2_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","SLED2_MD_REF_PWM", - "","","","", - "","","","", - "","","",""; - }; - - sled2_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - interrupt-parent = <&gpio0>; - interrupts = ; - vbus-supply = <&vbus_sled2>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - pd-disable; - typec-power-opmode = "default"; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c2 { - status = "okay"; - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; - }; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled3_ioexp41: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED3_SWD_MUX", "SLED3_XRES_SWD_N", - "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN"; - }; - - sled3_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - gpio-line-names = - "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", - "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", - "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", - "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; - }; - - sled3_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","SLED3_MD_REF_PWM", - "","","","", - "","","","", - "","","",""; - }; - - sled3_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - interrupt-parent = <&gpio0>; - interrupts = ; - vbus-supply = <&vbus_sled3>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - pd-disable; - typec-power-opmode = "default"; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c3 { - status = "okay"; - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; - }; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled4_ioexp41: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED4_SWD_MUX", "SLED4_XRES_SWD_N", - "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN"; - }; - - sled4_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - gpio-line-names = - "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", - "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", - "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", - "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; - }; - - sled4_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","SLED4_MD_REF_PWM", - "","","","", - "","","","", - "","","",""; - }; - - sled4_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - interrupt-parent = <&gpio0>; - interrupts = ; - vbus-supply = <&vbus_sled4>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - pd-disable; - typec-power-opmode = "default"; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c4 { - status = "okay"; - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; - }; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled5_ioexp41: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED5_SWD_MUX", "SLED5_XRES_SWD_N", - "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN"; - }; - - sled5_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - gpio-line-names = - "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", - "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", - "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", - "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; - }; - - sled5_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","SLED5_MD_REF_PWM", - "","","","", - "","","","", - "","","",""; - }; - - sled5_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - interrupt-parent = <&gpio0>; - interrupts = ; - vbus-supply = <&vbus_sled5>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - pd-disable; - typec-power-opmode = "default"; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c5 { - status = "okay"; - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; - }; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled6_ioexp41: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED6_SWD_MUX", "SLED6_XRES_SWD_N", - "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN"; - }; - - sled6_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - gpio-line-names = - "SLED6_MS_DETECT1","SLED6_VBUS_BMC_EN","SLED6_INA230_ALERT","SLED6_P12V_STBY_ALERT", - "SLED6_SSD_ALERT","SLED6_MS_DETECT0","SLED6_RST_CCG5","SLED6_FUSB302_INT", - "SLED6_MD_STBY_RESET","SLED6_MD_IOEXP_EN_FAULT","SLED6_MD_DIR","SLED6_MD_DECAY", - "SLED6_MD_MODE1","SLED6_MD_MODE2","SLED6_MD_MODE3","power-host6"; - }; - - sled6_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled6-amber","led-sled6-blue","SLED6_RST_IOEXP","SLED6_MD_REF_PWM", - "","","","", - "","","","", - "","","",""; - }; - - sled6_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - interrupt-parent = <&gpio0>; - interrupts = ; - vbus-supply = <&vbus_sled6>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - pd-disable; - typec-power-opmode = "default"; - }; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c6 { - status = "okay"; - - eeprom@56 { - compatible = "atmel,24c64"; - reg = <0x56>; - }; - - rtc@51 { - /* in-chip rtc disabled, use external rtc (battery-backed) */ - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&i2c7 { - status = "okay"; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c9 { - status = "okay"; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; -}; - -&i2c10 { - status = "okay"; - - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - front_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-fault-identify","power-p5v-stby-good", - "power-p1v0-dvdd-good","power-p1v0-avdd-good", - "","","","", - "","","","", - "","","",""; - }; -}; - -&i2c12 { - status = "okay"; - - adm1278@11 { - compatible = "adi,adm1278"; - reg = <0x11>; - shunt-resistor-micro-ohms = <300>; - adi,volt-curr-sample-average = <128>; - adi,power-sample-average = <128>; - }; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - tmp421@4d { - compatible = "ti,tmp421"; - reg = <0x4d>; - }; - - fan_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "presence-fan0","presence-fan1", - "presence-fan2","presence-fan3", - "power-fan0-good","power-fan1-good", - "power-fan2-good","power-fan3-good", - "","","","", - "","","",""; - }; -}; - -&i2c13 { - multi-master; - aspeed,hw-timeout-ms = <1000>; - status = "okay"; - - //USB Debug Connector - ipmb13@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiov2_unbiased_default>; - - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N", - "SEL_SPI2_MUX","SPI2_MUX1", - "SPI2_MUX2","SPI2_MUX3", - "","FUSB302_SLED3_INT_N", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK", - "BMC_SLED3_STCK","BMC_SLED4_STCK", - "BMC_SLED5_STCK","BMC_SLED6_STCK", - "","", - /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL", - "PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","", - /*H0-H7*/ "presence-riser1","presence-riser2", - "presence-sled1","presence-sled2", - "presence-sled3","presence-sled4", - "presence-sled5","presence-sled6", - /*I0-I7*/ "REV_ID0","", - "REV_ID1","REV_ID2", - "","BSM_FLASH_WP_STATUS", - "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","BMC_RTC_INT","","", - /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N", - "ALERT_SLED3_N","ALERT_SLED4_N", - "ALERT_SLED5_N","ALERT_SLED6_N", - "","USB_DEBUG_PWR_BTN_N", - /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", - "LED_POSTCODE_2","LED_POSTCODE_3", - "LED_POSTCODE_4","LED_POSTCODE_5", - "LED_POSTCODE_6","LED_POSTCODE_7", - /*O0-O7*/ "","","","", - "","BOARD_ID0","BOARD_ID1","BOARD_ID2", - /*P0-P7*/ "","","","","","","","BMC_HEARTBEAT", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","BAT_DETECT", - "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N", - "P12V_AUX_ALERT1_N","PSU_PRSNT", - "USB2_SEL0_A","USB2_SEL1_A", - "USB2_SEL0_B","USB2_SEL1_B", - /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N", - "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N", - "","","","", - /*Z0-Z7*/ "","","","","","","",""; -}; - -&adc0 { - vref = <1800>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; -}; - -&adc1 { - vref = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&mdio0 { - status = "okay"; - /* TODO: Add Marvell 88E6191X */ -}; - -&mdio3 { - status = "okay"; - /* TODO: Add Marvell 88X3310 */ -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&pinctrl { - pinctrl_gpiov2_unbiased_default: gpiov2 { - pins = "AD14"; - bias-disable; - }; -}; - -&wdt1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; - aspeed,reset-type = "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration = <256>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts deleted file mode 100644 index 5cd060029ea9..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts +++ /dev/null @@ -1,544 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. - -/dts-v1/; - -#include -#include "ast2600-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Cloudripper BMC"; - compatible = "facebook,cloudripper-bmc", "aspeed,ast2600"; - - aliases { - /* - * PCA9548 (1-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * PCA9548 (2-0070) provides 8 channels connecting to - * SCM (System Controller Module). - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * PCA9548 (3-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - - /* - * PCA9548 (8-0070) provides 8 channels connecting to - * PDB (Power Delivery Board). - */ - i2c40 = &imux40; - i2c41 = &imux41; - i2c42 = &imux42; - i2c43 = &imux43; - i2c44 = &imux44; - i2c45 = &imux45; - i2c46 = &imux46; - i2c47 = &imux47; - - /* - * PCA9548 (15-0076) provides 8 channels connecting to - * FCM (Fan Controller Module). - */ - i2c48 = &imux48; - i2c49 = &imux49; - i2c50 = &imux50; - i2c51 = &imux51; - i2c52 = &imux52; - i2c53 = &imux53; - i2c54 = &imux54; - i2c55 = &imux55; - }; - - spi_gpio: spi { - num-chipselects = <2>; - cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, - <&gpio0 ASPEED_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - - eeprom@1 { - compatible = "atmel,at93c46d"; - spi-max-frequency = <250000>; - data-size = <16>; - spi-cs-high; - reg = <1>; - }; - }; -}; - -&ehci1 { - status = "okay"; -}; - -/* - * "mdio1" is connected to the MDC/MDIO interface of the on-board - * management switch (whose ports are connected to BMC, Host and front - * panel ethernet port). - */ -&mdio1 { - status = "okay"; -}; - -&mdio3 { - status = "okay"; - - ethphy1: ethernet-phy@13 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0d>; - }; -}; - -&mac3 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; -}; - -&i2c0 { - multi-master; - bus-frequency = <1000000>; -}; - -&i2c1 { - /* - * PCA9548 (1-0070) provides 8 channels connecting to SMB (Switch - * Main Board). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c2 { - /* - * PCA9548 (2-0070) provides 8 channels connecting to SCM (System - * Controller Module). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - /* - * PCA9548 (3-0070) provides 8 channels connecting to SMB (Switch - * Main Board). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c6 { - lp5012@14 { - compatible = "ti,lp5012"; - reg = <0x14>; - #address-cells = <1>; - #size-cells = <0>; - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "sys"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "fan"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "psu"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "scm"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - }; -}; - -&i2c8 { - /* - * PCA9548 (8-0070) provides 8 channels connecting to PDB (Power - * Delivery Board). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux40: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux41: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux42: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux43: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux44: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux45: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux46: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux47: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c15 { - /* - * PCA9548 (15-0076) provides 8 channels connecting to FCM (Fan - * Controller Module). - */ - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux48: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux49: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux50: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux51: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux52: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux53: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux54: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux55: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts deleted file mode 100644 index 90a3f485c67a..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ /dev/null @@ -1,1590 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Backpack CMM BMC"; - compatible = "facebook,cmm-bmc", "aspeed,ast2500"; - - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - - /* - * PCA9548 (1-0077) provides 8 channels for connecting to - * 4 Line Cards and 4 Fabric Cards. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * PCA9548 (2-0071) provides 8 channels for connecting to - * Power Distribution Board. - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * PCA9548 (8-0077) provides 8 channels and the first 4 - * channels are connecting to 4 Fan Control Boards. - */ - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - - /* - * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting - * to Line Card #1. - */ - i2c40 = &imux40; - i2c41 = &imux41; - i2c42 = &imux42; - i2c43 = &imux43; - i2c44 = &imux44; - i2c45 = &imux45; - i2c46 = &imux46; - i2c47 = &imux47; - i2c48 = &imux48; - i2c49 = &imux49; - i2c50 = &imux50; - i2c51 = &imux51; - i2c52 = &imux52; - i2c53 = &imux53; - i2c54 = &imux54; - i2c55 = &imux55; - - /* - * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting - * to Line Card #2. - */ - i2c56 = &imux56; - i2c57 = &imux57; - i2c58 = &imux58; - i2c59 = &imux59; - i2c60 = &imux60; - i2c61 = &imux61; - i2c62 = &imux62; - i2c63 = &imux63; - i2c64 = &imux64; - i2c65 = &imux65; - i2c66 = &imux66; - i2c67 = &imux67; - i2c68 = &imux68; - i2c69 = &imux69; - i2c70 = &imux70; - i2c71 = &imux71; - - /* - * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting - * to Line Card #3. - */ - i2c72 = &imux72; - i2c73 = &imux73; - i2c74 = &imux74; - i2c75 = &imux75; - i2c76 = &imux76; - i2c77 = &imux77; - i2c78 = &imux78; - i2c79 = &imux79; - i2c80 = &imux80; - i2c81 = &imux81; - i2c82 = &imux82; - i2c83 = &imux83; - i2c84 = &imux84; - i2c85 = &imux85; - i2c86 = &imux86; - i2c87 = &imux87; - - /* - * 2 PCA9548 (21-0070 & 21-0073), 16 channels connecting - * to Line Card #4. - */ - i2c88 = &imux88; - i2c89 = &imux89; - i2c90 = &imux90; - i2c91 = &imux91; - i2c92 = &imux92; - i2c93 = &imux93; - i2c94 = &imux94; - i2c95 = &imux95; - i2c96 = &imux96; - i2c97 = &imux97; - i2c98 = &imux98; - i2c99 = &imux99; - i2c100 = &imux100; - i2c101 = &imux101; - i2c102 = &imux102; - i2c103 = &imux103; - - /* - * 2 PCA9548 (16-0070 & 16-0073), 16 channels connecting - * to Fabric Card #1. - */ - i2c104 = &imux104; - i2c105 = &imux105; - i2c106 = &imux106; - i2c107 = &imux107; - i2c108 = &imux108; - i2c109 = &imux109; - i2c110 = &imux110; - i2c111 = &imux111; - i2c112 = &imux112; - i2c113 = &imux113; - i2c114 = &imux114; - i2c115 = &imux115; - i2c116 = &imux116; - i2c117 = &imux117; - i2c118 = &imux118; - i2c119 = &imux119; - - /* - * 2 PCA9548 (17-0070 & 17-0073), 16 channels connecting - * to Fabric Card #2. - */ - i2c120 = &imux120; - i2c121 = &imux121; - i2c122 = &imux122; - i2c123 = &imux123; - i2c124 = &imux124; - i2c125 = &imux125; - i2c126 = &imux126; - i2c127 = &imux127; - i2c128 = &imux128; - i2c129 = &imux129; - i2c130 = &imux130; - i2c131 = &imux131; - i2c132 = &imux132; - i2c133 = &imux133; - i2c134 = &imux134; - i2c135 = &imux135; - - /* - * 2 PCA9548 (22-0070 & 22-0073), 16 channels connecting - * to Fabric Card #3. - */ - i2c136 = &imux136; - i2c137 = &imux137; - i2c138 = &imux138; - i2c139 = &imux139; - i2c140 = &imux140; - i2c141 = &imux141; - i2c142 = &imux142; - i2c143 = &imux143; - i2c144 = &imux144; - i2c145 = &imux145; - i2c146 = &imux146; - i2c147 = &imux147; - i2c148 = &imux148; - i2c149 = &imux149; - i2c150 = &imux150; - i2c151 = &imux151; - - /* - * 2 PCA9548 (23-0070 & 23-0073), 16 channels connecting - * to Fabric Card #4. - */ - i2c152 = &imux152; - i2c153 = &imux153; - i2c154 = &imux154; - i2c155 = &imux155; - i2c156 = &imux156; - i2c157 = &imux157; - i2c158 = &imux158; - i2c159 = &imux159; - i2c160 = &imux160; - i2c161 = &imux161; - i2c162 = &imux162; - i2c163 = &imux163; - i2c164 = &imux164; - i2c165 = &imux165; - i2c166 = &imux166; - i2c167 = &imux167; - - /* - * PCA9548 (32-0070), 8 channels connecting to Fan Control - # Board #1. - */ - i2c168 = &imux168; - i2c169 = &imux169; - i2c170 = &imux170; - i2c171 = &imux171; - i2c172 = &imux172; - i2c173 = &imux173; - i2c174 = &imux174; - i2c175 = &imux175; - - /* - * PCA9548 (33-0070), 8 channels connecting to Fan Control - # Board #2. - */ - i2c176 = &imux176; - i2c177 = &imux177; - i2c178 = &imux178; - i2c179 = &imux179; - i2c180 = &imux180; - i2c181 = &imux181; - i2c182 = &imux182; - i2c183 = &imux183; - - /* - * PCA9548 (34-0070), 8 channels connecting to Fan Control - # Board #3. - */ - i2c184 = &imux184; - i2c185 = &imux185; - i2c186 = &imux186; - i2c187 = &imux187; - i2c188 = &imux188; - i2c189 = &imux189; - i2c190 = &imux190; - i2c191 = &imux191; - - /* - * PCA9548 (35-0070), 8 channels connecting to Fan Control - # Board #4. - */ - i2c192 = &imux192; - i2c193 = &imux193; - i2c194 = &imux194; - i2c195 = &imux195; - i2c196 = &imux196; - i2c197 = &imux197; - i2c198 = &imux198; - i2c199 = &imux199; - }; - - chosen { - stdout-path = &uart1; - bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_ndsr1_default - &pinctrl_ndtr1_default - &pinctrl_nrts1_default>; -}; - -&uart3 { - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default - &pinctrl_ncts3_default - &pinctrl_ndcd3_default - &pinctrl_nri3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -/* - * I2C bus reserved for communication with COM-E. - */ -&i2c0 { - status = "okay"; -}; - -/* - * I2C bus to Line Cards and Fabric Cards. - */ -&i2c1 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - /* To Fabric Card #1 */ - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux104: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux105: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux106: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux107: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux108: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux109: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux110: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux111: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux112: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux113: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux114: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux115: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux116: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux117: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux118: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux119: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Fabric Card #2 */ - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux120: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux121: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux122: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux123: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux124: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux125: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux126: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux127: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux128: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux129: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux130: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux131: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux132: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux133: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux134: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux135: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Line Card #1 */ - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux40: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux41: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux42: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux43: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux44: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux45: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux46: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux47: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux48: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux49: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux50: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux51: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux52: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux53: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux54: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux55: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Line Card #2 */ - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux56: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux57: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux58: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux59: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux60: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux61: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux62: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux63: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux64: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux65: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux66: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux67: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux68: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux69: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux70: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux71: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To LC3 SCM */ - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux72: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux73: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux74: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux75: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux76: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux77: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux78: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux79: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux80: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux81: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux82: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux83: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux84: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux85: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux86: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux87: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Line Card #4 */ - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux88: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux89: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux90: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux91: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux92: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux93: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux94: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux95: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux96: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux97: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux98: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux99: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux100: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux101: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux102: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux103: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Fabric Card #3 */ - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux136: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux137: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux138: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux139: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux140: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux141: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux142: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux143: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux144: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux145: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux146: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux147: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux148: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux149: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux150: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux151: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Fabric Card #4 */ - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux152: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux153: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux154: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux155: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux156: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux157: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux158: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux159: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux160: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux161: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux162: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux163: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux164: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux165: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux166: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux167: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - }; -}; - -/* - * I2C bus to Power Distribution Board. - */ -&i2c2 { - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -/* - * I2c bus connected with temperature sensors on CMM. - */ -&i2c3 { - status = "okay"; -}; - -/* - * I2C bus reserved for communication with COM-E. - */ -&i2c4 { - status = "okay"; -}; - -/* - * I2c bus connected with ADM1278. - */ -&i2c5 { - status = "okay"; -}; - -/* - * I2c bus connected with I/O Expander. - */ -&i2c6 { - status = "okay"; -}; - -/* - * I2c bus connected with I/O Expander and EPROMs. - */ -&i2c7 { - status = "okay"; -}; - -/* - * I2C bus to Fan Control Boards. - */ -&i2c8 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - /* To Fan Control Board #1 */ - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux168: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux169: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux170: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux171: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux172: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux173: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux174: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux175: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Fan Control Board #2 */ - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux176: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux177: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux178: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux179: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux180: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux181: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux182: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux183: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Fan Control Board #3 */ - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux184: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux185: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux186: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux187: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux188: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux189: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux190: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux191: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* To Fan Control Board #4 */ - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux192: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - imux193: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - imux194: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - imux195: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - imux196: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - imux197: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - imux198: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - imux199: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -/* - * I2C bus to CMM CPLD. - */ -&i2c13 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&vhub { - status = "disabled"; -}; - -&sdhci0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_default>; -}; - -&sdhci1 { - status = "disabled"; -}; - -&fmc_flash0 { -#include "facebook-bmc-flash-layout.dtsi" -}; - -&fmc_flash1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts deleted file mode 100644 index b5cd4c7800b0..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. - -/dts-v1/; - -#include "ast2600-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Elbert BMC"; - compatible = "facebook,elbert-bmc", "aspeed,ast2600"; - - aliases { - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - - /* - * 8 child channels of PCA9548 2-0075. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * 8 child channels of PCA9548 5-0075. - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - }; - - chosen { - stdout-path = &uart5; - }; - - spi_gpio: spi { - num-chipselects = <1>; - cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; - }; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&i2c2 { - i2c-switch@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c5 { - i2c-switch@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c11 { - status = "okay"; -}; - -/* - * BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port - * directly (fixed link, no PHY in between). - * Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO - * interface, and the MDIO channel will be enabled in dts later, when - * BCM53134 is added to "bcm53xx" DSA driver. - */ -&mac3 { - status = "okay"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts deleted file mode 100644 index 6b319f34a9b9..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts +++ /dev/null @@ -1,1251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. - -/dts-v1/; - -#include -#include "ast2600-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Fuji BMC"; - compatible = "facebook,fuji-bmc", "aspeed,ast2600"; - - aliases { - /* - * PCA9548 (2-0070) provides 8 channels connecting to - * SCM (System Controller Module). - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * PCA9548 (8-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * PCA9548 (11-0077) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c40 = &imux40; - i2c41 = &imux41; - i2c42 = &imux42; - i2c43 = &imux43; - i2c44 = &imux44; - i2c45 = &imux45; - i2c46 = &imux46; - i2c47 = &imux47; - - /* - * PCA9548 (24-0071) provides 8 channels connecting to - * PDB-Left. - */ - i2c48 = &imux48; - i2c49 = &imux49; - i2c50 = &imux50; - i2c51 = &imux51; - i2c52 = &imux52; - i2c53 = &imux53; - i2c54 = &imux54; - i2c55 = &imux55; - - /* - * PCA9548 (25-0072) provides 8 channels connecting to - * PDB-Right. - */ - i2c56 = &imux56; - i2c57 = &imux57; - i2c58 = &imux58; - i2c59 = &imux59; - i2c60 = &imux60; - i2c61 = &imux61; - i2c62 = &imux62; - i2c63 = &imux63; - - /* - * PCA9548 (26-0076) provides 8 channels connecting to - * FCM1. - */ - i2c64 = &imux64; - i2c65 = &imux65; - i2c66 = &imux66; - i2c67 = &imux67; - i2c68 = &imux68; - i2c69 = &imux69; - i2c70 = &imux70; - i2c71 = &imux71; - - /* - * PCA9548 (27-0076) provides 8 channels connecting to - * FCM2. - */ - i2c72 = &imux72; - i2c73 = &imux73; - i2c74 = &imux74; - i2c75 = &imux75; - i2c76 = &imux76; - i2c77 = &imux77; - i2c78 = &imux78; - i2c79 = &imux79; - - /* - * PCA9548 (40-0076) provides 8 channels connecting to - * PIM1. - */ - i2c80 = &imux80; - i2c81 = &imux81; - i2c82 = &imux82; - i2c83 = &imux83; - i2c84 = &imux84; - i2c85 = &imux85; - i2c86 = &imux86; - i2c87 = &imux87; - - /* - * PCA9548 (41-0076) provides 8 channels connecting to - * PIM2. - */ - i2c88 = &imux88; - i2c89 = &imux89; - i2c90 = &imux90; - i2c91 = &imux91; - i2c92 = &imux92; - i2c93 = &imux93; - i2c94 = &imux94; - i2c95 = &imux95; - - /* - * PCA9548 (42-0076) provides 8 channels connecting to - * PIM3. - */ - i2c96 = &imux96; - i2c97 = &imux97; - i2c98 = &imux98; - i2c99 = &imux99; - i2c100 = &imux100; - i2c101 = &imux101; - i2c102 = &imux102; - i2c103 = &imux103; - - /* - * PCA9548 (43-0076) provides 8 channels connecting to - * PIM4. - */ - i2c104 = &imux104; - i2c105 = &imux105; - i2c106 = &imux106; - i2c107 = &imux107; - i2c108 = &imux108; - i2c109 = &imux109; - i2c110 = &imux110; - i2c111 = &imux111; - - /* - * PCA9548 (44-0076) provides 8 channels connecting to - * PIM5. - */ - i2c112 = &imux112; - i2c113 = &imux113; - i2c114 = &imux114; - i2c115 = &imux115; - i2c116 = &imux116; - i2c117 = &imux117; - i2c118 = &imux118; - i2c119 = &imux119; - - /* - * PCA9548 (45-0076) provides 8 channels connecting to - * PIM6. - */ - i2c120 = &imux120; - i2c121 = &imux121; - i2c122 = &imux122; - i2c123 = &imux123; - i2c124 = &imux124; - i2c125 = &imux125; - i2c126 = &imux126; - i2c127 = &imux127; - - /* - * PCA9548 (46-0076) provides 8 channels connecting to - * PIM7. - */ - i2c128 = &imux128; - i2c129 = &imux129; - i2c130 = &imux130; - i2c131 = &imux131; - i2c132 = &imux132; - i2c133 = &imux133; - i2c134 = &imux134; - i2c135 = &imux135; - - /* - * PCA9548 (47-0076) provides 8 channels connecting to - * PIM8. - */ - i2c136 = &imux136; - i2c137 = &imux137; - i2c138 = &imux138; - i2c139 = &imux139; - i2c140 = &imux140; - i2c141 = &imux141; - i2c142 = &imux142; - i2c143 = &imux143; - }; - - spi_gpio: spi { - num-chipselects = <3>; - cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, - <0>, /* device reg=<1> does not exist */ - <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_HIGH>; - - eeprom@2 { - compatible = "atmel,at93c46d"; - spi-max-frequency = <250000>; - data-size = <16>; - spi-cs-high; - reg = <2>; - }; - }; -}; - -&i2c0 { - multi-master; - bus-frequency = <1000000>; -}; - -&i2c2 { - /* - * PCA9548 (2-0070) provides 8 channels connecting to SCM (System - * Controller Module). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - shunt-resistor-micro-ohms = <1500>; - }; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c8 { - /* - * PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch - * Main Board). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - imux48: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux49: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux50: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - lp5012@14 { - compatible = "ti,lp5012"; - reg = <0x14>; - #address-cells = <1>; - #size-cells = <0>; - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "sys"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "fan"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "psu"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "smb"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - }; - }; - - imux51: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux52: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux53: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux54: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux55: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-switch@72 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - i2c-mux-idle-disconnect; - - imux56: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux57: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux58: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux59: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux60: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux61: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux62: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux63: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux64: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux65: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux66: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux67: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - shunt-resistor-micro-ohms = <250>; - }; - }; - - imux68: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux69: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux70: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux71: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux72: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux73: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux74: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux75: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - shunt-resistor-micro-ohms = <250>; - }; - }; - - imux76: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux77: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux78: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux79: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c11 { - status = "okay"; - - /* - * PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch - * Main Board). - */ - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - imux40: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux80: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux81: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux82: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux83: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux84: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux85: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux86: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux87: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux41: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux88: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux89: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux90: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux91: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux92: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux93: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux94: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux95: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux42: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux96: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux97: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux98: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux99: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux100: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux101: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux102: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux103: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux43: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux104: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux105: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux106: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux107: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux108: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux109: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux110: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux111: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux44: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux112: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux113: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux114: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux115: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux116: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux117: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux118: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux119: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux45: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux120: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux121: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux122: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux123: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux124: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux125: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux126: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux127: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux46: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux128: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux129: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux130: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux131: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux132: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux133: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux134: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux135: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux47: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux136: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux137: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux138: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux139: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux140: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux141: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux142: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux143: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - }; -}; - -&ehci1 { - status = "okay"; -}; - -&mdio1 { - status = "okay"; - - ethphy3: ethernet-phy@13 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0d>; - }; -}; - -&mac3 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <ðphy3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts deleted file mode 100644 index 60e875ac2461..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. -/dts-v1/; - -#include "ast2400-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Galaxy 100 BMC"; - compatible = "facebook,galaxy100-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 3>, <&adc 4>, <&adc 8>, <&adc 9>; - }; -}; - -&wdt2 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&fmc { - flash@1 { - status = "okay"; - m25p,fast-read; - label = "spi0.1"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; - }; -}; - - -&i2c9 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts deleted file mode 100644 index 7a53f54833a0..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2022 Facebook Inc. - -/dts-v1/; -#include "aspeed-g6.dtsi" -#include -#include -#include - -/ { - model = "Facebook Greatlakes BMC"; - compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 0>, <&adc1 2>, <&adc1 3>, <&adc1 4>, - <&adc1 5>, <&adc1 6>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&wdt1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; - aspeed,reset-type = "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration = <256>; -}; - -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - no-hw-checksum; - use-ncsi; - mlx,multi-host; - ncsi-ctrl,start-redo-probe; - ncsi-ctrl,no-channel-monitor; - ncsi-package = <1>; - ncsi-channel = <1>; - ncsi-rexmit = <1>; - ncsi-timeout = <2>; -}; - -&rtc { - status = "okay"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-rx-bus-width = <4>; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; - flash@1 { - status = "okay"; - m25p,fast-read; - label = "bmc2"; - spi-rx-bus-width = <4>; - spi-max-frequency = <50000000>; - }; -}; - -&i2c0 { - status = "okay"; - multi-master; - ipmb@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c1 { - status = "okay"; - multi-master; - ipmb@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c2 { - status = "okay"; - multi-master; - ipmb@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c3 { - status = "okay"; - multi-master; - ipmb@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - mctp-controller; - temperature-sensor@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - // NIC EEPROM - eeprom@50 { - compatible = "st,24c32"; - reg = <0x50>; - }; - mctp@10 { - compatible = "mctp-i2c-controller"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - }; -}; - -&i2c9 { - status = "okay"; - multi-master; - ipmb@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - }; - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; -}; - -&i2c12 { - status = "okay"; - temperature-sensor@4f { - compatible = "lm75"; - reg = <0x4f>; - }; -}; - -&i2c13 { - status = "okay"; -}; - -&adc0 { - ref_voltage = <2500>; - status = "okay"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; -}; - -&adc1 { - ref_voltage = <2500>; - status = "okay"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default - &pinctrl_adc11_default &pinctrl_adc12_default - &pinctrl_adc13_default &pinctrl_adc14_default>; -}; - - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; - - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "power-bmc-nic","presence-ocp-debug", - "power-bmc-slot1","power-bmc-slot2", - "power-bmc-slot3","power-bmc-slot4","","", - /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary", - "reset-cause-nic-secondary","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button", - "slot3-bmc-reset-button","slot4-bmc-reset-button", - "","","","presence-emmc", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","", - "presence-mb-slot1","presence-mb-slot2", - "presence-mb-slot3","presence-mb-slot4", - /*I0-I7*/ "","","","","","","bb-bmc-button","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","", - /*N0-N7*/ "","","","","bmc-ready","","","", - /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable", - /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable", - "reset-cause-pcie-slot1","reset-cause-pcie-slot2", - "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","GND", - /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button", - "bmc-slot3-ac-button","bmc-slot4-ac-button", - "","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","reset-cause-emmc","","","","", - /*Z0-Z7*/ "","","","","","","",""; -}; - -&gpio1 { - gpio-line-names = - /*18A0-18A7*/ "","","","","","","","", - /*18B0-18B7*/ "","","","","","","","", - /*18C0-18C7*/ "","","","","","","","", - /*18D0-18D7*/ "","","","","","","","", - /*18E0-18E3*/ "","","","","","","",""; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts deleted file mode 100644 index 230d16cd9967..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts +++ /dev/null @@ -1,1339 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Minipack 100 BMC"; - compatible = "facebook,minipack-bmc", "aspeed,ast2500"; - - aliases { - /* - * Override the default serial aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - - /* - * i2c switch 2-0070, pca9548, 8 child channels assigned - * with bus number 16-23. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * i2c switch 8-0070, pca9548, 8 child channels assigned - * with bus number 24-31. - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * i2c switch 9-0070, pca9548, 8 child channels assigned - * with bus number 32-39. - */ - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - - /* - * i2c switch 11-0070, pca9548, 8 child channels assigned - * with bus number 40-47. - */ - i2c40 = &imux40; - i2c41 = &imux41; - i2c42 = &imux42; - i2c43 = &imux43; - i2c44 = &imux44; - i2c45 = &imux45; - i2c46 = &imux46; - i2c47 = &imux47; - - /* - * I2C Switch 24-0071 (channel #0 of 8-0070): 8 channels for - * connecting to left PDB (Power Distribution Board). - */ - i2c48 = &imux48; - i2c49 = &imux49; - i2c50 = &imux50; - i2c51 = &imux51; - i2c52 = &imux52; - i2c53 = &imux53; - i2c54 = &imux54; - i2c55 = &imux55; - - /* - * I2C Switch 25-0072 (channel #1 of 8-0070): 8 channels for - * connecting to right PDB (Power Distribution Board). - */ - i2c56 = &imux56; - i2c57 = &imux57; - i2c58 = &imux58; - i2c59 = &imux59; - i2c60 = &imux60; - i2c61 = &imux61; - i2c62 = &imux62; - i2c63 = &imux63; - - /* - * I2C Switch 26-0076 (channel #2 of 8-0070): 8 channels for - * connecting to top FCM (Fan Control Module). - */ - i2c64 = &imux64; - i2c65 = &imux65; - i2c66 = &imux66; - i2c67 = &imux67; - i2c68 = &imux68; - i2c69 = &imux69; - i2c70 = &imux70; - i2c71 = &imux71; - - /* - * I2C Switch 27-0076 (channel #3 of 8-0070): 8 channels for - * connecting to bottom FCM (Fan Control Module). - */ - i2c72 = &imux72; - i2c73 = &imux73; - i2c74 = &imux74; - i2c75 = &imux75; - i2c76 = &imux76; - i2c77 = &imux77; - i2c78 = &imux78; - i2c79 = &imux79; - - /* - * I2C Switch 40-0073 (channel #0 of 11-0070): connecting - * to PIM (Port Interface Module) #1 (1-based). - */ - i2c80 = &imux80; - i2c81 = &imux81; - i2c82 = &imux82; - i2c83 = &imux83; - i2c84 = &imux84; - i2c85 = &imux85; - i2c86 = &imux86; - i2c87 = &imux87; - - /* - * I2C Switch 41-0073 (channel #1 of 11-0070): connecting - * to PIM (Port Interface Module) #2 (1-based). - */ - i2c88 = &imux88; - i2c89 = &imux89; - i2c90 = &imux90; - i2c91 = &imux91; - i2c92 = &imux92; - i2c93 = &imux93; - i2c94 = &imux94; - i2c95 = &imux95; - - /* - * I2C Switch 42-0073 (channel #2 of 11-0070): connecting - * to PIM (Port Interface Module) #3 (1-based). - */ - i2c96 = &imux96; - i2c97 = &imux97; - i2c98 = &imux98; - i2c99 = &imux99; - i2c100 = &imux100; - i2c101 = &imux101; - i2c102 = &imux102; - i2c103 = &imux103; - - /* - * I2C Switch 43-0073 (channel #3 of 11-0070): connecting - * to PIM (Port Interface Module) #4 (1-based). - */ - i2c104 = &imux104; - i2c105 = &imux105; - i2c106 = &imux106; - i2c107 = &imux107; - i2c108 = &imux108; - i2c109 = &imux109; - i2c110 = &imux110; - i2c111 = &imux111; - - /* - * I2C Switch 44-0073 (channel #4 of 11-0070): connecting - * to PIM (Port Interface Module) #5 (1-based). - */ - i2c112 = &imux112; - i2c113 = &imux113; - i2c114 = &imux114; - i2c115 = &imux115; - i2c116 = &imux116; - i2c117 = &imux117; - i2c118 = &imux118; - i2c119 = &imux119; - - /* - * I2C Switch 45-0073 (channel #5 of 11-0070): connecting - * to PIM (Port Interface Module) #6 (1-based). - */ - i2c120 = &imux120; - i2c121 = &imux121; - i2c122 = &imux122; - i2c123 = &imux123; - i2c124 = &imux124; - i2c125 = &imux125; - i2c126 = &imux126; - i2c127 = &imux127; - - /* - * I2C Switch 46-0073 (channel #6 of 11-0070): connecting - * to PIM (Port Interface Module) #7 (1-based). - */ - i2c128 = &imux128; - i2c129 = &imux129; - i2c130 = &imux130; - i2c131 = &imux131; - i2c132 = &imux132; - i2c133 = &imux133; - i2c134 = &imux134; - i2c135 = &imux135; - - /* - * I2C Switch 47-0073 (channel #7 of 11-0070): connecting - * to PIM (Port Interface Module) #8 (1-based). - */ - i2c136 = &imux136; - i2c137 = &imux137; - i2c138 = &imux138; - i2c139 = &imux139; - i2c140 = &imux140; - i2c141 = &imux141; - i2c142 = &imux142; - i2c143 = &imux143; - }; - - chosen { - stdout-path = &uart1; - bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw"; - }; -}; - -&wdt2 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -/* - * Both firmware flashes are 64MB on Minipack BMC. - */ -&fmc_flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * u-boot partition: 384KB. - */ - u-boot@0 { - reg = <0x0 0x60000>; - label = "u-boot"; - }; - - /* - * u-boot environment variables: 128KB. - */ - u-boot-env@60000 { - reg = <0x60000 0x20000>; - label = "env"; - }; - - /* - * FIT image: 55.5 MB. - */ - fit@80000 { - reg = <0x80000 0x3780000>; - label = "fit"; - }; - - /* - * "data0" partition (8MB) is reserved for persistent - * data store. - */ - data0@3800000 { - reg = <0x3800000 0x800000>; - label = "data0"; - }; - - /* - * "flash0" partition (covering the entire flash) is - * explicitly created to avoid breaking legacy applications. - */ - flash0@0 { - reg = <0x0 0x4000000>; - label = "flash0"; - }; - }; -}; - -&fmc_flash1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x4000000>; - }; - }; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_ncts1_default - &pinctrl_ndsr1_default - &pinctrl_ndtr1_default - &pinctrl_nrts1_default>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&i2c0 { - status = "okay"; - bus-frequency = <400000>; - multi-master; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - /* - * I2C Switch 2-0070 is connecting to SCM (System Controller - * Module). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - multi-master; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - /* - * I2C Switch 8-0070 channel #0: connecting to left PDB - * (Power Distribution Board). - */ - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - imux48: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux49: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux50: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux51: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux52: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux53: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux54: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux55: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 8-0070 channel #1: connecting to right PDB - * (Power Distribution Board). - */ - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-switch@72 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - i2c-mux-idle-disconnect; - - imux56: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux57: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux58: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux59: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux60: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux61: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux62: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux63: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 8-0070 channel #2: connecting to top FCM - * (Fan Control Module). - */ - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux64: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux65: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux66: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux67: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux68: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux69: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux70: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux71: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 8-0070 channel #3: connecting to bottom - * FCM (Fan Control Module). - */ - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux72: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux73: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux74: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux75: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux76: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux77: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux78: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux79: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c9 { - status = "okay"; - - /* - * I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB - * (Switch Main Board). - */ - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - /* - * I2C Switch 11-0070 channel #0: connecting to PIM - * (Port Interface Module) #1 (1-based). - */ - imux40: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux80: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux81: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux82: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux83: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux84: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux85: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux86: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux87: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #1: connecting to PIM - * (Port Interface Module) #2 (1-based). - */ - imux41: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux88: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux89: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux90: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux91: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux92: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux93: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux94: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux95: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #2: connecting to PIM - * (Port Interface Module) #3 (1-based). - */ - imux42: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux96: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux97: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux98: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux99: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux100: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux101: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux102: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux103: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #3: connecting to PIM - * (Port Interface Module) #4 (1-based). - */ - imux43: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux104: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux105: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux106: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux107: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux108: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux109: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux110: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux111: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #4: connecting to PIM - * (Port Interface Module) #5 (1-based). - */ - imux44: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux112: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux113: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux114: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux115: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux116: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux117: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux118: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux119: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #5: connecting to PIM - * (Port Interface Module) #6 (1-based). - */ - imux45: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux120: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux121: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux122: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux123: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux124: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux125: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux126: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux127: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #6: connecting to PIM - * (Port Interface Module) #7 (1-based). - */ - imux46: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux128: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux129: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux130: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux131: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux132: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux133: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux134: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux135: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - - /* - * I2C Switch 11-0070 channel #7: connecting to PIM - * (Port Interface Module) #8 (1-based). - */ - imux47: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - i2c-switch@73 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - imux136: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux137: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux138: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux139: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux140: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux141: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux142: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux143: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - }; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts deleted file mode 100644 index b6b16356f571..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ /dev/null @@ -1,549 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -// Author: Vijay Khemka -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Facebook TiogaPass BMC"; - compatible = "facebook,tiogapass-bmc", "aspeed,ast2500"; - aliases { - serial0 = &uart1; - serial4 = &uart5; - - /* - * Hardcode the bus number of i2c switches' channels to - * avoid breaking the legacy applications. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - }; - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&lpc_ctrl { - // Enable lpc clock - status = "okay"; -}; - -&uart1 { - // Host Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - // SoL Host Console - status = "okay"; -}; - -&uart3 { - // SoL BMC Console - status = "okay"; -}; - -&uart5 { - // BMC Console - status = "okay"; -}; - -&kcs2 { - // BMC KCS channel 2 - status = "okay"; - aspeed,lpc-io-reg = <0xca8>; -}; - -&kcs3 { - // BMC KCS channel 3 - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", - /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", - "IRQ_PVDDQ_GHJ_VRHOT_LVT3", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", - "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", - "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", - /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", - "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", - "CPU1_PROCHOT_LVT3_ BMC", - /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", - "IRQ_PVCCIN_CPU0_VRHOT_LVC3", - "IRQ_PVCCIN_CPU1_VRHOT_LVC3", - "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", - /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", - "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", - /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", - "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", - "LED_POST_CODE_6","LED_POST_CODE_7", - /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", - "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", - "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", - /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", - "CPU0_THERMTRIP_LATCH_LVT3", - "CPU1_THERMTRIP_LATCH_LVT3","","", - /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", - "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", - "BMC_PWR_DEBUG","RST_RSMRST", - /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", - "POST_CARD_PRES_BMC","PE_BMC_WAKE", - /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", - "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", - "SLT_CFG1", - /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", - "","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","BMC_FAULT","","", - /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","GLOBAL_RST_WARN", - "CPU0_MEMABC_MEMHOT_LVT3_BMC", - "CPU0_MEMDEF_MEMHOT_LVT3_BMC", - "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", - "CPU1_MEMKLM_MEMHOT_LVT3_BMC", - /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", - "","","", - /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", - "","","","", - /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", - "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", - "","POST_COMPLETE", - /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii2_default>; - use-ncsi; -}; - -&adc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - //Airmax Conn B, CPU0 PIROM, CPU1 PIROM -}; - -&i2c1 { - status = "okay"; - //X24 Riser - i2c-switch@71 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - tmp75@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - - tmp421@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - - imux20: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux21: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux22: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux23: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - }; - - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - tmp421@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - - tmp421@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - }; - - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - tmp421@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - - tmp421@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - - imux28: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux29: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux30: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux31: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - }; - - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@40 { - compatible = "ti,ina230"; - reg = <0x40>; - }; - - i2c-switch@41 { - compatible = "ti,ina230"; - reg = <0x41>; - }; - - i2c-switch@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - }; - - }; -}; - -&i2c2 { - status = "okay"; - // Mezz Management SMBus -}; - -&i2c3 { - status = "okay"; - // SMBus to Board ID EEPROM -}; - -&i2c4 { - status = "okay"; - // BMC Debug Header - ipmb0@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c5 { - status = "okay"; - // CPU Voltage regulators - regulator@48 { - compatible = "infineon,pxe1610"; - reg = <0x48>; - }; - regulator@4a { - compatible = "infineon,pxe1610"; - reg = <0x4a>; - }; - regulator@50 { - compatible = "infineon,pxe1610"; - reg = <0x50>; - }; - regulator@52 { - compatible = "infineon,pxe1610"; - reg = <0x52>; - }; - regulator@58 { - compatible = "infineon,pxe1610"; - reg = <0x58>; - }; - regulator@5a { - compatible = "infineon,pxe1610"; - reg = <0x5a>; - }; - regulator@68 { - compatible = "infineon,pxe1610"; - reg = <0x68>; - }; - regulator@70 { - compatible = "infineon,pxe1610"; - reg = <0x70>; - }; - regulator@72 { - compatible = "infineon,pxe1610"; - reg = <0x72>; - }; -}; - -&i2c6 { - status = "okay"; - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c7 { - status = "okay"; - //HSC, AirMax Conn A - adm1278@45 { - compatible = "adm1275"; - reg = <0x45>; - shunt-resistor-micro-ohms = <250>; - }; -}; - -&i2c8 { - status = "okay"; - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - //Mezz Sensor SMBus -}; - -&i2c9 { - status = "okay"; - //USB Debug Connector - ipmb0@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts deleted file mode 100644 index 584efa528450..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2400-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Wedge 100 BMC"; - compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart3; - bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; - }; -}; - -&wdt2 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&fmc { - flash@1 { - status = "okay"; - m25p,fast-read; - label = "spi0.1"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; - }; -}; - -&i2c7 { - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - }; -}; - -&i2c9 { - status = "okay"; -}; - - -&vhub { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts deleted file mode 100644 index 6624855d8ebd..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2400-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Wedge 40 BMC"; - compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart3; - bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; - }; -}; - -&wdt2 { - status = "disabled"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm6_default - &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; - - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; - }; - - fan@7 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts deleted file mode 100644 index ed305948386f..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts +++ /dev/null @@ -1,374 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2019 Facebook Inc. -/dts-v1/; - -#include -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Wedge 400 BMC"; - compatible = "facebook,wedge400-bmc", "aspeed,ast2500"; - - aliases { - /* - * PCA9548 (2-0070) provides 8 channels connecting to - * SCM (System Controller Module). - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * PCA9548 (8-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * PCA9548 (11-0076) provides 8 channels connecting to - * FCM (Fan Controller Module). - */ - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - - spi2 = &spi_gpio; - }; - - chosen { - stdout-path = &uart1; - bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; - }; - - /* - * GPIO-based SPI Master is required to access SPI TPM, because - * full-duplex SPI transactions are not supported by ASPEED SPI - * Controllers. - */ - spi_gpio: spi { - status = "okay"; - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; - gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; - spi-max-frequency = <33000000>; - reg = <0>; - }; - }; -}; - -/* - * Both firmware flashes are 128MB on Wedge400 BMC. - */ -&fmc_flash0 { -#include "facebook-bmc-flash-layout-128.dtsi" -}; - -&fmc_flash1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x8000000>; - label = "flash1"; - }; - }; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -/* - * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC - * communication. - */ -&i2c0 { - status = "okay"; - multi-master; - bus-frequency = <1000000>; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - i2c-switch@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&sdhci1 { - /* - * DMA mode needs to be disabled to avoid conflicts with UHCI - * Controller in AST2500 SoC. - */ - sdhci-caps-mask = <0x0 0x580000>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts deleted file mode 100644 index 5e6105874217..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook YAMP 100 BMC"; - compatible = "facebook,yamp-bmc", "aspeed,ast2500"; - - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; - }; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&mac0 { - status = "okay"; - use-ncsi; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&mac1 { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - i2c-switch@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&fmc_flash0 { -#include "facebook-bmc-flash-layout.dtsi" -}; - -&fmc_flash1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts deleted file mode 100644 index 6bf2ff85a40e..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Facebook Yosemitev2 BMC"; - compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500"; - aliases { - serial4 = &uart5; - }; - chosen { - stdout-path = &uart5; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - iio-hwmon { - // VOLATAGE SENSOR - compatible = "iio-hwmon"; - io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> , - <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> , - <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> , - <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; -&uart1 { - // Host1 Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - // Host2 Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; - -}; - -&uart3 { - // Host3 Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - // Host4 Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&uart5 { - // BMC Console - status = "okay"; -}; - -&vuart { - // Virtual UART - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - use-ncsi; - mlx,multi-host; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&i2c1 { - //Host1 IPMB bus - status = "okay"; - multi-master; - ipmb1@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c3 { - //Host2 IPMB bus - status = "okay"; - multi-master; - ipmb3@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c5 { - //Host3 IPMB bus - status = "okay"; - multi-master; - ipmb5@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c7 { - //Host4 IPMB bus - status = "okay"; - multi-master; - ipmb7@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c8 { - status = "okay"; - //FRU EEPROM - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&i2c9 { - status = "okay"; - tmp421@4e { - //INLET TEMP - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - //OUTLET TEMP - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; -}; - -&i2c10 { - status = "okay"; - //HSC - adm1278@40 { - compatible = "adi,adm1278"; - reg = <0x40>; - }; -}; - -&i2c11 { - status = "okay"; - //MEZZ_TEMP_SENSOR - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; - // Debug Card - multi-master; - ipmb13@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&pwm_tacho { - status = "okay"; - //FSC - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts deleted file mode 100644 index 81902cbe662c..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ /dev/null @@ -1,915 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2022 IBM Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include -#include - -/ { - model = "Bonnell"; - compatible = "ibm,bonnell-bmc", "aspeed,ast2600"; - - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; - - serial4 = &uart5; - i2c16 = &i2c11mux0chn0; - i2c17 = &i2c11mux0chn1; - i2c18 = &i2c11mux0chn2; - i2c19 = &i2c11mux0chn3; - - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; - - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@b3e00000 { - compatible = "ramoops"; - reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x8000>; - pmsg-size = <0x8000>; - max-reason = <3>; /* KMSG_DUMP_EMERG */ - }; - - /* LPC FW cycle bridge region requires natural alignment */ - flash_memory: region@b4000000 { - no-map; - reg = <0xb4000000 0x04000000>; /* 64M */ - }; - - /* VGA region is dictated by hardware strapping */ - vga_memory: region@bf000000 { - no-map; - compatible = "shared-dma-pool"; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - fan0 { - gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>; - }; - - fan1 { - gpios = <&gpio0 ASPEED_GPIO(G, 1) GPIO_ACTIVE_LOW>; - }; - - rear-enc-id0 { - gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; - }; - - rear-enc-fault0 { - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&gpio0 ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&gpio0 ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc1 7>; - }; -}; - -&adc1 { - status = "okay"; - aspeed,int-vref-microvolt = <2500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","","","","","checkstop","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","","", - /*G0-G7*/ "fan0","fan1","","","","","","", - /*H0-H7*/ "","","rear-enc-id0","rear-enc-fault0","","","","", - /*I0-I7*/ "","","","","","","bmc-secure-boot","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","usb-power","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", - /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", - /*S0-S7*/ "presence-ps0","presence-ps1","","","power-ffs-sync-history","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","",""; - - usb_power { - gpio-hog; - gpios = ; - output-high; - }; -}; - -&emmc_controller { - status = "okay"; -}; - -&pinctrl_emmc_default { - bias-disable; -}; - -&emmc { - status = "okay"; - clk-phase-mmc-hs200 = <180>, <180>; -}; - -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -&ibt { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - tca9554@20 { - compatible = "ti,tca9554"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "", - "RUSSEL_FW_I2C_ENABLE_N", - "RUSSEL_OPPANEL_PRESENCE_N", - "BLYTH_OPPANEL_PRESENCE_N", - "CPU_TPM_CARD_PRESENT_N", - "", - "", - "DASD_BP_PRESENT_N"; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c3 { - status = "okay"; - - power-supply@5a { - compatible = "acbel,fsg032"; - reg = <0x5a>; - }; - - power-supply@5b { - compatible = "acbel,fsg032"; - reg = <0x5b>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - multi-master; - status = "okay"; - - si7021-a20@40 { - compatible = "silabs,si7020"; - reg = <0x40>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan0: fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - }; - - fan1: fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - }; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "front-sys-id0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "front-check-log0"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "front-enc-fault1"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "front-sys-pwron0"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - ibm-panel@62 { - compatible = "ibm,op-panel"; - reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; -}; - -&i2c8 { - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "", - "APSS_RESET_N", - "", - "N_MODE_CPU_N", - "", - "", - "P10_DCM_PRESENT", - ""; - }; -}; - -&i2c9 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - tca9554@20 { - compatible = "ti,tca9554"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "BOOT_RCVRY_TWI", - "BOOT_RCVRY_UART", - "", - "", - "", - "", - "", - "PE_SWITCH_RSTB_N"; - }; - - tmp435@4c { - compatible = "ti,tmp435"; - reg = <0x4c>; - }; - - pca9849@75 { - compatible = "nxp,pca9849"; - reg = <0x75>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c11mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c11mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c11mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c11mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c12 { - status = "okay"; - - tpm@2e { - compatible = "nuvoton,npct75x"; - reg = <0x2e>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c13 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "nvme0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "nvme1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "nvme2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "nvme3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; -}; - -&i2c14 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vuart1 { - status = "okay"; -}; - -&vuart2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - status = "okay"; -}; - -&xdma { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8 0xcac>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts deleted file mode 100644 index c6f8f20914d1..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ /dev/null @@ -1,3723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2020 IBM Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include -#include - -/ { - model = "Everest"; - compatible = "ibm,everest-bmc", "aspeed,ast2600"; - - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; - i2c300 = &cfam2_i2c0; - i2c301 = &cfam2_i2c1; - i2c310 = &cfam2_i2c10; - i2c311 = &cfam2_i2c11; - i2c312 = &cfam2_i2c12; - i2c313 = &cfam2_i2c13; - i2c314 = &cfam2_i2c14; - i2c315 = &cfam2_i2c15; - i2c402 = &cfam3_i2c2; - i2c403 = &cfam3_i2c3; - i2c410 = &cfam3_i2c10; - i2c411 = &cfam3_i2c11; - i2c414 = &cfam3_i2c14; - i2c415 = &cfam3_i2c15; - i2c416 = &cfam3_i2c16; - i2c417 = &cfam3_i2c17; - i2c500 = &cfam4_i2c0; - i2c501 = &cfam4_i2c1; - i2c510 = &cfam4_i2c10; - i2c511 = &cfam4_i2c11; - i2c512 = &cfam4_i2c12; - i2c513 = &cfam4_i2c13; - i2c514 = &cfam4_i2c14; - i2c515 = &cfam4_i2c15; - i2c602 = &cfam5_i2c2; - i2c603 = &cfam5_i2c3; - i2c610 = &cfam5_i2c10; - i2c611 = &cfam5_i2c11; - i2c614 = &cfam5_i2c14; - i2c615 = &cfam5_i2c15; - i2c616 = &cfam5_i2c16; - i2c617 = &cfam5_i2c17; - i2c700 = &cfam6_i2c0; - i2c701 = &cfam6_i2c1; - i2c710 = &cfam6_i2c10; - i2c711 = &cfam6_i2c11; - i2c712 = &cfam6_i2c12; - i2c713 = &cfam6_i2c13; - i2c714 = &cfam6_i2c14; - i2c715 = &cfam6_i2c15; - i2c802 = &cfam7_i2c2; - i2c803 = &cfam7_i2c3; - i2c810 = &cfam7_i2c10; - i2c811 = &cfam7_i2c11; - i2c814 = &cfam7_i2c14; - i2c815 = &cfam7_i2c15; - i2c816 = &cfam7_i2c16; - i2c817 = &cfam7_i2c17; - - i2c16 = &i2c4mux0chn0; - i2c17 = &i2c4mux0chn1; - i2c18 = &i2c4mux0chn2; - i2c19 = &i2c5mux0chn0; - i2c20 = &i2c5mux0chn1; - i2c21 = &i2c5mux0chn2; - i2c22 = &i2c5mux0chn3; - i2c23 = &i2c6mux0chn0; - i2c24 = &i2c6mux0chn1; - i2c25 = &i2c6mux0chn2; - i2c26 = &i2c6mux0chn3; - i2c27 = &i2c14mux0chn0; - i2c28 = &i2c14mux0chn1; - i2c29 = &i2c14mux0chn2; - i2c30 = &i2c14mux0chn3; - i2c31 = &i2c14mux1chn0; - i2c32 = &i2c14mux1chn1; - i2c33 = &i2c14mux1chn2; - i2c34 = &i2c14mux1chn3; - i2c35 = &i2c15mux0chn0; - i2c36 = &i2c15mux0chn1; - i2c37 = &i2c15mux0chn2; - i2c38 = &i2c15mux0chn3; - i2c39 = &i2c15mux1chn0; - i2c40 = &i2c15mux1chn1; - i2c41 = &i2c15mux1chn2; - i2c42 = &i2c15mux1chn3; - i2c43 = &i2c15mux2chn0; - i2c44 = &i2c15mux2chn1; - i2c45 = &i2c15mux2chn2; - i2c46 = &i2c15mux2chn3; - i2c47 = &i2c8mux0chn0; - i2c48 = &i2c8mux0chn1; - - serial4 = &uart5; - - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; - spi30 = &cfam2_spi0; - spi31 = &cfam2_spi1; - spi32 = &cfam2_spi2; - spi33 = &cfam2_spi3; - spi40 = &cfam3_spi0; - spi41 = &cfam3_spi1; - spi42 = &cfam3_spi2; - spi43 = &cfam3_spi3; - spi50 = &cfam4_spi0; - spi51 = &cfam4_spi1; - spi52 = &cfam4_spi2; - spi53 = &cfam4_spi3; - spi60 = &cfam5_spi0; - spi61 = &cfam5_spi1; - spi62 = &cfam5_spi2; - spi63 = &cfam5_spi3; - spi70 = &cfam6_spi0; - spi71 = &cfam6_spi1; - spi72 = &cfam6_spi2; - spi73 = &cfam6_spi3; - spi80 = &cfam7_spi0; - spi81 = &cfam7_spi1; - spi82 = &cfam7_spi2; - spi83 = &cfam7_spi3; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - event_log: tcg_event_log@b3d00000 { - no-map; - reg = <0xb3d00000 0x100000>; - }; - - ramoops@b3e00000 { - compatible = "ramoops"; - reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x8000>; - pmsg-size = <0x8000>; - max-reason = <3>; /* KMSG_DUMP_EMERG */ - }; - - /* LPC FW cycle bridge region requires natural alignment */ - flash_memory: region@b4000000 { - no-map; - reg = <0xb4000000 0x04000000>; /* 64M */ - }; - - /* VGA region is dictated by hardware strapping */ - vga_memory: region@bf000000 { - no-map; - compatible = "shared-dma-pool"; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 15 GPIO_ACTIVE_LOW>; - linux,code = <15>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 14 GPIO_ACTIVE_LOW>; - linux,code = <14>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 13 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 12 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* RTC battery fault LED at the back */ - led-rtc-battery { - gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; - }; - - /* BMC Card fault LED at the back */ - led-bmc { - gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; - }; - - /* Enclosure Identify LED at the back */ - led-rear-enc-id0 { - gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; - }; - - /* Enclosure fault LED at the back */ - led-rear-enc-fault0 { - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - }; - - /* PCIE slot power LED */ - led-pcieslot-power { - gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc1 7>; - }; -}; - -&adc1 { - status = "okay"; - aspeed,int-vref-microvolt = <2500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&gpio0 { - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","checkstop","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", - /*I0-I7*/ "","","","","","","bmc-secure-boot","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","usb-power","","","","", - /*P0-P7*/ "","","","","led-pcieslot-power","","","", - /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", - /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", - /*S0-S7*/ "","","","","power-ffs-sync-history","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","",""; - - usb_power { - gpio-hog; - gpios = ; - output-high; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - pca1: pca9552@62 { - compatible = "nxp,pca9552"; - reg = <0x62>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "presence-ps0", - "presence-ps1", - "presence-ps2", - "presence-ps3", - "presence-pdb", - "presence-tpm", - "", "", - "presence-cp0", - "presence-cp1", - "presence-cp2", - "presence-cp3", - "presence-dasd", - "presence-lcd-op", - "presence-base-op", - ""; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - power-supply@68 { - compatible = "ibm,cffps"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps"; - reg = <0x69>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; - - power-supply@6d { - compatible = "ibm,cffps"; - reg = <0x6d>; - }; -}; - -&i2c4 { - status = "okay"; - - pca2: pca9552@65 { - compatible = "nxp,pca9552"; - reg = <0x65>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "presence-cable-card1", - "presence-cable-card2", - "presence-cable-card3", - "presence-cable-card4", - "presence-cable-card5", - "expander-cable-card1", - "expander-cable-card2", - "expander-cable-card3", - "expander-cable-card4", - "expander-cable-card5"; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c4mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - - pca_cable_card_c01: pca9551@62 { - compatible = "nxp,pca9551"; - reg = <0x62>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c01-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c01-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c4mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca_cable_card_c02: pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c02-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c02-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c4mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - pca_cable_card_c03: pca9551@61 { - compatible = "nxp,pca9551"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c03-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c03-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - pca3: pca9552@66 { - compatible = "nxp,pca9552"; - reg = <0x66>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "presence-cable-card6", - "presence-cable-card7", - "presence-cable-card8", - "presence-cable-card9", - "presence-cable-card10", - "presence-cable-card11", - "expander-cable-card6", - "expander-cable-card7", - "expander-cable-card8", - "expander-cable-card9", - "expander-cable-card10", - "expander-cable-card11"; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c5mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca_cable_card_c04: pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c04-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c04-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c5mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - pca_cable_card_c05: pca9551@61 { - compatible = "nxp,pca9551"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c05-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c05-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c5mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - - pca_cable_card_c06: pca9551@62 { - compatible = "nxp,pca9551"; - reg = <0x62>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c06-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c06-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c5mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - - pca_cable_card_c07: pca9551@63 { - compatible = "nxp,pca9551"; - reg = <0x63>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c07-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c07-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c6mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca_cable_card_c08: pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c08-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c08-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c6mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - - pca_cable_card_c09: pca9551@62 { - compatible = "nxp,pca9551"; - reg = <0x62>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c09-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c09-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c6mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - - pca_cable_card_c10: pca9551@63 { - compatible = "nxp,pca9551"; - reg = <0x63>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c10-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c10-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c6mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - pca_cable_card_c11: pca9551@61 { - compatible = "nxp,pca9551"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard-c11-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard-c11-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - }; - - pca_pcie_slot: pca9552@65 { - compatible = "nxp,pca9552"; - reg = <0x65>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@1 { - label = "pcieslot-c01"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "pcieslot-c02"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "pcieslot-c03"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "pcieslot-c04"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "pcieslot-c05"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "pcieslot-c06"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "pcieslot-c07"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "pcieslot-c08"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "pcieslot-c09"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "pcieslot-c10"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "pcieslot-c11"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; -}; - -&i2c7 { - status = "okay"; - - pic0_dimm: pca9552@31 { - compatible = "ibm,pca9552"; - reg = <0x31>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "ddimm0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "ddimm1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "ddimm2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "ddimm3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "ddimm4"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "ddimm5"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "ddimm6"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "ddimm7"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "ddimm8"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "ddimm9"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "ddimm10"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "ddimm11"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "ddimm12"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "ddimm13"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "ddimm14"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "ddimm15"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pic1_dimm: pca9552@32 { - compatible = "ibm,pca9552"; - reg = <0x32>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "ddimm16"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "ddimm17"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "ddimm18"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "ddimm19"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "ddimm20"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "ddimm21"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "ddimm22"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "ddimm23"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "ddimm24"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "ddimm25"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "ddimm26"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "ddimm27"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "ddimm28"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "ddimm29"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "ddimm30"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "ddimm31"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pic2_dimm: pca9552@33 { - compatible = "ibm,pca9552"; - reg = <0x33>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "ddimm32"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "ddimm33"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "ddimm34"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "ddimm35"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "ddimm36"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "ddimm37"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "ddimm38"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "ddimm39"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "ddimm40"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "ddimm41"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "ddimm42"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "ddimm43"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "ddimm44"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "ddimm45"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "ddimm46"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "ddimm47"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pic3_dimm: pca9552@30 { - compatible = "ibm,pca9552"; - reg = <0x30>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "ddimm48"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "ddimm49"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "ddimm50"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "ddimm51"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "ddimm52"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "ddimm53"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "ddimm54"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "ddimm55"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "ddimm56"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "ddimm57"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "ddimm58"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "ddimm59"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "ddimm60"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "ddimm61"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "ddimm62"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "ddimm63"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pic0_vrm_misc: pca9552@34 { - compatible = "ibm,pca9552"; - reg = <0x34>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "planar"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "tpm"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "cpu3-c61"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "cpu0-c14"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "opencapi-connector3"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "opencapi-connector4"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "opencapi-connector5"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "vrm4"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "vrm5"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "vrm6"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "vrm7"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "vrm12"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "vrm13"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "vrm14"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "vrm15"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pic1_vrm_misc: pca9552@35 { - compatible = "ibm,pca9552"; - reg = <0x35>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "dasd-backplane"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "power-distribution"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "cpu1-c19"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "cpu2-c56"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "opencapi-connector0"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "opencapi-connector1"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "opencapi-connector2"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "vrm0"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "vrm1"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "vrm2"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "vrm3"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "vrm8"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "vrm9"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "vrm10"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "vrm11"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; -}; - -&i2c8 { - status = "okay"; - - ucd90320@11 { - compatible = "ti,ucd90320"; - reg = <0x11>; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c8mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c8mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&i2c9 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - }; - - eeprom@53 { - compatible = "atmel,24c128"; - reg = <0x53>; - }; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - }; -}; - -&i2c10 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - eeprom@53 { - compatible = "atmel,24c128"; - reg = <0x53>; - }; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - }; -}; - -&i2c11 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - eeprom@53 { - compatible = "atmel,24c128"; - reg = <0x53>; - }; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - }; -}; - -&i2c12 { - status = "okay"; - - tpm@2e { - compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; - reg = <0x2e>; - memory-region = <&event_log>; - }; -}; - -&i2c13 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - eeprom@53 { - compatible = "atmel,24c128"; - reg = <0x53>; - }; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - }; -}; - -&i2c14 { - multi-master; - status = "okay"; - - ibm-panel@62 { - compatible = "ibm,op-panel"; - reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - idle-state = <1>; - - i2c14mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - i2c14mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - }; - }; - - i2c14mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - pca_oppanel: pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "front-sys-id0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "front-check-log0"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "front-enc-fault1"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "front-sys-pwron0"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c14mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - max31785@52 { - compatible = "maxim,max31785a"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x52>; - - fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - }; - - fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - }; - - fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - }; - - fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - }; - }; - - pca_fan_nvme: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "nvme0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "nvme1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "nvme2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "nvme3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "nvme4"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "nvme5"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "nvme6"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "nvme7"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "nvme8"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "nvme9"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "fan0"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "fan1"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "fan2"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "fan3"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pca0: pca9552@61 { - compatible = "nxp,pca9552"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x61>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "","","","", - "","","","", - "","","","", - "presence-fan3", - "presence-fan2", - "presence-fan1", - "presence-fan0"; - }; - }; - }; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c14mux1chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - }; - - i2c14mux1chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - }; - - i2c14mux1chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - }; - - i2c14mux1chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - }; - }; -}; - -&i2c15 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c15mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - }; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c15mux1chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux1chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux1chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux1chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - }; - - i2c-switch@72 { - compatible = "nxp,pca9546"; - reg = <0x72>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c15mux2chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux2chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c15mux2chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c15mux2chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&emmc_controller { - status = "okay"; -}; - -&pinctrl_emmc_default { - bias-disable; -}; - -&emmc { - status = "okay"; - clk-phase-mmc-hs200 = <210>, <228>; -}; - -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - /* - * CFAM Reset is supposed to be active low but pass1 hardware is wired - * active high. - */ - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { /* DCM0_C0 */ - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { /* DCM0_C1 */ - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@2,0 { /* DCM1_C0 */ - reg = <2 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <2>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam2_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; - - cfam2_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; - - cfam2_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam2_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam2_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam2_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam2_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam2_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam2_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ2: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub2: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@3,0 { /* DCM1_C1 */ - reg = <3 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <3>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam3_i2c2: i2c-bus@2 { - reg = <2>; /* OM45 */ - }; - - cfam3_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam3_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam3_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam3_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam3_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam3_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam3_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam3_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ3: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub3: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@4,0 { /* DCM2_C0 */ - reg = <4 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <4>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam4_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; - - cfam4_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; - - cfam4_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam4_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam4_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam4_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam4_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam4_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam4_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam4_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam4_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam4_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ4: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub4: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@5,0 { /* DCM2_C1 */ - reg = <5 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <5>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam5_i2c2: i2c-bus@2 { - reg = <2>; /* OM45 */ - }; - - cfam5_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam5_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam5_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam5_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam5_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam5_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam5_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam5_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam5_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam5_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam5_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ5: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub5: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@6,0 { /* DCM3_C0 */ - reg = <6 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <6>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam6_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; - - cfam6_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; - - cfam6_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam6_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam6_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam6_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam6_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam6_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam6_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam6_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam6_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam6_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ6: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub6: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@7,0 { /* DCM3_C1 */ - reg = <7 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <7>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam7_i2c2: i2c-bus@2 { - reg = <2>; /* OM45 */ - }; - - cfam7_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam7_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam7_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam7_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam7_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam7_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam7_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam7_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam7_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam7_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam7_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ7: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub7: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -&fsi_occ2 { - reg = <3>; -}; - -&fsi_occ3 { - reg = <4>; -}; - -&fsi_occ4 { - reg = <5>; -}; - -&fsi_occ5 { - reg = <6>; -}; - -&fsi_occ6 { - reg = <7>; -}; - -&fsi_occ7 { - reg = <8>; -}; - -&ibt { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vuart1 { - status = "okay"; -}; - -&vuart2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, - <&syscon ASPEED_CLK_MAC4RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - status = "okay"; -}; - -&xdma { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8 0xcac>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts deleted file mode 100644 index f5f5b18c113a..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2021 IBM Corp. -/dts-v1/; - -#include "aspeed-bmc-ibm-rainier-4u.dts" - -/ { - model = "Rainier 1S4U"; -}; - -&max { - /delete-node/ fan3; - /delete-node/ fan5; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts deleted file mode 100644 index 342546a3c0f5..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2020 IBM Corp. -/dts-v1/; - -#include "aspeed-bmc-ibm-rainier.dts" - -/ { - model = "Rainier 4U"; -}; - -&i2c3 { - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts deleted file mode 100644 index 7162e65b8115..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ /dev/null @@ -1,2420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include -#include - -/ { - model = "Rainier 2U"; - compatible = "ibm,rainier-bmc", "aspeed,ast2600"; - - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; - i2c300 = &cfam2_i2c0; - i2c301 = &cfam2_i2c1; - i2c310 = &cfam2_i2c10; - i2c311 = &cfam2_i2c11; - i2c312 = &cfam2_i2c12; - i2c313 = &cfam2_i2c13; - i2c314 = &cfam2_i2c14; - i2c315 = &cfam2_i2c15; - i2c402 = &cfam3_i2c2; - i2c403 = &cfam3_i2c3; - i2c410 = &cfam3_i2c10; - i2c411 = &cfam3_i2c11; - i2c414 = &cfam3_i2c14; - i2c415 = &cfam3_i2c15; - i2c416 = &cfam3_i2c16; - i2c417 = &cfam3_i2c17; - - serial4 = &uart5; - i2c16 = &i2c2mux0; - i2c17 = &i2c2mux1; - i2c18 = &i2c2mux2; - i2c19 = &i2c2mux3; - i2c20 = &i2c4mux0chn0; - i2c21 = &i2c4mux0chn1; - i2c22 = &i2c4mux0chn2; - i2c23 = &i2c5mux0chn0; - i2c24 = &i2c5mux0chn1; - i2c25 = &i2c6mux0chn0; - i2c26 = &i2c6mux0chn1; - i2c27 = &i2c6mux0chn2; - i2c28 = &i2c6mux0chn3; - i2c29 = &i2c11mux0chn0; - i2c30 = &i2c11mux0chn1; - - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; - spi30 = &cfam2_spi0; - spi31 = &cfam2_spi1; - spi32 = &cfam2_spi2; - spi33 = &cfam2_spi3; - spi40 = &cfam3_spi0; - spi41 = &cfam3_spi1; - spi42 = &cfam3_spi2; - spi43 = &cfam3_spi3; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@b3e00000 { - compatible = "ramoops"; - reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x8000>; - pmsg-size = <0x8000>; - max-reason = <3>; /* KMSG_DUMP_EMERG */ - }; - - /* LPC FW cycle bridge region requires natural alignment */ - flash_memory: region@b4000000 { - no-map; - reg = <0xb4000000 0x04000000>; /* 64M */ - }; - - /* VGA region is dictated by hardware strapping */ - vga_memory: region@bf000000 { - no-map; - compatible = "shared-dma-pool"; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; - }; - - i2c2mux: i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - i2c-parent = <&i2c2>; - mux-gpios = <&gpio0 ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>, - <&gpio0 ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>; - idle-state = <0>; - - i2c2mux0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c2mux1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c2mux2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c2mux3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* BMC Card fault LED at the back */ - bmc-ingraham0 { - gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; - }; - - /* Enclosure ID LED at the back */ - rear-enc-id0 { - gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; - }; - - /* Enclosure fault LED at the back */ - rear-enc-fault0 { - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - }; - - /* PCIE slot power LED */ - pcieslot-power { - gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 8 GPIO_ACTIVE_LOW>; - linux,code = <8>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 9 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - - event-fan4-presence { - label = "fan4-presence"; - gpios = <&pca0 10 GPIO_ACTIVE_LOW>; - linux,code = <10>; - }; - - event-fan5-presence { - label = "fan5-presence"; - gpios = <&pca0 11 GPIO_ACTIVE_LOW>; - linux,code = <11>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc1 7>; - }; -}; - -&adc1 { - status = "okay"; - aspeed,int-vref-microvolt = <2500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","","","","","checkstop","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", - /*I0-I7*/ "","","","","","","bmc-secure-boot","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","usb-power","","","","", - /*P0-P7*/ "","","","","pcieslot-power","","","", - /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", - /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", - /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", - "power-ffs-sync-history","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","",""; - - i2c3_mux_oe_n { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C3_MUX_OE_N"; - }; - - usb_power { - gpio-hog; - gpios = ; - output-high; - }; -}; - -&emmc_controller { - status = "okay"; -}; - -&pinctrl_emmc_default { - bias-disable; -}; - -&emmc { - status = "okay"; - clk-phase-mmc-hs200 = <180>, <180>; -}; - -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - /* - * CFAM Reset is supposed to be active low but pass1 hardware is wired - * active high. - */ - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@2,0 { - reg = <2 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <2>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam2_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; - - cfam2_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; - - cfam2_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam2_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam2_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam2_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam2_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam2_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam2_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ2: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub2: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@3,0 { - reg = <3 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <3>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam3_i2c2: i2c-bus@2 { - reg = <2>; /* OM45 */ - }; - - cfam3_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam3_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam3_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam3_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam3_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam3_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam3_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam3_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ3: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub3: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -&fsi_occ2 { - reg = <3>; -}; - -&fsi_occ3 { - reg = <4>; -}; - -&ibt { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - tca_pres1: tca9554@20{ - compatible = "ti,tca9554"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "", - "RUSSEL_FW_I2C_ENABLE_N", - "RUSSEL_OPPANEL_PRESENCE_N", - "BLYTH_OPPANEL_PRESENCE_N", - "CPU_TPM_CARD_PRESENT_N", - "DASD_BP2_PRESENT_N", - "DASD_BP1_PRESENT_N", - "DASD_BP0_PRESENT_N"; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - power-supply@68 { - compatible = "ibm,cffps"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps"; - reg = <0x69>; - }; - - pca_pres1: pca9552@61 { - compatible = "nxp,pca9552"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLOT0_PRSNT_EN_RSVD", "SLOT1_PRSNT_EN_RSVD", - "SLOT2_PRSNT_EN_RSVD", "SLOT3_PRSNT_EN_RSVD", - "SLOT4_PRSNT_EN_RSVD", "SLOT0_EXPANDER_PRSNT_N", - "SLOT1_EXPANDER_PRSNT_N", "SLOT2_EXPANDER_PRSNT_N", - "SLOT3_EXPANDER_PRSNT_N", "SLOT4_EXPANDER_PRSNT_N", - "", "", "", "", "", ""; - }; -}; - -&i2c4 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; - - pca9546@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c4mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard0-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard0-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c4mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - - i2c4mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - pca9546@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c5mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard3-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard3-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c5mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - pca9551@61 { - compatible = "nxp,pca9551"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard4-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard4-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; - - tmp275@4b { - compatible = "ti,tmp275"; - reg = <0x4b>; - }; - - pca9546@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c6mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - - i2c6mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; - - i2c6mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - i2c6mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - }; -}; - -&i2c7 { - multi-master; - status = "okay"; - - pca9552@30 { - compatible = "ibm,pca9552"; - reg = <0x30>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "pcieslot0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "pcieslot1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "pcieslot2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "pcieslot3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "pcieslot4"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "cpu1"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "cpu-vrm1"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "lcd-russel"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pca9552@31 { - compatible = "ibm,pca9552"; - reg = <0x31>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "ddimm0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "ddimm1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "ddimm2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "ddimm3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "ddimm4"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "ddimm5"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "ddimm6"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "ddimm7"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "ddimm8"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "ddimm9"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "ddimm10"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "ddimm11"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "ddimm12"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "ddimm13"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "ddimm14"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "ddimm15"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pca9552@32 { - compatible = "ibm,pca9552"; - reg = <0x32>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "ddimm16"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "ddimm17"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "ddimm18"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "ddimm19"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "ddimm20"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "ddimm21"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "ddimm22"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "ddimm23"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "ddimm24"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "ddimm25"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "ddimm26"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "ddimm27"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "ddimm28"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "ddimm29"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "ddimm30"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "ddimm31"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pca9552@33 { - compatible = "ibm,pca9552"; - reg = <0x33>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "planar"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cpu0"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "dasd-pyramid0"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "dasd-pyramid1"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "dasd-pyramid2"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "cpu0-vrm0"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "rtc-battery"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@8 { - label = "base-blyth"; - reg = <8>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@9 { - label = "pcieslot6"; - reg = <9>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@10 { - label = "pcieslot7"; - reg = <10>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@11 { - label = "pcieslot8"; - reg = <11>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@12 { - label = "pcieslot9"; - reg = <12>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@13 { - label = "pcieslot10"; - reg = <13>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@14 { - label = "pcieslot11"; - reg = <14>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@15 { - label = "tpm-wilson"; - reg = <15>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - si7021-a20@40 { - compatible = "silabs,si7020"; - reg = <0x40>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - max: max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan0: fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - }; - - fan1: fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - }; - - fan2: fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - }; - - fan3: fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - }; - - fan4: fan@4 { - compatible = "pmbus-fan"; - reg = <4>; - tach-pulses = <2>; - }; - - fan5: fan@5 { - compatible = "pmbus-fan"; - reg = <5>; - tach-pulses = <2>; - }; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "front-sys-id0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "front-check-log0"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "front-enc-fault1"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "front-sys-pwron0"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - pca0: pca9552@61 { - compatible = "nxp,pca9552"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "fan0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "fan1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "fan2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "fan3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "fan4"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "fan5"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - - ibm-panel@62 { - compatible = "ibm,op-panel"; - reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c8 { - status = "okay"; - - ucd90320@11 { - compatible = "ti,ucd90320"; - reg = <0x11>; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - pca_pres3: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "power-config-full-load", ""; - }; - - pca_pres2: pca9552@61 { - compatible = "nxp,pca9552"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLOT6_PRSNT_EN_RSVD", "SLOT7_PRSNT_EN_RSVD", - "SLOT8_PRSNT_EN_RSVD", "SLOT9_PRSNT_EN_RSVD", - "SLOT10_PRSNT_EN_RSVD", "SLOT11_PRSNT_EN_RSVD", - "SLOT6_EXPANDER_PRSNT_N", "SLOT7_EXPANDER_PRSNT_N", - "SLOT8_EXPANDER_PRSNT_N", "SLOT9_EXPANDER_PRSNT_N", - "SLOT10_EXPANDER_PRSNT_N", "SLOT11_EXPANDER_PRSNT_N", - "", "", "", ""; - }; - -}; - -&i2c9 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - tmp423b@4d { - compatible = "ti,tmp423"; - reg = <0x4d>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; -}; - -&i2c10 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - tmp423b@4d { - compatible = "ti,tmp423"; - reg = <0x4d>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; -}; - -&i2c11 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - pca9546@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c11mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard10-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "cablecard10-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; - }; - - i2c11mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - }; -}; - -&i2c12 { - status = "okay"; - - tpm@2e { - compatible = "nuvoton,npct75x"; - reg = <0x2e>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c13 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "nvme0"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "nvme1"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "nvme2"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "nvme3"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "nvme4"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "nvme5"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "nvme6"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "nvme7"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; -}; - -&i2c14 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "nvme8"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "nvme9"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "nvme10"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "nvme11"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "nvme12"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "nvme13"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "nvme14"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "nvme15"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; -}; - -&i2c15 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "nvme16"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@1 { - label = "nvme17"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@2 { - label = "nvme18"; - reg = <2>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@3 { - label = "nvme19"; - reg = <3>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@4 { - label = "nvme20"; - reg = <4>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@5 { - label = "nvme21"; - reg = <5>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@6 { - label = "nvme22"; - reg = <6>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - - led@7 { - label = "nvme23"; - reg = <7>; - retain-state-shutdown; - default-state = "keep"; - type = ; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&vuart1 { - status = "okay"; -}; - -&vuart2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, - <&syscon ASPEED_CLK_MAC4RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - status = "okay"; -}; - -&xdma { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8 0xcac>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts deleted file mode 100644 index 208b0f094ed9..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ /dev/null @@ -1,912 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include -#include - -/ { - model = "FP5280G2 BMC"; - compatible = "inspur,fp5280g2-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - coldfire_memory: codefire_memory@9ef00000 { - reg = <0x9ef00000 0x00100000>; - no-map; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca1 0 GPIO_ACTIVE_LOW>; - linux,code = <1>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca1 1 GPIO_ACTIVE_LOW>; - linux,code = <2>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca1 2 GPIO_ACTIVE_LOW>; - linux,code = <3>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca1 3 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - event-fan4-presence { - label = "fan4-presence"; - gpios = <&pca1 4 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - event-fan5-presence { - label = "fan5-presence"; - gpios = <&pca1 5 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-fan6-presence { - label = "fan6-presence"; - gpios = <&pca1 6 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - event-fan7-presence { - label = "fan7-presence"; - gpios = <&pca1 7 GPIO_ACTIVE_LOW>; - linux,code = <8>; - }; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "power"; - /* TODO: dummy gpio */ - gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; - }; - - init-ok { - label = "init-ok"; - gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; - }; - - front-memory { - label = "front-memory"; - gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; - }; - - front-syshot { - label = "front-syshot"; - gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; - }; - - front-syshealth { - label = "front-syshealth"; - gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; - }; - - front-fan { - label = "front-fan"; - gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; - }; - - front-psu { - label = "front-psu"; - gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - label = "identify"; - gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, - <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>; - }; - -}; - -&gpio { - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","front-psu","checkstop","cfam-reset","","","init-ok", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "ps0-presence","ps1-presence","","","front-memory","","","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","front-fan","","","", - /*I0-I7*/ "front-syshealth","front-syshot","mux-gpios","enable-gpios","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","power","trans-gpios","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","identify", - /*AA0-AA7*/ "clock-gpios","","data-gpios","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* Test Point */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart3 { - /* APSS */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - /* LCD */ - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - label = "fru"; - }; - -}; - -&i2c2 { - status = "okay"; - - tmp112@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - label = "inlet"; - }; - - tmp112@49 { - compatible = "ti,tmp112"; - reg = <0x49>; - label = "outlet"; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tmp112@4a { - compatible = "ti,tmp112"; - reg = <0x4a>; - label = "psu_inlet"; - }; - - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tmp112@4a { - compatible = "ti,tmp112"; - reg = <0x4a>; - label = "ocp_zone"; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - tmp112@4a { - compatible = "ti,tmp112"; - reg = <0x4a>; - label = "bmc_zone"; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - tmp112@7c { - compatible = "microchip,emc1413"; - reg = <0x7c>; - }; - }; - - }; -}; - -&i2c3 { - /* Riser Card */ - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; -}; - -&i2c5 { - /* vr */ - status = "okay"; -}; - -&i2c6 { - /* bp card */ - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - }; - - adm1278@13 { - compatible = "adi,adm1278"; - reg = <0x13>; - }; - - adm1278@50 { - compatible = "adi,adm1278"; - reg = <0x50>; - }; - - adm1278@53 { - compatible = "adi,adm1278"; - reg = <0x53>; - }; - - }; - - /*pcie riser*/ - - }; -}; - -&i2c8 { - status = "okay"; - - pca0: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - }; - - pca1: pca9555@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca2: pca9555@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca3: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca4: pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca5: pca9555@25 { - compatible = "nxp,pca9555"; - reg = <0x25>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - -}; - -&i2c9 { - /* cpld */ - status = "okay"; -}; - -&i2c10 { - /* hdd bp */ - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - power-supply@58 { - compatible = "inspur,ipsps1"; - reg = <0x58>; - }; - - power-supply@59 { - compatible = "inspur,ipsps1"; - reg = <0x59>; - }; -}; - -&i2c12 { - /* odcc */ - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&ibt { - status = "okay"; - -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default - &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default - &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default - &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; - }; - - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; - }; - - fan@7 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; - }; - -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts deleted file mode 100644 index b3c1e3ba5831..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts +++ /dev/null @@ -1,691 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2021 Inspur Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include -#include - -/ { - model = "NF5280M6 BMC"; - compatible = "inspur,nf5280m6-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - bmc_alive { - label = "bmc_alive"; - gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - led-pattern = <1000 1000>; - }; - - front-fan { - label = "front-fan"; - gpios = <&gpio ASPEED_GPIO(F,2) GPIO_ACTIVE_LOW>; - }; - - front-psu { - label = "front-psu"; - gpios = <&gpio ASPEED_GPIO(F,3) GPIO_ACTIVE_LOW>; - }; - - front-syshot { - label = "front-syshot"; - gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; - }; - - front-memory { - label = "front-memory"; - gpios = <&gpio ASPEED_GPIO(S, 7) GPIO_ACTIVE_LOW>; - }; - - identify { - label = "identify"; - gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bios"; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&gpio { - status = "okay"; - /* Enable GPIOE0 and GPIOE2 pass-through by default */ - pinctrl-names = "pass-through"; - pinctrl-0 = <&pinctrl_gpie0_default - &pinctrl_gpie2_default>; - gpio-line-names = - /*A0-A7*/ "","MAC2LINK","BMC_RESET_CPLD","","BMC_SCL9","","MAC2MDC_R","", - /*B0-B7*/ "BMC_INIT_OK","FM_SKU_ID2","FM_SPD_DDRCPU_LVLSHFT_DIS_R_N", - "FM_CPU_MSMI_CATERR_LVT3_BMC_N","","FM_CPU0_PROCHOT_LVT3_N", - "FM_CPU_MEM_THERMTRIP_LVT3_N","BIOS_LOAD_DEFAULT_R_N", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","BMC_SD2CMD","BMC_SD2DAT0","BMC_SD2DAT1","BMC_SD2DAT2", - "BMC_SD2DAT3","BMC_SD2DET","BMC_SD2WPT", - /*E0-E7*/ "FM_BOARD_ID0","FM_BOARD_ID1","FM_BOARD_ID2","FM_BOARD_ID3", - "FM_BOARD_ID4","FM_BOARD_ID5","","", - /*F0-F7*/ "PSU1_PRESENT_N","PSU2_PRESENT_N","FAN_FAULT_LED_N","PSU_FAULT_LED_N", - "BIOS_DEBUG_MODE_N","FP_LCD_RESET","FAN_TYPE_SEL", - "RST_GLB_RST_WARN_N", - /*G0-G7*/ "IRQ_LPTM21L_ALERT_N","IRQ_PLD_ALERT_N","AC_FAIL_N","FP_LCD_PRESENT_BMC", - "BMC_JTAG_TCK_MUX_SEL","BMC_BIOS_RESERVED","SYS_NMI_N","BMC_NMI_N", - /*H0-H7*/ "JTAG_BMC_TDI","JTAG_BMC_TDO","JTAG_BMC_TCK","JTAG_BMC_TMS","FM_BOARD_ID6", - "FM_SKU_ID0","IRQ_SML1_PMBUS_ALERT_N","IRQ_SML0_ALERT_MUX_N", - /*I0-I7*/ "FM_CPU_ERR0_LVT3_BMC_N","FM_CPU_ERR1_LVT3_BMC_N","FM_BMC_PCH_SCI_LPC_N", - "FM_SYS_THROTTLE_LVC3","SPI2_PCH_CS0_N","","","", - /*J0-J7*/ "FM_CPU0_SKTOCC_LVT3_N","FM_CPU1_SKTOCC_LVT3_N","","SYSHOT_FAULT_LED_N", - "VGA_HSYNC","VGA_VSYNC","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","SYS_UART_TXD1","SYS_UART_RXD1", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","FM_PCH_BMC_THERMTRIP_N","INTRUDER_N", - /*R0-R7*/ "SPI_BMC_BOOT_CS1_R_N","FM_CPU_MEMHOT_LVC3_N", - "DBP_CPU_PREQ_N","FM_CPU_ERR2_LVT3_BMC_N", - "RISER_NCSI_EN_N","","LOM_NCSI_EN_N","OCP_NCSI_EN_N", - /*S0-S7*/ "BMC_XDP_PRDY_N","SIO_POWER_GOOD","BMC_PWR_DEBUG_R_N","BMC_DEBUG_EN_R_N","", - "GPIOS5_BMC","","GPIOS7_BMC", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","BMC_DET_UID_N","BMC_JTAG_SEL","SIO_ONCONTROL","","","","", - /*Z0-Z7*/ "XDP_PRESENT_N","DBP_SYSPWROK","BMC_JTAG_SEL","FM_SMI_ACTIVE_N","", - "GPIOZ5","","", - /*AA0-AA7*/ "FP_BMC_SYSLED_N","PS_PWROK","RST_PLTRST_BMC_N","HDA_SDO_BMC", - "FM_SLPS4_R_N","","POWER_BUTTON","POWER_OUT", - /*AB0-AB7*/ "RESET_OUT","RESET_BUTTON","BIOS_REFLASH","POST_COMPLETE","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&i2c0 { - /* FP_LCD */ - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - label = "fru"; - }; -}; - -&i2c2 { - status = "okay"; - - tmp112@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - label = "inlet"; - }; - - tmp112@49 { - compatible = "ti,tmp112"; - reg = <0x49>; - label = "outlet"; - }; - - pca9548@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - }; -}; - -&i2c3 { - status = "okay"; - - pca9548@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - }; - - pca9548@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - }; - - pca9548@72 { - compatible = "nxp,pca9548"; - reg = <0x72>; - }; -}; - -&i2c4 { - /* IPMB */ - status = "okay"; -}; - -&i2c5 { - status = "okay"; - - pca9548@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - }; -}; - -&i2c6 { - status = "okay"; - - pca9548@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - }; -}; - -&i2c7 { - status = "okay"; - - adm1278@33 { - compatible = "adi,adm1293"; - reg = <0x33>; - }; - - adm1278@32 { - compatible = "adi,adm1293"; - reg = <0x32>; - }; - - adm1278@20 { - compatible = "adi,adm1293"; - reg = <0x20>; - }; -}; - -&i2c8 { - status = "okay"; - - pca0: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - }; - - pca1: pca9555@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca2: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca3: pca9555@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; -}; - -&i2c9 { - /* cpld */ - status = "okay"; -}; - -&i2c10 { - status = "okay"; - - pca4: pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca5: pca9555@25 { - compatible = "nxp,pca9555"; - reg = <0x25>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - }; -}; - -&i2c11 { - status = "okay"; - - power-supply@58 { - compatible = "inspur,ipsps1"; - reg = <0x58>; - }; - - power-supply@59 { - compatible = "inspur,ipsps1"; - reg = <0x59>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; - }; - - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; - }; - - fan@7 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; - }; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&kcs4 { - status = "okay"; - aspeed,lpc-io-reg = <0xca4>; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default - &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default - &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default - &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&vuart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts deleted file mode 100644 index 5a98a19f445e..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Inspur Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "ON5263M5 BMC"; - compatible = "inspur,on5263m5-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "earlycon"; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - bmc_alive { - label = "bmc_alive"; - gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c6 { - status = "okay"; - - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - - tmp112@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c7 { - status = "okay"; - - adm1278@11 { - compatible = "adi,adm1278"; - reg = <0x11>; - }; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; -}; - -&adc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts deleted file mode 100644 index d5b7d28cda88..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017 Intel Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" - -/ { - model = "S2600WF BMC"; - compatible = "intel,s2600wf-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts b/arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts deleted file mode 100644 index caf66651e5b5..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts +++ /dev/null @@ -1,328 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2021 Inventec Corp. - -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include "aspeed-g6-pinctrl.dtsi" -#include -#include - -/ { - model = "TRANSFORMERS BMC"; - compatible = "inventec,transformer-bmc", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - // UID led - uid { - label = "UID_LED"; - gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; - }; - - // Heart beat led - heartbeat { - label = "HB_LED"; - gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio0 { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mac3 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <33000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; -#include "openbmc-flash-layout.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "bmc2"; - spi-max-frequency = <33000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bios"; - spi-max-frequency = <33000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - }; -}; - -&wdt1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - //Set bmc' slave address; - bmc_slave@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - // FRU AT24C512C-SSHM-T - status = "okay"; - eeprom@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - pagesize = <128>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp75@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - tmp75@4f { - compatible = "ti,tmp75"; - reg = <0x4f>; - }; - - tmp468@48 { - compatible = "ti,tmp468"; - reg = <0x48>; - }; -}; - -&i2c7 { - status = "okay"; - adm1278@40 { - compatible = "adi,adm1278"; - reg = <0x40>; - }; -}; - - -&i2c8 { - // FRU AT24C512C-SSHM-T - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c512"; - reg = <0x51>; - pagesize = <128>; - }; - - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - pagesize = <128>; - }; -}; - -&i2c9 { - // M.2 - status = "okay"; -}; - -&i2c10 { - // I2C EXPANDER - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - }; -}; - -&i2c11 { - // I2C EXPANDER - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - pcie_eeprom_riser1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@55 { - compatible = "atmel,24c512"; - reg = <0x55>; - pagesize = <128>; - }; - }; - - pcie_eeprom_riser2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@55 { - compatible = "atmel,24c512"; - reg = <0x55>; - pagesize = <128>; - }; - }; - - pcie_eeprom_riser3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@55 { - compatible = "atmel,24c512"; - reg = <0x55>; - pagesize = <128>; - }; - }; - }; -}; - -&i2c12 { - status = "okay"; - - psu0:psu0@58 { - compatible = "pmbus"; - reg = <0x58>; - }; -}; - -&gpio0 { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","power-chassis-control","","","", - /*G0-G7*/ "","","jtag-mux","","","","","", - /*H0-H7*/ "","","","","reset-button","power-button","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","tck-mux","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","nmi-button","","","","","","", - /*V0-V7*/ "","","","","power-config-full-load","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; - non-removable; - max-frequency = <52000000>; - bus-width = <8>; -}; - -&vhub { - status = "okay"; - aspeed,vhub-downstream-ports = <7>; - aspeed,vhub-generic-endpoints = <21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ad_default>; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts deleted file mode 100644 index 8f543cca7c21..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts +++ /dev/null @@ -1,569 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Lenovo Hr630 platform - * - * Copyright (C) 2019-present Lenovo - */ - -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "HR630 BMC"; - compatible = "lenovo,hr630-bmc", "aspeed,ast2500"; - - aliases { - i2c14 = &i2c_rbp; - i2c15 = &i2c_fbp1; - i2c16 = &i2c_fbp2; - i2c17 = &i2c_fbp3; - i2c18 = &i2c_riser2; - i2c19 = &i2c_pcie4; - i2c20 = &i2c_riser1; - i2c21 = &i2c_ocp; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x00100000>; /* 1M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>; - }; - - fault { - gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, - <&adc 12>, <&adc 13>, <&adc 14>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default - &pinctrl_nrts2_default - &pinctrl_ndtr2_default - &pinctrl_ndsr2_default - &pinctrl_ncts2_default - &pinctrl_ndcd2_default - &pinctrl_nri2_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&adc { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default>; -}; - -&i2c0 { - status = "okay"; - /* temp1 inlet */ - tmp75@4e { - compatible = "national,lm75"; - reg = <0x4e>; - }; -}; - -&i2c1 { - status = "okay"; - /* temp2 outlet */ - tmp75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - /* Slot 0, - * Slot 1, - * Slot 2, - * Slot 3 - */ - - i2c-switch@70 { - compatible = "nxp,pca9545"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; /* may use mux@70 next. */ - - i2c_rbp: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_fbp1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_fbp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_fbp3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c7 { - status = "okay"; - - /* Slot 0, - * Slot 1, - * Slot 2, - * Slot 3 - */ - i2c-switch@76 { - compatible = "nxp,pca9546"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; /* may use mux@76 next. */ - - i2c_riser2: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_pcie4: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_riser1: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_ocp: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c8 { - status = "okay"; - - eeprom@57 { - compatible = "atmel,24c256"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@12 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@13 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; -}; - -&gpio { - - pin_gpio_b5 { - gpio-hog; - gpios = ; - output-high; - line-name = "IRQ_BMC_PCH_SMI_LPC_N"; - }; - - pin_gpio_f0 { - gpio-hog; - gpios = ; - output-low; - line-name = "IRQ_BMC_PCH_NMI_R"; - }; - - pin_gpio_f3 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_BUS0_RST_OUT_N"; - }; - - pin_gpio_f4 { - gpio-hog; - gpios = ; - output-low; - line-name = "FM_SKT0_FAULT_LED"; - }; - - pin_gpio_f5 { - gpio-hog; - gpios = ; - output-low; - line-name = "FM_SKT1_FAULT_LED"; - }; - - pin_gpio_g4 { - gpio-hog; - gpios = ; - output-high; - line-name = "FAN_PWR_CTL_N"; - }; - - pin_gpio_g7 { - gpio-hog; - gpios = ; - output-high; - line-name = "RST_BMC_PCIE_I2CMUX_N"; - }; - - pin_gpio_h2 { - gpio-hog; - gpios = ; - output-high; - line-name = "PSU1_FFS_N_R"; - }; - - pin_gpio_h3 { - gpio-hog; - gpios = ; - output-high; - line-name = "PSU2_FFS_N_R"; - }; - - pin_gpio_i3 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_INTRUDED_COVER"; - }; - - pin_gpio_j2 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_BIOS_UPDATE_N"; - }; - - pin_gpio_j3 { - gpio-hog; - gpios = ; - output-high; - line-name = "RST_BMC_HDD_I2CMUX_N"; - }; - - pin_gpio_s2 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_VGA_SW"; - }; - - pin_gpio_s4 { - gpio-hog; - gpios = ; - output; - line-name = "VBAT_EN_N"; - }; - - pin_gpio_s6 { - gpio-hog; - gpios = ; - output-high; - line-name = "PU_BMC_GPIOS6"; - }; - - pin_gpio_y0 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_NCSI_MUX_CTL_S0"; - }; - - pin_gpio_y1 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_NCSI_MUX_CTL_S1"; - }; - - pin_gpio_z0 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_RISER2_INT_N"; - }; - - pin_gpio_z2 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_RISER2_RESET_N"; - }; - - pin_gpio_z3 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_PCH_SCI_LPC_N"; - }; - - pin_gpio_z7 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_POST_CMPLT_N"; - }; - - pin_gpio_aa0 { - gpio-hog; - gpios = ; - output-low; - line-name = "HOST_BMC_USB_SEL"; - }; - - pin_gpio_aa5 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_BUS1_RST_OUT_N"; - }; - -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts deleted file mode 100644 index bcc1820f5c07..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts +++ /dev/null @@ -1,666 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Lenovo Hr855xg2 platform - * - * Copyright (C) 2019-present Lenovo - */ - -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "HR855XG2 BMC"; - compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500"; - - aliases { - i2c14 = &i2c_riser1; - i2c15 = &i2c_riser2; - i2c16 = &i2c_riser3; - i2c17 = &i2c_M2; - i2c18 = &channel_0; - i2c19 = &channel_1; - i2c20 = &channel_2; - i2c21 = &channel_3; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x00100000>; /* 1M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>; - }; - - fault { - gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>,<&adc 11>, - <&adc 12>,<&adc 13>,<&adc 14>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default - &pinctrl_nrts2_default - &pinctrl_ndtr2_default - &pinctrl_ndsr2_default - &pinctrl_ncts2_default - &pinctrl_ndcd2_default - &pinctrl_nri2_default>; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&adc{ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9545"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_riser1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_riser2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_riser3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_M2: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c1 { - status = "okay"; - bus-frequency = <90000>; - HotSwap@10 { - compatible = "adm1272"; - reg = <0x10>; - }; - - VR@45 { - compatible = "pmbus"; - reg = <0x45>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - channel_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - /* temp1 */ - tmp75@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - /* temp2 */ - tmp75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; - - eeprom@54 { - compatible = "atmel,24c256"; - reg = <0x54>; - pagesize = <16>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default - &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@12 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@13 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; - - fan@14 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e>; - }; - - fan@15 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0f>; - }; - - fan@16 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0f>; - }; -}; - -&gpio { - - pin_gpio_a1 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_EMMC_RST_N"; - }; - - pin_gpio_a3 { - gpio-hog; - gpios = ; - output-high; - line-name = "PCH_PWROK_BMC_FPGA"; - }; - - pin_gpio_b5 { - gpio-hog; - gpios = ; - output-high; - line-name = "IRQ_BMC_PCH_SMI_LPC_N"; - }; - - pin_gpio_b7 { - gpio-hog; - gpios = ; - output-low; - line-name = "CPU_SM_WP"; - }; - - pin_gpio_e0 { - gpio-hog; - gpios = ; - input; - line-name = "PDB_PSU_SEL"; - }; - - pin_gpio_e2 { - gpio-hog; - gpios = ; - output-high; - line-name = "LOCATOR_LED_N"; - }; - - pin_gpio_e5 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_DBP_PRESENT_R1_N"; - }; - - pin_gpio_e6 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_ME_SECURITY_OVERRIDE_N"; - }; - - pin_gpio_f0 { - gpio-hog; - gpios = ; - output-high; - line-name = "IRQ_BMC_PCH_NMI_R"; - }; - - pin_gpio_f1 { - gpio-hog; - gpios = ; - input; - line-name = "CPU2_PROCDIS_BMC_N"; - }; - - pin_gpio_f2 { - gpio-hog; - gpios = ; - output-high; - line-name = "RM_THROTTLE_EN_N"; - }; - - pin_gpio_f3 { - gpio-hog; - gpios = ; - output-low; - line-name = "FM_PMBUS_ALERT_B_EN"; - }; - - pin_gpio_f4 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_FORCE_NM_THROTTLE_N"; - }; - - pin_gpio_f6 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_CPU_PWR_DEBUG_N"; - }; - - pin_gpio_g7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_PCIE_I2C_MUX_RST_N"; - }; - - pin_gpio_h6 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_DBP_PRESENT_R2_N"; - }; - - pin_gpio_i3 { - gpio-hog; - gpios = ; - output-high; - line-name = "SPI_BMC_BIOS_WP_N"; - }; - - pin_gpio_j1 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_USB_SEL"; - }; - - pin_gpio_j2 { - gpio-hog; - gpios = ; - output-high; - line-name = "PDB_SMB_RST_N"; - }; - - pin_gpio_j3 { - gpio-hog; - gpios = ; - output-high; - line-name = "SPI_BMC_BIOS_HOLD_N"; - }; - - pin_gpio_l0 { - gpio-hog; - gpios = ; - output-high; - line-name = "PDB_FAN_TACH_SEL"; - }; - - pin_gpio_l1 { - gpio-hog; - gpios = ; - output-high; - line-name = "SYS_RESET_BMC_FPGA_N"; - }; - - pin_gpio_l4 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_EFUSE_FAN_G1_EN"; - }; - - pin_gpio_l5 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_EFUSE_FAN_G2_EN"; - }; - - pin_gpio_r6 { - gpio-hog; - gpios = ; - input; - line-name = "CPU3_PROCDIS_BMC_N"; - }; - - pin_gpio_r7 { - gpio-hog; - gpios = ; - input; - line-name = "CPU4_PROCDIS_BMC_N"; - }; - - pin_gpio_s1 { - gpio-hog; - gpios = ; - output-low; - line-name = "DBP_SYSPWROK_BMC"; - }; - - pin_gpio_s2 { - gpio-hog; - gpios = ; - output-high; - line-name = "PCH_RST_RSMRST_N"; - }; - - pin_gpio_s6 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_HW_STRAP_5"; - }; - - pin_gpio_z3 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_PCH_SCI_LPC_N"; - }; - - pin_gpio_aa0 { - gpio-hog; - gpios = ; - output-low; - line-name = "FW_PSU_ALERT_EN_N"; - }; - - pin_gpio_aa4 { - gpio-hog; - gpios = ; - output-high; - line-name = "DBP_CPU_PREQ_N"; - }; - - pin_gpio_ab3 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_WDTRST"; - }; - - pin_gpio_ac6 { - gpio-hog; - gpios = ; - output-high; - line-name = "ESPI_BMC_ALERT_N"; - }; - -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts deleted file mode 100644 index 3ef8358ff764..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts +++ /dev/null @@ -1,207 +0,0 @@ -//SPDX-License-Identifier: GPL-2.0+ - -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Olympus BMC"; - compatible = "microsoft,olympus-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@5f000000 { - no-map; - reg = <0x5f000000 0x01000000>; /* 16M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - bmc_heartbeat { - gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; - }; - - power_green { - gpios = <&gpio ASPEED_GPIO(U, 2) GPIO_ACTIVE_HIGH>; - }; - - power_amber { - gpios = <&gpio ASPEED_GPIO(U, 3) GPIO_ACTIVE_HIGH>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - }; - - fault { - gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; - }; - }; - - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default>; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&wdt2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts deleted file mode 100644 index c0847636f20b..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Inventec Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Lanyang BMC"; - compatible = "inventec,lanyang-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - sys_boot_status { - label = "System_boot_status"; - gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_LOW>; - }; - - attention { - label = "Attention_locator"; - gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>; - }; - - plt_fault { - label = "Platform_fault"; - gpios = <&gpio ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>; - }; - - hdd_fault { - label = "Onboard_drive_fault"; - gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_HIGH>; - }; - bmc_err { - lable = "BMC_fault"; - gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; - }; - - sys_err { - lable = "Sys_fault"; - gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - - clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 13>, <&adc 14>, <&adc 15>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2cs0_default - &pinctrl_spi2cs1_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default>; - - flash@0 { - status = "okay"; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@55 { - compatible = "atmel,24c64"; - reg = <0x55>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - tmp75@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_b0 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_HDD1_PWR_EN"; - }; - - pin_gpio_b5 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_USB1_OCI2"; - }; - - pin_gpio_h5 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_CP0_PERST_ENABLE_R"; - }; - - pin_gpio_z2 { - gpio-hog; - gpios = ; - output-high; - line-name = "RST_PCA9546_U177_N"; - }; - - pin_gpio_aa6 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_CP0_RESET_N"; - }; - - pin_gpio_aa7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_TPM_RESET_N"; - }; - - pin_gpio_ab0 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_USB_PWRON_N"; - }; -}; - -&ibt { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts deleted file mode 100644 index 31ff19ef87a0..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts +++ /dev/null @@ -1,667 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Mowgli BMC"; - compatible = "ibm,mowgli-bmc", "aspeed,ast2500"; - - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - button-id { - label = "id-button"; - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; - linux,code = <10>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; - linux,code = <11>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - - event-fan4-presence { - label = "fan4-presence"; - gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - }; - - leds { - compatible = "gpio-leds"; - - front-fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; - }; - - power-button { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; - }; - - front-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; - }; - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; - }; - - fan4 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon-12v { - compatible = "iio-hwmon"; - io-channels = <&adc 0>; - }; - - iio-hwmon-5v { - compatible = "iio-hwmon"; - io-channels = <&adc 1>; - }; - - iio-hwmon-3v { - compatible = "iio-hwmon"; - io-channels = <&adc 2>; - }; - - iio-hwmon-vdd { - compatible = "iio-hwmon"; - io-channels = <&adc 3>; - }; - - iio-hwmon-vcs { - compatible = "iio-hwmon"; - io-channels = <&adc 5>; - }; - - iio-hwmon-vdn { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - iio-hwmon-vio { - compatible = "iio-hwmon"; - io-channels = <&adc 9>; - }; - - iio-hwmon-vddra { - compatible = "iio-hwmon"; - io-channels = <&adc 11>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - iio-hwmon-vddrb { - compatible = "iio-hwmon"; - io-channels = <&adc 13>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "obmc-ubi"; - }; - }; - }; - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - /* CPU MFG CONN */ - -}; - -&i2c3 { - status = "okay"; - - /* APSS */ - /* CPLD */ - - /* PCA9516 (repeater) -> - * CLK Buffer 9FGS9092 - * Power Supply 0 - * Power Supply 1 - * PCA 9552 LED - */ - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - gpio@1 { - reg = <1>; - type = ; - }; - gpio@2 { - reg = <2>; - type = ; - }; - gpio@3 { - reg = <3>; - type = ; - }; - gpio@4 { - reg = <4>; - type = ; - }; - gpio@5 { - reg = <5>; - type = ; - }; - gpio@6 { - reg = <6>; - type = ; - }; - gpio@7 { - reg = <7>; - type = ; - }; - gpio@8 { - reg = <8>; - type = ; - }; - gpio@9 { - reg = <9>; - type = ; - }; - gpio@10 { - reg = <10>; - type = ; - }; - gpio@11 { - reg = <11>; - type = ; - }; - gpio@12 { - reg = <12>; - type = ; - }; - gpio@13 { - reg = <13>; - type = ; - }; - gpio@14 { - reg = <14>; - type = ; - }; - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps1"; - reg = <0x69>; - }; -}; - -&i2c4 { - status = "okay"; - - /* CP0 VDD & VCS : IR35221 */ - /* CP0 VDN & VIO : IR35221 */ - /* CP0 VDDR : IR35221 */ - - ir35221@28 { - compatible = "infineon,ir35221"; - reg = <0x28>; - }; - - ir35221@29 { - compatible = "infineon,ir35221"; - reg = <0x29>; - }; - - ir35221@2d { - compatible = "infineon,ir35221"; - reg = <0x2d>; - }; - -}; - -&i2c5 { - status = "disabled"; -}; - -&i2c6 { - status = "disabled"; -}; - -&i2c7 { - status = "disabled"; -}; - -&i2c8 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c9 { - status = "okay"; - - /* PCIe G3 x16 slot */ -}; - -&i2c10 { - status = "disabled"; -}; - -&i2c11 { - status = "okay"; - - /* CPLD */ - /* TPM */ - /* RTC RX8900CE */ - /* TMP275A */ - /* TMP275A */ - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - -}; - -&i2c12 { - status = "disabled"; -}; - -&i2c13 { - status = "disabled"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts deleted file mode 100644 index ac0d666ca10e..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2019 YADRO -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Nicole BMC"; - compatible = "yadro,nicole-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - coldfire_memory: codefire_memory@9ef00000 { - reg = <0x9ef00000 0x00100000>; - no-map; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "platform:green:power"; - gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; - }; - - identify { - label = "platform:blue:indicator"; - gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>; - }; - - fault { - label = "platform:red:fault"; - gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>; - }; - - attention { - label = "platform:yellow:alarm"; - gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&i2c2 { - status = "okay"; - /* CPU0 characterization connector */ -}; - -&i2c3 { - status = "okay"; - /* CLK GEN SI5338 */ -}; - -&i2c4 { - status = "okay"; - /* Voltage regulators for CPU0 */ -}; - -&i2c5 { - status = "okay"; - /* Voltage regulators for CPU1 */ -}; - -&i2c6 { - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&i2c7 { - status = "okay"; - /* CPLD */ -}; - -&gpio { - gpio-line-names = - /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf", - "func_mode0","func_mode1","func_mode2","","", - /*E0-E7*/ "","ncsi_cfg","","","","","","", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","checkstop","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","power-button","","","","","", - /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","", - /*Q0-Q7*/ "","","","","","","","id-button", - /*R0-R7*/ "","software_pwrgood","","","","","","", - /*S0-S7*/ "","","","","","","","seq_cont", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault", - "led-power","","","led-identify", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; - - func_mode0 { - gpio-hog; - gpios = ; - output-low; - }; - func_mode1 { - gpio-hog; - gpios = ; - output-low; - }; - func_mode2 { - gpio-hog; - gpios = ; - output-low; - }; - seq_cont { - gpio-hog; - gpios = ; - output-low; - }; - ncsi_cfg { - gpio-hog; - input; - gpios = ; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&ibt { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&adc { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts deleted file mode 100644 index 45631b47a7b3..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Palmetto BMC"; - compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@5f000000 { - no-map; - reg = <0x5f000000 0x01000000>; /* 16M */ - }; - - coldfire_memory: codefire_memory@5ee00000 { - reg = <0x5ee00000 0x00200000>; - no-map; - }; - - flash_memory: region@5c000000 { - no-map; - reg = <0x5C000000 0x02000000>; /* 32MB */ - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; - }; - - power { - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1debug_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - spi-max-frequency = <50000000>; - label = "pnor"; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default - - &pinctrl_vgahs_default &pinctrl_vgavs_default - &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; - - rtc@68 { - compatible = "dallas,ds3231"; - reg = <0x68>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - tmp423@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; -}; - -&i2c3 { - status = "okay"; - - occ-hwmon@50 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x50>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -&gpio { - pin_func_mode0 { - gpio-hog; - gpios = ; - output-low; - line-name = "func_mode0"; - }; - - pin_func_mode1 { - gpio-hog; - gpios = ; - output-low; - line-name = "func_mode1"; - }; - - pin_func_mode2 { - gpio-hog; - gpios = ; - output-low; - line-name = "func_mode2"; - }; - - pin_gpio_a0 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_FAN_RESERVED_N"; - }; - - pin_gpio_a1 { - gpio-hog; - gpios = ; - output-high; - line-name = "APSS_WDT_N"; - }; - - pin_gpio_b1 { - gpio-hog; - gpios = ; - output-high; - line-name = "APSS_BOOT_MODE"; - }; - - pin_gpio_b2 { - gpio-hog; - gpios = ; - output-high; - line-name = "APSS_RESET_N"; - }; - - pin_gpio_b7 { - gpio-hog; - gpios = ; - output-high; - line-name = "SPIVID_STBY_RESET_N"; - }; - - pin_gpio_d1 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_POWER_UP"; - }; - - pin_gpio_f1 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_BATTERY_TEST"; - }; - - pin_gpio_f4 { - gpio-hog; - gpios = ; - input; - line-name = "AST_HW_FAULT_N"; - }; - - pin_gpio_f5 { - gpio-hog; - gpios = ; - input; - line-name = "AST_SYS_FAULT_N"; - }; - - pin_gpio_f7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_FULL_SPEED_N"; - }; - - pin_gpio_g3 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_FAN_ERROR_N"; - }; - - pin_gpio_g4 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_WDT_RST1_P"; - }; - - pin_gpio_g5 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_WDT_RST2_P"; - }; - - pin_gpio_h0 { - gpio-hog; - gpios = ; - input; - line-name = "PE_SLOT_TEST_EN_N"; - }; - - pin_gpio_h1 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_RTCRST_N"; - }; - - pin_gpio_h2 { - gpio-hog; - gpios = ; - output-high; - line-name = "SYS_PWROK_BMC"; - }; - - pin_gpio_h7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_TPM_INT_N"; - }; -}; - -&fsi { - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - fsi_hub0: hub@3400 { - compatible = "ibm,fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - no-scan-on-init; - }; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts deleted file mode 100644 index 893e621ecab1..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Romulus BMC"; - compatible = "ibm,romulus-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - coldfire_memory: codefire_memory@9ef00000 { - reg = <0x9ef00000 0x00100000>; - no-map; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - fault { - gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - }; - - power { - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - id-button { - label = "id-button"; - gpios = <&gpio ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - /* PCIe slot 1 (x8) */ - status = "okay"; -}; - -&i2c7 { - /* PCIe slot 2 (x16) */ - status = "okay"; -}; - -&i2c8 { - /* PCIe slot 3 (x16) */ - status = "okay"; -}; - -&i2c9 { - /* PCIe slot 4 (x16) */ - status = "okay"; -}; - -&i2c10 { - /* PCIe slot 5 (x8) */ - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&i2c12 { - status = "okay"; - - w83773g@4c { - compatible = "nuvoton,w83773g"; - reg = <0x4c>; - }; -}; - -&gpio { - gpio-line-names = - /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","power-button","","","","", - /*J0-J7*/ "","","checkstop","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","led-fault","", - "led-identify","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","id-button", - /*R0-R7*/ "","","fsi-trans","","","led-power","","", - /*S0-S7*/ "","","","","","","","seq_cont", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; - - nic_func_mode0 { - gpio-hog; - gpios = ; - output-low; - }; - nic_func_mode1 { - gpio-hog; - gpios = ; - output-low; - }; - seq_cont { - gpio-hog; - gpios = ; - output-low; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@4 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@5 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; - - fan@6 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e>; - }; -}; - -&ibt { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts deleted file mode 100644 index bbf864f84d37..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ /dev/null @@ -1,978 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Swift BMC"; - compatible = "ibm,swift-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-oppanel-presence { - label = "oppanel-presence"; - gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-opencapi-riser-presence { - label = "opencapi-riser-presence"; - gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-scm0-presence { - label = "scm0-presence"; - gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-scm1-presence { - label = "scm1-presence"; - gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - event-cpu0vrm-presence { - label = "cpu0vrm-presence"; - gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - - event-cpu1vrm-presence { - label = "cpu1vrm-presence"; - gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 8 GPIO_ACTIVE_LOW>; - linux,code = <8>; - }; - - event-fanboost-presence { - label = "fanboost-presence"; - gpios = <&pca0 9 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - }; - - leds { - compatible = "gpio-leds"; - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 3 GPIO_ACTIVE_LOW>; - }; - - fanboost { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - }; - - front-fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca1 2 GPIO_ACTIVE_LOW>; - }; - - front-power { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca1 3 GPIO_ACTIVE_LOW>; - }; - - front-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca1 0 GPIO_ACTIVE_LOW>; - }; - - rear-fault { - gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; - }; - - rear-id { - gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon-dps310 { - compatible = "iio-hwmon"; - io-channels = <&dps 0>; - }; - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <100000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x7F80000>; - label = "obmc-ubi"; - }; - }; - }; - - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <100000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x7F80000>; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - use-ncsi; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&i2c2 { - status = "okay"; - - /* MUX -> - * Samtec 1 - * Samtec 2 - */ -}; - -&i2c3 { - status = "okay"; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@4 { - compatible = "pmbus-fan"; - reg = <4>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - }; - - pca0: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps2"; - reg = <0x68>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - power-supply@69 { - compatible = "ibm,cffps2"; - reg = <0x69>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c7 { - status = "okay"; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - si7021a20@20 { - compatible = "si,si7021a20"; - reg = <0x20>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca1: pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; -}; - -&i2c8 { - status = "okay"; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", - "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", - "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", - "P9_SCM0_PRES", "P9_SCM1_PRES", - "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", - "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", - "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N", - "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c9 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - pca2: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - }; - - gpio@1 { - reg = <1>; - }; - - gpio@2 { - reg = <2>; - }; - - gpio@3 { - reg = <3>; - }; - - gpio@4 { - reg = <4>; - }; - - gpio@5 { - reg = <5>; - }; - - gpio@6 { - reg = <6>; - }; - - gpio@7 { - reg = <7>; - }; - - gpio@8 { - reg = <8>; - }; - - gpio@9 { - reg = <9>; - }; - - gpio@10 { - reg = <10>; - }; - - gpio@11 { - reg = <11>; - }; - - gpio@12 { - reg = <12>; - }; - - gpio@13 { - reg = <13>; - }; - - gpio@14 { - reg = <14>; - }; - - gpio@15 { - reg = <15>; - }; - }; -}; - -&i2c10 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - pca3: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - }; - - gpio@1 { - reg = <1>; - }; - - gpio@2 { - reg = <2>; - }; - - gpio@3 { - reg = <3>; - }; - - gpio@4 { - reg = <4>; - }; - - gpio@5 { - reg = <5>; - }; - - gpio@6 { - reg = <6>; - }; - - gpio@7 { - reg = <7>; - }; - - gpio@8 { - reg = <8>; - }; - - gpio@9 { - reg = <9>; - }; - - gpio@10 { - reg = <10>; - }; - - gpio@11 { - reg = <11>; - }; - - gpio@12 { - reg = <12>; - }; - - gpio@13 { - reg = <13>; - }; - - gpio@14 { - reg = <14>; - }; - - gpio@15 { - reg = <15>; - }; - }; -}; - -&i2c11 { - /* MUX - * -> PCIe Slot 0 - * -> PCIe Slot 1 - * -> PCIe Slot 2 - * -> PCIe Slot 3 - */ - status = "okay"; -}; - -&i2c12 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; -}; - -&i2c13 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts deleted file mode 100644 index 3f6010ef2b86..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ /dev/null @@ -1,887 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include -#include - -/ { - model = "Tacoma"; - compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@b8000000 { - no-map; - reg = <0xb8000000 0x4000000>; /* 64M */ - }; - - ramoops@bc000000 { - compatible = "ramoops"; - reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ - record-size = <0x8000>; - console-size = <0x8000>; - pmsg-size = <0x8000>; - max-reason = <3>; /* KMSG_DUMP_EMERG */ - }; - - vga_memory: region@bf000000 { - no-map; - compatible = "shared-dma-pool"; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-ps0-presence { - label = "ps0-presence"; - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps1-presence { - label = "ps1-presence"; - gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - }; - - iio-hwmon-dps310 { - compatible = "iio-hwmon"; - io-channels = <&dps 0>; - }; - - iio-hwmon-bmp280 { - compatible = "iio-hwmon"; - io-channels = <&bmp 1>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "fsi-mux","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","presence-ps0","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "led-rear-power","led-rear-id","","usb-power","","","","", - /*P0-P7*/ "","","","","","bmc-tpm-reset","","", - /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","",""; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; - clk-phase-mmc-hs200 = <36>, <270>; -}; - -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; - fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam0_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam0_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam0_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam0_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam0_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam0_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam0_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam0_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam1_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam1_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam1_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam1_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam1_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam1_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam1_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam1_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam1_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -/ { - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c102 = &cfam0_i2c2; - i2c103 = &cfam0_i2c3; - i2c104 = &cfam0_i2c4; - i2c105 = &cfam0_i2c5; - i2c106 = &cfam0_i2c6; - i2c107 = &cfam0_i2c7; - i2c108 = &cfam0_i2c8; - i2c109 = &cfam0_i2c9; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c200 = &cfam1_i2c0; - i2c201 = &cfam1_i2c1; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c204 = &cfam1_i2c4; - i2c205 = &cfam1_i2c5; - i2c206 = &cfam1_i2c6; - i2c207 = &cfam1_i2c7; - i2c208 = &cfam1_i2c8; - i2c209 = &cfam1_i2c9; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c212 = &cfam1_i2c12; - i2c213 = &cfam1_i2c13; - i2c214 = &cfam1_i2c14; - }; - -}; - -&i2c0 { - multi-master; - status = "okay"; - - ibm-panel@62 { - compatible = "ibm,op-panel"; - reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; - }; -}; - -&i2c1 { - status = "okay"; - - tpm: tpm@2e { - compatible = "tcg,tpm-tis-i2c"; - reg = <0x2e>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - bmp: bmp280@77 { - compatible = "bosch,bmp280"; - reg = <0x77>; - #io-channel-cells = <1>; - }; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - pca0: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps1"; - reg = <0x69>; - }; -}; - -&i2c4 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - -&i2c5 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", - "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", - "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", - "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", - "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", - "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", - "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", - "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&uart1 { - status = "okay"; - // Workaround for A0 - compatible = "snps,dw-apb-uart"; -}; - -&uart5 { - // Workaround for A0 - compatible = "snps,dw-apb-uart"; -}; - -&vuart1 { - status = "okay"; -}; - -&vuart2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - status = "okay"; -}; - -&pinctrl { - /* Hog these as no driver is probed for the entire LPC block */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpc_default>, - <&pinctrl_lsirq_default>; -}; - -&xdma { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8 0xcac>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts deleted file mode 100644 index 8a7fb55ab489..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2019 YADRO -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Vesnin BMC"; - compatible = "yadro,vesnin-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@5f000000 { - no-map; - reg = <0x5f000000 0x01000000>; /* 16MB */ - }; - flash_memory: region@5c000000 { - no-map; - reg = <0x5c000000 0x02000000>; /* 32M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; - }; - power_red { - gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; - }; - - power_green { - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - }; - - id_blue { - gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; - }; - - alarm_red { - gpios = <&gpio ASPEED_GPIO(N, 6) GPIO_ACTIVE_LOW>; - }; - - alarm_yel { - gpios = <&gpio ASPEED_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-checkstop { - label = "checkstop"; - linux,code = <74>; - gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; - }; - - event-identify { - label = "identify"; - linux,code = <152>; - gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt"; - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1debug_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - }; -}; - -&mac0 { - status = "okay"; - use-ncsi; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -&ibt { - status = "okay"; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&i2c1 { - status = "okay"; - - tmp75@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - occ-hwmon@50 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x50>; - }; -}; - -&i2c5 { - status = "okay"; - - occ-hwmon@51 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x51>; - }; -}; - -&i2c6 { - status = "okay"; - - w83795g@2f { - compatible = "nuvoton,w83795g"; - reg = <0x2f>; - }; -}; - -&i2c7 { - status = "okay"; - - occ-hwmon@56 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x56>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - occ-hwmon@57 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x57>; - }; -}; - -&i2c12 { - status = "okay"; - - rtc@68 { - compatible = "maxim,ds3231"; - reg = <0x68>; - }; -}; - -&i2c13 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; - cd-inverted; - disable-wp; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts deleted file mode 100644 index a20a532fc280..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ /dev/null @@ -1,704 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Witherspoon BMC"; - compatible = "ibm,witherspoon-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - vga_memory: region@9f000000 { - no-map; - compatible = "shared-dma-pool"; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32MM */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 3 GPIO_ACTIVE_LOW>; - }; - - front-fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 13 GPIO_ACTIVE_LOW>; - }; - - front-power { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 14 GPIO_ACTIVE_LOW>; - }; - - front-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 15 GPIO_ACTIVE_LOW>; - }; - - rear-fault { - gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; - }; - - rear-id { - gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; - }; - - rear-power { - gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; - }; - - power-button { - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon-dps310 { - compatible = "iio-hwmon"; - io-channels = <&dps 0>; - }; - - iio-hwmon-bmp280 { - compatible = "iio-hwmon"; - io-channels = <&bmp 1>; - }; - -}; - -&gpio { - gpio-line-names = - /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", - /*B0-B7*/ "","","","","","air-water","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "fsi-enable","","","","","","","", - /*E0-E7*/ "fsi-data","","","","","","","", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","checkstop","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power", - "led-rear-id","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","presence-ps0", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","fsi-trans","","","power-button","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "fsi-clock","","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "obmc-ubi"; - }; - }; - }; - - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&i2c2 { - status = "okay"; - - /* MUX -> - * Samtec 1 - * Samtec 2 - */ -}; - -&i2c3 { - status = "okay"; - - bmp: bmp280@77 { - compatible = "bosch,bmp280"; - reg = <0x77>; - #io-channel-cells = <1>; - }; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - pca0: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps1"; - reg = <0x69>; - }; -}; - -&i2c4 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - - -&i2c5 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - -&i2c9 { - status = "okay"; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; -}; - -&i2c10 { - /* MUX - * -> PCIe Slot 3 - * -> PCIe Slot 4 - */ - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", - "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", - "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", - "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", - "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", - "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", - "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", - "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&xdma { - status = "okay"; - memory-region = <&vga_memory>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts deleted file mode 100644 index 0cb7b20ff3ab..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ /dev/null @@ -1,578 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Zaius BMC"; - compatible = "ingrasys,zaius-bmc", "aspeed,ast2500"; - - aliases { - i2c15 = &i2cpcie0; - i2c16 = &i2cpcie1; - i2c17 = &i2cpcie2; - i2c19 = &i2cpcie3; - i2c20 = &i2cpcie4; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - }; - - onewire0 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - }; - - onewire1 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - }; - - onewire2 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - onewire3 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-pcie-e2b-present{ - label = "pcie-e2b-present"; - gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - sys_boot_status { - label = "System boot status"; - gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>; - }; - - attention { - label = "Attention"; - gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; - }; - - plt_fault { - label = "Platform fault"; - gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>; - }; - - hdd_fault { - label = "Onboard drive fault"; - gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 13>, <&adc 14>, <&adc 15>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2cs0_default - &pinctrl_spi2cs1_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default>; - - flash@0 { - status = "okay"; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; - - /* Power sequencer UCD90160 PMBUS @64h - * FRU AT24C64D @50h - * RTC PCF8523 @68h - * Clock buffer 9DBL04 @6dh - */ -}; - -&i2c1 { - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2cpcie0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - i2cpcie1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2cpcie2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - i2ctpm: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - /* MUX1 PCA9546A @71h - * PCIe 0 - * PCIe 1 - * PCIe 2 - * TPM header - */ -}; - -&i2c2 { - status = "disabled"; - - /* OCP Mezz Connector A (OOB SMBUS) */ -}; - -&i2c3 { - status = "disabled"; - - /* OCP Mezz Connector A (PCIe slot SMBUS) */ -}; - -&i2c4 { - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2cpcie3: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - i2cpcie4: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - - /* MUX1 PCA9546A @71h - * PCIe 3 - * PCIe 4 - */ -}; - - -&i2c5 { - status = "disabled"; - - /* CPU0 PRM 0.7V */ - /* CPU0 PRM 1.2V CH03 */ - /* CPU0 PRM 0.8V */ - /* CPU0 PRM 1.2V CH47 */ -}; - -&i2c6 { - status = "disabled"; - - /* CPU1 PRM 0.7V */ - /* CPU1 PRM 1.2V CH03 */ - /* CPU1 PRM 0.8V */ - /* CPU1 PRM 1.2V CH47 */ -}; - -&i2c7 { - status = "okay"; - - pca9541a@70 { - compatible = "nxp,pca9541"; - reg = <0x70>; - - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - hotswap@54 { - compatible = "ti,lm5066i"; - reg = <0x54>; - }; - }; - - }; - - vrm@64 { - compatible = "isil,isl68137"; - reg = <0x64>; - }; - - vrm@40 { - compatible = "isil,isl68137"; - reg = <0x40>; - }; - - vrm@60 { - compatible = "isil,isl68137"; - reg = <0x60>; - }; - - vrm@43 { - compatible = "infineon,ir38064"; - reg = <0x43>; - }; - - vrm@41 { - compatible = "isil,isl68137"; - reg = <0x41>; - }; - - /* Master selector PCA9541A @70h (other master: CPU0) - * LM5066I PMBUS @10h - */ - - /* - * Brick will be one of these types/addresses. Depending - * on the board SKU only one is actually present and will successfully - * instantiate while the others will fail the probe operation. - * These are the PVT (and presumably beyond) addresses: - * 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah - * 12V Quarter Brick DC/DC Converter Q54SH12050 @30h - */ - power-brick@6a { - compatible = "delta,dps800"; - reg = <0x6a>; - }; - power-brick@30 { - compatible = "delta,dps800"; - reg = <0x30>; - }; - - /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ - /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ - /* CPU0 VR ISL68137 0.8V PMBUS @60h */ - /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ - /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ - /* Master selector PCA9541A @70h (other master: CPU0) - * LM5066I PMBUS @10h - */ -}; - -&i2c8 { - status = "okay"; - - vrm@64 { - compatible = "isil,isl68137"; - reg = <0x64>; - }; - - vrm@40 { - compatible = "isil,isl68137"; - reg = <0x40>; - }; - - vrm@41 { - compatible = "isil,isl68137"; - reg = <0x41>; - }; - - vrm@42 { - compatible = "infineon,ir38064"; - reg = <0x42>; - }; - - vrm@60 { - compatible = "isil,isl68137"; - reg = <0x60>; - }; - - /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ - /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ - /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ - /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ - /* CPU1 VR ISL68137 0.8V PMBUS @60h */ -}; - - -&i2c9 { - status = "disabled"; - - /* Fan board */ -}; - -&i2c10 { - status = "disabled"; -}; - -&i2c11 { - status = "disabled"; - - /* GPU sideband */ -}; - -&i2c12 { - status = "disabled"; -}; - -&i2c13 { - status = "disabled"; - - /* MUX PI3USB102 - * CPU0 debug - * CPU1 debug - */ -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; - - pinctrl_gpioh_unbiased: gpioi_unbiased { - pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7"; - bias-disable; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioh_unbiased>; - - gpio-line-names = - /*A0-A7*/ "","cfam-reset","","","","","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention", - "led-fault", - /*E0-E7*/ "","","","","","","","presence-pcie-e2b", - /*F0-F7*/ "","","","","","","","checkstop", - /*G0-G7*/ "fsi-clock","fsi-data","","","","","","", - /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","", - /*I0-I7*/ "","","","power-button","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","", - /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","", - "","fsi-mux","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","led-hdd-fault","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; - - line_iso_u146_en { - gpio-hog; - gpios = ; - output-high; - }; - - ncsi_mux_en_n { - gpio-hog; - gpios = ; - output-low; - }; - - line_bmc_i2c2_sw_rst_n { - gpio-hog; - gpios = ; - output-high; - }; - - line_bmc_i2c5_sw_rst_n { - gpio-hog; - gpios = ; - output-high; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; -}; - -&ibt { - status = "okay"; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts deleted file mode 100644 index a5e64ccc2b3a..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ /dev/null @@ -1,167 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017 Facebook Inc. -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Portwell Neptune BMC"; - compatible = "portwell,neptune-bmc", "aspeed,ast2500"; - aliases { - serial0 = &uart1; - serial4 = &uart5; - }; - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - postcode0 { - label = "BMC_UP"; - gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - postcode1 { - label = "BMC_HB"; - gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - postcode2 { - label = "FAULT"; - gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - // postcode3-7 are GPIOH3-H7 - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart1 { - // Host Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart5 { - // BMC Console - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default - &pinctrl_mdio1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii2_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, - <&syscon ASPEED_CLK_MAC2RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&i2c1 { - status = "okay"; - // To PCIe slot SMBUS -}; - -&i2c2 { - status = "okay"; - // To LAN I210 -}; - -&i2c3 { - status = "okay"; - // SMBus to COMe AB -}; - -&i2c4 { - status = "okay"; - // I2C to COMe AB -}; - -&i2c5 { - status = "okay"; -// USB Debug card - pca9555@27 { - compatible = "nxp,pca9555"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c6 { - status = "okay"; - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; -}; - -&i2c8 { - status = "okay"; - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts deleted file mode 100644 index 259ef3f54c5c..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. - -/dts-v1/; - -#include "aspeed-g6.dtsi" - -/ { - model = "Qualcomm DC-SCM V1 BMC"; - compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&mdio3 { - status = "okay"; - - ethphy3: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mac2 { - status = "okay"; - - /* Bootloader sets up the MAC to insert delay */ - phy-mode = "rgmii"; - phy-handle = <ðphy3>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii3_default>; -}; - -&mac3 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - - use-ncsi; -}; - -&rtc { - status = "okay"; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <133000000>; -#include "openbmc-flash-layout-64.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <133000000>; -#include "openbmc-flash-layout-64-alt.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bios"; - spi-max-frequency = <133000000>; - }; -}; - -&gpio0 { - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","", - /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3", - "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3", - "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&gpio1 { - gpio-line-names = - /*A0-A7*/ "GPI_1_BMC_1V8","","","","","", - "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8", - /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8", - "SCMFPGA_SPARE_GPIO5_1V8","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","", - "","TPM2_PIRQ_N","TPM2_RST_N","", - /*E0-E7*/ "","","","","","","",""; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&i2c14 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts deleted file mode 100644 index 9605e53f5bbf..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ /dev/null @@ -1,518 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Quanta Q71L BMC"; - compatible = "quanta,q71l-bmc", "aspeed,ast2400"; - - aliases { - i2c14 = &i2c_pcie2; - i2c15 = &i2c_pcie3; - i2c16 = &i2c_pcie6; - i2c17 = &i2c_pcie7; - i2c18 = &i2c_pcie1; - i2c19 = &i2c_pcie4; - i2c20 = &i2c_pcie5; - i2c21 = &i2c_pcie8; - i2c22 = &i2c_pcie9; - i2c23 = &i2c_pcie10; - i2c24 = &i2c_ssd1; - i2c25 = &i2c_ssd2; - i2c26 = &i2c_psu4; - i2c27 = &i2c_psu1; - i2c28 = &i2c_psu3; - i2c29 = &i2c_psu2; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@40000000 { - reg = <0x40000000 0x8000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@47800000 { - no-map; - reg = <0x47800000 0x00800000>; /* 8MB */ - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; - }; - - power { - gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 11>; - }; - - i2c1mux: i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */ - i2c-parent = <&i2c1>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default - &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; -}; - -&p2a { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&ibt { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&uart1 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - /* temp2 inlet */ - tmp75@4c { - compatible = "ti,tmp75"; - reg = <0x4c>; - }; - - /* temp3 */ - tmp75@4e { - compatible = "ti,tmp75"; - reg = <0x4e>; - }; - - /* temp1 */ - tmp75@4f { - compatible = "ti,tmp75"; - reg = <0x4f>; - }; - - /* Baseboard FRU */ - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; - - /* FP FRU */ - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; -}; - -&i2c2 { - status = "okay"; - - /* 0: PCIe Slot 2, - * Slot 3, - * Slot 6, - * Slot 7 - */ - i2c-switch@74 { - compatible = "nxp,pca9546"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; /* may use mux@77 next. */ - - i2c_pcie2: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_pcie3: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_pcie6: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_pcie7: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - /* 0: PCIe Slot 1, - * Slot 4, - * Slot 5, - * Slot 8, - * Slot 9, - * Slot 10, - * SSD 1, - * SSD 2 - */ - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; /* may use mux@74 next. */ - - i2c_pcie1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_pcie4: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_pcie5: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_pcie8: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c_pcie9: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c_pcie10: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c_ssd1: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c_ssd2: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - status = "okay"; - - /* BIOS FRU */ - eeprom@56 { - compatible = "atmel,24c64"; - reg = <0x56>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - /* 0: PSU4 - * PSU1 - * PSU3 - * PSU2 - */ - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_psu4: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - psu@59 { - compatible = "pmbus"; - reg = <0x59>; - }; - }; - - i2c_psu1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - }; - - i2c_psu3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - }; - - i2c_psu2: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - psu@59 { - compatible = "pmbus"; - reg = <0x59>; - }; - }; - }; - - /* PDB FRU */ - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; -}; - -&i2c8 { - status = "okay"; - - /* BMC FRU */ - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&vuart { - status = "okay"; -}; - -&wdt2 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; -}; - -&i2c1mux { - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - /* Memory Riser 1 FRU */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* Memory Riser 2 FRU */ - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* Memory Riser 3 FRU */ - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; - - /* Memory Riser 4 FRU */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* Memory Riser 5 FRU */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* Memory Riser 6 FRU */ - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* Memory Riser 7 FRU */ - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; - - /* Memory Riser 8 FRU */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts deleted file mode 100644 index 46cbba6305b8..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts +++ /dev/null @@ -1,610 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2022 Quanta Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include - -/ { - model = "Quanta S6Q BMC"; - compatible = "quanta,s6q-bmc", "aspeed,ast2600"; - - aliases { - // bus 0 - i2c20 = &SMB_HOST_DB2000_3V3AUX_SCL; - i2c21 = &U12_PCA9546_CH1; - i2c22 = &SMB_HOST_DB800_B_SCL; - i2c23 = &SMB_HOST_DB800_C_SCL; - - // bus 1 - i2c24 = &SMB_M2_P0_1V8AUX_SCL; - i2c25 = &SMB_M2_P1_1V8AUX_SCL; - i2c26 = &SMB_CPU_PIROM_3V3AUX_SCL; - i2c27 = &SMB_TEMP_3V3AUX_SCL; - i2c28 = &SMB_IPMB_3V3AUX_SSDSB_SCL; - i2c29 = &SMB_IPMB_3V3AUX_SCL; - i2c31 = &SMB_FB_SCL; - - // bus 1 - Fan board - i2c32 = &SMB_IOEXP_SCL; - i2c33 = &SMB_PROGRAM_SCL; - i2c34 = &SMB_FB_SCL_CH2; - i2c35 = &SMB_FAN_SENSE_SCL; - - // bus 6 - i2c36 = &U197_PCA9546_CH0; - i2c37 = &U197_PCA9546_CH1; - i2c38 = &U197_PCA9546_CH2; - i2c39 = &U197_PCA9546_CH3; - - //bus 7 - i2c40 = &SMB_OCP_SFF_3V3AUX_SCL; //OCP1 - i2c41 = &SMB_OCP_LFF_3V3AUX_SCL; //OCP2 - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, - <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; - }; - - leds { - compatible = "gpio-leds"; - - BMC_HEARTBEAT_N { - label = "BMC_HEARTBEAT_N"; - gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - BMC_LED_STATUS_AMBER_N { - label = "BMC_LED_STATUS_AMBER_N"; - gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - FM_ID_LED_N { - label = "FM_ID_LED_N"; - gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&gpio0 { - gpio-line-names = - /*A0 - A7*/ "", "", "", "", "", "", "", "", - /*B0 - B7*/ "", "", "", "", "", "", "", "", - /*C0 - C7*/ "", "", "", "", "", "", "", "", - /*D0 - D7*/ "", "", "", "", "", "", "", "", - /*E0 - E7*/ "", "", "", "", "", "", "", "", - /*F0 - F7*/ "PLTRST_N", "", "PWR_DEBUG_N", "", "", "", "", "", - /*G0 - G7*/ "", "", "", "", "", "", "", "", - /*H0 - H7*/ "", "", "", "", "", "", "", "", - /*I0 - I7*/ "", "", "", "", "", "", "", "", - /*J0 - J7*/ "", "", "", "", "", "", "", "", - /*K0 - K7*/ "", "", "", "", "", "", "", "", - /*L0 - L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "", - /*M0 - M7*/ "", "", "", "PWRGD_SYS_PWROK", "", "PRDY_N", "", "", - /*N0 - N7*/ "", "", "", "", "", "", "", "", - /*O0 - O7*/ "", "", "", "", "", "", "", "", - /*P0 - P7*/ "SYS_BMC_PWRBTN_R_N", "SYS_PWRBTN_N", "FM_MB_RST_BTN", "RST_BMC_RSTBTN_OUT_N", "", "", "", "", - /*Q0 - Q7*/ "", "", "", "", "", "", "", "", - /*R0 - R7*/ "", "", "", "", "", "", "", "", - /*S0 - S7*/ "", "", "", "FP_ID_BTN_SCM_N", "", "", "", "", - /*T0 - T7*/ "", "", "", "", "", "", "", "", - /*U0 - U7*/ "", "", "", "", "", "", "", "", - /*V0 - V7*/ "", "", "", "", "", "SMI", "", "", - /*W0 - W7*/ "", "", "", "", "", "", "", "", - /*X0 - X7*/ "", "", "", "", "", "", "", "", - /*Y0 - Y7*/ "", "", "", "", "", "", "", "", - /*Z0 - Z7*/ "FM_BMC_READY_N", "", "", "", "", "", "", "", - /*AA0 - AA7*/ "", "", "", "", "", "", "", "", - /*AB0 - AB7*/ "", "", "", "", "", "", "", "", - /*AC0 - AC7*/ "", "", "", "", "", "", "", ""; -}; - -&sgpiom0 { - status = "okay"; - ngpios = <128>; - bus-frequency = <48000>; - gpio-line-names = - /* SGPIO input lines */ - /*IOA0-IOA7*/ "","", "SIO_POWER_GOOD","OA1", "XDP_PRST_N","", "","", "FM_SLPS3_PLD_N","", "FM_SLPS4_PLD_N","", "FM_BIOS_POST_CMPLT_BMC_N","", "FM_ADR_TRIGGER_N","OA7", - /*IOB0-IOB7*/ "FM_ADR_COMPLETE","", "FM_PMBUS_ALERT_B_EN","", "PSU0_PRESENT_N","", "PSU1_PRESENT_N","", "PSU0_VIN_BUF_GOOD","", "PSU01_VIN_BUF_GOOD","", "PWRGD_PS0_PWROK_R","", "PWRGD_PS1_PWROK_R","", - /*IOC0-IOC7*/ "PWRGD_PS_PWROK_PLD_R","", "CHASSIS_INTRUSION","", "BMC_MFG_MODE","", "FM_BMC_EN_DET_R","", "FM_ME_BT_DONE","", "CPU1_PRESENCE","", "CPU2_PRESENCE","", "IRQ_PSYS_CRIT_N","", - /*IOD0-IOD7*/ "","", "CPU1_THERMTRIP","", "CPU2_THERMTRIP","", "CPU1_MEM_THERM_EVENT","", "CPU2_MEM_THERM_EVENT","", "CPU1_VRHOT","", "CPU2_VRHOT","", "","", - /*IOE0-IOE7*/ "","", "CPU1_MEM_VRHOT","", "CPU2_MEM_VRHOT","", "","", "PCH_BMC_THERMTRIP","", "","", "","", "","", - /*IOF0-IOF7*/ "CPU_ERR0","", "CPU_ERR1","", "CPU_ERR2","", "","", "","", "CPU_CATERR","", "","", "","", - /*IOG0-IOG7*/ "","", "","", "","", "","", "","", "","", "","", "","", - /*IOH0-IOH7*/ "","", "FP_ID_BTN_R1_N","", "FP_RST_BTN_N","", "","", "","", "FP_PWR_BTN_PLD_N_R","", "","", "","", - /*IOI0-IOI7*/ "","", "","", "","", "","", "","", "","", "","", "","", - /*IOJ0-IOJ7*/ "","", "","", "","", "","", "","", "","", "","", "","", - /*IOK0-IOK7*/ "","", "","", "","", "","", "","", "","", "","", "","", - /*IOL0-IOL7*/ "","", "","", "","", "","", "","", "","", "","", "","", - /*IOM0-IOM7*/ "","", "","", "","", "","", "","", "","", "","", "","", - /*ION0-ION7*/ "","BMC_SW_HEARTBEAT_N_R", "","FP_LED_FAULT_N", "","FP_ID_LED_N", "","FM_BMC_RSTBTN_OUT_N", "","FM_THERMTRIP_DLY_LVC1_R_N", "","", "","RST_PCA9548_SENSOR_PLD_N", "","USB_OC1_REAR_N", - /*IOO0-IOO7*/ "","IRQ_TPM_SPI_N", "","", "","IRQ_PCH_SCI_WHEA_R_N", "","IRQ_BMC_PCH_NMI_R", "","H_CPU_NMI_LVC1_R_N", "","", "","", "","FM_JTAG_BMC_PLD_MUX_SEL", - /*IOP0-IOP7*/ "IP0","OP0", "","", "","", "","", "","", "","", "","", "IP7","OP7"; -}; - -&adc0 { - vref = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; -}; - -&adc1 { - vref = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&mdio2 { - status = "okay"; - - ethphy2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mac2 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii3_default>; -}; - -&mac3 { - status = "okay"; - - phy-mode = "rmii"; - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default - &pinctrl_spi2cs2_default>; - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi2:0"; - spi-max-frequency = <50000000>; - }; -}; - -&kcs1 { - status = "okay"; - aspeed,lpc-io-reg = <0xCA0>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xCA8>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xCA2>; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - non-removable; - bus-width = <4>; - max-frequency = <100000000>; -}; - -&vhub { - status = "okay"; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&uart_routing { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - U34_PWR_ADC@48 { - compatible = "ti,ads7830"; - reg = <0x48>; - }; - - U35_PWR_ADC@4b { - compatible = "ti,ads7830"; - reg = <0x4b>; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - SMB_HOST_DB2000_3V3AUX_SCL: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - U12_PCA9546_CH1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - SMB_HOST_DB800_B_SCL: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - SMB_HOST_DB800_C_SCL: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - i2c-switch@59 { - compatible = "nxp,pca9848"; - reg = <0x59>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - SMB_M2_P0_1V8AUX_SCL: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - SMB_M2_P1_1V8AUX_SCL: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - SMB_CPU_PIROM_3V3AUX_SCL: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - SMB_TEMP_3V3AUX_SCL: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - U163_tmp75@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - U114_tmp75@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - }; - - SMB_IPMB_3V3AUX_SSDSB_SCL: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - U4_tmp75@4c { - compatible = "ti,tmp75"; - reg = <0x4c>; - }; - U73_tmp75@4d { - compatible = "ti,tmp75"; - reg = <0x4d>; - }; - }; - - SMB_IPMB_3V3AUX_SCL: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - U190_fru@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - }; - - SMB_FB_SCL: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - i2c-switch@77 { - compatible = "nxp,pca9546"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - SMB_IOEXP_SCL: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - SMB_PROGRAM_SCL: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - SMB_FB_SCL_CH2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - SMB_FAN_SENSE_SCL: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - Current_Meter_U2@45 { - compatible = "ti,ina219"; - reg = <0x45>; - shunt-resistor = <1000>; /* = 1 mOhm */ - }; - - Current_Meter_U3@44 { - compatible = "ti,ina219"; - reg = <0x44>; - shunt-resistor = <1000>; /* = 1 mOhm */ - }; - - TEMP_sensor_U2@4b { - compatible = "ti,tmp75"; - reg = <0x4b>; - }; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - bus-frequency = <400000>; - - ipmb@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; -}; - -&i2c3 { - status = "okay"; - - /* MB FRU (U173) @ 0xA2 */ - mb_fru: mb_fru@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - - /* FP_U1 Inlet */ - FP_U1_tmp75@4a { - compatible = "ti,tmp75"; - reg = <0x4a>; - }; - - FP_U4_fru@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - U197_PCA9546_CH0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - U197_PCA9546_CH1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - cpu0_pvccin@60 { - compatible = "isil,raa229004"; - reg = <0x60>; - }; - - cpu0_pvccinfaon@61 { - compatible = "isil,isl69260"; - reg = <0x61>; - }; - - cpu0_pvccd_hv@63 { - compatible = "isil,isl69260"; - reg = <0x63>; - }; - }; - - U197_PCA9546_CH2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - cpu1_pvccin@72 { - compatible = "isil,raa229004"; - reg = <0x72>; - }; - - cpu1_pvccinfaon@74 { - compatible = "isil,isl69260"; - reg = <0x74>; - }; - - cpu1_pvccd_hv@76 { - compatible = "isil,isl69260"; - reg = <0x76>; - }; - }; - - U197_PCA9546_CH3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c7 { - status = "okay"; - - i2c-switch@75 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - SMB_OCP_SFF_3V3AUX_SCL: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - SMB_OCP_LFF_3V3AUX_SCL: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c14 { - status = "okay"; - - /* SCM FRU (U19) @ 0xA2 */ - scm_fru: scm_fru@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - - scm_tmp75_u4@4a { - compatible = "ti,tmp75"; - reg = <0x4a>; - }; -}; - -&i2c15 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts deleted file mode 100644 index 50f3c6a5c0c8..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 Super Micro Computer, Inc - -/dts-v1/; - -#include "aspeed-g5.dtsi" - -/ { - model = "X11SPI BMC"; - compatible = "supermicro,x11spi-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@7f000000 { - no-map; - reg = <0x7f000000 0x01000000>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; - -}; - -&gpio { - status = "okay"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts deleted file mode 100644 index aff27c1d4b06..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ /dev/null @@ -1,528 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Tyan S7106 BMC"; - compatible = "tyan,s7106-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - p2a_memory: region@987f0000 { - no-map; - reg = <0x987f0000 0x00010000>; /* 64KB */ - }; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; /* 16M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - identify { - gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; - }; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - label = "bmc"; - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - /* RS-232 connector on header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart3 { - /* Alternative to vuart to internally connect (route) to uart1 - * when vuart cannot be used due to BIOS limitations. - */ - status = "okay"; -}; - -&uart4 { - /* Alternative to vuart to internally connect (route) to the - * external port usually used by uart1 when vuart cannot be - * used due to BIOS limitations. - */ - status = "okay"; -}; - -&uart5 { - /* BMC "debug" (console) UART; connected to RS-232 connector - * on header; selectable via jumpers as alternative to uart2 - */ - status = "okay"; -}; - -&uart_routing { - status = "okay"; -}; - -&vuart { - status = "okay"; - - /* We enable the VUART here, but leave it in a state that does - * not interfere with the SuperIO. The goal is to have both the - * VUART and the SuperIO available and decide at runtime whether - * the VUART should actually be used. For that reason, configure - * an "invalid" IO address and an IRQ that is not used by the - * BMC. - */ - - aspeed,lpc-io-reg = <0xffff>; - aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&p2a { - status = "okay"; - memory-region = <&p2a_memory>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&adc { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default>; - - /* CPU fan #0 */ - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - /* CPU fan #1 */ - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - /* PWM group for chassis fans #1, #2, #3 and #4 */ - fan@2 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - /* PWM group for chassis fans #5 and #6 */ - fan@6 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; -}; - -&i2c0 { - status = "okay"; - - /* Hardware monitor with temperature sensors */ - nct7802@28 { - compatible = "nuvoton,nct7802"; - reg = <0x28>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { /* LTD */ - reg = <0>; - }; - - channel@1 { /* RTD1 */ - reg = <1>; - sensor-type = "temperature"; - temperature-mode = "thermistor"; - }; - - channel@2 { /* RTD2 */ - reg = <2>; - sensor-type = "temperature"; - temperature-mode = "thermistor"; - }; - - channel@3 { /* RTD3 */ - reg = <3>; - sensor-type = "temperature"; - }; - }; - - /* Also connected to: - * - IPMB pin header - * - CPU #0 memory error LED @ 0x3A - * - CPU #1 memory error LED @ 0x3C - */ -}; - -&i2c1 { - /* Directly connected to PCH SMBUS #0 */ - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - /* BMC EEPROM, incl. mainboard FRU */ - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - /* Also connected to: - * - fan header - * - mini-SAS HD connector - * - SSATA SGPIO - * - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low) - * to PCH SMBUS #3 - */ -}; - -&i2c3 { - status = "okay"; - - /* PSU1 FRU @ 0xA0 */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* PSU2 FRU @ 0xA2 */ - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* PSU1 @ 0xB0 */ - power-supply@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - /* PSU2 @ 0xB2 */ - power-supply@59 { - compatible = "pmbus"; - reg = <0x59>; - }; - - /* Also connected to: - * - PCH SMBUS #1 - */ -}; - -&i2c4 { - status = "okay"; - - /* Connected to: - * - PCH SMBUS #2 - */ - - /* Connected via switch to: - * - CPU #0 channels ABC VDDQ @ 0x80 - * - CPU #0 channels DEF VDDQ @ 0x81 - * - CPU #1 channels ABC VDDQ @ 0x82 - * - CPU #1 channels DEF VDDQ @ 0x83 - * - CPU #0 VCCIO & VMCP @ 0x52 - * - CPU #1 VCCIO & VMCP @ 0x53 - * - CPU #0 VCCIN @ 0xC0 - * - CPU #0 VSA @ 0xC2 - * - CPU #1 VCCIN @ 0xC4 - * - CPU #1 VSA @ 0xC6 - * - J110 - */ -}; - -&i2c5 { - status = "okay"; - - /* Connected via switch (PCH_BMC_SMB_SW_P) to: - * - mainboard FRU @ 0xAE - * - XDP connector - * - ME debug header - * - clock buffer @ 0xD8 - * - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH) - * - PCH SMBUS - */ -}; - -&i2c6 { - status = "okay"; - - /* Connected via switch (BMC_PE_SMB_EN_1_N) to - * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to: - * - 0,0: PCIE slot 1, SMB #1 - * - 0,1: PCIE slot 1, SMB #2 - * - 1,0: PCIE slot 2, SMB #1 - * - 1,1: PCIE slot 2, SMB #2 - */ - - /* Connected via switch (BMC_PE_SMB_EN_2_N) to - * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to: - * - 0,0: OCP0 (A) SMB - * - 0,1: OCP0 (C) SMB - * - 1,0: OCP1 (A) SMB - * - 1,1: NC - */ -}; - -&i2c7 { - status = "okay"; - - /* Connected to: - * - PCH SMBUS #4 - */ -}; - -&i2c8 { - status = "okay"; - - /* Not connected */ -}; - -&mac0 { - status = "okay"; - use-ncsi; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&ibt { - status = "okay"; -}; - -&kcs1 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -/* We're following the GPIO naming as defined at - * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. - * - * Notes on led-identify and id-button: - * - A physical button is connected to id-button which - * triggers the clock on a D flip-flop. The /Q output of the - * flip-flop drives its D input. - * - The flip-flop's Q output drives led-identify which is - * connected to LEDs. - * - With that, every button press toggles the LED between on and off. - * - * Notes on power-, reset- and nmi- button and control: - * - The -button signals can be used to monitor physical buttons. - * - The -control signals can be used to actuate the specific - * operation. - * - In hardware, the -button signals are connected to the -control - * signals through drivers with the -control signals being - * protected through diodes. - */ -&gpio { - status = "okay"; - gpio-line-names = - /*A0*/ "", - /*A1*/ "", - /*A2*/ "led-identify", /* in/out: BMC_IDLED_ON_N */ - /*A3*/ "", - /*A4*/ "", - /*A5*/ "", - /*A6*/ "", - /*A7*/ "", - /*B0-B7*/ "","","","","","","","", - /*C0*/ "", - /*C1*/ "", - /*C2*/ "", - /*C3*/ "", - /*C4*/ "id-button", /* in/out: BMC_IDBTN_IN_OUT_N */ - /*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */ - /*C6*/ "", - /*C7*/ "", - /*D0*/ "", - /*D1*/ "", - /*D2*/ "power-chassis-good", /* in: SYS_PWROK_BUF */ - /*D3*/ "platform-reset", /* in: SYS_PLTRST_N */ - /*D4*/ "", - /*D5*/ "", - /*D6*/ "", - /*D7*/ "", - /*E0*/ "power-button", /* in: BMC_PWBTN_IN_N */ - /*E1*/ "power-chassis-control", /* out: BMC_PWRBTN_OUT_N */ - /*E2*/ "reset-button", /* in: BMC_RSTBTN_IN_N */ - /*E3*/ "reset-control", /* out: BMC_RSTBTN_OUT_N */ - /*E4*/ "nmi-button", /* in: BMC_NMIBTN_IN_N */ - /*E5*/ "nmi-control", /* out: BMC_NMIBTN_OUT_N */ - /*E6*/ "", - /*E7*/ "led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */ - /*F0*/ "", - /*F1*/ "clear-cmos-control", /* out: BMC_CLR_CMOS_N */ - /*F2*/ "", - /*F3*/ "", - /*F4*/ "led-fault", /* out: AST_HW_FAULT_N */ - /*F5*/ "", - /*F6*/ "", - /*F7*/ "", - /*G0*/ "BMC_PE_SMB_EN_1_N", /* out */ - /*G1*/ "BMC_PE_SMB_EN_2_N", /* out */ - /*G2*/ "", - /*G3*/ "", - /*G4*/ "", - /*G5*/ "", - /*G6*/ "", - /*G7*/ "", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0*/ "", - /*Q1*/ "", - /*Q2*/ "", - /*Q3*/ "", - /*Q4*/ "BMC_PE_SMB_SW_BIT0", /* out */ - /*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */ - /*Q6*/ "", - /*Q7*/ "", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0*/ "", - /*AA1*/ "", - /*AA2*/ "", - /*AA3*/ "BMC_SMB3_PCH_IE_SML3_EN", /* out */ - /*AA4*/ "", - /*AA5*/ "", - /*AA6*/ "", - /*AA7*/ "", - /*AB0-AB7*/ "","","","","","","",""; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts deleted file mode 100644 index f6c4549c0ac4..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts +++ /dev/null @@ -1,471 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Tyan S8036 BMC"; - compatible = "tyan,s8036-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - p2a_memory: region@987f0000 { - no-map; - reg = <0x987f0000 0x00010000>; /* 64KB */ - }; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; /* 16M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - identify { - gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; - }; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - label = "bmc"; - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - /* RS-232 connector on header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart3 { - /* Alternative to vuart to internally connect (route) to uart1 - * when vuart cannot be used due to BIOS limitations. - */ - status = "okay"; -}; - -&uart4 { - /* Alternative to vuart to internally connect (route) to the - * external port usually used by uart1 when vuart cannot be - * used due to BIOS limitations. - */ - status = "okay"; -}; - -&uart5 { - /* BMC "debug" (console) UART; connected to RS-232 connector - * on header; selectable via jumpers as alternative to uart2 - */ - status = "okay"; -}; - -&uart_routing { - status = "okay"; -}; - -&vuart { - status = "okay"; - - /* We enable the VUART here, but leave it in a state that does - * not interfere with the SuperIO. The goal is to have both the - * VUART and the SuperIO available and decide at runtime whether - * the VUART should actually be used. For that reason, configure - * an "invalid" IO address and an IRQ that is not used by the - * BMC. - */ - aspeed,lpc-io-reg = <0xffff>; - aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&p2a { - status = "okay"; - memory-region = <&p2a_memory>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&adc { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default>; - - /* CPU fan */ - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - /* PWM group for chassis fans #1, #2, #3 and #4 */ - fan@2 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - /* PWM group for chassis fans #5 and #6 */ - fan@6 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; -}; - -&i2c0 { - /* Directly connected to Sideband-Temperature Sensor Interface (APML) */ - status = "okay"; -}; - -&i2c1 { - /* Directly connected to IPMB HDR. */ - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - /* BMC EEPROM, incl. mainboard FRU */ - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - /* Also connected to: - * - BCM5720 - * - FPGA - * - FAN HDR - * - FPIO HDR - */ -}; - -&i2c3 { - status = "okay"; - - /* PSU1 FRU @ 0xA0 */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* PSU2 FRU @ 0xA2 */ - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* PSU1 @ 0xB0 */ - power-supply@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - /* PSU2 @ 0xB2 */ - power-supply@59 { - compatible = "pmbus"; - reg = <0x59>; - }; - -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; - /* Hardware monitor with temperature sensors */ - nct7802@28 { - compatible = "nuvoton,nct7802"; - reg = <0x28>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { /* LTD */ - reg = <0>; - status = "okay"; - }; - - channel@1 { /* RTD1 */ - reg = <1>; - status = "okay"; - sensor-type = "temperature"; - temperature-mode = "thermistor"; - }; - - channel@2 { /* RTD2 */ - reg = <2>; - status = "okay"; - sensor-type = "temperature"; - temperature-mode = "thermistor"; - }; - - channel@3 { /* RTD3 */ - reg = <3>; - status = "okay"; - sensor-type = "temperature"; - }; - }; - - /* Also connected to: - * - PCA9544 - * - CLK BUFF - * - OCP FRU - */ -}; - -&i2c6 { - status = "okay"; - /* Connected to: - * - PCA9548 @0xE0 - * - PCA9548 @0xE2 - * - PCA9544 @0xE4 - */ -}; - -&i2c7 { - status = "okay"; - - /* Connected to: - * - PCH SMBUS #4 - */ -}; - -&i2c8 { - status = "okay"; - - /* Not connected */ -}; - -&mac0 { - status = "okay"; - use-ncsi; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&ibt { - status = "okay"; -}; - -&kcs1 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; -}; - -/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -/* We're following the GPIO naming as defined at - * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. - * - * Notes on led-identify and id-button: - * - A physical button is connected to id-button which - * triggers the clock on a D flip-flop. The /Q output of the - * flip-flop drives its D input. - * - The flip-flop's Q output drives led-identify which is - * connected to LEDs. - * - With that, every button press toggles the LED between on and off. - * - * Notes on power-, reset- and nmi- button and control: - * - The -button signals can be used to monitor physical buttons. - * - The -control signals can be used to actuate the specific - * operation. - * - In hardware, the -button signals are connected to the -control - * signals through drivers with the -control signals being - * protected through diodes. - */ -&gpio { - status = "okay"; - gpio-line-names = - /*A0*/ "", - /*A1*/ "", - /*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */ - /*A3*/ "", - /*A4*/ "", - /*A5*/ "", - /*A6*/ "", - /*A7*/ "", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0*/ "", - /*D1*/ "", - /*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/ - /*D3*/ "platform-reset", /* in: RESET_LED_L */ - /*D4*/ "", - /*D5*/ "", - /*D6*/ "", - /*D7*/ "", - /*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */ - /*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */ - /*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/ - /*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */ - /*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */ - /*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */ - /*E6*/ "TSI_RESERT", - /*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */ - /*F0*/ "", - /*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */ - /*F2*/ "", - /*F3*/ "", - /*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */ - /*F5*/ "BMC_SYS_FAULT_LED_L", - /*F6*/ "BMC_ASSERT_BIOS_WP_L", - /*F7*/ "", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0*/ "", - /*Q1*/ "", - /*Q2*/ "", - /*Q3*/ "", - /*Q4*/ "", - /*Q5*/ "", - /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */ - /*Q7*/ "", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z2*/ "","","", - /*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */ - /*Z4-Z7*/ "","","","", - /*AA0*/ "", - /*AA1*/ "", - /*AA2*/ "", - /*AA3*/ "", - /*AA4*/ "", - /*AA5*/ "", - /*AA6*/ "", - /*AA7*/ "BMC_ASSERT_BMC_READY", - /*AB0*/ "BMC_SPD_SEL", - /*AB1-AB7*/ "","","","","","",""; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts deleted file mode 100644 index 7ab29129d1e4..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright (c) 2022 Ufispace Co., Ltd. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include - -/ { - model = "Ufispace NCPLite BMC"; - compatible = "ufispace,ncplite-bmc", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8 earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, - <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - fan-status-int-l { - label = "fan-status-int-l"; - gpios = <&gpio0 ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - allpwr-good { - label = "allpwr-good"; - gpios = <&gpio0 ASPEED_GPIO(V, 4) GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - - psu0-alert-n { - label = "psu0-alert-n"; - gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - psu1-alert-n { - label = "psu1-alert-n"; - gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - int-thermal-alert { - label = "int-thermal-alert"; - gpios = <&gpio0 ASPEED_GPIO(P, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - cpu-caterr-l { - label = "cpu-caterr-l"; - gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - cpu-thermtrip-l { - label = "cpu-thermtrip-l"; - gpios = <&gpio0 ASPEED_GPIO(V, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - psu0-presence-l { - label = "psu0-presence-l"; - gpios = <&gpio0 ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - psu1-presence-l { - label = "psu1-presence-l"; - gpios = <&gpio0 ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - psu0-power-ok { - label = "psu0-power-ok"; - gpios = <&gpio0 ASPEED_GPIO(M, 4) GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - - psu1-power-ok { - label = "psu1-power-ok"; - gpios = <&gpio0 ASPEED_GPIO(M, 5) GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&fan_ioexp 2 GPIO_ACTIVE_LOW>; - linux,code = <2>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&fan_ioexp 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan2-presence { - label = "fan2-presence"; - gpios = <&fan_ioexp 10 GPIO_ACTIVE_LOW>; - linux,code = <10>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&fan_ioexp 14 GPIO_ACTIVE_LOW>; - linux,code = <14>; - }; - }; -}; - -&mac2 { - status = "okay"; - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64-alt.dtsi" - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; -}; - -&lpc_reset { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&uart_routing { - status = "okay"; -}; - -&wdt1 { - status = "okay"; -}; - -&wdt2 { - status = "okay"; -}; - -&peci0 { - status = "okay"; -}; - -&udc { - status = "okay"; -}; - -&adc0 { - vref = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; -}; - -&adc1 { - vref = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - lm75@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - lm86@4c { - compatible = "national,lm86"; - reg = <0x4c>; - }; -}; - -&i2c2 { - status = "okay"; - - lm75@4f { - cpmpatible = "national,lm75"; - reg = <0x4f>; - }; - - fan_ioexp: pca9535@20 { - compatible = "nxp,pca9535"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "","","presence-fan0","", - "","","presence-fan1","", - "","","presence-fan2","", - "","","presence-fan3",""; - }; -}; - -&i2c3 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&i2c4 { - status = "okay"; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <1>; - }; -}; - -&i2c5 { - status = "okay"; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <1>; - }; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; - - lm75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; -}; - -&gpio0 { - status = "okay"; - - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "CPU_PWRGD","","","power-button","host0-ready","","presence-ps0","presence-ps1", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","reset-button","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","power-chassis-good","","",""; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts deleted file mode 100644 index 24319267d550..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (C) 2021 YADRO -/dts-v1/; - -#include "aspeed-bmc-vegman.dtsi" - -/ { - model = "YADRO VEGMAN N110 BMC"; - compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", - /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", - /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", - /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", - /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", - /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", - /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", - /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&sgpio { - ngpios = <80>; - bus-frequency = <2000000>; - status = "okay"; - /* SGPIO lines. even: input, odd: output */ - gpio-line-names = - /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", - /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", - /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", - /*D0-D7*/ "","","","","","","","","","","","","","","","", - /*E0-E7*/ "","","","","","","","","","","","","","","","", - /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", - /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", - /*H0-H7*/ "","","","","","","","","","","","","","","","", - /*I0-I7*/ "","","","","","","","","","","","","","","","", - /*J0-J7*/ "","","","","","","","","","","","","","","",""; -}; - -&i2c11 { - /* SMB_BMC_MGMT_LVC3 */ - gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", - /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; - }; - gpio@27 { - compatible = "nxp,pca9698"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", - /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", - /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", - /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", - /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; - }; -}; - -&i2c13 { - /* SMB_PCIE2_STBY_LVC3 */ - mux-expa@73 { - compatible = "nxp,pca9545"; - reg = <0x73>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; - mux-sata@71 { - compatible = "nxp,pca9543"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; -}; - -&i2c2 { - /* SMB_PCIE_STBY_LVC3 */ - mux-expb@71 { - compatible = "nxp,pca9545"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; - }; - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; - }; - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; - }; - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; - }; - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; - }; - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts deleted file mode 100644 index ebbb68b55559..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (C) 2021 YADRO -/dts-v1/; - -#include "aspeed-bmc-vegman.dtsi" - -/ { - model = "YADRO VEGMAN Rx20 BMC"; - compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500"; - - leds { - compatible = "gpio-leds"; - - temp_alarm { - label = "temp:red:status"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>; - }; - - temp_ok { - label = "temp:green:status"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; - }; - - psu_fault { - label = "psu:red:status"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>; - }; - - psu_ok { - label = "psu:green:status"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G", - /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","", - /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","", - /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","", - /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", - /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", - /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", - /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&sgpio { - ngpios = <80>; - bus-frequency = <2000000>; - status = "okay"; - /* SGPIO lines. even: input, odd: output */ - gpio-line-names = - /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", - /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", - /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", - /*D0-D7*/ "","","","","","","","","","","","","","","","", - /*E0-E7*/ "","","","","","","","","","","","","","","","", - /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", - /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", - /*H0-H7*/ "","","","","","","","","","","","","","","","", - /*I0-I7*/ "","","","","","","","","","","","","","","","", - /*J0-J7*/ "","","","","","","","","","","","","","","",""; -}; - -&i2c11 { - /* SMB_BMC_MGMT_LVC3 */ - gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N", - /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", ""; - }; - gpio@23 { - compatible = "nxp,pcal9535"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "", - /*IO1.0-1.7*/ "", "", "", "", "", "", "", ""; - }; - gpio@27 { - compatible = "nxp,pca9698"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", - /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", - /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", - /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", - /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1"; - }; - gpio@39 { - compatible = "nxp,pca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", ""; - }; -}; - -&i2c13 { - /* SMB_PCIE2_STBY_LVC3 */ - mux-expa@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - rsra-mux@72 { - compatible = "nxp,pca9548"; - reg = <0x72>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - at24@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - size = <8192>; - address-width = <16>; - }; - }; - }; - }; - }; - mux-sata@71 { - compatible = "nxp,pca9543"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; -}; - -&i2c2 { - /* SMB_PCIE_STBY_LVC3 */ - mux-expb@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - rsrb-mux@72 { - compatible = "nxp,pca9548"; - reg = <0x72>; - #address-cells = <1>; - #size-cells = <0>; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - at24@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - size = <8192>; - address-width = <16>; - }; - }; - }; - at24@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - size = <8192>; - address-width = <16>; - }; - }; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>; - }; - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; - }; - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; - }; - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; - }; - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; - }; - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>; - }; - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts deleted file mode 100644 index e36ee4704994..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (C) 2021 YADRO -/dts-v1/; - -#include "aspeed-bmc-vegman.dtsi" - -/ { - model = "YADRO VEGMAN Sx20 BMC"; - compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; -}; - -&gpio { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", - /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", - /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", - /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", - /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", - /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", - /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", - /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", - /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&sgpio { - ngpios = <80>; - bus-frequency = <2000000>; - status = "okay"; - /* SGPIO lines. even: input, odd: output */ - gpio-line-names = - /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", - /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", - /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", - /*D0-D7*/ "","","","","","","","","","","","","","","","", - /*E0-E7*/ "","","","","","","","","","","","","","","","", - /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", - /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", - /*H0-H7*/ "","","","","","","","","","","","","","","","", - /*I0-I7*/ "","","","","","","","","","","","","","","","", - /*J0-J7*/ "","","","","","","","","","","","","","","",""; -}; - -&i2c11 { - /* SMB_BMC_MGMT_LVC3 */ - gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", - /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; - }; - gpio@27 { - compatible = "nxp,pca9698"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", - /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", - /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", - /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", - /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; - }; -}; - -&i2c13 { - /* SMB_PCIE2_STBY_LVC3 */ - mux-expa@73 { - compatible = "nxp,pca9545"; - reg = <0x73>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; - mux-sata@71 { - compatible = "nxp,pca9543"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; -}; - -&i2c2 { - /* SMB_PCIE_STBY_LVC3 */ - mux-expb@71 { - compatible = "nxp,pca9545"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi deleted file mode 100644 index 1a5b25b2ea29..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi +++ /dev/null @@ -1,311 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (C) 2021 YADRO - -#include "aspeed-g5.dtsi" -#include - -/ { - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - ramoops@9eff0000{ - compatible = "ramoops"; - reg = <0x9eff0000 0x10000>; - record-size = <0x2000>; - console-size = <0x2000>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; - - leds { - compatible = "gpio-leds"; - - identify { - label = "platform:blue:indicator"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; - }; - - status_amber { - label = "platform:red:status"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; - }; - - status_green { - label = "platform:green:status"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; - }; - - power_fault { - label = "platform:red:power"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; - }; - - power_ok { - label = "platform:green:power"; - default-state = "off"; - gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>; - }; - }; - - beeper { - compatible = "pwm-beeper"; - pwms = <&timer 5 1000000 0>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; -#include "openbmc-flash-layout-64.dtsi" - }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default - &pinctrl_spi2cs0_default>; - flash@0 { - status = "okay"; - label = "bios"; - m25p,fast-read; - }; -}; - -&mac0 { - status = "okay"; - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; - - phy-mode = "rgmii"; - phy-handle = <&phy>; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@1 { - /* KSZ9131 */ - compatible = "ethernet-phy-id0022.1640"; - reg = <1>; - - micrel,led-mode = <0>; - }; - }; -}; - -&vhub { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; - disable-wp; -}; - -&timer { - fttmr010,pwm-outputs = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_timer5_default>; - #pwm-cells = <3>; - status = "okay"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&kcs3 { - aspeed,lpc-io-reg = <0xCA2>; - status = "okay"; -}; - -&kcs4 { - aspeed,lpc-io-reg = <0xCA4>; - status = "okay"; -}; - -&lpc_snoop { - snoop-ports = <0x80>; - status = "okay"; -}; - -&uart_routing { - status = "okay"; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; -}; - -&i2c0 { - /* SMB_IPMB_STBY_LVC3 */ - multi-master; - status = "okay"; -}; - -&i2c1 { - /* SMB_CHASSENSOR_STBY_LVC3 */ - status = "okay"; -}; - -&i2c2 { - /* SMB_PCIE_STBY_LVC3 */ - status = "okay"; -}; - -&i2c3 { - /* SMB_HOST_STBY_LVC3 */ - multi-master; - status = "okay"; -}; - -&i2c4 { - /* BMC_PMBUS2_STBY */ - status = "okay"; -}; - -&i2c5 { - /* SMB_SMLINK0_STBY_LVC3 */ - bus-frequency = <1000000>; - multi-master; - status = "okay"; -}; - -&i2c6 { - /* SMB_TEMPSENSOR_STBY_LVC3 */ - multi-master; - status = "okay"; -}; - -&i2c7 { - /* SMB_SM_PMB1_SML1_STBY_LVC3 */ - multi-master; - status = "okay"; -}; - -&i2c9 { - /* SMB_BMC_ETH3_LVC3 */ - status = "okay"; -}; - -&i2c10 { - /* SMB_BMC_ETH2_LVC3 */ - status = "okay"; -}; - -&i2c11 { - /* SMB_BMC_MGMT_LVC3 */ - status = "okay"; - - at24@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - size = <8192>; - address-width = <16>; - }; -}; - -&i2c12 { - /* SMB_BMC_FAULT_EXP_LVC3 */ - status = "okay"; -}; - -&i2c13 { - /* SMB_PCIE2_STBY_LVC3 */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi deleted file mode 100644 index 530491ae5eb2..000000000000 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ /dev/null @@ -1,1453 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2400"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &vuart; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fmc: spi@1e620000 { - reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - interrupts = <19>; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <2>; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <2>; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <2>; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@3 { - reg = < 3 >; - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <2>; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@4 { - reg = < 4 >; - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <2>; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - spi: spi@1e630000 { - reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - valid-sources = <0xffffffff 0x0007ffff>; - reg = <0x1e6c0080 0x80>; - }; - - cvic: copro-interrupt-controller@1e6c2000 { - compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; - valid-sources = <0x7fffffff>; - reg = <0x1e6c2000 0x80>; - }; - - mac0: ethernet@1e660000 { - compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - interrupts = <2>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; - status = "disabled"; - }; - - mac1: ethernet@1e680000 { - compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; - reg = <0x1e680000 0x180>; - interrupts = <3>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; - status = "disabled"; - }; - - ehci0: usb@1e6a1000 { - compatible = "aspeed,ast2400-ehci", "generic-ehci"; - reg = <0x1e6a1000 0x100>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2h_default>; - status = "disabled"; - }; - - uhci: usb@1e6b0000 { - compatible = "aspeed,ast2400-uhci", "generic-uhci"; - reg = <0x1e6b0000 0x100>; - interrupts = <14>; - #ports = <3>; - clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; - status = "disabled"; - /* - * No default pinmux, it will follow EHCI, use an explicit pinmux - * override if you don't enable EHCI - */ - }; - - vhub: usb-vhub@1e6a0000 { - compatible = "aspeed,ast2400-usb-vhub"; - reg = <0x1e6a0000 0x300>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - aspeed,vhub-downstream-ports = <5>; - aspeed,vhub-generic-endpoints = <15>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2d_default>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e6e2000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - p2a: p2a-control@2c { - reg = <0x2c 0x4>; - compatible = "aspeed,ast2400-p2a-ctrl"; - status = "disabled"; - }; - - silicon-id@7c { - compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; - reg = <0x7c 0x4>; - }; - - pinctrl: pinctrl@80 { - reg = <0x80 0x18>, <0xa0 0x10>; - compatible = "aspeed,ast2400-pinctrl"; - }; - }; - - rng: hwrng@1e6e2078 { - compatible = "timeriomem_rng"; - reg = <0x1e6e2078 0x4>; - period = <1>; - quality = <100>; - }; - - adc: adc@1e6e9000 { - compatible = "aspeed,ast2400-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_ADC>; - #io-channel-cells = <1>; - status = "disabled"; - }; - - sram: sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x8000>; // 32K - }; - - video: video@1e700000 { - compatible = "aspeed,ast2400-video-engine"; - reg = <0x1e700000 0x1000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, - <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - interrupts = <7>; - status = "disabled"; - }; - - sdmmc: sd-controller@1e740000 { - compatible = "aspeed,ast2400-sd-controller"; - reg = <0x1e740000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e740000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; - status = "disabled"; - - sdhci0: sdhci@100 { - compatible = "aspeed,ast2400-sdhci"; - reg = <0x100 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - - sdhci1: sdhci@200 { - compatible = "aspeed,ast2400-sdhci"; - reg = <0x200 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - }; - - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2400-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - clocks = <&syscon ASPEED_CLK_APB>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&syscon ASPEED_CLK_APB>; - clock-names = "PCLK"; - }; - - rtc: rtc@1e781000 { - compatible = "aspeed,ast2400-rtc"; - reg = <0x1e781000 0x18>; - status = "disabled"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x20>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; - no-loopback-test; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x20>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; - no-loopback-test; - status = "disabled"; - }; - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785000 0x1c>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - wdt2: watchdog@1e785020 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785020 0x1c>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - pwm_tacho: pwm-tacho-controller@1e786000 { - compatible = "aspeed,ast2400-pwm-tacho"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_24M>; - resets = <&syscon ASPEED_RESET_PWM>; - status = "disabled"; - }; - - vuart: serial@1e787000 { - compatible = "aspeed,ast2400-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_APB>; - no-loopback-test; - status = "disabled"; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2400-lpc-ctrl"; - reg = <0x80 0x10>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_snoop: lpc-snoop@90 { - compatible = "aspeed,ast2400-lpc-snoop"; - reg = <0x90 0x8>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lhc: lhc@a0 { - compatible = "aspeed,ast2400-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; - }; - - lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2400-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; - }; - - ibt: ibt@140 { - compatible = "aspeed,ast2400-ibt-bmc"; - reg = <0x140 0x18>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - uart_routing: uart-routing@9c { - compatible = "aspeed,ast2400-uart-routing"; - reg = <0x9c 0x4>; - status = "disabled"; - }; - }; - - peci0: peci-controller@1e78b000 { - compatible = "aspeed,ast2400-peci"; - reg = <0x1e78b000 0x60>; - interrupts = <15>; - clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; - resets = <&syscon ASPEED_RESET_PECI>; - cmd-timeout-ms = <1000>; - clock-frequency = <1000000>; - status = "disabled"; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x20>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; - no-loopback-test; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x20>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; - no-loopback-test; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x20>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; - no-loopback-test; - status = "disabled"; - }; - - i2c: bus@1e78a000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - }; - }; - }; -}; - -&i2c { - i2c_ic: interrupt-controller@0 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; - }; - - i2c0: i2c-bus@40 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x40 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <0>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c1: i2c-bus@80 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x80 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <1>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c2: i2c-bus@c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0xc0 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <2>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x100 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <3>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c-bus@140 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x140 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <4>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c-bus@180 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x180 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <5>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c-bus@1c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x1c0 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <6>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c-bus@300 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x300 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <7>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c-bus@340 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x340 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <8>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c-bus@380 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x380 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <9>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c-bus@3c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x3c0 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <10>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c-bus@400 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x400 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <11>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c-bus@440 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x440 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <12>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c-bus@480 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x480 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <13>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; -}; - -&pinctrl { - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; - - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; - - pinctrl_extrst_default: extrst_default { - function = "EXTRST"; - groups = "EXTRST"; - }; - - pinctrl_flack_default: flack_default { - function = "FLACK"; - groups = "FLACK"; - }; - - pinctrl_flbusy_default: flbusy_default { - function = "FLBUSY"; - groups = "FLBUSY"; - }; - - pinctrl_flwp_default: flwp_default { - function = "FLWP"; - groups = "FLWP"; - }; - - pinctrl_gpid_default: gpid_default { - function = "GPID"; - groups = "GPID"; - }; - - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; - - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; - - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; - - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; - - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; - - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; - - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; - - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; - - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_ndts4_default: ndts4_default { - function = "NDTS4"; - groups = "NDTS4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rom16_default: rom16_default { - function = "ROM16"; - groups = "ROM16"; - }; - - pinctrl_rom8_default: rom8_default { - function = "ROM8"; - groups = "ROM8"; - }; - - pinctrl_romcs1_default: romcs1_default { - function = "ROMCS1"; - groups = "ROMCS1"; - }; - - pinctrl_romcs2_default: romcs2_default { - function = "ROMCS2"; - groups = "ROMCS2"; - }; - - pinctrl_romcs3_default: romcs3_default { - function = "ROMCS3"; - groups = "ROMCS3"; - }; - - pinctrl_romcs4_default: romcs4_default { - function = "ROMCS4"; - groups = "ROMCS4"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_sgpmck_default: sgpmck_default { - function = "SGPMCK"; - groups = "SGPMCK"; - }; - - pinctrl_sgpmi_default: sgpmi_default { - function = "SGPMI"; - groups = "SGPMI"; - }; - - pinctrl_sgpmld_default: sgpmld_default { - function = "SGPMLD"; - groups = "SGPMLD"; - }; - - pinctrl_sgpmo_default: sgpmo_default { - function = "SGPMO"; - groups = "SGPMO"; - }; - - pinctrl_sgpsck_default: sgpsck_default { - function = "SGPSCK"; - groups = "SGPSCK"; - }; - - pinctrl_sgpsi0_default: sgpsi0_default { - function = "SGPSI0"; - groups = "SGPSI0"; - }; - - pinctrl_sgpsi1_default: sgpsi1_default { - function = "SGPSI1"; - groups = "SGPSI1"; - }; - - pinctrl_sgpsld_default: sgpsld_default { - function = "SGPSLD"; - groups = "SGPSLD"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; - - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; - - pinctrl_spics1_default: spics1_default { - function = "SPICS1"; - groups = "SPICS1"; - }; - - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; - - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; - - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; - - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; - - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; - - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; - - pinctrl_usb2h_default: usb2h_default { - function = "USB2H1"; - groups = "USB2H1"; - }; - - pinctrl_usb2d_default: usb2d_default { - function = "USB2D1"; - groups = "USB2D1"; - }; - - pinctrl_vgabios_rom_default: vgabios_rom_default { - function = "VGABIOS_ROM"; - groups = "VGABIOS_ROM"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_vpi18_default: vpi18_default { - function = "VPI18"; - groups = "VPI18"; - }; - - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; - - pinctrl_vpi30_default: vpi30_default { - function = "VPI30"; - groups = "VPI30"; - }; - - pinctrl_vpo12_default: vpo12_default { - function = "VPO12"; - groups = "VPO12"; - }; - - pinctrl_vpo24_default: vpo24_default { - function = "VPO24"; - groups = "VPO24"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi deleted file mode 100644 index 04f98d1dbb97..000000000000 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ /dev/null @@ -1,1661 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2500"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &vuart; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1176jzf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fmc: spi@1e620000 { - reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2500-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - interrupts = <19>; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - spi1: spi@1e630000 { - reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2500-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - spi2: spi@1e631000 { - reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2500-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - valid-sources = <0xfefff7ff 0x0807ffff>; - reg = <0x1e6c0080 0x80>; - }; - - cvic: copro-interrupt-controller@1e6c2000 { - compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; - valid-sources = <0xffffffff>; - copro-sw-interrupts = <1>; - reg = <0x1e6c2000 0x80>; - }; - - mac0: ethernet@1e660000 { - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - interrupts = <2>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; - status = "disabled"; - }; - - mac1: ethernet@1e680000 { - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; - reg = <0x1e680000 0x180>; - interrupts = <3>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; - status = "disabled"; - }; - - ehci0: usb@1e6a1000 { - compatible = "aspeed,ast2500-ehci", "generic-ehci"; - reg = <0x1e6a1000 0x100>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ah_default>; - status = "disabled"; - }; - - ehci1: usb@1e6a3000 { - compatible = "aspeed,ast2500-ehci", "generic-ehci"; - reg = <0x1e6a3000 0x100>; - interrupts = <13>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2bh_default>; - status = "disabled"; - }; - - uhci: usb@1e6b0000 { - compatible = "aspeed,ast2500-uhci", "generic-uhci"; - reg = <0x1e6b0000 0x100>; - interrupts = <14>; - #ports = <2>; - clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; - status = "disabled"; - /* - * No default pinmux, it will follow EHCI, use an explicit pinmux - * override if you don't enable EHCI - */ - }; - - vhub: usb-vhub@1e6a0000 { - compatible = "aspeed,ast2500-usb-vhub"; - reg = <0x1e6a0000 0x300>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - aspeed,vhub-downstream-ports = <5>; - aspeed,vhub-generic-endpoints = <15>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ad_default>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edac: memory-controller@1e6e0000 { - compatible = "aspeed,ast2500-sdram-edac"; - reg = <0x1e6e0000 0x174>; - interrupts = <0>; - status = "disabled"; - }; - - syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e6e2000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - scu_ic: interrupt-controller@18 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2500-scu-ic"; - reg = <0x18 0x4>; - interrupts = <21>; - interrupt-controller; - }; - - p2a: p2a-control@2c { - compatible = "aspeed,ast2500-p2a-ctrl"; - reg = <0x2c 0x4>; - status = "disabled"; - }; - - silicon-id@7c { - compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; - reg = <0x7c 0x4 0x150 0x8>; - }; - - pinctrl: pinctrl@80 { - compatible = "aspeed,ast2500-pinctrl"; - reg = <0x80 0x18>, <0xa0 0x10>; - aspeed,external-nodes = <&gfx>, <&lhc>; - }; - }; - - rng: hwrng@1e6e2078 { - compatible = "timeriomem_rng"; - reg = <0x1e6e2078 0x4>; - period = <1>; - quality = <100>; - }; - - hace: crypto@1e6e3000 { - compatible = "aspeed,ast2500-hace"; - reg = <0x1e6e3000 0x100>; - interrupts = <4>; - clocks = <&syscon ASPEED_CLK_GATE_YCLK>; - resets = <&syscon ASPEED_RESET_HACE>; - }; - - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_CRT1>; - syscon = <&syscon>; - status = "disabled"; - interrupts = <0x19>; - }; - - xdma: xdma@1e6e7000 { - compatible = "aspeed,ast2500-xdma"; - reg = <0x1e6e7000 0x100>; - clocks = <&syscon ASPEED_CLK_GATE_BCLK>; - resets = <&syscon ASPEED_RESET_XDMA>; - interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; - aspeed,pcie-device = "bmc"; - aspeed,scu = <&syscon>; - status = "disabled"; - }; - - adc: adc@1e6e9000 { - compatible = "aspeed,ast2500-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_ADC>; - #io-channel-cells = <1>; - status = "disabled"; - }; - - video: video@1e700000 { - compatible = "aspeed,ast2500-video-engine"; - reg = <0x1e700000 0x1000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, - <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - interrupts = <7>; - status = "disabled"; - }; - - sram: sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; - - sdmmc: sd-controller@1e740000 { - compatible = "aspeed,ast2500-sd-controller"; - reg = <0x1e740000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e740000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; - status = "disabled"; - - sdhci0: sdhci@100 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x100 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - - sdhci1: sdhci@200 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x200 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - }; - - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x200>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 232>; - clocks = <&syscon ASPEED_CLK_APB>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sgpio: sgpio@1e780200 { - #gpio-cells = <2>; - compatible = "aspeed,ast2500-sgpio"; - gpio-controller; - interrupts = <40>; - reg = <0x1e780200 0x0100>; - clocks = <&syscon ASPEED_CLK_APB>; - interrupt-controller; - bus-frequency = <12000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgpm_default>; - status = "disabled"; - }; - - rtc: rtc@1e781000 { - compatible = "aspeed,ast2500-rtc"; - reg = <0x1e781000 0x18>; - status = "disabled"; - }; - - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&syscon ASPEED_CLK_APB>; - clock-names = "PCLK"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x20>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; - no-loopback-test; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x20>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; - no-loopback-test; - status = "disabled"; - }; - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785000 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - wdt2: watchdog@1e785020 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785020 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - wdt3: watchdog@1e785040 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785040 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; - status = "disabled"; - }; - - pwm_tacho: pwm-tacho-controller@1e786000 { - compatible = "aspeed,ast2500-pwm-tacho"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_24M>; - resets = <&syscon ASPEED_RESET_PWM>; - status = "disabled"; - }; - - vuart: serial@1e787000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_APB>; - no-loopback-test; - status = "disabled"; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - kcs1: kcs@24 { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - kcs2: kcs@28 { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - kcs3: kcs@2c { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - kcs4: kcs@114 { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x80 0x10>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_snoop: lpc-snoop@90 { - compatible = "aspeed,ast2500-lpc-snoop"; - reg = <0x90 0x8>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; - }; - - uart_routing: uart-routing@9c { - compatible = "aspeed,ast2500-uart-routing"; - reg = <0x9c 0x4>; - status = "disabled"; - }; - - lhc: lhc@a0 { - compatible = "aspeed,ast2500-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; - }; - - - ibt: ibt@140 { - compatible = "aspeed,ast2500-ibt-bmc"; - reg = <0x140 0x18>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - }; - - peci0: peci-controller@1e78b000 { - compatible = "aspeed,ast2500-peci"; - reg = <0x1e78b000 0x60>; - interrupts = <15>; - clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; - resets = <&syscon ASPEED_RESET_PECI>; - cmd-timeout-ms = <1000>; - clock-frequency = <1000000>; - status = "disabled"; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x20>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; - no-loopback-test; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x20>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; - no-loopback-test; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x20>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; - no-loopback-test; - status = "disabled"; - }; - - i2c: bus@1e78a000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - }; - }; - }; -}; - -&i2c { - i2c_ic: interrupt-controller@0 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2500-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; - }; - - i2c0: i2c-bus@40 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x40 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <0>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c1: i2c-bus@80 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x80 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <1>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c2: i2c-bus@c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0xc0 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <2>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x100 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <3>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c-bus@140 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x140 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <4>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c-bus@180 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x180 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <5>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c-bus@1c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x1c0 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <6>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c-bus@300 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x300 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <7>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c-bus@340 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x340 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <8>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c-bus@380 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x380 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <9>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c-bus@3c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x3c0 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <10>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c-bus@400 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x400 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <11>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c-bus@440 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x440 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <12>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c-bus@480 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x480 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <13>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; -}; - -&pinctrl { - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; - - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; - - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; - - pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; - }; - - pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; - }; - - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; - - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; - - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; - - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; - - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; - - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; - - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; - - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; - - pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; - - pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; - - pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; - - pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; - - pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; - - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; - - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; - - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; - - pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; - - pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; - - pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; - - pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; - - pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; - - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; - - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; - - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; - - pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; - - pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; - - pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; - - pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; - - pinctrl_sgpm_default: sgpm_default { - function = "SGPM"; - groups = "SGPM"; - }; - - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; - - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; - - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; - - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; - - pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; - - pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; - - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; - - pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; - - pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; - - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; - - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; - - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; - - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; - - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; - - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; - - pinctrl_usb2ah_default: usb2ah_default { - function = "USB2AH"; - groups = "USB2AH"; - }; - - pinctrl_usb2ad_default: usb2ad_default { - function = "USB2AD"; - groups = "USB2AD"; - }; - - pinctrl_usb11bhid_default: usb11bhid_default { - function = "USB11BHID"; - groups = "USB11BHID"; - }; - - pinctrl_usb2bh_default: usb2bh_default { - function = "USB2BH"; - groups = "USB2BH"; - }; - - pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; - - pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi deleted file mode 100644 index 7cd4f075e325..000000000000 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ /dev/null @@ -1,1184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. - -&pinctrl { - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; - - pinctrl_espialt_default: espialt_default { - function = "ESPIALT"; - groups = "ESPIALT"; - }; - - pinctrl_fsi1_default: fsi1_default { - function = "FSI1"; - groups = "FSI1"; - }; - - pinctrl_fsi2_default: fsi2_default { - function = "FSI2"; - groups = "FSI2"; - }; - - pinctrl_fwspiabr_default: fwspiabr_default { - function = "FWSPIABR"; - groups = "FWSPIABR"; - }; - - pinctrl_fwspid_default: fwspid_default { - function = "FWSPID"; - groups = "FWSPID"; - }; - - pinctrl_fwqspi_default: fwqspi_default { - function = "FWQSPI"; - groups = "FWQSPI"; - }; - - pinctrl_fwspiwp_default: fwspiwp_default { - function = "FWSPIWP"; - groups = "FWSPIWP"; - }; - - pinctrl_gpit0_default: gpit0_default { - function = "GPIT0"; - groups = "GPIT0"; - }; - - pinctrl_gpit1_default: gpit1_default { - function = "GPIT1"; - groups = "GPIT1"; - }; - - pinctrl_gpit2_default: gpit2_default { - function = "GPIT2"; - groups = "GPIT2"; - }; - - pinctrl_gpit3_default: gpit3_default { - function = "GPIT3"; - groups = "GPIT3"; - }; - - pinctrl_gpit4_default: gpit4_default { - function = "GPIT4"; - groups = "GPIT4"; - }; - - pinctrl_gpit5_default: gpit5_default { - function = "GPIT5"; - groups = "GPIT5"; - }; - - pinctrl_gpit6_default: gpit6_default { - function = "GPIT6"; - groups = "GPIT6"; - }; - - pinctrl_gpit7_default: gpit7_default { - function = "GPIT7"; - groups = "GPIT7"; - }; - - pinctrl_gpiu0_default: gpiu0_default { - function = "GPIU0"; - groups = "GPIU0"; - }; - - pinctrl_gpiu1_default: gpiu1_default { - function = "GPIU1"; - groups = "GPIU1"; - }; - - pinctrl_gpiu2_default: gpiu2_default { - function = "GPIU2"; - groups = "GPIU2"; - }; - - pinctrl_gpiu3_default: gpiu3_default { - function = "GPIU3"; - groups = "GPIU3"; - }; - - pinctrl_gpiu4_default: gpiu4_default { - function = "GPIU4"; - groups = "GPIU4"; - }; - - pinctrl_gpiu5_default: gpiu5_default { - function = "GPIU5"; - groups = "GPIU5"; - }; - - pinctrl_gpiu6_default: gpiu6_default { - function = "GPIU6"; - groups = "GPIU6"; - }; - - pinctrl_gpiu7_default: gpiu7_default { - function = "GPIU7"; - groups = "GPIU7"; - }; - - pinctrl_hvi3c3_default: hvi3c3_default { - function = "I3C3"; - groups = "HVI3C3"; - }; - - pinctrl_hvi3c4_default: hvi3c4_default { - function = "I3C4"; - groups = "HVI3C4"; - }; - - pinctrl_i2c1_default: i2c1_default { - function = "I2C1"; - groups = "I2C1"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c15_default: i2c15_default { - function = "I2C15"; - groups = "I2C15"; - }; - - pinctrl_i2c16_default: i2c16_default { - function = "I2C16"; - groups = "I2C16"; - }; - - pinctrl_i2c2_default: i2c2_default { - function = "I2C2"; - groups = "I2C2"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_i3c3_default: i3c3_default { - function = "I3C3"; - groups = "I3C3"; - }; - - pinctrl_i3c4_default: i3c4_default { - function = "I3C4"; - groups = "I3C4"; - }; - - pinctrl_i3c5_default: i3c5_default { - function = "I3C5"; - groups = "I3C5"; - }; - - pinctrl_i3c6_default: i3c6_default { - function = "I3C6"; - groups = "I3C6"; - }; - - pinctrl_jtagm_default: jtagm_default { - function = "JTAGM"; - groups = "JTAGM"; - }; - - pinctrl_lhpd_default: lhpd_default { - function = "LHPD"; - groups = "LHPD"; - }; - - pinctrl_lhsirq_default: lhsirq_default { - function = "LHSIRQ"; - groups = "LHSIRQ"; - }; - - pinctrl_lpc_default: lpc_default { - function = "LPC"; - groups = "LPC"; - }; - - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; - - pinctrl_maclink1_default: maclink1_default { - function = "MACLINK1"; - groups = "MACLINK1"; - }; - - pinctrl_maclink2_default: maclink2_default { - function = "MACLINK2"; - groups = "MACLINK2"; - }; - - pinctrl_maclink3_default: maclink3_default { - function = "MACLINK3"; - groups = "MACLINK3"; - }; - - pinctrl_maclink4_default: maclink4_default { - function = "MACLINK4"; - groups = "MACLINK4"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_mdio3_default: mdio3_default { - function = "MDIO3"; - groups = "MDIO3"; - }; - - pinctrl_mdio4_default: mdio4_default { - function = "MDIO4"; - groups = "MDIO4"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm10g0_default: pwm10g0_default { - function = "PWM10"; - groups = "PWM10G0"; - }; - - pinctrl_pwm10g1_default: pwm10g1_default { - function = "PWM10"; - groups = "PWM10G1"; - }; - - pinctrl_pwm11g0_default: pwm11g0_default { - function = "PWM11"; - groups = "PWM11G0"; - }; - - pinctrl_pwm11g1_default: pwm11g1_default { - function = "PWM11"; - groups = "PWM11G1"; - }; - - pinctrl_pwm12g0_default: pwm12g0_default { - function = "PWM12"; - groups = "PWM12G0"; - }; - - pinctrl_pwm12g1_default: pwm12g1_default { - function = "PWM12"; - groups = "PWM12G1"; - }; - - pinctrl_pwm13g0_default: pwm13g0_default { - function = "PWM13"; - groups = "PWM13G0"; - }; - - pinctrl_pwm13g1_default: pwm13g1_default { - function = "PWM13"; - groups = "PWM13G1"; - }; - - pinctrl_pwm14g0_default: pwm14g0_default { - function = "PWM14"; - groups = "PWM14G0"; - }; - - pinctrl_pwm14g1_default: pwm14g1_default { - function = "PWM14"; - groups = "PWM14G1"; - }; - - pinctrl_pwm15g0_default: pwm15g0_default { - function = "PWM15"; - groups = "PWM15G0"; - }; - - pinctrl_pwm15g1_default: pwm15g1_default { - function = "PWM15"; - groups = "PWM15G1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_pwm8g0_default: pwm8g0_default { - function = "PWM8"; - groups = "PWM8G0"; - }; - - pinctrl_pwm8g1_default: pwm8g1_default { - function = "PWM8"; - groups = "PWM8G1"; - }; - - pinctrl_pwm9g0_default: pwm9g0_default { - function = "PWM9"; - groups = "PWM9G0"; - }; - - pinctrl_pwm9g1_default: pwm9g1_default { - function = "PWM9"; - groups = "PWM9G1"; - }; - - pinctrl_qspi1_default: qspi1_default { - function = "SPI1"; - groups = "QSPI1"; - }; - - pinctrl_qspi2_default: qspi2_default { - function = "SPI2"; - groups = "QSPI2"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rgmii3_default: rgmii3_default { - function = "RGMII3"; - groups = "RGMII3"; - }; - - pinctrl_rgmii4_default: rgmii4_default { - function = "RGMII4"; - groups = "RGMII4"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rmii3_default: rmii3_default { - function = "RMII3"; - groups = "RMII3"; - }; - - pinctrl_rmii4_default: rmii4_default { - function = "RMII4"; - groups = "RMII4"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt10g0_default: salt10g0_default { - function = "SALT10"; - groups = "SALT10G0"; - }; - - pinctrl_salt10g1_default: salt10g1_default { - function = "SALT10"; - groups = "SALT10G1"; - }; - - pinctrl_salt11g0_default: salt11g0_default { - function = "SALT11"; - groups = "SALT11G0"; - }; - - pinctrl_salt11g1_default: salt11g1_default { - function = "SALT11"; - groups = "SALT11G1"; - }; - - pinctrl_salt12g0_default: salt12g0_default { - function = "SALT12"; - groups = "SALT12G0"; - }; - - pinctrl_salt12g1_default: salt12g1_default { - function = "SALT12"; - groups = "SALT12G1"; - }; - - pinctrl_salt13g0_default: salt13g0_default { - function = "SALT13"; - groups = "SALT13G0"; - }; - - pinctrl_salt13g1_default: salt13g1_default { - function = "SALT13"; - groups = "SALT13G1"; - }; - - pinctrl_salt14g0_default: salt14g0_default { - function = "SALT14"; - groups = "SALT14G0"; - }; - - pinctrl_salt14g1_default: salt14g1_default { - function = "SALT14"; - groups = "SALT14G1"; - }; - - pinctrl_salt15g0_default: salt15g0_default { - function = "SALT15"; - groups = "SALT15G0"; - }; - - pinctrl_salt15g1_default: salt15g1_default { - function = "SALT15"; - groups = "SALT15G1"; - }; - - pinctrl_salt16g0_default: salt16g0_default { - function = "SALT16"; - groups = "SALT16G0"; - }; - - pinctrl_salt16g1_default: salt16g1_default { - function = "SALT16"; - groups = "SALT16G1"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; - - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; - - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; - - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; - - pinctrl_salt9g0_default: salt9g0_default { - function = "SALT9"; - groups = "SALT9G0"; - }; - - pinctrl_salt9g1_default: salt9g1_default { - function = "SALT9"; - groups = "SALT9G1"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_emmc_default: emmc_default { - function = "EMMC"; - groups = "EMMCG4"; - }; - - pinctrl_sgpm1_default: sgpm1_default { - function = "SGPM1"; - groups = "SGPM1"; - }; - - pinctrl_sgpm2_default: sgpm2_default { - function = "SGPM2"; - groups = "SGPM2"; - }; - - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; - - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1abr_default: spi1abr_default { - function = "SPI1ABR"; - groups = "SPI1ABR"; - }; - - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; - - pinctrl_spi1wp_default: spi1wp_default { - function = "SPI1WP"; - groups = "SPI1WP"; - }; - - pinctrl_spi2_default: spi2_default { - function = "SPI2"; - groups = "SPI2"; - }; - - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; - - pinctrl_spi2cs2_default: spi2cs2_default { - function = "SPI2CS2"; - groups = "SPI2CS2"; - }; - - pinctrl_tach0_default: tach0_default { - function = "TACH0"; - groups = "TACH0"; - }; - - pinctrl_tach1_default: tach1_default { - function = "TACH1"; - groups = "TACH1"; - }; - - pinctrl_tach10_default: tach10_default { - function = "TACH10"; - groups = "TACH10"; - }; - - pinctrl_tach11_default: tach11_default { - function = "TACH11"; - groups = "TACH11"; - }; - - pinctrl_tach12_default: tach12_default { - function = "TACH12"; - groups = "TACH12"; - }; - - pinctrl_tach13_default: tach13_default { - function = "TACH13"; - groups = "TACH13"; - }; - - pinctrl_tach14_default: tach14_default { - function = "TACH14"; - groups = "TACH14"; - }; - - pinctrl_tach15_default: tach15_default { - function = "TACH15"; - groups = "TACH15"; - }; - - pinctrl_tach2_default: tach2_default { - function = "TACH2"; - groups = "TACH2"; - }; - - pinctrl_tach3_default: tach3_default { - function = "TACH3"; - groups = "TACH3"; - }; - - pinctrl_tach4_default: tach4_default { - function = "TACH4"; - groups = "TACH4"; - }; - - pinctrl_tach5_default: tach5_default { - function = "TACH5"; - groups = "TACH5"; - }; - - pinctrl_tach6_default: tach6_default { - function = "TACH6"; - groups = "TACH6"; - }; - - pinctrl_tach7_default: tach7_default { - function = "TACH7"; - groups = "TACH7"; - }; - - pinctrl_tach8_default: tach8_default { - function = "TACH8"; - groups = "TACH8"; - }; - - pinctrl_tach9_default: tach9_default { - function = "TACH9"; - groups = "TACH9"; - }; - - pinctrl_thru0_default: thru0_default { - function = "THRU0"; - groups = "THRU0"; - }; - - pinctrl_thru1_default: thru1_default { - function = "THRU1"; - groups = "THRU1"; - }; - - pinctrl_thru2_default: thru2_default { - function = "THRU2"; - groups = "THRU2"; - }; - - pinctrl_thru3_default: thru3_default { - function = "THRU3"; - groups = "THRU3"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart10_default: uart10_default { - function = "UART10"; - groups = "UART10"; - }; - - pinctrl_uart11_default: uart11_default { - function = "UART11"; - groups = "UART11"; - }; - - pinctrl_uart12g0_default: uart12g0_default { - function = "UART12"; - groups = "UART12G0"; - }; - - pinctrl_uart12g1_default: uart12g1_default { - function = "UART12"; - groups = "UART12G1"; - }; - - pinctrl_uart13g0_default: uart13g0_default { - function = "UART13"; - groups = "UART13G0"; - }; - - pinctrl_uart13g1_default: uart13g1_default { - function = "UART13"; - groups = "UART13G1"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_uart7_default: uart7_default { - function = "UART7"; - groups = "UART7"; - }; - - pinctrl_uart8_default: uart8_default { - function = "UART8"; - groups = "UART8"; - }; - - pinctrl_uart9_default: uart9_default { - function = "UART9"; - groups = "UART9"; - }; - - pinctrl_usb2ah_default: usb2ah_default { - function = "USB2AH"; - groups = "USBA"; - }; - - pinctrl_usb2ad_default: usb2ad_default { - function = "USB2AD"; - groups = "USBA"; - }; - - pinctrl_usb2bh_default: usb2bh_default { - function = "USB2BH"; - groups = "USBB"; - }; - - pinctrl_usb2bd_default: usb2bd_default { - function = "USB2BD"; - groups = "USBB"; - }; - - pinctrl_usb11bhid_default: usb11bhid_default { - function = "USB11BHID"; - groups = "USBB"; - }; - - pinctrl_vb_default: vb_default { - function = "VB"; - groups = "VB"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; - - pinctrl_wdtrst3_default: wdtrst3_default { - function = "WDTRST3"; - groups = "WDTRST3"; - }; - - pinctrl_wdtrst4_default: wdtrst4_default { - function = "WDTRST4"; - groups = "WDTRST4"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi deleted file mode 100644 index 172dd748d807..000000000000 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ /dev/null @@ -1,1121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. - -#include -#include -#include - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2600"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &vuart1; - serial6 = &vuart2; - mdio0 = &mdio0; - mdio1 = &mdio1; - mdio2 = &mdio2; - mdio3 = &mdio3; - }; - - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "aspeed,ast2600-smp"; - - cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - }; - - cpu@f01 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clocks = <&syscon ASPEED_CLK_HPLL>; - arm,cpu-registers-not-fw-configured; - always-on; - }; - - edac: sdram@1e6e0000 { - compatible = "aspeed,ast2600-sdram-edac", "syscon"; - reg = <0x1e6e0000 0x174>; - interrupts = ; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - ranges; - - gic: interrupt-controller@40461000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&gic>; - reg = <0x40461000 0x1000>, - <0x40462000 0x1000>, - <0x40464000 0x2000>, - <0x40466000 0x2000>; - }; - - ahbc: bus@1e600000 { - compatible = "aspeed,ast2600-ahbc", "syscon"; - reg = <0x1e600000 0x100>; - }; - - fmc: spi@1e620000 { - reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2600-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - interrupts = ; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - spi1: spi@1e630000 { - reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2600-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - spi2: spi@1e631000 { - reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2600-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - status = "disabled"; - }; - }; - - mdio0: mdio@1e650000 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650000 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio1_default>; - resets = <&syscon ASPEED_RESET_MII>; - }; - - mdio1: mdio@1e650008 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650008 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio2_default>; - resets = <&syscon ASPEED_RESET_MII>; - }; - - mdio2: mdio@1e650010 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650010 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio3_default>; - resets = <&syscon ASPEED_RESET_MII>; - }; - - mdio3: mdio@1e650018 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650018 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio4_default>; - resets = <&syscon ASPEED_RESET_MII>; - }; - - mac0: ftgmac@1e660000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; - status = "disabled"; - }; - - mac1: ftgmac@1e680000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e680000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; - status = "disabled"; - }; - - mac2: ftgmac@1e670000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e670000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; - status = "disabled"; - }; - - mac3: ftgmac@1e690000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e690000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; - status = "disabled"; - }; - - ehci0: usb@1e6a1000 { - compatible = "aspeed,ast2600-ehci", "generic-ehci"; - reg = <0x1e6a1000 0x100>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ah_default>; - status = "disabled"; - }; - - ehci1: usb@1e6a3000 { - compatible = "aspeed,ast2600-ehci", "generic-ehci"; - reg = <0x1e6a3000 0x100>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2bh_default>; - status = "disabled"; - }; - - uhci: usb@1e6b0000 { - compatible = "aspeed,ast2600-uhci", "generic-uhci"; - reg = <0x1e6b0000 0x100>; - interrupts = ; - #ports = <2>; - clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; - status = "disabled"; - /* - * No default pinmux, it will follow EHCI, use an - * explicit pinmux override if EHCI is not enabled. - */ - }; - - vhub: usb-vhub@1e6a0000 { - compatible = "aspeed,ast2600-usb-vhub"; - reg = <0x1e6a0000 0x350>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - aspeed,vhub-downstream-ports = <7>; - aspeed,vhub-generic-endpoints = <21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ad_default>; - status = "disabled"; - }; - - udc: usb@1e6a2000 { - compatible = "aspeed,ast2600-udc"; - reg = <0x1e6a2000 0x300>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2bd_default>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hace: crypto@1e6d0000 { - compatible = "aspeed,ast2600-hace"; - reg = <0x1e6d0000 0x200>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_YCLK>; - resets = <&syscon ASPEED_RESET_HACE>; - }; - - syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1000>; - ranges = <0 0x1e6e2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - #reset-cells = <1>; - - pinctrl: pinctrl { - compatible = "aspeed,ast2600-pinctrl"; - }; - - silicon-id@14 { - compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; - reg = <0x14 0x4 0x5b0 0x8>; - }; - - smp-memram@180 { - compatible = "aspeed,ast2600-smpmem"; - reg = <0x180 0x40>; - }; - - scu_ic0: interrupt-controller@560 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2600-scu-ic0"; - reg = <0x560 0x4>; - interrupts = ; - interrupt-controller; - }; - - scu_ic1: interrupt-controller@570 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2600-scu-ic1"; - reg = <0x570 0x4>; - interrupts = ; - interrupt-controller; - }; - }; - - rng: hwrng@1e6e2524 { - compatible = "timeriomem_rng"; - reg = <0x1e6e2524 0x4>; - period = <1>; - quality = <100>; - }; - - gfx: display@1e6e6000 { - compatible = "aspeed,ast2600-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_GRAPHICS>; - syscon = <&syscon>; - status = "disabled"; - interrupts = ; - }; - - xdma: xdma@1e6e7000 { - compatible = "aspeed,ast2600-xdma"; - reg = <0x1e6e7000 0x100>; - clocks = <&syscon ASPEED_CLK_GATE_BCLK>; - resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; - reset-names = "device", "root-complex"; - interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; - aspeed,pcie-device = "bmc"; - aspeed,scu = <&syscon>; - status = "disabled"; - }; - - adc0: adc@1e6e9000 { - compatible = "aspeed,ast2600-adc0"; - reg = <0x1e6e9000 0x100>; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_ADC>; - interrupts = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - adc1: adc@1e6e9100 { - compatible = "aspeed,ast2600-adc1"; - reg = <0x1e6e9100 0x100>; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_ADC>; - interrupts = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - sbc: secure-boot-controller@1e6f2000 { - compatible = "aspeed,ast2600-sbc"; - reg = <0x1e6f2000 0x1000>; - }; - - acry: crypto@1e6fa000 { - compatible = "aspeed,ast2600-acry"; - reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_RSACLK>; - aspeed,ahbc = <&ahbc>; - }; - - video: video@1e700000 { - compatible = "aspeed,ast2600-video-engine"; - reg = <0x1e700000 0x1000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, - <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - interrupts = ; - status = "disabled"; - }; - - gpio0: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-gpio"; - reg = <0x1e780000 0x400>; - interrupts = ; - gpio-ranges = <&pinctrl 0 0 208>; - ngpios = <208>; - clocks = <&syscon ASPEED_CLK_APB2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sgpiom0: sgpiom@1e780500 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-sgpiom"; - reg = <0x1e780500 0x100>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_APB2>; - interrupt-controller; - bus-frequency = <12000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgpm1_default>; - status = "disabled"; - }; - - sgpiom1: sgpiom@1e780600 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-sgpiom"; - reg = <0x1e780600 0x100>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_APB2>; - interrupt-controller; - bus-frequency = <12000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgpm2_default>; - status = "disabled"; - }; - - gpio1: gpio@1e780800 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-gpio"; - reg = <0x1e780800 0x800>; - interrupts = ; - gpio-ranges = <&pinctrl 0 208 36>; - ngpios = <36>; - clocks = <&syscon ASPEED_CLK_APB1>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rtc: rtc@1e781000 { - compatible = "aspeed,ast2600-rtc"; - reg = <0x1e781000 0x18>; - interrupts = ; - status = "disabled"; - }; - - timer: timer@1e782000 { - compatible = "aspeed,ast2600-timer"; - reg = <0x1e782000 0x90>; - interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&syscon ASPEED_CLK_APB1>; - clock-names = "PCLK"; - status = "disabled"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; - no-loopback-test; - }; - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785000 0x40>; - }; - - wdt2: watchdog@1e785040 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785040 0x40>; - status = "disabled"; - }; - - wdt3: watchdog@1e785080 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785080 0x40>; - status = "disabled"; - }; - - wdt4: watchdog@1e7850c0 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e7850C0 0x40>; - status = "disabled"; - }; - - peci0: peci-controller@1e78b000 { - compatible = "aspeed,ast2600-peci"; - reg = <0x1e78b000 0x100>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; - resets = <&syscon ASPEED_RESET_PECI>; - cmd-timeout-ms = <1000>; - clock-frequency = <1000000>; - status = "disabled"; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - kcs1: kcs@24 { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - kcs_chan = <1>; - status = "disabled"; - }; - - kcs2: kcs@28 { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - kcs3: kcs@2c { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - kcs4: kcs@114 { - compatible = "aspeed,ast2500-kcs-bmc-v2"; - reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2600-lpc-ctrl"; - reg = <0x80 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_snoop: lpc-snoop@80 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x80 0x80>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lhc: lhc@a0 { - compatible = "aspeed,ast2600-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; - }; - - lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2600-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; - }; - - uart_routing: uart-routing@98 { - compatible = "aspeed,ast2600-uart-routing"; - reg = <0x98 0x8>; - status = "disabled"; - }; - - ibt: ibt@140 { - compatible = "aspeed,ast2600-ibt-bmc"; - reg = <0x140 0x18>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - }; - - sdc: sdc@1e740000 { - compatible = "aspeed,ast2600-sd-controller"; - reg = <0x1e740000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e740000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; - status = "disabled"; - - sdhci0: sdhci@1e740100 { - compatible = "aspeed,ast2600-sdhci", "sdhci"; - reg = <0x100 0x100>; - interrupts = ; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - - sdhci1: sdhci@1e740200 { - compatible = "aspeed,ast2600-sdhci", "sdhci"; - reg = <0x200 0x100>; - interrupts = ; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - }; - - emmc_controller: sdc@1e750000 { - compatible = "aspeed,ast2600-sd-controller"; - reg = <0x1e750000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e750000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; - status = "disabled"; - - emmc: sdhci@1e750100 { - compatible = "aspeed,ast2600-sdhci"; - reg = <0x100 0x100>; - sdhci,auto-cmd12; - interrupts = ; - clocks = <&syscon ASPEED_CLK_EMMC>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc_default>; - }; - }; - - vuart1: serial@1e787000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_APB1>; - no-loopback-test; - status = "disabled"; - }; - - vuart2: serial@1e788000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e788000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_APB1>; - no-loopback-test; - status = "disabled"; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; - status = "disabled"; - }; - - uart6: serial@1e790000 { - compatible = "ns16550a"; - reg = <0x1e790000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6_default>; - - status = "disabled"; - }; - - uart7: serial@1e790100 { - compatible = "ns16550a"; - reg = <0x1e790100 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7_default>; - - status = "disabled"; - }; - - uart8: serial@1e790200 { - compatible = "ns16550a"; - reg = <0x1e790200 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8_default>; - - status = "disabled"; - }; - - uart9: serial@1e790300 { - compatible = "ns16550a"; - reg = <0x1e790300 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart9_default>; - - status = "disabled"; - }; - - i2c: bus@1e78a000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - }; - - fsim0: fsi@1e79b000 { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b000 0x94>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi1_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - status = "disabled"; - }; - - fsim1: fsi@1e79b100 { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b100 0x94>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi2_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - status = "disabled"; - }; - - udma: dma-controller@1e79e000 { - compatible = "aspeed,ast2600-udma"; - reg = <0x1e79e000 0x1000>; - interrupts = ; - dma-channels = <28>; - #dma-cells = <1>; - status = "disabled"; - }; - }; - }; -}; - -#include "aspeed-g6-pinctrl.dtsi" - -&i2c { - i2c0: i2c-bus@80 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "disabled"; - }; - - i2c1: i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x100 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - status = "disabled"; - }; - - i2c2: i2c-bus@180 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x180 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c-bus@200 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x200 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c-bus@280 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x280 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c-bus@300 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x300 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c-bus@380 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x380 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c-bus@400 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x400 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c-bus@480 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x480 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c-bus@500 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x500 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c-bus@580 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x580 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c-bus@600 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x600 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c-bus@680 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x680 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c-bus@700 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x700 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; - - i2c14: i2c-bus@780 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x780 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c15_default>; - status = "disabled"; - }; - - i2c15: i2c-bus@800 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x800 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c16_default>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile new file mode 100644 index 000000000000..c68984322a86 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb-a1.dtb \ + aspeed-ast2600-evb.dtb \ + aspeed-bmc-amd-daytonax.dtb \ + aspeed-bmc-amd-ethanolx.dtb \ + aspeed-bmc-ampere-mtjade.dtb \ + aspeed-bmc-ampere-mtmitchell.dtb \ + aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-e3c246d4i.dtb \ + aspeed-bmc-asrock-romed8hm3.dtb \ + aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-delta-ahe50dc.dtb \ + aspeed-bmc-facebook-bletchley.dtb \ + aspeed-bmc-facebook-cloudripper.dtb \ + aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-elbert.dtb \ + aspeed-bmc-facebook-fuji.dtb \ + aspeed-bmc-facebook-galaxy100.dtb \ + aspeed-bmc-facebook-greatlakes.dtb \ + aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-tiogapass.dtb \ + aspeed-bmc-facebook-wedge40.dtb \ + aspeed-bmc-facebook-wedge100.dtb \ + aspeed-bmc-facebook-wedge400.dtb \ + aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-facebook-yosemitev2.dtb \ + aspeed-bmc-ibm-bonnell.dtb \ + aspeed-bmc-ibm-everest.dtb \ + aspeed-bmc-ibm-rainier.dtb \ + aspeed-bmc-ibm-rainier-1s4u.dtb \ + aspeed-bmc-ibm-rainier-4u.dtb \ + aspeed-bmc-intel-s2600wf.dtb \ + aspeed-bmc-inspur-fp5280g2.dtb \ + aspeed-bmc-inspur-nf5280m6.dtb \ + aspeed-bmc-inspur-on5263m5.dtb \ + aspeed-bmc-lenovo-hr630.dtb \ + aspeed-bmc-lenovo-hr855xg2.dtb \ + aspeed-bmc-microsoft-olympus.dtb \ + aspeed-bmc-opp-lanyang.dtb \ + aspeed-bmc-opp-mowgli.dtb \ + aspeed-bmc-opp-nicole.dtb \ + aspeed-bmc-opp-palmetto.dtb \ + aspeed-bmc-opp-romulus.dtb \ + aspeed-bmc-opp-swift.dtb \ + aspeed-bmc-opp-tacoma.dtb \ + aspeed-bmc-opp-vesnin.dtb \ + aspeed-bmc-opp-witherspoon.dtb \ + aspeed-bmc-opp-zaius.dtb \ + aspeed-bmc-portwell-neptune.dtb \ + aspeed-bmc-qcom-dc-scm-v1.dtb \ + aspeed-bmc-quanta-q71l.dtb \ + aspeed-bmc-quanta-s6q.dtb \ + aspeed-bmc-supermicro-x11spi.dtb \ + aspeed-bmc-inventec-transformers.dtb \ + aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-tyan-s8036.dtb \ + aspeed-bmc-ufispace-ncplite.dtb \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts new file mode 100644 index 000000000000..a497dd135491 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "AST2500 EVB"; + compatible = "aspeed,ast2500-evb", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&spi2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_default>; +}; + +/* + * Enable port A as device (via the virtual hub) and port B as + * host by default on the eval board. This can be easily changed + * by replacing the override below with &ehci0 { ... } to enable + * host on both ports. + */ +&vhub { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts new file mode 100644 index 000000000000..f34a2b1ec2f0 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 IBM Corp. + +#include "aspeed-ast2600-evb.dts" + +/ { + model = "AST2600 A1 EVB"; + compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600-evb", "aspeed,ast2600"; + + /delete-node/regulator-vcc-sdhci0; + /delete-node/regulator-vcc-sdhci1; + /delete-node/regulator-vccq-sdhci0; + /delete-node/regulator-vccq-sdhci1; +}; + +/delete-node/ &sdc; diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts new file mode 100644 index 000000000000..de83c0eb1d6e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include + +/ { + model = "AST2600 EVB"; + compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + vcc_sdhci0: regulator-vcc-sdhci0 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci0: regulator-vccq-sdhci0 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; + + vcc_sdhci1: regulator-vcc-sdhci1 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci1: regulator-vccq-sdhci1 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii-rxid"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + + +&mac1 { + status = "okay"; + + phy-mode = "rgmii-rxid"; + phy-handle = <ðphy1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default>; +}; + +&mac2 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-rx-bus-width = <4>; + spi-max-frequency = <100000000>; + }; +}; + +&uart5 { + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c8 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&fsim0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&sdc { + status = "okay"; +}; + +/* + * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be + * toggled by GPIO pins. + * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the + * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to + * a 1.8v and a 3.3v power load switch that provides signal voltage to + * sdhci0 bus. + * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled. + * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal + * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled, + * sdhci0 signal voltage becomes 1.8v. + * AST2600-A2 EVB also supports toggling signal voltage for sdhci1. + * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3 + * as power-switch-gpio. + */ +&sdhci0 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci0>; + vqmmc-supply = <&vccq_sdhci0>; + clk-phase-sd-hs = <7>, <200>; +}; + +&sdhci1 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci1>; + vqmmc-supply = <&vccq_sdhci1>; + clk-phase-sd-hs = <7>, <200>; +}; + +&vhub { + status = "okay"; + pinctrl-names = "default"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts new file mode 100644 index 000000000000..64bb9bf92de2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "AMD DaytonaX BMC"; + compatible = "amd,daytonax-bmc", "aspeed,ast2500"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + aliases { + serial0 = &uart1; + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led-fault { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + led-identify { + gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>, + <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + #include "openbmc-flash-layout.dtsi" + }; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&uart1 { + //Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + //BMC Console + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","led-fault","led-identify","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "id-button","","","","","","","", + /*D0-D7*/ "","","ASSERT_BMC_READY","","","","","", + /*E0-E7*/ "reset-button","reset-control","power-button","power-control","", + "power-good","power-ok","", + /*F0-F7*/ "","","","","","","BATTERY_DETECT","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "FM_BMC_READ_SPD_TEMP","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>, <0x81>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@14 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; + + fan@15 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts new file mode 100644 index 000000000000..6bded774c457 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 AMD Inc. +// Author: Supreeth Venkatesh +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "AMD EthanolX BMC"; + compatible = "amd,ethanolx-bmc", "aspeed,ast2500"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + + aliases { + serial0 = &uart1; + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + leds { + compatible = "gpio-leds"; + + fault { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; + }; + }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + #include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&uart1 { + //Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ncts1_default>; +}; + +&uart5 { + //BMC Console + status = "okay"; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","", + /*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S", + "JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD", + /*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN", + "MON_P0_PWR_GOOD","MON_PWROK","MON_RESET", + /*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP", + "MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","", + /*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0", + "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","", + /*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3", + "PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN", + "ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT", + "ASSERT_CLR_CMOS","ASSERT_BMC_READY", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT", + "P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT", + "P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT", + "P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","SENSOR THERM","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +//APML for P0 +&i2c0 { + status = "okay"; +}; + +//APML for P1 +&i2c1 { + status = "okay"; +}; + +//FPGA +&i2c2 { + status = "okay"; +}; + +//24LC128 EEPROM +&i2c3 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +//P0 Power regulators +&i2c4 { + status = "okay"; +}; + +//P1 Power regulators +&i2c5 { + status = "okay"; +}; + +//P0/P1 Thermal diode +&i2c6 { + status = "okay"; +}; + +// Thermal Sensors +&i2c7 { + status = "okay"; + + lm75a@48 { + compatible = "national,lm75a"; + reg = <0x48>; + }; + + lm75a@49 { + compatible = "national,lm75a"; + reg = <0x49>; + }; + + lm75a@4a { + compatible = "national,lm75a"; + reg = <0x4a>; + }; + + lm75a@4b { + compatible = "national,lm75a"; + reg = <0x4b>; + }; + + lm75a@4c { + compatible = "national,lm75a"; + reg = <0x4c>; + }; + + lm75a@4d { + compatible = "national,lm75a"; + reg = <0x4d>; + }; + + lm75a@4e { + compatible = "national,lm75a"; + reg = <0x4e>; + }; + + lm75a@4f { + compatible = "national,lm75a"; + reg = <0x4f>; + }; +}; + +//BMC I2C +&i2c8 { + status = "okay"; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0x60>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0x62>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA2>; +}; + +&kcs4 { + status = "okay"; + aspeed,lpc-io-reg = <0x97DE>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>, <0x81>; +}; + +&lpc_ctrl { + //Enable lpc clock + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts new file mode 100644 index 000000000000..0a51d2e32fab --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts @@ -0,0 +1,808 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Ampere Mt. Jade BMC"; + compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; + + aliases { + /* + * i2c bus 50-57 assigned to NVMe slot 0-7 + */ + i2c50 = &nvmeslot_0; + i2c51 = &nvmeslot_1; + i2c52 = &nvmeslot_2; + i2c53 = &nvmeslot_3; + i2c54 = &nvmeslot_4; + i2c55 = &nvmeslot_5; + i2c56 = &nvmeslot_6; + i2c57 = &nvmeslot_7; + + /* + * i2c bus 60-67 assigned to NVMe slot 8-15 + */ + i2c60 = &nvmeslot_8; + i2c61 = &nvmeslot_9; + i2c62 = &nvmeslot_10; + i2c63 = &nvmeslot_11; + i2c64 = &nvmeslot_12; + i2c65 = &nvmeslot_13; + i2c66 = &nvmeslot_14; + i2c67 = &nvmeslot_15; + + /* + * i2c bus 70-77 assigned to NVMe slot 16-23 + */ + i2c70 = &nvmeslot_16; + i2c71 = &nvmeslot_17; + i2c72 = &nvmeslot_18; + i2c73 = &nvmeslot_19; + i2c74 = &nvmeslot_20; + i2c75 = &nvmeslot_21; + i2c76 = &nvmeslot_22; + i2c77 = &nvmeslot_23; + + /* + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 + */ + i2c80 = &nvme_m2_0; + i2c81 = &nvme_m2_1; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + fault { + gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>; + }; + }; + + gpioA0mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>; + }; + + adc0mux: adc0mux { + compatible = "io-channel-mux"; + io-channels = <&adc 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc1mux: adc1mux { + compatible = "io-channel-mux"; + io-channels = <&adc 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc2mux: adc2mux { + compatible = "io-channel-mux"; + io-channels = <&adc 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc3mux: adc3mux { + compatible = "io-channel-mux"; + io-channels = <&adc 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc4mux: adc4mux { + compatible = "io-channel-mux"; + io-channels = <&adc 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc5mux: adc5mux { + compatible = "io-channel-mux"; + io-channels = <&adc 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc6mux: adc6mux { + compatible = "io-channel-mux"; + io-channels = <&adc 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc7mux: adc7mux { + compatible = "io-channel-mux"; + io-channels = <&adc 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc8mux: adc8mux { + compatible = "io-channel-mux"; + io-channels = <&adc 8>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc9mux: adc9mux { + compatible = "io-channel-mux"; + io-channels = <&adc 9>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc10mux: adc10mux { + compatible = "io-channel-mux"; + io-channels = <&adc 10>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc11mux: adc11mux { + compatible = "io-channel-mux"; + io-channels = <&adc 11>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc12mux: adc12mux { + compatible = "io-channel-mux"; + io-channels = <&adc 12>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + adc13mux: adc13mux { + compatible = "io-channel-mux"; + io-channels = <&adc 13>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioA0mux>; + channels = "s0", "s1"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0mux 0>, <&adc0mux 1>, + <&adc1mux 0>, <&adc1mux 1>, + <&adc2mux 0>, <&adc2mux 1>, + <&adc3mux 0>, <&adc3mux 1>, + <&adc4mux 0>, <&adc4mux 1>, + <&adc5mux 0>, <&adc5mux 1>, + <&adc6mux 0>, <&adc6mux 1>, + <&adc7mux 0>, <&adc7mux 1>, + <&adc8mux 0>, <&adc8mux 1>, + <&adc9mux 0>, <&adc9mux 1>, + <&adc10mux 0>, <&adc10mux 1>, + <&adc11mux 0>, <&adc11mux 1>, + <&adc12mux 0>, <&adc12mux 1>, + <&adc13mux 0>, <&adc13mux 1>, + <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + /* spi-max-frequency = <50000000>; */ +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + /* spi-max-frequency = <100000000>; */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + uefi@400000 { + reg = <0x400000 0x1C00000>; + label = "pnor-uefi"; + }; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_nrts1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* The BMC's uart */ +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; + smpro@4e { + compatible = "ampere,smpro"; + reg = <0x4e>; + }; +}; + +&i2c3 { + status = "okay"; + eeprom@50 { + compatible = "microchip,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + inlet_mem2: tmp175@28 { + compatible = "ti,tmp175"; + reg = <0x28>; + }; + + inlet_cpu: tmp175@29 { + compatible = "ti,tmp175"; + reg = <0x29>; + }; + + inlet_mem1: tmp175@2a { + compatible = "ti,tmp175"; + reg = <0x2a>; + }; + + outlet_cpu: tmp175@2b { + compatible = "ti,tmp175"; + reg = <0x2b>; + }; + + outlet1: tmp175@2c { + compatible = "ti,tmp175"; + reg = <0x2c>; + }; + + outlet2: tmp175@2d { + compatible = "ti,tmp175"; + reg = <0x2d>; + }; +}; + +&i2c4 { + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; +}; + +&i2c5 { + status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + nvmeslot_0_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8_15: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + nvmeslot_16_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + }; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + nvme_m2_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + nvme_m2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + }; +}; + +&nvmeslot_0_7 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + + }; +}; + +&nvmeslot_8_15 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_12: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_13: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_14: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_15: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&nvmeslot_16_23 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&i2c6 { + status = "okay"; + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + psu@59 { + compatible = "pmbus"; + reg = <0x59>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + }; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@1 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@2 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@5 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@6 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@7 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@8 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@9 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@10 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; + + fan@11 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; + +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","", + /*B0-B7*/ "BMC_SELECT_EEPROM","","","", + "POWER_BUTTON","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", + "S1_DDR_SAVE","","", + /*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","", + "","", + /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", + /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", + "","","","","", + /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", + "","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","UID_BUTTON","","", + /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", + "OCP_MAIN_PWREN","RESET_BUTTON","","", + /*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","", + "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR", + "S1_BMC_DDR_ADR","","","","", + /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", + "BMC_OCP_PG"; + + i2c4-o-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_I2C4_O_EN"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts new file mode 100644 index 000000000000..1e0e88465254 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2022, Ampere Computing LLC + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include + +/ { + model = "Ampere Mt.Mitchell BMC"; + compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600"; + + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + voltage_mon_reg: voltage-mon-regulator { + compatible = "regulator-fixed"; + regulator-name = "ltc2497_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpioI5mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>; + }; + + adc0mux: adc0mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc1mux: adc1mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc2mux: adc2mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc3mux: adc3mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc4mux: adc4mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc5mux: adc5mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc6mux: adc6mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc7mux: adc7mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc8mux: adc8mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc9mux: adc9mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc10mux: adc10mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc11mux: adc11mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc12mux: adc12mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc13mux: adc13mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc14mux: adc14mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc15mux: adc15mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0mux 0>, <&adc0mux 1>, + <&adc1mux 0>, <&adc1mux 1>, + <&adc2mux 0>, <&adc2mux 1>, + <&adc3mux 0>, <&adc3mux 1>, + <&adc4mux 0>, <&adc4mux 1>, + <&adc5mux 0>, <&adc5mux 1>, + <&adc6mux 0>, <&adc6mux 1>, + <&adc7mux 0>, <&adc7mux 1>, + <&adc8mux 0>, <&adc8mux 1>, + <&adc9mux 0>, <&adc9mux 1>, + <&adc10mux 0>, <&adc10mux 1>, + <&adc11mux 0>, <&adc11mux 1>, + <&adc12mux 0>, <&adc12mux 1>, + <&adc13mux 0>, <&adc13mux 1>, + <&adc14mux 0>, <&adc14mux 1>, + <&adc15mux 0>, <&adc15mux 1>, + <&adc_i2c 0>, <&adc_i2c 1>, + <&adc_i2c 2>, <&adc_i2c 3>, + <&adc_i2c 4>, <&adc_i2c 5>, + <&adc_i2c 6>, <&adc_i2c 7>, + <&adc_i2c 8>, <&adc_i2c 9>, + <&adc_i2c 10>, <&adc_i2c 11>, + <&adc_i2c 12>, <&adc_i2c 13>, + <&adc_i2c 14>, <&adc_i2c 15>; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + psu@59 { + compatible = "pmbus"; + reg = <0x59>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + adc_i2c: adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&voltage_mon_reg>; + #io-channel-cells = <1>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c4_bus70_chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + outlet_temp1: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + psu1_inlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + pcie_zone_temp1: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + psu0_inlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + pcie_zone_temp2: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + outlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + mb_inlet_temp1: temperature-sensor@7c { + compatible = "microchip,emc1413"; + reg = <0x7c>; + }; + mb_inlet_temp2: temperature-sensor@4c { + compatible = "microchip,emc1413"; + reg = <0x4c>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c6 { + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + gpio@77 { + compatible = "nxp,pca9539"; + reg = <0x77>; + gpio-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <2>; + + bmc-ocp0-en-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-high; + line-name = "bmc-ocp0-en-n"; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c14 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + bmc_ast2600_cpu: temperature-sensor@35 { + compatible = "ti,tmp175"; + reg = <0x35>; + }; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n", + /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","", + /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","", + "irq-n","","vrd-sel","spd-sel", + /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n", + "","bmc-ncsi-txen","","", + /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","", + /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control", + "cpu-bios-recover","s0-heartbeat","hs-csout-prochot", + "s0-vr-hot-n","s1-vr-hot-n", + /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","", + /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","", + /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0", + "s0-rtc-lock","","","", + /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb", + "jtag-dbgr-prsnt-n","s1-heartbeat","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","", + "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","identify-button","led-identify", + "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", + "host0-reboot-ack-n","host0-ready","host0-shd-req-n", + "host0-shd-ack-n","s0-overtemp-n", + /*W0-W7*/ "","ocp-main-pwren","ocp-pgood","", + "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", + /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", + "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", + "s1-overtemp-n","s1-spi-auth-fail-n", + /*Y0-Y7*/ "","","","","","","","host0-special-boot", + /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; + + ocp-aux-pwren-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "ocp-aux-pwren"; + }; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","s0-soc-pgood","", + /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1", + "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts new file mode 100644 index 000000000000..7c6af7f226e7 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "HXT StarDragon 4800 REP2 AST2520"; + compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + leds { + compatible = "gpio-leds"; + + system_fault1 { + label = "System_fault1"; + gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>; + }; + + system_fault2 { + label = "System_fault2"; + gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; +}; + +&uart3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; + current-speed = <115200>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii2_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, + <&syscon ASPEED_CLK_MAC2RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp421@1e { + compatible = "ti,tmp421"; + reg = <0x1e>; + }; + tmp421@2a { + compatible = "ti,tmp421"; + reg = <0x2a>; + }; + tmp421@1c { + compatible = "ti,tmp421"; + reg = <0x1c>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + nvt210@4c { + compatible = "nvt210"; + reg = <0x4c>; + }; + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <128>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + pca9641@70 { + compatible = "nxp,pca9641"; + reg = <0x70>; + i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + dps650ab@58 { + compatible = "dps650ab"; + reg = <0x58>; + }; + }; + }; + + dps650ab@58 { + compatible = "delta,dps650ab"; + reg = <0x58>; + }; + + dps650ab@59 { + compatible = "delta,dps650ab"; + reg = <0x59>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&gpio { + pin_gpio_c7 { + gpio-hog; + gpios = ; + output-low; + line-name = "BIOS_SPI_MUX_S"; + }; + pin_gpio_d1 { + gpio-hog; + gpios = ; + output-high; + line-name = "PHY2_RESET_N"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts new file mode 100644 index 000000000000..c4b2efbfdf56 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/{ + model = "ASRock E3C246D4I BMC"; + compatible = "asrock,e3c246d4i-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + /* BMC_HB_LED_N */ + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + system-fault { + /* SYSTEM_FAULT_LED_N */ + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + uid-button { + label = "uid-button"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; /* 50 MHz */ +#include "openbmc-flash-layout.dtsi" + }; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c1 { + status = "okay"; + + /* thermal sensor, one diode run to a disconnected header */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c3 { + status = "okay"; + + /* FRU EEPROM */ + eeprom@57 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&video { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "BMC_MAC1_INTB", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", + "", "", "", "", + /* B */ "", "", "", "", "", "IRQ_BMC_PCH_SMI_LPC_N", "", "", + /* C */ "", "", "", "", "", "", "", "", + /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", + "", "", "", "", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "LOCATORLED_STATUS_N", "LOCATORBTN", "", "", + "", "", "BMC_PCH_SCI_LPC", "BMC_NCSI_MUX_CTL", + /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", + "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "SML0ALERT", + /* H */ "FM_ME_RCVR_N", "O_PWROK", "SKL_CNL_R", "D4_DIMM_EVENT_3V_N", + "MFG_MODE_N", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "BMC_SMI", "", + "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "BMC_CTS1", "BMC_DCD1", "BMC_DSR1", "BMC_RI1", + "BMC_DTR1", "BMC_RTS1", "BMC_TXD1", "BMC_RXD1", + /* M */ "BMC_LAN0_DIS_N", "BMC_LAN1_DIS_N", "", "", + "", "", "", "", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", + "BMC_SBM_PRESENT_1_N", "BMC_SBM_PRESENT_2_N", + "BMC_SBM_PRESENT_3_N", "BMC_PCIE_WAKE_N", + /* R */ "", "", "", "", "", "", "", "", + /* S */ "PCHHOT_BMC_N", "", "RSMRST", + "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "PS_PWROK", /* dummy always-high signal */ + "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "SLP_S3", "SLP_S5", "", "", "", "", "", "", + /* Z */ "CPU_CATERR_BMC_PCH_N", "", "SYSTEM_FAULT_LED_N", "BMC_THROTTLE_N", + "", "", "", "", + /* AA */ "CPU1_THERMTRIP_LATCH_N", "", "CPU1_PROCHOT_N", "", + "", "", "IRQ_SMI_ACTIVE_N", "FM_BIOS_POST_CMPLT_N", + /* AB */ "", "", "ME_OVERRIDE", "BMC_DMI_MODIFY", + "", "", "", "", + /* AC */ "LAD0", "LAD1", "LAD2", "LAD3", + "CK_33M_BMC", "LFRAME", "SERIRQ", "S_PLTRST"; + + /* Assert BMC_READY so BIOS doesn't sit around waiting for it */ + bmc-ready { + gpio-hog; + gpios = ; + output-high; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&peci0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts new file mode 100644 index 000000000000..4554abf0c7cd --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/{ + model = "ASRock ROMED8HM3 BMC v1.00"; + compatible = "asrock,romed8hm3-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + system-fault { + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; /* 50 MHz */ +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; + + /* inlet temp sensor */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* IPB temp sensor */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; + + /* IPB PMIC */ + lm25066@40 { + compatible = "lm25066"; + reg = <0x40>; + shunt-resistor-micro-ohms = <1000>; + }; + + /* 12VSB PMIC */ + lm25066@41 { + compatible = "lm25066"; + reg = <0x41>; + shunt-resistor-micro-ohms = <10000>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + /* Baseboard FRU eeprom */ + eeprom@50 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&video { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", + "", "", "", "", + /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "", + /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "", + /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", + "", "", "", "PSU_FAN_FAIL_N", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "NIC_PWR_GOOD", "PRSNTB0", "PRSNTB1", "PRSNTB2", + "PRSNTB3", "", "3VSB_PCIE1_PG", "12V_PCIE1_PG", + /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", + "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "BMC_ALERT4_N", + /* H */ "X24_C1_PRSNT", "X24_C2_PRSNT", "X24_C3_PRSNT", "FM_MEM_THERM_EVENT_BMC_R_N", + "FACMODE", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "", "P0_MA_DDR_QS_CS_N", + "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "MEZZ_PWRBRK_N", "OCP_HP_RST_EN", + "MAIN_PWR_EN_G", "BMC_MAIN_EN", "AUX_PWR_EN_G", "BMC_AUX_EN", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", + "BMC_SMB_PRESENT_1_N", "BMC_SMB_PRESENT_2_N", + "BMC_SMB_PRESENT_3_N", "BMC_PCIE_WAKE_N", + /* R */ "", "", "THERMALTRIP_CLEAR_N", "", "", "", "", "", + /* S */ "", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "SLP_S3", "SLP_S4_S5", "NODE_ID_1", "NODE_ID_2", "", "", "", "", + /* Z */ "", "", "SYSTEM_FAULT_LED_N", "FAST_THROTTLE_N", + "", "", "", "", + /* AA */ "FM_CPU0_IBMC_THERMTRIP_N", "", "PROCHOT_L_G", "", + "", "", "", "", + /* AB */ "BMC_FORCE_SELFREFRESH", "PWRGD_OUT", "", "IRQ_BMC_PCH_SMI_LPC_N", + "", "", "", "", + /* AC */ "", "", "", "", "", "", "", ""; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts new file mode 100644 index 000000000000..f75cad41ae6f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts @@ -0,0 +1,940 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2020 Bytedance. +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model = "Bytedance G220A BMC"; + compatible = "bytedance,g220a-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + i2c14 = &channel_3_0; + i2c15 = &channel_3_1; + i2c16 = &channel_3_2; + i2c17 = &channel_3_3; + i2c18 = &channel_6_0; + i2c19 = &channel_6_1; + i2c20 = &channel_6_2; + i2c21 = &channel_6_3; + i2c22 = &channel_6_4; + i2c23 = &channel_6_5; + i2c24 = &channel_6_6; + i2c25 = &channel_6_7; + i2c26 = &channel_6_8; + i2c27 = &channel_6_9; + i2c28 = &channel_6_10; + i2c29 = &channel_6_11; + i2c30 = &channel_6_12; + i2c31 = &channel_6_13; + i2c32 = &channel_6_14; + i2c33 = &channel_6_15; + i2c34 = &channel_6_16; + i2c35 = &channel_6_17; + i2c36 = &channel_6_18; + i2c37 = &channel_6_19; + i2c38 = &channel_6_20; + i2c39 = &channel_6_21; + i2c40 = &channel_6_22; + i2c41 = &channel_6_23; + i2c42 = &channel_6_24; + i2c43 = &channel_6_25; + i2c44 = &channel_10_0; + i2c45 = &channel_10_1; + i2c46 = &channel_10_2; + i2c47 = &channel_10_3; + i2c48 = &channel_10_4; + i2c49 = &channel_10_5; + i2c50 = &channel_10_6; + i2c51 = &channel_10_7; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@bc000000 { + no-map; + reg = <0xbc000000 0x04000000>; /* 64M */ + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + led-pattern = <1000 1000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + event-burn-in-signal { + label = "burn-in"; + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-rear-riser1-presence { + label = "rear-riser1-presence"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + linux,code = <1>; + }; + + event-alrt-pvddq-cpu0 { + label = "alrt-pvddq-cpu0"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + event-rear-riser0-presence { + label = "rear-riser0-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <3>; + }; + + event-fault-pvddq-cpu0 { + label = "fault-pvddq-cpu0"; + gpios = <&pca0 10 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + event-alrt-pvddq-cpu1 { + label = "alrt-pvddq-cpu1"; + gpios = <&pca0 11 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + event-fault-pvddq-cpu1 { + label = "alrt-pvddq-cpu1"; + gpios = <&pca0 12 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-fault-pvccin-cpu1 { + label = "fault-pvccin-cpuq"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + event-bmc-rom0-wp { + label = "bmc-rom0-wp"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + event-bmc-rom1-wp { + label = "bmc-rom1-wp"; + gpios = <&pca1 1 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca1 4 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca1 5 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + event-fan4-presence { + label = "fan4-presence"; + gpios = <&pca1 6 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + + event-fan5-presence { + label = "fan5-presence"; + gpios = <&pca1 7 GPIO_ACTIVE_LOW>; + linux,code = <15>; + }; + + event-front-bp1-presence { + label = "front-bp1-presence"; + gpios = <&pca1 8 GPIO_ACTIVE_LOW>; + linux,code = <16>; + }; + + event-rear-bp-presence { + label = "rear-bp-presence"; + gpios = <&pca1 9 GPIO_ACTIVE_LOW>; + linux,code = <17>; + }; + + event-fault-pvccin-cpu0 { + label = "fault-pvccin-cpu0"; + gpios = <&pca1 10 GPIO_ACTIVE_LOW>; + linux,code = <18>; + }; + + event-alrt-p1v05-pvcc { + label = "alrt-p1v05-pvcc1"; + gpios = <&pca1 11 GPIO_ACTIVE_LOW>; + linux,code = <19>; + }; + + event-fault-p1v05-pvccio { + label = "alrt-p1v05-pvcc1"; + gpios = <&pca1 12 GPIO_ACTIVE_LOW>; + linux,code = <20>; + }; + + event-alrt-p1v8-pvccio { + label = "alrt-p1v8-pvccio"; + gpios = <&pca1 13 GPIO_ACTIVE_LOW>; + linux,code = <21>; + }; + + event-fault-p1v8-pvccio { + label = "fault-p1v8-pvccio"; + gpios = <&pca1 14 GPIO_ACTIVE_LOW>; + linux,code = <22>; + }; + + event-front-bp0-presence { + label = "front-bp0-presence"; + gpios = <&pca1 15 GPIO_ACTIVE_LOW>; + linux,code = <23>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; + +&adc { + status = "okay"; +}; + +&wdt2 { + status = "okay"; + aspeed,alt-boot; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "SMRST_OCP_N","MAC2_LINK","BMC_CPLD_SMB_RST_R_N","BMC_CPLD_GPIO0", + "","","","", + /*B0-B7*/ "BMC_INIT_R_OK","FM_BOARD_REV_ID2","FM_PROJECT_ID7","FAULT_P12V_STBY_N", + "","CPU0_PROCHOT_LVT3_N","","BIOS_LOAD_DEFAULT_R_N", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "FM_PROJECT_ID0","FM_PROJECT_ID1","FM_PROJECT_ID2","FM_PROJECT_ID3", + "FM_PROJECT_ID4","FM_PROJECT_ID5","","", + /*F0-F7*/ "PSU0_PRSNT_N","PSU1_PRSNT_N","","FAULT_P12V_NVME_N", + "BIOS_DEBUG_MODE_R_N","DISABLE_CPU_DDR_R_SPD","COOLING_STRATEGY", + "PCH_GLB_RST_N", + /*G0-G7*/ "P12V_PMBUS_ALERT_N","CPLD_ALERT_N","BMC_RELOAD_N", + "P12V_PVDDQ_PMBUS_ALERT_N","BMC_JTAG_TCK_MUX_R_SEL","","NMI_OUT", + "NMI_BUTTON", + /*H0-H7*/ "BMC_CPLD_JTAG_TDI","BMC_CPLD_JTAG_TDO","BMC_CPLD_JTAG_TCK", + "BMC_CPLD_JTAG_TMS","FM_PROJECT_ID6","FM_BOARD_REV_ID0", + "PCA9546_U70_RST_N","IRQ_SML0_ALERT_N", + /*I0-I7*/ "FAULT_FRONT_RISER_P12V_N","FAULT_OCP_P12V_N","FM_BMC_PCH_SCI_R_N", + "","","","","", + /*J0-J7*/ "FM_CPU0_SKTOCC_N","FM_CPU1_SKTOCC_N","FM_CPU1_DISABLE_COD_N", + "","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "P12V_FAULT_N","PWRGD_P12V_PCIE_RISER","","LEAKAGE_DETECT_INPUT_N", + "","IRQ_SML1_PMBUS_ALERT_N","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","CHASSIS_INTRUSION", + /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", + "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", + /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", + "FM_BMC_XDP_DEBUG_EN","","STRAP_BMC_BATTERY_GPIOS5","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","PWRGD_PSU0_PWROK","CPU1_PROCHOT_LVT3_N","IRQ_BMC_PCH_SMI_LPC_N", + "","","","", + /*Z0-Z7*/ "XDP_PRSNT_N","BMC_XDP_SYS_PWROK","BMC_XDP_JTAG_SEL", + "PCH_BMC_SMI_ACTIVE_R_N","","","","", + /*AA0-AA7*/ "PWRGD_P12V_STBY_OCP","PS_PWROK","RST_PLTRST_BMC_R_N","HDA_SDO_R", + "FM_SLPS4_R_N","PWRGD_PSU1_PWROK","POWER_BUTTON","POWER_OUT", + /*AB0-AB7*/ "","RESET_OUT","SPI_BIOS_MODE_SELECT","POST_COMPLETE","","","","", + /*AC0-AC7*/ "","","","","","","","CPLD_PLTRST_B_N"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + channel_3_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_3_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_3_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_3_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c4 { + status = "okay"; + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + i2c-switch@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + channel_6_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + channel_6_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + channel_6_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + channel_6_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_12: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + }; + + channel_6_13: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_14: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_15: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + }; + + channel_6_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + pca0:pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + }; + + pca1:pca9555@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + channel_10_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_10_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_10_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_10_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_10_4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_10_5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_10_6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_10_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; + }; +}; + +&gpio { + pin_gpio_i3 { + gpio-hog; + gpios = ; + output-low; + line-name = "NCSI_BMC_R_SEL"; + }; + + pin_gpio_b6 { + gpio-hog; + gpios = ; + output-low; + line-name = "EN_NCSI_SWITCH_N"; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts new file mode 100644 index 000000000000..6600f7e9bf5e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include + +#define EFUSE_OUTPUT(n) \ + efuse##n { \ + compatible = "regulator-output"; \ + vout-supply = <&efuse##n>; \ + } + +#define __stringify(x) #x + +#define EFUSE(hexaddr, num) \ + efuse@##hexaddr { \ + compatible = "lm25066"; \ + reg = <0x##hexaddr>; \ + shunt-resistor-micro-ohms = <675>; \ + regulators { \ + efuse##num: vout0 { \ + regulator-name = __stringify(efuse##num##-reg); \ + }; \ + }; \ + } + +/{ + model = "Delta Power AHE-50DC"; + compatible = "delta,ahe50dc-bmc", "aspeed,ast2400"; + + aliases { + serial4 = &uart5; + + /* + * pca9541-arbitrated logical i2c buses are numbered as the + * corresponding physical bus plus 20 + */ + i2c20 = &i2carb0; + i2c21 = &i2carb1; + i2c22 = &i2carb2; + i2c23 = &i2carb3; + i2c24 = &i2carb4; + i2c26 = &i2carb6; + i2c27 = &i2carb7; + i2c28 = &i2carb8; + i2c32 = &i2carb12; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS2,115200n8 earlycon"; + }; + + memory@40000000 { + reg = <0x40000000 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + panic { + gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "panic"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; + }; + + EFUSE_OUTPUT(01); + EFUSE_OUTPUT(02); + EFUSE_OUTPUT(03); + EFUSE_OUTPUT(04); + EFUSE_OUTPUT(05); + EFUSE_OUTPUT(06); + EFUSE_OUTPUT(07); + EFUSE_OUTPUT(08); + EFUSE_OUTPUT(09); + EFUSE_OUTPUT(10); + EFUSE_OUTPUT(11); + EFUSE_OUTPUT(12); + EFUSE_OUTPUT(13); + EFUSE_OUTPUT(14); + EFUSE_OUTPUT(15); + EFUSE_OUTPUT(16); + EFUSE_OUTPUT(17); + EFUSE_OUTPUT(18); + EFUSE_OUTPUT(19); + EFUSE_OUTPUT(20); + EFUSE_OUTPUT(21); + EFUSE_OUTPUT(22); + EFUSE_OUTPUT(23); + EFUSE_OUTPUT(24); + EFUSE_OUTPUT(25); + EFUSE_OUTPUT(26); + EFUSE_OUTPUT(27); + EFUSE_OUTPUT(28); + EFUSE_OUTPUT(29); + EFUSE_OUTPUT(30); + EFUSE_OUTPUT(31); + EFUSE_OUTPUT(32); + EFUSE_OUTPUT(33); + EFUSE_OUTPUT(34); + EFUSE_OUTPUT(35); + EFUSE_OUTPUT(36); + EFUSE_OUTPUT(37); + EFUSE_OUTPUT(38); + EFUSE_OUTPUT(39); + EFUSE_OUTPUT(40); + EFUSE_OUTPUT(41); + EFUSE_OUTPUT(42); + EFUSE_OUTPUT(43); + EFUSE_OUTPUT(44); + EFUSE_OUTPUT(45); + EFUSE_OUTPUT(46); + EFUSE_OUTPUT(47); + EFUSE_OUTPUT(48); + EFUSE_OUTPUT(49); + EFUSE_OUTPUT(50); + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "flash0"; + spi-max-frequency = <50000000>; // 50 MHz +#include "openbmc-flash-layout.dtsi" + }; +}; + +&uart3 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@79 { + compatible = "nxp,pca9541"; + reg = <0x79>; + + i2carb0: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + /* lm25066 efuses @ 10-17, 40-47, 50-57 */ + EFUSE(10, 03); + EFUSE(11, 04); + EFUSE(12, 01); + EFUSE(13, 02); + EFUSE(14, 13); + EFUSE(15, 14); + EFUSE(16, 15); + EFUSE(17, 16); + EFUSE(40, 12); + EFUSE(41, 11); + EFUSE(42, 10); + EFUSE(43, 09); + EFUSE(44, 08); + EFUSE(45, 07); + EFUSE(46, 05); + EFUSE(47, 06); + EFUSE(50, 17); + EFUSE(51, 18); + EFUSE(52, 20); + EFUSE(53, 19); + EFUSE(54, 22); + EFUSE(55, 21); + EFUSE(56, 24); + EFUSE(57, 23); + }; + }; +}; + +&i2c1 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@72 { + compatible = "nxp,pca9541"; + reg = <0x72>; + + i2carb1: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c2 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@73 { + compatible = "nxp,pca9541"; + reg = <0x73>; + + i2carb2: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c3 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@74 { + compatible = "nxp,pca9541"; + reg = <0x74>; + + i2carb3: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c4 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@7a { + compatible = "nxp,pca9541"; + reg = <0x7a>; + + i2carb4: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* lm25066 efuses @ 10-17, 40-47, 50-57, 59, 5a */ + EFUSE(10, 27); + EFUSE(11, 28); + EFUSE(12, 25); + EFUSE(13, 26); + EFUSE(14, 37); + EFUSE(15, 38); + EFUSE(16, 39); + EFUSE(17, 40); + EFUSE(40, 36); + EFUSE(41, 35); + EFUSE(42, 34); + EFUSE(43, 33); + EFUSE(44, 32); + EFUSE(45, 31); + EFUSE(46, 29); + EFUSE(47, 30); + EFUSE(50, 41); + EFUSE(51, 42); + EFUSE(52, 44); + EFUSE(53, 43); + EFUSE(54, 46); + EFUSE(55, 45); + EFUSE(56, 48); + EFUSE(57, 47); + EFUSE(59, 49); + EFUSE(5a, 50); + }; + }; +}; + +&i2c6 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@75 { + compatible = "nxp,pca9541"; + reg = <0x75>; + + i2carb6: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c7 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@76 { + compatible = "nxp,pca9541"; + reg = <0x76>; + + i2carb7: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c8 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@7c { + compatible = "nxp,pca9541"; + reg = <0x7c>; + + i2carb8: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + fancontrol@30 { + compatible = "delta,ahe50dc-fan"; + reg = <0x30>; + }; + + /* Baseboard FRU eeprom */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + }; +}; + +&i2c12 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@71 { + compatible = "nxp,pca9541"; + reg = <0x71>; + + i2carb12: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "", "", "", "", "", "", "", "", + /* B */ "", "", "", "", "", "", "", "", + /* C */ "RESET_PEER_N", "HEARTBEAT_OUT", "", "", "", "", "", "", + /* D */ "", "", "", "", "", "", "", "", + /* E */ "DOOM_N", "", "", "", "", "LED_PWR_BLUE", "", "", + /* F */ "", "", "", "", "", "", "", "", + /* G */ "", "", "", "", "", "", "", "", + /* H */ "", "", "", "", "", "", "", "", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "", "", "BMC_ID", "", "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "", "", "", "", "", "", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "LED_GREEN", "", "LED_RED", "", "", "", "", "", + /* Q */ "", "", "", "", "", "", "", "", + /* R */ "", "", "", "", "", "", "", "", + /* S */ "", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "HEARTBEAT_IN", "BOARDREV0", "BOARDREV1", "", + /* Z */ "", "", "", "", "", "", "", "", + /* AA */ "", "", "", "", "", "", "", "", + /* AB */ "", "", "", ""; + + /* + * I don't rightly know what this GPIO really *is*, but setting it to + * zero causes the fans to run at full speed, after which setting it + * back to one causes a power output glitch, so install a hog to keep + * it at one as a failsafe to ensure nothing accidentally touches it. + */ + doom-guardrail { + gpio-hog; + gpios = ; + output-low; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts new file mode 100644 index 000000000000..e899de681f47 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -0,0 +1,1077 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Facebook Bletchley BMC"; + compatible = "facebook,bletchley-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + bootargs = "console=ttyS4,57600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + spi1_gpio: spi1-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; + + switchphy: ethernet-phy@0 { + // Fixed link + }; + + front_gpio_leds { + compatible = "gpio-leds"; + sys_log_id { + default-state = "off"; + gpios = <&front_leds 0 GPIO_ACTIVE_LOW>; + }; + }; + + fan_gpio_leds { + compatible = "gpio-leds"; + fan0_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>; + }; + fan1_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>; + }; + fan2_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>; + }; + fan3_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>; + }; + fan0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>; + }; + fan1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>; + }; + fan2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>; + }; + fan3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>; + }; + }; + + sled1_gpio_leds { + compatible = "gpio-leds"; + sled1_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; + }; + sled1_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; + }; + }; + + sled2_gpio_leds { + compatible = "gpio-leds"; + sled2_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; + }; + sled2_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; + }; + }; + + sled3_gpio_leds { + compatible = "gpio-leds"; + sled3_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; + }; + sled3_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; + }; + }; + + sled4_gpio_leds { + compatible = "gpio-leds"; + sled4_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; + }; + sled4_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; + }; + }; + + sled5_gpio_leds { + compatible = "gpio-leds"; + sled5_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; + }; + sled5_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; + }; + }; + + sled6_gpio_leds { + compatible = "gpio-leds"; + sled6_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>; + }; + sled6_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + presence-sled1 { + label = "presence-sled1"; + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + presence-sled2 { + label = "presence-sled2"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + presence-sled3 { + label = "presence-sled3"; + gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + presence-sled4 { + label = "presence-sled4"; + gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + presence-sled5 { + label = "presence-sled5"; + gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + presence-sled6 { + label = "presence-sled6"; + gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + vbus_sled1: vbus_sled1 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled1_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled2: vbus_sled2 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled2_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled3: vbus_sled3 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled3_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled4: vbus_sled4 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled4"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled4_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled5: vbus_sled5 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled5"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled5_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled6: vbus_sled6 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled6"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled6_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&mac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&switchphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <50000000>; + }; +}; + +&i2c0 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled1_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED1_SWD_MUX", "SLED1_XRES_SWD_N", + "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN"; + }; + + sled1_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", + "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", + "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", + "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; + }; + + sled1_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","SLED1_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled1_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + interrupt-parent = <&gpio0>; + interrupts = ; + vbus-supply = <&vbus_sled1>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c1 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled2_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED2_SWD_MUX", "SLED2_XRES_SWD_N", + "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN"; + }; + + sled2_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", + "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", + "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", + "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; + }; + + sled2_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","SLED2_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled2_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + interrupt-parent = <&gpio0>; + interrupts = ; + vbus-supply = <&vbus_sled2>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c2 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled3_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED3_SWD_MUX", "SLED3_XRES_SWD_N", + "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN"; + }; + + sled3_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", + "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", + "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", + "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; + }; + + sled3_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","SLED3_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled3_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + interrupt-parent = <&gpio0>; + interrupts = ; + vbus-supply = <&vbus_sled3>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c3 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled4_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED4_SWD_MUX", "SLED4_XRES_SWD_N", + "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN"; + }; + + sled4_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", + "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", + "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", + "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; + }; + + sled4_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","SLED4_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled4_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + interrupt-parent = <&gpio0>; + interrupts = ; + vbus-supply = <&vbus_sled4>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c4 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled5_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED5_SWD_MUX", "SLED5_XRES_SWD_N", + "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN"; + }; + + sled5_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", + "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", + "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", + "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; + }; + + sled5_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","SLED5_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled5_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + interrupt-parent = <&gpio0>; + interrupts = ; + vbus-supply = <&vbus_sled5>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c5 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled6_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED6_SWD_MUX", "SLED6_XRES_SWD_N", + "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN"; + }; + + sled6_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED6_MS_DETECT1","SLED6_VBUS_BMC_EN","SLED6_INA230_ALERT","SLED6_P12V_STBY_ALERT", + "SLED6_SSD_ALERT","SLED6_MS_DETECT0","SLED6_RST_CCG5","SLED6_FUSB302_INT", + "SLED6_MD_STBY_RESET","SLED6_MD_IOEXP_EN_FAULT","SLED6_MD_DIR","SLED6_MD_DECAY", + "SLED6_MD_MODE1","SLED6_MD_MODE2","SLED6_MD_MODE3","power-host6"; + }; + + sled6_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled6-amber","led-sled6-blue","SLED6_RST_IOEXP","SLED6_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled6_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + interrupt-parent = <&gpio0>; + interrupts = ; + vbus-supply = <&vbus_sled6>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c6 { + status = "okay"; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; + + rtc@51 { + /* in-chip rtc disabled, use external rtc (battery-backed) */ + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c9 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + front_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-fault-identify","power-p5v-stby-good", + "power-p1v0-dvdd-good","power-p1v0-avdd-good", + "","","","", + "","","","", + "","","",""; + }; +}; + +&i2c12 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + shunt-resistor-micro-ohms = <300>; + adi,volt-curr-sample-average = <128>; + adi,power-sample-average = <128>; + }; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tmp421@4d { + compatible = "ti,tmp421"; + reg = <0x4d>; + }; + + fan_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-fan0","presence-fan1", + "presence-fan2","presence-fan3", + "power-fan0-good","power-fan1-good", + "power-fan2-good","power-fan3-good", + "","","","", + "","","",""; + }; +}; + +&i2c13 { + multi-master; + aspeed,hw-timeout-ms = <1000>; + status = "okay"; + + //USB Debug Connector + ipmb13@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiov2_unbiased_default>; + + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N", + "SEL_SPI2_MUX","SPI2_MUX1", + "SPI2_MUX2","SPI2_MUX3", + "","FUSB302_SLED3_INT_N", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK", + "BMC_SLED3_STCK","BMC_SLED4_STCK", + "BMC_SLED5_STCK","BMC_SLED6_STCK", + "","", + /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL", + "PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","", + /*H0-H7*/ "presence-riser1","presence-riser2", + "presence-sled1","presence-sled2", + "presence-sled3","presence-sled4", + "presence-sled5","presence-sled6", + /*I0-I7*/ "REV_ID0","", + "REV_ID1","REV_ID2", + "","BSM_FLASH_WP_STATUS", + "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","BMC_RTC_INT","","", + /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N", + "ALERT_SLED3_N","ALERT_SLED4_N", + "ALERT_SLED5_N","ALERT_SLED6_N", + "","USB_DEBUG_PWR_BTN_N", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", + "LED_POSTCODE_2","LED_POSTCODE_3", + "LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_6","LED_POSTCODE_7", + /*O0-O7*/ "","","","", + "","BOARD_ID0","BOARD_ID1","BOARD_ID2", + /*P0-P7*/ "","","","","","","","BMC_HEARTBEAT", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","BAT_DETECT", + "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N", + "P12V_AUX_ALERT1_N","PSU_PRSNT", + "USB2_SEL0_A","USB2_SEL1_A", + "USB2_SEL0_B","USB2_SEL1_B", + /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N", + "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N", + "","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&adc0 { + vref = <1800>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&mdio0 { + status = "okay"; + /* TODO: Add Marvell 88E6191X */ +}; + +&mdio3 { + status = "okay"; + /* TODO: Add Marvell 88X3310 */ +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&pinctrl { + pinctrl_gpiov2_unbiased_default: gpiov2 { + pins = "AD14"; + bias-disable; + }; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts new file mode 100644 index 000000000000..5cd060029ea9 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts @@ -0,0 +1,544 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +/dts-v1/; + +#include +#include "ast2600-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Cloudripper BMC"; + compatible = "facebook,cloudripper-bmc", "aspeed,ast2600"; + + aliases { + /* + * PCA9548 (1-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (3-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * PDB (Power Delivery Board). + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + + /* + * PCA9548 (15-0076) provides 8 channels connecting to + * FCM (Fan Controller Module). + */ + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + }; + + spi_gpio: spi { + num-chipselects = <2>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, + <&gpio0 ASPEED_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + + eeprom@1 { + compatible = "atmel,at93c46d"; + spi-max-frequency = <250000>; + data-size = <16>; + spi-cs-high; + reg = <1>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +/* + * "mdio1" is connected to the MDC/MDIO interface of the on-board + * management switch (whose ports are connected to BMC, Host and front + * panel ethernet port). + */ +&mdio1 { + status = "okay"; +}; + +&mdio3 { + status = "okay"; + + ethphy1: ethernet-phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0d>; + }; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&i2c0 { + multi-master; + bus-frequency = <1000000>; +}; + +&i2c1 { + /* + * PCA9548 (1-0070) provides 8 channels connecting to SMB (Switch + * Main Board). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + /* + * PCA9548 (2-0070) provides 8 channels connecting to SCM (System + * Controller Module). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + /* + * PCA9548 (3-0070) provides 8 channels connecting to SMB (Switch + * Main Board). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c6 { + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "sys"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "fan"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "psu"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "scm"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + }; +}; + +&i2c8 { + /* + * PCA9548 (8-0070) provides 8 channels connecting to PDB (Power + * Delivery Board). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c15 { + /* + * PCA9548 (15-0076) provides 8 channels connecting to FCM (Fan + * Controller Module). + */ + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts new file mode 100644 index 000000000000..90a3f485c67a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts @@ -0,0 +1,1590 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Backpack CMM BMC"; + compatible = "facebook,cmm-bmc", "aspeed,ast2500"; + + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + + /* + * PCA9548 (1-0077) provides 8 channels for connecting to + * 4 Line Cards and 4 Fabric Cards. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (2-0071) provides 8 channels for connecting to + * Power Distribution Board. + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (8-0077) provides 8 channels and the first 4 + * channels are connecting to 4 Fan Control Boards. + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + /* + * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting + * to Line Card #1. + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting + * to Line Card #2. + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting + * to Line Card #3. + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * 2 PCA9548 (21-0070 & 21-0073), 16 channels connecting + * to Line Card #4. + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * 2 PCA9548 (16-0070 & 16-0073), 16 channels connecting + * to Fabric Card #1. + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * 2 PCA9548 (17-0070 & 17-0073), 16 channels connecting + * to Fabric Card #2. + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * 2 PCA9548 (22-0070 & 22-0073), 16 channels connecting + * to Fabric Card #3. + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; + i2c144 = &imux144; + i2c145 = &imux145; + i2c146 = &imux146; + i2c147 = &imux147; + i2c148 = &imux148; + i2c149 = &imux149; + i2c150 = &imux150; + i2c151 = &imux151; + + /* + * 2 PCA9548 (23-0070 & 23-0073), 16 channels connecting + * to Fabric Card #4. + */ + i2c152 = &imux152; + i2c153 = &imux153; + i2c154 = &imux154; + i2c155 = &imux155; + i2c156 = &imux156; + i2c157 = &imux157; + i2c158 = &imux158; + i2c159 = &imux159; + i2c160 = &imux160; + i2c161 = &imux161; + i2c162 = &imux162; + i2c163 = &imux163; + i2c164 = &imux164; + i2c165 = &imux165; + i2c166 = &imux166; + i2c167 = &imux167; + + /* + * PCA9548 (32-0070), 8 channels connecting to Fan Control + # Board #1. + */ + i2c168 = &imux168; + i2c169 = &imux169; + i2c170 = &imux170; + i2c171 = &imux171; + i2c172 = &imux172; + i2c173 = &imux173; + i2c174 = &imux174; + i2c175 = &imux175; + + /* + * PCA9548 (33-0070), 8 channels connecting to Fan Control + # Board #2. + */ + i2c176 = &imux176; + i2c177 = &imux177; + i2c178 = &imux178; + i2c179 = &imux179; + i2c180 = &imux180; + i2c181 = &imux181; + i2c182 = &imux182; + i2c183 = &imux183; + + /* + * PCA9548 (34-0070), 8 channels connecting to Fan Control + # Board #3. + */ + i2c184 = &imux184; + i2c185 = &imux185; + i2c186 = &imux186; + i2c187 = &imux187; + i2c188 = &imux188; + i2c189 = &imux189; + i2c190 = &imux190; + i2c191 = &imux191; + + /* + * PCA9548 (35-0070), 8 channels connecting to Fan Control + # Board #4. + */ + i2c192 = &imux192; + i2c193 = &imux193; + i2c194 = &imux194; + i2c195 = &imux195; + i2c196 = &imux196; + i2c197 = &imux197; + i2c198 = &imux198; + i2c199 = &imux199; + }; + + chosen { + stdout-path = &uart1; + bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_ndsr1_default + &pinctrl_ndtr1_default + &pinctrl_nrts1_default>; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default + &pinctrl_ncts3_default + &pinctrl_ndcd3_default + &pinctrl_nri3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* + * I2C bus reserved for communication with COM-E. + */ +&i2c0 { + status = "okay"; +}; + +/* + * I2C bus to Line Cards and Fabric Cards. + */ +&i2c1 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + /* To Fabric Card #1 */ + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Fabric Card #2 */ + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Line Card #1 */ + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Line Card #2 */ + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To LC3 SCM */ + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Line Card #4 */ + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Fabric Card #3 */ + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux144: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux145: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux146: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux147: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux148: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux149: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux150: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux151: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Fabric Card #4 */ + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux152: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux153: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux154: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux155: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux156: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux157: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux158: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux159: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux160: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux161: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux162: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux163: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux164: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux165: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux166: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux167: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + }; +}; + +/* + * I2C bus to Power Distribution Board. + */ +&i2c2 { + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +/* + * I2c bus connected with temperature sensors on CMM. + */ +&i2c3 { + status = "okay"; +}; + +/* + * I2C bus reserved for communication with COM-E. + */ +&i2c4 { + status = "okay"; +}; + +/* + * I2c bus connected with ADM1278. + */ +&i2c5 { + status = "okay"; +}; + +/* + * I2c bus connected with I/O Expander. + */ +&i2c6 { + status = "okay"; +}; + +/* + * I2c bus connected with I/O Expander and EPROMs. + */ +&i2c7 { + status = "okay"; +}; + +/* + * I2C bus to Fan Control Boards. + */ +&i2c8 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + /* To Fan Control Board #1 */ + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux168: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux169: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux170: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux171: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux172: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux173: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux174: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux175: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Fan Control Board #2 */ + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux176: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux177: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux178: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux179: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux180: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux181: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux182: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux183: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Fan Control Board #3 */ + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux184: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux185: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux186: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux187: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux188: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux189: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux190: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux191: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* To Fan Control Board #4 */ + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux192: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux193: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux194: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux195: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux196: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux197: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux198: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux199: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +/* + * I2C bus to CMM CPLD. + */ +&i2c13 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&vhub { + status = "disabled"; +}; + +&sdhci0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_default>; +}; + +&sdhci1 { + status = "disabled"; +}; + +&fmc_flash0 { +#include "facebook-bmc-flash-layout.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts new file mode 100644 index 000000000000..b5cd4c7800b0 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +/dts-v1/; + +#include "ast2600-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Elbert BMC"; + compatible = "facebook,elbert-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + + /* + * 8 child channels of PCA9548 2-0075. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * 8 child channels of PCA9548 5-0075. + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + }; + + chosen { + stdout-path = &uart5; + }; + + spi_gpio: spi { + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; + }; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&i2c2 { + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c5 { + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c11 { + status = "okay"; +}; + +/* + * BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port + * directly (fixed link, no PHY in between). + * Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO + * interface, and the MDIO channel will be enabled in dts later, when + * BCM53134 is added to "bcm53xx" DSA driver. + */ +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts new file mode 100644 index 000000000000..6b319f34a9b9 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts @@ -0,0 +1,1251 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +/dts-v1/; + +#include +#include "ast2600-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Fuji BMC"; + compatible = "facebook,fuji-bmc", "aspeed,ast2600"; + + aliases { + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (11-0077) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + + /* + * PCA9548 (24-0071) provides 8 channels connecting to + * PDB-Left. + */ + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * PCA9548 (25-0072) provides 8 channels connecting to + * PDB-Right. + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + + /* + * PCA9548 (26-0076) provides 8 channels connecting to + * FCM1. + */ + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * PCA9548 (27-0076) provides 8 channels connecting to + * FCM2. + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + + /* + * PCA9548 (40-0076) provides 8 channels connecting to + * PIM1. + */ + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * PCA9548 (41-0076) provides 8 channels connecting to + * PIM2. + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + + /* + * PCA9548 (42-0076) provides 8 channels connecting to + * PIM3. + */ + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * PCA9548 (43-0076) provides 8 channels connecting to + * PIM4. + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + + /* + * PCA9548 (44-0076) provides 8 channels connecting to + * PIM5. + */ + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * PCA9548 (45-0076) provides 8 channels connecting to + * PIM6. + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + + /* + * PCA9548 (46-0076) provides 8 channels connecting to + * PIM7. + */ + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * PCA9548 (47-0076) provides 8 channels connecting to + * PIM8. + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; + }; + + spi_gpio: spi { + num-chipselects = <3>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, + <0>, /* device reg=<1> does not exist */ + <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_HIGH>; + + eeprom@2 { + compatible = "atmel,at93c46d"; + spi-max-frequency = <250000>; + data-size = <16>; + spi-cs-high; + reg = <2>; + }; + }; +}; + +&i2c0 { + multi-master; + bus-frequency = <1000000>; +}; + +&i2c2 { + /* + * PCA9548 (2-0070) provides 8 channels connecting to SCM (System + * Controller Module). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + shunt-resistor-micro-ohms = <1500>; + }; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c8 { + /* + * PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch + * Main Board). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "sys"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "fan"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "psu"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "smb"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + }; + }; + + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-switch@72 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + shunt-resistor-micro-ohms = <250>; + }; + }; + + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + shunt-resistor-micro-ohms = <250>; + }; + }; + + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c11 { + status = "okay"; + + /* + * PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch + * Main Board). + */ + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + }; +}; + +&ehci1 { + status = "okay"; +}; + +&mdio1 { + status = "okay"; + + ethphy3: ethernet-phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0d>; + }; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts new file mode 100644 index 000000000000..60e875ac2461 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. +/dts-v1/; + +#include "ast2400-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Galaxy 100 BMC"; + compatible = "facebook,galaxy100-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 3>, <&adc 4>, <&adc 8>, <&adc 9>; + }; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; + }; +}; + + +&i2c9 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts new file mode 100644 index 000000000000..7a53f54833a0 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Facebook Greatlakes BMC"; + compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 2>, <&adc1 3>, <&adc1 4>, + <&adc1 5>, <&adc1 6>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + no-hw-checksum; + use-ncsi; + mlx,multi-host; + ncsi-ctrl,start-redo-probe; + ncsi-ctrl,no-channel-monitor; + ncsi-package = <1>; + ncsi-channel = <1>; + ncsi-rexmit = <1>; + ncsi-timeout = <2>; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + }; +}; + +&i2c0 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c1 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c2 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + mctp-controller; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + // NIC EEPROM + eeprom@50 { + compatible = "st,24c32"; + reg = <0x50>; + }; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c9 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c12 { + status = "okay"; + temperature-sensor@4f { + compatible = "lm75"; + reg = <0x4f>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default + &pinctrl_adc11_default &pinctrl_adc12_default + &pinctrl_adc13_default &pinctrl_adc14_default>; +}; + + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; + + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug", + "power-bmc-slot1","power-bmc-slot2", + "power-bmc-slot3","power-bmc-slot4","","", + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary", + "reset-cause-nic-secondary","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button", + "slot3-bmc-reset-button","slot4-bmc-reset-button", + "","","","presence-emmc", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","", + "presence-mb-slot1","presence-mb-slot2", + "presence-mb-slot3","presence-mb-slot4", + /*I0-I7*/ "","","","","","","bb-bmc-button","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","", + /*N0-N7*/ "","","","","bmc-ready","","","", + /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable", + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable", + "reset-cause-pcie-slot1","reset-cause-pcie-slot2", + "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","GND", + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button", + "bmc-slot3-ac-button","bmc-slot4-ac-button", + "","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","","", + /*18C0-18C7*/ "","","","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","","","","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts new file mode 100644 index 000000000000..230d16cd9967 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts @@ -0,0 +1,1339 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Minipack 100 BMC"; + compatible = "facebook,minipack-bmc", "aspeed,ast2500"; + + aliases { + /* + * Override the default serial aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + + /* + * i2c switch 2-0070, pca9548, 8 child channels assigned + * with bus number 16-23. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * i2c switch 8-0070, pca9548, 8 child channels assigned + * with bus number 24-31. + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * i2c switch 9-0070, pca9548, 8 child channels assigned + * with bus number 32-39. + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + /* + * i2c switch 11-0070, pca9548, 8 child channels assigned + * with bus number 40-47. + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + + /* + * I2C Switch 24-0071 (channel #0 of 8-0070): 8 channels for + * connecting to left PDB (Power Distribution Board). + */ + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * I2C Switch 25-0072 (channel #1 of 8-0070): 8 channels for + * connecting to right PDB (Power Distribution Board). + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + + /* + * I2C Switch 26-0076 (channel #2 of 8-0070): 8 channels for + * connecting to top FCM (Fan Control Module). + */ + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * I2C Switch 27-0076 (channel #3 of 8-0070): 8 channels for + * connecting to bottom FCM (Fan Control Module). + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + + /* + * I2C Switch 40-0073 (channel #0 of 11-0070): connecting + * to PIM (Port Interface Module) #1 (1-based). + */ + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * I2C Switch 41-0073 (channel #1 of 11-0070): connecting + * to PIM (Port Interface Module) #2 (1-based). + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + + /* + * I2C Switch 42-0073 (channel #2 of 11-0070): connecting + * to PIM (Port Interface Module) #3 (1-based). + */ + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * I2C Switch 43-0073 (channel #3 of 11-0070): connecting + * to PIM (Port Interface Module) #4 (1-based). + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + + /* + * I2C Switch 44-0073 (channel #4 of 11-0070): connecting + * to PIM (Port Interface Module) #5 (1-based). + */ + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * I2C Switch 45-0073 (channel #5 of 11-0070): connecting + * to PIM (Port Interface Module) #6 (1-based). + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + + /* + * I2C Switch 46-0073 (channel #6 of 11-0070): connecting + * to PIM (Port Interface Module) #7 (1-based). + */ + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * I2C Switch 47-0073 (channel #7 of 11-0070): connecting + * to PIM (Port Interface Module) #8 (1-based). + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; + }; + + chosen { + stdout-path = &uart1; + bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw"; + }; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +/* + * Both firmware flashes are 64MB on Minipack BMC. + */ +&fmc_flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 384KB. + */ + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + /* + * u-boot environment variables: 128KB. + */ + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + /* + * FIT image: 55.5 MB. + */ + fit@80000 { + reg = <0x80000 0x3780000>; + label = "fit"; + }; + + /* + * "data0" partition (8MB) is reserved for persistent + * data store. + */ + data0@3800000 { + reg = <0x3800000 0x800000>; + label = "data0"; + }; + + /* + * "flash0" partition (covering the entire flash) is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x4000000>; + label = "flash0"; + }; + }; +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x4000000>; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_ndsr1_default + &pinctrl_ndtr1_default + &pinctrl_nrts1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&i2c0 { + status = "okay"; + bus-frequency = <400000>; + multi-master; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* + * I2C Switch 2-0070 is connecting to SCM (System Controller + * Module). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + multi-master; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + /* + * I2C Switch 8-0070 channel #0: connecting to left PDB + * (Power Distribution Board). + */ + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 8-0070 channel #1: connecting to right PDB + * (Power Distribution Board). + */ + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-switch@72 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 8-0070 channel #2: connecting to top FCM + * (Fan Control Module). + */ + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 8-0070 channel #3: connecting to bottom + * FCM (Fan Control Module). + */ + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + /* + * I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB + * (Switch Main Board). + */ + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + /* + * I2C Switch 11-0070 channel #0: connecting to PIM + * (Port Interface Module) #1 (1-based). + */ + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #1: connecting to PIM + * (Port Interface Module) #2 (1-based). + */ + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #2: connecting to PIM + * (Port Interface Module) #3 (1-based). + */ + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #3: connecting to PIM + * (Port Interface Module) #4 (1-based). + */ + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #4: connecting to PIM + * (Port Interface Module) #5 (1-based). + */ + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #5: connecting to PIM + * (Port Interface Module) #6 (1-based). + */ + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #6: connecting to PIM + * (Port Interface Module) #7 (1-based). + */ + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + /* + * I2C Switch 11-0070 channel #7: connecting to PIM + * (Port Interface Module) #8 (1-based). + */ + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts new file mode 100644 index 000000000000..b6b16356f571 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +// Author: Vijay Khemka +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Facebook TiogaPass BMC"; + compatible = "facebook,tiogapass-bmc", "aspeed,ast2500"; + aliases { + serial0 = &uart1; + serial4 = &uart5; + + /* + * Hardcode the bus number of i2c switches' channels to + * avoid breaking the legacy applications. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + }; + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&lpc_ctrl { + // Enable lpc clock + status = "okay"; +}; + +&uart1 { + // Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + // SoL Host Console + status = "okay"; +}; + +&uart3 { + // SoL BMC Console + status = "okay"; +}; + +&uart5 { + // BMC Console + status = "okay"; +}; + +&kcs2 { + // BMC KCS channel 2 + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + // BMC KCS channel 3 + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", + /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", + "IRQ_PVDDQ_GHJ_VRHOT_LVT3", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", + "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", + "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", + "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", + "CPU1_PROCHOT_LVT3_ BMC", + /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", + "IRQ_PVCCIN_CPU0_VRHOT_LVC3", + "IRQ_PVCCIN_CPU1_VRHOT_LVC3", + "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", + /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", + "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", + /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", + "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", + "LED_POST_CODE_6","LED_POST_CODE_7", + /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", + "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", + "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", + /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", + "CPU0_THERMTRIP_LATCH_LVT3", + "CPU1_THERMTRIP_LATCH_LVT3","","", + /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", + "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", + "BMC_PWR_DEBUG","RST_RSMRST", + /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", + "POST_CARD_PRES_BMC","PE_BMC_WAKE", + /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", + "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", + "SLT_CFG1", + /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", + "","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","BMC_FAULT","","", + /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","GLOBAL_RST_WARN", + "CPU0_MEMABC_MEMHOT_LVT3_BMC", + "CPU0_MEMDEF_MEMHOT_LVT3_BMC", + "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", + "CPU1_MEMKLM_MEMHOT_LVT3_BMC", + /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", + "","","", + /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", + "","","","", + /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", + "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", + "","POST_COMPLETE", + /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii2_default>; + use-ncsi; +}; + +&adc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + //Airmax Conn B, CPU0 PIROM, CPU1 PIROM +}; + +&i2c1 { + status = "okay"; + //X24 Riser + i2c-switch@71 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + tmp75@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + tmp421@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + + imux20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + }; + + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + tmp421@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + tmp421@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + }; + + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + tmp421@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + tmp421@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + + imux28: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux29: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux30: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux31: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + }; + + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@40 { + compatible = "ti,ina230"; + reg = <0x40>; + }; + + i2c-switch@41 { + compatible = "ti,ina230"; + reg = <0x41>; + }; + + i2c-switch@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + }; + + }; +}; + +&i2c2 { + status = "okay"; + // Mezz Management SMBus +}; + +&i2c3 { + status = "okay"; + // SMBus to Board ID EEPROM +}; + +&i2c4 { + status = "okay"; + // BMC Debug Header + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c5 { + status = "okay"; + // CPU Voltage regulators + regulator@48 { + compatible = "infineon,pxe1610"; + reg = <0x48>; + }; + regulator@4a { + compatible = "infineon,pxe1610"; + reg = <0x4a>; + }; + regulator@50 { + compatible = "infineon,pxe1610"; + reg = <0x50>; + }; + regulator@52 { + compatible = "infineon,pxe1610"; + reg = <0x52>; + }; + regulator@58 { + compatible = "infineon,pxe1610"; + reg = <0x58>; + }; + regulator@5a { + compatible = "infineon,pxe1610"; + reg = <0x5a>; + }; + regulator@68 { + compatible = "infineon,pxe1610"; + reg = <0x68>; + }; + regulator@70 { + compatible = "infineon,pxe1610"; + reg = <0x70>; + }; + regulator@72 { + compatible = "infineon,pxe1610"; + reg = <0x72>; + }; +}; + +&i2c6 { + status = "okay"; + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2c7 { + status = "okay"; + //HSC, AirMax Conn A + adm1278@45 { + compatible = "adm1275"; + reg = <0x45>; + shunt-resistor-micro-ohms = <250>; + }; +}; + +&i2c8 { + status = "okay"; + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + //Mezz Sensor SMBus +}; + +&i2c9 { + status = "okay"; + //USB Debug Connector + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts new file mode 100644 index 000000000000..584efa528450 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "ast2400-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Wedge 100 BMC"; + compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; + }; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; + }; +}; + +&i2c7 { + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c9 { + status = "okay"; +}; + + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts new file mode 100644 index 000000000000..6624855d8ebd --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "ast2400-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Wedge 40 BMC"; + compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; + }; +}; + +&wdt2 { + status = "disabled"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts new file mode 100644 index 000000000000..ed305948386f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2019 Facebook Inc. +/dts-v1/; + +#include +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Wedge 400 BMC"; + compatible = "facebook,wedge400-bmc", "aspeed,ast2500"; + + aliases { + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (11-0076) provides 8 channels connecting to + * FCM (Fan Controller Module). + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + spi2 = &spi_gpio; + }; + + chosen { + stdout-path = &uart1; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + }; + + /* + * GPIO-based SPI Master is required to access SPI TPM, because + * full-duplex SPI transactions are not supported by ASPEED SPI + * Controllers. + */ + spi_gpio: spi { + status = "okay"; + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; + gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +/* + * Both firmware flashes are 128MB on Wedge400 BMC. + */ +&fmc_flash0 { +#include "facebook-bmc-flash-layout-128.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x8000000>; + label = "flash1"; + }; + }; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* + * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC + * communication. + */ +&i2c0 { + status = "okay"; + multi-master; + bus-frequency = <1000000>; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&sdhci1 { + /* + * DMA mode needs to be disabled to avoid conflicts with UHCI + * Controller in AST2500 SoC. + */ + sdhci-caps-mask = <0x0 0x580000>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts new file mode 100644 index 000000000000..5e6105874217 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook YAMP 100 BMC"; + compatible = "facebook,yamp-bmc", "aspeed,ast2500"; + + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&mac1 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&fmc_flash0 { +#include "facebook-bmc-flash-layout.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts new file mode 100644 index 000000000000..6bf2ff85a40e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Facebook Yosemitev2 BMC"; + compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500"; + aliases { + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + iio-hwmon { + // VOLATAGE SENSOR + compatible = "iio-hwmon"; + io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> , + <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> , + <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> , + <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; +&uart1 { + // Host1 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + // Host2 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; + +}; + +&uart3 { + // Host3 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + // Host4 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + // BMC Console + status = "okay"; +}; + +&vuart { + // Virtual UART + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; + mlx,multi-host; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&i2c1 { + //Host1 IPMB bus + status = "okay"; + multi-master; + ipmb1@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + //Host2 IPMB bus + status = "okay"; + multi-master; + ipmb3@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c5 { + //Host3 IPMB bus + status = "okay"; + multi-master; + ipmb5@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c7 { + //Host4 IPMB bus + status = "okay"; + multi-master; + ipmb7@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c8 { + status = "okay"; + //FRU EEPROM + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c9 { + status = "okay"; + tmp421@4e { + //INLET TEMP + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + //OUTLET TEMP + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + //HSC + adm1278@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c11 { + status = "okay"; + //MEZZ_TEMP_SENSOR + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + // Debug Card + multi-master; + ipmb13@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&pwm_tacho { + status = "okay"; + //FSC + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts new file mode 100644 index 000000000000..81902cbe662c --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts @@ -0,0 +1,915 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Bonnell"; + compatible = "ibm,bonnell-bmc", "aspeed,ast2600"; + + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + + serial4 = &uart5; + i2c16 = &i2c11mux0chn0; + i2c17 = &i2c11mux0chn1; + i2c18 = &i2c11mux0chn2; + i2c19 = &i2c11mux0chn3; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + no-map; + reg = <0xb4000000 0x04000000>; /* 64M */ + }; + + /* VGA region is dictated by hardware strapping */ + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + fan0 { + gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>; + }; + + fan1 { + gpios = <&gpio0 ASPEED_GPIO(G, 1) GPIO_ACTIVE_LOW>; + }; + + rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&gpio0 ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&gpio0 ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 7>; + }; +}; + +&adc1 { + status = "okay"; + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","checkstop","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","","", + /*G0-G7*/ "fan0","fan1","","","","","","", + /*H0-H7*/ "","","rear-enc-id0","rear-enc-fault0","","","","", + /*I0-I7*/ "","","","","","","bmc-secure-boot","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", + /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", + /*S0-S7*/ "presence-ps0","presence-ps1","","","power-ffs-sync-history","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; +}; + +&emmc_controller { + status = "okay"; +}; + +&pinctrl_emmc_default { + bias-disable; +}; + +&emmc { + status = "okay"; + clk-phase-mmc-hs200 = <180>, <180>; +}; + +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; /* OMI01 */ + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; /* OMI23 */ + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam0_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; /* OMI45 */ + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; /* OMI67 */ + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam1_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam1_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam1_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&ibt { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + tca9554@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", + "RUSSEL_FW_I2C_ENABLE_N", + "RUSSEL_OPPANEL_PRESENCE_N", + "BLYTH_OPPANEL_PRESENCE_N", + "CPU_TPM_CARD_PRESENT_N", + "", + "", + "DASD_BP_PRESENT_N"; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c3 { + status = "okay"; + + power-supply@5a { + compatible = "acbel,fsg032"; + reg = <0x5a>; + }; + + power-supply@5b { + compatible = "acbel,fsg032"; + reg = <0x5b>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + multi-master; + status = "okay"; + + si7021-a20@40 { + compatible = "silabs,si7020"; + reg = <0x40>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan0: fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan1: fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; +}; + +&i2c8 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", + "APSS_RESET_N", + "", + "N_MODE_CPU_N", + "", + "", + "P10_DCM_PRESENT", + ""; + }; +}; + +&i2c9 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + tca9554@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "BOOT_RCVRY_TWI", + "BOOT_RCVRY_UART", + "", + "", + "", + "", + "", + "PE_SWITCH_RSTB_N"; + }; + + tmp435@4c { + compatible = "ti,tmp435"; + reg = <0x4c>; + }; + + pca9849@75 { + compatible = "nxp,pca9849"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c11mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c11mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c11mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c11mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c12 { + status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c13 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts new file mode 100644 index 000000000000..c6f8f20914d1 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -0,0 +1,3723 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2020 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Everest"; + compatible = "ibm,everest-bmc", "aspeed,ast2600"; + + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + i2c300 = &cfam2_i2c0; + i2c301 = &cfam2_i2c1; + i2c310 = &cfam2_i2c10; + i2c311 = &cfam2_i2c11; + i2c312 = &cfam2_i2c12; + i2c313 = &cfam2_i2c13; + i2c314 = &cfam2_i2c14; + i2c315 = &cfam2_i2c15; + i2c402 = &cfam3_i2c2; + i2c403 = &cfam3_i2c3; + i2c410 = &cfam3_i2c10; + i2c411 = &cfam3_i2c11; + i2c414 = &cfam3_i2c14; + i2c415 = &cfam3_i2c15; + i2c416 = &cfam3_i2c16; + i2c417 = &cfam3_i2c17; + i2c500 = &cfam4_i2c0; + i2c501 = &cfam4_i2c1; + i2c510 = &cfam4_i2c10; + i2c511 = &cfam4_i2c11; + i2c512 = &cfam4_i2c12; + i2c513 = &cfam4_i2c13; + i2c514 = &cfam4_i2c14; + i2c515 = &cfam4_i2c15; + i2c602 = &cfam5_i2c2; + i2c603 = &cfam5_i2c3; + i2c610 = &cfam5_i2c10; + i2c611 = &cfam5_i2c11; + i2c614 = &cfam5_i2c14; + i2c615 = &cfam5_i2c15; + i2c616 = &cfam5_i2c16; + i2c617 = &cfam5_i2c17; + i2c700 = &cfam6_i2c0; + i2c701 = &cfam6_i2c1; + i2c710 = &cfam6_i2c10; + i2c711 = &cfam6_i2c11; + i2c712 = &cfam6_i2c12; + i2c713 = &cfam6_i2c13; + i2c714 = &cfam6_i2c14; + i2c715 = &cfam6_i2c15; + i2c802 = &cfam7_i2c2; + i2c803 = &cfam7_i2c3; + i2c810 = &cfam7_i2c10; + i2c811 = &cfam7_i2c11; + i2c814 = &cfam7_i2c14; + i2c815 = &cfam7_i2c15; + i2c816 = &cfam7_i2c16; + i2c817 = &cfam7_i2c17; + + i2c16 = &i2c4mux0chn0; + i2c17 = &i2c4mux0chn1; + i2c18 = &i2c4mux0chn2; + i2c19 = &i2c5mux0chn0; + i2c20 = &i2c5mux0chn1; + i2c21 = &i2c5mux0chn2; + i2c22 = &i2c5mux0chn3; + i2c23 = &i2c6mux0chn0; + i2c24 = &i2c6mux0chn1; + i2c25 = &i2c6mux0chn2; + i2c26 = &i2c6mux0chn3; + i2c27 = &i2c14mux0chn0; + i2c28 = &i2c14mux0chn1; + i2c29 = &i2c14mux0chn2; + i2c30 = &i2c14mux0chn3; + i2c31 = &i2c14mux1chn0; + i2c32 = &i2c14mux1chn1; + i2c33 = &i2c14mux1chn2; + i2c34 = &i2c14mux1chn3; + i2c35 = &i2c15mux0chn0; + i2c36 = &i2c15mux0chn1; + i2c37 = &i2c15mux0chn2; + i2c38 = &i2c15mux0chn3; + i2c39 = &i2c15mux1chn0; + i2c40 = &i2c15mux1chn1; + i2c41 = &i2c15mux1chn2; + i2c42 = &i2c15mux1chn3; + i2c43 = &i2c15mux2chn0; + i2c44 = &i2c15mux2chn1; + i2c45 = &i2c15mux2chn2; + i2c46 = &i2c15mux2chn3; + i2c47 = &i2c8mux0chn0; + i2c48 = &i2c8mux0chn1; + + serial4 = &uart5; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + spi30 = &cfam2_spi0; + spi31 = &cfam2_spi1; + spi32 = &cfam2_spi2; + spi33 = &cfam2_spi3; + spi40 = &cfam3_spi0; + spi41 = &cfam3_spi1; + spi42 = &cfam3_spi2; + spi43 = &cfam3_spi3; + spi50 = &cfam4_spi0; + spi51 = &cfam4_spi1; + spi52 = &cfam4_spi2; + spi53 = &cfam4_spi3; + spi60 = &cfam5_spi0; + spi61 = &cfam5_spi1; + spi62 = &cfam5_spi2; + spi63 = &cfam5_spi3; + spi70 = &cfam6_spi0; + spi71 = &cfam6_spi1; + spi72 = &cfam6_spi2; + spi73 = &cfam6_spi3; + spi80 = &cfam7_spi0; + spi81 = &cfam7_spi1; + spi82 = &cfam7_spi2; + spi83 = &cfam7_spi3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + event_log: tcg_event_log@b3d00000 { + no-map; + reg = <0xb3d00000 0x100000>; + }; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + no-map; + reg = <0xb4000000 0x04000000>; /* 64M */ + }; + + /* VGA region is dictated by hardware strapping */ + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 15 GPIO_ACTIVE_LOW>; + linux,code = <15>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* RTC battery fault LED at the back */ + led-rtc-battery { + gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; + }; + + /* BMC Card fault LED at the back */ + led-bmc { + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure Identify LED at the back */ + led-rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure fault LED at the back */ + led-rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + + /* PCIE slot power LED */ + led-pcieslot-power { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 7>; + }; +}; + +&adc1 { + status = "okay"; + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","checkstop","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", + /*I0-I7*/ "","","","","","","bmc-secure-boot","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", + /*P0-P7*/ "","","","","led-pcieslot-power","","","", + /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", + /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", + /*S0-S7*/ "","","","","power-ffs-sync-history","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca1: pca9552@62 { + compatible = "nxp,pca9552"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-ps0", + "presence-ps1", + "presence-ps2", + "presence-ps3", + "presence-pdb", + "presence-tpm", + "", "", + "presence-cp0", + "presence-cp1", + "presence-cp2", + "presence-cp3", + "presence-dasd", + "presence-lcd-op", + "presence-base-op", + ""; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + + power-supply@68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; + + power-supply@6d { + compatible = "ibm,cffps"; + reg = <0x6d>; + }; +}; + +&i2c4 { + status = "okay"; + + pca2: pca9552@65 { + compatible = "nxp,pca9552"; + reg = <0x65>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-cable-card1", + "presence-cable-card2", + "presence-cable-card3", + "presence-cable-card4", + "presence-cable-card5", + "expander-cable-card1", + "expander-cable-card2", + "expander-cable-card3", + "expander-cable-card4", + "expander-cable-card5"; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c4mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c01: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c01-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c01-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c4mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c02: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c02-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c02-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c4mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca_cable_card_c03: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c03-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c03-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + pca3: pca9552@66 { + compatible = "nxp,pca9552"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-cable-card6", + "presence-cable-card7", + "presence-cable-card8", + "presence-cable-card9", + "presence-cable-card10", + "presence-cable-card11", + "expander-cable-card6", + "expander-cable-card7", + "expander-cable-card8", + "expander-cable-card9", + "expander-cable-card10", + "expander-cable-card11"; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c5mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c04: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c04-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c04-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c5mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca_cable_card_c05: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c05-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c05-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c5mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c06: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c06-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c06-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c5mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + + pca_cable_card_c07: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c07-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c07-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c6mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c08: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c08-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c08-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c6mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c09: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c09-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c09-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c6mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + + pca_cable_card_c10: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c10-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c10-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c6mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca_cable_card_c11: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c11-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c11-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + }; + + pca_pcie_slot: pca9552@65 { + compatible = "nxp,pca9552"; + reg = <0x65>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@1 { + label = "pcieslot-c01"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "pcieslot-c02"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "pcieslot-c03"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "pcieslot-c04"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "pcieslot-c05"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "pcieslot-c06"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "pcieslot-c07"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "pcieslot-c08"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "pcieslot-c09"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "pcieslot-c10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "pcieslot-c11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; +}; + +&i2c7 { + status = "okay"; + + pic0_dimm: pca9552@31 { + compatible = "ibm,pca9552"; + reg = <0x31>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic1_dimm: pca9552@32 { + compatible = "ibm,pca9552"; + reg = <0x32>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm16"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm17"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm18"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm19"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm20"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm21"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm22"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm23"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm24"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm25"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm26"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm27"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm28"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm29"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm30"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm31"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic2_dimm: pca9552@33 { + compatible = "ibm,pca9552"; + reg = <0x33>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm32"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm33"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm34"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm35"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm36"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm37"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm38"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm39"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm40"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm41"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm42"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm43"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm44"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm45"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm46"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm47"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic3_dimm: pca9552@30 { + compatible = "ibm,pca9552"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm48"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm49"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm50"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm51"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm52"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm53"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm54"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm55"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm56"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm57"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm58"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm59"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm60"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm61"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm62"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm63"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic0_vrm_misc: pca9552@34 { + compatible = "ibm,pca9552"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "planar"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "tpm"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "cpu3-c61"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "cpu0-c14"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "opencapi-connector3"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "opencapi-connector4"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "opencapi-connector5"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "vrm4"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "vrm5"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "vrm6"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "vrm7"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "vrm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "vrm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "vrm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "vrm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic1_vrm_misc: pca9552@35 { + compatible = "ibm,pca9552"; + reg = <0x35>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "dasd-backplane"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "power-distribution"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "cpu1-c19"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "cpu2-c56"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "opencapi-connector0"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "opencapi-connector1"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "opencapi-connector2"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "vrm0"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "vrm1"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "vrm2"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "vrm3"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "vrm8"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "vrm9"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "vrm10"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "vrm11"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; +}; + +&i2c8 { + status = "okay"; + + ucd90320@11 { + compatible = "ti,ucd90320"; + reg = <0x11>; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c8mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c8mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c11 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c12 { + status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + memory-region = <&event_log>; + }; +}; + +&i2c13 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c14 { + multi-master; + status = "okay"; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + idle-state = <1>; + + i2c14mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c14mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + }; + }; + + i2c14mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + pca_oppanel: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c14mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + max31785@52 { + compatible = "maxim,max31785a"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x52>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + }; + }; + + pca_fan_nvme: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "nvme4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "nvme5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "nvme6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "nvme7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "nvme8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "nvme9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "fan0"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "fan1"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "fan2"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "fan3"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pca0: pca9552@61 { + compatible = "nxp,pca9552"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x61>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","","","", + "","","","", + "","","","", + "presence-fan3", + "presence-fan2", + "presence-fan1", + "presence-fan0"; + }; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c14mux1chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c14mux1chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c14mux1chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c14mux1chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; +}; + +&i2c15 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c15mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c15mux1chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux1chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux1chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux1chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + }; + + i2c-switch@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c15mux2chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux2chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c15mux2chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c15mux2chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&emmc_controller { + status = "okay"; +}; + +&pinctrl_emmc_default { + bias-disable; +}; + +&emmc { + status = "okay"; + clk-phase-mmc-hs200 = <210>, <228>; +}; + +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + /* + * CFAM Reset is supposed to be active low but pass1 hardware is wired + * active high. + */ + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + + cfam@0,0 { /* DCM0_C0 */ + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; /* OMI01 */ + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; /* OMI23 */ + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam0_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { /* DCM0_C1 */ + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; /* OMI45 */ + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; /* OMI67 */ + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam1_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam1_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam1_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@2,0 { /* DCM1_C0 */ + reg = <2 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <2>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_i2c0: i2c-bus@0 { + reg = <0>; /* OM01 */ + }; + + cfam2_i2c1: i2c-bus@1 { + reg = <1>; /* OM23 */ + }; + + cfam2_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam2_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam2_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam2_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam2_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam2_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ2: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub2: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@3,0 { /* DCM1_C1 */ + reg = <3 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <3>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_i2c2: i2c-bus@2 { + reg = <2>; /* OM45 */ + }; + + cfam3_i2c3: i2c-bus@3 { + reg = <3>; /* OM67 */ + }; + + cfam3_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam3_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam3_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam3_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam3_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam3_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ3: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub3: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@4,0 { /* DCM2_C0 */ + reg = <4 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <4>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam4_i2c0: i2c-bus@0 { + reg = <0>; /* OM01 */ + }; + + cfam4_i2c1: i2c-bus@1 { + reg = <1>; /* OM23 */ + }; + + cfam4_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam4_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam4_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam4_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam4_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam4_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam4_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam4_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam4_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam4_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ4: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub4: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@5,0 { /* DCM2_C1 */ + reg = <5 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <5>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam5_i2c2: i2c-bus@2 { + reg = <2>; /* OM45 */ + }; + + cfam5_i2c3: i2c-bus@3 { + reg = <3>; /* OM67 */ + }; + + cfam5_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam5_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam5_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam5_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam5_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam5_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam5_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam5_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam5_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam5_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ5: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub5: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@6,0 { /* DCM3_C0 */ + reg = <6 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <6>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam6_i2c0: i2c-bus@0 { + reg = <0>; /* OM01 */ + }; + + cfam6_i2c1: i2c-bus@1 { + reg = <1>; /* OM23 */ + }; + + cfam6_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam6_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam6_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam6_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam6_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam6_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam6_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam6_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam6_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam6_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ6: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub6: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@7,0 { /* DCM3_C1 */ + reg = <7 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <7>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam7_i2c2: i2c-bus@2 { + reg = <2>; /* OM45 */ + }; + + cfam7_i2c3: i2c-bus@3 { + reg = <3>; /* OM67 */ + }; + + cfam7_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam7_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam7_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam7_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam7_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam7_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam7_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam7_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam7_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam7_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ7: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub7: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +&fsi_occ2 { + reg = <3>; +}; + +&fsi_occ3 { + reg = <4>; +}; + +&fsi_occ4 { + reg = <5>; +}; + +&fsi_occ5 { + reg = <6>; +}; + +&fsi_occ6 { + reg = <7>; +}; + +&fsi_occ7 { + reg = <8>; +}; + +&ibt { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, + <&syscon ASPEED_CLK_MAC4RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts new file mode 100644 index 000000000000..f5f5b18c113a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-rainier-4u.dts" + +/ { + model = "Rainier 1S4U"; +}; + +&max { + /delete-node/ fan3; + /delete-node/ fan5; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts new file mode 100644 index 000000000000..342546a3c0f5 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2020 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-rainier.dts" + +/ { + model = "Rainier 4U"; +}; + +&i2c3 { + power-supply@6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts new file mode 100644 index 000000000000..7162e65b8115 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts @@ -0,0 +1,2420 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Rainier 2U"; + compatible = "ibm,rainier-bmc", "aspeed,ast2600"; + + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + i2c300 = &cfam2_i2c0; + i2c301 = &cfam2_i2c1; + i2c310 = &cfam2_i2c10; + i2c311 = &cfam2_i2c11; + i2c312 = &cfam2_i2c12; + i2c313 = &cfam2_i2c13; + i2c314 = &cfam2_i2c14; + i2c315 = &cfam2_i2c15; + i2c402 = &cfam3_i2c2; + i2c403 = &cfam3_i2c3; + i2c410 = &cfam3_i2c10; + i2c411 = &cfam3_i2c11; + i2c414 = &cfam3_i2c14; + i2c415 = &cfam3_i2c15; + i2c416 = &cfam3_i2c16; + i2c417 = &cfam3_i2c17; + + serial4 = &uart5; + i2c16 = &i2c2mux0; + i2c17 = &i2c2mux1; + i2c18 = &i2c2mux2; + i2c19 = &i2c2mux3; + i2c20 = &i2c4mux0chn0; + i2c21 = &i2c4mux0chn1; + i2c22 = &i2c4mux0chn2; + i2c23 = &i2c5mux0chn0; + i2c24 = &i2c5mux0chn1; + i2c25 = &i2c6mux0chn0; + i2c26 = &i2c6mux0chn1; + i2c27 = &i2c6mux0chn2; + i2c28 = &i2c6mux0chn3; + i2c29 = &i2c11mux0chn0; + i2c30 = &i2c11mux0chn1; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + spi30 = &cfam2_spi0; + spi31 = &cfam2_spi1; + spi32 = &cfam2_spi2; + spi33 = &cfam2_spi3; + spi40 = &cfam3_spi0; + spi41 = &cfam3_spi1; + spi42 = &cfam3_spi2; + spi43 = &cfam3_spi3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + no-map; + reg = <0xb4000000 0x04000000>; /* 64M */ + }; + + /* VGA region is dictated by hardware strapping */ + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + i2c2mux: i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-parent = <&i2c2>; + mux-gpios = <&gpio0 ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>, + <&gpio0 ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>; + idle-state = <0>; + + i2c2mux0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c2mux1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c2mux2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c2mux3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* BMC Card fault LED at the back */ + bmc-ingraham0 { + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure ID LED at the back */ + rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure fault LED at the back */ + rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + + /* PCIE slot power LED */ + pcieslot-power { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + event-fan4-presence { + label = "fan4-presence"; + gpios = <&pca0 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + event-fan5-presence { + label = "fan5-presence"; + gpios = <&pca0 11 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 7>; + }; +}; + +&adc1 { + status = "okay"; + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","checkstop","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", + /*I0-I7*/ "","","","","","","bmc-secure-boot","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", + /*P0-P7*/ "","","","","pcieslot-power","","","", + /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", + /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", + /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", + "power-ffs-sync-history","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + + i2c3_mux_oe_n { + gpio-hog; + gpios = ; + output-high; + line-name = "I2C3_MUX_OE_N"; + }; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; +}; + +&emmc_controller { + status = "okay"; +}; + +&pinctrl_emmc_default { + bias-disable; +}; + +&emmc { + status = "okay"; + clk-phase-mmc-hs200 = <180>, <180>; +}; + +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + /* + * CFAM Reset is supposed to be active low but pass1 hardware is wired + * active high. + */ + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; /* OMI01 */ + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; /* OMI23 */ + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam0_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; /* OMI45 */ + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; /* OMI67 */ + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam1_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam1_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam1_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@2,0 { + reg = <2 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <2>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_i2c0: i2c-bus@0 { + reg = <0>; /* OM01 */ + }; + + cfam2_i2c1: i2c-bus@1 { + reg = <1>; /* OM23 */ + }; + + cfam2_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam2_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam2_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam2_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam2_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam2_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ2: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub2: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@3,0 { + reg = <3 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <3>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_i2c2: i2c-bus@2 { + reg = <2>; /* OM45 */ + }; + + cfam3_i2c3: i2c-bus@3 { + reg = <3>; /* OM67 */ + }; + + cfam3_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam3_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam3_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam3_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam3_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam3_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ3: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub3: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +&fsi_occ2 { + reg = <3>; +}; + +&fsi_occ3 { + reg = <4>; +}; + +&ibt { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + tca_pres1: tca9554@20{ + compatible = "ti,tca9554"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", + "RUSSEL_FW_I2C_ENABLE_N", + "RUSSEL_OPPANEL_PRESENCE_N", + "BLYTH_OPPANEL_PRESENCE_N", + "CPU_TPM_CARD_PRESENT_N", + "DASD_BP2_PRESENT_N", + "DASD_BP1_PRESENT_N", + "DASD_BP0_PRESENT_N"; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + power-supply@68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + pca_pres1: pca9552@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLOT0_PRSNT_EN_RSVD", "SLOT1_PRSNT_EN_RSVD", + "SLOT2_PRSNT_EN_RSVD", "SLOT3_PRSNT_EN_RSVD", + "SLOT4_PRSNT_EN_RSVD", "SLOT0_EXPANDER_PRSNT_N", + "SLOT1_EXPANDER_PRSNT_N", "SLOT2_EXPANDER_PRSNT_N", + "SLOT3_EXPANDER_PRSNT_N", "SLOT4_EXPANDER_PRSNT_N", + "", "", "", "", "", ""; + }; +}; + +&i2c4 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + pca9546@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c4mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard0-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard0-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c4mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + + i2c4mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + pca9546@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c5mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard3-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard3-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c5mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard4-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard4-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + tmp275@4b { + compatible = "ti,tmp275"; + reg = <0x4b>; + }; + + pca9546@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c6mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c6mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + + i2c6mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c6mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + }; +}; + +&i2c7 { + multi-master; + status = "okay"; + + pca9552@30 { + compatible = "ibm,pca9552"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "pcieslot0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "pcieslot1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "pcieslot2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "pcieslot3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "pcieslot4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "cpu1"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "cpu-vrm1"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "lcd-russel"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pca9552@31 { + compatible = "ibm,pca9552"; + reg = <0x31>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pca9552@32 { + compatible = "ibm,pca9552"; + reg = <0x32>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm16"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm17"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm18"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm19"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm20"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm21"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm22"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm23"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm24"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm25"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm26"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm27"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm28"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm29"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm30"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm31"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pca9552@33 { + compatible = "ibm,pca9552"; + reg = <0x33>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "planar"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cpu0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "dasd-pyramid0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "dasd-pyramid1"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "dasd-pyramid2"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "cpu0-vrm0"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "rtc-battery"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "base-blyth"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "pcieslot6"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "pcieslot7"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "pcieslot8"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "pcieslot9"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "pcieslot10"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "pcieslot11"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "tpm-wilson"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + si7021-a20@40 { + compatible = "silabs,si7020"; + reg = <0x40>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + max: max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan0: fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan1: fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + + fan2: fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + }; + + fan3: fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + }; + + fan4: fan@4 { + compatible = "pmbus-fan"; + reg = <4>; + tach-pulses = <2>; + }; + + fan5: fan@5 { + compatible = "pmbus-fan"; + reg = <5>; + tach-pulses = <2>; + }; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pca0: pca9552@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "fan0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "fan1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "fan2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "fan3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "fan4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "fan5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c8 { + status = "okay"; + + ucd90320@11 { + compatible = "ti,ucd90320"; + reg = <0x11>; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca_pres3: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "power-config-full-load", ""; + }; + + pca_pres2: pca9552@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLOT6_PRSNT_EN_RSVD", "SLOT7_PRSNT_EN_RSVD", + "SLOT8_PRSNT_EN_RSVD", "SLOT9_PRSNT_EN_RSVD", + "SLOT10_PRSNT_EN_RSVD", "SLOT11_PRSNT_EN_RSVD", + "SLOT6_EXPANDER_PRSNT_N", "SLOT7_EXPANDER_PRSNT_N", + "SLOT8_EXPANDER_PRSNT_N", "SLOT9_EXPANDER_PRSNT_N", + "SLOT10_EXPANDER_PRSNT_N", "SLOT11_EXPANDER_PRSNT_N", + "", "", "", ""; + }; + +}; + +&i2c9 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c10 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c11 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + pca9546@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c11mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard10-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard10-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + }; + + i2c11mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + }; +}; + +&i2c12 { + status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c13 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "nvme4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "nvme5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "nvme6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "nvme7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; +}; + +&i2c14 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme8"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "nvme9"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "nvme10"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "nvme11"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "nvme12"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "nvme13"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "nvme14"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "nvme15"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; +}; + +&i2c15 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme16"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "nvme17"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "nvme18"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "nvme19"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "nvme20"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "nvme21"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "nvme22"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "nvme23"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, + <&syscon ASPEED_CLK_MAC4RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts new file mode 100644 index 000000000000..208b0f094ed9 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model = "FP5280G2 BMC"; + compatible = "inspur,fp5280g2-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + linux,code = <1>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca1 1 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + linux,code = <3>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + event-fan4-presence { + label = "fan4-presence"; + gpios = <&pca1 4 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + event-fan5-presence { + label = "fan5-presence"; + gpios = <&pca1 5 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-fan6-presence { + label = "fan6-presence"; + gpios = <&pca1 6 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + event-fan7-presence { + label = "fan7-presence"; + gpios = <&pca1 7 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "power"; + /* TODO: dummy gpio */ + gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; + }; + + init-ok { + label = "init-ok"; + gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; + }; + + front-memory { + label = "front-memory"; + gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + }; + + front-syshot { + label = "front-syshot"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + }; + + front-syshealth { + label = "front-syshealth"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + }; + + front-fan { + label = "front-fan"; + gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + }; + + front-psu { + label = "front-psu"; + gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + label = "identify"; + gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>; + }; + +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","front-psu","checkstop","cfam-reset","","","init-ok", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "ps0-presence","ps1-presence","","","front-memory","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","front-fan","","","", + /*I0-I7*/ "front-syshealth","front-syshot","mux-gpios","enable-gpios","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","power","trans-gpios","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","identify", + /*AA0-AA7*/ "clock-gpios","","data-gpios","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* Test Point */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart3 { + /* APSS */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + /* LCD */ + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + label = "fru"; + }; + +}; + +&i2c2 { + status = "okay"; + + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + label = "inlet"; + }; + + tmp112@49 { + compatible = "ti,tmp112"; + reg = <0x49>; + label = "outlet"; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tmp112@4a { + compatible = "ti,tmp112"; + reg = <0x4a>; + label = "psu_inlet"; + }; + + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tmp112@4a { + compatible = "ti,tmp112"; + reg = <0x4a>; + label = "ocp_zone"; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tmp112@4a { + compatible = "ti,tmp112"; + reg = <0x4a>; + label = "bmc_zone"; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tmp112@7c { + compatible = "microchip,emc1413"; + reg = <0x7c>; + }; + }; + + }; +}; + +&i2c3 { + /* Riser Card */ + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; +}; + +&i2c5 { + /* vr */ + status = "okay"; +}; + +&i2c6 { + /* bp card */ + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + }; + + adm1278@13 { + compatible = "adi,adm1278"; + reg = <0x13>; + }; + + adm1278@50 { + compatible = "adi,adm1278"; + reg = <0x50>; + }; + + adm1278@53 { + compatible = "adi,adm1278"; + reg = <0x53>; + }; + + }; + + /*pcie riser*/ + + }; +}; + +&i2c8 { + status = "okay"; + + pca0: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + }; + + pca1: pca9555@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca2: pca9555@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca3: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca4: pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca5: pca9555@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + +}; + +&i2c9 { + /* cpld */ + status = "okay"; +}; + +&i2c10 { + /* hdd bp */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + power-supply@58 { + compatible = "inspur,ipsps1"; + reg = <0x58>; + }; + + power-supply@59 { + compatible = "inspur,ipsps1"; + reg = <0x59>; + }; +}; + +&i2c12 { + /* odcc */ + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&ibt { + status = "okay"; + +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default + &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default + &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default + &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; + }; + +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts new file mode 100644 index 000000000000..b3c1e3ba5831 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021 Inspur Corporation +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model = "NF5280M6 BMC"; + compatible = "inspur,nf5280m6-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + led-pattern = <1000 1000>; + }; + + front-fan { + label = "front-fan"; + gpios = <&gpio ASPEED_GPIO(F,2) GPIO_ACTIVE_LOW>; + }; + + front-psu { + label = "front-psu"; + gpios = <&gpio ASPEED_GPIO(F,3) GPIO_ACTIVE_LOW>; + }; + + front-syshot { + label = "front-syshot"; + gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; + }; + + front-memory { + label = "front-memory"; + gpios = <&gpio ASPEED_GPIO(S, 7) GPIO_ACTIVE_LOW>; + }; + + identify { + label = "identify"; + gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&gpio { + status = "okay"; + /* Enable GPIOE0 and GPIOE2 pass-through by default */ + pinctrl-names = "pass-through"; + pinctrl-0 = <&pinctrl_gpie0_default + &pinctrl_gpie2_default>; + gpio-line-names = + /*A0-A7*/ "","MAC2LINK","BMC_RESET_CPLD","","BMC_SCL9","","MAC2MDC_R","", + /*B0-B7*/ "BMC_INIT_OK","FM_SKU_ID2","FM_SPD_DDRCPU_LVLSHFT_DIS_R_N", + "FM_CPU_MSMI_CATERR_LVT3_BMC_N","","FM_CPU0_PROCHOT_LVT3_N", + "FM_CPU_MEM_THERMTRIP_LVT3_N","BIOS_LOAD_DEFAULT_R_N", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","BMC_SD2CMD","BMC_SD2DAT0","BMC_SD2DAT1","BMC_SD2DAT2", + "BMC_SD2DAT3","BMC_SD2DET","BMC_SD2WPT", + /*E0-E7*/ "FM_BOARD_ID0","FM_BOARD_ID1","FM_BOARD_ID2","FM_BOARD_ID3", + "FM_BOARD_ID4","FM_BOARD_ID5","","", + /*F0-F7*/ "PSU1_PRESENT_N","PSU2_PRESENT_N","FAN_FAULT_LED_N","PSU_FAULT_LED_N", + "BIOS_DEBUG_MODE_N","FP_LCD_RESET","FAN_TYPE_SEL", + "RST_GLB_RST_WARN_N", + /*G0-G7*/ "IRQ_LPTM21L_ALERT_N","IRQ_PLD_ALERT_N","AC_FAIL_N","FP_LCD_PRESENT_BMC", + "BMC_JTAG_TCK_MUX_SEL","BMC_BIOS_RESERVED","SYS_NMI_N","BMC_NMI_N", + /*H0-H7*/ "JTAG_BMC_TDI","JTAG_BMC_TDO","JTAG_BMC_TCK","JTAG_BMC_TMS","FM_BOARD_ID6", + "FM_SKU_ID0","IRQ_SML1_PMBUS_ALERT_N","IRQ_SML0_ALERT_MUX_N", + /*I0-I7*/ "FM_CPU_ERR0_LVT3_BMC_N","FM_CPU_ERR1_LVT3_BMC_N","FM_BMC_PCH_SCI_LPC_N", + "FM_SYS_THROTTLE_LVC3","SPI2_PCH_CS0_N","","","", + /*J0-J7*/ "FM_CPU0_SKTOCC_LVT3_N","FM_CPU1_SKTOCC_LVT3_N","","SYSHOT_FAULT_LED_N", + "VGA_HSYNC","VGA_VSYNC","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","SYS_UART_TXD1","SYS_UART_RXD1", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","FM_PCH_BMC_THERMTRIP_N","INTRUDER_N", + /*R0-R7*/ "SPI_BMC_BOOT_CS1_R_N","FM_CPU_MEMHOT_LVC3_N", + "DBP_CPU_PREQ_N","FM_CPU_ERR2_LVT3_BMC_N", + "RISER_NCSI_EN_N","","LOM_NCSI_EN_N","OCP_NCSI_EN_N", + /*S0-S7*/ "BMC_XDP_PRDY_N","SIO_POWER_GOOD","BMC_PWR_DEBUG_R_N","BMC_DEBUG_EN_R_N","", + "GPIOS5_BMC","","GPIOS7_BMC", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","BMC_DET_UID_N","BMC_JTAG_SEL","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "XDP_PRESENT_N","DBP_SYSPWROK","BMC_JTAG_SEL","FM_SMI_ACTIVE_N","", + "GPIOZ5","","", + /*AA0-AA7*/ "FP_BMC_SYSLED_N","PS_PWROK","RST_PLTRST_BMC_N","HDA_SDO_BMC", + "FM_SLPS4_R_N","","POWER_BUTTON","POWER_OUT", + /*AB0-AB7*/ "RESET_OUT","RESET_BUTTON","BIOS_REFLASH","POST_COMPLETE","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&i2c0 { + /* FP_LCD */ + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + label = "fru"; + }; +}; + +&i2c2 { + status = "okay"; + + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + label = "inlet"; + }; + + tmp112@49 { + compatible = "ti,tmp112"; + reg = <0x49>; + label = "outlet"; + }; + + pca9548@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + }; +}; + +&i2c3 { + status = "okay"; + + pca9548@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + }; + + pca9548@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + }; + + pca9548@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + }; +}; + +&i2c4 { + /* IPMB */ + status = "okay"; +}; + +&i2c5 { + status = "okay"; + + pca9548@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + }; +}; + +&i2c6 { + status = "okay"; + + pca9548@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + }; +}; + +&i2c7 { + status = "okay"; + + adm1278@33 { + compatible = "adi,adm1293"; + reg = <0x33>; + }; + + adm1278@32 { + compatible = "adi,adm1293"; + reg = <0x32>; + }; + + adm1278@20 { + compatible = "adi,adm1293"; + reg = <0x20>; + }; +}; + +&i2c8 { + status = "okay"; + + pca0: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + }; + + pca1: pca9555@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca2: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca3: pca9555@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; +}; + +&i2c9 { + /* cpld */ + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + pca4: pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + + pca5: pca9555@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + }; +}; + +&i2c11 { + status = "okay"; + + power-supply@58 { + compatible = "inspur,ipsps1"; + reg = <0x58>; + }; + + power-supply@59 { + compatible = "inspur,ipsps1"; + reg = <0x59>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; + }; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&kcs4 { + status = "okay"; + aspeed,lpc-io-reg = <0xca4>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default + &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default + &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default + &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vuart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts new file mode 100644 index 000000000000..5a98a19f445e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Inspur Corporation +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "ON5263M5 BMC"; + compatible = "inspur,on5263m5-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "earlycon"; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c6 { + status = "okay"; + + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2c7 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; +}; + +&adc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts new file mode 100644 index 000000000000..d5b7d28cda88 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Intel Corporation +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "S2600WF BMC"; + compatible = "intel,s2600wf-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default &pinctrl_pwm7_default>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts new file mode 100644 index 000000000000..caf66651e5b5 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 Inventec Corp. + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include "aspeed-g6-pinctrl.dtsi" +#include +#include + +/ { + model = "TRANSFORMERS BMC"; + compatible = "inventec,transformer-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + // UID led + uid { + label = "UID_LED"; + gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; + }; + + // Heart beat led + heartbeat { + label = "HB_LED"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <33000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +#include "openbmc-flash-layout.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-max-frequency = <33000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <33000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&wdt1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + //Set bmc' slave address; + bmc_slave@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + // FRU AT24C512C-SSHM-T + status = "okay"; + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + pagesize = <128>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + tmp75@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; + + tmp468@48 { + compatible = "ti,tmp468"; + reg = <0x48>; + }; +}; + +&i2c7 { + status = "okay"; + adm1278@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + + +&i2c8 { + // FRU AT24C512C-SSHM-T + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + pagesize = <128>; + }; + + eeprom@53 { + compatible = "atmel,24c512"; + reg = <0x53>; + pagesize = <128>; + }; +}; + +&i2c9 { + // M.2 + status = "okay"; +}; + +&i2c10 { + // I2C EXPANDER + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + }; +}; + +&i2c11 { + // I2C EXPANDER + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + pcie_eeprom_riser1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@55 { + compatible = "atmel,24c512"; + reg = <0x55>; + pagesize = <128>; + }; + }; + + pcie_eeprom_riser2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@55 { + compatible = "atmel,24c512"; + reg = <0x55>; + pagesize = <128>; + }; + }; + + pcie_eeprom_riser3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@55 { + compatible = "atmel,24c512"; + reg = <0x55>; + pagesize = <128>; + }; + }; + }; +}; + +&i2c12 { + status = "okay"; + + psu0:psu0@58 { + compatible = "pmbus"; + reg = <0x58>; + }; +}; + +&gpio0 { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","power-chassis-control","","","", + /*G0-G7*/ "","","jtag-mux","","","","","", + /*H0-H7*/ "","","","","reset-button","power-button","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","tck-mux","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","nmi-button","","","","","","", + /*V0-V7*/ "","","","","power-config-full-load","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; +}; + +&vhub { + status = "okay"; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts new file mode 100644 index 000000000000..8f543cca7c21 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Lenovo Hr630 platform + * + * Copyright (C) 2019-present Lenovo + */ + +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "HR630 BMC"; + compatible = "lenovo,hr630-bmc", "aspeed,ast2500"; + + aliases { + i2c14 = &i2c_rbp; + i2c15 = &i2c_fbp1; + i2c16 = &i2c_fbp2; + i2c17 = &i2c_fbp3; + i2c18 = &i2c_riser2; + i2c19 = &i2c_pcie4; + i2c20 = &i2c_riser1; + i2c21 = &i2c_ocp; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x00100000>; /* 1M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>; + }; + + fault { + gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default>; +}; + +&i2c0 { + status = "okay"; + /* temp1 inlet */ + tmp75@4e { + compatible = "national,lm75"; + reg = <0x4e>; + }; +}; + +&i2c1 { + status = "okay"; + /* temp2 outlet */ + tmp75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + /* Slot 0, + * Slot 1, + * Slot 2, + * Slot 3 + */ + + i2c-switch@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; /* may use mux@70 next. */ + + i2c_rbp: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_fbp1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_fbp2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_fbp3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + /* Slot 0, + * Slot 1, + * Slot 2, + * Slot 3 + */ + i2c-switch@76 { + compatible = "nxp,pca9546"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; /* may use mux@76 next. */ + + i2c_riser2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_riser1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_ocp: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c8 { + status = "okay"; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; +}; + +&gpio { + + pin_gpio_b5 { + gpio-hog; + gpios = ; + output-high; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + + pin_gpio_f0 { + gpio-hog; + gpios = ; + output-low; + line-name = "IRQ_BMC_PCH_NMI_R"; + }; + + pin_gpio_f3 { + gpio-hog; + gpios = ; + output-high; + line-name = "I2C_BUS0_RST_OUT_N"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = ; + output-low; + line-name = "FM_SKT0_FAULT_LED"; + }; + + pin_gpio_f5 { + gpio-hog; + gpios = ; + output-low; + line-name = "FM_SKT1_FAULT_LED"; + }; + + pin_gpio_g4 { + gpio-hog; + gpios = ; + output-high; + line-name = "FAN_PWR_CTL_N"; + }; + + pin_gpio_g7 { + gpio-hog; + gpios = ; + output-high; + line-name = "RST_BMC_PCIE_I2CMUX_N"; + }; + + pin_gpio_h2 { + gpio-hog; + gpios = ; + output-high; + line-name = "PSU1_FFS_N_R"; + }; + + pin_gpio_h3 { + gpio-hog; + gpios = ; + output-high; + line-name = "PSU2_FFS_N_R"; + }; + + pin_gpio_i3 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_INTRUDED_COVER"; + }; + + pin_gpio_j2 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_BIOS_UPDATE_N"; + }; + + pin_gpio_j3 { + gpio-hog; + gpios = ; + output-high; + line-name = "RST_BMC_HDD_I2CMUX_N"; + }; + + pin_gpio_s2 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_VGA_SW"; + }; + + pin_gpio_s4 { + gpio-hog; + gpios = ; + output; + line-name = "VBAT_EN_N"; + }; + + pin_gpio_s6 { + gpio-hog; + gpios = ; + output-high; + line-name = "PU_BMC_GPIOS6"; + }; + + pin_gpio_y0 { + gpio-hog; + gpios = ; + output-low; + line-name = "BMC_NCSI_MUX_CTL_S0"; + }; + + pin_gpio_y1 { + gpio-hog; + gpios = ; + output-low; + line-name = "BMC_NCSI_MUX_CTL_S1"; + }; + + pin_gpio_z0 { + gpio-hog; + gpios = ; + output-high; + line-name = "I2C_RISER2_INT_N"; + }; + + pin_gpio_z2 { + gpio-hog; + gpios = ; + output-high; + line-name = "I2C_RISER2_RESET_N"; + }; + + pin_gpio_z3 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_BMC_PCH_SCI_LPC_N"; + }; + + pin_gpio_z7 { + gpio-hog; + gpios = ; + output-low; + line-name = "BMC_POST_CMPLT_N"; + }; + + pin_gpio_aa0 { + gpio-hog; + gpios = ; + output-low; + line-name = "HOST_BMC_USB_SEL"; + }; + + pin_gpio_aa5 { + gpio-hog; + gpios = ; + output-high; + line-name = "I2C_BUS1_RST_OUT_N"; + }; + +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts new file mode 100644 index 000000000000..bcc1820f5c07 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Lenovo Hr855xg2 platform + * + * Copyright (C) 2019-present Lenovo + */ + +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "HR855XG2 BMC"; + compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500"; + + aliases { + i2c14 = &i2c_riser1; + i2c15 = &i2c_riser2; + i2c16 = &i2c_riser3; + i2c17 = &i2c_M2; + i2c18 = &channel_0; + i2c19 = &channel_1; + i2c20 = &channel_2; + i2c21 = &channel_3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x00100000>; /* 1M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + + fault { + gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>,<&adc 11>, + <&adc 12>,<&adc 13>,<&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&adc{ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&i2c0 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_riser1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_riser2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_riser3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_M2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c1 { + status = "okay"; + bus-frequency = <90000>; + HotSwap@10 { + compatible = "adm1272"; + reg = <0x10>; + }; + + VR@45 { + compatible = "pmbus"; + reg = <0x45>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + channel_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + /* temp1 */ + tmp75@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + /* temp2 */ + tmp75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; + + eeprom@54 { + compatible = "atmel,24c256"; + reg = <0x54>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@14 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; + + fan@15 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; + + fan@16 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; +}; + +&gpio { + + pin_gpio_a1 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_EMMC_RST_N"; + }; + + pin_gpio_a3 { + gpio-hog; + gpios = ; + output-high; + line-name = "PCH_PWROK_BMC_FPGA"; + }; + + pin_gpio_b5 { + gpio-hog; + gpios = ; + output-high; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + + pin_gpio_b7 { + gpio-hog; + gpios = ; + output-low; + line-name = "CPU_SM_WP"; + }; + + pin_gpio_e0 { + gpio-hog; + gpios = ; + input; + line-name = "PDB_PSU_SEL"; + }; + + pin_gpio_e2 { + gpio-hog; + gpios = ; + output-high; + line-name = "LOCATOR_LED_N"; + }; + + pin_gpio_e5 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_BMC_DBP_PRESENT_R1_N"; + }; + + pin_gpio_e6 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_ME_SECURITY_OVERRIDE_N"; + }; + + pin_gpio_f0 { + gpio-hog; + gpios = ; + output-high; + line-name = "IRQ_BMC_PCH_NMI_R"; + }; + + pin_gpio_f1 { + gpio-hog; + gpios = ; + input; + line-name = "CPU2_PROCDIS_BMC_N"; + }; + + pin_gpio_f2 { + gpio-hog; + gpios = ; + output-high; + line-name = "RM_THROTTLE_EN_N"; + }; + + pin_gpio_f3 { + gpio-hog; + gpios = ; + output-low; + line-name = "FM_PMBUS_ALERT_B_EN"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FORCE_NM_THROTTLE_N"; + }; + + pin_gpio_f6 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_BMC_CPU_PWR_DEBUG_N"; + }; + + pin_gpio_g7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_PCIE_I2C_MUX_RST_N"; + }; + + pin_gpio_h6 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_BMC_DBP_PRESENT_R2_N"; + }; + + pin_gpio_i3 { + gpio-hog; + gpios = ; + output-high; + line-name = "SPI_BMC_BIOS_WP_N"; + }; + + pin_gpio_j1 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_USB_SEL"; + }; + + pin_gpio_j2 { + gpio-hog; + gpios = ; + output-high; + line-name = "PDB_SMB_RST_N"; + }; + + pin_gpio_j3 { + gpio-hog; + gpios = ; + output-high; + line-name = "SPI_BMC_BIOS_HOLD_N"; + }; + + pin_gpio_l0 { + gpio-hog; + gpios = ; + output-high; + line-name = "PDB_FAN_TACH_SEL"; + }; + + pin_gpio_l1 { + gpio-hog; + gpios = ; + output-high; + line-name = "SYS_RESET_BMC_FPGA_N"; + }; + + pin_gpio_l4 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_EFUSE_FAN_G1_EN"; + }; + + pin_gpio_l5 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_EFUSE_FAN_G2_EN"; + }; + + pin_gpio_r6 { + gpio-hog; + gpios = ; + input; + line-name = "CPU3_PROCDIS_BMC_N"; + }; + + pin_gpio_r7 { + gpio-hog; + gpios = ; + input; + line-name = "CPU4_PROCDIS_BMC_N"; + }; + + pin_gpio_s1 { + gpio-hog; + gpios = ; + output-low; + line-name = "DBP_SYSPWROK_BMC"; + }; + + pin_gpio_s2 { + gpio-hog; + gpios = ; + output-high; + line-name = "PCH_RST_RSMRST_N"; + }; + + pin_gpio_s6 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_HW_STRAP_5"; + }; + + pin_gpio_z3 { + gpio-hog; + gpios = ; + output-high; + line-name = "FM_BMC_PCH_SCI_LPC_N"; + }; + + pin_gpio_aa0 { + gpio-hog; + gpios = ; + output-low; + line-name = "FW_PSU_ALERT_EN_N"; + }; + + pin_gpio_aa4 { + gpio-hog; + gpios = ; + output-high; + line-name = "DBP_CPU_PREQ_N"; + }; + + pin_gpio_ab3 { + gpio-hog; + gpios = ; + output-low; + line-name = "BMC_WDTRST"; + }; + + pin_gpio_ac6 { + gpio-hog; + gpios = ; + output-high; + line-name = "ESPI_BMC_ALERT_N"; + }; + +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts new file mode 100644 index 000000000000..3ef8358ff764 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts @@ -0,0 +1,207 @@ +//SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include + +/ { + model = "Olympus BMC"; + compatible = "microsoft,olympus-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@5f000000 { + no-map; + reg = <0x5f000000 0x01000000>; /* 16M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + bmc_heartbeat { + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + }; + + power_green { + gpios = <&gpio ASPEED_GPIO(U, 2) GPIO_ACTIVE_HIGH>; + }; + + power_amber { + gpios = <&gpio ASPEED_GPIO(U, 3) GPIO_ACTIVE_HIGH>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + }; + + fault { + gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; + }; + }; + + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts new file mode 100644 index 000000000000..c0847636f20b --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Inventec Corporation +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Lanyang BMC"; + compatible = "inventec,lanyang-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + sys_boot_status { + label = "System_boot_status"; + gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_LOW>; + }; + + attention { + label = "Attention_locator"; + gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>; + }; + + plt_fault { + label = "Platform_fault"; + gpios = <&gpio ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + }; + + hdd_fault { + label = "Onboard_drive_fault"; + gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_HIGH>; + }; + bmc_err { + lable = "BMC_fault"; + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; + }; + + sys_err { + lable = "Sys_fault"; + gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 13>, <&adc 14>, <&adc 15>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2cs0_default + &pinctrl_spi2cs1_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default>; + + flash@0 { + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + tmp75@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&gpio { + pin_gpio_b0 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_HDD1_PWR_EN"; + }; + + pin_gpio_b5 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_USB1_OCI2"; + }; + + pin_gpio_h5 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_CP0_PERST_ENABLE_R"; + }; + + pin_gpio_z2 { + gpio-hog; + gpios = ; + output-high; + line-name = "RST_PCA9546_U177_N"; + }; + + pin_gpio_aa6 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_CP0_RESET_N"; + }; + + pin_gpio_aa7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_TPM_RESET_N"; + }; + + pin_gpio_ab0 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_USB_PWRON_N"; + }; +}; + +&ibt { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts new file mode 100644 index 000000000000..31ff19ef87a0 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts @@ -0,0 +1,667 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Mowgli BMC"; + compatible = "ibm,mowgli-bmc", "aspeed,ast2500"; + + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-id { + label = "id-button"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + event-fan4-presence { + label = "fan4-presence"; + gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + }; + + leds { + compatible = "gpio-leds"; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; + }; + + power-button { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; + }; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; + }; + + fan4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-12v { + compatible = "iio-hwmon"; + io-channels = <&adc 0>; + }; + + iio-hwmon-5v { + compatible = "iio-hwmon"; + io-channels = <&adc 1>; + }; + + iio-hwmon-3v { + compatible = "iio-hwmon"; + io-channels = <&adc 2>; + }; + + iio-hwmon-vdd { + compatible = "iio-hwmon"; + io-channels = <&adc 3>; + }; + + iio-hwmon-vcs { + compatible = "iio-hwmon"; + io-channels = <&adc 5>; + }; + + iio-hwmon-vdn { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + iio-hwmon-vio { + compatible = "iio-hwmon"; + io-channels = <&adc 9>; + }; + + iio-hwmon-vddra { + compatible = "iio-hwmon"; + io-channels = <&adc 11>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + iio-hwmon-vddrb { + compatible = "iio-hwmon"; + io-channels = <&adc 13>; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "obmc-ubi"; + }; + }; + }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + /* CPU MFG CONN */ + +}; + +&i2c3 { + status = "okay"; + + /* APSS */ + /* CPLD */ + + /* PCA9516 (repeater) -> + * CLK Buffer 9FGS9092 + * Power Supply 0 + * Power Supply 1 + * PCA 9552 LED + */ + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + gpio@1 { + reg = <1>; + type = ; + }; + gpio@2 { + reg = <2>; + type = ; + }; + gpio@3 { + reg = <3>; + type = ; + }; + gpio@4 { + reg = <4>; + type = ; + }; + gpio@5 { + reg = <5>; + type = ; + }; + gpio@6 { + reg = <6>; + type = ; + }; + gpio@7 { + reg = <7>; + type = ; + }; + gpio@8 { + reg = <8>; + type = ; + }; + gpio@9 { + reg = <9>; + type = ; + }; + gpio@10 { + reg = <10>; + type = ; + }; + gpio@11 { + reg = <11>; + type = ; + }; + gpio@12 { + reg = <12>; + type = ; + }; + gpio@13 { + reg = <13>; + type = ; + }; + gpio@14 { + reg = <14>; + type = ; + }; + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + /* CP0 VDD & VCS : IR35221 */ + /* CP0 VDN & VIO : IR35221 */ + /* CP0 VDDR : IR35221 */ + + ir35221@28 { + compatible = "infineon,ir35221"; + reg = <0x28>; + }; + + ir35221@29 { + compatible = "infineon,ir35221"; + reg = <0x29>; + }; + + ir35221@2d { + compatible = "infineon,ir35221"; + reg = <0x2d>; + }; + +}; + +&i2c5 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; +}; + +&i2c7 { + status = "disabled"; +}; + +&i2c8 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + + /* PCIe G3 x16 slot */ +}; + +&i2c10 { + status = "disabled"; +}; + +&i2c11 { + status = "okay"; + + /* CPLD */ + /* TPM */ + /* RTC RX8900CE */ + /* TMP275A */ + /* TMP275A */ + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts new file mode 100644 index 000000000000..ac0d666ca10e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 YADRO +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Nicole BMC"; + compatible = "yadro,nicole-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "platform:green:power"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; + }; + + identify { + label = "platform:blue:indicator"; + gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>; + }; + + fault { + label = "platform:red:fault"; + gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>; + }; + + attention { + label = "platform:yellow:alarm"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c2 { + status = "okay"; + /* CPU0 characterization connector */ +}; + +&i2c3 { + status = "okay"; + /* CLK GEN SI5338 */ +}; + +&i2c4 { + status = "okay"; + /* Voltage regulators for CPU0 */ +}; + +&i2c5 { + status = "okay"; + /* Voltage regulators for CPU1 */ +}; + +&i2c6 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c7 { + status = "okay"; + /* CPLD */ +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf", + "func_mode0","func_mode1","func_mode2","","", + /*E0-E7*/ "","ncsi_cfg","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","power-button","","","","","", + /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","software_pwrgood","","","","","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault", + "led-power","","","led-identify", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + + func_mode0 { + gpio-hog; + gpios = ; + output-low; + }; + func_mode1 { + gpio-hog; + gpios = ; + output-low; + }; + func_mode2 { + gpio-hog; + gpios = ; + output-low; + }; + seq_cont { + gpio-hog; + gpios = ; + output-low; + }; + ncsi_cfg { + gpio-hog; + input; + gpios = ; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts new file mode 100644 index 000000000000..45631b47a7b3 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include + +/ { + model = "Palmetto BMC"; + compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@5f000000 { + no-map; + reg = <0x5f000000 0x01000000>; /* 16M */ + }; + + coldfire_memory: codefire_memory@5ee00000 { + reg = <0x5ee00000 0x00200000>; + no-map; + }; + + flash_memory: region@5c000000 { + no-map; + reg = <0x5C000000 0x02000000>; /* 32MB */ + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1debug_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + spi-max-frequency = <50000000>; + label = "pnor"; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default + + &pinctrl_vgahs_default &pinctrl_vgavs_default + &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; + + rtc@68 { + compatible = "dallas,ds3231"; + reg = <0x68>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + tmp423@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c3 { + status = "okay"; + + occ-hwmon@50 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x50>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi>; +}; + +&gpio { + pin_func_mode0 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode0"; + }; + + pin_func_mode1 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode1"; + }; + + pin_func_mode2 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode2"; + }; + + pin_gpio_a0 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_FAN_RESERVED_N"; + }; + + pin_gpio_a1 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_WDT_N"; + }; + + pin_gpio_b1 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_BOOT_MODE"; + }; + + pin_gpio_b2 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_RESET_N"; + }; + + pin_gpio_b7 { + gpio-hog; + gpios = ; + output-high; + line-name = "SPIVID_STBY_RESET_N"; + }; + + pin_gpio_d1 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_POWER_UP"; + }; + + pin_gpio_f1 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_BATTERY_TEST"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = ; + input; + line-name = "AST_HW_FAULT_N"; + }; + + pin_gpio_f5 { + gpio-hog; + gpios = ; + input; + line-name = "AST_SYS_FAULT_N"; + }; + + pin_gpio_f7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FULL_SPEED_N"; + }; + + pin_gpio_g3 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FAN_ERROR_N"; + }; + + pin_gpio_g4 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_WDT_RST1_P"; + }; + + pin_gpio_g5 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_WDT_RST2_P"; + }; + + pin_gpio_h0 { + gpio-hog; + gpios = ; + input; + line-name = "PE_SLOT_TEST_EN_N"; + }; + + pin_gpio_h1 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_RTCRST_N"; + }; + + pin_gpio_h2 { + gpio-hog; + gpios = ; + output-high; + line-name = "SYS_PWROK_BMC"; + }; + + pin_gpio_h7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_TPM_INT_N"; + }; +}; + +&fsi { + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + fsi_hub0: hub@3400 { + compatible = "ibm,fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts new file mode 100644 index 000000000000..893e621ecab1 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Romulus BMC"; + compatible = "ibm,romulus-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + fault { + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + id-button { + label = "id-button"; + gpios = <&gpio ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + /* PCIe slot 1 (x8) */ + status = "okay"; +}; + +&i2c7 { + /* PCIe slot 2 (x16) */ + status = "okay"; +}; + +&i2c8 { + /* PCIe slot 3 (x16) */ + status = "okay"; +}; + +&i2c9 { + /* PCIe slot 4 (x16) */ + status = "okay"; +}; + +&i2c10 { + /* PCIe slot 5 (x8) */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c12 { + status = "okay"; + + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","led-fault","", + "led-identify","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","","fsi-trans","","","led-power","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + + nic_func_mode0 { + gpio-hog; + gpios = ; + output-low; + }; + nic_func_mode1 { + gpio-hog; + gpios = ; + output-low; + }; + seq_cont { + gpio-hog; + gpios = ; + output-low; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@5 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@6 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts new file mode 100644 index 000000000000..bbf864f84d37 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts @@ -0,0 +1,978 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Swift BMC"; + compatible = "ibm,swift-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-oppanel-presence { + label = "oppanel-presence"; + gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-opencapi-riser-presence { + label = "opencapi-riser-presence"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-scm0-presence { + label = "scm0-presence"; + gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-scm1-presence { + label = "scm1-presence"; + gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + event-cpu0vrm-presence { + label = "cpu0vrm-presence"; + gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + event-cpu1vrm-presence { + label = "cpu1vrm-presence"; + gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + event-fanboost-presence { + label = "fanboost-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + }; + + leds { + compatible = "gpio-leds"; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; + }; + + fanboost { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + }; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + }; + + front-power { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + }; + + rear-fault { + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; + }; + + rear-id { + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <100000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x7F80000>; + label = "obmc-ubi"; + }; + }; + }; + + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <100000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x7F80000>; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&i2c2 { + status = "okay"; + + /* MUX -> + * Samtec 1 + * Samtec 2 + */ +}; + +&i2c3 { + status = "okay"; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@4 { + compatible = "pmbus-fan"; + reg = <4>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps2"; + reg = <0x68>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + power-supply@69 { + compatible = "ibm,cffps2"; + reg = <0x69>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + si7021a20@20 { + compatible = "si,si7021a20"; + reg = <0x20>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca1: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; +}; + +&i2c8 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "P9_SCM0_PRES", "P9_SCM1_PRES", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c9 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + pca2: pca9539@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + pca3: pca9539@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; +}; + +&i2c11 { + /* MUX + * -> PCIe Slot 0 + * -> PCIe Slot 1 + * -> PCIe Slot 2 + * -> PCIe Slot 3 + */ + status = "okay"; +}; + +&i2c12 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts new file mode 100644 index 000000000000..3f6010ef2b86 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts @@ -0,0 +1,887 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Tacoma"; + compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@b8000000 { + no-map; + reg = <0xb8000000 0x4000000>; /* 64M */ + }; + + ramoops@bc000000 { + compatible = "ramoops"; + reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + + iio-hwmon-bmp280 { + compatible = "iio-hwmon"; + io-channels = <&bmp 1>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "fsi-mux","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","presence-ps0","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "led-rear-power","led-rear-id","","usb-power","","","","", + /*P0-P7*/ "","","","","","bmc-tpm-reset","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + clk-phase-mmc-hs200 = <36>, <270>; +}; + +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam0_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam0_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam0_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam0_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam0_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam0_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam0_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam0_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam1_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam1_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam1_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam1_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam1_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam1_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam1_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam1_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam1_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c102 = &cfam0_i2c2; + i2c103 = &cfam0_i2c3; + i2c104 = &cfam0_i2c4; + i2c105 = &cfam0_i2c5; + i2c106 = &cfam0_i2c6; + i2c107 = &cfam0_i2c7; + i2c108 = &cfam0_i2c8; + i2c109 = &cfam0_i2c9; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c200 = &cfam1_i2c0; + i2c201 = &cfam1_i2c1; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c204 = &cfam1_i2c4; + i2c205 = &cfam1_i2c5; + i2c206 = &cfam1_i2c6; + i2c207 = &cfam1_i2c7; + i2c208 = &cfam1_i2c8; + i2c209 = &cfam1_i2c9; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c212 = &cfam1_i2c12; + i2c213 = &cfam1_i2c13; + i2c214 = &cfam1_i2c14; + }; + +}; + +&i2c0 { + multi-master; + status = "okay"; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c1 { + status = "okay"; + + tpm: tpm@2e { + compatible = "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + bmp: bmp280@77 { + compatible = "bosch,bmp280"; + reg = <0x77>; + #io-channel-cells = <1>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&uart1 { + status = "okay"; + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&uart5 { + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + +&pinctrl { + /* Hog these as no driver is probed for the entire LPC block */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpc_default>, + <&pinctrl_lsirq_default>; +}; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts new file mode 100644 index 000000000000..8a7fb55ab489 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 YADRO +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include + +/ { + model = "Vesnin BMC"; + compatible = "yadro,vesnin-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@5f000000 { + no-map; + reg = <0x5f000000 0x01000000>; /* 16MB */ + }; + flash_memory: region@5c000000 { + no-map; + reg = <0x5c000000 0x02000000>; /* 32M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; + }; + power_red { + gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; + }; + + power_green { + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + }; + + id_blue { + gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; + }; + + alarm_red { + gpios = <&gpio ASPEED_GPIO(N, 6) GPIO_ACTIVE_LOW>; + }; + + alarm_yel { + gpios = <&gpio ASPEED_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-checkstop { + label = "checkstop"; + linux,code = <74>; + gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; + }; + + event-identify { + label = "identify"; + linux,code = <152>; + gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt"; + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1debug_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi>; +}; + +&ibt { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c1 { + status = "okay"; + + tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + occ-hwmon@50 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x50>; + }; +}; + +&i2c5 { + status = "okay"; + + occ-hwmon@51 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x51>; + }; +}; + +&i2c6 { + status = "okay"; + + w83795g@2f { + compatible = "nuvoton,w83795g"; + reg = <0x2f>; + }; +}; + +&i2c7 { + status = "okay"; + + occ-hwmon@56 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x56>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + occ-hwmon@57 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x57>; + }; +}; + +&i2c12 { + status = "okay"; + + rtc@68 { + compatible = "maxim,ds3231"; + reg = <0x68>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + cd-inverted; + disable-wp; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts new file mode 100644 index 000000000000..a20a532fc280 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts @@ -0,0 +1,704 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Witherspoon BMC"; + compatible = "ibm,witherspoon-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + vga_memory: region@9f000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32MM */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + event-fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + event-fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + event-fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; + }; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + }; + + front-power { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 14 GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 15 GPIO_ACTIVE_LOW>; + }; + + rear-fault { + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; + }; + + rear-id { + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; + }; + + rear-power { + gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; + }; + + power-button { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + + iio-hwmon-bmp280 { + compatible = "iio-hwmon"; + io-channels = <&bmp 1>; + }; + +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","air-water","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","","","", + /*E0-E7*/ "fsi-data","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power", + "led-rear-id","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","presence-ps0", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","fsi-trans","","","power-button","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "obmc-ubi"; + }; + }; + }; + + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&i2c2 { + status = "okay"; + + /* MUX -> + * Samtec 1 + * Samtec 2 + */ +}; + +&i2c3 { + status = "okay"; + + bmp: bmp280@77 { + compatible = "bosch,bmp280"; + reg = <0x77>; + #io-channel-cells = <1>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + + +&i2c5 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c9 { + status = "okay"; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c10 { + /* MUX + * -> PCIe Slot 3 + * -> PCIe Slot 4 + */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts new file mode 100644 index 000000000000..0cb7b20ff3ab --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Zaius BMC"; + compatible = "ingrasys,zaius-bmc", "aspeed,ast2500"; + + aliases { + i2c15 = &i2cpcie0; + i2c16 = &i2cpcie1; + i2c17 = &i2cpcie2; + i2c19 = &i2cpcie3; + i2c20 = &i2cpcie4; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + }; + + onewire0 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + }; + + onewire1 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + }; + + onewire2 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + }; + + onewire3 { + compatible = "w1-gpio"; + gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-pcie-e2b-present{ + label = "pcie-e2b-present"; + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + sys_boot_status { + label = "System boot status"; + gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>; + }; + + attention { + label = "Attention"; + gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; + }; + + plt_fault { + label = "Platform fault"; + gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>; + }; + + hdd_fault { + label = "Onboard drive fault"; + gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 13>, <&adc 14>, <&adc 15>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2cs0_default + &pinctrl_spi2cs1_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default>; + + flash@0 { + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; + + /* Power sequencer UCD90160 PMBUS @64h + * FRU AT24C64D @50h + * RTC PCF8523 @68h + * Clock buffer 9DBL04 @6dh + */ +}; + +&i2c1 { + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + i2cpcie0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2cpcie1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2cpcie2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2ctpm: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + /* MUX1 PCA9546A @71h + * PCIe 0 + * PCIe 1 + * PCIe 2 + * TPM header + */ +}; + +&i2c2 { + status = "disabled"; + + /* OCP Mezz Connector A (OOB SMBUS) */ +}; + +&i2c3 { + status = "disabled"; + + /* OCP Mezz Connector A (PCIe slot SMBUS) */ +}; + +&i2c4 { + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + i2cpcie3: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2cpcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + + /* MUX1 PCA9546A @71h + * PCIe 3 + * PCIe 4 + */ +}; + + +&i2c5 { + status = "disabled"; + + /* CPU0 PRM 0.7V */ + /* CPU0 PRM 1.2V CH03 */ + /* CPU0 PRM 0.8V */ + /* CPU0 PRM 1.2V CH47 */ +}; + +&i2c6 { + status = "disabled"; + + /* CPU1 PRM 0.7V */ + /* CPU1 PRM 1.2V CH03 */ + /* CPU1 PRM 0.8V */ + /* CPU1 PRM 1.2V CH47 */ +}; + +&i2c7 { + status = "okay"; + + pca9541a@70 { + compatible = "nxp,pca9541"; + reg = <0x70>; + + i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + hotswap@54 { + compatible = "ti,lm5066i"; + reg = <0x54>; + }; + }; + + }; + + vrm@64 { + compatible = "isil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "isil,isl68137"; + reg = <0x40>; + }; + + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + + vrm@43 { + compatible = "infineon,ir38064"; + reg = <0x43>; + }; + + vrm@41 { + compatible = "isil,isl68137"; + reg = <0x41>; + }; + + /* Master selector PCA9541A @70h (other master: CPU0) + * LM5066I PMBUS @10h + */ + + /* + * Brick will be one of these types/addresses. Depending + * on the board SKU only one is actually present and will successfully + * instantiate while the others will fail the probe operation. + * These are the PVT (and presumably beyond) addresses: + * 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah + * 12V Quarter Brick DC/DC Converter Q54SH12050 @30h + */ + power-brick@6a { + compatible = "delta,dps800"; + reg = <0x6a>; + }; + power-brick@30 { + compatible = "delta,dps800"; + reg = <0x30>; + }; + + /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ + /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ + /* CPU0 VR ISL68137 0.8V PMBUS @60h */ + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ + /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ + /* Master selector PCA9541A @70h (other master: CPU0) + * LM5066I PMBUS @10h + */ +}; + +&i2c8 { + status = "okay"; + + vrm@64 { + compatible = "isil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "isil,isl68137"; + reg = <0x40>; + }; + + vrm@41 { + compatible = "isil,isl68137"; + reg = <0x41>; + }; + + vrm@42 { + compatible = "infineon,ir38064"; + reg = <0x42>; + }; + + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ + /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ + /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ + /* CPU1 VR ISL68137 0.8V PMBUS @60h */ +}; + + +&i2c9 { + status = "disabled"; + + /* Fan board */ +}; + +&i2c10 { + status = "disabled"; +}; + +&i2c11 { + status = "disabled"; + + /* GPU sideband */ +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; + + /* MUX PI3USB102 + * CPU0 debug + * CPU1 debug + */ +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; + + pinctrl_gpioh_unbiased: gpioi_unbiased { + pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7"; + bias-disable; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioh_unbiased>; + + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention", + "led-fault", + /*E0-E7*/ "","","","","","","","presence-pcie-e2b", + /*F0-F7*/ "","","","","","","","checkstop", + /*G0-G7*/ "fsi-clock","fsi-data","","","","","","", + /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","", + /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","", + "","fsi-mux","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","led-hdd-fault","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + + line_iso_u146_en { + gpio-hog; + gpios = ; + output-high; + }; + + ncsi_mux_en_n { + gpio-hog; + gpios = ; + output-low; + }; + + line_bmc_i2c2_sw_rst_n { + gpio-hog; + gpios = ; + output-high; + }; + + line_bmc_i2c5_sw_rst_n { + gpio-hog; + gpios = ; + output-high; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; +}; + +&ibt { + status = "okay"; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts new file mode 100644 index 000000000000..a5e64ccc2b3a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Facebook Inc. +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Portwell Neptune BMC"; + compatible = "portwell,neptune-bmc", "aspeed,ast2500"; + aliases { + serial0 = &uart1; + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + postcode0 { + label = "BMC_UP"; + gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + postcode1 { + label = "BMC_HB"; + gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + postcode2 { + label = "FAULT"; + gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + }; + // postcode3-7 are GPIOH3-H7 + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart1 { + // Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart5 { + // BMC Console + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default + &pinctrl_mdio1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii2_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, + <&syscon ASPEED_CLK_MAC2RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&i2c1 { + status = "okay"; + // To PCIe slot SMBUS +}; + +&i2c2 { + status = "okay"; + // To LAN I210 +}; + +&i2c3 { + status = "okay"; + // SMBus to COMe AB +}; + +&i2c4 { + status = "okay"; + // I2C to COMe AB +}; + +&i2c5 { + status = "okay"; +// USB Debug card + pca9555@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c6 { + status = "okay"; + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c8 { + status = "okay"; + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts new file mode 100644 index 000000000000..259ef3f54c5c --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + +/dts-v1/; + +#include "aspeed-g6.dtsi" + +/ { + model = "Qualcomm DC-SCM V1 BMC"; + compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac2 { + status = "okay"; + + /* Bootloader sets up the MAC to insert delay */ + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + + use-ncsi; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <133000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <133000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <133000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","", + /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3", + "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3", + "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*A0-A7*/ "GPI_1_BMC_1V8","","","","","", + "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8", + /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8", + "SCMFPGA_SPARE_GPIO5_1V8","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","", + "","TPM2_PIRQ_N","TPM2_RST_N","", + /*E0-E7*/ "","","","","","","",""; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts new file mode 100644 index 000000000000..9605e53f5bbf --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "aspeed-g4.dtsi" +#include + +/ { + model = "Quanta Q71L BMC"; + compatible = "quanta,q71l-bmc", "aspeed,ast2400"; + + aliases { + i2c14 = &i2c_pcie2; + i2c15 = &i2c_pcie3; + i2c16 = &i2c_pcie6; + i2c17 = &i2c_pcie7; + i2c18 = &i2c_pcie1; + i2c19 = &i2c_pcie4; + i2c20 = &i2c_pcie5; + i2c21 = &i2c_pcie8; + i2c22 = &i2c_pcie9; + i2c23 = &i2c_pcie10; + i2c24 = &i2c_ssd1; + i2c25 = &i2c_ssd2; + i2c26 = &i2c_psu4; + i2c27 = &i2c_psu1; + i2c28 = &i2c_psu3; + i2c29 = &i2c_psu2; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@40000000 { + reg = <0x40000000 0x8000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@47800000 { + no-map; + reg = <0x47800000 0x00800000>; /* 8MB */ + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 11>; + }; + + i2c1mux: i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */ + i2c-parent = <&i2c1>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default + &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +}; + +&p2a { + status = "okay"; + memory-region = <&vga_memory>; +}; + +&ibt { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&uart1 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + /* temp2 inlet */ + tmp75@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + + /* temp3 */ + tmp75@4e { + compatible = "ti,tmp75"; + reg = <0x4e>; + }; + + /* temp1 */ + tmp75@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; + + /* Baseboard FRU */ + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; + + /* FP FRU */ + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; +}; + +&i2c2 { + status = "okay"; + + /* 0: PCIe Slot 2, + * Slot 3, + * Slot 6, + * Slot 7 + */ + i2c-switch@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; /* may use mux@77 next. */ + + i2c_pcie2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_pcie3: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_pcie6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_pcie7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + /* 0: PCIe Slot 1, + * Slot 4, + * Slot 5, + * Slot 8, + * Slot 9, + * Slot 10, + * SSD 1, + * SSD 2 + */ + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; /* may use mux@74 next. */ + + i2c_pcie1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_pcie5: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_pcie8: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_pcie9: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_pcie10: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_ssd1: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c_ssd2: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; + + /* BIOS FRU */ + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + /* 0: PSU4 + * PSU1 + * PSU3 + * PSU2 + */ + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_psu4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + psu@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + }; + + i2c_psu1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + }; + + i2c_psu3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + }; + + i2c_psu2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + psu@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + }; + }; + + /* PDB FRU */ + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; +}; + +&i2c8 { + status = "okay"; + + /* BMC FRU */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&vuart { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c1mux { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Memory Riser 1 FRU */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* Memory Riser 2 FRU */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* Memory Riser 3 FRU */ + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Memory Riser 4 FRU */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Memory Riser 5 FRU */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* Memory Riser 6 FRU */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* Memory Riser 7 FRU */ + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Memory Riser 8 FRU */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts new file mode 100644 index 000000000000..46cbba6305b8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Quanta Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Quanta S6Q BMC"; + compatible = "quanta,s6q-bmc", "aspeed,ast2600"; + + aliases { + // bus 0 + i2c20 = &SMB_HOST_DB2000_3V3AUX_SCL; + i2c21 = &U12_PCA9546_CH1; + i2c22 = &SMB_HOST_DB800_B_SCL; + i2c23 = &SMB_HOST_DB800_C_SCL; + + // bus 1 + i2c24 = &SMB_M2_P0_1V8AUX_SCL; + i2c25 = &SMB_M2_P1_1V8AUX_SCL; + i2c26 = &SMB_CPU_PIROM_3V3AUX_SCL; + i2c27 = &SMB_TEMP_3V3AUX_SCL; + i2c28 = &SMB_IPMB_3V3AUX_SSDSB_SCL; + i2c29 = &SMB_IPMB_3V3AUX_SCL; + i2c31 = &SMB_FB_SCL; + + // bus 1 - Fan board + i2c32 = &SMB_IOEXP_SCL; + i2c33 = &SMB_PROGRAM_SCL; + i2c34 = &SMB_FB_SCL_CH2; + i2c35 = &SMB_FAN_SENSE_SCL; + + // bus 6 + i2c36 = &U197_PCA9546_CH0; + i2c37 = &U197_PCA9546_CH1; + i2c38 = &U197_PCA9546_CH2; + i2c39 = &U197_PCA9546_CH3; + + //bus 7 + i2c40 = &SMB_OCP_SFF_3V3AUX_SCL; //OCP1 + i2c41 = &SMB_OCP_LFF_3V3AUX_SCL; //OCP2 + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + leds { + compatible = "gpio-leds"; + + BMC_HEARTBEAT_N { + label = "BMC_HEARTBEAT_N"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + BMC_LED_STATUS_AMBER_N { + label = "BMC_LED_STATUS_AMBER_N"; + gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + FM_ID_LED_N { + label = "FM_ID_LED_N"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0 - A7*/ "", "", "", "", "", "", "", "", + /*B0 - B7*/ "", "", "", "", "", "", "", "", + /*C0 - C7*/ "", "", "", "", "", "", "", "", + /*D0 - D7*/ "", "", "", "", "", "", "", "", + /*E0 - E7*/ "", "", "", "", "", "", "", "", + /*F0 - F7*/ "PLTRST_N", "", "PWR_DEBUG_N", "", "", "", "", "", + /*G0 - G7*/ "", "", "", "", "", "", "", "", + /*H0 - H7*/ "", "", "", "", "", "", "", "", + /*I0 - I7*/ "", "", "", "", "", "", "", "", + /*J0 - J7*/ "", "", "", "", "", "", "", "", + /*K0 - K7*/ "", "", "", "", "", "", "", "", + /*L0 - L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "", + /*M0 - M7*/ "", "", "", "PWRGD_SYS_PWROK", "", "PRDY_N", "", "", + /*N0 - N7*/ "", "", "", "", "", "", "", "", + /*O0 - O7*/ "", "", "", "", "", "", "", "", + /*P0 - P7*/ "SYS_BMC_PWRBTN_R_N", "SYS_PWRBTN_N", "FM_MB_RST_BTN", "RST_BMC_RSTBTN_OUT_N", "", "", "", "", + /*Q0 - Q7*/ "", "", "", "", "", "", "", "", + /*R0 - R7*/ "", "", "", "", "", "", "", "", + /*S0 - S7*/ "", "", "", "FP_ID_BTN_SCM_N", "", "", "", "", + /*T0 - T7*/ "", "", "", "", "", "", "", "", + /*U0 - U7*/ "", "", "", "", "", "", "", "", + /*V0 - V7*/ "", "", "", "", "", "SMI", "", "", + /*W0 - W7*/ "", "", "", "", "", "", "", "", + /*X0 - X7*/ "", "", "", "", "", "", "", "", + /*Y0 - Y7*/ "", "", "", "", "", "", "", "", + /*Z0 - Z7*/ "FM_BMC_READY_N", "", "", "", "", "", "", "", + /*AA0 - AA7*/ "", "", "", "", "", "", "", "", + /*AB0 - AB7*/ "", "", "", "", "", "", "", "", + /*AC0 - AC7*/ "", "", "", "", "", "", "", ""; +}; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; + bus-frequency = <48000>; + gpio-line-names = + /* SGPIO input lines */ + /*IOA0-IOA7*/ "","", "SIO_POWER_GOOD","OA1", "XDP_PRST_N","", "","", "FM_SLPS3_PLD_N","", "FM_SLPS4_PLD_N","", "FM_BIOS_POST_CMPLT_BMC_N","", "FM_ADR_TRIGGER_N","OA7", + /*IOB0-IOB7*/ "FM_ADR_COMPLETE","", "FM_PMBUS_ALERT_B_EN","", "PSU0_PRESENT_N","", "PSU1_PRESENT_N","", "PSU0_VIN_BUF_GOOD","", "PSU01_VIN_BUF_GOOD","", "PWRGD_PS0_PWROK_R","", "PWRGD_PS1_PWROK_R","", + /*IOC0-IOC7*/ "PWRGD_PS_PWROK_PLD_R","", "CHASSIS_INTRUSION","", "BMC_MFG_MODE","", "FM_BMC_EN_DET_R","", "FM_ME_BT_DONE","", "CPU1_PRESENCE","", "CPU2_PRESENCE","", "IRQ_PSYS_CRIT_N","", + /*IOD0-IOD7*/ "","", "CPU1_THERMTRIP","", "CPU2_THERMTRIP","", "CPU1_MEM_THERM_EVENT","", "CPU2_MEM_THERM_EVENT","", "CPU1_VRHOT","", "CPU2_VRHOT","", "","", + /*IOE0-IOE7*/ "","", "CPU1_MEM_VRHOT","", "CPU2_MEM_VRHOT","", "","", "PCH_BMC_THERMTRIP","", "","", "","", "","", + /*IOF0-IOF7*/ "CPU_ERR0","", "CPU_ERR1","", "CPU_ERR2","", "","", "","", "CPU_CATERR","", "","", "","", + /*IOG0-IOG7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOH0-IOH7*/ "","", "FP_ID_BTN_R1_N","", "FP_RST_BTN_N","", "","", "","", "FP_PWR_BTN_PLD_N_R","", "","", "","", + /*IOI0-IOI7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOJ0-IOJ7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOK0-IOK7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOL0-IOL7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOM0-IOM7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*ION0-ION7*/ "","BMC_SW_HEARTBEAT_N_R", "","FP_LED_FAULT_N", "","FP_ID_LED_N", "","FM_BMC_RSTBTN_OUT_N", "","FM_THERMTRIP_DLY_LVC1_R_N", "","", "","RST_PCA9548_SENSOR_PLD_N", "","USB_OC1_REAR_N", + /*IOO0-IOO7*/ "","IRQ_TPM_SPI_N", "","", "","IRQ_PCH_SCI_WHEA_R_N", "","IRQ_BMC_PCH_NMI_R", "","H_CPU_NMI_LVC1_R_N", "","", "","", "","FM_JTAG_BMC_PLD_MUX_SEL", + /*IOP0-IOP7*/ "IP0","OP0", "","", "","", "","", "","", "","", "","", "IP7","OP7"; +}; + +&adc0 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac2 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + phy-mode = "rmii"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default + &pinctrl_spi2cs2_default>; + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi2:0"; + spi-max-frequency = <50000000>; + }; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA0>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA2>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <100000000>; +}; + +&vhub { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + U34_PWR_ADC@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + U35_PWR_ADC@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_HOST_DB2000_3V3AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + U12_PCA9546_CH1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_HOST_DB800_B_SCL: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_HOST_DB800_C_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + i2c-switch@59 { + compatible = "nxp,pca9848"; + reg = <0x59>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_M2_P0_1V8AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_M2_P1_1V8AUX_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_CPU_PIROM_3V3AUX_SCL: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_TEMP_3V3AUX_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + U163_tmp75@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + U114_tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + SMB_IPMB_3V3AUX_SSDSB_SCL: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + U4_tmp75@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + U73_tmp75@4d { + compatible = "ti,tmp75"; + reg = <0x4d>; + }; + }; + + SMB_IPMB_3V3AUX_SCL: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + U190_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + }; + + SMB_FB_SCL: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-switch@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_IOEXP_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_PROGRAM_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_FB_SCL_CH2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_FAN_SENSE_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + Current_Meter_U2@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <1000>; /* = 1 mOhm */ + }; + + Current_Meter_U3@44 { + compatible = "ti,ina219"; + reg = <0x44>; + shunt-resistor = <1000>; /* = 1 mOhm */ + }; + + TEMP_sensor_U2@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + bus-frequency = <400000>; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + status = "okay"; + + /* MB FRU (U173) @ 0xA2 */ + mb_fru: mb_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + /* FP_U1 Inlet */ + FP_U1_tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + + FP_U4_fru@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + U197_PCA9546_CH0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + U197_PCA9546_CH1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + cpu0_pvccin@60 { + compatible = "isil,raa229004"; + reg = <0x60>; + }; + + cpu0_pvccinfaon@61 { + compatible = "isil,isl69260"; + reg = <0x61>; + }; + + cpu0_pvccd_hv@63 { + compatible = "isil,isl69260"; + reg = <0x63>; + }; + }; + + U197_PCA9546_CH2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + cpu1_pvccin@72 { + compatible = "isil,raa229004"; + reg = <0x72>; + }; + + cpu1_pvccinfaon@74 { + compatible = "isil,isl69260"; + reg = <0x74>; + }; + + cpu1_pvccd_hv@76 { + compatible = "isil,isl69260"; + reg = <0x76>; + }; + }; + + U197_PCA9546_CH3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + SMB_OCP_SFF_3V3AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_OCP_LFF_3V3AUX_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; + + /* SCM FRU (U19) @ 0xA2 */ + scm_fru: scm_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + scm_tmp75_u4@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; +}; + +&i2c15 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts new file mode 100644 index 000000000000..50f3c6a5c0c8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Super Micro Computer, Inc + +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "X11SPI BMC"; + compatible = "supermicro,x11spi-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@7f000000 { + no-map; + reg = <0x7f000000 0x01000000>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + +}; + +&gpio { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default &pinctrl_pwm7_default>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts new file mode 100644 index 000000000000..aff27c1d4b06 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Tyan S7106 BMC"; + compatible = "tyan,s7106-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + p2a_memory: region@987f0000 { + no-map; + reg = <0x987f0000 0x00010000>; /* 64KB */ + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; /* 16M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + label = "bmc"; + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* RS-232 connector on header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + /* Alternative to vuart to internally connect (route) to uart1 + * when vuart cannot be used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart4 { + /* Alternative to vuart to internally connect (route) to the + * external port usually used by uart1 when vuart cannot be + * used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart5 { + /* BMC "debug" (console) UART; connected to RS-232 connector + * on header; selectable via jumpers as alternative to uart2 + */ + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&vuart { + status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&p2a { + status = "okay"; + memory-region = <&p2a_memory>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&adc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + /* CPU fan #0 */ + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + /* CPU fan #1 */ + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + /* PWM group for chassis fans #1, #2, #3 and #4 */ + fan@2 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + /* PWM group for chassis fans #5 and #6 */ + fan@6 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c0 { + status = "okay"; + + /* Hardware monitor with temperature sensors */ + nct7802@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + sensor-type = "temperature"; + }; + }; + + /* Also connected to: + * - IPMB pin header + * - CPU #0 memory error LED @ 0x3A + * - CPU #1 memory error LED @ 0x3C + */ +}; + +&i2c1 { + /* Directly connected to PCH SMBUS #0 */ + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* BMC EEPROM, incl. mainboard FRU */ + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + /* Also connected to: + * - fan header + * - mini-SAS HD connector + * - SSATA SGPIO + * - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low) + * to PCH SMBUS #3 + */ +}; + +&i2c3 { + status = "okay"; + + /* PSU1 FRU @ 0xA0 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* PSU2 FRU @ 0xA2 */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* PSU1 @ 0xB0 */ + power-supply@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + /* PSU2 @ 0xB2 */ + power-supply@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + + /* Also connected to: + * - PCH SMBUS #1 + */ +}; + +&i2c4 { + status = "okay"; + + /* Connected to: + * - PCH SMBUS #2 + */ + + /* Connected via switch to: + * - CPU #0 channels ABC VDDQ @ 0x80 + * - CPU #0 channels DEF VDDQ @ 0x81 + * - CPU #1 channels ABC VDDQ @ 0x82 + * - CPU #1 channels DEF VDDQ @ 0x83 + * - CPU #0 VCCIO & VMCP @ 0x52 + * - CPU #1 VCCIO & VMCP @ 0x53 + * - CPU #0 VCCIN @ 0xC0 + * - CPU #0 VSA @ 0xC2 + * - CPU #1 VCCIN @ 0xC4 + * - CPU #1 VSA @ 0xC6 + * - J110 + */ +}; + +&i2c5 { + status = "okay"; + + /* Connected via switch (PCH_BMC_SMB_SW_P) to: + * - mainboard FRU @ 0xAE + * - XDP connector + * - ME debug header + * - clock buffer @ 0xD8 + * - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH) + * - PCH SMBUS + */ +}; + +&i2c6 { + status = "okay"; + + /* Connected via switch (BMC_PE_SMB_EN_1_N) to + * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to: + * - 0,0: PCIE slot 1, SMB #1 + * - 0,1: PCIE slot 1, SMB #2 + * - 1,0: PCIE slot 2, SMB #1 + * - 1,1: PCIE slot 2, SMB #2 + */ + + /* Connected via switch (BMC_PE_SMB_EN_2_N) to + * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to: + * - 0,0: OCP0 (A) SMB + * - 0,1: OCP0 (C) SMB + * - 1,0: OCP1 (A) SMB + * - 1,1: NC + */ +}; + +&i2c7 { + status = "okay"; + + /* Connected to: + * - PCH SMBUS #4 + */ +}; + +&i2c8 { + status = "okay"; + + /* Not connected */ +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&ibt { + status = "okay"; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +/* We're following the GPIO naming as defined at + * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. + * + * Notes on led-identify and id-button: + * - A physical button is connected to id-button which + * triggers the clock on a D flip-flop. The /Q output of the + * flip-flop drives its D input. + * - The flip-flop's Q output drives led-identify which is + * connected to LEDs. + * - With that, every button press toggles the LED between on and off. + * + * Notes on power-, reset- and nmi- button and control: + * - The -button signals can be used to monitor physical buttons. + * - The -control signals can be used to actuate the specific + * operation. + * - In hardware, the -button signals are connected to the -control + * signals through drivers with the -control signals being + * protected through diodes. + */ +&gpio { + status = "okay"; + gpio-line-names = + /*A0*/ "", + /*A1*/ "", + /*A2*/ "led-identify", /* in/out: BMC_IDLED_ON_N */ + /*A3*/ "", + /*A4*/ "", + /*A5*/ "", + /*A6*/ "", + /*A7*/ "", + /*B0-B7*/ "","","","","","","","", + /*C0*/ "", + /*C1*/ "", + /*C2*/ "", + /*C3*/ "", + /*C4*/ "id-button", /* in/out: BMC_IDBTN_IN_OUT_N */ + /*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */ + /*C6*/ "", + /*C7*/ "", + /*D0*/ "", + /*D1*/ "", + /*D2*/ "power-chassis-good", /* in: SYS_PWROK_BUF */ + /*D3*/ "platform-reset", /* in: SYS_PLTRST_N */ + /*D4*/ "", + /*D5*/ "", + /*D6*/ "", + /*D7*/ "", + /*E0*/ "power-button", /* in: BMC_PWBTN_IN_N */ + /*E1*/ "power-chassis-control", /* out: BMC_PWRBTN_OUT_N */ + /*E2*/ "reset-button", /* in: BMC_RSTBTN_IN_N */ + /*E3*/ "reset-control", /* out: BMC_RSTBTN_OUT_N */ + /*E4*/ "nmi-button", /* in: BMC_NMIBTN_IN_N */ + /*E5*/ "nmi-control", /* out: BMC_NMIBTN_OUT_N */ + /*E6*/ "", + /*E7*/ "led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */ + /*F0*/ "", + /*F1*/ "clear-cmos-control", /* out: BMC_CLR_CMOS_N */ + /*F2*/ "", + /*F3*/ "", + /*F4*/ "led-fault", /* out: AST_HW_FAULT_N */ + /*F5*/ "", + /*F6*/ "", + /*F7*/ "", + /*G0*/ "BMC_PE_SMB_EN_1_N", /* out */ + /*G1*/ "BMC_PE_SMB_EN_2_N", /* out */ + /*G2*/ "", + /*G3*/ "", + /*G4*/ "", + /*G5*/ "", + /*G6*/ "", + /*G7*/ "", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0*/ "", + /*Q1*/ "", + /*Q2*/ "", + /*Q3*/ "", + /*Q4*/ "BMC_PE_SMB_SW_BIT0", /* out */ + /*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */ + /*Q6*/ "", + /*Q7*/ "", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0*/ "", + /*AA1*/ "", + /*AA2*/ "", + /*AA3*/ "BMC_SMB3_PCH_IE_SML3_EN", /* out */ + /*AA4*/ "", + /*AA5*/ "", + /*AA6*/ "", + /*AA7*/ "", + /*AB0-AB7*/ "","","","","","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts new file mode 100644 index 000000000000..f6c4549c0ac4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Tyan S8036 BMC"; + compatible = "tyan,s8036-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + p2a_memory: region@987f0000 { + no-map; + reg = <0x987f0000 0x00010000>; /* 64KB */ + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; /* 16M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + label = "bmc"; + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* RS-232 connector on header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + /* Alternative to vuart to internally connect (route) to uart1 + * when vuart cannot be used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart4 { + /* Alternative to vuart to internally connect (route) to the + * external port usually used by uart1 when vuart cannot be + * used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart5 { + /* BMC "debug" (console) UART; connected to RS-232 connector + * on header; selectable via jumpers as alternative to uart2 + */ + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&vuart { + status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&p2a { + status = "okay"; + memory-region = <&p2a_memory>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&adc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + /* CPU fan */ + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + /* PWM group for chassis fans #1, #2, #3 and #4 */ + fan@2 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + /* PWM group for chassis fans #5 and #6 */ + fan@6 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c0 { + /* Directly connected to Sideband-Temperature Sensor Interface (APML) */ + status = "okay"; +}; + +&i2c1 { + /* Directly connected to IPMB HDR. */ + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* BMC EEPROM, incl. mainboard FRU */ + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + /* Also connected to: + * - BCM5720 + * - FPGA + * - FAN HDR + * - FPIO HDR + */ +}; + +&i2c3 { + status = "okay"; + + /* PSU1 FRU @ 0xA0 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* PSU2 FRU @ 0xA2 */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* PSU1 @ 0xB0 */ + power-supply@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + /* PSU2 @ 0xB2 */ + power-supply@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + /* Hardware monitor with temperature sensors */ + nct7802@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + status = "okay"; + sensor-type = "temperature"; + }; + }; + + /* Also connected to: + * - PCA9544 + * - CLK BUFF + * - OCP FRU + */ +}; + +&i2c6 { + status = "okay"; + /* Connected to: + * - PCA9548 @0xE0 + * - PCA9548 @0xE2 + * - PCA9544 @0xE4 + */ +}; + +&i2c7 { + status = "okay"; + + /* Connected to: + * - PCH SMBUS #4 + */ +}; + +&i2c8 { + status = "okay"; + + /* Not connected */ +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&ibt { + status = "okay"; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; +}; + +/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +/* We're following the GPIO naming as defined at + * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. + * + * Notes on led-identify and id-button: + * - A physical button is connected to id-button which + * triggers the clock on a D flip-flop. The /Q output of the + * flip-flop drives its D input. + * - The flip-flop's Q output drives led-identify which is + * connected to LEDs. + * - With that, every button press toggles the LED between on and off. + * + * Notes on power-, reset- and nmi- button and control: + * - The -button signals can be used to monitor physical buttons. + * - The -control signals can be used to actuate the specific + * operation. + * - In hardware, the -button signals are connected to the -control + * signals through drivers with the -control signals being + * protected through diodes. + */ +&gpio { + status = "okay"; + gpio-line-names = + /*A0*/ "", + /*A1*/ "", + /*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */ + /*A3*/ "", + /*A4*/ "", + /*A5*/ "", + /*A6*/ "", + /*A7*/ "", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0*/ "", + /*D1*/ "", + /*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/ + /*D3*/ "platform-reset", /* in: RESET_LED_L */ + /*D4*/ "", + /*D5*/ "", + /*D6*/ "", + /*D7*/ "", + /*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */ + /*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */ + /*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/ + /*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */ + /*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */ + /*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */ + /*E6*/ "TSI_RESERT", + /*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */ + /*F0*/ "", + /*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */ + /*F2*/ "", + /*F3*/ "", + /*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */ + /*F5*/ "BMC_SYS_FAULT_LED_L", + /*F6*/ "BMC_ASSERT_BIOS_WP_L", + /*F7*/ "", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0*/ "", + /*Q1*/ "", + /*Q2*/ "", + /*Q3*/ "", + /*Q4*/ "", + /*Q5*/ "", + /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */ + /*Q7*/ "", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z2*/ "","","", + /*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */ + /*Z4-Z7*/ "","","","", + /*AA0*/ "", + /*AA1*/ "", + /*AA2*/ "", + /*AA3*/ "", + /*AA4*/ "", + /*AA5*/ "", + /*AA6*/ "", + /*AA7*/ "BMC_ASSERT_BMC_READY", + /*AB0*/ "BMC_SPD_SEL", + /*AB1-AB7*/ "","","","","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts new file mode 100644 index 000000000000..7ab29129d1e4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2022 Ufispace Co., Ltd. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Ufispace NCPLite BMC"; + compatible = "ufispace,ncplite-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + fan-status-int-l { + label = "fan-status-int-l"; + gpios = <&gpio0 ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + allpwr-good { + label = "allpwr-good"; + gpios = <&gpio0 ASPEED_GPIO(V, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + psu0-alert-n { + label = "psu0-alert-n"; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1-alert-n { + label = "psu1-alert-n"; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + int-thermal-alert { + label = "int-thermal-alert"; + gpios = <&gpio0 ASPEED_GPIO(P, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + cpu-caterr-l { + label = "cpu-caterr-l"; + gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + cpu-thermtrip-l { + label = "cpu-thermtrip-l"; + gpios = <&gpio0 ASPEED_GPIO(V, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu0-presence-l { + label = "psu0-presence-l"; + gpios = <&gpio0 ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1-presence-l { + label = "psu1-presence-l"; + gpios = <&gpio0 ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu0-power-ok { + label = "psu0-power-ok"; + gpios = <&gpio0 ASPEED_GPIO(M, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + psu1-power-ok { + label = "psu1-power-ok"; + gpios = <&gpio0 ASPEED_GPIO(M, 5) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&fan_ioexp 2 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&fan_ioexp 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&fan_ioexp 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&fan_ioexp 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + }; +}; + +&mac2 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_reset { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&peci0 { + status = "okay"; +}; + +&udc { + status = "okay"; +}; + +&adc0 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + lm75@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + lm86@4c { + compatible = "national,lm86"; + reg = <0x4c>; + }; +}; + +&i2c2 { + status = "okay"; + + lm75@4f { + cpmpatible = "national,lm75"; + reg = <0x4f>; + }; + + fan_ioexp: pca9535@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","","presence-fan0","", + "","","presence-fan1","", + "","","presence-fan2","", + "","","presence-fan3",""; + }; +}; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c4 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <1>; + }; +}; + +&i2c5 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <1>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&gpio0 { + status = "okay"; + + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "CPU_PWRGD","","","power-button","host0-ready","","presence-ps0","presence-ps1", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","reset-button","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","power-chassis-good","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts new file mode 100644 index 000000000000..24319267d550 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN N110 BMC"; + compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", + /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", + /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", + /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts new file mode 100644 index 000000000000..ebbb68b55559 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Rx20 BMC"; + compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500"; + + leds { + compatible = "gpio-leds"; + + temp_alarm { + label = "temp:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>; + }; + + temp_ok { + label = "temp:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + }; + + psu_fault { + label = "psu:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>; + }; + + psu_ok { + label = "psu:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N", + /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", ""; + }; + gpio@23 { + compatible = "nxp,pcal9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "", + /*IO1.0-1.7*/ "", "", "", "", "", "", "", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1"; + }; + gpio@39 { + compatible = "nxp,pca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + rsra-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + }; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rsrb-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts new file mode 100644 index 000000000000..e36ee4704994 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Sx20 BMC"; + compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", + /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi new file mode 100644 index 000000000000..1a5b25b2ea29 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO + +#include "aspeed-g5.dtsi" +#include + +/ { + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + ramoops@9eff0000{ + compatible = "ramoops"; + reg = <0x9eff0000 0x10000>; + record-size = <0x2000>; + console-size = <0x2000>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + + identify { + label = "platform:blue:indicator"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + }; + + status_amber { + label = "platform:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "platform:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; + }; + + power_fault { + label = "platform:red:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; + }; + + power_ok { + label = "platform:green:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&timer 5 1000000 0>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; + flash@0 { + status = "okay"; + label = "bios"; + m25p,fast-read; + }; +}; + +&mac0 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + phy-mode = "rgmii"; + phy-handle = <&phy>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + /* KSZ9131 */ + compatible = "ethernet-phy-id0022.1640"; + reg = <1>; + + micrel,led-mode = <0>; + }; + }; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + disable-wp; +}; + +&timer { + fttmr010,pwm-outputs = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_timer5_default>; + #pwm-cells = <3>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&i2c0 { + /* SMB_IPMB_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c1 { + /* SMB_CHASSENSOR_STBY_LVC3 */ + status = "okay"; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + status = "okay"; +}; + +&i2c3 { + /* SMB_HOST_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c4 { + /* BMC_PMBUS2_STBY */ + status = "okay"; +}; + +&i2c5 { + /* SMB_SMLINK0_STBY_LVC3 */ + bus-frequency = <1000000>; + multi-master; + status = "okay"; +}; + +&i2c6 { + /* SMB_TEMPSENSOR_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c7 { + /* SMB_SM_PMB1_SML1_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c9 { + /* SMB_BMC_ETH3_LVC3 */ + status = "okay"; +}; + +&i2c10 { + /* SMB_BMC_ETH2_LVC3 */ + status = "okay"; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; +}; + +&i2c12 { + /* SMB_BMC_FAULT_EXP_LVC3 */ + status = "okay"; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi new file mode 100644 index 000000000000..530491ae5eb2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi @@ -0,0 +1,1453 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2400"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fmc: spi@1e620000 { + reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@3 { + reg = < 3 >; + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@4 { + reg = < 4 >; + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + spi: spi@1e630000 { + reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xffffffff 0x0007ffff>; + reg = <0x1e6c0080 0x80>; + }; + + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; + valid-sources = <0x7fffffff>; + reg = <0x1e6c2000 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; + status = "disabled"; + }; + + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2400-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2h_default>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2400-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = <14>; + #ports = <3>; + clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; + status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an explicit pinmux + * override if you don't enable EHCI + */ + }; + + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2400-usb-vhub"; + reg = <0x1e6a0000 0x300>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + aspeed,vhub-downstream-ports = <5>; + aspeed,vhub-generic-endpoints = <15>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2d_default>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e6e2000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + + p2a: p2a-control@2c { + reg = <0x2c 0x4>; + compatible = "aspeed,ast2400-p2a-ctrl"; + status = "disabled"; + }; + + silicon-id@7c { + compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>; + }; + + pinctrl: pinctrl@80 { + reg = <0x80 0x18>, <0xa0 0x10>; + compatible = "aspeed,ast2400-pinctrl"; + }; + }; + + rng: hwrng@1e6e2078 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2078 0x4>; + period = <1>; + quality = <100>; + }; + + adc: adc@1e6e9000 { + compatible = "aspeed,ast2400-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sram: sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x8000>; // 32K + }; + + video: video@1e700000 { + compatible = "aspeed,ast2400-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <7>; + status = "disabled"; + }; + + sdmmc: sd-controller@1e740000 { + compatible = "aspeed,ast2400-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@100 { + compatible = "aspeed,ast2400-sdhci"; + reg = <0x100 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@200 { + compatible = "aspeed,ast2400-sdhci"; + reg = <0x200 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2400-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + interrupts = <16 17 18 35 36 37 38 39>; + clocks = <&syscon ASPEED_CLK_APB>; + clock-names = "PCLK"; + }; + + rtc: rtc@1e781000 { + compatible = "aspeed,ast2400-rtc"; + reg = <0x1e781000 0x18>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + no-loopback-test; + status = "disabled"; + }; + + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785000 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + }; + + wdt2: watchdog@1e785020 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785020 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2400-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + clocks = <&syscon ASPEED_CLK_24M>; + resets = <&syscon ASPEED_RESET_PWM>; + status = "disabled"; + }; + + vuart: serial@1e787000 { + compatible = "aspeed,ast2400-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; + no-loopback-test; + status = "disabled"; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2400-lpc-ctrl"; + reg = <0x80 0x10>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_snoop: lpc-snoop@90 { + compatible = "aspeed,ast2400-lpc-snoop"; + reg = <0x90 0x8>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lhc: lhc@a0 { + compatible = "aspeed,ast2400-lhc"; + reg = <0xa0 0x24 0xc8 0x8>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2400-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + ibt: ibt@140 { + compatible = "aspeed,ast2400-ibt-bmc"; + reg = <0x140 0x18>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + uart_routing: uart-routing@9c { + compatible = "aspeed,ast2400-uart-routing"; + reg = <0x9c 0x4>; + status = "disabled"; + }; + }; + + peci0: peci-controller@1e78b000 { + compatible = "aspeed,ast2400-peci"; + reg = <0x1e78b000 0x60>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + cmd-timeout-ms = <1000>; + clock-frequency = <1000000>; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; + no-loopback-test; + status = "disabled"; + }; + + i2c: bus@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +}; + +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2400-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; + +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; + + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; + + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; + + pinctrl_extrst_default: extrst_default { + function = "EXTRST"; + groups = "EXTRST"; + }; + + pinctrl_flack_default: flack_default { + function = "FLACK"; + groups = "FLACK"; + }; + + pinctrl_flbusy_default: flbusy_default { + function = "FLBUSY"; + groups = "FLBUSY"; + }; + + pinctrl_flwp_default: flwp_default { + function = "FLWP"; + groups = "FLWP"; + }; + + pinctrl_gpid_default: gpid_default { + function = "GPID"; + groups = "GPID"; + }; + + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; + + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; + + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; + + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; + + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; + + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; + + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; + + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_ndts4_default: ndts4_default { + function = "NDTS4"; + groups = "NDTS4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rom16_default: rom16_default { + function = "ROM16"; + groups = "ROM16"; + }; + + pinctrl_rom8_default: rom8_default { + function = "ROM8"; + groups = "ROM8"; + }; + + pinctrl_romcs1_default: romcs1_default { + function = "ROMCS1"; + groups = "ROMCS1"; + }; + + pinctrl_romcs2_default: romcs2_default { + function = "ROMCS2"; + groups = "ROMCS2"; + }; + + pinctrl_romcs3_default: romcs3_default { + function = "ROMCS3"; + groups = "ROMCS3"; + }; + + pinctrl_romcs4_default: romcs4_default { + function = "ROMCS4"; + groups = "ROMCS4"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_sgpmck_default: sgpmck_default { + function = "SGPMCK"; + groups = "SGPMCK"; + }; + + pinctrl_sgpmi_default: sgpmi_default { + function = "SGPMI"; + groups = "SGPMI"; + }; + + pinctrl_sgpmld_default: sgpmld_default { + function = "SGPMLD"; + groups = "SGPMLD"; + }; + + pinctrl_sgpmo_default: sgpmo_default { + function = "SGPMO"; + groups = "SGPMO"; + }; + + pinctrl_sgpsck_default: sgpsck_default { + function = "SGPSCK"; + groups = "SGPSCK"; + }; + + pinctrl_sgpsi0_default: sgpsi0_default { + function = "SGPSI0"; + groups = "SGPSI0"; + }; + + pinctrl_sgpsi1_default: sgpsi1_default { + function = "SGPSI1"; + groups = "SGPSI1"; + }; + + pinctrl_sgpsld_default: sgpsld_default { + function = "SGPSLD"; + groups = "SGPSLD"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; + + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; + + pinctrl_spics1_default: spics1_default { + function = "SPICS1"; + groups = "SPICS1"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_usb2h_default: usb2h_default { + function = "USB2H1"; + groups = "USB2H1"; + }; + + pinctrl_usb2d_default: usb2d_default { + function = "USB2D1"; + groups = "USB2D1"; + }; + + pinctrl_vgabios_rom_default: vgabios_rom_default { + function = "VGABIOS_ROM"; + groups = "VGABIOS_ROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi18_default: vpi18_default { + function = "VPI18"; + groups = "VPI18"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpi30_default: vpi30_default { + function = "VPI30"; + groups = "VPI30"; + }; + + pinctrl_vpo12_default: vpo12_default { + function = "VPO12"; + groups = "VPO12"; + }; + + pinctrl_vpo24_default: vpo24_default { + function = "VPO24"; + groups = "VPO24"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi new file mode 100644 index 000000000000..04f98d1dbb97 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -0,0 +1,1661 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fmc: spi@1e620000 { + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi1: spi@1e630000 { + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi2: spi@1e631000 { + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; + valid-sources = <0xffffffff>; + copro-sw-interrupts = <1>; + reg = <0x1e6c2000 0x80>; + }; + + mac0: ethernet@1e660000 { + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; + status = "disabled"; + }; + + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ah_default>; + status = "disabled"; + }; + + ehci1: usb@1e6a3000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a3000 0x100>; + interrupts = <13>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bh_default>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2500-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = <14>; + #ports = <2>; + clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; + status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an explicit pinmux + * override if you don't enable EHCI + */ + }; + + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2500-usb-vhub"; + reg = <0x1e6a0000 0x300>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + aspeed,vhub-downstream-ports = <5>; + aspeed,vhub-generic-endpoints = <15>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edac: memory-controller@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + status = "disabled"; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e6e2000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + reg = <0x18 0x4>; + interrupts = <21>; + interrupt-controller; + }; + + p2a: p2a-control@2c { + compatible = "aspeed,ast2500-p2a-ctrl"; + reg = <0x2c 0x4>; + status = "disabled"; + }; + + silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; + }; + + pinctrl: pinctrl@80 { + compatible = "aspeed,ast2500-pinctrl"; + reg = <0x80 0x18>, <0xa0 0x10>; + aspeed,external-nodes = <&gfx>, <&lhc>; + }; + }; + + rng: hwrng@1e6e2078 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2078 0x4>; + period = <1>; + quality = <100>; + }; + + hace: crypto@1e6e3000 { + compatible = "aspeed,ast2500-hace"; + reg = <0x1e6e3000 0x100>; + interrupts = <4>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + syscon = <&syscon>; + status = "disabled"; + interrupts = <0x19>; + }; + + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2500-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_XDMA>; + interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; + aspeed,pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + video: video@1e700000 { + compatible = "aspeed,ast2500-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <7>; + status = "disabled"; + }; + + sram: sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + sdmmc: sd-controller@1e740000 { + compatible = "aspeed,ast2500-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@100 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x100 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@200 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x200 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x200>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 232>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgpio: sgpio@1e780200 { + #gpio-cells = <2>; + compatible = "aspeed,ast2500-sgpio"; + gpio-controller; + interrupts = <40>; + reg = <0x1e780200 0x0100>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm_default>; + status = "disabled"; + }; + + rtc: rtc@1e781000 { + compatible = "aspeed,ast2500-rtc"; + reg = <0x1e781000 0x18>; + status = "disabled"; + }; + + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + interrupts = <16 17 18 35 36 37 38 39>; + clocks = <&syscon ASPEED_CLK_APB>; + clock-names = "PCLK"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + no-loopback-test; + status = "disabled"; + }; + + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + }; + + wdt2: watchdog@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + }; + + wdt3: watchdog@1e785040 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785040 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + status = "disabled"; + }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2500-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + clocks = <&syscon ASPEED_CLK_24M>; + resets = <&syscon ASPEED_RESET_PWM>; + status = "disabled"; + }; + + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; + no-loopback-test; + status = "disabled"; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + kcs4: kcs@114 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x80 0x10>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_snoop: lpc-snoop@90 { + compatible = "aspeed,ast2500-lpc-snoop"; + reg = <0x90 0x8>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + uart_routing: uart-routing@9c { + compatible = "aspeed,ast2500-uart-routing"; + reg = <0x9c 0x4>; + status = "disabled"; + }; + + lhc: lhc@a0 { + compatible = "aspeed,ast2500-lhc"; + reg = <0xa0 0x24 0xc8 0x8>; + }; + + + ibt: ibt@140 { + compatible = "aspeed,ast2500-ibt-bmc"; + reg = <0x140 0x18>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + }; + + peci0: peci-controller@1e78b000 { + compatible = "aspeed,ast2500-peci"; + reg = <0x1e78b000 0x60>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + cmd-timeout-ms = <1000>; + clock-frequency = <1000000>; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; + no-loopback-test; + status = "disabled"; + }; + + i2c: bus@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +}; + +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; + +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; + + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; + + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; + + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; + + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + }; + + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + }; + + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; + + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; + + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; + + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; + + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; + + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; + + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + }; + + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + }; + + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + }; + + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + }; + + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + }; + + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + }; + + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; + + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; + + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; + + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + }; + + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + }; + + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + }; + + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + }; + + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; + + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; + + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; + + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; + + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + }; + + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + }; + + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + }; + + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + }; + + pinctrl_sgpm_default: sgpm_default { + function = "SGPM"; + groups = "SGPM"; + }; + + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; + + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; + + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; + + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; + + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; + + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; + + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; + + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_usb2ah_default: usb2ah_default { + function = "USB2AH"; + groups = "USB2AH"; + }; + + pinctrl_usb2ad_default: usb2ad_default { + function = "USB2AD"; + groups = "USB2AD"; + }; + + pinctrl_usb11bhid_default: usb11bhid_default { + function = "USB11BHID"; + groups = "USB11BHID"; + }; + + pinctrl_usb2bh_default: usb2bh_default { + function = "USB2BH"; + groups = "USB2BH"; + }; + + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi new file mode 100644 index 000000000000..7cd4f075e325 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -0,0 +1,1184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. + +&pinctrl { + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; + + pinctrl_espialt_default: espialt_default { + function = "ESPIALT"; + groups = "ESPIALT"; + }; + + pinctrl_fsi1_default: fsi1_default { + function = "FSI1"; + groups = "FSI1"; + }; + + pinctrl_fsi2_default: fsi2_default { + function = "FSI2"; + groups = "FSI2"; + }; + + pinctrl_fwspiabr_default: fwspiabr_default { + function = "FWSPIABR"; + groups = "FWSPIABR"; + }; + + pinctrl_fwspid_default: fwspid_default { + function = "FWSPID"; + groups = "FWSPID"; + }; + + pinctrl_fwqspi_default: fwqspi_default { + function = "FWQSPI"; + groups = "FWQSPI"; + }; + + pinctrl_fwspiwp_default: fwspiwp_default { + function = "FWSPIWP"; + groups = "FWSPIWP"; + }; + + pinctrl_gpit0_default: gpit0_default { + function = "GPIT0"; + groups = "GPIT0"; + }; + + pinctrl_gpit1_default: gpit1_default { + function = "GPIT1"; + groups = "GPIT1"; + }; + + pinctrl_gpit2_default: gpit2_default { + function = "GPIT2"; + groups = "GPIT2"; + }; + + pinctrl_gpit3_default: gpit3_default { + function = "GPIT3"; + groups = "GPIT3"; + }; + + pinctrl_gpit4_default: gpit4_default { + function = "GPIT4"; + groups = "GPIT4"; + }; + + pinctrl_gpit5_default: gpit5_default { + function = "GPIT5"; + groups = "GPIT5"; + }; + + pinctrl_gpit6_default: gpit6_default { + function = "GPIT6"; + groups = "GPIT6"; + }; + + pinctrl_gpit7_default: gpit7_default { + function = "GPIT7"; + groups = "GPIT7"; + }; + + pinctrl_gpiu0_default: gpiu0_default { + function = "GPIU0"; + groups = "GPIU0"; + }; + + pinctrl_gpiu1_default: gpiu1_default { + function = "GPIU1"; + groups = "GPIU1"; + }; + + pinctrl_gpiu2_default: gpiu2_default { + function = "GPIU2"; + groups = "GPIU2"; + }; + + pinctrl_gpiu3_default: gpiu3_default { + function = "GPIU3"; + groups = "GPIU3"; + }; + + pinctrl_gpiu4_default: gpiu4_default { + function = "GPIU4"; + groups = "GPIU4"; + }; + + pinctrl_gpiu5_default: gpiu5_default { + function = "GPIU5"; + groups = "GPIU5"; + }; + + pinctrl_gpiu6_default: gpiu6_default { + function = "GPIU6"; + groups = "GPIU6"; + }; + + pinctrl_gpiu7_default: gpiu7_default { + function = "GPIU7"; + groups = "GPIU7"; + }; + + pinctrl_hvi3c3_default: hvi3c3_default { + function = "I3C3"; + groups = "HVI3C3"; + }; + + pinctrl_hvi3c4_default: hvi3c4_default { + function = "I3C4"; + groups = "HVI3C4"; + }; + + pinctrl_i2c1_default: i2c1_default { + function = "I2C1"; + groups = "I2C1"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c15_default: i2c15_default { + function = "I2C15"; + groups = "I2C15"; + }; + + pinctrl_i2c16_default: i2c16_default { + function = "I2C16"; + groups = "I2C16"; + }; + + pinctrl_i2c2_default: i2c2_default { + function = "I2C2"; + groups = "I2C2"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i3c3_default: i3c3_default { + function = "I3C3"; + groups = "I3C3"; + }; + + pinctrl_i3c4_default: i3c4_default { + function = "I3C4"; + groups = "I3C4"; + }; + + pinctrl_i3c5_default: i3c5_default { + function = "I3C5"; + groups = "I3C5"; + }; + + pinctrl_i3c6_default: i3c6_default { + function = "I3C6"; + groups = "I3C6"; + }; + + pinctrl_jtagm_default: jtagm_default { + function = "JTAGM"; + groups = "JTAGM"; + }; + + pinctrl_lhpd_default: lhpd_default { + function = "LHPD"; + groups = "LHPD"; + }; + + pinctrl_lhsirq_default: lhsirq_default { + function = "LHSIRQ"; + groups = "LHSIRQ"; + }; + + pinctrl_lpc_default: lpc_default { + function = "LPC"; + groups = "LPC"; + }; + + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; + + pinctrl_maclink1_default: maclink1_default { + function = "MACLINK1"; + groups = "MACLINK1"; + }; + + pinctrl_maclink2_default: maclink2_default { + function = "MACLINK2"; + groups = "MACLINK2"; + }; + + pinctrl_maclink3_default: maclink3_default { + function = "MACLINK3"; + groups = "MACLINK3"; + }; + + pinctrl_maclink4_default: maclink4_default { + function = "MACLINK4"; + groups = "MACLINK4"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_mdio3_default: mdio3_default { + function = "MDIO3"; + groups = "MDIO3"; + }; + + pinctrl_mdio4_default: mdio4_default { + function = "MDIO4"; + groups = "MDIO4"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm10g0_default: pwm10g0_default { + function = "PWM10"; + groups = "PWM10G0"; + }; + + pinctrl_pwm10g1_default: pwm10g1_default { + function = "PWM10"; + groups = "PWM10G1"; + }; + + pinctrl_pwm11g0_default: pwm11g0_default { + function = "PWM11"; + groups = "PWM11G0"; + }; + + pinctrl_pwm11g1_default: pwm11g1_default { + function = "PWM11"; + groups = "PWM11G1"; + }; + + pinctrl_pwm12g0_default: pwm12g0_default { + function = "PWM12"; + groups = "PWM12G0"; + }; + + pinctrl_pwm12g1_default: pwm12g1_default { + function = "PWM12"; + groups = "PWM12G1"; + }; + + pinctrl_pwm13g0_default: pwm13g0_default { + function = "PWM13"; + groups = "PWM13G0"; + }; + + pinctrl_pwm13g1_default: pwm13g1_default { + function = "PWM13"; + groups = "PWM13G1"; + }; + + pinctrl_pwm14g0_default: pwm14g0_default { + function = "PWM14"; + groups = "PWM14G0"; + }; + + pinctrl_pwm14g1_default: pwm14g1_default { + function = "PWM14"; + groups = "PWM14G1"; + }; + + pinctrl_pwm15g0_default: pwm15g0_default { + function = "PWM15"; + groups = "PWM15G0"; + }; + + pinctrl_pwm15g1_default: pwm15g1_default { + function = "PWM15"; + groups = "PWM15G1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_pwm8g0_default: pwm8g0_default { + function = "PWM8"; + groups = "PWM8G0"; + }; + + pinctrl_pwm8g1_default: pwm8g1_default { + function = "PWM8"; + groups = "PWM8G1"; + }; + + pinctrl_pwm9g0_default: pwm9g0_default { + function = "PWM9"; + groups = "PWM9G0"; + }; + + pinctrl_pwm9g1_default: pwm9g1_default { + function = "PWM9"; + groups = "PWM9G1"; + }; + + pinctrl_qspi1_default: qspi1_default { + function = "SPI1"; + groups = "QSPI1"; + }; + + pinctrl_qspi2_default: qspi2_default { + function = "SPI2"; + groups = "QSPI2"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rgmii3_default: rgmii3_default { + function = "RGMII3"; + groups = "RGMII3"; + }; + + pinctrl_rgmii4_default: rgmii4_default { + function = "RGMII4"; + groups = "RGMII4"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rmii3_default: rmii3_default { + function = "RMII3"; + groups = "RMII3"; + }; + + pinctrl_rmii4_default: rmii4_default { + function = "RMII4"; + groups = "RMII4"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt10g0_default: salt10g0_default { + function = "SALT10"; + groups = "SALT10G0"; + }; + + pinctrl_salt10g1_default: salt10g1_default { + function = "SALT10"; + groups = "SALT10G1"; + }; + + pinctrl_salt11g0_default: salt11g0_default { + function = "SALT11"; + groups = "SALT11G0"; + }; + + pinctrl_salt11g1_default: salt11g1_default { + function = "SALT11"; + groups = "SALT11G1"; + }; + + pinctrl_salt12g0_default: salt12g0_default { + function = "SALT12"; + groups = "SALT12G0"; + }; + + pinctrl_salt12g1_default: salt12g1_default { + function = "SALT12"; + groups = "SALT12G1"; + }; + + pinctrl_salt13g0_default: salt13g0_default { + function = "SALT13"; + groups = "SALT13G0"; + }; + + pinctrl_salt13g1_default: salt13g1_default { + function = "SALT13"; + groups = "SALT13G1"; + }; + + pinctrl_salt14g0_default: salt14g0_default { + function = "SALT14"; + groups = "SALT14G0"; + }; + + pinctrl_salt14g1_default: salt14g1_default { + function = "SALT14"; + groups = "SALT14G1"; + }; + + pinctrl_salt15g0_default: salt15g0_default { + function = "SALT15"; + groups = "SALT15G0"; + }; + + pinctrl_salt15g1_default: salt15g1_default { + function = "SALT15"; + groups = "SALT15G1"; + }; + + pinctrl_salt16g0_default: salt16g0_default { + function = "SALT16"; + groups = "SALT16G0"; + }; + + pinctrl_salt16g1_default: salt16g1_default { + function = "SALT16"; + groups = "SALT16G1"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; + + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; + + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; + + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; + + pinctrl_salt9g0_default: salt9g0_default { + function = "SALT9"; + groups = "SALT9G0"; + }; + + pinctrl_salt9g1_default: salt9g1_default { + function = "SALT9"; + groups = "SALT9G1"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_emmc_default: emmc_default { + function = "EMMC"; + groups = "EMMCG4"; + }; + + pinctrl_sgpm1_default: sgpm1_default { + function = "SGPM1"; + groups = "SGPM1"; + }; + + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; + + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; + + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1abr_default: spi1abr_default { + function = "SPI1ABR"; + groups = "SPI1ABR"; + }; + + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; + + pinctrl_spi1wp_default: spi1wp_default { + function = "SPI1WP"; + groups = "SPI1WP"; + }; + + pinctrl_spi2_default: spi2_default { + function = "SPI2"; + groups = "SPI2"; + }; + + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_spi2cs2_default: spi2cs2_default { + function = "SPI2CS2"; + groups = "SPI2CS2"; + }; + + pinctrl_tach0_default: tach0_default { + function = "TACH0"; + groups = "TACH0"; + }; + + pinctrl_tach1_default: tach1_default { + function = "TACH1"; + groups = "TACH1"; + }; + + pinctrl_tach10_default: tach10_default { + function = "TACH10"; + groups = "TACH10"; + }; + + pinctrl_tach11_default: tach11_default { + function = "TACH11"; + groups = "TACH11"; + }; + + pinctrl_tach12_default: tach12_default { + function = "TACH12"; + groups = "TACH12"; + }; + + pinctrl_tach13_default: tach13_default { + function = "TACH13"; + groups = "TACH13"; + }; + + pinctrl_tach14_default: tach14_default { + function = "TACH14"; + groups = "TACH14"; + }; + + pinctrl_tach15_default: tach15_default { + function = "TACH15"; + groups = "TACH15"; + }; + + pinctrl_tach2_default: tach2_default { + function = "TACH2"; + groups = "TACH2"; + }; + + pinctrl_tach3_default: tach3_default { + function = "TACH3"; + groups = "TACH3"; + }; + + pinctrl_tach4_default: tach4_default { + function = "TACH4"; + groups = "TACH4"; + }; + + pinctrl_tach5_default: tach5_default { + function = "TACH5"; + groups = "TACH5"; + }; + + pinctrl_tach6_default: tach6_default { + function = "TACH6"; + groups = "TACH6"; + }; + + pinctrl_tach7_default: tach7_default { + function = "TACH7"; + groups = "TACH7"; + }; + + pinctrl_tach8_default: tach8_default { + function = "TACH8"; + groups = "TACH8"; + }; + + pinctrl_tach9_default: tach9_default { + function = "TACH9"; + groups = "TACH9"; + }; + + pinctrl_thru0_default: thru0_default { + function = "THRU0"; + groups = "THRU0"; + }; + + pinctrl_thru1_default: thru1_default { + function = "THRU1"; + groups = "THRU1"; + }; + + pinctrl_thru2_default: thru2_default { + function = "THRU2"; + groups = "THRU2"; + }; + + pinctrl_thru3_default: thru3_default { + function = "THRU3"; + groups = "THRU3"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart10_default: uart10_default { + function = "UART10"; + groups = "UART10"; + }; + + pinctrl_uart11_default: uart11_default { + function = "UART11"; + groups = "UART11"; + }; + + pinctrl_uart12g0_default: uart12g0_default { + function = "UART12"; + groups = "UART12G0"; + }; + + pinctrl_uart12g1_default: uart12g1_default { + function = "UART12"; + groups = "UART12G1"; + }; + + pinctrl_uart13g0_default: uart13g0_default { + function = "UART13"; + groups = "UART13G0"; + }; + + pinctrl_uart13g1_default: uart13g1_default { + function = "UART13"; + groups = "UART13G1"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_uart7_default: uart7_default { + function = "UART7"; + groups = "UART7"; + }; + + pinctrl_uart8_default: uart8_default { + function = "UART8"; + groups = "UART8"; + }; + + pinctrl_uart9_default: uart9_default { + function = "UART9"; + groups = "UART9"; + }; + + pinctrl_usb2ah_default: usb2ah_default { + function = "USB2AH"; + groups = "USBA"; + }; + + pinctrl_usb2ad_default: usb2ad_default { + function = "USB2AD"; + groups = "USBA"; + }; + + pinctrl_usb2bh_default: usb2bh_default { + function = "USB2BH"; + groups = "USBB"; + }; + + pinctrl_usb2bd_default: usb2bd_default { + function = "USB2BD"; + groups = "USBB"; + }; + + pinctrl_usb11bhid_default: usb11bhid_default { + function = "USB11BHID"; + groups = "USBB"; + }; + + pinctrl_vb_default: vb_default { + function = "VB"; + groups = "VB"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; + + pinctrl_wdtrst3_default: wdtrst3_default { + function = "WDTRST3"; + groups = "WDTRST3"; + }; + + pinctrl_wdtrst4_default: wdtrst4_default { + function = "WDTRST4"; + groups = "WDTRST4"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi new file mode 100644 index 000000000000..172dd748d807 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -0,0 +1,1121 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. + +#include +#include +#include + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2600"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart1; + serial6 = &vuart2; + mdio0 = &mdio0; + mdio1 = &mdio1; + mdio2 = &mdio2; + mdio3 = &mdio3; + }; + + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "aspeed,ast2600-smp"; + + cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + }; + + cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clocks = <&syscon ASPEED_CLK_HPLL>; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2600-sdram-edac", "syscon"; + reg = <0x1e6e0000 0x174>; + interrupts = ; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges; + + gic: interrupt-controller@40461000 { + compatible = "arm,cortex-a7-gic"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + reg = <0x40461000 0x1000>, + <0x40462000 0x1000>, + <0x40464000 0x2000>, + <0x40466000 0x2000>; + }; + + ahbc: bus@1e600000 { + compatible = "aspeed,ast2600-ahbc", "syscon"; + reg = <0x1e600000 0x100>; + }; + + fmc: spi@1e620000 { + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + interrupts = ; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi1: spi@1e630000 { + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + spi2: spi@1e631000 { + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + status = "disabled"; + }; + }; + + mdio0: mdio@1e650000 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650000 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1_default>; + resets = <&syscon ASPEED_RESET_MII>; + }; + + mdio1: mdio@1e650008 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650008 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio2_default>; + resets = <&syscon ASPEED_RESET_MII>; + }; + + mdio2: mdio@1e650010 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650010 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio3_default>; + resets = <&syscon ASPEED_RESET_MII>; + }; + + mdio3: mdio@1e650018 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650018 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + resets = <&syscon ASPEED_RESET_MII>; + }; + + mac0: ftgmac@1e660000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; + status = "disabled"; + }; + + mac1: ftgmac@1e680000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; + status = "disabled"; + }; + + mac2: ftgmac@1e670000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e670000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; + status = "disabled"; + }; + + mac3: ftgmac@1e690000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e690000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; + status = "disabled"; + }; + + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2600-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ah_default>; + status = "disabled"; + }; + + ehci1: usb@1e6a3000 { + compatible = "aspeed,ast2600-ehci", "generic-ehci"; + reg = <0x1e6a3000 0x100>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bh_default>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2600-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = ; + #ports = <2>; + clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; + status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an + * explicit pinmux override if EHCI is not enabled. + */ + }; + + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2600-usb-vhub"; + reg = <0x1e6a0000 0x350>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; + status = "disabled"; + }; + + udc: usb@1e6a2000 { + compatible = "aspeed,ast2600-udc"; + reg = <0x1e6a2000 0x300>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bd_default>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hace: crypto@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1000>; + ranges = <0 0x1e6e2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl: pinctrl { + compatible = "aspeed,ast2600-pinctrl"; + }; + + silicon-id@14 { + compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; + reg = <0x14 0x4 0x5b0 0x8>; + }; + + smp-memram@180 { + compatible = "aspeed,ast2600-smpmem"; + reg = <0x180 0x40>; + }; + + scu_ic0: interrupt-controller@560 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic0"; + reg = <0x560 0x4>; + interrupts = ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@570 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic1"; + reg = <0x570 0x4>; + interrupts = ; + interrupt-controller; + }; + }; + + rng: hwrng@1e6e2524 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2524 0x4>; + period = <1>; + quality = <100>; + }; + + gfx: display@1e6e6000 { + compatible = "aspeed,ast2600-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_GRAPHICS>; + syscon = <&syscon>; + status = "disabled"; + interrupts = ; + }; + + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2600-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; + reset-names = "device", "root-complex"; + interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; + aspeed,pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + + adc0: adc@1e6e9000 { + compatible = "aspeed,ast2600-adc0"; + reg = <0x1e6e9000 0x100>; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_ADC>; + interrupts = ; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc1: adc@1e6e9100 { + compatible = "aspeed,ast2600-adc1"; + reg = <0x1e6e9100 0x100>; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_ADC>; + interrupts = ; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; + + acry: crypto@1e6fa000 { + compatible = "aspeed,ast2600-acry"; + reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_RSACLK>; + aspeed,ahbc = <&ahbc>; + }; + + video: video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = ; + status = "disabled"; + }; + + gpio0: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780000 0x400>; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 208>; + ngpios = <208>; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgpiom0: sgpiom@1e780500 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780500 0x100>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupt-controller; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm1_default>; + status = "disabled"; + }; + + sgpiom1: sgpiom@1e780600 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780600 0x100>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupt-controller; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm2_default>; + status = "disabled"; + }; + + gpio1: gpio@1e780800 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780800 0x800>; + interrupts = ; + gpio-ranges = <&pinctrl 0 208 36>; + ngpios = <36>; + clocks = <&syscon ASPEED_CLK_APB1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rtc: rtc@1e781000 { + compatible = "aspeed,ast2600-rtc"; + reg = <0x1e781000 0x18>; + interrupts = ; + status = "disabled"; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2600-timer"; + reg = <0x1e782000 0x90>; + interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB1>; + clock-names = "PCLK"; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + no-loopback-test; + }; + + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785000 0x40>; + }; + + wdt2: watchdog@1e785040 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785040 0x40>; + status = "disabled"; + }; + + wdt3: watchdog@1e785080 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785080 0x40>; + status = "disabled"; + }; + + wdt4: watchdog@1e7850c0 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e7850C0 0x40>; + status = "disabled"; + }; + + peci0: peci-controller@1e78b000 { + compatible = "aspeed,ast2600-peci"; + reg = <0x1e78b000 0x100>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + cmd-timeout-ms = <1000>; + clock-frequency = <1000000>; + status = "disabled"; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + kcs_chan = <1>; + status = "disabled"; + }; + + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + kcs4: kcs@114 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_snoop: lpc-snoop@80 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x80 0x80>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lhc: lhc@a0 { + compatible = "aspeed,ast2600-lhc"; + reg = <0xa0 0x24 0xc8 0x8>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + status = "disabled"; + }; + + ibt: ibt@140 { + compatible = "aspeed,ast2600-ibt-bmc"; + reg = <0x140 0x18>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + }; + + sdc: sdc@1e740000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@1e740100 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; + reg = <0x100 0x100>; + interrupts = ; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@1e740200 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; + reg = <0x200 0x100>; + interrupts = ; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + + emmc_controller: sdc@1e750000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e750000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e750000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; + status = "disabled"; + + emmc: sdhci@1e750100 { + compatible = "aspeed,ast2600-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + interrupts = ; + clocks = <&syscon ASPEED_CLK_EMMC>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_default>; + }; + }; + + vuart1: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_APB1>; + no-loopback-test; + status = "disabled"; + }; + + vuart2: serial@1e788000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e788000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_APB1>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; + status = "disabled"; + }; + + uart6: serial@1e790000 { + compatible = "ns16550a"; + reg = <0x1e790000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6_default>; + + status = "disabled"; + }; + + uart7: serial@1e790100 { + compatible = "ns16550a"; + reg = <0x1e790100 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7_default>; + + status = "disabled"; + }; + + uart8: serial@1e790200 { + compatible = "ns16550a"; + reg = <0x1e790200 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8_default>; + + status = "disabled"; + }; + + uart9: serial@1e790300 { + compatible = "ns16550a"; + reg = <0x1e790300 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart9_default>; + + status = "disabled"; + }; + + i2c: bus@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + + fsim0: fsi@1e79b000 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b000 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + + fsim1: fsi@1e79b100 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b100 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi2_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + + udma: dma-controller@1e79e000 { + compatible = "aspeed,ast2600-udma"; + reg = <0x1e79e000 0x1000>; + interrupts = ; + dma-channels = <28>; + #dma-cells = <1>; + status = "disabled"; + }; + }; + }; +}; + +#include "aspeed-g6-pinctrl.dtsi" + +&i2c { + i2c0: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "disabled"; + }; + + i2c1: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x100 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + status = "disabled"; + }; + + i2c2: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x180 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@200 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x200 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@280 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x280 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x300 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x380 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x400 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x480 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@500 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x500 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@580 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x580 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@600 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x600 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@680 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x680 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@700 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x700 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; + + i2c14: i2c-bus@780 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x780 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; + status = "disabled"; + }; + + i2c15: i2c-bus@800 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x800 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = ; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi new file mode 100644 index 000000000000..4e5e786e18b7 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; +}; + +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi0.0"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default + &pinctrl_ndts4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi new file mode 100644 index 000000000000..c0c43b8644ee --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2019 Facebook Inc. + +#include "aspeed-g5.dtsi" + +/ { + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; +}; + +/* + * Update reset type to "system" (full chip) to fix warm reboot hang issue + * when reset type is set to default ("soc", gated by reset mask registers). + */ +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&wdt2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + fmc_flash0: flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi0.0"; + }; + + fmc_flash1: flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + }; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&rtc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; +}; diff --git a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi new file mode 100644 index 000000000000..31590d3186a2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +#include "aspeed-g6.dtsi" +#include + +/ { + aliases { + mmc0 = &emmc; + spi1 = &spi1; + spi2 = &spi_gpio; + }; + + chosen { + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw vmalloc=640M"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + /* + * GPIO-based SPI Master is required to access SPI TPM, because + * full-duplex SPI transactions are not supported by ASPEED SPI + * Controllers. + */ + spi_gpio: spi { + status = "okay"; + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi0.0"; + +#include "facebook-bmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x8000000>; + label = "flash1"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + + non-removable; + max-frequency = <25000000>; + bus-width = <4>; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi new file mode 100644 index 000000000000..7f3652dea550 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 896KB. + */ + u-boot@0 { + reg = <0x0 0xe0000>; + label = "u-boot"; + }; + + /* + * u-boot environment variables: 64KB. + */ + u-boot-env@e0000 { + reg = <0xe0000 0x10000>; + label = "env"; + }; + + /* + * image metadata partition (64KB), used by Facebook internal + * tools. + */ + image-meta@f0000 { + reg = <0xf0000 0x10000>; + label = "meta"; + }; + + /* + * FIT image: 119 MB. + */ + fit@100000 { + reg = <0x100000 0x7700000>; + label = "fit"; + }; + + /* + * "data0" partition (8MB) is used by Facebook BMC platforms as + * persistent data store. + */ + data0@7800000 { + reg = <0x7800000 0x800000>; + label = "data0"; + }; + + /* + * Although the master partition can be created by enabling + * MTD_PARTITIONED_MASTER option, below "flash0" partition is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x8000000>; + label = "flash0"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi new file mode 100644 index 000000000000..87bb8b576250 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + fit@80000 { + reg = <0x80000 0x1b80000>; + label = "fit"; + }; + + /* + * "data0" partition is used by several Facebook BMC platforms + * as persistent data store. + */ + data0@1c00000 { + reg = <0x1c00000 0x400000>; + label = "data0"; + }; + + /* + * Although the master partition can be created by enabling + * MTD_PARTITIONED_MASTER option, below "flash0" partition is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x2000000>; + label = "flash0"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi new file mode 100644 index 000000000000..a0fa65b44b0f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2018 IBM Corp + +&fsi { + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam0_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam0_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam0_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam0_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam0_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam0_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam0_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam0_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ@1 { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam1_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam1_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam1_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam1_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam1_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam1_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam1_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam1_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam1_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ@2 { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c102 = &cfam0_i2c2; + i2c103 = &cfam0_i2c3; + i2c104 = &cfam0_i2c4; + i2c105 = &cfam0_i2c5; + i2c106 = &cfam0_i2c6; + i2c107 = &cfam0_i2c7; + i2c108 = &cfam0_i2c8; + i2c109 = &cfam0_i2c9; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c200 = &cfam1_i2c0; + i2c201 = &cfam1_i2c1; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c204 = &cfam1_i2c4; + i2c205 = &cfam1_i2c5; + i2c206 = &cfam1_i2c6; + i2c207 = &cfam1_i2c7; + i2c208 = &cfam1_i2c8; + i2c209 = &cfam1_i2c9; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c212 = &cfam1_i2c12; + i2c213 = &cfam1_i2c13; + i2c214 = &cfam1_i2c14; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi new file mode 100644 index 000000000000..05101a38c5bd --- /dev/null +++ b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x5600000>; // 86MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x6000000 0x2000000>; // 32MB + label = "rwfs"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi new file mode 100644 index 000000000000..650525867561 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "alt-u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "alt-u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "alt-kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "alt-rofs"; + }; + + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "alt-rwfs"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi new file mode 100644 index 000000000000..7af41361c480 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "rofs"; + }; + + rwfs@2a00000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "rwfs"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi new file mode 100644 index 000000000000..b47e14063c38 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "u-boot-env"; + }; + + kernel@80000 { + reg = <0x80000 0x440000>; + label = "kernel"; + }; + + rofs@4c0000 { + reg = <0x4c0000 0x1740000>; + label = "rofs"; + }; + + rwfs@1c00000 { + reg = <0x1c00000 0x400000>; + label = "rwfs"; + }; +}; diff --git a/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi deleted file mode 100644 index 4e5e786e18b7..000000000000 --- a/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. -/dts-v1/; - -#include "aspeed-g4.dtsi" - -/ { - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; -}; - -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi0.0"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default - &pinctrl_ndts4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&adc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi deleted file mode 100644 index c0c43b8644ee..000000000000 --- a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2019 Facebook Inc. - -#include "aspeed-g5.dtsi" - -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; -}; - -/* - * Update reset type to "system" (full chip) to fix warm reboot hang issue - * when reset type is set to default ("soc", gated by reset mask registers). - */ -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&wdt2 { - status = "disabled"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - -&fmc { - status = "okay"; - - fmc_flash0: flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi0.0"; - }; - - fmc_flash1: flash@1 { - status = "okay"; - m25p,fast-read; - label = "spi0.1"; - }; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&rtc { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; -}; diff --git a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi deleted file mode 100644 index 31590d3186a2..000000000000 --- a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. - -#include "aspeed-g6.dtsi" -#include - -/ { - aliases { - mmc0 = &emmc; - spi1 = &spi1; - spi2 = &spi_gpio; - }; - - chosen { - bootargs = "console=ttyS0,9600n8 root=/dev/ram rw vmalloc=640M"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - /* - * GPIO-based SPI Master is required to access SPI TPM, because - * full-duplex SPI transactions are not supported by ASPEED SPI - * Controllers. - */ - spi_gpio: spi { - status = "okay"; - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; - - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; - spi-max-frequency = <33000000>; - reg = <0>; - }; - }; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi0.0"; - -#include "facebook-bmc-flash-layout-128.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "spi0.1"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x8000000>; - label = "flash1"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&wdt1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; - - non-removable; - max-frequency = <25000000>; - bus-width = <4>; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts deleted file mode 100644 index 713d18f80356..000000000000 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based) - * - * Copyright (C) 2013 Douglas Gilbert , - * Robert Nelson - */ -/dts-v1/; -#include "at91sam9g25.dtsi" - -/ { - model = "Acme Systems Aria G25"; - compatible = "acme,ariag25", "atmel,at91sam9x5ek", - "atmel,at91sam9x5", "atmel,at91sam9"; - - aliases { - serial5 = &uart0; - serial6 = &uart1; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory@20000000 { - /* 128 MB, change this for 256 MB revision */ - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* little green LED in middle of Aria G25 module */ - aria_led { - label = "aria_led"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ - linux,default-trigger = "heartbeat"; - }; - - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&pioA 21 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_w1_0>; - }; -}; - -&adc0 { - status = "okay"; - atmel,adc-channels-used = <0xf>; -}; - -&dbgu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */ - -&macb0 { - phy-mode = "rmii"; - /* - * following can be overwritten by bootloader: - * for example u-boot 'ftd set' command - */ - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; -}; - - -&mmc0 { - /* N.B. Aria has no SD card detect (CD), assumed present */ - - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&pinctrl { - w1_0 { - pinctrl_w1_0: w1_0-0 { - atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -/* - * UART0/1 pins are marked as GPIO on - * Aria documentation. - * Change to "okay" if you need additional serial ports - */ -&uart0 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&usart0 { - pinctrl-0 = <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; -}; - -&usart1 { - pinctrl-0 = <&pinctrl_usart1 - /* &pinctrl_usart1_rts */ - /* &pinctrl_usart1_cts */ - >; - status = "okay"; -}; - -&usart2 { - /* cannot activate RTS2+CTS2, clash with - * ethernet on PB0 and PB1 */ - pinctrl-0 = <&pinctrl_usart2>; - status = "okay"; -}; - -&usart3 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <8 4 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3 - /* &pinctrl_usart3_rts */ - /* &pinctrl_usart3_cts */ - >; - status = "okay"; -}; - -&usb0 { - status = "okay"; - num-ports = <3>; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts deleted file mode 100644 index 2c52a71752c2..000000000000 --- a/arch/arm/boot/dts/at91-ariettag25.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Arietta G25 - * This device tree is minimal, to activate more peripherals, see: - * http://dts.acmesystems.it/arietta/ - */ -/dts-v1/; -#include "at91sam9g25.dtsi" - -/ { - model = "Acme Systems Arietta G25"; - compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - arietta_led { - label = "arietta_led"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&dbgu { - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&rtc { - status = "okay"; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usb0 { - num-ports = <3>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi deleted file mode 100644 index ee0f5da6d819..000000000000 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-cosino.dtsi - Device Tree file for Cosino core module - * - * Copyright (C) 2013 - Rodolfo Giometti - * HCE Engineering - * - * Derived from at91sam9x5ek.dtsi by: - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -#include "at91sam9g35.dtsi" - -/ { - model = "HCE Cosino core module"; - compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; - }; - - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_addr_nand - &pinctrl_ebi_data_0_7>; - pinctrl-names = "default"; - status = "okay"; - - nand-controller { - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "U-Boot Env"; - reg = <0xc0000 0x140000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD15 gpio CD pin pull up and deglitch */ - }; - }; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts deleted file mode 100644 index 04cb7bee937d..000000000000 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-cosino_mega2560.dts - Device Tree file for Cosino board with - * Mega 2560 extension - * - * Copyright (C) 2013 - Rodolfo Giometti - * HCE Engineering - * - * Derived from at91sam9g35ek.dts by: - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -/dts-v1/; -#include "at91-cosino.dtsi" - -/ { - model = "HCE Cosino Mega 2560"; - compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&mmc1 { - pinctrl-0 = < - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - non-removable; - }; -}; - -&rtc { - status = "okay"; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usb0 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ - &pioD 19 GPIO_ACTIVE_LOW - &pioD 20 GPIO_ACTIVE_LOW - >; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-dvk_som60.dts b/arch/arm/boot/dts/at91-dvk_som60.dts deleted file mode 100644 index ededd5b0d27b..000000000000 --- a/arch/arm/boot/dts/at91-dvk_som60.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ -/dts-v1/; -#include "at91-som60.dtsi" -#include "at91-dvk_su60_somc.dtsi" -#include "at91-dvk_su60_somc_lcm.dtsi" - -/ { - model = "Laird DVK SOM60"; - compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = &dbgu; - tick-timer = &pit; - }; -}; - -&mmc0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&ssc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&pit { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&macb0 { - status = "okay"; -}; - -&macb1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi deleted file mode 100644 index 3542ad8a243e..000000000000 --- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ - -/ { - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; - - atmel,model = "wm8904 @ DVK-SOM60"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "okay"; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - slot@0 { - bus-width = <4>; - cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; - cd-inverted; - }; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ - flash@0 { - compatible = "mxicy,mx25u4035", "jedec,spi-nor"; - spi-max-frequency = <33000000>; - reg = <0>; - }; -}; - -&ssc0 { - atmel,clk-from-rk-pin; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pmc PMC_TYPE_SYSTEM 10>; - clock-names = "mclk"; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom@57 { - compatible = "giantec,gt24c32a", "atmel,24c32"; - reg = <0x57>; - pagesize = <32>; - }; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&pit { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&macb0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@7 { - reg = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_geth_int>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; -}; - -&macb1 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_int>; - interrupt-parent = <&pioC>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi deleted file mode 100644 index bea920b192b6..000000000000 --- a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel: panel { - compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92"; - backlight = <&backlight>; - power-supply = <&vcc_lcd_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_lcd_reg: fixedregulator_lcd { - compatible = "regulator-fixed"; - regulator-name = "VCC LCM"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - status = "okay"; - }; -}; - -&pinctrl { - board { - pinctrl_lcd_ctp_int: lcd_ctp_int { - atmel,pins = - ; - }; - }; -}; - -&i2c1 { - status = "okay"; - - ft5426@38 { - compatible = "focaltech,ft5426", "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_ctp_int>; - - interrupt-parent = <&pioC>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&hlcdc { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts deleted file mode 100644 index 9dfd5de808d1..000000000000 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board - * - * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) - * - * Copyright (C) 2013 Douglas Gilbert - */ -/dts-v1/; -#include "at91sam9g20.dtsi" - -/ { - model = "Acme Systems FoxG20"; - compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - >; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart2: serial@fffb8000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - - uart0: serial@fffd4000 { - status = "okay"; - }; - - uart1: serial@fffd8000 { - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - ; - }; - }; - - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; /* CD pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* TWCK (SCL), open drain */ - }; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - i2c-gpio,delay-us = <5>; /* ~85 kHz */ - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - /* red LED marked "PC7" near mini USB (device) receptacle */ - user_led { - label = "user_led"; - gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button { - label = "Button"; - gpios = <&pioC 4 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts deleted file mode 100644 index 551300fd7746..000000000000 --- a/arch/arm/boot/dts/at91-gatwick.dts +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-gatwick.dts - Device Tree file for the Gatwick board - * - * Copyright (C) 2018 Laird - * - */ -/dts-v1/; -#include "at91-wb50n.dtsi" -#include - -/ { - model = "Laird Workgroup Bridge 50N - Project Gatwick"; - compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&pioE 31 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-ethernet { - label = "gatwick:yellow:ethernet"; - gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-wifi { - label = "gatwick:green:wifi"; - gpios = <&pioA 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-ble { - label = "gatwick:blue:ble"; - gpios = <&pioA 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-lora { - label = "gatwick:orange:lora"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-blank { - label = "gatwick:green:blank"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-user { - label = "gatwick:yellow:user"; - gpios = <&pioA 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&pinctrl { - board { - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; /* PE31 GPIO with pullup deglitch */ - }; - }; -}; - -&mmc0 { - status = "okay"; -}; - -&macb1 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -/* FTDI USART */ -&usart0 { - status = "okay"; -}; - -/* GPS USART */ -&usart1 { - pinctrl-0 = <&pinctrl_usart1>; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - spidev@0 { - compatible = "semtech,sx1301"; - reg = <0>; - spi-max-frequency = <8000000>; - }; -}; - -&usb1 { - status = "okay"; - /delete-property/atmel,oc-gpio; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts deleted file mode 100644 index 307663b4eec2..000000000000 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board - * - * Copyright (C) 2012-2014 Boris BREZILLON - * 2014-2015 Gaël PORTAY - */ -/dts-v1/; -#include "at91sam9g20.dtsi" -#include - -/ { - model = "Overkiz Kizbox"; - compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory@20000000 { - reg = <0x20000000 0x2000000>; - }; - - clocks { - main_xtal { - clock-frequency = <18432000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-reset { - label = "PB_RST"; - gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - - button-user { - label = "PB_USER"; - gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "pwm:green:network"; - pwms = <&tcb1_pwm1 0 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led-2 { - label = "pwm:red:network"; - pwms = <&tcb1_pwm2 0 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led-3 { - label = "pwm:green:user"; - pwms = <&tcb1_pwm0 0 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led-4 { - label = "pwm:red:user"; - pwms = <&tcb1_pwm0 1 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; -}; - -&tcb1 { - tcb1_pwm0: pwm@0 { - compatible = "atmel,tcb-pwm"; - reg = <0>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa0 &pinctrl_tcb1_tiob0>; - }; - - tcb1_pwm1: pwm@1 { - compatible = "atmel,tcb-pwm"; - reg = <1>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa1>; - }; - - tcb1_pwm2: pwm@2 { - compatible = "atmel,tcb-pwm"; - reg = <2>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa2>; - }; -}; - -&ebi { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; -}; - -&macb0 { - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_macb_rmii - &pinctrl_macb_rmii_mii_alt>; - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&watchdog { - timeout-sec = <15>; - atmel,max-heartbeat-sec = <16>; - atmel,min-heartbeat-sec = <0>; - status = "okay"; -}; - -&usb0 { - num-ports = <1>; - status = "okay"; -}; - -&i2c_gpio0 { - status = "okay"; - - rtc: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; diff --git a/arch/arm/boot/dts/at91-kizbox2-2.dts b/arch/arm/boot/dts/at91-kizbox2-2.dts deleted file mode 100644 index cab8b3579efa..000000000000 --- a/arch/arm/boot/dts/at91-kizbox2-2.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox2-2.dts - Device Tree file for the Kizbox2 with - * two head board - * - * Copyright (C) 2015 Overkiz SAS - * - * Authors: Antoine Aubert - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizbox2-common.dtsi" - -/ { - model = "Overkiz Kizbox 2 with two heads"; - compatible = "overkiz,kizbox2-2", "atmel,sama5d31", - "atmel,sama5d3", "atmel,sama5"; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi deleted file mode 100644 index e5e21dff882f..000000000000 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox2_common.dtsi - Device Tree Include file for - * Overkiz Kizbox 2 family SoC - * - * Copyright (C) 2014-2018 Overkiz SAS - * - * Authors: Antoine Aubert - * Gaël Portay - * Kévin Raymond - */ -#include "sama5d31.dtsi" - -/ { - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory@20000000 { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-prog { - label = "PB_PROG"; - gpios = <&pioE 27 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - button-reset { - label = "PB_RST"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - - button-user { - label = "PB_USER"; - gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "none"; - }; - - led-2 { - label = "pwm:green:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led-3 { - label = "pwm:red:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; - -&i2c1 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "okay"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vled_reg: LDO_REG3 { - regulator-name = "VLED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v3v8_rf_reg: LDO_REG4 { - regulator-name = "V3V8_RF"; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-always-on; - }; - }; - }; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&usart1 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&usart2 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 - &pinctrl_pwm0_pwmh1_1 - &pinctrl_pwm0_pwmh2_0>; - status = "okay"; -}; - -&adc0 { - atmel,adc-vref = <3333>; - status = "okay"; -}; - -&macb1 { - phy-mode = "rmii"; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -/* WMBUS (inverted with IO in the latest schematic) */ -&pinctrl_usart0 { - atmel,pins = - ; -}; - -/* RTS */ -&pinctrl_usart1 { - atmel,pins = - ; -}; - -/* IO (inverted with WMBUS in the latest schematic) */ -&pinctrl_usart2 { - atmel,pins = - ; -}; diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts deleted file mode 100644 index fec7269088d1..000000000000 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board - * - * Copyright (C) 2018 Overkiz SAS - * - * Authors: Dorian Rocipon - * Kevin Carli - * Mickael Gardet - */ -/dts-v1/; -#include "at91-kizbox3_common.dtsi" - -/ { - model = "Overkiz KIZBOX3-HS"; - compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5"; - - led-controller-1 { - status = "okay"; - - led-1 { - status = "okay"; - }; - - led-2 { - status = "okay"; - }; - - led-3 { - status = "okay"; - }; - - led-4 { - status = "okay"; - }; - }; - - led-controller-2 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_red - &pinctrl_led_white>; - status = "okay"; - - led-5 { - label = "pio:red:user"; - gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-6 { - label = "pio:white:user"; - gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default" , "default", "default", - "default", "default" ; - pinctrl-0 = <&pinctrl_key_gpio_default>; - pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>; - pinctrl-2 = <&pinctrl_pio_io_boot - &pinctrl_pio_io_reset - &pinctrl_pio_io_test_radio>; - pinctrl-3 = <&pinctrl_pio_zbe_test_radio - &pinctrl_pio_zbe_rst>; - pinctrl-4 = <&pinctrl_pio_input>; - - switch-1 { - label = "SW1"; - gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - wakeup-source; - }; - - switch-2 { - label = "SW2"; - gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - switch-3 { - label = "SW3"; - gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - switch-7 { - label = "SW7"; - gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>; - linux,code = <0x107>; - wakeup-source; - }; - - switch-8 { - label = "SW8"; - gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>; - linux,code = <0x108>; - wakeup-source; - }; - }; - - gpios { - compatible = "gpio"; - status = "okay"; - - rf_on { - label = "rf on"; - gpio = <&pioA PIN_PC19 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - wifi_on { - label = "wifi on"; - gpio = <&pioA PIN_PC20 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - zbe_test_radio { - label = "zbe test radio"; - gpio = <&pioA PIN_PB21 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - zbe_rst { - label = "zbe rst"; - gpio = <&pioA PIN_PB25 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_reset { - label = "io reset"; - gpio = <&pioA PIN_PB30 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_test_radio { - label = "io test radio"; - gpio = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_boot_0 { - label = "io boot 0"; - gpio = <&pioA PIN_PC11 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_boot_1 { - label = "io boot 1"; - gpio = <&pioA PIN_PC17 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - verbose_bootloader { - label = "verbose bootloader"; - gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; - input; - }; - - nail_bed_detection { - label = "nail bed detection"; - gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>; - input; - }; - - id_usba { - label = "id usba"; - gpio = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; - input; - }; - }; -}; - -&pioA { - pinctrl_key_gpio_default: key_gpio_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_gpio { - pinctrl_pio_rf: gpio_rf { - pinmux = ; - bias-disable; - }; - pinctrl_pio_wifi: gpio_wifi { - pinmux = ; - bias-disable; - }; - pinctrl_pio_io_boot: gpio_io_boot { - pinmux = - , - ; - bias-disable; - }; - pinctrl_pio_io_test_radio: gpio_io_test_radio { - pinmux = ; - bias-disable; - }; - pinctrl_pio_zbe_test_radio: gpio_zbe_test_radio { - pinmux = ; - bias-disable; - }; - pinctrl_pio_zbe_rst: gpio_zbe_rst { - pinmux = ; - bias-disable; - }; - /* stm32 reset must be open drain (internal pull up) */ - pinctrl_pio_io_reset: gpio_io_reset { - pinmux = ; - bias-disable; - drive-open-drain; - output-low; - }; - pinctrl_pio_input: gpio_input { - pinmux = - , - , - ; - bias-disable; - }; - }; - - pinctrl_leds { - pinctrl_led_red: led_red { - pinmux = ; - bias-disable; - }; - pinctrl_led_white: led_white { - pinmux = ; - bias-disable; - }; - }; -}; - -&adc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&flx0 { - status = "okay"; - - uart5: serial@200 { - status = "okay"; - }; -}; - -&flx3 { - status = "okay"; - uart8: serial@200 { - status = "okay"; - }; -}; - -&flx4 { - status = "okay"; - - i2c6: i2c@600 { - status = "okay"; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi deleted file mode 100644 index 465664628419..000000000000 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ /dev/null @@ -1,371 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3 - * family SoC boards - * - * Copyright (C) 2018 Overkiz SAS - * - * Authors: Dorian Rocipon - * Kevin Carli - * Mickael Gardet - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include -#include - -/ { - model = "Overkiz Kizbox3"; - compatible = "overkiz,kizbox3", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart8; - }; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = "serial1:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - vdd_adc_vddana: supply_3v3_ana { - compatible = "regulator-fixed"; - regulator-name = "adc-vddana"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_adc_vref: supply_3v3_ref { - compatible = "regulator-fixed"; - regulator-name = "adc-vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - led-controller-1 { - compatible = "pwm-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm_h0 - &pinctrl_pwm0_pwm_h1 - &pinctrl_pwm0_pwm_h2 - &pinctrl_pwm0_pwm_h3>; - status = "disabled"; - - led-1 { - label = "pwm:red:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - status = "disabled"; - }; - - led-2 { - label = "pwm:green:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - status = "disabled"; - }; - - led-3 { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - status = "disabled"; - }; - - led-4 { - label = "pwm:white:user"; - pwms = <&pwm0 3 10000000 0>; - max-brightness = <255>; - status = "disabled"; - }; - }; -}; - -&ebi { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@3 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - reg = <0x3 0x0 0x800000>; - - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - u-boot@20000 { - label = "u-boot"; - reg = <0x20000 0x140000>; - }; - - u-boot-factory@160000 { - label = "u-boot-factory"; - reg = <0x160000 0x140000>; - }; - - ubi@2A0000 { - label = "ubi"; - reg = <0x2A0000 0x7D60000>; - }; - }; - - }; -}; - -&rtc { - status = "okay"; -}; - -&pioA { - pinctrl_ebi_nand_addr: ebi-addr-1 { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_usart { - pinctrl_usart_0: usart0-0 { - pinmux = < PIN_PB26__URXD0>, ; - bias-disable; - }; - pinctrl_usart_1: usart1-0 { - pinmux = < PIN_PD2__URXD1>, ; - bias-disable; - }; - pinctrl_usart_2: usart2-0 { - pinmux = < PIN_PD4__URXD2>, ; - bias-disable; - }; - pinctrl_usart_3: usart3-0 { - pinmux = < PIN_PC12__URXD3>, ; - bias-disable; - }; - pinctrl_usart_4: usart4-0 { - pinmux = < PIN_PB3__URXD4>, ; - bias-disable; - }; - pinctrl_flx0_default: flx0_usart_default { - pinmux = , //TX - ; //RX - bias-disable; - }; - pinctrl_flx3_default: flx3_usart_default { - pinmux = , //RX - ; //TX - bias-disable; - }; - }; - - pinctrl_flx4_default: flx4_i2c6_default { - pinmux = , //DATA - ; //CLK - bias-disable; - drive-open-drain; - }; - - pinctrl_pwm0 { - pinctrl_pwm0_pwm_h0: pwm0_pwm_h0 { - pinmux = ; - bias-disable; - }; - pinctrl_pwm0_pwm_h1: pwm0_pwmh1 { - pinmux = ; - bias-disable; - }; - pinctrl_pwm0_pwm_h2: pwm0_pwm_h2 { - pinmux = ; - bias-disable; - }; - pinctrl_pwm0_pwm_h3: pwm0_pwm_h3 { - pinmux = ; - bias-disable; - }; - }; - - pinctrl_adc { - pinctrl_adc2: adc2 { - pinmux = ; - bias-disable; - }; - pinctrl_adc3: adc3 { - pinmux = ; - bias-disable; - }; - pinctrl_adc4: adc4 { - pinmux = ; - bias-disable; - }; - pinctrl_adc5: adc5 { - pinmux = ; - bias-disable; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_0>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -/* debug uart */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_1>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_2>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_3>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_4>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart5: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; -}; - -&flx3 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart8: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "disabled"; - - i2c6: i2c@600 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - status = "disabled"; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&shutdown_controller { - debounce-delay-us = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - }; -}; - -&watchdog { - status = "okay"; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc2 - &pinctrl_adc3 - &pinctrl_adc4 - &pinctrl_adc5>; - - vddana-supply = <&vdd_adc_vddana>; - vref-supply = <&vdd_adc_vref>; - status = "disabled"; -}; - -&securam { - export; - - /* export overkiz u-boot mode/version and factory */ - uboot@1400 { - reg = <0x1400 0x20>; - export; - }; -}; diff --git a/arch/arm/boot/dts/at91-kizboxmini-base.dts b/arch/arm/boot/dts/at91-kizboxmini-base.dts deleted file mode 100644 index 81c29ca5cc1b..000000000000 --- a/arch/arm/boot/dts/at91-kizboxmini-base.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini - * base board - * - * Copyright (C) 2015 Overkiz SAS - * Author: Antoine Aubert - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz Kizbox Mini"; - compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&pinctrl_usart0 { - atmel,pins = - ; -}; diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi deleted file mode 100644 index 42640fe6b6d0..000000000000 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board - * - * Copyright (C) 2014-2018 Overkiz SAS - * Author: Antoine Aubert - * Gaël Portay - * Kévin Raymond - * Dorian Rocipon - */ -#include "at91sam9g25.dtsi" - -/ { - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - main_xtal { - clock-frequency = <12000000>; - }; - - slow_xtal { - clock-frequency = <32768>; - }; - - adc_op_clk { - status = "disabled"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - key-prog { - label = "PB_PROG"; - gpios = <&pioC 17 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - key-reset { - label = "PB_RST"; - gpios = <&pioC 16 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds: led-controller-1 { - compatible = "pwm-leds"; - - led_blue: led-1 { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "none"; - status = "disabled"; - }; - - led_green: led-2 { - label = "pwm:green:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led_red: led-3 { - label = "pwm:red:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm0_1 - &pinctrl_pwm0_pwm1_1 - &pinctrl_pwm0_pwm2_1>; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&adc0 { - status = "disabled"; -}; - -&rtc { - status = "disabled"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_addr_nand - &pinctrl_ebi_data_0_7>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; -}; - -&usb0 { - num-ports = <1>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-kizboxmini-mb.dts b/arch/arm/boot/dts/at91-kizboxmini-mb.dts deleted file mode 100644 index c07d3076a9bc..000000000000 --- a/arch/arm/boot/dts/at91-kizboxmini-mb.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015-2018 Overkiz SAS - * Author: Mickael Gardet - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz Kizbox Mini Mother Board"; - compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&usb0 { - num-ports = <2>; -}; - -&rtc { - status = "okay"; -}; - -&led_blue { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-kizboxmini-rd.dts b/arch/arm/boot/dts/at91-kizboxmini-rd.dts deleted file mode 100644 index ab50f4d22387..000000000000 --- a/arch/arm/boot/dts/at91-kizboxmini-rd.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015-2018 Overkiz SAS - * Author: Mickael Gardet - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz Kizbox Mini RailDIN"; - compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; - - clocks { - adc_op_clk { - status = "okay"; - }; - }; -}; - -&pinctrl { - adc0 { - pinctrl_adc0_ad5: adc0_ad5-0 { - /* pull-up disable */ - atmel,pins = ; - }; - }; -}; - -&usart0 { - status = "disabled"; -}; - -&rtc { - status = "okay"; -}; - -&led_blue { - status = "okay"; -}; - -&adc0 { - atmel,adc-vref = <2500>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - atmel,adc-channels-used = <0x0020>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi deleted file mode 100644 index 533a440d5583..000000000000 --- a/arch/arm/boot/dts/at91-linea.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module. - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ - -#include "sama5d31.dtsi" - -/ { - compatible = "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - - -&nand_controller { - status = "okay"; - - nand: nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - }; -}; diff --git a/arch/arm/boot/dts/at91-lmu5000.dts b/arch/arm/boot/dts/at91-lmu5000.dts deleted file mode 100644 index f8863d7c0798..000000000000 --- a/arch/arm/boot/dts/at91-lmu5000.dts +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree file for CalAmp LMU5000 board - * - * Copyright (C) 2013 Adam Porter - */ - -/dts-v1/; -#include "at91sam9g20.dtsi" - -/ { - model = "CalAmp LMU5000"; - compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <18432000>; - }; - }; -}; - -&dbgu { - status = "okay"; -}; - -&ebi { - status = "okay"; - - nand_controller: nand-controller { - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - kernel@0 { - label = "kernel"; - reg = <0x0 0x400000>; - }; - - rootfs@400000 { - label = "rootfs"; - reg = <0x400000 0x3C00000>; - }; - - user1@4000000 { - label = "user1"; - reg = <0x4000000 0x2000000>; - }; - - user2@6000000 { - label = "user2"; - reg = <0x6000000 0x2000000>; - }; - }; - }; - }; -}; - -&macb0 { - phy-mode = "mii"; - status = "okay"; -}; - -&pinctrl { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = ; - }; - }; - - usb0 { - pinctrl_usb1_vbus_gpio: usb0_vbus_gpio { - atmel,pins = ; - }; - }; -}; - -&ssc0 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usart0 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usb0 { - num-ports = <2>; - status = "okay"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus_gpio>; - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-natte.dtsi b/arch/arm/boot/dts/at91-natte.dtsi deleted file mode 100644 index 49f0a0c46cde..000000000000 --- a/arch/arm/boot/dts/at91-natte.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * at91-natte.dts - Device Tree include file for the Natte board - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ - -/ { - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, - <&ioexp 1 GPIO_ACTIVE_HIGH>, - <&ioexp 2 GPIO_ACTIVE_HIGH>; - }; - - batntc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 5>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = - "batntc0", "batntc1", "batntc2", "batntc3", - "batntc4", "batntc5", "batntc6", "batntc7"; - }; - - batv-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 6>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = - "batv0", "batv1", "batv2", "batv3", - "batv4", "batv5", "batv6", "batv7"; - }; - - iout-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 7>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = - "iout0", "iout1", "iout2", "iout3", - "iout4", "iout5", "iout6", "iout7"; - }; - - i2c-mux { - compatible = "i2c-mux"; - mux-locked; - i2c-parent = <&i2c0>; - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; - - ioexp: ioexp@20 { - #gpio-cells = <2>; - compatible = "semtech,sx1502q"; - reg = <0x20>; - - gpio-controller; - ngpios = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio3_cfg_pins>; - - gpio3_cfg_pins: gpio3_cfg { - pins = "gpio3"; - bias-pull-up; - }; - }; - - adc: adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <2>; - ti,datarate = <4>; - }; - - channel@5 { - reg = <5>; - ti,gain = <2>; - ti,datarate = <4>; - }; - - channel@6 { - reg = <6>; - ti,gain = <1>; - ti,datarate = <4>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts deleted file mode 100644 index f71377c9b757..000000000000 --- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts +++ /dev/null @@ -1,306 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ -/dts-v1/; -#include "at91-linea.dtsi" -#include "at91-natte.dtsi" - -/ { - model = "Axentia Linea-Nattis v2 Natte v2"; - compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "Wakeup"; - linux,code = <10>; - wakeup-source; - gpios = <&pioB 27 GPIO_ACTIVE_LOW>; - }; - }; - - panel_reg: panel-regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-VCC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - bl_reg: backlight-regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-VDD"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - panel_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 100000 0>; - - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <40>; - - power-supply = <&bl_reg>; - enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_blon>; - }; - - panel: panel { - compatible = "sharp,lq150x1lg11", "panel-lvds"; - - backlight = <&panel_bl>; - power-supply = <&panel_reg>; - - width-mm = <304>; - height-mm = <228>; - - data-mapping = "jeida-18"; - - panel-timing { - // 1024x768 @ 60Hz (typical) - clock-frequency = <50000000 65000000 80000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <48 88 88>; - hback-porch = <96 168 168>; - hsync-len = <32 64 64>; - vsync-len = <3 13 74>; - vfront-porch = <3 13 74>; - vback-porch = <3 12 74>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; - }; - - lvds-encoder { - compatible = "ti,ds90c185", "lvds-encoder"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&hlcdc_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "nattis-tfa9879"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&cpu_dai>; - simple-audio-card,frame-master = <&cpu_dai>; - simple-audio-card,widgets = "Line", "Line Out Jack"; - simple-audio-card,routing = "Line Out Jack", "LINEOUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssc0>; - }; - - simple-audio-card,codec { - sound-dai = <&>; - }; - }; -}; - -&pinctrl { - nattis { - pinctrl_usba_vbus: usba_vbus { - atmel,pins = ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = ; - }; - - pinctrl_lvds_prlud0: lvds_prlud0 { - atmel,pins = ; - }; - - pinctrl_lvds_hipow0: lvds_hipow0 { - atmel,pins = ; - }; - - pinctrl_blon: blon { - atmel,pins = ; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <100000>; - - temp@18 { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x18>; - smbus-timeout-disable; - }; - - eeprom@50 { - compatible = "nxp,se97b", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - amp: amplifier@6c { - compatible = "nxp,tfa9879"; - reg = <0x6c>; - #sound-dai-cells = <0>; - }; -}; - -&ssc0 { - status = "okay"; - - atmel,clk-from-rk-pin; - #sound-dai-cells = <0>; -}; - -&hlcdc { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; - - port@0 { - hlcdc_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <16>; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 - &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_cd>; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cd-inverted; - }; -}; - -&usart0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - atmel,use-dma-rx; -}; - -&nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - barebox@40000 { - label = "barebox"; - reg = <0x40000 0x60000>; - }; - - bareboxenv@c0000 { - label = "bareboxenv"; - reg = <0xc0000 0x40000>; - }; - - bareboxenv2@100000 { - label = "bareboxenv2"; - reg = <0x100000 0x40000>; - }; - - oftree@180000 { - label = "oftree"; - reg = <0x180000 0x20000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; -}; - -&dbgu { - status = "okay"; - - atmel,use-dma-rx; -}; - -&usb0 { - status = "okay"; - - atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; -}; diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/at91-q5xr5.dts deleted file mode 100644 index 9cf60b6f695c..000000000000 --- a/arch/arm/boot/dts/at91-q5xr5.dts +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree file for Exegin Q5xR5 board - * - * Copyright (C) 2014 Owen Kirby - */ - -/dts-v1/; -#include "at91sam9g20.dtsi" - -/ { - model = "Exegin Q5x (rev5)"; - compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2"; - }; - - memory { - reg = <0x20000000 0x0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <18432000>; - }; - - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; -}; - -&dbgu { - status = "okay"; -}; - -&ebi { - status = "okay"; - - flash: flash@0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x1000000 0x800000>; - bank-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - kernel@0 { - label = "kernel"; - reg = <0x0 0x200000>; - }; - - rootfs@200000 { - label = "rootfs"; - reg = <0x200000 0x600000>; - }; - }; - }; -}; - -&macb0 { - phy-mode = "mii"; - status = "okay"; -}; - -&pinctrl { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; - }; - - pinctrl_spi0_npcs0: spi0_npcs0 { - atmel,pins = ; - }; - - pinctrl_spi0_npcs1: spi0_npcs1 { - atmel,pins = ; - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; - }; - - pinctrl_spi1_npcs0: spi1_npcs0 { - atmel,pins = ; - }; - - pinctrl_spi1_npcs1: spi1_npcs1 { - atmel,pins = ; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>; - cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - at91boot@0 { - label = "at91boot"; - reg = <0x0 0x4000>; - }; - - uenv@4000 { - label = "uboot-env"; - reg = <0x4000 0x4000>; - }; - - uboot@8000 { - label = "uboot"; - reg = <0x8000 0x3E000>; - }; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>; - cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>; - status = "okay"; -}; - -&usart0 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; -}; - -&usb0 { - num-ports = <2>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts deleted file mode 100644 index 9d26f9996348..000000000000 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board - * - * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9260.dtsi" -/ { - model = "Calao QIL A9260"; - compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - pinctrl-0 = - <&pinctrl_usart1 - &pinctrl_usart1_rts - &pinctrl_usart1_cts>; - status = "okay"; - }; - - usart2: serial@fffb8000 { - pinctrl-0 = - <&pinctrl_usart2 - &pinctrl_usart2_rts - &pinctrl_usart2_cts>; - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - spi0: spi@fffc8000 { - status = "okay"; - cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; - - m41t94@0 { - compatible = "st,m41t94"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@a0000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@c0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4c0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7cc0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-user { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts deleted file mode 100644 index 2fb51b9aca2a..000000000000 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board - * - * Copyright (C) 2016 Raashid Muhammed - */ -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Olimex sam9-l9260"; - compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; - }; - }; - - macb0: ethernet@fffc4000 { - pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - }; - }; - - spi0: spi@fffc8000 { - cs-gpios = <&pioC 11 0>, <0>, <0>, <0>; - status = "okay"; - - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* WP pin */ - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - }; - - usb0: ohci@500000 { - status = "okay"; - }; - - }; - - i2c-gpio-0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "sam9-l9260:yellow:pwr"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - }; - - status_led { - label = "sam9-l9260:green:status"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/at91-sam9x60_curiosity.dts deleted file mode 100644 index cb86a3a170ce..000000000000 --- a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts +++ /dev/null @@ -1,503 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board - * - * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries - * - * Author: Durai Manickam KR - */ -/dts-v1/; -#include "sam9x60.dtsi" -#include - -/ { - model = "Microchip SAM9X60 Curiosity"; - compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c6; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button-user { - label = "PB_USER"; - gpios = <&pioA 29 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-red { - label = "red"; - gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - }; - - led-green { - label = "green"; - gpios = <&pioD 19 GPIO_ACTIVE_HIGH>; - }; - - led-blue { - label = "blue"; - gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - - vdd_1v8: regulator-0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "VDD_1V8"; - }; - - vdd_1v15: regulator-1 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <1150000>; - regulator-min-microvolt = <1150000>; - regulator-name = "VDD_1V15"; - }; - - vdd1_3v3: regulator-2 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VDD1_3V3"; - }; -}; - -&adc { - vddana-supply = <&vdd1_3v3>; - vref-supply = <&vdd1_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - status = "disabled"; /* Conflict with dbgu. */ -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - status = "okay"; -}; - -&dbgu { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - status = "okay"; /* Conflict with can0. */ -}; - -&ebi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_lsb>; - status = "okay"; - - nand_controller: nand-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0xc0000>; - }; - - ubootenvred@100000 { - label = "U-Boot Env Redundant"; - reg = <0x100000 0x40000>; - }; - - ubootenv@140000 { - label = "U-Boot Env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c0: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - }; -}; - -&flx6 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c6: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx6_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "disabled"; - }; -}; - -&flx7 { - atmel,flexcom-mode = ; - status = "okay"; - - uart7: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx7_default>; - status = "okay"; - }; -}; - -&macb0 { - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - status = "okay"; - - ethernet-phy@0 { - reg = <0x0>; - }; -}; - -&pinctrl { - adc { - pinctrl_adc_default: adc-default { - atmel,pins = ; - }; - - pinctrl_adtrg_default: adtrg-default { - atmel,pins = ; - }; - }; - - can0 { - pinctrl_can0_rx_tx: can0-rx-tx { - atmel,pins = - ; /* Enable CAN Transceivers */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1-rx-tx { - atmel,pins = - ; /* Enable CAN Transceivers */ - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = ; - }; - }; - - ebi { - pinctrl_ebi_data_lsb: ebi-data-lsb { - atmel,pins = - ; - }; - - pinctrl_ebi_addr_nand: ebi-addr-nand { - atmel,pins = - ; - }; - }; - - flexcom { - pinctrl_flx0_default: flx0-twi { - atmel,pins = - ; - }; - - pinctrl_flx6_default: flx6-twi { - atmel,pins = - ; - }; - - pinctrl_flx7_default: flx7-usart { - atmel,pins = - ; - }; - }; - - gpio-keys { - pinctrl_key_gpio_default: pinctrl-key-gpio { - atmel,pins = ; - }; - }; - - leds { - pinctrl_gpio_leds: gpio-leds { - atmel,pins = ; - }; - }; - - macb0 { - pinctrl_macb0_rmii: macb0-rmii-0 { - atmel,pins = - ; /* PB10 periph A */ - }; - }; - - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - ; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - pwm0 { - pinctrl_pwm0_0: pwm0-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_1: pwm0-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_2: pwm0-2 { - atmel,pins = ; - }; - }; - - sdmmc0 { - pinctrl_sdmmc0_default: sdmmc0 { - atmel,pins = - ; /* PA20 DAT3 periph A with pullup */ - }; - - pinctrl_sdmmc0_cd: sdmmc0-cd { - atmel,pins = - ; - }; - }; - - sdmmc1 { - pinctrl_sdmmc1_default: sdmmc1 { - atmel,pins = - ; /* PA4 DAT3 periph B with pullup */ - }; - }; - - usb0 { - pinctrl_usba_vbus: usba-vbus { - atmel,pins = ; - }; - }; - - usb1 { - pinctrl_usb_default: usb-default { - atmel,pins = ; - }; - }; -}; /* pinctrl */ - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; - cd-gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - disable-wp; - status = "okay"; -}; - -&sdmmc1 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - disable-wp; - status = "okay"; -}; - -&shutdown_controller { - debounce-delay-us = <976>; - status = "okay"; - - input@0 { - reg = <0>; - }; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usb0 { - atmel,vbus-gpio = <&pioA 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioD 18 GPIO_ACTIVE_HIGH - &pioD 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts deleted file mode 100644 index 5cd593028aff..000000000000 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ /dev/null @@ -1,669 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Sandeep Sheriker M - */ -/dts-v1/; -#include "sam9x60.dtsi" -#include - -/ { - model = "Microchip SAM9X60-EK"; - compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c6; - serial1 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button-1 { - label = "SW1"; - gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - status = "okay"; /* Conflict with pwm0. */ - - red { - label = "red"; - gpios = <&pioB 11 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "green"; - gpios = <&pioB 12 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "blue"; - gpios = <&pioB 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vdd_1v8: fixed-regulator-vdd_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_1v15: fixed-regulator-vdd_1v15 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - vdd1_3v3: fixed-regulator-vdd1_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDD1_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd2_3v3: regulator-fixed-vdd2_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDD2_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&adc { - vddana-supply = <&vdd1_3v3>; - vref-supply = <&vdd1_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - status = "disabled"; /* Conflict with dbgu. */ -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - status = "okay"; -}; - -&classd { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_classd_default>; - atmel,pwm-type = "diff"; - atmel,non-overlap-time = <10>; - status = "okay"; -}; - -&dbgu { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - status = "okay"; /* Conflict with can0. */ -}; - -&ebi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; - status = "okay"; - - nand_controller: nand-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0xc0000>; - }; - - ubootenvred@100000 { - label = "U-Boot Env Redundant"; - reg = <0x100000 0x40000>; - }; - - ubootenv@140000 { - label = "U-Boot Env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c0: i2c@600 { - #address-cells = <1>; - #size-cells = <0>; - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - status = "okay"; - }; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "disabled"; - - spi4: spi@400 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - status = "disabled"; - }; -}; - -&flx5 { - atmel,flexcom-mode = ; - status = "okay"; - - uart5: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx5_default>; - status = "okay"; - }; -}; - -&flx6 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c6: i2c@600 { - #address-cells = <1>; - #size-cells = <0>; - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx6_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - gpio_exp: mcp23008@20 { - compatible = "microchip,mcp23008"; - reg = <0x20>; - }; - }; -}; - -&gpbr { - status = "okay"; -}; - -&i2s { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_default>; - #sound-dai-cells = <0>; - status = "disabled"; /* Conflict with QSPI. */ -}; - -&macb0 { - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - status = "okay"; - - ethernet-phy@0 { - reg = <0x0>; - }; -}; - -&pinctrl { - adc { - pinctrl_adc_default: adc_default { - atmel,pins = ; - }; - - pinctrl_adtrg_default: adtrg_default { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = ; - }; - }; - - i2s { - pinctrl_i2s_default: i2s { - atmel,pins = - ; /* I2SMCK */ - }; - }; - - qspi { - pinctrl_qspi: qspi { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - ; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - ebi { - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_0_15: ebi-data-msb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - ; - }; - }; - - flexcom { - pinctrl_flx0_default: flx0_twi { - atmel,pins = - ; - }; - - pinctrl_flx4_default: flx4_spi { - atmel,pins = - ; - }; - - pinctrl_flx5_default: flx5_uart { - atmel,pins = - ; - }; - - pinctrl_flx6_default: flx6_twi { - atmel,pins = - ; - }; - }; - - classd { - pinctrl_classd_default: classd { - atmel,pins = - ; - }; - }; - - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* Enable CAN Transceivers */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* Enable CAN Transceivers */ - }; - }; - - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; /* PB10 periph A */ - }; - }; - - pwm0 { - pinctrl_pwm0_0: pwm0_0 { - atmel,pins = ; - }; - - pinctrl_pwm0_1: pwm0_1 { - atmel,pins = ; - }; - - pinctrl_pwm0_2: pwm0_2 { - atmel,pins = ; - }; - - pinctrl_pwm0_3: pwm0_3 { - atmel,pins = ; - }; - }; - - sdmmc0 { - pinctrl_sdmmc0_default: sdmmc0 { - atmel,pins = - ; /* PA20 DAT3 periph A with pullup */ - }; - pinctrl_sdmmc0_cd: sdmmc0_cd { - atmel,pins = - ; - }; - }; - - sdmmc1 { - pinctrl_sdmmc1_default: sdmmc1 { - atmel,pins = - ; /* PA4 DAT3 periph B with pullup */ - }; - }; - - gpio_keys { - pinctrl_key_gpio_default: pinctrl_key_gpio { - atmel,pins = ; - }; - }; - - usb0 { - pinctrl_usba_vbus: usba_vbus { - atmel,pins = ; - }; - }; - - usb1 { - pinctrl_usb_default: usb_default { - atmel,pins = ; - }; - }; - - leds { - pinctrl_gpio_leds: gpio_leds { - atmel,pins = ; - }; - }; -}; /* pinctrl */ - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>; - status = "disabled"; /* Conflict with leds. */ -}; - -&sdmmc0 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; - status = "okay"; - cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - disable-wp; -}; - -&sdmmc1 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - no-1-8-v; - non-removable; - status = "disabled"; /* Conflict with flx4. */ -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; /* Conflict with i2s. */ - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - at91bootstrap@0 { - label = "qspi: at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "qspi: bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "qspi: bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "qspi: bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "qspi: device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "qspi: kernel"; - reg = <0x200000 0x600000>; - }; - }; -}; - -&rtt { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; -}; - -&shutdown_controller { - debounce-delay-us = <976>; - status = "okay"; - - input@0 { - reg = <0>; - }; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usb0 { - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioD 15 GPIO_ACTIVE_HIGH - &pioD 16 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi deleted file mode 100644 index 95ecb7d040a8..000000000000 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board - * - * Copyright (c) 2017, Microchip Technology Inc. - * 2017 Cristian Birsan - * 2017 Claudiu Beznea - */ -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include - -/ { - model = "Atmel SAMA5D27 SoM1"; - compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - i2c0 = &i2c0; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - ahb { - sdmmc0: sdio-host@a0000000 { - microchip,sdcal-inverted; - }; - - apb { - qspi1: spi@f0024000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1_default>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x00000000 0x00040000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x00040000 0x000c0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x00100000 0x00040000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x00140000 0x00040000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x00180000 0x00080000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x00200000 0x00600000>; - }; - }; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default>; - #address-cells = <1>; - #size-cells = <0>; - phy-mode = "rmii"; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioA>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_phy_irq>; - }; - }; - - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <8>; - }; - }; - - pinctrl@fc038000 { - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_gpio: i2c0_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_qspi1_default: qspi1_default { - sck_cs { - pinmux = , - ; - bias-disable; - }; - - data { - pinmux = , - , - , - ; - bias-pull-up; - }; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts deleted file mode 100644 index 52ddd0571f1c..000000000000 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ /dev/null @@ -1,552 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board - * - * Copyright (c) 2017, Microchip Technology Inc. - * 2016 Nicolas Ferre - * 2017 Cristian Birsan - * 2017 Claudiu Beznea - */ -/dts-v1/; -#include "at91-sama5d27_som1.dtsi" -#include -#include -#include - -/ { - model = "Atmel SAMA5D27 SOM1 EK"; - compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart1; /* DBGU */ - serial1 = &uart4; /* mikro BUS 1 */ - serial2 = &uart2; /* mikro BUS 2 */ - i2c1 = &i2c1; - i2c2 = &i2c3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ahb { - usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ - &pioA PIN_PA27 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@500000 { - status = "okay"; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - mmc-ddr-3_3v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; - }; - - sdmmc1: sdio-host@b0000000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - status = "okay"; - }; - - apb { - isc: isc@f0008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>; - }; - - qspi1: spi@f0024000 { - status = "okay"; - }; - - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - }; - - macb0: ethernet@f8008000 { - status = "okay"; - }; - - tcb0: timer@f800c000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - uart1: serial@f8020000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - uart2: serial@f8024000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus2_uart>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - pwm0: pwm@f802c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; - status = "disabled"; /* Conflict with leds. */ - }; - - flx1: flexcom@f8038000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c3: i2c@600 { - dmas = <0>, <0>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_mikrobus_i2c>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&pioA PIN_PA24 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PA23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - }; - }; - - shdwc@f8048010 { - debounce-delay-us = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - uart3: serial@fc008000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - status = "disabled"; /* Conflict with isc. */ - }; - - uart4: serial@fc00c000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_uart>; - status = "okay"; - }; - - flx3: flexcom@fc014000 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart8: serial@200 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - status = "disabled"; /* Conflict with isc. */ - }; - - spi5: spi@400 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - status = "disabled"; /* Conflict with isc. */ - }; - }; - - flx4: flexcom@fc018000 { - atmel,flexcom-mode = ; - status = "okay"; - - uart9: serial@200 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - status = "disabled"; /* Conflict with spi6 and i2c6. */ - }; - - spi6: spi@400 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; - status = "okay"; /* Conflict with uart5 and i2c6. */ - }; - - i2c6: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - status = "disabled"; /* Conflict with uart5 and spi6. */ - }; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - }; - - adc: adc@fc030000 { - vddana-supply = <&vddana>; - vref-supply = <&advref>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_an &pinctrl_mikrobus2_an>; - - status = "okay"; - }; - - pinctrl@fc038000 { - - pinctrl_can1_default: can1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx3_default: flx3_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; - - - pinctrl_isc_base: isc_base { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_isc_data_8bit: isc_data_8bit { - pinmux = , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_isc_data_9_10: isc_data_9_10 { - pinmux = , - ; - bias-disable; - }; - - pinctrl_isc_data_11_12: isc_data_11_12 { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - ck_cd_vddsel { - pinmux = , - , - ; - bias-disable; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - conf-ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart1_default: uart1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_an: mikrobus1_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_an: mikrobus2_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_rst: mikrobus1_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_rst: mikrobus2_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus_spi: mikrobus_spi { - pinmux = , - , - ; - bias-disable; - }; - - pinctrl_mikrobus1_pwm: mikrobus1_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_pwm: mikrobus2_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_int: mikrobus1_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_int: mikrobus2_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_uart: mikrobus1_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus2_uart: mikrobus2_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus_i2c: mikrobus1_i2c { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c3_gpio: i2c3_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx4_default: flx4_uart_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - }; - - can1: can@fc050000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button { - label = "USER"; - gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; /* Conflict with pwm0. */ - - led-red { - label = "red"; - gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; - }; - - led-green { - label = "green"; - gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; - }; - - led-blue { - label = "blue"; - gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vddin_3v3: fixed-regulator-vddin_3v3 { - compatible = "regulator-fixed"; - - regulator-name = "VDDIN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vddana: fixed-regulator-vddana { - compatible = "regulator-fixed"; - - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vddin_3v3>; - status = "okay"; - }; - - advref: fixed-regulator-advref { - compatible = "regulator-fixed"; - - regulator-name = "advref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vddana>; - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi deleted file mode 100644 index 4617805c7748..000000000000 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ /dev/null @@ -1,386 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1 - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Nicolas Ferre - * Author: Eugen Hristev - */ -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include - -/ { - model = "Microchip SAMA5D27 WLSOM1"; - compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - i2c0 = &i2c0; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-wilc1000"; - reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; - powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pinctrl_wilc_pwrseq>; - pinctrl-names = "default"; - }; -}; - -&flx1 { - atmel,flexcom-mode = ; - - uart6: serial@200 { - pinctrl-0 = <&pinctrl_flx1_default>; - pinctrl-names = "default"; - }; -}; - -&i2c0 { - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - pinctrl-names = "default", "gpio"; - sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c1 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - mcp16502@5b { - compatible = "microchip,mcp16502"; - reg = <0x5b>; - status = "okay"; - lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>; - - regulators { - vdd_3v3: VDD_IO { - regulator-name = "VDD_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vddio_ddr: VDD_DDR { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1200000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1200000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - }; - - vdd_core: VDD_CORE { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vdd_ddr: VDD_OTHER { - regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&macb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default>; - #address-cells = <1>; - #size-cells = <0>; - phy-mode = "rmii"; - - ethernet-phy@0 { - reg = <0x0>; - interrupt-parent = <&pioA>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_phy_irq>; - }; -}; - -&pmc { - atmel,osc-bypass; -}; - -&qspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1_default>; - status = "disabled"; - - qspi1_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - m25p,fast-read; - status = "disabled"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - }; -}; - -&pioA { - pinctrl_flx1_default: flx1_usart_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_gpio: i2c0_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_qspi1_default: qspi1_default { - pinmux = , - , - , - , - , - ; - bias-pull-up; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd-data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - conf-ck { - pinmux = ; - bias-disable; - }; - }; - - pinctrl_wilc_default: wilc_default { - conf-irq { - pinmux = ; - bias-disable; - }; - }; - - pinctrl_wilc_pwrseq: wilc_pwrseq { - conf-ce-nrst { - pinmux = , - ; - bias-disable; - }; - - conf-rtcclk { - pinmux = ; - bias-disable; - }; - }; -}; - -&sdmmc1 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - mmc-pwrseq = <&wifi_pwrseq>; - no-1-8-v; - non-removable; - bus-width = <4>; - status = "okay"; - - wilc: wifi@0 { - reg = <0>; - compatible = "microchip,wilc1000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wilc_default>; - clocks = <&pmc PMC_TYPE_SYSTEM 9>; - clock-names = "rtc"; - interrupts = ; - interrupt-parent = <&pioA>; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; - assigned-clock-rates = <32768>; - }; -}; - diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts deleted file mode 100644 index e055b9e2fe34..000000000000 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ /dev/null @@ -1,269 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Nicolas Ferre - */ -/dts-v1/; -#include "at91-sama5d27_wlsom1.dtsi" -#include - -/ { - model = "Microchip SAMA5D27 WLSOM1 EK"; - compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; /* DBGU */ - serial1 = &uart6; /* BT */ - serial2 = &uart5; /* mikro BUS 2 */ - serial3 = &uart3; /* mikro BUS 1 */ - i2c1 = &i2c1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button-1 { - label = "USER BUTTON"; - gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; - - led-red { - label = "red"; - gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; - }; - - led-green { - label = "green"; - gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; - }; - - led-blue { - label = "blue"; - gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&adc { - vddana-supply = <&vdd_3v3>; - vref-supply = <&vdd_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default>; - status = "okay"; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "okay"; - - uart5: serial@200 { - pinctrl-0 = <&pinctrl_flx0_default>; - pinctrl-names = "default"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; -}; - -&flx1 { - status = "okay"; - - uart6: serial@200 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; -}; - -&macb0 { - status = "okay"; -}; - -&pioA { - /* - * There is no real pinmux for ADC, if the pin - * is not requested by another peripheral then - * the muxing is done when channel is enabled. - * Requesting pins for ADC is GPIO is - * encouraged to prevent conflicts and to - * disable bias in order to be in the same - * state when the pin is not muxed to the adc. - */ - pinctrl_adc_default: adc_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx0_default: flx0_usart_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-down; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - ck_cd_vddsel { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - pinctrl_uart0_default: uart0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_pwm0_default: pwm0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default>; - status = "okay"; -}; - -&qspi1 { - status = "okay"; - - qspi1_flash: flash@0 { - status = "okay"; - }; -}; - -&sdmmc0 { - bus-width = <4>; - mmc-ddr-3_3v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; -}; - -&shutdown_controller { - debounce-delay-us = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - }; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&usb0 { - atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioA PIN_PA10 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; -}; - -&usb2 { - phy_type = "hsic"; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts deleted file mode 100644 index 999adeca6f33..000000000000 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ /dev/null @@ -1,790 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Radu Pirea & Razvan Stefanescu, - * Codrin Ciubotariu , - * Cristian Birsan - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include - -/ { - model = "Microchip SAMA5D2-ICP"; - compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ - serial1 = &uart1; /* mikro BUS 3 */ - serial3 = &uart3; /* mikro BUS 2 */ - serial5 = &uart7; /* flx2 */ - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button-1 { - label = "USER_PB1"; - gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; /* conflict with pwm0 */ - - led-red { - label = "red"; - gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; - }; - - led-green { - label = "green"; - gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; - }; - - led-blue { - label = "blue"; - gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&adc { - vddana-supply = <&vdd_io_reg>; - vref-supply = <&vdd_io_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; - status = "okay"; -}; - -&flx0 { /* mikrobus2 spi */ - atmel,flexcom-mode = ; - status = "okay"; - - spi2: spi@400 { - dmas = <0>, <0>; - cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - switch0: ksz8563@0 { - compatible = "microchip,ksz8563"; - reg = <0>; - reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>; - - spi-max-frequency = <500000>; - spi-cpha; - spi-cpol; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "cpu"; - ethernet = <&macb0>; - phy-mode = "mii"; - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&flx2 { - atmel,flexcom-mode = ; - status = "okay"; - - uart7: serial@200 { - pinctrl-0 = <&pinctrl_flx2_default>; - pinctrl-names = "default"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; /* Conflict w/ qspi1. */ - }; -}; - -&flx3 { /* mikrobus1 spi */ - atmel,flexcom-mode = ; - status = "okay"; - - spi5: spi@400 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; - status = "okay"; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c6: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - mcp16502@5b { - compatible = "microchip,mcp16502"; - reg = <0x5b>; - status = "okay"; - lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>; - - regulators { - vdd_io_reg: VDD_IO { - regulator-name = "VDD_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_DDR { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_CORE { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_OTHER { - regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - }; - }; - }; -}; - -&i2c0 { /* mikrobus i2c */ - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_mikrobus_i2c>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; -}; - -&i2c1 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - status = "okay"; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - status = "disabled"; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - status = "disabled"; - }; -}; - -&macb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; - phy-mode = "mii"; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&pioA { - pinctrl_adc_default: adc_default { - pinmux = , - , - ; - bias-disable; - }; - - /* - * The ADTRG pin can work on any edge type. - * In here it's being pulled up, so need to - * connect it to ground to get an edge e.g. - * Trigger can be configured on falling, rise - * or any edge, and the pull-up can be changed - * to pull-down or left floating according to - * needs. - */ - pinctrl_adtrg_default: adtrg_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_flx4_default: flx4_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_can0_default: can0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_can1_default: can1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_qspi1_default: qspi1_default { - pinmux = , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - ; - bias-disable; - }; - - ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_mikrobus_i2c: mikrobus_i2c { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_gpio: i2c0_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus1_an: mikrobus1_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_rst: mikrobus1_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_spi: mikrobus1_spi { - pinmux = , - , - ; - bias-disable; - }; - - pinctrl_mikrobus1_pwm: mikrobus1_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_int: mikrobus1_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_uart: mikrobus1_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus2_an: mikrobus2_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_rst: mikrobus2_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_spi: mikrobus2_spi { - pinmux = , - , - ; - bias-disable; - }; - - pinctrl_ksz_spi_cs: ksz_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_pwm: mikrobus2_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_int: mikrobus2_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_uart: mikrobus2_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus3_an: mikrobus3_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus3_rst: mikrobus3_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus3_spi: mikrobus3_spi { - pinmux = , - , - ; - bias-disable; - }; - - pinctrl_mikrobus3_pwm: mikrobus3_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus3_int: mikrobus3_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus3_uart: mikrobus3_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { - pinmux = , - ; - bias-pull-up; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_macb0_rst: macb0_sw_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_flx2_default: flx2_default { - pinmux = , - , - , - ; - bias-disable; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; - status = "disabled"; /* conflict with leds, HSIC */ -}; - -&qspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1_default>; - status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */ - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-cs-setup-ns = <7>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - at91bootstrap@0 { - label = "qspi: at91bootstrap"; - reg = <0x00000000 0x00040000>; - }; - - bootloader@40000 { - label = "qspi: bootloader"; - reg = <0x00040000 0x000c0000>; - }; - - bootloaderenvred@100000 { - label = "qspi: bootloader env redundant"; - reg = <0x00100000 0x00040000>; - }; - - bootloaderenv@140000 { - label = "qspi: bootloader env"; - reg = <0x00140000 0x00040000>; - }; - - dtb@180000 { - label = "qspi: device tree"; - reg = <0x00180000 0x00080000>; - }; - - kernel@200000 { - label = "qspi: kernel"; - reg = <0x00200000 0x00600000>; - }; - }; -}; - -&sdmmc0 { - no-1-8-v; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; -}; - -&shutdown_controller { - debounce-delay-us = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - }; -}; - -&spi0 { /* mikrobus3 spi */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>; - status = "okay"; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_uart>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus3_uart>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus2_uart>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&usb0 { - atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; -}; - -&usb1 { - num-ports = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; -}; - -&usb2 { - phy_type = "hsic"; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts deleted file mode 100644 index bf1c9ca72a9f..000000000000 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ /dev/null @@ -1,435 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board - * - * Copyright (C) 2017 Microchip/Atmel, - * 2017 Wenyou Yang - * 2017 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include -#include - -/ { - model = "Atmel SAMA5D2 PTC EK"; - compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; /* DBGU */ - i2c0 = &i2c0; /* mikroBUS 1 */ - i2c1 = &i2c1; /* XPRO EXT1 */ - i2c2 = &i2c2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - ahb { - usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioA PIN_PB12 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@500000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_default>; - status = "okay"; /* conflicts with sdmmc1 and qspi0 */ - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; - }; - - apb { - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; - #address-cells = <1>; - #size-cells = <0>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioA>; - interrupts = <56 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - tcb0: timer@f800c000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - uart0: serial@f801c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - uart2: serial@f8024000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - }; - - flx0: flexcom@f8034000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c2: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_flx0_default>; - pinctrl-1 = <&pinctrl_flx0_gpio>; - sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - }; - }; - - shdwc@f8048010 { - debounce-delay-us = <976>; - - input@0 { - reg = <0>; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - spi1: spi@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - status = "okay"; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <8>; - }; - }; - - pinctrl@fc038000 { - pinctrl_flx0_default: flx0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx0_gpio: flx0_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_gpio: i2c0_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_nand_default: nand_default { - re_we_data { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-pull-up; - atmel,drive-strength = ; - }; - - ale_cle_rdy_cs { - pinmux = , - , - , - ; - bias-pull-up; - }; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-pull-up; - }; - - ck_cd_vddsel { - pinmux = , - , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_spi1_default: spi1_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart0_default: uart0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart2_default: uart2_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - }; - - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button-1 { - label = "PB_USER"; - gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; - - led-red { - label = "red"; - gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; - }; - - led-green { - label = "green"; - gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; - }; - - led-blue { - label = "blue"; - gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts deleted file mode 100644 index 2d53c47d7cc8..000000000000 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ /dev/null @@ -1,745 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board - * - * Copyright (C) 2015 Atmel, - * 2015 Nicolas Ferre - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include -#include - -/ { - model = "Atmel SAMA5D2 Xplained"; - compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart1; /* DBGU */ - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; /* XPRO EXT2 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ - &pioA PIN_PB10 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@500000 { - status = "okay"; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-3_3v; - status = "okay"; - }; - - sdmmc1: sdio-host@b0000000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - status = "okay"; /* conflict with qspi0 */ - vqmmc-supply = <&vdd_3v3_reg>; - vmmc-supply = <&vdd_3v3_reg>; - }; - - apb { - qspi0: spi@f0020000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0_default>; - status = "disabled"; /* conflict with sdmmc1 */ - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x00000000 0x00040000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x00040000 0x000c0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x00100000 0x00040000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x00140000 0x00040000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x00180000 0x00080000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x00200000 0x00600000>; - }; - - misc@800000 { - label = "misc"; - reg = <0x00800000 0x00000000>; - }; - }; - }; - - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - - flash@0 { - compatible = "atmel,at25df321a"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; - #address-cells = <1>; - #size-cells = <0>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioA>; - interrupts = ; - }; - }; - - tcb0: timer@f800c000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - uart1: serial@f8020000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-sda-hold-time-ns = <350>; - status = "okay"; - - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - active-semi,vsel-high; - status = "okay"; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <1400000>; - regulator-suspend-max-microvolt = <1400000>; - regulator-changeable-in-suspend; - regulator-mode = ; - }; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - charger { - compatible = "active-semi,act8945a-charger"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - interrupt-parent = <&pioA>; - interrupts = ; - - active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - status = "okay"; - }; - }; - }; - - pwm0: pwm@f802c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; - status = "disabled"; /* conflict with leds */ - }; - - flx0: flexcom@f8034000 { - atmel,flexcom-mode = ; - status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ - - uart5: serial@200 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - status = "okay"; - }; - - i2c2: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_flx0_default>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-sda-hold-time-ns = <350>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ - }; - }; - - shdwc@f8048010 { - debounce-delay-us = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - i2s0: i2s@f8050000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s0_default>; - status = "disabled"; /* conflict with can0 */ - }; - - can0: can@f8054000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; - status = "okay"; - }; - - uart3: serial@fc008000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - status = "okay"; - }; - - flx4: flexcom@fc018000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c6: i2c@600 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_flx4_default>; - pinctrl-1 = <&pinctrl_flx4_gpio>; - sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - }; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - at24@54 { - compatible = "atmel,24c02"; - reg = <0x54>; - pagesize = <16>; - }; - }; - - adc: adc@fc030000 { - vddana-supply = <&vdd_3v3_lp_reg>; - vref-supply = <&vdd_3v3_lp_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; - status = "okay"; - }; - - pinctrl@fc038000 { - /* - * There is no real pinmux for ADC, if the pin - * is not requested by another peripheral then - * the muxing is done when channel is enabled. - * Requesting pins for ADC is GPIO is - * encouraged to prevent conflicts and to - * disable bias in order to be in the same - * state when the pin is not muxed to the adc. - */ - pinctrl_adc_default: adc_default { - pinmux = ; - bias-disable; - }; - - pinctrl_can0_default: can0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_can1_default: can1_default { - pinmux = , - ; - bias-disable; - }; - - /* - * The ADTRG pin can work on any edge type. - * In here it's being pulled up, so need to - * connect it to ground to get an edge e.g. - * Trigger can be configured on falling, rise - * or any edge, and the pull-up can be changed - * to pull-down or left floating according to - * needs. - */ - pinctrl_adtrg_default: adtrg_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_charger_chglev: charger_chglev { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_irq: charger_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_lbo: charger_lbo { - pinmux = ; - bias-pull-up; - }; - - pinctrl_classd_default_pfets: classd_default_pfets { - pinmux = , - ; - bias-pull-up; - }; - - pinctrl_classd_default_nfets: classd_default_nfets { - pinmux = , - ; - bias-pull-down; - }; - - pinctrl_flx0_default: flx0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx4_default: flx4_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx4_gpio: flx4_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_gpio: i2c0_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c2_gpio: i2c2_gpio { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2s0_default: i2s0_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_i2s1_default: i2s1_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_qspi0_default: qspi0_default { - sck_cs { - pinmux = , - ; - bias-disable; - }; - - data { - pinmux = , - , - , - ; - bias-pull-up; - }; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - ck_cd_rstn { - pinmux = , - , - ; - bias-disable; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - conf-ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart1_default: uart1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { - pinmux = , - ; - bias-pull-up; - }; - }; - - classd: classd@fc048000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_classd_default_pfets &pinctrl_classd_default_nfets>; - atmel,pwm-type = "diff"; - atmel,non-overlap-time = <10>; - status = "okay"; - }; - - i2s1: i2s@fc04c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s1_default>; - status = "disabled"; /* conflict with spi0, sdmmc1 */ - }; - - can1: can@fc050000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button { - label = "PB_USER"; - gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; /* conflict with pwm0 */ - - led-red { - label = "red"; - gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; - }; - - - led-green { - label = "green"; - gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; - }; - - led-blue { - label = "blue"; - gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/at91-sama5d3_eds.dts deleted file mode 100644 index c287b03d768b..000000000000 --- a/arch/arm/boot/dts/at91-sama5d3_eds.dts +++ /dev/null @@ -1,307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet - * Development System board. - * - * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries - * - * Author: Jerry Ray - */ -/dts-v1/; -#include "sama5d36.dtsi" - -/ { - model = "SAMA5D3 Ethernet Development System"; - compatible = "microchip,sama5d3-eds", "atmel,sama5d36", - "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - button-3 { - label = "PB_USER"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - memory@20000000 { - reg = <0x20000000 0x10000000>; - }; - - vcc_3v3_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_2v5_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "VCC_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - vin-supply = <&vcc_3v3_reg>; - }; - - vcc_1v8_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_3v3_reg>; - }; - - vcc_1v2_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_mmc0_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "mmc0-card-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; - gpio = <&pioE 2 GPIO_ACTIVE_LOW>; - }; -}; - -&can0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; -}; - -&i2c0 { - pinctrl-0 = <&pinctrl_i2c0_pu>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&pinctrl_i2c2_pu>; - status = "okay"; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&mmc0 { - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - board { - pinctrl_i2c0_pu: i2c0-pu { - atmel,pins = - , - ; - }; - - pinctrl_i2c2_pu: i2c2-pu { - atmel,pins = - , - ; - }; - - pinctrl_key_gpio: key-gpio-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_cd: mmc0-cd { - atmel,pins = - ; - }; - - /* Reserved for reset signal to the RGMII connector. */ - pinctrl_rgmii_rstn: rgmii-rstn { - atmel,pins = - ; - }; - - /* Reserved for an interrupt line from the RMII and RGMII connectors. */ - pinctrl_spi_irqn: spi-irqn { - atmel,pins = - ; - }; - - pinctrl_spi0_cs: spi0-cs-default { - atmel,pins = - ; - }; - - pinctrl_spi1_cs: spi1-cs-default { - atmel,pins = ; - }; - - pinctrl_usba_vbus: usba-vbus { - atmel,pins = - ; - }; - - pinctrl_usb_default: usb-default { - atmel,pins = - ; - }; - - /* Reserved for VBUS fault interrupt. */ - pinctrl_vbusfault_irqn: vbusfault-irqn { - atmel,pins = - ; - }; - - pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default { - atmel,pins = ; - }; - }; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&spi0 { - pinctrl-names = "default", "cs"; - pinctrl-1 = <&pinctrl_spi0_cs>; - cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default", "cs"; - pinctrl-1 = <&pinctrl_spi1_cs>; - cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>; - status = "okay"; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usb0 { /* USB Device port with VBUS detection. */ - atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; -}; - -&usb1 { /* 3-port Host. First port is unused. */ - atmel,vbus-gpio = <0 - &pioE 3 GPIO_ACTIVE_HIGH - &pioE 4 GPIO_ACTIVE_HIGH - >; - num-ports = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts deleted file mode 100644 index 14af1fd6d247..000000000000 --- a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 Oleksij Rempel , Pengutronix - */ -/dts-v1/; -#include "sama5d36.dtsi" - -/ { - model = "EVB-KSZ9477"; - compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", - "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = &dbgu; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vcc_mmc0: regulator-mmc0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcc0_vcc>; - regulator-name = "mmc0-vcc"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - gpio = <&pioE 2 GPIO_ACTIVE_LOW>; - }; -}; - -&dbgu { - status = "okay"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&pinctrl_i2c0_pu>; - status = "okay"; -}; - -&macb0 { - phy-mode = "rgmii"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&mmc0 { - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <8>; - cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_vcc_mmc0>; - vqmmc-supply = <®_3v3>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - }; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&spi0 { - cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, - <&pioD 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&spi1 { - pinctrl-0 = <&pinctrl_spi_ksz>; - cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - switch@0 { - compatible = "microchip,ksz9477"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - spi-cpol; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - phy-mode = "internal"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - phy-mode = "internal"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - phy-mode = "internal"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - phy-mode = "internal"; - }; - - port@4 { - reg = <4>; - label = "lan5"; - phy-mode = "internal"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&macb0>; - phy-mode = "rgmii-txid"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pinctrl { - board { - pinctrl_i2c0_pu: i2c0-pu { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_cd: mmc0-cd { - atmel,pins = ; - }; - - pinctrl_mcc0_vcc: mmc0-vcc { - atmel,pins = ; - }; - - pinctrl_spi_ksz: spi-ksz { - atmel,pins = - < - /* SPI1_MISO */ - AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - /* SPI1_MOSI */ - AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE - /* SPI1_SPCK */ - AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE - - /* SPI CS */ - AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE - /* switch IRQ */ - AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH - /* switch PME_N, SoC IN */ - AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP - /* switch RST */ - AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH - >; - }; - - pinctrl_usba_vbus: usba-vbus { - atmel,pins = - ; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts deleted file mode 100644 index 820033727088..000000000000 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - */ -/dts-v1/; -#include "sama5d36.dtsi" -#include - -/ { - model = "SAMA5D3 Xplained"; - compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; - }; - }; - - mmc1: mmc@f8000000 { - vmmc-supply = <&vcc_3v3_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "disabled"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; - }; - }; - - spi0: spi@f0004000 { - pinctrl-names = "default", "cs"; - pinctrl-1 = <&pinctrl_spi0_cs>; - cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - tcb0: timer@f0010000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - i2c0: i2c@f0014000 { - pinctrl-0 = <&pinctrl_i2c0_pu>; - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "disabled"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - }; - - macb0: ethernet@f0028000 { - phy-mode = "rgmii-rxid"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@7 { - reg = <0x7>; - }; - }; - - pwm0: pwm@f002c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; - status = "okay"; - }; - - usart0: serial@f001c000 { - status = "okay"; - }; - - usart1: serial@f0020000 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - uart0: serial@f0024000 { - status = "okay"; - }; - - mmc1: mmc@f8000000 { - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; - }; - }; - - spi1: spi@f8008000 { - pinctrl-names = "default", "cs"; - pinctrl-1 = <&pinctrl_spi1_cs>; - cs-gpios = <&pioC 25 0>; - status = "okay"; - }; - - adc0: adc@f8018000 { - atmel,adc-vref = <3300>; - atmel,adc-channels-used = <0xfe>; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7 - >; - status = "okay"; - }; - - i2c2: i2c@f801c000 { - dmas = <0>, <0>; /* Do not use DMA for i2c2 */ - pinctrl-0 = <&pinctrl_i2c2_pu>; - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - }; - }; - - dbgu: serial@ffffee00 { - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_i2c0_pu: i2c0_pu { - atmel,pins = - , - ; - }; - - pinctrl_i2c2_pu: i2c2_pu { - atmel,pins = - , - ; - }; - - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; /* PE9, conflicts with A9 */ - }; - pinctrl_usb_default: usb_default { - atmel,pins = - ; - }; - - pinctrl_gpio_leds: gpio_leds_default { - atmel,pins = - ; - }; - - pinctrl_spi0_cs: spi0_cs_default { - atmel,pins = - ; - }; - - pinctrl_spi1_cs: spi1_cs_default { - atmel,pins = ; - }; - - pinctrl_vcc_mmc0_reg_gpio: vcc_mmc0_reg_gpio_default { - atmel,pins = ; - }; - }; - }; - }; - - usb0: gadget@500000 { - atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@600000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 3 GPIO_ACTIVE_LOW - &pioE 4 GPIO_ACTIVE_LOW - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@700000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; - gpio = <&pioE 2 GPIO_ACTIVE_LOW>; - regulator-name = "mmc0-card-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - button { - label = "PB_USER"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - status = "okay"; - - led-d2 { - label = "d2"; - gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ - linux,default-trigger = "heartbeat"; - }; - - led-d3 { - label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */ - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi deleted file mode 100644 index fd1086f52b40..000000000000 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "sama5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4"; - compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - - memory@20000000 { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - - clk20m: clk20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - }; - - ahb { - apb { - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - broken-cd; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - - flash@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - - can1: can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; - regulator-name = "RST_n MCI0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-boot-on; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts deleted file mode 100644 index 8adf567f2f0f..000000000000 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015 Marek Vasut - */ - -/dts-v1/; -#include "at91-sama5d4_ma5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4EVK"; - compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - ahb { - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_LOW - &pioE 14 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@600000 { - status = "okay"; - }; - - apb { - hlcdc: hlcdc@f0000000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - usart0: serial@f802c000 { - status = "okay"; - }; - - usart1: serial@f8030000 { - status = "okay"; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - adc0: adc@fc034000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - }; - - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - led-user1 { - label = "user1"; - gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-user2 { - label = "user2"; - gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-user3 { - label = "user3"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - /* Actually Ampire 800480R2 */ - compatible = "foxlink,fl500wvr00-a0t"; - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 17 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts deleted file mode 100644 index 95d701d13fef..000000000000 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board - * - * Copyright (C) 2015 Atmel, - * 2015 Josh Wu - */ -/dts-v1/; -#include "sama5d4.dtsi" -#include - -/ { - model = "Atmel SAMA5D4 Xplained"; - compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - uart0: serial@f8004000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - i2c0: i2c@f8014000 { - i2c-digital-filter; - status = "okay"; - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; - - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - reg = <1>; - }; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 3 0>; - }; - }; - - usart3: serial@fc00c000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - usart4: serial@fc010000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - pinctrl-names = "default", "cs"; - pinctrl-1 = <&pinctrl_spi1_cs>; - cs-gpios = <&pioB 21 0>; - status = "okay"; - }; - - tcb2: timer@fc024000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - pinctrl_usb_default: usb_default { - atmel,pins = - ; - }; - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; - }; - pinctrl_macb0_phy_irq: macb0_phy_irq_0 { - atmel,pins = - ; - }; - pinctrl_spi1_cs: spi1_cs_default { - atmel,pins = - ; - }; - pinctrl_gpio_leds: gpio_leds_default { - atmel,pins = - ; - }; - pinctrl_vcc_mmc1_reg: vcc_mmc1_reg { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_HIGH - &pioE 14 GPIO_ACTIVE_HIGH - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@600000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe - &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy - &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - button { - label = "pb_user1"; - gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - status = "okay"; - - led-d8 { - label = "d8"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-d10 { - label = "d10"; - gpios = <&pioE 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_mmc1_reg>; - gpio = <&pioE 4 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-always-on; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts deleted file mode 100644 index 20ac775059ca..000000000000 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "Atmel SAMA5D4-EK"; - compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ - atmel,adc-vref = <3300>; - /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ - status = "okay"; /* Enable ADC IIO support */ - }; - - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - ssc0: ssc@f8008000 { - status = "okay"; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - flash@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pmc PMC_TYPE_SYSTEM 10>; - clock-names = "mclk"; - }; - - qt1070:keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioE>; - interrupts = <25 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - - touchscreen@4c { - compatible = "atmel,maxtouch"; - reg = <0x4c>; - interrupt-parent = <&pioE>; - interrupts = <24 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mxt_ts>; - }; - }; - - macb0: ethernet@f8020000 { - pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 6 0>; - }; - }; - - usart2: serial@fc008000 { - status = "okay"; - }; - - usart3: serial@fc00c000 { - status = "okay"; - }; - - usart4: serial@fc010000 { - status = "okay"; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_macb0_phy_irq: macb0_phy_irq { - atmel,pins = - ; - }; - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { - atmel,pins = - ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; /* PE13 gpio */ - }; - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - pinctrl_mxt_ts: mxt_irq { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ - &pioE 11 GPIO_ACTIVE_LOW - &pioE 12 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@600000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe - &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy - &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - button { - label = "pb_user1"; - gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - led-d8 { - label = "d8"; - /* PE28, conflicts with usart4 rts pin */ - gpios = <&pioE 28 GPIO_ACTIVE_LOW>; - }; - - led-d9 { - label = "d9"; - gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; - }; - - led-d10 { - label = "d10"; - gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D4EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN1L", "Line In Jack", - "IN1R", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; -}; diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts deleted file mode 100644 index aa5cc0e98bba..000000000000 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ /dev/null @@ -1,834 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries - * - * Author: Eugen Hristev - * Author: Claudiu Beznea - * - */ -/dts-v1/; -#include "sama7g5-pinfunc.h" -#include "sama7g5.dtsi" -#include -#include -#include -#include - -/ { - model = "Microchip SAMA7G5-EK"; - compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; - - chosen { - bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart3; - serial1 = &uart4; - serial2 = &uart7; - serial3 = &uart0; - i2c0 = &i2c1; - i2c1 = &i2c8; - i2c2 = &i2c9; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - button { - label = "PB_USER"; - gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; /* Conflict with pwm. */ - - red_led { - label = "red"; - gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; - }; - - green_led { - label = "green"; - gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; - }; - - blue_led { - label = "blue"; - gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* 512 M */ - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x20000000>; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sama7g5ek audio"; - #address-cells = <1>; - #size-cells = <0>; - simple-audio-card,dai-link@0 { - reg = <0>; - cpu { - sound-dai = <&spdiftx>; - }; - codec { - sound-dai = <&spdif_out>; - }; - }; - simple-audio-card,dai-link@1 { - reg = <1>; - cpu { - sound-dai = <&spdifrx>; - }; - codec { - sound-dai = <&spdif_in>; - }; - }; - }; - - spdif_in: spdif-in { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&adc { - vddana-supply = <&vddout25>; - vref-supply = <&vddout25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <133000000>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - m25p,fast-read; - - at91bootstrap@0 { - label = "ospi: at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "ospi: bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "ospi: bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "ospi: bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "ospi: device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "ospi: kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "ospi: rootfs"; - reg = <0x800000 0x7800000>; - }; - - }; -}; - -&dma0 { - status = "okay"; -}; - -&dma1 { - status = "okay"; -}; - -&dma2 { - status = "okay"; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart0: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - status = "disabled"; - }; -}; - -&flx1 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c1: i2c@600 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - mcp16502@5b { - compatible = "microchip,mcp16502"; - reg = <0x5b>; - status = "okay"; - - regulators { - vdd_3v3: VDD_IO { - regulator-name = "VDD_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vddioddr: VDD_DDR { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1350000>; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1350000>; - regulator-mode = <4>; - }; - }; - - vddcore: VDD_CORE { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-voltage = <1150000>; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vddcpu: VDD_OTHER { - regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1250000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-ramp-delay = <3125>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-voltage = <1050000>; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-standby { - regulator-suspend-voltage = <1800000>; - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - - regulator-state-standby { - regulator-suspend-voltage = <1800000>; - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - }; -}; - -&flx3 { - atmel,flexcom-mode = ; - status = "okay"; - - uart3: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - status = "okay"; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "okay"; - - uart4: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - status = "okay"; - }; -}; - -&flx7 { - atmel,flexcom-mode = ; - status = "okay"; - - uart7: serial@200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx7_default>; - status = "okay"; - }; -}; - -&flx8 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c8: i2c@600 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - }; -}; - -&flx9 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c9: i2c@600 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - }; -}; - -&flx11 { - atmel,flexcom-mode = ; - status = "okay"; - - spi11: spi@400 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; - status = "okay"; - }; -}; - -&gmac0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0_default - &pinctrl_gmac0_mdio_default - &pinctrl_gmac0_txck_default - &pinctrl_gmac0_phy_irq>; - phy-mode = "rgmii-id"; - status = "okay"; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioA>; - interrupts = ; - }; -}; - -&gmac1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac1_default - &pinctrl_gmac1_mdio_default - &pinctrl_gmac1_phy_irq>; - phy-mode = "rmii"; - status = "okay"; /* Conflict with pdmc0. */ - - ethernet-phy@0 { - reg = <0x0>; - interrupt-parent = <&pioA>; - interrupts = ; - }; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s0_default>; -}; - -&pdmc0 { - #sound-dai-cells = <0>; - microchip,mic-pos = , /* MIC 1 */ - , /* MIC 2 */ - , /* MIC 3 */ - ; /* MIC 4 */ - status = "disabled"; /* Conflict with gmac1. */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdmc0_default>; -}; - -&pioA { - - pinctrl_can0_default: can0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_can1_default: can1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx0_default: flx0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_flx3_default: flx3_default { - pinmux = , - ; - bias-pull-up; - }; - - pinctrl_flx4_default: flx4_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx7_default: flx7_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_gmac0_default: gmac0_default { - pinmux = , - , - , - , - , - , - , - , - , - , - , - ; - slew-rate = <0>; - bias-disable; - }; - - pinctrl_gmac0_mdio_default: gmac0_mdio_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_gmac0_txck_default: gmac0_txck_default { - pinmux = ; - slew-rate = <0>; - bias-pull-up; - }; - - pinctrl_gmac0_phy_irq: gmac0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_gmac1_default: gmac1_default { - pinmux = , - , - , - , - , - , - , - ; - slew-rate = <0>; - bias-disable; - }; - - pinctrl_gmac1_mdio_default: gmac1_mdio_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_gmac1_phy_irq: gmac1_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c8_default: i2c8_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c9_default: i2c9_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2s0_default: i2s0_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_mikrobus1_an_default: mikrobus1_an_default { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_an_default: mikrobus2_an_default { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_spi: mikrobus1_spi { - pinmux = , - , - ; - bias-disable; - }; - - pinctrl_pdmc0_default: pdmc0_default { - pinmux = , - , - ; - bias_disable; - }; - - pinctrl_qspi: qspi { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - ; - bias-disable; - slew-rate = <0>; - atmel,drive-strength = ; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <0>; - bias-pull-up; - }; - - ck_cd_rstn_vddsel { - pinmux = , - , - ; - slew-rate = <0>; - bias-pull-up; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - slew-rate = <0>; - bias-pull-up; - }; - - ck_cd_rstn_vddsel { - pinmux = , - , - , - ; - slew-rate = <0>; - bias-pull-up; - }; - }; - - pinctrl_sdmmc2_default: sdmmc2_default { - cmd_data { - pinmux = , - , - , - , - ; - slew-rate = <0>; - bias-pull-up; - }; - - ck { - pinmux = ; - slew-rate = <0>; - bias-pull-up; - }; - }; - - pinctrl_spdifrx_default: spdifrx_default { - pinmux = ; - bias-disable; - }; - - pinctrl_spdiftx_default: spdiftx_default { - pinmux = ; - bias-disable; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; - status = "disabled"; /* Conflict with leds. */ -}; - -&rtt { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; -}; - -&sdmmc0 { - bus-width = <8>; - non-removable; - sdhci-caps-mask = <0x0 0x00200000>; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&vldo1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; -}; - -&sdmmc1 { - bus-width = <4>; - no-1-8-v; - sdhci-caps-mask = <0x0 0x00200000>; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&vdd_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - status = "okay"; -}; - -&sdmmc2 { - bus-width = <4>; - no-1-8-v; - sdhci-caps-mask = <0x0 0x00200000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc2_default>; -}; - -&shdwc { - atmel,shdwc-debouncer = <976>; - status = "okay"; - - input@0 { - reg = <0>; - }; -}; - -&spdifrx { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdifrx_default>; - status = "okay"; -}; - -&spdiftx { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdiftx_default>; - status = "okay"; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&trng { - status = "okay"; -}; - -&vddout25 { - vin-supply = <&vdd_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/at91-smartkiz.dts deleted file mode 100644 index b76a6b5ac464..000000000000 --- a/arch/arm/boot/dts/at91-smartkiz.dts +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017-2018 Overkiz SAS - * Author: Mickael Gardet - * Kévin Raymond - * Dorian Rocipon - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz SmartKiz"; - compatible = "overkiz,smartkiz", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; - - clocks { - adc_op_clk { - status = "okay"; - }; - }; - - aliases { - serial5 = &uart0; - }; - - pio_keys { - hk_reset { - label = "HK_RESET"; - gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - }; - - power_rf { - label = "POWER_RF"; - gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; - }; - - power_wifi { - label = "POWER_WIFI"; - gpios = <&pioA 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; - }; - }; - - adc0 { - pinctrl_adc0_ad0: adc0_ad0-0 { - /* pull-up disable */ - atmel,pins = ; - }; - pinctrl_adc0_ad5: adc0_ad5-0 { - /* pull-up disable */ - atmel,pins = ; - }; - pinctrl_adc0_ad6: adc0_ad6-0 { - /* pull-up disable */ - atmel,pins = ; - }; - pinctrl_adc0_ad11: adc0_ad11-0 { - /* pull-up disable */ - atmel,pins = ; - }; - }; -}; - -&i2c1 { - dmas = <0>, <0>; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -&macb0 { - status = "disabled"; -}; - -&rtc { - status = "okay"; -}; - -&led_blue { - status = "okay"; -}; - -&adc0 { - atmel,adc-vref = <2500>; - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad11 - >; - atmel,adc-channels-used = <0x0861>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/at91-som60.dtsi deleted file mode 100644 index 39474a112b16..000000000000 --- a/arch/arm/boot/dts/at91-som60.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-som60.dtsi - Device Tree file for the SOM60 module - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ -#include "sama5d36.dtsi" - -/ { - model = "Laird SOM60"; - compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = &dbgu; - }; - - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; -}; - -&pinctrl { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc0_en: mmc0_en { - atmel,pins = - ; - }; - - pinctrl_nand0_wp: nand0_wp { - atmel,pins = - ; - }; - - pinctrl_usb_vbus: usb_vbus { - atmel,pins = - ; - /* Conflicts with USART2_SCK */ - }; - - pinctrl_usart2_sck: usart2_sck { - atmel,pins = - ; - /* Conflicts with USB_VBUS */ - }; - - pinctrl_usb_oc: usb_oc { - atmel,pins = - ; - /* Conflicts with USART3_SCK */ - }; - - pinctrl_usart3_sck: usart3_sck { - atmel,pins = - ; - /* Conflicts with USB_OC */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - - pinctrl_geth_int: geth_int { - atmel,pins = - ; - /* Conflicts with USART1_SCK */ - }; - - pinctrl_usart1_sck: usart1_sck { - atmel,pins = - ; - /* Conflicts with GETH_INT */ - }; - - pinctrl_eth_int: eth_int { - atmel,pins = - ; - }; - - pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { - atmel,pins = - ; - }; - }; -}; - -&mmc0 { - slot@0 { - reg = <0>; - bus-width = <8>; - }; -}; - -&mmc1 { - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&spi0 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; -}; - -&usart1 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; -}; - -&usart2 { - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>; -}; - -&usart3 { - pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; -}; - -&adc0 { - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - >; -}; - -&macb0 { - phy-mode = "rgmii"; -}; - -&macb1 { - phy-mode = "rmii"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand: nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ubootspl@0 { - label = "u-boot-spl"; - reg = <0x0 0x20000>; - }; - - uboot@20000 { - label = "u-boot"; - reg = <0x20000 0x80000>; - }; - - ubootenv@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - }; - - ubootenv@c0000 { - label = "u-boot-env"; - reg = <0xc0000 0x20000>; - }; - - ubi@e0000 { - label = "ubi"; - reg = <0xe0000 0xfe00000>; - }; - }; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>; - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 20 GPIO_ACTIVE_HIGH - 0>; - atmel,oc-gpio = <0 - &pioE 15 GPIO_ACTIVE_LOW - 0>; -}; diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts deleted file mode 100644 index 9d58a3931207..000000000000 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ /dev/null @@ -1,362 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ -/dts-v1/; -#include -#include "at91-linea.dtsi" - -/ { - model = "Axentia TSE-850 3.0"; - compatible = "axentia,tse850v3", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - sck: oscillator { - compatible = "fixed-clock"; - - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "sck"; - }; - - reg_3v3: regulator { - compatible = "regulator-fixed"; - - regulator-name = "3v3-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ana: reg-ana { - compatible = "pwm-regulator"; - - regulator-name = "ANA"; - - pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; - pwm-dutycycle-unit = <1000>; - pwm-dutycycle-range = <100 1000>; - - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <20000000>; - regulator-ramp-delay = <1000>; - }; - - sound { - compatible = "axentia,tse850-pcm5142"; - - axentia,cpu-dai = <&ssc0>; - axentia,audio-codec = <&pcm5142>; - - axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; - axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; - - axentia,ana-supply = <&ana>; - }; - - dac: dpot-dac { - compatible = "dpot-dac"; - vref-supply = <®_3v3>; - io-channels = <&dpot 0>; - io-channel-names = "dpot"; - #io-channel-cells = <1>; - }; - - env_det: envelope-detector { - compatible = "axentia,tse850-envelope-detector"; - io-channels = <&dac 0>; - io-channel-names = "dac"; - #io-channel-cells = <1>; - - interrupt-parent = <&pioA>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "comp"; - }; - - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>, - <&pioA 2 GPIO_ACTIVE_HIGH>; - idle-state = <0>; - }; - - envelope-detector-mux { - compatible = "io-channel-mux"; - io-channels = <&env_det 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "", "", - "sync-1", - "in", - "out", - "sync-2", - "sys-reg", - "ana-reg"; - }; - - leds { - compatible = "gpio-leds"; - - led-ch1-red { - label = "ch-1:red"; - gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - }; - led-ch1-green { - label = "ch-1:green"; - gpios = <&pioA 22 GPIO_ACTIVE_LOW>; - }; - led-ch2-red { - label = "ch-2:red"; - gpios = <&pioA 21 GPIO_ACTIVE_LOW>; - }; - led-ch2-green { - label = "ch-2:green"; - gpios = <&pioA 20 GPIO_ACTIVE_LOW>; - }; - led-data-red { - label = "data:red"; - gpios = <&pioA 19 GPIO_ACTIVE_LOW>; - }; - led-data-green { - label = "data:green"; - gpios = <&pioA 18 GPIO_ACTIVE_LOW>; - }; - led-alarm-red { - label = "alarm:red"; - gpios = <&pioA 17 GPIO_ACTIVE_LOW>; - }; - led-alarm-green { - label = "alarm:green"; - gpios = <&pioA 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - barebox@40000 { - label = "bootloader"; - reg = <0x40000 0x60000>; - }; - - bareboxenv@c0000 { - label = "bareboxenv"; - reg = <0xc0000 0x40000>; - }; - - bareboxenv2@100000 { - label = "bareboxenv2"; - reg = <0x100000 0x40000>; - }; - - oftree@180000 { - label = "oftree"; - reg = <0x180000 0x20000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - - ovlfs@10000000 { - label = "ovlfs"; - reg = <0x10000000 0x10000000>; - }; - }; -}; - -&ssc0 { - #sound-dai-cells = <0>; - - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - jc42@18 { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x18>; - smbus-timeout-disable; - }; - - dpot: mcp4651-104@28 { - compatible = "microchip,mcp4651-104"; - reg = <0x28>; - #io-channel-cells = <1>; - }; - - pcm5142: pcm5142@4c { - compatible = "ti,pcm5142"; - - reg = <0x4c>; - #sound-dai-cells = <0>; - - AVDD-supply = <®_3v3>; - DVDD-supply = <®_3v3>; - CPVDD-supply = <®_3v3>; - - clocks = <&sck>; - - pll-in = <3>; - pll-out = <6>; - }; - - eeprom@50 { - compatible = "nxp,se97b", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&pinctrl { - tse850 { - pinctrl_usba_vbus: usba-vbus { - atmel,pins = ; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&usart0 { - status = "okay"; - - atmel,use-dma-rx; -}; - -&pwm0 { - status = "okay"; - - pinctrl-0 = <&pinctrl_pwm0_pwml2_1>; - pinctrl-names = "default"; -}; - -&macb1 { - status = "okay"; - - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@3 { - reg = <3>; - - interrupt-parent = <&pioE>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&usb0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - atmel,vbus-gpio = <&pioC 31 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - status = "okay"; - - num-ports = <1>; - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - atmel,oc-gpio = <&pioC 15 GPIO_ACTIVE_LOW>; -}; - -&usb2 { - status = "okay"; -}; - -&dbgu { - status = "okay"; - - dmas = <0>, <0>; /* Do not use DMA for dbgu */ -}; - -&pioA { - gpio-line-names = - /* 0 */ "SUP-A", "SUP-B", "SUP-C", "SIGLIN", - /* 28 */ "RXD", "TXD", "BRX", "BTX"; -}; - -&pioC { - gpio-line-names = - /* 0 */ "ETX0", "ETX1", "ERX0", "ERX1", - /* 4 */ "ETXEN", "ECRSDV", "ERXER", "EREFCK", - /* 8 */ "EMDC", "EMDIO", "", "", - /* 12 */ "", "", "", "/ILIM", - /* 16 */ "BCK", "LRCK", "DIN", "", - /* 20 */ "", "", "", "", - /* 24 */ "", "", "", "", - /* 28 */ "", "", "", "VBUS"; -}; - -&pioD { - gpio-line-names = - /* 0 */ "I1", "I2", "O1", "EXTVEN", - /* 4 */ "", "456KHZ", "VCTRL", "SYNCSEL", - /* 8 */ "STEREO", "", "", "", - /* 12 */ "", "", "", "", - /* 16 */ "", ">LIN", "LIN>", "", - /* 20 */ "VREFEN", "", "", "", - /* 24 */ "", "", "VINOK", "", - /* 28 */ "POEOK", "USBON", "POELOAD", ""; -}; - -&pioE { - gpio-line-names = - /* 0 */ "", "", "", "", - /* 4 */ "", "", "", "", - /* 8 */ "", "", "", "", - /* 12 */ "", "", "", "", - /* 16 */ "", "", "", "", - /* 20 */ "", "ALE", "CLE", "", - /* 24 */ "", "", "", "", - /* 28 */ "", "", "", "/ETHINT"; -}; diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts deleted file mode 100644 index ebeaa6ab500e..000000000000 --- a/arch/arm/boot/dts/at91-vinco.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for VInCo platform - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - * 2015 Gregory CLEMENT - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "L+G VInCo platform"; - compatible = "l+g,vinco", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - - adc0: adc@fc034000 { - status = "okay"; /* Enable ADC IIO support */ - }; - - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 - &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_dat4_7>; - vqmmc-supply = <&vcc_3v3_reg>; - vmmc-supply = <&vcc_3v3_reg>; - no-1-8-v; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - non-removable; - broken-cd; - status = "okay"; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - flash@0 { - compatible = "n25q32b", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - i2c1: i2c@f8018000 { - status = "okay"; - /* kerkey security module */ - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - interrupt-parent = <&pioB>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - }; - - }; - - i2c2: i2c@f8024000 { - status = "okay"; - - rtc1: rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - }; - - usart2: serial@fc008000 { - /* MBUS */ - status = "okay"; - }; - - usart3: serial@fc00c000 { - /* debug */ - status = "okay"; - }; - - usart4: serial@fc010000 { - /* LMN */ - pinctrl-0 = <&pinctrl_usart4 &pinctrl_usart4_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - macb1: ethernet@fc028000 { - phy-mode = "rmii"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>; - }; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "disable"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_LOW - &pioE 12 GPIO_ACTIVE_LOW - >; - status = "disable"; - }; - - usb2: ehci@600000 { - /* 4G Modem */ - status = "okay"; - }; - - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - led_err { - label = "err"; - gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_rssi { - label = "rssi"; - gpios = <&pioA 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_tls { - label = "tls"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_lmc { - label = "lmc"; - gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_wmt { - label = "wmt"; - gpios = <&pioA 29 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_pwr { - label = "pwr"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts deleted file mode 100644 index ef73f727f7bd..000000000000 --- a/arch/arm/boot/dts/at91-wb45n.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb45n.dts - Device Tree file for WB45NBT board - * - * Copyright (C) 2018 Laird - * - */ -/dts-v1/; -#include "at91-wb45n.dtsi" - -/ { - model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; - compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; - - gpio-keys { - compatible = "gpio-keys"; - - button { - label = "IRQBTN"; - linux,code = <99>; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&mmc0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&macb0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&usart0 { - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi deleted file mode 100644 index 430c75358086..000000000000 --- a/arch/arm/boot/dts/at91-wb45n.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb45n.dtsi - Device Tree file for WB45NBT board - * - * Copyright (C) 2018 Laird - * - */ - -#include "at91sam9g25.dtsi" - -/ { - model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; - compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - atheros { - compatible = "atheros,ath6kl"; - atheros,board-id = "SD32"; - }; -}; - -&reset_controller { - compatible = "atmel,sama5d3-rstc"; -}; - -&shutdown_controller { - atmel,wakeup-mode = "low"; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&ebi { - status = "okay"; - nand_controller: nand-controller { - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>; - pinctrl-names = "default"; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bs"; - reg = <0x0 0x20000>; - }; - - uboot@20000 { - label = "u-boot"; - reg = <0x20000 0x80000>; - }; - - ubootenv@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - }; - - ubootenv@c0000 { - label = "redund-env"; - reg = <0xc0000 0x20000>; - }; - - kernel-a@e0000 { - label = "kernel-a"; - reg = <0xe0000 0x280000>; - }; - - kernel-b@360000 { - label = "kernel-b"; - reg = <0x360000 0x280000>; - }; - - rootfs-a@5e0000 { - label = "rootfs-a"; - reg = <0x5e0000 0x2600000>; - }; - - rootfs-b@2be0000 { - label = "rootfs-b"; - reg = <0x2be0000 0x2600000>; - }; - - user@51e0000 { - label = "user"; - reg = <0x51e0000 0x2dc0000>; - }; - - logs@7fa0000 { - label = "logs"; - reg = <0x7fa0000 0x60000>; - }; - - }; - }; - }; -}; - -&usb0 { - num-ports = <2>; - atmel,vbus-gpio = < - &pioB 12 GPIO_ACTIVE_HIGH - &pioA 31 GPIO_ACTIVE_HIGH - >; - atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; -}; - -&macb0 { - phy-mode = "rmii"; -}; - -&spi0 { - cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>; -}; - -&usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_board_usb2>; - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&pinctrl { - usb2 { - pinctrl_board_usb2: usb2-board { - atmel,pins = - ; /* PB11 gpio vbus sense, deglitch */ - }; - }; -}; - diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts deleted file mode 100644 index ec2becf6133b..000000000000 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb50n.dts - Device Tree file for wb50n evaluation board - * - * Copyright (C) 2018 Laird - * - */ - -/dts-v1/; -#include "at91-wb50n.dtsi" - -/ { - model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; - compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - gpio-keys { - compatible = "gpio-keys"; - - button-0 { - label = "BTNESC"; - linux,code = <1>; /* ESC button */ - gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-1 { - label = "IRQBTN"; - linux,code = <99>; /* SysReq button */ - gpios = <&pioE 31 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "wb50n:blue:led0"; - gpios = <&pioA 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "wb50n:green:led1"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "wb50n:red:led2"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&mmc0 { - status = "okay"; -}; - -&macb1 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -/* On BB40 this port is labeled UART1 */ -&usart0 { - status = "okay"; -}; - -/* On BB40 this port is labeled UART0 */ -&usart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi deleted file mode 100644 index 74b249bb6351..000000000000 --- a/arch/arm/boot/dts/at91-wb50n.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module - * - * Copyright (C) 2018 Laird - * - */ - -#include "sama5d31.dtsi" - -/ { - model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; - compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; -}; - -&pinctrl { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = ; /* PC26 GPIO with pullup deglitch */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = ; /* PB13 GPIO with deglitch */ - }; - }; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&clk32k { - atmel,osc-bypass; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>; - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "okay"; - atheros@0 { - compatible = "atheros,ath6kl"; - atheros,board-id = "SD32"; - reg = <0>; - bus-width = <4>; - }; -}; - -&macb1 { - phy-mode = "rmii"; -}; - -&dbgu { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ -}; - -/* On BB40 this port is labeled UART1 */ -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; -}; - -/* On BB40 this port is labeled UART0 */ -&usart1 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>; -}; - -/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */ -&usart3 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; - status = "okay"; -}; - -&spi1 { - cs-gpios = <&pioC 25 0>, <0>, <0>, <0>; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand: nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bs"; - reg = <0x0 0x20000>; - }; - - uboot@20000 { - label = "u-boot"; - reg = <0x20000 0x80000>; - }; - - ubootenv@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - }; - - ubootenv@c0000 { - label = "u-boot-env"; - reg = <0xc0000 0x20000>; - }; - - kernel-a@e0000 { - label = "kernel-a"; - reg = <0xe0000 0x500000>; - }; - - kernel-b@5e0000 { - label = "kernel-b"; - reg = <0x5e0000 0x500000>; - }; - - rootfs-a@ae0000 { - label = "rootfs-a"; - reg = <0xae0000 0x3000000>; - }; - - rootfs-b@3ae0000 { - label = "rootfs-b"; - reg = <0x3ae0000 0x3000000>; - }; - - user@6ae0000 { - label = "user"; - reg = <0x6ae0000 0x14e0000>; - }; - }; - }; -}; - -&usb0 { - atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>; - atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi deleted file mode 100644 index 37b500f6f395..000000000000 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ /dev/null @@ -1,729 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre , - * 2012 Joachim Eastwood - * - * Based on at91sam9260.dtsi - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91RM9200 family SoC"; - compatible = "atmel,at91rm9200"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - ssc2 = &ssc2; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm920t"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@200000 { - compatible = "mmio-sram"; - reg = <0x00200000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00200000 0x4000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <25 26 27 28 29 30 31>; - }; - - ramc0: ramc@ffffff00 { - compatible = "atmel,at91rm9200-sdramc", "syscon"; - reg = <0xffffff00 0x100>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - st: timer@fffffd00 { - compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; - reg = <0xfffffd00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - - watchdog { - compatible = "atmel,at91rm9200-wdt"; - }; - }; - - rtc: rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffa4000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa4000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 - 21 IRQ_TYPE_LEVEL_HIGH 0 - 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - i2c0: i2c@fffb8000 { - compatible = "atmel,at91rm9200-i2c"; - reg = <0xfffb8000 0x4000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_twi>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@fffb4000 { - compatible = "atmel,hsmci"; - reg = <0xfffb4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssc0: ssc@fffd0000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd0000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffd4000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd4000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc2: ssc@fffd8000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd8000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "pclk"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91rm9200-emac", "cdns,emac"; - reg = <0xfffbc000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "ether_clk"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffffffff /* pioA */ - 0xffffffff 0x083fffff /* pioB */ - 0xffff3fff 0x00000000 /* pioC */ - 0x03ff87ff 0x0fffff80 /* pioD */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - - pinctrl_uart0_cts: uart0_cts-0 { - atmel,pins = - ; /* PA20 periph A */ - }; - - pinctrl_uart0_rts: uart0_rts-0 { - atmel,pins = - ; /* PA21 periph A */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - - pinctrl_uart1_rts: uart1_rts-0 { - atmel,pins = - ; /* PB24 periph A */ - }; - - pinctrl_uart1_cts: uart1_cts-0 { - atmel,pins = - ; /* PB26 periph A */ - }; - - pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { - atmel,pins = - ; /* PB25 periph A */ - }; - - pinctrl_uart1_dcd: uart1_dcd-0 { - atmel,pins = - ; /* PB23 periph A */ - }; - - pinctrl_uart1_ri: uart1_ri-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - }; - - uart2 { - pinctrl_uart2: uart2-0 { - atmel,pins = - ; - }; - - pinctrl_uart2_rts: uart2_rts-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - - pinctrl_uart2_cts: uart2_cts-0 { - atmel,pins = - ; /* PA31 periph B */ - }; - }; - - uart3 { - pinctrl_uart3: uart3-0 { - atmel,pins = - ; - }; - - pinctrl_uart3_rts: uart3_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_uart3_cts: uart3_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PB1 gpio CD pin pull_up */ - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA16 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PB19 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA27 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA29 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PB5 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA9 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA12 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB2 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB5 periph A */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - }; - - ssc2 { - pinctrl_ssc2_tx: ssc2_tx-0 { - atmel,pins = - ; /* PB14 periph A */ - }; - - pinctrl_ssc2_rx: ssc2_rx-0 { - atmel,pins = - ; /* PB17 periph A */ - }; - }; - - twi { - pinctrl_twi: twi-0 { - atmel,pins = - ; /* PA26 periph A with multi drive */ - }; - - pinctrl_twi_gpio: twi_gpio-0 { - atmel,pins = - ; /* PA26 GPIO with multi drive */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph A SPI0_SPCK pin */ - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fffc0000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc0000 0x200>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffc4000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc4000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffc8000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc8000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffcc000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffcc000 0x200>; - atmel,usart-mode = ; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - status = "disabled"; - }; - - usb1: gadget@fffb0000 { - compatible = "atmel,at91rm9200-udc"; - reg = <0xfffb0000 0x4000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - spi0: spi@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffe0000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-ecc-mode = "soft"; - gpios = <&pioC 2 GPIO_ACTIVE_HIGH - 0 - &pioB 1 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - }; - - usb0: ohci@300000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00300000 0x100000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ - &pioA 26 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_twi_gpio>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91rm9200_pqfp.dtsi b/arch/arm/boot/dts/at91rm9200_pqfp.dtsi deleted file mode 100644 index c3d4177b9823..000000000000 --- a/arch/arm/boot/dts/at91rm9200_pqfp.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91rm9200.dtsi" - -/ { - compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200"; -}; - -&pioD { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts deleted file mode 100644 index 4624a6f076f8..000000000000 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit - * - * Copyright (C) 2012 Joachim Eastwood - */ -/dts-v1/; -#include "at91rm9200.dtsi" - -/ { - model = "Atmel AT91RM9200 evaluation kit"; - compatible = "atmel,at91rm9200ek", "atmel,at91rm9200"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; - atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy { - interrupt-parent = <&pioC>; - interrupts = <4 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - usart1: serial@fffc4000 { - pinctrl-0 = - <&pinctrl_uart1 - &pinctrl_uart1_rts - &pinctrl_uart1_cts - &pinctrl_uart1_dtr_dsr - &pinctrl_uart1_dcd - &pinctrl_uart1_ri>; - status = "okay"; - }; - - spi0: spi@fffe0000 { - status = "okay"; - cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - rtc: rtc@fffffe00 { - status = "okay"; - }; - }; - - usb0: ohci@300000 { - num-ports = <2>; - status = "okay"; - }; - - flash@10000000 { - compatible = "cfi-flash"; - reg = <0x10000000 0x800000>; - linux,mtd-name = "physmap-flash.0"; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - barebox@0 { - label = "barebox"; - reg = <0x00000 0x40000>; - }; - - bareboxenv@40000 { - label = "bareboxenv"; - reg = <0x40000 0x10000>; - }; - - kernel@50000 { - label = "kernel"; - reg = <0x50000 0x300000>; - }; - - root@350000 { - label = "root"; - reg = <0x350000 0x4B0000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds2 { - label = "green"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - ds4 { - label = "yellow"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - ds6 { - label = "red"; - gpios = <&pioB 2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi deleted file mode 100644 index 16e3b24b4ddd..000000000000 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ /dev/null @@ -1,796 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre , - * 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9260 family SoC"; - compatible = "atmel,at91sam9260"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - ssc0 = &ssc0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; - }; - }; - - sram0: sram@2ff000 { - compatible = "mmio-sram"; - reg = <0x002ff000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x002ff000 0x2000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <29 30 31>; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - smc: smc@ffffec00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffec00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9260-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9260-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - reset-controller@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffdc000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 - 27 IRQ_TYPE_LEVEL_HIGH 0 - 28 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - pinctrl: pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x600>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc00c3b /* pioA */ - 0xffffffff 0x7fff3ccf /* pioB */ - 0xffffffff 0x007fffff /* pioC */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PB26 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PB27 periph A */ - }; - - pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { - atmel,pins = - ; /* PB22 periph A */ - }; - - pinctrl_usart0_dcd: usart0_dcd-0 { - atmel,pins = - ; /* PB23 periph A */ - }; - - pinctrl_usart0_ri: usart0_ri-0 { - atmel,pins = - ; /* PB25 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PB28 periph A */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PB29 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PA4 periph A */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PA5 periph A */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA21 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - - pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA8 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA6 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA11 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA0 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA3 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB21 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB2 periph A SPI1_SPCK pin */ - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffd0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd0000 0x200>; - atmel,usart-mode = ; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; - status = "disabled"; - }; - - uart0: serial@fffd4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd4000 0x200>; - atmel,usart-mode = ; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@fffd8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd8000 0x200>; - atmel,usart-mode = ; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "usart"; - status = "disabled"; - }; - - macb0: ethernet@fffc4000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffc4000 0x100>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - usb1: gadget@fffa4000 { - compatible = "atmel,at91sam9260-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffac000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - mmc0: mmc@fffa8000 { - compatible = "atmel,hsmci"; - reg = <0xfffa8000 0x600>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi0: spi@fffc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffc8000 0x200>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - adc0: adc@fffe0000 { - compatible = "atmel,at91sam9260-adc"; - reg = <0xfffe0000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0xf>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <15>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - status = "disabled"; - }; - - watchdog: watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - gpbr: syscon@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; - status = "disabled"; - }; - }; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9260-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000 - 0x6 0x0 0x70000000 0x10000000 - 0x7 0x0 0x80000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9260-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c_gpio0: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ - &pioA 24 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts deleted file mode 100644 index bb72f050a4fe..000000000000 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Atmel at91sam9260 Evaluation Kit - * - * Copyright (C) 2016 Atmel, - * 2016 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include - -/ { - model = "Atmel at91sam9260ek"; - compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - stdout-path = &dbgu; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0_slot1 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - flash@1 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; - }; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-3 { - label = "Button 3"; - gpios = <&pioA 30 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - button-4 { - label = "Button 4"; - gpios = <&pioA 31 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi deleted file mode 100644 index fe9ead867e2a..000000000000 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ /dev/null @@ -1,667 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC - * - * Copyright (C) 2013 Jean-Jacques Hiblot - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9261 family SoC"; - compatible = "atmel,at91sam9261"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - ssc2 = &ssc2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x08000000>; - }; - - clocks { - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x28000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x28000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - fb0: fb@600000 { - compatible = "atmel,at91sam9261-lcdc"; - reg = <0x00600000 0x1000>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>; - clock-names = "lcdc_clk", "hclk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9261-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000 - 0x6 0x0 0x70000000 0x10000000 - 0x7 0x0 0x80000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9261-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, - <18 IRQ_TYPE_LEVEL_HIGH 0>, - <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - usb1: gadget@fffa4000 { - compatible = "atmel,at91sam9261-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - atmel,matrix = <&matrix>; - status = "disabled"; - }; - - mmc0: mmc@fffa8000 { - compatible = "atmel,hsmci"; - reg = <0xfffa8000 0x600>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9261-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_twi>; - reg = <0xfffac000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000{ - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffc0000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffc0000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc2: ssc@fffc4000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffc4000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi0: spi@fffc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffc8000 0x200>; - cs-gpios = <0>, <0>, <0>, <0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ramc: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - smc: smc@ffffec00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffec00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9261-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <29 30 31>; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x600>; - - atmel,mux-mask = - /* A B */ - <0xffffffff 0xfffffff7>, /* pioA */ - <0xffffffff 0xfffffff4>, /* pioB */ - <0xffffffff 0xffffff07>; /* pioC */ - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc2 { - pinctrl_ssc2_tx: ssc2_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc2_rx: ssc2_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - , - , - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - i2c0 { - pinctrl_i2c_bitbang: i2c-0-bitbang { - atmel,pins = - , - ; - }; - pinctrl_i2c_twi: i2c-0-twi { - atmel,pins = - , - ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9261-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - reset-controller@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&slow_xtal>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&slow_xtal>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - gpbr: syscon@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_bitbang>; - gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts deleted file mode 100644 index 88869ca874d1..000000000000 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board - * - * Copyright (C) 2013 Jean-Jacques Hiblot - */ -/dts-v1/; -#include "at91sam9261.dtsi" - -/ { - model = "Atmel at91sam9261ek"; - compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; - - chosen { - bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - usb0: ohci@500000 { - status = "okay"; - }; - - fb0: fb@600000 { - display = <&display0>; - atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - display0: panel { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - atmel,lcd-wiring-mode = "BRG"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - - apb { - tcb0: timer@fffa0000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer1: timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffc8000 { - cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; - status = "okay"; - - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <0>; - spi-max-frequency = <15000000>; - }; - - tsc2046@2 { - reg = <2>; - compatible = "ti,ads7843"; - interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; - spi-max-frequency = <3000000>; - pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <150>; - ti,x-max = /bits/ 16 <3830>; - ti,y-min = /bits/ 16 <190>; - ti,y-max = /bits/ 16 <3830>; - ti,vref-delay-usecs = /bits/ 16 <450>; - ti,x-plate-ohms = /bits/ 16 <450>; - ti,y-plate-ohms = /bits/ 16 <250>; - ti,pressure-max = /bits/ 16 <15000>; - ti,debounce-rep = /bits/ 16 <0>; - ti,debounce-tol = /bits/ 16 <65535>; - ti,debounce-max = /bits/ 16 <1>; - - wakeup-source; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - }; - }; - - leds { - compatible = "gpio-leds"; - - ds8 { - label = "ds8"; - gpios = <&pioA 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - ds7 { - label = "ds7"; - gpios = <&pioA 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - ds1 { - label = "ds1"; - gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-0 { - label = "button_0"; - gpios = <&pioA 27 GPIO_ACTIVE_LOW>; - linux,code = <256>; - wakeup-source; - }; - - button-1 { - label = "button_1"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <257>; - wakeup-source; - }; - - button-2 { - label = "button_2"; - gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - linux,code = <258>; - wakeup-source; - }; - - button-3 { - label = "button_3"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - linux,code = <259>; - wakeup-source; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi deleted file mode 100644 index ee5e6ed44dd4..000000000000 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ /dev/null @@ -1,839 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9263 family SoC"; - compatible = "atmel,at91sam9263"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x08000000>; - }; - - clocks { - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram0: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x14000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x14000>; - }; - - sram1: sram@500000 { - compatible = "mmio-sram"; - reg = <0x00500000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00500000 0x4000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <30 31>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9263-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - ramc0: ramc@ffffe200 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe200 0x200>; - }; - - smc0: smc@ffffe400 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffe400 0x200>; - }; - - ramc1: ramc@ffffe800 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe800 0x200>; - }; - - smc1: smc@ffffea00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x200>; - }; - - matrix: matrix@ffffec00 { - compatible = "atmel,at91sam9263-matrix", "syscon"; - reg = <0xffffec00 0x200>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; - clock-names = "t0_clk", "slow_clk"; - }; - - reset-controller@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&slow_xtal>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&slow_xtal>; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - - atmel,mux-mask = < - /* A B */ - 0xfffffffb 0xffffe07f /* pioA */ - 0x0007ffff 0x39072fff /* pioB */ - 0xffffffff 0x3ffffff8 /* pioC */ - 0xfffffbff 0xffffffff /* pioD */ - 0xffe00fff 0xfbfcff00 /* pioE */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA28 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA29 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PD7 periph B */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PD8 periph B */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PD5 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PD6 periph B */ - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PE30 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PE22 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA12 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA0 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA5 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA17 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_clk: mmc1_clk-0 { - atmel,pins = - ; /* PA6 periph A */ - }; - - pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA8 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA11 periph A with pullup */ - }; - - pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA22 periph A with pullup */ - }; - - pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { - atmel,pins = - ; /* PA25 periph A with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB2 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB5 periph B */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph B SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB14 periph A SPI1_SPCK pin */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - ; /* PC27 periph A */ - }; - }; - - can { - pinctrl_can_rx_tx: can_rx_tx { - atmel,pins = - ; /* CANTX, conflicts with PCK0 */ - }; - }; - - ac97 { - pinctrl_ac97: ac97-0 { - atmel,pins = - ; /* PB14 periph A AC97RX pin */ - }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fff90000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff90000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fff94000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff94000 0x200>; - atmel,usart-mode = ; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fff98000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfff98000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fff9c000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfff9c000 0x4000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; - clock-names = "pclk"; - status = "disabled"; - }; - - ac97: sound@fffa0000 { - compatible = "atmel,at91sam9263-ac97c"; - reg = <0xfffa0000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ac97>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - clock-names = "ac97_clk"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffbc000 0x100>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - usb1: gadget@fff78000 { - compatible = "atmel,at91sam9263-udc"; - reg = <0xfff78000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - i2c0: i2c@fff88000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfff88000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - status = "disabled"; - }; - - mmc0: mmc@fff80000 { - compatible = "atmel,hsmci"; - reg = <0xfff80000 0x600>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - mmc1: mmc@fff84000 { - compatible = "atmel,hsmci"; - reg = <0xfff84000 0x600>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - spi0: spi@fffa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa4000 0x200>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa8000 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - pwm0: pwm@fffb8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffb8000 0x300>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "pwm_clk"; - status = "disabled"; - }; - - can: can@fffac000 { - compatible = "atmel,at91sam9263-can"; - reg = <0xfffac000 0x300>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "can_clk"; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - rtc@fffffd50 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd50 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x50>; - status = "disabled"; - }; - }; - - fb0: fb@700000 { - compatible = "atmel,at91sam9263-lcdc"; - reg = <0x00700000 0x1000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "lcdc_clk", "hclk"; - status = "disabled"; - }; - - usb0: ohci@a00000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00a00000 0x100000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - ebi0: ebi@10000000 { - compatible = "atmel,at91sam9263-ebi0"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc0>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller0: nand-controller { - compatible = "atmel,at91sam9260-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - ebi1: ebi@70000000 { - compatible = "atmel,at91sam9263-ebi1"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc1>; - atmel,matrix = <&matrix>; - reg = <0x80000000 0x20000000>; - ranges = <0x0 0x0 0x80000000 0x10000000 - 0x1 0x0 0x90000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller1: nand-controller { - compatible = "atmel,at91sam9260-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts deleted file mode 100644 index ce8baff6a9f4..000000000000 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Atmel at91sam9263ek"; - compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16367660>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fff8c000 { - pinctrl-0 = < - &pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff200 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PE19 gpio WP pin pull up */ - }; - }; - }; - - spi0: spi@fffa4000 { - status = "okay"; - cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - fb0: fb@700000 { - display = <&display0>; - status = "okay"; - - display0: panel { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - ebi0: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@a00000 { - num-ports = <2>; - status = "okay"; - atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH - &pioA 21 GPIO_ACTIVE_HIGH - >; - }; - }; - - leds { - compatible = "gpio-leds"; - - d3 { - label = "d3"; - gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - d2 { - label = "d2"; - gpios = <&pioC 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-left-click { - label = "left_click"; - gpios = <&pioC 5 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - - button-right-click { - label = "right_click"; - gpios = <&pioC 4 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - pagesize = <128>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi deleted file mode 100644 index dde88276fe52..000000000000 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" - -/ { - model = "Atmel AT91SAM9G15 SoC"; - compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; -}; - -&pinctrl { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0x00000000 /* pioA */ - 0x00040000 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; -}; - -&pmc { - compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon"; -}; diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts deleted file mode 100644 index 889a5097eb2d..000000000000 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g15.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G15-EK"; - compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; - -&hlcdc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi deleted file mode 100644 index 738a43ffd228..000000000000 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9G20 family SoC"; - compatible = "atmel,at91sam9g20"; - - memory@20000000 { - reg = <0x20000000 0x08000000>; - }; - - sram0: sram@2ff000 { - status = "disabled"; - }; - - sram1: sram@2fc000 { - compatible = "mmio-sram"; - reg = <0x002fc000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x002fc000 0x8000>; - }; - - ahb { - apb { - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9g20-i2c"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91sam9rl-ssc"; - }; - - adc0: adc@fffe0000 { - atmel,adc-startup-time = <40>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts deleted file mode 100644 index 6de7a7cd3c07..000000000000 --- a/arch/arm/boot/dts/at91sam9g20ek.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g20ek_common.dtsi" - -/ { - model = "Atmel at91sam9g20ek"; - compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts deleted file mode 100644 index 2db95e8ffc64..000000000000 --- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g20ek_common.dtsi" - -/ { - model = "Atmel at91sam9g20ek 2 mmc"; - compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; - - ahb { - apb{ - mmc0: mmc@fffa8000 { - /* clk already mux wuth slot0 */ - pinctrl-0 = < - &pinctrl_board_mmc0_slot0 - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff400 { - mmc0_slot0 { - pinctrl_board_mmc0_slot0: mmc0_slot0-board { - atmel,pins = - ; /* PC2 gpio CD pin pull up and deglitch */ - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioB 8 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi deleted file mode 100644 index 024af2db638e..000000000000 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -#include "at91sam9g20.dtsi" -#include - -/ { - - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - ; /* PC1 periph B */ - }; - - }; - - usb1 { - pinctrl_usb1_vbus_gpio: usb1_vbus_gpio { - atmel,pins = - ; /* PC5 GPIO */ - }; - }; - - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; /* PC9 gpio CD pin pull up and deglitch */ - }; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - pinctrl-0 = <&pinctrl_usb1_vbus_gpio>; - pinctrl-names = "default"; - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0_slot1 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; - }; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - flash@1 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - vcc-supply = <®_3v3>; - }; - - wm8731: wm8731@1b { - compatible = "wm8731"; - reg = <0x1b>; - - /* PCK0 at 12MHz */ - clocks = <&pmc PMC_TYPE_SYSTEM 8>; - clock-names = "mclk"; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; - assigned-clock-rates = <12000000>; - - HPVDD-supply = <&vcc_dac>; - AVDD-supply = <&vcc_dac>; - DCVDD-supply = <®_3v3>; - DBVDD-supply = <®_3v3>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-3 { - label = "Button 3"; - gpios = <&pioA 30 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - button-4 { - label = "Button 4"; - gpios = <&pioA 31 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "atmel,at91sam9g20ek-wm8731-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8731 @ AT91SAMG20EK"; - - atmel,audio-routing = - "Ext Spk", "LHPOUT", - "Int Mic", "MICIN"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; - }; - - reg_5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - vin-supply = <®_5v>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_1v: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "1V"; - vin-supply = <®_5v>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vcc_dac: fixedregulator3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_DAC"; - vin-supply = <®_3v3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts deleted file mode 100644 index 92f2c05c873f..000000000000 --- a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the GARDENA smart Gateway (Article No. 19000) - * - * Copyright (C) 2020 GARDENA GmbH - */ - -/dts-v1/; - -#include "at91sam9g25.dtsi" -#include "at91sam9x5ek.dtsi" -#include - -/ { - model = "GARDENA smart Gateway (Article No. 19000)"; - compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9g25", "atmel,at91sam9x5", - "atmel,at91sam9"; - - aliases { - serial1 = &usart3; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button { - label = "USER_BTN1"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - 1wire_cm { - status = "disabled"; - }; - - leds { - compatible = "gpio-leds"; - - power_blue { - label = "smartgw:power:blue"; - gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - power_green { - label = "smartgw:power:green"; - gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - power_red { - label = "smartgw:power:red"; - gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - radio_blue { - label = "smartgw:radio:blue"; - gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - radio_green { - label = "smartgw:radio:green"; - gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - radio_red { - label = "smartgw:radio:red"; - gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - internet_blue { - label = "smartgw:internet:blue"; - gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - internet_green { - label = "smartgw:internet:green"; - gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - internet_red { - label = "smartgw:internet:red"; - gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat { - label = "smartgw:heartbeat"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - pb18 { - status = "disabled"; - }; - - pd21 { - status = "disabled"; - }; - }; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&usart0 { - status = "disabled"; -}; - -&usart2 { - status = "disabled"; -}; - -&usart3 { - status = "okay"; - - pinctrl-0 = <&pinctrl_usart3 - &pinctrl_usart3_rts - &pinctrl_usart3_cts - >; -}; - -&watchdog { - status = "okay"; -}; - -&mmc0 { - status = "disabled"; -}; - -&mmc1 { - status = "disabled"; -}; - -&spi0 { - status = "disabled"; -}; - -&i2c0 { - status = "disabled"; -}; - -&adc0 { - status = "disabled"; -}; - -&ssc0 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi deleted file mode 100644 index ec3c77221881..000000000000 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_isi.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" - -/ { - model = "Atmel AT91SAM9G25 SoC"; - compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0xc000001c /* pioA */ - 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ - 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts deleted file mode 100644 index 61b0bdb615dc..000000000000 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g25.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G25-EK"; - compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&i2c0 { - camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; - clocks = <&pmc PMC_TYPE_SYSTEM 8>; - clock-names = "xvclk"; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; - assigned-clock-rates = <25000000>; - status = "okay"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; -}; - -&isi { - status = "okay"; - - port { - isi_0: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&mmc1 { - status = "disabled"; -}; - -&spi0 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi deleted file mode 100644 index c9cfb93092ee..000000000000 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" -#include "at91sam9x5_macb0.dtsi" - -/ { - model = "Atmel AT91SAM9G35 SoC"; - compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0xc000000c /* pioA */ - 0x000406ff 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts deleted file mode 100644 index f966b56de63c..000000000000 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g35.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G35-EK"; - compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; - -&hlcdc { - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi deleted file mode 100644 index 498cb92b29f9..000000000000 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ /dev/null @@ -1,1023 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC - * applies to AT91SAM9G45, AT91SAM9M10, - * AT91SAM9G46, AT91SAM9M11 SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9G45 family SoC"; - compatible = "atmel,at91sam9g45"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - ramc0: ramc@ffffe400 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe400 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>; - clock-names = "ddrck"; - }; - - ramc1: ramc@ffffe600 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe600 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>; - clock-names = "ddrck"; - }; - - smc: smc@ffffe800 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffe800 0x200>; - }; - - matrix: matrix@ffffea00 { - compatible = "atmel,at91sam9g45-matrix", "syscon"; - reg = <0xffffea00 0x200>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9g45-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - reset-controller@fffffd00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - - shdwc@fffffd10 { - compatible = "atmel,at91sam9rl-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffd4000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffd4000 0x100>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc003ff /* pioA */ - 0xffffffff 0x800f8f00 /* pioB */ - 0xffffffff 0x00000e00 /* pioC */ - 0xffffffff 0xff0c1381 /* pioD */ - 0xffffffff 0x81ffff81 /* pioE */ - >; - - /* shared pinctrl settings */ - ac97 { - pinctrl_ac97: ac97-0 { - atmel,pins = - ; /* AC97CK */ - }; - }; - - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = ; - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = ; - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = ; - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = ; - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = ; - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = ; - }; - pinctrl_adc0_ad5: adc0_ad5 { - atmel,pins = ; - }; - pinctrl_adc0_ad6: adc0_ad6 { - atmel,pins = ; - }; - pinctrl_adc0_ad7: adc0_ad7 { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA20 periph A TWD0 */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PB10 periph A TWD1 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* HSYNC */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* D9 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* D11 */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PB17 periph B */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PB15 periph B */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PD16 periph A */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PD17 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PC9 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PC11 periph B */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PA23 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PA24 periph B */ - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA19 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA2 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA5 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { - atmel,pins = - ; /* PA9 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA23 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA26 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { - atmel,pins = - ; /* PA30 periph A with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PD2 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PD5 periph A */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PD12 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PD15 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PB2 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB16 periph A SPI1_SPCK pin */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - ; /* PE30 periph A */ - }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - atmel,usart-mode = ; - reg = <0xffffee00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fff90000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff90000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fff94000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff94000 0x200>; - atmel,usart-mode = ; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fff98000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff98000 0x200>; - atmel,usart-mode = ; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "usart"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffbc000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - trng@fffcc000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfffcc000 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - }; - - i2c0: i2c@fff84000 { - compatible = "atmel,at91sam9g10-i2c"; - reg = <0xfff84000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - status = "disabled"; - }; - - i2c1: i2c@fff88000 { - compatible = "atmel,at91sam9g10-i2c"; - reg = <0xfff88000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - status = "disabled"; - }; - - ssc0: ssc@fff9c000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfff9c000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffa0000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfffa0000 0x4000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; - clock-names = "pclk"; - status = "disabled"; - }; - - ac97: sound@fffac000 { - compatible = "atmel,at91sam9263-ac97c"; - reg = <0xfffac000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ac97>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "ac97_clk"; - status = "disabled"; - }; - - adc0: adc@fffb0000 { - compatible = "atmel,at91sam9g45-adc"; - reg = <0xfffb0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xff>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - }; - - isi@fffb4000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xfffb4000 0x4000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pwm0: pwm@fffb8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffb8000 0x300>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - status = "disabled"; - }; - - mmc0: mmc@fff80000 { - compatible = "atmel,hsmci"; - reg = <0xfff80000 0x600>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - mmc1: mmc@fffd0000 { - compatible = "atmel,hsmci"; - reg = <0xfffd0000 0x600>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; - dma-names = "rxtx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - spi0: spi@fffa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa4000 0x200>; - interrupts = <14 4 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa8000 0x200>; - interrupts = <15 4 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - usb2: gadget@fff78000 { - compatible = "atmel,at91sam9g45-udc"; - reg = <0x00600000 0x80000 - 0xfff78000 0x400>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - clk32k: clock-controller@fffffd50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffd50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - rtc@fffffdb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffdb0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x10>; - status = "disabled"; - }; - }; - - fb0: fb@500000 { - compatible = "atmel,at91sam9g45-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "hclk", "lcdc_clk"; - status = "disabled"; - }; - - usb0: ohci@700000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb1: ehci@800000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00800000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9g45-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ - &pioA 21 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <5>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts deleted file mode 100644 index 7f45e81ca165..000000000000 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ /dev/null @@ -1,393 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g45.dtsi" -#include - -/ { - model = "Atmel AT91SAM9M10G45-EK"; - compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; - stdout-path = "serial0:115200n8"; - }; - - memory@70000000 { - reg = <0x70000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart1: serial@fff90000 { - pinctrl-0 = - <&pinctrl_usart1 - &pinctrl_usart1_rts - &pinctrl_usart1_cts>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - i2c0: i2c@fff84000 { - status = "okay"; - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; - clocks = <&pmc PMC_TYPE_SYSTEM 9>; - clock-names = "xvclk"; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - i2c1: i2c@fff88000 { - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc1: mmc@fffd0000 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff200 { - camera_sensor { - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - }; - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD10 gpio CD pin pull up and deglitch */ - }; - }; - - mmc1 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - ; /* PD29 gpio WP pin pull up */ - }; - }; - - pwm0 { - pinctrl_pwm_leds: pwm-led { - atmel,pins = - ; /* PD31 periph B */ - }; - }; - }; - - spi0: spi@fffa4000{ - status = "okay"; - cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <13000000>; - reg = <0>; - }; - }; - - usb2: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - ac97: sound@fffac000 { - status = "okay"; - }; - - adc0: adc@fffb0000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7>; - atmel,adc-ts-wires = <4>; - status = "okay"; - }; - - isi@fffb4000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - status = "okay"; - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - pwm0: pwm@fffb8000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_leds>; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - gpbr: syscon@fffffd60 { - status = "okay"; - }; - - rtc@fffffdb0 { - status = "okay"; - }; - }; - - fb0: fb@500000 { - display = <&display0>; - status = "okay"; - - display0: panel { - bits-per-pixel = <32>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <9>; - atmel,lcd-wiring-mode = "RGB"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <1>; - hfront-porch = <1>; - vback-porch = <40>; - vfront-porch = <1>; - hsync-len = <45>; - vsync-len = <1>; - }; - }; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "bootstrap/uboot/kernel"; - reg = <0x0 0x400000>; - }; - - rootfs@400000 { - label = "rootfs"; - reg = <0x400000 0x3C00000>; - }; - - data@4000000 { - label = "data"; - reg = <0x4000000 0xC000000>; - }; - }; - }; - }; - }; - - usb0: ohci@700000 { - status = "okay"; - num-ports = <2>; - atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW - &pioD 3 GPIO_ACTIVE_LOW>; - }; - - usb1: ehci@800000 { - status = "okay"; - }; - }; - - led-controller-1 { - compatible = "gpio-leds"; - - led-1 { - label = "d8"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-controller-2 { - compatible = "pwm-leds"; - - led-2 { - label = "d6"; - pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "nand-disk"; - }; - - led-3 { - label = "d7"; - pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "mmc0"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-left-click { - label = "left_click"; - gpios = <&pioB 6 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - - button-right-click { - label = "right_click"; - gpios = <&pioB 7 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - - button-left { - label = "Joystick Left"; - gpios = <&pioB 14 GPIO_ACTIVE_LOW>; - linux,code = <105>; - }; - - button-right { - label = "Joystick Right"; - gpios = <&pioB 15 GPIO_ACTIVE_LOW>; - linux,code = <106>; - }; - - button-up { - label = "Joystick Up"; - gpios = <&pioB 16 GPIO_ACTIVE_LOW>; - linux,code = <103>; - }; - - button-down { - label = "Joystick Down"; - gpios = <&pioB 17 GPIO_ACTIVE_LOW>; - linux,code = <108>; - }; - - button-enter { - label = "Joystick Press"; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - linux,code = <28>; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi deleted file mode 100644 index 0e28101b26bf..000000000000 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ /dev/null @@ -1,799 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Hong Xu - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9N12 SoC"; - compatible = "atmel,at91sam9n12"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x8000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - matrix: matrix@ffffde00 { - compatible = "atmel,at91sam9n12-matrix", "syscon"; - reg = <0xffffde00 0x100>; - }; - - pmecc: ecc-engine@ffffe000 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffe000 0x600>, - <0xffffe600 0x200>; - }; - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>; - clock-names = "ddrck"; - }; - - smc: smc@ffffea00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x200>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9n12-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - }; - - reset-controller@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - shdwc@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - clk32k: clock-controller@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - hlcdc: hlcdc@f8038000 { - compatible = "atmel,at91sam9n12-hlcdc"; - reg = <0xf8038000 0x2000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk", "sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe07983 0x00000000 /* pioA */ - 0x00040000 0x00047e0f 0x00000000 /* pioB */ - 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PA0 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA2 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA3 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PA5 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PA7 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PC22 periph B */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PC25 periph B */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC8 periph C */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA15 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { - atmel,pins = - ; /* PA14 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PA26 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA13 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PA23 periph B SPI1_SPCK pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, - <&dma 0 AT91_DMA_CFG_PER_ID(22)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "pclk"; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x4000>; - atmel,usart-mode = ; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x4000>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x4000>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x4000>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, - <&dma 1 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - status = "disabled"; - }; - - i2c1: i2c@f8014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8014000 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, - <&dma 1 AT91_DMA_CFG_PER_ID(16)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - status = "disabled"; - }; - - spi0: spi@f0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0000000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, - <&dma 1 AT91_DMA_CFG_PER_ID(4)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - status = "disabled"; - }; - - usb1: gadget@f803c000 { - compatible = "atmel,at91sam9260-udc"; - reg = <0xf803c000 0x4000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - }; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x00100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9x5-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x60000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts deleted file mode 100644 index 4c644d4c6be7..000000000000 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Hong Xu - */ -/dts-v1/; -#include "at91sam9n12.dtsi" - -/ { - model = "Atmel AT91SAM9N12-EK"; - compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; - - chosen { - bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - ssc0: ssc@f0010000 { - status = "okay"; - }; - - tcb0: timer@f8008000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - i2c0: i2c@f8010000 { - status = "okay"; - - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pmc PMC_TYPE_SYSTEM 8>; - clock-names = "mclk"; - }; - - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioA>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - }; - }; - - mmc0: mmc@f0008000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PA7 gpio CD pin pull up and deglitch */ - }; - }; - - qt1070 { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - }; - - sound { - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; - }; - }; - - usb1 { - pinctrl_usb1_vbus_sense: usb1_vbus_sense { - atmel,pins = - ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ - }; - }; - }; - - spi0: spi@f0000000 { - status = "okay"; - cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - flash@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - hlcdc: hlcdc@f8038000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - usb1: gadget@f803c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus_sense>; - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-ecc-strength = <2>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <1>; - atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <&bl_reg>; - status = "okay"; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - d8 { - label = "d8"; - gpios = <&pioB 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - d9 { - label = "d9"; - gpios = <&pioB 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - d10 { - label = "d10"; - gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-enter { - label = "Enter"; - gpios = <&pioB 3 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "qiaodian,qd43003c0-40"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "okay"; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi deleted file mode 100644 index d7e8a115c916..000000000000 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ /dev/null @@ -1,861 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC - * - * Copyright (C) 2014 Microchip - * Alexandre Belloni - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9RL family SoC"; - compatible = "atmel,at91sam9rl", "atmel,at91sam9"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fb0: fb@500000 { - compatible = "atmel,at91sam9rl-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "hclk", "lcdc_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9rl-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, - <17 IRQ_TYPE_LEVEL_HIGH 0>, - <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - mmc0: mmc@fffa4000 { - compatible = "atmel,hsmci"; - reg = <0xfffa4000 0x600>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - i2c0: i2c@fffa8000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffa8000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - i2c1: i2c@fffac000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffac000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffbc000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffbc000 0x200>; - atmel,usart-mode = ; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fffc0000 { - compatible = "atmel,at91sam9rl-ssc"; - reg = <0xfffc0000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - status = "disabled"; - }; - - ssc1: ssc@fffc4000 { - compatible = "atmel,at91sam9rl-ssc"; - reg = <0xfffc4000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - status = "disabled"; - }; - - pwm0: pwm@fffc8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffc8000 0x300>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "pwm_clk"; - status = "disabled"; - }; - - spi0: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - adc0: adc@fffd0000 { - compatible = "atmel,at91sam9rl-adc"; - reg = <0xfffd0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0x3f>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - }; - - usb0: gadget@fffd4000 { - compatible = "atmel,at91sam9rl-udc"; - reg = <0x00600000 0x100000>, - <0xfffd4000 0x4000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - dma0: dma-controller@ffffe600 { - compatible = "atmel,at91sam9rl-dma"; - reg = <0xffffe600 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "dma_clk"; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - smc: smc@ffffec00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffec00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9rl-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = - /* A B */ - <0xffffffff 0xe05c6738>, /* pioA */ - <0xffffffff 0x0000c780>, /* pioB */ - <0xffffffff 0xe3ffff0e>, /* pioC */ - <0x003fffff 0x0001ff3c>; /* pioD */ - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_ts: adc0_ts-0 { - atmel,pins = - , - , - , - ; - }; - - pinctrl_adc0_ad0: adc0_ad0-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad1: adc0_ad1-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad2: adc0_ad2-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad3: adc0_ad3-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad4: adc0_ad4-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad5: adc0_ad5-0 { - atmel,pins = ; - }; - - pinctrl_adc0_adtrg: adc0_adtrg-0 { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , - ; - }; - }; - - ebi { - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - , - ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - , - ; - }; - }; - - i2c_gpio1 { - pinctrl_i2c_gpio1: i2c_gpio1-0 { - atmel,pins = - , - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - , - , - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - , - ; - }; - }; - - pwm0 { - pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_dcd: usart0_dcd-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_ri: usart0_ri-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_sck: usart0_sck-0 { - atmel,pins = - ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_sck: usart1_sck-0 { - atmel,pins = - ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_sck: usart2_sck-0 { - atmel,pins = - ; - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9rl-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - reset-controller@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - clk32k: clock-controller@fffffd50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffd50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x10>; - status = "disabled"; - }; - - rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio1>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts deleted file mode 100644 index a57351270551..000000000000 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board - * - * Copyright (C) 2014 Microchip - * Alexandre Belloni - */ -/dts-v1/; -#include "at91sam9rl.dtsi" - -/ { - model = "Atmel at91sam9rlek"; - compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; - - chosen { - bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - fb0: fb@500000 { - display = <&display0>; - status = "okay"; - - display0: panel { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - atmel,lcd-wiring-mode = "RGB"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_addr_nand>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - mmc0: mmc@fffa4000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = < - &pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - adc0: adc@fffd0000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_adtrg>; - atmel,adc-ts-wires = <4>; - status = "okay"; - }; - - usb0: gadget@fffd4000 { - atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffcc000 { - status = "okay"; - cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - pwm0: pwm@fffc8000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, - <&pinctrl_pwm0_pwm2_2>; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; - }; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - }; - - rtc@fffffe00 { - status = "okay"; - }; - }; - }; - - led-controller-1 { - compatible = "pwm-leds"; - - led-1 { - label = "ds1"; - pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - }; - - led-2 { - label = "ds2"; - pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - }; - }; - - led-controller-2 { - compatible = "gpio-leds"; - - led-3 { - label = "ds3"; - gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-right-click { - label = "right_click"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - - button-left-click { - label = "left_click"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - - i2c-gpio-1 { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi deleted file mode 100644 index 7036f5f04571..000000000000 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_macb1.dtsi" -#include "at91sam9x5_can.dtsi" - -/ { - model = "Atmel AT91SAM9X25 SoC"; - compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xc000001c /* pioA */ - 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ - 0x80000000 0xfffd0000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts deleted file mode 100644 index ad7c6b36f0ba..000000000000 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9x25.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9X25-EK"; - compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&can1 { - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&macb1 { - phy-mode = "rmii"; - status = "okay"; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm0_1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi deleted file mode 100644 index eb03b0497e37..000000000000 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_can.dtsi" - -/ { - model = "Atmel AT91SAM9X35 SoC"; - compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xc000000c /* pioA */ - 0x000406ff 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts deleted file mode 100644 index 66675c787b97..000000000000 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9x35.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9X35-EK"; - compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&backlight { - status = "okay"; -}; - -&bl_reg { - status = "okay"; -}; - -&hlcdc { - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&panel_reg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi deleted file mode 100644 index 0123ee47151c..000000000000 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ /dev/null @@ -1,978 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC - * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, - * AT91SAM9X25, AT91SAM9X35 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9x5 family SoC"; - compatible = "atmel,at91sam9x5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - ssc0 = &ssc0; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x8000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - matrix: matrix@ffffde00 { - compatible = "atmel,at91sam9x5-matrix", "syscon"; - reg = <0xffffde00 0x100>; - }; - - pmecc: ecc-engine@ffffe000 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffe000 0x600>, - <0xffffe600 0x200>; - }; - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>; - clock-names = "ddrck"; - }; - - smc: smc@ffffea00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x200>; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,at91sam9x5-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - reset_controller: reset-controller@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shdwc@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - clk32k: clock-controller@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - dma0: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "dma_clk"; - }; - - dma1: dma-controller@ffffee00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffee00 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "dma_clk"; - }; - - pinctrl: pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - ebi { - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_8_15: ebi-data-msb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA2 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA3 periph A */ - }; - - pinctrl_usart0_sck: usart0_sck-0 { - atmel,pins = - ; /* PA4 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PC27 periph C */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PC28 periph C */ - }; - - pinctrl_usart1_sck: usart1_sck-0 { - atmel,pins = - ; /* PC29 periph C */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - - pinctrl_usart2_sck: usart2_sck-0 { - atmel,pins = - ; /* PB2 periph B */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC9 periph C with pullup */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PC17 periph C with pullup */ - }; - }; - - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - ; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA15 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA11 periph B with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA4 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PA26 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA13 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PA23 periph B SPI1_SPCK pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA31 periph A I2C0 clock */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PC1 periph C I2C1 clock */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* PB5 periph B I2C2 clock */ - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - ; /* PA31 gpio multidrive I2C0 clock */ - }; - }; - - i2c_gpio1 { - pinctrl_i2c_gpio1: i2c_gpio1-0 { - atmel,pins = - ; /* PC1 gpio multidrive I2C1 clock */ - }; - }; - - i2c_gpio2 { - pinctrl_i2c_gpio2: i2c_gpio2-0 { - atmel,pins = - ; /* PB5 gpio multidrive I2C2 clock */ - }; - }; - - pwm0 { - pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - }; - - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "pclk"; - status = "disabled"; - }; - - mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc1: mmc@f000c000 { - compatible = "atmel,hsmci"; - reg = <0xf000c000 0x600>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x200>; - atmel,usart-mode = ; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x200>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, - <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x200>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - status = "disabled"; - }; - - i2c1: i2c@f8014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8014000 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, - <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - status = "disabled"; - }; - - i2c2: i2c@f8018000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8018000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - uart0: serial@f8040000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8040000 0x200>; - atmel,usart-mode = ; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8044000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8044000 0x200>; - atmel,usart-mode = ; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "usart"; - status = "disabled"; - }; - - adc0: adc@f804c000 { - compatible = "atmel,at91sam9x5-adc"; - reg = <0xf804c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0xffff>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-sample-hold-time = <11>; - }; - - spi0: spi@f0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0000000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - usb2: gadget@f803c000 { - compatible = "atmel,at91sam9g45-udc"; - reg = <0x00500000 0x80000 - 0xf803c000 0x400>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - watchdog: watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - rtc: rtc@fffffeb0 { - compatible = "atmel,at91sam9x5-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - usb0: ohci@600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb1: ehci@700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9x5-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x60000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ - &pioC 1 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio1>; - status = "disabled"; - }; - - i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio2>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi deleted file mode 100644 index 04ccb25d342c..000000000000 --- a/arch/arm/boot/dts/at91sam9x5_can.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - can0: can@f8000000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8000000 0x300>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8004000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8004000 0x300>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "can_clk"; - status = "disabled"; - }; - - pinctrl@fffff400 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* CANTX0, conflicts with DTXD */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* CANTX1, conflicts with TXD1 */ - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi deleted file mode 100644 index 4ce98f05d7db..000000000000 --- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an - * Image Sensor Interface. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* ISI_VSYNC, conflicts with LCDDAT13 */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* ISI_D9, conflicts with LCDDAT9 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* ISI_D11, conflicts with LCDDAT11 */ - }; - }; - }; - - isi: isi@f8048000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf8048000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi deleted file mode 100644 index f81c9d1691e0..000000000000 --- a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an - * LCD controller. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - hlcdc: hlcdc@f8038000 { - compatible = "atmel,at91sam9x5-hlcdc"; - reg = <0xf8038000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - }; - }; -}; - -&pinctrl { - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi deleted file mode 100644 index 222aa30f6860..000000000000 --- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; /* PB10 periph A */ - }; - - pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { - atmel,pins = - ; /* PB17 periph A */ - }; - }; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi deleted file mode 100644 index 26bf9b5de9ee..000000000000 --- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 - * Ethernet interfaces. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; /* PC31 periph B */ - }; - }; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf8030000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi deleted file mode 100644 index a47c765e1b20..000000000000 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * 4 USART. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include - -/ { - aliases { - serial4 = &usart3; - }; - - ahb { - apb { - pinctrl@fffff400 { - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PC25 periph B */ - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - ; /* PC26 periph B */ - }; - }; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - atmel,usart-mode = ; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi deleted file mode 100644 index cdd37f67280b..000000000000 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -/ { - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - tcb0: timer@f8008000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - pinctrl@fffff400 { - 1wire_cm { - pinctrl_1wire_cm: 1wire_cm-0 { - atmel,pins = ; /* PB18 multidrive, conflicts with led */ - }; - }; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_addr_nand - &pinctrl_ebi_data_0_7>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <2>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0xc0000>; - }; - - ubootenvred@100000 { - label = "U-Boot Env Redundant"; - reg = <0x100000 0x40000>; - }; - - ubootenv@140000 { - label = "U-Boot Env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pb18 { - label = "pb18"; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - pd21 { - label = "pd21"; - gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; - }; - }; - - 1wire_cm { - compatible = "w1-gpio"; - gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; - linux,open-drain; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_1wire_cm>; - status = "okay"; - }; - -}; diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi deleted file mode 100644 index a9278038af3b..000000000000 --- a/arch/arm/boot/dts/at91sam9x5dm.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module - * - * Copyright (C) 2014 Atmel, - * 2014 Free Electrons - * - * Author: Boris Brezillon - */ - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <&bl_reg>; - status = "disabled"; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "disabled"; - }; - - panel: panel { - compatible = "foxlink,fl500wvr00-a0t"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "disabled"; - }; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&i2c0 { - keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioA>; - interrupts = <7 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; -}; - -&hlcdc { - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; -}; - -&pinctrl { - board { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi deleted file mode 100644 index 5f4eaa618ab4..000000000000 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -#include "at91sam9x5cm.dtsi" - -/ { - model = "Atmel AT91SAM9X5-EK"; - compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; - stdout-path = "serial0:115200n8"; - }; - - sound { - compatible = "atmel,sam9x5-wm8731-audio"; - - atmel,model = "wm8731 @ AT91SAM9X5EK"; - - atmel,audio-routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; - }; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - wm8731: wm8731@1a { - compatible = "wm8731"; - reg = <0x1a>; - }; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - camera_sensor { - pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { - atmel,pins = - ; /* ISI_MCK */ - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD15 gpio CD pin pull up and deglitch */ - }; - }; - - mmc1 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - ; /* PD14 gpio CD pin pull up and deglitch */ - }; - }; - - usb2 { - pinctrl_board_usb2: usb2-board { - atmel,pins = - ; /* PB16 gpio vbus sense, deglitch */ - }; - }; -}; - -&spi0 { - cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - status = "disabled"; /* conflicts with mmc1 */ - - flash@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&ssc0 { - status = "okay"; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&usb0 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ - &pioD 19 GPIO_ACTIVE_LOW - &pioD 20 GPIO_ACTIVE_LOW - >; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_board_usb2>; - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi deleted file mode 100644 index f571f77779c3..000000000000 --- a/arch/arm/boot/dts/at91sam9xe.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Alexandre Belloni - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9XE family SoC"; - compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; - - sram0: sram@2ff000 { - status = "disabled"; - }; - - sram1: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x4000>; - }; -}; diff --git a/arch/arm/boot/dts/axis/Makefile b/arch/arm/boot/dts/axis/Makefile new file mode 100644 index 000000000000..2cab41451281 --- /dev/null +++ b/arch/arm/boot/dts/axis/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_ARTPEC6) += \ + artpec6-devboard.dtb +dtb-$(CONFIG_MACH_ARTPEC6) += \ + artpec6-devboard.dtb diff --git a/arch/arm/boot/dts/axis/artpec6-devboard.dts b/arch/arm/boot/dts/axis/artpec6-devboard.dts new file mode 100644 index 000000000000..042a9cc920c6 --- /dev/null +++ b/arch/arm/boot/dts/axis/artpec6-devboard.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Axis ARTPEC-6 development board. + +/dts-v1/; +#include "artpec6.dtsi" + +/ { + model = "ARTPEC-6 development board"; + compatible = "axis,artpec6-dev-board", "axis,artpec6"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +ðernet { + status = "okay"; + + phy-handle = <&phy1>; + phy-mode = "gmii"; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/axis/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi new file mode 100644 index 000000000000..037157e6c5ee --- /dev/null +++ b/arch/arm/boot/dts/axis/artpec6.dtsi @@ -0,0 +1,388 @@ +/* + * Device Tree Source for the Axis ARTPEC-6 SoC + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "axis,artpec6"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&pl310>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&pl310>; + }; + }; + + syscon: syscon@f8000000 { + compatible = "axis,artpec6-syscon", "syscon"; + reg = <0xf8000000 0x48>; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + psci_version = <0x84000000>; + cpu_on = <0x84000003>; + system_reset = <0x84000009>; + }; + + scu@faf00000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfaf00000 0x58>; + }; + + /* Main external clock driving CPU and peripherals */ + ext_clk: ext_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + eth_phy_ref_clk: eth_phy_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + clkctrl: clkctrl@f8000000 { + #clock-cells = <1>; + compatible = "axis,artpec6-clkctrl"; + reg = <0xf8000000 0x48>; + clocks = <&ext_clk>; + clock-names = "sys_refclk"; + }; + + gtimer@faf00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfaf00200 0x20>; + interrupts = ; + clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; + }; + + timer@faf00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfaf00600 0x20>; + interrupts = ; + clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; + status = "disabled"; + }; + + intc: interrupt-controller@faf01000 { + interrupt-controller; + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; + }; + + pl310: cache-controller@faf10000 { + compatible = "arm,pl310-cache"; + cache-unified; + cache-level = <2>; + reg = <0xfaf10000 0x1000>; + interrupts = ; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + arm,filter-ranges = <0x0 0x80000000>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,prefetch-offset = <0>; + arm,prefetch-drop = <1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* + * Both pci nodes cannot be enabled at the same time, + * leave the unwanted node as disabled. + */ + pcie: pcie@f8050000 { + compatible = "axis,artpec6-pcie", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x2000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* downstream I/O */ + ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + + pcie_ep: pcie_ep@f8050000 { + compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8051000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x20000000>; + reg-names = "dbi", "dbi2", "phy", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <2>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + + pinctrl: pinctrl@f801d000 { + compatible = "axis,artpec6-pinctrl"; + reg = <0xf801d000 0x400>; + + pinctrl_uart0: uart0grp { + function = "uart0"; + groups = "uart0grp2"; + bias-pull-up; + }; + pinctrl_uart1: uart1grp { + function = "uart1"; + groups = "uart1grp0"; + bias-pull-up; + }; + pinctrl_uart2: uart2grp { + function = "uart2"; + groups = "uart2grp1"; + bias-pull-up; + }; + pinctrl_uart3: uart3grp { + function = "uart3"; + groups = "uart3grp0"; + bias-pull-up; + }; + }; + + amba@0 { + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + dma-ranges; + + crypto@f4264000 { + compatible = "axis,artpec6-crypto"; + reg = <0xf4264000 0x4000>; + interrupts = ; + }; + + dma0: dma@f8019000 { + compatible = "renesas,nbpfaxi64dmac8b16"; + reg = <0xf8019000 0x400>; + interrupts = , /* error */ + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch12", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; + #dma-cells = <2>; + dma-channels = <8>; + dma-requests = <8>; + }; + dma1: dma@f8019400 { + compatible = "renesas,nbpfaxi64dmac8b16"; + reg = <0xf8019400 0x400>; + interrupts = , /* error */ + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch12", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; + #dma-cells = <2>; + dma-channels = <8>; + dma-requests = <8>; + }; + + ethernet: ethernet@f8010000 { + clock-names = "stmmaceth", "ptp_ref"; + clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>, + <&clkctrl ARTPEC6_CLK_PTP_REF>; + compatible = "snps,dwmac-4.10a", "snps,dwmac"; + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + reg = <0xf8010000 0x4000>; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + snps,txpbl = <8>; + snps,rxpbl = <2>; + snps,aal; + snps,tso; + + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <15>; + /* If FB is disabled, the AXI master chooses + * a burst length of any value less than the + * maximum enabled burst length + * (all lesser burst length enables are redundant). + */ + snps,blen = <0 0 0 0 16 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + uart0: serial@f8036000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8036000 0x1000>; + interrupts = ; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; + clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart1: serial@f8037000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8037000 0x1000>; + interrupts = ; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; + clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart2: serial@f8038000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8038000 0x1000>; + interrupts = ; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; + clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart3: serial@f8039000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8039000 0x1000>; + interrupts = ; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; + clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts deleted file mode 100644 index 2e2ad3c7ee77..000000000000 --- a/arch/arm/boot/dts/axm5516-amarillo.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/boot/dts/axm5516-amarillo.dts - * - * Copyright (C) 2013 LSI - */ - -/dts-v1/; - -/memreserve/ 0x00000000 0x00400000; - -#include "axm55xx.dtsi" -#include "axm5516-cpus.dtsi" - -/ { - model = "Amarillo AXM5516"; - compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0x02 0x00000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi deleted file mode 100644 index f13ef80b6637..000000000000 --- a/arch/arm/boot/dts/axm5516-cpus.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/boot/dts/axm5516-cpus.dtsi - * - * Copyright (C) 2013 LSI - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - cluster2 { - core0 { - cpu = <&CPU8>; - }; - core1 { - cpu = <&CPU9>; - }; - core2 { - cpu = <&CPU10>; - }; - core3 { - cpu = <&CPU11>; - }; - }; - cluster3 { - core0 { - cpu = <&CPU12>; - }; - core1 { - cpu = <&CPU13>; - }; - core2 { - cpu = <&CPU14>; - }; - core3 { - cpu = <&CPU15>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x00>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x01>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x02>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x03>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x102>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x103>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x200>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x201>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU10: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x202>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU11: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x203>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU12: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x300>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU13: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x301>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU14: cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x302>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU15: cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x303>; - clock-frequency = <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - }; -}; diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi deleted file mode 100644 index 5277890cfad2..000000000000 --- a/arch/arm/boot/dts/axm55xx.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/boot/dts/axm55xx.dtsi - * - * Copyright (C) 2013 LSI - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - timer = &timer0; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clk_ref0: clk_ref0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref1: clk_ref1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref2: clk_ref2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clks: clock-controller@2010020000 { - compatible = "lsi,axm5516-clks"; - #clock-cells = <1>; - reg = <0x20 0x10020000 0 0x20000>; - }; - }; - - gic: interrupt-controller@2001001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x20 0x01001000 0 0x1000>, - <0x20 0x01002000 0 0x2000>, - <0x20 0x01004000 0 0x2000>, - <0x20 0x01006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - device_type = "soc"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - ranges; - - syscon: syscon@2010030000 { - compatible = "lsi,axxia-syscon", "syscon"; - reg = <0x20 0x10030000 0 0x2000>; - }; - - reset: reset@2010031000 { - compatible = "lsi,axm55xx-reset"; - syscon = <&syscon>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - serial0: serial@2010080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10080000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial1: serial@2010081000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10081000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial2: serial@2010082000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10082000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial3: serial@2010083000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10083000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer0: timer@2010091000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x20 0x10091000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "okay"; - }; - - gpio0: gpio@2010092000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10092000 0x00 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@2010093000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10093000 0x00 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - }; - }; -}; - -/* - Local Variables: - mode: C - End: -*/ diff --git a/arch/arm/boot/dts/axp152.dtsi b/arch/arm/boot/dts/axp152.dtsi deleted file mode 100644 index f90ad6c64a07..000000000000 --- a/arch/arm/boot/dts/axp152.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&axp152 { - compatible = "x-powers,axp152"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi deleted file mode 100644 index 469d0f7d5185..000000000000 --- a/arch/arm/boot/dts/axp209.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP202/209 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP20X.php - * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf - */ - -/ { - pmic-temp { - compatible = "iio-hwmon"; - io-channels = <&axp_adc 4>; /* Internal temperature */ - }; -}; - -&axp209 { - compatible = "x-powers,axp209"; - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power { - compatible = "x-powers,axp202-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp209-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp209-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - battery_power_supply: battery-power { - compatible = "x-powers,axp209-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <1500>; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_ldo1: ldo1 { - /* LDO1 is a fixed output regulator */ - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "ldo1"; - }; - - reg_ldo2: ldo2 { - regulator-name = "ldo2"; - }; - - reg_ldo3: ldo3 { - regulator-name = "ldo3"; - }; - - reg_ldo4: ldo4 { - regulator-name = "ldo4"; - }; - - reg_ldo5: ldo5 { - regulator-name = "ldo5"; - status = "disabled"; - }; - }; - - usb_power_supply: usb-power { - compatible = "x-powers,axp202-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/axp223.dtsi b/arch/arm/boot/dts/axp223.dtsi deleted file mode 100644 index b91b6c1278c7..000000000000 --- a/arch/arm/boot/dts/axp223.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * - * Quentin Schulz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP223 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP22X.php - * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf - * - * The AXP223 shares most of its logic with the AXP221 but it has some - * differences, for the VBUS driver for example. - */ - -#include "axp22x.dtsi" - -&usb_power_supply { - compatible = "x-powers,axp223-usb-power-supply"; -}; diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi deleted file mode 100644 index f79650afd0a7..000000000000 --- a/arch/arm/boot/dts/axp22x.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP221/221s/223 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP22X.php - * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf - */ - -&axp22x { - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power { - compatible = "x-powers,axp221-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp221-adc"; - #io-channel-cells = <1>; - }; - - battery_power_supply: battery-power { - compatible = "x-powers,axp221-battery-power-supply"; - status = "disabled"; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp221-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_dcdc1: dcdc1 { - regulator-name = "dcdc1"; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_dcdc4: dcdc4 { - regulator-name = "dcdc4"; - }; - - reg_dcdc5: dcdc5 { - regulator-name = "dcdc5"; - }; - - reg_dc1sw: dc1sw { - regulator-name = "dc1sw"; - }; - - reg_dc5ldo: dc5ldo { - regulator-name = "dc5ldo"; - }; - - reg_aldo1: aldo1 { - regulator-name = "aldo1"; - }; - - reg_aldo2: aldo2 { - regulator-name = "aldo2"; - }; - - reg_aldo3: aldo3 { - regulator-name = "aldo3"; - }; - - reg_dldo1: dldo1 { - regulator-name = "dldo1"; - }; - - reg_dldo2: dldo2 { - regulator-name = "dldo2"; - }; - - reg_dldo3: dldo3 { - regulator-name = "dldo3"; - }; - - reg_dldo4: dldo4 { - regulator-name = "dldo4"; - }; - - reg_eldo1: eldo1 { - regulator-name = "eldo1"; - }; - - reg_eldo2: eldo2 { - regulator-name = "eldo2"; - }; - - reg_eldo3: eldo3 { - regulator-name = "eldo3"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-name = "ldo_io0"; - status = "disabled"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-name = "ldo_io1"; - status = "disabled"; - }; - - reg_rtc_ldo: rtc_ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "rtc_ldo"; - }; - - reg_drivevbus: drivevbus { - regulator-name = "drivevbus"; - status = "disabled"; - }; - }; - - usb_power_supply: usb-power { - compatible = "x-powers,axp221-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/axp809.dtsi deleted file mode 100644 index d134d4c00bd8..000000000000 --- a/arch/arm/boot/dts/axp809.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP809 Integrated Power Management Chip - */ - -&axp809 { - compatible = "x-powers,axp809"; - interrupt-controller; - #interrupt-cells = <1>; - - axp_gpio: gpio { - compatible = "x-powers,axp809-gpio", - "x-powers,axp221-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi deleted file mode 100644 index ebaf1c3ce8db..000000000000 --- a/arch/arm/boot/dts/axp81x.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2017 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* AXP813/818 Integrated Power Management Chip */ - -&axp81x { - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power { - compatible = "x-powers,axp813-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp813-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp813-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - battery_power_supply: battery-power { - compatible = "x-powers,axp813-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_dcdc1: dcdc1 { - }; - - reg_dcdc2: dcdc2 { - }; - - reg_dcdc3: dcdc3 { - }; - - reg_dcdc4: dcdc4 { - }; - - reg_dcdc5: dcdc5 { - }; - - reg_dcdc6: dcdc6 { - }; - - reg_dcdc7: dcdc7 { - }; - - reg_aldo1: aldo1 { - }; - - reg_aldo2: aldo2 { - }; - - reg_aldo3: aldo3 { - }; - - reg_dldo1: dldo1 { - }; - - reg_dldo2: dldo2 { - }; - - reg_dldo3: dldo3 { - }; - - reg_dldo4: dldo4 { - }; - - reg_eldo1: eldo1 { - }; - - reg_eldo2: eldo2 { - }; - - reg_eldo3: eldo3 { - }; - - reg_fldo1: fldo1 { - }; - - reg_fldo2: fldo2 { - }; - - reg_fldo3: fldo3 { - }; - - reg_ldo_io0: ldo-io0 { - /* Disable by default to avoid conflicts with GPIO */ - status = "disabled"; - }; - - reg_ldo_io1: ldo-io1 { - /* Disable by default to avoid conflicts with GPIO */ - status = "disabled"; - }; - - reg_rtc_ldo: rtc-ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_sw: sw { - }; - - reg_drivevbus: drivevbus { - status = "disabled"; - }; - }; - - usb_power_supply: usb-power { - compatible = "x-powers,axp813-usb-power-supply"; - }; -}; diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi deleted file mode 100644 index 52f91a12a99a..000000000000 --- a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - /* Cygnus ARM PLL */ - armpll: armpll@19000000 { - #clock-cells = <0>; - compatible = "brcm,cygnus-armpll"; - clocks = <&osc>; - reg = <0x19000000 0x1000>; - }; - - /* peripheral clock for system timer */ - periph_clk: arm_periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* APB bus clock */ - apb_clk: apb_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll: genpll@301d000 { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - - /* always 1/2 of the axi21 clock */ - axi41_clk: axi41_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll 1>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* always 1/4 of the axi21 clock */ - axi81_clk: axi81_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll 1>; - clock-div = <4>; - clock-mult = <1>; - }; - - lcpll0: lcpll0@301d02c { - #clock-cells = <1>; - compatible = "brcm,cygnus-lcpll0"; - reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio", - "usb_phy", "smart_card", "ch5"; - }; - - mipipll: mipipll@180a9800 { - #clock-cells = <1>; - compatible = "brcm,cygnus-mipipll"; - reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "mipipll", "ch0_unused", "ch1_lcd", - "ch2_v3d", "ch3_unused", "ch4_unused", - "ch5_unused"; - }; - - asiu_clks: asiu_clks@301d048 { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - - audiopll: audiopll@180aeb00 { - #clock-cells = <1>; - compatible = "brcm,cygnus-audiopll"; - reg = <0x180aeb00 0x68>; - clocks = <&osc>; - clock-output-names = "audiopll", "ch0_audio", - "ch1_audio", "ch2_audio"; - }; -}; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi deleted file mode 100644 index f9f79ed82518..000000000000 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ /dev/null @@ -1,623 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "brcm,cygnus"; - model = "Broadcom Cygnus SoC"; - interrupt-parent = <&gic>; - - aliases { - ethernet0 = ð0; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; - - /include/ "bcm-cygnus-clock.dtsi" - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - core@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - axi { - compatible = "simple-bus"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - otp: otp@301c800 { - compatible = "brcm,ocotp"; - reg = <0x0301c800 0x2c>; - brcm,ocotp-size = <2048>; - status = "disabled"; - }; - - pcie_phy: pcie_phy@301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - #address-cells = <1>; - #size-cells = <0>; - - pcie0_phy: pcie-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: pcie-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - pinctrl: pinctrl@301d0c8 { - compatible = "brcm,cygnus-pinmux"; - reg = <0x0301d0c8 0x30>, - <0x0301d24c 0x2c>; - - spi_0: spi_0 { - function = "spi0"; - groups = "spi0_grp"; - }; - - spi_1: spi_1 { - function = "spi1"; - groups = "spi1_grp"; - }; - - spi_2: spi_2 { - function = "spi2"; - groups = "spi2_grp"; - }; - }; - - mailbox: mailbox@3024024 { - compatible = "brcm,iproc-mailbox"; - reg = <0x03024024 0x40>; - interrupts = ; - #interrupt-cells = <1>; - interrupt-controller; - #mbox-cells = <1>; - }; - - gpio_crmu: gpio@3024800 { - compatible = "brcm,cygnus-crmu-gpio"; - reg = <0x03024800 0x50>, - <0x03024008 0x18>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - interrupt-parent = <&mailbox>; - interrupts = <0>; - }; - - mdio: mdio@18002000 { - compatible = "brcm,iproc-mdio"; - reg = <0x18002000 0x8>; - #size-cells = <0>; - #address-cells = <1>; - status = "disabled"; - - gphy0: ethernet-phy@0 { - reg = <0>; - }; - - gphy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - switch: switch@18007000 { - compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; - reg = <0x18007000 0x1000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-handle = <&gphy0>; - phy-mode = "rgmii"; - }; - - port@1 { - reg = <1>; - phy-handle = <&gphy1>; - phy-mode = "rgmii"; - }; - - port@8 { - reg = <8>; - label = "cpu"; - ethernet = <ð0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - i2c0: i2c@18008000 { - compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; - reg = <0x18008000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: wdt@18009000 { - compatible = "arm,sp805" , "arm,primecell"; - reg = <0x18009000 0x1000>; - interrupts = ; - clocks = <&axi81_clk>, <&axi81_clk>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - }; - - i2c1: i2c@1800b000 { - compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; - reg = <0x1800b000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, - <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, - <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&pcie1_phy>; - phy-names = "pcie-phy"; - - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - dma0: dma@18018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x18018000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&apb_clk>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - uart0: serial@18020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18020000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart1: serial@18021000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18021000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart2: serial@18022000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18022000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart3: serial@18023000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18023000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - spi0: spi@18028000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x18028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-0 = <&spi_0>; - clocks = <&axi81_clk>, <&axi81_clk>; - clock-names = "sspclk", "apb_pclk"; - status = "disabled"; - }; - - spi1: spi@18029000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x18029000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-0 = <&spi_1>; - clocks = <&axi81_clk>, <&axi81_clk>; - clock-names = "sspclk", "apb_pclk"; - status = "disabled"; - }; - - spi2: spi@1802a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-0 = <&spi_2>; - clocks = <&axi81_clk>, <&axi81_clk>; - clock-names = "sspclk", "apb_pclk"; - status = "disabled"; - }; - - rng: rng@18032000 { - compatible = "brcm,iproc-rng200"; - reg = <0x18032000 0x28>; - }; - - sdhci0: sdhci@18041000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x18041000 0x100>; - interrupts = ; - clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; - bus-width = <4>; - sdhci,auto-cmd12; - status = "disabled"; - }; - - eth0: ethernet@18042000 { - compatible = "brcm,amac"; - reg = <0x18042000 0x1000>, - <0x18110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: sdhci@18043000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x18043000 0x100>; - interrupts = ; - clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; - bus-width = <4>; - sdhci,auto-cmd12; - status = "disabled"; - }; - - nand_controller: nand-controller@18046000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x18046000 0x600>, <0xf8105408 0x600>, - <0x18046f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - ehci0: usb@18048000 { - compatible = "generic-ehci"; - reg = <0x18048000 0x100>; - interrupts = ; - status = "disabled"; - }; - - ohci0: usb@18048800 { - compatible = "generic-ohci"; - reg = <0x18048800 0x100>; - interrupts = ; - status = "disabled"; - }; - - clcd: clcd@180a0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x180a0000 0x1000>; - interrupts = ; - interrupt-names = "combined"; - clocks = <&axi41_clk>, <&apb_clk>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - v3d: v3d@180a2000 { - compatible = "brcm,cygnus-v3d"; - reg = <0x180a2000 0x1000>; - clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; - clock-names = "v3d_clk"; - interrupts = ; - status = "disabled"; - }; - - vc4: gpu { - compatible = "brcm,cygnus-vc4"; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>, - <&pinctrl 4 48 1>, - <&pinctrl 5 50 3>, - <&pinctrl 8 126 1>, - <&pinctrl 9 155 1>, - <&pinctrl 10 152 1>, - <&pinctrl 11 154 1>, - <&pinctrl 12 153 1>, - <&pinctrl 13 127 3>, - <&pinctrl 16 140 1>, - <&pinctrl 17 145 7>, - <&pinctrl 24 130 10>, - <&pinctrl 34 141 4>, - <&pinctrl 38 54 1>, - <&pinctrl 39 56 3>, - <&pinctrl 42 60 3>, - <&pinctrl 45 64 3>, - <&pinctrl 48 68 2>, - <&pinctrl 50 84 6>, - <&pinctrl 56 94 6>, - <&pinctrl 62 72 1>, - <&pinctrl 63 70 1>, - <&pinctrl 64 80 1>, - <&pinctrl 65 74 3>, - <&pinctrl 68 78 1>, - <&pinctrl 69 82 1>, - <&pinctrl 70 156 17>, - <&pinctrl 87 104 12>, - <&pinctrl 99 102 2>, - <&pinctrl 101 90 4>, - <&pinctrl 105 116 6>, - <&pinctrl 111 100 2>, - <&pinctrl 113 122 4>, - <&pinctrl 123 11 1>, - <&pinctrl 124 38 4>, - <&pinctrl 128 43 1>, - <&pinctrl 129 47 1>, - <&pinctrl 130 49 1>, - <&pinctrl 131 53 1>, - <&pinctrl 132 55 1>, - <&pinctrl 133 59 1>, - <&pinctrl 134 63 1>, - <&pinctrl 135 67 1>, - <&pinctrl 136 71 1>, - <&pinctrl 137 73 1>, - <&pinctrl 138 77 1>, - <&pinctrl 139 79 1>, - <&pinctrl 140 81 1>, - <&pinctrl 141 83 1>, - <&pinctrl 142 10 1>; - }; - - ts_adc_syscon: ts_adc_syscon@180a6000 { - compatible = "brcm,iproc-ts-adc-syscon", "syscon"; - reg = <0x180a6000 0xc30>; - }; - - touchscreen: touchscreen@180a6000 { - compatible = "brcm,iproc-touchscreen"; - #address-cells = <1>; - #size-cells = <1>; - ts_syscon = <&ts_adc_syscon>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - status = "disabled"; - }; - - adc: adc@180a6000 { - compatible = "brcm,iproc-static-adc"; - #io-channel-cells = <1>; - adc-syscon = <&ts_adc_syscon>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - status = "disabled"; - }; - - pwm: pwm@180aa500 { - compatible = "brcm,kona-pwm"; - reg = <0x180aa500 0xc4>; - #pwm-cells = <3>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; - status = "disabled"; - }; - - keypad: keypad@180ac000 { - compatible = "brcm,bcm-keypad"; - reg = <0x180ac000 0x14c>; - interrupts = ; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; - clock-names = "peri_clk"; - clock-frequency = <31250>; - pull-up-enabled; - col-debounce-filter-period = <0>; - status-debounce-filter-period = <0>; - row-output-enabled; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi deleted file mode 100644 index 33e6ba63a1ee..000000000000 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -/ { - compatible = "brcm,hr2"; - model = "Broadcom Hurricane 2 SoC"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>; - }; - - mpcore@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,hr2-armpll"; - clocks = <&osc>; - reg = <0x0 0x1000>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - axi@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011c40c>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550a"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - dma@20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - status = "disabled"; - }; - - amac0: ethernet@22000 { - compatible = "brcm,nsp-amac"; - reg = <0x22000 0x1000>, - <0x110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - status = "disabled"; - }; - - nand_controller: nand-controller@26000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x26000 0x600>, - <0x11b408 0x600>, - <0x026f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - gpiob: gpio@30000 { - compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; - reg = <0x30000 0x50>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <4>; - interrupt-controller; - interrupts = ; - }; - - pwm: pwm@31000 { - compatible = "brcm,iproc-pwm"; - reg = <0x31000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; - }; - - qspi: spi@27200 { - compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; - reg = <0x027200 0x184>, - <0x027000 0x124>, - <0x11c408 0x004>, - <0x0273a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - - /* partitions defined in board DTS */ - }; - - ccbtimer0: timer@34000 { - compatible = "arm,sp804"; - reg = <0x34000 0x1000>; - interrupts = , - ; - }; - - ccbtimer1: timer@35000 { - compatible = "arm,sp804"; - reg = <0x35000 0x1000>; - interrupts = , - ; - }; - - i2c0: i2c@38000 { - compatible = "brcm,iproc-i2c"; - reg = <0x38000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - }; - - watchdog: watchdog@39000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x39000 0x1000>; - interrupts = ; - }; - - i2c1: i2c@3b000 { - compatible = "brcm,iproc-i2c"; - reg = <0x3b000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - }; - }; - - pflash: nor@20000000 { - compatible = "cfi-flash", "jedec-flash"; - reg = <0x20000000 0x04000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - - /* partitions defined in board DTS */ - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi deleted file mode 100644 index dae9c47ace76..000000000000 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ /dev/null @@ -1,464 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2013-2014 Hauke Mehrtens - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chipcommon-a-bus@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@300 { - compatible = "ns16550"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&iprocslow>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&iprocslow>; - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_uart1>; - status = "disabled"; - }; - }; - - mpcore-bus@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - scu@20000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x20000 0x100>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - arm,shared-override; - prefetch-data = <1>; - prefetch-instr = <1>; - cache-level = <2>; - }; - }; - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - - /* Switch Register Access Block */ - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 1 */ - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 2 */ - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 3.0 Controller */ - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 2 */ - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 3 */ - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - - /* NAND Controller */ - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon: chipcommon@0 { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcie0: pcie@12000 { - reg = <0x00012000 0x1000>; - - #address-cells = <3>; - #size-cells = <2>; - }; - - pcie1: pcie@13000 { - reg = <0x00013000 0x1000>; - - #address-cells = <3>; - #size-cells = <2>; - }; - - pcie2: pcie@14000 { - reg = <0x00014000 0x1000>; - - #address-cells = <3>; - #size-cells = <2>; - }; - - usb2: usb2@21000 { - reg = <0x00021000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupt-parent = <&gic>; - - ehci: usb@21000 { - compatible = "generic-ehci"; - reg = <0x00021000 0x1000>; - interrupts = ; - phys = <&usb2_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - ehci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ehci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - - ohci: usb@22000 { - compatible = "generic-ohci"; - reg = <0x00022000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ohci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ohci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3: usb3@23000 { - reg = <0x00023000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupt-parent = <&gic>; - - xhci: usb@23000 { - compatible = "generic-xhci"; - reg = <0x00023000 0x1000>; - interrupts = ; - phys = <&usb3_phy>; - phy-names = "usb"; - - #address-cells = <1>; - #size-cells = <0>; - - xhci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - gmac0: ethernet@24000 { - reg = <0x24000 0x800>; - }; - - gmac1: ethernet@25000 { - reg = <0x25000 0x800>; - }; - - gmac2: ethernet@26000 { - reg = <0x26000 0x800>; - }; - - gmac3: ethernet@27000 { - reg = <0x27000 0x800>; - }; - }; - - pwm: pwm@18002000 { - compatible = "brcm,iproc-pwm"; - reg = <0x18002000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - mdio: mdio@18003000 { - compatible = "brcm,iproc-mdio"; - reg = <0x18003000 0x8>; - #size-cells = <0>; - #address-cells = <1>; - }; - - rng: rng@18004000 { - compatible = "brcm,bcm5301x-rng"; - reg = <0x18004000 0x14>; - }; - - srab: ethernet-switch@18007000 { - compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - - port@4 { - reg = <4>; - }; - - port@5 { - reg = <5>; - ethernet = <&gmac0>; - }; - - port@7 { - reg = <7>; - ethernet = <&gmac1>; - }; - - port@8 { - reg = <8>; - ethernet = <&gmac2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - uart2: serial@18008000 { - compatible = "ns16550a"; - reg = <0x18008000 0x20>; - clocks = <&iprocslow>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - dmu-bus@1800c000 { - compatible = "simple-bus"; - ranges = <0 0x1800c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - cru-bus@100 { - compatible = "brcm,ns-cru", "simple-mfd"; - reg = <0x100 0x1a4>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - usb2_phy: phy@164 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x164 0x4>; - brcm,syscon-clkset = <&cru_clkset>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - #phy-cells = <0>; - }; - - cru_clkset: syscon@180 { - compatible = "brcm,cru-clkset", "syscon"; - reg = <0x180 0x4>; - }; - - pinctrl: pinctrl@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; - - spi-pins { - groups = "spi_grp"; - function = "spi"; - }; - - pinmux_i2c: i2c-pins { - groups = "i2c_grp"; - function = "i2c"; - }; - - pinmux_pwm: pwm-pins { - groups = "pwm0_grp", "pwm1_grp", - "pwm2_grp", "pwm3_grp"; - function = "pwm"; - }; - - pinmux_uart1: uart1-pins { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - thermal: thermal@2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x2c0 0x10>; - #thermal-sensor-cells = <0>; - }; - }; - }; - - nand_controller: nand-controller@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - coefficients = <(-556) 418000>; - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/bcm-nsp-ax.dtsi deleted file mode 100644 index f2e941dbab10..000000000000 --- a/arch/arm/boot/dts/bcm-nsp-ax.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom Northstar Plus Ax stepping-specific bindings. - * Notable differences from B0+ are the secondary-boot-reg and - * lack of DMA coherency. - */ - -&cpu1 { - secondary-boot-reg = <0xffff042c>; -}; - -&dma { - /delete-property/ dma-coherent; -}; - -&sdio { - /delete-property/ dma-coherent; -}; - -&amac0 { - /delete-property/ dma-coherent; -}; - -&amac1 { - /delete-property/ dma-coherent; -}; - -&amac2 { - /delete-property/ dma-coherent; -}; - -&ehci0 { - /delete-property/ dma-coherent; -}; - -&mailbox { - /delete-property/ dma-coherent; -}; - -&xhci { - /delete-property/ dma-coherent; -}; - -&ehci0 { - /delete-property/ dma-coherent; -}; - -&ohci0 { - /delete-property/ dma-coherent; -}; - -&i2c0 { - /delete-property/ dma-coherent; -}; - -&sata { - /delete-property/ dma-coherent; -}; - -&pcie0 { - /delete-property/ dma-coherent; -}; - -&pcie1 { - /delete-property/ dma-coherent; -}; - -&pcie2 { - /delete-property/ dma-coherent; -}; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi deleted file mode 100644 index 5b1dc58d40ba..000000000000 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ /dev/null @@ -1,695 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "brcm,nsp"; - model = "Broadcom Northstar Plus SoC"; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = &amac0; - ethernet1 = &amac1; - ethernet2 = &amac2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff0fec>; - reg = <0x1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - mpcore-bus@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - axi: axi@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011c40c>; - #address-cells = <1>; - #size-cells = <1>; - - gpioa: gpio@20 { - compatible = "brcm,nsp-gpio-a"; - reg = <0x0020 0x70>, - <0x3f1c4 0x1c>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - uart0: serial@300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550a"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - dma: dma@20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - dma-coherent; - status = "disabled"; - }; - - sdio: mmc@21000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x21000 0x100>; - interrupts = ; - sdhci,auto-cmd12; - clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; - dma-coherent; - status = "disabled"; - }; - - amac0: ethernet@22000 { - compatible = "brcm,nsp-amac"; - reg = <0x022000 0x1000>, - <0x110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - amac1: ethernet@23000 { - compatible = "brcm,nsp-amac"; - reg = <0x023000 0x1000>, - <0x111000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - amac2: ethernet@24000 { - compatible = "brcm,nsp-amac"; - reg = <0x024000 0x1000>, - <0x112000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - mailbox: mailbox@25c00 { - compatible = "brcm,iproc-fa2-mbox"; - reg = <0x25c00 0x400>; - interrupts = ; - #mbox-cells = <1>; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - dma-coherent; - }; - - nand_controller: nand-controller@26000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x026000 0x600>, - <0x11b408 0x600>, - <0x026f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - qspi: spi@27200 { - compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; - reg = <0x027200 0x184>, - <0x027000 0x124>, - <0x11c408 0x004>, - <0x0273a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - xhci: usb@29000 { - compatible = "generic-xhci"; - reg = <0x29000 0x1000>; - interrupts = ; - phys = <&usb3_phy>; - phy-names = "usb3-phy"; - dma-coherent; - status = "disabled"; - }; - - ehci0: usb@2a000 { - compatible = "generic-ehci"; - reg = <0x2a000 0x100>; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - ohci0: usb@2b000 { - compatible = "generic-ohci"; - reg = <0x2b000 0x100>; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - crypto@2f000 { - compatible = "brcm,spum-nsp-crypto"; - reg = <0x2f000 0x900>; - mboxes = <&mailbox 0>; - }; - - gpiob: gpio@30000 { - compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; - reg = <0x30000 0x50>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <4>; - interrupt-controller; - interrupts = ; - }; - - pwm: pwm@31000 { - compatible = "brcm,iproc-pwm"; - reg = <0x31000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - mdio: mdio@32000 { - compatible = "brcm,iproc-mdio"; - reg = <0x32000 0x8>; - #size-cells = <0>; - #address-cells = <1>; - }; - - mdio-mux@32000 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - reg = <0x32000 0x4>; - mux-mask = <0x200>; - #address-cells = <1>; - #size-cells = <0>; - mdio-parent-bus = <&mdio>; - - mdio_int: mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - usb3_phy: usb3-phy@10 { - compatible = "brcm,ns-bx-usb3-phy"; - reg = <0x10>; - usb3-dmp-syscon = <&usb3_dmp>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - mdio_ext: mdio@200 { - reg = <0x200>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; - }; - - ccbtimer0: timer@34000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x34000 0x1000>; - interrupts = , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - ccbtimer1: timer@35000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x35000 0x1000>; - interrupts = , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - srab: ethernet-switch@36000 { - compatible = "brcm,nsp-srab"; - reg = <0x36000 0x1000>, - <0x3f308 0x8>, - <0x3f410 0xc>; - reg-names = "srab", "mux_config", "sgmii_config"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "link_state_p0", - "link_state_p1", - "link_state_p2", - "link_state_p3", - "link_state_p4", - "link_state_p5", - "link_state_p7", - "link_state_p8", - "phy", - "ts", - "imp_sleep_timer_p5", - "imp_sleep_timer_p7", - "imp_sleep_timer_p8"; - status = "disabled"; - - /* ports are defined in board DTS */ - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c0: i2c@38000 { - compatible = "brcm,iproc-i2c"; - reg = <0x38000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - dma-coherent; - status = "disabled"; - }; - - watchdog@39000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x39000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - lcpll0: lcpll0@3f100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x3f100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - - genpll: genpll@3f140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x3f140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - pinctrl: pinctrl@3f1c0 { - compatible = "brcm,nsp-pinmux"; - reg = <0x3f1c0 0x04>, - <0x30028 0x04>, - <0x3f408 0x04>; - }; - - thermal: thermal@3f2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x3f2c0 0x10>; - #thermal-sensor-cells = <0>; - }; - - sata_phy: sata_phy@40100 { - compatible = "brcm,iproc-nsp-sata-phy"; - reg = <0x40100 0x340>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - sata: sata@41000 { - compatible = "brcm,bcm-nsp-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x41000 0x1000>, <0x40020 0x1c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - dma-coherent; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - phy-names = "sata-phy"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - phy-names = "sata-phy"; - }; - }; - - usb3_dmp: syscon@104000 { - reg = <0x104000 0x1000>; - }; - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; - - dma-coherent; - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; - - dma-coherent; - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie2: pcie@18014000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18014000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <2>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; - - dma-coherent; - status = "disabled"; - - msi-parent = <&msi2>; - msi2: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - coefficients = <(-556) 418000>; - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi deleted file mode 100644 index b271a9bf06a9..000000000000 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2012-2013 Broadcom Corporation - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "BCM11351 SoC"; - compatible = "brcm,bcm11351"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; - reg = <1>; - }; - }; - - gic: interrupt-controller@3ff00100 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x3ff01000 0x1000>, - <0x3ff00100 0x100>; - }; - - smc@3404c000 { - compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; - reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ - }; - - uartb: serial@3e000000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e000000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb2: serial@3e001000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e001000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb3: serial@3e002000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e002000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb4: serial@3e003000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e003000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - L2: l2-cache@3ff20000 { - compatible = "brcm,bcm11351-a2-pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - watchdog@35002f40 { - compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; - reg = <0x35002f40 0x6c>; - }; - - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1000>; - interrupts = ; - clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; - }; - - gpio: gpio@35003000 { - compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x800>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - sdio1: mmc@3f180000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f180000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: mmc@3f190000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f190000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: mmc@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: mmc@3f1b0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1b0000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - }; - - bsc1: i2c@3e016000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e016000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - bsc2: i2c@3e017000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e017000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - bsc3: i2c@3e018000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e018000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - pmu_bsc: i2c@3500d000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3500d000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; - status = "disabled"; - }; - - pwm: pwm@3e01a000 { - compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; - reg = <0x3e01a000 0xcc>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - root_ccu: root_ccu@35001000 { - compatible = "brcm,bcm11351-root-ccu"; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - hub_ccu: hub_ccu@34000000 { - compatible = "brcm,bcm11351-hub-ccu"; - reg = <0x34000000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "tmon_1m"; - }; - - aon_ccu: aon_ccu@35002000 { - compatible = "brcm,bcm11351-aon-ccu"; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer", - "pmu_bsc", - "pmu_bsc_var"; - }; - - master_ccu: master_ccu@3f001000 { - compatible = "brcm,bcm11351-master-ccu"; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "usb_ic", - "hsic2_48m", - "hsic2_12m"; - }; - - slave_ccu: slave_ccu@3e011000 { - compatible = "brcm,bcm11351-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "uartb4", - "ssp0", - "ssp2", - "bsc1", - "bsc2", - "bsc3", - "pwm"; - }; - - ref_1m_clk: ref_1m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - }; - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_cx40_clk: ref_cx40 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - compatible = "fixed-clock"; - clock-frequency = <52000000>; - #clock-cells = <0>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - ref_208m_clk: ref_208m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - - var_208m_clk: var_208m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - - ref_312m_clk: ref_312m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <312000000>; - }; - - var_312m_clk: var_312m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <312000000>; - }; - }; - - usbotg: usb@3f120000 { - compatible = "snps,dwc2"; - reg = <0x3f120000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts deleted file mode 100644 index 8789fae178bf..000000000000 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2014 Broadcom Corporation - -/dts-v1/; - -#include - -#include "bcm21664.dtsi" - -/ { - model = "BCM21664 Garnet board"; - compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; -}; - -&sdio1 { - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio2 { - non-removable; - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio4 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uartb { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi deleted file mode 100644 index 2eb7f5b0c1dc..000000000000 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2014 Broadcom Corporation - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "BCM21664 SoC"; - compatible = "brcm,bcm21664"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x35004178>; - reg = <1>; - }; - }; - - gic: interrupt-controller@3ff00100 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x3ff01000 0x1000>, - <0x3ff00100 0x100>; - }; - - smc@3404e000 { - compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; - reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ - }; - - uartb: serial@3e000000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e000000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb2: serial@3e001000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e001000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb3: serial@3e002000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e002000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - L2: cache-controller@3ff20000 { - compatible = "arm,pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - brcm,resetmgr@35001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x35001f00 0x24>; - }; - - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1c>; - interrupts = ; - clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; - }; - - gpio: gpio@35003000 { - compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x524>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - sdio1: mmc@3f180000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f180000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: mmc@3f190000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f190000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: mmc@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: mmc@3f1b0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1b0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - bsc1: i2c@3e016000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e016000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - bsc2: i2c@3e017000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e017000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - bsc3: i2c@3e018000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e018000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - bsc4: i2c@3e01c000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e01c000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed clocks are defined before CCUs whose - * clocks may depend on them. - */ - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - root_ccu: root_ccu@35001000 { - compatible = "brcm,bcm21664-root-ccu"; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - aon_ccu: aon_ccu@35002000 { - compatible = "brcm,bcm21664-aon-ccu"; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer"; - }; - - master_ccu: master_ccu@3f001000 { - compatible = "brcm,bcm21664-master-ccu"; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "sdio1_sleep", - "sdio2_sleep", - "sdio3_sleep", - "sdio4_sleep"; - }; - - slave_ccu: slave_ccu@3e011000 { - compatible = "brcm,bcm21664-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "bsc1", - "bsc2", - "bsc3", - "bsc4"; - }; - }; - - usbotg: usb@3f120000 { - compatible = "snps,dwc2"; - reg = <0x3f120000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts deleted file mode 100644 index ace77709f468..000000000000 --- a/arch/arm/boot/dts/bcm23550-sparrow.dts +++ /dev/null @@ -1,81 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include - -#include "bcm23550.dtsi" - -/ { - model = "BCM23550 Sparrow board"; - compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550"; - - chosen { - stdout-path = "/slaves@3e000000/serial@0:115200n8"; - bootargs = "console=ttyS0,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&uartb { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&sdio1 { - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio2 { - non-removable; - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio4 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi deleted file mode 100644 index 445eadb8d871..000000000000 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ /dev/null @@ -1,414 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* BCM23550 and BCM21664 have almost identical clocks */ -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "BCM23550 SoC"; - compatible = "brcm,bcm23550"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <1>; - clock-frequency = <1000000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <2>; - clock-frequency = <1000000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <3>; - clock-frequency = <1000000000>; - }; - }; - - /* Hub bus */ - hub@34000000 { - compatible = "simple-bus"; - ranges = <0 0x34000000 0x102f83ac>; - #address-cells = <1>; - #size-cells = <1>; - - smc@4e000 { - compatible = "brcm,bcm23550-smc", "brcm,kona-smc"; - reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ - }; - - resetmgr: reset-controller@1001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x01001f00 0x24>; - }; - - gpio: gpio@1003000 { - compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; - reg = <0x01003000 0x524>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - timer@1006000 { - compatible = "brcm,kona-timer"; - reg = <0x01006000 0x1c>; - interrupts = ; - clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; - }; - }; - - /* Slaves bus */ - slaves@3e000000 { - compatible = "simple-bus"; - ranges = <0 0x3e000000 0x0001c070>; - #address-cells = <1>; - #size-cells = <1>; - - uartb: serial@0 { - compatible = "snps,dw-apb-uart"; - reg = <0x00000000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb2: serial@1000 { - compatible = "snps,dw-apb-uart"; - reg = <0x00001000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uartb3: serial@2000 { - compatible = "snps,dw-apb-uart"; - reg = <0x00002000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - bsc1: i2c@16000 { - compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; - reg = <0x00016000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - bsc2: i2c@17000 { - compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; - reg = <0x00017000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - bsc3: i2c@18000 { - compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; - reg = <0x00018000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - bsc4: i2c@1c000 { - compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; - reg = <0x0001c000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; - status = "disabled"; - }; - }; - - /* Apps bus */ - apps@3e300000 { - compatible = "simple-bus"; - ranges = <0 0x3e300000 0x01b77000>; - #address-cells = <1>; - #size-cells = <1>; - - usbotg: usb@e20000 { - compatible = "snps,dwc2"; - reg = <0x00e20000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@e30000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x00e30000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; - - sdio1: mmc@e80000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00e80000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: mmc@e90000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00e90000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: mmc@ea0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00ea0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: mmc@eb0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00eb0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - cdc: cdc@1b0e000 { - compatible = "brcm,bcm23550-cdc"; - reg = <0x01b0e000 0x78>; - }; - - gic: interrupt-controller@1b21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x01b21000 0x1000>, - <0x01b22000 0x1000>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed clocks are defined before CCUs whose - * clocks may depend on them. - */ - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - root_ccu: root_ccu@35001000 { - compatible = "brcm,bcm21664-root-ccu"; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - aon_ccu: aon_ccu@35002000 { - compatible = "brcm,bcm21664-aon-ccu"; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer"; - }; - - slave_ccu: slave_ccu@3e011000 { - compatible = "brcm,bcm21664-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "bsc1", - "bsc2", - "bsc3", - "bsc4"; - }; - - master_ccu: master_ccu@3f001000 { - compatible = "brcm,bcm21664-master-ccu"; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "sdio1_sleep", - "sdio2_sleep", - "sdio3_sleep", - "sdio4_sleep"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts deleted file mode 100644 index d5f8823230db..000000000000 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ /dev/null @@ -1,243 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2711.dtsi" -#include "bcm2711-rpi.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-peripheral.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; - model = "Raspberry Pi 4 Model B"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - sd_io_1v8_reg: regulator-sd-io-1v8 { - compatible = "regulator-gpio"; - regulator-name = "vdd-sd-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-settling-time-us = <5000>; - gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1>, - <3300000 0x0>; - status = "okay"; - }; - - sd_vcc_reg: regulator-sd-vcc { - compatible = "regulator-fixed"; - regulator-name = "vcc-sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&bt { - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -}; - -&ddc0 { - status = "okay"; -}; - -&ddc1 { - status = "okay"; -}; - -&expgpio { - gpio-line-names = "BT_ON", /* 0 */ - "WL_ON", - "PWR_LED_OFF", - "GLOBAL_RESET", - "VDD_SD_IO_SEL", - "CAM_GPIO", /* 5 */ - "SD_PWR_ON", - ""; -}; - -&gpio { - /* - * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", /* 0 */ - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", /* 5 */ - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", /* 10 */ - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", /* 15 */ - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", /* 20 */ - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", /* 25 */ - "GPIO26", - "GPIO27", - "RGMII_MDIO", - "RGMIO_MDC", - /* Used by BT module */ - "CTS0", /* 30 */ - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", /* 35 */ - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - /* Shared with SPI flash */ - "PWM0_MISO", /* 40 */ - "PWM1_MOSI", - "STATUS_LED_G_CLK", - "SPIFLASH_CE_N", - "SDA0", - "SCL0", /* 45 */ - "RGMII_RXCLK", - "RGMII_RXCTL", - "RGMII_RXD0", - "RGMII_RXD1", - "RGMII_RXD2", /* 50 */ - "RGMII_RXD3", - "RGMII_TXCLK", - "RGMII_TXCTL", - "RGMII_TXD0", - "RGMII_TXD1", /* 55 */ - "RGMII_TXD2", - "RGMII_TXD3"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdmi1 { - status = "okay"; -}; - -&led_act { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led_pwr: led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pixelvalve0 { - status = "okay"; -}; - -&pixelvalve1 { - status = "okay"; -}; - -&pixelvalve2 { - status = "okay"; -}; - -&pixelvalve4 { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; - status = "okay"; -}; - -/* EMMC2 is used to drive the SD card */ -&emmc2 { - vqmmc-supply = <&sd_io_1v8_reg>; - vmmc-supply = <&sd_vcc_reg>; - broken-cd; - status = "okay"; -}; - -&genet { - phy-handle = <&phy1>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -&genet_mdio { - phy1: ethernet-phy@1 { - /* No PHY interrupt */ - reg = <0x1>; - }; -}; - -&pcie0 { - pci@0,0 { - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - reg = <0 0 0 0 0>; - - usb@0,0 { - reg = <0 0 0 0 0>; - resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; - }; - }; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; - uart-has-rtscts; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -&vc4 { - status = "okay"; -}; - -&vec { - status = "disabled"; -}; - -&wifi_pwrseq { - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts deleted file mode 100644 index 1ab8184302db..000000000000 --- a/arch/arm/boot/dts/bcm2711-rpi-400.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2711-rpi-4-b.dts" - -/ { - compatible = "raspberrypi,400", "brcm,bcm2711"; - model = "Raspberry Pi 400"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&expgpio { - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_OFF", - "GLOBAL_RESET", - "VDD_SD_IO_SEL", - "GLOBAL_SHUTDOWN", - "SD_PWR_ON", - "SHUTDOWN_REQUEST"; -}; - -&genet_mdio { - clock-frequency = <1950000>; -}; - -&led_pwr { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -}; - -&leds { - /delete-node/ led_act; -}; - -&pm { - /delete-property/ system-power-controller; -}; diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts deleted file mode 100644 index d7ba02f586d3..000000000000 --- a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2711-rpi-cm4.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - model = "Raspberry Pi Compute Module 4 IO Board"; -}; - -&ddc0 { - status = "okay"; -}; - -&ddc1 { - status = "okay"; -}; - -&gpio { - /* - * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "RGMII_MDIO", - "RGMIO_MDC", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - /* Shared with SPI flash */ - "PWM0_MISO", - "PWM1_MOSI", - "STATUS_LED_G_CLK", - "SPIFLASH_CE_N", - "SDA0", - "SCL0", - "RGMII_RXCLK", - "RGMII_RXCTL", - "RGMII_RXD0", - "RGMII_RXD1", - "RGMII_RXD2", - "RGMII_RXD3", - "RGMII_TXCLK", - "RGMII_TXCTL", - "RGMII_TXD0", - "RGMII_TXD1", - "RGMII_TXD2", - "RGMII_TXD3"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdmi1 { - status = "okay"; -}; - -&genet { - status = "okay"; -}; - -&led_act { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pixelvalve0 { - status = "okay"; -}; - -&pixelvalve1 { - status = "okay"; -}; - -&pixelvalve2 { - status = "okay"; -}; - -&pixelvalve4 { - status = "okay"; -}; - -&vc4 { - status = "okay"; -}; - -&vec { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi b/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi deleted file mode 100644 index 48e63ab7848c..000000000000 --- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2711.dtsi" -#include "bcm2711-rpi.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,4-compute-module", "brcm,bcm2711"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - sd_io_1v8_reg: regulator-sd-io-1v8 { - compatible = "regulator-gpio"; - regulator-name = "vdd-sd-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-settling-time-us = <5000>; - gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1>, - <3300000 0x0>; - status = "okay"; - }; - - sd_vcc_reg: regulator-sd-vcc { - compatible = "regulator-fixed"; - regulator-name = "vcc-sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&bt { - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -}; - -/* EMMC2 is used to drive the eMMC */ -&emmc2 { - bus-width = <8>; - vqmmc-supply = <&sd_io_1v8_reg>; - vmmc-supply = <&sd_vcc_reg>; - broken-cd; - /* Even the IP block is limited to 100 MHz - * this provides a throughput gain - */ - mmc-hs200-1_8v; - status = "okay"; -}; - -&expgpio { - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_OFF", - "ANT1", - "VDD_SD_IO_SEL", - "CAM_GPIO", - "SD_PWR_ON", - "ANT2"; - - ant1: ant1-hog { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; - /* internal antenna enabled */ - output-high; - line-name = "ant1"; - }; - - ant2: ant2-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - /* external antenna disabled */ - output-low; - line-name = "ant2"; - }; -}; - -&genet { - phy-handle = <&phy1>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -&genet_mdio { - phy1: ethernet-phy@0 { - /* No PHY interrupt */ - reg = <0x0>; - }; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; - uart-has-rtscts; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -&wifi_pwrseq { - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi deleted file mode 100644 index 98817a6675b9..000000000000 --- a/arch/arm/boot/dts/bcm2711-rpi.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm2835-rpi.dtsi" - -#include - -/ { - /* Will be filled by the bootloader */ - memory@0 { - device_type = "memory"; - reg = <0 0 0>; - }; - - aliases { - emmc2bus = &emmc2bus; - ethernet0 = &genet; - pcie0 = &pcie0; - blconfig = &blconfig; - }; -}; - -&firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; - - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - status = "okay"; - }; - - reset: reset { - compatible = "raspberrypi,firmware-reset"; - #reset-cells = <1>; - }; -}; - -&hdmi0 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; -}; - -&hdmi1 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; -}; - -&hvs { - clocks = <&firmware_clocks 4>; -}; - -&rmem { - /* - * RPi4's co-processor will copy the board's bootloader configuration - * into memory for the OS to consume. It'll also update this node with - * its placement information. - */ - blconfig: nvram@0 { - compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x0>; - no-map; - status = "disabled"; - }; -}; - -&v3d { - clocks = <&firmware_clocks 5>; -}; - -&vchiq { - interrupts = ; -}; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi deleted file mode 100644 index 097e9f252235..000000000000 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ /dev/null @@ -1,1172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm283x.dtsi" - -#include -#include - -/ { - compatible = "brcm,bcm2711"; - - #address-cells = <2>; - #size-cells = <1>; - - interrupt-parent = <&gicv2>; - - vc4: gpu { - compatible = "brcm,bcm2711-vc5"; - status = "disabled"; - }; - - clk_27MHz: clk-27M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - clock-output-names = "27MHz-clock"; - }; - - clk_108MHz: clk-108M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <108000000>; - clock-output-names = "108MHz-clock"; - }; - - soc { - /* - * Defined ranges: - * Common BCM283x peripherals - * BCM2711-specific peripherals - * ARM-local peripherals - */ - ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, - <0x7c000000 0x0 0xfc000000 0x02000000>, - <0x40000000 0x0 0xff800000 0x00800000>; - /* Emulate a contiguous 30-bit address range for DMA */ - dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; - - /* - * This node is the provider for the enable-method for - * bringing up secondary cores. - */ - local_intc: interrupt-controller@40000000 { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - }; - - gicv2: interrupt-controller@40041000 { - interrupt-controller; - #interrupt-cells = <3>; - compatible = "arm,gic-400"; - reg = <0x40041000 0x1000>, - <0x40042000 0x2000>, - <0x40044000 0x2000>, - <0x40046000 0x2000>; - interrupts = ; - }; - - avs_monitor: avs-monitor@7d5d2000 { - compatible = "brcm,bcm2711-avs-monitor", - "syscon", "simple-mfd"; - reg = <0x7d5d2000 0xf00>; - - thermal: thermal { - compatible = "brcm,bcm2711-thermal"; - #thermal-sensor-cells = <0>; - }; - }; - - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xb00>; - interrupts = , - , - , - , - , - , - , - /* DMA lite 7 - 10 */ - , - , - , - ; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10"; - #dma-cells = <1>; - brcm,dma-channel-mask = <0x07f5>; - }; - - pm: watchdog@7e100000 { - compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x7e100000 0x114>, - <0x7e00a000 0x24>, - <0x7ec11000 0x20>; - reg-names = "pm", "asb", "rpivid_asb"; - clocks = <&clocks BCM2835_CLOCK_V3D>, - <&clocks BCM2835_CLOCK_PERI_IMAGE>, - <&clocks BCM2835_CLOCK_H264>, - <&clocks BCM2835_CLOCK_ISP>; - clock-names = "v3d", "peri_image", "h264", "isp"; - system-power-controller; - }; - - rng@7e104000 { - compatible = "brcm,bcm2711-rng200"; - reg = <0x7e104000 0x28>; - }; - - uart2: serial@7e201400 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201400 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - uart3: serial@7e201600 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201600 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - uart4: serial@7e201800 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201800 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - uart5: serial@7e201a00 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201a00 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - spi3: spi@7e204600 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204600 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@7e204800 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204800 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@7e204a00 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204a00 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@7e204c00 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204c00 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@7e205600 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205600 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@7e205800 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205800 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@7e205a00 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205a00 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@7e205c00 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205c00 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pixelvalve0: pixelvalve@7e206000 { - compatible = "brcm,bcm2711-pixelvalve0"; - reg = <0x7e206000 0x100>; - interrupts = ; - status = "disabled"; - }; - - pixelvalve1: pixelvalve@7e207000 { - compatible = "brcm,bcm2711-pixelvalve1"; - reg = <0x7e207000 0x100>; - interrupts = ; - status = "disabled"; - }; - - pixelvalve2: pixelvalve@7e20a000 { - compatible = "brcm,bcm2711-pixelvalve2"; - reg = <0x7e20a000 0x100>; - interrupts = ; - status = "disabled"; - }; - - pwm1: pwm@7e20c800 { - compatible = "brcm,bcm2835-pwm"; - reg = <0x7e20c800 0x28>; - clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clock-rates = <10000000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pixelvalve4: pixelvalve@7e216000 { - compatible = "brcm,bcm2711-pixelvalve4"; - reg = <0x7e216000 0x100>; - interrupts = ; - status = "disabled"; - }; - - hvs: hvs@7e400000 { - compatible = "brcm,bcm2711-hvs"; - reg = <0x7e400000 0x8000>; - interrupts = ; - }; - - pixelvalve3: pixelvalve@7ec12000 { - compatible = "brcm,bcm2711-pixelvalve3"; - reg = <0x7ec12000 0x100>; - interrupts = ; - status = "disabled"; - }; - - vec: vec@7ec13000 { - compatible = "brcm,bcm2711-vec"; - reg = <0x7ec13000 0x1000>; - clocks = <&clocks BCM2835_CLOCK_VEC>; - interrupts = ; - status = "disabled"; - }; - - dvp: clock@7ef00000 { - compatible = "brcm,brcm2711-dvp"; - reg = <0x7ef00000 0x10>; - clocks = <&clk_108MHz>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - aon_intr: interrupt-controller@7ef00100 { - compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; - reg = <0x7ef00100 0x30>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - }; - - hdmi0: hdmi@7ef00700 { - compatible = "brcm,bcm2711-hdmi0"; - reg = <0x7ef00700 0x300>, - <0x7ef00300 0x200>, - <0x7ef00f00 0x80>, - <0x7ef00f80 0x80>, - <0x7ef01b00 0x200>, - <0x7ef01f00 0x400>, - <0x7ef00200 0x80>, - <0x7ef04300 0x100>, - <0x7ef20000 0x100>; - reg-names = "hdmi", - "dvp", - "phy", - "rm", - "packet", - "metadata", - "csc", - "cec", - "hd"; - clock-names = "hdmi", "bvb", "audio", "cec"; - resets = <&dvp 0>; - interrupt-parent = <&aon_intr>; - interrupts = <0>, <1>, <2>, - <3>, <4>, <5>; - interrupt-names = "cec-tx", "cec-rx", "cec-low", - "wakeup", "hpd-connected", "hpd-removed"; - ddc = <&ddc0>; - dmas = <&dma 10>; - dma-names = "audio-rx"; - status = "disabled"; - }; - - ddc0: i2c@7ef04500 { - compatible = "brcm,bcm2711-hdmi-i2c"; - reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; - reg-names = "bsc", "auto-i2c"; - clock-frequency = <97500>; - status = "disabled"; - }; - - hdmi1: hdmi@7ef05700 { - compatible = "brcm,bcm2711-hdmi1"; - reg = <0x7ef05700 0x300>, - <0x7ef05300 0x200>, - <0x7ef05f00 0x80>, - <0x7ef05f80 0x80>, - <0x7ef06b00 0x200>, - <0x7ef06f00 0x400>, - <0x7ef00280 0x80>, - <0x7ef09300 0x100>, - <0x7ef20000 0x100>; - reg-names = "hdmi", - "dvp", - "phy", - "rm", - "packet", - "metadata", - "csc", - "cec", - "hd"; - ddc = <&ddc1>; - clock-names = "hdmi", "bvb", "audio", "cec"; - resets = <&dvp 1>; - interrupt-parent = <&aon_intr>; - interrupts = <8>, <7>, <6>, - <9>, <10>, <11>; - interrupt-names = "cec-tx", "cec-rx", "cec-low", - "wakeup", "hpd-connected", "hpd-removed"; - dmas = <&dma 17>; - dma-names = "audio-rx"; - status = "disabled"; - }; - - ddc1: i2c@7ef09500 { - compatible = "brcm,bcm2711-hdmi-i2c"; - reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; - reg-names = "bsc", "auto-i2c"; - clock-frequency = <97500>; - status = "disabled"; - }; - }; - - /* - * emmc2 has different DMA constraints based on SoC revisions. It was - * moved into its own bus, so as for RPi4's firmware to update them. - * The firmware will find whether the emmc2bus alias is defined, and if - * so, it'll edit the dma-ranges property below accordingly. - */ - emmc2bus: emmc2bus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; - dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; - - emmc2: mmc@7e340000 { - compatible = "brcm,bcm2711-emmc2"; - reg = <0x0 0x7e340000 0x100>; - interrupts = ; - clocks = <&clocks BCM2711_CLOCK_EMMC2>; - status = "disabled"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - /* This only applies to the ARMv7 stub */ - arm,cpu-registers-not-fw-configured; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit - - /* Source for d/i-cache-line-size and d/i-cache-sets - * https://developer.arm.com/documentation/100095/0003 - * /Level-1-Memory-System/About-the-L1-memory-system?lang=en - * Source for d/i-cache-size - * https://www.raspberrypi.com/documentation/computers - * /processors.html#bcm2711 - */ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000d8>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e8>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000f0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set - next-level-cache = <&l2>; - }; - - /* Source for d/i-cache-line-size and d/i-cache-sets - * https://developer.arm.com/documentation/100095/0003 - * /Level-2-Memory-System/About-the-L2-memory-system?lang=en - * Source for d/i-cache-size - * https://www.raspberrypi.com/documentation/computers - * /processors.html#bcm2711 - */ - l2: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set - cache-level = <2>; - }; - }; - - scb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, - <0x6 0x00000000 0x6 0x00000000 0x40000000>; - - pcie0: pcie@7d500000 { - compatible = "brcm,bcm2711-pcie"; - reg = <0x0 0x7d500000 0x9310>; - device_type = "pci"; - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - interrupts = , - ; - interrupt-names = "pcie", "msi"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 - IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gicv2 GIC_SPI 144 - IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gicv2 GIC_SPI 145 - IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gicv2 GIC_SPI 146 - IRQ_TYPE_LEVEL_HIGH>; - msi-controller; - msi-parent = <&pcie0>; - - ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 - 0x0 0x04000000>; - /* - * The wrapper around the PCIe block has a bug - * preventing it from accessing beyond the first 3GB of - * memory. - */ - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 - 0x0 0xc0000000>; - brcm,enable-ssc; - }; - - genet: ethernet@7d580000 { - compatible = "brcm,bcm2711-genet-v5"; - reg = <0x0 0x7d580000 0x10000>; - #address-cells = <0x1>; - #size-cells = <0x1>; - interrupts = , - ; - status = "disabled"; - - genet_mdio: mdio@e14 { - compatible = "brcm,genet-mdio-v5"; - reg = <0xe14 0x8>; - reg-names = "mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - }; - - v3d: gpu@7ec00000 { - compatible = "brcm,2711-v3d"; - reg = <0x0 0x7ec00000 0x4000>, - <0x0 0x7ec04000 0x4000>; - reg-names = "hub", "core0"; - - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; - resets = <&pm BCM2835_RESET_V3D>; - interrupts = ; - }; - }; -}; - -&clk_osc { - clock-frequency = <54000000>; -}; - -&clocks { - compatible = "brcm,bcm2711-cprman"; -}; - -&cpu_thermal { - coefficients = <(-487) 410040>; - thermal-sensors = <&thermal>; -}; - -&dsi0 { - interrupts = ; -}; - -&dsi1 { - interrupts = ; - compatible = "brcm,bcm2711-dsi1"; -}; - -&gpio { - compatible = "brcm,bcm2711-gpio"; - interrupts = , - , - , - ; - - gpio-ranges = <&gpio 0 0 58>; - - gpclk0_gpio49: gpclk0-gpio49 { - pin-gpclk { - pins = "gpio49"; - function = "alt1"; - bias-disable; - }; - }; - gpclk1_gpio50: gpclk1-gpio50 { - pin-gpclk { - pins = "gpio50"; - function = "alt1"; - bias-disable; - }; - }; - gpclk2_gpio51: gpclk2-gpio51 { - pin-gpclk { - pins = "gpio51"; - function = "alt1"; - bias-disable; - }; - }; - - i2c0_gpio46: i2c0-gpio46 { - pin-sda { - function = "alt0"; - pins = "gpio46"; - bias-pull-up; - }; - pin-scl { - function = "alt0"; - pins = "gpio47"; - bias-disable; - }; - }; - i2c1_gpio46: i2c1-gpio46 { - pin-sda { - function = "alt1"; - pins = "gpio46"; - bias-pull-up; - }; - pin-scl { - function = "alt1"; - pins = "gpio47"; - bias-disable; - }; - }; - i2c3_gpio2: i2c3-gpio2 { - pin-sda { - function = "alt5"; - pins = "gpio2"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio3"; - bias-disable; - }; - }; - i2c3_gpio4: i2c3-gpio4 { - pin-sda { - function = "alt5"; - pins = "gpio4"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio5"; - bias-disable; - }; - }; - i2c4_gpio6: i2c4-gpio6 { - pin-sda { - function = "alt5"; - pins = "gpio6"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio7"; - bias-disable; - }; - }; - i2c4_gpio8: i2c4-gpio8 { - pin-sda { - function = "alt5"; - pins = "gpio8"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio9"; - bias-disable; - }; - }; - i2c5_gpio10: i2c5-gpio10 { - pin-sda { - function = "alt5"; - pins = "gpio10"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio11"; - bias-disable; - }; - }; - i2c5_gpio12: i2c5-gpio12 { - pin-sda { - function = "alt5"; - pins = "gpio12"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio13"; - bias-disable; - }; - }; - i2c6_gpio0: i2c6-gpio0 { - pin-sda { - function = "alt5"; - pins = "gpio0"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio1"; - bias-disable; - }; - }; - i2c6_gpio22: i2c6-gpio22 { - pin-sda { - function = "alt5"; - pins = "gpio22"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio23"; - bias-disable; - }; - }; - i2c_slave_gpio8: i2c-slave-gpio8 { - pins-i2c-slave { - pins = "gpio8", - "gpio9", - "gpio10", - "gpio11"; - function = "alt3"; - }; - }; - - jtag_gpio48: jtag-gpio48 { - pins-jtag { - pins = "gpio48", - "gpio49", - "gpio50", - "gpio51", - "gpio52", - "gpio53"; - function = "alt4"; - }; - }; - - mii_gpio28: mii-gpio28 { - pins-mii { - pins = "gpio28", - "gpio29", - "gpio30", - "gpio31"; - function = "alt4"; - }; - }; - mii_gpio36: mii-gpio36 { - pins-mii { - pins = "gpio36", - "gpio37", - "gpio38", - "gpio39"; - function = "alt5"; - }; - }; - - pcm_gpio50: pcm-gpio50 { - pins-pcm { - pins = "gpio50", - "gpio51", - "gpio52", - "gpio53"; - function = "alt2"; - }; - }; - - pwm0_0_gpio12: pwm0-0-gpio12 { - pin-pwm { - pins = "gpio12"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_0_gpio18: pwm0-0-gpio18 { - pin-pwm { - pins = "gpio18"; - function = "alt5"; - bias-disable; - }; - }; - pwm1_0_gpio40: pwm1-0-gpio40 { - pin-pwm { - pins = "gpio40"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_1_gpio13: pwm0-1-gpio13 { - pin-pwm { - pins = "gpio13"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_1_gpio19: pwm0-1-gpio19 { - pin-pwm { - pins = "gpio19"; - function = "alt5"; - bias-disable; - }; - }; - pwm1_1_gpio41: pwm1-1-gpio41 { - pin-pwm { - pins = "gpio41"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_1_gpio45: pwm0-1-gpio45 { - pin-pwm { - pins = "gpio45"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_0_gpio52: pwm0-0-gpio52 { - pin-pwm { - pins = "gpio52"; - function = "alt1"; - bias-disable; - }; - }; - pwm0_1_gpio53: pwm0-1-gpio53 { - pin-pwm { - pins = "gpio53"; - function = "alt1"; - bias-disable; - }; - }; - - rgmii_gpio35: rgmii-gpio35 { - pin-start-stop { - pins = "gpio35"; - function = "alt4"; - }; - pin-rx-ok { - pins = "gpio36"; - function = "alt4"; - }; - }; - rgmii_irq_gpio34: rgmii-irq-gpio34 { - pin-irq { - pins = "gpio34"; - function = "alt5"; - }; - }; - rgmii_irq_gpio39: rgmii-irq-gpio39 { - pin-irq { - pins = "gpio39"; - function = "alt4"; - }; - }; - rgmii_mdio_gpio28: rgmii-mdio-gpio28 { - pins-mdio { - pins = "gpio28", - "gpio29"; - function = "alt5"; - }; - }; - rgmii_mdio_gpio37: rgmii-mdio-gpio37 { - pins-mdio { - pins = "gpio37", - "gpio38"; - function = "alt4"; - }; - }; - - spi0_gpio46: spi0-gpio46 { - pins-spi { - pins = "gpio46", - "gpio47", - "gpio48", - "gpio49"; - function = "alt2"; - }; - }; - spi2_gpio46: spi2-gpio46 { - pins-spi { - pins = "gpio46", - "gpio47", - "gpio48", - "gpio49", - "gpio50"; - function = "alt5"; - }; - }; - spi3_gpio0: spi3-gpio0 { - pins-spi { - pins = "gpio0", - "gpio1", - "gpio2", - "gpio3"; - function = "alt3"; - }; - }; - spi4_gpio4: spi4-gpio4 { - pins-spi { - pins = "gpio4", - "gpio5", - "gpio6", - "gpio7"; - function = "alt3"; - }; - }; - spi5_gpio12: spi5-gpio12 { - pins-spi { - pins = "gpio12", - "gpio13", - "gpio14", - "gpio15"; - function = "alt3"; - }; - }; - spi6_gpio18: spi6-gpio18 { - pins-spi { - pins = "gpio18", - "gpio19", - "gpio20", - "gpio21"; - function = "alt3"; - }; - }; - - uart2_gpio0: uart2-gpio0 { - pin-tx { - pins = "gpio0"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio1"; - function = "alt4"; - bias-pull-up; - }; - }; - uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 { - pin-cts { - pins = "gpio2"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio3"; - function = "alt4"; - bias-disable; - }; - }; - uart3_gpio4: uart3-gpio4 { - pin-tx { - pins = "gpio4"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio5"; - function = "alt4"; - bias-pull-up; - }; - }; - uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 { - pin-cts { - pins = "gpio6"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio7"; - function = "alt4"; - bias-disable; - }; - }; - uart4_gpio8: uart4-gpio8 { - pin-tx { - pins = "gpio8"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio9"; - function = "alt4"; - bias-pull-up; - }; - }; - uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 { - pin-cts { - pins = "gpio10"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio11"; - function = "alt4"; - bias-disable; - }; - }; - uart5_gpio12: uart5-gpio12 { - pin-tx { - pins = "gpio12"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio13"; - function = "alt4"; - bias-pull-up; - }; - }; - uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 { - pin-cts { - pins = "gpio14"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio15"; - function = "alt4"; - bias-disable; - }; - }; -}; - -&rmem { - #address-cells = <2>; -}; - -&cma { - /* - * arm64 reserves the CMA by default somewhere in ZONE_DMA32, - * that's not good enough for the BCM2711 as some devices can - * only address the lower 1G of memory (ZONE_DMA). - */ - alloc-ranges = <0x0 0x00000000 0x40000000>; -}; - -&i2c0 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - interrupts = ; -}; - -&i2c1 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - interrupts = ; -}; - -&mailbox { - interrupts = ; -}; - -&sdhci { - interrupts = ; -}; - -&sdhost { - interrupts = ; -}; - -&spi { - interrupts = ; -}; - -&spi1 { - interrupts = ; -}; - -&spi2 { - interrupts = ; -}; - -&system_timer { - interrupts = , - , - , - ; -}; - -&txp { - interrupts = ; -}; - -&uart0 { - interrupts = ; -}; - -&uart1 { - interrupts = ; -}; - -&usb { - interrupts = ; -}; - -&vec { - compatible = "brcm,bcm2711-vec"; - interrupts = ; -}; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts deleted file mode 100644 index 0a8ad1d673d8..000000000000 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2013 Broadcom Corporation - -/dts-v1/; - -#include - -#include "bcm11351.dtsi" - -/ { - model = "BCM28155 AP board"; - compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - serial@3e000000 { - status = "okay"; - }; - - i2c@3e016000 { - clock-frequency = <400000>; - status = "okay"; - }; - - i2c@3e017000 { - clock-frequency = <400000>; - status = "okay"; - }; - - i2c@3e018000 { - clock-frequency = <400000>; - status = "okay"; - }; - - i2c@3500d000 { - clock-frequency = <100000>; - status = "okay"; - - pmu: pmu@8 { - reg = <0x08>; - }; - }; - - sdio2: mmc@3f190000 { - non-removable; - max-frequency = <48000000>; - vmmc-supply = <&camldo1_reg>; - vqmmc-supply = <&iosr1_reg>; - status = "okay"; - }; - - sdio4: mmc@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <&sdldo_reg>; - vqmmc-supply = <&sdxldo_reg>; - status = "okay"; - }; - - pwm: pwm@3e01a000 { - status = "okay"; - }; - - usbotg: usb@3f120000 { - vusb_d-supply = <&usbldo_reg>; - vusb_a-supply = <&iosr1_reg>; - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; - -#include "bcm59056.dtsi" - -&pmu { - compatible = "brcm,bcm59056"; - interrupts = ; - regulators { - camldo1_reg: camldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdldo_reg: sdldo { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - sdxldo_reg: sdxldo { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - }; - - usbldo_reg: usbldo { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - iosr1_reg: iosr1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi deleted file mode 100644 index bb7e8f7facaf..000000000000 --- a/arch/arm/boot/dts/bcm2835-common.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* This include file covers the common peripherals and configuration between - * bcm2835, bcm2836 and bcm2837 implementations. - */ - -/ { - interrupt-parent = <&intc>; - - soc { - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - /* dma channel 11-14 share one irq */ - <1 27>, - <1 27>, - <1 27>, - <1 27>, - /* unused shared irq for all channels */ - <1 28>; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10", - "dma11", - "dma12", - "dma13", - "dma14", - "dma-shared-all"; - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; - }; - - intc: interrupt-controller@7e00b200 { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x7e100000 0x114>, - <0x7e00a000 0x24>; - reg-names = "pm", "asb"; - clocks = <&clocks BCM2835_CLOCK_V3D>, - <&clocks BCM2835_CLOCK_PERI_IMAGE>, - <&clocks BCM2835_CLOCK_H264>, - <&clocks BCM2835_CLOCK_ISP>; - clock-names = "v3d", "peri_image", "h264", "isp"; - system-power-controller; - }; - - rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; - }; - - pixelvalve@7e206000 { - compatible = "brcm,bcm2835-pixelvalve0"; - reg = <0x7e206000 0x100>; - interrupts = <2 13>; /* pwa0 */ - }; - - pixelvalve@7e207000 { - compatible = "brcm,bcm2835-pixelvalve1"; - reg = <0x7e207000 0x100>; - interrupts = <2 14>; /* pwa1 */ - }; - - thermal: thermal@7e212000 { - compatible = "brcm,bcm2835-thermal"; - reg = <0x7e212000 0x8>; - clocks = <&clocks BCM2835_CLOCK_TSENS>; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@7e805000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e805000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; - - vec: vec@7e806000 { - compatible = "brcm,bcm2835-vec"; - reg = <0x7e806000 0x1000>; - clocks = <&clocks BCM2835_CLOCK_VEC>; - interrupts = <2 27>; - status = "disabled"; - }; - - pixelvalve@7e807000 { - compatible = "brcm,bcm2835-pixelvalve2"; - reg = <0x7e807000 0x100>; - interrupts = <2 10>; /* pixelvalve */ - }; - - hdmi: hdmi@7e902000 { - compatible = "brcm,bcm2835-hdmi"; - reg = <0x7e902000 0x600>, - <0x7e808000 0x100>; - interrupts = <2 8>, <2 9>; - ddc = <&i2c2>; - clocks = <&clocks BCM2835_PLLH_PIX>, - <&clocks BCM2835_CLOCK_HSM>; - clock-names = "pixel", "hdmi"; - dmas = <&dma 17>; - dma-names = "audio-rx"; - status = "disabled"; - }; - - v3d: v3d@7ec00000 { - compatible = "brcm,bcm2835-v3d"; - reg = <0x7ec00000 0x1000>; - interrupts = <1 10>; - }; - - vc4: gpu { - compatible = "brcm,bcm2835-vc4"; - }; - }; -}; - -&cpu_thermal { - thermal-sensors = <&thermal>; -}; - -&gpio { - i2c_slave_gpio18: i2c-slave-gpio18 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; - - jtag_gpio4: jtag-gpio4 { - brcm,pins = <4 5 6 12 13>; - brcm,function = ; - }; - - pwm0_gpio12: pwm0-gpio12 { - brcm,pins = <12>; - brcm,function = ; - }; - pwm0_gpio18: pwm0-gpio18 { - brcm,pins = <18>; - brcm,function = ; - }; - pwm0_gpio40: pwm0-gpio40 { - brcm,pins = <40>; - brcm,function = ; - }; - pwm1_gpio13: pwm1-gpio13 { - brcm,pins = <13>; - brcm,function = ; - }; - pwm1_gpio19: pwm1-gpio19 { - brcm,pins = <19>; - brcm,function = ; - }; - pwm1_gpio41: pwm1-gpio41 { - brcm,pins = <41>; - brcm,function = ; - }; - pwm1_gpio45: pwm1-gpio45 { - brcm,pins = <45>; - brcm,function = ; - }; -}; - -&i2s { - dmas = <&dma 2>, <&dma 3>; - dma-names = "tx", "rx"; -}; - -&sdhost { - dmas = <&dma 13>; - dma-names = "rx-tx"; -}; - -&spi { - dmas = <&dma 6>, <&dma 7>; - dma-names = "tx", "rx"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts deleted file mode 100644 index 02ce817868ba..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model A+"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; -}; - -&gpio { - /* - * This is based on the unreleased schematic for the Model A+. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "", /* GPIO30 */ - "", /* GPIO31 */ - "CAM_GPIO1", /* GPIO32 */ - "", /* GPIO33 */ - "", /* GPIO34 */ - "PWR_LOW_N", /* GPIO35 */ - "", /* GPIO36 */ - "", /* GPIO37 */ - "USB_LIMIT", /* GPIO38 */ - "", /* GPIO39 */ - "PWM0_OUT", /* GPIO40 */ - "CAM_GPIO0", /* GPIO41 */ - "", /* GPIO42 */ - "", /* GPIO43 */ - "", /* GPIO44 */ - "PWM1_OUT", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led-pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts deleted file mode 100644 index 3fdf60eb11dc..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-a", "brcm,bcm2835"; - model = "Raspberry Pi Model A"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf - * RPI00021 sheet 02 - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "SDA0", - "SCL0", - "SDA1", - "SCL1", - "GPIO_GCLK", - "CAM_GPIO1", - "LAN_RUN", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "", /* GPIO12 */ - "", /* GPIO13 */ - /* Serial port */ - "TXD0", - "RXD0", - "STATUS_LED_N", - "GPIO17", - "GPIO18", - "", /* GPIO19 */ - "", /* GPIO20 */ - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "", /* GPIO26 */ - "CAM_GPIO0", - /* Binary number representing build/revision */ - "CONFIG0", - "CONFIG1", - "CONFIG2", - "CONFIG3", - "", /* GPIO32 */ - "", /* GPIO33 */ - "", /* GPIO34 */ - "", /* GPIO35 */ - "", /* GPIO36 */ - "", /* GPIO37 */ - "", /* GPIO38 */ - "", /* GPIO39 */ - "PWM0_OUT", - "", /* GPIO41 */ - "", /* GPIO42 */ - "", /* GPIO43 */ - "", /* GPIO44 */ - "PWM1_OUT", - "HDMI_HPD_P", - "SD_CARD_DET", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; - - /* I2S interface */ - i2s_alt2: i2s_alt2 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts deleted file mode 100644 index 9956fd06a4b6..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model B+"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf - * RPI-BPLUS sheet 1 - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "", /* GPIO30 */ - "LAN_RUN", /* GPIO31 */ - "CAM_GPIO1", /* GPIO32 */ - "", /* GPIO33 */ - "", /* GPIO34 */ - "PWR_LOW_N", /* GPIO35 */ - "", /* GPIO36 */ - "", /* GPIO37 */ - "USB_LIMIT", /* GPIO38 */ - "", /* GPIO39 */ - "PWM0_OUT", /* GPIO40 */ - "CAM_GPIO0", /* GPIO41 */ - "", /* GPIO42 */ - "", /* GPIO43 */ - "ETH_CLK", /* GPIO44 */ - "PWM1_OUT", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led-pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts deleted file mode 100644 index 4e1770afb145..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; - model = "Raspberry Pi Model B rev2"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf - * RPI00022 sheet 02 - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "SDA0", - "SCL0", - "SDA1", - "SCL1", - "GPIO_GCLK", - "CAM_CLK", - "LAN_RUN", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "", /* GPIO12 */ - "", /* GPIO13 */ - /* Serial port */ - "TXD0", - "RXD0", - "STATUS_LED_N", - "GPIO17", - "GPIO18", - "", /* GPIO19 */ - "", /* GPIO20 */ - "CAM_GPIO", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "", /* GPIO26 */ - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "", /* GPIO32 */ - "", /* GPIO33 */ - "", /* GPIO34 */ - "", /* GPIO35 */ - "", /* GPIO36 */ - "", /* GPIO37 */ - "", /* GPIO38 */ - "", /* GPIO39 */ - "PWM0_OUT", - "", /* GPIO41 */ - "", /* GPIO42 */ - "", /* GPIO43 */ - "", /* GPIO44 */ - "PWM1_OUT", - "HDMI_HPD_P", - "SD_CARD_DET", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; - - /* I2S interface */ - i2s_alt2: i2s_alt2 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts deleted file mode 100644 index eec1d0892d33..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b", "brcm,bcm2835"; - model = "Raspberry Pi Model B"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf - * RPI00021 sheet 02 - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "SDA0", - "SCL0", - "SDA1", - "SCL1", - "GPIO_GCLK", - "CAM_GPIO1", - "LAN_RUN", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "", /* GPIO12 */ - "", /* GPIO13 */ - /* Serial port */ - "TXD0", - "RXD0", - "STATUS_LED_N", - "GPIO17", - "GPIO18", - "", /* GPIO19 */ - "", /* GPIO20 */ - "CAM_GPIO0", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "", /* GPIO26 */ - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "", /* GPIO32 */ - "", /* GPIO33 */ - "", /* GPIO34 */ - "", /* GPIO35 */ - "", /* GPIO36 */ - "", /* GPIO37 */ - "", /* GPIO38 */ - "", /* GPIO39 */ - "PWM0_OUT", - "", /* GPIO41 */ - "", /* GPIO42 */ - "", /* GPIO43 */ - "", /* GPIO44 */ - "PWM1_OUT", - "HDMI_HPD_P", - "SD_CARD_DET", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts deleted file mode 100644 index 87958a96c3e0..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835-rpi-cm1.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,compute-module", "brcm,bcm2835"; - model = "Raspberry Pi Compute Module IO board rev1"; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "GPIO0", - "GPIO1", - "GPIO2", - "GPIO3", - "GPIO4", - "GPIO5", - "GPIO6", - "GPIO7", - "GPIO8", - "GPIO9", - "GPIO10", - "GPIO11", - "GPIO12", - "GPIO13", - "GPIO14", - "GPIO15", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "GPIO32", - "GPIO33", - "GPIO34", - "GPIO35", - "GPIO36", - "GPIO37", - "GPIO38", - "GPIO39", - "GPIO40", - "GPIO41", - "GPIO42", - "GPIO43", - "GPIO44", - "GPIO45", - "HDMI_HPD_N", - /* Also used as ACT LED */ - "EMMC_EN_N", - /* Used by eMMC */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi deleted file mode 100644 index 750cd76948e3..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" - -/ { - leds { - led-act { - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - reg_3v3: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1v8: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&led_act { - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; -}; - -&sdhost { - non-removable; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_1v8>; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi deleted file mode 100644 index 4e7b4a592da7..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This include file covers the common peripherals and configuration between - * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's - * firmware interface. - */ - -#include - -&firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; -}; - -&hdmi { - clocks = <&firmware_clocks 9>, - <&firmware_clocks 13>; - clock-names = "pixel", "hdmi"; -}; - -&v3d { - power-domains = <&power RPI_POWER_DOMAIN_V3D>; -}; - -&vec { - clocks = <&firmware_clocks 15>; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts deleted file mode 100644 index dbf825985ec0..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Stefan Wahren - */ - -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-otg.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; - model = "Raspberry Pi Zero W"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; -}; - -&bt { - shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "CAM_GPIO1", /* GPIO40 */ - "WL_ON", /* GPIO41 */ - "", /* GPIO42 */ - "WIFI_CLK", /* GPIO43 */ - "CAM_GPIO0", /* GPIO44 */ - "BT_ON", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED_N", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; -}; - -&sdhci { - pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -&wifi_pwrseq { - reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts deleted file mode 100644 index f80e65a825fd..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Stefan Wahren - */ - -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-otg.dtsi" - -/ { - compatible = "raspberrypi,model-zero", "brcm,bcm2835"; - model = "Raspberry Pi Zero"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "", /* GPIO30 */ - "", /* GPIO31 */ - "CAM_GPIO1", /* GPIO32 */ - "", /* GPIO33 */ - "", /* GPIO34 */ - "", /* GPIO35 */ - "", /* GPIO36 */ - "", /* GPIO37 */ - "", /* GPIO38 */ - "", /* GPIO39 */ - "", /* GPIO40 */ - "CAM_GPIO0", /* GPIO41 */ - "", /* GPIO42 */ - "", /* GPIO43 */ - "", /* GPIO44 */ - "", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED_N", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi deleted file mode 100644 index ee9ee9d1fe65..000000000000 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -#include - -/ { - soc { - firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - - mboxes = <&mailbox>; - dma-ranges; - }; - - power: power { - compatible = "raspberrypi,bcm2835-power"; - firmware = <&firmware>; - #power-domain-cells = <1>; - }; - - vchiq: mailbox@7e00b840 { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0x3c>; - interrupts = <0 2>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - - gpioout: gpioout { - brcm,pins = <6>; - brcm,function = ; - }; - - alt0: alt0 { - brcm,pins = <4 5 7 8 9 10 11>; - brcm,function = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_gpio0>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_gpio2>; - status = "okay"; - clock-frequency = <100000>; -}; - -&usb { - power-domains = <&power RPI_POWER_DOMAIN_USB>; -}; - -&vec { - power-domains = <&power RPI_POWER_DOMAIN_VEC>; - status = "okay"; -}; - -&dsi0 { - power-domains = <&power RPI_POWER_DOMAIN_DSI0>; -}; - -&dsi1 { - power-domains = <&power RPI_POWER_DOMAIN_DSI1>; -}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi deleted file mode 100644 index 15cb331febbb..000000000000 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm283x.dtsi" -#include "bcm2835-common.dtsi" - -/ { - compatible = "brcm,bcm2835"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s"; - reg = <0x0>; - /* Source for d/i-cache-line-size and d/i-cache-sets - * https://developer.arm.com/documentation/ddi0301 - * /h/level-one-memory-system/cache-organization?lang=en - * - * Source for d/i-cache-size - * https://forums.raspberrypi.com/viewtopic.php?t=98428 - * - * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU - * It can be shared with the CPU through fw settings, - * but this is not recommended. - */ - d-cache-size = <0x4000>; - d-cache-line-size = <16>; - d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set - i-cache-size = <0x4000>; - i-cache-line-size = <16>; - i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set - }; - }; - - soc { - ranges = <0x7e000000 0x20000000 0x02000000>; - dma-ranges = <0x40000000 0x00000000 0x20000000>; - }; - - arm-pmu { - compatible = "arm,arm1176-pmu"; - }; -}; - -&cpu_thermal { - coefficients = <(-538) 407000>; -}; - -/* enable thermal sensor with the correct compatible property set */ -&thermal { - compatible = "brcm,bcm2835-thermal"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts deleted file mode 100644 index 6068ec390081..000000000000 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2836.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; - model = "Raspberry Pi 2 Model B"; - - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; -}; - -&gpio { - /* - * Taken from rpi_SCH_2b_1p2_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "", /* GPIO30 */ - "LAN_RUN", - "CAM_GPIO1", - "", /* GPIO33 */ - "", /* GPIO34 */ - "PWR_LOW_N", - "", /* GPIO36 */ - "", /* GPIO37 */ - "USB_LIMIT", - "", /* GPIO39 */ - "PWM0_OUT", - "CAM_GPIO0", - "SMPS_SCL", - "SMPS_SDA", - "ETH_CLK", - "PWM1_OUT", - "HDMI_HPD_N", - "STATUS_LED", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led-pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/bcm2836-rpi.dtsi deleted file mode 100644 index 48b03b55ff56..000000000000 --- a/arch/arm/boot/dts/bcm2836-rpi.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm2835-rpi.dtsi" -#include "bcm2835-rpi-common.dtsi" - -&vchiq { - compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; -}; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi deleted file mode 100644 index 783fe624ba68..000000000000 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm283x.dtsi" -#include "bcm2835-common.dtsi" - -/ { - compatible = "brcm,bcm2836"; - - soc { - ranges = <0x7e000000 0x3f000000 0x1000000>, - <0x40000000 0x40000000 0x00001000>; - dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - - local_intc: interrupt-controller@40000000 { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&local_intc>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&local_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI - <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI - <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI - <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI - always-on; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm2836-smp"; - - /* Source for d/i-cache-line-size and d/i-cache-sets - * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System - * /About-the-L1-memory-system?lang=en - * - * Source for d/i-cache-size - * https://forums.raspberrypi.com/viewtopic.php?t=98428 - */ - - v7_cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - clock-frequency = <800000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <32>; - i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set - next-level-cache = <&l2>; - }; - - v7_cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - clock-frequency = <800000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <32>; - i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set - next-level-cache = <&l2>; - }; - - v7_cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - clock-frequency = <800000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <32>; - i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set - next-level-cache = <&l2>; - }; - - v7_cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - clock-frequency = <800000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <32>; - i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set - next-level-cache = <&l2>; - }; - - /* Source for cache-line-size + cache-sets - * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System - * /About-the-L2-Memory-system?lang=en - * Source for cache-size - * https://forums.raspberrypi.com/viewtopic.php?t=98428 - */ - l2: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set - cache-level = <2>; - }; - }; -}; - -/* Make the BCM2835-style global interrupt controller be a child of the - * CPU-local interrupt controller. - */ -&intc { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-parent = <&local_intc>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&cpu_thermal { - coefficients = <(-538) 407000>; -}; - -/* enable thermal sensor with the correct compatible property set */ -&thermal { - compatible = "brcm,bcm2836-thermal"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts deleted file mode 100644 index 3548306dfbcb..000000000000 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; - model = "Raspberry Pi 3 Model A+"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "", - "BT_WL_ON", - "STATUS_LED_R", - "", - "", - "CAM_GPIO0", - "CAM_GPIO1", - ""; - status = "okay"; - }; -}; - -&gpio { - /* - * This is mostly based on the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "HDMI_HPD_N", - "STATUS_LED_G", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "PWM0_OUT", - "PWM1_OUT", - "", /* GPIO42 */ - "WIFI_CLK", - "SDA0", - "SCL0", - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; -}; - -&hdmi { - hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; - status = "okay"; -}; - -/* SDHOST is used to drive the SD card */ -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - -/* uart0 communicates with the BT module - * - * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven - * by a single GPIO. We can't give GPIO control to one of the drivers, - * otherwise the other part would get unexpectedly disturbed. - */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts deleted file mode 100644 index 2f1800cbc522..000000000000 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-lan7515.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; - model = "Raspberry Pi 3 Model B+"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; -}; - -&bt { - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_R", - "LAN_RUN", - "", - "CAM_GPIO0", - "CAM_GPIO1", - ""; - status = "okay"; - }; -}; - -&gpio { - /* - * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "HDMI_HPD_N", - "STATUS_LED_G", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "PWM0_OUT", - "PWM1_OUT", - "ETH_CLK", - "WIFI_CLK", - "SDA0", - "SCL0", - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; -}; - -&hdmi { - hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; -}; - -&leds { - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; - status = "okay"; -}; - -/* SDHOST is used to drive the SD card */ -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -&wifi_pwrseq { - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts deleted file mode 100644 index 61270340075c..000000000000 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; - model = "Raspberry Pi 3 Model B"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; -}; - -&bt { - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "STATUS_LED", - "LAN_RUN", - "HDMI_HPD_N", - "CAM_GPIO0", - "CAM_GPIO1", - "PWR_LOW_N"; - status = "okay"; - }; -}; - -&gpio { - /* - * Taken from rpi_SCH_3b_1p2_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "", /* GPIO 28 */ - "LAN_RUN_BOOT", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "PWM0_OUT", - "PWM1_OUT", - "ETH_CLK", - "WIFI_CLK", - "SDA0", - "SCL0", - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -/* SDHOST is used to drive the SD card */ -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - -&wifi_pwrseq { - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts deleted file mode 100644 index cf84e69fced8..000000000000 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837-rpi-cm3.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; - model = "Raspberry Pi Compute Module 3 IO board V3.0"; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "GPIO0", - "GPIO1", - "GPIO2", - "GPIO3", - "GPIO4", - "GPIO5", - "GPIO6", - "GPIO7", - "GPIO8", - "GPIO9", - "GPIO10", - "GPIO11", - "GPIO12", - "GPIO13", - "GPIO14", - "GPIO15", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "GPIO32", - "GPIO33", - "GPIO34", - "GPIO35", - "GPIO36", - "GPIO37", - "GPIO38", - "GPIO39", - "GPIO40", - "GPIO41", - "GPIO42", - "GPIO43", - "GPIO44", - "GPIO45", - "SMPS_SCL", - "SMPS_SDA", - /* Used by eMMC */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi deleted file mode 100644 index 1e4e4946b6b6..000000000000 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - reg_3v3: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1v8: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "HDMI_HPD_N", - "EMMC_EN_N", - "", - "", - "", - "", - "", - ""; - status = "okay"; - }; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_1v8>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts deleted file mode 100644 index b9cc4594398b..000000000000 --- a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2022 Stefan Wahren - */ - -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-otg.dtsi" -#include "bcm283x-rpi-wifi-bt.dtsi" - -/ { - compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; - model = "Raspberry Pi Zero 2 W"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; -}; - -&bt { - shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "HDMI_HPD_N", - "STATUS_LED_N", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "CAM_GPIO0", /* GPIO40 */ - "WL_ON", /* GPIO41 */ - "BT_ON", /* GPIO42 */ - "WIFI_CLK", /* GPIO43 */ - "SDA0", /* GPIO44 */ - "SCL0", /* GPIO45 */ - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&led_act { - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; -}; - -&sdhci { - pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -&wifi_pwrseq { - reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi deleted file mode 100644 index 84c08b46519d..000000000000 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -#include "bcm283x.dtsi" -#include "bcm2835-common.dtsi" - -/ { - compatible = "brcm,bcm2837"; - - soc { - ranges = <0x7e000000 0x3f000000 0x1000000>, - <0x40000000 0x40000000 0x00001000>; - dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - - local_intc: local_intc@40000000 { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&local_intc>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&local_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI - <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI - <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI - <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI - always-on; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit - - /* Source for d/i-cache-line-size and d/i-cache-sets - * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system - * /about-the-l1-memory-system?lang=en - * - * Source for d/i-cache-size - * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks - */ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000d8>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e8>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000f0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set - next-level-cache = <&l2>; - }; - - /* Source for cache-line-size + cache-sets - * https://developer.arm.com/documentation/ddi0500 - * /e/level-2-memory-system/about-the-l2-memory-system?lang=en - * Source for cache-size - * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf - */ - l2: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set - cache-level = <2>; - }; - }; -}; - -/* Make the BCM2835-style global interrupt controller be a child of the - * CPU-local interrupt controller. - */ -&intc { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-parent = <&local_intc>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&cpu_thermal { - coefficients = <(-538) 412000>; -}; - -/* enable thermal sensor with the correct compatible property set */ -&thermal { - compatible = "brcm,bcm2837-thermal"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi deleted file mode 100644 index 70bece63f9a7..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - aliases { - ethernet0 = ðernet; - }; -}; - -&usb { - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,7800"; - reg = <1>; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - eth_phy: ethernet-phy@1 { - reg = <1>; - microchip,led-modes = < - LAN78XX_LINK_1000_ACTIVITY - LAN78XX_LINK_10_100_ACTIVITY - >; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi b/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi deleted file mode 100644 index f83e56de1a72..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - /* - * This file provides the now deprecated ACT LED to the - * Raspberry Pi boards. Please don't include this file - * for new boards! - */ - leds: leds { - compatible = "gpio-leds"; - - led_act: led-act { - label = "ACT"; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi deleted file mode 100644 index 882b13807075..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - aliases { - ethernet0 = ðernet; - }; -}; - -&usb { - usb1@1 { - compatible = "usb424,9512"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi deleted file mode 100644 index 4273b90b53cc..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/ { - aliases { - ethernet0 = ðernet; - }; -}; - -&usb { - usb1@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi deleted file mode 100644 index 73f4ece8dcd0..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi +++ /dev/null @@ -1,3 +0,0 @@ -&usb { - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi deleted file mode 100644 index e2fd9610e125..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&usb { - dr_mode = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - /* - * According to dwc2 the sum of all device EP - * fifo sizes shouldn't exceed 3776 bytes. - */ - g-tx-fifo-size = <256 256 512 512 512 768 768>; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi deleted file mode 100644 index 0ff0e9e25327..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&usb { - dr_mode = "peripheral"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 256 512 512 512 768 768>; -}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi b/arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi deleted file mode 100644 index 0b64cc19941f..000000000000 --- a/arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - }; -}; - -/* SDHCI is used to control the SDIO for wireless */ -&sdhci { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio34>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&wifi_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - status = "okay"; - - bt: bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - }; -}; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi deleted file mode 100644 index c9c52a19ef3b..000000000000 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ /dev/null @@ -1,501 +0,0 @@ -#include -#include -#include -#include -#include -#include - -/* firmware-provided startup stubs live here, where the secondary CPUs are - * spinning. - */ -/memreserve/ 0x00000000 0x00001000; - -/* This include file covers the common peripherals and configuration between - * bcm2835 and bcm2836 implementations, leaving the CPU configuration to - * bcm2835.dtsi and bcm2836.dtsi. - */ - -/ { - compatible = "brcm,bcm2835"; - model = "BCM2835"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - rmem: reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - cma: linux,cma { - compatible = "shared-dma-pool"; - size = <0x4000000>; /* 64MB */ - reusable; - linux,cma-default; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - - trips { - cpu-crit { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - system_timer: timer@7e003000 { - compatible = "brcm,bcm2835-system-timer"; - reg = <0x7e003000 0x1000>; - interrupts = <1 0>, <1 1>, <1 2>, <1 3>; - /* This could be a reference to BCM2835_CLOCK_TIMER, - * but we don't have the driver using the common clock - * support yet. - */ - clock-frequency = <1000000>; - }; - - txp: txp@7e004000 { - compatible = "brcm,bcm2835-txp"; - reg = <0x7e004000 0x20>; - interrupts = <1 11>; - }; - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - - /* CPRMAN derives almost everything from the - * platform's oscillator. However, the DSI - * pixel clocks come from the DSI analog PHY. - */ - clocks = <&clk_osc>, - <&dsi0 0>, <&dsi0 1>, <&dsi0 2>, - <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; - }; - - mailbox: mailbox@7e00b880 { - compatible = "brcm,bcm2835-mbox"; - reg = <0x7e00b880 0x40>; - interrupts = <0 1>; - #mbox-cells = <0>; - }; - - gpio: gpio@7e200000 { - compatible = "brcm,bcm2835-gpio"; - reg = <0x7e200000 0xb4>; - /* - * The GPIO IP block is designed for 3 banks of GPIOs. - * Each bank has a GPIO interrupt for itself. - * There is an overall "any bank" interrupt. - * In order, these are GIC interrupts 17, 18, 19, 20. - * Since the BCM2835 only has 2 banks, the 2nd bank - * interrupt output appears to be mirrored onto the - * 3rd bank's interrupt signal. - * So, a bank0 interrupt shows up on 17, 20, and - * a bank1 interrupt shows up on 18, 19, 20! - */ - interrupts = <2 17>, <2 18>, <2 19>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - gpio-ranges = <&gpio 0 0 54>; - - /* Defines common pin muxing groups - * - * While each pin can have its mux selected - * for various functions individually, some - * groups only make sense to switch to a - * particular function together. - */ - dpi_gpio0: dpi-gpio0 { - brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27>; - brcm,function = ; - }; - emmc_gpio22: emmc-gpio22 { - brcm,pins = <22 23 24 25 26 27>; - brcm,function = ; - }; - emmc_gpio34: emmc-gpio34 { - brcm,pins = <34 35 36 37 38 39>; - brcm,function = ; - brcm,pull = ; - }; - emmc_gpio48: emmc-gpio48 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = ; - }; - - gpclk0_gpio4: gpclk0-gpio4 { - brcm,pins = <4>; - brcm,function = ; - }; - gpclk1_gpio5: gpclk1-gpio5 { - brcm,pins = <5>; - brcm,function = ; - }; - gpclk1_gpio42: gpclk1-gpio42 { - brcm,pins = <42>; - brcm,function = ; - }; - gpclk1_gpio44: gpclk1-gpio44 { - brcm,pins = <44>; - brcm,function = ; - }; - gpclk2_gpio6: gpclk2-gpio6 { - brcm,pins = <6>; - brcm,function = ; - }; - gpclk2_gpio43: gpclk2-gpio43 { - brcm,pins = <43>; - brcm,function = ; - brcm,pull = ; - }; - - i2c0_gpio0: i2c0-gpio0 { - brcm,pins = <0 1>; - brcm,function = ; - }; - i2c0_gpio28: i2c0-gpio28 { - brcm,pins = <28 29>; - brcm,function = ; - }; - i2c0_gpio44: i2c0-gpio44 { - brcm,pins = <44 45>; - brcm,function = ; - }; - i2c1_gpio2: i2c1-gpio2 { - brcm,pins = <2 3>; - brcm,function = ; - }; - i2c1_gpio44: i2c1-gpio44 { - brcm,pins = <44 45>; - brcm,function = ; - }; - - jtag_gpio22: jtag-gpio22 { - brcm,pins = <22 23 24 25 26 27>; - brcm,function = ; - }; - - pcm_gpio18: pcm-gpio18 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; - pcm_gpio28: pcm-gpio28 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; - - sdhost_gpio48: sdhost-gpio48 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = ; - }; - - spi0_gpio7: spi0-gpio7 { - brcm,pins = <7 8 9 10 11>; - brcm,function = ; - }; - spi0_gpio35: spi0-gpio35 { - brcm,pins = <35 36 37 38 39>; - brcm,function = ; - }; - spi1_gpio16: spi1-gpio16 { - brcm,pins = <16 17 18 19 20 21>; - brcm,function = ; - }; - spi2_gpio40: spi2-gpio40 { - brcm,pins = <40 41 42 43 44 45>; - brcm,function = ; - }; - - uart0_gpio14: uart0-gpio14 { - brcm,pins = <14 15>; - brcm,function = ; - }; - /* Separate from the uart0_gpio14 group - * because it conflicts with spi1_gpio16, and - * people often run uart0 on the two pins - * without flow control. - */ - uart0_ctsrts_gpio16: uart0-ctsrts-gpio16 { - brcm,pins = <16 17>; - brcm,function = ; - }; - uart0_ctsrts_gpio30: uart0-ctsrts-gpio30 { - brcm,pins = <30 31>; - brcm,function = ; - brcm,pull = ; - }; - uart0_gpio32: uart0-gpio32 { - brcm,pins = <32 33>; - brcm,function = ; - brcm,pull = ; - }; - uart0_gpio36: uart0-gpio36 { - brcm,pins = <36 37>; - brcm,function = ; - }; - uart0_ctsrts_gpio38: uart0-ctsrts-gpio38 { - brcm,pins = <38 39>; - brcm,function = ; - }; - - uart1_gpio14: uart1-gpio14 { - brcm,pins = <14 15>; - brcm,function = ; - }; - uart1_ctsrts_gpio16: uart1-ctsrts-gpio16 { - brcm,pins = <16 17>; - brcm,function = ; - }; - uart1_gpio32: uart1-gpio32 { - brcm,pins = <32 33>; - brcm,function = ; - }; - uart1_ctsrts_gpio30: uart1-ctsrts-gpio30 { - brcm,pins = <30 31>; - brcm,function = ; - }; - uart1_gpio40: uart1-gpio40 { - brcm,pins = <40 41>; - brcm,function = ; - }; - uart1_ctsrts_gpio42: uart1-ctsrts-gpio42 { - brcm,pins = <42 43>; - brcm,function = ; - }; - }; - - uart0: serial@7e201000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x200>; - interrupts = <2 25>; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - }; - - sdhost: mmc@7e202000 { - compatible = "brcm,bcm2835-sdhost"; - reg = <0x7e202000 0x100>; - interrupts = <2 24>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - status = "disabled"; - }; - - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - status = "disabled"; - }; - - spi: spi@7e204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x200>; - interrupts = <2 22>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x200>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dpi: dpi@7e208000 { - compatible = "brcm,bcm2835-dpi"; - reg = <0x7e208000 0x8c>; - clocks = <&clocks BCM2835_CLOCK_VPU>, - <&clocks BCM2835_CLOCK_DPI>; - clock-names = "core", "pixel"; - status = "disabled"; - }; - - dsi0: dsi@7e209000 { - compatible = "brcm,bcm2835-dsi0"; - reg = <0x7e209000 0x78>; - interrupts = <2 4>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - clocks = <&clocks BCM2835_PLLA_DSI0>, - <&clocks BCM2835_CLOCK_DSI0E>, - <&clocks BCM2835_CLOCK_DSI0P>; - clock-names = "phy", "escape", "pixel"; - - clock-output-names = "dsi0_byte", - "dsi0_ddr2", - "dsi0_ddr"; - - status = "disabled"; - }; - - aux: aux@7e215000 { - compatible = "brcm,bcm2835-aux"; - #clock-cells = <1>; - reg = <0x7e215000 0x8>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - }; - - uart1: serial@7e215040 { - compatible = "brcm,bcm2835-aux-uart"; - reg = <0x7e215040 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_UART>; - status = "disabled"; - }; - - spi1: spi@7e215080 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e215080 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_SPI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@7e2150c0 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e2150c0 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_SPI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@7e20c000 { - compatible = "brcm,bcm2835-pwm"; - reg = <0x7e20c000 0x28>; - clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clock-rates = <10000000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - sdhci: mmc@7e300000 { - compatible = "brcm,bcm2835-sdhci"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clocks BCM2835_CLOCK_EMMC>; - status = "disabled"; - }; - - hvs@7e400000 { - compatible = "brcm,bcm2835-hvs"; - reg = <0x7e400000 0x6000>; - interrupts = <2 1>; - }; - - dsi1: dsi@7e700000 { - compatible = "brcm,bcm2835-dsi1"; - reg = <0x7e700000 0x8c>; - interrupts = <2 12>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - clocks = <&clocks BCM2835_PLLD_DSI1>, - <&clocks BCM2835_CLOCK_DSI1E>, - <&clocks BCM2835_CLOCK_DSI1P>; - clock-names = "phy", "escape", "pixel"; - - clock-output-names = "dsi1_byte", - "dsi1_ddr2", - "dsi1_ddr"; - - status = "disabled"; - }; - - i2c1: i2c@7e804000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e804000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb: usb@7e980000 { - compatible = "brcm,bcm2835-usb"; - reg = <0x7e980000 0x10000>; - interrupts = <1 9>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk_usb>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - }; - }; - - clocks { - /* The oscillator is the root of the clock tree. */ - clk_osc: clk-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "osc"; - clock-frequency = <19200000>; - }; - - clk_usb: clk-usb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "otg"; - clock-frequency = <480000000>; - }; - }; - - usbphy: phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts deleted file mode 100644 index c80ac16ad949..000000000000 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC56U - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac56u", "brcm,bcm4708"; - model = "Asus RT-AC56U (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - led-wan { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - led-lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - led-power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-all { - label = "bcm53xx:blue:all"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts deleted file mode 100644 index 3fe17bd7b86d..000000000000 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC68U - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac68u", "brcm,bcm4708"; - model = "Asus RT-AC68U (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - led-power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi deleted file mode 100644 index 42bcbf10957c..000000000000 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2 - * - * Copyright (C) 2014 Rafał Miłecki - * Copyright (C) 2022 SHIMAMOTO Takayoshi - */ - - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" -#include - -/ { - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - sck-gpios = <&chipcommon 7 0>; - mosi-gpios = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - led-usb { - /* label = "bcm53xx:blue:usb"; */ - function = LED_FUNCTION_USB; - color = ; - gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>, <&ohci_port2>, - <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-power0 { - /* label = "bcm53xx:red:power"; */ - function = LED_FUNCTION_FAULT; - color = ; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - }; - - led-power1 { - /* label = "bcm53xx:white:power"; */ - function = LED_FUNCTION_POWER; - color = ; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router0 { - /* label = "bcm53xx:blue:router"; */ - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router1 { - /* label = "bcm53xx:amber:router"; */ - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - led-wan { - /* label = "bcm53xx:blue:wan"; */ - function = LED_FUNCTION_WAN; - color = ; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-wireless0 { - /* label = "bcm53xx:blue:wireless"; */ - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - led-wireless1 { - /* label = "bcm53xx:amber:wireless"; */ - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - button-sw-ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan1"; - }; - - port@1 { - label = "lan2"; - }; - - port@2 { - label = "lan3"; - }; - - port@3 { - label = "lan4"; - }; - - port@4 { - label = "wan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts deleted file mode 100644 index 8e506269fa1a..000000000000 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindigs for Buffalo WZR-1166DHP - * - * Copyright (C) 2022 SHIMAMOTO Takayoshi - */ - -/dts-v1/; - -#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" - -/ { - compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708"; - model = "Buffalo WZR-1166DHP"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - -}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts deleted file mode 100644 index 596129027074..000000000000 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindigs for Buffalo WZR-1166DHP2 - * - * Copyright (C) 2022 SHIMAMOTO Takayoshi - */ - -/dts-v1/; - -#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" - -/ { - compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708"; - model = "Buffalo WZR-1166DHP2"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - -}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts deleted file mode 100644 index 95ef6ca7210b..000000000000 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-1750DHP - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; - model = "Buffalo WZR-1750DHP (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - sck-gpios = <&chipcommon 7 0>; - mosi-gpios = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - led-usb { - label = "bcm53xx:blue:usb"; - gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>, <&ohci_port2>, - <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-power0 { - label = "bcm53xx:red:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - }; - - led-power1 { - label = "bcm53xx:white:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router0 { - label = "bcm53xx:blue:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - led-wan { - label = "bcm53xx:blue:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-wireless0 { - label = "bcm53xx:blue:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - led-wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - button-sw-ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts deleted file mode 100644 index 0ed25bf71f0d..000000000000 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,ea6300-v1", "brcm,bcm4708"; - model = "Linksys EA6300 V1"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nvram@1c080000 { - compatible = "brcm,nvram"; - reg = <0x1c080000 0x180000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts deleted file mode 100644 index f1412ba83def..000000000000 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - * Copyright (C) 2018 Rene Kjellerup - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,ea6500-v2", "brcm,bcm4708"; - model = "Linksys EA6500 V2"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts deleted file mode 100644 index e04d2e5ea51a..000000000000 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - compatible = "luxul,xap-1510-v1", "brcm,bcm4708"; - model = "Luxul XAP-1510 V1"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - }; - }; - - leds { - compatible = "gpio-leds"; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "poe"; - }; - - port@4 { - label = "lan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts deleted file mode 100644 index a399800139d9..000000000000 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Luxul XWC-1000 - * - * Copyright 2014 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwc-1000", "brcm,bcm4708"; - model = "Luxul XWC-1000 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - }; - }; - - nand_controller: nand-controller@18028000 { - nand@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ubi"; - reg = <0x00000000 0x08000000>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@4 { - label = "lan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts deleted file mode 100644 index fad3473810a2..000000000000 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X arm platform code. - * DTS for Netgear R6250 V1 - * - * Copyright 2013 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r6250-v1", "brcm,bcm4708"; - model = "Netgear R6250 V1 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-power0 { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-wireless { - label = "bcm53xx:blue:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts deleted file mode 100644 index 77396730bdd3..000000000000 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R6300 V2 - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r6300-v2", "brcm,bcm4708"; - model = "Netgear R6300 V2 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-power0 { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - led-power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - }; - - led-wireless { - label = "bcm53xx:blue:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts deleted file mode 100644 index 5b2b7b8b3b12..000000000000 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X arm platform code. - * DTS for SmartRG SR400ac - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "smartrg,sr400ac", "brcm,bcm4708"; - model = "SmartRG SR400ac"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - }; - - led-usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - trigger-sources = <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-usb3-green { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - led-wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - }; - - led-status-red { - label = "bcm53xx:red:status"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - - led-status-green { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; - - led-status-blue { - label = "bcm53xx:blue:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - led-wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - - led-wan-red { - label = "bcm53xx:red:wan"; - gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi deleted file mode 100644 index 1a19e97a987d..000000000000 --- a/arch/arm/boot/dts/bcm4708.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for BCM4708 SoC. - * - * Copyright 2013-2014 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "bcm5301x.dtsi" - -/ { - compatible = "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm-nsp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - secondary-boot-reg = <0xffff0400>; - reg = <0x1>; - }; - }; - -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts deleted file mode 100644 index 3854db0118a9..000000000000 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-N18U - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; - model = "Asus RT-N18U (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-wan { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts deleted file mode 100644 index d0a26b643b82..000000000000 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-600DHP2 - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; - model = "Buffalo WZR-600DHP2 (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - sck-gpios = <&chipcommon 7 0>; - mosi-gpios = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power0 { - label = "bcm53xx:green:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-power1 { - label = "bcm53xx:red:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - }; - - led-router0 { - label = "bcm53xx:green:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - led-wan { - label = "bcm53xx:green:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-wireless0 { - label = "bcm53xx:green:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - led-wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - /* Switch device mode? */ - button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan1"; - }; - - port@1 { - label = "lan2"; - }; - - port@2 { - label = "lan3"; - }; - - port@3 { - label = "lan4"; - }; - - port@4 { - label = "wan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts deleted file mode 100644 index 7655e4ff2d1c..000000000000 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-900DHP - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; - model = "Buffalo WZR-900DHP (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - sck-gpios = <&chipcommon 7 0>; - mosi-gpios = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - led-usb { - label = "bcm53xx:green:usb"; - gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; - }; - - led-power0 { - label = "bcm53xx:green:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-power1 { - label = "bcm53xx:red:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - }; - - led-router0 { - label = "bcm53xx:green:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - led-wan { - label = "bcm53xx:green:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-wireless0 { - label = "bcm53xx:green:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - led-wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts deleted file mode 100644 index 9f21d6d6d35b..000000000000 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" - -/ { - compatible = "luxul,xap-1410-v1", "brcm,bcm47081", "brcm,bcm4708"; - model = "Luxul XAP-1410 V1"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - }; - }; - - leds { - compatible = "gpio-leds"; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@4 { - label = "poe"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts deleted file mode 100644 index 256107291702..000000000000 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708"; - model = "Luxul XWR-1200 V1"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - #nvmem-cell-cells = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-lan3 { - label = "bcm53xx:green:lan3"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-lan4 { - label = "bcm53xx:green:lan4"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-wan { - label = "bcm53xx:green:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-lan2 { - label = "bcm53xx:green:lan2"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-usb { - label = "bcm53xx:green:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - led-2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led-lan1 { - label = "bcm53xx:green:lan1"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr 0>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - nvmem-cells = <&et0macaddr 5>; - nvmem-cell-names = "mac-address"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts deleted file mode 100644 index b6a5886698b2..000000000000 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" - -/ { - compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708"; - model = "TP-LINK Archer C5 V2"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; - }; - - led-lan { - label = "bcm53xx:green:lan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - }; - - led-usb2-port1 { - label = "bcm53xx:green:usb2-port1"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - led-power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-wan-green { - label = "bcm53xx:green:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-wps { - label = "bcm53xx:green:wps"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - }; - - led-wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - - led-5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - - led-usb2-port2 { - label = "bcm53xx:green:usb2-port2"; - gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; - - partitions { - compatible = "tplink,safeloader-partitions"; - partitions-table-offset = <0xe50000>; - - partition-os-image { - compatible = "brcm,trx"; - }; - - partition-file-system { - linux,rootfs; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi deleted file mode 100644 index ed13af028528..000000000000 --- a/arch/arm/boot/dts/bcm47081.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for BCM47081 SoC. - * - * Copyright © 2014 Rafał Miłecki - */ - -#include "bcm5301x.dtsi" - -/ { - compatible = "brcm,bcm47081"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts deleted file mode 100644 index 4f44cb4df704..000000000000 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC87U - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; - model = "Asus RT-AC87U"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - led-power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-wan { - label = "bcm53xx:red:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - nvram@80000 { - label = "nvram"; - reg = <0x00080000 0x00180000>; - }; - - firmware@200000 { - label = "firmware"; - reg = <0x00200000 0x07cc0000>; - compatible = "brcm,trx"; - }; - - asus@7ec0000 { - label = "asus"; - reg = <0x07ec0000 0x00140000>; - read-only; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts deleted file mode 100644 index b7cd2faa30ce..000000000000 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WXR-1900DHP - * - * Copyright (C) 2015 Felix Fietkau - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; - model = "Buffalo WXR-1900DHP"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-usb { - label = "bcm53xx:green:usb"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - }; - - led-power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-router-amber { - label = "bcm53xx:amber:router"; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - }; - - led-router-white { - label = "bcm53xx:white:router"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - - led-wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; - - led-wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - led-wireless-amber { - label = "bcm53xx:amber:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - led-wireless-white { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-power { - label = "Power"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - - button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - button-sw-ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - - button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts deleted file mode 100644 index 99253fd7adb3..000000000000 --- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,ea9200", "brcm,bcm4709", "brcm,bcm4708"; - model = "Linksys EA9200"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - nvram@1c080000 { - compatible = "brcm,nvram"; - reg = <0x1c080000 0x180000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts deleted file mode 100644 index 24ba8f8f9bf3..000000000000 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R7000 - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; - model = "Netgear R7000"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - led-2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - }; - - led-wireless { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - }; - - led-usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts deleted file mode 100644 index 707c561703ed..000000000000 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R8000 - * - * Copyright (C) 2015 Rafał Miłecki - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, - * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM - * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE - * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; - model = "Netgear R8000 (BCM4709)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; - - led-5ghz-1 { - label = "bcm53xx:white:5ghz-1"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - led-2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-wireless { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - }; - - led-wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - }; - - led-5ghz-2 { - label = "bcm53xx:white:5ghz-2"; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - led-usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - button-brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5735000 5835000>; - brcm,ccode-map = "JP-JP-78", "US-Q2-86"; - }; - }; -}; - -&pcie1 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,0,0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,1,0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,0 { - reg = <0x800 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - brcm,ccode-map = "JP-JP-78", "US-Q2-86"; - }; - }; - - bridge@1,2,2 { - reg = <0x1000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@1,4,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5170000 5730000>; - brcm,ccode-map = "JP-JP-78", "US-Q2-86"; - }; - }; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan1"; - }; - - port@1 { - label = "lan2"; - }; - - port@2 { - label = "lan3"; - }; - - port@3 { - label = "lan4"; - }; - - port@4 { - label = "wan"; - }; - - port@8 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts deleted file mode 100644 index 5a8b2b1567e6..000000000000 --- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" - -/ { - compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708"; - model = "TP-LINK Archer C9 V1"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - }; - - led-wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - }; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - }; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-wan-blue { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - }; - - led-wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - }; - - led-power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; - - partitions { - compatible = "tplink,safeloader-partitions"; - partitions-table-offset = <0xe50000>; - - partition-os-image { - compatible = "brcm,trx"; - }; - - partition-file-system { - linux,rootfs; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi deleted file mode 100644 index cba3d910bed8..000000000000 --- a/arch/arm/boot/dts/bcm4709.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -#include "bcm4708.dtsi" - -&uart0 { - clock-frequency = <125000000>; - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; -}; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts deleted file mode 100644 index 4d5747aa5dc8..000000000000 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2021-2022 Arınç ÜNAL - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708"; - model = "Asus RT-AC88U"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - nvram@1c080000 { - compatible = "brcm,nvram"; - reg = <0x1c080000 0x00180000>; - - et1macaddr: et1macaddr { - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "white:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-wan-red { - label = "red:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-lan { - label = "white:lan"; - gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "white:usb2"; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - trigger-sources = <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-usb3 { - label = "white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - trigger-sources = <&ehci_port1>, <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-wps { - label = "white:wps"; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - - button-reset { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - button-wifi { - label = "Wi-Fi"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - - button-led { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - }; - - switch { - compatible = "realtek,rtl8365mb"; - /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ - mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - realtek,disable-leds; - dsa,member = <1 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - phy-handle = <ðphy0>; - }; - - port@1 { - reg = <1>; - label = "lan6"; - phy-handle = <ðphy1>; - }; - - port@2 { - reg = <2>; - label = "lan7"; - phy-handle = <ðphy2>; - }; - - port@3 { - reg = <3>; - label = "lan8"; - phy-handle = <ðphy3>; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&sw0_p5>; - phy-mode = "rgmii"; - tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2100>; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; - }; - }; - }; -}; - -&srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; - status = "okay"; - dsa,member = <0 0>; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - }; - - sw0_p5: port@5 { - /delete-property/ethernet; - - label = "extsw"; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - port@7 { - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@8 { - label = "cpu"; - }; - }; -}; - -&gmac0 { - status = "disabled"; -}; - -&gmac1 { - nvmem-cells = <&et1macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - partition@80000 { - label = "nvram"; - reg = <0x00080000 0x00180000>; - }; - - partition@200000 { - label = "firmware"; - reg = <0x00200000 0x07e00000>; - compatible = "brcm,trx"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts deleted file mode 100644 index 51ce510b3e3a..000000000000 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for D-Link DIR-885L - * - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch1.dtsi" - -/ { - compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708"; - model = "D-Link DIR-885L"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - nand_controller: nand-controller@18028000 { - nand@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - led-power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - led-wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - /* Switch: router / extender */ - button-extender { - label = "Extender"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - }; - - port@8 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts deleted file mode 100644 index 60744f82c2b7..000000000000 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device tree for D-Link DIR-890L - * D-Link calls this board "WRGAC36" - * this router has the same looks and form factor as D-Link DIR-885L. - * - * Some differences from DIR-885L include a separate USB2 port, separate LEDs - * for USB2 and USB3, a separate VCC supply for the USB2 slot and no - * router/extender switch is mounted (there is an empty mount point on the - * PCB) so this device is a pure router. Also the LAN ports are in the right - * order. - * - * Based on the device tree for DIR-885L - * Copyright (C) 2016 Rafał Miłecki - * Copyright (C) 2022 Linus Walleij - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch1.dtsi" - -/ { - compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708"; - model = "D-Link DIR-890L"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - /* - * LED information is derived from the boot log which - * conveniently lists all the LEDs. - */ - compatible = "gpio-leds"; - - led-power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - led-power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - led-wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-usb2-white { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - led-2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - /* Called "factory reset" in the vendor dmesg */ - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; - - /* - * The flash memory is memory mapped at 0x1e000000-0x1fffffff - * 64KB blocks; total size 2MB, same that can be - * found attached to the spi_nor SPI controller. - */ - nvram@1e1f0000 { - compatible = "brcm,nvram"; - reg = <0x1e1f0000 0x00010000>; - - et0macaddr: et0macaddr { - }; - }; -}; - -&gmac2 { - /* - * The NVRAM curiously does not contain a MAC address - * for et2 so since that is the only ethernet interface - * actually in use on the platform, we use this et0 MAC - * address for et2. - */ - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&nandcs { - /* Spansion S34ML01G2, 128MB with 128KB erase blocks */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * This is called "nflash" in the vendor kernel with - * "upgrade" and "rootfs" (probably using OpenWrt - * splitpart). We call it "firmware" like standard tools - * assume. The CFE loader contains incorrect information - * about TRX partitions, ignore this, there are no TRX - * partitions: this device uses SEAMA. - */ - firmware@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&usb2 { - vcc-gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan1"; - }; - - port@1 { - label = "lan2"; - }; - - port@2 { - label = "lan3"; - }; - - port@3 { - label = "lan4"; - }; - - port@4 { - label = "wan"; - }; - - port@8 { - label = "cpu"; - phy-mode = "rgmii"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts deleted file mode 100644 index 8036c04d81cb..000000000000 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,panamera", "brcm,bcm47094", "brcm,bcm4708"; - model = "Linksys EA9500"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - nvram@1c080000 { - compatible = "brcm,nvram"; - reg = <0x1c080000 0x100000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - button-reset { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "bcm53xx:green:usb2"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-power { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-wifi-disabled { - label = "bcm53xx:amber:wifi-disabled"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - led-wifi-enabled { - label = "bcm53xx:white:wifi-enabled"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar1 { - label = "bcm53xx:white:bluebar1"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar2 { - label = "bcm53xx:white:bluebar2"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar3 { - label = "bcm53xx:white:bluebar3"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - - led-bluebar4 { - label = "bcm53xx:white:bluebar4"; - gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar5 { - label = "bcm53xx:white:bluebar5"; - gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar6 { - label = "bcm53xx:white:bluebar6"; - gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar7 { - label = "bcm53xx:white:bluebar7"; - gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; - }; - - led-bluebar8 { - label = "bcm53xx:white:bluebar8"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - }; - - mdio-mux@18003000 { - - /* BIT(9) = 1 => external mdio */ - mdio@200 { - reg = <0x200>; - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "brcm,bcm53125"; - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - reset-names = "robo_reset"; - reg = <0>; - dsa,member = <1 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_mdio>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan5"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan6"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - sw1_p8: port@8 { - reg = <8>; - ethernet = <&sw0_p0>; - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>; -}; - -&srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; - status = "okay"; - dsa,member = <0 0>; - - ports { - sw0_p0: port@0 { - label = "extsw"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@1 { - label = "lan7"; - }; - - port@2 { - label = "lan4"; - }; - - port@3 { - label = "lan8"; - }; - - port@4 { - label = "wan"; - }; - - port@5 { - label = "cpu"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@7 { - label = "cpu"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@8 { - label = "cpu"; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "linksys,ns-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x0000000 0x0080000>; - read-only; - }; - - partition@80000 { - label = "nvram"; - reg = <0x080000 0x0100000>; - }; - - partition@180000{ - label = "devinfo"; - reg = <0x0180000 0x080000>; - }; - - partition@200000 { - reg = <0x0200000 0x01d00000>; - compatible = "linksys,ns-firmware", "brcm,trx"; - }; - - partition@1f00000 { - reg = <0x01f00000 0x01d00000>; - compatible = "linksys,ns-firmware", "brcm,trx"; - }; - - partition@5200000 { - label = "system"; - reg = <0x05200000 0x02e00000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts deleted file mode 100644 index e8991d4e248c..000000000000 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul ABR-4500 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - #nvmem-cell-cells = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - led-usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr 0>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "wan"; - nvmem-cells = <&et0macaddr 1>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - label = "lan4"; - }; - - port@2 { - label = "lan3"; - }; - - port@3 { - label = "lan2"; - }; - - port@4 { - label = "lan1"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts deleted file mode 100644 index 6875625869d9..000000000000 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" - -/ { - compatible = "luxul,xap-1610-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XAP-1610 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - }; - }; - - leds { - compatible = "gpio-leds"; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "poe"; - }; - - port@1 { - label = "lan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts deleted file mode 100644 index 7cfa4607ef31..000000000000 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XBR-4500 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - #nvmem-cell-cells = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - - led-usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr 0>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "wan"; - nvmem-cells = <&et0macaddr 1>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - label = "lan4"; - }; - - port@2 { - label = "lan3"; - }; - - port@3 { - label = "lan2"; - }; - - port@4 { - label = "lan1"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts deleted file mode 100644 index d55e10095eae..000000000000 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2019 Legrand AV Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwc-2000-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XWC-2000 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - }; - }; - - leds { - compatible = "gpio-leds"; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts deleted file mode 100644 index ccf031c0e276..000000000000 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - compatible = "luxul,xwr-3100-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XWR-3100 V1"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - #nvmem-cell-cells = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-lan3 { - label = "bcm53xx:green:lan3"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - led-lan4 { - label = "bcm53xx:green:lan4"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - led-wan { - label = "bcm53xx:green:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-lan1 { - label = "bcm53xx:green:lan1"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - led-lan2 { - label = "bcm53xx:green:lan2"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - led-usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - led-2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr 0>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - nvmem-cells = <&et0macaddr 5>; - nvmem-cell-names = "mac-address"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts deleted file mode 100644 index 789dd2a3d226..000000000000 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwr-3150-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XWR-3150 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; - - et0macaddr: et0macaddr { - #nvmem-cell-cells = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - led-2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr 0>; - nvmem-cell-names = "mac-address"; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - nvmem-cells = <&et0macaddr 5>; - nvmem-cell-names = "mac-address"; - }; - - port@5 { - label = "cpu"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts deleted file mode 100644 index 76d562610654..000000000000 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708"; - model = "Netgear R8500"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power0 { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - led-5ghz-1 { - label = "bcm53xx:white:5ghz-1"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - led-5ghz-2 { - label = "bcm53xx:white:5ghz-2"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - led-2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - led-usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts deleted file mode 100644 index 3bf6e24978ac..000000000000 --- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Hamster Tian - * Copyright (C) 2019 Hao Dong - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; - model = "Phicomm K3"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x0000000 0x0080000>; - read-only; - }; - - partition@80000 { - label = "nvram"; - reg = <0x0080000 0x0100000>; - }; - - partition@180000{ - label = "phicomm"; - reg = <0x0180000 0x0280000>; - read-only; - }; - - partition@400000 { - label = "firmware"; - reg = <0x0400000 0x7C00000>; - compatible = "brcm,trx"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi deleted file mode 100644 index 6282363313e1..000000000000 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -#include "bcm4708.dtsi" - -/ { -}; - -&pinctrl { - compatible = "brcm,bcm4709-pinmux"; - - pinmux_mdio: mdio-pins { - groups = "mdio_grp"; - function = "mdio"; - }; -}; - -&usb3_phy { - compatible = "brcm,ns-bx-usb3-phy"; -}; - -&uart0 { - clock-frequency = <125000000>; - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; -}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts deleted file mode 100644 index 0734aa249b8e..000000000000 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573"; - model = "Luxul XAP-1440 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-wlan { - label = "bcm53xx:blue:wlan"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - led-system { - label = "bcm53xx:green:system"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts deleted file mode 100644 index e6fb6cbe6963..000000000000 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; - model = "Luxul XAP-810 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds-0 { - compatible = "gpio-leds"; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - led-system { - label = "bcm53xx:green:system"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - leds-1 { - compatible = "gpio-leds"; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - ranges = <0x00000000 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - pcie0_chipcommon: chipcommon@0 { - reg = <0 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts deleted file mode 100644 index dab2e5f63a72..000000000000 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573"; - model = "Tenda AC9"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds-0 { - compatible = "gpio-leds"; - - led-usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - led-wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - led-system { - label = "bcm53xx:blue:system"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - leds-1 { - compatible = "gpio-leds"; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - ranges = <0x00000000 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - pcie0_chipcommon: chipcommon@0 { - reg = <0 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; -}; - -&switch { - status = "okay"; - - ports { - port@0 { - reg = <0>; - label = "wan"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi deleted file mode 100644 index 7cd38de118c3..000000000000 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm47622", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>, <&CA7_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0"; - reg = <0x1000 0x600>; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts deleted file mode 100644 index 03ad614e6b72..000000000000 --- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Meraki MR26 / Codename: Venom - * - * Copyright (C) 2022 Christian Lamparter - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" -#include - -/ { - compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708"; - model = "Meraki MR26"; - - memory@0 { - reg = <0x00000000 0x08000000>; - device_type = "memory"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_FAULT; - color = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; - panic-indicator; - }; - led-1 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - key-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - clock-frequency = <50000000>; - /delete-property/ clocks; -}; - -&uart1 { - status = "disabled"; -}; - -&gmac0 { - status = "okay"; -}; - -&gmac1 { - status = "disabled"; -}; -&gmac2 { - status = "disabled"; -}; -&gmac3 { - status = "disabled"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <0x1>; - #size-cells = <0x1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x200000>; - read-only; - }; - - partition@200000 { - label = "u-boot-env"; - reg = <0x200000 0x200000>; - /* empty */ - }; - - partition@400000 { - label = "u-boot-backup"; - reg = <0x400000 0x200000>; - /* empty */ - }; - - partition@600000 { - label = "u-boot-env-backup"; - reg = <0x600000 0x200000>; - /* empty */ - }; - - partition@800000 { - label = "ubi"; - reg = <0x800000 0x7780000>; - }; - }; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "poe"; - }; - - port@5 { - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_i2c>; - - clock-frequency = <100000>; - - ina219@40 { - compatible = "ti,ina219"; /* PoE power */ - reg = <0x40>; - shunt-resistor = <60000>; /* = 60 mOhms */ - }; - - eeprom@56 { - compatible = "atmel,24c64"; - reg = <0x56>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - /* it's empty */ - }; -}; - -&thermal { - status = "disabled"; - /* does not work, reads 418 degree Celsius */ -}; diff --git a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts deleted file mode 100644 index c1f54391746f..000000000000 --- a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" -#include -#include - -/ { - model = "D-Link DWL-8610AP"; - compatible = "dlink,dwl-8610ap", "brcm,bcm53016", "brcm,bcm4708"; - - memory@0 { - device_type = "memory"; - /* 512 MB RAM in 2 x Macronix D9PSH chips */ - reg = <0x00000000 0x08000000>, - <0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led-diag { - /* Actually "diag" unclear what this means */ - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-wlan-2g { - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - led-wlan-5g { - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-reset { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* This GPIO is actually stored in NVRAM, but it's not gonna change */ - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - }; - - /* - * Flash memory at 0x1e000000-0x1fffffff - * Macronix 32 64KB blocks; total size 2MB, same that can be - * found attached to the spi_nor SPI controller. - */ - nvram@1e080000 { - compatible = "brcm,nvram"; - reg = <0x1e080000 0x00020000>; - - et0macaddr: et0macaddr { - }; - - et1macaddr: et1macaddr { - }; - }; -}; - -&gmac0 { - nvmem-cells = <&et0macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&gmac1 { - nvmem-cells = <&et1macaddr>; - nvmem-cell-names = "mac-address"; -}; - -&spi_nor { - /* Serial SPI NOR Flash MX 25L1606E */ - status = "okay"; -}; - -&nandcs { - /* - * Spansion S34ML01G100TFI00 128 MB NAND Flash memory - * - * This ECC is a bit unorthodox but it is what the stock firmware - * is using, so to be able to mount the original partitions - * this is necessary. - */ - nand-ecc-strength = <5>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* This is named nflash1.trx in CFE */ - trx@0 { - label = "firmware"; - reg = <0x00000000 0x02800000>; - compatible = "brcm,trx"; - }; - - /* This is named nflash1.trx2 in CFE */ - trx2@2800000 { - label = "firmware2"; - reg = <0x02800000 0x02800000>; - compatible = "brcm,trx"; - }; - - /* This is named nflash1.rwfs in CFE */ - free@5000000 { - label = "free"; - reg = <0x05000000 0x03000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts deleted file mode 100644 index 26c12bfb0bdd..000000000000 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Meraki MR32 / Codename: Espresso - * - * Copyright (C) 2018-2020 Christian Lamparter - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" -#include - -/ { - compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; - model = "Meraki MR32"; - - chosen { - bootargs = " console=ttyS0,115200n8 earlycon"; - }; - - memory@0 { - reg = <0x00000000 0x08000000>; - device_type = "memory"; - }; - - aliases { - serial1 = &uart2; - }; - - leds { - compatible = "gpio-leds"; - - sysled3 { - function = LED_FUNCTION_FAULT; - color = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - panic-indicator; - }; - sysled2 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; - }; - }; - - pwm-leds { - compatible = "pwm-leds"; - - led-0 { - /* SYS-LED 1 - Tricolor */ - function = LED_FUNCTION_INDICATOR; - color = ; - pwms = <&pwm 0 50000 0>; - max-brightness = <255>; - }; - - led-1 { - /* SYS-LED 1 - Tricolor */ - function = LED_FUNCTION_POWER; - color = ; - pwms = <&pwm 1 50000 0>; - max-brightness = <255>; - }; - - led-2 { - /* SYS-LED 1 - Tricolor */ - function = LED_FUNCTION_INDICATOR; - color = ; - pwms = <&pwm 2 50000 0>; - max-brightness = <255>; - }; - }; -}; - -&uart0 { - clock-frequency = <62500000>; - /delete-property/ clocks; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - status = "okay"; - /* - * bluetooth-le { - * compatible = "brcm,bcm20732"; - * enable-gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; - *}; - */ -}; - -&gmac0 { - nvmem-cell-names = "mac-address"; - nvmem-cells = <&mac_address>; -}; - -&gmac1 { - status = "disabled"; -}; -&gmac2 { - status = "disabled"; -}; -&gmac3 { - status = "disabled"; -}; - -&pwm { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_pwm>; -}; - -&nandcs { - partitions { - /* - * The partition autodetection does not work for this device. - * It will only detect the "nvram" partition with an incorrect size. - * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0 - * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0": - * [ 1.733117] 0x000000400000-0x000008000000 : "nvram" - */ - - compatible = "fixed-partitions"; - #address-cells = <0x1>; - #size-cells = <0x1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "bootkernel1"; - reg = <0x100000 0x300000>; - read-only; - }; - - partition@400000 { - label = "nvram"; - reg = <0x400000 0x100000>; - read-only; - }; - - partition@500000 { - label = "bootkernel2"; - reg = <0x500000 0x300000>; - read-only; - }; - - partition@800000 { - label = "ubi"; - reg = <0x800000 0x7780000>; - }; - }; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - label = "poe"; - }; - - port@5 { - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_i2c>; - - clock-frequency = <100000>; - - current_sense: ina219@45 { - compatible = "ti,ina219"; - reg = <0x45>; - shunt-resistor = <60000>; /* = 60 mOhms */ - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi deleted file mode 100644 index c349e8f0afc5..000000000000 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom Northstar NAND. - * - * Copyright (C) 2016 Rafał Miłecki - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <1>; - nand-ecc-step-size = <512>; -}; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi deleted file mode 100644 index 18e25e302b13..000000000000 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016 Luxul Inc. - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; -}; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi deleted file mode 100644 index c8e56d30bd6f..000000000000 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X Nand chip defaults. - * - * This should be included if the NAND controller is on chip select 0 - * and uses 8 bit ECC. - * - * Copyright (C) 2015 Hauke Mehrtens - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; -}; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi deleted file mode 100644 index be9a00ff752d..000000000000 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom Northstar NAND. - * - * Copyright (C) 2015 Hauke Mehrtens - */ - -/ { - nand-controller@18028000 { - nandcs: nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi deleted file mode 100644 index 600a1b54f2ae..000000000000 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, - * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "bcm-ns.dtsi" - -/ { - mpcore-bus@19000000 { - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - - watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - mdio-mux@18003000 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&mdio>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x18003000 0x4>; - mux-mask = <0x200>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - usb3_phy: usb3-phy@10 { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x10>; - usb3-dmp-syscon = <&usb3_dmp>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb3_dmp: syscon@18105000 { - reg = <0x18105000 0x1000>; - }; - - i2c0: i2c@18009000 { - compatible = "brcm,iproc-i2c"; - reg = <0x18009000 0x50>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - dmu-bus@1800c000 { - cru-bus@100 { - lcpll0: clock-controller@100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", - "sdio", "ddr_phy"; - }; - - genpll: clock-controller@140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", - "ethernetclk", - "usbclk", "iprocfast", - "sata1", "sata2"; - }; - }; - }; - - spi@18029200 { - compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; - reg = <0x18029200 0x184>, - <0x18029000 0x124>, - <0x1811b408 0x004>, - <0x180293a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "mspi_done", - "mspi_halted", - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overread"; - clocks = <&iprocmed>; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - - spi_nor: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - status = "disabled"; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts deleted file mode 100644 index 975f854f652f..000000000000 --- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * DTS for Unifi Switch 8 port - * - * Copyright (C) 2017 Florian Fainelli - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm-hr2.dtsi" - -/ { - compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2"; - model = "Ubiquiti UniFi Switch 8 (BCM53342)"; - - /* Hurricane 2 designs use the second UART */ - chosen { - bootargs = "console=ttyS1,115200 earlyprintk"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x68000000 0x08000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - - flash: flash@0 { - compatible = "m25p80"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <12500000>; - spi-cpol; - spi-cpha; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "u-boot-env"; - reg = <0xc0000 0x10000>; - }; - - partition@d0000 { - label = "shmoo"; - reg = <0xd0000 0x10000>; - }; - - partition@e0000 { - label = "kernel0"; - reg = <0xe0000 0xf00000>; - }; - - partition@fe0000 { - label = "kernel1"; - reg = <0xfe0000 0xf10000>; - }; - - partition@1ef0000 { - label = "cfg"; - reg = <0x1ef0000 0x100000>; - }; - - partition@1ff0000 { - label = "EEPROM"; - reg = <0x1ff0000 0x10000>; - }; - }; -}; - -&pcie0 { - /* Attaches to the internal switch */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi deleted file mode 100644 index 3f03a381db0f..000000000000 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - }; - - mpcore@18310000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18310000 0x00008000>; - #address-cells = <1>; - #size-cells = <1>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x0100>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - alp: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - }; - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - - /* IEEE 802.11 0 */ - <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - - /* IEEE 802.11 1 */ - <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon: chipcommon@0 { - compatible = "simple-bus"; - reg = <0x00000000 0x1000>; - ranges; - - #address-cells = <1>; - #size-cells = <1>; - - gpio-controller; - #gpio-cells = <2>; - - uart0: serial@300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&alp>; - status = "okay"; - }; - }; - - pcie0: pcie@2000 { - reg = <0x00002000 0x1000>; - }; - - usb2: usb2@4000 { - reg = <0x4000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - ehci: usb@4000 { - compatible = "generic-ehci"; - reg = <0x4000 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ehci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ehci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - - ohci: usb@d000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; - reg = <0xd000 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ohci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ohci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - - gmac0: ethernet@5000 { - reg = <0x5000 0x1000>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch: switch@1e { - compatible = "brcm,bcm53125"; - reg = <0x1e>; - - status = "disabled"; - - /* ports are defined in board DTS */ - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; - - gmac1: ethernet@b000 { - reg = <0xb000 0x1000>; - }; - - pmu@12000 { - compatible = "simple-mfd", "syscon"; - reg = <0x00012000 0x00001000>; - - ilp: ilp { - compatible = "brcm,bcm53573-ilp"; - clocks = <&alp>; - #clock-cells = <0>; - clock-output-names = "ilp"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/bcm59056.dtsi deleted file mode 100644 index a9bb7ad81378..000000000000 --- a/arch/arm/boot/dts/bcm59056.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* -* Copyright 2014 Linaro Limited -* Author: Matt Porter -*/ - -&pmu { - compatible = "brcm,bcm59056"; - regulators { - rfldo_reg: rfldo { - }; - - camldo1_reg: camldo1 { - }; - - camldo2_reg: camldo2 { - }; - - simldo1_reg: simldo1 { - }; - - simldo2_reg: simldo2 { - }; - - sdldo_reg: sdldo { - }; - - sdxldo_reg: sdxldo { - }; - - mmcldo1_reg: mmcldo1 { - }; - - mmcldo2_reg: mmcldo2 { - }; - - audldo_reg: audldo { - }; - - micldo_reg: micldo { - }; - - usbldo_reg: usbldo { - }; - - vibldo_reg: vibldo { - }; - - csr_reg: csr { - }; - - iosr1_reg: iosr1 { - }; - - iosr2_reg: iosr2 { - }; - - msr_reg: msr { - }; - - sdsr1_reg: sdsr1 { - }; - - sdsr2_reg: sdsr2 { - }; - - vsr_reg: vsr { - }; - - gpldo1_reg: gpldo1 { - }; - - gpldo2_reg: gpldo2 { - }; - - gpldo3_reg: gpldo3 { - }; - - gpldo4_reg: gpldo4 { - }; - - gpldo5_reg: gpldo5 { - }; - - gpldo6_reg: gpldo6 { - }; - - vbus_reg: vbus { - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi deleted file mode 100644 index 93281c47c9ba..000000000000 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Broadcom BCM63138 DSL SoCs Device Tree - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "brcm,bcm63138", "brcm,bcmbca"; - model = "Broadcom BCM963138 Reference Board"; - interrupt-parent = <&gic>; - - aliases { - uart0 = &serial0; - uart1 = &serial1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0>; - enable-method = "brcm,bcm63138"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <1>; - enable-method = "brcm,bcm63138"; - resets = <&pmb0 4 1>; - }; - }; - - clocks { - /* UBUS peripheral clock */ - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "periph"; - }; - - /* peripheral clock for system timer */ - axi_clk: axi_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* APB bus clock */ - apb_clk: apb_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - }; - }; - - /* ARM bus */ - axi@80000000 { - compatible = "simple-bus"; - ranges = <0 0x80000000 0x784000>; - #address-cells = <1>; - #size-cells = <1>; - - L2: cache-controller@1d000 { - compatible = "arm,pl310-cache"; - reg = <0x1d000 0x1000>; - cache-unified; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <1024>; - cache-line-size = <32>; - interrupts = ; - }; - - scu: scu@1e000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000 0x100>; - }; - - gic: interrupt-controller@1f000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x1f000 0x1000 - 0x1e100 0x100>; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - }; - - global_timer: timer@1e200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1e200 0x20>; - interrupts = ; - clocks = <&axi_clk>; - }; - - local_timer: local-timer@1e600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e600 0x20>; - interrupts = ; - clocks = <&axi_clk>; - }; - - twd_watchdog: watchdog@1e620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e620 0x20>; - interrupts = ; - }; - - armpll: armpll@20000 { - #clock-cells = <0>; - compatible = "brcm,bcm63138-armpll"; - clocks = <&periph_clk>; - reg = <0x20000 0xf00>; - }; - - pmb0: reset-controller@4800c0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800c0 0x10>; - #reset-cells = <2>; - }; - - pmb1: reset-controller@4800e0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800e0 0x10>; - #reset-cells = <2>; - }; - - ahci: sata@a000 { - compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0xa000 0x9ac>, <0x8040 0x24>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - resets = <&pmb0 3 1>; - reset-names = "ahci"; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - }; - }; - - sata_phy: sata-phy@8100 { - compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3"; - reg = <0x8100 0x1e00>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - }; - - /* Legacy UBUS base */ - ubus@fffe8000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffe8000 0x8100>; - - timer: timer@80 { - compatible = "brcm,bcm6328-timer", "syscon"; - reg = <0x80 0x3c>; - }; - - serial0: serial@600 { - compatible = "brcm,bcm6345-uart"; - reg = <0x600 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "periph"; - status = "disabled"; - }; - - serial1: serial@620 { - compatible = "brcm,bcm6345-uart"; - reg = <0x620 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "periph"; - status = "disabled"; - }; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0"; - reg = <0x1000 0x600>; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - - nand_controller: nand-controller@2000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; - reg = <0x2000 0x600>, <0xf0 0x10>; - reg-names = "nand", "nand-int-base"; - status = "disabled"; - interrupts = ; - interrupt-names = "nand"; - }; - - bootlut: bootlut@8000 { - compatible = "brcm,bcm63138-bootlut"; - reg = <0x8000 0x50>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&timer>; - offset = <0x34>; - mask = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi deleted file mode 100644 index 24431de1810e..000000000000 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm63148", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - B15_0: cpu@0 { - device_type = "cpu"; - compatible = "brcm,brahma-b15"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B15_1: cpu@1 { - device_type = "cpu"; - compatible = "brcm,brahma-b15"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - ; - interrupt-affinity = <&B15_0>, <&B15_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@80030000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80030000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - interrupts = ; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffe8000 0x8000>; - - uart0: serial@600 { - compatible = "brcm,bcm6345-uart"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0"; - reg = <0x1000 0x600>; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi deleted file mode 100644 index 3f9aed96babf..000000000000 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm63178", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0"; - reg = <0x1000 0x600>; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi deleted file mode 100644 index 1d8d957d65dd..000000000000 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6756", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>, <&CA7_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; - reg = <0x1000 0x600>, <0x2610 0x4>; - reg-names = "hsspi", "spim-ctrl"; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi deleted file mode 100644 index cf92cf8c4693..000000000000 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6846", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0"; - reg = <0x1000 0x600>; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi deleted file mode 100644 index 52d6bc89f9f8..000000000000 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6855", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1"; - reg = <0x1000 0x600>, <0x2610 0x4>; - reg-names = "hsspi", "spim-ctrl"; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi deleted file mode 100644 index 2c5d706bac7e..000000000000 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6878", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - interrupts = ; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - hsspi: spi@1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0"; - reg = <0x1000 0x600>; - interrupts = ; - clocks = <&hsspi_pll &hsspi_pll>; - clock-names = "hsspi", "pll"; - num-cs = <8>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts deleted file mode 100644 index f92d2cf85972..000000000000 --- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm7445.dtsi" - -/ { - model = "Broadcom STB (bcm7445), SVMB reference board"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - - memory@0 { - device_type = "memory"; - reg = <0x00 0x00000000 0x00 0x40000000>, - <0x00 0x40000000 0x00 0x40000000>, - <0x00 0x80000000 0x00 0x40000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@1 { - compatible = "brcm,nandcs"; - reg = <1>; - nand-ecc-step-size = <512>; - nand-ecc-strength = <8>; - nand-on-flash-bbt; - - #size-cells = <2>; - #address-cells = <2>; - - flash1.rootfs0@0 { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - flash1.rootfs1@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi deleted file mode 100644 index 5ac2042515b8..000000000000 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "Broadcom STB (bcm7445)"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <0>; - }; - - cpu@1 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <1>; - }; - - cpu@2 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <2>; - }; - - cpu@3 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <3>; - }; - }; - - gic: interrupt-controller@ffd00000 { - compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; - reg = <0x00 0xffd01000 0x00 0x1000>, - <0x00 0xffd02000 0x00 0x2000>, - <0x00 0xffd04000 0x00 0x2000>, - <0x00 0xffd06000 0x00 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - rdb@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x00 0xf0000000 0x1000000>; - - serial@40ab00 { - compatible = "ns16550a"; - reg = <0x40ab00 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <81000000>; - }; - - sun_top_ctrl: syscon@404000 { - compatible = "brcm,bcm7445-sun-top-ctrl", - "syscon"; - reg = <0x404000 0x51c>; - }; - - hif_cpubiuctrl: syscon@3e2400 { - compatible = "brcm,bcm7445-hif-cpubiuctrl", - "syscon"; - reg = <0x3e2400 0x5b4>; - }; - - hif_continuation: syscon@452000 { - compatible = "brcm,bcm7445-hif-continuation", - "syscon"; - reg = <0x452000 0x100>; - }; - - irq0_intc: interrupt-controller@40a780 { - compatible = "brcm,bcm7120-l2-intc"; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - reg = <0x40a780 0x8>; - interrupt-controller; - interrupts = , - ; - brcm,int-map-mask = <0x25c>, <0x7000000>; - brcm,int-fwd-mask = <0x70000>; - }; - - irq0_aon_intc: interrupt-controller@417280 { - compatible = "brcm,bcm7120-l2-intc"; - reg = <0x417280 0x8>; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = , - , - ; - brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; - brcm,int-fwd-mask = <0x0>; - brcm,irq-can-wake; - }; - - hif_intr2_intc: interrupt-controller@3e1000 { - compatible = "brcm,l2-intc"; - reg = <0x3e1000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-names = "hif"; - }; - - aon_pm_l2_intc: interrupt-controller@410640 { - compatible = "brcm,l2-intc"; - reg = <0x410640 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = ; - interrupt-parent = <&gic>; - brcm,irq-can-wake; - }; - - aon-ctrl@410000 { - compatible = "brcm,brcmstb-aon-ctrl"; - reg = <0x410000 0x200>, <0x410200 0x400>; - reg-names = "aon-ctrl", "aon-sram"; - }; - - nand_controller: nand-controller@3e2800 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; - reg-names = "nand", "flash-dma"; - reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; - interrupt-parent = <&hif_intr2_intc>; - interrupts = <24>, <4>; - interrupt-names = "nand_ctlrdy", "flash_dma_done"; - }; - - sata@45a000 { - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x45a000 0xa9c>, <0x458040 0x24>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - }; - }; - - sata_phy: sata-phy@458100 { - compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; - reg = <0x458100 0x1f00>; - reg-names = "phy"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - upg_gio: gpio@40a700 { - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x40a700 0x80>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupt-parent = <&irq0_intc>; - interrupts = <6>; - brcm,gpio-bank-widths = <32 32 32 24>; - }; - - upg_gio_aon: gpio@4172c0 { - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x4172c0 0x40>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts-extended = <&irq0_aon_intc 0x6>, - <&aon_pm_l2_intc 0x5>; - wakeup-source; - brcm,gpio-bank-widths = <18 4>; - }; - - }; - - memory_controllers@f1100000 { - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf1100000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - memc@0 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - - memc@80000 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - - memc@100000 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - }; - - sram@ffe00000 { - compatible = "brcm,boot-sram", "mmio-sram"; - reg = <0x0 0xffe00000 0x0 0x10000>; - }; - - smpboot { - compatible = "brcm,brcmstb-smpboot"; - syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; - syscon-cont = <&hif_continuation>; - }; - - reboot { - compatible = "brcm,brcmstb-reboot"; - syscon = <&sun_top_ctrl 0x304 0x308>; - }; -}; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts deleted file mode 100644 index 363009e747b3..000000000000 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "dt-bindings/input/input.h" - -/ { - model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; - compatible = "brcm,bcm11360", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-hook { - label = "HOOK"; - linux,code = ; - gpios = <&gpio_asiu 48 0>; - }; - }; -}; - -ð0 { - status = "okay"; -}; - -&mdio { - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&v3d { - assigned-clocks = - <&mipipll BCM_CYGNUS_MIPIPLL>, - <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; - assigned-clock-rates = <525000000>, <300000000>; - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand_controller { - nand@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts deleted file mode 100644 index 091c73a46e08..000000000000 --- a/arch/arm/boot/dts/bcm911360k.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" - -/ { - model = "Cygnus SVK (BCM911360K)"; - compatible = "brcm,bcm11360", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts deleted file mode 100644 index d9eb2040b963..000000000000 --- a/arch/arm/boot/dts/bcm94708.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM94708)"; - compatible = "brcm,bcm94708", "brcm,bcm4708"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts deleted file mode 100644 index 618c812eef73..000000000000 --- a/arch/arm/boot/dts/bcm94709.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM94709)"; - compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts deleted file mode 100644 index 3709baa2376f..000000000000 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2017 Broadcom - * Author: Florian Fainelli - * - * Licensed under the ISC license. - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573"; - model = "Broadcom BCM947189ACDBMR"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - led-5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - led-2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 21 0>; - gpio-miso = <&chipcommon 22 0>; - gpio-mosi = <&chipcommon 23 0>; - cs-gpios = <&chipcommon 24 0>; - #address-cells = <1>; - #size-cells = <0>; - - /* External BCM6802 MoCA chip is connected */ - }; -}; - -&pcie0 { - ranges = <0x00000000 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts deleted file mode 100644 index 93b8ce22678d..000000000000 --- a/arch/arm/boot/dts/bcm947622.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm47622.dtsi" - -/ { - model = "Broadcom BCM947622 Reference Board"; - compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts deleted file mode 100644 index 4fe3b3653376..000000000000 --- a/arch/arm/boot/dts/bcm953012er.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - port@0 { - reg = <0>; - label = "port0"; - }; - - port@1 { - reg = <1>; - label = "port1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts deleted file mode 100644 index b070b69466bd..000000000000 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2017 Broadcom - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - model = "NorthStar HR (BCM953012HR)"; - compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&nandcs { - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x07000000>; - }; -}; - -&spi_nor { - status = "okay"; - spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000d0000>; - }; - partition@d000 { - label = "env"; - reg = <0x000d0000 0x00030000>; - }; - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x00900000>; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts deleted file mode 100644 index f1e6bcaa1edd..000000000000 --- a/arch/arm/boot/dts/bcm953012k.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x07000000>; - }; - }; -}; - -&spi_nor { - status = "okay"; - spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000d0000>; - }; - partition@d000 { - label = "env"; - reg = <0x000d0000 0x00030000>; - }; - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x00900000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts deleted file mode 100644 index dda3e11b711f..000000000000 --- a/arch/arm/boot/dts/bcm958300k.dts +++ /dev/null @@ -1,77 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "bcm9hmidc.dtsi" - -/ { - model = "Cygnus SVK (BCM958300K)"; - compatible = "brcm,bcm58300", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand_controller { - nand@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts deleted file mode 100644 index ea3c6b88b313..000000000000 --- a/arch/arm/boot/dts/bcm958305k.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "bcm9hmidc.dtsi" - -/ { - model = "Cygnus Wireless Audio (BCM958305K)"; - compatible = "brcm,bcm58305", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand_controller { - nand@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts deleted file mode 100644 index 15f023656df0..000000000000 --- a/arch/arm/boot/dts/bcm958522er.dts +++ /dev/null @@ -1,185 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958522ER)"; - compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 support needed to be complete */ - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58522-srab", "brcm,nsp-srab"; -}; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts deleted file mode 100644 index 9b9c225a1fb3..000000000000 --- a/arch/arm/boot/dts/bcm958525er.dts +++ /dev/null @@ -1,197 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958525ER)"; - compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 support needed to be complete */ - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; -}; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts deleted file mode 100644 index ca9311452739..000000000000 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ /dev/null @@ -1,217 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus XMC (BCM958525xmc)"; - compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* XHCI support needed to be complete */ - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "st,m41t81"; - reg = <0x68>; - }; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sdio { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; -}; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts deleted file mode 100644 index 9db3c851451a..000000000000 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958622HR)"; - compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 and SLIC support needed to be complete */ - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&srab { - compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts deleted file mode 100644 index 32786e7c4e12..000000000000 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ /dev/null @@ -1,231 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958623HR)"; - compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 and SLIC support needed to be complete */ - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&srab { - compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi deleted file mode 100644 index c54451dde6dd..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -#include "bcm958625-meraki-mx6x-common.dtsi" - -/ { - keys { - compatible = "gpio-keys-polled"; - autorepeat; - poll-interval = <20>; - - button-reset { - label = "reset"; - linux,code = ; - gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - /* green:wan1-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <0>; - color = ; - gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; - }; - - led-1 { - /* green:wan1-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <1>; - color = ; - gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; - }; - - led-2 { - /* green:wan2-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <2>; - color = ; - gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; - }; - - led-3 { - /* green:wan2-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <3>; - color = ; - gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; - }; - - led-4 { - /* amber:power */ - function = LED_FUNCTION_FAULT; - color = ; - gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; - }; - - led-5 { - /* white:status */ - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&axi { - mdio-mux@3f1c0 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - reg = <0x3f1c0 0x4>; - mux-mask = <0x2000>; - mdio-parent-bus = <&mdio_ext>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - phy_port6: phy@0 { - reg = <0>; - }; - - phy_port7: phy@1 { - reg = <1>; - }; - - phy_port8: phy@2 { - reg = <2>; - }; - - phy_port9: phy@3 { - reg = <3>; - }; - - phy_port10: phy@4 { - reg = <4>; - }; - - switch@10 { - compatible = "qca,qca8337"; - reg = <0x10>; - dsa,member = <1 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - ethernet = <&sgmii1>; - phy-mode = "sgmii"; - qca,sgmii-enable-pll; - qca,sgmii-txclk-falling-edge; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan8"; - phy-handle = <&phy_port6>; - }; - - port@2 { - reg = <2>; - label = "lan9"; - phy-handle = <&phy_port7>; - }; - - port@3 { - reg = <3>; - label = "lan10"; - phy-handle = <&phy_port8>; - }; - - port@4 { - reg = <4>; - label = "lan11"; - phy-handle = <&phy_port9>; - }; - - port@5 { - reg = <5>; - label = "lan12"; - phy-handle = <&phy_port10>; - }; - }; - }; - }; - - mdio-mii@2000 { - reg = <0x2000>; - #address-cells = <1>; - #size-cells = <0>; - - phy_port1: phy@0 { - reg = <0>; - }; - - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - - phy_port4: phy@3 { - reg = <3>; - }; - - phy_port5: phy@4 { - reg = <4>; - }; - - switch@10 { - compatible = "qca,qca8337"; - reg = <0x10>; - dsa,member = <2 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - ethernet = <&sgmii0>; - phy-mode = "sgmii"; - qca,sgmii-enable-pll; - qca,sgmii-txclk-falling-edge; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan3"; - phy-handle = <&phy_port1>; - }; - - port@2 { - reg = <2>; - label = "lan4"; - phy-handle = <&phy_port2>; - }; - - port@3 { - reg = <3>; - label = "lan5"; - phy-handle = <&phy_port3>; - }; - - port@4 { - reg = <4>; - label = "lan6"; - phy-handle = <&phy_port4>; - }; - - port@5 { - reg = <5>; - label = "lan7"; - phy-handle = <&phy_port5>; - }; - }; - }; - }; - }; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - dsa,member = <0 0>; - - ports { - port@0 { - label = "wan1"; - reg = <0>; - }; - - port@1 { - label = "wan2"; - reg = <1>; - }; - - sgmii0: port@4 { - label = "sw0"; - reg = <4>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - sgmii1: port@5 { - label = "sw1"; - reg = <5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@8 { - ethernet = <&amac2>; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi deleted file mode 100644 index 1830844c8404..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -#include "bcm958625-meraki-mx6x-common.dtsi" - -/ { - - keys { - compatible = "gpio-keys-polled"; - autorepeat; - poll-interval = <20>; - - button-reset { - label = "reset"; - linux,code = ; - gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - /* green:lan1-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <0>; - color = ; - gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; - }; - - led-1 { - /* green:lan1-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <1>; - color = ; - gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; - }; - - led-2 { - /* green:lan2-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <2>; - color = ; - gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; - }; - - led-3 { - /* green:lan2-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <3>; - color = ; - gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; - }; - - led-4 { - /* green:lan3-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <4>; - color = ; - gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; - }; - - led-5 { - /* green:lan3-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <5>; - color = ; - gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; - }; - - led-6 { - /* green:lan4-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <6>; - color = ; - gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; - }; - - led-7 { - /* green:lan4-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <7>; - color = ; - gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; - }; - - led-8 { - /* green:wan-left */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <8>; - color = ; - gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; - }; - - led-9 { - /* green:wan-right */ - function = LED_FUNCTION_ACTIVITY; - function-enumerator = <9>; - color = ; - gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; - }; - - led-a { - /* amber:power */ - function = LED_FUNCTION_FAULT; - color = ; - gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; - }; - - led-b { - /* white:status */ - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - port@0 { - label = "lan1"; - reg = <0>; - }; - - port@1 { - label = "lan2"; - reg = <1>; - }; - - port@2 { - label = "lan3"; - reg = <2>; - }; - - port@3 { - label = "lan4"; - reg = <3>; - }; - - port@4 { - label = "wan"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts deleted file mode 100644 index 9944566c1195..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -/dts-v1/; - -#include "bcm958625-meraki-kingpin.dtsi" -#include "bcm-nsp-ax.dtsi" - -/ { - model = "Cisco Meraki MX64(A0)"; - compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts deleted file mode 100644 index 06939438e874..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -/dts-v1/; - -#include "bcm958625-meraki-kingpin.dtsi" - -/ { - model = "Cisco Meraki MX64"; - compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts deleted file mode 100644 index 112fddb1eed8..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -/dts-v1/; - -#include "bcm958625-meraki-kingpin.dtsi" -#include "bcm-nsp-ax.dtsi" - -/ { - model = "Cisco Meraki MX64W(A0)"; - compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts deleted file mode 100644 index de2e367c3e78..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -/dts-v1/; - -#include "bcm958625-meraki-kingpin.dtsi" - -/ { - model = "Cisco Meraki MX64W"; - compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts deleted file mode 100644 index d1b684dcdbfa..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX65. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -/dts-v1/; - -#include "bcm958625-meraki-alamo.dtsi" - -/ { - model = "Cisco Meraki MX65"; - compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts deleted file mode 100644 index a2165aba3676..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Bindings for Cisco Meraki MX65W. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -/dts-v1/; - -#include "bcm958625-meraki-alamo.dtsi" - -/ { - model = "Cisco Meraki MX65W"; - compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi deleted file mode 100644 index b0854d881ac6..000000000000 --- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. - * - * Copyright (C) 2020-2021 Matthew Hagan - */ - -#include "bcm-nsp.dtsi" -#include -#include -#include - -/ { - pwm-leds { - compatible = "pwm-leds"; - - led-1 { - function = LED_FUNCTION_INDICATOR; - color = ; - pwms = <&pwm 1 50000>; - max-brightness = <255>; - }; - - led-2 { - function = LED_FUNCTION_POWER; - color = ; - pwms = <&pwm 2 50000>; - max-brightness = <255>; - }; - - led-3 { - function = LED_FUNCTION_INDICATOR; - color = ; - pwms = <&pwm 3 50000>; - max-brightness = <255>; - }; - }; -}; - -&amac2 { - status = "okay"; - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "shmoo"; - reg = <0x80000 0x80000>; - read-only; - }; - - partition@100000 { - label = "bootkernel1"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { - label = "nvram"; - reg = <0x400000 0x100000>; - }; - - partition@500000 { - label = "bootkernel2"; - reg = <0x500000 0x300000>; - }; - - partition@800000 { - label = "ubi"; - reg = <0x800000 0x3f700000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_leds>; - - pwm_leds: pwm_leds { - function = "pwm"; - groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; - }; -}; - -&pwm { - status = "okay"; - #pwm-cells = <2>; -}; - -&uart0 { - clock-frequency = <62500000>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts deleted file mode 100644 index 74263d98de73..000000000000 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ /dev/null @@ -1,254 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958625HR)"; - compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x20000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; - - sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; - los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@5 { - label = "sfp"; - phy-mode = "sgmii"; - reg = <5>; - sfp = <&sfp>; - managed = "in-band-status"; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts deleted file mode 100644 index 69ebc7a913a7..000000000000 --- a/arch/arm/boot/dts/bcm958625k.dts +++ /dev/null @@ -1,271 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" - -/ { - model = "NorthStar Plus SVK (BCM958625K)"; - compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>; - - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; - - gpiobs: gpiobs { - function = "gpio_b"; - groups = "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", - "gpio_b_3_grp"; - }; - - pwmc: pwmc { - function = "pwm"; - groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; - }; - - emmc_sel: emmc_sel { - function = "emmc"; - groups = "emmc_grp"; - }; -}; - -&pwm { - status = "okay"; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -/* - * By default the sd slot is functional. For emmc to work add "<&emmc_sel>" - * and delete "<&nand_sel>" in "pinctrl-0" property of pinctrl node. Remove the - * bus-width property here and disable the nand node with status = "disabled";. - * - * Ex: pinctrl-0 = <&emmc_sel>, <&gpiobs>, <&pwmc>; - */ -&sdio { - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/bcm963138.dts deleted file mode 100644 index 1b405c249213..000000000000 --- a/arch/arm/boot/dts/bcm963138.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63138.dtsi" - -/ { - model = "Broadcom BCM963138 Reference Board"; - compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts deleted file mode 100644 index b5af61853a07..000000000000 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Broadcom BCM63138 Reference Board DTS - */ - -/dts-v1/; - -#include "bcm63138.dtsi" - -/ { - compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca"; - model = "Broadcom BCM963138DVT"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - brcm,nand-oob-sectors-size = <16>; - }; -}; - -&ahci { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts deleted file mode 100644 index 1f5d6d783f09..000000000000 --- a/arch/arm/boot/dts/bcm963148.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63148.dtsi" - -/ { - model = "Broadcom BCM963148 Reference Board"; - compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts deleted file mode 100644 index d036e99dd8d1..000000000000 --- a/arch/arm/boot/dts/bcm963178.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63178.dtsi" - -/ { - model = "Broadcom BCM963178 Reference Board"; - compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts deleted file mode 100644 index 8b104f3fb14a..000000000000 --- a/arch/arm/boot/dts/bcm96756.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6756.dtsi" - -/ { - model = "Broadcom BCM96756 Reference Board"; - compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts deleted file mode 100644 index 55852c229608..000000000000 --- a/arch/arm/boot/dts/bcm96846.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6846.dtsi" - -/ { - model = "Broadcom BCM96846 Reference Board"; - compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts deleted file mode 100644 index 2ad880af2104..000000000000 --- a/arch/arm/boot/dts/bcm96855.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6855.dtsi" - -/ { - model = "Broadcom BCM96855 Reference Board"; - compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts deleted file mode 100644 index b7af8ade7a9d..000000000000 --- a/arch/arm/boot/dts/bcm96878.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6878.dtsi" - -/ { - model = "Broadcom BCM96878 Reference Board"; - compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&hsspi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts deleted file mode 100644 index e96bc3f2d5cf..000000000000 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ /dev/null @@ -1,231 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM988312HR)"; - compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 support needed to be complete */ - -&dma { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand_controller { - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm9hmidc.dtsi b/arch/arm/boot/dts/bcm9hmidc.dtsi deleted file mode 100644 index 65397c088335..000000000000 --- a/arch/arm/boot/dts/bcm9hmidc.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Broadcom human machine interface daughter card (bcm9hmidc) installed on - * bcm958300k/bcm958305k boards - */ - -&touchscreen { - touchscreen-inverted-x; - touchscreen-inverted-y; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts deleted file mode 100644 index 64a297759eb9..000000000000 --- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Sony NSZ-GS7 - * - * Sebastian Hesselbarth - */ - -/dts-v1/; - -#include "berlin2.dtsi" - -/ { - model = "Sony NSZ-GS7"; - compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; -}; - -&ahci { status = "okay"; }; - -ð1 { status = "okay"; }; - -/* Unpopulated SATA plug on solder side */ -&sata0 { status = "okay"; }; - -&sata_phy { status = "okay"; }; - -/* Samsung M8G2FA 8GB eMMC */ -&sdhci2 { - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi deleted file mode 100644 index 1114c592e461..000000000000 --- a/arch/arm/boot/dts/berlin2.dtsi +++ /dev/null @@ -1,540 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC - * - * Sebastian Hesselbarth - * - * based on GPL'ed 2.6 kernel sources - * (c) Marvell International Ltd. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500 (BG2) SoC"; - compatible = "marvell,berlin2", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu@0 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu@1 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - ranges = <0 0xf7000000 0x1000000>; - - sdhci0: mmc@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: mmc@ab0800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci2: mmc@ab1000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab1000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; - clock-names = "io", "core"; - pinctrl-0 = <&emmc_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - l2: cache-controller@ac0000 { - compatible = "marvell,tauros3-cache", "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu: snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x58>; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - eth1: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH1>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy1>; - status = "disabled"; - - ethphy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - cpu-ctrl@dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xdd0000 0x10000>; - }; - - eth0: ethernet@e50000 { - compatible = "marvell,pxa168-eth"; - reg = <0xe50000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - interrupts = <8>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - interrupts = <9>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - interrupts = <10>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - interrupts = <11>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - interrupts = <12>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - interrupts = <13>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - interrupts = <14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - interrupts = <15>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - ahci: sata@e90000 { - compatible = "marvell,berlin2-ahci", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - status = "disabled"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - status = "disabled"; - }; - }; - - sata_phy: phy@e900a0 { - compatible = "marvell,berlin2-sata-phy"; - reg = <0xe900a0 0x200>; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - status = "disabled"; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - chip_clk: clock { - compatible = "marvell,berlin2-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2-soc-pinctrl"; - - emmc_pmux: emmc-pmux { - groups = "G26"; - function = "emmc"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - }; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <11>; - }; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <8>; - clocks = <&refclk>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <9>; - clocks = <&refclk>; - pinctrl-0 = <&uart1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@b000 { - compatible = "snps,dw-apb-uart"; - reg = <0xb000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <10>; - clocks = <&refclk>; - pinctrl-0 = <&uart2_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2-system-pinctrl"; - uart0_pmux: uart0-pmux { - groups = "GSM4"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM5"; - function = "uart1"; - }; - uart2_pmux: uart2-pmux { - groups = "GSM3"; - function = "uart2"; - }; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts deleted file mode 100644 index c1d91424e658..000000000000 --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Google Chromecast - * - * Sebastian Hesselbarth - */ - -/dts-v1/; - -#include "berlin2cd.dtsi" -#include - -/ { - model = "Google Chromecast"; - compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - - /* - * We're using "linux,usable-memory" instead of "reg" here - * because the (signed and encrypted) bootloader that shipped - * with this device provides an incorrect memory range in - * ATAG_MEM. Linux helpfully overrides the "reg" property with - * data from the ATAG, so we can't specify the proper range - * normally. Fortunately, this alternate property is checked - * first by the OF driver, so we can (ab)use it instead. - */ - linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */ - }; - - led-controller { - compatible = "pwm-leds"; - pinctrl-0 = <&ledpwm_pmux>; - pinctrl-names = "default"; - - led-1 { - label = "white"; - pwms = <&pwm 0 600000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led-2 { - label = "red"; - pwms = <&pwm 1 600000 0>; - max-brightness = <255>; - }; - }; -}; - -/* - * AzureWave AW-NH387 (Marvell 88W8787) - * 802.11b/g/n + Bluetooth 2.1 - */ -&sdhci0 { - non-removable; - status = "okay"; -}; - -&uart0 { status = "okay"; }; - -&usb_phy1 { status = "okay"; }; - -&usb1 { status = "okay"; }; - -&soc_pinctrl { - ledpwm_pmux: ledpwm-pmux { - groups = "G0"; - function = "pwm"; - }; -}; diff --git a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts deleted file mode 100644 index 79ac842ae461..000000000000 --- a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Alexander Monakov - */ -/dts-v1/; - -#include "berlin2cd.dtsi" -#include - -/ { - model = "Valve Steam Link"; - compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&porta 6 GPIO_ACTIVE_HIGH>; - active-delay = <100>; - inactive-delay = <10>; - wait-delay = <100>; - priority = <200>; - }; -}; - -&cpu { - cpu-supply = <&vcpu>; - operating-points = < - /* kHz uV */ - 1000000 1325000 - >; -}; - -&i2c0 { - status = "okay"; - - /* There are two regulators on the board. One is accessible via I2C, - * with buck1 providing SoC power (set up by bootloader to 1.325V or - * less depending on leakage value in OTP), and buck2 likely used for - * DRAM (providing 1.35V). The other regulator on the opposite side - * of the board is probably supplying SDIO and NAND fixed voltages. */ - regulator@19 { - compatible = "marvell,88pg868"; - reg = <0x19>; - - vcpu: buck1 { - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1325000>; - }; - }; -}; - -/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */ -&sdhci0 { - keep-power-in-suspend; - non-removable; - status = "okay"; -}; - -&uart0 { - /* RX/TX are routed to TP50/TP51 on the board. */ - status = "okay"; -}; - -/* The SoC is connected to on-board USB hub that in turn has one downstream - * port wired to the on-board Steam Controller wireless receiver chip. */ -&usb_phy1 { status = "okay"; }; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -ð1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi deleted file mode 100644 index b2768f7a3185..000000000000 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ /dev/null @@ -1,583 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC - * - * Sebastian Hesselbarth - * - * based on GPL'ed 2.6 kernel sources - * (c) Marvell International Ltd. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500-mini (BG2CD) SoC"; - compatible = "marvell,berlin2cd", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 800000 1200000 - 600000 1200000 - >; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - ranges = <0 0xf7000000 0x1000000>; - - sdhci0: mmc@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - l2: cache-controller@ac0000 { - compatible = "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x100>; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - global-timer@ad0200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xad0200 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - local-wdt@ad0620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xad0620 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - usb_phy0: usb-phy@b74000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb74000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x178 23>; - status = "disabled"; - }; - - usb_phy1: usb-phy@b78000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb78000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x178 24>; - status = "disabled"; - }; - - eth1: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH1>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy1>; - status = "disabled"; - - ethphy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - eth0: ethernet@e50000 { - compatible = "marvell,pxa168-eth"; - reg = <0xe50000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - i2c0: i2c@1400 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1400 0x100>; - interrupts = <16>; - clocks = <&chip_clk CLKID_CFG>; - status = "disabled"; - }; - - i2c1: i2c@1800 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800 0x100>; - interrupts = <17>; - clocks = <&chip_clk CLKID_CFG>; - status = "disabled"; - }; - - spi0: spi@1c00 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1c00 0x100>; - interrupts = <4>; - clocks = <&chip_clk CLKID_CFG>; - status = "disabled"; - }; - - wdt4: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&chip_clk CLKID_CFG>; - interrupts = <5>; - status = "disabled"; - }; - - wdt5: watchdog@2400 { - compatible = "snps,dw-wdt"; - reg = <0x2400 0x100>; - clocks = <&chip_clk CLKID_CFG>; - interrupts = <6>; - status = "disabled"; - }; - - wdt6: watchdog@2800 { - compatible = "snps,dw-wdt"; - reg = <0x2800 0x100>; - clocks = <&chip_clk CLKID_CFG>; - interrupts = <7>; - status = "disabled"; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - interrupts = <8>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - interrupts = <9>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - interrupts = <10>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - interrupts = <11>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - interrupts = <12>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - interrupts = <13>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - interrupts = <14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - interrupts = <15>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - chip_clk: clock { - compatible = "marvell,berlin2-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2cd-soc-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "G6"; - function = "uart0"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - usb0: usb@ed0000 { - compatible = "chipidea,usb2"; - reg = <0xed0000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb1: usb@ee0000 { - compatible = "chipidea,usb2"; - reg = <0xee0000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_USB1>; - phys = <&usb_phy1>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - status = "disabled"; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - status = "disabled"; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - }; - }; - - spi1: spi@6000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6000 0x100>; - clocks = <&refclk>; - interrupts = <5>; - status = "disabled"; - }; - - i2c2: i2c@7000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x100>; - interrupts = <6>; - clocks = <&refclk>; - status = "disabled"; - }; - - i2c3: i2c@8000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x8000 0x100>; - interrupts = <7>; - clocks = <&refclk>; - status = "disabled"; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0>; - }; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <8>; - clocks = <&refclk>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <9>; - clocks = <&refclk>; - status = "disabled"; - }; - - uart2: serial@b000 { - compatible = "snps,dw-apb-uart"; - reg = <0xb000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <10>; - clocks = <&refclk>; - status = "disabled"; - }; - - sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2cd-system-pinctrl"; - }; - - adc: adc { - compatible = "marvell,berlin2-adc"; - interrupts = <12>, <14>; - interrupt-names = "adc", "tsen"; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts deleted file mode 100644 index c162f98cb8e8..000000000000 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2014 Antoine Ténart - */ - -/dts-v1/; - -#include -#include "berlin2q.dtsi" - -/ { - model = "Marvell BG2-Q DMP"; - compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator_usb0 { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator_usb1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb2_vbus: regulator_usb2 { - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sdio1_vmmc: regulator_sdio1_vmmc { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "sdio1_vmmc"; - enable-active-high; - regulator-boot-on; - gpio = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - - reg_sdio1_vqmmc: regulator_sido1_vqmmc { - compatible = "regulator-gpio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "sdio1_vqmmc"; - regulator-type = "voltage"; - enable-active-high; - gpios = <&portb 16 GPIO_ACTIVE_HIGH>; - states = <3300000 0x1 - 1800000 0x0>; - }; - }; -}; - -&soc_pinctrl { - sd1gpio_pmux: sd1pwr-pmux { - groups = "G23", "G32"; - function = "gpio"; - }; -}; - -&sdhci1 { - vmmc-supply = <®_sdio1_vmmc>; - vqmmc-supply = <®_sdio1_vqmmc>; - cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>; - wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy2 { - status = "okay"; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb2 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -ð0 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi deleted file mode 100644 index 6edaefa617a5..000000000000 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ /dev/null @@ -1,666 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2014 Antoine Ténart - */ - -#include -#include - -/ { - model = "Marvell Armada 1500 pro (BG2-Q) SoC"; - compatible = "marvell,berlin2q", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <2>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <3>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xf7000000 0x1000000>; - interrupt-parent = <&gic>; - - sdhci0: mmc@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: mmc@ab0800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci2: mmc@ab1000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab1000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - status = "disabled"; - }; - - l2: cache-controller@ac0000 { - compatible = "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <2 2 2>; - arm,tag-latency = <2 2 2>; - }; - - scu: snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x58>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - clocks = <&chip_clk CLKID_TWD>; - interrupts = ; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - usb_phy2: phy@a2f400 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xa2f400 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 14>; - status = "disabled"; - }; - - usb2: usb@a30000 { - compatible = "chipidea,usb2"; - reg = <0xa30000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB2>; - phys = <&usb_phy2>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb_phy0: phy@b74000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb74000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 12>; - status = "disabled"; - }; - - usb_phy1: phy@b78000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb78000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 13>; - status = "disabled"; - }; - - eth0: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - cpu-ctrl@dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xdd0000 0x10000>; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - i2c0: i2c@1400 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1400 0x100>; - interrupts = <4>; - clocks = <&chip_clk CLKID_CFG>; - pinctrl-0 = <&twsi0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c1: i2c@1800 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800 0x100>; - interrupts = <5>; - clocks = <&chip_clk CLKID_CFG>; - pinctrl-0 = <&twsi1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - interrupts = <8>; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3800 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3800 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>, <0xdd0170 0x10>; - - chip_clk: clock { - compatible = "marvell,berlin2q-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2q-soc-pinctrl"; - - sd1_pmux: sd1-pmux { - groups = "G31"; - function = "sd1"; - }; - - twsi0_pmux: twsi0-pmux { - groups = "G6"; - function = "twsi0"; - }; - - twsi1_pmux: twsi1-pmux { - groups = "G7"; - function = "twsi1"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - ahci: sata@e90000 { - compatible = "marvell,berlin2q-ahci", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - status = "disabled"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - status = "disabled"; - }; - }; - - sata_phy: phy@e900a0 { - compatible = "marvell,berlin2q-sata-phy"; - reg = <0xe900a0 0x200>; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - status = "disabled"; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; - - usb0: usb@ed0000 { - compatible = "chipidea,usb2"; - reg = <0xed0000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb1: usb@ee0000 { - compatible = "chipidea,usb2"; - reg = <0xee0000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB1>; - phys = <&usb_phy1>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - }; - }; - - i2c2: i2c@7000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x100>; - interrupts = <6>; - clocks = <&refclk>; - pinctrl-0 = <&twsi2_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c3: i2c@8000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x8000 0x100>; - interrupts = <7>; - clocks = <&refclk>; - pinctrl-0 = <&twsi3_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - interrupts = <8>; - clocks = <&refclk>; - reg-shift = <2>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - interrupts = <9>; - clocks = <&refclk>; - reg-shift = <2>; - pinctrl-0 = <&uart1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - }; - }; - - sysctrl: pin-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2q-system-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM14"; - function = "uart1"; - }; - - twsi2_pmux: twsi2-pmux { - groups = "GSM13"; - function = "twsi2"; - }; - - twsi3_pmux: twsi3-pmux { - groups = "GSM14"; - function = "twsi3"; - }; - }; - - adc: adc { - compatible = "marvell,berlin2-adc"; - interrupts = <12>, <14>; - interrupt-names = "adc", "tsen"; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile new file mode 100644 index 000000000000..95b0ef2a4215 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays +DTC_FLAGS_bcm2835-rpi-b := -@ +DTC_FLAGS_bcm2835-rpi-a := -@ +DTC_FLAGS_bcm2835-rpi-b-rev2 := -@ +DTC_FLAGS_bcm2835-rpi-b-plus := -@ +DTC_FLAGS_bcm2835-rpi-a-plus := -@ +DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ +DTC_FLAGS_bcm2836-rpi-2-b := -@ +DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ +DTC_FLAGS_bcm2837-rpi-3-b := -@ +DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ +DTC_FLAGS_bcm2837-rpi-cm3-io3 := -@ +DTC_FLAGS_bcm2837-rpi-zero-2-w := -@ +DTC_FLAGS_bcm2711-rpi-400 := -@ +DTC_FLAGS_bcm2711-rpi-4-b := -@ +DTC_FLAGS_bcm2711-rpi-cm4-io := -@ +DTC_FLAGS_bcm2835-rpi-zero := -@ +DTC_FLAGS_bcm2835-rpi-zero-w := -@ +dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2835-rpi-b.dtb \ + bcm2835-rpi-a.dtb \ + bcm2835-rpi-b-rev2.dtb \ + bcm2835-rpi-b-plus.dtb \ + bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-cm1-io1.dtb \ + bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb \ + bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ + bcm2711-rpi-cm4-io.dtb \ + bcm2835-rpi-zero.dtb \ + bcm2835-rpi-zero-w.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb \ + bcm963138.dtb \ + bcm963138dvt.dtb \ + bcm963148.dtb \ + bcm963178.dtb \ + bcm96756.dtb \ + bcm96846.dtb \ + bcm96855.dtb \ + bcm96878.dtb +dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp2.dtb \ + bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-linksys-ea6500-v2.dtb \ + bcm4708-luxul-xap-1510.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ + bcm4708-smartrg-sr400ac.dtb \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb \ + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm47081-luxul-xap-1410.dtb \ + bcm47081-luxul-xwr-1200.dtb \ + bcm47081-tplink-archer-c5-v2.dtb \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-linksys-ea9200.dtb \ + bcm4709-netgear-r7000.dtb \ + bcm4709-netgear-r8000.dtb \ + bcm4709-tplink-archer-c9-v1.dtb \ + bcm47094-asus-rt-ac88u.dtb \ + bcm47094-dlink-dir-885l.dtb \ + bcm47094-dlink-dir-890l.dtb \ + bcm47094-linksys-panamera.dtb \ + bcm47094-luxul-abr-4500.dtb \ + bcm47094-luxul-xap-1610.dtb \ + bcm47094-luxul-xbr-4500.dtb \ + bcm47094-luxul-xwc-2000.dtb \ + bcm47094-luxul-xwr-3100.dtb \ + bcm47094-luxul-xwr-3150-v1.dtb \ + bcm47094-netgear-r8500.dtb \ + bcm47094-phicomm-k3.dtb \ + bcm53015-meraki-mr26.dtb \ + bcm53016-dlink-dwl-8610ap.dtb \ + bcm53016-meraki-mr32.dtb \ + bcm94708.dtb \ + bcm94709.dtb \ + bcm953012er.dtb \ + bcm953012hr.dtb \ + bcm953012k.dtb +dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-luxul-xap-1440.dtb \ + bcm47189-luxul-xap-810.dtb \ + bcm47189-tenda-ac9.dtb \ + bcm947189acdbmr.dtb +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ + bcm911360_entphn.dtb \ + bcm911360k.dtb \ + bcm958300k.dtb \ + bcm958305k.dtb +dtb-$(CONFIG_ARCH_BCM_HR2) += \ + bcm53340-ubnt-unifi-switch8.dtb +dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ + bcm28155-ap.dtb \ + bcm21664-garnet.dtb \ + bcm23550-sparrow.dtb +dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958522er.dtb \ + bcm958525er.dtb \ + bcm958525xmc.dtb \ + bcm958622hr.dtb \ + bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ + bcm958625-meraki-mx65.dtb \ + bcm958625-meraki-mx65w.dtb \ + bcm958625hr.dtb \ + bcm988312hr.dtb \ + bcm958625k.dtb +dtb-$(CONFIG_ARCH_BRCMSTB) += \ + bcm7445-bcm97445svmb.dtb diff --git a/arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi new file mode 100644 index 000000000000..52f91a12a99a --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi @@ -0,0 +1,133 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + /* Cygnus ARM PLL */ + armpll: armpll@19000000 { + #clock-cells = <0>; + compatible = "brcm,cygnus-armpll"; + clocks = <&osc>; + reg = <0x19000000 0x1000>; + }; + + /* peripheral clock for system timer */ + periph_clk: arm_periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* APB bus clock */ + apb_clk: apb_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <4>; + clock-mult = <1>; + }; + + genpll: genpll@301d000 { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; + clocks = <&osc>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; + }; + + /* always 1/2 of the axi21 clock */ + axi41_clk: axi41_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll 1>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* always 1/4 of the axi21 clock */ + axi81_clk: axi81_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll 1>; + clock-div = <4>; + clock-mult = <1>; + }; + + lcpll0: lcpll0@301d02c { + #clock-cells = <1>; + compatible = "brcm,cygnus-lcpll0"; + reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio", + "usb_phy", "smart_card", "ch5"; + }; + + mipipll: mipipll@180a9800 { + #clock-cells = <1>; + compatible = "brcm,cygnus-mipipll"; + reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; + clocks = <&osc>; + clock-output-names = "mipipll", "ch0_unused", "ch1_lcd", + "ch2_v3d", "ch3_unused", "ch4_unused", + "ch5_unused"; + }; + + asiu_clks: asiu_clks@301d048 { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x0301d048 0xc>, <0x180aa024 0x4>; + + clocks = <&osc>; + clock-output-names = "keypad", "adc/touch", "pwm"; + }; + + audiopll: audiopll@180aeb00 { + #clock-cells = <1>; + compatible = "brcm,cygnus-audiopll"; + reg = <0x180aeb00 0x68>; + clocks = <&osc>; + clock-output-names = "audiopll", "ch0_audio", + "ch1_audio", "ch2_audio"; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi new file mode 100644 index 000000000000..f9f79ed82518 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi @@ -0,0 +1,623 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,cygnus"; + model = "Broadcom Cygnus SoC"; + interrupt-parent = <&gic>; + + aliases { + ethernet0 = ð0; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; + + /include/ "bcm-cygnus-clock.dtsi" + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + core@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + axi { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + otp: otp@301c800 { + compatible = "brcm,ocotp"; + reg = <0x0301c800 0x2c>; + brcm,ocotp-size = <2048>; + status = "disabled"; + }; + + pcie_phy: pcie_phy@301d0a0 { + compatible = "brcm,cygnus-pcie-phy"; + reg = <0x0301d0a0 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_phy: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_phy: pcie-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + pinctrl: pinctrl@301d0c8 { + compatible = "brcm,cygnus-pinmux"; + reg = <0x0301d0c8 0x30>, + <0x0301d24c 0x2c>; + + spi_0: spi_0 { + function = "spi0"; + groups = "spi0_grp"; + }; + + spi_1: spi_1 { + function = "spi1"; + groups = "spi1_grp"; + }; + + spi_2: spi_2 { + function = "spi2"; + groups = "spi2_grp"; + }; + }; + + mailbox: mailbox@3024024 { + compatible = "brcm,iproc-mailbox"; + reg = <0x03024024 0x40>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-controller; + #mbox-cells = <1>; + }; + + gpio_crmu: gpio@3024800 { + compatible = "brcm,cygnus-crmu-gpio"; + reg = <0x03024800 0x50>, + <0x03024008 0x18>; + ngpios = <6>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&mailbox>; + interrupts = <0>; + }; + + mdio: mdio@18002000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18002000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + status = "disabled"; + + gphy0: ethernet-phy@0 { + reg = <0>; + }; + + gphy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + switch: switch@18007000 { + compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; + reg = <0x18007000 0x1000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&gphy0>; + phy-mode = "rgmii"; + }; + + port@1 { + reg = <1>; + phy-handle = <&gphy1>; + phy-mode = "rgmii"; + }; + + port@8 { + reg = <8>; + label = "cpu"; + ethernet = <ð0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + i2c0: i2c@18008000 { + compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; + reg = <0x18008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + wdt0: wdt@18009000 { + compatible = "arm,sp805" , "arm,primecell"; + reg = <0x18009000 0x1000>; + interrupts = ; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + gpio_ccm: gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + ngpios = <24>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + interrupt-controller; + }; + + i2c1: i2c@1800b000 { + compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; + reg = <0x1800b000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + phys = <&pcie0_phy>; + phy-names = "pcie-phy"; + + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + phys = <&pcie1_phy>; + phy-names = "pcie-phy"; + + status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + dma0: dma@18018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x18018000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&apb_clk>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + uart0: serial@18020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18020000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart1: serial@18021000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18021000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart2: serial@18022000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18022000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart3: serial@18023000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18023000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + spi0: spi@18028000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x18028000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-0 = <&spi_0>; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; + status = "disabled"; + }; + + spi1: spi@18029000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x18029000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-0 = <&spi_1>; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; + status = "disabled"; + }; + + spi2: spi@1802a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1802a000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-0 = <&spi_2>; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; + status = "disabled"; + }; + + rng: rng@18032000 { + compatible = "brcm,iproc-rng200"; + reg = <0x18032000 0x28>; + }; + + sdhci0: sdhci@18041000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x18041000 0x100>; + interrupts = ; + clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; + bus-width = <4>; + sdhci,auto-cmd12; + status = "disabled"; + }; + + eth0: ethernet@18042000 { + compatible = "brcm,amac"; + reg = <0x18042000 0x1000>, + <0x18110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + status = "disabled"; + }; + + sdhci1: sdhci@18043000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x18043000 0x100>; + interrupts = ; + clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; + bus-width = <4>; + sdhci,auto-cmd12; + status = "disabled"; + }; + + nand_controller: nand-controller@18046000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x18046000 0x600>, <0xf8105408 0x600>, + <0x18046f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + ehci0: usb@18048000 { + compatible = "generic-ehci"; + reg = <0x18048000 0x100>; + interrupts = ; + status = "disabled"; + }; + + ohci0: usb@18048800 { + compatible = "generic-ohci"; + reg = <0x18048800 0x100>; + interrupts = ; + status = "disabled"; + }; + + clcd: clcd@180a0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x180a0000 0x1000>; + interrupts = ; + interrupt-names = "combined"; + clocks = <&axi41_clk>, <&apb_clk>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + + v3d: v3d@180a2000 { + compatible = "brcm,cygnus-v3d"; + reg = <0x180a2000 0x1000>; + clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; + clock-names = "v3d_clk"; + interrupts = ; + status = "disabled"; + }; + + vc4: gpu { + compatible = "brcm,cygnus-vc4"; + }; + + gpio_asiu: gpio@180a5000 { + compatible = "brcm,cygnus-asiu-gpio"; + reg = <0x180a5000 0x668>; + ngpios = <146>; + #gpio-cells = <2>; + gpio-controller; + + interrupt-controller; + interrupts = ; + gpio-ranges = <&pinctrl 0 42 1>, + <&pinctrl 1 44 3>, + <&pinctrl 4 48 1>, + <&pinctrl 5 50 3>, + <&pinctrl 8 126 1>, + <&pinctrl 9 155 1>, + <&pinctrl 10 152 1>, + <&pinctrl 11 154 1>, + <&pinctrl 12 153 1>, + <&pinctrl 13 127 3>, + <&pinctrl 16 140 1>, + <&pinctrl 17 145 7>, + <&pinctrl 24 130 10>, + <&pinctrl 34 141 4>, + <&pinctrl 38 54 1>, + <&pinctrl 39 56 3>, + <&pinctrl 42 60 3>, + <&pinctrl 45 64 3>, + <&pinctrl 48 68 2>, + <&pinctrl 50 84 6>, + <&pinctrl 56 94 6>, + <&pinctrl 62 72 1>, + <&pinctrl 63 70 1>, + <&pinctrl 64 80 1>, + <&pinctrl 65 74 3>, + <&pinctrl 68 78 1>, + <&pinctrl 69 82 1>, + <&pinctrl 70 156 17>, + <&pinctrl 87 104 12>, + <&pinctrl 99 102 2>, + <&pinctrl 101 90 4>, + <&pinctrl 105 116 6>, + <&pinctrl 111 100 2>, + <&pinctrl 113 122 4>, + <&pinctrl 123 11 1>, + <&pinctrl 124 38 4>, + <&pinctrl 128 43 1>, + <&pinctrl 129 47 1>, + <&pinctrl 130 49 1>, + <&pinctrl 131 53 1>, + <&pinctrl 132 55 1>, + <&pinctrl 133 59 1>, + <&pinctrl 134 63 1>, + <&pinctrl 135 67 1>, + <&pinctrl 136 71 1>, + <&pinctrl 137 73 1>, + <&pinctrl 138 77 1>, + <&pinctrl 139 79 1>, + <&pinctrl 140 81 1>, + <&pinctrl 141 83 1>, + <&pinctrl 142 10 1>; + }; + + ts_adc_syscon: ts_adc_syscon@180a6000 { + compatible = "brcm,iproc-ts-adc-syscon", "syscon"; + reg = <0x180a6000 0xc30>; + }; + + touchscreen: touchscreen@180a6000 { + compatible = "brcm,iproc-touchscreen"; + #address-cells = <1>; + #size-cells = <1>; + ts_syscon = <&ts_adc_syscon>; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; + clock-names = "tsc_clk"; + interrupts = ; + status = "disabled"; + }; + + adc: adc@180a6000 { + compatible = "brcm,iproc-static-adc"; + #io-channel-cells = <1>; + adc-syscon = <&ts_adc_syscon>; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; + clock-names = "tsc_clk"; + interrupts = ; + status = "disabled"; + }; + + pwm: pwm@180aa500 { + compatible = "brcm,kona-pwm"; + reg = <0x180aa500 0xc4>; + #pwm-cells = <3>; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; + status = "disabled"; + }; + + keypad: keypad@180ac000 { + compatible = "brcm,bcm-keypad"; + reg = <0x180ac000 0x14c>; + interrupts = ; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; + clock-names = "peri_clk"; + clock-frequency = <31250>; + pull-up-enabled; + col-debounce-filter-period = <0>; + status-debounce-filter-period = <0>; + row-output-enabled; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi new file mode 100644 index 000000000000..33e6ba63a1ee --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi @@ -0,0 +1,368 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/ { + compatible = "brcm,hr2"; + model = "Broadcom Hurricane 2 SoC"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + }; + + mpcore@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,hr2-armpll"; + clocks = <&osc>; + reg = <0x0 0x1000>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x0011c40c>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupts = ; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550a"; + reg = <0x0400 0x100>; + interrupts = ; + clocks = <&osc>; + status = "disabled"; + }; + + dma@20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + status = "disabled"; + }; + + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x22000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + status = "disabled"; + }; + + nand_controller: nand-controller@26000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x26000 0x600>, + <0x11b408 0x600>, + <0x026f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + gpiob: gpio@30000 { + compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = ; + }; + + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + rng: rng@33000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x33000 0x14>; + }; + + qspi: spi@27200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* partitions defined in board DTS */ + }; + + ccbtimer0: timer@34000 { + compatible = "arm,sp804"; + reg = <0x34000 0x1000>; + interrupts = , + ; + }; + + ccbtimer1: timer@35000 { + compatible = "arm,sp804"; + reg = <0x35000 0x1000>; + interrupts = , + ; + }; + + i2c0: i2c@38000 { + compatible = "brcm,iproc-i2c"; + reg = <0x38000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + }; + + watchdog: watchdog@39000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x39000 0x1000>; + interrupts = ; + }; + + i2c1: i2c@3b000 { + compatible = "brcm,iproc-i2c"; + reg = <0x3b000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + }; + }; + + pflash: nor@20000000 { + compatible = "cfi-flash", "jedec-flash"; + reg = <0x20000000 0x04000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + + /* partitions defined in board DTS */ + }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi new file mode 100644 index 000000000000..dae9c47ace76 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2013-2014 Hauke Mehrtens + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chipcommon-a-bus@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550"; + reg = <0x0300 0x100>; + interrupts = ; + clocks = <&iprocslow>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550"; + reg = <0x0400 0x100>; + interrupts = ; + clocks = <&iprocslow>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1>; + status = "disabled"; + }; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + scu@20000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x20000 0x100>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; + cache-level = <2>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; + }; + + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; + }; + + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + ehci: usb@21000 { + compatible = "generic-ehci"; + reg = <0x00021000 0x1000>; + interrupts = ; + phys = <&usb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@22000 { + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + }; + + usb3: usb3@23000 { + reg = <0x00023000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + xhci: usb@23000 { + compatible = "generic-xhci"; + reg = <0x00023000 0x1000>; + interrupts = ; + phys = <&usb3_phy>; + phy-names = "usb"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; + }; + + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; + + gmac1: ethernet@25000 { + reg = <0x25000 0x800>; + }; + + gmac2: ethernet@26000 { + reg = <0x26000 0x800>; + }; + + gmac3: ethernet@27000 { + reg = <0x27000 0x800>; + }; + }; + + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; + + srab: ethernet-switch@18007000 { + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + ethernet = <&gmac0>; + }; + + port@7 { + reg = <7>; + ethernet = <&gmac1>; + }; + + port@8 { + reg = <8>; + ethernet = <&gmac2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + + pinctrl: pinctrl@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + groups = "spi_grp"; + function = "spi"; + }; + + pinmux_i2c: i2c-pins { + groups = "i2c_grp"; + function = "i2c"; + }; + + pinmux_pwm: pwm-pins { + groups = "pwm0_grp", "pwm1_grp", + "pwm2_grp", "pwm3_grp"; + function = "pwm"; + }; + + pinmux_uart1: uart1-pins { + groups = "uart1_grp"; + function = "uart1"; + }; + }; + + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + }; + }; + + nand_controller: nand-controller@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi new file mode 100644 index 000000000000..f2e941dbab10 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar Plus Ax stepping-specific bindings. + * Notable differences from B0+ are the secondary-boot-reg and + * lack of DMA coherency. + */ + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&dma { + /delete-property/ dma-coherent; +}; + +&sdio { + /delete-property/ dma-coherent; +}; + +&amac0 { + /delete-property/ dma-coherent; +}; + +&amac1 { + /delete-property/ dma-coherent; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&xhci { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&sata { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; +}; + +&pcie1 { + /delete-property/ dma-coherent; +}; + +&pcie2 { + /delete-property/ dma-coherent; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi new file mode 100644 index 000000000000..5b1dc58d40ba --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi @@ -0,0 +1,695 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,nsp"; + model = "Broadcom Northstar Plus SoC"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = &amac0; + ethernet1 = &amac1; + ethernet2 = &amac2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + enable-method = "brcm,bcm-nsp-smp"; + secondary-boot-reg = <0xffff0fec>; + reg = <0x1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + twd-watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi: axi@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x0011c40c>; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@20 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x0020 0x70>, + <0x3f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + interrupt-controller; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + uart0: serial@300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupts = ; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550a"; + reg = <0x0400 0x100>; + interrupts = ; + clocks = <&osc>; + status = "disabled"; + }; + + dma: dma@20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + dma-coherent; + status = "disabled"; + }; + + sdio: mmc@21000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x21000 0x100>; + interrupts = ; + sdhci,auto-cmd12; + clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; + dma-coherent; + status = "disabled"; + }; + + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x022000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + amac1: ethernet@23000 { + compatible = "brcm,nsp-amac"; + reg = <0x023000 0x1000>, + <0x111000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + amac2: ethernet@24000 { + compatible = "brcm,nsp-amac"; + reg = <0x024000 0x1000>, + <0x112000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + mailbox: mailbox@25c00 { + compatible = "brcm,iproc-fa2-mbox"; + reg = <0x25c00 0x400>; + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + dma-coherent; + }; + + nand_controller: nand-controller@26000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x026000 0x600>, + <0x11b408 0x600>, + <0x026f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + qspi: spi@27200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xhci: usb@29000 { + compatible = "generic-xhci"; + reg = <0x29000 0x1000>; + interrupts = ; + phys = <&usb3_phy>; + phy-names = "usb3-phy"; + dma-coherent; + status = "disabled"; + }; + + ehci0: usb@2a000 { + compatible = "generic-ehci"; + reg = <0x2a000 0x100>; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + ohci0: usb@2b000 { + compatible = "generic-ohci"; + reg = <0x2b000 0x100>; + interrupts = ; + dma-coherent; + status = "disabled"; + }; + + crypto@2f000 { + compatible = "brcm,spum-nsp-crypto"; + reg = <0x2f000 0x900>; + mboxes = <&mailbox 0>; + }; + + gpiob: gpio@30000 { + compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = ; + }; + + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio: mdio@32000 { + compatible = "brcm,iproc-mdio"; + reg = <0x32000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + mdio-mux@32000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + reg = <0x32000 0x4>; + mux-mask = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + mdio-parent-bus = <&mdio>; + + mdio_int: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-bx-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + mdio_ext: mdio@200 { + reg = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rng: rng@33000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x33000 0x14>; + }; + + ccbtimer0: timer@34000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x34000 0x1000>; + interrupts = , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + + ccbtimer1: timer@35000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x35000 0x1000>; + interrupts = , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + + srab: ethernet-switch@36000 { + compatible = "brcm,nsp-srab"; + reg = <0x36000 0x1000>, + <0x3f308 0x8>, + <0x3f410 0xc>; + reg-names = "srab", "mux_config", "sgmii_config"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "link_state_p0", + "link_state_p1", + "link_state_p2", + "link_state_p3", + "link_state_p4", + "link_state_p5", + "link_state_p7", + "link_state_p8", + "phy", + "ts", + "imp_sleep_timer_p5", + "imp_sleep_timer_p7", + "imp_sleep_timer_p8"; + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c0: i2c@38000 { + compatible = "brcm,iproc-i2c"; + reg = <0x38000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + dma-coherent; + status = "disabled"; + }; + + watchdog@39000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x39000 0x1000>; + interrupts = ; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + lcpll0: lcpll0@3f100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x3f100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@3f140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x3f140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; + + pinctrl: pinctrl@3f1c0 { + compatible = "brcm,nsp-pinmux"; + reg = <0x3f1c0 0x04>, + <0x30028 0x04>, + <0x3f408 0x04>; + }; + + thermal: thermal@3f2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x3f2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + + sata_phy: sata_phy@40100 { + compatible = "brcm,iproc-nsp-sata-phy"; + reg = <0x40100 0x340>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + sata: sata@41000 { + compatible = "brcm,bcm-nsp-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0x41000 0x1000>, <0x40020 0x1c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + dma-coherent; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + phy-names = "sata-phy"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + phy-names = "sata-phy"; + }; + }; + + usb3_dmp: syscon@104000 { + reg = <0x104000 0x1000>; + }; + }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + dma-coherent; + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + dma-coherent; + status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + pcie2: pcie@18014000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18014000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <2>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; + + dma-coherent; + status = "disabled"; + + msi-parent = <&msi2>; + msi2: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm11351.dtsi b/arch/arm/boot/dts/broadcom/bcm11351.dtsi new file mode 100644 index 000000000000..b271a9bf06a9 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm11351.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012-2013 Broadcom Corporation + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "BCM11351 SoC"; + compatible = "brcm,bcm11351"; + interrupt-parent = <&gic>; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x3500417c>; + reg = <1>; + }; + }; + + gic: interrupt-controller@3ff00100 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x3ff01000 0x1000>, + <0x3ff00100 0x100>; + }; + + smc@3404c000 { + compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; + reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ + }; + + uartb: serial@3e000000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e000000 0x1000>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb2: serial@3e001000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e001000 0x1000>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb3: serial@3e002000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e002000 0x1000>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb4: serial@3e003000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e003000 0x1000>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + L2: l2-cache@3ff20000 { + compatible = "brcm,bcm11351-a2-pl310-cache"; + reg = <0x3ff20000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + watchdog@35002f40 { + compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; + reg = <0x35002f40 0x6c>; + }; + + timer@35006000 { + compatible = "brcm,kona-timer"; + reg = <0x35006000 0x1000>; + interrupts = ; + clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; + }; + + gpio: gpio@35003000 { + compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; + reg = <0x35003000 0x800>; + interrupts = + ; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + sdio1: mmc@3f180000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f180000 0x10000>; + interrupts = ; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; + status = "disabled"; + }; + + sdio2: mmc@3f190000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f190000 0x10000>; + interrupts = ; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; + status = "disabled"; + }; + + sdio3: mmc@3f1a0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f1a0000 0x10000>; + interrupts = ; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; + status = "disabled"; + }; + + sdio4: mmc@3f1b0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f1b0000 0x10000>; + interrupts = ; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; + status = "disabled"; + }; + + pinctrl@35004800 { + compatible = "brcm,bcm11351-pinctrl"; + reg = <0x35004800 0x430>; + }; + + bsc1: i2c@3e016000 { + compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; + reg = <0x3e016000 0x80>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; + status = "disabled"; + }; + + bsc2: i2c@3e017000 { + compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; + reg = <0x3e017000 0x80>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; + status = "disabled"; + }; + + bsc3: i2c@3e018000 { + compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; + reg = <0x3e018000 0x80>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; + status = "disabled"; + }; + + pmu_bsc: i2c@3500d000 { + compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; + reg = <0x3500d000 0x80>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; + status = "disabled"; + }; + + pwm: pwm@3e01a000 { + compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; + reg = <0x3e01a000 0xcc>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + root_ccu: root_ccu@35001000 { + compatible = "brcm,bcm11351-root-ccu"; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + hub_ccu: hub_ccu@34000000 { + compatible = "brcm,bcm11351-hub-ccu"; + reg = <0x34000000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "tmon_1m"; + }; + + aon_ccu: aon_ccu@35002000 { + compatible = "brcm,bcm11351-aon-ccu"; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer", + "pmu_bsc", + "pmu_bsc_var"; + }; + + master_ccu: master_ccu@3f001000 { + compatible = "brcm,bcm11351-master-ccu"; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "usb_ic", + "hsic2_48m", + "hsic2_12m"; + }; + + slave_ccu: slave_ccu@3e011000 { + compatible = "brcm,bcm11351-slave-ccu"; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "uartb4", + "ssp0", + "ssp2", + "bsc1", + "bsc2", + "bsc3", + "pwm"; + }; + + ref_1m_clk: ref_1m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + }; + + ref_32k_clk: ref_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + bbl_32k_clk: bbl_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + ref_13m_clk: ref_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + var_13m_clk: var_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + dft_19_5m_clk: dft_19_5m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; + }; + + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + ref_cx40_clk: ref_cx40 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + + ref_52m_clk: ref_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + var_52m_clk: var_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + usb_otg_ahb_clk: usb_otg_ahb { + compatible = "fixed-clock"; + clock-frequency = <52000000>; + #clock-cells = <0>; + }; + + ref_96m_clk: ref_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + var_96m_clk: var_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + ref_104m_clk: ref_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + var_104m_clk: var_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + ref_156m_clk: ref_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + var_156m_clk: var_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + ref_208m_clk: ref_208m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; + }; + + var_208m_clk: var_208m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; + }; + + ref_312m_clk: ref_312m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <312000000>; + }; + + var_312m_clk: var_312m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <312000000>; + }; + }; + + usbotg: usb@3f120000 { + compatible = "snps,dwc2"; + reg = <0x3f120000 0x10000>; + interrupts = ; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usbphy: usb-phy@3f130000 { + compatible = "brcm,kona-usb2-phy"; + reg = <0x3f130000 0x28>; + #phy-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts b/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts new file mode 100644 index 000000000000..8789fae178bf --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Broadcom Corporation + +/dts-v1/; + +#include + +#include "bcm21664.dtsi" + +/ { + model = "BCM21664 Garnet board"; + compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; + +&sdio1 { + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio2 { + non-removable; + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio4 { + max-frequency = <48000000>; + cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uartb { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm21664.dtsi b/arch/arm/boot/dts/broadcom/bcm21664.dtsi new file mode 100644 index 000000000000..2eb7f5b0c1dc --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm21664.dtsi @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Broadcom Corporation + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "BCM21664 SoC"; + compatible = "brcm,bcm21664"; + interrupt-parent = <&gic>; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x35004178>; + reg = <1>; + }; + }; + + gic: interrupt-controller@3ff00100 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x3ff01000 0x1000>, + <0x3ff00100 0x100>; + }; + + smc@3404e000 { + compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; + reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ + }; + + uartb: serial@3e000000 { + compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e000000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb2: serial@3e001000 { + compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e001000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb3: serial@3e002000 { + compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; + reg = <0x3e002000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + L2: cache-controller@3ff20000 { + compatible = "arm,pl310-cache"; + reg = <0x3ff20000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + brcm,resetmgr@35001f00 { + compatible = "brcm,bcm21664-resetmgr"; + reg = <0x35001f00 0x24>; + }; + + timer@35006000 { + compatible = "brcm,kona-timer"; + reg = <0x35006000 0x1c>; + interrupts = ; + clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; + }; + + gpio: gpio@35003000 { + compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; + reg = <0x35003000 0x524>; + interrupts = + ; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + sdio1: mmc@3f180000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f180000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; + status = "disabled"; + }; + + sdio2: mmc@3f190000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f190000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; + status = "disabled"; + }; + + sdio3: mmc@3f1a0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f1a0000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; + status = "disabled"; + }; + + sdio4: mmc@3f1b0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f1b0000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; + status = "disabled"; + }; + + bsc1: i2c@3e016000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e016000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; + status = "disabled"; + }; + + bsc2: i2c@3e017000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e017000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; + status = "disabled"; + }; + + bsc3: i2c@3e018000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e018000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; + status = "disabled"; + }; + + bsc4: i2c@3e01c000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e01c000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; + status = "disabled"; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * Fixed clocks are defined before CCUs whose + * clocks may depend on them. + */ + + ref_32k_clk: ref_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + bbl_32k_clk: bbl_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + ref_13m_clk: ref_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + var_13m_clk: var_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + dft_19_5m_clk: dft_19_5m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; + }; + + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + ref_52m_clk: ref_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + var_52m_clk: var_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + usb_otg_ahb_clk: usb_otg_ahb { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + ref_96m_clk: ref_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + var_96m_clk: var_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + ref_104m_clk: ref_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + var_104m_clk: var_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + ref_156m_clk: ref_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + var_156m_clk: var_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + root_ccu: root_ccu@35001000 { + compatible = "brcm,bcm21664-root-ccu"; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + aon_ccu: aon_ccu@35002000 { + compatible = "brcm,bcm21664-aon-ccu"; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer"; + }; + + master_ccu: master_ccu@3f001000 { + compatible = "brcm,bcm21664-master-ccu"; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "sdio1_sleep", + "sdio2_sleep", + "sdio3_sleep", + "sdio4_sleep"; + }; + + slave_ccu: slave_ccu@3e011000 { + compatible = "brcm,bcm21664-slave-ccu"; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "bsc1", + "bsc2", + "bsc3", + "bsc4"; + }; + }; + + usbotg: usb@3f120000 { + compatible = "snps,dwc2"; + reg = <0x3f120000 0x10000>; + interrupts = ; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usbphy: usb-phy@3f130000 { + compatible = "brcm,kona-usb2-phy"; + reg = <0x3f130000 0x28>; + #phy-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts b/arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts new file mode 100644 index 000000000000..ace77709f468 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts @@ -0,0 +1,81 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include + +#include "bcm23550.dtsi" + +/ { + model = "BCM23550 Sparrow board"; + compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550"; + + chosen { + stdout-path = "/slaves@3e000000/serial@0:115200n8"; + bootargs = "console=ttyS0,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&uartb { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&sdio1 { + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio2 { + non-removable; + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio4 { + max-frequency = <48000000>; + cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm23550.dtsi b/arch/arm/boot/dts/broadcom/bcm23550.dtsi new file mode 100644 index 000000000000..445eadb8d871 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm23550.dtsi @@ -0,0 +1,414 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* BCM23550 and BCM21664 have almost identical clocks */ +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "BCM23550 SoC"; + compatible = "brcm,bcm23550"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x35004178>; + reg = <1>; + clock-frequency = <1000000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x35004178>; + reg = <2>; + clock-frequency = <1000000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x35004178>; + reg = <3>; + clock-frequency = <1000000000>; + }; + }; + + /* Hub bus */ + hub@34000000 { + compatible = "simple-bus"; + ranges = <0 0x34000000 0x102f83ac>; + #address-cells = <1>; + #size-cells = <1>; + + smc@4e000 { + compatible = "brcm,bcm23550-smc", "brcm,kona-smc"; + reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ + }; + + resetmgr: reset-controller@1001f00 { + compatible = "brcm,bcm21664-resetmgr"; + reg = <0x01001f00 0x24>; + }; + + gpio: gpio@1003000 { + compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; + reg = <0x01003000 0x524>; + interrupts = + ; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + timer@1006000 { + compatible = "brcm,kona-timer"; + reg = <0x01006000 0x1c>; + interrupts = ; + clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; + }; + }; + + /* Slaves bus */ + slaves@3e000000 { + compatible = "simple-bus"; + ranges = <0 0x3e000000 0x0001c070>; + #address-cells = <1>; + #size-cells = <1>; + + uartb: serial@0 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb2: serial@1000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00001000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uartb3: serial@2000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00002000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + bsc1: i2c@16000 { + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; + reg = <0x00016000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; + status = "disabled"; + }; + + bsc2: i2c@17000 { + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; + reg = <0x00017000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; + status = "disabled"; + }; + + bsc3: i2c@18000 { + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; + reg = <0x00018000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; + status = "disabled"; + }; + + bsc4: i2c@1c000 { + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; + reg = <0x0001c000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; + status = "disabled"; + }; + }; + + /* Apps bus */ + apps@3e300000 { + compatible = "simple-bus"; + ranges = <0 0x3e300000 0x01b77000>; + #address-cells = <1>; + #size-cells = <1>; + + usbotg: usb@e20000 { + compatible = "snps,dwc2"; + reg = <0x00e20000 0x10000>; + interrupts = ; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usbphy: usb-phy@e30000 { + compatible = "brcm,kona-usb2-phy"; + reg = <0x00e30000 0x28>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdio1: mmc@e80000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00e80000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; + status = "disabled"; + }; + + sdio2: mmc@e90000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00e90000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; + status = "disabled"; + }; + + sdio3: mmc@ea0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00ea0000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; + status = "disabled"; + }; + + sdio4: mmc@eb0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00eb0000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; + status = "disabled"; + }; + + cdc: cdc@1b0e000 { + compatible = "brcm,bcm23550-cdc"; + reg = <0x01b0e000 0x78>; + }; + + gic: interrupt-controller@1b21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x01b21000 0x1000>, + <0x01b22000 0x1000>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * Fixed clocks are defined before CCUs whose + * clocks may depend on them. + */ + + ref_32k_clk: ref_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + bbl_32k_clk: bbl_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + ref_13m_clk: ref_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + var_13m_clk: var_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + dft_19_5m_clk: dft_19_5m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; + }; + + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + ref_52m_clk: ref_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + var_52m_clk: var_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + usb_otg_ahb_clk: usb_otg_ahb { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + ref_96m_clk: ref_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + var_96m_clk: var_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + ref_104m_clk: ref_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + var_104m_clk: var_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + ref_156m_clk: ref_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + var_156m_clk: var_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + root_ccu: root_ccu@35001000 { + compatible = "brcm,bcm21664-root-ccu"; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + aon_ccu: aon_ccu@35002000 { + compatible = "brcm,bcm21664-aon-ccu"; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer"; + }; + + slave_ccu: slave_ccu@3e011000 { + compatible = "brcm,bcm21664-slave-ccu"; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "bsc1", + "bsc2", + "bsc3", + "bsc4"; + }; + + master_ccu: master_ccu@3f001000 { + compatible = "brcm,bcm21664-master-ccu"; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "sdio1_sleep", + "sdio2_sleep", + "sdio3_sleep", + "sdio4_sleep"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts new file mode 100644 index 000000000000..d5f8823230db --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711.dtsi" +#include "bcm2711-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-peripheral.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; + model = "Raspberry Pi 4 Model B"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + sd_io_1v8_reg: regulator-sd-io-1v8 { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + status = "okay"; + }; + + sd_vcc_reg: regulator-sd-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&bt { + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +}; + +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; +}; + +&expgpio { + gpio-line-names = "BT_ON", /* 0 */ + "WL_ON", + "PWR_LED_OFF", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", /* 5 */ + "SD_PWR_ON", + ""; +}; + +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", /* 0 */ + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", /* 5 */ + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", /* 10 */ + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", /* 15 */ + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", /* 20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", /* 25 */ + "GPIO26", + "GPIO27", + "RGMII_MDIO", + "RGMIO_MDC", + /* Used by BT module */ + "CTS0", /* 30 */ + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", /* 35 */ + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + /* Shared with SPI flash */ + "PWM0_MISO", /* 40 */ + "PWM1_MOSI", + "STATUS_LED_G_CLK", + "SPIFLASH_CE_N", + "SDA0", + "SCL0", /* 45 */ + "RGMII_RXCLK", + "RGMII_RXCTL", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", /* 50 */ + "RGMII_RXD3", + "RGMII_TXCLK", + "RGMII_TXCTL", + "RGMII_TXD0", + "RGMII_TXD1", /* 55 */ + "RGMII_TXD2", + "RGMII_TXD3"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&led_act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led_pwr: led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; + status = "okay"; +}; + +/* EMMC2 is used to drive the SD card */ +&emmc2 { + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + broken-cd; + status = "okay"; +}; + +&genet { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&genet_mdio { + phy1: ethernet-phy@1 { + /* No PHY interrupt */ + reg = <0x1>; + }; +}; + +&pcie0 { + pci@0,0 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + reg = <0 0 0 0 0>; + + usb@0,0 { + reg = <0 0 0 0 0>; + resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; + }; + }; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; + uart-has-rtscts; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; + +&wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts new file mode 100644 index 000000000000..1ab8184302db --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711-rpi-4-b.dts" + +/ { + compatible = "raspberrypi,400", "brcm,bcm2711"; + model = "Raspberry Pi 400"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "GLOBAL_SHUTDOWN", + "SD_PWR_ON", + "SHUTDOWN_REQUEST"; +}; + +&genet_mdio { + clock-frequency = <1950000>; +}; + +&led_pwr { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&leds { + /delete-node/ led_act; +}; + +&pm { + /delete-property/ system-power-controller; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts new file mode 100644 index 000000000000..d7ba02f586d3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711-rpi-cm4.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + model = "Raspberry Pi Compute Module 4 IO Board"; +}; + +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; +}; + +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "RGMII_MDIO", + "RGMIO_MDC", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + /* Shared with SPI flash */ + "PWM0_MISO", + "PWM1_MOSI", + "STATUS_LED_G_CLK", + "SPIFLASH_CE_N", + "SDA0", + "SCL0", + "RGMII_RXCLK", + "RGMII_RXCTL", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", + "RGMII_RXD3", + "RGMII_TXCLK", + "RGMII_TXCTL", + "RGMII_TXD0", + "RGMII_TXD1", + "RGMII_TXD2", + "RGMII_TXD3"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&genet { + status = "okay"; +}; + +&led_act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi new file mode 100644 index 000000000000..48e63ab7848c --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711.dtsi" +#include "bcm2711-rpi.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,4-compute-module", "brcm,bcm2711"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + sd_io_1v8_reg: regulator-sd-io-1v8 { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + status = "okay"; + }; + + sd_vcc_reg: regulator-sd-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&bt { + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +}; + +/* EMMC2 is used to drive the eMMC */ +&emmc2 { + bus-width = <8>; + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + broken-cd; + /* Even the IP block is limited to 100 MHz + * this provides a throughput gain + */ + mmc-hs200-1_8v; + status = "okay"; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "ANT1", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + "ANT2"; + + ant1: ant1-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + /* internal antenna enabled */ + output-high; + line-name = "ant1"; + }; + + ant2: ant2-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + /* external antenna disabled */ + output-low; + line-name = "ant2"; + }; +}; + +&genet { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&genet_mdio { + phy1: ethernet-phy@0 { + /* No PHY interrupt */ + reg = <0x0>; + }; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; + uart-has-rtscts; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi new file mode 100644 index 000000000000..98817a6675b9 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +#include + +/ { + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0>; + }; + + aliases { + emmc2bus = &emmc2bus; + ethernet0 = &genet; + pcie0 = &pcie0; + blconfig = &blconfig; + }; +}; + +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; +}; + +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&rmem { + /* + * RPi4's co-processor will copy the board's bootloader configuration + * into memory for the OS to consume. It'll also update this node with + * its placement information. + */ + blconfig: nvram@0 { + compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; +}; + +&v3d { + clocks = <&firmware_clocks 5>; +}; + +&vchiq { + interrupts = ; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi new file mode 100644 index 000000000000..097e9f252235 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -0,0 +1,1172 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm283x.dtsi" + +#include +#include + +/ { + compatible = "brcm,bcm2711"; + + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gicv2>; + + vc4: gpu { + compatible = "brcm,bcm2711-vc5"; + status = "disabled"; + }; + + clk_27MHz: clk-27M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "27MHz-clock"; + }; + + clk_108MHz: clk-108M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <108000000>; + clock-output-names = "108MHz-clock"; + }; + + soc { + /* + * Defined ranges: + * Common BCM283x peripherals + * BCM2711-specific peripherals + * ARM-local peripherals + */ + ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, + <0x7c000000 0x0 0xfc000000 0x02000000>, + <0x40000000 0x0 0xff800000 0x00800000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; + + /* + * This node is the provider for the enable-method for + * bringing up secondary cores. + */ + local_intc: interrupt-controller@40000000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x40000000 0x100>; + }; + + gicv2: interrupt-controller@40041000 { + interrupt-controller; + #interrupt-cells = <3>; + compatible = "arm,gic-400"; + reg = <0x40041000 0x1000>, + <0x40042000 0x2000>, + <0x40044000 0x2000>, + <0x40046000 0x2000>; + interrupts = ; + }; + + avs_monitor: avs-monitor@7d5d2000 { + compatible = "brcm,bcm2711-avs-monitor", + "syscon", "simple-mfd"; + reg = <0x7d5d2000 0xf00>; + + thermal: thermal { + compatible = "brcm,bcm2711-thermal"; + #thermal-sensor-cells = <0>; + }; + }; + + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xb00>; + interrupts = , + , + , + , + , + , + , + /* DMA lite 7 - 10 */ + , + , + , + ; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5", + "dma6", + "dma7", + "dma8", + "dma9", + "dma10"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x07f5>; + }; + + pm: watchdog@7e100000 { + compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>, + <0x7ec11000 0x20>; + reg-names = "pm", "asb", "rpivid_asb"; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; + }; + + rng@7e104000 { + compatible = "brcm,bcm2711-rng200"; + reg = <0x7e104000 0x28>; + }; + + uart2: serial@7e201400 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201400 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart3: serial@7e201600 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201600 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart4: serial@7e201800 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201800 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + uart5: serial@7e201a00 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201a00 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + spi3: spi@7e204600 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204600 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@7e204800 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204800 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@7e204a00 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204a00 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@7e204c00 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204c00 0x0200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@7e205600 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205600 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@7e205800 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205800 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@7e205a00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205a00 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@7e205c00 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + reg = <0x7e205c00 0x200>; + interrupts = ; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pixelvalve0: pixelvalve@7e206000 { + compatible = "brcm,bcm2711-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pixelvalve1: pixelvalve@7e207000 { + compatible = "brcm,bcm2711-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pixelvalve2: pixelvalve@7e20a000 { + compatible = "brcm,bcm2711-pixelvalve2"; + reg = <0x7e20a000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pwm1: pwm@7e20c800 { + compatible = "brcm,bcm2835-pwm"; + reg = <0x7e20c800 0x28>; + clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clock-rates = <10000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pixelvalve4: pixelvalve@7e216000 { + compatible = "brcm,bcm2711-pixelvalve4"; + reg = <0x7e216000 0x100>; + interrupts = ; + status = "disabled"; + }; + + hvs: hvs@7e400000 { + compatible = "brcm,bcm2711-hvs"; + reg = <0x7e400000 0x8000>; + interrupts = ; + }; + + pixelvalve3: pixelvalve@7ec12000 { + compatible = "brcm,bcm2711-pixelvalve3"; + reg = <0x7ec12000 0x100>; + interrupts = ; + status = "disabled"; + }; + + vec: vec@7ec13000 { + compatible = "brcm,bcm2711-vec"; + reg = <0x7ec13000 0x1000>; + clocks = <&clocks BCM2835_CLOCK_VEC>; + interrupts = ; + status = "disabled"; + }; + + dvp: clock@7ef00000 { + compatible = "brcm,brcm2711-dvp"; + reg = <0x7ef00000 0x10>; + clocks = <&clk_108MHz>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + aon_intr: interrupt-controller@7ef00100 { + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; + reg = <0x7ef00100 0x30>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + hdmi0: hdmi@7ef00700 { + compatible = "brcm,bcm2711-hdmi0"; + reg = <0x7ef00700 0x300>, + <0x7ef00300 0x200>, + <0x7ef00f00 0x80>, + <0x7ef00f80 0x80>, + <0x7ef01b00 0x200>, + <0x7ef01f00 0x400>, + <0x7ef00200 0x80>, + <0x7ef04300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 0>; + interrupt-parent = <&aon_intr>; + interrupts = <0>, <1>, <2>, + <3>, <4>, <5>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", + "wakeup", "hpd-connected", "hpd-removed"; + ddc = <&ddc0>; + dmas = <&dma 10>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc0: i2c@7ef04500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; + + hdmi1: hdmi@7ef05700 { + compatible = "brcm,bcm2711-hdmi1"; + reg = <0x7ef05700 0x300>, + <0x7ef05300 0x200>, + <0x7ef05f00 0x80>, + <0x7ef05f80 0x80>, + <0x7ef06b00 0x200>, + <0x7ef06f00 0x400>, + <0x7ef00280 0x80>, + <0x7ef09300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + ddc = <&ddc1>; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 1>; + interrupt-parent = <&aon_intr>; + interrupts = <8>, <7>, <6>, + <9>, <10>, <11>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", + "wakeup", "hpd-connected", "hpd-removed"; + dmas = <&dma 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc1: i2c@7ef09500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; + }; + + /* + * emmc2 has different DMA constraints based on SoC revisions. It was + * moved into its own bus, so as for RPi4's firmware to update them. + * The firmware will find whether the emmc2bus alias is defined, and if + * so, it'll edit the dma-ranges property below accordingly. + */ + emmc2bus: emmc2bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; + dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; + + emmc2: mmc@7e340000 { + compatible = "brcm,bcm2711-emmc2"; + reg = <0x0 0x7e340000 0x100>; + interrupts = ; + clocks = <&clocks BCM2711_CLOCK_EMMC2>; + status = "disabled"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + /* This only applies to the ARMv7 stub */ + arm,cpu-registers-not-fw-configured; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-1-Memory-System/About-the-L1-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-2-Memory-System/About-the-L2-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ + l2: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set + cache-level = <2>; + }; + }; + + scb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, + <0x6 0x00000000 0x6 0x00000000 0x40000000>; + + pcie0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 144 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 145 + IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 146 + IRQ_TYPE_LEVEL_HIGH>; + msi-controller; + msi-parent = <&pcie0>; + + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 + 0x0 0x04000000>; + /* + * The wrapper around the PCIe block has a bug + * preventing it from accessing beyond the first 3GB of + * memory. + */ + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0xc0000000>; + brcm,enable-ssc; + }; + + genet: ethernet@7d580000 { + compatible = "brcm,bcm2711-genet-v5"; + reg = <0x0 0x7d580000 0x10000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + interrupts = , + ; + status = "disabled"; + + genet_mdio: mdio@e14 { + compatible = "brcm,genet-mdio-v5"; + reg = <0xe14 0x8>; + reg-names = "mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + }; + + v3d: gpu@7ec00000 { + compatible = "brcm,2711-v3d"; + reg = <0x0 0x7ec00000 0x4000>, + <0x0 0x7ec04000 0x4000>; + reg-names = "hub", "core0"; + + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; + resets = <&pm BCM2835_RESET_V3D>; + interrupts = ; + }; + }; +}; + +&clk_osc { + clock-frequency = <54000000>; +}; + +&clocks { + compatible = "brcm,bcm2711-cprman"; +}; + +&cpu_thermal { + coefficients = <(-487) 410040>; + thermal-sensors = <&thermal>; +}; + +&dsi0 { + interrupts = ; +}; + +&dsi1 { + interrupts = ; + compatible = "brcm,bcm2711-dsi1"; +}; + +&gpio { + compatible = "brcm,bcm2711-gpio"; + interrupts = , + , + , + ; + + gpio-ranges = <&gpio 0 0 58>; + + gpclk0_gpio49: gpclk0-gpio49 { + pin-gpclk { + pins = "gpio49"; + function = "alt1"; + bias-disable; + }; + }; + gpclk1_gpio50: gpclk1-gpio50 { + pin-gpclk { + pins = "gpio50"; + function = "alt1"; + bias-disable; + }; + }; + gpclk2_gpio51: gpclk2-gpio51 { + pin-gpclk { + pins = "gpio51"; + function = "alt1"; + bias-disable; + }; + }; + + i2c0_gpio46: i2c0-gpio46 { + pin-sda { + function = "alt0"; + pins = "gpio46"; + bias-pull-up; + }; + pin-scl { + function = "alt0"; + pins = "gpio47"; + bias-disable; + }; + }; + i2c1_gpio46: i2c1-gpio46 { + pin-sda { + function = "alt1"; + pins = "gpio46"; + bias-pull-up; + }; + pin-scl { + function = "alt1"; + pins = "gpio47"; + bias-disable; + }; + }; + i2c3_gpio2: i2c3-gpio2 { + pin-sda { + function = "alt5"; + pins = "gpio2"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio3"; + bias-disable; + }; + }; + i2c3_gpio4: i2c3-gpio4 { + pin-sda { + function = "alt5"; + pins = "gpio4"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio5"; + bias-disable; + }; + }; + i2c4_gpio6: i2c4-gpio6 { + pin-sda { + function = "alt5"; + pins = "gpio6"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio7"; + bias-disable; + }; + }; + i2c4_gpio8: i2c4-gpio8 { + pin-sda { + function = "alt5"; + pins = "gpio8"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio9"; + bias-disable; + }; + }; + i2c5_gpio10: i2c5-gpio10 { + pin-sda { + function = "alt5"; + pins = "gpio10"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio11"; + bias-disable; + }; + }; + i2c5_gpio12: i2c5-gpio12 { + pin-sda { + function = "alt5"; + pins = "gpio12"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio13"; + bias-disable; + }; + }; + i2c6_gpio0: i2c6-gpio0 { + pin-sda { + function = "alt5"; + pins = "gpio0"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio1"; + bias-disable; + }; + }; + i2c6_gpio22: i2c6-gpio22 { + pin-sda { + function = "alt5"; + pins = "gpio22"; + bias-pull-up; + }; + pin-scl { + function = "alt5"; + pins = "gpio23"; + bias-disable; + }; + }; + i2c_slave_gpio8: i2c-slave-gpio8 { + pins-i2c-slave { + pins = "gpio8", + "gpio9", + "gpio10", + "gpio11"; + function = "alt3"; + }; + }; + + jtag_gpio48: jtag-gpio48 { + pins-jtag { + pins = "gpio48", + "gpio49", + "gpio50", + "gpio51", + "gpio52", + "gpio53"; + function = "alt4"; + }; + }; + + mii_gpio28: mii-gpio28 { + pins-mii { + pins = "gpio28", + "gpio29", + "gpio30", + "gpio31"; + function = "alt4"; + }; + }; + mii_gpio36: mii-gpio36 { + pins-mii { + pins = "gpio36", + "gpio37", + "gpio38", + "gpio39"; + function = "alt5"; + }; + }; + + pcm_gpio50: pcm-gpio50 { + pins-pcm { + pins = "gpio50", + "gpio51", + "gpio52", + "gpio53"; + function = "alt2"; + }; + }; + + pwm0_0_gpio12: pwm0-0-gpio12 { + pin-pwm { + pins = "gpio12"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_0_gpio18: pwm0-0-gpio18 { + pin-pwm { + pins = "gpio18"; + function = "alt5"; + bias-disable; + }; + }; + pwm1_0_gpio40: pwm1-0-gpio40 { + pin-pwm { + pins = "gpio40"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_1_gpio13: pwm0-1-gpio13 { + pin-pwm { + pins = "gpio13"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_1_gpio19: pwm0-1-gpio19 { + pin-pwm { + pins = "gpio19"; + function = "alt5"; + bias-disable; + }; + }; + pwm1_1_gpio41: pwm1-1-gpio41 { + pin-pwm { + pins = "gpio41"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_1_gpio45: pwm0-1-gpio45 { + pin-pwm { + pins = "gpio45"; + function = "alt0"; + bias-disable; + }; + }; + pwm0_0_gpio52: pwm0-0-gpio52 { + pin-pwm { + pins = "gpio52"; + function = "alt1"; + bias-disable; + }; + }; + pwm0_1_gpio53: pwm0-1-gpio53 { + pin-pwm { + pins = "gpio53"; + function = "alt1"; + bias-disable; + }; + }; + + rgmii_gpio35: rgmii-gpio35 { + pin-start-stop { + pins = "gpio35"; + function = "alt4"; + }; + pin-rx-ok { + pins = "gpio36"; + function = "alt4"; + }; + }; + rgmii_irq_gpio34: rgmii-irq-gpio34 { + pin-irq { + pins = "gpio34"; + function = "alt5"; + }; + }; + rgmii_irq_gpio39: rgmii-irq-gpio39 { + pin-irq { + pins = "gpio39"; + function = "alt4"; + }; + }; + rgmii_mdio_gpio28: rgmii-mdio-gpio28 { + pins-mdio { + pins = "gpio28", + "gpio29"; + function = "alt5"; + }; + }; + rgmii_mdio_gpio37: rgmii-mdio-gpio37 { + pins-mdio { + pins = "gpio37", + "gpio38"; + function = "alt4"; + }; + }; + + spi0_gpio46: spi0-gpio46 { + pins-spi { + pins = "gpio46", + "gpio47", + "gpio48", + "gpio49"; + function = "alt2"; + }; + }; + spi2_gpio46: spi2-gpio46 { + pins-spi { + pins = "gpio46", + "gpio47", + "gpio48", + "gpio49", + "gpio50"; + function = "alt5"; + }; + }; + spi3_gpio0: spi3-gpio0 { + pins-spi { + pins = "gpio0", + "gpio1", + "gpio2", + "gpio3"; + function = "alt3"; + }; + }; + spi4_gpio4: spi4-gpio4 { + pins-spi { + pins = "gpio4", + "gpio5", + "gpio6", + "gpio7"; + function = "alt3"; + }; + }; + spi5_gpio12: spi5-gpio12 { + pins-spi { + pins = "gpio12", + "gpio13", + "gpio14", + "gpio15"; + function = "alt3"; + }; + }; + spi6_gpio18: spi6-gpio18 { + pins-spi { + pins = "gpio18", + "gpio19", + "gpio20", + "gpio21"; + function = "alt3"; + }; + }; + + uart2_gpio0: uart2-gpio0 { + pin-tx { + pins = "gpio0"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio1"; + function = "alt4"; + bias-pull-up; + }; + }; + uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 { + pin-cts { + pins = "gpio2"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio3"; + function = "alt4"; + bias-disable; + }; + }; + uart3_gpio4: uart3-gpio4 { + pin-tx { + pins = "gpio4"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio5"; + function = "alt4"; + bias-pull-up; + }; + }; + uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 { + pin-cts { + pins = "gpio6"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio7"; + function = "alt4"; + bias-disable; + }; + }; + uart4_gpio8: uart4-gpio8 { + pin-tx { + pins = "gpio8"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio9"; + function = "alt4"; + bias-pull-up; + }; + }; + uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 { + pin-cts { + pins = "gpio10"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio11"; + function = "alt4"; + bias-disable; + }; + }; + uart5_gpio12: uart5-gpio12 { + pin-tx { + pins = "gpio12"; + function = "alt4"; + bias-disable; + }; + pin-rx { + pins = "gpio13"; + function = "alt4"; + bias-pull-up; + }; + }; + uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 { + pin-cts { + pins = "gpio14"; + function = "alt4"; + bias-pull-up; + }; + pin-rts { + pins = "gpio15"; + function = "alt4"; + bias-disable; + }; + }; +}; + +&rmem { + #address-cells = <2>; +}; + +&cma { + /* + * arm64 reserves the CMA by default somewhere in ZONE_DMA32, + * that's not good enough for the BCM2711 as some devices can + * only address the lower 1G of memory (ZONE_DMA). + */ + alloc-ranges = <0x0 0x00000000 0x40000000>; +}; + +&i2c0 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + interrupts = ; +}; + +&i2c1 { + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; + interrupts = ; +}; + +&mailbox { + interrupts = ; +}; + +&sdhci { + interrupts = ; +}; + +&sdhost { + interrupts = ; +}; + +&spi { + interrupts = ; +}; + +&spi1 { + interrupts = ; +}; + +&spi2 { + interrupts = ; +}; + +&system_timer { + interrupts = , + , + , + ; +}; + +&txp { + interrupts = ; +}; + +&uart0 { + interrupts = ; +}; + +&uart1 { + interrupts = ; +}; + +&usb { + interrupts = ; +}; + +&vec { + compatible = "brcm,bcm2711-vec"; + interrupts = ; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm28155-ap.dts b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts new file mode 100644 index 000000000000..0a8ad1d673d8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2013 Broadcom Corporation + +/dts-v1/; + +#include + +#include "bcm11351.dtsi" + +/ { + model = "BCM28155 AP board"; + compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + serial@3e000000 { + status = "okay"; + }; + + i2c@3e016000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@3e017000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@3e018000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@3500d000 { + clock-frequency = <100000>; + status = "okay"; + + pmu: pmu@8 { + reg = <0x08>; + }; + }; + + sdio2: mmc@3f190000 { + non-removable; + max-frequency = <48000000>; + vmmc-supply = <&camldo1_reg>; + vqmmc-supply = <&iosr1_reg>; + status = "okay"; + }; + + sdio4: mmc@3f1b0000 { + max-frequency = <48000000>; + cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <&sdldo_reg>; + vqmmc-supply = <&sdxldo_reg>; + status = "okay"; + }; + + pwm: pwm@3e01a000 { + status = "okay"; + }; + + usbotg: usb@3f120000 { + vusb_d-supply = <&usbldo_reg>; + vusb_a-supply = <&iosr1_reg>; + status = "okay"; + }; + + usbphy: usb-phy@3f130000 { + status = "okay"; + }; +}; + +#include "bcm59056.dtsi" + +&pmu { + compatible = "brcm,bcm59056"; + interrupts = ; + regulators { + camldo1_reg: camldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdldo_reg: sdldo { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + sdxldo_reg: sdxldo { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + usbldo_reg: usbldo { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + iosr1_reg: iosr1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi new file mode 100644 index 000000000000..bb7e8f7facaf --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations. + */ + +/ { + interrupt-parent = <&intc>; + + soc { + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16>, + <1 17>, + <1 18>, + <1 19>, + <1 20>, + <1 21>, + <1 22>, + <1 23>, + <1 24>, + <1 25>, + <1 26>, + /* dma channel 11-14 share one irq */ + <1 27>, + <1 27>, + <1 27>, + <1 27>, + /* unused shared irq for all channels */ + <1 28>; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5", + "dma6", + "dma7", + "dma8", + "dma9", + "dma10", + "dma11", + "dma12", + "dma13", + "dma14", + "dma-shared-all"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x7f35>; + }; + + intc: interrupt-controller@7e00b200 { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>; + reg-names = "pm", "asb"; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; + }; + + rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + interrupts = <2 29>; + }; + + pixelvalve@7e206000 { + compatible = "brcm,bcm2835-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = <2 13>; /* pwa0 */ + }; + + pixelvalve@7e207000 { + compatible = "brcm,bcm2835-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = <2 14>; /* pwa1 */ + }; + + thermal: thermal@7e212000 { + compatible = "brcm,bcm2835-thermal"; + reg = <0x7e212000 0x8>; + clocks = <&clocks BCM2835_CLOCK_TSENS>; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@7e805000 { + compatible = "brcm,bcm2835-i2c"; + reg = <0x7e805000 0x1000>; + interrupts = <2 21>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + vec: vec@7e806000 { + compatible = "brcm,bcm2835-vec"; + reg = <0x7e806000 0x1000>; + clocks = <&clocks BCM2835_CLOCK_VEC>; + interrupts = <2 27>; + status = "disabled"; + }; + + pixelvalve@7e807000 { + compatible = "brcm,bcm2835-pixelvalve2"; + reg = <0x7e807000 0x100>; + interrupts = <2 10>; /* pixelvalve */ + }; + + hdmi: hdmi@7e902000 { + compatible = "brcm,bcm2835-hdmi"; + reg = <0x7e902000 0x600>, + <0x7e808000 0x100>; + interrupts = <2 8>, <2 9>; + ddc = <&i2c2>; + clocks = <&clocks BCM2835_PLLH_PIX>, + <&clocks BCM2835_CLOCK_HSM>; + clock-names = "pixel", "hdmi"; + dmas = <&dma 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + v3d: v3d@7ec00000 { + compatible = "brcm,bcm2835-v3d"; + reg = <0x7ec00000 0x1000>; + interrupts = <1 10>; + }; + + vc4: gpu { + compatible = "brcm,bcm2835-vc4"; + }; + }; +}; + +&cpu_thermal { + thermal-sensors = <&thermal>; +}; + +&gpio { + i2c_slave_gpio18: i2c-slave-gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + + jtag_gpio4: jtag-gpio4 { + brcm,pins = <4 5 6 12 13>; + brcm,function = ; + }; + + pwm0_gpio12: pwm0-gpio12 { + brcm,pins = <12>; + brcm,function = ; + }; + pwm0_gpio18: pwm0-gpio18 { + brcm,pins = <18>; + brcm,function = ; + }; + pwm0_gpio40: pwm0-gpio40 { + brcm,pins = <40>; + brcm,function = ; + }; + pwm1_gpio13: pwm1-gpio13 { + brcm,pins = <13>; + brcm,function = ; + }; + pwm1_gpio19: pwm1-gpio19 { + brcm,pins = <19>; + brcm,function = ; + }; + pwm1_gpio41: pwm1-gpio41 { + brcm,pins = <41>; + brcm,function = ; + }; + pwm1_gpio45: pwm1-gpio45 { + brcm,pins = <45>; + brcm,function = ; + }; +}; + +&i2s { + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; +}; + +&sdhost { + dmas = <&dma 13>; + dma-names = "rx-tx"; +}; + +&spi { + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts new file mode 100644 index 000000000000..02ce817868ba --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model A+"; + + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; +}; + +&gpio { + /* + * This is based on the unreleased schematic for the Model A+. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", /* GPIO38 */ + "", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts new file mode 100644 index 000000000000..3fdf60eb11dc --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-a", "brcm,bcm2835"; + model = "Raspberry Pi Model A"; + + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_GPIO1", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "", /* GPIO12 */ + "", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "", /* GPIO19 */ + "", /* GPIO20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "", /* GPIO26 */ + "CAM_GPIO0", + /* Binary number representing build/revision */ + "CONFIG0", + "CONFIG1", + "CONFIG2", + "CONFIG3", + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "PWM0_OUT", + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; + + /* I2S interface */ + i2s_alt2: i2s_alt2 { + brcm,pins = <28 29 30 31>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts new file mode 100644 index 000000000000..9956fd06a4b6 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model B+"; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf + * RPI-BPLUS sheet 1 + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "LAN_RUN", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", /* GPIO38 */ + "", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "ETH_CLK", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts new file mode 100644 index 000000000000..4e1770afb145 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; + model = "Raspberry Pi Model B rev2"; + + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf + * RPI00022 sheet 02 + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_CLK", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "", /* GPIO12 */ + "", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "", /* GPIO19 */ + "", /* GPIO20 */ + "CAM_GPIO", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "PWM0_OUT", + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; + + /* I2S interface */ + i2s_alt2: i2s_alt2 { + brcm,pins = <28 29 30 31>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts new file mode 100644 index 000000000000..eec1d0892d33 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; + + memory@0 { + device_type = "memory"; + reg = <0 0x10000000>; + }; +}; + +&gpio { + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_GPIO1", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "", /* GPIO12 */ + "", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "", /* GPIO19 */ + "", /* GPIO20 */ + "CAM_GPIO0", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "PWM0_OUT", + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts new file mode 100644 index 000000000000..87958a96c3e0 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835-rpi-cm1.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + model = "Raspberry Pi Compute Module IO board rev1"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "HDMI_HPD_N", + /* Also used as ACT LED */ + "EMMC_EN_N", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi new file mode 100644 index 000000000000..750cd76948e3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + leds { + led-act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + + reg_3v3: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; +}; + +&sdhost { + non-removable; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi new file mode 100644 index 000000000000..4e7b4a592da7 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's + * firmware interface. + */ + +#include + +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; +}; + +&hdmi { + clocks = <&firmware_clocks 9>, + <&firmware_clocks 13>; + clock-names = "pixel", "hdmi"; +}; + +&v3d { + power-domains = <&power RPI_POWER_DOMAIN_V3D>; +}; + +&vec { + clocks = <&firmware_clocks 15>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts new file mode 100644 index 000000000000..dbf825985ec0 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Stefan Wahren + */ + +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; + model = "Raspberry Pi Zero W"; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; +}; + +&bt { + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "CAM_GPIO1", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "CAM_GPIO0", /* GPIO44 */ + "BT_ON", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; +}; + +&sdhci { + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&wifi_pwrseq { + reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts new file mode 100644 index 000000000000..f80e65a825fd --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Stefan Wahren + */ + +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" + +/ { + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + model = "Raspberry Pi Zero"; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi new file mode 100644 index 000000000000..ee9ee9d1fe65 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi @@ -0,0 +1,71 @@ +#include + +/ { + soc { + firmware: firmware { + compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + mboxes = <&mailbox>; + dma-ranges; + }; + + power: power { + compatible = "raspberrypi,bcm2835-power"; + firmware = <&firmware>; + #power-domain-cells = <1>; + }; + + vchiq: mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0x3c>; + interrupts = <0 2>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + + gpioout: gpioout { + brcm,pins = <6>; + brcm,function = ; + }; + + alt0: alt0 { + brcm,pins = <4 5 7 8 9 10 11>; + brcm,function = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_gpio0>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_gpio2>; + status = "okay"; + clock-frequency = <100000>; +}; + +&usb { + power-domains = <&power RPI_POWER_DOMAIN_USB>; +}; + +&vec { + power-domains = <&power RPI_POWER_DOMAIN_VEC>; + status = "okay"; +}; + +&dsi0 { + power-domains = <&power RPI_POWER_DOMAIN_DSI0>; +}; + +&dsi1 { + power-domains = <&power RPI_POWER_DOMAIN_DSI1>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2835.dtsi b/arch/arm/boot/dts/broadcom/bcm2835.dtsi new file mode 100644 index 000000000000..15cb331febbb --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2835.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm283x.dtsi" +#include "bcm2835-common.dtsi" + +/ { + compatible = "brcm,bcm2835"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + reg = <0x0>; + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0301 + * /h/level-one-memory-system/cache-organization?lang=en + * + * Source for d/i-cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + * + * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU + * It can be shared with the CPU through fw settings, + * but this is not recommended. + */ + d-cache-size = <0x4000>; + d-cache-line-size = <16>; + d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set + i-cache-size = <0x4000>; + i-cache-line-size = <16>; + i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set + }; + }; + + soc { + ranges = <0x7e000000 0x20000000 0x02000000>; + dma-ranges = <0x40000000 0x00000000 0x20000000>; + }; + + arm-pmu { + compatible = "arm,arm1176-pmu"; + }; +}; + +&cpu_thermal { + coefficients = <(-538) 407000>; +}; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2835-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts new file mode 100644 index 000000000000..6068ec390081 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2836.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; + model = "Raspberry Pi 2 Model B"; + + memory@0 { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", + "", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETH_CLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi new file mode 100644 index 000000000000..48b03b55ff56 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" + +&vchiq { + compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2836.dtsi b/arch/arm/boot/dts/broadcom/bcm2836.dtsi new file mode 100644 index 000000000000..783fe624ba68 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2836.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm283x.dtsi" +#include "bcm2835-common.dtsi" + +/ { + compatible = "brcm,bcm2836"; + + soc { + ranges = <0x7e000000 0x3f000000 0x1000000>, + <0x40000000 0x40000000 0x00001000>; + dma-ranges = <0xc0000000 0x00000000 0x3f000000>; + + local_intc: interrupt-controller@40000000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x40000000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&local_intc>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&local_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI + <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI + <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI + <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI + always-on; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm2836-smp"; + + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System + * /About-the-L1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + */ + + v7_cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; + }; + + v7_cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; + }; + + v7_cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; + }; + + v7_cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; + }; + + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System + * /About-the-L2-Memory-system?lang=en + * Source for cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + */ + l2: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + }; + }; +}; + +/* Make the BCM2835-style global interrupt controller be a child of the + * CPU-local interrupt controller. + */ +&intc { + compatible = "brcm,bcm2836-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-parent = <&local_intc>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&cpu_thermal { + coefficients = <(-538) 407000>; +}; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2836-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 000000000000..3548306dfbcb --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model A+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", + "BT_WL_ON", + "STATUS_LED_R", + "", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * This is mostly based on the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "", /* GPIO42 */ + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module + * + * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven + * by a single GPIO. We can't give GPIO control to one of the drivers, + * otherwise the other part would get unexpectedly disturbed. + */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts new file mode 100644 index 000000000000..2f1800cbc522 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-lan7515.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; + +&bt { + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_R", + "LAN_RUN", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETH_CLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts new file mode 100644 index 000000000000..61270340075c --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; + +&bt { + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "STATUS_LED", + "LAN_RUN", + "HDMI_HPD_N", + "CAM_GPIO0", + "CAM_GPIO1", + "PWR_LOW_N"; + status = "okay"; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_3b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "", /* GPIO 28 */ + "LAN_RUN_BOOT", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETH_CLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +&wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts new file mode 100644 index 000000000000..cf84e69fced8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837-rpi-cm3.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; + model = "Raspberry Pi Compute Module 3 IO board V3.0"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "SMPS_SCL", + "SMPS_SDA", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi new file mode 100644 index 000000000000..1e4e4946b6b6 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + reg_3v3: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_HPD_N", + "EMMC_EN_N", + "", + "", + "", + "", + "", + ""; + status = "okay"; + }; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts new file mode 100644 index 000000000000..b9cc4594398b --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Stefan Wahren + */ + +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; + model = "Raspberry Pi Zero 2 W"; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; +}; + +&bt { + shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_N", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "CAM_GPIO0", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "BT_ON", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "SDA0", /* GPIO44 */ + "SCL0", /* GPIO45 */ + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; +}; + +&sdhci { + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&wifi_pwrseq { + reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837.dtsi b/arch/arm/boot/dts/broadcom/bcm2837.dtsi new file mode 100644 index 000000000000..84c08b46519d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837.dtsi @@ -0,0 +1,144 @@ +#include "bcm283x.dtsi" +#include "bcm2835-common.dtsi" + +/ { + compatible = "brcm,bcm2837"; + + soc { + ranges = <0x7e000000 0x3f000000 0x1000000>, + <0x40000000 0x40000000 0x00001000>; + dma-ranges = <0xc0000000 0x00000000 0x3f000000>; + + local_intc: local_intc@40000000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x40000000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&local_intc>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&local_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI + <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI + <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI + <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI + always-on; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system + * /about-the-l1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks + */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0500 + * /e/level-2-memory-system/about-the-l2-memory-system?lang=en + * Source for cache-size + * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf + */ + l2: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set + cache-level = <2>; + }; + }; +}; + +/* Make the BCM2835-style global interrupt controller be a child of the + * CPU-local interrupt controller. + */ +&intc { + compatible = "brcm,bcm2836-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-parent = <&local_intc>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&cpu_thermal { + coefficients = <(-538) 412000>; +}; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2837-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi new file mode 100644 index 000000000000..70bece63f9a7 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/ { + aliases { + ethernet0 = ðernet; + }; +}; + +&usb { + usb-port@1 { + compatible = "usb424,2514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usb-port@1 { + compatible = "usb424,2514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,7800"; + reg = <1>; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + eth_phy: ethernet-phy@1 { + reg = <1>; + microchip,led-modes = < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + >; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi new file mode 100644 index 000000000000..f83e56de1a72 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* + * This file provides the now deprecated ACT LED to the + * Raspberry Pi boards. Please don't include this file + * for new boards! + */ + leds: leds { + compatible = "gpio-leds"; + + led_act: led-act { + label = "ACT"; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi new file mode 100644 index 000000000000..882b13807075 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + aliases { + ethernet0 = ðernet; + }; +}; + +&usb { + usb1@1 { + compatible = "usb424,9512"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi new file mode 100644 index 000000000000..4273b90b53cc --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi @@ -0,0 +1,19 @@ +/ { + aliases { + ethernet0 = ðernet; + }; +}; + +&usb { + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi new file mode 100644 index 000000000000..73f4ece8dcd0 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi @@ -0,0 +1,3 @@ +&usb { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi new file mode 100644 index 000000000000..e2fd9610e125 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +&usb { + dr_mode = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + /* + * According to dwc2 the sum of all device EP + * fifo sizes shouldn't exceed 3776 bytes. + */ + g-tx-fifo-size = <256 256 512 512 512 768 768>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi new file mode 100644 index 000000000000..0ff0e9e25327 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +&usb { + dr_mode = "peripheral"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 256 512 512 512 768 768>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi new file mode 100644 index 000000000000..0b64cc19941f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + }; +}; + +/* SDHCI is used to control the SDIO for wireless */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + status = "okay"; + + bt: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi new file mode 100644 index 000000000000..c9c52a19ef3b --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm283x.dtsi @@ -0,0 +1,501 @@ +#include +#include +#include +#include +#include +#include + +/* firmware-provided startup stubs live here, where the secondary CPUs are + * spinning. + */ +/memreserve/ 0x00000000 0x00001000; + +/* This include file covers the common peripherals and configuration between + * bcm2835 and bcm2836 implementations, leaving the CPU configuration to + * bcm2835.dtsi and bcm2836.dtsi. + */ + +/ { + compatible = "brcm,bcm2835"; + model = "BCM2835"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + rmem: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + + trips { + cpu-crit { + temperature = <90000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + system_timer: timer@7e003000 { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7e003000 0x1000>; + interrupts = <1 0>, <1 1>, <1 2>, <1 3>; + /* This could be a reference to BCM2835_CLOCK_TIMER, + * but we don't have the driver using the common clock + * support yet. + */ + clock-frequency = <1000000>; + }; + + txp: txp@7e004000 { + compatible = "brcm,bcm2835-txp"; + reg = <0x7e004000 0x20>; + interrupts = <1 11>; + }; + + clocks: cprman@7e101000 { + compatible = "brcm,bcm2835-cprman"; + #clock-cells = <1>; + reg = <0x7e101000 0x2000>; + + /* CPRMAN derives almost everything from the + * platform's oscillator. However, the DSI + * pixel clocks come from the DSI analog PHY. + */ + clocks = <&clk_osc>, + <&dsi0 0>, <&dsi0 1>, <&dsi0 2>, + <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; + }; + + mailbox: mailbox@7e00b880 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; + #mbox-cells = <0>; + }; + + gpio: gpio@7e200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x7e200000 0xb4>; + /* + * The GPIO IP block is designed for 3 banks of GPIOs. + * Each bank has a GPIO interrupt for itself. + * There is an overall "any bank" interrupt. + * In order, these are GIC interrupts 17, 18, 19, 20. + * Since the BCM2835 only has 2 banks, the 2nd bank + * interrupt output appears to be mirrored onto the + * 3rd bank's interrupt signal. + * So, a bank0 interrupt shows up on 17, 20, and + * a bank1 interrupt shows up on 18, 19, 20! + */ + interrupts = <2 17>, <2 18>, <2 19>, <2 20>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&gpio 0 0 54>; + + /* Defines common pin muxing groups + * + * While each pin can have its mux selected + * for various functions individually, some + * groups only make sense to switch to a + * particular function together. + */ + dpi_gpio0: dpi-gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27>; + brcm,function = ; + }; + emmc_gpio22: emmc-gpio22 { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = ; + }; + emmc_gpio34: emmc-gpio34 { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = ; + brcm,pull = ; + }; + emmc_gpio48: emmc-gpio48 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = ; + }; + + gpclk0_gpio4: gpclk0-gpio4 { + brcm,pins = <4>; + brcm,function = ; + }; + gpclk1_gpio5: gpclk1-gpio5 { + brcm,pins = <5>; + brcm,function = ; + }; + gpclk1_gpio42: gpclk1-gpio42 { + brcm,pins = <42>; + brcm,function = ; + }; + gpclk1_gpio44: gpclk1-gpio44 { + brcm,pins = <44>; + brcm,function = ; + }; + gpclk2_gpio6: gpclk2-gpio6 { + brcm,pins = <6>; + brcm,function = ; + }; + gpclk2_gpio43: gpclk2-gpio43 { + brcm,pins = <43>; + brcm,function = ; + brcm,pull = ; + }; + + i2c0_gpio0: i2c0-gpio0 { + brcm,pins = <0 1>; + brcm,function = ; + }; + i2c0_gpio28: i2c0-gpio28 { + brcm,pins = <28 29>; + brcm,function = ; + }; + i2c0_gpio44: i2c0-gpio44 { + brcm,pins = <44 45>; + brcm,function = ; + }; + i2c1_gpio2: i2c1-gpio2 { + brcm,pins = <2 3>; + brcm,function = ; + }; + i2c1_gpio44: i2c1-gpio44 { + brcm,pins = <44 45>; + brcm,function = ; + }; + + jtag_gpio22: jtag-gpio22 { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = ; + }; + + pcm_gpio18: pcm-gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + pcm_gpio28: pcm-gpio28 { + brcm,pins = <28 29 30 31>; + brcm,function = ; + }; + + sdhost_gpio48: sdhost-gpio48 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = ; + }; + + spi0_gpio7: spi0-gpio7 { + brcm,pins = <7 8 9 10 11>; + brcm,function = ; + }; + spi0_gpio35: spi0-gpio35 { + brcm,pins = <35 36 37 38 39>; + brcm,function = ; + }; + spi1_gpio16: spi1-gpio16 { + brcm,pins = <16 17 18 19 20 21>; + brcm,function = ; + }; + spi2_gpio40: spi2-gpio40 { + brcm,pins = <40 41 42 43 44 45>; + brcm,function = ; + }; + + uart0_gpio14: uart0-gpio14 { + brcm,pins = <14 15>; + brcm,function = ; + }; + /* Separate from the uart0_gpio14 group + * because it conflicts with spi1_gpio16, and + * people often run uart0 on the two pins + * without flow control. + */ + uart0_ctsrts_gpio16: uart0-ctsrts-gpio16 { + brcm,pins = <16 17>; + brcm,function = ; + }; + uart0_ctsrts_gpio30: uart0-ctsrts-gpio30 { + brcm,pins = <30 31>; + brcm,function = ; + brcm,pull = ; + }; + uart0_gpio32: uart0-gpio32 { + brcm,pins = <32 33>; + brcm,function = ; + brcm,pull = ; + }; + uart0_gpio36: uart0-gpio36 { + brcm,pins = <36 37>; + brcm,function = ; + }; + uart0_ctsrts_gpio38: uart0-ctsrts-gpio38 { + brcm,pins = <38 39>; + brcm,function = ; + }; + + uart1_gpio14: uart1-gpio14 { + brcm,pins = <14 15>; + brcm,function = ; + }; + uart1_ctsrts_gpio16: uart1-ctsrts-gpio16 { + brcm,pins = <16 17>; + brcm,function = ; + }; + uart1_gpio32: uart1-gpio32 { + brcm,pins = <32 33>; + brcm,function = ; + }; + uart1_ctsrts_gpio30: uart1-ctsrts-gpio30 { + brcm,pins = <30 31>; + brcm,function = ; + }; + uart1_gpio40: uart1-gpio40 { + brcm,pins = <40 41>; + brcm,function = ; + }; + uart1_ctsrts_gpio42: uart1-ctsrts-gpio42 { + brcm,pins = <42 43>; + brcm,function = ; + }; + }; + + uart0: serial@7e201000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x200>; + interrupts = <2 25>; + clocks = <&clocks BCM2835_CLOCK_UART>, + <&clocks BCM2835_CLOCK_VPU>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + }; + + sdhost: mmc@7e202000 { + compatible = "brcm,bcm2835-sdhost"; + reg = <0x7e202000 0x100>; + interrupts = <2 24>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + status = "disabled"; + }; + + i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; + status = "disabled"; + }; + + spi: spi@7e204000 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204000 0x200>; + interrupts = <2 22>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@7e205000 { + compatible = "brcm,bcm2835-i2c"; + reg = <0x7e205000 0x200>; + interrupts = <2 21>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dpi: dpi@7e208000 { + compatible = "brcm,bcm2835-dpi"; + reg = <0x7e208000 0x8c>; + clocks = <&clocks BCM2835_CLOCK_VPU>, + <&clocks BCM2835_CLOCK_DPI>; + clock-names = "core", "pixel"; + status = "disabled"; + }; + + dsi0: dsi@7e209000 { + compatible = "brcm,bcm2835-dsi0"; + reg = <0x7e209000 0x78>; + interrupts = <2 4>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + clocks = <&clocks BCM2835_PLLA_DSI0>, + <&clocks BCM2835_CLOCK_DSI0E>, + <&clocks BCM2835_CLOCK_DSI0P>; + clock-names = "phy", "escape", "pixel"; + + clock-output-names = "dsi0_byte", + "dsi0_ddr2", + "dsi0_ddr"; + + status = "disabled"; + }; + + aux: aux@7e215000 { + compatible = "brcm,bcm2835-aux"; + #clock-cells = <1>; + reg = <0x7e215000 0x8>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + }; + + uart1: serial@7e215040 { + compatible = "brcm,bcm2835-aux-uart"; + reg = <0x7e215040 0x40>; + interrupts = <1 29>; + clocks = <&aux BCM2835_AUX_CLOCK_UART>; + status = "disabled"; + }; + + spi1: spi@7e215080 { + compatible = "brcm,bcm2835-aux-spi"; + reg = <0x7e215080 0x40>; + interrupts = <1 29>; + clocks = <&aux BCM2835_AUX_CLOCK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@7e2150c0 { + compatible = "brcm,bcm2835-aux-spi"; + reg = <0x7e2150c0 0x40>; + interrupts = <1 29>; + clocks = <&aux BCM2835_AUX_CLOCK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@7e20c000 { + compatible = "brcm,bcm2835-pwm"; + reg = <0x7e20c000 0x28>; + clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clock-rates = <10000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + sdhci: mmc@7e300000 { + compatible = "brcm,bcm2835-sdhci"; + reg = <0x7e300000 0x100>; + interrupts = <2 30>; + clocks = <&clocks BCM2835_CLOCK_EMMC>; + status = "disabled"; + }; + + hvs@7e400000 { + compatible = "brcm,bcm2835-hvs"; + reg = <0x7e400000 0x6000>; + interrupts = <2 1>; + }; + + dsi1: dsi@7e700000 { + compatible = "brcm,bcm2835-dsi1"; + reg = <0x7e700000 0x8c>; + interrupts = <2 12>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + clocks = <&clocks BCM2835_PLLD_DSI1>, + <&clocks BCM2835_CLOCK_DSI1E>, + <&clocks BCM2835_CLOCK_DSI1P>; + clock-names = "phy", "escape", "pixel"; + + clock-output-names = "dsi1_byte", + "dsi1_ddr2", + "dsi1_ddr"; + + status = "disabled"; + }; + + i2c1: i2c@7e804000 { + compatible = "brcm,bcm2835-i2c"; + reg = <0x7e804000 0x1000>; + interrupts = <2 21>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@7e980000 { + compatible = "brcm,bcm2835-usb"; + reg = <0x7e980000 0x10000>; + interrupts = <1 9>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_usb>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + }; + }; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <19200000>; + }; + + clk_usb: clk-usb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "otg"; + clock-frequency = <480000000>; + }; + }; + + usbphy: phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts new file mode 100644 index 000000000000..c80ac16ad949 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-AC56U + * + * Copyright (C) 2015 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-ac56u", "brcm,bcm4708"; + model = "Asus RT-AC56U (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + led-wan { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + led-lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-all { + label = "bcm53xx:blue:all"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts new file mode 100644 index 000000000000..3fe17bd7b86d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-AC68U + * + * Copyright (C) 2015 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-ac68u", "brcm,bcm4708"; + model = "Asus RT-AC68U (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-brightness { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi new file mode 100644 index 000000000000..42bcbf10957c --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2 + * + * Copyright (C) 2014 Rafał Miłecki + * Copyright (C) 2022 SHIMAMOTO Takayoshi + */ + + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + led-usb { + /* label = "bcm53xx:blue:usb"; */ + function = LED_FUNCTION_USB; + color = ; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>, <&ohci_port2>, + <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-power0 { + /* label = "bcm53xx:red:power"; */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + + led-power1 { + /* label = "bcm53xx:white:power"; */ + function = LED_FUNCTION_POWER; + color = ; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router0 { + /* label = "bcm53xx:blue:router"; */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router1 { + /* label = "bcm53xx:amber:router"; */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + /* label = "bcm53xx:blue:wan"; */ + function = LED_FUNCTION_WAN; + color = ; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wireless0 { + /* label = "bcm53xx:blue:wireless"; */ + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + led-wireless1 { + /* label = "bcm53xx:amber:wireless"; */ + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-aoss { + label = "AOSS"; + linux,code = ; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + button-mode { + label = "Mode"; + linux,code = ; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + button-sw-ap { + label = "AP"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + button-eject { + label = "USB eject"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan1"; + }; + + port@1 { + label = "lan2"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan4"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts new file mode 100644 index 000000000000..8e506269fa1a --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts new file mode 100644 index 000000000000..596129027074 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP2 + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP2"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts new file mode 100644 index 000000000000..95ef6ca7210b --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-1750DHP + * + * Copyright (C) 2014 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; + model = "Buffalo WZR-1750DHP (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>, <&ohci_port2>, + <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-power0 { + label = "bcm53xx:red:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + + led-power1 { + label = "bcm53xx:white:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router0 { + label = "bcm53xx:blue:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + label = "bcm53xx:blue:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wireless0 { + label = "bcm53xx:blue:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + led-wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-aoss { + label = "AOSS"; + linux,code = ; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + button-mode { + label = "Mode"; + linux,code = ; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + button-sw-ap { + label = "AP"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + button-eject { + label = "USB eject"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts new file mode 100644 index 000000000000..0ed25bf71f0d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "linksys,ea6300-v1", "brcm,bcm4708"; + model = "Linksys EA6300 V1"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x180000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts new file mode 100644 index 000000000000..f1412ba83def --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Rafał Miłecki + * Copyright (C) 2018 Rene Kjellerup + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "linksys,ea6500-v2", "brcm,bcm4708"; + model = "Linksys EA6500 V2"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts new file mode 100644 index 000000000000..e04d2e5ea51a --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "luxul,xap-1510-v1", "brcm,bcm4708"; + model = "Luxul XAP-1510 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "poe"; + }; + + port@4 { + label = "lan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts new file mode 100644 index 000000000000..a399800139d9 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Luxul XWC-1000 + * + * Copyright 2014 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,xwc-1000", "brcm,bcm4708"; + model = "Luxul XWC-1000 (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + + nand_controller: nand-controller@18028000 { + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ubi"; + reg = <0x00000000 0x08000000>; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@4 { + label = "lan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts new file mode 100644 index 000000000000..fad3473810a2 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts @@ -0,0 +1,126 @@ +/* + * Broadcom BCM470X / BCM5301X arm platform code. + * DTS for Netgear R6250 V1 + * + * Copyright 2013 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r6250-v1", "brcm,bcm4708"; + model = "Netgear R6250 V1 (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-power0 { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-wireless { + label = "bcm53xx:blue:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts new file mode 100644 index 000000000000..77396730bdd3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Netgear R6300 V2 + * + * Copyright (C) 2014 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r6300-v2", "brcm,bcm4708"; + model = "Netgear R6300 V2 (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-power0 { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + led-power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + }; + + led-wireless { + label = "bcm53xx:blue:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts new file mode 100644 index 000000000000..5b2b7b8b3b12 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X arm platform code. + * DTS for SmartRG SR400ac + * + * Copyright (C) 2015 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "smartrg,sr400ac", "brcm,bcm4708"; + model = "SmartRG SR400ac"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + }; + + led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + trigger-sources = <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-usb3-green { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + }; + + led-status-red { + label = "bcm53xx:red:status"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + + led-status-green { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + + led-status-blue { + label = "bcm53xx:blue:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + + led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + + led-wan-red { + label = "bcm53xx:red:wan"; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4708.dtsi b/arch/arm/boot/dts/broadcom/bcm4708.dtsi new file mode 100644 index 000000000000..1a19e97a987d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708.dtsi @@ -0,0 +1,48 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for BCM4708 SoC. + * + * Copyright 2013-2014 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include "bcm5301x.dtsi" + +/ { + compatible = "brcm,bcm4708"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm-nsp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + secondary-boot-reg = <0xffff0400>; + reg = <0x1>; + }; + }; + +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts new file mode 100644 index 000000000000..3854db0118a9 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-N18U + * + * Copyright (C) 2014 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; + model = "Asus RT-N18U (BCM47081)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-wan { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts new file mode 100644 index 000000000000..d0a26b643b82 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-600DHP2 + * + * Copyright (C) 2014 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; + model = "Buffalo WZR-600DHP2 (BCM47081)"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power0 { + label = "bcm53xx:green:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-power1 { + label = "bcm53xx:red:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + }; + + led-router0 { + label = "bcm53xx:green:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + label = "bcm53xx:green:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wireless0 { + label = "bcm53xx:green:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + led-wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-aoss { + label = "AOSS"; + linux,code = ; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + /* Switch device mode? */ + button-mode { + label = "Mode"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + button-eject { + label = "USB eject"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan1"; + }; + + port@1 { + label = "lan2"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan4"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts new file mode 100644 index 000000000000..7655e4ff2d1c --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-900DHP + * + * Copyright (C) 2015 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; + model = "Buffalo WZR-900DHP (BCM47081)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + led-usb { + label = "bcm53xx:green:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + }; + + led-power0 { + label = "bcm53xx:green:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-power1 { + label = "bcm53xx:red:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + }; + + led-router0 { + label = "bcm53xx:green:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + label = "bcm53xx:green:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wireless0 { + label = "bcm53xx:green:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + led-wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts new file mode 100644 index 000000000000..9f21d6d6d35b --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm47081.dtsi" + +/ { + compatible = "luxul,xap-1410-v1", "brcm,bcm47081", "brcm,bcm4708"; + model = "Luxul XAP-1410 V1"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@4 { + label = "poe"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts new file mode 100644 index 000000000000..256107291702 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708"; + model = "Luxul XWR-1200 V1"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-lan3 { + label = "bcm53xx:green:lan3"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-lan4 { + label = "bcm53xx:green:lan4"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-wan { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-lan2 { + label = "bcm53xx:green:lan2"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-usb { + label = "bcm53xx:green:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + led-lan1 { + label = "bcm53xx:green:lan1"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts new file mode 100644 index 000000000000..b6a5886698b2 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47081.dtsi" + +/ { + compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708"; + model = "TP-LINK Archer C5 V2"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; + }; + + led-lan { + label = "bcm53xx:green:lan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + }; + + led-usb2-port1 { + label = "bcm53xx:green:usb2-port1"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wan-green { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-wps { + label = "bcm53xx:green:wps"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + + led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + + led-usb2-port2 { + label = "bcm53xx:green:usb2-port2"; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi_nor { + status = "okay"; + + partitions { + compatible = "tplink,safeloader-partitions"; + partitions-table-offset = <0xe50000>; + + partition-os-image { + compatible = "brcm,trx"; + }; + + partition-file-system { + linux,rootfs; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47081.dtsi b/arch/arm/boot/dts/broadcom/bcm47081.dtsi new file mode 100644 index 000000000000..ed13af028528 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47081.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for BCM47081 SoC. + * + * Copyright © 2014 Rafał Miłecki + */ + +#include "bcm5301x.dtsi" + +/ { + compatible = "brcm,bcm47081"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts new file mode 100644 index 000000000000..4f44cb4df704 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-AC87U + * + * Copyright (C) 2015 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; + model = "Asus RT-AC87U"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan { + label = "bcm53xx:red:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + nvram@80000 { + label = "nvram"; + reg = <0x00080000 0x00180000>; + }; + + firmware@200000 { + label = "firmware"; + reg = <0x00200000 0x07cc0000>; + compatible = "brcm,trx"; + }; + + asus@7ec0000 { + label = "asus"; + reg = <0x07ec0000 0x00140000>; + read-only; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts new file mode 100644 index 000000000000..b7cd2faa30ce --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WXR-1900DHP + * + * Copyright (C) 2015 Felix Fietkau + */ + +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; + model = "Buffalo WXR-1900DHP"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-usb { + label = "bcm53xx:green:usb"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-router-amber { + label = "bcm53xx:amber:router"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + }; + + led-router-white { + label = "bcm53xx:white:router"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + + led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + + led-wireless-amber { + label = "bcm53xx:amber:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + + led-wireless-white { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-power { + label = "Power"; + linux,code = ; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + + button-aoss { + label = "AOSS"; + linux,code = ; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + button-mode { + label = "Mode"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + button-sw-ap { + label = "AP"; + linux,code = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + + button-eject { + label = "USB eject"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts new file mode 100644 index 000000000000..99253fd7adb3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "linksys,ea9200", "brcm,bcm4709", "brcm,bcm4708"; + model = "Linksys EA9200"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x180000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts new file mode 100644 index 000000000000..24ba8f8f9bf3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Netgear R7000 + * + * Copyright (C) 2015 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; + model = "Netgear R7000"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + + led-wireless { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + + led-usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts new file mode 100644 index 000000000000..707c561703ed --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts @@ -0,0 +1,234 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Netgear R8000 + * + * Copyright (C) 2015 Rafał Miłecki + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE + * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; + model = "Netgear R8000 (BCM4709)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + }; + + led-5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-wireless { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + + led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + + led-5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + + led-usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + + button-brightness { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5735000 5835000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; +}; + +&pcie1 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@1,0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + bridge@1,1,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + bridge@1,0 { + reg = <0x800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; + + bridge@1,2,2 { + reg = <0x1000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@1,4,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5170000 5730000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan1"; + }; + + port@1 { + label = "lan2"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan4"; + }; + + port@4 { + label = "wan"; + }; + + port@8 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts new file mode 100644 index 000000000000..5a8b2b1567e6 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2016 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm4709.dtsi" + +/ { + compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708"; + model = "TP-LINK Archer C9 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + }; + + led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + }; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + }; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-wan-blue { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + + led-power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; + + partitions { + compatible = "tplink,safeloader-partitions"; + partitions-table-offset = <0xe50000>; + + partition-os-image { + compatible = "brcm,trx"; + }; + + partition-file-system { + linux,rootfs; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709.dtsi b/arch/arm/boot/dts/broadcom/bcm4709.dtsi new file mode 100644 index 000000000000..cba3d910bed8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2016 Rafał Miłecki + */ + +#include "bcm4708.dtsi" + +&uart0 { + clock-frequency = <125000000>; + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts new file mode 100644 index 000000000000..4d5747aa5dc8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2021-2022 Arınç ÜNAL + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708"; + model = "Asus RT-AC88U"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x00180000>; + + et1macaddr: et1macaddr { + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "white:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-red { + label = "red:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-lan { + label = "white:lan"; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "white:usb2"; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-usb3 { + label = "white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port1>, <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-wps { + label = "white:wps"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-wifi { + label = "Wi-Fi"; + linux,code = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + + button-led { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + }; + + sw0_p5: port@5 { + /delete-property/ethernet; + + label = "extsw"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + port@7 { + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + label = "cpu"; + }; + }; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x00080000 0x00180000>; + }; + + partition@200000 { + label = "firmware"; + reg = <0x00200000 0x07e00000>; + compatible = "brcm,trx"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts new file mode 100644 index 000000000000..51ce510b3e3a --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for D-Link DIR-885L + * + * Copyright (C) 2016 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch1.dtsi" + +/ { + compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708"; + model = "D-Link DIR-885L"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + nand_controller: nand-controller@18028000 { + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + /* Switch: router / extender */ + button-extender { + label = "Extender"; + linux,code = ; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + }; + + port@8 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts new file mode 100644 index 000000000000..60744f82c2b7 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device tree for D-Link DIR-890L + * D-Link calls this board "WRGAC36" + * this router has the same looks and form factor as D-Link DIR-885L. + * + * Some differences from DIR-885L include a separate USB2 port, separate LEDs + * for USB2 and USB3, a separate VCC supply for the USB2 slot and no + * router/extender switch is mounted (there is an empty mount point on the + * PCB) so this device is a pure router. Also the LAN ports are in the right + * order. + * + * Based on the device tree for DIR-885L + * Copyright (C) 2016 Rafał Miłecki + * Copyright (C) 2022 Linus Walleij + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch1.dtsi" + +/ { + compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708"; + model = "D-Link DIR-890L"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + /* + * LED information is derived from the boot log which + * conveniently lists all the LEDs. + */ + compatible = "gpio-leds"; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-usb2-white { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + /* Called "factory reset" in the vendor dmesg */ + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; + + /* + * The flash memory is memory mapped at 0x1e000000-0x1fffffff + * 64KB blocks; total size 2MB, same that can be + * found attached to the spi_nor SPI controller. + */ + nvram@1e1f0000 { + compatible = "brcm,nvram"; + reg = <0x1e1f0000 0x00010000>; + + et0macaddr: et0macaddr { + }; + }; +}; + +&gmac2 { + /* + * The NVRAM curiously does not contain a MAC address + * for et2 so since that is the only ethernet interface + * actually in use on the platform, we use this et0 MAC + * address for et2. + */ + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&nandcs { + /* Spansion S34ML01G2, 128MB with 128KB erase blocks */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * This is called "nflash" in the vendor kernel with + * "upgrade" and "rootfs" (probably using OpenWrt + * splitpart). We call it "firmware" like standard tools + * assume. The CFE loader contains incorrect information + * about TRX partitions, ignore this, there are no TRX + * partitions: this device uses SEAMA. + */ + firmware@0 { + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&usb2 { + vcc-gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan1"; + }; + + port@1 { + label = "lan2"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan4"; + }; + + port@4 { + label = "wan"; + }; + + port@8 { + label = "cpu"; + phy-mode = "rgmii"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts new file mode 100644 index 000000000000..8036c04d81cb --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "linksys,panamera", "brcm,bcm47094", "brcm,bcm4708"; + model = "Linksys EA9500"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x100000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "bcm53xx:green:usb2"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-power { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wifi-disabled { + label = "bcm53xx:amber:wifi-disabled"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + led-wifi-enabled { + label = "bcm53xx:white:wifi-enabled"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar1 { + label = "bcm53xx:white:bluebar1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar2 { + label = "bcm53xx:white:bluebar2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar3 { + label = "bcm53xx:white:bluebar3"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + + led-bluebar4 { + label = "bcm53xx:white:bluebar4"; + gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar5 { + label = "bcm53xx:white:bluebar5"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar6 { + label = "bcm53xx:white:bluebar6"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar7 { + label = "bcm53xx:white:bluebar7"; + gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; + }; + + led-bluebar8 { + label = "bcm53xx:white:bluebar8"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + }; + + mdio-mux@18003000 { + + /* BIT(9) = 1 => external mdio */ + mdio@200 { + reg = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "brcm,bcm53125"; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + reset-names = "robo_reset"; + reg = <0>; + dsa,member = <1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_mdio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan5"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan6"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + sw1_p8: port@8 { + reg = <8>; + ethernet = <&sw0_p0>; + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + sw0_p0: port@0 { + label = "extsw"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + label = "lan7"; + }; + + port@2 { + label = "lan4"; + }; + + port@3 { + label = "lan8"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + label = "cpu"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@7 { + label = "cpu"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + label = "cpu"; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "linksys,ns-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x080000 0x0100000>; + }; + + partition@180000{ + label = "devinfo"; + reg = <0x0180000 0x080000>; + }; + + partition@200000 { + reg = <0x0200000 0x01d00000>; + compatible = "linksys,ns-firmware", "brcm,trx"; + }; + + partition@1f00000 { + reg = <0x01f00000 0x01d00000>; + compatible = "linksys,ns-firmware", "brcm,trx"; + }; + + partition@5200000 { + label = "system"; + reg = <0x05200000 0x02e00000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts new file mode 100644 index 000000000000..e8991d4e248c --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul ABR-4500 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + label = "lan4"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan2"; + }; + + port@4 { + label = "lan1"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts new file mode 100644 index 000000000000..6875625869d9 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" + +/ { + compatible = "luxul,xap-1610-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XAP-1610 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "poe"; + }; + + port@1 { + label = "lan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts new file mode 100644 index 000000000000..7cfa4607ef31 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XBR-4500 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + + led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + label = "lan4"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan2"; + }; + + port@4 { + label = "lan1"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts new file mode 100644 index 000000000000..d55e10095eae --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2019 Legrand AV Inc. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,xwc-2000-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XWC-2000 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts new file mode 100644 index 000000000000..ccf031c0e276 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "luxul,xwr-3100-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XWR-3100 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-lan3 { + label = "bcm53xx:green:lan3"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + led-lan4 { + label = "bcm53xx:green:lan4"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + led-wan { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-lan1 { + label = "bcm53xx:green:lan1"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + led-lan2 { + label = "bcm53xx:green:lan2"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + + led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts new file mode 100644 index 000000000000..789dd2a3d226 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,xwr-3150-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XWR-3150 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + led-2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; + }; + + port@5 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts new file mode 100644 index 000000000000..76d562610654 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2016 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708"; + model = "Netgear R8500"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power0 { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + led-5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + + led-usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-brightness { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts new file mode 100644 index 000000000000..3bf6e24978ac --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Hamster Tian + * Copyright (C) 2019 Hao Dong + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; + model = "Phicomm K3"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x0080000 0x0100000>; + }; + + partition@180000{ + label = "phicomm"; + reg = <0x0180000 0x0280000>; + read-only; + }; + + partition@400000 { + label = "firmware"; + reg = <0x0400000 0x7C00000>; + compatible = "brcm,trx"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094.dtsi b/arch/arm/boot/dts/broadcom/bcm47094.dtsi new file mode 100644 index 000000000000..6282363313e1 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2016 Rafał Miłecki + */ + +#include "bcm4708.dtsi" + +/ { +}; + +&pinctrl { + compatible = "brcm,bcm4709-pinmux"; + + pinmux_mdio: mdio-pins { + groups = "mdio_grp"; + function = "mdio"; + }; +}; + +&usb3_phy { + compatible = "brcm,ns-bx-usb3-phy"; +}; + +&uart0 { + clock-frequency = <125000000>; + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts new file mode 100644 index 000000000000..0734aa249b8e --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-1440 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-wlan { + label = "bcm53xx:blue:wlan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + led-system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts new file mode 100644 index 000000000000..e6fb6cbe6963 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017 Luxul Inc. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-810 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + leds-0 { + compatible = "gpio-leds"; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + led-system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + leds-1 { + compatible = "gpio-leds"; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + ranges = <0x00000000 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + pcie0_chipcommon: chipcommon@0 { + reg = <0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts new file mode 100644 index 000000000000..dab2e5f63a72 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2016 Rafał Miłecki + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573"; + model = "Tenda AC9"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + leds-0 { + compatible = "gpio-leds"; + + led-usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + + led-system { + label = "bcm53xx:blue:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + leds-1 { + compatible = "gpio-leds"; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + ranges = <0x00000000 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + pcie0_chipcommon: chipcommon@0 { + reg = <0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&switch { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47622.dtsi b/arch/arm/boot/dts/broadcom/bcm47622.dtsi new file mode 100644 index 000000000000..7cd38de118c3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47622.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm47622", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts new file mode 100644 index 000000000000..03ad614e6b72 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR26 / Codename: Venom + * + * Copyright (C) 2022 Christian Lamparter + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708"; + model = "Meraki MR26"; + + memory@0 { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + led-1 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + key-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + clock-frequency = <50000000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x200000 0x200000>; + /* empty */ + }; + + partition@400000 { + label = "u-boot-backup"; + reg = <0x400000 0x200000>; + /* empty */ + }; + + partition@600000 { + label = "u-boot-env-backup"; + reg = <0x600000 0x200000>; + /* empty */ + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "poe"; + }; + + port@5 { + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + ina219@40 { + compatible = "ti,ina219"; /* PoE power */ + reg = <0x40>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + /* it's empty */ + }; +}; + +&thermal { + status = "disabled"; + /* does not work, reads 418 degree Celsius */ +}; diff --git a/arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts b/arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts new file mode 100644 index 000000000000..c1f54391746f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include +#include + +/ { + model = "D-Link DWL-8610AP"; + compatible = "dlink,dwl-8610ap", "brcm,bcm53016", "brcm,bcm4708"; + + memory@0 { + device_type = "memory"; + /* 512 MB RAM in 2 x Macronix D9PSH chips */ + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-diag { + /* Actually "diag" unclear what this means */ + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-wlan-2g { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + led-wlan-5g { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "reset"; + /* This GPIO is actually stored in NVRAM, but it's not gonna change */ + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + }; + + /* + * Flash memory at 0x1e000000-0x1fffffff + * Macronix 32 64KB blocks; total size 2MB, same that can be + * found attached to the spi_nor SPI controller. + */ + nvram@1e080000 { + compatible = "brcm,nvram"; + reg = <0x1e080000 0x00020000>; + + et0macaddr: et0macaddr { + }; + + et1macaddr: et1macaddr { + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + /* Serial SPI NOR Flash MX 25L1606E */ + status = "okay"; +}; + +&nandcs { + /* + * Spansion S34ML01G100TFI00 128 MB NAND Flash memory + * + * This ECC is a bit unorthodox but it is what the stock firmware + * is using, so to be able to mount the original partitions + * this is necessary. + */ + nand-ecc-strength = <5>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* This is named nflash1.trx in CFE */ + trx@0 { + label = "firmware"; + reg = <0x00000000 0x02800000>; + compatible = "brcm,trx"; + }; + + /* This is named nflash1.trx2 in CFE */ + trx2@2800000 { + label = "firmware2"; + reg = <0x02800000 0x02800000>; + compatible = "brcm,trx"; + }; + + /* This is named nflash1.rwfs in CFE */ + free@5000000 { + label = "free"; + reg = <0x05000000 0x03000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts new file mode 100644 index 000000000000..26c12bfb0bdd --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR32 / Codename: Espresso + * + * Copyright (C) 2018-2020 Christian Lamparter + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; + model = "Meraki MR32"; + + chosen { + bootargs = " console=ttyS0,115200n8 earlycon"; + }; + + memory@0 { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + aliases { + serial1 = &uart2; + }; + + leds { + compatible = "gpio-leds"; + + sysled3 { + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + sysled2 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led-0 { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 0 50000 0>; + max-brightness = <255>; + }; + + led-1 { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_POWER; + color = ; + pwms = <&pwm 1 50000 0>; + max-brightness = <255>; + }; + + led-2 { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 2 50000 0>; + max-brightness = <255>; + }; + }; +}; + +&uart0 { + clock-frequency = <62500000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "okay"; + /* + * bluetooth-le { + * compatible = "brcm,bcm20732"; + * enable-gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + *}; + */ +}; + +&gmac0 { + nvmem-cell-names = "mac-address"; + nvmem-cells = <&mac_address>; +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&pwm { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_pwm>; +}; + +&nandcs { + partitions { + /* + * The partition autodetection does not work for this device. + * It will only detect the "nvram" partition with an incorrect size. + * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0 + * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0": + * [ 1.733117] 0x000000400000-0x000008000000 : "nvram" + */ + + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + read-only; + }; + + partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + read-only; + }; + + partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + read-only; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "poe"; + }; + + port@5 { + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi new file mode 100644 index 000000000000..c349e8f0afc5 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar NAND. + * + * Copyright (C) 2016 Rafał Miłecki + */ + +#include "bcm5301x-nand-cs0.dtsi" + +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi new file mode 100644 index 000000000000..18e25e302b13 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016 Luxul Inc. + */ + +#include "bcm5301x-nand-cs0.dtsi" + +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi new file mode 100644 index 000000000000..c8e56d30bd6f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X Nand chip defaults. + * + * This should be included if the NAND controller is on chip select 0 + * and uses 8 bit ECC. + * + * Copyright (C) 2015 Hauke Mehrtens + */ + +#include "bcm5301x-nand-cs0.dtsi" + +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi new file mode 100644 index 000000000000..be9a00ff752d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar NAND. + * + * Copyright (C) 2015 Hauke Mehrtens + */ + +/ { + nand-controller@18028000 { + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm5301x.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi new file mode 100644 index 000000000000..600a1b54f2ae --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi @@ -0,0 +1,170 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include "bcm-ns.dtsi" + +/ { + mpcore-bus@19000000 { + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; + }; + + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + dmu-bus@1800c000 { + cru-bus@100 { + lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: clock-controller@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + }; + }; + + spi@18029200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18029200 0x184>, + <0x18029000 0x124>, + <0x1811b408 0x004>, + <0x180293a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&iprocmed>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "disabled"; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts new file mode 100644 index 000000000000..975f854f652f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts @@ -0,0 +1,86 @@ +/* + * DTS for Unifi Switch 8 port + * + * Copyright (C) 2017 Florian Fainelli + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm-hr2.dtsi" + +/ { + compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2"; + model = "Ubiquiti UniFi Switch 8 (BCM53342)"; + + /* Hurricane 2 designs use the second UART */ + chosen { + bootargs = "console=ttyS1,115200 earlyprintk"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x68000000 0x08000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + + flash: flash@0 { + compatible = "m25p80"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12500000>; + spi-cpol; + spi-cpha; + + partition@0 { + label = "u-boot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + partition@d0000 { + label = "shmoo"; + reg = <0xd0000 0x10000>; + }; + + partition@e0000 { + label = "kernel0"; + reg = <0xe0000 0xf00000>; + }; + + partition@fe0000 { + label = "kernel1"; + reg = <0xfe0000 0xf10000>; + }; + + partition@1ef0000 { + label = "cfg"; + reg = <0x1ef0000 0x100000>; + }; + + partition@1ff0000 { + label = "EEPROM"; + reg = <0x1ff0000 0x10000>; + }; + }; +}; + +&pcie0 { + /* Attaches to the internal switch */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm53573.dtsi b/arch/arm/boot/dts/broadcom/bcm53573.dtsi new file mode 100644 index 000000000000..3f03a381db0f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm53573.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2016 Rafał Miłecki + */ + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + mpcore@18310000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18310000 0x00008000>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x0100>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + alp: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + + /* IEEE 802.11 0 */ + <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + + /* IEEE 802.11 1 */ + <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + compatible = "simple-bus"; + reg = <0x00000000 0x1000>; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + gpio-controller; + #gpio-cells = <2>; + + uart0: serial@300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&alp>; + status = "okay"; + }; + }; + + pcie0: pcie@2000 { + reg = <0x00002000 0x1000>; + }; + + usb2: usb2@4000 { + reg = <0x4000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + ehci: usb@4000 { + compatible = "generic-ehci"; + reg = <0x4000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@d000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0xd000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + }; + + gmac0: ethernet@5000 { + reg = <0x5000 0x1000>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@1e { + compatible = "brcm,bcm53125"; + reg = <0x1e>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + gmac1: ethernet@b000 { + reg = <0xb000 0x1000>; + }; + + pmu@12000 { + compatible = "simple-mfd", "syscon"; + reg = <0x00012000 0x00001000>; + + ilp: ilp { + compatible = "brcm,bcm53573-ilp"; + clocks = <&alp>; + #clock-cells = <0>; + clock-output-names = "ilp"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm59056.dtsi b/arch/arm/boot/dts/broadcom/bcm59056.dtsi new file mode 100644 index 000000000000..a9bb7ad81378 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm59056.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* +* Copyright 2014 Linaro Limited +* Author: Matt Porter +*/ + +&pmu { + compatible = "brcm,bcm59056"; + regulators { + rfldo_reg: rfldo { + }; + + camldo1_reg: camldo1 { + }; + + camldo2_reg: camldo2 { + }; + + simldo1_reg: simldo1 { + }; + + simldo2_reg: simldo2 { + }; + + sdldo_reg: sdldo { + }; + + sdxldo_reg: sdxldo { + }; + + mmcldo1_reg: mmcldo1 { + }; + + mmcldo2_reg: mmcldo2 { + }; + + audldo_reg: audldo { + }; + + micldo_reg: micldo { + }; + + usbldo_reg: usbldo { + }; + + vibldo_reg: vibldo { + }; + + csr_reg: csr { + }; + + iosr1_reg: iosr1 { + }; + + iosr2_reg: iosr2 { + }; + + msr_reg: msr { + }; + + sdsr1_reg: sdsr1 { + }; + + sdsr2_reg: sdsr2 { + }; + + vsr_reg: vsr { + }; + + gpldo1_reg: gpldo1 { + }; + + gpldo2_reg: gpldo2 { + }; + + gpldo3_reg: gpldo3 { + }; + + gpldo4_reg: gpldo4 { + }; + + gpldo5_reg: gpldo5 { + }; + + gpldo6_reg: gpldo6 { + }; + + vbus_reg: vbus { + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi new file mode 100644 index 000000000000..93281c47c9ba --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom BCM63138 DSL SoCs Device Tree + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm63138", "brcm,bcmbca"; + model = "Broadcom BCM963138 Reference Board"; + interrupt-parent = <&gic>; + + aliases { + uart0 = &serial0; + uart1 = &serial1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + enable-method = "brcm,bcm63138"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <1>; + enable-method = "brcm,bcm63138"; + resets = <&pmb0 4 1>; + }; + }; + + clocks { + /* UBUS peripheral clock */ + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + + /* peripheral clock for system timer */ + axi_clk: axi_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* APB bus clock */ + apb_clk: apb_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x784000>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller@1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <1024>; + cache-line-size = <32>; + interrupts = ; + }; + + scu: scu@1e000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000 0x100>; + }; + + gic: interrupt-controller@1f000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1f000 0x1000 + 0x1e100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + + global_timer: timer@1e200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1e200 0x20>; + interrupts = ; + clocks = <&axi_clk>; + }; + + local_timer: local-timer@1e600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e600 0x20>; + interrupts = ; + clocks = <&axi_clk>; + }; + + twd_watchdog: watchdog@1e620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e620 0x20>; + interrupts = ; + }; + + armpll: armpll@20000 { + #clock-cells = <0>; + compatible = "brcm,bcm63138-armpll"; + clocks = <&periph_clk>; + reg = <0x20000 0xf00>; + }; + + pmb0: reset-controller@4800c0 { + compatible = "brcm,bcm63138-pmb"; + reg = <0x4800c0 0x10>; + #reset-cells = <2>; + }; + + pmb1: reset-controller@4800e0 { + compatible = "brcm,bcm63138-pmb"; + reg = <0x4800e0 0x10>; + #reset-cells = <2>; + }; + + ahci: sata@a000 { + compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0xa000 0x9ac>, <0x8040 0x24>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + resets = <&pmb0 3 1>; + reset-names = "ahci"; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + }; + }; + + sata_phy: sata-phy@8100 { + compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3"; + reg = <0x8100 0x1e00>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + }; + + /* Legacy UBUS base */ + ubus@fffe8000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8100>; + + timer: timer@80 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x80 0x3c>; + }; + + serial0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "disabled"; + }; + + serial1: serial@620 { + compatible = "brcm,bcm6345-uart"; + reg = <0x620 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "disabled"; + }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + nand_controller: nand-controller@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; + reg = <0x2000 0x600>, <0xf0 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + interrupts = ; + interrupt-names = "nand"; + }; + + bootlut: bootlut@8000 { + compatible = "brcm,bcm63138-bootlut"; + reg = <0x8000 0x50>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi new file mode 100644 index 000000000000..24431de1810e --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm63148", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + B15_0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B15_1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu: pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + ; + interrupt-affinity = <&B15_0>, <&B15_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@80030000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80030000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = ; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm63178.dtsi b/arch/arm/boot/dts/broadcom/bcm63178.dtsi new file mode 100644 index 000000000000..3f9aed96babf --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm63178.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm63178", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm6756.dtsi b/arch/arm/boot/dts/broadcom/bcm6756.dtsi new file mode 100644 index 000000000000..1d8d957d65dd --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm6756.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6756", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi new file mode 100644 index 000000000000..cf92cf8c4693 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6846", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm6855.dtsi b/arch/arm/boot/dts/broadcom/bcm6855.dtsi new file mode 100644 index 000000000000..52d6bc89f9f8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6855", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi new file mode 100644 index 000000000000..2c5d706bac7e --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6878", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = ; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts new file mode 100644 index 000000000000..f92d2cf85972 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm7445.dtsi" + +/ { + model = "Broadcom STB (bcm7445), SVMB reference board"; + compatible = "brcm,bcm7445", "brcm,brcmstb"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00000000 0x00 0x40000000>, + <0x00 0x40000000 0x00 0x40000000>, + <0x00 0x80000000 0x00 0x40000000>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@1 { + compatible = "brcm,nandcs"; + reg = <1>; + nand-ecc-step-size = <512>; + nand-ecc-strength = <8>; + nand-on-flash-bbt; + + #size-cells = <2>; + #address-cells = <2>; + + flash1.rootfs0@0 { + reg = <0x0 0x0 0x0 0x80000000>; + }; + + flash1.rootfs1@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm7445.dtsi b/arch/arm/boot/dts/broadcom/bcm7445.dtsi new file mode 100644 index 000000000000..5ac2042515b8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm7445.dtsi @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Broadcom STB (bcm7445)"; + compatible = "brcm,bcm7445", "brcm,brcmstb"; + interrupt-parent = <&gic>; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <1>; + }; + + cpu@2 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <2>; + }; + + cpu@3 { + compatible = "brcm,brahma-b15"; + device_type = "cpu"; + enable-method = "brcm,brahma-b15"; + reg = <3>; + }; + }; + + gic: interrupt-controller@ffd00000 { + compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; + reg = <0x00 0xffd01000 0x00 0x1000>, + <0x00 0xffd02000 0x00 0x2000>, + <0x00 0xffd04000 0x00 0x2000>, + <0x00 0xffd06000 0x00 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + rdb@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x00 0xf0000000 0x1000000>; + + serial@40ab00 { + compatible = "ns16550a"; + reg = <0x40ab00 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <81000000>; + }; + + sun_top_ctrl: syscon@404000 { + compatible = "brcm,bcm7445-sun-top-ctrl", + "syscon"; + reg = <0x404000 0x51c>; + }; + + hif_cpubiuctrl: syscon@3e2400 { + compatible = "brcm,bcm7445-hif-cpubiuctrl", + "syscon"; + reg = <0x3e2400 0x5b4>; + }; + + hif_continuation: syscon@452000 { + compatible = "brcm,bcm7445-hif-continuation", + "syscon"; + reg = <0x452000 0x100>; + }; + + irq0_intc: interrupt-controller@40a780 { + compatible = "brcm,bcm7120-l2-intc"; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + reg = <0x40a780 0x8>; + interrupt-controller; + interrupts = , + ; + brcm,int-map-mask = <0x25c>, <0x7000000>; + brcm,int-fwd-mask = <0x70000>; + }; + + irq0_aon_intc: interrupt-controller@417280 { + compatible = "brcm,bcm7120-l2-intc"; + reg = <0x417280 0x8>; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = , + , + ; + brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; + brcm,int-fwd-mask = <0x0>; + brcm,irq-can-wake; + }; + + hif_intr2_intc: interrupt-controller@3e1000 { + compatible = "brcm,l2-intc"; + reg = <0x3e1000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-names = "hif"; + }; + + aon_pm_l2_intc: interrupt-controller@410640 { + compatible = "brcm,l2-intc"; + reg = <0x410640 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + interrupt-parent = <&gic>; + brcm,irq-can-wake; + }; + + aon-ctrl@410000 { + compatible = "brcm,brcmstb-aon-ctrl"; + reg = <0x410000 0x200>, <0x410200 0x400>; + reg-names = "aon-ctrl", "aon-sram"; + }; + + nand_controller: nand-controller@3e2800 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg-names = "nand", "flash-dma"; + reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; + interrupt-parent = <&hif_intr2_intc>; + interrupts = <24>, <4>; + interrupt-names = "nand_ctlrdy", "flash_dma_done"; + }; + + sata@45a000 { + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0x45a000 0xa9c>, <0x458040 0x24>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + }; + }; + + sata_phy: sata-phy@458100 { + compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; + reg = <0x458100 0x1f00>; + reg-names = "phy"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + upg_gio: gpio@40a700 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x40a700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 24>; + }; + + upg_gio_aon: gpio@4172c0 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x4172c0 0x40>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupts-extended = <&irq0_aon_intc 0x6>, + <&aon_pm_l2_intc 0x5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; + + }; + + memory_controllers@f1100000 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0xf1100000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + + memc@0 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x80000>; + + memc-ddr@2000 { + compatible = "brcm,brcmstb-memc-ddr"; + reg = <0x2000 0x800>; + }; + + ddr-phy@6000 { + compatible = "brcm,brcmstb-ddr-phy-v240.1"; + reg = <0x6000 0x21c>; + }; + + shimphy@8000 { + compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; + reg = <0x8000 0xe4>; + }; + }; + + memc@80000 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x80000>; + + memc-ddr@2000 { + compatible = "brcm,brcmstb-memc-ddr"; + reg = <0x2000 0x800>; + }; + + ddr-phy@6000 { + compatible = "brcm,brcmstb-ddr-phy-v240.1"; + reg = <0x6000 0x21c>; + }; + + shimphy@8000 { + compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; + reg = <0x8000 0xe4>; + }; + }; + + memc@100000 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x80000>; + + memc-ddr@2000 { + compatible = "brcm,brcmstb-memc-ddr"; + reg = <0x2000 0x800>; + }; + + ddr-phy@6000 { + compatible = "brcm,brcmstb-ddr-phy-v240.1"; + reg = <0x6000 0x21c>; + }; + + shimphy@8000 { + compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; + reg = <0x8000 0xe4>; + }; + }; + }; + + sram@ffe00000 { + compatible = "brcm,boot-sram", "mmio-sram"; + reg = <0x0 0xffe00000 0x0 0x10000>; + }; + + smpboot { + compatible = "brcm,brcmstb-smpboot"; + syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; + syscon-cont = <&hif_continuation>; + }; + + reboot { + compatible = "brcm,brcmstb-reboot"; + syscon = <&sun_top_ctrl 0x304 0x308>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm911360_entphn.dts b/arch/arm/boot/dts/broadcom/bcm911360_entphn.dts new file mode 100644 index 000000000000..363009e747b3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm911360_entphn.dts @@ -0,0 +1,99 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" +#include "dt-bindings/input/input.h" + +/ { + model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-hook { + label = "HOOK"; + linux,code = ; + gpios = <&gpio_asiu 48 0>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&v3d { + assigned-clocks = + <&mipipll BCM_CYGNUS_MIPIPLL>, + <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; + assigned-clock-rates = <525000000>, <300000000>; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&nand_controller { + nand@1 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm911360k.dts b/arch/arm/boot/dts/broadcom/bcm911360k.dts new file mode 100644 index 000000000000..091c73a46e08 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm911360k.dts @@ -0,0 +1,52 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus SVK (BCM911360K)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm94708.dts b/arch/arm/boot/dts/broadcom/bcm94708.dts new file mode 100644 index 000000000000..d9eb2040b963 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm94708.dts @@ -0,0 +1,49 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + model = "NorthStar SVK (BCM94708)"; + compatible = "brcm,bcm94708", "brcm,bcm4708"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm94709.dts b/arch/arm/boot/dts/broadcom/bcm94709.dts new file mode 100644 index 000000000000..618c812eef73 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm94709.dts @@ -0,0 +1,49 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + model = "NorthStar SVK (BCM94709)"; + compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts b/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts new file mode 100644 index 000000000000..3709baa2376f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2017 Broadcom + * Author: Florian Fainelli + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573"; + model = "Broadcom BCM947189ACDBMR"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + }; + + led-5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + + led-2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + }; + }; + + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + gpio-sck = <&chipcommon 21 0>; + gpio-miso = <&chipcommon 22 0>; + gpio-mosi = <&chipcommon 23 0>; + cs-gpios = <&chipcommon 24 0>; + #address-cells = <1>; + #size-cells = <0>; + + /* External BCM6802 MoCA chip is connected */ + }; +}; + +&pcie0 { + ranges = <0x00000000 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm947622.dts b/arch/arm/boot/dts/broadcom/bcm947622.dts new file mode 100644 index 000000000000..93b8ce22678d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm947622.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm953012er.dts b/arch/arm/boot/dts/broadcom/bcm953012er.dts new file mode 100644 index 000000000000..4fe3b3653376 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm953012er.dts @@ -0,0 +1,92 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + model = "NorthStar Enterprise Router (BCM953012ER)"; + compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + + button-restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "port0"; + }; + + port@1 { + reg = <1>; + label = "port1"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm953012hr.dts b/arch/arm/boot/dts/broadcom/bcm953012hr.dts new file mode 100644 index 000000000000..b070b69466bd --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm953012hr.dts @@ -0,0 +1,102 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2017 Broadcom + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + model = "NorthStar HR (BCM953012HR)"; + compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&nandcs { + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x07000000>; + }; +}; + +&spi_nor { + status = "okay"; + spi-max-frequency = <62500000>; + m25p,default-addr-width = <3>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000d0000>; + }; + partition@d000 { + label = "env"; + reg = <0x000d0000 0x00030000>; + }; + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x00900000>; + }; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm953012k.dts b/arch/arm/boot/dts/broadcom/bcm953012k.dts new file mode 100644 index 000000000000..f1e6bcaa1edd --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm953012k.dts @@ -0,0 +1,120 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + model = "NorthStar SVK (BCM953012K)"; + compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x07000000>; + }; + }; +}; + +&spi_nor { + status = "okay"; + spi-max-frequency = <62500000>; + m25p,default-addr-width = <3>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000d0000>; + }; + partition@d000 { + label = "env"; + reg = <0x000d0000 0x00030000>; + }; + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x00900000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958300k.dts b/arch/arm/boot/dts/broadcom/bcm958300k.dts new file mode 100644 index 000000000000..dda3e11b711f --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958300k.dts @@ -0,0 +1,77 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" +#include "bcm9hmidc.dtsi" + +/ { + model = "Cygnus SVK (BCM958300K)"; + compatible = "brcm,bcm58300", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&nand_controller { + nand@1 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958305k.dts b/arch/arm/boot/dts/broadcom/bcm958305k.dts new file mode 100644 index 000000000000..ea3c6b88b313 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958305k.dts @@ -0,0 +1,85 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" +#include "bcm9hmidc.dtsi" + +/ { + model = "Cygnus Wireless Audio (BCM958305K)"; + compatible = "brcm,bcm58305", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&nand_controller { + nand@1 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958522er.dts b/arch/arm/boot/dts/broadcom/bcm958522er.dts new file mode 100644 index 000000000000..15f023656df0 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958522er.dts @@ -0,0 +1,185 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958522ER)"; + compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; +}; + +/* USB 3 support needed to be complete */ + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58522-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958525er.dts b/arch/arm/boot/dts/broadcom/bcm958525er.dts new file mode 100644 index 000000000000..9b9c225a1fb3 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958525er.dts @@ -0,0 +1,197 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958525ER)"; + compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; +}; + +/* USB 3 support needed to be complete */ + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958525xmc.dts b/arch/arm/boot/dts/broadcom/bcm958525xmc.dts new file mode 100644 index 000000000000..ca9311452739 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958525xmc.dts @@ -0,0 +1,217 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus XMC (BCM958525xmc)"; + compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; +}; + +/* XHCI support needed to be complete */ + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "st,m41t81"; + reg = <0x68>; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958622hr.dts b/arch/arm/boot/dts/broadcom/bcm958622hr.dts new file mode 100644 index 000000000000..9db3c851451a --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958622hr.dts @@ -0,0 +1,227 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958622HR)"; + compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; +}; + +/* USB 3 and SLIC support needed to be complete */ + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + label = "cpu"; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958623hr.dts b/arch/arm/boot/dts/broadcom/bcm958623hr.dts new file mode 100644 index 000000000000..32786e7c4e12 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958623hr.dts @@ -0,0 +1,231 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958623HR)"; + compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; +}; + +/* USB 3 and SLIC support needed to be complete */ + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + label = "cpu"; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi new file mode 100644 index 000000000000..c54451dde6dd --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:wan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = ; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:wan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = ; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:wan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = ; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:wan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = ; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* amber:power */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&axi { + mdio-mux@3f1c0 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + reg = <0x3f1c0 0x4>; + mux-mask = <0x2000>; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port6: phy@0 { + reg = <0>; + }; + + phy_port7: phy@1 { + reg = <1>; + }; + + phy_port8: phy@2 { + reg = <2>; + }; + + phy_port9: phy@3 { + reg = <3>; + }; + + phy_port10: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii1>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan8"; + phy-handle = <&phy_port6>; + }; + + port@2 { + reg = <2>; + label = "lan9"; + phy-handle = <&phy_port7>; + }; + + port@3 { + reg = <3>; + label = "lan10"; + phy-handle = <&phy_port8>; + }; + + port@4 { + reg = <4>; + label = "lan11"; + phy-handle = <&phy_port9>; + }; + + port@5 { + reg = <5>; + label = "lan12"; + phy-handle = <&phy_port10>; + }; + }; + }; + }; + + mdio-mii@2000 { + reg = <0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <2 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii0>; + phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan3"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan4"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan5"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan6"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan7"; + phy-handle = <&phy_port5>; + }; + }; + }; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + port@0 { + label = "wan1"; + reg = <0>; + }; + + port@1 { + label = "wan2"; + reg = <1>; + }; + + sgmii0: port@4 { + label = "sw0"; + reg = <4>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sgmii1: port@5 { + label = "sw1"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000000..1830844c8404 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = ; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = ; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = ; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = ; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = ; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = ; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = ; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = ; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = ; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = ; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000000..9944566c1195 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000000..06939438e874 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts new file mode 100644 index 000000000000..112fddb1eed8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64W(A0)"; + compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts new file mode 100644 index 000000000000..de2e367c3e78 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W"; + compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts new file mode 100644 index 000000000000..d1b684dcdbfa --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65"; + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts new file mode 100644 index 000000000000..a2165aba3676 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65W. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65W"; + compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi new file mode 100644 index 000000000000..b0854d881ac6 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm-nsp.dtsi" +#include +#include +#include + +/ { + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 1 50000>; + max-brightness = <255>; + }; + + led-2 { + function = LED_FUNCTION_POWER; + color = ; + pwms = <&pwm 2 50000>; + max-brightness = <255>; + }; + + led-3 { + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 3 50000>; + max-brightness = <255>; + }; + }; +}; + +&amac2 { + status = "okay"; + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "shmoo"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x3f700000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_leds>; + + pwm_leds: pwm_leds { + function = "pwm"; + groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; + }; +}; + +&pwm { + status = "okay"; + #pwm-cells = <2>; +}; + +&uart0 { + clock-frequency = <62500000>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625hr.dts b/arch/arm/boot/dts/broadcom/bcm958625hr.dts new file mode 100644 index 000000000000..74263d98de73 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625hr.dts @@ -0,0 +1,254 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958625HR)"; + compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + label = "sfp"; + phy-mode = "sgmii"; + reg = <5>; + sfp = <&sfp>; + managed = "in-band-status"; + }; + + port@8 { + ethernet = <&amac2>; + label = "cpu"; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm958625k.dts b/arch/arm/boot/dts/broadcom/bcm958625k.dts new file mode 100644 index 000000000000..69ebc7a913a7 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm958625k.dts @@ -0,0 +1,271 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" + +/ { + model = "NorthStar Plus SVK (BCM958625K)"; + compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>; + + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; + + gpiobs: gpiobs { + function = "gpio_b"; + groups = "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", + "gpio_b_3_grp"; + }; + + pwmc: pwmc { + function = "pwm"; + groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; + }; + + emmc_sel: emmc_sel { + function = "emmc"; + groups = "emmc_grp"; + }; +}; + +&pwm { + status = "okay"; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +/* + * By default the sd slot is functional. For emmc to work add "<&emmc_sel>" + * and delete "<&nand_sel>" in "pinctrl-0" property of pinctrl node. Remove the + * bus-width property here and disable the nand node with status = "disabled";. + * + * Ex: pinctrl-0 = <&emmc_sel>, <&gpiobs>, <&pwmc>; + */ +&sdio { + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + label = "cpu"; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm963138.dts b/arch/arm/boot/dts/broadcom/bcm963138.dts new file mode 100644 index 000000000000..1b405c249213 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm963138.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + model = "Broadcom BCM963138 Reference Board"; + compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm963138dvt.dts b/arch/arm/boot/dts/broadcom/bcm963138dvt.dts new file mode 100644 index 000000000000..b5af61853a07 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm963138dvt.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom BCM63138 Reference Board DTS + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca"; + model = "Broadcom BCM963138DVT"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sectors-size = <16>; + }; +}; + +&ahci { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm963148.dts b/arch/arm/boot/dts/broadcom/bcm963148.dts new file mode 100644 index 000000000000..1f5d6d783f09 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm963148.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63148.dtsi" + +/ { + model = "Broadcom BCM963148 Reference Board"; + compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm963178.dts b/arch/arm/boot/dts/broadcom/bcm963178.dts new file mode 100644 index 000000000000..d036e99dd8d1 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm963178.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63178.dtsi" + +/ { + model = "Broadcom BCM963178 Reference Board"; + compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm96756.dts b/arch/arm/boot/dts/broadcom/bcm96756.dts new file mode 100644 index 000000000000..8b104f3fb14a --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm96756.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6756.dtsi" + +/ { + model = "Broadcom BCM96756 Reference Board"; + compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm96846.dts b/arch/arm/boot/dts/broadcom/bcm96846.dts new file mode 100644 index 000000000000..55852c229608 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm96846.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6846.dtsi" + +/ { + model = "Broadcom BCM96846 Reference Board"; + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm96855.dts b/arch/arm/boot/dts/broadcom/bcm96855.dts new file mode 100644 index 000000000000..2ad880af2104 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm96855.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6855.dtsi" + +/ { + model = "Broadcom BCM96855 Reference Board"; + compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm96878.dts b/arch/arm/boot/dts/broadcom/bcm96878.dts new file mode 100644 index 000000000000..b7af8ade7a9d --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm96878.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6878.dtsi" + +/ { + model = "Broadcom BCM96878 Reference Board"; + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm988312hr.dts b/arch/arm/boot/dts/broadcom/bcm988312hr.dts new file mode 100644 index 000000000000..e96bc3f2d5cf --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm988312hr.dts @@ -0,0 +1,231 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM988312HR)"; + compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; +}; + +/* USB 3 support needed to be complete */ + +&dma { + status = "okay"; +}; + +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + label = "cpu"; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi b/arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi new file mode 100644 index 000000000000..65397c088335 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi @@ -0,0 +1,42 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Broadcom human machine interface daughter card (bcm9hmidc) installed on + * bcm958300k/bcm958305k boards + */ + +&touchscreen { + touchscreen-inverted-x; + touchscreen-inverted-y; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/calxeda/Makefile b/arch/arm/boot/dts/calxeda/Makefile new file mode 100644 index 000000000000..f5126b6d26ad --- /dev/null +++ b/arch/arm/boot/dts/calxeda/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HIGHBANK) += \ + highbank.dtb \ + ecx-2000.dtb +dtb-$(CONFIG_ARCH_HIGHBANK) += \ + highbank.dtb \ + ecx-2000.dtb diff --git a/arch/arm/boot/dts/calxeda/ecx-2000.dts b/arch/arm/boot/dts/calxeda/ecx-2000.dts new file mode 100644 index 000000000000..f6eb71553b95 --- /dev/null +++ b/arch/arm/boot/dts/calxeda/ecx-2000.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2011-2012 Calxeda, Inc. + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda ECX-2000"; + compatible = "calxeda,ecx-2000"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0xff800000>; + }; + + memory@200000000 { + name = "memory"; + device_type = "memory"; + reg = <0x00000002 0x00000000 0x00000003 0x00000000>; + }; + + soc { + ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; + + timer { + compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + memory-controller@fff00000 { + compatible = "calxeda,ecx-2000-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = <1 9 0xf04>; + reg = <0xfff11000 0x1000>, + <0xfff12000 0x2000>, + <0xfff14000 0x2000>, + <0xfff16000 0x2000>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; + }; + }; +}; + +/include/ "ecx-common.dtsi" diff --git a/arch/arm/boot/dts/calxeda/ecx-common.dtsi b/arch/arm/boot/dts/calxeda/ecx-common.dtsi new file mode 100644 index 000000000000..ce5221c6b358 --- /dev/null +++ b/arch/arm/boot/dts/calxeda/ecx-common.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2011-2012 Calxeda, Inc. + */ + +/ { + chosen { + bootargs = "console=ttyAMA0"; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000002>; + cpu_off = <0x84000004>; + cpu_on = <0x84000006>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x10000>; + interrupts = <0 83 4>; + dma-coherent; + calxeda,port-phys = < &combophy5 0>, <&combophy0 0>, + <&combophy0 1>, <&combophy0 2>, + <&combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, + <&gpioh 7 1>; + calxeda,led-order = <4 0 1 2 3>; + }; + + sdhci@ffe0e000 { + compatible = "calxeda,hb-sdhci"; + reg = <0xffe0e000 0x1000>; + interrupts = <0 90 4>; + clocks = <&eclk>; + status = "disabled"; + }; + + ipc@fff20000 { + compatible = "arm,pl320", "arm,primecell"; + reg = <0xfff20000 0x1000>; + interrupts = <0 7 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpioe: gpio@fff30000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff30000 0x1000>; + interrupts = <0 14 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpiof: gpio@fff31000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff31000 0x1000>; + interrupts = <0 15 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpiog: gpio@fff32000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff32000 0x1000>; + interrupts = <0 16 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpioh: gpio@fff33000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff33000 0x1000>; + interrupts = <0 17 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + timer@fff34000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfff34000 0x1000>; + interrupts = <0 18 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + rtc@fff35000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0xfff35000 0x1000>; + interrupts = <0 19 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + serial@fff36000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xfff36000 0x1000>; + interrupts = <0 20 4>; + clocks = <&pclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + smic@fff3a000 { + compatible = "ipmi-smic"; + device_type = "ipmi"; + reg = <0xfff3a000 0x1000>; + interrupts = <0 24 4>; + reg-size = <4>; + reg-spacing = <4>; + }; + + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x108>; + }; + + a9pll: a9pll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x100>; + }; + + a9periphclk: a9periphclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9periph-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + + a9bclk: a9bclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9bus-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + + emmcpll: emmcpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x10C>; + }; + + eclk: eclk { + #clock-cells = <0>; + compatible = "calxeda,hb-emmc-clock"; + clocks = <&emmcpll>; + reg = <0x114>; + }; + + pclk: pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <150000000>; + }; + }; + }; + + dma@fff3d000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xfff3d000 0x1000>; + interrupts = <0 92 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4>, <0 78 4>, <0 79 4>; + dma-coherent; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4>, <0 81 4>, <0 82 4>; + dma-coherent; + }; + + combophy0: combo-phy@fff58000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff58000 0x1000>; + phydev = <5>; + }; + + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; + }; +}; diff --git a/arch/arm/boot/dts/calxeda/highbank.dts b/arch/arm/boot/dts/calxeda/highbank.dts new file mode 100644 index 000000000000..b6b0225a769e --- /dev/null +++ b/arch/arm/boot/dts/calxeda/highbank.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2011-2012 Calxeda, Inc. + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda Highbank"; + compatible = "calxeda,highbank"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@900 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x900>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@901 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x901>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@902 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x902>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@903 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x903>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0xff900000>; + }; + + soc { + ranges = <0x00000000 0x00000000 0xffffffff>; + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; + + timer@fff10600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfff10600 0x20>; + interrupts = <1 13 0xf01>; + clocks = <&a9periphclk>; + }; + + watchdog@fff10620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xfff10620 0x20>; + interrupts = <1 14 0xf01>; + clocks = <&a9periphclk>; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + interrupts = <0 70 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; + }; + + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; + + }; +}; + +/include/ "ecx-common.dtsi" diff --git a/arch/arm/boot/dts/cirrus/Makefile b/arch/arm/boot/dts/cirrus/Makefile new file mode 100644 index 000000000000..e944d3e2129d --- /dev/null +++ b/arch/arm/boot/dts/cirrus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb diff --git a/arch/arm/boot/dts/cirrus/ep7209.dtsi b/arch/arm/boot/dts/cirrus/ep7209.dtsi new file mode 100644 index 000000000000..57bdad2c1994 --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep7209.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Cirrus Logic EP7209"; + compatible = "cirrus,ep7209"; + + chosen { }; + + aliases { + gpio0 = &porta; + gpio1 = &portb; + gpio3 = &portd; + gpio4 = &porte; + serial0 = &uart1; + serial1 = &uart2; + spi0 = &spi; + timer0 = &timer1; + timer1 = &timer2; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm720t"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + clks: clks@80000000 { + #clock-cells = <1>; + compatible = "cirrus,ep7209-clk"; + reg = <0x80000000 0xc000>; + startup-frequency = <73728000>; + }; + + intc: intc@80000000 { + compatible = "cirrus,ep7209-intc"; + reg = <0x80000000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + porta: gpio@80000000 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000000 0x1 0x80000040 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + portb: gpio@80000001 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000001 0x1 0x80000041 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + portd: gpio@80000003 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000003 0x1 0x80000043 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + porte: gpio@80000083 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000083 0x1 0x800000c3 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + syscon1: syscon@80000100 { + compatible = "cirrus,ep7209-syscon1", "syscon"; + reg = <0x80000100 0x80>; + }; + + bus: bus@80000180 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "cirrus,ep7209-bus", "simple-bus"; + clocks = <&clks CLPS711X_CLK_BUS>; + reg = <0x80000180 0x80>; + ranges = < + 0 0 0x00000000 0x10000000 + 1 0 0x10000000 0x10000000 + 2 0 0x20000000 0x10000000 + 3 0 0x30000000 0x10000000 + 4 0 0x40000000 0x10000000 + 5 0 0x50000000 0x10000000 + 6 0 0x60000000 0x0000c000 + 7 0 0x70000000 0x00000080 + >; + }; + + fb: fb@800002c0 { + compatible = "cirrus,ep7209-fb"; + reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; + clocks = <&clks CLPS711X_CLK_BUS>; + syscon = <&syscon1>; + status = "disabled"; + }; + + timer1: timer@80000300 { + compatible = "cirrus,ep7209-timer"; + reg = <0x80000300 0x4>; + clocks = <&clks CLPS711X_CLK_TIMER1>; + interrupts = <8>; + }; + + timer2: timer@80000340 { + compatible = "cirrus,ep7209-timer"; + reg = <0x80000340 0x4>; + clocks = <&clks CLPS711X_CLK_TIMER2>; + interrupts = <9>; + }; + + pwm: pwm@80000400 { + compatible = "cirrus,ep7209-pwm"; + reg = <0x80000400 0x4>; + clocks = <&clks CLPS711X_CLK_PWM>; + #pwm-cells = <1>; + }; + + uart1: serial@80000480 { + compatible = "cirrus,ep7209-uart"; + reg = <0x80000480 0x80>; + interrupts = <12 13>; + clocks = <&clks CLPS711X_CLK_UART>; + syscon = <&syscon1>; + }; + + spi: spi@80000500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cirrus,ep7209-spi"; + reg = <0x80000500 0x4>; + interrupts = <15>; + clocks = <&clks CLPS711X_CLK_SPI>; + syscon = <&syscon3>; + status = "disabled"; + }; + + syscon2: syscon@80001100 { + compatible = "cirrus,ep7209-syscon2", "syscon"; + reg = <0x80001100 0x80>; + }; + + uart2: serial@80001480 { + compatible = "cirrus,ep7209-uart"; + reg = <0x80001480 0x80>; + interrupts = <28 29>; + clocks = <&clks CLPS711X_CLK_UART>; + syscon = <&syscon2>; + }; + + dai: dai@80002000 { + #sound-dai-cells = <0>; + compatible = "cirrus,ep7209-dai"; + reg = <0x80002000 0x604>; + clocks = <&clks CLPS711X_CLK_PLL>; + clock-names = "pll"; + interrupts = <32>; + syscon = <&syscon3>; + status = "disabled"; + }; + + syscon3: syscon@80002200 { + compatible = "cirrus,ep7209-syscon3", "syscon"; + reg = <0x80002200 0x40>; + }; + }; + + keypad: keypad { + compatible = "cirrus,ep7209-keypad"; + interrupt-parent = <&intc>; + interrupts = <16>; + syscon = <&syscon1>; + status = "disabled"; + }; + + mctrl: mctrl { + compatible = "cirrus,ep7209-mctrl-gpio"; + gpio,syscon-dev = <&syscon1 0 0>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts new file mode 100644 index 000000000000..7fb532f227af --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "ep7211.dtsi" +#include + +/ { + model = "Cirrus Logic EP7211 Development Board"; + compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x02000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0>; + brightness-levels = < + 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 + 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf + >; + default-brightness-level = <0x0>; + power-supply = <&blen>; + }; + + display: display { + model = "320x240x4"; + bits-per-pixel = <4>; + ac-prescale = <17>; + + display-timings { + native-mode = <&timing0>; + timing0: 320x240 { + hactive = <320>; + hback-porch = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vactive = <240>; + vback-porch = <0>; + vfront-porch = <0>; + vsync-len = <0>; + clock-frequency = <6500000>; + }; + }; + }; + + i2c: i2c { + compatible = "i2c-gpio"; + gpios = <&portd 4 GPIO_ACTIVE_HIGH>, + <&portd 5 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; + i2c-gpio,scl-output-only; + #address-cells = <1>; + #size-cells = <0>; + }; + + lcddc: lcddc { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT ENABLE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&portd 1 GPIO_ACTIVE_HIGH>; + }; + + blen: blen { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT ENABLE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&portd 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&bus { + flash: nor@0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fb { + display = <&display>; + lcd-supply = <&lcddc>; + status = "okay"; +}; + +&portd { + lcden { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LCD ENABLE"; + }; +}; diff --git a/arch/arm/boot/dts/cirrus/ep7211.dtsi b/arch/arm/boot/dts/cirrus/ep7211.dtsi new file mode 100644 index 000000000000..32a4e1237145 --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep7211.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "ep7209.dtsi" + +/ { + model = "Cirrus Logic EP7211"; + compatible = "cirrus,ep7211", "cirrus,ep7209"; +}; diff --git a/arch/arm/boot/dts/cnxt/Makefile b/arch/arm/boot/dts/cnxt/Makefile new file mode 100644 index 000000000000..d49df53f65a1 --- /dev/null +++ b/arch/arm/boot/dts/cnxt/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_DIGICOLOR) += \ + cx92755_equinox.dtb +dtb-$(CONFIG_ARCH_DIGICOLOR) += \ + cx92755_equinox.dtb diff --git a/arch/arm/boot/dts/cnxt/cx92755.dtsi b/arch/arm/boot/dts/cnxt/cx92755.dtsi new file mode 100644 index 000000000000..227675fbe820 --- /dev/null +++ b/arch/arm/boot/dts/cnxt/cx92755.dtsi @@ -0,0 +1,144 @@ +/* + * Device Tree Include file for the Conexant Digicolor CX92755 SoC + * + * Author: Baruch Siach + * + * Copyright (C) 2014 Paradox Innovation Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cnxt,cx92755"; + + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + main_clk: main_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + intc: interrupt-controller@f0000040 { + compatible = "cnxt,cx92755-ic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xf0000040 0x40>; + syscon = <&uc_regs>; + }; + + timer@f0000fc0 { + compatible = "cnxt,cx92755-timer"; + reg = <0xf0000fc0 0x40>; + interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; + clocks = <&main_clk>; + }; + + rtc@f0000c30 { + compatible = "cnxt,cx92755-rtc"; + reg = <0xf0000c30 0x18>; + interrupts = <25>; + }; + + watchdog@f0000fc0 { + compatible = "cnxt,cx92755-wdt"; + reg = <0xf0000fc0 0x8>; + clocks = <&main_clk>; + timeout-sec = <15>; + }; + + pinctrl: pinctrl@f0000e20 { + compatible = "cnxt,cx92755-pinctrl"; + reg = <0xf0000e20 0x100>; + gpio-controller; + #gpio-cells = <2>; + }; + + uc_regs: syscon@f00003a0 { + compatible = "cnxt,cx92755-uc", "syscon"; + reg = <0xf00003a0 0x10>; + }; + + uart0: serial@f0000740 { + compatible = "cnxt,cx92755-usart"; + reg = <0xf0000740 0x20>; + clocks = <&main_clk>; + interrupts = <44>; + status = "disabled"; + }; + + uart1: serial@f0000760 { + compatible = "cnxt,cx92755-usart"; + reg = <0xf0000760 0x20>; + clocks = <&main_clk>; + interrupts = <45>; + status = "disabled"; + }; + + uart2: serial@f0000780 { + compatible = "cnxt,cx92755-usart"; + reg = <0xf0000780 0x20>; + clocks = <&main_clk>; + interrupts = <46>; + status = "disabled"; + }; + + i2c: i2c@f0000120 { + compatible = "cnxt,cx92755-i2c"; + reg = <0xf0000120 0x10>; + interrupts = <28>; + clocks = <&main_clk>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/cnxt/cx92755_equinox.dts b/arch/arm/boot/dts/cnxt/cx92755_equinox.dts new file mode 100644 index 000000000000..026f556c8c50 --- /dev/null +++ b/arch/arm/boot/dts/cnxt/cx92755_equinox.dts @@ -0,0 +1,86 @@ +/* + * Device Tree file for the Conexant Equinox CX92755 EVK + * + * Author: Baruch Siach + * + * Copyright (C) 2014 Paradox Innovation Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "cx92755.dtsi" + +/ { + model = "Conexant Equinox CX92755 EVK"; + compatible = "cnxt,equinox", "cnxt,cx92755"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + memory@0 { + reg = <0 0x8000000>; + device_type = "memory"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c { + status = "okay"; +}; + +&pinctrl { + uart0_default: uart0_active { + pins = "GP_O0", "GP_O1"; + function = "client_b"; + }; +}; diff --git a/arch/arm/boot/dts/compulab-sb-som.dtsi b/arch/arm/boot/dts/compulab-sb-som.dtsi deleted file mode 100644 index f5e6216718d8..000000000000 --- a/arch/arm/boot/dts/compulab-sb-som.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - */ - -/ { - model = "CompuLab SB-SOM"; - compatible = "compulab,sb-som"; - - vsb_3v3: fixedregulator-v3_3 { - compatible = "regulator-fixed"; - regulator-name = "vsb_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - }; - - lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - hdmi_conn: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - }; -}; diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi deleted file mode 100644 index 227675fbe820..000000000000 --- a/arch/arm/boot/dts/cx92755.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Device Tree Include file for the Conexant Digicolor CX92755 SoC - * - * Author: Baruch Siach - * - * Copyright (C) 2014 Paradox Innovation Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cnxt,cx92755"; - - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - - main_clk: main_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - intc: interrupt-controller@f0000040 { - compatible = "cnxt,cx92755-ic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf0000040 0x40>; - syscon = <&uc_regs>; - }; - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; - - rtc@f0000c30 { - compatible = "cnxt,cx92755-rtc"; - reg = <0xf0000c30 0x18>; - interrupts = <25>; - }; - - watchdog@f0000fc0 { - compatible = "cnxt,cx92755-wdt"; - reg = <0xf0000fc0 0x8>; - clocks = <&main_clk>; - timeout-sec = <15>; - }; - - pinctrl: pinctrl@f0000e20 { - compatible = "cnxt,cx92755-pinctrl"; - reg = <0xf0000e20 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; - - uc_regs: syscon@f00003a0 { - compatible = "cnxt,cx92755-uc", "syscon"; - reg = <0xf00003a0 0x10>; - }; - - uart0: serial@f0000740 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000740 0x20>; - clocks = <&main_clk>; - interrupts = <44>; - status = "disabled"; - }; - - uart1: serial@f0000760 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000760 0x20>; - clocks = <&main_clk>; - interrupts = <45>; - status = "disabled"; - }; - - uart2: serial@f0000780 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000780 0x20>; - clocks = <&main_clk>; - interrupts = <46>; - status = "disabled"; - }; - - i2c: i2c@f0000120 { - compatible = "cnxt,cx92755-i2c"; - reg = <0xf0000120 0x10>; - interrupts = <28>; - clocks = <&main_clk>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/cx92755_equinox.dts b/arch/arm/boot/dts/cx92755_equinox.dts deleted file mode 100644 index 026f556c8c50..000000000000 --- a/arch/arm/boot/dts/cx92755_equinox.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Device Tree file for the Conexant Equinox CX92755 EVK - * - * Author: Baruch Siach - * - * Copyright (C) 2014 Paradox Innovation Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "cx92755.dtsi" - -/ { - model = "Conexant Equinox CX92755 EVK"; - compatible = "cnxt,equinox", "cnxt,cx92755"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory@0 { - reg = <0 0x8000000>; - device_type = "memory"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c { - status = "okay"; -}; - -&pinctrl { - uart0_default: uart0_active { - pins = "GP_O0", "GP_O1"; - function = "client_b"; - }; -}; diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts deleted file mode 100644 index d4a5237cee0a..000000000000 --- a/arch/arm/boot/dts/da850-enbw-cmc.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for AM1808 EnBW CMC board - * - * Copyright 2012 DENX Software Engineering GmbH - * Heiko Schocher - */ -/dts-v1/; -#include "da850.dtsi" - -/ { - compatible = "enbw,cmc", "ti,da850"; - model = "EnBW CMC"; - - soc@1c00000 { - serial0: serial@42000 { - status = "okay"; - }; - serial1: serial@10c000 { - status = "okay"; - }; - serial2: serial@10d000 { - status = "okay"; - }; - mdio: mdio@224000 { - status = "okay"; - }; - eth0: ethernet@220000 { - status = "okay"; - }; - }; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts deleted file mode 100644 index 0ca849885d1f..000000000000 --- a/arch/arm/boot/dts/da850-evm.dts +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree for DA850 EVM board - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; -#include "da850.dtsi" -#include - -/ { - compatible = "ti,da850-evm", "ti,da850"; - model = "DA850/AM1808/OMAP-L138 EVM"; - - chosen { - stdout-path = &serial2; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - ethernet0 = ð0; - spi0 = &spi1; - }; - - backlight: backlight-pwm { - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - power-supply = <&backlight_lcd>; - compatible = "pwm-backlight"; - /* - * The PWM here corresponds to production hardware. The - * schematic needs to be 1015171 (15 March 2010), Rev A - * or newer. - */ - pwms = <&ecap2 0 50000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <7>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, change the status below to 'disabled' then - * then change the status of the vpif below to 'okay' - */ - status = "okay"; - enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - baseboard_3v3: fixedregulator-3v3 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - baseboard_1v8: fixedregulator-1v8 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - backlight_lcd: backlight-regulator { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850-OMAPL138 EVM"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; -}; - -&ecap2 { - status = "okay"; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* - * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, - * AFSR, AMUTE - */ - 0x00 0x11111111 0xffffffff - /* AXR11, AXR12 */ - 0x04 0x00011000 0x000ff000 - >; - }; - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ - 0x1c 0x10110110 0xf0ff0ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&cpu { - cpu-supply = <&vdcdc3_reg>; -}; - -/* - * The standard da850-evm kits and SOM's are 375MHz so enable this operating - * point by default. Higher frequencies must be enabled for custom boards with - * other variants of the SoC. - */ -&opp_375 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - tps: tps@48 { - reg = <0x48>; - }; - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vdcdc2_reg>; - AVDD-supply = <&baseboard_3v3>; - DRVDD-supply = <&baseboard_3v3>; - DVDD-supply = <&baseboard_1v8>; - }; - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - tca6416_bb: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&wdt { - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <30000000>; - m25p,fast-read; - reg = <0>; - partition@0 { - label = "U-Boot-SPL"; - reg = <0x00000000 0x00010000>; - read-only; - }; - partition@1 { - label = "U-Boot"; - reg = <0x00010000 0x00080000>; - read-only; - }; - partition@2 { - label = "U-Boot-Env"; - reg = <0x00090000 0x00010000>; - read-only; - }; - partition@3 { - label = "Kernel"; - reg = <0x000a0000 0x00280000>; - }; - partition@4 { - label = "Filesystem"; - reg = <0x00320000 0x00400000>; - }; - partition@5 { - label = "MAC-Address"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; -}; - -ð0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; -}; - -&gpio { - status = "okay"; -}; - -/include/ "tps6507x.dtsi" - -&tps { - vdcdc1_2-supply = <&vbat>; - vdcdc3-supply = <&vbat>; - vldo1_2-supply = <&vbat>; - - regulators { - vdcdc1_reg: regulator@0 { - regulator-name = "VDCDC1_3.3V"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - }; - - vdcdc2_reg: regulator@1 { - regulator-name = "VDCDC2_3.3V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - vdcdc3_reg: regulator@2 { - regulator-name = "VDCDC3_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - ldo1_reg: regulator@3 { - regulator-name = "LDO1_1.8V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "LDO2_1.2V"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1320000>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 1 - 2 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "okay"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&vpif { - pinctrl-names = "default"; - pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, disable the ti,tilcdc,panel then - * change the status below to 'okay' - */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts deleted file mode 100644 index e379d6e7ad49..000000000000 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016 BayLibre, Inc. - */ -/dts-v1/; -#include "da850.dtsi" -#include -#include - -/ { - model = "DA850/AM1808/OMAP-L138 LCDK"; - compatible = "ti,da850-lcdk", "ti,da850"; - - aliases { - serial2 = &serial2; - ethernet0 = ð0; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@c0000000 { - /* 128 MB DDR2 SDRAM @ 0xc0000000 */ - reg = <0xc0000000 0x08000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dsp_memory_region: dsp-memory@c3000000 { - compatible = "shared-dma-pool"; - reg = <0xc3000000 0x1000000>; - reusable; - status = "okay"; - }; - }; - - vcc_5vd: fixedregulator-vcc_5vd { - compatible = "regulator-fixed"; - regulator-name = "vcc_5vd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vcc_3v3d: fixedregulator-vcc_3v3d { - /* TPS650250 - VDCDC1 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5vd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_1v8d: fixedregulator-vcc_1v8d { - /* TPS650250 - VDCDC2 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8d"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_5vd>; - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850-OMAPL138 LCDK"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out", - "Microphone", "Mic Jack"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - user1 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - - user2 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - }; - - vga-bridge { - compatible = "ti,ths8135"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&lcdc_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - ddc-i2c-bus = <&i2c0>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - cvdd: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "cvdd"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&cpu { - cpu-supply = <&cvdd>; -}; - -/* - * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are - * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we - * can't enable more than one OPP by default, since the controller sometimes - * becomes unresponsive after a transition. Fix the frequency at 456 MHz. - */ - -&opp_100 { - status = "disabled"; -}; - -&opp_200 { - status = "disabled"; -}; - -&opp_300 { - status = "disabled"; -}; - -&opp_456 { - status = "okay"; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* AHCLKX AFSX ACLKX */ - 0x00 0x00101010 0x00f0f0f0 - /* ARX13 ARX14 */ - 0x04 0x00000110 0x00000ff0 - >; - }; - - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ - 0x1c 0x10110010 0xf0ff00f0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* - * EMA_D[8], EMA_D[9], EMA_D[10], - * EMA_D[11], EMA_D[12], EMA_D[13], - * EMA_D[14], EMA_D[15] - */ - 0x20 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&serial2 { - pinctrl-names = "default"; - pinctrl-0 = <&serial2_rxtx_pins>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&sata_refclk { - status = "okay"; - clock-frequency = <100000000>; -}; - -&sata { - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - status = "okay"; - - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vcc_3v3d>; - AVDD-supply = <&vcc_3v3d>; - DRVDD-supply = <&vcc_3v3d>; - DVDD-supply = <&vcc_1v8d>; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - - op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 1 2 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "okay"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - - ti,davinci-nand-buswidth = <16>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - - /* - * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: - * "To boot from NAND Flash, the AIS should be written - * to NAND block 1 (NAND block 0 is not used by default)". - * The same doc mentions that for ROM "Silicon Revision 2.1", - * "Updated NAND boot mode to offer boot from block 0 or block 1". - * However the limitaion is left here by default for compatibility - * with older silicon and because it needs new boot pin settings - * not possible in stock LCDK. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot env"; - reg = <0 0x020000>; - }; - partition@20000 { - /* The LCDK defaults to booting from this partition */ - label = "u-boot"; - reg = <0x020000 0x080000>; - }; - partition@a0000 { - label = "free space"; - reg = <0x0a0000 0>; - }; - }; - }; - }; -}; - -&prictrl { - status = "okay"; -}; - -&memctrl { - status = "okay"; -}; - -&lcdc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - port { - lcdc_out_vga: endpoint { - remote-endpoint = <&vga_bridge_in>; - }; - }; -}; - -&vpif { - pinctrl-names = "default"; - pinctrl-0 = <&vpif_capture_pins>; - status = "okay"; -}; - -&dsp { - memory-region = <&dsp_memory_region>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts deleted file mode 100644 index afd04a423856..000000000000 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device tree for LEGO MINDSTORMS EV3 - * - * Copyright (C) 2017 David Lechner - */ - -/dts-v1/; -#include -#include -#include - -#include "da850.dtsi" - -/ { - compatible = "lego,ev3", "ti,da850"; - model = "LEGO MINDSTORMS EV3"; - - aliases { - serial1 = &serial1; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x04000000>; - }; - - /* - * The buttons on the EV3 are mapped to keyboard keys. - */ - gpio_keys { - compatible = "gpio-keys"; - label = "EV3 Brick Buttons"; - pinctrl-names = "default"; - pinctrl-0 = <&button_bias>; - - center { - label = "Center"; - linux,code = ; - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - left { - label = "Left"; - linux,code = ; - gpios = <&gpio 102 GPIO_ACTIVE_HIGH>; - }; - - back { - label = "Back"; - linux,code = ; - gpios = <&gpio 106 GPIO_ACTIVE_HIGH>; - }; - - right { - label = "Right"; - linux,code = ; - gpios = <&gpio 124 GPIO_ACTIVE_HIGH>; - }; - - down { - label = "Down"; - linux,code = ; - gpios = <&gpio 126 GPIO_ACTIVE_HIGH>; - }; - - up { - label = "Up"; - linux,code = ; - gpios = <&gpio 127 GPIO_ACTIVE_HIGH>; - }; - }; - - /* - * The EV3 has two built-in bi-color LEDs behind the buttons. - */ - leds { - compatible = "gpio-leds"; - - left_green { - label = "led0:green:brick-status"; - /* GP6[13] */ - gpios = <&gpio 103 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - right_red { - label = "led1:red:brick-status"; - /* GP6[7] */ - gpios = <&gpio 108 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - left_red { - label = "led0:red:brick-status"; - /* GP6[12] */ - gpios = <&gpio 109 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - right_green { - label = "led1:green:brick-status"; - /* GP6[14] */ - gpios = <&gpio 110 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - /* - * The EV3 is powered down by turning off the main 5V supply. - */ - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 107 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "pwm-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm0b_pins>; - pwms = <&ehrpwm0 1 1000000 0>; - amp-supply = <&>; - }; - - cvdd: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "cvdd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * This is a 5V current limiting regulator that is shared by USB, - * the sensor (input) ports, the motor (output) ports and the A/DC. - */ - vcc5v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 101 0>; - over-current-gpios = <&gpio 99 GPIO_ACTIVE_LOW>; - enable-active-high; - regulator-boot-on; - }; - - /* - * This is a simple voltage divider on VCC5V to provide a 2.5V - * reference signal to the ADC. - */ - adc_ref: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "adc ref"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - vin-supply = <&vcc5v>; - }; - - /* - * This is the amplifier for the speaker. - */ - amp: regulator3 { - compatible = "regulator-fixed"; - regulator-name = "amp"; - gpio = <&gpio 111 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* - * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack. - */ - battery { - compatible = "lego,ev3-battery"; - io-channels = <&adc 4>, <&adc 3>; - io-channel-names = "voltage", "current"; - rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; - }; - - bt_slow_clk: bt-clock { - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>; - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&ecap2 0 30518 0>; - }; - - /* ARM local RAM */ - memory@ffff0000 { - compatible = "syscon", "simple-mfd"; - reg = <0xffff0000 0x2000>; /* 8k */ - - /* - * The I2C bootloader looks for this magic value to either - * boot normally or boot into a firmware update mode. - */ - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x1ffc>; - mode-normal = <0x00000000>; - mode-loader = <0x5555aaaa>; - }; - }; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&cpu { - cpu-supply = <&cvdd>; -}; - -/* since we have a fixed regulator, we can't run at these points */ -&opp_100 { - status = "disabled"; -}; - -&opp_200 { - status = "disabled"; -}; - -/* - * The SoC is actually the 456MHz version, but because of the fixed regulator - * This is the fastest we can go. - */ -&opp_375 { - status = "okay"; -}; - -&pmx_core { - status = "okay"; - - ev3_lcd_pins: pinmux_lcd { - pinctrl-single,bits = < - /* SIMO, CLK */ - 0x14 0x00100100 0x00f00f00 - >; - }; -}; - -&pinconf { - status = "okay"; - - /* Buttons have external pulldown resistors */ - button_bias: button-bias-groups { - disable { - groups = "cp5", "cp24", "cp25", "cp28"; - bias-disable; - }; - }; - - bt_clock_bias: bt-clock-bias-groups { - disable { - groups = "cp2"; - bias-disable; - }; - }; - - bt_pic_bias: bt-pic-bias-groups { - disable { - groups = "cp20"; - bias-disable; - }; - }; -}; - -/* Input port 1 */ -&serial1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&serial1_rxtx_pins>; -}; - -&serial2 { - pinctrl-names = "default"; - pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>; - status = "okay"; - - bluetooth { - compatible = "ti,cc2560"; - clocks = <&bt_slow_clk>; - clock-names = "ext_clock"; - enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - nvmem-cells = <&bdaddr>; - nvmem-cell-names = "bd-address"; - }; -}; - -&rtc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - /* - * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC. - */ - eeprom@50 { - compatible = "microchip,24c128", "atmel,24c128"; - pagesize = <64>; - read-only; - reg = <0x50>; - #address-cells = <1>; - #size-cells = <1>; - - bdaddr: bdaddr@3f06 { - reg = <0x3f06 0x06>; - }; - }; -}; - -&wdt { - status = "okay"; -}; - -&mmc0 { - status = "okay"; - max-frequency = <50000000>; - bus-width = <4>; - cd-gpios = <&gpio 94 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>; - - flash@0 { - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - ti,spi-wdelay = <8>; - - /* Partitions are based on the official firmware from LEGO */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x40000>; - }; - - partition@40000 { - label = "U-Boot Env"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "Kernel"; - reg = <0x50000 0x200000>; - }; - - partition@250000 { - label = "Filesystem"; - reg = <0x250000 0xa50000>; - }; - - partition@cb0000 { - label = "Storage"; - reg = <0xcb0000 0x2f0000>; - }; - }; - }; - - adc: adc@3 { - compatible = "ti,ads7957"; - reg = <3>; - #io-channel-cells = <1>; - spi-max-frequency = <1000000>; - ti,spi-wdelay = <63>; - vref-supply = <&adc_ref>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&ev3_lcd_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - - display@0{ - compatible = "lego,ev3-lcd"; - reg = <0>; - spi-max-frequency = <10000000>; - a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; - }; -}; - -&ecap2 { - status = "okay"; -}; - -&ehrpwm0 { - status = "okay"; -}; - -&gpio { - status = "okay"; - - /* Don't pull down battery voltage adc io channel */ - batt_volt_en { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - }; - - /* Don't impede Bluetooth clock signal */ - bt_clock_en { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - input; - }; - - /* - * There is a PIC microcontroller for interfacing with an Apple MFi - * chip. This interferes with normal Bluetooth operation, so we need - * to make sure it is turned off. Note: The publicly available - * schematics from LEGO don't show that these pins are connected to - * anything, but they are present in the source code from LEGO. - */ - - bt_pic_en { - gpio-hog; - gpios = <51 GPIO_ACTIVE_HIGH>; - output-low; - }; - - bt_pic_rst { - gpio-hog; - gpios = <78 GPIO_ACTIVE_HIGH>; - output-high; - }; - - bt_pic_cts { - gpio-hog; - gpios = <87 GPIO_ACTIVE_HIGH>; - input; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&vcc5v>; -}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi deleted file mode 100644 index e46e4d22db39..000000000000 --- a/arch/arm/boot/dts/da850.dtsi +++ /dev/null @@ -1,964 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 DENX Software Engineering GmbH - * Heiko Schocher - */ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu: cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - clocks = <&psc0 14>; - operating-points-v2 = <&opp_table>; - }; - }; - - opp_table: opp-table { - compatible = "operating-points-v2"; - - opp_100: opp100-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000 950000 1050000>; - }; - - opp_200: opp110-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1100000 1050000 1160000>; - }; - - opp_300: opp120-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1200000 1140000 1320000>; - }; - - /* - * Original silicon was 300MHz max, so higher frequencies - * need to be enabled on a per-board basis if the chip is - * capable. - */ - - opp_375: opp120-375000000 { - status = "disabled"; - opp-hz = /bits/ 64 <375000000>; - opp-microvolt = <1200000 1140000 1320000>; - }; - - opp_456: opp130-456000000 { - status = "disabled"; - opp-hz = /bits/ 64 <456000000>; - opp-microvolt = <1300000 1250000 1350000>; - }; - }; - - arm { - #address-cells = <1>; - #size-cells = <1>; - ranges; - intc: interrupt-controller@fffee000 { - compatible = "ti,cp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <101>; - reg = <0xfffee000 0x2000>; - }; - }; - clocks: clocks { - ref_clk: ref_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "ref_clk"; - }; - sata_refclk: sata_refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sata_refclk"; - status = "disabled"; - }; - usb_refclkin: usb_refclkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "usb_refclkin"; - status = "disabled"; - }; - }; - dsp: dsp@11800000 { - compatible = "ti,da850-dsp"; - reg = <0x11800000 0x40000>, - <0x11e00000 0x8000>, - <0x11f00000 0x8000>, - <0x01c14044 0x4>, - <0x01c14174 0x8>; - reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&psc0 15>; - resets = <&psc0 15>; - status = "disabled"; - }; - soc@1c00000 { - compatible = "simple-bus"; - model = "da850"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x01c00000 0x400000>; - interrupt-parent = <&intc>; - - psc0: clock-controller@10000 { - compatible = "ti,da850-psc0"; - reg = <0x10000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, - <&pll0_sysclk 4>, <&pll0_sysclk 6>, - <&async1_clk>; - clock-names = "pll0_sysclk1", "pll0_sysclk2", - "pll0_sysclk4", "pll0_sysclk6", - "async1"; - }; - pll0: clock-controller@11000 { - compatible = "ti,da850-pll0"; - reg = <0x11000 0x1000>; - clocks = <&ref_clk>, <&pll1_sysclk 3>; - clock-names = "clksrc", "extclksrc"; - - pll0_pllout: pllout { - #clock-cells = <0>; - }; - pll0_sysclk: sysclk { - #clock-cells = <1>; - }; - pll0_auxclk: auxclk { - #clock-cells = <0>; - }; - pll0_obsclk: obsclk { - #clock-cells = <0>; - }; - }; - pmx_core: pinmux@14120 { - compatible = "pinctrl-single"; - reg = <0x14120 0x50>; - #pinctrl-cells = <2>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xf>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 17 0x8>, - <&range 17 8 0x4>, - <&range 26 8 0x4>, - <&range 34 80 0x8>, - <&range 129 31 0x8>; - status = "disabled"; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - serial0_rtscts_pins: pinmux_serial0_rtscts_pins { - pinctrl-single,bits = < - /* UART0_RTS UART0_CTS */ - 0x0c 0x22000000 0xff000000 - >; - }; - serial0_rxtx_pins: pinmux_serial0_rxtx_pins { - pinctrl-single,bits = < - /* UART0_TXD UART0_RXD */ - 0x0c 0x00220000 0x00ff0000 - >; - }; - serial1_rtscts_pins: pinmux_serial1_rtscts_pins { - pinctrl-single,bits = < - /* UART1_CTS UART1_RTS */ - 0x00 0x00440000 0x00ff0000 - >; - }; - serial1_rxtx_pins: pinmux_serial1_rxtx_pins { - pinctrl-single,bits = < - /* UART1_TXD UART1_RXD */ - 0x10 0x22000000 0xff000000 - >; - }; - serial2_rtscts_pins: pinmux_serial2_rtscts_pins { - pinctrl-single,bits = < - /* UART2_CTS UART2_RTS */ - 0x00 0x44000000 0xff000000 - >; - }; - serial2_rxtx_pins: pinmux_serial2_rxtx_pins { - pinctrl-single,bits = < - /* UART2_TXD UART2_RXD */ - 0x10 0x00220000 0x00ff0000 - >; - }; - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,bits = < - /* I2C0_SDA,I2C0_SCL */ - 0x10 0x00002200 0x0000ff00 - >; - }; - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,bits = < - /* I2C1_SDA, I2C1_SCL */ - 0x10 0x00440000 0x00ff0000 - >; - }; - mmc0_pins: pinmux_mmc_pins { - pinctrl-single,bits = < - /* MMCSD0_DAT[3] MMCSD0_DAT[2] - * MMCSD0_DAT[1] MMCSD0_DAT[0] - * MMCSD0_CMD MMCSD0_CLK - */ - 0x28 0x00222222 0x00ffffff - >; - }; - ehrpwm0a_pins: pinmux_ehrpwm0a_pins { - pinctrl-single,bits = < - /* EPWM0A */ - 0xc 0x00000002 0x0000000f - >; - }; - ehrpwm0b_pins: pinmux_ehrpwm0b_pins { - pinctrl-single,bits = < - /* EPWM0B */ - 0xc 0x00000020 0x000000f0 - >; - }; - ehrpwm1a_pins: pinmux_ehrpwm1a_pins { - pinctrl-single,bits = < - /* EPWM1A */ - 0x14 0x00000002 0x0000000f - >; - }; - ehrpwm1b_pins: pinmux_ehrpwm1b_pins { - pinctrl-single,bits = < - /* EPWM1B */ - 0x14 0x00000020 0x000000f0 - >; - }; - ecap0_pins: pinmux_ecap0_pins { - pinctrl-single,bits = < - /* ECAP0_APWM0 */ - 0x8 0x20000000 0xf0000000 - >; - }; - ecap1_pins: pinmux_ecap1_pins { - pinctrl-single,bits = < - /* ECAP1_APWM1 */ - 0x4 0x40000000 0xf0000000 - >; - }; - ecap2_pins: pinmux_ecap2_pins { - pinctrl-single,bits = < - /* ECAP2_APWM2 */ - 0x4 0x00000004 0x0000000f - >; - }; - spi0_pins: pinmux_spi0_pins { - pinctrl-single,bits = < - /* SIMO, SOMI, CLK */ - 0xc 0x00001101 0x0000ff0f - >; - }; - spi0_cs0_pin: pinmux_spi0_cs0 { - pinctrl-single,bits = < - /* CS0 */ - 0x10 0x00000010 0x000000f0 - >; - }; - spi0_cs3_pin: pinmux_spi0_cs3_pin { - pinctrl-single,bits = < - /* CS3 */ - 0xc 0x01000000 0x0f000000 - >; - }; - spi1_pins: pinmux_spi1_pins { - pinctrl-single,bits = < - /* SIMO, SOMI, CLK */ - 0x14 0x00110100 0x00ff0f00 - >; - }; - spi1_cs0_pin: pinmux_spi1_cs0 { - pinctrl-single,bits = < - /* CS0 */ - 0x14 0x00000010 0x000000f0 - >; - }; - mdio_pins: pinmux_mdio_pins { - pinctrl-single,bits = < - /* MDIO_CLK, MDIO_D */ - 0x10 0x00000088 0x000000ff - >; - }; - mii_pins: pinmux_mii_pins { - pinctrl-single,bits = < - /* - * MII_TXEN, MII_TXCLK, MII_COL - * MII_TXD_3, MII_TXD_2, MII_TXD_1 - * MII_TXD_0 - */ - 0x8 0x88888880 0xfffffff0 - /* - * MII_RXER, MII_CRS, MII_RXCLK - * MII_RXDV, MII_RXD_3, MII_RXD_2 - * MII_RXD_1, MII_RXD_0 - */ - 0xc 0x88888888 0xffffffff - >; - }; - lcd_pins: pinmux_lcd_pins { - pinctrl-single,bits = < - /* - * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], - * LCD_D[6], LCD_D[7] - */ - 0x40 0x22222200 0xffffff00 - /* - * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], - * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] - */ - 0x44 0x22222222 0xffffffff - /* LCD_D[8], LCD_D[9] */ - 0x48 0x00000022 0x000000ff - - /* LCD_PCLK */ - 0x48 0x02000000 0x0f000000 - /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ - 0x4c 0x02000022 0x0f0000ff - >; - }; - vpif_capture_pins: vpif_capture_pins { - pinctrl-single,bits = < - /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ - 0x38 0x11111111 0xffffffff - /* VP_DIN[10..15,0..1] */ - 0x3c 0x11111111 0xffffffff - /* VP_DIN[8..9] */ - 0x40 0x00000011 0x000000ff - >; - }; - vpif_display_pins: vpif_display_pins { - pinctrl-single,bits = < - /* VP_DOUT[2..7] */ - 0x40 0x11111100 0xffffff00 - /* VP_DOUT[10..15,0..1] */ - 0x44 0x11111111 0xffffffff - /* VP_DOUT[8..9] */ - 0x48 0x00000011 0x000000ff - /* - * VP_CLKOUT3, VP_CLKIN3, - * VP_CLKOUT2, VP_CLKIN2 - */ - 0x4c 0x00111100 0x00ffff00 - >; - }; - }; - prictrl: priority-controller@14110 { - compatible = "ti,da850-mstpri"; - reg = <0x14110 0x0c>; - status = "disabled"; - }; - cfgchip: chip-controller@1417c { - compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; - reg = <0x1417c 0x14>; - - usb_phy: usb-phy { - compatible = "ti,da830-usb-phy"; - #phy-cells = <1>; - clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; - clock-names = "usb0_clk48", "usb1_clk48"; - status = "disabled"; - }; - usb_phy_clk: usb-phy-clocks { - compatible = "ti,da830-usb-phy-clocks"; - #clock-cells = <1>; - clocks = <&psc1 1>, <&usb_refclkin>, - <&pll0_auxclk>; - clock-names = "fck", "usb_refclkin", "auxclk"; - }; - ehrpwm_tbclk: ehrpwm_tbclk { - compatible = "ti,da830-tbclksync"; - #clock-cells = <0>; - clocks = <&psc1 17>; - clock-names = "fck"; - }; - div4p5_clk: div4.5 { - compatible = "ti,da830-div4p5ena"; - #clock-cells = <0>; - clocks = <&pll0_pllout>; - clock-names = "pll0_pllout"; - }; - async1_clk: async1 { - compatible = "ti,da850-async1-clksrc"; - #clock-cells = <0>; - clocks = <&pll0_sysclk 3>, <&div4p5_clk>; - clock-names = "pll0_sysclk3", "div4.5"; - }; - async3_clk: async3 { - compatible = "ti,da850-async3-clksrc"; - #clock-cells = <0>; - clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; - clock-names = "pll0_sysclk2", "pll1_sysclk2"; - }; - }; - edma0: edma@0 { - compatible = "ti,edma3-tpcc"; - /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ - reg = <0x0 0x8000>; - reg-names = "edma3_cc"; - interrupts = <11 12>; - interrupt-names = "edma3_ccint", "edma3_ccerrint"; - #dma-cells = <2>; - - ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; - power-domains = <&psc0 0>; - }; - edma0_tptc0: tptc@8000 { - compatible = "ti,edma3-tptc"; - reg = <0x8000 0x400>; - interrupts = <13>; - interrupt-names = "edm3_tcerrint"; - power-domains = <&psc0 1>; - }; - edma0_tptc1: tptc@8400 { - compatible = "ti,edma3-tptc"; - reg = <0x8400 0x400>; - interrupts = <32>; - interrupt-names = "edm3_tcerrint"; - power-domains = <&psc0 2>; - }; - edma1: edma@230000 { - compatible = "ti,edma3-tpcc"; - /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ - reg = <0x230000 0x8000>; - reg-names = "edma3_cc"; - interrupts = <93 94>; - interrupt-names = "edma3_ccint", "edma3_ccerrint"; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>; - power-domains = <&psc1 0>; - }; - edma1_tptc0: tptc@238000 { - compatible = "ti,edma3-tptc"; - reg = <0x238000 0x400>; - interrupts = <95>; - interrupt-names = "edm3_tcerrint"; - power-domains = <&psc1 21>; - }; - serial0: serial@42000 { - compatible = "ti,da830-uart", "ns16550a"; - reg = <0x42000 0x100>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <25>; - clocks = <&psc0 9>; - power-domains = <&psc0 9>; - status = "disabled"; - }; - serial1: serial@10c000 { - compatible = "ti,da830-uart", "ns16550a"; - reg = <0x10c000 0x100>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <53>; - clocks = <&psc1 12>; - power-domains = <&psc1 12>; - status = "disabled"; - }; - serial2: serial@10d000 { - compatible = "ti,da830-uart", "ns16550a"; - reg = <0x10d000 0x100>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <61>; - clocks = <&psc1 13>; - power-domains = <&psc1 13>; - status = "disabled"; - }; - rtc0: rtc@23000 { - compatible = "ti,da830-rtc"; - reg = <0x23000 0x1000>; - interrupts = <19 - 19>; - clocks = <&pll0_auxclk>; - clock-names = "int-clk"; - status = "disabled"; - }; - i2c0: i2c@22000 { - compatible = "ti,davinci-i2c"; - reg = <0x22000 0x1000>; - interrupts = <15>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pll0_auxclk>; - status = "disabled"; - }; - i2c1: i2c@228000 { - compatible = "ti,davinci-i2c"; - reg = <0x228000 0x1000>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&psc1 11>; - power-domains = <&psc1 11>; - status = "disabled"; - }; - clocksource: timer@20000 { - compatible = "ti,da830-timer"; - reg = <0x20000 0x1000>; - interrupts = <21>, <22>; - interrupt-names = "tint12", "tint34"; - clocks = <&pll0_auxclk>; - }; - wdt: wdt@21000 { - compatible = "ti,davinci-wdt"; - reg = <0x21000 0x1000>; - clocks = <&pll0_auxclk>; - status = "disabled"; - }; - mmc0: mmc@40000 { - compatible = "ti,da830-mmc"; - reg = <0x40000 0x1000>; - cap-sd-highspeed; - cap-mmc-highspeed; - interrupts = <16>; - dmas = <&edma0 16 0>, <&edma0 17 0>; - dma-names = "rx", "tx"; - clocks = <&psc0 5>; - status = "disabled"; - }; - vpif: video@217000 { - compatible = "ti,da850-vpif"; - reg = <0x217000 0x1000>; - interrupts = <92>; - power-domains = <&psc1 9>; - status = "disabled"; - - /* VPIF capture port */ - port@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - - /* VPIF display port */ - port@1 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - mmc1: mmc@21b000 { - compatible = "ti,da830-mmc"; - reg = <0x21b000 0x1000>; - cap-sd-highspeed; - cap-mmc-highspeed; - interrupts = <72>; - dmas = <&edma1 28 0>, <&edma1 29 0>; - dma-names = "rx", "tx"; - clocks = <&psc1 18>; - status = "disabled"; - }; - ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x300000 0x2000>; - clocks = <&psc1 17>, <&ehrpwm_tbclk>; - clock-names = "fck", "tbclk"; - power-domains = <&psc1 17>; - status = "disabled"; - }; - ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x302000 0x2000>; - clocks = <&psc1 17>, <&ehrpwm_tbclk>; - clock-names = "fck", "tbclk"; - power-domains = <&psc1 17>; - status = "disabled"; - }; - ecap0: pwm@306000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x306000 0x80>; - clocks = <&psc1 20>; - clock-names = "fck"; - power-domains = <&psc1 20>; - status = "disabled"; - }; - ecap1: pwm@307000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x307000 0x80>; - clocks = <&psc1 20>; - clock-names = "fck"; - power-domains = <&psc1 20>; - status = "disabled"; - }; - ecap2: pwm@308000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x308000 0x80>; - clocks = <&psc1 20>; - clock-names = "fck"; - power-domains = <&psc1 20>; - status = "disabled"; - }; - spi0: spi@41000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,da830-spi"; - reg = <0x41000 0x1000>; - num-cs = <6>; - ti,davinci-spi-intr-line = <1>; - interrupts = <20>; - dmas = <&edma0 14 0>, <&edma0 15 0>; - dma-names = "rx", "tx"; - clocks = <&psc0 4>; - power-domains = <&psc0 4>; - status = "disabled"; - }; - spi1: spi@30e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,da830-spi"; - reg = <0x30e000 0x1000>; - num-cs = <4>; - ti,davinci-spi-intr-line = <1>; - interrupts = <56>; - dmas = <&edma0 18 0>, <&edma0 19 0>; - dma-names = "rx", "tx"; - clocks = <&psc1 10>; - power-domains = <&psc1 10>; - status = "disabled"; - }; - usb0: usb@200000 { - compatible = "ti,da830-musb"; - reg = <0x200000 0x1000>; - ranges; - interrupts = <58>; - interrupt-names = "mc"; - dr_mode = "otg"; - phys = <&usb_phy 0>; - phy-names = "usb-phy"; - clocks = <&psc1 1>; - clock-ranges; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <1>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 0 1 &cppi41dma 1 1 - &cppi41dma 2 1 &cppi41dma 3 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", - "tx1", "tx2", "tx3", "tx4"; - - cppi41dma: dma-controller@201000 { - compatible = "ti,da830-cppi41"; - reg = <0x201000 0x1000 - 0x202000 0x1000 - 0x204000 0x4000>; - reg-names = "controller", - "scheduler", "queuemgr"; - interrupts = <58>; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <4>; - dma-channels = <4>; - power-domains = <&psc1 1>; - status = "okay"; - }; - }; - sata: sata@218000 { - compatible = "ti,da850-ahci"; - reg = <0x218000 0x2000>, <0x22c018 0x4>; - interrupts = <67>; - clocks = <&psc1 8>, <&sata_refclk>; - clock-names = "fck", "refclk"; - status = "disabled"; - }; - pll1: clock-controller@21a000 { - compatible = "ti,da850-pll1"; - reg = <0x21a000 0x1000>; - clocks = <&ref_clk>; - clock-names = "clksrc"; - - pll1_sysclk: sysclk { - #clock-cells = <1>; - }; - pll1_obsclk: obsclk { - #clock-cells = <0>; - }; - }; - mdio: mdio@224000 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x224000 0x1000>; - clocks = <&psc1 5>; - clock-names = "fck"; - power-domains = <&psc1 5>; - status = "disabled"; - }; - eth0: ethernet@220000 { - compatible = "ti,davinci-dm6467-emac"; - reg = <0x220000 0x4000>; - ti,davinci-ctrl-reg-offset = <0x3000>; - ti,davinci-ctrl-mod-reg-offset = <0x2000>; - ti,davinci-ctrl-ram-offset = <0>; - ti,davinci-ctrl-ram-size = <0x2000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <33 - 34 - 35 - 36 - >; - clocks = <&psc1 5>; - power-domains = <&psc1 5>; - status = "disabled"; - }; - usb1: usb@225000 { - compatible = "ti,da830-ohci"; - reg = <0x225000 0x1000>; - interrupts = <59>; - phys = <&usb_phy 1>; - phy-names = "usb-phy"; - clocks = <&psc1 2>; - status = "disabled"; - }; - gpio: gpio@226000 { - compatible = "ti,dm6441-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x226000 0x1000>; - interrupts = <42 43 44 45 46 47 48 49 50>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&psc1 3>; - clock-names = "gpio"; - status = "disabled"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx_core 0 15 1>, - <&pmx_core 1 14 1>, - <&pmx_core 2 13 1>, - <&pmx_core 3 12 1>, - <&pmx_core 4 11 1>, - <&pmx_core 5 10 1>, - <&pmx_core 6 9 1>, - <&pmx_core 7 8 1>, - <&pmx_core 8 7 1>, - <&pmx_core 9 6 1>, - <&pmx_core 10 5 1>, - <&pmx_core 11 4 1>, - <&pmx_core 12 3 1>, - <&pmx_core 13 2 1>, - <&pmx_core 14 1 1>, - <&pmx_core 15 0 1>, - <&pmx_core 16 39 1>, - <&pmx_core 17 38 1>, - <&pmx_core 18 37 1>, - <&pmx_core 19 36 1>, - <&pmx_core 20 35 1>, - <&pmx_core 21 34 1>, - <&pmx_core 22 33 1>, - <&pmx_core 23 32 1>, - <&pmx_core 24 24 1>, - <&pmx_core 25 22 1>, - <&pmx_core 26 21 1>, - <&pmx_core 27 20 1>, - <&pmx_core 28 19 1>, - <&pmx_core 29 18 1>, - <&pmx_core 30 17 1>, - <&pmx_core 31 16 1>, - <&pmx_core 32 55 1>, - <&pmx_core 33 54 1>, - <&pmx_core 34 53 1>, - <&pmx_core 35 52 1>, - <&pmx_core 36 51 1>, - <&pmx_core 37 50 1>, - <&pmx_core 38 49 1>, - <&pmx_core 39 48 1>, - <&pmx_core 40 47 1>, - <&pmx_core 41 46 1>, - <&pmx_core 42 45 1>, - <&pmx_core 43 44 1>, - <&pmx_core 44 43 1>, - <&pmx_core 45 42 1>, - <&pmx_core 46 41 1>, - <&pmx_core 47 40 1>, - <&pmx_core 48 71 1>, - <&pmx_core 49 70 1>, - <&pmx_core 50 69 1>, - <&pmx_core 51 68 1>, - <&pmx_core 52 67 1>, - <&pmx_core 53 66 1>, - <&pmx_core 54 65 1>, - <&pmx_core 55 64 1>, - <&pmx_core 56 63 1>, - <&pmx_core 57 62 1>, - <&pmx_core 58 61 1>, - <&pmx_core 59 60 1>, - <&pmx_core 60 59 1>, - <&pmx_core 61 58 1>, - <&pmx_core 62 57 1>, - <&pmx_core 63 56 1>, - <&pmx_core 64 87 1>, - <&pmx_core 65 86 1>, - <&pmx_core 66 85 1>, - <&pmx_core 67 84 1>, - <&pmx_core 68 83 1>, - <&pmx_core 69 82 1>, - <&pmx_core 70 81 1>, - <&pmx_core 71 80 1>, - <&pmx_core 72 70 1>, - <&pmx_core 73 78 1>, - <&pmx_core 74 77 1>, - <&pmx_core 75 76 1>, - <&pmx_core 76 75 1>, - <&pmx_core 77 74 1>, - <&pmx_core 78 73 1>, - <&pmx_core 79 72 1>, - <&pmx_core 80 103 1>, - <&pmx_core 81 102 1>, - <&pmx_core 82 101 1>, - <&pmx_core 83 100 1>, - <&pmx_core 84 99 1>, - <&pmx_core 85 98 1>, - <&pmx_core 86 97 1>, - <&pmx_core 87 96 1>, - <&pmx_core 88 95 1>, - <&pmx_core 89 94 1>, - <&pmx_core 90 93 1>, - <&pmx_core 91 92 1>, - <&pmx_core 92 91 1>, - <&pmx_core 93 90 1>, - <&pmx_core 94 89 1>, - <&pmx_core 95 88 1>, - <&pmx_core 96 158 1>, - <&pmx_core 97 157 1>, - <&pmx_core 98 156 1>, - <&pmx_core 99 155 1>, - <&pmx_core 100 154 1>, - <&pmx_core 101 129 1>, - <&pmx_core 102 113 1>, - <&pmx_core 103 112 1>, - <&pmx_core 104 111 1>, - <&pmx_core 105 110 1>, - <&pmx_core 106 109 1>, - <&pmx_core 107 108 1>, - <&pmx_core 108 107 1>, - <&pmx_core 109 106 1>, - <&pmx_core 110 105 1>, - <&pmx_core 111 104 1>, - <&pmx_core 112 145 1>, - <&pmx_core 113 144 1>, - <&pmx_core 114 143 1>, - <&pmx_core 115 142 1>, - <&pmx_core 116 141 1>, - <&pmx_core 117 140 1>, - <&pmx_core 118 139 1>, - <&pmx_core 119 138 1>, - <&pmx_core 120 137 1>, - <&pmx_core 121 136 1>, - <&pmx_core 122 135 1>, - <&pmx_core 123 134 1>, - <&pmx_core 124 133 1>, - <&pmx_core 125 132 1>, - <&pmx_core 126 131 1>, - <&pmx_core 127 130 1>, - <&pmx_core 128 159 1>, - <&pmx_core 129 31 1>, - <&pmx_core 130 30 1>, - <&pmx_core 131 20 1>, - <&pmx_core 132 28 1>, - <&pmx_core 133 27 1>, - <&pmx_core 134 26 1>, - <&pmx_core 135 23 1>, - <&pmx_core 136 153 1>, - <&pmx_core 137 152 1>, - <&pmx_core 138 151 1>, - <&pmx_core 139 150 1>, - <&pmx_core 140 149 1>, - <&pmx_core 141 148 1>, - <&pmx_core 142 147 1>, - <&pmx_core 143 146 1>; - }; - psc1: clock-controller@227000 { - compatible = "ti,da850-psc1"; - reg = <0x227000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, - <&async3_clk>; - clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; - assigned-clocks = <&async3_clk>; - assigned-clock-parents = <&pll1_sysclk 2>; - }; - pinconf: pin-controller@22c00c { - compatible = "ti,da850-pupd"; - reg = <0x22c00c 0x8>; - status = "disabled"; - }; - - mcasp0: mcasp@100000 { - compatible = "ti,da830-mcasp-audio"; - reg = <0x100000 0x2000>, - <0x102000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <54>; - interrupt-names = "common"; - power-domains = <&psc1 7>; - status = "disabled"; - dmas = <&edma0 1 1>, - <&edma0 0 1>; - dma-names = "tx", "rx"; - }; - - lcdc: display@213000 { - compatible = "ti,da850-tilcdc"; - reg = <0x213000 0x1000>; - interrupts = <52>; - max-pixelclock = <37500>; - clocks = <&psc1 16>; - clock-names = "fck"; - power-domains = <&psc1 16>; - status = "disabled"; - }; - }; - aemif: aemif@68000000 { - compatible = "ti,da850-aemif"; - #address-cells = <2>; - #size-cells = <1>; - - reg = <0x68000000 0x00008000>; - ranges = <0 0 0x60000000 0x08000000 - 1 0 0x68000000 0x00008000>; - clocks = <&psc0 3>; - clock-names = "aemif"; - clock-ranges; - status = "disabled"; - }; - memctrl: memory-controller@b0000000 { - compatible = "ti,da850-ddr-controller"; - reg = <0xb0000000 0xe8>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/dm3725.dtsi b/arch/arm/boot/dts/dm3725.dtsi deleted file mode 100644 index d24e906a14b1..000000000000 --- a/arch/arm/boot/dts/dm3725.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&sgx_module { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts deleted file mode 100644 index ae8d9fa09d16..000000000000 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm814x.dtsi" -#include - -/ { - model = "DM8148 EVM"; - compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f2g16aadwp"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - status = "disabled"; -}; - -&pincntl { - sd1_pins: sd1-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ - >; - }; - - usb0_pins: usb0-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: usb1-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts deleted file mode 100644 index f3e2ecf6d723..000000000000 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm814x.dtsi" - -/ { - model = "HP t410 Smart Zero Client"; - compatible = "hp,t410", "ti,dm8148", "ti,dm814"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* gpio9 seems to control USB VBUS regulator and/or hub power */ - usb_power: regulator@9 { - compatible = "regulator-fixed"; - regulator-name = "usb_power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&sd2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ - &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ - dma-names = "tx", "rx"; - non-removable; -}; - -&pincntl { - sd2_pins: sd2-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ - DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ - DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[5] */ - DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[4] */ - DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[3] */ - DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[2] */ - DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[1] */ - DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[0] */ - DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1) /* SD2_CLK */ - DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2) /* SD2_CMD */ - DM814X_IOPAD(0x0920, PIN_INPUT | 0x40) /* SD2_SDCD */ - >; - }; - - usb0_pins: usb0-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: usb1-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi deleted file mode 100644 index f7939f43413b..000000000000 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ /dev/null @@ -1,379 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&pllss { - /* - * See TRM "2.6.10 Connected outputso DPLLS" and - * "2.6.11 Connected Outputs of DPLLJ". Only clkout is - * connected except for hdmi and usb. - */ - adpll_mpu_ck: adpll@40 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-s-clock"; - reg = <0x40 0x40>; - clocks = <&devosc_ck &devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow", "clkinphif"; - clock-output-names = "481c5040.adpll.dcoclkldo", - "481c5040.adpll.clkout", - "481c5040.adpll.clkoutx2", - "481c5040.adpll.clkouthif"; - }; - - adpll_dsp_ck: adpll@80 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x80 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5080.adpll.dcoclkldo", - "481c5080.adpll.clkout", - "481c5080.adpll.clkoutldo"; - }; - - adpll_sgx_ck: adpll@b0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0xb0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c50b0.adpll.dcoclkldo", - "481c50b0.adpll.clkout", - "481c50b0.adpll.clkoutldo"; - }; - - adpll_hdvic_ck: adpll@e0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0xe0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c50e0.adpll.dcoclkldo", - "481c50e0.adpll.clkout", - "481c50e0.adpll.clkoutldo"; - }; - - adpll_l3_ck: adpll@110 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x110 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5110.adpll.dcoclkldo", - "481c5110.adpll.clkout", - "481c5110.adpll.clkoutldo"; - }; - - adpll_isp_ck: adpll@140 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x140 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5140.adpll.dcoclkldo", - "481c5140.adpll.clkout", - "481c5140.adpll.clkoutldo"; - }; - - adpll_dss_ck: adpll@170 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x170 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5170.adpll.dcoclkldo", - "481c5170.adpll.clkout", - "481c5170.adpll.clkoutldo"; - }; - - adpll_video0_ck: adpll@1a0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x1a0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c51a0.adpll.dcoclkldo", - "481c51a0.adpll.clkout", - "481c51a0.adpll.clkoutldo"; - }; - - adpll_video1_ck: adpll@1d0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x1d0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c51d0.adpll.dcoclkldo", - "481c51d0.adpll.clkout", - "481c51d0.adpll.clkoutldo"; - }; - - adpll_hdmi_ck: adpll@200 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x200 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5200.adpll.dcoclkldo", - "481c5200.adpll.clkout", - "481c5200.adpll.clkoutldo"; - }; - - adpll_audio_ck: adpll@230 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x230 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5230.adpll.dcoclkldo", - "481c5230.adpll.clkout", - "481c5230.adpll.clkoutldo"; - }; - - adpll_usb_ck: adpll@260 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x260 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5260.adpll.dcoclkldo", - "481c5260.adpll.clkout", - "481c5260.adpll.clkoutldo"; - }; - - adpll_ddr_ck: adpll@290 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x290 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5290.adpll.dcoclkldo", - "481c5290.adpll.clkout", - "481c5290.adpll.clkoutldo"; - }; -}; - -&pllss_clocks { - timer1_fck: timer1_fck@2e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <3>; - reg = <0x2e0>; - }; - - timer2_fck: timer2_fck@2e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <6>; - reg = <0x2e0>; - }; - - /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */ - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&adpll_video0_ck 1 - &adpll_video1_ck 1 - &adpll_audio_ck 1>; - ti,bit-shift = <1>; - reg = <0x2e8>; - }; - - /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */ - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - }; - - sysclk18_ck: sysclk18_ck@2f0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&rtcosc_ck>, <&rtcdivider_ck>; - ti,bit-shift = <0>; - reg = <0x02f0>; - }; -}; - -&scm_clocks { - devosc_ck: devosc_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; - ti,bit-shift = <21>; - reg = <0x0040>; - }; - - /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ - auxosc_ck: auxosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <22572900>; - }; - - /* Optional 32768Hz crystal or clock on RTCOSC pins */ - rtcosc_ck: rtcosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - /* Optional external clock on TCLKIN pin, set rate in baord dts file */ - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - virt_20000000_ck: virt_20000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - mpu_ck: mpu_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000000>; - }; -}; - -&prcm_clocks { - osc_src_ck: osc_src_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&devosc_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mpu_clksrc_ck: mpu_clksrc_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&devosc_ck>, <&rtcdivider_ck>; - ti,bit-shift = <0>; - reg = <0x0040>; - }; - - /* Fixed divider clock 0.0016384 * devosc */ - rtcdivider_ck: rtcdivider_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&devosc_ck>; - clock-mult = <128>; - clock-div = <78125>; - }; - - /* L4_HS 220 MHz*/ - sysclk4_ck: sysclk4_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - }; - - /* L4_FWCFG */ - sysclk5_ck: sysclk5_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <2>; - }; - - /* L4_LS 110 MHz */ - sysclk6_ck: sysclk6_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <2>; - }; - - sysclk8_ck: sysclk8_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_usb_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - }; - - sysclk10_ck: sysclk10_ck { - compatible = "ti,divider-clock"; - reg = <0x324>; - ti,max-div = <7>; - #clock-cells = <0>; - clocks = <&adpll_usb_ck 1>; - }; - - aud_clkin0_ck: aud_clkin0_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - aud_clkin1_ck: aud_clkin1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - aud_clkin2_ck: aud_clkin2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; -}; - -&prcm { - default_cm: default_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - default_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x5c>; - #clock-cells = <2>; - }; - }; - - alwon_cm: alwon_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x300>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x300>; - - alwon_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x228>; - #clock-cells = <2>; - }; - }; - - alwon_ethernet_cm: alwon_ethernet_cm@15d4 { - compatible = "ti,omap4-cm"; - reg = <0x15d4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x15d4 0x4>; - - alwon_ethernet_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0 0x4>; - #clock-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi deleted file mode 100644 index a8cd724ce4bc..000000000000 --- a/arch/arm/boot/dts/dm814x.dtsi +++ /dev/null @@ -1,788 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include - -/ { - compatible = "ti,dm814"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - usb: usb@47400000 { - compatible = "ti,am33xx-usb"; - reg = <0x47400000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0_phy: usb-phy@47401300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401300 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - - usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <30>; - dma-channels = <30>; - #dma-requests = <256>; - dma-requests = <256>; - }; - }; - - /* - * See TRM "Table 1-317. L4LS Instance Summary" for hints. - * It shows the module target agent registers though, so the - * actual device is typically 0x1000 before the target agent - * except in cases where the module is larger than 0x1000. - */ - l4ls: l4ls@48000000 { - compatible = "ti,dm814-l4ls", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x2000000>; - - i2c1: i2c@28000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - reg = <0x28000 0x1000>; - interrupts = <70>; - }; - - elm: elm@80000 { - compatible = "ti,814-elm"; - ti,hwmods = "elm"; - reg = <0x80000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@32000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x32000 0x2000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4c000 0x2000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@1ac000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - reg = <0x1ac000 0x2000>; - interrupts = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@1ae000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - reg = <0x1ae000 0x2000>; - interrupts = <62>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c2: i2c@2a000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - reg = <0x2a000 0x1000>; - interrupts = <71>; - }; - - mcspi1: spi@30000 { - compatible = "ti,omap4-mcspi"; - reg = <0x30000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 0 &edma 17 0 - &edma 18 0 &edma 19 0 - &edma 20 0 &edma 21 0 - &edma 22 0 &edma 23 0>; - - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@1a0000 { - compatible = "ti,omap4-mcspi"; - reg = <0x1a0000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <125>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi2"; - dmas = <&edma 42 0 &edma 43 0 - &edma 44 0 &edma 45 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - /* Board must configure dmas with edma_xbar for EDMA */ - mcspi3: spi@1a2000 { - compatible = "ti,omap4-mcspi"; - reg = <0x1a2000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <126>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi3"; - }; - - mcspi4: spi@1a4000 { - compatible = "ti,omap4-mcspi"; - reg = <0x1a4000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <127>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi4"; - }; - - timer1_target: target-module@2e000 { - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&timer1_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>; - - timer1: timer@0 { - compatible = "ti,am335x-timer-1ms"; - reg = <0x0 0x400>; - interrupts = <67>; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - }; - - uart1: serial@20000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x20000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 0 &edma 27 0>; - dma-names = "tx", "rx"; - }; - - uart2: serial@22000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x22000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 0 &edma 29 0>; - dma-names = "tx", "rx"; - }; - - uart3: serial@24000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x24000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 0 &edma 31 0>; - dma-names = "tx", "rx"; - }; - - timer2_target: target-module@40000 { - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&timer2_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - timer2: timer@0 { - compatible = "ti,dm814-timer"; - reg = <0 0x1000>; - interrupts = <68>; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - }; - - timer3: timer@42000 { - compatible = "ti,dm814-timer"; - reg = <0x42000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - mmc1: mmc@60000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - dmas = <&edma 24 0 - &edma 25 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - interrupt-parent = <&intc>; - reg = <0x60000 0x1000>; - }; - - rtc: rtc@c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0xc0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mmc2: mmc@1d8000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - interrupt-parent = <&intc>; - reg = <0x1d8000 0x1000>; - }; - - control: control@140000 { - compatible = "ti,dm814-scm", "simple-bus"; - reg = <0x140000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x140000 0x20000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,dm814-phy-gmii-sel"; - reg = <0x650 0x4>; - #phy-cells = <1>; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scm_clockdomains: clockdomains { - }; - }; - - usb_ctrl_mod: control@620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x620 0x10 - 0x648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - /* - * Note that silicon revision 2.1 and older - * require input enabled (bit 18 set) for all - * 3.3V I/Os to avoid cumulative hardware damage. - * For more info, see errata advisory 2.1.87. - * We leave bit 18 out of function-mask and rely - * on the bootloader for it. - */ - pincntl: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x438>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x307ff>; - }; - - usb1_phy: usb-phy@1b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x1b00 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - }; - - prcm: prcm@180000 { - compatible = "ti,dm814-prcm", "simple-bus"; - reg = <0x180000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x180000 0x2000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ - pllss: pllss@1c5000 { - compatible = "ti,dm814-pllss", "simple-bus"; - reg = <0x1c5000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1c5000 0x1000>; - - pllss_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - pllss_clockdomains: clockdomains { - }; - }; - - wdt1: wdt@1c7000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x1c7000 0x1000>; - interrupts = <91>; - }; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm814-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - /* Board must configure evtmux with edma_xbar for EDMA */ - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc3"; - interrupts = <29>; - interrupt-parent = <&intc>; - reg = <0x47810000 0x1000>; - }; - - target-module@49000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49000000 0x4>; - reg-names = "rev"; - clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49000000 0x10000>; - - edma: dma@0 { - compatible = "ti,edma3-tpcc"; - reg = <0 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 3>, <&edma_tptc3 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - }; - - target-module@49800000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49800000 0x4>, - <0x49800010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49800000 0x100000>; - - edma_tptc0: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49900000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49900000 0x4>, - <0x49900010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49900000 0x100000>; - - edma_tptc1: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49a00000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49a00000 0x4>, - <0x49a00010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49a00000 0x100000>; - - edma_tptc2: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49b00000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49b00000 0x4>, - <0x49b00010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49b00000 0x100000>; - - edma_tptc3: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <115>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - /* See TRM "Table 1-318. L4HS Instance Summary" */ - l4hs: l4hs@4a000000 { - compatible = "ti,dm814-l4hs", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x1b4040>; - - target-module@100000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x100900 0x4>, - <0x100908 0x4>, - <0x100904 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x100000 0x8000>; - - mac: ethernet@0 { - compatible = "ti,cpsw"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0 0x800>, - <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges = <0 0 0x8000>; - syscon = <&scm_conf>; - - davinci_mdio: mdio@800 { - compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; - clocks = <&cpsw_125mhz_gclk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x800 0x100>; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - }; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - reg = <0x50000000 0x2000>; - interrupts = <100>; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -#include "dm814x-clocks.dtsi" - -/* Preferred always-on timer for clocksource */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&timer1_fck>; - assigned-clock-parents = <&devosc_ck>; - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&timer2_fck>; - assigned-clock-parents = <&devosc_ck>; - }; -}; diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts deleted file mode 100644 index 1d80288f6ba5..000000000000 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm816x.dtsi" -#include - -/ { - model = "DM8168 EVM"; - compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000 /* 1 GB */ - 0xc0000000 0x40000000>; /* 1 GB */ - }; - - /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sata_refclk: fixedclock0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; -}; - -&dm816x_pinmux { - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ - >; - }; - - mmc_pins: mmc-pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ - DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ - DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ - DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ - DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ - DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ - DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ - >; - }; - - usb0_pins: usb0-pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: usb1-pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ - >; - }; - - nandflash_pins: nandflash-pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ - DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ - DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ - DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ - DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ - DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ - DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ - DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ - DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ - DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ - DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ - DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ - DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ - DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ - DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ - DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ - DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ - DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ - DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ - DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ - DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ - DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ - DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ - >; - }; -}; - -&i2c1 { - extgpio0: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c2 { - extgpio1: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name = "micron,mt29f2g16aadwp"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - flash@0 { - compatible = "w25x32"; - spi-max-frequency = <48000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; -}; - -/* At least dm8168-evm rev c won't support multipoint, later may */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - mentor,multipoint = <0>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - mentor,multipoint = <0>; -}; - -&sata { - clocks = <&sysclk5_ck>, <&sata_refclk>; -}; diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/dm816x-clocks.dtsi deleted file mode 100644 index 338449b32a18..000000000000 --- a/arch/arm/boot/dts/dm816x-clocks.dtsi +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&scrm { - main_fapll: main_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x400 0x40>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names = "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; - - ddr_fapll: ddr_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x440 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>; - clock-output-names = "ddr_pll_clk1", - "ddr_pll_clk2", - "ddr_pll_clk3", - "ddr_pll_clk4"; - }; - - video_fapll: video_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x470 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>; - clock-output-names = "video_pll_clk1", - "video_pll_clk2", - "video_pll_clk3"; - }; - - audio_fapll: audio_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x4a0 0x30>; - clocks = <&main_fapll 7>, < &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>; - clock-output-names = "audio_pll_clk1", - "audio_pll_clk2", - "audio_pll_clk3", - "audio_pll_clk4", - "audio_pll_clk5"; - }; -}; - -&scrm_clocks { - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clkin_ck: sys_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; -}; - -/* 0x48180000 */ -&prcm_clocks { - clkout_pre_ck: clkout_pre_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 - &audio_fapll 1>; - reg = <0x100>; - }; - - clkout_div_ck: clkout_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x100>; - }; - - clkout_ck: clkout_ck@100 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout_div_ck>; - ti,bit-shift = <7>; - reg = <0x100>; - }; - - /* CM_DPLL clocks p1795 */ - sysclk1_ck: sysclk1_ck@300 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 1>; - ti,max-div = <7>; - reg = <0x0300>; - }; - - sysclk2_ck: sysclk2_ck@304 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 2>; - ti,max-div = <7>; - reg = <0x0304>; - }; - - sysclk3_ck: sysclk3_ck@308 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 3>; - ti,max-div = <7>; - reg = <0x0308>; - }; - - sysclk4_ck: sysclk4_ck@30c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,max-div = <1>; - reg = <0x030c>; - }; - - sysclk5_ck: sysclk5_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclk4_ck>; - ti,max-div = <1>; - reg = <0x0310>; - }; - - sysclk6_ck: sysclk6_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,dividers = <2>, <4>; - reg = <0x0314>; - }; - - sysclk10_ck: sysclk10_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&ddr_fapll 2>; - ti,max-div = <7>; - reg = <0x0324>; - }; - - sysclk24_ck: sysclk24_ck@3b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 5>; - ti,max-div = <7>; - reg = <0x03b4>; - }; - - mpu_ck: mpu_ck@15dc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sysclk2_ck>; - ti,bit-shift = <1>; - reg = <0x15dc>; - }; - - audio_pll_a_ck: audio_pll_a_ck@35c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&audio_fapll 1>; - ti,max-div = <7>; - reg = <0x035c>; - }; - - sysclk18_ck: sysclk18_ck@378 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; - reg = <0x0378>; - }; - - timer1_fck: timer1_fck@390 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0390>; - }; - - timer2_fck: timer2_fck@394 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0394>; - }; - - timer3_fck: timer3_fck@398 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0398>; - }; - - timer4_fck: timer4_fck@39c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x039c>; - }; - - timer5_fck: timer5_fck@3a0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a0>; - }; - - timer6_fck: timer6_fck@3a4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a4>; - }; - - timer7_fck: timer7_fck@3a8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a8>; - }; -}; - -&prcm { - default_cm: default_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - default_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x5c>; - #clock-cells = <2>; - }; - }; - - alwon_cm: alwon_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x300>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x300>; - - alwon_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x208>; - #clock-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi deleted file mode 100644 index b68686f0643b..000000000000 --- a/arch/arm/boot/dts/dm816x.dtsi +++ /dev/null @@ -1,691 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include - -/ { - compatible = "ti,dm816"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = ð0; - ethernet1 = ð1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the dm816x interconnect. - * The real dm816x interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - reg = <0x44000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - prcm: prcm@48180000 { - compatible = "ti,dm816-prcm", "simple-bus"; - reg = <0x48180000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48180000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@48140000 { - compatible = "ti,dm816-scrm", "simple-bus"; - reg = <0x48140000 0x21000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x48140000 0x21000>; - - dm816x_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x50a>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xf>; - }; - - /* Device Configuration Registers */ - scm_conf: syscon@600 { - compatible = "syscon", "simple-bus"; - reg = <0x600 0x110>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x110>; - - usb_phy0: usb-phy@20 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x20 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - - usb_phy1: usb-phy@28 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x28 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - }; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - target-module@49000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49000000 0x4>; - reg-names = "rev"; - clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49000000 0x10000>; - - edma: dma@0 { - compatible = "ti,edma3-tpcc"; - reg = <0 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 3>, <&edma_tptc3 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - }; - - target-module@49800000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49800000 0x4>, - <0x49800010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49800000 0x100000>; - - edma_tptc0: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49900000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49900000 0x4>, - <0x49900010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49900000 0x100000>; - - edma_tptc1: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49a00000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49a00000 0x4>, - <0x49a00010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49a00000 0x100000>; - - edma_tptc2: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@49b00000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x49b00000 0x4>, - <0x49b00010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = ; - ti,sysc-sidle = , - ; - clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49b00000 0x100000>; - - edma_tptc3: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = <115>; - interrupt-names = "edma3_tcerrint"; - }; - }; - - elm: elm@48080000 { - compatible = "ti,am3352-elm"; - ti,hwmods = "elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@48032000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x48032000 0x1000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <6>; - gpmc,num-waitpins = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c1: i2c@48028000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <70>; - }; - - i2c2: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <71>; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm816-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - rtc: rtc@480c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x480c0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480c8000 0x2000>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <0 0 0>; - }; - }; - - spinbox: spinbox@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x2000>; - ti,hwmods = "spinbox"; - #hwlock-cells = <1>; - }; - - mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4a100800 0x100>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - phy1: ethernet-phy@1 { - reg = <2>; - }; - }; - - eth0: ethernet@4a100000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac0"; - reg = <0x4a100000 0x800 - 0x4a100900 0x3700>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <40 41 42 43>; - phy-handle = <&phy0>; - }; - - eth1: ethernet@4a120000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac1"; - reg = <0x4a120000 0x4000>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <44 45 46 47>; - phy-handle = <&phy1>; - }; - - sata: sata@4a140000 { - compatible = "ti,dm816-ahci"; - reg = <0x4a140000 0x10000>; - interrupts = <16>; - ti,hwmods = "sata"; - }; - - mcspi1: spi@48030000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48030000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 0 &edma 17 0 - &edma 18 0 &edma 19 0 - &edma 20 0 &edma 21 0 - &edma 22 0 &edma 23 0>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x11000>; - ti,hwmods = "mmc1"; - interrupts = <64>; - dmas = <&edma 24 0 &edma 25 0>; - dma-names = "tx", "rx"; - }; - - timer1_target: target-module@4802e000 { - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x4802e000 0x4>, - <0x4802e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4802e000 0x1000>; - - timer1: timer@0 { - compatible = "ti,dm816-timer"; - reg = <0 0x1000>; - interrupts = <67>; - ti,timer-alwon; - clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - }; - }; - - timer2_target: target-module@48040000 { - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x48040000 0x4>, - <0x48040010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48040000 0x1000>; - - timer2: timer@0 { - compatible = "ti,dm816-timer"; - reg = <0 0x1000>; - interrupts = <68>; - clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - }; - }; - - timer3: timer@48042000 { - compatible = "ti,dm816-timer"; - reg = <0x48042000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,dm816-timer"; - reg = <0x48044000 0x2000>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,dm816-timer"; - reg = <0x48046000 0x2000>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,dm816-timer"; - reg = <0x48048000 0x2000>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,dm816-timer"; - reg = <0x4804a000 0x2000>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - uart1: serial@48020000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x48020000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 0 &edma 27 0>; - dma-names = "tx", "rx"; - }; - - uart2: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x48022000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 0 &edma 29 0>; - dma-names = "tx", "rx"; - }; - - uart3: serial@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x48024000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 0 &edma 31 0>; - dma-names = "tx", "rx"; - }; - - /* NOTE: USB needs a transceiver driver for phys to work */ - usb: usb_otg_hs@47401000 { - compatible = "ti,am33xx-usb"; - reg = <0x47401000 0x400000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0: usb@47401000 { - compatible = "ti,musb-dm816"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-dm816"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <30>; - dma-channels = <30>; - #dma-requests = <256>; - dma-requests = <256>; - }; - }; - - wd_timer2: wd_timer@480c2000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x480c2000 0x1000>; - interrupts = <0>; - }; - }; -}; - -#include "dm816x-clocks.dtsi" - -/* Preferred always-on timer for clocksource */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&timer1_fck>; - assigned-clock-parents = <&sys_clkin_ck>; - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&timer2_fck>; - assigned-clock-parents = <&sys_clkin_ck>; - }; -}; diff --git a/arch/arm/boot/dts/dove-cm-a510.dtsi b/arch/arm/boot/dts/dove-cm-a510.dtsi deleted file mode 100644 index 1082fdfbfe60..000000000000 --- a/arch/arm/boot/dts/dove-cm-a510.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Device Tree include for Compulab CM-A510 System-on-Module - * - * Copyright (C) 2015, Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The CM-A510 comes with several optional components: - * - * Memory options: - * D512: 512M - * D1024: 1G - * - * NAND options: - * N512: 512M NAND - * - * Ethernet options: - * E1: PHY RTL8211D on internal GbE (SMI address 0x03) - * E2: Additional ethernet NIC RTL8111D on PCIe1 - * - * Audio options: - * A: TI TLV320AIC23b audio codec (I2C address 0x1a) - * - * Touchscreen options: - * I: TI TSC2046 touchscreen controller (on SPI1) - * - * USB options: - * U2: 2 dual-role USB2.0 ports - * U4: 2 additional USB2.0 host ports (via USB1) - * - * WiFi options: - * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1) - * - * GPIOs used on CM-A510: - * 1 GbE PHY reset (active low) - * 3 WakeUp - * 8 PowerOff (active low) - * 13 Touchscreen pen irq (active low) - * 65 System LED (active high) - * 69 USB Hub reset (active low) - * 70 WLAN reset (active low) - * 71 WLAN regulator (active high) - */ - -#include "dove.dtsi" - -/ { - model = "Compulab CM-A510"; - compatible = "compulab,cm-a510", "marvell,dove"; - - /* - * Set the minimum memory size here and let the - * bootloader set the real size. - */ - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - /* Set upper NAND data bit to GPO */ - pinctrl-0 = <&pmx_nand_gpo>; - pinctrl-names = "default"; - - led-system { - label = "cm-a510:system:green"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - wifi_power: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "WiFi Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* Optional RTL8211D GbE PHY on SMI address 0x03 */ -&mdio { - ethphy: ethernet-phy@3 { - reg = <3>; - status = "disabled"; - }; -}; - -ð { - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c0 { - /* Optional TI TLV320AIC23b audio codec */ - opt_audio: audio@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - status = "disabled"; - }; -}; - -/* Optional RTL8111D GbE NIC on PCIe1 */ -&pcie { status = "disabled"; }; - -&pcie1 { - pinctrl-0 = <&pmx_pcie1_clkreq>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&pinctrl { - pmx_uart2: pmx-uart2 { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "uart2"; - }; -}; - -/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */ -&sdio1 { - non-removable; - vmmc-supply = <&wifi_power>; - reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&spi0 { - status = "okay"; - - /* 1M Flash Winbond W25Q80BL */ - flash@0 { - compatible = "winbond,w25q80"; - spi-max-frequency = <80000000>; - reg = <0>; - }; -}; - -&spi1 { - pinctrl-0 = <&pmx_spi1_20_23>; - pinctrl-names = "default"; - status = "disabled"; - - /* Optional TI TSC2046 touchscreen controller */ - opt_touch: touchscreen@0 { - compatible = "ti,tsc2046"; - spi-max-frequency = <2500000>; - reg = <0>; - pinctrl-0 = <&pmx_gpio_13>; - pinctrl-names = "default"; - interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&uart2 { - pinctrl-0 = <&pmx_uart2>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/dove-cubox-es.dts b/arch/arm/boot/dts/dove-cubox-es.dts deleted file mode 100644 index ad361ec1361d..000000000000 --- a/arch/arm/boot/dts/dove-cubox-es.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "dove-cubox.dts" - -/ { - model = "SolidRun CuBox (Engineering Sample)"; - compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; -}; - -&sdio0 { - /* sdio0 card detect is connected to wrong pin on CuBox ES */ - cd-gpios = <&gpio0 12 1>; - pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; -}; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts deleted file mode 100644 index dbba0c8cdab1..000000000000 --- a/arch/arm/boot/dts/dove-cubox.dts +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "SolidRun CuBox"; - compatible = "solidrun,cubox", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_18>; - pinctrl-names = "default"; - - led-power { - label = "Power"; - gpios = <&gpio0 18 1>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 0>; - pinctrl-0 = <&pmx_gpio_1>; - pinctrl-names = "default"; - }; - }; - - clocks { - /* 25MHz reference crystal */ - ref25: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 19 1>; - pinctrl-0 = <&pmx_gpio_19>; - pinctrl-names = "default"; - }; - - gpu-subsystem { - status = "okay"; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&mdio { status = "okay"; }; -ð { - status = "okay"; - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&mdio { - ethphy: ethernet-phy@1 { - compatible = "marvell,88e1310"; - reg = <1>; - }; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - si5351: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - - clkout2 { - reg = <2>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - }; -}; - -&sdio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Winbond W25Q32BV */ - flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&audio1 { - status = "okay"; - clocks = <&gate_clk 13>, <&si5351 2>; - clock-names = "internal", "extclk"; - pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts deleted file mode 100644 index 79ee2b32409d..000000000000 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D2Plug"; - compatible = "globalscale,d2plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - led-wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 0 1>; - }; - - led-wlan-act { - label = "wlan-act"; - gpios = <&gpio0 1 1>; - }; - - led-bluetooth-act { - label = "bt-act"; - gpios = <&gpio0 2 1>; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; -&mdio { status = "okay"; }; -ð { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Macronix MX25L3205D */ - flash@0 { - compatible = "st,m25l3205d"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts deleted file mode 100644 index 5aa5d4a7d51d..000000000000 --- a/arch/arm/boot/dts/dove-d3plug.dts +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D3Plug"; - compatible = "globalscale,d3plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - led-wlan-act { - label = "wlan-act"; - gpios = <&gpio0 0 1>; - }; - - led-wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 1 1>; - }; - - led-status { - label = "status"; - gpios = <&gpio0 2 1>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 0>; - pinctrl-0 = <&pmx_gpio_8>; - pinctrl-names = "default"; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 2M Flash Macronix MX25L1605D */ - flash@0 { - compatible = "st,m25l1605d"; - spi-max-frequency = <86000000>; - reg = <0>; - }; -}; - -&pcie { - status = "okay"; - /* Fresco Logic USB3.0 xHCI controller */ - pcie@1 { - status = "okay"; - reset-gpios = <&gpio0 26 1>; - reset-delay-us = <20000>; - pinctrl-0 = <&pmx_camera_gpio>; - pinctrl-names = "default"; - }; - /* Mini-PCIe slot */ - pcie@2 { - status = "okay"; - reset-gpios = <&gpio0 25 1>; - }; -}; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts deleted file mode 100644 index c1912dc6bfc3..000000000000 --- a/arch/arm/boot/dts/dove-dove-db.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Marvell DB-MV88AP510-BP Development Board"; - compatible = "marvell,dove-db", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; -}; - -&uart0 { status = "okay"; }; -&uart1 { status = "okay"; }; -&sdio0 { status = "okay"; }; -&sdio1 { status = "okay"; }; -&sata0 { status = "okay"; }; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash ST-M25P32-VMF6P */ - flash@0 { - compatible = "st,m25p32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/dove-sbc-a510.dts b/arch/arm/boot/dts/dove-sbc-a510.dts deleted file mode 100644 index df021f9b0117..000000000000 --- a/arch/arm/boot/dts/dove-sbc-a510.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Device Tree file for Compulab SBC-A510 Single Board Computer - * - * Copyright (C) 2015, Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to - * - * 0.0 USB0 VBUS_EN (active high) - * 0.1 USB0 VBUS_GOOD - * 0.2 DVI transmitter TI TFP410 MSEN - * 0.3 DVI transmitter TI TFP410 PD# (active low power down) - * 0.4 LVDS transmitter DS90C365 PD# (active low power down) - * 0.5 LCD nRST (active low reset) - * 0.6 PCIe0 nRST (active low reset) - * 0.7 mini-PCIe slot W_DISABLE# - * - * 1.0 MMC WP - * 1.1 Camera Input FPC FLASH_STB and P21.5 - * 1.2 Camera Input FPC WE and P21.22 - * 1.3 MMC VCC_EN (active high) and P21.7 - * 1.4 Camera Input FPC AFTR_RST and P21.17 - * 1.5 Camera Input FPC OE and P21.19 - * 1.6 Camera Input FPC SNPSHT and P21.6 - * 1.7 Camera Input FPC SHTR and P21.10 - */ - -/dts-v1/; - -#include "dove-cm-a510.dtsi" - -/ { - model = "Compulab SBC-A510"; - compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove"; - - chosen { - stdout-path = &uart0; - }; - - regulators { - usb0_power: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; - }; - - mmc_power: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "MMC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* Ethernet0 depends on CM-A510 option E1 */ -&mdio { status = "disabled"; }; -ð { status = "disabled"; }; -ðphy { status = "disabled"; }; - -/* - * USB port 0 can be powered and monitored by I2C GPIO expander: - * VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1 - */ -&ehci0 { - status = "okay"; - vbus-supply = <&usb0_power>; -}; - -/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */ -&ehci1 { status = "okay"; }; - -/* - * I2C bus layout: - * i2c0: - * - Audio Codec, 0x1a (option from CM-A510) - * - DVI transmitter TI TFP410, 0x39 - * - HDMI/DVI DDC channel - * i2c1: - * - GPIO expander, NXP PCA9555, 0x20 - * - VGA DDC channel - */ -&i2c { - pinctrl-0 = <&pmx_i2c1>; - pinctrl-names = "default"; -}; - -&i2c0 { - /* TI TFP410 DVI transmitter */ - dvi: video@39 { - compatible = "ti,tfp410"; - reg = <0x39>; - powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - /* NXP PCA9555 GPIO expander */ - gpio_ext: gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pcie { status = "okay"; }; - -/* - * PCIe0 can be configured by Jumper E1 to be either connected to - * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge. - */ -&pcie0 { - status = "okay"; - pinctrl-0 = <&pmx_pcie0_clkreq>; - pinctrl-names = "default"; - reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>; -}; - -/* Ethernet1 depends on CM-A510 option E2 */ -&pcie1 { status = "disabled"; }; - -/* SATA connector */ -&sata0 { status = "okay"; }; - -/* - * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has - * VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10 - */ -&sdio0 { - vmmc-supply = <&mmc_power>; - wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* UART0 on RS232 mini-connector */ -&uart0 { status = "okay"; }; -/* UART2 on pin headers */ -&uart2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi deleted file mode 100644 index 062c86361640..000000000000 --- a/arch/arm/boot/dts/dove.dtsi +++ /dev/null @@ -1,820 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "marvell,dove"; - model = "Marvell Armada 88AP510 SoC"; - interrupt-parent = <&intc>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "marvell,pj4a", "marvell,sheeva-v7"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - }; - }; - - l2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0>; - }; - - gpu-subsystem { - compatible = "marvell,dove-gpu-subsystem"; - cores = <&gpu>; - status = "disabled"; - }; - - i2c-mux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c>; - - pinctrl-names = "i2c0", "i2c1", "i2c2"; - pinctrl-0 = <&pmx_i2cmux_0>; - pinctrl-1 = <&pmx_i2cmux_1>; - pinctrl-2 = <&pmx_i2cmux_2>; - - i2c0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; - - i2c1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - /* Requires pmx_i2c1 on i2c controller node */ - status = "disabled"; - }; - - i2c2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - /* Requires pmx_i2c2 on i2c controller node */ - status = "disabled"; - }; - }; - - mbus { - compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ - pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ - - ranges = ; /* PMU SRAM 1M */ - - pcie: pcie { - compatible = "marvell,dove-pcie"; - status = "disabled"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&intc>; - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 - 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 - 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ - 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ - 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ - 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - - pcie0: pcie@1 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - clocks = <&gate_clk 4>; - marvell,pcie-port = <0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - - #interrupt-cells = <1>; - interrupt-names = "intx", "error"; - interrupts = <16>, <15>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@2 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - clocks = <&gate_clk 5>; - marvell,pcie-port = <1>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - - #interrupt-cells = <1>; - interrupt-names = "intx", "error"; - interrupts = <18>, <17>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ - 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ - 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ - 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - clocks = <&core_clk 0>; - status = "okay"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <7>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "ns16550a"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "ns16550a"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - spi1: spi@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - sysc: system-ctrl@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x110>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - intc: interrupt-controller@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - watchdog@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&core_clk 0>; - }; - - crypto: crypto-engine@30000 { - compatible = "marvell,dove-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <31>; - clocks = <&gate_clk 15>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - eth: ethernet-ctrl@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - phys = <&sata_phy0>; - phy-names = "port0"; - nr-ports = <1>; - status = "disabled"; - }; - - sata_phy0: sata-phy@a2000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0xa2000 0x0334>; - clocks = <&gate_clk 3>; - clock-names = "sata"; - #phy-cells = <0>; - status = "okay"; - }; - - audio0: audio-controller@b0000 { - compatible = "marvell,dove-audio"; - reg = <0xb0000 0x2210>; - interrupts = <19>, <20>; - clocks = <&gate_clk 12>; - clock-names = "internal"; - status = "disabled"; - }; - - audio1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; - status = "disabled"; - }; - - pmu: power-management@d0000 { - compatible = "marvell,dove-pmu", "simple-bus"; - reg = <0xd0000 0x8000>, <0xd8000 0x8000>; - ranges = <0x00000000 0x000d0000 0x8000 - 0x00008000 0x000d8000 0x8000>; - interrupts = <33>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - #reset-cells = <1>; - - domains { - vpu_domain: vpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000008>; - marvell,pmu_iso_mask = <0x00000001>; - resets = <&pmu 16>; - }; - - gpu_domain: gpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000004>; - marvell,pmu_iso_mask = <0x00000002>; - resets = <&pmu 18>; - }; - }; - - thermal: thermal-diode@1c { - compatible = "marvell,dove-thermal"; - reg = <0x001c 0x0c>, <0x005c 0x08>; - }; - - gate_clk: clock-gating-ctrl@38 { - compatible = "marvell,dove-gating-clock"; - reg = <0x0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - divider_clk: core-clock@64 { - compatible = "marvell,dove-divider-clock"; - reg = <0x0064 0x8>; - #clock-cells = <1>; - }; - - pinctrl: pin-ctrl@200 { - compatible = "marvell,dove-pinctrl"; - reg = <0x0200 0x14>, - <0x0440 0x04>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_pcie1_clkreq: pmx-pcie1-clkreq { - marvell,pins = "mpp9"; - marvell,function = "pex1"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_pcie0_clkreq: pmx-pcie0-clkreq { - marvell,pins = "mpp11"; - marvell,function = "pex0"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_audio1_extclk: pmx-audio1-extclk { - marvell,pins = "mpp13"; - marvell,function = "audio1"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { - marvell,pins = "mpp_audio1"; - marvell,function = "i2s1/spdifo"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_spi1_4_7: pmx-spi1-4-7 { - marvell,pins = "mpp4", "mpp5", - "mpp6", "mpp7"; - marvell,function = "spi1"; - }; - - pmx_spi1_20_23: pmx-spi1-20-23 { - marvell,pins = "mpp20", "mpp21", - "mpp22", "mpp23"; - marvell,function = "spi1"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - - pmx_i2c1: pmx-i2c1 { - marvell,pins = "mpp17", "mpp19"; - marvell,function = "twsi"; - }; - - pmx_i2c2: pmx-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "twsi"; - }; - - pmx_ssp_i2c2: pmx-ssp-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "ssp/twsi"; - }; - - pmx_i2cmux_0: pmx-i2cmux-0 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt1"; - }; - - pmx_i2cmux_1: pmx-i2cmux-1 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt2"; - }; - - pmx_i2cmux_2: pmx-i2cmux-2 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt3"; - }; - }; - - core_clk: core-clocks@214 { - compatible = "marvell,dove-core-clock"; - reg = <0x0214 0x4>; - #clock-cells = <1>; - }; - - gpio0: gpio-ctrl@400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl@420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x0420 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <61>; - }; - - rtc: real-time-clock@8500 { - compatible = "marvell,orion-rtc"; - reg = <0x8500 0x20>; - interrupts = <5>; - }; - }; - - gconf: global-config@e802c { - compatible = "marvell,dove-global-config", - "syscon"; - reg = <0xe802c 0x14>; - }; - - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; - }; - - lcd1: lcd-controller@810000 { - compatible = "marvell,dove-lcd"; - reg = <0x810000 0x1000>; - interrupts = <46>; - status = "disabled"; - }; - - lcd0: lcd-controller@820000 { - compatible = "marvell,dove-lcd"; - reg = <0x820000 0x1000>; - interrupts = <47>; - status = "disabled"; - }; - - crypto_sram: sram@ffffe000 { - compatible = "mmio-sram"; - reg = <0xffffe000 0x800>; - clocks = <&gate_clk 15>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpu: gpu@840000 { - clocks = <÷r_clk 1>; - clock-names = "core"; - compatible = "vivante,gc"; - interrupts = <48>; - power-domains = <&gpu_domain>; - reg = <0x840000 0x4000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/dra62x-clocks.dtsi b/arch/arm/boot/dts/dra62x-clocks.dtsi deleted file mode 100644 index 11d1241b0e13..000000000000 --- a/arch/arm/boot/dts/dra62x-clocks.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "dm814x-clocks.dtsi" - -/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ -&adpll_hdvic_ck { - status = "disabled"; -}; - -&adpll_l3_ck { - status = "disabled"; -}; - -&adpll_dss_ck { - status = "disabled"; -}; - -/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ -&sysclk4_ck { - clocks = <&adpll_isp_ck 1>; -}; - -&sysclk5_ck { - clocks = <&adpll_isp_ck 1>; -}; - -&sysclk6_ck { - clocks = <&adpll_isp_ck 1>; -}; - -/* - * Compared to dm814x, dra62x has different shifts and more mux options. - * Please add the extra options for ysclk_14 and 16 if really needed. - */ -&timer1_fck { - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <4>; -}; - -&timer2_fck { - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <8>; -}; diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts deleted file mode 100644 index 2f6ac267fc15..000000000000 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dra62x.dtsi" -#include - -/ { - model = "DRA62x J5 Eco EVM"; - compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f2g16aadwp"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -}; - -&pincntl { - sd1_pins: sd1-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ - >; - }; - - usb0_pins: usb0-pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; -}; - -/* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "otg"; -}; - -&usb1_phy { - status = "disabled"; -}; - -&usb1 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/dra62x.dtsi deleted file mode 100644 index cfefa670515c..000000000000 --- a/arch/arm/boot/dts/dra62x.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "dm814x.dtsi" - -/ { - compatible = "ti,dra62x"; -}; - -/* Compared to dm814x, dra62x has different offsets for Ethernet */ -&mac { - reg = <0 0x800>, - <0x1200 0x100>; -}; - -&davinci_mdio { - reg = <0x1000 0x100>; -}; - -#include "dra62x-clocks.dtsi" diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi deleted file mode 100644 index 747ff0db90c7..000000000000 --- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for DRA7x SoC DSPEVE thermal - * - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include - -dspeve_thermal: dspeve_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 3>; - - trips { - dspeve_crit: dspeve_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi deleted file mode 100644 index 4cdffd6db740..000000000000 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "dra74-ipu-dsp-common.dtsi" -#include -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "dra7:usr1"; - gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "dra7:usr2"; - gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "dra7:usr3"; - gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "dra7:usr4"; - gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - USER1 { - label = "btnUser1"; - linux,code = ; - gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; - }; - - USER2 { - label = "btnUser2"; - linux,code = ; - gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; -}; - -&mcspi1 { - status = "okay"; -}; - -&mcspi2 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - flash@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x00010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&usb1 { - dr_mode = "otg"; - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - dr_mode = "host"; - extcon = <&extcon_usb2>; -}; - -&atl { - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = ; - aws = ; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&pcie1_rc { - status = "okay"; -}; - -&mmc4 { - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - #address-cells = <1>; - #size-cells = <0>; - wifi@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts deleted file mode 100644 index 46efbaa67a8e..000000000000 --- a/arch/arm/boot/dts/dra7-evm.dts +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "dra74x.dtsi" -#include "dra7-evm-common.dtsi" -#include "dra74x-mmc-iodelay.dtsi" - -/ { - model = "TI DRA742"; - compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ - }; - - evm_12v0: fixedregulator-evm_12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - vin-supply = <&smps9_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - - dsp2_memory_region: dsp2-memory@9f000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9f000000 0x0 0x800000>; - reusable; - status = "okay"; - }; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - evm_3v3_sw: fixedregulator-evm_3v3_sw { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sw"; - vin-supply = <&sysen1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3_sw>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_5v0: fixedregulator-evm_5v0 { - /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */ - compatible = "regulator-fixed"; - regulator-name = "evm_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_3v6: fixedregulator-evm_3v6 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v6"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - vin-supply = <&evm_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 8 0>; - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - vin-supply = <&sysen2>; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - -}; - -&dra7_pmx_core { - dcan1_pins_default: dcan1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1-sleep-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - ti,palmas-override-powerhold; - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps123_reg: smps123 { - /* VDD_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* CORE_VDD */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVAHD */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDS1V8 */ - regulator-name = "smps9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* VDD_RTCIO */ - /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - /* REGEN1 is unused */ - - regen2: regen2 { - /* Needed for PMIC internal resources */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - - /* REGEN3 is unused */ - - sysen1: sysen1 { - /* PMIC_REGEN_3V3 */ - regulator-name = "sysen1"; - regulator-boot-on; - regulator-always-on; - }; - - sysen2: sysen2 { - /* PMIC_REGEN_DDR */ - regulator-name = "sysen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - }; - - pcf_lcd: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_gpio_21: gpio@21 { - compatible = "nxp,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3_sw>; - IOVDD-supply = <&evm_3v3_sw>; - DRVDD-supply = <&evm_3v3_sw>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - pcf_hdmi: gpio@26 { - compatible = "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - hdmi-audio-hog { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&evm_3v3_sd>; - vqmmc-supply = <&ldo1_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is always hardwired. - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; - pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; - pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&evm_1v8_sw>; - vqmmc-supply = <&evm_1v8_sw>; - bus-width = <8>; - non-removable; - pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; - pinctrl-3 = <&mmc2_pins_ddr_rev20>; - pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; - pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; -}; - -&mmc4 { - status = "okay"; - vmmc-supply = <&evm_3v6>; - vqmmc-supply = <&vmmcwl_fixed>; - pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25"; - pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>; - pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>; - pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; - pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; - pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; - pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; - pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; - pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; -}; - -&cpu0 { - vdd-supply = <&smps123_reg>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * For the existing IOdelay configuration via U-Boot we don't - * support NAND on dra7-evm. Keep it disabled. Enabling it - * requires a different configuration by U-Boot. - */ - status = "disabled"; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&gpio7_target { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&mac_sw { - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - ethphy0: ethernet-phy@2 { - reg = <2>; - }; - - ethphy1: ethernet-phy@3 { - reg = <3>; - }; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; - -&dsp2 { - status = "okay"; - memory-region = <&dsp2_memory_region>; -}; diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi deleted file mode 100644 index a5bdc6431d8d..000000000000 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common IPU and DSP data for TI DRA7xx/AM57xx platforms - */ - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { - status = "okay"; - }; -}; - -&ipu2 { - mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; - ti,timers = <&timer3>; - ti,watchdog-timers = <&timer4>, <&timer9>; -}; - -&ipu1 { - mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; - ti,timers = <&timer11>; - ti,watchdog-timers = <&timer7>, <&timer8>; -}; - -&dsp1 { - mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; - ti,timers = <&timer5>; - ti,watchdog-timers = <&timer10>; -}; diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi deleted file mode 100644 index 0a31313065df..000000000000 --- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for DRA7x SoC IVA thermal - * - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include - -iva_thermal: iva_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 4>; - - trips { - iva_crit: iva_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi deleted file mode 100644 index 5733e3a4ea8e..000000000000 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ /dev/null @@ -1,4606 +0,0 @@ -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; - power-domains = <&prm_coreaon>; - clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ - <0x00100000 0x4a100000 0x100000>, /* segment 1 */ - <0x00200000 0x4a200000 0x100000>; /* segment 2 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x001000>, /* ap 2 */ - <0x00002000 0x00002000 0x002000>, /* ap 3 */ - <0x00004000 0x00004000 0x001000>, /* ap 4 */ - <0x00005000 0x00005000 0x001000>, /* ap 5 */ - <0x00006000 0x00006000 0x001000>, /* ap 6 */ - <0x00008000 0x00008000 0x002000>, /* ap 7 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ - <0x00056000 0x00056000 0x001000>, /* ap 9 */ - <0x00057000 0x00057000 0x001000>, /* ap 10 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ - <0x00060000 0x00060000 0x001000>, /* ap 12 */ - <0x00080000 0x00080000 0x008000>, /* ap 13 */ - <0x00088000 0x00088000 0x001000>, /* ap 14 */ - <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ - <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ - <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ - <0x000da000 0x000da000 0x001000>, /* ap 18 */ - <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ - <0x000de000 0x000de000 0x001000>, /* ap 20 */ - <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ - <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ - <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ - <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ - <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ - <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ - <0x00090000 0x00090000 0x008000>, /* ap 59 */ - <0x00098000 0x00098000 0x001000>; /* ap 60 */ - - target-module@2000 { /* 0x4a002000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x2000>; - - scm: scm@0 { - compatible = "ti,dra7-scm-core", "simple-bus"; - reg = <0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x1400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x1400>; - - pbias_regulator: pbias_regulator@e00 { - compatible = "ti,pbias-dra7", "ti,pbias-omap"; - reg = <0xe00 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,dra7xx-phy-gmii-sel"; - reg = <0x554 0x4>; - #phy-cells = <1>; - }; - - scm_conf_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dra7_pmx_core: pinmux@1400 { - compatible = "ti,dra7-padconf", - "pinctrl-single"; - reg = <0x1400 0x0468>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - - scm_conf1: scm_conf@1c04 { - compatible = "syscon"; - reg = <0x1c04 0x0020>; - #syscon-cells = <2>; - }; - - scm_conf_pcie: scm_conf@1c24 { - compatible = "syscon"; - reg = <0x1c24 0x0024>; - }; - - sdma_xbar: dma-router@b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xb78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; - }; - - edma_xbar: dma-router@c78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xc78 0x7c>; - #dma-cells = <2>; - dma-requests = <204>; - ti,dma-safe-map = <0>; - dma-masters = <&edma>; - }; - }; - }; - - target-module@5000 { /* 0x4a005000, ap 5 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - - cm_core_aon: cm_core_aon@0 { - compatible = "ti,dra7-cm-core-aon", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2000>; - ranges = <0 0 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm_core: cm_core@0 { - compatible = "ti,dra7-cm-core", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x3000>; - ranges = <0 0 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 9 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): core_pwrdm, dma_clkdm */ - clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@80000 { /* 0x4a080000, ap 13 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x80000 0x4>, - <0x80010 0x4>, - <0x80014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x8000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - reg = <0x0 0x20>; - - usb2_phy1: phy@4000 { - compatible = "ti,dra7x-usb2", "ti,omap-usb2"; - reg = <0x4000 0x400>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy1_always_on_clk32k>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb2_phy2: phy@5000 { - compatible = "ti,dra7x-usb2-phy2", - "ti,omap-usb2"; - reg = <0x5000 0x400>; - syscon-phy-power = <&scm_conf 0xe74>; - clocks = <&usb_phy2_always_on_clk32k>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb3_phy1: phy@4400 { - compatible = "ti,omap-usb3"; - reg = <0x4400 0x80>, - <0x4800 0x64>, - <0x4c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy3_always_on_clk32k>, - <&sys_clkin1>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - }; - - target-module@90000 { /* 0x4a090000, ap 59 42.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x90000 0x4>, - <0x90010 0x4>, - <0x90014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x8000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - reg = <0x0 0x20>; - - pcie1_phy: pciephy@4000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x4000 0x80>, /* phy_rx */ - <0x4400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x1c>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - }; - - pcie2_phy: pciephy@5000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x5000 0x80>, /* phy_rx */ - <0x5400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x20>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy: phy@6000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x6400 0x64>, /* phy_tx */ - <0x6800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin1>, - <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - syscon-pllreset = <&scm_conf 0x3fc>; - #phy-cells = <0>; - }; - }; - }; - - target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x8000>; - }; - - target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - reg = <0xd9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ - clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd9000 0x1000>; - - /* SmartReflex child device marked reserved in TRM */ - }; - - target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - reg = <0xdd038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ - clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xdd000 0x1000>; - - /* SmartReflex child device marked reserved in TRM */ - }; - - target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0000 0x1000>; - }; - - target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf4000 0x4>, - <0xf4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf4000 0x1000>; - - mailbox1: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - status = "disabled"; - }; - }; - - target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xf6000 0x4>, - <0xf6010 0x4>, - <0xf6014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf6000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ - <0x00003000 0x00103000 0x001000>, /* ap 28 */ - <0x00008000 0x00108000 0x001000>, /* ap 29 */ - <0x00009000 0x00109000 0x001000>, /* ap 30 */ - <0x00040000 0x00140000 0x010000>, /* ap 31 */ - <0x00050000 0x00150000 0x001000>, /* ap 32 */ - <0x00051000 0x00151000 0x001000>, /* ap 33 */ - <0x00052000 0x00152000 0x001000>, /* ap 34 */ - <0x00053000 0x00153000 0x001000>, /* ap 35 */ - <0x00054000 0x00154000 0x001000>, /* ap 36 */ - <0x00055000 0x00155000 0x001000>, /* ap 37 */ - <0x00056000 0x00156000 0x001000>, /* ap 38 */ - <0x00057000 0x00157000 0x001000>, /* ap 39 */ - <0x00058000 0x00158000 0x001000>, /* ap 40 */ - <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ - <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ - <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ - <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ - <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ - <0x00060000 0x00160000 0x001000>, /* ap 48 */ - <0x00061000 0x00161000 0x001000>, /* ap 49 */ - <0x00062000 0x00162000 0x001000>, /* ap 50 */ - <0x00063000 0x00163000 0x001000>, /* ap 51 */ - <0x00064000 0x00164000 0x001000>, /* ap 52 */ - <0x00065000 0x00165000 0x001000>, /* ap 53 */ - <0x00066000 0x00166000 0x001000>, /* ap 54 */ - <0x00067000 0x00167000 0x001000>, /* ap 55 */ - <0x00068000 0x00168000 0x001000>, /* ap 56 */ - <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ - <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ - <0x00071000 0x00171000 0x001000>, /* ap 61 */ - <0x00072000 0x00172000 0x001000>, /* ap 62 */ - <0x00073000 0x00173000 0x001000>, /* ap 63 */ - <0x00074000 0x00174000 0x001000>, /* ap 64 */ - <0x00075000 0x00175000 0x001000>, /* ap 65 */ - <0x00076000 0x00176000 0x001000>, /* ap 66 */ - <0x00077000 0x00177000 0x001000>, /* ap 67 */ - <0x00078000 0x00178000 0x001000>, /* ap 68 */ - <0x00081000 0x00181000 0x001000>, /* ap 69 */ - <0x00082000 0x00182000 0x001000>, /* ap 70 */ - <0x00083000 0x00183000 0x001000>, /* ap 71 */ - <0x00084000 0x00184000 0x001000>, /* ap 72 */ - <0x00085000 0x00185000 0x001000>, /* ap 73 */ - <0x00086000 0x00186000 0x001000>, /* ap 74 */ - <0x00087000 0x00187000 0x001000>, /* ap 75 */ - <0x00088000 0x00188000 0x001000>, /* ap 76 */ - <0x00069000 0x00169000 0x001000>, /* ap 103 */ - <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ - <0x00079000 0x00179000 0x001000>, /* ap 105 */ - <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ - <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ - <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ - <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ - <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ - <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ - <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ - <0x00059000 0x00159000 0x001000>, /* ap 125 */ - <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ - - target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@40000 { /* 0x4a140000, ap 31 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x400fc 4>, - <0x41100 4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - power-domains = <&prm_l3init>; - clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>; - clock-names = "fck"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - - sata: sata@0 { - compatible = "snps,dwc-ahci"; - reg = <0 0x1100>, <0x1100 0x8>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - ports-implemented = <0x1>; - }; - }; - - target-module@51000 { /* 0x4a151000, ap 33 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - }; - - target-module@53000 { /* 0x4a153000, ap 35 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - }; - - target-module@55000 { /* 0x4a155000, ap 37 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - }; - - target-module@57000 { /* 0x4a157000, ap 39 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - }; - - target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - }; - - target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5f000 0x1000>; - }; - - target-module@61000 { /* 0x4a161000, ap 49 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x61000 0x1000>; - }; - - target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x63000 0x1000>; - }; - - target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x65000 0x1000>; - }; - - target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x67000 0x1000>; - }; - - target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x69000 0x1000>; - }; - - target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6b000 0x1000>; - }; - - target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6d000 0x1000>; - }; - - target-module@71000 { /* 0x4a171000, ap 61 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x71000 0x1000>; - }; - - target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x73000 0x1000>; - }; - - target-module@75000 { /* 0x4a175000, ap 65 64.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x75000 0x1000>; - }; - - target-module@77000 { /* 0x4a177000, ap 67 66.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x77000 0x1000>; - }; - - target-module@79000 { /* 0x4a179000, ap 105 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x79000 0x1000>; - }; - - target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7b000 0x1000>; - }; - - target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7d000 0x1000>; - }; - - target-module@81000 { /* 0x4a181000, ap 69 26.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x81000 0x1000>; - }; - - target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x83000 0x1000>; - }; - - target-module@85000 { /* 0x4a185000, ap 73 36.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x85000 0x1000>; - }; - - target-module@87000 { /* 0x4a187000, ap 75 74.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x87000 0x1000>; - }; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ - <0x00019000 0x00219000 0x001000>, /* ap 44 */ - <0x00000000 0x00200000 0x001000>, /* ap 77 */ - <0x00001000 0x00201000 0x001000>, /* ap 78 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ - <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ - <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ - <0x00010000 0x00210000 0x001000>, /* ap 85 */ - <0x00011000 0x00211000 0x001000>, /* ap 86 */ - <0x00012000 0x00212000 0x001000>, /* ap 87 */ - <0x00013000 0x00213000 0x001000>, /* ap 88 */ - <0x00014000 0x00214000 0x001000>, /* ap 89 */ - <0x00015000 0x00215000 0x001000>, /* ap 90 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ - <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ - <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ - <0x00020000 0x00220000 0x001000>, /* ap 97 */ - <0x00021000 0x00221000 0x001000>, /* ap 98 */ - <0x00024000 0x00224000 0x001000>, /* ap 99 */ - <0x00025000 0x00225000 0x001000>, /* ap 100 */ - <0x00026000 0x00226000 0x001000>, /* ap 101 */ - <0x00027000 0x00227000 0x001000>, /* ap 102 */ - <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ - <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ - <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ - <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ - <0x00030000 0x00230000 0x001000>, /* ap 113 */ - <0x00031000 0x00231000 0x001000>, /* ap 114 */ - <0x00032000 0x00232000 0x001000>, /* ap 115 */ - <0x00033000 0x00233000 0x001000>, /* ap 116 */ - <0x00034000 0x00234000 0x001000>, /* ap 117 */ - <0x00035000 0x00235000 0x001000>, /* ap 118 */ - <0x00036000 0x00236000 0x001000>, /* ap 119 */ - <0x00037000 0x00237000 0x001000>, /* ap 120 */ - <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ - <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ - - target-module@0 { /* 0x4a200000, ap 77 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 85 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 87 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 43 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 97 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@24000 { /* 0x4a224000, ap 99 44.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - - target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2c000 0x1000>; - }; - - target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>; - }; - - target-module@30000 { /* 0x4a230000, ap 113 70.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - }; - - target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - }; - - target-module@34000 { /* 0x4a234000, ap 117 76.1 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - }; - - target-module@36000 { /* 0x4a236000, ap 119 62.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - }; -}; - -&l4_per1 { /* 0x48000000 */ - compatible = "ti,dra7-l4-per1", "simple-pm-bus"; - power-domains = <&prm_l4per>; - clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00055000 0x00055000 0x001000>, /* ap 13 */ - <0x00056000 0x00056000 0x001000>, /* ap 14 */ - <0x00057000 0x00057000 0x001000>, /* ap 15 */ - <0x00058000 0x00058000 0x001000>, /* ap 16 */ - <0x00059000 0x00059000 0x001000>, /* ap 17 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ - <0x00060000 0x00060000 0x001000>, /* ap 23 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ - <0x00070000 0x00070000 0x001000>, /* ap 30 */ - <0x00071000 0x00071000 0x001000>, /* ap 31 */ - <0x00072000 0x00072000 0x001000>, /* ap 32 */ - <0x00073000 0x00073000 0x001000>, /* ap 33 */ - <0x00061000 0x00061000 0x001000>, /* ap 34 */ - <0x00053000 0x00053000 0x001000>, /* ap 35 */ - <0x00054000 0x00054000 0x001000>, /* ap 36 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x001000>, /* ap 39 */ - <0x00079000 0x00079000 0x001000>, /* ap 40 */ - <0x00086000 0x00086000 0x001000>, /* ap 41 */ - <0x00087000 0x00087000 0x001000>, /* ap 42 */ - <0x00088000 0x00088000 0x001000>, /* ap 43 */ - <0x00089000 0x00089000 0x001000>, /* ap 44 */ - <0x00051000 0x00051000 0x001000>, /* ap 45 */ - <0x00052000 0x00052000 0x001000>, /* ap 46 */ - <0x00098000 0x00098000 0x001000>, /* ap 47 */ - <0x00099000 0x00099000 0x001000>, /* ap 48 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ - <0x00068000 0x00068000 0x001000>, /* ap 53 */ - <0x00069000 0x00069000 0x001000>, /* ap 54 */ - <0x00090000 0x00090000 0x002000>, /* ap 55 */ - <0x00092000 0x00092000 0x001000>, /* ap 56 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ - <0x00066000 0x00066000 0x001000>, /* ap 63 */ - <0x00067000 0x00067000 0x001000>, /* ap 64 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ - <0x00001400 0x00001400 0x000400>, /* ap 77 */ - <0x00001800 0x00001800 0x000400>, /* ap 78 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ - <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ - <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ - <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ - <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; - dma-names = "tx", "rx"; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 3e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x51000 0x4>, - <0x51010 0x4>, - <0x51114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - - gpio7: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@53000 { /* 0x48053000, ap 35 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53000 0x4>, - <0x53010 0x4>, - <0x53114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - - gpio8: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 23 32.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@66000 { /* 0x48066000, ap 63 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66050 0x4>, - <0x66054 0x4>, - <0x66058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - uart5: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; - dma-names = "tx", "rx"; - }; - }; - - target-module@68000 { /* 0x48068000, ap 53 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x68050 0x4>, - <0x68054 0x4>, - <0x68058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x1000>; - - uart6: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; - dma-names = "tx", "rx"; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; - dma-names = "tx", "rx"; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; - dma-names = "tx", "rx"; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; - dma-names = "tx", "rx"; - }; - }; - - target-module@70000 { /* 0x48070000, ap 30 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@72000 { /* 0x48072000, ap 32 2a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@78000 { /* 0x48078000, ap 39 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x78000 0x4>, - <0x78010 0x4>, - <0x78014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0xfc0>; /* device IO registers */ - interrupts = ; - status = "disabled"; - }; - }; - - target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7a000 0x8>, - <0x7a010 0x8>, - <0x7a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7a000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7c000 0x8>, - <0x7c010 0x8>, - <0x7c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x1000>; - - i2c5: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@86000 { /* 0x48086000, ap 41 5e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x86000 0x4>, - <0x86010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@88000 { /* 0x48088000, ap 43 66.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@90000 { /* 0x48090000, ap 55 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - ; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - target-module@98000 { /* 0x48098000, ap 47 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma_xbar 35>, - <&sdma_xbar 36>, - <&sdma_xbar 37>, - <&sdma_xbar 38>, - <&sdma_xbar 39>, - <&sdma_xbar 40>, - <&sdma_xbar 41>, - <&sdma_xbar 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - status = "disabled"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 43>, - <&sdma_xbar 44>, - <&sdma_xbar 45>, - <&sdma_xbar 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - pbias-supply = <&pbias_mmc_reg>; - max-frequency = <192000000>; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - }; - }; - - target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - des_target: target-module@a5000 { /* 0x480a5000 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa5030 0x4>, - <0xa5034 0x4>, - <0xa5038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa5000 0x00001000>; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ - max-frequency = <64000000>; - /* SDMA is not supported */ - sdhci-caps-mask = <0x0 0x400000>; - }; - }; - - target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xb2000 0x4>, - <0xb2014 0x4>, - <0xb2018 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - ti,no-reset-on-init; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - - hdqw1w: 1w@0 { - compatible = "ti,omap3-1w"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - max-frequency = <192000000>; - /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ - sdhci-caps-mask = <0x7 0x0>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - max-frequency = <192000000>; - /* SDMA is not supported */ - sdhci-caps-mask = <0x0 0x400000>; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_per2 { /* 0x48400000 */ - compatible = "ti,dra7-l4-per2", "simple-pm-bus"; - power-domains = <&prm_l4per>; - clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48400000 0x800>, - <0x48400800 0x800>, - <0x48401000 0x400>, - <0x48401400 0x400>, - <0x48401800 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ - <0x45800000 0x45800000 0x400000>, /* L3 data port */ - <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ - <0x46000000 0x46000000 0x400000>, /* L3 data port */ - <0x48436000 0x48436000 0x400000>, /* L3 data port */ - <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ - <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ - <0x48450000 0x48450000 0x400000>, /* L3 data port */ - <0x48454000 0x48454000 0x400000>; /* L3 data port */ - - segment@0 { /* 0x48400000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00084000 0x00084000 0x004000>, /* ap 3 */ - <0x00001400 0x00001400 0x000400>, /* ap 4 */ - <0x00001800 0x00001800 0x000400>, /* ap 5 */ - <0x00088000 0x00088000 0x001000>, /* ap 6 */ - <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ - <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ - <0x00060000 0x00060000 0x002000>, /* ap 9 */ - <0x00062000 0x00062000 0x001000>, /* ap 10 */ - <0x00064000 0x00064000 0x002000>, /* ap 11 */ - <0x00066000 0x00066000 0x001000>, /* ap 12 */ - <0x00068000 0x00068000 0x002000>, /* ap 13 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ - <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ - <0x00036000 0x00036000 0x001000>, /* ap 17 */ - <0x00037000 0x00037000 0x001000>, /* ap 18 */ - <0x00070000 0x00070000 0x002000>, /* ap 19 */ - <0x00072000 0x00072000 0x001000>, /* ap 20 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ - <0x00040000 0x00040000 0x001000>, /* ap 27 */ - <0x00041000 0x00041000 0x001000>, /* ap 28 */ - <0x00042000 0x00042000 0x001000>, /* ap 29 */ - <0x00043000 0x00043000 0x001000>, /* ap 30 */ - <0x00080000 0x00080000 0x002000>, /* ap 31 */ - <0x00082000 0x00082000 0x001000>, /* ap 32 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ - <0x00074000 0x00074000 0x002000>, /* ap 35 */ - <0x00076000 0x00076000 0x001000>, /* ap 36 */ - <0x00050000 0x00050000 0x001000>, /* ap 37 */ - <0x00051000 0x00051000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x002000>, /* ap 39 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ - <0x00054000 0x00054000 0x001000>, /* ap 41 */ - <0x00055000 0x00055000 0x001000>, /* ap 42 */ - <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ - <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ - <0x00020000 0x00020000 0x001000>, /* ap 47 */ - <0x00021000 0x00021000 0x001000>, /* ap 48 */ - <0x00022000 0x00022000 0x001000>, /* ap 49 */ - <0x00023000 0x00023000 0x001000>, /* ap 50 */ - <0x00024000 0x00024000 0x001000>, /* ap 51 */ - <0x00025000 0x00025000 0x001000>, /* ap 52 */ - <0x00046000 0x00046000 0x001000>, /* ap 53 */ - <0x00047000 0x00047000 0x001000>, /* ap 54 */ - <0x00048000 0x00048000 0x001000>, /* ap 55 */ - <0x00049000 0x00049000 0x001000>, /* ap 56 */ - <0x00058000 0x00058000 0x002000>, /* ap 57 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ - <0x45800000 0x45800000 0x400000>, /* L3 data port */ - <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ - <0x46000000 0x46000000 0x400000>, /* L3 data port */ - <0x48436000 0x48436000 0x400000>, /* L3 data port */ - <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ - <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ - <0x48450000 0x48450000 0x400000>, /* L3 data port */ - <0x48454000 0x48454000 0x400000>; /* L3 data port */ - - target-module@20000 { /* 0x48420000, ap 47 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart7: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@22000 { /* 0x48422000, ap 49 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x22050 0x4>, - <0x22054 0x4>, - <0x22058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - uart8: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x48424000, ap 51 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x24050 0x4>, - <0x24054 0x4>, - <0x24058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - uart9: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2c000 0x1000>; - }; - - target-module@36000 { /* 0x48436000, ap 17 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>; - }; - - atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x3c000 0x4>; - reg-names = "rev"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>; - - atl: atl@0 { - compatible = "ti,dra7-atl"; - reg = <0x0 0x3ff>; - ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, - <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - epwmss0: epwmss@0 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x0 0x30>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap0: pwm@100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm0: pwm@200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@40000 { /* 0x48440000, ap 27 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - epwmss1: epwmss@0 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x0 0x30>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap1: pwm@100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm1: pwm@200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@42000 { /* 0x48442000, ap 29 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x42000 0x4>, - <0x42004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - epwmss2: epwmss@0 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x0 0x30>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap2: pwm@100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm2: pwm@200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@46000 { /* 0x48446000, ap 53 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - }; - - target-module@48000 { /* 0x48448000, ap 55 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - }; - - target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - }; - - target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - }; - - target-module@50000 { /* 0x48450000, ap 37 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000 0x1000>; - }; - - target-module@54000 { /* 0x48454000, ap 41 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x54000 0x1000>; - }; - - target-module@58000 { /* 0x48458000, ap 57 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58000 0x2000>; - }; - - target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@60000 { /* 0x48460000, ap 9 0e.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x60000 0x4>, - <0x60004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x2000>, - <0x45800000 0x45800000 0x400000>; - - mcasp1: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x45800000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; - dma-names = "tx", "rx"; - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - }; - - target-module@64000 { /* 0x48464000, ap 11 1e.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x64000 0x4>, - <0x64004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x2000>, - <0x45c00000 0x45c00000 0x400000>; - - mcasp2: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x45c00000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - }; - - target-module@68000 { /* 0x48468000, ap 13 26.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x68000 0x4>, - <0x68004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x2000>, - <0x46000000 0x46000000 0x400000>; - - mcasp3: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x6c000 0x4>, - <0x6c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x2000>, - <0x48436000 0x48436000 0x400000>; - - mcasp4: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x48436000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@70000 { /* 0x48470000, ap 19 36.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x70000 0x4>, - <0x70004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x2000>, - <0x4843a000 0x4843a000 0x400000>; - - mcasp5: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x4843a000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@74000 { /* 0x48474000, ap 35 14.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x74000 0x4>, - <0x74004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x2000>, - <0x4844c000 0x4844c000 0x400000>; - - mcasp6: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x4844c000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@78000 { /* 0x48478000, ap 39 0c.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x78000 0x4>, - <0x78004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x2000>, - <0x48450000 0x48450000 0x400000>; - - mcasp7: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x48450000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x7c000 0x4>, - <0x7c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x2000>, - <0x48454000 0x48454000 0x400000>; - - mcasp8: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x48454000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48480000, ap 31 16.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x80020 0x4>; - reg-names = "rev"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x2000>; - - dcan2: can@0 { - compatible = "ti,dra7-d_can"; - reg = <0x0 0x2000>; - syscon-raminit = <&scm_conf 0x558 1>; - interrupts = ; - clocks = <&sys_clkin1>; - status = "disabled"; - }; - }; - - target-module@84000 { /* 0x48484000, ap 3 10.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x85200 0x4>, - <0x85208 0x4>, - <0x85204 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x84000 0x4000>; - /* - * Do not allow gating of cpsw clock as workaround - * for errata i877. Keeping internal clock disabled - * causes the device switching characteristics - * to degrade over time and eventually fail to meet - * the data manual delay time/skew specs. - */ - ti,no-idle; - - mac_sw: switch@0 { - compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; - reg = <0x0 0x4000>; - ranges = <0 0 0x4000>; - clocks = <&gmac_main_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - syscon = <&scm_conf>; - status = "disabled"; - - interrupts = , - , - , - ; - interrupt-names = "rx_thresh", "rx", "tx", "misc"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - label = "port1"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - }; - - cpsw_port2: port@2 { - reg = <2>; - label = "port2"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - - davinci_mdio_sw: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_main_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpts { - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "cpts"; - }; - }; - }; - }; -}; - -&l4_per3 { /* 0x48800000 */ - compatible = "ti,dra7-l4-per3", "simple-pm-bus"; - power-domains = <&prm_l4per>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48800000 0x800>, - <0x48800800 0x800>, - <0x48801000 0x400>, - <0x48801400 0x400>, - <0x48801800 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ - - segment@0 { /* 0x48800000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>, /* ap 3 */ - <0x00001800 0x00001800 0x000400>, /* ap 4 */ - <0x00020000 0x00020000 0x001000>, /* ap 5 */ - <0x00021000 0x00021000 0x001000>, /* ap 6 */ - <0x00022000 0x00022000 0x001000>, /* ap 7 */ - <0x00023000 0x00023000 0x001000>, /* ap 8 */ - <0x00024000 0x00024000 0x001000>, /* ap 9 */ - <0x00025000 0x00025000 0x001000>, /* ap 10 */ - <0x00026000 0x00026000 0x001000>, /* ap 11 */ - <0x00027000 0x00027000 0x001000>, /* ap 12 */ - <0x00028000 0x00028000 0x001000>, /* ap 13 */ - <0x00029000 0x00029000 0x001000>, /* ap 14 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ - <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ - <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ - <0x00170000 0x00170000 0x010000>, /* ap 21 */ - <0x00180000 0x00180000 0x001000>, /* ap 22 */ - <0x00190000 0x00190000 0x010000>, /* ap 23 */ - <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ - <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ - <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ - <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ - <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ - <0x00038000 0x00038000 0x001000>, /* ap 29 */ - <0x00039000 0x00039000 0x001000>, /* ap 30 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ - <0x00040000 0x00040000 0x001000>, /* ap 39 */ - <0x00041000 0x00041000 0x001000>, /* ap 40 */ - <0x00042000 0x00042000 0x001000>, /* ap 41 */ - <0x00043000 0x00043000 0x001000>, /* ap 42 */ - <0x00044000 0x00044000 0x001000>, /* ap 43 */ - <0x00045000 0x00045000 0x001000>, /* ap 44 */ - <0x00046000 0x00046000 0x001000>, /* ap 45 */ - <0x00047000 0x00047000 0x001000>, /* ap 46 */ - <0x00048000 0x00048000 0x001000>, /* ap 47 */ - <0x00049000 0x00049000 0x001000>, /* ap 48 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ - <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ - <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ - <0x00050000 0x00050000 0x001000>, /* ap 55 */ - <0x00051000 0x00051000 0x001000>, /* ap 56 */ - <0x00052000 0x00052000 0x001000>, /* ap 57 */ - <0x00053000 0x00053000 0x001000>, /* ap 58 */ - <0x00054000 0x00054000 0x001000>, /* ap 59 */ - <0x00055000 0x00055000 0x001000>, /* ap 60 */ - <0x00056000 0x00056000 0x001000>, /* ap 61 */ - <0x00057000 0x00057000 0x001000>, /* ap 62 */ - <0x00058000 0x00058000 0x001000>, /* ap 63 */ - <0x00059000 0x00059000 0x001000>, /* ap 64 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ - <0x00064000 0x00064000 0x001000>, /* ap 67 */ - <0x00065000 0x00065000 0x001000>, /* ap 68 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ - <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ - <0x00060000 0x00060000 0x001000>, /* ap 71 */ - <0x00061000 0x00061000 0x001000>, /* ap 72 */ - <0x00062000 0x00062000 0x001000>, /* ap 73 */ - <0x00063000 0x00063000 0x001000>, /* ap 74 */ - <0x00140000 0x00140000 0x020000>, /* ap 75 */ - <0x00160000 0x00160000 0x001000>, /* ap 76 */ - <0x00016000 0x00016000 0x001000>, /* ap 77 */ - <0x00017000 0x00017000 0x001000>, /* ap 78 */ - <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ - <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ - <0x00004000 0x00004000 0x001000>, /* ap 81 */ - <0x00005000 0x00005000 0x001000>, /* ap 82 */ - <0x00080000 0x00080000 0x020000>, /* ap 83 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ - <0x00100000 0x00100000 0x020000>, /* ap 85 */ - <0x00120000 0x00120000 0x001000>, /* ap 86 */ - <0x00010000 0x00010000 0x001000>, /* ap 87 */ - <0x00011000 0x00011000 0x001000>, /* ap 88 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ - <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ - <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ - <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ - <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ - <0x00002000 0x00002000 0x001000>, /* ap 95 */ - <0x00003000 0x00003000 0x001000>; /* ap 96 */ - - target-module@2000 { /* 0x48802000, ap 95 7c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - mailbox13: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@4000 { /* 0x48804000, ap 81 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@a000 { /* 0x4880a000, ap 89 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@10000 { /* 0x48810000, ap 87 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@16000 { /* 0x48816000, ap 77 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x48820000, ap 5 08.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x20000 0x4>, - <0x20010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@22000 { /* 0x48822000, ap 7 24.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x22000 0x4>, - <0x22010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@24000 { /* 0x48824000, ap 9 26.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x24000 0x4>, - <0x24010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@26000 { /* 0x48826000, ap 11 0c.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x26000 0x4>, - <0x26010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@28000 { /* 0x48828000, ap 13 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x28000 0x4>, - <0x28010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - - timer13: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x2a000 0x4>, - <0x2a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - - timer14: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x2c000 0x4>, - <0x2c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2c000 0x1000>; - - timer15: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>; - - timer16: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x38074 0x4>, - <0x38078 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ - clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>; - - rtc: rtc@0 { - compatible = "ti,am3352-rtc"; - reg = <0x0 0x100>; - interrupts = , - ; - clocks = <&sys_32k_ck>; - }; - }; - - target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>; - - mailbox2: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>; - - mailbox3: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - mailbox4: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@40000 { /* 0x48840000, ap 39 64.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - mailbox5: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@42000 { /* 0x48842000, ap 41 4e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x42000 0x4>, - <0x42010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - mailbox6: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@44000 { /* 0x48844000, ap 43 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x44000 0x4>, - <0x44010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - - mailbox7: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@46000 { /* 0x48846000, ap 45 48.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x46000 0x4>, - <0x46010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - - mailbox8: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@48000 { /* 0x48848000, ap 47 36.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - }; - - target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - }; - - target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - }; - - target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4e000 0x1000>; - }; - - target-module@50000 { /* 0x48850000, ap 55 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000 0x1000>; - }; - - target-module@52000 { /* 0x48852000, ap 57 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x52000 0x1000>; - }; - - target-module@54000 { /* 0x48854000, ap 59 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x54000 0x1000>; - }; - - target-module@56000 { /* 0x48856000, ap 61 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - }; - - target-module@58000 { /* 0x48858000, ap 63 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58000 0x1000>; - }; - - target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5a000 0x1000>; - }; - - target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5c000 0x1000>; - }; - - target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5e000 0x4>, - <0x5e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x1000>; - - mailbox9: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@60000 { /* 0x48860000, ap 71 4a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x60000 0x4>, - <0x60010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - mailbox10: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@62000 { /* 0x48862000, ap 73 74.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x62000 0x4>, - <0x62010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - mailbox11: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@64000 { /* 0x48864000, ap 67 52.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x64000 0x4>, - <0x64010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - mailbox12: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48880000, ap 83 0e.1 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x80000 0x4>, - <0x80010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x20000>; - - omap_dwc3_1: omap_dwc3_1@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - - usb1: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc0000 0x4>, - <0xc0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x20000>; - - omap_dwc3_2: omap_dwc3_2@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - - usb2: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - snps,dis_metastability_quirk; - }; - }; - }; - - usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x100000 0x4>, - <0x100010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x20000>; - - omap_dwc3_3: omap_dwc3_3@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - status = "disabled"; - - usb3: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@170000 { /* 0x48970000, ap 21 0a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x170010 0x4>; - reg-names = "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x170000 0x10000>; - status = "disabled"; - }; - - target-module@190000 { /* 0x48990000, ap 23 2e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x190010 0x4>; - reg-names = "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x190000 0x10000>; - status = "disabled"; - }; - - target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x1b0000 0x4>, - <0x1b0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b0000 0x10000>; - status = "disabled"; - }; - - target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x1d0010 0x4>; - reg-names = "sysc"; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - , - ; - power-domains = <&prm_vpe>; - clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1d0000 0x10000>; - - vpe: vpe@0 { - compatible = "ti,dra7-vpe"; - reg = <0x0000 0x120>, - <0x0700 0x80>, - <0x5700 0x18>, - <0xd000 0x400>; - reg-names = "vpe_top", - "sc", - "csc", - "vpdma"; - interrupts = ; - }; - }; - }; -}; - -&l4_wkup { /* 0x4ae00000 */ - compatible = "ti,dra7-l4-wkup", "simple-pm-bus"; - power-domains = <&prm_wkupaon>; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4ae00000 0x800>, - <0x4ae00800 0x800>, - <0x4ae01000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ - <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ - <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ - <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ - - segment@0 { /* 0x4ae00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 15 */ - <0x00005000 0x00005000 0x001000>, /* ap 16 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ - - target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,dra7-prm", "simple-bus"; - reg = <0 0x3000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x3000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - scm_wkup: scm_conf@0 { - compatible = "syscon"; - reg = <0 0x1000>; - }; - }; - }; - - segment@10000 { /* 0x4ae10000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ - - target-module@0 { /* 0x4ae10000, ap 5 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, - <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x8000 0x4>, - <0x8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - }; - - segment@20000 { /* 0x4ae20000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 19 */ - <0x00001000 0x00021000 0x001000>, /* ap 20 */ - <0x00002000 0x00022000 0x001000>, /* ap 21 */ - <0x00003000 0x00023000 0x001000>, /* ap 22 */ - <0x00007000 0x00027000 0x000400>, /* ap 23 */ - <0x00008000 0x00028000 0x000800>, /* ap 24 */ - <0x00009000 0x00029000 0x000100>, /* ap 25 */ - <0x00008800 0x00028800 0x000200>, /* ap 26 */ - <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ - <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ - <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ - <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ - - target-module@0 { /* 0x4ae20000, ap 19 08.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - timer12: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - interrupts = ; - ti,timer-alwon; - ti,timer-secure; - }; - }; - - target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00002800 0x00008800 0x00000200>, - <0x00002a00 0x00008a00 0x00000100>, - <0x00003000 0x00009000 0x00000100>; - }; - - target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xb050 0x4>, - <0xb054 0x4>, - <0xb058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb000 0x1000>; - - uart10: serial@0 { - compatible = "ti,dra742-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf000 0x1000>; - }; - }; - - segment@30000 { /* 0x4ae30000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ - <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ - <0x00000000 0x00030000 0x001000>, /* ap 33 */ - <0x00001000 0x00031000 0x001000>, /* ap 34 */ - <0x00002000 0x00032000 0x001000>, /* ap 35 */ - <0x00003000 0x00033000 0x001000>, /* ap 36 */ - <0x00004000 0x00034000 0x001000>, /* ap 37 */ - <0x00005000 0x00035000 0x001000>, /* ap 38 */ - <0x00006000 0x00036000 0x001000>, /* ap 39 */ - <0x00007000 0x00037000 0x001000>, /* ap 40 */ - <0x00008000 0x00038000 0x001000>, /* ap 41 */ - <0x00009000 0x00039000 0x001000>, /* ap 42 */ - <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ - - target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1000 0x1000>; - }; - - target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - - target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - }; - - target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - }; - - target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9000 0x1000>; - }; - - target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc020 0x4>; - reg-names = "rev"; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x2000>; - - dcan1: can@0 { - compatible = "ti,dra7-d_can"; - reg = <0x0 0x2000>; - syscon-raminit = <&scm_conf 0x558 0>; - interrupts = ; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; - status = "disabled"; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi deleted file mode 100644 index cb1a682c26cd..000000000000 --- a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * MMC IOdelay values for TI's DRA7xx SoCs. - * Copyright (C) 2018 Texas Instruments - * Author: Kishon Vijay Abraham I - */ - -&dra7_pmx_core { - mmc1_pins_default_no_clk_pu: mmc1-default-no-clk-pu-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi deleted file mode 100644 index 97ce0c4f1df7..000000000000 --- a/arch/arm/boot/dts/dra7.dtsi +++ /dev/null @@ -1,1358 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include -#include -#include -#include -#include - -#define MAX_SOURCES 400 - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,dra7xx"; - interrupt-parent = <&crossbar_mpu>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - serial8 = &uart9; - serial9 = &uart10; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - d_can0 = &dcan1; - d_can1 = &dcan2; - spi0 = &qspi; - }; - - timer { - compatible = "arm,armv7-timer"; - status = "disabled"; /* See ARM architected timer wrap erratum i940 */ - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x48211000 0x0 0x1000>, - <0x0 0x48212000 0x0 0x2000>, - <0x0 0x48214000 0x0 0x2000>, - <0x0 0x48216000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x48281000 0x0 0x1000>; - interrupt-parent = <&gic>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - - vbb-supply = <&abb_mpu>; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_wkup>; - - opp_nom-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1060000 850000 1150000>, - <1060000 850000 1150000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp_od-1176000000 { - opp-hz = /bits/ 64 <1176000000>; - opp-microvolt = <1160000 885000 1160000>, - <1160000 885000 1160000>; - - opp-supported-hw = <0xFF 0x02>; - }; - - opp_high@1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1210000 950000 1250000>, - <1210000 950000 1250000>; - opp-supported-hw = <0xFF 0x04>; - }; - }; - - /* - * XXX: Use a flat representation of the SOC interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp: ocp { - compatible = "simple-pm-bus"; - power-domains = <&prm_core>; - clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>, - <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; - - l3-noc@44000000 { - compatible = "ti,dra7-l3-noc"; - reg = <0x44000000 0x1000>, - <0x45000000 0x1000>; - interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - l4_cfg: interconnect@4a000000 { - }; - l4_wkup: interconnect@4ae00000 { - }; - l4_per1: interconnect@48000000 { - }; - - target-module@48210000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - power-domains = <&prm_mpu>; - clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48210000 0x1f0000>; - - mpu { - compatible = "ti,omap5-mpu"; - }; - }; - - l4_per2: interconnect@48400000 { - }; - l4_per3: interconnect@48800000 { - }; - - /* - * Register access seems to have complex dependencies and also - * seems to need an enabled phy. See the TRM chapter for "Table - * 26-678. Main Sequence PCIe Controller Global Initialization" - * and also dra7xx_pcie_probe(). - */ - axi0: target-module@51000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - power-domains = <&prm_l3init>; - resets = <&prm_l3init 0>; - reset-names = "rstctrl"; - clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>; - clock-names = "fck", "phy-clk", "phy-clk-div"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000>, - <0x20000000 0x20000000 0x10000000>; - dma-ranges; - /** - * To enable PCI endpoint mode, disable the pcie1_rc - * node and enable pcie1_ep mode. - */ - pcie1_rc: pcie@51000000 { - reg = <0x51000000 0x2000>, - <0x51002000 0x14c>, - <0x20001000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 232 0x4>, <0 233 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>, - <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>; - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - num-lanes = <1>; - linux,pci-domain = <0>; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 1>, - <0 0 0 2 &pcie1_intc 2>, - <0 0 0 3 &pcie1_intc 3>, - <0 0 0 4 &pcie1_intc 4>; - ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; - status = "disabled"; - pcie1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1_ep: pcie_ep@51000000 { - reg = <0x51000000 0x28>, - <0x51002000 0x14c>, - <0x51001000 0x28>, - <0x20001000 0x10000000>; - reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; - interrupts = <0 232 0x4>; - num-lanes = <1>; - num-ib-windows = <4>; - num-ob-windows = <16>; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; - ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; - status = "disabled"; - }; - }; - - /* - * Register access seems to have complex dependencies and also - * seems to need an enabled phy. See the TRM chapter for "Table - * 26-678. Main Sequence PCIe Controller Global Initialization" - * and also dra7xx_pcie_probe(). - */ - axi1: target-module@51800000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>; - clock-names = "fck", "phy-clk", "phy-clk-div"; - power-domains = <&prm_l3init>; - resets = <&prm_l3init 1>; - reset-names = "rstctrl"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51800000 0x51800000 0x3000>, - <0x30000000 0x30000000 0x10000000>; - dma-ranges; - status = "disabled"; - pcie2_rc: pcie@51800000 { - reg = <0x51800000 0x2000>, - <0x51802000 0x14c>, - <0x30001000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 355 0x4>, <0 356 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, - <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - num-lanes = <1>; - linux,pci-domain = <1>; - phys = <&pcie2_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 1>, - <0 0 0 2 &pcie2_intc 2>, - <0 0 0 3 &pcie2_intc 3>, - <0 0 0 4 &pcie2_intc 4>; - ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; - pcie2_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - ocmcram1: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x80000>; - ranges = <0x0 0x40300000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - /* - * This is a placeholder for an optional reserved - * region for use by secure software. The size - * of this region is not known until runtime so it - * is set as zero to either be updated to reserve - * space or left unchanged to leave all SRAM for use. - * On HS parts that that require the reserved region - * either the bootloader can update the size to - * the required amount or the node can be overridden - * from the board dts file for the secure platform. - */ - sram-hs@0 { - compatible = "ti,secure-ram"; - reg = <0x0 0x0>; - }; - }; - - /* - * NOTE: ocmcram2 and ocmcram3 are not available on all - * DRA7xx and AM57xx variants. Confirm availability in - * the data manual for the exact part number in use - * before enabling these nodes in the board dts file. - */ - ocmcram2: ocmcram@40400000 { - status = "disabled"; - compatible = "mmio-sram"; - reg = <0x40400000 0x100000>; - ranges = <0x0 0x40400000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - ocmcram3: ocmcram@40500000 { - status = "disabled"; - compatible = "mmio-sram"; - reg = <0x40500000 0x100000>; - ranges = <0x0 0x40500000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c - 0x4a002564 0x8 - 0x4a002574 0x50>; - compatible = "ti,dra752-bandgap"; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - dsp1_system: dsp_system@40d00000 { - compatible = "syscon"; - reg = <0x40d00000 0x100>; - }; - - dra7_iodelay_core: padconf@4844a000 { - compatible = "ti,dra7-iodelay"; - reg = <0x4844a000 0x0d1c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - }; - - target-module@43300000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x43300000 0x4>, - <0x43300010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x43300000 0x100000>; - - edma: dma@0 { - compatible = "ti,edma3-tpcc"; - reg = <0 0x100000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <20 21>; - * for example. Note that these channels need to be - * masked in the xbar as well. - */ - }; - }; - - target-module@43400000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x43400000 0x4>, - <0x43400010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x43400000 0x100000>; - - edma_tptc0: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@43500000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x43500000 0x4>, - <0x43500010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x43500000 0x100000>; - - edma_tptc1: dma@0 { - compatible = "ti,edma3-tptc"; - reg = <0 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - }; - - target-module@4e000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4e000000 0x4>, - <0x4e000010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - ranges = <0x0 0x4e000000 0x2000000>; - #size-cells = <1>; - #address-cells = <1>; - - dmm@0 { - compatible = "ti,omap5-dmm"; - reg = <0 0x800>; - interrupts = ; - }; - }; - - ipu1: ipu@58820000 { - compatible = "ti,dra7-ipu"; - reg = <0x58820000 0x10000>; - reg-names = "l2ram"; - iommus = <&mmu_ipu1>; - status = "disabled"; - resets = <&prm_ipu 0>, <&prm_ipu 1>; - clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; - firmware-name = "dra7-ipu1-fw.xem4"; - }; - - ipu2: ipu@55020000 { - compatible = "ti,dra7-ipu"; - reg = <0x55020000 0x10000>; - reg-names = "l2ram"; - iommus = <&mmu_ipu2>; - status = "disabled"; - resets = <&prm_core 0>, <&prm_core 1>; - clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; - firmware-name = "dra7-ipu2-fw.xem4"; - }; - - dsp1: dsp@40800000 { - compatible = "ti,dra7-dsp"; - reg = <0x40800000 0x48000>, - <0x40e00000 0x8000>, - <0x40f00000 0x8000>; - reg-names = "l2ram", "l1pram", "l1dram"; - ti,bootreg = <&scm_conf 0x55c 10>; - iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; - status = "disabled"; - resets = <&prm_dsp1 0>; - clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; - firmware-name = "dra7-dsp1-fw.xe66"; - }; - - target-module@40d01000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x40d01000 0x4>, - <0x40d01010 0x4>, - <0x40d01014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp1 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x40d01000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu0_dsp1: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x0>; - }; - }; - - target-module@40d02000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x40d02000 0x4>, - <0x40d02010 0x4>, - <0x40d02014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp1 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x40d02000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu1_dsp1: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x1>; - }; - }; - - target-module@58882000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58882000 0x4>, - <0x58882010 0x4>, - <0x58882014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_ipu 2>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58882000 0x100>; - - mmu_ipu1: mmu@0 { - compatible = "ti,dra7-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - }; - - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55082000 0x100>; - - mmu_ipu2: mmu@0 { - compatible = "ti,dra7-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v3"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, - <0x4ae06014 0x4>, <0x4a003b20 0xc>, - <0x4ae0c158 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1160000 0 0x4 0 0x02000000 0x01F00000 - 1210000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_ivahd: regulator-abb-ivahd { - compatible = "ti,abb-v3"; - regulator-name = "abb_ivahd"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, - <0x4ae06010 0x4>, <0x4a0025cc 0xc>, - <0x4a002470 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x40000000>; - /* LDOVBBIVA_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBIVA_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1055000 0 0x0 0 0x02000000 0x01F00000 - 1150000 0 0x4 0 0x02000000 0x01F00000 - 1250000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_dspeve: regulator-abb-dspeve { - compatible = "ti,abb-v3"; - regulator-name = "abb_dspeve"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, - <0x4ae06010 0x4>, <0x4a0025e0 0xc>, - <0x4a00246c 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x20000000>; - /* LDOVBBDSPEVE_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBDSPEVE_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1055000 0 0x0 0 0x02000000 0x01F00000 - 1150000 0 0x4 0 0x02000000 0x01F00000 - 1250000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_gpu: regulator-abb-gpu { - compatible = "ti,abb-v3"; - regulator-name = "abb_gpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, - <0x4ae06010 0x4>, <0x4a003b08 0xc>, - <0x4ae0c154 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x10000000>; - /* LDOVBBGPU_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBGPU_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1090000 0 0x0 0 0x02000000 0x01F00000 - 1210000 0 0x4 0 0x02000000 0x01F00000 - 1280000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - target-module@4b300000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4b300000 0x4>, - <0x4b300010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b300000 0x1000>, - <0x5c000000 0x5c000000 0x4000000>; - - qspi: spi@0 { - compatible = "ti,dra7xxx-qspi"; - reg = <0 0x100>, - <0x5c000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - syscon-chipselects = <&scm_conf 0x558>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; - clock-names = "fck"; - num-cs = <4>; - interrupts = ; - status = "disabled"; - }; - }; - - /* OCP2SCP1 */ - /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - - target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000000 4>, - <0x50000010 4>, - <0x50000014 4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ - <0x00000000 0x00000000 0x40000000>; /* data */ - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; - dmas = <&edma_xbar 4 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - }; - - crossbar_mpu: crossbar@4a002a48 { - compatible = "ti,irq-crossbar"; - reg = <0x4a002a48 0x130>; - interrupt-controller; - interrupt-parent = <&wakeupgen>; - #interrupt-cells = <3>; - ti,max-irqs = <160>; - ti,max-crossbar-sources = ; - ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132>; - ti,irqs-skip = <10 133 139 140>; - ti,irqs-safe-map = <0>; - }; - - target-module@58000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58000000 4>, - <0x58000014 4>; - reg-names = "rev", "syss"; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; - clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x58000000 0x800000>; - - dss: dss@0 { - compatible = "ti,dra7-dss"; - /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ - /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ - status = "disabled"; - /* CTRL_CORE_DSS_PLL_CONTROL */ - syscon-pll-ctrl = <&scm_conf 0x538>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800000>; - - target-module@1000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x1000 0x4>, - <0x1010 0x4>, - <0x1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-midle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x1000>; - - dispc@0 { - compatible = "ti,dra7-dispc"; - reg = <0 0x1000>; - interrupts = ; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - /* CTRL_CORE_SMA_SW_1 */ - syscon-pol = <&scm_conf 0x534>; - }; - }; - - target-module@40000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; - clock-names = "fck", "dss_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000 0x40000>; - - hdmi: encoder@0 { - compatible = "ti,dra7-hdmi"; - reg = <0 0x200>, - <0x200 0x80>, - <0x300 0x80>, - <0x20000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma_xbar 76>; - dma-names = "audio_tx"; - }; - }; - }; - }; - - target-module@59000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x59000020 0x4>; - reg-names = "rev"; - clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000000 0x1000>; - - bb2d: gpu@0 { - compatible = "vivante,gc"; - reg = <0x0 0x700>; - interrupts = ; - clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; - clock-names = "core"; - }; - }; - - aes1_target: target-module@4b500000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b500080 0x4>, - <0x4b500084 0x4>, - <0x4b500088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b500000 0x1000>; - - aes1: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - aes2_target: target-module@4b700000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b700080 0x4>, - <0x4b700084 0x4>, - <0x4b700088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b700000 0x1000>; - - aes2: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - sham1_target: target-module@4b101000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x4b101100 0x4>, - <0x4b101110 0x4>, - <0x4b101114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b101000 0x1000>; - - sham1: sham@0 { - compatible = "ti,omap5-sham"; - reg = <0 0x300>; - interrupts = ; - dmas = <&edma_xbar 119 0>; - dma-names = "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - sham2_target: target-module@42701000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x42701100 0x4>, - <0x42701110 0x4>, - <0x42701114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42701000 0x1000>; - - sham2: sham@0 { - compatible = "ti,omap5-sham"; - reg = <0 0x300>; - interrupts = ; - dmas = <&edma_xbar 165 0>; - dma-names = "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - iva_hd_target: target-module@5a000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5a05a400 0x4>, - <0x5a05a410 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - power-domains = <&prm_iva>; - resets = <&prm_iva 2>; - reset-names = "rstctrl"; - clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5a000000 0x5a000000 0x1000000>, - <0x5b000000 0x5b000000 0x1000000>; - - iva { - compatible = "ti,ivahd"; - }; - }; - - opp_supply_mpu: opp-supply@4a003b20 { - compatible = "ti,omap5-opp-supply"; - reg = <0x4a003b20 0xc>; - ti,efuse-settings = < - /* uV offset */ - 1060000 0x0 - 1160000 0x4 - 1210000 0x8 - >; - ti,absolute-max-voltage-uv = <1500000>; - }; - - }; - - thermal_zones: thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - #include "dra7-dspeve-thermal.dtsi" - #include "dra7-iva-thermal.dtsi" - }; - -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ - coefficients = <0 2000>; -}; - -&gpu_thermal { - coefficients = <0 2000>; -}; - -&core_thermal { - coefficients = <0 2000>; -}; - -&dspeve_thermal { - coefficients = <0 2000>; -}; - -&iva_thermal { - coefficients = <0 2000>; -}; - -&cpu_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&core_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&gpu_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&dspeve_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&iva_crit { - temperature = <120000>; /* milli Celsius */ -}; - -#include "dra7-l4.dtsi" -#include "dra7xx-clocks.dtsi" - -&prm { - prm_mpu: prm@300 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x300 0x100>; - #power-domain-cells = <0>; - }; - - prm_dsp1: prm@400 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_ipu: prm@500 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x500 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_coreaon: prm@628 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x628 0xd8>; - #power-domain-cells = <0>; - }; - - prm_core: prm@700 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_iva: prm@f00 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0xf00 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_cam: prm@1000 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1000 0x100>; - #power-domain-cells = <0>; - }; - - prm_dss: prm@1100 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1100 0x100>; - #power-domain-cells = <0>; - }; - - prm_gpu: prm@1200 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #power-domain-cells = <0>; - }; - - prm_l3init: prm@1300 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1300 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_l4per: prm@1400 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1400 0x100>; - #power-domain-cells = <0>; - }; - - prm_custefuse: prm@1600 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1600 0x100>; - #power-domain-cells = <0>; - }; - - prm_wkupaon: prm@1724 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1724 0x100>; - #power-domain-cells = <0>; - }; - - prm_dsp2: prm@1b00 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b00 0x40>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_eve1: prm@1b40 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b40 0x40>; - #power-domain-cells = <0>; - }; - - prm_eve2: prm@1b80 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b80 0x40>; - #power-domain-cells = <0>; - }; - - prm_eve3: prm@1bc0 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1bc0 0x40>; - #power-domain-cells = <0>; - }; - - prm_eve4: prm@1c00 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c00 0x60>; - #power-domain-cells = <0>; - }; - - prm_rtc: prm@1c60 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c60 0x20>; - #power-domain-cells = <0>; - }; - - prm_vpe: prm@1c80 { - compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c80 0x80>; - #power-domain-cells = <0>; - }; -}; - -/* Preferred always-on timer for clockevent */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; - assigned-clock-parents = <&sys_32k_ck>; - }; -}; - -/* Local timers, see ARM architected timer wrap erratum i940 */ -&timer15_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; - assigned-clock-parents = <&timer_sys_clk_div>; - }; -}; - -&timer16_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; - assigned-clock-parents = <&timer_sys_clk_div>; - }; -}; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts deleted file mode 100644 index a64364443031..000000000000 --- a/arch/arm/boot/dts/dra71-evm.dts +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "dra71x.dtsi" -#include "dra7-mmc-iodelay.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -#include - -/ { - compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; - model = "TI DRA718 EVM"; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - }; - - vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { - compatible = "regulator-gpio"; - - regulator-name = "vddshv8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&evm_5v0>; - - gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&lp8732_buck0_reg>; - regulator-always-on; - regulator-boot-on; - }; - - poweroff: gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; - input; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - lp8733: lp8733@60 { - compatible = "ti,lp8733"; - reg = <0x60>; - - buck0-in-supply =<&vsys_3v3>; - buck1-in-supply =<&vsys_3v3>; - ldo0-in-supply =<&evm_5v0>; - ldo1-in-supply =<&evm_5v0>; - - lp8733_regulators: regulators { - lp8733_buck0_reg: buck0 { - /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ - regulator-name = "lp8733-buck0"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - lp8733_buck1_reg: buck1 { - /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ - regulator-name = "lp8733-buck1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8733_ldo0_reg: ldo0 { - /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ - regulator-name = "lp8733-ldo0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8733_ldo1_reg: ldo1 { - /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ - regulator-name = "lp8733-ldo1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - lp8732: lp8732@61 { - compatible = "ti,lp8732"; - reg = <0x61>; - - buck0-in-supply =<&vsys_3v3>; - buck1-in-supply =<&vsys_3v3>; - ldo0-in-supply =<&vsys_3v3>; - ldo1-in-supply =<&vsys_3v3>; - - lp8732_regulators: regulators { - lp8732_buck0_reg: buck0 { - /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ - regulator-name = "lp8732-buck0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - lp8732_buck1_reg: buck1 { - /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ - regulator-name = "lp8732-buck1"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8732_ldo0_reg: ldo0 { - /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ - regulator-name = "lp8732-ldo0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8732_ldo1_reg: ldo1 { - /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ - regulator-name = "lp8732-ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&pcf_lcd { - interrupt-parent = <&gpio7>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio7>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; -}; - -&pcf_hdmi { - hdmi-i2c-disable-hog { - /* - * PM_OEn to High: Disable routing I2C3 to PM_I2C - * With this PM_SEL(p3) should not matter - */ - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-high; - line-name = "pm_oe_n"; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; - vqmmc-supply = <&vpo_sd_1v8_3v3>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; - vmmc-supply = <&evm_1v8_sw>; - vqmmc-supply = <&evm_1v8_sw>; -}; - -&mac_sw { - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, - <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ - <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <&dp83867_0>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <&dp83867_1>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -/* No Sata on this device */ -&sata_phy { - status = "disabled"; -}; - -&sata { - status = "disabled"; -}; - -/* No RTC on this device */ -&rtc { - status = "disabled"; -}; - -&usb2_phy1 { - phy-supply = <&lp8733_ldo1_reg>; -}; - -&usb2_phy2 { - phy-supply = <&lp8733_ldo1_reg>; -}; - -&dss { - /* Supplied by VDA_1V8_PLL */ - vdda_video-supply = <&lp8732_ldo0_reg>; -}; - -&hdmi { - /* Supplied by VDA_1V8_PHY */ - vdda_video-supply = <&lp8732_ldo1_reg>; -}; - -&extcon_usb1 { - vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; -}; - -&extcon_usb2 { - vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/dra71x.dtsi deleted file mode 100644 index 9c270d8f75d5..000000000000 --- a/arch/arm/boot/dts/dra71x.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "dra72-evm-common.dtsi" - -&rtctarget { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi deleted file mode 100644 index 31ab0c60ca75..000000000000 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ /dev/null @@ -1,593 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "dra72x.dtsi" -#include "dra7-ipu-dsp-common.dtsi" -#include -#include - -/ { - compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; - - aliases { - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart1; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - evm_5v0: fixedregulator-evm5v0 { - /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ - /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ - compatible = "regulator-fixed"; - regulator-name = "evm_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_3v6: fixedregulator-evm_3v6 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v6"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - vin-supply = <&evm_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ - /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_3v3_sw: fixedregulator-evm_3v3 { - /* TPS22965DSG */ - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3_sw>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_3v3_sw>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; -}; - -&dra7_pmx_core { - dcan1_pins_default: dcan1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1-sleep-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - pcf_lcd: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_gpio_21: gpio@21 { - compatible = "nxp,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3_sw>; - IOVDD-supply = <&evm_3v3_sw>; - DRVDD-supply = <&evm_3v3_sw>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { - compatible = "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - - hdmi-audio-hog { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * For the existing IOdelay configuration via U-Boot we don't - * support NAND on dra72-evm. Keep it disabled. Enabling it - * requires a different configuration by U-Boot. - */ - status = "disabled"; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "otg"; - extcon = <&extcon_usb1>; -}; - -&usb2 { - dr_mode = "host"; - extcon = <&extcon_usb2>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&evm_3v3_sd>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - max-frequency = <192000000>; -}; - -&mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - bus-width = <8>; - non-removable; - max-frequency = <192000000>; -}; - -&mmc4 { - status = "okay"; - vmmc-supply = <&evm_3v6>; - vqmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "hs", "sdr12", "sdr25"; - pinctrl-0 = <&mmc4_pins_default>; - pinctrl-1 = <&mmc4_pins_default>; - pinctrl-2 = <&mmc4_pins_default>; - pinctrl-3 = <&mmc4_pins_default>; - #address-cells = <1>; - #size-cells = <0>; - wifi@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - flash@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x00010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&atl { - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = ; - aws = ; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&pcie1_rc { - status = "okay"; -}; - -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts deleted file mode 100644 index f242b937f88c..000000000000 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include "dra72-evm-common.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -#include - -/ { - model = "TI DRA722 Rev C EVM"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_cma_pool: ipu2_cma@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_cma_pool: dsp1_cma@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_cma_pool: ipu1_cma@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&smps4_reg>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c1 { - tps65917: tps65917@58 { - reg = <0x58>; - - interrupts = ; /* IRQ_SYS_1N */ - }; -}; - -#include "dra72-evm-tps65917.dtsi" - -&ldo2_reg { - /* LDO2_OUT --> VDDA_1V8_PHY2 */ - regulator-always-on; - regulator-boot-on; -}; - -&hdmi { - vdda-supply = <&ldo2_reg>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; -}; - -&mac_sw { - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, - <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ - <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <&dp83867_0>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <&dp83867_1>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,dp83867-rxctrl-strap-quirk; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; - vmmc-supply = <&evm_1v8_sw>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_cma_pool>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_cma_pool>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_cma_pool>; -}; diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi deleted file mode 100644 index 7b433f549239..000000000000 --- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf - */ - -&tps65917 { - compatible = "ti,tps65917"; - - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - smps1-in-supply = <&vsys_3v3>; - smps2-in-supply = <&vsys_3v3>; - smps3-in-supply = <&vsys_3v3>; - smps4-in-supply = <&vsys_3v3>; - smps5-in-supply = <&vsys_3v3>; - ldo1-in-supply = <&vsys_3v3>; - ldo2-in-supply = <&vsys_3v3>; - ldo3-in-supply = <&vsys_3v3>; - ldo4-in-supply = <&evm_5v0>; - ldo5-in-supply = <&vsys_3v3>; - - tps65917_regulators: regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-bypass; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&dss { - vdda_video-supply = <&ldo5_reg>; -}; - -&mmc1 { - vqmmc-supply = <&ldo1_reg>; -}; - -&cpu0 { - vdd-supply = <&smps1_reg>; -}; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts deleted file mode 100644 index 5f62f92eb96c..000000000000 --- a/arch/arm/boot/dts/dra72-evm.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include "dra72-evm-common.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -/ { - model = "TI DRA722"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_memory_region: ipu2-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_memory_region: dsp1-memory@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_memory_region: ipu1-memory@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&smps4_reg>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c1 { - tps65917: tps65917@58 { - reg = <0x58>; - - interrupts = ; /* IRQ_SYS_1N */ - }; -}; - -#include "dra72-evm-tps65917.dtsi" - -&hdmi { - vdda-supply = <&ldo3_reg>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; -}; - -&mac_sw { - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&davinci_mdio_sw { - ethphy0: ethernet-phy@3 { - reg = <3>; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50_rev10>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev10>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; - vmmc-supply = <&evm_1v8_sw>; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_memory_region>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_memory_region>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_memory_region>; -}; diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi deleted file mode 100644 index d006f1dfdeb5..000000000000 --- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +++ /dev/null @@ -1,353 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. - * - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * Rules for modifying this file: - * a) Update of this file should typically correspond to a datamanual revision. - * Datamanual revision that was used should be updated in comment below. - * If there is no update to datamanual, do not update the values. If you - * need to use values different from that recommended by the datamanual - * for your design, then you should consider adding values to the device- - * -tree file for your board directly. - * b) We keep the mode names as close to the datamanual as possible. So - * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, - * we follow that in code too. - * c) If the values change between multiple revisions of silicon, we add - * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, - * 'rev20' for PG 2.0 and so on. - * d) The node name and node label should be the exact same string. This is - * to curb naming creativity and achieve consistency. - * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and - * 'dra72_' tag to entries. Both the new and old entries should gain a tag. - * - * Datamanual Revisions: - * - * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 - * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 - * DRA71x : SPRS960B, Revised February 2017 - */ - -&dra7_pmx_core { - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr12: mmc1-sdr12-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_hs: mmc1-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr25: mmc1-sdr25-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr50: mmc1-sdr50-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - >; - }; - - mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr104: mmc1-sdr104-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs: mmc2-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_rev10: mmc2-ddr-rev10-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - >; - }; - - mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs200: mmc2-hs200-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc4_pins_default: mmc4-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; -}; - -&dra7_iodelay_core { - - /* Corresponds to MMC1_MANUAL1 in datamanual */ - mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ - 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ - 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ - 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ - 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ - 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - >; - }; - - /* Corresponds to MMC1_MANUAL2 in datamanual */ - mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - >; - }; - - /* Corresponds to MMC1_MANUAL2 in datamanual */ - mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - >; - }; - - /* Corresponds to MMC2_MANUAL1 in datamanual */ - mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ - 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ - 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ - 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ - 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ - 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - >; - }; - - /* Corresponds to MMC2_MANUAL3 in datamanual */ - mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { - pinctrl-pin-array = < - 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ - 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ - 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - >; - }; - - /* Corresponds to MMC2_MANUAL3 in datamanual */ - mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { - pinctrl-pin-array = < - 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ - 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - >; - }; -}; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi deleted file mode 100644 index 90617261373c..000000000000 --- a/arch/arm/boot/dts/dra72x.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include "dra7.dtsi" - -/ { - compatible = "ti,dra722", "ti,dra72", "ti,dra7"; - - aliases { - rproc0 = &ipu1; - rproc1 = &ipu2; - rproc2 = &dsp1; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&wakeupgen>; - interrupts = ; - }; -}; - -&l4_per2 { - target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - cal: cal@0 { - compatible = "ti,dra72-cal"; - reg = <0x0000 0x400>, - <0x0800 0x40>, - <0x0900 0x40>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1"; - interrupts = ; - ti,camerrx-control = <&scm_conf 0xE94>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - }; -}; - -&dss { - reg = <0 0x80>, - <0x4054 0x4>, - <0x4300 0x20>; - reg-names = "dss", "pll1_clkctrl", "pll1"; - - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; - clock-names = "fck", "video1_clk"; -}; - -&mailbox5 { - mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&mailbox6 { - mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; -}; - -&pcie1_rc { - compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; -}; - -&pcie1_ep { - compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; -}; - -&pcie2_rc { - compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; -}; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi deleted file mode 100644 index 3256631510c5..000000000000 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms - */ - -#include "dra7-ipu-dsp-common.dtsi" - -&mailbox6 { - mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { - status = "okay"; - }; -}; - -&dsp2 { - mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; - ti,timers = <&timer6>; - ti,watchdog-timers = <&timer13>; -}; diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi deleted file mode 100644 index e2fdb0702f5c..000000000000 --- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +++ /dev/null @@ -1,639 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. - * - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * Rules for modifying this file: - * a) Update of this file should typically correspond to a datamanual revision. - * Datamanual revision that was used should be updated in comment below. - * If there is no update to datamanual, do not update the values. If you - * need to use values different from that recommended by the datamanual - * for your design, then you should consider adding values to the device- - * -tree file for your board directly. - * b) We keep the mode names as close to the datamanual as possible. So - * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, - * we follow that in code too. - * c) If the values change between multiple revisions of silicon, we add - * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, - * 'rev20' for PG 2.0 and so on. - * d) The node name and node label should be the exact same string. This is - * to curb naming creativity and achieve consistency. - * - * Datamanual Revisions: - * - * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019 - * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 - * - */ - -&dra7_pmx_core { - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr12: mmc1-sdr12-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_hs: mmc1-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr25: mmc1-sdr25-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr50: mmc1-sdr50-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_ddr50: mmc1-ddr50-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr104: mmc1-sdr104-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs: mmc2-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_3_3v_rev11: mmc2-ddr-3-3v-rev11-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_1_8v_rev11: mmc2-ddr-1-8v-rev11-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs200: mmc2-hs200-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc4_pins_default: mmc4-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; - - mmc4_pins_hs: mmc4-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; - - mmc3_pins_default: mmc3-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_hs: mmc3-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_sdr12: mmc3-sdr12-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_sdr25: mmc3-sdr25-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_sdr50: mmc3-sdr50-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc4_pins_sdr12: mmc4-sdr12-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; - - mmc4_pins_sdr25: mmc4-sdr25-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; -}; - -&dra7_iodelay_core { - - /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ - mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ - 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ - mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ - 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ - 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ - mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ - mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ - mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { - pinctrl-pin-array = < - 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ - 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ - mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { - pinctrl-pin-array = < - 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ - 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ - mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ - 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ - 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ - 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ - 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ - 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ - 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ - 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ - mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ - 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ - 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ - 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ - 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ - 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ - 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ - 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL1 in datamanual */ - mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL1 in datamanual */ - mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ - mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ - mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_MANUAL1 in datamanual */ - mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_MANUAL1 in datamanual */ - mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; -}; diff --git a/arch/arm/boot/dts/dra74x-p.dtsi b/arch/arm/boot/dts/dra74x-p.dtsi deleted file mode 100644 index 006189dad7a7..000000000000 --- a/arch/arm/boot/dts/dra74x-p.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "dra74x.dtsi" - -/ { - compatible = "ti,dra762", "ti,dra7"; - - ocp { - emif1: emif@4c000000 { - compatible = "ti,emif-dra7xx"; - reg = <0x4c000000 0x200>; - interrupts = ; - status = "disabled"; - }; - }; -}; - -/* MCAN interrupts are hard-wired to irqs 67, 68 */ -&crossbar_mpu { - ti,irqs-skip = <10 67 68 133 139 140>; -}; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi deleted file mode 100644 index cfb39dde4930..000000000000 --- a/arch/arm/boot/dts/dra74x.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include "dra7.dtsi" - -/ { - compatible = "ti,dra742", "ti,dra74", "ti,dra7"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - - vbb-supply = <&abb_mpu>; - }; - }; - - aliases { - rproc0 = &ipu1; - rproc1 = &ipu2; - rproc2 = &dsp1; - rproc3 = &dsp2; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&wakeupgen>; - interrupts = , - ; - }; - - ocp { - dsp2_system: dsp_system@41500000 { - compatible = "syscon"; - reg = <0x41500000 0x100>; - }; - - - target-module@41501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x41501000 0x4>, - <0x41501010 0x4>, - <0x41501014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp2 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x41501000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu0_dsp2: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - }; - }; - - target-module@41502000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x41502000 0x4>, - <0x41502010 0x4>, - <0x41502014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - - clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp2 1>; - reset-names = "rstctrl"; - ranges = <0x0 0x41502000 0x1000>; - #size-cells = <1>; - #address-cells = <1>; - - mmu1_dsp2: mmu@0 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - }; - }; - - dsp2: dsp@41000000 { - compatible = "ti,dra7-dsp"; - reg = <0x41000000 0x48000>, - <0x41600000 0x8000>, - <0x41700000 0x8000>; - reg-names = "l2ram", "l1pram", "l1dram"; - ti,bootreg = <&scm_conf 0x560 10>; - iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; - status = "disabled"; - resets = <&prm_dsp2 0>; - clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; - firmware-name = "dra7-dsp2-fw.xe66"; - }; - }; -}; - -&cpu0_opp_table { - opp-shared; -}; - -&dss { - reg = <0 0x80>, - <0x4054 0x4>, - <0x4300 0x20>, - <0x9054 0x4>, - <0x9300 0x20>; - reg-names = "dss", "pll1_clkctrl", "pll1", - "pll2_clkctrl", "pll2"; - - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>; - clock-names = "fck", "video1_clk", "video2_clk"; -}; - -&mailbox5 { - mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&mailbox6 { - mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&pcie1_rc { - compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; -}; - -&pcie1_ep { - compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; -}; - -&pcie2_rc { - compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; -}; - -&l4_per3 { - segment@0 { - usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x140000 0x4>, - <0x140010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x140000 0x20000>; - - omap_dwc3_4: omap_dwc3_4@0 { - compatible = "ti,dwc3"; - reg = <0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts deleted file mode 100644 index 57868ac60d29..000000000000 --- a/arch/arm/boot/dts/dra76-evm.dts +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "dra76x.dtsi" -#include "dra7-evm-common.dtsi" -#include "dra76x-mmc-iodelay.dtsi" -#include - -/ { - model = "TI DRA762 EVM"; - compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; - - aliases { - display0 = &hdmi0; - - sound0 = &sound0; - sound1 = &hdmi; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipu2_cma_pool: ipu2_cma@95800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x95800000 0x0 0x3800000>; - reusable; - status = "okay"; - }; - - dsp1_cma_pool: dsp1_cma@99000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x99000000 0x0 0x4000000>; - reusable; - status = "okay"; - }; - - ipu1_cma_pool: ipu1_cma@9d000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9d000000 0x0 0x2000000>; - reusable; - status = "okay"; - }; - - dsp2_cma_pool: dsp2_cma@9f000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x9f000000 0x0 0x800000>; - reusable; - status = "okay"; - }; - }; - - vsys_12v0: fixedregulator-vsys12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "vsys_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vsys_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vio_3v6: fixedregulator-vio_3v6 { - compatible = "regulator-fixed"; - regulator-name = "vio_3v6"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - vin-supply = <&vsys_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vio_3v3: fixedregulator-vio_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - vio_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vio_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vio_3v3>; - enable-active-high; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - vio_1v8: fixedregulator-vio_1v8 { - compatible = "regulator-fixed"; - regulator-name = "vio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&smps5_reg>; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 8 0>; /* gpio5_8 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&vio_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ - <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - ti,system-power-controller; - ti,palmas-override-powerhold; - interrupt-controller; - #interrupt-cells = <2>; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - smps12-in-supply = <&vsys_3v3>; - smps3-in-supply = <&vsys_3v3>; - smps4-in-supply = <&vsys_3v3>; - smps5-in-supply = <&vsys_3v3>; - ldo1-in-supply = <&vsys_3v3>; - ldo2-in-supply = <&vsys_3v3>; - ldo3-in-supply = <&vsys_5v0>; - ldo4-in-supply = <&vsys_5v0>; - ldo5-in-supply = <&vsys_3v3>; - - tps65917_regulators: regulators { - smps12_reg: smps12 { - /* VDD_DSPEVE */ - regulator-name = "smps12"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_CORE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDD_IVA */ - regulator-name = "smps4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDDS1V8 */ - regulator-name = "smps5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> VDA_PHY1_1V8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo2_reg: ldo2 { - /* LDO2_OUT --> VDA_PHY2_1V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-bypass; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - /* VDA_USB_3V3 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDD_SDIO_DV */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - lp87565: lp87565@60 { - compatible = "ti,lp87565-q1"; - reg = <0x60>; - - buck10-in-supply =<&vsys_3v3>; - buck23-in-supply =<&vsys_3v3>; - - regulators: regulators { - buck10_reg: buck10 { - /*VDD_MPU*/ - regulator-name = "buck10"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - buck23_reg: buck23 { - /* VDD_GPU*/ - regulator-name = "buck23"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - pcf_lcd: pcf8757@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - - pcf_gpio_21: pcf8757@21 { - compatible = "nxp,pcf8575"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_hdmi: pcf8575@26 { - compatible = "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - hdmi-audio-hog { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vio_3v3>; - IOVDD-supply = <&vio_3v3>; - DRVDD-supply = <&vio_3v3>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&cpu0 { - vdd-supply = <&buck10_reg>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vio_3v3_sd>; - vqmmc-supply = <&ldo4_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is always hardwired. - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vio_1v8>; - vqmmc-supply = <&vio_1v8>; - bus-width = <8>; - non-removable; - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_default>; - pinctrl-2 = <&mmc2_pins_default>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; -}; - -&mmc4 { - status = "okay"; - vmmc-supply = <&vio_3v6>; - vqmmc-supply = <&vmmcwl_fixed>; - pinctrl-names = "default", "hs", "sdr12", "sdr25"; - pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; - pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; - pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; - pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; -}; - -/* No RTC on this device */ -&rtc { - status = "disabled"; -}; - -&mac_sw { - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <&dp83867_0>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <&dp83867_1>; - phy-mode = "rgmii-id"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo3_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo3_reg>; -}; - -&dss { - status = "okay"; - vdda_video-supply = <&ldo5_reg>; -}; - -&hdmi { - status = "okay"; - - vdda-supply = <&ldo1_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&qspi { - spi-max-frequency = <96000000>; - flash@0 { - spi-max-frequency = <96000000>; - }; -}; - -&pcie2_phy { - status = "okay"; -}; - -&pcie1_rc { - num-lanes = <2>; - phys = <&pcie1_phy>, <&pcie2_phy>; - phy-names = "pcie-phy0", "pcie-phy1"; -}; - -&pcie1_ep { - num-lanes = <2>; - phys = <&pcie1_phy>, <&pcie2_phy>; - phy-names = "pcie-phy0", "pcie-phy1"; -}; - -&extcon_usb1 { - vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; -}; - -&extcon_usb2 { - vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; -}; - -&m_can0 { - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -&ipu2 { - status = "okay"; - memory-region = <&ipu2_cma_pool>; -}; - -&ipu1 { - status = "okay"; - memory-region = <&ipu1_cma_pool>; -}; - -&dsp1 { - status = "okay"; - memory-region = <&dsp1_cma_pool>; -}; - -&dsp2 { - status = "okay"; - memory-region = <&dsp2_cma_pool>; -}; diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi deleted file mode 100644 index 4690554dfa6e..000000000000 --- a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Texas Instruments -// MMC IOdelay values for TI's DRA76x and AM576x SoCs. -// Author: Sekhar Nori - -/* - * Rules for modifying this file: - * a) Update of this file should typically correspond to a datamanual revision. - * Datamanual revision that was used should be updated in comment below. - * If there is no update to datamanual, do not update the values. If you - * need to use values different from that recommended by the datamanual - * for your design, then you should consider adding values to the device- - * -tree file for your board directly. - * b) We keep the mode names as close to the datamanual as possible. So - * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, - * we follow that in code too. - * c) If the values change between multiple revisions of silicon, we add - * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, - * 'rev20' for PG 2.0 and so on. - * d) The node name and node label should be the exact same string. This is - * to curb naming creativity and achieve consistency. - * - * Datamanual Revisions: - * - * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018 - * - */ - -&dra7_pmx_core { - mmc1_pins_default: mmc1-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_hs: mmc1-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr50: mmc1-sdr50-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_ddr50: mmc1-ddr50-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs200: mmc2-hs200-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc3_pins_default: mmc3-default-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc4_pins_hs: mmc4-hs-pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; -}; - -&dra7_iodelay_core { - - /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ - mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ - 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ - 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ - 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ - 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ - 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ - mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ - mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { - pinctrl-pin-array = < - 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ - 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ - 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL1 in datamanual */ - mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL2 in datamanual */ - mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC4_MANUAL1 in datamanual */ - mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ - mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; -}; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi deleted file mode 100644 index 931db7932c11..000000000000 --- a/arch/arm/boot/dts/dra76x.dtsi +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "dra74x.dtsi" - -/ { - compatible = "ti,dra762", "ti,dra7"; - - ocp { - target-module@42c01900 { - compatible = "ti,sysc-dra7-mcan", "ti,sysc"; - ranges = <0x0 0x42c00000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x42c01900 0x4>, - <0x42c01904 0x4>, - <0x42c01908 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | - SYSC_DRA7_MCAN_ENAWAKEUP)>; - ti,syss-mask = <1>; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; - clock-names = "fck"; - - m_can0: mcan@1a00 { - compatible = "bosch,m_can"; - reg = <0x1a00 0x4000>, <0x0 0x18FC>; - reg-names = "m_can", "message_ram"; - interrupt-parent = <&gic>; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&l3_iclk_div>, <&mcan_clk>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; - }; - }; - }; - -}; - -&l4_per3 { - target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x1b0000 0x4>, - <0x1b0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b0000 0x10000>; - - cal: cal@0 { - compatible = "ti,dra76-cal"; - reg = <0x0000 0x400>, - <0x0800 0x40>, - <0x0900 0x40>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1"; - interrupts = ; - ti,camerrx-control = <&scm_conf 0x6dc>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - }; -}; - -&scm_conf_clocks { - dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - reg = <0x03fc>; - ti,bit-shift = <20>; - ti,latch-bit = <26>; - assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; - assigned-clock-rates = <80000000>; - }; - - dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; - reg = <0x3fc>; - ti,bit-shift = <29>; - ti,latch-bit = <26>; - assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; - assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; - }; - - mcan_clk: mcan_clk@3fc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; - ti,bit-shift = <27>; - reg = <0x3fc>; - }; -}; - -&rtctarget { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; - -&mmc3 { - /* dra76x is not affected by i887 */ - max-frequency = <96000000>; -}; - -&cpu0_opp_table { - opp_plus@1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000 950000 1250000>, - <1250000 950000 1250000>; - opp-supported-hw = <0xFF 0x08>; - }; -}; - -&opp_supply_mpu { - ti,efuse-settings = < - /* uV offset */ - 1060000 0x0 - 1160000 0x4 - 1210000 0x8 - 1250000 0xC - >; -}; - -&abb_mpu { - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1160000 0 0x4 0 0x02000000 0x01F00000 - 1210000 0 0x8 0 0x02000000 0x01F00000 - 1250000 0 0xC 0 0x02000000 0x01F00000 - >; -}; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi deleted file mode 100644 index 04a7a6d1d529..000000000000 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ /dev/null @@ -1,2094 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for DRA7xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_core_aon_clocks { - atl_clkin0_ck: clock-atl-clkin0 { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clock-output-names = "atl_clkin0_ck"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - atl_clkin1_ck: clock-atl-clkin1 { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clock-output-names = "atl_clkin1_ck"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - atl_clkin2_ck: clock-atl-clkin2 { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clock-output-names = "atl_clkin2_ck"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - atl_clkin3_ck: clock-atl-clkin3 { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clock-output-names = "atl_clkin3_ck"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - hdmi_clkin_ck: clock-hdmi-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "hdmi_clkin_ck"; - clock-frequency = <0>; - }; - - mlb_clkin_ck: clock-mlb-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "mlb_clkin_ck"; - clock-frequency = <0>; - }; - - mlbp_clkin_ck: clock-mlbp-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "mlbp_clkin_ck"; - clock-frequency = <0>; - }; - - pciesref_acs_clk_ck: clock-pciesref-acs { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "pciesref_acs_clk_ck"; - clock-frequency = <100000000>; - }; - - ref_clkin0_ck: clock-ref-clkin0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "ref_clkin0_ck"; - clock-frequency = <0>; - }; - - ref_clkin1_ck: clock-ref-clkin1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "ref_clkin1_ck"; - clock-frequency = <0>; - }; - - ref_clkin2_ck: clock-ref-clkin2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "ref_clkin2_ck"; - clock-frequency = <0>; - }; - - ref_clkin3_ck: clock-ref-clkin3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "ref_clkin3_ck"; - clock-frequency = <0>; - }; - - rmii_clk_ck: clock-rmii { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "rmii_clk_ck"; - clock-frequency = <0>; - }; - - sdvenc_clkin_ck: clock-sdvenc-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "sdvenc_clkin_ck"; - clock-frequency = <0>; - }; - - secure_32k_clk_src_ck: clock-secure-32k-clk-src { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "secure_32k_clk_src_ck"; - clock-frequency = <32768>; - }; - - sys_clk32_crystal_ck: clock-sys-clk32-crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "sys_clk32_crystal_ck"; - clock-frequency = <32768>; - }; - - sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "sys_clk32_pseudo_ck"; - clocks = <&sys_clkin1>; - clock-mult = <1>; - clock-div = <610>; - }; - - virt_12000000_ck: clock-virt-12000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_12000000_ck"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: clock-virt-13000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_13000000_ck"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: clock-virt-16800000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_16800000_ck"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: clock-virt-19200000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_19200000_ck"; - clock-frequency = <19200000>; - }; - - virt_20000000_ck: clock-virt-20000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_20000000_ck"; - clock-frequency = <20000000>; - }; - - virt_26000000_ck: clock-virt-26000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_26000000_ck"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: clock-virt-27000000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_27000000_ck"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: clock-virt-38400000 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_38400000_ck"; - clock-frequency = <38400000>; - }; - - sys_clkin2: clock-sys-clkin2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "sys_clkin2"; - clock-frequency = <22579200>; - }; - - usb_otg_clkin_ck: clock-usb-otg-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "usb_otg_clkin_ck"; - clock-frequency = <0>; - }; - - video1_clkin_ck: clock-video1-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "video1_clkin_ck"; - clock-frequency = <0>; - }; - - video1_m2_clkin_ck: clock-video1-m2-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "video1_m2_clkin_ck"; - clock-frequency = <0>; - }; - - video2_clkin_ck: clock-video2-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "video2_clkin_ck"; - clock-frequency = <0>; - }; - - video2_m2_clkin_ck: clock-video2-m2-clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "video2_m2_clkin_ck"; - clock-frequency = <0>; - }; - - dpll_abe_ck: clock@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clock-output-names = "dpll_abe_ck"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: clock-dpll-abe-x2 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_abe_x2_ck"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m2x2_ck"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - abe_clk: clock-abe@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_clk"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m2_ck"; - clocks = <&dpll_abe_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m3x2_ck"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_core_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: clock@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clock-output-names = "dpll_core_ck"; - clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: clock-dpll-core-x2 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_core_x2_ck"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h12x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x013c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mpu_dpll_hs_clk_div"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: clock@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clock-output-names = "dpll_mpu_ck"; - clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_mpu_m2_ck"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0170>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_dclk_div: clock-mpu-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mpu_dclk_div"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dsp_dpll_hs_clk_div"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_dsp_byp_mux"; - clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0240>; - }; - - dpll_dsp_ck: clock@234 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_dsp_ck"; - clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; - reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; - assigned-clocks = <&dpll_dsp_ck>; - assigned-clock-rates = <600000000>; - }; - - dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_dsp_m2_ck"; - clocks = <&dpll_dsp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0244>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_dsp_m2_ck>; - assigned-clock-rates = <600000000>; - }; - - iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "iva_dpll_hs_clk_div"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_iva_byp_mux"; - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: clock@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_iva_ck"; - clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <1165000000>; - }; - - dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_iva_m2_ck"; - clocks = <&dpll_iva_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01b0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_iva_m2_ck>; - assigned-clock-rates = <388333334>; - }; - - iva_dclk: clock-iva-dclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "iva_dclk"; - clocks = <&dpll_iva_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_gpu_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02e4>; - }; - - dpll_gpu_ck: clock@2d8 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_gpu_ck"; - clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; - reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; - assigned-clocks = <&dpll_gpu_ck>; - assigned-clock-rates = <1277000000>; - }; - - dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_gpu_m2_ck"; - clocks = <&dpll_gpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02e8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_gpu_m2_ck>; - assigned-clock-rates = <425666667>; - }; - - dpll_core_m2_ck: clock-dpll-core-m2-8@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m2_ck"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0130>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "core_dpll_out_dclk_div"; - clocks = <&dpll_core_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_ddr_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x021c>; - }; - - dpll_ddr_ck: clock@210 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_ddr_ck"; - clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; - reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; - }; - - dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_ddr_m2_ck"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0220>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_gmac_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02b4>; - }; - - dpll_gmac_ck: clock@2a8 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_gmac_ck"; - clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; - reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; - }; - - dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_gmac_m2_ck"; - clocks = <&dpll_gmac_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02b8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - video2_dclk_div: clock-video2-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "video2_dclk_div"; - clocks = <&video2_m2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video1_dclk_div: clock-video1-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "video1_dclk_div"; - clocks = <&video1_m2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdmi_dclk_div: clock-hdmi-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "hdmi_dclk_div"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "per_dpll_hs_clk_div"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "usb_dpll_hs_clk_div"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "eve_dpll_hs_clk_div"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_eve_byp_mux"; - clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0290>; - }; - - dpll_eve_ck: clock@284 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_eve_ck"; - clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; - reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; - }; - - dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_eve_m2_ck"; - clocks = <&dpll_eve_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0294>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - eve_dclk_div: clock-eve-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "eve_dclk_div"; - clocks = <&dpll_eve_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h13x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0140>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h14x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0144>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h22x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0154>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h23x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h24x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_ddr_x2_ck: clock-dpll-ddr-x2 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_ddr_x2_ck"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_ddr_h11x2_ck"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0228>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_dsp_x2_ck: clock-dpll-dsp-x2 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_dsp_x2_ck"; - clocks = <&dpll_dsp_ck>; - }; - - dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_dsp_m3x2_ck"; - clocks = <&dpll_dsp_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0248>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_dsp_m3x2_ck>; - assigned-clock-rates = <400000000>; - }; - - dpll_gmac_x2_ck: clock-dpll-gmac-x2 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_gmac_x2_ck"; - clocks = <&dpll_gmac_ck>; - }; - - dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_gmac_h11x2_ck"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_gmac_h12x2_ck"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_gmac_h13x2_ck"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_gmac_m3x2_ck"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02bc>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - gmii_m_clk_div: clock-gmii-m-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "gmii_m_clk_div"; - clocks = <&dpll_gmac_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hdmi_clk2_div: clock-hdmi-clk2-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "hdmi_clk2_div"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdmi_div_clk: clock-hdmi-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "hdmi_div_clk"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3_iclk_div: clock-l3-iclk-div-4@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3_iclk_div"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x0100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - l4_root_clk_div: clock-l4-root-clk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l4_root_clk_div"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - video1_clk2_div: clock-video1-clk2-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "video1_clk2_div"; - clocks = <&video1_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video1_div_clk: clock-video1-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "video1_div_clk"; - clocks = <&video1_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video2_clk2_div: clock-video2-clk2-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "video2_clk2_div"; - clocks = <&video2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video2_div_clk: clock-video2-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "video2_div_clk"; - clocks = <&video2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dummy_ck: clock-dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "dummy_ck"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin1: clock-sys-clkin1@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sys_clkin1"; - clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_sys_clk_mux"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0118>; - }; - - abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_bypass_clk_mux"; - clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; - reg = <0x0114>; - }; - - abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_clk_mux"; - clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - abe_24m_fclk: clock-abe-24m@11c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_24m_fclk"; - clocks = <&dpll_abe_m2x2_ck>; - reg = <0x011c>; - ti,dividers = <8>, <16>; - }; - - aess_fclk: clock-aess@178 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "aess_fclk"; - clocks = <&abe_clk>; - reg = <0x0178>; - ti,max-div = <2>; - }; - - abe_giclk_div: clock-abe-giclk-div@174 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_giclk_div"; - clocks = <&aess_fclk>; - reg = <0x0174>; - ti,max-div = <2>; - }; - - abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_lp_clk_div"; - clocks = <&dpll_abe_m2x2_ck>; - reg = <0x01d8>; - ti,dividers = <16>, <32>; - }; - - abe_sys_clk_div: clock-abe-sys-clk-div@120 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_sys_clk_div"; - clocks = <&sys_clkin1>; - reg = <0x0120>; - ti,max-div = <2>; - }; - - adc_gfclk_mux: clock-adc-gfclk-mux@1dc { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "adc_gfclk_mux"; - clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; - reg = <0x01dc>; - }; - - sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "sys_clk1_dclk_div"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x01c8>; - ti,index-power-of-two; - }; - - sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "sys_clk2_dclk_div"; - clocks = <&sys_clkin2>; - ti,max-div = <64>; - reg = <0x01cc>; - ti,index-power-of-two; - }; - - per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "per_abe_x1_dclk_div"; - clocks = <&dpll_abe_m2_ck>; - ti,max-div = <64>; - reg = <0x01bc>; - ti,index-power-of-two; - }; - - dsp_gclk_div: clock-dsp-gclk-div@18c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dsp_gclk_div"; - clocks = <&dpll_dsp_m2_ck>; - ti,max-div = <64>; - reg = <0x018c>; - ti,index-power-of-two; - }; - - gpu_dclk: clock-gpu-dclk@1a0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "gpu_dclk"; - clocks = <&dpll_gpu_m2_ck>; - ti,max-div = <64>; - reg = <0x01a0>; - ti,index-power-of-two; - }; - - emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "emif_phy_dclk_div"; - clocks = <&dpll_ddr_m2_ck>; - ti,max-div = <64>; - reg = <0x0190>; - ti,index-power-of-two; - }; - - gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "gmac_250m_dclk_div"; - clocks = <&dpll_gmac_m2_ck>; - ti,max-div = <64>; - reg = <0x019c>; - ti,index-power-of-two; - }; - - gmac_main_clk: clock-gmac-main { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "gmac_main_clk"; - clocks = <&gmac_250m_dclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3init_480m_dclk_div"; - clocks = <&dpll_usb_m2_ck>; - ti,max-div = <64>; - reg = <0x01ac>; - ti,index-power-of-two; - }; - - usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "usb_otg_dclk_div"; - clocks = <&usb_otg_clkin_ck>; - ti,max-div = <64>; - reg = <0x0184>; - ti,index-power-of-two; - }; - - sata_dclk_div: clock-sata-dclk-div@1c0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "sata_dclk_div"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x01c0>; - ti,index-power-of-two; - }; - - pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "pcie2_dclk_div"; - clocks = <&dpll_pcie_ref_m2_ck>; - ti,max-div = <64>; - reg = <0x01b8>; - ti,index-power-of-two; - }; - - pcie_dclk_div: clock-pcie-dclk-div@1b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "pcie_dclk_div"; - clocks = <&apll_pcie_m2_ck>; - ti,max-div = <64>; - reg = <0x01b4>; - ti,index-power-of-two; - }; - - emu_dclk_div: clock-emu-dclk-div@194 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "emu_dclk_div"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x0194>; - ti,index-power-of-two; - }; - - secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "secure_32k_dclk_div"; - clocks = <&secure_32k_clk_src_ck>; - ti,max-div = <64>; - reg = <0x01c4>; - ti,index-power-of-two; - }; - - clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "clkoutmux0_clk_mux"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x0158>; - }; - - clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "clkoutmux1_clk_mux"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x015c>; - }; - - clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "clkoutmux2_clk_mux"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x0160>; - }; - - custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "custefuse_sys_gfclk_div"; - clocks = <&sys_clkin1>; - clock-mult = <1>; - clock-div = <2>; - }; - - eve_clk: clock-eve@180 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "eve_clk"; - clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; - reg = <0x0180>; - }; - - hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "hdmi_dpll_clk_mux"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0164>; - }; - - mlb_clk: clock-mlb@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "mlb_clk"; - clocks = <&mlb_clkin_ck>; - ti,max-div = <64>; - reg = <0x0134>; - ti,index-power-of-two; - }; - - mlbp_clk: clock-mlbp@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "mlbp_clk"; - clocks = <&mlbp_clkin_ck>; - ti,max-div = <64>; - reg = <0x0130>; - ti,index-power-of-two; - }; - - per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "per_abe_x1_gfclk2_div"; - clocks = <&dpll_abe_m2_ck>; - ti,max-div = <64>; - reg = <0x0138>; - ti,index-power-of-two; - }; - - timer_sys_clk_div: clock-timer-sys-clk-div@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "timer_sys_clk_div"; - clocks = <&sys_clkin1>; - reg = <0x0144>; - ti,max-div = <2>; - }; - - video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "video1_dpll_clk_mux"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0168>; - }; - - video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "video2_dpll_clk_mux"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x016c>; - }; - - wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "wkupaon_iclk_mux"; - clocks = <&sys_clkin1>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; -}; - -&cm_core_clocks { - dpll_pcie_ref_ck: clock@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_pcie_ref_ck"; - clocks = <&sys_clkin1>, <&sys_clkin1>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_pcie_ref_m2ldo_ck"; - clocks = <&dpll_pcie_ref_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0210>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { - compatible = "ti,mux-clock"; - clock-output-names = "apll_pcie_in_clk_mux"; - clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; - #clock-cells = <0>; - reg = <0x021c 0x4>; - ti,bit-shift = <7>; - }; - - apll_pcie_ck: clock@21c { - #clock-cells = <0>; - compatible = "ti,dra7-apll-clock"; - clock-output-names = "apll_pcie_ck"; - clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; - reg = <0x021c>, <0x0220>; - }; - - optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { - compatible = "ti,divider-clock"; - clock-output-names = "optfclk_pciephy_div"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x021c>; - ti,dividers = <2>, <1>; - ti,bit-shift = <8>; - ti,max-div = <2>; - }; - - apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "apll_pcie_clkvcoldo"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "apll_pcie_clkvcoldo_div"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - apll_pcie_m2_ck: clock-apll-pcie-m2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "apll_pcie_m2_ck"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_per_byp_mux"; - clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: clock@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_per_ck"; - clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_m2_ck: clock-dpll-per-m2-8@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2_ck"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_96m_aon_dclk_div"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_usb_byp_mux"; - clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: clock@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clock-output-names = "dpll_usb_ck"; - clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_usb_m2_ck"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0190>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_pcie_ref_m2_ck"; - clocks = <&dpll_pcie_ref_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0210>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_x2_ck: clock-dpll-per-x2 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_per_x2_ck"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h11x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h12x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h13x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0160>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h14x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0164>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_usb_clkdcoldo"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - func_128m_clk: clock-func-128m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_128m_clk"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: clock-func-12m-fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_12m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: clock-func-24m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_24m_clk"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: clock-func-48m-fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_48m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: clock-func-96m-fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_96m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: clock-l3init-60m@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3init_60m_fclk"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - clkout2_clk: clock-clkout2-8@6b0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "clkout2_clk"; - clocks = <&clkoutmux2_clk_mux>; - ti,bit-shift = <8>; - reg = <0x06b0>; - }; - - l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "l3init_960m_gfclk"; - clocks = <&dpll_usb_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x06c0>; - }; - - usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy1_always_on_clk32k"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy2_always_on_clk32k"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0688>; - }; - - usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy3_always_on_clk32k"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0698>; - }; - - gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gpu_core_gclk_mux"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; - ti,bit-shift = <24>; - reg = <0x1220>; - assigned-clocks = <&gpu_core_gclk_mux>; - assigned-clock-parents = <&dpll_gpu_m2_ck>; - }; - - gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gpu_hyd_gclk_mux"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; - ti,bit-shift = <26>; - reg = <0x1220>; - assigned-clocks = <&gpu_hyd_gclk_mux>; - assigned-clock-parents = <&dpll_gpu_m2_ck>; - }; - - l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3instr_ts_gclk_div"; - clocks = <&wkupaon_iclk_mux>; - ti,bit-shift = <24>; - reg = <0x0e50>; - ti,dividers = <8>, <16>, <32>; - }; - - vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "vip1_gclk_mux"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1020>; - }; - - vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "vip2_gclk_mux"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1028>; - }; - - vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "vip3_gclk_mux"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1030>; - }; -}; - -&cm_core_clockdomains { - coreaon_clkdm: clock-coreaon-clkdm { - compatible = "ti,clockdomain"; - clock-output-names = "coreaon_clkdm"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scm_conf_clocks { - dss_deshdcp_clk: clock-dss-deshdcp-0@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss_deshdcp_clk"; - clocks = <&l3_iclk_div>; - ti,bit-shift = <0>; - reg = <0x558>; - }; - - ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm0_tbclk"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <20>; - reg = <0x0558>; - }; - - ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm1_tbclk"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <21>; - reg = <0x0558>; - }; - - ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "ehrpwm2_tbclk"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <22>; - reg = <0x0558>; - }; - - sys_32k_ck: clock-sys-32k { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sys_32k_ck"; - clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; - ti,bit-shift = <8>; - reg = <0x6c4>; - }; -}; - -&cm_core_aon { - mpu_cm: clock@300 { - compatible = "ti,omap4-cm"; - clock-output-names = "mpu_cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpu_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "mpu_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - dsp1_cm: clock@400 { - compatible = "ti,omap4-cm"; - clock-output-names = "dsp1_cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - dsp1_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dsp1_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - ipu_cm: clock@500 { - compatible = "ti,omap4-cm"; - clock-output-names = "ipu_cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - ipu1_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "ipu1_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; - assigned-clock-parents = <&dpll_core_h22x2_ck>; - }; - - ipu_clkctrl: clock@50 { - compatible = "ti,clkctrl"; - clock-output-names = "ipu_clkctrl"; - reg = <0x50 0x34>; - #clock-cells = <2>; - }; - - }; - - dsp2_cm: clock@600 { - compatible = "ti,omap4-cm"; - clock-output-names = "dsp2_cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - dsp2_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dsp2_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - rtc_cm: clock@700 { - compatible = "ti,omap4-cm"; - clock-output-names = "rtc_cm"; - reg = <0x700 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x60>; - - rtc_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "rtc_clkctrl"; - reg = <0x20 0x28>; - #clock-cells = <2>; - }; - }; - - vpe_cm: clock@760 { - compatible = "ti,omap4-cm"; - clock-output-names = "vpe_cm"; - reg = <0x760 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x760 0xc>; - - vpe_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "vpe_clkctrl"; - reg = <0x0 0xc>; - #clock-cells = <2>; - }; - }; - -}; - -&cm_core { - coreaon_cm: clock@600 { - compatible = "ti,omap4-cm"; - clock-output-names = "coreaon_cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - coreaon_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "coreaon_clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l3main1_cm: clock@700 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3main1_cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3main1_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3main1_clkctrl"; - reg = <0x20 0x74>; - #clock-cells = <2>; - }; - - }; - - ipu2_cm: clock@900 { - compatible = "ti,omap4-cm"; - clock-output-names = "ipu2_cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ipu2_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "ipu2_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - dma_cm: clock@a00 { - compatible = "ti,omap4-cm"; - clock-output-names = "dma_cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - dma_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dma_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - emif_cm: clock@b00 { - compatible = "ti,omap4-cm"; - clock-output-names = "emif_cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - emif_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "emif_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - atl_cm: clock@c00 { - compatible = "ti,omap4-cm"; - clock-output-names = "atl_cm"; - reg = <0xc00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xc00 0x100>; - - atl_clkctrl: clock@0 { - compatible = "ti,clkctrl"; - clock-output-names = "atl_clkctrl"; - reg = <0x0 0x4>; - #clock-cells = <2>; - }; - }; - - l4cfg_cm: clock@d00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4cfg_cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4cfg_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4cfg_clkctrl"; - reg = <0x20 0x84>; - #clock-cells = <2>; - }; - }; - - l3instr_cm: clock@e00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3instr_cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3instr_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3instr_clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - iva_cm: clock@f00 { - compatible = "ti,omap4-cm"; - clock-output-names = "iva_cm"; - reg = <0xf00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xf00 0x100>; - - iva_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "iva_clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - cam_cm: clock@1000 { - compatible = "ti,omap4-cm"; - clock-output-names = "cam_cm"; - reg = <0x1000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x100>; - - cam_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "cam_clkctrl"; - reg = <0x20 0x2c>; - #clock-cells = <2>; - }; - }; - - dss_cm: clock@1100 { - compatible = "ti,omap4-cm"; - clock-output-names = "dss_cm"; - reg = <0x1100 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1100 0x100>; - - dss_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dss_clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - gpu_cm: clock@1200 { - compatible = "ti,omap4-cm"; - clock-output-names = "gpu_cm"; - reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1200 0x100>; - - gpu_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "gpu_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3init_cm: clock@1300 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3init_cm"; - reg = <0x1300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1300 0x100>; - - l3init_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3init_clkctrl"; - reg = <0x20 0x6c>, <0xe0 0x14>; - #clock-cells = <2>; - }; - - pcie_clkctrl: clock@b0 { - compatible = "ti,clkctrl"; - clock-output-names = "pcie_clkctrl"; - reg = <0xb0 0xc>; - #clock-cells = <2>; - }; - - gmac_clkctrl: clock@d0 { - compatible = "ti,clkctrl"; - clock-output-names = "gmac_clkctrl"; - reg = <0xd0 0x4>; - #clock-cells = <2>; - }; - - }; - - l4per_cm: clock@1700 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4per_cm"; - reg = <0x1700 0x300>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1700 0x300>; - - l4per_clkctrl: clock@28 { - compatible = "ti,clkctrl"; - clock-output-names = "l4per_clkctrl"; - reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; - #clock-cells = <2>; - - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&abe_24m_fclk>; - }; - - l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4sec_clkctrl"; - reg = <0x1a0 0x2c>; - #clock-cells = <2>; - }; - - l4per2_clkctrl: clock@c { - compatible = "ti,clkctrl"; - clock-output-names = "l4per2_clkctrl"; - reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; - #clock-cells = <2>; - }; - - l4per3_clkctrl: clock@14 { - compatible = "ti,clkctrl"; - clock-output-names = "l4per3_clkctrl"; - reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; - #clock-cells = <2>; - }; - }; - -}; - -&prm { - wkupaon_cm: clock@1800 { - compatible = "ti,omap4-cm"; - clock-output-names = "wkupaon_cm"; - reg = <0x1800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1800 0x100>; - - wkupaon_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "wkupaon_clkctrl"; - reg = <0x20 0x6c>; - #clock-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi deleted file mode 100644 index dd03e3860f97..000000000000 --- a/arch/arm/boot/dts/e60k02.dtsi +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - * and - * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd - * - * Netronix E60K02 board common. - * This board is equipped with different SoCs and - * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and - * the Tolino Shine 3 (with i.MX6SL) - */ -#include - -/ { - - chosen { - stdout-path = &uart1; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-cover { - label = "Cover"; - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - - led { - label = "e60k02:white:on"; - gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - regulator-name = "SD3_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <20>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - }; -}; - - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; - - lm3630a: backlight@36 { - reg = <0x36>; - compatible = "ti,lm3630a"; - enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0>; - label = "backlight_warm"; - default-brightness = <0>; - max-brightness = <255>; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - label = "backlight_cold"; - default-brightness = <0>; - max-brightness = <255>; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - status = "okay"; - - touchscreen@24 { - compatible = "cypress,tt21000"; - reg = <0x24>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cyttsp5_gpio>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - vdd-supply = <&ldo5_reg>; - }; - - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ - -}; - -&i2c3 { - clock-frequency = <100000>; - status = "okay"; - - ricoh619: pmic@32 { - compatible = "ricoh,rc5t619"; - reg = <0x32>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - system-power-controller; - - regulators { - dcdc1_reg: DCDC1 { - regulator-name = "DCDC1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <900000>; - regulator-suspend-min-microvolt = <900000>; - }; - }; - - /* Core3_3V3 */ - dcdc2_reg: DCDC2 { - regulator-name = "DCDC2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3300000>; - regulator-suspend-min-microvolt = <3300000>; - }; - }; - - dcdc3_reg: DCDC3 { - regulator-name = "DCDC3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V2 */ - dcdc4_reg: DCDC4 { - regulator-name = "DCDC4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V8 */ - dcdc5_reg: DCDC5 { - regulator-name = "DCDC5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1700000>; - regulator-suspend-min-microvolt = <1700000>; - }; - }; - - /* IR_3V3 */ - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-boot-on; - }; - - /* Core1_3V3 */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3000000>; - regulator-suspend-min-microvolt = <3000000>; - }; - }; - - /* Core5_1V2 */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-boot-on; - }; - - /* SPD_3V3 */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-always-on; - regulator-boot-on; - }; - - /* DDR_0V6 */ - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-always-on; - regulator-boot-on; - }; - - /* VDD_PWM */ - ldo7_reg: LDO7 { - regulator-name = "LDO7"; - regulator-always-on; - regulator-boot-on; - }; - - /* ldo_1v8 */ - ldo8_reg: LDO8 { - regulator-name = "LDO8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "LDO9"; - regulator-boot-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "LDO10"; - regulator-boot-on; - }; - - ldortc1_reg: LDORTC1 { - regulator-name = "LDORTC1"; - regulator-boot-on; - }; - }; - }; -}; - -&snvs_rtc { - /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ - status = "disabled"; -}; - -&uart1 { - /* J4, through-hole */ - status = "okay"; -}; - -&uart4 { - /* TP198, next to J4, SMD pads */ - status = "okay"; -}; - -&usdhc2 { - non-removable; - status = "okay"; -}; - -&usdhc3 { - vmmc-supply = <®_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - cap-power-off-card; - non-removable; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi deleted file mode 100644 index 4e1bf080eaca..000000000000 --- a/arch/arm/boot/dts/e70k02.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2021 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - * and - * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd - * - * Netronix E70K02 board common. - * This board is equipped with different SoCs and - * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and - * the Tolino Shine 3 (with i.MX6SL) - */ -#include - -/ { - aliases { - mmc0 = &usdhc1; - mmc1 = &usdhc3; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-cover { - label = "Cover"; - gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - - key-pageup { - label = "PageUp"; - gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-pagedown { - label = "PageDown"; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - - led { - label = "e70k02:white:on"; - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - regulator-name = "SD3_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <20>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; - - lm3630a: backlight@36 { - reg = <0x36>; - compatible = "ti,lm3630a"; - enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0>; - label = "backlight_warm"; - default-brightness = <0>; - max-brightness = <255>; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - label = "backlight_cold"; - default-brightness = <0>; - max-brightness = <255>; - }; - }; - - /* TODO: KX122 acceleration sensor a 0x1e */ - -}; - -&i2c2 { - clock-frequency = <100000>; - status = "okay"; - - touchscreen@24 { - compatible = "cypress,tt21000"; - reg = <0x24>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cyttsp5_gpio>; - interrupt-parent = <&gpio4>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - vdd-supply = <&ldo5_reg>; - }; - - /* TODO: SY7636 PMIC for E Ink at 0x62 */ - -}; - -&i2c3 { - clock-frequency = <100000>; - status = "okay"; - - ricoh619: pmic@32 { - compatible = "ricoh,rc5t619"; - reg = <0x32>; - interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - system-power-controller; - - regulators { - dcdc1_reg: DCDC1 { - regulator-name = "DCDC1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <900000>; - regulator-suspend-min-microvolt = <900000>; - }; - }; - - /* Core3_3V3 */ - dcdc2_reg: DCDC2 { - regulator-name = "DCDC2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3300000>; - regulator-suspend-min-microvolt = <3300000>; - }; - }; - - dcdc3_reg: DCDC3 { - regulator-name = "DCDC3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V2 */ - dcdc4_reg: DCDC4 { - regulator-name = "DCDC4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V8 */ - dcdc5_reg: DCDC5 { - regulator-name = "DCDC5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1700000>; - regulator-suspend-min-microvolt = <1700000>; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-boot-on; - }; - - /* Core1_3V3 */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3000000>; - regulator-suspend-min-microvolt = <3000000>; - }; - }; - - /* Core5_1V2 */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-boot-on; - }; - - /* SPD_3V3 */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-always-on; - regulator-boot-on; - }; - - /* DDR_0V6 */ - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-always-on; - regulator-boot-on; - }; - - /* VDD_PWM */ - ldo7_reg: LDO7 { - regulator-name = "LDO7"; - regulator-boot-on; - }; - - /* ldo_1v8 */ - ldo8_reg: LDO8 { - regulator-name = "LDO8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "LDO9"; - regulator-boot-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "LDO10"; - regulator-boot-on; - }; - - ldortc1_reg: LDORTC1 { - regulator-name = "LDORTC1"; - regulator-boot-on; - }; - }; - }; -}; - -&snvs_rtc { - /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ - status = "disabled"; -}; - -&uart1 { - status = "okay"; -}; - -&usdhc1 { - non-removable; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - vmmc-supply = <®_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - cap-power-off-card; - non-removable; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts deleted file mode 100644 index f6eb71553b95..000000000000 --- a/arch/arm/boot/dts/ecx-2000.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda ECX-2000"; - compatible = "calxeda,ecx-2000"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0xff800000>; - }; - - memory@200000000 { - name = "memory"; - device_type = "memory"; - reg = <0x00000002 0x00000000 0x00000003 0x00000000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; - - timer { - compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - memory-controller@fff00000 { - compatible = "calxeda,ecx-2000-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - interrupts = <1 9 0xf04>; - reg = <0xfff11000 0x1000>, - <0xfff12000 0x2000>, - <0xfff14000 0x2000>, - <0xfff16000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; - }; - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi deleted file mode 100644 index ce5221c6b358..000000000000 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/ { - chosen { - bootargs = "console=ttyAMA0"; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x10000>; - interrupts = <0 83 4>; - dma-coherent; - calxeda,port-phys = < &combophy5 0>, <&combophy0 0>, - <&combophy0 1>, <&combophy0 2>, - <&combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, - <&gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - }; - - sdhci@ffe0e000 { - compatible = "calxeda,hb-sdhci"; - reg = <0xffe0e000 0x1000>; - interrupts = <0 90 4>; - clocks = <&eclk>; - status = "disabled"; - }; - - ipc@fff20000 { - compatible = "arm,pl320", "arm,primecell"; - reg = <0xfff20000 0x1000>; - interrupts = <0 7 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpioe: gpio@fff30000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff30000 0x1000>; - interrupts = <0 14 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiof: gpio@fff31000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff31000 0x1000>; - interrupts = <0 15 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiog: gpio@fff32000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff32000 0x1000>; - interrupts = <0 16 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpioh: gpio@fff33000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff33000 0x1000>; - interrupts = <0 17 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer@fff34000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xfff34000 0x1000>; - interrupts = <0 18 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@fff35000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0xfff35000 0x1000>; - interrupts = <0 19 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xfff36000 0x1000>; - interrupts = <0 20 4>; - clocks = <&pclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; - }; - - sregs@fff3c000 { - compatible = "calxeda,hb-sregs"; - reg = <0xfff3c000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333000>; - }; - - ddrpll: ddrpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x108>; - }; - - a9pll: a9pll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x100>; - }; - - a9periphclk: a9periphclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9periph-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - a9bclk: a9bclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9bus-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - emmcpll: emmcpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x10C>; - }; - - eclk: eclk { - #clock-cells = <0>; - compatible = "calxeda,hb-emmc-clock"; - clocks = <&emmcpll>; - reg = <0x114>; - }; - - pclk: pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <150000000>; - }; - }; - }; - - dma@fff3d000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfff3d000 0x1000>; - interrupts = <0 92 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4>, <0 78 4>, <0 79 4>; - dma-coherent; - }; - - ethernet@fff51000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff51000 0x1000>; - interrupts = <0 80 4>, <0 81 4>, <0 82 4>; - dma-coherent; - }; - - combophy0: combo-phy@fff58000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff58000 0x1000>; - phydev = <5>; - }; - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - }; -}; diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi deleted file mode 100644 index 9698801cbcfb..000000000000 --- a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common devices used in different OMAP boards - */ - -/ { - elpida_ECB240ABACN: lpddr2 { - compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts deleted file mode 100644 index 89495dd37358..000000000000 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the KZM9D board - * - * Copyright (C) 2013 Renesas Solutions Corp. - */ -/dts-v1/; - -#include "emev2.dtsi" -#include -#include -#include - -/ { - model = "EMEV2 KZM9D Board"; - compatible = "renesas,kzm9d", "renesas,emev2"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x8000000>; - }; - - aliases { - serial1 = &uart1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial1:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - one { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-1"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - two { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-2"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - three { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-3"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - four { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-4"; - linux,code = ; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ethernet@20000000 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <0x20000000 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; -}; - -&iic0 { - status = "okay"; -}; - -&iic1 { - status = "okay"; -}; - -&pfc { - uart1_pins: uart1 { - groups = "uart1_ctrl", "uart1_data"; - function = "uart1"; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi deleted file mode 100644 index ecfaa0b7523e..000000000000 --- a/arch/arm/boot/dts/emev2.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Emma Mobile EV2 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include -#include - -/ { - compatible = "renesas,emev2"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &iic0; - i2c1 = &iic1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <533000000>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <533000000>; - }; - }; - - gic: interrupt-controller@e0020000 { - compatible = "arm,pl390"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xe0028000 0x1000>, - <0xe0020000 0x0100>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - clocks@e0110000 { - compatible = "renesas,emev2-smu"; - reg = <0xe0110000 0x10000>; - #address-cells = <2>; - #size-cells = <0>; - - c32ki: c32ki { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - iic0_sclkdiv: iic0_sclkdiv@624,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x624 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - iic0_sclk: iic0_sclk@48c,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x48c 1>; - clocks = <&iic0_sclkdiv>; - #clock-cells = <0>; - }; - iic1_sclkdiv: iic1_sclkdiv@624,16 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x624 16>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - iic1_sclk: iic1_sclk@490,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x490 1>; - clocks = <&iic1_sclkdiv>; - #clock-cells = <0>; - }; - pll3_fo: pll3_fo { - compatible = "fixed-factor-clock"; - clocks = <&c32ki>; - clock-div = <1>; - clock-mult = <7000>; - #clock-cells = <0>; - }; - usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x65c 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x65c 16>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x660 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usia_u0_sclk: usia_u0_sclk@4a0,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; - }; - usib_u1_sclk: usib_u1_sclk@4b8,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4b8 1>; - clocks = <&usib_u1_sclkdiv>; - #clock-cells = <0>; - }; - usib_u2_sclk: usib_u2_sclk@4bc,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4bc 1>; - clocks = <&usib_u2_sclkdiv>; - #clock-cells = <0>; - }; - usib_u3_sclk: usib_u3_sclk@4c0,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4c0 1>; - clocks = <&usib_u3_sclkdiv>; - #clock-cells = <0>; - }; - sti_sclk: sti_sclk@528,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x528 1>; - clocks = <&c32ki>; - #clock-cells = <0>; - }; - }; - - timer@e0180000 { - compatible = "renesas,em-sti"; - reg = <0xe0180000 0x54>; - interrupts = ; - clocks = <&sti_sclk>; - clock-names = "sclk"; - }; - - uart0: serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = ; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; - }; - - uart1: serial@e1030000 { - compatible = "renesas,em-uart"; - reg = <0xe1030000 0x38>; - interrupts = ; - clocks = <&usib_u1_sclk>; - clock-names = "sclk"; - }; - - uart2: serial@e1040000 { - compatible = "renesas,em-uart"; - reg = <0xe1040000 0x38>; - interrupts = ; - clocks = <&usib_u2_sclk>; - clock-names = "sclk"; - }; - - uart3: serial@e1050000 { - compatible = "renesas,em-uart"; - reg = <0xe1050000 0x38>; - interrupts = ; - clocks = <&usib_u3_sclk>; - clock-names = "sclk"; - }; - - pfc: pinctrl@e0140200 { - compatible = "renesas,pfc-emev2"; - reg = <0xe0140200 0x100>; - }; - - gpio0: gpio@e0050000 { - compatible = "renesas,em-gio"; - reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@e0050080 { - compatible = "renesas,em-gio"; - reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@e0050100 { - compatible = "renesas,em-gio"; - reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@e0050180 { - compatible = "renesas,em-gio"; - reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@e0050200 { - compatible = "renesas,em-gio"; - reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 128 31>; - #gpio-cells = <2>; - ngpios = <31>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - iic0: i2c@e0070000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe0070000 0x28>; - interrupts = ; - clocks = <&iic0_sclk>; - clock-names = "sclk"; - status = "disabled"; - }; - - iic1: i2c@e10a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe10a0000 0x28>; - interrupts = ; - clocks = <&iic1_sclk>; - clock-names = "sclk"; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts deleted file mode 100644 index f23a25cce119..000000000000 --- a/arch/arm/boot/dts/en7523-evb.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/dts-v1/; - -/* Bootloader installs ATF here */ -/memreserve/ 0x80000000 0x200000; - -#include "en7523.dtsi" - -/ { - model = "Airoha EN7523 Evaluation Board"; - compatible = "airoha,en7523-evb", "airoha,en7523"; - - aliases { - serial0 = &uart1; - }; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - stdout-path = "serial0:115200n8"; - linux,usable-memory-range = <0x80200000 0x1fe00000>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi deleted file mode 100644 index b523a868c4ad..000000000000 --- a/arch/arm/boot/dts/en7523.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - npu_binary@84000000 { - no-map; - reg = <0x84000000 0xA00000>; - }; - - npu_flag@84B0000 { - no-map; - reg = <0x84B00000 0x100000>; - }; - - npu_pkt@85000000 { - no-map; - reg = <0x85000000 0x1A00000>; - }; - - npu_phyaddr@86B00000 { - no-map; - reg = <0x86B00000 0x100000>; - }; - - npu_rxdesc@86D00000 { - no-map; - reg = <0x86D00000 0x100000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - clock-frequency = <80000000>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - clock-frequency = <80000000>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - scu: system-controller@1fa20000 { - compatible = "airoha,en7523-scu"; - reg = <0x1fa20000 0x400>, - <0x1fb00000 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@9000000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x09000000 0x20000>, - <0x09080000 0x80000>, - <0x09400000 0x2000>, - <0x09500000 0x2000>, - <0x09600000 0x20000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - uart1: serial@1fbf0000 { - compatible = "ns16550"; - reg = <0x1fbf0000 0x30>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = ; - clock-frequency = <1843200>; - status = "okay"; - }; - - gpio0: gpio@1fbf0200 { - compatible = "airoha,en7523-gpio"; - reg = <0x1fbf0204 0x4>, - <0x1fbf0200 0x4>, - <0x1fbf0220 0x4>, - <0x1fbf0214 0x4>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio1: gpio@1fbf0270 { - compatible = "airoha,en7523-gpio"; - reg = <0x1fbf0270 0x4>, - <0x1fbf0260 0x4>, - <0x1fbf0264 0x4>, - <0x1fbf0278 0x4>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcie0: pcie@1fa91000 { - compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0x1fa91000 0x1000>; - reg-names = "port0"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&scu EN7523_CLK_PCIE>; - clock-names = "sys_ck0"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1fa92000 { - compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0x1fa92000 0x1000>; - reg-names = "port1"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&scu EN7523_CLK_PCIE>; - clock-names = "sys_ck1"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/ep7209.dtsi deleted file mode 100644 index 57bdad2c1994..000000000000 --- a/arch/arm/boot/dts/ep7209.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -/dts-v1/; - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Cirrus Logic EP7209"; - compatible = "cirrus,ep7209"; - - chosen { }; - - aliases { - gpio0 = &porta; - gpio1 = &portb; - gpio3 = &portd; - gpio4 = &porte; - serial0 = &uart1; - serial1 = &uart2; - spi0 = &spi; - timer0 = &timer1; - timer1 = &timer2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm720t"; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - clks: clks@80000000 { - #clock-cells = <1>; - compatible = "cirrus,ep7209-clk"; - reg = <0x80000000 0xc000>; - startup-frequency = <73728000>; - }; - - intc: intc@80000000 { - compatible = "cirrus,ep7209-intc"; - reg = <0x80000000 0x4000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - porta: gpio@80000000 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000000 0x1 0x80000040 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - portb: gpio@80000001 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000001 0x1 0x80000041 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - portd: gpio@80000003 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000003 0x1 0x80000043 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - porte: gpio@80000083 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000083 0x1 0x800000c3 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - syscon1: syscon@80000100 { - compatible = "cirrus,ep7209-syscon1", "syscon"; - reg = <0x80000100 0x80>; - }; - - bus: bus@80000180 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "cirrus,ep7209-bus", "simple-bus"; - clocks = <&clks CLPS711X_CLK_BUS>; - reg = <0x80000180 0x80>; - ranges = < - 0 0 0x00000000 0x10000000 - 1 0 0x10000000 0x10000000 - 2 0 0x20000000 0x10000000 - 3 0 0x30000000 0x10000000 - 4 0 0x40000000 0x10000000 - 5 0 0x50000000 0x10000000 - 6 0 0x60000000 0x0000c000 - 7 0 0x70000000 0x00000080 - >; - }; - - fb: fb@800002c0 { - compatible = "cirrus,ep7209-fb"; - reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; - clocks = <&clks CLPS711X_CLK_BUS>; - syscon = <&syscon1>; - status = "disabled"; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - clocks = <&clks CLPS711X_CLK_TIMER1>; - interrupts = <8>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - clocks = <&clks CLPS711X_CLK_TIMER2>; - interrupts = <9>; - }; - - pwm: pwm@80000400 { - compatible = "cirrus,ep7209-pwm"; - reg = <0x80000400 0x4>; - clocks = <&clks CLPS711X_CLK_PWM>; - #pwm-cells = <1>; - }; - - uart1: serial@80000480 { - compatible = "cirrus,ep7209-uart"; - reg = <0x80000480 0x80>; - interrupts = <12 13>; - clocks = <&clks CLPS711X_CLK_UART>; - syscon = <&syscon1>; - }; - - spi: spi@80000500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cirrus,ep7209-spi"; - reg = <0x80000500 0x4>; - interrupts = <15>; - clocks = <&clks CLPS711X_CLK_SPI>; - syscon = <&syscon3>; - status = "disabled"; - }; - - syscon2: syscon@80001100 { - compatible = "cirrus,ep7209-syscon2", "syscon"; - reg = <0x80001100 0x80>; - }; - - uart2: serial@80001480 { - compatible = "cirrus,ep7209-uart"; - reg = <0x80001480 0x80>; - interrupts = <28 29>; - clocks = <&clks CLPS711X_CLK_UART>; - syscon = <&syscon2>; - }; - - dai: dai@80002000 { - #sound-dai-cells = <0>; - compatible = "cirrus,ep7209-dai"; - reg = <0x80002000 0x604>; - clocks = <&clks CLPS711X_CLK_PLL>; - clock-names = "pll"; - interrupts = <32>; - syscon = <&syscon3>; - status = "disabled"; - }; - - syscon3: syscon@80002200 { - compatible = "cirrus,ep7209-syscon3", "syscon"; - reg = <0x80002200 0x40>; - }; - }; - - keypad: keypad { - compatible = "cirrus,ep7209-keypad"; - interrupt-parent = <&intc>; - interrupts = <16>; - syscon = <&syscon1>; - status = "disabled"; - }; - - mctrl: mctrl { - compatible = "cirrus,ep7209-mctrl-gpio"; - gpio,syscon-dev = <&syscon1 0 0>; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts deleted file mode 100644 index 7fb532f227af..000000000000 --- a/arch/arm/boot/dts/ep7211-edb7211.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ep7211.dtsi" -#include - -/ { - model = "Cirrus Logic EP7211 Development Board"; - compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x02000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0>; - brightness-levels = < - 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 - 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf - >; - default-brightness-level = <0x0>; - power-supply = <&blen>; - }; - - display: display { - model = "320x240x4"; - bits-per-pixel = <4>; - ac-prescale = <17>; - - display-timings { - native-mode = <&timing0>; - timing0: 320x240 { - hactive = <320>; - hback-porch = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vactive = <240>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <0>; - clock-frequency = <6500000>; - }; - }; - }; - - i2c: i2c { - compatible = "i2c-gpio"; - gpios = <&portd 4 GPIO_ACTIVE_HIGH>, - <&portd 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - i2c-gpio,scl-output-only; - #address-cells = <1>; - #size-cells = <0>; - }; - - lcddc: lcddc { - compatible = "regulator-fixed"; - regulator-name = "BACKLIGHT ENABLE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&portd 1 GPIO_ACTIVE_HIGH>; - }; - - blen: blen { - compatible = "regulator-fixed"; - regulator-name = "BACKLIGHT ENABLE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&portd 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&bus { - flash: nor@0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fb { - display = <&display>; - lcd-supply = <&lcddc>; - status = "okay"; -}; - -&portd { - lcden { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LCD ENABLE"; - }; -}; diff --git a/arch/arm/boot/dts/ep7211.dtsi b/arch/arm/boot/dts/ep7211.dtsi deleted file mode 100644 index 32a4e1237145..000000000000 --- a/arch/arm/boot/dts/ep7211.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ep7209.dtsi" - -/ { - model = "Cirrus Logic EP7211"; - compatible = "cirrus,ep7211", "cirrus,ep7209"; -}; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts deleted file mode 100644 index ad7a0850252a..000000000000 --- a/arch/arm/boot/dts/ethernut5.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ethernut5.dts - Device Tree file for Ethernut 5 board - * - * Copyright (C) 2012 egnite GmbH - */ -/dts-v1/; -#include "at91sam9xe.dtsi" - -/ { - model = "Ethernut 5"; - compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; - }; - - memory@20000000 { - reg = <0x20000000 0x08000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs>; - pinctrl-names = "default"; - - nand: nand@3 { - reg = <0x3 0x0 0x800000>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - root@0 { - label = "root"; - reg = <0x0 0x08000000>; - }; - - data@20000 { - label = "data"; - reg = <0x08000000 0x38000000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - pcf8563@50 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; -}; diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts deleted file mode 100644 index 6d519d02d190..000000000000 --- a/arch/arm/boot/dts/evk-pro3.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 - * - * Copyright (C) 2012 Telit, - * 2012 Fabio Porcedda - */ - -/dts-v1/; - -#include "ge863-pro3.dtsi" - -/ { - model = "Telit EVK-PRO3 for Telit GE863-PRO3"; - compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - }; - - ahb { - apb { - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart2: serial@fffb8000 { - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - -}; diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi deleted file mode 100644 index 597ade3e252f..000000000000 --- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd - */ - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region-mfc-left { - compatible = "shared-dma-pool"; - no-map; - size = <0x2400000>; - alignment = <0x100000>; - }; - - mfc_right: region-mfc-right { - compatible = "shared-dma-pool"; - no-map; - size = <0x800000>; - alignment = <0x100000>; - }; - }; -}; - -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/exynos-pinctrl.h deleted file mode 100644 index e3a6df95281c..000000000000 --- a/arch/arm/boot/dts/exynos-pinctrl.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung Exynos DTS pinctrl constants - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Linaro Ltd - * Author: Krzysztof Kozlowski - */ - -#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ -#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ - -#define EXYNOS_PIN_PULL_NONE 0 -#define EXYNOS_PIN_PULL_DOWN 1 -#define EXYNOS_PIN_PULL_UP 3 - -/* Pin function in power down mode */ -#define EXYNOS_PIN_PDN_OUT0 0 -#define EXYNOS_PIN_PDN_OUT1 1 -#define EXYNOS_PIN_PDN_INPUT 2 -#define EXYNOS_PIN_PDN_PREV 3 - -/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ -#define EXYNOS4_PIN_DRV_LV1 0 -#define EXYNOS4_PIN_DRV_LV2 2 -#define EXYNOS4_PIN_DRV_LV3 1 -#define EXYNOS4_PIN_DRV_LV4 3 - -/* Drive strengths for Exynos5260 */ -#define EXYNOS5260_PIN_DRV_LV1 0 -#define EXYNOS5260_PIN_DRV_LV2 1 -#define EXYNOS5260_PIN_DRV_LV4 2 -#define EXYNOS5260_PIN_DRV_LV6 3 - -/* - * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except - * GPIO_HSI block) - */ -#define EXYNOS5420_PIN_DRV_LV1 0 -#define EXYNOS5420_PIN_DRV_LV2 1 -#define EXYNOS5420_PIN_DRV_LV3 2 -#define EXYNOS5420_PIN_DRV_LV4 3 - -#define EXYNOS_PIN_FUNC_INPUT 0 -#define EXYNOS_PIN_FUNC_OUTPUT 1 -#define EXYNOS_PIN_FUNC_2 2 -#define EXYNOS_PIN_FUNC_3 3 -#define EXYNOS_PIN_FUNC_4 4 -#define EXYNOS_PIN_FUNC_5 5 -#define EXYNOS_PIN_FUNC_6 6 -#define EXYNOS_PIN_FUNC_EINT 0xf -#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT - -#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi deleted file mode 100644 index bc9a78f6d4b7..000000000000 --- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. - */ - -&pmu_system_controller { - poweroff: syscon-poweroff { - compatible = "syscon-poweroff"; - regmap = <&pmu_system_controller>; - offset = <0x330c>; /* PS_HOLD_CONTROL */ - mask = <0x5200>; /* reset value */ - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; /* SWRESET */ - mask = <0x1>; - }; -}; diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts deleted file mode 100644 index 660cc7fac4db..000000000000 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's ARTIK5 evaluation board - * which is based on Samsung Exynos3250 SoC. - */ - -/dts-v1/; -#include "exynos3250-artik5.dtsi" - -/ { - model = "Samsung ARTIK5 evaluation board"; - compatible = "samsung,artik5-eval", "samsung,artik5", - "samsung,exynos3250", "samsung,exynos3"; - - aliases { - mmc0 = &mshc_2; - }; -}; - -&mshc_2 { - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&ldo3_reg>; - card-detect-delay = <200>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&spi_0 { - status = "okay"; - cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; - - assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, - <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; - assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ - <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ - <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ - <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ - - ethernet@0 { - compatible = "asix,ax88796c"; - reg = <0x0>; - local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */ - interrupt-parent = <&gpx2>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <40000000>; - reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; - - controller-data { - samsung,spi-feedback-delay = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi deleted file mode 100644 index 3fdd922e635c..000000000000 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based ARTIK5 module device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's ARTIK5 module which is based on - * Samsung Exynos3250 SoC. - */ - -#include "exynos3250.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; - - aliases { - mmc0 = &mshc_0; - mmc1 = &mshc_1; - }; - - chosen { - stdout-path = &serial_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1f800000>; - }; - - firmware@205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205f000 0x1000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>, - <&cpu1 5 5>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>, - <&cpu1 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo7_reg>; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; -}; - -&cmu { - clocks = <&xusbxti>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx3>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps14_irq>; - reg = <0x66>; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - /* VDD_ALIVE15x */ - regulator-name = "VLDO1_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - /* VDDQM176 ~ VDDQM185 */ - regulator-name = "VLDO2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - /* - * VDD1_E106 ~ VDD1_E111 - * DVDD_RTC_AP, DVDD_MMC2_AP - */ - regulator-name = "VLDO3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - /* AVDD_PLL1120 ~ AVDD_PLL11201 */ - regulator-name = "VLDO4_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */ - regulator-name = "VLDO5_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* VDD_USB, VDD10_HSIC */ - regulator-name = "VLDO6_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - /* - * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2, - * AVDD_ADC, AVDD_ABB_0, M4S_VDD18 - */ - regulator-name = "VLDO7_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - /* AVDD33_UOTG */ - regulator-name = "VLDO8_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - /* VDDQ_E86 ~ VDDQ_E105*/ - regulator-name = "VLDO9_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VLDO10_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo11_reg: LDO11 { - /* VDD74 ~ VDD75 */ - regulator-name = "VLDO11_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - /* VDD72 ~ VDD73 */ - regulator-name = "VLDO12_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VLDO13_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VLDO14_2.7V"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VLDO_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VLDO16_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VLDO17_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo18_reg: LDO18 { - /* DVDD_MMC2_AP */ - regulator-name = "VLDO18_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VLDO19_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VLDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VLDO21_1.25V"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VLDO22_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo23_reg: LDO23 { - /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */ - regulator-name = "VLDO23_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "VLDO24_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "VLDO25_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - /* VDD_MIF */ - regulator-name = "VBUCK1_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - /* VDD_CPU */ - regulator-name = "VBUCK2_1.2V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - /* VDD_G3D */ - regulator-name = "VBUCK3_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VBUCK4_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "VBUCK5_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&mshc_0 { - non-removable; - cap-mmc-highspeed; - card-detect-delay = <200>; - vmmc-supply = <&ldo12_reg>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&mshc_1 { - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - non-removable; - keep-power-in-suspend; - fifo-depth = <0x40>; - vqmmc-supply = <&ldo11_reg>; - /* - * Voltage negotiation is broken for the SDIO periph so we - * can't actually set the voltage here. - * vmmc-supply = <&ldo23_reg>; - */ - card-detect-delay = <500>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>; - bus-width = <4>; - status = "okay"; -}; - -&pinctrl_1 { - bten: bten-pins { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; - - wlanen: wlanen-pins { - samsung,pins = "gpx2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <1>; - }; - - s2mps14_irq: s2mps14-irq-pins { - samsung,pins = "gpx3-5"; - samsung,pin-pud = ; - }; - - bthostwake: bthostwake-pins { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; - - btwake: btwake-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - pinctrl-names = "default"; - pinctrl-0 = <&bten &btwake &bthostwake>; - max-speed = <3000000>; - shutdown-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx3 6 GPIO_ACTIVE_HIGH>; - clocks = <&s2mps14_osc S2MPS11_CLK_BT>; - }; -}; - -&tmu { - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts deleted file mode 100644 index 2de877d4ccc5..000000000000 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ /dev/null @@ -1,644 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based Monk board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Monk board which is based on - * Samsung Exynos3250 SoC. - */ - -/dts-v1/; -#include "exynos3250.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Monk board"; - compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; - - aliases { - i2c7 = &i2c_max77836; - mmc0 = &mshc_0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205f000 0x1000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - vemmc_reg: voltage-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "V_EMMC_2.8V-fixed"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - i2c_max77836: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - max77836: pmic@25 { - compatible = "maxim,max77836"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - reg = <0x25>; - wakeup-source; - - extcon { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - safeout_reg: SAFEOUT { - regulator-name = "SAFEOUT"; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <45000>; - regulator-max-microamp = <475000>; - regulator-boot-on; - }; - - motor_reg: LDO1 { - regulator-name = "MOT_2.7V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <2700000>; - }; - - LDO2 { - regulator-name = "UNUSED_LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; - }; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_reg>; - min-microvolt = <1100000>; - max-microvolt = <2700000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Correspond to 500MHz at freq_table */ - cooling-device = <&cpu0 5 5>, - <&cpu1 5 5>; - }; - map1 { - /* Correspond to 200MHz at freq_table */ - cooling-device = <&cpu0 8 8>, - <&cpu1 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; - - thermistor-ap { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 1>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&cmu { - clocks = <&xusbxti>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - vbus-supply = <&safeout_reg>; - status = "okay"; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - reg = <0x66>; - wakeup-source; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VAP_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VAP_M1_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_AP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VAP_AVDD_PLL1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VAP_PLL_ISO_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VAP_MIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VAP_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VAP_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "V_LPDDR_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "UNUSED_LDO10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "V_EMMC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VSENSOR_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "UNUSED_LDO14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "LCD_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "UNUSED_LDO17"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "UNUSED_LDO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "LCD_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "UNUSED_LDO21"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "UNUSED_LDO22"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "UNUSED_LDO23"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "UNUSED_LDO24"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VAP_MIF_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VAP_ARM_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VAP_INT3D_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VCC_SUB_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max77836-battery"; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reg = <0x36>; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&mshc_0 { - #address-cells = <1>; - #size-cells = <0>; - broken-cd; - non-removable; - cap-mmc-highspeed; - mmc-hs200-1_8v; - card-detect-delay = <200>; - vmmc-supply = <&vemmc_reg>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo7_reg>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, DOWN); - PIN_SLP(gpa0-1, INPUT, DOWN); - PIN_SLP(gpa0-2, INPUT, DOWN); - PIN_SLP(gpa0-3, INPUT, DOWN); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, DOWN); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, PREV, NONE); - PIN_SLP(gpb-1, PREV, NONE); - PIN_SLP(gpb-2, PREV, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&initial1 &sleep1>; - - initial1: initial-state { - PIN_IN(gpk2-0, DOWN, LV1); - PIN_IN(gpk2-1, DOWN, LV1); - PIN_IN(gpk2-2, DOWN, LV1); - PIN_IN(gpk2-3, DOWN, LV1); - PIN_IN(gpk2-4, DOWN, LV1); - PIN_IN(gpk2-5, DOWN, LV1); - PIN_IN(gpk2-6, DOWN, LV1); - }; - - sleep1: sleep-state { - PIN_SLP(gpe0-0, PREV, NONE); - PIN_SLP(gpe0-1, PREV, NONE); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, DOWN); - PIN_SLP(gpe0-4, PREV, NONE); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, PREV, NONE); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, INPUT, DOWN); - PIN_SLP(gpe1-4, INPUT, DOWN); - PIN_SLP(gpe1-5, INPUT, DOWN); - PIN_SLP(gpe1-6, INPUT, DOWN); - PIN_SLP(gpe1-7, INPUT, NONE); - - PIN_SLP(gpe2-0, INPUT, NONE); - PIN_SLP(gpe2-1, INPUT, NONE); - PIN_SLP(gpe2-2, INPUT, NONE); - - PIN_SLP(gpk0-0, INPUT, DOWN); - PIN_SLP(gpk0-1, INPUT, DOWN); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, INPUT, DOWN); - PIN_SLP(gpk0-4, INPUT, DOWN); - PIN_SLP(gpk0-5, INPUT, DOWN); - PIN_SLP(gpk0-6, INPUT, DOWN); - PIN_SLP(gpk0-7, INPUT, DOWN); - - PIN_SLP(gpk1-0, PREV, NONE); - PIN_SLP(gpk1-1, PREV, NONE); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, DOWN); - PIN_SLP(gpm1-3, INPUT, DOWN); - PIN_SLP(gpm1-4, INPUT, DOWN); - PIN_SLP(gpm1-5, INPUT, DOWN); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, DOWN); - PIN_SLP(gpm2-1, INPUT, DOWN); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, INPUT, DOWN); - PIN_SLP(gpm3-1, INPUT, DOWN); - PIN_SLP(gpm3-2, INPUT, DOWN); - PIN_SLP(gpm3-3, INPUT, DOWN); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - }; -}; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi deleted file mode 100644 index 07828551d4b3..000000000000 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ /dev/null @@ -1,543 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device - * tree nodes in this file. - */ - -#include "exynos-pinctrl.h" - -#define PIN_IN(_pin, _pull, _drv) \ - pin- ## _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_SLP(_pin, _mode, _pull) \ - pin- ## _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -&pinctrl_0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus-pins { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus-pins { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus-pins { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus-pins { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk-pins { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe2: gpe2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk0: gpk0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs-pins { - samsung,pins = "gpk0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io-pins { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active-pins { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle-pins { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0-pins { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1-pins { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart-pins { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts deleted file mode 100644 index 88fb3e68ff02..000000000000 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ /dev/null @@ -1,921 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based Rinato board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Rinato board which is based on - * Samsung Exynos3250 SoC. - */ - -/dts-v1/; -#include "exynos3250.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Rinato board"; - compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; - chassis-type = "watch"; - - aliases { - i2c7 = &i2c_max77836; - mmc0 = &mshc_0; - mmc1 = &mshc_1; - }; - - chosen { - stdout-path = &serial_1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205f000 0x1000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - wlan_pwrseq: mshc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; - }; - - i2c_max77836: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - max77836: pmic@25 { - compatible = "maxim,max77836"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - reg = <0x25>; - wakeup-source; - - extcon { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - safeout_reg: SAFEOUT { - regulator-name = "SAFEOUT"; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <45000>; - regulator-max-microamp = <475000>; - regulator-boot-on; - }; - - motor_reg: LDO1 { - regulator-name = "MOT_2.7V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <2700000>; - }; - - LDO2 { - regulator-name = "UNUSED_LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; - }; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_reg>; - min-microvolt = <1100000>; - max-microvolt = <2700000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>, - <&cpu1 5 5>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>, - <&cpu1 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; - - thermistor-ap { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 1>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_lcd0 { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mcuisp { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_isp { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peril { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cmu { - clocks = <&xusbxti>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safeout_reg>; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&dsi_0 { - vddcore-supply = <&ldo6_reg>; - vddio-supply = <&ldo6_reg>; - samsung,burst-clock-frequency = <250000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - panel@0 { - compatible = "samsung,s6e63j0x03"; - reg = <0>; - vdd3-supply = <&ldo16_reg>; - vci-supply = <&ldo20_reg>; - reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; - te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&fimd { - status = "okay"; - - i80-if-timings { - cs-setup = <0>; - wr-setup = <0>; - wr-active = <1>; - wr-hold = <0>; - }; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - reg = <0x66>; - wakeup-source; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VAP_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "VAP_M1_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_AP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VAP_AVDD_PLL1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VAP_PLL_ISO_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "VAP_VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VAP_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VAP_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "V_LPDDR_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "UNUSED_LDO10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "V_EMMC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_AVDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "UNUSED_LDO14"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "LCD_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "V_IRLED_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_AF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "LCD_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo21_reg: LDO21 { - regulator-name = "CAM_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo22_reg: LDO22 { - regulator-name = "CAM_DVDD_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo23_reg: LDO23 { - regulator-name = "HRM_VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "HRM_VCC_3.3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "VAP_MIF_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VAP_ARM_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VAP_INT3D_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VCC_SUB_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max77836-battery"; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reg = <0x36>; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&jpeg { - status = "okay"; -}; - -&mshc_0 { - broken-cd; - non-removable; - cap-mmc-highspeed; - mmc-hs200-1_8v; - card-detect-delay = <200>; - vmmc-supply = <&ldo12_reg>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&mshc_1 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - non-removable; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; - bus-width = <4>; - - mmc-pwrseq = <&wlan_pwrseq>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - clocks = <&s2mps14_osc S2MPS11_CLK_BT>; - }; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo7_reg>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&initial0 &sleep0>; - - initial0: initial-state { - PIN_IN(gpa1-4, DOWN, LV1); - PIN_IN(gpa1-5, DOWN, LV1); - - PIN_IN(gpc0-0, DOWN, LV1); - PIN_IN(gpc0-1, DOWN, LV1); - PIN_IN(gpc0-2, DOWN, LV1); - PIN_IN(gpc0-3, DOWN, LV1); - PIN_IN(gpc0-4, DOWN, LV1); - - PIN_IN(gpd0-0, DOWN, LV1); - PIN_IN(gpd0-1, DOWN, LV1); - }; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, DOWN); - PIN_SLP(gpa0-1, INPUT, DOWN); - PIN_SLP(gpa0-2, INPUT, DOWN); - PIN_SLP(gpa0-3, INPUT, DOWN); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, DOWN); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, PREV, NONE); - PIN_SLP(gpb-1, PREV, NONE); - PIN_SLP(gpb-2, PREV, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&initial1 &sleep1>; - - initial1: initial-state { - PIN_IN(gpe0-6, DOWN, LV1); - PIN_IN(gpe0-7, DOWN, LV1); - - PIN_IN(gpe1-0, DOWN, LV1); - PIN_IN(gpe1-3, DOWN, LV1); - PIN_IN(gpe1-4, DOWN, LV1); - PIN_IN(gpe1-5, DOWN, LV1); - PIN_IN(gpe1-6, DOWN, LV1); - - PIN_IN(gpk2-0, DOWN, LV1); - PIN_IN(gpk2-1, DOWN, LV1); - PIN_IN(gpk2-2, DOWN, LV1); - PIN_IN(gpk2-3, DOWN, LV1); - PIN_IN(gpk2-4, DOWN, LV1); - PIN_IN(gpk2-5, DOWN, LV1); - PIN_IN(gpk2-6, DOWN, LV1); - - PIN_IN(gpm0-0, DOWN, LV1); - PIN_IN(gpm0-1, DOWN, LV1); - PIN_IN(gpm0-2, DOWN, LV1); - PIN_IN(gpm0-3, DOWN, LV1); - PIN_IN(gpm0-4, DOWN, LV1); - PIN_IN(gpm0-5, DOWN, LV1); - PIN_IN(gpm0-6, DOWN, LV1); - PIN_IN(gpm0-7, DOWN, LV1); - - PIN_IN(gpm1-0, DOWN, LV1); - PIN_IN(gpm1-1, DOWN, LV1); - PIN_IN(gpm1-2, DOWN, LV1); - PIN_IN(gpm1-3, DOWN, LV1); - PIN_IN(gpm1-4, DOWN, LV1); - PIN_IN(gpm1-5, DOWN, LV1); - PIN_IN(gpm1-6, DOWN, LV1); - - PIN_IN(gpm2-0, DOWN, LV1); - PIN_IN(gpm2-1, DOWN, LV1); - - PIN_IN(gpm3-0, DOWN, LV1); - PIN_IN(gpm3-1, DOWN, LV1); - PIN_IN(gpm3-2, DOWN, LV1); - PIN_IN(gpm3-3, DOWN, LV1); - PIN_IN(gpm3-4, DOWN, LV1); - - PIN_IN(gpm4-1, DOWN, LV1); - PIN_IN(gpm4-2, DOWN, LV1); - PIN_IN(gpm4-3, DOWN, LV1); - PIN_IN(gpm4-4, DOWN, LV1); - PIN_IN(gpm4-5, DOWN, LV1); - PIN_IN(gpm4-6, DOWN, LV1); - PIN_IN(gpm4-7, DOWN, LV1); - }; - - sleep1: sleep-state { - PIN_SLP(gpe0-0, PREV, NONE); - PIN_SLP(gpe0-1, PREV, NONE); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, UP); - PIN_SLP(gpe0-4, INPUT, DOWN); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, PREV, NONE); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, INPUT, DOWN); - PIN_SLP(gpe1-4, INPUT, DOWN); - PIN_SLP(gpe1-5, INPUT, DOWN); - PIN_SLP(gpe1-6, INPUT, DOWN); - PIN_SLP(gpe1-7, INPUT, NONE); - - PIN_SLP(gpe2-0, INPUT, NONE); - PIN_SLP(gpe2-1, INPUT, NONE); - PIN_SLP(gpe2-2, INPUT, NONE); - - PIN_SLP(gpk0-0, INPUT, DOWN); - PIN_SLP(gpk0-1, INPUT, DOWN); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, INPUT, DOWN); - PIN_SLP(gpk0-4, INPUT, DOWN); - PIN_SLP(gpk0-5, INPUT, DOWN); - PIN_SLP(gpk0-6, INPUT, DOWN); - PIN_SLP(gpk0-7, INPUT, DOWN); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, INPUT, DOWN); - PIN_SLP(gpk1-4, INPUT, DOWN); - PIN_SLP(gpk1-5, INPUT, DOWN); - PIN_SLP(gpk1-6, INPUT, DOWN); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, DOWN); - PIN_SLP(gpm1-3, INPUT, DOWN); - PIN_SLP(gpm1-4, INPUT, DOWN); - PIN_SLP(gpm1-5, INPUT, DOWN); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, DOWN); - PIN_SLP(gpm2-1, INPUT, DOWN); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, INPUT, DOWN); - PIN_SLP(gpm3-1, INPUT, DOWN); - PIN_SLP(gpm3-2, INPUT, DOWN); - PIN_SLP(gpm3-3, INPUT, DOWN); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - }; -}; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi deleted file mode 100644 index 3f1015edab43..000000000000 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ /dev/null @@ -1,950 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4-cpu-thermal.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos3250"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - spi0 = &spi_0; - spi1 = &spi_1; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_dmc CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - - bus_dmc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <800000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <800000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <800000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000>; - }; - }; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_isp: bus-isp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_isp_opp_table>; - status = "disabled"; - - bus_isp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - }; - - bus_lcd0: bus-lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_160>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mcuisp: bus-mcuisp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; - clock-names = "bus"; - operating-points-v2 = <&bus_mcuisp_opp_table>; - status = "disabled"; - - bus_mcuisp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_peril: bus-peril { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peril_opp_table>; - status = "disabled"; - - bus_peril_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cmu CLK_ARM_CLK>; - clock-names = "cpu"; - #cooling-cells = <2>; - - operating-points = < - 1000000 1150000 - 900000 1112500 - 800000 1075000 - 700000 1037500 - 600000 1000000 - 500000 962500 - 400000 925000 - 300000 887500 - 200000 850000 - 100000 850000 - >; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cmu CLK_ARM_CLK>; - clock-names = "cpu"; - #cooling-cells = <2>; - - operating-points = < - 1000000 1150000 - 900000 1112500 - 800000 1075000 - 700000 1037500 - 600000 1000000 - 500000 962500 - 400000 925000 - 300000 887500 - 200000 850000 - 100000 850000 - >; - }; - }; - - xusbxti: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xusbxti"; - }; - - xxti: clock-1 { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xxti"; - }; - - xtcxo: clock-2 { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xtcxo"; - }; - - bus_leftbus_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <900000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - opp-microvolt = <900000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@3f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x3f000 0x1000>; - }; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sys_reg: syscon@10010000 { - compatible = "samsung,exynos3-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - clock-names = "clkout8"; - clocks = <&cmu CLK_FIN_PLL>; - #clock-cells = <1>; - - mipi_phy: mipi-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - }; - }; - - pd_cam: power-domain@10023c00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c00 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; - - pd_mfc: power-domain@10023c40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c40 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_g3d: power-domain@10023c60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c60 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_lcd0: power-domain@10023c80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c80 0x20>; - #power-domain-cells = <0>; - label = "LCD0"; - }; - - pd_isp: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023ca0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos3250-cmu"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, - <&cmu CLK_MOUT_ACLK_266_SUB>; - assigned-clock-parents = <&cmu CLK_FIN_PLL>, - <&cmu CLK_FIN_PLL>; - }; - - cmu_dmc: clock-controller@105c0000 { - compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105c0000 0x2000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = , - ; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; - }; - - tmu: tmu@100c0000 { - compatible = "samsung,exynos3250-tmu"; - reg = <0x100c0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x2000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = ; - }; - - timer@10050000 { - compatible = "samsung,exynos3250-mct", - "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos3250-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupts = ; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos3250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - jpeg: codec@11830000 { - compatible = "samsung,exynos3250-jpeg"; - reg = <0x11830000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; - clock-names = "jpeg", "sclk"; - power-domains = <&pd_cam>; - assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; - assigned-clock-rates = <0>, <150000000>; - assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; - iommus = <&sysmmu_jpeg>; - status = "disabled"; - }; - - sysmmu_jpeg: sysmmu@11a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a60000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos3250-fimd"; - reg = <0x11c00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , - , - ; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; - - dsi_0: dsi@11c80000 { - compatible = "samsung,exynos3250-mipi-dsi"; - reg = <0x11c80000 0x10000>; - interrupts = ; - samsung,phy-type = <0>; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: usb@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = ; - clocks = <&cmu CLK_USBOTG>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mmc@12510000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mmc@12520000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mmc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - exynos_usbphy: usb-phy@125b0000 { - compatible = "samsung,exynos3250-usb2-phy"; - reg = <0x125b0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - pdma0: dma-controller@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pdma1: dma-controller@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos3250-adc"; - reg = <0x126c0000 0x100>; - interrupts = ; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - gpu: gpu@13000000 { - compatible = "samsung,exynos4210-mali", "arm,mali-400"; - reg = <0x13000000 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - clocks = <&cmu CLK_G3D>, - <&cmu CLK_SCLK_G3D>; - clock-names = "bus", "core"; - power-domains = <&pd_g3d>; - status = "disabled"; - /* TODO: operating points for DVFS, assigned clock as 134 MHz */ - }; - - mfc: codec@13400000 { - compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7"; - reg = <0x13400000 0x10000>; - interrupts = ; - clock-names = "mfc", "sclk_mfc"; - clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; - power-domains = <&pd_mfc>; - iommus = <&sysmmu_mfc>; - }; - - sysmmu_mfc: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = ; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data &uart0_fctl>; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = ; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = ; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138a0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138b0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138c0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138d0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = ; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = ; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&i2s2_bus>; - pinctrl-names = "default"; - status = "disabled"; - }; - - pwm: pwm@139d0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139d0000 0x1000>; - interrupts = , - , - , - , - ; - #pwm-cells = <3>; - status = "disabled"; - }; - - ppmu_dmc0: ppmu@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - status = "disabled"; - }; - - ppmu_dmc1: ppmu@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - status = "disabled"; - }; - - ppmu_cpu: ppmu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - status = "disabled"; - }; - - ppmu_rightbus: ppmu@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&cmu CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&cmu CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_camif: ppmu@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&cmu CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_lcd0: ppmu@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&cmu CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_fsys: ppmu@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - clocks = <&cmu CLK_PPMUFILE>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_g3d: ppmu@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&cmu CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc: ppmu@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&cmu CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; - }; -}; - -#include "exynos3250-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi deleted file mode 100644 index 27a1a8952665..000000000000 --- a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4 thermal zone - * - * Copyright (c) 2014 Lukasz Majewski - */ - -#include - -/ { -thermal-zones { - cpu_thermal: cpu-thermal { - thermal-sensors = <&tmu>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <95000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - }; - map1 { - trip = <&cpu_alert1>; - }; - }; - }; -}; -}; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi deleted file mode 100644 index f775b9377a38..000000000000 --- a/arch/arm/boot/dts/exynos4.dtsi +++ /dev/null @@ -1,1007 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4 SoC series common device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular - * SoCs from Exynos4 series can include this file and provide values for SoCs - * specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional - * nodes can be added to this file. - */ - -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - csis0 = &csis_0; - csis1 = &csis_1; - fimc0 = &fimc_0; - fimc1 = &fimc_1; - fimc2 = &fimc_2; - fimc3 = &fimc_3; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - }; - - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - status = "disabled"; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock_audss: clock-controller@3810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0c>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, - <&clock CLK_SCLK_AUDIO0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", - "sclk_pcm_in"; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; - dma-names = "tx", "rx", "tx-sec"; - samsung,idma-addr = <0x03000000>; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - scu: snoop-control-unit@10500000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x10500000 0x2000>; - }; - - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - - pd_mfc: power-domain@10023c40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c40 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_g3d: power-domain@10023c60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c60 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_lcd0: power-domain@10023c80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c80 0x20>; - #power-domain-cells = <0>; - label = "LCD0"; - }; - - pd_tv: power-domain@10023c20 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c20 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_lcd0>; - label = "TV"; - }; - - pd_cam: power-domain@10023c00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023c00 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; - - pd_gps: power-domain@10023ce0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023ce0 0x20>; - #power-domain-cells = <0>; - label = "GPS"; - }; - - pd_gps_alive: power-domain@10023d00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023d00 0x20>; - #power-domain-cells = <0>; - label = "GPS alive"; - }; - - gic: interrupt-controller@10490000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10490000 0x10000>, <0x10480000 0x10000>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x10440000 0x1000>; - }; - - sys_reg: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4210-pmu", "simple-mfd", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - - mipi_phy: mipi-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - }; - }; - - dsi_0: dsi@11c80000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11c80000 0x10000>; - interrupts = ; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "sclk_mipi"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - camera: camera@11800000 { - compatible = "samsung,fimc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - - fimc_0: fimc@11800000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc0>; - status = "disabled"; - }; - - fimc_1: fimc@11810000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11810000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc1>; - status = "disabled"; - }; - - fimc_2: fimc@11820000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11820000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc2>; - status = "disabled"; - }; - - fimc_3: fimc@11830000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11830000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc3>; - status = "disabled"; - }; - - csis_0: csis@11880000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x4000>; - interrupts = ; - clocks = <&clock CLK_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - clock-names = "csis", "sclk_csis"; - bus-width = <4>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 0>; - phy-names = "csis"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - csis_1: csis@11890000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11890000 0x4000>; - interrupts = ; - clocks = <&clock CLK_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - clock-names = "csis", "sclk_csis"; - bus-width = <2>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 2>; - phy-names = "csis"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupt-parent = <&pmu_system_controller>; - interrupts = , - ; - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - keypad: keypad@100a0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100a0000 0x100>; - interrupts = ; - clocks = <&clock CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - sdhci_0: mmc@12510000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12510000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_1: mmc@12520000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12520000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_2: mmc@12530000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12530000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_3: mmc@12540000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12540000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - exynos_usbphy: usb-phy@125b0000 { - compatible = "samsung,exynos4210-usb2-phy"; - reg = <0x125b0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - hsotg: usb@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = ; - clocks = <&clock CLK_USB_DEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - ehci: usb@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = ; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>; - phy-names = "host", "hsic0", "hsic1"; - }; - - ohci: usb@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = ; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - phys = <&exynos_usbphy 1>; - phy-names = "host"; - }; - - gpu: gpu@13000000 { - compatible = "samsung,exynos4210-mali", "arm,mali-400"; - reg = <0x13000000 0x10000>; - /* - * CLK_G3D is not actually bus clock but a IP-level clock. - * The bus clock is not described in hardware manual. - */ - clocks = <&clock CLK_G3D>, - <&clock CLK_SCLK_G3D>; - clock-names = "bus", "core"; - power-domains = <&pd_g3d>; - status = "disabled"; - }; - - i2s1: i2s@13960000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13960000 0x100>; - clocks = <&clock CLK_I2S1>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - dmas = <&pdma1 12>, <&pdma1 11>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - clocks = <&clock CLK_I2S2>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = ; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; - clock-names = "mfc", "sclk_mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 17>, <&pdma0 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138a0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138b0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138c0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138d0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - i2c_8: i2c@138e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x138e0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - - hdmi_i2c_phy: hdmi-phy@38 { - compatible = "samsung,exynos4210-hdmiphy"; - reg = <0x38>; - }; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = ; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = ; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = ; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - pwm: pwm@139d0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139d0000 0x1000>; - interrupts = , - , - , - , - ; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pdma0: dma-controller@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pdma1: dma-controller@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - mdma1: dma-controller@12850000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12850000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; - - tmu: tmu@100c0000 { - interrupt-parent = <&combiner>; - reg = <0x100c0000 0x100>; - interrupts = <2 4>; - status = "disabled"; - #thermal-sensor-cells = <0>; - }; - - jpeg_codec: jpeg-codec@11840000 { - compatible = "samsung,exynos4210-jpeg"; - reg = <0x11840000 0x1000>; - interrupts = ; - clocks = <&clock CLK_JPEG>; - clock-names = "jpeg"; - power-domains = <&pd_cam>; - iommus = <&sysmmu_jpeg>; - }; - - rotator: rotator@12810000 { - compatible = "samsung,exynos4210-rotator"; - reg = <0x12810000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - hdmi: hdmi@12d00000 { - compatible = "samsung,exynos4210-hdmi"; - reg = <0x12d00000 0x70000>; - interrupts = ; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, - <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - phy = <&hdmi_i2c_phy>; - power-domains = <&pd_tv>; - samsung,syscon-phandle = <&pmu_system_controller>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmicec: cec@100b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x100b0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@12c10000 { - compatible = "samsung,exynos4210-mixer"; - interrupts = ; - reg = <0x12c10000 0x2100>, <0x12c00000 0x300>; - power-domains = <&pd_tv>; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - ppmu_dmc0: ppmu@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - clocks = <&clock CLK_PPMUDMC0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_dmc1: ppmu@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - clocks = <&clock CLK_PPMUDMC1>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_cpu: ppmu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - clocks = <&clock CLK_PPMUCPU>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_rightbus: ppmu@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&clock CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&clock CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_camif: ppmu@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&clock CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_lcd0: ppmu@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&clock CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_fsys: ppmu@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - status = "disabled"; - }; - - ppmu_image: ppmu@12aa0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12aa0000 0x2000>; - clocks = <&clock CLK_PPMUIMAGE>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_tv: ppmu@12e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12e40000 0x2000>; - clocks = <&clock CLK_PPMUTV>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_g3d: ppmu@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&clock CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc_left: ppmu@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&clock CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc_right: ppmu@13670000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13670000 0x2000>; - clocks = <&clock CLK_PPMUMFC_R>; - clock-names = "ppmu"; - status = "disabled"; - }; - - sysmmu_mfc_l: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@13630000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13630000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@12e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12e20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - power-domains = <&pd_tv>; - #iommu-cells = <0>; - }; - - sysmmu_fimc0: sysmmu@11a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc1: sysmmu@11a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc2: sysmmu@11a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc3: sysmmu@11a50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg: sysmmu@11a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@12a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12a30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, - <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_fimd0: sysmmu@11e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = ; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - - prng: rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - }; -}; - -#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts deleted file mode 100644 index 37cd4dde53e4..000000000000 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ /dev/null @@ -1,860 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2020 Stenkin Evgeniy - * Copyright (c) 2020 Paul Cercueil - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include "exynos4412-ppmu-common.dtsi" - -#include -#include - -/ { - model = "Samsung Galaxy S2 (GT-I9100)"; - compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4"; - chassis-type = "handset"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - mmc0 = &sdhci_0; - mmc1 = &sdhci_2; - mmc2 = &sdhci_3; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - vemmc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - tsp_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "TSP_FIXED_VOLTAGES"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - cam_af_28v_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "8M_AF_2.8V_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_en_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_IO_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_12v_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "8M_1.2V_EN"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vt_core_15v_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VT_CORE_1.5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-vol-down { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume down"; - debounce-interval = <10>; - }; - - key-vol-up { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume up"; - debounce-interval = <10>; - }; - - key-power { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - key-ok { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "ok"; - debounce-interval = <10>; - }; - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; - }; - - i2c_max17042_fuel: i2c-gpio-0 { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - - battery@36 { - compatible = "maxim,max17042"; - - interrupt-parent = <&gpx2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&max17042_fuel_irq>; - pinctrl-names = "default"; - - reg = <0x36>; - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - }; - }; - - i2c_s5k5baf: i2c-gpio-1 { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - sda-gpios = <&gpc1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpc1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - - image-sensor@2d { - compatible = "samsung,s5k5baf"; - reg = <0x2d>; - vdda-supply = <&cam_io_en_reg>; - vddreg-supply = <&vt_core_15v_reg>; - vddio-supply = <&vtcam_reg>; - clocks = <&camera 0>; - clock-names = "mclk"; - stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>; - rstn-gpios = <&gpl2 1 GPIO_ACTIVE_LOW>; - clock-frequency = <24000000>; - - port { - s5k5bafx_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; - }; - - spi-3 { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - num-chipselects = <1>; - cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; - sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; - - lcd@0 { - compatible = "samsung,ld9040"; - reg = <0>; - - spi-max-frequency = <1200000>; - - vdd3-supply = <&vmipi_reg>; - vci-supply = <&vcclcd_reg>; - - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay = <10>; - reset-delay = <10>; - - panel-width-mm = <90>; - panel-height-mm = <154>; - - display-timings { - timing { - clock-frequency = <23492370>; - hactive = <480>; - vactive = <800>; - hback-porch = <16>; - hfront-porch = <16>; - vback-porch = <2>; - vfront-porch = <28>; - hsync-len = <2>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_dpi_ep>; - }; - }; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on max8997 PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&camera { - pinctrl-0 = <&cam_port_a_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>, <&clock CLK_MOUT_CAM1>; - assigned-clock-parents = <&clock CLK_XUSBXTI>, <&clock CLK_XUSBXTI>; -}; - -&csis_1 { - status = "okay"; - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - clock-frequency = <160000000>; - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - csis1_ep: endpoint { - remote-endpoint = <&s5k5bafx_ep>; - data-lanes = <1>; - samsung,csis-hs-settle = <6>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&varm_breg>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 4 4>; - }; - }; -}; - -&ehci { - status = "okay"; - - phys = <&exynos_usbphy 1>; - phy-names = "host"; -}; - -&exynos_usbphy { - status = "okay"; - - vbus-supply = <&safe1_sreg>; -}; - -&fimc_0 { - status = "okay"; - - assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_1 { - /* Back camera not implemented */ - status = "disabled"; - - assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_2 { - status = "okay"; - - assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_3 { - /* Back camera not implemented */ - status = "disabled"; - - assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimd { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - samsung,invert-vden; - samsung,invert-vclk; - - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - - port@3 { - reg = <3>; - - fimd_dpi_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; -}; - -&gpu { - status = "okay"; - - mali-supply = <&vg3d_breg>; -}; - -&hsotg { - status = "okay"; - - dr_mode = "otg"; - vusb_d-supply = <&vusb_reg>; - vusb_a-supply = <&vusbdac_reg>; -}; - -&i2c_3 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c_5 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - - pmic@66 { - compatible = "maxim,max8997-pmic"; - reg = <0x66>; - - interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>, - <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>, - <&gpl0 0 GPIO_ACTIVE_HIGH>; - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, - <950000>, <900000>, - <1100000>, <1000000>, - <950000>, <900000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; - pinctrl-names = "default"; - - charger-supply = <&charger_reg>; - - regulators { - vadc_reg: LDO1 { - regulator-name = "VADC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - }; - valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - }; - - vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vhsic_reg: LDO5 { - regulator-name = "VHSIC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vusbdac_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vtouch_reg: LDO11 { - regulator-name = "TOUCH_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcclcd_reg: LDO13 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - vmotor_reg: LDO14 { - regulator-name = "VCC_2.8V_MOTOR"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vled_reg: LDO15 { - regulator-name = "LED_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtf_reg: LDO17 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vtouchled_reg: LDO18 { - regulator-name = "TOUCH_LED_3.3V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - - vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - varm_breg: BUCK1 { - regulator-name = "VARM_1.2V_C210"; - regulator-min-microvolt = <65000>; - regulator-max-microvolt = <2225000>; - regulator-always-on; - }; - - vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <65000>; - regulator-max-microvolt = <2225000>; - regulator-always-on; - }; - - vg3d_breg: BUCK3 { - regulator-name = "G3D_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-microvolt-offset = <50000>; - regulator-always-on; - }; - - camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - - EN32KHZ_AP { - regulator-name = "EN32KHZ_AP"; - regulator-always-on; - }; - - EN32KHZ_CP { - regulator-name = "EN32KHZ_CP"; - regulator-always-on; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <200000>; - regulator-max-microamp = <950000>; - }; - - chargercv_reg: CHARGER_CV { - regulator-name = "CHARGER_CV"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - CHARGER_TOPOFF { - regulator-name = "CHARGER_TOPOFF"; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_7 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - - gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - sleep0: sleep-state { - gpa0-0-pin { - samsung,pins = "gpa0-0"; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; - - gpa0-1-pin { - samsung,pins = "gpa0-1"; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; - - gpa0-2-pin { - samsung,pins = "gpa0-2"; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; - - gpa0-3-pin { - samsung,pins = "gpa0-3"; - samsung,pin-con-pdn = ; - samsung,pin-pud-pdn = ; - }; - }; -}; - -&pinctrl_1 { - mhl_int: mhl-int-pins { - samsung,pins = "gpf3-5"; - samsung,pin-pud = ; - }; - - i2c_mhl_bus: i2c-mhl-bus-pins { - samsung,pins = "gpf0-4", "gpf0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb_sel: usb-sel-pins { - samsung,pins = "gpl0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - bt_en: bt-en-pins { - samsung,pins = "gpl0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - bt_res: bt-res-pins { - samsung,pins = "gpl1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - otg_gp: otg-gp-pins { - samsung,pins = "gpx3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - mag_mhl_gpio: mag-mhl-pins { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - max8997_irq: max8997-irq-pins { - samsung,pins = "gpx0-7"; - samsung,pin-pud = ; - }; - - max17042_fuel_irq: max17042-fuel-irq-pins { - samsung,pins = "gpx2-3"; - samsung,pin-pud = ; - }; - - tsp224_irq: tsp224-irq-pins { - samsung,pins = "gpx0-4"; - samsung,pin-pud = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_0 { - status = "okay"; - - bus-width = <8>; - non-removable; - vmmc-supply = <&vemmc_reg>; - - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>; - pinctrl-names = "default"; -}; - -&sdhci_2 { - status = "okay"; - - bus-width = <4>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vtf_reg>; - - pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>; - pinctrl-names = "default"; -}; - -&sdhci_3 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - non-removable; - bus-width = <4>; - mmc-pwrseq = <&wlan_pwrseq>; - vmmc-supply = <&vtf_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - - shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; - device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - - interrupt-parent = <&gpx2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wakeup"; - }; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts deleted file mode 100644 index f1927ca15e08..000000000000 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Origen board device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4210 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4210"; - compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; - }; - - aliases { - mmc0 = &sdhci_0; - mmc1 = &sdhci_2; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial2:115200n8"; - }; - - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-up { - label = "Up"; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-down { - label = "Down"; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-back { - label = "Back"; - gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-home { - label = "Home"; - gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-menu { - label = "Menu"; - gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - led-status { - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - function = LED_FUNCTION_HEARTBEAT; - linux,default-trigger = "heartbeat"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on max8997 PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck1_reg>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 4 4>; - }; - }; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo3_reg>; - vusb_a-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - - pmic@66 { - compatible = "maxim,max8997-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max8997_irq>; - - max8997,pmic-buck1-dvs-voltage = <1350000>; - max8997,pmic-buck2-dvs-voltage = <1100000>; - max8997,pmic-buck5-dvs-voltage = <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VMIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_RTC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_AUD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "DVDD_SWB_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_PLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_AUD_3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "AVDD18_SWB_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDD_SWB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD_MIF_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_ARM_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_INT_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_G3D_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VDD_LCD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - EN32KHZ_AP { - regulator-name = "EN32KHZ_AP"; - regulator-always-on; - }; - }; - }; -}; - -&pinctrl_1 { - max8997_irq: max8997-irq-pins { - samsung,pins = "gpx0-3", "gpx0-4"; - samsung,pin-pud = ; - }; -}; - -&sdhci_0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&tmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi deleted file mode 100644 index 70d268f9fcb1..000000000000 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ /dev/null @@ -1,863 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2011-2012 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device - * tree nodes in this file. - */ - -#include "exynos-pinctrl.h" - -&pinctrl_0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe2: gpe2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe3: gpe3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe4: gpe4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus-pins { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus-pins { - samsung,pins = "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus-pins { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus-pins { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus-pins { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl-pins { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync-pins { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_en: lcd-en-pins { - samsung,pins = "gpe3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk-pins { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16-pins { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18-pins { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24-pins { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpj0: gpj0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk-pins { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd-pins { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd-pins { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1-pins { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4-pins { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8-pins { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8-pins { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk-pins { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd-pins { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd-pins { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1-pins { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4-pins { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0-pins { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8-pins { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15-pins { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16-pins { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io-pins { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active-pins { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle-pins { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec-pins { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz: gpz-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - i2s0_bus: i2s0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts deleted file mode 100644 index b566f878ed84..000000000000 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based SMDKV310 board device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Device tree source file for Samsung's SMDKV310 board which is based on - * Samsung's Exynos4210 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung smdkv310 evaluation board based on Exynos4210"; - compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - mmc0 = &sdhci_2; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial1:115200n8"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <12000000>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 4 4>; - }; - }; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - eeprom@50 { - compatible = "samsung,24ad0xd1"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "samsung,24ad0xd1"; - reg = <0x52>; - }; -}; - -&keypad { - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_cols>; - status = "okay"; - - key-1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; - - key-2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; - - key-3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; - - key-4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = <5>; - }; - - key-5 { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <6>; - }; - - key-a { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <30>; - }; - - key-b { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <48>; - }; - - key-c { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <46>; - }; - - key-d { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <32>; - }; - - key-e { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <18>; - }; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows-pins { - samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols-pins { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_2 { - cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25x80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts deleted file mode 100644 index bfb04b31e11b..000000000000 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Trats board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats board which is based on - * Samsung's Exynos4210 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include - -/ { - model = "Samsung Trats based on Exynos4210"; - compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; - chassis-type = "handset"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; - }; - - aliases { - mmc0 = &sdhci_0; - mmc1 = &sdhci_2; - mmc2 = &sdhci_3; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = "serial2:115200n8"; - }; - - vemmc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - tsp_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "TSP_FIXED_VOLTAGES"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_af_28v_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "8M_AF_2.8V_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_en_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_IO_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_12v_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "8M_1.2V_EN"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vt_core_15v_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VT_CORE_1.5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - vol-down-key { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - vol-up-key { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - ok-key { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = <352>; - label = "ok"; - debounce-interval = <10>; - }; - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on max8997 PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&camera { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&varm_breg>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; - }; - }; -}; - -&dsi_0 { - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - panel@0 { - reg = <0>; - compatible = "samsung,s6e8aa0"; - vdd3-supply = <&vcclcd_reg>; - vci-supply = <&vlcd_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay = <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safe1_sreg>; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimd { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&vusb_reg>; - vusb_a-supply = <&vusbdac_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - avdd-supply = <&tsp_reg>; - vdd-supply = <&tsp_reg>; - }; -}; - -&i2c_5 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - pmic@66 { - compatible = "maxim,max8997-pmic"; - - reg = <0x66>; - interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, - <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>, - <&gpl0 0 GPIO_ACTIVE_HIGH>; - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, - <950000>, <900000>, - <1100000>, <1000000>, - <950000>, <900000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vusbdac_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcclcd_reg: LDO13 { - regulator-name = "VCC_3.3V_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vlcd_reg: LDO15 { - regulator-name = "VLCD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - tflash_reg: LDO17 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - varm_breg: BUCK1 { - regulator-name = "VARM_1.2V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V_C210"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - - EN32KHZ_AP { - regulator-name = "EN32KHZ_AP"; - regulator-always-on; - }; - - EN32KHZ_CP { - regulator-name = "EN32KHZ_CP"; - regulator-always-on; - }; - }; - }; -}; - -&pinctrl_1 { - bt_shutdown: bt-shutdown-pins { - samsung,pins = "gpl1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_host_wakeup: bt-host-wakeup-pins { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_device_wakeup: bt-device-wakeup-pins { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_0 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&tflash_reg>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sdhci_3 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - non-removable; - bus-width = <4>; - mmc-pwrseq = <&wlan_pwrseq>; - vmmc-supply = <&tflash_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - status = "okay"; - pinctrl-0 = <&uart0_data &uart0_fctl>; - pinctrl-names = "default"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; - pinctrl-names = "default"; - shutdown-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts deleted file mode 100644 index c84af3d27c1c..000000000000 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ /dev/null @@ -1,689 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Universal C210 board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Universal C210 board which is based on - * Samsung's Exynos4210 rev0 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include - -/ { - model = "Samsung Universal C210 based on Exynos4210 rev0"; - compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; - chassis-type = "handset"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000>; - }; - - aliases { - mmc0 = &sdhci_0; - mmc1 = &sdhci_2; - mmc2 = &sdhci_3; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; - stdout-path = "serial2:115200n8"; - }; - - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - vemmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2_8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - vol-up-key { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <1>; - }; - - vol-down-key { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <1>; - }; - - config-key { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <171>; - label = "config"; - debounce-interval = <1>; - wakeup-source; - }; - - camera-key { - gpios = <&gpx2 3 GPIO_ACTIVE_LOW>; - linux,code = <212>; - label = "camera"; - debounce-interval = <1>; - }; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - - ok-key { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = <352>; - label = "ok"; - debounce-interval = <1>; - }; - }; - - tsp_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "TSP_2_8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi-3 { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; - - lcd@0 { - compatible = "samsung,ld9040"; - reg = <0>; - vdd3-supply = <&ldo7_reg>; - vci-supply = <&ldo17_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <1200000>; - power-on-delay = <10>; - reset-delay = <10>; - panel-width-mm = <90>; - panel-height-mm = <154>; - display-timings { - timing { - clock-frequency = <23492370>; - hactive = <480>; - vactive = <800>; - hback-porch = <16>; - hfront-porch = <16>; - vback-porch = <2>; - vfront-porch = <28>; - hsync-len = <2>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_dpi_ep>; - }; - }; - }; - }; - - hdmi_en: voltage-regulator-hdmi-5v { - compatible = "regulator-fixed"; - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpe0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi_ddc: i2c-ddc { - compatible = "i2c-gpio"; - sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <100>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&i2c_ddc_bus>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&camera { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm_reg>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 4 4>; - }; - }; -}; - -&ehci { - status = "okay"; - phys = <&exynos_usbphy 1>; - phy-names = "host"; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safeout1_reg>; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimd { - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - samsung,invert-vden; - samsung,invert-vclk; - #address-cells = <1>; - #size-cells = <0>; - port@3 { - reg = <3>; - fimd_dpi_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; -}; - -&gpu { - mali-supply = <&buck2_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - hdmi-en-supply = <&hdmi_en>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&hdmi_ddc>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo3_reg>; - vusb_a-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - tsp@4a { - /* TBD: Atmel maXtouch touchscreen */ - reg = <0x4a>; - }; -}; - -&i2c_5 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - vdd_arm_reg: pmic@60 { - compatible = "maxim,max8952"; - reg = <0x60>; - - max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>, - <&gpx0 4 GPIO_ACTIVE_HIGH>; - max8952,default-mode = <0>; - max8952,dvs-mode-microvolt = <1250000>, <1200000>, - <1050000>, <950000>; - max8952,sync-freq = <0>; - max8952,ramp-speed = <0>; - - regulator-name = "VARM_1.2V_C210"; - regulator-min-microvolt = <770000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - pmic@66 { - compatible = "national,lp3974"; - interrupts-extended = <&gpx0 7 0>, <&gpx2 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&lp3974_irq>; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, - <1100000>, <1000000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD+VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "PS_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VHIC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_I_HOST_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "CAM_S_ANA_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VINT_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VG3D_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VMEM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - cp32khz_reg: EN32KHz-CP { - regulator-name = "32KHz CP"; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; -}; - -&mct { - status = "disabled"; -}; - -&mdma1 { - /* Use the secure mdma0 */ - status = "disabled"; -}; - -&mixer { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pinctrl_1 { - bt_shutdown: bt-shutdown-pins { - samsung,pins = "gpe1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_host_wakeup: bt-host-wakeup-pins { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_device_wakeup: bt-device-wakeup-pins { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lp3974_irq: lp3974-irq-pins { - samsung,pins = "gpx0-7", "gpx2-7"; - samsung,pin-pud = ; - }; - - hdmi_hpd: hdmi-hpd-pins { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; -}; - -&pinctrl_0 { - i2c_ddc_bus: i2c-ddc-bus-pins { - samsung,pins = "gpe4-2", "gpe4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - compatible = "samsung,s5p6440-pwm"; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_0 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sdhci_3 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - non-removable; - bus-width = <4>; - mmc-pwrseq = <&wlan_pwrseq>; - vmmc-supply = <&ldo5_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - pinctrl-0 = <&uart0_data &uart0_fctl>; - pinctrl-names = "default"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; - pinctrl-names = "default"; - shutdown-gpios = <&gpe1 4 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&serial_1 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_2 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_3 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&soc { - mdma0: dma-controller@12840000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12840000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - power-domains = <&pd_lcd0>; - }; -}; - -&sysram { - smp-sram@0 { - status = "disabled"; - }; - - smp-sram@5000 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x5000 0x1000>; - }; - - smp-sram@1f000 { - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi deleted file mode 100644 index 0e27c3375e2e..000000000000 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ /dev/null @@ -1,531 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 SoC device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4.dtsi" -#include "exynos4-cpu-thermal.dtsi" - -/ { - compatible = "samsung,exynos4210", "samsung,exynos4"; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - - bus_acp_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - - bus_display_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - }; - }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - - bus_dmc_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1025000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1150000>; - opp-suspend; - }; - }; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - - bus_fsys_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-10000000 { - opp-hz = /bits/ 64 <10000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - }; - - bus_lcd0: bus-lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - - bus_peri_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-5000000 { - opp-hz = /bits/ 64 <5000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@900 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x900>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - clock-latency = <160000>; - - operating-points = < - 1200000 1250000 - 1000000 1150000 - 800000 1075000 - 500000 975000 - 400000 975000 - 200000 950000 - >; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@901 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x901>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - clock-latency = <160000>; - - operating-points = < - 1200000 1250000 - 1000000 1150000 - 800000 1075000 - 500000 975000 - 400000 975000 - 200000 950000 - >; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - bus_leftbus_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-suspend; - }; - }; - - soc: soc { - sysram: sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x20000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@1f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x1f000 0x1000>; - }; - }; - - pd_lcd1: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023ca0 0x20>; - #power-domain-cells = <0>; - label = "LCD1"; - }; - - l2c: cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <2 2 1>; - }; - - mct: timer@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&combiner 12 6>, - <&combiner 12 7>, - <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x03860000 0x1000>; - }; - - g2d: g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_g2d>; - }; - - ppmu_acp: ppmu@10ae0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10ae0000 0x2000>; - status = "disabled"; - }; - - ppmu_lcd1: ppmu@12240000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12240000 0x2000>; - clocks = <&clock CLK_PPMULCD1>; - clock-names = "ppmu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@12a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12a20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1: sysmmu@12220000 { - compatible = "samsung,exynos-sysmmu"; - interrupt-parent = <&combiner>; - reg = <0x12220000 0x1000>; - interrupts = <5 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - power-domains = <&pd_lcd1>; - #iommu-cells = <0>; - }; - }; -}; - -&cpu_alert0 { - temperature = <85000>; /* millicelsius */ -}; - -&cpu_alert1 { - temperature = <100000>; /* millicelsius */ -}; - -&cpu_alert2 { - temperature = <110000>; /* millicelsius */ -}; - -&cpu_thermal { - polling-delay-passive = <0>; - polling-delay = <0>; -}; - -&gic { - cpu-offset = <0x8000>; -}; - -&camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; -}; - -&combiner { - samsung,combiner-nr = <16>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&fimc_0 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; -}; - -&fimc_1 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; -}; - -&fimc_2 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; -}; - -&fimc_3 { - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,lcd-wb; -}; - -&gpu { - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - }; -}; - -&mdma1 { - power-domains = <&pd_lcd0>; -}; - -&mixer { - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", - "sclk_mixer"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, - <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; -}; - -&pmu { - interrupts = <2 2>, <3 2>; - interrupt-affinity = <&cpu0>, <&cpu1>; - status = "okay"; -}; - -&pmu_system_controller { - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&rotator { - power-domains = <&pd_lcd0>; -}; - -&sysmmu_rotator { - power-domains = <&pd_lcd0>; -}; - -&tmu { - compatible = "samsung,exynos4210-tmu"; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; -}; - -#include "exynos4210-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi deleted file mode 100644 index aa984601ee06..000000000000 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4212 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4x12.dtsi" - -/ { - compatible = "samsung,exynos4212", "samsung,exynos4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - opp-suspend; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - cpu0_opp_1500: opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; -}; - -&clock { - compatible = "samsung,exynos4212-clock"; -}; - -&combiner { - samsung,combiner-nr = <18>; -}; - -&gic { - cpu-offset = <0x8000>; -}; - -&pmu { - interrupts = <2 2>, <3 2>; - interrupt-affinity = <&cpu0>, <&cpu1>; - status = "okay"; -}; - -&pmu_system_controller { - compatible = "samsung,exynos4212-pmu", "simple-mfd", "syscon"; -}; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi deleted file mode 100644 index 94122e9c6625..000000000000 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based Galaxy S3 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include "exynos4412-midas.dtsi" - -/ { - aliases { - i2c9 = &i2c_ak8975; - i2c10 = &i2c_cm36651; - }; - - led-controller { - compatible = "skyworks,aat1290"; - flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; - enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default", "host", "isp"; - pinctrl-0 = <&camera_flash_host>; - pinctrl-1 = <&camera_flash_host>; - pinctrl-2 = <&camera_flash_isp>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - led-max-microamp = <520833>; - flash-max-microamp = <1012500>; - flash-max-timeout-us = <1940000>; - }; - }; - - lcd_vdd3_reg: voltage-regulator-10 { - compatible = "regulator-fixed"; - regulator-name = "LCD_VDD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ps_als_reg: voltage-regulator-11 { - compatible = "regulator-fixed"; - regulator-name = "LED_A_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - i2c_ak8975: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c_cm36651: i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - light-sensor@18 { - compatible = "capella,cm36651"; - reg = <0x18>; - interrupt-parent = <&gpx0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vled-supply = <&ps_als_reg>; - }; - }; -}; - -&buck9_reg { - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; -}; - -&cam_af_reg { - gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cam_io_reg { - gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dsi_0 { - status = "okay"; - - panel@0 { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&lcd_vdd3_reg>; - vci-supply = <&ldo25_reg>; - reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay = <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; -}; - -&i2c_3 { - touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; -}; - -&ldo25_reg { - regulator-name = "LCD_VCC_3.3V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&pinctrl_0 { - camera_flash_host: camera-flash-host-pins { - samsung,pins = "gpj1-0"; - samsung,pin-function = ; - samsung,pin-val = <0>; - }; - - camera_flash_isp: camera-flash-isp-pins { - samsung,pins = "gpj1-0"; - samsung,pin-function = ; - samsung,pin-val = <1>; - }; -}; - -&s5c73m3 { - standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ - vdda-supply = <&ldo17_reg>; - status = "okay"; -}; - -&sound { - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", - - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP", - - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", - - "HDMI", "LINEOUT1N", - "HDMI", "LINEOUT1P", - - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", - - "IN1LP", "MICBIAS1", - "IN1LN", "MICBIAS1", - "Main Mic", "MICBIAS1", - - "IN1RP", "Sub Mic", - "IN1RN", "Sub Mic", - - "IN2LP:VXRN", "MICBIAS2", - "Headset Mic", "MICBIAS2", - - "IN2RN", "FM In", - "IN2RP:VXRP", "FM In"; -}; - -&submic_bias_reg { - gpio = <&gpf2 0 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; - -&touchkey_reg { - gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts deleted file mode 100644 index 61aca5798f38..000000000000 --- a/arch/arm/boot/dts/exynos4412-i9300.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos4412-galaxy-s3.dtsi" - -/ { - model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412"; - compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - chassis-type = "handset"; - - /* bootargs are passed in by bootloader */ - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; -}; - -&sound { - fm-sel-gpios = <&gpl0 3 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/exynos4412-i9305.dts deleted file mode 100644 index 77083f1a8273..000000000000 --- a/arch/arm/boot/dts/exynos4412-i9305.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "exynos4412-galaxy-s3.dtsi" - -/ { - model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412"; - compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - chassis-type = "handset"; - - /* bootargs are passed in by bootloader */ - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; -}; - -&i2c0_bus { - /* SCL and SDA pins are swapped */ - samsung,pins = "gpd1-1", "gpd1-0"; -}; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts deleted file mode 100644 index ded232b04e0d..000000000000 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * TOPEET's Exynos4412 based itop board device tree source - * - * Copyright (c) 2016 SUMOMO Computer Association - * https://www.sumomo.mobi - * Randy Li - * - * Device tree source file for TOPEET iTop Exynos 4412 core board - * which is based on Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include -#include -#include -#include "exynos4412-itop-scp-core.dtsi" - -/ { - model = "TOPEET iTop 4412 Elite board based on Exynos4412"; - compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - mmc1 = &sdhci_2; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; - stdout-path = "serial2:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led2 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led3 { - label = "red:user"; - color = ; - gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-home { - label = "GPIO Key Home"; - linux,code = ; - gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; - }; - - key-back { - label = "GPIO Key Back"; - linux,code = ; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - }; - - key-sleep { - label = "GPIO Key Sleep"; - linux,code = ; - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - }; - - key-vol-up { - label = "GPIO Key Vol+"; - linux,code = ; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - }; - - key-vol-down { - label = "GPIO Key Vol-"; - linux,code = ; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm-sound"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&i2s0 0>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - system-clock-frequency = <11289600>; - }; - }; - - beep { - compatible = "pwm-beeper"; - pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; -}; - -&camera { - pinctrl-0 = <&cam_port_a_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, <0>, <112896000>, <11289600>; -}; - -&ehci { - status = "okay"; - /* In order to reset USB ethernet */ - samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - - phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>; - phy-names = "host", "hsic1"; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - codec: audio-codec@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - wlf,shared-lrclk; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pinctrl_1 { - ether-reset-pins { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - status = "okay"; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - cd-gpios = <&gpx0 7 GPIO_ACTIVE_LOW>; - cap-sd-highspeed; - vmmc-supply = <&ldo23_reg>; - vqmmc-supply = <&ldo17_reg>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi deleted file mode 100644 index 7bc6968af9c3..000000000000 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ /dev/null @@ -1,509 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * TOPEET's Exynos4412 based itop board device tree source - * - * Copyright (c) 2016 SUMOMO Computer Association - * https://www.sumomo.mobi - * Randy Li - * - * Device tree source file for TOPEET iTop Exynos 4412 SCP package core - * board which is based on Samsung's Exynos4412 SoC. - */ - -#include -#include -#include -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - mmc0 = &mshc_0; - }; - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203f000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; - - usb-hub { - compatible = "smsc,usb3503a"; - reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>; - connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>; - intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hsic_reset>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c1_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5m8767: pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>, - <&gpb 6 GPIO_ACTIVE_HIGH>, - <&gpb 7 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, - <&gpm3 6 GPIO_ACTIVE_HIGH>, - <&gpm3 7 GPIO_ACTIVE_HIGH>; - - /* VDD_ARM */ - s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>, - <1243750>, <1118750>, - <1068750>, <1012500>, - <956250>, <900000>; - /* VDD_INT */ - s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>, - <925000>, <925000>, - <887500>, <887500>, - <850000>, <850000>; - /* VDD_G3D */ - s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>, - <1025000>, <950000>, - <918750>, <900000>, - <875000>, <831250>; - wakeup-source; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - /* SCP uses 1.5v, POP uses 1.2v */ - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_LDO5"; - op_mode = <0>; /* Always off Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - /* Used by HSIC */ - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "VDD_LDO19"; - op_mode = <0>; /* Always off Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1456250>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck7_reg: BUCK7 { - regulator-name = "pvdd_buck7"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck8_reg: BUCK8 { - regulator-name = "pvdd_buck8"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; /* Normal Mode */ - }; - }; - - s5m8767_osc: clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "s5m8767_ap", - "s5m8767_cp", "s5m8767_bt"; - }; - - }; -}; - -&mfc { - status = "okay"; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - vmmc-supply = <&buck9_reg>; - broken-cd; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pinctrl_1 { - hsic_reset: hsic-reset-pins { - samsung,pins = "gpm2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&tmu { - vtmu-supply = <&ldo16_reg>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi deleted file mode 100644 index e6b949c1a00f..000000000000 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ /dev/null @@ -1,1459 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based Trats 2 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats 2 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" - -#include -#include -#include -#include -#include "exynos-pinctrl.h" - -/ { - compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - i2c11 = &i2c_max77693; - i2c12 = &i2c_max77693_fuel; - mmc0 = &mshc_0; - mmc2 = &sdhci_2; - mmc3 = &sdhci_3; - }; - - chosen { - stdout-path = &serial_2; - }; - - firmware@204f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204f000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - cam_io_reg: voltage-regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - status = "disabled"; - }; - - cam_af_reg: voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - status = "disabled"; - }; - - vsil12: voltage-regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "VSIL_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&buck7_reg>; - }; - - vcc33mhl: voltage-regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3.3_MHL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc18mhl: voltage-regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8_MHL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - touchkey_reg: voltage-regulator-6 { - compatible = "regulator-fixed"; - regulator-name = "LED_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - status = "disabled"; - }; - - vbatt_reg: voltage-regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "VBATT"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - mic_bias_reg: voltage-regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "MICBIAS_LDO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpf1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - submic_bias_reg: voltage-regulator-9 { - compatible = "regulator-fixed"; - regulator-name = "SUB_MICBIAS_LDO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - - key-down { - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - key-up { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - key-power { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - key-ok { - gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; - linux,code = <139>; - label = "ok"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - i2c_max77693: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "maxim,max77693"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&max77693_irq>; - reg = <0x66>; - - regulators { - esafeout1_reg: ESAFEOUT1 { - regulator-name = "ESAFEOUT1"; - }; - esafeout2_reg: ESAFEOUT2 { - regulator-name = "ESAFEOUT2"; - }; - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <60000>; - regulator-max-microamp = <2580000>; - }; - }; - - motor-driver { - compatible = "maxim,max77693-haptic"; - haptic-supply = <&ldo26_reg>; - pwms = <&pwm 0 38022 0>; - }; - - charger { - compatible = "maxim,max77693-charger"; - - maxim,constant-microvolt = <4350000>; - maxim,min-system-microvolt = <3600000>; - maxim,thermal-regulation-celsius = <100>; - maxim,battery-overcurrent-microamp = <3500000>; - maxim,charge-input-threshold-microvolt = <4300000>; - }; - }; - }; - - i2c_max77693_fuel: i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - fuel-gauge@36 { - compatible = "maxim,max17047"; - interrupt-parent = <&gpx2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&max77693_fuel_irq>; - reg = <0x36>; - - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - }; - }; - - i2c-gpio-4 { - compatible = "i2c-gpio"; - sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - touchkey@20 { - compatible = "cypress,midas-touchkey"; - reg = <0x20>; - vdd-supply = <&touchkey_reg>; - vcc-supply = <&ldo5_reg>; - interrupt-parent = <&gpj0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - linux,keycodes = ; - }; - }; - - i2c-mhl { - compatible = "i2c-gpio"; - sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <100>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&i2c_mhl_bus>; - pinctrl-names = "default"; - - sii9234: hdmi-bridge@39 { - compatible = "sil,sii9234"; - avcc33-supply = <&vcc33mhl>; - iovcc18-supply = <&vcc18mhl>; - avcc12-supply = <&vsil12>; - cvcc12-supply = <&vsil12>; - reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpf3>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; - }; - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; - - sound: sound { - compatible = "samsung,midas-audio"; - model = "Midas"; - mic-bias-supply = <&mic_bias_reg>; - submic-bias-supply = <&submic_bias_reg>; - - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&wm1811>; - }; - }; - - thermistor-ap { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 1>; /* AP temperature */ - }; - - thermistor-battery { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 2>; /* Battery temperature */ - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&camera { - pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>, - <&clock CLK_MOUT_CAM1>; - assigned-clock-parents = <&clock CLK_XUSBXTI>, - <&clock CLK_XUSBXTI>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, - <&cpu2 13 13>, <&cpu3 13 13>; - }; - }; -}; - -&csis_0 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera C (3) MIPI CSI-2 (CSIS0) */ - port@3 { - reg = <3>; - csis0_ep: endpoint { - remote-endpoint = <&s5c73m3_ep>; - data-lanes = <1 2 3 4>; - samsung,csis-hs-settle = <12>; - }; - }; -}; - -&csis_1 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera D (4) MIPI CSI-2 (CSIS1) */ - port@4 { - reg = <4>; - csis1_ep: endpoint { - remote-endpoint = <&is_s5k6a3_ep>; - data-lanes = <1>; - samsung,csis-hs-settle = <18>; - samsung,csis-wclk; - }; - }; -}; - -&dsi_0 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; -}; - -&exynos_usbphy { - vbus-supply = <&esafeout1_reg>; - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_is { - pinctrl-0 = <&fimc_is_uart>; - pinctrl-names = "default"; - status = "okay"; -}; - -&fimc_lite_0 { - status = "okay"; -}; - -&fimc_lite_1 { - status = "okay"; -}; - -&fimd { - status = "okay"; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&i2c_5>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hdmi_to_mhl: endpoint { - remote-endpoint = <&mhl_to_hdmi>; - }; - }; - }; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5c73m3: image-sensor@3c { - compatible = "samsung,s5c73m3"; - reg = <0x3c>; - xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ - vdd-int-supply = <&buck9_reg>; - vddio-cis-supply = <&ldo9_reg>; - vddio-host-supply = <&ldo18_reg>; - vdd-af-supply = <&cam_af_reg>; - vdd-reg-supply = <&cam_io_reg>; - clock-frequency = <24000000>; - /* CAM_A_CLKOUT */ - clocks = <&camera 0>; - clock-names = "cis_extclk"; - status = "disabled"; - port { - s5c73m3_ep: endpoint { - remote-endpoint = <&csis0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c1_isp { - pinctrl-0 = <&fimc_is_i2c1>; - pinctrl-names = "default"; - - image-sensor@10 { - compatible = "samsung,s5k6a3"; - reg = <0x10>; - svdda-supply = <&cam_io_reg>; - svddio-supply = <&ldo19_reg>; - afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; - /* CAM_B_CLKOUT */ - clocks = <&camera 1>; - clock-names = "extclk"; - gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; - - port { - is_s5k6a3_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - wm1811: audio-codec@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>, - <&max77686 MAX77686_CLK_PMIC>; - clock-names = "MCLK1", "MCLK2"; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpx3>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; - - gpio-controller; - #gpio-cells = <2>; - #sound-dai-cells = <0>; - - wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0 - 0x0 0x8000 0x0 0x0 0x0>; - wlf,micbias-cfg = <0x2f 0x2b>; - - wlf,lineout1-feedback; - wlf,lineout1-se; - wlf,lineout2-se; - wlf,ldoena-always-driven; - - AVDD2-supply = <&vbatt_reg>; - DBVDD1-supply = <&ldo3_reg>; - DBVDD2-supply = <&vbatt_reg>; - DBVDD3-supply = <&vbatt_reg>; - DCVDD-supply = <&ldo3_reg>; - CPVDD-supply = <&vbatt_reg>; - SPKVDD1-supply = <&vbatt_reg>; - SPKVDD2-supply = <&vbatt_reg>; - wlf,ldo1ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c_5 { - status = "okay"; -}; - -&i2c_7 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - status = "okay"; - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&max77686_irq>; - pinctrl-names = "default"; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VALIVE_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VM1M2_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VCC_1.8V_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "CAM_ISP_MIPI_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VABB1_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VUOTG_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "NFC_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VABB2_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VHSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VHSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_ISP_SEN_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VDDQ_PRE_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo23_reg: LDO23 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "LDO25"; - }; - - ldo26_reg: LDO26 { - regulator-name = "MOTOR_VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VMEM_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VMEM_VDDF_3.0V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - buck9_reg: BUCK9 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mshc_0 { - broken-cd; - non-removable; - card-detect-delay = <200>; - vmmc-supply = <&ldo22_reg>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <0>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - mmc-ddr-1_8v; - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - mhl_int: mhl-int-pins { - samsung,pins = "gpf3-5"; - samsung,pin-pud = ; - }; - - i2c_mhl_bus: i2c-mhl-bus-pins { - samsung,pins = "gpf0-4", "gpf0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, NONE); - PIN_SLP(gpa0-1, OUT0, NONE); - PIN_SLP(gpa0-2, INPUT, NONE); - PIN_SLP(gpa0-3, INPUT, UP); - PIN_SLP(gpa0-4, INPUT, NONE); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, UP); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, INPUT, NONE); - PIN_SLP(gpb-1, INPUT, NONE); - PIN_SLP(gpb-2, INPUT, NONE); - PIN_SLP(gpb-3, INPUT, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, UP); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, NONE); - PIN_SLP(gpc1-1, PREV, NONE); - PIN_SLP(gpc1-2, INPUT, NONE); - PIN_SLP(gpc1-3, INPUT, NONE); - PIN_SLP(gpc1-4, INPUT, NONE); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, DOWN); - PIN_SLP(gpd1-1, INPUT, DOWN); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - - PIN_SLP(gpf0-0, INPUT, NONE); - PIN_SLP(gpf0-1, INPUT, NONE); - PIN_SLP(gpf0-2, INPUT, DOWN); - PIN_SLP(gpf0-3, INPUT, DOWN); - PIN_SLP(gpf0-4, INPUT, NONE); - PIN_SLP(gpf0-5, INPUT, DOWN); - PIN_SLP(gpf0-6, INPUT, NONE); - PIN_SLP(gpf0-7, INPUT, DOWN); - - PIN_SLP(gpf1-0, INPUT, DOWN); - PIN_SLP(gpf1-1, INPUT, DOWN); - PIN_SLP(gpf1-2, INPUT, DOWN); - PIN_SLP(gpf1-3, INPUT, DOWN); - PIN_SLP(gpf1-4, INPUT, NONE); - PIN_SLP(gpf1-5, INPUT, NONE); - PIN_SLP(gpf1-6, INPUT, DOWN); - PIN_SLP(gpf1-7, PREV, NONE); - - PIN_SLP(gpf2-0, PREV, NONE); - PIN_SLP(gpf2-1, INPUT, DOWN); - PIN_SLP(gpf2-2, INPUT, DOWN); - PIN_SLP(gpf2-3, INPUT, DOWN); - PIN_SLP(gpf2-4, INPUT, DOWN); - PIN_SLP(gpf2-5, INPUT, DOWN); - PIN_SLP(gpf2-6, INPUT, NONE); - PIN_SLP(gpf2-7, INPUT, NONE); - - PIN_SLP(gpf3-0, INPUT, NONE); - PIN_SLP(gpf3-1, PREV, NONE); - PIN_SLP(gpf3-2, PREV, NONE); - PIN_SLP(gpf3-3, PREV, NONE); - PIN_SLP(gpf3-4, OUT1, NONE); - PIN_SLP(gpf3-5, INPUT, DOWN); - - PIN_SLP(gpj0-0, PREV, NONE); - PIN_SLP(gpj0-1, PREV, NONE); - PIN_SLP(gpj0-2, PREV, NONE); - PIN_SLP(gpj0-3, INPUT, DOWN); - PIN_SLP(gpj0-4, PREV, NONE); - PIN_SLP(gpj0-5, PREV, NONE); - PIN_SLP(gpj0-6, INPUT, DOWN); - PIN_SLP(gpj0-7, INPUT, DOWN); - - PIN_SLP(gpj1-0, INPUT, DOWN); - PIN_SLP(gpj1-1, PREV, NONE); - PIN_SLP(gpj1-2, PREV, NONE); - PIN_SLP(gpj1-3, INPUT, DOWN); - PIN_SLP(gpj1-4, INPUT, DOWN); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; - - gpio_keys: gpio-keys-pins { - samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; - samsung,pin-pud = ; - }; - - bt_shutdown: bt-shutdown-pins { - samsung,pins = "gpl0-6"; - samsung,pin-pud = ; - }; - - bt_host_wakeup: bt-host-wakeup-pins { - samsung,pins = "gpx2-6"; - samsung,pin-pud = ; - }; - - bt_device_wakeup: bt-device-wakeup-pins { - samsung,pins = "gpx3-1"; - samsung,pin-pud = ; - }; - - max77686_irq: max77686-irq-pins { - samsung,pins = "gpx0-7"; - samsung,pin-pud = ; - }; - - max77693_irq: max77693-irq-pins { - samsung,pins = "gpx1-5"; - samsung,pin-pud = ; - }; - - max77693_fuel_irq: max77693-fuel-irq-pins { - samsung,pins = "gpx2-3"; - samsung,pin-pud = ; - }; - - sdhci2_cd: sdhci2-cd-irq-pins { - samsung,pins = "gpx3-4"; - samsung,pin-pud = ; - }; - - hdmi_hpd: hdmi-hpd-pins { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; - - sleep1: sleep-state { - PIN_SLP(gpk0-0, PREV, NONE); - PIN_SLP(gpk0-1, PREV, NONE); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, PREV, NONE); - PIN_SLP(gpk0-4, PREV, NONE); - PIN_SLP(gpk0-5, PREV, NONE); - PIN_SLP(gpk0-6, PREV, NONE); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpk3-0, OUT0, NONE); - PIN_SLP(gpk3-1, INPUT, NONE); - PIN_SLP(gpk3-2, INPUT, DOWN); - PIN_SLP(gpk3-3, INPUT, NONE); - PIN_SLP(gpk3-4, INPUT, NONE); - PIN_SLP(gpk3-5, INPUT, NONE); - PIN_SLP(gpk3-6, INPUT, NONE); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - PIN_SLP(gpl0-4, PREV, NONE); - PIN_SLP(gpl0-6, PREV, NONE); - - PIN_SLP(gpl1-0, INPUT, DOWN); - PIN_SLP(gpl1-1, INPUT, DOWN); - PIN_SLP(gpl2-0, INPUT, DOWN); - PIN_SLP(gpl2-1, INPUT, DOWN); - PIN_SLP(gpl2-2, INPUT, DOWN); - PIN_SLP(gpl2-3, INPUT, DOWN); - PIN_SLP(gpl2-4, INPUT, DOWN); - PIN_SLP(gpl2-5, INPUT, DOWN); - PIN_SLP(gpl2-6, PREV, NONE); - PIN_SLP(gpl2-7, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, NONE); - PIN_SLP(gpm1-3, INPUT, NONE); - PIN_SLP(gpm1-4, INPUT, NONE); - PIN_SLP(gpm1-5, INPUT, NONE); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, NONE); - PIN_SLP(gpm2-1, INPUT, NONE); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, PREV, NONE); - PIN_SLP(gpm3-1, PREV, NONE); - PIN_SLP(gpm3-2, PREV, NONE); - PIN_SLP(gpm3-3, OUT1, NONE); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - - PIN_SLP(gpy0-0, INPUT, DOWN); - PIN_SLP(gpy0-1, INPUT, DOWN); - PIN_SLP(gpy0-2, INPUT, DOWN); - PIN_SLP(gpy0-3, INPUT, DOWN); - PIN_SLP(gpy0-4, INPUT, DOWN); - PIN_SLP(gpy0-5, INPUT, DOWN); - - PIN_SLP(gpy1-0, INPUT, DOWN); - PIN_SLP(gpy1-1, INPUT, DOWN); - PIN_SLP(gpy1-2, INPUT, DOWN); - PIN_SLP(gpy1-3, INPUT, DOWN); - - PIN_SLP(gpy2-0, PREV, NONE); - PIN_SLP(gpy2-1, INPUT, DOWN); - PIN_SLP(gpy2-2, INPUT, NONE); - PIN_SLP(gpy2-3, INPUT, NONE); - PIN_SLP(gpy2-4, INPUT, NONE); - PIN_SLP(gpy2-5, INPUT, NONE); - - PIN_SLP(gpy3-0, INPUT, DOWN); - PIN_SLP(gpy3-1, INPUT, DOWN); - PIN_SLP(gpy3-2, INPUT, DOWN); - PIN_SLP(gpy3-3, INPUT, DOWN); - PIN_SLP(gpy3-4, INPUT, DOWN); - PIN_SLP(gpy3-5, INPUT, DOWN); - PIN_SLP(gpy3-6, INPUT, DOWN); - PIN_SLP(gpy3-7, INPUT, DOWN); - - PIN_SLP(gpy4-0, INPUT, DOWN); - PIN_SLP(gpy4-1, INPUT, DOWN); - PIN_SLP(gpy4-2, INPUT, DOWN); - PIN_SLP(gpy4-3, INPUT, DOWN); - PIN_SLP(gpy4-4, INPUT, DOWN); - PIN_SLP(gpy4-5, INPUT, DOWN); - PIN_SLP(gpy4-6, INPUT, DOWN); - PIN_SLP(gpy4-7, INPUT, DOWN); - - PIN_SLP(gpy5-0, INPUT, DOWN); - PIN_SLP(gpy5-1, INPUT, DOWN); - PIN_SLP(gpy5-2, INPUT, DOWN); - PIN_SLP(gpy5-3, INPUT, DOWN); - PIN_SLP(gpy5-4, INPUT, DOWN); - PIN_SLP(gpy5-5, INPUT, DOWN); - PIN_SLP(gpy5-6, INPUT, DOWN); - PIN_SLP(gpy5-7, INPUT, DOWN); - - PIN_SLP(gpy6-0, INPUT, DOWN); - PIN_SLP(gpy6-1, INPUT, DOWN); - PIN_SLP(gpy6-2, INPUT, DOWN); - PIN_SLP(gpy6-3, INPUT, DOWN); - PIN_SLP(gpy6-4, INPUT, DOWN); - PIN_SLP(gpy6-5, INPUT, DOWN); - PIN_SLP(gpy6-6, INPUT, DOWN); - PIN_SLP(gpy6-7, INPUT, DOWN); - }; -}; - -&pinctrl_2 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep2>; - - sleep2: sleep-state { - PIN_SLP(gpz-0, INPUT, DOWN); - PIN_SLP(gpz-1, INPUT, DOWN); - PIN_SLP(gpz-2, INPUT, DOWN); - PIN_SLP(gpz-3, INPUT, DOWN); - PIN_SLP(gpz-4, INPUT, DOWN); - PIN_SLP(gpz-5, INPUT, DOWN); - PIN_SLP(gpz-6, INPUT, DOWN); - }; -}; - -&pinctrl_3 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep3>; - - sleep3: sleep-state { - PIN_SLP(gpv0-0, INPUT, DOWN); - PIN_SLP(gpv0-1, INPUT, DOWN); - PIN_SLP(gpv0-2, INPUT, DOWN); - PIN_SLP(gpv0-3, INPUT, DOWN); - PIN_SLP(gpv0-4, INPUT, DOWN); - PIN_SLP(gpv0-5, INPUT, DOWN); - PIN_SLP(gpv0-6, INPUT, DOWN); - PIN_SLP(gpv0-7, INPUT, DOWN); - - PIN_SLP(gpv1-0, INPUT, DOWN); - PIN_SLP(gpv1-1, INPUT, DOWN); - PIN_SLP(gpv1-2, INPUT, DOWN); - PIN_SLP(gpv1-3, INPUT, DOWN); - PIN_SLP(gpv1-4, INPUT, DOWN); - PIN_SLP(gpv1-5, INPUT, DOWN); - PIN_SLP(gpv1-6, INPUT, DOWN); - PIN_SLP(gpv1-7, INPUT, DOWN); - - PIN_SLP(gpv2-0, INPUT, DOWN); - PIN_SLP(gpv2-1, INPUT, DOWN); - PIN_SLP(gpv2-2, INPUT, DOWN); - PIN_SLP(gpv2-3, INPUT, DOWN); - PIN_SLP(gpv2-4, INPUT, DOWN); - PIN_SLP(gpv2-5, INPUT, DOWN); - PIN_SLP(gpv2-6, INPUT, DOWN); - PIN_SLP(gpv2-7, INPUT, DOWN); - - PIN_SLP(gpv3-0, INPUT, DOWN); - PIN_SLP(gpv3-1, INPUT, DOWN); - PIN_SLP(gpv3-2, INPUT, DOWN); - PIN_SLP(gpv3-3, INPUT, DOWN); - PIN_SLP(gpv3-4, INPUT, DOWN); - PIN_SLP(gpv3-5, INPUT, DOWN); - PIN_SLP(gpv3-6, INPUT, DOWN); - PIN_SLP(gpv3-7, INPUT, DOWN); - - PIN_SLP(gpv4-0, INPUT, DOWN); - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - status = "okay"; -}; - -&sdhci_3 { - #address-cells = <1>; - #size-cells = <0>; - non-removable; - bus-width = <4>; - - mmc-pwrseq = <&wlan_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_NONE>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - pinctrl-0 = <&uart0_data &uart0_fctl>; - pinctrl-names = "default"; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; - pinctrl-names = "default"; - max-speed = <3000000>; - shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - clocks = <&max77686 MAX77686_CLK_PMIC>; - }; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - - s5c73m3_spi: image-sensor@0 { - compatible = "samsung,s5c73m3"; - spi-max-frequency = <50000000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <2>; - }; - }; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts deleted file mode 100644 index 9ae05b0d684c..000000000000 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "exynos4412-midas.dtsi" - -/ { - compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412"; - chassis-type = "handset"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - /* bootargs are passed in by bootloader */ - - cam_vdda_reg: voltage-regulator-10 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&buck9_reg { - maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>; -}; - -&cam_af_reg { - gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cam_io_reg { - gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - touchscreen@48 { - compatible = "melfas,mms152"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; -}; - -&ldo13_reg { - regulator-name = "VCC_1.8V_LCD"; - regulator-always-on; -}; - -&ldo25_reg { - regulator-name = "VCI_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&s5c73m3 { - standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ - vdda-supply = <&cam_vdda_reg>; - status = "okay"; -}; - -&sound { - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", - - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", - - "HDMI", "LINEOUT1N", - "HDMI", "LINEOUT1P", - - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", - - "IN1LP", "MICBIAS2", - "IN1LN", "MICBIAS2", - "Headset Mic", "MICBIAS2", - - "IN1RP", "Sub Mic", - "IN1RN", "Sub Mic", - - "IN2LP:VXRN", "Main Mic", - "IN2LN", "Main Mic", - - "IN2RN", "FM In", - "IN2RP:VXRP", "FM In"; -}; - -&submic_bias_reg { - regulator-always-on; -}; - -&touchkey_reg { - gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi deleted file mode 100644 index 93ddbd4b0a18..000000000000 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ /dev/null @@ -1,574 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards - * device tree source - */ - -#include -#include -#include -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - aliases { - mmc0 = &mshc_0; - mmc2 = &sdhci_2; - }; - - chosen { - stdout-path = &serial_1; - }; - - firmware@204f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204f000 0x1000>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_power_key>; - - power-key { - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - sound: sound { - compatible = "hardkernel,odroid-xu4-audio"; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&hdmi>, <&max98090>; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_rstn>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&camera { - status = "okay"; -}; - -&clock { - clocks = <&clock CLK_XUSBXTI>; - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <45158401>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, <0>, - <196608001>, - <(196608001 / 2)>, - <(196608001 / 8)>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&cpu0_opp_table { - opp-1000000000 { - opp-suspend; - }; - opp-800000000 { - /delete-property/opp-suspend; - }; -}; - -&cpu_thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, - <&cpu2 13 13>, <&cpu3 13 13>; - }; - }; -}; - -&pinctrl_1 { - gpio_power_key: power-key-pins { - samsung,pins = "gpx1-3"; - samsung,pin-pud = ; - }; - - max77686_irq: max77686-irq-pins { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd: hdmi-hpd-pins { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; - - emmc_rstn: emmc-rstn-pins { - samsung,pins = "gpk1-2"; - samsung,pin-pud = ; - }; -}; - -&ehci { - status = "okay"; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - ddc = <&i2c_2>; - status = "okay"; -}; - -&hdmicec { - status = "okay"; -}; - -&hsotg { - status = "okay"; - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - usb3503: usb-hub@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - }; - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M1_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDQ_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_MMC2_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDDQ_MMC1_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_HDMI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDDQ_MIPIHSI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_USB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_HSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo20_reg: LDO20 { - regulator-name = "LDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "TFLASH_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo22_reg: LDO22 { - /* - * Only U3 uses it, so let it define the - * constraints - */ - regulator-name = "LDO22"; - regulator-boot-on; - }; - - ldo25_reg: LDO25 { - regulator-name = "VDDQ_LCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-microvolt-offset = <50000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_CKEM1_2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "BUCK6_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "BUCK7_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - /* - * Constraints set by specific board: X, - * X2 and U3. - */ - regulator-name = "BUCK8_2.8V"; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - max98090: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx0>; - interrupts = <0 IRQ_TYPE_NONE>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2c_2 { - status = "okay"; -}; - -&i2c_8 { - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; -}; - -&mixer { - status = "okay"; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&ldo20_reg>; - mmc-pwrseq = <&emmc_pwrseq>; - status = "okay"; - - broken-cd; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - vqmmc-supply = <&ldo4_reg>; - cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts deleted file mode 100644 index 42812da1f882..000000000000 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel's Exynos4412 based ODROID-U3 board device tree source - * - * Copyright (c) 2014 Marek Szyprowski - * - * Device tree source file for Hardkernel's ODROID-U3 board which is based - * on Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include -#include "exynos4412-odroid-common.dtsi" -#include "exynos4412-prime.dtsi" - -/ { - model = "Hardkernel ODROID-U3 board based on Exynos4412"; - compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - ethernet = ðernet; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7ff00000>; - }; - - vbus_otg_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VBUS_VDD_5.0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpl2 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - led1 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 10000 0>; - #cooling-cells = <2>; - cooling-levels = <0 102 170 230>; - }; -}; - -&adc { - vdd-supply = <&ldo10_reg>; - /* Nothing connected to ADC inputs, keep it disabled */ -}; - -/* Supply for LAN9730/SMSC95xx */ -&buck8_reg { - regulator-name = "BUCK8_P3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, - <&cpu2 9 9>, <&cpu3 9 9>, - <&fan0 1 2>; - }; - map1 { - trip = <&cpu_alert2>; - cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, - <&cpu2 15 15>, <&cpu3 15 15>, - <&fan0 2 3>; - }; - map2 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - }; -}; - -&hdmicec { - needs-hpd; -}; - -/* VDDQ for MSHC (eMMC card) */ -&ldo22_reg { - regulator-name = "LDO22_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&mshc_0 { - vqmmc-supply = <&ldo22_reg>; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&usb3503 { - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - refclk-frequency = <24000000>; -}; - -&ehci { - #address-cells = <1>; - #size-cells = <0>; - phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; - phy-names = "hsic0", "hsic1"; - - ethernet: ethernet@2 { - compatible = "usb424,9730"; - reg = <2>; - local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ - }; -}; - -&hsotg { - dr_mode = "otg"; - vbus-supply = <&vbus_otg_reg>; -}; - -&sound { - model = "Odroid-U3"; - samsung,audio-widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts deleted file mode 100644 index d5316cf2fbb6..000000000000 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel's Exynos4412 based ODROID-X board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X board which is based - * on Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include -#include "exynos4412-odroid-common.dtsi" - -/ { - model = "Hardkernel ODROID-X board based on Exynos4412"; - compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - ethernet = ðernet; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x3ff00000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led2 { - label = "led2:mmc0"; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "mmc0"; - }; - }; - - regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "p3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; -}; - -&adc { - vdd-supply = <&ldo10_reg>; - status = "okay"; -}; - -/* VDDQ for MSHC (eMMC card) */ -&buck8_reg { - regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&ehci { - #address-cells = <1>; - #size-cells = <0>; - phys = <&exynos_usbphy 2>; - phy-names = "hsic0"; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - /* Filled in by a bootloader */ - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; -}; - -&gpio_keys { - pinctrl-0 = <&gpio_power_key &gpio_home_key>; - - home-key { - gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - label = "home key"; - debounce-interval = <10>; - wakeup-source; - }; -}; - -&hsotg { - dr_mode = "peripheral"; -}; - -&mshc_0 { - vqmmc-supply = <&buck8_reg>; -}; - -&pinctrl_1 { - gpio_home_key: home-key-pins { - samsung,pins = "gpx2-2"; - samsung,pin-pud = ; - }; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&sound { - model = "Odroid-X"; - samsung,audio-widgets = - "Headphone", "Headphone Jack", - "Microphone", "Mic Jack", - "Microphone", "DMIC"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "IN1", "Mic Jack", - "Mic Jack", "MICBIAS"; -}; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts deleted file mode 100644 index 7be4cbdc4413..000000000000 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel's Exynos4412 based ODROID-X2 board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X2 board which is based - * on Samsung's Exynos4412 SoC. - */ - -#include "exynos4412-odroidx.dts" -#include "exynos4412-prime.dtsi" - -/ { - model = "Hardkernel ODROID-X2 board based on Exynos4412"; - compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7ff00000>; - }; -}; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts deleted file mode 100644 index 23b151645d66..000000000000 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Insignal's Exynos4412 based Origen board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4412"; - compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - mmc0 = &mshc_0; - mmc1 = &sdhci_2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203f000 0x1000>; - }; - - mmc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&cpu_thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, - <&cpu2 13 13>, <&cpu3 13 13>; - }; - }; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&ehci { - samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; - phy-names = "hsic0", "hsic1"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, - <&gpm3 6 GPIO_ACTIVE_HIGH>, - <&gpm3 7 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - wakeup-source; - - s5m8767_osc: clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "s5m8767_ap", "s5m8767_cp", - "s5m8767_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD18_2M"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "DVDD25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_M12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "VDD12_5M"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "VDDF28_EMMC"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - }; - }; -}; - -&keypad { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <2>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key-home { - keypad,row = <0>; - keypad,column = <0>; - linux,code = ; - }; - - key-down { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key-up { - keypad,row = <1>; - keypad,column = <0>; - linux,code = ; - }; - - key-menu { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key-back { - keypad,row = <2>; - keypad,column = <0>; - linux,code = ; - }; - - key-enter { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - - broken-cd; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows-pins { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols-pins { - samsung,pins = "gpx1-0", "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-p4note-n8010.dts b/arch/arm/boot/dts/exynos4412-p4note-n8010.dts deleted file mode 100644 index 0932ec5866cc..000000000000 --- a/arch/arm/boot/dts/exynos4412-p4note-n8010.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Galaxy Note 10.1 - N801x (wifi only version) - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos4412-p4note.dtsi" - -/ { - model = "Samsung Galaxy Note 10.1 (GT-N8010/N8013) based on Exynos4412"; - compatible = "samsung,n8010", "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; - chassis-type = "tablet"; - - /* this is the base variant without any kind of modem */ -}; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi deleted file mode 100644 index 0b89d5682f85..000000000000 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ /dev/null @@ -1,1229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based p4note device family base DT. - * Based on exynos4412-midas.dtsi. - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" - -#include -#include -#include -#include -#include -#include "exynos-pinctrl.h" - -/ { - compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - mmc0 = &mshc_0; - mmc2 = &sdhci_2; - mmc3 = &sdhci_3; - }; - - chosen { - stdout-path = &serial_2; - }; - - firmware@204f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204f000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - - key-down { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume down"; - debounce-interval = <10>; - }; - - key-up { - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume up"; - debounce-interval = <10>; - }; - - key-power { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - voltage-regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "TSP_LDO1"; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_reg_gpio_1>; - gpios = <&gpm4 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "TSP_LDO2"; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_reg_gpio_2>; - gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - voltage-regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "TSP_LDO3"; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_reg_gpio_3>; - gpios = <&gpb 7 GPIO_ACTIVE_HIGH>; - startup-delay-us = <20000>; - enable-active-high; - regulator-always-on; - }; - - panel_vdd: voltage-regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "LCD_ENABLE"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable>; - gpios = <&gpc0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&wifi_reset>; - pinctrl-names = "default"; - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; - - battery_cell: battery-cell { - compatible = "simple-battery"; - device-chemistry = "lithium-ion"; - constant-charge-current-max-microamp = <2200000>; - precharge-current-microamp = <250000>; - charge-term-current-microamp = <250000>; - constant-charge-voltage-max-microvolt = <4200000>; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - pinctrl-0 = <&ak8975_irq>; - pinctrl-names = "default"; - interrupt-parent = <&gpm4>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - fuel-gauge@36 { - compatible = "maxim,max17042"; - reg = <0x36>; - pinctrl-0 = <&fuel_alert_irq>; - pinctrl-names = "default"; - interrupt-parent = <&gpx2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - maxim,rsns-microohm = <10000>; - maxim,over-heat-temp = <600>; - maxim,over-volt = <4300>; - }; - }; - - i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpm4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpm4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - #address-cells = <1>; - #size-cells = <0>; - - adc@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - pinctrl-0 = <&stmpe_adc_irq>; - pinctrl-names = "default"; - interrupt-parent = <&gpx0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - st,adc-freq = <3>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,sample-time = <3>; - - adc { - compatible = "st,stmpe-adc"; - #io-channel-cells = <1>; - st,norequest-mask = <0x2f>; - }; - }; - }; - - i2c-gpio-4 { - compatible = "i2c-gpio"; - sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - power_supply: charger@6 { - compatible = "summit,smb347"; - reg = <0x6>; - summit,enable-usb-charging; - summit,enable-charge-control = ; - summit,fast-voltage-threshold-microvolt = <2600000>; - summit,chip-temperature-threshold-celsius = <130>; - summit,usb-current-limit-microamp = <1800000>; - - monitored-battery = <&battery_cell>; - }; - }; - - panel { - compatible = "samsung,ltl101al01"; - pinctrl-0 = <&lvds_nshdn>; - pinctrl-names = "default"; - power-supply = <&panel_vdd>; - enable-gpios = <&gpm0 5 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; - - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_ep>; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-0 = <&led_bl_reset>; - pinctrl-names = "default"; - enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>; - power-supply = <&panel_vdd>; - pwms = <&pwm 1 78770 0>; - brightness-levels = <0 48 128 255>; - num-interpolated-steps = <8>; - default-brightness-level = <12>; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - /* not verified */ - status = "okay"; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&cpu_thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, - <&cpu2 13 13>, <&cpu3 13 13>; - }; - }; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - samsung,invert-vclk; - - port@3 { - reg = <3>; - - fimd_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - pinctrl-0 = <&tsp_rst &tsp_irq>; - pinctrl-names = "default"; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpm0 4 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c_7 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - status = "okay"; - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&max77686_irq>; - pinctrl-names = "default"; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-always-on; - }; - - /* WM8994 audio */ - ldo3_reg: LDO3 { - regulator-name = "VCC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VCC_1.8V_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "ldo7"; - regulator-always-on; - }; - - /* CSI IP block */ - ldo8_reg: LDO8 { - regulator-name = "VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* IR LED on/off */ - ldo9_reg: LDO9 { - regulator-name = "VLED_IC_1.9V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* CSI IP block */ - ldo10_reg: LDO10 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VABB1_1.9V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* USB OTG */ - ldo12_reg: LDO12 { - regulator-name = "VUOTG_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* not connected */ - ldo13_reg: LDO13 { - regulator-name = "ldo13"; - }; - - ldo14_reg: LDO14 { - regulator-name = "VABB2_1.9V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "ldo15"; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "ldo16"; - regulator-always-on; - }; - - /* not connected */ - ldo17_reg: LDO17 { - regulator-name = "ldo17"; - }; - - /* Camera ISX012 */ - ldo18_reg: LDO18 { - regulator-name = "CAM_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Camera S5K6A3 */ - ldo19_reg: LDO19 { - regulator-name = "VT_CORE_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* not connected */ - ldo20_reg: LDO20 { - regulator-name = "ldo20"; - }; - - /* MMC2 */ - ldo21_reg: LDO21 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; - }; - - /* not connected */ - ldo22_reg: LDO22 { - regulator-name = "ldo22"; - }; - - /* ADC */ - ldo23_reg: LDO23 { - regulator-name = "VDD_ADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Camera S5K6A3 */ - ldo24_reg: LDO24 { - regulator-name = "CAM_A2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - regulator-name = "VLED_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Camera ISX012 */ - ldo26_reg: LDO26 { - regulator-name = "3MP_AF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1075000>; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-always-on; - }; - - /* not connected */ - buck8_reg: BUCK8 { - regulator-name = "buck8"; - }; - - buck9_reg: BUCK9 { - regulator-name = "3MP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mshc_0 { - broken-cd; - non-removable; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <0>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - mmc-ddr-1_8v; - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - status = "okay"; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - tsp_reg_gpio_2: tsp-reg-gpio-2-pins { - samsung,pins = "gpb-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - tsp_reg_gpio_3: tsp-reg-gpio-3-pins { - samsung,pins = "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_enable: lcd-enable-pins { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, NONE); - PIN_SLP(gpa0-1, OUT0, NONE); - PIN_SLP(gpa0-2, INPUT, NONE); - PIN_SLP(gpa0-3, INPUT, UP); - PIN_SLP(gpa0-4, INPUT, NONE); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, UP); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, INPUT, NONE); - PIN_SLP(gpb-1, INPUT, NONE); - PIN_SLP(gpb-2, INPUT, NONE); - PIN_SLP(gpb-3, INPUT, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, UP); - PIN_SLP(gpc1-1, PREV, NONE); - PIN_SLP(gpc1-2, INPUT, UP); - PIN_SLP(gpc1-3, INPUT, UP); - PIN_SLP(gpc1-4, INPUT, UP); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, OUT0, NONE); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, DOWN); - PIN_SLP(gpd1-1, INPUT, DOWN); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - - PIN_SLP(gpf0-0, OUT0, NONE); - PIN_SLP(gpf0-1, OUT0, NONE); - PIN_SLP(gpf0-2, OUT0, NONE); - PIN_SLP(gpf0-3, OUT0, NONE); - PIN_SLP(gpf0-4, OUT0, NONE); - PIN_SLP(gpf0-5, OUT0, NONE); - PIN_SLP(gpf0-6, OUT0, NONE); - PIN_SLP(gpf0-7, OUT0, NONE); - - PIN_SLP(gpf1-0, OUT0, NONE); - PIN_SLP(gpf1-1, OUT0, NONE); - PIN_SLP(gpf1-2, OUT0, NONE); - PIN_SLP(gpf1-3, OUT0, NONE); - PIN_SLP(gpf1-4, OUT0, NONE); - PIN_SLP(gpf1-5, OUT0, NONE); - PIN_SLP(gpf1-6, OUT0, NONE); - PIN_SLP(gpf1-7, OUT0, NONE); - - PIN_SLP(gpf2-0, OUT0, NONE); - PIN_SLP(gpf2-1, OUT0, NONE); - PIN_SLP(gpf2-2, OUT0, NONE); - PIN_SLP(gpf2-3, OUT0, NONE); - PIN_SLP(gpf2-4, OUT0, NONE); - PIN_SLP(gpf2-5, OUT0, NONE); - PIN_SLP(gpf2-6, OUT0, NONE); - PIN_SLP(gpf2-7, OUT0, NONE); - - PIN_SLP(gpf3-0, OUT0, NONE); - PIN_SLP(gpf3-1, OUT0, NONE); - PIN_SLP(gpf3-2, OUT0, NONE); - PIN_SLP(gpf3-3, OUT0, NONE); - PIN_SLP(gpf3-4, OUT0, NONE); - PIN_SLP(gpf3-5, OUT0, NONE); - - PIN_SLP(gpj0-0, INPUT, DOWN); - PIN_SLP(gpj0-1, INPUT, DOWN); - PIN_SLP(gpj0-2, INPUT, DOWN); - PIN_SLP(gpj0-3, PREV, NONE); - PIN_SLP(gpj0-4, PREV, NONE); - PIN_SLP(gpj0-5, OUT0, NONE); - PIN_SLP(gpj0-6, OUT0, NONE); - PIN_SLP(gpj0-7, OUT0, NONE); - - PIN_SLP(gpj1-0, OUT0, NONE); - PIN_SLP(gpj1-1, INPUT, DOWN); - PIN_SLP(gpj1-2, PREV, NONE); - PIN_SLP(gpj1-3, OUT0, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; - - sd3_wifi: sd3-wifi-pins { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_shutdown: bt-shutdown-pins { - samsung,pins = "gpl0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart_sel: uart-sel-pins { - samsung,pins = "gpl2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-val = <1>; - /* 0 = CP, 1 = AP (serial output) */ - }; - - led_bl_reset: led-bl-reset-pins { - samsung,pins = "gpm0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - tsp_rst: tsp-rst-pins { - samsung,pins = "gpm0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lvds_nshdn: lvds-nshdn-pins { - samsung,pins = "gpm0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - tsp_irq: tsp-irq-pins { - samsung,pins = "gpm2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - wifi_reset: wifi-reset-pins { - samsung,pins = "gpm3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - tsp_reg_gpio_1: tsp-reg-gpio-1-pins { - samsung,pins = "gpm4-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ak8975_irq: ak8975-irq-pins { - samsung,pins = "gpm4-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - stmpe_adc_irq: stmpe-adc-irq-pins { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - max77686_irq: max77686-irq-pins { - samsung,pins = "gpx0-7"; - samsung,pin-pud = ; - }; - - gpio_keys: gpio-keys-pins { - samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; - samsung,pin-pud = ; - }; - - fuel_alert_irq: fuel-alert-irq-pins { - samsung,pins = "gpx2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - wifi_host_wake: wifi-host-wake-pins { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_host_wakeup: bt-host-wakeup-pins { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_device_wakeup: bt-device-wakeup-pins { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sdhci2_cd: sdhci2-cd-pins { - samsung,pins = "gpx3-4"; - samsung,pin-pud = ; - }; - - sleep1: sleep-state { - PIN_SLP(gpk0-0, PREV, NONE); - PIN_SLP(gpk0-1, PREV, NONE); - PIN_SLP(gpk0-2, PREV, NONE); - PIN_SLP(gpk0-3, PREV, NONE); - PIN_SLP(gpk0-4, PREV, NONE); - PIN_SLP(gpk0-5, PREV, NONE); - PIN_SLP(gpk0-6, PREV, NONE); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpk3-0, OUT0, NONE); - PIN_SLP(gpk3-1, INPUT, NONE); - PIN_SLP(gpk3-2, INPUT, DOWN); - PIN_SLP(gpk3-3, INPUT, NONE); - PIN_SLP(gpk3-4, INPUT, NONE); - PIN_SLP(gpk3-5, INPUT, NONE); - PIN_SLP(gpk3-6, INPUT, NONE); - - PIN_SLP(gpl0-0, OUT0, NONE); - PIN_SLP(gpl0-1, INPUT, NONE); - PIN_SLP(gpl0-2, INPUT, NONE); - PIN_SLP(gpl0-3, INPUT, DOWN); - PIN_SLP(gpl0-4, PREV, NONE); - PIN_SLP(gpl0-6, PREV, NONE); - - PIN_SLP(gpl1-0, OUT0, NONE); - PIN_SLP(gpl1-1, OUT0, NONE); - - PIN_SLP(gpl2-0, INPUT, DOWN); - PIN_SLP(gpl2-1, INPUT, DOWN); - PIN_SLP(gpl2-2, INPUT, DOWN); - PIN_SLP(gpl2-3, INPUT, DOWN); - PIN_SLP(gpl2-4, OUT0, NONE); - PIN_SLP(gpl2-5, INPUT, DOWN); - PIN_SLP(gpl2-6, PREV, NONE); - PIN_SLP(gpl2-7, PREV, NONE); - - PIN_SLP(gpm0-0, PREV, NONE); - PIN_SLP(gpm0-1, OUT0, NONE); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, NONE); - PIN_SLP(gpm0-4, OUT0, NONE); - PIN_SLP(gpm0-5, OUT0, NONE); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, OUT0, NONE); - - PIN_SLP(gpm1-0, INPUT, NONE); - PIN_SLP(gpm1-1, INPUT, NONE); - PIN_SLP(gpm1-2, INPUT, NONE); - PIN_SLP(gpm1-3, INPUT, NONE); - PIN_SLP(gpm1-4, INPUT, NONE); - PIN_SLP(gpm1-5, INPUT, NONE); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, NONE); - PIN_SLP(gpm2-1, INPUT, NONE); - PIN_SLP(gpm2-2, OUT0, NONE); - PIN_SLP(gpm2-3, OUT0, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, PREV, NONE); - PIN_SLP(gpm3-1, PREV, NONE); - PIN_SLP(gpm3-2, PREV, NONE); - PIN_SLP(gpm3-3, OUT1, NONE); - PIN_SLP(gpm3-4, OUT0, DOWN); - PIN_SLP(gpm3-5, PREV, NONE); - PIN_SLP(gpm3-6, PREV, NONE); - PIN_SLP(gpm3-7, OUT0, NONE); - - PIN_SLP(gpm4-0, INPUT, NONE); - PIN_SLP(gpm4-1, INPUT, NONE); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, PREV, NONE); - PIN_SLP(gpm4-5, OUT0, NONE); - PIN_SLP(gpm4-6, OUT0, NONE); - PIN_SLP(gpm4-7, INPUT, DOWN); - - PIN_SLP(gpy0-0, INPUT, DOWN); - PIN_SLP(gpy0-1, INPUT, DOWN); - PIN_SLP(gpy0-2, INPUT, NONE); - PIN_SLP(gpy0-3, INPUT, NONE); - PIN_SLP(gpy0-4, INPUT, NONE); - PIN_SLP(gpy0-5, INPUT, NONE); - - PIN_SLP(gpy1-0, INPUT, DOWN); - PIN_SLP(gpy1-1, INPUT, DOWN); - PIN_SLP(gpy1-2, INPUT, DOWN); - PIN_SLP(gpy1-3, INPUT, DOWN); - - PIN_SLP(gpy2-0, PREV, NONE); - PIN_SLP(gpy2-1, INPUT, DOWN); - PIN_SLP(gpy2-2, INPUT, NONE); - PIN_SLP(gpy2-3, INPUT, NONE); - PIN_SLP(gpy2-4, INPUT, NONE); - PIN_SLP(gpy2-5, INPUT, NONE); - - PIN_SLP(gpy3-0, INPUT, DOWN); - PIN_SLP(gpy3-1, INPUT, DOWN); - PIN_SLP(gpy3-2, INPUT, DOWN); - PIN_SLP(gpy3-3, INPUT, DOWN); - PIN_SLP(gpy3-4, INPUT, DOWN); - PIN_SLP(gpy3-5, INPUT, DOWN); - PIN_SLP(gpy3-6, INPUT, DOWN); - PIN_SLP(gpy3-7, INPUT, DOWN); - - PIN_SLP(gpy4-0, INPUT, DOWN); - PIN_SLP(gpy4-1, INPUT, DOWN); - PIN_SLP(gpy4-2, INPUT, DOWN); - PIN_SLP(gpy4-3, INPUT, DOWN); - PIN_SLP(gpy4-4, INPUT, DOWN); - PIN_SLP(gpy4-5, INPUT, DOWN); - PIN_SLP(gpy4-6, INPUT, DOWN); - PIN_SLP(gpy4-7, INPUT, DOWN); - - PIN_SLP(gpy5-0, INPUT, DOWN); - PIN_SLP(gpy5-1, INPUT, DOWN); - PIN_SLP(gpy5-2, INPUT, DOWN); - PIN_SLP(gpy5-3, INPUT, DOWN); - PIN_SLP(gpy5-4, INPUT, DOWN); - PIN_SLP(gpy5-5, INPUT, DOWN); - PIN_SLP(gpy5-6, INPUT, DOWN); - PIN_SLP(gpy5-7, INPUT, DOWN); - - PIN_SLP(gpy6-0, INPUT, DOWN); - PIN_SLP(gpy6-1, INPUT, DOWN); - PIN_SLP(gpy6-2, INPUT, DOWN); - PIN_SLP(gpy6-3, INPUT, DOWN); - PIN_SLP(gpy6-4, INPUT, DOWN); - PIN_SLP(gpy6-5, INPUT, DOWN); - PIN_SLP(gpy6-6, INPUT, DOWN); - PIN_SLP(gpy6-7, INPUT, DOWN); - }; -}; - -&pinctrl_2 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep2>; - - sleep2: sleep-state { - PIN_SLP(gpz-0, INPUT, DOWN); - PIN_SLP(gpz-1, INPUT, DOWN); - PIN_SLP(gpz-2, INPUT, DOWN); - PIN_SLP(gpz-3, INPUT, DOWN); - PIN_SLP(gpz-4, INPUT, DOWN); - PIN_SLP(gpz-5, INPUT, DOWN); - PIN_SLP(gpz-6, INPUT, DOWN); - }; -}; - -&pinctrl_3 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep3>; - - sleep3: sleep-state { - PIN_SLP(gpv0-0, INPUT, DOWN); - PIN_SLP(gpv0-1, INPUT, DOWN); - PIN_SLP(gpv0-2, INPUT, DOWN); - PIN_SLP(gpv0-3, INPUT, DOWN); - PIN_SLP(gpv0-4, INPUT, DOWN); - PIN_SLP(gpv0-5, INPUT, DOWN); - PIN_SLP(gpv0-6, INPUT, DOWN); - PIN_SLP(gpv0-7, INPUT, DOWN); - - PIN_SLP(gpv1-0, INPUT, DOWN); - PIN_SLP(gpv1-1, INPUT, DOWN); - PIN_SLP(gpv1-2, INPUT, DOWN); - PIN_SLP(gpv1-3, INPUT, DOWN); - PIN_SLP(gpv1-4, INPUT, DOWN); - PIN_SLP(gpv1-5, INPUT, DOWN); - PIN_SLP(gpv1-6, INPUT, DOWN); - PIN_SLP(gpv1-7, INPUT, DOWN); - - PIN_SLP(gpv2-0, INPUT, DOWN); - PIN_SLP(gpv2-1, INPUT, DOWN); - PIN_SLP(gpv2-2, INPUT, DOWN); - PIN_SLP(gpv2-3, INPUT, DOWN); - PIN_SLP(gpv2-4, INPUT, DOWN); - PIN_SLP(gpv2-5, INPUT, DOWN); - PIN_SLP(gpv2-6, INPUT, DOWN); - PIN_SLP(gpv2-7, INPUT, DOWN); - - PIN_SLP(gpv3-0, INPUT, DOWN); - PIN_SLP(gpv3-1, INPUT, DOWN); - PIN_SLP(gpv3-2, INPUT, DOWN); - PIN_SLP(gpv3-3, INPUT, DOWN); - PIN_SLP(gpv3-4, INPUT, DOWN); - PIN_SLP(gpv3-5, INPUT, DOWN); - PIN_SLP(gpv3-6, INPUT, DOWN); - PIN_SLP(gpv3-7, INPUT, DOWN); - - PIN_SLP(gpv4-0, INPUT, DOWN); - PIN_SLP(gpv4-1, INPUT, DOWN); - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&pwm { - pinctrl-0 = <&pwm1_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <1>; - status = "okay"; -}; - -&rtc { - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - status = "okay"; -}; - -&sdhci_3 { - #address-cells = <1>; - #size-cells = <0>; - non-removable; - bus-width = <4>; - mmc-pwrseq = <&wlan_pwrseq>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_wifi>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake>; - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - pinctrl-0 = <&uart0_data &uart0_fctl>; - pinctrl-names = "default"; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; - pinctrl-names = "default"; - - max-speed = <2000000>; - shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "lpo"; - }; -}; - -&serial_2 { - pinctrl-0 = <&uart_sel>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi deleted file mode 100644 index 7f187a3dedcc..000000000000 --- a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4412 PPMU common device tree - * - * Copyright (C) 2015 Samsung Electronics - * Author: Chanwoo Choi - */ - -&ppmu_dmc0 { - status = "okay"; - - events { - ppmu_dmc0_3: ppmu-event3-dmc0 { - event-name = "ppmu-event3-dmc0"; - }; - }; -}; - -&ppmu_dmc1 { - status = "okay"; - - events { - ppmu_dmc1_3: ppmu-event3-dmc1 { - event-name = "ppmu-event3-dmc1"; - }; - }; -}; - -&ppmu_leftbus { - status = "okay"; - - events { - ppmu_leftbus_3: ppmu-event3-leftbus { - event-name = "ppmu-event3-leftbus"; - }; - }; -}; - -&ppmu_rightbus { - status = "okay"; - - events { - ppmu_rightbus_3: ppmu-event3-rightbus { - event-name = "ppmu-event3-rightbus"; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/exynos4412-prime.dtsi deleted file mode 100644 index 3731a225f779..000000000000 --- a/arch/arm/boot/dts/exynos4412-prime.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 Prime SoC device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/* - * Exynos4412 Prime SoC revision supports higher CPU frequencies than - * non-Prime version. Therefore we need to update OPPs table and - * thermal maps accordingly. - */ - -&cpu0_opp_1500 { - /delete-property/turbo-mode; -}; - -&cpu0_opp_table { - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - }; -}; - -&cooling_map0 { - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, - <&cpu2 9 9>, <&cpu3 9 9>; -}; - -&cooling_map1 { - cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, - <&cpu2 15 15>, <&cpu3 15 15>; -}; - -&gpu_opp_table { - opp-533000000 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <1075000>; - }; -}; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts deleted file mode 100644 index 715dfcba1417..000000000000 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based SMDK board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's SMDK4412 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung SMDK evaluation board based on Exynos4412"; - compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - mmc0 = &sdhci_2; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial1:115200n8"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, - <&cpu2 13 13>, <&cpu3 13 13>; - }; - }; -}; - -&keypad { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key-1 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <2>; - }; - - key-2 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <3>; - }; - - key-3 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <4>; - }; - - key-4 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <5>; - }; - - key-5 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <6>; - }; - - key-A { - keypad,row = <2>; - keypad,column = <6>; - linux,code = <30>; - }; - - key-B { - keypad,row = <2>; - keypad,column = <7>; - linux,code = <48>; - }; - - key-C { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <46>; - }; - - key-D { - keypad,row = <2>; - keypad,column = <5>; - linux,code = <32>; - }; - - key-E { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <18>; - }; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows-pins { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols-pins { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts deleted file mode 100644 index 5a2dcdc5c28b..000000000000 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * FriendlyARM's Exynos4412 based TINY4412 board device tree source - * - * Copyright (c) 2013 Alex Ling - * - * Device tree source file for FriendlyARM's TINY4412 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include -#include - -/ { - model = "FriendlyARM TINY4412 board based on Exynos4412"; - compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - mmc0 = &sdhci_2; - }; - - chosen { - stdout-path = &serial_0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "led1"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "led2"; - gpios = <&gpm4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "led3"; - gpios = <&gpm4 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led4 { - label = "led4"; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - panel { - compatible = "innolux,at070tn92"; - power-supply = <&vddq_lcd>; - - port { - panel_input: endpoint { - remote-endpoint = <&lcdc_output>; - }; - }; - }; - - vddq_lcd: regulator-vddq-lcd { - compatible = "regulator-fixed"; - regulator-name = "vddq-lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&cpu_thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, - <&cpu2 13 13>, <&cpu3 13 13>; - }; - }; -}; - -&fimd { - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@3 { - reg = <3>; - lcdc_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts deleted file mode 100644 index 3c2d2a7836da..000000000000 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based Trats 2 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats 2 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412-galaxy-s3.dtsi" - -/ { - model = "Samsung Trats 2 based on Exynos4412"; - compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - chassis-type = "handset"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = "serial2:115200n8"; - }; -}; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi deleted file mode 100644 index dcbe0ce6180f..000000000000 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4x12.dtsi" - -/ { - compatible = "samsung,exynos4412", "samsung,exynos4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa02>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa03>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - opp-suspend; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - cpu0_opp_1500: opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; -}; - -&clock { - compatible = "samsung,exynos4412-clock"; -}; - -&combiner { - samsung,combiner-nr = <20>; -}; - -&gic { - cpu-offset = <0x4000>; -}; - -&pmu { - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - -&pmu_system_controller { - compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon"; -}; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi deleted file mode 100644 index 04935fbe2f2a..000000000000 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ /dev/null @@ -1,979 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device - * tree nodes in this file. - */ - -#include "exynos-pinctrl.h" - -#define PIN_SLP(_pin, _mode, _pull) \ - pin- ## _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -&pinctrl_0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus-pins { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus-pins { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus-pins { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus-pins { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl-pins { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus-pins { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk-pins { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi1_clk: mipi1-clk-pins { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk-pins { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16-pins { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18-pins { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24-pins { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ldi: lcd-ldi-pins { - samsung,pins = "gpf3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io-pins { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active-pins { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle-pins { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpk0: gpk0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk-pins { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd-pins { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd-pins { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1-pins { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4-pins { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8-pins { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8-pins { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk-pins { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd-pins { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd-pins { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1-pins { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4-pins { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io-pins { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active-pins { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle-pins { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0-pins { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8-pins { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15-pins { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16-pins { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0-pins { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1-pins { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart-pins { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec-pins { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz: gpz-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpv0: gpv0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_bus: c2c-bus-pins { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", - "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", - "gpv4-0", "gpv4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi deleted file mode 100644 index 84c1db221c98..000000000000 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ /dev/null @@ -1,664 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4x12 SoC series device nodes are listed in this file. - * Particular SoCs from Exynos4x12 series can include this file and provide - * values for SoCs specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4x12 SoCs. As device tree coverage for Exynos4x12 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4.dtsi" - -#include "exynos4-cpu-thermal.dtsi" - -/ { - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - fimc-lite0 = &fimc_lite_0; - fimc-lite1 = &fimc_lite_1; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - - bus_acp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - }; - - bus_c2c: bus-c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - samsung,data-clock-ratio = <4>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - interconnects = <&bus_leftbus &bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - - bus_display_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - - bus_fsys_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - interconnects = <&bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - - bus_peri_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - opp-suspend; - }; - }; - - bus_leftbus_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - opp-suspend; - }; - }; - - soc: soc { - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; - }; - - pinctrl_3: pinctrl@106e0000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106e0000 0x1000>; - interrupts = ; - }; - - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_isp: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023ca0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - l2c: cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - clock: clock-controller@10030000 { - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; - - timer@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <&combiner 12 5>, - <&combiner 12 6>, - <&combiner 12 7>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos4212-adc"; - reg = <0x126c0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10a40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122a0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@123b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@123c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123c0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, - <&isp_clock CLK_ISP_FIMC_LITE1>; - #iommu-cells = <0>; - }; - }; -}; - -&combiner { - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; - }; - - fimc_lite_1: fimc-lite@123a0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123a0000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; - }; - - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; - interrupts = , - ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE1>, - <&isp_clock CLK_ISP_PPMUISPX>, - <&isp_clock CLK_ISP_PPMUISPMX>, - <&isp_clock CLK_ISP_FIMC_ISP>, - <&isp_clock CLK_ISP_FIMC_DRC>, - <&isp_clock CLK_ISP_FIMC_FD>, - <&isp_clock CLK_ISP_MCUISP>, - <&isp_clock CLK_ISP_GICISP>, - <&isp_clock CLK_ISP_MCUCTL_ISP>, - <&isp_clock CLK_ISP_PWM_ISP>, - <&isp_clock CLK_ISP_DIV_ISP0>, - <&isp_clock CLK_ISP_DIV_ISP1>, - <&isp_clock CLK_ISP_DIV_MCUISP0>, - <&isp_clock CLK_ISP_DIV_MCUISP1>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK200>, - <&clock CLK_DIV_ACLK400_MCUISP>, - <&clock CLK_UART_ISP_SCLK>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "mpll", "aclk200", - "aclk400mcuisp", "div_aclk200", - "div_aclk400mcuisp", "uart"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - pmu@10020000 { - reg = <0x10020000 0x3000>; - }; - - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&isp_clock CLK_ISP_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&exynos_usbphy { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; -}; - -&fimc_0 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_1 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_2 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; -}; - -&fimc_3 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; -}; - -&gpu { - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <875000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <900000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <950000>; - }; - opp-440000000 { - opp-hz = /bits/ 64 <440000000>; - opp-microvolt = <1025000>; - }; - }; -}; - -&hdmi { - compatible = "samsung,exynos4212-hdmi"; -}; - -&jpeg_codec { - compatible = "samsung,exynos4212-jpeg"; -}; - -&rotator { - compatible = "samsung,exynos4212-rotator"; -}; - -&mixer { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; - interconnects = <&bus_display &bus_dmc>; -}; - -&pmu_system_controller { - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&tmu { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100c0000 0x100>; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - status = "disabled"; -}; - -#include "exynos4x12-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi deleted file mode 100644 index 4a17a19586bb..000000000000 --- a/arch/arm/boot/dts/exynos5.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5 SoC series common device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular - * SoCs from Exynos5 series can include this file and provide values for SoCs - * specific bindings. - */ - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - chipid: chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sromc: memory-controller@12250000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12250000 0x14>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x2000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = ; - }; - - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - - serial_0: serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c00000 0x100>; - interrupts = ; - }; - - serial_1: serial@12c10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c10000 0x100>; - interrupts = ; - }; - - serial_2: serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c20000 0x100>; - interrupts = ; - }; - - serial_3: serial@12c30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c30000 0x100>; - interrupts = ; - }; - - i2c_0: i2c@12c60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12c60000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12c70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12c70000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12c80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12c80000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12c90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12c90000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - pwm: pwm@12dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12dd0000 0x100>; - interrupts = , - , - , - , - ; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - }; - - rtc: rtc@101e0000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x101e0000 0x100>; - interrupts = , - ; - status = "disabled"; - }; - - fimd: fimd@14400000 { - compatible = "samsung,exynos5250-fimd"; - interrupt-parent = <&combiner>; - reg = <0x14400000 0x40000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <18 4>, <18 5>, <18 6>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dp: dp-controller@145b0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x1000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - status = "disabled"; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = ; - }; - - prng: rng@10830400 { - compatible = "samsung,exynos5250-prng"; - reg = <0x10830400 0x200>; - }; - - trng: rng@10830600 { - compatible = "samsung,exynos5250-trng"; - reg = <0x10830600 0x100>; - }; - - g2d: g2d@10850000 { - compatible = "samsung,exynos5250-g2d"; - reg = <0x10850000 0x1000>; - interrupts = ; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts deleted file mode 100644 index d586189966da..000000000000 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ /dev/null @@ -1,643 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5250 based Arndale board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Insignal Arndale evaluation board based on Exynos5250"; - compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-menu { - label = "SW-TACT2"; - gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-home { - label = "SW-TACT3"; - gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-up { - label = "SW-TACT4"; - gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-down { - label = "SW-TACT5"; - gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-back { - label = "SW-TACT6"; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-wakeup { - label = "SW-TACT7"; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - /* - * For unknown reasons HDMI-DDC does not work with Exynos I2C - * controllers. Lets use software I2C over GPIO pins as a workaround. - */ - i2c_ddc: i2c-10 { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_gpio_bus>; - sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - }; - - panel: panel { - compatible = "boe,hv070wsa-100"; - power-supply = <&vcc_3v3_reg>; - enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; - port { - panel_ep: endpoint { - remote-endpoint = <&bridge_out_ep>; - }; - }; - }; - - main_dc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "MAIN_DC"; - regulator-always-on; - }; - - mmc_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_MMC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_hdmi_en: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "hdmi-en"; - regulator-always-on; - }; - - vcc_1v2_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_1v8_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_3v3_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "samsung,arndale-wm1811"; - samsung,audio-cpu = <&i2s0>; - samsung,audio-codec = <&wm1811>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - // SMSC USB3503 connected in hardware only mode as a PHY - usb_hub: usb-hub { - compatible = "smsc,usb3503a"; - - reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&clock { - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <49152000>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dsi_0 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,pll-clock-frequency = <24000000>; - samsung,burst-clock-frequency = <320000000>; - samsung,esc-clock-frequency = <10000000>; - status = "okay"; - - bridge@0 { - reg = <0>; - compatible = "toshiba,tc358764"; - vddc-supply = <&vcc_1v2_reg>; - vddio-supply = <&vcc_1v8_reg>; - vddlvds-supply = <&vcc_3v3_reg>; - reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - bridge_out_ep: endpoint { - remote-endpoint = <&panel_ep>; - }; - }; - }; - }; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - status = "okay"; - ddc = <&i2c_ddc>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - samsung,i2c-slave-addr = <0x66>; - - pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s5m8767_irq>; - wakeup-source; - - vinb1-supply = <&main_dc_reg>; - vinb2-supply = <&main_dc_reg>; - vinb3-supply = <&main_dc_reg>; - vinb4-supply = <&main_dc_reg>; - vinb5-supply = <&main_dc_reg>; - vinb6-supply = <&main_dc_reg>; - vinb7-supply = <&main_dc_reg>; - vinb8-supply = <&main_dc_reg>; - vinb9-supply = <&main_dc_reg>; - - vinl1-supply = <&buck7_reg>; - vinl2-supply = <&buck7_reg>; - vinl3-supply = <&buck7_reg>; - vinl4-supply = <&main_dc_reg>; - vinl5-supply = <&main_dc_reg>; - vinl6-supply = <&main_dc_reg>; - vinl7-supply = <&main_dc_reg>; - vinl8-supply = <&buck8_reg>; - vinl9-supply = <&buck8_reg>; - - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, - <&gpd1 1 GPIO_ACTIVE_HIGH>, - <&gpd1 2 GPIO_ACTIVE_HIGH>; - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; - - s5m8767_osc: clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "s5m8767_ap", "unused1", "unused2"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_28IO_DP_1.35V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_COMMON1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_IOPERI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_XPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_COMMON2_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_33ON_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_COMMON3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_ABB2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_COMMON4_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDQ_MMC2_3_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo22_reg: LDO22 { - regulator-name = "EXT_33_OFF"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; - }; - - ldo23_reg: LDO23 { - regulator-name = "EXT_28_OFF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo25_reg: LDO25 { - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; - }; - - ldo26_reg: LDO26 { - regulator-name = "EXT_18_OFF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1.35V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1355000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck7_reg: BUCK7 { - regulator-name = "PVDD_BUCK7"; - regulator-always-on; - op_mode = <1>; - }; - - buck8_reg: BUCK8 { - regulator-name = "PVDD_BUCK8"; - regulator-always-on; - op_mode = <1>; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_33_OFF_EXT1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - }; - }; -}; - -&i2c_3 { - status = "okay"; - - wm1811: audio-codec@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "MCLK1"; - - AVDD2-supply = <&main_dc_reg>; - CPVDD-supply = <&main_dc_reg>; - DBVDD1-supply = <&main_dc_reg>; - DBVDD2-supply = <&main_dc_reg>; - DBVDD3-supply = <&main_dc_reg>; - LDO1VDD-supply = <&main_dc_reg>; - SPKVDD1-supply = <&main_dc_reg>; - SPKVDD2-supply = <&main_dc_reg>; - - wlf,ldo1ena-gpios = <&gpb0 0 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena-gpios = <&gpb0 1 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_9 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&i2s0_bus { - samsung,pin-drv = ; -}; - -&mali { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; -}; - -&pinctrl_0 { - s5m8767_irq: s5m8767-irq-pins { - samsung,pins = "gpx3-2"; - samsung,pin-pud = ; - }; -}; - -&rtc { - clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; -}; - -&sata_phy_i2c { - status = "okay"; -}; - -&usbdrd { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi deleted file mode 100644 index d956540a2d88..000000000000 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ /dev/null @@ -1,833 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device - * tree nodes in this file. - */ - -#include "exynos-pinctrl.h" - -&pinctrl_0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc4: gpc4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_hs_bus: i2c2-hs-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_gpio_bus: i2c2-gpio-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_hs_bus: i2c3-hs-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus-pins { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus-pins { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus-pins { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus-pins { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus-pins { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus-pins { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus-pins { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_hs_bus: i2c0-hs-bus-pins { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_hs_bus: i2c1-hs-bus-pins { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpc3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpc3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8-pins { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk-pins { - samsung,pins = "gpc4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd-pins { - samsung,pins = "gpc4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd-pins { - samsung,pins = "gpc4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1-pins { - samsung,pins = "gpc4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4-pins { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd: dp-hpd-pins { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec-pins { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd: hdmi-hpd-pins { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; -}; - -&pinctrl_1 { - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a-pins { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b-pins { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c2_bus: cam-i2c2-bus-pins { - samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus-pins { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus-pins { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus-pins { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus-pins { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_bayrgb_bus: cam-bayrgb-bus-pins { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0", "gpg2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a: cam-port-a-pins { - samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", - "gph1-0", "gph1-1", "gph1-2", "gph1-3", - "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpv0: gpv0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_rxd: c2c-rxd-pins { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - c2c_txd: c2c-txd-pins { - samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpz: gpz-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts deleted file mode 100644 index bb623726ef1e..000000000000 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ /dev/null @@ -1,430 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK5250 board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Samsung SMDK5250 board based on Exynos5250"; - compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial2:115200n8"; - }; - - vdd: fixed-regulator-vdd { - compatible = "regulator-fixed"; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - dbvdd: fixed-regulator-dbvdd { - compatible = "regulator-fixed"; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spkvdd: fixed-regulator-spkvdd { - compatible = "regulator-fixed"; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound { - compatible = "samsung,smdk-wm8994"; - - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&wm8994>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - - codec_mclk: codec-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16934000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; - }; - }; -}; - -&ehci { - samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - status = "okay"; - ddc = <&i2c_2>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - - eeprom@50 { - compatible = "samsung,s524ad0xd1", "atmel,24c128"; - reg = <0x50>; - }; - - max77686: pmic@9 { - compatible = "maxim,max77686"; - reg = <0x09>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - #clock-cells = <1>; - wakeup-source; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.2V_LDO_OUT2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "P2.8V_LDO_OUT4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.8V_LDO_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "P1.1V_LDO_OUT6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - - eeprom@51 { - compatible = "samsung,s524ad0xd1", "atmel,24c128"; - reg = <0x51>; - }; - - wm8994: audio-codec@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - - clocks = <&codec_mclk>; - clock-names = "MCLK1"; - - AVDD2-supply = <&vdd>; - CPVDD-supply = <&vdd>; - DBVDD-supply = <&dbvdd>; - SPKVDD1-supply = <&spkvdd>; - SPKVDD2-supply = <&spkvdd>; - }; -}; - -&i2c_2 { - status = "okay"; - /* used by HDMI DDC */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_9 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; -}; - -&i2s0 { - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; -}; - -&sata_phy_i2c { - status = "okay"; -}; - -&spi_1 { - status = "okay"; - cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25x80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; -}; - -&pinctrl_0 { - max77686_irq: max77686-irq-pins { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&usbdrd { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi deleted file mode 100644 index 59b2cc35c37b..000000000000 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ /dev/null @@ -1,718 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - */ - -#include -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - aliases { - i2c104 = &i2c_104; - mmc0 = &mmc_0; /* eMMC */ - mmc1 = &mmc_2; /* SD */ - mmc2 = &mmc_3; /* WiFi */ - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=tty1"; - stdout-path = "serial3:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power-key { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - vbat: vbat-fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - }; - - i2c-arbitrator { - compatible = "i2c-arb-gpio-challenge"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c_4>; - - our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; - their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; - slew-delay-us = <10>; - wait-retry-us = <3000>; - wait-free-us = <50000>; - - pinctrl-names = "default"; - pinctrl-0 = <&arb_our_claim &arb_their_claim>; - - /* Use ID 104 as a hint that we're on physical bus 4 */ - i2c_104: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - }; - - cros_ec: embedded-controller@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - wakeup-source; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - dcdc1 { - ti,enable-ext-control; - }; - dcdc2 { - ti,enable-ext-control; - }; - dcdc3 { - ti,enable-ext-control; - }; - fet1: fet1 { - regulator-name = "vcd_led"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet4 { - regulator-name = "sdcard"; - ti,overcurrent-wait = <3>; - }; - fet5 { - regulator-name = "camout"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet6: fet6 { - regulator-name = "lcd_vdd"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - ldo1 { - }; - ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; - - sound { - samsung,i2s-controller = <&i2s0>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_en>; - enable-active-high; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - power-supply = <&fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - mmc3_pwrseq: mmc3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ - <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; -}; - -&clock { - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <49152000>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hdmicec { - status = "okay"; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad@67 { - reg = <0x67>; - compatible = "cypress,cyapa"; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = ; -}; - -&i2c_2 { - status = "okay"; - /* used by HDMI DDC */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - ptn3460: lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; - edid-emulation = <5>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&mali { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - non-removable; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; -}; - -/* uSD card */ -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; - cap-sd-highspeed; -}; - -/* - * On Snow we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - * - * WiFi SDIO module - */ -&mmc_3 { - status = "okay"; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc3_pwrseq>; -}; - -&pinctrl_0 { - wifi_en: wifi-en-pins { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wifi_rst: wifi-rst-pins { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq-pins { - samsung,pins = "gpx1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq-pins { - samsung,pins = "gpx1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq-pins { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_vbus_en: usb3-vbus-en-pins { - samsung,pins = "gpx2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77686_irq: max77686-irq-pins { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq-pins { - samsung,pins = "gpx3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - arb_their_claim: arb-their-claim-pins { - samsung,pins = "gpe0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - arb_our_claim: arb-our-claim-pins { - samsung,pins = "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sd3_bus4 { - samsung,pin-drv = ; -}; - -&sd3_clk { - samsung,pin-drv = ; -}; - -&sd3_cmd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; - cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; -}; - -&usbdrd { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; - -&usbdrd_dwc3 { - dr_mode = "host"; -}; - -&usbdrd_phy { - vbus-supply = <&usb3_vbus_reg>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts deleted file mode 100644 index 3d32c3476e84..000000000000 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Snow Rev 5+ board device tree source - * - * Copyright (c) 2012 Google, Inc - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5250-snow-common.dtsi" - -/ { - model = "Google Snow Rev 5+"; - compatible = "google,snow-rev5", "samsung,exynos5250", - "samsung,exynos5"; - chassis-type = "laptop"; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Snow-I2S-MAX98090"; - samsung,audio-codec = <&max98090>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98090>, <&hdmi>; - }; - }; -}; - -&i2c_7 { - max98090: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <4 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&pinctrl_0 { - max98090_irq: max98090-irq-pins { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts deleted file mode 100644 index 906aa7aae710..000000000000 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - */ - -/dts-v1/; -#include "exynos5250-snow-common.dtsi" - -/ { - model = "Google Snow"; - compatible = "google,snow-rev4", "google,snow", "samsung,exynos5250", - "samsung,exynos5"; - chassis-type = "laptop"; - - sound { - compatible = "google,snow-audio-max98095"; - - samsung,model = "Snow-I2S-MAX98095"; - samsung,audio-codec = <&max98095>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98095 0>, <&hdmi>; - }; - }; -}; - -&i2c_7 { - max98095: audio-codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; - pinctrl-names = "default"; - pinctrl-0 = <&max98095_en>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <1>; - }; -}; - -&pinctrl_0 { - max98095_en: max98095-en-pins { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts deleted file mode 100644 index c12bb17631b7..000000000000 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Spring board device tree source - * - * Copyright (c) 2013 Google, Inc - * Copyright (c) 2014 SUSE LINUX Products GmbH - */ - -/dts-v1/; -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Google Spring"; - compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; - chassis-type = "laptop"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_1; - }; - - chosen { - bootargs = "console=tty1"; - stdout-path = "serial3:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq>, <&lid_irq>; - - power-key { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - usb-hub { - compatible = "smsc,usb3503a"; - reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hsic_reset>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <1>; - hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - hdmi-en-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; - wakeup-source; - - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ - <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ - <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ - - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ - <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ - <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ - - /* - * The following arrays of DVS voltages are not used, since we are - * not using GPIOs to control PMIC bucks, but they must be defined - * to please the driver. - */ - s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - s5m8767_osc: clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "en32khz_ap", - "en32khz_cp", - "en32khz_bt"; - }; - - regulators { - ldo4_reg: LDO4 { - regulator-name = "P1.0V_LDO_OUT4"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.0V_LDO_OUT5"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_mydp"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo17_reg: LDO17 { - regulator-name = "P2.8V_LDO_OUT17"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo25_reg: LDO25 { - regulator-name = "vdd_bridge"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - op_mode = <3>; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.2V_BUCK_OUT6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <0>; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_ummc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = ; -}; - -&i2c_2 { - status = "okay"; - /* used by HDMI DDC */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - cros_ec: embedded-controller@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - }; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - temperature-sensor@4c { - compatible = "gmt,g781"; - reg = <0x4c>; - }; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; -}; - -&i2s0 { - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; -}; - -/* - * On Spring we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ -&mmc_1 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - s5m8767_dvs: s5m8767-dvs-pins { - samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp-hpd-pins { - samsung,pins = "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq-pins { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq-pins { - samsung,pins = "gpx1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq-pins { - samsung,pins = "gpx1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s5m8767_ds: s5m8767-ds-pins { - samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s5m8767_irq: s5m8767-irq-pins { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq-pins { - samsung,pins = "gpx3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - hsic_reset: hsic-reset-pins { - samsung,pins = "gpe1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sd1_bus4 { - samsung,pin-drv = ; -}; - -&sd1_cd { - samsung,pin-drv = ; -}; - -&sd1_clk { - samsung,pin-drv = ; -}; - -&sd1_cmd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; -}; - -&usbdrd { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi deleted file mode 100644 index 99c84bebf25a..000000000000 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ /dev/null @@ -1,1225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5250 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5250 SoC device nodes are listed in this file. - * Exynos5250 based board files can include this file and provide - * values for board specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, - * additional nodes can be added to this file. - */ - -#include -#include "exynos5.dtsi" -#include "exynos4-cpu-thermal.dtsi" -#include - -/ { - compatible = "samsung,exynos5250", "samsung,exynos5"; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - gsc0 = &gsc_0; - gsc1 = &gsc_1; - gsc2 = &gsc_2; - gsc3 = &gsc_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - i2c9 = &i2c_9; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <925000>; - clock-latency-ns = <140000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - clock-latency-ns = <140000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <1012500>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1050000>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1075000>; - clock-latency-ns = <140000>; - opp-suspend; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1125000>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1150000>; - clock-latency-ns = <140000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <140000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <140000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <140000>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, <22 4>; - }; - - soc: soc { - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x30000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_gsc: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - label = "GSC"; - }; - - pd_mfc: power-domain@10044040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044040 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_g3d: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_disp1: power-domain@100440a0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440a0 0x20>; - #power-domain-cells = <0>; - label = "DISP1"; - }; - - pd_mau: power-domain@100440c0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440c0 0x20>; - #power-domain-cells = <0>; - label = "MAU"; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0c>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - power-domains = <&pd_mau>; - }; - - timer@101c0000 { - compatible = "samsung,exynos5250-mct", - "samsung,exynos4210-mct"; - reg = <0x101c0000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&combiner 23 3>, - <&combiner 23 4>, - <&combiner 25 2>, - <&combiner 25 3>, - <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@13400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = ; - }; - - pinctrl_3: pinctrl@3860000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = ; - power-domains = <&pd_mau>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - - dp_phy: dp-phy { - compatible = "samsung,exynos5250-dp-video-phy"; - #phy-cells = <0>; - }; - - mipi_phy: mipi-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - }; - }; - - watchdog@101d0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101d0000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v6"; - reg = <0x11000000 0x10000>; - interrupts = ; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - rotator: rotator@11c00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11c00000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - mali: gpu@11800000 { - compatible = "samsung,exynos5250-mali", "arm,mali-t604"; - reg = <0x11800000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clock CLK_G3D>; - clock-names = "core"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&pd_g3d>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <925000>; - }; - opp-266000000 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <1025000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <1075000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1125000>; - }; - opp-450000000 { - opp-hz = /bits/ 64 <450000000>; - opp-microvolt = <1150000>; - }; - opp-533000000 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <1250000>; - }; - }; - }; - - tmu: tmu@10060000 { - compatible = "samsung,exynos5250-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - sata: sata@122f0000 { - compatible = "snps,dwc-ahci"; - reg = <0x122f0000 0x1ff>; - interrupts = ; - clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; - clock-names = "sata", "pclk"; - phys = <&sata_phy>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - status = "disabled"; - }; - - sata_phy: sata-phy@12170000 { - compatible = "samsung,exynos5250-sata-phy"; - reg = <0x12170000 0x1ff>; - clocks = <&clock CLK_SATA_PHYCTRL>; - clock-names = "sata_phyctrl"; - #phy-cells = <0>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - i2c_4: i2c@12ca0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12ca0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@12cb0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12cb0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@12cc0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12cc0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@12cd0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12cd0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - i2c_8: i2c@12ce0000 { - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x12ce0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - - hdmiphy: hdmi-phy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - i2c_9: i2c@121d0000 { - compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121d0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SATA_PHYI2C>; - clock-names = "i2c"; - status = "disabled"; - - sata_phy_i2c: sata-phy-i2c@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - status = "disabled"; - }; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d20000 0x100>; - interrupts = ; - dmas = <&pdma0 5>, <&pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d30000 0x100>; - interrupts = ; - dmas = <&pdma1 5>, <&pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d40000 0x100>; - interrupts = ; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x1000>; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x1000>; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_3: mmc@12230000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12230000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - status = "disabled"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10>, - <&pdma0 9>, - <&pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - power-domains = <&pd_mau>; - #clock-cells = <1>; - #sound-dai-cells = <1>; - }; - - i2s1: i2s@12d60000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12d60000 0x100>; - dmas = <&pdma1 12>, - <&pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - power-domains = <&pd_mau>; - #sound-dai-cells = <1>; - }; - - i2s2: i2s@12d70000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12d70000 0x100>; - dmas = <&pdma0 12>, - <&pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - power-domains = <&pd_mau>; - #sound-dai-cells = <1>; - }; - - usbdrd: usb@12000000 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USB3>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000000 0x10000>; - - usbdrd_dwc3: usb@0 { - compatible = "snps,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy: phy@12100000 { - compatible = "samsung,exynos5250-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - ehci: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = ; - - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - phys = <&usb2_phy_gen 1>; - phy-names = "host"; - }; - - ohci: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = ; - - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - phys = <&usb2_phy_gen 1>; - phy-names = "host"; - }; - - usb2_phy_gen: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - - pdma0: dma-controller@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121a0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pdma1: dma-controller@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121b0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - mdma0: dma-controller@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - mdma1: dma-controller@11c10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11c10000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc0>; - }; - - gsc_1: gsc@13e10000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc1>; - }; - - gsc_2: gsc@13e20000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e20000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL2>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc2>; - }; - - gsc_3: gsc@13e30000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e30000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL3>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc3>; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos4212-hdmi"; - reg = <0x14530000 0x70000>; - power-domains = <&pd_disp1>; - interrupts = ; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - samsung,syscon-phandle = <&pmu_system_controller>; - phy = <&hdmiphy>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmicec: cec@101b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x101b0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5250-mixer"; - reg = <0x14450000 0x10000>; - power-domains = <&pd_disp1>; - interrupts = ; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - dsi_0: dsi@14500000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = ; - samsung,power-domain = <&pd_disp1>; - phys = <&mipi_phy 3>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "sclk_mipi"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x12d10000 0x100>; - interrupts = ; - clocks = <&clock CLK_ADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10a60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@11d40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11d40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg: sysmmu@11f20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11f20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@13260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@13270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@132a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132a0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_scc: sysmmu@13280000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13280000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_scp: sysmmu@13290000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13290000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@132b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_MCU>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_odc: sysmmu@132c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132c0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ODC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_dis0: sysmmu@132d0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132d0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_dis1: sysmmu@132e0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132e0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <9 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS1>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_3dnr: sysmmu@132f0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132f0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_3DNR>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@13c40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13c40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@13c50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13c50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 1>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; - - sysmmu_gsc0: sysmmu@13e80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13e80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_gsc1: sysmmu@13e90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13e90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_gsc2: sysmmu@13ea0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13ea0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_gsc3: sysmmu@13eb0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13eb0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 6>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1: sysmmu@14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - #iommu-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - /* - * Unfortunately we need this since some versions - * of U-Boot on Exynos don't set the CNTFRQ register, - * so we need the value from DT. - */ - clock-frequency = <24000000>; - }; -}; - -&cpu_thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu>; - - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>; - }; - }; -}; - -&dp { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_DP>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; -}; - -&fimd { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - iommus = <&sysmmu_fimd1>; -}; - -&g2d { - iommus = <&sysmmu_g2d>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - status = "okay"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&prng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 13>, <&pdma0 14>; - dma-names = "rx", "tx"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&trng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -#include "exynos5250-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi deleted file mode 100644 index d15494b4bda9..000000000000 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device - * tree nodes in this file. - */ - -#include "exynos-pinctrl.h" - -&pinctrl_0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb5: gpb5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_vbus0_en: usb3-vbus0-en-pins { - samsung,pins = "gpa2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif1_bus: spdif1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus-pins { - samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_hs_bus: i2c0-hs-bus-pins { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_hs_bus: i2c1-hs-bus-pins { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_hs_bus: i2c2-hs-bus-pins { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_hs_bus: i2c3-hs-bus-pins { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus-pins { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus-pins { - samsung,pins = "gpb4-2", "gpb4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus-pins { - samsung,pins = "gpb4-4", "gpb4-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus-pins { - samsung,pins = "gpb4-6", "gpb4-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c8_bus: i2c8-bus-pins { - samsung,pins = "gpb5-0", "gpb5-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c9_bus: i2c9-bus-pins { - samsung,pins = "gpb5-2", "gpb5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c10_bus: i2c10-bus-pins { - samsung,pins = "gpb5-4", "gpb5-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c11_bus: i2c11-bus-pins { - samsung,pins = "gpb5-6", "gpb5-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_a: cam-gpio-a-pins { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b-pins { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus-pins { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus-pins { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus-pins { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus-pins { - samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs-pins { - samsung,pins = "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpc1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpc1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8-pins { - samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz0: gpz0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpz1: gpz1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts deleted file mode 100644 index d072a7398866..000000000000 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung XYREF5260 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5260.dtsi" - -/ { - model = "Samsung XYREF5260 board based on Exynos5260"; - compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - ioclk_pcm: clock-pcm-ext { - compatible = "fixed-clock"; - clock-frequency = <2048000>; - clock-output-names = "ioclk_pcm_extclk"; - #clock-cells = <0>; - }; - - ioclk_i2s: clock-i2s-cd { - compatible = "fixed-clock"; - clock-frequency = <147456000>; - clock-output-names = "ioclk_i2s_cdclk"; - #clock-cells = <0>; - }; - - ioclk_spdif: clock-spdif-ext { - compatible = "fixed-clock"; - clock-frequency = <49152000>; - clock-output-names = "ioclk_spdif_extclk"; - #clock-cells = <0>; - }; - - xrtcxti: xrtcxti { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xrtcxti"; - #clock-cells = <0>; - }; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - cap-mmc-highspeed; - mmc-hs200-1_8v; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - disable-wp; -}; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi deleted file mode 100644 index a97449b4640c..000000000000 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ /dev/null @@ -1,554 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5260 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include -#include - -/ { - compatible = "samsung,exynos5260", "samsung,exynos5"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &hsi2c_0; - i2c1 = &hsi2c_1; - i2c2 = &hsi2c_2; - i2c3 = &hsi2c_3; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - core2 { - cpu = <&cpu4>; - }; - core3 { - cpu = <&cpu5>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cci-control-port = <&cci_control1>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cci-control-port = <&cci_control1>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control0>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control0>; - }; - - cpu4: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control0>; - }; - - cpu5: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cci-control-port = <&cci_control0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock_top: clock-controller@10010000 { - compatible = "samsung,exynos5260-clock-top"; - reg = <0x10010000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_mif MIF_DOUT_MEM_PLL>, - <&clock_mif MIF_DOUT_BUS_PLL>, - <&clock_mif MIF_DOUT_MEDIA_PLL>; - clock-names = "fin_pll", - "dout_mem_pll", - "dout_bus_pll", - "dout_media_pll"; - }; - - clock_peri: clock-controller@10200000 { - compatible = "samsung,exynos5260-clock-peri"; - reg = <0x10200000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&ioclk_pcm>, - <&ioclk_i2s>, - <&ioclk_spdif>, - <&fin_pll>, - <&clock_top TOP_DOUT_ACLK_PERI_66>, - <&clock_top TOP_DOUT_SCLK_PERI_UART0>, - <&clock_top TOP_DOUT_SCLK_PERI_UART1>, - <&clock_top TOP_DOUT_SCLK_PERI_UART2>, - <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>, - <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>, - <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>, - <&clock_top TOP_DOUT_ACLK_PERI_AUD>; - clock-names = "fin_pll", - "ioclk_pcm_extclk", - "ioclk_i2s_cdclk", - "ioclk_spdif_extclk", - "phyclk_hdmi_phy_ref_cko", - "dout_aclk_peri_66", - "dout_sclk_peri_uart0", - "dout_sclk_peri_uart1", - "dout_sclk_peri_uart2", - "dout_sclk_peri_spi0_b", - "dout_sclk_peri_spi1_b", - "dout_sclk_peri_spi2_b", - "dout_aclk_peri_aud"; - }; - - clock_egl: clock-controller@10600000 { - compatible = "samsung,exynos5260-clock-egl"; - reg = <0x10600000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_mif MIF_DOUT_BUS_PLL>; - clock-names = "fin_pll", - "dout_bus_pll"; - }; - - clock_kfc: clock-controller@10700000 { - compatible = "samsung,exynos5260-clock-kfc"; - reg = <0x10700000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_mif MIF_DOUT_MEDIA_PLL>; - clock-names = "fin_pll", - "dout_media_pll"; - }; - - clock_g2d: clock-controller@10a00000 { - compatible = "samsung,exynos5260-clock-g2d"; - reg = <0x10a00000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_top TOP_DOUT_ACLK_G2D_333>; - clock-names = "fin_pll", - "dout_aclk_g2d_333"; - }; - - clock_mif: clock-controller@10ce0000 { - compatible = "samsung,exynos5260-clock-mif"; - reg = <0x10ce0000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>; - clock-names = "fin_pll"; - }; - - clock_mfc: clock-controller@11090000 { - compatible = "samsung,exynos5260-clock-mfc"; - reg = <0x11090000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_top TOP_DOUT_ACLK_MFC_333>; - clock-names = "fin_pll", - "dout_aclk_mfc_333"; - }; - - clock_g3d: clock-controller@11830000 { - compatible = "samsung,exynos5260-clock-g3d"; - reg = <0x11830000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>; - clock-names = "fin_pll"; - }; - - clock_fsys: clock-controller@122e0000 { - compatible = "samsung,exynos5260-clock-fsys"; - reg = <0x122e0000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&clock_top TOP_DOUT_ACLK_FSYS_200>; - clock-names = "fin_pll", - "phyclk_usbhost20_phy_phyclock", - "phyclk_usbhost20_phy_freeclk", - "phyclk_usbhost20_phy_clk48mohci", - "phyclk_usbdrd30_udrd30_pipe_pclk", - "phyclk_usbdrd30_udrd30_phyclock", - "dout_aclk_fsys_200"; - }; - - clock_aud: clock-controller@128c0000 { - compatible = "samsung,exynos5260-clock-aud"; - reg = <0x128c0000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_top TOP_FOUT_AUD_PLL>, - <&ioclk_i2s>, - <&ioclk_pcm>; - clock-names = "fin_pll", - "fout_aud_pll", - "ioclk_i2s_cdclk", - "ioclk_pcm_extclk"; - }; - - clock_isp: clock-controller@133c0000 { - compatible = "samsung,exynos5260-clock-isp"; - reg = <0x133c0000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_top TOP_DOUT_ACLK_ISP1_266>, - <&clock_top TOP_DOUT_ACLK_ISP1_400>, - <&clock_top TOP_MOUT_ACLK_ISP1_266>; - clock-names = "fin_pll", - "dout_aclk_isp1_266", - "dout_aclk_isp1_400", - "mout_aclk_isp1_266"; - }; - - clock_gscl: clock-controller@13f00000 { - compatible = "samsung,exynos5260-clock-gscl"; - reg = <0x13f00000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&clock_top TOP_DOUT_ACLK_GSCL_400>, - <&clock_top TOP_DOUT_ACLK_GSCL_333>; - clock-names = "fin_pll", - "dout_aclk_gscl_400", - "dout_aclk_gscl_333"; - }; - - clock_disp: clock-controller@14550000 { - compatible = "samsung,exynos5260-clock-disp"; - reg = <0x14550000 0x10000>; - #clock-cells = <1>; - clocks = <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&fin_pll>, - <&ioclk_spdif>, - <&clock_top TOP_DOUT_ACLK_PERI_AUD>, - <&clock_top TOP_DOUT_ACLK_DISP_222>, - <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>, - <&clock_top TOP_DOUT_ACLK_DISP_333>; - clock-names = "fin_pll", - "phyclk_dptx_phy_ch3_txd_clk", - "phyclk_dptx_phy_ch2_txd_clk", - "phyclk_dptx_phy_ch1_txd_clk", - "phyclk_dptx_phy_ch0_txd_clk", - "phyclk_hdmi_phy_tmds_clko", - "phyclk_hdmi_phy_ref_clko", - "phyclk_hdmi_phy_pixel_clko", - "phyclk_hdmi_link_o_tmds_clkhi", - "phyclk_mipi_dphy_4l_m_txbyte_clkhs", - "phyclk_dptx_phy_o_ref_clk_24m", - "phyclk_dptx_phy_clk_div2", - "phyclk_mipi_dphy_4l_m_rxclkesc0", - "phyclk_hdmi_phy_ref_cko", - "ioclk_spdif_extclk", - "dout_aclk_peri_aud", - "dout_aclk_disp_222", - "dout_sclk_disp_pixel", - "dout_aclk_disp_333"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x2000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = ; - }; - - chipid: chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - mct: timer@100b0000 { - compatible = "samsung,exynos5260-mct", - "samsung,exynos4210-mct"; - reg = <0x100b0000 0x1000>; - clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - }; - - cci: cci@10f00000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10f00000 0x1000>; - ranges = <0x0 0x10f00000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - }; - - pinctrl_0: pinctrl@11600000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x11600000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@12290000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x12290000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@128b0000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x128b0000 0x1000>; - interrupts = ; - }; - - pmu_system_controller: system-controller@10d50000 { - compatible = "samsung,exynos5260-pmu", "syscon"; - reg = <0x10d50000 0x10000>; - }; - - uart0: serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c00000 0x100>; - interrupts = ; - clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart1: serial@12c10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c10000 0x100>; - interrupts = ; - clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart2: serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12c20000 0x100>; - interrupts = ; - clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart3: serial@12860000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12860000 0x100>; - interrupts = ; - clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - mmc_0: mmc@12140000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12140000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; - clock-names = "biu", "ciu"; - assigned-clocks = - <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, - <&clock_top TOP_SCLK_MMC0>; - assigned-clock-parents = - <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; - assigned-clock-rates = <0>, <0>, <800000000>; - fifo-depth = <64>; - status = "disabled"; - }; - - mmc_1: mmc@12150000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12150000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; - clock-names = "biu", "ciu"; - assigned-clocks = - <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, - <&clock_top TOP_SCLK_MMC1>; - assigned-clock-parents = - <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; - assigned-clock-rates = <0>, <0>, <800000000>; - fifo-depth = <64>; - status = "disabled"; - }; - - mmc_2: mmc@12160000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12160000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; - clock-names = "biu", "ciu"; - assigned-clocks = - <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, - <&clock_top TOP_SCLK_MMC2>; - assigned-clock-parents = - <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; - assigned-clock-rates = <0>, <0>, <800000000>; - fifo-depth = <64>; - status = "disabled"; - }; - - hsi2c_0: i2c@12da0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12da0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_1: i2c@12db0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12db0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_2: i2c@12dc0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12dc0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_3: i2c@12dd0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12dd0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - }; -}; - -#include "exynos5260-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts deleted file mode 100644 index 882fc77c4bc4..000000000000 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ /dev/null @@ -1,664 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2016 Krzysztof Kozlowski - */ - -/dts-v1/; -#include "exynos5410.dtsi" -#include -#include -#include -#include -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU"; - compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; - - aliases { - ethernet = ðernet; - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7ea00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 20972 0>; - #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - sound: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "Odroid-XU"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - - simple-audio-card,cpu { - sound-dai = <&audi2s0 0>; - system-clock-frequency = <19200000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&max98090>; - clocks = <&audi2s0 CLK_I2S_CDCLK>; - }; - }; -}; - -&adc { - vdd-supply = <&ldo10_reg>; - status = "okay"; -}; - -&audi2s0 { - status = "okay"; -}; - -&clock { - clocks = <&fin_pll>; - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <192000000>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <96000000>, - <19200000>; -}; - -&cpu0_thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - }; -}; - -&hsi2c_4 { - clock-frequency = <400000>; - status = "okay"; - - usb3503: usb-hub@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; - connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - refclk-frequency = <24000000>; - }; - - max77802: pmic@9 { - compatible = "maxim,max77802"; - reg = <0x9>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>; - wakeup-source; - #clock-cells = <1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&buck10_reg>; - inl7-supply = <&buck9_reg>; - /* inl9 supply is BOOST, not configured here */ - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - /* vdd_mmc0 */ - regulator-name = "vddf_2v85"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "buck9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "buck10"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_alive"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "vddq_m1_m2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_gpio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - /* Having it off prevents reboot */ - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd18_hsic"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd18_bpll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vddq_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* Supplies also GPK and GPJ */ - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd10_hdmi"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "ldo9"; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd18_mipi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vddq_mmc01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Having it off prevents accessing MMC after - * reboot with error: - * MMC Device 1: Clock OFF has been failed. - */ - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd33_usb3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_abbg0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "vddq_abbg1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd10_usb3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "cam_sensor_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo19"; - }; - - ldo20_reg: LDO20 { - regulator-name = "vdd_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - /* vdd_mmc2 */ - regulator-name = "vddf_2v8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "dp_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "cam_af"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "eth_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "usb30_extclk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo27"; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo28"; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo29"; - }; - - ldo30_reg: LDO30 { - regulator-name = "vddq_e1_e2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* On revisions with ti,ina231 this is sensor VS */ - ldo32_reg: LDO32 { - regulator-name = "vs_power_meter"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo33"; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo34"; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo35"; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - max98090: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpj3>; - interrupts = <0 IRQ_TYPE_NONE>; - clocks = <&audi2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - vmmc-supply = <&ldo20_reg>; - vqmmc-supply = <&ldo11_reg>; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4 &sd2_wp>; - bus-width = <4>; - cap-sd-highspeed; - vmmc-supply = <&ldo21_reg>; - vqmmc-supply = <&ldo4_reg>; -}; - -&pinctrl_0 { - emmc_nrst_pin: emmc-nrst-pins { - samsung,pins = "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_wp: sd2-wp-pins { - samsung,pins = "gpm5-0"; - samsung,pin-function = ; - /* Pin is floating so be sure to disable write-protect */ - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_2: pmic-dvs-2-pins { - samsung,pins = "gpx0-0", "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1-pins { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <1>; - }; - - max77802_irq: max77802-irq-pins { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&usb3_0_oc { - /* External pull up */ - samsung,pin-pud = ; -}; - -&usb3_1_oc { - /* External pull up */ - samsung,pin-pud = ; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd3_0 { - vdd33-supply = <&ldo12_reg>; - vdd10-supply = <&ldo15_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo12_reg>; - vdd10-supply = <&ldo15_reg>; -}; - -&usbhost2 { - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@2 { - compatible = "usb424,9730"; - reg = <2>; - local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ - }; -}; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi deleted file mode 100644 index f7b923382892..000000000000 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ /dev/null @@ -1,652 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Exynos5410 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Hardkernel Co., Ltd. - * https://www.hardkernel.com - */ - -#include "exynos-pinctrl.h" - -&pinctrl_0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm5: gpm5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm7: gpm7-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy0: gpy0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy7: gpy7-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, - <24 0>, - <25 0>, - <25 1>, - <26 0>, - <26 1>, - <27 0>, - <27 1>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, - <28 1>, - <29 0>, - <29 1>, - <30 0>, - <30 1>, - <31 0>, - <31 1>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_hs_bus: i2c4-hs-bus-pins { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_hs_bus: i2c5-hs-bus-pins { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_hs_bus: i2c6-hs-bus-pins { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_hs_bus: i2c7-hs-bus-pins { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpj0: gpj0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj2: gpj2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj3: gpj3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - usb3_1_oc: usb3-1-oc-pins { - samsung,pins = "gpk2-4", "gpk2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_1_vbusctrl: usb3-1-vbusctrl-pins { - samsung,pins = "gpk2-6", "gpk2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_0_oc: usb3-0-oc-pins { - samsung,pins = "gpk3-0", "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_0_vbusctrl: usb3-0-vbusctrl-pins { - samsung,pins = "gpk3-2", "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpv0: gpv0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_3 { - gpz: gpz-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - audi2s0_bus: audi2s0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - -}; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts deleted file mode 100644 index bb29b76f6f6a..000000000000 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK5410 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5410.dtsi" -#include -/ { - model = "Samsung SMDK5410 board based on Exynos5410"; - compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - pmic_ap_clk: pmic-ap-clk { - /* Workaround for missing PMIC and its clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - firmware@2037000 { - compatible = "samsung,secure-firmware"; - reg = <0x02037000 0x1000>; - }; - - vdd10_usb3: voltage-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VDD10_USB3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vdd33_usb3: voltage-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VDD33_USB3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc_0 { - status = "okay"; - cap-mmc-highspeed; - broken-cd; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <4>; - disable-wp; -}; - -&pinctrl_0 { - srom_ctl: srom-ctl-pins { - samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", - "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; - samsung,pin-function = ; - samsung,pin-drv = ; - }; - - srom_ebi: srom-ebi-pins { - samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", - "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", - "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", - "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", - "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", - "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sromc { - pinctrl-names = "default"; - pinctrl-0 = <&srom_ctl>, <&srom_ebi>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&usbdrd3_0 { - vdd10-supply = <&vdd10_usb3>; - vdd33-supply = <&vdd33_usb3>; -}; - -&usbdrd3_1 { - vdd10-supply = <&vdd10_usb3>; - vdd33-supply = <&vdd33_usb3>; -}; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi deleted file mode 100644 index 546035e78f40..000000000000 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5410 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5410 SoC device nodes are listed in this file. - * Exynos5410 based board files can include this file and provide - * values for board specific bindings. - */ - -#include "exynos54xx.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos5410", "samsung,exynos5"; - interrupt-parent = <&gic>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5410-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&fin_pll>; - #clock-cells = <1>; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5410-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5410-audss-clock"; - reg = <0x03810000 0x0c>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; - clock-names = "pll_ref", "pll_in"; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10068000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x1006c000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12210000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12220000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@14000000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = ; - }; - - pinctrl_3: pinctrl@3860000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = ; - }; - - pdma0: dma-controller@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121a0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pdma1: dma-controller@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121b0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - audi2s0: i2s@3830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10>, - <&pdma0 9>, - <&pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&audi2s0_bus>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - }; -}; - -&adc { - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -&arm_a15_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&hsi2c_4 { - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; -}; - -&hsi2c_5 { - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; -}; - -&hsi2c_6 { - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; -}; - -&hsi2c_7 { - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; -}; - -&mct { - clocks = <&fin_pll>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; -}; - -&prng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 13>, <&pdma0 14>; - dma-names = "rx", "tx"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&sromc { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 - 1 0 0x05000000 0x20000 - 2 0 0x06000000 0x20000 - 3 0 0x07000000 0x20000>; -}; - -&trng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>; -}; - -&usbdrd_phy0 { - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>; -}; - -&usbdrd_dwc3_1 { - interrupts = ; -}; - -&usbdrd_phy1 { - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbhost1 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usbhost2 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usb2_phy { - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; -}; - -&watchdog { - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -#include "exynos5410-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts deleted file mode 100644 index 809ddda02e53..000000000000 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ /dev/null @@ -1,843 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5420 based Arndale Octa board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include -#include -#include -#include - -/ { - model = "Insignal Arndale Octa evaluation board based on Exynos5420"; - compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "SW-TACT1"; - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&adc { - vdd-supply = <&ldo4_reg>; - status = "okay"; -}; - -&cci { - status = "disabled"; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&cpu0_thermal { - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * Reduce the CPU speed by 2 steps, down to: 1600 MHz - * and 1100 MHz. - */ - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - /* - * Reduce the CPU speed down to 1200 MHz big (6 steps) - * and 800 MHz LITTLE (5 steps). - */ - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - /* - * Reduce the CPU speed as much as possible, down to 700 MHz - * big (11 steps) and 600 MHz LITTLE (7 steps). - */ - map2 { - trip = <&cpu0_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 5 7>, - <&cpu5 5 7>, - <&cpu6 5 7>, - <&cpu7 5 7>; - }; - }; -}; - -&cpu1_thermal { - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu1_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - map2 { - trip = <&cpu1_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 5 7>, - <&cpu5 5 7>, - <&cpu6 5 7>, - <&cpu7 5 7>; - }; - }; -}; - -&cpu2_thermal { - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu2_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - map2 { - trip = <&cpu2_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 6 7>, - <&cpu5 6 7>, - <&cpu6 6 7>, - <&cpu7 6 7>; - }; - }; -}; - -&cpu3_thermal { - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu3_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - map2 { - trip = <&cpu3_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 5 7>, - <&cpu5 5 7>, - <&cpu6 5 7>, - <&cpu7 5 7>; - }; - }; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; - ddc = <&i2c_2>; - status = "okay"; -}; - -&hsi2c_4 { - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - wakeup-source; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "PVDD_ALIVE_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "PVDD_APIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "PVDD_APIO_MMCON_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Must be always on, even though there is - * a consumer (mmc_0). Otherwise the board - * does not reboot with vendor U-Boot - * (Linaro for Arndale Octa, v2012.07). - */ - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "PVDD_ADC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "PVDD_PLL_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "PVDD_ANAIP_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "PVDD_ANAIP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "PVDD_ABB_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "PVDD_USB_3V3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "PVDD_PRE_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "PVDD_USB_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "PVDD_HSIC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "PVDD_APIO_MMCOFF_2V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - /* Unused */ - regulator-name = "PVDD_LDO14"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "PVDD_PERI_2V8"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "PVDD_PERI_3V3"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - /* Unused */ - regulator-name = "PVDD_LDO17"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "PVDD_EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Must stay in "off" mode during shutdown for - * proper eMMC reset. The "off" mode is in - * fact controlled by LDO18EN. The eMMC does - * not have reset pin connected so the reset - * will be triggered by falling edge of - * LDO18EN. - */ - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "PVDD_TFLASH_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "PVDD_BTWIFI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "PVDD_CAM1IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo22_reg: LDO22 { - /* Unused */ - regulator-name = "PVDD_LDO22"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "PVDD_MIFS_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo24_reg: LDO24 { - regulator-name = "PVDD_CAM1_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - /* Unused */ - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "PVDD_CAM0_AF_2V8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "PVDD_G3DS_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo28_reg: LDO28 { - regulator-name = "PVDD_TSP_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "PVDD_AUDIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - /* Unused */ - regulator-name = "PVDD_LDO30"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo31_reg: LDO31 { - regulator-name = "PVDD_PERI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo32_reg: LDO32 { - regulator-name = "PVDD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "PVDD_CAM0IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo34_reg: LDO34 { - /* Unused */ - regulator-name = "PVDD_LDO34"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "PVDD_CAM0_DVDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo36_reg: LDO36 { - /* Unused */ - regulator-name = "PVDD_LDO36"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo37_reg: LDO37 { - /* Unused */ - regulator-name = "PVDD_LDO37"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo38_reg: LDO38 { - regulator-name = "PVDD_CAM0_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "PVDD_MIF_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "PVDD_ARM_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "PVDD_INT_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "PVDD_G3D_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "PVDD_LPDDR3_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "PVDD_KFC_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VIN_HLDO_3V5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "PVDD_EMMCF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* - * Must stay in "off" mode during shutdown for - * proper eMMC reset. The "off" mode is in - * fact controlled by BUCK10EN. The eMMC does - * not have reset pin connected so the reset - * will be triggered by falling edge of - * BUCK10EN. - */ - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c_2 { - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - non-removable; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - vmmc-supply = <&ldo18_reg>; - vqmmc-supply = <&ldo3_reg>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; - -&pinctrl_0 { - s2mps11_irq: s2mps11-irq-pins { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd3_0 { - vdd10-supply = <&ldo11_reg>; - vdd33-supply = <&ldo9_reg>; -}; - -&usbdrd3_1 { - vdd10-supply = <&ldo11_reg>; - vdd33-supply = <&ldo9_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5420-chagall-wifi.dts b/arch/arm/boot/dts/exynos5420-chagall-wifi.dts deleted file mode 100644 index 1319344a2c74..000000000000 --- a/arch/arm/boot/dts/exynos5420-chagall-wifi.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5420 Chagall WiFi board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Henrik Grimler - */ - -/dts-v1/; -#include "exynos5420-galaxy-tab-common.dtsi" - -/ { - model = "Samsung Chagall WiFi based on Exynos5420"; - compatible = "samsung,chagall-wifi", "samsung,exynos5420", \ - "samsung,exynos5"; -}; - -&ldo15_reg { - /* Unused */ - regulator-name = "VDD_LDO15"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&ldo17_reg { - regulator-name = "VDD_IRLED_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&ldo28_reg { - /* Unused */ - regulator-name = "VDD_LDO28"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&ldo29_reg { - regulator-name = "VDD_TCON_1V8"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&ldo31_reg { - regulator-name = "VDD_GRIP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&ldo32_reg { - regulator-name = "VDD_TSP_1V8"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi deleted file mode 100644 index e9f4eb75b50f..000000000000 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5420 SoC cpu device tree source - * - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This file provides desired ordering for Exynos5420 and Exynos5800 - * boards: CPU[0123] being the A15. - * - * The Exynos5420, 5422 and 5800 actually share the same CPU configuration - * but particular boards choose different booting order. - * - * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 - * booting cluster (big or LITTLE) is chosen by IROM code by reading - * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting - * from the LITTLE: Cortex-A7. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - }; -}; - -&arm_a7_pmu { - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - status = "okay"; -}; - -&arm_a15_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi deleted file mode 100644 index f525b2f5e4e0..000000000000 --- a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi +++ /dev/null @@ -1,696 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Base DT for Samsung's family of tablets based on Exynos5420. - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Henrik Grimler - */ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include -#include -#include - -/ { - chassis-type = "tablet"; - - /* - * To successfully boot the mainline kernel with the stock - * bootloader (SBOOT), the tlb needs to be flushed after the - * page table pointer has been updated in __common_mmu_cache_on. - * The same hack is also needed to boot exynos4412-i9300 with - * stock bootloader, and probably other Samsung devices of - * similar age. See - * https://lore.kernel.org/all/1355276466-18295-1-git-send-email-arve@android.com - * for more details. - */ - - aliases { - mmc0 = &mmc_0; - mmc2 = &mmc_2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0xc0000000>; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - debounce-interval = <10>; - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = ; - wakeup-source; - }; - - key-home { - debounce-interval = <10>; - gpios = <&gpx0 5 GPIO_ACTIVE_LOW>; - label = "Home"; - linux,code = ; - wakeup-source; - }; - - key-volume-up { - debounce-interval = <10>; - gpios = <&gpx0 2 GPIO_ACTIVE_LOW>; - label = "Volume Up"; - linux,code = ; - }; - - key-volume-down { - debounce-interval = <10>; - gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; - label = "Volume Down"; - linux,code = ; - }; - }; -}; - -&cci { - /* CCI is disabled in hardware */ - status = "disabled"; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&gpu { - status = "okay"; - mali-supply = <&buck4_reg>; -}; - -&hsi2c_7 { - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", "s2mps11_cp", - "s2mps11_bt"; - }; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF_1V1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D_1V0"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - buck6_reg: BUCK6 { - regulator-name = "VDD_KFC_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VIN_HLDO_3V5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "VDD_CAM_ISP_1V0"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3550000>; - }; - - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_APIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_APIO_MMC01_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_ADC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - /* Unused */ - regulator-name = "VDD_LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MIPI_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_MIPI_PLL_ABB1_18V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - /* Unused */ - regulator-name = "VDD_LDO8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_UOTG_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDDQ_PRE_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_HSIC_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_HSIC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDD_APIO_MMC2_2V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD_MOTOR_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD_LDO15"; - /* - * LDO15 varies between devices and is - * specified in the device dts - */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD_AP_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDD_LDO17"; - /* - * LDO17 varies between devices and is - * specified in the device dts - */ - }; - - ldo18_reg: LDO18 { - /* Unused */ - regulator-name = "VDD_LDO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VDD_VTF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD_CAM1_CAM_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD_CAM_IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo22_reg: LDO22 { - regulator-name = "VDD_CAM0_S_CORE_1V1"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD_MIFS_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD_TSP_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - /* Unused */ - regulator-name = "VDD_LDO25"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD_CAM0_AF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo27_reg: LDO27 { - regulator-name = "VDD_G3DS_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo28_reg: LDO28 { - regulator-name = "VDD_LDO28"; - /* - * LDO28 varies between devices and is - * specified in the device dts - */ - }; - - ldo29_reg: LDO29 { - regulator-name = "VDD_LDO29"; - /* - * LDO29 varies between devices and is - * specified in the device dts - */ - }; - - ldo30_reg: LDO30 { - regulator-name = "VDD_TOUCH_1V8"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo31_reg: LDO31 { - regulator-name = "VDD_LDO31"; - /* - * LDO31 varies between devices and is - * specified in the device dts - */ - }; - - ldo32_reg: LDO32 { - regulator-name = "VDD_LDO32"; - /* - * LDO32 varies between devices and is - * specified in the device dts - */ - }; - - ldo33_reg: LDO33 { - regulator-name = "VDD_MHL_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo34_reg: LDO34 { - regulator-name = "VDD_MHL_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo35_reg: LDO35 { - regulator-name = "VDD_SIL_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo36_reg: LDO36 { - /* Unused */ - regulator-name = "VDD_LDO36"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo37_reg: LDO37 { - /* Unused */ - regulator-name = "VDD_LDO37"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo38_reg: LDO38 { - regulator-name = "VDD_KEY_LED_3V3"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mixer { - status = "okay"; -}; - -/* Internal storage */ -&mmc_0 { - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; - card-detect-delay = <200>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - pinctrl-names = "default"; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-sdr-timing = <0 4>; - vqmmc-supply = <&ldo3_reg>; -}; - -/* External sdcard */ -&mmc_2 { - status = "okay"; - bus-width = <4>; - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sd2_clk &sd2_cmd &mmc2_cd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-sdr-timing = <0 4>; - sd-uhs-sdr50; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; -}; - -&pinctrl_0 { - mmc2_cd: mmc2-cd-pins { - samsung,pins = "gpx2-4"; - samsung,pin-pud = ; - }; - - s2mps11_irq: s2mps11-irq-pins { - samsung,pins = "gpx3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5420-klimt-wifi.dts b/arch/arm/boot/dts/exynos5420-klimt-wifi.dts deleted file mode 100644 index 011787b1bbf0..000000000000 --- a/arch/arm/boot/dts/exynos5420-klimt-wifi.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5420 Klimt WiFi board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Henrik Grimler - */ - -/dts-v1/; -#include "exynos5420-galaxy-tab-common.dtsi" - -/ { - model = "Samsung Klimt WiFi based on Exynos5420"; - compatible = "samsung,klimt-wifi", "samsung,exynos5420", \ - "samsung,exynos5"; -}; - -&ldo15_reg { - /* Unused */ - regulator-name = "VDD_LDO15"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&ldo17_reg { - regulator-name = "VDD_VCI_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&ldo28_reg { - regulator-name = "VDD3_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&ldo29_reg { - regulator-name = "VDDR_1V6"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1600000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&ldo31_reg { - /* Unused */ - regulator-name = "VDD_LDO31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&ldo32_reg { - regulator-name = "VDD_TSP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; -}; - -&mmc_2 { - sd-uhs-sdr104; -}; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts deleted file mode 100644 index 7a48f2b32819..000000000000 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ /dev/null @@ -1,1126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Peach Pit Rev 6+ board device tree source - * - * Copyright (c) 2014 Google, Inc - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" - -/ { - model = "Google Peach Pit Rev 6+"; - - compatible = "google,pit-rev16", - "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", - "google,pit-rev11", "google,pit-rev10", - "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", - "google,pit", "google,peach","samsung,exynos5420", - "samsung,exynos5"; - chassis-type = "laptop"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - mmc0 = &mmc_0; /* eMMC */ - mmc1 = &mmc_2; /* uSD */ - mmc2 = &mmc_1; /* WiFi */ - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power-key { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Peach-Pit-I2S-MAX98090"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98090>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98090>, <&hdmi>; - }; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - mmc1_pwrseq: mmc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77802 MAX77802_CLK_32K_CP>; - clock-names = "ext_clock"; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_MAU_EPLL>; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x06>; - samsung,lane-count = <2>; - hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98090: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; - - ps8625: lvds-bridge@48 { - compatible = "parade,ps8625"; - reg = <0x48>; - sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; - lane-count = <2>; - use-external-pwm; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - - /* Atmel mXT336S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -/* WiFi SDIO module */ -&mmc_1 { - status = "okay"; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, - <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc1_pwrseq>; - vqmmc-supply = <&buck10_reg>; -}; - -/* uSD card */ -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - wifi_en: wifi-en-pins { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max98090_irq: max98090-irq-pins { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset-pins { - samsung,pins = "gpx0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq-pins { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq-pins { - samsung,pins = "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq-pins { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq-pins { - samsung,pins = "gpx1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq-pins { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp-hpd-gpio-pins { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77802_irq: max77802-irq-pins { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq-pins { - samsung,pins = "gpx3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1-pins { - samsung,pins = "gpy7-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -/* pinctrl_1 */ -/* Adjust WiFi drive strengths lower for EMI */ -&sd1_bus1 { - samsung,pin-drv = ; -}; - -&sd1_bus4 { - samsung,pin-drv = ; -}; - -&sd1_bus8 { - samsung,pin-drv = ; -}; - -&sd1_clk { - samsung,pin-drv = ; -}; - -&sd1_cmd { - samsung,pin-drv = ; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2-pins { - samsung,pins = "gpj4-2", "gpj4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -/* pinctrl_3*/ -/* Drive SPI lines at x2 for better integrity */ -&spi2_bus { - samsung,pin-drv = ; -}; - -&pinctrl_3 { - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs-pins { - samsung,pins = "gpb1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb300_vbus_en: usb300-vbus-en-pins { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en-pins { - samsung,pins = "gph0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_selb: pmic-selb-pins { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - google,has-vbc-nvram; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&serial_3 { - status = "okay"; -}; - -&timer { - arm,cpu-registers-not-fw-configured; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd3_0 { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; - -&usbdrd3_1 { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi deleted file mode 100644 index 93b9873fa84f..000000000000 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ /dev/null @@ -1,734 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device - * tree nodes in this file. - */ - -#include "exynos-pinctrl.h" - -&pinctrl_0 { - gpy7: gpy7-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dp_hpd: dp-hpd-pins { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec-pins { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rclk: sd0-rclk-pins { - samsung,pins = "gpc0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpc1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpc1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_int: sd1-int-pins { - samsung,pins = "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpc1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8-pins { - samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_wp: sd2-wp-pins { - samsung,pins = "gpc4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a-pins { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b-pins { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c2_bus: cam-i2c2-bus-pins { - samsung,pins = "gpf0-4", "gpf0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus-pins { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus-pins { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus-pins { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus-pins { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_bayrgb_bus: cam-bayrgb-bus-pins { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_hs_bus: i2c4-hs-bus-pins { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_hs_bus: i2c5-hs-bus-pins { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus-pins { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus-pins { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus-pins { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_hs_bus: i2c6-hs-bus-pins { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_hs_bus: i2c7-hs-bus-pins { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c8_hs_bus: i2c8-hs-bus-pins { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c9_hs_bus: i2c9-hs-bus-pins { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c10_hs_bus: i2c10-hs-bus-pins { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_4 { - gpz: gpz-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus-pins { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts deleted file mode 100644 index e299344e427a..000000000000 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ /dev/null @@ -1,435 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK5420 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include -#include - -/ { - model = "Samsung SMDK5420 board based on Exynos5420"; - compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - aliases { - mmc0 = &mmc_0; - mmc1 = &mmc_2; - }; - - chosen { - bootargs = "init=/linuxrc"; - stdout-path = "serial2:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - vdd: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - dbvdd: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spkvdd: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - usb300_vbus_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpg0 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "VBUS1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpg1 4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; - }; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - status = "okay"; - ddc = <&i2c_2>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - vdd-supply = <&ldo6_reg>; - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; -}; - -&hsi2c_4 { - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - wakeup-source; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - /* used by HDMI DDC */ - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - mmc-ddr-1_8v; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 - &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - usb300_vbus_en: usb300-vbus-en-pins { - samsung,pins = "gpg0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en-pins { - samsung,pins = "gpg1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd3_0 { - vdd10-supply = <&ldo11_reg>; - vdd33-supply = <&ldo9_reg>; -}; - -&usbdrd3_1 { - vdd10-supply = <&ldo11_reg>; - vdd33-supply = <&ldo9_reg>; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/exynos5420-trip-points.dtsi deleted file mode 100644 index a67a380717ec..000000000000 --- a/arch/arm/boot/dts/exynos5420-trip-points.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for default Exynos5420 thermal zone definition - * - * Copyright (c) 2014 Lukasz Majewski - */ - -polling-delay-passive = <0>; -polling-delay = <0>; -trips { - cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-alert-1 { - temperature = <103000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi deleted file mode 100644 index 25ed90374679..000000000000 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ /dev/null @@ -1,1397 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5420 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5420 SoC device nodes are listed in this file. - * Exynos5420 based board files can include this file and provide - * values for board specific bindings. - */ - -#include "exynos54xx.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos5420", "samsung,exynos5"; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - pinctrl4 = &pinctrl_4; - i2c8 = &hsi2c_8; - i2c9 = &hsi2c_9; - i2c10 = &hsi2c_10; - gsc0 = &gsc_0; - gsc1 = &gsc_1; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - }; - - bus_disp1: bus-disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1_fimd: bus-disp1-fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys2: bus-fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys_apb: bus-fsys-apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d: bus-g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d_acp: bus-g2d-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - bus_gen: bus-gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gscl_scaler: bus-gscl-scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg: bus-jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg_apb: bus-jpeg-apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mscl: bus-mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_noc: bus-noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_wcore: bus-wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - status = "disabled"; - }; - - /* - * The 'cpus' node is not present here but instead it is provided - * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. - */ - - cluster_a15_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000 1250000 1500000>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500 1212500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000 1175000 1500000>; - clock-latency-ns = <140000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500 1137500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500 1112500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500 1062500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500 1037500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500 1012500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500 987500 1500000>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500 962500 1500000>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500 937500 1500000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500 912500 1500000>; - clock-latency-ns = <140000>; - }; - }; - - cluster_a7_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1162500>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - }; - - soc: soc { - cci: cci@10d20000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10d20000 0x1000>; - ranges = <0x0 0x10d20000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock", "syscon"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0c>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, - <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - power-domains = <&mau_pd>; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v7"; - reg = <0x11000000 0x10000>; - interrupts = ; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - power-domains = <&mfc_pd>; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x2000>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x2000>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5420-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - dmc: memory-controller@10c20000 { - compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; - clocks = <&clock CLK_FOUT_SPLL>, - <&clock CLK_MOUT_SCLK_SPLL>, - <&clock CLK_FF_DOUT_SPLL2>, - <&clock CLK_FOUT_BPLL>, - <&clock CLK_MOUT_BPLL>, - <&clock CLK_SCLK_BPLL>, - <&clock CLK_MOUT_MX_MSPLL_CCORE>, - <&clock CLK_MOUT_MCLK_CDREX>; - clock-names = "fout_spll", - "mout_sclk_spll", - "ff_dout_spll2", - "fout_bpll", - "mout_bpll", - "sclk_bpll", - "mout_mx_mspll_ccore", - "mout_mclk_cdrex"; - samsung,syscon-clk = <&clock>; - status = "disabled"; - }; - - nocp_mem0_0: nocp@10ca1000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10ca1000 0x200>; - status = "disabled"; - }; - - nocp_mem0_1: nocp@10ca1400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10ca1400 0x200>; - status = "disabled"; - }; - - nocp_mem1_0: nocp@10ca1800 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10ca1800 0x200>; - status = "disabled"; - }; - - nocp_mem1_1: nocp@10ca1c00 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10ca1c00 0x200>; - status = "disabled"; - }; - - nocp_g3d_0: nocp@11a51000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11a51000 0x200>; - status = "disabled"; - }; - - nocp_g3d_1: nocp@11a51400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11a51400 0x200>; - status = "disabled"; - }; - - ppmu_dmc0_0: ppmu@10d00000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d00000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 { - event-name = "ppmu-event3-dmc0-0"; - }; - }; - }; - - ppmu_dmc0_1: ppmu@10d10000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d10000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 { - event-name = "ppmu-event3-dmc0-1"; - }; - }; - }; - - ppmu_dmc1_0: ppmu@10d60000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d60000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 { - event-name = "ppmu-event3-dmc1-0"; - }; - }; - }; - - ppmu_dmc1_1: ppmu@10d70000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d70000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 { - event-name = "ppmu-event3-dmc1-1"; - }; - }; - }; - - gsc_pd: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - label = "GSC"; - }; - - isp_pd: power-domain@10044020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044020 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - mfc_pd: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - g3d_pd: power-domain@10044080 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044080 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - disp_pd: power-domain@100440c0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440c0 0x20>; - #power-domain-cells = <0>; - label = "DISP"; - }; - - mau_pd: power-domain@100440e0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440e0 0x20>; - #power-domain-cells = <0>; - label = "MAU"; - }; - - msc_pd: power-domain@10044120 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044120 0x20>; - #power-domain-cells = <0>; - label = "MSC"; - }; - - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@13410000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13410000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@14000000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = ; - }; - - pinctrl_3: pinctrl@14010000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14010000 0x1000>; - interrupts = ; - }; - - pinctrl_4: pinctrl@3860000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = ; - power-domains = <&mau_pd>; - }; - - adma: dma-controller@3880000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x03880000 0x1000>; - interrupts = ; - clocks = <&clock_audss EXYNOS_ADMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - power-domains = <&mau_pd>; - }; - - pdma0: dma-controller@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121a0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pdma1: dma-controller@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121b0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - mdma0: dma-controller@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - mdma1: dma-controller@11c10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11c10000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in - * the kernel for boards that run in secure - * mode, we are getting imprecise external - * aborts causing the kernel to oops. - */ - status = "disabled"; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&adma 0>, - <&adma 2>, - <&adma 1>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - power-domains = <&mau_pd>; - status = "disabled"; - }; - - i2s1: i2s@12d60000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12d60000 0x100>; - dmas = <&pdma1 12>, - <&pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s2: i2s@12d70000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12d70000 0x100>; - dmas = <&pdma0 12>, - <&pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d20000 0x100>; - interrupts = ; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d30000 0x100>; - interrupts = ; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d40000 0x100>; - interrupts = ; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - dsi: dsi@14500000 { - compatible = "samsung,exynos5410-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = ; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_8: i2c@12e00000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12e00000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_USI4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: i2c@12e10000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12e10000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_USI5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: i2c@12e20000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12e20000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_USI6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos5420-hdmi"; - reg = <0x14530000 0x70000>; - interrupts = ; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - phy = <&hdmiphy>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - power-domains = <&disp_pd>; - #sound-dai-cells = <0>; - }; - - hdmiphy: hdmi-phy@145d0000 { - reg = <0x145d0000 0x20>; - }; - - hdmicec: cec@101b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x101b0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5420-mixer"; - reg = <0x14450000 0x10000>; - interrupts = ; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - rotator: rotator@11c00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11c00000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = ; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl0>; - }; - - gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = ; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl1>; - }; - - gpu: gpu@11800000 { - compatible = "samsung,exynos5420-mali", "arm,mali-t628"; - reg = <0x11800000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - - clocks = <&clock CLK_G3D>; - clock-names = "core"; - power-domains = <&g3d_pd>; - operating-points-v2 = <&gpu_opp_table>; - - status = "disabled"; - #cooling-cells = <2>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-177000000 { - opp-hz = /bits/ 64 <177000000>; - opp-microvolt = <812500>; - }; - opp-266000000 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <862500>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <912500>; - }; - opp-420000000 { - opp-hz = /bits/ 64 <420000000>; - opp-microvolt = <962500>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <1000000>; - }; - opp-543000000 { - opp-hz = /bits/ 64 <543000000>; - opp-microvolt = <1037500>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1150000>; - }; - }; - }; - - scaler_0: scaler@12800000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12800000 0x1294>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL0>; - clock-names = "mscl"; - power-domains = <&msc_pd>; - iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; - }; - - scaler_1: scaler@12810000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12810000 0x1294>; - interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL1>; - clock-names = "mscl"; - power-domains = <&msc_pd>; - iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; - }; - - scaler_2: scaler@12820000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12820000 0x1294>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL2>; - clock-names = "mscl"; - power-domains = <&msc_pd>; - iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; - }; - - jpeg_0: jpeg@11f50000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11f50000 0x1000>; - interrupts = ; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG>; - iommus = <&sysmmu_jpeg0>; - }; - - jpeg_1: jpeg@11f60000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11f60000 0x1000>; - interrupts = ; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG2>; - iommus = <&sysmmu_jpeg1>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - - dp_phy: dp-phy { - compatible = "samsung,exynos5420-dp-video-phy"; - #phy-cells = <0>; - }; - - mipi_phy: mipi-phy { - compatible = "samsung,exynos5420-mipi-video-phy"; - #phy-cells = <1>; - }; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = ; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = ; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_gpu: tmu@100a0000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = ; - clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - sysmmu_g2dr: sysmmu@10a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10a60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_g2dw: sysmmu@10a70000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10a70000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl0: sysmmu@13e80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13e80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl1: sysmmu@13e90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13e90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0r: sysmmu@12880000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12880000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1r: sysmmu@12890000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12890000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2r: sysmmu@128a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128a0000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0w: sysmmu@128c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128c0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <27 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1w: sysmmu@128d0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128d0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2w: sysmmu@128e0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128e0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <19 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@11d40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11d40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg0: sysmmu@11f10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11f10000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg1: sysmmu@11f20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11f20000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_0: sysmmu@14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_1: sysmmu@14680000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14680000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" - }; - }; -}; - -&adc { - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -&dp { - clocks = <&clock CLK_DP1>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; - power-domains = <&disp_pd>; -}; - -&fimd { - compatible = "samsung,exynos5420-fimd"; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; - iommu-names = "m0", "m1"; -}; - -&g2d { - iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - status = "okay"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&hsi2c_4 { - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; -}; - -&hsi2c_5 { - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; -}; - -&hsi2c_6 { - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; -}; - -&hsi2c_7 { - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; -}; - -&mct { - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; -}; - -&prng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 13>, <&pdma0 14>; - dma-names = "rx", "tx"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&trng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; -}; - -&usbdrd_phy0 { - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; -}; - -&usbdrd_dwc3_1 { - interrupts = ; -}; - -&usbdrd_phy1 { - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbhost1 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usbhost2 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usb2_phy { - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; -}; - -&watchdog { - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -#include "exynos5420-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi deleted file mode 100644 index 412a0bb4b988..000000000000 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5422 SoC cpu device tree source - * - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. - * - * The Exynos5420, 5422 and 5800 actually share the same CPU configuration - * but particular boards choose different booting order. - * - * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 - * booting cluster (big or LITTLE) is chosen by IROM code by reading - * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting - * from the LITTLE: Cortex-A7. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - dynamic-power-coefficient = <90>; - }; - - cpu1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - dynamic-power-coefficient = <90>; - }; - - cpu2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - dynamic-power-coefficient = <90>; - }; - - cpu3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - dynamic-power-coefficient = <90>; - }; - - cpu4: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <310>; - }; - - cpu5: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <310>; - }; - - cpu6: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <310>; - }; - - cpu7: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <310>; - }; - }; -}; - -&arm_a7_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - -&arm_a15_pmu { - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi deleted file mode 100644 index 2f5b8602e020..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ /dev/null @@ -1,1072 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source - * - * Copyright (c) 2017 Marek Szyprowski - * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5422-cpus.dtsi" - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7ea00000>; - }; - - aliases { - mmc2 = &mmc_2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - bus_wcore_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - /* derived from 532MHz MPLL */ - opp00 { - opp-hz = /bits/ 64 <88700000>; - opp-microvolt = <925000 925000 1400000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - opp-microvolt = <950000 950000 1400000>; - }; - opp02 { - opp-hz = /bits/ 64 <177400000>; - opp-microvolt = <950000 950000 1400000>; - }; - opp03 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <950000 950000 1400000>; - }; - opp04 { - opp-hz = /bits/ 64 <532000000>; - opp-microvolt = <1000000 1000000 1400000>; - }; - }; - - bus_noc_opp_table: opp-table-3 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <66600000>; - }; - opp01 { - opp-hz = /bits/ 64 <74000000>; - }; - opp02 { - opp-hz = /bits/ 64 <83250000>; - }; - opp03 { - opp-hz = /bits/ 64 <111000000>; - }; - }; - - bus_fsys_apb_opp_table: opp-table-4 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <111000000>; - }; - opp01 { - opp-hz = /bits/ 64 <222000000>; - }; - }; - - bus_fsys2_opp_table: opp-table-5 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <120000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_mfc_opp_table: opp-table-6 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <83250000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <166500000>; - }; - opp03 { - opp-hz = /bits/ 64 <222000000>; - }; - opp04 { - opp-hz = /bits/ 64 <333000000>; - }; - }; - - bus_gen_opp_table: opp-table-7 { - compatible = "operating-points-v2"; - - /* derived from 532MHz MPLL */ - opp00 { - opp-hz = /bits/ 64 <88700000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - }; - opp02 { - opp-hz = /bits/ 64 <178000000>; - }; - opp03 { - opp-hz = /bits/ 64 <266000000>; - }; - }; - - bus_peri_opp_table: opp-table-8 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <66600000>; - }; - }; - - bus_g2d_opp_table: opp-table-9 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <83250000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <166500000>; - }; - opp03 { - opp-hz = /bits/ 64 <222000000>; - }; - opp04 { - opp-hz = /bits/ 64 <333000000>; - }; - }; - - bus_g2d_acp_opp_table: opp-table-10 { - compatible = "operating-points-v2"; - - /* derived from 532MHz MPLL */ - opp00 { - opp-hz = /bits/ 64 <66500000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - }; - opp02 { - opp-hz = /bits/ 64 <178000000>; - }; - opp03 { - opp-hz = /bits/ 64 <266000000>; - }; - }; - - bus_jpeg_opp_table: opp-table-11 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <150000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - opp03 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_jpeg_apb_opp_table: opp-table-12 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <83250000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <133000000>; - }; - opp03 { - opp-hz = /bits/ 64 <166500000>; - }; - }; - - bus_disp1_fimd_opp_table: opp-table-13 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <120000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_disp1_opp_table: opp-table-14 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <120000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - opp02 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_gscl_opp_table: opp-table-15 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <150000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - opp02 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_mscl_opp_table: opp-table-16 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <84000000>; - }; - opp01 { - opp-hz = /bits/ 64 <167000000>; - }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - }; - opp03 { - opp-hz = /bits/ 64 <333000000>; - }; - opp04 { - opp-hz = /bits/ 64 <666000000>; - }; - }; - - dmc_opp_table: opp-table-17 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <165000000>; - opp-microvolt = <875000>; - }; - opp01 { - opp-hz = /bits/ 64 <206000000>; - opp-microvolt = <875000>; - }; - opp02 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <875000>; - }; - opp03 { - opp-hz = /bits/ 64 <413000000>; - opp-microvolt = <887500>; - }; - opp04 { - opp-hz = /bits/ 64 <543000000>; - opp-microvolt = <937500>; - }; - opp05 { - opp-hz = /bits/ 64 <633000000>; - opp-microvolt = <1012500>; - }; - opp06 { - opp-hz = /bits/ 64 <728000000>; - opp-microvolt = <1037500>; - }; - opp07 { - opp-hz = /bits/ 64 <825000000>; - opp-microvolt = <1050000>; - }; - }; - - samsung_K3QF2F20DB: lpddr3 { - compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; - density = <16384>; - io-width = <32>; - - tRFC-min-tck = <17>; - tRRD-min-tck = <2>; - tRPab-min-tck = <2>; - tRPpb-min-tck = <2>; - tRCD-min-tck = <3>; - tRC-min-tck = <6>; - tRAS-min-tck = <5>; - tWTR-min-tck = <2>; - tWR-min-tck = <7>; - tRTP-min-tck = <2>; - tW2W-C2C-min-tck = <0>; - tR2R-C2C-min-tck = <0>; - tWL-min-tck = <8>; - tDQSCK-min-tck = <5>; - tRL-min-tck = <14>; - tFAW-min-tck = <5>; - tXSR-min-tck = <12>; - tXP-min-tck = <2>; - tCKE-min-tck = <2>; - tCKESR-min-tck = <2>; - tMRD-min-tck = <5>; - - timings_samsung_K3QF2F20DB_800mhz: timings { - compatible = "jedec,lpddr3-timings"; - max-freq = <800000000>; - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; - }; - }; -}; - -&adc { - vdd-supply = <&ldo4_reg>; - status = "okay"; -}; - -&bus_wcore { - operating-points-v2 = <&bus_wcore_opp_table>; - devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, - <&nocp_mem1_0>, <&nocp_mem1_1>; - vdd-supply = <&buck3_reg>; - exynos,saturation-ratio = <100>; - status = "okay"; -}; - -&bus_noc { - operating-points-v2 = <&bus_noc_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys_apb { - operating-points-v2 = <&bus_fsys_apb_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys2 { - operating-points-v2 = <&bus_fsys2_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mfc { - operating-points-v2 = <&bus_mfc_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gen { - operating-points-v2 = <&bus_gen_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_peri { - operating-points-v2 = <&bus_peri_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d { - operating-points-v2 = <&bus_g2d_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d_acp { - operating-points-v2 = <&bus_g2d_acp_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg { - operating-points-v2 = <&bus_jpeg_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg_apb { - operating-points-v2 = <&bus_jpeg_apb_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1_fimd { - operating-points-v2 = <&bus_disp1_fimd_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1 { - operating-points-v2 = <&bus_disp1_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gscl_scaler { - operating-points-v2 = <&bus_gscl_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mscl { - operating-points-v2 = <&bus_mscl_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&buck6_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - -&dmc { - devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, - <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; - device-handle = <&samsung_K3QF2F20DB>; - operating-points-v2 = <&dmc_opp_table>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&hsi2c_4 { - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - samsung,s2mps11-acokb-ground; - - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - wakeup-source; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "vdd_adc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - /* Unused */ - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - /* Unused */ - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - /* Unused */ - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_ldo17"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_emmc_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - /* Unused */ - regulator-name = "vdd_ldo20"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo21_reg: LDO21 { - /* Unused */ - regulator-name = "vdd_ldo21"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo22_reg: LDO22 { - /* Unused */ - regulator-name = "vdd_ldo22"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo24_reg: LDO24 { - /* Unused */ - regulator-name = "vdd_ldo24"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo25_reg: LDO25 { - /* Unused */ - regulator-name = "vdd_ldo25"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo26_reg: LDO26 { - /* Used on XU3, XU3-Lite and XU4 */ - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo27_reg: LDO27 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo28_reg: LDO28 { - /* Used on XU3 */ - regulator-name = "vdd_ldo28"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo29_reg: LDO29 { - /* Unused */ - regulator-name = "vdd_ldo29"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo30_reg: LDO30 { - /* Unused */ - regulator-name = "vdd_ldo30"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo31_reg: LDO31 { - /* Unused */ - regulator-name = "vdd_ldo31"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo32_reg: LDO32 { - /* Unused */ - regulator-name = "vdd_ldo32"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo33_reg: LDO33 { - /* Unused */ - regulator-name = "vdd_ldo33"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo34_reg: LDO34 { - /* Unused */ - regulator-name = "vdd_ldo34"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo35_reg: LDO35 { - /* Unused */ - regulator-name = "vdd_ldo35"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo36_reg: LDO36 { - /* Unused */ - regulator-name = "vdd_ldo36"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo37_reg: LDO37 { - /* Unused */ - regulator-name = "vdd_ldo37"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo38_reg: LDO38 { - /* Unused */ - regulator-name = "vdd_ldo38"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-coupled-with = <&buck3_reg>; - regulator-coupled-max-spread = <300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-coupled-with = <&buck2_reg>; - regulator-coupled-max-spread = <300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.35v_ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_2.0v_ldo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <200000000>; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; - -&nocp_mem0_0 { - status = "okay"; -}; - -&nocp_mem0_1 { - status = "okay"; -}; - -&nocp_mem1_0 { - status = "okay"; -}; - -&nocp_mem1_1 { - status = "okay"; -}; - -&pinctrl_0 { - s2mps11_irq: s2mps11-irq-pins { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&ppmu_dmc0_0 { - status = "okay"; -}; - -&ppmu_dmc0_1 { - status = "okay"; -}; - -&ppmu_dmc1_0 { - status = "okay"; -}; - -&ppmu_dmc1_1 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo7_reg>; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -/* usbdrd_dwc3_1 mode customized in each board */ - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts deleted file mode 100644 index 5e4280393706..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid HC1 board device tree source - * - * Copyright (c) 2017 Marek Szyprowski - * Copyright (c) 2017 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include "exynos5422-odroid-core.dtsi" - -/ { - model = "Hardkernel Odroid HC1"; - compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ - "samsung,exynos5"; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * When reaching cpu0_alert0, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1600 MHz and 1100 MHz. - */ - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - /* - * When reaching cpu0_alert1, reduce CPU - * further, down to 600 MHz (12 steps for big, - * 7 steps for LITTLE). - */ - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - trips { - gpu_alert0: gpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - gpu_alert1: gpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - gpu_crit0: gpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = <&gpu 0 2>; - }; - map1 { - trip = <&gpu_alert1>; - cooling-device = <&gpu 3 6>; - }; - }; - }; - }; - -}; - -&pwm { - /* - * PWM 2 -- Blue LED - */ - pinctrl-0 = <&pwm2_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <2>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi deleted file mode 100644 index 86b96f9706db..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3 audio subsystem device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include - -/ { - sound: sound { - compatible = "samsung,odroid-xu3-audio"; - model = "Odroid-XU3"; - - samsung,audio-widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN12", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR", - "I2S Playback", "Mixer DAI TX", - "HiFi Playback", "Mixer DAI TX", - "Mixer DAI RX", "HiFi Capture"; - - cpu { - sound-dai = <&i2s0 0>, <&i2s0 1>; - }; - codec { - sound-dai = <&hdmi>, <&max98090>; - }; - }; -}; - -&hsi2c_5 { - status = "okay"; - max98090: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&i2s0 CLK_I2S_RCLK_SRC>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_SCLK_I2S>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi deleted file mode 100644 index b4a851aa8881..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2015 Lukasz Majewski - * Anand Moon - */ - -#include -#include "exynos5422-odroid-core.dtsi" - -/ { - aliases { - mmc0 = &mmc_0; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - power-key { - /* - * The power button (SW2) is connected to the PWRON - * pin (active high) of the S2MPS11 PMIC, which acts - * as a 16ms debouce filter and signal inverter with - * output on ONOB pin (active low). ONOB PMIC pin is - * then connected to XEINT3 SoC pin. - */ - gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <0>; - wakeup-source; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 20972 0>; - #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu0_alert2 - */ - cpu0_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu0_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu0_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * (usually) be: 1800 MHz and 1200 MHz. - */ - map3 { - trip = <&cpu0_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - /* - * When reaching cpu0_alert4, reduce CPU - * further, down to 600 MHz (14 steps for big, - * 8 steps for LITTLE). - */ - cpu0_cooling_map4: map4 { - trip = <&cpu0_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu1_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu1_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu1_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu1_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - cpu1_cooling_map4: map4 { - trip = <&cpu1_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu2_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu2_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu2_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu2_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - cpu2_cooling_map4: map4 { - trip = <&cpu2_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu3_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu3_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu3_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu3_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - cpu3_cooling_map4: map4 { - trip = <&cpu3_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - gpu_alert0: gpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - gpu_alert1: gpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - gpu_alert2: gpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - gpu_crit0: gpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - gpu_alert3: gpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - gpu_alert4: gpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&gpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&gpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&gpu_alert3>; - cooling-device = <&gpu 0 2>; - }; - map4 { - trip = <&gpu_alert4>; - cooling-device = <&gpu 3 6>; - }; - }; - }; - }; -}; - -&buck10_reg { - /* Supplies vmmc-supply of mmc_0 */ - regulator-always-on; - regulator-boot-on; -}; - -&hdmi { - status = "okay"; - ddc = <&i2c_2>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; -}; - -&hdmicec { - status = "okay"; - needs-hpd; -}; - -&i2c_2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - /* used by HDMI DDC */ - status = "okay"; -}; - -&ldo26_reg { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - max-frequency = <200000000>; - vmmc-supply = <&ldo18_reg>; - vqmmc-supply = <&ldo3_reg>; -}; - -&pinctrl_0 { - power_key: power-key-pins { - samsung,pins = "gpx0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - emmc_nrst_pin: emmc-nrst-pins { - samsung,pins = "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts deleted file mode 100644 index e3154a1cae23..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3-Lite board device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" -#include "exynos5422-odroidxu3-audio.dtsi" -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU3 Lite"; - compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; - - aliases { - ethernet = ðernet; - }; -}; - -&arm_a7_pmu { - status = "disabled"; -}; - -&arm_a15_pmu { - status = "disabled"; -}; - -&chipid { - samsung,asv-bin = <2>; -}; - -/* - * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies - * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores. - * Therefore we need to update OPPs tables and thermal maps accordingly. - */ -&cluster_a15_opp_table { - /delete-node/opp-2000000000; - /delete-node/opp-1900000000; -}; - -&cluster_a7_opp_table { - /delete-node/opp-1400000000; -}; - -&cpu0_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&cpu1_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&cpu2_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&cpu3_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; - -&usbhost2 { - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts deleted file mode 100644 index a378d4937ff7..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3 board device tree source - * - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" -#include "exynos5422-odroidxu3-audio.dtsi" -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU3"; - compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; - - aliases { - ethernet = ðernet; - }; -}; - -&i2c_0 { - status = "okay"; - - /* A15 cluster: VDD_ARM */ - power-sensor@40 { - compatible = "ti,ina231"; - reg = <0x40>; - shunt-resistor = <10000>; - }; - - /* memory: VDD_MEM */ - power-sensor@41 { - compatible = "ti,ina231"; - reg = <0x41>; - shunt-resistor = <10000>; - }; - - /* GPU: VDD_G3D */ - power-sensor@44 { - compatible = "ti,ina231"; - reg = <0x44>; - shunt-resistor = <10000>; - }; - - /* A7 cluster: VDD_KFC */ - power-sensor@45 { - compatible = "ti,ina231"; - reg = <0x45>; - shunt-resistor = <10000>; - }; -}; - -&ldo28_reg { - regulator-name = "dp_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; - -&usbhost2 { - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts deleted file mode 100644 index f5fb617f46bd..000000000000 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU4 board device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include -#include "exynos5422-odroidxu3-common.dtsi" - -/ { - model = "Hardkernel Odroid XU4"; - compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ - "samsung,exynos5"; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound: sound { - compatible = "samsung,odroid-xu3-audio"; - model = "Odroid-XU4"; - - samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; - - cpu { - sound-dai = <&i2s0 0>, <&i2s0 1>; - }; - - codec { - sound-dai = <&hdmi>; - }; - }; -}; - -&i2s0 { - status = "okay"; - - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&i2s0 CLK_I2S_RCLK_SRC>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_SCLK_I2S>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 2 -- Blue LED - */ - pinctrl-0 = <&pwm0_out &pwm2_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>, <2>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts deleted file mode 100644 index c35261a338ff..000000000000 --- a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts +++ /dev/null @@ -1,679 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Galaxy S5 (SM-G900H) device-tree source - * - * Copyright (c) 2023 Markuss Broks - */ - -/dts-v1/; -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5422-cpus.dtsi" - -/ { - model = "Samsung Galaxy S5 (SM-G900H)"; - compatible = "samsung,k3g", "samsung,exynos5800", \ - "samsung,exynos5"; - - chassis-type = "handset"; - - aliases { - mmc0 = &mmc_0; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; /* 2 GiB */ - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - tsp_vdd: regulator-tsp-vdd-en { - compatible = "regulator-fixed"; - regulator-name = "tsp_vdd_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpy3 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&gpu { - status = "okay"; - mali-supply = <&buck4_reg>; -}; - -&hsi2c_7 { - status = "okay"; - - pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_INT"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_G3D"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "VDD_KFC"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "VIN_LLDO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VIN_MLDO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VIN_HLDO"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "VDD_CAM_ISP"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3550000>; - }; - - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_APIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_APIO_MMC01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_ADC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_HRM_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_MIPI_PLL_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_VTF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_UOTG"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_HSIC_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_HSIC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDD_APIO_MMC2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD_MOTOR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD_CAM1_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - /* Unused */ - regulator-name = "VDD_LDO17"; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_CODEC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "VDD_VMMC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD_CAM1_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD_CAM_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo22_reg: LDO22 { - regulator-name = "VDD_CAM0_S_CORE"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD_MIFS"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD_MHL_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD_CAM0_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo27_reg: LDO27 { - regulator-name = "VDD_G3DS"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo28_reg: LDO28 { - regulator-name = "VDD_LCD_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo29_reg: LDO29 { - /* Unused */ - regulator-name = "VDD_LDO29"; - }; - - ldo30_reg: LDO30 { - regulator-name = "VDD_TOUCH"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo31_reg: LDO31 { - regulator-name = "VDD_COMP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "VDD_TOUCH_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo33_reg: LDO33 { - regulator-name = "VDD_MHL_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo34_reg: LDO34 { - regulator-name = "VDD_HRM_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo35_reg: LDO35 { - regulator-name = "VDD_SIL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo36_reg: LDO36 { - /* Unused */ - regulator-name = "VDD_LDO36"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo37_reg: LDO37 { - /* Unused */ - regulator-name = "VDD_LDO37"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo38_reg: LDO38 { - regulator-name = "VDD_KEY_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c_0 { - status = "okay"; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - interrupt-parent = <&gpx1>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - vio-supply = <&ldo32_reg>; - vdd-supply = <&tsp_vdd>; - syna,startup-delay-ms = <100>; - - pinctrl-0 = <&touch_irq>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -&pinctrl_0 { - s2mps11_irq: s2mps11-irq-pins { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - touch_irq: touch-irq-pins { - samsung,pins = "gpx1-6"; - samsung,pin-pud = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&timer { - arm,cpu-registers-not-fw-configured; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi deleted file mode 100644 index 8c0e1716c0b3..000000000000 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU/XU3 LED device tree source - * - * Copyright (c) 2015,2016 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include - -/ { - led-controller-1 { - compatible = "pwm-leds"; - - led-1 { - label = "green:mmc0"; - function = LED_FUNCTION_DISK_ACTIVITY; - color = ; - pwms = <&pwm 1 2000000 0>; - pwm-names = "pwm1"; - /* - * Green LED is much brighter than the others - * so limit its max brightness - */ - max-brightness = <127>; - linux,default-trigger = "mmc0"; - }; - - led-2 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-controller-2 { - compatible = "gpio-leds"; - - led-3 { - label = "red:microSD"; - function = LED_FUNCTION_DISK_ACTIVITY; - color = ; - gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi deleted file mode 100644 index 5c799886c275..000000000000 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos54xx SoC series common device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2016 Krzysztof Kozlowski - * - * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific - * Exynos 54xx SoCs should include this file and customize it further - * (e.g. with clocks). - */ - -#include "exynos5.dtsi" - -/ { - compatible = "samsung,exynos5"; - - aliases { - i2c4 = &hsi2c_4; - i2c5 = &hsi2c_5; - i2c6 = &hsi2c_6; - i2c7 = &hsi2c_7; - usbdrdphy0 = &usbdrd_phy0; - usbdrdphy1 = &usbdrd_phy1; - }; - - arm_a7_pmu: arm-a7-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - status = "disabled"; - }; - - arm_a15_pmu: arm-a15-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, - <7 0>, - <16 6>, - <19 2>; - status = "disabled"; - }; - - timer: timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - soc: soc { - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - - mct: timer@101c0000 { - compatible = "samsung,exynos5420-mct", - "samsung,exynos4210-mct"; - reg = <0x101c0000 0xb00>; - interrupts-extended = <&combiner 23 3>, - <&combiner 23 4>, - <&combiner 25 2>, - <&combiner 25 3>, - <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@101d0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101d0000 0x100>; - interrupts = ; - }; - - adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v2"; - reg = <0x12d10000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12ca0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12ca0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_5: i2c@12cb0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cb0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_6: i2c@12cc0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cc0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_7: i2c@12cd0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cd0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usbdrd3_0: usb@12000000 { - compatible = "samsung,exynos5250-dwusb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000000 0x10000>; - - usbdrd_dwc3_0: usb@0 { - compatible = "snps,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_u3_susphy_quirk; - }; - }; - - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb@12400000 { - compatible = "samsung,exynos5250-dwusb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12400000 0x10000>; - - usbdrd_dwc3_1: usb@0 { - compatible = "snps,dwc3"; - reg = <0x0 0x10000>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_u3_susphy_quirk; - }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - #phy-cells = <1>; - }; - - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = ; - phys = <&usb2_phy 0>; - phy-names = "host"; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = ; - phys = <&usb2_phy 0>; - phy-names = "host"; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5420-usb2-phy"; - reg = <0x12130000 0x100>; - #phy-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts deleted file mode 100644 index 1f544f12da6c..000000000000 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ /dev/null @@ -1,1108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Peach Pi Rev 10+ board device tree source - * - * Copyright (c) 2014 Google, Inc - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5420-cpus.dtsi" - -/ { - model = "Google Peach Pi Rev 10+"; - - compatible = "google,pi-rev16", - "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", - "google,pi-rev11", "google,pi-rev10", - "google,pi", "google,peach", "samsung,exynos5800", - "samsung,exynos5"; - chassis-type = "laptop"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - mmc0 = &mmc_0; /* eMMC */ - mmc1 = &mmc_2; /* SD */ - mmc2 = &mmc_1; /* WiFi */ - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power-key { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98091"; - - samsung,model = "Peach-Pi-I2S-MAX98091"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98091>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98091>, <&hdmi>; - }; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b133htn01"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - - mmc1_pwrseq: mmc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77802 MAX77802_CLK_32K_CP>; - clock-names = "ext_clock"; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_MAU_EPLL>; -}; - -/* - * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores - * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to - * update A7 OPPs table accordingly. - */ -&cluster_a7_opp_table { - /delete-node/opp-1400000000; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-coupled-with = <&buck3_reg>; - regulator-coupled-max-spread = <300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-coupled-with = <&buck2_reg>; - regulator-coupled-max-spread = <300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98091: codec@10 { - compatible = "maxim,max98091"; - reg = <0x10>; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98091_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - /* Atmel mXT540S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO 3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <800000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -/* WiFi SDIO module */ -&mmc_1 { - status = "okay"; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, - <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc1_pwrseq>; - vqmmc-supply = <&buck10_reg>; -}; - -/* uSD card */ -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - wifi_en: wifi-en-pins { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max98091_irq: max98091-irq-pins { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset-pins { - samsung,pins = "gpx0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq-pins { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq-pins { - samsung,pins = "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq-pins { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq-pins { - samsung,pins = "gpx1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq-pins { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp-hpd-gpio-pins { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77802_irq: max77802-irq-pins { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq-pins { - samsung,pins = "gpx3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq-pins { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1-pins { - samsung,pins = "gpy7-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -/* pinctrl_1 */ -/* Adjust WiFi drive strengths lower for EMI */ -&sd1_bus1 { - samsung,pin-drv = ; -}; - -&sd1_bus4 { - samsung,pin-drv = ; -}; - -&sd1_bus8 { - samsung,pin-drv = ; -}; - -&sd1_clk { - samsung,pin-drv = ; -}; - -&sd1_cmd { - samsung,pin-drv = ; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2-pins { - samsung,pins = "gpj4-2", "gpj4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -/* pinctrl_3*/ -/* Drive SPI lines at x2 for better integrity */ -&spi2_bus { - samsung,pin-drv = ; -}; - -&pinctrl_3 { - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs-pins { - samsung,pins = "gpb1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb300_vbus_en: usb300-vbus-en-pins { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en-pins { - samsung,pins = "gph0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_selb: pmic-selb-pins { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - google,has-vbc-nvram; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&serial_3 { - status = "okay"; -}; - -&timer { - arm,cpu-registers-not-fw-configured; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd3_0 { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; - -&usbdrd3_1 { - vdd10-supply = <&ldo15_reg>; - vdd33-supply = <&ldo12_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi deleted file mode 100644 index 72d3a3535a7a..000000000000 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5800 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5800 SoC device nodes are listed in this file. - * Exynos5800 based board files can include this file and provide - * values for board specific bindings. - */ - -#include "exynos5420.dtsi" - -/ { - compatible = "samsung,exynos5800", "samsung,exynos5"; -}; - -&clock { - compatible = "samsung,exynos5800-clock", "syscon"; -}; - -&cluster_a15_opp_table { - opp-2000000000 { - opp-hz = /bits/ 64 <2000000000>; - opp-microvolt = <1312500 1312500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1900000000 { - opp-hz = /bits/ 64 <1900000000>; - opp-microvolt = <1262500 1262500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1237500 1237500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-microvolt = <1250000 1250000 1500000>; - }; - opp-1600000000 { - opp-microvolt = <1250000 1250000 1500000>; - }; - opp-1500000000 { - opp-microvolt = <1100000 1100000 1500000>; - }; - opp-1400000000 { - opp-microvolt = <1100000 1100000 1500000>; - }; - opp-1300000000 { - opp-microvolt = <1100000 1100000 1500000>; - }; - opp-1200000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-1100000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-1000000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-900000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-800000000 { - opp-microvolt = <900000 900000 1500000>; - }; - opp-700000000 { - opp-microvolt = <900000 900000 1500000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; -}; - -&cluster_a7_opp_table { - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-microvolt = <1250000>; - }; - opp-1200000000 { - opp-microvolt = <1250000>; - }; - opp-1100000000 { - opp-microvolt = <1250000>; - }; - opp-1000000000 { - opp-microvolt = <1100000>; - }; - opp-900000000 { - opp-microvolt = <1100000>; - }; - opp-800000000 { - opp-microvolt = <1100000>; - }; - opp-700000000 { - opp-microvolt = <1000000>; - }; - opp-600000000 { - opp-microvolt = <1000000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; -}; - -&dsi { - compatible = "samsung,exynos5422-mipi-dsi"; -}; - -&mfc { - compatible = "samsung,mfc-v8"; -}; - -&soc { - cam_pd: power-domain@10045100 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10045100 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; -}; diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi b/arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi deleted file mode 100644 index 7f3652dea550..000000000000 --- a/arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2020 Facebook Inc. - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * u-boot partition: 896KB. - */ - u-boot@0 { - reg = <0x0 0xe0000>; - label = "u-boot"; - }; - - /* - * u-boot environment variables: 64KB. - */ - u-boot-env@e0000 { - reg = <0xe0000 0x10000>; - label = "env"; - }; - - /* - * image metadata partition (64KB), used by Facebook internal - * tools. - */ - image-meta@f0000 { - reg = <0xf0000 0x10000>; - label = "meta"; - }; - - /* - * FIT image: 119 MB. - */ - fit@100000 { - reg = <0x100000 0x7700000>; - label = "fit"; - }; - - /* - * "data0" partition (8MB) is used by Facebook BMC platforms as - * persistent data store. - */ - data0@7800000 { - reg = <0x7800000 0x800000>; - label = "data0"; - }; - - /* - * Although the master partition can be created by enabling - * MTD_PARTITIONED_MASTER option, below "flash0" partition is - * explicitly created to avoid breaking legacy applications. - */ - flash0@0 { - reg = <0x0 0x8000000>; - label = "flash0"; - }; -}; diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi b/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi deleted file mode 100644 index 87bb8b576250..000000000000 --- a/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0x60000>; - label = "u-boot"; - }; - - u-boot-env@60000 { - reg = <0x60000 0x20000>; - label = "env"; - }; - - fit@80000 { - reg = <0x80000 0x1b80000>; - label = "fit"; - }; - - /* - * "data0" partition is used by several Facebook BMC platforms - * as persistent data store. - */ - data0@1c00000 { - reg = <0x1c00000 0x400000>; - label = "data0"; - }; - - /* - * Although the master partition can be created by enabling - * MTD_PARTITIONED_MASTER option, below "flash0" partition is - * explicitly created to avoid breaking legacy applications. - */ - flash0@0 { - reg = <0x0 0x2000000>; - label = "flash0"; - }; -}; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi deleted file mode 100644 index dbba33e5a06c..000000000000 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 - * - * Copyright (C) 2012 Telit, - * 2012 Fabio Porcedda - */ - -#include "at91sam9260.dtsi" - -/ { - clocks { - main_xtal { - clock-frequency = <6000000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x0 0x7c0000>; - }; - - root@7c0000 { - label = "root"; - reg = <0x7c0000 0x7840000>; - }; - }; - }; - }; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; - }; -}; diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts deleted file mode 100644 index 396149664297..000000000000 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Device Tree file for D-Link DIR-685 Xtreme N Storage Router - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "D-Link DIR-685 Xtreme N Storage Router"; - compatible = "dlink,dir-685", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300"; - stdout-path = "uart0:19200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-esc { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - button-eject { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "unmount"; - /* Collides with LPC LFRAME, UART RTS, SSP TXD */ - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - }; - - vdisp: regulator { - compatible = "regulator-fixed"; - regulator-name = "display-power"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - /* Collides with LCD E */ - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - /* Collides with IDE pins, that's cool (we do not use them) */ - sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - panel: display@0 { - compatible = "dlink,dir-685-panel", "ilitek,ili9322"; - reg = <0>; - /* 50 ns min period = 20 MHz */ - spi-max-frequency = <20000000>; - vcc-supply = <&vdisp>; - iovcc-supply = <&vdisp>; - vci-supply = <&vdisp>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - led-wps { - label = "dir685:blue:WPS"; - /* Collides with ICE */ - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - /* - * These two LEDs are on the side of the device. - * For electrical reasons, both LEDs cannot be active - * at the same time so only blue or orange can be on at - * one time. Enabling both makes the LED go dark. - * The LEDs both sit inside the unmount button and the - * label on the case says "unmount". - */ - led-blue-hd { - label = "dir685:blue:HD"; - /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */ - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-read"; - }; - led-orange-hd { - label = "dir685:orange:HD"; - /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */ - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-write"; - }; - }; - - /* - * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. - * sensor. It is turned on when the temperature exceeds 46 degrees - * and turned off when the temperatures goes below 41 degrees - * (celsius). - */ - fan0: gpio-fan { - compatible = "gpio-fan"; - /* Collides with IDE */ - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, <10000 1>; - #cooling-cells = <2>; - }; - - thermal-zones { - chassis-thermal { - /* Poll every 20 seconds */ - polling-delay = <20000>; - /* Poll every 2nd second when cooling */ - polling-delay-passive = <2000>; - /* Use the thermal sensor in the hard drive */ - thermal-sensors = <&drive0>; - - /* Tripping points from the fan.script in the rootfs */ - trips { - alert: chassis-alert { - /* At 43 degrees turn on the fan */ - temperature = <43000>; - hysteresis = <3000>; - type = "active"; - }; - crit: chassis-crit { - /* Just shut down at 60 degrees */ - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&alert>; - cooling-device = <&fan0 1 1>; - }; - }; - }; - }; - - /* - * The touchpad input is connected to a GPIO bit-banged - * I2C bus. - */ - i2c { - compatible = "i2c-gpio"; - /* Collides with ICE */ - sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - touchkeys@26 { - compatible = "dlink,dir685-touchkeys"; - reg = <0x26>; - interrupt-parent = <&gpio0>; - /* Collides with NAND flash */ - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - }; - }; - - /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ - switch { - compatible = "realtek,rtl8366rb"; - /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ - mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - realtek,disable-leds; - - switch_intc: interrupt-controller { - /* GPIO 15 provides the interrupt */ - interrupt-parent = <&gpio0>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-handle = <&phy0>; - }; - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&phy1>; - }; - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&phy2>; - }; - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&phy3>; - }; - port@4 { - reg = <4>; - label = "wan"; - phy-handle = <&phy4>; - }; - rtl8366rb_cpu_port: port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy0: phy@0 { - reg = <0>; - interrupt-parent = <&switch_intc>; - interrupts = <0>; - }; - phy1: phy@1 { - reg = <1>; - interrupt-parent = <&switch_intc>; - interrupts = <1>; - }; - phy2: phy@2 { - reg = <2>; - interrupt-parent = <&switch_intc>; - interrupts = <2>; - }; - phy3: phy@3 { - reg = <3>; - interrupt-parent = <&switch_intc>; - interrupts = <3>; - }; - phy4: phy@4 { - reg = <4>; - interrupt-parent = <&switch_intc>; - interrupts = <12>; - }; - }; - }; - - soc { - flash@30000000 { - /* - * Flash access collides with the Chip Enable signal for - * the display panel, that reuse the parallel flash Chip - * Select 1 (CS1). We switch the pin control state so we - * enable these pins for flash access only when we need - * then, and when disabled they can be used for GPIO which - * is what the display panel needs. - */ - status = "okay"; - pinctrl-names = "enabled", "disabled"; - pinctrl-0 = <&pflash_default_pins>; - pinctrl-1 = <&pflash_disabled_pins>; - - /* 32MB of flash */ - reg = <0x30000000 0x02000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * This "RedBoot" is the Storlink derivative. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - /* - * This firmware image contains the kernel catenated - * with the squashfs root filesystem. For some reason - * this is called "upgrade" on the vendor system. - */ - partition@40000 { - label = "upgrade"; - reg = <0x00040000 0x01f40000>; - read-only; - }; - /* RGDB, Residental Gateway Database? */ - partition@1f80000 { - label = "rgdb"; - reg = <0x01f80000 0x00040000>; - read-only; - }; - /* - * This partition contains MAC addresses for WAN, - * WLAN and LAN, and the country code (for wireless - * I guess). - */ - partition@1fc0000 { - label = "nvram"; - reg = <0x01fc0000 0x00020000>; - read-only; - }; - partition@1fe0000 { - label = "LangPack"; - reg = <0x01fe0000 0x00020000>; - read-only; - }; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0bgrp cover line 5, 6 used by TK I2C - * gpio0bgrp cover line 7 used by WPS LED - * gpio0cgrp cover line 8, 13 used by keys - * and 11, 12 used by the HD LEDs - * and line 14, 15 used by RTL8366 - * RESET and phy ready - * gpio0egrp cover line 16 used by VDISP - * gpio0fgrp cover line 17 used by TK IRQ - * gpio0ggrp cover line 20 used by panel CS - * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0bgrp", - "gpio0cgrp", - "gpio0egrp", - "gpio0fgrp", - "gpio0hgrp"; - }; - }; - /* - * gpio1bgrp cover line 5,8,7 used by panel SPI - * also line 6 used by the fan - * - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1bgrp"; - }; - }; - /* - * These GPIO groups will be mapped in over some - * of the flash pins when the flash is not in - * active use. - */ - pflash_disabled_pins: pinctrl-pflash-disabled { - mux { - function = "gpio0"; - groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", - "gpio0kgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - conf0 { - pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV", - "Y7 GMAC0 RXC", "Y11 GMAC1 RXC", - "T8 GMAC0 TXEN", "W11 GMAC1 TXEN", - "U8 GMAC0 TXC", "V11 GMAC1 TXC", - "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", - "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", - "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", - "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", - "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", - "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", - "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", - "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Set up drive strength on GMAC0 to 16 mA */ - conf1 { - groups = "gmii_gmac0_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - pci@50000000 { - status = "okay"; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ide@63000000 { - status = "okay"; - - /* - * This drive may have a temperature sensor with a - * thermal zone we can use for thermal control of the - * chassis temperature using the fan. - */ - drive0: ide-port@0 { - reg = <0>; - #thermal-sensor-cells = <0>; - }; - }; - - display-controller@6a000000 { - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts deleted file mode 100644 index 138c47e1ac1b..000000000000 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include -#include - -/ { - model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; - compatible = "dlink,dns-313", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/sda4 rw rootwait"; - stdout-path = "uart0:19200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-esc { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-power { - label = "dns313:blue:power"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-disk-blue { - label = "dns313:blue:disk"; - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-disk-green { - label = "dns313:green:disk"; - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-read"; - }; - led-disk-red { - label = "dns313:red:disk"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-write"; - }; - }; - - /* - * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM. - */ - fan0: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, - <&gpio0 12 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; - #cooling-cells = <2>; - }; - - /* - * This is the type B USB connector on the device, - * a GPIO-controlled USB VBUS detect - */ - usb1_phy: phy { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - #phy-cells = <0>; - vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - - /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - g751: temperature-sensor@48 { - compatible = "gmt,g751"; - reg = <0x48>; - #thermal-sensor-cells = <0>; - }; - }; - - thermal-zones { - chassis-thermal { - /* Poll every 20 seconds */ - polling-delay = <20000>; - /* Poll every 2nd second when cooling */ - polling-delay-passive = <2000>; - - thermal-sensors = <&g751>; - - /* Tripping points from the fan.script in the rootfs */ - trips { - chassis_alert0: chassis-alert0 { - /* At 43 degrees turn on low speed */ - temperature = <43000>; - hysteresis = <3000>; - type = "active"; - }; - chassis_alert1: chassis-alert1 { - /* At 47 degrees turn on high speed */ - temperature = <47000>; - hysteresis = <3000>; - type = "active"; - }; - chassis_crit: chassis-crit { - /* Just shut down at 60 degrees */ - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&chassis_alert0>; - cooling-device = <&fan0 1 1>; - }; - map1 { - trip = <&chassis_alert1>; - cooling-device = <&fan0 2 2>; - }; - }; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - /* Uses MDC and MDIO */ - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* This is a Realtek RTL8211B Gigabit ethernet transceiver */ - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - /* - * This is a Eon EN29LV400AB 512 KiB flash with - * three partitions. - */ - compatible = "cortina,gemini-flash", "jedec-flash"; - status = "okay"; - reg = <0x30000000 0x00080000>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * This "RedBoot" is the Storlink derivative. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "MTD1"; - reg = <0x00040000 0x00020000>; - read-only; - }; - partition@60000 { - label = "MTD2"; - reg = <0x00060000 0x00020000>; - read-only; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = - /* Used by LEDs conflicts ICE */ - "gpio0bgrp", - /* Used by ? conflicts ICE */ - "gpio0cgrp", - /* - * Used by fan & G751, conflicts LPC, - * UART modem lines, SSP - */ - "gpio0egrp", - /* Used by G751 */ - "gpio0fgrp", - /* Used by MDIO */ - "gpio0igrp"; - }; - }; - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - /* Used by "reset" button */ - groups = "gpio1dgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - /* - * In the vendor Linux tree, these values are set for the C3 - * version of the SL3512 ASIC with the comment "benson suggest" - */ - conf0 { - pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; - skew-delay = <0>; - }; - conf1 { - pins = "T8 GMAC0 RXC"; - skew-delay = <10>; - }; - conf2 { - pins = "T11 GMAC1 RXC"; - skew-delay = <15>; - }; - conf3 { - pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf4 { - pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; - skew-delay = <10>; - }; - conf5 { - /* The data lines all have default skew */ - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; - skew-delay = <7>; - }; - conf6 { - pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; - skew-delay = <5>; - }; - /* Set up drive strength on GMAC0 to 16 mA */ - conf7 { - groups = "gmii_gmac0_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - /* The ROM uses this muxmode */ - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ide@63000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - dr_mode = "peripheral"; - usb-phy = <&usb1_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_default_pins>; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts deleted file mode 100644 index 6544c730340f..000000000000 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Raidsonic NAS IB-4220-B"; - compatible = "raidsonic,ib-4220-b", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "Backup button"; - /* Conflict with TVC */ - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - button-restart { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "Softreset button"; - /* Conflict with TVC */ - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-orange-hdd { - label = "nas4220b:orange:hdd"; - /* Conflict with TVC */ - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - led-green-os { - label = "nas4220b:green:os"; - /* Conflict with TVC */ - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 16MB of flash */ - reg = <0x30000000 0x01000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x7f>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio1dgrp cover line 28-31 otherwise used - * by TVC. - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - /* Settings come from OpenWRT, pins on SL3516 */ - conf0 { - pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; - skew-delay = <0>; - }; - conf1 { - pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; - skew-delay = <15>; - }; - conf2 { - pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf3 { - pins = "U8 GMAC0 TXC"; - skew-delay = <11>; - }; - conf4 { - pins = "V11 GMAC1 TXC"; - skew-delay = <10>; - }; - conf5 { - /* The data lines all have default skew */ - pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", - "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", - "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", - "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", - "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", - "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", - "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", - "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Set up drive strength on GMAC0 to 16 mA */ - conf6 { - groups = "gmii_gmac0_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ide@63000000 { - status = "okay"; - }; - - ide@63400000 { - status = "okay"; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-ns2502.dts b/arch/arm/boot/dts/gemini-ns2502.dts deleted file mode 100644 index e6eeb35e8819..000000000000 --- a/arch/arm/boot/dts/gemini-ns2502.dts +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Corentin Labbe - * Device Tree file for Edimax NS 2502 - */ - -/dts-v1/; - -#include "gemini.dtsi" - -/ { - model = "Edimax NS-2502"; - compatible = "edimax,ns-2502", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; - - chosen { - bootargs = "console=ttyS0,19200n8"; - stdout-path = &uart0; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; -}; - -ðernet { - status = "okay"; - ethernet-port@0 { - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - }; -}; - -&flash { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - - pinctrl-names = "enabled", "disabled"; - pinctrl-0 = <&pflash_default_pins>; - pinctrl-1 = <&pflash_disabled_pins>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; -}; - -&ide0 { - status = "okay"; -}; - -&ide1 { - status = "okay"; -}; - -&sata { - cortina,gemini-ata-muxmode = <3>; - cortina,gemini-enable-sata-bridge; - status = "okay"; -}; - -&syscon { - pinctrl { - /* - * gpio0agrp cover line 0-4 - * gpio0bgrp cover line 5 - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", "gpio0bgrp", "gpio0hgrp"; - }; - }; - pflash_disabled_pins: pinctrl-pflash-disabled { - mux { - function = "gpio0"; - groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", - "gpio0kgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - }; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts deleted file mode 100644 index 0ebda4efd9d0..000000000000 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Teltonika RUT1xx - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Teltonika RUT1xx"; - compatible = "teltonika,rut1xx", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "Reset to defaults"; - /* Conflict with TVC */ - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-gsm { - /* FIXME: add the LED color */ - label = "rut1xx::gsm"; - /* Conflict with ICE */ - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - led-power { - /* FIXME: add the LED color */ - label = "rut1xx::power"; - /* Conflict with NAND CE0 */ - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - /* TODO: add flash partitions here */ - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0bgrp cover line 7 used by GSM LED - * gpio0fgrp cover line 17 used by power LED - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0bgrp", - "gpio0fgrp"; - }; - }; - /* - * gpio1dgrp cover line 28-31 otherwise used - * by TVC. - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - }; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts deleted file mode 100644 index 91c19e8ebfe8..000000000000 --- a/arch/arm/boot/dts/gemini-sl93512r.dts +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for the Storm Semiconductor SL93512R_BRD - * Gemini reference design, also initially called - * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor. - * The series were later acquired by Cortina Systems. - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD"; - compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB Samsung K4H511638B */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-wps { - debounce-interval = <50>; - wakeup-source; - linux,code = ; - label = "WPS"; - /* Conflicts with TVC and extended flash */ - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - button-setup { - debounce-interval = <50>; - wakeup-source; - linux,code = ; - label = "factory reset"; - /* Conflict with NAND flash */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-green-harddisk { - label = "sq201:green:harddisk"; - /* Conflict with LCD (no problem) */ - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "disk-activity"; - }; - led-green-wireless { - label = "sq201:green:wireless"; - /* Conflict with NAND flash CE0 (no problem) */ - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - /* Uses MDC and MDIO */ - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* This is a Marvell 88E1111 ethernet transciever */ - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - /* Check pin collisions */ - sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - switch@0 { - compatible = "vitesse,vsc7385"; - reg = <0>; - /* Specified for 2.5 MHz or below */ - spi-max-frequency = <2500000>; - gpio-controller; - #gpio-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - vsc: port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; - - - soc { - flash@30000000 { - status = "okay"; - /* 16MB of flash */ - reg = <0x30000000 0x01000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0agrp cover line 0, used by WPS button - * gpio0fgrp cover line 16 used by HD LED - * gpio0ggrp cover line 17, 18 used by wireless LAN LED and - * reset button OR USB ID select on 17 and USB VBUS select - * on 18. (Confusing.) - * gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", - "gpio0fgrp", - "gpio0ggrp", - "gpio0igrp"; - }; - }; - /* - * gpio1dgrp cover lines used by SPI for - * the Vitesse chip (28-31) - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - /* Control pad skew comes from sl_switch.c in the vendor code */ - conf0 { - pins = "P10 GMAC1 TXC"; - skew-delay = <5>; - }; - conf1 { - pins = "V11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf2 { - pins = "T11 GMAC1 RXC"; - skew-delay = <8>; - }; - conf3 { - pins = "U11 GMAC1 RXDV"; - skew-delay = <7>; - }; - conf4 { - pins = "V7 GMAC0 TXC"; - skew-delay = <10>; - }; - conf5 { - pins = "P8 GMAC0 TXEN"; - skew-delay = <7>; /* 5 at another place? */ - }; - conf6 { - pins = "T8 GMAC0 RXC"; - skew-delay = <15>; - }; - conf7 { - pins = "R8 GMAC0 RXDV"; - skew-delay = <0>; - }; - conf8 { - /* The data lines all have default skew */ - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Appears in sl351x_gmac.c in the vendor code */ - conf9 { - pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; - skew-delay = <5>; - }; - }; - }; - }; - - /* Both interfaces brought out on SATA connectors */ - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - pci@50000000 { - status = "okay"; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - ide@63000000 { - status = "okay"; - }; - - ide@63400000 { - status = "okay"; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts deleted file mode 100644 index d0efd76695da..000000000000 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ /dev/null @@ -1,286 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for ITian Square One SQ201 NAS - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "ITian Square One SQ201"; - compatible = "itian,sq201", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "factory reset"; - /* Conflict with NAND flash */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-green-info { - label = "sq201:green:info"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-green-usb { - label = "sq201:green:usb"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "usb-host"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - /* Uses MDC and MDIO */ - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* This is a Marvell 88E1111 ethernet transciever */ - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - /* Check pin collisions */ - sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - switch@0 { - compatible = "vitesse,vsc7395"; - reg = <0>; - /* Specified for 2.5 MHz or below */ - spi-max-frequency = <2500000>; - gpio-controller; - #gpio-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - vsc: port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; - - - soc { - flash@30000000 { - status = "okay"; - pinctrl-names = "enabled", "disabled"; - pinctrl-0 = <&pflash_default_pins>; - pinctrl-1 = <&pflash_disabled_pins>; - /* 16MB of flash */ - reg = <0x30000000 0x01000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0fgrp cover line 18 used by reset button - * gpio0ggrp cover line 20 used by info LED - * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY - * gpio0kgrp cover line 31 used by USB LED - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0fgrp", - "gpio0hgrp"; - }; - }; - /* - * gpio0dgrp cover lines used by the SPI - * to the Vitesse G5x chip. - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - /* - * These GPIO groups will be mapped in over some - * of the flash pins when the flash is not in - * active use. - */ - pflash_disabled_pins: pinctrl-pflash-disabled { - mux { - function = "gpio0"; - groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", - "gpio0kgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - /* Settings come from memory dump in PLATO */ - conf0 { - pins = "V8 GMAC0 RXDV"; - skew-delay = <0>; - }; - conf1 { - pins = "Y7 GMAC0 RXC"; - skew-delay = <15>; - }; - conf2 { - pins = "T8 GMAC0 TXEN"; - skew-delay = <7>; - }; - conf3 { - pins = "U8 GMAC0 TXC"; - skew-delay = <10>; - }; - conf4 { - pins = "T10 GMAC1 RXDV"; - skew-delay = <7>; - }; - conf5 { - pins = "Y11 GMAC1 RXC"; - skew-delay = <8>; - }; - conf6 { - pins = "W11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf7 { - pins = "V11 GMAC1 TXC"; - skew-delay = <5>; - }; - conf8 { - /* The data lines all have default skew */ - pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", - "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", - "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", - "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", - "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", - "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", - "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", - "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */ - conf9 { - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - pci@50000000 { - status = "okay"; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - ide@63000000 { - status = "okay"; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini-ssi1328.dts deleted file mode 100644 index 42e85f07cf76..000000000000 --- a/arch/arm/boot/dts/gemini-ssi1328.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Corentin Labbe - * Device Tree file for SSI 1328 - */ - -/dts-v1/; - -#include "gemini.dtsi" - -/ { - model = "SSI 1328"; - compatible = "ssi,1328", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 initrd=0x900000,9M"; - stdout-path = &uart0; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* LAN Marvell 88E1118 */ - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - /* WAN ICPlus IP101A */ - phy1: ethernet-phy@2 { - reg = <2>; - device_type = "ethernet-phy"; - }; - }; -}; - -ðernet { - status = "okay"; - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; -}; - -&flash { - status = "okay"; - /* 32MB of flash */ - reg = <0x30000000 0x03200000>; - - pinctrl-names = "enabled", "disabled"; - pinctrl-0 = <&pflash_default_pins>; - pinctrl-1 = <&pflash_disabled_pins>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x7F>; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; -}; - -&ide0 { - status = "okay"; -}; - -&ide1 { - status = "okay"; -}; - -&sata { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; -}; - -&syscon { - pinctrl { - /* - * gpio0agrp cover line 0-4 - * gpio0bgrp cover line 5 - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", "gpio0bgrp"; - }; - }; - pflash_disabled_pins: pinctrl-pflash-disabled { - mux { - function = "gpio0"; - groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", - "gpio0kgrp"; - }; - }; - pinctrl-gmii { - /* This platform use both the ethernet ports */ - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - }; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts deleted file mode 100644 index 3c88c59ab481..000000000000 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Wiliboard WBD-111 - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Wiliboard WBD-111"; - compatible = "wiliboard,wbd111", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* Conflict with ICE */ - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-red-l3 { - label = "wbd111:red:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-green-l4 { - label = "wbd111:green:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-red-l4 { - label = "wbd111:red:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-greeb-l3 { - label = "wbd111:green:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0agrp cover line 0-4 - * gpio0bgrp cover line 5 - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", - "gpio0bgrp"; - }; - }; - }; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - pci@50000000 { - status = "okay"; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts deleted file mode 100644 index ff72bbc4db3e..000000000000 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Wiliboard WBD-222 - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Wiliboard WBD-222"; - compatible = "wiliboard,wbd222", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* Conflict with ICE */ - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-red-l3 { - label = "wbd111:red:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-green-l4 { - label = "wbd111:green:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-red-l4 { - label = "wbd111:red:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-green-l3 { - label = "wbd111:green:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - - phy1: ethernet-phy@3 { - reg = <3>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0agrp cover line 0-4 - * gpio0bgrp cover line 5 - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", - "gpio0bgrp"; - }; - }; - pinctrl-gmii { - /* This platform use both the ethernet ports */ - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - }; - }; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - pci@50000000 { - status = "okay"; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi deleted file mode 100644 index befe322bd7de..000000000000 --- a/arch/arm/boot/dts/gemini.dtsi +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Cortina systems Gemini SoC - */ - -#include -#include -#include -#include - -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - interrupt-parent = <&intcon>; - - flash: flash@30000000 { - compatible = "cortina,gemini-flash", "cfi-flash"; - syscon = <&syscon>; - pinctrl-names = "default"; - pinctrl-0 = <&pflash_default_pins>; - bank-width = <2>; - status = "disabled"; - }; - - syscon: syscon@40000000 { - compatible = "cortina,gemini-syscon", - "syscon", "simple-mfd"; - reg = <0x40000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&syscon>; - /* GLOBAL_RESET register */ - offset = <0x0c>; - /* RESET_GLOBAL | RESET_CPU1 */ - mask = <0xC0000000>; - }; - - pinctrl { - compatible = "cortina,gemini-pinctrl"; - regmap = <&syscon>; - /* Hog the DRAM pins */ - pinctrl-names = "default"; - pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, - <&vcontrol_default_pins>; - - dram_default_pins: pinctrl-dram { - mux { - function = "dram"; - groups = "dramgrp"; - }; - }; - rtc_default_pins: pinctrl-rtc { - mux { - function = "rtc"; - groups = "rtcgrp"; - }; - }; - power_default_pins: pinctrl-power { - mux { - function = "power"; - groups = "powergrp"; - }; - }; - cir_default_pins: pinctrl-cir { - mux { - function = "cir"; - groups = "cirgrp"; - }; - }; - system_default_pins: pinctrl-system { - mux { - function = "system"; - groups = "systemgrp"; - }; - }; - vcontrol_default_pins: pinctrl-vcontrol { - mux { - function = "vcontrol"; - groups = "vcontrolgrp"; - }; - }; - ice_default_pins: pinctrl-ice { - mux { - function = "ice"; - groups = "icegrp"; - }; - }; - uart_default_pins: pinctrl-uart { - mux { - function = "uart"; - groups = "uartrxtxgrp"; - }; - }; - pflash_default_pins: pinctrl-pflash { - mux { - function = "pflash"; - groups = "pflashgrp"; - }; - }; - usb_default_pins: pinctrl-usb { - mux { - function = "usb"; - groups = "usbgrp"; - }; - }; - gmii_default_pins: pinctrl-gmii { - /* - * Only activate GMAC0 by default since - * GMAC1 will overlap with 8 GPIO lines - * gpio2a, gpio2b. Overlay groups with - * "gmii_gmac0_grp", "gmii_gmac1_grp" for - * both ethernet interfaces. - */ - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - }; - pci_default_pins: pinctrl-pci { - mux { - function = "pci"; - groups = "pcigrp"; - }; - }; - sata_default_pins: pinctrl-sata { - mux { - function = "sata"; - groups = "satagrp"; - }; - }; - /* Activate both groups of pins for this state */ - sata_and_ide_pins: pinctrl-sata-ide { - mux0 { - function = "sata"; - groups = "satagrp"; - }; - mux1 { - function = "ide"; - groups = "idegrp"; - }; - }; - tvc_default_pins: pinctrl-tvc { - mux { - function = "tvc"; - groups = "tvcgrp"; - }; - }; - }; - }; - - watchdog@41000000 { - compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; - reg = <0x41000000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_WDOG>; - clocks = <&syscon GEMINI_CLK_APB>; - clock-names = "PCLK"; - }; - - uart0: serial@42000000 { - compatible = "ns16550a"; - reg = <0x42000000 0x100>; - resets = <&syscon GEMINI_RESET_UART>; - clocks = <&syscon GEMINI_CLK_UART>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&uart_default_pins>; - reg-shift = <2>; - }; - - timer@43000000 { - compatible = "faraday,fttmr010"; - reg = <0x43000000 0x1000>; - interrupt-parent = <&intcon>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ - resets = <&syscon GEMINI_RESET_TIMER>; - /* APB clock or RTC clock */ - clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; - clock-names = "PCLK", "EXTCLK"; - syscon = <&syscon>; - }; - - rtc@45000000 { - compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; - reg = <0x45000000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_RTC>; - clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; - clock-names = "PCLK", "EXTCLK"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_default_pins>; - }; - - sata: sata@46000000 { - compatible = "cortina,gemini-sata-bridge"; - reg = <0x46000000 0x100>; - resets = <&syscon GEMINI_RESET_SATA0>, - <&syscon GEMINI_RESET_SATA1>; - reset-names = "sata0", "sata1"; - clocks = <&syscon GEMINI_CLK_GATE_SATA0>, - <&syscon GEMINI_CLK_GATE_SATA1>; - clock-names = "SATA0_PCLK", "SATA1_PCLK"; - /* - * This defines the special "ide" state that needs - * to be explicitly enabled to enable the IDE pins, - * as these pins are normally used for other things. - */ - pinctrl-names = "default", "ide"; - pinctrl-0 = <&sata_default_pins>; - pinctrl-1 = <&sata_and_ide_pins>; - syscon = <&syscon>; - status = "disabled"; - }; - - intcon: interrupt-controller@48000000 { - compatible = "faraday,ftintc010"; - reg = <0x48000000 0x1000>; - resets = <&syscon GEMINI_RESET_INTCON0>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - power-controller@4b000000 { - compatible = "cortina,gemini-power-controller"; - reg = <0x4b000000 0x100>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&power_default_pins>; - }; - - gpio0: gpio@4d000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4d000000 0x100>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GPIO0>; - clocks = <&syscon GEMINI_CLK_APB>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@4e000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4e000000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GPIO1>; - clocks = <&syscon GEMINI_CLK_APB>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4f000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4f000000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GPIO2>; - clocks = <&syscon GEMINI_CLK_APB>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pci@50000000 { - compatible = "cortina,gemini-pci", "faraday,ftpci100"; - /* - * The first 256 bytes in the IO range is actually used - * to configure the host bridge. - */ - reg = <0x50000000 0x100>; - resets = <&syscon GEMINI_RESET_PCI>; - clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; - clock-names = "PCLK", "PCICLK"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_default_pins>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - - bus-range = <0x00 0xff>; - /* PCI ranges mappings */ - ranges = - /* 1MiB I/O space 0x50000000-0x500fffff */ - <0x01000000 0 0 0x50000000 0 0x00100000>, - /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ - <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; - - /* DMA ranges */ - dma-ranges = - /* 128MiB at 0x00000000-0x07ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, - /* 64MiB at 0x00000000-0x03ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, - /* 64MiB at 0x00000000-0x03ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; - - /* - * This PCI host bridge variant has a cascaded interrupt - * controller embedded in the host bridge. - */ - pci_intc: interrupt-controller { - interrupt-parent = <&intcon>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - ethernet: ethernet@60000000 { - compatible = "cortina,gemini-ethernet"; - reg = <0x60000000 0x4000>, /* Global registers, queue */ - <0x60004000 0x2000>, /* V-bit */ - <0x60006000 0x2000>; /* A-bit */ - pinctrl-names = "default"; - pinctrl-0 = <&gmii_default_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gmac0: ethernet-port@0 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ - <0x6000a000 0x2000>; /* Port 0 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC0>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; - clock-names = "PCLK"; - }; - - gmac1: ethernet-port@1 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ - <0x6000e000 0x2000>; /* Port 1 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC1>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; - clock-names = "PCLK"; - }; - }; - - crypto: crypto@62000000 { - compatible = "cortina,sl3516-crypto"; - reg = <0x62000000 0x10000>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_SECURITY>; - clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; - }; - - ide0: ide@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x1000>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_IDE>; - clocks = <&syscon GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ide1: ide@63400000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63400000 0x1000>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_IDE>; - clocks = <&syscon GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - dma-controller@67000000 { - compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; - /* Faraday Technology FTDMAC020 variant */ - arm,primecell-periphid = <0x0003b080>; - reg = <0x67000000 0x1000>; - interrupts = <9 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_DMAC>; - clocks = <&syscon GEMINI_CLK_AHB>; - clock-names = "apb_pclk"; - /* Bus interface AHB1 (AHB0) is totally tilted */ - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - - display-controller@6a000000 { - compatible = "cortina,gemini-tvc", "faraday,tve200"; - reg = <0x6a000000 0x1000>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_TVC>; - clocks = <&syscon GEMINI_CLK_GATE_TVC>, - <&syscon GEMINI_CLK_TVC>; - clock-names = "PCLK", "TVE"; - pinctrl-names = "default"; - pinctrl-0 = <&tvc_default_pins>; - status = "disabled"; - }; - - usb0: usb@68000000 { - compatible = "cortina,gemini-usb", "faraday,fotg200"; - reg = <0x68000000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_USB0>; - clocks = <&syscon GEMINI_CLK_GATE_USB0>; - clock-names = "PCLK"; - /* - * This will claim pins for USB0 and USB1 at the same - * time as they are using some common pins. If you for - * some reason have a system using USB1 at 96000000 but - * NOT using USB0 at 68000000 you wll have to add the - * usb_default_pins to the USB controller at 96000000 - * in your .dts for the board. - */ - pinctrl-names = "default"; - pinctrl-0 = <&usb_default_pins>; - /* Default to host mode */ - dr_mode = "host"; - syscon = <&syscon>; - status = "disabled"; - }; - - usb1: usb@69000000 { - compatible = "cortina,gemini-usb", "faraday,fotg200"; - reg = <0x69000000 0x1000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_USB1>; - clocks = <&syscon GEMINI_CLK_GATE_USB1>; - clock-names = "PCLK"; - syscon = <&syscon>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/gemini/Makefile b/arch/arm/boot/dts/gemini/Makefile new file mode 100644 index 000000000000..f9f63ce3eb49 --- /dev/null +++ b/arch/arm/boot/dts/gemini/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_GEMINI) += \ + gemini-dlink-dir-685.dtb \ + gemini-dlink-dns-313.dtb \ + gemini-nas4220b.dtb \ + gemini-ns2502.dtb \ + gemini-rut1xx.dtb \ + gemini-sl93512r.dtb \ + gemini-sq201.dtb \ + gemini-ssi1328.dtb \ + gemini-wbd111.dtb \ + gemini-wbd222.dtb diff --git a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts new file mode 100644 index 000000000000..396149664297 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts @@ -0,0 +1,492 @@ +/* + * Device Tree file for D-Link DIR-685 Xtreme N Storage Router + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "D-Link DIR-685 Xtreme N Storage Router"; + compatible = "dlink,dir-685", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300"; + stdout-path = "uart0:19200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-esc { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "reset"; + /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + button-eject { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "unmount"; + /* Collides with LPC LFRAME, UART RTS, SSP TXD */ + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + + vdisp: regulator { + compatible = "regulator-fixed"; + regulator-name = "display-power"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + /* Collides with LCD E */ + gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Collides with IDE pins, that's cool (we do not use them) */ + sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + panel: display@0 { + compatible = "dlink,dir-685-panel", "ilitek,ili9322"; + reg = <0>; + /* 50 ns min period = 20 MHz */ + spi-max-frequency = <20000000>; + vcc-supply = <&vdisp>; + iovcc-supply = <&vdisp>; + vci-supply = <&vdisp>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + led-wps { + label = "dir685:blue:WPS"; + /* Collides with ICE */ + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + /* + * These two LEDs are on the side of the device. + * For electrical reasons, both LEDs cannot be active + * at the same time so only blue or orange can be on at + * one time. Enabling both makes the LED go dark. + * The LEDs both sit inside the unmount button and the + * label on the case says "unmount". + */ + led-blue-hd { + label = "dir685:blue:HD"; + /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */ + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "disk-read"; + }; + led-orange-hd { + label = "dir685:orange:HD"; + /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */ + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "disk-write"; + }; + }; + + /* + * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. + * sensor. It is turned on when the temperature exceeds 46 degrees + * and turned off when the temperatures goes below 41 degrees + * (celsius). + */ + fan0: gpio-fan { + compatible = "gpio-fan"; + /* Collides with IDE */ + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, <10000 1>; + #cooling-cells = <2>; + }; + + thermal-zones { + chassis-thermal { + /* Poll every 20 seconds */ + polling-delay = <20000>; + /* Poll every 2nd second when cooling */ + polling-delay-passive = <2000>; + /* Use the thermal sensor in the hard drive */ + thermal-sensors = <&drive0>; + + /* Tripping points from the fan.script in the rootfs */ + trips { + alert: chassis-alert { + /* At 43 degrees turn on the fan */ + temperature = <43000>; + hysteresis = <3000>; + type = "active"; + }; + crit: chassis-crit { + /* Just shut down at 60 degrees */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert>; + cooling-device = <&fan0 1 1>; + }; + }; + }; + }; + + /* + * The touchpad input is connected to a GPIO bit-banged + * I2C bus. + */ + i2c { + compatible = "i2c-gpio"; + /* Collides with ICE */ + sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + touchkeys@26 { + compatible = "dlink,dir685-touchkeys"; + reg = <0x26>; + interrupt-parent = <&gpio0>; + /* Collides with NAND flash */ + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + }; + }; + + /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ + switch { + compatible = "realtek,rtl8366rb"; + /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ + mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + + switch_intc: interrupt-controller { + /* GPIO 15 provides the interrupt */ + interrupt-parent = <&gpio0>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&phy0>; + }; + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&phy1>; + }; + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&phy2>; + }; + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&phy3>; + }; + port@4 { + reg = <4>; + label = "wan"; + phy-handle = <&phy4>; + }; + rtl8366rb_cpu_port: port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + interrupt-parent = <&switch_intc>; + interrupts = <0>; + }; + phy1: phy@1 { + reg = <1>; + interrupt-parent = <&switch_intc>; + interrupts = <1>; + }; + phy2: phy@2 { + reg = <2>; + interrupt-parent = <&switch_intc>; + interrupts = <2>; + }; + phy3: phy@3 { + reg = <3>; + interrupt-parent = <&switch_intc>; + interrupts = <3>; + }; + phy4: phy@4 { + reg = <4>; + interrupt-parent = <&switch_intc>; + interrupts = <12>; + }; + }; + }; + + soc { + flash@30000000 { + /* + * Flash access collides with the Chip Enable signal for + * the display panel, that reuse the parallel flash Chip + * Select 1 (CS1). We switch the pin control state so we + * enable these pins for flash access only when we need + * then, and when disabled they can be used for GPIO which + * is what the display panel needs. + */ + status = "okay"; + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; + + /* 32MB of flash */ + reg = <0x30000000 0x02000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * This "RedBoot" is the Storlink derivative. + */ + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + /* + * This firmware image contains the kernel catenated + * with the squashfs root filesystem. For some reason + * this is called "upgrade" on the vendor system. + */ + partition@40000 { + label = "upgrade"; + reg = <0x00040000 0x01f40000>; + read-only; + }; + /* RGDB, Residental Gateway Database? */ + partition@1f80000 { + label = "rgdb"; + reg = <0x01f80000 0x00040000>; + read-only; + }; + /* + * This partition contains MAC addresses for WAN, + * WLAN and LAN, and the country code (for wireless + * I guess). + */ + partition@1fc0000 { + label = "nvram"; + reg = <0x01fc0000 0x00020000>; + read-only; + }; + partition@1fe0000 { + label = "LangPack"; + reg = <0x01fe0000 0x00020000>; + read-only; + }; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0bgrp cover line 5, 6 used by TK I2C + * gpio0bgrp cover line 7 used by WPS LED + * gpio0cgrp cover line 8, 13 used by keys + * and 11, 12 used by the HD LEDs + * and line 14, 15 used by RTL8366 + * RESET and phy ready + * gpio0egrp cover line 16 used by VDISP + * gpio0fgrp cover line 17 used by TK IRQ + * gpio0ggrp cover line 20 used by panel CS + * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0bgrp", + "gpio0cgrp", + "gpio0egrp", + "gpio0fgrp", + "gpio0hgrp"; + }; + }; + /* + * gpio1bgrp cover line 5,8,7 used by panel SPI + * also line 6 used by the fan + * + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1bgrp"; + }; + }; + /* + * These GPIO groups will be mapped in over some + * of the flash pins when the flash is not in + * active use. + */ + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + conf0 { + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV", + "Y7 GMAC0 RXC", "Y11 GMAC1 RXC", + "T8 GMAC0 TXEN", "W11 GMAC1 TXEN", + "U8 GMAC0 TXC", "V11 GMAC1 TXC", + "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf1 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; + }; + }; + + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + pci@50000000 { + status = "okay"; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + ide@63000000 { + status = "okay"; + + /* + * This drive may have a temperature sensor with a + * thermal zone we can use for thermal control of the + * chassis temperature using the fan. + */ + drive0: ide-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; + }; + + display-controller@6a000000 { + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts new file mode 100644 index 000000000000..138c47e1ac1b --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include +#include + +/ { + model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; + compatible = "dlink,dns-313", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/sda4 rw rootwait"; + stdout-path = "uart0:19200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-esc { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-power { + label = "dns313:blue:power"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-disk-blue { + label = "dns313:blue:disk"; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-disk-green { + label = "dns313:green:disk"; + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "disk-read"; + }; + led-disk-red { + label = "dns313:red:disk"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "disk-write"; + }; + }; + + /* + * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM. + */ + fan0: gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, + <&gpio0 12 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; + #cooling-cells = <2>; + }; + + /* + * This is the type B USB connector on the device, + * a GPIO-controlled USB VBUS detect + */ + usb1_phy: phy { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + #phy-cells = <0>; + vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + + /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + g751: temperature-sensor@48 { + compatible = "gmt,g751"; + reg = <0x48>; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + chassis-thermal { + /* Poll every 20 seconds */ + polling-delay = <20000>; + /* Poll every 2nd second when cooling */ + polling-delay-passive = <2000>; + + thermal-sensors = <&g751>; + + /* Tripping points from the fan.script in the rootfs */ + trips { + chassis_alert0: chassis-alert0 { + /* At 43 degrees turn on low speed */ + temperature = <43000>; + hysteresis = <3000>; + type = "active"; + }; + chassis_alert1: chassis-alert1 { + /* At 47 degrees turn on high speed */ + temperature = <47000>; + hysteresis = <3000>; + type = "active"; + }; + chassis_crit: chassis-crit { + /* Just shut down at 60 degrees */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&chassis_alert0>; + cooling-device = <&fan0 1 1>; + }; + map1 { + trip = <&chassis_alert1>; + cooling-device = <&fan0 2 2>; + }; + }; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Realtek RTL8211B Gigabit ethernet transceiver */ + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + /* + * This is a Eon EN29LV400AB 512 KiB flash with + * three partitions. + */ + compatible = "cortina,gemini-flash", "jedec-flash"; + status = "okay"; + reg = <0x30000000 0x00080000>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * This "RedBoot" is the Storlink derivative. + */ + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "MTD1"; + reg = <0x00040000 0x00020000>; + read-only; + }; + partition@60000 { + label = "MTD2"; + reg = <0x00060000 0x00020000>; + read-only; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = + /* Used by LEDs conflicts ICE */ + "gpio0bgrp", + /* Used by ? conflicts ICE */ + "gpio0cgrp", + /* + * Used by fan & G751, conflicts LPC, + * UART modem lines, SSP + */ + "gpio0egrp", + /* Used by G751 */ + "gpio0fgrp", + /* Used by MDIO */ + "gpio0igrp"; + }; + }; + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + /* Used by "reset" button */ + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + /* + * In the vendor Linux tree, these values are set for the C3 + * version of the SL3512 ASIC with the comment "benson suggest" + */ + conf0 { + pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "T8 GMAC0 RXC"; + skew-delay = <10>; + }; + conf2 { + pins = "T11 GMAC1 RXC"; + skew-delay = <15>; + }; + conf3 { + pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf4 { + pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; + skew-delay = <10>; + }; + conf5 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + conf6 { + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; + skew-delay = <5>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf7 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; + }; + }; + + sata: sata@46000000 { + /* The ROM uses this muxmode */ + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + ide@63000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + dr_mode = "peripheral"; + usb-phy = <&usb1_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_default_pins>; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini/gemini-nas4220b.dts new file mode 100644 index 000000000000..6544c730340f --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-nas4220b.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Raidsonic NAS IB-4220-B"; + compatible = "raidsonic,ib-4220-b", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-setup { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "Backup button"; + /* Conflict with TVC */ + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; + button-restart { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "Softreset button"; + /* Conflict with TVC */ + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-orange-hdd { + label = "nas4220b:orange:hdd"; + /* Conflict with TVC */ + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + led-green-os { + label = "nas4220b:green:os"; + /* Conflict with TVC */ + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + status = "okay"; + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x7f>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio1dgrp cover line 28-31 otherwise used + * by TVC. + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + /* Settings come from OpenWRT, pins on SL3516 */ + conf0 { + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "U8 GMAC0 TXC"; + skew-delay = <11>; + }; + conf4 { + pins = "V11 GMAC1 TXC"; + skew-delay = <10>; + }; + conf5 { + /* The data lines all have default skew */ + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf6 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; + }; + }; + + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + ide@63000000 { + status = "okay"; + }; + + ide@63400000 { + status = "okay"; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-ns2502.dts b/arch/arm/boot/dts/gemini/gemini-ns2502.dts new file mode 100644 index 000000000000..e6eeb35e8819 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-ns2502.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Corentin Labbe + * Device Tree file for Edimax NS 2502 + */ + +/dts-v1/; + +#include "gemini.dtsi" + +/ { + model = "Edimax NS-2502"; + compatible = "edimax,ns-2502", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + chosen { + bootargs = "console=ttyS0,19200n8"; + stdout-path = &uart0; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; +}; + +ðernet { + status = "okay"; + ethernet-port@0 { + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + }; +}; + +&flash { + status = "okay"; + /* 8MB of flash */ + reg = <0x30000000 0x00800000>; + + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; +}; + +&ide0 { + status = "okay"; +}; + +&ide1 { + status = "okay"; +}; + +&sata { + cortina,gemini-ata-muxmode = <3>; + cortina,gemini-enable-sata-bridge; + status = "okay"; +}; + +&syscon { + pinctrl { + /* + * gpio0agrp cover line 0-4 + * gpio0bgrp cover line 5 + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", "gpio0bgrp", "gpio0hgrp"; + }; + }; + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + }; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini/gemini-rut1xx.dts new file mode 100644 index 000000000000..0ebda4efd9d0 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-rut1xx.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Teltonika RUT1xx + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Teltonika RUT1xx"; + compatible = "teltonika,rut1xx", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-setup { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "Reset to defaults"; + /* Conflict with TVC */ + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-gsm { + /* FIXME: add the LED color */ + label = "rut1xx::gsm"; + /* Conflict with ICE */ + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + led-power { + /* FIXME: add the LED color */ + label = "rut1xx::power"; + /* Conflict with NAND CE0 */ + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + status = "okay"; + /* 8MB of flash */ + reg = <0x30000000 0x00800000>; + /* TODO: add flash partitions here */ + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0bgrp cover line 7 used by GSM LED + * gpio0fgrp cover line 17 used by power LED + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0bgrp", + "gpio0fgrp"; + }; + }; + /* + * gpio1dgrp cover line 28-31 otherwise used + * by TVC. + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + }; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts new file mode 100644 index 000000000000..91c19e8ebfe8 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the Storm Semiconductor SL93512R_BRD + * Gemini reference design, also initially called + * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor. + * The series were later acquired by Cortina Systems. + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD"; + compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB Samsung K4H511638B */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-wps { + debounce-interval = <50>; + wakeup-source; + linux,code = ; + label = "WPS"; + /* Conflicts with TVC and extended flash */ + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + button-setup { + debounce-interval = <50>; + wakeup-source; + linux,code = ; + label = "factory reset"; + /* Conflict with NAND flash */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-green-harddisk { + label = "sq201:green:harddisk"; + /* Conflict with LCD (no problem) */ + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "disk-activity"; + }; + led-green-wireless { + label = "sq201:green:wireless"; + /* Conflict with NAND flash CE0 (no problem) */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Marvell 88E1111 ethernet transciever */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + /* Check pin collisions */ + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + switch@0 { + compatible = "vitesse,vsc7385"; + reg = <0>; + /* Specified for 2.5 MHz or below */ + spi-max-frequency = <2500000>; + gpio-controller; + #gpio-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + vsc: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + + soc { + flash@30000000 { + status = "okay"; + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x1fc>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0agrp cover line 0, used by WPS button + * gpio0fgrp cover line 16 used by HD LED + * gpio0ggrp cover line 17, 18 used by wireless LAN LED and + * reset button OR USB ID select on 17 and USB VBUS select + * on 18. (Confusing.) + * gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", + "gpio0fgrp", + "gpio0ggrp", + "gpio0igrp"; + }; + }; + /* + * gpio1dgrp cover lines used by SPI for + * the Vitesse chip (28-31) + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + /* Control pad skew comes from sl_switch.c in the vendor code */ + conf0 { + pins = "P10 GMAC1 TXC"; + skew-delay = <5>; + }; + conf1 { + pins = "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf2 { + pins = "T11 GMAC1 RXC"; + skew-delay = <8>; + }; + conf3 { + pins = "U11 GMAC1 RXDV"; + skew-delay = <7>; + }; + conf4 { + pins = "V7 GMAC0 TXC"; + skew-delay = <10>; + }; + conf5 { + pins = "P8 GMAC0 TXEN"; + skew-delay = <7>; /* 5 at another place? */ + }; + conf6 { + pins = "T8 GMAC0 RXC"; + skew-delay = <15>; + }; + conf7 { + pins = "R8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf8 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Appears in sl351x_gmac.c in the vendor code */ + conf9 { + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; + skew-delay = <5>; + }; + }; + }; + }; + + /* Both interfaces brought out on SATA connectors */ + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + pci@50000000 { + status = "okay"; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + ide@63000000 { + status = "okay"; + }; + + ide@63400000 { + status = "okay"; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-sq201.dts b/arch/arm/boot/dts/gemini/gemini-sq201.dts new file mode 100644 index 000000000000..d0efd76695da --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-sq201.dts @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for ITian Square One SQ201 NAS + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "ITian Square One SQ201"; + compatible = "itian,sq201", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-setup { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "factory reset"; + /* Conflict with NAND flash */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-green-info { + label = "sq201:green:info"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-green-usb { + label = "sq201:green:usb"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "usb-host"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Marvell 88E1111 ethernet transciever */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + /* Check pin collisions */ + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + switch@0 { + compatible = "vitesse,vsc7395"; + reg = <0>; + /* Specified for 2.5 MHz or below */ + spi-max-frequency = <2500000>; + gpio-controller; + #gpio-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + vsc: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + + soc { + flash@30000000 { + status = "okay"; + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x1fc>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0fgrp cover line 18 used by reset button + * gpio0ggrp cover line 20 used by info LED + * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY + * gpio0kgrp cover line 31 used by USB LED + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0fgrp", + "gpio0hgrp"; + }; + }; + /* + * gpio0dgrp cover lines used by the SPI + * to the Vitesse G5x chip. + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + /* + * These GPIO groups will be mapped in over some + * of the flash pins when the flash is not in + * active use. + */ + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + /* Settings come from memory dump in PLATO */ + conf0 { + pins = "V8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "Y7 GMAC0 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "T8 GMAC0 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "U8 GMAC0 TXC"; + skew-delay = <10>; + }; + conf4 { + pins = "T10 GMAC1 RXDV"; + skew-delay = <7>; + }; + conf5 { + pins = "Y11 GMAC1 RXC"; + skew-delay = <8>; + }; + conf6 { + pins = "W11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf7 { + pins = "V11 GMAC1 TXC"; + skew-delay = <5>; + }; + conf8 { + /* The data lines all have default skew */ + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */ + conf9 { + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + drive-strength = <16>; + }; + }; + }; + }; + + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + pci@50000000 { + status = "okay"; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + ide@63000000 { + status = "okay"; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini/gemini-ssi1328.dts new file mode 100644 index 000000000000..42e85f07cf76 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-ssi1328.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Corentin Labbe + * Device Tree file for SSI 1328 + */ + +/dts-v1/; + +#include "gemini.dtsi" + +/ { + model = "SSI 1328"; + compatible = "ssi,1328", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 initrd=0x900000,9M"; + stdout-path = &uart0; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* LAN Marvell 88E1118 */ + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + /* WAN ICPlus IP101A */ + phy1: ethernet-phy@2 { + reg = <2>; + device_type = "ethernet-phy"; + }; + }; +}; + +ðernet { + status = "okay"; + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; +}; + +&flash { + status = "okay"; + /* 32MB of flash */ + reg = <0x30000000 0x03200000>; + + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x7F>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; +}; + +&ide0 { + status = "okay"; +}; + +&ide1 { + status = "okay"; +}; + +&sata { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; +}; + +&syscon { + pinctrl { + /* + * gpio0agrp cover line 0-4 + * gpio0bgrp cover line 5 + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", "gpio0bgrp"; + }; + }; + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; + pinctrl-gmii { + /* This platform use both the ethernet ports */ + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + }; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-wbd111.dts b/arch/arm/boot/dts/gemini/gemini-wbd111.dts new file mode 100644 index 000000000000..3c88c59ab481 --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-wbd111.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Wiliboard WBD-111 + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Wiliboard WBD-111"; + compatible = "wiliboard,wbd111", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-setup { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "reset"; + /* Conflict with ICE */ + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-red-l3 { + label = "wbd111:red:L3"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-green-l4 { + label = "wbd111:green:L4"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-red-l4 { + label = "wbd111:red:L4"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-greeb-l3 { + label = "wbd111:green:L3"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + status = "okay"; + /* 8MB of flash */ + reg = <0x30000000 0x00800000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0agrp cover line 0-4 + * gpio0bgrp cover line 5 + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", + "gpio0bgrp"; + }; + }; + }; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + pci@50000000 { + status = "okay"; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini-wbd222.dts b/arch/arm/boot/dts/gemini/gemini-wbd222.dts new file mode 100644 index 000000000000..ff72bbc4db3e --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini-wbd222.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Wiliboard WBD-222 + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Wiliboard WBD-222"; + compatible = "wiliboard,wbd222", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-setup { + debounce-interval = <100>; + wakeup-source; + linux,code = ; + label = "reset"; + /* Conflict with ICE */ + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-red-l3 { + label = "wbd111:red:L3"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-green-l4 { + label = "wbd111:green:L4"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-red-l4 { + label = "wbd111:red:L4"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-green-l3 { + label = "wbd111:green:L3"; + /* Conflict with TVC and extended parallel flash */ + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + + phy1: ethernet-phy@3 { + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + + soc { + flash@30000000 { + status = "okay"; + /* 8MB of flash */ + reg = <0x30000000 0x00800000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0agrp cover line 0-4 + * gpio0bgrp cover line 5 + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", + "gpio0bgrp"; + }; + }; + pinctrl-gmii { + /* This platform use both the ethernet ports */ + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + }; + }; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + pci@50000000 { + status = "okay"; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini/gemini.dtsi b/arch/arm/boot/dts/gemini/gemini.dtsi new file mode 100644 index 000000000000..befe322bd7de --- /dev/null +++ b/arch/arm/boot/dts/gemini/gemini.dtsi @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Cortina systems Gemini SoC + */ + +#include +#include +#include +#include + +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + interrupt-parent = <&intcon>; + + flash: flash@30000000 { + compatible = "cortina,gemini-flash", "cfi-flash"; + syscon = <&syscon>; + pinctrl-names = "default"; + pinctrl-0 = <&pflash_default_pins>; + bank-width = <2>; + status = "disabled"; + }; + + syscon: syscon@40000000 { + compatible = "cortina,gemini-syscon", + "syscon", "simple-mfd"; + reg = <0x40000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&syscon>; + /* GLOBAL_RESET register */ + offset = <0x0c>; + /* RESET_GLOBAL | RESET_CPU1 */ + mask = <0xC0000000>; + }; + + pinctrl { + compatible = "cortina,gemini-pinctrl"; + regmap = <&syscon>; + /* Hog the DRAM pins */ + pinctrl-names = "default"; + pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, + <&vcontrol_default_pins>; + + dram_default_pins: pinctrl-dram { + mux { + function = "dram"; + groups = "dramgrp"; + }; + }; + rtc_default_pins: pinctrl-rtc { + mux { + function = "rtc"; + groups = "rtcgrp"; + }; + }; + power_default_pins: pinctrl-power { + mux { + function = "power"; + groups = "powergrp"; + }; + }; + cir_default_pins: pinctrl-cir { + mux { + function = "cir"; + groups = "cirgrp"; + }; + }; + system_default_pins: pinctrl-system { + mux { + function = "system"; + groups = "systemgrp"; + }; + }; + vcontrol_default_pins: pinctrl-vcontrol { + mux { + function = "vcontrol"; + groups = "vcontrolgrp"; + }; + }; + ice_default_pins: pinctrl-ice { + mux { + function = "ice"; + groups = "icegrp"; + }; + }; + uart_default_pins: pinctrl-uart { + mux { + function = "uart"; + groups = "uartrxtxgrp"; + }; + }; + pflash_default_pins: pinctrl-pflash { + mux { + function = "pflash"; + groups = "pflashgrp"; + }; + }; + usb_default_pins: pinctrl-usb { + mux { + function = "usb"; + groups = "usbgrp"; + }; + }; + gmii_default_pins: pinctrl-gmii { + /* + * Only activate GMAC0 by default since + * GMAC1 will overlap with 8 GPIO lines + * gpio2a, gpio2b. Overlay groups with + * "gmii_gmac0_grp", "gmii_gmac1_grp" for + * both ethernet interfaces. + */ + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + }; + pci_default_pins: pinctrl-pci { + mux { + function = "pci"; + groups = "pcigrp"; + }; + }; + sata_default_pins: pinctrl-sata { + mux { + function = "sata"; + groups = "satagrp"; + }; + }; + /* Activate both groups of pins for this state */ + sata_and_ide_pins: pinctrl-sata-ide { + mux0 { + function = "sata"; + groups = "satagrp"; + }; + mux1 { + function = "ide"; + groups = "idegrp"; + }; + }; + tvc_default_pins: pinctrl-tvc { + mux { + function = "tvc"; + groups = "tvcgrp"; + }; + }; + }; + }; + + watchdog@41000000 { + compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; + reg = <0x41000000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_WDOG>; + clocks = <&syscon GEMINI_CLK_APB>; + clock-names = "PCLK"; + }; + + uart0: serial@42000000 { + compatible = "ns16550a"; + reg = <0x42000000 0x100>; + resets = <&syscon GEMINI_RESET_UART>; + clocks = <&syscon GEMINI_CLK_UART>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart_default_pins>; + reg-shift = <2>; + }; + + timer@43000000 { + compatible = "faraday,fttmr010"; + reg = <0x43000000 0x1000>; + interrupt-parent = <&intcon>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ + <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ + <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ + resets = <&syscon GEMINI_RESET_TIMER>; + /* APB clock or RTC clock */ + clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; + clock-names = "PCLK", "EXTCLK"; + syscon = <&syscon>; + }; + + rtc@45000000 { + compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; + reg = <0x45000000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_RTC>; + clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; + clock-names = "PCLK", "EXTCLK"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_default_pins>; + }; + + sata: sata@46000000 { + compatible = "cortina,gemini-sata-bridge"; + reg = <0x46000000 0x100>; + resets = <&syscon GEMINI_RESET_SATA0>, + <&syscon GEMINI_RESET_SATA1>; + reset-names = "sata0", "sata1"; + clocks = <&syscon GEMINI_CLK_GATE_SATA0>, + <&syscon GEMINI_CLK_GATE_SATA1>; + clock-names = "SATA0_PCLK", "SATA1_PCLK"; + /* + * This defines the special "ide" state that needs + * to be explicitly enabled to enable the IDE pins, + * as these pins are normally used for other things. + */ + pinctrl-names = "default", "ide"; + pinctrl-0 = <&sata_default_pins>; + pinctrl-1 = <&sata_and_ide_pins>; + syscon = <&syscon>; + status = "disabled"; + }; + + intcon: interrupt-controller@48000000 { + compatible = "faraday,ftintc010"; + reg = <0x48000000 0x1000>; + resets = <&syscon GEMINI_RESET_INTCON0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + power-controller@4b000000 { + compatible = "cortina,gemini-power-controller"; + reg = <0x4b000000 0x100>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&power_default_pins>; + }; + + gpio0: gpio@4d000000 { + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; + reg = <0x4d000000 0x100>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GPIO0>; + clocks = <&syscon GEMINI_CLK_APB>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@4e000000 { + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; + reg = <0x4e000000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GPIO1>; + clocks = <&syscon GEMINI_CLK_APB>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@4f000000 { + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; + reg = <0x4f000000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GPIO2>; + clocks = <&syscon GEMINI_CLK_APB>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pci@50000000 { + compatible = "cortina,gemini-pci", "faraday,ftpci100"; + /* + * The first 256 bytes in the IO range is actually used + * to configure the host bridge. + */ + reg = <0x50000000 0x100>; + resets = <&syscon GEMINI_RESET_PCI>; + clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; + clock-names = "PCLK", "PCICLK"; + pinctrl-names = "default"; + pinctrl-0 = <&pci_default_pins>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + + bus-range = <0x00 0xff>; + /* PCI ranges mappings */ + ranges = + /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + + /* DMA ranges */ + dma-ranges = + /* 128MiB at 0x00000000-0x07ffffff */ + <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, + /* 64MiB at 0x00000000-0x03ffffff */ + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, + /* 64MiB at 0x00000000-0x03ffffff */ + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; + + /* + * This PCI host bridge variant has a cascaded interrupt + * controller embedded in the host bridge. + */ + pci_intc: interrupt-controller { + interrupt-parent = <&intcon>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + ethernet: ethernet@60000000 { + compatible = "cortina,gemini-ethernet"; + reg = <0x60000000 0x4000>, /* Global registers, queue */ + <0x60004000 0x2000>, /* V-bit */ + <0x60006000 0x2000>; /* A-bit */ + pinctrl-names = "default"; + pinctrl-0 = <&gmii_default_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gmac0: ethernet-port@0 { + compatible = "cortina,gemini-ethernet-port"; + reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ + <0x6000a000 0x2000>; /* Port 0 GMAC */ + interrupt-parent = <&intcon>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GMAC0>; + clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; + clock-names = "PCLK"; + }; + + gmac1: ethernet-port@1 { + compatible = "cortina,gemini-ethernet-port"; + reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ + <0x6000e000 0x2000>; /* Port 1 GMAC */ + interrupt-parent = <&intcon>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GMAC1>; + clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; + clock-names = "PCLK"; + }; + }; + + crypto: crypto@62000000 { + compatible = "cortina,sl3516-crypto"; + reg = <0x62000000 0x10000>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_SECURITY>; + clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; + }; + + ide0: ide@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x1000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_IDE>; + clocks = <&syscon GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ide1: ide@63400000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63400000 0x1000>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_IDE>; + clocks = <&syscon GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + dma-controller@67000000 { + compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; + /* Faraday Technology FTDMAC020 variant */ + arm,primecell-periphid = <0x0003b080>; + reg = <0x67000000 0x1000>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_DMAC>; + clocks = <&syscon GEMINI_CLK_AHB>; + clock-names = "apb_pclk"; + /* Bus interface AHB1 (AHB0) is totally tilted */ + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + + display-controller@6a000000 { + compatible = "cortina,gemini-tvc", "faraday,tve200"; + reg = <0x6a000000 0x1000>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_TVC>; + clocks = <&syscon GEMINI_CLK_GATE_TVC>, + <&syscon GEMINI_CLK_TVC>; + clock-names = "PCLK", "TVE"; + pinctrl-names = "default"; + pinctrl-0 = <&tvc_default_pins>; + status = "disabled"; + }; + + usb0: usb@68000000 { + compatible = "cortina,gemini-usb", "faraday,fotg200"; + reg = <0x68000000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_USB0>; + clocks = <&syscon GEMINI_CLK_GATE_USB0>; + clock-names = "PCLK"; + /* + * This will claim pins for USB0 and USB1 at the same + * time as they are using some common pins. If you for + * some reason have a system using USB1 at 96000000 but + * NOT using USB0 at 68000000 you wll have to add the + * usb_default_pins to the USB controller at 96000000 + * in your .dts for the board. + */ + pinctrl-names = "default"; + pinctrl-0 = <&usb_default_pins>; + /* Default to host mode */ + dr_mode = "host"; + syscon = <&syscon>; + status = "disabled"; + }; + + usb1: usb@69000000 { + compatible = "cortina,gemini-usb", "faraday,fotg200"; + reg = <0x69000000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_USB1>; + clocks = <&syscon GEMINI_CLK_GATE_USB1>; + clock-names = "PCLK"; + syscon = <&syscon>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi deleted file mode 100644 index 8d77579807ec..000000000000 --- a/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach audiocamera shield expansion board - * - * Copyright (C) 2017 Jacopo Mondi - */ - -#include "r7s72100.dtsi" -#include -#include - -/ { - /* On-board camera clock. */ - camera_clk: camera_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&pinctrl { - i2c1_pins: i2c1 { - /* P1_2 as SCL; P1_3 as SDA */ - pinmux = , ; - }; - - vio_pins: vio { - /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ - pinmux = , /* VIO_VD */ - , /* VIO_HD */ - , /* VIO_D0 */ - , /* VIO_D1 */ - , /* VIO_D2 */ - , /* VIO_D3 */ - , /* VIO_D4 */ - , /* VIO_D5 */ - , /* VIO_D6 */ - , /* VIO_D7 */ - ; /* VIO_CLK */ - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - camera@48 { - compatible = "aptina,mt9v111"; - reg = <0x48>; - - clocks = <&camera_clk>; - - port { - mt9v111_out: endpoint { - remote-endpoint = <&ceu_in>; - }; - }; - }; -}; - -&ceu { - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&mt9v111_out>; - }; - }; -}; diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts deleted file mode 100644 index f473fa22e9ce..000000000000 --- a/arch/arm/boot/dts/hi3519-demb.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - */ - -/dts-v1/; -#include "hi3519.dtsi" - -/ { - model = "HiSilicon HI3519 DEMO Board"; - compatible = "hisilicon,hi3519"; - - aliases { - serial0 = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&dual_timer0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi deleted file mode 100644 index c524c854d319..000000000000 --- a/arch/arm/boot/dts/hi3519.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - */ - -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - }; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10301000 0x1000>, <0x10302000 0x1000>; - }; - - clk_3m: clk_3m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3000000>; - }; - - crg: clock-reset-controller@12010000 { - compatible = "hisilicon,hi3519-crg"; - #clock-cells = <1>; - #reset-cells = <2>; - reg = <0x12010000 0x10000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - uart0: serial@12100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12100000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>; - clock-names = "uartclk", "apb_pclk"; - status = "disable"; - }; - - uart1: serial@12101000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12101000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>; - clock-names = "uartclk", "apb_pclk"; - status = "disable"; - }; - - uart2: serial@12102000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12102000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>; - clock-names = "uartclk", "apb_pclk"; - status = "disable"; - }; - - uart3: serial@12103000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12103000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>; - clock-names = "uartclk", "apb_pclk"; - status = "disable"; - }; - - uart4: serial@12104000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12104000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>; - clock-names = "uartclk", "apb_pclk"; - status = "disable"; - }; - - dual_timer0: timer@12000000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12000000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer1: timer@12001000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12001000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer2: timer@12002000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12002000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - spi_bus0: spi@12120000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12120000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>; - clock-names = "sspclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - spi_bus1: spi@12121000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12121000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>; - clock-names = "sspclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - spi_bus2: spi@12122000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12122000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>; - clock-names = "sspclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - sysctrl: system-controller@12020000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12020000 0x1000>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&sysctrl>; - offset = <0x4>; - mask = <0xdeadbeef>; - }; - }; -}; diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts deleted file mode 100644 index f1c816a1d7cf..000000000000 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012-2013 Linaro Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; - -#include "hi3620.dtsi" - -/ { - model = "Hisilicon Hi4511 Development Board"; - compatible = "hisilicon,hi3620-hi4511"; - - chosen { - bootargs = "root=/dev/ram0"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - amba-bus { - dual_timer0: dual_timer@800000 { - status = "okay"; - }; - - uart0: serial@b00000 { /* console */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; - status = "okay"; - }; - - uart1: serial@b01000 { /* modem */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; - pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; - status = "okay"; - }; - - uart2: serial@b02000 { /* audience */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; - status = "okay"; - }; - - uart3: serial@b03000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; - status = "okay"; - }; - - uart4: serial@b04000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; - status = "okay"; - }; - - pmx0: pinmux@803000 { - pinctrl-names = "default"; - pinctrl-0 = <&board_pmx_pins>; - - board_pmx_pins: board-pins { - pinctrl-single,pins = < - 0x008 0x0 /* GPIO -- eFUSE_DOUT */ - 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ - >; - }; - uart0_pmx_func: uart0-pins { - pinctrl-single,pins = < - 0x0f0 0x0 - 0x0f4 0x0 /* UART0_RX & UART0_TX */ - >; - }; - uart0_pmx_idle: uart0-idle-pins { - pinctrl-single,pins = < - /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ - 0x0f4 0x1 /* UART0_RX & UART0_TX */ - >; - }; - uart1_pmx_func: uart1-pins { - pinctrl-single,pins = < - 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ - 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ - >; - }; - uart1_pmx_idle: uart1-idle-pins { - pinctrl-single,pins = < - 0x0f8 0x1 /* GPIO (IOMG61) */ - 0x0fc 0x1 /* GPIO (IOMG62) */ - >; - }; - uart2_pmx_func: uart2-pins { - pinctrl-single,pins = < - 0x104 0x2 /* UART2_RXD (IOMG96) */ - 0x108 0x2 /* UART2_TXD (IOMG64) */ - >; - }; - uart2_pmx_idle: uart2-idle-pins { - pinctrl-single,pins = < - 0x104 0x1 /* GPIO (IOMG96) */ - 0x108 0x1 /* GPIO (IOMG64) */ - >; - }; - uart3_pmx_func: uart3-pins { - pinctrl-single,pins = < - 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ - 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ - >; - }; - uart3_pmx_idle: uart3-idle-pins { - pinctrl-single,pins = < - 0x160 0x1 /* GPIO (IOMG85) */ - 0x164 0x1 /* GPIO (IOMG86) */ - >; - }; - uart4_pmx_func: uart4-pins { - pinctrl-single,pins = < - 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ - 0x16c 0x0 /* UART4_RXD (IOMG88) */ - 0x170 0x0 /* UART4_TXD (IOMG93) */ - >; - }; - uart4_pmx_idle: uart4-idle-pins { - pinctrl-single,pins = < - 0x168 0x1 /* GPIO (IOMG87) */ - 0x16c 0x1 /* GPIO (IOMG88) */ - 0x170 0x1 /* GPIO (IOMG93) */ - >; - }; - i2c0_pmx_func: i2c0-pins { - pinctrl-single,pins = < - 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ - >; - }; - i2c0_pmx_idle: i2c0-idle-pins { - pinctrl-single,pins = < - 0x0b4 0x1 /* GPIO (IOMG45) */ - >; - }; - i2c1_pmx_func: i2c1-pins { - pinctrl-single,pins = < - 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ - >; - }; - i2c1_pmx_idle: i2c1-idle-pins { - pinctrl-single,pins = < - 0x0b8 0x1 /* GPIO (IOMG46) */ - >; - }; - i2c2_pmx_func: i2c2-pins { - pinctrl-single,pins = < - 0x068 0x0 /* I2C2_SCL (IOMG26) */ - 0x06c 0x0 /* I2C2_SDA (IOMG27) */ - >; - }; - i2c2_pmx_idle: i2c2-idle-pins { - pinctrl-single,pins = < - 0x068 0x1 /* GPIO (IOMG26) */ - 0x06c 0x1 /* GPIO (IOMG27) */ - >; - }; - i2c3_pmx_func: i2c3-pins { - pinctrl-single,pins = < - 0x050 0x2 /* I2C3_SCL (IOMG20) */ - 0x054 0x2 /* I2C3_SDA (IOMG21) */ - >; - }; - i2c3_pmx_idle: i2c3-idle-pins { - pinctrl-single,pins = < - 0x050 0x1 /* GPIO (IOMG20) */ - 0x054 0x1 /* GPIO (IOMG21) */ - >; - }; - spi0_pmx_func: spi0-pins { - pinctrl-single,pins = < - 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ - 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ - 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ - 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ - 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ - >; - }; - spi0_pmx_idle: spi0-idle-pins { - pinctrl-single,pins = < - 0x0d4 0x1 /* GPIO (IOMG53) */ - 0x0d8 0x1 /* GPIO (IOMG54) */ - 0x0dc 0x1 /* GPIO (IOMG55) */ - 0x0e0 0x1 /* GPIO (IOMG56) */ - 0x0e4 0x1 /* GPIO (IOMG57) */ - >; - }; - spi1_pmx_func: spi1-pins { - pinctrl-single,pins = < - 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ - 0x0e8 0x0 /* SPI1_DO (IOMG58) */ - 0x0ec 0x0 /* SPI1_CS (IOMG95) */ - >; - }; - spi1_pmx_idle: spi1-idle-pins { - pinctrl-single,pins = < - 0x184 0x1 /* GPIO (IOMG98) */ - 0x0e8 0x1 /* GPIO (IOMG58) */ - 0x0ec 0x1 /* GPIO (IOMG95) */ - >; - }; - kpc_pmx_func: kpc-pins { - pinctrl-single,pins = < - 0x12c 0x0 /* KEY_IN0 (IOMG73) */ - 0x130 0x0 /* KEY_IN1 (IOMG74) */ - 0x134 0x0 /* KEY_IN2 (IOMG75) */ - 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ - 0x110 0x0 /* KEY_OUT1 (IOMG66) */ - 0x114 0x0 /* KEY_OUT2 (IOMG67) */ - >; - }; - kpc_pmx_idle: kpc-idle-pins { - pinctrl-single,pins = < - 0x12c 0x1 /* GPIO (IOMG73) */ - 0x130 0x1 /* GPIO (IOMG74) */ - 0x134 0x1 /* GPIO (IOMG75) */ - 0x10c 0x1 /* GPIO (IOMG65) */ - 0x110 0x1 /* GPIO (IOMG66) */ - 0x114 0x1 /* GPIO (IOMG67) */ - >; - }; - gpio_key_func: gpio-key-pins { - pinctrl-single,pins = < - 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ - 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ - >; - }; - emmc_pmx_func: emmc-pins { - pinctrl-single,pins = < - 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ - 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ - >; - }; - emmc_pmx_idle: emmc-idle-pins { - pinctrl-single,pins = < - 0x030 0x0 /* GPIO (IOMG12) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ - 0x02c 0x1 /* GPIO (IOMG10) */ - >; - }; - sd_pmx_func: sd-pins { - pinctrl-single,pins = < - 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ - 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ - >; - }; - sd_pmx_idle: sd-idle-pins { - pinctrl-single,pins = < - 0x0bc 0x1 /* GPIO (IOMG47) */ - 0x0c0 0x1 /* GPIO (IOMG48) */ - >; - }; - nand_pmx_func: nand-pins { - pinctrl-single,pins = < - 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ - 0x010 0x0 /* NAND_CS1_N (IOMG4) */ - 0x014 0x0 /* NAND_CS2_N (IOMG5) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ - 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ - 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ - >; - }; - nand_pmx_idle: nand-idle-pins { - pinctrl-single,pins = < - 0x00c 0x1 /* GPIO (IOMG3) */ - 0x010 0x1 /* GPIO (IOMG4) */ - 0x014 0x1 /* GPIO (IOMG5) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x01c 0x1 /* GPIO (IOMG94) */ - 0x020 0x1 /* GPIO (IOMG7) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ - 0x02c 0x1 /* GPIO (IOMG10) */ - >; - }; - sdio_pmx_func: sdio-pins { - pinctrl-single,pins = < - 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ - >; - }; - sdio_pmx_idle: sdio-idle-pins { - pinctrl-single,pins = < - 0x0c4 0x1 /* GPIO (IOMG49) */ - >; - }; - audio_out_pmx_func: audio-out-pins { - pinctrl-single,pins = < - 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ - >; - }; - }; - - pmx1: pinmux@803800 { - pinctrl-names = "default"; - pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins - &board_np_pins &board_ps_pins &kpc_cfg_func - &audio_out_cfg_func>; - board_pu_pins: board-pu-pins { - pinctrl-single,pins = < - 0x014 0 /* GPIO_158 (IOCFG2) */ - 0x018 0 /* GPIO_159 (IOCFG3) */ - 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ - 0x020 0 /* BOOT_MODE1 (IOCFG5) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - }; - board_pd_pins: board-pd-pins { - pinctrl-single,pins = < - 0x038 0 /* eFUSE_DOUT (IOCFG11) */ - 0x150 0 /* ISP_GPIO8 (IOCFG93) */ - 0x154 0 /* ISP_GPIO9 (IOCFG94) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - board_pd_ps_pins: board-pd-ps-pins { - pinctrl-single,pins = < - 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ - 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - board_np_pins: board-np-pins { - pinctrl-single,pins = < - 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - board_ps_pins: board-ps-pins { - pinctrl-single,pins = < - 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ - 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ - >; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - uart0_cfg_func: uart0-cfg-pins { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart0_cfg_idle: uart0-cfg-idle-pins { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart1_cfg_func: uart1-cfg-pins { - pinctrl-single,pins = < - 0x210 0 /* UART1_CTS (IOCFG140) */ - 0x214 0 /* UART1_RTS (IOCFG141) */ - 0x218 0 /* UART1_RXD (IOCFG142) */ - 0x21c 0 /* UART1_TXD (IOCFG143) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart1_cfg_idle: uart1-cfg-idle-pins { - pinctrl-single,pins = < - 0x210 0 /* UART1_CTS (IOCFG140) */ - 0x214 0 /* UART1_RTS (IOCFG141) */ - 0x218 0 /* UART1_RXD (IOCFG142) */ - 0x21c 0 /* UART1_TXD (IOCFG143) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart2_cfg_func: uart2-cfg-pins { - pinctrl-single,pins = < - 0x220 0 /* UART2_CTS (IOCFG144) */ - 0x224 0 /* UART2_RTS (IOCFG145) */ - 0x228 0 /* UART2_RXD (IOCFG146) */ - 0x22c 0 /* UART2_TXD (IOCFG147) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart2_cfg_idle: uart2-cfg-idle-pins { - pinctrl-single,pins = < - 0x220 0 /* GPIO (IOCFG144) */ - 0x224 0 /* GPIO (IOCFG145) */ - 0x228 0 /* GPIO (IOCFG146) */ - 0x22c 0 /* GPIO (IOCFG147) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart3_cfg_func: uart3-cfg-pins { - pinctrl-single,pins = < - 0x294 0 /* UART3_CTS (IOCFG173) */ - 0x298 0 /* UART3_RTS (IOCFG174) */ - 0x29c 0 /* UART3_RXD (IOCFG175) */ - 0x2a0 0 /* UART3_TXD (IOCFG176) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart3_cfg_idle: uart3-cfg-idle-pins { - pinctrl-single,pins = < - 0x294 0 /* UART3_CTS (IOCFG173) */ - 0x298 0 /* UART3_RTS (IOCFG174) */ - 0x29c 0 /* UART3_RXD (IOCFG175) */ - 0x2a0 0 /* UART3_TXD (IOCFG176) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart4_cfg_func: uart4-cfg-pins { - pinctrl-single,pins = < - 0x2a4 0 /* UART4_CTS (IOCFG177) */ - 0x2a8 0 /* UART4_RTS (IOCFG178) */ - 0x2ac 0 /* UART4_RXD (IOCFG179) */ - 0x2b0 0 /* UART4_TXD (IOCFG180) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - i2c0_cfg_func: i2c0-cfg-pins { - pinctrl-single,pins = < - 0x17c 0 /* I2C0_SCL (IOCFG103) */ - 0x180 0 /* I2C0_SDA (IOCFG104) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c1_cfg_func: i2c1-cfg-pins { - pinctrl-single,pins = < - 0x184 0 /* I2C1_SCL (IOCFG105) */ - 0x188 0 /* I2C1_SDA (IOCFG106) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c2_cfg_func: i2c2-cfg-pins { - pinctrl-single,pins = < - 0x118 0 /* I2C2_SCL (IOCFG79) */ - 0x11c 0 /* I2C2_SDA (IOCFG80) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c3_cfg_func: i2c3-cfg-pins { - pinctrl-single,pins = < - 0x100 0 /* I2C3_SCL (IOCFG73) */ - 0x104 0 /* I2C3_SDA (IOCFG74) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi0_cfg_func1: spi0-cfg-func1-pins { - pinctrl-single,pins = < - 0x1d4 0 /* SPI0_CLK (IOCFG125) */ - 0x1d8 0 /* SPI0_DI (IOCFG126) */ - 0x1dc 0 /* SPI0_DO (IOCFG127) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi0_cfg_func2: spi0-cfg-func2-pins { - pinctrl-single,pins = < - 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ - 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ - 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ - 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi1_cfg_func1: spi1-cfg-func1-pins { - pinctrl-single,pins = < - 0x1f0 0 /* SPI1_CLK (IOCFG132) */ - 0x1f4 0 /* SPI1_DI (IOCFG133) */ - 0x1f8 0 /* SPI1_DO (IOCFG134) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi1_cfg_func2: spi1-cfg-func2-pins { - pinctrl-single,pins = < - 0x1fc 0 /* SPI1_CS (IOCFG135) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - kpc_cfg_func: kpc-cfg-pins { - pinctrl-single,pins = < - 0x250 0 /* KEY_IN0 (IOCFG156) */ - 0x254 0 /* KEY_IN1 (IOCFG157) */ - 0x258 0 /* KEY_IN2 (IOCFG158) */ - 0x230 0 /* KEY_OUT0 (IOCFG148) */ - 0x234 0 /* KEY_OUT1 (IOCFG149) */ - 0x238 0 /* KEY_OUT2 (IOCFG150) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - emmc_cfg_func: emmc-cfg-pins { - pinctrl-single,pins = < - 0x0ac 0 /* eMMC_CMD (IOCFG40) */ - 0x0b0 0 /* eMMC_CLK (IOCFG41) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ - 0x08c 0 /* NAND_DATA8 (IOCFG32) */ - 0x090 0 /* NAND_DATA9 (IOCFG33) */ - 0x094 0 /* NAND_DATA10 (IOCFG34) */ - 0x098 0 /* NAND_DATA11 (IOCFG35) */ - 0x09c 0 /* NAND_DATA12 (IOCFG36) */ - 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ - 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ - 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sd_cfg_func1: sd-cfg-func1-pins { - pinctrl-single,pins = < - 0x18c 0 /* SD_CLK (IOCFG107) */ - 0x190 0 /* SD_CMD (IOCFG108) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sd_cfg_func2: sd-cfg-func2-pins { - pinctrl-single,pins = < - 0x194 0 /* SD_DATA0 (IOCFG109) */ - 0x198 0 /* SD_DATA1 (IOCFG110) */ - 0x19c 0 /* SD_DATA2 (IOCFG111) */ - 0x1a0 0 /* SD_DATA3 (IOCFG112) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x70 0xf0>; - }; - nand_cfg_func1: nand-cfg-func1-pins { - pinctrl-single,pins = < - 0x03c 0 /* NAND_ALE (IOCFG12) */ - 0x040 0 /* NAND_CLE (IOCFG13) */ - 0x06c 0 /* NAND_DATA0 (IOCFG24) */ - 0x070 0 /* NAND_DATA1 (IOCFG25) */ - 0x074 0 /* NAND_DATA2 (IOCFG26) */ - 0x078 0 /* NAND_DATA3 (IOCFG27) */ - 0x07c 0 /* NAND_DATA4 (IOCFG28) */ - 0x080 0 /* NAND_DATA5 (IOCFG29) */ - 0x084 0 /* NAND_DATA6 (IOCFG30) */ - 0x088 0 /* NAND_DATA7 (IOCFG31) */ - 0x08c 0 /* NAND_DATA8 (IOCFG32) */ - 0x090 0 /* NAND_DATA9 (IOCFG33) */ - 0x094 0 /* NAND_DATA10 (IOCFG34) */ - 0x098 0 /* NAND_DATA11 (IOCFG35) */ - 0x09c 0 /* NAND_DATA12 (IOCFG36) */ - 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ - 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ - 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - nand_cfg_func2: nand-cfg-func2-pins { - pinctrl-single,pins = < - 0x044 0 /* NAND_RE_N (IOCFG14) */ - 0x048 0 /* NAND_WE_N (IOCFG15) */ - 0x04c 0 /* NAND_CS0_N (IOCFG16) */ - 0x050 0 /* NAND_CS1_N (IOCFG17) */ - 0x054 0 /* NAND_CS2_N (IOCFG18) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ - 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sdio_cfg_func: sdio-cfg-pins { - pinctrl-single,pins = < - 0x1a4 0 /* SDIO0_CLK (IOCG113) */ - 0x1a8 0 /* SDIO0_CMD (IOCG114) */ - 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ - 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ - 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ - 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - audio_out_cfg_func: audio-out-cfg-pins { - pinctrl-single,pins = < - 0x200 0 /* GPIO (IOCFG136) */ - 0x204 0 /* GPIO (IOCFG137) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - call { - label = "call"; - gpios = <&gpio17 2 0>; - linux,code = <169>; /* KEY_PHONE */ - }; - }; -}; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi deleted file mode 100644 index a254ec009296..000000000000 --- a/arch/arm/boot/dts/hi3620.dtsi +++ /dev/null @@ -1,575 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * HiSilicon Ltd. Hi3620 SoC - * - * Copyright (C) 2012-2013 HiSilicon Ltd. - * Copyright (C) 2012-2013 Linaro Ltd. - * - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - pclk: clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "apb_pclk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hi3620-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - amba-bus { - - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0xfc000000 0x2000000>; - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0x100000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0x1000 0x1000>, <0x100 0x100>; - }; - - sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl", "syscon"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x802000 0x1000>; - reg = <0x802000 0x1000>; - - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - - clock: clock@0 { - compatible = "hisilicon,hi3620-clock"; - reg = <0 0x10000>; - #clock-cells = <1>; - }; - }; - - dual_timer0: dual_timer@800000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x800000 0x1000>; - /* timer00 & timer01 */ - interrupts = <0 0 4>, <0 1 4>; - clocks = <&clock HI3620_TIMER0_MUX>, - <&clock HI3620_TIMER1_MUX>, - <&clock HI3620_TIMER0_MUX>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - dual_timer1: dual_timer@801000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x801000 0x1000>; - /* timer10 & timer11 */ - interrupts = <0 2 4>, <0 3 4>; - clocks = <&clock HI3620_TIMER2_MUX>, - <&clock HI3620_TIMER3_MUX>, - <&clock HI3620_TIMER2_MUX>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - dual_timer2: dual_timer@a01000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa01000 0x1000>; - /* timer20 & timer21 */ - interrupts = <0 4 4>, <0 5 4>; - clocks = <&clock HI3620_TIMER4_MUX>, - <&clock HI3620_TIMER5_MUX>, - <&clock HI3620_TIMER4_MUX>; - clock-names = "timer0lck", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - dual_timer3: dual_timer@a02000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa02000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 6 4>, <0 7 4>; - clocks = <&clock HI3620_TIMER6_MUX>, - <&clock HI3620_TIMER7_MUX>, - <&clock HI3620_TIMER6_MUX>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - dual_timer4: dual_timer@a03000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa03000 0x1000>; - /* timer40 & timer41 */ - interrupts = <0 96 4>, <0 97 4>; - clocks = <&clock HI3620_TIMER8_MUX>, - <&clock HI3620_TIMER9_MUX>, - <&clock HI3620_TIMER8_MUX>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - timer5: timer@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x20>; - interrupts = <1 13 0xf01>; - }; - - uart0: serial@b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb00000 0x1000>; - interrupts = <0 20 4>; - clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart1: serial@b01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb01000 0x1000>; - interrupts = <0 21 4>; - clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb02000 0x1000>; - interrupts = <0 22 4>; - clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart3: serial@b03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb03000 0x1000>; - interrupts = <0 23 4>; - clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart4: serial@b04000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb04000 0x1000>; - interrupts = <0 24 4>; - clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - gpio0: gpio@806000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x806000 0x1000>; - interrupts = <0 64 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 - &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@807000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x807000 0x1000>; - interrupts = <0 65 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 - &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 - &pmx0 6 5 1 &pmx0 7 6 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@808000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x808000 0x1000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 - &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 - &pmx0 6 3 1 &pmx0 7 3 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@809000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x809000 0x1000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 - &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 - &pmx0 6 11 1 &pmx0 7 11 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@80a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80a000 0x1000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 - &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 - &pmx0 6 13 1 &pmx0 7 13 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@80b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80b000 0x1000>; - interrupts = <0 69 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 - &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 - &pmx0 6 16 1 &pmx0 7 16 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@80c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80c000 0x1000>; - interrupts = <0 70 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 - &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 - &pmx0 6 18 1 &pmx0 7 19 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@80d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80d000 0x1000>; - interrupts = <0 71 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 - &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 - &pmx0 6 25 1 &pmx0 7 26 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@80e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80e000 0x1000>; - interrupts = <0 72 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 - &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 - &pmx0 6 33 1 &pmx0 7 34 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@80f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80f000 0x1000>; - interrupts = <0 73 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 - &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 - &pmx0 6 41 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@810000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x810000 0x1000>; - interrupts = <0 74 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 - &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@811000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x811000 0x1000>; - interrupts = <0 75 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 - &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 - &pmx0 6 49 1 &pmx0 7 49 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@812000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x812000 0x1000>; - interrupts = <0 76 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 - &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 - &pmx0 6 51 1 &pmx0 7 52 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@813000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x813000 0x1000>; - interrupts = <0 77 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 - &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 - &pmx0 6 55 1 &pmx0 7 56 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@814000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x814000 0x1000>; - interrupts = <0 78 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 - &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 - &pmx0 6 60 1 &pmx0 7 61 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@815000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x815000 0x1000>; - interrupts = <0 79 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 - &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 - &pmx0 6 64 1 &pmx0 7 65 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@816000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x816000 0x1000>; - interrupts = <0 80 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 - &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 - &pmx0 6 72 1 &pmx0 7 73 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@817000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x817000 0x1000>; - interrupts = <0 81 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 - &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 - &pmx0 6 80 1 &pmx0 7 81 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@818000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x818000 0x1000>; - interrupts = <0 82 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 - &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 - &pmx0 6 86 1 &pmx0 7 87 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@819000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x819000 0x1000>; - interrupts = <0 83 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 - &pmx0 3 88 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@81a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x81a000 0x1000>; - interrupts = <0 84 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 - &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@81b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x81b000 0x1000>; - interrupts = <0 85 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK21>; - clock-names = "apb_pclk"; - }; - - pmx0: pinmux@803000 { - compatible = "pinctrl-single"; - reg = <0x803000 0x188>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #gpio-range-cells = <3>; - - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 - &range 12 1 0 &range 13 29 1 - &range 43 1 0 &range 44 49 1 - &range 94 1 1 &range 96 2 1>; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - pmx1: pinmux@803800 { - compatible = "pinconf-single"; - reg = <0x803800 0x2dc>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - - pinctrl-single,register-width = <32>; - }; - }; -}; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts deleted file mode 100644 index b6b0225a769e..000000000000 --- a/arch/arm/boot/dts/highbank.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda Highbank"; - compatible = "calxeda,highbank"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@900 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x900>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@901 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x901>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@902 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x902>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@903 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x903>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0xff900000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0xffffffff>; - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - timer@fff10600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfff10600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&a9periphclk>; - }; - - watchdog@fff10620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xfff10620 0x20>; - interrupts = <1 14 0xf01>; - clocks = <&a9periphclk>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfff11000 0x1000>, - <0xfff10100 0x100>; - }; - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - interrupts = <0 70 4>; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; - }; - - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4>, <0 72 4>; - }; - - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts deleted file mode 100644 index f3faf247cd61..000000000000 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * HiSilicon Ltd. HiP01 SoC - * - * Copyright (C) 2014 HiSilicon Ltd. - * Copyright (C) 2014 Huawei Ltd. - * - * Author: Wang Long - */ - -/dts-v1/; - -/* First 8KB reserved for secondary core boot */ -/memreserve/ 0x80000000 0x00002000; - -#include "hip01.dtsi" - -/ { - model = "Hisilicon HIP01 Development Board"; - compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hip01-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi deleted file mode 100644 index e17f36bd9006..000000000000 --- a/arch/arm/boot/dts/hip01.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * HiSilicon Ltd. HiP01 SoC - * - * Copyright (c) 2014 HiSilicon Ltd. - * Copyright (c) 2014 Huawei Ltd. - * - * Author: Wang Long - */ - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; - }; - - hisi_refclk144mhz: refclk144mkhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <144000000>; - clock-output-names = "hisi:refclk144khz"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0x10000000 0x20000000>; - - amba-bus { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - uart0: serial@10001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - interrupts = <0 32 4>; - status = "disabled"; - }; - - uart1: serial@10002000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - interrupts = <0 33 4>; - status = "disabled"; - }; - - uart2: serial@10003000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - interrupts = <0 34 4>; - status = "disabled"; - }; - - uart3: serial@10006000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - interrupts = <0 4 4>; - status = "disabled"; - }; - }; - - system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - - global_timer@a000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x0a000200 0x100>; - interrupts = <1 11 0xf04>; - clocks = <&hisi_refclk144mhz>; - }; - - local_timer@a000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0a000600 0x100>; - interrupts = <1 13 0xf04>; - clocks = <&hisi_refclk144mhz>; - }; - }; -}; diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts deleted file mode 100644 index 0210064bf6a5..000000000000 --- a/arch/arm/boot/dts/hip04-d01.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013-2014 Linaro Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; - -#include "hip04.dtsi" - -/ { - /* memory bus is 64-bit */ - #address-cells = <2>; - #size-cells = <2>; - model = "Hisilicon D01 Development Board"; - compatible = "hisilicon,hip04-d01"; - - memory@0,10000000 { - device_type = "memory"; - reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, - <0x00000004 0xc0000000 0x00000003 0x40000000>; - }; - - soc { - uart0: serial@4007000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi deleted file mode 100644 index 2424cc545c9c..000000000000 --- a/arch/arm/boot/dts/hip04.dtsi +++ /dev/null @@ -1,986 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * HiSilicon Ltd. HiP04 SoC - * - * Copyright (C) 2013-2014 HiSilicon Ltd. - * Copyright (C) 2013-2014 Linaro Ltd. - * - * Author: Haojian Zhuang - */ - -/ { - /* memory bus is 64-bit */ - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - }; - - bootwrapper { - compatible = "hisilicon,hip04-bootwrapper"; - boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - cluster2 { - core0 { - cpu = <&CPU8>; - }; - core1 { - cpu = <&CPU9>; - }; - core2 { - cpu = <&CPU10>; - }; - core3 { - cpu = <&CPU11>; - }; - }; - cluster3 { - core0 { - cpu = <&CPU12>; - }; - core1 { - cpu = <&CPU13>; - }; - core2 { - cpu = <&CPU14>; - }; - core3 { - cpu = <&CPU15>; - }; - }; - }; - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x102>; - }; - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x103>; - }; - CPU8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x200>; - }; - CPU9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x201>; - }; - CPU10: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x202>; - }; - CPU11: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x203>; - }; - CPU12: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x300>; - }; - CPU13: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x301>; - }; - CPU14: cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x302>; - }; - CPU15: cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x303>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - clk_50m: clk_50m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - clk_168m: clk_168m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_375m: clk_375m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <375000000>; - }; - - soc { - /* It's a 32-bit SoC. */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0 0xe0000000 0x10000000>; - - gic: interrupt-controller@c01000 { - compatible = "hisilicon,hip04-intc"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - interrupts = <1 9 0xf04>; - - reg = <0xc01000 0x1000>, <0xc02000 0x1000>, - <0xc04000 0x2000>, <0xc06000 0x2000>; - }; - - sysctrl: sysctrl { - compatible = "hisilicon,sysctrl", "syscon"; - reg = <0x3e00000 0x00100000>; - }; - - fabric: fabric { - compatible = "hisilicon,hip04-fabric"; - reg = <0x302a000 0x1000>; - }; - - dual_timer0: dual_timer@3000000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x3000000 0x1000>; - interrupts = <0 224 4>; - clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - }; - - arm-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 64 4>, - <0 65 4>, - <0 66 4>, - <0 67 4>, - <0 68 4>, - <0 69 4>, - <0 70 4>, - <0 71 4>, - <0 72 4>, - <0 73 4>, - <0 74 4>, - <0 75 4>, - <0 76 4>, - <0 77 4>, - <0 78 4>, - <0 79 4>; - }; - - uart0: serial@4007000 { - compatible = "snps,dw-apb-uart"; - reg = <0x4007000 0x1000>; - interrupts = <0 381 4>; - clocks = <&clk_168m>, <&clk_168m>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - status = "disabled"; - }; - - sata0: sata@a000000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0xa000000 0x1000000>; - interrupts = <0 372 4>; - }; - - }; - - etb@0,e3c42000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3c42000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb0_in_port: endpoint@0 { - remote-endpoint = <&replicator0_out_port0>; - }; - }; - }; - }; - - etb@0,e3c82000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3c82000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb1_in_port: endpoint@0 { - remote-endpoint = <&replicator1_out_port0>; - }; - }; - }; - }; - - etb@0,e3cc2000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3cc2000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb2_in_port: endpoint@0 { - remote-endpoint = <&replicator2_out_port0>; - }; - }; - }; - }; - - etb@0,e3d02000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3d02000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb3_in_port: endpoint@0 { - remote-endpoint = <&replicator3_out_port0>; - }; - }; - }; - }; - - tpiu@0,e3c05000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xe3c05000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint@0 { - remote-endpoint = <&funnel4_out_port0>; - }; - }; - }; - }; - - replicator0 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator0_out_port0: endpoint { - remote-endpoint = <&etb0_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator0_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port0>; - }; - }; - }; - - in-ports { - port { - replicator0_in_port0: endpoint { - remote-endpoint = <&funnel0_out_port0>; - }; - }; - }; - }; - - replicator1 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator1_out_port0: endpoint { - remote-endpoint = <&etb1_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator1_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port1>; - }; - }; - }; - - in-ports { - port { - replicator1_in_port0: endpoint { - remote-endpoint = <&funnel1_out_port0>; - }; - }; - }; - }; - - replicator2 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator2_out_port0: endpoint { - remote-endpoint = <&etb2_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator2_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port2>; - }; - }; - }; - - in-ports { - port { - replicator2_in_port0: endpoint { - remote-endpoint = <&funnel2_out_port0>; - }; - }; - }; - }; - - replicator3 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator3_out_port0: endpoint { - remote-endpoint = <&etb3_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator3_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port3>; - }; - }; - }; - - in-ports { - port { - replicator3_in_port0: endpoint { - remote-endpoint = <&funnel3_out_port0>; - }; - }; - }; - }; - - funnel@0,e3c41000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3c41000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel0_out_port0: endpoint { - remote-endpoint = - <&replicator0_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel0_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel0_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel0_in_port2: endpoint { - remote-endpoint = <&ptm2_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel0_in_port3: endpoint { - remote-endpoint = <&ptm3_out_port>; - }; - }; - }; - }; - - funnel@0,e3c81000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3c81000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel1_out_port0: endpoint { - remote-endpoint = - <&replicator1_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel1_in_port0: endpoint { - remote-endpoint = <&ptm4_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel1_in_port1: endpoint { - remote-endpoint = <&ptm5_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel1_in_port2: endpoint { - remote-endpoint = <&ptm6_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel1_in_port3: endpoint { - remote-endpoint = <&ptm7_out_port>; - }; - }; - }; - }; - - funnel@0,e3cc1000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3cc1000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel2_out_port0: endpoint { - remote-endpoint = - <&replicator2_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel2_in_port0: endpoint { - remote-endpoint = <&ptm8_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel2_in_port1: endpoint { - remote-endpoint = <&ptm9_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel2_in_port2: endpoint { - remote-endpoint = <&ptm10_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel2_in_port3: endpoint { - remote-endpoint = <&ptm11_out_port>; - }; - }; - }; - }; - - funnel@0,e3d01000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3d01000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel3_out_port0: endpoint { - remote-endpoint = - <&replicator3_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel3_in_port0: endpoint { - remote-endpoint = <&ptm12_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel3_in_port1: endpoint { - remote-endpoint = <&ptm13_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel3_in_port2: endpoint { - remote-endpoint = <&ptm14_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel3_in_port3: endpoint { - remote-endpoint = <&ptm15_out_port>; - }; - }; - }; - }; - - funnel@0,e3c04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3c04000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel4_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel4_in_port0: endpoint { - remote-endpoint = - <&replicator0_out_port1>; - }; - }; - - port@1 { - reg = <1>; - funnel4_in_port1: endpoint { - remote-endpoint = - <&replicator1_out_port1>; - }; - }; - - port@2 { - reg = <2>; - funnel4_in_port2: endpoint { - remote-endpoint = - <&replicator2_out_port1>; - }; - }; - - port@3 { - reg = <3>; - funnel4_in_port3: endpoint { - remote-endpoint = - <&replicator3_out_port1>; - }; - }; - }; - }; - - ptm@0,e3c7c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7c000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel0_in_port0>; - }; - }; - }; - }; - - ptm@0,e3c7d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7d000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel0_in_port1>; - }; - }; - }; - }; - - ptm@0,e3c7e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7e000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; - out-ports { - port { - ptm2_out_port: endpoint { - remote-endpoint = <&funnel0_in_port2>; - }; - }; - }; - }; - - ptm@0,e3c7f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7f000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; - out-ports { - port { - ptm3_out_port: endpoint { - remote-endpoint = <&funnel0_in_port3>; - }; - }; - }; - }; - - ptm@0,e3cbc000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbc000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU4>; - out-ports { - port { - ptm4_out_port: endpoint { - remote-endpoint = <&funnel1_in_port0>; - }; - }; - }; - }; - - ptm@0,e3cbd000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbd000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU5>; - out-ports { - port { - ptm5_out_port: endpoint { - remote-endpoint = <&funnel1_in_port1>; - }; - }; - }; - }; - - ptm@0,e3cbe000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbe000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU6>; - out-ports { - port { - ptm6_out_port: endpoint { - remote-endpoint = <&funnel1_in_port2>; - }; - }; - }; - }; - - ptm@0,e3cbf000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbf000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU7>; - out-ports { - port { - ptm7_out_port: endpoint { - remote-endpoint = <&funnel1_in_port3>; - }; - }; - }; - }; - - ptm@0,e3cfc000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfc000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU8>; - out-ports { - port { - ptm8_out_port: endpoint { - remote-endpoint = <&funnel2_in_port0>; - }; - }; - }; - }; - - ptm@0,e3cfd000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfd000 0 0x1000>; - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU9>; - out-ports { - port { - ptm9_out_port: endpoint { - remote-endpoint = <&funnel2_in_port1>; - }; - }; - }; - }; - - ptm@0,e3cfe000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfe000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU10>; - out-ports { - port { - ptm10_out_port: endpoint { - remote-endpoint = <&funnel2_in_port2>; - }; - }; - }; - }; - - ptm@0,e3cff000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cff000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU11>; - out-ports { - port { - ptm11_out_port: endpoint { - remote-endpoint = <&funnel2_in_port3>; - }; - }; - }; - }; - - ptm@0,e3d3c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3c000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU12>; - out-ports { - port { - ptm12_out_port: endpoint { - remote-endpoint = <&funnel3_in_port0>; - }; - }; - }; - }; - - ptm@0,e3d3d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3d000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU13>; - out-ports { - port { - ptm13_out_port: endpoint { - remote-endpoint = <&funnel3_in_port1>; - }; - }; - }; - }; - - ptm@0,e3d3e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3e000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU14>; - out-ports { - port { - ptm14_out_port: endpoint { - remote-endpoint = <&funnel3_in_port2>; - }; - }; - }; - }; - - ptm@0,e3d3f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3f000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU15>; - out-ports { - port { - ptm15_out_port: endpoint { - remote-endpoint = <&funnel3_in_port3>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts deleted file mode 100644 index 7758c19038f0..000000000000 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 HiSilicon Limited. - */ - -/dts-v1/; -#include "hisi-x5hd2.dtsi" - -/ { - model = "Hisilicon HIX5HD2 Development Board"; - compatible = "hisilicon,hix5hd2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hix5hd2-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&gmac0 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy2>; - phy-mode = "mii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy2: ethernet-phy@2 { - reg = <2>; - }; -}; - -&gmac1 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ahci { - phys = <&sata_phy>; - phy-names = "sata-phy"; -}; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi deleted file mode 100644 index dc991ba2a9fb..000000000000 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 HiSilicon Limited. - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - }; - - gic: interrupt-controller@f8a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0xf8000000 0x8000000>; - - amba-bus { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - timer0: timer@2000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00002000 0x1000>; - /* timer00 & timer01 */ - interrupts = <0 24 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer1: timer@a29000 { - /* - * Only used in NORMAL state, not available ins - * SLOW or DOZE state. - * The rate is fixed in 24MHz. - */ - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a29000 0x1000>; - /* timer10 & timer11 */ - interrupts = <0 25 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer2: timer@a2a000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a2a000 0x1000>; - /* timer20 & timer21 */ - interrupts = <0 26 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer3: timer@a2b000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a2b000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 27 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer4: timer@a81000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a81000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 28 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - uart0: serial@b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b00000 0x1000>; - interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart1: serial@6000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00006000 0x1000>; - interrupts = <0 50 4>; - clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b02000 0x1000>; - interrupts = <0 51 4>; - clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart3: serial@b03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b03000 0x1000>; - interrupts = <0 52 4>; - clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - uart4: serial@b04000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb04000 0x1000>; - interrupts = <0 53 4>; - clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - gpio0: gpio@b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb20000 0x1000>; - interrupts = <0 108 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb21000 0x1000>; - interrupts = <0 109 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio2: gpio@b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb22000 0x1000>; - interrupts = <0 110 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio3: gpio@b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb23000 0x1000>; - interrupts = <0 111 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio4: gpio@b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb24000 0x1000>; - interrupts = <0 112 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio5: gpio@4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x004000 0x1000>; - interrupts = <0 113 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio6: gpio@b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb26000 0x1000>; - interrupts = <0 114 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio7: gpio@b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb27000 0x1000>; - interrupts = <0 115 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio8: gpio@b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb28000 0x1000>; - interrupts = <0 116 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio9: gpio@b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb29000 0x1000>; - interrupts = <0 117 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio10: gpio@b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2a000 0x1000>; - interrupts = <0 118 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio11: gpio@b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2b000 0x1000>; - interrupts = <0 119 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio12: gpio@b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2c000 0x1000>; - interrupts = <0 120 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio13: gpio@b2d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2d000 0x1000>; - interrupts = <0 121 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio14: gpio@b2e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2e000 0x1000>; - interrupts = <0 122 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio15: gpio@b2f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2f000 0x1000>; - interrupts = <0 123 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio16: gpio@b30000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb30000 0x1000>; - interrupts = <0 124 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio17: gpio@b31000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb31000 0x1000>; - interrupts = <0 125 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - wdt0: watchdog@a2c000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0xa2c000 0x1000>; - interrupts = <0 29 4>; - clocks = <&clock HIX5HD2_WDG0_RST>, - <&clock HIX5HD2_WDG0_RST>; - clock-names = "wdog_clk", "apb_pclk"; - }; - }; - - local_timer@a00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x00a00600 0x20>; - interrupts = <1 13 0xf01>; - }; - - l2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0x00a10000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - }; - - sysctrl: system-controller@0 { - compatible = "hisilicon,sysctrl", "syscon"; - reg = <0x00000000 0x1000>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&sysctrl>; - offset = <0x4>; - mask = <0xdeadbeef>; - }; - - cpuctrl@a22000 { - compatible = "hisilicon,cpuctrl"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00a22000 0x2000>; - ranges = <0 0x00a22000 0x2000>; - - clock: clock@0 { - compatible = "hisilicon,hix5hd2-clock"; - reg = <0 0x2000>; - #clock-cells = <1>; - }; - }; - - /* unremovable emmc as mmcblk0 */ - mmc: mmc@1830000 { - compatible = "snps,dw-mshc"; - reg = <0x1830000 0x1000>; - interrupts = <0 35 4>; - clocks = <&clock HIX5HD2_MMC_CIU_RST>, - <&clock HIX5HD2_MMC_BIU_CLK>; - clock-names = "biu", "ciu"; - }; - - sd: mmc@1820000 { - compatible = "snps,dw-mshc"; - reg = <0x1820000 0x1000>; - interrupts = <0 34 4>; - clocks = <&clock HIX5HD2_SD_CIU_RST>, - <&clock HIX5HD2_SD_BIU_CLK>; - clock-names = "biu", "ciu"; - }; - - gmac0: ethernet@1840000 { - compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; - reg = <0x1840000 0x1000>,<0x184300c 0x4>; - interrupts = <0 71 4>; - clocks = <&clock HIX5HD2_MAC0_CLK>; - clock-names = "mac_core"; - status = "disabled"; - }; - - gmac1: ethernet@1841000 { - compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; - reg = <0x1841000 0x1000>,<0x1843010 0x4>; - interrupts = <0 72 4>; - clocks = <&clock HIX5HD2_MAC1_CLK>; - clock-names = "mac_core"; - status = "disabled"; - }; - - usb0: usb@1890000 { - compatible = "generic-ehci"; - reg = <0x1890000 0x1000>; - interrupts = <0 66 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - usb1: usb@1880000 { - compatible = "generic-ohci"; - reg = <0x1880000 0x1000>; - interrupts = <0 67 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - peripheral_ctrl: syscon@a20000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0xa20000 0x1000>; - }; - - sata_phy: phy@1900000 { - compatible = "hisilicon,hix5hd2-sata-phy"; - reg = <0x1900000 0x10000>; - #phy-cells = <0>; - hisilicon,peripheral-syscon = <&peripheral_ctrl>; - hisilicon,power-reg = <0x8 10>; - }; - - ahci: sata@1900000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0x1900000 0x10000>; - interrupts = <0 70 4>; - clocks = <&clock HIX5HD2_SATA_CLK>; - }; - - ir: ir@1000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0x001000 0x1000>; - interrupts = <0 47 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - hisilicon,power-syscon = <&sysctrl>; - }; - - i2c0: i2c@b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb10000 0x1000>; - interrupts = <0 38 4>; - clocks = <&clock HIX5HD2_I2C0_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@b11000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb11000 0x1000>; - interrupts = <0 39 4>; - clocks = <&clock HIX5HD2_I2C1_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@b12000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb12000 0x1000>; - interrupts = <0 40 4>; - clocks = <&clock HIX5HD2_I2C2_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@b13000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb13000 0x1000>; - interrupts = <0 41 4>; - clocks = <&clock HIX5HD2_I2C3_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@b16000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb16000 0x1000>; - interrupts = <0 43 4>; - clocks = <&clock HIX5HD2_I2C4_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@b17000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb17000 0x1000>; - interrupts = <0 44 4>; - clocks = <&clock HIX5HD2_I2C5_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/hisilicon/Makefile b/arch/arm/boot/dts/hisilicon/Makefile new file mode 100644 index 000000000000..5ce0512c0010 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HI3xxx) += \ + hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HIP01) += \ + hip01-ca9x2.dtb +dtb-$(CONFIG_ARCH_HIP04) += \ + hip04-d01.dtb +dtb-$(CONFIG_ARCH_HISI) += \ + hi3519-demb.dtb +dtb-$(CONFIG_ARCH_HIX5HD2) += \ + hisi-x5hd2-dkb.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb diff --git a/arch/arm/boot/dts/hisilicon/hi3519-demb.dts b/arch/arm/boot/dts/hisilicon/hi3519-demb.dts new file mode 100644 index 000000000000..f473fa22e9ce --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hi3519-demb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + */ + +/dts-v1/; +#include "hi3519.dtsi" + +/ { + model = "HiSilicon HI3519 DEMO Board"; + compatible = "hisilicon,hi3519"; + + aliases { + serial0 = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&dual_timer0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hisilicon/hi3519.dtsi b/arch/arm/boot/dts/hisilicon/hi3519.dtsi new file mode 100644 index 000000000000..c524c854d319 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hi3519.dtsi @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + */ + +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + }; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10301000 0x1000>, <0x10302000 0x1000>; + }; + + clk_3m: clk_3m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + + crg: clock-reset-controller@12010000 { + compatible = "hisilicon,hi3519-crg"; + #clock-cells = <1>; + #reset-cells = <2>; + reg = <0x12010000 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@12100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12100000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disable"; + }; + + uart1: serial@12101000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12101000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disable"; + }; + + uart2: serial@12102000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12102000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disable"; + }; + + uart3: serial@12103000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12103000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disable"; + }; + + uart4: serial@12104000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12104000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disable"; + }; + + dual_timer0: timer@12000000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12000000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer1: timer@12001000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12001000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer2: timer@12002000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12002000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + spi_bus0: spi@12120000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12120000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>; + clock-names = "sspclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus1: spi@12121000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12121000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>; + clock-names = "sspclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus2: spi@12122000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12122000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>; + clock-names = "sspclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + sysctrl: system-controller@12020000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12020000 0x1000>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts b/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts new file mode 100644 index 000000000000..f1c816a1d7cf --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts @@ -0,0 +1,647 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012-2013 Linaro Ltd. + * Author: Haojian Zhuang + */ + +/dts-v1/; + +#include "hi3620.dtsi" + +/ { + model = "Hisilicon Hi4511 Development Board"; + compatible = "hisilicon,hi3620-hi4511"; + + chosen { + bootargs = "root=/dev/ram0"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + amba-bus { + dual_timer0: dual_timer@800000 { + status = "okay"; + }; + + uart0: serial@b00000 { /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; + status = "okay"; + }; + + uart1: serial@b01000 { /* modem */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; + pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; + status = "okay"; + }; + + uart2: serial@b02000 { /* audience */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; + status = "okay"; + }; + + uart3: serial@b03000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; + status = "okay"; + }; + + uart4: serial@b04000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; + status = "okay"; + }; + + pmx0: pinmux@803000 { + pinctrl-names = "default"; + pinctrl-0 = <&board_pmx_pins>; + + board_pmx_pins: board-pins { + pinctrl-single,pins = < + 0x008 0x0 /* GPIO -- eFUSE_DOUT */ + 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ + >; + }; + uart0_pmx_func: uart0-pins { + pinctrl-single,pins = < + 0x0f0 0x0 + 0x0f4 0x0 /* UART0_RX & UART0_TX */ + >; + }; + uart0_pmx_idle: uart0-idle-pins { + pinctrl-single,pins = < + /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ + 0x0f4 0x1 /* UART0_RX & UART0_TX */ + >; + }; + uart1_pmx_func: uart1-pins { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ + 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ + >; + }; + uart1_pmx_idle: uart1-idle-pins { + pinctrl-single,pins = < + 0x0f8 0x1 /* GPIO (IOMG61) */ + 0x0fc 0x1 /* GPIO (IOMG62) */ + >; + }; + uart2_pmx_func: uart2-pins { + pinctrl-single,pins = < + 0x104 0x2 /* UART2_RXD (IOMG96) */ + 0x108 0x2 /* UART2_TXD (IOMG64) */ + >; + }; + uart2_pmx_idle: uart2-idle-pins { + pinctrl-single,pins = < + 0x104 0x1 /* GPIO (IOMG96) */ + 0x108 0x1 /* GPIO (IOMG64) */ + >; + }; + uart3_pmx_func: uart3-pins { + pinctrl-single,pins = < + 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ + 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ + >; + }; + uart3_pmx_idle: uart3-idle-pins { + pinctrl-single,pins = < + 0x160 0x1 /* GPIO (IOMG85) */ + 0x164 0x1 /* GPIO (IOMG86) */ + >; + }; + uart4_pmx_func: uart4-pins { + pinctrl-single,pins = < + 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ + 0x16c 0x0 /* UART4_RXD (IOMG88) */ + 0x170 0x0 /* UART4_TXD (IOMG93) */ + >; + }; + uart4_pmx_idle: uart4-idle-pins { + pinctrl-single,pins = < + 0x168 0x1 /* GPIO (IOMG87) */ + 0x16c 0x1 /* GPIO (IOMG88) */ + 0x170 0x1 /* GPIO (IOMG93) */ + >; + }; + i2c0_pmx_func: i2c0-pins { + pinctrl-single,pins = < + 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ + >; + }; + i2c0_pmx_idle: i2c0-idle-pins { + pinctrl-single,pins = < + 0x0b4 0x1 /* GPIO (IOMG45) */ + >; + }; + i2c1_pmx_func: i2c1-pins { + pinctrl-single,pins = < + 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ + >; + }; + i2c1_pmx_idle: i2c1-idle-pins { + pinctrl-single,pins = < + 0x0b8 0x1 /* GPIO (IOMG46) */ + >; + }; + i2c2_pmx_func: i2c2-pins { + pinctrl-single,pins = < + 0x068 0x0 /* I2C2_SCL (IOMG26) */ + 0x06c 0x0 /* I2C2_SDA (IOMG27) */ + >; + }; + i2c2_pmx_idle: i2c2-idle-pins { + pinctrl-single,pins = < + 0x068 0x1 /* GPIO (IOMG26) */ + 0x06c 0x1 /* GPIO (IOMG27) */ + >; + }; + i2c3_pmx_func: i2c3-pins { + pinctrl-single,pins = < + 0x050 0x2 /* I2C3_SCL (IOMG20) */ + 0x054 0x2 /* I2C3_SDA (IOMG21) */ + >; + }; + i2c3_pmx_idle: i2c3-idle-pins { + pinctrl-single,pins = < + 0x050 0x1 /* GPIO (IOMG20) */ + 0x054 0x1 /* GPIO (IOMG21) */ + >; + }; + spi0_pmx_func: spi0-pins { + pinctrl-single,pins = < + 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ + 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ + 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ + 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ + 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ + >; + }; + spi0_pmx_idle: spi0-idle-pins { + pinctrl-single,pins = < + 0x0d4 0x1 /* GPIO (IOMG53) */ + 0x0d8 0x1 /* GPIO (IOMG54) */ + 0x0dc 0x1 /* GPIO (IOMG55) */ + 0x0e0 0x1 /* GPIO (IOMG56) */ + 0x0e4 0x1 /* GPIO (IOMG57) */ + >; + }; + spi1_pmx_func: spi1-pins { + pinctrl-single,pins = < + 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ + 0x0e8 0x0 /* SPI1_DO (IOMG58) */ + 0x0ec 0x0 /* SPI1_CS (IOMG95) */ + >; + }; + spi1_pmx_idle: spi1-idle-pins { + pinctrl-single,pins = < + 0x184 0x1 /* GPIO (IOMG98) */ + 0x0e8 0x1 /* GPIO (IOMG58) */ + 0x0ec 0x1 /* GPIO (IOMG95) */ + >; + }; + kpc_pmx_func: kpc-pins { + pinctrl-single,pins = < + 0x12c 0x0 /* KEY_IN0 (IOMG73) */ + 0x130 0x0 /* KEY_IN1 (IOMG74) */ + 0x134 0x0 /* KEY_IN2 (IOMG75) */ + 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ + 0x110 0x0 /* KEY_OUT1 (IOMG66) */ + 0x114 0x0 /* KEY_OUT2 (IOMG67) */ + >; + }; + kpc_pmx_idle: kpc-idle-pins { + pinctrl-single,pins = < + 0x12c 0x1 /* GPIO (IOMG73) */ + 0x130 0x1 /* GPIO (IOMG74) */ + 0x134 0x1 /* GPIO (IOMG75) */ + 0x10c 0x1 /* GPIO (IOMG65) */ + 0x110 0x1 /* GPIO (IOMG66) */ + 0x114 0x1 /* GPIO (IOMG67) */ + >; + }; + gpio_key_func: gpio-key-pins { + pinctrl-single,pins = < + 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ + 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ + >; + }; + emmc_pmx_func: emmc-pins { + pinctrl-single,pins = < + 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ + 0x018 0x0 /* NAND_CS3_N (IOMG6) */ + 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ + 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ + 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ + >; + }; + emmc_pmx_idle: emmc-idle-pins { + pinctrl-single,pins = < + 0x030 0x0 /* GPIO (IOMG12) */ + 0x018 0x1 /* GPIO (IOMG6) */ + 0x024 0x1 /* GPIO (IOMG8) */ + 0x028 0x1 /* GPIO (IOMG9) */ + 0x02c 0x1 /* GPIO (IOMG10) */ + >; + }; + sd_pmx_func: sd-pins { + pinctrl-single,pins = < + 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ + 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ + >; + }; + sd_pmx_idle: sd-idle-pins { + pinctrl-single,pins = < + 0x0bc 0x1 /* GPIO (IOMG47) */ + 0x0c0 0x1 /* GPIO (IOMG48) */ + >; + }; + nand_pmx_func: nand-pins { + pinctrl-single,pins = < + 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ + 0x010 0x0 /* NAND_CS1_N (IOMG4) */ + 0x014 0x0 /* NAND_CS2_N (IOMG5) */ + 0x018 0x0 /* NAND_CS3_N (IOMG6) */ + 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ + 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ + 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ + 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ + 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ + >; + }; + nand_pmx_idle: nand-idle-pins { + pinctrl-single,pins = < + 0x00c 0x1 /* GPIO (IOMG3) */ + 0x010 0x1 /* GPIO (IOMG4) */ + 0x014 0x1 /* GPIO (IOMG5) */ + 0x018 0x1 /* GPIO (IOMG6) */ + 0x01c 0x1 /* GPIO (IOMG94) */ + 0x020 0x1 /* GPIO (IOMG7) */ + 0x024 0x1 /* GPIO (IOMG8) */ + 0x028 0x1 /* GPIO (IOMG9) */ + 0x02c 0x1 /* GPIO (IOMG10) */ + >; + }; + sdio_pmx_func: sdio-pins { + pinctrl-single,pins = < + 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ + >; + }; + sdio_pmx_idle: sdio-idle-pins { + pinctrl-single,pins = < + 0x0c4 0x1 /* GPIO (IOMG49) */ + >; + }; + audio_out_pmx_func: audio-out-pins { + pinctrl-single,pins = < + 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ + >; + }; + }; + + pmx1: pinmux@803800 { + pinctrl-names = "default"; + pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins + &board_np_pins &board_ps_pins &kpc_cfg_func + &audio_out_cfg_func>; + board_pu_pins: board-pu-pins { + pinctrl-single,pins = < + 0x014 0 /* GPIO_158 (IOCFG2) */ + 0x018 0 /* GPIO_159 (IOCFG3) */ + 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ + 0x020 0 /* BOOT_MODE1 (IOCFG5) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + }; + board_pd_pins: board-pd-pins { + pinctrl-single,pins = < + 0x038 0 /* eFUSE_DOUT (IOCFG11) */ + 0x150 0 /* ISP_GPIO8 (IOCFG93) */ + 0x154 0 /* ISP_GPIO9 (IOCFG94) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + board_pd_ps_pins: board-pd-ps-pins { + pinctrl-single,pins = < + 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ + 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + board_np_pins: board-np-pins { + pinctrl-single,pins = < + 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + board_ps_pins: board-ps-pins { + pinctrl-single,pins = < + 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ + 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ + >; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + uart0_cfg_func: uart0-cfg-pins { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart0_cfg_idle: uart0-cfg-idle-pins { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart1_cfg_func: uart1-cfg-pins { + pinctrl-single,pins = < + 0x210 0 /* UART1_CTS (IOCFG140) */ + 0x214 0 /* UART1_RTS (IOCFG141) */ + 0x218 0 /* UART1_RXD (IOCFG142) */ + 0x21c 0 /* UART1_TXD (IOCFG143) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart1_cfg_idle: uart1-cfg-idle-pins { + pinctrl-single,pins = < + 0x210 0 /* UART1_CTS (IOCFG140) */ + 0x214 0 /* UART1_RTS (IOCFG141) */ + 0x218 0 /* UART1_RXD (IOCFG142) */ + 0x21c 0 /* UART1_TXD (IOCFG143) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart2_cfg_func: uart2-cfg-pins { + pinctrl-single,pins = < + 0x220 0 /* UART2_CTS (IOCFG144) */ + 0x224 0 /* UART2_RTS (IOCFG145) */ + 0x228 0 /* UART2_RXD (IOCFG146) */ + 0x22c 0 /* UART2_TXD (IOCFG147) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart2_cfg_idle: uart2-cfg-idle-pins { + pinctrl-single,pins = < + 0x220 0 /* GPIO (IOCFG144) */ + 0x224 0 /* GPIO (IOCFG145) */ + 0x228 0 /* GPIO (IOCFG146) */ + 0x22c 0 /* GPIO (IOCFG147) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart3_cfg_func: uart3-cfg-pins { + pinctrl-single,pins = < + 0x294 0 /* UART3_CTS (IOCFG173) */ + 0x298 0 /* UART3_RTS (IOCFG174) */ + 0x29c 0 /* UART3_RXD (IOCFG175) */ + 0x2a0 0 /* UART3_TXD (IOCFG176) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart3_cfg_idle: uart3-cfg-idle-pins { + pinctrl-single,pins = < + 0x294 0 /* UART3_CTS (IOCFG173) */ + 0x298 0 /* UART3_RTS (IOCFG174) */ + 0x29c 0 /* UART3_RXD (IOCFG175) */ + 0x2a0 0 /* UART3_TXD (IOCFG176) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart4_cfg_func: uart4-cfg-pins { + pinctrl-single,pins = < + 0x2a4 0 /* UART4_CTS (IOCFG177) */ + 0x2a8 0 /* UART4_RTS (IOCFG178) */ + 0x2ac 0 /* UART4_RXD (IOCFG179) */ + 0x2b0 0 /* UART4_TXD (IOCFG180) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + i2c0_cfg_func: i2c0-cfg-pins { + pinctrl-single,pins = < + 0x17c 0 /* I2C0_SCL (IOCFG103) */ + 0x180 0 /* I2C0_SDA (IOCFG104) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + i2c1_cfg_func: i2c1-cfg-pins { + pinctrl-single,pins = < + 0x184 0 /* I2C1_SCL (IOCFG105) */ + 0x188 0 /* I2C1_SDA (IOCFG106) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + i2c2_cfg_func: i2c2-cfg-pins { + pinctrl-single,pins = < + 0x118 0 /* I2C2_SCL (IOCFG79) */ + 0x11c 0 /* I2C2_SDA (IOCFG80) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + i2c3_cfg_func: i2c3-cfg-pins { + pinctrl-single,pins = < + 0x100 0 /* I2C3_SCL (IOCFG73) */ + 0x104 0 /* I2C3_SDA (IOCFG74) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi0_cfg_func1: spi0-cfg-func1-pins { + pinctrl-single,pins = < + 0x1d4 0 /* SPI0_CLK (IOCFG125) */ + 0x1d8 0 /* SPI0_DI (IOCFG126) */ + 0x1dc 0 /* SPI0_DO (IOCFG127) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi0_cfg_func2: spi0-cfg-func2-pins { + pinctrl-single,pins = < + 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ + 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ + 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ + 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi1_cfg_func1: spi1-cfg-func1-pins { + pinctrl-single,pins = < + 0x1f0 0 /* SPI1_CLK (IOCFG132) */ + 0x1f4 0 /* SPI1_DI (IOCFG133) */ + 0x1f8 0 /* SPI1_DO (IOCFG134) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi1_cfg_func2: spi1-cfg-func2-pins { + pinctrl-single,pins = < + 0x1fc 0 /* SPI1_CS (IOCFG135) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + kpc_cfg_func: kpc-cfg-pins { + pinctrl-single,pins = < + 0x250 0 /* KEY_IN0 (IOCFG156) */ + 0x254 0 /* KEY_IN1 (IOCFG157) */ + 0x258 0 /* KEY_IN2 (IOCFG158) */ + 0x230 0 /* KEY_OUT0 (IOCFG148) */ + 0x234 0 /* KEY_OUT1 (IOCFG149) */ + 0x238 0 /* KEY_OUT2 (IOCFG150) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + emmc_cfg_func: emmc-cfg-pins { + pinctrl-single,pins = < + 0x0ac 0 /* eMMC_CMD (IOCFG40) */ + 0x0b0 0 /* eMMC_CLK (IOCFG41) */ + 0x058 0 /* NAND_CS3_N (IOCFG19) */ + 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ + 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ + 0x08c 0 /* NAND_DATA8 (IOCFG32) */ + 0x090 0 /* NAND_DATA9 (IOCFG33) */ + 0x094 0 /* NAND_DATA10 (IOCFG34) */ + 0x098 0 /* NAND_DATA11 (IOCFG35) */ + 0x09c 0 /* NAND_DATA12 (IOCFG36) */ + 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ + 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ + 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + sd_cfg_func1: sd-cfg-func1-pins { + pinctrl-single,pins = < + 0x18c 0 /* SD_CLK (IOCFG107) */ + 0x190 0 /* SD_CMD (IOCFG108) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + sd_cfg_func2: sd-cfg-func2-pins { + pinctrl-single,pins = < + 0x194 0 /* SD_DATA0 (IOCFG109) */ + 0x198 0 /* SD_DATA1 (IOCFG110) */ + 0x19c 0 /* SD_DATA2 (IOCFG111) */ + 0x1a0 0 /* SD_DATA3 (IOCFG112) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x70 0xf0>; + }; + nand_cfg_func1: nand-cfg-func1-pins { + pinctrl-single,pins = < + 0x03c 0 /* NAND_ALE (IOCFG12) */ + 0x040 0 /* NAND_CLE (IOCFG13) */ + 0x06c 0 /* NAND_DATA0 (IOCFG24) */ + 0x070 0 /* NAND_DATA1 (IOCFG25) */ + 0x074 0 /* NAND_DATA2 (IOCFG26) */ + 0x078 0 /* NAND_DATA3 (IOCFG27) */ + 0x07c 0 /* NAND_DATA4 (IOCFG28) */ + 0x080 0 /* NAND_DATA5 (IOCFG29) */ + 0x084 0 /* NAND_DATA6 (IOCFG30) */ + 0x088 0 /* NAND_DATA7 (IOCFG31) */ + 0x08c 0 /* NAND_DATA8 (IOCFG32) */ + 0x090 0 /* NAND_DATA9 (IOCFG33) */ + 0x094 0 /* NAND_DATA10 (IOCFG34) */ + 0x098 0 /* NAND_DATA11 (IOCFG35) */ + 0x09c 0 /* NAND_DATA12 (IOCFG36) */ + 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ + 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ + 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + nand_cfg_func2: nand-cfg-func2-pins { + pinctrl-single,pins = < + 0x044 0 /* NAND_RE_N (IOCFG14) */ + 0x048 0 /* NAND_WE_N (IOCFG15) */ + 0x04c 0 /* NAND_CS0_N (IOCFG16) */ + 0x050 0 /* NAND_CS1_N (IOCFG17) */ + 0x054 0 /* NAND_CS2_N (IOCFG18) */ + 0x058 0 /* NAND_CS3_N (IOCFG19) */ + 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ + 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ + 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ + 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + sdio_cfg_func: sdio-cfg-pins { + pinctrl-single,pins = < + 0x1a4 0 /* SDIO0_CLK (IOCG113) */ + 0x1a8 0 /* SDIO0_CMD (IOCG114) */ + 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ + 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ + 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ + 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + audio_out_cfg_func: audio-out-cfg-pins { + pinctrl-single,pins = < + 0x200 0 /* GPIO (IOCFG136) */ + 0x204 0 /* GPIO (IOCFG137) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + call { + label = "call"; + gpios = <&gpio17 2 0>; + linux,code = <169>; /* KEY_PHONE */ + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/hi3620.dtsi b/arch/arm/boot/dts/hisilicon/hi3620.dtsi new file mode 100644 index 000000000000..a254ec009296 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hi3620.dtsi @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * HiSilicon Ltd. Hi3620 SoC + * + * Copyright (C) 2012-2013 HiSilicon Ltd. + * Copyright (C) 2012-2013 Linaro Ltd. + * + * Author: Haojian Zhuang + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + pclk: clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "apb_pclk"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "hisilicon,hi3620-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + amba-bus { + + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0xfc000000 0x2000000>; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0x100000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + }; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0x1000 0x1000>, <0x100 0x100>; + }; + + sysctrl: system-controller@802000 { + compatible = "hisilicon,sysctrl", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x802000 0x1000>; + reg = <0x802000 0x1000>; + + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + + clock: clock@0 { + compatible = "hisilicon,hi3620-clock"; + reg = <0 0x10000>; + #clock-cells = <1>; + }; + }; + + dual_timer0: dual_timer@800000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x800000 0x1000>; + /* timer00 & timer01 */ + interrupts = <0 0 4>, <0 1 4>; + clocks = <&clock HI3620_TIMER0_MUX>, + <&clock HI3620_TIMER1_MUX>, + <&clock HI3620_TIMER0_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + dual_timer1: dual_timer@801000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x801000 0x1000>; + /* timer10 & timer11 */ + interrupts = <0 2 4>, <0 3 4>; + clocks = <&clock HI3620_TIMER2_MUX>, + <&clock HI3620_TIMER3_MUX>, + <&clock HI3620_TIMER2_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + dual_timer2: dual_timer@a01000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xa01000 0x1000>; + /* timer20 & timer21 */ + interrupts = <0 4 4>, <0 5 4>; + clocks = <&clock HI3620_TIMER4_MUX>, + <&clock HI3620_TIMER5_MUX>, + <&clock HI3620_TIMER4_MUX>; + clock-names = "timer0lck", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + dual_timer3: dual_timer@a02000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xa02000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 6 4>, <0 7 4>; + clocks = <&clock HI3620_TIMER6_MUX>, + <&clock HI3620_TIMER7_MUX>, + <&clock HI3620_TIMER6_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + dual_timer4: dual_timer@a03000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xa03000 0x1000>; + /* timer40 & timer41 */ + interrupts = <0 96 4>, <0 97 4>; + clocks = <&clock HI3620_TIMER8_MUX>, + <&clock HI3620_TIMER9_MUX>, + <&clock HI3620_TIMER8_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + status = "disabled"; + }; + + timer5: timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = <1 13 0xf01>; + }; + + uart0: serial@b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb00000 0x1000>; + interrupts = <0 20 4>; + clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@b01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb01000 0x1000>; + interrupts = <0 21 4>; + clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb02000 0x1000>; + interrupts = <0 22 4>; + clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@b03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb03000 0x1000>; + interrupts = <0 23 4>; + clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@b04000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb04000 0x1000>; + interrupts = <0 24 4>; + clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + gpio0: gpio@806000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x806000 0x1000>; + interrupts = <0 64 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 + &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@807000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x807000 0x1000>; + interrupts = <0 65 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 + &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 + &pmx0 6 5 1 &pmx0 7 6 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@808000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x808000 0x1000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 + &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 + &pmx0 6 3 1 &pmx0 7 3 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@809000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x809000 0x1000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 + &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 + &pmx0 6 11 1 &pmx0 7 11 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@80a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80a000 0x1000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 + &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 + &pmx0 6 13 1 &pmx0 7 13 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@80b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80b000 0x1000>; + interrupts = <0 69 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 + &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 + &pmx0 6 16 1 &pmx0 7 16 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@80c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80c000 0x1000>; + interrupts = <0 70 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 + &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 + &pmx0 6 18 1 &pmx0 7 19 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@80d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80d000 0x1000>; + interrupts = <0 71 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 + &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 + &pmx0 6 25 1 &pmx0 7 26 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@80e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80e000 0x1000>; + interrupts = <0 72 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 + &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 + &pmx0 6 33 1 &pmx0 7 34 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@80f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80f000 0x1000>; + interrupts = <0 73 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 + &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 + &pmx0 6 41 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@810000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x810000 0x1000>; + interrupts = <0 74 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 + &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@811000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x811000 0x1000>; + interrupts = <0 75 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 + &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 + &pmx0 6 49 1 &pmx0 7 49 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@812000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x812000 0x1000>; + interrupts = <0 76 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 + &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 + &pmx0 6 51 1 &pmx0 7 52 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@813000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x813000 0x1000>; + interrupts = <0 77 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 + &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 + &pmx0 6 55 1 &pmx0 7 56 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@814000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x814000 0x1000>; + interrupts = <0 78 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 + &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 + &pmx0 6 60 1 &pmx0 7 61 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@815000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x815000 0x1000>; + interrupts = <0 79 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 + &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 + &pmx0 6 64 1 &pmx0 7 65 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@816000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x816000 0x1000>; + interrupts = <0 80 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 + &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 + &pmx0 6 72 1 &pmx0 7 73 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@817000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x817000 0x1000>; + interrupts = <0 81 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 + &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 + &pmx0 6 80 1 &pmx0 7 81 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@818000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x818000 0x1000>; + interrupts = <0 82 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 + &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 + &pmx0 6 86 1 &pmx0 7 87 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@819000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x819000 0x1000>; + interrupts = <0 83 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 + &pmx0 3 88 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@81a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x81a000 0x1000>; + interrupts = <0 84 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 + &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@81b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x81b000 0x1000>; + interrupts = <0 85 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK21>; + clock-names = "apb_pclk"; + }; + + pmx0: pinmux@803000 { + compatible = "pinctrl-single"; + reg = <0x803000 0x188>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #gpio-range-cells = <3>; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 + &range 12 1 0 &range 13 29 1 + &range 43 1 0 &range 44 49 1 + &range 94 1 1 &range 96 2 1>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pmx1: pinmux@803800 { + compatible = "pinconf-single"; + reg = <0x803800 0x2dc>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + + pinctrl-single,register-width = <32>; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts b/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts new file mode 100644 index 000000000000..f3faf247cd61 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * HiSilicon Ltd. HiP01 SoC + * + * Copyright (C) 2014 HiSilicon Ltd. + * Copyright (C) 2014 Huawei Ltd. + * + * Author: Wang Long + */ + +/dts-v1/; + +/* First 8KB reserved for secondary core boot */ +/memreserve/ 0x80000000 0x00002000; + +#include "hip01.dtsi" + +/ { + model = "Hisilicon HIP01 Development Board"; + compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "hisilicon,hip01-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hisilicon/hip01.dtsi b/arch/arm/boot/dts/hisilicon/hip01.dtsi new file mode 100644 index 000000000000..e17f36bd9006 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hip01.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * HiSilicon Ltd. HiP01 SoC + * + * Copyright (c) 2014 HiSilicon Ltd. + * Copyright (c) 2014 Huawei Ltd. + * + * Author: Wang Long + */ + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; + }; + + hisi_refclk144mhz: refclk144mkhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <144000000>; + clock-output-names = "hisi:refclk144khz"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0x10000000 0x20000000>; + + amba-bus { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + uart0: serial@10001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10001000 0x1000>; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <0 32 4>; + status = "disabled"; + }; + + uart1: serial@10002000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10002000 0x1000>; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <0 33 4>; + status = "disabled"; + }; + + uart2: serial@10003000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10003000 0x1000>; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <0 34 4>; + status = "disabled"; + }; + + uart3: serial@10006000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10006000 0x1000>; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <0 4 4>; + status = "disabled"; + }; + }; + + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + global_timer@a000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x0a000200 0x100>; + interrupts = <1 11 0xf04>; + clocks = <&hisi_refclk144mhz>; + }; + + local_timer@a000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x0a000600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&hisi_refclk144mhz>; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/hip04-d01.dts b/arch/arm/boot/dts/hisilicon/hip04-d01.dts new file mode 100644 index 000000000000..0210064bf6a5 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hip04-d01.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Linaro Ltd. + * Author: Haojian Zhuang + */ + +/dts-v1/; + +#include "hip04.dtsi" + +/ { + /* memory bus is 64-bit */ + #address-cells = <2>; + #size-cells = <2>; + model = "Hisilicon D01 Development Board"; + compatible = "hisilicon,hip04-d01"; + + memory@0,10000000 { + device_type = "memory"; + reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, + <0x00000004 0xc0000000 0x00000003 0x40000000>; + }; + + soc { + uart0: serial@4007000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/hip04.dtsi b/arch/arm/boot/dts/hisilicon/hip04.dtsi new file mode 100644 index 000000000000..2424cc545c9c --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hip04.dtsi @@ -0,0 +1,986 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * HiSilicon Ltd. HiP04 SoC + * + * Copyright (C) 2013-2014 HiSilicon Ltd. + * Copyright (C) 2013-2014 Linaro Ltd. + * + * Author: Haojian Zhuang + */ + +/ { + /* memory bus is 64-bit */ + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + bootwrapper { + compatible = "hisilicon,hip04-bootwrapper"; + boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + core2 { + cpu = <&CPU10>; + }; + core3 { + cpu = <&CPU11>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + core2 { + cpu = <&CPU14>; + }; + core3 { + cpu = <&CPU15>; + }; + }; + }; + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + }; + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + }; + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x102>; + }; + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x103>; + }; + CPU8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x200>; + }; + CPU9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x201>; + }; + CPU10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x202>; + }; + CPU11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x203>; + }; + CPU12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x300>; + }; + CPU13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x301>; + }; + CPU14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x302>; + }; + CPU15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x303>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + clk_50m: clk_50m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + clk_168m: clk_168m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <168000000>; + }; + + clk_375m: clk_375m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <375000000>; + }; + + soc { + /* It's a 32-bit SoC. */ + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0 0xe0000000 0x10000000>; + + gic: interrupt-controller@c01000 { + compatible = "hisilicon,hip04-intc"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = <1 9 0xf04>; + + reg = <0xc01000 0x1000>, <0xc02000 0x1000>, + <0xc04000 0x2000>, <0xc06000 0x2000>; + }; + + sysctrl: sysctrl { + compatible = "hisilicon,sysctrl", "syscon"; + reg = <0x3e00000 0x00100000>; + }; + + fabric: fabric { + compatible = "hisilicon,hip04-fabric"; + reg = <0x302a000 0x1000>; + }; + + dual_timer0: dual_timer@3000000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x3000000 0x1000>; + interrupts = <0 224 4>; + clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; + }; + + arm-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 64 4>, + <0 65 4>, + <0 66 4>, + <0 67 4>, + <0 68 4>, + <0 69 4>, + <0 70 4>, + <0 71 4>, + <0 72 4>, + <0 73 4>, + <0 74 4>, + <0 75 4>, + <0 76 4>, + <0 77 4>, + <0 78 4>, + <0 79 4>; + }; + + uart0: serial@4007000 { + compatible = "snps,dw-apb-uart"; + reg = <0x4007000 0x1000>; + interrupts = <0 381 4>; + clocks = <&clk_168m>, <&clk_168m>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + status = "disabled"; + }; + + sata0: sata@a000000 { + compatible = "hisilicon,hisi-ahci"; + reg = <0xa000000 0x1000000>; + interrupts = <0 372 4>; + }; + + }; + + etb@0,e3c42000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3c42000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + etb0_in_port: endpoint@0 { + remote-endpoint = <&replicator0_out_port0>; + }; + }; + }; + }; + + etb@0,e3c82000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3c82000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + etb1_in_port: endpoint@0 { + remote-endpoint = <&replicator1_out_port0>; + }; + }; + }; + }; + + etb@0,e3cc2000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3cc2000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + etb2_in_port: endpoint@0 { + remote-endpoint = <&replicator2_out_port0>; + }; + }; + }; + }; + + etb@0,e3d02000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3d02000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + etb3_in_port: endpoint@0 { + remote-endpoint = <&replicator3_out_port0>; + }; + }; + }; + }; + + tpiu@0,e3c05000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xe3c05000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint@0 { + remote-endpoint = <&funnel4_out_port0>; + }; + }; + }; + }; + + replicator0 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator0_out_port0: endpoint { + remote-endpoint = <&etb0_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator0_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port0>; + }; + }; + }; + + in-ports { + port { + replicator0_in_port0: endpoint { + remote-endpoint = <&funnel0_out_port0>; + }; + }; + }; + }; + + replicator1 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator1_out_port0: endpoint { + remote-endpoint = <&etb1_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator1_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port1>; + }; + }; + }; + + in-ports { + port { + replicator1_in_port0: endpoint { + remote-endpoint = <&funnel1_out_port0>; + }; + }; + }; + }; + + replicator2 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator2_out_port0: endpoint { + remote-endpoint = <&etb2_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator2_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port2>; + }; + }; + }; + + in-ports { + port { + replicator2_in_port0: endpoint { + remote-endpoint = <&funnel2_out_port0>; + }; + }; + }; + }; + + replicator3 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator3_out_port0: endpoint { + remote-endpoint = <&etb3_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator3_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port3>; + }; + }; + }; + + in-ports { + port { + replicator3_in_port0: endpoint { + remote-endpoint = <&funnel3_out_port0>; + }; + }; + }; + }; + + funnel@0,e3c41000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xe3c41000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel0_out_port0: endpoint { + remote-endpoint = + <&replicator0_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel0_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel0_in_port2: endpoint { + remote-endpoint = <&ptm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel0_in_port3: endpoint { + remote-endpoint = <&ptm3_out_port>; + }; + }; + }; + }; + + funnel@0,e3c81000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xe3c81000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel1_out_port0: endpoint { + remote-endpoint = + <&replicator1_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in_port0: endpoint { + remote-endpoint = <&ptm4_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel1_in_port1: endpoint { + remote-endpoint = <&ptm5_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel1_in_port2: endpoint { + remote-endpoint = <&ptm6_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel1_in_port3: endpoint { + remote-endpoint = <&ptm7_out_port>; + }; + }; + }; + }; + + funnel@0,e3cc1000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xe3cc1000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel2_out_port0: endpoint { + remote-endpoint = + <&replicator2_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel2_in_port0: endpoint { + remote-endpoint = <&ptm8_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel2_in_port1: endpoint { + remote-endpoint = <&ptm9_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel2_in_port2: endpoint { + remote-endpoint = <&ptm10_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel2_in_port3: endpoint { + remote-endpoint = <&ptm11_out_port>; + }; + }; + }; + }; + + funnel@0,e3d01000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xe3d01000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel3_out_port0: endpoint { + remote-endpoint = + <&replicator3_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel3_in_port0: endpoint { + remote-endpoint = <&ptm12_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel3_in_port1: endpoint { + remote-endpoint = <&ptm13_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel3_in_port2: endpoint { + remote-endpoint = <&ptm14_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel3_in_port3: endpoint { + remote-endpoint = <&ptm15_out_port>; + }; + }; + }; + }; + + funnel@0,e3c04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xe3c04000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel4_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel4_in_port0: endpoint { + remote-endpoint = + <&replicator0_out_port1>; + }; + }; + + port@1 { + reg = <1>; + funnel4_in_port1: endpoint { + remote-endpoint = + <&replicator1_out_port1>; + }; + }; + + port@2 { + reg = <2>; + funnel4_in_port2: endpoint { + remote-endpoint = + <&replicator2_out_port1>; + }; + }; + + port@3 { + reg = <3>; + funnel4_in_port3: endpoint { + remote-endpoint = + <&replicator3_out_port1>; + }; + }; + }; + }; + + ptm@0,e3c7c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7c000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; + }; + + ptm@0,e3c7d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7d000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel0_in_port1>; + }; + }; + }; + }; + + ptm@0,e3c7e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7e000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU2>; + out-ports { + port { + ptm2_out_port: endpoint { + remote-endpoint = <&funnel0_in_port2>; + }; + }; + }; + }; + + ptm@0,e3c7f000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7f000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU3>; + out-ports { + port { + ptm3_out_port: endpoint { + remote-endpoint = <&funnel0_in_port3>; + }; + }; + }; + }; + + ptm@0,e3cbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbc000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU4>; + out-ports { + port { + ptm4_out_port: endpoint { + remote-endpoint = <&funnel1_in_port0>; + }; + }; + }; + }; + + ptm@0,e3cbd000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbd000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU5>; + out-ports { + port { + ptm5_out_port: endpoint { + remote-endpoint = <&funnel1_in_port1>; + }; + }; + }; + }; + + ptm@0,e3cbe000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbe000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU6>; + out-ports { + port { + ptm6_out_port: endpoint { + remote-endpoint = <&funnel1_in_port2>; + }; + }; + }; + }; + + ptm@0,e3cbf000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbf000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU7>; + out-ports { + port { + ptm7_out_port: endpoint { + remote-endpoint = <&funnel1_in_port3>; + }; + }; + }; + }; + + ptm@0,e3cfc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cfc000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU8>; + out-ports { + port { + ptm8_out_port: endpoint { + remote-endpoint = <&funnel2_in_port0>; + }; + }; + }; + }; + + ptm@0,e3cfd000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cfd000 0 0x1000>; + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU9>; + out-ports { + port { + ptm9_out_port: endpoint { + remote-endpoint = <&funnel2_in_port1>; + }; + }; + }; + }; + + ptm@0,e3cfe000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cfe000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU10>; + out-ports { + port { + ptm10_out_port: endpoint { + remote-endpoint = <&funnel2_in_port2>; + }; + }; + }; + }; + + ptm@0,e3cff000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cff000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU11>; + out-ports { + port { + ptm11_out_port: endpoint { + remote-endpoint = <&funnel2_in_port3>; + }; + }; + }; + }; + + ptm@0,e3d3c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3c000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU12>; + out-ports { + port { + ptm12_out_port: endpoint { + remote-endpoint = <&funnel3_in_port0>; + }; + }; + }; + }; + + ptm@0,e3d3d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3d000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU13>; + out-ports { + port { + ptm13_out_port: endpoint { + remote-endpoint = <&funnel3_in_port1>; + }; + }; + }; + }; + + ptm@0,e3d3e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3e000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU14>; + out-ports { + port { + ptm14_out_port: endpoint { + remote-endpoint = <&funnel3_in_port2>; + }; + }; + }; + }; + + ptm@0,e3d3f000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3f000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU15>; + out-ports { + port { + ptm15_out_port: endpoint { + remote-endpoint = <&funnel3_in_port3>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts new file mode 100644 index 000000000000..7758c19038f0 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2014 Linaro Ltd. + * Copyright (c) 2013-2014 HiSilicon Limited. + */ + +/dts-v1/; +#include "hisi-x5hd2.dtsi" + +/ { + model = "Hisilicon HIX5HD2 Development Board"; + compatible = "hisilicon,hix5hd2"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "hisilicon,hix5hd2-smp"; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x80000000>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy2>; + phy-mode = "mii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy2: ethernet-phy@2 { + reg = <2>; + }; +}; + +&gmac1 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ahci { + phys = <&sata_phy>; + phy-names = "sata-phy"; +}; diff --git a/arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi new file mode 100644 index 000000000000..dc991ba2a9fb --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2014 Linaro Ltd. + * Copyright (c) 2013-2014 HiSilicon Limited. + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + }; + + gic: interrupt-controller@f8a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0xf8000000 0x8000000>; + + amba-bus { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + timer0: timer@2000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00002000 0x1000>; + /* timer00 & timer01 */ + interrupts = <0 24 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer1: timer@a29000 { + /* + * Only used in NORMAL state, not available ins + * SLOW or DOZE state. + * The rate is fixed in 24MHz. + */ + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a29000 0x1000>; + /* timer10 & timer11 */ + interrupts = <0 25 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer2: timer@a2a000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a2a000 0x1000>; + /* timer20 & timer21 */ + interrupts = <0 26 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer3: timer@a2b000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a2b000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 27 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer4: timer@a81000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a81000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 28 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + uart0: serial@b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b00000 0x1000>; + interrupts = <0 49 4>; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@6000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00006000 0x1000>; + interrupts = <0 50 4>; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b02000 0x1000>; + interrupts = <0 51 4>; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@b03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b03000 0x1000>; + interrupts = <0 52 4>; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@b04000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb04000 0x1000>; + interrupts = <0 53 4>; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + gpio0: gpio@b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb20000 0x1000>; + interrupts = <0 108 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb21000 0x1000>; + interrupts = <0 109 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb22000 0x1000>; + interrupts = <0 110 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio3: gpio@b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb23000 0x1000>; + interrupts = <0 111 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio4: gpio@b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb24000 0x1000>; + interrupts = <0 112 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio5: gpio@4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x004000 0x1000>; + interrupts = <0 113 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio6: gpio@b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb26000 0x1000>; + interrupts = <0 114 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio7: gpio@b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb27000 0x1000>; + interrupts = <0 115 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio8: gpio@b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb28000 0x1000>; + interrupts = <0 116 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio9: gpio@b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb29000 0x1000>; + interrupts = <0 117 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio10: gpio@b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2a000 0x1000>; + interrupts = <0 118 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio11: gpio@b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2b000 0x1000>; + interrupts = <0 119 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio12: gpio@b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2c000 0x1000>; + interrupts = <0 120 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio13: gpio@b2d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2d000 0x1000>; + interrupts = <0 121 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio14: gpio@b2e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2e000 0x1000>; + interrupts = <0 122 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio15: gpio@b2f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2f000 0x1000>; + interrupts = <0 123 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio16: gpio@b30000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb30000 0x1000>; + interrupts = <0 124 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio17: gpio@b31000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb31000 0x1000>; + interrupts = <0 125 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + wdt0: watchdog@a2c000 { + compatible = "arm,sp805", "arm,primecell"; + arm,primecell-periphid = <0x00141805>; + reg = <0xa2c000 0x1000>; + interrupts = <0 29 4>; + clocks = <&clock HIX5HD2_WDG0_RST>, + <&clock HIX5HD2_WDG0_RST>; + clock-names = "wdog_clk", "apb_pclk"; + }; + }; + + local_timer@a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + l2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0x00a10000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + }; + + sysctrl: system-controller@0 { + compatible = "hisilicon,sysctrl", "syscon"; + reg = <0x00000000 0x1000>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; + }; + + cpuctrl@a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; + + /* unremovable emmc as mmcblk0 */ + mmc: mmc@1830000 { + compatible = "snps,dw-mshc"; + reg = <0x1830000 0x1000>; + interrupts = <0 35 4>; + clocks = <&clock HIX5HD2_MMC_CIU_RST>, + <&clock HIX5HD2_MMC_BIU_CLK>; + clock-names = "biu", "ciu"; + }; + + sd: mmc@1820000 { + compatible = "snps,dw-mshc"; + reg = <0x1820000 0x1000>; + interrupts = <0 34 4>; + clocks = <&clock HIX5HD2_SD_CIU_RST>, + <&clock HIX5HD2_SD_BIU_CLK>; + clock-names = "biu", "ciu"; + }; + + gmac0: ethernet@1840000 { + compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; + reg = <0x1840000 0x1000>,<0x184300c 0x4>; + interrupts = <0 71 4>; + clocks = <&clock HIX5HD2_MAC0_CLK>; + clock-names = "mac_core"; + status = "disabled"; + }; + + gmac1: ethernet@1841000 { + compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; + reg = <0x1841000 0x1000>,<0x1843010 0x4>; + interrupts = <0 72 4>; + clocks = <&clock HIX5HD2_MAC1_CLK>; + clock-names = "mac_core"; + status = "disabled"; + }; + + usb0: usb@1890000 { + compatible = "generic-ehci"; + reg = <0x1890000 0x1000>; + interrupts = <0 66 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + usb1: usb@1880000 { + compatible = "generic-ohci"; + reg = <0x1880000 0x1000>; + interrupts = <0 67 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + peripheral_ctrl: syscon@a20000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0xa20000 0x1000>; + }; + + sata_phy: phy@1900000 { + compatible = "hisilicon,hix5hd2-sata-phy"; + reg = <0x1900000 0x10000>; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peripheral_ctrl>; + hisilicon,power-reg = <0x8 10>; + }; + + ahci: sata@1900000 { + compatible = "hisilicon,hisi-ahci"; + reg = <0x1900000 0x10000>; + interrupts = <0 70 4>; + clocks = <&clock HIX5HD2_SATA_CLK>; + }; + + ir: ir@1000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x001000 0x1000>; + interrupts = <0 47 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + hisilicon,power-syscon = <&sysctrl>; + }; + + i2c0: i2c@b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb10000 0x1000>; + interrupts = <0 38 4>; + clocks = <&clock HIX5HD2_I2C0_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb11000 0x1000>; + interrupts = <0 39 4>; + clocks = <&clock HIX5HD2_I2C1_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb12000 0x1000>; + interrupts = <0 40 4>; + clocks = <&clock HIX5HD2_I2C2_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb13000 0x1000>; + interrupts = <0 41 4>; + clocks = <&clock HIX5HD2_I2C3_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@b16000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb16000 0x1000>; + interrupts = <0 43 4>; + clocks = <&clock HIX5HD2_I2C4_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@b17000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb17000 0x1000>; + interrupts = <0 44 4>; + clocks = <&clock HIX5HD2_I2C5_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisilicon/sd5203.dts b/arch/arm/boot/dts/hisilicon/sd5203.dts new file mode 100644 index 000000000000..69381819e07b --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 HiSilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "H836ASDJ", "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts deleted file mode 100644 index 3a7382ce40ef..000000000000 --- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for HPE DL360Gen10 - */ - -/include/ "hpe-gxp.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "hpe,gxp-dl360gen10", "hpe,gxp"; - model = "Hewlett Packard Enterprise ProLiant dl360 Gen10"; - - aliases { - serial0 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; -}; diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi deleted file mode 100644 index cf735b3c4f35..000000000000 --- a/arch/arm/boot/dts/hpe-gxp.dtsi +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for HPE GXP - */ - -/dts-v1/; -/ { - model = "Hewlett Packard Enterprise GXP BMC"; - compatible = "hpe,gxp"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - device_type = "cpu"; - next-level-cache = <&L2>; - }; - }; - - clocks { - pll: clock-0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1600000000>; - }; - - iopclk: clock-1 { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll>; - }; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - dma-ranges; - - L2: cache-controller@b0040000 { - compatible = "arm,pl310-cache"; - reg = <0xb0040000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - ahb@c0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000000 0x30000000>; - dma-ranges; - - vic0: interrupt-controller@eff0000 { - compatible = "arm,pl192-vic"; - reg = <0xeff0000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@80f00000 { - compatible = "arm,pl192-vic"; - reg = <0x80f00000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - uarta: serial@e0 { - compatible = "ns16550a"; - reg = <0xe0 0x8>; - interrupts = <17>; - interrupt-parent = <&vic0>; - clock-frequency = <1846153>; - reg-shift = <0>; - }; - - uartb: serial@e8 { - compatible = "ns16550a"; - reg = <0xe8 0x8>; - interrupts = <18>; - interrupt-parent = <&vic0>; - clock-frequency = <1846153>; - reg-shift = <0>; - }; - - uartc: serial@f0 { - compatible = "ns16550a"; - reg = <0xf0 0x8>; - interrupts = <19>; - interrupt-parent = <&vic0>; - clock-frequency = <1846153>; - reg-shift = <0>; - }; - - usb0: usb@efe0000 { - compatible = "hpe,gxp-ehci", "generic-ehci"; - reg = <0xefe0000 0x100>; - interrupts = <7>; - interrupt-parent = <&vic0>; - }; - - st: timer@80 { - compatible = "hpe,gxp-timer"; - reg = <0x80 0x16>; - interrupts = <0>; - interrupt-parent = <&vic0>; - clocks = <&iopclk>; - clock-names = "iop"; - }; - - usb1: usb@efe0100 { - compatible = "hpe,gxp-ohci", "generic-ohci"; - reg = <0xefe0100 0x110>; - interrupts = <6>; - interrupt-parent = <&vic0>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/hpe/Makefile b/arch/arm/boot/dts/hpe/Makefile new file mode 100644 index 000000000000..e175b1732cdb --- /dev/null +++ b/arch/arm/boot/dts/hpe/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HPE_GXP) += \ + hpe-bmc-dl360gen10.dtb diff --git a/arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts new file mode 100644 index 000000000000..3a7382ce40ef --- /dev/null +++ b/arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE DL360Gen10 + */ + +/include/ "hpe-gxp.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "hpe,gxp-dl360gen10", "hpe,gxp"; + model = "Hewlett Packard Enterprise ProLiant dl360 Gen10"; + + aliases { + serial0 = &uartc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/hpe/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi new file mode 100644 index 000000000000..cf735b3c4f35 --- /dev/null +++ b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GXP + */ + +/dts-v1/; +/ { + model = "Hewlett Packard Enterprise GXP BMC"; + compatible = "hpe,gxp"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + clocks { + pll: clock-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1600000000>; + }; + + iopclk: clock-1 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + L2: cache-controller@b0040000 { + compatible = "arm,pl310-cache"; + reg = <0xb0040000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + ahb@c0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000000 0x30000000>; + dma-ranges; + + vic0: interrupt-controller@eff0000 { + compatible = "arm,pl192-vic"; + reg = <0xeff0000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@80f00000 { + compatible = "arm,pl192-vic"; + reg = <0x80f00000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uarta: serial@e0 { + compatible = "ns16550a"; + reg = <0xe0 0x8>; + interrupts = <17>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartb: serial@e8 { + compatible = "ns16550a"; + reg = <0xe8 0x8>; + interrupts = <18>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartc: serial@f0 { + compatible = "ns16550a"; + reg = <0xf0 0x8>; + interrupts = <19>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + usb0: usb@efe0000 { + compatible = "hpe,gxp-ehci", "generic-ehci"; + reg = <0xefe0000 0x100>; + interrupts = <7>; + interrupt-parent = <&vic0>; + }; + + st: timer@80 { + compatible = "hpe,gxp-timer"; + reg = <0x80 0x16>; + interrupts = <0>; + interrupt-parent = <&vic0>; + clocks = <&iopclk>; + clock-names = "iop"; + }; + + usb1: usb@efe0100 { + compatible = "hpe,gxp-ohci", "generic-ohci"; + reg = <0xefe0100 0x110>; + interrupts = <6>; + interrupt-parent = <&vic0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ibm-power9-dual.dtsi b/arch/arm/boot/dts/ibm-power9-dual.dtsi deleted file mode 100644 index a0fa65b44b0f..000000000000 --- a/arch/arm/boot/dts/ibm-power9-dual.dtsi +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2018 IBM Corp - -&fsi { - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam0_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam0_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam0_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam0_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam0_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam0_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam0_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam0_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ@1 { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam1_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam1_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam1_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam1_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam1_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam1_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam1_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam1_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam1_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ@2 { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -/ { - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c102 = &cfam0_i2c2; - i2c103 = &cfam0_i2c3; - i2c104 = &cfam0_i2c4; - i2c105 = &cfam0_i2c5; - i2c106 = &cfam0_i2c6; - i2c107 = &cfam0_i2c7; - i2c108 = &cfam0_i2c8; - i2c109 = &cfam0_i2c9; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c200 = &cfam1_i2c0; - i2c201 = &cfam1_i2c1; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c204 = &cfam1_i2c4; - i2c205 = &cfam1_i2c5; - i2c206 = &cfam1_i2c6; - i2c207 = &cfam1_i2c7; - i2c208 = &cfam1_i2c8; - i2c209 = &cfam1_i2c9; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c212 = &cfam1_i2c12; - i2c213 = &cfam1_i2c13; - i2c214 = &cfam1_i2c14; - }; -}; diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts deleted file mode 100644 index 5833fb6f15d8..000000000000 --- a/arch/arm/boot/dts/imx1-ads.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx1.dtsi" - -/ { - model = "Freescale MX1 ADS"; - compatible = "fsl,imx1ads", "fsl,imx1"; - - chosen { - stdout-path = &uart1; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x04000000>; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>; - cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - status = "okay"; - - extgpio0: pcf8575@22 { - compatible = "nxp,pcf8575"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - extgpio1: pcf8575@24 { - compatible = "nxp,pcf8575"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <4>; - fsl,weim-cs-timing = <0x00003e00 0x00000801>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&iomuxc { - imx1-ads { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 - MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 - MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 - MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 - MX1_PAD_SPI1_SS__GPIO3_15 0x0 - >; - }; - - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts deleted file mode 100644 index 77b21aa7a146..000000000000 --- a/arch/arm/boot/dts/imx1-apf9328.dts +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx1.dtsi" - -/ { - model = "Armadeus APF9328"; - compatible = "armadeus,imx1-apf9328", "fsl,imx1"; - - chosen { - stdout-path = &uart1; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x00800000>; - }; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00330e04 0x00000d01>; - #address-cells = <1>; - #size-cells = <1>; - }; - - eth: eth@4,c00000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth>; - compatible = "davicom,dm9000"; - reg = < - 4 0x00c00000 0x2 - 4 0x00c00002 0x2 - >; - interrupt-parent = <&gpio2>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - fsl,weim-cs-timing = <0x0000c700 0x19190d01>; - }; -}; - -&iomuxc { - imx1-apf9328 { - pinctrl_eth: ethgrp { - fsl,pins = < - MX1_PAD_SIM_SVEN__GPIO2_14 0x0 - >; - }; - - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h deleted file mode 100644 index bd2e679cb26c..000000000000 --- a/arch/arm/boot/dts/imx1-pinfunc.h +++ /dev/null @@ -1,296 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#ifndef __DTS_IMX1_PINFUNC_H -#define __DTS_IMX1_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - * mux_id consists of - * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - * - * function: 0 - Primary function - * 1 - Alternate function - * 2 - GPIO - * direction: 0 - Input - * 1 - Output - * gpio_oconf: 0 - A_IN - * 1 - B_IN - * 2 - A_OUT - * 3 - Data Register - * gpio_iconfa/b: 0 - GPIO_IN - * 1 - Interrupt Status Register - * 2 - 0 - * 3 - 1 - * - * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is - * the pin number on the specific port (between 0 and 31). - */ - -#define MX1_PAD_A24__A24 0x00 0x004 -#define MX1_PAD_A24__GPIO1_0 0x00 0x032 -#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 -#define MX1_PAD_TIN__TIN 0x01 0x000 -#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 -#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 -#define MX1_PAD_PWMO__PWMO 0x02 0x004 -#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 -#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 -#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 -#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 -#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 -#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 -#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 -#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 -#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 -#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 -#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 -#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 -#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 -#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 -#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 -#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 -#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 -#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 -#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 -#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 -#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 -#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 -#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 -#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 -#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 -#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 -#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 -#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 -#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 -#define MX1_PAD_DTACK__DTACK 0x11 0x000 -#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 -#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 -#define MX1_PAD_DTACK__A25 0x11 0x016 -#define MX1_PAD_BCLK__BCLK 0x12 0x004 -#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 -#define MX1_PAD_LBA__LBA 0x13 0x004 -#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 -#define MX1_PAD_ECB__ECB 0x14 0x000 -#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 -#define MX1_PAD_A0__A0 0x15 0x004 -#define MX1_PAD_A0__GPIO1_21 0x15 0x032 -#define MX1_PAD_CS4__CS4 0x16 0x004 -#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 -#define MX1_PAD_CS5__CS5 0x17 0x004 -#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 -#define MX1_PAD_A16__A16 0x18 0x004 -#define MX1_PAD_A16__GPIO1_24 0x18 0x032 -#define MX1_PAD_A17__A17 0x19 0x004 -#define MX1_PAD_A17__GPIO1_25 0x19 0x032 -#define MX1_PAD_A18__A18 0x1a 0x004 -#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 -#define MX1_PAD_A19__A19 0x1b 0x004 -#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 -#define MX1_PAD_A20__A20 0x1c 0x004 -#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 -#define MX1_PAD_A21__A21 0x1d 0x004 -#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 -#define MX1_PAD_A22__A22 0x1e 0x004 -#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 -#define MX1_PAD_A23__A23 0x1f 0x004 -#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 -#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 -#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 -#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 -#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 -#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 -#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 -#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 -#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 -#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 -#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 -#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 -#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 -#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 -#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 -#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 -#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 -#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 -#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 -#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 -#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 -#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 -#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 -#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 -#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 -#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 -#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 -#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 -#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 -#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 -#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 -#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 -#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 -#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 -#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 -#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 -#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 -#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 -#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 -#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 -#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 -#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 -#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 -#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 -#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 -#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 -#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 -#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 -#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 -#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 -#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 -#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 -#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 -#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 -#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 -#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 -#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 -#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 -#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 -#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 -#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 -#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 -#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 -#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 -#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 -#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 -#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 -#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 -#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 -#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 -#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 -#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 -#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 -#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 -#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 -#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 -#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 -#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 -#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 -#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 -#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 -#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 -#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 -#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 -#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 -#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 -#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 -#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 -#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 -#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 -#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 -#define MX1_PAD_BT13__BT13 0x53 0x004 -#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 -#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 -#define MX1_PAD_BT12__BT12 0x54 0x004 -#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 -#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 -#define MX1_PAD_BT11__BT11 0x55 0x004 -#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 -#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 -#define MX1_PAD_BT10__BT10 0x56 0x004 -#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 -#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 -#define MX1_PAD_BT9__BT9 0x57 0x004 -#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 -#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 -#define MX1_PAD_BT8__BT8 0x58 0x004 -#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 -#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 -#define MX1_PAD_BT8__UART3_RI 0x58 0x016 -#define MX1_PAD_BT7__BT7 0x59 0x004 -#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 -#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 -#define MX1_PAD_BT6__BT6 0x5a 0x004 -#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 -#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 -#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 -#define MX1_PAD_BT5__BT5 0x5b 0x000 -#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 -#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 -#define MX1_PAD_BT4__BT4 0x5c 0x000 -#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 -#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 -#define MX1_PAD_BT3__BT3 0x5d 0x000 -#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 -#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 -#define MX1_PAD_BT2__BT2 0x5e 0x004 -#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 -#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 -#define MX1_PAD_BT1__BT1 0x5f 0x000 -#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 -#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 -#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 -#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 -#define MX1_PAD_REV__REV 0x67 0x004 -#define MX1_PAD_REV__UART2_DTR 0x67 0x001 -#define MX1_PAD_REV__GPIO4_7 0x67 0x032 -#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 -#define MX1_PAD_CLS__CLS 0x68 0x004 -#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 -#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 -#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 -#define MX1_PAD_PS__PS 0x69 0x004 -#define MX1_PAD_PS__UART2_RI 0x69 0x005 -#define MX1_PAD_PS__GPIO4_9 0x69 0x032 -#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 -#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 -#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 -#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 -#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 -#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 -#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 -#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 -#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 -#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 -#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 -#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 -#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 -#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 -#define MX1_PAD_LD0__LD0 0x6f 0x004 -#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 -#define MX1_PAD_LD1__LD1 0x70 0x004 -#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 -#define MX1_PAD_LD2__LD2 0x71 0x004 -#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 -#define MX1_PAD_LD3__LD3 0x72 0x004 -#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 -#define MX1_PAD_LD4__LD4 0x73 0x004 -#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 -#define MX1_PAD_LD5__LD5 0x74 0x004 -#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 -#define MX1_PAD_LD6__LD6 0x75 0x004 -#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 -#define MX1_PAD_LD7__LD7 0x76 0x004 -#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 -#define MX1_PAD_LD8__LD8 0x77 0x004 -#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 -#define MX1_PAD_LD9__LD9 0x78 0x004 -#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 -#define MX1_PAD_LD10__LD10 0x79 0x004 -#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 -#define MX1_PAD_LD11__LD11 0x7a 0x004 -#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 -#define MX1_PAD_LD12__LD12 0x7b 0x004 -#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 -#define MX1_PAD_LD13__LD13 0x7c 0x004 -#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 -#define MX1_PAD_LD14__LD14 0x7d 0x004 -#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 -#define MX1_PAD_LD15__LD15 0x7e 0x004 -#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 -#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 -#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 -#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 - -#endif diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi deleted file mode 100644 index e312f1e74e2f..000000000000 --- a/arch/arm/boot/dts/imx1.dtsi +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (C) 2014 Alexander Shiyan - -#include "imx1-pinfunc.h" - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &cspi1; - spi1 = &cspi2; - }; - - aitc: aitc-interrupt-controller@223000 { - compatible = "fsl,imx1-aitc", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x00223000 0x1000>; - }; - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "arm,arm920t"; - operating-points = <200000 1900000>; - clock-latency = <62500>; - clocks = <&clks IMX1_CLK_MCU>; - voltage-tolerance = <5>; - }; - }; - - clocks { - clk32 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&aitc>; - ranges; - - aipi@200000 { - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00200000 0x10000>; - ranges; - - gpt1: timer@202000 { - compatible = "fsl,imx1-gpt"; - reg = <0x00202000 0x1000>; - interrupts = <59>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@203000 { - compatible = "fsl,imx1-gpt"; - reg = <0x00203000 0x1000>; - interrupts = <58>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - fb: fb@205000 { - compatible = "fsl,imx1-fb"; - reg = <0x00205000 0x1000>; - interrupts = <14>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER2>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - uart1: serial@206000 { - compatible = "fsl,imx1-uart"; - reg = <0x00206000 0x1000>; - interrupts = <30 29 26>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@207000 { - compatible = "fsl,imx1-uart"; - reg = <0x00207000 0x1000>; - interrupts = <24 23 20>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm: pwm@208000 { - #pwm-cells = <3>; - compatible = "fsl,imx1-pwm"; - reg = <0x00208000 0x1000>; - interrupts = <34>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - dma: dma@209000 { - compatible = "fsl,imx1-dma"; - reg = <0x00209000 0x1000>; - interrupts = <61 60>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_DMA_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <1>; - }; - - uart3: serial@20a000 { - compatible = "fsl,imx1-uart"; - reg = <0x0020a000 0x1000>; - interrupts = <54 4 1>; - clocks = <&clks IMX1_CLK_UART3_GATE>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - aipi@210000 { - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00210000 0x10000>; - ranges; - - cspi1: spi@213000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-cspi"; - reg = <0x00213000 0x1000>; - interrupts = <41>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c: i2c@217000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-i2c"; - reg = <0x00217000 0x1000>; - interrupts = <39>; - clocks = <&clks IMX1_CLK_HCLK>; - status = "disabled"; - }; - - cspi2: spi@219000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-cspi"; - reg = <0x00219000 0x1000>; - interrupts = <40>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - clks: ccm@21b000 { - compatible = "fsl,imx1-ccm"; - reg = <0x0021b000 0x1000>; - #clock-cells = <1>; - }; - - iomuxc: iomuxc@21c000 { - compatible = "fsl,imx1-iomuxc"; - reg = <0x0021c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@21c000 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c000 0x100>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@21c100 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c100 0x100>; - interrupts = <12>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@21c200 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c200 0x100>; - interrupts = <13>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@21c300 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c300 0x100>; - interrupts = <62>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - }; - - weim: weim@220000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx1-weim"; - reg = <0x00220000 0x1000>; - clocks = <&clks IMX1_CLK_DUMMY>; - ranges = < - 0 0 0x10000000 0x02000000 - 1 0 0x12000000 0x01000000 - 2 0 0x13000000 0x01000000 - 3 0 0x14000000 0x01000000 - 4 0 0x15000000 0x01000000 - 5 0 0x16000000 0x01000000 - >; - status = "disabled"; - }; - - esram: esram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x20000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts deleted file mode 100644 index 3b609d987d88..000000000000 --- a/arch/arm/boot/dts/imx23-evk.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Freescale i.MX23 Evaluation Kit"; - compatible = "fsl,imx23-evk", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 18 0>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_LCD_RESET__GPIO_1_18 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - }; - }; - - backlight_display: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts deleted file mode 100644 index 0729e72f2283..000000000000 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -/dts-v1/; -#include -#include "imx23.dtsi" - -/ { - model = "i.MX23 Olinuxino Low Cost Board"; - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; - bus-width = <4>; - broken-cd; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_ALE__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio2_1: led_gpio2_1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__GPIO_2_1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - ssp1: spi@80034000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_b>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "host"; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ - gpio = <&gpio0 17 0>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio2_1>; - - user { - label = "green"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h deleted file mode 100644 index 468c079f3c2b..000000000000 --- a/arch/arm/boot/dts/imx23-pinfunc.h +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Header providing constants for i.MX23 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - */ - -#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ -#define __DT_BINDINGS_MX23_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -#define MX23_PAD_LCD_D00__LCD_D00 0x1000 -#define MX23_PAD_LCD_D01__LCD_D01 0x1010 -#define MX23_PAD_LCD_D02__LCD_D02 0x1020 -#define MX23_PAD_LCD_D03__LCD_D03 0x1030 -#define MX23_PAD_LCD_D04__LCD_D04 0x1040 -#define MX23_PAD_LCD_D05__LCD_D05 0x1050 -#define MX23_PAD_LCD_D06__LCD_D06 0x1060 -#define MX23_PAD_LCD_D07__LCD_D07 0x1070 -#define MX23_PAD_LCD_D08__LCD_D08 0x1080 -#define MX23_PAD_LCD_D09__LCD_D09 0x1090 -#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX23_PAD_LCD_D16__LCD_D16 0x1100 -#define MX23_PAD_LCD_D17__LCD_D17 0x1110 -#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -#define MX23_PAD_LCD_RS__LCD_RS 0x1130 -#define MX23_PAD_LCD_WR__LCD_WR 0x1140 -#define MX23_PAD_LCD_CS__LCD_CS 0x1150 -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -#define MX23_PAD_PWM0__PWM0 0x11a0 -#define MX23_PAD_PWM1__PWM1 0x11b0 -#define MX23_PAD_PWM2__PWM2 0x11c0 -#define MX23_PAD_PWM3__PWM3 0x11d0 -#define MX23_PAD_PWM4__PWM4 0x11e0 -#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -#define MX23_PAD_ROTARYA__ROTARYA 0x2070 -#define MX23_PAD_ROTARYB__ROTARYB 0x2080 -#define MX23_PAD_EMI_A00__EMI_A00 0x2090 -#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 -#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 -#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 -#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 -#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 -#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 -#define MX23_PAD_EMI_A07__EMI_A07 0x2100 -#define MX23_PAD_EMI_A08__EMI_A08 0x2110 -#define MX23_PAD_EMI_A09__EMI_A09 0x2120 -#define MX23_PAD_EMI_A10__EMI_A10 0x2130 -#define MX23_PAD_EMI_A11__EMI_A11 0x2140 -#define MX23_PAD_EMI_A12__EMI_A12 0x2150 -#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -#define MX23_PAD_EMI_D00__EMI_D00 0x3000 -#define MX23_PAD_EMI_D01__EMI_D01 0x3010 -#define MX23_PAD_EMI_D02__EMI_D02 0x3020 -#define MX23_PAD_EMI_D03__EMI_D03 0x3030 -#define MX23_PAD_EMI_D04__EMI_D04 0x3040 -#define MX23_PAD_EMI_D05__EMI_D05 0x3050 -#define MX23_PAD_EMI_D06__EMI_D06 0x3060 -#define MX23_PAD_EMI_D07__EMI_D07 0x3070 -#define MX23_PAD_EMI_D08__EMI_D08 0x3080 -#define MX23_PAD_EMI_D09__EMI_D09 0x3090 -#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 -#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 -#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 -#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 -#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 -#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 -#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 -#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 -#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 -#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 -#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 -#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 -#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 -#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 -#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 -#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 -#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 -#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 -#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 -#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 -#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 -#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 -#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 -#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 -#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 -#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 -#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 -#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 -#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -#define MX23_PAD_PWM0__ROTARYA 0x11a1 -#define MX23_PAD_PWM1__ROTARYB 0x11b1 -#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 -#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -#define MX23_PAD_PWM0__DUART_RX 0x11a2 -#define MX23_PAD_PWM1__DUART_TX 0x11b2 -#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 -#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 -#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -#define MX23_PAD_ROTARYA__SPDIF 0x2072 -#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 -#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 -#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 -#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 -#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 -#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 - -#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts deleted file mode 100644 index 46057d9bf555..000000000000 --- a/arch/arm/boot/dts/imx23-sansa.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (C) 2013-2016 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include -#include "imx23.dtsi" - -/ { - model = "SanDisk Sansa Fuze+"; - compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - cd-inverted; - status = "okay"; - }; - - ssp1: spi@80034000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_8bit_pins_a>; - bus-width = <8>; - vmmc-supply = <®_vddio_sd1>; - non-removable; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D08__GPIO_0_8 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_AUART1_RTS__GPIO_0_27 - MX23_PAD_AUART1_CTS__GPIO_0_26 - MX23_PAD_I2C_SCL__I2C_SCL - MX23_PAD_I2C_SDA__I2C_SDA - MX23_PAD_LCD_DOTCK__GPIO_1_22 - MX23_PAD_LCD_HSYNC__GPIO_1_24 - MX23_PAD_PWM3__GPIO_1_29 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "peripheral"; - status = "okay"; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 8 0>; - }; - - reg_vddio_sd1: regulator-vddio-sd1 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - - reg_vdd_touchpad: regulator-vdd-touchpad0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-touchpad0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - reg_vdd_tuner: regulator-vdd-tuner0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-tuner0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 29 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c-0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = < - &gpio1 24 0 /* SDA */ - &gpio1 22 0 /* SCL */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; - - i2c-1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = < - &gpio0 31 0 /* SDA */ - &gpio0 30 0 /* SCL */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - - touch: touch@20 { - compatible = "synaptics,synaptics_i2c"; - reg = <0x20>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts deleted file mode 100644 index da4b88f32eaa..000000000000 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Freescale STMP378x Development Board"; - compatible = "fsl,stmp378x-devb", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_vddio_sd0: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts deleted file mode 100644 index b1d8210f3ecc..000000000000 --- a/arch/arm/boot/dts/imx23-xfi3.dts +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (C) 2013-2016 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Creative ZEN X-Fi3"; - compatible = "creative,x-fi3", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - cd-inverted; - status = "okay"; - }; - - ssp1: spi@80034000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_4bit_pins_a>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - key_pins_a: keys@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_ROTARYA__GPIO_2_7 - MX23_PAD_ROTARYB__GPIO_2_8 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - }; - }; - - apbx@80040000 { - i2c: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_a>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart1: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "peripheral"; - status = "okay"; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 7 0>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - key-voldown { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio2 7 0>; - debounce-interval = <20>; - }; - - key-volup { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio2 8 0>; - debounce-interval = <20>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi deleted file mode 100644 index a3668a0827fc..000000000000 --- a/arch/arm/boot/dts/imx23.dtsi +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -#include "imx23-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&icoll>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - serial0 = &auart0; - serial1 = &auart1; - spi0 = &ssp0; - spi1 = &ssp1; - usbphy0 = &usbphy0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - apb@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x80000>; - ranges; - - apbh@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x40000>; - ranges; - - icoll: interrupt-controller@80000000 { - compatible = "fsl,imx23-icoll", "fsl,icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80000000 0x2000>; - }; - - dma_apbh: dma-controller@80004000 { - compatible = "fsl,imx23-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <0 14 20 0 - 13 13 13 13>; - #dma-cells = <1>; - dma-channels = <8>; - clocks = <&clks 15>; - }; - - ecc@80008000 { - reg = <0x80008000 0x2000>; - status = "disabled"; - }; - - nand-controller@8000c000 { - compatible = "fsl,imx23-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <56>; - interrupt-names = "bch"; - clocks = <&clks 34>; - clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp0: spi@80010000 { - reg = <0x80010000 0x2000>; - interrupts = <15>; - clocks = <&clks 33>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - etm@80014000 { - reg = <0x80014000 0x2000>; - status = "disabled"; - }; - - pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <0>; - interrupts = <16>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <1>; - interrupts = <17>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <2>; - interrupts = <18>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - duart_pins_a: duart@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM0__DUART_RX - MX23_PAD_PWM1__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_pins_a: auart0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_AUART1_RX__AUART1_RX - MX23_PAD_AUART1_TX__AUART1_TX - MX23_PAD_AUART1_CTS__AUART1_CTS - MX23_PAD_AUART1_RTS__AUART1_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_2pins_a: auart0-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__AUART1_TX - MX23_PAD_I2C_SDA__AUART1_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_2pins_a: auart1-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D14__AUART2_RX - MX23_PAD_GPMI_D15__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_a: gpmi-nand@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__GPMI_D00 - MX23_PAD_GPMI_D01__GPMI_D01 - MX23_PAD_GPMI_D02__GPMI_D02 - MX23_PAD_GPMI_D03__GPMI_D03 - MX23_PAD_GPMI_D04__GPMI_D04 - MX23_PAD_GPMI_D05__GPMI_D05 - MX23_PAD_GPMI_D06__GPMI_D06 - MX23_PAD_GPMI_D07__GPMI_D07 - MX23_PAD_GPMI_CLE__GPMI_CLE - MX23_PAD_GPMI_ALE__GPMI_ALE - MX23_PAD_GPMI_RDY0__GPMI_RDY0 - MX23_PAD_GPMI_RDY1__GPMI_RDY1 - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - MX23_PAD_GPMI_CE1N__GPMI_CE1N - MX23_PAD_GPMI_CE0N__GPMI_CE0N - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_fixup: gpmi-pins-fixup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - >; - fsl,drive-strength = ; - }; - - mmc0_4bit_pins_a: mmc0-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_GPMI_D08__SSP1_DATA4 - MX23_PAD_GPMI_D09__SSP1_DATA5 - MX23_PAD_GPMI_D10__SSP1_DATA6 - MX23_PAD_GPMI_D11__SSP1_DATA7 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_pins_fixup: mmc0-pins-fixup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,pull-up = ; - }; - - mmc0_sck_cfg: mmc0-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,pull-up = ; - }; - - mmc1_4bit_pins_a: mmc1-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D01__SSP2_DATA1 - MX23_PAD_GPMI_D02__SSP2_DATA2 - MX23_PAD_GPMI_D03__SSP2_DATA3 - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_WRN__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc1_8bit_pins_a: mmc1-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D01__SSP2_DATA1 - MX23_PAD_GPMI_D02__SSP2_DATA2 - MX23_PAD_GPMI_D03__SSP2_DATA3 - MX23_PAD_GPMI_D04__SSP2_DATA4 - MX23_PAD_GPMI_D05__SSP2_DATA5 - MX23_PAD_GPMI_D06__SSP2_DATA6 - MX23_PAD_GPMI_D07__SSP2_DATA7 - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_WRN__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm2_pins_a: pwm2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM2__PWM2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_24bit_pins_a: lcdif-24bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_LCD_D00__LCD_D00 - MX23_PAD_LCD_D01__LCD_D01 - MX23_PAD_LCD_D02__LCD_D02 - MX23_PAD_LCD_D03__LCD_D03 - MX23_PAD_LCD_D04__LCD_D04 - MX23_PAD_LCD_D05__LCD_D05 - MX23_PAD_LCD_D06__LCD_D06 - MX23_PAD_LCD_D07__LCD_D07 - MX23_PAD_LCD_D08__LCD_D08 - MX23_PAD_LCD_D09__LCD_D09 - MX23_PAD_LCD_D10__LCD_D10 - MX23_PAD_LCD_D11__LCD_D11 - MX23_PAD_LCD_D12__LCD_D12 - MX23_PAD_LCD_D13__LCD_D13 - MX23_PAD_LCD_D14__LCD_D14 - MX23_PAD_LCD_D15__LCD_D15 - MX23_PAD_LCD_D16__LCD_D16 - MX23_PAD_LCD_D17__LCD_D17 - MX23_PAD_GPMI_D08__LCD_D18 - MX23_PAD_GPMI_D09__LCD_D19 - MX23_PAD_GPMI_D10__LCD_D20 - MX23_PAD_GPMI_D11__LCD_D21 - MX23_PAD_GPMI_D12__LCD_D22 - MX23_PAD_GPMI_D13__LCD_D23 - MX23_PAD_LCD_DOTCK__LCD_DOTCK - MX23_PAD_LCD_ENABLE__LCD_ENABLE - MX23_PAD_LCD_HSYNC__LCD_HSYNC - MX23_PAD_LCD_VSYNC__LCD_VSYNC - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_a: spi2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_WRN__SSP2_SCK - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D03__SSP2_DATA3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_a: i2c@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__I2C_SCL - MX23_PAD_I2C_SDA__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_b: i2c@1 { - reg = <1>; - fsl,pinmux-ids = < - MX23_PAD_LCD_ENABLE__I2C_SCL - MX23_PAD_LCD_HSYNC__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_c: i2c@2 { - reg = <2>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA1__I2C_SCL - MX23_PAD_SSP1_DATA2__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - digctl@8001c000 { - compatible = "fsl,imx23-digctl"; - reg = <0x8001c000 2000>; - status = "disabled"; - }; - - emi@80020000 { - reg = <0x80020000 0x2000>; - status = "disabled"; - }; - - dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx23-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <7 5 9 26 - 19 0 25 23 - 60 58 9 0 - 0 0 0 0>; - interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", - "saif0", "empty", "auart0-rx", "auart0-tx", - "auart1-rx", "auart1-tx", "saif1", "empty", - "empty", "empty", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 16>; - }; - - dcp: crypto@80028000 { - compatible = "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <53 54>; - status = "okay"; - }; - - pxp@8002a000 { - reg = <0x8002a000 0x2000>; - status = "disabled"; - }; - - efuse@8002c000 { - compatible = "fsl,imx23-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 15>; - }; - - axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; - status = "disabled"; - }; - - lcdif@80030000 { - compatible = "fsl,imx23-lcdif"; - reg = <0x80030000 2000>; - interrupts = <46 45>; - clocks = <&clks 38>; - status = "disabled"; - }; - - ssp1: spi@80034000 { - reg = <0x80034000 0x2000>; - interrupts = <2>; - clocks = <&clks 33>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - tvenc@80038000 { - reg = <0x80038000 0x2000>; - status = "disabled"; - }; - }; - - apbx@80040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80040000 0x40000>; - ranges; - - clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; - }; - - saif0: saif@80042000 { - reg = <0x80042000 0x2000>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - power@80044000 { - reg = <0x80044000 0x2000>; - status = "disabled"; - }; - - saif1: saif@80046000 { - reg = <0x80046000 0x2000>; - dmas = <&dma_apbx 10>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - audio-out@80048000 { - reg = <0x80048000 0x2000>; - dmas = <&dma_apbx 1>; - dma-names = "tx"; - status = "disabled"; - }; - - audio-in@8004c000 { - reg = <0x8004c000 0x2000>; - dmas = <&dma_apbx 0>; - dma-names = "rx"; - status = "disabled"; - }; - - lradc: lradc@80050000 { - compatible = "fsl,imx23-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <36 37 38 39 40 41 42 43 44>; - status = "disabled"; - clocks = <&clks 26>; - #io-channel-cells = <1>; - }; - - spdif@80054000 { - reg = <0x80054000 2000>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; - status = "disabled"; - }; - - i2c: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-i2c"; - reg = <0x80058000 0x2000>; - interrupts = <27>; - clock-frequency = <100000>; - dmas = <&dma_apbx 3>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - rtc@8005c000 { - compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x8005c000 0x2000>; - interrupts = <22>; - }; - - pwm: pwm@80064000 { - compatible = "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - clocks = <&clks 30>; - #pwm-cells = <2>; - fsl,pwm-number = <5>; - status = "disabled"; - }; - - timrot@80068000 { - compatible = "fsl,imx23-timrot", "fsl,timrot"; - reg = <0x80068000 0x2000>; - interrupts = <28 29 30 31>; - clocks = <&clks 28>; - }; - - auart0: serial@8006c000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <24>; - clocks = <&clks 32>; - dmas = <&dma_apbx 6>, <&dma_apbx 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - auart1: serial@8006e000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006e000 0x2000>; - interrupts = <59>; - clocks = <&clks 32>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - duart: serial@80070000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80070000 0x2000>; - interrupts = <0>; - clocks = <&clks 32>, <&clks 16>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; - }; - - usbphy0: usbphy@8007c000 { - compatible = "fsl,imx23-usbphy"; - reg = <0x8007c000 0x2000>; - clocks = <&clks 41>; - status = "disabled"; - }; - }; - }; - - ahb@80080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80080000 0x80000>; - ranges; - - usb0: usb@80080000 { - compatible = "fsl,imx23-usb", "fsl,imx27-usb"; - reg = <0x80080000 0x40000>; - interrupts = <11>; - fsl,usbphy = <&usbphy0>; - clocks = <&clks 40>; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&lradc 8>; - }; -}; diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi deleted file mode 100644 index 0703f62d10d1..000000000000 --- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25.dtsi" - -/ { - model = "Eukrea CPUIMX25"; - compatible = "eukrea,cpuimx25", "fsl,imx25"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; /* 64M */ - }; -}; - -&fec { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&iomuxc { - imx25-eukrea-cpuimx25 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts deleted file mode 100644 index 7d4301b22b90..000000000000 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - cmo_qvga: display { - model = "CMO-QVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xcad08b80>; - bus-width = <18>; - display-timings { - native-mode = <&qvga_timings>; - qvga_timings: 320x240 { - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <30>; - hfront-porch = <38>; - vback-porch = <20>; - vfront-porch = <3>; - hsync-len = <15>; - vsync-len = <4>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_lcd_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&iomuxc { - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = ; - }; - }; -}; - -&lcdc { - display = <&cmo_qvga>; - fsl,lpccr = <0x00a903ff>; - lcd-supply = <®_lcd_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts deleted file mode 100644 index 80a7f96de4c6..000000000000 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - dvi_svga: display { - model = "DVI-SVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - display-timings { - native-mode = <&dvi_svga_timings>; - dvi_svga_timings: 800x600 { - clock-frequency = <40000000>; - hactive = <800>; - vactive = <600>; - hback-porch = <75>; - hfront-porch = <75>; - vback-porch = <7>; - vfront-porch = <75>; - hsync-len = <7>; - vsync-len = <7>; - }; - }; - }; -}; - -&lcdc { - display = <&dvi_svga>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts deleted file mode 100644 index 24027a1fb46d..000000000000 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - dvi_vga: display { - model = "DVI-VGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - display-timings { - native-mode = <&dvi_vga_timings>; - dvi_vga_timings: 640x480 { - clock-frequency = <31250000>; - hactive = <640>; - vactive = <480>; - hback-porch = <100>; - hfront-porch = <100>; - vback-porch = <7>; - vfront-porch = <100>; - hsync-len = <7>; - vsync-len = <7>; - }; - }; - }; -}; - -&lcdc { - display = <&dvi_vga>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts deleted file mode 100644 index c7207ea437c4..000000000000 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -/dts-v1/; - -#include -#include -#include "imx25-eukrea-cpuimx25.dtsi" - -/ { - model = "Eukrea MBIMXSD25"; - compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - button { - label = "BP1"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx25-eukrea-tlv320aic23"; - ssi-controller = <&ssi1>; - fsl,mux-int-port = <1>; - fsl,mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx25-eukrea-mbimxsd25-baseboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 - MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 - MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 - MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 - MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 - MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 - MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 - MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 - MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = ; - }; - - pinctrl_gpioled: gpioledgrp { - fsl,pins = ; - }; - - pinctrl_lcdc: lcdcgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0x1 - MX25_PAD_LD1__LD1 0x1 - MX25_PAD_LD2__LD2 0x1 - MX25_PAD_LD3__LD3 0x1 - MX25_PAD_LD4__LD4 0x1 - MX25_PAD_LD5__LD5 0x1 - MX25_PAD_LD6__LD6 0x1 - MX25_PAD_LD7__LD7 0x1 - MX25_PAD_LD8__LD8 0x1 - MX25_PAD_LD9__LD9 0x1 - MX25_PAD_LD10__LD10 0x1 - MX25_PAD_LD11__LD11 0x1 - MX25_PAD_LD12__LD12 0x1 - MX25_PAD_LD13__LD13 0x1 - MX25_PAD_LD14__LD14 0x1 - MX25_PAD_LD15__LD15 0x1 - MX25_PAD_GPIO_E__LD16 0x1 - MX25_PAD_GPIO_F__LD17 0x1 - MX25_PAD_HSYNC__HSYNC 0x80000000 - MX25_PAD_VSYNC__VSYNC 0x80000000 - MX25_PAD_LSCLK__LSCLK 0x80000000 - MX25_PAD_OE_ACD__OE_ACD 0x80000000 - MX25_PAD_CONTRAST__CONTRAST 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 - MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 - MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 - MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 - >; - }; - }; -}; - -&ssi1 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - status = "okay"; -}; - -&usbotg { - external-vbus-divider; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts deleted file mode 100644 index 0950eb66d3d9..000000000000 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Pengutronix - */ - -/dts-v1/; -#include "imx25.dtsi" - -/ { - model = "Ka-Ro TX25"; - compatible = "karo,imx25-tx25", "fsl,imx25"; - - chosen { - stdout-path = &uart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_phy: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 0>; - enable-active-high; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x02000000 0x90000000 0x02000000>; - }; -}; - -&iomuxc { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 - MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 - MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ - MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX25_PAD_NF_CE0__NF_CE0 0x80000000 - MX25_PAD_NFWE_B__NFWE_B 0x80000000 - MX25_PAD_NFRE_B__NFRE_B 0x80000000 - MX25_PAD_NFALE__NFALE 0x80000000 - MX25_PAD_NFCLE__NFCLE 0x80000000 - MX25_PAD_NFWP_B__NFWP_B 0x80000000 - MX25_PAD_NFRB__NFRB 0x80000000 - MX25_PAD_D7__D7 0x80000000 - MX25_PAD_D6__D6 0x80000000 - MX25_PAD_D5__D5 0x80000000 - MX25_PAD_D4__D4 0x80000000 - MX25_PAD_D3__D3 0x80000000 - MX25_PAD_D2__D2 0x80000000 - MX25_PAD_D1__D1 0x80000000 - MX25_PAD_D0__D0 0x80000000 - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - phy-mode = "rmii"; - phy-supply = <®_fec_phy>; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-bus-width = <8>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts deleted file mode 100644 index fb66884d8a2f..000000000000 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Freescale Semiconductor, Inc. - -/dts-v1/; -#include -#include -#include "imx25.dtsi" - -/ { - model = "Freescale i.MX25 Product Development Kit"; - compatible = "fsl,imx25-pdk", "fsl,imx25"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 3 0>; - enable-active-high; - }; - - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 6 0>; - }; - }; - - sound { - compatible = "fsl,imx25-pdk-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx25-pdk-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - wvga: display { - model = "CLAA057VC01CW"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - display-timings { - native-mode = <&wvga_timings>; - wvga_timings: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <45>; - hfront-porch = <114>; - hsync-len = <1>; - vback-porch = <33>; - vfront-porch = <11>; - vsync-len = <1>; - clock-frequency = <25200000>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 129>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - imx25-pdk { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_RW__AUD4_TXFS 0xe0 - MX25_PAD_OE__AUD4_TXC 0xe0 - MX25_PAD_EB0__AUD4_TXD 0xe0 - MX25_PAD_EB1__AUD4_RXD 0xe0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX25_PAD_GPIO_A__CAN1_TX 0x0 - MX25_PAD_GPIO_B__CAN1_RX 0x0 - MX25_PAD_D14__GPIO_4_6 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - MX25_PAD_A14__GPIO_2_0 0x80000000 - MX25_PAD_A15__GPIO_2_1 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - MX25_PAD_A17__GPIO_2_3 0x80000000 - MX25_PAD_D12__GPIO_4_8 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 - MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 - MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 - MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 - MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 - MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 - MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 - MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0xe0 - MX25_PAD_LD1__LD1 0xe0 - MX25_PAD_LD2__LD2 0xe0 - MX25_PAD_LD3__LD3 0xe0 - MX25_PAD_LD4__LD4 0xe0 - MX25_PAD_LD5__LD5 0xe0 - MX25_PAD_LD6__LD6 0xe0 - MX25_PAD_LD7__LD7 0xe0 - MX25_PAD_LD8__LD8 0xe0 - MX25_PAD_LD9__LD9 0xe0 - MX25_PAD_LD10__LD10 0xe0 - MX25_PAD_LD11__LD11 0xe0 - MX25_PAD_LD12__LD12 0xe0 - MX25_PAD_LD13__LD13 0xe0 - MX25_PAD_LD14__LD14 0xe0 - MX25_PAD_LD15__LD15 0xe0 - MX25_PAD_GPIO_E__LD16 0xe0 - MX25_PAD_GPIO_F__LD17 0xe0 - MX25_PAD_HSYNC__HSYNC 0xe0 - MX25_PAD_VSYNC__VSYNC 0xe0 - MX25_PAD_LSCLK__LSCLK 0xe0 - MX25_PAD_OE_ACD__OE_ACD 0xe0 - MX25_PAD_CONTRAST__CONTRAST 0xe0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; - }; -}; - -&lcdc { - display = <&wvga>; - fsl,lpccr = <0x00a903ff>; - fsl,lscr1 = <0x00120300>; - fsl,dmacr = <0x00020010>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; -}; - -&nfc { - nand-on-flash-bbt; - status = "okay"; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) - MATRIX_KEY(0x0, 0x1, KEY_DOWN) - MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) - MATRIX_KEY(0x0, 0x3, KEY_HOME) - MATRIX_KEY(0x1, 0x0, KEY_RIGHT) - MATRIX_KEY(0x1, 0x1, KEY_LEFT) - MATRIX_KEY(0x1, 0x2, KEY_ENTER) - MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) - MATRIX_KEY(0x2, 0x0, KEY_F6) - MATRIX_KEY(0x2, 0x1, KEY_F8) - MATRIX_KEY(0x2, 0x2, KEY_F9) - MATRIX_KEY(0x2, 0x3, KEY_F10) - MATRIX_KEY(0x3, 0x0, KEY_F1) - MATRIX_KEY(0x3, 0x1, KEY_F2) - MATRIX_KEY(0x3, 0x2, KEY_F3) - MATRIX_KEY(0x3, 0x2, KEY_POWER) - >; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&tsc { - status = "okay"; -}; - -&tscadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - status = "okay"; -}; - -&usbotg { - external-vbus-divider; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h deleted file mode 100644 index 908caf810351..000000000000 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ /dev/null @@ -1,652 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Eukréa Electromatique - * Based on imx35-pinfunc.h in the same directory Which is: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX25_PINFUNC_H -#define __DTS_IMX25_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 -#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 - -#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 -#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 -#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 - -#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 -#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 -#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 -#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 - -#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 -#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000 -#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000 -#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000 - -#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000 -#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000 -#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000 -#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000 - -#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000 -#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000 -#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000 -#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000 - -#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000 -#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000 -#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000 -#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000 - -#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000 -#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000 -#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000 -#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000 - -#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000 -#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000 -#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000 -#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000 - -#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000 -#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000 -#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000 -#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000 - -#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000 -#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000 -#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000 -#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 - -#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000 -#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000 -#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000 -#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000 - -#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000 -#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000 -#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000 -#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000 - -#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000 -#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000 -#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000 - -#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 -#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 -#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 -#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000 - -#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 -#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 -#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 -#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000 - -#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 -#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 -#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000 - -#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 -#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 -#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 -#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 - -#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000 -#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 -#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 -#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 -#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000 - -#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 -#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 -#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 -#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 -#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 - -#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 -#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000 -#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 - -#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 -#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 -#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 -#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000 - -#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 -#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 -#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 -#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000 - -#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 -#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 - -#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000 -#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000 -#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000 - -#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000 -#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000 - -#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 -#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 -#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 -#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 - -#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 -#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 -#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 -#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 - -#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 -#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 -#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 -#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 - -#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 -#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 -#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 - -#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 -#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 -#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000 - -#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 -#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 -#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 - -#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 -#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 -#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 - -#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 -#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 -#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 - -#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 -#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 - -#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 -#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 - -#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 -#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 - -#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 -#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 - -#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 -#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 - -#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 -#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 - -#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 -#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 - -#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 -#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 - -#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000 -#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000 -#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000 - -#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000 -#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000 -#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000 - -#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000 -#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000 - -#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000 -#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000 - -#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000 -#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000 - -#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000 -#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000 - -#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000 -#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000 - -#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000 -#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000 - -#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 -#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 -#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 -/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ -#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000 - -#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 -#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 -#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 -#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 - -#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 -#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 -#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 - -#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 -#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 -#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 -#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 - -#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 -#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 -#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000 -#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 - -#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 -#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 -#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000 -#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 - -#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 -#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 -#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000 - -#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000 -#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 -#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001 - -#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000 -#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000 - -#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000 -#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000 - -#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000 -#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000 - -#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000 -#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 -#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 - -#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 -#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000 -#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 -#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 -#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 -#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 - -#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000 -#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000 -#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001 - -#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000 -#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 -#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 -#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001 - -#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 -#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 -#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000 -#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001 - -#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 -#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 -#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 -#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001 - -#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 -#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 -#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 -#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001 - -#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 -/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ -#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 -#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 -#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 -#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001 - -#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 -#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 -#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001 - -#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 -#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 -#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000 -#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000 - -#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000 -#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000 -#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000 -#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000 - -#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 -#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 -#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 -#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 - -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 -#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 -#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 -#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 - -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 -#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 -#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 -#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 - -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 -#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 -#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 -#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 - -#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 -#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000 - -#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000 -#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000 -#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 -#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000 - -#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 -#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 -#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000 - -#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000 -#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000 -#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000 - -#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 -#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 -#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000 -#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 -#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 - -#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000 -#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001 -#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 -#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 - -#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000 -#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000 - -#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000 -#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000 - -#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 -#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 -#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000 -#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 -#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 - -#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 -#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 -#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 -#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001 - -/* - * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the ESDHCn_CMD function doesn't enable the input path - * for this pin. - * This might have side effects for other hardware units that are connected to - * that pin and use the respective function as input. - */ -#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000 -#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 -#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 -#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 - -#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000 -#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 -#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 -#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 -#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001 -#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 -#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001 -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 -#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001 -#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 -#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 -#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002 -#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002 -#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001 -#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000 -#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 -#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000 -#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 -/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ -#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002 -#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 -#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 - -#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000 -#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001 -#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000 -#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000 -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001 -#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 -#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 -#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000 - -#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 -#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 -#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000 - -#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 -/* - * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, - * 01/2011) this is CAN1_TX but that's wrong. - */ -#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000 -#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000 -/* - * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, - * 01/2011) this is CAN1_RX but that's wrong. - */ -#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000 -#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000 -#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000 - -#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000 -#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000 -#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000 - -#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 - -#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 -#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 - -#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000 -#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 -#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 - -#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000 -#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 -#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 - -#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000 -#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 -#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 -#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 -#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000 -#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 -#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 -#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 - -#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000 -#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 -#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 -#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 - -#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000 -#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 -#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 -#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 -#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 - -#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000 -#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 -#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 -#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 - -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000 -#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000 -#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000 - -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 -#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 -#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 - -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 -#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001 -#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 - -#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 -#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001 -#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000 -#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000 - -#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000 -#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000 - -#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 -#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 - -#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 -#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 - -/* - * Compatibility defines for out-of-tree users. You should update if you make - * use of one of them. - */ -#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7 -#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6 -#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5 -#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4 -#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD -#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK -#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1 -#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD -#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK -#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0 -#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 -#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 -#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 -#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD -#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK -#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 -#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 -#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 -#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 - -#endif /* __DTS_IMX25_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi deleted file mode 100644 index 5f90d72b840b..000000000000 --- a/arch/arm/boot/dts/imx25.dtsi +++ /dev/null @@ -1,637 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Sascha Hauer, Pengutronix - -#include -#include "imx25-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - pwm0 = &pwm1; - pwm1 = &pwm2; - pwm2 = &pwm3; - pwm3 = &pwm4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &spi1; - spi1 = &spi2; - spi2 = &spi3; - usb0 = &usbotg; - usb1 = &usbhost1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - asic: asic-interrupt-controller@68000000 { - compatible = "fsl,imx25-asic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x8000000>; - }; - - clocks { - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&asic>; - ranges; - - bus@43f00000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - aips1: bridge@43f00000 { - compatible = "fsl,imx25-aips"; - reg = <0x43f00000 0x4000>; - }; - - i2c1: i2c@43f80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f80000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <3>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f84000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <10>; - status = "disabled"; - }; - - can1: can@43f88000 { - compatible = "fsl,imx25-flexcan"; - reg = <0x43f88000 0x4000>; - interrupts = <43>; - clocks = <&clks 75>, <&clks 75>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: can@43f8c000 { - compatible = "fsl,imx25-flexcan"; - reg = <0x43f8c000 0x4000>; - interrupts = <44>; - clocks = <&clks 76>, <&clks 76>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 120>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - interrupts = <32>; - clocks = <&clks 121>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f98000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <4>; - status = "disabled"; - }; - - owire@43f9c000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x43f9c000 0x4000>; - clocks = <&clks 51>; - clock-names = ""; - interrupts = <2>; - status = "disabled"; - }; - - spi1: spi@43fa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x43fa4000 0x4000>; - clocks = <&clks 78>, <&clks 78>; - clock-names = "ipg", "per"; - interrupts = <14>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - clocks = <&clks 102>; - clock-names = ""; - interrupts = <24>; - status = "disabled"; - }; - - iomuxc: iomuxc@43fac000 { - compatible = "fsl,imx25-iomuxc"; - reg = <0x43fac000 0x4000>; - }; - - audmux: audmux@43fb0000 { - compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; - reg = <0x43fb0000 0x4000>; - status = "disabled"; - }; - }; - - spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - spi3: spi@50004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x50004000 0x4000>; - interrupts = <0>; - clocks = <&clks 80>, <&clks 80>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@50008000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x50008000 0x4000>; - interrupts = <5>; - clocks = <&clks 123>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <18>; - clocks = <&clks 122>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spi2: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x50010000 0x4000>; - clocks = <&clks 79>, <&clks 79>; - clock-names = "ipg", "per"; - interrupts = <13>; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <11>; - clocks = <&clks 118>; - clock-names = "ipg"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esai@50018000 { - reg = <0x50018000 0x4000>; - interrupts = <7>; - }; - - uart5: serial@5002c000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x5002c000 0x4000>; - interrupts = <40>; - clocks = <&clks 124>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - tscadc: tscadc@50030000 { - compatible = "fsl,imx25-tsadc"; - reg = <0x50030000 0xc>; - interrupts = <46>; - clocks = <&clks 119>; - clock-names = "ipg"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - adc: adc@50030800 { - compatible = "fsl,imx25-gcq"; - reg = <0x50030800 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tsc: tcq@50030400 { - compatible = "fsl,imx25-tcq"; - reg = <0x50030400 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <0>; - fsl,wires = <4>; - status = "disabled"; - }; - }; - - ssi1: ssi@50034000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; - reg = <0x50034000 0x4000>; - interrupts = <12>; - clocks = <&clks 117>; - clock-names = "ipg"; - dmas = <&sdma 28 1 0>, - <&sdma 29 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@50038000 { - compatible = "fsl,imx25-fec"; - reg = <0x50038000 0x4000>; - interrupts = <57>; - clocks = <&clks 88>, <&clks 65>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - }; - - bus@53f00000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - aips2: bridge@53f00000 { - compatible = "fsl,imx25-aips"; - reg = <0x53f00000 0x4000>; - }; - - clks: ccm@53f80000 { - compatible = "fsl,imx25-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; - }; - - gpt4: timer@53f84000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f84000 0x4000>; - clocks = <&clks 95>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <1>; - }; - - gpt3: timer@53f88000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f88000 0x4000>; - clocks = <&clks 94>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <29>; - }; - - gpt2: timer@53f8c000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f8c000 0x4000>; - clocks = <&clks 93>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <53>; - }; - - gpt1: timer@53f90000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - clocks = <&clks 92>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <54>; - }; - - epit1: timer@53f94000 { - compatible = "fsl,imx25-epit"; - reg = <0x53f94000 0x4000>; - clocks = <&clks 83>, <&clks 43>; - clock-names = "ipg", "per"; - interrupts = <28>; - }; - - epit2: timer@53f98000 { - compatible = "fsl,imx25-epit"; - reg = <0x53f98000 0x4000>; - clocks = <&clks 84>, <&clks 43>; - clock-names = "ipg", "per"; - interrupts = <27>; - }; - - gpio4: gpio@53f9c000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53f9c000 0x4000>; - interrupts = <23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm2: pwm@53fa0000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <3>; - reg = <0x53fa0000 0x4000>; - clocks = <&clks 106>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <36>; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <16>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm3: pwm@53fa8000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <3>; - reg = <0x53fa8000 0x4000>; - clocks = <&clks 107>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <41>; - }; - - scc: crypto@53fac000 { - compatible = "fsl,imx25-scc"; - reg = <0x53fac000 0x4000>; - clocks = <&clks 111>; - clock-names = "ipg"; - interrupts = <49>, <50>; - interrupt-names = "scm", "smn"; - }; - - rngb: rngb@53fb0000 { - compatible = "fsl,imx25-rngb"; - reg = <0x53fb0000 0x4000>; - clocks = <&clks 109>; - interrupts = <22>; - }; - - esdhc1: mmc@53fb4000 { - compatible = "fsl,imx25-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <9>; - clocks = <&clks 86>, <&clks 63>, <&clks 45>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: mmc@53fb8000 { - compatible = "fsl,imx25-esdhc"; - reg = <0x53fb8000 0x4000>; - interrupts = <8>; - clocks = <&clks 87>, <&clks 64>, <&clks 46>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - lcdc: lcdc@53fbc000 { - compatible = "fsl,imx25-fb", "fsl,imx21-fb"; - reg = <0x53fbc000 0x4000>; - interrupts = <39>; - clocks = <&clks 103>, <&clks 66>, <&clks 49>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - slcdc@53fc0000 { - reg = <0x53fc0000 0x4000>; - interrupts = <38>; - status = "disabled"; - }; - - pwm4: pwm@53fc8000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <3>; - reg = <0x53fc8000 0x4000>; - clocks = <&clks 108>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <42>; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: dma-controller@53fd4000 { - compatible = "fsl,imx25-sdma"; - reg = <0x53fd4000 0x4000>; - clocks = <&clks 112>, <&clks 68>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - interrupts = <34>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; - }; - - watchdog@53fdc000 { - compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 126>; - clock-names = ""; - interrupts = <55>; - }; - - pwm1: pwm@53fe0000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <3>; - reg = <0x53fe0000 0x4000>; - clocks = <&clks 105>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <26>; - }; - - iim: efuse@53ff0000 { - compatible = "fsl,imx25-iim", "fsl,imx27-iim"; - reg = <0x53ff0000 0x4000>; - interrupts = <19>; - clocks = <&clks 99>; - }; - - usbotg: usb@53ff4000 { - compatible = "fsl,imx25-usb", "fsl,imx27-usb"; - reg = <0x53ff4000 0x0200>; - interrupts = <37>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - phy_type = "utmi"; - dr_mode = "otg"; - status = "disabled"; - }; - - usbhost1: usb@53ff4400 { - compatible = "fsl,imx25-usb", "fsl,imx27-usb"; - reg = <0x53ff4400 0x0200>; - interrupts = <35>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - maximum-speed = "full-speed"; - phy_type = "serial"; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53ff4600 { - #index-cells = <1>; - compatible = "fsl,imx25-usbmisc"; - reg = <0x53ff4600 0x00f>; - }; - - dryice@53ffc000 { - compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; - reg = <0x53ffc000 0x4000>; - clocks = <&clks 81>; - clock-names = "ipg"; - interrupts = <25 56>; - }; - }; - - iram: sram@78000000 { - compatible = "mmio-sram"; - reg = <0x78000000 0x20000>; - }; - - emi@80000000 { - compatible = "fsl,emi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x3b002000>; - ranges; - - nfc: nand@bb000000 { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "fsl,imx25-nand"; - reg = <0xbb000000 0x2000>; - clocks = <&clks 50>; - clock-names = ""; - interrupts = <33>; - status = "disabled"; - }; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts deleted file mode 100644 index 745d5d409952..000000000000 --- a/arch/arm/boot/dts/imx27-apf27.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Philippe Reynes - * Copyright 2012 Armadeus Systems - * - * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Armadeus Systems APF27 module"; - compatible = "armadeus,imx27-apf27", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x04000000>; - }; -}; - -&clk_osc26m { - clock-frequency = <0>; -}; - -&iomuxc { - imx27-apf27 { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&nfc { - status = "okay"; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "env2"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "firmware"; - reg = <0x200000 0x80000>; - }; - - partition@280000 { - label = "dtb"; - reg = <0x280000 0x80000>; - }; - - partition@300000 { - label = "kernel"; - reg = <0x300000 0x500000>; - }; - - partition@800000 { - label = "rootfs"; - reg = <0x800000 0xf800000>; - }; -}; diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts deleted file mode 100644 index 6f1e8ce9e76e..000000000000 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Armadeus Systems - - */ - -/* APF27Dev is a docking board for the APF27 SOM */ -#include "imx27-apf27.dts" - -/ { - model = "Armadeus Systems APF27Dev docking/development board"; - compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; - - display: display { - model = "Chimei-LW700AT9003"; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xfae80083>; /* non-standard but required */ - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-key { - label = "user"; - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - linux,code = <276>; /* BTN_EXTRA */ - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user { - label = "Heartbeat"; - gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_max5821: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "max5821-reg"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; -}; - -&cspi1 { - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; - status = "okay"; - - adc@0 { - compatible = "maxim,max1027"; - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_max1027>; - spi-max-frequency = <10000000>; - }; -}; - -&cspi2 { - cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, - <&gpio4 27 GPIO_ACTIVE_LOW>, - <&gpio2 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; - status = "okay"; -}; - -&fb { - display = <&display>; - fsl,dmacr = <0x00020010>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb1>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - max5821@38 { - compatible = "maxim,max5821"; - reg = <0x38>; - vref-supply = <®_max5821>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - imx27-apf27dev { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - >; - }; - - pinctrl_cspi1_cs: cspi1csgrp { - fsl,pins = ; - }; - - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - >; - }; - - pinctrl_cspi2_cs: cspi2csgrp { - fsl,pins = < - MX27_PAD_CSI_D5__GPIO2_17 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = ; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = ; - }; - - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_max1027: max1027 { - fsl,pins = < - MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ - MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ - >; - }; - - pinctrl_pwm: pwmgrp { - fsl,pins = < - MX27_PAD_PWMO__PWMO 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; - - pinctrl_sdhc2_cd: sdhc2cdgrp { - fsl,pins = ; - }; - }; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm>; -}; diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi deleted file mode 100644 index 74110bbcd9d4..000000000000 --- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Eukrea CPUIMX27"; - compatible = "eukrea,cpuimx27", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x04000000>; - }; - - clk14745600: clk-uart { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <14745600>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0 0x00000000 0x04000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; - }; - - uart8250@3,200000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_1>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x200000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,400000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_2>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x400000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,800000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_3>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x800000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,1000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_4>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x1000000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; -}; - -&iomuxc { - imx27-eukrea-cpuimx27 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_owire: owiregrp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 - MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 - MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 - MX27_PAD_USBH1_FS__UART4_RTS 0x0 - >; - }; - - pinctrl_uart8250_1: uart82501grp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 - >; - }; - - pinctrl_uart8250_2: uart82502grp { - fsl,pins = < - MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 - >; - }; - - pinctrl_uart8250_3: uart82503grp { - fsl,pins = < - MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 - >; - }; - - pinctrl_uart8250_4: uart82504grp { - fsl,pins = < - MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts deleted file mode 100644 index 9c3ec82ec7e5..000000000000 --- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#include "imx27-eukrea-cpuimx27.dtsi" - -/ { - model = "Eukrea MBIMXSD27"; - compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; - - display0: CMO-QVGA { - model = "CMO-QVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfad08b80>; - - display-timings { - native-mode = <&timing0>; - timing0: 320x240 { - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <20>; - hsync-len = <30>; - hfront-porch = <38>; - vback-porch = <4>; - vsync-len = <3>; - vfront-porch = <15>; - }; - }; - }; - - backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds>; - - led1 { - label = "system::live"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "system::user"; - gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - reg_lcd: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdreg>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "LCD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - status = "okay"; - - ads7846@0 { - compatible = "ti,ads7846"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - reg = <0>; - interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; - spi-cpol; - spi-max-frequency = <1500000>; - ti,keep-vref-on; - }; -}; - -&fb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb>; - display = <&display0>; - lcd-supply = <®_lcd>; - fsl,dmacr = <0x00040060>; - fsl,lscr1 = <0x00120300>; - fsl,lpccr = <0x00a903ff>; - status = "okay"; -}; - -&i2c1 { - codec: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&kpp { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - >; - status = "okay"; -}; - -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - codec-handle = <&codec>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&iomuxc { - imx27-eukrea-cpuimx27-baseboard { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX27_PAD_PWMO__GPIO5_5 0x0 - >; - }; - - pinctrl_gpioleds: gpioledsgrp { - fsl,pins = < - MX27_PAD_PC_PWRON__GPIO6_16 0x0 - MX27_PAD_PC_CD2_B__GPIO6_19 0x0 - >; - }; - - pinctrl_imxfb: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_lcdreg: lcdreggrp { - fsl,pins = < - MX27_PAD_CLS__GPIO1_25 0x0 - >; - }; - - pinctrl_sdhc1: sdhc1grp { - fsl,pins = < - MX27_PAD_SD1_CLK__SD1_CLK 0x0 - MX27_PAD_SD1_CMD__SD1_CMD 0x0 - MX27_PAD_SD1_D0__SD1_D0 0x0 - MX27_PAD_SD1_D1__SD1_D1 0x0 - MX27_PAD_SD1_D2__SD1_D2 0x0 - MX27_PAD_SD1_D3__SD1_D3 0x0 - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 - MX27_PAD_SSI4_FS__SSI4_FS 0x0 - MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 - MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts deleted file mode 100644 index 35123b7cb6b3..000000000000 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Sascha Hauer, Pengutronix - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Freescale i.MX27 Product Development Kit"; - compatible = "fsl,imx27-pdk", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x08000000>; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - }; -}; - -&cspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2>; - cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13783@0 { - compatible = "fsl,mc13783"; - reg = <0>; - spi-cs-high; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio3>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - - regulators { - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { - regulator-always-on; - regulator-boot-on; - }; - - gpo3_reg: gpo3 { - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&fec { - phy-mode = "mii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&kpp { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - >; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - fsl,usbphy = <&usbphy0>; - phy_type = "ulpi"; - status = "okay"; -}; - -&iomuxc { - imx27-pdk { - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ - MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts deleted file mode 100644 index 188639738dc3..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Markus Pargmann, Pengutronix - */ - -#include "imx27-phytec-phycard-s-som.dtsi" - -/ { - model = "Phytec pca100 rapid development kit"; - compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; - - chosen { - stdout-path = &uart1; - }; - - display: display { - model = "Primeview-PD050VL1"; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xf0c88080>; /* non-standard but required */ - display-timings { - native-mode = <&timing0>; - timing0: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <112>; - hfront-porch = <36>; - hsync-len = <32>; - vback-porch = <33>; - vfront-porch = <33>; - vsync-len = <2>; - clock-frequency = <25000000>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&fb { - display = <&display>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - vcc-supply = <®_3v3>; - reg = <0x64>; - }; -}; - -&iomuxc { - imx27-phycard-s-rdk { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi deleted file mode 100644 index 303f920201c5..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar - * and Markus Pargmann, Pengutronix - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pca100"; - compatible = "phytec,imx27-pca100", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x08000000>; /* 128MB */ - }; -}; - -&cspi1 { - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, - <&gpio4 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&iomuxc { - imx27-phycard-s-som { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts deleted file mode 100644 index 344e77790152..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - */ - -#include "imx27-phytec-phycore-som.dtsi" - -/ { - model = "Phytec pcm970"; - compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; - - chosen { - stdout-path = &uart1; - }; - - display0: LQ035Q7 { - model = "Sharp-LQ035Q7"; - bits-per-pixel = <16>; - fsl,pcr = <0xf00080c0>; - - display-timings { - native-mode = <&timing0>; - timing0: 240x320 { - clock-frequency = <5500000>; - hactive = <240>; - vactive = <320>; - hback-porch = <5>; - hsync-len = <7>; - hfront-porch = <16>; - vback-porch = <7>; - vsync-len = <1>; - vfront-porch = <9>; - pixelclk-active = <1>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <0>; - }; - }; - }; - - regulators { - regulator@2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csien>; - reg = <2>; - regulator-name = "CSI_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - }; - - usbphy { - usbphy2: usbphy@2 { - compatible = "usb-nop-xceiv"; - reg = <2>; - vcc-supply = <®_5v0>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, - <&gpio4 27 GPIO_ACTIVE_LOW>; -}; - -&fb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb1>; - display = <&display0>; - lcd-supply = <®_5v0>; - fsl,dmacr = <0x00020010>; - fsl,lscr1 = <0x00120300>; - fsl,lpccr = <0x00a903ff>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - camgpio: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - imx27_phycore_rdk { - pinctrl_csien: csiengrp { - fsl,pins = < - MX27_PAD_USB_OC_B__GPIO2_24 0x0 - >; - }; - - pinctrl_cspi1cs1: cspi1cs1grp { - fsl,pins = < - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; - - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - /* Add pullup to DATA line */ - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x1 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ - MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&pmicleds { - ledr1: led@3 { - reg = <3>; - label = "system:red1:user"; - }; - - ledg1: led@4 { - reg = <4>; - label = "system:green1:user"; - }; - - ledb1: led@5 { - reg = <5>; - label = "system:blue1:user"; - }; - - ledr2: led@6 { - reg = <6>; - label = "system:red2:user"; - }; - - ledg2: led@7 { - reg = <7>; - label = "system:green2:user"; - }; - - ledb2: led@8 { - reg = <8>; - label = "system:blue2:user"; - }; - - ledr3: led@9 { - reg = <9>; - label = "system:red3:nand"; - linux,default-trigger = "nand-disk"; - }; - - ledg3: led@10 { - reg = <10>; - label = "system:green3:live"; - linux,default-trigger = "heartbeat"; - }; - - ledb3: led@11 { - reg = <11>; - label = "system:blue3:cpu"; - linux,default-trigger = "cpu0"; - }; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - bus-width = <4>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vmmc1_reg>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - vbus-supply = <®_5v0>; - fsl,usbphy = <&usbphy2>; - disable-over-current; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - - can@4,0 { - compatible = "nxp,sja1000"; - reg = <4 0x00000000 0x00000100>; - interrupt-parent = <&gpio5>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - nxp,external-clock-frequency = <16000000>; - nxp,tx-output-config = <0x16>; - nxp,no-comparator-bypass; - fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; - }; -}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi deleted file mode 100644 index 3d10273177e9..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Pengutronix - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pcm038"; - compatible = "phytec,imx27-pcm038", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - vcc-supply = <&sw3_reg>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - }; -}; - -&audmux { - status = "okay"; - - /* SSI0 <=> PINS_4 (MC13783 Audio) */ - ssi0 { - fsl,audmux-port = <0>; - fsl,port-config = <0xcb205000>; - }; - - pins4 { - fsl,audmux-port = <2>; - fsl,port-config = <0x00001000>; - }; -}; - -&cspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13783@0 { - compatible = "fsl,mc13783"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0>; - spi-cs-high; - spi-max-frequency = <20000000>; - interrupt-parent = <&gpio2>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - pmicleds: leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; - }; - - regulators { - /* SW1A and SW1B joined operation */ - sw1_reg: sw1a { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SW2A and SW2B joined operation */ - sw2_reg: sw2a { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vaudio_reg: vaudio { - regulator-always-on; - regulator-boot-on; - }; - - violo_reg: violo { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - viohi_reg: viohi { - regulator-always-on; - regulator-boot-on; - }; - - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vrf1_reg: vrf1 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vrf2_reg: vrf2 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { }; - - pwgt1spi_reg: pwgt1spi { - regulator-always-on; - }; - }; - }; -}; - -&fec { - phy-mode = "mii"; - phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; -}; - -&iomuxc { - imx27_phycore_som { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI1_FS__SSI1_FS 0x0 - MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 - MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 - MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - phy_type = "ulpi"; - fsl,usbphy = <&usbphy0>; - vbus-supply = <&sw3_reg>; - disable-over-current; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; - #address-cells = <1>; - #size-cells = <1>; - }; - - sram: sram@1,0 { - compatible = "mtd-ram"; - reg = <1 0x00000000 0x00800000>; - bank-width = <2>; - linux,mtd-name = "mtd-ram.0"; - fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h deleted file mode 100644 index 75aea0c701d4..000000000000 --- a/arch/arm/boot/dts/imx27-pinfunc.h +++ /dev/null @@ -1,474 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Markus Pargmann , Pengutronix - */ - -#ifndef __DTS_IMX27_PINFUNC_H -#define __DTS_IMX27_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - * mux_id consists of - * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - * - * function: 0 - Primary function - * 1 - Alternate function - * 2 - GPIO - * direction: 0 - Input - * 1 - Output - * gpio_oconf: 0 - A_IN - * 1 - B_IN - * 2 - C_IN - * 3 - Data Register - * gpio_iconfa/b: 0 - GPIO_IN - * 1 - Interrupt Status Register - * 2 - 0 - * 3 - 1 - * - * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is - * the pin number on the specific port (between 0 and 31). - */ - -#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 -#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 -#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 -#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 -#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 -#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 -#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 -#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 -#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 -#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 -#define MX27_PAD_LSCLK__LSCLK 0x05 0x004 -#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 -#define MX27_PAD_LD0__LD0 0x06 0x004 -#define MX27_PAD_LD0__GPIO1_6 0x06 0x032 -#define MX27_PAD_LD1__LD1 0x07 0x004 -#define MX27_PAD_LD1__GPIO1_7 0x07 0x032 -#define MX27_PAD_LD2__LD2 0x08 0x004 -#define MX27_PAD_LD2__GPIO1_8 0x08 0x032 -#define MX27_PAD_LD3__LD3 0x09 0x004 -#define MX27_PAD_LD3__GPIO1_9 0x09 0x032 -#define MX27_PAD_LD4__LD4 0x0a 0x004 -#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 -#define MX27_PAD_LD5__LD5 0x0b 0x004 -#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 -#define MX27_PAD_LD6__LD6 0x0c 0x004 -#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 -#define MX27_PAD_LD7__LD7 0x0d 0x004 -#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 -#define MX27_PAD_LD8__LD8 0x0e 0x004 -#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 -#define MX27_PAD_LD9__LD9 0x0f 0x004 -#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 -#define MX27_PAD_LD10__LD10 0x10 0x004 -#define MX27_PAD_LD10__GPIO1_16 0x10 0x032 -#define MX27_PAD_LD11__LD11 0x11 0x004 -#define MX27_PAD_LD11__GPIO1_17 0x11 0x032 -#define MX27_PAD_LD12__LD12 0x12 0x004 -#define MX27_PAD_LD12__GPIO1_18 0x12 0x032 -#define MX27_PAD_LD13__LD13 0x13 0x004 -#define MX27_PAD_LD13__GPIO1_19 0x13 0x032 -#define MX27_PAD_LD14__LD14 0x14 0x004 -#define MX27_PAD_LD14__GPIO1_20 0x14 0x032 -#define MX27_PAD_LD15__LD15 0x15 0x004 -#define MX27_PAD_LD15__GPIO1_21 0x15 0x032 -#define MX27_PAD_LD16__LD16 0x16 0x004 -#define MX27_PAD_LD16__GPIO1_22 0x16 0x032 -#define MX27_PAD_LD17__LD17 0x17 0x004 -#define MX27_PAD_LD17__GPIO1_23 0x17 0x032 -#define MX27_PAD_REV__REV 0x18 0x004 -#define MX27_PAD_REV__GPIO1_24 0x18 0x032 -#define MX27_PAD_CLS__CLS 0x19 0x004 -#define MX27_PAD_CLS__GPIO1_25 0x19 0x032 -#define MX27_PAD_PS__PS 0x1a 0x004 -#define MX27_PAD_PS__GPIO1_26 0x1a 0x032 -#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 -#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 -#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 -#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 -#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 -#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 -#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 -#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 -#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 -#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 -#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 -#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 -#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 -#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 -#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 -#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 -#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 -#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 -#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 -#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 -#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 -#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 -#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 -#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 -#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 -#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 -#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 -#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 -#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 -#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 -#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 -#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 -#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 -#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 -#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 -#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 -#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 -#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 -#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 -#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 -#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 -#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 -#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 -#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 -#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 -#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 -#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 -#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 -#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 -#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 -#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 -#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 -#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 -#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 -#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 -#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 -#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 -#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 -#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 -#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 -#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 -#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 -#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 -#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 -#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 -#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 -#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 -#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 -#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 -#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 -#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 -#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 -#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 -#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 -#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 -#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 -#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 -#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 -#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 -#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 -#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 -#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 -#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 -#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 -#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 -#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 -#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 -#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 -#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 -#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 -#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 -#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 -#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 -#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 -#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 -#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 -#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 -#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 -#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 -#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 -#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 -#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 -#define MX27_PAD_TOUT__TOUT 0x4e 0x004 -#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 -#define MX27_PAD_TIN__TIN 0x4f 0x000 -#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 -#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 -#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 -#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 -#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 -#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 -#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 -#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 -#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 -#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 -#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 -#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 -#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 -#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 -#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 -#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 -#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 -#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 -#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 -#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 -#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 -#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 -#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 -#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 -#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 -#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 -#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 -#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 -#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 -#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 -#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 -#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 -#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 -#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 -#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 -#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 -#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 -#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 -#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 -#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 -#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 -#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 -#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 -#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 -#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 -#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 -#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 -#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 -#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 -#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 -#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 -#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 -#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 -#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 -#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 -#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 -#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 -#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 -#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 -#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 -#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 -#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 -#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 -#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 -#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 -#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 -#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 -#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 -#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 -#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 -#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 -#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 -#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 -#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 -#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 -#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 -#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 -#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 -#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 -#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 -#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 -#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 -#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 -#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 -#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 -#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 -#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 -#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 -#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 -#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 -#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 -#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 -#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 -#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 -#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 -#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 -#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 -#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 -#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 -#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 -#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 -#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 -#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 -#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 -#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 -#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 -#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 -#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 -#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 -#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 -#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 -#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 -#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 -#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 -#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 -#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 -#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 -#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 -#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 -#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 -#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 -#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 -#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 -#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 -#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 -#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 -#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 -#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 -#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 -#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 -#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 -#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 -#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 -#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 -#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 -#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 -#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 -#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 -#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 -#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 -#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 -#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 -#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 -#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 -#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 -#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 -#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 -#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 -#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 -#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 -#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 -#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 -#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 -#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 -#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 -#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 -#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 -#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 -#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 -#define MX27_PAD_PWMO__PWMO 0x85 0x004 -#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 -#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 -#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 -#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 -#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 -#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 -#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 -#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 -#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 -#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 -#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 -#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 -#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 -#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 -#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 -#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 -#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 -#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 -#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 -#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 -#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 -#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 -#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 -#define MX27_PAD_RTCK__RTCK 0x90 0x004 -#define MX27_PAD_RTCK__OWIRE 0x90 0x005 -#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 -#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 -#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 -#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 -#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 -#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 -#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 -#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 -#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 -#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 -#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 -#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 -#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 -#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 -#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 -#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 -#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 -#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 -#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 -#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 -#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 -#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 -#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 -#define MX27_PAD_NFRB__NFRB 0xa0 0x000 -#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 -#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 -#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 -#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 -#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 -#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 -#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 -#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 -#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 -#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 -#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 -#define MX27_PAD_NFALE__NFALE 0xa4 0x004 -#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 -#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 -#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 -#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 -#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 -#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 -#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 -#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 -#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 -#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 -#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 -#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 -#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 -#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 -#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 -#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 -#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 -#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 -#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 -#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 -#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 -#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 -#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 -#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 -#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 -#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 -#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 -#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 -#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 -#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 -#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 -#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 -#define MX27_PAD_CLKO__CLKO 0xaf 0x004 -#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 -#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 -#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 -#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 -#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 -#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 -#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 -#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 -#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 -#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 -#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 -#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 -#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 -#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 -#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 -#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 -#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 -#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 -#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 -#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 -#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 -#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 -#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 -#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 -#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 -#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 - -#endif /* __DTS_IMX27_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi deleted file mode 100644 index e140307be2e7..000000000000 --- a/arch/arm/boot/dts/imx27.dtsi +++ /dev/null @@ -1,593 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Sascha Hauer, Pengutronix - -#include "imx27-pinfunc.h" - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - spi0 = &cspi1; - spi1 = &cspi2; - spi2 = &cspi3; - }; - - aitc: aitc-interrupt-controller@10040000 { - compatible = "fsl,imx27-aitc", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10040000 0x1000>; - }; - - clocks { - clk_osc26m: osc26m { - compatible = "fsl,imx-osc26m", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu: cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "arm,arm926ej-s"; - operating-points = < - /* kHz uV */ - 266000 1300000 - 399000 1450000 - >; - clock-latency = <62500>; - clocks = <&clks IMX27_CLK_CPU_DIV>; - voltage-tolerance = <5>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&aitc>; - ranges; - - aipi1: aipi@10000000 { /* AIPI1 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10000000 0x20000>; - ranges; - - dma: dma@10001000 { - compatible = "fsl,imx27-dma"; - reg = <0x10001000 0x1000>; - interrupts = <32>; - clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, - <&clks IMX27_CLK_DMA_AHB_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <1>; - dma-channels = <16>; - }; - - wdog: watchdog@10002000 { - compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; - reg = <0x10002000 0x1000>; - interrupts = <27>; - clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; - }; - - gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10003000 0x1000>; - interrupts = <26>; - clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@10004000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10004000 0x1000>; - interrupts = <25>; - clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt3: timer@10005000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10005000 0x1000>; - interrupts = <24>; - clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - pwm: pwm@10006000 { - #pwm-cells = <3>; - compatible = "fsl,imx27-pwm"; - reg = <0x10006000 0x1000>; - interrupts = <23>; - clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - rtc: rtc@10007000 { - compatible = "fsl,imx21-rtc"; - reg = <0x10007000 0x1000>; - interrupts = <22>; - clocks = <&clks IMX27_CLK_CKIL>, - <&clks IMX27_CLK_RTC_IPG_GATE>; - clock-names = "ref", "ipg"; - }; - - kpp: kpp@10008000 { - compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; - reg = <0x10008000 0x1000>; - interrupts = <21>; - clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; - status = "disabled"; - }; - - owire: owire@10009000 { - compatible = "fsl,imx27-owire", "fsl,imx21-owire"; - reg = <0x10009000 0x1000>; - clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; - status = "disabled"; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@1000b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000b000 0x1000>; - interrupts = <19>; - clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@1000c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000c000 0x1000>; - interrupts = <18>; - clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@1000d000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000d000 0x1000>; - interrupts = <17>; - clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - cspi1: spi@1000e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000e000 0x1000>; - interrupts = <16>; - clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - cspi2: spi@1000f000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000f000 0x1000>; - interrupts = <15>; - clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi1: ssi@10010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; - reg = <0x10010000 0x1000>; - interrupts = <14>; - clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; - dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; - dma-names = "rx0", "tx0", "rx1", "tx1"; - fsl,fifo-depth = <8>; - status = "disabled"; - }; - - ssi2: ssi@10011000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; - reg = <0x10011000 0x1000>; - interrupts = <13>; - clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; - dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; - dma-names = "rx0", "tx0", "rx1", "tx1"; - fsl,fifo-depth = <8>; - status = "disabled"; - }; - - i2c1: i2c@10012000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; - reg = <0x10012000 0x1000>; - interrupts = <12>; - clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; - status = "disabled"; - }; - - sdhci1: mmc@10013000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10013000 0x1000>; - interrupts = <11>; - clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 7>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - sdhci2: mmc@10014000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10014000 0x1000>; - interrupts = <10>; - clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 6>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015000 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@10015100 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015100 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@10015200 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015200 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@10015300 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015300 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@10015400 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015400 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@10015500 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015500 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - audmux: audmux@10016000 { - compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; - reg = <0x10016000 0x1000>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "audmux"; - status = "disabled"; - }; - - cspi3: spi@10017000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x10017000 0x1000>; - interrupts = <6>; - clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: timer@10019000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10019000 0x1000>; - interrupts = <4>; - clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt5: timer@1001a000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x1001a000 0x1000>; - interrupts = <3>; - clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - uart5: serial@1001b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001b000 0x1000>; - interrupts = <49>; - clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@1001c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001c000 0x1000>; - interrupts = <48>; - clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@1001d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; - reg = <0x1001d000 0x1000>; - interrupts = <1>; - clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; - status = "disabled"; - }; - - sdhci3: mmc@1001e000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x1001e000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 36>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gpt6: timer@1001f000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x1001f000 0x1000>; - interrupts = <2>; - clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - }; - - aipi2: aipi@10020000 { /* AIPI2 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10020000 0x20000>; - ranges; - - fb: fb@10021000 { - compatible = "fsl,imx27-fb", "fsl,imx21-fb"; - interrupts = <61>; - reg = <0x10021000 0x1000>; - clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, - <&clks IMX27_CLK_LCDC_AHB_GATE>, - <&clks IMX27_CLK_PER3_GATE>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - coda: coda@10023000 { - compatible = "fsl,imx27-vpu", "cnm,codadx6"; - reg = <0x10023000 0x0200>; - interrupts = <53>; - clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, - <&clks IMX27_CLK_VPU_AHB_GATE>; - clock-names = "per", "ahb"; - iram = <&iram>; - }; - - usbotg: usb@10024000 { - compatible = "fsl,imx27-usb"; - reg = <0x10024000 0x200>; - interrupts = <56>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - status = "disabled"; - }; - - usbh1: usb@10024200 { - compatible = "fsl,imx27-usb"; - reg = <0x10024200 0x200>; - interrupts = <54>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@10024400 { - compatible = "fsl,imx27-usb"; - reg = <0x10024400 0x200>; - interrupts = <55>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@10024600 { - #index-cells = <1>; - compatible = "fsl,imx27-usbmisc"; - reg = <0x10024600 0x200>; - }; - - sahara2: crypto@10025000 { - compatible = "fsl,imx27-sahara"; - reg = <0x10025000 0x1000>; - interrupts = <59>; - clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, - <&clks IMX27_CLK_SAHARA_AHB_GATE>; - clock-names = "ipg", "ahb"; - }; - - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; - - iim: efuse@10028000 { - compatible = "fsl,imx27-iim"; - reg = <0x10028000 0x1000>; - interrupts = <62>; - clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; - }; - - fec: ethernet@1002b000 { - compatible = "fsl,imx27-fec"; - reg = <0x1002b000 0x1000>; - interrupts = <50>; - clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, - <&clks IMX27_CLK_FEC_AHB_GATE>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - }; - - nfc: nand-controller@d8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx27-nand"; - reg = <0xd8000000 0x1000>; - interrupts = <29>; - clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; - status = "disabled"; - }; - - weim: weim@d8002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx27-weim"; - reg = <0xd8002000 0x1000>; - clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; - ranges = < - 0 0 0xc0000000 0x08000000 - 1 0 0xc8000000 0x08000000 - 2 0 0xd0000000 0x02000000 - 3 0 0xd2000000 0x02000000 - 4 0 0xd4000000 0x02000000 - 5 0 0xd6000000 0x02000000 - >; - status = "disabled"; - }; - - iram: sram@ffff4c00 { - compatible = "mmio-sram"; - reg = <0xffff4c00 0xb400>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts deleted file mode 100644 index 98672932e41b..000000000000 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Armadeus Systems - - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Armadeus Systems APF28 module"; - compatible = "armadeus,imx28-apf28", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; - - partition@300000 { - label = "env"; - reg = <0x300000 0x80000>; - }; - - partition@380000 { - label = "env2"; - reg = <0x380000 0x80000>; - }; - - partition@400000 { - label = "dtb"; - reg = <0x400000 0x80000>; - }; - - partition@480000 { - label = "splash"; - reg = <0x480000 0x80000>; - }; - - partition@500000 { - label = "kernel"; - reg = <0x500000 0x800000>; - }; - - partition@d00000 { - label = "rootfs"; - reg = <0xd00000 0xf300000>; - }; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts deleted file mode 100644 index 4704b6141836..000000000000 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Armadeus Systems - - */ - -/* APF28Dev is a docking board for the APF28 SOM */ -#include "imx28-apf28.dts" - -/ { - model = "Armadeus Systems APF28Dev docking/development board"; - compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 23 1>; - enable-active-high; - }; - - reg_can0_vcc: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "can0_vcc"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio0 21 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - - pwms = <&pwm 3 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-button { - label = "User button"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can0_vcc>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_16bit_pins_a - &lcdif_pins_apf28dev>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_apf28dev>; - - hog_pins_apf28dev: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D16__GPIO_1_16 - MX28_PAD_LCD_D17__GPIO_1_17 - MX28_PAD_LCD_D18__GPIO_1_18 - MX28_PAD_LCD_D19__GPIO_1_19 - MX28_PAD_LCD_D20__GPIO_1_20 - MX28_PAD_LCD_D21__GPIO_1_21 - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apf28dev: lcdif-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_apf28dev: otg-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; -}; - -&ssp2 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_apf28dev - &usb0_id_pins_b>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts deleted file mode 100644 index f9bf40d96568..000000000000 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Bluegiga APX4 Development Kit"; - compatible = "bluegiga,apx4devkit", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "bluegiga,apx4devkit-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "apx4devkit-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio3 28 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; -}; - -&auart1 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; -}; - -&auart2 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_a>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_apx4>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hfront-porch = <40>; - vback-porch = <32>; - vfront-porch = <13>; - hsync-len = <48>; - vsync-len = <3>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - pcf8563: rtc@51 { - compatible = "phg,pcf8563"; - reg = <0x51>; - }; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_RDY1__GPIO_0_21 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_JTAG_RTCK__GPIO_4_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apx4: lcdif-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_SSP0_DATA7__SSP2_SCK - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; -}; - -&ssp2 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; - bus-width = <4>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usbphy1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts deleted file mode 100644 index d004b1cbb4ae..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Free Electrons - */ - -/dts-v1/; -#include "imx28.dtsi" -#include - -/ { - model = "Crystalfontz CFA-10036 Board"; - compatible = "crystalfontz,cfa10036", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cfa10036>; - - power { - gpios = <&gpio3 4 1>; - default-state = "on"; - }; - }; - - reg_vddio_sd0: vddio-sd0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pwr_cfa10036>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_b>; - clock-frequency = <400000>; - status = "okay"; - - ssd1306: oled@3c { - compatible = "solomon,ssd1306fb-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&ssd1306_cfa10036>; - reg = <0x3c>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - solomon,height = <32>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,com-lrremap; - solomon,com-invdir; - solomon,com-offset = <32>; - }; -}; - -&pinctrl { - ssd1306_cfa10036: ssd1306-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_cfa10036: leds-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_cfa10036: otg-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x31c3 /* - MX28_PAD_PWM3__GPIO_3_28 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - vmmc-supply = <®_vddio_sd0>; - bus-width = <4>; - status = "okay"; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_cfa10036>; - dr_mode = "peripheral"; - phy_type = "utmi"; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts deleted file mode 100644 index d3e9a731525b..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Free Electrons - */ - -/* - * The CFA-10049 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10037 Board"; - compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10037: usb-10037@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10037: mac0-10037@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10037>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10037>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts deleted file mode 100644 index c5a7f56d83db..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Free Electrons - */ - -/* - * The CFA-10049 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10049 Board"; - compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; - - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2cmux_pins_cfa10049>; - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; - i2c-parent = <&i2c1>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adc0: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adc1: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - adc2: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca_pins_cfa10049>; - interrupt-parent = <&gpio2>; - interrupts = <19 0x2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10049>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - spi-2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10049>; - status = "okay"; - sck-gpios = <&gpio2 16 0>; - mosi-gpios = <&gpio2 17 0>; - miso-gpios = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8357: hx8357@0 { - compatible = "himax,hx8357b", "himax,hx8357"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>; - }; - }; - - spi-3 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_cfa10049>; - status = "okay"; - sck-gpios = <&gpio0 24 0>; - mosi-gpios = <&gpio0 28 0>; - cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; - num-chipselects = <3>; - #address-cells = <1>; - #size-cells = <0>; - - gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <2>; - spi-max-frequency = <100000>; - }; - - gpio6: gpio6@1 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <1>; - registers-number = <4>; - spi-max-frequency = <100000>; - }; - - dac0: dh2228@2 { - compatible = "rohm,dh2228fv"; - reg = <2>; - spi-max-frequency = <100000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&rotary_btn_pins_cfa10049>; - - rotary-button { - label = "rotary_button"; - gpios = <&gpio3 26 1>; - debounce-interval = <10>; - linux,code = <28>; - }; - }; - - rotary { - compatible = "rotary-encoder"; - pinctrl-names = "default"; - pinctrl-0 = <&rotary_pins_cfa10049>; - gpios = <&gpio3 24 1>, <&gpio3 25 1>; - linux,axis = <1>; /* REL_Y */ - rotary-encoder,relative-axis; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&w1_gpio_pins>; - status = "okay"; - gpios = <&gpio1 21 0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10049 - &lcdif_pins_cfa10049 - &lcdif_pins_cfa10049_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10049>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; -}; - -&pinctrl { - usb_pins_cfa10049: usb-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2cmux_pins_cfa10049: i2cmux-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10049: mac0-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pca_pins_cfa10049: pca-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_pins_cfa10049: rotary-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_btn_pins_cfa10049: rotary-btn-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__GPIO_3_26 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_cfa10049: spi2-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_cfa10049: spi3-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPIO_0_24 - MX28_PAD_GPMI_RESETN__GPIO_0_28 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_ALE__GPIO_0_26 - MX28_PAD_GPMI_CLE__GPIO_0_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - w1_gpio_pins: w1-gpio@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; /* 0 will enable the keeper */ - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts deleted file mode 100644 index 70e225a99fbe..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Crystalfontz America, Inc. - * Free Electrons - */ - -/* - * The CFA-10055 is an expansion board for the CFA-10036 module and - * CFA-10037, thus we need to include the CFA-10037 DTS. - */ -#include "imx28-cfa10037.dts" - -/ { - model = "Crystalfontz CFA-10055 Board"; - compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - spi-2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10055>; - status = "okay"; - sck-gpios = <&gpio2 16 0>; - mosi-gpios = <&gpio2 17 0>; - miso-gpios = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8357: hx8357@0 { - compatible = "himax,hx8357b", "himax,hx8357"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10055 - &lcdif_pins_cfa10055 - &lcdif_pins_cfa10055_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&pinctrl { - spi2_pins_cfa10055: spi2-cfa10055@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts deleted file mode 100644 index bc2d6fcad12f..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Free Electrons - */ - -/* - * The CFA-10055 is an expansion board for the CFA-10036 module and - * CFA-10037, thus we need to include the CFA-10037 DTS. - */ -#include "imx28-cfa10037.dts" - -/ { - model = "Crystalfontz CFA-10056 Board"; - compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - spi-2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10056>; - status = "okay"; - sck-gpios = <&gpio2 16 0>; - mosi-gpios = <&gpio2 17 0>; - miso-gpios = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8369: hx8369@0 { - compatible = "himax,hx8369a", "himax,hx8369"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - }; - }; -}; - -&pinctrl { - spi2_pins_cfa10056: spi2-cfa10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056: lcdif-10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10056 - &lcdif_pins_cfa10056_pullup >; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <32000000>; - hactive = <480>; - vactive = <800>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <5>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts deleted file mode 100644 index 27602c01f162..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Crystalfontz America, Inc. - * Copyright 2012 Free Electrons - */ - -/* - * The CFA-10057 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10057 Board"; - compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10057>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10057 - &lcdif_pins_cfa10057>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <12>; - hback-porch = <2>; - vfront-porch = <5>; - vback-porch = <3>; - hsync-len = <2>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; -}; - -&pinctrl { - usb_pins_cfa10057: usb-10057@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10057: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts deleted file mode 100644 index 931c4d089b26..000000000000 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Crystalfontz America, Inc. - * Copyright 2013 Free Electrons - */ - -/* - * The CFA-10058 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10058 Board"; - compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10058>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10058>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <13>; - vfront-porch = <29>; - hsync-len = <8>; - vsync-len = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; -}; - -&pinctrl { - usb_pins_cfa10058: usb-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10058: lcdif-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts deleted file mode 100644 index b73020ff1053..000000000000 --- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include "imx28-duckbill-2.dts" - -/ { - model = "I2SE Duckbill 2 485"; - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - - leds { - rs485-red { - label = "duckbill:red:rs485"; - gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - }; - - rs485-green { - label = "duckbill:green:rs485"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c0 { - status = "disabled"; -}; - -&led_pins { - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; -}; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts deleted file mode 100644 index 473d99b9b42f..000000000000 --- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include -#include "imx28-duckbill-2.dts" - -/ { - model = "I2SE Duckbill 2 EnOcean"; - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - - leds { - enocean-blue { - label = "duckbill:blue:enocean"; - gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - }; - - enocean-red { - label = "duckbill:red:enocean"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - }; - - enocean-green { - label = "duckbill:green:enocean"; - gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&enocean_button>; - - key-enocean { - label = "EnOcean"; - linux,code = ; - gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&i2c0 { - status = "disabled"; -}; - -&led_pins { - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - MX28_PAD_AUART0_CTS__GPIO_3_2 - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; -}; - -&pinctrl { - enocean_button: enocean-button@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts deleted file mode 100644 index 859d97a5a775..000000000000 --- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include "imx28-duckbill-2.dts" - -/ { - model = "I2SE Duckbill 2 SPI"; - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; - - aliases { - ethernet1 = &qca7000; - }; -}; - -&auart0 { - status = "disabled"; -}; - -&i2c0 { - status = "disabled"; -}; - -&pinctrl { - qca7000_pins: qca7000@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ - MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */ - MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */ - MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */ - MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */ - MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&ssp2 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - /delete-property/ bus-width; - /delete-property/ vmmc-supply; - status = "okay"; - - qca7000: ethernet@0 { - reg = <0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&qca7000_pins>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <8000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts deleted file mode 100644 index 4e28212e9626..000000000000 --- a/arch/arm/boot/dts/imx28-duckbill-2.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill 2"; - compatible = "i2se,duckbill-2", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&lradc { - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; -}; - -&ssp2 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usbphy0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts deleted file mode 100644 index 13ffd533fdea..000000000000 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013-2014,2016 Michael Heimpold - * Copyright (C) 2015-2017 I2SE GmbH - */ - -/dts-v1/; -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill"; - compatible = "i2se,duckbill", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&lradc { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&ssp2 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts deleted file mode 100644 index 29f8a3a245d4..000000000000 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - */ - -/* - * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC - */ - -/dts-v1/; -#include "imx28-eukrea-mbmx28lc.dtsi" - -/ { - model = "Eukrea Electromatique MBMX283LC"; - compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl{ - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cpuimx283>; - - hog_pins_cpuimx283: hog-cpuimx283@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_ENET0_TX_CLK__GPIO_4_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts deleted file mode 100644 index cd875ace168d..000000000000 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - */ - -/* - * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC - */ - -#include "imx28-eukrea-mbmx283lc.dts" - -/ { - model = "Eukrea Electromatique MBMX287LC"; - compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; - hog_pins_cpuimx287: hog-cpuimx287@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi deleted file mode 100644 index b285a946e2c2..000000000000 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - */ - -#include -#include -#include "imx28.dtsi" - -/ { - model = "Eukrea Electromatique MBMX28LC"; - compatible = "eukrea,mbmx28lc", "fsl,imx28"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 1000000>; - brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; - default-brightness-level = <10>; - }; - - gpio-keys-0 { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; - - switch-sw3 { - label = "SW3"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - gpio-keys-1 { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; - - switch-sw4 { - label = "SW4"; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - led-d6 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_d6_pins_mbmx28lc>; - - led1 { - label = "d6"; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-d7 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_d7_pins_mbmx28lc>; - - led1 { - label = "d7"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_lcd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx28-mbmx28lc-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-mbmx28lc-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - model = "43WVF1G-0"; - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9072000>; - hactive = <480>; - vactive = <272>; - hback-porch = <10>; - hfront-porch = <5>; - vback-porch = <8>; - vfront-porch = <8>; - hsync-len = <40>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&pinctrl { - gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D20__GPIO_1_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D18__GPIO_1_18 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D19__GPIO_1_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - cd-inverted; - status = "okay"; -}; - -&usb0 { - disable-over-current; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_b>; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts deleted file mode 100644 index 783abb82b2a8..000000000000 --- a/arch/arm/boot/dts/imx28-evk.dts +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Freescale i.MX28 Evaluation Kit"; - compatible = "fsl,imx28-evk", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_fec_3v3: regulator-fec-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 15 0>; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - enable-active-high; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; - - reg_can_3v3: regulator-can-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 13 0>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx28-evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio3_5>; - - user { - label = "Heartbeat"; - gpios = <&gpio3 5 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight_display: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&auart3 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg - &gpmi_pins_evk>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_evk>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - at24@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - }; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP1_DATA3__GPIO_2_15 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio3_5: led_gpio3_5@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_evk: gpmi-nand-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPMI_CE1N - MX28_PAD_GPMI_RDY1__GPMI_READY1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_evk: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio2 12 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; -}; - -&ssp1 { - compatible = "fsl,imx28-mmc"; - bus-width = <8>; - wp-gpios = <&gpio0 28 0>; -}; - -&ssp2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_a>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/imx28-lwe.dtsi deleted file mode 100644 index bb971e660db8..000000000000 --- a/arch/arm/boot/dts/imx28-lwe.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2021 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - aliases { - spi2 = &ssp3; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1"; - }; - - memory@40000000 { - reg = <0x40000000 0x08000000>; - }; - - reg_3v3: regulator-reg-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_5v: regulator-reg-usb-5v { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_fec_3v3: regulator-reg-fec-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec-phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - #sound-dai-cells = <0>; - assigned-clocks = <&clks 53>; - assigned-clock-rates = <12000000>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - #sound-dai-cells = <0>; - status = "okay"; -}; - -&spi3_pins_a { - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__SSP3_D4 - MX28_PAD_AUART2_TX__SSP3_D5 - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - MX28_PAD_AUART2_TX__GPIO_3_9 - >; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a>; - bus-width = <8>; - vmmc-supply = <®_3v3>; - non-removable; - status = "okay"; -}; - -&ssp2 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&ssp3 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_a>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0 0x80000>; - read-only; - }; - - partition@80000 { - label = "env0"; - reg = <0x80000 0x10000>; - }; - - partition@90000 { - label = "env1"; - reg = <0x90000 0x10000>; - }; - - partition@100000 { - label = "kernel"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "swupdate"; - reg = <0x500000 0x800000>; - }; - }; - }; -}; - -&usb0 { - vbus-supply = <®_usb_5v>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb_5v>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_b>; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi deleted file mode 100644 index c08b14ad7cd5..000000000000 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Marek Vasut - */ - -#include "imx28.dtsi" - -/ { - model = "Aries/DENX M28"; - compatible = "aries,m28", "denx,m28", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&gpmi { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts deleted file mode 100644 index 6b01de9efd02..000000000000 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013 Marek Vasut - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "MSR M28CU3"; - compatible = "msr,m28cu3", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_gpio>; - - user1 { - label = "sd0-led"; - gpios = <&gpio2 26 0>; - linux,default-trigger = "mmc0"; - }; - - user2 { - label = "sd1-led"; - gpios = <&gpio2 24 0>; - linux,default-trigger = "mmc2"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 0>; - }; - - reg_vddio_sd1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 0>; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; -}; - -&auart3 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_2pins_b>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; -}; - -&gpmi { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "gpmi-nfc-0-boot"; - reg = <0x00000000 0x01400000>; - read-only; - }; - - partition@1 { - label = "gpmi-nfc-general-use"; - reg = <0x01400000 0x0ec00000>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <6410256>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hfront-porch = <20>; - vback-porch = <15>; - vfront-porch = <5>; - hsync-len = <30>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; -}; - -&ocotp { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - MX28_PAD_PWM4__GPIO_3_29 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_RESET__LCD_RESET - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_gpio: leds-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SCK__GPIO_2_24 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; -}; - -&ssp2 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_a - &mmc2_cd_cfg - &mmc2_sck_cfg_a>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd1>; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts deleted file mode 100644 index e350d57a4cec..000000000000 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - - * Copyright (C) 2012 Marek Vasut - */ - -/dts-v1/; -#include "imx28-m28.dtsi" - -/ { - model = "Aries/DENX M28EVK"; - compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - regulators { - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 12 0>; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 13 0>; - }; - }; - - sound { - compatible = "denx,m28evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "m28evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; -}; - -&auart1 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; -}; - -&auart2 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_b>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&i2c0 { - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - eeprom: eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <0>; - hfront-porch = <256>; - vback-porch = <0>; - vfront-porch = <45>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_AUART2_CTS__GPIO_3_10 - MX28_PAD_AUART2_RTS__GPIO_3_11 - MX28_PAD_AUART3_RX__GPIO_3_12 - MX28_PAD_AUART3_TX__GPIO_3_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio3 10 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; -}; - -&ssp2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_a>; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h deleted file mode 100644 index d427e6c2fa78..000000000000 --- a/arch/arm/boot/dts/imx28-pinfunc.h +++ /dev/null @@ -1,500 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - */ - -#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ -#define __DT_BINDINGS_MX28_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -#define MX28_PAD_LCD_D00__LCD_D0 0x1000 -#define MX28_PAD_LCD_D01__LCD_D1 0x1010 -#define MX28_PAD_LCD_D02__LCD_D2 0x1020 -#define MX28_PAD_LCD_D03__LCD_D3 0x1030 -#define MX28_PAD_LCD_D04__LCD_D4 0x1040 -#define MX28_PAD_LCD_D05__LCD_D5 0x1050 -#define MX28_PAD_LCD_D06__LCD_D6 0x1060 -#define MX28_PAD_LCD_D07__LCD_D7 0x1070 -#define MX28_PAD_LCD_D08__LCD_D8 0x1080 -#define MX28_PAD_LCD_D09__LCD_D9 0x1090 -#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX28_PAD_LCD_D16__LCD_D16 0x1100 -#define MX28_PAD_LCD_D17__LCD_D17 0x1110 -#define MX28_PAD_LCD_D18__LCD_D18 0x1120 -#define MX28_PAD_LCD_D19__LCD_D19 0x1130 -#define MX28_PAD_LCD_D20__LCD_D20 0x1140 -#define MX28_PAD_LCD_D21__LCD_D21 0x1150 -#define MX28_PAD_LCD_D22__LCD_D22 0x1160 -#define MX28_PAD_LCD_D23__LCD_D23 0x1170 -#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 -#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -#define MX28_PAD_PWM0__PWM_0 0x3100 -#define MX28_PAD_PWM1__PWM_1 0x3110 -#define MX28_PAD_PWM2__PWM_2 0x3120 -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -#define MX28_PAD_PWM3__PWM_3 0x31c0 -#define MX28_PAD_PWM4__PWM_4 0x31d0 -#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 -#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 -#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 -#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -#define MX28_PAD_PWM0__I2C1_SCL 0x3101 -#define MX28_PAD_PWM1__I2C1_SDA 0x3111 -#define MX28_PAD_PWM2__USB0_ID 0x3121 -#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 -#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 -#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 -#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 -#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 -#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 -#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 -#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 -#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 -#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 -#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 -#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 -#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 -#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 -#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 -#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 -#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 -#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 -#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -#define MX28_PAD_AUART1_RX__PWM_0 0x3042 -#define MX28_PAD_AUART1_TX__PWM_1 0x3052 -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -#define MX28_PAD_PWM0__DUART_RX 0x3102 -#define MX28_PAD_PWM1__DUART_TX 0x3112 -#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -#define MX28_PAD_PWM0__GPIO_3_16 0x3103 -#define MX28_PAD_PWM1__GPIO_3_17 0x3113 -#define MX28_PAD_PWM2__GPIO_3_18 0x3123 -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 -#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 -#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts deleted file mode 100644 index 5d74a68c56ff..000000000000 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2012 Marek Vasut - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "SchulerControl GmbH, SC SPS 1"; - compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - compatible = "gpio-leds"; - status = "okay"; - - led@1 { - label = "sps1-1:yellow:user"; - gpios = <&gpio0 6 0>; - linux,default-trigger = "heartbeat"; - reg = <0>; - }; - - led@2 { - label = "sps1-2:red:user"; - gpios = <&gpio0 3 0>; - linux,default-trigger = "heartbeat"; - reg = <1>; - }; - - led@3 { - label = "sps1-3:red:user"; - gpios = <&gpio0 0 0>; - default-trigger = "heartbeat"; - reg = <2>; - }; - - }; -}; - -&auart0 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom: eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPIO_0_0 - MX28_PAD_GPMI_D03__GPIO_0_3 - MX28_PAD_GPMI_D06__GPIO_0_6 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a>; - bus-width = <4>; - status = "okay"; -}; - -&ssp2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256", "mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_b>; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts deleted file mode 100644 index ae6ed5c41be3..000000000000 --- a/arch/arm/boot/dts/imx28-ts4600.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2016 Savoir-Faire Linux - * Author: Sebastien Bourdelin - */ - -/dts-v1/; -#include "imx28.dtsi" -#include "dt-bindings/gpio/gpio.h" - -/ { - - model = "Technologic Systems i.MX28 TS-4600"; - compatible = "technologic,imx28-ts4600", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000>; /* 256MB */ - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; - }; - -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; -}; - -&pinctrl { - en_sd_pwr: en-sd-pwr@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_sck_cfg - &en_sd_pwr>; - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts deleted file mode 100644 index 23ad7cd0a1de..000000000000 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ /dev/null @@ -1,677 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2012 Shawn Guo - * Copyright 2013-2017 Lothar Waßmann - */ - -/dts-v1/; -#include "imx28.dtsi" -#include -#include - -/ { - model = "Ka-Ro electronics TX28 module"; - compatible = "karo,tx28", "fsl,imx28"; - - aliases { - can0 = &can0; - can1 = &can1; - display = &display0; - ds1339 = &ds1339; - gpio5 = &gpio5; - lcdif = &lcdif; - lcdif_23bit_pins = &tx28_lcdif_23bit_pins; - lcdif_24bit_pins = &lcdif_24bit_pins_a; - reg_can_xcvr = ®_can_xcvr; - spi_gpio = &spi_gpio; - spi_mxs = &ssp3; - stk5led = &user_led; - usbotg = &usb0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0>; /* will be filled in by U-Boot */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_flexcan_xcvr_pins>; - }; - - reg_lcd: regulator-lcd-power { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_reset: regulator-lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - startup-delay-us = <300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - sound { - compatible = "fsl,imx28-tx28-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-tx28-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 500000>; - /* - * a silly way to create a 1:1 relationship between the - * PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - matrix_keypad: matrix-keypad { - compatible = "gpio-matrix-keypad"; - col-gpios = < - &gpio5 0 GPIO_ACTIVE_HIGH - &gpio5 1 GPIO_ACTIVE_HIGH - &gpio5 2 GPIO_ACTIVE_HIGH - &gpio5 3 GPIO_ACTIVE_HIGH - >; - row-gpios = < - &gpio5 4 GPIO_ACTIVE_HIGH - &gpio5 5 GPIO_ACTIVE_HIGH - &gpio5 6 GPIO_ACTIVE_HIGH - &gpio5 7 GPIO_ACTIVE_HIGH - >; - /* sample keymap */ - linux,keymap = < - 0x00000074 /* row 0, col 0, KEY_POWER */ - 0x00010052 /* row 0, col 1, KEY_KP0 */ - 0x0002004f /* row 0, col 2, KEY_KP1 */ - 0x00030050 /* row 0, col 3, KEY_KP2 */ - 0x01000051 /* row 1, col 0, KEY_KP3 */ - 0x0101004b /* row 1, col 1, KEY_KP4 */ - 0x0102004c /* row 1, col 2, KEY_KP5 */ - 0x0103004d /* row 1, col 3, KEY_KP6 */ - 0x02000047 /* row 2, col 0, KEY_KP7 */ - 0x02010048 /* row 2, col 1, KEY_KP8 */ - 0x02020049 /* row 2, col 2, KEY_KP9 */ - >; - gpio-activelow; - wakeup-source; - debounce-delay-ms = <100>; - col-scan-delay-us = <5000>; - linux,no-autorepeat; - }; - - spi_gpio: spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_spi_gpio_pins>; - - sck-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - num-chipselects = <3>; - cs-gpios = < - &gpio2 27 GPIO_ACTIVE_LOW - &gpio3 8 GPIO_ACTIVE_LOW - &gpio3 9 GPIO_ACTIVE_LOW - >; - /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ - status = "disabled"; - }; -}; - -/* 2nd TX-Std UART - (A)UART1 */ -&auart1 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; -}; - -/* 3rd TX-Std UART - (A)UART3 */ -&auart3 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&digctl { - status = "okay"; -}; - -/* 1st TX-Std UART - (D)UART */ -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - clocks = <&mclk>; - }; - - gpio5: pca953x@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_pca9554_pins>; - interrupt-parent = <&gpio3>; - interrupts = <28 IRQ_TYPE_NONE>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_edt_ft5x06_pins>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_tsc2007_pins>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = /bits/ 16 <660>; - }; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - trickle-resistor-ohms = <250>; - trickle-diode-disable; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; - lcd-supply = <®_lcd>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - display-timings { - native-mode = <&timing5>; - timing0: timing0 { - panel-name = "VGA"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing1: timing1 { - panel-name = "ETV570"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing2: timing2 { - panel-name = "ET0350"; - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing3: timing3 { - panel-name = "ET0430"; - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing4: timing4 { - panel-name = "ET0500", "ET0700"; - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing5: timing5 { - panel-name = "ETQ570"; - clock-frequency = <6400000>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default", "gpio_mode"; - pinctrl-0 = <&mac0_pins_a>; - pinctrl-1 = <&tx28_mac0_pins_gpio>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - /* not enabled by default */ -}; - -&mxs_rtc { - status = "okay"; -}; - -&ocotp { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ - MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ - MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__GPIO_1_0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 { - reg = <0>; - fsl,pinmux-ids = < - /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ - MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__GPIO_4_0 - MX28_PAD_ENET0_MDIO__GPIO_4_1 - MX28_PAD_ENET0_RX_EN__GPIO_4_2 - MX28_PAD_ENET0_RXD0__GPIO_4_3 - MX28_PAD_ENET0_RXD1__GPIO_4_4 - MX28_PAD_ENET0_TX_EN__GPIO_4_6 - MX28_PAD_ENET0_TXD0__GPIO_4_7 - MX28_PAD_ENET0_TXD1__GPIO_4_8 - MX28_PAD_ENET_CLK__GPIO_4_16 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_pca9554_pins: tx28-pca9554-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_spi_gpio_pins: spi-gpiogrp@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - MX28_PAD_SSP3_SCK__GPIO_2_24 - MX28_PAD_SSP3_MOSI__GPIO_2_25 - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SS0__GPIO_2_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_tsc2007_pins: tx28-tsc2007-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - - tx28_usbphy0_pins: tx28-usbphy0-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ - MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_usbphy1_pins: tx28-usbphy1-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ - MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_b>; - fsl,saif-master; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default", "special"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; -}; - -&ssp3 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_a>; - clock-frequency = <57600000>; - status = "okay"; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - disable-over-current; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy0_pins>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbphy1 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy1_pins>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/imx28-xea.dts deleted file mode 100644 index a400c108f66a..000000000000 --- a/arch/arm/boot/dts/imx28-xea.dts +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2021 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx28-lwe.dtsi" - -/ { - compatible = "lwn,imx28-xea", "fsl,imx28"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a &hog_pins_tiva>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPIO_0_0 - MX28_PAD_GPMI_D02__GPIO_0_2 - MX28_PAD_GPMI_D05__GPIO_0_5 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_RDY0__GPIO_0_20 - MX28_PAD_GPMI_RDY1__GPIO_0_21 - MX28_PAD_GPMI_RDY2__GPIO_0_22 - MX28_PAD_GPMI_RDN__GPIO_0_24 - MX28_PAD_GPMI_CLE__GPIO_0_27 - MX28_PAD_LCD_VSYNC__GPIO_1_28 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP2_SS1__GPIO_2_20 - MX28_PAD_SSP2_SS2__GPIO_2_21 - MX28_PAD_LCD_D00__GPIO_1_0 - MX28_PAD_LCD_D01__GPIO_1_1 - MX28_PAD_LCD_D02__GPIO_1_2 - MX28_PAD_LCD_D03__GPIO_1_3 - MX28_PAD_LCD_D04__GPIO_1_4 - MX28_PAD_LCD_D05__GPIO_1_5 - MX28_PAD_LCD_D06__GPIO_1_6 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - hog_pins_tiva: hog@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY3__GPIO_0_23 - MX28_PAD_GPMI_WRN__GPIO_0_25 - >; - fsl,voltage = ; - fsl,pull-up = ; - }; - - hog_pins_coding: hog@2 { - reg = <2>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D01__GPIO_0_1 - MX28_PAD_GPMI_D03__GPIO_0_3 - MX28_PAD_GPMI_D04__GPIO_0_4 - MX28_PAD_GPMI_D06__GPIO_0_6 - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -®_fec_3v3 { - gpio = <&gpio0 0 0>; -}; - -®_usb_5v { - gpio = <&gpio0 2 0>; -}; - -&spi2_pins_a { - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__GPIO_2_19 - >; -}; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi deleted file mode 100644 index 29e37b1fae66..000000000000 --- a/arch/arm/boot/dts/imx28.dtsi +++ /dev/null @@ -1,1334 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -#include -#include "imx28-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&icoll>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &mac0; - ethernet1 = &mac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - saif0 = &saif0; - saif1 = &saif1; - serial0 = &auart0; - serial1 = &auart1; - serial2 = &auart2; - serial3 = &auart3; - serial4 = &auart4; - spi0 = &ssp1; - spi1 = &ssp2; - usbphy0 = &usbphy0; - usbphy1 = &usbphy1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - apb@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x80000>; - ranges; - - apbh@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x3c900>; - ranges; - - icoll: interrupt-controller@80000000 { - compatible = "fsl,imx28-icoll", "fsl,icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80000000 0x2000>; - }; - - hsadc: hsadc@80002000 { - reg = <0x80002000 0x2000>; - interrupts = <13>; - dmas = <&dma_apbh 12>; - dma-names = "rx"; - status = "disabled"; - }; - - dma_apbh: dma-controller@80004000 { - compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 25>; - }; - - perfmon: perfmon@80006000 { - reg = <0x80006000 0x800>; - interrupts = <27>; - status = "disabled"; - }; - - gpmi: nand-controller@8000c000 { - compatible = "fsl,imx28-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <41>; - interrupt-names = "bch"; - clocks = <&clks 50>; - clock-names = "gpmi_io"; - assigned-clocks = <&clks 13>; - assigned-clock-parents = <&clks 10>; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp0: spi@80010000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80010000 0x2000>; - interrupts = <96>; - clocks = <&clks 46>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp1: spi@80012000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80012000 0x2000>; - interrupts = <97>; - clocks = <&clks 47>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80014000 0x2000>; - interrupts = <98>; - clocks = <&clks 48>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp3: spi@80016000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80016000 0x2000>; - interrupts = <99>; - clocks = <&clks 49>; - dmas = <&dma_apbh 3>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - pinctrl: pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <0>; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <1>; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <2>; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@3 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <3>; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@4 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <4>; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - duart_pins_a: duart@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__DUART_RX - MX28_PAD_PWM1__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - duart_pins_b: duart@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - duart_4pins_a: duart-4pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - MX28_PAD_AUART0_RX__DUART_CTS - MX28_PAD_AUART0_TX__DUART_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_a: gpmi-nand@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPMI_D0 - MX28_PAD_GPMI_D01__GPMI_D1 - MX28_PAD_GPMI_D02__GPMI_D2 - MX28_PAD_GPMI_D03__GPMI_D3 - MX28_PAD_GPMI_D04__GPMI_D4 - MX28_PAD_GPMI_D05__GPMI_D5 - MX28_PAD_GPMI_D06__GPMI_D6 - MX28_PAD_GPMI_D07__GPMI_D7 - MX28_PAD_GPMI_CE0N__GPMI_CE0N - MX28_PAD_GPMI_RDY0__GPMI_READY0 - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_ALE__GPMI_ALE - MX28_PAD_GPMI_CLE__GPMI_CLE - MX28_PAD_GPMI_RESETN__GPMI_RESETN - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_status_cfg: gpmi-status-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_RESETN__GPMI_RESETN - >; - fsl,drive-strength = ; - }; - - auart0_pins_a: auart0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - MX28_PAD_AUART0_CTS__AUART0_CTS - MX28_PAD_AUART0_RTS__AUART0_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_2pins_a: auart0-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_pins_a: auart1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - MX28_PAD_AUART1_CTS__AUART1_CTS - MX28_PAD_AUART1_RTS__AUART1_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_2pins_a: auart1-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_2pins_a: auart2-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__AUART2_RX - MX28_PAD_SSP2_MOSI__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_2pins_b: auart2-2pins@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_pins_a: auart2-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX - MX28_PAD_AUART2_CTS__AUART2_CTS - MX28_PAD_AUART2_RTS__AUART2_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_pins_a: auart3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - MX28_PAD_AUART3_CTS__AUART3_CTS - MX28_PAD_AUART3_RTS__AUART3_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_2pins_a: auart3-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_MISO__AUART3_RX - MX28_PAD_SSP2_SS0__AUART3_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_2pins_b: auart3-2pins@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart4_2pins_a: auart4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__AUART4_TX - MX28_PAD_SSP3_MOSI__AUART4_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart4_2pins_b: auart4@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__AUART4_RX - MX28_PAD_AUART0_RTS__AUART4_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_a: mac0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET_CLK__CLKCTRL_ENET - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_b: mac0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_RXD2__ENET0_RXD2 - MX28_PAD_ENET0_RXD3__ENET0_RXD3 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET0_TXD2__ENET0_TXD2 - MX28_PAD_ENET0_TXD3__ENET0_TXD3 - MX28_PAD_ENET_CLK__CLKCTRL_ENET - MX28_PAD_ENET0_COL__ENET0_COL - MX28_PAD_ENET0_CRS__ENET0_CRS - MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK - MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac1_pins_a: mac1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_CRS__ENET1_RX_EN - MX28_PAD_ENET0_RXD2__ENET1_RXD0 - MX28_PAD_ENET0_RXD3__ENET1_RXD1 - MX28_PAD_ENET0_COL__ENET1_TX_EN - MX28_PAD_ENET0_TXD2__ENET1_TXD0 - MX28_PAD_ENET0_TXD3__ENET1_TXD1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_4bit_pins_a: mmc0-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_cd_cfg: mmc0-cd-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc0_sck_cfg: mmc0-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - mmc1_4bit_pins_a: mmc1-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__SSP1_D0 - MX28_PAD_GPMI_D01__SSP1_D1 - MX28_PAD_GPMI_D02__SSP1_D2 - MX28_PAD_GPMI_D03__SSP1_D3 - MX28_PAD_GPMI_RDY1__SSP1_CMD - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT - MX28_PAD_GPMI_WRN__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc1_cd_cfg: mmc1-cd-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc1_sck_cfg: mmc1-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_WRN__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - - mmc2_4bit_pins_a: mmc2-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP1_SCK__SSP2_D1 - MX28_PAD_SSP1_CMD__SSP2_D2 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_4bit_pins_b: mmc2-4bit@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__SSP2_D3 - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_cd_cfg: mmc2-cd-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_a: mmc2-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_b: mmc2-sck-cfg@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - i2c0_pins_a: i2c0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__I2C0_SCL - MX28_PAD_I2C0_SDA__I2C0_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c0_pins_b: i2c0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__I2C0_SCL - MX28_PAD_AUART0_TX__I2C0_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c1_pins_a: i2c1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__I2C1_SCL - MX28_PAD_PWM1__I2C1_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c1_pins_b: i2c1@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_CTS__I2C1_SCL - MX28_PAD_AUART2_RTS__I2C1_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif0_pins_a: saif0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif0_pins_b: saif0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif1_pins_a: saif1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm0_pins_a: pwm0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__PWM_0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm2_pins_a: pwm2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__PWM_2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm3_pins_a: pwm3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__PWM_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm3_pins_b: pwm3@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__PWM_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm4_pins_a: pwm4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM4__PWM_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_24bit_pins_a: lcdif-24bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_a: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_16bit_pins_a: lcdif-16bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_sync_pins_a: lcdif-sync@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - can0_pins_a: can0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY2__CAN0_TX - MX28_PAD_GPMI_RDY3__CAN0_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - can1_pins_a: can1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__CAN1_TX - MX28_PAD_GPMI_CE3N__CAN1_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_a: spi2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__SSP2_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_a: spi3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__SSP3_D4 - MX28_PAD_AUART2_TX__SSP3_D5 - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_b: spi3@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_pins_a: usb0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__USB0_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_pins_b: usb0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_CTS__USB0_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb1_pins_a: usb1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS1__USB1_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb1_pins_b: usb1@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__USB1_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_id_pins_a: usb0id@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RTS__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_id_pins_b: usb0id1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - - digctl: digctl@8001c000 { - compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; - reg = <0x8001c000 0x2000>; - interrupts = <89>; - status = "disabled"; - }; - - etm: etm@80022000 { - reg = <0x80022000 0x2000>; - status = "disabled"; - }; - - dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 26>; - }; - - dcp: crypto@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <52 53 54>; - status = "okay"; - }; - - pxp: pxp@8002a000 { - reg = <0x8002a000 0x2000>; - interrupts = <39>; - status = "disabled"; - }; - - ocotp: efuse@8002c000 { - compatible = "fsl,imx28-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 25>; - }; - - axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; - status = "disabled"; - }; - - lcdif: lcdif@80030000 { - compatible = "fsl,imx28-lcdif"; - reg = <0x80030000 0x2000>; - interrupts = <38>; - clocks = <&clks 55>; - dmas = <&dma_apbh 13>; - dma-names = "rx"; - status = "disabled"; - }; - - can0: can@80032000 { - compatible = "fsl,imx28-flexcan"; - reg = <0x80032000 0x2000>; - interrupts = <8>; - clocks = <&clks 58>, <&clks 58>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: can@80034000 { - compatible = "fsl,imx28-flexcan"; - reg = <0x80034000 0x2000>; - interrupts = <9>; - clocks = <&clks 59>, <&clks 59>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - simdbg: simdbg@8003c000 { - reg = <0x8003c000 0x200>; - status = "disabled"; - }; - - simgpmisel: simgpmisel@8003c200 { - reg = <0x8003c200 0x100>; - status = "disabled"; - }; - - simsspsel: simsspsel@8003c300 { - reg = <0x8003c300 0x100>; - status = "disabled"; - }; - - simmemsel: simmemsel@8003c400 { - reg = <0x8003c400 0x100>; - status = "disabled"; - }; - - gpiomon: gpiomon@8003c500 { - reg = <0x8003c500 0x100>; - status = "disabled"; - }; - - simenet: simenet@8003c700 { - reg = <0x8003c700 0x100>; - status = "disabled"; - }; - - armjtag: armjtag@8003c800 { - reg = <0x8003c800 0x100>; - status = "disabled"; - }; - }; - - apbx@80040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80040000 0x40000>; - ranges; - - clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; - }; - - saif0: saif@80042000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx28-saif"; - reg = <0x80042000 0x2000>; - interrupts = <59>; - #clock-cells = <0>; - clocks = <&clks 53>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - power: power@80044000 { - reg = <0x80044000 0x2000>; - status = "disabled"; - }; - - saif1: saif@80046000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx28-saif"; - reg = <0x80046000 0x2000>; - interrupts = <58>; - clocks = <&clks 54>; - dmas = <&dma_apbx 5>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - lradc: lradc@80050000 { - compatible = "fsl,imx28-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <10 14 15 16 17 18 19 - 20 21 22 23 24 25>; - status = "disabled"; - clocks = <&clks 41>; - #io-channel-cells = <1>; - }; - - spdif: spdif@80054000 { - reg = <0x80054000 0x2000>; - interrupts = <45>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; - status = "disabled"; - }; - - mxs_rtc: rtc@80056000 { - compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x80056000 0x2000>; - interrupts = <29>; - }; - - i2c0: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x80058000 0x2000>; - interrupts = <111>; - clock-frequency = <100000>; - dmas = <&dma_apbx 6>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - i2c1: i2c@8005a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x8005a000 0x2000>; - interrupts = <110>; - clock-frequency = <100000>; - dmas = <&dma_apbx 7>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - pwm: pwm@80064000 { - compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - clocks = <&clks 44>; - #pwm-cells = <2>; - fsl,pwm-number = <8>; - status = "disabled"; - }; - - timer: timrot@80068000 { - compatible = "fsl,imx28-timrot", "fsl,timrot"; - reg = <0x80068000 0x2000>; - interrupts = <48 49 50 51>; - clocks = <&clks 26>; - }; - - auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart1: serial@8006c000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <113>; - dmas = <&dma_apbx 10>, <&dma_apbx 11>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart2: serial@8006e000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006e000 0x2000>; - interrupts = <114>; - dmas = <&dma_apbx 12>, <&dma_apbx 13>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart3: serial@80070000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x80070000 0x2000>; - interrupts = <115>; - dmas = <&dma_apbx 14>, <&dma_apbx 15>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart4: serial@80072000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x80072000 0x2000>; - interrupts = <116>; - dmas = <&dma_apbx 0>, <&dma_apbx 1>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - duart: serial@80074000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80074000 0x1000>; - interrupts = <47>; - clocks = <&clks 45>, <&clks 26>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; - }; - - usbphy0: usbphy@8007c000 { - compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; - reg = <0x8007c000 0x2000>; - clocks = <&clks 62>; - status = "disabled"; - }; - - usbphy1: usbphy@8007e000 { - compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; - reg = <0x8007e000 0x2000>; - clocks = <&clks 63>; - status = "disabled"; - }; - }; - }; - - ahb@80080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80080000 0x80000>; - ranges; - - usb0: usb@80080000 { - compatible = "fsl,imx28-usb", "fsl,imx27-usb"; - reg = <0x80080000 0x10000>; - interrupts = <93>; - clocks = <&clks 60>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usb1: usb@80090000 { - compatible = "fsl,imx28-usb", "fsl,imx27-usb"; - reg = <0x80090000 0x10000>; - interrupts = <92>; - clocks = <&clks 61>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - dflpt: dflpt@800c0000 { - reg = <0x800c0000 0x10000>; - status = "disabled"; - }; - - mac0: ethernet@800f0000 { - compatible = "fsl,imx28-fec"; - reg = <0x800f0000 0x4000>; - interrupts = <101>; - clocks = <&clks 57>, <&clks 57>, <&clks 64>; - clock-names = "ipg", "ahb", "enet_out"; - status = "disabled"; - }; - - mac1: ethernet@800f4000 { - compatible = "fsl,imx28-fec"; - reg = <0x800f4000 0x4000>; - interrupts = <102>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - eth_switch: switch@800f8000 { - reg = <0x800f8000 0x8000>; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&lradc 8>; - }; -}; diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts deleted file mode 100644 index d87eee3f9b3c..000000000000 --- a/arch/arm/boot/dts/imx31-bug.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Denis 'GNUtoo' Carikli - */ - -/dts-v1/; -#include "imx31.dtsi" - -/ { - model = "Buglabs i.MX31 Bug 1.x"; - compatible = "buglabs,imx31-bug", "fsl,imx31"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128M */ - }; -}; - -&uart5 { - uart-has-rtscts; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts deleted file mode 100644 index d17abdfb6330..000000000000 --- a/arch/arm/boot/dts/imx31-lite.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (C) 2016-2018 Vladimir Zapolskiy - -/dts-v1/; - -#include "imx31.dtsi" - -#include -#include - -/ { - model = "LogicPD i.MX31 Lite"; - compatible = "logicpd,imx31-lite", "fsl,imx31"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - led1 { - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ata { - status = "okay"; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13783"; - reg = <0>; - spi-cs-high; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - regulators { - sw1a { /* QVCC */ - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - sw1b { /* QVCC */ - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw2b { /* NVCC10 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - violo { /* NVCC1 and NVCC7 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - viohi { /* VIOHI */ - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vaudio { /* VAUDIO */ - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vcam { /* NVCC4 */ - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc2 { /* NVCC3 */ - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&uart1 { - uart-has-rtscts; - status = "okay"; -}; - -/* Routed to the extension board */ -&uart2 { - uart-has-rtscts; - status = "okay"; -}; - -/* Routed to the extension board */ -&uart3 { - uart-has-rtscts; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x0 0x200000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; - }; - - ethernet@4,0 { - compatible = "smsc,lan9117", "smsc,lan9115"; - reg = <4 0x0 0x100>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,irq-push-pull; - fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; - }; -}; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi deleted file mode 100644 index 95c05f17a6d5..000000000000 --- a/arch/arm/boot/dts/imx31.dtsi +++ /dev/null @@ -1,371 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2016-2018 Vladimir Zapolskiy -// Copyright 2012 Denis 'GNUtoo' Carikli - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &spi1; - spi1 = &spi2; - spi2 = &spi3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - avic: interrupt-controller@68000000 { - compatible = "fsl,imx31-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x100000>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - iram: sram@1fffc000 { - compatible = "mmio-sram"; - reg = <0x1fffc000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1fffc000 0x4000>; - }; - - aips1: bus@43f00000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - i2c1: i2c@43f80000 { - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; - reg = <0x43f80000 0x4000>; - interrupts = <10>; - clocks = <&clks 33>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; - reg = <0x43f84000 0x4000>; - interrupts = <3>; - clocks = <&clks 35>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ata: ata@43f8c000 { - compatible = "fsl,imx31-pata", "fsl,imx27-pata"; - reg = <0x43f8c000 0x4000>; - interrupts = <15>; - clocks = <&clks 26>; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 10>, <&clks 30>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - interrupts = <32>; - clocks = <&clks 10>, <&clks 31>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; - reg = <0x43f98000 0x4000>; - interrupts = <4>; - clocks = <&clks 34>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@43fa4000 { - compatible = "fsl,imx31-cspi"; - reg = <0x43fa4000 0x4000>; - interrupts = <14>; - clocks = <&clks 10>, <&clks 53>; - clock-names = "ipg", "per"; - dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - interrupts = <24>; - clocks = <&clks 46>; - status = "disabled"; - }; - - uart4: serial@43fb0000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43fb0000 0x4000>; - clocks = <&clks 10>, <&clks 49>; - clock-names = "ipg", "per"; - interrupts = <46>; - status = "disabled"; - }; - - uart5: serial@43fb4000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43fb4000 0x4000>; - interrupts = <47>; - clocks = <&clks 10>, <&clks 50>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x100000>; - ranges; - - sdhci1: mmc@50004000 { - compatible = "fsl,imx31-mmc"; - reg = <0x50004000 0x4000>; - interrupts = <9>; - clocks = <&clks 10>, <&clks 20>; - clock-names = "ipg", "per"; - dmas = <&sdma 20 3 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - sdhci2: mmc@50008000 { - compatible = "fsl,imx31-mmc"; - reg = <0x50008000 0x4000>; - interrupts = <8>; - clocks = <&clks 10>, <&clks 21>; - clock-names = "ipg", "per"; - dmas = <&sdma 21 3 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <18>; - clocks = <&clks 10>, <&clks 48>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spi2: spi@50010000 { - compatible = "fsl,imx31-cspi"; - reg = <0x50010000 0x4000>; - interrupts = <13>; - clocks = <&clks 10>, <&clks 54>; - clock-names = "ipg", "per"; - dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - iim: efuse@5001c000 { - compatible = "fsl,imx31-iim", "fsl,imx27-iim"; - reg = <0x5001c000 0x1000>; - interrupts = <19>; - clocks = <&clks 25>; - }; - }; - - bus@53f00000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>, <53>; - #clock-cells = <1>; - }; - - spi3: spi@53f84000 { - compatible = "fsl,imx31-cspi"; - reg = <0x53f84000 0x4000>; - interrupts = <17>; - clocks = <&clks 10>, <&clks 28>; - clock-names = "ipg", "per"; - dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpt: timer@53f90000 { - compatible = "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - interrupts = <29>; - clocks = <&clks 10>, <&clks 22>; - clock-names = "ipg", "per"; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx31-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <56>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rng@53fb0000 { - compatible = "fsl,imx31-rnga"; - reg = <0x53fb0000 0x4000>; - interrupts = <22>; - clocks = <&clks 29>; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx31-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx31-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: dma-controller@53fd4000 { - compatible = "fsl,imx31-sdma"; - reg = <0x53fd4000 0x4000>; - interrupts = <34>; - clocks = <&clks 10>, <&clks 27>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; - }; - - rtc: rtc@53fd8000 { - compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; - reg = <0x53fd8000 0x4000>; - interrupts = <25>; - clocks = <&clks 2>, <&clks 40>; - clock-names = "ref", "ipg"; - }; - - wdog: watchdog@53fdc000 { - compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 41>; - interrupts = <55>; - }; - - pwm: pwm@53fe0000 { - compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; - reg = <0x53fe0000 0x4000>; - interrupts = <26>; - clocks = <&clks 10>, <&clks 42>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - emi@b8000000 { /* External Memory Interface */ - compatible = "simple-bus"; - reg = <0xb8000000 0x5000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - nfc: nand@b8000000 { - compatible = "fsl,imx31-nand", "fsl,imx27-nand"; - reg = <0xb8000000 0x1000>; - interrupts = <33>; - clocks = <&clks 9>; - dmas = <&sdma 30 17 0>; - dma-names = "rx-tx"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - weim: weim@b8002000 { - compatible = "fsl,imx31-weim", "fsl,imx27-weim"; - reg = <0xb8002000 0x1000>; - clocks = <&clks 56>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xa0000000 0x08000000 - 1 0 0xa8000000 0x08000000 - 2 0 0xb0000000 0x02000000 - 3 0 0xb2000000 0x02000000 - 4 0 0xb4000000 0x02000000 - 5 0 0xb6000000 0x02000000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi deleted file mode 100644 index 17bd2a97609a..000000000000 --- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx35.dtsi" - -/ { - model = "Eukrea CPUIMX35"; - compatible = "eukrea,cpuimx35", "fsl,imx35"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128M */ - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsc2007: tsc2007@48 { - compatible = "ti,tsc2007"; - gpios = <&gpio3 2 0>; - interrupt-parent = <&gpio3>; - interrupts = <0x2 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007_1>; - reg = <0x48>; - ti,x-plate-ohms = <180>; - }; -}; - -&iomuxc { - imx35-eukrea { - pinctrl_fec: fecgrp { - fsl,pins = < - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 - MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX35_PAD_FEC_COL__FEC_COL 0x80000000 - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 - MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 - MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 - MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 - >; - }; - - pinctrl_tsc2007_1: tsc2007grp-1 { - fsl,pins = ; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts deleted file mode 100644 index 7f4f812b0811..000000000000 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -/dts-v1/; - -#include -#include -#include "imx35-eukrea-cpuimx35.dtsi" - -/ { - model = "Eukrea CPUIMX35"; - compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bp1>; - - button { - label = "BP1"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - linux,input-type = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led1>; - - led1 { - label = "led1"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx35-eukrea-tlv320aic23"; - ssi-controller = <&ssi1>; - fsl,mux-int-port = <1>; - fsl,mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx35-eukrea { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 - MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 - MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 - >; - }; - - pinctrl_bp1: bp1grp { - fsl,pins = ; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ - >; - }; - - pinctrl_led1: led1grp { - fsl,pins = ; - }; - - pinctrl_reg_lcd_3v3: reg-lcd-3v3 { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 - MX35_PAD_CTS1__UART1_CTS 0x1c5 - MX35_PAD_RTS1__UART1_RTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 - MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 - MX35_PAD_RTS2__UART2_RTS 0x1c5 - MX35_PAD_CTS2__UART2_CTS 0x1c5 - >; - }; - }; -}; - -&ssi1 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - phy_type = "serial"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "otg"; - external-vbus-divider; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts deleted file mode 100644 index ddce0a844758..000000000000 --- a/arch/arm/boot/dts/imx35-pdk.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Eukréa Electromatique -// Copyright 2014 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx35.dtsi" - -/ { - model = "Freescale i.MX35 Product Development Kit"; - compatible = "fsl,imx35-pdk", "fsl,imx35"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>, - <0x90000000 0x8000000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&iomuxc { - imx35-pdk { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 - MX35_PAD_CTS1__UART1_CTS 0x1c5 - MX35_PAD_RTS1__UART1_RTS 0x1c5 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx35-pinfunc.h b/arch/arm/boot/dts/imx35-pinfunc.h deleted file mode 100644 index 9d6cc9564b72..000000000000 --- a/arch/arm/boot/dts/imx35-pinfunc.h +++ /dev/null @@ -1,966 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX35_PINFUNC_H -#define __DTS_IMX35_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 -#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 -#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 -#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 -#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 -#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 -#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 -#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 -#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 -#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0 -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0 -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 -#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 -#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0 -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0 -#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0 -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0 -#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0 -#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0 -#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0 -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0 -#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0 -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0 -#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0 -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0 -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0 -#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0 -#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0 -#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0 -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0 -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0 -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0 -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0 -#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0 -#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 -#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0 -#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0 -#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0 -#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0 -#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0 -#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0 -#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0 -#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0 -#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0 -#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0 -#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0 -#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0 -#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0 -#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0 -#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0 -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0 -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0 -#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0 -#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0 -#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0 -#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0 -#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0 -#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0 -#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0 -#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0 -#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0 -#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0 -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0 -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0 -#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0 -#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0 -#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0 -#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0 -#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0 -#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0 -#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0 -#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0 -#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0 -#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0 -#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0 -#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0 -#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0 -#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0 -#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0 -#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0 -#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0 -#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0 -#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0 -#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0 -#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0 -#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0 -#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0 -#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0 -#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0 -#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0 -#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0 -#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0 -#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0 -#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0 -#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0 -#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0 -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0 -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0 -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0 -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0 -#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0 -#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0 -#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0 -#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0 -#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0 -#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 -#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0 -#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0 -#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0 -#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0 -#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 -#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 -#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0 -#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0 -#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1 -#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 -#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0 -#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 -#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0 -#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0 -#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0 -#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0 -#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0 -#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0 -#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0 -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0 -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0 -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0 -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0 -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0 -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0 -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0 -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0 -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0 -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0 -#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0 -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0 -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0 -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0 -#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0 -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0 -#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0 -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0 -#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0 -#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0 -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0 -#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0 -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0 -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0 -#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0 -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0 -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0 -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0 -#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0 -#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0 -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0 -#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0 -#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0 -#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0 -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0 -#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0 -#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0 -#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0 -#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0 -#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0 -#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0 -#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0 -#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0 -#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0 -#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0 -#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0 -#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0 -#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0 -#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0 -#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0 -#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0 -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0 -#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0 -#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1 -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0 -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0 -#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0 -#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1 -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0 -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0 -#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0 -#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1 -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0 -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0 -#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0 -#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0 -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0 -#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0 -#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0 -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0 -#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0 -#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0 -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0 -#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0 -#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0 -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0 -#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0 -#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0 -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0 -#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0 -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0 -#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0 -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0 -#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0 -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0 -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0 -#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0 -#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0 -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0 -#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0 -#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0 -#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0 -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0 -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0 -#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0 -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0 -#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0 -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0 -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0 -#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0 -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0 -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0 -#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0 -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0 -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0 -#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0 -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0 -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0 -#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0 -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0 -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0 -#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0 -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0 -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0 -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0 -#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0 -#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1 -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0 -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0 -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0 -#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0 -#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1 -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0 -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0 -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0 -#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0 -#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0 -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0 -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0 -#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0 -#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0 -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0 -#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0 -#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1 -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0 -#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0 -#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1 -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0 -#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0 -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0 -#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0 -#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 -#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1 -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0 -#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0 -#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1 -#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0 -#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1 -#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0 -#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1 -#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0 -#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1 -#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0 -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0 -#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0 -#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0 -#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1 -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0 -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0 -#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1 -#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 -#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0 -#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0 -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0 -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0 -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0 -#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0 -#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0 -#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0 -#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0 -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0 -#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1 -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0 -#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0 -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0 -#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0 -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0 -#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1 -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0 -#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0 -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0 -#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0 -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0 -#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1 -#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0 -#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1 -#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2 -#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0 -#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0 -#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0 -#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0 -#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1 -#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0 -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1 -#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0 -#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1 -#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0 -#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0 -#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0 -#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1 -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1 -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1 -#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0 -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1 -#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0 -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0 -#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0 -#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1 -#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0 -#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0 -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0 -#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0 -#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1 -#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0 -#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0 -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0 -#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0 -#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1 -#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1 -#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1 -#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0 -#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0 -#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0 -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0 -#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0 -#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1 -#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1 -#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1 -#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0 -#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0 -#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0 -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0 -#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0 -#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0 -#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0 -#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0 -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2 -#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0 -#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0 -#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0 -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1 -#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1 -#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1 -#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0 -#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0 -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0 -#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0 -#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0 -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0 -#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0 -#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1 -#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0 -#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0 -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0 -#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0 -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0 -#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0 -#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0 -#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0 -#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0 -#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0 -#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0 -#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0 -#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0 -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1 -#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0 -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0 -#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1 -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0 -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0 -#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0 -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0 -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0 -#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0 -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0 -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0 -#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0 -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0 -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0 -#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0 -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0 -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0 -#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0 -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0 -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0 -#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0 -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0 -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0 -#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0 -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0 -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0 -#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0 -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0 -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0 -#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0 -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0 -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0 -#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0 -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0 -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0 -#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0 -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0 -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0 -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0 -#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0 -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0 -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0 -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0 -#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0 -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0 -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0 -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0 -#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0 -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0 -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0 -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0 -#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0 -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0 -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0 -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0 -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0 -#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0 -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0 -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0 -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0 -#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0 -#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0 -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0 -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0 -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0 -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1 -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1 -#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0 -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0 -#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0 -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0 -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0 -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0 -#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0 -#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0 -#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0 -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0 -#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0 -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0 -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0 -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0 -#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0 -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0 -#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0 -#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0 -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0 -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0 -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0 -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0 -#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0 -#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0 -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0 -#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0 -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0 -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0 -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0 -#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0 -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0 -#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0 -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0 -#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0 -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0 -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0 -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0 -#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0 -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1 -#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0 -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0 -#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0 -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0 -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0 -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0 -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2 -#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0 -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0 -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0 -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0 -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0 -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0 -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0 -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0 -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0 -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0 -#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2 -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0 -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0 -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0 -#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2 -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0 -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0 -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0 -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0 -#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1 -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0 -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0 -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0 -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0 -#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1 -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0 -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0 -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0 -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0 -#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2 -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0 -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0 -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0 -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2 -#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2 -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0 -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0 -#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0 -#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0 -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2 -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0 -#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2 -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0 -#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0 -#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0 -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0 -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0 -#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2 -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0 -#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2 -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0 -#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1 -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0 -#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1 -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0 -#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1 -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0 -#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0 -#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2 -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0 -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2 -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0 -#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2 -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0 -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3 -#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0 -#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2 -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0 -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2 -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0 -#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1 -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2 -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0 -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1 -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0 -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1 -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0 -#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1 -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3 -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0 -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0 -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1 -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0 -#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1 -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0 -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1 -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1 -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0 -#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1 -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0 -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0 -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1 -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0 -#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1 -#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0 -#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1 -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0 -#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1 -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0 -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0 -#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0 -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0 -#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1 -#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1 -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0 -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0 -#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0 -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1 -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1 -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0 -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1 -#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1 -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0 -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0 -#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1 -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0 -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0 -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2 -#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1 -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1 -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1 -#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2 -#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1 -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0 -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0 -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1 -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1 -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0 -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2 -#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1 -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0 -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0 -#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0 -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0 -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1 -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3 -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0 -#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1 -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0 -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1 -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4 -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1 -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1 -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0 -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1 -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1 -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0 -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1 -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1 -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1 -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2 -#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1 -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1 -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1 -#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1 -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1 -#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1 -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0 -#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1 -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2 -#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0 -#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1 -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1 -#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0 -#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1 -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0 -#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1 -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2 -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0 -#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1 -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0 -#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1 -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3 -#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1 -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3 -#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1 -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2 -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2 -#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1 -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2 -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2 -#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1 -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0 -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0 -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3 -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2 -#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1 -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0 -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0 -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3 -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2 -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1 -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0 -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2 -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2 -#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1 -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2 -#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2 -#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1 -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2 -#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2 -#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0 -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2 -#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2 -#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0 -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0 -#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0 -#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0 -#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0 -#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1 -#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0 -#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1 -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1 -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3 -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1 -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3 -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1 -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5 -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1 -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0 -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0 -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3 -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1 -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4 -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1 -#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2 -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1 -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3 -#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1 -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0 -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0 -#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0 -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1 -#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0 -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1 -#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3 -#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1 -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0 -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0 -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0 -#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0 -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1 -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2 -#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1 -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0 -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0 -#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0 -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1 -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2 -#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1 -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0 -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3 -#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0 -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1 -#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1 -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0 -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0 -#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0 -#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0 -#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0 -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1 -#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1 -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0 -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0 -#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0 -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2 -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1 -#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1 -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0 -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0 -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2 -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4 -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1 -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1 -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3 -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3 -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1 -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1 -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0 -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5 -#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0 -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3 -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0 -#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1 -#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0 -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4 -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0 -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2 -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1 -#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0 -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4 -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1 -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1 -#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0 -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3 -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1 -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1 -#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0 -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3 -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1 -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1 -#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0 -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3 -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1 -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1 -#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3 -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1 -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1 -#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0 -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0 -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0 - -#endif /* __DTS_IMX35_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi deleted file mode 100644 index 2d20e5541acc..000000000000 --- a/arch/arm/boot/dts/imx35.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2012 Steffen Trumtrar, Pengutronix -// -// based on imx27.dtsi - -#include "imx35-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &spi1; - spi1 = &spi2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - avic: avic-interrupt-controller@68000000 { - compatible = "fsl,imx35-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x10000000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - L2: cache-controller@30000000 { - compatible = "arm,l210-cache"; - reg = <0x30000000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - aips1: bus@43f00000 { - compatible = "fsl,aips", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - i2c1: i2c@43f80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f80000 0x4000>; - clocks = <&clks 51>; - clock-names = "ipg_per"; - interrupts = <10>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f84000 0x4000>; - clocks = <&clks 53>; - clock-names = "ipg_per"; - interrupts = <3>; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - clocks = <&clks 9>, <&clks 70>; - clock-names = "ipg", "per"; - interrupts = <45>; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - clocks = <&clks 9>, <&clks 71>; - clock-names = "ipg", "per"; - interrupts = <32>; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f98000 0x4000>; - clocks = <&clks 52>; - clock-names = "ipg_per"; - interrupts = <4>; - status = "disabled"; - }; - - ssi1: ssi@43fa0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; - reg = <0x43fa0000 0x4000>; - interrupts = <11>; - clocks = <&clks 68>; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - spi1: spi@43fa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-cspi"; - reg = <0x43fa4000 0x4000>; - clocks = <&clks 35 &clks 35>; - clock-names = "ipg", "per"; - interrupts = <14>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - compatible = "fsl,imx35-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - interrupts = <24>; - clocks = <&clks 56>; - status = "disabled"; - }; - - iomuxc: iomuxc@43fac000 { - compatible = "fsl,imx35-iomuxc"; - reg = <0x43fac000 0x4000>; - }; - }; - - spba: spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x100000>; - ranges; - - uart3: serial@5000c000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - clocks = <&clks 9>, <&clks 72>; - clock-names = "ipg", "per"; - interrupts = <18>; - status = "disabled"; - }; - - spi2: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-cspi"; - reg = <0x50010000 0x4000>; - interrupts = <13>; - clocks = <&clks 36 &clks 36>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - fec: ethernet@50038000 { - compatible = "fsl,imx35-fec", "fsl,imx27-fec"; - reg = <0x50038000 0x4000>; - clocks = <&clks 46>, <&clks 8>; - clock-names = "ipg", "ahb"; - interrupts = <57>; - status = "disabled"; - }; - }; - - aips2: bus@53f00000 { - compatible = "fsl,aips", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000 { - compatible = "fsl,imx35-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; - }; - - gpt: timer@53f90000 { - compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - interrupts = <29>; - clocks = <&clks 9>, <&clks 50>; - clock-names = "ipg", "per"; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <56>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - esdhc1: mmc@53fb4000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <7>; - clocks = <&clks 9>, <&clks 8>, <&clks 43>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: mmc@53fb8000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb8000 0x4000>; - interrupts = <8>; - clocks = <&clks 9>, <&clks 8>, <&clks 44>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc3: mmc@53fbc000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fbc000 0x4000>; - interrupts = <9>; - clocks = <&clks 9>, <&clks 8>, <&clks 45>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - audmux: audmux@53fc4000 { - compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; - reg = <0x53fc4000 0x4000>; - status = "disabled"; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: dma-controller@53fd4000 { - compatible = "fsl,imx35-sdma"; - reg = <0x53fd4000 0x4000>; - clocks = <&clks 9>, <&clks 65>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - interrupts = <34>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; - }; - - wdog: watchdog@53fdc000 { - compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 74>; - interrupts = <55>; - }; - - can1: can@53fe4000 { - compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fe4000 0x1000>; - clocks = <&clks 33>, <&clks 33>; - clock-names = "ipg", "per"; - interrupts = <43>; - status = "disabled"; - }; - - can2: can@53fe8000 { - compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fe8000 0x1000>; - clocks = <&clks 34>, <&clks 34>; - clock-names = "ipg", "per"; - interrupts = <44>; - status = "disabled"; - }; - - efuse@53ff0000 { - compatible = "fsl,imx35-iim"; - reg = <0x53ff0000 0x4000>; - interrupts = <19>; - clocks = <&clks 80>; - }; - - usbotg: usb@53ff4000 { - compatible = "fsl,imx35-usb", "fsl,imx27-usb"; - reg = <0x53ff4000 0x0200>; - interrupts = <37>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbhost1: usb@53ff4400 { - compatible = "fsl,imx35-usb", "fsl,imx27-usb"; - reg = <0x53ff4400 0x0200>; - interrupts = <35>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53ff4600 { - #index-cells = <1>; - compatible = "fsl,imx35-usbmisc"; - reg = <0x53ff4600 0x00f>; - }; - }; - - emi@80000000 { /* External Memory Interface */ - compatible = "fsl,emi", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x40000000>; - ranges; - - nfc: nand@bb000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx35-nand", "fsl,imx25-nand"; - reg = <0xbb000000 0x2000>; - clocks = <&clks 29>; - clock-names = ""; - interrupts = <33>; - status = "disabled"; - }; - - weim: weim@b8002000 { - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clks 0>; - compatible = "fsl,imx35-weim", "fsl,imx27-weim"; - reg = <0xb8002000 0x1000>; - ranges = < - 0 0 0xa0000000 0x8000000 - 1 0 0xa8000000 0x8000000 - 2 0 0xb0000000 0x2000000 - 3 0 0xb2000000 0x2000000 - 4 0 0xb4000000 0x2000000 - 5 0 0xb6000000 0x2000000 - >; - status = "disabled"; - }; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts deleted file mode 100644 index 4ea5c23f181b..000000000000 --- a/arch/arm/boot/dts/imx50-evk.dts +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Greg Ungerer -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include "imx50.dtsi" - -/ { - model = "Freescale i.MX50 Evaluation Kit"; - compatible = "fsl,imx50-evk", "fsl,imx50"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x80000000>; - }; -}; - -&cspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash: m25p32@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p32", "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "kernel"; - reg = <0x100000 0x300000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - imx50-evk { - pinctrl_cspi: cspigrp { - fsl,pins = < - MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 - MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 - MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 - MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 - MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX50_PAD_SSI_RXFS__FEC_MDC 0x80 - MX50_PAD_SSI_RXC__FEC_MDIO 0x80 - MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 - MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 - MX50_PAD_DISP_D2__FEC_RX_DV 0x80 - MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 - MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 - MX50_PAD_DISP_D5__FEC_TX_EN 0x80 - MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 - MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 - MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 - MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 - MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts deleted file mode 100644 index 467db6b4ed7f..000000000000 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2019 Jonathan Neuschäfer -// -// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B. - -/dts-v1/; -#include "imx50.dtsi" -#include -#include - -/ { - model = "Kobo Aura (N514)"; - compatible = "kobo,aura", "fsl,imx50"; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x10000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-on { - label = "kobo_aura:orange:on"; - gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; - panic-indicator; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - key-power { - label = "Power Button"; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - event-hallsensor { - label = "Hallsensor"; - gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - event-frontlight { - label = "Frontlight"; - gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sd2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_reset>; - reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; - }; - - sd2_vmmc: gpio-regulator { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_vmmc>; - regulator-name = "vmmc"; - states = <3300000 0>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - max-frequency = <50000000>; - bus-width = <4>; - cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - disable-wp; - status = "okay"; - - /* External µSD card */ -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2>; - bus-width = <4>; - max-frequency = <50000000>; - disable-wp; - mmc-pwrseq = <&sd2_pwrseq>; - vmmc-supply = <&sd2_vmmc>; - status = "okay"; - - /* CyberTan WC121 SDIO WiFi (BCM43362) */ -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd3>; - bus-width = <8>; - non-removable; - max-frequency = <50000000>; - disable-wp; - status = "okay"; - - /* Internal eMMC */ -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@15 { - reg = <0x15>; - compatible = "elan,ektf2132"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - embedded-controller@43 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ec>; - compatible = "netronix,ntxec"; - reg = <0x43>; - system-power-controller; - interrupts-extended = <&gpio4 11 IRQ_TYPE_EDGE_FALLING>; - #pwm-cells = <2>; - }; -}; - -&iomuxc { - pinctrl_ec: ecgrp { - fsl,pins = < - MX50_PAD_CSPI_SS0__GPIO4_11 0x0 /* INT */ - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - MX50_PAD_CSPI_MISO__GPIO4_10 0x0 - MX50_PAD_SD2_D7__GPIO5_15 0x0 - MX50_PAD_KEY_ROW0__GPIO4_1 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd - MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd - MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd - MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX50_PAD_PWM1__GPIO6_24 0x0 - >; - }; - - pinctrl_sd1: sd1grp { - fsl,pins = < - MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 - MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 - MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 - MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 - MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 - MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 - - MX50_PAD_SD2_CD__GPIO5_17 0x0 - >; - }; - - pinctrl_sd2: sd2grp { - fsl,pins = < - MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 - MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 - MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 - MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 - MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 - MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 - >; - }; - - pinctrl_sd2_reset: sd2-resetgrp { - fsl,pins = < - MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 - >; - }; - - pinctrl_sd2_vmmc: sd2-vmmcgrp { - fsl,pins = < - MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 - >; - }; - - pinctrl_sd3: sd3grp { - fsl,pins = < - MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 - MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 - MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 - MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 - MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 - MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 - MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 - MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 - MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 - MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX50_PAD_CSPI_MOSI__GPIO4_9 0x0 - MX50_PAD_SD2_D5__GPIO5_13 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 - MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 - >; - }; - - pinctrl_usbphy: usbphygrp { - fsl,pins = < - MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi_wide"; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbphy>; - vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h deleted file mode 100644 index 5e6b30247543..000000000000 --- a/arch/arm/boot/dts/imx50-pinfunc.h +++ /dev/null @@ -1,919 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Greg Ungerer - */ - -#ifndef __DTS_IMX50_PINFUNC_H -#define __DTS_IMX50_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 -#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 -#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 -#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 -#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 -#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 -#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 -#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 -#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 -#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 -#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 -#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 -#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 -#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 -#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 -#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 -#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 -#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 -#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 -#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 -#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 -#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 -#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 -#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 -#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 -#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 -#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 -#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 -#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 -#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 -#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 -#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 -#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 -#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 -#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 -#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 -#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 -#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 -#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 -#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 -#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 -#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 -#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 -#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 -#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 -#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 -#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 -#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 -#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 -#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 -#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 -#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 -#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 -#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 -#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 -#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 -#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 -#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 -#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 -#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 -#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 -#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 -#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 -#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 -#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 -#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 -#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 -#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 -#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 -#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 -#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 -#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 -#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 -#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 -#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 -#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 -#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 -#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 -#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 -#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 -#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 -#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 -#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 -#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 -#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 -#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 -#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 -#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 -#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 -#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 -#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 -#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 -#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 -#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 -#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 -#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 -#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 -#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 -#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 -#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 -#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 -#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 -#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 -#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 -#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 -#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 -#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 -#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 -#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 -#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 -#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 -#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 -#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 -#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 -#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 -#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 -#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 -#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 -#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 -#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 -#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 -#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 -#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 -#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 -#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 -#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 -#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 -#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 -#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 -#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 -#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 -#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 -#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 -#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 -#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 -#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 -#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 -#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 -#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 -#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 -#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 -#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 -#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 -#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 -#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 -#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 -#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 -#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 -#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 -#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 -#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 -#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 -#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 -#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 -#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 -#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 -#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 -#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 -#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 -#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 -#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 -#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 -#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 -#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 -#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 -#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 -#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 -#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 -#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 -#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 -#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 -#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 -#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 -#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 -#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 -#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 -#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 -#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 -#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 -#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 -#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 -#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 -#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 -#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 -#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 -#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 -#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 -#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 -#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 -#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 -#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 -#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 -#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 -#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 -#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 -#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 -#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 -#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 -#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 -#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 -#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 -#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 -#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 -#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 -#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 -#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 -#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 -#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 -#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 -#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 -#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 -#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 -#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 -#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 -#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 -#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 -#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 -#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 -#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 -#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 -#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 -#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 -#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 -#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 -#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 -#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 -#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 -#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 -#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 -#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 -#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 -#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 -#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 -#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 -#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 -#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 -#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 -#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 -#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 -#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 -#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 -#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 -#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 -#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 -#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 -#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 -#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 -#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 -#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 -#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 -#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 -#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 -#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 -#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 -#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 -#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 -#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 -#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 -#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 -#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 -#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 -#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 -#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 -#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 -#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 -#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 -#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 -#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 -#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 -#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 -#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 -#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 -#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 -#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 -#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 -#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 -#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 -#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 -#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 -#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 -#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 -#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 -#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 -#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 -#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 -#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 -#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 -#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 -#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 -#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 -#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 -#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 -#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 -#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 -#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 -#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 -#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 -#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 -#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 -#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 -#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 -#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 -#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 -#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 -#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 -#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 -#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 -#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 -#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 -#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 -#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 -#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 -#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 -#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 -#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 -#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 -#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 -#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 -#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 -#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 -#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 -#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 -#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 -#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 -#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 -#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 -#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 -#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 -#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 -#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 -#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 -#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 -#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 -#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 -#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 -#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 -#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 -#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 -#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 -#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 -#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 -#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 -#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 -#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 -#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 -#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 -#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 -#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 -#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 -#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 -#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 -#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 -#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 -#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 -#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 -#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 -#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 -#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 -#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 -#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 -#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 -#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 -#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 -#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 -#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 -#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 -#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 -#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 -#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 -#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 -#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 -#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 -#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 -#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 -#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 -#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 -#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 -#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 -#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 -#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 -#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 -#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 -#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 -#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 -#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 -#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 -#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 -#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 -#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 -#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 -#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 -#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 -#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 -#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 -#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 -#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 -#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 -#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 -#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 -#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 -#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 -#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 -#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 -#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 -#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 -#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 -#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 -#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 -#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 -#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 -#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 -#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 -#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 -#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 -#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 -#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 -#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 -#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 -#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 -#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 -#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 -#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 -#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 -#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 -#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 -#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 -#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 -#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 -#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 -#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 -#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 -#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 -#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 -#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 -#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 -#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 -#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 -#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 -#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 -#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 -#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 -#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 -#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 -#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 -#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 -#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 -#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 -#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 -#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 -#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 -#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 -#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 -#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 -#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 -#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 -#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 -#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 -#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 -#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 -#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 -#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 -#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 -#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 -#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 -#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 -#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 -#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 -#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 -#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 -#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 -#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 -#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 -#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 -#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 -#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 -#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 -#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 -#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 -#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 -#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 -#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 -#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 -#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 -#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 -#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 -#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 -#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 -#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 -#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 -#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 -#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 -#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 -#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 -#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 -#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 -#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 -#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 -#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 -#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 -#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 -#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 -#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 -#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 -#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 - -#endif /* __DTS_IMX50_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi deleted file mode 100644 index 3d9a9f37f672..000000000000 --- a/arch/arm/boot/dts/imx50.dtsi +++ /dev/null @@ -1,499 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Greg Ungerer -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx50-pinfunc.h" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - - tzic: tz-interrupt-controller@fffc000 { - compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x0fffc000 0x4000>; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - }; - - ckih2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - usbphy0: usbphy-0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - status = "okay"; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - aips1: bus@50000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x10000000>; - ranges; - - spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - esdhc1: mmc@50004000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc2: mmc@50008000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi1: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; - reg = <0x50010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx50-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: mmc@50020000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: mmc@50024000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - usbotg: usb@53f80000 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@53f80200 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - gpio1: gpio@53f84000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 151 28>; - }; - - gpio2: gpio@53f88000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, - <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, - <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, - <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; - }; - - gpio3: gpio@53f8c000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 108 32>; - }; - - gpio4: gpio@53f90000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, - <&iomuxc 20 140 11>; - }; - - wdog1: watchdog@53f98000 { - compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; - reg = <0x53f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - gpt: timer@53fa0000 { - compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; - reg = <0x53fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - pwm1: pwm@53fb4000 { - #pwm-cells = <3>; - compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@53fb8000 { - #pwm-cells = <3>; - compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; - reg = <0x53fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@53fbc000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@53fc0000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: reset-controller@53fd0000 { - compatible = "fsl,imx50-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - interrupts = <75>; - #reset-cells = <1>; - }; - - clks: ccm@53fd4000{ - compatible = "fsl,imx50-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - - gpio5: gpio@53fdc000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53fdc000 0x4000>; - interrupts = <103 104>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; - }; - - gpio6: gpio@53fe0000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53fe0000 0x4000>; - interrupts = <105 106>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; - }; - - i2c3: i2c@53fec000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x53fec000 0x4000>; - interrupts = <64>; - clocks = <&clks IMX5_CLK_I2C3_GATE>; - status = "disabled"; - }; - - uart4: serial@53ff0000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53ff0000 0x4000>; - interrupts = <13>; - clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - aips2: bus@60000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000000 0x10000000>; - ranges; - - uart5: serial@63f90000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x63f90000 0x4000>; - interrupts = <86>; - clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - owire: owire@63fa4000 { - compatible = "fsl,imx50-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: spi@63fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; - reg = <0x63fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: dma-controller@63fb0000 { - compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; - reg = <0x63fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; - }; - - cspi: spi@63fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; - reg = <0x63fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@63fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x63fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@63fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x63fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@63fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@63fd0000 { - compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; - reg = <0x63fd0000 0x4000>; - status = "disabled"; - }; - - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts deleted file mode 100644 index ba28ffe06fe2..000000000000 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Armadeus Systems - - * Copyright 2012 Laurent Cans - * - * Based on mx51-babbage.dts - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Armadeus Systems APF51 module"; - compatible = "armadeus,imx51-apf51", "fsl,imx51"; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x20000000>; - }; - - clocks { - osc { - clock-frequency = <33554432>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&iomuxc { - imx51-apf51 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts deleted file mode 100644 index b61d55ca1467..000000000000 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Armadeus Systems - - */ - -/* APF51Dev is a docking board for the APF51 SOM */ -#include "imx51-apf51.dts" - -/ { - model = "Armadeus Systems APF51Dev docking/development board"; - compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; - - backlight { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - compatible = "gpio-backlight"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - default-on; - }; - - disp1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - display-timings { - lw700 { - native-mode; - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-key { - label = "user"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - linux,code = <256>; /* BTN_0 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - led-user { - label = "Heartbeat"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, - <&gpio3 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx51-apf51dev { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 - MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 - MX51_PAD_EIM_CS4__GPIO2_29 0x100 - MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 - MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 - MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 - MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 - MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 - MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed - MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - >; - }; - }; -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display_in>; -}; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts deleted file mode 100644 index a1f9c6a72275..000000000000 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ /dev/null @@ -1,726 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Freescale i.MX51 Babbage Board"; - compatible = "fsl,imx51-babbage", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x20000000>; - }; - - ckih1 { - clock-frequency = <22579200>; - }; - - clk_osc: clk-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - clk_osc_gate: clk-osc-gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz_osc>; - clocks = <&clk_osc>; - #clock-cells = <0>; - enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - }; - - clk_audio: clk-audio { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz_audio>; - clocks = <&clk_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; - - clk_usb: clk-usb { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz_usb>; - clocks = <&clk_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - display1: disp1 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - - port@1 { - reg = <1>; - - parallel_display_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; - }; - - display2: disp2 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb565"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2>; - status = "disabled"; - display-timings { - native-mode = <&timing1>; - timing1: claawvga { - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <60>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <20>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp2>; - }; - }; - }; - - dvi-connector { - compatible = "dvi-connector"; - digital; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <¶llel_display_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-power { - label = "Power Button"; - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-diagnostic { - label = "diagnostic"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_hub_reset: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgreg>; - reg = <0>; - regulator-name = "hub_reset"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - usbphy1: usbphy1 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1reg>; - clocks = <&clk_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic: mc13892@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb_reg: vusb { - regulator-boot-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - }; - - flash: at45db321d@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_audio>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; - }; -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display0_in>; -}; - -&ipu_di1_disp2 { - remote-endpoint = <&display1_in>; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 3, KEY_HOME) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(1, 3, KEY_VOLUMEUP) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - MATRIX_KEY(3, 0, KEY_F1) - MATRIX_KEY(3, 1, KEY_F2) - MATRIX_KEY(3, 2, KEY_F3) - MATRIX_KEY(3, 3, KEY_POWER) - >; - status = "okay"; -}; - -&pmu { - secure-reg-access; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_hub_reset>; - fsl,usbphy = <&usbphy1>; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb_reg>; -}; - -&usbotg { - dr_mode = "otg"; - disable-over-current; - phy_type = "utmi_wide"; - status = "okay"; -}; - -&iomuxc { - imx51-babbage { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - - pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { - fsl,pins = < - MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 - >; - }; - - pinctrl_clk26mhz_osc: clk26mhzoscgrp { - fsl,pins = < - MX51_PAD_DI1_PIN12__GPIO3_1 0x85 - >; - }; - - pinctrl_clk26mhz_usb: clk26mhzusbgrp { - fsl,pins = < - MX51_PAD_EIM_D17__GPIO2_1 0x85 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ - MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 - MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 - MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 - MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX51_PAD_EIM_A27__GPIO2_21 0x5 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX51_PAD_EIM_D22__GPIO2_6 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed - MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - >; - }; - - pinctrl_ipu_disp2: ipudisp2grp { - fsl,pins = < - MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 - MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 - MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 - MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 - MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 - MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 - MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 - MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 - MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 - MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 - MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 - MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 - MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 - MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 - MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 - MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 - MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 - MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 - MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 - MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 - MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 - MX51_PAD_KEY_COL0__KEY_COL0 0xe8 - MX51_PAD_KEY_COL1__KEY_COL1 0xe8 - MX51_PAD_KEY_COL2__KEY_COL2 0xe8 - MX51_PAD_KEY_COL3__KEY_COL3 0xe8 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - MX51_PAD_EIM_D27__UART3_RTS 0x1c5 - MX51_PAD_EIM_D24__UART3_CTS 0x1c5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 - >; - }; - - pinctrl_usbh1reg: usbh1reggrp { - fsl,pins = < - MX51_PAD_EIM_D21__GPIO2_5 0x85 - >; - }; - - pinctrl_usbotgreg: usbotgreggrp { - fsl,pins = < - MX51_PAD_GPIO1_7__GPIO1_7 0x85 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts deleted file mode 100644 index 10cae7c3a879..000000000000 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#include "imx51-digi-connectcore-som.dtsi" - -/ { - model = "Digi ConnectCore CC(W)-MX51 JSK"; - compatible = "digi,connectcore-ccxmx51-jsk", - "digi,connectcore-ccxmx51-som", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - usbphy1: usbphy1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; -}; - -&esdhc1 { - status = "okay"; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire>; - status = "okay"; -}; - -&pmic { - fsl,mc13xxx-uses-rtc; - - regulators { - vcoincell_reg: vcoincell { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - imx51-digi-connectcore-jsk { - pinctrl_owire: owiregrp { - fsl,pins = < - MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi deleted file mode 100644 index f0809a16a2ce..000000000000 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Digi ConnectCore CC(W)-MX51"; - compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x08000000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13892@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mc13892>; - compatible = "fsl,mc13892"; - spi-max-frequency = <16000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1275000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { }; - - viohi_reg: viohi { - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - gpo2_reg: gpo2 { }; - - gpo3_reg: gpo3 { }; - - gpo4_reg: gpo4 { }; - - pwgt2spi_reg: pwgt2spi { - regulator-always-on; - }; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - max-frequency = <50000000>; - bus-width = <1>; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cap-sdio-irq; - wakeup-source; - keep-power-in-suspend; - max-frequency = <50000000>; - no-1-8-v; - non-removable; - vmmc-supply = <&gpo4_reg>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-supply = <&gpo3_reg>; - /* Pins shared with LCD2, keep status disabled */ -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - - mma7455l@1d { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mma7455l>; - compatible = "fsl,mma7455l"; - reg = <0x1d>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi_wide"; - disable-over-current; - vbus-supply = <&swbst_reg>; - /* Device role is not known, keep status disabled */ -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - lan9221: ethernet@5,0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lan9221>; - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <5 0x00000000 0x1000>; - fsl,weim-cs-timing = < - 0x00420081 0x00000000 - 0x32260000 0x00000000 - 0x72080f00 0x00000000 - >; - clocks = <&clks IMX5_CLK_DUMMY>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,irq-push-pull; - vdd33a-supply = <&gpo2_reg>; - vddvario-supply = <&gpo2_reg>; - }; -}; - -&iomuxc { - imx51-digi-connectcore-som { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed - MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed - MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 - MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 - MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 - MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 - MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 - MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 - MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 - MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 - MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 - MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 - MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 - MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 - MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 - MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 - MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 - >; - }; - - pinctrl_lan9221: lan9221grp { - fsl,pins = < - MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ - >; - }; - - pinctrl_mc13892: mc13892grp { - fsl,pins = < - MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ - >; - }; - - pinctrl_mma7455l: mma7455lgrp { - fsl,pins = < - MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ - MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 - MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 - MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 - MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 - MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 - MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 - MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 - MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 - MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 - MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 - MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 - MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 - MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 - MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 - MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 - MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 - MX51_PAD_EIM_A16__EIM_A16 0x80000000 - MX51_PAD_EIM_A17__EIM_A17 0x80000000 - MX51_PAD_EIM_A18__EIM_A18 0x80000000 - MX51_PAD_EIM_A19__EIM_A19 0x80000000 - MX51_PAD_EIM_A20__EIM_A20 0x80000000 - MX51_PAD_EIM_A21__EIM_A21 0x80000000 - MX51_PAD_EIM_A22__EIM_A22 0x80000000 - MX51_PAD_EIM_A23__EIM_A23 0x80000000 - MX51_PAD_EIM_A24__EIM_A24 0x80000000 - MX51_PAD_EIM_A25__EIM_A25 0x80000000 - MX51_PAD_EIM_A26__EIM_A26 0x80000000 - MX51_PAD_EIM_A27__EIM_A27 0x80000000 - MX51_PAD_EIM_D16__EIM_D16 0x80000000 - MX51_PAD_EIM_D17__EIM_D17 0x80000000 - MX51_PAD_EIM_D18__EIM_D18 0x80000000 - MX51_PAD_EIM_D19__EIM_D19 0x80000000 - MX51_PAD_EIM_D20__EIM_D20 0x80000000 - MX51_PAD_EIM_D21__EIM_D21 0x80000000 - MX51_PAD_EIM_D22__EIM_D22 0x80000000 - MX51_PAD_EIM_D23__EIM_D23 0x80000000 - MX51_PAD_EIM_D24__EIM_D24 0x80000000 - MX51_PAD_EIM_D25__EIM_D25 0x80000000 - MX51_PAD_EIM_D26__EIM_D26 0x80000000 - MX51_PAD_EIM_D27__EIM_D27 0x80000000 - MX51_PAD_EIM_D28__EIM_D28 0x80000000 - MX51_PAD_EIM_D29__EIM_D29 0x80000000 - MX51_PAD_EIM_D30__EIM_D30 0x80000000 - MX51_PAD_EIM_D31__EIM_D31 0x80000000 - MX51_PAD_EIM_OE__EIM_OE 0x80000000 - MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 - MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 - MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi deleted file mode 100644 index c2a929ba8ceb..000000000000 --- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx51.dtsi" - -/ { - model = "Eukrea CPUIMX51"; - compatible = "eukrea,cpuimx51", "fsl,imx51"; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x10000000>; /* 256M */ - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsc2007: tsc2007@49 { - compatible = "ti,tsc2007"; - gpios = <&gpio4 0 1>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007_1>; - reg = <0x49>; - ti,x-plate-ohms = <180>; - }; -}; - -&iomuxc { - imx51-eukrea { - pinctrl_tsc2007_1: tsc2007grp-1 { - fsl,pins = < - MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 - MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed - MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts deleted file mode 100644 index b6d931e96a8f..000000000000 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -/dts-v1/; -#include "imx51-eukrea-cpuimx51.dtsi" -#include - -/ { - model = "Eukrea CPUIMX51"; - compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; - - clocks { - clk24M: can_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys_1>; - - button-1 { - label = "BP1"; - gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - linux,code = <256>; - wakeup-source; - linux,input-type = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_can: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "CAN_RST"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <20000>; - enable-active-high; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx51-eukrea-tlv320aic23"; - ssi-controller = <&ssi2>; - fsl,mux-int-port = <2>; - fsl,mux-ext-port = <3>; - }; - - usbphy1: usbphy1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - can0: can@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can>; - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk24M>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <®_can>; - }; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx51-eukrea { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - - - pinctrl_can: cangrp { - fsl,pins = < - MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ - MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_uart3_rtscts: uart3rtsctsgrp { - fsl,pins = < - MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 - MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 - >; - }; - - pinctrl_backlight_1: backlightgrp-1 { - fsl,pins = < - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 - >; - }; - - pinctrl_esdhc1_cd: esdhc1_cd { - fsl,pins = < - MX51_PAD_GPIO1_0__GPIO1_0 0xd5 - >; - }; - - pinctrl_gpiokeys_1: gpiokeysgrp-1 { - fsl,pins = < - MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 - >; - }; - - pinctrl_gpioled: gpioledgrp-1 { - fsl,pins = < - MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 - >; - }; - - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = < - MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 - >; - }; - }; -}; - -&ssi2 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - phy_type = "utmi_wide"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/imx51-pinfunc.h deleted file mode 100644 index 910e0ec50ef3..000000000000 --- a/arch/arm/boot/dts/imx51-pinfunc.h +++ /dev/null @@ -1,768 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX51_PINFUNC_H -#define __DTS_IMX51_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 -#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 -#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 -#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 -#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 -#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 -#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 -#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 -#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 -#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 -#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 -#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 -#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 -#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 -#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 -#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 -#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 -#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 -#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 -#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 -#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 -#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 -#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 -#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 -#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 -#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 -#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 -#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 -#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 -#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 -#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 -#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 -#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 -#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 -#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 -#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 -#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 -#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 -#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 -#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 -#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 -#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 -#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 -#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 -#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 -#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 -#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 -#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 -#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 -#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 -#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 -#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 -#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 -#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 -#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 -#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 -#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 -#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 -#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 -#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 -#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 -#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 -#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 -#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 -#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 -#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 -#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 -#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 -#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 -#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 -#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 -#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 -#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 -#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 -#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 -#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 -#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 -#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 -#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 -#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 -#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 -#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 -#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 -#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 -#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 -#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 -#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 -#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 -#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 -#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 -#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 -#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 -#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 -#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 -#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 -#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 -#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 -#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 -#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 -#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 -#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 -#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 -#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 -#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 -#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 -#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 -#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 -#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 -#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 -#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 -#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 -#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 -#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 -#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 -#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 -#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 -#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 -#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 -#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 -#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 -#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 -#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 -#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 -#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 -#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 -#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 -#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 -#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 -#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 -#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 -#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 -#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 -#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 -#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 -#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 -#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 -#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 -#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 -#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 -#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 -#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 -#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 -#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 -#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 -#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 -#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 -#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 -#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 -#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 -#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 -#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 -#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 -#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 -#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 -#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 -#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 -#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 -#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 -#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 -#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 -#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 -#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 -#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 -#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 -#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 -#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 -#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 -#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 -#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 -#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 -#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 -#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 -#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 -#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 -#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 -#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 -#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 -#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 -#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 -#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 -#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 -#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 -#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 -#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 -#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 -#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 -#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 -#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 -#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 -#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 -#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 -#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 -#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 -#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 -#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 -#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 -#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 -#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 -#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 -#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 -#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 -#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 -#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 -#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 -#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 -#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 -#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 -#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 -#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 -#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 -#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 -#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 -#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 -#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 -#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 -#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 -#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 -#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 -#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 -#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 -#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 -#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 -#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 -#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 -#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 -#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 -#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 -#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 -#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 -#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 -#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 -#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 -#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 -#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 -#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 -#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 -#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 -#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 -#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 -#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 -#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 -#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 -#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 -#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 -#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 -#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 -#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 -#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 -#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 -#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 -#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 -#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 -#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 -#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 -#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 -#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 - -#endif /* __DTS_IMX51_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts deleted file mode 100644 index f7408722d68a..000000000000 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright 2015 Savoir-faire Linux - * - * This device tree is based on imx51-babbage.dts - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Technologic Systems TS-4800"; - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x10000000>; - }; - - clocks { - ckih1 { - clock-frequency = <22579200>; - }; - - ckih2 { - clock-frequency = <24576000>; - }; - }; - - backlight_reg: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_lcd>; - regulator-name = "enable_lcd_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 78770>; - brightness-levels = <0 150 200 255>; - default-brightness-level = <1>; - power-supply = <&backlight_reg>; - }; - - display1: disp1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <30066000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <50>; - hback-porch = <70>; - hsync-len = <50>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <50>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display0_in>; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_backlight>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - fpga@0 { - compatible = "simple-bus"; - fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 - 0x00000000 0x1c092480 0x00000000>; - reg = <0 0x0000000 0x1d000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x1d000>; - - syscon: syscon@10000 { - compatible = "syscon", "simple-mfd"; - reg = <0x10000 0x3d>; - reg-io-width = <2>; - - wdt { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - }; - }; - - touchscreen@12000 { - compatible = "technologic,ts4800-ts"; - reg = <0x12000 0x1000>; - syscon = <&syscon 0x10 6>; - }; - - fpga_irqc: fpga-irqc@15000 { - compatible = "technologic,ts4800-irqc"; - reg = <0x15000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_interrupt_fpga>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - can@1a000 { - compatible = "technologic,sja1000"; - reg = <0x1a000 0x100>; - interrupt-parent = <&fpga_irqc>; - interrupts = <1>; - reg-io-width = <2>; - nxp,tx-output-config = <0x06>; - nxp,external-clock-frequency = <24000000>; - }; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - >; - }; - - pinctrl_enable_lcd: enablelcdgrp { - fsl,pins = < - MX51_PAD_CSI2_D12__GPIO4_9 0x1c5 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 - MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 - MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_interrupt_fpga: fpgaicgrp { - fsl,pins = < - MX51_PAD_EIM_D27__GPIO2_9 0xe5 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - - pinctrl_pwm_backlight: backlightgrp { - fsl,pins = < - MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX51_PAD_EIM_DTACK__EIM_DTACK 0x85 - MX51_PAD_EIM_CS0__EIM_CS0 0x0 - MX51_PAD_EIM_CS1__EIM_CS1 0x0 - MX51_PAD_EIM_EB0__EIM_EB0 0x85 - MX51_PAD_EIM_EB1__EIM_EB1 0x85 - MX51_PAD_EIM_OE__EIM_OE 0x85 - MX51_PAD_EIM_LBA__EIM_LBA 0x85 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts deleted file mode 100644 index 5d4b29d76585..000000000000 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ /dev/null @@ -1,894 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2017 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "imx51.dtsi" -#include - -/ { - model = "ZII RDU1 Board"; - compatible = "zii,imx51-rdu1", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - /* Will be filled by the bootloader */ - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0>; - }; - - aliases { - mdio-gpio0 = &mdio_gpio; - rtc0 = &ds1341; - }; - - clk_26M_osc: 26M_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - clk_26M_osc_gate: 26M_gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz>; - clocks = <&clk_26M_osc>; - #clock-cells = <0>; - enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - }; - - clk_26M_usb: usbhost_gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbgate26mhz>; - clocks = <&clk_26M_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - }; - - clk_26M_snd: snd_gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sndgate26mhz>; - clocks = <&clk_26M_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; - - reg_5p0v_main: regulator-5p0v-main { - compatible = "regulator-fixed"; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - disp0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel { - /* no compatible here, bootloader will patch in correct one */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel>; - power-supply = <®_3p3v>; - enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - i2c_gpio: i2c-gpio { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_swi2c>; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <50>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clk_26M_snd>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; - #sound-dai-cells = <0>; - }; - }; - - spi_gpio: spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiospi0>; - status = "okay"; - - sck-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - - eeprom@0 { - compatible = "eeprom-93xx46"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cs-high; - data-size = <8>; - }; - }; - - mdio_gpio: mdio-gpio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_swmdio>; - gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ - <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ - - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-mode = "rev-mii"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "netaux"; - }; - - port@3 { - reg = <3>; - label = "netright"; - }; - - port@4 { - reg = <4>; - label = "netleft"; - }; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Front"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "TPA6130A2 HPLEFT", - "Headphone Jack", "TPA6130A2 HPRIGHT"; - simple-audio-card,aux-devs = <&hpa1>; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clk_26M_snd>; - }; - }; - - usbh1phy: usbphy1 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1phy>; - clocks = <&clk_26M_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; - - usbh2phy: usbphy2 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2phy>; - clocks = <&clk_26M_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCSEL(2) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&cpu { - cpu-supply = <&sw1_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x0 0x0 0x3f83f8 0x0>; - - sysled0@3 { - reg = <3>; - label = "system:green:status"; - linux,default-trigger = "default-on"; - }; - - sysled1@4 { - reg = <4>; - label = "system:green:act"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-supply = <&vgen3_reg>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "hp-amp-shutdown-b", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; - - unused-sd3-wp-hog { - /* - * See pinctrl_esdhc1 below for more details on this - */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - hpa1: amp@60 { - compatible = "ti,tpa6130a2"; - reg = <0x60>; - Vdd-supply = <®_3p3v>; - sound-name-prefix = "TPA6130A2"; - }; - - ds1341: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; - - /* touch nodes default disabled, bootloader will enable the right one */ - - touchscreen@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; - - touchscreen@4c { - compatible = "atmel,maxtouch"; - reg = <0x4c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <2>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - }; - -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display_in>; -}; - -&pmu { - secure-reg-access; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-rdu1"; - current-speed = <38400>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "dds-eeprom"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - - eeprom@ae { - compatible = "zii,rave-sp-eeprom"; - reg = <0xae 0x200>; - zii,eeprom-name = "switch-eeprom"; - /* - * Not all RDU1s have this functionality, so we - * rely on the bootloader to enable this - */ - status = "disabled"; - }; - }; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - phy_type = "ulpi"; - fsl,usbphy = <&usbh1phy>; - disable-over-current; - maximum-speed = "full-speed"; - vbus-supply = <®_5p0v_main>; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - fsl,usbphy = <&usbh2phy>; - disable-over-current; - vbus-supply = <®_5p0v_main>; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb_reg>; -}; - -&usbotg { - dr_mode = "host"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <®_5p0v_main>; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_GPIO1_9__GPIO1_9 0x5e - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 - >; - }; - - pinctrl_clk26mhz: clk26mhzgrp { - fsl,pins = < - MX51_PAD_DI1_PIN12__GPIO3_1 0x85 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - /* - * GPIO1_1 is not directly used by eSDHC1 in - * any capacity, but earlier versions of RDU1 - * used that pin as WP GPIO for eSDHC3 and - * because of that that pad has an external - * pull-up resistor. This is problematic - * because out of reset the pad is configured - * as ALT0 which serves as SD1_WP, which, when - * pulled high by and external pull-up, will - * inhibit execution of any write request to - * attached eMMC device. - * - * To avoid this problem we configure the pad - * to ALT1/GPIO and avoid driving SD1_WP - * signal high. - */ - MX51_PAD_GPIO1_1__GPIO1_1 0x0000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 - MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 - MX51_PAD_EIM_CS5__FEC_CRS 0x180 - MX51_PAD_NANDF_RB2__FEC_COL 0x2180 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 - MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 - MX51_PAD_EIM_A20__GPIO2_14 0x85 - >; - }; - - pinctrl_gpiospi0: gpiospi0grp { - fsl,pins = < - MX51_PAD_CSI2_D18__GPIO4_11 0x85 - MX51_PAD_CSI2_D19__GPIO4_12 0x85 - MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 - MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - >; - }; - - pinctrl_panel: panelgrp { - fsl,pins = < - MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 - MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 - >; - }; - - pinctrl_sndgate26mhz: sndgate26mhzgrp { - fsl,pins = < - MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 - >; - }; - - pinctrl_swi2c: swi2cgrp { - fsl,pins = < - MX51_PAD_GPIO1_2__GPIO1_2 0xc5 - MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 - >; - }; - - pinctrl_swmdio: swmdiogrp { - fsl,pins = < - MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 - MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX51_PAD_CSI1_D8__GPIO3_12 0x04 - MX51_PAD_CSI1_D9__GPIO3_13 0x85 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0xc5 - MX51_PAD_UART2_TXD__UART2_TXD 0xc5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usbgate26mhz: usbgate26mhzgrp { - fsl,pins = < - MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_STP__USBH1_STP 0x0 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 - >; - }; - - pinctrl_usbh1phy: usbh1phygrp { - fsl,pins = < - MX51_PAD_NANDF_D0__GPIO4_8 0x85 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX51_PAD_EIM_A26__USBH2_STP 0x0 - MX51_PAD_EIM_A24__USBH2_CLK 0x0 - MX51_PAD_EIM_A25__USBH2_DIR 0x0 - MX51_PAD_EIM_A27__USBH2_NXT 0x0 - MX51_PAD_EIM_D16__USBH2_DATA0 0x0 - MX51_PAD_EIM_D17__USBH2_DATA1 0x0 - MX51_PAD_EIM_D18__USBH2_DATA2 0x0 - MX51_PAD_EIM_D19__USBH2_DATA3 0x0 - MX51_PAD_EIM_D20__USBH2_DATA4 0x0 - MX51_PAD_EIM_D21__USBH2_DATA5 0x0 - MX51_PAD_EIM_D22__USBH2_DATA6 0x0 - MX51_PAD_EIM_D23__USBH2_DATA7 0x0 - >; - }; - - pinctrl_usbh2phy: usbh2phygrp { - fsl,pins = < - MX51_PAD_NANDF_D1__GPIO4_7 0x85 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts deleted file mode 100644 index 625f9ac671ae..000000000000 --- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts +++ /dev/null @@ -1,457 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx51.dtsi" - -/ { - model = "ZII SCU2 Mezz Board"; - compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - /* Will be filled by the bootloader */ - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0>; - }; - - aliases { - mdio-gpio0 = &mdio_gpio; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_mmc_reset>; - gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; - startup-delay-us = <150000>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - mdio_gpio: mdio-gpio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_swmdio>; - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ - <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port4"; - }; - - port@1 { - reg = <1>; - label = "port5"; - }; - - port@2 { - reg = <2>; - label = "port6"; - }; - - port@3 { - reg = <3>; - label = "port7"; - }; - - port@4 { - reg = <4>; - phy-mode = "rev-mii"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@5 { - reg = <5>; - label = "mezz2esb"; - phy-mode = "sgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&cpu { - cpu-supply = <&sw1_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x0 0x0 0x3f83f8 0x0>; - - sysled3: led3@3 { - reg = <3>; - label = "system:red:power"; - linux,default-trigger = "default-on"; - }; - - sysled4: led4@4 { - reg = <4>; - label = "system:green:act"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - flash@1 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <1>; - spi-max-frequency = <25000000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc4>; - bus-width = <4>; - no-1-8-v; - no-sdio; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - status = "okay"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-supply = <&vgen3_reg>; - phy-handle = <ðphy>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - reg = <0>; - max-speed = <100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-mezz"; - current-speed = <57600>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog-legacy"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg { - dr_mode = "host"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <&usb_vbus>; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb2_reg>; -}; - -&vpu { - status = "disabled"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 - MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 - MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 - MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 - >; - }; - - pinctrl_esdhc4: esdhc4grp { - fsl,pins = < - MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 - MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 - MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 - MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 - MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 - MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 - MX51_PAD_NANDF_D0__GPIO4_8 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 - MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 - MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 - MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 - MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 - MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 - MX51_PAD_EIM_A20__GPIO2_14 0x0085 - MX51_PAD_EIM_A21__GPIO2_15 0x00e5 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_4__GPIO1_4 0x85 - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 - >; - }; - - pinctrl_swmdio: swmdiogrp { - fsl,pins = < - MX51_PAD_EIM_D22__GPIO2_6 0x100 - MX51_PAD_EIM_D23__GPIO2_7 0x100 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usb_mmc_reset: usbmmcgrp { - fsl,pins = < - MX51_PAD_CSI1_D9__GPIO3_13 0x85 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts deleted file mode 100644 index 19a3b142c964..000000000000 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ /dev/null @@ -1,471 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx51.dtsi" - -/ { - model = "ZII SCU3 ESB board"; - compatible = "zii,imx51-scu3-esb", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - /* Will be filled by the bootloader */ - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0>; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_mmc_reset>; - gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; - startup-delay-us = <150000>; - }; -}; - -&cpu { - cpu-supply = <&sw1_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x0 0x0 0x3f83f8 0x0>; - - sysled3: led3@3 { - reg = <3>; - label = "system:red:power"; - linux,default-trigger = "default-on"; - }; - - sysled4: led4@4 { - reg = <4>; - label = "system:green:act"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc4>; - bus-width = <4>; - no-1-8-v; - no-sdio; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - fec_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port1"; - }; - - port@1 { - reg = <1>; - label = "port2"; - }; - - port@2 { - reg = <2>; - label = "port3"; - }; - - port@3 { - reg = <3>; - label = "scu2scu"; - }; - - port@4 { - reg = <4>; - label = "esb2host"; - }; - - port@5 { - reg = <5>; - label = "esb2mezz"; - phy-mode = "sgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - phy-mode = "mii"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&ipu { - status = "disabled"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-esb"; - current-speed = <57600>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog-legacy"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg { - dr_mode = "host"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <&usb_vbus>; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb2_reg>; -}; - -&vpu { - status = "disabled"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 - MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 - MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 - MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 - >; - }; - - pinctrl_esdhc4: esdhc4grp { - fsl,pins = < - MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 - MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 - MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 - MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 - MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 - MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 - MX51_PAD_NANDF_D0__GPIO4_8 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 - MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 - - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 - MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 - MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 - MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_4__GPIO1_4 0x85 - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 - >; - }; - - pinctrl_switch: switchgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 - MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usb_mmc_reset: usbmmcgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi deleted file mode 100644 index ba92a3ea6872..000000000000 --- a/arch/arm/boot/dts/imx51.dtsi +++ /dev/null @@ -1,663 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx51-pinfunc.h" -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c1; - i2c1 = &i2c2; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - tzic: tz-interrupt-controller@e0000000 { - compatible = "fsl,imx51-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xe0000000 0x4000>; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - ckih2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - clock-latency = <62500>; - clocks = <&clks IMX5_CLK_CPU_PODF>; - clock-names = "cpu"; - operating-points = < - 166000 1000000 - 600000 1050000 - 800000 1100000 - >; - voltage-tolerance = <5>; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&tzic>; - interrupts = <77>; - }; - - usbphy0: usbphy0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu_csi0>, <&ipu_csi1>; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>, <&ipu_di1>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - iram: sram@1ffe0000 { - compatible = "mmio-sram"; - reg = <0x1ffe0000 0x20000>; - ranges = <0 0x1ffe0000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpu: gpu@30000000 { - compatible = "amd,imageon-200.1", "amd,imageon"; - reg = <0x30000000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <12>; - interrupt-names = "kgsl_3d0_irq"; - clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; - clock-names = "core_clk", "mem_iface_clk"; - }; - - ipu: ipu@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ipu"; - reg = <0x40000000 0x20000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu_csi0: port@0 { - reg = <0>; - }; - - ipu_csi1: port@1 { - reg = <1>; - }; - - ipu_di0: port@2 { - reg = <2>; - - ipu_di0_disp1: endpoint { - }; - }; - - ipu_di1: port@3 { - reg = <3>; - - ipu_di1_disp2: endpoint { - }; - }; - }; - - aips1: bus@70000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x70000000 0x10000000>; - ranges; - - spba-bus@70000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x70000000 0x40000>; - ranges; - - esdhc1: mmc@70004000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: mmc@70008000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@7000c000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x7000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 43 5 1>, <&sdma 44 5 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi1: spi@70010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x70010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@70014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x70014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, - <&clks IMX5_CLK_SSI2_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: mmc@70020000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: mmc@70024000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - aipstz1: bridge@73f00000 { - compatible = "fsl,imx51-aipstz"; - reg = <0x73f00000 0x60>; - }; - - usbotg: usb@73f80000 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@73f80200 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@73f80400 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@73f80600 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@73f80800 { - #index-cells = <1>; - compatible = "fsl,imx51-usbmisc"; - reg = <0x73f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - - gpio1: gpio@73f84000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@73f88000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@73f8c000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@73f90000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@73f94000 { - compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; - reg = <0x73f94000 0x4000>; - interrupts = <60>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: watchdog@73f98000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - wdog2: watchdog@73f9c000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f9c000 0x4000>; - interrupts = <59>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - gpt: timer@73fa0000 { - compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; - reg = <0x73fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@73fa8000 { - compatible = "fsl,imx51-iomuxc"; - reg = <0x73fa8000 0x4000>; - }; - - pwm1: pwm@73fb4000 { - #pwm-cells = <3>; - compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; - reg = <0x73fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@73fb8000 { - #pwm-cells = <3>; - compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; - reg = <0x73fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@73fbc000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@73fc0000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 16 4 1>, <&sdma 17 4 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - src: reset-controller@73fd0000 { - compatible = "fsl,imx51-src"; - reg = <0x73fd0000 0x4000>; - interrupts = <75>; - #reset-cells = <1>; - }; - - clks: ccm@73fd4000{ - compatible = "fsl,imx51-ccm"; - reg = <0x73fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - }; - - aips2: bus@80000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x10000000>; - ranges; - - aipstz2: bridge@83f00000 { - compatible = "fsl,imx51-aipstz"; - reg = <0x83f00000 0x60>; - }; - - iim: efuse@83f98000 { - compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon"; - reg = <0x83f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; - - tigerp: tigerp@83fa0000 { - compatible = "fsl,imx51-tigerp"; - reg = <0x83fa0000 0x28>; - }; - - owire: owire@83fa4000 { - compatible = "fsl,imx51-owire", "fsl,imx21-owire"; - reg = <0x83fa4000 0x4000>; - interrupts = <88>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: spi@83fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x83fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: dma-controller@83fb0000 { - compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; - reg = <0x83fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; - }; - - cspi: spi@83fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; - reg = <0x83fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@83fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@83fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@83fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x83fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, - <&clks IMX5_CLK_SSI1_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@83fd0000 { - compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; - reg = <0x83fd0000 0x4000>; - clocks = <&clks IMX5_CLK_DUMMY>; - clock-names = "audmux"; - status = "disabled"; - }; - - m4if: m4if@83fd8000 { - compatible = "fsl,imx51-m4if"; - reg = <0x83fd8000 0x1000>; - }; - - weim: weim@83fda000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx51-weim"; - reg = <0x83fda000 0x1000>; - clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; - ranges = < - 0 0 0xb0000000 0x08000000 - 1 0 0xb8000000 0x08000000 - 2 0 0xc0000000 0x08000000 - 3 0 0xc8000000 0x04000000 - 4 0 0xcc000000 0x02000000 - 5 0 0xce000000 0x02000000 - >; - status = "disabled"; - }; - - nfc: nand@83fdb000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx51-nand"; - reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; - interrupts = <8>; - clocks = <&clks IMX5_CLK_NFC_GATE>; - status = "disabled"; - }; - - pata: pata@83fe0000 { - compatible = "fsl,imx51-pata", "fsl,imx27-pata"; - reg = <0x83fe0000 0x4000>; - interrupts = <70>; - clocks = <&clks IMX5_CLK_PATA_GATE>; - status = "disabled"; - }; - - ssi3: ssi@83fe8000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x83fe8000 0x4000>; - interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, - <&clks IMX5_CLK_SSI3_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 46 0 0>, - <&sdma 47 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@83fec000 { - compatible = "fsl,imx51-fec", "fsl,imx27-fec"; - reg = <0x83fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - vpu: vpu@83ff4000 { - compatible = "fsl,imx51-vpu", "cnm,codahx4"; - reg = <0x83ff4000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; - clock-names = "per", "ahb"; - resets = <&src 1>; - iram = <&iram>; - }; - - sahara: crypto@83ff8000 { - compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; - reg = <0x83ff8000 0x4000>; - interrupts = <19 20>; - clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; - clock-names = "ipg", "ahb"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts deleted file mode 100644 index 23a7492e2929..000000000000 --- a/arch/arm/boot/dts/imx53-ard.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Automotive Reference Design Board"; - compatible = "fsl,imx53-ard", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x40000000>; - }; - - eim-cs1@f4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,eim-bus", "simple-bus"; - reg = <0xf4000000 0x3ff0000>; - ranges; - - ethernet@f4000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0xf4000000 0x2000000>; - phy-mode = "mii"; - interrupt-parent = <&gpio2>; - interrupts = <31 0x8>; - reg-io-width = <4>; - /* - * VDD33A and VDDVARIO of LAN9220 are supplied by - * SW4_3V3 of LTC3589. Before the regulator driver - * for this PMIC is available, we use a fixed dummy - * 3V3 regulator to get LAN9220 driver probing work. - */ - vdd33a-supply = <®_3p3v>; - vddvario-supply = <®_3p3v>; - smsc,irq-push-pull; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-home { - label = "Home"; - gpios = <&gpio5 10 0>; - linux,code = ; - wakeup-source; - }; - - key-back { - label = "Back"; - gpios = <&gpio5 11 0>; - linux,code = ; - wakeup-source; - }; - - key-program { - label = "Program"; - gpios = <&gpio5 12 0>; - linux,code = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio5 13 0>; - linux,code = ; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio4 0 0>; - linux,code = ; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-ard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_1__GPIO1_1 0x80000000 - MX53_PAD_GPIO_9__GPIO1_9 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_GPIO_10__GPIO4_0 0x80000000 - MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 - MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 - MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 - MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 - MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 - MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 - MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 - MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 - MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 - MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 - MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 - MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 - MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 - MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 - MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 - MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 - MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 - MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 - MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 - MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 - MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 - MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts deleted file mode 100644 index 055d23a9aee7..000000000000 --- a/arch/arm/boot/dts/imx53-cx9020.dts +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2017 Beckhoff Automation GmbH & Co. KG - * based on imx53-qsb.dts - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Beckhoff CX9020 Embedded PC"; - compatible = "bhf,cx9020", "fsl,imx53"; - - chosen { - stdout-path = &uart2; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - display-0 { - #address-cells =<1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp0>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display0_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; - }; - - dvi-connector { - compatible = "dvi-connector"; - ddc-i2c-bus = <&i2c2>; - digital; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-converter { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&display0_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-pwr-r { - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-pwr-g { - gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-pwr-b { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-sd1-b { - linux,default-trigger = "mmc0"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - }; - - led-sd2-b { - linux,default-trigger = "mmc1"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - }; - }; - - regulator-3p2v { - compatible = "regulator-fixed"; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,dte-mode; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_CLKO 0x1c4 - MX53_PAD_GPIO_16__I2C3_SDA 0x1c4 - MX53_PAD_EIM_D22__GPIO3_22 0x1c4 - MX53_PAD_EIM_D23__GPIO3_23 0x1e4 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 - MX53_PAD_GPIO_3__GPIO1_3 0x1c4 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4 - MX53_PAD_EIM_D20__GPIO3_20 0x1e4 - MX53_PAD_GPIO_8__GPIO1_8 0x1c4 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp0: ipudisp0grp { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 - MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 - MX53_PAD_EIM_D28__UART2_RTS 0x1e4 - MX53_PAD_EIM_D29__UART2_CTS 0x1e4 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/imx53-kp-ddc.dts deleted file mode 100644 index 0e7f071fd10e..000000000000 --- a/arch/arm/boot/dts/imx53-kp-ddc.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx53-kp.dtsi" - -/ { - model = "K+P imx53 DDC"; - compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - power-supply = <®_backlight>; - brightness-levels = <0 24 28 32 36 - 40 44 48 52 56 - 60 64 68 72 76 - 80 84 88 92 96 100>; - default-brightness-level = <20>; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp>; - - port@0 { - reg = <0>; - - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - lcd_panel: lcd-panel { - compatible = "koe,tx14d24vm1bpa"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "backlight-supply"; - regulator-min-microvolt = <15000000>; - regulator-max-microvolt = <15000000>; - regulator-always-on; - }; -}; - -&fec { - status = "okay"; -}; - -&i2c3 { - adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <2>; - ti,datarate = <4>; - }; - - channel@6 { - reg = <6>; - ti,gain = <2>; - ti,datarate = <4>; - }; - }; - - gpio-expander2@21 { - compatible = "nxp,pcf8574"; - reg = <0x21>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; -}; - -&iomuxc { - imx53-kp-ddc { - pinctrl_disp: dispgrp { - fsl,pins = < - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 - MX53_PAD_GPIO_1__PWM2_PWMO 0x4 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&pmic { - fsl,mc13xxx-uses-touch; -}; diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/imx53-kp-hsc.dts deleted file mode 100644 index 6e3d71baac0f..000000000000 --- a/arch/arm/boot/dts/imx53-kp-hsc.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx53-kp.dtsi" - -/ { - model = "K+P imx53 HSC"; - compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; -}; - -&fec { - status = "okay"; - - fixed-link { /* RMII fixed link to LAN9303 */ - speed = <100>; - full-duplex; - }; -}; - -&i2c3 { - switch: switch@a { - compatible = "smsc,lan9303-i2c"; - reg = <0xa>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <400>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { /* RMII fixed link to master */ - reg = <0>; - label = "cpu"; - ethernet = <&fec>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi deleted file mode 100644 index 4508f34139a0..000000000000 --- a/arch/arm/boot/dts/imx53-kp.dtsi +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx53-tqma53.dtsi" -#include - -/ { - buzzer { - compatible = "pwm-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buzzer>; - pwms = <&pwm1 0 500000>; - }; - - gpio-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiobuttons>; - - button-kalt { - label = "Kaltstart"; - linux,code = ; - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - }; - - button-pwr { - label = "PowerFailInterrupt"; - linux,code = ; - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-bus { - label = "bus"; - gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - led-error { - label = "error"; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - led-flash { - label = "flash"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - gpio-expander1@22 { - compatible = "nxp,pcf8574"; - reg = <0x22>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kp_common>; - - imx53-kp-common { - pinctrl_buzzer: buzzergrp { - fsl,pins = < - MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 - >; - }; - - pinctrl_gpiobuttons: gpiobuttonsgrp { - fsl,pins = < - MX53_PAD_EIM_RW__GPIO2_26 0x1e4 - MX53_PAD_EIM_D22__GPIO3_22 0x1e4 - >; - }; - - pinctrl_kp_common: kpcommongrp { - fsl,pins = < - MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 - MX53_PAD_GPIO_19__GPIO4_5 0x1e4 - MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 - MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 - MX53_PAD_EIM_D18__GPIO3_18 0x1e4 - MX53_PAD_EIM_D21__GPIO3_21 0x1e4 - MX53_PAD_EIM_D29__GPIO3_29 0x1e4 - MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 - MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 - MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 - MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 - MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 - MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 - >; - }; - - pinctrl_leds: ledgrp { - fsl,pins = < - MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 - MX53_PAD_EIM_D28__GPIO3_28 0x1d4 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&pinctrl_uart1 { - fsl,pins = < - MX53_PAD_EIM_D23__GPIO3_23 0x1e4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 - MX53_PAD_EIM_D25__GPIO3_25 0x1e4 - MX53_PAD_EIM_D19__GPIO3_19 0x1e4 - MX53_PAD_EIM_D20__GPIO3_20 0x1e4 - >; -}; - -&pwm1 { - #pwm-cells = <2>; -}; - -&pwm2 { - #pwm-cells = <2>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy0 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi deleted file mode 100644 index fe5e0d308e99..000000000000 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Marek Vasut - */ - -#include "imx53.dtsi" - -/ { - model = "Aries/DENX M53"; - compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_backlight: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd-supply"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@41 { - compatible = "st,stmpe610"; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - interrupts = <6 0x0>; - interrupt-parent = <&gpio7>; - irq-trigger = <0x1>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <3>; - st,touch-det-delay = <3>; - st,settling = <4>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 - MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts deleted file mode 100644 index 2bd2432d317f..000000000000 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ /dev/null @@ -1,371 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013 Marek Vasut - */ - -/dts-v1/; -#include "imx53-m53.dtsi" - -/ { - model = "Aries/DENX M53EVK"; - compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; - - display1: disp1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <31500000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <128>; - vback-porch = <33>; - vfront-porch = <9>; - vsync-len = <3>; - vsync-active = <1>; - }; - }; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 3000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_backlight>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio>; - - led-user1 { - label = "user1"; - gpios = <&gpio2 8 0>; - linux,default-trigger = "heartbeat"; - }; - - led-user2 { - label = "user2"; - gpios = <&gpio2 9 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 0>; - }; - - reg_usb_otg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 0>; - }; - }; - - sound { - compatible = "fsl,imx53-m53evk-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-m53evk-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Ext Spk", "LINE_OUT"; - mux-int-port = <2>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - pinctrl_usb: usbgrp { - fsl,pins = < - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x000b0 - >; - }; - - led_pin_gpio: led_gpio { - fsl,pins = < - MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 - MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 - MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb>; - vbus-supply = <®_usbh1_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts deleted file mode 100644 index 4d77b6077fc1..000000000000 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ /dev/null @@ -1,517 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marek Vasut - */ - -/dts-v1/; -#include "imx53-m53.dtsi" - -/ { - model = "MENLO M53 EMBEDDED DEVICE"; - compatible = "menlo,m53menlo", "fsl,imx53"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_power_button>; - pinctrl-names = "default"; - - power-button { - label = "Power button"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pinctrl_power_out>; - pinctrl-names = "default"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-user1 { - label = "TestLed601"; - gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - led-user2 { - label = "TestLed602"; - gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-eth { - label = "EthLedYe"; - gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "netdev"; - }; - }; - - lvds-decoder { - compatible = "ti,ds90cf364a", "lvds-decoder"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_decoder_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - - lvds_decoder_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; - - panel { - compatible = "edt,etm0700g0dh6"; - pinctrl-0 = <&pinctrl_display_gpio>; - pinctrl-names = "default"; - enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_decoder_out>; - }; - }; - }; - - beeper { - compatible = "gpio-beeper"; - pinctrl-0 = <&pinctrl_beeper>; - gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 0>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, - <&clks IMX5_CLK_CKO1_PODF>, - <&clks IMX5_CLK_CKO1>; - assigned-clock-parents = <&clks IMX5_CLK_AHB>; - assigned-clock-rates = <133333334>, <33333334>, <33333334>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>; - status = "okay"; - - spidev@0 { - compatible = "menlo,m53cpld"; - spi-max-frequency = <25000000>; - reg = <0>; - }; - - spidev@1 { - compatible = "menlo,m53cpld"; - spi-max-frequency = <25000000>; - reg = <1>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "TestPin_SV2_3", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", - "", "CPLD_JTAG_TDO", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "CPLD_JTAG_TCK", "KBD_intK", - "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", - "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", - "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; -}; - -&gpio6 { - gpio-line-names = - "", "", "", "", - "CPLD_reset", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio7 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "USB-OTG_OverCurrent", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio6>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - dac@60 { - compatible = "microchip,mcp4725"; - reg = <0x60>; - }; -}; - -&i2c2 { - touchscreen@41 { - status = "disabled"; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - hoggrp { - fsl,pins = < - MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 - MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 - MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 - MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 - MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 - MX53_PAD_EIM_D25__GPIO3_25 0x1e4 - MX53_PAD_EIM_D29__GPIO3_29 0x1e4 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 - MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 - >; - }; - - pinctrl_beeper: beepergrp { - fsl,pins = < - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 - >; - }; - - pinctrl_display_gpio: display-gpiogrp { - fsl,pins = < - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ - - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ - MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 - MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 - MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 - MX53_PAD_EIM_RW__GPIO2_26 0xe4 - MX53_PAD_EIM_LBA__GPIO2_27 0xe4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 - MX53_PAD_GPIO_1__GPIO1_1 0x1c4 - MX53_PAD_GPIO_9__GPIO1_9 0x1e4 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 - MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 - MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 - >; - }; - - pinctrl_lvds0: lvds0grp { - /* LVDS pins only have pin mux configuration */ - fsl,pins = < - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - >; - }; - - pinctrl_power_button: powerbutgrp { - fsl,pins = < - MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 - >; - }; - - pinctrl_power_out: poweroutgrp { - fsl,pins = < - MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - - pinctrl_usb: usbgrp { - fsl,pins = < - MX53_PAD_GPIO_2__GPIO1_2 0x1c4 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 - MX53_PAD_GPIO_4__GPIO1_4 0x1c4 - MX53_PAD_GPIO_18__GPIO7_13 0x1c4 - >; - }; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0>; - status = "okay"; - - lvds0: lvds-channel@0 { - reg = <0>; - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@2 { - reg = <2>; - - lvds0_out: endpoint { - remote-endpoint = <&lvds_decoder_in>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb>; - vbus-supply = <®_usbh1_vbus>; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts deleted file mode 100644 index 09eee0dd44c1..000000000000 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer , Pengutronix - * Copyright 2012 Steffen Trumtrar , Pengutronix - */ - -/dts-v1/; -#include "imx53-tqma53.dtsi" - -/ { - model = "TQ MBa53 starter kit"; - compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; - - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; - default-brightness-level = <10>; - enable-gpios = <&gpio7 7 0>; - power-supply = <®_backlight>; - }; - - disp1: disp1 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp1_1>; - interface-pix-fmt = "rgb24"; - status = "disabled"; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_backlight: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd-supply"; - gpio = <&gpio2 5 0>; - startup-delay-us = <5000>; - }; - - reg_3p2v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - }; - - sound { - compatible = "tq,imx53-mba53-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-mba53-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds1_1>; - status = "disabled"; -}; - -&iomuxc { - lvds1 { - pinctrl_lvds1_1: lvds1-grp1 { - fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - >; - }; - - pinctrl_lvds1_2: lvds1-grp2 { - fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - >; - }; - }; - - disp1 { - pinctrl_disp1_1: disp1-grp1 { - fsl,pins = < - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ - MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 - >; - }; - }; - - tve { - pinctrl_vga_sync_1: vgasync-grp1 { - fsl,pins = < - /* VGA_VSYNC, HSYNC with max drive strength */ - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&cspi { - status = "okay"; -}; - -&audmux { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; -}; - -&i2c2 { - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - }; - - expander: pca9554@20 { - compatible = "pca9554"; - reg = <0x20>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; - - sensor2: lm75@49 { - compatible = "lm75"; - reg = <0x49>; - }; -}; - -&fec { - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&esdhc2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ecspi1 { - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&tve { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vga_sync_1>; - ddc-i2c-bus = <&i2c3>; - fsl,tve-mode = "vga"; - fsl,hsync-pin = <4>; - fsl,vsync-pin = <6>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/imx53-pinfunc.h deleted file mode 100644 index 67bd06610fdf..000000000000 --- a/arch/arm/boot/dts/imx53-pinfunc.h +++ /dev/null @@ -1,1189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX53_PINFUNC_H -#define __DTS_IMX53_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 -#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 -#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 -#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 -#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 -#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 -#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 -#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 -#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 -#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 -#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 -#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 -#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 -#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 -#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 -#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 -#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 -#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 -#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 -#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 -#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 -#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 -#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 -#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 -#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 -#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 -#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 -#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 -#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 -#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 -#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 -#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 -#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 -#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 -#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 -#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 -#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 -#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 -#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 -#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 -#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 -#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 -#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 -#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 -#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 -#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 -#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 -#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 -#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 -#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 -#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 -#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 -#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 -#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 -#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 -#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 -#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 -#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 -#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 -#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 -#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 -#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 -#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 -#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 -#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 -#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 -#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 -#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 -#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 -#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 -#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 -#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 -#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 -#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 -#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 -#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 -#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 -#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 -#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 -#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 -#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 -#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 -#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 -#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 -#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 -#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 -#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 -#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 -#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 -#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 -#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 -#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 -#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 -#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 -#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 -#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 -#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 -#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 -#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 -#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 -#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 -#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 -#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 -#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 -#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 -#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 -#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 -#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 -#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 -#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 -#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 -#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 -#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 -#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 -#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 -#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 -#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 -#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 -#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 -#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 -#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 -#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 -#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 -#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 -#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 -#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 -#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 -#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 -#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 -#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 -#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 -#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 -#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 -#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 -#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 -#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 -#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 -#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 -#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 -#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 -#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 -#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 -#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 -#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 -#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 -#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 -#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 -#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 -#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 -#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 -#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 -#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 -#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 -#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 -#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 -#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 -#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 -#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 -#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 - -#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts deleted file mode 100644 index 70c4a4852256..000000000000 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ /dev/null @@ -1,1122 +0,0 @@ -/* - * Copyright 2014 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx53.dtsi" -#include - -/ { - model = "General Electric CS ONE"; - compatible = "ge,imx53-cpuvo", "fsl,imx53"; - - aliases { - spi0 = &cspi; - spi1 = &ecspi1; - spi2 = &ecspi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - cko2_11M: sgtl-clock-cko2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - achc_24M: achc-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - sgtlsound: sound { - compatible = "fsl,imx53-cpuvo-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-cpuvo-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <6>; - }; - - reg_sgtl5k: regulator-sgtl5k { - compatible = "regulator-fixed"; - regulator-name = "regulator-sgtl5k"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-0 = <&pinctrl_usb_otg_vbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usbh2_vbus: regulator-usbh2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbh3_vbus: regulator-usbh3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh3_vbus>; - gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_tsiref: regulator-tsiref { - compatible = "regulator-fixed"; - regulator-name = "tsiref"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - /* TPS54320 */ - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3v3_lcd: regulator-3v3-lcd { - /* MIC2009 */ - compatible = "regulator-fixed"; - regulator-name = "LCD_3V3"; - vin-supply = <®_3v3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pwm_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 - 38 40 43 45 48 51 53 56 58 61 63 66 68 71 - 73 76 79 81 84 86 89 91 94 96 99 102 104 - 107 109 112 114 117 119 122 124 127 130 - 132 135 137 140 142 145 147 150 153 155 - 158 160 163 165 168 170 173 175 178 181 - 183 186 188 191 193 196 198 201 204 206 - 209 211 214 216 219 221 224 226 229 232 - 234 237 239 242 244 247 249 252 255>; - default-brightness-level = <0>; - enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3_lcd>; - }; - - led-controller-1 { - compatible = "pwm-leds"; - - led-1 { - label = "alarm-brightness"; - pwms = <&pwm1 0 100000>; - max-brightness = <255>; - }; - }; - - led-controller-2 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_alarmled_pins>; - - led-2 { - label = "alarm:red"; - gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "alarm:yellow"; - gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; - }; - - led-4 { - label = "alarm:blue"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - }; - - led-5 { - label = "alarm:silenced"; - gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - active-delay = <100>; - inactive-delay = <10>; - wait-delay = <100>; - }; - - power-gpio-keys { - compatible = "gpio-keys"; - - power-button { - label = "Power button"; - gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - touch-lock-key { - compatible = "gpio-keys"; - - touch-lock-button { - label = "Touch lock button"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - usbphy2: usbphy-2 { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_3v3>; - reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; - clock-names = "main_clk"; - clock-frequency = <24000000>; - clocks = <&clks IMX5_CLK_CKO2>; - assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; - assigned-clock-parents = <&clks IMX5_CLK_OSC>; - }; - - usbphy3: usbphy-3 { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_3v3>; - reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; - clock-names = "main_clk"; - - clock-frequency = <24000000>; - clocks = <&clks IMX5_CLK_CKO2>; - assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; - assigned-clock-parents = <&clks IMX5_CLK_OSC>; - }; - - panel-lvds0 { - compatible = "nvd,9128"; - power-supply = <®_3v3_lcd>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&usbphy0 { - vcc-supply = <®_3v3>; -}; - -&usbphy1 { - vcc-supply = <®_3v3>; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&cpu0 { - /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ - operating-points = < - /* kHz uV */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - >; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW - &gpio4 10 GPIO_ACTIVE_LOW - &gpio4 11 GPIO_ACTIVE_LOW - &gpio4 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - spidev0: spi@1 { - compatible = "ge,achc", "nxp,kinetis-k20"; - reg = <1>, <0>; - vdd-supply = <®_3v3>; - vdda-supply = <®_3v3>; - clocks = <&achc_24M>; - reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - }; - - gpioxra0: gpio@2 { - compatible = "exar,xra1403"; - reg = <2>; - gpio-controller; - #gpio-cells = <2>; - spi-max-frequency = <1000000>; - }; - - gpioxra1: gpio@3 { - compatible = "exar,xra1403"; - reg = <3>; - gpio-controller; - #gpio-cells = <2>; - spi-max-frequency = <1000000>; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - status = "okay"; - - da9053@0 { - compatible = "dlg,da9053-aa"; - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <1000000>; - dlg,tsi-as-adc; - tsiref-supply = <®_tsiref>; - - regulators { - buck1_reg: buck1 { - regulator-name = "BUCKCORE"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-name = "BUCKPRO"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-name = "BUCKMEM"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-name = "BUCKPERI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "ldo1_1v3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2_1v3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "ldo3_3v3"; - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-name = "ldo4_2v775"; - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "ldo5_3v3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "ldo6_1v3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-name = "ldo7_2v75"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "ldo8_1v8"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-name = "ldo9_1v5"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3650000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-name = "ldo10_1v3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - }; - }; - -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - bus-width = <8>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-supply = <®_3v3>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9547"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; - - i2c4: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - VDDA-supply = <®_sgtl5k>; - VDDIO-supply = <®_sgtl5k>; - clocks = <&cko2_11M>; - status = "okay"; - }; - }; - - i2c5: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - - temp@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - }; - - mma8453q: accelerometer@1c { - compatible = "fsl,mma8453"; - reg = <0x1c>; - interrupt-parent = <&gpio1>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-names = "INT1"; - }; - - mpl3115: pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; - }; - - i2c6: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c7: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c8: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c9: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c10: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c11: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - status = "okay"; - - touchscreen@4b { - compatible = "atmel,maxtouch"; - reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; - reg = <0x4b>; - interrupt-parent = <&gpio5>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@2 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pmu { - secure-reg-access; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,dma-info = <24 20>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - fsl,dma-info = <4096 4>; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - phy_type = "utmi"; - vbus-supply = <®_usb_otg_vbus>; - pinctrl-0 = <&pinctrl_usb_otg>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - phy_type = "ulpi"; - dr_mode = "host"; - fsl,usbphy = <&usbphy2>; - vbus-supply = <®_usbh2_vbus>; - status = "okay"; -}; - -&usbh3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh3>; - phy_type = "ulpi"; - dr_mode = "host"; - vbus-supply = <®_usbh3_vbus>; - fsl,usbphy = <&usbphy3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_rev6>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400 - MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400 - MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400 - MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400 - MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400 - MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400 - MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400 - MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400 - MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400 - MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400 - /* ECSPI1_SS0, must treat as GPIO for EzPort */ - MX53_PAD_DISP0_DAT23__GPIO5_17 0x400 - MX53_PAD_KEY_COL2__GPIO4_10 0x0 - MX53_PAD_KEY_ROW2__GPIO4_11 0x0 - MX53_PAD_KEY_COL3__GPIO4_12 0x0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0 - MX53_PAD_EIM_OE__ECSPI2_MISO 0x0 - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0 - MX53_PAD_EIM_RW__GPIO2_26 0x0 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x0 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x0 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0 - >; - }; - - pinctrl_hog_rev6: hoggrp { - fsl,pins = < - /* CKO2 */ - MX53_PAD_GPIO_3__CCM_CLKO2 0x4 - /* DEFIB_SYNC_MARKER_IN_IRQ */ - MX53_PAD_GPIO_5__GPIO1_5 0x0 - /* ACCELEROMETER_DATA_RDY_N */ - MX53_PAD_GPIO_6__GPIO1_6 0x0 - /* TEMPERATURE_ALERT_N */ - MX53_PAD_GPIO_7__GPIO1_7 0x0 - /* BAROMETRIC_PRESSURE_DATA_RDY_N */ - MX53_PAD_GPIO_8__GPIO1_8 0x0 - /* DOCKING_I2C_INTERFACE_IRQ_N */ - MX53_PAD_PATA_DATA4__GPIO2_4 0x0 - /* PWR_OUT_TO_DOCK_FAULT_N */ - MX53_PAD_PATA_DATA5__GPIO2_5 0x0 - /* ENABLE_PWR_TO_DOCK_N */ - MX53_PAD_PATA_DATA6__GPIO2_6 0x0 - /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ - MX53_PAD_PATA_DATA7__GPIO2_7 0x0 - /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */ - MX53_PAD_PATA_DATA12__GPIO2_12 0x0 - /* DOCK_PRESENT_N */ - MX53_PAD_PATA_DATA13__GPIO2_13 0x0 - /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */ - MX53_PAD_PATA_DATA14__GPIO2_14 0x0 - /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */ - MX53_PAD_PATA_DATA15__GPIO2_15 0x0 - /* RESET_IMX535_ETHERNET_PHY_N */ - MX53_PAD_EIM_A22__GPIO2_16 0x0 - /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ - MX53_PAD_EIM_A21__GPIO2_17 0x0 - /* RESET_I2C1_BUS_SEGMENT_MUX_N */ - MX53_PAD_EIM_A20__GPIO2_18 0x0 - /* RESET_IMX535_USB_HOST3_PHY_N */ - MX53_PAD_EIM_A19__GPIO2_19 0x0 - /* ESDHC3_EMMC_NAND_RST_N */ - MX53_PAD_EIM_A18__GPIO2_20 0x0 - /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */ - MX53_PAD_EIM_A17__GPIO2_21 0x0 - /* POWER_DOWN_LVDS0_DESERIALIZER_N */ - MX53_PAD_EIM_A16__GPIO2_22 0x0 - /* POWER_DOWN_LVDS1_DESERIALIZER_N */ - MX53_PAD_EIM_LBA__GPIO2_27 0x0 - /* RESET_DP0_TRANSMITTER_N */ - MX53_PAD_EIM_EB0__GPIO2_28 0x0 - /* RESET_DP1_TRANSMITTER_N */ - MX53_PAD_EIM_EB1__GPIO2_29 0x0 - /* ENABLE_SPDIF_AUDIO_TO_DP0 */ - MX53_PAD_EIM_DA0__GPIO3_0 0x0 - /* ENABLE_SPDIF_AUDIO_TO_DP1 */ - MX53_PAD_EIM_DA1__GPIO3_1 0x0 - /* LVDS1_MUX_CTRL */ - MX53_PAD_EIM_DA2__GPIO3_2 0x0 - /* LVDS0_MUX_CTRL */ - MX53_PAD_EIM_DA3__GPIO3_3 0x0 - /* DP1_TRANSMITTER_IRQ */ - MX53_PAD_EIM_DA4__GPIO3_4 0x0 - /* DP0_TRANSMITTER_IRQ */ - MX53_PAD_EIM_DA5__GPIO3_5 0x0 - /* USB_RESET_N */ - MX53_PAD_EIM_DA6__GPIO3_6 0x0 - /* ENABLE_BATTERY_CHARGER */ - MX53_PAD_EIM_DA7__GPIO3_7 0x0 - /* SOFTWARE_CONTROLLED_PWR_CYCLE */ - MX53_PAD_EIM_DA8__GPIO3_8 0x0 - /* SOFTWARE_CONTROLLED_POWERDOWN */ - MX53_PAD_EIM_DA9__GPIO3_9 0x0 - /* DC_PWR_IN_OK */ - MX53_PAD_EIM_DA10__GPIO3_10 0x0 - /* BATT_PRESENT_N */ - MX53_PAD_EIM_DA11__GPIO3_11 0xe4 - /* PMIC_IRQ_N */ - MX53_PAD_EIM_DA12__GPIO3_12 0x0 - /* PMIC_VDD_FAULT_STATUS_N */ - MX53_PAD_EIM_DA13__GPIO3_13 0x0 - /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */ - MX53_PAD_EIM_DA14__GPIO3_14 0x0 - /* NOT USED - AVAILABLE 3.3V GPIO */ - MX53_PAD_EIM_DA15__GPIO3_15 0x0 - /* NOT USED - AVAILABLE 3.3V GPIO */ - MX53_PAD_EIM_D22__GPIO3_22 0x0 - /* NOT USED - AVAILABLE 3.3V GPIO */ - MX53_PAD_EIM_D24__GPIO3_24 0x0 - /* NBP_PUMP_VALVE_PWR_ENABLE */ - MX53_PAD_EIM_D25__GPIO3_25 0x0 - /* NIBP_RESET_N */ - MX53_PAD_EIM_D26__GPIO3_26 0x0 - /* LATCHED_OVERPRESSURE_N */ - MX53_PAD_EIM_D27__GPIO3_27 0x0 - /* NBP_SBWTCLK */ - MX53_PAD_EIM_D29__GPIO3_29 0x0 - /* ENABLE_WIFI_MODULE */ - MX53_PAD_GPIO_11__GPIO4_1 0x400 - /* WIFI_MODULE_IRQ_N */ - MX53_PAD_GPIO_12__GPIO4_2 0x400 - /* ENABLE_BLUETOOTH_MODULE */ - MX53_PAD_GPIO_13__GPIO4_3 0x400 - /* RESET_IMX535_USB_HOST2_PHY_N */ - MX53_PAD_GPIO_14__GPIO4_4 0x400 - /* ONKEY_IS_DEPRESSED */ - MX53_PAD_KEY_ROW3__GPIO4_13 0x0 - /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */ - MX53_PAD_EIM_WAIT__GPIO5_0 0x0 - /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */ - MX53_PAD_EIM_A25__GPIO5_2 0x0 - /* I2C_PCAP_TOUCHSCREEN_IRQ_N */ - MX53_PAD_EIM_A24__GPIO5_4 0x0 - /* NOT USED - AVAILABLE 1.8V GPIO */ - MX53_PAD_DISP0_DAT13__GPIO5_7 0x400 - /* NOT USED - AVAILABLE 1.8V GPIO */ - MX53_PAD_DISP0_DAT14__GPIO5_8 0x400 - /* NOT USED - AVAILABLE 1.8V GPIO */ - MX53_PAD_DISP0_DAT15__GPIO5_9 0x400 - /* HOST_CONTROLLED_RESET_TO_LCD_N */ - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0 - /* HOST_CONTROLLED_RESET_TO_PCAP_N */ - MX53_PAD_CSI0_MCLK__GPIO5_19 0x0 - /* LR_SCAN_CTRL */ - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0 - /* UD_SCAN_CTRL */ - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0 - /* DATA_WIDTH_CTRL */ - MX53_PAD_CSI0_DAT10__GPIO5_28 0x0 - /* BACKLIGHT_ENABLE */ - MX53_PAD_CSI0_DAT11__GPIO5_29 0x0 - /* MED_USB_PORT_1_HOST_SELECT */ - MX53_PAD_EIM_A23__GPIO6_6 0x0 - /* MED_USB_PORT_2_HOST_SELECT */ - MX53_PAD_NANDF_CLE__GPIO6_7 0x0 - /* MED_USB_PORT_3_HOST_SELECT */ - MX53_PAD_NANDF_ALE__GPIO6_8 0x0 - /* MED_USB_PORT_4_HOST_SELECT */ - MX53_PAD_NANDF_WP_B__GPIO6_9 0x0 - /* MED_USB_PORT_5_HOST_SELECT */ - MX53_PAD_NANDF_RB0__GPIO6_10 0x0 - /* MED_USB_PORT_6_HOST_SELECT */ - MX53_PAD_NANDF_CS0__GPIO6_11 0x0 - /* MED_USB_PORT_7_HOST_SELECT */ - MX53_PAD_NANDF_WE_B__GPIO6_12 0x0 - /* MED_USB_PORT_8_HOST_SELECT */ - MX53_PAD_NANDF_RE_B__GPIO6_13 0x0 - /* MED_USB_PORT_TO_IMX_SELECT_0 */ - MX53_PAD_NANDF_CS1__GPIO6_14 0x0 - /* MED_USB_PORT_TO_IMX_SELECT_1 */ - MX53_PAD_NANDF_CS2__GPIO6_15 0x0 - /* MED_USB_PORT_TO_IMX_SELECT_2 */ - MX53_PAD_NANDF_CS3__GPIO6_16 0x0 - /* POWER_AND_BOOT_STATUS_INDICATOR */ - MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 - /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ - MX53_PAD_GPIO_16__GPIO7_11 0x0 - /* BATTERY_STATUS_INDICATOR_AMBER */ - MX53_PAD_GPIO_17__GPIO7_12 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D28__GPIO3_28 0x1e4 - MX53_PAD_EIM_D21__GPIO3_21 0x1e4 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 - MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D16__GPIO3_16 0x1e4 - MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 - MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D18__GPIO3_18 0x1e4 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX53_PAD_GPIO_9__PWM1_PWMO 0x5 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_EIM_D23__UART3_CTS 0x1e4 - MX53_PAD_EIM_EB3__UART3_RTS 0x1e4 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 - >; - }; - - pinctrl_usb_otg_vbus: usb-otg-vbusgrp { - fsl,pins = < - /* USB_HS_OTG_VBUS_ENABLE */ - MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - /* USB H2 */ - MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180 - MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180 - MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180 - MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180 - MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180 - MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180 - MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180 - MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180 - MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180 - MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180 - MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180 - MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5 - MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180 - >; - }; - - pinctrl_usbh2_vbus: usbh2-vbusgrp { - fsl,pins = < - /* USB_HS_HOST2_VBUS_ENABLE */ - MX53_PAD_EIM_D31__GPIO3_31 0x0 - >; - }; - - pinctrl_usbh3_vbus: usbh3-vbusgrp { - fsl,pins = < - /* USB_HS_HOST3_VBUS_ENABLE */ - MX53_PAD_CSI0_DAT9__GPIO5_27 0x0 - >; - }; - - pinctrl_usbh3: usbh3grp { - fsl,pins = < - /* USB H3 */ - MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180 - MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180 - MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180 - MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180 - MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180 - MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180 - MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180 - MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180 - MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5 - MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180 - MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180 - MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180 - MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180 - >; - }; - - pinctrl_usb_otg: usbotggrp { - fsl,pins = < - /* USB_OTG_FAULT_N */ - MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 - >; - }; - - pinctrl_alarmled_pins: qmx6alarmledgrp { - fsl,pins = < - /* ACTIVATE_ALARM_LIGHT_RED */ - MX53_PAD_PATA_DIOR__GPIO7_3 0x0 - /* ACTIVATE_ALARM_LIGHT_YELLOW */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x0 - /* ACTIVATE_ALARM_LIGHT_CYAN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x0 - /* AUDIO_ALARMS_SILENCED_INDICATOR */ - MX53_PAD_GPIO_18__GPIO7_13 0x0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi deleted file mode 100644 index 50fef8dd3675..000000000000 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ /dev/null @@ -1,387 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx53.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - display0: disp0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp0>; - - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power Button"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio7_7>; - - led-user { - label = "Heartbeat"; - gpios = <&gpio7 7 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel { - compatible = "sii,43wvf1g"; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx53-qsb-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-qsb-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&cpu0 { - /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ - operating-points = < - /* kHz uV */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - >; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&ssi2 { - status = "okay"; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-qsb { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_8__GPIO1_8 0x80000000 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 - MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - >; - }; - - led_pin_gpio7_7: led_gpio7_7 { - fsl,pins = < - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_EIM_DA13__GPIO3_13 0xe4 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 - >; - }; - - /* open drain */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec - MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp0: ipudisp0grp { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_vga_sync: vgasync-grp { - fsl,pins = < - /* VGA_HSYNC, VSYNC with max drive strength */ - MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 - MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&tve { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vga_sync>; - ddc-i2c-bus = <&i2c2>; - fsl,tve-mode = "vga"; - fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ - fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts deleted file mode 100644 index 6831836bd726..000000000000 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include "imx53-qsb-common.dtsi" - -/ { - model = "Freescale i.MX53 Quick Start Board"; - compatible = "fsl,imx53-qsb", "fsl,imx53"; -}; - -&i2c1 { - pmic: dialog@48 { - compatible = "dlg,da9053-aa", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ - - regulators { - buck1_reg: buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - ldo8_reg: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - }; - }; -}; - -&tve { - dac-supply = <&ldo7_reg>; -}; diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts deleted file mode 100644 index 1bbf24ad308a..000000000000 --- a/arch/arm/boot/dts/imx53-qsrb.dts +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx53-qsb-common.dtsi" - -/ { - model = "Freescale i.MX53 Quick Start-R Board"; - compatible = "fsl,imx53-qsrb", "fsl,imx53"; -}; - -&iomuxc { - imx53-qsrb { - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */ - >; - }; - }; -}; - -&i2c1 { - pmic: mc34708@8 { - compatible = "fsl,mc34708"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x08>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - regulators { - sw1_reg: sw1a { - regulator-name = "SW1"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw1b_reg: sw1b { - regulator-name = "SW1B"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-name = "SW2"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-name = "SW3"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - }; - - sw4a_reg: sw4a { - regulator-name = "SW4A"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4b_reg: sw4b { - regulator-name = "SW4B"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw5_reg: sw5 { - regulator-name = "SW5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-name = "SWBST"; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-name = "VPLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - vrefddr_reg: vrefddr { - regulator-name = "VREFDDR"; - regulator-boot-on; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-name = "VUSB"; - regulator-boot-on; - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-name = "VUSB2"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vdac_reg: vdac { - regulator-name = "VDAC"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - vgen1_reg: vgen1 { - regulator-name = "VGEN1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-name = "VGEN2"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&tve { - dac-supply = <&vdac_reg>; -}; diff --git a/arch/arm/boot/dts/imx53-sk-imx53.dts b/arch/arm/boot/dts/imx53-sk-imx53.dts deleted file mode 100644 index 103e73176e47..000000000000 --- a/arch/arm/boot/dts/imx53-sk-imx53.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2023 Linaro Ltd. - -/dts-v1/; - -#include "imx53.dtsi" - -/ { - model = "StarterKit SK-iMX53 Board"; - compatible = "starterkit,sk-imx53", "fsl,imx53"; - - aliases { - /* - * iMX RTC is not battery powered on this board. - * Use the i2c RTC as rtc0. - */ - rtc0 = &rtc; - rtc1 = &srtc; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@70000000 { - device_type = "memory"; - /* v2 had only 256 MB, v3 has 512 MB */ - reg = <0x70000000 0x20000000>; - }; - - reg_usb1_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&esdhc1 { - cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - status = "okay"; - - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - #sound-dai-cells = <0>; - }; - - rtc: rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x1e4 - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x1e4 - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x1e4 - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x1e4 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x1e4 - MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x1e4 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x1e4 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x1e4 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x1e4 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x1e4 - MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x1e4 - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x1e4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_EIM_DA14__GPIO3_14 0x1f0 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 - MX53_PAD_GPIO_1__GPIO1_1 0x1c4 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0x400001e4 - MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4 - MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x4 - MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x4 - MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x4 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX53_PAD_GPIO_9__PWM1_PWMO 0x5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_EIM_D24__UART3_TXD_MUX 0x1e4 - MX53_PAD_EIM_D25__UART3_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 - >; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x00100000 0x00100000>; - read-only; - }; - - partition@200000 { - label = "u-boot-env"; - reg = <0x00200000 0x00100000>; - read-only; - }; - - partition@1000000 { - label = "kernel-safe"; - reg = <0x01000000 0x00a00000>; - read-only; - }; - - partition@1a00000 { - label = "kernel"; - reg = <0x01a00000 0x005e0000>; - }; - - partition@2000000 { - label = "ubifs"; - reg = <0x02000000 0x0e000000>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb1_vbus>; - phy_type = "utmi"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts deleted file mode 100644 index f8d17967a67e..000000000000 --- a/arch/arm/boot/dts/imx53-smd.dts +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Smart Mobile Reference Design Board"; - compatible = "fsl,imx53-smd", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 0>; - linux,code = ; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 0>; - linux,code = ; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - non-removable; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - zigbee: mc1323@0 { - compatible = "fsl,mc1323"; - spi-max-frequency = <8000000>; - reg = <0>; - }; - - flash: m25p32@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "st,m25p", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-smd { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 - MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 - MX53_PAD_EIM_D19__GPIO3_19 0x80000000 - MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_csi0: ipucsi0grp { - fsl,pins = < - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 - >; - }; - - pinctrl_ov5642: ov5642grp { - fsl,pins = < - MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 - MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - }; - - magnetometer: mag3110@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - }; - - touchkey: mpr121@5a { - compatible = "fsl,mpr121"; - reg = <0x5a>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - - camera: ov5642@3c { - compatible = "ovti,ov5642"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; - assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>, - <&clks IMX5_CLK_SSI_EXT1_COM_SEL>; - assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>, - <&clks IMX5_CLK_SSI_EXT1_PODF>; - assigned-clock-rates = <0>, <24000000>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - clock-names = "xclk"; - DVDD-supply = <&ldo9_reg>; - AVDD-supply = <&ldo7_reg>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - - port { - ov5642_to_ipu_csi0: endpoint { - remote-endpoint = <&ipu_csi0_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - - pmic: dialog@48 { - compatible = "dlg,da9053", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - - regulators { - ldo7_reg: ldo7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - }; - - ldo9_reg: ldo9 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3650000>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ipu_csi0_from_parallel_sensor { - remote-endpoint = <&ov5642_to_ipu_csi0>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vsync-active = <1>; -}; - -&ipu_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_csi0>; -}; diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi deleted file mode 100644 index d930739674a1..000000000000 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer , Pengutronix - * Copyright 2012 Steffen Trumtrar , Pengutronix - */ - -#include "imx53.dtsi" - -/ { - model = "TQ TQMa53"; - compatible = "tq,tqma53", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x40000000>; /* Up to 1GiB */ - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>, - <&pinctrl_esdhc2_cdwp>; - vmmc-supply = <®_3p3v>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, - <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&esdhc3 { /* EMMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-tqma53 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ - MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ - MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ - MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ - MX53_PAD_GPIO_3__GPIO1_3 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 - MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_cspi: cspigrp { - fsl,pins = < - MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 - MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 - MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_esdhc2_cdwp: esdhc2cdwp { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; -}; - -&pwm2 { - #pwm-cells = <2>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&cspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>, - <&gpio1 21 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: mc34708@8 { - compatible = "fsl,mc34708"; - reg = <0x8>; - fsl,mc13xxx-uses-rtc; - interrupt-parent = <&gpio2>; - interrupts = <6 4>; /* PATA_DATA6, active high */ - }; - - sensor1: lm75@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x50>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts deleted file mode 100644 index a7f77527269d..000000000000 --- a/arch/arm/boot/dts/imx53-tx53-x03x.dts +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright 2013-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx53-tx53.dtsi" -#include -#include -#include - -/ { - model = "Ka-Ro electronics TX53 module (LCD)"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - display = &display; - }; - - display: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb24_vga1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - reg_lcd_pwr: regulator-lcd-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_reset: regulator-lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06_1>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&iomuxc { - imx53-tx53-x03x { - pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { - fsl,pins = < - MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ - MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ - MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 - MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 - MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 - MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 - MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 - MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 - >; - }; - - pinctrl_rgb24_vga1: rgb24-vgagrp1 { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ - >; - }; - }; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0,1 are mapped to KPP row/col 6,7 */ - linux,keymap = < - MATRIX_KEY(6, 6, KEY_POWER) - MATRIX_KEY(6, 7, KEY_KP0) - MATRIX_KEY(6, 2, KEY_KP1) - MATRIX_KEY(6, 3, KEY_KP2) - MATRIX_KEY(7, 6, KEY_KP3) - MATRIX_KEY(7, 7, KEY_KP4) - MATRIX_KEY(7, 2, KEY_KP5) - MATRIX_KEY(7, 3, KEY_KP6) - MATRIX_KEY(2, 6, KEY_KP7) - MATRIX_KEY(2, 7, KEY_KP8) - MATRIX_KEY(2, 2, KEY_KP9) - >; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts deleted file mode 100644 index 6cdf2082c742..000000000000 --- a/arch/arm/boot/dts/imx53-tx53-x13x.dts +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright 2013-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-tx53.dtsi" -#include - -/ { - model = "Ka-Ro electronics TX53 module (LVDS)"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - reg_lcd_pwr0: regulator-lvds0-pwr { - compatible = "regulator-fixed"; - regulator-name = "LVDS0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_pwr1: regulator-lvds1-pwr { - compatible = "regulator-fixed"; - regulator-name = "LVDS1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; -}; - -&iomuxc { - imx53-tx53-x13x { - pinctrl_lvds0: lvds0grp { - fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - >; - }; - - pinctrl_lvds1: lvds1grp { - fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = ; - }; - - pinctrl_eeti1: eeti1grp { - fsl,pins = < - MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ - >; - }; - - pinctrl_eeti2: eeti2grp { - fsl,pins = < - MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ - >; - }; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing0>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hsync-len = <60>; - hfront-porch = <40>; - vback-porch = <21>; - vsync-len = <10>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hsync-len = <60>; - hfront-porch = <50>; - vback-porch = <5>; - vsync-len = <13>; - vfront-porch = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing0>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hsync-len = <60>; - hfront-porch = <40>; - vback-porch = <21>; - vsync-len = <10>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi deleted file mode 100644 index a439a47fb65a..000000000000 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright 2012-2017 - * based on imx53-qsb.dts - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx53.dtsi" -#include - -/ { - model = "Ka-Ro electronics TX53 module"; - compatible = "karo,tx53", "fsl,imx53"; - - /* Will be filled by the bootloader */ - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0>; - }; - - aliases { - can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ - can1 = &can1; - ipu = &ipu; - reg-can-xcvr = ®_can_xcvr; - usbh1 = &usbh1; - usbotg = &usbotg; - }; - - clocks { - ckih1 { - clock-frequency = <0>; - }; - }; - - mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_key>; - - key-power { - label = "Power Button"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,code = <116>; /* KEY_POWER */ - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stk5led>; - - led-user { - label = "Heartbeat"; - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "tx53-audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - /* '1' based port numbers according to datasheet names */ - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - cs-gpios = < - &gpio2 30 GPIO_ACTIVE_HIGH - &gpio3 19 GPIO_ACTIVE_HIGH - >; - -}; - -&esdhc1 { - cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&esdhc2 { - cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - phy-handle = <&phy0>; - mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - device_type = "ethernet-phy"; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-0 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - clock-frequency = <400000>; - status = "okay"; - - rtc1: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ds1339>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - trickle-resistor-ohms = <250>; - trickle-diode-disable; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-tx53 { - pinctrl_hog: hoggrp { - /* pins not in use by any device on the Starterkit board series */ - fsl,pins = < - /* CMOS Sensor Interface */ - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 - MX53_PAD_GPIO_0__GPIO1_0 0x1f4 - /* Module Specific Signal */ - /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ - /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ - MX53_PAD_EIM_D29__GPIO3_29 0x1f4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 - /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ - /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ - MX53_PAD_EIM_A19__GPIO2_19 0x1f4 - MX53_PAD_EIM_A20__GPIO2_18 0x1f4 - MX53_PAD_EIM_A21__GPIO2_17 0x1f4 - MX53_PAD_EIM_A22__GPIO2_16 0x1f4 - MX53_PAD_EIM_A23__GPIO6_6 0x1f4 - MX53_PAD_EIM_A24__GPIO5_4 0x1f4 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 - /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ - /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ - MX53_PAD_GPIO_13__GPIO4_3 0x1f4 - MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 - MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 - MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 - MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 - MX53_PAD_EIM_OE__GPIO2_25 0x1f4 - MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 - MX53_PAD_EIM_RW__GPIO2_26 0x1f4 - MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 - MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 - MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 - MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 - MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 - MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 - MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 - MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = ; /* Flexcan XCVR enable */ - }; - - pinctrl_ds1339: ds1339grp { - fsl,pins = ; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 - MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_EIM_D24__GPIO3_24 0x1f0 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - MX53_PAD_EIM_D25__GPIO3_25 0x1f0 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_gpio_key: gpio-keygrp { - fsl,pins = ; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 - MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 - MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 - >; - }; - - pinctrl_i2c3_gpio: i2c3-gpiogrp { - fsl,pins = < - MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 - MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_ssi2: ssi2grp { - fsl,pins = < - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 - MX53_PAD_EIM_D27__GPIO3_27 0x1f0 - >; - }; - - pinctrl_stk5led: stk5ledgrp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ - MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ - >; - }; - }; -}; - -&ipu { - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; -}; - -&sdma { - fsl,sdma-ram-script-name = "sdma-imx53.bin"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - phy_type = "utmi"; - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "peripheral"; - disable-over-current; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts deleted file mode 100644 index acc44010d510..000000000000 --- a/arch/arm/boot/dts/imx53-usbarmory.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * USB armory MkI device tree file - * https://inversepath.com/usbarmory - * - * Copyright (C) 2015, Inverse Path - * Andrej Rosano - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Inverse Path USB armory"; - compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; -}; - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-user { - label = "LED"; - gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* - * Not every i.MX53 P/N supports clock > 800MHz. - * As USB armory does not mount a specific P/N set a safe clock upper limit. - */ -&cpu0 { - operating-points = < - /* kHz */ - 166666 850000 - 400000 900000 - 800000 1050000 - >; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&iomuxc { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_i2c1_pmic: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x80 - MX53_PAD_EIM_D28__I2C1_SDA 0x80 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 - >; - }; - - /* - * UART mode pin header configuration - * 3 - GPIO5[26], pull-down 100K - * 4 - GPIO5[27], pull-down 100K - * 5 - TX, pull-up 100K - * 6 - RX, pull-up 100K - * 7 - GPIO5[30], pull-down 100K - */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 - MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 - >; - }; -}; - -&i2c1 { - pinctrl-0 = <&pinctrl_i2c1_pmic>; - status = "okay"; - - ltc3589: pmic@34 { - compatible = "lltc,ltc3589-2"; - reg = <0x34>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <591930>; - regulator-max-microvolt = <1224671>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456803>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1341250>; - regulator-max-microvolt = <2775000>; - lltc,fb-voltage-divider = <270000 100000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - bb_out_reg: bb-out { - regulator-min-microvolt = <3387341>; - regulator-max-microvolt = <3387341>; - lltc,fb-voltage-divider = <511000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1306329>; - regulator-max-microvolt = <1306329>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456806>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3200000>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts deleted file mode 100644 index ae53d178a683..000000000000 --- a/arch/arm/boot/dts/imx53-voipac-bsb.dts +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. - */ - -/dts-v1/; -#include "imx53-voipac-dmm-668.dtsi" - -/ { - sound { - compatible = "fsl,imx53-voipac-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-voipac-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio>; - - led1 { - label = "led-red"; - gpios = <&gpio3 29 0>; - default-state = "off"; - }; - - led2 { - label = "led-orange"; - gpios = <&gpio2 31 0>; - default-state = "off"; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-voipac { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SD2_CD */ - MX53_PAD_EIM_D25__GPIO3_25 0x80000000 - /* SD2_WP */ - MX53_PAD_EIM_A19__GPIO2_19 0x80000000 - >; - }; - - led_pin_gpio: led_gpio { - fsl,pins = < - MX53_PAD_EIM_D29__GPIO3_29 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - >; - }; - - /* Keyboard controller */ - pinctrl_kpp_1: kppgrp-1 { - fsl,pins = < - MX53_PAD_GPIO_9__KPP_COL_6 0xe8 - MX53_PAD_GPIO_4__KPP_COL_7 0xe8 - MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 - MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 - MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 - MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 - MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 - MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - >; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&clks 150>; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = < - 0x0203003b /* KEY_F1 */ - 0x0603003c /* KEY_F2 */ - 0x0207003d /* KEY_F3 */ - 0x0607003e /* KEY_F4 */ - >; - keypad,num-rows = <8>; - keypad,num-columns = <1>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi deleted file mode 100644 index 24859d0c09c1..000000000000 --- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. - */ - -#include "imx53.dtsi" - -/ { - model = "Voipac i.MX53 X53-DMM-668"; - compatible = "voipac,imx53-dmm-668", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 0>; /* PEN */ - enable-active-high; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-voipac { - pinctrl_hog: hoggrp { - fsl,pins = < - /* Make DA9053 regulator functional */ - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - /* FEC Power enable */ - MX53_PAD_GPIO_11__GPIO4_1 0x80000000 - /* FEC RST */ - MX53_PAD_GPIO_12__GPIO4_2 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, - <&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: dialog@48 { - compatible = "dlg,da9053-aa", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ - - regulators { - buck1_reg: buck1 { - regulator-name = "BUCKCORE"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-name = "BUCKPRO"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-name = "BUCKMEM"; - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1580000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-name = "BUCKPERI"; - regulator-min-microvolt = <2370000>; - regulator-max-microvolt = <2630000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "ldo1_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "ldo3_3v3"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-name = "ldo4_2v775"; - regulator-min-microvolt = <2770000>; - regulator-max-microvolt = <2780000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "ldo5_3v3"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "ldo6_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-name = "ldo7_2v75"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "ldo8_1v8"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1850000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-name = "ldo9_1v5"; - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-name = "ldo10_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi deleted file mode 100644 index 17dc13719639..000000000000 --- a/arch/arm/boot/dts/imx53.dtsi +++ /dev/null @@ -1,859 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx53-pinfunc.h" -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - ipu0 = &ipu; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&clks IMX5_CLK_ARM>; - clock-latency = <61036>; - voltage-tolerance = <5>; - operating-points = < - /* kHz */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - 1200000 1300000 - >; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>, <&ipu_di1>; - }; - - capture_subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu_csi0>, <&ipu_csi1>; - }; - - tzic: tz-interrupt-controller@fffc000 { - compatible = "fsl,imx53-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x0fffc000 0x4000>; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - }; - - ckih2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&tzic>; - interrupts = <77>; - }; - - usbphy0: usbphy-0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - status = "okay"; - }; - - usbphy1: usbphy-1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - status = "okay"; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - sata: sata@10000000 { - compatible = "fsl,imx53-ahci"; - reg = <0x10000000 0x1000>; - interrupts = <28>; - clocks = <&clks IMX5_CLK_SATA_GATE>, - <&clks IMX5_CLK_SATA_REF>, - <&clks IMX5_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; - status = "disabled"; - }; - - ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x08000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu_csi0: port@0 { - reg = <0>; - - ipu_csi0_from_parallel_sensor: endpoint { - }; - }; - - ipu_csi1: port@1 { - reg = <1>; - - ipu_csi1_from_parallel_sensor: endpoint { - }; - }; - - ipu_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu_di0_lvds0: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds0_in>; - }; - }; - - ipu_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu_di1_lvds1: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds1_in>; - }; - - ipu_di1_tve: endpoint@2 { - reg = <2>; - remote-endpoint = <&tve_in>; - }; - }; - }; - - gpu: gpu@30000000 { - compatible = "amd,imageon-200.0", "amd,imageon"; - reg = <0x30000000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <12>; - interrupt-names = "kgsl_3d0_irq"; - clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; - clock-names = "core_clk", "mem_iface_clk"; - }; - - aips1: bus@50000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x10000000>; - ranges; - - spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - esdhc1: mmc@50004000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc2: mmc@50008000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi1: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; - reg = <0x50010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, - <&clks IMX5_CLK_SSI2_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: mmc@50020000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: mmc@50024000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - aipstz1: bridge@53f00000 { - compatible = "fsl,imx53-aipstz"; - reg = <0x53f00000 0x60>; - }; - - usbotg: usb@53f80000 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@53f80200 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@53f80400 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53f80800 { - #index-cells = <1>; - compatible = "fsl,imx53-usbmisc"; - reg = <0x53f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - - gpio1: gpio@53f84000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53f88000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@53f8c000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@53f90000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@53f94000 { - compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; - reg = <0x53f94000 0x4000>; - interrupts = <60>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: watchdog@53f98000 { - compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; - reg = <0x53f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - wdog2: watchdog@53f9c000 { - compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; - reg = <0x53f9c000 0x4000>; - interrupts = <59>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - gpt: timer@53fa0000 { - compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; - reg = <0x53fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - srtc: rtc@53fa4000 { - compatible = "fsl,imx53-rtc"; - reg = <0x53fa4000 0x4000>; - interrupts = <24>; - clocks = <&clks IMX5_CLK_SRTC_GATE>; - }; - - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx53-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - - ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - reg = <0x53fa8008 0x4>; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@1 { - reg = <1>; - - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - }; - - pwm1: pwm@53fb4000 { - #pwm-cells = <3>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@53fb8000 { - #pwm-cells = <3>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@53fbc000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@53fc0000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, - <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: can@53fcc000 { - compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fcc000 0x4000>; - interrupts = <83>; - clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, - <&clks IMX5_CLK_CAN2_SERIAL_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: reset-controller@53fd0000 { - compatible = "fsl,imx53-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - interrupts = <75>; - #reset-cells = <1>; - }; - - clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - - gpio5: gpio@53fdc000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fdc000 0x4000>; - interrupts = <103 104>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@53fe0000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fe0000 0x4000>; - interrupts = <105 106>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@53fe4000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fe4000 0x4000>; - interrupts = <107 108>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c3: i2c@53fec000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x53fec000 0x4000>; - interrupts = <64>; - clocks = <&clks IMX5_CLK_I2C3_GATE>; - status = "disabled"; - }; - - uart4: serial@53ff0000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53ff0000 0x4000>; - interrupts = <13>; - clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - aips2: bus@60000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000000 0x10000000>; - ranges; - - aipstz2: bridge@63f00000 { - compatible = "fsl,imx53-aipstz"; - reg = <0x63f00000 0x60>; - }; - - iim: efuse@63f98000 { - compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon"; - reg = <0x63f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; - - uart5: serial@63f90000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x63f90000 0x4000>; - interrupts = <86>; - clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tigerp: tigerp@63fa0000 { - compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; - reg = <0x63fa0000 0x28>; - }; - - owire: owire@63fa4000 { - compatible = "fsl,imx53-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: spi@63fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; - reg = <0x63fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: dma-controller@63fb0000 { - compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; - reg = <0x63fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - - cspi: spi@63fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; - reg = <0x63fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@63fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x63fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@63fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x63fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@63fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, - <&clks IMX5_CLK_SSI1_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@63fd0000 { - compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; - reg = <0x63fd0000 0x4000>; - status = "disabled"; - }; - - nfc: nand@63fdb000 { - compatible = "fsl,imx53-nand"; - reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; - interrupts = <8>; - clocks = <&clks IMX5_CLK_NFC_GATE>; - status = "disabled"; - }; - - ssi3: ssi@63fe8000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fe8000 0x4000>; - interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, - <&clks IMX5_CLK_SSI3_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 46 0 0>, - <&sdma 47 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - tve: tve@63ff0000 { - compatible = "fsl,imx53-tve"; - reg = <0x63ff0000 0x1000>; - interrupts = <92>; - clocks = <&clks IMX5_CLK_TVE_GATE>, - <&clks IMX5_CLK_IPU_DI1_SEL>; - clock-names = "tve", "di_sel"; - status = "disabled"; - - port { - tve_in: endpoint { - remote-endpoint = <&ipu_di1_tve>; - }; - }; - }; - - vpu: vpu@63ff4000 { - compatible = "fsl,imx53-vpu", "cnm,coda7541"; - reg = <0x63ff4000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; - clock-names = "per", "ahb"; - resets = <&src 1>; - iram = <&ocram>; - }; - - sahara: crypto@63ff8000 { - compatible = "fsl,imx53-sahara"; - reg = <0x63ff8000 0x4000>; - interrupts = <19 20>; - clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; - clock-names = "ipg", "ahb"; - }; - }; - - ocram: sram@f8000000 { - compatible = "mmio-sram"; - reg = <0xf8000000 0x20000>; - ranges = <0 0xf8000000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX5_CLK_OCRAM>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi deleted file mode 100644 index d477a937b47a..000000000000 --- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +++ /dev/null @@ -1,561 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2019 Logic PD, Inc. - -/ { - keyboard { - compatible = "gpio-keys"; - - button-0 { - gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; - label = "btn0"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - button-1 { - gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; - label = "btn1"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - button-2 { - gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; - label = "btn2"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - button-3 { - gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; - label = "btn3"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - }; - - leds { - compatible = "gpio-leds"; - - gen-led0 { - label = "led0"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led0>; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - }; - - gen-led1 { - label = "led1"; - gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; - }; - - gen-led2 { - label = "led2"; - gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - gen-led3 { - label = "led3"; - gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - reg_usb_otg_vbus: regulator-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_3v3: regulator-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_3v3>; - compatible = "regulator-fixed"; - regulator-name = "reg_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - }; - - reg_enet: regulator-ethernet { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_enet>; - compatible = "regulator-fixed"; - regulator-name = "ethernet-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&sw4_reg>; - }; - - reg_audio: regulator-audio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_audio>; - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3>; - }; - - reg_hdmi: regulator-hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_hdmi>; - compatible = "regulator-fixed"; - regulator-name = "hdmi-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3>; - }; - - reg_uart3: regulator-uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_uart3>; - compatible = "regulator-fixed"; - regulator-name = "uart3-supply"; - gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_3v3>; - }; - - reg_1v8: regulator-1v8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_1v8>; - compatible = "regulator-fixed"; - regulator-name = "1v8-supply"; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_3v3>; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_pcie>; - regulator-name = "mpcie_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_mipi: regulator-mipi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_mipi>; - regulator-name = "mipi_pwr_en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - phy-supply = <®_enet>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; -}; - -&i2c3 { - ov5640: camera@10 { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x10>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <®_mipi>; - AVDD-supply = <®_mipi>; - DVDD-supply = <®_mipi>; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - pcf8575: gpio@20 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcf8574>; - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - lines-initial-states = <0x0710>; - wakeup-source; - }; -}; - -&ipu1_csi1_from_mipi_vc1 { - clock-lanes = <0>; - data-lanes = <1 2>; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - vmmc-supply = <®_3v3>; - no-1-8-v; - keep-power-in-suspend; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_led0: led0grp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 - >; - }; - - pinctrl_pcf8574: pcf8575grp { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_1v8: reg1v8grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 - >; - }; - - pinctrl_reg_3v3: reg3v3grp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 - >; - }; - - pinctrl_reg_audio: reg-audiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_reg_enet: reg-enetgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - >; - }; - - pinctrl_reg_hdmi: reg-hdmigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - >; - }; - - pinctrl_reg_mipi: reg-mipigrp { - fsl,pins = ; - }; - - pinctrl_reg_pcie: reg-pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_reg_uart3: reguart3grp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - >; - }; - - pinctrl_reg_usb_h1_vbus: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_reg_usb_otg: reg-usb-otggrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 - >; - }; - - pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - -}; diff --git a/arch/arm/boot/dts/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/imx6-logicpd-som.dtsi deleted file mode 100644 index 547fb141ec0c..000000000000 --- a/arch/arm/boot/dts/imx6-logicpd-som.dtsi +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2019 Logic PD, Inc. - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1837"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vddcore"; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vddsoc"; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "gen_3v3"; - regulator-boot-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-name = "sw3a_vddr"; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-name = "sw3b_vddr"; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "gen_rgmii"; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-name = "gen_5v0"; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "gen_vsns"; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "gen_1v5"; - }; - - vgen2_reg: vgen2 { - regulator-name = "vgen2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-name = "gen_vadj_0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-name = "gen_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-name = "gen_vadj_1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-name = "gen_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - coin_reg: coin { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@49 { - compatible = "ti,tmp102"; - reg = <0x49>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - temperature-sensor@4a { - compatible = "ti,tmp102"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x51>; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -/* Reroute power feeding the CPU to come from the external PMIC */ -®_arm -{ - vin-supply = <&sw1a_reg>; -}; - -®_soc -{ - vin-supply = <&sw1c_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_gpmi_nand: gpmi-nandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < /* Enable ARM Debugger */ - MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ - >; - }; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_wl18xx_vmmc>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts deleted file mode 100644 index 4989e8d069a1..000000000000 --- a/arch/arm/boot/dts/imx6dl-alti6p.dts +++ /dev/null @@ -1,578 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include -#include -#include -#include "imx6dl.dtsi" - -/ { - model = "Altesco I6P Board"; - compatible = "alt,alti6p", "fsl,imx6dl"; - - chosen { - stdout-path = &uart4; - }; - - clock_ksz8081: clock-ksz8081 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - i2c2-mux { - compatible = "i2c-mux"; - i2c-parent = <&i2c2>; - mux-controls = <&i2c_mux>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c4-mux { - compatible = "i2c-mux"; - i2c-parent = <&i2c4>; - mux-controls = <&i2c_mux>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-debug0 { - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-debug1 { - function = LED_FUNCTION_SD; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - }; - - i2c_mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2cmux>; - - mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>, - <&gpio5 11 GPIO_ACTIVE_HIGH>; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - bitclock-master; - frame-master; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_5v0>; - status = "okay"; -}; - -&clks { - clocks = <&clock_ksz8081>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clock_ksz8081>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "SD1_CD", "", "USB_H1_OC", "", "", "", "", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "I2C_EN13", "I2C_EN24", "", "", "", "", - "", "", "", "", "", "AUDIO_RESET", "", "", - "", "", "", "", "", "", "", ""; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c1>; - status = "okay"; -}; - -/* DDC */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c2 { - clock-frequency = <50000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - /* external interface, device are configured from user space */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - }; -}; - -&i2c4 { - clock-frequency = <50000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - /* NOTE: DDC is done via I2C2, so DON'T configure DDC - * pins for HDMI! - */ - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 - MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2cmux: i2cmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058 - - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/imx6dl-apf6dev.dts deleted file mode 100644 index 3dcce3454b08..000000000000 --- a/arch/arm/boot/dts/imx6dl-apf6dev.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-apf6.dtsi" -#include "imx6qdl-apf6dev.dtsi" - -/ { - model = "Armadeus APF6 Solo Module on APF6Dev Board"; - compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts deleted file mode 100644 index dfa6f64d43cc..000000000000 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ /dev/null @@ -1,158 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts deleted file mode 100644 index 5e15212eaf3a..000000000000 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - panel: panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts deleted file mode 100644 index cc861a43eb58..000000000000 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos.dtsi" - -/ { - model = "aristainetos i.MX6 Dual Lite Board 4"; - compatible = "abb,aristainetos-imx6dl-4", "fsl,imx6dl"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - status = "okay"; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 480x800p60 { - native-mode; - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <59>; - hback-porch = <10>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm1 { - #pwm-cells = <2>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts deleted file mode 100644 index b6cb78870cd5..000000000000 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos.dtsi" - -/ { - model = "aristainetos i.MX6 Dual Lite Board 7"; - compatible = "abb,aristainetos-imx6dl-7", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <33246000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <88>; - hback-porch = <88>; - hsync-len = <80>; - vback-porch = <10>; - vfront-porch = <10>; - vsync-len = <25>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 3000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm3 { - #pwm-cells = <2>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts deleted file mode 100644 index 411aa72d344b..000000000000 --- a/arch/arm/boot/dts/imx6dl-b105pv2.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B105Pv2 -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -/dts-v1/; -#include "imx6dl-b1x5pv2.dtsi" - -/ { - model = "General Electric B105Pv2"; - compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl"; - - panel { - compatible = "auo,g101evn010"; - }; -}; - -&i2c3 { - touchscreen@41 { - compatible = "ilitek,ili251x"; - reg = <0x41>; - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_q7_gpio0>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1280>; - touchscreen-size-y = <800>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts deleted file mode 100644 index d011127c635b..000000000000 --- a/arch/arm/boot/dts/imx6dl-b105v2.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B105v2 -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -/dts-v1/; -#include "imx6dl-b1x5v2.dtsi" - -/ { - model = "General Electric B105v2"; - compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl"; - - panel { - compatible = "auo,g101evn010"; - }; -}; - -&i2c3 { - touchscreen@41 { - compatible = "ilitek,ili251x"; - reg = <0x41>; - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_q7_gpio0>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1280>; - touchscreen-size-y = <800>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts deleted file mode 100644 index ca840fa84052..000000000000 --- a/arch/arm/boot/dts/imx6dl-b125pv2.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B125Pv2 -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -/dts-v1/; -#include "imx6dl-b1x5pv2.dtsi" - -/ { - model = "General Electric B125Pv2"; - compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl"; - - panel { - compatible = "auo,g121ean01"; - }; -}; - -&i2c3 { - touchscreen@2a { - compatible = "eeti,exc80h60"; - reg = <0x2a>; - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_q7_gpio0>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts deleted file mode 100644 index 81e5a9cb8900..000000000000 --- a/arch/arm/boot/dts/imx6dl-b125v2.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B125v2 -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -/dts-v1/; -#include "imx6dl-b1x5v2.dtsi" - -/ { - model = "General Electric B125v2"; - compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl"; - - panel { - compatible = "auo,g121ean01"; - }; -}; - -&i2c3 { - touchscreen@2a { - compatible = "eeti,exc80h60"; - reg = <0x2a>; - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_q7_gpio0>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts deleted file mode 100644 index c861937b30f6..000000000000 --- a/arch/arm/boot/dts/imx6dl-b155v2.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B155v2 -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -/dts-v1/; -#include "imx6dl-b1x5v2.dtsi" - -/ { - model = "General Electric B155v2"; - compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl"; - - panel { - compatible = "auo,g156xtn01"; - }; -}; - -&i2c3 { - touchscreen@2a { - compatible = "eeti,exc80h84"; - reg = <0x2a>; - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_q7_gpio0>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - touchscreen-inverted-x; - touchscreen-inverted-y; - reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi deleted file mode 100644 index 37697fac9dea..000000000000 --- a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B1x5Pv2 -// patient monitor series -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -#include -#include "imx6dl-qmx6.dtsi" - -/ { - chosen { - stdout-path = &uart3; - }; - - /* Do not allow frequencies above 800MHz */ - cpus { - cpu@0 { - operating-points = < - /* kHz uV */ - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 792000 1175000 - 396000 1175000 - >; - }; - - cpu@1 { - operating-points = < - /* kHz uV */ - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 792000 1175000 - 396000 1175000 - >; - }; - }; - - reg_syspwr: regulator-12v { - compatible = "regulator-fixed"; - regulator-name = "SYS_PWR"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - reg_5v_pmc: regulator-5v-pmc { - compatible = "regulator-fixed"; - regulator-name = "5V PMC"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_syspwr>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_syspwr>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_syspwr>; - }; - - reg_5v0_audio: regulator-5v0-audio { - compatible = "regulator-fixed"; - regulator-name = "5V0_AUDIO"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v>; - gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * This must be always-on for da7212, which has some not - * properly documented dependencies for it's speaker supply - * pin. The issue manifests as speaker volume being very low. - */ - regulator-always-on; - }; - - - reg_3v3_audio: regulator-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "3V3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_3v3>; - pinctrl-0 = <&pinctrl_q7_hda_reset>; - pinctrl-names = "default"; - gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5_audio: regulator-2v5-audio { - compatible = "regulator-fixed"; - regulator-name = "2V5_AUDIO"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - vin-supply = <®_3v3_audio>; - - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "WLAN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_sdio_power>; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <70000>; - }; - - reg_bl: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "LED_VCC"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_syspwr>; - pinctrl-0 = <&pinctrl_q7_lcd_power>; - pinctrl-names = "default"; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "LCD_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v>; - }; - - usb_power: regulator-usb-power { - compatible = "regulator-fixed"; - regulator-name = "USB POWER"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v>; - }; - - charger: battery-charger { - compatible = "gpio-charger"; /* ti,bq24172 */ - charger-type = "mains"; - gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>; - charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>, - <&tca6424a 12 GPIO_ACTIVE_HIGH>; - charge-current-limit-mapping = <1300000 0x0>, - <700000 0x1>, - <0 0x2>; - charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>; - }; - - poweroff { - compatible = "gpio-poweroff"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_spi_cs1>; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - }; - - power-button-key { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_sleep_button>; - - power-button { - label = "power button"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - rotary-encoder-key { - compatible = "gpio-keys"; - - rotary-encoder-event { - label = "rotary-encoder press"; - gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,can-disable; - }; - }; - - rotary-encoder { - compatible = "rotary-encoder"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>; - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>; - rotary-encoder,relative-axis; - rotary-encoder,steps-per-period = <2>; - wakeup-source; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; - - led-alarm1 { - label = "alarm:red"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - led-alarm2 { - label = "alarm:yellow"; - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; - }; - - led-alarm3 { - label = "alarm:blue"; - gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_backlight_enable>; - power-supply = <®_bl>; - pwms = <&pwm4 0 5000000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <179>; - enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - panel { - backlight = <&backlight>; - power-supply = <®_lcd>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = "Speaker", "Ext Spk"; - simple-audio-card,audio-routing = "Ext Spk", "LINE"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; -}; - -&audmux { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - battery: battery@b { - compatible = "ti,bq20z65", "sbs,sbs-battery"; - reg = <0x0b>; - sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>; - sbs,i2c-retry-count = <5>; - power-supplies = <&charger>; - }; - - codec: audio-codec@1a { - compatible = "dlg,da7212"; - reg = <0x1a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5_audio>; - VDDSP-supply = <®_5v0_audio>; - VDDMIC-supply = <®_3v3_audio>; - VDDIO-supply = <®_3v3_audio>; - clocks = <&clk_ext_audio_codec>; - clock-names = "mclk"; - }; -}; - -&i2c5 { - tca6424a: gpio-controller@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <®_3v3>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_gpio6>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN", - "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF", - "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0", - "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "", - "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", - "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2"; - - }; - - tmp75: temperature-sensor@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - vs-supply = <®_3v3>; - interrupt-parent = <&tca6424a>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm4 { - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <&usb_power>; - disable-over-current; - dr_mode = "host"; - status = "okay"; - - /* - * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N. - * On QMX6 this is not connceted to the i.MX6, but to the USB Hub - * from &usbh1. This means, that we cannot easily detect and handle - * over-current events. Fortunately the regulator limits the current - * automatically, so the hardware is still protected. - */ -}; - -&usdhc4 { - /* WiFi module */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - no-1-8-v; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - max-frequency = <25000000>; - vmmc-supply = <®_wlan>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_q7_gpio7>; - - interrupt-parent = <&gpio4>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi deleted file mode 100644 index f028b6a191df..000000000000 --- a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for General Electric B1x5v2 -// patient monitor series -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora - -#include -#include "imx6dl-b1x5pv2.dtsi" - -/ { - reg_3v3_acm: regulator-3v3-acm { - compatible = "regulator-fixed"; - regulator-name = "3V3 ACM"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_3v3>; - }; -}; - -&i2c1 { - tca6416: gpio-controller@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>; - vcc-supply = <®_3v3_acm>; - gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2", - "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1", - "ACM2_CL2", "", "", "", - "", "", "", ""; - - /* - * The interrupt pin is connected to &tca6424a pin 1, but the Linux - * TCA6424 driver cannot handle low type interrupts at the moment - * (and support cannot be added without some ugly hacks). Since this - * controller does not have any input type GPIOs, just pretend - * that the interrupt pin is unconnected. - */ - }; -}; - -&i2c5 { - mpl3115a2: pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - - /* - * The MPL3115 interrupts are connected to pin 22 and 23 - * of &tca6424a, but the binding does not yet support - * interrupts. - */ - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts deleted file mode 100644 index 82a0d1a28d12..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-aster.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include -#include -#include "imx6dl.dtsi" -#include "imx6qdl-colibri.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; - compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", - "fsl,imx6dl"; - - aliases { - i2c0 = &i2c2; - i2c1 = &i2c3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* Colibri SSP */ -&ecspi4 { - cs-gpios = < - &gpio5 2 GPIO_ACTIVE_HIGH - &gpio5 4 GPIO_ACTIVE_HIGH - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; - status = "okay"; -}; - -/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ -&i2c3 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_csi_gpio_1 - &pinctrl_gpio_2 - &pinctrl_gpio_aster - &pinctrl_usbh_oc_1 - &pinctrl_usbc_id_1 - &pinctrl_weim_gpio_5 - >; - - pinctrl_gpio_aster: gpioaster { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - >; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbotg { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts deleted file mode 100644 index f50a26dd34c0..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include "imx6dl.dtsi" -#include "imx6qdl-colibri.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", - "fsl,imx6dl"; - - aliases { - i2c0 = &i2c2; - i2c1 = &i2c3; - }; - - aliases { - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* Fixed crystal dedicated to mcp251x */ - clk16m: clock-16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; -}; - -/* Colibri SSP */ -&ecspi4 { - status = "okay"; - - mcp251x0: mcp251x@0 { - compatible = "microchip,mcp2515"; - clocks = <&clk16m>; - interrupt-parent = <&gpio3>; - interrupts = <27 0x2>; - reg = <0>; - spi-max-frequency = <10000000>; - status = "okay"; - }; -}; - -/* - * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) - */ -&i2c3 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 - &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 - &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 - &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 - >; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbotg { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; -}; - -&weim { - status = "okay"; - - /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ - ranges = <0 0 0x08000000 0x02000000 - 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000 - 3 0 0x0e000000 0x02000000>; - - /* SRAM on Colibri nEXT_CS0 */ - sram@0,0 { - compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; - reg = <0 0 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 - 0x00000000 0x04000040 0x00000000>; - }; - - /* SRAM on Colibri nEXT_CS1 */ - sram@1,0 { - compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; - reg = <1 0 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 - 0x00000000 0x04000040 0x00000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts deleted file mode 100644 index 3a6d3889760d..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx6dl-colibri-iris.dts" - -/ { - model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; - compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl", - "fsl,imx6dl"; - - reg_3v3_vmmc: regulator-3v3-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; - regulator-name = "3v3_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>; - - pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - >; - }; -}; - -/* Colibri MMC */ -&usdhc1 { - cap-power-off-card; - /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */ - /* /delete-property/ no-1-8-v; */ - vmmc-supply = <®_3v3_vmmc>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts deleted file mode 100644 index 4303c88bb2a9..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-iris.dts +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include -#include -#include "imx6dl.dtsi" -#include "imx6qdl-colibri.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; - compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl", - "fsl,imx6dl"; - - aliases { - i2c0 = &i2c2; - i2c1 = &i2c3; - }; - - aliases { - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* Colibri SSP */ -&ecspi4 { - status = "okay"; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>; - - /* - * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one - * wants to turn the transceiver off, that property has to be deleted - * and the gpio handled in userspace. - * The same applies to uart-b-c-on-x14-enable where the UART_B and - * UART_C transceiver is turned on. - */ - uart-a-on-x13-enable-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ - output-high; - }; - - uart-b-c-on-x14-enable-hog { - gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ - output-high; - }; -}; - -/* - * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) - */ -&i2c3 { - status = "okay"; - - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_gpio_iris - &pinctrl_usbh_oc_1 - &pinctrl_usbc_id_1 - >; - - pinctrl_gpio_iris: gpioirisgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - >; - }; - - pinctrl_uart1_forceoff: uart1forceoffgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - >; - }; - - pinctrl_uart23_forceoff: uart23forceoffgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - >; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbotg { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts deleted file mode 100644 index 2b2fc360b865..000000000000 --- a/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts b/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts deleted file mode 100644 index e09c565d1d1f..000000000000 --- a/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite (1.5som)"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts deleted file mode 100644 index 2b1b3e193f53..000000000000 --- a/arch/arm/boot/dts/imx6dl-cubox-i.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts deleted file mode 100644 index cece4aafdad8..000000000000 --- a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer - */ - -#ifndef __DTS_V1__ -#define __DTS_V1__ -/dts-v1/; -#endif - -#include "imx6dl.dtsi" -#include "imx6qdl-dfi-fs700-m60.dtsi" - -/ { - model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; - compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts deleted file mode 100644 index 038bb0025556..000000000000 --- a/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2021 DH electronics GmbH - * - * DHCOM iMX6 variant: - * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 - * DHCOM PCB number: 493-300 or newer - * PicoITX PCB number: 487-600 or newer - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-dhcom-som.dtsi" -#include "imx6qdl-dhcom-picoitx.dtsi" - -/ { - model = "DH electronics i.MX6DL DHCOM on PicoITX"; - compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som", - "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts deleted file mode 100644 index 33825b5a8f26..000000000000 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 Eckelmann AG. - * Copyright (C) 2013 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include - -#include "imx6dl.dtsi" - -/ { - model = "Eckelmann CI 4X10 Board"; - compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; - - chosen { - stdout-path = &uart3; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - rmii_clk: clock-rmii { - /* This clock is provided by the phy (KSZ8091RNB) */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - siox { - compatible = "eckelmann,siox-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_siox>; - din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - clocks = <&rmii_clk>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&rmii_clk>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "everspin,mr25h256"; - reg = <0>; - spi-max-frequency = <15000000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&gpio2 { - gpio-line-names = "buzzer", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", "", "", "", "in2", - "prio2", "prio1", "aux", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio6 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "in1", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - temperature-sensor@49 { - compatible = "ad,ad7414"; - reg = <0x49>; - }; - - rtc@51 { - compatible = "nxp,pcf2127"; - reg = <0x51>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hog { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ - - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 - MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 - MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 - MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - /* without SION i2c doesn't detect bus busy */ - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 - >; - }; - - pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 - >; - }; - - pinctrl_siox: sioxgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ - >; - }; - - pinctrl_uart1_dte: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ - >; - }; - - pinctrl_uart2_dte: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 - MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 - MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ - >; - }; - - pinctrl_uart3_dce: uart3grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 - >; - }; - - pinctrl_uart4_dce: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 - >; - }; - - pinctrl_uart5_dce: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 - >; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte>; - uart-has-rtscts; - fsl,dte-mode; - dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - uart-has-rtscts; - fsl,dte-mode; - dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_dce>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_dce>; - rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5_dce>; - rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts deleted file mode 100644 index 407ad8d43c84..000000000000 --- a/arch/arm/boot/dts/imx6dl-emcon-avari.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-emcon.dtsi" -#include "imx6qdl-emcon-avari.dtsi" - -/ { - model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; - compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/imx6dl-gw51xx.dts deleted file mode 100644 index 9956d12a1245..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw51xx.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw51xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; - compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts deleted file mode 100644 index 9ea23dd54f3c..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw52xx.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw52xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; - compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; -}; - -&ipu1_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; -}; - -&ipu1_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi1: ipu1_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts deleted file mode 100644 index 182e8194c249..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw53xx.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw53xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; - compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; -}; - -&ipu1_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; -}; - -&ipu1_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi1: ipu1_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts deleted file mode 100644 index a106c4e3e329..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw54xx.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw54xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; - compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; -}; - -&ipu1_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; -}; - -&ipu1_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi1: ipu1_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw551x.dts b/arch/arm/boot/dts/imx6dl-gw551x.dts deleted file mode 100644 index 82d5f85722ea..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw551x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw551x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; - compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts deleted file mode 100644 index 4864a36f9b36..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw552x.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw552x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; - compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw553x.dts b/arch/arm/boot/dts/imx6dl-gw553x.dts deleted file mode 100644 index 59b8afc36e66..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw553x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw553x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; - compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw560x.dts b/arch/arm/boot/dts/imx6dl-gw560x.dts deleted file mode 100644 index 21bdfaf8df53..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw560x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw560x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X"; - compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw5903.dts b/arch/arm/boot/dts/imx6dl-gw5903.dts deleted file mode 100644 index 103261ea9334..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw5903.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw5903.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903"; - compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw5904.dts b/arch/arm/boot/dts/imx6dl-gw5904.dts deleted file mode 100644 index 9c6d3cd3d6a7..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw5904.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw5904.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904"; - compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw5907.dts b/arch/arm/boot/dts/imx6dl-gw5907.dts deleted file mode 100644 index 3fa2822beffc..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw5907.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw5907.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; - compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/imx6dl-gw5910.dts deleted file mode 100644 index 0d5e7e5da536..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw5910.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw5910.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; - compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/imx6dl-gw5912.dts deleted file mode 100644 index 5260e0142d63..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw5912.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw5912.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; - compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/imx6dl-gw5913.dts deleted file mode 100644 index b74e533c8e67..000000000000 --- a/arch/arm/boot/dts/imx6dl-gw5913.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw5913.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; - compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts deleted file mode 100644 index a63f742f20d9..000000000000 --- a/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts deleted file mode 100644 index 66a06cf3cdf3..000000000000 --- a/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite (1.5som)"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts deleted file mode 100644 index cbd02eb486e1..000000000000 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts deleted file mode 100644 index 80313c13bcdb..000000000000 --- a/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts b/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts deleted file mode 100644 index e61ef1156f8b..000000000000 --- a/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Solo/DualLite (1.5som)"; - compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/imx6dl-hummingboard2.dts deleted file mode 100644 index b12cd87f3f94..000000000000 --- a/arch/arm/boot/dts/imx6dl-hummingboard2.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard2.dtsi" -#include "imx6qdl-hummingboard2-emmc.dtsi" - -/ { - model = "SolidRun HummingBoard2 Solo/DualLite"; - compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts deleted file mode 100644 index d8f3821a0ffd..000000000000 --- a/arch/arm/boot/dts/imx6dl-icore-mipi.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2018 Engicam S.r.l. - * Copyright (C) 2018 Amarula Solutions B.V. - * Author: Jagan Teki - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-icore-1.5.dtsi" - -/ { - model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6dl"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts deleted file mode 100644 index 73d710d34b9d..000000000000 --- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-icore-rqs.dtsi" - -/ { - model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit"; - compatible = "engicam,imx6-icore-rqs", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts deleted file mode 100644 index 80fa60607ab1..000000000000 --- a/arch/arm/boot/dts/imx6dl-icore.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 DualLite/Solo Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6dl"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c1 { - max11801: touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi deleted file mode 100644 index a864fdbd5f16..000000000000 --- a/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2019 (C) Pengutronix, Marco Felsch - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-kontron-samx6i.dtsi" - -/ { - model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; - compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts deleted file mode 100644 index 7c62db91173b..000000000000 --- a/arch/arm/boot/dts/imx6dl-lanmcu.dts +++ /dev/null @@ -1,483 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2019 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include -#include -#include "imx6dl.dtsi" - -/ { - model = "Van der Laan LANMCU"; - compatible = "vdl,lanmcu", "fsl,imx6dl"; - - chosen { - stdout-path = &uart4; - }; - - clock_ksz8081: clock-ksz8081 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 1000>; - num-interpolated-steps = <20>; - default-brightness-level = <19>; - }; - - display { - compatible = "fsl,imx-parallel-display"; - pinctrl-0 = <&pinctrl_ipu1_disp>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel { - compatible = "edt,etm0700g0bdh6"; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; - }; - -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - clocks = <&clock_ksz8081>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clock_ksz8081>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "SD1_CD", "", "", "", "", "", "", - "DEBUG_0", "BL_PWM", "", "", "", "", "", "", - "", "", "", "", "", "", "", "ENET_LED_GREEN", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", - "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "ENET_RST", "ENET_INT", - "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; -}; - -&gpio6 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "WLAN_REG_ON", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio7 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "EMMC_RST", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts_edt>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; - - touchscreen-size-x = <1792>; - touchscreen-size-y = <1024>; - - touchscreen-fuzz-x = <0>; - touchscreen-fuzz-y = <0>; - - /* Touch screen calibration */ - threshold = <50>; - gain = <5>; - offset = <10>; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - linux,rs485-enabled-at-boot-time; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&usdhc2_wifi_pwrseq>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_disp: ipudisp1grp { - fsl,pins = < - /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 - >; - }; - - pinctrl_ts_edt: ts1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; - - pinctrl_wifi_npd: wifigrp { - fsl,pins = < - /* WL_REG_ON */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts deleted file mode 100644 index 028951955bde..000000000000 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ /dev/null @@ -1,496 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 BTicino - * Copyright (C) 2018 Amarula Solutions B.V. - */ - -/dts-v1/; - -#include -#include "imx6dl.dtsi" - -/ { - model = "BTicino i.MX6DL Mamoj board"; - compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ - brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; - default-brightness-level = <7>; - }; - - display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "rocktech,rk070er9427"; - backlight = <&backlight_lcd>; - power-supply = <®_lcd_lr>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_lcd_3v3: regulator-lcd-dvdd { - compatible = "regulator-fixed"; - regulator-name = "lcd-dvdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 1 0>; - enable-active-high; - startup-delay-us = <21000>; - }; - - reg_lcd_power: regulator-lcd-power { - compatible = "regulator-fixed"; - regulator-name = "lcd-enable"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 6 0>; - enable-active-high; - vin-supply = <®_lcd_3v3>; - }; - - reg_lcd_vgl: regulator-lcd-vgl { - compatible = "regulator-fixed"; - regulator-name = "lcd-vgl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - startup-delay-us = <6000>; - enable-active-high; - vin-supply = <®_lcd_power>; - }; - - reg_lcd_vgh: regulator-lcd-vgh { - compatible = "regulator-fixed"; - regulator-name = "lcd-vgh"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <6000>; - enable-active-high; - vin-supply = <®_lcd_avdd>; - }; - - reg_lcd_vcom: regulator-lcd-vcom { - compatible = "regulator-fixed"; - regulator-name = "lcd-vcom"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; - startup-delay-us = <11000>; - enable-active-high; - vin-supply = <®_lcd_vgh>; - }; - - reg_lcd_lr: regulator-lcd-lr { - compatible = "regulator-fixed"; - regulator-name = "lcd-lr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_lcd_vcom>; - }; - - reg_lcd_avdd: regulator-lcd-avdd { - compatible = "regulator-fixed"; - regulator-name = "lcd-avdd"; - regulator-min-microvolt = <10280000>; - regulator-max-microvolt = <10280000>; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - startup-delay-us = <6000>; - enable-active-high; - vin-supply = <®_lcd_vgl>; - }; - - reg_usb_host: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbhost-vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhost>; - regulator-min-microvolt = <50000000>; - regulator-max-microvolt = <50000000>; - gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wl18xx_vmmc: regulator-wl18xx-vmcc { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - /* CPU vdd_arm core */ - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* SOC vdd_soc */ - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* I/O power GEN_3V3 */ - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DDR memory */ - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DDR memory */ - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - /* not used */ - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - /* not used */ - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - /* PMIC vsnvs. EX boot mode */ - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - /* not used */ - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - /* not used */ - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - /* not used */ - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* 1v8 general power */ - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* 2v8 general power IMX6 */ - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* 3v3 Ethernet */ - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - no-1-8-v; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 - MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 - MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 - MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ - MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhost: usbhostgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-mba6.dtsi b/arch/arm/boot/dts/imx6dl-mba6.dtsi deleted file mode 100644 index b749b424bbd6..000000000000 --- a/arch/arm/boot/dts/imx6dl-mba6.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -ðphy { - rxdv-skew-ps = <180>; - txen-skew-ps = <0>; - rxd3-skew-ps = <180>; - rxd2-skew-ps = <180>; - rxd1-skew-ps = <180>; - rxd0-skew-ps = <180>; - txd3-skew-ps = <120>; - txd2-skew-ps = <0>; - txd1-skew-ps = <300>; - txd0-skew-ps = <120>; - txc-skew-ps = <1860>; - rxc-skew-ps = <1860>; -}; diff --git a/arch/arm/boot/dts/imx6dl-mba6a.dts b/arch/arm/boot/dts/imx6dl-mba6a.dts deleted file mode 100644 index df0a96b28af0..000000000000 --- a/arch/arm/boot/dts/imx6dl-mba6a.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include -#include "imx6dl-tqma6a.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6a.dtsi" -#include "imx6dl-mba6.dtsi" - -/ { - model = "TQ TQMa6S/DL on MBa6x"; - compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", - "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-mba6b.dts b/arch/arm/boot/dts/imx6dl-mba6b.dts deleted file mode 100644 index 610b19d2db0f..000000000000 --- a/arch/arm/boot/dts/imx6dl-mba6b.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include -#include "imx6dl-tqma6b.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6b.dtsi" -#include "imx6dl-mba6.dtsi" - -/ { - model = "TQ TQMa6S/DL on MBa6x"; - compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", - "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/imx6dl-nit6xlite.dts deleted file mode 100644 index 61fa30991d67..000000000000 --- a/arch/arm/boot/dts/imx6dl-nit6xlite.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-nit6xlite.dtsi" - -/ { - model = "Boundary Devices i.MX6 Solo Nitrogen6_Lite Board"; - compatible = "boundary,imx6dl-nit6xlite", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts deleted file mode 100644 index ef58d3b0ea0d..000000000000 --- a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-nitrogen6x.dtsi" - -/ { - model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; - compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts deleted file mode 100644 index d906a7f05aaa..000000000000 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" -#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" -#include "imx6qdl-phytec-mira-peb-av-02.dtsi" -#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; - compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6dl"; - - chosen { - stdout-path = &uart2; - }; -}; - -ðphy { - max-speed = <100>; -}; - -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts deleted file mode 100644 index 0a07cc6f815e..000000000000 --- a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -/dts-v1/; -#include "imx6dl-phytec-pfla02.dtsi" -#include "imx6qdl-phytec-pbab01.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; - compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi deleted file mode 100644 index 6f8aaf524425..000000000000 --- a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; - compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts deleted file mode 100644 index d85b15a8c127..000000000000 --- a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-pico-pi.dtsi" - -/ { - model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; - compatible = "technexion,imx6dl-pico-dwarf", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts deleted file mode 100644 index 08fedcbcc91b..000000000000 --- a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-pico-hobbit.dtsi" - -/ { - model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; - compatible = "technexion,imx6dl-pico-hobbit", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/imx6dl-pico-nymph.dts deleted file mode 100644 index 32ccfc5d41ce..000000000000 --- a/arch/arm/boot/dts/imx6dl-pico-nymph.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-pico-pi.dtsi" - -/ { - model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; - compatible = "technexion,imx6dl-pico-nymph", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/imx6dl-pico-pi.dts deleted file mode 100644 index 4590e8ad9a91..000000000000 --- a/arch/arm/boot/dts/imx6dl-pico-pi.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-pico-pi.dtsi" - -/ { - model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; - compatible = "technexion,imx6dl-pico-pi", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h deleted file mode 100644 index 9d88d09f9bf6..000000000000 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ /dev/null @@ -1,1088 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6DL_PINFUNC_H -#define __DTS_IMX6DL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 -#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 -#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 -#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 -#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6DL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts deleted file mode 100644 index 84f34da06267..000000000000 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ /dev/null @@ -1,396 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include -#include -#include "imx6dl.dtsi" - -/ { - model = "Plymovent BAS board"; - compatible = "ply,plybas", "fsl,imx6dl"; - - chosen { - stdout-path = &uart4; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - - button-start { - label = "START"; - linux,code = <31>; - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - }; - - button-clean { - label = "CLEAN"; - linux,code = <46>; - gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "debug1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "light_tower1"; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-3 { - label = "light_tower2"; - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - - led-4 { - label = "light_tower3"; - gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - }; - - led-5 { - label = "light_tower4"; - gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; - }; - }; - - clk50m_phy: phy-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_5v0>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_5v0>; - status = "okay"; -}; - -&clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clk50m_phy>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "SD1_CD", "", "", "", "", "", "", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "ECSPI1_SS1", "", "USB_EXT_PWR", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "IMX6_IN12", "IMX6_HMI", - "IMX6_IN11", "IMX6_BUZZER", "IMX6_LED1", "IMX6_LED2", - "IMX6_LED3", "IMX6_LED4", "ETH_RESET", "IMX6_ANA_OUT_SD", - "IMX6_ANA_OUT_ERR", "IMX6_ANA_OUT", "ETH_INTRP", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "IMX6_RELAY1", "IMX6_RELAY2", "", - "IMX6_IN1", "IMX6_IN2", "IMX6_IN3", "IMX6_IN4", "IMX6_IN5", - "IMX6_IN6", "IMX6_IN7", "IMX6_IN8", - "IMX6_IN9", "IMX6_IN10", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 20>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG_0 */ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - /* DEBUG_1 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - - /* LED1 (lighttower) */ - MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x13070 - /* LED2 (lighttower) */ - MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x13070 - /* LED3 (lighttower) */ - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x13070 - /* LED4 (lighttower) */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x13070 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x130b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts deleted file mode 100644 index dfa8110b1d97..000000000000 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ /dev/null @@ -1,573 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include -#include -#include "imx6dl.dtsi" - -/ { - model = "Plymovent M2M board"; - compatible = "ply,plym2m", "fsl,imx6dl"; - - chosen { - stdout-path = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 1000>; - num-interpolated-steps = <20>; - default-brightness-level = <19>; - power-supply = <®_12v0>; - }; - - display { - compatible = "fsl,imx-parallel-display"; - pinctrl-0 = <&pinctrl_ipu1_disp>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel { - compatible = "edt,etm0700g0bdh6"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - clk50m_phy: phy-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_12v0: regulator-12v0 { - compatible = "regulator-fixed"; - regulator-name = "12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - thermal-zones { - chassis-thermal { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&tsens0>; - - trips { - alert { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - - touch-thermal0 { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&touch_temp0>; - - trips { - alert { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - - touch-thermal1 { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&touch_temp1>; - - trips { - alert { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - }; - - touchscreen { - compatible = "resistive-adc-touch"; - io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, - <&adc_ts 5>; - io-channel-names = "y", "z1", "z2", "x"; - touchscreen-min-pressure = <64687>; - touchscreen-inverted-x; - touchscreen-inverted-y; - touchscreen-x-plate-ohms = <300>; - touchscreen-y-plate-ohms = <800>; - }; - - touch_temp0: touch-temperature-sensor0 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc_ts 0>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 736 - 85000 474>; - }; - - touch_temp1: touch-temperature-sensor1 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc_ts 7>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 826 - 85000 609>; - }; - - vdiv_vaccu: voltage-divider-vaccu { - compatible = "voltage-divider"; - io-channels = <&adc_ts 2>; - output-ohms = <2500>; - full-ohms = <64000>; - #io-channel-cells = <0>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_5v0>; - status = "okay"; -}; - -&clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clk50m_phy>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - adc_ts: adc@0 { - compatible = "ti,tsc2046e-adc"; - reg = <0>; - pinctrl-0 = <&pinctrl_tsc2046>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0>; - settling-time-us = <300>; - oversampling-ratio = <5>; - }; - - channel@1 { - reg = <1>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@2 { - reg = <2>; - settling-time-us = <300>; - oversampling-ratio = <5>; - }; - - channel@3 { - reg = <3>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@4 { - reg = <4>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@5 { - reg = <5>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - /* channel 6 is not connected */ - - channel@7 { - reg = <7>; - settling-time-us = <300>; - oversampling-ratio = <5>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "", "", "", "", "", "", - "DEBUG_0", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ECSPI2_SS0", "", "", "", "TSC_BUSY", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "ECSPI1_SS1", "TSC_PENIRQ", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "ETH_RESET", "ETH_INTRP", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x10000 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x3008 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x3008 - /* CS */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x3008 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_disp: ipudisp1grp { - fsl,pins = < - /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 - >; - }; - - pinctrl_tsc2046: tsc2046grp { - fsl,pins = < - /* TSC_PENIRQ */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 - /* TSC_BUSY */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/imx6dl-prtmvt.dts deleted file mode 100644 index 773a84a5739d..000000000000 --- a/arch/arm/boot/dts/imx6dl-prtmvt.dts +++ /dev/null @@ -1,860 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include -#include "imx6dl.dtsi" - -/ { - model = "Protonic MVT board"; - compatible = "prt,prtmvt", "fsl,imx6dl"; - - chosen { - stdout-path = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <1>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - key-power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-f1 { - label = "GPIO Key F1"; - linux,code = ; - gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; - }; - - key-f2 { - label = "GPIO Key F2"; - linux,code = ; - gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; - }; - - key-f3 { - label = "GPIO Key F3"; - linux,code = ; - gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; - }; - - key-f4 { - label = "GPIO Key F4"; - linux,code = ; - gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; - }; - - key-f5 { - label = "GPIO Key F5"; - linux,code = ; - gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; - }; - - key-cycle { - label = "GPIO Key CYCLE"; - linux,code = ; - gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; - }; - - key-esc { - label = "GPIO Key ESC"; - linux,code = ; - gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; - }; - - key-up { - label = "GPIO Key UP"; - linux,code = ; - gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; - }; - - key-down { - label = "GPIO Key DOWN"; - linux,code = ; - gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; - }; - - key-ok { - label = "GPIO Key OK"; - linux,code = ; - gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; - }; - - key-f6 { - label = "GPIO Key F6"; - linux,code = ; - gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; - }; - - key-f7 { - label = "GPIO Key F7"; - linux,code = ; - gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; - }; - - key-f8 { - label = "GPIO Key F8"; - linux,code = ; - gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; - }; - - key-f9 { - label = "GPIO Key F9"; - linux,code = ; - gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; - }; - - key-f10 { - label = "GPIO Key F10"; - linux,code = ; - gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; - }; - - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - panel { - compatible = "kyo,tcg070wvlq", "lg,lb070wv8"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - clk50m_phy: phy-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&rmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <3000>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", - "", "", "", "", "", "", "", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "", "", "", "", - "CPU_LIGHT_ON", "", "ETH_RESET", "", "BL_EN", - "BL_PWM", "ETH_INTRP", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; - - gpio_pca: gpio@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9539>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_h1_vbus>; - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - >; - }; - - pinctrl_pca9539: pca9539 { - fsl,pins = < - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts deleted file mode 100644 index 36b031236e47..000000000000 --- a/arch/arm/boot/dts/imx6dl-prtrvt.dts +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-prti6q.dtsi" -#include - -/ { - model = "Protonic RVT board"; - compatible = "prt,prtrvt", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-debug0 { - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - nfc@0 { - compatible = "ti,trf7970a"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - spi-max-frequency = <2000000>; - interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; - ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, - <&gpio5 11 GPIO_ACTIVE_LOW>; - vin-supply = <®_3v3>; - autosuspend-delay = <30000>; - irq-status-read-quirk; - en2-rf-quirk; - status = "okay"; - }; -}; - -&i2c3 { - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* nc */ - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - /* nc */ - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - /* can1_l */ - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - /* can1_h */ - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&pcie { - status = "okay"; -}; - -&usbh1 { - status = "disabled"; -}; - -&usbotg { - disable-over-current; -}; - -&vpu { - status = "disabled"; -}; - -&iomuxc { - pinctrl_can1phy: can1phy { - fsl,pins = < - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - /* NFC_ASK_OOK */ - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 - /* NFC_PWR_EN */ - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 - /* NFC_EN2 */ - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 - /* NFC_EN */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - /* NFC_MOD */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 - /* NFC_IRQ */ - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts deleted file mode 100644 index 568e98cb62aa..000000000000 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ /dev/null @@ -1,612 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-prti6q.dtsi" -#include -#include -#include -#include - -/ { - model = "Protonic VT7"; - compatible = "prt,prtvt7", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - brightness-levels = <0 20 81 248 1000>; - default-brightness-level = <65>; - num-interpolated-steps = <21>; - power-supply = <®_bl_12v0>; - }; - - display { - compatible = "fsl,imx-parallel-display"; - pinctrl-0 = <&pinctrl_ipu1_disp>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>; - }; - - keys { - compatible = "gpio-keys"; - autorepeat; - - key-esc { - label = "GPIO Key ESC"; - linux,code = ; - gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; - }; - - key-up { - label = "GPIO Key UP"; - linux,code = ; - gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; - }; - - key-down { - label = "GPIO Key DOWN"; - linux,code = ; - gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; - }; - - key-enter { - label = "GPIO Key Enter"; - linux,code = ; - gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; - }; - - key-cycle { - label = "GPIO Key CYCLE"; - linux,code = ; - gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; - }; - - key-f1 { - label = "GPIO Key F1"; - linux,code = ; - gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; - }; - - key-f2 { - label = "GPIO Key F2"; - linux,code = ; - gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; - }; - - key-f3 { - label = "GPIO Key F3"; - linux,code = ; - gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; - }; - - key-f4 { - label = "GPIO Key F4"; - linux,code = ; - gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; - }; - - key-f5 { - label = "GPIO Key F5"; - linux,code = ; - gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; - }; - - key-f6 { - label = "GPIO Key F6"; - linux,code = ; - gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; - }; - - key-f7 { - label = "GPIO Key F7"; - linux,code = ; - gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; - }; - - key-f8 { - label = "GPIO Key F8"; - linux,code = ; - gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; - }; - - key-f9 { - label = "GPIO Key F9"; - linux,code = ; - gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; - }; - - key-f10 { - label = "GPIO Key F10"; - linux,code = ; - gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-debug0 { - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel { - compatible = "innolux,g070y2-t02"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - reg_bl_12v0: regulator-bl-12v0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_bl_12v0>; - regulator-name = "bl-12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - bitclock-master; - frame-master; - }; - }; - - thermal-zones { - chassis-thermal { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&tsens0>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - - touch-thermal0 { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&touch_temp0>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - - touch-thermal1 { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&touch_temp1>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - }; - - touchscreen { - compatible = "resistive-adc-touch"; - io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, - <&adc_ts 5>; - io-channel-names = "y", "z1", "z2", "x"; - touchscreen-min-pressure = <64687>; - touchscreen-x-plate-ohms = <300>; - touchscreen-y-plate-ohms = <800>; - }; - - touch_temp0: touch-temperature-sensor0 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc_ts 0>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 736 - 85000 474>; - }; - - touch_temp1: touch-temperature-sensor1 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc_ts 7>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 826 - 85000 609>; - }; - - vdiv_vaccu: voltage-divider-vaccu { - compatible = "voltage-divider"; - io-channels = <&adc_ts 2>; - output-ohms = <2500>; - full-ohms = <64000>; - #io-channel-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - adc_ts: adc@0 { - compatible = "ti,tsc2046e-adc"; - reg = <0>; - pinctrl-0 = <&pinctrl_tsc>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@1 { - reg = <1>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@3 { - reg = <3>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@4 { - reg = <4>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@5 { - reg = <5>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - }; -}; - -&i2c1 { - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; -}; - -&i2c3 { - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; - - gpio_pca: gpio@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - }; -}; - -&ipu1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display_in>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1phy: can1phy { - fsl,pins = < - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - >; - }; - - pinctrl_ipu1_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 - - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 - - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 - - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_reg_bl_12v0: 12blgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; - - pinctrl_tsc: tscgrp { - - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi deleted file mode 100644 index 05fd8ff4da1e..000000000000 --- a/arch/arm/boot/dts/imx6dl-qmx6.dtsi +++ /dev/null @@ -1,612 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT -// -// Device Tree Source for i.MX6DL based congatec QMX6 -// System on Module -// -// Copyright 2018-2021 General Electric Company -// Copyright 2018-2021 Collabora -// Copyright 2016 congatec AG - -#include "imx6dl.dtsi" -#include -#include - -/ { - memory@10000000 { - reg = <0x10000000 0x40000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c2>; - - i2c5: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c6: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - - mux-ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) - >; - }; - - mux-aud6 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&clks { - clocks = <&rtc_sqw>; - clock-names = "ckil"; - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, - <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf032b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - - partition@0 { - label = "bootloader"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "user"; - reg = <0x0100000 0x2fc000>; - }; - - partition@3fc000 { - label = "reserved"; - reg = <0x03fc000 0x4000>; - read-only; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - fsl,magic-packet; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@6 { - reg = <6>; - qca,clk-out-frequency = <125000000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - rtc: m41t62@68 { - compatible = "st,m41t62"; - reg = <0x68>; - - rtc_sqw: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&i2c6 { - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - /* - * keep VGEN3, VGEN4 and VGEN5 enabled in order to - * maintain backward compatibility with hw-rev. A.0 - */ - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* supply voltage for eMMC */ - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 20 0>; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; -}; - -&usdhc2 { - /* MicroSD card slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc3 { - /* eMMC module */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - bus-width = <8>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - qmx6mux: imx6qdl-qmx6 { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ - >; - }; - - /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ - pinctrl_enet: enet { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ - >; - }; - - pinctrl_i2c1: i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ - >; - }; - - pinctrl_i2c2: i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ - >; - }; - - pinctrl_i2c2_gpio: i2c2-gpio { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ - >; - }; - - pinctrl_i2c3: i2c3 { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ - >; - }; - - pinctrl_i2c3_gpio: i2c3-gpio { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ - >; - }; - - pinctrl_phy_reset: phy-reset { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ - >; - }; - - pinctrl_pwm4: pwm4 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ - >; - }; - - pinctrl_q7_backlight_enable: q7-backlight-enable { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ - >; - }; - - pinctrl_q7_gpio0: q7-gpio0 { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ - >; - }; - - pinctrl_q7_gpio1: q7-gpio1 { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ - >; - }; - - pinctrl_q7_gpio2: q7-gpio2 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ - >; - }; - - pinctrl_q7_gpio3: q7-gpio3 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ - >; - }; - - pinctrl_q7_gpio4: q7-gpio4 { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ - >; - }; - - pinctrl_q7_gpio5: q7-gpio5 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ - >; - }; - - pinctrl_q7_gpio6: q7-gpio6 { - fsl,pins = < - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ - >; - }; - - pinctrl_q7_gpio7: q7-gpio7 { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ - >; - }; - - pinctrl_q7_hda_reset: q7-hda-reset { - fsl,pins = < - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ - >; - }; - - pinctrl_q7_lcd_power: lcd-power { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ - >; - }; - - pinctrl_q7_sdio_power: q7-sdio-power { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ - >; - }; - - pinctrl_q7_sleep_button: q7-sleep-button { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ - >; - }; - - pinctrl_q7_spi_cs1: spi-cs1 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ - >; - }; - - /* SPI1 bus does not leave System on Module */ - pinctrl_spi1: spi1 { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - >; - }; - - /* Debug connector on Q7 module */ - pinctrl_uart2: uart2 { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3 { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ - >; - }; - - pinctrl_usbotg: usbotg { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ - >; - }; - - /* µSD card slot on Q7 module */ - pinctrl_usdhc2: usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ - >; - }; - - /* eMMC module on Q7 module */ - pinctrl_usdhc3: usdhc3 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4 { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ - >; - }; - - pinctrl_wdog: wdog { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts deleted file mode 100644 index b72f8ea1e6f6..000000000000 --- a/arch/arm/boot/dts/imx6dl-rex-basic.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-rex.dtsi" - -/ { - model = "Rex Basic i.MX6 Dual Lite Board"; - compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; - -&ecspi3 { - flash: flash@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts deleted file mode 100644 index 0366d1037ef4..000000000000 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ /dev/null @@ -1,597 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 Iain Paton - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include - -/ { - model = "RIoTboard i.MX6S"; - compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6-riotboard-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - fsl,pmic-stby-poweroff; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Atheros AR8035 PHY */ - rgmii_phy: ethernet-phy@4 { - reg = <4>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <1000>; - qca,smarteee-tw-us-1g = <24>; - qca,clk-out-frequency = <125000000>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", - "I2C3_SDA", "I2C4_SCL", - "I2C4_SDA", "", "", "", "", "", "", "", - "", "PWM3", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "USB_OTG_VBUS", "", - "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", - "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", - "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", - "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", - "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; -}; - -&gpio5 { - gpio-line-names = - "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", - "GPIO5_07", - "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", - "CSPI2_CS0", "CSPI2_CLK", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio7 { - gpio-line-names = - "SD3_CD", "SD3_WP", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - interrupt-parent = <&gpio5>; - interrupts = <16 8>; - fsl,pmic-stby-poweroff; - - regulators { - reg_vddcore: sw1ab { /* VDDARM_IN */ - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_vddsoc: sw1c { /* VDDSOC_IN */ - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_gen_3v3: sw2 { /* VDDHIGH_IN */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_vtt: sw4 { /* MIPI conn */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_5v_600mA: swbst { /* not used */ - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { /* VREF_DDR */ - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1_1v5: vgen1 { /* not used */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - reg_vgen3_2v8: vgen3 { /* not used */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&clks 116>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6-riotboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts deleted file mode 100644 index ff3283c83a39..000000000000 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; -}; - -&cpu0 { - operating-points = < - /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1200000 - 792000 1175000 - 396000 1175000 - >; -}; diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts deleted file mode 100644 index 33040761b253..000000000000 --- a/arch/arm/boot/dts/imx6dl-sabrelite.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-sabrelite.dtsi" - -/ { - model = "Freescale i.MX6 DualLite SABRE Lite Board"; - compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts deleted file mode 100644 index cd6bbf22a16f..000000000000 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/arch/arm/boot/dts/imx6dl-savageboard.dts b/arch/arm/boot/dts/imx6dl-savageboard.dts deleted file mode 100644 index b95469c520a4..000000000000 --- a/arch/arm/boot/dts/imx6dl-savageboard.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2017 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-savageboard.dtsi" - -/ { - model = "Poslab SavageBoard Dual"; - compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts b/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts deleted file mode 100644 index b12b5aabe70a..000000000000 --- a/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-skov-cpu.dtsi" -#include "imx6qdl-skov-cpu-revc.dtsi" -#include "imx6qdl-skov-revc-lt2.dtsi" - -/ { - model = "SKOV IMX6 CPU SoloCore"; - compatible = "skov,imx6dl-skov-revc-lt2", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts b/arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts deleted file mode 100644 index 5dcc433fe2af..000000000000 --- a/arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-skov-cpu.dtsi" -#include "imx6qdl-skov-cpu-revc.dtsi" - -/ { - model = "SKOV IMX6 CPU SoloCore"; - compatible = "skov,imx6dl-skov-revc-lt6", "fsl,imx6dl"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; - pwms = <&pwm2 0 20000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <17>; - default-brightness-level = <8>; - power-supply = <®_24v0>; - }; - - display { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel { - compatible = "logictechno,lttd800480070-l6wh-rt"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display0_out>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-solidsense.dts b/arch/arm/boot/dts/imx6dl-solidsense.dts deleted file mode 100644 index 2a3699adbed0..000000000000 --- a/arch/arm/boot/dts/imx6dl-solidsense.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" -#include "imx6qdl-solidsense.dtsi" - -/ { - model = "SolidRun SolidSense Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,solidsense/dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi deleted file mode 100644 index e891ef9b0091..000000000000 --- a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-tqma6a.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi deleted file mode 100644 index 38cd8501a886..000000000000 --- a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-tqma6b.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts deleted file mode 100644 index 3d60cc725d9e..000000000000 --- a/arch/arm/boot/dts/imx6dl-ts4900.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-ts4900.dtsi" - -/ { - model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts deleted file mode 100644 index 5da6feba2e66..000000000000 --- a/arch/arm/boot/dts/imx6dl-ts7970.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-ts7970.dtsi" - -/ { - model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts deleted file mode 100644 index 51a9bb9d6bc2..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; - -&backlight { - pwms = <&pwm2 0 500000 0>; - /delete-property/ turn-on-delay-ms; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&kpp { - status = "disabled"; -}; - -&lcd_panel { - compatible = "edt,etm0700g0edh6"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts deleted file mode 100644 index fc23b4d291a1..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6s-8034.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts deleted file mode 100644 index 9eb2ef17339c..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2015-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8034 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - cpus { - /delete-node/ cpu@1; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&pinctrl_usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts deleted file mode 100644 index 4101c6597721..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6s-8035.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts deleted file mode 100644 index a5532ecc18c5..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2015-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8035 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - cpus { - /delete-node/ cpu@1; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts deleted file mode 100644 index 67ed0452f5de..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-801x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts deleted file mode 100644 index d34189fc52d9..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6u-8033.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts deleted file mode 100644 index 7030b2654bbd..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8033 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts deleted file mode 100644 index aef5fcc42904..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6u-801x.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts deleted file mode 100644 index 5342f2f5a8a8..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lvds.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-811x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts deleted file mode 100644 index c4588fb0bf6f..000000000000 --- a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2016-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6u-811x.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6dl-udoo.dts b/arch/arm/boot/dts/imx6dl-udoo.dts deleted file mode 100644 index d871cac1711f..000000000000 --- a/arch/arm/boot/dts/imx6dl-udoo.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-udoo.dtsi" - -/ { - model = "Udoo i.MX6 Dual-lite Board"; - compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts deleted file mode 100644 index 4875afadb630..000000000000 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-vicut1.dtsi" - -/ { - model = "Kverneland TGO"; - compatible = "kvg,victgo", "fsl,imx6dl"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - key-power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-enter { - label = "Rotary Key"; - gpios = <&gpio2 05 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; - }; - - panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - clk50m_phy: phy-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - rotary-encoder { - compatible = "rotary-encoder"; - pinctrl-0 = <&pinctrl_rotary_ch>; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>, - <&gpio2 4 GPIO_ACTIVE_HIGH>; - linux,axis = ; - rotary-encoder,steps-per-period = <4>; - rotary-encoder,relative-axis; - rotary-encoder,rollover; - wakeup-source; - }; - - thermal-zones { - chassis-thermal { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&tsens0>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - - touch-thermal0 { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&touch_temp0>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - - touch-thermal1 { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&touch_temp1>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - }; - - touchscreen { - compatible = "resistive-adc-touch"; - io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, - <&adc_ts 5>; - io-channel-names = "y", "z1", "z2", "x"; - touchscreen-min-pressure = <64687>; - touchscreen-inverted-y; - touchscreen-x-plate-ohms = <300>; - touchscreen-y-plate-ohms = <800>; - }; - - touch_temp0: touch-temperature-sensor0 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc_ts 0>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 736 - 85000 474>; - }; - - touch_temp1: touch-temperature-sensor1 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc_ts 7>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 826 - 85000 609>; - }; - - vdiv_vaccu: voltage-divider-vaccu { - compatible = "voltage-divider"; - io-channels = <&adc_ts 2>; - output-ohms = <2500>; - full-ohms = <64000>; - #io-channel-cells = <0>; - }; - - vdiv_hitch_pos: voltage-divider-hitch-pos { - compatible = "voltage-divider"; - io-channels = <&adc_ts 6>; - output-ohms = <3300>; - full-ohms = <13300>; - #io-channel-cells = <0>; - }; -}; - -&clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clk50m_phy>; -}; - -&ecspi2 { - cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - adc_ts: adc@0 { - compatible = "ti,tsc2046e-adc"; - reg = <0>; - pinctrl-0 = <&pinctrl_touchscreen>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@1 { - reg = <1>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@3 { - reg = <3>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@4 { - reg = <4>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@5 { - reg = <5>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&rmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "", "", "", "", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN", - "BL_PWM", "ETH_INT", "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO", - "ECSPI2_SS0", "ECSPI2_SCLK", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - keypad@70 { - compatible = "holtek,ht16k33"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keypad>; - reg = <0x70>; - refresh-rate-hz = <20>; - debounce-delay-ms = <50>; - interrupts-extended = <&gpio4 5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - keypad,num-rows = <12>; - keypad,num-columns = <3>; - linux,keymap = < - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(3, 0, KEY_F8) - MATRIX_KEY(4, 0, KEY_F10) - MATRIX_KEY(5, 0, KEY_F4) - MATRIX_KEY(6, 0, KEY_F2) - MATRIX_KEY(2, 1, KEY_F5) - MATRIX_KEY(3, 1, KEY_F7) - MATRIX_KEY(4, 1, KEY_F9) - MATRIX_KEY(5, 1, KEY_F3) - MATRIX_KEY(6, 1, KEY_F1) - >; - }; -}; - -&iomuxc { - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* ROTARY_BTN */ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; - - pinctrl_keypad: keypadgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_rotary_ch: rotarychgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts deleted file mode 100644 index 5035d303447d..000000000000 --- a/arch/arm/boot/dts/imx6dl-vicut1.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-vicut1.dtsi" -#include "imx6qdl-vicut1-12inch.dtsi" - -/ { - model = "Kverneland UT1 Board"; - compatible = "kvg,vicut1", "fsl,imx6dl"; -}; diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts deleted file mode 100644 index c2946fbaa0dd..000000000000 --- a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board rev B1"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts deleted file mode 100644 index 6d1d863c2e3a..000000000000 --- a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revd1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board revD1"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts deleted file mode 100644 index 4a08d5a99452..000000000000 --- a/arch/arm/boot/dts/imx6dl-wandboard.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revc1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi deleted file mode 100644 index 3be38a3c4bb1..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ /dev/null @@ -1,648 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -#include -#include -#include -#include -#include - -/ { - aliases: aliases { - ethernet1 = ð1; - ethernet2 = ð2; - mmc0 = &usdhc3; - mmc1 = &usdhc4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 32 64 128 255>; - default-brightness-level = <32>; - num-interpolated-steps = <8>; - power-supply = <&sw2_reg>; - status = "disabled"; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - compatible = "dataimage,scf0700c48ggu18"; - power-supply = <&sw2_reg>; - backlight = <&backlight>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-supply = <&sw2_reg>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - - switch@10 { - compatible = "qca,qca8334"; - reg = <10>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - - switch_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: port@0 { - reg = <0>; - label = "cpu"; - phy-mode = "rgmii-id"; - ethernet = <&fec>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - eth2: port@2 { - reg = <2>; - label = "eth2"; - phy-handle = <&phy_port2>; - }; - - eth1: port@3 { - reg = <3>; - label = "eth1"; - phy-handle = <&phy_port3>; - }; - }; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; - status = "disabled"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze200"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vsnvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - leds: led-controller@30 { - compatible = "ti,lp5562"; - reg = <0x30>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - led@0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <0>; - color = ; - }; - - led@1 { - chan-name = "G"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <1>; - color = ; - }; - - led@2 { - chan-name = "B"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <2>; - color = ; - }; - }; - - eeprom@57 { - compatible = "atmel,24c128"; - reg = <0x57>; - pagesize = <64>; - }; - - touchscreen: touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - pinctrl-0 = <&pinctrl_touch>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - status = "disabled"; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - oled_1309: oled@3c { - compatible = "solomon,ssd1309fb-i2c"; - reg = <0x3c>; - solomon,height = <64>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,segment-no-remap; - solomon,prechargep2 = <15>; - reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; - vbat-supply = <&sw2_reg>; - status = "disabled"; - }; - - oled_1305: oled@3d { - compatible = "solomon,ssd1305fb-i2c"; - reg = <0x3d>; - solomon,height = <64>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,col-offset = <4>; - solomon,prechargep2 = <15>; - reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; - vbat-supply = <&sw2_reg>; - status = "disabled"; - }; - - gpio_oled: gpio@41 { - compatible = "nxp,pca9536"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x41>; - vcc-supply = <&sw2_reg>; - status = "disabled"; - }; - - touchkeys: keys@5a { - compatible = "fsl,mpr121-touchkey"; - reg = <0x5a>; - vdd-supply = <&sw2_reg>; - autorepeat; - linux,keycodes = , , , , , - , , , , - , , ; - poll-interval = <50>; - status = "disabled"; - }; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbus { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbus { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "disabled"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - over-current-active-low; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - over-current-active-low; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; - status = "okay"; -}; - -&usbphy2 { - fsl,tx-d-cal = <109>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&sw2_reg>; - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - vmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts deleted file mode 100644 index a38c407fd837..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Draco i.MX6Solo board"; - compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; - -&backlight { - status = "okay"; -}; - -&lcd_display { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchscreen { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts deleted file mode 100644 index a19609c7c7c0..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Hydra i.MX6DualLite board"; - compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled_1305 { - status = "okay"; -}; - -&oled_1309 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -®_pcie { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts deleted file mode 100644 index 5c2cd517589b..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp43-common.dtsi" - -/ { - model = "Y Soft IOTA Lynx i.MX6DualLite board"; - compatible = "ysoft,imx6dl-yapp4-lynx", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; - -&backlight { - status = "okay"; -}; - -&lcd_display { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchscreen { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts deleted file mode 100644 index 884b236746bb..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2020 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Orion i.MX6DualLite board"; - compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xf0000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled_1305 { - status = "okay"; -}; - -&oled_1309 { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&uart2 { - status = "disabled"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts b/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts deleted file mode 100644 index e0292f11d03e..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp43-common.dtsi" - -/ { - model = "Y Soft IOTA Phoenix i.MX6DualLite board"; - compatible = "ysoft,imx6dl-yapp4-phoenix", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; - -&aliases { - /delete-property/ ethernet1; -}; - -&gpio_keys { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&switch_ports { - /delete-node/ port@2; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts deleted file mode 100644 index f6ae24efd4aa..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Ursa i.MX6Solo board"; - compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; - -&aliases { - /delete-property/ ethernet1; -}; - -&backlight { - status = "okay"; -}; - -&lcd_display { - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&switch_ports { - /delete-node/ port@3; -}; - -&touchscreen { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi deleted file mode 100644 index 52a0f6ee426f..000000000000 --- a/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi +++ /dev/null @@ -1,615 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -#include -#include -#include -#include -#include - -/ { - aliases: aliases { - ethernet1 = ð1; - ethernet2 = ð2; - mmc0 = &usdhc3; - mmc1 = &usdhc4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 32 64 128 255>; - default-brightness-level = <32>; - num-interpolated-steps = <8>; - power-supply = <&sw2_reg>; - status = "disabled"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - status = "disabled"; - - button { - label = "Factory RESET"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - compatible = "dataimage,scf0700c48ggu18"; - power-supply = <&sw2_reg>; - backlight = <&backlight>; - enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-supply = <&sw2_reg>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - - switch_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: port@0 { - reg = <0>; - label = "cpu"; - phy-mode = "rgmii-id"; - ethernet = <&fec>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - eth2: port@1 { - reg = <1>; - label = "eth2"; - phy-handle = <&phy_port1>; - }; - - eth1: port@2 { - reg = <2>; - label = "eth1"; - phy-handle = <&phy_port2>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy_port1: switchphy@11 { - reg = <0x11>; - }; - - phy_port2: switchphy@12 { - reg = <0x12>; - }; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze200"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vsnvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - leds: led-controller@30 { - compatible = "ti,lp5562"; - reg = <0x30>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - led@0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <0>; - color = ; - }; - - led@1 { - chan-name = "G"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <1>; - color = ; - }; - - led@2 { - chan-name = "B"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <2>; - color = ; - }; - }; - - eeprom@57 { - compatible = "atmel,24c128"; - reg = <0x57>; - pagesize = <64>; - }; - - touchscreen: touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - pinctrl-0 = <&pinctrl_touch>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - status = "disabled"; - }; - - rtc: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; - - oled_1309: oled@3c { - compatible = "solomon,ssd1309fb-i2c"; - reg = <0x3c>; - solomon,height = <64>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,segment-no-remap; - solomon,prechargep2 = <15>; - reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; - vbat-supply = <&sw2_reg>; - status = "disabled"; - }; - - oled_1305: oled@3d { - compatible = "solomon,ssd1305fb-i2c"; - reg = <0x3d>; - solomon,height = <64>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,col-offset = <4>; - solomon,prechargep2 = <15>; - reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; - vbat-supply = <&sw2_reg>; - status = "disabled"; - }; - - gpio_oled: gpio@41 { - compatible = "nxp,pca9536"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x41>; - vcc-supply = <&sw2_reg>; - status = "disabled"; - }; - - touchkeys: keys@5a { - compatible = "fsl,mpr121-touchkey"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchkeys>; - reg = <0x5a>; - vdd-supply = <&sw2_reg>; - autorepeat; - linux,keycodes = , , , , , - , , , , - , , ; - poll-interval = <50>; - status = "disabled"; - }; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 - >; - }; - - pinctrl_touchkeys: touchkeysgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b098 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbus { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbus { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - over-current-active-low; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - over-current-active-low; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; - status = "okay"; -}; - -&usbphy2 { - fsl,tx-d-cal = <109>; - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - vmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi deleted file mode 100644 index dc919e09a505..000000000000 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ /dev/null @@ -1,397 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include -#include "imx6dl-pinfunc.h" -#include "imx6qdl.dtsi" - -/ { - aliases { - i2c3 = &i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - }; - - soc: soc { - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips1: bus@2000000 { - pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: bus@2100000 { - i2c4: i2c@21f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6DL_CLK_I2C4>; - status = "disabled"; - }; - }; - }; - - capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>; - }; -}; - -&gpio1 { - gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, - <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, - <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, - <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, - <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, - <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, - <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; -}; - -&gpio2 { - gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, - <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, - <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, - <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, - <&iomuxc 28 113 4>; -}; - -&gpio3 { - gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, - <&iomuxc 16 81 16>; -}; - -&gpio4 { - gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, - <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, - <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, - <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, - <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; -}; - -&gpio5 { - gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, - <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, - <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, - <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; -}; - -&gpio6 { - gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, - <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, - <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, - <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, - <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, - <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; -}; - -&gpio7 { - gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, - <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, - <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; -}; - -&gpr { - ipu1_csi0_mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu1_csi0_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu1_csi0_mux_from_mipi_vc1: endpoint { - remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; - }; - }; - - port@2 { - reg = <2>; - - ipu1_csi0_mux_from_mipi_vc2: endpoint { - remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; - }; - }; - - port@3 { - reg = <3>; - - ipu1_csi0_mux_from_mipi_vc3: endpoint { - remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; - }; - }; - - port@4 { - reg = <4>; - - ipu1_csi0_mux_from_parallel_sensor: endpoint { - }; - }; - - port@5 { - reg = <5>; - - ipu1_csi0_mux_to_ipu1_csi0: endpoint { - remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; - }; - }; - }; - - ipu1_csi1_mux { - compatible = "video-mux"; - mux-controls = <&mux 1>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu1_csi1_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu1_csi1_mux_from_mipi_vc1: endpoint { - remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; - }; - }; - - port@2 { - reg = <2>; - - ipu1_csi1_mux_from_mipi_vc2: endpoint { - remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; - }; - }; - - port@3 { - reg = <3>; - - ipu1_csi1_mux_from_mipi_vc3: endpoint { - remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; - }; - }; - - port@4 { - reg = <4>; - - ipu1_csi1_mux_from_parallel_sensor: endpoint { - }; - }; - - port@5 { - reg = <5>; - - ipu1_csi1_mux_to_ipu1_csi1: endpoint { - remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; - }; - }; - }; -}; - -&gpt { - compatible = "fsl,imx6dl-gpt"; -}; - -&hdmi { - compatible = "fsl,imx6dl-hdmi"; -}; - -&iomuxc { - compatible = "fsl,imx6dl-iomuxc"; -}; - -&ipu1_csi1 { - ipu1_csi1_from_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; - }; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; -}; - -&mipi_csi { - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; - }; - - mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; - }; - }; - - port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; - }; - - mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; - }; - }; - - port@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; - }; - - mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; - }; - }; - - port@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; - }; - - mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; - }; - }; -}; - -&mux { - mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ - <0x34 0x00000038>, /* IPU_CSI1_MUX */ - <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ - <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ - <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ - <0x28 0x00000003>, /* DCIC1_MUX_CTL */ - <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ -}; - -&vpu { - compatible = "fsl,imx6dl-vpu", "cnm,coda960"; -}; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts deleted file mode 100644 index 3fc079dfd61e..000000000000 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; - compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_pcie_switch: regulator-pcie-switch { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "pcie_switch"; - startup-delay-us = <100000>; - status = "okay"; - }; - - reg_3v3_sw: regulator-3v3-sw { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3.3V_SW"; - }; -}; - -&can1 { - xceiver-supply = <®_3v3_sw>; - status = "okay"; -}; - -&can2 { - xceiver-supply = <®_3v3_sw>; - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - vpcie-supply = <®_pcie_switch>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* MMC1 */ -&usdhc1 { - status = "okay"; -}; - -/* SD1 */ -&usdhc2 { - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts deleted file mode 100644 index 44637d606e61..000000000000 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -#include "imx6q-apalis-ixora-v1.2.dts" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; - compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q", - "fsl,imx6q"; - - -}; - -/delete-node/ &eeprom; -/delete-node/ ®_3v3_vmmc; -/delete-node/ ®_can1_supply; -/delete-node/ ®_can2_supply; - -&can1 { - /delete-property/ xceiver-supply; -}; - -&can2 { - /delete-property/ xceiver-supply; -}; - -/* MMC1 */ -&usdhc1 { - /delete-property/ cap-power-off-card; - /delete-property/ pinctrl-1; - /delete-property/ vmmc-supply; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts deleted file mode 100644 index 717decda0ceb..000000000000 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2"; - compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - label = "LED_4_GREEN"; - }; - - led4-red { - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - label = "LED_4_RED"; - }; - - led5-green { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - label = "LED_5_GREEN"; - }; - - led5-red { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "LED_5_RED"; - }; - }; - - reg_3v3_vmmc: regulator-3v3-vmmc { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3v3_vmmc"; - startup-delay-us = <100>; - }; - - reg_can1_supply: regulator-can1-supply { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_can1_power>; - regulator-name = "can1_supply"; - }; - - reg_can2_supply: regulator-can2-supply { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_can2_power>; - regulator-name = "can2_supply"; - }; -}; - -&can1 { - xceiver-supply = <®_can1_supply>; - status = "okay"; -}; - -&can2 { - xceiver-supply = <®_can2_supply>; - status = "okay"; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart24_forceoff>; - - /* - * uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis - * UART2 and UART3. If one wants to disable the transceiver force - * the GPIO to output-low, if one wants to control the transceiver - * from user space delete the hog node. - */ - uart-2-4-on-x21-enable-hog { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */ - output-high; - }; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* MMC1 */ -&usdhc1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; - pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>; - bus-width = <4>; - cap-power-off-card; - vmmc-supply = <®_3v3_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - pinctrl_enable_can1_power: enablecan1powergrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - >; - }; - - pinctrl_enable_can2_power: enablecan2powergrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 - >; - }; - - pinctrl_uart24_forceoff: uart24forceoffgrp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 - >; - }; - - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; - - pinctrl_mmc_cd_sleep: mmccdslpgrp { - fsl,pins = < - /* MMC1 CD */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0 - >; - }; - - pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts deleted file mode 100644 index f338be435277..000000000000 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board"; - compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - label = "LED_4_GREEN"; - }; - - led4-red { - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - label = "LED_4_RED"; - }; - - led5-green { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - label = "LED_5_GREEN"; - }; - - led5-red { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "LED_5_RED"; - }; - }; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* SD1 */ -&usdhc2 { - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - status = "okay"; -}; - -&iomuxc { - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/imx6q-apf6dev.dts deleted file mode 100644 index 664b0af8f0bb..000000000000 --- a/arch/arm/boot/dts/imx6q-apf6dev.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-apf6.dtsi" -#include "imx6qdl-apf6dev.dtsi" - -/ { - model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; - compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts deleted file mode 100644 index 75586299d9ca..000000000000 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Freescale i.MX6 Quad Armadillo2 Board"; - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - - debug-led { - label = "Heartbeat"; - gpios = <&gpio3 25 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "disabled"; /* gpmi nand conflicts with SD */ -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-arm2 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - status = "okay"; -}; - -&usdhc4 { - non-removable; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,dte-mode; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts deleted file mode 100644 index d994b32ad825..000000000000 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B450v3"; - compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pca9539 { - gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", - "", "SM_D_ACT", "DP1_RST#", "", - "WD15S_EN", "WD15S_DIS#", "", "", - "", "", "", ""; - - P04-hog { - gpio-hog; - gpios = <4 0>; - output-low; - line-name = "PCA9539-P04"; - }; - - P07-hog { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; -}; - -&pci_root { - /* Intel Corporation I210 Gigabit Network Connection */ - switch_nic: ethernet@3,0 { - compatible = "pci8086,1533"; - reg = <0x00010000 0 0 0 0>; - }; -}; - -&switch_ports { - port@0 { - reg = <0>; - label = "enacq"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "eneport1"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "enix"; - phy-handle = <&switchphy2>; - }; - - port@3 { - reg = <3>; - label = "enid"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&switch_nic>; - phy-handle = <&switchphy4>; - }; - - port@5 { - reg = <5>; - label = "enembc"; - - /* connected to Ethernet MAC of AT91RM9200 in MII mode */ - fixed-link { - speed = <100>; - full-duplex; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts deleted file mode 100644 index fa1a1df37cde..000000000000 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B650v3"; - compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pca9539 { - gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", - "", "SM_D_ACT", "DP1_RST#", "", - "WD15S_EN", "WD15S_DIS#", "", "", - "", "", "", ""; - - P07-hog { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; -}; - -&usbphy1 { - fsl,tx-cal-45-dn-ohms = <55>; - fsl,tx-cal-45-dp-ohms = <55>; - fsl,tx-d-cal = <100>; -}; - -&pci_root { - /* Intel Corporation I210 Gigabit Network Connection */ - switch_nic: ethernet@3,0 { - compatible = "pci8086,1533"; - reg = <0x00010000 0 0 0 0>; - }; -}; - -&switch_ports { - port@0 { - reg = <0>; - label = "enacq"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "eneport1"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "enix"; - phy-handle = <&switchphy2>; - }; - - port@3 { - reg = <3>; - label = "enid"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&switch_nic>; - phy-handle = <&switchphy4>; - }; - - port@5 { - reg = <5>; - label = "enembc"; - - /* connected to Ethernet MAC of AT91RM9200 in MII mode */ - fixed-link { - speed = <100>; - full-duplex; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts deleted file mode 100644 index db8c332df6a1..000000000000 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B850v3"; - compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&stdp4028_in>; - }; - }; - }; -}; - -&i2c2 { - pca9547_ddc: mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - mux2_i2c1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - - mux2_i2c2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - - mux2_i2c3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - mux2_i2c4: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - - mux2_i2c5: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - - mux2_i2c6: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - - mux2_i2c7: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - - mux2_i2c8: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&mux2_i2c1>; -}; - -&mux1_i2c1 { - ads7830@4a { - compatible = "ti,ads7830"; - reg = <0x4a>; - }; -}; - -&mux2_i2c2 { - clock-frequency = <100000>; - - stdp2690@72 { - compatible = "megachips,stdp2690-ge-b850v3-fw"; - reg = <0x72>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - stdp2690_in: endpoint { - remote-endpoint = <&stdp4028_out>; - }; - }; - - port@1 { - reg = <1>; - - stdp2690_out: endpoint { - /* Connector for external display */ - }; - }; - }; - }; - - stdp4028@73 { - compatible = "megachips,stdp4028-ge-b850v3-fw"; - reg = <0x73>; - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - stdp4028_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - - stdp4028_out: endpoint { - remote-endpoint = <&stdp2690_in>; - }; - }; - }; - }; -}; - -&pca9539 { - gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", - "REMOTE_ON_PML#", "SM_D_ACT", "DP1_RST#", "DP2_RST#", - "", "", "", "", - "", "", "", ""; - - P10-hog { - gpio-hog; - gpios = <8 0>; - output-low; - line-name = "PCA9539-P10"; - }; - - P11-hog { - gpio-hog; - gpios = <9 0>; - output-low; - line-name = "PCA9539-P11"; - }; -}; - -&pci_root { - /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ - bridge@1,0 { - compatible = "pci10b5,8605"; - reg = <0x00010000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - bridge@2,1 { - compatible = "pci10b5,8605"; - reg = <0x00020800 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - /* Intel Corporation I210 Gigabit Network Connection */ - ethernet@3,0 { - compatible = "pci8086,1533"; - reg = <0x00030000 0 0 0 0>; - }; - }; - - bridge@2,2 { - compatible = "pci10b5,8605"; - reg = <0x00021000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - /* Intel Corporation I210 Gigabit Network Connection */ - switch_nic: ethernet@4,0 { - compatible = "pci8086,1533"; - reg = <0x00040000 0 0 0 0>; - }; - }; - }; -}; - -&switch_ports { - port@0 { - reg = <0>; - label = "eneport1"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "eneport2"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "enix"; - phy-handle = <&switchphy2>; - }; - - port@3 { - reg = <3>; - label = "enid"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&switch_nic>; - phy-handle = <&switchphy4>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi deleted file mode 100644 index f266f1b7e0cf..000000000000 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Support for imx6 based Advantech DMS-BA16 Qseven module - * - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q.dtsi" -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_display>; - pwms = <&pwm1 0 5000000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <255>; - enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - reg = <0>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x10000>; - }; - - partition@d0000 { - label = "spare"; - reg = <0xd0000 0x320000>; - }; - - partition@3f0000 { - label = "mfg"; - reg = <0x3f0000 0x10000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-supply = <®_3p3v>; - phy-handle = <&phy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@4 { - reg = <4>; - qca,clk-out-frequency = <125000000>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio7>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - regulators { - vdd_bcore1: bcore1 { - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1420000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bcore2: bcore2 { - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1420000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bmem: bmem { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bio: bio { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1860000>; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1860000>; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3440000>; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3440000>; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo9: ldo9 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc@32 { - compatible = "epson,rx8010"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x32>; - interrupt-parent = <&gpio4>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - fsl,tx-swing-full = <103>; - fsl,tx-swing-low = <103>; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&sata { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - vbus-supply = <®_usb_h1_vbus>; - reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; - bus-width = <8>; - vmmc-supply = <&vdd_bperi>; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_display: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SPI1 CS */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* FEC Reset */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - /* AR8033 Interrupt */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* GPIO 0-7 */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 - /* SUS_S3_OUT to CPLD */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe Reset */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* PCIe Wake */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC Interrupt */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - /* RTC_INT */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - /* HUB_RESET */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - /* uSDHC2 CD */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_reset: usdhc3grp-reset { - fsl,pins = < - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - /* uSDHC4 CD */ - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - /* uSDHC4 SDIO PWR */ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - /* uSDHC4 SDIO WP */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* uSDHC4 SDIO LED */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts deleted file mode 100644 index 8263bfef9bf8..000000000000 --- a/arch/arm/boot/dts/imx6q-bosch-acc.dts +++ /dev/null @@ -1,779 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for the i.MX6-based Bosch ACC board. - * - * Copyright (C) 2016 Garz & Fricke GmbH - * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher - * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie - * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker - * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner - */ - -/dts-v1/; - -#include -#include -#include "imx6q.dtsi" - -/ { - model = "Bosch ACC"; - compatible = "bosch,imx6q-acc", "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc4; - mmc1 = &usdhc2; - serial0 = &uart2; - serial1 = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 200000>; - brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; - num-interpolated-steps = <10>; - default-brightness-level = <60>; - power-supply = <®_lcd>; - }; - - panel { - compatible = "dataimage,fg1001l0dsswmg01"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - refclk: refclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "12mhz_refclk"; - assigned-clocks = <&clks IMX6QDL_CLK_CKO>, - <&clks IMX6QDL_CLK_CKO2>, - <&clks IMX6QDL_CLK_CKO2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, - <&clks IMX6QDL_CLK_CKO2_PODF>, - <&clks IMX6QDL_CLK_OSC>; - assigned-clock-rates = <0>, <12000000>, <0>; - }; - - cpus { - cpu0: cpu@0 { - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1225000 - 852000 1225000 - 792000 1150000 - 396000 950000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1225000 - 996000 1175000 - 852000 1175000 - 792000 1150000 - 396000 1150000 - >; - }; - - cpu1: cpu@1 { - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1225000 - 852000 1225000 - 792000 1150000 - 396000 950000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1225000 - 996000 1175000 - 852000 1175000 - 792000 1150000 - 396000 1150000 - >; - }; - }; - - pwm-leds { - compatible = "pwm-leds"; - - led_red: led-0 { - color = ; - max-brightness = <248>; - default-state = "off"; - pwms = <&pwm2 0 500000>; - }; - - led_white: led-1 { - color = ; - max-brightness = <248>; - default-state = "off"; - pwms = <&pwm3 0 500000>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_gpio_led>; - - led-2 { - color = ; - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - reg_5p0: regulator-5p0 { - compatible = "regulator-fixed"; - regulator-name = "5p0"; - }; - - reg_vin: regulator-vin { - compatible = "regulator-fixed"; - regulator-name = "VIN"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <4500000>; - regulator-always-on; - vin-supply = <®_5p0>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <®_5p0>; - }; - - reg_usb_h2_vbus: regulator-usb-h2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5p0> ; - regulator-always-on; - }; - - reg_vsnvs: regulator-vsnvs { - compatible = "regulator-fixed"; - regulator-name = "VSNVS_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - vin-supply = <®_5p0>; - }; - - reg_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "LCD0 POWER"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_enable>; - gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_dac: regulator-dac { - compatible = "regulator-fixed"; - regulator-name = "vref_dac"; - regulator-min-microvolt = <20000>; - regulator-max-microvolt = <20000>; - vin-supply = <®_5p0> ; - regulator-boot-on; - }; - - reg_sw4: regulator-sw4 { - compatible = "regulator-fixed"; - regulator-name = "SW4_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_5p0>; - }; - - reg_sys: regulator-sys { - compatible = "regulator-fixed"; - regulator-name = "SYS_4V2"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - vin-supply = <®_5p0>; - }; -}; - -®_arm { - vin-supply = <&sw2_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -®_vdd1p1 { - vin-supply = <®_vsnvs>; -}; - -®_vdd2p5 { - vin-supply = <®_vsnvs>; -}; - -®_vdd3p0 { - vin-supply = <®_vsnvs>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; - phy-mode = "rmii"; - phy-supply = <®_sw4>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - smsc,disable-energy-detect; - }; - }; -}; - -&gpu_vg { - status = "disabled"; -}; - -&gpu_2d { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1c_reg: sw1c { - regulator-name = "VDD_SOC (sw1abc)"; - regulator-min-microvolt = <1275000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-name = "VDD_ARM (sw2)"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - compatible = "regulator-fixed"; - regulator-name = "DDR_1V5a"; - regulator-boot-on; - regulator-always-on; - - }; - - sw3b_reg: sw3b { - compatible = "regulator-fixed"; - regulator-name = "DDR_1V5b"; - regulator-boot-on; - regulator-always-on; - - }; - - sw4_reg: sw4 { - regulator-name = "AUX 3V15 (sw4)"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - status = "disabled"; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - lm75: sensor@49 { - compatible = "national,lm75b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm75>; - reg = <0x49>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc: rtc@51 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - eeprom_ext: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - usb3503: usb@8 { - compatible = "smsc,usb3503"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3503>; - reg = <0x08>; - connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ - intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ - initial-mode = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - refclk-frequency = <12000000>; - }; - - exc3000: touchscreen@2a { - compatible = "eeti,exc3000"; - reg = <0x2a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctouch>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - }; - - vcnl4035: light-sensor@60 { - compatible = "vishay,vcnl4035"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_proximity>; - reg = <0x60>; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "idle", "active"; - pinctrl-0 = <&pinctrl_usbh2_idle>; - pinctrl-1 = <&pinctrl_usbh2_active>; - vbus-supply = <®_usb_h2_vbus>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphynop1 { - clocks = <&clks IMX6QDL_CLK_USBPHY1>; - clock-names = "main_clk"; - vcc-supply = <®_usb_h1_vbus>; -}; - -&usbphynop2 { - vcc-supply = <®_usb_h2_vbus>; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - voltage-ranges = <3300 3300>; - vmmc-supply = <®_sw4>; - fsl,wp-controller; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - voltage-ranges = <3300 3300>; - vmmc-supply = <®_sw4>; - fsl,wp-controller; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - fsl,ext-reset-output; - timeout-sec = <10>; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_reset_gpio_led: reset-gpio-led-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_lcd_enable: lcdenablegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */ - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */ - >; - }; - - pinctrl_lm75: lm75grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_proximity: proximitygrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0 - >; - }; - - pinctrl_rtc: rtc-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */ - >; - }; - - pinctrl_ctouch: ctouch-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */ - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh2_idle: usbh2-idle-grp { - fsl,pins = < - MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 - >; - }; - - pinctrl_usbh2_active: usbh2-active-grp { - fsl,pins = < - MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 - >; - }; - - pinctrl_usb3503: usb3503-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 - MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 - >; - }; - - pinctrl_wdog1: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi deleted file mode 100644 index ead83091e193..000000000000 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q-ba16.dtsi" - -/ { - mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22000000>; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "3P3V_wlan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "fsl,imx6q-ba16-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-ba16-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; - - mdio0: mdio-gpio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ - <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ - - #address-cells = <1>; - #size-cells = <0>; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; /* 88e6240*/ - reg = <0>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - switch_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy4: switchphy@4 { - reg = <4>; - interrupt-parent = <&switch>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; - -&ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - status = "okay"; - - m25_eeprom: flash@0 { - compatible = "atmel,at25"; - spi-max-frequency = <10000000>; - size = <0x8000>; - pagesize = <64>; - reg = <0>; - address-width = <16>; - }; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - pca9547: mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - mux1_i2c1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ads7830: ads7830@48 { - compatible = "ti,ads7830"; - reg = <0x48>; - }; - - mma8453: mma8453@1c { - compatible = "fsl,mma8453"; - reg = <0x1c>; - }; - }; - - mux1_i2c2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; - - mpl3115: mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - mux1_i2c3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - mux1_i2c4: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&mclk>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - }; - - mux1_i2c5: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - pca9539: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - P12-hog { - gpio-hog; - gpios = <10 0>; - output-low; - line-name = "PCA9539-P12"; - }; - - P13-hog { - gpio-hog; - gpios = <11 0>; - output-low; - line-name = "PCA9539-P13"; - }; - - P14-hog { - gpio-hog; - gpios = <12 0>; - output-low; - line-name = "PCA9539-P14"; - }; - - P15-hog { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "PCA9539-P15"; - }; - - P16-hog { - gpio-hog; - gpios = <14 0>; - output-low; - line-name = "PCA9539-P16"; - }; - - P17-hog { - gpio-hog; - gpios = <15 0>; - output-low; - line-name = "PCA9539-P17"; - }; - }; - }; - - mux1_i2c6: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - - mux1_i2c7: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - - mux1_i2c8: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&iomuxc { - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - >; - }; -}; - -&pmu { - secure-reg-access; -}; - -&usdhc2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - no-1-8-v; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&pcie { - /* Synopsys, Inc. Device */ - pci_root: root@0,0 { - compatible = "pci16c3,abcd"; - reg = <0x00000000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, - <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, - <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, - <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; -}; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts deleted file mode 100644 index ffb3b8eeae5d..000000000000 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright 2013 CompuLab Ltd. - * - * Author: Valentin Raevsky - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "imx6q.dtsi" - -/ { - model = "CompuLab CM-FX6"; - compatible = "compulab,cm-fx6", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat-led { - label = "Heartbeat"; - gpios = <&gpio2 31 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - awnh387_pwrseq: pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwrseq>; - compatible = "mmc-pwrseq-sd8787"; - powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { - compatible = "regulator-fixed"; - regulator-name = "regulator-pcie-power-on-gpio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - }; - - reg_usb_h1_vbus: usb_h1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: usb_otg_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound-analog { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board analog audio"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "MICIN", "Mic Bias", - "Mic Bias", "Mic Jack"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - sound_master: simple-audio-card,cpu { - sound-dai = <&ssi2>; - system-clock-frequency = <2822400>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8731>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - spdif-in; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_RCLKDIR | - IMX_AUDMUX_V2_PTCR_RCSEL(3 | 0x8) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(3)) - IMX_AUDMUX_V2_PDCR_RXDSEL(3) - >; - }; - - mux-audmux4 { - fsl,audmux-port = <3>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(1) | - IMX_AUDMUX_V2_PTCR_RCLKDIR | - IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(1)) - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&cpu0 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&cpu1 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&cpu2 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&cpu3 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - wm8731: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8731"; - reg = <0x1a>; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059 - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 - >; - }; - - pinctrl_pwrseq: pwrseqgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie_power_on_gpio>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi2 { - assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>, - <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <786432000>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - mmc-pwrseq = <&awnh387_pwrseq>; - non-removable; - /* - * If the OS probes the Bluetooth AMP function advertised on this bus - * but the firmware in place does not support it, the WiFi/BT module - * gets unresponsive. - * Users who configured their OS properly can enable this node to gain - * WiFi and/or plain Bluetooth support. - */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts deleted file mode 100644 index 3e59ebbb3608..000000000000 --- a/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts b/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts deleted file mode 100644 index dab70d1230a2..000000000000 --- a/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad (1.5som)"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts deleted file mode 100644 index 1c7b262e3709..000000000000 --- a/arch/arm/boot/dts/imx6q-cubox-i.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts deleted file mode 100644 index 8bfe6337cd65..000000000000 --- a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer - */ - -#ifndef __DTS_V1__ -#define __DTS_V1__ -/dts-v1/; -#endif - -#include "imx6q.dtsi" -#include "imx6qdl-dfi-fs700-m60.dtsi" - -/ { - model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; - compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts deleted file mode 100644 index d4d57370615d..000000000000 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015-2021 DH electronics GmbH - * Copyright (C) 2018 Marek Vasut - * - * DHCOM iMX6 variant: - * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 - * DHCOM PCB number: 493-300 or newer - * PDK2 PCB number: 516-400 or newer - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-dhcom-som.dtsi" -#include "imx6qdl-dhcom-pdk2.dtsi" - -/ { - model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)"; - compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", - "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts deleted file mode 100644 index 16658b76fc4e..000000000000 --- a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-display5.dtsi" - -&panel { - compatible = "tianma,tm070jdhg30"; -}; - -&ldb { - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi deleted file mode 100644 index 4ab31f2217cd..000000000000 --- a/arch/arm/boot/dts/imx6q-display5.dtsi +++ /dev/null @@ -1,596 +0,0 @@ -/* - * Copyright 2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" - -#include -#include -#include - -/ { - model = "Liebherr (LWN) display5 i.MX6 Quad Board"; - compatible = "lwn,display5", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 5000000 0>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <250>; - enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lvds>; - gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-enable-ramp-delay = <300000>; - }; - - sound { - compatible = "simple-audio-card"; - label = "tfa9879-mono"; - - simple-audio-card,dai-link { - /* DAC */ - format = "i2s"; - bitclock-master = <&dailink_master>; - frame-master = <&dailink_master>; - - dailink_master: cpu { - sound-dai = <&ssi2>; - }; - codec { - sound-dai = <&codec>; - }; - }; - }; - - panel: panel-lvds0 { - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(5) | - IMX_AUDMUX_V2_PTCR_TCSEL(5) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(5) - >; - }; - - mux-aud6 { - fsl,audmux-port = <5>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_RFSEL(8) | - IMX_AUDMUX_V2_PTCR_RCSEL(8) | - IMX_AUDMUX_V2_PTCR_TFSEL(1) | - IMX_AUDMUX_V2_PTCR_TCSEL(1) | - IMX_AUDMUX_V2_PTCR_RFSDIR | - IMX_AUDMUX_V2_PTCR_RCLKDIR | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; - status = "okay"; - - s25fl256s: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - - partition@0 { - label = "SPL (spi)"; - reg = <0x0 0x20000>; - read-only; - }; - partition@1 { - label = "u-boot (spi)"; - reg = <0x20000 0x100000>; - read-only; - }; - partition@2 { - label = "uboot-env (spi)"; - reg = <0x120000 0x10000>; - }; - partition@3 { - label = "uboot-envr (spi)"; - reg = <0x130000 0x10000>; - }; - partition@4 { - label = "linux-recovery (spi)"; - reg = <0x140000 0x800000>; - }; - partition@5 { - label = "swupdate-fitImg (spi)"; - reg = <0x940000 0x400000>; - }; - partition@6 { - label = "swupdate-initramfs (spi)"; - reg = <0xD40000 0x800000>; - }; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðernet_phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - ethernet_phy0: ethernet-phy@0 { - compatible = "marvell,88E1510"; - device_type = "ethernet-phy"; - /* Set LED0 control: */ - /* On - Link, Blink - Activity, Off - No Link */ - marvell,reg-init = <3 0x10 0 0x1011>; - max-speed = <100>; - reg = <0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: tfa9879@6c { - #sound-dai-cells = <0>; - compatible = "nxp,tfa9879"; - reg = <0x6C>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* I2S OUTPUT AUD6*/ - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 - >; - }; - - pinctrl_backlight: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi2_cs: ecspi2csgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 - >; - }; - - pinctrl_ecspi2_flwp: ecspi2flwpgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3_cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 - >; - }; - - pinctrl_ecspi3_flwp: ecspi3flwpgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_lvds: reqlvdsgrp { - fsl,pins = < - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 - >; - }; - - pinctrl_usbh1_vbus: usbh1_vbus_grp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts deleted file mode 100644 index 3815cb660ff7..000000000000 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Data Modul AG - */ - -/dts-v1/; - -#include -#include "imx6q.dtsi" - -/ { - model = "Data Modul eDM-QMX6 Board"; - compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; - - aliases { - gpio7 = &stmpe_gpio1; - gpio8 = &stmpe_gpio2; - stmpe-i2c0 = &stmpe1; - stmpe-i2c1 = &stmpe2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_switch: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_switch"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 12 0>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_host1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_host1_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 0>; - enable-active-high; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-blue { - label = "blue"; - gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-green { - label = "green"; - gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - led-pink { - label = "pink"; - gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led-red { - label = "red"; - gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&ecspi5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash: flash@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - phy-supply = <&vgen2_1v2_eth>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2 - &pinctrl_stmpe1 - &pinctrl_stmpe2 - &pinctrl_pfuze>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - interrupt-parent = <&gpio3>; - interrupts = <20 8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_1v2_eth: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vdd_high_in: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - stmpe1: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <30 0>; - interrupt-parent = <&gpio3>; - vcc-supply = <&sw2_reg>; - vio-supply = <&sw2_reg>; - - stmpe_gpio1: stmpe_gpio { - #gpio-cells = <2>; - compatible = "st,stmpe-gpio"; - }; - }; - - stmpe2: stmpe1601@44 { - compatible = "st,stmpe1601"; - reg = <0x44>; - interrupts = <2 0>; - interrupt-parent = <&gpio5>; - vcc-supply = <&sw2_reg>; - vio-supply = <&sw2_reg>; - - stmpe_gpio2: stmpe_gpio { - #gpio-cells = <2>; - compatible = "st,stmpe-gpio"; - }; - }; - - temp1: ad7414@4c { - compatible = "ad,ad7414"; - reg = <0x4c>; - }; - - temp2: ad7414@4d { - compatible = "ad,ad7414"; - reg = <0x4d>; - }; - - rtc: m41t62@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-dmo-edmqmx6 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5rp-1 { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 - >; - }; - - pinctrl_pfuze: pfuze100grp1 { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 - >; - }; - - pinctrl_stmpe1: stmpe1grp { - fsl,pins = ; - }; - - pinctrl_stmpe2: stmpe2grp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host1>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <8>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts deleted file mode 100644 index 137db38f0d27..000000000000 --- a/arch/arm/boot/dts/imx6q-dms-ba16.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "imx6q-ba16.dtsi" - -/ { - model = "Advantech DMS-BA16"; - compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q"; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22000000>; - }; - - sound { - compatible = "fsl,imx6q-ba16-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-ba16-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - status = "okay"; - - m25_eeprom: flash@0 { - compatible = "atmel,at25256B", "atmel,at25"; - spi-max-frequency = <20000000>; - size = <0x8000>; - pagesize = <64>; - reg = <0>; - address-width = <16>; - }; -}; - -&iomuxc { - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&sys_mclk>; - lrclk-strength = <0x3>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&sata { - fsl,no-spread-spectrum; - fsl,transmit-atten-16ths = <12>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-level-mV = <1133>; - fsl,receive-dpll-mode = <1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/imx6q-ds.dts deleted file mode 100644 index b0a63a133977..000000000000 --- a/arch/arm/boot/dts/imx6q-ds.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2021 Dillon Min -// -// Based on imx6qdl-sabresd.dtsi which is: -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-ds.dtsi" - -/ { - model = "DaSheng i.MX6 Quad Com-9xx Board"; - compatible = "ds,imx6q-sbc", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts deleted file mode 100644 index 0f582a9d4c0e..000000000000 --- a/arch/arm/boot/dts/imx6q-emcon-avari.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-emcon.dtsi" -#include "imx6qdl-emcon-avari.dtsi" - -/ { - model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; - compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts deleted file mode 100644 index 78d941fef5df..000000000000 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ /dev/null @@ -1,518 +0,0 @@ -/* - * Copyright 2016 United Western Technologies. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include -#include - -/ { - model = "Uniwest Evi"; - compatible = "uniwest,imx6q-evi", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_usbh1_vbus: regulator-usbhubreset { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_hubreset>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - panel { - compatible = "sharp,lq101k1ly04"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ecspi1 { - cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; - status = "okay"; - - fpga: fpga@0 { - compatible = "altr,fpga-passive-serial"; - spi-max-frequency = <20000000>; - reg = <0>; - pinctrl-0 = <&pinctrl_fpgaspi>; - nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, - <&gpio4 25 GPIO_ACTIVE_LOW>, - <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>; - status = "okay"; -}; - -&ecspi5 { - cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, - <&gpio1 13 GPIO_ACTIVE_LOW>, - <&gpio1 12 GPIO_ACTIVE_LOW>, - <&gpio2 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; - status = "okay"; - - eeprom: m95m02@1 { - compatible = "st,m95m02", "atmel,at25"; - size = <262144>; - pagesize = <256>; - address-width = <24>; - spi-max-frequency = <5000000>; - reg = <1>; - }; - - pb_rtc: rtc@3 { - compatible = "nxp,rtc-pcf2123"; - spi-max-frequency = <2450000>; - spi-cs-high; - reg = <3>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpminand>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - clock-frequency = <100000>; - scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0x0b>; - sbs,poll-retry-count = <100>; - sbs,i2c-retry-count = <100>; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - status = "okay"; -}; - -&weim { - ranges = <0 0 0x08000000 0x08000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* pwr mcu alert irq */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* remainder ???? */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1cs: ecspi1csgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068 - >; - }; - - pinctrl_ecspi3cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5grp { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1 - MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1 - MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1 - >; - }; - - pinctrl_ecspi5cs: ecspi5csgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_fpgaspi: fpgaspigrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_gpminand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 - >; - }; - - pinctrl_weimcs: weimcsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 - >; - }; - - pinctrl_weimfpga: weimfpgagrp { - fsl,pins = < - /* weim misc */ - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1 - MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1 - MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1 - MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1 - MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1 - /* weim data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - /* weim address */ - MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1 - MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0 - /* usbh1_b OC */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_usbh1_hubreset: usbh1hubresetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts deleted file mode 100644 index 2fda68f9d3f6..000000000000 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2013 Philipp Zabel - -/dts-v1/; -#include -#include -#include "imx6q.dtsi" - -/ { - model = "Zealz GK802"; - compatible = "zealz,imx6q-gk802", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - recovery-button { - label = "recovery"; - gpios = <&gpio3 16 1>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -/* Internal I2C */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ - eeprom: dm2016@51 { - compatible = "sdmc,dm2016"; - reg = <0x51>; - }; -}; - -/* External I2C via HDMI */ -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-gk802 { - pinctrl_hog: hoggrp { - fsl,pins = < - /* Recovery button, active-low */ - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 - /* RTL8192CU enable GPIO, active-low */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - >; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* External USB-A port (USBOTG) */ -&usbotg { - disable-over-current; - status = "okay"; -}; - -/* Internal USB port (USBH1), connected to RTL8192CU */ -&usbh1 { - disable-over-current; - status = "okay"; -}; - -/* External microSD */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* Internal microSD */ -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts deleted file mode 100644 index f80173458e3f..000000000000 --- a/arch/arm/boot/dts/imx6q-gw51xx.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw51xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; - compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts deleted file mode 100644 index 6e1c493c9c8c..000000000000 --- a/arch/arm/boot/dts/imx6q-gw52xx.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw52xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; - compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; -}; - -&ipu2_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; -}; - -&ipu2_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu2_csi1: ipu2_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts deleted file mode 100644 index f13df8e9c8c4..000000000000 --- a/arch/arm/boot/dts/imx6q-gw53xx.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw53xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; - compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; -}; - -&ipu2_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; -}; - -&ipu2_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_csi1>; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu2_csi1: ipu2_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts deleted file mode 100644 index 0ba802b891b5..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Gateworks Ventana GW5400-A"; - compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; - - /* these are used by bootloader for disabling nodes */ - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - led0 = &led0; - led1 = &led1; - led2 = &led2; - ssi0 = &ssi1; - spi0 = &ecspi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "sst,w25q256", "jedec,spi-nor"; - spi-max-frequency = <30000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <&sw4_reg>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts deleted file mode 100644 index d5d46908cf6e..000000000000 --- a/arch/arm/boot/dts/imx6q-gw54xx.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw54xx.dtsi" -#include - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; - compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; - - sound-digital { - compatible = "simple-audio-card"; - simple-audio-card,name = "tda1997x-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&hdmi_receiver>; - }; - }; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; - - hdmi_receiver: hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <&sw4_reg>; - DVDD-supply = <&sw4_reg>; - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same cycle - * which we map to VP[15:08]<->CSI_DATA[19:12] - */ - nxp,vidout-portcfg = - /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; -}; - -&ipu2_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; -}; - -&ipu2_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_csi1>; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi0: ipu1_csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_ipu2_csi1: ipu2_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_tda1997x: tda1997xgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-gw551x.dts b/arch/arm/boot/dts/imx6q-gw551x.dts deleted file mode 100644 index 2c7feeef1b0e..000000000000 --- a/arch/arm/boot/dts/imx6q-gw551x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw551x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; - compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts deleted file mode 100644 index c973b7304225..000000000000 --- a/arch/arm/boot/dts/imx6q-gw552x.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw552x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; - compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw553x.dts b/arch/arm/boot/dts/imx6q-gw553x.dts deleted file mode 100644 index e9c224cea752..000000000000 --- a/arch/arm/boot/dts/imx6q-gw553x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw553x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; - compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw560x.dts b/arch/arm/boot/dts/imx6q-gw560x.dts deleted file mode 100644 index 735f2bbf1439..000000000000 --- a/arch/arm/boot/dts/imx6q-gw560x.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw560x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW560X"; - compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5903.dts b/arch/arm/boot/dts/imx6q-gw5903.dts deleted file mode 100644 index a182e4cb0e6e..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5903.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw5903.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5903"; - compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5904.dts b/arch/arm/boot/dts/imx6q-gw5904.dts deleted file mode 100644 index ca1e2ae3341e..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5904.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw5904.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5904"; - compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5907.dts b/arch/arm/boot/dts/imx6q-gw5907.dts deleted file mode 100644 index b25526ef5886..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5907.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw5907.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; - compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/imx6q-gw5910.dts deleted file mode 100644 index 6aafa2fcee08..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5910.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw5910.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; - compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/imx6q-gw5912.dts deleted file mode 100644 index 4dcbd943cd93..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5912.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw5912.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; - compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/imx6q-gw5913.dts deleted file mode 100644 index 6f511f1665fd..000000000000 --- a/arch/arm/boot/dts/imx6q-gw5913.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw5913.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; - compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts deleted file mode 100644 index 3fe4591e21f5..000000000000 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ /dev/null @@ -1,382 +0,0 @@ -/* - * Copyright (C) 2015 Lucas Stach - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" - -/ { - model = "Auvidea H100"; - compatible = "auvidea,h100", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = &uart2; - }; - - hdmi_osc: hdmi-osc { - compatible = "fixed-clock"; - clock-output-names = "hdmi-osc"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_leds>; - - led0: led-power { - label = "power"; - gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led1: led-stream { - label = "stream"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2: led-rec { - label = "rec"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_hdmi: regulator-hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_reg_hdmi>; - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - regulator-name = "V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbh1_vbus>; - regulator-name = "USB_H1_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbotg_vbus>; - regulator-name = "USB_OTG_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-sgtl5000 { - compatible = "fsl,imx-audio-sgtl5000"; - model = "H100 on-board codec"; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-ext-port = <5>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_i2c1>; - status = "okay"; - - eeprom: eeprom@51 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x51>; - }; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_sgtl5000>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; - - tc358743: tc358743@f { - compatible = "toshiba,tc358743"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_tc358743>; - clocks = <&hdmi_osc>; - clock-names = "refclk"; - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - /* IRQ has a wrong pull resistor which renders it useless */ - - port { - tc358743_out: endpoint { - remote-endpoint = <&mipi_csi2_in>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_i2c2>; - status = "okay"; -}; - -&iomuxc { - h100 { - pinctrl_h100_hdmi: h100-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_h100_i2c1: h100-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_h100_i2c2: h100-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_h100_leds: pinctrl-h100-leds { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - >; - }; - - pinctrl_h100_reg_hdmi: h100-reg-hdmi { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 - >; - }; - - pinctrl_h100_sgtl5000: h100-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_h100_tc358743: h100-tc358743 { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - >; - }; - - pinctrl_h100_uart2: h100-uart2 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_h100_usbotg_id: hummingboard-usbotg-id { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2: h100-usdhc2 { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 - >; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - port { - mipi_csi2_in: endpoint { - remote-endpoint = <&tc358743_out>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_uart2>; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_h100_usdhc2>; - pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts deleted file mode 100644 index c51b4e4fd71e..000000000000 --- a/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts deleted file mode 100644 index e4132d62ffa2..000000000000 --- a/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad (1.5som)"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts deleted file mode 100644 index 8c9e94e648a7..000000000000 --- a/arch/arm/boot/dts/imx6q-hummingboard.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts deleted file mode 100644 index 1998ebfa0fe0..000000000000 --- a/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts b/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts deleted file mode 100644 index d3ad7329cd6d..000000000000 --- a/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Dual/Quad (1.5som)"; - compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard2.dts b/arch/arm/boot/dts/imx6q-hummingboard2.dts deleted file mode 100644 index 5249f53dcdbc..000000000000 --- a/arch/arm/boot/dts/imx6q-hummingboard2.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard2.dtsi" -#include "imx6qdl-hummingboard2-emmc.dtsi" - -/ { - model = "SolidRun HummingBoard2 Dual/Quad"; - compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/imx6q-icore-mipi.dts deleted file mode 100644 index d51745268dbf..000000000000 --- a/arch/arm/boot/dts/imx6q-icore-mipi.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2017 Engicam S.r.l. - * Copyright (C) 2017 Amarula Solutions B.V. - * Author: Jagan Teki - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore-1.5.dtsi" - -/ { - model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&mipi_csi { - status = "okay"; -}; - -&ov5640 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts deleted file mode 100644 index 02aca1e28ce3..000000000000 --- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; - - panel { - compatible = "ampire,am-1280800n3tzqw-t00h"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts deleted file mode 100644 index 241811c52b62..000000000000 --- a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 12 Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; - - panel { - compatible = "koe,tx31d200vm0baa"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - reg = <0>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts deleted file mode 100644 index cf6ba724f497..000000000000 --- a/arch/arm/boot/dts/imx6q-icore-rqs.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2015 Amarula Solutions B.V. - * Copyright (C) 2015 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore-rqs.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; - compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts deleted file mode 100644 index fe28c3cf54c0..000000000000 --- a/arch/arm/boot/dts/imx6q-icore.dts +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c1 { - max11801: touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <30>; - hfront-porch = <30>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <64>; - vsync-len = <20>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi deleted file mode 100644 index 4d6a0c3e8455..000000000000 --- a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2019 (C) Pengutronix, Marco Felsch - */ - -#include "imx6q.dtsi" -#include "imx6qdl-kontron-samx6i.dtsi" -#include - -/ { - model = "Kontron SMARC sAMX6i Quad/Dual"; - compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; -}; - -/* Quad/Dual SoMs have 3 chip-select signals */ -&ecspi4 { - cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, - <&gpio3 29 GPIO_ACTIVE_LOW>, - <&gpio3 25 GPIO_ACTIVE_LOW>; -}; - -&pinctrl_ecspi4 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - - /* SPI4_IMX_CS2# - connected to internal flash */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 - /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 - >; -}; diff --git a/arch/arm/boot/dts/imx6q-kp-tpc.dts b/arch/arm/boot/dts/imx6q-kp-tpc.dts deleted file mode 100644 index 50fbf46d17c2..000000000000 --- a/arch/arm/boot/dts/imx6q-kp-tpc.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; - -#include "imx6q-kp.dtsi" - -/ { - model = "Freescale i.MX6 Qwuad K+P TPC Board"; - compatible = "kiebackpeter,imx6q-tpc", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/imx6q-kp.dtsi deleted file mode 100644 index 091903f53a56..000000000000 --- a/arch/arm/boot/dts/imx6q-kp.dtsi +++ /dev/null @@ -1,434 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; - -#include "imx6q.dtsi" - -#include -#include -#include - -/ { - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <250>; - }; - - beeper { - compatible = "pwm-beeper"; - pwms = <&pwm2 0 500000>; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - lcd_panel: lcd-panel { - compatible = "auo,g070vvn01"; - backlight = <&backlight_lcd>; - power-supply = <®_display>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - label = "led1"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - led-red { - label = "led0"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "sgtl5000-supply"; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_display: regulator-display { - compatible = "regulator-fixed"; - regulator-name = "display-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb_h1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6q-sgtl5000-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCSEL(2) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - fsl,magic-packet; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - }; - - ds1307: rtc@32 { - compatible = "dallas,ds1307"; - reg = <0x32>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - /* sgtl5000 sys_mclk clock routed to CLKO1 */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_flexcan1: can1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts deleted file mode 100644 index 46a4ddedb423..000000000000 --- a/arch/arm/boot/dts/imx6q-logicpd.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2019 Logic PD, Inc. - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6-logicpd-som.dtsi" -#include "imx6-logicpd-baseboard.dtsi" - -/ { - model = "Logic PD i.MX6QD SOM-M3"; - compatible = "logicpd,imx6q-logicpd", "fsl,imx6q"; - - backlight: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 20000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_lcd>; - }; - - panel-lvds0 { - compatible = "okaya,rs800480t-7x0gp"; - power-supply = <®_lcd_reset>; - backlight = <&backlight>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - reg_lcd: regulator-lcd { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_reg>; - compatible = "regulator-fixed"; - regulator-name = "lcd_panel_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3>; - startup-delay-us = <500000>; - }; - - reg_lcd_reset: regulator-lcd-reset { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_reset>; - compatible = "regulator-fixed"; - regulator-name = "nLCD_RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_lcd>; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - touchscreen@26 { - compatible = "ilitek,ili2117"; - reg = <0x26>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - -}; - -&pwm3 { - status = "okay"; -}; - -®_hdmi { - regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ -}; - -&iomuxc { - pinctrl_lcd_reg: lcdreg { - fsl,pins = < - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ - >; - }; - - pinctrl_lcd_reset: lcdreset { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts deleted file mode 100644 index 2c9961333b0a..000000000000 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ /dev/null @@ -1,417 +0,0 @@ -/* - * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include - -/ { - model = "Embest MarS Board i.MX6Dual"; - compatible = "embest,imx6q-marsboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-user1 { - label = "imx6:green:user1"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led-user2 { - label = "imx6:green:user2"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Atheros AR8035 PHY */ - rgmii_phy: ethernet-phy@4 { - reg = <4>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <1000>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&iomuxc { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* RGMII_nRST */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/imx6q-mba6.dtsi deleted file mode 100644 index 0d7be4567291..000000000000 --- a/arch/arm/boot/dts/imx6q-mba6.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -&ecspi5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5_mba6x>; - cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; -}; - -ðphy { - rxdv-skew-ps = <180>; - txen-skew-ps = <120>; - rxd3-skew-ps = <180>; - rxd2-skew-ps = <180>; - rxd1-skew-ps = <180>; - rxd0-skew-ps = <180>; - txd3-skew-ps = <120>; - txd2-skew-ps = <0>; - txd1-skew-ps = <180>; - txd0-skew-ps = <360>; - txc-skew-ps = <1860>; - rxc-skew-ps = <1860>; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { - fsl,pins = < - /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-mba6a.dts b/arch/arm/boot/dts/imx6q-mba6a.dts deleted file mode 100644 index 349a08605a5e..000000000000 --- a/arch/arm/boot/dts/imx6q-mba6a.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6q-tqma6a.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6a.dtsi" -#include "imx6q-mba6.dtsi" - -/ { - model = "TQ TQMa6Q on MBa6x"; - compatible = "tq,imx6q-mba6x-a", "tq,mba6a", - "tq,imx6q-tqma6q-a", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-mba6b.dts b/arch/arm/boot/dts/imx6q-mba6b.dts deleted file mode 100644 index 02c9f3e91b8f..000000000000 --- a/arch/arm/boot/dts/imx6q-mba6b.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6q-tqma6b.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6b.dtsi" -#include "imx6q-mba6.dtsi" - -/ { - model = "TQ TQMa6Q on MBa6x"; - compatible = "tq,imx6q-mba6x-b", "tq,mba6b", - "tq,imx6q-tqma6q-b", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts deleted file mode 100644 index f08b37010291..000000000000 --- a/arch/arm/boot/dts/imx6q-mccmon6.dts +++ /dev/null @@ -1,471 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; - -#include "imx6q.dtsi" - -#include -#include - -/ { - model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; - compatible = "lwn,mccmon6", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <50>; - enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lvds>; - gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; - status = "okay"; - - s25sl032p: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - ranges = <0 0 0x08000000 0x08000000>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - use-advanced-sector-protection; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_backlight: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3_cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 - >; - }; - - pinctrl_ecspi3_flwp: ecspi3flwpgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_lvds: reqlvdsgrp { - fsl,pins = < - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor: weimnorgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts deleted file mode 100644 index 03bec0c53063..000000000000 --- a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6_max.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6_MAX Board"; - compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts deleted file mode 100644 index eb4eecb6ed22..000000000000 --- a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6_som2.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board"; - compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts deleted file mode 100644 index 435445a34ad0..000000000000 --- a/arch/arm/boot/dts/imx6q-nitrogen6x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6x.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6x Board"; - compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts deleted file mode 100644 index a7d5a68110fc..000000000000 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ /dev/null @@ -1,803 +0,0 @@ -/* - * Copyright 2015 Sutajio Ko-Usagi PTE LTD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include -#include - -/ { - model = "Kosagi Novena Dual/Quad"; - compatible = "kosagi,imx6q-novena", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 10000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_novena>; - power-supply = <®_lvds_lcd>; - brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; - default-brightness-level = <12>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys_novena>; - - user-button { - label = "User Button"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - lid-event { - label = "Lid"; - gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_novena>; - - led-heartbeat { - label = "novena:white:panel"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - panel: panel { - compatible = "innolux,n133hse-ea1"; - backlight = <&backlight>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_audio_codec: regulator-audio-codec { - compatible = "regulator-fixed"; - regulator-name = "es8328-power"; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <400000>; - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_display: regulator-display { - compatible = "regulator-fixed"; - regulator-name = "lcd-display-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_lcd: regulator-lvds-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd-lvds-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pcie-bus-power"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sata: regulator-sata { - compatible = "regulator-fixed"; - regulator-name = "sata-power"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <10000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-es8328"; - model = "imx-audio-es8328"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-amp-supply = <®_audio_codec>; - jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>; - audio-routing = - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Speaker", "audio-amp", - "Headphone", "ROUT1", - "Headphone", "LOUT1", - "LINPUT1", "Mic Jack", - "RINPUT1", "Mic Jack", - "Mic Jack", "Mic Bias"; - mux-int-port = <0x1>; - mux-ext-port = <0x3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_novena>; - status = "okay"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3_novena>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_novena>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txen-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <3000>; - txd1-skew-ps = <3000>; - txd2-skew-ps = <3000>; - txd3-skew-ps = <3000>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_novena>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_novena>; - status = "okay"; - - accel: mma8452@1c { - compatible = "fsl,mma8452"; - reg = <0x1c>; - }; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sbs_battery: bq20z75@b { - compatible = "sbs,sbs-battery"; - reg = <0x0b>; - sbs,i2c-retry-count = <50>; - }; - - touch: stmpe811@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe_novena>; - vio-supply = <®_3p3v>; - vcc-supply = <®_3p3v>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_novena>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - reg_sw1a: sw1a { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - reg_sw1c: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw2: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw3a: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw3b: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw4: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_swbst: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - }; - - reg_snvs: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vref: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen2: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen3: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vgen4: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_novena>; - status = "okay"; - - codec: es8328@11 { - compatible = "everest,es8328"; - reg = <0x11>; - DVDD-supply = <®_audio_codec>; - AVDD-supply = <®_audio_codec>; - PVDD-supply = <®_audio_codec>; - HPVDD-supply = <®_audio_codec>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sound_novena>; - clocks = <&clks IMX6QDL_CLK_CKO1>; - assigned-clocks = <&clks IMX6QDL_CLK_CKO>, - <&clks IMX6QDL_CLK_CKO1_SEL>, - <&clks IMX6QDL_CLK_PLL4_AUDIO>, - <&clks IMX6QDL_CLK_CKO1>; - assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, - <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, - <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_CKO1_PODF>; - assigned-clock-rates = <0 0 722534400 22579200>; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_novena>; - linux,keymap = < - MATRIX_KEY(1, 1, KEY_CONFIG) - >; - status = "okay"; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - fsl,panel = <&panel>; - status = "okay"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_novena>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - status = "okay"; -}; - -&sata { - target-supply = <®_sata>; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <8>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_novena>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_novena>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_novena>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_novena>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_swbst>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_novena>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_novena>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux_novena: audmuxgrp-novena { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight_novena: backlightgrp-novena { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 - >; - }; - - pinctrl_ecspi3_novena: ecspi3grp-novena { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet_novena: enetgrp-novena { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* Ethernet reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 - >; - }; - - pinctrl_fpga_gpio: fpgagpiogrp-novena { - fsl,pins = < - /* FPGA power */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 - /* Reset */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - /* FPGA GPIOs */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 - >; - }; - - pinctrl_fpga_eim: fpgaeimgrp-novena { - fsl,pins = < - /* FPGA power */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 - /* Reset */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - /* FPGA GPIOs */ - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1 - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1 - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1 - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1 - MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1 - >; - }; - - pinctrl_gpio_keys_novena: gpiokeysgrp-novena { - fsl,pins = < - /* User button */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - /* PCIe Wakeup */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0 - /* Lid switch */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - >; - }; - - pinctrl_hdmi_novena: hdmigrp-novena { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 - >; - }; - - pinctrl_i2c1_novena: i2c1grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_novena: i2c2grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_novena: i2c3grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp_novena: kppgrp-novena { - fsl,pins = < - /* Front panel button */ - MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 - /* Fake column driver, not connected */ - MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1 - >; - }; - - pinctrl_leds_novena: ledsgrp-novena { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 - >; - }; - - pinctrl_pcie_novena: pciegrp-novena { - fsl,pins = < - /* Reset */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 - /* Power On */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - /* Wifi kill */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 - >; - }; - - pinctrl_sata_novena: satagrp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 - >; - }; - - pinctrl_senoko_novena: senokogrp-novena { - fsl,pins = < - /* Senoko IRQ line */ - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 - /* Senoko reset line */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 - >; - }; - - pinctrl_sound_novena: soundgrp-novena { - fsl,pins = < - /* Audio power regulator */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 - /* Headphone plug */ - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_stmpe_novena: stmpegrp-novena { - fsl,pins = < - /* Touchscreen interrupt */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - >; - }; - - pinctrl_uart2_novena: uart2grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_novena: uart3grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4_novena: uart4grp-novena { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg_novena: usbotggrp-novena { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2_novena: usdhc2grp-novena { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - /* Write protect */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - /* Card detect */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 - >; - }; - - pinctrl_usdhc3_novena: usdhc3grp-novena { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts deleted file mode 100644 index 322f071d972f..000000000000 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" -#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" -#include "imx6qdl-phytec-mira-peb-av-02.dtsi" -#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; - compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&m25p80 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usdhc4 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts deleted file mode 100644 index 3f13726c8058..000000000000 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" -#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" -#include "imx6qdl-phytec-mira-peb-av-02.dtsi" -#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; - compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&m25p80 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts deleted file mode 100644 index affe30b02d5a..000000000000 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -/dts-v1/; -#include "imx6q-phytec-pfla02.dtsi" -#include "imx6qdl-phytec-pbab01.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; - compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi deleted file mode 100644 index 500944bd2a05..000000000000 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include "imx6q.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/imx6q-pico-dwarf.dts deleted file mode 100644 index 479a63ed42af..000000000000 --- a/arch/arm/boot/dts/imx6q-pico-dwarf.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-pico-pi.dtsi" - -/ { - model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; - compatible = "technexion,imx6q-pico-dwarf", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/imx6q-pico-hobbit.dts deleted file mode 100644 index b767131068f5..000000000000 --- a/arch/arm/boot/dts/imx6q-pico-hobbit.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-pico-hobbit.dtsi" - -/ { - model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; - compatible = "technexion,imx6q-pico-hobbit", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/imx6q-pico-nymph.dts deleted file mode 100644 index e8ad4c12b263..000000000000 --- a/arch/arm/boot/dts/imx6q-pico-nymph.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-pico-pi.dtsi" - -/ { - model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; - compatible = "technexion,imx6q-pico-nymph", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/imx6q-pico-pi.dts deleted file mode 100644 index cc2394ddad6c..000000000000 --- a/arch/arm/boot/dts/imx6q-pico-pi.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-pico-pi.dtsi" - -/ { - model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; - compatible = "technexion,imx6q-pico-pi", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h deleted file mode 100644 index e40409d04b97..000000000000 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ /dev/null @@ -1,1044 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6Q_PINFUNC_H -#define __DTS_IMX6Q_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 -#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 -#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 -#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6Q_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts deleted file mode 100644 index 109b46a22b5e..000000000000 --- a/arch/arm/boot/dts/imx6q-pistachio.dts +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright (C) 2017 NutsBoard.Org - * - * Author: Wig Cheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "imx6q.dtsi" - -/ { - model = "NutsBoard i.MX6 Quad Pistachio board"; - compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - wlan_en_reg: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-power { - label = "Power Button"; - gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; - brightness-levels = < - 0 /*1 2 3 4 5 6*/ 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <94>; - status = "okay"; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - ar1021@4d { - compatible = "microchip,ar1021-i2c"; - reg = <0x4d>; - interrupt-parent = <&gpio6>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/ - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/ - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/ - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/ - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00 - >; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - fsl,dte-mode; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <0x5>; -}; - -&usbphy2 { - fsl,tx-d-cal = <0x5>; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - keep-power-in-suspend; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <&wlan_en_reg>; - no-1-8-v; - keep-power-in-suspend; - non-removable; - cap-power-off-card; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&wdog1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/imx6q-prti6q.dts deleted file mode 100644 index d8fa83effd63..000000000000 --- a/arch/arm/boot/dts/imx6q-prti6q.dts +++ /dev/null @@ -1,543 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-prti6q.dtsi" -#include -#include - -/ { - model = "Protonic PRTI6Q board"; - compatible = "prt,prti6q", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xf0000000>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <1>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - can_osc: can-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-debug0 { - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-debug1 { - function = LED_FUNCTION_SD; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - enable-active-high; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "regulator-WL12xx"; - startup-delay-us = <70000>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - bitclock-master; - frame-master; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - spdif-out; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can3>; - clocks = <&can_osc>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <5000000>; - }; - - adc@1 { - compatible = "ti,adc128s052"; - reg = <1>; - spi-max-frequency = <2000000>; - vref-supply = <®_3v3>; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; -}; - -/* DDC */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* can2_l */ - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - /* can2_h */ - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - /* can1_l */ - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - /* can1_h */ - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - vmmc-supply = <®_wifi>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - wifi { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi>; - interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <19200000>; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008 - >; - }; - - pinctrl_can3: can3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 - >; - }; - - pinctrl_ecspi2_cs: ecspi2csgrp { - fsl,pins = < - /* ADC128S022 CS */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - /* NOTE: DDC is done via I2C2, so DON'T - * configure DDC pins for HDMI! - */ - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - /* DDC */ - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg_id: usbotgidgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - /* WL12xx IRQ */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 - >; - }; - - pinctrl_wifi_npd: wifinpd { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts deleted file mode 100644 index 792b8903d345..000000000000 --- a/arch/arm/boot/dts/imx6q-prtwd2.dts +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2018 Protonic Holland - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-prti6q.dtsi" -#include - -/ { - model = "Protonic WD2 board"; - compatible = "prt,prtwd2", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - clk50m_phy: phy-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; - }; - - /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ - i2c { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <20>; /* ~10 kHz */ - i2c-gpio,scl-output-only; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; - status = "okay"; -}; - -&clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clk50m_phy>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - status = "okay"; - - fixed-link { - speed = <100>; - pause; - full-duplex; - }; -}; - -&i2c3 { - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* V in */ - channel@4 { - reg = <4>; - ti,gain = <1>; - ti,datarate = <3>; - }; - - /* I charge */ - channel@5 { - reg = <5>; - ti,gain = <1>; - ti,datarate = <3>; - }; - - /* V bus */ - channel@6 { - reg = <6>; - ti,gain = <1>; - ti,datarate = <3>; - }; - - /* nc */ - channel@7 { - reg = <7>; - ti,gain = <1>; - ti,datarate = <3>; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&usdhc2_wifi_pwrseq>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth_chg>; - - pinctrl_can1phy: can1phy { - fsl,pins = < - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* MX6QDL_ENET_PINGRP4 */ - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - /* Phy reset */ - MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 - /* nINTRP */ - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0 - MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0 - >; - }; - - pinctrl_usb_eth_chg: usbethchggrp { - fsl,pins = < - /* USB charging control */ - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_wifi_npd: wifinpd { - fsl,pins = < - /* WL_REG_ON */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts deleted file mode 100644 index 271f4b2d9b9f..000000000000 --- a/arch/arm/boot/dts/imx6q-rex-pro.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-rex.dtsi" - -/ { - model = "Rex Pro i.MX6 Quad Board"; - compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&ecspi3 { - flash: flash@0 { - compatible = "sst,sst25vf032b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts deleted file mode 100644 index 6e981a3e0a83..000000000000 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Automotive Board"; - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts deleted file mode 100644 index 7c6a2f234ccb..000000000000 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-sabrelite.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Lite Board"; - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; - -&ipu1_csi1_from_mipi_vc1 { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts deleted file mode 100644 index eec944673c0b..000000000000 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Smart Device Board"; - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; - -&ipu1_csi1_from_mipi_vc1 { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/arch/arm/boot/dts/imx6q-savageboard.dts b/arch/arm/boot/dts/imx6q-savageboard.dts deleted file mode 100644 index 717ac62fc2cf..000000000000 --- a/arch/arm/boot/dts/imx6q-savageboard.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2017 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-savageboard.dtsi" - -/ { - model = "Poslab SavageBoard Quad"; - compatible = "poslab,imx6q-savageboard", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts deleted file mode 100644 index 9054c1d58b9d..000000000000 --- a/arch/arm/boot/dts/imx6q-sbc6x.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Pavel Machek - */ - -/dts-v1/; -#include "imx6q.dtsi" - -/ { - model = "MicroSys sbc6x board"; - compatible = "microsys,sbc6x", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&iomuxc { - imx6q-sbc6x { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts b/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts deleted file mode 100644 index ff97d22eb09f..000000000000 --- a/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-skov-cpu.dtsi" -#include "imx6qdl-skov-cpu-revc.dtsi" -#include "imx6qdl-skov-revc-lt2.dtsi" - -/ { - model = "SKOV IMX6 CPU QuadCore"; - compatible = "skov,imx6q-skov-revc-lt2", "fsl,imx6q"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - /* internal 22 k pull up required */ - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001f878 - /* internal 22 k pull up required */ - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001f878 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt6.dts b/arch/arm/boot/dts/imx6q-skov-revc-lt6.dts deleted file mode 100644 index 3e3b36ad362a..000000000000 --- a/arch/arm/boot/dts/imx6q-skov-revc-lt6.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-skov-cpu.dtsi" -#include "imx6qdl-skov-cpu-revc.dtsi" - -/ { - model = "SKOV IMX6 CPU QuadCore"; - compatible = "skov,imx6q-skov-revc-lt6", "fsl,imx6q"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; - pwms = <&pwm2 0 20000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <17>; - default-brightness-level = <8>; - power-supply = <®_24v0>; - }; - - display { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel { - compatible = "logictechno,lttd800480070-l6wh-rt"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display0_out>; - }; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - /* internal 22 k pull up required */ - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 - /* internal 22 k pull up required */ - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts deleted file mode 100644 index a3f247c722b4..000000000000 --- a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-skov-cpu.dtsi" - -/ { - model = "SKOV IMX6 CPU QuadCore"; - compatible = "skov,imx6q-skov-reve-mi1010ait-1cp1", "fsl,imx6q"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; - pwms = <&pwm2 0 20000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <17>; - default-brightness-level = <8>; - power-supply = <®_24v0>; - }; - - panel { - compatible = "multi-inno,mi1010ait-1cp"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio3>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1280>; - touchscreen-size-y = <800>; - wakeup-source; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&iomuxc { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - /* external 1 k pull up */ - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x40010878 - /* external 1 k pull up */ - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x40010878 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - /* internal 22 k pull up required */ - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 - /* internal 22 k pull up required */ - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - /* external 10 k pull up */ - /* CTP_INT */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - /* CTP_RST */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - >; - }; -}; - -®_tft_vcom { - regulator-min-microvolt = <3160000>; - regulator-max-microvolt = <3160000>; - voltage-table = <3160000 73>; -}; diff --git a/arch/arm/boot/dts/imx6q-solidsense.dts b/arch/arm/boot/dts/imx6q-solidsense.dts deleted file mode 100644 index 0e6a325df363..000000000000 --- a/arch/arm/boot/dts/imx6q-solidsense.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" -#include "imx6qdl-solidsense.dtsi" - -/ { - model = "SolidRun SolidSense Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,solidsense/q", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts deleted file mode 100644 index 2f576e2ce73f..000000000000 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2014 Soeren Moch - -/dts-v1/; - -#include "imx6q.dtsi" -#include -#include - -/ { - model = "TBS2910 Matrix ARM mini PC"; - compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; - - chosen { - stdout-path = &uart1; - }; - - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc3; - mmc2 = &usdhc4; - /delete-property/ mmc3; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - fan { - compatible = "gpio-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_fan>; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 3000 1>; - }; - - ir_recv { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-blue { - label = "blue_status_led"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-sgtl5000 { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "On-board Codec"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@4 { - reg = <4>; - qca,clk-out-frequency = <125000000>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: sgtl5000@a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc: rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <16>; - fsl,receive-eq-mdB = <3000>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_5p0v>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 - >; - }; - - pinctrl_gpio_fan: gpiofangrp { - fsl,pins = < - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/imx6q-tqma6a.dtsi deleted file mode 100644 index ab4c07c13a13..000000000000 --- a/arch/arm/boot/dts/imx6q-tqma6a.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel - */ - -#include "imx6q.dtsi" -#include "imx6qdl-tqma6a.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/imx6q-tqma6b.dtsi deleted file mode 100644 index 7224c376c318..000000000000 --- a/arch/arm/boot/dts/imx6q-tqma6b.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - */ - -#include "imx6q.dtsi" -#include "imx6qdl-tqma6b.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts deleted file mode 100644 index dce1e8671ebe..000000000000 --- a/arch/arm/boot/dts/imx6q-ts4900.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-ts4900.dtsi" - -/ { - model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; - compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts deleted file mode 100644 index 570bd3c309a6..000000000000 --- a/arch/arm/boot/dts/imx6q-ts7970.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-ts7970.dtsi" - -/ { - model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; - compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts deleted file mode 100644 index ac3050a835e5..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&backlight { - pwms = <&pwm2 0 500000 0>; - /delete-property/ turn-on-delay-ms; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&kpp { - status = "disabled"; -}; - -&lcd_panel { - compatible = "edt,etm0700g0edh6"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts deleted file mode 100644 index 4ee860b626ff..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010/-1030 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ipu2 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts deleted file mode 100644 index a773f252816c..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&backlight { - pwms = <&pwm2 0 500000 0>; - /delete-property/ turn-on-delay-ms; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&kpp { - status = "disabled"; -}; - -&lcd_panel { - compatible = "edt,etm0700g0edh6"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts deleted file mode 100644 index 0a4daec8d3ad..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1020 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts deleted file mode 100644 index 9ffbb0fe7df8..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q-tx6q-1036.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/imx6q-tx6q-1036.dts deleted file mode 100644 index cb2fcb4896c6..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1036.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1036 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts deleted file mode 100644 index d43a5d8f1749..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q-tx6q-1010.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts deleted file mode 100644 index f7b0acb65352..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-1110.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lvds.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1110/-1130 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ipu2 { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts deleted file mode 100644 index 387edf2b3f96..000000000000 --- a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2016-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q-tx6q-1110.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts deleted file mode 100644 index 52e9f4a211d0..000000000000 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-udoo.dtsi" - -/ { - model = "Udoo i.MX6 Quad Board"; - compatible = "udoo,imx6q-udoo", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts deleted file mode 100644 index ad59b23ef27a..000000000000 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright 2013 CompuLab Ltd. - * Copyright 2016 Christopher Spinrath - * - * Based on the devicetree distributed with the vendor kernel for the - * Utilite Pro: - * Copyright 2013 CompuLab Ltd. - * Author: Valentin Raevsky - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "imx6q-cm-fx6.dts" - -/ { - model = "CompuLab Utilite Pro"; - compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q"; - - aliases { - ethernet1 = ð1; - rtc0 = &em3027; - rtc1 = &snvs_rtc; - }; - - encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <¶llel_display_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-power { - label = "Power Button"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hpd>; - type = "a"; - ddc-i2c-bus = <&i2c_dvi_ddc>; - hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - i2cmux { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1mux>; - #address-cells = <1>; - #size-cells = <0>; - - mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c1>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - em3027: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - }; - - i2c_dvi_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - parallel-display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - - interface-pix-fmt = "rgb24"; - - port@0 { - reg = <0>; - - parallel_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - parallel_display_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; - }; -}; - -/* - * A single IPU is not able to drive both display interfaces available on the - * Utilite Pro at high resolution due to its bandwidth limitation. Since the - * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the - * SoC-internal Designware HDMI encoder forcing the latter to be connected to - * IPU2 instead of IPU1. - */ -/delete-node/&ipu1_di0_hdmi; -/delete-node/&hdmi_mux_0; -/delete-node/&ipu1_di1_hdmi; -/delete-node/&hdmi_mux_1; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmicec>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_hdmicec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hpd: hpdgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1mux: i2c1muxgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <¶llel_display_in>; -}; - -&pcie { - pcie@0,0 { - reg = <0x000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - /* non-removable i211 ethernet card */ - eth1: intel,i211@pcie0,0 { - reg = <0x010000 0 0 0 0>; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - no-1-8-v; - broken-cd; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts deleted file mode 100644 index 2290c1237634..000000000000 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Support for Variscite DART-MX6 Carrier-board - * - * Copyright 2017 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-var-dart.dtsi" -#include - -/ { - model = "Variscite DART-MX6 Carrier-board"; - compatible = "variscite,dt6customboard", "fsl,imx6q"; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 248>; - default-brightness-level = <7>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-back { - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Key Back"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - - key-home { - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Key Home"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - - key-menu { - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Key Menu"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led1 { - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - panel1: lvds-panel { - compatible = "sgd,gktw70sdae4se", "panel-lvds"; - backlight = <&backlight_lvds>; - width-mm = <153>; - height-mm = <86>; - label = "gktw70sdae4se"; - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <32000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <39>; - hfront-porch = <39>; - vback-porch = <29>; - vfront-porch = <13>; - hsync-len = <47>; - vsync-len = <2>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - reg_usb_h1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "dt6-customboard-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&clks IMX6QDL_CLK_CKO>; - }; - }; -}; - -&can1 { - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, - <&gpio4 10 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - status = "okay"; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-inverted-y; - wakeup-source; - }; - - rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm2 { - #pwm-cells = <2>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usdhc2 { - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts deleted file mode 100644 index dd91aff3f9e2..000000000000 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-vicut1.dtsi" -#include "imx6qdl-vicut1-12inch.dtsi" - -/ { - model = "Kverneland UT1Q Board"; - compatible = "kvg,vicut1q", "fsl,imx6q"; -}; diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts deleted file mode 100644 index f6ccbecff92c..000000000000 --- a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board rev B1"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts deleted file mode 100644 index 55331021d80c..000000000000 --- a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revd1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board revD1"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts deleted file mode 100644 index 0be548beef86..000000000000 --- a/arch/arm/boot/dts/imx6q-wandboard.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revc1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/imx6q-yapp4-crux.dts deleted file mode 100644 index bddf3822ebf7..000000000000 --- a/arch/arm/boot/dts/imx6q-yapp4-crux.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Crux i.MX6Quad board"; - compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xf0000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled_1305 { - status = "okay"; -}; - -&oled_1309 { - status = "okay"; -}; - -®_pu { - regulator-always-on; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&uart2 { - status = "disabled"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts deleted file mode 100644 index ec6651ba4ba2..000000000000 --- a/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6dl-yapp43-common.dtsi" - -/ { - model = "Y Soft IOTA Pegasus i.MX6Quad board"; - compatible = "ysoft,imx6q-yapp4-pegasus", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xf0000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled_1305 { - status = "okay"; -}; - -&oled_1309 { - status = "okay"; -}; - -®_pu { - regulator-always-on; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts deleted file mode 100644 index a1c5e69d81ba..000000000000 --- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2016-2017 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-zii-rdu2.dtsi" - -/ { - model = "ZII RDU2 Board"; - compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi deleted file mode 100644 index df86049a695b..000000000000 --- a/arch/arm/boot/dts/imx6q.dtsi +++ /dev/null @@ -1,553 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include -#include "imx6q-pinfunc.h" -#include "imx6qdl.dtsi" - -/ { - aliases { - ipu1 = &ipu2; - spi4 = &ecspi5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - }; - - soc: soc { - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; - ranges = <0 0x00900000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips1: bus@2000000 { /* AIPS1 */ - spba-bus@2000000 { - ecspi5: spi@2018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02018000 0x4000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6Q_CLK_ECSPI5>, - <&clks IMX6Q_CLK_ECSPI5>; - clock-names = "ipg", "per"; - dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - }; - - sata: sata@2200000 { - compatible = "fsl,imx6q-ahci"; - reg = <0x02200000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SATA>, - <&clks IMX6QDL_CLK_SATA_REF_100M>, - <&clks IMX6QDL_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; - status = "disabled"; - }; - - gpu_vg: gpu@2204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - #cooling-cells = <2>; - }; - - ipu2: ipu@2800000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02800000 0x400000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 4>; - - ipu2_csi0: port@0 { - reg = <0>; - - ipu2_csi0_from_mipi_vc2: endpoint { - remote-endpoint = <&mipi_vc2_to_ipu2_csi0>; - }; - }; - - ipu2_csi1: port@1 { - reg = <1>; - - ipu2_csi1_from_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>; - }; - }; - - ipu2_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu2_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu2_di0_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_2>; - }; - - ipu2_di0_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_2>; - }; - - ipu2_di0_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_2>; - }; - - ipu2_di0_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_2>; - }; - }; - - ipu2_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu2_di1_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_3>; - }; - - ipu2_di1_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_3>; - }; - - ipu2_di1_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_3>; - }; - - ipu2_di1_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_3>; - }; - }; - }; - }; - - capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; - }; -}; - -&gpio1 { - gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, - <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, - <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, - <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, - <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, - <&iomuxc 22 116 10>; -}; - -&gpio2 { - gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, - <&iomuxc 31 44 1>; -}; - -&gpio3 { - gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; -}; - -&gpio4 { - gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; -}; - -&gpio5 { - gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, - <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; -}; - -&gpio6 { - gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, - <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, - <&iomuxc 31 86 1>; -}; - -&gpio7 { - gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; -}; - -&gpr { - ipu1_csi0_mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu1_csi0_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu1_csi0_mux_from_parallel_sensor: endpoint { - }; - }; - - port@2 { - reg = <2>; - - ipu1_csi0_mux_to_ipu1_csi0: endpoint { - remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; - }; - }; - }; - - ipu2_csi1_mux { - compatible = "video-mux"; - mux-controls = <&mux 1>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu2_csi1_mux_from_mipi_vc3: endpoint { - remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu2_csi1_mux_from_parallel_sensor: endpoint { - }; - }; - - port@2 { - reg = <2>; - - ipu2_csi1_mux_to_ipu2_csi1: endpoint { - remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>; - }; - }; - }; -}; - -&hdmi { - compatible = "fsl,imx6q-hdmi"; - - ports { - port@2 { - reg = <2>; - - hdmi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_hdmi>; - }; - }; - - port@3 { - reg = <3>; - - hdmi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_hdmi>; - }; - }; - }; -}; - -&iomuxc { - compatible = "fsl,imx6q-iomuxc"; -}; - -&ipu1_csi1 { - ipu1_csi1_from_mipi_vc1: endpoint { - remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; - }; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; - - lvds-channel@0 { - port@2 { - reg = <2>; - - lvds0_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds0>; - }; - }; - - port@3 { - reg = <3>; - - lvds0_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - port@2 { - reg = <2>; - - lvds1_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds1>; - }; - }; - - port@3 { - reg = <3>; - - lvds1_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds1>; - }; - }; - }; -}; - -&mipi_csi { - port@1 { - reg = <1>; - - mipi_vc0_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; - }; - }; - - port@2 { - reg = <2>; - - mipi_vc1_to_ipu1_csi1: endpoint { - remote-endpoint = <&ipu1_csi1_from_mipi_vc1>; - }; - }; - - port@3 { - reg = <3>; - - mipi_vc2_to_ipu2_csi0: endpoint { - remote-endpoint = <&ipu2_csi0_from_mipi_vc2>; - }; - }; - - port@4 { - reg = <4>; - - mipi_vc3_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>; - }; - }; -}; - -&mipi_dsi { - ports { - port@2 { - reg = <2>; - - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; - }; - }; - - port@3 { - reg = <3>; - - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; - }; - }; - }; -}; - -&mux { - mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */ - <0x04 0x00100000>, /* MIPI_IPU2_MUX */ - <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ - <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ - <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ - <0x28 0x00000003>, /* DCIC1_MUX_CTL */ - <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ -}; - -&vpu { - compatible = "fsl,imx6q-vpu", "cnm,coda960"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi deleted file mode 100644 index 4cc965277c52..000000000000 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ /dev/null @@ -1,1371 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -#include -#include - -/ { - model = "Toradex Apalis iMX6Q/D Module"; - compatible = "toradex,apalis_imx6q", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - power-supply = <®_module_3v3>; - pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - clk_ov5640_osc: clk-ov5640-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-wakeup { - debounce-interval = <10>; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = ; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel_dpi: panel-dpi { - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - status = "disabled"; - - port { - lvds_panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3"; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_AUDIO"; - }; - - reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "DOVDD/DVDD_1.8V"; - /* Note: The CSI module uses on-board 3.3V_SW supply */ - vin-supply = <®_module_3v3>; - }; - - reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <2800000>; - regulator-min-microvolt = <2800000>; - regulator-name = "AVDD/AFVDD_2.8V"; - /* Note: The CSI module uses on-board 3.3V_SW supply */ - vin-supply = <®_module_3v3>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb_otg_vbus"; - status = "disabled"; - }; - - /* on module USB hub */ - reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb_host_vbus_hub"; - startup-delay-us = <2000>; - status = "okay"; - }; - - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb_host_vbus"; - vin-supply = <®_usb_host_vbus_hub>; - status = "disabled"; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - audio-codec = <&codec>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - model = "imx6q-apalis-sgtl5000"; - mux-ext-port = <4>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; - - sound_spdif: sound-spdif { - compatible = "fsl,imx-audio-spdif"; - spdif-controller = <&spdif>; - spdif-in; - spdif-out; - model = "imx-spdif"; - status = "disabled"; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_flexcan1_default>; - pinctrl-1 = <&pinctrl_flexcan1_sleep>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_flexcan2_default>; - pinctrl-1 = <&pinctrl_flexcan2_sleep>; - status = "disabled"; -}; - -&clks { - fsl,pmic-stby-poweroff; -}; - -/* Apalis SPI1 */ -&ecspi1 { - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "disabled"; -}; - -/* Apalis SPI2 */ -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "disabled"; -}; - -&gpio1 { - gpio-line-names = "MXM3_84", - "MXM3_4", - "MXM3_15/GPIO7", - "MXM3_96", - "MXM3_37", - "", - "MXM3_17/GPIO8", - "MXM3_14", - "MXM3_12", - "MXM3_2", - "MXM3_184", - "MXM3_180", - "MXM3_178", - "MXM3_176", - "MXM3_188", - "MXM3_186", - "MXM3_160", - "MXM3_162", - "MXM3_150", - "MXM3_144", - "MXM3_154", - "MXM3_146", - "", - "", - "MXM3_72"; -}; - -&gpio2 { - gpio-line-names = "MXM3_148", - "MXM3_152", - "MXM3_156", - "MXM3_158", - "MXM3_1/GPIO1", - "MXM3_3/GPIO2", - "MXM3_5/GPIO3", - "MXM3_7/GPIO4", - "MXM3_95", - "MXM3_6", - "MXM3_8", - "MXM3_123", - "MXM3_126", - "MXM3_128", - "MXM3_130", - "MXM3_132", - "MXM3_253", - "MXM3_251", - "MXM3_283", - "MXM3_281", - "MXM3_279", - "MXM3_277", - "MXM3_243", - "MXM3_235", - "MXM3_231", - "MXM3_229", - "MXM3_233", - "MXM3_198", - "MXM3_275", - "MXM3_273", - "MXM3_207", - "MXM3_122"; -}; - -&gpio3 { - gpio-line-names = "MXM3_271", - "MXM3_269", - "MXM3_301", - "MXM3_299", - "MXM3_297", - "MXM3_295", - "MXM3_293", - "MXM3_291", - "MXM3_289", - "MXM3_287", - "MXM3_249", - "MXM3_247", - "MXM3_245", - "MXM3_286", - "MXM3_239", - "MXM3_35", - "MXM3_205", - "MXM3_203", - "MXM3_201", - "MXM3_116", - "MXM3_114", - "MXM3_262", - "MXM3_274", - "MXM3_124", - "MXM3_110", - "MXM3_120", - "MXM3_263", - "MXM3_265", - "", - "MXM3_135", - "MXM3_261", - "MXM3_259"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "MXM3_194", - "MXM3_136", - "MXM3_134", - "MXM3_140", - "MXM3_138", - "", - "MXM3_220", - "", - "", - "MXM3_18", - "MXM3_16", - "", - "", - "MXM3_214", - "MXM3_216", - "MXM3_164"; -}; - -&gpio5 { - gpio-line-names = "MXM3_159", - "", - "", - "", - "MXM3_257", - "", - "", - "", - "", - "", - "MXM3_200", - "MXM3_196", - "MXM3_204", - "MXM3_202", - "", - "", - "", - "", - "MXM3_191", - "MXM3_197", - "MXM3_77", - "MXM3_195", - "MXM3_221", - "MXM3_225", - "MXM3_223", - "MXM3_227", - "MXM3_209", - "MXM3_211", - "MXM3_118", - "MXM3_112", - "MXM3_187", - "MXM3_185"; -}; - -&gpio6 { - gpio-line-names = "MXM3_183", - "MXM3_181", - "MXM3_179", - "MXM3_177", - "MXM3_175", - "MXM3_173", - "MXM3_255", - "MXM3_83", - "MXM3_91", - "MXM3_13/GPIO6", - "MXM3_11/GPIO5", - "MXM3_79", - "", - "", - "MXM3_190", - "MXM3_193", - "MXM3_89"; -}; - -&gpio7 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "MXM3_99", - "MXM3_85", - "MXM3_217", - "MXM3_215"; -}; - -&gpr { - ipu1_csi0_mux { - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@1 { - reg = <1>; - ipu1_csi0_mux_from_parallel_sensor: endpoint { - remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@7 { - interrupt-parent = <&gpio1>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - reg = <7>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; - status = "disabled"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - - atmel_mxt_ts: touchscreen@4a { - compatible = "atmel,maxtouch"; - /* These GPIOs are muxed with the iomuxc node */ - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ - reg = <0x4a>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ - status = "disabled"; - }; -}; - -/* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - fsl,pmic-stby-poweroff; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1875000>; - regulator-min-microvolt = <300000>; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1875000>; - regulator-min-microvolt = <300000>; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1975000>; - regulator-min-microvolt = <400000>; - }; - - swbst_reg: swbst { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <5150000>; - regulator-min-microvolt = <5000000>; - }; - - snvs_reg: vsnvs { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <1000000>; - }; - - vref_reg: vrefddr { - regulator-always-on; - regulator-boot-on; - }; - - vgen1_reg: vgen1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1550000>; - regulator-min-microvolt = <800000>; - }; - - vgen2_reg: vgen2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1550000>; - regulator-min-microvolt = <800000>; - }; - - vgen3_reg: vgen3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - }; - - vgen4_reg: vgen4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - }; - - vgen5_reg: vgen5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - }; - - vgen6_reg: vgen6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - }; - }; - }; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - clocks = <&clks IMX6QDL_CLK_CKO>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_audio>; - VDDIO-supply = <®_module_3v3>; - VDDD-supply = <&vgen4_reg>; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - blocks = <0x5>; - id = <0>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - interrupt-parent = <&gpio4>; - irq-trigger = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC conversion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_ts: stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - status = "disabled"; - }; - - stmpe_adc: stmpe_adc { - compatible = "st,stmpe-adc"; - #io-channel-cells = <1>; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - - adv_7280: adv7280@21 { - compatible = "adi,adv7280"; - adv,force-bt656-4; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - reg = <0x21>; - status = "disabled"; - - port { - adv7280_to_ipu1_csi0_mux: endpoint { - bus-width = <8>; - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; - - ov5640_csi_cam: ov5640_mipi@3c { - compatible = "ovti,ov5640"; - AVDD-supply = <®_ov5640_2v8_a_vdd>; - DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; - DVDD-supply = <®_ov5640_1v8_d_o_vdd>; - clock-names = "xclk"; - clocks = <&clks IMX6QDL_CLK_CKO2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cam_mclk>; - /* These GPIOs are muxed with the iomuxc node */ - powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - reg = <0x3c>; - reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - status = "disabled"; - - port { - ov5640_to_mipi_csi2: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&mipi_csi_from_ov5640>; - }; - }; - }; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - lvds-channel@0 { - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - }; - }; - }; -}; - -&mipi_csi { - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - mipi_csi_from_ov5640: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&ov5640_to_mipi_csi2>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "disabled"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart2 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart4 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_dte>; - status = "disabled"; -}; - -&uart5 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5_dte>; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "disabled"; -}; - -/* MMC1 */ -&usdhc1 { - bus-width = <8>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - disable-wp; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; - vqmmc-supply = <®_module_3v3>; - status = "disabled"; -}; - -/* SD1 */ -&usdhc2 { - bus-width = <4>; - disable-wp; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_module_3v3>; - status = "disabled"; -}; - -/* eMMC */ -&usdhc3 { - bus-width = <8>; - no-1-8-v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; - status = "okay"; -}; - -&weim { - status = "disabled"; -}; - -&iomuxc { - /* Mux the Apalis GPIOs */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - - pinctrl_apalis_gpio1: apalisgpio1grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 - >; - }; - - pinctrl_apalis_gpio2: apalisgpio2grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 - >; - }; - - pinctrl_apalis_gpio3: apalisgpio3grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 - >; - }; - - pinctrl_apalis_gpio4: apalisgpio4grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 - >; - }; - - pinctrl_apalis_gpio5: apalisgpio5grp { - fsl,pins = < - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 - >; - }; - - pinctrl_apalis_gpio6: apalisgpio6grp { - fsl,pins = < - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 - >; - }; - - pinctrl_apalis_gpio7: apalisgpio7grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 - >; - }; - - pinctrl_apalis_gpio8: apalisgpio8grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_cam_mclk: cammclkgrp { - fsl,pins = < - /* CAM sys_mclk */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 - /* SPI1 cs */ - MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - /* SPI2 cs */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Ethernet PHY reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 - /* Ethernet PHY interrupt */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 - >; - }; - - pinctrl_flexcan1_default: flexcan1defgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan1_sleep: flexcan1slpgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 - >; - }; - - pinctrl_flexcan2_default: flexcan2defgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - pinctrl_flexcan2_sleep: flexcan2slpgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 - >; - }; - - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpio1io04grp { - fsl,pins = < - /* Power button */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hdmi_ddc: hdmiddcgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 - >; - }; - - pinctrl_ipu1_lcdif: ipu1lcdifgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 - /* DE */ - MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 - /* HSync */ - MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 - /* VSync */ - MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 - MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 - MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 - MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 - MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 - MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 - MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 - MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 - MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 - MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 - MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 - MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 - MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 - MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 - MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 - MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 - MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 - MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 - MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 - MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 - MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 - MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 - MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 - MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 - MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 - >; - }; - - pinctrl_ipu2_vdac: ipu2vdacgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 - MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 - MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 - MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 - MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 - MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 - MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 - MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 - MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 - MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 - MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 - MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 - MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 - MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 - MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 - MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 - MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 - MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 - MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 - MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 - >; - }; - - pinctrl_mmc_cd: mmccdgrp { - fsl,pins = < - /* MMC1 CD */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_regulator_usbh_pwr: regusbhpwrgrp { - fsl,pins = < - /* USBH_EN */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 - >; - }; - - pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { - fsl,pins = < - /* USBH_HUB_EN */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 - >; - }; - - pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { - fsl,pins = < - /* USBO1 power en */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 - >; - }; - - pinctrl_reset_moci: resetmocigrp { - fsl,pins = < - /* RESET_MOCI control */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 - >; - }; - - pinctrl_sd_cd: sdcdgrp { - fsl,pins = < - /* SD1 CD */ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touch_int: touchintgrp { - fsl,pins = < - /* STMPE811 interrupt */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart1_dce: uart1dcegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart1_dte: uart1dtegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2_dce: uart2dcegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart2_dte: uart2dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4_dce: uart4dcegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart4_dte: uart4dtegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5_dce: uart5dcegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart5_dte: uart5dtegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1_4bit: usdhc1-4bitgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc1_8bit: usdhc1-8bitgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/imx6qdl-apf6.dtsi deleted file mode 100644 index b78ed7974ea9..000000000000 --- a/arch/arm/boot/dts/imx6qdl-apf6.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -#include -#include - -/ { - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_3p3v>; - }; - - usdhc1_pwrseq: usdhc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <15>; - power-off-delay-us = <70>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - }; - }; -}; - -/* Bluetooth */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -/* Wi-Fi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <38400000>; - }; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi deleted file mode 100644 index 2577eb4f535a..000000000000 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <0>; - power-supply = <®_5v>; - }; - - disp0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_disp0>; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-button { - label = "User button"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user-led { - label = "User LED"; - gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - }; - - panel { - compatible = "armadeus,st0700-adapt"; - power-supply = <®_3p3v>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_5v>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound { - compatible = "fsl,imx6-armadeus-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-armadeus-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_5v>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, - <&gpio4 10 GPIO_ACTIVE_LOW>, - <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@48 { - compatible = "semtech,sx8654"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* GSM */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_5v>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 - >; - }; - - pinctrl_gsm: gsmgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_ipu1_disp0: ipu1disp0grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi deleted file mode 100644 index baa197c90060..000000000000 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - */ - -#include - -/ { - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&ecspi4 { - cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; - - imx6qdl-aristainetos { - pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 6b64b2fc3995..000000000000 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,637 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW - &gpio4 10 GPIO_ACTIVE_LOW - &gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&ecspi4 { - cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - - flash: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <04 0x8>; - - regulators { - bcore1 { - regulator-name = "bcore1"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bcore2 { - regulator-name = "bcore2"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bpro { - regulator-name = "bpro"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bperi { - regulator-name = "bperi"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bmem { - regulator-name = "bmem"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "ldo2"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3 { - regulator-name = "ldo3"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "ldo4"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5 { - regulator-name = "ldo5"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "ldo6"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "ldo7"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo8 { - regulator-name = "ldo8"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9 { - regulator-name = "ldo9"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo10 { - regulator-name = "ldo10"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo11 { - regulator-name = "ldo11"; - regulator-always-on; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bio { - regulator-name = "bio"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - expander: tca6416@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50{ - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@57{ - compatible = "atmel,24c64"; - reg = <0x57>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi deleted file mode 100644 index 570995707504..000000000000 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ /dev/null @@ -1,1309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2022 Toradex - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -#include -#include - -/ { - model = "Toradex Colibri iMX6DL/S Module"; - compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - power-supply = <®_module_3v3>; - pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - extcon_usbc_det: usbc-det { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbc_det>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-wakeup { - debounce-interval = <10>; - gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ - label = "Wake-Up"; - linux,code = ; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - panel_dpi: panel-dpi { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb_host_vbus"; - status = "disabled"; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias"; - model = "imx6dl-colibri-sgtl5000"; - mux-int-port = <1>; - mux-ext-port = <5>; - ssi-controller = <&ssi1>; - }; - - /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ - sound_spdif: sound-spdif { - compatible = "fsl,imx-audio-spdif"; - spdif-controller = <&spdif>; - spdif-in; - spdif-out; - model = "imx-spdif"; - status = "disabled"; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; - status = "okay"; -}; - -/* Optional on SODIMM 55/63 */ -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -/* Optional on SODIMM 178/188 */ -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -&clks { - fsl,pmic-stby-poweroff; -}; - -/* Colibri SSP */ -&ecspi4 { - cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "disabled"; -}; - -&fec { - phy-mode = "rmii"; - phy-handle = <ðphy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - reg = <0>; - micrel,led-mode = <0>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", - "SODIMM_67", - "SODIMM_180", - "SODIMM_196", - "SODIMM_174", - "SODIMM_176", - "SODIMM_194", - "SODIMM_55", - "SODIMM_63", - "SODIMM_28", - "SODIMM_93", - "SODIMM_69", - "SODIMM_99", - "SODIMM_130", - "SODIMM_106", - "SODIMM_98", - "SODIMM_192", - "SODIMM_49", - "SODIMM_190", - "SODIMM_51", - "SODIMM_47", - "SODIMM_53", - "", - "SODIMM_22"; -}; - -&gpio2 { - gpio-line-names = "SODIMM_132", - "SODIMM_134", - "SODIMM_135", - "SODIMM_133", - "SODIMM_102", - "SODIMM_43", - "SODIMM_127", - "SODIMM_37", - "SODIMM_104", - "SODIMM_59", - "SODIMM_30", - "SODIMM_100", - "SODIMM_38", - "SODIMM_34", - "SODIMM_32", - "SODIMM_36", - "SODIMM_59", - "SODIMM_67", - "SODIMM_97", - "SODIMM_79", - "SODIMM_103", - "SODIMM_101", - "SODIMM_45", - "SODIMM_105", - "SODIMM_107", - "SODIMM_91", - "SODIMM_89", - "SODIMM_150", - "SODIMM_126", - "SODIMM_128", - "", - "SODIMM_94"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_111", - "SODIMM_113", - "SODIMM_115", - "SODIMM_117", - "SODIMM_119", - "SODIMM_121", - "SODIMM_123", - "SODIMM_125", - "SODIMM_110", - "SODIMM_112", - "SODIMM_114", - "SODIMM_116", - "SODIMM_118", - "SODIMM_120", - "SODIMM_122", - "SODIMM_124", - "", - "SODIMM_96", - "SODIMM_77", - "SODIMM_25", - "SODIMM_27", - "SODIMM_88", - "SODIMM_90", - "SODIMM_31", - "SODIMM_23", - "SODIMM_29", - "SODIMM_71", - "SODIMM_73", - "SODIMM_92", - "SODIMM_81", - "SODIMM_131", - "SODIMM_129"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "SODIMM_168", - "", - "", - "", - "", - "SODIMM_184", - "SODIMM_186", - "HDMI_15", - "HDMI_16", - "SODIMM_178", - "SODIMM_188", - "SODIMM_56", - "SODIMM_44", - "SODIMM_68", - "SODIMM_82", - "SODIMM_24", - "SODIMM_76", - "SODIMM_70", - "SODIMM_60", - "SODIMM_58", - "SODIMM_78", - "SODIMM_72", - "SODIMM_80", - "SODIMM_46", - "SODIMM_62", - "SODIMM_48", - "SODIMM_74"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_95", - "", - "SODIMM_86", - "", - "SODIMM_65", - "SODIMM_50", - "SODIMM_52", - "SODIMM_54", - "SODIMM_66", - "SODIMM_64", - "SODIMM_57", - "SODIMM_61", - "SODIMM_136", - "SODIMM_138", - "SODIMM_140", - "SODIMM_142", - "SODIMM_144", - "SODIMM_146", - "SODIMM_172", - "SODIMM_170", - "SODIMM_149", - "SODIMM_151", - "SODIMM_153", - "SODIMM_155", - "SODIMM_157", - "SODIMM_159", - "SODIMM_161", - "SODIMM_163", - "SODIMM_33", - "SODIMM_35", - "SODIMM_165", - "SODIMM_167"; -}; - -&gpio6 { - gpio-line-names = "SODIMM_169", - "SODIMM_171", - "SODIMM_173", - "SODIMM_175", - "SODIMM_177", - "SODIMM_179", - "SODIMM_85", - "SODIMM_166", - "SODIMM_160", - "SODIMM_162", - "SODIMM_158", - "SODIMM_164", - "", - "", - "SODIMM_156", - "SODIMM_75", - "SODIMM_154", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_152"; -}; - -&gpio7 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_19", - "SODIMM_21", - "", - "SODIMM_137"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_ddc>; - status = "disabled"; -}; - -/* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - fsl,pmic-stby-poweroff; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1875000>; - regulator-min-microvolt = <300000>; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1875000>; - regulator-min-microvolt = <300000>; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1975000>; - regulator-min-microvolt = <400000>; - }; - - swbst_reg: swbst { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <5150000>; - regulator-min-microvolt = <5000000>; - }; - - snvs_reg: vsnvs { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <1000000>; - }; - - vref_reg: vrefddr { - regulator-always-on; - regulator-boot-on; - }; - - /* vgen1: unused */ - - vgen2_reg: vgen2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1550000>; - regulator-min-microvolt = <800000>; - }; - - /* - * +V3.3_1.8_SD1 coming off VGEN3 and supplying - * the i.MX 6 NVCC_SD1. - */ - vgen3_reg: vgen3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - }; - - vgen4_reg: vgen4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - }; - - vgen5_reg: vgen5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - }; - - vgen6_reg: vgen6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - }; - }; - }; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX6QDL_CLK_CKO>; - lrclk-strength = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_module_3v3_audio>; - VDDIO-supply = <®_module_3v3>; - VDDD-supply = <&vgen4_reg>; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - blocks = <0x5>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio6>; - interrupt-controller; - id = <0>; - irq-trigger = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_ts: stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - status = "disabled"; - }; - - stmpe_adc: stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; -}; - -/* - * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) - */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - - atmel_mxt_ts: touchscreen@4a { - compatible = "atmel,maxtouch"; - interrupt-parent = <&gpio2>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_atmel_conn>; - reg = <0x4a>; - reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ - status = "disabled"; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -/* Colibri PWM */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "disabled"; -}; - -/* Optional S/PDIF out on SODIMM 137 */ -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - uart-has-rtscts; - status = "disabled"; -}; - -/* Colibri UART_B */ -&uart2 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - uart-has-rtscts; - status = "disabled"; -}; - -/* Colibri UART_C */ -&uart3 { - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_dte>; - status = "disabled"; -}; - -/* Colibri USBH */ -&usbh1 { - vbus-supply = <®_usb_host_vbus>; -}; - -/* Colibri USBC */ -&usbotg { - dr_mode = "otg"; - extcon = <0>, <&extcon_usbc_det>; - status = "disabled"; -}; - -/* Colibri MMC */ -&usdhc1 { - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ - bus-width = <4>; - no-1-8-v; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <&vgen3_reg>; - status = "disabled"; -}; - -/* eMMC */ -&usdhc3 { - bus-width = <8>; - no-1-8-v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 - &pinctrl_weim_cs1 &pinctrl_weim_cs2 - &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; - #address-cells = <2>; - #size-cells = <1>; - status = "disabled"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_oc_1>; - - /* Atmel MXT touchsceen + Capacitive Touch Adapter */ - /* NOTE: This pin group conflicts with pin groups - * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. - */ - pinctrl_atmel_adap: atmeladaptergrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ - >; - }; - - /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ - /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and - * pinctrl_weim_cs2. Don't use them simultaneously. - */ - pinctrl_atmel_conn: atmelconnectorgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 - >; - }; - - pinctrl_cam_mclk: cammclkgrp { - fsl,pins = < - /* Parallel Camera CAM sys_mclk */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 - >; - }; - - /* CSI pins used as GPIOs */ - pinctrl_csi_gpio_1: csigpio1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - >; - }; - - pinctrl_csi_gpio_2: csigpio2grp { - fsl,pins = < - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - /* SPI CS */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_1: gpio1grp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - >; - }; - pinctrl_gpio_2: gpio2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - >; - }; - - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - >; - }; - - pinctrl_hdmi_ddc: hdmiddcgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ - fsl,pins = < - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 - MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 - MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 - MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 - MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 - MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 - MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 - MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 - MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 - /* Disable PWM pins on camera interface */ - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 - >; - }; - - pinctrl_ipu1_lcdif: ipu1lcdifgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 - >; - }; - - pinctrl_lvds_transceiver: lvdstxgrp { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ - >; - }; - - pinctrl_mic_gnd: micgndgrp { - fsl,pins = < - /* Controls Mic GND, PU or '1' pull Mic GND to GND */ - MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 - >; - }; - - pinctrl_mmc_cd: mmccdgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 - >; - }; - - pinctrl_mmc_cd_sleep: mmccdslpgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { - fsl,pins = < - /* SODIMM 129 / USBH_PEN */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touch_int: gpiotouchintgrp { - fsl,pins = < - /* STMPE811 interrupt */ - MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 - >; - }; - - pinctrl_uart1_dce: uart1dcegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart1_dte: uart1dtegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - >; - }; - - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart2_dte: uart2dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_dte: uart3dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - /* SODIMM 137 / USBC_DET */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* USBC_DET_OVERWRITE */ - MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 - /* USBC_DET_EN */ - MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 - >; - }; - - pinctrl_usbc_id_1: usbcid1grp { - fsl,pins = < - /* USBC_ID */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; - - pinctrl_usbh_oc_1: usbhoc1grp { - fsl,pins = < - /* USBH_OC */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 - >; - }; - - /* avoid backfeeding with removed card power */ - pinctrl_usdhc1_sleep: usdhc1sleepgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - /* nEXT_CS0 */ - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_cs1: weimcs1grp { - fsl,pins = < - /* nEXT_CS1 */ - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 - >; - }; - - pinctrl_weim_cs2: weimcs2grp { - fsl,pins = < - /* nEXT_CS2 */ - MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 - >; - }; - - /* ADDRESS[16:18] [25] used as GPIO */ - pinctrl_weim_gpio_1: weimgpio1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* ADDRESS[19:24] used as GPIO */ - pinctrl_weim_gpio_2: weimgpio2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* DATA[16:31] used as GPIO */ - pinctrl_weim_gpio_3: weimgpio3grp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 - >; - }; - - /* DQM[0:3] used as GPIO */ - pinctrl_weim_gpio_4: weimgpio4grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - >; - }; - - /* RDY used as GPIO */ - pinctrl_weim_gpio_5: weimgpio5grp { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 - >; - }; - - /* ADDRESS[16] DATA[30] used as GPIO */ - pinctrl_weim_gpio_6: weimgpio6grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_weim_npwe: weimnpwegrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 - >; - }; - - pinctrl_weim_sram: weimsramgrp { - fsl,pins = < - /* Data */ - MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 - /* Address */ - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - /* Ctrl */ - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - >; - }; - - pinctrl_weim_rdnwr: weimrdnwrgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 - MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi deleted file mode 100644 index 1e530d892b76..000000000000 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 9 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_ir>; - }; - - led-controller { - compatible = "pwm-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_pwm1>; - - led-1 { - active-low; - label = "imx6:red:front"; - max-brightness = <248>; - pwms = <&pwm1 0 50000>; - }; - }; - - v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_5v0"; - }; - - v_usb2: regulator-v-usb2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb2"; - vin-supply = <&v_5v0>; - }; - - v_usb1: regulator-v-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb1"; - vin-supply = <&v_5v0>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "Integrated SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_gpio_key>; - pinctrl-names = "default"; - - button_0 { - label = "Button 0"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c3>; - - status = "okay"; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; -}; - -&iomuxc { - cubox_i { - pinctrl_cubox_i_hdmi: cubox-i-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_cubox_i_i2c2: cubox-i-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_cubox_i_i2c3: cubox-i-i2c3 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_cubox_i_ir: cubox-i-ir { - fsl,pins = < - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 - >; - }; - - pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { - fsl,pins = ; - }; - - pinctrl_cubox_i_spdif: cubox-i-spdif { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbh1: cubox-i-usbh1 { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbotg: cubox-i-usbotg { - /* - * The Cubox-i pulls ID low, but as it's pointless - * leaving it as a pull-up, even if it is just 10uA. - */ - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; - - pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - - pinctrl_gpio_key: gpio-key { - fsl,pins = < - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 - >; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_spdif>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1>; - vbus-supply = <&v_usb2>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg>; - vbus-supply = <&v_usb1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; - vmmc-supply = <&vcc_3v3>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&vcc_3v3 { - vin-supply = <&v_5v0>; -}; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi deleted file mode 100644 index 2c1d6f28e695..000000000000 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "dummy-supply"; - }; - - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - chosen { - stdout-path = &uart1; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf040b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - status = "okay"; - phy-mode = "rgmii"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-dfi-fs700-m60 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - >; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { /* module slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { /* baseboard slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; -}; - -&usdhc4 { /* eMMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi deleted file mode 100644 index 702cd4a1b2e6..000000000000 --- a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2021 DH electronics GmbH - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* - * Special SoM hardware required which uses the pins from micro SD card. The - * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 - * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD - * card must be disabled and the uart1 rts/cts must be output on other DHCOM - * pins, see uart1 and usdhc3 node below. - */ -&can2 { - status = "okay"; -}; - -&gpio1 { - /* - * NOTE: On DRC02, the RS485_RX_En is controlled by a separate - * GPIO line, however the i.MX6 UART driver assumes RX happens - * during TX anyway and that it only controls drive enable DE - * line. Hence, the RX is always enabled here. - */ - rs485-rx-en-hog { - gpio-hog; - gpios = <18 0>; /* GPIO Q */ - line-name = "rs485-rx-en"; - output-low; - }; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "DRC02-In1", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", - "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", - "", "", "", "", "DRC02-Out1", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio6 { - gpio-line-names = - "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", - "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&uart1 { - /* - * Due to the use of can2 the signals for can2 Tx and Rx are routed to - * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs - * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. - */ - /delete-property/ uart-has-rtscts; - cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ - pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; - pinctrl-names = "default"; - rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ -}; - -&uart5 { - /* - * On DRC02 this UART is used as RS485 interface and RS485_TX_En is - * controlled by DHCOM GPIO P. So remove rts/cts pins and the property - * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via - * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 - * node above. - */ - /delete-property/ uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; - pinctrl-names = "default"; - rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ -}; - -&usbh1 { - disable-over-current; -}; - -&usdhc2 { /* SD card */ - status = "okay"; -}; - -&usdhc3 { - /* - * Due to the use of can2 the micro SD card on module have to be - * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as - * can2 Tx and Rx. - */ - status = "disabled"; -}; - -&iomuxc { - pinctrl-0 = < - /* - * The following DHCOM GPIOs are used on this board. - * Therefore, they have been removed from the list below. - * I: uart1 rts - * M: uart1 cts - * P: uart5 rs485-tx-en - * Q: uart5 rs485-rx-en - */ - &pinctrl_hog_base - &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c - &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f - &pinctrl_dhcom_g &pinctrl_dhcom_h - &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - &pinctrl_dhcom_n &pinctrl_dhcom_o - &pinctrl_dhcom_r - &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u - &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int - >; - pinctrl-names = "default"; - - pinctrl_uart5_core: uart5-core-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi deleted file mode 100644 index 6248b126b557..000000000000 --- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015-2021 DH electronics GmbH - * Copyright (C) 2018 Marek Vasut - */ - -#include -#include -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk_ext_audio_codec: clock-codec { - #clock-cells = <0>; - clock-frequency = <24000000>; - compatible = "fixed-clock"; - }; - - display_bl: display-bl { - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - compatible = "pwm-backlight"; - default-brightness-level = <8>; - enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */ - pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; - status = "okay"; - }; - - lcd_display: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; - pinctrl-names = "default"; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - gpio-keys { - #size-cells = <0>; - compatible = "gpio-keys"; - - button-0 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */ - label = "TA1-GPIO-A"; - linux,code = ; - pinctrl-0 = <&pinctrl_dhcom_a>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-1 { - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */ - label = "TA2-GPIO-B"; - linux,code = ; - pinctrl-0 = <&pinctrl_dhcom_b>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-2 { - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */ - label = "TA3-GPIO-C"; - linux,code = ; - pinctrl-0 = <&pinctrl_dhcom_c>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-3 { - gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */ - label = "TA4-GPIO-D"; - linux,code = ; - pinctrl-0 = <&pinctrl_dhcom_d>; - pinctrl-names = "default"; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - /* - * Disable led-5, because GPIO E is - * already used as touch interrupt. - */ - led-5 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ - pinctrl-0 = <&pinctrl_dhcom_e>; - pinctrl-names = "default"; - status = "disabled"; - }; - - led-6 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ - pinctrl-0 = <&pinctrl_dhcom_f>; - pinctrl-names = "default"; - }; - - led-7 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ - pinctrl-0 = <&pinctrl_dhcom_h>; - pinctrl-names = "default"; - }; - - led-8 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ - pinctrl-0 = <&pinctrl_dhcom_i>; - pinctrl-names = "default"; - }; - }; - - panel { - backlight = <&display_bl>; - compatible = "edt,etm0700g0edh6"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - sound { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-sgtl5000"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - pinctrl-0 = <&pinctrl_audmux_ext>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -/* 1G ethernet */ -/delete-node/ ðphy0; -&fec { - phy-mode = "rgmii"; - phy-handle = <ðphy7>; - pinctrl-0 = <&pinctrl_enet_1G>; - pinctrl-names = "default"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy7: ethernet-phy@7 { /* KSZ 9021 */ - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pinctrl_ethphy7>; - pinctrl-names = "default"; - reg = <7>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - txen-skew-ps = <0>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - sgtl5000: codec@a { - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <&sw2_reg>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - pinctrl-0 = <&pinctrl_dhcom_e>; - pinctrl-names = "default"; - reg = <0x38>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pcie { - pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; - reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */ - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; -}; - -&usdhc2 { /* SD card */ - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = < - /* - * The following DHCOM GPIOs are used on this board. - * Therefore, they have been removed from the list below. - * A: key TA1 - * B: key TA2 - * C: key TA3 - * D: key TA4 - * E: touchscreen - * F: led6 - * G: backlight enable - * H: led7 - * I: led8 - * J: PCIe reset - */ - &pinctrl_hog_base - &pinctrl_dhcom_k &pinctrl_dhcom_l - &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o - &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r - &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u - &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int - >; - pinctrl-names = "default"; - - pinctrl_audmux_ext: audmux-ext-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - >; - }; - - pinctrl_enet_1G: enet-1G-grp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - >; - }; - - pinctrl_ethphy7: ethphy7-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi deleted file mode 100644 index 4cd4cb9543c8..000000000000 --- a/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2021 DH electronics GmbH - */ - -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ - pinctrl-0 = <&pinctrl_dhcom_i>; - pinctrl-names = "default"; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "", - "", "", "", "", "", "", "", "", - "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H", - "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "", - "", "", "", "", "PicoITX-Out1", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio6 { - gpio-line-names = - "", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "", - "", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&iomuxc { - pinctrl-0 = < - /* - * The following DHCOM GPIOs are used on this board. - * Therefore, they have been removed from the list below. - * I: yellow led - */ - &pinctrl_hog_base - &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c - &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f - &pinctrl_dhcom_g &pinctrl_dhcom_h - &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o - &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r - &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u - &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int - >; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi deleted file mode 100644 index eaa87b333164..000000000000 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ /dev/null @@ -1,850 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015-2021 DH electronics GmbH - * Copyright (C) 2018 Marek Vasut - */ - -#include -#include -#include -#include - -/ { - aliases { - i2c0 = &i2c2; - i2c1 = &i2c1; - i2c2 = &i2c3; - mmc0 = &usdhc2; - mmc1 = &usdhc3; - mmc2 = &usdhc4; - mmc3 = &usdhc1; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - serial0 = &uart1; - serial1 = &uart5; - serial2 = &uart4; - serial3 = &uart2; - serial4 = &uart3; - }; - - memory@10000000 { /* Appropriate memory size will be filled by U-Boot */ - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - reg_3p3v: regulator-3P3V { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "3P3V"; - }; - - reg_eth_vio: regulator-eth-vio { - compatible = "regulator-fixed"; - gpio = <&gpio1 7 0>; - pinctrl-0 = <&pinctrl_enet_vio>; - pinctrl-names = "default"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "eth_vio"; - vin-supply = <&sw2_reg>; - }; - - /* OE pin of the latch is low active */ - reg_latch_oe_on: regulator-latch-oe-on { - compatible = "regulator-fixed"; - gpio = <&gpio3 22 0>; - regulator-always-on; - regulator-name = "latch_oe_on"; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 31 0>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb_h1_vbus"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb_otg_vbus"; - }; -}; - -&can1 { - pinctrl-0 = <&pinctrl_flexcan1>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* - * Special SoM hardware required which uses the pins from micro SD card. The - * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 - * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on - * the board device tree file, the micro SD card must be disabled and the uart1 - * rts/cts must be disabled or output on other DHCOM pins. - */ -&can2 { - pinctrl-0 = <&pinctrl_flexcan2>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_ecspi1>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { /* S25FL116K */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - m25p,fast-read; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_ecspi2>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&fec { - phy-mode = "rmii"; - phy-handle = <ðphy0>; - pinctrl-0 = <&pinctrl_enet_100M>; - pinctrl-names = "default"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ - compatible = "ethernet-phy-id0007.c0f0", - "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio4>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pinctrl_ethphy0>; - pinctrl-names = "default"; - reg = <0>; - reset-assert-us = <500>; - reset-deassert-us = <500>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - smsc,disable-energy-detect; /* Make plugin detection reliable */ - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "", - "", "", "", "", "", "", "", "", - "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "DHCOM-G", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H", - "DHCOM-I", "DHCOM-L", "", "", "", "", "", "", - "", "", "", "", "DHCOM-F", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio6 { - gpio-line-names = - "", "", "", "DHCOM-D", "", "", "SOM-HW1", "", - "", "", "", "", "", "", "DHCOM-J", "DHCOM-K", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio7 { - gpio-line-names = - "DHCOM-M", "DHCOM-N", "", "", "", "", "", "", - "", "", "", "", "", "DHCOM-P", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - /* - * Info: According to erratum ERR007805 clock frequency limit is 375000. - * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2]. - * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf - * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf - */ - clock-frequency = <100000>; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - pinctrl-names = "default", "gpio"; - scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c2 { - /* Info: Clock frequency limit is 375000 (for details see i2c1) */ - clock-frequency = <100000>; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - pinctrl-names = "default", "gpio"; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c3 { - /* Info: Clock frequency limit is 375000 (for details see i2c1) */ - clock-frequency = <100000>; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - pinctrl-names = "default", "gpio"; - scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-0 = <&pinctrl_pmic>; - pinctrl-names = "default"; - reg = <0x3c>; - - regulators { - sw1_reg: sw1 { - lltc,fb-voltage-divider = <100000 110000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1527272>; - regulator-min-microvolt = <787500>; - regulator-ramp-delay = <7000>; - regulator-suspend-mem-microvolt = <1040000>; - }; - - sw2_reg: sw2 { - lltc,fb-voltage-divider = <100000 28000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3657142>; - regulator-min-microvolt = <1885714>; - regulator-ramp-delay = <7000>; - }; - - sw3_reg: sw3 { - lltc,fb-voltage-divider = <100000 110000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1527272>; - regulator-min-microvolt = <787500>; - regulator-ramp-delay = <7000>; - regulator-suspend-mem-microvolt = <980000>; - }; - - sw4_reg: sw4 { - lltc,fb-voltage-divider = <100000 93100>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1659291>; - regulator-min-microvolt = <855571>; - regulator-ramp-delay = <7000>; - }; - - ldo1_reg: ldo1 { - lltc,fb-voltage-divider = <102000 29400>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3240306>; - regulator-min-microvolt = <3240306>; - }; - - ldo2_reg: ldo2 { - lltc,fb-voltage-divider = <100000 41200>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2484708>; - regulator-min-microvolt = <2484708>; - }; - }; - }; - - touchscreen@49 { /* TSC2004 */ - compatible = "ti,tsc2004"; - interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; - pinctrl-0 = <&pinctrl_tsc2004>; - pinctrl-names = "default"; - reg = <0x49>; - vio-supply = <®_3p3v>; - status = "disabled"; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_i2c: rtc@56 { - compatible = "microcrystal,rv3029"; - interrupt-parent = <&gpio7>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - pinctrl-0 = <&pinctrl_rtc>; - pinctrl-names = "default"; - reg = <0x56>; - }; -}; - -&pcie { - pinctrl-0 = <&pinctrl_pcie>; - pinctrl-names = "default"; -}; - -&pwm1 { - pinctrl-0 = <&pinctrl_pwm1>; - pinctrl-names = "default"; -}; - -®_arm { - vin-supply = <&sw3_reg>; -}; - -®_pu { - vin-supply = <&sw1_reg>; -}; - -®_soc { - vin-supply = <&sw1_reg>; -}; - -®_vdd1p1 { - vin-supply = <&sw2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&sw2_reg>; -}; - -&uart1 { /* DHCOM UART1 */ - dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_uart1>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { /* DHCOM UART3 */ - pinctrl-0 = <&pinctrl_uart4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart5 { /* DHCOM UART2 */ - pinctrl-0 = <&pinctrl_uart5>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - pinctrl-0 = <&pinctrl_usbh1>; - pinctrl-names = "default"; - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - dr_mode = "otg"; - pinctrl-0 = <&pinctrl_usbotg>; - pinctrl-names = "default"; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -&usdhc2 { /* External SD card via DHCOM */ - cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&usdhc3 { /* Micro SD card on module */ - cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - keep-power-in-suspend; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usdhc4 { /* eMMC on module */ - bus-width = <8>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - pinctrl-0 = <&pinctrl_usdhc4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&weim { - #address-cells = <2>; - #size-cells = <1>; - fsl,weim-cs-gpr = <&gpr>; - pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>; - pinctrl-names = "default"; - /* It is necessary to setup 2x 64MB otherwise setting gpr fails */ - ranges = <0 0 0x08000000 0x04000000>, /* CS0 */ - <1 0 0x0c000000 0x04000000>; /* CS1 */ - status = "disabled"; -}; - -&iomuxc { - pinctrl-0 = < - &pinctrl_hog_base - &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c - &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f - &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i - &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o - &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r - &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u - &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int - >; - pinctrl-names = "default"; - - pinctrl_hog_base: hog-base-grp { - fsl,pins = < - /* GPIOs for memory coding */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0 - /* GPIOs for hardware coding */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 - >; - }; - - /* DHCOM GPIOs */ - pinctrl_dhcom_a: dhcom-a-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_b: dhcom-b-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_c: dhcom-c-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_d: dhcom-d-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_e: dhcom-e-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_f: dhcom-f-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_g: dhcom-g-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_h: dhcom-h-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_i: dhcom-i-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_j: dhcom-j-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_k: dhcom-k-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_l: dhcom-l-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_m: dhcom-m-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_n: dhcom-n-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_o: dhcom-o-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_p: dhcom-p-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_q: dhcom-q-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_r: dhcom-r-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_s: dhcom-s-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_t: dhcom-t-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_u: dhcom-u-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_v: dhcom-v-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_w: dhcom-w-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_int: dhcom-int-grp { - fsl,pins = ; - }; - - pinctrl_ecspi1: ecspi1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 - >; - }; - - pinctrl_enet_100M: enet-100M-grp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_enet_vio: enet-vio-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 - >; - }; - - pinctrl_ethphy0: ethphy0-grp { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */ - >; - }; - - pinctrl_flexcan1: flexcan1-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2-grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpio-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2-gpio-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3-gpio-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 - >; - }; - - pinctrl_ipu1_lcdif: ipu1-lcdif-grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 - >; - }; - - pinctrl_pcie: pcie-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ - >; - }; - - pinctrl_pmic: pmic-grp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1-grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_rtc: rtc-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0 - >; - }; - - pinctrl_tsc2004: tsc2004-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0 - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1 - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1 - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1 - >; - }; - - pinctrl_usbh1: usbh1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotg-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2-grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3-grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0 - >; - }; - - pinctrl_usdhc4: usdhc4-grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_weim: weim-grp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */ - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */ - >; - }; - - pinctrl_weim_cs0: weim-cs0-grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_cs1: weim-cs1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/imx6qdl-ds.dtsi deleted file mode 100644 index f7e517555697..000000000000 --- a/arch/arm/boot/dts/imx6qdl-ds.dtsi +++ /dev/null @@ -1,458 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2021 Dillon Min -// -// Based on imx6qdl-sabresd.dtsi which is: -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vsync-active = <1>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&ov2659_to_ipu1_csi0_mux>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>; - status = "okay"; - - m25p80: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&phy>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@1 { - reg = <1>; - qca,clk-out-frequency = <125000000>; - reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - ov2659: camera@30 { - compatible = "ovti,ov2659"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov2659>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xvclk"; - reg = <0x30>; - powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - status = "okay"; - - port { - ov2659_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - link-frequencies = /bits/ 64 <70000000>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - >; - }; - - pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_ov2659: ov2659grp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 - >; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - bus-width = <4>; - cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi deleted file mode 100644 index c4e146f3341b..000000000000 --- a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -/ { - aliases { - boardid = &boardid; - mmc0 = &usdhc3; - mmc1 = &usdhc2; - mmc2 = &usdhc1; - mmc3 = &usdhc4; - }; - - reg_wall_5p0: reg-wall5p0 { - compatible = "regulator-fixed"; - regulator-name = "Main-Supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_base3p3: reg-base3p3 { - compatible = "regulator-fixed"; - vin-supply = <®_wall_5p0>; - regulator-name = "3V3-avari"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_base1p5: reg-base1p5 { - compatible = "regulator-fixed"; - vin-supply = <®_base3p3>; - regulator-name = "1V5-avari"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_usb_otg: reg-otgvbus { - compatible = "regulator-fixed"; - vin-supply = <®_wall_5p0>; - regulator-name = "OTG_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - clk_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "emCON-avari-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&ecspi2 { - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_codec>; - VDDA-supply = <®_base3p3>; - VDDIO-supply = <®_base3p3>; - }; - - captouch: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; - interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - boardid: gpio@3a { - compatible = "nxp,pca8574"; - reg = <0x3a>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pcie { - status = "okay"; -}; - -&rgb_encoder { - status = "okay"; -}; - -&rgb_panel { - compatible = "edt,etm0700g0bdh6"; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - uart-has-rtscts; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi deleted file mode 100644 index ee2dd75cead6..000000000000 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ /dev/null @@ -1,834 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -#include -#include -#include - -/ { - - model = "emtrion SoM emCON-MX6"; - compatible = "emtrion,emcon-mx6"; - - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc2; - mmc2 = &usdhc1; - rtc0 = &ds1307; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emcon_wake>; - - wake { - label = "Wake"; - linux,code = ; - gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - som_leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_som_leds>; - - led-green { - label = "som:green"; - gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led-red { - label = "som:red"; - gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - }; - - lvds_backlight: lvds-backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds_bl>; - enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - pwms = <&pwm1 0 50000>; - brightness-levels = < - 0 4 8 16 32 64 80 96 112 - 128 144 160 176 250 - >; - default-brightness-level = <13>; - status = "okay"; - }; - - pwm_fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm4 0 50000>; - cooling-levels = <0 64 127 191 255>; - status = "disabled"; - }; - - - rgb_encoder: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb24_display>; - status = "disabled"; - - port@0 { - reg = <0>; - - rgb_encoder_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - rgb_encoder_out: endpoint { - remote-endpoint = <&rgb_panel_in>; - }; - }; - }; - - rgb_panel: lcd { - backlight = <&rgb_backlight>; - power-supply = <®_parallel_disp>; - - port { - rgb_panel_in: endpoint { - remote-endpoint = <&rgb_encoder_out>; - }; - }; - }; - - reg_parallel_disp: reg-parallel-display { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb_bl_en>; - regulator-name = "LCD-Supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_disp: reg-lvds-display { - compatible = "regulator-fixed"; - regulator-name = "LVDS-Supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - rgb_backlight: rgb-backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb_bl>; - enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - pwms = <&pwm3 0 5000000>; - brightness-levels = < - 250 176 160 144 128 112 - 96 80 64 48 32 16 8 1 - >; - default-brightness-level = <13>; - status = "okay"; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, - <&gpio2 27 GPIO_ACTIVE_LOW>; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nor_flash>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - phy-reset-duration = <50>; - phy-supply = <&vdd_1V8_reg>; - phy-handle = <&ksz9031>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ksz9031: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; - rxdv-skew-ps = <480>; - txen-skew-ps = <480>; - rxd0-skew-ps = <480>; - rxd1-skew-ps = <480>; - rxd2-skew-ps = <480>; - rxd3-skew-ps = <480>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <360>; - txd3-skew-ps = <360>; - txc-skew-ps = <1020>; - rxc-skew-ps = <960>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - da9063: pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio2>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - wakeup-source; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - timeout-sec = <0>; - }; - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <2>; - regulator-name = "DA9063_CORE"; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <2>; - regulator-name = "DA9063_SOC"; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <2>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <2>; - regulator-always-on; - }; - - vdd_sata_reg: ldo3 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - vdd_mipi_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_hdmi_reg: ldo6 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_pcie_reg: ldo7 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_1V8_reg: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_3V3_sdc_reg: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1V2_reg: ldo10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - }; - }; - - ds1307: rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; -}; - -&iomuxc { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 - >; - }; - - pinctrl_cpi1: csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 - >; - }; - - /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; - - pinctrl_emcon_gpio1: emcongpio1 { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio2: emcongpio2 { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio3: emcongpio3 { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio4: emcongpio4 { - fsl,pins = < - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio5: emcongpio5 { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio6: emcongpio6 { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio7: emcongpio7 { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio8: emcongpio8 { - fsl,pins = < - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_a: emconirqa { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_b: emconirqb { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_c: emconirqc { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_pwr: emconirqpwr { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 - >; - }; - - pinctrl_emcon_wake: emconwake { - fsl,pins = < - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 - >; - }; - - pinctrl_irq_touch1: irqtouch1 { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 - >; - }; - - pinctrl_irq_touch2: irqtouch2 { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 - >; - }; - - pinctrl_lvds_bl: lvdsbacklightgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 - >; - }; - - pinctrl_lvds_reg: lvdsreggrp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 - >; - }; - - - pinctrl_nor_flash: norflashgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 - >; - }; - - pinctrl_pcie_ctrl: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 - >; - }; - - pinctrl_pwm_fan: pwmfan { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 - >; - }; - - pinctrl_rgb_bl: rgbbacklightgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 - >; - }; - - pinctrl_rgb_bl_en: rgbenable { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 - >; - }; - - pinctrl_rgb24_display: rgbgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_secure: securegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 - >; - }; - - pinctrl_som_leds: somledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 - >; - }; - - pinctrl_spdif_in: spdifin { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_spdif_out: spdifout { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usb_host1: usbhgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 - >; - }; - - pinctrl_usb_otg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 - MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 - MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&rgb_encoder_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_ctrl>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; -}; - -&pwm1 { - #pwm-cells = <2>; - status = "okay"; -}; - -&pwm3 { - #pwm-cells = <2>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_host1>; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg>; - vbus-supply = <®_usb_otg>; - dr_mode = "peripheral"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - fsl,wp-controller; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - fsl,wp-controller; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -/******device power Management*********/ - -&cpu0 { - voltage-tolerance = <2>; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -/*******Disabled HW following***********/ - -&snvs_rtc { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi deleted file mode 100644 index e75e1a5364b8..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ /dev/null @@ -1,638 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_an1"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi deleted file mode 100644 index 47d9a8d08197..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ /dev/null @@ -1,795 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can1>; - regulator-name = "can1_stby"; - gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - - channel@29 { - gw,mode = <1>; - reg = <0x29>; - label = "vdd_an1"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_AUD_1P8: Audio codec */ - reg_aud_1p8v: ldo3 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; - - accel@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_can1: regcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi deleted file mode 100644 index fb1d29abe099..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ /dev/null @@ -1,784 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can1>; - regulator-name = "can1_stby"; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - - channel@26 { - gw,mode = <1>; - reg = <0x26>; - label = "vdd_gps"; - }; - - channel@29 { - gw,mode = <1>; - reg = <0x29>; - label = "vdd_an1"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_AUD_1P8: Audio codec */ - reg_aud_1p8v: ldo3 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <11 2>; - wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - accel@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_can1: regcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi deleted file mode 100644 index a642be45ffe2..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ /dev/null @@ -1,877 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can1>; - regulator-name = "can1_stby"; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound-analog { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ - status = "okay"; - - mux-ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-aud5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - - channel@26 { - gw,mode = <1>; - reg = <0x26>; - label = "vdd_gps"; - }; - }; - - fan-controller@2c { - compatible = "gw,gsc-fan"; - reg = <0x2c>; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <&sw4_reg>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; - - accel@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default", "state_dio"; - pinctrl-0 = <&pinctrl_pwm4_backlight>; - pinctrl-1 = <&pinctrl_pwm4_dio>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_ecspi2: escpi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4_backlight: pwm4grpbacklight { - fsl,pins = < - /* LVDS_PWM J6.5 */ - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4_dio: pwm4grpdio { - fsl,pins = < - /* DIO3 J16.4 */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_can1: regcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi deleted file mode 100644 index 29960d1cf6a0..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-digital { - compatible = "simple-audio-card"; - simple-audio-card,name = "tda1997x-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&hdmi_receiver>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-aud5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8a"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0b"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_3P3 (1+R1/R2 = 1.281) */ - reg_3p3: sw4 { - regulator-name = "vdd3p3"; - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <3647000>; - lltc,fb-voltage-divider = <200000 56200>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ - reg_1p8a: ldo2 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1816125>; - regulator-max-microvolt = <1816125>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8b: HDMI In analog */ - reg_1p8b: ldo3 { - regulator-name = "vdd1p8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - gpio_exp: pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi_receiver: hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3>; - AVDD-supply = <®_1p8b>; - DVDD-supply = <®_1p8a>; - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same cycle - * which we map to VP[15:08]<->CSI_DATA[19:12] - */ - nxp,vidout-portcfg = - /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 - MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1_csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_tda1997x: tda1997xgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi deleted file mode 100644 index 77ae611b817a..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; }; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi deleted file mode 100644 index 7f16c602cc07..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ /dev/null @@ -1,738 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8a"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0b"; - }; - - channel@26 { - gw,mode = <1>; - reg = <0x26>; - label = "vdd_an1"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - magn@1c { - compatible = "st,lsm9ds1-magn"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mag>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - }; - - imu@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - st,drdy-int-pin = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imu>; - interrupt-parent = <&gpio7>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_3P3 (1+R1/R2 = 1.281) */ - reg_3p3v: sw4 { - regulator-name = "vdd3p3"; - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <3647000>; - lltc,fb-voltage-divider = <200000 56200>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ - reg_1p8a: ldo2 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1816125>; - regulator-max-microvolt = <1816125>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8b: microSD VDD_1P8 */ - reg_1p8b: ldo3 { - regulator-name = "vdd1p8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_imu: imugrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_mag: maggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi deleted file mode 100644 index 46cf4080fec3..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ /dev/null @@ -1,931 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; - - backlight-keypad { - compatible = "gpio-backlight"; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - default-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "12P0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_1p4v: regulator-vddsoc { - compatible = "regulator-fixed"; - regulator-name = "vdd_soc"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_an1"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - - channel@26 { - gw,mode = <1>; - reg = <0x26>; - label = "vdd_gps"; - }; - - channel@29 { - gw,mode = <1>; - reg = <0x29>; - label = "vdd_an2"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - ds1672: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - magn@1c { - compatible = "st,lsm9ds1-magn"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mag>; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_EDGE_RISING>; - }; - - tca8418: keypad@34 { - compatible = "ti,tca8418"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keypad>; - reg = <0x34>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) - MATRIX_KEY(0x00, 0x00, BTN_1) - MATRIX_KEY(0x01, 0x01, BTN_2) - MATRIX_KEY(0x01, 0x00, BTN_3) - MATRIX_KEY(0x02, 0x00, BTN_4) - MATRIX_KEY(0x00, 0x03, BTN_5) - MATRIX_KEY(0x00, 0x02, BTN_6) - MATRIX_KEY(0x01, 0x03, BTN_7) - MATRIX_KEY(0x01, 0x02, BTN_8) - MATRIX_KEY(0x02, 0x02, BTN_9) - >; - keypad,num-rows = <4>; - keypad,num-columns = <4>; - }; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.931) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <796551>; - regulator-max-microvolt = <1544827>; - lltc,fb-voltage-divider = <243000 261000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - linux,phandle = <®_vdd_arm>; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw4 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ - reg_1p0v: ldo2 { - regulator-name = "vdd1p0"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1050000>; - lltc,fb-voltage-divider = <78700 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_AUD_1P8: Audio codec */ - reg_aud_1p8v: ldo3 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - imu@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - st,drdy-int-pin = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imu>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts: touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio5>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* AUD4 */ - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - /* AUD6 */ - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ - >; - }; - - pinctrl_flexcan: flexcangrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ - >; - }; - - pinctrl_imu: imugrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 - >; - }; - - pinctrl_keypad: keypadgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ - >; - }; - - pinctrl_mag: maggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi deleted file mode 100644 index a74cde050158..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ /dev/null @@ -1,793 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_12p0: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "12P0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-tlv320"; - model = "imx-tlv320"; - ssi-controller = <&ssi1>; - audio-codec = <&tlv320aic3105>; - /* routing of sink, source */ - audio-routing = - /* TLV320 LINE1L pin <-> Mic Jack connector */ - "LINE1L", "Mic Jack", - /* board Headphone Jack <-> HPOUT */ - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Mic Jack", "Mic Bias"; - mux-int-port = <1>; - mux-ext-port = <6>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_an1"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - dts1672: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ - reg_1p8v: sw1 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - linux,phandle = <®_vdd_arm>; - }; - - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw4 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - linux,phandle = <®_vdd_soc>; - }; - - /* VDD_1P0 (1+R1/R2 = 1.38): */ - reg_1p0v: ldo2 { - regulator-name = "vdd1p0"; - regulator-min-microvolt = <1002777>; - regulator-max-microvolt = <1002777>; - lltc,fb-voltage-divider = <100000 261000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - tlv320aic3105: codec@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - clocks = <&clks IMX6QDL_CLK_CKO>; - ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ - /* Regulators */ - DRVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <®_1p8v>; - }; - - accelerometer@1d { - compatible = "fsl,mma8451"; - reg = <0x1d>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; - }; - - /* headphone detect */ - ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - ti,micbias = <4>; /* 2.5V micbias */ - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: g101evn010 { - clock-frequency = <68930000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <4>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - max-frequency = <100000000>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - vmmc-supply = <®_3p3v>; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - /* I2C3 */ - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - - /* Headphone Detect */ - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ - - /* Codec */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ - - /* Touch Controller */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ - - /* Stow Sensor */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ - - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi deleted file mode 100644 index 9594bc5745ed..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ /dev/null @@ -1,820 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - ethernet = <&fec>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_an1"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - dts1672: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - magn@1c { - compatible = "st,lsm9ds1-magn"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mag>; - interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - }; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - crypto@60 { - compatible = "atmel,atecc508a"; - reg = <0x60>; - }; - - imu@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - st,drdy-int-pin = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imu>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts: touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - vmmc-supply = <®_3p3v>; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_imu: imugrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_mag: maggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi deleted file mode 100644 index 955a51226eda..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +++ /dev/null @@ -1,536 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_an1"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <0>; - ti,datarate = <5>; - }; - - channel@5 { - reg = <5>; - ti,gain = <0>; - ti,datarate = <5>; - }; - - channel@6 { - reg = <6>; - ti,gain = <0>; - ti,datarate = <5>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi deleted file mode 100644 index 218d6e667ed2..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ /dev/null @@ -1,664 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_wl: regulator-wl { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <3>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <800000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <22100 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_3p0"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_soc"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_1p5"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p8"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_an1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accel@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio7>; - interrupts = <13 0>; - interrupt-names = "INT1"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -/* off-board RS232 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* serial console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* cc1352 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -/* Sterling-LWB Bluetooth */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; -}; - -/* GPS */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -/* Sterling-LWB SDIO WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_wl>; - non-removable; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_accel: accelmuxgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 - >; - }; - - pinctrl_bten: btengrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */ - MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */ - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */ - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */ - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */ - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi deleted file mode 100644 index de5983cf7810..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ /dev/null @@ -1,604 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: led-user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - gw,mode = <0>; - reg = <0x00>; - label = "temp"; - }; - - channel@2 { - gw,mode = <1>; - reg = <0x02>; - label = "vdd_vin"; - }; - - channel@5 { - gw,mode = <1>; - reg = <0x05>; - label = "vdd_3p3"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@b { - gw,mode = <1>; - reg = <0x0b>; - label = "vdd_5p0"; - }; - - channel@e { - gw,mode = <1>; - reg = <0xe>; - label = "vdd_arm"; - }; - - channel@11 { - gw,mode = <1>; - reg = <0x11>; - label = "vdd_soc"; - }; - - channel@14 { - gw,mode = <1>; - reg = <0x14>; - label = "vdd_3p0"; - }; - - channel@17 { - gw,mode = <1>; - reg = <0x17>; - label = "vdd_1p5"; - }; - - channel@1d { - gw,mode = <1>; - reg = <0x1d>; - label = "vdd_1p8"; - }; - - channel@20 { - gw,mode = <1>; - reg = <0x20>; - label = "vdd_1p0"; - }; - - channel@23 { - gw,mode = <1>; - reg = <0x23>; - label = "vdd_2p5"; - }; - }; - - fan-controller@a { - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accel@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio7>; - interrupts = <13 0>; - interrupt-names = "INT1"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_accel: accelmuxgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - >; - }; - - pinctrl_ecspi2: escpi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi deleted file mode 100644 index 82f47c295b08..000000000000 --- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +++ /dev/null @@ -1,498 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-pb { - label = "user_pb"; - gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - user-pb1x { - label = "user_pb1x"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key-erased"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - eeprom-wp { - label = "eeprom_wp"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - tamper { - label = "tamper"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = ; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: led-user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: led-user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <3>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <800000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <22100 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_arm"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_soc"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p5"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_1p0"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_3p0"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_an1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gsc_gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi deleted file mode 100644 index bfade7149080..000000000000 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; - }; - - v_3v2: regulator-v-3v2 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_3v2"; - vin-supply = <&v_5v0>; - }; - - v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_5v0"; - }; - - v_sd: regulator-v-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_vmmc>; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_sd"; - startup-delay-us = <1000>; - vin-supply = <&v_3v2>; - }; - - v_usb2: regulator-v-usb2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb2"; - vin-supply = <&v_5v0>; - }; - - v_usb1: regulator-v-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb1"; - vin-supply = <&v_5v0>; - }; - - audio: sound-sgtl5000 { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board Codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = - "Microphone", "Headphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Headphone Jack", - "Headphone Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - status = "okay"; - - /* Pro baseboard model */ - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - /* Pro baseboard model */ - sgtl5000: codec@a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; - #sound-dai-cells = <0>; - reg = <0x0a>; - VDDA-supply = <&v_3v2>; - VDDIO-supply = <&v_3v2>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -}; - -&iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { - fsl,pins = < - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 - >; - }; - - pinctrl_hummingboard_hdmi: hummingboard-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_i2c2: hummingboard-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { - fsl,pins = < - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 - >; - }; - - pinctrl_hummingboard_pwm1: pwm1grp { - fsl,pins = ; - }; - - pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { - /* - * We want it pulled down for a fixed host connection. - */ - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - >; - }; - - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - pinctrl_hummingboard_vmmc: hummingboard-vmmc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; - reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <&v_usb2>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <&v_usb1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_hummingboard_usdhc2_aux - &pinctrl_hummingboard_usdhc2 - >; - vmmc-supply = <&v_sd>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&vcc_3v3 { - vin-supply = <&v_3v2>; -}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi deleted file mode 100644 index f400405381a7..000000000000 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&iomuxc { - hummingboard2 { - pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; - vmmc-supply = <&v_3v2>; - vqmmc-supply = <&v_3v2>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi deleted file mode 100644 index 0883ef99cded..000000000000 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; - linux,rc-map-name = "rc-rc6-mce"; - }; - - v_3v2: regulator-v-3v2 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_3v2"; - }; - - v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_5v0"; - }; - - vcc_1p8: regulator-vcc-1p8 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "vcc_1p8"; - vin-supply = <&v_3v2>; - }; - - v_sd: regulator-v-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_sd"; - startup-delay-us = <1000>; - vin-supply = <&v_3v2>; - }; - - v_usb1: regulator-v-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb1"; - vin-supply = <&v_5v0>; - }; - - v_usb2: regulator-v-usb2 { - /* USB hub port 1 */ - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb2"; - vin-supply = <&v_5v0>; - }; - - v_usb3: regulator-v-usb3 { - /* USB hub port 3 */ - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb3"; - vin-supply = <&v_5v0>; - }; - - v_usb4: regulator-v-usb4 { - /* USB hub port 4 */ - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb4"; - vin-supply = <&v_5v0>; - }; - - audio: sound-sgtl5000 { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board Codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; - status = "okay"; - - pcf8523: rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sgtl5000: codec@a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <&v_3v2>; - VDDD-supply = <&vcc_1p8>; - VDDIO-supply = <&v_3v2>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hummingboard2 { - pinctrl_hog: hoggrp { - fsl,pins = < - /* - * 36 pin headers GPIO description. The pins - * numbering as following - - * - * 3.2v 5v 74 75 - * 73 72 71 70 - * 69 68 67 66 - * - * 77 78 79 76 - * 65 64 61 60 - * 53 52 51 50 - * 49 48 166 132 - * 95 94 90 91 - * GND 54 24 204 - * - * The GPIO numbers can be extracted using - * signal name from below. - * Example - - * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is - * GPIO(3,10) which is (3-1)*32+10 = gpio 74 - * - * i.e. The mapping of GPIO(X,Y) to Linux gpio - * number is : gpio number = (X-1) * 32 + Y - */ - /* DI1_PIN15 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 - /* DI1_PIN02 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 - /* DISP1_DATA00 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 - /* DISP1_DATA01 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 - /* DISP1_DATA02 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 - /* DISP1_DATA03 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 - /* DISP1_DATA04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 - /* DISP1_DATA05 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 - /* DISP1_DATA06 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 - /* DISP1_DATA07 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 - /* DI1_D0_CS */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 - /* DI1_D1_CS */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 - /* DI1_PIN01 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 - /* DI1_PIN03 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 - /* DISP1_DATA08 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 - /* DISP1_DATA09 */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 - /* DISP1_DATA10 */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 - /* DISP1_DATA11 */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 - /* DISP1_DATA12 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 - /* DISP1_DATA13 */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 - /* DISP1_DATA14 */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 - /* DISP1_DATA15 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 - /* DISP1_DATA16 */ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 - /* DISP1_DATA17 */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 - /* DISP1_DATA18 */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 - /* DISP1_DATA19 */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 - /* DISP1_DATA20 */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 - /* DISP1_DATA21 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 - /* DISP1_DATA22 */ - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 - /* DISP1_DATA23 */ - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 - /* DI1_DISP_CLK */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 - /* SPDIF_IN */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 - /* SPDIF_OUT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 - - /* MikroBUS GPIO pin number 10 */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 - >; - }; - - pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ - >; - }; - - pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 - >; - }; - - pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard2_mipi: hummingboard2_mipi { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 - >; - }; - - pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { - fsl,pins = < - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 - >; - }; - - pinctrl_hummingboard2_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_hummingboard2_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { - /* - * We want it pulled down for a fixed host connection. - */ - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; - - pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - - pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 - >; - }; - - pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 - >; - }; - - pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - - pinctrl_hummingboard2_uart3: hummingboard2-uart3 { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; - reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_pwm3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; - vbus-supply = <&v_usb1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = < - &pinctrl_hummingboard2_usdhc2_aux - &pinctrl_hummingboard2_usdhc2 - >; - pinctrl-1 = < - &pinctrl_hummingboard2_usdhc2_aux - &pinctrl_hummingboard2_usdhc2_100mhz - >; - pinctrl-2 = < - &pinctrl_hummingboard2_usdhc2_aux - &pinctrl_hummingboard2_usdhc2_200mhz - >; - vmmc-supply = <&v_sd>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_uart3>; - status = "okay"; -}; - -&vcc_3v3 { - vin-supply = <&v_3v2>; -}; diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi deleted file mode 100644 index 0fd7f2e24d9c..000000000000 --- a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Jacopo Mondi - */ - -#include "imx6qdl-icore.dtsi" - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi deleted file mode 100644 index d339957cc097..000000000000 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2015 Amarula Solutions B.V. - * Copyright (C) 2015 Engicam S.r.l. - */ - -#include -#include -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sd3_vmmc: regulator-sd3-vmmc { - compatible = "regulator-fixed"; - regulator-name = "P3V3_SD3_SWITCHED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - - reg_sd4_vmmc: regulator-sd4-vmmc { - compatible = "regulator-fixed"; - regulator-name = "P3V3_SD4_SWITCHED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - usb_hub: usb-hub { - compatible = "smsc,usb3503a"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; - clock-names = "refclk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack", - "Speaker", "Line Out Jack", - "Speaker", "Ext Spk"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) - >; - }; - - mux-aud4 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ð_phy>; - phy-mode = "rgmii"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - eth_phy: ethernet-phy@0 { - reg = <0x0>; - rxc-skew-ps = <1140>; - txc-skew-ps = <1140>; - txen-skew-ps = <600>; - rxdv-skew-ps = <240>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <600>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <240>; - txd0-skew-ps = <60>; - txd1-skew-ps = <60>; - txd2-skew-ps = <60>; - txd3-skew-ps = <240>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmmc-supply = <®_sd3_vmmc>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - vmmc-supply = <®_sd4_vmmc>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi deleted file mode 100644 index efe11524b885..000000000000 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -#include -#include -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - chosen { - stdout-path = &uart4; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 100000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - rmii_clk: clock-rmii-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; /* 25MHz for example */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6qdl-icore-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack", - "Speaker", "Line Out Jack", - "Speaker", "Ext Spk"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - - mux-ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) - >; - }; - - mux-aud4 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_3p3v>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_3p3v>; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; - phy-mode = "rmii"; - phy-handle = <ð_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - eth_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - reset-assert-us = <4000>; - reset-deassert-us = <4000>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <®_1p8v>; - AVDD-supply = <®_3p3v>; - DVDD-supply = <®_3p3v>; - powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; - status = "disabled"; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - sgtl5000: codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&mipi_csi { - status = "disabled"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - no-1-8-v; - non-removable; - status = "disabled"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi deleted file mode 100644 index 85aeebc9485d..000000000000 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ /dev/null @@ -1,821 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2017 (C) Priit Laes - * Copyright 2018 (C) Pengutronix, Michael Grzeschik - * Copyright 2019 (C) Pengutronix, Marco Felsch - * - * Based on initial work by Nikita Yushchenko - */ - -#include -#include - -/ { - reg_1p0v_s0: regulator-1p0v-s0 { - compatible = "regulator-fixed"; - regulator-name = "V_1V0_S0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_smarc_suppy>; - }; - - reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { - compatible = "regulator-fixed"; - regulator-name = "V_1V35_VCOREDIG_S5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_1p8v_s5: regulator-1p8v-s5 { - compatible = "regulator-fixed"; - regulator-name = "V_1V8_S5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_3p3v_s0: regulator-3p3v-s0 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_3p3v_s5: regulator-3p3v-s5 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S5"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_smarc_suppy>; - }; - - reg_smarc_lcdbklt: regulator-smarc-lcdbklt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdbklt_en>; - regulator-name = "LCD_BKLT_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_smarc_lcdvdd: regulator-smarc-lcdvdd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdvdd_en>; - regulator-name = "LCD_VDD_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_smarc_rtc: regulator-smarc-rtc { - compatible = "regulator-fixed"; - regulator-name = "V_IN_RTC_BATT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* Module supply range can be 3.00V ... 5.25V */ - reg_smarc_suppy: regulator-smarc-supply { - compatible = "regulator-fixed"; - regulator-name = "V_IN_WIDE"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - lcd: lcd { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - - lcd_out: endpoint { - }; - }; - }; - - lcd_backlight: lcd-backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000 0>; - pwm-names = "LCD_BKLT_PWM"; - - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <4>; - - power-supply = <®_smarc_lcdbklt>; - status = "disabled"; - }; - - i2c_intern: i2c-gpio-intern { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio_intern>; - sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c_lcd: i2c-gpio-lcd { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; - sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_cam: i2c-gpio-cam { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio_cam>; - sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; - -/* I2S0, I2S1 */ -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - - audmux_ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | - IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) - >; - }; - - audmux_adu3 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; - - audmux_ssi2 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) - >; - }; - - audmux_adu4 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) - >; - }; -}; - -/* CAN0 */ -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -/* CAN1 */ -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -/* SPI1 */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, - <&gpio2 27 GPIO_ACTIVE_LOW>; -}; - -/* SPI0 */ -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, - <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - /* default boot source: workaround #1 for errata ERR006282 */ - smarc_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -/* GBE */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <1000>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; -}; - -&i2c_intern { - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - reg_v_core_s0: sw1ab { - regulator-name = "V_CORE_S0"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vddsoc_s0: sw1c { - regulator-name = "V_VDDSOC_S0"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p15v_s0: sw2 { - regulator-name = "V_3V15_S0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* sw3a/b is used in dual mode, but driver does not - * support it. Although, there's no need to control - * DDR power - so just leaving dummy entries for sw3a - * and sw3b for now. - */ - sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v_s0: sw4 { - regulator-name = "V_1V8_S0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* Regulator for USB */ - reg_5p0v_s0: swbst { - regulator-name = "V_5V0_S0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - }; - - reg_vsnvs: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - /* - * Per schematics, of all VGEN's, only VGEN5 has some - * usage ... but even that - over DNI resistor - */ - vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_2p5v_s0: vgen5 { - regulator-name = "V_2V5_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -/* I2C_GP */ -&i2c1 { - clock-frequency = <375000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; -}; - -/* HDMI_CTRL */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; -}; - -/* I2C_PM */ -&i2c3 { - clock-frequency = <375000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - smarc_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - - /* AUDIO MCLK */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - - /* SPI_IMX_CS2# - connected to internal flash */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 - /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ - >; - }; - - pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ - >; - }; - - pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ - >; - }; - - pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 - - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ - >; - }; - - pinctrl_lcdbklt_en: lcdbkltengrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 - >; - }; - - pinctrl_lcdvdd_en: lcdvddengrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_mipi_csi: mipi-csigrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ - >; - }; - - pinctrl_mgmt_gpios: mgmt-gpiosgrp { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ - MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 - /* power, oc muxed but not used by the driver */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wdog1: wdog1rp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; - -&mipi_csi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_csi>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; -}; - -/* LCD_BKLT_PWM */ -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -®_arm { - vin-supply = <®_v_core_s0>; -}; - -®_pu { - vin-supply = <®_vddsoc_s0>; -}; - -®_soc { - vin-supply = <®_vddsoc_s0>; -}; - -/* SER0 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; -}; - -/* SER1 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -/* SER2 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; -}; - -/* SER3 */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; -}; - -/* USB0 */ -&usbotg { - /* - * no 'imx6-usb-charger-detection' - * since USB_OTG_CHD_B pin is not wired - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; -}; - -/* USB1/2 via hub */ -&usbh1 { - vbus-supply = <®_5p0v_s0>; -}; - -/* SDIO */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - no-1-8-v; -}; - -/* SDMMC */ -&usdhc4 { - /* Internal eMMC, optional on some boards */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - vmmc-supply = <®_3p3v_s0>; - vqmmc-supply = <®_1p8v_s0>; -}; - -&wdog1 { - /* CPLD is feeded by watchdog (hardwired) */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi deleted file mode 100644 index 212c623418fc..000000000000 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -#include -#include -#include -#include - -/ { - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc2; - /delete-property/ mmc2; - /delete-property/ mmc3; - rtc0 = &rtc0; - }; - - chosen { - stdout-path = &uart2; - }; - - beeper: gpio-beeper { - compatible = "gpio-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiobeeper>; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - }; - - gpio_buttons: gpio-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiobuttons>; - - button1 { - label = "s6"; - linux,code = ; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button2 { - label = "s7"; - linux,code = ; - gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button3 { - label = "s8"; - linux,code = ; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_mba6_3p3v: regulator-mba6-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-mba6-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regpcie>; - regulator-name = "supply-pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* PCIE.PWR_EN */ - gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_mba6_3p3v>; - }; - - reg_vcc3v3_audio: regulator-vcc3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3-audio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_mba6_3p3v>; - }; - - sound { - compatible = "fsl,imx-audio-tlv320aic32x4"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - model = "imx-audio-tlv320aic32x4"; - ssi-controller = <&ssi1>; - audio-codec = <&tlv320aic32x4>; - audio-asrc = <&asrc>; - audio-routing = - "IN3_L", "Mic Jack", - "Mic Jack", "Mic Bias", - "IN1_L", "Line In Jack", - "IN1_R", "Line In Jack", - "Line Out Jack", "LOL", - "Line Out Jack", "LOR"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - status = "okay"; - - mux-ssi0 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) - >; - }; - - mux-aud3 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; - cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; -}; - -&fec { - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <1000>; - reset-deassert-us = <100000>; - micrel,force-master; - max-speed = <1000>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - tlv320aic32x4: audio-codec@18 { - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - ldoin-supply = <®_vcc3v3_audio>; - iov-supply = <®_mba6_3p3v>; - }; -}; - -/* DDC */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_recovery>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { - compatible = "usb424,2517"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet@1 { - compatible = "usb424,9e00"; - reg = <1>; - nvmem-cells = <&mba_mac_address>; - nvmem-cell-names = "mac-address"; - }; - }; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - power-active-high; - over-current-active-low; - srp-disable; - hnp-disable; - adp-disable; - dr_mode = "otg"; - status = "okay"; -}; - -/* SD card slot */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_mba6_3p3v>; - bus-width = <4>; - no-1-8-v; - no-mmc; - no-sdio; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - /* does not work on unmodified starter kit */ - /* fsl,ext-reset-output; */ - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ - >; - }; - - pinctrl_ecspi1_mba6: ecspimba6grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* FEC phy IRQ */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 - /* FEC phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 - /* DSE = 100, 100k up, SPEED = MED */ - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 - /* DSE = 111, pull 100k up */ - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 - /* DSE = 111, pull external */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 - /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 - >; - }; - - pinctrl_gpiobeeper: gpiobeepergrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 - >; - }; - - pinctrl_gpiobuttons: gpiobuttongrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 - >; - }; - - pinctrl_gpioled: gpioledgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ - >; - }; - - pinctrl_hdmi: hdmigrp { - /* NOTE: DDC is done via I2C2, so DON'T - * configure DDC pins for HDMI! - */ - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 - - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 - - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 - - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 - - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 - - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 - - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 - >; - }; - - pinctrl_i2c2_recovery: i2c2recoverygrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 - >; - }; - - pinctrl_regpcie: regpciegrp { - fsl,pins = < - /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 - /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 - - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - /* Watchdog out */ - MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi deleted file mode 100644 index 27fec340c380..000000000000 --- a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; -}; - -&i2c1 { - lm75: temperature-sensor@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - m24c64_57: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - #address-cells = <1>; - #size-cells = <1>; - - mba_mac_address: mac-address@20 { - reg = <0x20 0x6>; - }; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi deleted file mode 100644 index 0a9f076eeb36..000000000000 --- a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_recovery>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c3 { - lm75: temperature-sensor@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - m24c64_57: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - #address-cells = <1>; - #size-cells = <1>; - - mba_mac_address: mac-address@20 { - reg = <0x20 0x6>; - }; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi deleted file mode 100644 index 6d4eab1942b9..000000000000 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ /dev/null @@ -1,583 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - home { - label = "Home"; - gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; - linux,code = <102>; - }; - - back { - label = "Back"; - gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; - linux,code = <158>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-j14-pin1 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - led-j14-pin3 { - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - led-j14-pins8-9 { - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - led-j46-pin2 { - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - led-j46-pin3 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - }; - - backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight-lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6dl-nit6xlite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6dl-nit6xlite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - rtc@6f { - compatible = "isil,isl1208"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x6f>; - interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j10>; - pinctrl-1 = <&pinctrl_j28>; - - imx6dl-nit6xlite { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Home Button: J14 pin 5 */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Back Button: J14 pin 7 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - /* Touch IRQ: J7 pin 4 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - /* tcs2004 IRQ */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - /* tsc2004 reset */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 - >; - }; - - pinctrl_j10: j10grp { - fsl,pins = < - /* Broadcom WiFi module pins */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - - pinctrl_j28: j28grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi deleted file mode 100644 index 81a9a302aec1..000000000000 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ /dev/null @@ -1,849 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xF0000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_can_xcvr: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - i2c2mux { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2mux>; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH - &gpio4 15 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c2>; - idle-state = <0>; - - i2c2mux@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2mux@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c3mux { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3mux>; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c3>; - idle-state = <0>; - - i2c3mux@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-speaker-enable { - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "off"; - }; - - led-ttymxc4-rs232 { - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "on"; - }; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight-lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds1: backlight-lvds1 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel-lvds1 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds1>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6_max-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; -}; - -&iomuxc { - imx6q-nitrogen6-max { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2mux: i2c2muxgrp { - fsl,pins = < - /* ov5642 camera i2c enable */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 - /* ov5640_mipi camera i2c enable */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - /* PCIe I2C enable */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe reset */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_rv4162: rv4162grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 - /* RS485 RX Enable: pull up */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 - /* RS485 DEN: pull down */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 - /* RS485/!RS232 Select: pull down (rs232) */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 - /* ON: pull down */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - - lvds-channel@1 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi deleted file mode 100644 index 000e9dc97b1a..000000000000 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ /dev/null @@ -1,736 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight-lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds1: backlight-lvds1 { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_lvds1>; - gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - default-on; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel-lvds1 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds1>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - reg_1p8v: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator-wlan-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6_som2-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight_lvds1: backlight-lvds1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - /* PCIe I2C enable */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe reset */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 - >; - }; - - pinctrl_rv4162: rv4162grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi deleted file mode 100644 index 731759bdd7f5..000000000000 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ /dev/null @@ -1,693 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_wlan_vmmc: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6x-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6x-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x2000>; - }; - - partition@c2000 { - label = "splash"; - reg = <0xc2000 0x13e000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-nitrogen6x { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi deleted file mode 100644 index 0020dbb1722c..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik - * Author: Christian Hemp - */ - -/ { - display: display0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0>; - interface-pix-fmt = "rgb24"; - status = "disabled"; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display0_out: endpoint { - remote-endpoint = <&peb_panel_lcd_in>; - }; - }; - }; - - panel-lcd { - compatible = "edt,etm0700g0edh6"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_pwr>; - power-supply = <®_display>; - enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; - status = "disabled"; - - port { - peb_panel_lcd_in: endpoint { - remote-endpoint = <&display0_out>; - }; - }; - }; - - reg_display: regulator-peb-display { - compatible = "regulator-fixed"; - regulator-name = "peb-display"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&i2c1 { - edt_ft5x06: touchscreen@38 { - compatible = "edt,edt-ft5406"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - reg = <0x38>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_NONE>; - status = "disabled"; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_disp0: disp0grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_disp0_pwr: disp0pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_edt_ft5x06: edtft5x06grp { - fsl,pins = < - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi deleted file mode 100644 index 037b60197598..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik - * Author: Christian Hemp - */ - -#include - -/ { - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - status = "disabled"; - - power { - label = "Power Button"; - gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - sleep { - label = "Sleep Button"; - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - user_leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_leds>; - status = "disabled"; - - user-led1 { - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - - user-led2 { - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - - user-led3 { - gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - }; -}; - -&iomuxc { - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 - >; - }; - - pinctrl_user_leds: userledsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi deleted file mode 100644 index 84f884d6e55b..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 PHYTEC Messtechnik GmbH - * Author: Yunus Bas - */ - -#include -#include - -/ { - reg_wl_en: regulator-wl-en { - compatible = "regulator-fixed"; - regulator-name = "wlan_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wl>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - status = "disabled"; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_bt>; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_wl>; - vmmc-supply = <®_wl_en>; - bus-width = <4>; - non-removable; - no-1-8-v; - status = "disabled"; - - brmcf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&iomuxc { - pinctrl_uart3_bt: uart3grp-bt { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */ - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */ - >; - }; - - pinctrl_usdhc3_wl: usdhc3grp-wl { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_wl: wlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi deleted file mode 100644 index 1a599c294ab8..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - - -/ { - aliases { - rtc0 = &i2c_rtc; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_backlight>; - pwms = <&pwm1 0 5000000>; - status = "okay"; - }; - - gpio_leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds>; - status = "disabled"; - - led-red { - label = "phyboard-mira:red"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; - }; - - led-green { - label = "phyboard-mira:green"; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; - }; - - led-blue { - label = "phyboard-mira:blue"; - gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "backlight_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_en_switch: regulator-en-switch { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_en_switch>; - regulator-name = "Enable Switch"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - reg_flexcan1: regulator-flexcan1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_en>; - regulator-name = "flexcan1-reg"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_panel: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "mPCIe_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: usbotg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "auo,g104sn02"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel_en>; - power-supply = <®_panel>; - enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_flexcan1>; - status = "disabled"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmicec>; - ddc-i2c-bus = <&i2c2>; - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <400000>; - status = "disabled"; - - stmpe: touchctrl@44 { - compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - reg = <0x44>; - interrupt-parent = <&gpio7>; - interrupts = <12 IRQ_TYPE_NONE>; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - i2c_rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - reg = <0x68>; - interrupt-parent = <&gpio7>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <100000>; - status = "disabled"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "disabled"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "disabled"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usbotg_vbus>; - disable-over-current; - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - status = "disabled"; -}; - -&iomuxc { - pinctrl_panel_en: panelen1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 - >; - }; - - pinctrl_en_switch: enswitchgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan1_en: flexcan1engrp { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1 - >; - }; - - pinctrl_gpioleds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 - >; - }; - - pinctrl_hdmicec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi deleted file mode 100644 index a41e47c06ef4..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - regulators { - sound_1v8: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "i2s-audio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - sound_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "i2s-audio-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - tlv320_mclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "tlv320-mclk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "OnboardTLV320AIC3007"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "Speaker", "SPOP", - "Speaker", "SPOM", - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&tlv320_mclk>; - }; - }; - -}; - -&audmux { - status = "okay"; - - mux-ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4)) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - codec: tlv320@18 { - compatible = "ti,tlv320aic3007"; - #sound-dai-cells = <0>; - reg = <0x18>; - ai3x-micbias-vg = <2>; - - AVDD-supply = <&sound_3v3>; - IOVDD-supply = <&sound_3v3>; - DRVDD-supply = <&sound_3v3>; - DVDD-supply = <&sound_1v8>; - }; - - stmpe@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - }; - - rtc@51 { - compatible = "epson,rtc8564"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - reg = <0x64>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi deleted file mode 100644 index 80adb2a02cc9..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - enable-active-high; - }; - }; - - gpio_leds: leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - compatible = "gpio-leds"; - - led_green: led-green { - label = "phyflex:green"; - gpios = <&gpio1 30 0>; - }; - - led_red: led-red { - label = "phyflex:red"; - gpios = <&gpio2 31 0>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - - som_flash: flash@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-duration = <10>; /* in msecs */ - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - phy-supply = <&vdd_eth_io_reg>; - status = "disabled"; - - fec_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - som_eeprom: eeprom@50 { - compatible = "catalyst,24c32", "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pmic@58 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ - interrupt-controller; - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - - da9063_rtc: rtc { - compatible = "dlg,da9063-rtc"; - }; - - da9063_wdog: watchdog { - compatible = "dlg,da9063-watchdog"; - }; - - onkey { - compatible = "dlg,da9063-onkey"; - status = "disabled"; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; -}; - -&iomuxc { - imx6q-phytec-pfla02 { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = ; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = ; /* PMIC interrupt */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_sd1_reg>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_sd0_reg>; - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi deleted file mode 100644 index 28a805384668..000000000000 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ /dev/null @@ -1,311 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -#include -#include - -/ { - aliases { - rtc1 = &da9062_rtc; - rtc2 = &snvs_rtc; - }; - - /* - * Set the minimum memory size here and - * let the bootloader set the real size. - */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x8000000>; - }; - - gpio_leds_som: somleds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds_som>; - - som-led-green { - label = "phycore:green"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - m25p80: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - status = "disabled"; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-supply = <&vdd_eth_io>; - phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "st,24c32", "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pmic: pmic@58 { - compatible = "dlg,da9062"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - - da9062_rtc: rtc { - compatible = "dlg,da9062-rtc"; - }; - - da9062_onkey: onkey { - compatible = "dlg,da9062-onkey"; - }; - - watchdog { - compatible = "dlg,da9062-watchdog"; - dlg,use-sw-pm; - }; - - thermal { - compatible = "dlg,da9062-thermal"; - status = "disabled"; - }; - - gpio { - compatible = "dlg,da9062-gpio"; - status = "disabled"; - }; - - regulators { - vdd_arm: buck1 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1380000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_soc: buck2 { - regulator-name = "vdd_soc"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1380000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_ddr3_1p5: buck3 { - regulator-name = "vdd_ddr3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_eth_1p2: buck4 { - regulator-name = "vdd_eth"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_snvs: ldo1 { - regulator-name = "vdd_snvs"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_high: ldo2 { - regulator-name = "vdd_high"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_eth_io: ldo3 { - regulator-name = "vdd_eth_io"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vdd_emmc_1p8: ldo4 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -®_arm { - vin-supply = <&vdd_arm>; -}; - -®_pu { - vin-supply = <&vdd_soc>; -}; - -®_soc { - vin-supply = <&vdd_soc>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "disabled"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - >; - }; - - pinctrl_gpioleds_som: gpioledssomgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 - MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi b/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi deleted file mode 100644 index 3a968782e854..000000000000 --- a/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2017 NXP - -#include "imx6qdl-pico.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - -&i2c1 { - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&i2c2 { - io-expander@25 { - compatible = "nxp,pca9554"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi b/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi deleted file mode 100644 index 144c4727fbc7..000000000000 --- a/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2017 NXP - -#include "imx6qdl-pico.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - -&i2c2 { - status = "okay"; - - adc081c: adc@50 { - compatible = "ti,adc081c"; - reg = <0x50>; - vref-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi b/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi deleted file mode 100644 index 3d56a4216448..000000000000 --- a/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT - -#include "imx6qdl-pico.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - -&i2c1 { - adc@52 { - compatible = "ti,adc081c"; - reg = <0x52>; - vref-supply = <®_2p5v>; - }; -}; - -&i2c2 { - io-expander@25 { - compatible = "nxp,pca9554"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; -}; - -&i2c3 { - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -&pcie { - status = "okay"; -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi b/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi deleted file mode 100644 index b823dce62e63..000000000000 --- a/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2017 NXP - -#include "imx6qdl-pico.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - -&hdmi { - status = "disabled"; -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/imx6qdl-pico.dtsi deleted file mode 100644 index c39a9ebdaba1..000000000000 --- a/arch/arm/boot/dts/imx6qdl-pico.dtsi +++ /dev/null @@ -1,627 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2018 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_1p5v: regulator-1p5v { - compatible = "regulator-fixed"; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_2p8v: regulator-2p8v { - compatible = "regulator-fixed"; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - }; - - codec_osc: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6-pico-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 50000 0>; - brightness-levels = <0 36 72 108 144 180 216 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel { - compatible = "vxt,vl050-8048nt-c01"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@1 { - reg = <1>; - qca,clk-out-frequency = <125000000>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: audio-codec@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&codec_osc>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_1p8v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio5>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - wakeup-source; - }; - - camera@3c { - compatible = "ovti,ov5645"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5645>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-frequency = <24000000>; - vdddo-supply = <®_1p8v>; - vdda-supply = <®_2p8v>; - vddd-supply = <®_1p5v>; - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - - port { - ov5645_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5645_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reset>; - reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { /* Bluetooth module */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { /* Wifi/BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - keep-power-in-suspend; - non-removable; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ov5645: ov5645grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 - >; - }; - - pinctrl_pcie_reset: pciegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_lcd: reglcdgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi deleted file mode 100644 index 36f84f4da6b0..000000000000 --- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&can1 { - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b008 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b008 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi deleted file mode 100644 index f804ff95a6ad..000000000000 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led0: led-usr { - label = "usr"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "fsl,imx6-rex-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-rex-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&ecspi3 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pca9535: gpio-expander@27 { - compatible = "nxp,pca9535"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9535>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-rex { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - /* user led */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_pca9535: pca9535grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - /* power enable, high active */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - /* CD */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* WP */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - /* CD */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - /* WP */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 - >; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi deleted file mode 100644 index 68e97180d33e..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ /dev/null @@ -1,864 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-user { - label = "debug"; - gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - home { - label = "Home"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - back { - label = "Back"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - program { - label = "Program"; - gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - clocks { - codec_osc: anaclk2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; - }; - - sound-cs42888 { - compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; - model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; - audio-codec = <&codec>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif", - "fsl,imx-sabreauto-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; - - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3mux>; - mux-gpios = <&gpio5 4 0>; - i2c-parent = <&i2c3>; - idle-state = <0>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adv7180: camera@21 { - compatible = "adi,adv7180"; - reg = <0x21>; - powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; - - max7310_a: gpio@30 { - compatible = "maxim,max7310"; - reg = <0x30>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_b: gpio@32 { - compatible = "maxim,max7310"; - reg = <0x32>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_max7310>; - reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - max7310_c: gpio@34 { - compatible = "maxim,max7310"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - }; - - magnetometer@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - }; - - accelerometer@1c { - compatible = "fsl,mma8451"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mma8451_int>; - interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_PLL4_BYPASS>, - <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_PLL4_POST_DIV>; - assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, - <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; - status = "disabled"; /* pin conflict with WEIM NOR */ - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&esai { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esai>; - assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, - <&clks IMX6QDL_CLK_ESAI_EXTAL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - fsl,magic-packet; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "disabled"; /* pin conflict with fec */ -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - codec: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&codec_osc>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; - }; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_egalax_int>; - interrupt-parent = <&gpio2>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-sabreauto { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1_cs: ecspi1cs { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - >; - }; - - pinctrl_egalax_int: egalax-intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_esai: esaigrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 - MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 - MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 - MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 - MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_max7310: max7310grp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - >; - }; - - pinctrl_mma8451_int: mma8451intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 - >; - }; - - pinctrl_pwm3: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_gpt_input_capture0: gptinputcapture0grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 - >; - }; - - pinctrl_gpt_input_capture1: gptinputcapture1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor: weimnorgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - ranges = <0 0 0x08000000 0x08000000>; - status = "disabled"; /* pin conflict with SPI NOR */ - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi deleted file mode 100644 index 12573e1f917c..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ /dev/null @@ -1,748 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - */ - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_1p5v: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_1p8v: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p8v: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - mipi_xclk: mipi_xclk { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <22000000>; - clock-output-names = "mipi_pwm3"; - pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vync-active = <1>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ov5640: camera@40 { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x40>; - clocks = <&mipi_xclk>; - clock-names = "xclk"; - DOVDD-supply = <®_1p8v>; - AVDD-supply = <®_2p8v>; - DVDD-supply = <®_1p5v>; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */ - powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */ - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - ov5642: camera@42 { - compatible = "ovti,ov5642"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; - clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-names = "xclk"; - reg = <0x42>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - port { - ov5642_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-sabrelite { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 - >; - }; - - pinctrl_ov5642: ov5642grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi deleted file mode 100644 index 4fe58764b929..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ /dev/null @@ -1,851 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply"; - gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sensors: regulator-sensors { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensors_reg>; - regulator-name = "sensors-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-sabresd-wm8962", - "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-asrc = <&asrc>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC", - "DMIC", "MICBIAS", - "DMICDAT", "DMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; - mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-red { - gpios = <&gpio1 2 0>; - default-state = "on"; - }; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vsync-active = <1>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&phy>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@1 { - reg = <1>; - qca,clk-out-frequency = <125000000>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - accelerometer@1c { - compatible = "fsl,mma8451"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <®_sensors>; - vddio-supply = <®_sensors>; - }; - - ov5642: camera@3c { - compatible = "ovti,ov5642"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - reg = <0x3c>; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 - rev B board is VGEN5 */ - DVDD-supply = <&vgen2_reg>; /* 1.5v*/ - powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - status = "disabled"; - - port { - ov5642_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_egalax_int>; - interrupt-parent = <&gpio6>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; - }; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 - rev B board is VGEN5 */ - DVDD-supply = <&vgen2_reg>; /* 1.5v*/ - powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio6>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - }; - - magnetometer@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; - interrupt-parent = <&gpio3>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - vdd-supply = <®_sensors>; - vddio-supply = <®_sensors>; - }; - - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; - interrupt-parent = <&gpio3>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <®_sensors>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-sabresd { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 - >; - }; - - pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 - >; - }; - - pinctrl_ov5642: ov5642grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_sensors_reg: sensorsreggrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; - }; - - gpio_leds { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -®_vdd1p1 { - vin-supply = <&vgen5_reg>; -}; - -®_vdd2p5 { - vin-supply = <&vgen5_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi deleted file mode 100644 index 02e6d36e85fa..000000000000 --- a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (C) 2017 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - label = "Power Button"; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "avic,tm097tdh02", "hannstar,hsd100pxn1"; - backlight = <&panel_bl>; - power-supply = <®_3p3v>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel_bl: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <4>; - power-supply = <®_3p3v>; - pwms = <&pwm1 0 10000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - reg = <0>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -/* SD card */ -&usdhc3 { - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd>; - status = "okay"; -}; - -/* eMMC */ -&usdhc4 { - bus-width = <8>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_emmc: emmcgrp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* PHY reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_sd: sdgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - /* CD pin */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi deleted file mode 100644 index b81799d7076a..000000000000 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -/ { - touchscreen { - compatible = "resistive-adc-touch"; - io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; - io-channel-names = "y", "z1", "z2", "x"; - touchscreen-min-pressure = <65000>; - touchscreen-inverted-y; - touchscreen-swapped-x-y; - touchscreen-x-plate-ohms = <300>; - touchscreen-y-plate-ohms = <800>; - }; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - status = "okay"; - - adc_ts: adc@0 { - compatible = "ti,tsc2046e-adc"; - reg = <0>; - pinctrl-0 = <&pinctrl_touch>; - pinctrl-names ="default"; - spi-max-frequency = <1000000>; - interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@1 { - reg = <1>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@3 { - reg = <3>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@4 { - reg = <4>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - - channel@5 { - reg = <5>; - settling-time-us = <700>; - oversampling-ratio = <5>; - }; - }; -}; - -&iomuxc { - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x000b1 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x000b1 - /* *no* external pull up */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x40000058 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - /* external pull up */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x10040 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi deleted file mode 100644 index 2731faede1cb..000000000000 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2020 Pengutronix, Ulrich Oelmann - -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - aliases { - can0 = &can1; - can1 = &can2; - mdio-gpio0 = &mdio; - nand = &gpmi; - rtc0 = &i2c_rtc; - rtc1 = &snvs; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, /* 24V */ - <&adc 1>; /* temperature */ - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "D1"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_STATUS; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "D2"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "D3"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mdio: mdio { - compatible = "microchip,mdio-smi0"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio>; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, - <&gpio1 22 GPIO_ACTIVE_HIGH>; - - switch@0 { - compatible = "microchip,ksz8873"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - interrupt-parent = <&gpio3>; - interrupt = <30 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - ports@0 { - reg = <0>; - phy-mode = "internal"; - label = "lan1"; - }; - - ports@1 { - reg = <1>; - phy-mode = "internal"; - label = "lan2"; - }; - - ports@2 { - reg = <2>; - label = "cpu"; - ethernet = <&fec>; - phy-mode = "rmii"; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - - }; - - clk50m_phy: phy-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet_ref_pad"; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - vin-supply = <®_5v0>; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_24v0: regulator-24v0 { - compatible = "regulator-fixed"; - regulator-name = "24v0"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_stby>; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2_stby>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; - }; - - reg_tft_vcom: regulator-tft-vcom { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 20000 0>; - regulator-name = "tft_vcom"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - voltage-table = <3600000 26>; - }; - - reg_vcc_mmc: regulator-vcc-mmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_mmc>; - vin-supply = <®_3v3>; - regulator-name = "mmc_vcc_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - }; - - reg_vcc_mmc_io: regulator-vcc-mmc-io { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_mmc_io>; - vin-supply = <®_5v0>; - regulator-name = "mmc_io_supply"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - states = <1800000 0x1>, <3300000 0x0>; - startup-delay-us = <100>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <54000000>; - reg = <0>; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - status = "okay"; - - adc: adc@0 { - compatible = "microchip,mcp3002"; - reg = <0>; - vref-supply = <®_3v3>; - spi-max-frequency = <1000000>; - #io-channel-cells = <1>; - }; -}; - -&clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; - assigned-clock-parents = <&clk50m_phy>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-supply = <®_3v3>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - i2c_rtc: rtc@51 { - compatible = "nxp,pcf85063"; - reg = <0x51>; - quartz-load-femtofarads = <12500>; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <2>; - status = "okay"; -}; - -&pwm3 { - /* used for LCD contrast control */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_5v0>; - disable-over-current; - status = "okay"; -}; - -/* no usbh2 */ -&usbphynop1 { - status = "disabled"; -}; - -/* no usbh3 */ -&usbphynop2 { - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_5v0>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - cap-power-off-card; - full-pwr-cycle; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - mmc-ddr-1_8v; - vmmc-supply = <®_vcc_mmc>; - vqmmc-supply = <®_vcc_mmc_io>; - status = "okay"; -}; - -&iomuxc { - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000 - >; - }; - - pinctrl_can1_stby: can1stbygrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - >; - }; - - pinctrl_can2_stby: can2stbygrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1 - /* *no* external pull up */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1 - /* external pull up */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* RMII 50 MHz */ - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58 - /* GPIO for "link active" */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - /* external 10 k pull up */ - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878 - /* external 10 k pull up */ - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878 - >; - }; - - pinctrl_mdio: mdiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1 - MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58 - >; - }; - - pinctrl_switch: switchgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - /* SoC internal pull up required */ - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - /* SoC internal pull up required */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040 - /* SoC internal pull up required */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040 - >; - }; - - pinctrl_vcc_mmc: vccmmcgrp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58 - >; - }; - - pinctrl_vcc_mmc_io: vccmmciogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi b/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi deleted file mode 100644 index 48c9ce051f47..000000000000 --- a/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2021 Pengutronix, Oleksij Rempel - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; - pwms = <&pwm2 0 20000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <17>; - default-brightness-level = <8>; - power-supply = <®_24v0>; - }; - - display { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel { - compatible = "logictechno,lttd800480070-l2rt"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display0_out>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-solidsense.dtsi b/arch/arm/boot/dts/imx6qdl-solidsense.dtsi deleted file mode 100644 index 234827e554d0..000000000000 --- a/arch/arm/boot/dts/imx6qdl-solidsense.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2021 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_solidsense_leds>; - - /* Red/Green LED1 - next to WiFi SMA */ - led-11 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - }; - - led-12 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - }; - - /* Red/Green LED2 - next to GPS SMA */ - led-21 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - }; - - led-22 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&audio { - status = "disabled"; -}; - -&ecspi2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>, <&pinctrl_solidsense_hog>; - - solidsense { - pinctrl_solidsense_hog: solidsense-hog { - fsl,pins = < - /* Nordic RESET_N */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x400130b1 - /* Nordic Chip 1 SWDIO - GPIO 125 */ - MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x400130b1 - /* Nordic Chip 1 SWDCLK - GPIO 59 */ - /* already claimed in the HB2 hogs */ - /* MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 */ - /* Nordic Chip 2 SWDIO - GPIO 81 */ - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x400130b1 - /* Nordic Chip 2 SWCLK - GPIO 82 */ - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x400130b1 - >; - }; - - pinctrl_solidsense_leds: solidsense-leds { - fsl,pins = < - /* Red LED 1 - GPIO 58 */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x400130b1 - /* Green LED 1 - GPIO 55 */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x400130b1 - /* Red LED 2 - GPIO 57 */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x400130b1 - /* Green LED 2 - GPIO 56 */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x400130b1 - >; - }; - - pinctrl_solidsense_uart2: solidsense-uart2 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_solidsense_uart3: solidsense-uart3 { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - }; -}; - -&pwm1 { - status = "disabled"; -}; - -&sgtl5000 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_solidsense_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_solidsense_uart3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi deleted file mode 100644 index b55af61dfeca..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -/ { - clk_brcm: brcm-clock { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_osc>; - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - reg_brcm: brcm-reg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, - <&gpio6 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_brcm>; - clock-names = "ext_clock"; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_brcm_bt: microsom-brcm-bt { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 - >; - }; - - pinctrl_microsom_brcm_osc: microsom-brcm-osc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 - >; - }; - - pinctrl_microsom_brcm_reg: microsom-brcm-reg { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 - >; - }; - - pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { - fsl,pins = < - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 - >; - }; - - pinctrl_microsom_uart4: microsom-uart4 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_microsom_usdhc1: microsom-usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - }; -}; - -/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi deleted file mode 100644 index 5f3b8baab20f..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&iomuxc { - microsom { - pinctrl_microsom_usdhc3: microsom-usdhc3 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - }; -}; - -/* USDHC3 - eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_usdhc3>; - bus-width = <8>; - non-removable; - vmmc-supply = <&vcc_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi deleted file mode 100644 index 352ac585ca6b..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - nvcc_sd1: regulator-nvcc-sd1 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "nvcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; - - clk_ti_wifi: ti-wifi-clock { - /* This is a hack around the kernel - using "fixed clock" - * results in the "pinctrl" properties being ignored, and - * the clock not being output. Instead, use a gated clock - * and the unrouted WL_XTAL_PU gpio. - */ - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_clk>; - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - pwrseq_ti_wifi: ti-wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>; - reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - clocks = <&clk_ti_wifi>; - clock-names = "ext_clock"; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_ti_bt: microsom-ti-bt { - fsl,pins = < - /* BT_EN_SOC */ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 - >; - }; - - pinctrl_microsom_ti_clk: microsom-ti-clk { - fsl,pins = < - /* EXT_32K */ - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 - /* WL_XTAL_PU (unrouted) */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 - >; - }; - - pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { - fsl,pins = < - /* WLAN_EN_SOC */ - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 - >; - }; - - pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { - fsl,pins = < - /* WLAN_IRQ */ - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 - >; - }; - - pinctrl_microsom_uart4: microsom-uart4 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_microsom_usdhc1: microsom-usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - }; -}; - -/* UART4 - Connected to optional TI Wi-Fi/BT/FM */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart4>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - clocks = <&clk_ti_wifi>; - clock-names = "ext_clock"; - enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_bt>; - }; -}; - -/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_usdhc1>; - bus-width = <4>; - keep-power-in-suspend; - mmc-pwrseq = <&pwrseq_ti_wifi>; - cap-power-off-card; - non-removable; - vmmc-supply = <&vcc_3v3>; - /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi deleted file mode 100644 index ce543e325cd3..000000000000 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; - phy-mode = "rgmii-id"; - - /* - * The PHY seems to require a long-enough reset duration to avoid - * some rare issues where the PHY gets stuck in an inconsistent and - * non-functional state at boot-up. 10ms proved to be fine . - */ - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* - * The PHY can appear at either address 0 or 4 due to the - * configuration (LED) pin not being pulled sufficiently. - */ - ethernet-phy@0 { - reg = <0>; - qca,clk-out-frequency = <125000000>; - qca,smarteee-tw-us-1g = <24>; - }; - - ethernet-phy@4 { - reg = <4>; - qca,clk-out-frequency = <125000000>; - qca,smarteee-tw-us-1g = <24>; - }; - - /* - * ADIN1300 (som rev 1.9 or later) is always at address 1. It - * will be enabled automatically by U-Boot if detected. - */ - ethernet-phy@1 { - reg = <1>; - adi,phy-output-clock = "125mhz-free-running"; - status = "disabled"; - }; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - - /* - * As the RMII pins are also connected to RGMII - * so that an AR8030 can be placed, set these - * to high-z with the same pulls as above. - * Use the GPIO settings to avoid changing the - * input select registers. - */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 - >; - }; - - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi deleted file mode 100644 index 344ea935c7da..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel - */ - -#include -#include - -/ { - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - m25p80: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - m25p,fast-read; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 - /* eCSPI1 SS1 */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 - >; - }; - - pinctrl_i2c1_recovery: i2c1recoverygrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 - >; - }; - - pinctrl_i2c3_recovery: i2c3recoverygrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; - -&pmic { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_vddcore: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_vddsoc: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_gen_3v3: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_ddr_1v5a: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_1v5b: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5v_600mA: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-always-on; - }; - - reg_snvs_3v: vsnvs { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1_1v5: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - /* not used */ - }; - - reg_vgen2_1v2_eth: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - reg_vgen3_2v8: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen4_1v8: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5_1v8_eth: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6_3v3: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - disable-wp; - no-sd; - no-sdio; - bus-width = <8>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi deleted file mode 100644 index aff46f3040c1..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel - */ - -#include - -&fec { - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_recovery>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - }; - - sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <®_3p3v>; - }; -}; - -&iomuxc { - /* - * This pinmuxing is required for the ERR006687 workaround. Board - * DTS files that enable the FEC controller with - * fsl,err006687-workaround-present must include this group. - */ - pinctrl_enet_fix: enetfixgrp { - fsl,pins = < - /* ENET ping patch */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi deleted file mode 100644 index a3f6543c3aaa..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel - */ - -#include - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - }; - - sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <®_3p3v>; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi deleted file mode 100644 index f88da757edda..000000000000 --- a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi +++ /dev/null @@ -1,479 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - aliases { - ethernet0 = &fec; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; - compatible = "gpio-leds"; - - green-led { - label = "green-led"; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - red-led { - label = "red-led"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - isl12022: rtc@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; - - gpio8: gpio@28 { - compatible = "technologic,ts4900-gpio"; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - ngpio = <32>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ - MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 - MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 - MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 - MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 - MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_leds1: leds1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - fsl,wp-controller; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi deleted file mode 100644 index 1e0a041e9f60..000000000000 --- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi +++ /dev/null @@ -1,594 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-Faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; - compatible = "gpio-leds"; - - green-led { - label = "green-led"; - gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - red-led { - label = "red-led"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yel-led { - label = "yellow-led"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-led { - label = "blue-led"; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - en-usb-5v-led { - label = "en-usb-5v"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - sel-dc-usb-led { - label = "sel_dc_usb"; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_3v3: reg_can1_3v3 { - compatible = "regulator-fixed"; - regulator-name = "reg_can1_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_3v3: en-reg_can2_3v3 { - compatible = "regulator-fixed"; - regulator-name = "reg_can2_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator_wlan_vmmc { - compatible = "regulator-fixed"; - regulator-name = "wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - sound-sgtl5000 { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "On-board Codec"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_3v3>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = < - &gpio5 31 GPIO_ACTIVE_LOW - &gpio7 12 GPIO_ACTIVE_LOW - &gpio5 18 GPIO_ACTIVE_LOW - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - m41t00s: rtc@68 { - compatible = "m41t00"; - reg = <0x68>; - }; - - isl12022: rtc@6f { - compatible = "isl,isl12022"; - reg = <0x6f>; - }; - - gpio8: gpio@28 { - compatible = "technologic,ts7970-gpio"; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <62>; - }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */ - >; - }; - - pinctrl_ecspi2: ecspi2 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */ - MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */ - >; - }; - - pinctrl_enet: enet { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */ - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* Onboard */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */ - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */ - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */ - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */ - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */ - - /* Offboard */ - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */ - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */ - - /* Strapping only */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_leds1: leds1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */ - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -/* WIFI */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_wlan_vmmc>; - bus-width = <4>; - non-removable; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - fsl,wp-controller; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi deleted file mode 100644 index 79f2354886b7..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_pwr>; - enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - turn-on-delay-ms = <35>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - lcd_panel: lcd-panel { - compatible = "edt,etm0700g0dh6"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_out>; - }; - }; - }; - - display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - u-boot,panel-name = "edt,et057090dhu"; - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - u-boot,panel-name = "edt,et0350g0dh6"; - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - u-boot,panel-name = "edt,et0430g0dh6"; - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - u-boot,panel-name = "edt,etm0700g0dh6"; - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - CoMTFT { /* same as ET0700 but with inverted pixel clock */ - u-boot,panel-name = "edt,etm0700g0edh6"; - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_in>; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi deleted file mode 100644 index 2ca2eb37e14f..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - lvds0_panel: lvds0-panel { - compatible = "nlt,nl12880bc20-spwg-24"; - backlight = <&backlight0>; - power-supply = <®_3v3>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - lvds1_panel: lvds1-panel { - compatible = "nlt,nl12880bc20-spwg-24"; - backlight = <&backlight1>; - power-supply = <®_3v3>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; -}; - -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - - display-timings { - hsd100pxn1 { - u-boot,panel-name = "hannstar,hsd100pxn1"; - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - nl12880bc20 { - u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0700 { - u-boot,panel-name = "edt,etm0700g0dh6"; - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - u-boot,panel-name = "edt,et057090dhu"; - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - - display-timings { - hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -®_lcd0_pwr { - status = "okay"; -}; - -®_lcd1_pwr { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi deleted file mode 100644 index 99ec7a838f8d..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - backlight0 { - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - turn-on-delay-ms = <35>; - power-supply = <®_lcd1_pwr>; - }; - - backlight1 { - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - turn-on-delay-ms = <35>; - power-supply = <®_lcd1_pwr>; - }; - - lcd-panel { - compatible = "edt,et057090dhu"; - pixelclk-active = <0>; - }; - - lvds0-panel { - compatible = "edt,etml1010g0dka"; - pixelclk-active = <0>; - }; - - lvds1-panel { - compatible = "edt,etml1010g0dka"; - pixelclk-active = <0>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - /* - * The backup voltage of the module internal RTC is not wired - * by default on the MB7, so disable that RTC chip. - */ - status = "disabled"; -}; - -&i2c3 { - rtc: rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -®_lcd0_pwr { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi deleted file mode 100644 index e2fe337f7d9e..000000000000 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ /dev/null @@ -1,792 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -/ { - aliases { - can0 = &can2; - can1 = &can1; - ethernet0 = &fec; - lcdif-23bit-pins-a = &pinctrl_disp0_1; - lcdif-24bit-pins-a = &pinctrl_disp0_2; - pwm0 = &pwm1; - pwm1 = &pwm2; - reg-can-xcvr = ®_can_xcvr; - stk5led = &user_led; - usbotg = &usbotg; - sdhc0 = &usdhc1; - sdhc1 = &usdhc2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; /* will be filled by U-Boot */ - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power Button"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led: led-user { - label = "Heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_led>; - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3_etn: regulator-3v3-etn { - compatible = "regulator-fixed"; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - }; - - reg_lcd0_pwr: regulator-lcd0-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_lcd1_pwr: regulator-lcd1-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_pwr>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "karo,imx6qdl-tx6-sgtl5000", - "simple-audio-card"; - simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = < - &gpio2 30 GPIO_ACTIVE_HIGH - &gpio3 19 GPIO_ACTIVE_HIGH - >; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - phy-reset-post-delay = <10>; - phy-handle = <&etnphy>; - phy-supply = <®_3v3_etn>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_int>; - interrupt-parent = <&gpio7>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - clock-frequency = <400000>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - trickle-resistor-ohms = <250>; - trickle-diode-disable; - }; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 0>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ - >; - }; - - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 - MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; - - pinctrl_enet_mdio: enet-mdiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - >; - }; - - pinctrl_etnphy_int: etnphy-intgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ - >; - }; - - pinctrl_etnphy_rst: etnphy-rstgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3-gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 - MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 - MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 - MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 - MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 - MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 - MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 - MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 - >; - }; - - pinctrl_lcd0_pwr: lcd0-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ - >; - }; - - pinctrl_lcd1_pwr: lcd-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart1_rtscts: uart1_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2_rtscts: uart2_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_rtscts: uart3_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 - MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ - >; - }; - - pinctrl_user_led: user-ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ - >; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0,1 are mapped to KPP row/col 6,7 */ - linux,keymap = < - MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ - MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ - MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ - MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ - MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ - MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ - MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ - MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ - MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ - MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ - MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ - >; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi deleted file mode 100644 index 93a8123da27d..000000000000 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include - -/ { - aliases { - backlight = &backlight; - panelchan = &panelchan; - panel7 = &panel7; - touchscreenp7 = &touchscreenp7; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio1 4 0>; - default-on; - status = "disabled"; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio2 4 0>; - pinctrl-0 = <&pinctrl_power_off>; - pinctrl-names = "default"; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - panel7: panel7 { - /* - * in reality it is a -20t (parallel) model, - * but with LVDS bridge chip attached, - * so it is equivalent to -19t model in drive - * characteristics - */ - compatible = "urt,umsh-8596md-19t"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel>; - power-supply = <®_panel>; - backlight = <&backlight>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_h1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ - gpio = <&gpio7 12 0>; - }; - - reg_panel: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd_panel"; - enable-active-high; - gpio = <&gpio1 2 0>; - }; - }; - - sound { - compatible = "fsl,imx6q-udoo-ac97", - "fsl,imx-audio-ac97"; - model = "fsl,imx6q-udoo-ac97"; - audio-cpu = <&ssi1>; - audio-routing = - "RX", "Mic Jack", - "Headphone Jack", "TX"; - mux-int-port = <1>; - mux-ext-port = <6>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreenp7: touchscreenp7@55 { - compatible = "sitronix,st1232"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreenp7>; - reg = <0x55>; - interrupt-parent = <&gpio1>; - interrupts = <13 8>; - gpios = <&gpio1 15 0>; - status = "disabled"; - }; -}; - -&iomuxc { - imx6q-udoo { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_panel: panelgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 - >; - }; - - pinctrl_power_off: poweroffgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 - >; - }; - - pinctrl_touchscreenp7: touchscreenp7grp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh: usbhgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 - >; - }; - - pinctrl_usbotg: usbotg { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_ac97_running: ac97running { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ac97_warm_reset: ac97warmreset { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ac97_reset: ac97reset { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - panelchan: lvds-channel@0 { - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh>; - vbus-supply = <®_usb_h1_vbus>; - clocks = <&clks IMX6QDL_CLK_CKO>; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&audmux { - status = "okay"; -}; - -&ssi1 { - cell-index = <0>; - fsl,mode = "ac97-slave"; - pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; - pinctrl-0 = <&pinctrl_ac97_running>; - pinctrl-1 = <&pinctrl_ac97_reset>; - pinctrl-2 = <&pinctrl_ac97_warm_reset>; - ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi deleted file mode 100644 index 200559d7158d..000000000000 --- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Support for Variscite DART-MX6 Module - * - * Copyright 2017 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <70000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(2)) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "disabled"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmicec>; - ddc-i2c-bus = <&i2c1>; - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - tlv320aic3106: codec@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - #sound-dai-cells = <0>; - DRVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <®_3p3v>; - ai3x-ocmv = <0>; - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&iomuxc { - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - /* Audio Clock */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_bt: bt { - fsl,pins = < - /* Bluetooth enable */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1 - /* Bluetooth Slow Clock */ - MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - /* SPI1 CS0 */ - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - /* SPI1 CS1 */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_hdmicec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC INT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* WL_EN */ - MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071 - /* WL_IRQ */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - fsl,tx-swing-full = <103>; - fsl,tx-swing-low = <103>; - reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbh1 { - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi deleted file mode 100644 index 73f381e14467..000000000000 --- a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 Protonic Holland - */ - -/ { - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power-button { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi deleted file mode 100644 index 96e4f4b0b248..000000000000 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ /dev/null @@ -1,712 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -#include -#include -#include -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - backlight_led: backlight-led { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - }; - - /* only for backwards compatibility with old HW */ - backlight_isb: backlight-isb { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 5000000 0>; - brightness-levels = <0 8 48 255>; - num-interpolated-steps = <5>; - default-brightness-level = <0>; - power-supply = <®_3v3>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - counter-0 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter0>; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - - counter-1 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter1>; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - counter-2 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter2>; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-3 { - label = "isb_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; - }; - }; - - thermal-zones { - chassis-thermal { - polling-delay = <20000>; - polling-delay-passive = <0>; - thermal-sensors = <&tsens0>; - - trips { - alert { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - termination-ohms = <150>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&gpio2 { - gpio-line-names = - "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", - "", "LED_PWM", "", "", "", - "", "", "", - "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; -}; - -&gpio7 { - gpio-line-names = - "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", - "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", - "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", - "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video-decoder@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_counter0: counter0grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 - >; - }; - - pinctrl_counter1: counter1grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 - >; - }; - - pinctrl_counter2: counter2grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - /* ISB_LED */ - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - >; - }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi deleted file mode 100644 index e781a45785ed..000000000000 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. -// -// Author: Fabio Estevam - -#include "imx6qdl-wandboard.dtsi" - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi deleted file mode 100644 index 3874e74703f0..000000000000 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. -// -// Author: Fabio Estevam - -#include "imx6qdl-wandboard.dtsi" - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi deleted file mode 100644 index 9b8c9c23ab54..000000000000 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. -// -// Author: Fabio Estevam - -#include "imx6qdl-wandboard.dtsi" - -/ { - reg_eth_phy: regulator-eth-phy { - compatible = "regulator-fixed"; - regulator-name = "ETH_PHY"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&fec { - phy-supply = <®_eth_phy>; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi deleted file mode 100644 index e4f63423d8ee..000000000000 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - sound { - compatible = "fsl,imx6-wandboard-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-wandboard-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; - - reg_1p5v: regulator-1p5v { - compatible = "regulator-fixed"; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p8v: regulator-2p8v { - compatible = "regulator-fixed"; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c1>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - codec: sgtl5000@a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mclk>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - lrclk-strength = <3>; - }; - - camera@3c { - compatible = "ovti,ov5645"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5645>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-frequency = <24000000>; - vdddo-supply = <®_1p8v>; - vdda-supply = <®_2p8v>; - vddd-supply = <®_1p5v>; - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - - port { - ov5645_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6qdl-wandboard { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0 - >; - }; - - pinctrl_mclk: mclkgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_ov5645: ov5645grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - qca,clk-out-frequency = <125000000>; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5645_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi deleted file mode 100644 index 9ff183e4e069..000000000000 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ /dev/null @@ -1,1142 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2016-2017 Zodiac Inflight Innovations - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - aliases { - mdio-gpio0 = &mdio1; - rtc0 = &ds1341; - }; - - mdio1: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio1>; - gpios = <&gpio6 5 GPIO_ACTIVE_HIGH - &gpio6 4 GPIO_ACTIVE_HIGH>; - - phy: ethernet-phy@0 { - pinctrl-0 = <&pinctrl_rmii_phy_irq>; - pinctrl-names = "default"; - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - reg_28p0v: regulator-28p0v { - compatible = "regulator-fixed"; - regulator-name = "28V_IN"; - regulator-min-microvolt = <28000000>; - regulator-max-microvolt = <28000000>; - regulator-always-on; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - vin-supply = <®_28p0v>; - regulator-name = "12V_MAIN"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_5p0v_main: regulator-5p0v-main { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3v_pmic: regulator-3p3v-pmic { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "PMIC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - vin-supply = <®_3p3v_pmic>; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3p3v_sd: regulator-3p3v-sd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_3p3v_sd>; - vin-supply = <®_3p3v>; - regulator-name = "3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - startup-delay-us = <1000>; - enable-active-high; - regulator-always-on; - }; - - reg_3p3v_display: regulator-3p3v-display { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "3V3_DISPLAY"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3p3v_ssd: regulator-3p3v-ssd { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "3V3_SSD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "front"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound1_codec>; - simple-audio-card,frame-master = <&sound1_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPA1 HPLEFT", - "Headphone Jack", "HPA1 HPRIGHT", - "HPA1 LEFTIN", "HPL", - "HPA1 RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa1>; - - sound1_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound1_codec: simple-audio-card,codec { - sound-dai = <&codec1>; - clocks = <&cs2000>; - }; - }; - - sound2 { - compatible = "simple-audio-card"; - simple-audio-card,name = "periph"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound2_codec>; - simple-audio-card,frame-master = <&sound2_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPA1 HPLEFT", - "Headphone Jack", "HPA1 HPRIGHT", - "HPA1 LEFTIN", "HPL", - "HPA1 RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa2>; - - sound2_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound2_codec: simple-audio-card,codec { - sound-dai = <&codec2>; - clocks = <&cs2000>; - }; - }; - - panel { - power-supply = <®_3p3v_display>; - backlight = <&sp_backlight>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - disp0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0>; - status = "disabled"; - - port@0 { - reg = <0>; - - disp0_in_0: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - disp0_out: endpoint { - remote-endpoint = <&tc358767_in>; - }; - }; - }; - - cs2000_ref: cs2000-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - cs2000_in_dummy: cs2000-in-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - edp_refclk: edp-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&cpu0 { - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1300000 - 996000 1275000 - 852000 1275000 - 792000 1200000 - 396000 1200000 - >; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -&ldb { - lvds-channel@0 { - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - sp_backlight: backlight { - compatible = "zii,rave-sp-backlight"; - }; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "dds-eeprom"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "st,m25p128", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&gpio3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio3_hog>; - - usb-emulation-hog { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "usb-emulation"; - }; - - usb-mode1-hog { - gpio-hog; - gpios = <20 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode1"; - }; - - usb-pwr-hog { - gpio-hog; - gpios = <22 GPIO_ACTIVE_LOW>; - output-high; - line-name = "usb-pwr-ctrl-en-n"; - }; - - usb-mode2-hog { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode2"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - codec2: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec2>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - accel@1c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "fsl,mma8451"; - reg = <0x1c>; - interrupt-parent = <&gpio1>; - interrupt-names = "INT2"; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <®_3p3v>; - vddio-supply = <®_3p3v>; - }; - - hpa2: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa2>; - reg = <0x60>; - power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - sound-name-prefix = "HPA1"; - }; - - edp-bridge@68 { - compatible = "toshiba,tc358767"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tc358767>; - reg = <0x68>; - shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - clock-names = "ref"; - clocks = <&edp_refclk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - tc358767_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pfuze100_irq>; - reg = <0x08>; - interrupt-parent = <&gpio7>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; - - temp-sense@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - cs2000: clkgen@4e { - compatible = "cirrus,cs2000-cp"; - reg = <0x4e>; - #clock-cells = <0>; - clock-names = "clk_in", "ref_clk"; - clocks = <&cs2000_in_dummy>, <&cs2000_ref>; - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24000000>; - }; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - ds1341: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - codec1: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec1>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <®_5p0v_main>; - vio-supply = <®_3p3v>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <2>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - syna,delta-x-threshold = <5>; - syna,delta-y-threshold = <10>; - }; - - rmi4-f12@12 { - reg = <0x12>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - }; - - touchscreen@2a { - compatible = "eeti,exc3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x2a>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "disabled"; - }; - - reg_5p0v_user_usb: charger@32 { - compatible = "microchip,ucs1002"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ucs1002_pins>; - reg = <0x32>; - interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>, - <&gpio3 21 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "a_det", "alert"; - }; - - hpa1: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa1>; - reg = <0x60>; - power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - sound-name-prefix = "HPA1"; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&disp0_in_0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - host@0 { - reg = <0 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - i210: i210@0 { - reg = <0 0 0 0 0>; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_3p3v_sd>; - vqmmc-supply = <®_3p3v>; - no-1-8-v; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_3p3v_sd>; - vqmmc-supply = <®_3p3v>; - no-1-8-v; - no-sdio; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&sata { - target-supply = <®_3p3v_ssd>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&phy>; - phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - phy-supply = <®_3p3v>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_switch_irq>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "gigabit_proc"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "netaux"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - phy-mode = "rev-rmii"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@3 { - reg = <3>; - label = "netright"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "netleft"; - phy-handle = <&switchphy4>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy4: switchphy@4 { - reg = <4>; - interrupt-parent = <&switch>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; - -&usbh1 { - vbus-supply = <®_5p0v_main>; - disable-over-current; - maximum-speed = "full-speed"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v_user_usb>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCSEL(2) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; - - mux-ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - mux-aud5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&iomuxc { - pinctrl_accel: accelgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_codec1: dac1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038 - >; - }; - - pinctrl_codec2: dac2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038 - >; - }; - - pinctrl_disp0: disp0grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - >; - }; - - pinctrl_gpio3_hog: gpio3hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b811 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b811 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b811 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b811 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b811 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b811 - >; - }; - - pinctrl_mdio1: bitbangmdiogrp { - fsl,pins = < - /* Bitbang MDIO for DEB Switch */ - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038 - >; - }; - - pinctrl_pfuze100_irq: pfuze100grp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000 - >; - }; - - pinctrl_reg_3p3v_sd: mmcsupply1grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858 - >; - }; - - pinctrl_rmii_phy_irq: phygrp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000 - >; - }; - - pinctrl_switch_irq: switchgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000 - >; - }; - - pinctrl_tc358767: tc358767grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10 - >; - }; - - pinctrl_tpa1: tpa6130-1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038 - >; - }; - - pinctrl_tpa2: tpa6130-2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_ucs1002_pins: ucs1002grp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040 - - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi deleted file mode 100644 index bda182edc589..000000000000 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ /dev/null @@ -1,1393 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - can0 = &can1; - can1 = &can2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - ipu0 = &ipu1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usb0 = &usbotg; - usb1 = &usbh1; - usb2 = &usbh2; - usb3 = &usbh3; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - ldb: ldb { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; - gpr = <&gpr>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - dma_apbh: dma-controller@110000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x00110000 0x2000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6QDL_CLK_APBH_DMA>; - }; - - gpmi: nand-controller@112000 { - compatible = "fsl,imx6q-gpmi-nand"; - reg = <0x00112000 0x2000>, <0x00114000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bch"; - clocks = <&clks IMX6QDL_CLK_GPMI_IO>, - <&clks IMX6QDL_CLK_GPMI_APB>, - <&clks IMX6QDL_CLK_GPMI_BCH>, - <&clks IMX6QDL_CLK_GPMI_BCH_APB>, - <&clks IMX6QDL_CLK_PER1_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - hdmi: hdmi@120000 { - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; - }; - - gpu_3d: gpu@130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&pd_pu>; - #cooling-cells = <2>; - }; - - gpu_2d: gpu@134000 { - compatible = "vivante,gc"; - reg = <0x00134000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - #cooling-cells = <2>; - }; - - timer@a00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x00a00600 0x20>; - interrupts = <1 13 0xf01>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6QDL_CLK_TWD>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: cache-controller@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - arm,shared-override; - }; - - pcie: pcie@1ffc000 { - compatible = "fsl,imx6q-pcie"; - reg = <0x01ffc000 0x04000>, - <0x01f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */ - <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, - <&clks IMX6QDL_CLK_LVDS1_GATE>, - <&clks IMX6QDL_CLK_PCIE_REF_125M>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - status = "disabled"; - }; - - aips1: bus@2000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI1>, - <&clks IMX6QDL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI2>, - <&clks IMX6QDL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI3>, - <&clks IMX6QDL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI4>, - <&clks IMX6QDL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai: esai@2024000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx35-esai"; - reg = <0x02024000 0x4000>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_ESAI_MEM>, - <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "mem", "extal", "fsys", "spba"; - dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, - <&clks IMX6QDL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, - <&clks IMX6QDL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, - <&clks IMX6QDL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - asrc: asrc@2034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, - <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, - <&clks IMX6QDL_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck_0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "spba"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; - status = "okay"; - }; - - spba-bus@203c000 { - reg = <0x0203c000 0x4000>; - }; - }; - - vpu: vpu@2040000 { - compatible = "cnm,coda960"; - reg = <0x02040000 0x3c000>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bit", "jpeg"; - clocks = <&clks IMX6QDL_CLK_VPU_AXI>, - <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; - clock-names = "per", "ahb"; - power-domains = <&pd_pu>; - resets = <&src 1>; - iram = <&ocram>; - }; - - aipstz@207c000 { /* AIPSTZ1 */ - reg = <0x0207c000 0x4000>; - }; - - pwm1: pwm@2080000 { - #pwm-cells = <3>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm2: pwm@2084000 { - #pwm-cells = <3>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm3: pwm@2088000 { - #pwm-cells = <3>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm4: pwm@208c000 { - #pwm-cells = <3>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: can@2090000 { - compatible = "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, - <&clks IMX6QDL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 28>; - status = "disabled"; - }; - - can2: can@2094000 { - compatible = "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, - <&clks IMX6QDL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 29>; - status = "disabled"; - }; - - gpt: timer@2098000 { - compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPT_IPG>, - <&clks IMX6QDL_CLK_GPT_IPG_PER>, - <&clks IMX6QDL_CLK_GPT_3M>; - clock-names = "ipg", "per", "osc_per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@20b0000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, - <0 77 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@20b4000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020b4000 0x4000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 79 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6q-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-enable-ramp-delay = <380>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - #thermal-sensor-cells = <0>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6q-snvs-lpgpr"; - }; - }; - - epit1: epit@20d0000 { /* EPIT1 */ - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@20d4000 { /* EPIT2 */ - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6q-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6QDL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - }; - }; - }; - - gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; - reg = <0x20e0000 0x38>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - }; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; - reg = <0x20e0000 0x4000>; - }; - - dcic1: dcic@20e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; - }; - - dcic2: dcic@20e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: dma-controller@20ec000 { - compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; - - aips2: bus@2100000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: crypto@2100000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, - <&clks IMX6QDL_CLK_CAAM_ACLK>, - <&clks IMX6QDL_CLK_CAAM_IPG>, - <&clks IMX6QDL_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - aipstz@217c000 { /* AIPSTZ2 */ - reg = <0x0217c000 0x4000>; - }; - - usbotg: usb@2184000 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh1: usb@2184200 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh2: usb@2184400 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh3: usb@2184600 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184600 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop2>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - }; - - fec: ethernet@2188000 { - compatible = "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, - <0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF_SEL>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - fsl,stop-mode = <&gpr 0x34 27>; - nvmem-cells = <&fec_mac_addr>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - mlb@218c000 { - reg = <0x0218c000 0x4000>; - interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 117 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC1>, - <&clks IMX6QDL_CLK_USDHC1>, - <&clks IMX6QDL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC2>, - <&clks IMX6QDL_CLK_USDHC2>, - <&clks IMX6QDL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@2198000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC3>, - <&clks IMX6QDL_CLK_USDHC3>, - <&clks IMX6QDL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: mmc@219c000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC4>, - <&clks IMX6QDL_CLK_USDHC4>, - <&clks IMX6QDL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C3>; - status = "disabled"; - }; - - romcp@21ac000 { - reg = <0x021ac000 0x4000>; - }; - - mmdc0: memory-controller@21b0000 { /* MMDC0 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; - }; - - mmdc1: memory-controller@21b4000 { /* MMDC1 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b4000 0x4000>; - status = "disabled"; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: efuse@21bc000 { - compatible = "fsl,imx6q-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6QDL_CLK_IIM>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - - fec_mac_addr: mac-addr@88 { - reg = <0x88 6>; - }; - }; - - tzasc@21d0000 { /* TZASC1 */ - reg = <0x021d0000 0x4000>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - }; - - tzasc@21d4000 { /* TZASC2 */ - reg = <0x021d4000 0x4000>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - mipi_csi: mipi@21dc000 { - compatible = "fsl,imx6-mipi-csi2"; - reg = <0x021dc000 0x4000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 100 0x04>, <0 101 0x04>; - clocks = <&clks IMX6QDL_CLK_HSI_TX>, - <&clks IMX6QDL_CLK_VIDEO_27M>, - <&clks IMX6QDL_CLK_EIM_PODF>; - clock-names = "dphy", "ref", "pix"; - status = "disabled"; - }; - - mipi_dsi: mipi@21e0000 { - reg = <0x021e0000 0x4000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mipi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_mipi>; - }; - }; - - port@1 { - reg = <1>; - - mipi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_mipi>; - }; - }; - }; - }; - - vdoa@21e4000 { - compatible = "fsl,imx6q-vdoa"; - reg = <0x021e4000 0x4000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_VDOA>; - }; - - uart2: serial@21e8000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@21ec000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@21f0000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - ipu1: ipu@2400000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02400000 0x400000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, - <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu1_csi0: port@0 { - reg = <0>; - - ipu1_csi0_from_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; - }; - }; - - ipu1_csi1: port@1 { - reg = <1>; - }; - - ipu1_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu1_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu1_di0_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_0>; - }; - - ipu1_di0_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_0>; - }; - - ipu1_di0_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_0>; - }; - - ipu1_di0_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_0>; - }; - }; - - ipu1_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu1_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu1_di1_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_1>; - }; - - ipu1_di1_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_1>; - }; - - ipu1_di1_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_1>; - }; - - ipu1_di1_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_1>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6qp-mba6b.dts b/arch/arm/boot/dts/imx6qp-mba6b.dts deleted file mode 100644 index eee2e09d6e94..000000000000 --- a/arch/arm/boot/dts/imx6qp-mba6b.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2015-2021 TQ-Systems GmbH - * Author: Markus Niebel - */ -/dts-v1/; - -#include -#include "imx6qp-tqma6b.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6b.dtsi" -#include "imx6q-mba6.dtsi" - -/ { - model = "TQ TQMa6QP on MBa6x"; - compatible = "tq,imx6qp-mba6x-b", "tq,mba6b", - "tq,imx6qp-tqma6qp-b", "fsl,imx6qp"; -}; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts deleted file mode 100644 index 741d1ed338ca..000000000000 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-nitrogen6_max.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; - compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; -}; - -&pcie { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts deleted file mode 100644 index 1593ac86b2a4..000000000000 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2017 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-nitrogen6_som2.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_SOM2 Board"; - compatible = "boundary,imx6qp-nitrogen6_som2", "fsl,imx6qp"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts deleted file mode 100644 index a18266598d39..000000000000 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Enrico Scholz - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" -#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" -#include "imx6qdl-phytec-mira-peb-av-02.dtsi" -#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; - compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6qp"; - - chosen { - stdout-path = &uart2; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&m25p80 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/imx6qp-prtwd3.dts deleted file mode 100644 index ae00d538a4df..000000000000 --- a/arch/arm/boot/dts/imx6qp-prtwd3.dts +++ /dev/null @@ -1,557 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2018 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include -#include "imx6qp.dtsi" - -/ { - model = "Protonic WD3 board"; - compatible = "prt,prtwd3", "fsl,imx6qp"; - - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - clock_ksz8081: clock-ksz8081 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - clock_ksz9031: clock-ksz9031 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - clock_mcp251xfd: clock-mcp251xfd { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - }; - - clock_sja1105: clock-sja1105 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio>; - - #address-cells = <1>; - #size-cells = <0>; - gpios = <&gpio5 6 GPIO_ACTIVE_HIGH - &gpio5 7 GPIO_ACTIVE_HIGH>; - - /* Microchip KSZ8081 */ - usbeth_phy: ethernet-phy@3 { - reg = <0x3>; - - interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - reset-assert-us = <500>; - reset-deassert-us = <1000>; - clocks = <&clock_ksz8081>; - clock-names = "rmii-ref"; - micrel,led-mode = <0>; - }; - - tja1102_phy0: ethernet-phy@4 { - reg = <0x4>; - - interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <20>; - reset-deassert-us = <2000>; - #address-cells = <1>; - #size-cells = <0>; - - tja1102_phy1: ethernet-phy@5 { - reg = <0x5>; - - interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_5v0>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - switch@0 { - compatible = "nxp,sja1105q"; - reg = <0>; - spi-max-frequency = <4000000>; - spi-rx-delay-us = <1>; - spi-tx-delay-us = <1>; - spi-cpha; - - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - - clocks = <&clock_sja1105>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "usb"; - phy-handle = <&usbeth_phy>; - phy-mode = "rmii"; - }; - - port@1 { - reg = <1>; - label = "t1slave"; - phy-handle = <&tja1102_phy1>; - phy-mode = "rmii"; - }; - - port@2 { - reg = <2>; - label = "t1master"; - phy-handle = <&tja1102_phy0>; - phy-mode = "rmii"; - - }; - - port@3 { - reg = <3>; - label = "rj45"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-id"; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&fec>; - phy-mode = "rgmii-id"; - rx-internal-delay-ps = <2000>; - tx-internal-delay-ps = <2000>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp251xfd"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - reg = <0>; - clocks = <&clock_mcp251xfd>; - spi-max-frequency = <10000000>; - interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>; - assigned-clock-rates = <125000000>; - status = "okay"; - - phy-mode = "rgmii"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031 */ - rgmii_phy: ethernet-phy@2 { - reg = <2>; - - interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <1000>; - - clocks = <&clock_ksz9031>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "SD1_CD", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", - "", "", "", "", "", "", "", "", - "", "", "ECSPI2_SS0", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", - "", "", "", "", "", "", "", "", - "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "SW_RESET", "", "", - "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", - "PHY0_INT", "", "", "", - "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", - "", "", - "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", - "DISP0_EN", "CAM_GPIO0"; -}; - -&gpio6 { - gpio-line-names = - "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", - "CAM_LOCK", "", "POWER_TG", - "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", - "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", - "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* VIN */ - channel@4 { - reg = <4>; - ti,gain = <1>; - ti,datarate = <3>; - }; - - /* VBUS */ - channel@5 { - reg = <5>; - ti,gain = <1>; - ti,datarate = <3>; - }; - - /* ICHG */ - channel@6 { - reg = <6>; - ti,gain = <1>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <1>; - ti,datarate = <3>; - }; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usbphynop1 { - status = "disabled"; -}; - -&usbphynop2 { - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&usdhc2_wifi_pwrseq>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - /* CAN2_nINT */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - - /* Configure clock provider for RGMII ref clock */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 - /* Configure clock consumer for RGMII ref clock */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - - /* SJA1105Q switch reset */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 - - /* phy3/rgmii_phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 - /* phy3/rgmii_phy int */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_mdio: mdiogrp { - fsl,pins = < - /* phy0/usbeth_phy reset */ - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 - /* phy0/usbeth_phy int */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - - /* phy12/tja1102_phy0 reset */ - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 - /* phy12/tja1102_phy0 int */ - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 - /* phy12/tja1102_phy0 enable. Set 100K pull-up */ - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; - - pinctrl_wifi_npd: wifinpd { - fsl,pins = < - /* WL_REG_ON */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts deleted file mode 100644 index 2bb3bfb18ec3..000000000000 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2016 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; -}; - -&i2c2 { - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; -}; - -&pcie { - reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&vgen3_reg { - regulator-always-on; -}; diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts deleted file mode 100644 index f69eec18d865..000000000000 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2016 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; -}; - -®_arm { - vin-supply = <&sw2_reg>; -}; - -&iomuxc { - imx6qdl-sabresd { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - }; -}; - -&vgen3_reg { - regulator-always-on; -}; - -&pcie { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi deleted file mode 100644 index bb6ff7c64b27..000000000000 --- a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - */ - -#include "imx6q.dtsi" -#include "imx6qp.dtsi" -#include "imx6qdl-tqma6b.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts deleted file mode 100644 index 92b38e6699aa..000000000000 --- a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp-tx6qp-8037.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard"; -}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts deleted file mode 100644 index ffc0f2ee11d2..000000000000 --- a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6QP-8037 Module"; - compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts deleted file mode 100644 index 07ad70718aec..000000000000 --- a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp-tx6qp-8137.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard"; - compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; -}; - -&ipu2 { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts deleted file mode 100644 index dd494d587014..000000000000 --- a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lvds.dtsi" - -/ { - model = "Ka-Ro electronics TX6QP-8137 Module"; - compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts deleted file mode 100644 index 49ff145fffe5..000000000000 --- a/arch/arm/boot/dts/imx6qp-vicutp.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2014 Protonic Holland - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-vicut1.dtsi" -#include "imx6qdl-vicut1-12inch.dtsi" - -/ { - model = "Kverneland UT1P Board"; - compatible = "kvg,vicutp", "fsl,imx6qp"; -}; diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts deleted file mode 100644 index 08d8b78a2096..000000000000 --- a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-wandboard-revd1.dtsi" - -/ { - model = "Wandboard i.MX6 QuadPlus Board revD1"; - compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts deleted file mode 100644 index afaf4a6759d4..000000000000 --- a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Crux+ i.MX6QuadPlus board"; - compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xf0000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled_1305 { - status = "okay"; -}; - -&oled_1309 { - status = "okay"; -}; - -®_pu { - regulator-always-on; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&uart2 { - status = "disabled"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts deleted file mode 100644 index 4a961a33bf2d..000000000000 --- a/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2021 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6dl-yapp43-common.dtsi" - -/ { - model = "Y Soft IOTA Pegasus+ i.MX6QuadPlus board"; - compatible = "ysoft,imx6qp-yapp4-pegasus-plus", "fsl,imx6qp"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xf0000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled_1305 { - status = "okay"; -}; - -&oled_1309 { - status = "okay"; -}; - -®_pu { - regulator-always-on; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts deleted file mode 100644 index 57de447c4609..000000000000 --- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2016-2017 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-zii-rdu2.dtsi" - -/ { - model = "ZII RDU2+ Board"; - compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; - -&gpu_3d { - assigned-clocks = <&clks IMX6QDL_CLK_GPU3D_SHADER_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>; -}; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi deleted file mode 100644 index fc164991d2ae..000000000000 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2016 Freescale Semiconductor, Inc. - -#include "imx6q.dtsi" - -/ { - soc { - ocram2: sram@940000 { - compatible = "mmio-sram"; - reg = <0x00940000 0x20000>; - ranges = <0 0x00940000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - ocram3: sram@960000 { - compatible = "mmio-sram"; - reg = <0x00960000 0x20000>; - ranges = <0 0x00960000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - bus@2100000 { - pre1: pre@21c8000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c8000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE0>; - clock-names = "axi"; - fsl,iram = <&ocram2>; - }; - - pre2: pre@21c9000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE1>; - clock-names = "axi"; - fsl,iram = <&ocram2>; - }; - - pre3: pre@21ca000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE2>; - clock-names = "axi"; - fsl,iram = <&ocram3>; - }; - - pre4: pre@21cb000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021cb000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE3>; - clock-names = "axi"; - fsl,iram = <&ocram3>; - }; - - prg1: prg@21cc000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cc000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, - <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; - }; - - prg2: prg@21cd000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cd000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG1_APB>, - <&clks IMX6QDL_CLK_PRG1_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre4>, <&pre2>, <&pre3>; - }; - }; - }; -}; - -&fec { - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, - <0 119 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpc { - compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; -}; - -&ipu1 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - fsl,prg = <&prg1>; -}; - -&ipu2 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - fsl,prg = <&prg2>; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; -}; - -&mmdc0 { - compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; -}; - -&pcie { - compatible = "fsl,imx6qp-pcie"; -}; diff --git a/arch/arm/boot/dts/imx6s-dhcom-drc02.dts b/arch/arm/boot/dts/imx6s-dhcom-drc02.dts deleted file mode 100644 index 4077b607c29e..000000000000 --- a/arch/arm/boot/dts/imx6s-dhcom-drc02.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2021 DH electronics GmbH - * - * DHCOM iMX6 variant: - * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 - * DHCOM PCB number: 493-400 or newer - * DRC02 PCB number: 568-100 or newer - */ -/dts-v1/; - -/* - * The kernel only distinguishes between i.MX6 Quad and DualLite, - * but the Solo is actually a DualLite with only one CPU. So use - * DualLite for the Solo and disable one CPU node. - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-dhcom-som.dtsi" -#include "imx6qdl-dhcom-drc02.dtsi" - -/ { - model = "DH electronics i.MX6S DHCOM on DRC02"; - compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som", - "fsl,imx6dl"; - - cpus { - /delete-node/ cpu@1; - }; -}; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts deleted file mode 100644 index 239bc6dfc584..000000000000 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ /dev/null @@ -1,658 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -//Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" - -/ { - model = "Freescale i.MX6 SoloLite EVK Board"; - compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight_display: backlight_display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-user { - label = "debug"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_aud3v: regulator-aud3v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; - - reg_aud4v: regulator-aud4v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound { - compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux3>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; - DCVDD-supply = <&vgen3_reg>; - DBVDD-supply = <®_aud3v>; - AVDD-supply = <&vgen3_reg>; - CPVDD-supply = <&vgen3_reg>; - MICVDD-supply = <®_aud3v>; - PLLVDD-supply = <&vgen3_reg>; - SPKVDD1-supply = <®_aud4v>; - SPKVDD2-supply = <®_aud4v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6sl-evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 - MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 - MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 - MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 - >; - }; - - pinctrl_audmux3: audmux3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 - MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 - MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 - MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 - MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 - MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 - MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 - MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 - MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 - >; - }; - - pinctrl_fec_sleep: fecgrp-sleep { - fsl,pins = < - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 - MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 - MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 - MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 - >; - }; - - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 - MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 - MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 - MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 - MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 - MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 - MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 - MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 - MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 - MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 - MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 - MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 - MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 - MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 - MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 - MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 - MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 - MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 - MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 - MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 - MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 - MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 - MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 - MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 - MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 - MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 - MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 - MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 - MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 - MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 - MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 - MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 - MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 - >; - }; - - pinctrl_pwm1: pwmgrp { - fsl,pins = < - MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_reg_lcd_3v3: reglcd3v3grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ - MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ - MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ - MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ - MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ - MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ - MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ - MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -®_vdd1p1 { - vin-supply = <&sw2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&sw2_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sl-kobo-aura2.dts b/arch/arm/boot/dts/imx6sl-kobo-aura2.dts deleted file mode 100644 index 657d0f1b6115..000000000000 --- a/arch/arm/boot/dts/imx6sl-kobo-aura2.dts +++ /dev/null @@ -1,555 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for the Kobo Aura 2 ebook reader - * - * Name on mainboard is: 37NB-E60QL0+4B1 - * Serials start with: E60QL2 - * - * Copyright 2022 Andreas Kemnade - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6sl.dtsi" - -/ { - model = "Kobo Aura 2"; - compatible = "kobo,aura2", "fsl,imx6sl"; - - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc3; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-cover { - label = "Cover"; - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - - key-power { - label = "Power"; - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-0 { - label = "koboaura2:white:on"; - gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; - color = ; - linux,default-trigger = "timer"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; - regulator-name = "SD3_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - post-power-on-delay-ms = <20>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; - status = "okay"; - - lm3630a: backlight@36 { - compatible = "ti,lm3630a"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; - reg = <0x36>; - enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0>; - label = "backlight"; - default-brightness = <0>; - max-brightness = <255>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; - clock-frequency = <100000>; - status = "okay"; - - /* eKTF2232 at 0x15 */ - /* FP9928 at 0x48 */ -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - ricoh619: pmic@32 { - compatible = "ricoh,rc5t619"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; - reg = <0x32>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - system-power-controller; - - regulators { - dcdc1_reg: DCDC1 { - regulator-name = "DCDC1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <900000>; - regulator-suspend-min-microvolt = <900000>; - }; - }; - - /* Core3_3V3 */ - dcdc2_reg: DCDC2 { - regulator-name = "DCDC2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3100000>; - regulator-suspend-min-microvolt = <3100000>; - }; - }; - - dcdc3_reg: DCDC3 { - regulator-name = "DCDC3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V2 */ - dcdc4_reg: DCDC4 { - regulator-name = "DCDC4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V8 */ - dcdc5_reg: DCDC5 { - regulator-name = "DCDC5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1700000>; - regulator-suspend-min-microvolt = <1700000>; - }; - }; - - /* IR_3V3 */ - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-always-on; - regulator-boot-on; - }; - - /* Core1_3V3 */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3000000>; - regulator-suspend-min-microvolt = <3000000>; - }; - }; - - /* Core5_1V2 */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-boot-on; - }; - - /* SPD_3V3 */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-always-on; - regulator-boot-on; - }; - - /* DDR_0V6 */ - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-always-on; - regulator-boot-on; - }; - - /* VDD_PWM */ - ldo7_reg: LDO7 { - regulator-name = "LDO7"; - regulator-always-on; - regulator-boot-on; - }; - - /* ldo_1v8 */ - ldo8_reg: LDO8 { - regulator-name = "LDO8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "LDO9"; - regulator-boot-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "LDO10"; - regulator-boot-on; - }; - - ldortc1_reg: LDORTC1 { - regulator-name = "LDORTC1"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -®_vdd1p1 { - vin-supply = <&dcdc2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&dcdc2_reg>; -}; - -®_arm { - vin-supply = <&dcdc3_reg>; -}; - -®_soc { - vin-supply = <&dcdc1_reg>; -}; - -®_pu { - vin-supply = <&dcdc1_reg>; -}; - -&snvs_rtc { - /* - * We are using the RTC in the PMIC, but this one is not disabled - * in imx6sl.dtsi. - */ - status = "disabled"; -}; - -&uart1 { - /* J4, through-holes */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - /* TP198, next to J4, SMD pads */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; - non-removable; - status = "okay"; - - /* internal uSD card */ -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; - vmmc-supply = <®_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - cap-power-off-card; - non-removable; - status = "okay"; - - /* - * RTL8189F SDIO WiFi - */ -}; - -&usbotg1 { - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 - MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1-sleepgrp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2-sleepgrp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh-gpiogrp { - fsl,pins = < - MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ - MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ - MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 - MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2-sleepgrp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 - MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 - MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 - MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3-sleepgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 - MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 - MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 - MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6sl-pinfunc.h b/arch/arm/boot/dts/imx6sl-pinfunc.h deleted file mode 100644 index bcf16060ecdc..000000000000 --- a/arch/arm/boot/dts/imx6sl-pinfunc.h +++ /dev/null @@ -1,1073 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6SL_PINFUNC_H -#define __DTS_IMX6SL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 -#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 -#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 -#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 -#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 -#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 -#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 -#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 -#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 -#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 -#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 -#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 -#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 -#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 -#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 -#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 -#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 -#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 -#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 -#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 -#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 -#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 -#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 -#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 -#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 -#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 -#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 -#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 -#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 -#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 -#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 -#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 -#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 -#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 -#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 -#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 -#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 -#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 -#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 -#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 -#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 -#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 -#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 -#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 -#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 -#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 -#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 -#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 -#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 -#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 -#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 -#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 -#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 -#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 -#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 -#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 -#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 -#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 -#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 -#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 -#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 -#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 -#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 -#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 -#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 -#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 -#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 -#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 -#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 -#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 -#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 -#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 -#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 -#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 -#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 -#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 -#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 -#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 -#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 -#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 -#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 -#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 -#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 -#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 -#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 -#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 -#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 -#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 -#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 -#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 -#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 -#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 -#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 -#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 -#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 -#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 -#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 -#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 -#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 -#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 -#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 -#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 -#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 -#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 -#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 -#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 -#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 -#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 -#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 -#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 -#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 -#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 -#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 -#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 -#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 -#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 -#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 -#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 -#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 -#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 -#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 -#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 -#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 -#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 -#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 -#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 -#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 -#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 -#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 -#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 -#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 -#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 -#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 -#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 -#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 -#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 -#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 -#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 -#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 -#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 -#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 -#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 -#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 -#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 -#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 -#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 -#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 -#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 -#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 -#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 -#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 -#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 -#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 -#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 -#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 -#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 -#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 -#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 -#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 -#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 -#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 -#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 -#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 -#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 -#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 -#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 -#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 -#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 -#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 -#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 -#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 -#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 -#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 -#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 -#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 -#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 -#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 -#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 -#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 -#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 -#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 -#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 -#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 -#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 -#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 -#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 -#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 -#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 -#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 -#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 -#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 -#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 -#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 -#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 -#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 -#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 -#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 -#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 -#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 -#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 -#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 -#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 -#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 -#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 -#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 -#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 -#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 -#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 -#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 -#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 -#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 -#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 -#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 -#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 -#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 -#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 -#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 -#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 -#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 -#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 -#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 -#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 -#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 -#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 -#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 -#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 -#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 -#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 -#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 -#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 -#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 -#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 -#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 -#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 -#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 -#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 -#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 -#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 -#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 -#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 -#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 -#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 -#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 -#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 -#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 -#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 -#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 -#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 -#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 -#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 -#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 -#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 -#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 -#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 -#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 -#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 -#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 -#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 -#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 -#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 -#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 -#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 -#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 -#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 -#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 -#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 -#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 -#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 -#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 -#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 -#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 -#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 -#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 -#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 -#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 -#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 -#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 -#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 -#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 -#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 -#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 -#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 -#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 -#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 -#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 -#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 -#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 -#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 -#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 -#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 -#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 -#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 -#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 -#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 -#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 -#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 -#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 -#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 -#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 -#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 -#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 -#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 -#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 -#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 -#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 -#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 -#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 -#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 -#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 -#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 -#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 -#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 -#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 -#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 -#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 -#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 -#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 -#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 -#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 -#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 -#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 -#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 -#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 -#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 -#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 -#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 -#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 -#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 -#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 -#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 -#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 -#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 -#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 -#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 -#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 -#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 -#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 -#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 - -#endif /* __DTS_IMX6SL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts deleted file mode 100644 index 815119c12bd4..000000000000 --- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for the Tolino Shine 2 HD ebook reader - * - * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3 - * Serials start with: E60QF2 - * - * Copyright 2020 Andreas Kemnade - */ - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" - -/ { - model = "Tolino Shine 2 HD"; - compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ec 0 50000>; - power-supply = <&backlight_regulator>; - }; - - backlight_regulator: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_power>; - regulator-name = "backlight"; - gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-cover { - label = "Cover"; - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - - key-fl { - label = "Frontlight"; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-home { - label = "Home"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-power { - label = "Power"; - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-0 { - label = "tolinoshine2hd:white:on"; - gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - led-1 { - label = "tolinoshine2hd:white:backlightboost"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "off"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; - regulator-name = "SD3_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - post-power-on-delay-ms = <20>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; - status = "okay"; - - ec: embedded-controller@43 { - compatible = "netronix,ntxec"; - reg = <0x43>; - #pwm-cells = <2>; - }; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; - clock-frequency = <100000>; - status = "okay"; - - zforce: touchscreen@50 { - compatible = "neonode,zforce"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_zforce>; - reg = <0x50>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&ldo1_reg>; - reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - x-size = <1072>; - y-size = <1448>; - }; - - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ - -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - ricoh619: pmic@32 { - compatible = "ricoh,rc5t619"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; - reg = <0x32>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - system-power-controller; - - regulators { - dcdc1_reg: DCDC1 { - regulator-name = "DCDC1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <900000>; - regulator-suspend-min-microvolt = <900000>; - }; - }; - - /* Core3_3V3 */ - dcdc2_reg: DCDC2 { - regulator-name = "DCDC2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3100000>; - regulator-suspend-min-microvolt = <3100000>; - }; - }; - - dcdc3_reg: DCDC3 { - regulator-name = "DCDC3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V2 */ - dcdc4_reg: DCDC4 { - regulator-name = "DCDC4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V8 */ - dcdc5_reg: DCDC5 { - regulator-name = "DCDC5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1700000>; - regulator-suspend-min-microvolt = <1700000>; - }; - }; - - /* IR_3V3 */ - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-boot-on; - }; - - /* Core1_3V3 */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3000000>; - regulator-suspend-min-microvolt = <3000000>; - }; - }; - - /* Core5_1V2 */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-boot-on; - }; - - /* SPD_3V3 */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-always-on; - regulator-boot-on; - }; - - /* DDR_0V6 */ - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-always-on; - regulator-boot-on; - }; - - /* VDD_PWM */ - ldo7_reg: LDO7 { - regulator-name = "LDO7"; - regulator-always-on; - regulator-boot-on; - }; - - /* ldo_1v8 */ - ldo8_reg: LDO8 { - regulator-name = "LDO8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "LDO9"; - regulator-boot-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "LDO10"; - regulator-boot-on; - }; - - ldortc1_reg: LDORTC1 { - regulator-name = "LDORTC1"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_backlight_power: backlight-powergrp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 - MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 - MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059 - MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 - MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 - MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 - MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 - MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 - MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 - MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 - MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 - MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 - MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 - MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 - MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 - MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 - MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 - MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 - MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 - MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 - MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 - MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 - MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 - MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 - MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 - MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 - MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 - MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 - MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059 - >; - }; - - pinctrl_ricoh_gpio: ricoh_gpiogrp { - fsl,pins = < - MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ - MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ - MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 - MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2grp-sleep { - fsl,pins = < - MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 - MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 - MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 - MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grp-sleep { - fsl,pins = < - MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 - MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 - MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 - MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; - - pinctrl_zforce: zforcegrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ - MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */ - >; - }; -}; - -®_vdd1p1 { - vin-supply = <&dcdc2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&dcdc2_reg>; -}; - -®_arm { - vin-supply = <&dcdc3_reg>; -}; - -®_soc { - vin-supply = <&dcdc1_reg>; -}; - -®_pu { - vin-supply = <&dcdc1_reg>; -}; - -&snvs_rtc { - /* - * We are using the RTC in the PMIC, but this one is not disabled - * in imx6sl.dtsi. - */ - status = "disabled"; -}; - -&uart1 { - /* J4, through-holes */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - /* TP198, next to J4, SMD pads */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; - non-removable; - status = "okay"; - - /* internal uSD card */ -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; - vmmc-supply = <®_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - cap-power-off-card; - non-removable; - status = "okay"; - - /* - * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi - * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi - */ -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts deleted file mode 100644 index db5d8509935f..000000000000 --- a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts +++ /dev/null @@ -1,340 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * Device tree for the Tolino Shine 3 ebook reader - * - * Name on mainboard is: 37NB-E60K00+4A4 - * Serials start with: E60K02 (a number also seen in - * vendor kernel sources) - * - * This mainboard seems to be equipped with different SoCs. - * In the Toline Shine 3 ebook reader it is a i.MX6SL - * - * Copyright 2019 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" -#include "e60k02.dtsi" - -/ { - model = "Tolino Shine 3"; - compatible = "kobo,tolino-shine3", "fsl,imx6sl"; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ - MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x10059 /* TP_RST */ - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ - MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 - MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 - MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 - MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 - MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 - MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 - MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 - MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 - MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 - MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 - MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 - MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 - MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 - MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 - MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 - MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 - MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 - MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 - MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 - MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 - MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 - MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 - MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 - MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 - MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh_gpiogrp { - fsl,pins = < - MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ - MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ - MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 - MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2grp-sleep { - fsl,pins = < - MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 - MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 - MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 - MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grp-sleep { - fsl,pins = < - MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 - MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 - MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 - MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; -}; - -&lm3630a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; -}; - -®_wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; -}; - -®_vdd1p1 { - vin-supply = <&dcdc2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&dcdc2_reg>; -}; - -&ricoh619 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; -}; - -&wifi_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; -}; diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/imx6sl-tolino-vision.dts deleted file mode 100644 index 2694fe18a91b..000000000000 --- a/arch/arm/boot/dts/imx6sl-tolino-vision.dts +++ /dev/null @@ -1,490 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for the Tolino Vison ebook reader - * - * Name on mainboard is: 37NB-E60Q30+4A3 - * Serials start with: 6032 - * - * Copyright 2023 Andreas Kemnade - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6sl.dtsi" - -/ { - model = "Tolino Vision"; - compatible = "kobo,tolino-vision", "fsl,imx6sl"; - - aliases { - mmc0 = &usdhc4; - mmc1 = &usdhc2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ec 0 50000>; - power-supply = <&backlight_regulator>; - }; - - backlight_regulator: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_power>; - regulator-name = "backlight"; - gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-cover { - /* magnetic sensor in the corner next to the uSD slot */ - label = "Cover"; - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - - key-fl { - label = "Frontlight"; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-power { - label = "Power"; - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - /* LED on home button */ - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - }; - - led-1 { - /* LED on power button */ - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; - regulator-name = "SD3_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - }; - - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - post-power-on-delay-ms = <20>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; - status = "okay"; - - touchscreen@15 { - compatible = "elan,ektf2132"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - power-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; - interrupts-extended = <&gpio5 6 IRQ_TYPE_EDGE_FALLING>; - }; - - accelerometer@1d { - compatible = "fsl,mma8652"; - reg = <0x1d>; - }; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - ec: embedded-controller@43 { - compatible = "netronix,ntxec"; - reg = <0x43>; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ec>; - interrupts-extended = <&gpio5 11 IRQ_TYPE_EDGE_FALLING>; - system-power-controller; - }; -}; - -&snvs_rtc { - /* - * We are using the RTC in the PMIC, but this one is not disabled - * in imx6sl.dtsi. - */ - status = "disabled"; -}; - -&uart1 { - /* J4 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - /* J9 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; - cd-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - status = "okay"; - - /* removable uSD card */ -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; - vmmc-supply = <®_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - cap-power-off-card; - non-removable; - status = "okay"; - - /* CyberTan WC121 (BCM43362) SDIO WiFi */ -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc4>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - pinctrl-3 = <&pinctrl_usdhc4_sleep>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; - - /* internal eMMC */ -}; - -&usbotg1 { - pinctrl-names = "default"; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&iomuxc { - pinctrl_backlight_power: backlight-powergrp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 - >; - }; - - pinctrl_ec: ecgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x17000 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x110B0 - MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x110B0 - MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x11030 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1-sleepgrp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2-sleepgrp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 - MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x17059 - MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x110B0 - MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x1B0B1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 - MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x1b0b1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2-sleepgrp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 - MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 - MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 - MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3-sleepgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 - MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 - MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 - MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x17059 - MX6SL_PAD_FEC_MDIO__SD4_CLK 0x13059 - MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x17059 - MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x17059 - MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x17059 - MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x17059 - MX6SL_PAD_FEC_MDC__SD4_DATA4 0x17059 - MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x17059 - MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x17059 - MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x17059 - MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x17068 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { - fsl,pins = < - MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170b9 - MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130b9 - MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170b9 - MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170b9 - MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170b9 - MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170b9 - MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170b9 - MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170b9 - MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170b9 - MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { - fsl,pins = < - MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170f9 - MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130f9 - MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170f9 - MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170f9 - MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170f9 - MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170f9 - MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170f9 - MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170f9 - MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170f9 - MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4_sleep: usdhc4-sleepgrp { - fsl,pins = < - MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x100c1 - MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x100c1 - MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x100c1 - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x100c1 - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x100c1 - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x100c1 - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x100c1 - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x100c1 - MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x100c1 - MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts deleted file mode 100644 index 6bc342035e2b..000000000000 --- a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts +++ /dev/null @@ -1,356 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * Device tree for the Tolino Vision 5 ebook reader - * - * Name on mainboard is: 37NB-E70K0M+6A3 - * Serials start with: E70K02 (a number also seen in - * vendor kernel sources) - * - * This mainboard seems to be equipped with different SoCs. - * In the Tolino Vision 5 ebook reader it is a i.MX6SL - * - * Copyright 2021 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" -#include "e70k02.dtsi" - -/ { - model = "Tolino Vision 5"; - compatible = "kobo,tolino-vision5", "fsl,imx6sl"; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { - fsl,pins = < - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x17059 /* TP_INT */ - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x10059 /* TP_RST */ - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x17059 /* HALL_EN */ - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */ - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 - MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 - MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 - MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 - MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 - MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 - MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 - MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 - MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 - MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 - MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 - MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 - MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 - MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 - MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 - MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 - MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 - MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 - MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 - MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 - MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 - MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x79 - MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x79 - MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x10059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh-gpiogrp { - fsl,pins = < - MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */ - MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */ - MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x17059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x170b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x170f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_sleep: usdhc1-sleepgrp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x10059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x10059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x10059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x10059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x10059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x10059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x10059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x10059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x10059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3-sleepgrp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 - MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 - MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 - MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; -}; - -&lm3630a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; -}; - -®_wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; -}; - -®_vdd1p1 { - vin-supply = <&dcdc2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&dcdc2_reg>; -}; - -®_arm { - vin-supply = <&dcdc3_reg>; -}; - -®_soc { - vin-supply = <&dcdc1_reg>; -}; - -®_pu { - vin-supply = <&dcdc1_reg>; -}; - -&ricoh619 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-3 = <&pinctrl_usdhc1_sleep>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; -}; - -&wifi_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; -}; diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts deleted file mode 100644 index 9d7c8884892a..000000000000 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2014, 2015 O.S. Systems Software LTDA. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "imx6sl.dtsi" - -/ { - model = "Revotics WaRP Board"; - compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ - <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ - <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ - <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ - <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - wakeup-source; - mmc-pwrseq = <&usdhc3_pwrseq>; - status = "okay"; -}; - -&iomuxc { - imx6sl-warp { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 - >; - }; - - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 - MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 - MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 - MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 - MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 - MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi deleted file mode 100644 index 28111efb19a6..000000000000 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ /dev/null @@ -1,1008 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include -#include "imx6sl-pinfunc.h" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usb0 = &usbotg1; - usb1 = &usbotg2; - usb2 = &usbh; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - operating-points = - /* kHz uV */ - <996000 1275000>, - <792000 1175000>, - <396000 975000>; - fsl,soc-operating-points = - /* ARM kHz SOC-PU uV */ - <996000 1225000>, - <792000 1175000>, - <396000 1175000>; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6SL_CLK_OCRAM>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: cache-controller@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - aips1: bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba: spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sl-spdif", - "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, - <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI1>, - <&clks IMX6SL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI2>, - <&clks IMX6SL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI3>, - <&clks IMX6SL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI4>, - <&clks IMX6SL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@2018000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@2024000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02024000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI1_IPG>, - <&clks IMX6SL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI2_IPG>, - <&clks IMX6SL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI3_IPG>, - <&clks IMX6SL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - uart3: serial@2034000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02034000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@2038000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02038000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - pwm1: pwm@2080000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM1>; - clock-names = "ipg", "per"; - }; - - pwm2: pwm@2084000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM2>; - clock-names = "ipg", "per"; - }; - - pwm3: pwm@2088000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM3>; - clock-names = "ipg", "per"; - }; - - pwm4: pwm@208c000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM4>; - clock-names = "ipg", "per"; - }; - - gpt: timer@2098000 { - compatible = "fsl,imx6sl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_GPT>, - <&clks IMX6SL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, - <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, - <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, - <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, - <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, - <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, - <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, - <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, - <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, - <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, - <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, - <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, - <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, - <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, - <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, - <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, - <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, - <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, - <&iomuxc 31 102 1>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, - <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, - <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, - <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, - <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, - <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, - <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, - <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, - <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, - <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, - <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, - <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, - <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, - <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, - <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, - <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, - <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, - <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, - <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, - <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, - <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, - <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, - <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, - <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, - <&iomuxc 21 161 1>; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6sl-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sl-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2850000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6sl-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - }; - - pd_disp: power-domain@2 { - reg = <2>; - #power-domain-cells = <0>; - clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_EPDC_AXI>, - <&clks IMX6SL_CLK_EPDC_PIX>, - <&clks IMX6SL_CLK_PXP_AXI>; - }; - }; - }; - - gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6sl-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - csi: csi@20e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - spdc: spdc@20e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: dma-controller@20ec000 { - compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SDMA>, - <&clks IMX6SL_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sl reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - - lcdif: lcdif@20f8000 { - compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; - reg = <0x020f8000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - power-domains = <&pd_disp>; - }; - - dcp: crypto@20fc000 { - compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; - reg = <0x020fc000 0x4000>; - interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, - <0 100 IRQ_TYPE_LEVEL_HIGH>, - <0 101 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@2184400 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - }; - - fec: ethernet@2188000 { - compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; - reg = <0x02188000 0x4000>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ENET>, - <&clks IMX6SL_CLK_ENET_REF>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@2198000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: mmc@219c000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; - }; - - rngb: rngb@21b4000 { - compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; - reg = <0x021b4000 0x4000>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: efuse@21bc000 { - compatible = "fsl,imx6sl-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SL_CLK_OCOTP>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - }; - - gpu_2d: gpu@2200000 { - compatible = "vivante,gc"; - reg = <0x02200000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, - <&clks IMX6SL_CLK_GPU2D_OVG>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - }; - - gpu_vg: gpu@2204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, - <&clks IMX6SL_CLK_GPU2D_OVG>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts deleted file mode 100644 index e3e9b0ec4f73..000000000000 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ /dev/null @@ -1,643 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -/dts-v1/; - -#include -#include -#include "imx6sll.dtsi" - -/ { - model = "Freescale i.MX6SLL EVK Board"; - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-user { - label = "debug"; - gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_usb_otg1_vbus: regulator-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2_vbus>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_aud3v: regulator-aud3v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; - - reg_aud4v: regulator-aud4v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sd2_vmmc: regulator-sd2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "eMMC-VCCQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - reg_sd3_vmmc: regulator-sd3-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; - regulator-name = "SD3_WIFI"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - model = "wm8962-audio"; - audio-cpu = <&ssi2>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux3>; - status = "okay"; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; - soc-supply = <&sw1c_reg>; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; - DCVDD-supply = <&vgen3_reg>; - DBVDD-supply = <®_aud3v>; - AVDD-supply = <&vgen3_reg>; - CPVDD-supply = <&vgen3_reg>; - MICVDD-supply = <®_aud3v>; - PLLVDD-supply = <&vgen3_reg>; - SPKVDD1-supply = <®_aud4v>; - SPKVDD2-supply = <®_aud4v>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - non-removable; - vqmmc-supply = <®_sd2_vmmc>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd3_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux3: audmux3grp { - fsl,pins = < - MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 - MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 - MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 - MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 - MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ - >; - }; - - pinctrl_reg_sd3_vmmc: sd3vmmcgrp { - fsl,pins = < - MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 - >; - }; - - pinctrl_usb_otg1_vbus: vbus1grp { - fsl,pins = < - MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 - >; - }; - - pinctrl_usb_otg2_vbus: vbus2grp { - fsl,pins = < - MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 - >; - }; - - pinctrl_reg_lcd_3v3: reglcd3v3grp { - fsl,pins = < - MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 - >; - }; - - pinctrl_reg_sd1_vmmc: sd1vmmcgrp { - fsl,pins = < - MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 - MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 - MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 - MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 - MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 - MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 - MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x13059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 - MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 - MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 - MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 - MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 - MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 - MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 - MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 - MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 - MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 - MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130f9 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 - MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 - MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 - MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 - MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 - MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 - MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 - MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 - MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 - MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 - MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 - MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 - MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 - MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 - MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 - MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 - >; - }; - - pinctrl_pwm1: pmw1grp { - fsl,pins = < - MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts deleted file mode 100644 index c7cfe0b70f04..000000000000 --- a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts +++ /dev/null @@ -1,342 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * Device tree for the Kobo Clara HD ebook reader - * - * Name on mainboard is: 37NB-E60K00+4A4 - * Serials start with: E60K02 (a number also seen in - * vendor kernel sources) - * - * This mainboard seems to be equipped with different SoCs. - * In the Kobo Clara HD ebook reader it is an i.MX6SLL - * - * Copyright 2019 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include -#include -#include "imx6sll.dtsi" -#include "e60k02.dtsi" - -/ { - model = "Kobo Clara HD"; - compatible = "kobo,clarahd", "fsl,imx6sll"; -}; - -&clks { - assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <393216000>; -}; - -&cpu0 { - arm-supply = <&dcdc3_reg>; - soc-supply = <&dcdc1_reg>; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { - fsl,pins = < - MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x17059 /* TP_INT */ - MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x10059 /* TP_RST */ - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ - MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79 - MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 - MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79 - MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79 - MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 - MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 - MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 - MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 - MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 - MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 - MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 - MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 - MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 - MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 - MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 - MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 - MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 - MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 - MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 - MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 - MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 - MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 - MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 - MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 - MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh-gpiogrp { - fsl,pins = < - MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ - MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ - MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 - MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1 - MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2grp-sleep { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 - MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 - MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 - MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grp-sleep { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 - MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 - MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 - MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; -}; - -&lm3630a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; -}; - -®_wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; -}; - -&ricoh619 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; -}; - -&wifi_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; -}; diff --git a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts deleted file mode 100644 index 7e4f38dd11e2..000000000000 --- a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * Device tree for the Kobo Libra H2O ebook reader - * - * Name on mainboard is: 37NB-E70K0M+6A3 - * Serials start with: E70K02 (a number also seen in - * vendor kernel sources) - * - * This mainboard seems to be equipped with different SoCs. - * In the Kobo Libra H2O ebook reader it is an i.MX6SLL - * - * Copyright 2021 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include -#include -#include "imx6sll.dtsi" -#include "e70k02.dtsi" - -/ { - model = "Kobo Libra H2O"; - compatible = "kobo,librah2o", "fsl,imx6sll"; -}; - -&clks { - assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <393216000>; -}; - -&cpu0 { - arm-supply = <&dcdc3_reg>; - soc-supply = <&dcdc1_reg>; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { - fsl,pins = < - MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* TP_INT */ - MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */ - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ - MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x17059 /* HALL_EN */ - MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */ - MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 - MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 - MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 - MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 - MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 - MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 - MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 - MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 - MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 - MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 - MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 - MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 - MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 - MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 - MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 - MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 - MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 - MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 - MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 - MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 - MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 - MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x79 - MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x79 - MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x10059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh-gpiogrp { - fsl,pins = < - MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */ - MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */ - MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 - MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 - MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x17059 - MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x17059 - MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x17059 - MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 - MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9 - MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9 - MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9 - MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 - MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9 - MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9 - MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9 - MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_sleep: usdhc1-sleepgrp { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x10059 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x10059 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x10059 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x10059 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x10059 - MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x10059 - MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x10059 - MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x10059 - MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x10059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3-sleepgrp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 - MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 - MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 - MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; -}; - -&lm3630a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; -}; - -®_wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; -}; - -&ricoh619 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-3 = <&pinctrl_usdhc1_sleep>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; -}; - -&wifi_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; -}; diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h deleted file mode 100644 index 713a346f4c89..000000000000 --- a/arch/arm/boot/dts/imx6sll-pinfunc.h +++ /dev/null @@ -1,880 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DTS_IMX6SLL_PINFUNC_H -#define __DTS_IMX6SLL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 -#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 -#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 -#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 -#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 -#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 -#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 -#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 -#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 -#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 -#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 -#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 -#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 -#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 -#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 -#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 -#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 -#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 -#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 -#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 -#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 -#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 -#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 -#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 -#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 -#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 -#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 -#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 -#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 -#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 -#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 -#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 -#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 -#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 -#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 -#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 -#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 -#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 -#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 -#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 -#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 -#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 -#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 -#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 -#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 -#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 -#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 -#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 -#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 -#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 -#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 -#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 -#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 -#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 -#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 -#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 -#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 -#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 -#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 -#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 -#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 -#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 -#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 -#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 -#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 -#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 -#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 -#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 -#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 -#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 -#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 -#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 -#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 -#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 -#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 -#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 -#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 -#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 -#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 -#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 -#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 -#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 -#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 -#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 -#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 -#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 -#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 -#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 -#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 -#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 -#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 -#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 -#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 -#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 -#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 -#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 -#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 -#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 -#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 -#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 -#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 -#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 -#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 -#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 -#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 -#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 -#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 -#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 -#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 -#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 -#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 -#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 -#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 -#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 -#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 -#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 -#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 -#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 -#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 -#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 -#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 -#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 -#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 -#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 -#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 -#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 -#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 -#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 -#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 -#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 -#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 -#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 -#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 -#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 -#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 -#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 -#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 -#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 -#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 -#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 -#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 -#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 -#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 -#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 -#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 -#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 -#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 -#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 -#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 -#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 -#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 -#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 -#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 -#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 -#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 -#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 -#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 -#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 -#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 -#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 -#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 -#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 -#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 -#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 -#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 -#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 -#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 -#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 -#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 -#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 -#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 -#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 -#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 -#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 -#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 -#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 -#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 -#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 -#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 -#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 -#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 -#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 -#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 -#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 -#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 -#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 -#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 -#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 -#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 -#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 -#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 -#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 -#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 -#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 -#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 -#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 - -#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi deleted file mode 100644 index 2873369a57c0..000000000000 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ /dev/null @@ -1,839 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#include -#include -#include -#include "imx6sll-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi3 = &ecspi3; - spi4 = &ecspi4; - usb0 = &usbotg1; - usb1 = &usbotg2; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = - /* kHz uV */ - <996000 1275000>, - <792000 1175000>, - <396000 1075000>, - <198000 975000>; - fsl,soc-operating-points = - /* ARM kHz SOC-PU uV */ - <996000 1175000>, - <792000 1175000>, - <396000 1175000>, - <198000 1175000>; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SLL_CLK_ARM>, - <&clks IMX6SLL_CLK_PLL2_PFD2>, - <&clks IMX6SLL_CLK_STEP>, - <&clks IMX6SLL_CLK_PLL1_SW>, - <&clks IMX6SLL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-ipp-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-ipp-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: cache-controller@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - aips1: bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba: spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = ; - dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, - <&clks IMX6SLL_CLK_OSC>, - <&clks IMX6SLL_CLK_SPDIF>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_IPG>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "dma"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI1>, - <&clks IMX6SLL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI2>, - <&clks IMX6SLL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI3>, - <&clks IMX6SLL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI4>, - <&clks IMX6SLL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@2018000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = ; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART4_IPG>, - <&clks IMX6SLL_CLK_UART4_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART1_IPG>, - <&clks IMX6SLL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@2024000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02024000 0x4000>; - interrupts = ; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART2_IPG>, - <&clks IMX6SLL_CLK_UART2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = ; - dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, - <&clks IMX6SLL_CLK_SSI1>; - clock-names = "ipg", "baud"; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = ; - dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, - <&clks IMX6SLL_CLK_SSI2>; - clock-names = "ipg", "baud"; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = ; - dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, - <&clks IMX6SLL_CLK_SSI3>; - clock-names = "ipg", "baud"; - status = "disabled"; - }; - - uart3: serial@2034000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02034000 0x4000>; - interrupts = ; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-name = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART3_IPG>, - <&clks IMX6SLL_CLK_UART3_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - pwm1: pwm@2080000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM1>, - <&clks IMX6SLL_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm2: pwm@2084000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM2>, - <&clks IMX6SLL_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm3: pwm@2088000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM3>, - <&clks IMX6SLL_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm4: pwm@208c000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM4>, - <&clks IMX6SLL_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - gpt1: timer@2098000 { - compatible = "fsl,imx6sl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_GPT_BUS>, - <&clks IMX6SLL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 50 32>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>, - <&iomuxc 16 101 2>, <&iomuxc 18 5 1>, - <&iomuxc 21 6 11>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>, - <&iomuxc 16 151 1>, <&iomuxc 17 149 1>, - <&iomuxc 18 146 1>, <&iomuxc 19 144 1>, - <&iomuxc 20 142 1>, <&iomuxc 21 143 1>, - <&iomuxc 22 150 1>, <&iomuxc 23 148 1>, - <&iomuxc 24 147 1>, <&iomuxc 25 145 1>, - <&iomuxc 26 152 1>, <&iomuxc 27 125 1>, - <&iomuxc 28 131 1>, <&iomuxc 29 134 1>, - <&iomuxc 30 129 1>, <&iomuxc 31 133 1>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>, - <&iomuxc 2 132 1>, <&iomuxc 3 130 1>, - <&iomuxc 4 127 1>, <&iomuxc 5 126 1>, - <&iomuxc 6 120 1>, <&iomuxc 7 123 1>, - <&iomuxc 8 118 1>, <&iomuxc 9 122 1>, - <&iomuxc 10 124 1>, <&iomuxc 11 117 1>, - <&iomuxc 12 121 1>, <&iomuxc 13 119 1>, - <&iomuxc 14 116 1>, <&iomuxc 15 115 1>, - <&iomuxc 16 140 2>, <&iomuxc 18 136 1>, - <&iomuxc 19 138 1>, <&iomuxc 20 139 1>, - <&iomuxc 21 137 1>; - }; - - gpio6: gpio@20b0000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO6>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_KPP>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_WDOG1>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_WDOG2>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6sll-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - - assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; - assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sll-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x4000>; - interrupts = , - , - ; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p0: regulator-3p0@20c8120 { - compatible = "fsl,anatop-regulator"; - reg = <0x20c8120>; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2625000>; - regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - tempmon: temperature-sensor { - compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; - interrupts = ; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; - }; - }; - - usbphy1: usb-phy@20c9000 { - compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", - "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBPHY1>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usb-phy@20ca000 { - compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", - "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBPHY2>; - phy-reg_3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x61>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6sll-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: interrupt-controller@20dc000 { - compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6sll-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@20e4000 { - compatible = "fsl,imx6sll-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - csi: csi@20e8000 { - compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; - reg = <0x020e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_CSI>, - <&clks IMX6SLL_CLK_DUMMY>; - clock-names = "disp-axi", "csi_mclk", "disp_dcic"; - status = "disabled"; - }; - - sdma: dma-controller@20ec000 { - compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_IPG>, - <&clks IMX6SLL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - iram = <&ocram>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pxp: pxp@20f0000 { - compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp"; - reg = <0x20f0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_PXP>; - clock-names = "axi"; - }; - - lcdif: lcd-controller@20f8000 { - compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; - reg = <0x020f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, - <&clks IMX6SLL_CLK_LCDIF_APB>, - <&clks IMX6SLL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - dcp: crypto@20fc000 { - compatible = "fsl,imx28-dcp"; - reg = <0x020fc000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6SLL_CLK_DCP>; - clock-names = "dcp"; - }; - }; - - aips2: bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", - "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", - "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USDHC1>, - <&clks IMX6SLL_CLK_USDHC1>, - <&clks IMX6SLL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USDHC2>, - <&clks IMX6SLL_CLK_USDHC2>, - <&clks IMX6SLL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - usdhc3: mmc@2198000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USDHC3>, - <&clks IMX6SLL_CLK_USDHC3>, - <&clks IMX6SLL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_I2C3>; - status = "disabled"; - }; - - mmdc: memory-controller@21b0000 { - compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; - }; - - rngb: rng@21b4000 { - compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb"; - reg = <0x021b4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_DUMMY>; - }; - - ocotp: efuse@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sll-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SLL_CLK_OCOTP>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART5_IPG>, - <&clks IMX6SLL_CLK_UART5_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts deleted file mode 100644 index a2c79bcf9a11..000000000000 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ /dev/null @@ -1,603 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx6sx.dtsi" - -/ { - model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; - compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3p3v>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_3v3: regulator-can1-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlan>; - compatible = "regulator-fixed"; - clocks = <&clks IMX6SX_CLK_CKO>; - clock-names = "slow"; - regulator-name = "wlan-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6sx-nitrogen6sx-sgtl5000"; - cpu-dai = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - read-only; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x2000>; - read-only; - }; - - partition@c2000 { - label = "Kernel"; - reg = <0xc2000 0x11e000>; - }; - - partition@1e0000 { - label = "M4"; - reg = <0x1e0000 0x20000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@4 { - reg = <4>; - }; - - ethphy2: ethernet-phy@5 { - reg = <5>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_3v3>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6SX_CLK_CKO2>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - VDDD-supply = <®_1p8v>; - assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, - <&clks IMX6SX_CLK_CKO2>; - assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; - assigned-clock-rates = <0>, <24000000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm4 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - disable-over-current; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - vmmc-supply = <®_wlan>; - cap-power-off-card; - cap-sdio-irq; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4_50mhz>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 - MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 - MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 - MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 - MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 - MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 - MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 - MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 - MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 - MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 - MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 - MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 - MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 - MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 - MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 - /* Test points */ - MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 - MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 - MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_reg_wlan: reg-wlangrp { - fsl,pins = < - MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 - MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 - MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 - >; - }; - - pinctrl_usbotg1_vbus: usbotg1-vbusgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 - >; - }; - - pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 - MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h deleted file mode 100644 index f4dc46207954..000000000000 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ /dev/null @@ -1,1668 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6SX_PINFUNC_H -#define __DTS_IMX6SX_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 -#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 -#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 -#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 -#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 -#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 -#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 -#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 -#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 -#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 -#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 -#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 -#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 -#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 -#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 -#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 -#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1 -#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 -#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 -#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 -#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1 -#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 -#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 -#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 -#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2 -#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 -#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 -#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2 -#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 -#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 -#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3 -#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 -#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 -#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 -#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 -#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3 -#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 -#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 -#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 -#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 -#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 -#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 -#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 -#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 -#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 -#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 -#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 -#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 -/* - * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is - * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a - * PHY in RMII mode. This configuration is valid if: - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset - * It seems to be a silicon bug that in this configuration ENET1_TX reference - * clock isn't provided automatically. According to i.MX6SX reference manual - * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it - * should be the case. - * So this might have unwanted side effects for other hardware units that are - * also connected to that pin and using respective function as input (e.g. - * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). - */ -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 -#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2 -#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 -#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 -#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 -#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 -#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3 -#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 -#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 -#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3 -#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 -#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2 -#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 -#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 -#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 -#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 -#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2 -#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 -#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 -#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 -#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 -#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2 -#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2 -#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 -#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 -#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3 -#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 -#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 -#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 -#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3 -#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 -#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 -#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 -#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 -#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3 -#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 -#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 -#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3 -#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 -#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 -#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 -#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 -#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 -#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 -#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 -#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 -#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 -#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 -#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 -#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 -#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 -#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 -#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 -#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 -#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 -#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 -#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 -#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 -#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 -#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 -#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 -#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 -#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 -#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 -#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 -#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 -#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 -#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 -#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 -#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 -#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 -#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 -#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 -#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 -#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 -#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 -#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1 -#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 -#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1 -#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 -#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 -#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 -#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 -#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 -#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 -#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 -#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 -#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 -#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4 -#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 -#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 -#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5 -#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 -#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 -#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 -#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2 -#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3 -#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 -#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2 -#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 -#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3 -#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 -#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 -#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 -#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 -#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 -#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 -#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 -#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 -#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 -#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 -#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 -#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4 -#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 -#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 -#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 -#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5 -#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 -#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 -#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 -#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 -#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4 -#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 -#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 -#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 -#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 -#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5 -#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0 -#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 -#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 -#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 -#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 -#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 -#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 -#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 -#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 -#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1 -#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 -#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1 -#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 -#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 -#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 -#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2 -#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3 -#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2 -#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 -#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3 -#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 -#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 -#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 -#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 -#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 -#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 -#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 -#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 -#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 -#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 -#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 -#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1 -#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 -#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 -#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 -#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 -#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1 -#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 -#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 -#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 -#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 -#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 -#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 - -/* these are not supposed to be used any more and remove them after some time */ -#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX -#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX -#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX -#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX -#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX -#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX -#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS -#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX -#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX -#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS -#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS -#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS -#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX -#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX -#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX -#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX -#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS -#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS -#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS -#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX -#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX -#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX -#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX -#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS -#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX -#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX -#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX -#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX -#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS -#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS -#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS -#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX -#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX -#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS -#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX -#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX -#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS -#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX -#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX -#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS -#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX -#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX -#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS -#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS -#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX -#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX -#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX -#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX -#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS -#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS -#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX -#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX -#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX -#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX -#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX -#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX -#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS -#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS -#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX -#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX -#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX -#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX -#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX -#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX -#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX -#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX -#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS -#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX -#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX -#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS -#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX -#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX -#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX -#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX -#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX -#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX -#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS -#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS -#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX -#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX -#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX -#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX -#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS -#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS - -#endif /* __DTS_IMX6SX_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts deleted file mode 100644 index b0c27b9b0244..000000000000 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ /dev/null @@ -1,557 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2014 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6sx.dtsi" - -/ { - model = "Freescale i.MX6 SoloX Sabre Auto Board"; - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led-user { - label = "debug"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_sd3: regulator-vcc-sd3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_wake: regulator-can-wake { - compatible = "regulator-fixed"; - regulator-name = "can-wake"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_wake>; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; - }; - - reg_cs42888: cs42888_supply { - compatible = "regulator-fixed"; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound-cs42888 { - compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; - model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; - audio-codec = <&cs42888>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - }; -}; - -&anaclk2 { - clock-frequency = <24576000>; -}; - -&clks { - assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, - <&clks IMX6SX_PLL4_BYPASS>, - <&clks IMX6SX_CLK_PLL4_POST_DIV>; - assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, - <&clks IMX6SX_PLL4_BYPASS_SRC>; - assigned-clock-rates = <0>, <0>, <24576000>; -}; - -&esai { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esai>; - assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, - <&clks IMX6SX_CLK_ESAI_EXTAL>; - assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&iomuxc { - pinctrl_egalax_int: egalax-intgrp { - fsl,pins = < - MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - >; - }; - - pinctrl_esai: esaigrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 - MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 - MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 - MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 - MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 - MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 - MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 - MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 - MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 - MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - cs42888: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&anaclk2 0>; - clock-names = "mclk"; - VA-supply = <®_cs42888>; - VD-supply = <®_cs42888>; - VLS-supply = <®_cs42888>; - VLC-supply = <®_cs42888>; - }; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_egalax_int>; - interrupt-parent = <&gpio6>; - interrupts = <22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; - }; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - max7310_a: gpio@30 { - compatible = "maxim,max7310"; - reg = <0x30>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_b: gpio@32 { - compatible = "maxim,max7310"; - reg = <0x32>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts deleted file mode 100644 index a4ab2d3e960c..000000000000 --- a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2014 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dts" -/ { - - sound { - status = "disabled"; - }; - - sound-mqs { - compatible = "fsl,imx6sx-sdb-mqs", - "fsl,imx-audio-mqs"; - model = "mqs-audio"; - audio-cpu = <&sai1>; - audio-asrc = <&asrc>; - audio-codec = <&mqs>; - }; -}; - -&usdhc2 { - /* pin conflict with mqs*/ - status = "disabled"; -}; - -&mqs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mqs>; - clocks = <&clks IMX6SX_CLK_SAI1>; - clock-names = "mclk"; - status = "okay"; -}; - -&sai1 { - pinctrl-0 = <>; - status = "okay"; -}; - -&ssi2 { - status = "disabled"; -}; - -&sdma { - gpr = <&gpr>; - /* SDMA event remap for SAI1 */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts deleted file mode 100644 index 48f19dede467..000000000000 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB RevA Board"; - compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; - - flash1: flash@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; -}; - -®_can_en { - /* Transceiver EN/STBY is active high on RevA board */ - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; - -®_can_stby { - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; -}; - -®_vdd1p1 { - vin-supply = <&vgen6_reg>; -}; - -®_vdd2p5 { - vin-supply = <&vgen6_reg>; -}; - -&snvs_pwrkey { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/imx6sx-sdb-sai.dts deleted file mode 100644 index 1c4eacd68e1b..000000000000 --- a/arch/arm/boot/dts/imx6sx-sdb-sai.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2016 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dts" - -/ { - sound { - audio-cpu = <&sai1>; - }; -}; - -&audmux { - /* pin conflict with sai */ - status = "disabled"; -}; - -&sai1 { - status = "okay"; -}; - -&sdma { - gpr = <&gpr>; - /* SDMA event remap for SAI1 */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; - -&ssi2 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts deleted file mode 100644 index e05a1be5553c..000000000000 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB RevB Board"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - flash1: flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <2>; - }; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_soc { - vin-supply = <&sw1a_reg>; -}; - -®_vdd1p1 { - vin-supply = <&vgen6_reg>; -}; - -®_vdd2p5 { - vin-supply = <&vgen6_reg>; -}; - -®_can_stby { - /* Transceiver EN/STBY is active low on RevB board */ - gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; -}; - -&snvs_pwrkey { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi deleted file mode 100644 index c6e85e4a0883..000000000000 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ /dev/null @@ -1,718 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2014 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include -#include -#include "imx6sx.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB Board"; - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - vcc_sd3: regulator-vcc-sd3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_psu_5v: regulator-psu-5v { - compatible = "regulator-fixed"; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; - - reg_peri_3v3: regulator-peri-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_enet_3v3: regulator-enet-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - regulator-boot-on; - regulator-always-on; - }; - - reg_pcie_gpio: regulator-pcie-gpio { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound { - compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <6>; - hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif", - "fsl,imx6sx-sdb-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; - -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-supply = <®_enet_3v3>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy2>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SX_CLK_AUDIO>; - DCVDD-supply = <&vgen4_reg>; - DBVDD-supply = <&vgen4_reg>; - AVDD-supply = <&vgen4_reg>; - CPVDD-supply = <&vgen4_reg>; - MICVDD-supply = <&vgen3_reg>; - PLLVDD-supply = <&vgen4_reg>; - SPKVDD1-supply = <®_psu_5v>; - SPKVDD2-supply = <®_psu_5v>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie_gpio>; - status = "okay"; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "disabled"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart5 { /* for bluetooth */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6x-sdb { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 - MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 - MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 - MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 - /* phy reset */ - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 - >; - }; - - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 - MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 - MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - >; - }; - - pinctrl_mqs: mqsgrp { - fsl,pins = < - MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 - MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 - >; - }; - - pinctrl_peri_3v3: peri3v3grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 - >; - }; - - pinctrl_pwm3: pwm3grp-1 { - fsl,pins = < - MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_qspi2: qspi2grp { - fsl,pins = < - MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 - MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 - MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 - MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 - MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 - MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 - MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 - MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 - MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 - MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 - MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 - MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 - MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 - MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 - MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 - MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 - MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts deleted file mode 100644 index bfcd8f7d86dd..000000000000 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Christoph Fritz - */ - -/dts-v1/; - -#include -#include -#include "imx6sx.dtsi" - -/ { - model = "Softing VIN|ING 2000"; - compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reg_usb_otg1_vbus: regulator-usb_otg1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_peri_3v3: regulator-peri_3v3 { - compatible = "regulator-fixed"; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "red"; - max-brightness = <255>; - pwms = <&pwm6 0 50000>; - }; - - led-2 { - label = "green"; - max-brightness = <255>; - pwms = <&pwm2 0 50000>; - }; - - led-3 { - label = "blue"; - max-brightness = <255>; - pwms = <&pwm1 0 50000>; - }; - }; -}; - -&adc1 { - vref-supply = <®_peri_3v3>; - status = "okay"; -}; - -&cpu0 { - /* - * This board has a shared rail of reg_arm and reg_soc (supplied by - * sw1a_reg) which is modeled below, but still this module behaves - * unstable without higher voltages. Hence, set higher voltages here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC uV */ - 996000 1250000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-supply = <®_peri_3v3>; - phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <5>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet0-phy@0 { - reg = <0>; - max-speed = <100>; - interrupt-parent = <&gpio2>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-supply = <®_peri_3v3>; - phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <5>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet1-phy@0 { - reg = <0>; - max-speed = <100>; - interrupt-parent = <&gpio2>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - proximity: sx9500@28 { - compatible = "semtech,sx9500"; - reg = <0x28>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sx9500>; - interrupt-parent = <&gpio2>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - }; - - pmic: pmic@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 - MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 - MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 - MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 - MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 - /* LAN8720 PHY Reset */ - MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 - /* MDIO */ - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 - /* IRQ from PHY */ - MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 - MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 - /* LAN8720 PHY Reset */ - MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 - /* MDIO */ - MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 - MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 - /* IRQ from PHY */ - MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - /* reset external uC */ - MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 - /* IRQ from external uC */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 - /* overcurrent detection */ - MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 - >; - }; - - pinctrl_pwm1: pwm1grp-1 { - fsl,pins = < - /* blue LED */ - MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp-1 { - fsl,pins = < - /* green LED */ - MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm6: pwm6grp-1 { - fsl,pins = < - /* red LED */ - MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 - >; - }; - - pinctrl_sx9500: sx9500grp { - fsl,pins = < - /* Reset */ - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 - /* IRQ */ - MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { - fsl,pins = < - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 - MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 - MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4-100mhz { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4-200mhz { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm6 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm6>; - status = "okay"; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_soc { - vin-supply = <&sw1a_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_50mhz>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc4 { - /* hs200-mode is currently unsupported because Vccq is on 3.1V, but - * not on necessary 1.8V. - */ - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4_50mhz>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - bus-width = <8>; - keep-power-in-suspend; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts deleted file mode 100644 index 205ea26484e3..000000000000 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Basic"; - compatible = "udoo,neobasic", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&fec1 { - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts deleted file mode 100644 index 5817b4985391..000000000000 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Extended"; - compatible = "udoo,neoextended", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - status = "okay"; -}; - -&uart3 { /* Bluetooth */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts deleted file mode 100644 index 96f4d89848a3..000000000000 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Full"; - compatible = "udoo,neofull", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&fec1 { - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - status = "okay"; -}; - -&uart3 { /* Bluetooth */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi deleted file mode 100644 index 725d0b5cb55f..000000000000 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ /dev/null @@ -1,482 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "imx6sx.dtsi" - -/ { - compatible = "fsl,imx6sx"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-red { - label = "udoo-neo:red:mmc"; - gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led-orange { - label = "udoo-neo:orange:user"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - reg_sdio_pwr: regulator-sdio-pwr { - compatible = "regulator-fixed"; - gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "SDIO_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg1_reg>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg2_reg>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { /* Brick snap in sensors connector */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - hdmi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>; - - ports { - port { - hdmi: endpoint { - remote-endpoint = <&lcdc>; - }; - }; - }; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <100000>; - status = "disabled"; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - lcdc: endpoint { - remote-endpoint = <&hdmi>; - }; - }; -}; - -&iomuxc { - pinctrl_bt_reg: btreggrp { - fsl,pins = - ; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = - , - , - , - , - , - , - - , - , - , - , - , - , - - ; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = - , - ; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = - , - ; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = - , - ; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = - , - ; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - , - ; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - , - ; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - , - , - , - ; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = - , - ; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = - , - , - , - , - , - , - , - ; - }; - - pinctrl_otg1_reg: otg1grp { - fsl,pins = - ; - }; - - pinctrl_otg2_reg: otg2grp { - fsl,pins = - ; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = - , - ; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = - ; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - , - , - , - , - , - , - ; /* CD */ - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - , - , - , - , - , - , - , - , - ; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* Cortex-M4 serial */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&uart3 { /* Bluetooth - only on Extended/Full versions */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; - - bluetooth { - compatible = "ti,wl1831-st"; - enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - max-speed = <921600>; - }; -}; - -/* Arduino serial */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "disabled"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbotg1 { /* J2 micro USB port */ - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - status = "okay"; -}; - -&usbotg2 { /* J3 host USB port */ - vbus-supply = <®_usb_otg2_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_sdio_pwr>; - bus-width = <4>; - cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { /* Wi-Fi */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - vmmc-supply = <®_wlan>; - cap-power-off-card; - wakeup-source; - keep-power-in-suspend; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1831"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi deleted file mode 100644 index 3a4308666552..000000000000 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ /dev/null @@ -1,1469 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2014 Freescale Semiconductor, Inc. - -#include -#include -#include -#include -#include "imx6sx-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - can0 = &flexcan1; - can1 = &flexcan2; - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - spi4 = &ecspi5; - usb0 = &usbotg1; - usb1 = &usbotg2; - usb2 = &usbh; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SX_CLK_ARM>, - <&clks IMX6SX_CLK_PLL2_PFD2>, - <&clks IMX6SX_CLK_STEP>, - <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-ipp-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-ipp-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - anaclk1: clock-anaclk1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "anaclk1"; - }; - - anaclk2: clock-anaclk2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "anaclk2"; - }; - - mqs: mqs { - compatible = "fsl,imx6sx-mqs"; - gpr = <&gpr>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = ; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram_s: sram@8f8000 { - compatible = "mmio-sram"; - reg = <0x008f8000 0x4000>; - ranges = <0 0x008f8000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6SX_CLK_OCRAM_S>; - }; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clks IMX6SX_CLK_OCRAM>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: cache-controller@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - gpu: gpu@1800000 { - compatible = "vivante,gc"; - reg = <0x01800000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>; - clock-names = "bus", "core", "shader"; - power-domains = <&pd_pu>; - }; - - dma_apbh: dma-controller@1804000 { - compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6SX_CLK_APBH_DMA>; - }; - - gpmi: nand-controller@1806000{ - compatible = "fsl,imx6sx-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clks IMX6SX_CLK_GPMI_IO>, - <&clks IMX6SX_CLK_GPMI_APB>, - <&clks IMX6SX_CLK_GPMI_BCH>, - <&clks IMX6SX_CLK_GPMI_BCH_APB>, - <&clks IMX6SX_CLK_PER1_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = ; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, - <&clks IMX6SX_CLK_OSC>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_IPG>, - <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI1>, - <&clks IMX6SX_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI2>, - <&clks IMX6SX_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI3>, - <&clks IMX6SX_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI4>, - <&clks IMX6SX_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai: esai@2024000 { - compatible = "fsl,imx6sx-esai", "fsl,imx35-esai"; - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_ESAI_MEM>, - <&clks IMX6SX_CLK_ESAI_EXTAL>, - <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "mem", "extal", - "fsys", "spba"; - dmas = <&sdma 23 21 0>, - <&sdma 24 21 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI1_IPG>, - <&clks IMX6SX_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI2_IPG>, - <&clks IMX6SX_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI3_IPG>, - <&clks IMX6SX_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - asrc: asrc@2034000 { - compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck_0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "spba"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, - <&sdma 19 23 1>, <&sdma 20 23 1>, - <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; - status = "okay"; - }; - }; - - pwm1: pwm@2080000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM1>, - <&clks IMX6SX_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm2: pwm@2084000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM2>, - <&clks IMX6SX_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm3: pwm@2088000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM3>, - <&clks IMX6SX_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm4: pwm@208c000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM4>, - <&clks IMX6SX_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - flexcan1: can@2090000 { - compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_CAN1_IPG>, - <&clks IMX6SX_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1>; - status = "disabled"; - }; - - flexcan2: can@2094000 { - compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_CAN2_IPG>, - <&clks IMX6SX_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2>; - status = "disabled"; - }; - - gpt: timer@2098000 { - compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPT_BUS>, - <&clks IMX6SX_CLK_GPT_3M>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 5 26>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 31 20>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 51 29>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 80 32>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 24>; - }; - - gpio6: gpio@20b0000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; - }; - - gpio7: gpio@20b4000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020b4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6sx-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pcie: regulator-vddpcie { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6sx-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_soc>; - clocks = <&clks IMX6SX_CLK_GPU>; - }; - - pd_disp: power-domain@2 { - reg = <2>; - #power-domain-cells = <0>; - clocks = <&clks IMX6SX_CLK_PXP_AXI>, - <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_LCDIF2_PIX>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_VADC>; - }; - - pd_pci: power-domain@3 { - reg = <3>; - #power-domain-cells = <0>; - power-supply = <®_pcie>; - }; - }; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6sx-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: syscon@20e4000 { - compatible = "fsl,imx6sx-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x020e4000 0x4000>; - - lvds_bridge: bridge@18 { - compatible = "fsl,imx6sx-ldb"; - reg = <0x18 0x4>; - clocks = <&clks IMX6SX_CLK_LDB_DI0>; - clock-names = "ldb"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ldb_from_lcdif1: endpoint { - remote-endpoint = <&lcdif1_to_ldb>; - }; - }; - - port@1 { - reg = <1>; - - ldb_lvds_ch0: endpoint { - }; - }; - }; - }; - }; - - sdma: dma-controller@20ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>, - <&clks IMX6SX_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sx reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; - - aips2: bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: crypto@2100000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SX_CLK_CAAM_MEM>, - <&clks IMX6SX_CLK_CAAM_ACLK>, - <&clks IMX6SX_CLK_CAAM_IPG>, - <&clks IMX6SX_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@2184400 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc 2>; - phy_type = "hsic"; - fsl,anatop = <&anatop>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SX_CLK_USBOH3>; - }; - - fec1: ethernet@2188000 { - compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6SX_CLK_ENET>, - <&clks IMX6SX_CLK_ENET_AHB>, - <&clks IMX6SX_CLK_ENET_PTP>, - <&clks IMX6SX_CLK_ENET_REF>, - <&clks IMX6SX_CLK_ENET_PTP>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - fsl,stop-mode = <&gpr 0x10 3>; - status = "disabled"; - }; - - mlb: mlb@218c000 { - reg = <0x0218c000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6SX_CLK_MLB>; - status = "disabled"; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC1>, - <&clks IMX6SX_CLK_USDHC1>, - <&clks IMX6SX_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC2>, - <&clks IMX6SX_CLK_USDHC2>, - <&clks IMX6SX_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@2198000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC3>, - <&clks IMX6SX_CLK_USDHC3>, - <&clks IMX6SX_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: mmc@219c000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC4>, - <&clks IMX6SX_CLK_USDHC4>, - <&clks IMX6SX_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; - }; - - fec2: ethernet@21b4000 { - compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; - reg = <0x021b4000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6SX_CLK_ENET>, - <&clks IMX6SX_CLK_ENET_AHB>, - <&clks IMX6SX_CLK_ENET_PTP>, - <&clks IMX6SX_CLK_ENET2_REF_125M>, - <&clks IMX6SX_CLK_ENET_PTP>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,stop-mode = <&gpr 0x10 4>; - status = "disabled"; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_EIM_SLOW>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: efuse@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; - - sai1: sai@21d4000 { - compatible = "fsl,imx6sx-sai"; - reg = <0x021d4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SAI1_IPG>, - <&clks IMX6SX_CLK_SAI1>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; - status = "disabled"; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - sai2: sai@21dc000 { - compatible = "fsl,imx6sx-sai"; - reg = <0x021dc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SAI2_IPG>, - <&clks IMX6SX_CLK_SAI2>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; - status = "disabled"; - }; - - qspi1: spi@21e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6SX_CLK_QSPI1>, - <&clks IMX6SX_CLK_QSPI1>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - qspi2: spi@21e4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-qspi"; - reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6SX_CLK_QSPI2>, - <&clks IMX6SX_CLK_QSPI2>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - uart2: serial@21e8000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@21ec000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@21f0000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@21f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C4>; - status = "disabled"; - }; - }; - - aips3: bus@2200000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02200000 0x100000>; - ranges; - - spba-bus@2240000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02240000 0x40000>; - ranges; - - csi1: csi@2214000 { - reg = <0x02214000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; - status = "disabled"; - }; - - pxp: pxp@2218000 { - compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; - reg = <0x02218000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>; - clock-names = "axi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - - csi2: csi@221c000 { - reg = <0x0221c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_DCIC2>; - clock-names = "disp-axi", "csi_mclk", "dcic"; - status = "disabled"; - }; - - lcdif1: lcdif@2220000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02220000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - power-domains = <&pd_disp>; - status = "disabled"; - - ports { - port { - lcdif1_to_ldb: endpoint { - remote-endpoint = <&ldb_from_lcdif1>; - }; - }; - }; - }; - - lcdif2: lcdif@2224000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02224000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - - vadc: vadc@2228000 { - reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; - reg-names = "vadc-vafe", "vadc-vdec"; - clocks = <&clks IMX6SX_CLK_VADC>, - <&clks IMX6SX_CLK_CSI>; - clock-names = "vadc", "csi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - }; - - adc1: adc@2280000 { - compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; - reg = <0x02280000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - adc2: adc@2284000 { - compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; - reg = <0x02284000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - wdog3: watchdog@2288000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x02288000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - status = "disabled"; - }; - - ecspi5: spi@228c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x0228c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI5>, - <&clks IMX6SX_CLK_ECSPI5>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@22a0000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x022a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm5: pwm@22a4000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM5>, - <&clks IMX6SX_CLK_PWM5>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm6: pwm@22a8000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM6>, - <&clks IMX6SX_CLK_PWM6>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm7: pwm@22ac000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022ac000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM7>, - <&clks IMX6SX_CLK_PWM7>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - - pwm8: pwm@22b0000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022b0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM8>, - <&clks IMX6SX_CLK_PWM8>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - }; - }; - - pcie: pcie@8ffc000 { - compatible = "fsl,imx6sx-pcie"; - reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */ - <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SX_CLK_PCIE_AXI>, - <&clks IMX6SX_CLK_LVDS1_OUT>, - <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; - power-domains = <&pd_disp>, <&pd_pci>; - power-domain-names = "pcie", "pcie_phy"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts deleted file mode 100644 index 2438669f149a..000000000000 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6ul.dtsi" -#include "imx6ul-14x14-evk.dtsi" - -/ { - model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; -}; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi deleted file mode 100644 index 155515fe13fa..000000000000 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_peri_3v3: regulator-peri-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "VPERI_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; - /* - * If you want to want to make this dynamic please - * check schematics and test all affected peripherals: - * - * - sensors - * - ethernet phy - * - can - * - bluetooth - * - wm8960 audio codec - * - ov5640 camera - */ - regulator-always-on; - }; - - reg_can_3v3: regulator-can-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; - }; - - sound-wm8960 { - compatible = "fsl,imx-audio-wm8960"; - model = "wm8960-audio"; - audio-cpu = <&sai2>; - audio-codec = <&codec>; - audio-asrc = <&asrc>; - hp-det-gpio = <&gpio5 4 0>; - audio-routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT2", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "AMIC", - "RINPUT2", "AMIC", - "Mic Jack", "MICB", - "AMIC", "MICB"; - }; - - spi-4 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - status = "okay"; - sck-gpios = <&gpio5 11 0>; - mosi-gpios = <&gpio5 10 0>; - cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - }; - }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight_display>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8960@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8960"; - reg = <0x1a>; - wlf,shared-lrclk; - wlf,hp-cfg = <3 2 3>; - wlf,gpio-cfg = <1 3>; - clocks = <&clks IMX6UL_CLK_SAI2>; - clock-names = "mclk"; - }; - - camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_camera_clock>; - clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "xclk"; - powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; - - port { - ov5640_to_parallel: endpoint { - remote-endpoint = <¶llel_from_ov5640>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; -}; - -&csi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi1>; - status = "okay"; - - port { - parallel_from_ov5640: endpoint { - remote-endpoint = <&ov5640_to_parallel>; - bus-type = ; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <®_peri_3v3>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-supply = <®_peri_3v3>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-id0022.1560"; - reg = <2>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1560"; - reg = <1>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&gpio_spi { - eth0-phy-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "eth0-phy"; - }; - - eth1-phy-hog { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "eth1-phy"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - magnetometer@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - vdd-supply = <®_peri_3v3>; - vddio-supply = <®_peri_3v3>; - }; -}; - -&lcdif { - assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xfff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - broken-cd; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_camera_clock: cameraclockgrp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 - >; - }; - - pinctrl_csi1: csi1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 - MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 - MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 - MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 - MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 - MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 - MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 - MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 - MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 - MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 - MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* used for lcd reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 - >; - }; - - pinctrl_peri_3v3: peri3v3grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_sim2: sim2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 - MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 - MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 - MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 - MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 - >; - }; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 - MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts deleted file mode 100644 index 3792679c0c90..000000000000 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Digi International's ConnectCore6UL SBC Express board device tree source - * - * Copyright 2018 Digi International, Inc. - * - */ - -/dts-v1/; -#include -#include -#include "imx6ul.dtsi" -#include "imx6ul-ccimx6ulsom.dtsi" - -/ { - model = "Digi International ConnectCore 6UL SBC Express."; - compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", - "fsl,imx6ul"; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <&ext_3v3>; - status = "okay"; -}; - -&ecspi3 { - cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3_master>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - smsc,disable-energy-detect; - reg = <0>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - broken-cd; /* no carrier detect line (use polling) */ - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_ecspi3_master: ecspi3grp1 { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ - >; - }; - - pinctrl_ecspi3_slave: ecspi3grp2 { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - /* General purpose pinctrl */ - pinctrl_hog: hoggrp { - fsl,pins = < - /* GPIOs BANK 3 */ - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts deleted file mode 100644 index 3ec042bfccba..000000000000 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ /dev/null @@ -1,428 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Digi International's ConnectCore6UL SBC Pro board device tree source - * - * Copyright 2018 Digi International, Inc. - * - */ - -/dts-v1/; -#include -#include -#include "imx6ul.dtsi" -#include "imx6ul-ccimx6ulsom.dtsi" - -/ { - model = "Digi International ConnectCore 6UL SBC Pro."; - compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul"; - - lcd_backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm5 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel { - compatible = "auo,g101evn010"; - power-supply = <&ldo4_ext>; - backlight = <&lcd_backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <&ext_3v3>; - status = "okay"; -}; - -/* CAN2 is multiplexed with UART2 RTS/CTS */ -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <&ext_3v3>; - status = "disabled"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_master>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - phy-reset-duration = <26>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - smsc,disable-energy-detect; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - smsc,disable-energy-detect; - reg = <1>; - }; - }; -}; - -&gpio5 { - emmc-usd-mux-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-high; - }; -}; - -&i2c1 { - touchscreen@14 { - compatible = "goodix,gt911"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_goodix_touch>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat0_17 - &pinctrl_lcdif_clken - &pinctrl_lcdif_hvsync>; - lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */ - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&ldo4_ext { - regulator-max-microvolt = <1800000>; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&pwm5 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - status = "okay"; -}; - -&pwm6 { - status = "okay"; -}; - -&pwm7 { - status = "okay"; -}; - -&pwm8 { - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_sai2>; - pinctrl-1 = <&pinctrl_sai2_sleep>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-rates = <0>, <786432000>, <12288000>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - status = "okay"; -}; - -/* UART2 RTS/CTS muxed with CAN2 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_4wires>; - uart-has-rtscts; - status = "okay"; -}; - -/* UART3 RTS/CTS muxed with CAN 1 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_2wires>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* USDHC2 (microSD conflicts with eMMC) */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - broken-cd; /* no carrier detect line (use polling) */ - status = "okay"; -}; - -&iomuxc { - pinctrl_adc1: adc1grp { - fsl,pins = < - /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */ - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - >; - }; - - pinctrl_ecspi1_master: ecspi1grp1 { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0 - MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0 - MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0 - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051 - >; - }; - - pinctrl_enet2_mdio: mdioenet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - >; - }; - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - >; - }; - - pinctrl_goodix_touch: goodixgrp{ - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 - >; - }; - - pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_lcdif_clken: lcdifctrlgrp1 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - >; - }; - - pinctrl_lcdif_hvsync: lcdifctrlgrp2 { - fsl,pins = < - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 - >; - }; - - pinctrl_sai2_sleep: sai2grp-sleep { - fsl,pins = < - MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000 - MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000 - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000 - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000 - /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000 - >; - }; - - pinctrl_uart2_4wires: uart2grp-4wires { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3_2wires: uart3grp-2wires { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - /* Mux selector between eMMC/SD# */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059 - MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi deleted file mode 100644 index 7d1a391431bd..000000000000 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Digi International's ConnectCore 6UL System-On-Module device tree source - * - * Copyright 2018 Digi International, Inc. - * - */ - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; /* will be filled by U-Boot */ - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x4000000>; - linux,cma-default; - }; - }; -}; - -&adc1 { - vref-supply = <&vdda_adc_3v3>; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pfuze3000: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - int_3v3: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <6250>; - regulator-boot-on; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_arm_soc_in: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-ramp-delay = <6250>; - regulator-boot-on; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <925000>; - }; - }; - - ext_3v3: sw2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr3: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1300000>; - }; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - vdd_snvs_3v3: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vdda_adc_3v3: vldo1 { - compatible = "regulator-fixed"; - regulator-name = "vref-adc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo2_ext: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vdda_wlan: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_high_in: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_int: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4_ext: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vcoin_chg: coin { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -/* UART1 (Bluetooth) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -/* USDHC1 (Wireless) */ -&usdhc1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>; - pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>; - non-removable; - no-1-8-v; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmigrp { - fsl,pins = < - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_sleep: usdhc1grp-sleep { - fsl,pins = < - MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000 - MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000 - MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000 - MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000 - MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000 - MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000 - >; - }; - - pinctrl_wifibt_ctrl: wifibt-ctrl-grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0 - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0 - >; - }; - - pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000 - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000 - >; - }; -}; - -®_arm { - vin-supply = <&vdd_arm_soc_in>; - regulator-allow-bypass; -}; - -®_soc { - vin-supply = <&vdd_arm_soc_in>; - regulator-allow-bypass; -}; diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts deleted file mode 100644 index a0097da03f38..000000000000 --- a/arch/arm/boot/dts/imx6ul-geam.dts +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include -#include -#include "imx6ul.dtsi" - -/ { - model = "Engicam GEAM6UL Starter Kit"; - compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x08000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm8 0 100000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <100>; - }; - - chosen { - stdout-path = &uart1; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6ul-geam-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks IMX6UL_CLK_OSC>; - clock-names = "mclk"; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <28000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <30>; - hback-porch = <30>; - hsync-len = <64>; - vback-porch = <5>; - vfront-porch = <5>; - vsync-len = <20>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm8 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&tsc { - measure-delay-time = <0x1ffff>; - pre-charge-time = <0x1fff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pin = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 - MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi deleted file mode 100644 index f2386dcb9ff2..000000000000 --- a/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; /* will be filled by U-Boot */ - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - usdhc3_pwrseq: usdhc3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-reset-duration = <1>; - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - phy-handle = <ðphy1>; - phy-supply = <®_3v3>; - status = "okay"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - }; - }; -}; - -/* Bluetooth */ -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8>; - uart-has-rtscts; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -/* WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&usdhc3_pwrseq>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio2>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - /* INT# */ - MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 - /* RST# */ - MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_uart8: uart8grp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 - /* BT_REG_ON */ - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 - MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 - MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 - MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 - MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 - MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 - /* WL_REG_ON */ - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 - /* WL_IRQ */ - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi deleted file mode 100644 index 18cac19aa9b0..000000000000 --- a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -/ { - chosen { - stdout-path = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_5v>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-button { - label = "User button"; - gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - user-led { - label = "User"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_w1>; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; - - panel: panel { - compatible = "armadeus,st0700-adapt"; - power-supply = <®_3v3>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg1_vbus: regulator-usbotg1vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg1vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg2_vbus: regulator-usbotg2vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg2vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2_vbus>; - gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc1 { - vref-supply = <®_3v3>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_5v>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_5v>; - status = "okay"; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xffff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - vbus-supply = <®_usbotg1_vbus>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usbotg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0 - MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0 - MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0 - MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0 - MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0 - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0 - MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0 - MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0 - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0 - MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1 - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0 - >; - }; - - pinctrl_usbotg1_vbus: usbotg1vbusgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts deleted file mode 100644 index 1df3e376ae2c..000000000000 --- a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6ul-isiot.dtsi" - -/ { - model = "Engicam Is.IoT MX6UL eMMC Starter kit"; - compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; -}; - -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/imx6ul-isiot-nand.dts deleted file mode 100644 index 8c26d4d1a7bf..000000000000 --- a/arch/arm/boot/dts/imx6ul-isiot-nand.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6ul-isiot.dtsi" - -/ { - model = "Engicam Is.IoT MX6UL NAND Starter kit"; - compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; -}; - -&gpmi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi deleted file mode 100644 index 14fc4828ba4e..000000000000 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ /dev/null @@ -1,387 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -#include -#include -#include "imx6ul.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = &uart1; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm8 0 100000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <100>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6ul-isiot-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks IMX6UL_CLK_OSC>; - clock-names = "mclk"; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; - - stmpe811: gpio-expander@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - stmpe: touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <28000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <30>; - hback-porch = <30>; - hsync-len = <64>; - vback-porch = <5>; - vfront-porch = <5>; - vsync-len = <20>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm8 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - bus-width = <8>; - no-1-8-v; - status = "disabled"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 - MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts b/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts deleted file mode 100644 index 0c643706a158..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul-kontron-bl.dts" - -/ { - model = "Kontron BL i.MX6UL 43 (N631X S 43)"; - compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", - "kontron,sl-imx6ul", "fsl,imx6ul"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm7 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; -}; - -&i2c4 { - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cap_touch>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - /* Leave status disabled because of missing display panel node */ -}; - -&pwm7 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&iomuxc { - pinctrl_cap_touch: captouchgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi deleted file mode 100644 index 43868311f48a..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "debug-led1"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "debug-led2"; - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "debug-led3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_adc: regulator-vref-adc { - compatible = "regulator-fixed"; - regulator-name = "vref-adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - vref-supply = <®_vref_adc>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - eeprom@0 { - compatible = "anvo,anv32e61w", "atmel,at25"; - reg = <0>; - spi-max-frequency = <20000000>; - spi-cpha; - spi-cpol; - pagesize = <1>; - size = <8192>; - address-width = <16>; - }; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm8 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - rs485-rts-active-low; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 - >; - }; - - pinctrl_enet2_mdio: enet2mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 - /* - * mux unused RTS to make sure it doesn't cause - * any interrupts when it is undefined - */ - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl.dts b/arch/arm/boot/dts/imx6ul-kontron-bl.dts deleted file mode 100644 index dadf6d3d5f52..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-bl.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -/dts-v1/; - -#include "imx6ul-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6UL (N631X S)"; - compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi deleted file mode 100644 index dcf88f610346..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec2 { - phy-mode = "rmii"; - status = "disabled"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_out>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 - >; - }; - - pinctrl_enet1_mdio: enet1mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_reset_out: rstoutgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi b/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi deleted file mode 100644 index 0580d043e5ae..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6UL (N631X SOM)"; - compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts deleted file mode 100644 index 1d863a16bcf0..000000000000 --- a/arch/arm/boot/dts/imx6ul-liteboard.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2016 Grinn - * - * Author: Marcin Niestroj - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6ul-litesom.dtsi" - -/ { - model = "Grinn i.MX6UL liteBoard"; - compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom", - "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 8 GPIO_ACTIVE_LOW>; - }; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usb_otg1_vbus: usb-otg1-vbus { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79 - >; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi deleted file mode 100644 index 8d6893210842..000000000000 --- a/arch/arm/boot/dts/imx6ul-litesom.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2016 Grinn - * - * Author: Marcin Niestroj - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6ul.dtsi" - -/ { - model = "Grinn i.MX6UL liteSOM"; - compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 - >; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - bus-width = <8>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi deleted file mode 100644 index 6ce84f92b027..000000000000 --- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2017 Armadeus Systems - -#include "imx6ul.dtsi" -#include "imx6ul-imx6ull-opos6ul.dtsi" diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/imx6ul-opos6uldev.dts deleted file mode 100644 index 375b98d7205a..000000000000 --- a/arch/arm/boot/dts/imx6ul-opos6uldev.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2017 Armadeus Systems - -/dts-v1/; -#include "imx6ul-opos6ul.dtsi" -#include "imx6ul-imx6ull-opos6uldev.dtsi" - -/ { - model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board"; - compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>; - - pinctrl_tamper_gpios: tampergpiosgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 - >; - }; - - pinctrl_usbotg2_vbus: usbotg2vbusgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_w1: w1grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi deleted file mode 100644 index a3ea1b208462..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -#include -#include -#include - -/ { - model = "PHYTEC phyCORE-i.MX6 UltraLite"; - compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - /* - * Set the minimum memory size here and - * let the bootloader set the real size. - */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - gpio_leds_som: leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds_som>; - compatible = "gpio-leds"; - - led-phycore-green { - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - status = "disabled"; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <100000>; - status = "okay"; - - eeprom@52 { - compatible = "catalyst,24c32", "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "disabled"; -}; - -&wdog1 { - fsl,suspend-in-wait; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 - >; - }; - - pinctrl_gpioleds_som: gpioledssomgrp { - fsl,pins = ; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2cgrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c1_gpio: i2cgpiogrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; - -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts deleted file mode 100644 index cfc744f8fcad..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Yunus Bas - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-phytec-phycore-som.dtsi" -#include "imx6ul-phytec-segin.dtsi" -#include "imx6ul-phytec-segin-peb-eval-01.dtsi" -#include "imx6ul-phytec-segin-peb-av-02.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; - compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10", - "phytec,imx6ul-pcl063","fsl,imx6ul"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts deleted file mode 100644 index 607eddc5030f..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-phytec-phycore-som.dtsi" -#include "imx6ul-phytec-segin.dtsi" -#include "imx6ul-phytec-segin-peb-eval-01.dtsi" -#include "imx6ul-phytec-segin-peb-av-02.dtsi" -#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; - compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10", - "phytec,imx6ul-pcl063", "fsl,imx6ul"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi deleted file mode 100644 index ec042648bd98..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright (C) 2016, 2020 PHYTEC Messtechnik - * Author: Christian Hemp - * Author: Stefan Riedmueller - */ - -/ { - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <5>; - power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000 0>; - status = "disabled"; - }; - - lcd_panel: lcd-panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&backlight_lcd>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcdif_parallel_out>; - }; - }; - }; - - reg_backlight_en: regulator-backlight-en { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_en>; - regulator-name = "backlight-lcd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&i2c1 { - edt_ft5406: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5406>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - status = "disabled"; - }; - - stmpe: touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - wakeup-source; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat>; - status = "disabled"; - - port { - lcdif_parallel_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -&iomuxc { - pinctrl_edt_ft5406: edtft5406grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 - >; - }; - - pinctrl_backlight_en: bachlightengrp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59 - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi deleted file mode 100644 index 2f3fd32a1167..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik - * Author: Christian Hemp - */ - -#include - -/ { - gpio_keys: gpio-keys { - compatible = "gpio-key"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - status = "disabled"; - - power { - label = "Power Button"; - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - user_leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_leds>; - status = "disabled"; - - user-led1 { - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - - user-led2 { - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - }; -}; - -&iomuxc { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 - >; - }; - - pinctrl_user_leds: user_ledsgrp { - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi deleted file mode 100644 index 04477fd4b9a9..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 PHYTEC Messtechnik GmbH - * Author: Yunus Bas - */ - -#include -#include - -/ { - reg_wl_en: regulator-wl-en { - compatible = "regulator-fixed"; - regulator-name = "wlan_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wl>; - gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - status = "disabled"; - }; -}; - -&iomuxc { - pinctrl_bt: btgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */ - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */ - >; - }; - - pinctrl_uart2_bt: uart2grp-bt { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059 - MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059 - MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059 - >; - }; - - pinctrl_usdhc2_wl: usdhc2grp-wl { - fsl,pins = < - MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051 - MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061 - MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051 - MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051 - MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051 - MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051 - >; - }; - - pinctrl_wl: wlgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>; - uart-has-rtscts; - status = "disabled"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_wl>; - vmmc-supply = <®_wl_en>; - bus-width = <4>; - non-removable; - no-1-8-v; - status = "disabled"; - - brmcf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi deleted file mode 100644 index 38ea4dcfa228..000000000000 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite"; - compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &snvs_rtc; - }; - - reg_sound_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "i2s-audio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "disabled"; - }; - - reg_sound_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "i2s-audio-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "disabled"; - }; - - reg_can1_en: regulator-can1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&princtrl_flexcan1_en>; - regulator-name = "Can"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_adc1_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "Speaker", "SPOP", - "Speaker", "SPOM", - "LINE1L", "Line In", - "LINE1R", "Line In"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&tlv320>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; - -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - vref-supply = <®_adc1_vref_3v3>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_en>; - status = "disabled"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "disabled"; -}; - -&i2c1 { - tlv320: codec@18 { - compatible = "ti,tlv320aic3007"; - #sound-dai-cells = <0>; - reg = <0x18>; - AVDD-supply = <®_sound_3v3>; - IOVDD-supply = <®_sound_3v3>; - DRVDD-supply = <®_sound_3v3>; - DVDD-supply = <®_sound_1v8>; - status = "disabled"; - }; - - i2c_rtc: rtc@68 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - compatible = "microcrystal,rv4162"; - reg = <0x68>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; -}; - -&mdio { - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - status = "disabled"; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <19200000>; - fsl,sai-mclk-direction-output; - status = "disabled"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - status = "disabled"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - disable-wp; - status = "disabled"; -}; - -&iomuxc { - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 - >; - }; - - pinctrl_flexcan1: flexcan1 { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - princtrl_flexcan1_en: flexcan1engrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts deleted file mode 100644 index 5a74c7f68eb6..000000000000 --- a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul-pico.dtsi" -/ { - model = "TechNexion PICO-IMX6UL and DWARF baseboard"; - compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul"; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: audio-codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts deleted file mode 100644 index 09f7ffa9ad8c..000000000000 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul-pico.dtsi" -/ { - model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; - compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c3 { - status = "okay"; - - polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; - - adc081c: adc@50 { - compatible = "ti,adc081c"; - reg = <0x50>; - vref-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-pico-pi.dts b/arch/arm/boot/dts/imx6ul-pico-pi.dts deleted file mode 100644 index 6cd7d5877d20..000000000000 --- a/arch/arm/boot/dts/imx6ul-pico-pi.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul-pico.dtsi" -/ { - model = "TechNexion PICO-IMX6UL and PI baseboard"; - compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi deleted file mode 100644 index 4ffe99ed55ca..000000000000 --- a/arch/arm/boot/dts/imx6ul-pico.dtsi +++ /dev/null @@ -1,453 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul.dtsi" - -/ { - /* Will be filled by the bootloader */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - chosen { - stdout-path = &uart6; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 6 0>; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - panel { - compatible = "vxt,vl050-8048nt-c01"; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - max-speed = <100>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - /* VDD_ARM_SOC_IN*/ - sw1b_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* DRAM */ - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DRAM */ - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm3 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { /* Wifi SDIO */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ - MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 - MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* LCD reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 - MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 - MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 - MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h deleted file mode 100644 index 380d2db13a9b..000000000000 --- a/arch/arm/boot/dts/imx6ul-pinfunc.h +++ /dev/null @@ -1,959 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6UL_PINFUNC_H -#define __DTS_IMX6UL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 -#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 - -#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 - -#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 -#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 -#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 -#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 -#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 -#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 -#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 -#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 -#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 -#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 -#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 -#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 -#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 -#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 -#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 -#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 -#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 -#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 -#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 -#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 -#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 -#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 -#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 -#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 -#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 -#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 -#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 -#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 -#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 -#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 -#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 -#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 -#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 -#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 -#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 -#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 -#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 -#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 -#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 -#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 -#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 -#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 -#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 -#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 -#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 -#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 -#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 -#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 -#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 -#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 -#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 -#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 -#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 -#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 -#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 -#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 -#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 -#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 -#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 -#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 -#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 -#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 -#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 -#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 -#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 -#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 -#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 -#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 -#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 -#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 -#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 -#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 -#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 -#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 -#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 -#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 -#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 -#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 -#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 -#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 -#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 -#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 -#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 -#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 -#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 -#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 -#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 -#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 -#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 -#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 -#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 -#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 -#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 -#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 -#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 -#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 -#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 -#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 -#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 -#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 -#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 -#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 -#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 -#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 -#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 -#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 -#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 -#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 -#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 -#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 -#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 -#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 -#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 -#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 -#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 -#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 -#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 -#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 -#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 -#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 -#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 -#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 -#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 -#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 -#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 -#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 -#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 -#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 -#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 -#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 -#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 -#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 -#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 -#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 -#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 -#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 -#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 -#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 -#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 -#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 -#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 -#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 -#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 -#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 -#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 -#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 -#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 -#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 -#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 -#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 -#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 -#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 -#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 -#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 -#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 -#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 -#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 -#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 -#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 -#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 -#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 -#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 -#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 -#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 -#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 -#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 -#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 -#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 -#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 -#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 -#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 -#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 -#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 -#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 -#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 -#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 -#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 -#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 -#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 -#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 -#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 -#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 -#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 -#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 -#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 -#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 -#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 -#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 -#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 -#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 -#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 -#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 -#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 -#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 -#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 -#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 -#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 -#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 -#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 -#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 -#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 -#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 -#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 -#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 -#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 -#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 -#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 -#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 -#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 -#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 -#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 -#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 -#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 -#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 -#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 -#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 -#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 -#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 -#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 -#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 -#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 -#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 -#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 -#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 -#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 -#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 -#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 -#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 -#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 -#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 -#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 -#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 -#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 -#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 -#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 -#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 -#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 -#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 -#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 -#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 -#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 -#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 -#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 -#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 -#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 -#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 -#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 -#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 -#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 -#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 -#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 -#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 -#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 -#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 -#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 -#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 -#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 -#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 -#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 -#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 -#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 -#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 -#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 -#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 -#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 -#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 -#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 -#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 -#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 -#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 -#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 -#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 -#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 -#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 -#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 -#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 -#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 -#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 -#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 -#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 -#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 -#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 -#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 -#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 -#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 -#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 -#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 -#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 -#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 -#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 -#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 -#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 -#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 -#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 -#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 -#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 -#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 -#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 -#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 -#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 -#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 -#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 -#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 -#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 -#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 -#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 -#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 -#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 -#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 -#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 -#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 -#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 -#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 -#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 -#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 -#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 -#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 -#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 -#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 -#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 -#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 -#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 -#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 -#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 -#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 -#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 -#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 -#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 -#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 -#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 -#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 -#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 -#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 -#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 -#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 -#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 -#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 -#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 -#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 -#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 -#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 -#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 -#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 -#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 -#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 -#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 -#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 -#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 -#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 -#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 -#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 -#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 -#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 -#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 -#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 -#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 -#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 -#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 -#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 -#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 -#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 -#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 -#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 -#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 -#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 -#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 -#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 -#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 -#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 -#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 -#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 -#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 -#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 -#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 -#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 -#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 -#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 -#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 -#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 -#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 -#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 -#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 -#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 -#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 -#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 -#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 -#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 -#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 -#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 -#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 -#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 -#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 -#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 -#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 -#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 -#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 -#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 -#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 -#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 -#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 -#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 -#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 -#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 -#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 -#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 -#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 -#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 -#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 -#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 -#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 -#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 -#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 -#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 - -#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts deleted file mode 100644 index c3c50f51a5a8..000000000000 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ /dev/null @@ -1,353 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include - -/ { - model = "Protonic PRTI6G Board"; - compatible = "prt,prti6g", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - clock_ksz8081_in: clock-ksz8081-in { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - clock_ksz8081_out: clock-ksz8081-out { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet1_ref_pad"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v2: regulator-3v2 { - compatible = "regulator-fixed"; - regulator-name = "3v2"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad"; - assigned-clocks = <&clks IMX6UL_CLK_ENET1_REF_SEL>; - assigned-clock-parents = <&clock_ksz8081_out>; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth1>; - phy-mode = "rmii"; - phy-handle = <&rmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ8081RNA PHY */ - rmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - clocks = <&clock_ksz8081_in>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3v2>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - /* SR */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 - /* TERM */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - /* nSMBALERT */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 - /* SR */ - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0 - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0 - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0 - >; - }; - - pinctrl_eth1: eth1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000 - /* PHY ENET1_RST */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 - /* PHY ENET1_IRQ */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* HW revision detect */ - /* REV_ID0 */ - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 */ - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 - /* REV_ID2 */ - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 - /* BOARD_ID0 */ - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 - /* BOARD_ID1 */ - MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 - /* BOARD_ID2 */ - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 - /* BOARD_ID3 */ - MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 - /* Safety controller IO */ - /* WAKE_SC */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 - /* PROGRAM_SC */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 - MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 - /* SD1 CD */ - MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi deleted file mode 100644 index 57e647fc3237..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/* - * Common for - * - TQMa6ULx - * - TQMa6ULxL - * - TQMa6ULLx - * - TQMa6ULLxL - */ - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_recovery>; - scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pfuze3000: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - reg_sw1a: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-ramp-delay = <6250>; - /* not used */ - }; - - reg_sw1b_core: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - reg_sw2: sw2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sw3_ddr: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_swbst: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - /* not used */ - }; - - reg_snvs_3v0: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vccsd: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - }; - - reg_v33_3v3: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vldo1_3v3: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - /* not used */ - }; - - reg_vldo2: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - /* not used */ - }; - - reg_vldo3: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - /* not used */ - }; - - reg_vldo4: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - - jc42_1a: eeprom-temperature@1a { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x1a>; - }; - - m24c64_50: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - m24c02_52: eeprom@52 { - compatible = "nxp,se97b", "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - read-only; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - - /* - * PMIC & temperature sensor IRQ - * Both do currently not use IRQ - * potentially dangerous if used on baseboard - */ - pmic-int-hog { - gpio-hog; - gpios = <24 0>; - input; - }; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <33000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; -}; - -/* eMMC */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz" , "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - - bus-width = <8>; - disable-wp; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4_recovery: i2c4recoverygrp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 - MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 - >; - }; - - pinctrl_pmic: pmic { - fsl,pins = < - /* PMIC irq */ - MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts deleted file mode 100644 index f2a5f17f312e..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6ul-tqma6ul1.dtsi" -#include "mba6ulx.dtsi" - -/ { - model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; - compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; -}; - -/* - * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) - * and need to be disabled here again - */ -&can2 { - status = "disabled"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <0>; - }; - }; -}; - -&fec2 { - /delete-property/ phy-handle; - /delete-node/ mdio; -}; - -&iomuxc { - pinctrl_enet1_mdc: enet1mdcgrp { - fsl,pins = < - /* mdio */ - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi deleted file mode 100644 index 24192d012ef7..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -#include "imx6ul-tqma6ul2.dtsi" - -/ { - model = "TQ-Systems TQMa6UL1 SoM"; - compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; -}; - -/* - * There are no module specific differences compared to TQMa6UL2, - * only external interfaces differ - */ - -/* - * Devices not available on i.MX6ULG1 and should not be enabled on - * mainboard level (again) - */ -&can2 { - status = "disabled"; -}; - -&csi { - status = "disabled"; -}; - -&fec2 { - status = "disabled"; -}; - -&lcdif { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts deleted file mode 100644 index 0757df2b8f48..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6ul-tqma6ul2.dtsi" -#include "mba6ulx.dtsi" - -/ { - model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; - compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi deleted file mode 100644 index e2e95dd92263..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -#include "imx6ul.dtsi" -#include "imx6ul-tqma6ul-common.dtsi" -#include "imx6ul-tqma6ulx-common.dtsi" - -/ { - model = "TQ-Systems TQMa6UL2 SoM"; - compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; -}; - -&usdhc2 { - fsl,tuning-step = <6>; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts deleted file mode 100644 index 9d9b6b744a1c..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6ul-tqma6ul2l.dtsi" -#include "mba6ulx.dtsi" - -/ { - model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; - compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi deleted file mode 100644 index 4b87e2dc70dc..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -#include "imx6ul.dtsi" -#include "imx6ul-tqma6ul-common.dtsi" -#include "imx6ul-tqma6ulxl-common.dtsi" - -/ { - model = "TQ-Systems TQMa6UL2L SoM"; - compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; -}; - -&usdhc2 { - fsl,tuning-step = <6>; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi deleted file mode 100644 index 5afb9046c202..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/* - * Common for - * - TQMa6ULx - * - TQMa6ULLx - */ - -&m24c64_50 { - vcc-supply = <®_sw2>; -}; - -&m24c02_52 { - vcc-supply = <®_sw2>; -}; - -®_sw2 { - regulator-boot-on; - regulator-always-on; -}; - -/* eMMC */ -&usdhc2 { - vmmc-supply = <®_sw2>; - vqmmc-supply = <®_vldo4>; -}; - -&iomuxc { - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi deleted file mode 100644 index ba84a4f70ebd..000000000000 --- a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/* - * Common for - * - TQMa6ULxL - * - TQMa6ULLxL - */ - -/ { - reg_vin: reg-vin { - compatible = "regulator-fixed"; - regulator-name = "VIN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&m24c64_50 { - vcc-supply = <®_vin>; -}; - -&m24c02_52 { - vcc-supply = <®_vin>; -}; - -/* eMMC */ -&usdhc2 { - vmmc-supply = <®_vin>; - vqmmc-supply = <®_vldo4>; -}; - -&iomuxc { - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts b/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts deleted file mode 100644 index 8c2f3df79b47..000000000000 --- a/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0010 Module"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - /delete-property/ mmc1; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts b/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts deleted file mode 100644 index d82698e7d50f..000000000000 --- a/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0011 Module"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc1; - }; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - fsl,wp-controller; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts deleted file mode 100644 index 92ac0edcb608..000000000000 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - lcdif-24bit-pins-a = &pinctrl_disp0_3; - mmc0 = &usdhc1; - /delete-property/ mmc1; - serial2 = &uart3; - serial4 = &uart5; - }; - /delete-node/ sound; -}; - -&can1 { - xceiver-supply = <®_3v3>; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - status = "disabled"; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy0_int>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - etnphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy1_int>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - }; -}; - -&i2c_gpio { - status = "disabled"; -}; - -&i2c2 { - /delete-node/ codec@a; - /delete-node/ touchscreen@48; - - rtc: rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&kpp { - status = "disabled"; -}; - -&lcdif { - pinctrl-0 = <&pinctrl_disp0_3>; -}; - -®_usbotg_vbus{ - status = "disabled"; -}; - -&usdhc1 { - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - /delete-property/ cd-gpios; - cap-sdio-irq; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_uart1>; - /delete-property/ uart-has-rtscts; -}; - -&uart2 { - pinctrl-0 = <&pinctrl_uart2>; - /delete-property/ uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8>; - status = "disabled"; /* conflicts with LCDIF */ -}; - -&iomuxc { - hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */ - >; - }; - - pinctrl_disp0_3: disp0grp-3 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - /* LCD_DATA08..09 not wired */ - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - /* LCD_DATA16..17 not wired */ - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart8: uart8grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi deleted file mode 100644 index 6bd90473050b..000000000000 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ /dev/null @@ -1,947 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - aliases { - can0 = &can2; - can1 = &can1; - display = &display; - i2c0 = &i2c2; - i2c1 = &i2c_gpio; - i2c2 = &i2c1; - i2c3 = &i2c3; - i2c4 = &i2c4; - lcdif-23bit-pins-a = &pinctrl_disp0_1; - lcdif-24bit-pins-a = &pinctrl_disp0_2; - pwm0 = &pwm5; - reg-can-xcvr = ®_can_xcvr; - serial2 = &uart5; - serial4 = &uart3; - spi0 = &ecspi2; - spi1 = &spi_gpio; - stk5led = &user_led; - usbh1 = &usbotg2; - usbotg = &usbotg1; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; /* will be filled by U-Boot */ - }; - - clocks { - mclk: mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_rst>; - enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - i2c_gpio: i2c-gpio { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio>; - gpios = < - &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ - &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ - >; - clock-frequency = <400000>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - status = "disabled"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led: led-user { - label = "Heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3_etn: regulator-3v3etn { - compatible = "regulator-fixed"; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-canxcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; - }; - - reg_lcd_pwr: regulator-lcdpwr { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwr>; - gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi_gpio: spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_gpio>; - mosi-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - num-chipselects = <2>; - cs-gpios = < - &gpio1 29 GPIO_ACTIVE_HIGH - &gpio1 10 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - }; - - sound { - compatible = "karo,imx6ul-tx6ul-sgtl5000", - "simple-audio-card"; - simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = < - &gpio1 29 GPIO_ACTIVE_HIGH - &gpio1 10 GPIO_ACTIVE_HIGH - >; - status = "disabled"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy0_int>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - etnphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy1_int>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy1>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: polytouch@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: touchscreen@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_NONE>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0..3 are mapped to KPP row/col 4..7 */ - linux,keymap = < - MATRIX_KEY(4, 4, KEY_POWER) - MATRIX_KEY(4, 5, KEY_KP0) - MATRIX_KEY(4, 6, KEY_KP1) - MATRIX_KEY(4, 7, KEY_KP2) - MATRIX_KEY(5, 4, KEY_KP3) - MATRIX_KEY(5, 5, KEY_KP4) - MATRIX_KEY(5, 6, KEY_KP5) - MATRIX_KEY(5, 7, KEY_KP6) - MATRIX_KEY(6, 4, KEY_KP7) - MATRIX_KEY(6, 5, KEY_KP8) - MATRIX_KEY(6, 6, KEY_KP9) - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - lcd-supply = <®_lcd_pwr>; - display = <&display>; - status = "okay"; - - display: disp0 { - bits-per-pixel = <32>; - bus-width = <24>; - status = "okay"; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usbotg_vbus>; - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ - >; - }; - - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ - MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ - MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ - >; - }; - - pinctrl_etnphy0_int: etnphy-intgrp-0 { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy0_rst: etnphy-rstgrp-0 { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ - >; - }; - - pinctrl_etnphy1_int: etnphy-intgrp-1 { - fsl,pins = < - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy1_rst: etnphy-rstgrp-1 { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c_gpio: i2c-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 - >; - }; - - pinctrl_lcd_pwr: lcd-pwrgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ - >; - }; - - pinctrl_lcd_rst: lcd-rstgrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ - >; - }; - - pinctrl_spi_gpio: spi-gpiogrp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart1_rtscts: uart1-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 - MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart2_rtscts: uart2-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart5_rtscts: uart5-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_usbh1_oc: usbh1-ocgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ - >; - }; - - pinctrl_usbotg_oc: usbotg-ocgrp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 - >; - }; - - pinctrl_usdhc1_cd: usdhc1cdgrp { - fsl,pins = < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 - /* eMMC RESET */ - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi deleted file mode 100644 index 0174f3edbd16..000000000000 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ /dev/null @@ -1,1124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2015 Freescale Semiconductor, Inc. - -#include -#include -#include -#include -#include "imx6ul-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - sai1 = &sai1; - sai2 = &sai2; - sai3 = &sai3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usb0 = &usbotg1; - usb1 = &usbotg2; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <696000000>; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - operating-points = - /* kHz uV */ - <696000 1275000>, - <528000 1175000>, - <396000 1025000>, - <198000 950000>; - fsl,soc-operating-points = - /* KHz uV */ - <696000 1275000>, - <528000 1175000>, - <396000 1175000>, - <198000 1175000>; - clocks = <&clks IMX6UL_CLK_ARM>, - <&clks IMX6UL_CLK_PLL2_BUS>, - <&clks IMX6UL_CLK_PLL2_PFD2>, - <&clks IMX6UL_CA7_SECONDARY_SEL>, - <&clks IMX6UL_CLK_STEP>, - <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", - "secondary_sel", "step", "pll1_sw", - "pll1_sys"; - arm-supply = <®_arm>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - ckil: clock-cli { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gpc>; - interrupts = ; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x00a01000 0x1000>, - <0x00a02000 0x2000>, - <0x00a04000 0x2000>, - <0x00a06000 0x2000>; - }; - - dma_apbh: dma-controller@1804000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6UL_CLK_APBHDMA>; - }; - - gpmi: nand-controller@1806000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bch"; - clocks = <&clks IMX6UL_CLK_GPMI_IO>, - <&clks IMX6UL_CLK_GPMI_APB>, - <&clks IMX6UL_CLK_GPMI_BCH>, - <&clks IMX6UL_CLK_GPMI_BCH_APB>, - <&clks IMX6UL_CLK_PER_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI1>, - <&clks IMX6UL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI2>, - <&clks IMX6UL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI3>, - <&clks IMX6UL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI4>, - <&clks IMX6UL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart7: serial@2018000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02018000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART7_IPG>, - <&clks IMX6UL_CLK_UART7_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART1_IPG>, - <&clks IMX6UL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart8: serial@2024000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART8_IPG>, - <&clks IMX6UL_CLK_UART8_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai1: sai@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI1_IPG>, - <&clks IMX6UL_CLK_SAI1>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 35 24 0>, - <&sdma 36 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI2_IPG>, - <&clks IMX6UL_CLK_SAI2>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 37 24 0>, - <&sdma 38 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI3_IPG>, - <&clks IMX6UL_CLK_SAI3>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 39 24 0>, - <&sdma 40 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - asrc: asrc@2034000 { - compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; - reg = <0x2034000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ASRC_IPG>, - <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, - <&clks IMX6UL_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck_0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "spba"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; - status = "okay"; - }; - }; - - tsc: tsc@2040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - status = "disabled"; - }; - - pwm1: pwm@2080000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM1>, - <&clks IMX6UL_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@2084000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM2>, - <&clks IMX6UL_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@2088000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM3>, - <&clks IMX6UL_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@208c000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM4>, - <&clks IMX6UL_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - can1: can@2090000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN1_IPG>, - <&clks IMX6UL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1>; - status = "disabled"; - }; - - can2: can@2094000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN2_IPG>, - <&clks IMX6UL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2>; - status = "disabled"; - }; - - gpt1: timer@2098000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT1_BUS>, - <&clks IMX6UL_CLK_GPT1_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, - <&iomuxc 16 33 16>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 65 29>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; - }; - - fec2: ethernet@20b4000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x020b4000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET2_REF_SEL>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref"; - fsl,num-tx-queues = <1>; - fsl,num-rx-queues = <1>; - fsl,stop-mode = <&gpr 0x10 4>; - fsl,magic-packet; - status = "disabled"; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_KPP>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG1>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG2>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6ul-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - reg_3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2625000>; - regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - tempmon: tempmon { - compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY1>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY2>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6ul-snvs-lpgpr"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6ul-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&clks IMX6UL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - }; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6ul-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@20e4000 { - compatible = "fsl,imx6ul-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - gpt2: timer@20e8000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; - reg = <0x020e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT2_BUS>, - <&clks IMX6UL_CLK_GPT2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: dma-controller@20ec000 { - compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", - "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pwm5: pwm@20f0000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM5>, - <&clks IMX6UL_CLK_PWM5>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@20f4000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM6>, - <&clks IMX6UL_CLK_PWM6>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@20f8000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM7>, - <&clks IMX6UL_CLK_PWM7>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@20fc000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM8>, - <&clks IMX6UL_CLK_PWM8>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - aips2: bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: crypto@2140000 { - compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2140000 0x3c000>; - ranges = <0 0x2140000 0x3c000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, - <&clks IMX6UL_CLK_CAAM_MEM>; - clock-names = "ipg", "aclk", "mem"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - }; - - fec1: ethernet@2188000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET1_REF_SEL>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref"; - fsl,num-tx-queues = <1>; - fsl,num-rx-queues = <1>; - fsl,stop-mode = <&gpr 0x10 3>; - fsl,magic-packet; - status = "disabled"; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - adc1: adc@2198000 { - compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ADC1>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_EIM>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: efuse@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6ul-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6UL_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - csi: csi@21c4000 { - compatible = "fsl,imx6ul-csi"; - reg = <0x021c4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "mclk"; - status = "disabled"; - }; - - lcdif: lcdif@21c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; - reg = <0x021c8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, - <&clks IMX6UL_CLK_LCDIF_APB>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - pxp: pxp@21cc000 { - compatible = "fsl,imx6ul-pxp"; - reg = <0x021cc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PXP>; - clock-names = "axi"; - }; - - qspi: spi@21e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6UL_CLK_QSPI>, - <&clks IMX6UL_CLK_QSPI>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - wdog3: watchdog@21e4000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x021e4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG3>; - status = "disabled"; - }; - - uart2: serial@21e8000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART2_IPG>, - <&clks IMX6UL_CLK_UART2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@21ec000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART3_IPG>, - <&clks IMX6UL_CLK_UART3_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@21f0000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART4_IPG>, - <&clks IMX6UL_CLK_UART4_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART5_IPG>, - <&clks IMX6UL_CLK_UART5_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c4: i2c@21f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C4>; - status = "disabled"; - }; - - uart6: serial@21fc000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART6_IPG>, - <&clks IMX6UL_CLK_UART6_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts deleted file mode 100644 index 74aaa8a56a3d..000000000000 --- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2016 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6ull.dtsi" -#include "imx6ul-14x14-evk.dtsi" - -/ { - model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; - assigned-clock-rates = <320000000>; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts deleted file mode 100644 index 3e0897c3a296..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-aster.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-nonwifi.dtsi" -#include "imx6ull-colibri-aster.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster"; - compatible = "toradex,colibri-imx6ull-aster", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - /* Pin already used by atmel_mxt_ts touchscreen */ - status = "disabled"; -}; - -/* PWM */ -&pwm6 { - /* Pin already used by atmel_mxt_ts touchscreen */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi deleted file mode 100644 index de4dc7c1a03a..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&adc1 { - status = "okay"; -}; - -&ecspi1 { - status = "okay"; - - num-cs = <2>; - cs-gpios = < - &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */ - &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */ - >; -}; - -/* - * Following SODIMM Pins should not be accessed as GPIO on Aster board: - * 134 - AIN5_SCL (no connection) - * 127 - Voltage Level Translator OE# signal (IC11 and IC12) - * - * To configure GPIO to LED5, please disable FEC2 and uncomment the following: - * &iomuxc { - * pinctrl-names = "default"; - * pinctrl-0 = < - * &pinctrl_gpio1 - * &pinctrl_gpio2 - * &pinctrl_gpio3 - * &pinctrl_gpio4 - * &pinctrl_gpio6 - for non-WiFi modules only - * &pinctrl_gpio7 - * &pinctrl_gpio_aster - * >; - * - * pinctrl_gpio_aster: gpio-aster { - * fsl,pins = < - * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0 - * >; - * }; - * }; - */ - -&i2c1 { - status = "okay"; - - m41t0m6: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* PWM */ -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - status = "okay"; -}; - -/* PWM */ -&pwm6 { - status = "okay"; -}; - -/* PWM */ -&pwm7 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - disable-over-current; - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usdhc1 { - vmmc-supply = <®_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts deleted file mode 100644 index 919c0464d6cb..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-emmc-nonwifi.dtsi" -#include "imx6ull-colibri-aster.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster"; - compatible = "toradex,colibri-imx6ull-emmc-aster", - "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts deleted file mode 100644 index 61b93cb040c7..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2021 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-emmc-nonwifi.dtsi" -#include "imx6ull-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-emmc-eval", - "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts deleted file mode 100644 index b9060c2f7977..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-emmc-nonwifi.dtsi" -#include "imx6ull-colibri-iris-v2.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2"; - compatible = "toradex,colibri-imx6ull-iris-v2", - "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts deleted file mode 100644 index 0ab71f2f5daa..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-emmc-nonwifi.dtsi" -#include "imx6ull-colibri-iris.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris"; - compatible = "toradex,colibri-imx6ull-emmc-iris", - "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi deleted file mode 100644 index ea238525d5c0..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -#include "imx6ull-colibri.dtsi" - -/ { - aliases { - mmc0 = &usdhc2; /* eMMC */ - mmc1 = &usdhc1; /* MMC 4-bit slot */ - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&gpio1 { - gpio-line-names = "SODIMM_8", - "SODIMM_6", - "SODIMM_129", - "SODIMM_89", - "SODIMM_19", - "SODIMM_21", - "UNUSABLE_SODIMM_180", - "UNUSABLE_SODIMM_184", - "SODIMM_4", - "SODIMM_2", - "SODIMM_106", - "SODIMM_71", - "SODIMM_23", - "SODIMM_31", - "SODIMM_99", - "SODIMM_102", - "SODIMM_33", - "SODIMM_35", - "SODIMM_25", - "SODIMM_27", - "SODIMM_36", - "SODIMM_38", - "SODIMM_32", - "SODIMM_34", - "SODIMM_135", - "SODIMM_77", - "SODIMM_100", - "SODIMM_186", - "SODIMM_196", - "SODIMM_194"; -}; - -&gpio2 { - gpio-line-names = "SODIMM_55", - "SODIMM_63", - "SODIMM_178", - "SODIMM_188", - "SODIMM_73", - "SODIMM_30", - "SODIMM_67", - "SODIMM_104", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_190", - "SODIMM_47", - "SODIMM_192", - "SODIMM_49", - "SODIMM_51", - "SODIMM_53"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_56", - "SODIMM_44", - "SODIMM_68", - "SODIMM_82", - "", - "SODIMM_76", - "SODIMM_70", - "SODIMM_60", - "SODIMM_58", - "SODIMM_78", - "SODIMM_72", - "SODIMM_80", - "SODIMM_46", - "SODIMM_62", - "SODIMM_48", - "SODIMM_74", - "SODIMM_50", - "SODIMM_52", - "SODIMM_54", - "SODIMM_66", - "SODIMM_64", - "SODIMM_57", - "SODIMM_61", - "SODIMM_29", - "SODIMM_37", - "SODIMM_88", - "SODIMM_86", - "SODIMM_92", - "SODIMM_90"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_140", - "SODIMM_59", - "SODIMM_142", - "SODIMM_144", - "SODIMM_133", - "SODIMM_146", - "SODIMM_28", - "SODIMM_75", - "SODIMM_96", - "SODIMM_81", - "SODIMM_94", - "SODIMM_101", - "SODIMM_103", - "SODIMM_79", - "SODIMM_97", - "SODIMM_69", - "SODIMM_98", - "SODIMM_85", - "SODIMM_65"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_43", - "SODIMM_45", - "SODIMM_137", - "SODIMM_95", - "SODIMM_107", - "SODIMM_131", - "SODIMM_93", - "", - "SODIMM_138", - "", - "SODIMM_105", - "SODIMM_127"; -}; - -/* NAND */ -&gpmi { - status = "disabled"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7 - &pinctrl_gpmi_gpio>; -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; -}; - -/* eMMC */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2emmc>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; - bus-width = <8>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_module_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts deleted file mode 100644 index d6da984e518d..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-nonwifi.dtsi" -#include "imx6ull-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi deleted file mode 100644 index 692ef26fbab3..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* fixed crystal dedicated to mcp2515 */ - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&adc1 { - status = "okay"; -}; - -&ecspi1 { - status = "okay"; - - mcp2515: can@0 { - compatible = "microchip,mcp2515"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - status = "okay"; - }; -}; - -&i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - m41t0m6: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* PWM */ -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - status = "okay"; -}; - -/* PWM */ -&pwm6 { - status = "okay"; -}; - -/* PWM */ -&pwm7 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - disable-over-current; - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usdhc1 { - vmmc-supply = <®_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts deleted file mode 100644 index f6b31118be17..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-nonwifi.dtsi" -#include "imx6ull-colibri-iris-v2.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2"; - compatible = "toradex,colibri-imx6ull-iris-v2", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&gpio1 { - /* This turns the LVDS transceiver on */ - lvds-power-on-hog { - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ - line-name = "LVDS_POWER_ON"; - output-high; - }; -}; - -&gpio2 { - /* - * This switches the LVDS transceiver to the single-channel - * output mode. - */ - lvds-ch-mode-hog { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ - line-name = "LVDS_CH_MODE"; - output-high; - }; - - /* - * This switches the LVDS transceiver to the 24-bit RGB mode. - */ - lvds-rgb-mode-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ - line-name = "LVDS_RGB_MODE"; - output-low; - }; -}; - -&gpio5 { - /* - * This switches the LVDS transceiver to VESA color mapping mode. - */ - lvds-color-map-hog { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ - line-name = "LVDS_COLOR_MAP"; - output-low; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - /* Pin already used by atmel_mxt_ts touchscreen */ - status = "disabled"; -}; - -/* PWM */ -&pwm6 { - /* Pin already used by atmel_mxt_ts touchscreen */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi deleted file mode 100644 index 93649cad0cc0..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -#include "imx6ull-colibri-iris.dtsi" - -/ { - reg_3v3_vmmc: regulator-3v3-vmmc { - compatible = "regulator-fixed"; - regulator-name = "3v3_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - }; -}; - - -&usdhc1 { - cap-power-off-card; - vmmc-supply = <®_3v3_vmmc>; - /delete-property/ keep-power-in-suspend; - /delete-property/ no-1-8-v; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts deleted file mode 100644 index 2a0d0fc3b9d6..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-iris.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-nonwifi.dtsi" -#include "imx6ull-colibri-iris.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris"; - compatible = "toradex,colibri-imx6ull-iris", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi deleted file mode 100644 index f52f8b5ad8a6..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&adc1 { - status = "okay"; -}; - -&gpio1 { - /* - * uart25_tx_on turns the UART transceiver on. If one wants to turn the - * transceiver off, that property has to be deleted and the gpio handled - * in userspace. - * The same applies to uart1_tx_on. - */ - uart25_tx_on-hog { - gpio-hog; - gpios = <15 0>; - output-high; - }; -}; - -&gpio2 { - uart1_tx_on-hog { - gpio-hog; - gpios = <7 0>; - output-high; - }; -}; - -&i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - m41t0m6: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* PWM */ -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - status = "okay"; -}; - -/* PWM */ -&pwm6 { - status = "okay"; -}; - -/* PWM */ -&pwm7 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - disable-over-current; - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usdhc1 { - vmmc-supply = <®_3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi deleted file mode 100644 index 88901db255d6..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -#include "imx6ull-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&gpio1 { - gpio-line-names = "SODIMM_8", - "SODIMM_6", - "SODIMM_129", - "SODIMM_89", - "SODIMM_19", - "SODIMM_21", - "UNUSABLE_SODIMM_180", - "UNUSABLE_SODIMM_184", - "SODIMM_4", - "SODIMM_2", - "SODIMM_106", - "SODIMM_71", - "SODIMM_23", - "SODIMM_31", - "SODIMM_99", - "SODIMM_102", - "SODIMM_33", - "SODIMM_35", - "SODIMM_25", - "SODIMM_27", - "SODIMM_36", - "SODIMM_38", - "SODIMM_32", - "SODIMM_34", - "SODIMM_135", - "SODIMM_77", - "SODIMM_100", - "SODIMM_186", - "SODIMM_196", - "SODIMM_194"; -}; - -&gpio2 { - gpio-line-names = "SODIMM_55", - "SODIMM_63", - "SODIMM_178", - "SODIMM_188", - "SODIMM_73", - "SODIMM_30", - "SODIMM_67", - "SODIMM_104", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_190", - "SODIMM_47", - "SODIMM_192", - "SODIMM_49", - "SODIMM_51", - "SODIMM_53"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_56", - "SODIMM_44", - "SODIMM_68", - "SODIMM_82", - "", - "SODIMM_76", - "SODIMM_70", - "SODIMM_60", - "SODIMM_58", - "SODIMM_78", - "SODIMM_72", - "SODIMM_80", - "SODIMM_46", - "SODIMM_62", - "SODIMM_48", - "SODIMM_74", - "SODIMM_50", - "SODIMM_52", - "SODIMM_54", - "SODIMM_66", - "SODIMM_64", - "SODIMM_57", - "SODIMM_61", - "SODIMM_29", - "SODIMM_37", - "SODIMM_88", - "SODIMM_86", - "SODIMM_92", - "SODIMM_90"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_59", - "", - "", - "SODIMM_133", - "", - "SODIMM_28", - "SODIMM_75", - "SODIMM_96", - "SODIMM_81", - "SODIMM_94", - "SODIMM_101", - "SODIMM_103", - "SODIMM_79", - "SODIMM_97", - "SODIMM_69", - "SODIMM_98", - "SODIMM_85", - "SODIMM_65"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_43", - "SODIMM_45", - "SODIMM_137", - "SODIMM_95", - "SODIMM_107", - "SODIMM_131", - "SODIMM_93", - "", - "SODIMM_138", - "", - "SODIMM_105", - "SODIMM_127"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>; -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts deleted file mode 100644 index c7da5b41966f..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-wifi.dtsi" -#include "imx6ull-colibri-aster.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; - compatible = "toradex,colibri-imx6ull-wifi-aster", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - /* Pin already used by atmel_mxt_ts touchscreen */ - status = "disabled"; -}; - -/* PWM */ -&pwm6 { - /* Pin already used by atmel_mxt_ts touchscreen */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts deleted file mode 100644 index 917f5dbe64ba..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-wifi.dtsi" -#include "imx6ull-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts deleted file mode 100644 index 488da6df56fa..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-wifi.dtsi" -#include "imx6ull-colibri-iris-v2.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; - compatible = "toradex,colibri-imx6ull-wifi-iris-v2", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&gpio1 { - /* This turns the LVDS transceiver on */ - lvds-power-on-hog { - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ - line-name = "LVDS_POWER_ON"; - output-high; - }; -}; - -&gpio2 { - /* - * This switches the LVDS transceiver to the single-channel - * output mode. - */ - lvds-ch-mode-hog { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ - line-name = "LVDS_CH_MODE"; - output-high; - }; - - /* - * This switches the LVDS transceiver to the 24-bit RGB mode. - */ - lvds-rgb-mode-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ - line-name = "LVDS_RGB_MODE"; - output-low; - }; -}; - -&gpio5 { - /* - * This switches the LVDS transceiver to VESA color mapping mode. - */ - lvds-color-map-hog { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ - line-name = "LVDS_COLOR_MAP"; - output-low; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts deleted file mode 100644 index e63253254754..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -/dts-v1/; - -#include "imx6ull-colibri-wifi.dtsi" -#include "imx6ull-colibri-iris.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; - compatible = "toradex,colibri-imx6ull-wifi-iris", - "toradex,colibri-imx6ull", - "fsl,imx6ull"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi deleted file mode 100644 index db59ee6b1c86..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -#include "imx6ull-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - wifi_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_wifi_pdn>; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu0 { - clock-frequency = <792000000>; -}; - -&gpio1 { - gpio-line-names = "SODIMM_8", - "SODIMM_6", - "SODIMM_129", - "", - "SODIMM_19", - "SODIMM_21", - "UNUSABLE_SODIMM_180", - "UNUSABLE_SODIMM_184", - "SODIMM_4", - "SODIMM_2", - "SODIMM_106", - "SODIMM_71", - "SODIMM_23", - "SODIMM_31", - "SODIMM_99", - "SODIMM_102", - "SODIMM_33", - "SODIMM_35", - "SODIMM_25", - "SODIMM_27", - "SODIMM_36", - "SODIMM_38", - "SODIMM_32", - "SODIMM_34", - "SODIMM_135", - "SODIMM_77", - "SODIMM_100", - "SODIMM_186", - "SODIMM_196", - "SODIMM_194"; -}; - -&gpio2 { - gpio-line-names = "SODIMM_55", - "SODIMM_63", - "SODIMM_178", - "SODIMM_188", - "SODIMM_73", - "SODIMM_30", - "SODIMM_67", - "SODIMM_104", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_190", - "SODIMM_47", - "SODIMM_192", - "SODIMM_49", - "SODIMM_51", - "SODIMM_53"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_56", - "SODIMM_44", - "SODIMM_68", - "SODIMM_82", - "", - "SODIMM_76", - "SODIMM_70", - "SODIMM_60", - "SODIMM_58", - "SODIMM_78", - "SODIMM_72", - "SODIMM_80", - "SODIMM_46", - "SODIMM_62", - "SODIMM_48", - "SODIMM_74", - "SODIMM_50", - "SODIMM_52", - "SODIMM_54", - "SODIMM_66", - "SODIMM_64", - "SODIMM_57", - "SODIMM_61", - "SODIMM_29", - "SODIMM_37", - "SODIMM_88", - "SODIMM_86", - "SODIMM_92", - "SODIMM_90"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_59", - "", - "", - "SODIMM_133", - "", - "SODIMM_28", - "SODIMM_75", - "SODIMM_96", - "", - "", - "", - "", - "", - "", - "SODIMM_69", - "SODIMM_98", - "SODIMM_85", - "SODIMM_65"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_43", - "SODIMM_45", - "SODIMM_137", - "SODIMM_95", - "SODIMM_107", - "SODIMM_131", - "", - "", - "", - "", - "SODIMM_105"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio7>; - -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1>; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; - cap-power-off-card; - keep-power-in-suspend; - max-frequency = <25000000>; - mmc-pwrseq = <&wifi_pwrseq>; - no-1-8-v; - non-removable; - vmmc-supply = <®_module_3v3>; - wakeup-source; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi deleted file mode 100644 index fde8a19aac0f..000000000000 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ /dev/null @@ -1,773 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018-2022 Toradex - */ - -#include "imx6ull.dtsi" - -/ { - /* Ethernet aliases to ensure correct MAC addresses */ - aliases { - ethernet0 = &fec2; - ethernet1 = &fec1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - power-supply = <®_3v3>; - pwms = <&pwm4 0 5000000 1>; - status = "disabled"; - }; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_usbc_det>; - id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ - label = "USBC"; - self-powered; - type = "micro"; - - port { - usb_dr_connector: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - key-wakeup { - debounce-interval = <10>; - gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ - label = "Wake-Up"; - linux,code = ; - wakeup-source; - }; - }; - - panel_dpi: panel-dpi { - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sd1_vqmmc: regulator-sd1-vqmmc { - compatible = "regulator-gpio"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_reg_sd>; - regulator-always-on; - regulator-name = "+V3.3_1.8_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - states = <1800000 0x1 3300000 0x0>; - vin-supply = <®_module_3v3>; - }; - - reg_eth_phy: regulator-eth-phy { - compatible = "regulator-fixed-clock"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "+V3.3_ETH"; - regulator-type = "voltage"; - vin-supply = <®_module_3v3>; - clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; - startup-delay-us = <150000>; - }; -}; - -&adc1 { - vref-supply = <®_module_3v3_avdd>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -/* Colibri SPI */ -&ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; -}; - -/* Ethernet */ -&fec2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet2>; - pinctrl-1 = <&pinctrl_enet2_sleep>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-supply = <®_eth_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <2>; - }; - }; -}; - -/* NAND */ -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - fsl,use-minimum-ecc; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - status = "okay"; -}; - -/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - - /* Atmel maxtouch controller */ - atmel_mxt_ts: touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; - reg = <0x4a>; - interrupt-parent = <&gpio5>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ - status = "disabled"; - }; -}; - -/* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ -&i2c2 { - /* Use low frequency to compensate for the high pull-up values. */ - clock-frequency = <40000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - ad7879_ts: touchscreen@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - status = "disabled"; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "disabled"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; -}; - -/* PWM */ -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -/* PWM */ -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; -}; - -/* PWM */ -&pwm6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm6>; -}; - -/* PWM */ -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; -}; - -&sdma { - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -/* Colibri UART_A */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; - uart-has-rtscts; - fsl,dte-mode; -}; - -/* Colibri UART_B */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - fsl,dte-mode; -}; - -/* Colibri UART_C */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - fsl,dte-mode; -}; - -/* Colibri USBC */ -&usbotg1 { - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - usb-role-switch; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&usb_dr_connector>; - }; - }; -}; - -/* Colibri USBH */ -&usbotg2 { - dr_mode = "host"; -}; - -/* Colibri MMC/SD */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; - bus-width = <4>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ - disable-wp; - keep-power-in-suspend; - no-1-8-v; - vqmmc-supply = <®_sd1_vqmmc>; - wakeup-source; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ - >; - }; - - pinctrl_atmel_adap: atmeladapgrp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ - MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ - >; - }; - - pinctrl_atmel_conn: atmelconngrp { - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ - >; - }; - - pinctrl_can_int: canintgrp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - >; - }; - - pinctrl_enet2_sleep: enet2-sleepgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 - MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 - MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 - >; - }; - - pinctrl_ecspi1_cs: ecspi1csgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ - MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ - MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ - MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ - MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ - MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ - MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ - MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ - MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ - >; - }; - - pinctrl_gpio2: gpio2grp { /* Camera */ - fsl,pins = < - MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ - MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ - MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ - >; - }; - - pinctrl_gpio3: gpio3grp { /* CAN2 */ - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ - MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ - >; - }; - - pinctrl_gpio4: gpio4grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ - >; - }; - - pinctrl_gpio6: gpio6grp { /* Wifi pins */ - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ - MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ - MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ - >; - }; - - pinctrl_gpio7: gpio7grp { /* CAN1 */ - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ - MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ - >; - }; - - /* - * With an eMMC instead of a raw NAND device the following pins - * are available at SODIMM pins. - */ - pinctrl_gpmi_gpio: gpmigpiogrp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ - MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ - MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ - MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpiogrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2-gpiogrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ - >; - }; - - pinctrl_pwm6: pwm6grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ - MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ - MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ - MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ - >; - }; - - pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ - fsl,pins = < - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ - MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ - MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ - MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ - >; - }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ - MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ - >; - }; - - pinctrl_usbh_reg: usbhreggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 - - MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 - >; - }; - - pinctrl_usdhc2emmc: usdhc2emmcgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; - -&iomuxc_snvs { - pinctrl_atmel_snvs_conn: atmelsnvsconngrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ - >; - }; - - pinctrl_snvs_gpio1: snvsgpio1grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ - >; - }; - - pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ - fsl,pins = < - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ - >; - }; - - pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 - >; - }; - - pinctrl_snvs_reg_sd: snvsregsdgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 - >; - }; - - pinctrl_snvs_usbc_det: snvsusbcdetgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 - >; - }; - - pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ - >; - }; - - pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ - >; - }; - - pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 - >; - }; - - pinctrl_snvs_wifi_pdn: snvswifipdngrp { - fsl,pins = < - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts deleted file mode 100644 index b539975a872c..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2023 DH electronics GmbH - * - * DHCOM iMX6ULL variant: - * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 - * DHCOR PCB number: 578-200 or newer - * DHCOM PCB number: 579-200 or newer - * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM) - */ -/dts-v1/; - -#include "imx6ull-dhcom-som.dtsi" -#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" - -/ { - model = "DH electronics i.MX6ULL DHCOM on DRC02"; - compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som", - "dh,imx6ull-dhcor-som", "fsl,imx6ull"; -}; - -/* - * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. - * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1 - * node below. - */ -&can2 { - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "DRC02-In2", - "", "", "", "", - "", "", "DHCOM-I", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "DRC02-HW0", "DRC02-HW1", "DHCOM-M", - "DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S", - "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", - "DHCOM-N", "", "", ""; - /* - * NOTE: On DRC02, the RS485_RX_En is controlled by a separate - * GPIO line, however the i.MX6ULL UART driver assumes RX happens - * during TX anyway and that it only controls drive enable DE - * line. Hence, the RX is always enabled here. - */ - rs485-rx-en-hog { - gpio-hog; - gpios = <25 0>; /* GPIO Q */ - line-name = "rs485-rx-en"; - output-low; - }; -}; - -&gpio5 { - gpio-line-names = - "DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2", - "DHCOM-E", "", "", "DRC02-Out1", - "DRC02-In1", "DHCOM-H", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -/* DHCOM I2C2 */ -&i2c1 { - eeprom@56 { - compatible = "atmel,24c04"; - reg = <0x56>; - pagesize = <16>; - }; -}; - -&uart1 { - /delete-property/ uart-has-rtscts; - rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ - cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */ -}; - -/* Use UART as RS485 */ -&uart2 { - /delete-property/ uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */ -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts deleted file mode 100644 index b29713831a74..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2023 DH electronics GmbH - * - * DHCOM iMX6ULL variant: - * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-RTC-WBT-ADC-I-01D2 - * DHCOR PCB number: 578-200 or newer - * DHCOM PCB number: 579-200 or newer - * PDK2 PCB number: 516-400 or newer - */ -/dts-v1/; - -#include "imx6ull-dhcom-som.dtsi" - -/ { - model = "DH electronics i.MX6ULL DHCOM on Premium Developer Kit (2)"; - compatible = "dh,imx6ull-dhcom-pdk2", "dh,imx6ull-dhcom-som", - "dh,imx6ull-dhcor-som", "fsl,imx6ull"; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - display_bl: display-bl { - compatible = "pwm-backlight"; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* GPIO G */ - power-supply = <®_panel_3v3>; - pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-0 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* GPIO A */ - label = "TA1-GPIO-A"; - linux,code = ; - wakeup-source; - }; - - button-1 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; /* GPIO B */ - label = "TA2-GPIO-B"; - linux,code = ; - wakeup-source; - }; - - button-2 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ - label = "TA3-GPIO-C"; - linux,code = ; - wakeup-source; - }; - - button-3 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; /* GPIO D */ - label = "TA4-GPIO-D"; - linux,code = ; - wakeup-source; - }; - }; - - led: led { - compatible = "gpio-leds"; - - /* - * Disable PDK2 LED5, because GPIO E is - * already used as touch interrupt. - */ - led-0 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <5>; /* PDK2 LED5 */ - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; /* GPIO E */ - status = "disabled"; - }; - - led-1 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <6>; /* PDK2 LED6 */ - gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; /* GPIO F */ - }; - - /* - * Disable PDK2 LED7, because GPIO H is - * already used for WiFi pin WL_REG_ON. - */ - led-2 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <7>; /* PDK2 LED7 */ - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* GPIO H */ - status = "disabled"; - }; - - /* - * Disable PDK2 LED8, because GPIO I is - * already used for BT pin BT_REG_ON. - */ - led-3 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <8>; /* PDK2 LED8 */ - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ - status = "disabled"; - }; - }; - - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - power-supply = <®_panel_3v3>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - /* Filtered supply voltage */ - reg_pdk2_24v: regulator-pdk2-24v { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <24000000>; - regulator-min-microvolt = <24000000>; - regulator-name = "24V_PDK2"; - }; - - /* PDK2 U35 */ - reg_pdk2_3v3: regulator-pdk2-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "3V3_PDK2"; - vin-supply = <®_pdk2_24v>; - }; - - /* 560-200 U1 */ - reg_panel_3v3: regulator-panel-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "3V3_PANEL"; - vin-supply = <®_pdk2_24v>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "sgtl5000"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - clocks = <&clk_ext_audio_codec>; - sound-dai = <&sgtl5000>; - }; - }; -}; - -/* DHCOM I2C1 */ -&i2c2 { - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <®_pdk2_3v3>; - VDDIO-supply = <®_pdk2_3v3>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpio5>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - power-supply = <®_panel_3v3>; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts b/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts deleted file mode 100644 index e4cc2223583a..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2023 DH electronics GmbH - * - * DHCOM iMX6ULL variant: - * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 - * DHCOR PCB number: 578-200 or newer - * DHCOM PCB number: 579-200 or newer - * PicoITX PCB number: 487-600 or newer - */ -/dts-v1/; - -#include "imx6ull-dhcom-som.dtsi" -#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" - -/ { - model = "DH electronics i.MX6ULL DHCOM on PicoITX"; - compatible = "dh,imx6ull-dhcom-picoitx", "dh,imx6ull-dhcom-som", - "dh,imx6ull-dhcor-som", "fsl,imx6ull"; - - led { - compatible = "gpio-leds"; - - led-0 { - color = ; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ - }; - }; -}; - -&fec1 { - phy-handle = <&mdio1_phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - mdio1_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clock-names = "rmii-ref"; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; - pinctrl-names = "default"; - reset-assert-us = <500>; - reset-deassert-us = <500>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - smsc,disable-energy-detect; /* Make plugin detection reliable */ - }; - }; -}; - -&fec2 { - status = "disabled"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "PicoITX-HW2", "PicoITX-HW1", "DHCOM-M", - "PicoITX-HW0", "DHCOM-U", "DHCOM-T", "DHCOM-S", - "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", - "DHCOM-N", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2", - "PicoITX-In1", "", "", "PicoITX-Out1", - "DHCOM-G", "DHCOM-H", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&iomuxc { - pinctrl_fec1: fec1-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi deleted file mode 100644 index 040421f9c970..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2023 DH electronics GmbH - */ - -/* - * Special SoM configuration: SD card - * - * Enabled: Micro SD card on module or - * external SD card via DHCOM depends on hardware variant - * GPIO H and GPIO I will be available - * DHCOM UART2 will be available - * Disabled: WiFi and BT - */ - -/* - * To use usdhc1 as SD card, the WiFi node must be deleted. - * BT is also not available, so remove BT from the UART node. - */ -/delete-node/ &brcmf; -/delete-node/ &bluetooth; - -/ { - aliases { - mmc1 = &usdhc1; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; -}; - -/* Micro SD card on module or external SD card via DHCOM */ -&usdhc1 { - /delete-property/ #address-cells; - /delete-property/ #size-cells; - /delete-property/ keep-power-in-suspend; - /delete-property/ mmc-pwrseq; - /delete-property/ non-removable; - /delete-property/ wakeup-source; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc1: usdhc1-grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ - - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi deleted file mode 100644 index 830b5a5064f2..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi +++ /dev/null @@ -1,631 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2023 DH electronics GmbH - */ - -#include "imx6ull-dhcor-som.dtsi" - -/ { - aliases { - /delete-property/ spi2; - /delete-property/ spi3; - i2c0 = &i2c2; - i2c1 = &i2c1; - mmc2 = &usdhc2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - serial0 = &uart1; - serial1 = &uart6; /* DHCOM UART2, special hardware required */ - serial2 = &uart3; - serial3 = &uart2; /* Use BT UART always as ttymxc3 */ - serial4 = &uart4; - serial5 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_ext_3v3_ref: regulator-ext-3v3-ref { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VCC_3V3_REF"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb-otg1-vbus"; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb-otg2-vbus"; - }; - - /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */ - /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */ - }; -}; - -/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */ -&bluetooth { - shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ -}; - -&can1 { - pinctrl-0 = <&pinctrl_flexcan1>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* - * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. - * Only if this pins are used as CAN interface enable it on board layer. - */ -&can2 { - pinctrl-0 = <&pinctrl_flexcan2>; - pinctrl-names = "default"; -}; - -/* DHCOM SPI1 */ -&ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_ecspi1>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* - * DHCOM SPI2 - * Special hardware required that uses the pins of FEC2. Therefore this SPI - * interface can only be used if FEC2 is disabled. - */ -&ecspi4 { - cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_ecspi4>; - pinctrl-names = "default"; -}; - -/* DHCOM ETH1 */ -&fec1 { - phy-handle = <&mdio2_phy0>; - phy-mode = "rmii"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* DHCOM ETH2 */ -&fec2 { - phy-handle = <&mdio2_phy1>; - phy-mode = "rmii"; - pinctrl-0 = <&pinctrl_fec2>; - pinctrl-names = "default"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - mdio2_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clock-names = "rmii-ref"; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; - pinctrl-names = "default"; - reset-assert-us = <500>; - reset-deassert-us = <500>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - smsc,disable-energy-detect; /* Make plugin detection reliable */ - }; - - mdio2_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clock-names = "rmii-ref"; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>; - pinctrl-names = "default"; - reset-assert-us = <500>; - reset-deassert-us = <500>; - reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - smsc,disable-energy-detect; /* Make plugin detection reliable */ - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "DHCOM-INT", - "", "", "", "", - "", "", "DHCOM-I", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; - pinctrl-0 = <&pinctrl_spi1_switch - &pinctrl_dhcom_i &pinctrl_dhcom_int>; - pinctrl-names = "default"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "DHCOM-L", "DHCOM-K", "DHCOM-M", - "DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S", - "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", - "DHCOM-N", "", "", ""; - pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k - &pinctrl_dhcom_l &pinctrl_dhcom_m - &pinctrl_dhcom_n &pinctrl_dhcom_o - &pinctrl_dhcom_p &pinctrl_dhcom_q - &pinctrl_dhcom_r &pinctrl_dhcom_s - &pinctrl_dhcom_t &pinctrl_dhcom_u>; - pinctrl-names = "default"; -}; - -&gpio5 { - gpio-line-names = - "DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D", - "DHCOM-E", "", "", "DHCOM-F", - "DHCOM-G", "DHCOM-H", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; - pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b - &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d - &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f - &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>; - pinctrl-names = "default"; -}; - -/* DHCOM I2C2 */ -&i2c1 { - rtc_i2c: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - /* TI ADC101C027 */ - adc@51 { - compatible = "ti,adc101c"; - reg = <0x51>; - vref-supply = <®_ext_3v3_ref>; - }; - - /* TI ADC101C027 */ - adc@52 { - compatible = "ti,adc101c"; - reg = <0x52>; - vref-supply = <®_ext_3v3_ref>; - }; - - /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -/* DHCOM I2C1 */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - pinctrl-names = "default", "gpio"; - scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&lcdif { - pinctrl-0 = <&pinctrl_lcdif>; - pinctrl-names = "default"; -}; - -&pwm1 { - pinctrl-0 = <&pinctrl_pwm1>; - pinctrl-names = "default"; -}; - -&sai2 { - assigned-clock-rates = <320000000>; - assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; - pinctrl-0 = <&pinctrl_sai2>; - pinctrl-names = "default"; -}; - -&tsc { - measure-delay-time = <0xffff>; - pinctrl-0 = <&pinctrl_tsc>; - pinctrl-names = "default"; - pre-charge-time = <0xfff>; - touchscreen-average-samples = <32>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; -}; - -/* DHCOM UART1 */ -&uart1 { - pinctrl-0 = <&pinctrl_uart1>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* - * DHCOM UART2 (alternative) - * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2. - * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are - * removed from GPIO hog muxing. - */ -&uart6 { - pinctrl-0 = <&pinctrl_uart6>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&usbotg1 { - adp-disable; - disable-over-current; - dr_mode = "otg"; - hnp-disable; - pinctrl-0 = <&pinctrl_usbotg1>; - pinctrl-names = "default"; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; /* Overcurrent pin is used for TSC */ - dr_mode = "host"; - pinctrl-0 = <&pinctrl_usbotg2>; - pinctrl-names = "default"; - tpl-support; - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -/* WiFi on LGA */ -&usdhc1 { - mmc-pwrseq = <&usdhc1_pwrseq>; -}; - -/* eMMC on module */ -&usdhc2 { - bus-width = <8>; - no-1-8-v; - non-removable; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_3v3>; - status = "okay"; -}; - -&iomuxc { - /* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */ - pinctrl_dhcom_i: dhcom-i-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_j: dhcom-j-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_k: dhcom-k-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_l: dhcom-l-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_m: dhcom-m-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_n: dhcom-n-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_o: dhcom-o-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_p: dhcom-p-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_q: dhcom-q-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_r: dhcom-r-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_s: dhcom-s-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_t: dhcom-t-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_u: dhcom-u-grp { - fsl,pins = ; - }; - - pinctrl_dhcom_int: dhcom-int-grp { - fsl,pins = ; - }; - - pinctrl_ecspi1: ecspi1-grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 - MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */ - >; - }; - - pinctrl_ecspi4: ecspi4-grp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 - MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 - MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ - >; - }; - - pinctrl_fec1: fec1-grp { - fsl,pins = < - /* FEC1 uses MDIO bus from FEC2 */ - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 - >; - }; - - pinctrl_fec1_phy: fec1-phy-grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */ - >; - }; - - pinctrl_fec2: fec2-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 - >; - }; - - pinctrl_fec2_phy: fec2-phy-grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */ - >; - }; - - pinctrl_flexcan1: flexcan1-grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2-grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c2: i2c2-grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2-gpio-grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 - >; - }; - - pinctrl_lcdif: lcdif-grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_pwm1: pwm1-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_sai2: sai2-grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 - >; - }; - - pinctrl_tsc: tsc-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart6: uart6-grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 - MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 - MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg2: usbotg2-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 - >; - }; - - pinctrl_usdhc2: usdhc2-grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ - >; - }; -}; - -&iomuxc_snvs { - /* DHCOM GPIOs A..H */ - pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp { - fsl,pins = ; - }; - - pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp { - fsl,pins = ; - }; - - pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */ - >; - }; - - pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts b/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts deleted file mode 100644 index 047f7b2d8526..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2023 DH electronics GmbH - * Copyright (C) 2023 Marantec electronics GmbH - * - * DHCOM iMX6ULL variant: - * DHCR-iMX6ULL-C080-R051-SPI-WBT-I-01LG - * DHCOR PCB number: 578-200 or newer - * maveo box PCB number: 525-200 or newer - */ - -/dts-v1/; - -#include "imx6ull-dhcor-som.dtsi" - -/ { - model = "DH electronics i.MX6ULL DHCOR on maveo box"; - compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som", - "fsl,imx6ull"; - - aliases { - mmc2 = &usdhc2; - spi0 = &ecspi4; - spi3 = &ecspi1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb-otg1-vbus"; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb-otg2-vbus"; - }; - - /* WiFi pin WL_REG_ON is connected to GPIO 5.9 */ - usdhc1_pwrseq: usdhc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - }; -}; - -/* BT pin BT_REG_ON is connected to GPIO 1.18 */ -&bluetooth { - shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; -}; - -/* X10 connector */ -&ecspi4 { - cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_ecspi4>; - pinctrl-names = "default"; - status = "okay"; - - spidev@0 { - compatible = "dh,dhcom-board"; - reg = <0>; - spi-cpha; - spi-cpol; - spi-max-frequency = <54000000>; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "BUTTON-USER", "", "", - "BUTTON-RESET", "", "", "", - "", "", "", "", - "", "", "BT-REG-ON", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "PSOC-GPIO-1", "", "", "X10-12", - "X10-10", "PSOC-GPIO-2", "PSOC-GPIO-3", "", - "X10-11", "X10-9", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "DHCOR-HW0", "DHCOR-HW1", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "MAVEO-BOX-HW0", "LED-G", "MAVEO-BOX-VAR1", - "MAVEO-BOX-VAR0", "MAVEO-BOX-HW1", "MAVEO-BOX-HW2", "LED-B", - "LED-R", "", "", "", - "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "PSOC-SWD-IO", "PSOC-SWD-CLK", "PSOC-RESET", "ZIGBEE-PROG", - "ZIGBEE-RESET", "", "PSOC-PWR-FAIL-OUT", "NFC-ENABLE", - "NFC-IRQ", "WL-REG-ON", "DHCOR-BOOT-M0", "DHCOR-BOOT-M1", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - pinctrl-names = "default", "gpio"; - scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* Console UART */ -&uart1 { - pinctrl-0 = <&pinctrl_uart1>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* BT on LGA */ -&uart2 { - pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt_gpio>; -}; - -/* Zigbee UART */ -&uart3 { - pinctrl-0 = <&pinctrl_uart3 &pinctrl_snvs_zigbee_gpio>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg1 { - adp-disable; - disable-over-current; /* Overcurrent pin isn't connected */ - dr_mode = "otg"; - hnp-disable; - pinctrl-0 = <&pinctrl_usbotg1>; - pinctrl-names = "default"; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; /* Overcurrent pin isn't connected */ - dr_mode = "host"; - pinctrl-0 = <&pinctrl_usbotg2>; - pinctrl-names = "default"; - tpl-support; - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -/* WiFi on LGA */ -&usdhc1 { - mmc-pwrseq = <&usdhc1_pwrseq>; - pinctrl-0 = <&pinctrl_usdhc1_wifi &pinctrl_snvs_wifi_gpio>; -}; - -/* eMMC */ -&usdhc2 { - bus-width = <8>; - no-1-8-v; - non-removable; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_3v3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_hog_maveo_box>; - pinctrl-names = "default"; - - pinctrl_hog_maveo_box: hog-maveo-box-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 /* BUTTON_USER */ - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x120b0 /* BUTTON_RESET */ - MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0 /* LED_G */ - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0 /* LED_B */ - MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0 /* LED_R */ - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x400120b0 /* X10_9 */ - MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x400120b0 /* X10_10 */ - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x400120b0 /* X10_11 */ - MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x400120b0 /* X10_12 */ - MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x400120b0 /* PSOC_GPIO_1 */ - MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x400120b0 /* PSOC_GPIO_2 */ - MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x400120b0 /* PSOC_GPIO_3 */ - MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x120b0 /* MAVEO_BOX_HW0 */ - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x120b0 /* MAVEO_BOX_HW1 */ - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x120b0 /* MAVEO_BOX_HW2 */ - MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x120b0 /* MAVEO_BOX_VAR0 */ - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x120b0 /* MAVEO_BOX_VAR1 */ - MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x120b0 /* DHCOR_HW0 */ - MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x120b0 /* DHCOR_HW1 */ - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x120b0 - MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x120b0 - MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x120b0 - MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x120b0 - MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x120b0 - MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x120b0 - MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x120b0 - MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x120b0 - MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x120b0 - MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x120b0 - MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x120b0 - MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x120b0 - MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x120b0 - MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x120b0 - MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x120b0 - MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x120b0 - MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x120b0 - MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x120b0 - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x120b0 - >; - }; - - pinctrl_bt_gpio: bt-gpio-grp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0 /* BT_REG_ON */ - >; - }; - - pinctrl_ecspi4: ecspi4-grp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 - MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 - MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ - >; - }; - - pinctrl_i2c2: i2c2-grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2-gpio-grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3-grp { - fsl,pins = < - MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x120b0 /* USB_OTG1_PWR */ - >; - }; - - pinctrl_usbotg2: usbotg2-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x120b0 /* USB_OTG2_PWR */ - >; - }; - - pinctrl_usdhc2: usdhc2-grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ - >; - }; -}; - -&iomuxc_snvs { - pinctrl-0 = <&pinctrl_snvs_hog_maveo_box>; - pinctrl-names = "default"; - - pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0 /* PSOC_SWD_IO */ - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0 /* PSOC_SWD_CLK */ - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0 /* PSOC_RESET */ - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x400120b0 /* PSOC_PWR_FAIL_OUT */ - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0 /* NFC_ENABLE */ - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0 /* NFC_IRQ */ - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x120b0 /* DHCOR_BOOT_M0 */ - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x120b0 /* DHCOR_BOOT_M1 */ - >; - }; - - pinctrl_snvs_wifi_gpio: snvs-wifi-gpio-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0 /* WL_REG_ON */ - >; - }; - - pinctrl_snvs_zigbee_gpio: snvs-zigbee-gpio-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0 /* ZIGBEE_PROG */ - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0 /* ZIGBEE_RESET */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi deleted file mode 100644 index a386c1e9bed3..000000000000 --- a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2023 DH electronics GmbH - */ - -#include -#include -#include -#include -#include -#include "imx6ull.dtsi" - -/ { - aliases { - /delete-property/ mmc0; - /delete-property/ mmc1; - }; - - memory@80000000 { - /* Appropriate memory size will be filled by U-Boot */ - reg = <0x80000000 0>; - device_type = "memory"; - }; -}; - -&cpu0 { - /* - * Due to the design as a solderable SOM, there are no capacitors - * below the SoC, therefore higher voltages are required. - */ - operating-points = < - /* kHz uV */ - 900000 1275000 - 792000 1250000 /* Voltage increased */ - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 900000 1250000 - 792000 1250000 /* Voltage increased */ - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; -}; - -&gpio1 { - pinctrl-0 = <&pinctrl_spi1_switch>; - pinctrl-names = "default"; - /* - * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the - * DHCOM SPI1 interface or accessing the SPI bootflash. Both using - * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses - * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins - * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for - * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they - * are used for the bus interface to the SPI bootflash. The GPIOs are - * disconnected by a buffer which is also controlled via the pin - * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a - * special case and is disabled by setting GPIO 1.9 to high. - */ - spi1-switch-hog { - gpio-hog; - gpios = <9 0>; - output-high; - line-name = "spi1-switch"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - pinctrl-names = "default", "gpio"; - scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9061"; - reg = <0x58>; - - onkey { - compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; - status = "disabled"; - }; - - regulators { - vdd_soc_in_1v4: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1400000>; - regulator-min-microvolt = <1400000>; - regulator-name = "vdd_soc_in_1v4"; - }; - - vcc_3v3: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "vcc_3v3"; - }; - - /* - * The current DRR3 memory can be supplied with a - * voltage of either 1.35V or 1.5V. For reasons of - * backward compatibility to only 1.5V DDR3 memory, - * the voltage is set to 1.5V. - */ - vcc_ddr_1v35: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1500000>; - regulator-min-microvolt = <1500000>; - regulator-name = "vcc_ddr_1v35"; - }; - - vcc_2v5: ldo1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <2500000>; - regulator-name = "vcc_2v5"; - }; - - vdd_snvs_in_3v3: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "vdd_snvs_in_3v3"; - }; - - vcc_1v8: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - }; - - vcc_1v2: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1200000>; - regulator-min-microvolt = <1200000>; - regulator-name = "vcc_1v2"; - }; - }; - - thermal { - compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; - status = "disabled"; - }; - - watchdog { - compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog"; - status = "disabled"; - }; - }; -}; - -&ocotp { - /* Don't get write access by default */ - read-only; -}; - -®_arm { - vin-supply = <&vdd_soc_in_1v4>; -}; - -®_soc { - vin-supply = <&vdd_soc_in_1v4>; -}; - -/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */ -&uart2 { - pinctrl-0 = <&pinctrl_uart2>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; - - /* - * Actually, the maximum speed of the chip is 4MBdps, but there are - * limitations that prevent this speed. It hasn't yet been figured out - * what the reason for this is. Currently, the maximum speed of 3MBdps - * can be used without any problems. If the limitation can be overcome, - * the speed can be increased accordingly. - */ - bluetooth: bluetooth { - compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */ - max-speed = <3000000>; - vbat-supply = <&vcc_3v3>; - vddio-supply = <&vcc_3v3>; - }; -}; - -/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */ -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - pinctrl-0 = <&pinctrl_usdhc1_wifi>; - pinctrl-names = "default"; - wakeup-source; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */ - reg = <1>; - }; -}; - -&iomuxc { - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpio-grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 - >; - }; - - pinctrl_spi1_switch: spi1-switch-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */ - >; - }; - - pinctrl_uart2: uart2-grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1_wifi: usdhc1-wifi-grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-jozacp.dts b/arch/arm/boot/dts/imx6ull-jozacp.dts deleted file mode 100644 index a152eeb78e88..000000000000 --- a/arch/arm/boot/dts/imx6ull-jozacp.dts +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2020 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -/dts-v1/; - -#include -#include -#include "imx6ull.dtsi" - -/ { - model = "JOZ Access Point"; - compatible = "joz,jozacp", "fsl,imx6ull"; - - chosen { - stdout-path = &uart1; - }; - - /* On board name LED_RGB1 */ - led-controller-1 { - compatible = "pwm-leds"; - - led-0 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - pwms = <&pwm1 0 10000000 0>; - max-brightness = <255>; - }; - - led-1 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - pwms = <&pwm3 0 10000000 0>; - max-brightness = <255>; - }; - - led-2 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - pwms = <&pwm5 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* On board name LED_RGB2 */ - led-controller-2 { - compatible = "pwm-leds"; - - led-3 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - pwms = <&pwm2 0 10000000 0>; - max-brightness = <255>; - }; - - led-4 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <4>; - pwms = <&pwm4 0 10000000 0>; - max-brightness = <255>; - }; - - led-5 { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <5>; - pwms = <&pwm6 0 10000000 0>; - max-brightness = <255>; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_5v0>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vbus: regulator-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vbus>; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&cpu0 { - clock-frequency = <792000000>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - status = "okay"; -}; - -&pwm6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm6>; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - vbus-supply = <®_vbus>; - dr_mode = "host"; - over-current-active-low; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_3v3>; - bus-width = <8>; - no-1-8-v; - non-removable; - cap-mmc-hw-reset; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - mmc-pwrseq = <&usdhc2_wifi_pwrseq>; - bus-width = <4>; - no-1-8-v; - no-mmc; - no-sd; - non-removable; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0 - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* HW Revision */ - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 - - /* HW ID */ - MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 - - /* Digital inputs */ - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000 - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000 - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000 - - /* Isolated outputs */ - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020 - MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020 - MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020 - MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020 - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1 - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1 - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010 - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010 - >; - }; - - pinctrl_pwm6: pwm6grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 - MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 - MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0 - MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0 - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_vbus: vbus0grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0 - >; - }; - - pinctrl_wifi_npd: wifigrp { - fsl,pins = < - /* WL_REG_ON */ - MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020 - >; - }; -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_hog>; - - pinctrl_snvs_hog: snvs-hog-grp { - fsl,pins = < - /* Digital outputs */ - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020 - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020 - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020 - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020 - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020 - - /* Digital outputs fault feedback */ - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000 - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000 - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000 - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000 - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-bl.dts b/arch/arm/boot/dts/imx6ull-kontron-bl.dts deleted file mode 100644 index fa016465cdbc..000000000000 --- a/arch/arm/boot/dts/imx6ull-kontron-bl.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6ULL (N641X S)"; - compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi b/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi deleted file mode 100644 index 93f10eb3494f..000000000000 --- a/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6ULL (N641X SOM)"; - compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts deleted file mode 100644 index 79cc45728cd2..000000000000 --- a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Linumiz - * Author: Parthiban Nallathambi - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-myir-mys-6ulx.dtsi" - -/ { - model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; - compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull"; -}; - -&gpmi { - fsl,use-minimum-ecc; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi deleted file mode 100644 index d03694feaf5c..000000000000 --- a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Linumiz - * Author: Parthiban Nallathambi - */ - -#include -#include -#include - -/ { - model = "MYiR MYS-6ULX Single Board Computer"; - compatible = "fsl,imx6ull"; - - chosen { - stdout-path = &uart1; - }; - - reg_vdd_5v: regulator-vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_vdd_3v3: regulator-vdd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vdd_5v>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <®_vdd_3v3>; - status = "okay"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_vdd_3v3>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - non-removable; - keep-power-in-suspend; - vmmc-supply = <®_vdd_3v3>; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/imx6ull-opos6ul.dtsi deleted file mode 100644 index 155f941f2811..000000000000 --- a/arch/arm/boot/dts/imx6ull-opos6ul.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -#include "imx6ull.dtsi" -#include "imx6ul-imx6ull-opos6ul.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/imx6ull-opos6uldev.dts deleted file mode 100644 index 198fdb72641b..000000000000 --- a/arch/arm/boot/dts/imx6ull-opos6uldev.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -/dts-v1/; -#include "imx6ull-opos6ul.dtsi" -#include "imx6ul-imx6ull-opos6uldev.dtsi" - -/ { - model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board"; - compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull"; -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tamper_gpios>; - - pinctrl_tamper_gpios: tampergpiosgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 - >; - }; - - pinctrl_usbotg2_vbus: usbotg2vbusgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_w1: w1grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi deleted file mode 100644 index 56cd16e5a77f..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-phycore-som.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX6 ULL"; - compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -&iomuxc { - /delete-node/ gpioledssomgrp; -}; - -&iomuxc_snvs { - pinctrl_gpioleds_som: gpioledssomgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts deleted file mode 100644 index 8e2a4c5d7765..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" -#include "imx6ull-phytec-segin.dtsi" -#include "imx6ull-phytec-segin-peb-eval-01.dtsi" -#include "imx6ull-phytec-segin-peb-av-02.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; - compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10", - "phytec,imx6ull-pcl063","fsl,imx6ull"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts deleted file mode 100644 index 1d7362b5ac91..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" -#include "imx6ull-phytec-segin.dtsi" -#include "imx6ull-phytec-segin-peb-eval-01.dtsi" -#include "imx6ull-phytec-segin-peb-av-02.dtsi" -#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; - compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts deleted file mode 100644 index 4bcbae024d8d..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" -#include "imx6ull-phytec-segin.dtsi" -#include "imx6ull-phytec-segin-peb-eval-01.dtsi" -#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; - compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -&adc1 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi deleted file mode 100644 index 06bb7f327780..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-segin-peb-av-02.dtsi" - -&iomuxc { - /delete-node/ edtft5406grp; - /delete-node/ stmpegrp; -}; - -&iomuxc_snvs { - pinctrl_edt_ft5406: edtft5406grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi deleted file mode 100644 index ff08d95a1aa2..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-segin-peb-eval-01.dtsi" - -&iomuxc { - /delete-node/ gpio_keysgrp; -}; - -&iomuxc_snvs { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi deleted file mode 100644 index df25814a3371..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 PHYTEC Messtechnik GmbH - * Author: Yunus Bas - */ - -#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" - -&iomuxc { - /delete-node/ wlgrp; -}; - -&iomuxc_snvs { - pinctrl_wl: wlgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi deleted file mode 100644 index e287a0453b5f..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-segin.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL"; - compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull"; -}; - -&iomuxc { - /delete-node/ flexcan1engrp; - /delete-node/ rtcintgrp; -}; - -&iomuxc_snvs { - princtrl_flexcan1_en: flexcan1engrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts deleted file mode 100644 index 14adb87da911..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 PHYTEC Messtechnik GmbH - * Author: Alexander Bauer - */ - -/dts-v1/; -#include "imx6ull-phytec-tauri.dtsi" - -/ { - model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; - compatible = "phytec,imx6ull-phygate-tauri", - "phytec,imx6ull-phygate-tauri-emmc", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -/* EMMC-Version */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts deleted file mode 100644 index ae396ac63443..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 PHYTEC Messtechnik GmbH - * Author: Alexander Bauer - */ - -/dts-v1/; -#include "imx6ull-phytec-tauri.dtsi" - -/ { - model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; - compatible = "phytec,imx6ull-phygate-tauri", - "phytec,imx6ull-phygate-tauri-nand", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -/* NAND-Version */ -&gpmi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi deleted file mode 100644 index ea627638e40c..000000000000 --- a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 PHYTEC Messtechnik GmbH - * Author: Alexander Bauer - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" - -/ { - - model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; - compatible = "phytec,imx6ull-phygate-tauri", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &snvs_rtc; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-key"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key { - label = "KEY-A"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - reg_adc1_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_s25fl064_hold: regulator-s25fl064-hold { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_s25fl064_hold>; - compatible = "regulator-fixed"; - regulator-name = "s25fl064_hold"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usb_hub_vbus: regulator-hub-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhubpwr>; - compatible = "regulator-fixed"; - regulator-name = "usb_hub_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwr>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - user_leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_leds>, - <&pinctrl_user_leds_snvs>; - - user-led1 { - label = "yellow"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "off"; - }; - - user-led2 { - label = "red"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "off"; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>, - <&pinctrl_ecspi1_cs>; - cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, - <&gpio3 10 GPIO_ACTIVE_LOW>, - <&gpio3 11 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm_tis: tpm@1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm>; - compatible = "tcg,tpm_tis-spi"; - reg = <1>; - spi-max-frequency = <20000000>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - }; - - s25fl064: flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = " jedec,spi-nor"; - reg = <2>; - spi-max-frequency = <40000000>; - m25p,fast-read; - status = "disabled"; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - dmas = <&sdma 7 8 0>, - <&sdma 8 8 0>; - dma-names = "rx", "tx"; - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp102: tmp@49 { - compatible = "ti,tmp102"; - reg = <0x49>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; - interrupt-parent = <&gpio5>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - i2c_rtc: rtc@68 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - compatible = "microcrystal,rv4162"; - reg = <0x68>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&mdio { - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - status = "okay"; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm6>; - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* UART4 * RS485 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -/* UART5 * RS232 */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - vbus-supply = <®_usb_otg1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_hub_vbus>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc2 { - status = "disabled"; -}; - -&iomuxc_snvs { - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 - >; - }; - - pinctrl_tpm: tpmgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 - >; - }; - - pinctrl_usbhubpwr: usbhubpwrgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 - >; - }; - - pinctrl_user_leds_snvs: user_ledsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; -}; - -&iomuxc { - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ - MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 - MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 - >; - }; - - pinctrl_ecspi1_cs: ecspi1csgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 - MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 - MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 - >; - }; - - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 - >; - }; - - princtrl_flexcan2_en: flexcan2engrp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 - MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 - MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 - MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 - >; - }; - - pinctrl_pwm6: pwm6grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 - >; - }; - - pinctrl_s25fl064_hold: s25fl064holdgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 - MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 - MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 - >; - }; - - pinctrl_usbotg1pwr: usbotg1pwrgrp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_user_leds: userledsgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h deleted file mode 100644 index 54cfe72295aa..000000000000 --- a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright (C) 2017 NXP - */ - -#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H -#define __DTS_IMX6ULL_PINFUNC_SNVS_H -/* - * The pin function ID is a tuple of - * - */ -#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 -#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 - -#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h deleted file mode 100644 index 7328d4ef8559..000000000000 --- a/arch/arm/boot/dts/imx6ull-pinfunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6ULL_PINFUNC_H -#define __DTS_IMX6ULL_PINFUNC_H - -#include "imx6ul-pinfunc.h" -/* - * The pin function ID is a tuple of - * - */ -/* signals common for i.MX6UL and i.MX6ULL */ -#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 -#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 -#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 -#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 -#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 - -/* signals for i.MX6ULL only */ -#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 -#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 -#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 -#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 -#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0 - -#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi deleted file mode 100644 index 3fdece5bd31f..000000000000 --- a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi +++ /dev/null @@ -1,852 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright (C) 2023 chargebyte GmbH - -/dts-v1/; - -#include -#include -#include -#include "imx6ull.dtsi" - -/ { - aliases { - mmc0 = &usdhc2; /* eMMC */ - }; - - chosen { - stdout-path = &uart4; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&pinctrl_emmc_rst>; - pinctrl-names = "default"; - reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - }; - - reg_dcdc_3v3: regulator-dcdc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "dcdc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "ldo-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_status_leds>; - - led-1 { - function = LED_FUNCTION_BOOT; - color = ; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - - led-2 { - function = LED_FUNCTION_PROGRAMMING; - color = ; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_motor - &pinctrl_adc_cp - &pinctrl_adc_pp>; - vref-supply = <&vgen1_reg>; - status = "okay"; -}; - -&cpu0 { - clock-frequency = <792000000>; -}; - -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - num-cs = <3>; - cs-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH - &gpio3 2 GPIO_ACTIVE_HIGH - &gpio3 4 GPIO_ACTIVE_HIGH>; -}; - -&ecspi4 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - num-cs = <1>; - cs-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 - &pinctrl_enet1_phy_rst - &pinctrl_enet_mdio>; - phy-supply = <®_dcdc_3v3>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1_phy_int>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - max-speed = <100>; - smsc,disable-energy-detect; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", /* 0 */ - "", - "", - "", - "", - "", /* 5 */ - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "CP_INVERT", - "", - "", /* 15 */ - "", - "", - "", - "MOTOR_1_FAULT_N", - "", /* 20 */ - "", - "ROTARY_SWITCH_1_2_N", - "ROTARY_SWITCH_1_4_N", - "ROTARY_SWITCH_1_8_N", - "MOTOR_2_FAULT_N"; /* 25 */ -}; - -&gpio3 { - gpio-line-names = "", /* 0 */ - "", - "", - "", - "", - "", /* 5 */ - "EXT_GPIO", - "MOTOR_1_DRIVER_IN1_N", - "MOTOR_1_DRIVER_IN2", - "MOTOR_2_DRIVER_IN1", - "STM32_BOOT0", /* 10 */ - "STM32_RST_N", - "RELAY_1_ENABLE", - "RELAY_2_ENABLE", - "", - "", /* 15 */ - "QCA700X_MAINS_BOOTLOADER_N", - "QCA700X_CP_RST_N", - "QCA700X_CP_BOOTLOADER_N", - "", - "DIGITAL_OUT_1", /* 20 */ - "DIGITAL_OUT_2", - "DIGITAL_OUT_3", - "DIGITAL_OUT_4", - "DIGITAL_OUT_5", - "DIGITAL_OUT_6", /* 25 */ - "ROTARY_SWITCH_2_8_N", - "ROTARY_SWITCH_2_4_N", - "ROTARY_SWITCH_2_2_N"; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - - gpio-line-names = "", /* 0 */ - "", - "", - "", - "", - "", /* 5 */ - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "BOARD_VARIANT_1", - "BOARD_VARIANT_2", - "BOARD_VARIANT_0", /* 15 */ - "BOARD_VARIANT_3", - "", - "ROTARY_SWITCH_2_1_N", - "", - "DIGITAL_IN_5", /* 20 */ - "", - "", - "DIGITAL_IN_6", - "", - "DIGITAL_IN_1", /* 25 */ - "DIGITAL_IN_2", - "DIGITAL_IN_4", - "DIGITAL_IN_3"; - - pmic-int-hog { - gpio-hog; - gpios = <19 0>; - input; - }; -}; - -&gpio5 { - gpio-line-names = "ROTARY_SWITCH_1_1_N", /* 0 */ - "", - "RELAY_2_SENSE", - "RELAY_1_SENSE", - "", - "", /* 5 */ - "", - "QCA700X_MAINS_RST_N", - "MOTOR_2_DRIVER_IN2", - "", - "CP_POSITIVE_PEAK_RST", /* 10 */ - "CP_NEGATIVE_PEAK_RST"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pfuze3001: pmic@8 { - compatible = "fsl,pfuze3001"; - reg = <0x08>; - - regulators { - sw1_reg: sw1 { - regulator-name = "SW1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-name = "SW2"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-name = "SW3"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-name = "VSNVS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-name = "VLDO1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-name = "VLDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-name = "VCCSD"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-name = "V33"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-name = "VLDO3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-name = "VLDO4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - onewire@18 { - compatible = "maxim,ds2484"; - reg = <0x18>; - }; - - accelerometer@19 { - compatible = "st,iis328dq", "st,h3lis331dl-accel"; - reg = <0x19>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accelerometer_int1_snvs>; - vdd-supply = <®_dcdc_3v3>; - vddio-supply = <®_dcdc_3v3>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_board_var - &pinctrl_digital_input - &pinctrl_digital_output - &pinctrl_gpio_motor - &pinctrl_hog_pins - &pinctrl_rotary_switch1 - &pinctrl_rotary_switch2>; - - pinctrl_adc_cp: adc-cpgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - >; - }; - - pinctrl_adc_motor: adc-motorgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_adc_pp: adc-ppgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0 - >; - }; - - pinctrl_board_var: board-vargrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__GPIO4_IO15 0xb0 - MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0xb0 - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0xb0 - MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0 - >; - }; - - pinctrl_digital_input: digital-inputgrp { - fsl,pins = < - MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0xb0 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0xb0 - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0xb0 - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0xb0 - MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0xb0 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0xb0 - >; - }; - - pinctrl_digital_output: digital-outputgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400000b0 - MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400000b0 - MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400000b0 - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400000b0 - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400000b0 - MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400000b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 - MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0xb0 - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xb0 - MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x10b0 - MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x10b0 - MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x10b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0 - MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0 - MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0 - MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0 - >; - }; - - pinctrl_emmc_rst: emmc-rstgrp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x400010b0 - >; - }; - - pinctrl_enet_mdio: enet-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10b0 - >; - }; - - pinctrl_enet1_phy_int: enet1-phy-intgrp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x100b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x100b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0xb0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0xb0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0xb0 - >; - }; - - pinctrl_ext_uart: ext-uartgrp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0xb0 - MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0xb0 - >; - }; - - pinctrl_fan_enable: fan-enablegrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400000b0 - >; - }; - - pinctrl_gpio_motor: gpio-motorgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400000b0 - MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400000b0 - MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400000b0 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0xb0 - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0xb0 - >; - }; - - pinctrl_hog_pins: hog-pinsgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400000b0 - MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400000b0 - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x400070a0 - MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400000b0 - MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400000b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x400008b0 - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x400008b0 - >; - }; - - pinctrl_i2c4_gpio: i2c4-gpiogrp { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400008b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400008b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x70b1 - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0xb0 - >; - }; - - pinctrl_pwm_cp: pinctrl-pwm-cpgrp { - fsl,pins = < - MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x60a0 - >; - }; - - pinctrl_pwm_digital_input_ref: pwm-digital-input-refgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0xb0 - >; - }; - - pinctrl_pwm_fan: pwm-fangrp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x60a0 - >; - }; - - pinctrl_qca700x_cp_btld: qca700x-cp-btldgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400000b0 - >; - }; - - pinctrl_qca700x_cp_int: qca700x-cp-intgrp { - fsl,pins = < - MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x10b0 - >; - }; - - pinctrl_qca700x_cp_rst: qca700x-cp-rstgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400000b0 - >; - }; - - pinctrl_qca700x_mains_btld: qca700x-mains-btldgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400000b0 - >; - }; - - pinctrl_rotary_switch1: rotary-switch1grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0xb0 - MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0xb0 - MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0xb0 - >; - }; - - pinctrl_rotary_switch2: rotary-switch2grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0xb0 - MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0xb0 - MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0xb0 - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0xb0 - >; - }; - - pinctrl_rs485_1: rs485-1grp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0xb0 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0xb0 - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0xb0 - >; - }; - - pinctrl_rs485_2: rs485-2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 - MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x10b0 - MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x10b0 - >; - }; - - pinctrl_status_leds: status-ledsgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0xb0 - MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0xb0 - MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0xb0 - >; - }; - - pinctrl_stm32: stm32grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x10b0 - MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x10b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0xb0 - MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0xb0 - >; - }; - - pinctrl_usb: usbgrp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x70b0 - MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x70b0 - >; - }; - - pinctrl_usb_pwr: usb-pwrgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0xb0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x7071 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x7071 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x7071 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x7071 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x7071 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x7071 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x7071 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x7071 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x7071 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x7071 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70b1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70b1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70b1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70b1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70b1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70b1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70b1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70b1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70b1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70b1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70f1 - >; - }; - - pinctrl_wdog2: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x10b0 - >; - }; -}; - -&iomuxc_snvs { - pinctrl-names = "default_snvs"; - pinctrl-0 = <&pinctrl_cp_peak_snvs - &pinctrl_gpio_motor_snvs - &pinctrl_relay_sense_snvs - &pinctrl_rotary_switch1_snvs>; - - pinctrl_accelerometer_int1_snvs: accelerometer-int1-snvsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x130a0 - >; - }; - - pinctrl_cp_peak_snvs: cp-peak-snvsgrp { - fsl,pins = < - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x130a0 - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 - >; - }; - - pinctrl_enet1_phy_rst: enet1-phy-rstgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x100a0 - >; - }; - - pinctrl_fan_sense_snvs: fan-sense-snvsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x100a0 - >; - }; - - pinctrl_gpio_motor_snvs: gpio-motor-snvsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 - >; - }; - - pinctrl_qca700x_mains_int: qca700x-mains-intgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x130a0 - >; - }; - - pinctrl_qca700x_mains_rst: qca700x-mains-rstgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400100a0 - >; - }; - - pinctrl_relay_sense_snvs: relay-sense-snvsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x100a0 - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x100a0 - >; - }; - - pinctrl_rotary_switch1_snvs: rotary-switch1-snvsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x110a0 - >; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_digital_input_ref>; - status = "okay"; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_cp>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rs485_1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - fsl,dte-mode; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rs485_2>; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stm32>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ext_uart>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb - &pinctrl_usb_pwr>; - dr_mode = "host"; - power-active-high; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-cal-45-dn-ohms = <35>; - fsl,tx-cal-45-dp-ohms = <35>; -}; - -&usbphy2 { - fsl,tx-cal-45-dn-ohms = <35>; - fsl,tx-cal-45-dp-ohms = <35>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - vmmc-supply = <&sw2_reg>; - vqmmc-supply = <®_1v8>; - mmc-pwrseq = <&emmc_pwrseq>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog2>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/imx6ull-tarragon-master.dts deleted file mode 100644 index 67007ce383e3..000000000000 --- a/arch/arm/boot/dts/imx6ull-tarragon-master.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright (C) 2023 chargebyte GmbH - -#include "imx6ull-tarragon-common.dtsi" - -/ { - model = "chargebyte Tarragon Master"; - compatible = "chargebyte,imx6ull-tarragon-master", "fsl,imx6ull"; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan_sense_snvs>; - fan-supply = <®_fan>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - - reg_fan: regulator { - compatible = "regulator-fixed"; - regulator-name = "fan-supply"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan_enable>; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&ecspi2 { - status = "okay"; - - qca700x_cp: ethernet@0 { - reg = <0x0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qca700x_cp_int - &pinctrl_qca700x_cp_rst - &pinctrl_qca700x_cp_btld>; - interrupt-parent = <&gpio2>; - interrupts = <19 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <16000000>; - }; -}; - -&ecspi4 { - status = "okay"; - - qca700x_mains: ethernet@0 { - reg = <0x0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qca700x_mains_int - &pinctrl_qca700x_mains_rst - &pinctrl_qca700x_mains_btld>; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <16000000>; - }; -}; - -&fec1 { - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_fan>; - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts deleted file mode 100644 index e471c2005bee..000000000000 --- a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright (C) 2023 chargebyte GmbH - -#include "imx6ull-tarragon-common.dtsi" - -/ { - model = "chargebyte Tarragon Micro"; - compatible = "chargebyte,imx6ull-tarragon-micro", "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts deleted file mode 100644 index cee223b5f8e1..000000000000 --- a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright (C) 2023 chargebyte GmbH - -#include "imx6ull-tarragon-common.dtsi" - -/ { - model = "chargebyte Tarragon Slave"; - compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull"; -}; - -&ecspi2 { - status = "okay"; - - qca700x_cp: ethernet@0 { - reg = <0x0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qca700x_cp_int - &pinctrl_qca700x_cp_rst - &pinctrl_qca700x_cp_btld>; - interrupt-parent = <&gpio2>; - interrupts = <19 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <16000000>; - }; -}; - -&fec1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts deleted file mode 100644 index 7fd53b7a4372..000000000000 --- a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright (C) 2023 chargebyte GmbH - -#include "imx6ull-tarragon-common.dtsi" - -/ { - model = "chargebyte Tarragon SlaveXT"; - compatible = "chargebyte,imx6ull-tarragon-slavext", "fsl,imx6ull"; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan_sense_snvs>; - fan-supply = <®_fan>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - - reg_fan: regulator { - compatible = "regulator-fixed"; - regulator-name = "fan-supply"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan_enable>; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&ecspi2 { - status = "okay"; - - qca700x_cp: ethernet@0 { - reg = <0x0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qca700x_cp_int - &pinctrl_qca700x_cp_rst - &pinctrl_qca700x_cp_btld>; - interrupt-parent = <&gpio2>; - interrupts = <19 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <16000000>; - }; -}; - -&fec1 { - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_fan>; - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts deleted file mode 100644 index e593b7036fc7..000000000000 --- a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6ull-tqma6ull2.dtsi" -#include "mba6ulx.dtsi" - -/ { - model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; - compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi deleted file mode 100644 index 8541cb3f3b3e..000000000000 --- a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -#include "imx6ull.dtsi" -#include "imx6ul-tqma6ul-common.dtsi" -#include "imx6ul-tqma6ulx-common.dtsi" - -/ { - model = "TQ-Systems TQMa6ULL2 SoM"; - compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; -}; - -&usdhc2 { - fsl,tuning-step = <6>; - /* Errata ERR010450 Workaround */ - max-frequency = <99000000>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts deleted file mode 100644 index 33437aae9822..000000000000 --- a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/dts-v1/; - -#include "imx6ull-tqma6ull2l.dtsi" -#include "mba6ulx.dtsi" - -/ { - model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; - compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi deleted file mode 100644 index be593d47e3b1..000000000000 --- a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -#include "imx6ull.dtsi" -#include "imx6ul-tqma6ul-common.dtsi" -#include "imx6ul-tqma6ulxl-common.dtsi" - -/ { - model = "TQ Systems TQMa6ULL2L SoM"; - compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; -}; - -&usdhc2 { - fsl,tuning-step = <6>; - /* Errata ERR010450 Workaround */ - max-frequency = <99000000>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi deleted file mode 100644 index 2bccd45e9fc2..000000000000 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2016 Freescale Semiconductor, Inc. - -#include "imx6ul.dtsi" -#include "imx6ull-pinfunc.h" -#include "imx6ull-pinfunc-snvs.h" - -/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ -/delete-node/ &uart8; -/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ -/delete-node/ &crypto; - -&cpu0 { - clock-frequency = <900000000>; - operating-points = < - /* kHz uV */ - 900000 1275000 - 792000 1225000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 900000 1250000 - 792000 1175000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; -}; - -&ocotp { - compatible = "fsl,imx6ull-ocotp", "syscon"; -}; - -&pxp { - compatible = "fsl,imx6ull-pxp"; - interrupts = , - ; -}; - -&usdhc1 { - compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; -}; - -&usdhc2 { - compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; -}; - -/ { - soc: soc { - aips3: bus@2200000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02200000 0x100000>; - ranges; - - dcp: crypto@2280000 { - compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; - reg = <0x02280000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6ULL_CLK_DCP_CLK>; - clock-names = "dcp"; - }; - - rngb: rng@2284000 { - compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; - reg = <0x02284000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>; - }; - - iomuxc_snvs: iomuxc-snvs@2290000 { - compatible = "fsl,imx6ull-iomuxc-snvs"; - reg = <0x02290000 0x4000>; - }; - - uart8: serial@2288000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02288000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART8_IPG>, - <&clks IMX6UL_CLK_UART8_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts deleted file mode 100644 index 483d9732c002..000000000000 --- a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2018 NXP. - -/dts-v1/; - -#include "imx6ulz.dtsi" -#include "imx6ul-14x14-evk.dtsi" - -/delete-node/ &fec1; -/delete-node/ &fec2; -/delete-node/ &can1; -/delete-node/ &can2; -/delete-node/ &lcdif; -/delete-node/ &tsc; - -/ { - model = "Freescale i.MX6 ULZ 14x14 EVK Board"; - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; - - /delete-node/ panel; -}; diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts deleted file mode 100644 index c92e4e2f6ab9..000000000000 --- a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include -#include "imx6ulz.dtsi" - -/ { - model = "BSH SMM M2"; - compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; - - chosen { - stdout-path = &uart4; - }; - - usdhc2_pwrseq: usdhc2-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - bus-width = <4>; - no-1-8-v; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - cap-sdio-irq; - mmc-pwrseq = <&usdhc2_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&wdog1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ - MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ - MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ - MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ulz.dtsi b/arch/arm/boot/dts/imx6ulz.dtsi deleted file mode 100644 index 0b5f1a763567..000000000000 --- a/arch/arm/boot/dts/imx6ulz.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2018 NXP. - -#include "imx6ull.dtsi" - -/ { - aliases { - /delete-property/ ethernet0; - /delete-property/ ethernet1; - /delete-property/ i2c2; - /delete-property/ i2c3; - /delete-property/ serial4; - /delete-property/ serial5; - /delete-property/ serial6; - /delete-property/ serial7; - /delete-property/ spi2; - /delete-property/ spi3; - }; -}; - -/delete-node/ &adc1; -/delete-node/ &ecspi3; -/delete-node/ &ecspi4; -/delete-node/ &epit2; -/delete-node/ &gpt2; -/delete-node/ &i2c3; -/delete-node/ &i2c4; -/delete-node/ &pwm5; -/delete-node/ &pwm6; -/delete-node/ &pwm7; -/delete-node/ &pwm8; -/delete-node/ &uart5; -/delete-node/ &uart6; -/delete-node/ &uart7; -/delete-node/ &uart8; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi deleted file mode 100644 index 01612741f792..000000000000 --- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/* Colibri AD0 to AD3 */ -&adc1 { - status = "okay"; -}; - -/* Colibri SSP */ -&ecspi3 { - cs-gpios = < - &gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or */ - &gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */ - &gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */ - >; - status = "okay"; -}; - -/* Colibri Fast Ethernet */ -&fec1 { - status = "okay"; -}; - -/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ -&i2c4 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm1 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm4 { - status = "okay"; -}; - -/* M41T0M6 real time clock */ -&rtc { - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - status = "okay"; -}; - -/* Colibri UART_B */ -&uart2 { - status = "okay"; -}; - -/* Colibri UART_C */ -&uart3 { - status = "okay"; -}; - -/* Colibri USBC */ -&usbotg1 { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC/SD */ -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi deleted file mode 100644 index 326440f2b4f4..000000000000 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016-2022 Toradex - */ - -/ { - /* Fixed crystal dedicated to MCP2515. */ - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; -}; - -/* Colibri AD0 to AD3 */ -&adc1 { - status = "okay"; -}; - -/* - * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. - * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. - */ -&atmel_mxt_ts { - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ - pinctrl-0 = <&pinctrl_atmel_adapter>; - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ - status = "disabled"; -}; - -/* Colibri SSP */ -&ecspi3 { - status = "okay"; - - mcp2515: can@0 { - clocks = <&clk16m>; - compatible = "microchip,mcp2515"; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; -}; - -/* Colibri Fast Ethernet */ -&fec1 { - status = "okay"; -}; - -/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ -&i2c4 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm1 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm4 { - status = "okay"; -}; - -/* M41T0M6 real time clock */ -&rtc { - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - status = "okay"; -}; - -/* Colibri UART_B */ -&uart2 { - status = "okay"; -}; - -/* Colibri UART_C */ -&uart3 { - status = "okay"; -}; - -/* Colibri USBC */ -&usbotg1 { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC/SD */ -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi deleted file mode 100644 index b687727f956a..000000000000 --- a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - reg_3v3_vmmc: regulator-3v3-vmmc { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */ - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3v3_vmmc"; - startup-delay-us = <100>; - }; -}; - -/* Colibri AD0 to AD3 */ -&adc1 { - status = "okay"; -}; - -/* Colibri SSP */ -&ecspi3 { - status = "okay"; -}; - -/* Colibri Fast Ethernet */ -&fec1 { - status = "okay"; -}; - -&gpio2 { - /* - * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to - * turn the transceiver off, that property has to be deleted and the gpio handled in - * userspace. - * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on. - */ - uart-b-c-on-x14-enable-hog { - gpio-hog; - gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ - output-high; - }; -}; - -&gpio5 { - uart-a-on-x13-enable-hog { - gpio-hog; - gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ - output-high; - }; -}; - -/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ -&i2c4 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm1 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm4 { - status = "okay"; -}; - -/* M41T0M6 real time clock */ -&rtc { - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - status = "okay"; -}; - -/* Colibri UART_B */ -&uart2 { - status = "okay"; -}; - -/* Colibri UART_C */ -&uart3 { - status = "okay"; -}; - -/* Colibri USBC */ -&usbotg1 { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC/SD, UHS-I capable uSD slot */ -&usdhc1 { - cap-power-off-card; - /delete-property/ keep-power-in-suspend; - /delete-property/ no-1-8-v; - vmmc-supply = <®_3v3_vmmc>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi deleted file mode 100644 index 6a9e5ab59691..000000000000 --- a/arch/arm/boot/dts/imx7-colibri-iris.dtsi +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/* Colibri AD0 to AD3 */ -&adc1 { - status = "okay"; -}; - -/* - * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. - * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. - */ -&atmel_mxt_ts { - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ - pinctrl-0 = <&pinctrl_atmel_adapter>; - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ -}; - -/* Colibri SSP */ -&ecspi3 { - status = "okay"; -}; - -/* Colibri Fast Ethernet */ -&fec1 { - status = "okay"; -}; - -&gpio2 { - /* - * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the - * transceiver off, that property has to be deleted and the gpio handled in userspace. - * The same applies to uart1_tx_on where the UART1 transceiver is turned on. - */ - uart25-tx-on-hog { - gpio-hog; - gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ - output-high; - }; -}; - -&gpio5 { - uart1-tx-on-hog { - gpio-hog; - gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ - output-high; - }; -}; - -/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ -&i2c4 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm1 { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm4 { - status = "okay"; -}; - -/* M41T0M6 real time clock */ -&rtc { - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - status = "okay"; -}; - -/* Colibri UART_B */ -&uart2 { - status = "okay"; -}; - -/* Colibri UART_C */ -&uart3 { - status = "okay"; -}; - -/* Colibri USBC */ -&usbotg1 { - disable-over-current; - status = "okay"; -}; - -/* Colibri MMC/SD */ -&usdhc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi deleted file mode 100644 index 104580d51d74..000000000000 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ /dev/null @@ -1,1142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016-2022 Toradex - */ - -#include - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - backlight: backlight { - brightness-levels = <0 45 63 88 119 158 203 255>; - compatible = "pwm-backlight"; - default-brightness-level = <4>; - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - power-supply = <®_module_3v3>; - pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - extcon_usbc_det: usbc-det { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbc_det>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - key-wakeup { - debounce-interval = <10>; - gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ - label = "Wake-Up"; - linux,code = ; - wakeup-source; - }; - }; - - panel_dpi: panel-dpi { - backlight = <&backlight>; - compatible = "edt,et057090dhu"; - power-supply = <®_3v3>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3.3V"; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "5V"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3"; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_AVDD_AUDIO"; - }; - - reg_module_3v3_eth: regulator-module-3v3-eth { - compatible = "regulator-fixed"; - off-on-delay-us = <200000>; - regulator-name = "+V3.3_ETH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - startup-delay-us = <200000>; - vin-supply = <®_LDO1>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "VCC_USB[1-4]"; - vin-supply = <®_5v0>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "imx7-sgtl5000"; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - sound-dai = <&codec>; - }; - }; -}; - -/* Colibri AD0 to AD3 */ -&adc1 { - vref-supply = <®_DCDC3>; -}; - -/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */ - -&cpu0 { - cpu-supply = <®_DCDC2>; -}; - -/* Colibri SSP */ -&ecspi3 { - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; -}; - -/* Colibri Fast Ethernet */ -&fec1 { - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rmii"; - phy-supply = <®_module_3v3_eth>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet1>; - pinctrl-1 = <&pinctrl_enet1_sleep>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Micrel KSZ8041RNL */ - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - micrel,led-mode = <0>; - reg = <0>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&gpio1 { - gpio-line-names = "SODIMM_43", - "SODIMM_45", - "SODIMM_135", - "SODIMM_22", - "", - "", - "SODIMM_37", - "SODIMM_29", - "SODIMM_59", - "SODIMM_28", - "SODIMM_30", - "SODIMM_67", - "", - "", - "SODIMM_188", - "SODIMM_178"; -}; - -&gpio2 { - gpio-line-names = "SODIMM_111", - "SODIMM_113", - "SODIMM_115", - "SODIMM_117", - "SODIMM_119", - "SODIMM_121", - "SODIMM_123", - "SODIMM_125", - "SODIMM_91", - "SODIMM_89", - "SODIMM_105", - "SODIMM_152", - "SODIMM_150", - "SODIMM_95", - "SODIMM_126", - "SODIMM_107", - "SODIMM_114", - "SODIMM_116", - "SODIMM_118", - "SODIMM_120", - "SODIMM_122", - "SODIMM_124", - "SODIMM_127", - "SODIMM_130", - "SODIMM_132", - "SODIMM_134", - "SODIMM_133", - "SODIMM_104", - "SODIMM_106", - "SODIMM_110", - "SODIMM_112", - "SODIMM_128"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_56", - "SODIMM_44", - "SODIMM_68", - "SODIMM_82", - "SODIMM_93", - "SODIMM_76", - "SODIMM_70", - "SODIMM_60", - "SODIMM_58", - "SODIMM_78", - "SODIMM_72", - "SODIMM_80", - "SODIMM_46", - "SODIMM_62", - "SODIMM_48", - "SODIMM_74", - "SODIMM_50", - "SODIMM_52", - "SODIMM_54", - "SODIMM_66", - "SODIMM_64", - "SODIMM_57", - "SODIMM_61", - "SODIMM_136", - "SODIMM_138", - "SODIMM_140", - "SODIMM_142", - "SODIMM_144", - "SODIMM_146"; -}; - -&gpio4 { - gpio-line-names = "SODIMM_35", - "SODIMM_33", - "SODIMM_38", - "SODIMM_36", - "SODIMM_21", - "SODIMM_19", - "SODIMM_131", - "SODIMM_129", - "SODIMM_90", - "SODIMM_92", - "SODIMM_88", - "SODIMM_86", - "SODIMM_81", - "SODIMM_94", - "SODIMM_96", - "SODIMM_75", - "SODIMM_101", - "SODIMM_103", - "SODIMM_79", - "SODIMM_97", - "SODIMM_67", - "SODIMM_59", - "SODIMM_85", - "SODIMM_65"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_69", - "SODIMM_71", - "SODIMM_73", - "SODIMM_47", - "SODIMM_190", - "SODIMM_192", - "SODIMM_49", - "SODIMM_51", - "SODIMM_53", - "", - "", - "SODIMM_98", - "SODIMM_184", - "SODIMM_186", - "SODIMM_23", - "SODIMM_31", - "SODIMM_100", - "SODIMM_102"; -}; - -&gpio6 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_169", - "", - "", - "", - "SODIMM_77", - "SODIMM_24", - "", - "SODIMM_25", - "SODIMM_27", - "SODIMM_32", - "SODIMM_34"; -}; - -&gpio7 { - gpio-line-names = "", - "", - "SODIMM_63", - "SODIMM_55", - "", - "", - "", - "", - "SODIMM_196", - "SODIMM_194", - "", - "SODIMM_99", - "", - "", - "SODIMM_137"; -}; - -/* NAND on such SKUs */ -&gpmi { - fsl,use-minimum-ecc; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; -}; - -/* On-module Power I2C */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; - pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; - scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1_mclk>; - reg = <0xa>; - VDDA-supply = <®_module_3v3_avdd>; - VDDD-supply = <®_DCDC3>; - VDDIO-supply = <®_module_3v3>; - }; - - ad7879_ts: touchscreen@2c { - adi,acquisition-time = /bits/ 8 <1>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,median-filter-size = /bits/ 8 <2>; - adi,resistance-plate-x = <120>; - compatible = "adi,ad7879-1"; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reg = <0x2c>; - touchscreen-max-pressure = <4096>; - status = "disabled"; - }; - - pmic@33 { - compatible = "ricoh,rn5t567"; - reg = <0x33>; - - regulators { - reg_DCDC1: DCDC1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1000000>; - regulator-name = "+V1.0_SOC"; - }; - - reg_DCDC2: DCDC2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <975000>; - regulator-name = "+V1.1_ARM"; - }; - - reg_DCDC3: DCDC3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8"; - }; - - reg_DCDC4: DCDC4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1350000>; - regulator-min-microvolt = <1350000>; - regulator-name = "+V1.35_DRAM"; - }; - - reg_LDO1: LDO1 { - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PWR_EN_+V3.3_ETH"; - }; - - reg_LDO2: LDO2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SD"; - }; - - reg_LDO3: LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PWR_EN_+V3.3_LPSR"; - }; - - reg_LDO4: LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_LPSR"; - }; - - reg_LDO5: LDO5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PWR_EN_+V3.3"; - }; - }; - }; -}; - -/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_recovery>; - scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; - - /* Atmel maxtouch controller */ - atmel_mxt_ts: touchscreen@4a { - compatible = "atmel,maxtouch"; - interrupt-parent = <&gpio2>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_atmel_connector>; - reg = <0x4a>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - status = "disabled"; - }; -}; - -&lcdif { - assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "disabled"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; -}; - -/* Colibri PWM */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -/* Colibri PWM */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; -}; - -/* Colibri PWM */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -/* Colibri PWM */ -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -®_1p0d { - vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */ -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; - uart-has-rtscts; -}; - -/* Colibri UART_B */ -&uart2 { - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* Colibri UART_C */ -&uart3 { - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -/* Colibri USBC */ -&usbotg1 { - dr_mode = "otg"; - extcon = <0>, <&extcon_usbc_det>; -}; - -/* Colibri MMC/SD */ -&usdhc1 { - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - disable-wp; - no-1-8-v; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; - pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_LDO2>; - wakeup-source; -}; - -/* eMMC on 1GB (eMMC) SKUs */ -&usdhc3 { - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - sdhci-caps-mask = <0x80000000 0x0>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <®_DCDC3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; - - /* - * Atmel MXT touchsceen + Capacitive Touch Adapter - * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3. - * Don't use them simultaneously. - */ - pinctrl_atmel_adapter: atmeladaptergrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */ - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */ - >; - }; - - /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ - pinctrl_atmel_connector: atmelconnectorgrp { - fsl,pins = < - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */ - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */ - >; - }; - - pinctrl_can_int: canintgrp { - fsl,pins = < - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */ - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */ - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */ - >; - }; - - pinctrl_ecspi3_cs: ecspi3csgrp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - >; - }; - - pinctrl_enet1_sleep: enet1-sleepgrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 - MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 - MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 - MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 - MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ - MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ - MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ - MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ - >; - }; - - pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */ - fsl,pins = < - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ - MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ - MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ - >; - }; - - pinctrl_gpio3: gpio3grp { /* LCD 18-23 */ - fsl,pins = < - MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ - MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ - MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ - >; - }; - - pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */ - fsl,pins = < - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ - >; - }; - - pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */ - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - >; - }; - - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 - MX7D_PAD_SD3_CLK__NAND_CLE 0x71 - MX7D_PAD_SD3_CMD__NAND_ALE 0x71 - MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 - MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 - MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 - MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 - MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 - MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 - MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 - MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 - MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 - MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 - >; - }; - - pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */ - fsl,pins = < - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */ - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */ - >; - }; - - pinctrl_i2c4_recovery: i2c4-recoverygrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f - MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */ - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */ - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */ - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */ - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */ - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */ - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */ - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */ - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */ - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */ - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */ - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */ - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */ - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */ - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */ - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */ - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */ - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */ - >; - }; - - pinctrl_lcdif_dat_24: lcdifdat24grp { - fsl,pins = < - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */ - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */ - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */ - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */ - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */ - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */ - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */ - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */ - >; - }; - - pinctrl_lvds_transceiver: lvdstx { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */ - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */ - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */ - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */ - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */ - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */ - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */ - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */ - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */ - >; - }; - - pinctrl_uart1_ctrl1: uart1ctrl1grp { - fsl,pins = < - MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */ - MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */ - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */ - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */ - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */ - >; - }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */ - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */ - >; - }; - - pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */ - >; - }; - - pinctrl_usbh_reg: usbhreggrp { - fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */ - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */ - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */ - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */ - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */ - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; - - /* Avoid backfeeding with removed card power. */ - pinctrl_usdhc1_sleep: usdhc1-slpgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x10 - MX7D_PAD_SD1_CLK__SD1_CLK 0x10 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - >; - }; - - pinctrl_sai1_mclk: sai1mclkgrp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_lpsr>; - - pinctrl_cd_usdhc1: cdusdhc1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */ - >; - }; - - pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0 - >; - }; - - pinctrl_gpio_lpsr: gpiolpsrgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */ - MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */ - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c1_recovery: i2c1-recoverygrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f - >; - }; - - pinctrl_uart1_ctrl2: uart1ctrl2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */ - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi deleted file mode 100644 index 3df6dff7734a..000000000000 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ /dev/null @@ -1,640 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ-Systems MBa7 carrier board. - * - * Copyright (C) 2016 TQ-Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - * - * Note: This file does not include nodes for all peripheral devices. - * As device driver coverage increases additional nodes can be added. - */ - -#include -#include - -/ { - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc1; - /delete-property/ mmc2; - }; - - beeper { - compatible = "gpio-beeper"; - gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = &uart6; - }; - - gpio_buttons: gpio-keys { - compatible = "gpio-keys"; - - button-0 { - /* #SWITCH_A */ - label = "S11"; - linux,code = ; - gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; - }; - - button-1 { - /* #SWITCH_B */ - label = "S12"; - linux,code = ; - gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; - }; - - button-2 { - /* #SWITCH_C */ - label = "S13"; - linux,code = ; - gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led1 { - label = "led1"; - gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led2 { - label = "led2"; - gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_SD1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_fec1_pwdn: regulator-fec1-pwdn { - compatible = "regulator-fixed"; - regulator-name = "PWDN_FEC1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_fec2_pwdn: regulator-fec2-pwdn { - compatible = "regulator-fixed"; - regulator-name = "PWDN_FEC2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_USBOTG1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_USBOTG2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_mpcie_1v5: regulator-mpcie-1v5 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V5_MPCIE"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_mpcie_3v3: regulator-mpcie-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_MPCIE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_mba_12v0: regulator-mba-12v0 { - compatible = "regulator-fixed"; - regulator-name = "VCC12V0_MBA7"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_transmitter: regulator-lvds-transmitter { - compatible = "regulator-fixed"; - regulator-name = "#SHTDN_LVDS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8_REF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&sw2_reg>; - }; - - reg_audio_3v3: regulator-audio-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; - ssi-controller = <&sai1>; - audio-codec = <&tlv320aic32x4>; - audio-routing = - "IN3_L", "Mic Jack", - "Mic Jack", "Mic Bias", - "IN1_L", "Line In Jack", - "IN1_R", "Line In Jack", - "Line Out Jack", "LOL", - "Line Out Jack", "LOR"; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, - <&gpio4 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-supply = <®_fec1_pwdn>; - phy-handle = <ðphy1_0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1_0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - }; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - uboot@0 { - label = "U-Boot"; - reg = <0x0 0xd0000>; - }; - - env1@d0000 { - label = "ENV1"; - reg = <0xd0000 0x10000>; - }; - - env2@e0000 { - label = "ENV2"; - reg = <0xe0000 0x10000>; - }; - - dtb@f0000 { - label = "DTB"; - reg = <0xf0000 0x10000>; - }; - - linux@100000 { - label = "Linux"; - reg = <0x100000 0x700000>; - }; - - rootfs@800000 { - label = "RootFS"; - reg = <0x800000 0x3800000>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - lm75: temperature-sensor@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - tlv320aic32x4: audio-codec@18 { - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - clock-names = "mclk"; - ldoin-supply = <®_audio_3v3>; - iov-supply = <®_audio_3v3>; - }; - - pca9555: gpio-expander@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9555>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio7>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 - /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 - /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 - >; - }; - - pinctrl_hog_mba7_1: hogmba71grp { - fsl,pins = < - /* Limitation: WDOG2_B / WDOG2_RESET not usable */ - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 - /* #BOOT_EN */ - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 - >; - }; - - pinctrl_pca9555: pca95550grp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 - MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c - MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c - - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 - /* Limitation: RTS is not connected */ - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e - >; - }; - - pinctrl_usdhc1_gpio: usdhc1grp_gpio { - fsl,pins = < - /* WP */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c - /* CD */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c - /* VSELECT */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5e - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_pwm1: pwm1grp { - fsl,pins = < - /* LCD_CONTRAST */ - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -&usbh { - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - vbus-supply = <®_usb_otg1_vbus>; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_sd1_vmmc>; - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - fsl,ext-reset-output; -}; diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi deleted file mode 100644 index fe42b0a46831..000000000000 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB. - * - * Copyright (C) 2016 TQ-Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -/ { - memory@80000000 { - device_type = "memory"; - /* 512 MB - default configuration */ - reg = <0x80000000 0x20000000>; - }; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&gpio2 { - /* Configured as pullup by QSPI pin group */ - qspi-reset-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - input; - line-name = "qspi-reset"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - pfuze3000: pmic@8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic1>; - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - /* NXP SE97BTP with temperature sensor + eeprom */ - se97b: temperature-sensor-eeprom@1e { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x1e>; - status = "okay"; - }; - - /* ST M24C64 */ - m24c64: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - status = "okay"; - }; - - at24c02: eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - pagesize = <16>; - status = "okay"; - }; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 - >; - }; - - pinctrl_pmic1: pmic1grp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 - MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 - >; - }; - - pinctrl_qspi_reset: qspi_resetgrp { - fsl,pins = < - /* #QSPI_RESET */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x56 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; - }; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; -}; - -&sdma { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - non-removable; - vmmc-supply = <&vgen4_reg>; - vqmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - /* - * Errata e10574: - * WDOG reset needs to run with WDOG_RESET_B signal enabled. - * X1-51 (WDOG1#) signal needs carrier board handling to reset - * TQMa7 on X1-22 (RESET_IN#). - */ - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts deleted file mode 100644 index 713483c39c9d..000000000000 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Support for CompuLab CL-SOM-iMX7 System-on-Module - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Ilya Ledvich - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "CompuLab CL-SOM-iMX7"; - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ - }; - - reg_usb_otg1_vbus: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&cpu1 { - cpu-supply = <&sw1a_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30 - MX7D_PAD_SD2_WP__ENET1_MDC 0x30 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts deleted file mode 100644 index 00ab92e56da4..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-aster.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri.dtsi" -#include "imx7-colibri-aster.dtsi" - -/ { - model = "Toradex Colibri iMX7D on Aster Carrier Board"; - compatible = "toradex,colibri-imx7d-aster", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts deleted file mode 100644 index d9c7045a55ba..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - * - */ - -/dts-v1/; -#include "imx7d-colibri-emmc.dtsi" -#include "imx7-colibri-aster.dtsi" - -/ { - model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; - compatible = "toradex,colibri-imx7d-emmc-aster", - "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts deleted file mode 100644 index 96b599439dde..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri-emmc.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-emmc-eval-v3", - "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts deleted file mode 100644 index 5eccb837b158..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri-emmc.dtsi" -#include "imx7-colibri-iris-v2.dtsi" - -/ { - model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board"; - compatible = "toradex,colibri-imx7d-emmc-iris-v2", - "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts deleted file mode 100644 index ae10e8a66ff1..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri-emmc.dtsi" -#include "imx7-colibri-iris.dtsi" - -/ { - model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board"; - compatible = "toradex,colibri-imx7d-emmc-iris", - "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi deleted file mode 100644 index 3740e34ef99f..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - */ - -#include "imx7d.dtsi" -#include "imx7-colibri.dtsi" - -/ { - aliases { - /* Required to properly pass MAC addresses from bootloader. */ - ethernet0 = &fec1; - ethernet1 = &fec2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&cpu1 { - cpu-supply = <®_DCDC2>; -}; - -&gpio6 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_169", - "SODIMM_157", - "", - "SODIMM_163", - "SODIMM_77", - "SODIMM_24", - "", - "SODIMM_25", - "SODIMM_27", - "SODIMM_32", - "SODIMM_34"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - dr_mode = "host"; - vbus-supply = <®_usbh_vbus>; -}; - -/* eMMC */ -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts deleted file mode 100644 index 33d787617db0..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016-2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-eval-v3", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -&ad7879_ts { - status = "okay"; -}; - -/* - * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. - * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. - */ -&atmel_mxt_ts { - status = "disabled"; -}; - -&backlight { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts deleted file mode 100644 index afdb1d06c7f6..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri.dtsi" -#include "imx7-colibri-iris-v2.dtsi" - -/ { - model = "Toradex Colibri iMX7D on Iris V2 Carrier Board"; - compatible = "toradex,colibri-imx7d-iris-v2", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&gpio2 { - /* - * This switches the LVDS transceiver to VESA color mapping mode. - */ - lvds-color-map-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ - line-name = "LVDS_COLOR_MAP"; - output-low; - }; -}; - -&gpio7 { - /* - * This switches the LVDS transceiver to the 24-bit RGB mode. - */ - lvds-rgb-mode-hog { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ - line-name = "LVDS_RGB_MODE"; - output-low; - }; - - /* - * This switches the LVDS transceiver to the single-channel - * output mode. - */ - lvds-ch-mode-hog { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ - line-name = "LVDS_CH_MODE"; - output-high; - }; - - /* This turns the LVDS transceiver on */ - lvds-power-on-hog { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ - line-name = "LVDS_POWER_ON"; - output-high; - }; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts deleted file mode 100644 index 531b0b99bd5a..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri-iris.dts +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; -#include "imx7d-colibri.dtsi" -#include "imx7-colibri-iris.dtsi" - -/ { - model = "Toradex Colibri iMX7D on Iris Carrier Board"; - compatible = "toradex,colibri-imx7d-iris", - "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -&ad7879_ts { - status = "okay"; -}; - -/* - * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. - * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. - */ -&atmel_mxt_ts { - status = "disabled"; -}; - -&backlight { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri USBH */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi deleted file mode 100644 index 531a45b176a1..000000000000 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016-2022 Toradex - */ - -#include "imx7d.dtsi" -#include "imx7-colibri.dtsi" - -/ { - aliases { - /* Required to properly pass MAC addresses from bootloader. */ - ethernet0 = &fec1; - ethernet1 = &fec2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&cpu1 { - cpu-supply = <®_DCDC2>; -}; - -/* NAND */ -&gpmi { - status = "okay"; -}; - -/* Colibri USBH */ -&usbotg2 { - dr_mode = "host"; - vbus-supply = <®_usbh_vbus>; -}; diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts deleted file mode 100644 index a6d68165fb1e..000000000000 --- a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Kamstrup OMNIA Flex Concentrator in - * manufacturing/debugging mode. - * - * Copyright (C) 2020 Kamstrup A/S - * Author: Bruno Thomsen - */ - -/dts-v1/; - -#include "imx7d-flex-concentrator.dts" - -/ { - model = "Kamstrup OMNIA Flex Concentrator - Manufacturing"; - compatible = "kam,imx7d-flex-concentrator-mfg", "fsl,imx7d"; - - chosen { - stdout-path = &uart4; - }; -}; - -&uart4 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/imx7d-flex-concentrator.dts deleted file mode 100644 index 3a723843d562..000000000000 --- a/arch/arm/boot/dts/imx7d-flex-concentrator.dts +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Kamstrup OMNIA Flex Concentrator. - * - * Copyright (C) 2020 Kamstrup A/S - * Author: Bruno Thomsen - */ - -/dts-v1/; - -#include "imx7d-tqma7.dtsi" - -/* One I2C device on TQMa7 SoM is not mounted */ -/delete-node/ &ds1339; - -/ { - model = "Kamstrup OMNIA Flex Concentrator"; - compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; - - memory@80000000 { - device_type = "memory"; - /* 1024 MB - TQMa7D board configuration */ - reg = <0x80000000 0x40000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_USBOTG2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8_REF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&sw2_reg>; - }; - - /* - * Human Machine Interface consists of 4 dual red/green LEDs. - * hmi-a:green is controlled directly by the switch-mode power supply. - * hmi-a:red is not used. - */ - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "hmi-b:red:heartbeat-degraded"; - gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "hmi-b:green:heartbeat-running"; - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "hmi-c:red:mesh-error"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "hmi-c:green:mesh-activity"; - gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - }; - - led-4 { - label = "hmi-d:red:omnia-error"; - gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - }; - - led-5 { - label = "hmi-d:green:omnia-activity"; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - }; - }; - - /* - * Errata e10574 board restart workaround. - */ - gpio-restart { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_restart>; - compatible = "gpio-restart"; - gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -/* - * Analog signals - * ADC1_IN0: SMPS - 5V output monitor (voltage divider: 1/0.2806) - */ -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; - status = "okay"; - - pcf2127: rtc@0 { - compatible = "nxp,pcf2127"; - reg = <0>; - spi-max-frequency = <2000000>; - reset-source; - }; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; - status = "okay"; - - /* - * ST chip maximum SPI clock frequency is 33 MHz. - * - * TCG specification - Section 6.4.1 Clocking: - * TPM shall support a SPI clock frequency range of 10-24 MHz. - */ - st33htph: tpm-tis@0 { - compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <24000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy>; - status = "okay"; - - /* - * MDIO bus reset is used to generate PHY device reset before - * Ethernet PHY type ID auto-detection. Otherwise this communication - * fails as device does not answer when recommended reset circuit - * is used. - */ - mdio { - #address-cells = <1>; - #size-cells = <0>; - - reset-delay-us = <100000>; - reset-post-delay-us = <500000>; - reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - - /* Microchip/Micrel KSZ8081RNB */ - ethphy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - reg = <1>; - }; - }; -}; - -/* - * Detection signals for internal USB modules. - * Used for robust USB plug and play handling such as USB downstream port - * power-cycle and USB hub reset in case of misbehaving or crashed modules. - * - * SMPS - AC input monitor based on zero crossing. - * Used for last gasp notification. - */ -&gpio3 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "smps-ac-monitor", "", "usb-hub-reset", "", - "", "", "", "", "", "", "", "", - "", "module-b-detection", "", "module-a-detection", "", "", "", ""; -}; - -/* - * Tamper IRQ trigger timestamp reading. - * Used for sealed cover opened/closed notification. - */ -&gpio5 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "rtc-tamper-irq", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_misc>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c /* X2-15 */ - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 /* X2-18 */ - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 /* X2-13 */ - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* X2-20 */ - /* RTC - Tamper IRQ */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x7c /* X2-72 */ - MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x74 /* X2-68 */ - MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x74 /* X2-76 */ - MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x74 /* X2-78 */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x03 /* X2-48 */ - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x03 /* X2-46 */ - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 /* X2-53 */ - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 /* X2-55 */ - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 /* X2-61 */ - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 /* X2-56 */ - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 /* X2-58 */ - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 /* X2-64 */ - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 /* X2-52 */ - /* PHY reset: SRE_FAST, DSE_X1 */ - MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* X1-96 */ - /* Clock from PHY to MAC: 100kPU */ - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x70 /* X3-4 */ - /* PHY interrupt: 100kPU, HYS */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x78 /* X1-80 */ - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x14 /* X2-82 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* X1-82 */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* X1-84 */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* X1-86 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* X1-88 */ - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x14 /* X1-90 */ - >; - }; - - pinctrl_misc: miscgrp { - fsl,pins = < - /* Module A detection (low = present) */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x7c /* X2-105 */ - /* Module B detection (low = present) */ - MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x7c /* X2-103 */ - /* SMPS - AC input monitor (high = failure) */ - MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x7c /* X2-88 */ - /* USB - Hub reset */ - MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */ - >; - }; - - pinctrl_restart: restartgrp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x74 /* X1-94 */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e /* X3-14 */ - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 /* X3-16 */ - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c /* X3-11 */ - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 /* X3-9 */ - >; - }; - -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - dr_mode = "host"; - status = "okay"; -}; - -/* - * External watchdog feature provided by pcf2127. - */ -&wdog1 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts deleted file mode 100644 index 32bf9fa9d00e..000000000000 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board. - * - * Copyright (C) 2016 TQ-Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -/dts-v1/; - -#include "imx7d-tqma7.dtsi" -#include "imx7-mba7.dtsi" - -/ { - model = "TQ-Systems TQMa7D board on MBa7 carrier board"; - compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-supply = <®_fec2_pwdn>; - phy-handle = <ðphy2_0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy2_0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 - MX7D_PAD_SD2_WP__ENET2_MDC 0x00 - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 - /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 - /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* #pcie_wake */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 - /* #pcie_rst */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 - /* #pcie_dis */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - /* 1.5V logically from 3.3V */ - /* probe deferral not supported */ - /* pcie-bus-supply = <®_mpcie_1v5>; */ - reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; - dr_mode = "host"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7d-meerkat96.dts b/arch/arm/boot/dts/imx7d-meerkat96.dts deleted file mode 100644 index dd8003bd1fc0..000000000000 --- a/arch/arm/boot/dts/imx7d-meerkat96.dts +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2019 Linaro Ltd. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "96Boards Meerkat96 Board"; - compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; - - chosen { - stdout-path = &uart6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MB */ - }; - - reg_wlreg_on: regulator-wlreg-on { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlreg_on>; - regulator-name = "wlreg_on"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "green:user1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user4"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wlan"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; - assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - fsl,dte-mode; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - }; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - keep-power-in-suspend; - fsl,tuning-step = <2>; - vmmc-supply = <®_3p3v>; - no-1-8-v; - broken-cd; - status = "okay"; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - no-1-8-v; - no-mmc; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_wlreg_on>; - vqmmc-supply =<®_3p3v>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_irq>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&iomuxc { - pinctrl_bt_gpios: btgpiosgrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX7D_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 - MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 - MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 - MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 - MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 - MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 - MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 - MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x0D - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - >; - }; - - pinctrl_wlan_irq: wlanirqgrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 - >; - }; - - pinctrl_wlreg_on: wlregongrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts deleted file mode 100644 index 9c6476bda4a0..000000000000 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ /dev/null @@ -1,699 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "Boundary Devices i.MX7 Nitrogen7 Board"; - compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight-j9 { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_j9>; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-on; - }; - - backlight_lcd: backlight-j20 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "reg_wlan"; - startup-delay-us = <70000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_pwrseq: usdhc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "ext_clock"; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&cpu1 { - cpu-supply = <&sw1a_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - }; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touch@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_tsc2004>; - interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - clock-names = "mclk"; - wlf,shared-lrclk; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vgen3_reg>; - bus-width = <4>; - fsl,tuning-step = <2>; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan>; - mmc-pwrseq = <&usdhc2_pwrseq>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; - - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 - MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c2_rv4162: i2c2-rv4162grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c3_tsc2004: i2c3tsc2004grp { - fsl,pins = < - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_j2: j2grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d - MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d - MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_2>; - - pinctrl_hog_2: hoggrp-2 { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d - MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d - >; - }; - - pinctrl_backlight_j9: backlightj9grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/imx7d-pico-dwarf.dts deleted file mode 100644 index fdc10563f147..000000000000 --- a/arch/arm/boot/dts/imx7d-pico-dwarf.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx7d-pico.dtsi" -/ { - model = "TechNexion PICO-IMX7D and DWARF baseboard"; - compatible = "technexion,imx7d-pico-dwarf", "fsl,imx7d"; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx7d-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: audio-codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pca9554: io-expander@25 { - compatible = "nxp,pca9554"; - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - reg = <0x25>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio2>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pca9554 4 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&iomuxc { - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/imx7d-pico-hobbit.dts deleted file mode 100644 index d917dc4f2f22..000000000000 --- a/arch/arm/boot/dts/imx7d-pico-hobbit.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2017 NXP - -#include "imx7d-pico.dtsi" - -/ { - model = "TechNexion PICO-IMX7D Board using Hobbit baseboard"; - compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - }; - }; -}; - -&i2c1 { - sgtl5000: codec@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_vref_1v8>; - }; -}; - -&i2c4 { - status = "okay"; - - adc081c: adc@50 { - compatible = "ti,adc081c"; - reg = <0x50>; - vref-supply = <®_3p3v>; - }; -}; - -&ecspi3 { - ads7846@0 { - reg = <0>; - compatible = "ti,ads7846"; - interrupt-parent = <&gpio2>; - interrupts = <7 0>; - spi-max-frequency = <1000000>; - pendown-gpio = <&gpio2 7 0>; - vcc-supply = <®_3p3v>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <4095>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4095>; - ti,pressure-max = /bits/ 16 <1024>; - ti,x-plate-ohms = /bits/ 16 <90>; - ti,y-plate-ohms = /bits/ 16 <90>; - ti,debounce-max = /bits/ 16 <70>; - ti,debounce-tol = /bits/ 16 <3>; - ti,debounce-rep = /bits/ 16 <2>; - ti,settle-delay-usec = /bits/ 16 <150>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/imx7d-pico-nymph.dts deleted file mode 100644 index 5afb1674e012..000000000000 --- a/arch/arm/boot/dts/imx7d-pico-nymph.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx7d-pico.dtsi" -/ { - model = "TechNexion PICO-IMX7 and NYMPH baseboard"; - compatible = "technexion,imx7d-pico-nymph", "fsl,imx7d"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx7d-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: audio-codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - adc@52 { - compatible = "ti,adc081c"; - reg = <0x52>; - vref-supply = <®_2p5v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts deleted file mode 100644 index f263e391e24c..000000000000 --- a/arch/arm/boot/dts/imx7d-pico-pi.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2017 NXP - -#include "imx7d-pico.dtsi" - -/ { - model = "TechNexion PICO-IMX7D Board and PI baseboard"; - compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - }; - }; -}; - -&i2c1 { - sgtl5000: codec@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_vref_1v8>; - }; -}; - -&i2c4 { - polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio2>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 - >; - }; - -}; diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi deleted file mode 100644 index 73d90845e85c..000000000000 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ /dev/null @@ -1,675 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2017 NXP - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 50000 0>; - brightness-levels = <0 36 72 108 144 180 216 255>; - default-brightness-level = <6>; - }; - - /* Will be filled by the bootloader */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - panel { - compatible = "vxt,vl050-8048nt-c01"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcdreg_on>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlreg_on: regulator-wlreg_on { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlreg_on>; - regulator-name = "wlreg_on"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_pwr>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usdhc2_pwrseq: usdhc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "ext_clock"; - }; -}; - -&clks { - assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; -}; - -&ecspi3 { - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - status = "okay"; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { /* Backlight */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&uart7 { /* Bluetooth */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - fsl,tuning-step = <2>; - vmmc-supply = <®_3p3v>; - wakeup-source; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { /* Wifi SDIO */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_wlreg_on>; - mmc-pwrseq = <&usdhc2_pwrseq>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - no-1-8-v; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f - MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f - MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ - >; - }; - - pinctrl_can1: can1frp { - fsl,pins = < - MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 - MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 - >; - }; - - pinctrl_can2: can2frp { - fsl,pins = < - MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 - MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78 - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 - >; - }; - - pinctrl_pwm1: pwm1 { - fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f - >; - }; - - pinctrl_pwm2: pwm2 { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f - >; - }; - - pinctrl_pwm3: pwm3 { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f - >; - }; - - pinctrl_pwm4: pwm4grp{ - fsl,pins = < - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f - >; - }; - - pinctrl_reg_wlreg_on: regregongrp { - fsl,pins = < - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79 - MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79 - MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79 - MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79 - >; - }; - - pinctrl_usbotg1_pwr: usbotg_pwr { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wifi_clk: wificlkgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d - >; - }; - - pinctrl_reg_lcdreg_on: reglcdongrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h deleted file mode 100644 index 69f2c1ec8254..000000000000 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ /dev/null @@ -1,1154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX7D_PINFUNC_H -#define __DTS_IMX7D_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 -#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 -#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 -#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 -#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 -#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 -#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 -#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 -#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 -#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 -#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 -#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 -#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 -#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 -#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 -#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 -#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 -#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 -#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 -#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 -#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 -#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 -#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 -#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 -#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 -#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 -#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 -#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 -#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 -#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 -#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 -#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 -#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 -#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 -#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 -#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 -#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 -#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 -#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 -#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 -#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 -#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 -#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 -#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 -#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 -#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 -#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 -#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 -#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 -#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 -#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 -#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 -#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 -#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 -#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 -#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 -#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 -#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 -#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 -#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 -#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 -#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 -#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 -#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 -#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 -#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 -#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 -#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 -#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 -#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 -#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 -#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 -#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 -#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 -#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 -#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 -#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 -#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 -#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 -#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 -#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 -#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 -#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 -#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 -#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 -#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 -#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 -#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 -#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 -#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 -#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 -#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 -#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 -#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 -#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 -#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 -#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 -#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 -#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 -#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 -#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 -#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 -#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 -#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 -#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 -#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 -#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 -#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 -#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 -#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 -#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 -#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 -#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 -#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 -#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 -#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 -#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 -#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 -#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 -#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 -#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 -#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 -#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 -#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 -#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 -#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 -#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 -#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 -#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 -#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 -#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 -#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 -#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 -#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 -#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 -#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 -#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 -#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 -#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 -#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 -#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 -#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 -#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 -#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 -#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 -#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 -#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 -#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 -#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 -#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 -#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 -#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 -#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 -#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 -#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 -#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 -#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 -#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 -#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 -#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 -#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 -#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 -#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 -#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 -#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 -#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 -#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 -#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 -#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 -#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 -#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 -#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 -#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 -#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 -#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 -#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 -#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 -#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 -#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 -#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 -#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 -#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 -#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 -#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 -#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 -#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 -#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 -#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 -#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 -#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 -#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 -#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 -#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 -#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 -#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 -#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 -#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 -#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 -#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 -#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 -#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 -#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 -#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 -#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 -#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 -#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 -#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 -#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 -#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 -#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 -#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 -#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 -#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 -#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 -#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 -#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 -#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 -#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 -#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 -#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 -#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 -#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 -#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 -#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 -#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 -#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 -#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 -#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 -#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 -#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 -#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 -#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 -#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 -#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 -#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 -#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 -#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 -#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 -#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 -#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 -#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 -#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 -#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 -#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 -#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 -#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 -#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 -#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 -#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 -#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 -#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 -#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 -#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 -#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 -#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 -#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 -#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 -#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 -#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 -#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 -#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 -#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 -#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 -#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 -#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 -#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 -#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 -#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 -#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 -#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 -#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 -#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 -#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 -#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 -#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 -#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 -#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 -#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 -#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 -#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 -#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 -#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 - -#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts deleted file mode 100644 index 92cb45dacda6..000000000000 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ /dev/null @@ -1,595 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * Copyright (C) 2019 reMarkable AS - http://www.remarkable.com/ - * - */ - -/dts-v1/; - -#include "imx7d.dtsi" -#include - -/ { - model = "reMarkable 2.0"; - compatible = "remarkable,imx7d-remarkable2", "fsl,imx7d"; - - chosen { - stdout-path = &uart6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - thermal-zones { - epd-thermal { - thermal-sensors = <&sy7636a>; - polling-delay-passive = <30000>; - polling-delay = <30000>; - - trips { - trip0 { - temperature = <49000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip1 { - temperature = <50000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <150>; - }; - - reg_digitizer: regulator-digitizer { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_DIGITIZER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_digitizer_reg>; - pinctrl-1 = <&pinctrl_digitizer_reg>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100000>; /* 100 ms */ - }; - - reg_touch: regulator-touch { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_TOUCH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_reg>; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi>; - reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <&buck1>; -}; - -&clks { - assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - wacom_digitizer: digitizer@9 { - compatible = "hid-over-i2c"; - reg = <0x09>; - hid-descr-addr = <0x01>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wacom>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - touchscreen-inverted-x; - touchscreen-inverted-y; - vdd-supply = <®_digitizer>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - bd71815: pmic@4b { - compatible = "rohm,bd71815"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bd71815>; - interrupt-parent = <&gpio6>; /* PMIC_INT_B GPIO6_IO16 */ - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - clocks = <&clks IMX7D_CLKO2_ROOT_SRC>; - clock-output-names = "bd71815-32k-out"; - #clock-cells = <0>; - #gpio-cells = <2>; - - regulators { - buck1: buck1 { - regulator-name = "buck1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2: buck2 { - regulator-name = "buck2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3: buck3 { - regulator-name = "buck3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2700000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4: buck4 { - regulator-name = "buck4"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: buck5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: ldo3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: ldo4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: ldo5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6: ldodvref { - regulator-name = "ldodvref"; - regulator-boot-on; - regulator-always-on; - }; - - ldo7: ldolpsr { - regulator-name = "ldolpsr"; - regulator-boot-on; - regulator-always-on; - }; - - boost: wled { - regulator-name = "wled"; - regulator-min-microamp = <10>; - regulator-max-microamp = <25000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@24 { - compatible = "cypress,tt21000"; - reg = <0x24>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - vdd-supply = <®_touch>; - touchscreen-size-x = <880>; - touchscreen-size-y = <1280>; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - reg = <0>; - linux,keycodes = ; - }; - - button@1 { - reg = <1>; - linux,keycodes = ; - }; - - button@2 { - reg = <2>; - linux,keycodes = ; - }; - - button@3 { - reg = <3>; - linux,keycodes = ; - }; - - button@4 { - reg = <4>; - linux,keycodes = ; - }; - - button@5 { - reg = <5>; - linux,keycodes = ; - }; - - button@6 { - reg = <6>; - linux,keycodes = ; - }; - - button@7 { - reg = <7>; - linux,keycodes = ; - }; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4>; - status = "okay"; - - sy7636a: pmic@62 { - compatible = "silergy,sy7636a"; - reg = <0x62>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epdpmic>; - #thermal-sensor-cells = <0>; - epd-pwr-good-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; - - regulators { - reg_epdpmic: vcom { - regulator-name = "vcom"; - regulator-boot-on; - }; - }; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&usbotg2 { - srp-disable; - hnp-disable; - status = "okay"; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - mmc-pwrseq = <&wifi_pwrseq>; - vmmc-supply = <®_brcm>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - cap-power-off-card; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc_lpsr { - pinctrl_digitizer_reg: digitizerreggrp { - fsl,pins = < - /* DIGITIZER_PWR_EN */ - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 - >; - }; - - pinctrl_wacom: wacomgrp { - fsl,pins = < - /*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */ - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */ - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */ - /*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */ - /*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */ - >; - }; -}; - -&iomuxc { - pinctrl_bd71815: bd71815grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x59 - >; - }; - - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - /* WIFI_PWR_EN */ - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x14 - >; - }; - - pinctrl_epdpmic: epdpmicgrp { - fsl,pins = < - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x00000074 - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x00000014 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - /* CYTTSP interrupt */ - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x54 - /* CYTTSP reset */ - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x04 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_touch_reg: touchreggrp { - fsl,pins = < - /* TOUCH_PWR_EN */ - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x14 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x74 - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - /* WiFi Reg On */ - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x00000014 - /* WiFi Sleep 32k */ - MX7D_PAD_SD1_WP__CCM_CLKO2 0x00000014 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-sbc-imx7.dts b/arch/arm/boot/dts/imx7d-sbc-imx7.dts deleted file mode 100644 index f8a868552707..000000000000 --- a/arch/arm/boot/dts/imx7d-sbc-imx7.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Support for CompuLab SBC-iMX7 Single Board Computer - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Ilya Ledvich - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - */ - -#include "imx7d-cl-som-imx7.dts" - -/ { - model = "CompuLab SBC-iMX7"; - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/imx7d-sdb-reva.dts deleted file mode 100644 index cabdaa6dc518..000000000000 --- a/arch/arm/boot/dts/imx7d-sdb-reva.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx7d-sdb.dts" - -/ { - model = "Freescale i.MX7 SabreSD RevA Board"; - compatible = "fsl,imx7d-sdb-reva", "fsl,imx7d"; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&fec2 { - /delete-property/phy-supply; -}; - -&iomuxc { - imx7d-sdb { - pinctrl_tsc2046_pendown: tsc2046_pendown { - fsl,pins = < - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ - >; - }; - - pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp { - fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-sdb-sht11.dts b/arch/arm/boot/dts/imx7d-sdb-sht11.dts deleted file mode 100644 index 996555596d40..000000000000 --- a/arch/arm/boot/dts/imx7d-sdb-sht11.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include "imx7d-sdb.dts" - -/ { - sensor { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensor>; - compatible = "sensirion,sht15"; - clk-gpios = <&gpio4 12 0>; - data-gpios = <&gpio4 13 0>; - vcc-supply = <®_sht15>; - }; - - reg_sht15: regulator-sht15 { - compatible = "regulator-fixed"; - regulator-name = "reg_sht15"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&i2c3 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_sensor: sensorgrp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts deleted file mode 100644 index cc9b8570ed4d..000000000000 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ /dev/null @@ -1,904 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "Freescale i.MX7 SabreSD Board"; - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - spi-4 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - extended_io: gpio-expander@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - }; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VDD_SD1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <200000>; - off-on-delay-us = <20000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "brcm_reg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; - }; - - reg_fec2_3v3: regulator-fec2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec2-3v3"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx7d-evk-wm8960", - "fsl,imx-audio-wm8960"; - model = "wm8960-audio"; - audio-cpu = <&sai1>; - audio-codec = <&codec>; - hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; - audio-routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "AMIC", - "AMIC", "MICB"; - }; - - sound-hdmi { - compatible = "fsl,imx-audio-sii902x"; - model = "sii902x-audio"; - audio-cpu = <&sai3>; - hdmi-out; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&cpu1 { - cpu-supply = <&sw1a_reg>; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - tsc2046@0 { - compatible = "ti,tsc2046"; - reg = <0>; - spi-max-frequency = <1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2046_pendown>; - interrupt-parent = <&gpio2>; - interrupts = <29 0>; - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - touchscreen-max-pressure = <255>; - wakeup-source; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_fec2_3v3>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - clock-names = "mclk"; - wlf,shared-lrclk; - wlf,hp-cfg = <2 2 3>; - wlf,gpio-cfg = <1 3>; - assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, - <&clks IMX7D_PLL_AUDIO_POST_DIV>, - <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <884736000>, <12288000>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pcie { - reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -®_1p0d { - vin-supply = <&sw2_reg>; -}; - -®_1p2 { - vin-supply = <&sw2_reg>; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_PLL_AUDIO_POST_DIV>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <884736000>, <36864000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; - assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, - <&clks IMX7D_PLL_AUDIO_POST_DIV>, - <&clks IMX7D_SAI3_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <884736000>, <36864000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_sd1_vmmc>; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - wakeup-source; - keep-power-in-suspend; - non-removable; - vmmc-supply = <®_brcm>; - fsl,tuning-step = <2>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx7d-sdb { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 - MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 - MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2_reg: enet2reggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX7D_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f - MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f - MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 - MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f - MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f - MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 - >; - }; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 - >; - }; - - pinctrl_tsc2046_pendown: tsc2046_pendown { - fsl,pins = < - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 - MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1_gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b - >; - }; - - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&iomuxc_lpsr { - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 - >; - }; - - pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 - >; - }; - - pinctrl_sai3_mclk: sai3grp_mclk { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts deleted file mode 100644 index 85b97b5f64e7..000000000000 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ /dev/null @@ -1,468 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright (C) 2020 PHYTEC Messtechnik GmbH -// Author: Jens Lang -// Copyright (C) 2021 Fabio Estevam - -/dts-v1/; -#include -#include "imx7d.dtsi" - -/ { - model = "Storopack SMEGW01 board"; - compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; - - aliases { - ethernet0 = &fec1; - ethernet1 = &fec2; - mmc0 = &usdhc1; - mmc1 = &usdhc3; - mmc2 = &usdhc2; - rtc0 = &i2c_rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_lte_on: regulator-lte-on { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lte_on>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "lte_on"; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_lte_nreset: regulator-lte-nreset { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lte_nreset>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "LTE_nReset"; - gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi>; - regulator-name = "wifi_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_wlan_rfkill: regulator-wlan-rfkill { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rfkill>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "wlan_rfkill"; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - sram@0 { - compatible = "microchip,48l640"; - reg = <0>; - spi-max-frequency = <16000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - - ethphy1: ethernet-phy@2 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - reg = <2>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - i2c_rtc: rtc@52 { - compatible = "microcrystal,rv3028"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - reg = <0x52>; - interrupt-parent = <&gpio2>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_lpsr>; - dr_mode = "otg"; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - over-current-active-low; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - vmmc-supply = <®_wifi>; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - max-frequency = <200000000>; - bus-width = <8>; - fsl,tuning-step = <1>; - non-removable; - cap-mmc-highspeed; - cap-mmc-hw-reset; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04 - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04 - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04 - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004 - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0 - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0 - >; - }; - - pinctrl_lte_on: lteongrp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059 - >; - }; - - pinctrl_lte_nreset: ltenresetgrp { - fsl,pins = < - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059 - >; - }; - - pinctrl_rfkill: rfkillgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74 - >; - }; - - pinctrl_usbotg1_lpsr: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 - >; - }; - - pinctrl_usbotg1_pwr: usbotg1-pwrgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 - >; - }; - - pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5d - MX7D_PAD_SD3_CLK__SD3_CLK 0x1d - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5e - MX7D_PAD_SD3_CLK__SD3_CLK 0x1e - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5f - MX7D_PAD_SD3_CLK__SD3_CLK 0x0f - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04 - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi deleted file mode 100644 index 3ee2017c1ab3..000000000000 --- a/arch/arm/boot/dts/imx7d-tqma7.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ-Systems TQMa7D board with NXP i.MX7Dual SoC. - * - * Copyright (C) 2016 TQ-Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -#include "imx7d.dtsi" -#include "imx7-tqma7.dtsi" - -&cpu1 { - cpu-supply = <&sw1a_reg>; -}; diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts deleted file mode 100644 index 521493342fe9..000000000000 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device tree file for ZII's RMU2 board - * - * RMU - Remote Modem Unit - * - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include -#include "imx7d.dtsi" - -/ { - model = "ZII RMU2 Board"; - compatible = "zii,imx7d-rmu2", "fsl,imx7d"; - - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <&fec1_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - fec1_phy: ethernet-phy@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1_phy_reset>, - <&pinctrl_enet1_phy_interrupt>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - no-sdio; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet1_phy_reset: enet1phyresetgrp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 - - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_leds_debug: ledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 - >; - }; - - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 - MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp { - fsl,phy = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts deleted file mode 100644 index decc19af3b83..000000000000 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ /dev/null @@ -1,923 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device tree file for ZII's RPU2 board - * - * RPU - Remote Peripheral Unit - * - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include -#include "imx7d.dtsi" - -/ { - model = "ZII RPU2 Board"; - compatible = "zii,imx7d-rpu2", "fsl,imx7d"; - - chosen { - stdout-path = &uart2; - }; - - cs2000_ref: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - cs2000_in_dummy: dummy-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, - <&adc2 1>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_stby>; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_stby>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v_main: regulator-5p0v-main { - compatible = "regulator-fixed"; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Audio Output 1"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound1_codec>; - simple-audio-card,frame-master = <&sound1_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa1>; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - sound1_codec: simple-audio-card,codec { - sound-dai = <&codec1>; - clocks = <&cs2000>; - }; - }; - - sound2 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Audio Output 2"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound2_codec>; - simple-audio-card,frame-master = <&sound2_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa2>; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - sound2_codec: simple-audio-card,codec { - sound-dai = <&codec2>; - clocks = <&cs2000>; - }; - }; - - sound3 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Audio Output 3"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound3_codec>; - simple-audio-card,frame-master = <&sound3_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa3>; - - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - - sound3_codec: simple-audio-card,codec { - sound-dai = <&codec3>; - clocks = <&cs2000>; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&clks { - assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <884736000>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - reg = <0>; - eeprom-length = <512>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "eth_cu_1000_1"; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_2"; - }; - - port@2 { - reg = <2>; - label = "pic"; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec1>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - label = "gigabit_proc"; - ethernet = <&fec2>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - fsl,magic-packet; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", - "usb_1_en_b", - "usb_2_en_b", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", ""; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio2>; - - gpio-line-names = "12v_out_en_1", - "12v_out_en_2", - "12v_out_en_3", - "28v_out_en_5", - "28v_out_en_1", - "28v_out_en_2", - "28v_out_en_3", - "28v_out_en_4", - "", "", - "usb_3_en_b", - "usb_4_en_b", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - cs2000: clkgen@4e { - compatible = "cirrus,cs2000-cp"; - reg = <0x4e>; - #clock-cells = <0>; - clock-names = "clk_in", "ref_clk"; - clocks = <&cs2000_in_dummy>, <&cs2000_ref>; - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24000000>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec2: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec2>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hpa2: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa2>; - reg = <0x60>; - power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec3: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec3>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hpa3: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa3>; - reg = <0x60>; - power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec1: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec1>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hpa1: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa1>; - reg = <0x60>; - power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, - <&clks IMX7D_SAI2_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, - <&clks IMX7D_SAI3_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - no-sdio; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 - MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 - >; - }; - - pinctrl_flexcan1_stby: flexcan1stbygrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_flexcan2_stby: flexcan2stbygrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00 - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00 - >; - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00 - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00 - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00 - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03 - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03 - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03 - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03 - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03 - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00 - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f - >; - }; - - pinctrl_leds_debug: debuggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f - MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f - MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f - MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f - MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 - >; - }; - - pinctrl_tpa1: tpa6130-1grp { - fsl,pins = < - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038 - >; - }; - - pinctrl_tpa2: tpa6130-2grp { - fsl,pins = < - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038 - >; - }; - - pinctrl_tpa3: tpa6130-3grp { - fsl,pins = < - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 - MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_codec1: dac1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038 - >; - }; - - pinctrl_codec2: dac2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038 - >; - }; - - pinctrl_codec3: dac3grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038 - >; - }; - - pinctrl_switch: switchgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi deleted file mode 100644 index 4b94b8afb55d..000000000000 --- a/arch/arm/boot/dts/imx7d.dtsi +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Freescale Semiconductor, Inc. -// Copyright 2016 Toradex AG - -#include "imx7s.dtsi" -#include - -/ { - aliases { - usb0 = &usbotg1; - usb1 = &usbotg2; - usb2 = &usbh; - }; - - cpus { - cpu0: cpu@0 { - clock-frequency = <996000000>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&fuse_grade>; - nvmem-cell-names = "speed_grade"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <996000000>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_sleep_wait>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0xd>, <0x7>; - opp-suspend; - }; - - opp-996000000 { - opp-hz = /bits/ 64 <996000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0xc>, <0x7>; - opp-suspend; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0x8>, <0x3>; - opp-suspend; - }; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - soc: soc { - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; - - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; - }; - }; - }; - }; - - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x31001000 0x1000>, - <0x31002000 0x2000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - - pcie: pcie@33800000 { - compatible = "fsl,imx7d-pcie"; - reg = <0x33800000 0x4000>, - <0x4ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ - <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - /* - * Reference manual lists pci irqs incorrectly - * Real hardware ordering is same as imx6: D+MSI, C, B, A - */ - interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, - <&clks IMX7D_PCIE_PHY_ROOT_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, - <&clks IMX7D_PCIE_PHY_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie_phy>; - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - fsl,imx7d-pcie-phy = <&pcie_phy>; - status = "disabled"; - }; - }; -}; - -&aips2 { - pcie_phy: pcie-phy@306d0000 { - compatible = "fsl,imx7d-pcie-phy"; - reg = <0x306d0000 0x10000>; - status = "disabled"; - }; - - pxp: pxp@30700000 { - compatible = "fsl,imx7d-pxp"; - reg = <0x30700000 0x10000>; - interrupts = , - ; - clocks = <&clks IMX7D_PXP_CLK>; - clock-names = "axi"; - }; -}; - -&aips3 { - usbotg2: usb@30b20000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b20000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc2: usbmisc@30b20200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b20200 0x200>; - }; - - fec2: ethernet@30bf0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30bf0000 0x10000>; - interrupt-names = "int0", "int1", "int2", "pps"; - interrupts = , - , - , - ; - clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - fsl,stop-mode = <&gpr 0x10 4>; - status = "disabled"; - }; -}; - -&ca_funnel_in_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - ca_funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts deleted file mode 100644 index 58ebb02d948a..000000000000 --- a/arch/arm/boot/dts/imx7s-colibri-aster.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017-2022 Toradex - * - */ - -/dts-v1/; -#include "imx7s-colibri.dtsi" -#include "imx7-colibri-aster.dtsi" - -/ { - model = "Toradex Colibri iMX7S on Aster Carrier Board"; - compatible = "toradex,colibri-imx7s-aster", - "toradex,colibri-imx7s", - "fsl,imx7s"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts deleted file mode 100644 index 38de76630d6a..000000000000 --- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016-2022 Toradex - */ - -/dts-v1/; -#include "imx7s-colibri.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7s-eval-v3", - "toradex,colibri-imx7s", - "fsl,imx7s"; -}; - -&ad7879_ts { - status = "okay"; -}; - -/* - * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. - * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. - */ -&atmel_mxt_ts { - status = "disabled"; -}; - -&backlight { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts deleted file mode 100644 index 72b5c17ab1ab..000000000000 --- a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; -#include "imx7s-colibri.dtsi" -#include "imx7-colibri-iris-v2.dtsi" - -/ { - model = "Toradex Colibri iMX7S on Iris V2 Carrier Board"; - compatible = "toradex,colibri-imx7s-iris-v2", - "toradex,colibri-imx7s", - "fsl,imx7s"; -}; - -&ad7879_ts { - status = "okay"; -}; - -&atmel_mxt_ts { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&gpio2 { - /* - * This switches the LVDS transceiver to VESA color mapping mode. - */ - lvds-color-map-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ - line-name = "LVDS_COLOR_MAP"; - output-low; - }; -}; - -&gpio7 { - /* - * This switches the LVDS transceiver to the 24-bit RGB mode. - */ - lvds-rgb-mode-hog { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ - line-name = "LVDS_RGB_MODE"; - output-low; - }; - - /* - * This switches the LVDS transceiver to the single-channel - * output mode. - */ - lvds-ch-mode-hog { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ - line-name = "LVDS_CH_MODE"; - output-high; - }; - - /* This turns the LVDS transceiver on */ - lvds-power-on-hog { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ - line-name = "LVDS_POWER_ON"; - output-high; - }; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/imx7s-colibri-iris.dts deleted file mode 100644 index 26ba72c17feb..000000000000 --- a/arch/arm/boot/dts/imx7s-colibri-iris.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; -#include "imx7s-colibri.dtsi" -#include "imx7-colibri-iris.dtsi" - -/ { - model = "Toradex Colibri iMX7S on Iris Carrier Board"; - compatible = "toradex,colibri-imx7s-iris", - "toradex,colibri-imx7s", - "fsl,imx7s"; -}; - -&ad7879_ts { - status = "okay"; -}; - -/* - * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. - * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. - */ -&atmel_mxt_ts { - status = "disabled"; -}; - -&backlight { - status = "okay"; -}; - -&lcdif { - status = "okay"; -}; - -&panel_dpi { - status = "okay"; -}; - -/* Colibri PWM */ -&pwm2 { - /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; - -/* Colibri PWM */ -&pwm3 { - /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi deleted file mode 100644 index ef51395d3537..000000000000 --- a/arch/arm/boot/dts/imx7s-colibri.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016-2022 Toradex - */ - -#include "imx7s.dtsi" -#include "imx7-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -/* NAND */ -&gpmi { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts deleted file mode 100644 index 8e4cf589c92c..000000000000 --- a/arch/arm/boot/dts/imx7s-mba7.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Source for TQ-Systems TQMa7S board on MBa7 carrier board. - * - * Copyright (C) 2016 TQ-Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -/dts-v1/; - -#include "imx7s-tqma7.dtsi" -#include "imx7-mba7.dtsi" - -/ { - model = "TQ-Systems TQMa7S board on MBa7 carrier board"; - compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; -}; diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/imx7s-tqma7.dtsi deleted file mode 100644 index 7a190fdb2d30..000000000000 --- a/arch/arm/boot/dts/imx7s-tqma7.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ-Systems TQMa7S board with NXP i.MX7Solo SoC. - * - * Copyright (C) 2016 TQ-Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -#include "imx7s.dtsi" -#include "imx7-tqma7.dtsi" diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts deleted file mode 100644 index ba7231b364bb..000000000000 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ /dev/null @@ -1,500 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 NXP Semiconductors. - * Author: Fabio Estevam - */ - -/dts-v1/; - -#include -#include "imx7s.dtsi" - -/ { - model = "Element14 Warp i.MX7 Board"; - compatible = "element14,imx7s-warp", "fsl,imx7s"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_gpio>; - autorepeat; - - back { - label = "Back"; - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - reg_bt: regulator-bt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - enable-active-high; - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - regulator-name = "bt_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_peri_3p15v: regulator-peri-3p15v { - compatible = "regulator-fixed"; - regulator-name = "peri_3p15v_reg"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <884736000>; -}; - -&csi { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ov2680: camera@36 { - compatible = "ovti,ov2680"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov2680>; - reg = <0x36>; - clocks = <&osc>; - clock-names = "xvclk"; - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - DOVDD-supply = <&sw2_reg>; - DVDD-supply = <&sw2_reg>; - AVDD-supply = <®_peri_3p15v>; - - port { - ov2680_to_mipi: endpoint { - remote-endpoint = <&mipi_from_sensor>; - clock-lanes = <0>; - data-lanes = <1>; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1_mclk>; - VDDA-supply = <&vgen4_reg>; - VDDIO-supply = <&vgen4_reg>; - VDDD-supply = <&vgen2_reg>; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&mipi_csi { - clock-frequency = <166000000>; - status = "okay"; - - ports { - port@0 { - reg = <0>; - - mipi_from_sensor: endpoint { - remote-endpoint = <&ov2680_to_mipi>; - data-lanes = <1>; - }; - }; - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - fsl,dte-mode; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - no-1-8-v; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&video_mux { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ - >; - }; - - pinctrl_bt_reg: btreggrp { - fsl,pins = < - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - >; - }; - - pinctrl_ov2680: ov2660grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 - >; - }; - - pinctrl_sai1_mclk: sai1mclkgrp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi deleted file mode 100644 index 54026c2c93fa..000000000000 --- a/arch/arm/boot/dts/imx7s.dtsi +++ /dev/null @@ -1,1290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Freescale Semiconductor, Inc. -// Copyright 2016 Toradex AG - -#include -#include -#include -#include -#include -#include -#include "imx7d-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usb0 = &usbotg1; - usb1 = &usbh; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_sleep_wait: cpu-sleep-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <50>; - min-residency-us = <1000>; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <792000000>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX7D_CLK_ARM>; - cpu-idle-states = <&cpu_sleep_wait>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&fuse_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0xf>, <0xf>; - }; - }; - - ckil: clock-cki { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - power-domains = <&pgc_hsic_phy>; - #phy-cells = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gpc>; - interrupts = ; - interrupt-affinity = <&cpu0>; - }; - - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - funnel@30041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ca_funnel_in_ports: in-ports { - port { - ca_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - - out-ports { - port { - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - - }; - }; - - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; - }; - }; - }; - - funnel@30083000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - /* M4 input */ - }; - }; - /* the other input ports are not connect to anything */ - }; - - out-ports { - port { - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - }; - }; - - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etf_in_port: endpoint { - remote-endpoint = <&hugo_funnel_out_port0>; - }; - }; - }; - - out-ports { - port { - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x31001000 0x1000>, - <0x31002000 0x2000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30000000 0x400000>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , /* GPIO1_INT15_0 */ - ; /* GPIO1_INT31_16 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 13 32>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 45 29>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 74 24>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 98 18>; - }; - - gpio6: gpio@30250000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30250000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 116 23>; - }; - - gpio7: gpio@30260000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30260000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 139 16>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; - status = "disabled"; - }; - - wdog4: watchdog@302b0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc_lpsr: pinctrl@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - }; - - gpt1: timer@302d0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302d0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT1_ROOT_CLK>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@302e0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302e0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT2_ROOT_CLK>, - <&clks IMX7D_GPT2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt3: timer@302f0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302f0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT3_ROOT_CLK>, - <&clks IMX7D_GPT3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: timer@30300000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x30300000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT4_ROOT_CLK>, - <&clks IMX7D_GPT4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - kpp: keypad@30320000 { - compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; - reg = <0x30320000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_KPP_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon", - "simple-mfd"; - reg = <0x30340000 0x10000>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x14 0x00000010>; - }; - - video_mux: csi-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - csi_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_csi_mux>; - }; - }; - - port@2 { - reg = <2>; - - csi_mux_to_csi: endpoint { - remote-endpoint = <&csi_from_csi_mux>; - }; - }; - }; - }; - - ocotp: efuse@30350000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx7d-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clks IMX7D_OCOTP_CLK>; - - tempmon_calib: calib@3c { - reg = <0x3c 0x4>; - }; - - fuse_grade: fuse-grade@10 { - reg = <0x10 0x4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x30360000 0x10000>; - interrupts = , - ; - - reg_1p0d: regulator-vdd1p0d { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p0d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - anatop-reg-offset = <0x210>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <8>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1200000>; - anatop-enable-bit = <0>; - }; - - reg_1p2: regulator-vdd1p2 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - anatop-reg-offset = <0x220>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0x14>; - anatop-min-voltage = <1100000>; - anatop-max-voltage = <1300000>; - anatop-enable-bit = <0>; - }; - - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&fuse_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; - }; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-pwrkey"; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clks: clock-controller@30380000 { - compatible = "fsl,imx7d-ccm"; - reg = <0x30380000 0x10000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>; - clock-names = "ckil", "osc"; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx7d-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx7d-gpc"; - reg = <0x303a0000 0x10000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - #power-domain-cells = <1>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_mipi_phy: power-domain@0 { - #power-domain-cells = <0>; - reg = <0>; - power-supply = <®_1p0d>; - }; - - pgc_pcie_phy: power-domain@1 { - #power-domain-cells = <0>; - reg = <1>; - power-supply = <®_1p0d>; - }; - - pgc_hsic_phy: power-domain@2 { - #power-domain-cells = <0>; - reg = <2>; - power-supply = <®_1p2>; - }; - }; - }; - }; - - aips2: bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30400000 0x400000>; - ranges; - - adc1: adc@30610000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30610000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - adc2: adc@30620000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30620000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - ecspi4: spi@30630000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30630000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, - <&clks IMX7D_ECSPI4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ftm1: pwm@30640000 { - compatible = "fsl,vf610-ftm-pwm"; - reg = <0x30640000 0x10000>; - #pwm-cells = <3>; - interrupts = ; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, - <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, - <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, - <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; - status = "disabled"; - }; - - ftm2: pwm@30650000 { - compatible = "fsl,vf610-ftm-pwm"; - reg = <0x30650000 0x10000>; - #pwm-cells = <3>; - interrupts = ; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, - <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, - <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, - <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; - status = "disabled"; - }; - - pwm1: pwm@30660000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM1_ROOT_CLK>, - <&clks IMX7D_PWM1_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM2_ROOT_CLK>, - <&clks IMX7D_PWM2_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM3_ROOT_CLK>, - <&clks IMX7D_PWM3_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM4_ROOT_CLK>, - <&clks IMX7D_PWM4_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - csi: csi@30710000 { - compatible = "fsl,imx7-csi"; - reg = <0x30710000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CSI_MCLK_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "axi", "mclk", "dcic"; - status = "disabled"; - - port { - csi_from_csi_mux: endpoint { - remote-endpoint = <&csi_mux_to_csi>; - }; - }; - }; - - lcdif: lcdif@30730000 { - compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; - reg = <0x30730000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; - status = "disabled"; - }; - - mipi_csi: mipi-csi@30750000 { - compatible = "fsl,imx7-mipi-csi2"; - reg = <0x30750000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_MIPI_CSI_ROOT_CLK>, - <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; - clock-names = "pclk", "wrap", "phy"; - power-domains = <&pgc_mipi_phy>; - phy-supply = <®_1p0d>; - resets = <&src IMX7_RESET_MIPI_PHY_MRST>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - mipi_vc0_to_csi_mux: endpoint { - remote-endpoint = <&csi_mux_from_mipi_vc0>; - }; - }; - }; - }; - }; - - aips3: bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x400000>; - ranges; - - spba-bus@30800000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x100000>; - ranges; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai1: sai@308a0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI1_IPG_CLK>, - <&clks IMX7D_SAI1_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI2_IPG_CLK>, - <&clks IMX7D_SAI2_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI3_IPG_CLK>, - <&clks IMX7D_SAI3_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; - status = "disabled"; - }; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clks IMX7D_CAAM_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; - clock-names = "ipg", "aclk"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - flexcan1: can@30a00000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a00000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN1_ROOT_CLK>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1>; - status = "disabled"; - }; - - flexcan2: can@30a10000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a10000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN2_ROOT_CLK>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C1_ROOT_CLK>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C2_ROOT_CLK>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C3_ROOT_CLK>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C4_ROOT_CLK>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART4_ROOT_CLK>, - <&clks IMX7D_UART4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@30a70000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a70000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART5_ROOT_CLK>, - <&clks IMX7D_UART5_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@30a80000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a80000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART6_ROOT_CLK>, - <&clks IMX7D_UART6_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart7: serial@30a90000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a90000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART7_ROOT_CLK>, - <&clks IMX7D_UART7_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - mu0a: mailbox@30aa0000 { - compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_MU_ROOT_CLK>; - #mbox-cells = <2>; - status = "disabled"; - }; - - mu0b: mailbox@30ab0000 { - compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; - reg = <0x30ab0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_MU_ROOT_CLK>; - #mbox-cells = <2>; - fsl,mu-side-b; - status = "disabled"; - }; - - usbotg1: usb@30b10000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b10000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbh: usb@30b30000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b30000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop3>; - fsl,usbmisc = <&usbmisc3 0>; - phy_type = "hsic"; - dr_mode = "host"; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc1: usbmisc@30b10200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b10200 0x200>; - }; - - usbmisc3: usbmisc@30b30200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b30200 0x200>; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, - <&clks IMX7D_USDHC1_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, - <&clks IMX7D_USDHC2_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@30b60000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, - <&clks IMX7D_USDHC3_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - qspi: spi@30bb0000 { - compatible = "fsl,imx7d-qspi"; - reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clks IMX7D_QSPI_ROOT_CLK>, - <&clks IMX7D_QSPI_ROOT_CLK>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - sdma: dma-controller@30bd0000 { - compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_SDMA_CORE_CLK>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupt-names = "int0", "int1", "int2", "pps"; - interrupts = , - , - , - ; - clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - fsl,stop-mode = <&gpr 0x10 3>; - status = "disabled"; - }; - }; - - dma_apbh: dma-controller@33000000 { - compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x33000000 0x2000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; - }; - - gpmi: nand-controller@33002000{ - compatible = "fsl,imx7d-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x33002000 0x2000>, <0x33004000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; - clock-names = "gpmi_io", "gpmi_bch_apb"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx7ulp-com.dts b/arch/arm/boot/dts/imx7ulp-com.dts deleted file mode 100644 index d76fea3b35c6..000000000000 --- a/arch/arm/boot/dts/imx7ulp-com.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2019 NXP - -/dts-v1/; - -#include "imx7ulp.dtsi" -#include - -/ { - model = "Embedded Artists i.MX7ULP COM"; - compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; - - chosen { - stdout-path = &lpuart4; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x4000000>; - }; -}; - -&lpuart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0>; - non-removable; - bus-width = <8>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc1 { - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 - IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 - IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 - IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 - IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts deleted file mode 100644 index eff51e113db4..000000000000 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng - */ - -/dts-v1/; - -#include "imx7ulp.dtsi" - -/ { - model = "NXP i.MX7ULP EVK"; - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; - - chosen { - stdout-path = &lpuart4; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpm4 1 50000 0>; - brightness-levels = <0 20 25 30 35 40 100>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vsd_3v3: regulator-vsd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0_rst>; - gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&lpuart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart4>; - status = "okay"; -}; - -&tpm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - disable-over-current; - status = "okay"; -}; - -&usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_vsd_3v3>; - status = "okay"; -}; - -&iomuxc1 { - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - bias-pull-up; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 - >; - }; - - pinctrl_usbotg1_vbus: otg1vbusgrp { - fsl,pins = < - IMX7ULP_PAD_PTC0__PTC0 0x20000 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ - >; - }; - - pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { - fsl,pins = < - IMX7ULP_PAD_PTD0__PTD0 0x3 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h deleted file mode 100644 index c0148d79b62d..000000000000 --- a/arch/arm/boot/dts/imx7ulp-pinfunc.h +++ /dev/null @@ -1,478 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX7ULP_PINFUNC_H -#define __DTS_IMX7ULP_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 -#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 -#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 -#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 -#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 -#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 -#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 -#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 -#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 -#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 -#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 -#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 -#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 -#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 -#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 -#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 -#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 -#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 -#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 -#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 -#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 -#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 -#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 -#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 -#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 -#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 -#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 -#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 -#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 -#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 -#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 -#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 -#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 -#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 -#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 -#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 -#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 -#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 -#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 -#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 -#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 -#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 -#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 -#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 -#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 -#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 -#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 -#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 -#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 -#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 -#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 -#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 -#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 -#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 -#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 -#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 -#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 -#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 -#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 -#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 -#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 -#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 -#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 -#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 -#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 -#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 -#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 -#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 -#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 -#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 -#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 -#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 -#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 -#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 -#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 -#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 -#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 -#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 -#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 -#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 -#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 -#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 -#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 -#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 -#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 -#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 -#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 -#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 -#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 -#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 -#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 -#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 -#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 -#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 -#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 -#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 -#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 -#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 -#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 -#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 -#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 -#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 -#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 -#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 -#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 -#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 -#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 -#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 -#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 -#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 -#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 -#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 -#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 -#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 -#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 -#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 -#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 -#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 -#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 -#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 -#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 -#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 -#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 -#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 -#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 -#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 -#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 -#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 -#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 -#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 -#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 -#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 -#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 -#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 -#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 -#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 -#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 -#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 -#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 -#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 -#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 -#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 -#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 -#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 -#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 -#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 -#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 -#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 -#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 -#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 -#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 -#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 -#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 -#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 -#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 -#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 -#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 -#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 -#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 -#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 -#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 -#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 -#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 -#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 -#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 -#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 -#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 -#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 -#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 -#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 -#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 -#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 -#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 -#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 -#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 -#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 -#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 -#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 -#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 -#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 -#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 -#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 -#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 -#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 -#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 -#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 -#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 -#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 -#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 -#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 -#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 -#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 -#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 -#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 -#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 -#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 -#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 -#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 -#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 -#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 -#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 -#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 -#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 -#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 -#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 -#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 -#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 -#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 -#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 -#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 -#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 -#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 -#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 -#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 -#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 -#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 -#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 -#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 -#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 - -#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi deleted file mode 100644 index b01ddda7bd9e..000000000000 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng - */ - -#include -#include -#include - -#include "imx7ulp-pinfunc.h" - -/ { - interrupt-parent = <&intc>; - - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio_ptc; - gpio1 = &gpio_ptd; - gpio2 = &gpio_pte; - gpio3 = &gpio_ptf; - i2c0 = &lpi2c6; - i2c1 = &lpi2c7; - mmc0 = &usdhc0; - mmc1 = &usdhc1; - serial0 = &lpuart4; - serial1 = &lpuart5; - serial2 = &lpuart6; - serial3 = &lpuart7; - usbphy0 = &usbphy1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - }; - }; - - intc: interrupt-controller@40021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x40021000 0x1000>, - <0x40022000 0x1000>; - }; - - rosc: clock-rosc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "rosc"; - #clock-cells = <0>; - }; - - sosc: clock-sosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "sosc"; - #clock-cells = <0>; - }; - - sirc: clock-sirc { - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "sirc"; - #clock-cells = <0>; - }; - - firc: clock-firc { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - clock-output-names = "firc"; - #clock-cells = <0>; - }; - - upll: clock-upll { - compatible = "fixed-clock"; - clock-frequency = <480000000>; - clock-output-names = "upll"; - #clock-cells = <0>; - }; - - ahbbridge0: bus@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x800000>; - ranges; - - edma1: dma-controller@40080000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x40080000 0x2000>, - <0x40210000 0x1000>; - dma-channels = <32>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clock-names = "dma", "dmamux0"; - clocks = <&pcc2 IMX7ULP_CLK_DMA1>, - <&pcc2 IMX7ULP_CLK_DMA_MUX1>; - }; - - crypto: crypto@40240000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40240000 0x10000>; - ranges = <0 0x40240000 0x10000>; - clocks = <&pcc2 IMX7ULP_CLK_CAAM>, - <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - lpuart4: serial@402d0000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402d0000 0x1000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; - clock-names = "ipg"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - assigned-clock-rates = <24000000>; - status = "disabled"; - }; - - lpuart5: serial@402e0000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402e0000 0x1000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - clock-names = "ipg"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - tpm4: pwm@40250000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x40250000 0x1000>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = ; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&pcc2 IMX7ULP_CLK_LPTPM5>; - clock-names = "ipg", "per"; - }; - - usbotg1: usb@40330000 { - compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x40330000 0x200>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_USB0>; - phys = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc1: usbmisc@40330200 { - compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - #index-cells = <1>; - reg = <0x40330200 0x200>; - }; - - usbphy1: usb-phy@40350000 { - compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; - reg = <0x40350000 0x1000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; - #phy-cells = <0>; - }; - - usdhc0: mmc@40370000 { - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x40370000 0x10000>; - interrupts = ; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC0>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - usdhc1: mmc@40380000 { - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x40380000 0x10000>; - interrupts = ; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - scg1: clock-controller@403e0000 { - compatible = "fsl,imx7ulp-scg1"; - reg = <0x403e0000 0x10000>; - clocks = <&rosc>, <&sosc>, <&sirc>, - <&firc>, <&upll>; - clock-names = "rosc", "sosc", "sirc", - "firc", "upll"; - #clock-cells = <1>; - }; - - wdog1: watchdog@403d0000 { - compatible = "fsl,imx7ulp-wdt"; - reg = <0x403d0000 0x10000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; - timeout-sec = <40>; - }; - - pcc2: clock-controller@403f0000 { - compatible = "fsl,imx7ulp-pcc2"; - reg = <0x403f0000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", - "firc_bus_clk", "rosc", "spll_bus_clk"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - }; - - smc1: clock-controller@40410000 { - compatible = "fsl,imx7ulp-smc1"; - reg = <0x40410000 0x1000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, - <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; - clock-names = "divcore", "hsrun_divcore"; - }; - - pcc3: clock-controller@40b30000 { - compatible = "fsl,imx7ulp-pcc3"; - reg = <0x40b30000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", - "firc_bus_clk", "rosc", "spll_bus_clk"; - }; - }; - - ahbbridge1: bus@40800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40800000 0x800000>; - ranges; - - lpi2c6: i2c@40a40000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40a40000 0x10000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>, - <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; - clock-names = "per", "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpi2c7: i2c@40a50000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40a50000 0x10000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>, - <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; - clock-names = "per", "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart6: serial@40a60000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40a60000 0x1000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart7: serial@40a70000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40a70000 0x1000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - memory-controller@40ab0000 { - compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; - reg = <0x40ab0000 0x1000>; - clocks = <&pcc3 IMX7ULP_CLK_MMDC>; - }; - - iomuxc1: pinctrl@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc1"; - reg = <0x40ac0000 0x1000>; - }; - - gpio_ptc: gpio@40ae0000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40ae0000 0x1000 0x400f0000 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLC>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 0 20>; - }; - - gpio_ptd: gpio@40af0000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40af0000 0x1000 0x400f0040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLD>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 32 12>; - }; - - gpio_pte: gpio@40b00000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40b00000 0x1000 0x400f0080 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 64 16>; - }; - - gpio_ptf: gpio@40b10000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40b10000 0x1000 0x400f00c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLF>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 96 20>; - }; - }; - - m4aips1: bus@41080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x41080000 0x80000>; - ranges; - - sim: sim@410a3000 { - compatible = "fsl,imx7ulp-sim", "syscon"; - reg = <0x410a3000 0x1000>; - }; - - ocotp: efuse@410a6000 { - compatible = "fsl,imx7ulp-ocotp", "syscon"; - reg = <0x410a6000 0x4000>; - clocks = <&scg1 IMX7ULP_CLK_DUMMY>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts deleted file mode 100644 index 6a9c10decf52..000000000000 --- a/arch/arm/boot/dts/imxrt1050-evk.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -/dts-v1/; -#include "imxrt1050.dtsi" -#include "imxrt1050-pinfunc.h" - -/ { - model = "NXP IMXRT1050-evk board"; - compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; - - chosen { - stdout-path = &lpuart1; - }; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - mmc0 = &usdhc1; - serial0 = &lpuart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x2000000>; - }; -}; - -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 - >; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc0>; - pinctrl-1 = <&pinctrl_usdhc0>; - pinctrl-2 = <&pinctrl_usdhc0>; - pinctrl-3 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imxrt1050-pinfunc.h b/arch/arm/boot/dts/imxrt1050-pinfunc.h deleted file mode 100644 index 22c14a3262ad..000000000000 --- a/arch/arm/boot/dts/imxrt1050-pinfunc.h +++ /dev/null @@ -1,993 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H -#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H - -#define IMX_PAD_SION 0x40000000 - -/* - * The pin function ID is a tuple of - * - */ - -#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 -#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 -#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 - -#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 - -#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 - -#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 - -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi deleted file mode 100644 index 852861558b47..000000000000 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -#include "armv7-m.dtsi" -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - osc3M: osc3M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3000000>; - }; - }; - - soc { - lpuart1: serial@40184000 { - compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x40184000 0x4000>; - interrupts = <20>; - clocks = <&clks IMXRT1050_CLK_LPUART1>; - clock-names = "ipg"; - status = "disabled"; - }; - - iomuxc: pinctrl@401f8000 { - compatible = "fsl,imxrt1050-iomuxc"; - reg = <0x401f8000 0x4000>; - fsl,mux_mask = <0x7>; - }; - - anatop: anatop@400d8000 { - compatible = "fsl,imxrt-anatop"; - reg = <0x400d8000 0x4000>; - }; - - clks: clock-controller@400fc000 { - compatible = "fsl,imxrt1050-ccm"; - reg = <0x400fc000 0x4000>; - interrupts = <95>, <96>; - clocks = <&osc>; - clock-names = "osc"; - #clock-cells = <1>; - assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, - <&clks IMXRT1050_CLK_PLL1_BYPASS>, - <&clks IMXRT1050_CLK_PLL2_BYPASS>, - <&clks IMXRT1050_CLK_PLL3_BYPASS>, - <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, - <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, - <&clks IMXRT1050_CLK_PLL1_ARM>, - <&clks IMXRT1050_CLK_PLL2_SYS>, - <&clks IMXRT1050_CLK_PLL3_USB_OTG>, - <&clks IMXRT1050_CLK_PLL3_USB_OTG>, - <&clks IMXRT1050_CLK_PLL2_SYS>; - }; - - edma1: dma-controller@400e8000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x400e8000 0x4000>, - <0x400ec000 0x4000>; - dma-channels = <32>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; - clock-names = "dma", "dmamux0"; - clocks = <&clks IMXRT1050_CLK_DMA>, - <&clks IMXRT1050_CLK_DMA_MUX>; - }; - - usdhc1: mmc@402c0000 { - compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x402c0000 0x4000>; - interrupts = <110>; - clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, - <&clks IMXRT1050_CLK_OSC>, - <&clks IMXRT1050_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,wp-controller; - no-1-8-v; - max-frequency = <200000000>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - gpio1: gpio@401b8000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401b8000 0x4000>; - interrupts = <80>, <81>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@401bc000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401bc000 0x4000>; - interrupts = <82>, <83>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@401c0000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401c0000 0x4000>; - interrupts = <84>, <85>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@401c4000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401c4000 0x4000>; - interrupts = <86>, <87>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@400c0000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x400c0000 0x4000>; - interrupts = <88>, <89>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpt: timer@401ec000 { - compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; - reg = <0x401ec000 0x4000>; - interrupts = <100>; - clocks = <&osc3M>; - clock-names = "per"; - }; - }; -}; diff --git a/arch/arm/boot/dts/imxrt1170-pinfunc.h b/arch/arm/boot/dts/imxrt1170-pinfunc.h deleted file mode 100644 index 3b9fff2f08e1..000000000000 --- a/arch/arm/boot/dts/imxrt1170-pinfunc.h +++ /dev/null @@ -1,1561 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2021 - * Author(s): Jesse Taube - */ - -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H -#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H - -#define IMX_PAD_SION 0x40000000 - -/* - * The pin function ID is a tuple of - * - */ - -#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 -#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 -#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 -#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 -#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 -#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 - -#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0 -#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 -#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 -#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 -#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 -#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 -#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 -#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 -#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 -#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 - -#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 -#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 -#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0 -#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0 -#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0 -#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1 -#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1 -#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0 -#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1 -#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0 -#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1 -#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0 - -#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1 -#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2 -#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1 -#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1 -#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0 - -#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1 -#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0 -#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1 -#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2 - -#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1 -#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0 -#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2 -#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1 -#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1 - -#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1 -#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1 -#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1 - -#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1 -#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1 -#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1 -#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1 -#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1 -#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1 - -#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0 -#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1 - -#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0 -#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0 - -#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0 -#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0 - -#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0 - -#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0 - -#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0 - -#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0 -#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1 -#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1 - -#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1 - -#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1 - -#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1 -#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1 -#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1 -#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1 -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1 -#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1 -#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0 -#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0 -#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1 -#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0 -#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1 -#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0 -#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1 -#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0 -#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1 -#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1 -#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1 -#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1 -#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1 -#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1 -#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0 -#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0 -#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1 -#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0 -#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0 -#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1 -#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0 -#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0 -#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0 -#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0 -#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0 -#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0 -#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0 -#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1 -#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0 -#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0 -#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0 -#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0 -#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1 -#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0 -#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0 -#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0 - -#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0 -#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0 -#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0 -#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1 -#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2 -#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0 -#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0 -#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1 - -#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0 -#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0 -#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1 -#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0 -#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0 -#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0 -#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0 -#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0 -#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0 -#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0 -#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0 -#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0 -#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0 -#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0 -#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0 -#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0 -#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0 -#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0 -#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1 -#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0 -#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0 -#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0 -#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0 -#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1 -#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0 - -#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0 -#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0 -#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1 -#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1 - -#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0 -#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0 -#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1 -#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1 -#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1 - -#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0 -#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1 -#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1 -#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1 -#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0 -#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0 -#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1 -#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1 -#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1 -#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1 -#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1 -#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1 -#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1 -#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0 -#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1 -#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1 -#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1 -#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1 -#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0 -#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1 -#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3 -#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1 -#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0 - -#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0 -#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0 - -#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0 -#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0 -#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0 -#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0 -#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0 - -#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2 -#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0 -#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1 -#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0 -#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1 -#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1 - -#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1 - -#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1 - -#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1 -#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1 -#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1 -#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0 -#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1 -#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1 -#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2 -#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2 -#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0 - -#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0 -#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0 - -#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0 - -#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1 - -#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1 - -#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1 -#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1 -#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2 - -#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1 -#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2 - -#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2 -#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2 - -#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0 -#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2 -#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1 -#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3 - -#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2 -#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1 -#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0 - -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */ diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi deleted file mode 100644 index 7f1c8ee9dd8a..000000000000 --- a/arch/arm/boot/dts/integrator.dtsi +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SoC core Device Tree for the ARM Integrator platforms - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - core-module@10000000 { - compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; - reg = <0x10000000 0x200>; - ranges = <0x0 0x10000000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - - /* Use core module LED to indicate CPU load */ - led@c,0 { - compatible = "register-bit-led"; - reg = <0x0c 0x04>; - offset = <0x0c>; - mask = <0x01>; - label = "integrator:core_module"; - linux,default-trigger = "cpu0"; - default-state = "on"; - }; - }; - - ebi@12000000 { - compatible = "arm,external-bus-interface"; - reg = <0x12000000 0x100>; - }; - - timer@13000000 { - reg = <0x13000000 0x100>; - interrupt-parent = <&pic>; - interrupts = <5>; - }; - - timer@13000100 { - reg = <0x13000100 0x100>; - interrupt-parent = <&pic>; - interrupts = <6>; - }; - - timer@13000200 { - reg = <0x13000200 0x100>; - interrupt-parent = <&pic>; - interrupts = <7>; - }; - - pic@14000000 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x14000000 0x100>; - clear-mask = <0xffffffff>; - }; - - flash@24000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x24000000 0x02000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&pic>; - - /* - * These PrimeCells are in the same locations and using the - * same interrupts in all Integrators, however the silicon - * version deployed is different. - */ - rtc@15000000 { - reg = <0x15000000 0x1000>; - interrupts = <8>; - }; - - serial@16000000 { - reg = <0x16000000 0x1000>; - interrupts = <1>; - }; - - serial@17000000 { - reg = <0x17000000 0x1000>; - interrupts = <2>; - }; - - kmi@18000000 { - reg = <0x18000000 0x1000>; - interrupts = <3>; - }; - - kmi@19000000 { - reg = <0x19000000 0x1000>; - interrupts = <4>; - }; - - syscon@1a000000 { - /* Debug registers mapped as syscon */ - compatible = "syscon", "simple-mfd"; - reg = <0x1a000000 0x10>; - ranges = <0x0 0x1a000000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - - led@4,0 { - compatible = "register-bit-led"; - reg = <0x04 0x04>; - offset = <0x04>; - mask = <0x01>; - label = "integrator:green0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@4,1 { - compatible = "register-bit-led"; - reg = <0x04 0x04>; - offset = <0x04>; - mask = <0x02>; - label = "integrator:yellow"; - default-state = "off"; - }; - led@4,2 { - compatible = "register-bit-led"; - reg = <0x04 0x04>; - offset = <0x04>; - mask = <0x04>; - label = "integrator:red"; - default-state = "off"; - }; - led@4,3 { - compatible = "register-bit-led"; - reg = <0x04 0x04>; - offset = <0x04>; - mask = <0x08>; - label = "integrator:green1"; - default-state = "off"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts deleted file mode 100644 index 7072a70da00d..000000000000 --- a/arch/arm/boot/dts/integratorap-im-pd1.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ARM Integrator/AP platform - * with the IM-PD1 example logical module mounted. - */ - -#include "integratorap.dts" - -/ { - model = "ARM Integrator/AP with IM-PD1"; - compatible = "arm,integrator-ap"; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - impd1_ram: vram@c2000000 { - /* 1 MB of designated video RAM on the IM-PD1 */ - compatible = "shared-dma-pool"; - reg = <0xc2000000 0x00100000>; - no-map; - }; - }; -}; - -&lm0 { - syscon@0 { - compatible = "arm,im-pd1-syscon", "syscon"; - reg = <0x00000000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - vco1: clock-controller@0 { - compatible = "arm,impd1-vco1"; - reg = <0x00 0x04>; - #clock-cells = <0>; - lock-offset = <0x08>; - vco-offset = <0x00>; - clocks = <&sysclk>; - clock-output-names = "IM-PD1-VCO1"; - }; - - vco2: clock-controller@4 { - compatible = "arm,impd1-vco2"; - reg = <0x04 0x04>; - #clock-cells = <0>; - lock-offset = <0x08>; - vco-offset = <0x04>; - clocks = <&sysclk>; - clock-output-names = "IM-PD1-VCO2"; - }; - }; - - /* Also used for the Smart Card Interface SCI */ - impd1_uartclk: clock@1_4 { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&vco2>; - clock-output-names = "VCO2_DIV4"; - }; - - /* For the SSP the clock is divided by 64 */ - impd1_sspclk: clock@1_64 { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <64>; - clock-mult = <1>; - clocks = <&vco2>; - clock-output-names = "VCO2_DIV64"; - }; - - /* Fixed regulator for the MMC */ - impd1_3v3: regulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* Push buttons on the IM-PD1 */ - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - debounce-interval = <50>; - linux,code = ; - label = "UP"; - gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; - }; - button@1 { - debounce-interval = <50>; - linux,code = ; - label = "DOWN"; - gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; - }; - button@2 { - debounce-interval = <50>; - linux,code = ; - label = "LEFT"; - gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; - }; - button@3 { - debounce-interval = <50>; - linux,code = ; - label = "UP"; - gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - button@4 { - debounce-interval = <50>; - linux,code = ; - label = "ESC"; - gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; - }; - button@5 { - debounce-interval = <50>; - linux,code = ; - label = "ENTER"; - gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; - }; - }; - - - bridge { - compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads_vga_dac>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - serial@100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00100000 0x1000>; - interrupts-extended = <&impd1_vic 1>; - clocks = <&impd1_uartclk>, <&sysclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial@200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00200000 0x1000>; - interrupts-extended = <&impd1_vic 2>; - clocks = <&impd1_uartclk>, <&sysclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - spi@300000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x00300000 0x1000>; - interrupts-extended = <&impd1_vic 3>; - clocks = <&impd1_sspclk>, <&sysclk>; - clock-names = "sspclk", "apb_pclk"; - }; - - impd1_gpio0: gpio@400000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x00400000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts-extended = <&impd1_vic 4>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; - }; - - impd1_gpio1: gpio@500000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x00500000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts-extended = <&impd1_vic 5>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; - }; - - rtc@600000 { - compatible = "arm,pl030", "arm,primecell"; - reg = <0x00600000 0x1000>; - interrupts-extended = <&impd1_vic 6>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; - }; - - mmc@700000 { - compatible = "arm,pl181", "arm,primecell"; - reg = <0x00700000 0x1000>; - interrupts-extended = <&impd1_vic 7>, - <&impd1_vic 8>; - clocks = <&sysclk>, <&sysclk>; - clock-names = "mclk", "apb_pclk"; - bus-width = <1>; - max-frequency = <515633>; - vmmc-supply = <&impd1_3v3>; - wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; - cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; - }; - - aaci@800000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x00800000 0x1000>; - interrupts-extended = <&impd1_vic 9>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; - }; - - display@1000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x01000000 0x1000>; - interrupts-extended = <&impd1_vic 11>; - clocks = <&vco1>, <&sysclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ - max-memory-bandwidth = <40000000>; - memory-region = <&impd1_ram>; - dma-ranges; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - clcd_pads_vga_dac: endpoint@0 { - reg = <0>; - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - impd1_vic: interrupt-controller@3000000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x03000000 0x1000>; - /* Valid interrupts, 0-9 and 11 */ - valid-mask = <0x00000bff>; - /* LM site 0 has IRQ 9 on the PIC */ - interrupts-extended = <&pic 9>; - }; -}; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts deleted file mode 100644 index 5b52d75bc6be..000000000000 --- a/arch/arm/boot/dts/integratorap.dts +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ARM Integrator/AP platform - */ - -/dts-v1/; -#include "integrator.dtsi" -#include -#include - -/ { - model = "ARM Integrator/AP"; - compatible = "arm,integrator-ap"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - /* - * Since the board has pluggable CPU modules, we - * cannot define a proper compatible here. Let the - * boot loader fill in the apropriate compatible - * string if necessary. - */ - /* compatible = "arm,arm926ej-s"; */ - reg = <0>; - /* - * The documentation in ARM DUI 0138E page 3-12 states - * that the maximum frequency for this clock is 200 MHz - * but painful trial-and-error has proved to me that it - * is actually just hanging the system above 71 MHz. - * Sad but true. - */ - /* kHz uV */ - operating-points = <71000 0 - 66000 0 - 60000 0 - 48000 0 - 36000 0 - 24000 0 - 12000 0>; - clocks = <&cmosc>; - clock-names = "cpu"; - clock-latency = <1000000>; /* 1 ms */ - }; - }; - - aliases { - arm,timer-primary = &timer2; - arm,timer-secondary = &timer1; - }; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; - }; - - /* 24 MHz chrystal on the Integrator/AP development board */ - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* The UART clock is 14.74 MHz divided by an ICS525 */ - uartclk: uartclk@14.74M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - clocks = <&xtal24mhz>; - }; - - core-module@10000000 { - /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - /* Oscillator on the core module, clocks the CPU core */ - cmosc: clock-controller@8 { - compatible = "arm,syscon-icst525-integratorap-cm"; - reg = <0x08 0x04>; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Auxilary oscillator on the core module, 32.369MHz at boot */ - auxosc: clock-controller@1c { - compatible = "arm,syscon-icst525"; - reg = <0x1c 0x04>; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x1c>; - clocks = <&cm24mhz>; - }; - }; - - syscon { - compatible = "arm,integrator-ap-syscon", "syscon"; - reg = <0x11000000 0x100>; - ranges = <0x0 0x11000000 0x100>; - #size-cells = <1>; - #address-cells = <1>; - - /* - * SYSCLK clocks PCIv3 bridge, system controller and the - * logic modules. - */ - sysclk: clock-controller@4 { - compatible = "arm,syscon-icst525-integratorap-sys"; - reg = <0x04 0x04>; - #clock-cells = <0>; - lock-offset = <0x1c>; - vco-offset = <0x04>; - clocks = <&xtal24mhz>; - }; - - /* One-bit control for the PCI bus clock (33 or 25 MHz) */ - pciclk: clock-controller@4,8 { - compatible = "arm,syscon-icst525-integratorap-pci"; - reg = <0x04 0x04>; - #clock-cells = <0>; - lock-offset = <0x1c>; - vco-offset = <0x04>; - clocks = <&xtal24mhz>; - }; - }; - - timer0: timer@13000000 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - timer1: timer@13000100 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - timer2: timer@13000200 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - pic: pic@14000000 { - valid-mask = <0x003fffff>; - }; - - pci: pciv3@62000000 { - compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - /* Bridge registers and config access space */ - reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; - interrupt-parent = <&pic>; - interrupts = <17>; /* Bus error IRQ */ - clocks = <&pciclk>; - bus-range = <0x00 0xff>; - ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ - 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ - 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ - 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ - 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ - 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ - dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ - 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ - 0x02000000 0 0x80000000 /* Core module alias memory */ - 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = < - /* IDSEL 9 */ - 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ - 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ - 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ - 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ - /* IDSEL 10 */ - 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ - 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ - 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ - 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ - /* IDSEL 11 */ - 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ - 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ - 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ - 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ - /* IDSEL 12 */ - 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ - 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ - 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ - 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ - >; - }; - - fpga { - /* - * The Integator/AP predates the idea to have magic numbers - * identifying the PrimeCell in hardware, thus we have to - * supply these from the device tree. - */ - rtc: rtc@15000000 { - compatible = "arm,pl030", "arm,primecell"; - arm,primecell-periphid = <0x00041030>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart0: serial@16000000 { - compatible = "arm,pl010", "arm,primecell"; - arm,primecell-periphid = <0x00041010>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: serial@17000000 { - compatible = "arm,pl010", "arm,primecell"; - arm,primecell-periphid = <0x00041010>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - kmi0: kmi@18000000 { - compatible = "arm,pl050", "arm,primecell"; - arm,primecell-periphid = <0x00041050>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@19000000 { - compatible = "arm,pl050", "arm,primecell"; - arm,primecell-periphid = <0x00041050>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - }; - - /* - * Logic module bus, we support up to 4 logical modules - * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 - * and use interrupts 9, 10, 11 and 12 respectively. - */ - bus@c0000000 { - compatible = "arm,integrator-ap-lm"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc0000000 0xc0000000 0x40000000>; - dma-ranges; - - lm0: bus@c0000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xc0000000 0x10000000>; - dma-ranges = <0x00000000 0xc0000000 0x10000000>; - reg = <0xc0000000 0x10000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - lm1: bus@d0000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xd0000000 0x10000000>; - dma-ranges = <0x00000000 0xd0000000 0x10000000>; - reg = <0xd0000000 0x10000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - lm2: bus@e0000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xe0000000 0x10000000>; - dma-ranges = <0x00000000 0xe0000000 0x10000000>; - reg = <0xe0000000 0x10000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - lm3: bus@f0000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf0000000 0x10000000>; - dma-ranges = <0x00000000 0xf0000000 0x10000000>; - reg = <0xf0000000 0x10000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts deleted file mode 100644 index c011333eb165..000000000000 --- a/arch/arm/boot/dts/integratorcp.dts +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ARM Integrator/CP platform - */ - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/CP"; - compatible = "arm,integrator-cp"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - /* - * Since the board has pluggable CPU modules, we - * cannot define a proper compatible here. Let the - * boot loader fill in the apropriate compatible - * string if necessary. - */ - /* compatible = "arm,arm920t"; */ - reg = <0>; - /* - * TBD comment. - */ - /* kHz uV */ - operating-points = <50000 0 - 48000 0>; - clocks = <&cmcore>; - clock-names = "cpu"; - clock-latency = <1000000>; /* 1 ms */ - }; - }; - - /* - * The Integrator/CP overall clocking architecture can be found in - * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which - * appear to illustrate the layout used in most configurations. - */ - - /* The codec chrystal operates at 24.576 MHz */ - xtal_codec: xtal24.576@24.576M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - /* The chrystal is divided by 2 by the codec for the AACI bit clock */ - aaci_bitclk: aaci_bitclk@12.288M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&xtal_codec>; - }; - - /* This is a 25MHz chrystal on the base board */ - xtal25mhz: xtal25mhz@25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ - uartclk: uartclk@14.74M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - }; - - /* Actually sysclk I think */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - core-module@10000000 { - /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - /* Oscillator on the core module, clocks the CPU core */ - cmcore: clock-controller@8 { - compatible = "arm,syscon-icst525-integratorcp-cm-core"; - reg = <0x08 0x04>; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Oscillator on the core module, clocks the memory bus */ - cmmem: clock-controller@8,12 { - compatible = "arm,syscon-icst525-integratorcp-cm-mem"; - reg = <0x08 0x04>; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Auxilary oscillator on the core module, clocks the CLCD */ - auxosc: clock-controller@1c { - compatible = "arm,syscon-icst525"; - reg = <0x1c 0x04>; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x1c>; - clocks = <&cm24mhz>; - }; - - /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ - kmiclk: kmiclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <3>; - clock-mult = <1>; - clocks = <&cm24mhz>; - }; - - /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&cm24mhz>; - }; - }; - - syscon { - compatible = "arm,integrator-cp-syscon", "syscon"; - reg = <0xcb000000 0x100>; - }; - - timer0: timer@13000000 { - /* TIMER0 runs directly on the 25MHz chrystal */ - compatible = "arm,integrator-cp-timer"; - clocks = <&xtal25mhz>; - }; - - timer1: timer@13000100 { - /* TIMER1 runs @ 1MHz */ - compatible = "arm,integrator-cp-timer"; - clocks = <&timclk>; - }; - - timer2: timer@13000200 { - /* TIMER2 runs @ 1MHz */ - compatible = "arm,integrator-cp-timer"; - clocks = <&timclk>; - }; - - pic: pic@14000000 { - valid-mask = <0x1fc003ff>; - }; - - cic: cic@10000040 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x10000040 0x100>; - clear-mask = <0xffffffff>; - valid-mask = <0x00000007>; - }; - - /* The SIC is cascaded off IRQ 26 on the PIC */ - sic: sic@ca000000 { - compatible = "arm,versatile-fpga-irq"; - interrupt-parent = <&pic>; - interrupts = <26>; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0xca000000 0x100>; - clear-mask = <0x00000fff>; - valid-mask = <0x00000fff>; - }; - - ethernet@c8000000 { - compatible = "smsc,lan91c111"; - reg = <0xc8000000 0x10>; - interrupt-parent = <&pic>; - interrupts = <27>; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads_vga_dac>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - fpga { - /* - * These PrimeCells are at the same location and using - * the same interrupts in all Integrators, but in the CP - * slightly newer versions are deployed. - */ - rtc@15000000 { - compatible = "arm,pl031", "arm,primecell"; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial@16000000 { - compatible = "arm,pl011", "arm,primecell"; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial@17000000 { - compatible = "arm,pl011", "arm,primecell"; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - kmi@18000000 { - compatible = "arm,pl050", "arm,primecell"; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@19000000 { - compatible = "arm,pl050", "arm,primecell"; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - /* - * These PrimeCells are only available on the Integrator/CP - */ - mmc@1c000000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x1c000000 0x1000>; - interrupts = <23 24>; - max-frequency = <515633>; - clocks = <&uartclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - - aaci@1d000000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x1d000000 0x1000>; - interrupts = <25>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - clcd@c0000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0xC0000000 0x1000>; - interrupts = <22>; - clocks = <&auxosc>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ - max-memory-bandwidth = <40000000>; - - /* - * This port is routed through a PLD (Programmable - * Logic Device) that routes the output from the CLCD - * (after transformations) to the VGA DAC and also an - * external panel connector. The PLD is essential for - * supporting RGB565/BGR565. - * - * The signals from the port thus reaches two endpoints. - * The PLD is managed through a few special bits in the - * FPGA "sysreg". - * - * This arrangement can be clearly seen in - * ARM DUI 0225D, page 3-41, figure 3-19. - */ - port@0 { - clcd_pads_vga_dac: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts deleted file mode 100644 index 765ab36e6f0c..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for ADI Engineering Coyote platform. - * Derived from boardfiles written by MontaVista software. - * Ethernet set-up from OpenWrt. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "ADI Engineering Coyote reference design"; - compatible = "adieng,coyote", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */ - device_type = "memory"; - reg = <0x00000000 0x01000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; - stdout-path = "uart1:115200n8"; - }; - - aliases { - /* These are switched around */ - serial0 = &uart1; - serial1 = &uart0; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 32 MB of Flash in 128 0x20000 sized blocks - * mapped in at CS0 and CS1 - */ - reg = <0 0x00000000 0x2000000>; - - /* Configure expansion bus to allow writes */ - intel,ixp4xx-eb-write-enable = <1>; - - partitions { - compatible = "redboot-fis"; - /* CHECKME: guess this is Redboot FIS */ - fis-index-block = <0x1ff>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from Coyote PCI boardfile. - * We have slots (IDSEL) 1 and 2 with one assigned IRQ - * each handling all IRQs. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */ - <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */ - <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */ - <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ - <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */ - <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ - <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */ - }; - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts deleted file mode 100644 index 6f5b4e4eb1cc..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Arcom/Eurotech Vulcan board. - * This board is a single board computer in the PC/104 form factor based on - * IXP425, and was released around 2005. It previously had the name "Mercury". - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Arcom/Eurotech Vulcan"; - compatible = "arcom,vulcan", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - /* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */ - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 32 MB of Flash in 0x20000 byte blocks - * mapped in at CS0 and CS1. - * - * The documentation mentions the existence - * of a 16MB version, which we conveniently - * ignore. Shout if you own one! - */ - reg = <0 0x00000000 0x2000000>; - - /* Expansion bus settings */ - intel,ixp4xx-eb-t3 = <3>; - intel,ixp4xx-eb-byte-access-on-halfword = <1>; - intel,ixp4xx-eb-write-enable = <1>; - - partitions { - compatible = "redboot-fis"; - fis-index-block = <0x1ff>; - }; - }; - sram@2,0 { - /* 256 KB SDRAM memory at CS2 */ - compatible = "shared-dma-pool"; - device_type = "memory"; - reg = <2 0x00000000 0x40000>; - no-map; - /* Expansion bus settings */ - intel,ixp4xx-eb-t3 = <1>; - intel,ixp4xx-eb-t4 = <2>; - intel,ixp4xx-eb-ahb-split-transfers = <1>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - }; - serial@3,0 { - /* - * 8250-compatible Exar XR16L2551 2 x UART - * - * CHECKME: if special tweaks are needed, then fix the - * operating system to handle it. - */ - compatible = "exar,xr16l2551", "ns8250"; - reg = <3 0x00000000 0x10>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - clock-frequency = <1843200>; - /* Expansion bus settings */ - intel,ixp4xx-eb-t3 = <3>; - intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */ - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - }; - gpio1: gpio@4,0 { - /* - * MMIO GPIO in one byte - */ - compatible = "arcom,vulcan-gpio"; - reg = <4 0x00000000 0x1>; - /* Expansion bus settings */ - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - }; - watchdog@5,0 { - compatible = "maxim,max6369"; - reg = <5 0x00000000 0x1>; - /* Expansion bus settings */ - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from Vulcan PCI boardfile. - * - * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt - * per slot. This interrupt is shared (OR:ed) by all four pins. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */ - <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */ - <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */ - <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */ - <0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */ - <0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */ - <0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */ - }; - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts deleted file mode 100644 index b9d46eb06507..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for D-Link DSM-G600 revision A based on IXP420 - * NOTE: revision B of this device uses PowerPC and is NOT supported by - * this device tree. - * - * Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo - * and Michael Westerhof. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "D-Link DSM-G600 rev A"; - compatible = "dlink,dsm-g600-a", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-power { - label = "dsmg600:green:power"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-wlan { - label = "dsmg600:green:wlan"; - /* CHECKME: flagged as active low in the old board file */ - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - /* We don't have WLAN trigger in the kernel (yet) */ - linux,default-trigger = "netdev"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-reset { - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys_polled { - compatible = "gpio-keys-polled"; - - /* - * According to the board file this key cannot handle interrupts and - * need to be polled. Investigate if this is really the case or if - * this can be moved adjacent to the ordinary gpio-keys above. - */ - button-power { - wakeup-source; - linux,code = ; - label = "power"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - timeout-ms = <5000>; - }; - - soc { - bus@c4000000 { - /* The first 16MB region at CS0 on the expansion bus */ - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 16 MB of Flash in 128 0x20000 sized blocks - * mapped in at CS0. - */ - reg = <0 0x00000000 0x1000000>; - - partitions { - compatible = "redboot-fis"; - /* - * A boot log says the directory is at 0xfe0000 - * 0x7f * 0x20000 = 0xfe0000 - */ - fis-index-block = <0x7f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from DSM-G600 PCI boardfile (dsmg600-pci.c) - * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3. - * Only slot 3 have three IRQs. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ - /* IDSEL 3 */ - <0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */ - <0x1800 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */ - <0x1800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */ - /* IDSEL 4 */ - <0x2000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */ - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts deleted file mode 100644 index 5a5e16cc7335..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Freecom FSG-3 router. - * This machine is based on IXP425. - * This device tree is inspired by the board file by Rod Whitby. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Freecom FSG-3"; - compatible = "freecom,fsg-3", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB memory */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - /* Boot from the first partition on the hard drive */ - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-sync { - wakeup-source; - /* Closest approximation of what the key should do */ - linux,code = ; - label = "sync"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - }; - button-reset { - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; - }; - button-usb { - wakeup-source; - /* Unplug USB, closest approximation of what the key should do */ - linux,code = ; - label = "usb"; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - hwmon@28 { - /* - * Temperature sensor and fan control chip. - * - * TODO: create a proper device tree binding for - * the sensor and temperature zone and create a - * zone with fan control. - */ - compatible = "winbond,w83781d"; - reg = <0x28>; - }; - rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 4 MB of Flash mapped in at CS0 */ - reg = <0 0x00000000 0x400000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x3e0000 */ - fis-index-block = <0x1f>; - }; - }; - - /* Small syscon with some LEDs at CS2 */ - syscon@2,0 { - compatible = "freecom,fsg-cs2-system-controller", "syscon"; - reg = <2 0x0 0x200>; - reg-io-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <2 0x0 0x0 0x200>; - - led@0,0 { - compatible = "register-bit-led"; - reg = <0x00 0x02>; - mask = <0x01>; - label = "fsg:blue:wlan"; - linux,default-trigger = "wlan"; - default-state = "on"; - }; - led@0,1 { - compatible = "register-bit-led"; - reg = <0x00 0x02>; - mask = <0x02>; - label = "fsg:blue:wan"; - linux,default-trigger = ""; - default-state = "on"; - }; - led@0,2 { - compatible = "register-bit-led"; - reg = <0x00 0x02>; - mask = <0x04>; - label = "fsg:blue:sata"; - linux,default-trigger = ""; - default-state = "on"; - }; - led@0,3 { - compatible = "register-bit-led"; - reg = <0x00 0x02>; - mask = <0x04>; - label = "fsg:blue:usb"; - linux,default-trigger = ""; - default-state = "on"; - }; - led@0,4 { - compatible = "register-bit-led"; - reg = <0x00 0x02>; - mask = <0x08>; - label = "fsg:blue:sync"; - linux,default-trigger = ""; - default-state = "on"; - }; - led@0,5 { - compatible = "register-bit-led"; - reg = <0x00 0x02>; - mask = <0x10>; - label = "fsg:blue:ring"; - linux,default-trigger = ""; - default-state = "on"; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Written based on the FSG-3 PCI boardfile. - * We have slots 12, 13 & 14 (IDSEL) with one IRQ each. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 12 */ - <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ - <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ - <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ - <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ - /* IDSEL 13 */ - <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ - <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ - <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ - <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ - /* IDSEL 14 */ - <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ - <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ - <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ - <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ - }; - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts deleted file mode 100644 index 4d70f6afd13a..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Gateway 7001 AP based on IXP422 - * Derived from boardfiles written by Imre Kaloz - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Gateway 7001 AP"; - compatible = "gateway,7001", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 32 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "uart1:115200n8"; - }; - - aliases { - /* second UART is the primary console */ - serial0 = &uart1; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of flash - */ - reg = <0 0x00000000 0x800000>; - - /* Configure expansion bus to allow writes */ - intel,ixp4xx-eb-write-enable = <1>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) - * We have slots (IDSEL) 1 and 2 with one assigned IRQ - * each handling all IRQs. - */ - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */ - <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */ - <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ - <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ - <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ - <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ - }; - - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy2>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts deleted file mode 100644 index 97e3f25bb210..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Gateworks Avila GW2348 board. - * This machine is based on IXP425. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Gateworks Avila GW2348"; - compatible = "gateworks,gw2348", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-user { - label = "gw2348:green:user"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - hwmon@28 { - compatible = "adi,ad7418"; - reg = <0x28>; - }; - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - eeprom@51 { - compatible = "atmel,24c08"; - reg = <0x51>; - pagesize = <16>; - size = <1024>; - read-only; - }; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 16 MB of Flash mapped in at CS0 */ - reg = <0 0x00000000 0x1000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x0fe0000 */ - fis-index-block = <0x7f>; - }; - }; - ide@1,0 { - compatible = "intel,ixp4xx-compact-flash"; - /* - * Set up expansion bus config to a really slow timing. - * The CF driver will dynamically reconfigure these timings - * depending on selected PIO mode (0-4). - */ - intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase - intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase - intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase - intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase - intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase - intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type - intel,ixp4xx-eb-byte-access-on-halfword = <1>; - intel,ixp4xx-eb-mux-address-and-data = <0>; - intel,ixp4xx-eb-ahb-split-transfers = <0>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - /* First register set is CMD second is CTL (notice it uses CS2) */ - reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>; - interrupt-parent = <&gpio0>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - }; - /* - * FIXME: Latch LEDs or extra UARTs at CS4 - */ - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from Avila PCI boardfile. - * - * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ - <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ - <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ - <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ - /* IDSEL 3 */ - <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ - <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ - <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ - <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ - /* IDSEL 4 */ - <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ - <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ - <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ - <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ - }; - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts deleted file mode 100644 index 9ec0169bacf8..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Goramo MultiLink Router - * There are two variants: - * - MultiLink Basic (a box) - * - MultiLink Max (19" rack mount) - * This device tree supports MultiLink Basic. - * This machine is based on IXP425. - * This is one of the few devices supporting the IXP4xx High-Speed Serial - * (HSS) link for a V.35 WAN interface. - * The hardware originates in Poland. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Goramo MultiLink Router"; - compatible = "goramo,multilink-router", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* - * 64 MB of RAM according to the manual. The MultiLink - * Max has 128 MB. - */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - /* - * 74HC4094 which is used as a rudimentary GPIO expander - * FIXME: - * - Create device tree bindings for this as GPIO expander - * - Write a pure DT GPIO driver using these bindings - * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) - */ - gpio_74: gpio-74hc4094 { - compatible = "nxp,74hc4094"; - cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - /* oe-gpios is optional */ - gpio-controller; - #gpio-cells = <2>; - /* We are not cascaded */ - registers-number = <1>; - gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N", - "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET", - "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N"; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 16 MB of Flash mapped in at CS0 */ - reg = <0 0x00000000 0x1000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x0fe0000 */ - fis-index-block = <0x7f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. - * The slots have Ethernet, Ethernet, NEC and MPCI. - * The IDSELs are 11, 12, 13, 14. - */ - interrupt-map = - /* IDSEL 11 - Ethernet A */ - <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ - <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ - <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */ - <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */ - /* IDSEL 12 - Ethernet B */ - <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ - <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ - <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ - <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ - /* IDSEL 13 - MPCI */ - <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */ - <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */ - <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */ - <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */ - /* IDSEL 14 - NEC */ - <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */ - <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */ - <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */ - <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */ - }; - - /* HSS links */ - npe@c8006000 { - hss@0 { - status = "okay"; - intel,queue-chl-rxtrig = <&qmgr 12>; - intel,queue-chl-txready = <&qmgr 34>; - intel,queue-pkt-rx = <&qmgr 13>; - intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; - intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; - intel,queue-pkt-txdone = <&qmgr 22>; - /* The Goramo GPIO-based clock etc control */ - cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; - clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; - }; - hss@1 { - status = "okay"; - intel,queue-chl-rxtrig = <&qmgr 10>; - intel,queue-chl-txready = <&qmgr 35>; - intel,queue-pkt-rx = <&qmgr 0>; - intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>; - intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>; - intel,queue-pkt-txdone = <&qmgr 9>; - /* The Goramo GPIO-based clock etc control */ - cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>; - clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>; - }; - }; - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 32>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 33>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts deleted file mode 100644 index 8da6823e1dbe..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Iomega NAS 100D - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Iomega NAS 100D"; - compatible = "iom,nas-100d", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-wlan { - label = "nas100d:red:wlan"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - /* We don't have WLAN trigger in the kernel (yet) */ - linux,default-trigger = "netdev"; - }; - led-disk { - label = "nas100d:red:disk"; - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "disk-activity"; - }; - led-power { - label = "nas100d:red:power"; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-power { - wakeup-source; - linux,code = ; - label = "power"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - button-reset { - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - timeout-ms = <5000>; - }; - - soc { - bus@c4000000 { - /* The first 16MB region at CS0 on the expansion bus */ - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of Flash in 0x20000 byte blocks - * mapped in at CS0. - */ - reg = <0 0x00000000 0x800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from NAS 100D PCI boardfile (nas100d-pci.c) - * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ - /* IDSEL 3 */ - <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ - <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ - <0x1800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */ - }; - - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts deleted file mode 100644 index 194945748dc3..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane - * processor reference design. - * - * This platform has the codename "Richfield". - * - * This machine is based on a 533 MHz IXP425. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include "intel-ixp4xx-reference-design.dtsi" -#include - -/ { - model = "Intel IXDP425/IXCDP1100 Richfield Reference Design"; - compatible = "intel,ixdp425", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 16 MB of Flash mapped in at CS0 */ - reg = <0 0x00000000 0x1000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x0fe0000 */ - fis-index-block = <0x7f>; - }; - }; - }; - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts deleted file mode 100644 index 7011fea6205b..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Intel IXDPG425 reference design. - * Derived from boardfiles written by MontaVista software. - * Ethernet set-up from OpenWrt. - * - * The device has 4 x FXS RJ11 ports for analog phones for - * internet telephony. (Not supported yet.) - * - * The device has 9 status LEDs we do not support yet. - * - * This device is very similar to ADI engingeering Coyote. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Intel IXDPG425 reference design"; - compatible = "intel,ixdpg425", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 32 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x02000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * CHECKME: the product brief says 16MB in a flash - * socket. - */ - reg = <0 0x00000000 0x1000000>; - - /* Configure expansion bus to allow writes */ - intel,ixp4xx-eb-write-enable = <1>; - - partitions { - compatible = "redboot-fis"; - /* CHECKME: guess this is Redboot FIS */ - fis-index-block = <0x7f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from IXDPG425 PCI boardfile. - * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ - * for 12 & 13 and one for 14. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 12 */ - <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */ - <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */ - <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */ - <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */ - /* IDSEL 13 */ - <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ - <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ - <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ - <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ - /* IDSEL 14 */ - <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ - <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ - <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ - <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ - }; - - /* - * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind - * of Realtek DSA switch on the board. - */ - - /* EthB */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - }; - }; - }; - - /* EthC */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts deleted file mode 100644 index da1e93212b86..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Linksys NSLU2 - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)"; - compatible = "linksys,nslu2", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 32 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-status { - label = "nslu2:red:status"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-ready { - label = "nslu2:green:ready"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - led-disk-1 { - label = "nslu2:green:disk-1"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - led-disk-2 { - label = "nslu2:green:disk-2"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-power { - wakeup-source; - linux,code = ; - label = "power"; - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - }; - button-reset { - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6f { - compatible = "xicor,x1205"; - reg = <0x6f>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - timeout-ms = <5000>; - }; - - gpio-beeper { - compatible = "gpio-beeper"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - }; - - soc { - bus@c4000000 { - /* The first 16MB region at CS0 on the expansion bus */ - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of Flash in 0x20000 byte blocks - * mapped in at CS0. - */ - reg = <0 0x00000000 0x800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant - * We have slots (IDSEL) 1, 2 and 3. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ - <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ - <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ - <0x1000 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */ - /* IDSEL 3 */ - <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ - <0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ - <0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ - <0x1800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */ - }; - - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts deleted file mode 100644 index 4aba9e0214a0..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Linksys WRV54G router - * Also known as Gemtek GTWX5715 - * Based on a board file by George T. Joseph and other patches. - * This machine is based on IXP425. - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Linksys WRV54G / Gemtek GTWX5715"; - compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 32 MB memory */ - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "uart1:115200n8"; - }; - - aliases { - /* UART2 is the primary console */ - serial0 = &uart1; - serial1 = &uart0; - }; - - /* There is an unpopulated LED slot (3) connected to GPIO 8 */ - leds { - compatible = "gpio-leds"; - led-power { - label = "wrv54g:yellow:power"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-wireless { - label = "wrv54g:yellow:wireless"; - gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - led-internet { - label = "wrv54g:yellow:internet"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - led-dmz { - label = "wrv54g:green:dmz"; - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - /* This set-up comes from an OpenWrt patch */ - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - switch@0 { - compatible = "micrel,ks8995"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 8 MB of Flash mapped in at CS0 */ - reg = <0 0x00000000 0x00800000>; - - partitions { - compatible = "fixed-partitions"; - /* - * Partition info from a boot log - * CHECKME: not using redboot? FIS index 0x3f @7e00000? - */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "boot"; - reg = <0x0 0x140000>; - read-only; - }; - partition@140000 { - label = "linux"; - reg = <0x140000 0x100000>; - read-only; - }; - partition@240000 { - label = "root"; - reg = <0x240000 0x480000>; - read-write; - }; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. - * Derived from the GTWX5715 PCI boardfile. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 0 */ - <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */ - <0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */ - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */ - }; - - /* - * EthB - connected to the KS8995 switch ports 1-4 - * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to - * all four switch ports, also using an out of tree multiphy patch. - * Do we need a new binding and property for this? - */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Should be ports 1-4 on the KS8995 switch */ - phy4: ethernet-phy@4 { - reg = <4>; - }; - - /* Should be port 5 on the KS8995 switch */ - phy5: ethernet-phy@5 { - reg = <5>; - }; - }; - }; - - /* EthC - connected to KS8995 switch port 5 */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts deleted file mode 100644 index 19d56e9aec9d..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Netgear WG302v2 based on IXP422BB - * Derived from boardfiles written by Imre Kaloz - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Netgear WG302 v1"; - compatible = "netgear,wg302v1", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 32 MB SDRAM according to boot arguments */ - device_type = "memory"; - reg = <0x00000000 0x02000000>; - }; - - chosen { - /* The RedBoot comes up in 9600 baud so let's keep this */ - bootargs = "console=ttyS0,9600n8"; - stdout-path = "uart1:9600n8"; - }; - - aliases { - /* These are switched around */ - serial0 = &uart1; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of Flash in 64 0x20000 sized blocks - * mapped in at CS0. - */ - reg = <0 0x00000000 0x800000>; - - /* Configure expansion bus to allow writes */ - intel,ixp4xx-eb-write-enable = <1>; - - partitions { - compatible = "redboot-fis"; - fis-index-block = <0x3f>; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) - * We have slots (IDSEL) 1 and 2 with one assigned IRQ - * each handling all IRQs. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */ - <0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */ - <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ - <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ - <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ - }; - - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy30>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy30: ethernet-phy@30 { - reg = <30>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts deleted file mode 100644 index c550c421b659..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Corentin Labbe - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" - -/ { - model = "Welltech EPBX100"; - compatible = "welltech,epbx100", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 16 MB of Flash - */ - reg = <0 0x00000000 0x1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "zImage"; - reg = <0x00080000 0x00100000>; - read-only; - }; - partition@180000 { - label = "ramdisk"; - reg = <0x00180000 0x00300000>; - read-only; - }; - partition@480000 { - label = "User"; - reg = <0x00480000 0x00b60000>; - read-only; - }; - partition@fe0000 { - label = "FIS directory"; - reg = <0x00fe0000 0x001f000>; - read-only; - }; - partition@fff000 { - label = "RedBoot config"; - reg = <0x00fff000 0x0001000>; - read-only; - }; - }; - }; - }; - - /* LAN port */ - ethernet@c8009000 { - status = "okay"; - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy5: ethernet-phy@5 { - reg = <5>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi deleted file mode 100644 index 84cee8ec3ab8..000000000000 --- a/arch/arm/boot/dts/intel-ixp42x.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP 42x series. This series has 32 interrupts. - */ -#include "intel-ixp4xx.dtsi" - -/ { - soc { - bus@c4000000 { - compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; - reg = <0xc4000000 0x30>; - }; - - pci@c0000000 { - compatible = "intel,ixp42x-pci"; - }; - - interrupt-controller@c8003000 { - compatible = "intel,ixp42x-interrupt"; - }; - - /* - * This is the USB Device Mode (UDC) controller, which is used - * to present the IXP4xx as a device on a USB bus. - */ - usb@c800b000 { - compatible = "intel,ixp4xx-udc"; - reg = <0xc800b000 0x1000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts deleted file mode 100644 index 1db849515f9e..000000000000 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Gateworks IXP43x-based Cambria GW2358 - */ - -/dts-v1/; - -#include "intel-ixp43x.dtsi" - -/ { - model = "Gateworks Cambria GW2358"; - compatible = "gateworks,gw2358", "intel,ixp43x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-user { - label = "gw2358:green:LED"; - gpios = <&pld1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - hwmon@28 { - compatible = "adi,ad7418"; - reg = <0x28>; - }; - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - eeprom@51 { - compatible = "atmel,24c08"; - reg = <0x51>; - pagesize = <16>; - size = <1024>; - read-only; - }; - pld0: pld@56 { - compatible = "gateworks,pld-gpio"; - reg = <0x56>; - gpio-controller; - #gpio-cells = <2>; - }; - /* This PLD just handles the LED and user button */ - pld1: pld@57 { - compatible = "gateworks,pld-gpio"; - reg = <0x57>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* - * 32 MB of Flash in 0x20000 byte blocks - * mapped in at CS0 and CS1 - */ - reg = <0 0x00000000 0x2000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x1fe0000 */ - fis-index-block = <0xff>; - }; - }; - ide@3,0 { - compatible = "intel,ixp4xx-compact-flash"; - /* - * Set up expansion bus config to a really slow timing. - * The CF driver will dynamically reconfigure these timings - * depending on selected PIO mode (0-4). - */ - intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase - intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase - intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase - intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase - intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase - intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type - intel,ixp4xx-eb-byte-access-on-halfword = <1>; - intel,ixp4xx-eb-mux-address-and-data = <0>; - intel,ixp4xx-eb-ahb-split-transfers = <0>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - /* First register set is CMD second is CTL */ - reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>; - interrupt-parent = <&gpio0>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * In the boardfile for the Cambria from OpenWRT the interrupts - * are assigned one per IDSEL, so all 4 interrupts from IDSEL - * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2 - * connected to IRQ 10 etc. I find this highly unlikely so I - * have instead assumed that they are rotated (swizzled) like - * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ - <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ - <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ - <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ - /* IDSEL 3 */ - <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ - <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ - <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ - <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ - /* IDSEL 4 */ - <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */ - <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ - <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ - <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */ - /* IDSEL 6 */ - <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */ - <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */ - <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */ - <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */ - /* IDSEL 15 */ - <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */ - <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ - <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ - <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */ - }; - - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - }; - }; - - ethernet@c800c000 { - status = "okay"; - queue-rx = <&qmgr 2>; - queue-txready = <&qmgr 19>; - phy-mode = "rgmii"; - phy-handle = <&phy2>; - intel,npe-handle = <&npe 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts deleted file mode 100644 index 4703a8b24765..000000000000 --- a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Intel KIXRP435 Control Plane - * processor reference design. - */ - -/dts-v1/; - -#include "intel-ixp43x.dtsi" -#include "intel-ixp4xx-reference-design.dtsi" -#include - -/ { - model = "Intel KIXRP435 Reference Design"; - compatible = "intel,kixrp435", "intel,ixp43x"; - #address-cells = <1>; - #size-cells = <1>; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 16 MB of Flash mapped in at CS0 */ - reg = <0 0x00000000 0x1000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x0fe0000 */ - fis-index-block = <0x7f>; - }; - }; - }; - - /* CHECKME: ethernet set-up taken from Gateworks Cambria */ - ethernet@c800a000 { - status = "okay"; - queue-rx = <&qmgr 4>; - queue-txready = <&qmgr 21>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - }; - }; - - ethernet@c800c000 { - status = "okay"; - queue-rx = <&qmgr 2>; - queue-txready = <&qmgr 19>; - phy-mode = "rgmii"; - phy-handle = <&phy2>; - intel,npe-handle = <&npe 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi deleted file mode 100644 index 60bf9903e0f8..000000000000 --- a/arch/arm/boot/dts/intel-ixp43x.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP 43x series. This series has 64 interrupts and adds a few more - * peripherals over the 42x series. - */ -#include "intel-ixp4xx.dtsi" - -/ { - soc { - bus@c4000000 { - compatible = "intel,ixp43x-expansion-bus-controller", "syscon"; - /* Uses at least up to 0x230 */ - reg = <0xc4000000 0x1000>; - }; - - pci@c0000000 { - compatible = "intel,ixp43x-pci"; - }; - - interrupt-controller@c8003000 { - compatible = "intel,ixp43x-interrupt"; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi deleted file mode 100644 index 1dd4a65cb7a6..000000000000 --- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a - * few more peripherals over the 42x and 43x series so this extends the - * basic IXP4xx DTSI. - */ -#include "intel-ixp4xx.dtsi" - -/ { - soc { - bus@c4000000 { - compatible = "intel,ixp46x-expansion-bus-controller", "syscon"; - /* Uses at least up to 0x124 */ - reg = <0xc4000000 0x1000>; - }; - - rng@70002100 { - compatible = "intel,ixp46x-rng"; - reg = <0x70002100 4>; - }; - - interrupt-controller@c8003000 { - compatible = "intel,ixp43x-interrupt"; - }; - - /* - * This is the USB Device Mode (UDC) controller, which is used - * to present the IXP4xx as a device on a USB bus. - */ - usb@c800b000 { - compatible = "intel,ixp4xx-udc"; - reg = <0xc800b000 0x1000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c@c8011000 { - compatible = "intel,ixp4xx-i2c"; - reg = <0xc8011000 0x18>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - /* This is known as EthB1 */ - ethernet@c800d000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc800d000 0x1000>; - status = "disabled"; - intel,npe = <1>; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 0>; - queue-txready = <&qmgr 0>; - }; - - /* This is known as EthB2 */ - ethernet@c800e000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc800e000 0x1000>; - status = "disabled"; - intel,npe = <2>; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 0>; - queue-txready = <&qmgr 0>; - }; - - /* This is known as EthB3 */ - ethernet@c800f000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc800f000 0x1000>; - status = "disabled"; - intel,npe = <3>; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 0>; - queue-txready = <&qmgr 0>; - }; - - ptp-timer@c8010000 { - compatible = "intel,ixp46x-ptp-timer"; - reg = <0xc8010000 0x1000>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "master", "slave"; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts b/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts deleted file mode 100644 index a062cd1a6588..000000000000 --- a/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for the Intel IXDP465 Control Plane processor reference - * design, codename "BMP". - */ - -/dts-v1/; - -#include "intel-ixp45x-ixp46x.dtsi" -#include "intel-ixp4xx-reference-design.dtsi" -#include - -/ { - model = "Intel IXDP465 BMP Reference Design"; - compatible = "intel,ixdp465", "intel,ixp46x"; - #address-cells = <1>; - #size-cells = <1>; - - soc { - bus@c4000000 { - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* Enable writes on the expansion bus */ - intel,ixp4xx-eb-write-enable = <1>; - /* 32 MB of Flash mapped in at CS0 and CS1 */ - reg = <0 0x00000000 0x2000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x1fe0000 */ - fis-index-block = <0xff>; - }; - }; - }; - /* TODO: configure ethernet etc */ - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi deleted file mode 100644 index 31c0a69771c4..000000000000 --- a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree include file for Intel reference designs for the - * XScale Network Processors in the IXP 4xx series. Common device - * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465. - */ - -/ { - memory@0 { - /* - * The board supports up to 256 MB of memory. Here we put in - * 64 MB and this may be modified by the boot loader. - */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@50 { - /* - * Philips PCF8582C-2T/03 512byte I2C EEPROM - * should behave like an Atmel 24c04. - */ - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - size = <512>; - read-only; - }; - }; - - soc { - bus@c4000000 { - /* Flash memory defined per-variant */ - nand-controller@3,0 { - /* Some designs have a NAND on CS3 enable it here if present */ - status = "disabled"; - - /* - * gen_nand needs to be extended and documented to get - * command byte = 1 and address byte = 2 from the device - * tree. - */ - compatible = "gen_nand"; - - /* Expansion bus set-up */ - intel,ixp4xx-eb-t1 = <0>; - intel,ixp4xx-eb-t2 = <0>; - intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase - intel,ixp4xx-eb-t4 = <0>; - intel,ixp4xx-eb-t5 = <0>; - intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type - intel,ixp4xx-eb-byte-access-on-halfword = <0>; - intel,ixp4xx-eb-mux-address-and-data = <0>; - intel,ixp4xx-eb-ahb-split-transfers = <0>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - - /* 512 bytes memory window */ - reg = <3 0x00000000 0x200>; - nand-on-flash-bbt; - nand-ecc-mode = "soft_bch"; - nand-ecc-step-size = <512>; - nand-ecc-strength = <4>; - nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */ - - label = "ixp400 NAND"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - fs@0 { - label = "ixp400 NAND FS 0"; - reg = <0x0 0x800000>; - }; - fs@800000 { - label = "ixp400 NAND FS 1"; - reg = <0x800000 0x0>; - }; - }; - }; - }; - - pci@c0000000 { - status = "okay"; - - /* - * Taken from IXDP425 PCI boardfile. - * PCI slots on the BIXMB425BD base card. - * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. - */ - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - /* IDSEL 1 */ - <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ - <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ - <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ - <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ - /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ - <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ - /* IDSEL 3 */ - <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ - <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ - <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ - <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ - /* IDSEL 4 */ - <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ - <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ - <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ - <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ - }; - }; -}; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi deleted file mode 100644 index 51a716c59669..000000000000 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP 4xx series. - */ -#include -#include - -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - interrupt-parent = <&intcon>; - - /* - * The IXP4xx expansion bus is a set of up to 7 each up to 16MB - * windows in the 256MB space from 0x50000000 to 0x5fffffff. - */ - bus@c4000000 { - /* compatible and reg filled in by per-soc device tree */ - native-endian; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x01000000>, - <1 0x0 0x51000000 0x01000000>, - <2 0x0 0x52000000 0x01000000>, - <3 0x0 0x53000000 0x01000000>, - <4 0x0 0x54000000 0x01000000>, - <5 0x0 0x55000000 0x01000000>, - <6 0x0 0x56000000 0x01000000>, - <7 0x0 0x57000000 0x01000000>; - dma-ranges = <0 0x0 0x50000000 0x01000000>, - <1 0x0 0x51000000 0x01000000>, - <2 0x0 0x52000000 0x01000000>, - <3 0x0 0x53000000 0x01000000>, - <4 0x0 0x54000000 0x01000000>, - <5 0x0 0x55000000 0x01000000>, - <6 0x0 0x56000000 0x01000000>, - <7 0x0 0x57000000 0x01000000>; - }; - - qmgr: queue-manager@60000000 { - compatible = "intel,ixp4xx-ahb-queue-manager"; - reg = <0x60000000 0x4000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; - }; - - pci@c0000000 { - /* compatible filled in by per-soc device tree */ - reg = <0xc0000000 0x1000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, - <9 IRQ_TYPE_LEVEL_HIGH>, - <10 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - status = "disabled"; - - ranges = - /* - * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff - * done in 4 chunks of 16MB each. - */ - <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, - /* 64KB I/O space at 0x4c000000 */ - <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; - - /* - * This needs to map to the start of physical memory so - * PCI devices can see all (hopefully) memory. This is done - * using 4 1:1 16MB windows, so the RAM should not be more than - * 64 MB for this to work. If your memory is anywhere else - * than at 0x0 you need to alter this. - */ - dma-ranges = - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; - - /* Each unique DTS using PCI must specify the swizzling */ - }; - - uart0: serial@c8000000 { - compatible = "intel,xscale-uart"; - reg = <0xc8000000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; - reg-shift = <2>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <14745600>; - no-loopback-test; - }; - - uart1: serial@c8001000 { - compatible = "intel,xscale-uart"; - reg = <0xc8001000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; - reg-shift = <2>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <14745600>; - no-loopback-test; - }; - - gpio0: gpio@c8004000 { - compatible = "intel,ixp4xx-gpio"; - reg = <0xc8004000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - intcon: interrupt-controller@c8003000 { - /* - * Note: no compatible string. The subvariant of the - * chip needs to define what version it is. The - * location of the interrupt controller is fixed in - * memory across all variants. - */ - reg = <0xc8003000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@c8005000 { - compatible = "intel,ixp4xx-timer"; - reg = <0xc8005000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - }; - - npe: npe@c8006000 { - compatible = "intel,ixp4xx-network-processing-engine"; - reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - /* NPE-A contains two high-speed serial links */ - hss@0 { - compatible = "intel,ixp4xx-hss"; - reg = <0>; - intel,npe-handle = <&npe 0>; - status = "disabled"; - }; - - hss@1 { - compatible = "intel,ixp4xx-hss"; - reg = <1>; - intel,npe-handle = <&npe 0>; - status = "disabled"; - }; - - /* NPE-C contains a crypto accelerator */ - crypto { - compatible = "intel,ixp4xx-crypto"; - intel,npe-handle = <&npe 2>; - queue-rx = <&qmgr 30>; - queue-txready = <&qmgr 29>; - }; - }; - - /* This is known as EthB */ - ethernet@c8009000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc8009000 0x1000>; - status = "disabled"; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 3>; - queue-txready = <&qmgr 20>; - intel,npe-handle = <&npe 1>; - }; - - /* This is known as EthC */ - ethernet@c800a000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc800a000 0x1000>; - status = "disabled"; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 0>; - queue-txready = <&qmgr 0>; - intel,npe-handle = <&npe 2>; - }; - - /* This is known as EthA */ - ethernet@c800c000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc800c000 0x1000>; - status = "disabled"; - intel,npe = <0>; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 0>; - queue-txready = <&qmgr 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/intel/Makefile b/arch/arm/boot/dts/intel/Makefile new file mode 100644 index 000000000000..c5fc845deb61 --- /dev/null +++ b/arch/arm/boot/dts/intel/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += axm +subdir-y += ixp +subdir-y += pxa +subdir-y += socfpga diff --git a/arch/arm/boot/dts/intel/axm/Makefile b/arch/arm/boot/dts/intel/axm/Makefile new file mode 100644 index 000000000000..7c7dc679964d --- /dev/null +++ b/arch/arm/boot/dts/intel/axm/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb +dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb diff --git a/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts b/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts new file mode 100644 index 000000000000..2e2ad3c7ee77 --- /dev/null +++ b/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * arch/arm/boot/dts/axm5516-amarillo.dts + * + * Copyright (C) 2013 LSI + */ + +/dts-v1/; + +/memreserve/ 0x00000000 0x00400000; + +#include "axm55xx.dtsi" +#include "axm5516-cpus.dtsi" + +/ { + model = "Amarillo AXM5516"; + compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0x02 0x00000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi b/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi new file mode 100644 index 000000000000..f13ef80b6637 --- /dev/null +++ b/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * arch/arm/boot/dts/axm5516-cpus.dtsi + * + * Copyright (C) 2013 LSI + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + core2 { + cpu = <&CPU10>; + }; + core3 { + cpu = <&CPU11>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + core2 { + cpu = <&CPU14>; + }; + core3 { + cpu = <&CPU15>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x00>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x01>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x02>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x03>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x102>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x103>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x200>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x201>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x202>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x203>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x300>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x301>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x302>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x303>; + clock-frequency = <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/axm/axm55xx.dtsi b/arch/arm/boot/dts/intel/axm/axm55xx.dtsi new file mode 100644 index 000000000000..5277890cfad2 --- /dev/null +++ b/arch/arm/boot/dts/intel/axm/axm55xx.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * arch/arm/boot/dts/axm55xx.dtsi + * + * Copyright (C) 2013 LSI + */ + +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + timer = &timer0; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clk_ref0: clk_ref0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_ref1: clk_ref1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_ref2: clk_ref2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clks: clock-controller@2010020000 { + compatible = "lsi,axm5516-clks"; + #clock-cells = <1>; + reg = <0x20 0x10020000 0 0x20000>; + }; + }; + + gic: interrupt-controller@2001001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x20 0x01001000 0 0x1000>, + <0x20 0x01002000 0 0x2000>, + <0x20 0x01004000 0 0x2000>, + <0x20 0x01006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + }; + + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + device_type = "soc"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + ranges; + + syscon: syscon@2010030000 { + compatible = "lsi,axxia-syscon", "syscon"; + reg = <0x20 0x10030000 0 0x2000>; + }; + + reset: reset@2010031000 { + compatible = "lsi,axm55xx-reset"; + syscon = <&syscon>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial0: serial@2010080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10080000 0 0x1000>; + interrupts = ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + serial1: serial@2010081000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10081000 0 0x1000>; + interrupts = ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + serial2: serial@2010082000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10082000 0 0x1000>; + interrupts = ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + serial3: serial@2010083000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10083000 0 0x1000>; + interrupts = ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + timer0: timer@2010091000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x20 0x10091000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio0: gpio@2010092000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x20 0x10092000 0x00 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@2010093000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x20 0x10093000 0x00 0x1000>; + interrupts = ; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + }; + }; +}; + +/* + Local Variables: + mode: C + End: +*/ diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel/ixp/Makefile new file mode 100644 index 000000000000..1a25ce3cf84f --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_IXP4XX) += \ + intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-linksys-wrv54g.dtb \ + intel-ixp42x-freecom-fsg-3.dtb \ + intel-ixp42x-welltech-epbx100.dtb \ + intel-ixp42x-ixdp425.dtb \ + intel-ixp43x-kixrp435.dtb \ + intel-ixp46x-ixdp465.dtb \ + intel-ixp42x-adi-coyote.dtb \ + intel-ixp42x-ixdpg425.dtb \ + intel-ixp42x-goramo-multilink.dtb \ + intel-ixp42x-iomega-nas100d.dtb \ + intel-ixp42x-dlink-dsm-g600.dtb \ + intel-ixp42x-gateworks-gw2348.dtb \ + intel-ixp43x-gateworks-gw2358.dtb \ + intel-ixp42x-netgear-wg302v1.dtb \ + intel-ixp42x-arcom-vulcan.dtb \ + intel-ixp42x-gateway-7001.dtb diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts new file mode 100644 index 000000000000..765ab36e6f0c --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for ADI Engineering Coyote platform. + * Derived from boardfiles written by MontaVista software. + * Ethernet set-up from OpenWrt. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "ADI Engineering Coyote reference design"; + compatible = "adieng,coyote", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */ + device_type = "memory"; + reg = <0x00000000 0x01000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* These are switched around */ + serial0 = &uart1; + serial1 = &uart0; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 32 MB of Flash in 128 0x20000 sized blocks + * mapped in at CS0 and CS1 + */ + reg = <0 0x00000000 0x2000000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + /* CHECKME: guess this is Redboot FIS */ + fis-index-block = <0x1ff>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from Coyote PCI boardfile. + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */ + <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */ + <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */ + <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ + <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */ + <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ + <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */ + }; + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts new file mode 100644 index 000000000000..6f5b4e4eb1cc --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Arcom/Eurotech Vulcan board. + * This board is a single board computer in the PC/104 form factor based on + * IXP425, and was released around 2005. It previously had the name "Mercury". + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Arcom/Eurotech Vulcan"; + compatible = "arcom,vulcan", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + /* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */ + bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + onewire { + compatible = "w1-gpio"; + gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 32 MB of Flash in 0x20000 byte blocks + * mapped in at CS0 and CS1. + * + * The documentation mentions the existence + * of a 16MB version, which we conveniently + * ignore. Shout if you own one! + */ + reg = <0 0x00000000 0x2000000>; + + /* Expansion bus settings */ + intel,ixp4xx-eb-t3 = <3>; + intel,ixp4xx-eb-byte-access-on-halfword = <1>; + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + fis-index-block = <0x1ff>; + }; + }; + sram@2,0 { + /* 256 KB SDRAM memory at CS2 */ + compatible = "shared-dma-pool"; + device_type = "memory"; + reg = <2 0x00000000 0x40000>; + no-map; + /* Expansion bus settings */ + intel,ixp4xx-eb-t3 = <1>; + intel,ixp4xx-eb-t4 = <2>; + intel,ixp4xx-eb-ahb-split-transfers = <1>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + }; + serial@3,0 { + /* + * 8250-compatible Exar XR16L2551 2 x UART + * + * CHECKME: if special tweaks are needed, then fix the + * operating system to handle it. + */ + compatible = "exar,xr16l2551", "ns8250"; + reg = <3 0x00000000 0x10>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <1843200>; + /* Expansion bus settings */ + intel,ixp4xx-eb-t3 = <3>; + intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */ + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + }; + gpio1: gpio@4,0 { + /* + * MMIO GPIO in one byte + */ + compatible = "arcom,vulcan-gpio"; + reg = <4 0x00000000 0x1>; + /* Expansion bus settings */ + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + }; + watchdog@5,0 { + compatible = "maxim,max6369"; + reg = <5 0x00000000 0x1>; + /* Expansion bus settings */ + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from Vulcan PCI boardfile. + * + * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt + * per slot. This interrupt is shared (OR:ed) by all four pins. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */ + <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */ + <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */ + <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */ + <0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */ + <0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */ + <0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */ + }; + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts new file mode 100644 index 000000000000..b9d46eb06507 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for D-Link DSM-G600 revision A based on IXP420 + * NOTE: revision B of this device uses PowerPC and is NOT supported by + * this device tree. + * + * Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo + * and Michael Westerhof. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "D-Link DSM-G600 rev A"; + compatible = "dlink,dsm-g600-a", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led-power { + label = "dsmg600:green:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-wlan { + label = "dsmg600:green:wlan"; + /* CHECKME: flagged as active low in the old board file */ + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + /* We don't have WLAN trigger in the kernel (yet) */ + linux,default-trigger = "netdev"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys_polled { + compatible = "gpio-keys-polled"; + + /* + * According to the board file this key cannot handle interrupts and + * need to be polled. Investigate if this is really the case or if + * this can be moved adjacent to the ordinary gpio-keys above. + */ + button-power { + wakeup-source; + linux,code = ; + label = "power"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + timeout-ms = <5000>; + }; + + soc { + bus@c4000000 { + /* The first 16MB region at CS0 on the expansion bus */ + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 16 MB of Flash in 128 0x20000 sized blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* + * A boot log says the directory is at 0xfe0000 + * 0x7f * 0x20000 = 0xfe0000 + */ + fis-index-block = <0x7f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from DSM-G600 PCI boardfile (dsmg600-pci.c) + * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3. + * Only slot 3 have three IRQs. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */ + <0x1800 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */ + <0x1800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */ + /* IDSEL 4 */ + <0x2000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */ + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts new file mode 100644 index 000000000000..5a5e16cc7335 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Freecom FSG-3 router. + * This machine is based on IXP425. + * This device tree is inspired by the board file by Rod Whitby. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Freecom FSG-3"; + compatible = "freecom,fsg-3", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB memory */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + /* Boot from the first partition on the hard drive */ + bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-sync { + wakeup-source; + /* Closest approximation of what the key should do */ + linux,code = ; + label = "sync"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + button-reset { + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + button-usb { + wakeup-source; + /* Unplug USB, closest approximation of what the key should do */ + linux,code = ; + label = "usb"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + hwmon@28 { + /* + * Temperature sensor and fan control chip. + * + * TODO: create a proper device tree binding for + * the sensor and temperature zone and create a + * zone with fan control. + */ + compatible = "winbond,w83781d"; + reg = <0x28>; + }; + rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 4 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x400000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x3e0000 */ + fis-index-block = <0x1f>; + }; + }; + + /* Small syscon with some LEDs at CS2 */ + syscon@2,0 { + compatible = "freecom,fsg-cs2-system-controller", "syscon"; + reg = <2 0x0 0x200>; + reg-io-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <2 0x0 0x0 0x200>; + + led@0,0 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x01>; + label = "fsg:blue:wlan"; + linux,default-trigger = "wlan"; + default-state = "on"; + }; + led@0,1 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x02>; + label = "fsg:blue:wan"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,2 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:sata"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,3 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:usb"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,4 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x08>; + label = "fsg:blue:sync"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,5 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x10>; + label = "fsg:blue:ring"; + linux,default-trigger = ""; + default-state = "on"; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Written based on the FSG-3 PCI boardfile. + * We have slots 12, 13 & 14 (IDSEL) with one IRQ each. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 12 */ + <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ + <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ + <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ + <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ + /* IDSEL 13 */ + <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ + <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ + <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ + <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ + /* IDSEL 14 */ + <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ + <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ + <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ + <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ + }; + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts new file mode 100644 index 000000000000..4d70f6afd13a --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Gateway 7001 AP based on IXP422 + * Derived from boardfiles written by Imre Kaloz + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Gateway 7001 AP"; + compatible = "gateway,7001", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* second UART is the primary console */ + serial0 = &uart1; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of flash + */ + reg = <0 0x00000000 0x800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */ + <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */ + <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ + }; + + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts new file mode 100644 index 000000000000..97e3f25bb210 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Gateworks Avila GW2348 board. + * This machine is based on IXP425. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Gateworks Avila GW2348"; + compatible = "gateworks,gw2348", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led-user { + label = "gw2348:green:user"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + hwmon@28 { + compatible = "adi,ad7418"; + reg = <0x28>; + }; + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + eeprom@51 { + compatible = "atmel,24c08"; + reg = <0x51>; + pagesize = <16>; + size = <1024>; + read-only; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + ide@1,0 { + compatible = "intel,ixp4xx-compact-flash"; + /* + * Set up expansion bus config to a really slow timing. + * The CF driver will dynamically reconfigure these timings + * depending on selected PIO mode (0-4). + */ + intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase + intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase + intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase + intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase + intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase + intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type + intel,ixp4xx-eb-byte-access-on-halfword = <1>; + intel,ixp4xx-eb-mux-address-and-data = <0>; + intel,ixp4xx-eb-ahb-split-transfers = <0>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + /* First register set is CMD second is CTL (notice it uses CS2) */ + reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>; + interrupt-parent = <&gpio0>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + }; + /* + * FIXME: Latch LEDs or extra UARTs at CS4 + */ + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from Avila PCI boardfile. + * + * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ + <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ + <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ + /* IDSEL 4 */ + <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ + <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ + <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ + <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ + }; + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts new file mode 100644 index 000000000000..9ec0169bacf8 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Goramo MultiLink Router + * There are two variants: + * - MultiLink Basic (a box) + * - MultiLink Max (19" rack mount) + * This device tree supports MultiLink Basic. + * This machine is based on IXP425. + * This is one of the few devices supporting the IXP4xx High-Speed Serial + * (HSS) link for a V.35 WAN interface. + * The hardware originates in Poland. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Goramo MultiLink Router"; + compatible = "goramo,multilink-router", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* + * 64 MB of RAM according to the manual. The MultiLink + * Max has 128 MB. + */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + /* + * 74HC4094 which is used as a rudimentary GPIO expander + * FIXME: + * - Create device tree bindings for this as GPIO expander + * - Write a pure DT GPIO driver using these bindings + * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) + */ + gpio_74: gpio-74hc4094 { + compatible = "nxp,74hc4094"; + cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + /* oe-gpios is optional */ + gpio-controller; + #gpio-cells = <2>; + /* We are not cascaded */ + registers-number = <1>; + gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N", + "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET", + "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N"; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. + * The slots have Ethernet, Ethernet, NEC and MPCI. + * The IDSELs are 11, 12, 13, 14. + */ + interrupt-map = + /* IDSEL 11 - Ethernet A */ + <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ + <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ + <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */ + <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */ + /* IDSEL 12 - Ethernet B */ + <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ + <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ + <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ + <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ + /* IDSEL 13 - MPCI */ + <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */ + <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */ + <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */ + <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */ + /* IDSEL 14 - NEC */ + <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */ + <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */ + <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */ + <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */ + }; + + /* HSS links */ + npe@c8006000 { + hss@0 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 12>; + intel,queue-chl-txready = <&qmgr 34>; + intel,queue-pkt-rx = <&qmgr 13>; + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; + intel,queue-pkt-txdone = <&qmgr 22>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; + }; + hss@1 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 10>; + intel,queue-chl-txready = <&qmgr 35>; + intel,queue-pkt-rx = <&qmgr 0>; + intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>; + intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>; + intel,queue-pkt-txdone = <&qmgr 9>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>; + }; + }; + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 32>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 33>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts new file mode 100644 index 000000000000..8da6823e1dbe --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Iomega NAS 100D + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Iomega NAS 100D"; + compatible = "iom,nas-100d", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led-wlan { + label = "nas100d:red:wlan"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + /* We don't have WLAN trigger in the kernel (yet) */ + linux,default-trigger = "netdev"; + }; + led-disk { + label = "nas100d:red:disk"; + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "disk-activity"; + }; + led-power { + label = "nas100d:red:power"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-power { + wakeup-source; + linux,code = ; + label = "power"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + button-reset { + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + }; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + timeout-ms = <5000>; + }; + + soc { + bus@c4000000 { + /* The first 16MB region at CS0 on the expansion bus */ + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 0x20000 byte blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x800000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from NAS 100D PCI boardfile (nas100d-pci.c) + * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */ + }; + + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts new file mode 100644 index 000000000000..194945748dc3 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane + * processor reference design. + * + * This platform has the codename "Richfield". + * + * This machine is based on a 533 MHz IXP425. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include "intel-ixp4xx-reference-design.dtsi" +#include + +/ { + model = "Intel IXDP425/IXCDP1100 Richfield Reference Design"; + compatible = "intel,ixdp425", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + }; + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts new file mode 100644 index 000000000000..7011fea6205b --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Intel IXDPG425 reference design. + * Derived from boardfiles written by MontaVista software. + * Ethernet set-up from OpenWrt. + * + * The device has 4 x FXS RJ11 ports for analog phones for + * internet telephony. (Not supported yet.) + * + * The device has 9 status LEDs we do not support yet. + * + * This device is very similar to ADI engingeering Coyote. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Intel IXDPG425 reference design"; + compatible = "intel,ixdpg425", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * CHECKME: the product brief says 16MB in a flash + * socket. + */ + reg = <0 0x00000000 0x1000000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + /* CHECKME: guess this is Redboot FIS */ + fis-index-block = <0x7f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from IXDPG425 PCI boardfile. + * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ + * for 12 & 13 and one for 14. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 12 */ + <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */ + <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */ + <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */ + <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */ + /* IDSEL 13 */ + <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ + <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ + <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ + <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ + /* IDSEL 14 */ + <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ + <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ + <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ + <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ + }; + + /* + * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind + * of Realtek DSA switch on the board. + */ + + /* EthB */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts new file mode 100644 index 000000000000..da1e93212b86 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Linksys NSLU2 + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)"; + compatible = "linksys,nslu2", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led-status { + label = "nslu2:red:status"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-ready { + label = "nslu2:green:ready"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + led-disk-1 { + label = "nslu2:green:disk-1"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-disk-2 { + label = "nslu2:green:disk-2"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-power { + wakeup-source; + linux,code = ; + label = "power"; + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + }; + button-reset { + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6f { + compatible = "xicor,x1205"; + reg = <0x6f>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + timeout-ms = <5000>; + }; + + gpio-beeper { + compatible = "gpio-beeper"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + + soc { + bus@c4000000 { + /* The first 16MB region at CS0 on the expansion bus */ + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 0x20000 byte blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x800000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant + * We have slots (IDSEL) 1, 2 and 3. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ + <0x1000 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ + <0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ + <0x1800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */ + }; + + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts new file mode 100644 index 000000000000..4aba9e0214a0 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Linksys WRV54G router + * Also known as Gemtek GTWX5715 + * Based on a board file by George T. Joseph and other patches. + * This machine is based on IXP425. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Linksys WRV54G / Gemtek GTWX5715"; + compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB memory */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* UART2 is the primary console */ + serial0 = &uart1; + serial1 = &uart0; + }; + + /* There is an unpopulated LED slot (3) connected to GPIO 8 */ + leds { + compatible = "gpio-leds"; + led-power { + label = "wrv54g:yellow:power"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-wireless { + label = "wrv54g:yellow:wireless"; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + led-internet { + label = "wrv54g:yellow:internet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + led-dmz { + label = "wrv54g:green:dmz"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + /* This set-up comes from an OpenWrt patch */ + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + switch@0 { + compatible = "micrel,ks8995"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 8 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x00800000>; + + partitions { + compatible = "fixed-partitions"; + /* + * Partition info from a boot log + * CHECKME: not using redboot? FIS index 0x3f @7e00000? + */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x0 0x140000>; + read-only; + }; + partition@140000 { + label = "linux"; + reg = <0x140000 0x100000>; + read-only; + }; + partition@240000 { + label = "root"; + reg = <0x240000 0x480000>; + read-write; + }; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. + * Derived from the GTWX5715 PCI boardfile. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 0 */ + <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */ + <0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */ + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */ + }; + + /* + * EthB - connected to the KS8995 switch ports 1-4 + * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to + * all four switch ports, also using an out of tree multiphy patch. + * Do we need a new binding and property for this? + */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy4>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Should be ports 1-4 on the KS8995 switch */ + phy4: ethernet-phy@4 { + reg = <4>; + }; + + /* Should be port 5 on the KS8995 switch */ + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + + /* EthC - connected to KS8995 switch port 5 */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts new file mode 100644 index 000000000000..19d56e9aec9d --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Netgear WG302v2 based on IXP422BB + * Derived from boardfiles written by Imre Kaloz + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Netgear WG302 v1"; + compatible = "netgear,wg302v1", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM according to boot arguments */ + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + /* The RedBoot comes up in 9600 baud so let's keep this */ + bootargs = "console=ttyS0,9600n8"; + stdout-path = "uart1:9600n8"; + }; + + aliases { + /* These are switched around */ + serial0 = &uart1; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 64 0x20000 sized blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */ + <0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */ + <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ + <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ + <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ + }; + + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy30>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy30: ethernet-phy@30 { + reg = <30>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts new file mode 100644 index 000000000000..c550c421b659 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Corentin Labbe + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" + +/ { + model = "Welltech EPBX100"; + compatible = "welltech,epbx100", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 16 MB of Flash + */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "zImage"; + reg = <0x00080000 0x00100000>; + read-only; + }; + partition@180000 { + label = "ramdisk"; + reg = <0x00180000 0x00300000>; + read-only; + }; + partition@480000 { + label = "User"; + reg = <0x00480000 0x00b60000>; + read-only; + }; + partition@fe0000 { + label = "FIS directory"; + reg = <0x00fe0000 0x001f000>; + read-only; + }; + partition@fff000 { + label = "RedBoot config"; + reg = <0x00fff000 0x0001000>; + read-only; + }; + }; + }; + }; + + /* LAN port */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi new file mode 100644 index 000000000000..84cee8ec3ab8 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Intel XScale Network Processors + * in the IXP 42x series. This series has 32 interrupts. + */ +#include "intel-ixp4xx.dtsi" + +/ { + soc { + bus@c4000000 { + compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; + reg = <0xc4000000 0x30>; + }; + + pci@c0000000 { + compatible = "intel,ixp42x-pci"; + }; + + interrupt-controller@c8003000 { + compatible = "intel,ixp42x-interrupt"; + }; + + /* + * This is the USB Device Mode (UDC) controller, which is used + * to present the IXP4xx as a device on a USB bus. + */ + usb@c800b000 { + compatible = "intel,ixp4xx-udc"; + reg = <0xc800b000 0x1000>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts new file mode 100644 index 000000000000..1db849515f9e --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Gateworks IXP43x-based Cambria GW2358 + */ + +/dts-v1/; + +#include "intel-ixp43x.dtsi" + +/ { + model = "Gateworks Cambria GW2358"; + compatible = "gateworks,gw2358", "intel,ixp43x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 128 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led-user { + label = "gw2358:green:LED"; + gpios = <&pld1 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + hwmon@28 { + compatible = "adi,ad7418"; + reg = <0x28>; + }; + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + eeprom@51 { + compatible = "atmel,24c08"; + reg = <0x51>; + pagesize = <16>; + size = <1024>; + read-only; + }; + pld0: pld@56 { + compatible = "gateworks,pld-gpio"; + reg = <0x56>; + gpio-controller; + #gpio-cells = <2>; + }; + /* This PLD just handles the LED and user button */ + pld1: pld@57 { + compatible = "gateworks,pld-gpio"; + reg = <0x57>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* + * 32 MB of Flash in 0x20000 byte blocks + * mapped in at CS0 and CS1 + */ + reg = <0 0x00000000 0x2000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x1fe0000 */ + fis-index-block = <0xff>; + }; + }; + ide@3,0 { + compatible = "intel,ixp4xx-compact-flash"; + /* + * Set up expansion bus config to a really slow timing. + * The CF driver will dynamically reconfigure these timings + * depending on selected PIO mode (0-4). + */ + intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase + intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase + intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase + intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase + intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase + intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type + intel,ixp4xx-eb-byte-access-on-halfword = <1>; + intel,ixp4xx-eb-mux-address-and-data = <0>; + intel,ixp4xx-eb-ahb-split-transfers = <0>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + /* First register set is CMD second is CTL */ + reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>; + interrupt-parent = <&gpio0>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * In the boardfile for the Cambria from OpenWRT the interrupts + * are assigned one per IDSEL, so all 4 interrupts from IDSEL + * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2 + * connected to IRQ 10 etc. I find this highly unlikely so I + * have instead assumed that they are rotated (swizzled) like + * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ + <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ + <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ + /* IDSEL 4 */ + <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */ + <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ + <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ + <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */ + /* IDSEL 6 */ + <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */ + <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */ + <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */ + <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */ + /* IDSEL 15 */ + <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */ + <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ + <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ + <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */ + }; + + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + + ethernet@c800c000 { + status = "okay"; + queue-rx = <&qmgr 2>; + queue-txready = <&qmgr 19>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + intel,npe-handle = <&npe 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts new file mode 100644 index 000000000000..4703a8b24765 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Intel KIXRP435 Control Plane + * processor reference design. + */ + +/dts-v1/; + +#include "intel-ixp43x.dtsi" +#include "intel-ixp4xx-reference-design.dtsi" +#include + +/ { + model = "Intel KIXRP435 Reference Design"; + compatible = "intel,kixrp435", "intel,ixp43x"; + #address-cells = <1>; + #size-cells = <1>; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + }; + + /* CHECKME: ethernet set-up taken from Gateworks Cambria */ + ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + + ethernet@c800c000 { + status = "okay"; + queue-rx = <&qmgr 2>; + queue-txready = <&qmgr 19>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + intel,npe-handle = <&npe 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi new file mode 100644 index 000000000000..60bf9903e0f8 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Intel XScale Network Processors + * in the IXP 43x series. This series has 64 interrupts and adds a few more + * peripherals over the 42x series. + */ +#include "intel-ixp4xx.dtsi" + +/ { + soc { + bus@c4000000 { + compatible = "intel,ixp43x-expansion-bus-controller", "syscon"; + /* Uses at least up to 0x230 */ + reg = <0xc4000000 0x1000>; + }; + + pci@c0000000 { + compatible = "intel,ixp43x-pci"; + }; + + interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi new file mode 100644 index 000000000000..1dd4a65cb7a6 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Intel XScale Network Processors + * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a + * few more peripherals over the 42x and 43x series so this extends the + * basic IXP4xx DTSI. + */ +#include "intel-ixp4xx.dtsi" + +/ { + soc { + bus@c4000000 { + compatible = "intel,ixp46x-expansion-bus-controller", "syscon"; + /* Uses at least up to 0x124 */ + reg = <0xc4000000 0x1000>; + }; + + rng@70002100 { + compatible = "intel,ixp46x-rng"; + reg = <0x70002100 4>; + }; + + interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + }; + + /* + * This is the USB Device Mode (UDC) controller, which is used + * to present the IXP4xx as a device on a USB bus. + */ + usb@c800b000 { + compatible = "intel,ixp4xx-udc"; + reg = <0xc800b000 0x1000>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c@c8011000 { + compatible = "intel,ixp4xx-i2c"; + reg = <0xc8011000 0x18>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + /* This is known as EthB1 */ + ethernet@c800d000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800d000 0x1000>; + status = "disabled"; + intel,npe = <1>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB2 */ + ethernet@c800e000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800e000 0x1000>; + status = "disabled"; + intel,npe = <2>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB3 */ + ethernet@c800f000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800f000 0x1000>; + status = "disabled"; + intel,npe = <3>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + ptp-timer@c8010000 { + compatible = "intel,ixp46x-ptp-timer"; + reg = <0xc8010000 0x1000>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "master", "slave"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts new file mode 100644 index 000000000000..a062cd1a6588 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Intel IXDP465 Control Plane processor reference + * design, codename "BMP". + */ + +/dts-v1/; + +#include "intel-ixp45x-ixp46x.dtsi" +#include "intel-ixp4xx-reference-design.dtsi" +#include + +/ { + model = "Intel IXDP465 BMP Reference Design"; + compatible = "intel,ixdp465", "intel,ixp46x"; + #address-cells = <1>; + #size-cells = <1>; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 32 MB of Flash mapped in at CS0 and CS1 */ + reg = <0 0x00000000 0x2000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x1fe0000 */ + fis-index-block = <0xff>; + }; + }; + }; + /* TODO: configure ethernet etc */ + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi new file mode 100644 index 000000000000..31c0a69771c4 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree include file for Intel reference designs for the + * XScale Network Processors in the IXP 4xx series. Common device + * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465. + */ + +/ { + memory@0 { + /* + * The board supports up to 256 MB of memory. Here we put in + * 64 MB and this may be modified by the boot loader. + */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + /* + * Philips PCF8582C-2T/03 512byte I2C EEPROM + * should behave like an Atmel 24c04. + */ + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + size = <512>; + read-only; + }; + }; + + soc { + bus@c4000000 { + /* Flash memory defined per-variant */ + nand-controller@3,0 { + /* Some designs have a NAND on CS3 enable it here if present */ + status = "disabled"; + + /* + * gen_nand needs to be extended and documented to get + * command byte = 1 and address byte = 2 from the device + * tree. + */ + compatible = "gen_nand"; + + /* Expansion bus set-up */ + intel,ixp4xx-eb-t1 = <0>; + intel,ixp4xx-eb-t2 = <0>; + intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase + intel,ixp4xx-eb-t4 = <0>; + intel,ixp4xx-eb-t5 = <0>; + intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type + intel,ixp4xx-eb-byte-access-on-halfword = <0>; + intel,ixp4xx-eb-mux-address-and-data = <0>; + intel,ixp4xx-eb-ahb-split-transfers = <0>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + + /* 512 bytes memory window */ + reg = <3 0x00000000 0x200>; + nand-on-flash-bbt; + nand-ecc-mode = "soft_bch"; + nand-ecc-step-size = <512>; + nand-ecc-strength = <4>; + nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */ + + label = "ixp400 NAND"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + fs@0 { + label = "ixp400 NAND FS 0"; + reg = <0x0 0x800000>; + }; + fs@800000 { + label = "ixp400 NAND FS 1"; + reg = <0x800000 0x0>; + }; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from IXDP425 PCI boardfile. + * PCI slots on the BIXMB425BD base card. + * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ + <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ + <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ + /* IDSEL 4 */ + <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ + <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ + <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ + <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi new file mode 100644 index 000000000000..51a716c59669 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Intel XScale Network Processors + * in the IXP 4xx series. + */ +#include +#include + +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + interrupt-parent = <&intcon>; + + /* + * The IXP4xx expansion bus is a set of up to 7 each up to 16MB + * windows in the 256MB space from 0x50000000 to 0x5fffffff. + */ + bus@c4000000 { + /* compatible and reg filled in by per-soc device tree */ + native-endian; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x01000000>, + <1 0x0 0x51000000 0x01000000>, + <2 0x0 0x52000000 0x01000000>, + <3 0x0 0x53000000 0x01000000>, + <4 0x0 0x54000000 0x01000000>, + <5 0x0 0x55000000 0x01000000>, + <6 0x0 0x56000000 0x01000000>, + <7 0x0 0x57000000 0x01000000>; + dma-ranges = <0 0x0 0x50000000 0x01000000>, + <1 0x0 0x51000000 0x01000000>, + <2 0x0 0x52000000 0x01000000>, + <3 0x0 0x53000000 0x01000000>, + <4 0x0 0x54000000 0x01000000>, + <5 0x0 0x55000000 0x01000000>, + <6 0x0 0x56000000 0x01000000>, + <7 0x0 0x57000000 0x01000000>; + }; + + qmgr: queue-manager@60000000 { + compatible = "intel,ixp4xx-ahb-queue-manager"; + reg = <0x60000000 0x4000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci@c0000000 { + /* compatible filled in by per-soc device tree */ + reg = <0xc0000000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>, + <10 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + status = "disabled"; + + ranges = + /* + * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff + * done in 4 chunks of 16MB each. + */ + <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, + /* 64KB I/O space at 0x4c000000 */ + <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; + + /* + * This needs to map to the start of physical memory so + * PCI devices can see all (hopefully) memory. This is done + * using 4 1:1 16MB windows, so the RAM should not be more than + * 64 MB for this to work. If your memory is anywhere else + * than at 0x0 you need to alter this. + */ + dma-ranges = + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; + + /* Each unique DTS using PCI must specify the swizzling */ + }; + + uart0: serial@c8000000 { + compatible = "intel,xscale-uart"; + reg = <0xc8000000 0x1000>; + /* + * The reg-offset and reg-shift is a side effect + * of running the platform in big endian mode. + */ + reg-offset = <3>; + reg-shift = <2>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <14745600>; + no-loopback-test; + }; + + uart1: serial@c8001000 { + compatible = "intel,xscale-uart"; + reg = <0xc8001000 0x1000>; + /* + * The reg-offset and reg-shift is a side effect + * of running the platform in big endian mode. + */ + reg-offset = <3>; + reg-shift = <2>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <14745600>; + no-loopback-test; + }; + + gpio0: gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + intcon: interrupt-controller@c8003000 { + /* + * Note: no compatible string. The subvariant of the + * chip needs to define what version it is. The + * location of the interrupt controller is fixed in + * memory across all variants. + */ + reg = <0xc8003000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer@c8005000 { + compatible = "intel,ixp4xx-timer"; + reg = <0xc8005000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; + + npe: npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + /* NPE-A contains two high-speed serial links */ + hss@0 { + compatible = "intel,ixp4xx-hss"; + reg = <0>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; + + hss@1 { + compatible = "intel,ixp4xx-hss"; + reg = <1>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; + + /* NPE-C contains a crypto accelerator */ + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; + }; + + /* This is known as EthB */ + ethernet@c8009000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc8009000 0x1000>; + status = "disabled"; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + intel,npe-handle = <&npe 1>; + }; + + /* This is known as EthC */ + ethernet@c800a000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800a000 0x1000>; + status = "disabled"; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 2>; + }; + + /* This is known as EthA */ + ethernet@c800c000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800c000 0x1000>; + status = "disabled"; + intel,npe = <0>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/Makefile b/arch/arm/boot/dts/intel/pxa/Makefile new file mode 100644 index 000000000000..24d5240f08e7 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PXA) += \ + pxa300-raumfeld-connector.dtb \ + pxa300-raumfeld-controller.dtb \ + pxa300-raumfeld-speaker-l.dtb \ + pxa300-raumfeld-speaker-m.dtb \ + pxa300-raumfeld-speaker-one.dtb \ + pxa300-raumfeld-speaker-s.dtb diff --git a/arch/arm/boot/dts/intel/pxa/pxa25x.dtsi b/arch/arm/boot/dts/intel/pxa/pxa25x.dtsi new file mode 100644 index 000000000000..5f8300e356ad --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa25x.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Robert Jarzmik + */ +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa-clock.h" + +/ { + model = "Marvell PXA25x family SoC"; + compatible = "marvell,pxa250"; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa250-core-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + + /* timer oscillator */ + clktimer: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3686400>; + clock-output-names = "ostimer"; + }; + }; + + pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <16>; + dma-channels = <16>; + #dma-requests = <40>; + dma-requests = <40>; + status = "okay"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <32>; + }; + + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa25x-pinctrl"; + }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa25x-gpio"; + gpio-ranges = <&pinctrl 0 0 84>; + clocks = <&clks CLK_NONE>; + }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + + rtc@40900000 { + clocks = <&clks CLK_OSC32k768>; + }; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clktimer>; + status = "okay"; + }; + + pxa250_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp-99532800 { + opp-hz = /bits/ 64 <99532800>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp-199065600 { + opp-hz = /bits/ 64 <199065600>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp-298598400 { + opp-hz = /bits/ 64 <298598400>; + opp-microvolt = <1100000 1045000 1650000>; + clock-latency-ns = <20>; + }; + opp-398131200 { + opp-hz = /bits/ 64 <398131200>; + opp-microvolt = <1300000 1235000 1650000>; + clock-latency-ns = <20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa27x.dtsi b/arch/arm/boot/dts/intel/pxa/pxa27x.dtsi new file mode 100644 index 000000000000..a2cbfb3be609 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa27x.dtsi @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* The pxa3xx skeleton simply augments the 2xx version */ +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa-clock.h" + +/ { + model = "Marvell PXA27x familiy SoC"; + compatible = "marvell,pxa27x"; + + pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <32>; + dma-channels = <32>; + #dma-requests = <75>; + dma-requests = <75>; + status = "okay"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <34>; + }; + + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa27x-pinctrl"; + }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa27x-gpio"; + gpio-ranges = <&pinctrl 0 0 128>; + clocks = <&clks CLK_NONE>; + }; + + usb0: usb@4c000000 { + compatible = "marvell,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + clocks = <&clks CLK_USBHOST>; + status = "disabled"; + }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + + pwm2: pwm@40c00000 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40c00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; + + pwm3: pwm@40c00010 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40c00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + + pwri2c: i2c@40f00180 { + compatible = "mrvl,pxa-i2c"; + reg = <0x40f00180 0x24>; + interrupts = <6>; + clocks = <&clks CLK_PWRI2C>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + pxa27x_udc: udc@40600000 { + compatible = "marvell,pxa270-udc"; + reg = <0x40600000 0x10000>; + interrupts = <11>; + clocks = <&clks CLK_USB>; + status = "disabled"; + }; + + keypad: keypad@41500000 { + compatible = "marvell,pxa27x-keypad"; + reg = <0x41500000 0x4c>; + interrupts = <4>; + clocks = <&clks CLK_KEYPAD>; + status = "disabled"; + }; + + pxa_camera: imaging@50000000 { + compatible = "marvell,pxa270-qci"; + reg = <0x50000000 0x1000>; + interrupts = <33>; + dmas = <&pdma 68 0 /* Y channel */ + &pdma 69 0 /* U channel */ + &pdma 70 0>; /* V channel */ + dma-names = "CI_Y", "CI_U", "CI_V"; + + clocks = <&clks CLK_CAMERA>; + clock-names = "ciclk"; + clock-frequency = <5000000>; + clock-output-names = "qci_mclk"; + + status = "disabled"; + }; + + rtc@40900000 { + clocks = <&clks CLK_OSC32k768>; + }; + }; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa270-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clks CLK_OSTIMER>; + status = "okay"; + }; + + pxa270_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp-104000000 { + opp-hz = /bits/ 64 <104000000>; + opp-microvolt = <900000 900000 1705000>; + clock-latency-ns = <20>; + }; + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + opp-microvolt = <1000000 1000000 1705000>; + clock-latency-ns = <20>; + }; + opp-208000000 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1180000 1180000 1705000>; + clock-latency-ns = <20>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1250000 1250000 1705000>; + clock-latency-ns = <20>; + }; + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <1350000 1350000 1705000>; + clock-latency-ns = <20>; + }; + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1450000 1450000 1705000>; + clock-latency-ns = <20>; + }; + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <1550000 1550000 1705000>; + clock-latency-ns = <20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi b/arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi new file mode 100644 index 000000000000..84154c43fe65 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC + * + * Copyright (C) 2011 Marek Vasut + */ + +#include "dt-bindings/clock/pxa-clock.h" + +#define PMGROUP(pin) #pin +#define PMMUX(func, pin, af) \ + mux- ## func { \ + groups = PMGROUP(P ## pin); \ + function = #af; \ + } +#define PMMUX_LPM_LOW(func, pin, af) \ + mux- ## func { \ + groups = PMGROUP(P ## pin); \ + function = #af; \ + low-power-disable; \ + } +#define PMMUX_LPM_HIGH(func, pin, af) \ + mux- ## func { \ + groups = PMGROUP(P ## pin); \ + function = #af; \ + low-power-enable; \ + } + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell PXA2xx family SoC"; + compatible = "marvell,pxa2xx"; + interrupt-parent = <&pxairq>; + + aliases { + serial0 = &ffuart; + serial1 = &btuart; + serial2 = &stuart; + serial3 = &hwuart; + i2c0 = &pwri2c; + i2c1 = &pxai2c1; + }; + + cpus { + cpu { + compatible = "marvell,xscale"; + device_type = "cpu"; + }; + }; + + pxabus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pxairq: interrupt-controller@40d00000 { + #interrupt-cells = <1>; + compatible = "marvell,pxa-intc"; + interrupt-controller; + interrupt-parent; + marvell,intc-nr-irqs = <32>; + reg = <0x40d00000 0xd0>; + }; + + gpio: gpio@40e00000 { + compatible = "mrvl,pxa-gpio"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x40e00000 0x10000>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = <8>, <9>, <10>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; + interrupt-controller; + #interrupt-cells = <0x2>; + ranges; + + gcb0: gpio@40e00000 { + reg = <0x40e00000 0x4>; + }; + + gcb1: gpio@40e00004 { + reg = <0x40e00004 0x4>; + }; + + gcb2: gpio@40e00008 { + reg = <0x40e00008 0x4>; + }; + gcb3: gpio@40e0000c { + reg = <0x40e0000c 0x4>; + }; + }; + + ffuart: serial@40100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40100000 0x30>; + interrupts = <22>; + clocks = <&clks CLK_FFUART>; + status = "disabled"; + }; + + btuart: serial@40200000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40200000 0x30>; + interrupts = <21>; + clocks = <&clks CLK_BTUART>; + status = "disabled"; + }; + + stuart: serial@40700000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40700000 0x30>; + interrupts = <20>; + clocks = <&clks CLK_STUART>; + status = "disabled"; + }; + + hwuart: serial@41600000 { + compatible = "mrvl,pxa-uart"; + reg = <0x41600000 0x30>; + interrupts = <7>; + status = "disabled"; + }; + + pxai2c1: i2c@40301680 { + compatible = "mrvl,pxa-i2c"; + reg = <0x40301680 0x30>; + interrupts = <18>; + clocks = <&clks CLK_I2C>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@41100000 { + compatible = "marvell,pxa-mmc"; + reg = <0x41100000 0x1000>; + interrupts = <23>; + clocks = <&clks CLK_MMC>; + dmas = <&pdma 21 3 + &pdma 22 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtc@40900000 { + compatible = "marvell,pxa-rtc"; + reg = <0x40900000 0x3c>; + interrupts = <30 31>; + }; + + lcdc: lcd-controller@40500000 { + compatible = "marvell,pxa2xx-lcdc"; + reg = <0x44000000 0x10000>; + interrupts = <17>; + clocks = <&clks CLK_LCD>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi new file mode 100644 index 000000000000..147c99191dc2 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "pxa3xx.dtsi" +#include +#include +#include + +/ { + /* Will be overridden by bootloader */ + hw-revision = <0>; + + chosen { + bootargs = "root=ubi0:RootFS rootfstype=ubifs rw ubi.mtd=3"; + stdout-path = &ffuart; + }; + + memory { + device_type = "memory"; + reg = <0xa0000000 0x8000000>; /* 128 MB */ + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8-fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_va_5v0: regulator-va-5v0 { + compatible = "regulator-fixed"; + regulator-name = "va-5v0-fixed-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 124 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + ssp_dai0: ssp-dai0 { + compatible = "mrvl,pxa-ssp-dai"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_dai_pins>; + port = <&ssp1>; + #sound-dai-cells = <0>; + dmas = <&pdma 13 3 + &pdma 14 3>; + dma-names = "rx", "tx"; + clock-names = "extclk"; + }; + + ssp_dai1: ssp-dai1 { + compatible = "mrvl,pxa-ssp-dai"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_dai_pins>; + port = <&ssp2>; + #sound-dai-cells = <0>; + dmas = <&pdma 15 3 + &pdma 16 3>; + dma-names = "rx", "tx"; + clock-names = "extclk"; + }; + + spi: spi { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + gpio-sck = <&gpio 95 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio 98 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio 97 GPIO_ACTIVE_HIGH>; + cs-gpios = < + &gpio 34 GPIO_ACTIVE_HIGH + &gpio 125 GPIO_ACTIVE_HIGH + &gpio 96 GPIO_ACTIVE_HIGH + >; + num-chipselects = <3>; + + dac: dac@2 { + compatible = "ti,dac7512"; + reg = <2>; + spi-max-frequency = <1000000>; + vcc-supply = <®_3v3>; + }; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + on-off { + label = "on_off button"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + rescue-boot { + label = "rescue boot button"; + gpios = <&gpio 115 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + setup { + label = "setup"; + gpios = <&gpio 119 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + rotary: rotary-encoder { + compatible = "rotary-encoder"; + gpios = < + &gpio 19 GPIO_ACTIVE_LOW + &gpio 20 GPIO_ACTIVE_HIGH + >; + linux,axis = ; + rotary-encoder,relative-axis; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a &led_pins_b>; + + left { + label = "raumfeld:1"; + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + }; + + right { + label = "raumfeld:2"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_pins>; + gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + }; + + mmc0_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pwrseq_pins>; + reset-gpios = < + &gpio 113 GPIO_ACTIVE_LOW /* W2W_RESET */ + &gpio 114 GPIO_ACTIVE_LOW /* W2W_PDN */ + >; + }; + + ethernet: ethernet@10000000 { + compatible = "smsc,lan9115"; + pinctrl-names = "default"; + pinctrl-0 = <&smsc_pins &smsc_bus_pins>; + reg = <0x10000000 0x100000>; + phy-mode = "mii"; + interrupt-parent = <&gpio>; + interrupts = <40 IRQ_TYPE_EDGE_FALLING>; + vdd33a-supply = <®_3v3>; + vddvario-supply = <®_1v8>; + reset-gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + reg-io-width = <4>; + smsc,save-mac-address; + smsc,irq-push-pull; + }; +}; + +&ffuart { + status = "okay"; +}; + +&pwri2c { + status = "okay"; + + max8660: regulator@34 { + compatible = "maxim,max8660"; + reg = <0x34>; + + regulators { + regulator-v3 { + regulator-compatible = "V3(DCDC)"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1800000>; + }; + + regulator-v4 { + regulator-compatible = "V4(DCDC)"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1800000>; + }; + + regulator-v5 { + regulator-compatible = "V5(LDO)"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + }; + + reg_vcc_sdio: regulator-v6 { + regulator-compatible = "V6(LDO)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator-v7 { + regulator-compatible = "V7(LDO)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&pxai2c1 { + status = "okay"; + mrvl,i2c-fast-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pxai2c1_pins>; +}; + +&ssp1 { + status = "okay"; +}; + +&ssp2 { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + nand-rb = <0>; + nand-ecc-mode = "hw"; + marvell,nand-keep-config; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0000000 0xa0000>; + read-only; + }; + + partition@a0000 { + label = "BootloaderEnvironment"; + reg = <0x0a0000 0x20000>; + }; + + partition@c0000 { + label = "BootloaderSplashScreen"; + reg = <0x0c0000 0x60000>; + }; + + partition@120000 { + label = "UBI"; + reg = <0x120000 0x7ee0000>; + }; + }; + }; +}; + +&usb0 { + status = "okay"; + marvell,enable-port1; + marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ + pinctrl-names = "default"; + pinctrl-0 = <&pxa3xx_ohci_pins>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + pxa-mmc,detect-delay-ms = <200>; + vmmc-supply = <®_vcc_sdio>; + mmc-pwrseq = <&mmc0_pwrseq>; + non-removable; + bus-width = <4>; +}; + +&pinctrl { + poweroff_pins: poweroff-pins { + pinctrl-single,pins = ; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + led_pins_a: led-pins-a { + pinctrl-single,pins = ; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + led_pins_b: led-pins-b { + pinctrl-single,pins = ; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); + }; + + pxai2c1_pins: pxai2c1-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(21) MFP_AF1 /* I2C_SCL */ + MFP_PIN_PXA300(22) MFP_AF1 /* I2C_SDA */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); + }; + + gpio_keys_pins: gpio-keys-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(14) MFP_AF0 /* on-off */ + MFP_PIN_PXA300(115) MFP_AF0 /* rescue boot */ + MFP_PIN_PXA300(119) MFP_AF0 /* setup */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + spi_pins: spi-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(95) MFP_AF0 /* SCK */ + MFP_PIN_PXA300(97) MFP_AF0 /* MOSI */ + MFP_PIN_PXA300(98) MFP_AF0 /* MISO */ + MFP_PIN_PXA300(34) MFP_AF0 /* CS#0 */ + MFP_PIN_PXA300(125) MFP_AF0 /* CS#1 */ + MFP_PIN_PXA300(96) MFP_AF0 /* CS#2 */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + pxa3xx_ohci_pins: pxa3xx-ohci-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300_2(0) MFP_AF1 /* USBHPEN */ + MFP_PIN_PXA300_2(1) MFP_AF1 /* USBHPWR */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + smsc_pins: smsc-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(39) MFP_AF0 /* RESET */ + MFP_PIN_PXA300(40) MFP_AF0 /* IRQ */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + smsc_bus_pins: smsc-bus-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(1) MFP_AF1 /* nCS2 */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + mmc0_pins: mmc0-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(3) MFP_AF4 /* MMC1_DAT0 */ + MFP_PIN_PXA300(4) MFP_AF4 /* MMC1_DAT1 */ + MFP_PIN_PXA300(5) MFP_AF4 /* MMC1_DAT2 */ + MFP_PIN_PXA300(6) MFP_AF4 /* MMC1_DAT3 */ + MFP_PIN_PXA300(7) MFP_AF4 /* MMC1_CLK */ + MFP_PIN_PXA300(8) MFP_AF4 /* MMC1_CMD */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); + }; + + mmc0_pwrseq_pins: mmc0-pwrseq-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(113) MFP_AF0 /* W2W_RESET */ + MFP_PIN_PXA300(114) MFP_AF0 /* W2W_PDN */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + ssp0_dai_pins: ssp0-dai-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(85) MFP_AF1 /* SSP1_SCLK */ + MFP_PIN_PXA300(86) MFP_AF1 /* SSP1_FRM */ + MFP_PIN_PXA300(87) MFP_AF1 /* SSP1_TXD */ + MFP_PIN_PXA300(88) MFP_AF1 /* SSP1_RXD */ + MFP_PIN_PXA300(89) MFP_AF1 /* SSP1_EXTCLK */ + MFP_PIN_PXA300(90) MFP_AF1 /* SSP1_SYSCLK */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + ssp1_dai_pins: ssp1-dai-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(25) MFP_AF2 /* SSP2_SCLK */ + MFP_PIN_PXA300(26) MFP_AF2 /* SSP2_FRM */ + MFP_PIN_PXA300(27) MFP_AF2 /* SSP2_TXD */ + MFP_PIN_PXA300(29) MFP_AF2 /* SSP2_EXTCLK */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts new file mode 100644 index 000000000000..3e9445419e39 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Connector (PXA3xx)"; + compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300"; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Raumfeld Connector"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&dailink_master_analog>; + frame-master = <&dailink_master_analog>; + mclk-fs = <256>; + + dailink_master_analog: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&cs4270>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + format = "i2s"; + bitclock-master = <&dailink_master_digital>; + frame-master = <&dailink_master_digital>; + mclk-fs = <256>; + + dailink_master_digital: cpu { + sound-dai = <&ssp_dai1>; + }; + + codec { + sound-dai = <&ak4104>; + }; + }; + }; +}; + +&ssp1 { + status = "okay"; +}; + +&ssp2 { + status = "okay"; +}; + +&spi { + ak4104: optical-transmitter@0 { + compatible = "asahi-kasei,ak4104"; + reg = <0>; + vdd-supply = <®_3v3>; + spi-max-frequency = <5000000>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&rotary { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts new file mode 100644 index 000000000000..12b15945ac6d --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" + +/ { + model = "Raumfeld Controller (PXA3xx)"; + compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300"; + + reg_vbatt: regulator-vbatt { + compatible = "regulator-fixed"; + regulator-name = "vbatt-fixed-supply"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + lcd_supply: regulator-va-tft { + compatible = "regulator-fixed"; + regulator-name = "va-tft-fixed-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + onewire { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_pins>; + gpios = < + &gpio 126 GPIO_OPEN_DRAIN /* W1 I/O */ + &gpio 105 GPIO_ACTIVE_HIGH /* pullup */ + >; + + w1_ds2760: slave-ds2760 { + compatible = "maxim,ds2760"; + power-supplies = <&charger>; + }; + }; + + charger: charger { + pinctrl-names = "default"; + pinctrl-0 = <&charger_pins>; + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio 101 GPIO_ACTIVE_LOW>; + }; + + /* + * One of the following two will be set to "okay" by the bootloader, + * depending on the hardware revision. + */ + backlight-controller-pwm { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + pwms = <&pwm0 10000>; + power-supply = <®_vbatt>; + status = "disabled"; + + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + backlight-controller { + compatible = "lltc,lt3593"; + pinctrl-names = "default"; + pinctrl-0 = <<3593_pins>; + lltc,ctrl-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + led { + label = "backlight"; + default-state = "on"; + }; + }; +}; + +®_va_5v0 { + status = "disabled"; +}; + +ðernet { + status = "disabled"; +}; + +&leds { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&pwm0 { + status = "okay"; +}; + +&keys { + pinctrl-0 = <&gpio_keys_pins &dock_detect_pins>; + dock-detect { + label = "dock detect"; + gpios = <&gpio 116 GPIO_ACTIVE_LOW>; + linux,code = ; + }; +}; + +&spi { + accelerometer@1 { + compatible = "st,lis302dl-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&lis302_pins>; + reg = <1>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <104 IRQ_TYPE_EDGE_FALLING>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + }; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_pins>; + lcd-supply = <&lcd_supply>; + + port { + lcdc_out: endpoint { + remote-endpoint = <&panel_in>; + bus-width = <16>; + }; + }; + + panel { + compatible = "sharp,lq043t3dx0-panel"; + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <9009000>; + pixelclk-active = <0>; /* negative edge */ + hactive = <480>; + vactive = <272>; + hsync-len = <41>; + hback-porch = <2>; + hfront-porch = <1>; + vsync-len = <10>; + vback-porch = <3>; + vfront-porch = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdc_out>; + }; + }; + }; +}; + +&gcu { + status = "okay"; +}; + +&pxai2c1 { + touchscreen@a { + compatible = "eeti,exc3000-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&eeti_ts_pins>; + reg = <0xa>; + interrupt-parent = <&gpio>; + interrupts = <32 IRQ_TYPE_EDGE_RISING>; + attn-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-y; + }; +}; + +&pinctrl { + lis302_pins: lis302-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(104) MFP_AF0 /* IRQ */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + eeti_ts_pins: eeti-ts-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(32) MFP_AF0 /* IRQ */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + lt3593_pins: lt3593-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(17) MFP_AF0 /* Backlight */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + pwm0_pins: pwm0-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(17) MFP_AF1 /* PWM */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + w1_pins: w1-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(126) MFP_AF0 /* PWM */ + MFP_PIN_PXA300(105) MFP_AF0 /* PWM */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + charger_pins: charger_pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(31) MFP_AF0 /* PEN2 */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); + pinctrl-single,bias-pullup = MPF_PULL_UP; + }; + + dock_detect_pins: dock_detect_pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(116) MFP_AF0 /* DOCK_DETECT */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); + pinctrl-single,bias-pullup = MPF_PULL_UP; + }; + + lcdc_pins: lcdc-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */ + MFP_PIN_PXA300(55) MFP_AF1 /* LDD_1 */ + MFP_PIN_PXA300(56) MFP_AF1 /* LDD_2 */ + MFP_PIN_PXA300(57) MFP_AF1 /* LDD_3 */ + MFP_PIN_PXA300(58) MFP_AF1 /* LDD_4 */ + MFP_PIN_PXA300(59) MFP_AF1 /* LDD_5 */ + MFP_PIN_PXA300(60) MFP_AF1 /* LDD_6 */ + MFP_PIN_PXA300(61) MFP_AF1 /* LDD_7 */ + MFP_PIN_PXA300(62) MFP_AF1 /* LDD_8 */ + MFP_PIN_PXA300(63) MFP_AF1 /* LDD_9 */ + MFP_PIN_PXA300(64) MFP_AF1 /* LDD_10 */ + MFP_PIN_PXA300(65) MFP_AF1 /* LDD_11 */ + MFP_PIN_PXA300(66) MFP_AF1 /* LDD_12 */ + MFP_PIN_PXA300(67) MFP_AF1 /* LDD_13 */ + MFP_PIN_PXA300(68) MFP_AF1 /* LDD_14 */ + MFP_PIN_PXA300(69) MFP_AF1 /* LDD_15 */ + MFP_PIN_PXA300(70) MFP_AF1 /* LDD_16 */ + MFP_PIN_PXA300(71) MFP_AF1 /* LDD_17 */ + MFP_PIN_PXA300(72) MFP_AF1 /* LCD_FCLK */ + MFP_PIN_PXA300(73) MFP_AF1 /* LCD_LCLK */ + MFP_PIN_PXA300(74) MFP_AF1 /* LCD_PCLK */ + MFP_PIN_PXA300(75) MFP_AF1 /* LCD_BIAS */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts new file mode 100644 index 000000000000..5a0f7f17856f --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Speaker L (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-l-pxa303", "marvell,pxa300"; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts new file mode 100644 index 000000000000..fa10d896282c --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Speaker M (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-m-pxa303", "marvell,pxa300"; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts new file mode 100644 index 000000000000..a70560a8ea92 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" + +/ { + model = "Raumfeld Speaker One (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300"; + + wm8782: wm8782 { + compatible = "wm8782"; + #sound-dai-cells = <0>; + Vdd-supply = <®_3v3>; + Vdda-supply = <®_va_5v0>; + }; + + xo_11mhz: oscillator-11mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + clock-accuracy = <100>; + }; + + xo_audio: clock-gate { + compatible = "gpio-gate-clock"; + pinctrlnames = "default"; + pinctrl-0 = <&xo_audio_pins>; + clocks = <&xo_11mhz>; + #clock-cells = <0>; + enable-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; + }; + + reg_va_30v0: regulator-va-30v0 { + compatible = "regulator-fixed"; + regulator-name = "va-30v0-fixed-supply"; + regulator-min-microvolt = <30000000>; + regulator-max-microvolt = <30000000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Raumfeld Speaker"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&dailink_master_analog_out>; + frame-master = <&dailink_master_analog_out>; + mclk-fs = <256>; + + dailink_master_analog_out: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&sta320>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + format = "i2s"; + bitclock-master = <&dailink_master_analog_in>; + frame-master = <&dailink_master_analog_in>; + mclk-fs = <256>; + + dailink_master_analog_in: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&wm8782>; + }; + }; + }; +}; + +&ssp_dai0 { + clocks = <&xo_audio>; +}; + +&spi { + dac@2 { + compatible = "ti,dac7512"; + reg = <2>; + spi-max-frequency = <1000000>; + vcc-supply = <®_3v3>; + }; +}; + +&rotary { + status = "okay"; +}; + +&pxai2c1 { + sta320: codec@1a { + compatible = "st,sta32x"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&sta320_pins>; + clocks = <&xo_audio>; + clock-names = "xti"; + reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; + Vdda-supply = <®_3v3>; + Vdd3-supply = <®_3v3>; + Vcc-supply = <®_va_30v0>; + #sound-dai-cells = <0>; + st,thermal-warning-adjustment; + st,thermal-warning-recovery; + st,fault-detect-recovery; + st,drop-compensation-ns = <80>; + st,max-power-use-mpcc; + st,invalid-input-detect-mute; + /* 2 (half-bridge) and 1 (full-bridge) on-board power */ + st,output-conf = /bits/ 8 <0x1>; + st,ch1-output-mapping = /bits/ 8 <0>; + st,ch2-output-mapping = /bits/ 8 <1>; + st,ch3-output-mapping = /bits/ 8 <2>; + st,needs_esd_watchdog; + }; +}; + +&pinctrl { + xo_audio_pins: xo-audio-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(111) MFP_AF0 /* ENABLE */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + sta320_pins: sta320-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(120) MFP_AF0 /* CODEC_RESET */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts new file mode 100644 index 000000000000..36e20cbf8704 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Speaker S (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-s-pxa303", "marvell,pxa300"; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi new file mode 100644 index 000000000000..561483b93989 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + xo_27mhz: oscillator-27mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-accuracy = <100>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Raumfeld Speaker"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&dailink_master_analog>; + frame-master = <&dailink_master_analog>; + mclk-fs = <256>; + + dailink_master_analog: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&cs4270>; + }; + }; + }; +}; + +&ssp_dai0 { + clocks = <&max9485 MAX9485_CLKOUT1>; +}; + +&ssp_dai1 { + clocks = <&max9485 MAX9485_CLKOUT1>; +}; + +&pxai2c1 { + cs4270: codec@48 { + compatible = "cirrus,cs4270"; + pinctrl-names = "default"; + pinctrl-0 = <&cs4270_pins>; + reg = <0x48>; + va-supply = <®_va_5v0>; + vd-supply = <®_3v3>; + vlc-supply = <®_3v3>; + reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + + max9485: clock-generator@63 { + compatible = "maxim,max9485"; + pinctrl-names = "default"; + pinctrl-0 = <&max9485_pins>; + reg = <0x63>; + vdd-supply = <®_3v3>; + clock-names = "xclk"; + clocks = <&xo_27mhz>; + reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; + #clock-cells = <1>; + }; +}; + +&pinctrl { + cs4270_pins: cs4270-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(120) MFP_AF0 /* RESET */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + max9485_pins: max9485-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(111) MFP_AF0 /* RESET */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; +}; diff --git a/arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi b/arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi new file mode 100644 index 000000000000..f9c216f91865 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0 +/* The pxa3xx skeleton simply augments the 2xx version */ +#include "pxa2xx.dtsi" + +#define MFP_PIN_PXA300(gpio) \ + ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ + (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ + (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + 0) +#define MFP_PIN_PXA300_2(gpio) \ + ((gpio <= 1) ? (0x674 + 4 * gpio) : \ + (gpio <= 6) ? (0x2dc + 4 * gpio) : \ + 0) + +#define MFP_PIN_PXA310(gpio) \ + ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ + (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ + (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + (gpio <= 262) ? 0 : \ + (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ + 0) +#define MFP_PIN_PXA310_2(gpio) \ + ((gpio <= 1) ? (0x674 + 4 * gpio) : \ + (gpio <= 6) ? (0x2dc + 4 * gpio) : \ + (gpio <= 10) ? (0x52c + 4 * gpio) : \ + 0) + +#define MFP_PIN_PXA320(gpio) \ + ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ + (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ + (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ + (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ + (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ + (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ + (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + 0) +#define MFP_PIN_PXA320_2(gpio) \ + ((gpio <= 3) ? (0x674 + 4 * gpio) : \ + (gpio <= 5) ? (0x284 + 4 * gpio) : \ + 0) + +/* + * MFP Alternate functions for pins having a gpio. + * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > + */ +#define MFP_AF0 (0 << 0) +#define MFP_AF1 (1 << 0) +#define MFP_AF2 (2 << 0) +#define MFP_AF3 (3 << 0) +#define MFP_AF4 (4 << 0) +#define MFP_AF5 (5 << 0) +#define MFP_AF6 (6 << 0) + +/* + * MFP drive strength functions for pins. + * Example of use: pinctrl-single,drive-strength = MFP_DS03X; + */ +#define MFP_DSMSK (0x7 << 10) +#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > +#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > +#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > +#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > +#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > +#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > +#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > +#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > + +/* + * MFP bias pull mode for pins. + * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; + */ +#define MPF_PULL_MSK (0x7 << 13) +#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > +#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > + +/* + * MFP low power mode for pins. + * Example of use: + * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); + * + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) + * + * Input 0 X(0) X(0) X(0) 0 + * Drive 0 0 0 0 X(1) 0 + * Drive 1 0 1 X(1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFP_LPM(x) < (x) MFP_LPM_MSK > + +#define MFP_LPM_MSK 0xe1f0 +#define MFP_LPM_INPUT 0x0000 +#define MFP_LPM_DRIVE_LOW 0x2000 +#define MFP_LPM_DRIVE_HIGH 0x4100 +#define MFP_LPM_PULL_LOW 0x2080 +#define MFP_LPM_PULL_HIGH 0x4180 +#define MFP_LPM_FLOAT 0x0080 + +#define MFP_LPM_EDGE_NONE 0x0000 +#define MFP_LPM_EDGE_RISE 0x0010 +#define MFP_LPM_EDGE_FALL 0x0020 +#define MFP_LPM_EDGE_BOTH 0x0030 + +/ { + model = "Marvell PXA3xx familiy SoC"; + compatible = "marvell,pxa3xx"; + + pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <32>; + dma-channels = <32>; + #dma-requests = <100>; + dma-requests = <100>; + status = "okay"; + }; + + pwri2c: i2c@40f500c0 { + compatible = "mrvl,pwri2c"; + reg = <0x40f500c0 0x30>; + interrupts = <6>; + clocks = <&clks CLK_PWRI2C>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + nand_controller: nand-controller@43100000 { + compatible = "marvell,pxa3xx-nand-controller"; + reg = <0x43100000 90>; + interrupts = <45>; + clocks = <&clks CLK_NAND>; + clock-names = "core"; + dmas = <&pdma 97 3>; + dma-names = "data"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <56>; + }; + + pinctrl: pinctrl@40e10000 { + compatible = "pinconf-single"; + reg = <0x40e10000 0xffff>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; + }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa3xx-gpio"; + reg = <0x40e00000 0x10000>; + clocks = <&clks CLK_GPIO>; + gpio-ranges = <&pinctrl 0 0 128>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; + interrupts = <8>, <9>, <10>; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + mmc0: mmc@41100000 { + compatible = "marvell,pxa-mmc"; + reg = <0x41100000 0x1000>; + interrupts = <23>; + clocks = <&clks CLK_MMC1>; + dmas = <&pdma 21 3 + &pdma 22 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mmc1: mmc@42000000 { + compatible = "marvell,pxa-mmc"; + reg = <0x42000000 0x1000>; + interrupts = <41>; + clocks = <&clks CLK_MMC2>; + dmas = <&pdma 93 3 + &pdma 94 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mmc2: mmc@42500000 { + compatible = "marvell,pxa-mmc"; + reg = <0x42500000 0x1000>; + interrupts = <55>; + clocks = <&clks CLK_MMC3>; + dmas = <&pdma 46 3 + &pdma 47 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usb0: usb@4c000000 { + compatible = "marvell,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + clocks = <&clks CLK_USBH>; + status = "disabled"; + }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + status = "disabled"; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + status = "disabled"; + }; + + pwm2: pwm@40c00000 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40c00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + status = "disabled"; + }; + + pwm3: pwm@40c00010 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40c00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + status = "disabled"; + }; + + ssp1: ssp@41000000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41000000 0x40>; + interrupts = <24>; + clocks = <&clks CLK_SSP1>; + status = "disabled"; + }; + + ssp2: ssp@41700000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41700000 0x40>; + interrupts = <16>; + clocks = <&clks CLK_SSP2>; + status = "disabled"; + }; + + ssp3: ssp@41900000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41900000 0x40>; + interrupts = <0>; + clocks = <&clks CLK_SSP3>; + status = "disabled"; + }; + + ssp4: ssp@41a00000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41a00000 0x40>; + interrupts = <13>; + clocks = <&clks CLK_SSP4>; + status = "disabled"; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clks CLK_OSTIMER>; + status = "okay"; + }; + + gcu: display-controller@54000000 { + compatible = "marvell,pxa300-gcu"; + reg = <0x54000000 0x1000>; + interrupts = <39>; + clocks = <&clks CLK_PXA300_GCU>; + status = "disabled"; + }; + }; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: clocks { + compatible = "marvell,pxa300-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile new file mode 100644 index 000000000000..c467828aeb4b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ + socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_pe1.dtb \ + socfpga_arria10_socdk_nand.dtb \ + socfpga_arria10_socdk_qspi.dtb \ + socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_chameleon96.dtb \ + socfpga_cyclone5_mcvevk.dtb \ + socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ + socfpga_cyclone5_vining_fpga.dtb \ + socfpga_vt.dtb diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi new file mode 100644 index 000000000000..4c1d140f40f8 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -0,0 +1,984 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Altera + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "altr,socfpga-smp"; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + pmu: pmu@ff111000 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 176 4>, <0 177 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; + reg = <0xff111000 0x1000>, + <0xff113000 0x1000>; + }; + + intc: interrupt-controller@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; + reset-names = "dma"; + }; + }; + + base_fpga_region { + compatible = "fpga-region"; + fpga-mgr = <&fpgamgr0>; + + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll@40 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk@48 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk@4c { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk@50 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>, <&osc1>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk@54 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll@80 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk@88 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk@8c { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk@90 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk@94 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk@98 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk@9c { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll@c0 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk@c8 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk@d0 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk@d4 { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&l3_mp_clk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_at_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + }; + + sdmmc_clk_divided: sdmmc_clk_divided { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&sdmmc_clk>; + clk-gate = <0xa0 8>; + fixed-divider = <4>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + + ddr_dqs_clk_gate: ddr_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dqs_clk>; + clk-gate = <0xd8 0>; + }; + + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_2x_dqs_clk>; + clk-gate = <0xd8 1>; + }; + + ddr_dq_clk_gate: ddr_dq_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dq_clk>; + clk-gate = <0xd8 2>; + }; + + h2f_user2_clk: h2f_user2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr2_clk>; + clk-gate = <0xd8 3>; + }; + + }; + }; + + fpga_bridge0: fpga_bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge1: fpga_bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + status = "disabled"; + }; + + fpgamgr0: fpgamgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x4>; + interrupts = <0 175 4>; + }; + + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac_0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; + snps,axi-config = <&socfpga_axi_setup>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac_1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; + snps,axi-config = <&socfpga_axi_setup>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + resets = <&rst I2C0_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + resets = <&rst I2C1_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + resets = <&rst I2C2_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + resets = <&rst I2C3_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + eccmgr: eccmgr { + compatible = "altr,socfpga-ecc-manager"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + l2-ecc@ffd08140 { + compatible = "altr,socfpga-l2-ecc"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; + + ocram-ecc@ffd08144 { + compatible = "altr,socfpga-ocram-ecc"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; + }; + + L2: cache-controller@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <0>; + arm,prefetch-offset = <7>; + }; + + l3regs@ff800000 { + compatible = "altr,l3regs", "syscon"; + reg = <0xff800000 0x1000>; + }; + + mmc: mmc@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; + clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x108 3>; + status = "disabled"; + }; + + nand0: nand@ff900000 { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xff900000 0x100000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0x0 0x90 0x4>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; + status = "disabled"; + }; + + ocram: sram@ffff0000 { + compatible = "mmio-sram"; + reg = <0xffff0000 0x10000>; + }; + + qspi: spi@ff705000 { + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; + status = "disabled"; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + altr,modrst-offset = <0x10>; + }; + + scu: snoop-control-unit@fffec000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffec000 0x100>; + }; + + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + resets = <&rst SDR_RESET>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + spi0: spi@fff00000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff00000 0x1000>; + interrupts = <0 154 4>; + num-cs = <4>; + clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; + reset-names = "spi"; + status = "disabled"; + }; + + spi1: spi@fff01000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff01000 0x1000>; + interrupts = <0 155 4>; + num-cs = <4>; + clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; + reset-names = "spi"; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf01>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + resets = <&rst SPTIMER0_RESET>; + reset-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + resets = <&rst SPTIMER1_RESET>; + reset-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + resets = <&rst OSC1TIMER0_RESET>; + reset-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + resets = <&rst OSC1TIMER1_RESET>; + reset-names = "timer"; + }; + + uart0: serial@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + dmas = <&pdma 28>, + <&pdma 29>; + dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; + }; + + uart1: serial@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + dmas = <&pdma 30>, + <&pdma 31>; + dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; + }; + + usbphy0: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi new file mode 100644 index 000000000000..72c55e5187ca --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -0,0 +1,920 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright Altera Corporation (C) 2014. All rights reserved. + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "altr,socfpga-a10-smp"; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + pmu: pmu@ff111000 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 124 4>, <0 125 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; + reg = <0xff111000 0x1000>, + <0xff113000 0x1000>; + }; + + intc: interrupt-controller@ffffd000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xffffd000 0x1000>, + <0xffffc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, + <0 84 IRQ_TYPE_LEVEL_HIGH>, + <0 85 IRQ_TYPE_LEVEL_HIGH>, + <0 86 IRQ_TYPE_LEVEL_HIGH>, + <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>, + <0 89 IRQ_TYPE_LEVEL_HIGH>, + <0 90 IRQ_TYPE_LEVEL_HIGH>, + <0 91 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; + reset-names = "dma", "dma-ocp"; + }; + }; + + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb_intosc_ls_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s_free_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll@40 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>; + reg = <0x40>; + + main_mpu_base_clk: main_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x140 0 11>; + }; + + main_noc_base_clk: main_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x144 0 11>; + }; + + main_emaca_clk: main_emaca_clk@68 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x68>; + }; + + main_emacb_clk: main_emacb_clk@6c { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x6C>; + }; + + main_emac_ptp_clk: main_emac_ptp_clk@70 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x70>; + }; + + main_gpio_db_clk: main_gpio_db_clk@74 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x74>; + }; + + main_sdmmc_clk: main_sdmmc_clk@78 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk" +; + clocks = <&main_pll>; + reg = <0x78>; + }; + + main_s2f_usr0_clk: main_s2f_usr0_clk@7c { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x7C>; + }; + + main_s2f_usr1_clk: main_s2f_usr1_clk@80 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x80>; + }; + + main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x84>; + }; + + main_periph_ref_clk: main_periph_ref_clk@9c { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x9C>; + }; + }; + + periph_pll: periph_pll@c0 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>, <&main_periph_ref_clk>; + reg = <0xC0>; + + peri_mpu_base_clk: peri_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x140 16 11>; + }; + + peri_noc_base_clk: peri_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x144 16 11>; + }; + + peri_emaca_clk: peri_emaca_clk@e8 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xE8>; + }; + + peri_emacb_clk: peri_emacb_clk@ec { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xEC>; + }; + + peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF0>; + }; + + peri_gpio_db_clk: peri_gpio_db_clk@f4 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF4>; + }; + + peri_sdmmc_clk: peri_sdmmc_clk@f8 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF8>; + }; + + peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xFC>; + }; + + peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x100>; + }; + + peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x104>; + }; + }; + + mpu_free_clk: mpu_free_clk@60 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x60>; + }; + + noc_free_clk: noc_free_clk@64 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x64>; + }; + + s2f_user1_free_clk: s2f_user1_free_clk@104 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x104>; + }; + + sdmmc_free_clk: sdmmc_free_clk@f8 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + fixed-divider = <4>; + reg = <0xF8>; + }; + + l4_sys_free_clk: l4_sys_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&noc_free_clk>; + fixed-divider = <4>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 0 2>; + clk-gate = <0x48 1>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 8 2>; + clk-gate = <0x48 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 16 2>; + clk-gate = <0x48 3>; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&mpu_free_clk>; + fixed-divider = <4>; + clk-gate = <0x48 0>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&sdmmc_free_clk>; + clk-gate = <0xC8 5>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 11>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 10>; + }; + + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xC8 10>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + fixed-divider = <4>; + clk-gate = <0xC8 10>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 9>; + }; + + usb_clk: usb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 8>; + }; + + s2f_usr1_clk: s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&peri_s2f_usr1_clk>; + clk-gate = <0xC8 6>; + }; + }; + }; + + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + reg = <0xff800000 0x2000>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + snps,axi-config = <&socfpga_axi_setup>; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; + reg = <0xff802000 0x2000>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + snps,axi-config = <&socfpga_axi_setup>; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 16>; + reg = <0xff804000 0x2000>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + snps,axi-config = <&socfpga_axi_setup>; + status = "disabled"; + }; + + gpio0: gpio@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02900 0x100>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02a00 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio2: gpio@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02b00 0x100>; + resets = <&rst GPIO2_RESET>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + reset-names = "fpgamgr"; + }; + + i2c0: i2c@ffc02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02200 0x100>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + resets = <&rst I2C0_RESET>; + status = "disabled"; + }; + + i2c1: i2c@ffc02300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02300 0x100>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + resets = <&rst I2C1_RESET>; + status = "disabled"; + }; + + i2c2: i2c@ffc02400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02400 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + resets = <&rst I2C2_RESET>; + status = "disabled"; + }; + + i2c3: i2c@ffc02500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02500 0x100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + resets = <&rst I2C3_RESET>; + status = "disabled"; + }; + + i2c4: i2c@ffc02600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02600 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + resets = <&rst I2C4_RESET>; + status = "disabled"; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x100>; + interrupts = <0 101 4>; + num-cs = <4>; + /*32bit_access;*/ + clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; + reset-names = "spi"; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-cs = <4>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; + reset-names = "spi"; + status = "disabled"; + }; + + sdr: sdr@ffcfb100 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffcfb100 0x80>; + }; + + L2: cache-controller@fffff000 { + compatible = "arm,pl310-cache"; + reg = <0xfffff000 0x1000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; + }; + + mmc: mmc@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <0x400>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; + status = "disabled"; + }; + + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x72000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 99 4>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + }; + + eccmgr: eccmgr { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-a10"; + altr,sdr-syscon = <&sdr>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <49 IRQ_TYPE_LEVEL_HIGH>; + }; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <32 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocram-ecc@ff8c3000 { + compatible = "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8c3000 0x400>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@ff8c0800 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0800 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, + <36 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0c00 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0c00 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, + <37 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + + dma-ecc@ff8c8000 { + compatible = "altr,socfpga-dma-ecc"; + reg = <0xff8c8000 0x400>; + altr,ecc-parent = <&pdma>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <42 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c8800 { + compatible = "altr,socfpga-usb-ecc"; + reg = <0xff8c8800 0x400>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qspi: spi@ff809000 { + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; + reset-names = "qspi", "qspi-ocp"; + status = "disabled"; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x100>; + altr,modrst-offset = <0x20>; + }; + + scu: snoop-control-unit@ffffc000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xffffc000 0x100>; + }; + + sysmgr: sysmgr@ffd06000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd06000 0x300>; + cpu1-start-addr = <0xffd06230>; + }; + + /* Local timer */ + timer@ffffc600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xffffc600 0x100>; + interrupts = <1 13 0xf01>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc02700 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02700 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + resets = <&rst SPTIMER0_RESET>; + reset-names = "timer"; + }; + + timer1: timer1@ffc02800 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02800 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + resets = <&rst SPTIMER1_RESET>; + reset-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd00000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; + resets = <&rst L4SYSTIMER0_RESET>; + reset-names = "timer"; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd00100 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; + resets = <&rst L4SYSTIMER1_RESET>; + reset-names = "timer"; + }; + + uart0: serial@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + resets = <&rst UART0_RESET>; + status = "disabled"; + }; + + uart1: serial@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + resets = <&rst UART1_RESET>; + status = "disabled"; + }; + + usbphy0: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD0_RESET>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD1_RESET>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts new file mode 100644 index 000000000000..422d00cd4c74 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Google Chameleon V3"; + compatible = "google,chameleon-v3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ssm2603: audio-codec@1a { + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&i2c1 { + status = "okay"; + + u80: gpio@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SOM_AUD_MUTE", + "DP1_OUT_CEC_EN", + "DP2_OUT_CEC_EN", + "DP1_SOM_PS8469_CAD", + "DPD_SOM_PS8469_CAD", + "DP_OUT_PWR_EN", + "STM32_RST_L", + "STM32_BOOT0", + + "FPGA_PROT", + "STM32_FPGA_COMM0", + "TP119", + "TP120", + "TP121", + "TP122", + "TP123", + "TP124"; + }; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi new file mode 100644 index 000000000000..41f865c8c098 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ + +#include "socfpga_arria10.dtsi" + +/ { + + model = "Enclustra Mercury AA1"; + compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + serial1 = &uart1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + max-frame-size = <3800>; + + phy-handle = <&phy3>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy3: ethernet-phy@3 { + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + reg = <3>; + }; + }; +}; + +&i2c1 { + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + + isl12022: isl12022@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +/* Following mappings are taken from arria10 socdk dts */ +&mmc { + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <33330000>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts new file mode 100644 index 000000000000..cf533f76a9fd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023 Steffen Trumtrar + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Enclustra Mercury+ PE1"; + compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + serial0 = &uart0; + serial1 = &uart1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi new file mode 100644 index 000000000000..ec7365444a3b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Altera Corporation + */ +#include "socfpga_arria10.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + serial0 = &uart1; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + a10leds { + compatible = "gpio-leds"; + + a10sr_led0 { + label = "a10sr-led0"; + gpios = <&a10sr_gpio 0 1>; + }; + + a10sr_led1 { + label = "a10sr-led1"; + gpios = <&a10sr_gpio 1 1>; + }; + + a10sr_led2 { + label = "a10sr-led2"; + gpios = <&a10sr_gpio 2 1>; + }; + + a10sr_led3 { + label = "a10sr-led3"; + gpios = <&a10sr_gpio 3 1>; + }; + }; + + ref_033v: 033-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + /* + * These skews assume the user's FPGA design is adding 600ps of delay + * for TX_CLK on Arria 10. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + /* low-level active IRQ at GPIO1_5 */ + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + a10sr_rst: reset-controller { + compatible = "altr,a10sr-reset"; + #reset-cells = <1>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + clock-frequency = <100000>; + i2c-sda-falling-time-ns = <6000>; + i2c-scl-falling-time-ns = <6000>; + + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&ref_033v>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + + ltc@5c { + compatible = "ltc2977"; + reg = <0x5c>; + }; + + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts new file mode 100644 index 000000000000..a662df319a84 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Altera Corporation. All rights reserved. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x02500000>; + }; + partition@1c00000 { + label = "Root Filesystem - JFFS2"; + reg = <0x02500000 0x05500000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 000000000000..11ccdc6c2dc6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Intel. All rights reserved. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&qspi { + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <3>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + label = "Boot and fpga data"; + reg = <0x0 0x2720000>; + }; + + partition@qspi-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x2720000 0x58E0000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts new file mode 100644 index 000000000000..d3969367f4b5 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014-2015 Altera Corporation + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&mmc { + status = "okay"; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi new file mode 100644 index 000000000000..40fecde65c54 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2013 Altera Corporation + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: mmc@ff704000 { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts new file mode 100644 index 000000000000..c48385702a85 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 Altera Corporation + */ + +#include "socfpga_arria5.dtsi" + +/ { + model = "Altera SOCFPGA Arria V SoC Development Kit"; + compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + led-hps0 { + label = "hps_led0"; + gpios = <&porta 0 1>; + }; + + led-hps1 { + label = "hps_led1"; + gpios = <&portb 11 1>; + }; + + led-hps2 { + label = "hps_led2"; + gpios = <&porta 17 1>; + }; + + led-hps3 { + label = "hps_led3"; + gpios = <&porta 18 1>; + }; + }; + + regulator_3_3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi new file mode 100644 index 000000000000..305fe207b237 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Altera Corporation + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: mmc@ff704000 { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts new file mode 100644 index 000000000000..76262f1e5e03 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Chameleon96 + * + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Novetech Chameleon96"; + compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x20000000>; /* 512MB */ + }; + + regulator_3_3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "green:user1"; + gpios = <&porta 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "green:user2"; + gpios = <&porta 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "green:user3"; + gpios = <&porta 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + user_led4 { + label = "green:user4"; + gpios = <&portb 3 GPIO_ACTIVE_LOW>; + panic-indicator; + linux,default-trigger = "none"; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&spi0 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; + +&spi1 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&uart0 { + /* On Low speed expansion */ + label = "LS-UART1"; + status = "okay"; +}; + +&uart1 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 000000000000..bedf577cb056 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright Altera Corporation (C) 2015. All rights reserved. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE-0(Atlas)"; + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + led-hps0 { + label = "hps_led0"; + gpios = <&portb 24 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + + max-frame-size = <3800>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + adxl345: adxl345@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi new file mode 100644 index 000000000000..3b9daddf91cd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Marek Vasut + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Aries/DENX MCV"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 GiB */ + }; +}; + +&mmc0 { /* On-SoM eMMC */ + bus-width = <8>; + clk-phase-sd-hs = <0>, <135>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts new file mode 100644 index 000000000000..ceaec29770c6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Marek Vasut + */ + +#include "socfpga_cyclone5_mcv.dtsi" + +/ { + model = "Aries/DENX MCV EVK"; + compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + stmpe-i2c0 = &stmpe1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpio0 { /* GPIO 0 ... 28 */ + status = "okay"; +}; + +&gpio1 { /* GPIO 29 ... 57 */ + status = "okay"; +}; + +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + stmpe1: stmpe811@41 { + compatible = "st,stmpe811"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */ + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + ts,sample-time = <4>; + ts,mod-12b = <1>; + ts,ref-sel = <0>; + ts,adc-freq = <1>; + ts,ave-ctrl = <1>; + ts,touch-det-delay = <3>; + ts,settling = <4>; + ts,fraction-z = <7>; + ts,i-drive = <1>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts new file mode 100644 index 000000000000..c7f5fa0ba0f2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Altera Corporation + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Altera SOCFPGA Cyclone V SoC Development Kit"; + compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + led-hps0 { + label = "hps_led0"; + gpios = <&portb 15 1>; + }; + + led-hps1 { + label = "hps_led1"; + gpios = <&portb 14 1>; + }; + + led-hps2 { + label = "hps_led2"; + gpios = <&portb 13 1>; + }; + + led-hps3 { + label = "hps_led3"; + gpios = <&portb 12 1>; + }; + }; + + regulator_3_3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + +&spi0 { + status = "okay"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts new file mode 100644 index 000000000000..3dd99c7c95e0 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 Steffen Trumtrar + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic SoCkit"; + compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:blue:led0"; + gpios = <&portb 24 0>; /* HPS_GPIO53 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led1 { + label = "hps:blue:led1"; + gpios = <&portb 25 0>; /* HPS_GPIO54 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led2 { + label = "hps:blue:led2"; + gpios = <&portb 26 0>; /* HPS_GPIO55 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led3 { + label = "hps:blue:led3"; + gpios = <&portb 27 0>; /* HPS_GPIO56 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&portc 20 0>; /* HPS_GPI7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; /* SW_LID */ + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&portc 19 0>; /* HPS_GPI6 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x5>; /* SW_DOCK */ + }; + + hps_sw2 { + label = "hps_sw2"; + gpios = <&portc 18 0>; /* HPS_GPI5 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ + }; + + hps_sw3 { + label = "hps_sw3"; + gpios = <&portc 17 0>; /* HPS_GPI4 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xc>; /* SW_ROTATE_LOCK */ + }; + + hps_hkey0 { + label = "hps_hkey0"; + gpios = <&portc 21 1>; /* HPS_GPI8 */ + linux,code = <187>; /* KEY_F17 */ + }; + + hps_hkey1 { + label = "hps_hkey1"; + gpios = <&portc 22 1>; /* HPS_GPI9 */ + linux,code = <188>; /* KEY_F18 */ + }; + + hps_hkey2 { + label = "hps_hkey2"; + gpios = <&portc 23 1>; /* HPS_GPI10 */ + linux,code = <189>; /* KEY_F19 */ + }; + + hps_hkey3 { + label = "hps_hkey3"; + gpios = <&portc 24 1>; /* HPS_GPI11 */ + linux,code = <190>; /* KEY_F20 */ + }; + }; + + regulator_3_3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { /* GPIO 0..29 */ + status = "okay"; +}; + +&gpio1 { /* GPIO 30..57 */ + status = "okay"; +}; + +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + accel1: accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts new file mode 100644 index 000000000000..ca18b959e655 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Steffen Trumtrar + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + aliases { + ethernet0 = &gmac1; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + leds: gpio-leds { + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t82"; + reg = <0x68>; + }; +}; + +&leds { + compatible = "gpio-leds"; + + led0 { + label = "led:green:heartbeat"; + gpios = <&porta 28 1>; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led:green:D7"; + gpios = <&portb 19 1>; + }; + + led2 { + label = "led:green:D8"; + gpios = <&portb 25 1>; + }; +}; + +&mmc { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts new file mode 100644 index 000000000000..2564671fc1c6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Nobuhiro Iwamatsu + */ + +#include "socfpga_cyclone5.dtsi" +#include +#include + +/ { + model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; + compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:green:led0"; + gpios = <&portb 12 GPIO_ACTIVE_LOW>; + }; + + hps_led1 { + label = "hps:green:led1"; + gpios = <&portb 13 GPIO_ACTIVE_LOW>; + }; + + hps_led2 { + label = "hps:green:led2"; + gpios = <&portb 14 GPIO_ACTIVE_LOW>; + }; + + hps_led3 { + label = "hps:green:led3"; + gpios = <&portb 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512a", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts new file mode 100644 index 000000000000..e0630b0eed03 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright (C) 2015 Marek Vasut + */ + +#include "socfpga_cyclone5.dtsi" +#include +#include + +/ { + model = "samtec VIN|ING FPGA"; + compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* + * This allow the ethaddr uboot environment variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + ethernet1 = &gmac0; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_temp0 { + label = "BTN_0"; /* TEMP_OS */ + gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPI5 */ + linux,code = ; + }; + + hps_hkey0 { + label = "GP_SWITCH"; /* GP_SWITCH */ + gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPI6 */ + linux,code = ; + }; + + hps_hkey1 { + label = "RESET_SWITCH"; /* RESET_SWITCH */ + gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPI7 */ + linux,code = ; + }; + + hps_hkey2 { + label = "POWER_DOWN"; /* POWER_DOWN */ + gpios = <&portc 4 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ + linux,code = ; + }; + + hps_hkey3 { + label = "SENSE"; /* SENSE */ + gpios = <&porta 9 GPIO_ACTIVE_LOW>; /* HPS_GPIO9 */ + linux,code = ; + }; + }; + + regulator-usb-nrst { + compatible = "regulator-fixed"; + regulator-name = "usb_nrst"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <10000 10000 10000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <1860>; + }; + }; +}; + +&gpio0 { /* GPIO 0..29 */ + status = "okay"; +}; + +&gpio1 { /* GPIO 30..57 */ + status = "okay"; +}; + +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio: pca9557@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + temp: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + at24@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@6 { /* Backplane EEPROM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + eeprom@51 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@7 { /* Power board EEPROM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + eeprom@51 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; + }; +}; + +&qspi { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128", "jedec,spi-nor"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + m25p,fast-read; + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <1>; /* chip select */ + spi-max-frequency = <100000000>; + m25p,fast-read; + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts new file mode 100644 index 000000000000..845ab2cc5ce6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 Altera Corporation + */ + +/dts-v1/; +#include "socfpga.dtsi" + +/ { + model = "Altera SOCFPGA VT"; + compatible = "altr,socfpga-vt", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 GB */ + }; + + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <10000000>; + }; + }; + }; + + mmc@ff704000 { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff700000 { + phy-mode = "gmii"; + status = "okay"; + }; + + timer0@ffc08000 { + clock-frequency = <7000000>; + }; + + timer1@ffc09000 { + clock-frequency = <7000000>; + }; + + timer2@ffd00000 { + clock-frequency = <7000000>; + }; + + timer3@ffd01000 { + clock-frequency = <7000000>; + }; + + serial@ffc02000 { + clock-frequency = <7372800>; + }; + + serial@ffc03000 { + clock-frequency = <7372800>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd08010>; + }; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "gmii"; +}; diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi deleted file mode 100644 index 4351c5a02fa5..000000000000 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/* - * SSI-SGTL5000 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/ { - aliases { - serial0 = &scif0; - serial3 = &scifb1; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - lcd_backlight: backlight { - compatible = "pwm-backlight"; - - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - }; - - lvds-receiver { - compatible = "ti,ds90cf384a", "lvds-decoder"; - power-supply = <&vcc_3v3_tft1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_receiver_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - port@1 { - reg = <1>; - lvds_receiver_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; - - panel { - compatible = "edt,etm0700g0dh6"; - backlight = <&lcd_backlight>; - power-supply = <&vcc_3v3_tft1>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_receiver_out>; - }; - }; - }; - - reg_1p5v: 1p5v { - compatible = "regulator-fixed"; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - vcc_3v3_tft1: regulator-panel { - compatible = "regulator-fixed"; - - regulator-name = "vcc-3v3-tft1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - startup-delay-us = <500>; - gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&cmt0 { - status = "okay"; -}; - -&du { - status = "okay"; -}; - -&gpio2 { - touch-interrupt-hog { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - input; - }; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p5v>; - }; - - touch: touchpanel@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&vcc_3v3_tft1>; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&lvds_receiver_in>; - }; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pfc { - can0_pins: can0 { - groups = "can0_data_d"; - function = "can0"; - }; - - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - pwm3_pins: pwm3 { - groups = "pwm3"; - function = "pwm3"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scifb1_pins: scifb1 { - groups = "scifb1_data_d", "scifb1_ctrl"; - function = "scifb1"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&pwm3 { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi1>, <&src3>, <&dvc1>; - capture = <&ssi0>, <&src2>, <&dvc0>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifb1 { - pinctrl-0 = <&scifb1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi deleted file mode 100644 index e10f99278c77..000000000000 --- a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/ { - aliases { - serial1 = &scif1; - serial4 = &hscif1; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio0>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&pfc { - can1_pins: can1 { - groups = "can1_data_d"; - function = "can1"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; - function = "du"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data_c", "hscif1_ctrl_c"; - function = "hscif1"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi deleted file mode 100644 index 0397c3423d2d..000000000000 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 clock tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mainmuxclk: mainmuxclk@2310108 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclksys>; - reg = <0x02310108 4>; - bit-shift = <23>; - bit-mask = <1>; - clock-output-names = "mainmuxclk"; - }; - - chipclk1: chipclk1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1"; - }; - - chipclk1rstiso: chipclk1rstiso { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso"; - }; - - gemtraceclk: gemtraceclk@2310120 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310120 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "gemtraceclk"; - }; - - chipstmxptclk: chipstmxptclk@2310164 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310164 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "chipstmxptclk"; - }; - - chipclk12: chipclk12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <2>; - clock-mult = <1>; - clock-output-names = "chipclk12"; - }; - - chipclk13: chipclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk13"; - }; - - paclk13: paclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&papllclk>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "paclk13"; - }; - - chipclk14: chipclk14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk14"; - }; - - chipclk16: chipclk16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk16"; - }; - - chipclk112: chipclk112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk112"; - }; - - chipclk124: chipclk124 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <24>; - clock-mult = <1>; - clock-output-names = "chipclk114"; - }; - - chipclk1rstiso13: chipclk1rstiso13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso13"; - }; - - chipclk1rstiso14: chipclk1rstiso14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso14"; - }; - - chipclk1rstiso16: chipclk1rstiso16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso16"; - }; - - chipclk1rstiso112: chipclk1rstiso112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso112"; - }; - - clkmodrst0: clkmodrst0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "modrst0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkusb: clkusb@2350008 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemifspi: clkaemifspi@235000c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "aemif-spi"; - reg = <0x0235000c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkdebugsstrc: clkdebugsstrc@2350014 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "debugss-trc"; - reg = <0x02350014 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clktetbtrc: clktetbtrc@2350018 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tetb-trc"; - reg = <0x02350018 0xb00>, <0x02350004 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clkpa: clkpa@235001c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&paclk13>; - clock-output-names = "pa"; - reg = <0x0235001c 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkcpgmac: clkcpgmac@2350020 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "cpgmac"; - reg = <0x02350020 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clksa: clksa@2350024 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "sa"; - reg = <0x02350024 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkpcie: clkpcie@2350028 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x02350028 0xb00>, <0x0235000c 0x400>; - reg-names = "control", "domain"; - domain-id = <3>; - }; - - clksr: clksr@2350034 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso112>; - clock-output-names = "sr"; - reg = <0x02350034 0xb00>, <0x02350018 0x400>; - reg-names = "control", "domain"; - domain-id = <6>; - }; - - clkgem0: clkgem0@235003c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem0"; - reg = <0x0235003c 0xb00>, <0x02350020 0x400>; - reg-names = "control", "domain"; - domain-id = <8>; - }; - - clkddr30: clkddr30@235005c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "ddr3-0"; - reg = <0x0235005c 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clkwdtimer0: clkwdtimer0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer1: clkwdtimer1@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer2: clkwdtimer2@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer3: clkwdtimer3@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clktimer15: clktimer15@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer15"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart0: clkuart0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart1: clkuart1@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemif: clkaemif@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "aemif"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkusim: clkusim@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "usim"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clki2c: clki2c@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "i2c"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkspi: clkspi@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "spi"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkgpio: clkgpio@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "gpio"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkkeymgr: clkkeymgr@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "keymgr"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - /* - * Below are set of fixed, input clocks definitions, - * for which real frequencies have to be defined in board files. - * Those clocks can be used as reference clocks for some HW modules - * (as cpts, for example) by configuring corresponding clock muxes. - */ - timi0: timi0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "timi0"; - }; - - timi1: timi1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "timi1"; - }; - - tsrefclk: tsrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "tsrefclk"; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi deleted file mode 100644 index cf30e007fea3..000000000000 --- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison SoC specific device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkusb1: clkusb1@2350004 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb1"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkhyperlink0: clkhyperlink0@2350030 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkpcie1: clkpcie1@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie1"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkxge: clkxge@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - /* - * Below are set of fixed, input clocks definitions, - * for which real frequencies have to be defined in board files. - * Those clocks can be used as reference clocks for some HW modules - * (as cpts, for example) by configuring corresponding clock muxes. - */ - tsipclka: tsipclka { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "tsipclka"; - }; - - tsipclkb: tsipclkb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "tsipclkb"; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts deleted file mode 100644 index 6978d6a362f3..000000000000 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison EVM device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2e.dtsi" - -/ { - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison EVM"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; -}; - -&soc0 { - - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-pass"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1_phy { - status = "okay"; -}; - -&keystone_usb1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; -}; - -&i2c0 { - eeprom@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi deleted file mode 100644 index bff73a0ed10b..000000000000 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Edison Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x24186000 0x100>, - <0x24187000 0x2a0>, - <0x24188000 0xb60>, - <0x24186100 0x80>, - <0x24189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@24000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x24000000 0x1000000>; - - clocks = <&clkpa>, <&clkcpgmac>; - clock-names = "pa_clk", "ethss_clk"; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-9"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - cpts { - clocks = <&cpts_refclk_mux>; - clock-names = "cpts"; - - cpts_refclk_mux: cpts-refclk-mux { - #clock-cells = <0>; - clocks = <&chipclk12>, <&chipclk13>, - <&timi0>, <&timi1>, - <&tsipclka>, <&tsrefclk>, - <&tsipclkb>; - ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x4>, <0x8>, <0xc>; - assigned-clocks = <&cpts_refclk_mux>; - assigned-clock-parents = <&chipclk12>; - }; - }; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - port-4 { - slave-port = <4>; - link-interface = <2>; - }; - port-5 { - slave-port = <5>; - link-interface = <2>; - }; - port-6 { - slave-port = <6>; - link-interface = <2>; - }; - port-7 { - slave-port = <7>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 00]; - netcp-gbe = <&gbe1>; - }; - }; -}; - -sa_subsys: subsys@24080000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x24080000 0x40000>; - - sa_config: subsys@0 { - compatible = "syscon"; - reg = <0x0 0x100>; - }; - - rng@24000 { - compatible = "ti,keystone-rng"; - reg = <0x24000 0x1000>; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi deleted file mode 100644 index 65c32946c522..000000000000 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison soc device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include - -/ { - compatible = "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - aliases { - rproc0 = &dsp0; - }; -}; - -&soc0 { - /include/ "keystone-k2e-clocks.dtsi" - - usb: usb@2680000 { - interrupts = ; - usb@2690000 { - interrupts = ; - }; - }; - - usb1_phy: usb_phy@2620750 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620750 24>; - status = "disabled"; - }; - - keystone_usb1: usb@25000000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x25000000 0x10000>; - clocks = <&clkusb1>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb1: usb@25010000 { - compatible = "snps,dwc3"; - reg = <0x25010000 0x70000>; - interrupts = ; - usb-phy = <&usb1_phy>, <&usb1_phy>; - }; - }; - - msm_ram: sram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x200000>; - ranges = <0x0 0x0c000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - bm-sram@1f0000 { - reg = <0x001f0000 0x8000>; - }; - }; - - psc: power-sleep-controller@2350000 { - pscrst: reset-controller { - compatible = "ti,k2e-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - >; - }; - }; - - devctrl: device-state-control@2620000 { - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2e-dsp"; - reg = <0x10800000 0x00080000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x844>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; - clocks = <&clkpcie1>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x60000000 0x60000000 - 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - bus-range = <0x00 0xff>; - - /* error interrupt */ - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ - <0 0 0 2 &pcie_intc1 1>, /* INT B */ - <0 0 0 3 &pcie_intc1 2>, /* INT C */ - <0 0 0 4 &pcie_intc1 3>; /* INT D */ - - pcie_msi_intc1: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc1: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x24200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2e-netcp.dtsi" -}; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts deleted file mode 100644 index 7bfc80f1af26..000000000000 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G EVM - * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" - -/ { - compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; - model = "Texas Instruments K2G General Purpose EVM"; - - memory@800000000 { - device_type = "memory"; - reg = <0x00000008 0x00000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; - - vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { - compatible = "regulator-fixed"; - regulator-name = "mmc0_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { - compatible = "regulator-fixed"; - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 { - compatible = "regulator-fixed"; - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - hdmi: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&sii9022_out>; - }; - }; - }; - - aud_mclk: aud_mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - sound0: sound@0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "K2G-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - bitclock-master = <&sound0_0_master>; - frame-master = <&sound0_0_master>; - sound0_0_master: cpu { - sound-dai = <&mcasp2>; - clocks = <&k2g_clks 0x6 1>; - system-clock-direction-out; - }; - - codec { - sound-dai = <&tlv320aic3106>; - clocks = <&aud_mclk>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - bitclock-master = <&sound0_1_master>; - frame-master = <&sound0_1_master>; - sound0_1_master: cpu { - sound-dai = <&mcasp2>; - clocks = <&k2g_clks 0x6 1>; - system-clock-direction-out; - }; - - codec { - sound-dai = <&sii9022>; - clocks = <&aud_mclk>; - }; - }; - }; -}; - -&k2g_pinctrl { - uart0_pins: uart0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - mmc0_pins: mmc0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ - K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ - K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ - K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ - K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ - K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ - K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ - K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ - K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ - K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ - K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - ecap0_pins: ecap0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ - >; - }; - - spi1_pins: spi1-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ - K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ - K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ - K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ - >; - }; - - qspi_pins: qspi-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ - K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ - K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ - K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ - K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ - K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ - K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ - K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ - >; - }; - - dcan0_pins: dcan0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ - K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ - >; - }; - - dcan1_pins: dcan1-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ - K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ - >; - }; - - emac_pins: emac-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ - K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ - K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ - K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ - K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ - K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ - K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ - K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ - K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ - K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ - >; - }; - - mdio_pins: mdio-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ - K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ - >; - }; - - vout_pins: vout-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ - K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ - K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ - K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ - K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ - K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ - K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ - K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ - K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ - K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ - K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ - K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ - K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ - K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ - K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ - K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ - K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ - K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ - K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ - K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ - K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ - K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ - K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ - K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ - K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ - K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ - K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ - K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ - K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ - >; - }; - - mcasp2_pins: mcasp2-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ - K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ - K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */ - K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <&vcc3v3_dcin_reg>; - vqmmc-supply = <&vcc3v3_dcin_reg>; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ - vqmmc-supply = <&vcc1v8_ldo1_reg>; - ti,non-removable; - status = "okay"; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; - status = "okay"; -}; - -&keystone_usb1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <5000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x100000 0xf00000>; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - cdns,rclk-en; - - flash0: flash@0 { - compatible = "s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <96000000>; - #address-cells = <1>; - #size-cells = <1>; - cdns,read-delay = <5>; - cdns,tshsl-ns = <500>; - cdns,tsd2d-ns = <500>; - cdns,tchsh-ns = <119>; - cdns,tslch-ns = <119>; - - partition@0 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "QSPI.u-boot-env"; - reg = <0x00100000 0x00040000>; - }; - partition@2 { - label = "QSPI.skern"; - reg = <0x00140000 0x0040000>; - }; - partition@3 { - label = "QSPI.pmmc-firmware"; - reg = <0x00180000 0x0040000>; - }; - partition@4 { - label = "QSPI.kernel"; - reg = <0x001c0000 0x0800000>; - }; - partition@5 { - label = "QSPI.file-system"; - reg = <0x009c0000 0x3640000>; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&dcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; - status = "okay"; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -&qmss { - status = "okay"; -}; - -&knav_dmas { - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gbe0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -&netcp { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - clock-frequency = <400000>; - - sii9022: sii9022@3b { - #sound-dai-cells = <0>; - compatible = "sil,sii9022"; - reg = <0x3b>; - - sil,i2s-data-lanes = < 0 >; - clocks = <&aud_mclk>; - clock-names = "mclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sii9022_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - sii9022_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vcc3v3_dcin_reg>; - IOVDD-supply = <&vcc3v3_dcin_reg>; - DRVDD-supply = <&vcc3v3_dcin_reg>; - DVDD-supply = <&vcc1v8_ldo2_reg>; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&vout_pins>; - status = "okay"; - - port { - dpi_out: endpoint { - remote-endpoint = <&sii9022_in>; - data-lines = <24>; - }; - }; -}; - -&mcasp2 { - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mcasp2_pins>; - - assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>; - assigned-clock-parents = <0>, <&k2g_clks 0x6 2>; - assigned-clock-rates = <22579200>, <0>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 6 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 0 0 // AXR2: TX, AXR3: rx - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts deleted file mode 100644 index 6ceb0d5c6388..000000000000 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G Industrial Communication Engine EVM - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" -#include - -/ { - compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; - model = "Texas Instruments K2G Industrial Communication EVM"; - - memory@800000000 { - device_type = "memory"; - reg = <0x00000008 0x00000000 0x00000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain_fixed"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - v5_0: fixedregulator-v5_0 { - /* TPS54531 */ - compatible = "regulator-fixed"; - regulator-name = "v5_0_fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain>; - regulator-always-on; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - /* TLV62084 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vdd_1v8: fixedregulator-vdd_1v8 { - /* TLV62084 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vdds_ddr: fixedregulator-vdds_ddr { - /* TLV62080 */ - compatible = "regulator-fixed"; - regulator-name = "vdds_ddr_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vref_ddr: fixedregulator-vref_ddr { - /* LP2996A */ - compatible = "regulator-fixed"; - regulator-name = "vref_ddr_fixed"; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <675000>; - vin-supply = <&vdd_3v3>; - regulator-always-on; - }; - - vtt_ddr: fixedregulator-vtt_ddr { - /* LP2996A */ - compatible = "regulator-fixed"; - regulator-name = "vtt_ddr_fixed"; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <675000>; - vin-supply = <&vdd_3v3>; - regulator-always-on; - }; - - vdd_0v9: fixedregulator-vdd_0v9 { - /* TPS62180 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_0v9_fixed"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vddb: fixedregulator-vddb { - /* TPS22945 */ - compatible = "regulator-fixed"; - regulator-name = "vddb_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-decoder { - compatible = "gpio-decoder"; - gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, - <&pca9536 2 GPIO_ACTIVE_HIGH>, - <&pca9536 1 GPIO_ACTIVE_HIGH>, - <&pca9536 0 GPIO_ACTIVE_HIGH>; - linux,axis = <0>; /* ABS_X */ - decoder-max-value = <9>; - }; - - leds1 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - led0 { - label = "status0:red:cpu0"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - led1 { - label = "status0:green:usr"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "status0:yellow:usr"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "status1:red:mmc0"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led4 { - label = "status1:green:usr"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "status1:yellow:usr"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led6 { - label = "status2:red:usr"; - gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led7 { - label = "status2:green:usr"; - gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led8 { - label = "status2:yellow:usr"; - gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led9 { - label = "status3:red:usr"; - gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led10 { - label = "status3:green:usr"; - gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led11 { - label = "status3:yellow:usr"; - gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led12 { - label = "status4:green:heartbeat"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&k2g_pinctrl { - uart0_pins: uart0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - qspi_pins: qspi-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ - K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ - K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ - K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ - K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ - K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ - K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ - K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ - K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ - >; - }; - - i2c0_pins: i2c0-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - user_leds: user-leds-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ - K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ - K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */ - K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */ - K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */ - K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */ - K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */ - K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */ - K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */ - K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */ - K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */ - K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */ - K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ - >; - }; - - emac_pins: emac-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ - K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ - K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ - K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ - K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ - K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ - K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ - K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ - K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ - K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ - >; - }; - - mdio_pins: mdio-pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ - K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - cdns,rclk-en; - status = "okay"; - - flash0: flash@0 { - compatible = "s25fl256s1", "jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <96000000>; - #address-cells = <1>; - #size-cells = <1>; - cdns,read-delay = <5>; - cdns,tshsl-ns = <500>; - cdns,tsd2d-ns = <500>; - cdns,tchsh-ns = <119>; - cdns,tslch-ns = <119>; - - partition@0 { - label = "QSPI.u-boot"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "QSPI.u-boot-env"; - reg = <0x00100000 0x00040000>; - }; - partition@2 { - label = "QSPI.skern"; - reg = <0x00140000 0x0040000>; - }; - partition@3 { - label = "QSPI.pmmc-firmware"; - reg = <0x00180000 0x0040000>; - }; - partition@4 { - label = "QSPI.kernel"; - reg = <0x001c0000 0x0800000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x009c0000 0x0040000>; - }; - partition@6 { - label = "QSPI.file-system"; - reg = <0x00a00000 0x1600000>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vdd_3v3>; - cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - clock-frequency = <400000>; - - pca9536: gpio@41 { - compatible = "ti,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_3v3>; - }; -}; - -&qmss { - status = "okay"; -}; - -&knav_dmas { - status = "okay"; -}; - -&netcp { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gbe0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi deleted file mode 100644 index f6306933ff42..000000000000 --- a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G Netcp driver - * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@4020000 { - compatible = "ti,66ak2g-navss-qm"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k2g_pds 0x0018>; - clocks = <&k2g_clks 0x0018 0>; - clock-names = "nss_vclk"; - ranges; - queue-range = <0 0x80>; - linkram0 = <0x4020000 0x7ff>; - status = "disabled"; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x80>; - reg = <0x4100000 0x800>, - <0x4040000 0x100>, - <0x4080000 0x800>, - <0x40c0000 0x800>; - reg-names = "peek", "config", - "region", "push"; - }; - - }; - queue-pools { - qpend { - qpend-0 { - qrange = <77 8>; - interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 - 0 311 0xf04 0 312 0xf04 0 313 0xf04 - 0 314 0xf04 0 315 0xf04>; - qalloc-by-id; - }; - }; - general-purpose { - gp-0 { - qrange = <112 8>; - }; - netcp-tx { - qrange = <5 8>; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <1023 128>; /* num_desc desc_size */ - link-index = <0x400>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - power-domains = <&k2g_pds 0x0018>; - clocks = <&k2g_clks 0x0018 0>; - clock-names = "nss_vclk"; - ranges; - ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x4010000 0x100>, - <0x4011000 0x2a0>, /* 21 Tx channels */ - <0x4012000 0x400>, /* 32 Rx channels */ - <0x4010100 0x80>, - <0x4013000 0x400>; /* 32 Rx flows */ - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; - -}; - -netcp: netcp@4000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - power-domains = <&k2g_pds 0x0018>; - clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>; - clock-names = "ethss_clk", "cpts"; - - /* NetCP address range */ - ranges = <0 0x4000000 0x1000000>; - - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; - ti,navigator-dma-names = "netrx0", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe: gbe@200000 { - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-2"; - reg = <0x200000 0x20>, <0x220000 0x20000>; - enable-ale; - tx-queue = <5>; - tx-channel = "nettx"; - cpts-rftclk-sel = <0>; - cpts-ext-ts-inputs = <8>; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <5>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <512 12>; - tx-pool = <511 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <77>; - tx-completion-queue = <78>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi deleted file mode 100644 index 102d59694d90..000000000000 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ /dev/null @@ -1,644 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G SOC - * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include - -/ { - compatible = "ti,k2g","ti,keystone"; - model = "Texas Instruments K2G SoC"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - chosen { }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - rproc0 = &dsp0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2561000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x2000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usb0_phy: usb-phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - status = "disabled"; - }; - - usb1_phy: usb-phy@1 { - compatible = "usb-nop-xceiv"; - reg = <1>; - status = "disabled"; - }; - }; - - soc0: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - compatible = "ti,keystone","simple-bus"; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - - msm_ram: sram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x100000>; - ranges = <0x0 0x0c000000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - - bm-sram@f7000 { - reg = <0x000f7000 0x8000>; - }; - }; - - k2g_pinctrl: pinmux@2621000 { - compatible = "pinctrl-single"; - reg = <0x02621000 0x410>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x001b0007>; - }; - - devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; - reg = <0x02620000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x02620000 0x1000>; - - kirq0: keystone_irq@2a0 { - compatible = "ti,keystone-irq"; - reg = <0x2a0 0x10>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - }; - - uart0: serial@2530c00 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - interrupts = ; - clocks = <&k2g_clks 0x2c 0>; - power-domains = <&k2g_pds 0x2c>; - status = "disabled"; - }; - - uart1: serial@2531000 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - interrupts = ; - clocks = <&k2g_clks 0x2d 0>; - power-domains = <&k2g_pds 0x2d>; - status = "disabled"; - }; - - uart2: serial@2531400 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531400 0x100>; - interrupts = ; - clocks = <&k2g_clks 0x2e 0>; - power-domains = <&k2g_pds 0x2e>; - status = "disabled"; - }; - - dcan0: can@260b200 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260b200 0x200>; - interrupts = ; - status = "disabled"; - power-domains = <&k2g_pds 0x0008>; - clocks = <&k2g_clks 0x0008 1>; - }; - - dcan1: can@260b400 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260b400 0x200>; - interrupts = ; - status = "disabled"; - power-domains = <&k2g_pds 0x0009>; - clocks = <&k2g_clks 0x0009 1>; - }; - - i2c0: i2c@2530000 { - compatible = "ti,keystone-i2c"; - reg = <0x02530000 0x400>; - clocks = <&k2g_clks 0x003a 0>; - power-domains = <&k2g_pds 0x003a>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@2530400 { - compatible = "ti,keystone-i2c"; - reg = <0x02530400 0x400>; - clocks = <&k2g_clks 0x003b 0>; - power-domains = <&k2g_pds 0x003b>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@2530800 { - compatible = "ti,keystone-i2c"; - reg = <0x02530800 0x400>; - clocks = <&k2g_clks 0x003c 0>; - power-domains = <&k2g_pds 0x003c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2g-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - power-domains = <&k2g_pds 0x0046>; - ti,syscon-dev = <&devctrl 0x844>; - resets = <&k2g_reset 0x0046 0x1>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - msgmgr: mailbox@2a00000 { - compatible = "ti,k2g-message-manager"; - #mbox-cells = <2>; - reg-names = "queue_proxy_region", - "queue_state_debug_region"; - reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; - interrupt-names = "rx_005", - "rx_057"; - interrupts = , - ; - }; - - pmmc: system-controller@2921c00 { - compatible = "ti,k2g-sci"; - /* - * In case of rare platforms that does not use k2g as - * system master, use /delete-property/ - */ - ti,system-reboot-controller; - mbox-names = "rx", "tx"; - mboxes = <&msgmgr 5 2>, - <&msgmgr 0 0>; - reg-names = "debug_messages"; - reg = <0x02921c00 0x400>; - - k2g_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <1>; - }; - - k2g_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k2g_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - gpio0: gpio@2603000 { - compatible = "ti,k2g-gpio", "ti,keystone-gpio"; - reg = <0x02603000 0x100>; - gpio-controller; - #gpio-cells = <2>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k2g_clks 0x001b 0x0>; - clock-names = "gpio"; - }; - - gpio1: gpio@260a000 { - compatible = "ti,k2g-gpio", "ti,keystone-gpio"; - reg = <0x0260a000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <68>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k2g_clks 0x001c 0x0>; - clock-names = "gpio"; - }; - - dss: dss@02540000 { - compatible = "ti,k2g-dss"; - reg = <0x02540000 0x400>, - <0x02550000 0x1000>, - <0x02557000 0x1000>, - <0x0255a800 0x100>, - <0x0255ac00 0x100>; - reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; - clocks = <&k2g_clks 0x2 0>, - <&k2g_clks 0x2 1>; - clock-names = "fck", "vp1"; - interrupts = ; - - power-domains = <&k2g_pds 0x2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - max-memory-bandwidth = <230000000>; - }; - - edma0: edma@2700000 { - compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02700000 0x8000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; - - ti,edma-memcpy-channels = <32 33 34 35>; - - power-domains = <&k2g_pds 0x3f>; - }; - - edma0_tptc0: tptc@2760000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02760000 0x400>; - power-domains = <&k2g_pds 0x3f>; - }; - - edma0_tptc1: tptc@2768000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02768000 0x400>; - power-domains = <&k2g_pds 0x3f>; - }; - - edma1: edma@2728000 { - compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02728000 0x8000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <12 13 14 15>; - * for example. - */ - - power-domains = <&k2g_pds 0x4f>; - }; - - edma1_tptc0: tptc@27b0000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b0000 0x400>; - power-domains = <&k2g_pds 0x4f>; - }; - - edma1_tptc1: tptc@27b8000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b8000 0x400>; - power-domains = <&k2g_pds 0x4f>; - }; - - mmc0: mmc@23000000 { - compatible = "ti,k2g-sdhci"; - reg = <0x23000000 0x400>; - interrupts = ; - bus-width = <4>; - no-1-8-v; - max-frequency = <96000000>; - power-domains = <&k2g_pds 0xb>; - clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; - clock-names = "fck", "mmchsdb_fck"; - status = "disabled"; - }; - - mmc1: mmc@23100000 { - compatible = "ti,k2g-sdhci"; - reg = <0x23100000 0x400>; - interrupts = ; - bus-width = <8>; - no-1-8-v; - non-removable; - max-frequency = <96000000>; - power-domains = <&k2g_pds 0xc>; - clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; - clock-names = "fck", "mmchsdb_fck"; - }; - - qspi: spi@2940000 { - compatible = "ti,k2g-qspi", "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02940000 0x1000>, - <0x24000000 0x4000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x24000000>; - clocks = <&k2g_clks 0x43 0x0>; - power-domains = <&k2g_pds 0x43>; - status = "disabled"; - }; - - mcasp0: mcasp@2340000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x02340000 0x2000>, - <0x21804000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma0 24 1>, <&edma0 25 1>; - dma-names = "tx", "rx"; - power-domains = <&k2g_pds 0x4>; - clocks = <&k2g_clks 0x4 0>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp1: mcasp@2342000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x02342000 0x2000>, - <0x21804400 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma1 48 1>, <&edma1 49 1>; - dma-names = "tx", "rx"; - power-domains = <&k2g_pds 0x5>; - clocks = <&k2g_clks 0x5 0>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp2: mcasp@2344000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x02344000 0x2000>, - <0x21804800 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma1 50 1>, <&edma1 51 1>; - dma-names = "tx", "rx"; - power-domains = <&k2g_pds 0x6>; - clocks = <&k2g_clks 0x6 0>; - clock-names = "fck"; - status = "disabled"; - }; - - keystone_usb0: keystone-dwc3@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - power-domains = <&k2g_pds 0x0016>; - - usb0: usb@2690000 { - compatible = "snps,dwc3"; - reg = <0x2690000 0x10000>; - interrupts = ; - maximum-speed = "high-speed"; - dr_mode = "otg"; - usb-phy = <&usb0_phy>; - status = "disabled"; - }; - }; - - keystone_usb1: keystone-dwc3@2580000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2580000 0x10000>; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - power-domains = <&k2g_pds 0x0017>; - - usb1: usb@2590000 { - compatible = "snps,dwc3"; - reg = <0x2590000 0x10000>; - interrupts = ; - maximum-speed = "high-speed"; - dr_mode = "otg"; - usb-phy = <&usb1_phy>; - status = "disabled"; - }; - }; - - ecap0: pwm@21d1800 { - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x021d1800 0x60>; - power-domains = <&k2g_pds 0x38>; - clocks = <&k2g_clks 0x38 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap1: pwm@21d1c00 { - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x021d1c00 0x60>; - power-domains = <&k2g_pds 0x39>; - clocks = <&k2g_clks 0x39 0x0>; - clock-names = "fck"; - status = "disabled"; - }; - - spi0: spi@21805400 { - compatible = "ti,keystone-spi"; - reg = <0x21805400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0010>; - clocks = <&k2g_clks 0x0010 0>; - }; - - spi1: spi@21805800 { - compatible = "ti,keystone-spi"; - reg = <0x21805800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0011>; - clocks = <&k2g_clks 0x0011 0>; - }; - - spi2: spi@21805c00 { - compatible = "ti,keystone-spi"; - reg = <0x21805c00 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0012>; - clocks = <&k2g_clks 0x0012 0>; - }; - - spi3: spi@21806000 { - compatible = "ti,keystone-spi"; - reg = <0x21806000 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0013>; - clocks = <&k2g_clks 0x0013 0>; - }; - - wdt: wdt@02250000 { - compatible = "ti,keystone-wdt", "ti,davinci-wdt"; - reg = <0x02250000 0x80>; - power-domains = <&k2g_pds 0x22>; - clocks = <&k2g_clks 0x22 0>; - }; - - emif: emif@21010000 { - compatible = "ti,emif-keystone"; - reg = <0x21010000 0x200>; - interrupts = ; - }; - - mdio: mdio@4200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - reg = <0x04200f00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k2g_clks 0x0018 3>; - clock-names = "fck"; - power-domains = <&k2g_pds 0x0018>; - status = "disabled"; - bus_freq = <2500000>; - }; - #include "keystone-k2g-netcp.dtsi" - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi deleted file mode 100644 index 4ba6912176ef..000000000000 --- a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking SoC clock nodes - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - clktsip: clktsip@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "tsip"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clksrio: clksrio@235002c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0@2350030 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkgem1: clkgem1@2350040 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2@2350044 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3@2350048 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4@235004c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5@2350050 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6@2350054 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7@2350058 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr31: clkddr31@2350060 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac@2350064 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clkrac01@2350068 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clkrac23@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0@2350070 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1@2350074 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2@2350078 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3@235007c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4@2350080 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5@2350084 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif@2350088 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0@235008c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1@2350090 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2@2350094 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3@2350098 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0@235009c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1@23500a0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2@23500a4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3@23500a8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4@23500ac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5@23500b0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6@23500b4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7@23500b8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp@23500bc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb@23500c0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1@23500c4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts deleted file mode 100644 index 206df8a8d9dd..000000000000 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking EVM device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2hk.dtsi" - -/ { - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - led-debug-1-1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - led-debug-1-2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - led-debug-2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - led-debug-3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; -}; - -&soc0 { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-pass"; - }; - - refclkarm: refclkarm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "refclk-arm"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - - refclkddr3b: refclkddr3b { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3b"; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&i2c0 { - eeprom@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&spi0 { - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp1 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp2 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp3 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp4 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp5 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp6 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp7 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi deleted file mode 100644 index 8a421c65f920..000000000000 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Hawking Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - netcpx-tx { - qrange = <8752 8>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; - - clocks = <&clkpa>, <&clkcpgmac>; - clock-names = "pa_clk", "ethss_clk"; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - ranges; - #address-cells = <1>; - #size-cells = <1>; - gbe@90000 { /* ETHSS */ - #address-cells = <1>; - #size-cells = <1>; - label = "netcp-gbe"; - compatible = "ti,netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = "nettx"; - - cpts { - clocks = <&cpts_refclk_mux>; - clock-names = "cpts"; - - cpts_refclk_mux: cpts-refclk-mux { - #clock-cells = <0>; - clocks = <&chipclk12>, <&chipclk13>, - <&timi0>, <&timi1>, - <&tsrefclk>; - ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x8>; - assigned-clocks = <&cpts_refclk_mux>; - assigned-clock-parents = <&chipclk12>; - }; - }; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; - -sa_subsys: subsys@20c0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x20c0000 0x40000>; - - sa_config: subsys@0 { - compatible = "syscon"; - reg = <0x0 0x100>; - }; - - rng@24000 { - compatible = "ti,keystone-rng"; - reg = <0x24000 0x1000>; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi deleted file mode 100644 index da6d3934c2e8..000000000000 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking soc specific device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include - -/ { - compatible = "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - aliases { - rproc0 = &dsp0; - rproc1 = &dsp1; - rproc2 = &dsp2; - rproc3 = &dsp3; - rproc4 = &dsp4; - rproc5 = &dsp5; - rproc6 = &dsp6; - rproc7 = &dsp7; - }; -}; - -&soc0 { - /include/ "keystone-k2hk-clocks.dtsi" - - msm_ram: sram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x600000>; - ranges = <0x0 0x0c000000 0x600000>; - #address-cells = <1>; - #size-cells = <1>; - - bm-sram@5f0000 { - reg = <0x5f0000 0x8000>; - }; - }; - - psc: power-sleep-controller@2350000 { - pscrst: reset-controller { - compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ - 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ - 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ - 0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */ - 0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */ - 0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */ - 0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */ - >; - }; - }; - - devctrl: device-state-control@2620000 { - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@244 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x244 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@248 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x248 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@24c { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x24c 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - dspgpio4: keystone_dsp_gpio@250 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x250 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; - - dspgpio5: keystone_dsp_gpio@254 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x254 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; - - dspgpio6: keystone_dsp_gpio@258 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x258 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; - - dspgpio7: keystone_dsp_gpio@25c { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x25c 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; - }; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x40>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - dsp1: dsp@11800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x11800000 0x00100000>, - <0x11e00000 0x00008000>, - <0x11f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem1>; - ti,syscon-dev = <&devctrl 0x44>; - resets = <&pscrst 1>; - interrupt-parent = <&kirq0>; - interrupts = <1 9>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio1 27 0>; - status = "disabled"; - }; - - dsp2: dsp@12800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x12800000 0x00100000>, - <0x12e00000 0x00008000>, - <0x12f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem2>; - ti,syscon-dev = <&devctrl 0x48>; - resets = <&pscrst 2>; - interrupt-parent = <&kirq0>; - interrupts = <2 10>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio2 27 0>; - status = "disabled"; - }; - - dsp3: dsp@13800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x13800000 0x00100000>, - <0x13e00000 0x00008000>, - <0x13f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem3>; - ti,syscon-dev = <&devctrl 0x4c>; - resets = <&pscrst 3>; - interrupt-parent = <&kirq0>; - interrupts = <3 11>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio3 27 0>; - status = "disabled"; - }; - - dsp4: dsp@14800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x14800000 0x00100000>, - <0x14e00000 0x00008000>, - <0x14f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem4>; - ti,syscon-dev = <&devctrl 0x50>; - resets = <&pscrst 4>; - interrupt-parent = <&kirq0>; - interrupts = <4 12>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio4 27 0>; - status = "disabled"; - }; - - dsp5: dsp@15800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x15800000 0x00100000>, - <0x15e00000 0x00008000>, - <0x15f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem5>; - ti,syscon-dev = <&devctrl 0x54>; - resets = <&pscrst 5>; - interrupt-parent = <&kirq0>; - interrupts = <5 13>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio5 27 0>; - status = "disabled"; - }; - - dsp6: dsp@16800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x16800000 0x00100000>, - <0x16e00000 0x00008000>, - <0x16f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem6>; - ti,syscon-dev = <&devctrl 0x58>; - resets = <&pscrst 6>; - interrupt-parent = <&kirq0>; - interrupts = <6 14>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio6 27 0>; - status = "disabled"; - }; - - dsp7: dsp@17800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x17800000 0x00100000>, - <0x17e00000 0x00008000>, - <0x17f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem7>; - ti,syscon-dev = <&devctrl 0x5c>; - resets = <&pscrst 7>; - interrupt-parent = <&kirq0>; - interrupts = <7 15>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio7 27 0>; - status = "disabled"; - }; - - mdio: mdio@2090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02090300 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2hk-netcp.dtsi" -}; diff --git a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi deleted file mode 100644 index 635528064dea..000000000000 --- a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 lamarr SoC clock nodes - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkdfeiqnsys: clkdfeiqnsys@2350004 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "dfe"; - reg-names = "control", "domain"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - domain-id = <0>; - }; - - clkpcie1: clkpcie1@235002c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235002c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkgem1: clkgem1@2350040 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2@2350044 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3@2350048 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clktac: clktac@2350064 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac: clkrac@2350068 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkdfepd0: clkdfepd0@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd0"; - reg = <0x0235006c 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0@2350070 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkosr: clkosr@2350088 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "osr"; - reg = <0x02350088 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0@235008c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1@2350094 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350094 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0@235009c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1@23500a0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2@23500a4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3@23500a8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkbcp: clkbcp@23500bc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdfepd1: clkdfepd1@23500c0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd1"; - reg = <0x023500c0 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkfftc1: clkfftc1@23500c4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkiqnail: clkiqnail@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "iqn-ail"; - reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkuart2: clkuart2@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart3: clkuart3@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts deleted file mode 100644 index be619e39a16f..000000000000 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Lamarr EVM device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2l.dtsi" - -/ { - compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr EVM"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; -}; - -&soc0 { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&i2c0 { - eeprom@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7fe80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp1 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp2 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp3 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi deleted file mode 100644 index 5ec6680a533d..000000000000 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Lamarr Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; - -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x26186000 0x100>, - <0x26187000 0x2a0>, - <0x26188000 0xb60>, - <0x26186100 0x80>, - <0x26189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@26000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x26000000 0x1000000>; - - clocks = <&clkpa>, <&clkcpgmac>; - clock-names = "pa_clk", "ethss_clk"; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-5"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - cpts { - clocks = <&cpts_refclk_mux>; - clock-names = "cpts"; - - cpts_refclk_mux: cpts-refclk-mux { - #clock-cells = <0>; - clocks = <&chipclk12>, <&chipclk13>, - <&timi0>, <&timi1>, - <&tsrefclk>; - ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x8>; - assigned-clocks = <&cpts_refclk_mux>; - assigned-clock-parents = <&chipclk12>; - }; - }; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 7f]; - netcp-gbe = <&gbe1>; - }; - }; -}; - -sa_subsys: subsys@26080000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x26080000 0x40000>; - - sa_config: subsys@0 { - compatible = "syscon"; - reg = <0x0 0x100>; - }; - - rng@24000 { - compatible = "ti,keystone-rng"; - reg = <0x24000 0x1000>; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - }; -}; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi deleted file mode 100644 index 8949578e62e8..000000000000 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Lamarr SoC specific device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include - -/ { - compatible = "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - }; - - aliases { - rproc0 = &dsp0; - rproc1 = &dsp1; - rproc2 = &dsp2; - rproc3 = &dsp3; - }; -}; - -&soc0 { - /include/ "keystone-k2l-clocks.dtsi" - - uart2: serial@2348400 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348400 0x100>; - clocks = <&clkuart2>; - interrupts = ; - }; - - uart3: serial@2348800 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348800 0x100>; - clocks = <&clkuart3>; - interrupts = ; - }; - - gpio1: gpio@2348000 { - compatible = "ti,keystone-gpio"; - reg = <0x02348000 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; - }; - - k2l_pmx: pinmux@2620690 { - compatible = "pinctrl-single"; - reg = <0x02620690 0xc>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - status = "disabled"; - - uart3_emifa_pins: uart3-emifa-pins { - pinctrl-single,bits = < - /* UART3_EMIFA_SEL */ - 0x0 0x0 0xc0 - >; - }; - - uart2_emifa_pins: uart2-emifa-pins { - pinctrl-single,bits = < - /* UART2_EMIFA_SEL */ - 0x0 0x0 0x30 - >; - }; - - uart01_spi2_pins: uart01-spi2-pins { - pinctrl-single,bits = < - /* UART01_SPI2_SEL */ - 0x0 0x0 0x4 - >; - }; - - dfesync_rp1_pins: dfesync-rp1-pins{ - pinctrl-single,bits = < - /* DFESYNC_RP1_SEL */ - 0x0 0x0 0x2 - >; - }; - - avsif_pins: avsif-pins { - pinctrl-single,bits = < - /* AVSIF_SEL */ - 0x0 0x0 0x1 - >; - }; - - gpio_emu_pins: gpio-emu-pins { - pinctrl-single,bits = < - /* - * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 - * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 - * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 - * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 - * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 - * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 - * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 - * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 - * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 - * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 - * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 - * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 - * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 - * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 - * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 - */ - 0x4 0x0000 0xfffe0000 - >; - }; - - gpio_timio_pins: gpio-timio-pins { - pinctrl-single,bits = < - /* - * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 - * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 - * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 - * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 - * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 - * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 - * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 - * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 - * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 - * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 - * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 - * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 - */ - 0x4 0x0 0xfff0 - >; - }; - - gpio_spi2cs_pins: gpio-spi2cs-pins { - pinctrl-single,bits = < - /* - * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 - * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 - * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 - * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 - */ - 0x4 0x0 0xf - >; - }; - - gpio_dfeio_pins: gpio-dfeio-pins { - pinctrl-single,bits = < - /* - * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 - * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 - * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 - * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 - * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 - * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 - * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 - * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 - * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 - * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 - * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 - * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 - * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 - * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 - * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 - * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 - */ - 0x8 0x0 0xffff0000 - >; - }; - - gpio_emifa_pins: gpio-emifa-pins { - pinctrl-single,bits = < - /* - * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 - * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 - * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 - * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 - * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 - * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 - * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 - * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 - * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 - * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 - * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 - * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 - * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 - * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 - * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 - * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 - */ - 0x8 0x0 0xffff - >; - }; - }; - - msm_ram: sram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x200000>; - ranges = <0x0 0x0c000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - bm-sram@1f8000 { - reg = <0x001f8000 0x8000>; - }; - }; - - psc: power-sleep-controller@2350000 { - pscrst: reset-controller { - compatible = "ti,k2l-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ - 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ - 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ - >; - }; - }; - - osr: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x70000000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clkosr>; - }; - - devctrl: device-state-control@2620000 { - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@244 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x244 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@248 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x248 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@24c { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x24c 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2l-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x844>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - dsp1: dsp@11800000 { - compatible = "ti,k2l-dsp"; - reg = <0x11800000 0x00100000>, - <0x11e00000 0x00008000>, - <0x11f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem1>; - ti,syscon-dev = <&devctrl 0x848>; - resets = <&pscrst 1>; - interrupt-parent = <&kirq0>; - interrupts = <1 9>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio1 27 0>; - status = "disabled"; - }; - - dsp2: dsp@12800000 { - compatible = "ti,k2l-dsp"; - reg = <0x12800000 0x00100000>, - <0x12e00000 0x00008000>, - <0x12f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem2>; - ti,syscon-dev = <&devctrl 0x84c>; - resets = <&pscrst 2>; - interrupt-parent = <&kirq0>; - interrupts = <2 10>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio2 27 0>; - status = "disabled"; - }; - - dsp3: dsp@13800000 { - compatible = "ti,k2l-dsp"; - reg = <0x13800000 0x00100000>, - <0x13e00000 0x00008000>, - <0x13f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem3>; - ti,syscon-dev = <&devctrl 0x850>; - resets = <&pscrst 3>; - interrupt-parent = <&kirq0>; - interrupts = <3 11>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio3 27 0>; - status = "disabled"; - }; - - mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x26200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2l-netcp.dtsi" -}; - -&spi0 { - ti,davinci-spi-num-cs = <5>; -}; - -&spi1 { - ti,davinci-spi-num-cs = <3>; -}; - -&spi2 { - ti,davinci-spi-num-cs = <5>; - /* Pin muxed. Enabled and configured by Bootloader */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi deleted file mode 100644 index 1fd04bb37a15..000000000000 --- a/arch/arm/boot/dts/keystone.dtsi +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include - -/ { - compatible = "ti,keystone"; - model = "Texas Instruments Keystone 2 SoC"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - chosen { }; - - memory: memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; - }; - - gic: interrupt-controller@2561000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x2000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - soc0: soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - - pllctrl: pll-controller@2310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; - }; - - psc: power-sleep-controller@2350000 { - compatible = "syscon", "simple-mfd"; - reg = <0x02350000 0x1000>; - }; - - devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; - reg = <0x02620000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x02620000 0x1000>; - - kirq0: keystone_irq@2a0 { - compatible = "ti,keystone-irq"; - reg = <0x2a0 0x4>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - rstctrl: reset-controller@328 { - compatible = "ti,keystone-reset"; - reg = <0x328 0x10>; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; - }; - }; - - /include/ "keystone-clocks.dtsi" - - uart0: serial@2530c00 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; - interrupts = ; - }; - - uart1: serial@2531000 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - clocks = <&clkuart1>; - interrupts = ; - }; - - i2c0: i2c@2530000 { - compatible = "ti,davinci-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@2530400 { - compatible = "ti,davinci-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@2530800 { - compatible = "ti,davinci-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@21000400 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@21000600 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000600 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@21000800 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_phy: usb_phy@2620738 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620738 24>; - status = "disabled"; - }; - - keystone_usb0: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb0: usb@2690000 { - compatible = "snps,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = ; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; - - wdt: wdt@22f0080 { - compatible = "ti,keystone-wdt","ti,davinci-wdt"; - reg = <0x022f0080 0x80>; - clocks = <&clkwdtimer0>; - }; - - clock_event: timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = ; - clocks = <&clktimer15>; - }; - - gpio0: gpio@260bf00 { - compatible = "ti,keystone-gpio"; - reg = <0x0260bf00 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; - }; - - aemif: aemif@21000a00 { - compatible = "ti,keystone-aemif", "ti,davinci-aemif"; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clkaemif>; - clock-names = "aemif"; - clock-ranges; - - reg = <0x21000a00 0x00000100>; - ranges = <0 0 0x30000000 0x10000000 - 1 0 0x21000a00 0x00000100>; - }; - - pcie0: pcie@21800000 { - compatible = "ti,keystone-pcie", "snps,dw-pcie"; - clocks = <&clkpcie>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x50000000 0x50000000 - 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - bus-range = <0x00 0xff>; - - /* error interrupt */ - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ - <0 0 0 2 &pcie_intc0 1>, /* INT B */ - <0 0 0 3 &pcie_intc0 2>, /* INT C */ - <0 0 0 4 &pcie_intc0 3>; /* INT D */ - - pcie_msi_intc0: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc0: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - emif: emif@21010000 { - compatible = "ti,emif-keystone"; - reg = <0x21010000 0x200>; - interrupts = ; - interrupt-parent = <&gic>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-4i-edge-200.dts b/arch/arm/boot/dts/kirkwood-4i-edge-200.dts deleted file mode 100644 index b1749d3f60b7..000000000000 --- a/arch/arm/boot/dts/kirkwood-4i-edge-200.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Endian 4i Edge 200 Board Description - * Note: Endian UTM Mini is hardware clone of Endian Edge 200 - * Copyright 2021-2022 Pawel Dembicki - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include - -/ { - model = "Endian 4i Edge 200"; - compatible = "endian,4i-edge-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led>; - pinctrl-names = "default"; - - led-1 { - function = LED_FUNCTION_SD; - color = ; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -ð0 { - status = "okay"; -}; - -ð0port { - speed = <1000>; - duplex = <1>; -}; - -ð1 { - status = "okay"; -}; - -ð1port { - phy-handle = <ðphyb>; -}; - -&mdio { - status = "okay"; - - ethphyb: ethernet-phy@b { - reg = <0x0b>; - - marvell,reg-init = - /* link-activity, bi-color mode 4 */ - <3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */ - }; - - switch0: switch@11 { - compatible = "marvell,mv88e6085"; - reg = <0x11>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port1"; - }; - - port@1 { - reg = <1>; - label = "port2"; - }; - - port@2 { - reg = <2>; - label = "port3"; - }; - - port@3 { - reg = <3>; - label = "port4"; - }; - - port@5 { - reg = <5>; - phy-mode = "rgmii-id"; - ethernet = <ð0port>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x000a0000>; - read-only; - }; - - partition@a0000 { - label = "u-boot-env"; - reg = <0x000a0000 0x00060000>; - read-only; - }; - - partition@100000 { - label = "kernel"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "ubi"; - reg = <0x00500000 0x1fb00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&pmx_sysrst>; - pinctrl-names = "default"; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led: pmx-led { - marvell,pins = "mpp34", "mpp35", "mpp49"; - marvell,function = "gpio"; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; - -&sdio { - pinctrl-0 = <&pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio0 28 9>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi deleted file mode 100644 index 705c0d7effed..000000000000 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <9>, <44>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6192-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi deleted file mode 100644 index 8e311165fd13..000000000000 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <9>, <44>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6281-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi deleted file mode 100644 index e33723160ce7..000000000000 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <9>, <44>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <10>, <45>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 18>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; - ocp@f1000000 { - - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6282-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - - /* - * Default I2C1 pinctrl setting on mpp36/mpp37, - * overwrite marvell,pins on board level if required. - */ - pmx_twsi1: pmx-twsi1 { - marvell,pins = "mpp36", "mpp37"; - marvell,function = "twsi1"; - }; - - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - thermal: thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi deleted file mode 100644 index c3469a2fc58a..000000000000 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <9>, <44>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,98dx4122-pinctrl"; - - }; - }; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts deleted file mode 100644 index 681343c1357a..000000000000 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Excito Bubba B3 - * - * Copyright (C) 2013, Andrew Lunn - * - * - * Note: This requires a new'ish version of u-boot, which disables the - * L2 cache. If your B3 silently fails to boot, u-boot is probably too - * old. Either upgrade, or consider the following email: - * - * https://lists.debian.org/debian-arm/2012/08/msg00128.html - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Excito B3"; - compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - memory { /* 512 MB */ - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_beeper: pmx-beeper { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - - m25p16@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0xc0000>; - label = "u-boot"; - }; - - partition@c0000 { - reg = <0xc0000 0x20000>; - label = "u-boot env"; - }; - - partition@e0000 { - reg = <0xe0000 0x120000>; - label = "data"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - /* - * There is something on the bus at address 0x64. - * Not yet identified what it is, maybe the eeprom - * for the Atheros WiFi chip? - */ - }; - - - serial@12000 { - /* Internal on test pins, 3.3v TTL - * UART0_RX = Testpoint 65 - * UART0_TX = Testpoint 66 - * See the Excito Wiki for more details. - */ - status = "okay"; - }; - - sata@80000 { - /* One internal, the second as eSATA */ - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-leds { - /* - * There is one LED "port" on the front and the colours - * mix together giving some interesting combinations. - */ - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_green &pmx_led_red - &pmx_led_blue >; - pinctrl-names = "default"; - - programming_led { - label = "bubba3:green:programming"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - error_led { - label = "bubba3:red:error"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - active_led { - label = "bubba3:blue:active"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power>; - pinctrl-names = "default"; - - power-button { - /* On the back */ - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - }; - - beeper: beeper { - /* 4KHz Piezoelectric buzzer */ - compatible = "gpio-beeper"; - pinctrl-0 = <&pmx_beeper>; - pinctrl-names = "default"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@24 { - device_type = "ethernet-phy"; - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -/* Wifi model has Atheros chipset on pcie port */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts deleted file mode 100644 index 07fbfca444d5..000000000000 --- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Seagate Blackarmor NAS220 - * - * Copyright (C) 2014 Evgeni Dobrev - */ - -/dts-v1/; - -#include -#include -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Seagate Blackarmor NAS220"; - compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - button { - label = "Power"; - linux,code = ; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-power { - label = "nas220:blue:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* - * Serial port routed to connector CN5 - * - * pin 1 - TX (CPU's TX) - * pin 4 - RX (CPU's RX) - * pin 6 - GND - */ -&uart0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&pmx_button_reset &pmx_button_power>; - pinctrl-names = "default"; - - pmx_act_sata0: pmx-act-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - - pmx_act_sata1: pmx-act-sata1 { - marvell,pins = "mpp16"; - marvell,function = "sata1"; - }; - - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_button_power: pmx-button-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&i2c0 { - status = "okay"; - - adt7476: thermal@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; -}; - -&nand { - status = "okay"; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-c200-v1.dts b/arch/arm/boot/dts/kirkwood-c200-v1.dts deleted file mode 100644 index f59ff7578dfc..000000000000 --- a/arch/arm/boot/dts/kirkwood-c200-v1.dts +++ /dev/null @@ -1,310 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Ctera C200 V1 Board Description - * Copyright 2021-2022 Pawel Dembicki - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include - -/ { - model = "Ctera C200 V1"; - compatible = "ctera,c200-v1", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - - usb1 { - label = "USB1 Button"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - - usb2 { - label = "USB2 Button"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-0 { - function = LED_FUNCTION_DISK; - function-enumerator = <2>; - color = ; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - led-1 { - function = LED_FUNCTION_DISK; - function-enumerator = <1>; - color = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - led-2 { - function = LED_FUNCTION_DISK; - function-enumerator = <2>; - color = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - - led-3 { - function = LED_FUNCTION_DISK; - function-enumerator = <1>; - color = ; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - led-6 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - led-7 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-8 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - led-9 { - function = LED_FUNCTION_USB; - function-enumerator = <1>; - color = ; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - - led-10 { - function = LED_FUNCTION_USB; - function-enumerator = <1>; - color = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port2>; - }; - - led-11 { - function = LED_FUNCTION_USB; - function-enumerator = <2>; - color = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - - led-12 { - function = LED_FUNCTION_USB; - function-enumerator = <2>; - color = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port1>; - }; - }; -}; - -ð0 { - status = "okay"; -}; - -ð0port { - phy-handle = <ðphy9>; -}; - -&i2c0 { - status = "okay"; - - rtc@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - - lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; -}; - -&mdio { - status = "okay"; - - ethphy9: ethernet-phy@9 { - reg = <9>; - }; -}; - -&nand { - status = "okay"; - chip-delay = <40>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x200000>; - }; - - partition@200000 { - label = "certificate"; - reg = <0x0200000 0x100000>; - }; - - partition@300000 { - label = "preset_cfg"; - reg = <0x0300000 0x100000>; - }; - - partition@400000 { - label = "dev_params"; - reg = <0x0400000 0x100000>; - }; - - partition@500000 { - label = "active_bank"; - reg = <0x0500000 0x0100000>; - }; - - partition@600000 { - label = "magic"; - reg = <0x0600000 0x0100000>; - }; - - partition@700000 { - label = "bank1"; - reg = <0x0700000 0x2800000>; - }; - - partition@2f00000 { - label = "bank2"; - reg = <0x2f00000 0x2800000>; - }; - - /* 0x5700000-0x5a00000 undefined in vendor firmware */ - - partition@5a00000 { - label = "reserved"; - reg = <0x5a00000 0x2000000>; - }; - - partition@7a00000 { - label = "rootfs"; - reg = <0x7a00000 0x8600000>; - }; -}; - -&pinctrl { - /* Buzzer gpios are connected to two pins of buzzer. - * This buzzer require a modulated signal from gpio. - * Leave it as is due lack of proper driver. - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp12", "mpp13"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp14", "mpp15", "mpp16", "mpp17", "mpp38", - "mpp39", "mpp40", "mpp42", "mpp43", "mpp44", - "mpp45", "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp28", "mpp29", "mpp48", "mpp49"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; -}; - -&rtc { - status = "disabled"; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - #trigger-source-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - hub_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts deleted file mode 100644 index 448b0cd23b5f..000000000000 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "LaCie CloudBox"; - compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_cloudbox_sata0: pmx-cloudbox-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - pinctrl-0 = <&pmx_cloudbox_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "cloudbox:red:fail"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - blue-sata { - label = "cloudbox:blue:sata"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/kirkwood-d2net.dts deleted file mode 100644 index bd3b266dd766..000000000000 --- a/arch/arm/boot/dts/kirkwood-d2net.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for d2 Network v2 - * - * Copyright (C) 2014 Simon Guinot - * -*/ - -/dts-v1/; - -#include -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie d2 Network v2"; - compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "d2net_v2:blue:sata"; - slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - modes-map = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "d2net_v2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts deleted file mode 100644 index a9a8e6b744c7..000000000000 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-88F6281-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell DB-88F6281-BP Development Board"; - compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts deleted file mode 100644 index 6dc6579d4524..000000000000 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-88F6282-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Marvell DB-88F6282-BP Development Board"; - compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi deleted file mode 100644 index 6fe2e31534af..000000000000 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-{88F6281,88F6282}-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_sdio_gpios: pmx-sdio-gpios { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <2>; - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio_gpios>; - pinctrl-names = "default"; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts deleted file mode 100644 index 0c0851cd9bec..000000000000 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2014 Claudio Leite - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DIR-665"; - compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 =< &pmx_led_usb - &pmx_led_internet_blue - &pmx_led_internet_amber - &pmx_led_5g &pmx_led_status_blue - &pmx_led_wps &pmx_led_status_amber - &pmx_led_24g - &pmx_btn_restart &pmx_btn_wps>; - pinctrl-names = "default"; - - pmx_led_usb: pmx-led-usb { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_led_internet_blue: pmx-led-internet-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_internet_amber: pmx-led-internet-amber { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_5g: pmx-led-5g { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_status_blue: pmx-led-status-blue { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_wps: pmx-led-wps { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_status_amber: pmx-led-status-amber { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_24g: pmx-led-24g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_btn_restart: pmx-btn-restart { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_btn_wps: pmx-btn-wps { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "nvram"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "kernel"; - reg = <0x40000 0x180000>; - }; - - partition@1c0000 { - label = "rootfs"; - reg = <0x1c0000 0xe00000>; - }; - - cal_data: partition@fc0000 { - label = "cal_data"; - reg = <0xfc0000 0x10000>; - read-only; - }; - - partition@fd0000 { - label = "lang_pack"; - reg = <0xfd0000 0x30000>; - read-only; - }; - }; - }; - - serial@12000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-usb { - label = "dir665:blue:usb"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - blue-internet { - /* Can only be turned on if the Internet - * Ethernet port has Link - */ - label = "dir665:blue:internet"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - amber-internet { - label = "dir665:amber:internet"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - blue-wifi5g { - label = "dir665:blue:5g"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - blue-status { - label = "dir665:blue:status"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - blue-wps { - label = "dir665:blue:wps"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - amber-status { - label = "dir665:amber:status"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - blue-24g { - label = "dir665:blue:24g"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - phy-mode = "rgmii-id"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set - * fixed speed and duplex. */ -ð0 { - status = "okay"; - - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - phy-mode = "rgmii"; - }; -}; - -/* eth1 is connected to the switch as well. However DSA only supports a - * single CPU port. So leave this port disabled to avoid confusion. */ - -ð1 { - status = "disabled"; -}; - -/* There is no battery on the boards, so the RTC does not keep time - * when there is no power, making it useless. */ -&rtc { - status = "disabled"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts deleted file mode 100644 index d6b0f418fd01..000000000000 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-320 NAS (Rev A1)"; - compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - blue-power { - label = "dns320:blue:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - blue-usb { - label = "dns320:blue:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - orange-l_hdd { - label = "dns320:orange:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - orange-r_hdd { - label = "dns320:orange:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - orange-usb { - label = "dns320:orange:usb"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ - }; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts deleted file mode 100644 index 94d9c06cbbf5..000000000000 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-325 NAS (Rev A1)"; - compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - white-power { - label = "dns325:white:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - white-usb { - label = "dns325:white:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ - }; - red-l_hdd { - label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - red-r_hdd { - label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - red-usb { - label = "dns325:red:usb"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - - lm75: lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi deleted file mode 100644 index eb917462b219..000000000000 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DNS NASes (kirkwood-based)"; - compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power &pmx_button_unmount - &pmx_button_reset>; - pinctrl-names = "default"; - - power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - eject { - label = "USB unmount button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; - pinctrl-names = "default"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 - &pmx_present_sata1 &pmx_fan_tacho - &pmx_temp_alarm>; - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - pmx_led_red_right_hdd: pmx-led-red-right-hdd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_led_red_left_hdd: pmx-led-red-left-hdd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_325: pmx-led-red-usb-325 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_320: pmx-led-red-usb-320 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_power_back_on: pmx-power-back-on { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_present_sata0: pmx-present-sata0 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_present_sata1: pmx-present-sata1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_white_usb: pmx-led-white-usb { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_fan_tacho: pmx-fan-tacho { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_fan_high_speed: pmx-fan-high-speed { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_fan_low_speed: pmx-fan-low-speed { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_button_unmount: pmx-button-unmount { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_temp_alarm: pmx-temp-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 7 0>; - }; - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 8 0>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts deleted file mode 100644 index 264938dfa4d9..000000000000 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate FreeAgent Dockstar"; - compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_orange>; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1116"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts deleted file mode 100644 index 328516351e84..000000000000 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Dreamplug"; - compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_bluetooth: pmx-led-bluetooth { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wifi: pmx-led-wifi { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wifi_ap: pmx-led-wifi-ap { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@100000 { - reg = <0x100000 0x10000>; - label = "u-boot env"; - }; - - partition@180000 { - reg = <0x180000 0x10000>; - label = "dtb"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - - bluetooth { - label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wifi { - label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wifi-ap { - label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts deleted file mode 100644 index 29982e7acb7f..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds109.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS109, DS110, DS110jv20"; - compatible = "synology,ds109", "synology,ds110jv20", - "synology,ds110", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts deleted file mode 100644 index d68c616e9309..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds110jv10.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS110j v10 and v30"; - compatible = "synology,ds110jv10", "synology,ds110jv30", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts deleted file mode 100644 index e1420cbcd7e4..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds111.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS111"; - compatible = "synology,ds111", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts deleted file mode 100644 index 3912f1b525b6..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds112.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS112"; - compatible = "synology,ds111", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-21-2 { - status = "okay"; - }; - - regulators-hdd-30 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts deleted file mode 100644 index f41fe95e055f..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds209.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS209"; - compatible = "synology,ds209", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; - - regulators-hdd-31 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts deleted file mode 100644 index 729f959a7838..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds210.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS210 v10, v20, v30, DS211j"; - compatible = "synology,ds210jv10", "synology,ds210jv20", - "synology,ds210jv30", "synology,ds211j", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; - - regulators-hdd-31 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts deleted file mode 100644 index 416bab50d170..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds212.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; - compatible = "synology,ds212", "synology,ds212pv10", - "synology,ds212pv10", "synology,ds212pv20", - "synology,ds213airv10", "synology,ds213v10", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts deleted file mode 100644 index 14cf4d8afaf3..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds212j.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS212j v10, v20"; - compatible = "synology,ds212jv10", "synology,ds212jv20", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts deleted file mode 100644 index a8650f9e3eb7..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds409.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS409, DS410j"; - compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - gpio-leds-alarm-12 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts deleted file mode 100644 index 27a1d840bd15..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds409slim.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology 409slim"; - compatible = "synology,ds409slim", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-20 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts deleted file mode 100644 index 1d4256ef325d..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds411.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411, DS413jv10"; - compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - regulators-hdd-34 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts deleted file mode 100644 index bb3200daea1e..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds411j.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411j"; - compatible = "synology,ds411j", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - gpio-leds-alarm-12 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts deleted file mode 100644 index 9c5364a4e0a8..000000000000 --- a/arch/arm/boot/dts/kirkwood-ds411slim.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411slim"; - compatible = "synology,ds411slim", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts deleted file mode 100644 index d4cb3cd3e2a2..000000000000 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate GoFlex Net"; - compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_0: pmx-led_right_cap_0 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_1: pmx-led_right_cap_1 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_2: pmx-led_right_cap_2 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_3: pmx-led_right_cap_3 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_0: pmx-led_left_cap_0 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_1: pmx-led_left_cap_1 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_2: pmx-led_left_cap_2 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_3: pmx-led_left_cap_3 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led_green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led_orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - left0 { - label = "status:white:left0"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - left1 { - label = "status:white:left1"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - left2 { - label = "status:white:left2"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - left3 { - label = "status:white:left3"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - right0 { - label = "status:white:right0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - right1 { - label = "status:white:right1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - right2 { - label = "status:white:right2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - right3 { - label = "status:white:right3"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts deleted file mode 100644 index dfb41393941d..000000000000 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Guruplug Server Plus"; - compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health_r: pmx-led-health-r { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_health_g: pmx-led-health-g { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wmode_r: pmx-led-wmode-r { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wmode_g: pmx-led-wmode-g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - /* AzureWave AW-GH381 WiFi/BT */ - mvsdio@90000 { - status = "okay"; - non-removable; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - - health-r { - label = "guruplug:red:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - health-g { - label = "guruplug:green:health"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wmode-r { - label = "guruplug:red:wmode"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wmode-g { - label = "guruplug:green:wmode"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - phy-connection-type = "rgmii-id"; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts deleted file mode 100644 index 962a910a6f5c..000000000000 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_os_red: pmx-led-os-red { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_os_green: pmx-led-os-green { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - pmx_led_usb_transfer: pmx-led-usb-transfer { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_button_usb_copy: pmx-button-usb-copy { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green - &pmx_led_usb_transfer>; - pinctrl-names = "default"; - - green-os { - label = "ib62x0:green:os"; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - red-os { - label = "ib62x0:red:os"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; - usb-copy { - label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0xe0000>; - }; - - partition@e0000 { - label = "u-boot environment"; - reg = <0xe0000 0x20000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts deleted file mode 100644 index aed20185fd7a..000000000000 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega Iconnect"; - compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - linux,initrd-start = <0x4500040>; - linux,initrd-end = <0x4800000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_level: pmx-led-level { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_blue: pmx-led-power-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_red: pmx-power-red { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_usb1: pmx-led-usb1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_usb2: pmx-led-usb2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_usb3: pmx-led-usb3 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_usb4: pmx-led-usb4 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_otb: pmx-led-otb { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_level &pmx_led_power_blue - &pmx_led_power_red &pmx_led_usb1 - &pmx_led_usb2 &pmx_led_usb3 - &pmx_led_usb4 &pmx_led_otb >; - pinctrl-names = "default"; - - led-level { - label = "led_level"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - power-blue { - label = "power:blue"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power-red { - label = "power:red"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - usb1 { - label = "usb1:blue"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - usb2 { - label = "usb2:blue"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3:blue"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - usb4 { - label = "usb4:blue"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - otb { - label = "otb:blue"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; - pinctrl-names = "default"; - - otb { - label = "OTB Button"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts deleted file mode 100644 index 2338f495d517..000000000000 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega StorCenter ix2-200"; - compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 - &pmx_led_sata_brt_ctrl_2 - &pmx_led_backup_brt_ctrl_1 - &pmx_led_backup_brt_ctrl_2 - &pmx_led_power_brt_ctrl_1 - &pmx_led_power_brt_ctrl_2 - &pmx_led_health_brt_ctrl_1 - &pmx_led_health_brt_ctrl_2 - &pmx_led_rebuild_brt_ctrl_1 - &pmx_led_rebuild_brt_ctrl_2 >; - pinctrl-names = "default"; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - pmx_led_backup: pmx-led-backup { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_rebuild: pmx-led-rebuild { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_health: pmx-led_health { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_backup &pmx_led_power - &pmx_led_rebuild &pmx_led_health >; - pinctrl-names = "default"; - - power_led { - label = "status:white:power_led"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - rebuild_led { - label = "status:white:rebuild_led"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - health_led { - label = "status:red:health_led"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_power - &pmx_button_otb>; - pinctrl-names = "default"; - - - Power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - Reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - OTB { - label = "OTB Button"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - }; - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x1C00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts deleted file mode 100644 index 1bc16a5cdbaa..000000000000 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Internet Space v2"; - compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi deleted file mode 100644 index 52baffe45f12..000000000000 --- a/arch/arm/boot/dts/kirkwood-km_common.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; - pinctrl-names = "default"; - - pmx_i2c_gpio_sda: pmx-gpio-sda { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_i2c_gpio_scl: pmx-gpio-scl { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - }; - - i2c { - compatible = "i2c-gpio"; - gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ - &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; -}; - -&nand { - status = "okay"; - chip-delay = <25>; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts deleted file mode 100644 index 515be7bccc0a..000000000000 --- a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Fixed Eth"; - compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; /* */ - duplex = <1>; /* */ - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts deleted file mode 100644 index f035eff1c111..000000000000 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Reference Design"; - compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts deleted file mode 100644 index 9fd3581bb24b..000000000000 --- a/arch/arm/boot/dts/kirkwood-l-50.dts +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Check Point L-50 Board Description - * Copyright 2020 Pawel Dembicki - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Check Point L-50"; - compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; - pinctrl-names = "default"; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_button29: pmx_button29 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led38: pmx_led38 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio1 14 9>; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - gpio2: gpio-expander@20{ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1505q"; - reg = <0x20>; - - gpio-controller; - }; - - /* Three GPIOs from 0x21 exp. are undescribed in dts: - * 1: DSL module reset (active low) - * 5: mPCIE reset (active low) - * 6: Express card reset (active low) - */ - gpio3: gpio-expander@21{ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1505q"; - reg = <0x21>; - - gpio-controller; - }; - - rtc@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status_green { - label = "l-50:green:status"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - status_red { - label = "l-50:red:status"; - gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - }; - - wifi { - label = "l-50:green:wifi"; - gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "phy0tpt"; - }; - - internet_green { - label = "l-50:green:internet"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - - internet_red { - label = "l-50:red:internet"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - usb1_green { - label = "l-50:green:usb1"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port3>; - }; - - usb1_red { - label = "l-50:red:usb1"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - }; - - usb2_green { - label = "l-50:green:usb2"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port1>; - }; - - usb2_red { - label = "l-50:red:usb2"; - gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - }; - }; - - usb2_pwr { - compatible = "regulator-fixed"; - regulator-name = "usb2_pwr"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - usb1_pwr { - compatible = "regulator-fixed"; - regulator-name = "usb1_pwr"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - mpcie_pwr { - compatible = "regulator-fixed"; - regulator-name = "mpcie_pwr"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - express_card_pwr { - compatible = "regulator-fixed"; - regulator-name = "express_card_pwr"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - keys { - compatible = "gpio-keys"; - - factory_defaults { - label = "factory_defaults"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy8: ethernet-phy@8 { - reg = <0x08>; - }; - - switch0: switch@10 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan6"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan7"; - }; - - switch0port5: port@5 { - reg = <5>; - phy-mode = "rgmii-txid"; - link = <&switch1port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - phy-mode = "rgmii-id"; - ethernet = <ð1port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - switch@11 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11>; - dsa,member = <0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan3"; - }; - - port@1 { - reg = <1>; - label = "lan8"; - }; - - port@2 { - reg = <2>; - label = "lan4"; - }; - - port@3 { - reg = <3>; - label = "dmz"; - }; - - switch1port5: port@5 { - reg = <5>; - phy-mode = "rgmii-txid"; - link = <&switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - label = "dsl"; - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy8>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - speed = <1000>; - duplex = <1>; - phy-mode = "rgmii"; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x000c0000>; - }; - - partition@a0000 { - label = "bootldr-env"; - reg = <0x000c0000 0x00040000>; - }; - - partition@100000 { - label = "kernel-1"; - reg = <0x00100000 0x00800000>; - }; - - partition@900000 { - label = "rootfs-1"; - reg = <0x00900000 0x07100000>; - }; - - partition@7a00000 { - label = "kernel-2"; - reg = <0x07a00000 0x00800000>; - }; - - partition@8200000 { - label = "rootfs-2"; - reg = <0x08200000 0x07100000>; - }; - - partition@f300000 { - label = "default_sw"; - reg = <0x0f300000 0x07900000>; - }; - - partition@16c00000 { - label = "logs"; - reg = <0x16c00000 0x01800000>; - }; - - partition@18400000 { - label = "preset_cfg"; - reg = <0x18400000 0x00100000>; - }; - - partition@18500000 { - label = "adsl"; - reg = <0x18500000 0x00100000>; - }; - - partition@18600000 { - label = "storage"; - reg = <0x18600000 0x07a00000>; - }; -}; - -&rtc { - status = "disabled"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; - -&usb0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - #trigger-source-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - hub_port3: port@3 { - reg = <3>; - #trigger-source-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts deleted file mode 100644 index 8c2b540eaf4f..000000000000 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013 Maxime Hadjinlian - * - */ - -/dts-v1/; - -#include -#include -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "LaCie LaPlug"; - compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "laplug_v2:red:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - blue-power { - label = "laplug_v2:blue:power"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power_back1: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power Back 1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - usb_power_back2: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "USB Power Back 2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - - usb_power_front: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "USB Power Front"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - /* Total size : 512MB */ - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; /* 1MB */ - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x1000000>; /* 16MB */ - }; - - partition@1100000 { - label = "rootfs"; - reg = <0x1100000 0x1EF00000>; /* 495MB */ - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi b/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi deleted file mode 100644 index 377b6e970259..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree common file for kirkwood-6282 based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-linkstation.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - function-button { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - red-alarm-led { - label = "linkstation:red:alarm"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - red-function-led { - label = "linkstation:red:function"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - amber-info-led { - label = "linkstation:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - - blue-function-led { - label = "linkstation:blue:function"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - blue-power-led { - label = "linkstation:blue:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio0 17 GPIO_ACTIVE_LOW - &gpio0 16 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - regulators { - usb_power: regulator@1 { - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - - hdd_power0: regulator@2 { - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi b/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi deleted file mode 100644 index ba629e02ba31..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-linkstation.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_keys { - function-button { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - red-alarm-led { - label = "linkstation:red:alarm"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - - red-function-led { - label = "linkstation:red:function"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - amber-info-led { - label = "linkstation:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - blue-function-led { - label = "linkstation:blue:function"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - blue-power-led { - label = "linkstation:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - usb_power: regulator@1 { - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - hdd_power0: regulator@2 { - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts deleted file mode 100644 index 8bb381088910..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-QVL - * - * Copyright (C) 2016, Mario Lange - * - * Based on kirkwood-linkstation-lswvl.dts, - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-QVL"; - compatible = "buffalo,lsqvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_hdderr2: pmx-led-hdderr2 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_hdderr3: pmx-led-hdderr3 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1 - &pmx_led_hdderr2 - &pmx_led_hdderr3>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - - red-hdderr2-led { - label = "linkstation:red:hdderr2"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - red-hdderr3-led { - label = "linkstation:red:hdderr3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts deleted file mode 100644 index 3f2a0bfe03ed..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-VL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-VL"; - compatible = "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts deleted file mode 100644 index c42d0da38fe7..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-WSXL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-duo-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WSXL"; - compatible = "buffalo,lswsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts deleted file mode 100644 index e0f62adc0d5d..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-WVL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-WVL"; - compatible = "buffalo,lswvl","marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts deleted file mode 100644 index c6024b569423..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-WXL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-duo-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WXL"; - compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio1 16 GPIO_ACTIVE_LOW - &gpio1 15 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/kirkwood-linkstation.dtsi deleted file mode 100644 index b54c9980f636..000000000000 --- a/arch/arm/boot/dts/kirkwood-linkstation.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree common file for kirkwood based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - function-button { - label = "Function Button"; - linux,code = ; - }; - - power-on-switch { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - }; - - power-auto-switch { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd0 &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - hdd_power0: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts deleted file mode 100644 index 27fd6e2337d5..000000000000 --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) - * - * (c) 2013 Jonas Gorski - * (c) 2013 Deutsche Telekom Innovation Laboratories - * (c) 2014 Luka Perkov - * (c) 2014 Randy C. Will - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Linksys Viper (E4200v2 / EA4500)"; - compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; - pinctrl-names = "default"; - - wps { - label = "WPS Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; - pinctrl-names = "default"; - - white-health { - label = "viper:white:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - white-pulse { - label = "viper:white:pulse"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pmx_led_white_health: pmx-led-white-health { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - pmx_led_white_pulse: pmx-led-white-pulse { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - pmx_btn_wps: pmx-btn-wps { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u_env"; - reg = <0x80000 0x20000>; - }; - - partition@a0000 { - label = "s_env"; - reg = <0xA0000 0x20000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x2A0000>; - }; - - partition@4a0000 { - label = "rootfs"; - reg = <0x4A0000 0x1760000>; - }; - - partition@1c00000 { - label = "alt_kernel"; - reg = <0x1C00000 0x2A0000>; - }; - - partition@1ea0000 { - label = "alt_rootfs"; - reg = <0x1EA0000 0x1760000>; - }; - - partition@3600000 { - label = "syscfg"; - reg = <0x3600000 0x4A00000>; - }; - - partition@c0000 { - label = "unused"; - reg = <0xC0000 0x140000>; - }; - - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&mdio { - status = "okay"; - - switch@10 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <16>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "ethernet1"; - }; - - port@1 { - reg = <1>; - label = "ethernet2"; - }; - - port@2 { - reg = <2>; - label = "ethernet3"; - }; - - port@3 { - reg = <3>; - label = "ethernet4"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - phy-mode = "rgmii-id"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set - * fixed speed and duplex. - */ -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - phy-mode = "rgmii"; - }; -}; - -/* eth1 is connected to the switch at port 6. However DSA only supports a - * single CPU port. So leave this port disabled to avoid confusion. - */ -ð1 { - status = "disabled"; -}; - -/* There is no battery on the board, so the RTC does not keep - * time when there is no power, making it useless. - */ -&rtc { - status = "disabled"; -}; - diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts deleted file mode 100644 index 1d737d903f5f..000000000000 --- a/arch/arm/boot/dts/kirkwood-lschlv2.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-CHLv2"; - compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts deleted file mode 100644 index a56e0d797778..000000000000 --- a/arch/arm/boot/dts/kirkwood-lsxhl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-XHL"; - compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi deleted file mode 100644 index 88b70ba1c8fe..000000000000 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - /* Non-default UART pins */ - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp4", "mpp5"; - }; - - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp19"; - marvell,function = "gpo"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function_red { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - }; - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - option { - label = "Function Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - reserved { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - power { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - - func_blue { - label = "lsxl:blue:func"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - alarm { - label = "lsxl:red:alarm"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lsxl:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lsxl:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - func_red { - label = "lsxl:red:func"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW - &gpio0 18 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 11 0>; - }; - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 0>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts deleted file mode 100644 index e87ea7146546..000000000000 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "MPL CEC4"; - compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health: pmx-led-health { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp34"; - marvell,function = "sata1"; - }; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp35"; - marvell,function = "sata0"; - }; - - pmx_led_user1o: pmx-led-user1o { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_led_user1g: pmx-led-user1g { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_user0o: pmx-led-user0o { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_led_user0g: pmx-led-user0g { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_led_misc: pmx-led-misc { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - i2c@11000 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - }; - - }; - - serial@12000 { - status = "okay"; - }; - - rtc@10300 { - status = "disabled"; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <2>; - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - /* No WP GPIO */ - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health - &pmx_led_user1o - &pmx_led_user1g &pmx_led_user0o - &pmx_led_user0g &pmx_led_misc - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - }; - - user1o { - label = "user1:orange"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user1g { - label = "user1:green"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0o { - label = "user0:orange"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0g { - label = "user0:green"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - misc { - label = "status:orange:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "fdt"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x400000>; - }; - - partition@600000 { - label = "rootfs"; - reg = <0x600000 0x1fa00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts deleted file mode 100644 index 5a77286136c7..000000000000 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell 88F6281 GTW GE Board - * - * Lennert Buytenhek - * Thomas Petazzoni - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell 88F6281 GTW GE Board"; - compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_usb_led: pmx-usb-led { - marvell,pins = "mpp12"; - marvell,function = "gpo"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp20", "mpp21"; - marvell,function = "gpio"; - }; - - pmx_keys: pmx-keys { - marvell,pins = "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds &pmx_usb_led>; - pinctrl-names = "default"; - - green-status { - label = "gtw:green:Status"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - }; - - red-status { - label = "gtw:red:Status"; - gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - - green-usb { - label = "gtw:green:USB"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_keys>; - pinctrl-names = "default"; - - restart { - label = "SWR Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wps { - label = "WPS Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - phy-mode = "rgmii-id"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - phy-mode = "rgmii"; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts deleted file mode 100644 index 0b0a15093146..000000000000 --- a/arch/arm/boot/dts/kirkwood-nas2big.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 2Big NAS - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - * -*/ - -/dts-v1/; - -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big NAS"; - compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - rtc@10300 { - /* The on-chip RTC is not powered (no supercap). */ - status = "disabled"; - }; - spi@10600 { - /* - * A NAND flash is used instead of an SPI flash for - * the other netxbig-compatible boards. - */ - status = "disabled"; - }; - }; - - fan { - /* - * An I2C fan controller (GMT G762) is used but alarm is - * wired to a separate GPIO. - */ - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - /* - * An external I2C RTC (Dallas DS1337S+) is used. This allows - * to power-up the board on an RTC alarm. The external RTC can - * be kept powered, even when the SoC is off. - */ - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - interrupts = <43>; - }; - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; - -&nand { - chip-delay = <50>; - status = "okay"; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x1000000>; - }; - - partition@1100000 { - label = "root"; - reg = <0x1100000 0x8000000>; - }; - - partition@9100000 { - label = "unused"; - reg = <0x9100000 0x6f00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts deleted file mode 100644 index d5f6bb50ba11..000000000000 --- a/arch/arm/boot/dts/kirkwood-net2big.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 2Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big Network v2"; - compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - fan { - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts deleted file mode 100644 index 2497ad26b5b6..000000000000 --- a/arch/arm/boot/dts/kirkwood-net5big.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 5Big Network v2"; - compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - netxbig-leds { - blue-sata2 { - label = "netxbig:blue:sata2"; - mode-addr = <5>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata2 { - label = "netxbig:red:sata2"; - mode-addr = <5>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata3 { - label = "netxbig:blue:sata3"; - mode-addr = <6>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata3 { - label = "netxbig:red:sata3"; - mode-addr = <6>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata4 { - label = "netxbig:blue:sata4"; - mode-addr = <7>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata4 { - label = "netxbig:red:sata4"; - mode-addr = <7>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts deleted file mode 100644 index cb564c3bcdc4..000000000000 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for NETGEAR ReadyNAS Duo v2 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "NETGEAR ReadyNAS Duo v2"; - compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_button_backup: pmx-button-backup { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_blue_power: pmx-led-blue-power { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_led_blue_activity: pmx-led-blue-activity { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk1: pmx-led-blue-disk1 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk2: pmx-led-blue-disk2 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_blue_backup: pmx-led-blue-backup { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - i2c@11000 { - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity - &pmx_led_blue_disk1 &pmx_led_blue_disk2 - &pmx_led_blue_backup >; - pinctrl-names = "default"; - - power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - activity_led { - label = "status:blue:activity_led"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power &pmx_button_backup - &pmx_button_reset>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_regulator: usb3-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts deleted file mode 100644 index 6cf76430cfab..000000000000 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for NETGEAR ReadyNAS NV+ v2 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "NETGEAR ReadyNAS NV+ v2"; - compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_button_backup: pmx-button-backup { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_blue_power: pmx-led-blue-power { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_led_blue_backup: pmx-led-blue-backup { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk1: pmx-led-blue-disk1 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk2: pmx-led-blue-disk2 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk3: pmx-led-blue-disk3 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk4: pmx-led-blue-disk4 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - i2c@11000 { - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ - status = "okay"; - nr-ports = <1>; - }; - }; - - auxdisplay { - compatible = "hit,hd44780"; - data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>, - <&gpio1 1 GPIO_ACTIVE_HIGH>, - <&gpio1 3 GPIO_ACTIVE_HIGH>, - <&gpio1 17 GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - display-height-chars = <2>; - display-width-chars = <16>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup - &pmx_led_blue_disk1 &pmx_led_blue_disk2 - &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; - pinctrl-names = "default"; - - power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - disk3_led { - label = "status:blue:disk3_led"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - disk4_led { - label = "status:blue:disk4_led"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power &pmx_button_backup - &pmx_button_reset>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_regulator: usb3-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -/* Connected to NEC uPD720200 USB 3.0 controller */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/kirkwood-netxbig.dtsi deleted file mode 100644 index b5737026e244..000000000000 --- a/arch/arm/boot/dts/kirkwood-netxbig.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for LaCie 2Big and 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * -*/ - -#include -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * esc and power represent a three position rocker - * switch. Thus the conventional KEY_POWER does not fit - */ - exc { - label = "Back power switch (on|auto)"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - power { - label = "Back power switch (auto|off)"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - option { - label = "Function button"; - linux,code = ; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd0power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; - - netxbig_gpio_ext: netxbig-gpio-ext { - compatible = "lacie,netxbig-gpio-ext"; - - addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH - &gpio1 16 GPIO_ACTIVE_HIGH - &gpio1 17 GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH - &gpio1 14 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - netxbig-leds { - compatible = "lacie,netxbig-leds"; - - gpio-ext = <&netxbig_gpio_ext>; - - timers = ; - - blue-power { - label = "netxbig:blue:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - red-power { - label = "netxbig:red:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - blue-sata0 { - label = "netxbig:blue:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata0 { - label = "netxbig:red:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata1 { - label = "netxbig:blue:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata1 { - label = "netxbig:red:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - - pmx_button_function: pmx-button-function { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_button_power_off: pmx-button-power-off { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_button_power_on: pmx-button-power-on { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi deleted file mode 100644 index 51530ea86622..000000000000 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_ns2_sata0: pmx-ns2-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_ns2_sata1: pmx-ns2-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "ns2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts deleted file mode 100644 index 7b67083e1ec0..000000000000 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space v2"; - compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts deleted file mode 100644 index b0cb5907ed63..000000000000 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Lite v2"; - compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-sata { - label = "ns2:blue:sata"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts deleted file mode 100644 index c0a087e77408..000000000000 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Max v2"; - compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 1500 15 - 1700 14 - 1800 13 - 2100 12 - 3100 11 - 3300 10 - 4300 9 - 5500 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts deleted file mode 100644 index 5b9fa14b6428..000000000000 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - /* This machine is embedded in the first LaCie CloudBox product. */ - model = "LaCie Network Space Mini v2"; - compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 3000 15 - 3180 14 - 4140 13 - 4570 12 - 6760 11 - 7140 10 - 7980 9 - 9200 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts deleted file mode 100644 index c1799a07816e..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_unknown>; - pinctrl-names = "default"; - - pmx_led_esata_green: pmx-led-esata-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_esata_red: pmx-led-esata-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_usb_red: pmx-led-usb-red { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_green: pmx-led-hdd-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_red: pmx-led-hdd-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_unknown: pmx-unknown { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - }; - - i2c@11000 { - status = "okay"; - - adt7476: adt7476a@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red - &pmx_led_usb_green &pmx_led_usb_red - &pmx_led_sys_green &pmx_led_sys_red - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd_green &pmx_led_hdd_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa310:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - red-sys { - label = "nsa310:red:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd { - label = "nsa310:green:hdd"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd { - label = "nsa310:red:hdd"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-esata { - label = "nsa310:green:esata"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-esata { - label = "nsa310:red:esata"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - red-usb { - label = "nsa310:red:usb"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa310:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts deleted file mode 100644 index b85e314f045a..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/* - * There are at least two different NSA310 designs. This variant does - * not have the red USB Led. - */ - -/ { - compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_esata_green: pmx-led-esata-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_esata_red: pmx-led-esata-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_green: pmx-led-hdd-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_red: pmx-led-hdd-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - }; - - i2c@11000 { - status = "okay"; - - lm85: lm85@2e { - compatible = "national,lm85"; - reg = <0x2e>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green-sys { - label = "nsa310:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - red-sys { - label = "nsa310:red:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd { - label = "nsa310:green:hdd"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd { - label = "nsa310:red:hdd"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-esata { - label = "nsa310:green:esata"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-esata { - label = "nsa310:red:esata"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa310:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa310s.dts b/arch/arm/boot/dts/kirkwood-nsa310s.dts deleted file mode 100644 index 49da633a1bc0..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa310s.dts +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * ZyXEL NSA310S Board Description - * Copyright 2020-2022 Pawel Dembicki - * Copyright (c) 2015-2021, Tony Dinh - * Copyright (c) 2014, Adam Baker - * Based upon the board setup file created by Peter Schildmann - */ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include - -/ { - model = "ZyXEL NSA310S"; - compatible = "zyxel,nsa310s", "marvell,kirkwood-88f6702", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - - keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - }; - - copy { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-1 { - function = LED_FUNCTION_DISK_ERR; - color = ; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - function = LED_FUNCTION_USB; - color = ; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usb-host"; - }; - - led-3 { - function = LED_FUNCTION_DISK; - color = ; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ata1"; - }; - - led-4 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; - - led-5 { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "USB Power"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "SATA1 Power"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - thermal-zones { - disk-thermal { - polling-delay = <20000>; - polling-delay-passive = <2000>; - - thermal-sensors = <&hdd_temp>; - - trips { - disk_alert: disk-alert { - temperature = <40000>; - hysteresis = <5000>; - type = "active"; - }; - disk_crit: disk-crit { - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&i2c0 { - status = "okay"; - - rtc@68 { - compatible = "htk,ht1382"; - reg = <0x68>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@1 { - reg = <1>; - phy-mode = "rgmii-id"; - marvell,reg-init = <0x1 0x16 0x0 0x3>, - <0x1 0x10 0x0 0x1017>, - <0x1 0x11 0x0 0x4408>, - <0x1 0x16 0x0 0x0>; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x00c0000>; - read-only; - }; - partition@c0000 { - label = "uboot_env"; - reg = <0x00c0000 0x0080000>; - }; - partition@140000 { - label = "ubi"; - reg = <0x0140000 0x7ec0000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp24", "mpp25", "mpp26"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp13", "mpp15", "mpp16", "mpp22", "mpp23", - "mpp28", "mpp29"; - marvell,function = "gpio"; - }; - - pmx_power: pmx-power { - marvell,pins = "mpp21", "mpp33"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; -}; - -&rtc { - status = "disabled"; -}; - -&sata { - status = "okay"; - nr-ports = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hdd_temp: sata-port@0 { - reg = <0>; - #thermal-sensor-cells = <0>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts deleted file mode 100644 index 652405e65006..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa320.dts +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Device tree file for the Zyxel NSA 320 NAS box. - * - * Copyright (c) 2014, Adam Baker - * - * - * Based upon the board setup file created by Peter Schildmann */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "Zyxel NSA320"; - compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - /* SATA Activity and Present pins are not connected */ - pmx_sata0: pmx-sata0 { - marvell,pins ; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins ; - marvell,function = "sata1"; - }; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* Buzzer needs to be switched at around 1kHz so is - not compatible with the gpio-beeper driver. */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - usb0_power: regulator@1 { - enable-active-high; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa320:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa320:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa320:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa320:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa320:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa320:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa320:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa320:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa320:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; - - hwmon { - compatible = "zyxel,nsa320-mcu"; - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; - pinctrl-names = "default"; - - data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/kirkwood-nsa325.dts deleted file mode 100644 index 371456de34b2..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa325.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Device tree file for the Zyxel NSA 325 NAS box. - * - * Copyright (c) 2015, Hans Ulli Kroll - * - * - * Based upon the board setup file created by Peter Schildmann - */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "ZyXEL NSA325"; - compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* - * Buzzer needs to be switched at around 1kHz so is - * not compatible with the gpio-beeper driver. - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - /* This board uses the pcf8563 RTC instead of the SoC RTC */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_pwr_sata1>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - enable-active-high; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa325:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa325:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa325:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa325:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa325:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa325:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa325:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa325:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa325:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act - &pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ - }; - - -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi deleted file mode 100644 index ea3d36512e9f..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "ZyXEL NSA310"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - copy { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts deleted file mode 100644 index 8ea430168ea5..000000000000 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA6"; - compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "gpio"; - }; - - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", - "mpp28", "mpp29", "mpp30", "mpp31"; - marvell,function = "gpio"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa6:red:stat"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - led-green { - label = "obsa6:green:stat"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-yellow { - label = "obsa6:yellow:stat"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x90000>; - }; - - partition@90000 { - label = "env"; - reg = <0x90000 0x44000>; - }; - - partition@d4000 { - label = "test"; - reg = <0xd4000 0x20000>; - }; - - partition@f4000 { - label = "conf"; - reg = <0xf4000 0x400000>; - }; - - partition@4f4000 { - label = "linux"; - reg = <0x4f4000 0x1d20000>; - }; - - partition@2214000 { - label = "user"; - reg = <0x2214000 0x1dec000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&gpio0 { - status = "okay"; - - pinctrl-0 = <&pmx_gpio_header>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts deleted file mode 100644 index 946f0f453dd1..000000000000 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for OpenBlocks A7 board - * - * Copyright (C) 2013 Free Electrons - * - * Thomas Petazzoni - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA7"; - compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - - s24c02: s24c02@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header - &pmx_gpio_header_gpo>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - - /* - * Accessible on connector J202. The MPP - * listed below are pin 1-7, pin 8 is unused, - * pin 9 is external reset input and pin 10 is - * ground. - */ - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp17", "mpp29", "mpp28", - "mpp35", "mpp34", "mpp40"; - marvell,function = "gpio"; - }; - - pmx_gpio_header_gpo: pxm-gpio-header-gpo { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa7:red:stat"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - led-green { - label = "obsa7:green:stat"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-yellow { - label = "obsa7:yellow:stat"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - button { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x1c0000>; - }; - - partition@1c0000 { - label = "env"; - reg = <0x1c0000 0x2c0000>; - }; - - partition@480000 { - label = "test"; - reg = <0x480000 0x160000>; - }; - - partition@5e0000 { - label = "conf"; - reg = <0x5e0000 0x540000>; - }; - - partition@b20000 { - label = "linux"; - reg = <0xb20000 0x3d40000>; - }; - - partition@4860000 { - label = "user"; - reg = <0x4860000 0xb7a0000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/kirkwood-openrd-base.dts deleted file mode 100644 index 094191ece3d7..000000000000 --- a/arch/arm/boot/dts/kirkwood-openrd-base.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Base Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are specific to OpenRD - * base variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Base"; - compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - serial@12100 { - status = "okay"; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/kirkwood-openrd-client.dts deleted file mode 100644 index d4e0b8150a84..000000000000 --- a/arch/arm/boot/dts/kirkwood-openrd-client.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Client Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are specific to OpenRD - * client variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Client"; - compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - audio-controller@a0000 { - status = "okay"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio0 0>; - }; - - simple-audio-card,codec { - sound-dai = <&cs42l51>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; - ethphy1: ethernet-phy@24 { - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts deleted file mode 100644 index 888e13320c19..000000000000 --- a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Ultimate Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are specific to OpenRD - * ultimate variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Ultimate"; - compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/kirkwood-openrd.dtsi deleted file mode 100644 index 47f03c69c55a..000000000000 --- a/arch/arm/boot/dts/kirkwood-openrd.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD (Base|Client|Ultimate) Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; - pinctrl-names = "default"; - - pmx_select28: pmx-select-rs232-rs485 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_select34: pmx-select-uart-sd { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - - }; - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio0 29 9>; - }; - gpio@10100 { - p28 { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - /* - * SelRS232or485 selects between RS-232 or RS-485 - * mode for the second UART. - * - * Low: RS-232 - * High: RS-485 - * - * To use the second UART, you need to change also - * the SelUARTorSD. - */ - output-low; - line-name = "SelRS232or485"; - }; - }; - gpio@10140 { - p2 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - /* - * SelUARTorSD selects between the second UART - * (serial@12100) and SD (mvsdio@90000). - * - * Low: UART - * High: SD - * - * When changing this line make sure the newly - * selected device node is enabled and the - * previously selected device node is disabled. - */ - output-high; /* Select SD by default */ - line-name = "SelUARTorSD"; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@600000 { - label = "root"; - reg = <0x0600000 0x1FA00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/kirkwood-pogo_e02.dts deleted file mode 100644 index f9e95e55f36d..000000000000 --- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 - * - * Copyright (C) 2015 Christoph Junghans - * - * based on information of dts files from - * Arch Linux ARM by Oleg Rakhmanov - * OpenWrt by Felix Kaechele - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Cloud Engines Pogoplug E02"; - compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - - health { - label = "pogo_e02:green:health"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "pogo_e02:orange:fault"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_green >; - pinctrl-names = "default"; - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0x5b00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts deleted file mode 100644 index 5aa4669ae254..000000000000 --- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 - * inspired by the board files made by Kevin Mihelich for ArchLinux, - * and their DTS file. - * - * Copyright (C) 2015 Linus Walleij - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" -#include - -/ { - model = "Cloud Engines PogoPlug Series 4"; - compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - chosen { - stdout-path = "uart0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_eject>; - pinctrl-names = "default"; - - eject { - debounce-interval = <50>; - wakeup-source; - linux,code = ; - label = "Eject Button"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "pogoplugv4:green:health"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - fault { - label = "pogoplugv4:red:fault"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_eject: pmx-button-eject { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_red: pmx-led-red { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* - * This PCIE controller has a USB 3.0 XHCI controller at 1,0 - */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&sata { - status = "okay"; - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <1>; -}; - -&sdio { - status = "okay"; - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -}; - -&nand { - /* 128 MiB of NAND flash */ - chip-delay = <40>; - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x00200000 0x300000>; - }; - - partition@500000 { - label = "uImage2"; - reg = <0x00500000 0x300000>; - }; - - partition@800000 { - label = "failsafe"; - reg = <0x00800000 0x800000>; - }; - - partition@1000000 { - label = "root"; - reg = <0x01000000 0x7000000>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts deleted file mode 100644 index f00325ffde07..000000000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6192 Board descrition - * - * Andrew Lunn - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Marvell RD88F6192 reference design"; - compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - }; - - serial@12000 { - status = "okay"; - - }; - - spi@10600 { - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts deleted file mode 100644 index 5da163591bbf..000000000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6181 A Board descrition - * - * Andrew Lunn - * - * This file contains the definitions for the board with the A0 or - * higher stepping of the SoC. The ethernet switch does not have a - * "wan" port. - */ - -/dts-v1/; -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; - compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@11 { - reg = <11>; - }; -}; - -&switch { - reg = <10>; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts deleted file mode 100644 index 72edd47e19ff..000000000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6181 Z0 stepping descrition - * - * Andrew Lunn - * - * This file contains the definitions for the board using the Z0 - * stepping of the SoC. The ethernet switch has a "wan" port. -*/ - -/dts-v1/; - -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with Z0 SoC"; - compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - -}; - -ð1 { - status = "disabled"; -}; - -&switch { - reg = <0>; - - ports { - port@4 { - reg = <4>; - label = "wan"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi deleted file mode 100644 index 9d62f910cddf..000000000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6181 Common Board descrition - * - * Andrew Lunn - * - * This file contains the definitions that are common between the two - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - /* No WP GPIO */ - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x200000>; - }; - - partition@300000 { - label = "rootfs"; - reg = <0x0300000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - phy-mode = "rgmii-id"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - }; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts deleted file mode 100644 index 4ad412115a24..000000000000 --- a/arch/arm/boot/dts/kirkwood-rs212.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS212"; - compatible = "synology,rs212", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-3 { - status = "okay"; - }; - - gpio-leds-hdd-38 { - status = "okay"; - }; - - regulators-hdd-30-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts deleted file mode 100644 index 43673b03cb35..000000000000 --- a/arch/arm/boot/dts/kirkwood-rs409.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS409"; - compatible = "synology,rs409", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts deleted file mode 100644 index 41fa63cec839..000000000000 --- a/arch/arm/boot/dts/kirkwood-rs411.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS411 RS812"; - compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-3 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b7393..000000000000 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs - * - * Copyright (C) 2013 Simon Baatz - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts deleted file mode 100644 index ae8f493c9a0f..000000000000 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug - * - * Copyright (C) 2013 Simon Baatz - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies eSATA SheevaPlug"; - compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c4..000000000000 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug - * - * Copyright (C) 2013 Simon Baatz - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - misc { - label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi deleted file mode 100644 index 9b6666020cdd..000000000000 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Nodes for Marvell 628x Synology devices - * - * Andrew Lunn - * Ben Peddell - * - */ - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_alarmled_12: pmx-alarmled-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_15: pmx-fanctrl-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_16: pmx-fanctrl-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_17: pmx-fanctrl-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_18: pmx-fanalarm-18 { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - - pmx_hddled_20: pmx-hddled-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_hddled_21: pmx-hddled-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_hddled_22: pmx-hddled-22 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_hddled_23: pmx-hddled-23 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_hddled_24: pmx-hddled-24 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_hddled_25: pmx-hddled-25 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_hddled_26: pmx-hddled-26 { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_hddled_27: pmx-hddled-27 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_hddled_28: pmx-hddled-28 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_32: pmx-fanctrl-32 { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_33: pmx-fanctrl-33 { - marvell,pins = "mpp33"; - marvell,function = "gpo"; - }; - - pmx_fanctrl_34: pmx-fanctrl-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_35: pmx-fanalarm-35 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - pmx_hddled_36: pmx-hddled-36 { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_hddled_37: pmx-hddled-37 { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_hddled_38: pmx-hddled-38 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_hddled_39: pmx-hddled-39 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_hddled_40: pmx-hddled-40 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_hddled_41: pmx-hddled-41 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_hddled_42: pmx-hddled-42 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_hddled_43: pmx-hddled-43 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_hddled_44: pmx-hddled-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hddled_45: pmx-hddled-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_44: pmx-fanalarm-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_45: pmx-fanalarm-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - }; - - rtc@10300 { - status = "disabled"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x00000000 0x00080000>; - label = "RedBoot"; - }; - - partition@80000 { - reg = <0x00080000 0x00200000>; - label = "zImage"; - }; - - partition@280000 { - reg = <0x00280000 0x00140000>; - label = "rd.gz"; - }; - - partition@3c0000 { - reg = <0x003c0000 0x00010000>; - label = "vendor"; - }; - - partition@3d0000 { - reg = <0x003d0000 0x00020000>; - label = "RedBoot config"; - }; - - partition@3f0000 { - reg = <0x003f0000 0x00010000>; - label = "FIS directory"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - rs5c372: rs5c372@32 { - status = "disabled"; - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - s35390a: s35390a@30 { - status = "disabled"; - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-fan-150-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-150-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-100-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-1 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-3 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH - &gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-leds-alarm-12 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_alarmled_12>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:alarm"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-20 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 - &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 - &pmx_hddled_26 &pmx_hddled_27>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-1 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-2 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-36 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 - &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 - &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 - &pmx_hddled_45>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - hdd5-green { - label = "synology:green:hdd5"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - - hdd5-amber { - label = "synology:amber:hdd5"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-38 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; - - regulators-hdd-29 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-1 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-2 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-4 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 - &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-31 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-34 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 - &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - reg = <9>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "disabled"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts deleted file mode 100644 index ad093324e075..000000000000 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for HP t5325 Thin Client" - * - * Copyright (C) 2014 - * - * Thomas Petazzoni - * Andrew Lunn - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "HP t5325 Thin Client"; - compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_i2s &pmx_sysrst>; - pinctrl-names = "default"; - - pmx_button_power: pmx-button_power { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_off: pmx-power-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led: pmx-led { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_spi: pmx-spi { - marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; - marvell,function = "spi"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_i2s: pmx-i2s { - marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", - "mpp43"; - marvell,function = "audio"; - }; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - spi-max-frequency = <86000000>; - reg = <0>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@1 { - reg = <0x80000 0x40000>; - label = "SSD firmware"; - }; - - partition@2 { - reg = <0xc0000 0x10000>; - label = "u-boot env"; - }; - - partition@3 { - reg = <0xd0000 0x10000>; - label = "permanent u-boot env"; - }; - - partition@4 { - reg = <0xd0000 0x10000>; - label = "permanent u-boot env"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - alc5621: alc5621@1a { - compatible = "realtek,alc5621"; - reg = <0x1a>; - #sound-dai-cells = <0>; - add-ctrl = <0x3700>; - jack-det-ctrl = <0x4810>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - audio: audio-controller@a0000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_sata_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB-SATA Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Speaker", "SPKOUT", - "Speaker", "SPKOUTN", - "MIC1", "Mic Jack", - "MIC2", "Mic Jack"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speaker", "Speaker", - "Microphone", "Mic Jack"; - - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio>; - }; - - simple-audio-card,codec { - sound-dai = <&alc5621>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts deleted file mode 100644 index a5b51e29f63e..000000000000 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Universal Scientific Industrial Co. Topkick-1281P2"; - compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - /* - * Switch positions - * - * /-SW_LEFT(2) - * | - * | /-SW_IDLE - * | | - * | | /-SW_RIGHT - * | | | - * PS [L] [I] [R] LEDS - */ - pinctrl-0 = <&pmx_sw_left &pmx_sw_right - &pmx_sw_idle &pmx_sw_left2>; - pinctrl-names = "default"; - - pmx_led_disk_yellow: pmx-led-disk-yellow { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_sata0_pwr_enable: pmx-sata0-pwr-enable { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_sys_blue: pmx-led-sys-blue { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_led_wifi_green: pmx-led-wifi-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_sw_left: pmx-sw-left { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_sw_right: pmx-sw-right { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_sw_idle: pmx-sw-idle { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_sw_left2: pmx-sw-left2 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_wifi_yellow: pmx-led-wifi-yellow { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - i2c@11000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - /* - * GPIO LED layout - * - * /-SYS_LED(2) - * | - * | /-DISK_LED - * | | - * | | /-WLAN_LED(2) - * | | | - * [SW] [*] [*] [*] - */ - - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red - &pmx_led_sys_blue &pmx_led_wifi_green - &pmx_led_wifi_yellow>; - pinctrl-names = "default"; - - disk { - label = "topkick:yellow:disk"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - system2 { - label = "topkick:red:system"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - system { - label = "topkick:blue:system"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - wifi { - label = "topkick:green:wifi"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "topkick:yellow:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_pwr_enable>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 4 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - }; - - partition@180000 { - label = "u-boot env"; - reg = <0x0180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "uInitrd"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "rootfs"; - reg = <0x1800000 0xe800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts deleted file mode 100644 index 30892c19aceb..000000000000 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-ts219.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_ram_size &pmx_board_id>; - pinctrl-names = "default"; - - pmx_ram_size: pmx-ram-size { - /* RAM: 0: 256 MB, 1: 512 MB */ - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_board_id: pmx-board-id { - /* 0: TS-11x, 1: TS-21x */ - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts deleted file mode 100644 index aba1205981f1..000000000000 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-ts219.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_ram_size &pmx_board_id>; - pinctrl-names = "default"; - - pmx_ram_size: pmx-ram-size { - /* RAM: 0: 256 MB, 1: 512 MB */ - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_board_id: pmx-board-id { - /* 0: TS-11x, 1: TS-21x */ - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ðphy0 { reg = <0>; }; - -&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi deleted file mode 100644 index 1939462a5f48..000000000000 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - model = "QNAP TS219 family"; - compatible = "qnap,ts219", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - poweroff@12100 { - compatible = "qnap,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - spi@10600 { - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x00000000 0x00080000>; - label = "U-Boot"; - }; - - partition@200000 { - reg = <0x00200000 0x00200000>; - label = "Kernel"; - }; - - partition@400000 { - reg = <0x00400000 0x00900000>; - label = "RootFS1"; - }; - partition@d00000 { - reg = <0x00d00000 0x00300000>; - label = "RootFS2"; - }; - partition@40000 { - reg = <0x00080000 0x00040000>; - label = "U-Boot Config"; - }; - partition@c0000 { - reg = <0x000c0000 0x00140000>; - label = "NAS Config"; - }; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&rtc { - /* - * There is a s35390a available on the i2c bus, the internal rtc isn't - * working (probably no crystal assembled). - */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/kirkwood-ts419-6281.dts deleted file mode 100644 index 4a42ebcca4f0..000000000000 --- a/arch/arm/boot/dts/kirkwood-ts419-6281.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for QNAP TS41X with 6281 SoC - * - * Copyright (C) 2013, Andrew Lunn - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-ts219.dtsi" -#include "kirkwood-ts419.dtsi" - -ðphy0 { reg = <8>; }; -ðphy1 { reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/kirkwood-ts419-6282.dts deleted file mode 100644 index be772e194c2b..000000000000 --- a/arch/arm/boot/dts/kirkwood-ts419-6282.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for QNAP TS41X with 6282 SoC - * - * Copyright (C) 2013, Andrew Lunn - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-ts219.dtsi" -#include "kirkwood-ts419.dtsi" - -ðphy0 { reg = <0>; }; -ðphy1 { reg = <1>; }; - -&pciec { status = "okay"; }; -&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi deleted file mode 100644 index 717236853e45..000000000000 --- a/arch/arm/boot/dts/kirkwood-ts419.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree include file for QNAP TS41X - * - * Copyright (C) 2013, Andrew Lunn - */ - -/ { - model = "QNAP TS419 family"; - compatible = "qnap,ts419", "marvell,kirkwood"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - /* - * JP1 indicates if an LCD module is installed - * on the serial port (0), or if the port is used - * as a console (1). - */ - pmx_jumper_jp1: pmx-jumper_jp1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - /* overwrite reg property in board file */ - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi deleted file mode 100644 index 815ef7719d13..000000000000 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ /dev/null @@ -1,394 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "marvell,kirkwood"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,feroceon"; - reg = <0>; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; - }; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - i2c0 = &i2c0; - }; - - mbus@f1000000 { - compatible = "marvell,kirkwood-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - /* If a board file needs to change this ranges it must replace it completely */ - ranges = ; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ - pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - - nand: nand@12f { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = ; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "disabled"; - }; - - crypto_sram: sa-sram@301 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gate_clk 17>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000>; - #address-cells = <1>; - #size-cells = <1>; - - pinctrl: pin-controller@10000 { - /* set compatible property in SoC file */ - reg = <0x10000 0x20>; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; - - /* - * Default SPI0 pinctrl setting with CSn on mpp0, - * overwrite marvell,pins on board level if required. - */ - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - - /* - * Default UART pinctrl setting without RTS/CTS, - * overwrite marvell,pins on board level if required. - */ - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,kirkwood-core-clock"; - reg = <0x10030 0x4>; - #clock-cells = <1>; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <35>, <36>, <37>, <38>; - clocks = <&gate_clk 7>; - }; - - gpio1: gpio@10140 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10140 0x40>; - ngpios = <18>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <39>, <40>, <41>; - clocks = <&gate_clk 7>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - sysc: system-controller@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x120>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - - gate_clk: clock-gating-control@2011c { - compatible = "marvell,kirkwood-gating-clock"; - reg = <0x2011c 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; - - intc: interrupt-controller@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: watchdog-timer@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&gate_clk 7>; - status = "okay"; - }; - - cesa: crypto@30000 { - compatible = "marvell,kirkwood-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - clocks = <&gate_clk 17>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - usb0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - dma0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - clocks = <&gate_clk 8>; - - xor00 { - interrupts = <5>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <6>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - dma1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60B00 0x100>; - status = "okay"; - clocks = <&gate_clk 16>; - - xor00 { - interrupts = <7>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <8>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth0: ethernet-controller@72000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 0>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - eth0port: ethernet0-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <11>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - eth1: ethernet-controller@76000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76000 0x4000>; - clocks = <&gate_clk 19>; - marvell,tx-checksum-limit = <1600>; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; - status = "disabled"; - - eth1port: ethernet1-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <15>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - sata_phy0: sata-phy@82000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x82000 0x0334>; - clocks = <&gate_clk 14>; - clock-names = "sata"; - #phy-cells = <0>; - status = "okay"; - }; - - sata_phy1: sata-phy@84000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x84000 0x0334>; - clocks = <&gate_clk 15>; - clock-names = "sata"; - #phy-cells = <0>; - status = "okay"; - }; - - audio0: audio-controller@a0000 { - compatible = "marvell,kirkwood-audio"; - #sound-dai-cells = <0>; - reg = <0xa0000 0x2210>; - interrupts = <24>; - clocks = <&gate_clk 9>; - clock-names = "internal"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts deleted file mode 100644 index 0f555eb45bda..000000000000 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS - */ - -/dts-v1/; -#include "lan966x-kontron-kswitch-d10-mmt.dtsi" - -/ { - model = "Kontron KSwitch D10 MMT 6G-2GS"; - compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921", - "microchip,lan9668", "microchip,lan966"; - - aliases { - i2c0 = &i2c4; - i2c1 = &i2c1; - }; - - sfp0: sfp0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c4>; - los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <2500>; - tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>; - rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>; - }; - - sfp1: sfp1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <2500>; - tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>; - rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&flx1 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c1: i2c@600 { - pinctrl-0 = <&fc1_c_pins>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c4: i2c@600 { - pinctrl-0 = <&fc4_b_pins>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&gpio { - fc1_c_pins: fc1-c-i2c-pins { - /* SCL, SDA */ - pins = "GPIO_47", "GPIO_48"; - function = "fc1_c"; - }; - - fc4_b_pins: fc4-b-i2c-pins { - /* SCL, SDA */ - pins = "GPIO_57", "GPIO_58"; - function = "fc4_b"; - }; -}; - -&port2 { - phys = <&serdes 2 SERDES6G(0)>; - sfp = <&sfp0>; - managed = "in-band-status"; - phy-mode = "sgmii"; - status = "okay"; -}; - -&port3 { - phys = <&serdes 3 SERDES6G(1)>; - sfp = <&sfp1>; - managed = "in-band-status"; - phy-mode = "sgmii"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts deleted file mode 100644 index 5feef9a59a79..000000000000 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for the Kontron KSwitch D10 MMT 8G - */ - -/dts-v1/; -#include "lan966x-kontron-kswitch-d10-mmt.dtsi" - -/ { - model = "Kontron KSwitch D10 MMT 8G"; - compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921", - "microchip,lan9668", "microchip,lan966"; -}; - -&mdio0 { - phy2: ethernet-phy@3 { - reg = <3>; - }; - - phy3: ethernet-phy@4 { - reg = <4>; - }; -}; - -&port2 { - phys = <&serdes 2 SERDES6G(0)>; - phy-handle = <&phy2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&port3 { - phys = <&serdes 3 SERDES6G(1)>; - phy-handle = <&phy3>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi deleted file mode 100644 index 0097e72e3fb2..000000000000 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Common part of the device tree for the Kontron KSwitch D10 MMT - */ - -/dts-v1/; -#include "lan966x.dtsi" -#include "dt-bindings/phy/phy-lan966x-serdes.h" - -/ { - aliases { - serial0 = &usart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 56 GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "okay"; - - usart0: serial@200 { - pinctrl-0 = <&usart0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&flx3 { - atmel,flexcom-mode = ; - status = "okay"; - - spi3: spi@400 { - pinctrl-0 = <&fc3_b_pins>; - pinctrl-names = "default"; - status = "okay"; - cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - }; -}; - -&gpio { - fc3_b_pins: fc3-b-pins { - /* SCK, MISO, MOSI */ - pins = "GPIO_51", "GPIO_52", "GPIO_53"; - function = "fc3_b"; - }; - - miim_c_pins: miim-c-pins { - /* MDC, MDIO */ - pins = "GPIO_59", "GPIO_60"; - function = "miim_c"; - }; - - sgpio_a_pins: sgpio-a-pins { - /* SCK, D0, D1 */ - pins = "GPIO_32", "GPIO_33", "GPIO_34"; - function = "sgpio_a"; - }; - - sgpio_b_pins: sgpio-b-pins { - /* LD */ - pins = "GPIO_64"; - function = "sgpio_b"; - }; - - usart0_pins: usart0-pins { - /* RXD, TXD */ - pins = "GPIO_25", "GPIO_26"; - function = "fc0_b"; - }; - - usbs_a_pins: usbs-a-pins { - /* VBUS_DET */ - pins = "GPIO_66"; - function = "gpio"; - }; -}; - -&mdio0 { - pinctrl-0 = <&miim_c_pins>; - pinctrl-names = "default"; - reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - clock-frequency = <2500000>; - status = "okay"; - - phy4: ethernet-phy@5 { - reg = <5>; - coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; - }; - - phy5: ethernet-phy@6 { - reg = <6>; - coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; - }; - - phy6: ethernet-phy@7 { - reg = <7>; - coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; - }; - - phy7: ethernet-phy@8 { - reg = <8>; - coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; - }; -}; - -&mdio1 { - status = "okay"; -}; - -&phy0 { - status = "okay"; -}; - -&phy1 { - status = "okay"; -}; - -&port0 { - phys = <&serdes 0 CU(0)>; - phy-handle = <&phy0>; - phy-mode = "gmii"; - status = "okay"; -}; - -&port1 { - phys = <&serdes 1 CU(1)>; - phy-handle = <&phy1>; - phy-mode = "gmii"; - status = "okay"; -}; - -&port4 { - phys = <&serdes 4 SERDES6G(2)>; - phy-handle = <&phy4>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&port5 { - phys = <&serdes 5 SERDES6G(2)>; - phy-handle = <&phy5>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&port6 { - phys = <&serdes 6 SERDES6G(2)>; - phy-handle = <&phy6>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&port7 { - phys = <&serdes 7 SERDES6G(2)>; - phy-handle = <&phy7>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&serdes { - status = "okay"; -}; - -&sgpio { - pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>; - pinctrl-names = "default"; - bus-frequency = <8000000>; - /* arbitrary range because all GPIOs are in software mode */ - microchip,sgpio-port-ranges = <0 11>; - status = "okay"; - - sgpio_in: gpio@0 { - ngpios = <128>; - }; - - sgpio_out: gpio@1 { - ngpios = <128>; - }; -}; - -&switch { - status = "okay"; -}; - -&udc { - pinctrl-0 = <&usbs_a_pins>; - pinctrl-names = "default"; - atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/lan966x-pcb8290.dts deleted file mode 100644 index 8804e8ba5370..000000000000 --- a/arch/arm/boot/dts/lan966x-pcb8290.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board - * - * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries - * - * Author: Horatiu Vultur - */ -/dts-v1/; -#include "lan966x.dtsi" -#include "dt-bindings/phy/phy-lan966x-serdes.h" - -/ { - model = "Microchip EVB LAN9668"; - compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966"; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 56 GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -&aes { - status = "disabled"; /* Reserved by secure OS */ -}; - -&gpio { - miim_a_pins: mdio-pins { - /* MDC, MDIO */ - pins = "GPIO_28", "GPIO_29"; - function = "miim_a"; - }; - - pps_out_pins: pps-out-pins { - /* 1pps output */ - pins = "GPIO_38"; - function = "ptpsync_3"; - }; - - ptp_ext_pins: ptp-ext-pins { - /* 1pps input */ - pins = "GPIO_35"; - function = "ptpsync_0"; - }; - - udc_pins: ucd-pins { - /* VBUS_DET B */ - pins = "GPIO_8"; - function = "usb_slave_b"; - }; -}; - -&mdio0 { - pinctrl-0 = <&miim_a_pins>; - pinctrl-names = "default"; - status = "okay"; - - ext_phy0: ethernet-phy@7 { - reg = <7>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy1: ethernet-phy@8 { - reg = <8>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy2: ethernet-phy@9 { - reg = <9>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy3: ethernet-phy@10 { - reg = <10>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy4: ethernet-phy@15 { - reg = <15>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy5: ethernet-phy@16 { - reg = <16>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy6: ethernet-phy@17 { - reg = <17>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; - - ext_phy7: ethernet-phy@18 { - reg = <18>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio>; - coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; - }; -}; - -&port0 { - reg = <2>; - phy-handle = <&ext_phy2>; - phy-mode = "qsgmii"; - phys = <&serdes 0 SERDES6G(1)>; - status = "okay"; -}; - -&port1 { - reg = <3>; - phy-handle = <&ext_phy3>; - phy-mode = "qsgmii"; - phys = <&serdes 1 SERDES6G(1)>; - status = "okay"; -}; - -&port2 { - reg = <0>; - phy-handle = <&ext_phy0>; - phy-mode = "qsgmii"; - phys = <&serdes 2 SERDES6G(1)>; - status = "okay"; -}; - -&port3 { - reg = <1>; - phy-handle = <&ext_phy1>; - phy-mode = "qsgmii"; - phys = <&serdes 3 SERDES6G(1)>; - status = "okay"; -}; - -&port4 { - reg = <6>; - phy-handle = <&ext_phy6>; - phy-mode = "qsgmii"; - phys = <&serdes 4 SERDES6G(2)>; - status = "okay"; -}; - -&port5 { - reg = <7>; - phy-handle = <&ext_phy7>; - phy-mode = "qsgmii"; - phys = <&serdes 5 SERDES6G(2)>; - status = "okay"; -}; - -&port6 { - reg = <4>; - phy-handle = <&ext_phy4>; - phy-mode = "qsgmii"; - phys = <&serdes 6 SERDES6G(2)>; - status = "okay"; -}; - -&port7 { - reg = <5>; - phy-handle = <&ext_phy5>; - phy-mode = "qsgmii"; - phys = <&serdes 7 SERDES6G(2)>; - status = "okay"; -}; - -&serdes { - status = "okay"; -}; - -&switch { - pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&udc { - pinctrl-0 = <&udc_pins>; - pinctrl-names = "default"; - atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts deleted file mode 100644 index 3a3d76af8612..000000000000 --- a/arch/arm/boot/dts/lan966x-pcb8291.dts +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * lan966x_pcb8291.dts - Device Tree file for PCB8291 - */ -/dts-v1/; -#include "lan966x.dtsi" -#include "dt-bindings/phy/phy-lan966x-serdes.h" - -/ { - model = "Microchip EVB - LAN9662"; - compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &usart3; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 56 GPIO_ACTIVE_LOW>; - priority = <200>; - }; - - leds { - compatible = "gpio-leds"; - - led-s0-blue { - label = "s0:blue"; - gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-s0-green { - label = "s0:green"; - gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-s1-blue { - label = "s1:blue"; - gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-s1-green { - label = "s1:green"; - gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&aes { - status = "disabled"; /* Reserved by secure OS */ -}; - -&gpio { - fc3_b_pins: fc3-b-pins { - /* RX, TX */ - pins = "GPIO_52", "GPIO_53"; - function = "fc3_b"; - }; - - can0_b_pins: can0-b-pins { - /* RX, TX */ - pins = "GPIO_35", "GPIO_36"; - function = "can0_b"; - }; - - sgpio_a_pins: sgpio-a-pins { - /* SCK, D0, D1, LD */ - pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; - function = "sgpio_a"; - }; -}; - -&can0 { - pinctrl-0 = <&can0_b_pins>; - pinctrl-names = "default"; - status = "disabled"; /* Conflict with switch */ -}; - -&flx3 { - atmel,flexcom-mode = ; - status = "okay"; - - usart3: serial@200 { - pinctrl-0 = <&fc3_b_pins>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&mdio1 { - status = "okay"; -}; - -&phy0 { - status = "okay"; -}; - -&phy1 { - status = "okay"; -}; - -&port0 { - phy-handle = <&phy0>; - phy-mode = "gmii"; - phys = <&serdes 0 CU(0)>; - status = "okay"; -}; - -&port1 { - phy-handle = <&phy1>; - phy-mode = "gmii"; - phys = <&serdes 1 CU(1)>; - status = "okay"; -}; - -&serdes { - status = "okay"; -}; - -&sgpio { - pinctrl-0 = <&sgpio_a_pins>; - pinctrl-names = "default"; - microchip,sgpio-port-ranges = <0 3>, <8 11>; - status = "okay"; - - gpio@0 { - ngpios = <64>; - }; - gpio@1 { - ngpios = <64>; - }; -}; - -&switch { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/lan966x-pcb8309.dts deleted file mode 100644 index 0cb505f79ba1..000000000000 --- a/arch/arm/boot/dts/lan966x-pcb8309.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * lan966x_pcb8309.dts - Device Tree file for PCB8309 - */ -/dts-v1/; -#include "lan966x.dtsi" -#include "dt-bindings/phy/phy-lan966x-serdes.h" - -/ { - model = "Microchip EVB - LAN9662"; - compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966"; - - aliases { - serial0 = &usart3; - i2c102 = &i2c102; - i2c103 = &i2c103; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 56 GPIO_ACTIVE_LOW>; - priority = <200>; - }; - - i2c-mux { - compatible = "i2c-mux"; - #address-cells = <1>; - #size-cells = <0>; - mux-controls = <&mux>; - i2c-parent = <&i2c4>; - - i2c102: i2c-sfp@1 { - reg = <1>; - }; - - i2c103: i2c-sfp@2 { - reg = <2>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-s0-green { - label = "s0:green"; - gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-s0-red { - label = "s0:red"; - gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-s1-green { - label = "s1:green"; - gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-s1-red { - label = "s1:red"; - gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */ - <&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */ - }; - - sfp2: sfp2 { - compatible = "sff,sfp"; - i2c-bus = <&i2c102>; - tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; - }; - - sfp3: sfp3 { - compatible = "sff,sfp"; - i2c-bus = <&i2c103>; - tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>; - }; -}; - -&aes { - status = "disabled"; /* Reserved by secure OS */ -}; - -&flx3 { - atmel,flexcom-mode = ; - status = "okay"; - - usart3: serial@200 { - pinctrl-0 = <&fc3_b_pins>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c4: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - clocks = <&nic_clk>; - pinctrl-0 = <&fc4_b_pins>; - pinctrl-names = "default"; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - i2c-sda-hold-time-ns = <1500>; - status = "okay"; - }; -}; - -&gpio { - fc3_b_pins: fc3-b-pins { - /* RXD, TXD */ - pins = "GPIO_52", "GPIO_53"; - function = "fc3_b"; - }; - - fc4_b_pins: fc4-b-pins { - /* SCL, SDA */ - pins = "GPIO_57", "GPIO_58"; - function = "fc4_b"; - }; - - pps_out_pins: pps-out-pins { - /* 1pps output */ - pins = "GPIO_38"; - function = "ptpsync_3"; - }; - - ptp_ext_pins: ptp-ext-pins { - /* 1pps input */ - pins = "GPIO_39"; - function = "ptpsync_4"; - }; - - sgpio_a_pins: sgpio-a-pins { - /* SCK, D0, D1, LD */ - pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; - function = "sgpio_a"; - }; -}; - -&mdio1 { - status = "okay"; -}; - -&phy0 { - status = "okay"; -}; - -&phy1 { - status = "okay"; -}; - -&port0 { - phy-handle = <&phy0>; - phy-mode = "gmii"; - phys = <&serdes 0 CU(0)>; - status = "okay"; -}; - -&port1 { - phy-handle = <&phy1>; - phy-mode = "gmii"; - phys = <&serdes 1 CU(1)>; - status = "okay"; -}; - -&port2 { - sfp = <&sfp2>; - managed = "in-band-status"; - phy-mode = "sgmii"; - phys = <&serdes 2 SERDES6G(0)>; - status = "okay"; -}; - -&port3 { - sfp = <&sfp3>; - managed = "in-band-status"; - phy-mode = "sgmii"; - phys = <&serdes 3 SERDES6G(1)>; - status = "okay"; -}; - -&serdes { - status = "okay"; -}; - -&sgpio { - pinctrl-0 = <&sgpio_a_pins>; - pinctrl-names = "default"; - microchip,sgpio-port-ranges = <0 3>, <8 11>; - status = "okay"; - - gpio@0 { - ngpios = <64>; - }; - gpio@1 { - ngpios = <64>; - }; -}; - -&switch { - pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi deleted file mode 100644 index 05b73f7cf0c7..000000000000 --- a/arch/arm/boot/dts/lan966x.dtsi +++ /dev/null @@ -1,615 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC - * - * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries - * - * Author: Kavyasree Kotagiri - * - */ - -#include -#include -#include -#include -#include -#include - -/ { - model = "Microchip LAN966 family SoC"; - compatible = "microchip,lan966"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - clock-frequency = <600000000>; - reg = <0x0>; - }; - }; - - clocks { - sys_clk: sys_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <165625000>; - }; - - cpu_clk: cpu_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - }; - - ddr_clk: ddr_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; - - nic_clk: nic_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - clks: clock-controller@e00c00a8 { - compatible = "microchip,lan966x-gck"; - #clock-cells = <1>; - clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; - clock-names = "cpu", "ddr", "sys"; - reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <37500000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - udc: usb@200000 { - compatible = "microchip,lan9662-udc", - "atmel,sama5d3-udc"; - reg = <0x00200000 0x80000>, - <0xe0808000 0x400>; - interrupts = ; - clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - switch: switch@e0000000 { - compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, - <0xe2000000 0x0800000>; - reg-names = "cpu", "gcb"; - interrupts = , - , - , - , - ; - interrupt-names = "xtr", "fdma", "ana", "ptp", - "ptp-ext"; - resets = <&reset 0>; - reset-names = "switch"; - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - port0: port@0 { - reg = <0>; - status = "disabled"; - }; - - port1: port@1 { - reg = <1>; - status = "disabled"; - }; - - port2: port@2 { - reg = <2>; - status = "disabled"; - }; - - port3: port@3 { - reg = <3>; - status = "disabled"; - }; - - port4: port@4 { - reg = <4>; - status = "disabled"; - }; - - port5: port@5 { - reg = <5>; - status = "disabled"; - }; - - port6: port@6 { - reg = <6>; - status = "disabled"; - }; - - port7: port@7 { - reg = <7>; - status = "disabled"; - }; - }; - }; - - otp: otp@e0021000 { - compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc"; - reg = <0xe0021000 0x300>; - }; - - flx0: flexcom@e0040000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe0040000 0x100>; - clocks = <&clks GCK_ID_FLEXCOM0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0040000 0x800>; - status = "disabled"; - - usart0: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, - <&dma0 AT91_XDMAC_DT_PERID(2)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "usart"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi0: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, - <&dma0 AT91_XDMAC_DT_PERID(2)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, - <&dma0 AT91_XDMAC_DT_PERID(2)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - flx1: flexcom@e0044000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe0044000 0x100>; - clocks = <&clks GCK_ID_FLEXCOM1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0044000 0x800>; - status = "disabled"; - - usart1: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, - <&dma0 AT91_XDMAC_DT_PERID(4)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "usart"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi1: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, - <&dma0 AT91_XDMAC_DT_PERID(4)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, - <&dma0 AT91_XDMAC_DT_PERID(4)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - trng: rng@e0048000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xe0048000 0x100>; - clocks = <&nic_clk>; - }; - - aes: crypto@e004c000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xe004c000 0x100>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, - <&dma0 AT91_XDMAC_DT_PERID(13)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "aes_clk"; - }; - - flx2: flexcom@e0060000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe0060000 0x100>; - clocks = <&clks GCK_ID_FLEXCOM2>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0060000 0x800>; - status = "disabled"; - - usart2: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(6)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "usart"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi2: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(6)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(6)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - flx3: flexcom@e0064000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe0064000 0x100>; - clocks = <&clks GCK_ID_FLEXCOM3>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0064000 0x800>; - status = "disabled"; - - usart3: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "usart"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi3: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - dma0: dma-controller@e0068000 { - compatible = "microchip,sama7g5-dma"; - reg = <0xe0068000 0x1000>; - interrupts = ; - #dma-cells = <1>; - clocks = <&nic_clk>; - clock-names = "dma_clk"; - }; - - sha: crypto@e006c000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xe006c000 0xec>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; - dma-names = "tx"; - clocks = <&nic_clk>; - clock-names = "sha_clk"; - }; - - flx4: flexcom@e0070000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe0070000 0x100>; - clocks = <&clks GCK_ID_FLEXCOM4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0070000 0x800>; - status = "disabled"; - - usart4: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, - <&dma0 AT91_XDMAC_DT_PERID(10)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "usart"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi4: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, - <&dma0 AT91_XDMAC_DT_PERID(10)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, - <&dma0 AT91_XDMAC_DT_PERID(10)>; - dma-names = "tx", "rx"; - clocks = <&nic_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - timer0: timer@e008c000 { - compatible = "snps,dw-apb-timer"; - reg = <0xe008c000 0x400>; - clocks = <&nic_clk>; - clock-names = "timer"; - interrupts = ; - }; - - watchdog: watchdog@e0090000 { - compatible = "snps,dw-wdt"; - reg = <0xe0090000 0x1000>; - interrupts = ; - clocks = <&nic_clk>; - status = "disabled"; - }; - - cpu_ctrl: syscon@e00c0000 { - compatible = "microchip,lan966x-cpu-syscon", "syscon"; - reg = <0xe00c0000 0x350>; - }; - - can0: can@e081c000 { - compatible = "bosch,m_can"; - reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&clks GCK_ID_MCAN0>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - can1: can@e0820000 { - compatible = "bosch,m_can"; - reg = <0xe0820000 0xfc>, <0x00100000 0x8000>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&clks GCK_ID_MCAN1>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - reset: reset-controller@e200400c { - compatible = "microchip,lan966x-switch-reset"; - reg = <0xe200400c 0x4>; - reg-names = "gcb"; - #reset-cells = <1>; - cpu-syscon = <&cpu_ctrl>; - }; - - gpio: pinctrl@e2004064 { - compatible = "microchip,lan966x-pinctrl"; - reg = <0xe2004064 0xb4>, - <0xe2010024 0x138>; - resets = <&reset 0>; - reset-names = "switch"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 78>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - }; - - mdio0: mdio@e2004118 { - compatible = "microchip,lan966x-miim"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xe2004118 0x24>; - clocks = <&sys_clk>; - status = "disabled"; - }; - - mdio1: mdio@e200413c { - compatible = "microchip,lan966x-miim"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xe200413c 0x24>, - <0xe2010020 0x4>; - clocks = <&sys_clk>; - status = "disabled"; - - phy0: ethernet-phy@1 { - reg = <1>; - interrupts = ; - status = "disabled"; - }; - - phy1: ethernet-phy@2 { - reg = <2>; - interrupts = ; - status = "disabled"; - }; - }; - - sgpio: gpio@e2004190 { - compatible = "microchip,sparx5-sgpio"; - reg = <0xe2004190 0x118>; - clocks = <&sys_clk>; - resets = <&reset 0>; - reset-names = "switch"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sgpio_in: gpio@0 { - compatible = "microchip,sparx5-sgpio-bank"; - reg = <0>; - gpio-controller; - #gpio-cells = <3>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - sgpio_out: gpio@1 { - compatible = "microchip,sparx5-sgpio-bank"; - reg = <1>; - gpio-controller; - #gpio-cells = <3>; - }; - }; - - hwmon: hwmon@e2010180 { - compatible = "microchip,lan9668-hwmon"; - reg = <0xe2010180 0xc>, - <0xe20042a8 0xc>; - reg-names = "pvt", "fan"; - clocks = <&sys_clk>; - }; - - serdes: serdes@e202c000 { - compatible = "microchip,lan966x-serdes"; - reg = <0xe202c000 0x9c>, - <0xe2004010 0x4>; - #phy-cells = <2>; - status = "disabled"; - }; - - gic: interrupt-controller@e8c11000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupts = ; - interrupt-controller; - reg = <0xe8c11000 0x1000>, - <0xe8c12000 0x2000>, - <0xe8c14000 0x2000>, - <0xe8c16000 0x2000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts deleted file mode 100644 index c1705f6f3d10..000000000000 --- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "logicpd-som-lv-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts deleted file mode 100644 index 9dbbcc7ced7c..000000000000 --- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "logicpd-som-lv-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi deleted file mode 100644 index 690f2ad50c65..000000000000 --- a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - sysboot2 { - label = "gpio3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &led_pins_wkup>; - - led1 { - label = "led1"; - gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ - linux,default-trigger = "none"; - }; - }; -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ - 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lcd0: display { - /* This isn't the exact LCD, but the timings meet spec */ - compatible = "logicpd,type28"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_pin>; - backlight = <&bl>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&twl_pwm 0 5000000>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: gpio-key-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ - >; - }; - - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ - >; - }; - - lan9221_pins: lan9221-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ - >; - }; - - lcd_enable_pin: lcd-enable-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: dss-dpi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; -}; - -&omap3_pmx_wkup { - led_pins_wkup: led-wkup-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; -}; - - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi deleted file mode 100644 index c0e6b73fa472..000000000000 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ /dev/null @@ -1,296 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 3 0>; /* gpio_3 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vaux3>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb2_phy: hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ - #phy-cells = <0>; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - clocks = <&hfclk_26m>; - clock-names = "fck"; - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; - pinctrl-0 = <&mmc3_pins &wl127x_gpio>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1273"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ - ref-clock-frequency = <26000000>; - }; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&omap3_pmx_core { - - mmc3_pins: mm3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ - >; - }; - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - hsusb_otg_pins: hsusb-otg-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - tsc2004_pins: tsc2004-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; -}; - -&omap3_pmx_wkup { - - hsusb2_reset_pin: hsusb1-reset-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - wl127x_gpio: wl127x-gpio-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts deleted file mode 100644 index eaa583fdc3d6..000000000000 --- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "logicpd-torpedo-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core { - isp1763_pins: isp1763-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts deleted file mode 100644 index b5536132971f..000000000000 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -/* - * There are two types of 4.3" LCD, Type 15 and Type 28. - * By default, type 15 was used. This device tree file - * uses the timing for the type 28 LCD - */ - -#include "logicpd-torpedo-37xx-devkit.dts" - -&lcd0 { - compatible = "logicpd,type28"; -}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts deleted file mode 100644 index 533ce7ce387a..000000000000 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "omap-gpmc-smsc9221.dtsi" -#include "logicpd-torpedo-baseboard.dtsi" - -/ { - model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 29 0>; /* gpio157 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -/* - * Only found on the wireless SOM. For the SOM without wireless, the pins for - * MMC3 can be routed with jumpers to the second MMC slot on the devkit and - * gpio157 is not connected. So this should be OK to keep common for now, - * probably device tree overlays is the way to go with the various SOM and - * jumpering combinations for the long run. - */ -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; - pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1283"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&uart2 { - /delete-property/dma-names; - bluetooth { - compatible = "ti,wl1283-st"; - enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */ - max-speed = <3000000>; - }; -}; - -/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */ -&mt9p031_out { - pixel-clock-frequency = <90000000>; -}; - -&omap3_pmx_core { - mmc3_pins: mm3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_core2_pins: mmc3-core2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - >; - }; -}; - -/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ -&omap3_pmx_wkup { - isp1763_pins: isp1763-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi deleted file mode 100644 index e0caed539810..000000000000 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ /dev/null @@ -1,420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; - - sysboot2 { - label = "sysboot2"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ - linux,code = ; - wakeup-source; - }; - - sysboot5 { - label = "sysboot5"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ - linux,code = ; - wakeup-source; - }; - - gpio1 { - label = "gpio1"; - gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ - linux,code = ; - wakeup-source; - }; - - gpio2 { - label = "gpio2"; - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "led1"; - gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ - linux,default-trigger = "none"; - }; - }; - - pwm10: pwm-10 { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer10>; - #pwm-cells = <3>; - ti,clock-source = <0x01>; - }; - -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ - 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ - reg = <1 0 0xff>; - }; - - usb@6,0 { - pinctrl-names = "default"; - pinctrl-0 = <&isp1763_pins>; - compatible = "nxp,usb-isp1763"; - reg = <0x6 0x0 0xff>; - interrupt-parent = <&gpio5>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host"; - bus-width = <16>; - dr_mode = "host"; - gpmc,mux-add-data = <0>; - gpmc,device-width = <2>; - gpmc,wait-pin = <0>; - gpmc,burst-length = <4>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <45>; - gpmc,cs-wr-off-ns = <45>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <0>; - gpmc,adv-wr-off-ns = <0>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <45>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <25>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <45>; - gpmc,access-ns = <35>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <60>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <5>; - gpmc,wr-access-ns = <20>; - }; -}; - -&hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&vpll2>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - /* This isn't the exact LCD, but the timings meet spec */ - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - label = "15"; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pwr_pins>; - backlight = <&bl>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm10 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd>; - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: gpio-key-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ - >; - }; - - hdq_pins: hdq-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ - >; - }; - - pwm_pins: pwm-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ - >; - }; - - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - tsc2004_pins: tsc2004-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ - >; - }; - - isp_pins: isp-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ - - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ - >; - }; - - panel_pwr_pins: panel-pwr-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: dss-dpi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_wkup { - gpio_key_pins_wkup: gpio-key-wkup-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; - - lan9221_pins: lan9221-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - mmc1_cd: mmc1-cd-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ - >; - }; -}; - -&i2c2 { - mt9p031@48 { - compatible = "aptina,mt9p031"; - reg = <0x48>; - clocks = <&isp 0>; - vaa-supply = <&vaux4>; - vdd-supply = <&vaux4>; - vdd_io-supply = <&vaux4>; - port { - mt9p031_out: endpoint { - input-clock-frequency = <24000000>; - pixel-clock-frequency = <72000000>; - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; - -&i2c3 { - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mcspi1 { - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; -}; - -&isp { - pinctrl-names = "default"; - pinctrl-0 = <&isp_pins>; - ports { - port@0 { - reg = <0>; - ccdc_ep: endpoint { - remote-endpoint = <&mt9p031_out>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi deleted file mode 100644 index 227699890890..000000000000 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - leds { - compatible = "gpio-leds"; - led-user0 { - label = "user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - linux,default-trigger = "none"; - }; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; -}; - -/* The Torpedo doesn't route the USB host pins */ -&usbhshost { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - at24@50 { - compatible = "atmel,24c64"; - readonly; - reg = <0x50>; - }; -}; - -&omap3_pmx_core { - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - hsusb_otg_pins: hsusb-otg-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi deleted file mode 100644 index 1bb686a7b3ec..000000000000 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Common base for NXP LPC18xx and LPC43xx devices. - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#include "armv7-m.dtsi" - -#include "dt-bindings/clock/lpc18xx-cgu.h" -#include "dt-bindings/clock/lpc18xx-ccu.h" - -#define LPC_PIN(port, pin) (0x##port * 32 + pin) -#define LPC_GPIO(port, pin) (port * 32 + pin) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-m3"; - device_type = "cpu"; - reg = <0x0>; - clocks = <&ccu1 CLK_CPU_CORE>; - }; - }; - - clocks { - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - xtal32: xtal32 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - enet_rx_clk: enet_rx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_rx_clk"; - }; - - enet_tx_clk: enet_tx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_tx_clk"; - }; - - gp_clkin: gp_clkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "gp_clkin"; - }; - }; - - soc { - sct_pwm: pwm@40000000 { - compatible = "nxp,lpc1850-sct-pwm"; - reg = <0x40000000 0x1000>; - clocks =<&ccu1 CLK_CPU_SCT>; - clock-names = "pwm"; - resets = <&rgu 37>; - #pwm-cells = <3>; - status = "disabled"; - }; - - dmac: dma-controller@40002000 { - compatible = "arm,pl080", "arm,primecell"; - arm,primecell-periphid = <0x00041080>; - reg = <0x40002000 0x1000>; - interrupts = <2>; - clocks = <&ccu1 CLK_CPU_DMA>; - clock-names = "apb_pclk"; - resets = <&rgu 19>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <16>; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb1; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - }; - - spifi: flash-controller@40003000 { - compatible = "nxp,lpc1773-spifi"; - reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; - reg-names = "spifi", "flash"; - interrupts = <30>; - clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; - clock-names = "spifi", "reg"; - resets = <&rgu 53>; - status = "disabled"; - }; - - mmcsd: mmcsd@40004000 { - compatible = "snps,dw-mshc"; - reg = <0x40004000 0x1000>; - interrupts = <6>; - clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; - clock-names = "ciu", "biu"; - resets = <&rgu 20>; - status = "disabled"; - }; - - usb0: usb@40006100 { - compatible = "nxp,lpc1850-ehci", "generic-ehci"; - reg = <0x40006100 0x100>; - interrupts = <8>; - clocks = <&ccu1 CLK_CPU_USB0>; - resets = <&rgu 17>; - phys = <&usb0_otg_phy>; - phy-names = "usb"; - has-transaction-translator; - status = "disabled"; - }; - - usb1: usb@40007100 { - compatible = "nxp,lpc1850-ehci", "generic-ehci"; - reg = <0x40007100 0x100>; - interrupts = <9>; - clocks = <&ccu1 CLK_CPU_USB1>; - resets = <&rgu 18>; - status = "disabled"; - }; - - emc: memory-controller@40005000 { - compatible = "arm,pl172", "arm,primecell"; - reg = <0x40005000 0x1000>; - clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; - clock-names = "mpmcclk", "apb_pclk"; - resets = <&rgu 21>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x1c000000 0x1000000 - 1 0 0x1d000000 0x1000000 - 2 0 0x1e000000 0x1000000 - 3 0 0x1f000000 0x1000000>; - status = "disabled"; - }; - - lcdc: lcd-controller@40008000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x40008000 0x1000>; - interrupts = <7>; - interrupt-names = "combined"; - clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; - clock-names = "clcdclk", "apb_pclk"; - resets = <&rgu 16>; - status = "disabled"; - }; - - eeprom: eeprom@4000e000 { - compatible = "nxp,lpc1857-eeprom"; - reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; - reg-names = "reg", "mem"; - clocks = <&ccu1 CLK_CPU_EEPROM>; - clock-names = "eeprom"; - resets = <&rgu 27>; - interrupts = <4>; - status = "disabled"; - }; - - mac: ethernet@40010000 { - compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; - reg = <0x40010000 0x2000>; - interrupts = <5>; - interrupt-names = "macirq"; - clocks = <&ccu1 CLK_CPU_ETHERNET>; - clock-names = "stmmaceth"; - resets = <&rgu 22>; - reset-names = "stmmaceth"; - rx-fifo-depth = <256>; - tx-fifo-depth = <256>; - snps,pbl = <4>; /* 32 (8x mode) */ - snps,force_thresh_dma_mode; - status = "disabled"; - }; - - creg: syscon@40043000 { - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; - reg = <0x40043000 0x1000>; - clocks = <&ccu1 CLK_CPU_CREG>; - resets = <&rgu 5>; - - creg_clk: clock-controller { - compatible = "nxp,lpc1850-creg-clk"; - clocks = <&xtal32>; - #clock-cells = <1>; - }; - - usb0_otg_phy: phy { - compatible = "nxp,lpc1850-usb-otg-phy"; - clocks = <&ccu1 CLK_USB0>; - #phy-cells = <0>; - }; - - dmamux: dma-mux { - compatible = "nxp,lpc1850-dmamux"; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&dmac>; - }; - }; - - rtc: rtc@40046000 { - compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; - reg = <0x40046000 0x1000>; - interrupts = <47>; - clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; - clock-names = "rtc", "reg"; - }; - - cgu: clock-controller@40050000 { - compatible = "nxp,lpc1850-cgu"; - reg = <0x40050000 0x1000>; - #clock-cells = <1>; - clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; - }; - - ccu1: clock-controller@40051000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40051000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, - <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, - <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, - <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; - clock-names = "base_apb3_clk", "base_apb1_clk", - "base_spifi_clk", "base_cpu_clk", - "base_periph_clk", "base_usb0_clk", - "base_usb1_clk", "base_spi_clk"; - }; - - ccu2: clock-controller@40052000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40052000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, - <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, - <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, - <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; - clock-names = "base_audio_clk", "base_uart3_clk", - "base_uart2_clk", "base_uart1_clk", - "base_uart0_clk", "base_ssp1_clk", - "base_ssp0_clk", "base_sdio_clk"; - }; - - rgu: reset-controller@40053000 { - compatible = "nxp,lpc1850-rgu"; - reg = <0x40053000 0x1000>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; - clock-names = "delay", "reg"; - #reset-cells = <1>; - }; - - watchdog@40080000 { - compatible = "nxp,lpc1850-wwdt"; - reg = <0x40080000 0x24>; - interrupts = <49>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; - clock-names = "wdtclk", "reg"; - }; - - uart0: serial@40081000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40081000 0x1000>; - reg-shift = <2>; - interrupts = <24>; - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; - clock-names = "uartclk", "reg"; - resets = <&rgu 44>; - dmas = <&dmamux 1 1 2 - &dmamux 2 1 2 - &dmamux 11 2 2 - &dmamux 12 2 2>; - dma-names = "tx", "rx", "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@40082000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40082000 0x1000>; - reg-shift = <2>; - interrupts = <25>; - clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; - clock-names = "uartclk", "reg"; - resets = <&rgu 45>; - dmas = <&dmamux 3 1 2 - &dmamux 4 1 2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - ssp0: spi@40083000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x40083000 0x1000>; - interrupts = <22>; - clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; - clock-names = "sspclk", "apb_pclk"; - resets = <&rgu 50>; - dmas = <&dmamux 9 0 2 - &dmamux 10 0 2>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@40084000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40084000 0x1000>; - interrupts = <12>; - clocks = <&ccu1 CLK_CPU_TIMER0>; - clock-names = "timerclk"; - resets = <&rgu 32>; - }; - - timer1: timer@40085000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40085000 0x1000>; - interrupts = <13>; - clocks = <&ccu1 CLK_CPU_TIMER1>; - clock-names = "timerclk"; - resets = <&rgu 33>; - }; - - pinctrl: pinctrl@40086000 { - compatible = "nxp,lpc1850-scu"; - reg = <0x40086000 0x1000>; - clocks = <&ccu1 CLK_CPU_SCU>; - }; - - i2c0: i2c@400a1000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400a1000 0x1000>; - interrupts = <18>; - clocks = <&ccu1 CLK_APB1_I2C0>; - resets = <&rgu 48>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@400a4000 { - compatible = "bosch,c_can"; - reg = <0x400a4000 0x1000>; - interrupts = <43>; - clocks = <&ccu1 CLK_APB1_CAN1>; - resets = <&rgu 54>; - status = "disabled"; - }; - - uart2: serial@400c1000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x400c1000 0x1000>; - reg-shift = <2>; - interrupts = <26>; - clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; - clock-names = "uartclk", "reg"; - resets = <&rgu 46>; - dmas = <&dmamux 5 1 2 - &dmamux 6 1 2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@400c2000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x400c2000 0x1000>; - reg-shift = <2>; - interrupts = <27>; - clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; - clock-names = "uartclk", "reg"; - resets = <&rgu 47>; - dmas = <&dmamux 7 1 2 - &dmamux 8 1 2 - &dmamux 13 3 2 - &dmamux 14 3 2>; - dma-names = "tx", "rx", "rx", "tx"; - status = "disabled"; - }; - - timer2: timer@400c3000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x400c3000 0x1000>; - interrupts = <14>; - clocks = <&ccu1 CLK_CPU_TIMER2>; - clock-names = "timerclk"; - resets = <&rgu 34>; - }; - - timer3: timer@400c4000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x400c4000 0x1000>; - interrupts = <15>; - clocks = <&ccu1 CLK_CPU_TIMER3>; - clock-names = "timerclk"; - resets = <&rgu 35>; - }; - - ssp1: spi@400c5000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x400c5000 0x1000>; - interrupts = <23>; - clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; - clock-names = "sspclk", "apb_pclk"; - resets = <&rgu 51>; - dmas = <&dmamux 11 2 2 - &dmamux 12 2 2 - &dmamux 3 3 2 - &dmamux 4 3 2 - &dmamux 5 2 2 - &dmamux 6 2 2 - &dmamux 13 2 2 - &dmamux 14 2 2>; - dma-names = "rx", "tx", "tx", "rx", - "tx", "rx", "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@400e0000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400e0000 0x1000>; - interrupts = <19>; - clocks = <&ccu1 CLK_APB3_I2C1>; - resets = <&rgu 49>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dac: dac@400e1000 { - compatible = "nxp,lpc1850-dac"; - reg = <0x400e1000 0x1000>; - interrupts = <0>; - clocks = <&ccu1 CLK_APB3_DAC>; - resets = <&rgu 42>; - status = "disabled"; - }; - - can0: can@400e2000 { - compatible = "bosch,c_can"; - reg = <0x400e2000 0x1000>; - interrupts = <51>; - clocks = <&ccu1 CLK_APB3_CAN0>; - resets = <&rgu 55>; - status = "disabled"; - }; - - adc0: adc@400e3000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e3000 0x1000>; - interrupts = <17>; - clocks = <&ccu1 CLK_APB3_ADC0>; - resets = <&rgu 40>; - status = "disabled"; - }; - - adc1: adc@400e4000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e4000 0x1000>; - interrupts = <21>; - clocks = <&ccu1 CLK_APB3_ADC1>; - resets = <&rgu 41>; - status = "disabled"; - }; - - gpio: gpio@400f4000 { - compatible = "nxp,lpc1850-gpio"; - reg = <0x400f4000 0x4000>; - clocks = <&ccu1 CLK_CPU_GPIO>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, - <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, - <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, - <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, - <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, - <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, - <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, - <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, - <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, - <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, - <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, - <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, - <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, - <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, - <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, - <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, - <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, - <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, - <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, - <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, - <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, - <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, - <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, - <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, - <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, - <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, - <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, - <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, - <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, - <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, - <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, - <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, - <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, - <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, - <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, - <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, - <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, - <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, - <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, - <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; - }; - }; -}; diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts deleted file mode 100644 index 63c6f17bb7c9..000000000000 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Embedded Artists LPC3250 board - * - * Copyright 2012 Roland Stigge - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "Embedded Artists LPC3250 board based on NXP LPC3250"; - compatible = "ea,ea3250", "nxp,lpc3250"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - button { - label = "Interrupt Key"; - linux,code = <103>; - gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ - }; - - key1 { - label = "KEY1"; - linux,code = <1>; - gpios = <&pca9532 0 0>; - }; - - key2 { - label = "KEY2"; - linux,code = <2>; - gpios = <&pca9532 1 0>; - }; - - key3 { - label = "KEY3"; - linux,code = <3>; - gpios = <&pca9532 2 0>; - }; - - key4 { - label = "KEY4"; - linux,code = <4>; - gpios = <&pca9532 3 0>; - }; - - joy0 { - label = "Joystick Key 0"; - linux,code = <10>; - gpios = <&gpio 2 0 0>; /* P2.0 */ - }; - - joy1 { - label = "Joystick Key 1"; - linux,code = <11>; - gpios = <&gpio 2 1 0>; /* P2.1 */ - }; - - joy2 { - label = "Joystick Key 2"; - linux,code = <12>; - gpios = <&gpio 2 2 0>; /* P2.2 */ - }; - - joy3 { - label = "Joystick Key 3"; - linux,code = <13>; - gpios = <&gpio 2 3 0>; /* P2.3 */ - }; - - joy4 { - label = "Joystick Key 4"; - linux,code = <14>; - gpios = <&gpio 2 4 0>; /* P2.4 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - /* LEDs on OEM Board */ - - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ - linux,default-trigger = "timer"; - default-state = "off"; - }; - - led2 { - gpios = <&gpio 2 10 1>; /* P2.10, active low */ - default-state = "off"; - }; - - led3 { - gpios = <&gpio 2 11 1>; /* P2.11, active low */ - default-state = "off"; - }; - - led4 { - gpios = <&gpio 2 12 1>; /* P2.12, active low */ - default-state = "off"; - }; - - /* LEDs on Base Board */ - - lede1 { - gpios = <&pca9532 8 0>; - default-state = "off"; - }; - lede2 { - gpios = <&pca9532 9 0>; - default-state = "off"; - }; - lede3 { - gpios = <&pca9532 10 0>; - default-state = "off"; - }; - lede4 { - gpios = <&pca9532 11 0>; - default-state = "off"; - }; - lede5 { - gpios = <&pca9532 12 0>; - default-state = "off"; - }; - lede6 { - gpios = <&pca9532 13 0>; - default-state = "off"; - }; - lede7 { - gpios = <&pca9532 14 0>; - default-state = "off"; - }; - lede8 { - gpios = <&pca9532 15 0>; - default-state = "off"; - }; - }; -}; - -/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ -&adc { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 3 10 0>; - reset-gpio = <&gpio 3 2 0>; - dac-clk = "wspll"; - }; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; -}; - -&mac { - phy-mode = "rmii"; - use-iram; - status = "okay"; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&sd { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; -}; - -/* 128MB Flash via SLC NAND controller */ -&slc { - status = "okay"; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - mtd0@0 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@80000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&uart6 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts deleted file mode 100644 index 21a6d0bca1e8..000000000000 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * PHYTEC phyCORE-LPC3250 board - * - * Copyright (C) 2015-2019 Vladimir Zapolskiy - * Copyright 2012 Roland Stigge - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; - compatible = "phytec,phy3250", "nxp,lpc3250"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { /* red */ - gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ - default-state = "off"; - }; - - led1 { /* green */ - gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - compatible = "sharp,lq035q7db03"; - power-supply = <®_lcd>; - - port { - panel_input: endpoint { - remote-endpoint = <&cldc_output>; - }; - }; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "backlight"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 4 0>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 0 0>; - enable-active-high; - regulator-boot-on; - }; - - reg_sd: regulator-sd { - compatible = "regulator-fixed"; - regulator-name = "sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 5 5 0>; - enable-active-high; - regulator-boot-on; - }; -}; - -&clcd { - max-memory-bandwidth = <18710000>; - status = "okay"; - - port { - cldc_output: endpoint { - remote-endpoint = <&panel_input>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 3 10 0>; - reset-gpio = <&gpio 3 2 0>; - dac-clk = "wspll"; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; -}; - -&key { - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - status = "okay"; -}; - -&mac { - phy-mode = "rmii"; - use-iram; - status = "okay"; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&sd { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - vmmc-supply = <®_sd>; - status = "okay"; -}; - -/* 64MB Flash via SLC NAND controller */ -&slc { - status = "okay"; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - mtd0@0 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - mtd1@64000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; - - mtd2@1f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; - - mtd3@204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; - - mtd4@604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; - }; - }; -}; - -&ssp0 { - num-cs = <1>; - cs-gpios = <&gpio 3 5 0>; - status = "okay"; - - eeprom: at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - - pl022,interface = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - }; -}; - -&tsc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi deleted file mode 100644 index 974410918f35..000000000000 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ /dev/null @@ -1,508 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * NXP LPC32xx SoC - * - * Copyright (C) 2015-2019 Vladimir Zapolskiy - * Copyright 2012 Roland Stigge - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nxp,lpc3220"; - interrupt-parent = <&mic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - clocks { - xtal_32k: xtal_32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xtal_32k"; - }; - - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <13000000>; - clock-output-names = "xtal"; - }; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x00000000 0x00000000 0x10000000>, - <0x20000000 0x20000000 0x30000000>, - <0xe0000000 0xe0000000 0x04000000>; - - iram: sram@8000000 { - compatible = "mmio-sram"; - reg = <0x08000000 0x20000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x08000000 0x20000>; - }; - - /* - * Enable either SLC or MLC - */ - slc: flash@20020000 { - compatible = "nxp,lpc3220-slc"; - reg = <0x20020000 0x1000>; - clocks = <&clk LPC32XX_CLK_SLC>; - status = "disabled"; - }; - - mlc: flash@200a8000 { - compatible = "nxp,lpc3220-mlc"; - reg = <0x200a8000 0x11000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_MLC>; - status = "disabled"; - }; - - dma: dma@31000000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x31000000 0x1000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_DMA>; - clock-names = "apb_pclk"; - }; - - usb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; - - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: ohci@0 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_HOST>; - status = "disabled"; - }; - - usbd: usbd@0 { - compatible = "nxp,lpc3220-udc"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, - <30 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_LOW>; - clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; - status = "disabled"; - }; - - i2cusb: i2c@300 { - compatible = "nxp,pnx-i2c"; - reg = <0x300 0x100>; - interrupt-parent = <&sic1>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_I2C>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; - }; - - clcd: clcd@31040000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x31040000 0x1000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - mac: ethernet@31060000 { - compatible = "nxp,lpc-eth"; - reg = <0x31060000 0x1000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_MAC>; - status = "disabled"; - }; - - emc: memory-controller@31080000 { - compatible = "arm,pl175", "arm,primecell"; - reg = <0x31080000 0x1000>; - clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; - clock-names = "mpmcclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe0000000 0x01000000>, - <1 0xe1000000 0x01000000>, - <2 0xe2000000 0x01000000>, - <3 0xe3000000 0x01000000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; - - /* - * ssp0 and spi1 are shared pins; - * enable one in your board dts, as needed. - */ - ssp0: spi@20084000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x20084000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP0>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@20088000 { - compatible = "nxp,lpc3220-spi"; - reg = <0x20088000 0x1000>; - clocks = <&clk LPC32XX_CLK_SPI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* - * ssp1 and spi2 are shared pins; - * enable one in your board dts, as needed. - */ - ssp1: spi@2008c000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x2008c000 0x1000>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP1>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@20090000 { - compatible = "nxp,lpc3220-spi"; - reg = <0x20090000 0x1000>; - clocks = <&clk LPC32XX_CLK_SPI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2s0: i2s@20094000 { - compatible = "nxp,lpc3220-i2s"; - reg = <0x20094000 0x1000>; - status = "disabled"; - }; - - sd: sd@20098000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x20098000 0x1000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SD>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2s1: i2s@2009c000 { - compatible = "nxp,lpc3220-i2s"; - reg = <0x2009c000 0x1000>; - status = "disabled"; - }; - - /* UART5 first since it is the default console, ttyS0 */ - uart5: serial@40090000 { - /* actually, ns16550a w/ 64 byte fifos! */ - compatible = "nxp,lpc3220-uart"; - reg = <0x40090000 0x1000>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART5>; - status = "disabled"; - }; - - uart3: serial@40080000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40080000 0x1000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART3>; - status = "disabled"; - }; - - uart4: serial@40088000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40088000 0x1000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART4>; - status = "disabled"; - }; - - uart6: serial@40098000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40098000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART6>; - status = "disabled"; - }; - - i2c1: i2c@400a0000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400a0000 0x100>; - interrupt-parent = <&sic1>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk LPC32XX_CLK_I2C1>; - }; - - i2c2: i2c@400a8000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400a8000 0x100>; - interrupt-parent = <&sic1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk LPC32XX_CLK_I2C2>; - }; - - mpwm: mpwm@400e8000 { - compatible = "nxp,lpc3220-motor-pwm"; - reg = <0x400e8000 0x78>; - status = "disabled"; - #pwm-cells = <2>; - }; - }; - - fab { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; - - /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x40004000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - clk: clock-controller@0 { - compatible = "nxp,lpc3220-clk"; - reg = <0x00 0x114>; - #clock-cells = <1>; - - clocks = <&xtal_32k>, <&xtal>; - clock-names = "xtal_32k", "xtal"; - }; - }; - - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40014000 0x1000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart2: serial@40018000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40018000 0x1000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart7: serial@4001c000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x4001c000 0x1000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - rtc: rtc@40024000 { - compatible = "nxp,lpc3220-rtc"; - reg = <0x40024000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_RTC>; - }; - - gpio: gpio@40028000 { - compatible = "nxp,lpc3220-gpio"; - reg = <0x40028000 0x1000>; - gpio-controller; - #gpio-cells = <3>; /* bank, pin, flags */ - }; - - timer4: timer@4002c000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x4002c000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER4>; - clock-names = "timerclk"; - status = "disabled"; - }; - - timer5: timer@40030000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40030000 0x1000>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER5>; - clock-names = "timerclk"; - status = "disabled"; - }; - - watchdog: watchdog@4003c000 { - compatible = "nxp,pnx4008-wdt"; - reg = <0x4003c000 0x1000>; - clocks = <&clk LPC32XX_CLK_WDOG>; - }; - - timer0: timer@40044000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40044000 0x1000>; - clocks = <&clk LPC32XX_CLK_TIMER0>; - clock-names = "timerclk"; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; - - /* - * TSC vs. ADC: Since those two share the same - * hardware, you need to choose from one of the - * following two and do 'status = "okay";' for one of - * them - */ - - adc: adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_ADC>; - status = "disabled"; - }; - - tsc: tsc@40048000 { - compatible = "nxp,lpc3220-tsc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_ADC>; - status = "disabled"; - }; - - timer1: timer@4004c000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x4004c000 0x1000>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER1>; - clock-names = "timerclk"; - }; - - key: key@40050000 { - compatible = "nxp,lpc3220-key"; - reg = <0x40050000 0x1000>; - clocks = <&clk LPC32XX_CLK_KEY>; - interrupt-parent = <&sic1>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer2: timer@40058000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40058000 0x1000>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER2>; - clock-names = "timerclk"; - status = "disabled"; - }; - - pwm1: pwm@4005c000 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005c000 0x4>; - clocks = <&clk LPC32XX_CLK_PWM1>; - assigned-clocks = <&clk LPC32XX_CLK_PWM1>; - assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; - status = "disabled"; - }; - - pwm2: pwm@4005c004 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005c004 0x4>; - clocks = <&clk LPC32XX_CLK_PWM2>; - assigned-clocks = <&clk LPC32XX_CLK_PWM2>; - assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; - status = "disabled"; - }; - - timer3: timer@40060000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40060000 0x1000>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER3>; - clock-names = "timerclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/lpc4337-ciaa.dts deleted file mode 100644 index beddaba85393..000000000000 --- a/arch/arm/boot/dts/lpc4337-ciaa.dts +++ /dev/null @@ -1,221 +0,0 @@ -/* - * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) - * - * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "CIAA NXP LPC4337"; - compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; - - aliases { - serial0 = &uart2; - serial1 = &uart3; - }; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart2; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x0800000>; /* 8 MB */ - }; -}; - -&pinctrl { - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdc_cfg { - pins = "p7_7"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - ssp_pins: ssp-pins { - ssp1_cs { - pins = "p6_7"; - function = "gpio"; - bias-pull-up; - bias-disable; - }; - - ssp1_miso_mosi { - pins = "p1_3", "p1_4"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - input-enable; - input-schmitt-disable; - }; - - ssp1_sck { - pins = "pf_4"; - function = "ssp1"; - slew-rate = <1>; - bias-disable; - }; - }; - - uart2_pins: uart2-pins { - uart2_rx_cfg { - pins = "p7_2"; - function = "uart2"; - bias-disable; - input-enable; - }; - - uart2_tx_cfg { - pins = "p7_1"; - function = "uart2"; - bias-disable; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - bias-disable; - input-enable; - }; - - uart3_tx_cfg { - pins = "p2_3"; - function = "uart3"; - bias-disable; - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "microchip,24c512", "atmel,24c512"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x51>; - }; - - eeprom@54 { - compatible = "microchip,24c512", "atmel,24c512"; - reg = <0x54>; - }; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; -}; - -&sct_pwm { - status = "okay"; -}; - -&ssp1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp_pins>; - cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; - num-cs = <1>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts deleted file mode 100644 index 93d0c2e99e7c..000000000000 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ /dev/null @@ -1,481 +0,0 @@ -/* - * Hitex LPC4350 Evaluation Board - * - * Copyright 2015 Ariel D'Alessandro - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4350.dtsi" - -#include "dt-bindings/input/input.h" -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "Hitex LPC4350 Evaluation Board"; - compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart0; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x800000>; /* 8 MB */ - }; - - pca_buttons { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - autorepeat; - - button0 { - label = "joy:right"; - linux,code = ; - gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; - }; - - button1 { - label = "joy:up"; - linux,code = ; - gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; - }; - - - button2 { - label = "joy:enter"; - linux,code = ; - gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "joy:left"; - linux,code = ; - gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; - }; - - button4 { - label = "joy:down"; - linux,code = ; - gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; - }; - - button5 { - label = "user:sw3"; - linux,code = ; - gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; - }; - - button6 { - label = "user:sw4"; - linux,code = ; - gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; - }; - - button7 { - label = "user:sw5"; - linux,code = ; - gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; - }; - }; - - pca_leds { - compatible = "gpio-leds"; - - led0 { - label = "ext:led0"; - gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "ext:led1"; - gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; - }; - - led2 { - label = "ext:led2"; - gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; - }; - - led3 { - label = "ext:led3"; - gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; - }; - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "3v3io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&pinctrl { - adc1_pins: adc1-pins { - adc1_pins_cfg { - pins = "pf_9"; - function = "adc"; - input-disable; - bias-disable; - }; - }; - - emc_pins: emc-pins { - emc_addr0_23_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4", "pa_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_data0_15_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_bls0_3_cfg { - pins = "p1_4", "p6_6", "pd_13", "pd_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_cs0_cs2_cfg { - pins = "p1_5", "pd_12"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dqm0_3_cfg { - pins = "p6_12", "p6_10", "pd_0", "pe_13"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0", "clk1", "clk2", "clk3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - enet_mii_pins: enet-mii-pins { - enet_mii_rxd0_3_cfg { - pins = "p1_15", "p0_0", "p9_3", "p9_2"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_txd0_3_cfg { - pins = "p1_18", "p1_20", "p9_4", "p9_5"; - function = "enet"; - bias-disable; - }; - - enet_mii_crs_col_cfg { - pins = "p9_0", "p9_6"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_rx_clk_dv_er_cfg { - pins = "pc_0", "p1_16", "p9_1"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_tx_clk_en_cfg { - pins = "p1_19", "p0_1"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - spifi_pins: spifi-pins { - spifi_clk_cfg { - pins = "p3_3"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_mosi_miso_sio2_3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; -}; - -&adc1 { - status = "okay"; - vref-supply = <&vcc>; - pinctrl-names = "default"; - pinctrl-0 = <&adc1_pins>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2C0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x100000>; /* 1 MiB */ - }; - }; - }; - - cs2 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <2>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <30>; - mpmc,read-access-delay = <90>; - mpmc,page-mode-read-delay = <55>; - mpmc,write-access-delay = <55>; - mpmc,turn-round-delay = <55>; - - ext_sram: sram@2,0 { - compatible = "mmio-sram"; - reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <25000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - /* NXP SE97BTP with temperature sensor + eeprom */ - sensor@18 { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x18>; - }; - - eeprom@50 { - compatible = "nxp,24c02", "atmel,24c02"; - reg = <0x50>; - }; - - pca_gpio: gpio@24 { - compatible = "nxp,pca9673"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mac { - status = "okay"; - phy-mode = "mii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_mii_pins>; -}; - -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - flash { - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2c0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x500000>; /* 5 MiB */ - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; diff --git a/arch/arm/boot/dts/lpc4350.dtsi b/arch/arm/boot/dts/lpc4350.dtsi deleted file mode 100644 index c4422f587055..000000000000 --- a/arch/arm/boot/dts/lpc4350.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * NXP LPC4350 and LPC4330 SoC - * - * Copyright 2015 Ariel D'Alessandro - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/ { - compatible = "nxp,lpc4350", "nxp,lpc4330"; - - cpus { - cpu@0 { - compatible = "arm,cortex-m4"; - }; - }; - - soc { - sram0: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ - }; - - sram1: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ - }; - - sram2: sram@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ - }; - }; -}; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts deleted file mode 100644 index 224f80a4a31d..000000000000 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Embedded Artist LPC4357 Developer's Kit - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include "dt-bindings/input/input.h" -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "Embedded Artists' LPC4357 Developer's Kit"; - compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart0; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x2000000>; /* 32 MB */ - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "3v3-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* vmmc is controlled by sdmmc host internally */ - vmmc: vmmc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - gpio_joystick { - compatible = "gpio-keys-polled"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_joystick_pins>; - poll-interval = <100>; - autorepeat; - - button0 { - label = "joy_enter"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; - }; - - button1 { - label = "joy_left"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; - }; - - button2 { - label = "joy_up"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "joy_right"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; - }; - - button4 { - label = "joy_down"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; - }; - }; - - leds_mmio { - compatible = "gpio-leds"; - - led1 { - gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; - }; - - led3 { - gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; - }; - - led4 { - gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; - }; - - led5 { - gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; - }; - - led6 { - gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; - }; - - led7 { - gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; - }; - - led8 { - gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; - }; - - led9 { - gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; - }; - - led10 { - gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; - }; - - led11 { - gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; - }; - - led12 { - gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; - }; - - led13 { - gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; - }; - - led14 { - gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; - }; - - led15 { - gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; - }; - - led16 { - gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - emc_pins: emc-pins { - emc_addr0_23_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4", "pa_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_data0_31_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3", - "pd_2", "pd_3", "pd_4", "pd_5", - "pd_6", "pd_7", "pd_8", "pd_9", - "pe_5", "pe_6", "pe_7", "pe_8", - "pe_9", "pe_10", "pe_11", "pe_12"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_bls0_3_cfg { - pins = "p1_4", "p6_6", "pd_13", "pd_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_cs0_3_cfg { - pins = "p1_5", "p6_3", "pd_12", "pd_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dqm0_3_cfg { - pins = "p6_12", "p6_10", "pd_0", "pe_13"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0", "clk1", "clk2", "clk3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - gpio_joystick_pins: gpio-joystick-pins { - gpio_joystick_cfg { - pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; - function = "gpio"; - input-enable; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - sdmmc_pins: sdmmc-pins { - sdmmc_clk_cfg { - pins = "pc_0"; - function = "sdmmc"; - slew-rate = <1>; - bias-pull-down; - }; - - sdmmc_cmd_dat0_3_cfg { - pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; - function = "sdmmc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - sdmmc_cd_cfg { - pins = "pc_8"; - function = "sdmmc"; - bias-pull-down; - input-enable; - }; - - sdmmc_pow_cfg { - pins = "pc_9"; - function = "sdmmc"; - bias-pull-down; - }; - }; - - spifi_pins: spifi-pins { - spifi_clk_cfg { - pins = "p3_3"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_mosi_miso_sio2_3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - slew-rate = <0>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - bias-disable; - }; - }; - - ssp0_pins: ssp0-pins { - ssp0_sck_miso_mosi { - pins = "pf_0", "pf_2", "pf_3"; - function = "ssp0"; - slew-rate = <1>; - bias-pull-down; - input-enable; - input-schmitt-disable; - }; - - ssp0_ssel { - pins = "pf_1"; - function = "ssp0"; - bias-pull-up; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart3_tx_cfg { - pins = "p9_3"; - function = "uart3"; - bias-pull-down; - }; - }; - - usb0_pins: usb0-pins { - usb0_pwr_enable { - pins = "p2_3"; - function = "usb0"; - }; - - usb0_pwr_fault { - pins = "p8_0"; - function = "usb0"; - bias-disable; - input-enable; - }; - }; -}; - -&adc0 { - status = "okay"; - vref-supply = <&vcc>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - mma7455@1d { - compatible = "fsl,mma7455"; - reg = <0x1d>; - }; - - lm75@48 { - compatible = "nxp,lm75"; - reg = <0x48>; - }; - - eeprom@57 { - compatible = "microchip,24c64", "atmel,24c64"; - reg = <0x57>; - }; -}; - -&dac { - status = "okay"; - vref-supply = <&vcc>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2c0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x100000>; /* 1 MiB */ - }; - }; - }; - - cs2 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <2>; - mpmc,memory-width = <16>; - - mmio_leds: gpio@2,0 { - compatible = "ti,7416374"; - reg = <2 0 0x2>; - gpio-controller; - #gpio-cells = <2>; - }; - - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; -}; - -&mmcsd { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vmmc>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pins>; -}; - -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - flash { - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data"; - reg = <0 0x200000>; - }; - }; -}; - -&ssp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_pins>; - num-cs = <1>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; -}; diff --git a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts deleted file mode 100644 index 1f84654df50c..000000000000 --- a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts +++ /dev/null @@ -1,619 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel - * - * Copyright (C) 2016-2018 Vladimir Zapolskiy - */ - -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include - -/ { - model = "MYIR Tech LPC4357 Development Board"; - compatible = "myir,myd-lpc4357", "nxp,lpc4357"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x2000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led4 { - gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led5 { - gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led6 { - gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - panel: panel { - compatible = "innolux,at070tn92"; - - port { - panel_input: endpoint { - remote-endpoint = <&lcdc_output>; - }; - }; - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vcc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vmmc: vmmc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&pinctrl { - can0_pins: can0-pins { - can_rd_cfg { - pins = "p3_1"; - function = "can0"; - input-enable; - }; - - can_td_cfg { - pins = "p3_2"; - function = "can0"; - }; - }; - - can1_pins: can1-pins { - can_rd_cfg { - pins = "pe_1"; - function = "can1"; - input-enable; - }; - - can_td_cfg { - pins = "pe_0"; - function = "can1"; - }; - }; - - emc_pins: emc-pins { - emc_addr0_22_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_data0_15_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3"; - function = "emc"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_cs0_cfg { - pins = "p1_5"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_dqm0_1_cfg { - pins = "p6_12", "p6_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0"; - function = "emc"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - }; - - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - input-enable; - input-schmitt-disable; - bias-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - input-enable; - input-schmitt-disable; - bias-disable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - slew-rate = <1>; - bias-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - input-enable; - input-schmitt-disable; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - i2c1_pins: i2c1-pins { - i2c1_pins_cfg { - pins = "pe_15", "pe_13"; - function = "i2c1"; - input-enable; - }; - }; - - lcd_pins: lcd-pins { - lcd_vd0_23_cfg { - pins = "p4_1", "p4_4", "p4_3", "p4_2", - "p8_7", "p8_6", "p8_5", "p8_4", - "p7_5", "p4_8", "p4_10", "p4_9", - "p8_3", "pb_6", "pb_5", "pb_4", - "p7_4", "p7_3", "p7_2", "p7_1", - "pb_3", "pb_2", "pb_1", "pb_0"; - function = "lcd"; - }; - - lcd_vsync_en_dclk_lp_pwr_cfg { - pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; - function = "lcd"; - }; - }; - - led_pins: led-pins { - led_1_6_cfg { - pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; - function = "gpio"; - bias-pull-down; - }; - }; - - sdmmc_pins: sdmmc-pins { - sdmmc_clk_cfg { - pins = "pc_0"; - function = "sdmmc"; - slew-rate = <1>; - bias-pull-down; - }; - - sdmmc_cmd_dat0_3_cfg { - pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; - function = "sdmmc"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - sdmmc_cd_cfg { - pins = "pc_8"; - function = "sdmmc"; - input-enable; - bias-pull-down; - }; - }; - - spifi_pins: spifi-pins { - spifi_sck_cfg { - pins = "p3_3"; - function = "spifi"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - spifi_mosi_miso_sio2_sio3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - bias-disable; - }; - }; - - ssp1_pins: ssp1-pins { - ssp1_sck_cfg { - pins = "pf_4"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - }; - - ssp1_miso_cfg { - pins = "pf_6"; - function = "ssp1"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-pull-down; - }; - - ssp1_mosi_cfg { - pins = "pf_7"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - }; - - ssp1_ssel_cfg { - pins = "pf_5"; - function = "gpio"; - bias-disable; - }; - }; - - uart0_pins: uart0-pins { - uart0_rxd_cfg { - pins = "pf_11"; - function = "uart0"; - input-enable; - input-schmitt-disable; - bias-disable; - }; - - uart0_clk_dir_txd_cfg { - pins = "pf_8", "pf_9", "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; - - uart1_pins: uart1-pins { - uart1_rxd_cfg { - pins = "pc_14"; - function = "uart1"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - uart1_dtr_txd_cfg { - pins = "pc_12", "pc_13"; - function = "uart1"; - bias-pull-down; - }; - }; - - uart2_pins: uart2-pins { - uart2_rxd_cfg { - pins = "pa_2"; - function = "uart2"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - uart2_txd_cfg { - pins = "pa_1"; - function = "uart2"; - bias-pull-down; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - uart3_tx_cfg { - pins = "p2_3"; - function = "uart3"; - bias-pull-down; - }; - }; - - usb0_pins: usb0-pins { - usb0_pwr_enable_cfg { - pins = "p6_3"; - function = "usb0"; - }; - - usb0_pwr_fault_cfg { - pins = "p8_0"; - function = "usb0"; - bias-disable; - input-enable; - }; - }; -}; - -&adc1 { - status = "okay"; - vref-supply = <&vcc>; -}; - -&can0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins>; -}; - -/* Pin conflict with EMC, muxed by JP5 and JP6 */ -&can1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - /* SST/Microchip SST39VF1601 */ - flash@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - sensor@49 { - compatible = "lm75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - }; -}; - -&lcdc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - max-memory-bandwidth = <92240000>; - - port { - lcdc_output: endpoint { - remote-endpoint = <&panel_input>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; - phy-handle = <&phy1>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&mmcsd { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pins>; - bus-width = <4>; - vmmc-supply = <&vmmc>; -}; - -/* Pin conflict with SSP0, the latter is routed to J17 pin header */ -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - /* Atmel AT25DF321A */ - flash { - compatible = "jedec,spi-nor"; - spi-max-frequency = <51000000>; - spi-cpol; - spi-cpha; - }; -}; - -&ssp1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp1_pins>; - num-cs = <1>; - cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; -}; - -/* Routed to J17 pin header */ -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -/* RS485 */ -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -/* Routed to J17 pin header */ -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; -}; diff --git a/arch/arm/boot/dts/lpc4357.dtsi b/arch/arm/boot/dts/lpc4357.dtsi deleted file mode 100644 index 72f12db8d53a..000000000000 --- a/arch/arm/boot/dts/lpc4357.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -/* - * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/ { - compatible = "nxp,lpc4357"; - - cpus { - cpu@0 { - compatible = "arm,cortex-m4"; - }; - }; - - soc { - sram0: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ - }; - - sram1: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ - }; - - sram2: sram@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ - }; - }; -}; - -&eeprom { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts deleted file mode 100644 index ce8e26d7791f..000000000000 --- a/arch/arm/boot/dts/ls1021a-iot.dts +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2021-2022 NXP - * - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A-IOT Board"; - compatible = "fsl,ls1021a-iot", "fsl,ls1021a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator-3V3 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2V5 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - frame-master; - bitclock-master; - }; - }; -}; - -&can0{ - status = "disabled"; -}; - -&can1{ - status = "disabled"; -}; - -&can2{ - status = "disabled"; -}; - -&can3{ - status = "okay"; -}; - -&dcu { - display = <&display>; - status = "okay"; - - display: display@0 { - bits-per-pixel = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: mode0 { - clock-frequency = <25000000>; - hactive = <640>; - vactive = <480>; - hback-porch = <80>; - hfront-porch = <80>; - vback-porch = <16>; - vfront-porch = <16>; - hsync-len = <12>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; -}; - -&enet0 { - tbi-handle = <&tbi1>; - phy-handle = <&phy1>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi1>; - phy-handle = <&phy3>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - fixed-link = <0 1 1000 0 0>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&esdhc{ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9555: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sgtl5000: audio-codec@2a { - #sound-dai-cells = <0x0>; - compatible = "fsl,sgtl5000"; - reg = <0x2a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_2p5v>; - clocks = <&sys_mclk>; - }; - - max1239: adc@35 { - compatible = "maxim,max1239"; - reg = <0x35>; - #io-channel-cells = <1>; - }; - - ina2201: core-monitor@44 { - compatible = "ti,ina220"; - reg = <0x44>; - shunt-resistor = <1000>; - }; - - ina2202: current-monitor@45 { - compatible = "ti,ina220"; - reg = <0x45>; - shunt-resistor = <1000>; - }; - - lm75b: thermal-monitor@48 { - compatible = "national,lm75b"; - reg = <0x48>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - phy0: ethernet-phy@0 { - reg = <0x0>; - }; - - phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - phy3: ethernet-phy@3 { - reg = <0x3>; - }; - - tbi1: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&qspi { - num-cs = <2>; - status = "okay"; - - s25fl128s: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&sai2 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts deleted file mode 100644 index d2cae8c7d7a6..000000000000 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/ - * - * Author: Harry YJ Jhou (周亞諄) - * Jimmy Chen (陳永達) - * SZ Lin (林上智) - */ - -/dts-v1/; - -#include -#include -#include "ls1021a.dtsi" - -/ { - model = "Moxa UC-8410A"; - compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; - - aliases { - enet0_rgmii_phy = &rgmii_phy0; - enet1_rgmii_phy = &rgmii_phy1; - enet2_rgmii_phy = &rgmii_phy2; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - cel-pwr { - label = "UC8410A:CEL-PWR"; - gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - cel-reset { - label = "UC8410A:CEL-RESET"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - str-led { - label = "UC8410A:RED:PROG"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - sw-ready { - label = "UC8410A:GREEN:SWRDY"; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - beeper { - label = "UC8410A:BEEP"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - prog-led0 { - label = "UC8410A:GREEN:PROG2"; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - prog-led1 { - label = "UC8410A:GREEN:PROG1"; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - prog-led2 { - label = "UC8410A:GREEN:PROG0"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - wifi-signal0 { - label = "UC8410A:GREEN:CEL2"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - wifi-signal1 { - label = "UC8410A:GREEN:CEL1"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - wifi-signal2 { - label = "UC8410A:GREEN:CEL0"; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - cpu-diag-red { - label = "UC8410A:RED:DIA"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - cpu-diag-green { - label = "UC8410A:GREEN:DIA"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - cpu-diag-yellow { - label = "UC8410A:YELLOW:DIA"; - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pushbtn-key { - label = "push button key"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,code = ; - default-state = "on"; - }; - }; -}; - -&enet0 { - phy-handle = <&rgmii_phy0>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&enet1 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - tpm@20 { - compatible = "infineon,slb9635tt"; - reg = <0x20>; - }; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@0 { - compatible = "marvell,88e1118"; - reg = <0x0>; - marvell,reg-init = - <3 0x11 0 0x4415>, /* Reg 3,17 */ - <3 0x10 0 0x77>; /* Reg 3,16 */ - }; - - rgmii_phy1: ethernet-phy@1 { - compatible = "marvell,88e1118"; - reg = <0x1>; - marvell,reg-init = - <3 0x11 0 0x4415>, /* Reg 3,17 */ - <3 0x10 0 0x77>; /* Reg 3,16 */ - }; - - rgmii_phy2: ethernet-phy@2 { - compatible = "marvell,88e1118"; - reg = <0x2>; - marvell,reg-init = - <3 0x11 0 0x4415>, /* Reg 3,17 */ - <3 0x10 0 0x77>; /* Reg 3,16 */ - }; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl064l", "spansion,s25fl164k"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - - partitions@0 { - label = "U-Boot"; - reg = <0x0 0x180000>; - }; - - partitions@180000 { - label = "U-Boot Env"; - reg = <0x180000 0x680000>; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts deleted file mode 100644 index f1acb97aee69..000000000000 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A QDS Board"; - compatible = "fsl,ls1021a-qds", "fsl,ls1021a"; - - aliases { - enet0_rgmii_phy = &rgmii_phy1; - enet1_rgmii_phy = &rgmii_phy2; - enet2_rgmii_phy = &rgmii_phy3; - enet0_sgmii_phy = &sgmii_phy1c; - enet1_sgmii_phy = &sgmii_phy1d; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - dspiflash: at45db021d@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1c>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1d>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy3>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547: mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ds3232: rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - interrupts = ; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - adt7461a@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - codec: sgtl5000@2a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x2a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000>, - <0x2 0x0 0x0 0x7e800000 0x00010000>, - <0x3 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-mfd"; - reg = <0x3 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 3 0 0x100>; - - mdio-mux-emi1 { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x54 1>; /* BRDCFG4 */ - mux-mask = <0xe0>; /* EMI1[2:0] */ - - /* Onboard PHYs */ - ls1021amdio0: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - - ls1021amdio1: mdio@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - ls1021amdio2: mdio@40 { - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - }; - - ls1021amdio3: mdio@60 { - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1c: ethernet-phy@1c { - reg = <0x1c>; - }; - }; - - ls1021amdio4: mdio@80 { - reg = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1d: ethernet-phy@1d { - reg = <0x1d>; - }; - }; - }; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - tbi0: tbi-phy@8 { - reg = <0x8>; - device_type = "tbi-phy"; - }; -}; - -&qspi { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - reg = <0>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -&can3 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts deleted file mode 100644 index 1ea32fff4120..000000000000 --- a/arch/arm/boot/dts/ls1021a-tsn.dts +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2018 NXP Semiconductors - * Copyright 2019 Vladimir Oltean - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "NXP LS1021A-TSN Board"; - compatible = "fsl,ls1021a-tsn", "fsl,ls1021a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_vdda_codec: regulator-3V3 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_codec: regulator-2V5 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - /* ADG704BRMZ 1:4 SPI mux/demux */ - sja1105: ethernet-switch@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,sja1105t"; - /* 12 MHz */ - spi-max-frequency = <12000000>; - /* Sample data on trailing clock edge */ - spi-cpha; - /* SPI controller settings for SJA1105 timing requirements */ - fsl,spi-cs-sck-delay = <1000>; - fsl,spi-sck-cs-delay = <1000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - /* ETH5 written on chassis */ - label = "swp5"; - phy-handle = <&rgmii_phy6>; - phy-mode = "rgmii-id"; - reg = <0>; - }; - - port@1 { - /* ETH2 written on chassis */ - label = "swp2"; - phy-handle = <&rgmii_phy3>; - phy-mode = "rgmii-id"; - reg = <1>; - }; - - port@2 { - /* ETH3 written on chassis */ - label = "swp3"; - phy-handle = <&rgmii_phy4>; - phy-mode = "rgmii-id"; - reg = <2>; - }; - - port@3 { - /* ETH4 written on chassis */ - label = "swp4"; - phy-handle = <&rgmii_phy5>; - phy-mode = "rgmii-id"; - reg = <3>; - }; - - port@4 { - /* Internal port connected to eth2 */ - ethernet = <&enet2>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - reg = <4>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy2>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -/* RGMII delays added via PCB traces */ -&enet2 { - phy-mode = "rgmii"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&esdhc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - /* 3 axis accelerometer */ - accelerometer@1e { - compatible = "fsl,fxls8471"; - reg = <0x1e>; - }; - - /* Audio codec (SAI2) */ - audio-codec@2a { - compatible = "fsl,sgtl5000"; - VDDIO-supply = <®_vddio_codec>; - VDDA-supply = <®_vdda_codec>; - #sound-dai-cells = <0>; - clocks = <&sys_mclk>; - reg = <0x2a>; - }; - - /* Current sensing circuit for 1V VDDCORE PMIC rail */ - current-sensor@44 { - compatible = "ti,ina220"; - shunt-resistor = <1000>; - reg = <0x44>; - }; - - /* Current sensing circuit for 12V VCC rail */ - current-sensor@45 { - compatible = "ti,ina220"; - shunt-resistor = <1000>; - reg = <0x45>; - }; - - /* Thermal monitor - case */ - temperature-sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - /* Thermal monitor - chip */ - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - }; - - /* Unsupported devices: - * - FXAS21002C Gyroscope at 0x20 - * - TI ADS7924 4-channel ADC at 0x49 - */ -}; - -&ifc { - status = "disabled"; -}; - -&lpuart0 { - status = "okay"; -}; - -&lpuart3 { - status = "okay"; -}; - -&mdio0 { - /* AR8031 */ - sgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - /* SGMII1_PHY_INT_B: connected to IRQ2, active low */ - interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; - }; - - /* AR8031 */ - sgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - /* SGMII2_PHY_INT_B: connected to IRQ2, active low */ - interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; - }; - - /* BCM5464 quad PHY */ - rgmii_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - - rgmii_phy4: ethernet-phy@4 { - reg = <0x4>; - }; - - rgmii_phy5: ethernet-phy@5 { - reg = <0x5>; - }; - - rgmii_phy6: ethernet-phy@6 { - reg = <0x6>; - }; - - /* SGMII PCS for enet0 */ - tbi0: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&mdio1 { - /* SGMII PCS for enet1 */ - tbi1: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&qspi { - status = "okay"; - - flash@0 { - /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "RCW"; - reg = <0x0 0x40000>; - }; - - partition@40000 { - label = "U-Boot"; - reg = <0x40000 0x300000>; - }; - - partition@340000 { - label = "U-Boot Env"; - reg = <0x340000 0x100000>; - }; - }; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts deleted file mode 100644 index f5c03871b205..000000000000 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A TWR Board"; - compatible = "fsl,ls1021a-twr", "fsl,ls1021a"; - - aliases { - enet2_rgmii_phy = &rgmii_phy1; - enet0_sgmii_phy = &sgmii_phy2; - enet1_sgmii_phy = &sgmii_phy0; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; - - panel: panel { - compatible = "nec,nl4827hc19-05b"; - - port { - panel_in: endpoint { - remote-endpoint = <&dcu_out>; - }; - }; - }; -}; - -&dcu { - status = "okay"; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&dspi1 { - bus-num = <0>; - status = "okay"; - - dspiflash: s25fl064k@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl064k"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy2>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy0>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - -}; - -&i2c1 { - status = "okay"; - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk>; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR Flash on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - sgmii_phy0: ethernet-phy@0 { - reg = <0x0>; - }; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - sgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - tbi0: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&mdio1 { - tbi1: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&esdhc { - status = "okay"; -}; - -&qspi { - status = "okay"; - - n25q128a130: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; -}; - -&sai1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -&can3 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi deleted file mode 100644 index 49c78c84cd5d..000000000000 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ /dev/null @@ -1,987 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - crypto = &crypto; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - rtc1 = &ftm_alarm0; - serial0 = &lpuart0; - serial1 = &lpuart1; - serial2 = &lpuart2; - serial3 = &lpuart3; - serial4 = &lpuart4; - serial5 = &lpuart5; - sysclk = &sysclk; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - clocks = <&clockgen 1 0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@f01 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; - clocks = <&clockgen 1 0>; - #cooling-cells = <2>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x0>; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - device_type = "soc"; - interrupt-parent = <&gic>; - ranges; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - big-endian; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0x0 0x1000>, - <0x0 0x1402000 0x0 0x2000>, - <0x0 0x1404000 0x0 0x2000>, - <0x0 0x1406000 0x0 0x2000>; - interrupts = ; - - }; - - msi1: msi-controller@1570e00 { - compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e00 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - msi2: msi-controller@1570e08 { - compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e08 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - ifc: memory-controller@1530000 { - compatible = "fsl,ifc"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = ; - status = "disabled"; - }; - - sfp: efuse@1e80000 { - compatible = "fsl,ls1021a-sfp"; - reg = <0x0 0x1e80000 0x0 0x10000>; - clocks = <&clockgen 4 3>; - clock-names = "sfp"; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x1000>; - big-endian; - }; - - qspi: spi@1550000 { - compatible = "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x20000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - status = "disabled"; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1021a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20220520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; - dma-coherent; - status = "disabled"; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1021a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1570000 0x10000>; - - extirq: interrupt-controller@1ac { - compatible = "fsl,ls1021a-extirq"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1ac 4>; - interrupt-map = - <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0x7 0x0>; - }; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <7>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x1700000 0x0 0x100000>; - ranges = <0x0 0x0 0x1700000 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - - }; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1021a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = ; - fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; - fsl,tmu-calibration = <0x00000000 0x00000020>, - <0x00000001 0x00000024>, - <0x00000002 0x0000002a>, - <0x00000003 0x00000032>, - <0x00000004 0x00000038>, - <0x00000005 0x0000003e>, - <0x00000006 0x00000043>, - <0x00000007 0x0000004a>, - <0x00000008 0x00000050>, - <0x00000009 0x00000059>, - <0x0000000a 0x0000005f>, - <0x0000000b 0x00000066>, - - <0x00010000 0x00000023>, - <0x00010001 0x0000002b>, - <0x00010002 0x00000033>, - <0x00010003 0x0000003a>, - <0x00010004 0x00000042>, - <0x00010005 0x0000004a>, - <0x00010006 0x00000054>, - <0x00010007 0x0000005c>, - <0x00010008 0x00000065>, - <0x00010009 0x0000006f>, - - <0x00020000 0x00000029>, - <0x00020001 0x00000033>, - <0x00020002 0x0000003d>, - <0x00020003 0x00000048>, - <0x00020004 0x00000054>, - <0x00020005 0x00000060>, - <0x00020006 0x0000006c>, - - <0x00030000 0x00000025>, - <0x00030001 0x00000033>, - <0x00030002 0x00000043>, - <0x00030003 0x00000055>; - #thermal-sensor-cells = <1>; - }; - - dspi0: spi@2100000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - - dspi1: spi@2110000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - dma-names = "rx", "tx"; - dmas = <&edma0 1 38>, <&edma0 1 39>; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - dma-names = "rx", "tx"; - dmas = <&edma0 1 36>, <&edma0 1 37>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - dma-names = "rx", "tx"; - dmas = <&edma0 1 34>, <&edma0 1 35>; - status = "disabled"; - }; - - uart0: serial@21c0500 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart1: serial@21c0600 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart2: serial@21d0500 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart3: serial@21d0600 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - counter0: counter@29d0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29d0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - counter1: counter@29e0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29e0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - counter2: counter@29f0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29f0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - counter3: counter@2a00000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x2a00000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = ; - clocks = <&sysclk>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - pwm0: pwm@29d0000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x29d0000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm1: pwm@29e0000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x29e0000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm2: pwm@29f0000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x29f0000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm3: pwm@2a00000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a00000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm4: pwm@2a10000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a10000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm5: pwm@2a20000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a20000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm6: pwm@2a30000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a30000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm7: pwm@2a40000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a40000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "wdog-en"; - big-endian; - }; - - sai1: sai@2b50000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; - status = "disabled"; - }; - - sai2: sai@2b60000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; - status = "disabled"; - }; - - edma0: dma-controller@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; - }; - - dcu: dcu@2ce0000 { - compatible = "fsl,ls1021a-dcu"; - reg = <0x0 0x2ce0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 0>, - <&clockgen 4 0>; - clock-names = "dcu", "pix"; - big-endian; - status = "disabled"; - }; - - mdio0: mdio@2d24000 { - compatible = "gianfar"; - device_type = "mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2d24000 0x0 0x4000>, - <0x0 0x2d10030 0x0 0x4>; - }; - - mdio1: mdio@2d64000 { - compatible = "gianfar"; - device_type = "mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2d64000 0x0 0x4000>, - <0x0 0x2d50030 0x0 0x4>; - }; - - ptp_clock@2d10e00 { - compatible = "fsl,etsec-ptp"; - reg = <0x0 0x2d10e00 0x0 0xb0>; - interrupts = ; - fsl,tclk-period = <5>; - fsl,tmr-prsc = <2>; - fsl,tmr-add = <0xaaaaaaab>; - fsl,tmr-fiper1 = <999999995>; - fsl,tmr-fiper2 = <999999995>; - fsl,max-adj = <499999999>; - fsl,extts-fifo; - }; - - enet0: ethernet@2d10000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - fsl,magic-packet; - ranges; - dma-coherent; - - queue-group@2d10000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d10000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d14000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d14000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - enet1: ethernet@2d50000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - ranges; - dma-coherent; - - queue-group@2d50000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d50000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d54000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d54000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - enet2: ethernet@2d90000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - ranges; - dma-coherent; - - queue-group@2d90000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d90000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d94000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d94000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - usb2: usb@8600000 { - compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; - reg = <0x0 0x8600000 0x0 0x1000>; - interrupts = ; - dr_mode = "host"; - phy_type = "ulpi"; - }; - - usb3: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - pcie@3400000 { - compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ - <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */ - <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie@3500000 { - compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ - <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; - fsl,pcie-scfg = <&scfg 1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */ - <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - can0: can@2a70000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2a70000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - status = "disabled"; - }; - - can1: can@2a80000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2a80000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - status = "disabled"; - }; - - can2: can@2a90000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2a90000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - status = "disabled"; - }; - - can3: can@2aa0000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2aa0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - status = "disabled"; - }; - - ocram1: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x0 0x10000000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x10000000 0x10000>; - }; - - ocram2: sram@10010000 { - compatible = "mmio-sram"; - reg = <0x0 0x10010000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x10010000 0x10000>; - }; - - qdma: dma-controller@8390000 { - compatible = "fsl,ls1021a-qdma"; - reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8389000 0x0 0x1000>, /* Status regs */ - <0x0 0x838a000 0x0 0x2000>; /* Block regs */ - interrupts = , - , - ; - interrupt-names = "qdma-error", - "qdma-queue0", "qdma-queue1"; - #dma-cells = <2>; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x1000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - big-endian; - }; - - rcpm: power-controller@1ee2140 { - compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1ee2140 0x0 0x8>; - #fsl,rcpm-wakeup-cells = <2>; - #power-domain-cells = <0>; - }; - - ftm_alarm0: timer0@29d0000 { - compatible = "fsl,ls1021a-ftm-alarm"; - reg = <0x0 0x29d0000 0x0 0x10000>; - reg-names = "ftm"; - fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; - interrupts = ; - big-endian; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/marvell/Makefile b/arch/arm/boot/dts/marvell/Makefile new file mode 100644 index 000000000000..1e0f5ff492f7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/Makefile @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MMP) += \ + pxa168-aspenite.dtb \ + pxa910-dkb.dtb \ + mmp2-brownstone.dtb \ + mmp2-olpc-xo-1-75.dtb \ + mmp3-dell-ariel.dtb +dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-kuroboxpro.dtb \ + orion5x-lacie-d2-network.dtb \ + orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-linkstation-lsgl.dtb \ + orion5x-linkstation-lswtgl.dtb \ + orion5x-linkstation-lschl.dtb \ + orion5x-lswsgl.dtb \ + orion5x-maxtor-shared-storage-2.dtb \ + orion5x-netgear-wnr854t.dtb \ + orion5x-rd88f5182-nas.dtb +dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-c200-v2.dtb \ + armada-370-db.dtb \ + armada-370-dlink-dns327l.dtb \ + armada-370-mirabox.dtb \ + armada-370-netgear-rn102.dtb \ + armada-370-netgear-rn104.dtb \ + armada-370-rd.dtb \ + armada-370-seagate-nas-2bay.dtb \ + armada-370-seagate-nas-4bay.dtb \ + armada-370-seagate-personal-cloud.dtb \ + armada-370-seagate-personal-cloud-2bay.dtb \ + armada-370-synology-ds213j.dtb +dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb +dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-381-netgear-gs110emx.dtb \ + armada-382-rd-ac3x-48g4x2xl.dtb \ + armada-385-atl-x530.dtb \ + armada-385-clearfog-gtr-s4.dtb \ + armada-385-clearfog-gtr-l8.dtb \ + armada-385-db-88f6820-amc.dtb \ + armada-385-db-ap.dtb \ + armada-385-linksys-caiman.dtb \ + armada-385-linksys-cobra.dtb \ + armada-385-linksys-rango.dtb \ + armada-385-linksys-shelby.dtb \ + armada-385-synology-ds116.dtb \ + armada-385-turris-omnia.dtb \ + armada-388-clearfog.dtb \ + armada-388-clearfog-base.dtb \ + armada-388-clearfog-pro.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-helios4.dtb \ + armada-388-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-390-db.dtb \ + armada-395-gp.dtb \ + armada-398-db.dtb +dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-crs305-1g-4s-bit.dtb \ + armada-xp-crs326-24g-2s.dtb \ + armada-xp-crs326-24g-2s-bit.dtb \ + armada-xp-crs328-4c-20s-4s.dtb \ + armada-xp-crs328-4c-20s-4s-bit.dtb \ + armada-xp-db.dtb \ + armada-xp-db-dxbc2.dtb \ + armada-xp-db-xc3-24g4xg.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ + armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb \ + armada-xp-synology-ds414.dtb +dtb-$(CONFIG_MACH_DOVE) += \ + dove-cubox.dtb \ + dove-cubox-es.dtb \ + dove-d2plug.dtb \ + dove-d3plug.dtb \ + dove-dove-db.dtb \ + dove-sbc-a510.dtb +dtb-$(CONFIG_MACH_KIRKWOOD) += \ + kirkwood-4i-edge-200.dtb \ + kirkwood-b3.dtb \ + kirkwood-blackarmor-nas220.dtb \ + kirkwood-c200-v1.dtb \ + kirkwood-cloudbox.dtb \ + kirkwood-d2net.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ + kirkwood-dir665.dtb \ + kirkwood-dns320.dtb \ + kirkwood-dns325.dtb \ + kirkwood-dockstar.dtb \ + kirkwood-dreamplug.dtb \ + kirkwood-ds109.dtb \ + kirkwood-ds110jv10.dtb \ + kirkwood-ds111.dtb \ + kirkwood-ds112.dtb \ + kirkwood-ds209.dtb \ + kirkwood-ds210.dtb \ + kirkwood-ds212.dtb \ + kirkwood-ds212j.dtb \ + kirkwood-ds409.dtb \ + kirkwood-ds409slim.dtb \ + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ + kirkwood-ib62x0.dtb \ + kirkwood-iconnect.dtb \ + kirkwood-iomega_ix2_200.dtb \ + kirkwood-is2.dtb \ + kirkwood-km_fixedeth.dtb \ + kirkwood-km_kirkwood.dtb \ + kirkwood-l-50.dtb \ + kirkwood-laplug.dtb \ + kirkwood-linkstation-lsqvl.dtb \ + kirkwood-linkstation-lsvl.dtb \ + kirkwood-linkstation-lswsxl.dtb \ + kirkwood-linkstation-lswvl.dtb \ + kirkwood-linkstation-lswxl.dtb \ + kirkwood-linksys-viper.dtb \ + kirkwood-lschlv2.dtb \ + kirkwood-lsxhl.dtb \ + kirkwood-mplcec4.dtb \ + kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-nas2big.dtb \ + kirkwood-net2big.dtb \ + kirkwood-net5big.dtb \ + kirkwood-netgear_readynas_duo_v2.dtb \ + kirkwood-netgear_readynas_nv+_v2.dtb \ + kirkwood-ns2.dtb \ + kirkwood-ns2lite.dtb \ + kirkwood-ns2max.dtb \ + kirkwood-ns2mini.dtb \ + kirkwood-nsa310.dtb \ + kirkwood-nsa310a.dtb \ + kirkwood-nsa310s.dtb \ + kirkwood-nsa320.dtb \ + kirkwood-nsa325.dtb \ + kirkwood-openblocks_a6.dtb \ + kirkwood-openblocks_a7.dtb \ + kirkwood-openrd-base.dtb \ + kirkwood-openrd-client.dtb \ + kirkwood-openrd-ultimate.dtb \ + kirkwood-pogo_e02.dtb \ + kirkwood-pogoplug-series-4.dtb \ + kirkwood-rd88f6192.dtb \ + kirkwood-rd88f6281-z0.dtb \ + kirkwood-rd88f6281-a.dtb \ + kirkwood-rs212.dtb \ + kirkwood-rs409.dtb \ + kirkwood-rs411.dtb \ + kirkwood-sheevaplug.dtb \ + kirkwood-sheevaplug-esata.dtb \ + kirkwood-t5325.dtb \ + kirkwood-topkick.dtb \ + kirkwood-ts219-6281.dtb \ + kirkwood-ts219-6282.dtb \ + kirkwood-ts419-6281.dtb \ + kirkwood-ts419-6282.dtb diff --git a/arch/arm/boot/dts/marvell/armada-370-c200-v2.dts b/arch/arm/boot/dts/marvell/armada-370-c200-v2.dts new file mode 100644 index 000000000000..84d40e1d70ef --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-c200-v2.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree file for Ctera C200-V2 + * + * Copyright (C) 2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "armada-370.dtsi" +#include +#include +#include +#include + +/ { + model = "Ctera C200 V2"; + compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1024 MB */ + }; + + soc { + ranges = ; + }; + + thermal-zones { + ethphy-thermal { + polling-delay = <20000>; + polling-delay-passive = <2000>; + + thermal-sensors = <ðphy0>; + + trips { + ethphy_alert1: trip1 { + temperature = <65000>; + hysteresis = <4000>; + type = "passive"; + }; + + ethphy_crit: trip2 { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pinctrl-0 = <&pmx_beeper>; + pinctrl-names = "default"; + pwms = <&gpio1 31 4000>; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + button-power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + button-reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + button-usb1 { + label = "USB1 Button"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + + button-usb2 { + label = "USB2 Button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds1 &pmx_leds2>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-3 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; + + led-11 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + + led-12 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&coherencyfab { + broken-idle; +}; + +ð1 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + hwmon@2a { + compatible = "nuvoton,nct7802"; + reg = <0x2a>; + }; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + #thermal-sensor-cells = <0>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x200000>; + read-only; + }; + + partition@200000 { + label = "certificate"; + reg = <0x0200000 0x100000>; + read-only; + }; + + partition@300000 { + label = "preset_cfg"; + reg = <0x0300000 0x100000>; + read-only; + }; + + partition@400000 { + label = "dev_params"; + reg = <0x0400000 0x100000>; + read-only; + }; + partition@500000 { + label = "active_bank"; + reg = <0x0500000 0x0100000>; + }; + + partition@600000 { + label = "magic"; + reg = <0x0600000 0x0100000>; + read-only; + }; + + partition@700000 { + label = "bank1"; + reg = <0x0700000 0x2800000>; + }; + + partition@2f00000 { + label = "bank2"; + reg = <0x2f00000 0x2800000>; + }; + + /* 0x5700000-0x5a00000 undefined in vendor firmware */ + + partition@5a00000 { + label = "reserved"; + reg = <0x5a00000 0x2000000>; + }; + + partition@7a00000 { + label = "rootfs"; + reg = <0x7a00000 0x8600000>; + }; + }; + }; +}; + +&pciec { + status = "okay"; + + pcie@1,0 { /* Renesas uPD720202 USB 3.0 controller */ + pinctrl-0 = <&pmx_pcie>; + pinctrl-names = "default"; + status = "okay"; + reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_power_cpu: pmx-power-cpu { + marvell,pins = "mpp4"; + marvell,function = "vdd"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32"; + marvell,function = "gpio"; + }; + + pmx_leds1: pmx-leds1 { + marvell,pins = "mpp47"; + marvell,function = "gpo"; + }; + + pmx_leds2: pmx-leds2 { + marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51", + "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58"; + marvell,function = "gpio"; + }; + + pmx_pcie: pmx-pcie { + marvell,pins = "mpp59"; + marvell,function = "gpio"; + }; + + pmx_beeper: pmx-beeper { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; +}; + +&pmsu { + pinctrl-0 = <&pmx_power_cpu>; + pinctrl-names = "default"; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + nr-ports = <2>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hdd0_temp: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; + + hdd1_temp: sata-port@1 { + reg = <1>; + #thermal-sensor-cells = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-db.dts b/arch/arm/boot/dts/marvell/armada-370-db.dts new file mode 100644 index 000000000000..a7dc4c04d10b --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-db.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada 370 evaluation board + * (DB-88F6710-BP-DDR3) + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-370.dtsi" + +/ { + model = "Marvell Armada 370 Evaluation Board"; + compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + status = "okay"; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + i2c@11000 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + audio_codec: audio-codec@4a { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; + }; + + audio-controller@30000 { + pinctrl-0 = <&i2s_pins2>; + pinctrl-names = "default"; + status = "okay"; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins1>; + pinctrl-names = "default"; + /* + * This device is disabled by default, because + * using the SD card connector requires + * changing the default CON40 connector + * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a + * different connector + * "DB-88F6710_MPP_RGMII_SD_Jumper". + */ + status = "disabled"; + /* No CD or WP GPIOs */ + broken-cd; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Armada 370 DB Audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Out Jack", + "Line", "In Jack"; + simple-audio-card,routing = + "Out Jack", "HPL", + "Out Jack", "HPR", + "AIN1L", "In Jack", + "AIN1L", "In Jack"; + status = "okay"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 0>; + }; + + codec { + sound-dai = <&audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_out>; + }; + }; + + simple-audio-card,dai-link@2 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_in>; + }; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + }; +}; + +&pciec { + status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + + +&spi0 { + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l25635e", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts new file mode 100644 index 000000000000..561195b749eb --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for D-Link DNS-327L + * + * Copyright (C) 2015, Andrew Andrianov + */ + +/* Remaining unsolved: + * There's still some unknown device on i2c address 0x13 + */ + +/dts-v1/; + +#include +#include +#include "armada-370.dtsi" + +/ { + model = "D-Link DNS-327L"; + compatible = "dlink,dns327l", + "marvell,armada370", + "marvell,armada-370-xp"; + + chosen { + stdout-path = &uart0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MiB */ + }; + + soc { + ranges = ; + + internal-regs { + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + usb@50000 { + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = < + &backup_button_pin + &power_button_pin + &reset_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < + &sata_l_amber_pin + &sata_r_amber_pin + &backup_led_pin + /* Ensure these are managed by hardware */ + &sata_l_white_pin + &sata_r_white_pin>; + + pinctrl-names = "default"; + + led-sata-r-amber { + label = "dns327l:amber:sata-r"; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-sata-l-amber { + label = "dns327l:amber:sata-l"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-backup { + label = "dns327l:white:usb"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-0 = <&xhci_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "USB3.0 Port Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + sata_r_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-0 = <&sata_r_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "SATA-R Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; + + sata_l_power: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-0 = <&sata_l_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "SATA-L Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pciec { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&pinctrl { + sata_l_white_pin: sata-l-white-pin { + marvell,pins = "mpp57"; + marvell,function = "sata0"; + }; + + sata_r_white_pin: sata-r-white-pin { + marvell,pins = "mpp55"; + marvell,function = "sata1"; + }; + + sata_r_amber_pin: sata-r-amber-pin { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + + sata_l_amber_pin: sata-l-amber-pin { + marvell,pins = "mpp53"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp61"; + marvell,function = "gpo"; + }; + + xhci_pwr_pin: xhci-pwr-pin { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + sata_r_pwr_pin: sata-r-pwr-pin { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; + + sata_l_pwr_pin: sata-l-pwr-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp60", "mpp61"; + marvell,function = "uart1"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; + + backup_button_pin: backup-button-pin { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; +}; + +/* Serial console */ +&uart0 { + status = "okay"; +}; + +/* Connected to Weltrend MCU */ +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + marvell,reg-init = <0x2 0x19 0x0 0x0077>, + <0x2 0x18 0x0 0x5747>; + }; +}; + +ð1 { + phy = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <100000>; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + /* 1.0 MiB */ + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + /* 128 KiB */ + reg = <0x100000 0x20000>; + read-only; + }; + + partition@120000 { + label = "uImage"; + /* 7 MiB */ + reg = <0x120000 0x700000>; + }; + + partition@820000 { + label = "ubifs"; + /* ~ 84 MiB */ + reg = <0x820000 0x54e0000>; + }; + + /* Hardcoded into stock bootloader */ + partition@5d00000 { + label = "failsafe-uImage"; + /* 5 MiB */ + reg = <0x5d00000 0x500000>; + }; + + partition@6200000 { + label = "failsafe-fs"; + /* 29 MiB */ + reg = <0x6200000 0x1d00000>; + }; + + partition@7f00000 { + label = "bbt"; + /* 1 MiB for BBT */ + reg = <0x7f00000 0x100000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-mirabox.dts b/arch/arm/boot/dts/marvell/armada-370-mirabox.dts new file mode 100644 index 000000000000..7c2f5a79b50d --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-mirabox.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Globalscale Mirabox + * + * Gregory CLEMENT + */ + +/dts-v1/; +#include +#include "armada-370.dtsi" + +/ { + model = "Globalscale Mirabox"; + compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + status = "okay"; + }; + timer@20300 { + clock-frequency = <600000000>; + status = "okay"; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led_pin &stat_led_pins>; + + green_pwr_led { + label = "mirabox:green:pwr"; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + blue_stat_led { + label = "mirabox:blue:stat"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + green_stat_led { + label = "mirabox:green:stat"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + crypto@90000 { + status = "okay"; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins3>; + pinctrl-names = "default"; + status = "okay"; + /* + * No CD or WP GPIOs: SDIO interface used for + * Wifi/Bluetooth chip + */ + broken-cd; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + pca9505: pca9505@25 { + compatible = "nxp,pca9505"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x25>; + }; + }; + }; + }; +}; + +&pciec { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&pinctrl { + pwr_led_pin: pwr-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; + + stat_led_pins: stat-led-pins { + marvell,pins = "mpp64", "mpp65"; + marvell,function = "gpio"; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Linux"; + reg = <0x400000 0x400000>; + }; + partition@800000 { + label = "Filesystem"; + reg = <0x800000 0x3f800000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts new file mode 100644 index 000000000000..079b37cf148a --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NETGEAR ReadyNAS 102 + * + * Copyright (C) 2013, Arnaud EBALARD + */ + +/dts-v1/; + +#include +#include +#include "armada-370.dtsi" + +/ { + model = "NETGEAR ReadyNAS 102"; + compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* RTC is provided by Intersil ISL12057 I2C RTC chip */ + rtc@10300 { + status = "disabled"; + }; + + serial@12000 { + status = "okay"; + }; + + /* eSATA interface */ + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + isl12057: rtc@68 { + compatible = "isil,isl12057"; + reg = <0x68>; + wakeup-source; + }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin + &sata1_led_pin + &sata2_led_pin + &backup_led_pin>; + pinctrl-names = "default"; + + blue-power-led { + label = "rn102:blue:pwr"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + blue-sata1-led { + label = "rn102:blue:sata1"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + blue-sata2-led { + label = "rn102:blue:sata2"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + blue-backup-led { + label = "rn102:blue:backup"; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin + &reset_button_pin + &backup_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; +}; + +&pciec { + status = "okay"; + + /* Connected to Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; +}; + +&pinctrl { + power_led_pin: power-led-pin { + marvell,pins = "mpp57"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + backup_button_pin: backup-button-pin { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + poweroff: poweroff { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts new file mode 100644 index 000000000000..d752ac1d7b58 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NETGEAR ReadyNAS 104 + * + * Copyright (C) 2013, Arnaud EBALARD + */ + +/dts-v1/; + +#include +#include +#include "armada-370.dtsi" + +/ { + model = "NETGEAR ReadyNAS 104"; + compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* RTC is provided by Intersil ISL12057 I2C RTC chip */ + rtc@10300 { + status = "disabled"; + }; + + serial@12000 { + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + isl12057: rtc@68 { + compatible = "isil,isl12057"; + reg = <0x68>; + wakeup-source; + }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + pca9554: pca9554@23 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x23>; + }; + }; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&backup_led_pin &power_led_pin>; + pinctrl-names = "default"; + + blue-backup-led { + label = "rn104:blue:backup"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue-power-led { + label = "rn104:blue:pwr"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "keep"; + }; + + blue-sata1-led { + label = "rn104:blue:sata1"; + gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-sata2-led { + label = "rn104:blue:sata2"; + gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-sata3-led { + label = "rn104:blue:sata3"; + gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-sata4-led { + label = "rn104:blue:sata4"; + gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + auxdisplay { + compatible = "hit,hd44780"; + data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>, + <&gpio1 26 GPIO_ACTIVE_HIGH>, + <&gpio1 27 GPIO_ACTIVE_HIGH>, + <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + display-height-chars = <2>; + display-width-chars = <16>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&backup_button_pin + &power_button_pin + &reset_button_pin>; + pinctrl-names = "default"; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; +}; + +&pciec { + status = "okay"; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to Marvell 88SE9215 SATA controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + +&pinctrl { + poweroff: poweroff { + marvell,pins = "mpp60"; + marvell,function = "gpio"; + }; + + backup_button_pin: backup-button-pin { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-rd.dts b/arch/arm/boot/dts/marvell/armada-370-rd.dts new file mode 100644 index 000000000000..b459a670f615 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-rd.dts @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada 370 Reference Design board + * (RD-88F6710-A1) + * + * Copied from arch/arm/boot/dts/armada-370-db.dts + * + * Copyright (C) 2013 Florian Fainelli + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include +#include +#include +#include +#include "armada-370.dtsi" + +/ { + model = "Marvell Armada 370 Reference Design"; + compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + status = "okay"; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins1>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + button { + label = "Software Button"; + linux,code = ; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 3000 1>; + pinctrl-0 = <&fan_pins>; + pinctrl-names = "default"; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + sw_led { + label = "370rd:green:sw"; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + }; + }; +}; + +&pciec { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Internal mini-PCIe connector */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; + }; + + switch: switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@5 { + reg = <5>; + ethernet = <ð1>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + interrupt-parent = <&switch>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy1: switchphy@1 { + reg = <1>; + interrupt-parent = <&switch>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy2: switchphy@2 { + reg = <2>; + interrupt-parent = <&switch>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy3: switchphy@3 { + reg = <3>; + interrupt-parent = <&switch>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; + + +&pinctrl { + fan_pins: fan-pins { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + led_pins: led-pins { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts new file mode 100644 index 000000000000..8dd242e668e6 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC). + * + * Copyright (C) 2015 Seagate + * + * Author: Vincent Donnefort + */ + +/* + * Here are some information allowing to identify the device: + * + * Product name : Seagate NAS 2-Bay + * Code name (board/PCB) : Dart 2-Bay + * Model name (case sticker) : SRPD20 + * Material desc (product spec) : STCTxxxxxxx + */ + +/dts-v1/; +#include "armada-370-seagate-nas-xbay.dtsi" + +/ { + model = "Seagate NAS 2-Bay (Dart, SRPD20)"; + compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp"; + + gpio-fan { + gpio-fan,speed-map = + < 0 3 + 950 2 + 1400 1 + 1800 0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts new file mode 100644 index 000000000000..9cb69999b1db --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC). + * + * Copyright (C) 2015 Seagate + * + * Author: Vincent Donnefort + */ + +/* + * Here are some information allowing to identify the device: + * + * Product name : Seagate NAS 4-Bay + * Code name (board/PCB) : Dart 4-Bay + * Model name (case sticker) : SRPD40 + * Material desc (product spec) : STCUxxxxxxx + */ + +/dts-v1/; +#include "armada-370-seagate-nas-xbay.dtsi" +#include + +/ { + model = "Seagate NAS 4-Bay (Dart, SRPD40)"; + compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; + + soc { + internal-regs { + ethernet@74000 { + status = "okay"; + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + i2c@11000 { + /* I2C GPIO expander (PCA9554A) */ + pca9554: pca9554@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + }; + }; + + regulators { + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA2 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; + }; + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA3 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + led-red-sata2 { + label = "dart:red:sata2"; + gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; + }; + led-red-sata3 { + label = "dart:red:sata3"; + gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; + }; + }; + + leds-ns2 { + compatible = "lacie,ns2-leds"; + + white-sata2 { + label = "dart:white:sata2"; + cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>; + slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>; + num-modes = <4>; + modes-map = ; + }; + white-sata3 { + label = "dart:white:sata3"; + cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; + slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>; + num-modes = <4>; + modes-map = ; + }; + }; + + gpio-fan { + gpio-fan,speed-map = + < 0 3 + 800 2 + 1050 1 + 1300 0>; + }; +}; + +&pciec { + /* SATA AHCI controller 88SE9170 */ + pcie@1,0 { + status = "okay"; + }; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi new file mode 100644 index 000000000000..822f10734946 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC). + * + * Copyright (C) 2015 Seagate + * + * Author: Vincent Donnefort + */ + +/* + * TODO: add support for the white SATA LEDs associated with HDD 0 and 1. + */ + +#include "armada-370.dtsi" +#include +#include + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + i2c@11000 { + status = "okay"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + + /* RTC - NXP 8563T (second source) */ + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + interrupts = <110>; + }; + /* RTC - MCP7940NT */ + rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupts = <110>; + }; + }; + }; + + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio2 0 GPIO_ACTIVE_HIGH + &gpio2 1 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-power { + label = "Power button"; + linux,code = ; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + button-backup { + label = "Backup button"; + linux,code = ; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + button-reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-white-power { + label = "dart:white:power"; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + + }; + led-red-power { + label = "dart:red:power"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + }; + led-red-sata0 { + label = "dart:red:sata0"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + led-red-sata1 { + label = "dart:red:sata1"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + }; +}; + +&pciec { + status = "okay"; + + /* USB 3.0 bridge ASM1042A */ + pcie@2,0 { + status = "okay"; + }; +}; + + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pinctrl { + pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; + pinctrl-names = "default"; + + hdd0_led_sata_pin: hdd0-led-sata-pin { + marvell,pins = "mpp48"; + marvell,function = "sata1"; + }; + hdd0_led_gpio_pin: hdd0-led-gpio-pin { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + hdd1_led_sata_pin: hdd1-led-sata-pin { + marvell,pins = "mpp57"; + marvell,function = "sata0"; + }; + hdd1_led_gpio_pin: hdd1-led-gpio-pin { + marvell,pins = "mpp57"; + marvell,function = "gpio"; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x300000>; + }; + partition@300000 { + label = "device-tree"; + reg = <0x300000 0x20000>; + }; + partition@320000 { + label = "linux"; + reg = <0x320000 0x2000000>; + }; + partition@2320000 { + label = "rootfs"; + reg = <0x2320000 0xdce0000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts new file mode 100644 index 000000000000..5ee572dc9242 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC). + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + */ + +/* + * Here are some information allowing to identify the device: + * + * Product name : Seagate Personal Cloud 2-Bay + * Code name (board/PCB) : Cumulus Max + * Model name (case sticker) : SRN22C + * Material desc (product spec) : STCSxxxxxxx + */ + +/dts-v1/; +#include "armada-370-seagate-personal-cloud.dtsi" + +/ { + model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)"; + compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp"; + + soc { + internal-regs { + sata@a0000 { + status = "okay"; + nr-ports = <2>; + }; + }; + }; + + regulators { + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts new file mode 100644 index 000000000000..578b54b39c8f --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC). + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + */ + +/* + * Here are some information allowing to identify the device: + * + * Product name : Seagate Personal Cloud + * Code name (board/PCB) : Cumulus + * Model name (case sticker) : SRN21C + * Material desc (product spec) : STCRxxxxxxx + */ + +/dts-v1/; +#include "armada-370-seagate-personal-cloud.dtsi" + +/ { + model = "Seagate Personal Cloud (Cumulus, SRN21C)"; + compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp"; + + soc { + internal-regs { + sata@a0000 { + status = "okay"; + nr-ports = <1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi new file mode 100644 index 000000000000..124a8ba279e3 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay + * (Armada 370 SoC). + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + */ + +/* + * TODO: add support for the white SATA LED. + */ + +#include "armada-370.dtsi" +#include +#include + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + coherency-fabric@20200 { + broken-idle; + }; + + serial@12000 { + status = "okay"; + }; + + ethernet@74000 { + status = "okay"; + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-power { + label = "Power button"; + linux,code = ; + gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + debounce-interval = <100>; + }; + button-reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + button-usb { + label = "USB VBUS error"; + linux,code = ; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-red-sata0 { + label = "cumulus:red:sata0"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + }; +}; + +&pciec { + status = "okay"; + + /* USB 3.0 Bridge ASM1042A */ + pcie@1,0 { + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pinctrl { + pinctrl-0 = <&sata_led_pin>; + pinctrl-names = "default"; + + sata_led_pin: sata-led-pin { + marvell,pins = "mpp60"; + marvell,function = "sata0"; + }; + gpio_led_pin: gpio-led-pin { + marvell,pins = "mpp60"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + /* MX25L8006E */ + compatible = "mxicy,mx25l8005", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts new file mode 100644 index 000000000000..f0893cc06607 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Synology DS213j + * + * Copyright (C) 2014, Arnaud EBALARD + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include +#include +#include "armada-370.dtsi" + +/ { + model = "Synology DS213j"; + compatible = "synology,ds213j", "marvell,armada370", + "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* RTC provided by Seiko S-35390A I2C RTC chip below */ + rtc@10300 { + status = "disabled"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + /* Main device RTC chip */ + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB */ + serial@12000 { + status = "okay"; + }; + + /* Connected to a TI MSP430F2111 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* rear USB port, near reset button */ + usb@50000 { + status = "okay"; + }; + + /* rear USB port, near RJ45 port */ + usb@51000 { + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + }; + }; + + gpio-fan-32-38 { + status = "okay"; + compatible = "gpio-fan"; + pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin + &fan_ctrl_high_pin &fan_alarm_pin>; + pinctrl-names = "default"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH + &gpio2 0 GPIO_ACTIVE_HIGH + &gpio2 1 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 1000 1 + 1150 2 + 1350 4 + 1500 3 + 1650 5 + 1750 6 + 1900 7 >; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&disk1_led_pin + &disk2_led_pin>; + pinctrl-names = "default"; + + disk1-led-amber { + label = "synology:amber:disk1"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + disk2-led-amber { + label = "synology:amber:disk2"; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + +&pinctrl { + disk1_led_pin: disk1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + disk2_led_pin: disk2-led-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp60"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp55"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp57"; + marvell,function = "gpio"; + }; + + syno_id_bit3_pin: syno-id-bit3-pin { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + + fan_ctrl_low_pin: fan-ctrl-low-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; + + fan_ctrl_mid_pin: fan-ctrl-mid-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; + + fan_ctrl_high_pin: fan-ctrl-high-pin { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; + + fan_alarm_pin: fan-alarm-pin { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@0 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000c0000>; /* 768KB */ + }; + + partition@c0000 { /* uImage */ + label = "zImage"; + reg = <0x000c0000 0x002d0000>; /* 2880KB */ + }; + + partition@390000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x00390000 0x00440000>; /* 4250KB */ + }; + + partition@7d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@7e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@7f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi new file mode 100644 index 000000000000..0b8c2a64b36f --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 370 and Armada XP SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * Ben Dooks + * + * This file contains the definitions that are common to the Armada + * 370 and Armada XP SoC. + */ + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 370 and XP SoC"; + compatible = "marvell,armada-370-xp"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "marvell,sheeva-v7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&mpic>; + pcie-mem-aperture = <0xf8000000 0x7e00000>; + pcie-io-aperture = <0xffe00000 0x100000>; + + devbus_bootcs: devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs0: devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs1: devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs2: devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs3: devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + rtc: rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <50>; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <41>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <42>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + }; + + coredivclk: corediv-clock@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + }; + + coherencyfab: coherency-fabric@20200 { + compatible = "marvell,coherency-fabric"; + reg = <0x20200 0xb0>, <0x21010 0x1c>; + }; + + timer: timer@20300 { + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts = <37>, <38>, <39>, <40>, <5>, <6>; + }; + + watchdog: watchdog@20300 { + reg = <0x20300 0x34>, <0x20704 0x4>; + }; + + cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x8>; + }; + + pmsu: pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; + }; + + usb0: usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = <45>; + status = "disabled"; + }; + + usb1: usb@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x500>; + interrupts = <46>; + status = "disabled"; + }; + + eth0: ethernet@70000 { + reg = <0x70000 0x4000>; + interrupts = <8>; + clocks = <&gateclk 4>; + status = "disabled"; + }; + + mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + clocks = <&gateclk 4>; + }; + + eth1: ethernet@74000 { + reg = <0x74000 0x4000>; + interrupts = <10>; + clocks = <&gateclk 3>; + status = "disabled"; + }; + + sata: sata@a0000 { + compatible = "marvell,armada-370-sata"; + reg = <0xa0000 0x5000>; + interrupts = <55>; + clocks = <&gateclk 15>, <&gateclk 30>; + clock-names = "0", "1"; + status = "disabled"; + }; + + nand_controller: nand-controller@d0000 { + compatible = "marvell,armada370-nand-controller"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <113>; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + sdio: mvsdio@d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd4000 0x200>; + interrupts = <54>; + clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; + + spi0: spi@10600 { + reg = , /* control */ + , /* CS0 */ + , /* CS1 */ + , /* CS2 */ + , /* CS3 */ + , /* CS4 */ + , /* CS5 */ + , /* CS6 */ + ; /* CS7 */ + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + reg = , /* control */ + , /* CS0 */ + , /* CS1 */ + , /* CS2 */ + , /* CS3 */ + , /* CS4 */ + , /* CS5 */ + , /* CS6 */ + ; /* CS7 */ + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; + }; diff --git a/arch/arm/boot/dts/marvell/armada-370.dtsi b/arch/arm/boot/dts/marvell/armada-370.dtsi new file mode 100644 index 000000000000..2013a5ccecd3 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-370.dtsi @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 370 family SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * Contains definitions specific to the Armada 370 SoC that are not + * common to all Armada SoCs. + */ + +#include "armada-370-xp.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Marvell Armada 370 family SoC"; + compatible = "marvell,armada370", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + soc { + compatible = "marvell,armada370-mbus", "simple-bus"; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + pciec: pcie@82000000 { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie2: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + internal-regs { + L2: l2-cache@8000 { + compatible = "marvell,aurora-outer-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; + cache-level = <2>; + cache-unified; + wt-override; + }; + + gpio0: gpio@18100 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <91>; + }; + + + systemc: system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-370-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18230 { + compatible = "marvell,armada-370-core-clock"; + reg = <0x18230 0x08>; + #clock-cells = <1>; + }; + + thermal: thermal@18300 { + compatible = "marvell,armada370-thermal"; + reg = <0x18300 0x4 + 0x18304 0x4>; + status = "okay"; + }; + + sscg: sscg@18330 { + reg = <0x18330 0x4>; + }; + + cpuconf: cpu-config@21000 { + compatible = "marvell,armada-370-cpu-config"; + reg = <0x21000 0x8>; + }; + + audio_controller: audio-controller@30000 { + #sound-dai-cells = <1>; + compatible = "marvell,armada370-audio"; + reg = <0x30000 0x4000>; + interrupts = <93>; + clocks = <&gateclk 0>; + clock-names = "internal"; + status = "disabled"; + }; + + xor0: xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + status = "okay"; + + xor00 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor1: xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor10 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + cesa: crypto@90000 { + compatible = "marvell,armada-370-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <48>; + clocks = <&gateclk 23>; + clock-names = "cesa0"; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x7e0>; + }; + }; + + crypto_sram: sa-sram { + compatible = "mmio-sram"; + reg = ; + reg-names = "sram"; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; + + /* + * The Armada 370 has an erratum preventing the use of + * the standard workflow for CPU idle support (relying + * on the BootROM code to enter/exit idle state). + * Reserve some amount of the crypto SRAM to put the + * cpuidle workaround. + */ + idle-sram@0 { + reg = <0x0 0x20>; + }; + }; + }; +}; + +/* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used. + */ + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + reg = <0x11000 0x20>; +}; + +&i2c1 { + reg = <0x11100 0x20>; +}; + +&mpic { + reg = <0x20a00 0x1d0>, <0x21870 0x58>; +}; + +&timer { + compatible = "marvell,armada-370-timer"; + clocks = <&coreclk 2>; +}; + +&watchdog { + compatible = "marvell,armada-370-wdt"; + clocks = <&coreclk 2>; +}; + +&usb0 { + clocks = <&coreclk 0>; +}; + +&usb1 { + clocks = <&coreclk 0>; +}; + +ð0 { + compatible = "marvell,armada-370-neta"; +}; + +ð1 { + compatible = "marvell,armada-370-neta"; +}; + +&pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + + spi0_pins1: spi0-pins1 { + marvell,pins = "mpp33", "mpp34", + "mpp35", "mpp36"; + marvell,function = "spi0"; + }; + + spi0_pins2: spi0_pins2 { + marvell,pins = "mpp32", "mpp63", + "mpp64", "mpp65"; + marvell,function = "spi0"; + }; + + spi1_pins: spi1-pins { + marvell,pins = "mpp49", "mpp50", + "mpp51", "mpp52"; + marvell,function = "spi1"; + }; + + uart0_pins: uart0-pins { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "uart0"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp41", "mpp42"; + marvell,function = "uart1"; + }; + + sdio_pins1: sdio-pins1 { + marvell,pins = "mpp9", "mpp11", "mpp12", + "mpp13", "mpp14", "mpp15"; + marvell,function = "sd0"; + }; + + sdio_pins2: sdio-pins2 { + marvell,pins = "mpp47", "mpp48", "mpp49", + "mpp50", "mpp51", "mpp52"; + marvell,function = "sd0"; + }; + + sdio_pins3: sdio-pins3 { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp51", "mpp52", "mpp53"; + marvell,function = "sd0"; + }; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + i2s_pins1: i2s-pins1 { + marvell,pins = "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", + "mpp12", "mpp13"; + marvell,function = "audio"; + }; + + i2s_pins2: i2s-pins2 { + marvell,pins = "mpp49", "mpp47", "mpp50", + "mpp59", "mpp57", "mpp61", + "mpp62", "mpp60", "mpp58"; + marvell,function = "audio"; + }; + + mdio_pins: mdio-pins { + marvell,pins = "mpp17", "mpp18"; + marvell,function = "ge"; + }; + + ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", "mpp12", + "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27", "mpp28", "mpp29", "mpp30"; + marvell,function = "ge1"; + }; +}; + +/* + * Default SPI pinctrl setting, can be overwritten on + * board level if a different configuration is used. + */ +&spi0 { + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins1>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-375-db.dts b/arch/arm/boot/dts/marvell/armada-375-db.dts new file mode 100644 index 000000000000..4c4092790a20 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-375-db.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada 375 evaluation board + * (DB-88F6720) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + */ + +/dts-v1/; +#include +#include "armada-375.dtsi" + +/ { + model = "Marvell Armada 375 Development Board"; + compatible = "marvell,a375-db", "marvell,armada375"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + }; +}; +&pciec { + status = "okay"; +}; + +/* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ +&pcie0 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&pcie1 { + /* Port 1, Lane 0 */ + status = "okay"; +}; + + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + + /* + * SPI conflicts with NAND, so we disable it here, and + * select NAND as the enabled device by default. + */ + + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + sdio_st_pins: sdio-st-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&nand_controller { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&sdio { + pinctrl-0 = <&sdio_pins &sdio_st_pins>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +ðernet { + status = "okay"; +}; + + +ð0 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +ð1 { + status = "okay"; + phy = <&phy3>; + phy-mode = "gmii"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-375.dtsi b/arch/arm/boot/dts/marvell/armada-375.dtsi new file mode 100644 index 000000000000..ddc49547d786 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-375.dtsi @@ -0,0 +1,645 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 375 family SoC + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + */ + +#include +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Marvell Armada 375 family SoC"; + compatible = "marvell,armada375"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + serial0 = &uart0; + serial1 = &uart1; + }; + + clocks { + /* 1 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-375-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + + soc { + compatible = "marvell,armada375-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + devbus_bootcs: devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs0: devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs1: devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs2: devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs3: devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <0>; + prefetch-data = <1>; + }; + + scu: scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + + timer0: timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + mdio: mdio@c0054 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0xc0054 0x4>; + clocks = <&gateclk 19>; + }; + + /* Network controller */ + ethernet: ethernet@f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,armada-375-pp2"; + reg = <0xf0000 0xa000>, /* Packet Processor regs */ + <0xc0000 0x3060>, /* LMS regs */ + <0xc4000 0x100>, /* eth0 regs */ + <0xc5000 0x100>; /* eth1 regs */ + clocks = <&gateclk 3>, <&gateclk 19>; + clock-names = "pp_clk", "gop_clk"; + status = "disabled"; + + eth0: ethernet-port@0 { + interrupts = ; + reg = <0>; + port-id = <0>; /* For backward compatibility. */ + status = "disabled"; + }; + + eth1: ethernet-port@1 { + interrupts = ; + reg = <1>; + port-id = <1>; /* For backward compatibility. */ + status = "disabled"; + }; + }; + + rtc: rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = ; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-375-spi", + "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-375-spi", + "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl: pinctrl@18000 { + compatible = "marvell,mv88f6720-pinctrl"; + reg = <0x18000 0x24>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp61", "mpp62"; + marvell,function = "i2c1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp0", "mpp1", "mpp2", + "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13"; + marvell,function = "nand"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp24", "mpp25", "mpp26", + "mpp27", "mpp28", "mpp29"; + marvell,function = "sd"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp0", "mpp1", "mpp4", + "mpp5", "mpp8", "mpp9"; + marvell,function = "spi0"; + }; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + systemc: system-controller@18200 { + compatible = "marvell,armada-375-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-375-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + usbcluster: usb-cluster@18400 { + compatible = "marvell,armada-375-usb-cluster"; + reg = <0x18400 0x4>; + #phy-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer1: timer@20300 { + compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + watchdog: watchdog@20300 { + compatible = "marvell,armada-375-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + coherencyfab: coherency-fabric@21010 { + compatible = "marvell,armada-375-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + + usb0: usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = ; + clocks = <&gateclk 18>; + phys = <&usbcluster PHY_TYPE_USB2>; + phy-names = "usb"; + status = "disabled"; + }; + + usb1: usb@54000 { + compatible = "marvell,orion-ehci"; + reg = <0x54000 0x500>; + interrupts = ; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + usb2: usb@58000 { + compatible = "marvell,armada-375-xhci"; + reg = <0x58000 0x20000>,<0x5b880 0x80>; + interrupts = ; + clocks = <&gateclk 16>; + phys = <&usbcluster PHY_TYPE_USB3>; + phy-names = "usb"; + status = "disabled"; + }; + + xor0: xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor1: xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 23>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + cesa: crypto@90000 { + compatible = "marvell,armada-375-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = , + ; + clocks = <&gateclk 30>, <&gateclk 31>, + <&gateclk 28>, <&gateclk 29>; + clock-names = "cesa0", "cesa1", + "cesaz0", "cesaz1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + + sata: sata@a0000 { + compatible = "marvell,armada-370-sata"; + reg = <0xa0000 0x5000>; + interrupts = ; + clocks = <&gateclk 14>, <&gateclk 20>; + clock-names = "0", "1"; + status = "disabled"; + }; + + nand_controller: nand-controller@d0000 { + compatible = "marvell,armada370-nand-controller"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + sdio: mvsdio@d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd4000 0x200>; + interrupts = ; + clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + + thermal: thermal@e8078 { + compatible = "marvell,armada375-thermal"; + reg = <0xe8078 0x4>, <0xe807c 0x8>; + status = "okay"; + }; + + coreclk: mvebu-sar@e8204 { + compatible = "marvell,armada-375-core-clock"; + reg = <0xe8204 0x04>; + #clock-cells = <1>; + }; + + coredivclk: corediv-clock@e8250 { + compatible = "marvell,armada-375-corediv-clock"; + reg = <0xe8250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + pciec: pcie@82000000 { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 30>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 31>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi new file mode 100644 index 000000000000..e94f22b0e9b5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-380.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 380 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 380 family SoC"; + compatible = "marvell,armada380"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6810-pinctrl"; + }; + }; + + pcie { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + + /* x1 port */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts new file mode 100644 index 000000000000..f4c4b213ef4e --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Marcel Ziswiler */ + +/dts-v1/; +#include "armada-385.dtsi" +#include +#include + +/ { + model = "Netgear GS110EMX"; + compatible = "netgear,gs110emx", "marvell,armada380"; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&front_button_pins>; + pinctrl-names = "default"; + + key-factory-default { + label = "Factory Default"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; /* 128 MB */ + }; + + soc { + ranges = ; + + internal-regs { + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" + * twice in u-boot. + */ + status = "okay"; + }; + }; + }; +}; + +ð0 { + /* ethernet@70000 */ + bm,pool-long = <0>; + bm,pool-short = <1>; + buffer-manager = <&bm>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + + fixed-link { + full-duplex; + pause; + speed = <1000>; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&switch_interrupt_pins>; + pinctrl-names = "default"; + #size-cells = <0>; + reg = <0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy1: switch0phy1@1 { + reg = <0x1>; + }; + + switch0phy2: switch0phy2@2 { + reg = <0x2>; + }; + + switch0phy3: switch0phy3@3 { + reg = <0x3>; + }; + + switch0phy4: switch0phy4@4 { + reg = <0x4>; + }; + + switch0phy5: switch0phy5@5 { + reg = <0x5>; + }; + + switch0phy6: switch0phy6@6 { + reg = <0x6>; + }; + + switch0phy7: switch0phy7@7 { + reg = <0x7>; + }; + + switch0phy8: switch0phy8@8 { + reg = <0x8>; + }; + }; + + mdio-external { + compatible = "marvell,mv88e6xxx-mdio-external"; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@b { + reg = <0xb>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + phy2: ethernet-phy@c { + reg = <0xc>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + ethernet = <ð0>; + phy-mode = "rgmii"; + reg = <0>; + + fixed-link { + full-duplex; + pause; + speed = <1000>; + }; + }; + + port@1 { + label = "lan1"; + phy-handle = <&switch0phy1>; + reg = <1>; + }; + + port@2 { + label = "lan2"; + phy-handle = <&switch0phy2>; + reg = <2>; + }; + + port@3 { + label = "lan3"; + phy-handle = <&switch0phy3>; + reg = <3>; + }; + + port@4 { + label = "lan4"; + phy-handle = <&switch0phy4>; + reg = <4>; + }; + + port@5 { + label = "lan5"; + phy-handle = <&switch0phy5>; + reg = <5>; + }; + + port@6 { + label = "lan6"; + phy-handle = <&switch0phy6>; + reg = <6>; + }; + + port@7 { + label = "lan7"; + phy-handle = <&switch0phy7>; + reg = <7>; + }; + + port@8 { + label = "lan8"; + phy-handle = <&switch0phy8>; + reg = <8>; + }; + + port@9 { + /* 88X3310P external phy */ + label = "lan9"; + phy-handle = <&phy1>; + phy-mode = "xaui"; + reg = <9>; + }; + + port@a { + /* 88X3310P external phy */ + label = "lan10"; + phy-handle = <&phy2>; + phy-mode = "xaui"; + reg = <0xa>; + }; + }; + }; +}; + +&pinctrl { + front_button_pins: front-button-pins { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + switch_interrupt_pins: switch-interrupt-pins { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + read-only; + reg = <0x00000000 0x00100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x00100000 0x00010000>; + }; + + partition@200000 { + label = "rsv"; + reg = <0x00110000 0x00010000>; + }; + + partition@300000 { + label = "image0"; + reg = <0x00120000 0x00900000>; + }; + + partition@400000 { + label = "config"; + reg = <0x00a20000 0x00300000>; + }; + + partition@480000 { + label = "debug"; + reg = <0x00d20000 0x002e0000>; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts new file mode 100644 index 000000000000..584f0d0398a5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 382 reference board + * (RD-AC3X-48G4X2XL) + * + * Copyright (C) 2020 Allied Telesis Labs + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "Marvell Armada 382 RD-AC3X"; + compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x", + "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MB */ + }; + + soc { + ranges = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@53{ + compatible = "atmel,24c64"; + reg = <0x53>; + }; + + /* CPLD device present at 0x3c. Function unknown */ +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +ð1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x00500000>; + label = "u-boot"; + }; + partition@500000{ + reg = <0x00500000 0x00400000>; + label = "u-boot env"; + }; + partition@900000{ + reg = <0x00900000 0x3F700000>; + label = "user"; + }; + }; + }; +}; + +&refclk { + clock-frequency = <200000000>; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts new file mode 100644 index 000000000000..5a9ab8410b7b --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board. + (x530/AT-GS980MX) + * + Copyright (C) 2020 Allied Telesis Labs + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "x530/AT-GS980MX"; + compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c0: i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + }; + + uart0: serial@12000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <400000>; +}; + +&pcie2 { + status = "okay"; +}; + +&devbus_cs1 { + compatible = "marvell,mvebu-devbus"; + status = "okay"; + + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + nvs@0 { + status = "okay"; + + compatible = "mtd-ram"; + reg = <0 0x00080000>; + bank-width = <1>; + label = "nvs"; + }; +}; + +&pinctrl { + i2c0_gpio_pins: i2c-gpio-pins-0 { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "gpio"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + i2c0mux: mux@71 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9544"; + reg = <0x71>; + i2c-mux-idle-disconnect; + + i2c@0 { /* POE devices MUX */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + adt7476_2e: hwmon@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + adt7476_2d: hwmon@2d { + compatible = "adi,adt7476"; + reg = <0x2d>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + rtc@68 { + compatible = "dallas,ds1340"; + reg = <0x68>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + gpio@20 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + }; +}; + +&usb0 { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <1>; /* Chip select 1 */ + spi-max-frequency = <54000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@100000 { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + partition@140000 { + reg = <0x00140000 0x00e80000>; + label = "unused"; + }; + partition@fc0000 { + reg = <0x00fc0000 0x00040000>; + label = "idprom"; + }; + }; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + marvell,nand-enable-arbiter; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x0f000000>; + label = "user"; + }; + partition@f000000 { + /* Maximum mtdoops size is 8MB, so set to that. */ + reg = <0x0f000000 0x00800000>; + label = "errlog"; + }; + partition@f800000 { + reg = <0x0f800000 0x00800000>; + label = "nand-bbt"; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts new file mode 100644 index 000000000000..1990f7d0cc79 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "armada-385-clearfog-gtr.dtsi" + +/ { + model = "SolidRun Clearfog GTR L8"; +}; + +&mdio { + switch0: switch0@4 { + compatible = "marvell,mv88e6190"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cf_gtr_switch_reset_pins>; + reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan8"; + phy-handle = <&switch0phy0>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <&switch0phy1>; + }; + + port@3 { + reg = <3>; + label = "lan6"; + phy-handle = <&switch0phy2>; + }; + + port@4 { + reg = <4>; + label = "lan5"; + phy-handle = <&switch0phy3>; + }; + + port@5 { + reg = <5>; + label = "lan4"; + phy-handle = <&switch0phy4>; + }; + + port@6 { + reg = <6>; + label = "lan3"; + phy-handle = <&switch0phy5>; + }; + + port@7 { + reg = <7>; + label = "lan2"; + phy-handle = <&switch0phy6>; + }; + + port@8 { + reg = <8>; + label = "lan1"; + phy-handle = <&switch0phy7>; + }; + + port@10 { + reg = <10>; + phy-mode = "2500base-x"; + + ethernet = <ð1>; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: switch0phy0@1 { + reg = <0x1>; + }; + + switch0phy1: switch0phy1@2 { + reg = <0x2>; + }; + + switch0phy2: switch0phy2@3 { + reg = <0x3>; + }; + + switch0phy3: switch0phy3@4 { + reg = <0x4>; + }; + + switch0phy4: switch0phy4@5 { + reg = <0x5>; + }; + + switch0phy5: switch0phy5@6 { + reg = <0x6>; + }; + + switch0phy6: switch0phy6@7 { + reg = <0x7>; + }; + + switch0phy7: switch0phy7@8 { + reg = <0x8>; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts new file mode 100644 index 000000000000..b795ad573891 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "armada-385-clearfog-gtr.dtsi" + +/ { + model = "SolidRun Clearfog GTR S4"; +}; + +&sfp0 { + tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; +}; + +&mdio { + switch0: switch0@4 { + compatible = "marvell,mv88e6085"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cf_gtr_switch_reset_pins>; + reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan2"; + phy-handle = <&switch0phy0>; + }; + + port@2 { + reg = <2>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; + + port@3 { + reg = <3>; + label = "lan4"; + phy-handle = <&switch0phy2>; + }; + + port@4 { + reg = <4>; + label = "lan3"; + phy-handle = <&switch0phy3>; + }; + + port@5 { + reg = <5>; + phy-mode = "2500base-x"; + ethernet = <ð1>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: switch0phy0@11 { + reg = <0x11>; + }; + + switch0phy1: switch0phy1@12 { + reg = <0x12>; + }; + + switch0phy2: switch0phy2@13 { + reg = <0x13>; + }; + + switch0phy3: switch0phy3@14 { + reg = <0x14>; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi new file mode 100644 index 000000000000..d1452a04e904 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825) + * + * Rabeeh Khoury , based on Russell King clearfog work + */ + +/* + SERDES mapping - + 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0 + 1. 6141 switch (2.5Gbps capable) + 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1 + 3. USB 3.0 Host + 4. mini PCIe CON2 - PCIe2 + 5. SFP connector, or optionally SGMII Ethernet 1512 PHY + + USB 2.0 mapping - + 0. USB 2.0 - 0 USB pins header CON12 + 1. USB 2.0 - 1 mini PCIe CON2 + 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3) + + Pin mapping - + 0,1 - console UART + 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors, + front panel and PSE controller + 4,5 - MDC/MDIO + 6..17 - RGMII + 18 - Topaz switch reset (active low) + 19 - 1512 phy reset + 20 - 1512 phy reset (eth2, optional) + 21,28,37,38,39,40 - SD0 + 22 - USB 3.0 current limiter enable (active high) + 24 - SFP TX fault (input active high) + 25 - SFP present (input active low) + 26,27 - I2C1 - connected to SFP + 29 - Fan PWM + 30 - CON4 mini PCIe wifi disable + 31 - CON3 mini PCIe wifi disable + 32 - Fuse programming power toggle (1.8v) + 33 - CON4 mini PCIe reset + 34 - CON2 mini PCIe wifi disable + 35 - CON3 mini PCIe reset + 36 - Rear button (GPIO active low) + 41 - CON1 front panel connector + 42 - Front LED1, or front panel CON1 + 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS + 44 - CON2 mini PCIe reset + 45 - TPM PIRQ signal, or front panel CON1 + 46 - SFP TX disable + 47 - Control isolation of boot sensitive SAR signals + 48 - PSE reset + 49 - PSE OSS signal + 50 - PSE interrupt + 52 - Front LED2, or front panel + 53 - Front button + 54 - SFP LOS (input active high) + 55 - Fan sense + 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM + 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable) +*/ + +/dts-v1/; +#include +#include +#include +#include "armada-385.dtsi" + +/ { + compatible = "marvell,armada385", "marvell,armada380"; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + ethernet2 = ð1; + ethernet3 = ð2; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + v_usb3_con: regulator-v-usb3-con { + compatible = "regulator-fixed"; + gpio = <&gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cf_gtr_usb3_con_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb3_con"; + vin-supply = <®_5p0v>; + regulator-boot-on; + regulator-always-on; + }; + + soc { + ranges = ; + + internal-regs { + + rtc@a3800 { + status = "okay"; + }; + + i2c@11000 { /* ROM, temp sensor and front panel */ + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + i2c@11100 { /* SFP (CON5/CON6) */ + pinctrl-0 = <&cf_gtr_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + pinctrl@18000 { + cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + cf_gtr_fan_pwm: cf-gtr-fan-pwm { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + cf_gtr_i2c1_pins: i2c1-pins { + /* SFP */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + + cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + + cf_gtr_isolation_pins: cf-gtr-isolation-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + cf_gtr_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp59"; + marvell,function = "spi1"; + }; + + cf_gtr_front_button_pins: cf-gtr-front-button-pins { + marvell,pins = "mpp53"; + marvell,function = "gpio"; + }; + + cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + }; + + sdhci@d8000 { + bus-width = <4>; + no-1-8-v; + non-removable; + pinctrl-0 = <&cf_gtr_sdhci_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + usb@58000 { + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + vbus-supply = <&v_usb3_con>; + status = "okay"; + }; + }; + + pcie { + status = "okay"; + /* + * The PCIe units are accessible through + * the mini-PCIe connectors on the board. + */ + pcie@1,0 { + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + pcie@2,0 { + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + pcie@3,0 { + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + }; + + sfp0: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>; + pinctrl-names = "default"; + + button-0 { + label = "Rear Button"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + + button-1 { + label = "Front Button"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + function = LED_FUNCTION_CPU; + color = ; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + led2 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +ð0 { + /* ethernet@70000 */ + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy_dedicated>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + status = "okay"; +}; + +ð1 { + /* ethernet@30000 */ + bm,pool-long = <2>; + bm,pool-short = <1>; + buffer-manager = <&bm>; + phys = <&comphy1 1>; + phy-mode = "2500base-x"; + status = "okay"; + + fixed-link { + speed = <2500>; + full-duplex; + }; +}; + +ð2 { + /* ethernet@34000 */ + bm,pool-long = <3>; + bm,pool-short = <1>; + buffer-manager = <&bm>; + managed = "in-band-status"; + phys = <&comphy5 1>; + phy-mode = "sgmii"; + sfp = <&sfp0>; + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + phy_dedicated: ethernet-phy@0 { + /* + * Annoyingly, the marvell phy driver configures the LED + * register, rather than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x1017>; + reg = <0>; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi1 { + /* + * CS0: W25Q32 flash + */ + pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "okay"; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* U26 temperature sensor placed near SoC */ + temp1: nct75@4c { + compatible = "lm75"; + reg = <0x4c>; + }; + + /* U27 temperature sensor placed near RTC battery */ + temp2: nct75@4d { + compatible = "lm75"; + reg = <0x4d>; + }; + + /* 2Kb eeprom */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; +}; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-names = "default"; + + wifi-disable { + gpio-hog; + gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; + output-low; + line-name = "wifi-disable"; + }; +}; + +&gpio1 { + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-names = "default"; + + lte-disable { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "lte-disable"; + }; + + /* + * This signal, when asserted, isolates Armada 38x sample at reset pins + * from control of external devices. Should be de-asserted after reset. + */ + sar-isolation { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-low; + line-name = "sar-isolation"; + }; + + poe-reset { + gpio-hog; + gpios = <16 GPIO_ACTIVE_LOW>; + output-low; + line-name = "poe-reset"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts new file mode 100644 index 000000000000..389d9c75d546 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 385 AMC board + * (DB-88F6820-AMC) + * + * Copyright (C) 2017 Allied Telesis Labs + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "Marvell Armada 385 AMC"; + compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + spi1 = &spi1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2GB */ + }; + + soc { + ranges = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&uart0 { + /* + * Exported on the micro USB connector CON3 + * through an FTDI + */ + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + + +ð0 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +ð2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; +}; + +&usb0 { + status = "okay"; +}; + + + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@0 { + reg = <0>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x40000000>; + label = "user"; + }; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@100000 { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + }; + }; +}; + +&refclk { + clock-frequency = <20000000>; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-db-ap.dts b/arch/arm/boot/dts/marvell/armada-385-db-ap.dts new file mode 100644 index 000000000000..332f8fce77dc --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-db-ap.dts @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 385 Access Point Development board + * (DB-88F6820-AP) + * + * Copyright (C) 2014 Marvell + * + * Nadav Haklai + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "Marvell Armada 385 Access Point Development Board"; + compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c0: i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + /* + * This bus is wired to two EEPROM + * sockets, one of which holding the + * board ID used by the bootloader. + * Erasing this EEPROM's content will + * brick the board. + * Use this bus with caution. + */ + }; + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@4 { + reg = <4>; + }; + + phy2: ethernet-phy@6 { + reg = <6>; + }; + }; + + /* UART0 is exposed through the JP8 connector */ + uart0: serial@12000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + + /* + * UART1 is exposed through a FTDI chip + * wired to the mini-USB connector + */ + uart1: serial@12100 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + + pinctrl@18000 { + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + + /* CON3 */ + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + bm,pool-short = <3>; + }; + + /* CON2 */ + ethernet@34000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + }; + + usb@58000 { + status = "okay"; + }; + + /* CON4 */ + ethernet@70000 { + pinctrl-names = "default"; + + /* + * The Reference Clock 0 is used to + * provide a clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <3>; + }; + + bm@c8000 { + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; + }; + + bm-bppi { + status = "okay"; + }; + + pcie { + status = "okay"; + + /* + * The three PCIe units are accessible through + * standard mini-PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + #phy-cells = <0>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <54000000>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00800000>; + read-only; + }; + + partition@800000 { + label = "uImage"; + reg = <0x00800000 0x00400000>; + read-only; + }; + + partition@c00000 { + label = "Root"; + reg = <0x00c00000 0x3f400000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts new file mode 100644 index 000000000000..88b2921fed55 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree include for the Linksys WRT1200AC (Caiman) + * + * Copyright (C) 2015 Imre Kaloz + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1200AC"; + compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; +}; + +&expander0 { + wan_amber@0 { + label = "caiman:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "caiman:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "caiman:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "caiman:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "caiman:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "caiman:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "caiman:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "caiman:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "caiman:amber:wps"; + reg = <0x9>; + }; +}; + +&gpio_leds { + led-power { + label = "caiman:white:power"; + }; + + led-sata { + label = "caiman:white:sata"; + }; +}; + +&nand { + /* 128MiB */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KiB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MiB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MiB */ + }; + + /* + * 38MiB, last MiB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MiB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts new file mode 100644 index 000000000000..88200f930d0d --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Linksys WRT1900ACv2 (Cobra) + * + * Copyright (C) 2015 Imre Kaloz + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1900ACv2"; + compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; +}; + +&expander0 { + wan_amber@0 { + label = "cobra:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "cobra:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "cobra:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "cobra:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "cobra:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "cobra:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "cobra:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "cobra:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "cobra:amber:wps"; + reg = <0x9>; + }; +}; + +&gpio_leds { + led-power { + label = "cobra:white:power"; + }; + + led-sata { + label = "cobra:white:sata"; + }; +}; + +&nand { + /* 128MiB */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KiB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MiB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MiB */ + }; + + /* + * 38MiB, last MiB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MiB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts new file mode 100644 index 000000000000..4ab45f294de2 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Linksys WRT3200ACM (Rango) + * + * Copyright (C) 2016 Imre Kaloz + */ + +/dts-v1/; +#include +#include +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT3200ACM"; + compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; +}; + +&expander0 { + wan_amber@0 { + label = "rango:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "rango:white:wan"; + reg = <0x1>; + }; + + usb2@5 { + label = "rango:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "rango:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "rango:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "rango:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "rango:amber:wps"; + reg = <0x9>; + }; +}; + +&gpio_leds { + led-power { + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + label = "rango:white:power"; + }; + + led-sata { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "rango:white:sata"; + }; + + led-wlan_2g { + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + label = "rango:white:wlan_2g"; + }; + + led-wlan_5g { + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + label = "rango:white:wlan_5g"; + }; +}; + +&gpio_leds_pins { + marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; +}; + +&nand { + /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@200000 { + label = "u_env"; + reg = <0x200000 0x20000>; /* 128KiB */ + }; + + partition@220000 { + label = "s_env"; + reg = <0x220000 0x40000>; /* 256KiB */ + }; + + partition@7e0000 { + label = "devinfo"; + reg = <0x7e0000 0x40000>; /* 256KiB */ + read-only; + }; + + partition@820000 { + label = "sysdiag"; + reg = <0x820000 0x1e0000>; /* 1920KiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x5000000>; /* 80MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x4a00000>; /* 74MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@5a00000 { + label = "kernel2"; + reg = <0x5a00000 0x5000000>; /* 80MiB */ + }; + + partition@6000000 { + label = "rootfs2"; + reg = <0x6000000 0x4a00000>; /* 74MiB */ + }; + + /* + * 86MiB, last MiB is for the BBT, not writable + */ + partition@aa00000 { + label = "syscfg"; + reg = <0xaa00000 0x5600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x260000 0x5c0000>; /* 5.75MiB */ + }; + }; +}; + +&sdhci { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + no-1-8-v; + non-removable; + wp-inverted; + bus-width = <8>; + status = "okay"; +}; + +&usb3_1_vbus { + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +}; + +&usb3_1_vbus_pins { + marvell,pins = "mpp44"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts new file mode 100644 index 000000000000..f1b1f22413f1 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Linksys WRT1900ACS (Shelby) + * + * Copyright (C) 2015 Imre Kaloz + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1900ACS"; + compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; +}; + +&expander0 { + wan_amber@0 { + label = "shelby:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "shelby:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "shelby:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "shelby:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "shelby:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "shelby:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "shelby:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "shelby:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "shelby:amber:wps"; + reg = <0x9>; + }; +}; + +&gpio_leds { + led-power { + label = "shelby:white:power"; + }; + + led-sata { + label = "shelby:white:sata"; + }; +}; + +&nand { + /* 128MiB */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KiB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MiB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MiB */ + }; + + /* + * 38MiB, last MiB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MiB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi new file mode 100644 index 000000000000..fc8216fd9f60 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree include file for Armada 385 based Linksys boards + * + * Copyright (C) 2015 Imre Kaloz + */ + +#include +#include +#include "armada-385.dtsi" + +/ { + model = "Linksys boards based on Armada 385"; + compatible = "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MiB */ + }; + + soc { + ranges = ; + }; + + usb3_1_phy: usb3_1-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&usb3_1_vbus>; + #phy-cells = <0>; + }; + + usb3_1_vbus: usb3_1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_1_vbus_pins>; + regulator-name = "usb3_1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_pins>; + pinctrl-names = "default"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_pins>; + pinctrl-names = "default"; + + led-power { + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-sata { + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "disk-activity"; + }; + }; +}; + +&ahci0 { + status = "okay"; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ð2 { + status = "okay"; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + expander0: pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9635"; + reg = <0x68>; + }; +}; + +&nand_controller { + /* 128MiB or 256MiB */ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + nand: nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-keep-config; + nand-on-flash-bbt; + }; +}; + +&mdio { + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + phy-mode = "sgmii"; + ethernet = <ð2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Marvell 88W8864, 5GHz-only */ + status = "okay"; +}; + +&pcie2 { + /* Marvell 88W8864, 2GHz-only */ + status = "okay"; +}; + +&pinctrl { + gpio_keys_pins: gpio-keys-pins { + /* mpp24: wps, mpp29: reset */ + marvell,pins = "mpp24", "mpp29"; + marvell,function = "gpio"; + }; + + gpio_leds_pins: gpio-leds-pins { + /* mpp54: sata, mpp55: power */ + marvell,pins = "mpp54", "mpp55"; + marvell,function = "gpio"; + }; + + usb3_1_vbus_pins: usb3_1-vbus-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + status = "disabled"; +}; + +&uart0 { + /* J10: VCC, NC, RX, NC, TX, GND */ + status = "okay"; +}; + +&usb0 { + /* USB part of the eSATA/USB 2.0 port */ + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + usb-phy = <&usb3_1_phy>; +}; + +&rtc { + /* No crystal connected to the internal RTC */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts b/arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts new file mode 100644 index 000000000000..ea91ff964d94 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Synology DS116 NAS + * + * Copyright (C) 2017 Willy Tarreau + */ + +/dts-v1/; +#include "armada-385.dtsi" +#include + +/ { + model = "Synology DS116"; + compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + }; + + serial@12000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + + serial@12100 { + /* A PIC16F1829 is connected to uart1 at 9600 bps, + * and takes single-character orders : + * "1" : power off // already handled by the poweroff node + * "2" : short beep + * "3" : long beep + * "4" : turn the power LED ON + * "5" : flash the power LED + * "6" : turn the power LED OFF + * "7" : turn the status LED OFF + * "8" : turn the status LED ON + * "9" : flash the status LED + * "A" : flash the motherboard LED (D8) + * "B" : turn the motherboard LED OFF + * "C" : hard reset + */ + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + ethernet@70000 { + pinctrl-names = "default"; + phy = <&phy0>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + status = "okay"; + }; + + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + sata@a8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata0_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + target-supply = <®_5v_sata0>; + }; + }; + + bm@c8000 { + status = "okay"; + }; + + usb3@f0000 { + usb-phy = <&usb3_0_phy>; + status = "okay"; + }; + + usb3@f8000 { + usb-phy = <&usb3_1_phy>; + status = "okay"; + }; + }; + + bm-bppi { + status = "okay"; + }; + + gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>, + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 16 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 1500 1 + 2500 2 + 3000 3 + 3400 4 + 3700 5 + 3900 6 + 4000 7>; + #cooling-cells = <2>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + /* The green part is on gpio0.20 which is also used by + * sata0, and accesses to SATA disk 0 make it blink so it + * doesn't need to be declared here. + */ + led-orange { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "ds116:orange:disk"; + default-state = "off"; + }; + }; + }; + + usb3_0_phy: usb3_0_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_usb3_0_vbus>; + #phy-cells = <0>; + }; + + usb3_1_phy: usb3_1_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_usb3_1_vbus>; + #phy-cells = <0>; + }; + + reg_usb3_0_vbus: usb3-vbus0 { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus0"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + + reg_usb3_1_vbus: usb3-vbus1 { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus1"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci1_vbus_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; + }; + + reg_sata0: pwr-sata0 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + regulator-boot-on; + gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata0: v5-sata0 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_sata0>; + }; + + reg_12v_sata0: v12-sata0 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_sata0>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25l6405d", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + + /* Note: there is a redboot partition table despite u-boot + * being used. The names presented here are the same as those + * found in the FIS directory. There is also a small device + * tree in the last 64kB of the RedBoot partition which is not + * enumerated. The MAC address and the serial number are listed + * in the "vendor" partition. + */ + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x000f0000>; + read-only; + }; + + partition@c0000 { + label = "zImage"; + reg = <0x000f0000 0x002d0000>; + }; + + partition@390000 { + label = "rd.gz"; + reg = <0x003c0000 0x00410000>; + }; + + partition@7d0000 { + label = "vendor"; + reg = <0x007d0000 0x00010000>; + read-only; + }; + + partition@7e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; + read-only; + }; + + partition@7f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; + read-only; + }; + }; +}; + +&pinctrl { + /* use only one pin for UART1, as mpp20 is used by sata0 */ + uart1_pins: uart-pins-1 { + marvell,pins = "mpp19"; + marvell,function = "ua1"; + }; + + xhci0_vbus_pins: xhci0_vbus_pins { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + xhci1_vbus_pins: xhci1_vbus_pins { + marvell,pins = "mpp59"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts new file mode 100644 index 000000000000..2d8d319bec83 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Turris Omnia + * + * Copyright (C) 2016 Uwe Kleine-König + * Copyright (C) 2016 Tomas Hlavacek + * + * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf + */ + +/dts-v1/; + +#include +#include +#include +#include "armada-385.dtsi" + +/ { + model = "Turris Omnia"; + compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = &uart0; + }; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + ethernet2 = ð2; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1024 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* USB part of the PCIe2/USB 2.0 port */ + usb@58000 { + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + status = "okay"; + + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + slot-power-limit-milliwatt = <10000>; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + slot-power-limit-milliwatt = <10000>; + }; + + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + slot-power-limit-milliwatt = <10000>; + }; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <3000>; + + /* + * For now this has to be enabled at boot time by U-Boot when + * a SFP module is present. Read more in the comment in the + * eth2 node below. + */ + status = "disabled"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&audio_controller 1>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&audio_controller { + /* Pin header U16, GPIO51 in SPDIFO mode */ + pinctrl-0 = <&spdif_pins>; + pinctrl-names = "default"; + spdif-mode; + status = "okay"; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +/* Connected to 88E6176 switch, port 6 */ +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&ge0_rgmii_pins>; + status = "okay"; + phy-mode = "rgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <3>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/* Connected to 88E6176 switch, port 5 */ +ð1 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy-mode = "rgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + bm,pool-short = <3>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/* WAN port */ +ð2 { + /* + * eth2 is connected via a multiplexor to both the SFP cage and to + * ethernet-phy@1. The multiplexor switches the signal to SFP cage when + * a SFP module is present, as determined by the mode-def0 GPIO. + * + * Until kernel supports this configuration properly, in case SFP module + * is present, U-Boot has to enable the sfp node above, remove phy + * handle and add managed = "in-band-status" property. + */ + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phys = <&comphy5 2>; + sfp = <&sfp>; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + label = "wan"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + i2cmux@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* STM32F0 command interface at address 0x2a */ + + led-controller@2b { + compatible = "cznic,turris-omnia-leds"; + reg = <0x2b>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* + * LEDs are controlled by MCU (STM32F0) at + * address 0x2b. + * + * LED functions are not stable yet: + * - there are 3 LEDs connected via MCU to PCIe + * ports. One of these ports supports mSATA. + * There is no mSATA nor PCIe function. + * For now we use LED_FUNCTION_WLAN, since + * in most cases users have wifi cards in + * these slots + * - there are 2 LEDs dedicated for user: A and + * B. Again there is no such function defined. + * For now we use LED_FUNCTION_INDICATOR + */ + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + multi-led@1 { + reg = <0x1>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + multi-led@2 { + reg = <0x2>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <3>; + }; + + multi-led@3 { + reg = <0x3>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <2>; + }; + + multi-led@4 { + reg = <0x4>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <1>; + }; + + multi-led@5 { + reg = <0x5>; + color = ; + function = LED_FUNCTION_WAN; + }; + + multi-led@6 { + reg = <0x6>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + }; + + multi-led@7 { + reg = <0x7>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + }; + + multi-led@8 { + reg = <0x8>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + }; + + multi-led@9 { + reg = <0x9>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + + multi-led@a { + reg = <0xa>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + }; + + multi-led@b { + reg = <0xb>; + color = ; + function = LED_FUNCTION_POWER; + }; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + + /* The EEPROM contains data for bootloader. + * Contents: + * struct omnia_eeprom { + * u32 magic; (=0x0341a034 in LE) + * u32 ramsize; (in GiB) + * char regdomain[4]; + * u32 crc32; + * }; + */ + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* routed to PCIe0/mSATA connector (CN7A) */ + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* routed to PCIe1/USB2 connector (CN61A) */ + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + /* routed to PCIe2 connector (CN62A) */ + }; + + sfp_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + /* routed to SFP+ */ + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + /* ATSHA204A-MAHDA-T crypto module */ + crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + /* exposed on pin header */ + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + pcawan: gpio@71 { + /* + * GPIO expander for SFP+ signals and + * and phy irq + */ + compatible = "nxp,pca9538"; + reg = <0x71>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcawan_pins>; + + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <3 18 0 0x4985>, + <3 16 0xfff0 0x0001>; + + /* irq is connected to &pcawan pin 7 */ + }; + + /* Switch MV88E6176 at address 0x10 */ + switch@10 { + pinctrl-names = "default"; + pinctrl-0 = <&swint_pins>; + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + + dsa,member = <0 0>; + reg = <0x10>; + + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + reg = <0>; + label = "lan0"; + }; + + ports@1 { + reg = <1>; + label = "lan1"; + }; + + ports@2 { + reg = <2>; + label = "lan2"; + }; + + ports@3 { + reg = <3>; + label = "lan3"; + }; + + ports@4 { + reg = <4>; + label = "lan4"; + }; + + ports@5 { + reg = <5>; + ethernet = <ð1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ports@6 { + reg = <6>; + ethernet = <ð0>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&pinctrl { + pcawan_pins: pcawan-pins { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + swint_pins: swint-pins { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + spi0cs0_pins: spi0cs0-pins { + marvell,pins = "mpp25"; + marvell,function = "spi0"; + }; + + spi0cs2_pins: spi0cs2-pins { + marvell,pins = "mpp26"; + marvell,function = "spi0"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0cs0_pins>; + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl164k", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x00100000>; + label = "U-Boot"; + }; + + partition@100000 { + reg = <0x00100000 0x00700000>; + label = "Rescue system"; + }; + }; + }; + + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ +}; + +&uart0 { + /* Pin header CN10 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + /* Pin header CN11 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385.dtsi b/arch/arm/boot/dts/marvell/armada-385.dtsi new file mode 100644 index 000000000000..be8d607c59b2 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 385 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 385 family SoC"; + compatible = "marvell,armada385", "marvell,armada380"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + pciec: pcie { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie1: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* x1 port */ + pcie2: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* x1 port */ + pcie3: pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie4: pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts new file mode 100644 index 000000000000..f7daa3bc707e --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2015 Russell King + */ + +/dts-v1/; +#include "armada-388-clearfog.dtsi" + +/ { + model = "SolidRun Clearfog Base A1"; + compatible = "solidrun,clearfog-base-a1", + "solidrun,clearfog-a1", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button-0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + }; +}; + +ð1 { + phy = <&phy1>; +}; + +&gpio0 { + phy1_reset { + gpio-hog; + gpios = <19 GPIO_ACTIVE_LOW>; + output-low; + line-name = "phy1-reset"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>; + phy1: ethernet-phy@1 { + /* + * Annoyingly, the marvell phy driver configures the LED + * register, rather than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x101e>; + reg = <1>; + }; +}; + +&pinctrl { + /* phy1 reset */ + clearfog_phy_pins: clearfog-phy-pins { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + rear_button_pins: rear-button-pins { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts new file mode 100644 index 000000000000..ff890c09c3ed --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2015 Russell King + */ +#include "armada-388-clearfog.dts" + +/ { + model = "SolidRun Clearfog Pro A1"; + compatible = "solidrun,clearfog-pro-a1", + "solidrun,clearfog-a1", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts new file mode 100644 index 000000000000..32c569df142f --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2015 Russell King + */ + +/dts-v1/; +#include "armada-388-clearfog.dtsi" + +/ { + model = "SolidRun Clearfog A1"; + compatible = "solidrun,clearfog-a1", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + soc { + internal-regs { + usb3@f0000 { + /* CON2, nearest CPU, USB2 only. */ + status = "okay"; + }; + }; + + pcie { + pcie@3,0 { + /* Port 2, Lane 0. CON2, nearest CPU. */ + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button-0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + }; +}; + +ð1 { + /* ethernet@30000 */ + phy-mode = "1000base-x"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&expander0 { + /* + * PCA9655 GPIO expander: + * 0-CON3 CLKREQ# + * 1-CON3 PERST# + * 2-CON2 PERST# + * 3-CON3 W_DISABLE + * 4-CON2 CLKREQ# + * 5-USB3 overcurrent + * 6-USB3 power + * 7-CON2 W_DISABLE + * 8-JP4 P1 + * 9-JP4 P4 + * 10-JP4 P5 + * 11-m.2 DEVSLP + * 12-SFP_LOS + * 13-SFP_TX_FAULT + * 14-SFP_TX_DISABLE + * 15-SFP_MOD_DEF0 + */ + pcie2-0-clkreq-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie2.0-clkreq"; + }; + pcie2-0-w-disable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie2.0-w-disable"; + }; +}; + +&mdio { + status = "okay"; + + switch@4 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan1"; + }; + + port@5 { + reg = <5>; + ethernet = <ð1>; + phy-mode = "1000base-x"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + /* 88E1512 external phy */ + reg = <6>; + label = "lan6"; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&pinctrl { + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + clearfog_dsa0_pins: clearfog-dsa0-pins { + marvell,pins = "mpp23", "mpp41"; + marvell,function = "gpio"; + }; + clearfog_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp55"; + marvell,function = "spi1"; + }; + rear_button_pins: rear-button-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; +}; + +&spi1 { + /* + * Add SPI CS pins for clearfog: + * CS0: W25Q32 + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi b/arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi new file mode 100644 index 000000000000..f8a06ae4a3c9 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree include file for SolidRun Clearfog 88F6828 based boards + * + * Copyright (C) 2015 Russell King + */ + +#include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi" + +/ { + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + ethernet2 = ð1; + ethernet3 = ð2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + internal-regs { + sata@a8000 { + /* pinctrl? */ + status = "okay"; + }; + + sata@e0000 { + /* pinctrl? */ + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <µsom_sdhci_pins + &clearfog_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc-supply = <®_3p3v>; + wp-inverted; + }; + + usb@58000 { + /* CON3, nearest power. */ + status = "okay"; + }; + + usb3@f8000 { + /* CON7 */ + status = "okay"; + }; + }; + + pcie { + status = "okay"; + /* + * The two PCIe units are accessible through + * the mini-PCIe connectors on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0. CON3, nearest power. */ + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; +}; + +ð1 { + /* ethernet@30000 */ + bm,pool-long = <2>; + bm,pool-short = <1>; + buffer-manager = <&bm>; + phys = <&comphy1 1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +ð2 { + /* ethernet@34000 */ + bm,pool-long = <3>; + bm,pool-short = <1>; + buffer-manager = <&bm>; + managed = "in-band-status"; + phys = <&comphy5 2>; + phy-mode = "sgmii"; + sfp = <&sfp>; + status = "okay"; +}; + +&i2c0 { + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-CON3 CLKREQ# + * 1-CON3 PERST# + * 2- + * 3-CON3 W_DISABLE + * 4- + * 5-USB3 overcurrent + * 6-USB3 power + * 7- + * 8-JP4 P1 + * 9-JP4 P4 + * 10-JP4 P5 + * 11-m.2 DEVSLP + * 12-SFP_LOS + * 13-SFP_TX_FAULT + * 14-SFP_TX_DISABLE + * 15-SFP_MOD_DEF0 + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", "nxp,pca9555"; + * but you can't do this because of the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + pcie1-0-clkreq-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie1.0-clkreq"; + }; + pcie1-0-w-disable-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie1.0-w-disable"; + }; + usb3-ilimit-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + input; + line-name = "usb3-current-limit"; + }; + usb3-power-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb3-power"; + }; + m2-devslp-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2 devslp"; + }; + }; + + /* The MCP3021 supports standard and fast modes */ + mikrobus_adc: mcp3021@4c { + compatible = "microchip,mcp3021"; + reg = <0x4c>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; +}; + +&i2c1 { + /* + * Routed to SFP, mikrobus, and PCIe. + * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with + * address pins tied low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C bus being present. + * PCIe uses ARP to assign addresses, or 0x63-0x64. + */ + clock-frequency = <100000>; + pinctrl-0 = <&clearfog_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + clearfog_i2c1_pins: i2c1-pins { + /* SFP, PCIe, mSATA, mikrobus */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + mikro_pins: mikro-pins { + /* int: mpp22 rst: mpp29 */ + marvell,pins = "mpp22", "mpp29"; + marvell,function = "gpio"; + }; + mikro_spi_pins: mikro-spi-pins { + marvell,pins = "mpp43"; + marvell,function = "spi1"; + }; + mikro_uart_pins: mikro-uart-pins { + marvell,pins = "mpp24", "mpp25"; + marvell,function = "ua1"; + }; +}; + +&spi1 { + /* + * Add SPI CS pins for clearfog: + * CS0: W25Q32 + * CS1: PIC microcontroller (Pro models) + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + /* mikrobus uart */ + pinctrl-0 = <&mikro_uart_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-db.dts b/arch/arm/boot/dts/marvell/armada-388-db.dts new file mode 100644 index 000000000000..45cc784659fd --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-db.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada 388 evaluation board + * (DB-88F6820) + * + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni + */ + +/dts-v1/; +#include "armada-388.dtsi" + +/ { + model = "Marvell Armada 385 Development Board"; + compatible = "marvell,a385-db", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + audio_codec: audio-codec@4a { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; + }; + + i2c@11100 { + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + }; + + usb@58000 { + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + }; + + mdio@72004 { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + sata@a8000 { + status = "okay"; + }; + + sata@e0000 { + status = "okay"; + }; + + bm@c8000 { + status = "okay"; + }; + + sdhci@d8000 { + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + no-1-8-v; + }; + + audio-controller@e8000 { + pinctrl-0 = <&i2s_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + bm-bppi { + status = "okay"; + }; + + pcie { + status = "okay"; + /* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Armada 385 DB Audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Out Jack", + "Line", "In Jack"; + simple-audio-card,routing = + "Out Jack", "HPL", + "Out Jack", "HPR", + "AIN1L", "In Jack", + "AIN1R", "In Jack"; + status = "disabled"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 0>; + }; + + codec { + sound-dai = <&audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_out>; + }; + }; + + simple-audio-card,dai-link@2 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_in>; + }; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-gp.dts b/arch/arm/boot/dts/marvell/armada-388-gp.dts new file mode 100644 index 000000000000..e2ba50520b6b --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-gp.dts @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 385 development board + * (RD-88F6820-GP) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + */ + +/dts-v1/; +#include "armada-388.dtsi" +#include + +/ { + model = "Marvell Armada 388 DB-88F6820-GP"; + compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; + + expander0: pca9555@20 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20>; + }; + + expander1: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x21>; + }; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON16 + * through an FTDI + */ + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + + /* GE1 CON15 */ + ethernet@30000 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + }; + + /* CON4 */ + usb@58000 { + vcc-supply = <®_usb2_0_vbus>; + status = "okay"; + }; + + /* GE0 CON1 */ + ethernet@70000 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + }; + + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + sata@a8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata0_pins>, <&sata1_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + target-supply = <®_5v_sata0>; + }; + + sata1: sata-port@1 { + reg = <1>; + target-supply = <®_5v_sata1>; + }; + }; + + bm@c8000 { + status = "okay"; + }; + + sata@e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata2_pins>, <&sata3_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata2: sata-port@0 { + reg = <0>; + target-supply = <®_5v_sata2>; + }; + + sata3: sata-port@1 { + reg = <1>; + target-supply = <®_5v_sata3>; + }; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + no-1-8-v; + /* + * A388-GP board v1.5 and higher replace + * hitherto card detection method based on GPIO + * with the one using DAT3 pin. As they are + * incompatible, software-based polling is + * enabled with 'broken-cd' property. For boards + * older than v1.5 it can be replaced with: + * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', + * whereas for the newer ones following can be + * used instead: + * 'dat3-cd;' + * 'cd-inverted;' + */ + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + + /* CON5 */ + usb3@f0000 { + usb-phy = <&usb2_1_phy>; + status = "okay"; + }; + + /* CON7 */ + usb3@f8000 { + usb-phy = <&usb3_phy>; + status = "okay"; + }; + }; + + bm-bppi { + status = "okay"; + }; + + pcie { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * The two other PCIe units are accessible + * through mini PCIe slot on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + + gpio-fan { + compatible = "gpio-fan"; + gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + }; + + usb2_1_phy: usb2_1_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_usb2_1_vbus>; + #phy-cells = <0>; + }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_usb3_vbus>; + #phy-cells = <0>; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_0_vbus: v5-vbus0 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_1_vbus: v5-vbus1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; + + reg_sata0: pwr-sata0 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + regulator-boot-on; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata0: v5-sata0 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_sata0>; + }; + + reg_12v_sata0: v12-sata0 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_sata0>; + }; + + reg_sata1: pwr-sata1 { + regulator-name = "pwr_en_sata1"; + compatible = "regulator-fixed"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + regulator-boot-on; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata1: v5-sata1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_sata1>; + }; + + reg_12v_sata1: v12-sata1 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_sata1>; + }; + + reg_sata2: pwr-sata2 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata2"; + enable-active-high; + regulator-boot-on; + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata2: v5-sata2 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_sata2>; + }; + + reg_12v_sata2: v12-sata2 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata2"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_sata2>; + }; + + reg_sata3: pwr-sata3 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata3"; + enable-active-high; + regulator-boot-on; + gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata3: v5-sata3 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_sata3>; + }; + + reg_12v_sata3: v12-sata3 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata3"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_sata3>; + }; +}; + +&pinctrl { + pca0_pins: pca0_pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-helios4.dts b/arch/arm/boot/dts/marvell/armada-388-helios4.dts new file mode 100644 index 000000000000..ec134e22bae3 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-helios4.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Helios4 + * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2017 Aditya Prayoga + * + */ + +/dts-v1/; +#include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi" + +/ { + model = "Helios4"; + compatible = "kobol,helios4", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "power_brick_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_hdd: regulator-5v-hdd { + compatible = "regulator-fixed"; + regulator-name = "5V_HDD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_usb: regulator-5v-usb { + compatible = "regulator-fixed"; + regulator-name = "USB-PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_12v>; + }; + + system-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&helios_system_led_pins>; + + status-led { + label = "helios4:green:status"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + fault-led { + label = "helios4:red:fault"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + io-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&helios_io_led_pins>; + + sata1-led { + label = "helios4:green:ata1"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata1"; + default-state = "off"; + }; + sata2-led { + label = "helios4:green:ata2"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata2"; + default-state = "off"; + }; + sata3-led { + label = "helios4:green:ata3"; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata3"; + default-state = "off"; + }; + sata4-led { + label = "helios4:green:ata4"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata4"; + default-state = "off"; + }; + usb-led { + label = "helios4:green:usb"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usb-host"; + default-state = "off"; + }; + }; + + fan1: j10-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ + pinctrl-names = "default"; + pinctrl-0 = <&helios_fan1_pins>; + }; + + fan2: j17-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ + pinctrl-names = "default"; + pinctrl-0 = <&helios_fan2_pins>; + }; + + usb2_phy: usb2-phy { + compatible = "usb-nop-xceiv"; + vbus-regulator = <®_5p0v_usb>; + }; + + usb3_phy: usb3-phy { + compatible = "usb-nop-xceiv"; + }; + + soc { + internal-regs { + i2c@11000 { + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-Board Revision bit 0 # + * 1-Board Revision bit 1 # + * 5-USB3 overcurrent + * 6-USB3 power + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + board-rev-bit-0-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-0"; + }; + board-rev-bit-1-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-1"; + }; + usb3-ilimit-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + line-name = "usb-overcurrent-status"; + }; + }; + + temp_sensor: temp@4c { + compatible = "ti,lm75"; + reg = <0x4c>; + vcc-supply = <®_3p3v>; + }; + }; + + i2c@11100 { + /* + * External I2C Bus for user peripheral + */ + clock-frequency = <400000>; + pinctrl-0 = <&helios_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + }; + + sata1: sata-port@1 { + reg = <1>; + }; + }; + + sata@e0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata2: sata-port@0 { + reg = <0>; + }; + + sata3: sata-port@1 { + reg = <1>; + }; + }; + + spi@10680 { + pinctrl-0 = <&spi1_pins + µsom_spi1_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&helios_sdhci_pins + &helios_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + usb@58000 { + usb-phy = <&usb2_phy>; + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + + pinctrl@18000 { + pca0_pins: pca0-pins { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + microsom_phy0_int_pins: microsom-phy0-int-pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + helios_i2c1_pins: i2c1-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + helios_sdhci_cd_pins: helios-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + helios_system_led_pins: helios-system-led-pins { + marvell,pins = "mpp24", "mpp25"; + marvell,function = "gpio"; + }; + helios_io_led_pins: helios-io-led-pins { + marvell,pins = "mpp49", "mpp50", + "mpp52", "mpp53", + "mpp54"; + marvell,function = "gpio"; + }; + helios_fan1_pins: helios_fan1_pins { + marvell,pins = "mpp41", "mpp43"; + marvell,function = "gpio"; + }; + helios_fan2_pins: helios_fan2_pins { + marvell,pins = "mpp48", "mpp55"; + marvell,function = "gpio"; + }; + microsom_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp59"; + marvell,function = "spi1"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-388-rd.dts b/arch/arm/boot/dts/marvell/armada-388-rd.dts new file mode 100644 index 000000000000..c0efafd45b33 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388-rd.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada 388 Reference Design board + * (RD-88F6820-AP) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + */ + +/dts-v1/; +#include "armada-388.dtsi" + +/ { + model = "Marvell Armada 385 Reference Design"; + compatible = "marvell,a385-rd", "marvell,armada388", + "marvell,armada385","marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + broken-cd; + no-1-8-v; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + + serial@12000 { + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + + mdio@72004 { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + usb3@f0000 { + status = "okay"; + }; + }; + + pcie { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + diff --git a/arch/arm/boot/dts/marvell/armada-388.dtsi b/arch/arm/boot/dts/marvell/armada-388.dtsi new file mode 100644 index 000000000000..f3a020ff577e --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-388.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 388 SoC. + * + * Copyright (C) 2015 Marvell + * + * Gregory CLEMENT + * + * The main difference with the Armada 385 is that the 388 can handle two more + * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl + * property and the name of the SoC, and add the second SATA host which control + * the 2 other ports. + */ + +#include "armada-385.dtsi" + +/ { + model = "Marvell Armada 388 family SoC"; + compatible = "marvell,armada388", "marvell,armada385", + "marvell,armada380"; + soc { + internal-regs { + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = ; + clocks = <&gateclk 30>; + status = "disabled"; + }; + + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv88f6828-pinctrl"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi new file mode 100644 index 000000000000..2c64bc6e5a17 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidRun Armada 38x Microsom + * + * Copyright (C) 2015 Russell King + */ +#include +#include + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = ; + + internal-regs { + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" + * twice in u-boot. + */ + status = "okay"; + }; + }; + }; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +ð0 { + /* ethernet@70000 */ + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy_dedicated>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + status = "okay"; +}; + +&mdio { + /* + * Add the phy clock here, so the phy can be accessed to read its + * IDs prior to binding with the driver. + */ + pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; + pinctrl-names = "default"; + + phy_dedicated: ethernet-phy@0 { + /* + * Annoyingly, the marvell phy driver configures the LED + * register, rather than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x101e>; + reg = <0>; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&pinctrl { + microsom_phy_clk_pins: microsom-phy-clk-pins { + marvell,pins = "mpp45"; + marvell,function = "ref"; + }; + /* Optional eMMC */ + microsom_sdhci_pins: microsom-sdhci-pins { + marvell,pins = "mpp21", "mpp28", "mpp37", + "mpp38", "mpp39", "mpp40"; + marvell,function = "sd0"; + }; +}; + +&spi1 { + /* The microsom has an optional W25Q32 on board, connected to CS0 */ + pinctrl-0 = <&spi1_pins>; + + w25q32: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi new file mode 100644 index 000000000000..446861b6b17b --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 38x family of SoCs. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + */ + +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Marvell Armada 38x family SoC"; + compatible = "marvell,armada380"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + serial0 = &uart0; + serial1 = &uart1; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + + soc { + compatible = "marvell,armada380-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + devbus_bootcs: devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs0: devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs1: devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs2: devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus_cs3: devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + sdramc: sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <0>; + prefetch-data = <1>; + }; + + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + + timer@c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xc200 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "marvell,armada-38x-uart", "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "marvell,armada-38x-uart", "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl: pinctrl@18000 { + reg = <0x18000 0x20>; + + ge0_rgmii_pins: ge-rgmii-pins-0 { + marvell,pins = "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge-rgmii-pins-1 { + marvell,pins = "mpp21", "mpp27", "mpp28", + "mpp29", "mpp30", "mpp31", + "mpp32", "mpp37", "mpp38", + "mpp39", "mpp40", "mpp41"; + marvell,function = "ge1"; + }; + + i2c0_pins: i2c-pins-0 { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + mdio_pins: mdio-pins { + marvell,pins = "mpp4", "mpp5"; + marvell,function = "ge"; + }; + + ref_clk0_pins: ref-clk-pins-0 { + marvell,pins = "mpp45"; + marvell,function = "ref"; + }; + + ref_clk1_pins: ref-clk-pins-1 { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + + spi0_pins: spi-pins-0 { + marvell,pins = "mpp22", "mpp23", "mpp24", + "mpp25"; + marvell,function = "spi0"; + }; + + spi1_pins: spi-pins-1 { + marvell,pins = "mpp56", "mpp57", "mpp58", + "mpp59"; + marvell,function = "spi1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", + "mpp33", "mpp38", "mpp28", + "mpp40", "mpp42", "mpp35", + "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp41"; + marvell,function = "nand"; + }; + + uart0_pins: uart-pins-0 { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "ua0"; + }; + + uart1_pins: uart-pins-1 { + marvell,pins = "mpp19", "mpp20"; + marvell,function = "ua1"; + }; + + sdhci_pins: sdhci-pins { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp52", "mpp53", "mpp54", + "mpp55", "mpp57", "mpp58", + "mpp59"; + marvell,function = "sd0"; + }; + + sata0_pins: sata-pins-0 { + marvell,pins = "mpp20"; + marvell,function = "sata0"; + }; + + sata1_pins: sata-pins-1 { + marvell,pins = "mpp19"; + marvell,function = "sata1"; + }; + + sata2_pins: sata-pins-2 { + marvell,pins = "mpp47"; + marvell,function = "sata2"; + }; + + sata3_pins: sata-pins-3 { + marvell,pins = "mpp44"; + marvell,function = "sata3"; + }; + + i2s_pins: i2s-pins { + marvell,pins = "mpp48", "mpp49", + "mpp50", "mpp51", + "mpp52", "mpp53"; + marvell,function = "audio"; + }; + + spdif_pins: spdif-pins { + marvell,pins = "mpp51"; + marvell,function = "audio"; + }; + }; + + gpio0: gpio@18100 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <28>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 28>; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + clocks = <&coreclk 0>; + }; + + systemc: system-controller@18200 { + compatible = "marvell,armada-380-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-380-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + comphy: phy@18300 { + compatible = "marvell,armada-380-comphy"; + reg-names = "comphy", "conf"; + reg = <0x18300 0x100>, <0x18460 4>; + #address-cells = <1>; + #size-cells = <0>; + + comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + + comphy2: phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + + comphy3: phy@3 { + reg = <3>; + #phy-cells = <1>; + }; + + comphy4: phy@4 { + reg = <4>; + #phy-cells = <1>; + }; + + comphy5: phy@5 { + reg = <5>; + #phy-cells = <1>; + }; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-380-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer: timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + watchdog: watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + + coherencyfab: coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + + pmsu: pmsu@22000 { + compatible = "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + + /* + * As a special exception to the "order by + * register address" rule, the eth0 node is + * placed here to ensure that it gets + * registered as the first interface, since + * the network subsystem doesn't allow naming + * interfaces using DT aliases. Without this, + * the ordering of interfaces is different + * from the one used in U-Boot and the + * labeling of interfaces on the boards, which + * is very confusing for users. + */ + eth0: ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x4000>; + interrupts-extended = <&mpic 8>; + clocks = <&gateclk 4>; + tx-csum-limit = <9800>; + status = "disabled"; + }; + + eth1: ethernet@30000 { + compatible = "marvell,armada-370-neta"; + reg = <0x30000 0x4000>; + interrupts-extended = <&mpic 10>; + clocks = <&gateclk 3>; + status = "disabled"; + }; + + eth2: ethernet@34000 { + compatible = "marvell,armada-370-neta"; + reg = <0x34000 0x4000>; + interrupts-extended = <&mpic 12>; + clocks = <&gateclk 2>; + status = "disabled"; + }; + + usb0: usb@58000 { + compatible = "marvell,orion-ehci"; + reg = <0x58000 0x500>; + interrupts = ; + clocks = <&gateclk 18>; + status = "disabled"; + }; + + xor0: xor@60800 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor1: xor@60900 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + clocks = <&gateclk 4>; + }; + + cesa: crypto@90000 { + compatible = "marvell,armada-38x-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = , + ; + clocks = <&gateclk 23>, <&gateclk 21>, + <&gateclk 14>, <&gateclk 16>; + clock-names = "cesa0", "cesa1", + "cesaz0", "cesaz1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + + rtc: rtc@a3800 { + compatible = "marvell,armada-380-rtc"; + reg = <0xa3800 0x20>, <0x184a0 0x0c>; + reg-names = "rtc", "rtc-soc"; + interrupts = ; + }; + + ahci0: sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = ; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + bm: bm@c8000 { + compatible = "marvell,armada-380-neta-bm"; + reg = <0xc8000 0xac>; + clocks = <&gateclk 13>; + internal-mem = <&bm_bppi>; + status = "disabled"; + }; + + ahci1: sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = ; + clocks = <&gateclk 30>; + status = "disabled"; + }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + + thermal: thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4070 0x8>; + status = "okay"; + }; + + nand_controller: nand-controller@d0000 { + compatible = "marvell,armada370-nand-controller"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + sdhci: sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; + interrupts = ; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; + + audio_controller: audio-controller@e8000 { + #sound-dai-cells = <1>; + compatible = "marvell,armada-380-audio"; + reg = <0xe8000 0x4000>, <0x18410 0xc>, + <0x18204 0x4>; + reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; + interrupts = ; + clocks = <&gateclk 0>; + clock-names = "internal"; + status = "disabled"; + }; + + usb3_0: usb3@f0000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf0000 0x4000>,<0xf4000 0x4000>; + interrupts = ; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + usb3_1: usb3@f8000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf8000 0x4000>,<0xfc000 0x4000>; + interrupts = ; + clocks = <&gateclk 10>; + status = "disabled"; + }; + }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; + }; + + bm_bppi: bm-bppi { + compatible = "mmio-sram"; + reg = ; + ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gateclk 13>; + no-memory-wc; + status = "disabled"; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + }; + + clocks { + /* 1 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-390-db.dts b/arch/arm/boot/dts/marvell/armada-390-db.dts new file mode 100644 index 000000000000..792d0a0184e8 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-390-db.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada 390 Development Board + * (DB-88F6920) + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk + */ + +/dts-v1/; +#include "armada-390.dtsi" + +/ { + model = "Marvell Armada 390 Development Board"; + compatible = "marvell,a390-db", "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + /* CON104 */ + serial@12000 { + status = "okay"; + }; + + /* CON97 */ + usb@58000 { + status = "okay"; + }; + + /* CON98 */ + usb3@f8000 { + status = "okay"; + }; + }; + + pcie { + status = "okay"; + + /* CON30 */ + pcie@1,0 { + status = "okay"; + }; + + /* CON44 */ + pcie@2,0 { + status = "okay"; + }; + + /* CON61 */ + pcie@3,0 { + status = "okay"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", + "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; +}; + +&nand_controller { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-390.dtsi b/arch/arm/boot/dts/marvell/armada-390.dtsi new file mode 100644 index 000000000000..aa2057d4d6f8 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-390.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 390 SoC. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + */ + +#include "armada-39x.dtsi" + +/ { + compatible = "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6920-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-395-gp.dts b/arch/arm/boot/dts/marvell/armada-395-gp.dts new file mode 100644 index 000000000000..6dd9e9077f84 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-395-gp.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 395 GP board + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk + */ + +/dts-v1/; +#include "armada-395.dtsi" + +/ { + model = "Marvell Armada 395 GP Board"; + compatible = "marvell,a395-gp", "marvell,armada395", + "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON17 + * through an FTDI + */ + status = "okay"; + }; + + /* CON1 */ + usb@58000 { + status = "okay"; + }; + + /* CON2 */ + sata@a8000 { + status = "okay"; + }; + + /* CON18 */ + sdhci@d8000 { + clock-frequency = <200000000>; + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + no-1-8-v; + }; + + /* CON4 */ + usb3@f0000 { + status = "okay"; + }; + }; + + pcie { + status = "okay"; + + /* + * The two PCIe units are accessible through + * mini PCIe slot on the board. + */ + + /* CON7 */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + /* CON8 */ + pcie@4,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + }; +}; + +&nand_controller { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00600000>; + read-only; + }; + + partition@800000 { + label = "uImage"; + reg = <0x00600000 0x00400000>; + read-only; + }; + + partition@1000000 { + label = "Root"; + reg = <0x00a00000 0x3f600000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-395.dtsi b/arch/arm/boot/dts/marvell/armada-395.dtsi new file mode 100644 index 000000000000..e18a7d9cd7d4 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-395.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 395 SoC. + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk + */ + +#include "armada-39x.dtsi" + +/ { + compatible = "marvell,armada395", "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6925-pinctrl"; + reg = <0x18000 0x20>; + }; + + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = ; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + usb3@f0000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf0000 0x4000>,<0xf4000 0x4000>; + interrupts = ; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-398-db.dts b/arch/arm/boot/dts/marvell/armada-398-db.dts new file mode 100644 index 000000000000..ec6cdbeedde7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-398-db.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 398 Development Board + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + */ + +/dts-v1/; +#include "armada-398.dtsi" + +/ { + model = "Marvell Armada 398 Development Board"; + compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@12100 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + usb@58000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + + pcie@3,0 { + status = "okay"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0x1000000>; + }; + }; +}; + +&nand_controller { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-398.dtsi b/arch/arm/boot/dts/marvell/armada-398.dtsi new file mode 100644 index 000000000000..c5ac89399ce1 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-398.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 398 SoC. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + */ + +#include "armada-395.dtsi" + +/ { + compatible = "marvell,armada398", "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6928-pinctrl"; + reg = <0x18000 0x20>; + }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = ; + clocks = <&gateclk 30>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-39x.dtsi b/arch/arm/boot/dts/marvell/armada-39x.dtsi new file mode 100644 index 000000000000..9d1cac49c022 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-39x.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada 39x family of SoCs. + * + * Copyright (C) 2015 Marvell + * + * Thomas Petazzoni + */ + +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 39x family SoC"; + compatible = "marvell,armada390"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-390-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + + soc { + compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <0>; + prefetch-data = <1>; + }; + + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x100>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c2: i2c@11200 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11200 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c3: i2c@11300 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11300 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl@18000 { + i2c0_pins: i2c0-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + uart0_pins: uart0-pins { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "ua0"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp19", "mpp20"; + marvell,function = "ua1"; + }; + + spi1_pins: spi1-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; + marvell,function = "spi1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", + "mpp38", "mpp28", "mpp40", "mpp42", + "mpp35", "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + system-controller@18200 { + compatible = "marvell,armada-390-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-390-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-390-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&coreclk 5>; + clock-names = "nbclk", "fixed"; + }; + + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, + <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + + coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + + pmsu@22000 { + compatible = "marvell,armada-390-pmsu", + "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + + xor@60800 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + rtc@a3800 { + compatible = "marvell,armada-380-rtc"; + reg = <0xa3800 0x20>, <0x184a0 0x0c>; + reg-names = "rtc", "rtc-soc"; + interrupts = ; + }; + + nand_controller: nand-controller@d0000 { + compatible = "marvell,armada370-nand-controller"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; + interrupts = ; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-390-corediv-clock", + "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + + thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4074 0x4>; + status = "okay"; + }; + }; + + pcie { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + }; + + clocks { + /* 1 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi new file mode 100644 index 000000000000..7a7e2066c498 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell 98dx3236 family SoC + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Contains definitions specific to the 98dx3236 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-370-xp.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + + model = "Marvell 98DX3236 SoC"; + compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,98dx3236-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + }; + + soc { + compatible = "marvell,armadaxp-mbus", "simple-bus"; + + ranges = ; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + /* + * 98DX3236 has 1 x1 PCIe unit Gen2.0 + */ + pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie1: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + internal-regs { + sdramc: sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + + L2: l2-cache@8000 { + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; + cache-level = <2>; + cache-unified; + wt-override; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + /* does not exist */ + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + status = "disabled"; + }; + + gpio2: gpio@18180 { /* rework some properties */ + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <1>; /* only gpio #32 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>; + }; + + systemc: system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,mv98dx3236-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + cpuclk: clock-complex@18700 { + #clock-cells = <1>; + compatible = "marvell,mv98dx3236-cpu-clock"; + reg = <0x18700 0x24>, <0x1c054 0x10>; + clocks = <&coreclk 1>; + }; + + corediv-clock@18740 { + status = "disabled"; + }; + + cpu-config@21000 { + compatible = "marvell,armada-xp-cpu-config"; + reg = <0x21000 0x8>; + }; + + ethernet@70000 { + compatible = "marvell,armada-xp-neta"; + }; + + ethernet@74000 { + compatible = "marvell,armada-xp-neta"; + }; + + xor1: xor@f0800 { + compatible = "marvell,orion-xor"; + reg = <0xf0800 0x100 + 0xf0a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor10 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + nand_controller: nand-controller@d0000 { + clocks = <&dfx_coredivclk 0>; + }; + + xor0: xor@f0900 { + compatible = "marvell,orion-xor"; + reg = <0xF0900 0x100 + 0xF0B00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor00 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + }; + + dfx: dfx-server@ac000000 { + compatible = "marvell,dfx-server", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; + reg = ; + + coreclk: mvebu-sar@f8204 { + compatible = "marvell,mv98dx3236-core-clock"; + reg = <0xf8204 0x4>; + #clock-cells = <1>; + }; + + dfx_coredivclk: corediv-clock@f8268 { + compatible = "marvell,mv98dx3236-corediv-clock"; + reg = <0xf8268 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + switch: switch@a8000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; + + pp0: packet-processor@0 { + compatible = "marvell,prestera-98dx3236", "marvell,prestera"; + reg = <0 0x4000000>; + interrupts = <33>, <34>, <35>; + dfx = <&dfx>; + }; + }; + }; + + clocks { + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; + +&i2c0 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&mpic { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; +}; + +&rtc { + status = "disabled"; +}; + +&timer { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&watchdog { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + interrupts = <93>, <38>; +}; + +&cpurst { + reg = <0x20800 0x20>; +}; + +&usb0 { + clocks = <&gateclk 18>; +}; + +&usb1 { + clocks = <&gateclk 19>; +}; + +&pinctrl { + compatible = "marvell,98dx3236-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", + "mpp26", "mpp27", "mpp28", + "mpp29", "mpp30"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp19"; + marvell,function = "nand"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp0", "mpp1", + "mpp2", "mpp3"; + marvell,function = "spi0"; + }; + + i2c0_pins: i2c-pins-0 { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "i2c0"; + }; +}; + +&spi0 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; +}; + +&sdio { + status = "disabled"; +}; + +&uart0 { + compatible = "marvell,armada-38x-uart"; +}; + +&uart1 { + compatible = "marvell,armada-38x-uart"; +}; + diff --git a/arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi new file mode 100644 index 000000000000..1d9d8a8ea60c --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell 98dx3336 family SoC + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Contains definitions specific to the 98dx3236 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "Marvell 98DX3336 SoC"; + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + cpus { + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + internal-regs { + resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; + }; + }; + }; +}; + +&pp0 { + compatible = "marvell,prestera-98dx3336", "marvell,prestera"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi new file mode 100644 index 000000000000..48ffdc72bfc7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell 98dx4521 family SoC + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Contains definitions specific to the 98dx4521 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "Marvell 98DX4251 SoC"; + compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + cpus { + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + internal-regs { + resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; + }; + }; + }; +}; + +&sdio { + status = "okay"; +}; + +&pinctrl { + compatible = "marvell,98dx4251-pinctrl"; + + sdio_pins: sdio-pins { + marvell,pins = "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10"; + marvell,function = "sd0"; + }; +}; + +&pp0 { + compatible = "marvell,prestera-98dx4251", "marvell,prestera"; + interrupts = <33>, <34>, <35>, <36>; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts new file mode 100644 index 000000000000..5a74197be0ad --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell RD-AXPWiFiAP. + * + * Note: this board is shipped with a new generation boot loader that + * remaps internal registers at 0xf1000000. Therefore, if earlyprintk + * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the + * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni + */ + +/dts-v1/; +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Marvell RD-AXPWiFiAP"; + compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ + }; + + soc { + ranges = ; + + internal-regs { + /* UART0 */ + serial@12000 { + status = "okay"; + }; + + /* UART1 */ + serial@12100 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button-reset { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&pciec { + status = "okay"; + + /* First mini-PCIe port */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Renesas uPD720202 USB 3.0 controller */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; +}; + +&pinctrl { + pinctrl-0 = <&phy_int_pin>; + pinctrl-names = "default"; + + keys_pin: keys-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + phy_int_pin: phy-int-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts new file mode 100644 index 000000000000..c28e140b4afc --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS305-1G-4S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs305-1g-4s.dtsi" + +/ { + model = "MikroTik CRS305-1G-4S+ Bit"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts new file mode 100644 index 000000000000..010b83b54212 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS305-1G-4S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs305-1g-4s.dtsi" + +/ { + model = "MikroTik CRS305-1G-4S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi new file mode 100644 index 000000000000..47b003a81bd4 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS305-1G-4S board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS305-1G-4S+"; + compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts new file mode 100644 index 000000000000..20ba5c823bb2 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS326-24G-2S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs326-24g-2s.dtsi" + +/ { + model = "MikroTik CRS326-24G-2S+ Bit"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts new file mode 100644 index 000000000000..83aef43f66d5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS326-24G-2S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs326-24g-2s.dtsi" + +/ { + model = "MikroTik CRS326-24G-2S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi new file mode 100644 index 000000000000..cab99d8e2911 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS326-24G-2S board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS326-24G-2S+"; + compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts new file mode 100644 index 000000000000..2caa3980fdf6 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs328-4c-20s-4s.dtsi" + +/ { + model = "MikroTik CRS328-4C-20S-4S+ Bit"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts new file mode 100644 index 000000000000..665757f6e18e --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS328-4C-20S-4S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs328-4c-20s-4s.dtsi" + +/ { + model = "MikroTik CRS328-4C-20S-4S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi new file mode 100644 index 000000000000..7028482ce4b2 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS328-4C-20S-4S+ board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS328-4C-20S-4S+"; + compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts new file mode 100644 index 000000000000..02bef8dc4270 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for DB-DXBC2 board + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx4251.dtsi" + +/ { + model = "Marvell Bobcat2 Evaluation Board"; + compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; + +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; +}; + +&sdio { + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00140000 0x00ec0000>; + label = "unused"; + }; + + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts new file mode 100644 index 000000000000..d1b61dad0c46 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for DB-XC3-24G4XG board + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3336.dtsi" + +/ { + model = "DB-XC3-24G4XG"; + compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00140000 0x00ec0000>; + label = "unused"; + }; + + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-db.dts b/arch/arm/boot/dts/marvell/armada-xp-db.dts new file mode 100644 index 000000000000..75318fd0fc11 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-db.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada XP evaluation board + * (DB-78460-BP) + * + * Copyright (C) 2012-2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP Evaluation Board"; + compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + internal-regs { + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <3>; + }; + + bm@c0000 { + status = "okay"; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + usb@52000 { + status = "okay"; + }; + + nand-controller@d0000 { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; + }; + }; + + bm-bppi { + status = "okay"; + }; + }; +}; + +&pciec { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@a,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <25>; + }; + + phy3: ethernet-phy@3 { + reg = <27>; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-gp.dts b/arch/arm/boot/dts/marvell/armada-xp-gp.dts new file mode 100644 index 000000000000..d1d348b91c0a --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-gp.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada XP development board + * (DB-MV784MP-GP) + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP Development Board DB-MV784MP-GP"; + compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + /* + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). + */ + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, + <0x00000001 0x00000000 0x00000001 0x00000000>; + }; + + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + ranges = ; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + internal-regs { + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <3>; + }; + + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + + bm@c0000 { + status = "okay"; + }; + + nand-controller@d0000 { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + }; + }; + }; + + bm-bppi { + status = "okay"; + }; + }; +}; + +&pciec { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@a,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts new file mode 100644 index 000000000000..21b95578fe95 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Lenovo Iomega ix4-300d + * + * Copyright (C) 2014, Benoit Masson + */ + +/dts-v1/; + +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Lenovo Iomega ix4-300d"; + compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512MB */ + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + adt7473@2e { + compatible = "adi,adt7473"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + }; + + nand-controller@d0000 { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000e0000>; + read-only; + }; + + partition@e0000 { + label = "u-boot-env"; + reg = <0x000e0000 0x00020000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env2"; + reg = <0x00100000 0x00020000>; + read-only; + }; + + partition@120000 { + label = "zImage"; + reg = <0x00120000 0x00400000>; + }; + + partition@520000 { + label = "initrd"; + reg = <0x00520000 0x00400000>; + }; + + partition@e00000 { + label = "boot"; + reg = <0x00e00000 0x3f200000>; + }; + }; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin &reset_button_pin + &select_button_pin &scroll_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + select-button { + label = "Select Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + scroll-button { + label = "Scroll Button"; + linux,code = ; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + }; + + spi-3 { + compatible = "spi-gpio"; + status = "okay"; + sck-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + mosi-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ + cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&hdd_led_pin>; + pinctrl-names = "default"; + + hdd-led { + label = "ix4-300d:hdd:blue"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power-led { + label = "ix4-300d:power:white"; + gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; + /* init blinking while booting */ + linux,default-trigger = "timer"; + default-state = "on"; + }; + + sysfail-led { + label = "ix4-300d:sysfail:red"; + gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + sys-led { + label = "ix4-300d:sys:blue"; + gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + hddfail-led { + label = "ix4-300d:hddfail:red"; + gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + }; + + /* + * Warning: you need both eth1 & 0 PHY initialized (i.e having + * them up does the tweak) for poweroff to shutdown otherwise it + * reboots + */ + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff_pin>; + pinctrl-names = "default"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; +}; +&pciec { + status = "okay"; + + /* Quad port sata: Marvell 88SX7042 */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* USB 3.0 xHCI controller: NEC D720200F1 */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + +&pinctrl { + poweroff_pin: poweroff-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + select_button_pin: select-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + scroll_button_pin: scroll-button-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + hdd_led_pin: hdd-led-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts new file mode 100644 index 000000000000..7a0614fd0c93 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Linksys WRT1900AC (Mamba). + * + * Note: this board is shipped with a new generation boot loader that + * remaps internal registers at 0xf1000000. Therefore, if earlyprintk + * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be + * used. + * + * Copyright (C) 2014 Imre Kaloz + * + * Based on armada-xp-axpwifiap.dts: + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni + */ + +/dts-v1/; +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Linksys WRT1900AC"; + compatible = "linksys,mamba", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ + }; + + soc { + ranges = ; + + internal-regs { + + rtc@10300 { + /* No crystal connected to the internal RTC */ + status = "disabled"; + }; + + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tlc59116@68 { + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <2>; + compatible = "ti,tlc59116"; + reg = <0x68>; + + wan_amber@0 { + label = "mamba:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "mamba:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "mamba:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "mamba:white:wlan_5g"; + reg = <0x3>; + }; + + esata@4 { + label = "mamba:white:esata"; + reg = <0x4>; + linux,default-trigger = "disk-activity"; + }; + + usb2@5 { + label = "mamba:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "mamba:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "mamba:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "mamba:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "mamba:amber:wps"; + reg = <0x9>; + }; + }; + }; + + bm@c8000 { + status = "okay"; + }; + }; + + bm-bppi { + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin>; + pinctrl-names = "default"; + + led-power { + label = "mamba:white:power"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + pwm_fan { + /* SUNON HA4010V4-0000-C99 */ + + compatible = "pwm-fan"; + pwms = <&gpio0 24 4000>; + }; +}; + +&pciec { + status = "okay"; + + /* Etron EJ168 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* First mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; +}; + +&pinctrl { + + keys_pin: keys-pin { + marvell,pins = "mpp32", "mpp33"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + gpio_fan_pin: gpio-fan-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <40000000>; + }; +}; + +&mdio { + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "internet"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x100000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x140000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@d00000 { + label = "rootfs1"; + reg = <0xd00000 0x2500000>; /* 37MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3500000 { + label = "rootfs2"; + reg = <0x3500000 0x2500000>; /* 37MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x180000 0x780000>; /* 7.5MB */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-matrix.dts b/arch/arm/boot/dts/marvell/armada-xp-matrix.dts new file mode 100644 index 000000000000..1395cea12759 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-matrix.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada XP Matrix board + * + * Copyright (C) 2013 Marvell + * + * Lior Amsalem + */ + +/dts-v1/; +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP Matrix Board"; + compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + /* + * This board has 4 GB of RAM, but the last 256 MB of + * RAM are not usable due to the overlap with the MBus + * Window address range + */ + reg = <0 0x00000000 0 0xf0000000>; + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + usb@50000 { + status = "okay"; + }; + }; + }; +}; + +&pciec { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi new file mode 100644 index 000000000000..5ea9d509cd30 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * Contains definitions specific to the Armada XP MV78230 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78230 SoC"; + compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + /* + * MV78230 has 2 PCIe units Gen2.0: One unit can be + * configured as x4 or quad x1 lanes. One unit is + * x1 only. + */ + pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; + + pcie1: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie2: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie3: pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie4: pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie5: pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; + clocks = <&coreclk 0>; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv78230-pinctrl"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi new file mode 100644 index 000000000000..6c6fbb9faf5a --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * Contains definitions specific to the Armada XP MV78260 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78260 SoC"; + compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + /* + * MV78260 has 3 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. One unit is + * x4 only. + */ + pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ + + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; + + pcie1: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie2: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie3: pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie4: pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie5: pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie6: pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 63>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie7: pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 64>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie8: pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 65>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie9: pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 99>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <91>; + }; + + eth3: ethernet@34000 { + compatible = "marvell,armada-xp-neta"; + reg = <0x34000 0x4000>; + interrupts = <14>; + clocks = <&gateclk 1>; + status = "disabled"; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv78260-pinctrl"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi new file mode 100644 index 000000000000..16185edf9aa5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * Contains definitions specific to the Armada XP MV78460 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78460 SoC"; + compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <2>; + clocks = <&cpuclk 2>; + clock-latency = <1000000>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <3>; + clocks = <&cpuclk 3>; + clock-latency = <1000000>; + }; + }; + + soc { + /* + * MV78460 has 4 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. Two units are + * x4/x1. + */ + pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ + + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ + + 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ + 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; + + pcie1: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie2: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie3: pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie4: pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie5: pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie6: pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 63>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie7: pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 64>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie8: pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 65>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie9: pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 99>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie10: pcie@a,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 103>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie10_intc 0>, + <0 0 0 2 &pcie10_intc 1>, + <0 0 0 3 &pcie10_intc 2>, + <0 0 0 4 &pcie10_intc 3>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + + pcie10_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <91>; + }; + + eth3: ethernet@34000 { + compatible = "marvell,armada-xp-neta"; + reg = <0x34000 0x4000>; + interrupts = <14>; + clocks = <&gateclk 1>; + status = "disabled"; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv78460-pinctrl"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts new file mode 100644 index 000000000000..31933f81144e --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NETGEAR ReadyNAS 2120 + * + * Copyright (C) 2013, Arnaud EBALARD + */ + +/dts-v1/; + +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "NETGEAR ReadyNAS 2120"; + compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x00000000 0 0x80000000>; /* 2GB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* RTC is provided by Intersil ISL12057 I2C RTC chip */ + rtc@10300 { + status = "disabled"; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + /* Controller for rear fan #1 of 3 (Protechnic + * MGT4012XB-O20, 8000RPM) near eSATA port */ + g762_fan1: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Controller for rear (center) fan #2 of 3 */ + g762_fan2: g762@48 { + compatible = "gmt,g762"; + reg = <0x48>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Controller for rear fan #3 of 3 */ + g762_fan3: g762@49 { + compatible = "gmt,g762"; + reg = <0x49>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Temperature sensor */ + g751: g751@4c { + compatible = "gmt,g751"; + reg = <0x4c>; + }; + + isl12057: rtc@68 { + compatible = "isil,isl12057"; + reg = <0x68>; + wakeup-source; + }; + }; + + serial@12000 { + status = "okay"; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + /* Two rear eSATA ports */ + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin + &sata3_led_pin &sata4_led_pin>; + pinctrl-names = "default"; + + red-sata1-led { + label = "rn2120:red:sata1"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata2-led { + label = "rn2120:red:sata2"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata3-led { + label = "rn2120:red:sata3"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata4-led { + label = "rn2120:red:sata4"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-err-led { + label = "rn2120:red:err"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin &reset_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; +}; + +&pciec { + status = "okay"; + + /* Connected to first Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to second Marvell 88SE9170 SATA controller */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Connected to Fresco Logic FL1009 USB 3.0 controller */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + + +&pinctrl { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata3_led_pin: sata3-led-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata4_led_pin: sata4-led-pin { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + sata1_power_pin: sata1-power-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + sata2_power_pin: sata2-power-pin { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + sata3_power_pin: sata3-power-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + sata4_power_pin: sata4-power-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + err_led_pin: err-led-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts new file mode 100644 index 000000000000..1ecf72a61bca --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for OpenBlocks AX3-4 board + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + */ + +/dts-v1/; +#include +#include +#include "armada-xp-mv78260.dtsi" + +/ { + model = "PlatHome OpenBlocks AX3-4 board"; + compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ + }; + + soc { + ranges = ; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 128 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x8000000>; + bank-width = <2>; + }; + }; + + internal-regs { + rtc@10300 { + /* No crystal connected to the internal RTC */ + status = "disabled"; + }; + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + red_led { + label = "red_led"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + yellow_led { + label = "yellow_led"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + green_led { + label = "green_led"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-init { + label = "Init Button"; + linux,code = ; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <3>; + }; + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + }; + i2c@11100 { + status = "okay"; + clock-frequency = <400000>; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + /* Front side USB 0 */ + usb@50000 { + status = "okay"; + }; + + /* Front side USB 1 */ + usb@51000 { + status = "okay"; + }; + + bm@c0000 { + status = "okay"; + }; + }; + + bm-bppi { + status = "okay"; + }; + }; +}; + +&pciec { + status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +&pinctrl { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts new file mode 100644 index 000000000000..5551bac1962c --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Synology DS414 + * + * Copyright (C) 2014, Arnaud EBALARD + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Synology DS414"; + compatible = "synology,ds414", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* RTC is provided by Seiko S-35390A below */ + rtc@10300 { + status = "disabled"; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB. This + * provides the main console for the device. + * + * Warning: the device may not boot with a 3.3V + * USB-serial converter connected when the power + * button is pressed. The converter needs to be + * connected a few seconds after pressing the + * power button. This is possibly due to UART0_TXD + * pin being sampled at reset (bit 0 of SAR). + */ + serial@12000 { + status = "okay"; + }; + + /* Connected to a Microchip PIC16F883 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin + &sata3_pwr_pin &sata4_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + sata3_regulator: sata3-regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + sata4_regulator: sata4-regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pciec { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + +&pinctrl { + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata3_pwr_pin: sata3-pwr-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + sata4_pwr_pin: sata4-pwr-pin { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + fan1_alarm_pin: fan1-alarm-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + fan2_alarm_pin: fan2-alarm-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@0 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@3a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@7d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@7e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@7f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-xp.dtsi b/arch/arm/boot/dts/marvell/armada-xp.dtsi new file mode 100644 index 000000000000..4297482da62f --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-xp.dtsi @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * Ben Dooks + * + * Contains definitions specific to the Armada XP SoC that are not + * common to all Armada SoCs. + */ + +#include "armada-370-xp.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + + model = "Marvell Armada XP family SoC"; + compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + serial2 = &uart2; + serial3 = &uart3; + }; + + soc { + compatible = "marvell,armadaxp-mbus", "simple-bus"; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + internal-regs { + sdramc: sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + + L2: l2-cache@8000 { + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; + cache-level = <2>; + cache-unified; + wt-override; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <43>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <44>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + systemc: system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-xp-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18230 { + compatible = "marvell,armada-xp-core-clock"; + reg = <0x18230 0x08>; + #clock-cells = <1>; + }; + + thermal: thermal@182b0 { + compatible = "marvell,armadaxp-thermal"; + reg = <0x182b0 0x4 + 0x184d0 0x4>; + status = "okay"; + }; + + cpuclk: clock-complex@18700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clock"; + reg = <0x18700 0x24>, <0x1c054 0x10>; + clocks = <&coreclk 1>; + }; + + cpu-config@21000 { + compatible = "marvell,armada-xp-cpu-config"; + reg = <0x21000 0x8>; + }; + + eth2: ethernet@30000 { + compatible = "marvell,armada-xp-neta"; + reg = <0x30000 0x4000>; + interrupts = <12>; + clocks = <&gateclk 2>; + status = "disabled"; + }; + + usb2: usb@52000 { + compatible = "marvell,orion-ehci"; + reg = <0x52000 0x500>; + interrupts = <47>; + clocks = <&gateclk 20>; + status = "disabled"; + }; + + xor1: xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor10 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + ethernet@70000 { + compatible = "marvell,armada-xp-neta"; + }; + + ethernet@74000 { + compatible = "marvell,armada-xp-neta"; + }; + + cesa: crypto@90000 { + compatible = "marvell,armada-xp-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <48>, <49>; + clocks = <&gateclk 23>, <&gateclk 23>; + clock-names = "cesa0", "cesa1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + + bm: bm@c0000 { + compatible = "marvell,armada-380-neta-bm"; + reg = <0xc0000 0xac>; + clocks = <&gateclk 13>; + internal-mem = <&bm_bppi>; + status = "disabled"; + }; + + xor0: xor@f0900 { + compatible = "marvell,orion-xor"; + reg = <0xF0900 0x100 + 0xF0B00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor00 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; + }; + + bm_bppi: bm-bppi { + compatible = "mmio-sram"; + reg = ; + ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gateclk 13>; + no-memory-wc; + status = "disabled"; + }; + }; + + clocks { + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; + +&i2c0 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +}; + +&i2c1 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; +}; + +&mpic { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; +}; + +&timer { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&watchdog { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + interrupts = <93>, <38>; +}; + +&cpurst { + reg = <0x20800 0x20>; +}; + +&usb0 { + clocks = <&gateclk 18>; +}; + +&usb1 { + clocks = <&gateclk 19>; +}; + +&pinctrl { + ge0_gmii_pins: ge0-gmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge0"; + }; + + ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge1"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp36", "mpp37", + "mpp38", "mpp39"; + marvell,function = "spi0"; + }; + + spi1_pins: spi1-pins { + marvell,pins = "mpp13", "mpp14", + "mpp16", "mpp17"; + marvell,function = "spi1"; + }; + + uart2_pins: uart2-pins { + marvell,pins = "mpp42", "mpp43"; + marvell,function = "uart2"; + }; + + uart3_pins: uart3-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "uart3"; + }; +}; + +&spi0 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi b/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi new file mode 100644 index 000000000000..1082fdfbfe60 --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi @@ -0,0 +1,203 @@ +/* + * Device Tree include for Compulab CM-A510 System-on-Module + * + * Copyright (C) 2015, Sebastian Hesselbarth + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The CM-A510 comes with several optional components: + * + * Memory options: + * D512: 512M + * D1024: 1G + * + * NAND options: + * N512: 512M NAND + * + * Ethernet options: + * E1: PHY RTL8211D on internal GbE (SMI address 0x03) + * E2: Additional ethernet NIC RTL8111D on PCIe1 + * + * Audio options: + * A: TI TLV320AIC23b audio codec (I2C address 0x1a) + * + * Touchscreen options: + * I: TI TSC2046 touchscreen controller (on SPI1) + * + * USB options: + * U2: 2 dual-role USB2.0 ports + * U4: 2 additional USB2.0 host ports (via USB1) + * + * WiFi options: + * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1) + * + * GPIOs used on CM-A510: + * 1 GbE PHY reset (active low) + * 3 WakeUp + * 8 PowerOff (active low) + * 13 Touchscreen pen irq (active low) + * 65 System LED (active high) + * 69 USB Hub reset (active low) + * 70 WLAN reset (active low) + * 71 WLAN regulator (active high) + */ + +#include "dove.dtsi" + +/ { + model = "Compulab CM-A510"; + compatible = "compulab,cm-a510", "marvell,dove"; + + /* + * Set the minimum memory size here and let the + * bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + /* Set upper NAND data bit to GPO */ + pinctrl-0 = <&pmx_nand_gpo>; + pinctrl-names = "default"; + + led-system { + label = "cm-a510:system:green"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wifi_power: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "WiFi Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Optional RTL8211D GbE PHY on SMI address 0x03 */ +&mdio { + ethphy: ethernet-phy@3 { + reg = <3>; + status = "disabled"; + }; +}; + +ð { + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c0 { + /* Optional TI TLV320AIC23b audio codec */ + opt_audio: audio@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + status = "disabled"; + }; +}; + +/* Optional RTL8111D GbE NIC on PCIe1 */ +&pcie { status = "disabled"; }; + +&pcie1 { + pinctrl-0 = <&pmx_pcie1_clkreq>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&pinctrl { + pmx_uart2: pmx-uart2 { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "uart2"; + }; +}; + +/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */ +&sdio1 { + non-removable; + vmmc-supply = <&wifi_power>; + reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&spi0 { + status = "okay"; + + /* 1M Flash Winbond W25Q80BL */ + flash@0 { + compatible = "winbond,w25q80"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&spi1 { + pinctrl-0 = <&pmx_spi1_20_23>; + pinctrl-names = "default"; + status = "disabled"; + + /* Optional TI TSC2046 touchscreen controller */ + opt_touch: touchscreen@0 { + compatible = "ti,tsc2046"; + spi-max-frequency = <2500000>; + reg = <0>; + pinctrl-0 = <&pmx_gpio_13>; + pinctrl-names = "default"; + interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&uart2 { + pinctrl-0 = <&pmx_uart2>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/marvell/dove-cubox-es.dts b/arch/arm/boot/dts/marvell/dove-cubox-es.dts new file mode 100644 index 000000000000..ad361ec1361d --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-cubox-es.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "dove-cubox.dts" + +/ { + model = "SolidRun CuBox (Engineering Sample)"; + compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; +}; + +&sdio0 { + /* sdio0 card detect is connected to wrong pin on CuBox ES */ + cd-gpios = <&gpio0 12 1>; + pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; +}; diff --git a/arch/arm/boot/dts/marvell/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts new file mode 100644 index 000000000000..dbba0c8cdab1 --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-cubox.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "dove.dtsi" + +/ { + model = "SolidRun CuBox"; + compatible = "solidrun,cubox", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_18>; + pinctrl-names = "default"; + + led-power { + label = "Power"; + gpios = <&gpio0 18 1>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 1 0>; + pinctrl-0 = <&pmx_gpio_1>; + pinctrl-names = "default"; + }; + }; + + clocks { + /* 25MHz reference crystal */ + ref25: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 19 1>; + pinctrl-0 = <&pmx_gpio_19>; + pinctrl-names = "default"; + }; + + gpu-subsystem { + status = "okay"; + }; +}; + +&uart0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&mdio { status = "okay"; }; +ð { + status = "okay"; + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&mdio { + ethphy: ethernet-phy@1 { + compatible = "marvell,88e1310"; + reg = <1>; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + si5351: clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* connect xtal input to 25MHz reference */ + clocks = <&ref25>; + clock-names = "xtal"; + + /* connect xtal input as source of pll0 and pll1 */ + silabs,pll-source = <0 0>, <1 0>; + + clkout0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + }; + + clkout2 { + reg = <2>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + }; + }; +}; + +&sdio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Winbond W25Q32BV */ + flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&audio1 { + status = "okay"; + clocks = <&gate_clk 13>, <&si5351 2>; + clock-names = "internal", "extclk"; + pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/marvell/dove-d2plug.dts b/arch/arm/boot/dts/marvell/dove-d2plug.dts new file mode 100644 index 000000000000..79ee2b32409d --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-d2plug.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "dove.dtsi" + +/ { + model = "Globalscale D2Plug"; + compatible = "globalscale,d2plug", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; + pinctrl-names = "default"; + + led-wlan-ap { + label = "wlan-ap"; + gpios = <&gpio0 0 1>; + }; + + led-wlan-act { + label = "wlan-act"; + gpios = <&gpio0 1 1>; + }; + + led-bluetooth-act { + label = "bt-act"; + gpios = <&gpio0 2 1>; + }; + }; +}; + +&uart0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&i2c0 { status = "okay"; }; +&mdio { status = "okay"; }; +ð { status = "okay"; }; + +/* Samsung M8G2F eMMC */ +&sdio0 { + status = "okay"; + non-removable; + bus-width = <4>; +}; + +/* Marvell SD8787 WLAN/BT */ +&sdio1 { + status = "okay"; + non-removable; + bus-width = <4>; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Macronix MX25L3205D */ + flash@0 { + compatible = "st,m25l3205d"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/dove-d3plug.dts b/arch/arm/boot/dts/marvell/dove-d3plug.dts new file mode 100644 index 000000000000..5aa5d4a7d51d --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-d3plug.dts @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "dove.dtsi" + +/ { + model = "Globalscale D3Plug"; + compatible = "globalscale,d3plug", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; + pinctrl-names = "default"; + + led-wlan-act { + label = "wlan-act"; + gpios = <&gpio0 0 1>; + }; + + led-wlan-ap { + label = "wlan-ap"; + gpios = <&gpio0 1 1>; + }; + + led-status { + label = "status"; + gpios = <&gpio0 2 1>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 8 0>; + pinctrl-0 = <&pmx_gpio_8>; + pinctrl-names = "default"; + }; + }; +}; + +&uart0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&i2c0 { status = "okay"; }; + +/* Samsung M8G2F eMMC */ +&sdio0 { + status = "okay"; + non-removable; + bus-width = <4>; +}; + +/* Marvell SD8787 WLAN/BT */ +&sdio1 { + status = "okay"; + non-removable; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 2M Flash Macronix MX25L1605D */ + flash@0 { + compatible = "st,m25l1605d"; + spi-max-frequency = <86000000>; + reg = <0>; + }; +}; + +&pcie { + status = "okay"; + /* Fresco Logic USB3.0 xHCI controller */ + pcie@1 { + status = "okay"; + reset-gpios = <&gpio0 26 1>; + reset-delay-us = <20000>; + pinctrl-0 = <&pmx_camera_gpio>; + pinctrl-names = "default"; + }; + /* Mini-PCIe slot */ + pcie@2 { + status = "okay"; + reset-gpios = <&gpio0 25 1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/dove-dove-db.dts b/arch/arm/boot/dts/marvell/dove-dove-db.dts new file mode 100644 index 000000000000..c1912dc6bfc3 --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-dove-db.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "dove.dtsi" + +/ { + model = "Marvell DB-MV88AP510-BP Development Board"; + compatible = "marvell,dove-db", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; +}; + +&uart0 { status = "okay"; }; +&uart1 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sdio1 { status = "okay"; }; +&sata0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash ST-M25P32-VMF6P */ + flash@0 { + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/dove-sbc-a510.dts b/arch/arm/boot/dts/marvell/dove-sbc-a510.dts new file mode 100644 index 000000000000..df021f9b0117 --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove-sbc-a510.dts @@ -0,0 +1,183 @@ +/* + * Device Tree file for Compulab SBC-A510 Single Board Computer + * + * Copyright (C) 2015, Sebastian Hesselbarth + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to + * + * 0.0 USB0 VBUS_EN (active high) + * 0.1 USB0 VBUS_GOOD + * 0.2 DVI transmitter TI TFP410 MSEN + * 0.3 DVI transmitter TI TFP410 PD# (active low power down) + * 0.4 LVDS transmitter DS90C365 PD# (active low power down) + * 0.5 LCD nRST (active low reset) + * 0.6 PCIe0 nRST (active low reset) + * 0.7 mini-PCIe slot W_DISABLE# + * + * 1.0 MMC WP + * 1.1 Camera Input FPC FLASH_STB and P21.5 + * 1.2 Camera Input FPC WE and P21.22 + * 1.3 MMC VCC_EN (active high) and P21.7 + * 1.4 Camera Input FPC AFTR_RST and P21.17 + * 1.5 Camera Input FPC OE and P21.19 + * 1.6 Camera Input FPC SNPSHT and P21.6 + * 1.7 Camera Input FPC SHTR and P21.10 + */ + +/dts-v1/; + +#include "dove-cm-a510.dtsi" + +/ { + model = "Compulab SBC-A510"; + compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove"; + + chosen { + stdout-path = &uart0; + }; + + regulators { + usb0_power: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; + }; + + mmc_power: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "MMC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Ethernet0 depends on CM-A510 option E1 */ +&mdio { status = "disabled"; }; +ð { status = "disabled"; }; +ðphy { status = "disabled"; }; + +/* + * USB port 0 can be powered and monitored by I2C GPIO expander: + * VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1 + */ +&ehci0 { + status = "okay"; + vbus-supply = <&usb0_power>; +}; + +/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */ +&ehci1 { status = "okay"; }; + +/* + * I2C bus layout: + * i2c0: + * - Audio Codec, 0x1a (option from CM-A510) + * - DVI transmitter TI TFP410, 0x39 + * - HDMI/DVI DDC channel + * i2c1: + * - GPIO expander, NXP PCA9555, 0x20 + * - VGA DDC channel + */ +&i2c { + pinctrl-0 = <&pmx_i2c1>; + pinctrl-names = "default"; +}; + +&i2c0 { + /* TI TFP410 DVI transmitter */ + dvi: video@39 { + compatible = "ti,tfp410"; + reg = <0x39>; + powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + /* NXP PCA9555 GPIO expander */ + gpio_ext: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&pcie { status = "okay"; }; + +/* + * PCIe0 can be configured by Jumper E1 to be either connected to + * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge. + */ +&pcie0 { + status = "okay"; + pinctrl-0 = <&pmx_pcie0_clkreq>; + pinctrl-names = "default"; + reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>; +}; + +/* Ethernet1 depends on CM-A510 option E2 */ +&pcie1 { status = "disabled"; }; + +/* SATA connector */ +&sata0 { status = "okay"; }; + +/* + * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has + * VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10 + */ +&sdio0 { + vmmc-supply = <&mmc_power>; + wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* UART0 on RS232 mini-connector */ +&uart0 { status = "okay"; }; +/* UART2 on pin headers */ +&uart2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/marvell/dove.dtsi b/arch/arm/boot/dts/marvell/dove.dtsi new file mode 100644 index 000000000000..062c86361640 --- /dev/null +++ b/arch/arm/boot/dts/marvell/dove.dtsi @@ -0,0 +1,820 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "marvell,dove"; + model = "Marvell Armada 88AP510 SoC"; + interrupt-parent = <&intc>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "marvell,pj4a", "marvell,sheeva-v7"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + }; + + l2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0>; + }; + + gpu-subsystem { + compatible = "marvell,dove-gpu-subsystem"; + cores = <&gpu>; + status = "disabled"; + }; + + i2c-mux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c>; + + pinctrl-names = "i2c0", "i2c1", "i2c2"; + pinctrl-0 = <&pmx_i2cmux_0>; + pinctrl-1 = <&pmx_i2cmux_1>; + pinctrl-2 = <&pmx_i2cmux_2>; + + i2c0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + i2c1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + /* Requires pmx_i2c1 on i2c controller node */ + status = "disabled"; + }; + + i2c2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + /* Requires pmx_i2c2 on i2c controller node */ + status = "disabled"; + }; + }; + + mbus { + compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ + pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ + + ranges = ; /* PMU SRAM 1M */ + + pcie: pcie { + compatible = "marvell,dove-pcie"; + status = "disabled"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&intc>; + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 + 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 + 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ + 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ + 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ + 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ + + pcie0: pcie@1 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + clocks = <&gate_clk 4>; + marvell,pcie-port = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; + interrupt-names = "intx", "error"; + interrupts = <16>, <15>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@2 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + clocks = <&gate_clk 5>; + marvell,pcie-port = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + + #interrupt-cells = <1>; + interrupt-names = "intx", "error"; + interrupts = <18>, <17>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ + 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ + 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ + 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; + clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_spi0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + clocks = <&core_clk 0>; + status = "okay"; + }; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <7>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "ns16550a"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "ns16550a"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + spi1: spi@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + mbusc: mbus-ctrl@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x800100 0x8>; + }; + + sysc: system-ctrl@20000 { + compatible = "marvell,orion-system-controller"; + reg = <0x20000 0x110>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <5>; + }; + + intc: interrupt-controller@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + watchdog@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>, <0x20108 0x4>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; + clocks = <&core_clk 0>; + }; + + crypto: crypto-engine@30000 { + compatible = "marvell,dove-crypto"; + reg = <0x30000 0x10000>; + reg-names = "regs"; + interrupts = <31>; + clocks = <&gate_clk 15>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x800>; + status = "okay"; + }; + + ehci0: usb-host@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <24>; + clocks = <&gate_clk 0>; + status = "okay"; + }; + + ehci1: usb-host@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x1000>; + interrupts = <25>; + clocks = <&gate_clk 1>; + status = "okay"; + }; + + xor0: dma-engine@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gate_clk 23>; + status = "okay"; + + channel0 { + interrupts = <39>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <40>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + xor1: dma-engine@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gate_clk 24>; + status = "okay"; + + channel0 { + interrupts = <42>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <43>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + sdio1: sdio-host@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + clocks = <&gate_clk 9>; + pinctrl-0 = <&pmx_sdio1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + eth: ethernet-ctrl@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 2>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <29>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <30>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + + sdio0: sdio-host@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + clocks = <&gate_clk 8>; + pinctrl-0 = <&pmx_sdio0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata0: sata-host@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + clocks = <&gate_clk 3>; + phys = <&sata_phy0>; + phy-names = "port0"; + nr-ports = <1>; + status = "disabled"; + }; + + sata_phy0: sata-phy@a2000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0xa2000 0x0334>; + clocks = <&gate_clk 3>; + clock-names = "sata"; + #phy-cells = <0>; + status = "okay"; + }; + + audio0: audio-controller@b0000 { + compatible = "marvell,dove-audio"; + reg = <0xb0000 0x2210>; + interrupts = <19>, <20>; + clocks = <&gate_clk 12>; + clock-names = "internal"; + status = "disabled"; + }; + + audio1: audio-controller@b4000 { + compatible = "marvell,dove-audio"; + reg = <0xb4000 0x2210>; + interrupts = <21>, <22>; + clocks = <&gate_clk 13>; + clock-names = "internal"; + status = "disabled"; + }; + + pmu: power-management@d0000 { + compatible = "marvell,dove-pmu", "simple-bus"; + reg = <0xd0000 0x8000>, <0xd8000 0x8000>; + ranges = <0x00000000 0x000d0000 0x8000 + 0x00008000 0x000d8000 0x8000>; + interrupts = <33>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + #reset-cells = <1>; + + domains { + vpu_domain: vpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000008>; + marvell,pmu_iso_mask = <0x00000001>; + resets = <&pmu 16>; + }; + + gpu_domain: gpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000004>; + marvell,pmu_iso_mask = <0x00000002>; + resets = <&pmu 18>; + }; + }; + + thermal: thermal-diode@1c { + compatible = "marvell,dove-thermal"; + reg = <0x001c 0x0c>, <0x005c 0x08>; + }; + + gate_clk: clock-gating-ctrl@38 { + compatible = "marvell,dove-gating-clock"; + reg = <0x0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + divider_clk: core-clock@64 { + compatible = "marvell,dove-divider-clock"; + reg = <0x0064 0x8>; + #clock-cells = <1>; + }; + + pinctrl: pin-ctrl@200 { + compatible = "marvell,dove-pinctrl"; + reg = <0x0200 0x14>, + <0x0440 0x04>; + clocks = <&gate_clk 22>; + + pmx_gpio_0: pmx-gpio-0 { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_gpio_1: pmx-gpio-1 { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_gpio_2: pmx-gpio-2 { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_gpio_3: pmx-gpio-3 { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_gpio_4: pmx-gpio-4 { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + pmx_gpio_5: pmx-gpio-5 { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_6: pmx-gpio-6 { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_gpio_7: pmx-gpio-7 { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + pmx_gpio_8: pmx-gpio-8 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_9: pmx-gpio-9 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_pcie1_clkreq: pmx-pcie1-clkreq { + marvell,pins = "mpp9"; + marvell,function = "pex1"; + }; + + pmx_gpio_10: pmx-gpio-10 { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + pmx_gpio_11: pmx-gpio-11 { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + pmx_pcie0_clkreq: pmx-pcie0-clkreq { + marvell,pins = "mpp11"; + marvell,function = "pex0"; + }; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_gpio_13: pmx-gpio-13 { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_audio1_extclk: pmx-audio1-extclk { + marvell,pins = "mpp13"; + marvell,function = "audio1"; + }; + + pmx_gpio_14: pmx-gpio-14 { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_gpio_15: pmx-gpio-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_gpio_16: pmx-gpio-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_gpio_17: pmx-gpio-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_gpio_19: pmx-gpio-19 { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_gpio_20: pmx-gpio-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_gpio_21: pmx-gpio-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_camera: pmx-camera { + marvell,pins = "mpp_camera"; + marvell,function = "camera"; + }; + + pmx_camera_gpio: pmx-camera-gpio { + marvell,pins = "mpp_camera"; + marvell,function = "gpio"; + }; + + pmx_sdio0: pmx-sdio0 { + marvell,pins = "mpp_sdio0"; + marvell,function = "sdio0"; + }; + + pmx_sdio0_gpio: pmx-sdio0-gpio { + marvell,pins = "mpp_sdio0"; + marvell,function = "gpio"; + }; + + pmx_sdio1: pmx-sdio1 { + marvell,pins = "mpp_sdio1"; + marvell,function = "sdio1"; + }; + + pmx_sdio1_gpio: pmx-sdio1-gpio { + marvell,pins = "mpp_sdio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_gpio: pmx-audio1-gpio { + marvell,pins = "mpp_audio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { + marvell,pins = "mpp_audio1"; + marvell,function = "i2s1/spdifo"; + }; + + pmx_spi0: pmx-spi0 { + marvell,pins = "mpp_spi0"; + marvell,function = "spi0"; + }; + + pmx_spi0_gpio: pmx-spi0-gpio { + marvell,pins = "mpp_spi0"; + marvell,function = "gpio"; + }; + + pmx_spi1_4_7: pmx-spi1-4-7 { + marvell,pins = "mpp4", "mpp5", + "mpp6", "mpp7"; + marvell,function = "spi1"; + }; + + pmx_spi1_20_23: pmx-spi1-20-23 { + marvell,pins = "mpp20", "mpp21", + "mpp22", "mpp23"; + marvell,function = "spi1"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; + + pmx_uart1_gpio: pmx-uart1-gpio { + marvell,pins = "mpp_uart1"; + marvell,function = "gpio"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp_nand"; + marvell,function = "nand"; + }; + + pmx_nand_gpo: pmx-nand-gpo { + marvell,pins = "mpp_nand"; + marvell,function = "gpo"; + }; + + pmx_i2c1: pmx-i2c1 { + marvell,pins = "mpp17", "mpp19"; + marvell,function = "twsi"; + }; + + pmx_i2c2: pmx-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "twsi"; + }; + + pmx_ssp_i2c2: pmx-ssp-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "ssp/twsi"; + }; + + pmx_i2cmux_0: pmx-i2cmux-0 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt1"; + }; + + pmx_i2cmux_1: pmx-i2cmux-1 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt2"; + }; + + pmx_i2cmux_2: pmx-i2cmux-2 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt3"; + }; + }; + + core_clk: core-clocks@214 { + compatible = "marvell,dove-core-clock"; + reg = <0x0214 0x4>; + #clock-cells = <1>; + }; + + gpio0: gpio-ctrl@400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio-ctrl@420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <61>; + }; + + rtc: real-time-clock@8500 { + compatible = "marvell,orion-rtc"; + reg = <0x8500 0x20>; + interrupts = <5>; + }; + }; + + gconf: global-config@e802c { + compatible = "marvell,dove-global-config", + "syscon"; + reg = <0xe802c 0x14>; + }; + + gpio2: gpio-ctrl@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpios = <8>; + }; + + lcd1: lcd-controller@810000 { + compatible = "marvell,dove-lcd"; + reg = <0x810000 0x1000>; + interrupts = <46>; + status = "disabled"; + }; + + lcd0: lcd-controller@820000 { + compatible = "marvell,dove-lcd"; + reg = <0x820000 0x1000>; + interrupts = <47>; + status = "disabled"; + }; + + crypto_sram: sram@ffffe000 { + compatible = "mmio-sram"; + reg = <0xffffe000 0x800>; + clocks = <&gate_clk 15>; + #address-cells = <1>; + #size-cells = <1>; + }; + + gpu: gpu@840000 { + clocks = <÷r_clk 1>; + clock-names = "core"; + compatible = "vivante,gc"; + interrupts = <48>; + power-domains = <&gpu_domain>; + reg = <0x840000 0x4000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts b/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts new file mode 100644 index 000000000000..b1749d3f60b7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Endian 4i Edge 200 Board Description + * Note: Endian UTM Mini is hardware clone of Endian Edge 200 + * Copyright 2021-2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include + +/ { + model = "Endian 4i Edge 200"; + compatible = "endian,4i-edge-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_SD; + color = ; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +ð0port { + speed = <1000>; + duplex = <1>; +}; + +ð1 { + status = "okay"; +}; + +ð1port { + phy-handle = <ðphyb>; +}; + +&mdio { + status = "okay"; + + ethphyb: ethernet-phy@b { + reg = <0x0b>; + + marvell,reg-init = + /* link-activity, bi-color mode 4 */ + <3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */ + }; + + switch0: switch@11 { + compatible = "marvell,mv88e6085"; + reg = <0x11>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "port4"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000a0000>; + read-only; + }; + + partition@a0000 { + label = "u-boot-env"; + reg = <0x000a0000 0x00060000>; + read-only; + }; + + partition@100000 { + label = "kernel"; + reg = <0x00100000 0x00400000>; + }; + + partition@500000 { + label = "ubi"; + reg = <0x00500000 0x1fb00000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_sysrst>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led: pmx-led { + marvell,pins = "mpp34", "mpp35", "mpp49"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&sdio { + pinctrl-0 = <&pmx_sdio_cd>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio0 28 9>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-6192.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6192.dtsi new file mode 100644 index 000000000000..705c0d7effed --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-6192.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + mbus@f1000000 { + pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + compatible = "marvell,88f6192-pinctrl"; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + rtc: rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata: sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; + status = "disabled"; + }; + + sdio: mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6281.dtsi new file mode 100644 index 000000000000..8e311165fd13 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-6281.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + mbus@f1000000 { + pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + compatible = "marvell,88f6281-pinctrl"; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + rtc: rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata: sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; + status = "disabled"; + }; + + sdio: mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-6282.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6282.dtsi new file mode 100644 index 000000000000..e33723160ce7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-6282.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + mbus@f1000000 { + pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <10>, <45>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; + ocp@f1000000 { + + pinctrl: pin-controller@10000 { + compatible = "marvell,88f6282-pinctrl"; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + + /* + * Default I2C1 pinctrl setting on mpp36/mpp37, + * overwrite marvell,pins on board level if required. + */ + pmx_twsi1: pmx-twsi1 { + marvell,pins = "mpp36", "mpp37"; + marvell,function = "twsi1"; + }; + + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + thermal: thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + + rtc: rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata: sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; + status = "disabled"; + }; + + sdio: mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi new file mode 100644 index 000000000000..c3469a2fc58a --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + mbus@f1000000 { + pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + compatible = "marvell,98dx4122-pinctrl"; + + }; + }; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-b3.dts b/arch/arm/boot/dts/marvell/kirkwood-b3.dts new file mode 100644 index 000000000000..681343c1357a --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-b3.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Excito Bubba B3 + * + * Copyright (C) 2013, Andrew Lunn + * + * + * Note: This requires a new'ish version of u-boot, which disables the + * L2 cache. If your B3 silently fails to boot, u-boot is probably too + * old. Either upgrade, or consider the following email: + * + * https://lists.debian.org/debian-arm/2012/08/msg00128.html + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Excito B3"; + compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + memory { /* 512 MB */ + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_button_power: pmx-button-power { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led-green { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_red: pmx-led-red { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_blue: pmx-led-blue { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_beeper: pmx-beeper { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + status = "okay"; + + m25p16@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p16", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0xc0000>; + label = "u-boot"; + }; + + partition@c0000 { + reg = <0xc0000 0x20000>; + label = "u-boot env"; + }; + + partition@e0000 { + reg = <0xe0000 0x120000>; + label = "data"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + /* + * There is something on the bus at address 0x64. + * Not yet identified what it is, maybe the eeprom + * for the Atheros WiFi chip? + */ + }; + + + serial@12000 { + /* Internal on test pins, 3.3v TTL + * UART0_RX = Testpoint 65 + * UART0_TX = Testpoint 66 + * See the Excito Wiki for more details. + */ + status = "okay"; + }; + + sata@80000 { + /* One internal, the second as eSATA */ + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-leds { + /* + * There is one LED "port" on the front and the colours + * mix together giving some interesting combinations. + */ + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_green &pmx_led_red + &pmx_led_blue >; + pinctrl-names = "default"; + + programming_led { + label = "bubba3:green:programming"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + error_led { + label = "bubba3:red:error"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + active_led { + label = "bubba3:blue:active"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_button_power>; + pinctrl-names = "default"; + + power-button { + /* On the back */ + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; + + beeper: beeper { + /* 4KHz Piezoelectric buzzer */ + compatible = "gpio-beeper"; + pinctrl-0 = <&pmx_beeper>; + pinctrl-names = "default"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; + + ethphy1: ethernet-phy@24 { + device_type = "ethernet-phy"; + reg = <24>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + +/* Wifi model has Atheros chipset on pcie port */ +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts new file mode 100644 index 000000000000..07fbfca444d5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Seagate Blackarmor NAS220 + * + * Copyright (C) 2014 Evgeni Dobrev + */ + +/dts-v1/; + +#include +#include +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "Seagate Blackarmor NAS220"; + compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", + "marvell,kirkwood"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + button { + label = "Power"; + linux,code = ; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue-power { + label = "nas220:blue:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; + pinctrl-names = "default"; + + sata0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* + * Serial port routed to connector CN5 + * + * pin 1 - TX (CPU's TX) + * pin 4 - RX (CPU's RX) + * pin 6 - GND + */ +&uart0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_button_reset &pmx_button_power>; + pinctrl-names = "default"; + + pmx_act_sata0: pmx-act-sata0 { + marvell,pins = "mpp15"; + marvell,function = "sata0"; + }; + + pmx_act_sata1: pmx-act-sata1 { + marvell,pins = "mpp16"; + marvell,function = "sata1"; + }; + + pmx_power_sata0: pmx-power-sata0 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_power_sata1: pmx-power-sata1 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_button_power: pmx-button-power { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&i2c0 { + status = "okay"; + + adt7476: thermal@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; +}; + +&nand { + status = "okay"; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts new file mode 100644 index 000000000000..f59ff7578dfc --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ctera C200 V1 Board Description + * Copyright 2021-2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include + +/ { + model = "Ctera C200 V1"; + compatible = "ctera,c200-v1", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + + usb1 { + label = "USB1 Button"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + usb2 { + label = "USB2 Button"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-3 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-8 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port2>; + }; + + led-11 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + led-12 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +ð0port { + phy-handle = <ðphy9>; +}; + +&i2c0 { + status = "okay"; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + + lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; +}; + +&mdio { + status = "okay"; + + ethphy9: ethernet-phy@9 { + reg = <9>; + }; +}; + +&nand { + status = "okay"; + chip-delay = <40>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x200000>; + }; + + partition@200000 { + label = "certificate"; + reg = <0x0200000 0x100000>; + }; + + partition@300000 { + label = "preset_cfg"; + reg = <0x0300000 0x100000>; + }; + + partition@400000 { + label = "dev_params"; + reg = <0x0400000 0x100000>; + }; + + partition@500000 { + label = "active_bank"; + reg = <0x0500000 0x0100000>; + }; + + partition@600000 { + label = "magic"; + reg = <0x0600000 0x0100000>; + }; + + partition@700000 { + label = "bank1"; + reg = <0x0700000 0x2800000>; + }; + + partition@2f00000 { + label = "bank2"; + reg = <0x2f00000 0x2800000>; + }; + + /* 0x5700000-0x5a00000 undefined in vendor firmware */ + + partition@5a00000 { + label = "reserved"; + reg = <0x5a00000 0x2000000>; + }; + + partition@7a00000 { + label = "rootfs"; + reg = <0x7a00000 0x8600000>; + }; +}; + +&pinctrl { + /* Buzzer gpios are connected to two pins of buzzer. + * This buzzer require a modulated signal from gpio. + * Leave it as is due lack of proper driver. + */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp12", "mpp13"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp14", "mpp15", "mpp16", "mpp17", "mpp38", + "mpp39", "mpp40", "mpp42", "mpp43", "mpp44", + "mpp45", "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp28", "mpp29", "mpp48", "mpp49"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts new file mode 100644 index 000000000000..448b0cd23b5f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "LaCie CloudBox"; + compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_cloudbox_sata0: pmx-cloudbox-sata0 { + marvell,pins = "mpp15"; + marvell,function = "sata0"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + pinctrl-0 = <&pmx_cloudbox_sata0>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <1>; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + power { + label = "Power push button"; + linux,code = ; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "cloudbox:red:fail"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + blue-sata { + label = "cloudbox:blue:sata"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-d2net.dts b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts new file mode 100644 index 000000000000..bd3b266dd766 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for d2 Network v2 + * + * Copyright (C) 2014 Simon Guinot + * +*/ + +/dts-v1/; + +#include +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie d2 Network v2"; + compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ns2-leds { + compatible = "lacie,ns2-leds"; + + blue-sata { + label = "d2net_v2:blue:sata"; + slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + modes-map = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "d2net_v2:red:fail"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts new file mode 100644 index 000000000000..a9a8e6b744c7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara + * Thomas Petazzoni + * + */ + +/dts-v1/; + +#include "kirkwood-db.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Marvell DB-88F6281-BP Development Board"; + compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts new file mode 100644 index 000000000000..6dc6579d4524 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell DB-88F6282-BP Development Board Setup + * + * Saeed Bishara + * Thomas Petazzoni + * + */ + +/dts-v1/; + +#include "kirkwood-db.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Marvell DB-88F6282-BP Development Board"; + compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-db.dtsi b/arch/arm/boot/dts/marvell/kirkwood-db.dtsi new file mode 100644 index 000000000000..6fe2e31534af --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-db.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell DB-{88F6281,88F6282}-BP Development Board Setup + * + * Saeed Bishara + * Thomas Petazzoni + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +#include "kirkwood.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pin-controller@10000 { + pmx_sdio_gpios: pmx-sdio-gpios { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + nr-ports = <2>; + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio_gpios>; + pinctrl-names = "default"; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&nand { + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts new file mode 100644 index 000000000000..0c0851cd9bec --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014 Claudio Leite + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "D-Link DIR-665"; + compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 =< &pmx_led_usb + &pmx_led_internet_blue + &pmx_led_internet_amber + &pmx_led_5g &pmx_led_status_blue + &pmx_led_wps &pmx_led_status_amber + &pmx_led_24g + &pmx_btn_restart &pmx_btn_wps>; + pinctrl-names = "default"; + + pmx_led_usb: pmx-led-usb { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_led_internet_blue: pmx-led-internet-blue { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_internet_amber: pmx-led-internet-amber { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_5g: pmx-led-5g { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_status_blue: pmx-led-status-blue { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_wps: pmx-led-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_status_amber: pmx-led-status-amber { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_24g: pmx-led-24g { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_btn_restart: pmx-btn-restart { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "nvram"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "kernel"; + reg = <0x40000 0x180000>; + }; + + partition@1c0000 { + label = "rootfs"; + reg = <0x1c0000 0xe00000>; + }; + + cal_data: partition@fc0000 { + label = "cal_data"; + reg = <0xfc0000 0x10000>; + read-only; + }; + + partition@fd0000 { + label = "lang_pack"; + reg = <0xfd0000 0x30000>; + read-only; + }; + }; + }; + + serial@12000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue-usb { + label = "dir665:blue:usb"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-internet { + /* Can only be turned on if the Internet + * Ethernet port has Link + */ + label = "dir665:blue:internet"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + amber-internet { + label = "dir665:amber:internet"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + blue-wifi5g { + label = "dir665:blue:5g"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + blue-status { + label = "dir665:blue:status"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + blue-wps { + label = "dir665:blue:wps"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + amber-status { + label = "dir665:amber:status"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + blue-24g { + label = "dir665:blue:24g"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio { + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. */ +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + phy-mode = "rgmii"; + }; +}; + +/* eth1 is connected to the switch as well. However DSA only supports a + * single CPU port. So leave this port disabled to avoid confusion. */ + +ð1 { + status = "disabled"; +}; + +/* There is no battery on the boards, so the RTC does not keep time + * when there is no power, making it useless. */ +&rtc { + status = "disabled"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dns320.dts b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts new file mode 100644 index 000000000000..d6b0f418fd01 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-dnskw.dtsi" + +/ { + model = "D-Link DNS-320 NAS (Rev A1)"; + compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 + &pmx_led_red_left_hdd &pmx_led_red_right_hdd + &pmx_led_white_usb>; + pinctrl-names = "default"; + + blue-power { + label = "dns320:blue:power"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + blue-usb { + label = "dns320:blue:usb"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + orange-l_hdd { + label = "dns320:orange:l_hdd"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + orange-r_hdd { + label = "dns320:orange:r_hdd"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + orange-usb { + label = "dns320:orange:usb"; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ + }; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + + serial@12100 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dns325.dts b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts new file mode 100644 index 000000000000..94d9c06cbbf5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-dnskw.dtsi" + +/ { + model = "D-Link DNS-325 NAS (Rev A1)"; + compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 + &pmx_led_red_left_hdd &pmx_led_red_right_hdd + &pmx_led_white_usb>; + pinctrl-names = "default"; + + white-power { + label = "dns325:white:power"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + white-usb { + label = "dns325:white:usb"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ + }; + red-l_hdd { + label = "dns325:red:l_hdd"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + red-r_hdd { + label = "dns325:red:r_hdd"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + red-usb { + label = "dns325:red:usb"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + + lm75: lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + }; + serial@12000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi new file mode 100644 index 000000000000..eb917462b219 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "D-Link DNS NASes (kirkwood-based)"; + compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_power &pmx_button_unmount + &pmx_button_reset>; + pinctrl-names = "default"; + + power { + label = "Power button"; + linux,code = ; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + eject { + label = "USB unmount button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; + pinctrl-names = "default"; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH + &gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 3000 1 + 6000 2>; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + + pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 + &pmx_present_sata1 &pmx_fan_tacho + &pmx_temp_alarm>; + pinctrl-names = "default"; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp20"; + marvell,function = "sata1"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp21"; + marvell,function = "sata0"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + pmx_led_red_right_hdd: pmx-led-red-right-hdd { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + pmx_led_red_left_hdd: pmx-led-red-left-hdd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_led_red_usb_325: pmx-led-red-usb-325 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_button_power: pmx-button-power { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_red_usb_320: pmx-led-red-usb-320 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_power_off: pmx-power-off { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_power_back_on: pmx-power-back-on { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_power_sata0: pmx-power-sata0 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_power_sata1: pmx-power-sata1 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_present_sata0: pmx-present-sata0 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_present_sata1: pmx-present-sata1 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_white_usb: pmx-led-white-usb { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_fan_tacho: pmx-fan-tacho { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_fan_high_speed: pmx-fan-high-speed { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_fan_low_speed: pmx-fan-low-speed { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_button_unmount: pmx-button-unmount { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_temp_alarm: pmx-temp-alarm { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; + sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; + pinctrl-names = "default"; + + sata0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 7 0>; + }; + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 8 0>; + }; + }; +}; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x500000>; + }; + + partition@600000 { + label = "ramdisk"; + reg = <0x0600000 0x500000>; + }; + + partition@b00000 { + label = "image"; + reg = <0x0b00000 0x6600000>; + }; + + partition@7100000 { + label = "mini firmware"; + reg = <0x7100000 0xa00000>; + }; + + partition@7b00000 { + label = "config"; + reg = <0x7b00000 0x500000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts new file mode 100644 index 000000000000..264938dfa4d9 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led-green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + }; + }; + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; + + health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 0>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x0500000 0xfb00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "marvell,88e1116"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts new file mode 100644 index 000000000000..328516351e84 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Globalscale Technologies Dreamplug"; + compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_led_bluetooth: pmx-led-bluetooth { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_wifi: pmx-led-wifi { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_wifi_ap: pmx-led-wifi-ap { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + }; + + spi@10600 { + status = "okay"; + + m25p40@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + + partition@100000 { + reg = <0x100000 0x10000>; + label = "u-boot env"; + }; + + partition@180000 { + reg = <0x180000 0x10000>; + label = "dtb"; + }; + }; + }; + + sata@80000 { + status = "okay"; + nr-ports = <1>; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi + &pmx_led_wifi_ap >; + pinctrl-names = "default"; + + bluetooth { + label = "dreamplug:blue:bluetooth"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + wifi { + label = "dreamplug:green:wifi"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + wifi-ap { + label = "dreamplug:green:wifi_ap"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds109.dts b/arch/arm/boot/dts/marvell/kirkwood-ds109.dts new file mode 100644 index 000000000000..29982e7acb7f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds109.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS109, DS110, DS110jv20"; + compatible = "synology,ds109", "synology,ds110jv20", + "synology,ds110", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts new file mode 100644 index 000000000000..d68c616e9309 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS110j v10 and v30"; + compatible = "synology,ds110jv10", "synology,ds110jv30", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds111.dts b/arch/arm/boot/dts/marvell/kirkwood-ds111.dts new file mode 100644 index 000000000000..e1420cbcd7e4 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds111.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS111"; + compatible = "synology,ds111", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds112.dts b/arch/arm/boot/dts/marvell/kirkwood-ds112.dts new file mode 100644 index 000000000000..3912f1b525b6 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds112.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS112"; + compatible = "synology,ds111", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-21-2 { + status = "okay"; + }; + + regulators-hdd-30 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds209.dts b/arch/arm/boot/dts/marvell/kirkwood-ds209.dts new file mode 100644 index 000000000000..f41fe95e055f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds209.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS209"; + compatible = "synology,ds209", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; + + regulators-hdd-31 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds210.dts b/arch/arm/boot/dts/marvell/kirkwood-ds210.dts new file mode 100644 index 000000000000..729f959a7838 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds210.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS210 v10, v20, v30, DS211j"; + compatible = "synology,ds210jv10", "synology,ds210jv20", + "synology,ds210jv30", "synology,ds211j", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; + + regulators-hdd-31 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds212.dts b/arch/arm/boot/dts/marvell/kirkwood-ds212.dts new file mode 100644 index 000000000000..416bab50d170 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds212.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; + compatible = "synology,ds212", "synology,ds212pv10", + "synology,ds212pv10", "synology,ds212pv20", + "synology,ds213airv10", "synology,ds213v10", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds212j.dts b/arch/arm/boot/dts/marvell/kirkwood-ds212j.dts new file mode 100644 index 000000000000..14cf4d8afaf3 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds212j.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS212j v10, v20"; + compatible = "synology,ds212jv10", "synology,ds212jv20", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds409.dts b/arch/arm/boot/dts/marvell/kirkwood-ds409.dts new file mode 100644 index 000000000000..a8650f9e3eb7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds409.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS409, DS410j"; + compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + gpio-leds-alarm-12 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts b/arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts new file mode 100644 index 000000000000..27a1d840bd15 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology 409slim"; + compatible = "synology,ds409slim", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-20 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds411.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411.dts new file mode 100644 index 000000000000..1d4256ef325d --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds411.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411, DS413jv10"; + compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + regulators-hdd-34 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds411j.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411j.dts new file mode 100644 index 000000000000..bb3200daea1e --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds411j.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411j"; + compatible = "synology,ds411j", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + gpio-leds-alarm-12 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts new file mode 100644 index 000000000000..9c5364a4e0a8 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411slim"; + compatible = "synology,ds411slim", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts new file mode 100644 index 000000000000..d4cb3cd3e2a2 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate GoFlex Net"; + compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_0: pmx-led_right_cap_0 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_1: pmx-led_right_cap_1 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_2: pmx-led_right_cap_2 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_led_right_cap_3: pmx-led_right_cap_3 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_0: pmx-led_left_cap_0 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_1: pmx-led_left_cap_1 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_2: pmx-led_left_cap_2 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_left_cap_3: pmx-led_left_cap_3 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led_green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_orange: pmx-led_orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_orange + &pmx_led_left_cap_0 &pmx_led_left_cap_1 + &pmx_led_left_cap_2 &pmx_led_left_cap_3 + &pmx_led_right_cap_0 &pmx_led_right_cap_1 + &pmx_led_right_cap_2 &pmx_led_right_cap_3 + >; + pinctrl-names = "default"; + + health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + left0 { + label = "status:white:left0"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + left1 { + label = "status:white:left1"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + left2 { + label = "status:white:left2"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + left3 { + label = "status:white:left3"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + right0 { + label = "status:white:right0"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + right1 { + label = "status:white:right1"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + right2 { + label = "status:white:right2"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + right3 { + label = "status:white:right3"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + chip-delay = <40>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "pogoplug"; + reg = <0x0500000 0x2000000>; + }; + + partition@2500000 { + label = "root"; + reg = <0x02500000 0xd800000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts new file mode 100644 index 000000000000..dfb41393941d --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Globalscale Technologies Guruplug Server Plus"; + compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_led_health_r: pmx-led-health-r { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_health_g: pmx-led-health-g { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_wmode_r: pmx-led-wmode-r { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_wmode_g: pmx-led-wmode-g { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <1>; + }; + + /* AzureWave AW-GH381 WiFi/BT */ + mvsdio@90000 { + status = "okay"; + non-removable; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g + &pmx_led_wmode_r &pmx_led_wmode_g >; + pinctrl-names = "default"; + + health-r { + label = "guruplug:red:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + health-g { + label = "guruplug:green:health"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + wmode-r { + label = "guruplug:red:wmode"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + wmode-g { + label = "guruplug:green:wmode"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x00100000 0x00400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x00500000 0x1fb00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts new file mode 100644 index 000000000000..962a910a6f5c --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; + compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_led_os_red: pmx-led-os-red { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + pmx_power_off: pmx-power-off { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + pmx_led_os_green: pmx-led-os-green { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + pmx_led_usb_transfer: pmx-led-usb-transfer { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_button_usb_copy: pmx-button-usb-copy { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; + pinctrl-names = "default"; + + copy { + label = "USB Copy"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green + &pmx_led_usb_transfer>; + pinctrl-names = "default"; + + green-os { + label = "ib62x0:green:os"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + red-os { + label = "ib62x0:red:os"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; + usb-copy { + label = "ib62x0:red:usb_copy"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0xe0000>; + }; + + partition@e0000 { + label = "u-boot environment"; + reg = <0xe0000 0x20000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x600000>; + }; + + partition@700000 { + label = "root"; + reg = <0x0700000 0xf900000>; + }; + +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts new file mode 100644 index 000000000000..aed20185fd7a --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Iomega Iconnect"; + compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + linux,initrd-start = <0x4500040>; + linux,initrd-end = <0x4800000>; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_button_otb: pmx-button-otb { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_led_level: pmx-led-level { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_power_blue: pmx-led-power-blue { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_power_red: pmx-power-red { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_usb1: pmx-led-usb1 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_usb2: pmx-led-usb2 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_usb3: pmx-led-usb3 { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_usb4: pmx-led-usb4 { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_otb: pmx-led-otb { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + }; + i2c@11000 { + status = "okay"; + + lm63: lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; + }; + serial@12000 { + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_level &pmx_led_power_blue + &pmx_led_power_red &pmx_led_usb1 + &pmx_led_usb2 &pmx_led_usb3 + &pmx_led_usb4 &pmx_led_otb >; + pinctrl-names = "default"; + + led-level { + label = "led_level"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + power-blue { + label = "power:blue"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + power-red { + label = "power:red"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + usb1 { + label = "usb1:blue"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + usb2 { + label = "usb2:blue"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + usb3 { + label = "usb3:blue"; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + usb4 { + label = "usb4:blue"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + otb { + label = "otb:blue"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; + pinctrl-names = "default"; + + otb { + label = "OTB Button"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0xc0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + }; + + partition@100000 { + label = "zImage"; + reg = <0x100000 0x300000>; + }; + + partition@540000 { + label = "initrd"; + reg = <0x540000 0x300000>; + }; + + partition@980000 { + label = "boot"; + reg = <0x980000 0x1f400000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@11 { + reg = <11>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts new file mode 100644 index 000000000000..2338f495d517 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 + &pmx_led_sata_brt_ctrl_2 + &pmx_led_backup_brt_ctrl_1 + &pmx_led_backup_brt_ctrl_2 + &pmx_led_power_brt_ctrl_1 + &pmx_led_power_brt_ctrl_2 + &pmx_led_health_brt_ctrl_1 + &pmx_led_health_brt_ctrl_2 + &pmx_led_rebuild_brt_ctrl_1 + &pmx_led_rebuild_brt_ctrl_2 >; + pinctrl-names = "default"; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_button_power: pmx-button-power { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + pmx_led_backup: pmx-led-backup { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + pmx_button_otb: pmx-button-otb { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_led_rebuild: pmx-led-rebuild { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_health: pmx-led_health { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + }; + i2c@11000 { + status = "okay"; + + lm63: lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_backup &pmx_led_power + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; + + power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; + health_led { + label = "status:red:health_led"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_reset &pmx_button_power + &pmx_button_otb>; + pinctrl-names = "default"; + + + Power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + Reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + OTB { + label = "OTB Button"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + }; + }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "rootfs"; + reg = <0x400000 0x1C00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@11 { + reg = <11>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-is2.dts b/arch/arm/boot/dts/marvell/kirkwood-is2.dts new file mode 100644 index 000000000000..1bc16a5cdbaa --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-is2.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "kirkwood-ns2-common.dtsi" + +/ { + model = "LaCie Internet Space v2"; + compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + ocp@f1000000 { + sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <1>; + }; + }; + + ns2-leds { + compatible = "lacie,ns2-leds"; + + blue-sata { + label = "ns2:blue:sata"; + slow-gpio = <&gpio0 29 0>; + cmd-gpio = <&gpio0 30 0>; + modes-map = ; + }; + }; +}; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi new file mode 100644 index 000000000000..52baffe45f12 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; + pinctrl-names = "default"; + + pmx_i2c_gpio_sda: pmx-gpio-sda { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_i2c_gpio_scl: pmx-gpio-scl { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + }; + + i2c { + compatible = "i2c-gpio"; + gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ + &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + }; +}; + +&nand { + status = "okay"; + chip-delay = <25>; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts new file mode 100644 index 000000000000..515be7bccc0a --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-98dx4122.dtsi" +#include "kirkwood-km_common.dtsi" + +/ { + model = "Keymile Kirkwood Fixed Eth"; + compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; /* */ + duplex = <1>; /* */ + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts new file mode 100644 index 000000000000..f035eff1c111 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-98dx4122.dtsi" +#include "kirkwood-km_common.dtsi" + +/ { + model = "Keymile Kirkwood Reference Design"; + compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts new file mode 100644 index 000000000000..9fd3581bb24b --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Check Point L-50 Board Description + * Copyright 2020 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Check Point L-50"; + compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_button29: pmx_button29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led38: pmx_led38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + mvsdio@90000 { + status = "okay"; + cd-gpios = <&gpio1 14 9>; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + gpio2: gpio-expander@20{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x20>; + + gpio-controller; + }; + + /* Three GPIOs from 0x21 exp. are undescribed in dts: + * 1: DSL module reset (active low) + * 5: mPCIE reset (active low) + * 6: Express card reset (active low) + */ + gpio3: gpio-expander@21{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x21>; + + gpio-controller; + }; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_green { + label = "l-50:green:status"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + status_red { + label = "l-50:red:status"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + + wifi { + label = "l-50:green:wifi"; + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + internet_green { + label = "l-50:green:internet"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + + internet_red { + label = "l-50:red:internet"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + usb1_green { + label = "l-50:green:usb1"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port3>; + }; + + usb1_red { + label = "l-50:red:usb1"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + }; + + usb2_green { + label = "l-50:green:usb2"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + + usb2_red { + label = "l-50:red:usb2"; + gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + }; + }; + + usb2_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb2_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + usb1_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb1_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + mpcie_pwr { + compatible = "regulator-fixed"; + regulator-name = "mpcie_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + express_card_pwr { + compatible = "regulator-fixed"; + regulator-name = "express_card_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory_defaults { + label = "factory_defaults"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy8: ethernet-phy@8 { + reg = <0x08>; + }; + + switch0: switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan6"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan7"; + }; + + switch0port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch1port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + phy-mode = "rgmii-id"; + ethernet = <ð1port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + switch@11 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11>; + dsa,member = <0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan8"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "dmz"; + }; + + switch1port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch0port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "dsl"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy8>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + phy-mode = "rgmii"; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000c0000>; + }; + + partition@a0000 { + label = "bootldr-env"; + reg = <0x000c0000 0x00040000>; + }; + + partition@100000 { + label = "kernel-1"; + reg = <0x00100000 0x00800000>; + }; + + partition@900000 { + label = "rootfs-1"; + reg = <0x00900000 0x07100000>; + }; + + partition@7a00000 { + label = "kernel-2"; + reg = <0x07a00000 0x00800000>; + }; + + partition@8200000 { + label = "rootfs-2"; + reg = <0x08200000 0x07100000>; + }; + + partition@f300000 { + label = "default_sw"; + reg = <0x0f300000 0x07900000>; + }; + + partition@16c00000 { + label = "logs"; + reg = <0x16c00000 0x01800000>; + }; + + partition@18400000 { + label = "preset_cfg"; + reg = <0x18400000 0x00100000>; + }; + + partition@18500000 { + label = "adsl"; + reg = <0x18500000 0x00100000>; + }; + + partition@18600000 { + label = "storage"; + reg = <0x18600000 0x07a00000>; + }; +}; + +&rtc { + status = "disabled"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port3: port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts new file mode 100644 index 000000000000..8c2b540eaf4f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2013 Maxime Hadjinlian + * + */ + +/dts-v1/; + +#include +#include +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "LaCie LaPlug"; + compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + }; + + pinctrl: pin-controller@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + power { + label = "Power push button"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "laplug_v2:red:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-power { + label = "laplug_v2:blue:power"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power_back1: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power Back 1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + usb_power_back2: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "USB Power Back 2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + + usb_power_front: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "USB Power Front"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + /* Total size : 512MB */ + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; /* 16MB */ + }; + + partition@1100000 { + label = "rootfs"; + reg = <0x1100000 0x1EF00000>; /* 495MB */ + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi new file mode 100644 index 000000000000..377b6e970259 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree common file for kirkwood-6282 based Buffalo Linkstation + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-linkstation.dtsi" + +/ { + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd0: pmx-power-hdd0 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function-red { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + function-button { + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + power-on-switch { + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + power-auto-switch { + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + red-alarm-led { + label = "linkstation:red:alarm"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; + + red-function-led { + label = "linkstation:red:function"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + amber-info-led { + label = "linkstation:amber:info"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + blue-function-led { + label = "linkstation:blue:function"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + blue-power-led { + label = "linkstation:blue:power"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + gpios = <&gpio0 17 GPIO_ACTIVE_LOW + &gpio0 16 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 3 + 1500 2 + 3250 1 + 5000 0>; + + alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + regulators { + usb_power: regulator@1 { + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + + hdd_power0: regulator@2 { + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi new file mode 100644 index 000000000000..ba629e02ba31 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-linkstation.dtsi" + +/ { + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd0: pmx-power-hdd0 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_power_hdd1: pmx-power-hdd1 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function-red { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + }; + + sata@80000 { + nr-ports = <2>; + }; + }; + + gpio_keys { + function-button { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + power-on-switch { + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + power-auto-switch { + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + red-alarm-led { + label = "linkstation:red:alarm"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + + red-function-led { + label = "linkstation:red:function"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + amber-info-led { + label = "linkstation:amber:info"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + blue-function-led { + label = "linkstation:blue:function"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + blue-power-led { + label = "linkstation:blue:power"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + regulators { + pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; + + usb_power: regulator@1 { + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + hdd_power0: regulator@2 { + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + + hdd_power1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "HDD1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts new file mode 100644 index 000000000000..8bb381088910 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Buffalo Linkstation LS-QVL + * + * Copyright (C) 2016, Mario Lange + * + * Based on kirkwood-linkstation-lswvl.dts, + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +/dts-v1/; +#include "kirkwood-linkstation-6282.dtsi" + +/ { + model = "Buffalo Linkstation LS-QVL"; + compatible = "buffalo,lsqvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd1: pmx-power-hdd1 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + pmx_led_hdderr0: pmx-led-hdderr0 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_hdderr1: pmx-led-hdderr1 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_led_hdderr2: pmx-led-hdderr2 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + pmx_led_hdderr3: pmx-led-hdderr3 { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + }; + + sata@80000 { + nr-ports = <2>; + }; + }; + + gpio_leds { + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue + &pmx_led_hdderr0 + &pmx_led_hdderr1 + &pmx_led_hdderr2 + &pmx_led_hdderr3>; + + red-hdderr0-led { + label = "linkstation:red:hdderr0"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + red-hdderr1-led { + label = "linkstation:red:hdderr1"; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + }; + + red-hdderr2-led { + label = "linkstation:red:hdderr2"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + red-hdderr3-led { + label = "linkstation:red:hdderr3"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { + pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; + + hdd_power1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "HDD1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts new file mode 100644 index 000000000000..3f2a0bfe03ed --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Buffalo Linkstation LS-VL + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +/dts-v1/; +#include "kirkwood-linkstation-6282.dtsi" + +/ { + model = "Buffalo Linkstation LS-VL"; + compatible = "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts new file mode 100644 index 000000000000..c42d0da38fe7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Buffalo Linkstation LS-WSXL + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +/dts-v1/; +#include "kirkwood-linkstation-duo-6281.dtsi" + +/ { + model = "Buffalo Linkstation LS-WSXL"; + compatible = "buffalo,lswsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts new file mode 100644 index 000000000000..e0f62adc0d5d --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Buffalo Linkstation LS-WVL + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +/dts-v1/; +#include "kirkwood-linkstation-6282.dtsi" + +/ { + model = "Buffalo Linkstation LS-WVL"; + compatible = "buffalo,lswvl","marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd1: pmx-power-hdd1 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + pmx_led_hdderr0: pmx-led-hdderr0 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_hdderr1: pmx-led-hdderr1 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + }; + + sata@80000 { + nr-ports = <2>; + }; + }; + + gpio_leds { + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue + &pmx_led_hdderr0 + &pmx_led_hdderr1>; + + red-hdderr0-led { + label = "linkstation:red:hdderr0"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + red-hdderr1-led { + label = "linkstation:red:hdderr1"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; + + hdd_power1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "HDD1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts new file mode 100644 index 000000000000..c6024b569423 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Buffalo Linkstation LS-WXL + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +/dts-v1/; +#include "kirkwood-linkstation-duo-6281.dtsi" + +/ { + model = "Buffalo Linkstation LS-WXL"; + compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_led_hdderr0: pmx-led-hdderr0 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_led_hdderr1: pmx-led-hdderr1 { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_leds { + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue + &pmx_led_hdderr0 + &pmx_led_hdderr1>; + + red-hdderr0-led { + label = "linkstation:red:hdderr0"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + }; + + red-hdderr1-led { + label = "linkstation:red:hdderr1"; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + gpios = <&gpio1 16 GPIO_ACTIVE_LOW + &gpio1 15 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 3 + 1500 2 + 3250 1 + 5000 0>; + + alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi new file mode 100644 index 000000000000..b54c9980f636 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree common file for kirkwood based Buffalo Linkstation + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + */ + +/ { + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd0: pmx-power-hdd0 { + marvell,function = "gpio"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function-red { + marvell,function = "gpio"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <1>; + }; + + spi@10600 { + status = "okay"; + + m25p40@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p40", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x60000>; + label = "uboot"; + read-only; + }; + + partition@60000 { + reg = <0x60000 0x10000>; + label = "dtb"; + read-only; + }; + + partition@70000 { + reg = <0x70000 0x10000>; + label = "uboot_env"; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_function &pmx_power_switch + &pmx_power_auto_switch>; + pinctrl-names = "default"; + + function-button { + label = "Function Button"; + linux,code = ; + }; + + power-on-switch { + label = "Power-on Switch"; + linux,code = ; + linux,input-type = <5>; + }; + + power-auto-switch { + label = "Power-auto Switch"; + linux,code = ; + linux,input-type = <5>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue>; + pinctrl-names = "default"; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd0 &pmx_usb_vbus>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + hdd_power0: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts new file mode 100644 index 000000000000..27fd6e2337d5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) + * + * (c) 2013 Jonas Gorski + * (c) 2013 Deutsche Telekom Innovation Laboratories + * (c) 2014 Luka Perkov + * (c) 2014 Randy C. Will + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Linksys Viper (E4200v2 / EA4500)"; + compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; + pinctrl-names = "default"; + + wps { + label = "WPS Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; + pinctrl-names = "default"; + + white-health { + label = "viper:white:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + white-pulse { + label = "viper:white:pulse"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + pmx_led_white_health: pmx-led-white-health { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + pmx_led_white_pulse: pmx-led-white-pulse { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u_env"; + reg = <0x80000 0x20000>; + }; + + partition@a0000 { + label = "s_env"; + reg = <0xA0000 0x20000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x2A0000>; + }; + + partition@4a0000 { + label = "rootfs"; + reg = <0x4A0000 0x1760000>; + }; + + partition@1c00000 { + label = "alt_kernel"; + reg = <0x1C00000 0x2A0000>; + }; + + partition@1ea0000 { + label = "alt_rootfs"; + reg = <0x1EA0000 0x1760000>; + }; + + partition@3600000 { + label = "syscfg"; + reg = <0x3600000 0x4A00000>; + }; + + partition@c0000 { + label = "unused"; + reg = <0xC0000 0x140000>; + }; + + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&mdio { + status = "okay"; + + switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <16>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "ethernet1"; + }; + + port@1 { + reg = <1>; + label = "ethernet2"; + }; + + port@2 { + reg = <2>; + label = "ethernet3"; + }; + + port@3 { + reg = <3>; + label = "ethernet4"; + }; + + port@4 { + reg = <4>; + label = "internet"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. + */ +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + phy-mode = "rgmii"; + }; +}; + +/* eth1 is connected to the switch at port 6. However DSA only supports a + * single CPU port. So leave this port disabled to avoid confusion. + */ +ð1 { + status = "disabled"; +}; + +/* There is no battery on the board, so the RTC does not keep + * time when there is no power, making it useless. + */ +&rtc { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts b/arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts new file mode 100644 index 000000000000..1d737d903f5f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-lsxl.dtsi" + +/ { + model = "Buffalo Linkstation LS-CHLv2"; + compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts b/arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts new file mode 100644 index 000000000000..a56e0d797778 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-lsxl.dtsi" + +/ { + model = "Buffalo Linkstation LS-XHL"; + compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi new file mode 100644 index 000000000000..88b70ba1c8fe --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + /* Non-default UART pins */ + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp4", "mpp5"; + }; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp10"; + marvell,function = "gpo"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp18"; + marvell,function = "gpo"; + }; + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp19"; + marvell,function = "gpo"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function_red { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + }; + sata@80000 { + status = "okay"; + nr-ports = <1>; + }; + + spi@10600 { + status = "okay"; + + m25p40@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p40", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x60000>; + label = "uboot"; + read-only; + }; + + partition@60000 { + reg = <0x60000 0x10000>; + label = "dtb"; + read-only; + }; + + partition@70000 { + reg = <0x70000 0x10000>; + label = "uboot_env"; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_function &pmx_power_switch + &pmx_power_auto_switch>; + pinctrl-names = "default"; + + option { + label = "Function Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + reserved { + label = "Power-on Switch"; + linux,code = ; + linux,input-type = <5>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + power { + label = "Power-auto Switch"; + linux,code = ; + linux,input-type = <5>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue>; + pinctrl-names = "default"; + + func_blue { + label = "lsxl:blue:func"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + alarm { + label = "lsxl:red:alarm"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + info { + label = "lsxl:amber:info"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + power { + label = "lsxl:blue:power"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + func_red { + label = "lsxl:red:func"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; + gpio-fan,speed-map = <0 3 + 1500 2 + 3250 1 + 5000 0>; + alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 11 0>; + }; + hdd_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 10 0>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts new file mode 100644 index 000000000000..e87ea7146546 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "MPL CEC4"; + compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_led_health: pmx-led-health { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp34"; + marvell,function = "sata1"; + }; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp35"; + marvell,function = "sata0"; + }; + + pmx_led_user1o: pmx-led-user1o { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_led_user1g: pmx-led-user1g { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_user0o: pmx-led-user0o { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_led_user0g: pmx-led-user0g { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_led_misc: pmx-led-misc { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + i2c@11000 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + }; + + }; + + serial@12000 { + status = "okay"; + }; + + rtc@10300 { + status = "disabled"; + }; + + sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + nr-ports = <2>; + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + /* No WP GPIO */ + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health + &pmx_led_user1o + &pmx_led_user1g &pmx_led_user0o + &pmx_led_user0g &pmx_led_misc + >; + pinctrl-names = "default"; + + health { + label = "status:green:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + }; + + user1o { + label = "user1:orange"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + user1g { + label = "user1:green"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + user0o { + label = "user0:orange"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + user0g { + label = "user0:green"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + misc { + label = "status:orange:misc"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "fdt"; + reg = <0x180000 0x80000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x400000>; + }; + + partition@600000 { + label = "rootfs"; + reg = <0x600000 0x1fa00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts new file mode 100644 index 000000000000..5a77286136c7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell 88F6281 GTW GE Board + * + * Lennert Buytenhek + * Thomas Petazzoni + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Marvell 88F6281 GTW GE Board"; + compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pin-controller@10000 { + pmx_usb_led: pmx-usb-led { + marvell,pins = "mpp12"; + marvell,function = "gpo"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "gpio"; + }; + + pmx_keys: pmx-keys { + marvell,pins = "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + mode = <0>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds &pmx_usb_led>; + pinctrl-names = "default"; + + green-status { + label = "gtw:green:Status"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + }; + + red-status { + label = "gtw:red:Status"; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + green-usb { + label = "gtw:green:USB"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_keys>; + pinctrl-names = "default"; + + restart { + label = "SWR Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + wps { + label = "WPS Button"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio { + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + phy-mode = "rgmii"; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nas2big.dts b/arch/arm/boot/dts/marvell/kirkwood-nas2big.dts new file mode 100644 index 000000000000..0b0a15093146 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nas2big.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for LaCie 2Big NAS + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + * +*/ + +/dts-v1/; + +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 2Big NAS"; + compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + rtc@10300 { + /* The on-chip RTC is not powered (no supercap). */ + status = "disabled"; + }; + spi@10600 { + /* + * A NAND flash is used instead of an SPI flash for + * the other netxbig-compatible boards. + */ + status = "disabled"; + }; + }; + + fan { + /* + * An I2C fan controller (GMT G762) is used but alarm is + * wired to a separate GPIO. + */ + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + regulators: regulators { + status = "okay"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + /* + * An external I2C RTC (Dallas DS1337S+) is used. This allows + * to power-up the board on an RTC alarm. The external RTC can + * be kept powered, even when the SoC is off. + */ + rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + interrupts = <43>; + }; + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; + +&nand { + chip-delay = <50>; + status = "okay"; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; + }; + + partition@1100000 { + label = "root"; + reg = <0x1100000 0x8000000>; + }; + + partition@9100000 { + label = "unused"; + reg = <0x9100000 0x6f00000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-net2big.dts b/arch/arm/boot/dts/marvell/kirkwood-net2big.dts new file mode 100644 index 000000000000..d5f6bb50ba11 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-net2big.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for LaCie 2Big Network v2 + * + * Copyright (C) 2014 + * + * Andrew Lunn + * + * Based on netxbig_v2-setup.c, + * Copyright (C) 2010 Simon Guinot + * +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 2Big Network v2"; + compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + fan { + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; +}; + +®ulators { + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&i2c0 { + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-net5big.dts b/arch/arm/boot/dts/marvell/kirkwood-net5big.dts new file mode 100644 index 000000000000..2497ad26b5b6 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-net5big.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for LaCie 5Big Network v2 + * + * Copyright (C) 2014 + * + * Andrew Lunn + * + * Based on netxbig_v2-setup.c, + * Copyright (C) 2010 Simon Guinot + * +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 5Big Network v2"; + compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + +}; + +®ulators { + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + netxbig-leds { + blue-sata2 { + label = "netxbig:blue:sata2"; + mode-addr = <5>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + red-sata2 { + label = "netxbig:red:sata2"; + mode-addr = <5>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + blue-sata3 { + label = "netxbig:blue:sata3"; + mode-addr = <6>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + red-sata3 { + label = "netxbig:red:sata3"; + mode-addr = <6>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + blue-sata4 { + label = "netxbig:blue:sata4"; + mode-addr = <7>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + red-sata4 { + label = "netxbig:red:sata4"; + mode-addr = <7>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + }; +}; + +&mdio { + ethphy1: ethernet-phy@1 { + reg = <0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + + +&i2c0 { + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts new file mode 100644 index 000000000000..cb564c3bcdc4 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for NETGEAR ReadyNAS Duo v2 + * + * Copyright (C) 2013, Arnaud EBALARD + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "NETGEAR ReadyNAS Duo v2"; + compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_button_power: pmx-button-power { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_button_backup: pmx-button-backup { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_blue_power: pmx-led-blue-power { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_led_blue_activity: pmx-led-blue-activity { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk1: pmx-led-blue-disk1 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk2: pmx-led-blue-disk2 { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_led_blue_backup: pmx-led-blue-backup { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + i2c@11000 { + status = "okay"; + + rs5c372a: rs5c372a@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity + &pmx_led_blue_disk1 &pmx_led_blue_disk2 + &pmx_led_blue_backup >; + pinctrl-names = "default"; + + power_led { + label = "status:blue:power_led"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + activity_led { + label = "status:blue:activity_led"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + disk1_led { + label = "status:blue:disk1_led"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + disk2_led { + label = "status:blue:disk2_led"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_button_power &pmx_button_backup + &pmx_button_reset>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb3_regulator: usb3-regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB 3.0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "jffs2"; + reg = <0x1800000 0x6800000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts new file mode 100644 index 000000000000..6cf76430cfab --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for NETGEAR ReadyNAS NV+ v2 + * + * Copyright (C) 2013, Arnaud EBALARD + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "NETGEAR ReadyNAS NV+ v2"; + compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_button_power: pmx-button-power { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_button_backup: pmx-button-backup { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_blue_power: pmx-led-blue-power { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_led_blue_backup: pmx-led-blue-backup { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk1: pmx-led-blue-disk1 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk2: pmx-led-blue-disk2 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk3: pmx-led-blue-disk3 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk4: pmx-led-blue-disk4 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + i2c@11000 { + status = "okay"; + + rs5c372a: rs5c372a@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ + status = "okay"; + nr-ports = <1>; + }; + }; + + auxdisplay { + compatible = "hit,hd44780"; + data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio1 1 GPIO_ACTIVE_HIGH>, + <&gpio1 3 GPIO_ACTIVE_HIGH>, + <&gpio1 17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + display-height-chars = <2>; + display-width-chars = <16>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup + &pmx_led_blue_disk1 &pmx_led_blue_disk2 + &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; + pinctrl-names = "default"; + + power_led { + label = "status:blue:power_led"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + disk1_led { + label = "status:blue:disk1_led"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + disk2_led { + label = "status:blue:disk2_led"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + disk3_led { + label = "status:blue:disk3_led"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + disk4_led { + label = "status:blue:disk4_led"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_button_power &pmx_button_backup + &pmx_button_reset>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb3_regulator: usb3-regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB 3.0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "jffs2"; + reg = <0x1800000 0x6800000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +/* Connected to NEC uPD720200 USB 3.0 controller */ +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi new file mode 100644 index 000000000000..b5737026e244 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree common file for LaCie 2Big and 5Big Network v2 + * + * Copyright (C) 2014 + * + * Andrew Lunn + * + * Based on netxbig_v2-setup.c, + * Copyright (C) 2010 Simon Guinot + * +*/ + +#include +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + }; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + /* + * esc and power represent a three position rocker + * switch. Thus the conventional KEY_POWER does not fit + */ + exc { + label = "Back power switch (on|auto)"; + linux,code = ; + linux,input-type = <5>; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + power { + label = "Back power switch (auto|off)"; + linux,code = ; + linux,input-type = <5>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + option { + label = "Function button"; + linux,code = ; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + regulators: regulators { + status = "okay"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd0power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + }; + + netxbig_gpio_ext: netxbig-gpio-ext { + compatible = "lacie,netxbig-gpio-ext"; + + addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH + &gpio1 16 GPIO_ACTIVE_HIGH + &gpio1 17 GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH + &gpio1 13 GPIO_ACTIVE_HIGH + &gpio1 14 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + netxbig-leds { + compatible = "lacie,netxbig-leds"; + + gpio-ext = <&netxbig_gpio_ext>; + + timers = ; + + blue-power { + label = "netxbig:blue:power"; + mode-addr = <0>; + mode-val = ; + bright-addr = <1>; + max-brightness = <7>; + }; + red-power { + label = "netxbig:red:power"; + mode-addr = <0>; + mode-val = ; + bright-addr = <1>; + max-brightness = <7>; + }; + blue-sata0 { + label = "netxbig:blue:sata0"; + mode-addr = <3>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + red-sata0 { + label = "netxbig:red:sata0"; + mode-addr = <3>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + blue-sata1 { + label = "netxbig:blue:sata1"; + mode-addr = <4>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + red-sata1 { + label = "netxbig:red:sata1"; + mode-addr = <4>; + mode-val = ; + bright-addr = <2>; + max-brightness = <7>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <8>; + }; + + ethphy1: ethernet-phy@1 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + + pmx_button_function: pmx-button-function { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_button_power_off: pmx-button-power-off { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + pmx_button_power_on: pmx-button-power-on { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi new file mode 100644 index 000000000000..51530ea86622 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_ns2_sata0: pmx-ns2-sata0 { + marvell,pins = "mpp21"; + marvell,function = "sata0"; + }; + pmx_ns2_sata1: pmx-ns2-sata1 { + marvell,pins = "mpp20"; + marvell,function = "sata1"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + power { + label = "Power push button"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "ns2:red:fail"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@X { + /* overwrite reg property in board file */ + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2.dts new file mode 100644 index 000000000000..7b67083e1ec0 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "kirkwood-ns2-common.dtsi" + +/ { + model = "LaCie Network Space v2"; + compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ocp@f1000000 { + sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <1>; + }; + }; + + ns2-leds { + compatible = "lacie,ns2-leds"; + + blue-sata { + label = "ns2:blue:sata"; + slow-gpio = <&gpio0 29 0>; + cmd-gpio = <&gpio0 30 0>; + modes-map = ; + }; + }; +}; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts new file mode 100644 index 000000000000..b0cb5907ed63 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-ns2-common.dtsi" + +/ { + model = "LaCie Network Space Lite v2"; + compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + ocp@f1000000 { + sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <1>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue-sata { + label = "ns2:blue:sata"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; +}; + +ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2max.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2max.dts new file mode 100644 index 000000000000..c0a087e77408 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2max.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "kirkwood-ns2-common.dtsi" + +/ { + model = "LaCie Network Space Max v2"; + compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + ocp@f1000000 { + sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW + &gpio1 1 GPIO_ACTIVE_LOW + &gpio0 23 GPIO_ACTIVE_LOW>; + gpio-fan,speed-map = + < 0 0 + 1500 15 + 1700 14 + 1800 13 + 2100 12 + 3100 11 + 3300 10 + 4300 9 + 5500 8>; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + ns2-leds { + compatible = "lacie,ns2-leds"; + + blue-sata { + label = "ns2:blue:sata"; + slow-gpio = <&gpio0 29 0>; + cmd-gpio = <&gpio0 30 0>; + modes-map = ; + }; + }; +}; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts new file mode 100644 index 000000000000..5b9fa14b6428 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "kirkwood-ns2-common.dtsi" + +/ { + /* This machine is embedded in the first LaCie CloudBox product. */ + model = "LaCie Network Space Mini v2"; + compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + ocp@f1000000 { + sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <1>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW + &gpio1 1 GPIO_ACTIVE_LOW + &gpio0 23 GPIO_ACTIVE_LOW>; + gpio-fan,speed-map = + < 0 0 + 3000 15 + 3180 14 + 4140 13 + 4570 12 + 6760 11 + 7140 10 + 7980 9 + 9200 8>; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + ns2-leds { + compatible = "lacie,ns2-leds"; + + blue-sata { + label = "ns2:blue:sata"; + slow-gpio = <&gpio0 29 0>; + cmd-gpio = <&gpio0 30 0>; + modes-map = ; + }; + }; +}; + +ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts new file mode 100644 index 000000000000..c1799a07816e --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/ { + compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_unknown>; + pinctrl-names = "default"; + + pmx_led_esata_green: pmx-led-esata-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_esata_red: pmx-led-esata-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_led_usb_red: pmx-led-usb-red { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_green: pmx-led-hdd-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_red: pmx-led-hdd-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_unknown: pmx-unknown { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + }; + + i2c@11000 { + status = "okay"; + + adt7476: adt7476a@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red + &pmx_led_usb_green &pmx_led_usb_red + &pmx_led_sys_green &pmx_led_sys_red + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd_green &pmx_led_hdd_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa310:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + red-sys { + label = "nsa310:red:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd { + label = "nsa310:green:hdd"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd { + label = "nsa310:red:hdd"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-esata { + label = "nsa310:green:esata"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-esata { + label = "nsa310:red:esata"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa310:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + red-usb { + label = "nsa310:red:usb"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa310:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa310:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts new file mode 100644 index 000000000000..b85e314f045a --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/* + * There are at least two different NSA310 designs. This variant does + * not have the red USB Led. + */ + +/ { + compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_esata_green: pmx-led-esata-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_esata_red: pmx-led-esata-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_green: pmx-led-hdd-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_red: pmx-led-hdd-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + }; + + i2c@11000 { + status = "okay"; + + lm85: lm85@2e { + compatible = "national,lm85"; + reg = <0x2e>; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green-sys { + label = "nsa310:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + red-sys { + label = "nsa310:red:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd { + label = "nsa310:green:hdd"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd { + label = "nsa310:red:hdd"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-esata { + label = "nsa310:green:esata"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-esata { + label = "nsa310:red:esata"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa310:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa310:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa310:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts new file mode 100644 index 000000000000..49da633a1bc0 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * ZyXEL NSA310S Board Description + * Copyright 2020-2022 Pawel Dembicki + * Copyright (c) 2015-2021, Tony Dinh + * Copyright (c) 2014, Adam Baker + * Based upon the board setup file created by Peter Schildmann + */ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include + +/ { + model = "ZyXEL NSA310S"; + compatible = "zyxel,nsa310s", "marvell,kirkwood-88f6702", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + }; + + copy { + label = "Copy Button"; + linux,code = ; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + function = LED_FUNCTION_USB; + color = ; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usb-host"; + }; + + led-3 { + function = LED_FUNCTION_DISK; + color = ; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "ata1"; + }; + + led-4 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-7 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; + + usb0_power: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "SATA1 Power"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + thermal-zones { + disk-thermal { + polling-delay = <20000>; + polling-delay-passive = <2000>; + + thermal-sensors = <&hdd_temp>; + + trips { + disk_alert: disk-alert { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + disk_crit: disk-crit { + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&i2c0 { + status = "okay"; + + rtc@68 { + compatible = "htk,ht1382"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + phy-mode = "rgmii-id"; + marvell,reg-init = <0x1 0x16 0x0 0x3>, + <0x1 0x10 0x0 0x1017>, + <0x1 0x11 0x0 0x4408>, + <0x1 0x16 0x0 0x0>; + }; +}; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x00c0000>; + read-only; + }; + partition@c0000 { + label = "uboot_env"; + reg = <0x00c0000 0x0080000>; + }; + partition@140000 { + label = "ubi"; + reg = <0x0140000 0x7ec0000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp24", "mpp25", "mpp26"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp13", "mpp15", "mpp16", "mpp22", "mpp23", + "mpp28", "mpp29"; + marvell,function = "gpio"; + }; + + pmx_power: pmx-power { + marvell,pins = "mpp21", "mpp33"; + marvell,function = "gpio"; + }; + + pmx_pwr_off: pmx-pwr-off { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "okay"; + nr-ports = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hdd_temp: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts new file mode 100644 index 000000000000..652405e65006 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Device tree file for the Zyxel NSA 320 NAS box. + * + * Copyright (c) 2014, Adam Baker + * + * + * Based upon the board setup file created by Peter Schildmann */ + +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/ { + model = "Zyxel NSA320"; + compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + /* SATA Activity and Present pins are not connected */ + pmx_sata0: pmx-sata0 { + marvell,pins ; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins ; + marvell,function = "sata1"; + }; + + pmx_led_hdd2_green: pmx-led-hdd2-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_hdd2_red: pmx-led-hdd2-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_mcu_data: pmx-mcu-data { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_mcu_clk: pmx-mcu-clk { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_mcu_act: pmx-mcu-act { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_orange: pmx-led-sys-orange { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_green: pmx-led-hdd1-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_red: pmx-led-hdd1-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_htp: pmx-htp { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + /* Buzzer needs to be switched at around 1kHz so is + not compatible with the gpio-beeper driver. */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_vid_b1: pmx-vid-b1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_resume_data: pmx-power-resume-data { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_power_resume_clk: pmx-power-resume-clk { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; + + i2c@11000 { + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + regulators { + usb0_power: regulator@1 { + enable-active-high; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red + &pmx_led_usb_green + &pmx_led_sys_green &pmx_led_sys_orange + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa320:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + orange-sys { + label = "nsa320:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa320:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd1 { + label = "nsa320:red:hdd1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-hdd2 { + label = "nsa320:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-hdd2 { + label = "nsa320:red:hdd2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa320:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa320:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa320:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; + + hwmon { + compatible = "zyxel,nsa320-mcu"; + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; + pinctrl-names = "default"; + + data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + + /* The following pins are currently not assigned to a driver, + some of them should be configured as inputs. + pinctrl-0 = <&pmx_htp &pmx_vid_b1 + &pmx_power_resume_data &pmx_power_resume_clk>; */ +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts new file mode 100644 index 000000000000..371456de34b2 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Device tree file for the Zyxel NSA 325 NAS box. + * + * Copyright (c) 2015, Hans Ulli Kroll + * + * + * Based upon the board setup file created by Peter Schildmann + */ + +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/ { + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_hdd2_green: pmx-led-hdd2-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_hdd2_red: pmx-led-hdd2-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_mcu_data: pmx-mcu-data { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_mcu_clk: pmx-mcu-clk { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_mcu_act: pmx-mcu-act { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_orange: pmx-led-sys-orange { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_green: pmx-led-hdd1-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_red: pmx-led-hdd1-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_htp: pmx-htp { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + /* + * Buzzer needs to be switched at around 1kHz so is + * not compatible with the gpio-beeper driver. + */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_vid_b1: pmx-vid-b1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_resume_data: pmx-power-resume-data { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_power_resume_clk: pmx-power-resume-clk { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + + pmx_pwr_sata1: pmx-pwr-sata1 { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + /* This board uses the pcf8563 RTC instead of the SoC RTC */ + rtc@10300 { + status = "disabled"; + }; + + i2c@11000 { + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_pwr_sata1>; + pinctrl-names = "default"; + + usb0_power: regulator@1 { + enable-active-high; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red + &pmx_led_usb_green + &pmx_led_sys_green &pmx_led_sys_orange + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa325:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd1 { + label = "nsa325:red:hdd1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-hdd2 { + label = "nsa325:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-hdd2 { + label = "nsa325:red:hdd2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa325:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa325:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa325:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + /* The following pins are currently not assigned to a driver, + some of them should be configured as inputs. + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act + &pmx_htp &pmx_vid_b1 + &pmx_power_resume_data &pmx_power_resume_clk>; */ + }; + + +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi new file mode 100644 index 000000000000..ea3d36512e9f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "ZyXEL NSA310"; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_pwr_off: pmx-pwr-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_btn_copy: pmx-btn-copy { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_btn_power: pmx-btn-power { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_copy_green: pmx-led-copy-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_led_copy_red: pmx-led-copy-red { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + copy { + label = "Copy Button"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; + + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + usb0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; + reg = <0x0100000 0x0080000>; + }; + partition@180000 { + label = "key_store"; + reg = <0x0180000 0x0080000>; + }; + partition@200000 { + label = "info"; + reg = <0x0200000 0x0080000>; + }; + partition@280000 { + label = "etc"; + reg = <0x0280000 0x0a00000>; + }; + partition@c80000 { + label = "kernel_1"; + reg = <0x0c80000 0x0a00000>; + }; + partition@1680000 { + label = "rootfs1"; + reg = <0x1680000 0x2fc0000>; + }; + partition@4640000 { + label = "kernel_2"; + reg = <0x4640000 0x0a00000>; + }; + partition@5040000 { + label = "rootfs2"; + reg = <0x5040000 0x2fc0000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts new file mode 100644 index 000000000000..8ea430168ea5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Plat'Home OpenBlocksA6"; + compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + + serial@12100 { + status = "okay"; + }; + + sata@80000 { + nr-ports = <1>; + status = "okay"; + }; + + i2c@11100 { + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_dip_switches>; + pinctrl-names = "default"; + + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11", "mpp15", + "mpp16"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14", "mpp8", + "mpp9"; + marvell,function = "uart1"; + }; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_dip_switches: pmx-dip-switches { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "gpio"; + }; + + pmx_gpio_header: pmx-gpio-header { + marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", + "mpp28", "mpp29", "mpp30", "mpp31"; + marvell,function = "gpio"; + }; + + pmx_gpio_init: pmx-init { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_usb_oc: pmx-usb-oc { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp41", "mpp42", "mpp43"; + marvell,function = "gpio"; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-red { + label = "obsa6:red:stat"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + led-green { + label = "obsa6:green:stat"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-yellow { + label = "obsa6:yellow:stat"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_init>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + power { + label = "Init Button"; + linux,code = ; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x90000>; + }; + + partition@90000 { + label = "env"; + reg = <0x90000 0x44000>; + }; + + partition@d4000 { + label = "test"; + reg = <0xd4000 0x20000>; + }; + + partition@f4000 { + label = "conf"; + reg = <0xf4000 0x400000>; + }; + + partition@4f4000 { + label = "linux"; + reg = <0x4f4000 0x1d20000>; + }; + + partition@2214000 { + label = "user"; + reg = <0x2214000 0x1dec000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&gpio0 { + status = "okay"; + + pinctrl-0 = <&pmx_gpio_header>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts new file mode 100644 index 000000000000..946f0f453dd1 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for OpenBlocks A7 board + * + * Copyright (C) 2013 Free Electrons + * + * Thomas Petazzoni + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Plat'Home OpenBlocksA7"; + compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + serial@12000 { + status = "okay"; + }; + + serial@12100 { + status = "okay"; + }; + + sata@80000 { + nr-ports = <1>; + status = "okay"; + }; + + i2c@11100 { + status = "okay"; + + s24c02: s24c02@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header + &pmx_gpio_header_gpo>; + pinctrl-names = "default"; + + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11", "mpp15", + "mpp16"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14", "mpp8", + "mpp9"; + marvell,function = "uart1"; + }; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_dip_switches: pmx-dip-switches { + marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + + /* + * Accessible on connector J202. The MPP + * listed below are pin 1-7, pin 8 is unused, + * pin 9 is external reset input and pin 10 is + * ground. + */ + pmx_gpio_header: pmx-gpio-header { + marvell,pins = "mpp17", "mpp29", "mpp28", + "mpp35", "mpp34", "mpp40"; + marvell,function = "gpio"; + }; + + pmx_gpio_header_gpo: pxm-gpio-header-gpo { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_gpio_init: pmx-init { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_usb_oc: pmx-usb-oc { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp41", "mpp42", "mpp43"; + marvell,function = "gpio"; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-red { + label = "obsa7:red:stat"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + led-green { + label = "obsa7:green:stat"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-yellow { + label = "obsa7:yellow:stat"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_init>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + button { + label = "Init Button"; + linux,code = ; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x1c0000>; + }; + + partition@1c0000 { + label = "env"; + reg = <0x1c0000 0x2c0000>; + }; + + partition@480000 { + label = "test"; + reg = <0x480000 0x160000>; + }; + + partition@5e0000 { + label = "conf"; + reg = <0x5e0000 0x540000>; + }; + + partition@b20000 { + label = "linux"; + reg = <0xb20000 0x3d40000>; + }; + + partition@4860000 { + label = "user"; + reg = <0x4860000 0xb7a0000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts new file mode 100644 index 000000000000..094191ece3d7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell OpenRD Base Board Description + * + * Andrew Lunn + * + * This file contains the definitions that are specific to OpenRD + * base variant of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood-openrd.dtsi" + +/ { + model = "OpenRD Base"; + compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + serial@12100 { + status = "okay"; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts new file mode 100644 index 000000000000..d4e0b8150a84 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell OpenRD Client Board Description + * + * Andrew Lunn + * + * This file contains the definitions that are specific to OpenRD + * client variant of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood-openrd.dtsi" + +/ { + model = "OpenRD Client"; + compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + audio-controller@a0000 { + status = "okay"; + }; + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + cs42l51: cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + #sound-dai-cells = <0>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&audio0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&cs42l51>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; + ethphy1: ethernet-phy@24 { + reg = <24>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + diff --git a/arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts new file mode 100644 index 000000000000..888e13320c19 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell OpenRD Ultimate Board Description + * + * Andrew Lunn + * + * This file contains the definitions that are specific to OpenRD + * ultimate variant of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood-openrd.dtsi" + +/ { + model = "OpenRD Ultimate"; + compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + cs42l51: cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi new file mode 100644 index 000000000000..47f03c69c55a --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell OpenRD (Base|Client|Ultimate) Board Description + * + * Andrew Lunn + * + * This file contains the definitions that are common between the three + * variants of the Marvell Kirkwood Development Board. + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; + pinctrl-names = "default"; + + pmx_select28: pmx-select-rs232-rs485 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_select34: pmx-select-uart-sd { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + + }; + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + mvsdio@90000 { + status = "okay"; + cd-gpios = <&gpio0 29 9>; + }; + gpio@10100 { + p28 { + gpio-hog; + gpios = <28 GPIO_ACTIVE_HIGH>; + /* + * SelRS232or485 selects between RS-232 or RS-485 + * mode for the second UART. + * + * Low: RS-232 + * High: RS-485 + * + * To use the second UART, you need to change also + * the SelUARTorSD. + */ + output-low; + line-name = "SelRS232or485"; + }; + }; + gpio@10140 { + p2 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + /* + * SelUARTorSD selects between the second UART + * (serial@12100) and SD (mvsdio@90000). + * + * Low: UART + * High: SD + * + * When changing this line make sure the newly + * selected device node is enabled and the + * previously selected device node is disabled. + */ + output-high; /* Select SD by default */ + line-name = "SelUARTorSD"; + }; + }; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@600000 { + label = "root"; + reg = <0x0600000 0x1FA00000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts new file mode 100644 index 000000000000..f9e95e55f36d --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 + * + * Copyright (C) 2015 Christoph Junghans + * + * based on information of dts files from + * Arch Linux ARM by Oleg Rakhmanov + * OpenWrt by Felix Kaechele + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Cloud Engines Pogoplug E02"; + compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-leds { + compatible = "gpio-leds"; + + health { + label = "pogo_e02:green:health"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + fault { + label = "pogo_e02:orange:fault"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange + &pmx_led_green >; + pinctrl-names = "default"; + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_green: pmx-led-green { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&nand { + chip-delay = <40>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "pogoplug"; + reg = <0x0500000 0x2000000>; + }; + + partition@2500000 { + label = "root"; + reg = <0x02500000 0x5b00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts new file mode 100644 index 000000000000..5aa4669ae254 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 + * inspired by the board files made by Kevin Mihelich for ArchLinux, + * and their DTS file. + * + * Copyright (C) 2015 Linus Walleij + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" +#include + +/ { + model = "Cloud Engines PogoPlug Series 4"; + compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { + stdout-path = "uart0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_eject>; + pinctrl-names = "default"; + + eject { + debounce-interval = <50>; + wakeup-source; + linux,code = ; + label = "Eject Button"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_green &pmx_led_red>; + pinctrl-names = "default"; + + health { + label = "pogoplugv4:green:health"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + fault { + label = "pogoplugv4:red:fault"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp21"; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp20"; + marvell,function = "sata1"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + pmx_sdio_wp: pmx-sdio-wp { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_button_eject: pmx-button-eject { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_green: pmx-led-green { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_led_red: pmx-led-red { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + status = "okay"; +}; + +/* + * This PCIE controller has a USB 3.0 XHCI controller at 1,0 + */ +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&sata { + status = "okay"; + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + nr-ports = <1>; +}; + +&sdio { + status = "okay"; + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; + pinctrl-names = "default"; + cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +}; + +&nand { + /* 128 MiB of NAND flash */ + chip-delay = <40>; + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x200000>; + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x00200000 0x300000>; + }; + + partition@500000 { + label = "uImage2"; + reg = <0x00500000 0x300000>; + }; + + partition@800000 { + label = "failsafe"; + reg = <0x00800000 0x800000>; + }; + + partition@1000000 { + label = "root"; + reg = <0x01000000 0x7000000>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts new file mode 100644 index 000000000000..f00325ffde07 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell RD88F6192 Board descrition + * + * Andrew Lunn + * + * This file contains the definitions that are common between the three + * variants of the Marvell Kirkwood Development Board. + */ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "Marvell RD88F6192 reference design"; + compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp10"; + marvell,function = "gpo"; + }; + }; + + serial@12000 { + status = "okay"; + + }; + + spi@10600 { + status = "okay"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + }; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + usb_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "USB VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts new file mode 100644 index 000000000000..5da163591bbf --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell RD88F6181 A Board descrition + * + * Andrew Lunn + * + * This file contains the definitions for the board with the A0 or + * higher stepping of the SoC. The ethernet switch does not have a + * "wan" port. + */ + +/dts-v1/; +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; + compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@11 { + reg = <11>; + }; +}; + +&switch { + reg = <10>; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts new file mode 100644 index 000000000000..72edd47e19ff --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell RD88F6181 Z0 stepping descrition + * + * Andrew Lunn + * + * This file contains the definitions for the board using the Z0 + * stepping of the SoC. The ethernet switch has a "wan" port. +*/ + +/dts-v1/; + +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with Z0 SoC"; + compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + +}; + +ð1 { + status = "disabled"; +}; + +&switch { + reg = <0>; + + ports { + port@4 { + reg = <4>; + label = "wan"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi new file mode 100644 index 000000000000..9d62f910cddf --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell RD88F6181 Common Board descrition + * + * Andrew Lunn + * + * This file contains the definitions that are common between the two + * variants of the Marvell Kirkwood Development Board. + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + /* No WP GPIO */ + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x200000>; + }; + + partition@300000 { + label = "rootfs"; + reg = <0x0300000 0x500000>; + }; +}; + +&mdio { + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + }; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rs212.dts b/arch/arm/boot/dts/marvell/kirkwood-rs212.dts new file mode 100644 index 000000000000..4ad412115a24 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rs212.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS212"; + compatible = "synology,rs212", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-3 { + status = "okay"; + }; + + gpio-leds-hdd-38 { + status = "okay"; + }; + + regulators-hdd-30-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rs409.dts b/arch/arm/boot/dts/marvell/kirkwood-rs409.dts new file mode 100644 index 000000000000..43673b03cb35 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rs409.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS409"; + compatible = "synology,rs409", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&rs5c372 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-rs411.dts b/arch/arm/boot/dts/marvell/kirkwood-rs411.dts new file mode 100644 index 000000000000..41fa63cec839 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-rs411.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Andrew Lunn + * Ben Peddell + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS411 RS812"; + compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-fan-100-15-35-3 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi new file mode 100644 index 000000000000..0a698d3b7393 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs + * + * Copyright (C) 2013 Simon Baatz + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_red: pmx-led-red { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_blue: pmx-led-blue { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_sdio_wp: pmx-sdio-wp { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 0>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x0500000 0x1fb00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts new file mode 100644 index 000000000000..ae8f493c9a0f --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug + * + * Copyright (C) 2013 Simon Baatz + */ + +/dts-v1/; + +#include "kirkwood-sheevaplug-common.dtsi" + +/ { + model = "Globalscale Technologies eSATA SheevaPlug"; + compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_blue>; + pinctrl-names = "default"; + + health { + label = "sheevaplug:blue:health"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts new file mode 100644 index 000000000000..c73cc904e5c4 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug + * + * Copyright (C) 2013 Simon Baatz + */ + +/dts-v1/; + +#include "kirkwood-sheevaplug-common.dtsi" + +/ { + model = "Globalscale Technologies SheevaPlug"; + compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_blue &pmx_led_red>; + pinctrl-names = "default"; + + health { + label = "sheevaplug:blue:health"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + misc { + label = "sheevaplug:red:misc"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi new file mode 100644 index 000000000000..9b6666020cdd --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nodes for Marvell 628x Synology devices + * + * Andrew Lunn + * Ben Peddell + * + */ + +/ { + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_alarmled_12: pmx-alarmled-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_15: pmx-fanctrl-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_16: pmx-fanctrl-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_17: pmx-fanctrl-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_18: pmx-fanalarm-18 { + marvell,pins = "mpp18"; + marvell,function = "gpo"; + }; + + pmx_hddled_20: pmx-hddled-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_hddled_21: pmx-hddled-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_hddled_22: pmx-hddled-22 { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_hddled_23: pmx-hddled-23 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_hddled_24: pmx-hddled-24 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_hddled_25: pmx-hddled-25 { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + pmx_hddled_26: pmx-hddled-26 { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + pmx_hddled_27: pmx-hddled-27 { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + pmx_hddled_28: pmx-hddled-28 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + + pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_32: pmx-fanctrl-32 { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_33: pmx-fanctrl-33 { + marvell,pins = "mpp33"; + marvell,function = "gpo"; + }; + + pmx_fanctrl_34: pmx-fanctrl-34 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_35: pmx-fanalarm-35 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + pmx_hddled_36: pmx-hddled-36 { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_hddled_37: pmx-hddled-37 { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_hddled_38: pmx-hddled-38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_hddled_39: pmx-hddled-39 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_hddled_40: pmx-hddled-40 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_hddled_41: pmx-hddled-41 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_hddled_42: pmx-hddled-42 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_hddled_43: pmx-hddled-43 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + pmx_hddled_44: pmx-hddled-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_hddled_45: pmx-hddled-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_44: pmx-fanalarm-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_45: pmx-fanalarm-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + }; + + rtc@10300 { + status = "disabled"; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@0 { + reg = <0x00000000 0x00080000>; + label = "RedBoot"; + }; + + partition@80000 { + reg = <0x00080000 0x00200000>; + label = "zImage"; + }; + + partition@280000 { + reg = <0x00280000 0x00140000>; + label = "rd.gz"; + }; + + partition@3c0000 { + reg = <0x003c0000 0x00010000>; + label = "vendor"; + }; + + partition@3d0000 { + reg = <0x003d0000 0x00020000>; + label = "RedBoot config"; + }; + + partition@3f0000 { + reg = <0x003f0000 0x00010000>; + label = "FIS directory"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + rs5c372: rs5c372@32 { + status = "disabled"; + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; + + s35390a: s35390a@30 { + status = "disabled"; + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-fan-150-32-35 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH + &gpio1 1 GPIO_ACTIVE_HIGH + &gpio1 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2200 1 + 2500 2 + 3000 4 + 3300 3 + 3700 5 + 3800 6 + 4200 7 >; + }; + + gpio-fan-150-15-18 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_18>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2200 1 + 2500 2 + 3000 4 + 3300 3 + 3700 5 + 3800 6 + 4200 7 >; + }; + + gpio-fan-100-32-35 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH + &gpio1 1 GPIO_ACTIVE_HIGH + &gpio1 2 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-18 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_18>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-35-1 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-35-3 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH + &gpio1 12 GPIO_ACTIVE_HIGH + &gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-leds-alarm-12 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_alarmled_12>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:alarm"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-20 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 + &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 + &pmx_hddled_26 &pmx_hddled_27>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + hdd3-green { + label = "synology:green:hdd3"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + hdd3-amber { + label = "synology:amber:hdd3"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + hdd4-green { + label = "synology:green:hdd4"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + hdd4-amber { + label = "synology:amber:hdd4"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-21-1 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-21-2 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-36 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 + &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 + &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 + &pmx_hddled_45>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hdd3-green { + label = "synology:green:hdd3"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + hdd3-amber { + label = "synology:amber:hdd3"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + hdd4-green { + label = "synology:green:hdd4"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + hdd4-amber { + label = "synology:amber:hdd4"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + hdd5-green { + label = "synology:green:hdd5"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + + hdd5-amber { + label = "synology:amber:hdd5"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-38 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + }; + + regulators-hdd-29 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-1 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-2 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-4 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 + &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-31 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd2_pwr_31>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-34 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 + &pmx_hdd4_pwr_45>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <8>; + }; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <9>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "disabled"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts new file mode 100644 index 000000000000..ad093324e075 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HP t5325 Thin Client" + * + * Copyright (C) 2014 + * + * Thomas Petazzoni + * Andrew Lunn + * +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "HP t5325 Thin Client"; + compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_i2s &pmx_sysrst>; + pinctrl-names = "default"; + + pmx_button_power: pmx-button_power { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_led: pmx-led { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_spi: pmx-spi { + marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; + marvell,function = "spi"; + }; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_i2s: pmx-i2s { + marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", + "mpp43"; + marvell,function = "audio"; + }; + }; + + spi@10600 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80", "jedec,spi-nor"; + spi-max-frequency = <86000000>; + reg = <0>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + + partition@1 { + reg = <0x80000 0x40000>; + label = "SSD firmware"; + }; + + partition@2 { + reg = <0xc0000 0x10000>; + label = "u-boot env"; + }; + + partition@3 { + reg = <0xd0000 0x10000>; + label = "permanent u-boot env"; + }; + + partition@4 { + reg = <0xd0000 0x10000>; + label = "permanent u-boot env"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + + alc5621: alc5621@1a { + compatible = "realtek,alc5621"; + reg = <0x1a>; + #sound-dai-cells = <0>; + add-ctrl = <0x3700>; + jack-det-ctrl = <0x4810>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + audio: audio-controller@a0000 { + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_sata_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB-SATA Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_power>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPKOUT", + "Speaker", "SPKOUTN", + "MIC1", "Mic Jack", + "MIC2", "Mic Jack"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Speaker", + "Microphone", "Mic Jack"; + + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&audio>; + }; + + simple-audio-card,codec { + sound-dai = <&alc5621>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-topkick.dts b/arch/arm/boot/dts/marvell/kirkwood-topkick.dts new file mode 100644 index 000000000000..a5b51e29f63e --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-topkick.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Universal Scientific Industrial Co. Topkick-1281P2"; + compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + /* + * Switch positions + * + * /-SW_LEFT(2) + * | + * | /-SW_IDLE + * | | + * | | /-SW_RIGHT + * | | | + * PS [L] [I] [R] LEDS + */ + pinctrl-0 = <&pmx_sw_left &pmx_sw_right + &pmx_sw_idle &pmx_sw_left2>; + pinctrl-names = "default"; + + pmx_led_disk_yellow: pmx-led-disk-yellow { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_sata0_pwr_enable: pmx-sata0-pwr-enable { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_led_sys_blue: pmx-led-sys-blue { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_led_wifi_green: pmx-led-wifi-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_sw_left: pmx-sw-left { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + pmx_sw_right: pmx-sw-right { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_sw_idle: pmx-sw-idle { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_sw_left2: pmx-sw-left2 { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_wifi_yellow: pmx-led-wifi-yellow { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <1>; + }; + + i2c@11000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + }; + + gpio-leds { + /* + * GPIO LED layout + * + * /-SYS_LED(2) + * | + * | /-DISK_LED + * | | + * | | /-WLAN_LED(2) + * | | | + * [SW] [*] [*] [*] + */ + + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red + &pmx_led_sys_blue &pmx_led_wifi_green + &pmx_led_wifi_yellow>; + pinctrl-names = "default"; + + disk { + label = "topkick:yellow:disk"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + system2 { + label = "topkick:red:system"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + system { + label = "topkick:blue:system"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + wifi { + label = "topkick:green:wifi"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + wifi2 { + label = "topkick:yellow:wifi"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_pwr_enable>; + pinctrl-names = "default"; + + sata0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 4 0>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + }; + + partition@180000 { + label = "u-boot env"; + reg = <0x0180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "uInitrd"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "rootfs"; + reg = <0x1800000 0xe800000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts new file mode 100644 index 000000000000..30892c19aceb --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-ts219.dtsi" + +/ { + ocp@f1000000 { + pinctrl: pin-controller@10000 { + + pinctrl-0 = <&pmx_ram_size &pmx_board_id>; + pinctrl-names = "default"; + + pmx_ram_size: pmx-ram-size { + /* RAM: 0: 256 MB, 1: 512 MB */ + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_USB_copy_button: pmx-USB-copy-button { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + pmx_board_id: pmx-board-id { + /* 0: TS-11x, 1: TS-21x */ + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + + copy { + label = "USB Copy"; + linux,code = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts new file mode 100644 index 000000000000..aba1205981f1 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-ts219.dtsi" + +/ { + ocp@f1000000 { + pinctrl: pin-controller@10000 { + + pinctrl-0 = <&pmx_ram_size &pmx_board_id>; + pinctrl-names = "default"; + + pmx_ram_size: pmx-ram-size { + /* RAM: 0: 256 MB, 1: 512 MB */ + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_USB_copy_button: pmx-USB-copy-button { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_board_id: pmx-board-id { + /* 0: TS-11x, 1: TS-21x */ + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + + copy { + label = "USB Copy"; + linux,code = ; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ðphy0 { reg = <0>; }; + +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi new file mode 100644 index 000000000000..1939462a5f48 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + model = "QNAP TS219 family"; + compatible = "qnap,ts219", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + poweroff@12100 { + compatible = "qnap,power-off"; + reg = <0x12100 0x100>; + clocks = <&gate_clk 7>; + }; + spi@10600 { + status = "okay"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@0 { + reg = <0x00000000 0x00080000>; + label = "U-Boot"; + }; + + partition@200000 { + reg = <0x00200000 0x00200000>; + label = "Kernel"; + }; + + partition@400000 { + reg = <0x00400000 0x00900000>; + label = "RootFS1"; + }; + partition@d00000 { + reg = <0x00d00000 0x00300000>; + label = "RootFS2"; + }; + partition@40000 { + reg = <0x00080000 0x00040000>; + label = "U-Boot Config"; + }; + partition@c0000 { + reg = <0x000c0000 0x00140000>; + label = "NAS Config"; + }; + }; + }; + sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@X { + /* overwrite reg property in board file */ + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&rtc { + /* + * There is a s35390a available on the i2c bus, the internal rtc isn't + * working (probably no crystal assembled). + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts new file mode 100644 index 000000000000..4a42ebcca4f0 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for QNAP TS41X with 6281 SoC + * + * Copyright (C) 2013, Andrew Lunn + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-ts219.dtsi" +#include "kirkwood-ts419.dtsi" + +ðphy0 { reg = <8>; }; +ðphy1 { reg = <0>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts new file mode 100644 index 000000000000..be772e194c2b --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for QNAP TS41X with 6282 SoC + * + * Copyright (C) 2013, Andrew Lunn + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-ts219.dtsi" +#include "kirkwood-ts419.dtsi" + +ðphy0 { reg = <0>; }; +ðphy1 { reg = <1>; }; + +&pciec { status = "okay"; }; +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi new file mode 100644 index 000000000000..717236853e45 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree include file for QNAP TS41X + * + * Copyright (C) 2013, Andrew Lunn + */ + +/ { + model = "QNAP TS419 family"; + compatible = "qnap,ts419", "marvell,kirkwood"; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_USB_copy_button: pmx-USB-copy-button { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + /* + * JP1 indicates if an LCD module is installed + * on the serial port (0), or if the port is used + * as a console (1). + */ + pmx_jumper_jp1: pmx-jumper_jp1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + + copy { + label = "USB Copy"; + linux,code = ; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + /* overwrite reg property in board file */ + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/marvell/kirkwood.dtsi b/arch/arm/boot/dts/marvell/kirkwood.dtsi new file mode 100644 index 000000000000..815ef7719d13 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood.dtsi @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "marvell,kirkwood"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,feroceon"; + reg = <0>; + clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; + clock-names = "cpu_clk", "ddrclk", "powersave"; + }; + }; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + i2c0 = &i2c0; + }; + + mbus@f1000000 { + compatible = "marvell,kirkwood-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + /* If a board file needs to change this ranges it must replace it completely */ + ranges = ; + controller = <&mbusc>; + pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ + pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ + + nand: nand@12f { + #address-cells = <1>; + #size-cells = <1>; + cle = <0>; + ale = <1>; + bank-width = <1>; + compatible = "marvell,orion-nand"; + reg = ; + chip-delay = <25>; + /* set partition map and/or chip-delay in board dts */ + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "disabled"; + }; + + crypto_sram: sa-sram@301 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gate_clk 17>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + ocp@f1000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xf1000000 0x0100000>; + #address-cells = <1>; + #size-cells = <1>; + + pinctrl: pin-controller@10000 { + /* set compatible property in SoC file */ + reg = <0x10000 0x20>; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", "mpp27", + "mpp30", "mpp31", "mpp32", "mpp33"; + marvell,function = "ge1"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", "mpp19"; + marvell,function = "nand"; + }; + + /* + * Default SPI0 pinctrl setting with CSn on mpp0, + * overwrite marvell,pins on board level if required. + */ + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + + /* + * Default UART pinctrl setting without RTS/CTS, + * overwrite marvell,pins on board level if required. + */ + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + }; + + core_clk: core-clocks@10030 { + compatible = "marvell,kirkwood-core-clock"; + reg = <0x10030 0x4>; + #clock-cells = <1>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <23>; + reg = <0x10600 0x28>; + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + status = "disabled"; + }; + + gpio0: gpio@10100 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x10100 0x40>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <35>, <36>, <37>, <38>; + clocks = <&gate_clk 7>; + }; + + gpio1: gpio@10140 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x10140 0x40>; + ngpios = <18>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <39>, <40>, <41>; + clocks = <&gate_clk 7>; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <29>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x1500 0x20>; + }; + + sysc: system-controller@20000 { + compatible = "marvell,orion-system-controller"; + reg = <0x20000 0x120>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <1>; + marvell,#interrupts = <6>; + }; + + gate_clk: clock-gating-control@2011c { + compatible = "marvell,kirkwood-gating-clock"; + reg = <0x2011c 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; + + intc: interrupt-controller@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + wdt: watchdog-timer@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>, <0x20108 0x4>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; + clocks = <&gate_clk 7>; + status = "okay"; + }; + + cesa: crypto@30000 { + compatible = "marvell,kirkwood-crypto"; + reg = <0x30000 0x10000>; + reg-names = "regs"; + interrupts = <22>; + clocks = <&gate_clk 17>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x800>; + status = "okay"; + }; + + usb0: ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <19>; + clocks = <&gate_clk 3>; + status = "okay"; + }; + + dma0: xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + status = "okay"; + clocks = <&gate_clk 8>; + + xor00 { + interrupts = <5>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <6>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + dma1: xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60B00 0x100>; + status = "okay"; + clocks = <&gate_clk 16>; + + xor00 { + interrupts = <7>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <8>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + eth0: ethernet-controller@72000 { + compatible = "marvell,kirkwood-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 0>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + eth0port: ethernet0-port@0 { + compatible = "marvell,kirkwood-eth-port"; + reg = <0>; + interrupts = <11>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <46>; + clocks = <&gate_clk 0>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + eth1: ethernet-controller@76000 { + compatible = "marvell,kirkwood-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76000 0x4000>; + clocks = <&gate_clk 19>; + marvell,tx-checksum-limit = <1600>; + pinctrl-0 = <&pmx_ge1>; + pinctrl-names = "default"; + status = "disabled"; + + eth1port: ethernet1-port@0 { + compatible = "marvell,kirkwood-eth-port"; + reg = <0>; + interrupts = <15>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; + + sata_phy0: sata-phy@82000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x82000 0x0334>; + clocks = <&gate_clk 14>; + clock-names = "sata"; + #phy-cells = <0>; + status = "okay"; + }; + + sata_phy1: sata-phy@84000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x84000 0x0334>; + clocks = <&gate_clk 15>; + clock-names = "sata"; + #phy-cells = <0>; + status = "okay"; + }; + + audio0: audio-controller@a0000 { + compatible = "marvell,kirkwood-audio"; + #sound-dai-cells = <0>; + reg = <0xa0000 0x2210>; + interrupts = <24>; + clocks = <&gate_clk 9>; + clock-names = "internal"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/mmp2-brownstone.dts b/arch/arm/boot/dts/marvell/mmp2-brownstone.dts new file mode 100644 index 000000000000..04f1ae1382e7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/mmp2-brownstone.dts @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + */ + +/dts-v1/; +#include "mmp2.dtsi" + +/ { + model = "Marvell MMP2 Brownstone Development Board"; + compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; + + chosen { + bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; +}; + +&uart3 { + status = "okay"; +}; + +&twsi1 { + status = "okay"; + pmic: max8925@3c { + compatible = "maxium,max8925"; + reg = <0x3c>; + interrupts = <1>; + interrupt-parent = <&intcmux4>; + interrupt-controller; + #interrupt-cells = <1>; + maxim,tsc-irq = <0>; + + regulators { + SDV1 { + regulator-min-microvolt = <637500>; + regulator-max-microvolt = <1425000>; + regulator-boot-on; + regulator-always-on; + }; + SDV2 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2225000>; + regulator-boot-on; + regulator-always-on; + }; + SDV3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO1 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO2 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO3 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO4 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO5 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO6 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO7 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO8 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO10 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + }; + LDO11 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO12 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO13 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO14 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO15 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO16 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO17 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO18 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO19 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO20 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + }; + backlight { + maxim,max8925-dual-string = <0>; + }; + charger { + batt-detect = <0>; + topoff-threshold = <1>; + fast-charge = <7>; + no-temp-support = <0>; + no-insert-detect = <0>; + }; + }; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts new file mode 100644 index 000000000000..55ea87870af3 --- /dev/null +++ b/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * OLPC XO 1.75 Laptop. + * + * Copyright (C) 2018,2019,2020 Lubomir Rintel + */ + +/dts-v1/; +#include "mmp2.dtsi" +#include +#include +#include +#include + +/ { + model = "OLPC XO-1.75"; + compatible = "olpc,xo-1.75", "mrvl,mmp2"; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@1fc00000 { + compatible = "simple-framebuffer"; + reg = <0x1fc00000 (1200 * 900 * 2)>; + width = <1200>; + height = <900>; + stride = <(1200 * 2)>; + format = "r5g6b5"; + clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>, + <&soc_clocks MMP2_CLK_DISP0>; + }; + }; + + memory@0 { + available = <0xcf000 0x1ef31000 0x1000 0xbf000>; + reg = <0x0 0x20000000>; + device_type = "memory"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio 129 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + }; + + tablet_mode { + label = "E-Book Mode"; + gpios = <&gpio 128 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + }; + }; + + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + i2c-gpio,timeout-ms = <1000>; + status = "okay"; + + camera@21 { + compatible = "ovti,ov7670"; + reg = <0x21>; + reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>; + clocks = <&camera0>; + clock-names = "xclk"; + + port { + ov7670_0: endpoint { + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&camera0_0>; + }; + }; + }; + }; + + battery { + compatible = "olpc,xo1.5-battery", "olpc,xo1-battery"; + }; + + wlan_reg: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "wlan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 34 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlan_pwrseq: pwrseq0 { + compatible = "mmc-pwrseq-sd8787"; + powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; + }; + + sound-card { + compatible = "audio-graph-card"; + label = "OLPC XO"; + dais = <&sspa0_dai>; + routing = "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC2", "Mic Jack"; + widgets = "Headphone", "Headphones", "Microphone", "Mic Jack"; + hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>; + mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>; + }; + + soc { + axi@d4200000 { + ap-sp@d4290000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "olpc,ap-sp"; + interrupts = <40>; + reg = <0xd4290000 0x1000>; + data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; + clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + }; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_otg0 { + status = "okay"; +}; + +&mmc1 { + clock-frequency = <50000000>; + no-1-8-v; + mrvl,clk-delay-cycles = <31>; + broken-cd; + status = "okay"; +}; + +&mmc2 { + clock-frequency = <50000000>; + no-1-8-v; + bus-width = <4>; + non-removable; + broken-cd; + wakeup-source; + keep-power-in-suspend; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&wlan_reg>; + status = "okay"; +}; + +&mmc3 { + clock-frequency = <50000000>; + no-1-8-v; + bus-width = <8>; + non-removable; + broken-cd; + mrvl,clk-delay-cycles = <31>; + status = "okay"; +}; + +&twsi1 { + status = "okay"; + + audio-codec@1a { + compatible = "realtek,alc5631"; + reg = <0x1a>; + status = "okay"; + + port { + rt5631_0: endpoint { + mclk-fs = <256>; + clocks = <&audio_clk MMP2_CLK_AUDIO_SYSCLK>; + remote-endpoint = <&sspa0_0>; + }; + }; + }; +}; + +&twsi2 { + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + status = "okay"; + }; +}; + +&twsi6 { + status = "okay"; + + accelerometer@1d { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x1d>; + status = "okay"; + }; +}; + +&ssp3 { + #address-cells = <0>; + spi-slave; + status = "okay"; + ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>; + + slave { + compatible = "olpc,xo1.75-ec"; + spi-cpha; + cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>; + }; +}; + +&camera0 { + status = "okay"; + + port { + camera0_0: endpoint { + remote-endpoint = <&ov7670_0>; + }; + }; +}; + +&asram { + status = "okay"; +}; + +&adma0 { + status = "okay"; +}; + +&audio_clk { + status = "okay"; +}; + +&sspa0 { + status = "okay"; + dmas = <&adma0 0>, <&adma0 1>; + dma-names = "tx", "rx"; + + sspa0_dai: port { + sspa0_0: endpoint { + remote-endpoint = <&rt5631_0>; + frame-master; + bitclock-master; + dai-format = "i2s"; + }; + }; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/mmp2.dtsi b/arch/arm/boot/dts/marvell/mmp2.dtsi new file mode 100644 index 000000000000..987d792f67ea --- /dev/null +++ b/arch/arm/boot/dts/marvell/mmp2.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + gpu: gpu@d420d000 { + compatible = "vivante,gc"; + reg = <0xd420d000 0x4000>; + interrupts = <8>; + status = "disabled"; + clocks = <&soc_clocks MMP2_CLK_GPU_3D>, + <&soc_clocks MMP2_CLK_GPU_BUS>; + clock-names = "core", "bus"; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; + }; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + intcmux4: interrupt-controller@d4282150 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <4>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x150 0x4>, <0x168 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + intcmux5: interrupt-controller@d4282154 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <5>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x154 0x4>, <0x16c 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + mrvl,clr-mfp-irq = <1>; + }; + + intcmux9: interrupt-controller@d4282180 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <9>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x180 0x4>, <0x17c 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <3>; + }; + + intcmux17: interrupt-controller@d4282158 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <17>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x158 0x4>, <0x170 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <5>; + }; + + intcmux35: interrupt-controller@d428215c { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <35>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x15c 0x4>, <0x174 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <15>; + }; + + intcmux51: interrupt-controller@d4282160 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <51>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x160 0x4>, <0x178 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + intcmux55: interrupt-controller@d4282188 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <55>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x188 0x4>, <0x184 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + usb_phy0: usb-phy@d4207000 { + compatible = "marvell,mmp2-usb-phy"; + reg = <0xd4207000 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_otg0: usb-otg@d4208000 { + compatible = "marvell,pxau2o-ehci"; + reg = <0xd4208000 0x200>; + interrupts = <44>; + clocks = <&soc_clocks MMP2_CLK_USB>; + clock-names = "USBCLK"; + phys = <&usb_phy0>; + phy-names = "usb"; + status = "disabled"; + }; + + mmc1: mmc@d4280000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280000 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH0>; + clock-names = "io"; + interrupts = <39>; + status = "disabled"; + }; + + mmc2: mmc@d4280800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280800 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH1>; + clock-names = "io"; + interrupts = <52>; + status = "disabled"; + }; + + mmc3: mmc@d4281000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4281000 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH2>; + clock-names = "io"; + interrupts = <53>; + status = "disabled"; + }; + + mmc4: mmc@d4281800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4281800 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH3>; + clock-names = "io"; + interrupts = <54>; + status = "disabled"; + }; + + camera0: camera@d420a000 { + compatible = "marvell,mmp2-ccic"; + reg = <0xd420a000 0x800>; + interrupts = <42>; + clocks = <&soc_clocks MMP2_CLK_CCIC0>; + clock-names = "axi"; + #clock-cells = <0>; + clock-output-names = "mclk"; + status = "disabled"; + }; + + camera1: camera@d420a800 { + compatible = "marvell,mmp2-ccic"; + reg = <0xd420a800 0x800>; + interrupts = <30>; + clocks = <&soc_clocks MMP2_CLK_CCIC1>; + clock-names = "axi"; + #clock-cells = <0>; + clock-output-names = "mclk"; + status = "disabled"; + }; + + adma0: dma-controller@d42a0800 { + compatible = "marvell,adma-1.0"; + reg = <0xd42a0800 0x100>; + interrupts = <48>; + #dma-cells = <1>; + asram = <&asram>; + iram = <&asram>; + status = "disabled"; + }; + + adma1: dma-controller@d42a0900 { + compatible = "marvell,adma-1.0"; + reg = <0xd42a0900 0x100>; + interrupts = <48>; + #dma-cells = <1>; + status = "disabled"; + }; + + audio_clk: clocks@d42a0c30 { + compatible = "marvell,mmp2-audio-clock"; + reg = <0xd42a0c30 0x10>; + clock-names = "audio", "vctcxo", "i2s0", "i2s1"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&soc_clocks MMP2_CLK_VCTCXO>, + <&soc_clocks MMP2_CLK_I2S0>, + <&soc_clocks MMP2_CLK_I2S1>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #clock-cells = <1>; + status = "disabled"; + }; + + sspa0: audio-controller@d42a0c00 { + compatible = "marvell,mmp-sspa"; + reg = <0xd42a0c00 0x30>, + <0xd42a0c80 0x30>; + interrupts = <2>; + clock-names = "audio", "bitclk"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&audio_clk MMP2_CLK_AUDIO_SSPA0>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sspa1: audio-controller@d42a0d00 { + compatible = "marvell,mmp-sspa"; + reg = <0xd42a0d00 0x30>, + <0xd42a0d80 0x30>; + interrupts = <3>; + clock-names = "audio", "bitclk"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&audio_clk MMP2_CLK_AUDIO_SSPA1>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + }; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + dma-controller@d4000000 { + compatible = "marvell,pdma-1.0"; + reg = <0xd4000000 0x10000>; + interrupts = <48>; + /* For backwards compatibility: */ + #dma-channels = <16>; + dma-channels = <16>; + status = "disabled"; + }; + + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + clocks = <&soc_clocks MMP2_CLK_TIMER>; + }; + + uart1: serial@d4030000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4030000 0x1000>; + interrupts = <27>; + clocks = <&soc_clocks MMP2_CLK_UART0>; + resets = <&soc_clocks MMP2_CLK_UART0>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4017000 0x1000>; + interrupts = <28>; + clocks = <&soc_clocks MMP2_CLK_UART1>; + resets = <&soc_clocks MMP2_CLK_UART1>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4018000 0x1000>; + interrupts = <24>; + clocks = <&soc_clocks MMP2_CLK_UART2>; + resets = <&soc_clocks MMP2_CLK_UART2>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@d4016000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4016000 0x1000>; + interrupts = <46>; + clocks = <&soc_clocks MMP2_CLK_UART3>; + resets = <&soc_clocks MMP2_CLK_UART3>; + reg-shift = <2>; + status = "disabled"; + }; + + gpio: gpio@d4019000 { + compatible = "marvell,mmp2-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + clocks = <&soc_clocks MMP2_CLK_GPIO>; + resets = <&soc_clocks MMP2_CLK_GPIO>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + + gcb4: gpio@d4019104 { + reg = <0xd4019104 0x4>; + }; + + gcb5: gpio@d4019108 { + reg = <0xd4019108 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + clocks = <&soc_clocks MMP2_CLK_TWSI0>; + resets = <&soc_clocks MMP2_CLK_TWSI0>; + #address-cells = <1>; + #size-cells = <0>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4031000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4031000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <0>; + clocks = <&soc_clocks MMP2_CLK_TWSI1>; + resets = <&soc_clocks MMP2_CLK_TWSI1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi3: i2c@d4032000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4032000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <1>; + clocks = <&soc_clocks MMP2_CLK_TWSI2>; + resets = <&soc_clocks MMP2_CLK_TWSI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi4: i2c@d4033000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4033000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <2>; + clocks = <&soc_clocks MMP2_CLK_TWSI3>; + resets = <&soc_clocks MMP2_CLK_TWSI3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + twsi5: i2c@d4033800 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4033800 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <3>; + clocks = <&soc_clocks MMP2_CLK_TWSI4>; + resets = <&soc_clocks MMP2_CLK_TWSI4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi6: i2c@d4034000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4034000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <4>; + clocks = <&soc_clocks MMP2_CLK_TWSI5>; + resets = <&soc_clocks MMP2_CLK_TWSI5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <1>, <0>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + interrupt-parent = <&intcmux5>; + clocks = <&soc_clocks MMP2_CLK_RTC>; + resets = <&soc_clocks MMP2_CLK_RTC>; + status = "disabled"; + }; + + ssp1: spi@d4035000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4035000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP0>; + interrupts = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp2: spi@d4036000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4036000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP1>; + interrupts = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp3: spi@d4037000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4037000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP2>; + interrupts = <20>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp4: spi@d4039000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4039000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP3>; + interrupts = <21>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + asram: sram@e0000000 { + compatible = "mmio-sram"; + reg = <0xe0000000 0x10000>; + ranges = <0 0xe0000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + soc_clocks: clocks { + compatible = "marvell,mmp2-clock"; + reg = <0xd4050000 0x2000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts b/arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts new file mode 100644 index 000000000000..fe6df364a9eb --- /dev/null +++ b/arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D) + * + * Copyright (C) 2019 Lubomir Rintel + */ + +/dts-v1/; +#include "mmp3.dtsi" +#include +#include + +/ { + model = "Dell Ariel"; + compatible = "dell,wyse-ariel", "marvell,mmp3"; + + aliases { + serial2 = &uart3; + }; + + chosen { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200"; + }; + + memory@0 { + available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>; + reg = <0x0 0x80000000>; + device_type = "memory"; + }; + + ec_input_spi: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + num-chipselects = <0>; + sck-gpios = <&gpio 55 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart3 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&usb_otg0 { + status = "okay"; +}; + +&usb_otg_phy0 { + status = "okay"; +}; + +&hsic0 { + status = "okay"; + + usb1@1 { + compatible = "usb424,2640"; + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + mass-storage@1 { + compatible = "usb424,4040"; + reg = <0x01>; + status = "disabled"; + }; + }; +}; + +&hsic_phy0 { + status = "okay"; + reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; +}; + +&mmc3 { + status = "okay"; + max-frequency = <50000000>; + status = "okay"; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; +}; + +&twsi1 { + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + status = "okay"; + }; +}; + +&twsi3 { + status = "okay"; +}; + +&twsi4 { + status = "okay"; + + embedded-controller@58 { + compatible = "dell,wyse-ariel-ec", "ene,kb3930"; + reg = <0x58>; + system-power-controller; + + off-gpios = <&gpio 126 GPIO_ACTIVE_HIGH>, + <&gpio 127 GPIO_ACTIVE_HIGH>; + }; +}; + +&ssp1 { + status = "okay"; + cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + + firmware-flash@0 { + compatible = "winbond,w25q32", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + }; +}; + +&ec_input_spi { + status = "okay"; + cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + + power-button@0 { + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <60 IRQ_TYPE_EDGE_RISING>; + compatible = "dell,wyse-ariel-ec-input", "ene,kb3930-input"; + spi-max-frequency = <33000000>; + }; +}; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/mmp3.dtsi b/arch/arm/boot/dts/marvell/mmp3.dtsi new file mode 100644 index 000000000000..a4fb9203ec1f --- /dev/null +++ b/arch/arm/boot/dts/marvell/mmp3.dtsi @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Lubomir Rintel + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,mmp3-smp"; + + cpu@0 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + axi@d4200000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + interrupt-controller@d4282000 { + compatible = "marvell,mmp3-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>, + <0xd4284000 0x100>; + mrvl,intc-nr-irqs = <64>; + }; + + pmic_mux: interrupt-controller@d4282150 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x150 0x4>, <0x168 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <4>; + }; + + rtc_mux: interrupt-controller@d4282154 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x154 0x4>, <0x16c 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + hsi3_mux: interrupt-controller@d42821bc { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1bc 0x4>, <0x1a4 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <3>; + }; + + gpu_mux: interrupt-controller@d42821c0 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1c0 0x4>, <0x1a8 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <3>; + }; + + twsi_mux: interrupt-controller@d4282158 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x158 0x4>, <0x170 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <5>; + }; + + hsi2_mux: interrupt-controller@d42821c4 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1c4 0x4>, <0x1ac 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + dxo_mux: interrupt-controller@d42821c8 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1c8 0x4>, <0x1b0 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + misc1_mux: interrupt-controller@d428215c { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x15c 0x4>, <0x174 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <31>; + }; + + ci_mux: interrupt-controller@d42821cc { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1cc 0x4>, <0x1b4 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + ssp_mux: interrupt-controller@d4282160 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x160 0x4>, <0x178 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + hsi1_mux: interrupt-controller@d4282184 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x184 0x4>, <0x17c 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <4>; + }; + + misc2_mux: interrupt-controller@d4282188 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x188 0x4>, <0x180 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <20>; + }; + + hsi0_mux: interrupt-controller@d42821d0 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x1d0 0x4>, <0x1b8 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <5>; + }; + + usb_otg_phy0: usb-phy@d4207000 { + compatible = "marvell,mmp3-usb-phy"; + reg = <0xd4207000 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_otg0: usb@d4208000 { + compatible = "marvell,pxau2o-ehci"; + reg = <0xd4208000 0x200>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_USB>; + clock-names = "USBCLK"; + phys = <&usb_otg_phy0>; + phy-names = "usb"; + status = "disabled"; + }; + + hsic_phy0: usb-phy@f0001800 { + compatible = "marvell,mmp3-hsic-phy"; + reg = <0xf0001800 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; + + hsic0: usb@f0001000 { + compatible = "marvell,pxau2o-ehci"; + reg = <0xf0001000 0x200>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_USBHSIC0>; + clock-names = "USBCLK"; + phys = <&hsic_phy0>; + phy-names = "usb"; + phy_type = "hsic"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + hsic_phy1: usb-phy@f0002800 { + compatible = "marvell,mmp3-hsic-phy"; + reg = <0xf0002800 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; + + hsic1: usb@f0002000 { + compatible = "marvell,pxau2o-ehci"; + reg = <0xf0002000 0x200>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_USBHSIC1>; + clock-names = "USBCLK"; + phys = <&hsic_phy1>; + phy-names = "usb"; + phy_type = "hsic"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + mmc1: mmc@d4280000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280000 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH0>; + clock-names = "io"; + interrupts = ; + status = "disabled"; + }; + + mmc2: mmc@d4280800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280800 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH1>; + clock-names = "io"; + interrupts = ; + status = "disabled"; + }; + + mmc3: mmc@d4281000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4281000 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH2>; + clock-names = "io"; + interrupts = ; + status = "disabled"; + }; + + mmc4: mmc@d4281800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4281800 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH3>; + clock-names = "io"; + interrupts = ; + status = "disabled"; + }; + + mmc5: mmc@d4217000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4217000 0x120>; + clocks = <&soc_clocks MMP3_CLK_SDH4>; + clock-names = "io"; + interrupt-parent = <&hsi1_mux>; + interrupts = <0>; + status = "disabled"; + }; + + camera0: camera@d420a000 { + compatible = "marvell,mmp2-ccic"; + reg = <0xd420a000 0x800>; + interrupts = <1>; + interrupt-parent = <&ci_mux>; + clocks = <&soc_clocks MMP2_CLK_CCIC0>; + clock-names = "axi"; + power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; + #clock-cells = <0>; + clock-output-names = "mclk"; + status = "disabled"; + }; + + camera1: camera@d420a800 { + compatible = "marvell,mmp2-ccic"; + reg = <0xd420a800 0x800>; + interrupts = <2>; + interrupt-parent = <&ci_mux>; + clocks = <&soc_clocks MMP2_CLK_CCIC1>; + clock-names = "axi"; + power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; + #clock-cells = <0>; + clock-output-names = "mclk"; + status = "disabled"; + }; + + gpu_3d: gpu@d420d000 { + compatible = "vivante,gc"; + reg = <0xd420d000 0x2000>; + interrupt-parent = <&gpu_mux>; + interrupts = <0>; + status = "disabled"; + clocks = <&soc_clocks MMP3_CLK_GPU_3D>, + <&soc_clocks MMP3_CLK_GPU_BUS>; + clock-names = "core", "bus"; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; + }; + + gpu_2d: gpu@d420f000 { + compatible = "vivante,gc"; + reg = <0xd420f000 0x2000>; + interrupt-parent = <&gpu_mux>; + interrupts = <2>; + status = "disabled"; + clocks = <&soc_clocks MMP3_CLK_GPU_2D>, + <&soc_clocks MMP3_CLK_GPU_BUS>; + clock-names = "core", "bus"; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; + }; + }; + + apb@d4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + timer: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_TIMER>; + }; + + uart1: serial@d4030000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4030000 0x1000>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_UART0>; + resets = <&soc_clocks MMP2_CLK_UART0>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4017000 0x1000>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_UART1>; + resets = <&soc_clocks MMP2_CLK_UART1>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4018000 0x1000>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_UART2>; + resets = <&soc_clocks MMP2_CLK_UART2>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@d4016000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4016000 0x1000>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_UART3>; + resets = <&soc_clocks MMP2_CLK_UART3>; + reg-shift = <2>; + status = "disabled"; + }; + + gpio: gpio@d4019000 { + compatible = "marvell,mmp2-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-names = "gpio_mux"; + clocks = <&soc_clocks MMP2_CLK_GPIO>; + resets = <&soc_clocks MMP2_CLK_GPIO>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + + gcb4: gpio@d4019104 { + reg = <0xd4019104 0x4>; + }; + + gcb5: gpio@d4019108 { + reg = <0xd4019108 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4011000 0x70>; + interrupts = ; + clocks = <&soc_clocks MMP2_CLK_TWSI0>; + resets = <&soc_clocks MMP2_CLK_TWSI0>; + #address-cells = <1>; + #size-cells = <0>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4031000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4031000 0x70>; + interrupt-parent = <&twsi_mux>; + interrupts = <0>; + clocks = <&soc_clocks MMP2_CLK_TWSI1>; + resets = <&soc_clocks MMP2_CLK_TWSI1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi3: i2c@d4032000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4032000 0x70>; + interrupt-parent = <&twsi_mux>; + interrupts = <1>; + clocks = <&soc_clocks MMP2_CLK_TWSI2>; + resets = <&soc_clocks MMP2_CLK_TWSI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi4: i2c@d4033000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4033000 0x70>; + interrupt-parent = <&twsi_mux>; + interrupts = <2>; + clocks = <&soc_clocks MMP2_CLK_TWSI3>; + resets = <&soc_clocks MMP2_CLK_TWSI3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + twsi5: i2c@d4033800 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4033800 0x70>; + interrupt-parent = <&twsi_mux>; + interrupts = <3>; + clocks = <&soc_clocks MMP2_CLK_TWSI4>; + resets = <&soc_clocks MMP2_CLK_TWSI4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi6: i2c@d4034000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4034000 0x70>; + interrupt-parent = <&twsi_mux>; + interrupts = <4>; + clocks = <&soc_clocks MMP2_CLK_TWSI5>; + resets = <&soc_clocks MMP2_CLK_TWSI5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <1>, <0>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + interrupt-parent = <&rtc_mux>; + clocks = <&soc_clocks MMP2_CLK_RTC>; + resets = <&soc_clocks MMP2_CLK_RTC>; + status = "disabled"; + }; + + ssp1: spi@d4035000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4035000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp2: spi@d4036000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4036000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp3: spi@d4037000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4037000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp4: spi@d4039000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4039000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + l2: cache-controller@d0020000 { + compatible = "marvell,tauros3-cache", "arm,pl310-cache"; + reg = <0xd0020000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + soc_clocks: clocks@d4050000 { + compatible = "marvell,mmp3-clock"; + reg = <0xd4050000 0x2000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + snoop-control-unit@e0000000 { + compatible = "arm,arm11mp-scu"; + reg = <0xe0000000 0x100>; + }; + + gic: interrupt-controller@e0001000 { + compatible = "arm,arm11mp-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xe0001000 0x1000>, + <0xe0000100 0x100>; + }; + + local-timer@e0000600 { + compatible = "arm,arm11mp-twd-timer"; + interrupts = ; + reg = <0xe0000600 0x20>; + }; + + watchdog@e0000620 { + compatible = "arm,arm11mp-twd-wdt"; + reg = <0xe0000620 0x20>; + interrupts = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi new file mode 100644 index 000000000000..e172029a0c4d --- /dev/null +++ b/arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi @@ -0,0 +1,72 @@ +/* + * Device Tree common file for gpio-fan on Buffalo Linkstation + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + gpio-fan,speed-map = + <0 3 + 1500 2 + 3250 1 + 5000 0>; + }; +}; + +&pinctrl { + pmx_fan_low: pmx-fan-low { + marvell,function = "gpio"; + }; + + pmx_fan_high: pmx-fan-high { + marvell,function = "gpio"; + }; + + pmx_fan_lock: pmx-fan-lock { + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi new file mode 100644 index 000000000000..c2d87ba6190a --- /dev/null +++ b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi @@ -0,0 +1,105 @@ +/* + * Device Tree common file for gpio-{keys,leds} on Buffalo Linkstation + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_switch>; + pinctrl-names = "default"; + + power-on-switch { + label = "Power-on Switch"; + linux,code = ; + linux,input-type = <5>; + }; + + power-auto-switch { + label = "Power-auto Switch"; + linux,code = ; + linux,input-type = <5>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info>; + pinctrl-names = "default"; + + blue-power-led { + label = "linkstation:blue:power"; + default-state = "keep"; + }; + + red-alarm-led { + label = "linkstation:red:alarm"; + }; + + amber-info-led { + label = "linkstation:amber:info"; + }; + }; +}; + +&pinctrl { + pmx_power_switch: pmx-power-switch { + marvell,function = "gpio"; + }; + + pmx_led_power: pmx-leds { + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts b/arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts new file mode 100644 index 000000000000..e28b568e741a --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts @@ -0,0 +1,127 @@ +/* + * Device Tree file for Buffalo/Revogear Kurobox Pro + * + * Copyright (C) 2016 + * Roger Shimizu + * + * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c + * Copyright (C) Ronen Shitrit + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include + +/ { + model = "Buffalo/Revogear Kurobox Pro"; + compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x"; + + soc { + ranges = , + , + , + ; + }; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; +}; + +&pinctrl { + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; +}; + +&devbus_cs0 { + status = "okay"; + compatible = "marvell,orion-nand"; + reg = ; + cle = <0>; + ale = <1>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uImage@0 { /* 4 MB */ + reg = <0 0x400000>; + read-only; + }; + + rootfs@400000 { /* 64 MB */ + reg = <0x400000 0x4000000>; + read-only; + }; + + extra@4400000 { /* 188 MB */ + reg = <0x4400000 0xBC00000>; + read-only; + }; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + +&sata { + nr-ports = <2>; +}; + +&ehci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts new file mode 100644 index 000000000000..03471d30bfd9 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Thomas Petazzoni + * Copyright (C) 2009 Simon Guinot + */ + +/dts-v1/; + +#include +#include +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "LaCie d2 Network"; + compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + front_button { + label = "Front Push Button"; + linux,code = ; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + }; + + power_rocker_sw_on { + label = "Power rocker switch (on|auto)"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + }; + + power_rocker_sw_off { + label = "Power rocker switch (auto|off)"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; + pinctrl-names = "default"; + + sata0_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full512Kb"; + reg = <0 0x80000>; + read-only; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372b"; + reg = <0x32>; + }; + + fan@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + + /* Not enough HW info */ + status = "disabled"; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; + pinctrl-names = "default"; + + pmx_board_id: pmx-board-id { + marvell,pins = "mpp0", "mpp1", "mpp2"; + marvell,function = "gpio"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp8", "mpp9", "mpp18"; + marvell,function = "gpio"; + }; + + pmx_fan_fail: pmx-fan-fail { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + /* + * MPP6: Red front LED + * MPP16: Blue front LED blink control + */ + pmx_leds: pmx-leds { + marvell,pins = "mpp6", "mpp16"; + marvell,function = "gpio"; + }; + + pmx_sata0_led_active: pmx-sata0-led-active { + marvell,pins = "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata0_power: pmx-sata0-power { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_sata1_led_active: pmx-sata1-led-active { + marvell,pins = "mpp15"; + marvell,function = "sata1"; + }; + + pmx_sata1_power: pmx-sata1-power { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + /* + * Non MPP GPIOs: + * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) + * GPIO 23: Blue front LED off + * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) + */ +}; + +&sata { + pinctrl-0 = <&pmx_sata0_led_active + &pmx_sata1_led_active>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts new file mode 100644 index 000000000000..f17e25ac98dd --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012 Thomas Petazzoni + +/* + * TODO: add Orion USB device port init when kernel.org support is added. + * TODO: add flash write support: see below. + * TODO: add power-off support. + * TODO: add I2C EEPROM support. + */ + +/dts-v1/; + +#include +#include +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "LaCie Ethernet Disk mini V2"; + compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_power_button>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + button@1 { + label = "Power-on Switch"; + linux,code = ; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led>; + pinctrl-names = "default"; + + led@1 { + label = "power:blue"; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full512Kb"; + reg = <0 0x80000>; + read-only; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; + pinctrl-names = "default"; + + pmx_power_button: pmx-power-button { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_power_led_ctrl: pmx-power-led-ctrl { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts new file mode 100644 index 000000000000..ee751995c8d0 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts @@ -0,0 +1,171 @@ +/* + * Device Tree file for Buffalo Linkstation LS-CHLv3 + * + * Copyright (C) 2016 Ash Hughes + * Copyright (C) 2015-2017 + * Roger Shimizu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include "mvebu-linkstation-gpio-simple.dtsi" +#include "mvebu-linkstation-fan.dtsi" +#include + +/ { + model = "Buffalo Linkstation LiveV3 (LS-CHL)"; + compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + gpio_keys { + func { + label = "Function Button"; + linux,code = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + power-on-switch { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + power-auto-switch { + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>; + blue-power-led { + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + red-alarm-led { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + amber-info-led { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + func { + label = "lschl:func:blue:top"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW + &gpio0 16 GPIO_ACTIVE_LOW>; + + alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + pmx_led_power: pmx-leds { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp8", "mpp10", "mpp15"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_func: pmx-leds { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_sw_init: pmx-sw-init { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts new file mode 100644 index 000000000000..9f6fedd39170 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts @@ -0,0 +1,91 @@ +/* + * Device Tree file for Buffalo Linkstation LS-GL + * (also known as Buffalo Linkstation Pro/Live) + * + * Copyright (C) 2016 + * Roger Shimizu + * + * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c + * Copyright (C) Ronen Shitrit + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include + +/ { + model = "Buffalo Linkstation Pro/Live"; + compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; +}; + +&pinctrl { + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + +&sata { + nr-ports = <2>; +}; + +&ehci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts new file mode 100644 index 000000000000..7f77ce8cc1fc --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts @@ -0,0 +1,151 @@ +/* + * Device Tree file for Buffalo Linkstation LS-WTGL + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include "mvebu-linkstation-gpio-simple.dtsi" +#include "mvebu-linkstation-fan.dtsi" +#include + +/ { + model = "Buffalo Linkstation LS-WTGL"; + compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { /* 64 MB */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + gpio_keys { + power-on-switch { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + power-auto-switch { + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + blue-power-led { + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + red-alarm-led { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + amber-info-led { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW + &gpio0 17 GPIO_ACTIVE_LOW>; + + alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + pmx_led_power: pmx-leds { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp8", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + +&sata { + nr-ports = <2>; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi b/arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi new file mode 100644 index 000000000000..b6c9b85951ea --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi @@ -0,0 +1,180 @@ +/* + * Device Tree common file for orion5x based Buffalo Linkstation + * + * Copyright (C) 2015, 2016 + * Roger Shimizu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "orion5x-mv88f5182.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + hdd_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + }; +}; + +&pinctrl { + pmx_power_hdd: pmx-power-hdd { + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,function = "gpio"; + }; +}; + +&devbus_bootcs { + status = "okay"; + devbus,keep-config; + + flash@0 { + compatible = "jedec-flash"; + reg = <0 0x40000>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + header@0 { + reg = <0 0x30000>; + read-only; + }; + + uboot@30000 { + reg = <0x30000 0xF000>; + read-only; + }; + + uboot_env@3F000 { + reg = <0x3F000 0x1000>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c { + status = "okay"; + + rtc@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; +}; + +&wdt { + status = "disabled"; +}; + +&sata { + status = "okay"; + nr-ports = <1>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts new file mode 100644 index 000000000000..2fbc17d6dfa4 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2015 Benjamin Cama + * Copyright (C) 2014 Thomas Petazzoni + * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c, + * Copyright (C) 2008 Alexey Kopytko + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Buffalo Linkstation Mini (LS-WSGL)"; + compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + func { + label = "Function Button"; + linux,code = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + power { + label = "Power-on Switch"; + linux,input-type = <5>; /* EV_SW */ + linux,code = ; /* LSMINI_SW_POWER */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + + autopower { + label = "Power-auto Switch"; + linux,input-type = <5>; /* EV_SW */ + linux,code = ; /* LSMINI_SW_AUTOPOWER */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func + &pmx_led_power>; + pinctrl-names = "default"; + + alarm { + label = "lswsgl:alarm:red"; + gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + info { + label = "lswsgl:info:amber"; + gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + func { + label = "lswsgl:func:blue:top"; + gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + power { + label = "lswsgl:power:blue:bottom"; + gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>; + pinctrl-names = "default"; + + sata0_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; + }; + + usb_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x40000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full256Kb"; + reg = <0 0x40000>; + read-only; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; +}; + +&pinctrl { + pmx_buttons: pmx-buttons { + marvell,pins = "mpp15", "mpp17", "mpp18"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_led_func: pmx-leds { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_led_power: pmx-leds { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_sata0_power: pmx-sata0-power { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_sata1_power: pmx-sata1-power { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts new file mode 100644 index 000000000000..d57859998350 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Thomas Petazzoni + * Copyright (C) Sylver Bruneau + */ + +/dts-v1/; + +#include +#include +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Maxtor Shared Storage II"; + compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + power { + label = "Power"; + linux,code = ; + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x40000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@68 { + compatible = "st,m41t81"; + reg = <0x68>; + pinctrl-0 = <&pmx_rtc>; + pinctrl-names = "default"; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_leds &pmx_misc>; + pinctrl-names = "default"; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp11", "mpp12"; + marvell,function = "gpio"; + }; + + /* + * MPP0: Power LED + * MPP1: Error LED + */ + pmx_leds: pmx-leds { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "gpio"; + }; + + /* + * MPP4: HDD ind. (Single/Dual) + * MPP5: HD0 5V control + * MPP6: HD0 12V control + * MPP7: HD1 5V control + * MPP8: HD1 12V control + */ + pmx_misc: pmx-misc { + marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_sata0_led_active: pmx-sata0-led-active { + marvell,pins = "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata1_led_active: pmx-sata1-led-active { + marvell,pins = "mpp15"; + marvell,function = "sata1"; + }; + + /* + * Non MPP GPIOs: + * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) + * GPIO 23: Blue front LED off + * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) + */ +}; + +&sata { + pinctrl-0 = <&pmx_sata0_led_active + &pmx_sata1_led_active>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi new file mode 100644 index 000000000000..819f9efb7058 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2016 Jamie Lentin + +#include "orion5x.dtsi" + +/ { + compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; + + soc { + compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; + + internal-regs { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f5181-pinctrl"; + reg = <0x10000 0x8>, <0x10050 0x4>; + }; + + core_clk: core-clocks@10030 { + compatible = "marvell,mv88f5181-core-clock"; + reg = <0x10010 0x4>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x1500 0x20>; + }; + }; + }; +}; + +&pinctrl { + pmx_ge: pmx-ge { + marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; + marvell,function = "ge"; + }; +}; + +ð { + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi new file mode 100644 index 000000000000..86b87fb26dc9 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Thomas Petazzoni + +#include "orion5x.dtsi" + +/ { + compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; + + soc { + compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; + + internal-regs { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f5182-pinctrl"; + reg = <0x10000 0x8>, <0x10050 0x4>; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp12", "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp13", "mpp15"; + marvell,function = "sata1"; + }; + }; + + core_clk: core-clocks@10030 { + compatible = "marvell,mv88f5182-core-clock"; + reg = <0x10010 0x4>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x1500 0x20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts new file mode 100644 index 000000000000..fb203e7d37f5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2016 Jamie Lentin + +/dts-v1/; + +#include +#include +#include "orion5x-mv88f5181.dtsi" + +/ { + model = "Netgear WNR854-t"; + compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", + "marvell,orion5x"; + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x2000000>; /* 32 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_reset_button>; + pinctrl-names = "default"; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; + pinctrl-names = "default"; + + led@0 { + label = "wnr854t:green:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "wnr854t:blink:power"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "wnr854t:green:wan"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "rootfs"; + reg = <0x100000 0x660000>; + }; + + partition@760000 { + label = "uboot_env"; + reg = <0x760000 0x20000>; + }; + + partition@780000 { + label = "uboot"; + reg = <0x780000 0x80000>; + read-only; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + phy-handle = <&lan3phy>; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-handle = <&lan4phy>; + }; + + port@2 { + reg = <2>; + label = "wan"; + phy-handle = <&wanphy>; + }; + + port@3 { + reg = <3>; + ethernet = <ðport>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "lan1"; + phy-handle = <&lan1phy>; + }; + + port@7 { + reg = <7>; + label = "lan2"; + phy-handle = <&lan2phy>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + lan3phy: ethernet-phy@0 { + /* Marvell 88E1121R (port 1) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan4phy: ethernet-phy@1 { + /* Marvell 88E1121R (port 2) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + wanphy: ethernet-phy@2 { + /* Marvell 88E1121R (port 1) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan1phy: ethernet-phy@5 { + /* Marvell 88E1112 */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <5>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan2phy: ethernet-phy@7 { + /* Marvell 88E1112 */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + }; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + /* Hardwired to DSA switch */ + speed = <1000>; + duplex = <1>; + phy-mode = "rgmii"; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_pci_gpios>; + pinctrl-names = "default"; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_led_blink: pmx-power-led-blink { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_wan_led: pmx-wan-led { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts new file mode 100644 index 000000000000..fd78aa02a3c5 --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Thomas Petazzoni + +/dts-v1/; + +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Marvell Reference Design 88F5182 NAS"; + compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + soc { + ranges = , + , + , + ; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_debug_led>; + pinctrl-names = "default"; + + led@0 { + label = "rd88f5182:cpu"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + }; +}; + +&devbus_cs1 { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <1>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@68 { + pinctrl-0 = <&pmx_rtc>; + pinctrl-names = "default"; + compatible = "dallas,ds1338"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios + &pmx_pci_gpios>; + pinctrl-names = "default"; + + /* + * MPP[20] PCI Clock to MV88F5182 + * MPP[21] PCI Clock to mini PCI CON11 + * MPP[22] USB 0 over current indication + * MPP[23] USB 1 over current indication + * MPP[24] USB 1 over current enable + * MPP[25] USB 0 over current enable + */ + + pmx_debug_led: pmx-debug_led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_switch: pmx-reset-switch { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_misc_gpios: pmx-misc-gpios { + marvell,pins = "mpp4", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp6", "mpp7"; + marvell,function = "gpio"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/orion5x.dtsi b/arch/arm/boot/dts/marvell/orion5x.dtsi new file mode 100644 index 000000000000..2d41f5c166ee --- /dev/null +++ b/arch/arm/boot/dts/marvell/orion5x.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012 Thomas Petazzoni + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Orion5x SoC"; + compatible = "marvell,orion5x"; + interrupt-parent = <&intc>; + + aliases { + gpio0 = &gpio0; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + + devbus_bootcs: devbus-bootcs { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + devbus_cs0: devbus-cs0 { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + devbus_cs1: devbus-cs1 { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + devbus_cs2: devbus-cs2 { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + gpio0: gpio@10100 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x10100 0x40>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <6>, <7>, <8>, <9>; + }; + + spi: spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + reg = <0x10600 0x28>; + status = "disabled"; + }; + + i2c: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <5>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <3>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <4>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <4>; + }; + + intc: interrupt-controller@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x08>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + wdt: wdt@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>, <0x20108 0x4>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; + clocks = <&core_clk 0>; + status = "okay"; + }; + + ehci0: ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17>; + status = "disabled"; + }; + + xor: dma-controller@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor00 { + interrupts = <30>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <31>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + eth: ethernet-controller@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethport: ethernet-port@0 { + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <21>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <22>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + sata: sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <29>; + status = "disabled"; + }; + + cesa: crypto@90000 { + compatible = "marvell,orion-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <28>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x800>; + status = "okay"; + }; + + ehci1: ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + }; + + crypto_sram: sa-sram { + compatible = "mmio-sram"; + reg = ; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/pxa168-aspenite.dts b/arch/arm/boot/dts/marvell/pxa168-aspenite.dts new file mode 100644 index 000000000000..8bade6bf395b --- /dev/null +++ b/arch/arm/boot/dts/marvell/pxa168-aspenite.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + */ + +/dts-v1/; +#include "pxa168.dtsi" + +/ { + model = "Marvell PXA168 Aspenite Development Board"; + compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + reg = <0x00000000 0x04000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&twsi1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/pxa168.dtsi b/arch/arm/boot/dts/marvell/pxa168.dtsi new file mode 100644 index 000000000000..16212b912b94 --- /dev/null +++ b/arch/arm/boot/dts/marvell/pxa168.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + }; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + clocks = <&soc_clocks PXA168_CLK_TIMER>; + resets = <&soc_clocks PXA168_CLK_TIMER>; + }; + + uart1: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4017000 0x1000>; + reg-shift = <2>; + interrupts = <27>; + clocks = <&soc_clocks PXA168_CLK_UART0>; + resets = <&soc_clocks PXA168_CLK_UART0>; + status = "disabled"; + }; + + uart2: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4018000 0x1000>; + reg-shift = <2>; + interrupts = <28>; + clocks = <&soc_clocks PXA168_CLK_UART1>; + resets = <&soc_clocks PXA168_CLK_UART1>; + status = "disabled"; + }; + + uart3: serial@d4026000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4026000 0x1000>; + reg-shift = <2>; + interrupts = <29>; + clocks = <&soc_clocks PXA168_CLK_UART2>; + resets = <&soc_clocks PXA168_CLK_UART2>; + status = "disabled"; + }; + + gpio@d4019000 { + compatible = "marvell,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <49>; + clocks = <&soc_clocks PXA168_CLK_GPIO>; + resets = <&soc_clocks PXA168_CLK_GPIO>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + clocks = <&soc_clocks PXA168_CLK_TWSI0>; + resets = <&soc_clocks PXA168_CLK_TWSI0>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4025000 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd4025000 0x1000>; + interrupts = <58>; + clocks = <&soc_clocks PXA168_CLK_TWSI1>; + resets = <&soc_clocks PXA168_CLK_TWSI1>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <5>, <6>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + clocks = <&soc_clocks PXA168_CLK_RTC>; + resets = <&soc_clocks PXA168_CLK_RTC>; + status = "disabled"; + }; + }; + + soc_clocks: clocks{ + compatible = "marvell,pxa168-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/pxa910-dkb.dts b/arch/arm/boot/dts/marvell/pxa910-dkb.dts new file mode 100644 index 000000000000..ce76158867c7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/pxa910-dkb.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + */ + +/dts-v1/; +#include "pxa910.dtsi" + +/ { + model = "Marvell PXA910 DKB Development Board"; + compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + reg = <0x00000000 0x10000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&twsi1 { + status = "okay"; + + pmic: 88pm860x@34 { + compatible = "marvell,88pm860x"; + reg = <0x34>; + interrupts = <4>; + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <1>; + + marvell,88pm860x-irq-read-clr; + marvell,88pm860x-slave-addr = <0x11>; + + regulators { + BUCK1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + regulator-always-on; + }; + LDO2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO5 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO13 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + rtc { + marvell,88pm860x-vrtc = <1>; + }; + touch { + marvell,88pm860x-gpadc-prebias = <1>; + marvell,88pm860x-gpadc-slot-cycle = <1>; + marvell,88pm860x-tsi-prebias = <6>; + marvell,88pm860x-pen-prebias = <16>; + marvell,88pm860x-pen-prechg = <2>; + marvell,88pm860x-resistor-X = <300>; + }; + backlights { + backlight-0 { + marvell,88pm860x-iset = <4>; + marvell,88pm860x-pwm = <3>; + }; + backlight-2 { + }; + }; + leds { + led0-red { + marvell,88pm860x-iset = <12>; + }; + led0-green { + marvell,88pm860x-iset = <12>; + }; + led0-blue { + marvell,88pm860x-iset = <12>; + }; + }; + }; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/pxa910.dtsi b/arch/arm/boot/dts/marvell/pxa910.dtsi new file mode 100644 index 000000000000..352a39357810 --- /dev/null +++ b/arch/arm/boot/dts/marvell/pxa910.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + }; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + }; + + timer1: timer@d4016000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4016000 0x100>; + interrupts = <29>; + status = "disabled"; + }; + + uart1: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4017000 0x1000>; + reg-shift = <2>; + interrupts = <27>; + clocks = <&soc_clocks PXA910_CLK_UART0>; + resets = <&soc_clocks PXA910_CLK_UART0>; + status = "disabled"; + }; + + uart2: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4018000 0x1000>; + reg-shift = <2>; + interrupts = <28>; + clocks = <&soc_clocks PXA910_CLK_UART1>; + resets = <&soc_clocks PXA910_CLK_UART1>; + status = "disabled"; + }; + + uart3: serial@d4036000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0xd4036000 0x1000>; + reg-shift = <2>; + interrupts = <59>; + clocks = <&soc_clocks PXA910_CLK_UART2>; + resets = <&soc_clocks PXA910_CLK_UART2>; + status = "disabled"; + }; + + gpio@d4019000 { + compatible = "marvell,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + clocks = <&soc_clocks PXA910_CLK_GPIO>; + resets = <&soc_clocks PXA910_CLK_GPIO>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + clocks = <&soc_clocks PXA910_CLK_TWSI0>; + resets = <&soc_clocks PXA910_CLK_TWSI0>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4037000 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd4037000 0x1000>; + interrupts = <54>; + clocks = <&soc_clocks PXA910_CLK_TWSI1>; + resets = <&soc_clocks PXA910_CLK_TWSI1>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <5>, <6>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + clocks = <&soc_clocks PXA910_CLK_RTC>; + resets = <&soc_clocks PXA910_CLK_RTC>; + status = "disabled"; + }; + }; + + soc_clocks: clocks{ + compatible = "marvell,pxa910-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>, + <0xd403b000 0x1000>; + reg-names = "mpmu", "apmu", "apbc", "apbcp"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi deleted file mode 100644 index e3b2d23068f7..000000000000 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ /dev/null @@ -1,573 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel - */ - -/ { - model = "TQ-Systems MBA6ULx Baseboard"; - - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc1; - rtc0 = &rtc0; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <®_mba6ul_3v3>; - enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - beeper: beeper { - compatible = "gpio-beeper"; - gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; - }; - - gpio_buttons: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buttons>; - - button1 { - label = "s14"; - linux,code = ; - gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; - }; - - button2 { - label = "s6"; - linux,code = ; - gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "s7"; - linux,code = ; - gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; - }; - - power-button { - label = "POWER"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - status = "okay"; - - led1 { - label = "led1"; - gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led2 { - label = "led2"; - gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_lcd_pwr: regulator-lcd-pwr { - compatible = "regulator-fixed"; - regulator-name = "lcd-pwr"; - gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_mba6ul_3v3: regulator-mba6ul-3v3 { - compatible = "regulator-fixed"; - regulator-name = "supply-mba6ul-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_mba6ul_5v0: regulator-mba6ul-5v0 { - compatible = "regulator-fixed"; - regulator-name = "supply-mba6ul-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_mpcie: regulator-mpcie-3v3 { - compatible = "regulator-fixed"; - regulator-name = "mpcie-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - startup-delay-us = <500000>; - vin-supply = <®_mba6ul_3v3>; - }; - - reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { - compatible = "regulator-fixed"; - gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "otg2-vbus-supply-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_mpcie>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x6000000>; - linux,cma-default; - }; - }; - - sound { - compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; - ssi-controller = <&sai1>; - audio-codec = <&tlv320aic32x4>; - audio-asrc = <&asrc>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_mba6ul_3v3>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_mba6ul_3v3>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <768000000>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - num-cs = <1>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <®_mba6ul_3v3>; - phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-reset-post-delay = <1>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-supply = <®_mba6ul_3v3>; - phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-reset-post-delay = <1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - reg = <0>; - max-speed = <100>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; - reg = <1>; - max-speed = <100>; - }; - }; -}; - -&i2c4 { - tlv320aic32x4: audio-codec@18 { - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&clks IMX6UL_CLK_SAI1>; - clock-names = "mclk"; - ldoin-supply = <®_mba6ul_3v3>; - iov-supply = <®_mba6ul_3v3>; - }; - - jc42: temperature-sensor@19 { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x19>; - }; - - expander_out0: gpio-expander@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <®_mba6ul_3v3>; - }; - - expander_in0: gpio-expander@21 { - compatible = "nxp,pca9554"; - reg = <0x21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_expander_in0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <®_mba6ul_3v3>; - - enet1_int-hog { - gpio-hog; - gpios = <6 0>; - input; - }; - - enet2_int-hog { - gpio-hog; - gpios = <7 0>; - input; - }; - }; - - expander_out1: gpio-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <®_mba6ul_3v3>; - }; - - analog_touch: touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - interrupts = <21 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio4>; - interrupt-controller; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ - st,ave-ctrl = <3>; /* 8 sample average control */ - st,fraction-z = <7>; /* 7 length fractional part in z */ - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - st,mod-12b = <1>; /* 12-bit ADC */ - st,ref-sel = <0>; /* internal ADC reference */ - st,sample-time = <4>; /* ADC converstion time: 80 clocks */ - st,settling = <3>; /* 1 ms panel driver settling time */ - st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ - }; - }; - - /* NXP SE97BTP with temperature sensor + eeprom */ - se97b: eeprom@51 { - compatible = "nxp,se97b", "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - vcc-supply = <®_mba6ul_3v3>; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, - <&clks IMX6UL_CLK_SAI1>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <24000000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - /* for DTE mode, add below change */ - /* fsl,dte-mode; */ - /* pinctrl-0 = <&pinctrl_uart6dte>; */ - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* otg-port */ -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - power-active-high; - over-current-active-low; - /* we implement only dual role but not a fully featured OTG */ - hnp-disable; - srp-disable; - adp-disable; - dr_mode = "otg"; - status = "okay"; -}; - -/* 7-port usb hub */ -/* id, pwr, oc pins not connected */ -&usbotg2 { - disable-over-current; - vbus-supply = <®_otg2vbus_5v0>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - vmmc-supply = <®_mba6ul_3v3>; - vqmmc-supply = <®_vccsd>; - no-1-8-v; - no-mmc; - no-sdio; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_buttons: buttonsgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 - MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 - MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 - MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 - >; - }; - - pinctrl_enet2_mdc: enet2mdcgrp { - fsl,pins = < - /* mdio */ - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_expander_in0: expanderin0grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 - MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 - MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 - MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 - MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 - MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 - MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_uart6dte: uart6dte { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 - MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 - MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 - MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 - MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 - MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 - /* WP */ - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 - /* CD */ - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 - /* WP */ - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 - /* CD */ - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 - /* WP */ - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 - /* CD */ - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 - >; - }; -}; diff --git a/arch/arm/boot/dts/mediatek/Makefile b/arch/arm/boot/dts/mediatek/Makefile new file mode 100644 index 000000000000..1957947cb41c --- /dev/null +++ b/arch/arm/boot/dts/mediatek/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt2701-evb.dtb \ + mt6580-evbp1.dtb \ + mt6582-prestigio-pmt5008-3g.dtb \ + mt6589-aquaris5.dtb \ + mt6589-fairphone-fp1.dtb \ + mt6592-evb.dtb \ + mt7623a-rfb-emmc.dtb \ + mt7623a-rfb-nand.dtb \ + mt7623n-rfb-emmc.dtb \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb diff --git a/arch/arm/boot/dts/mediatek/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts new file mode 100644 index 000000000000..d1535f385f36 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt2701-evb.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Erin Lo + * + */ + +/dts-v1/; +#include +#include "mt2701.dtsi" + +/ { + model = "MediaTek MT2701 evaluation board"; + compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + sound:sound { + compatible = "mediatek,mt2701-cs42448-machine"; + mediatek,platform = <&afe>; + /* CS42448 Machine name */ + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "AMIC", + "AIN1R", "AMIC", + "AIN2L", "Tuner In", + "AIN2R", "Tuner In", + "AIN3L", "Satellite Tuner In", + "AIN3R", "Satellite Tuner In", + "AIN3L", "AUX In", + "AIN3R", "AUX In"; + mediatek,audio-codec = <&cs42448>; + mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + i2s1-in-sel-gpio1 = <&pio 53 0>; + i2s1-in-sel-gpio2 = <&pio 54 0>; + status = "okay"; + }; + + bt_sco_codec:bt_sco_codec { + compatible = "linux,bt-sco"; + }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&bls 0 100000>; + brightness-levels = < + 0 16 32 48 64 80 96 112 + 128 144 160 176 192 208 224 240 + 255 + >; + default-brightness-level = <9>; + }; + + usb_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&auxadc { + status = "okay"; +}; + +&bls { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_bls_gpio>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + cs42448: cs42448@48 { + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; + clock-names = "mclk"; + }; +}; + +&pio { + i2c0_pins_a: i2c0@0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1@0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins_a: i2c2@0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + pwm_bls_gpio: pwm_bls_gpio { + pins_cmd_dat { + pinmux = ; + }; + }; + + spi_pins_a: spi0@0 { + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + aud_pins_default: audiodefault { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = ; + bias-pull-down; + }; + }; + + spi_pins_b: spi1@0 { + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_c: spi2@0 { + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_a>; + status = "disabled"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_b>; + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_c>; + status = "disabled"; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pio { + nor_pins_default: nor { + pins1 { + pinmux = , + , + , + , + , + ; + drive-strength = ; + bias-pull-up; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb2 { + status = "okay"; + usb-role-switch; + connector{ + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_vbus>; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt2701-pinfunc.h b/arch/arm/boot/dts/mediatek/mt2701-pinfunc.h new file mode 100644 index 000000000000..136a25a0ae28 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt2701-pinfunc.h @@ -0,0 +1,727 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Biao Huang + */ + +#ifndef __DTS_MT2701_PINFUNC_H +#define __DTS_MT2701_PINFUNC_H + +#include + +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) + +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) + +#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) + +#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) + +#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) + +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) + +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7) + +#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) +#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4) +#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7) + +#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) +#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) +#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4) +#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7) + +#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) +#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) +#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4) +#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7) + +#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) + +#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) + +#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) + +#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) + +#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) +#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2) +#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) +#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7) + +#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) +#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2) +#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7) + +#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) +#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) +#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) +#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) +#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6) +#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7) + +#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) +#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) +#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) +#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6) +#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7) + +#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) +#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2) +#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3) +#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) +#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) +#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6) +#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7) + +#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) +#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2) +#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3) +#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) +#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) +#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6) +#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7) + +#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1) +#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3) +#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) +#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) +#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7) +#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10) + +#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1) +#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3) +#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) +#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) +#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7) +#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10) + +#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1) +#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3) +#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) +#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7) +#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10) + +#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1) +#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3) +#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) +#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7) + +#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1) +#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) +#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3) +#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) +#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) +#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) +#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7) + +#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1) +#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) +#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3) +#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) +#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) +#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7) + +#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) +#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3) +#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) +#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) +#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7) + +#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1) +#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) +#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3) +#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) +#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) +#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7) +#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14) + +#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) +#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) +#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3) +#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) +#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) +#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6) +#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7) + +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3) +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6) +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7) + +#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) +#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) +#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) +#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6) +#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7) + +#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) +#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) +#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) +#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6) +#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7) + +#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) +#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) +#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7) + +#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) +#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) +#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) +#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) + +#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) +#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) +#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) +#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) + +#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) +#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) +#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) + +#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) +#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) +#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) + +#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1) +#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) + +#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1) +#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2) + +#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1) +#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) + +#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1) + +#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1) +#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) + +#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1) +#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) + +#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) +#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) +#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3) +#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6) +#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7) + +#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) +#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3) +#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) +#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5) +#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7) + +#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) +#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) +#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) +#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7) + +#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) +#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) +#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) +#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) +#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5) +#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7) + +#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) +#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) +#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) +#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7) + +#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) + +#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) + +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3) +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4) +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6) +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7) + +#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) +#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) +#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6) +#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7) + +#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) +#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) +#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6) +#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7) + +#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) + +#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) + +#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) + +#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) + +#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) +#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) +#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) + +#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) +#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) + +#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) +#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) + +#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) +#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) + +#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) +#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) +#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7) + +#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) +#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7) + +#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) + +#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) + +#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) + +#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) + +#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) + +#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) + +#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) + +#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) + +#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) + +#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) +#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) + +#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) +#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3) +#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4) + +#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) +#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) +#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3) +#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4) + +#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) +#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) +#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3) +#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4) + +#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) +#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3) +#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4) + +#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) +#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2) +#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3) +#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) +#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7) + +#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) +#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2) +#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3) +#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) +#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7) + +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2) +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5) +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7) + +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2) +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3) +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5) +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6) +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7) + +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2) +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3) +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5) +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6) +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7) + +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6) +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7) + +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4) + +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4) + +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4) + +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4) + +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4) + +#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) +#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4) + +#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) +#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4) + +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4) + +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4) + +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4) + +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4) +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) + +#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1) +#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4) +#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5) + +#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1) +#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4) +#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5) + +#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1) +#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4) +#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5) + +#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1) +#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4) +#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5) + +#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) +#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6) +#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7) + +#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) +#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3) +#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4) +#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7) + +#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1) +#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5) +#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6) +#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7) + +#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1) +#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5) +#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6) +#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7) + +#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1) + +#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1) +#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) +#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5) +#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7) +#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9) + +#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1) +#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2) +#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5) +#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7) +#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9) + +#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1) +#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2) +#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5) +#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7) + +#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1) +#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2) +#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3) +#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5) +#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7) + +#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1) +#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2) +#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3) +#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5) +#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7) + +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2) +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4) +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7) +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11) + +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5) +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7) +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11) + +#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) +#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2) +#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7) + +#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) +#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) + +#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) +#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2) + +#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) +#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2) + +#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) + +#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) + +#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1) +#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2) +#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3) +#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4) +#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7) + +#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1) +#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2) +#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3) +#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4) +#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7) + +#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) +#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1) + +#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) +#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1) + +#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) + +#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) +#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1) + +#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) +#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1) + +#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9) + +#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9) +#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14) + +#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9) +#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14) + +#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9) +#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14) + +#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9) +#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14) + +#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9) +#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14) + +#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9) +#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14) + +#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9) + +#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9) + +#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9) + +#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9) + +#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9) + +#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) +#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7) + +#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) +#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) + +#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) +#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) +#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6) + +#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) +#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) +#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6) + +#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) +#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) +#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6) + +#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) +#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) +#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6) + +#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) +#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1) + +#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) +#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1) + +#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) +#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) + +#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) +#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) + +#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0) +#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) + +#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0) +#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) + +#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0) +#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) + +#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0) +#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1) +#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6) + +#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0) +#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1) +#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6) + +#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0) +#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) + +#endif /* __DTS_MT2701_PINFUNC_H */ diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi new file mode 100644 index 000000000000..ce6a4015fed5 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Erin.Lo + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "mt2701-pinfunc.h" + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mediatek,mt2701"; + interrupt-parent = <&cirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt81xx-tz-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + trustzone-bootinfo@80002000 { + compatible = "mediatek,trustzone-bootinfo"; + reg = <0 0x80002000 0 0x1000>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + rtc32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; + }; + + thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&thermal 0>; + sustainable-power = <1000>; + + trips { + threshold: trip-point@0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point@1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit@0 { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt2701-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2701-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2701-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + syscfg_pctl_a: syscfg@10005000 { + compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt2701-scpsys", "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "mm", "mfg", "ethif"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt2701-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt2701-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt2701-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + }; + + smi_common: smi@1000c000 { + compatible = "mediatek,mt2701-smi-common"; + reg = <0 0x1000c000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_SMI>, + <&mmsys CLK_MM_SMI_COMMON>, + <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi", "async"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt2701-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200100 0 0x1c>; + }; + + cirq: interrupt-controller@10204000 { + compatible = "mediatek,mt2701-cirq", + "mediatek,mtk-cirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&sysirq>; + reg = <0 0x10204000 0 0x400>; + mediatek,ext-irq-range = <32 200>; + }; + + iommu: mmsys_iommu@10205000 { + compatible = "mediatek,mt2701-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2>; + #iommu-cells = <1>; + }; + + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2701-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt2701-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt2701-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt2701-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt2701-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt2701-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt2701-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11007000 0 0x70>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt2701-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11008000 0 0x70>, + <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt2701-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11009000 0 0x70>, + <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt2701-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT2701_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + + nandc: nand-controller@1100d000 { + compatible = "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + status = "disabled"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + }; + + bch: ecc@1100e000 { + compatible = "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + + nor_flash: spi@11014000 { + compatible = "mediatek,mt2701-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; + clocks = <&pericfg CLK_PERI_FLASH>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11017000 { + compatible = "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI2_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + audsys: clock-controller@11220000 { + compatible = "mediatek,mt2701-audsys", "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + compatible = "mediatek,mt2701-audio"; + interrupts = , + ; + interrupt-names = "afe", "asys"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&audsys CLK_AUD_I2SO1>, + <&audsys CLK_AUD_I2SO2>, + <&audsys CLK_AUD_I2SO3>, + <&audsys CLK_AUD_I2SO4>, + <&audsys CLK_AUD_I2SIN1>, + <&audsys CLK_AUD_I2SIN2>, + <&audsys CLK_AUD_I2SIN3>, + <&audsys CLK_AUD_I2SIN4>, + <&audsys CLK_AUD_ASRCO1>, + <&audsys CLK_AUD_ASRCO2>, + <&audsys CLK_AUD_ASRCO3>, + <&audsys CLK_AUD_ASRCO4>, + <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_AFE_CONN>, + <&audsys CLK_AUD_A1SYS>, + <&audsys CLK_AUD_A2SYS>, + <&audsys CLK_AUD_AFE_MRGIF>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_a1sys_hp", + "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", + "i2s3_src_sel", + "i2s0_src_div", + "i2s1_src_div", + "i2s2_src_div", + "i2s3_src_div", + "i2s0_mclk_en", + "i2s1_mclk_en", + "i2s2_mclk_en", + "i2s3_mclk_en", + "i2so0_hop_ck", + "i2so1_hop_ck", + "i2so2_hop_ck", + "i2so3_hop_ck", + "i2si0_hop_ck", + "i2si1_hop_ck", + "i2si2_hop_ck", + "i2si3_hop_ck", + "asrc0_out_ck", + "asrc1_out_ck", + "asrc2_out_ck", + "asrc3_out_ck", + "audio_afe_pd", + "audio_afe_conn_pd", + "audio_a1sys_pd", + "audio_a2sys_pd", + "audio_mrgif_pd"; + + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>; + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt2701-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + bls: pwm@1400a000 { + compatible = "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + larb0: larb@14010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt2701-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + }; + + jpegdec: jpegdec@15004000 { + compatible = "mediatek,mt2701-jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; + + jpegenc: jpegenc@1500a000 { + compatible = "mediatek,mt2701-jpgenc", + "mediatek,mtk-jpgenc"; + reg = <0 0x1500a000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_VENC>; + clock-names = "jpgenc"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, + <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt2701-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; + }; + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt2701-hifsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb0: usb@1a1c0000 { + compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci"; + reg = <0 0x1a1c0000 0 0x1000>, + <0 0x1a1c4700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy0: t-phy@1a1c4000 { + compatible = "mediatek,mt2701-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a1c4000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb1: usb@1a240000 { + compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci"; + reg = <0 0x1a240000 0 0x1000>, + <0 0x1a244700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: t-phy@1a244000 { + compatible = "mediatek,mt2701-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a244000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb2: usb@11200000 { + compatible = "mediatek,mt2701-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + status = "disabled"; + }; + + u2phy0: t-phy@11210000 { + compatible = "mediatek,mt2701-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port2: usb-phy@1a1c4800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt2701-ethsys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt2701-eth", "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = , + , + ; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_ESW>, + <ðsys CLK_ETHSYS_GP1>, + <ðsys CLK_ETHSYS_GP2>, + <&apmixedsys CLK_APMIXED_TRGPLL>; + clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; + resets = <ðsys MT2701_ETHSYS_FE_RST>, + <ðsys MT2701_ETHSYS_GMAC_RST>, + <ðsys MT2701_ETHSYS_PPE_RST>; + reset-names = "fe", "gmac", "ppe"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + mediatek,ethsys = <ðsys>; + mediatek,pctl = <&syscfg_pctl_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bdpsys: syscon@1c000000 { + compatible = "mediatek,mt2701-bdpsys", "syscon"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi new file mode 100644 index 000000000000..7fda40ab5fe8 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6323.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: John Crispin + * Sean Wang + * + */ + +&pwrap { + pmic: mt6323 { + compatible = "mediatek,mt6323"; + interrupt-parent = <&pio>; + interrupts = <150 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + mt6323_leds: leds { + compatible = "mediatek,mt6323-led"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mt6323regulator: mt6323regulator{ + compatible = "mediatek,mt6323-regulator"; + + mt6323_vproc_reg: buck_vproc{ + regulator-name = "vproc"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vsys_reg: buck_vsys{ + regulator-name = "vsys"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <2987500>; + regulator-ramp-delay = <25000>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vpa_reg: buck_vpa{ + regulator-name = "vpa"; + regulator-min-microvolt = < 500000>; + regulator-max-microvolt = <3650000>; + }; + + mt6323_vtcxo_reg: ldo_vtcxo{ + regulator-name = "vtcxo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <90>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vcn28_reg: ldo_vcn28{ + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <185>; + }; + + mt6323_vcn33_bt_reg: ldo_vcn33_bt{ + regulator-name = "vcn33_bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <185>; + }; + + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ + regulator-name = "vcn33_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <185>; + }; + + mt6323_va_reg: ldo_va{ + regulator-name = "va"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <216>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vcama_reg: ldo_vcama{ + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vio28_reg: ldo_vio28{ + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <216>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vusb_reg: ldo_vusb{ + regulator-name = "vusb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <216>; + regulator-boot-on; + }; + + mt6323_vmc_reg: ldo_vmc{ + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + regulator-boot-on; + }; + + mt6323_vmch_reg: ldo_vmch{ + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + regulator-boot-on; + }; + + mt6323_vemc3v3_reg: ldo_vemc3v3{ + regulator-name = "vemc3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + regulator-boot-on; + }; + + mt6323_vgp1_reg: ldo_vgp1{ + regulator-name = "vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vgp2_reg: ldo_vgp2{ + regulator-name = "vgp2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vgp3_reg: ldo_vgp3{ + regulator-name = "vgp3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vcn18_reg: ldo_vcn18{ + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vsim1_reg: ldo_vsim1{ + regulator-name = "vsim1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vsim2_reg: ldo_vsim2{ + regulator-name = "vsim2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vrtc_reg: ldo_vrtc{ + regulator-name = "vrtc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vcamaf_reg: ldo_vcamaf{ + regulator-name = "vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vibr_reg: ldo_vibr{ + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + }; + + mt6323_vrf18_reg: ldo_vrf18{ + regulator-name = "vrf18"; + regulator-min-microvolt = <1825000>; + regulator-max-microvolt = <1825000>; + regulator-enable-ramp-delay = <187>; + }; + + mt6323_vm_reg: ldo_vm{ + regulator-name = "vm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vio18_reg: ldo_vio18{ + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + regulator-always-on; + regulator-boot-on; + }; + + mt6323_vcamd_reg: ldo_vcamd{ + regulator-name = "vcamd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vcamio_reg: ldo_vcamio{ + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + }; + + mt6323keys: mt6323keys { + compatible = "mediatek,mt6323-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power { + linux,keycodes = <116>; + wakeup-source; + }; + + home { + linux,keycodes = <114>; + }; + }; + + codec: mt6397codec { + compatible = "mediatek,mt6397-codec"; + }; + + power-controller { + compatible = "mediatek,mt6323-pwrc"; + }; + + rtc { + compatible = "mediatek,mt6323-rtc"; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6580-evbp1.dts b/arch/arm/boot/dts/mediatek/mt6580-evbp1.dts new file mode 100644 index 000000000000..755a0774a8ee --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6580-evbp1.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C + * + */ + +/dts-v1/; +#include "mt6580.dtsi" + +/ { + model = "MediaTek MT6580 evaluation board"; + compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6580.dtsi b/arch/arm/boot/dts/mediatek/mt6580.dtsi new file mode 100644 index 000000000000..9e17698c0609 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6580.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C + * + */ + +#include +#include + +/ { + compatible = "mediatek,mt6580"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt6580-timer", + "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6580-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11005000 { + compatible = "mediatek,mt6580-uart", + "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11006000 { + compatible = "mediatek,mt6580-uart", + "mediatek,mt6577-uart"; + reg = <0x11006000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts b/arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts new file mode 100644 index 000000000000..b057e037f940 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Maxim Kutnij + */ + +/dts-v1/; +#include "mt6582.dtsi" + +/ { + model = "Prestigio PMT5008 3G"; + compatible = "prestigio,pmt5008-3g", "mediatek,mt6582"; + + aliases { + bootargs = "console=ttyS0,921600n8 earlyprintk"; + serial0 = &uart0; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6582.dtsi b/arch/arm/boot/dts/mediatek/mt6582.dtsi new file mode 100644 index 000000000000..4263371784cd --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6582.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Maxim Kutnij + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt6582"; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer@11008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6582-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6582-wdt", + "mediatek,mt6589-wdt"; + reg = <0x10007000 0x100>; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts b/arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts new file mode 100644 index 000000000000..1e7079a3b449 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Matthias Brugger + * + */ + +/dts-v1/; +#include "mt6589.dtsi" + +/ { + model = "bq Aquaris5"; + compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; + + chosen { + bootargs = "console=ttyS0,921600n8 earlyprintk"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + +}; + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts new file mode 100644 index 000000000000..c952347981de --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Luca Weiss + */ + +/dts-v1/; +#include "mt6589.dtsi" + +/ { + model = "Fairphone 1"; + compatible = "fairphone,fp1", "mediatek,mt6589"; + + chosen { + stdout-path = &uart3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&cpus { + /* SMP is not stable on this board, makes the kernel panic */ + /delete-property/ enable-method; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi new file mode 100644 index 000000000000..c6babc8ad2ba --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Matthias Brugger + * +*/ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt6589"; + interrupt-parent = <&sysirq>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + timer: timer@10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6589-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11006000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11006000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11007000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11007000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11008000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11008000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11009000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11009000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + wdt: watchdog@10000000 { + compatible = "mediatek,mt6589-wdt"; + reg = <0x10000000 0x44>; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6592-evb.dts b/arch/arm/boot/dts/mediatek/mt6592-evb.dts new file mode 100644 index 000000000000..5e00c1cca2d1 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6592-evb.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Howard Chen + * + */ + +/dts-v1/; +#include "mt6592.dtsi" + +/ { + model = "mt6592 evb"; + compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6592.dtsi b/arch/arm/boot/dts/mediatek/mt6592.dtsi new file mode 100644 index 000000000000..3716f8db951c --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6592.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Howard Chen + * + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt6592"; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x4>; + }; + cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x5>; + }; + cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x6>; + }; + cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x7>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200220 { + compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200220 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi new file mode 100644 index 000000000000..f0b4a09004b3 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -0,0 +1,1313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: John Crispin + * Sean Wang + * Ryder Lee + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7623"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-98000000 { + opp-hz = /bits/ 64 <98000000>; + opp-microvolt = <1050000>; + }; + + opp-198000000 { + opp-hz = /bits/ 64 <198000000>; + opp-microvolt = <1050000>; + }; + + opp-398000000 { + opp-hz = /bits/ 64 <398000000>; + opp-microvolt = <1050000>; + }; + + opp-598000000 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <1050000>; + }; + + opp-747500000 { + opp-hz = /bits/ 64 <747500000>; + opp-microvolt = <1050000>; + }; + + opp-1040000000 { + opp-hz = /bits/ 64 <1040000000>; + opp-microvolt = <1150000>; + }; + + opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1200000>; + }; + + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1300000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + clock-frequency = <1300000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + clock-frequency = <1300000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + clock-frequency = <1300000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + clock-frequency = <1300000000>; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc32k: oscillator-1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; + }; + + clk26m: oscillator-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = <&thermal 0>; + + trips { + cpu_passive: cpu-passive { + temperature = <57000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_active: cpu-active { + temperature = <67000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu-hot { + temperature = <87000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu-crit { + temperature = <107000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_active>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt7623-topckgen", + "mediatek,mt2701-topckgen", + "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt7623-infracfg", + "mediatek,mt2701-infracfg", + "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt7623-pericfg", + "mediatek,mt2701-pericfg", + "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt7623-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + interrupts = , + ; + }; + + syscfg_pctl_a: syscfg@10005000 { + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt7623-scpsys", + "mediatek,mt2701-scpsys", + "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "mm", "mfg", "ethif"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt7623-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt7623-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc32k>; + clock-names = "system-clk", "rtc-clk"; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt7623-pwrap", + "mediatek,mt2701-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; + reset-names = "pwrap"; + clocks = <&infracfg CLK_INFRA_PMICSPI>, + <&infracfg CLK_INFRA_PMICWRAP>; + clock-names = "spi", "wrap"; + }; + + cir: cir@10013000 { + compatible = "mediatek,mt7623-cir"; + reg = <0 0x10013000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IRRX>; + clock-names = "clk"; + status = "disabled"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt7623-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200100 0 0x1c>; + }; + + efuse: efuse@10206000 { + compatible = "mediatek,mt7623-efuse", + "mediatek,mt8173-efuse"; + reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration_data: calib@424 { + reg = <0x424 0xc>; + }; + }; + + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt7623-apmixedsys", + "mediatek,mt2701-apmixedsys", + "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt7623-auxadc", + "mediatek,mt2701-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7623-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART0_SEL>, + <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7623-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART1_SEL>, + <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7623-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART2_SEL>, + <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt7623-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART3_SEL>, + <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt7623-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>; + clock-names = "top", "main", "pwm1", "pwm2", + "pwm3", "pwm4", "pwm5"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt7623-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11007000 0 0x70>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt7623-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11008000 0 0x70>, + <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt7623-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11009000 0 0x70>, + <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7623-thermal", + "mediatek,mt2701-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT2701_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration_data>; + nvmem-cell-names = "calibration-data"; + }; + + btif: serial@1100c000 { + compatible = "mediatek,mt7623-btif", + "mediatek,mtk-btif"; + reg = <0 0x1100c000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_BTIF>; + clock-names = "main"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + nandc: nfi@1100d000 { + compatible = "mediatek,mt7623-nfc", + "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + status = "disabled"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + }; + + bch: ecc@1100e000 { + compatible = "mediatek,mt7623-ecc", + "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + + nor_flash: spi@11014000 { + compatible = "mediatek,mt7623-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0x1000>; + clocks = <&pericfg CLK_PERI_FLASH>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11017000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI2_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + usb0: usb@11200000 { + compatible = "mediatek,mt7623-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + status = "disabled"; + }; + + u2phy1: t-phy@11210000 { + compatible = "mediatek,mt7623-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port2: usb-phy@11210800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7623-audsys", + "mediatek,mt2701-audsys", + "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + compatible = "mediatek,mt7623-audio", + "mediatek,mt2701-audio"; + interrupts = , + ; + interrupt-names = "afe", "asys"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&audsys CLK_AUD_I2SO1>, + <&audsys CLK_AUD_I2SO2>, + <&audsys CLK_AUD_I2SO3>, + <&audsys CLK_AUD_I2SO4>, + <&audsys CLK_AUD_I2SIN1>, + <&audsys CLK_AUD_I2SIN2>, + <&audsys CLK_AUD_I2SIN3>, + <&audsys CLK_AUD_I2SIN4>, + <&audsys CLK_AUD_ASRCO1>, + <&audsys CLK_AUD_ASRCO2>, + <&audsys CLK_AUD_ASRCO3>, + <&audsys CLK_AUD_ASRCO4>, + <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_AFE_CONN>, + <&audsys CLK_AUD_A1SYS>, + <&audsys CLK_AUD_A2SYS>, + <&audsys CLK_AUD_AFE_MRGIF>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_a1sys_hp", + "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", + "i2s3_src_sel", + "i2s0_src_div", + "i2s1_src_div", + "i2s2_src_div", + "i2s3_src_div", + "i2s0_mclk_en", + "i2s1_mclk_en", + "i2s2_mclk_en", + "i2s3_mclk_en", + "i2so0_hop_ck", + "i2so1_hop_ck", + "i2so2_hop_ck", + "i2so3_hop_ck", + "i2si0_hop_ck", + "i2si1_hop_ck", + "i2si2_hop_ck", + "i2si3_hop_ck", + "asrc0_out_ck", + "asrc1_out_ck", + "asrc2_out_ck", + "asrc3_out_ck", + "audio_afe_pd", + "audio_afe_conn_pd", + "audio_a1sys_pd", + "audio_a2sys_pd", + "audio_mrgif_pd"; + + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>; + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7623-mmc", + "mediatek,mt2701-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC30_0_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt7623-mmc", + "mediatek,mt2701-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_MSDC30_1_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt7623-vdecsys", + "mediatek,mt2701-vdecsys", + "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "mediatek,mt2701-hifsys", + "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + }; + + pcie0_phy: t-phy@1a149000 { + compatible = "mediatek,mt7623-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a149000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0 0x1a149900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: t-phy@1a14a000 { + compatible = "mediatek,mt7623-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a14a000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0 0x1a14a900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x1a1c0000 0 0x1000>, + <0 0x1a1c4700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: t-phy@1a1c4000 { + compatible = "mediatek,mt7623-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a1c4000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb2: usb@1a240000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x1a240000 0 0x1000>, + <0 0x1a244700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy2: t-phy@1a244000 { + compatible = "mediatek,mt7623-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a244000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7623-ethsys", + "mediatek,mt2701-ethsys", + "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + hsdma: dma-controller@1b007000 { + compatible = "mediatek,mt7623-hsdma"; + reg = <0 0x1b007000 0 0x1000>; + interrupts = ; + clocks = <ðsys CLK_ETHSYS_HSDMA>; + clock-names = "hsdma"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + #dma-cells = <1>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt7623-eth", + "mediatek,mt2701-eth", + "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = , + , + ; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_ESW>, + <ðsys CLK_ETHSYS_GP1>, + <ðsys CLK_ETHSYS_GP2>, + <&apmixedsys CLK_APMIXED_TRGPLL>; + clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; + resets = <ðsys MT2701_ETHSYS_FE_RST>, + <ðsys MT2701_ETHSYS_GMAC_RST>, + <ðsys MT2701_ETHSYS_PPE_RST>; + reset-names = "fe", "gmac", "ppe"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + mediatek,ethsys = <ðsys>; + mediatek,pctl = <&syscfg_pctl_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + status = "disabled"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; + }; + + crypto: crypto@1b240000 { + compatible = "mediatek,eip97-crypto"; + reg = <0 0x1b240000 0 0x20000>; + interrupts = , + , + , + , + ; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; + clock-names = "cryp"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + status = "disabled"; + }; + + bdpsys: syscon@1c000000 { + compatible = "mediatek,mt7623-bdpsys", + "mediatek,mt2701-bdpsys", + "syscon"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; +}; + +&pio { + cir_pins_a:cir-default { + pins-cir { + pinmux = ; + bias-disable; + }; + }; + + i2c0_pins_a: i2c0-default { + pins-i2c0 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1-default { + pin-i2c1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c1_pins_b: i2c1-alt { + pin-i2c1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins_a: i2c2-default { + pin-i2c2 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins_b: i2c2-alt { + pin-i2c2 { + pinmux = , + ; + bias-disable; + }; + }; + + i2s0_pins_a: i2s0-default { + pin-i2s0 { + pinmux = , + , + , + , + ; + drive-strength = ; + bias-pull-down; + }; + }; + + i2s1_pins_a: i2s1-default { + pin-i2s1 { + pinmux = , + , + , + , + ; + drive-strength = ; + bias-pull-down; + }; + }; + + key_pins_a: keys-alt { + pins-keys { + pinmux = , + ; + input-enable; + }; + }; + + led_pins_a: leds-alt { + pins-leds { + pinmux = , + , + ; + }; + }; + + mmc0_pins_default: mmc0default { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + bias-pull-down; + }; + + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + bias-pull-down; + drive-strength = ; + }; + + pins-wp { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + + nand_pins_default: nanddefault { + pins-ale { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up; + }; + + pins-we { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + pcie_default: pcie_pin_default { + pins_cmd_dat { + pinmux = , + ; + bias-disable; + }; + }; + + pwm_pins_a: pwm-default { + pins-pwm { + pinmux = , + , + , + , + ; + }; + }; + + spi0_pins_a: spi0-default { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins_a: spi1-default { + pins-spi { + pinmux = , + , + , + ; + }; + }; + + spi2_pins_a: spi2-default { + pins-spi { + pinmux = , + , + , + ; + }; + }; + + uart0_pins_a: uart0-default { + pins-dat { + pinmux = , + ; + }; + }; + + uart1_pins_a: uart1-default { + pins-dat { + pinmux = , + ; + }; + }; + + uart2_pins_a: uart2-default { + pins-dat { + pinmux = , + ; + }; + }; + + uart2_pins_b: uart2-alt { + pins-dat { + pinmux = , + ; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts new file mode 100644 index 000000000000..5654284bab01 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: Sean Wang + * + */ + +/dts-v1/; +#include +#include "mt7623a.dtsi" +#include "mt6323.dtsi" + +/ { + model = "MediaTek MT7623A with eMMC reference board"; + compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@1 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@2 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@3 { + proc-supply = <&mt6323_vproc_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + button-factory { + label = "factory"; + linux,code = ; + gpios = <&pio 256 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 257 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "mediatek,mt2701-wm8960-machine"; + mediatek,platform = <&afe>; + audio-routing = + "Headphone", "HP_L", + "Headphone", "HP_R", + "LINPUT1", "AMIC", + "RINPUT1", "AMIC"; + mediatek,audio-codec = <&wm8960>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins_a>; + }; +}; + +&btif { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan0"; + }; + + port@1 { + status = "okay"; + label = "lan1"; + }; + + port@2 { + status = "okay"; + label = "lan2"; + }; + + port@3 { + status = "okay"; + label = "lan3"; + }; + + port@4 { + status = "okay"; + label = "wan"; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_b>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins_a>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_b>; + status = "okay"; +}; + +&usb1 { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts new file mode 100644 index 000000000000..afd177b3b516 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: Sean Wang + * + */ + +/dts-v1/; +#include +#include "mt7623a.dtsi" +#include "mt6323.dtsi" + +/ { + model = "MediaTek MT7623A with NAND reference board"; + compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@1 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@2 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@3 { + proc-supply = <&mt6323_vproc_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + button-factory { + label = "factory"; + linux,code = ; + gpios = <&pio 256 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 257 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "mediatek,mt2701-wm8960-machine"; + mediatek,platform = <&afe>; + audio-routing = + "Headphone", "HP_L", + "Headphone", "HP_R", + "LINPUT1", "AMIC", + "RINPUT1", "AMIC"; + mediatek,audio-codec = <&wm8960>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins_a>; + }; +}; + +&bch { + status = "okay"; +}; + +&btif { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan0"; + }; + + port@1 { + status = "okay"; + label = "lan1"; + }; + + port@2 { + status = "okay"; + label = "lan2"; + }; + + port@3 { + status = "okay"; + label = "lan3"; + }; + + port@4 { + status = "okay"; + label = "wan"; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_b>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&nandc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_default>; + status = "okay"; + + nand@0 { + reg = <0>; + spare_per_sector = <64>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <12>; + nand-ecc-step-size = <1024>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "preloader"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "uboot"; + reg = <0x40000 0x80000>; + }; + + partition@c0000 { + label = "uboot-env"; + reg = <0xC0000 0x40000>; + }; + + partition@140000 { + label = "bootimg"; + reg = <0x140000 0x2000000>; + }; + + partition@2140000 { + label = "recovery"; + reg = <0x2140000 0x2000000>; + }; + + partition@4140000 { + label = "rootfs"; + reg = <0x4140000 0x1000000>; + }; + + partition@5140000 { + label = "usrdata"; + reg = <0x5140000 0x1000000>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins_a>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_b>; + status = "okay"; +}; + +&usb1 { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623a.dtsi b/arch/arm/boot/dts/mediatek/mt7623a.dtsi new file mode 100644 index 000000000000..bcf909d58a1c --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623a.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: Sean Wang + * + */ + +/dts-v1/; +#include +#include "mt7623.dtsi" + +&afe { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +}; + +&crypto { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +ð { + status = "okay"; + power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@1f { + compatible = "mediatek,mt7530"; + reg = <0x1f>; + mediatek,mcm; + resets = <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names = "mcm"; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + status = "disabled"; + reg = <0>; + label = "swp0"; + }; + + port@1 { + status = "disabled"; + reg = <1>; + label = "swp1"; + }; + + port@2 { + status = "disabled"; + reg = <2>; + label = "swp2"; + }; + + port@3 { + status = "disabled"; + reg = <3>; + label = "swp3"; + }; + + port@4 { + status = "disabled"; + reg = <4>; + label = "swp4"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&nandc { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +}; + +&pcie { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +}; + +&scpsys { + compatible = "mediatek,mt7623a-scpsys"; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "ethif"; +}; + +&usb0 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +}; + +&usb1 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +}; + +&usb2 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts new file mode 100644 index 000000000000..a37f3fa223c7 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts @@ -0,0 +1,471 @@ +/* + * Copyright 2017-2018 Sean Wang + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include "mt7623n.dtsi" +#include "mt6323.dtsi" + +/ { + model = "Bananapi BPI-R2"; + compatible = "bananapi,bpi-r2", "mediatek,mt7623"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@1 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@2 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@3 { + proc-supply = <&mt6323_vproc_reg>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vgpu: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed_vgpu"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + button-factory { + label = "factory"; + linux,code = ; + gpios = <&pio 256 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 257 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a>; + + blue { + label = "bpi-r2:pio:blue"; + gpios = <&pio 240 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + green { + label = "bpi-r2:pio:green"; + gpios = <&pio 241 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + red { + label = "bpi-r2:pio:red"; + gpios = <&pio 239 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x80000000>; + }; +}; + +&bls { + status = "okay"; +}; + +&btif { + status = "okay"; +}; + +&cec { + status = "okay"; +}; + +&cir { + pinctrl-names = "default"; + pinctrl-0 = <&cir_pins_a>; + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +ð { + status = "okay"; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7530"; + reg = <0x1f>; + reset-gpios = <&pio 33 0>; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan0"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&mali { + mali-supply = <®_vgpu>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&mt6323keys { + home { + status = "disabled"; + }; +}; + +&mt6323_leds { + status = "okay"; + + led@0 { + reg = <0>; + label = "bpi-r2:isink:green"; + default-state = "off"; + }; + + led@1 { + reg = <1>; + label = "bpi-r2:isink:red"; + default-state = "off"; + }; + + led@2 { + reg = <2>; + label = "bpi-r2:isink:blue"; + default-state = "off"; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pio { + musb_pins: musb { + pins-musb { + pinmux = ; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins_a>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&musb_pins>; + status = "okay"; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + }; +}; + +&usb1 { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usb2 { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts new file mode 100644 index 000000000000..34994f3f5a4b --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: Sean Wang + * + */ + +/dts-v1/; +#include +#include "mt7623n.dtsi" +#include "mt6323.dtsi" + +/ { + model = "MediaTek MT7623N with eMMC reference board"; + compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@1 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@2 { + proc-supply = <&mt6323_vproc_reg>; + }; + + cpu@3 { + proc-supply = <&mt6323_vproc_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + button-factory { + label = "factory"; + linux,code = ; + gpios = <&pio 256 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 257 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "mediatek,mt2701-wm8960-machine"; + mediatek,platform = <&afe>; + audio-routing = + "Headphone", "HP_L", + "Headphone", "HP_R", + "LINPUT1", "AMIC", + "RINPUT1", "AMIC"; + mediatek,audio-codec = <&wm8960>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins_a>; + }; +}; + +&bls { + status = "okay"; +}; + +&btif { + status = "okay"; +}; + +&cec { + status = "okay"; +}; + +&cir { + pinctrl-names = "default"; + pinctrl-0 = <&cir_pins_a>; + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy5>; +}; + +ð { + status = "okay"; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii-rxid"; + }; + + switch@1f { + compatible = "mediatek,mt7530"; + reg = <0x1f>; + reset-gpios = <&pio 33 0>; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins_a>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; + +&usb1 { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7623n.dtsi b/arch/arm/boot/dts/mediatek/mt7623n.dtsi new file mode 100644 index 000000000000..3adab5cd1fef --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623n.dtsi @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2017-2020 MediaTek Inc. + * Author: Sean Wang + * Ryder Lee + * + */ + +#include "mt7623.dtsi" +#include + +/ { + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + + g3dsys: syscon@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt7623-mmsys", + "mediatek,mt2701-mmsys", + "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb0: larb@14010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt7623-imgsys", + "mediatek,mt2701-imgsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + iommu: mmsys_iommu@10205000 { + compatible = "mediatek,mt7623-m4u", + "mediatek,mt2701-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2>; + #iommu-cells = <1>; + }; + + jpegdec: jpegdec@15004000 { + compatible = "mediatek,mt7623-jpgdec", + "mediatek,mt2701-jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; + + smi_common: smi@1000c000 { + compatible = "mediatek,mt7623-smi-common", + "mediatek,mt2701-smi-common"; + reg = <0 0x1000c000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_SMI>, + <&mmsys CLK_MM_SMI_COMMON>, + <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi", "async"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + ovl: ovl@14007000 { + compatible = "mediatek,mt7623-disp-ovl", + "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + }; + + wdma@14009000 { + compatible = "mediatek,mt7623-disp-wdma", + "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + }; + + bls: pwm@1400a000 { + compatible = "mediatek,mt7623-disp-pwm", + "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, + <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + color: color@1400b000 { + compatible = "mediatek,mt7623-disp-color", + "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi: dsi@1400c000 { + compatible = "mediatek,mt7623-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt7623-disp-mutex", + "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + + rdma1: rdma@14012000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + }; + + dpi0: dpi@14014000 { + compatible = "mediatek,mt7623-dpi", + "mediatek,mt2701-dpi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI1_DIGL>, + <&mmsys CLK_MM_DPI1_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + + hdmi0: hdmi@14015000 { + compatible = "mediatek,mt7623-hdmi", + "mediatek,mt2701-hdmi"; + reg = <0 0x14015000 0 0x400>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLL>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + cec = <&cec>; + status = "disabled"; + }; + + mipi_tx0: dsi-phy@10010000 { + compatible = "mediatek,mt7623-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + cec: cec@10012000 { + compatible = "mediatek,mt7623-cec", + "mediatek,mt8173-cec"; + reg = <0 0x10012000 0 0xbc>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + + hdmi_phy: hdmi-phy@10209100 { + compatible = "mediatek,mt7623-hdmi-phy", + "mediatek,mt2701-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdmiddc0: i2c@11013000 { + compatible = "mediatek,mt7623-hdmi-ddc", + "mediatek,mt8173-hdmi-ddc"; + interrupts = ; + reg = <0 0x11013000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C3>; + clock-names = "ddc-i2c"; + status = "disabled"; + }; +}; + +&pio { + hdmi_pins_a: hdmi-default { + pins-hdmi { + pinmux = ; + input-enable; + bias-pull-down; + }; + }; + + hdmi_ddc_pins_a: hdmi_ddc-default { + pins-hdmi-ddc { + pinmux = , + ; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts new file mode 100644 index 000000000000..84e14bee7235 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Ryder Lee + */ + +/dts-v1/; +#include +#include "mt7629.dtsi" + +/ { + model = "MediaTek MT7629 reference board"; + compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "factory"; + linux,code = ; + gpios = <&pio 60 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 58 GPIO_ACTIVE_LOW>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + pinctrl-1 = <&ephy_leds_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000 0x60000>; + read-only; + }; + + partition@60000 { + label = "u-boot-env"; + reg = <0x60000 0x10000>; + read-only; + }; + + factory: partition@70000 { + label = "factory"; + reg = <0x70000 0x40000>; + read-only; + }; + + partition@b0000 { + label = "kernel"; + reg = <0xb0000 0xb50000>; + }; + }; + }; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pciephy1 { + status = "okay"; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + ephy_leds_pins: ephy-leds-pins { + mux { + function = "led"; + groups = "gphy_leds_0", "ephy_leds"; + }; + }; + + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c_0"; + }; + + conf { + pins = "I2C_SDA", "I2C_SCL"; + drive-strength = <4>; + bias-disable; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clkreq", + "pcie_pereset", + "pcie_wake"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm_0"; + }; + }; + + /* SPI-NOR is shared pin with serial NAND */ + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spi_pins: spi-pins { + mux { + function = "spi"; + groups = "spi_0"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_txd_rxd" ; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_0_tx_rx" ; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_0_txd_rxd" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt7629.dtsi b/arch/arm/boot/dts/mediatek/mt7629.dtsi new file mode 100644 index 000000000000..acab0883a3bb --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7629.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7629"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1250000000>; + cci-control-port = <&cci_control2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1250000000>; + cci-control-port = <&cci_control2>; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + clk20m: oscillator-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "clk20m"; + }; + + clk40m: oscillator-1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <20000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + infracfg: syscon@10000000 { + compatible = "mediatek,mt7629-infracfg", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10002000 { + compatible = "mediatek,mt7629-pericfg", "syscon"; + reg = <0x10002000 0x1000>; + #clock-cells = <1>; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt7629-scpsys", + "mediatek,mt7622-scpsys"; + #power-domain-cells = <1>; + reg = <0x10006000 0x1000>; + clocks = <&topckgen CLK_TOP_HIF_SEL>; + clock-names = "hif_sel"; + assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; + infracfg = <&infracfg>; + }; + + timer: timer@10009000 { + compatible = "mediatek,mt7629-timer", + "mediatek,mt6765-timer"; + reg = <0x10009000 0x60>; + interrupts = ; + clocks = <&clk20m>; + clock-names = "clk20m"; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt7629-sysirq", + "mediatek,mt6577-sysirq"; + reg = <0x10200a80 0x20>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt7629-apmixedsys", "syscon"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt7629-rng", + "mediatek,mt7623-rng"; + reg = <0x1020f000 0x100>; + clocks = <&infracfg CLK_INFRA_TRNG_PD>; + clock-names = "rng"; + }; + + topckgen: syscon@10210000 { + compatible = "mediatek,mt7629-topckgen", "syscon"; + reg = <0x10210000 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@10212000 { + compatible = "mediatek,mt7629-wdt", + "mediatek,mt6589-wdt"; + reg = <0x10212000 0x100>; + }; + + pio: pinctrl@10217000 { + compatible = "mediatek,mt7629-pinctrl"; + reg = <0x10217000 0x8000>, + <0x10005000 0x1000>; + reg-names = "base", "eint"; + gpio-controller; + gpio-ranges = <&pio 0 0 79>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10310000 0x1000>, + <0x10320000 0x1000>, + <0x10340000 0x2000>, + <0x10360000 0x2000>; + }; + + cci: cci@10390000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10390000 0x1000>; + ranges = <0 0x10390000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + ; + }; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7629-uart", + "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7629-uart", + "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7629-uart", + "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt7629-pwm"; + reg = <0x11006000 0x1000>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>; + clock-names = "top", "main", "pwm1"; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_UNIVPLL2_D4>; + status = "disabled"; + }; + + i2c: i2c@11007000 { + compatible = "mediatek,mt7629-i2c", + "mediatek,mt2712-i2c"; + reg = <0x11007000 0x90>, + <0x11000100 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C0_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt7629-spi", + "mediatek,mt7622-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1100a000 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0_PD>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + qspi: spi@11014000 { + compatible = "mediatek,mt7629-nor", + "mediatek,mt8173-nor"; + reg = <0x11014000 0xe0>; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssusbsys: syscon@1a000000 { + compatible = "mediatek,mt7629-ssusbsys", "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ssusb: usb@1a0c0000 { + compatible = "mediatek,mt7629-xhci", + "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x01000>, + <0x1a0c3e00 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, + <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, + <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, + <&topckgen CLK_TOP_SATA_SEL>, + <&topckgen CLK_TOP_HIF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, + <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_UNIVPLL1_D2>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy0: t-phy@1a0c4000 { + compatible = "mediatek,mt7629-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1a0c4000 0xe00>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0 0x700>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&clk20m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pciesys: syscon@1a100800 { + compatible = "mediatek,mt7629-pciesys", "syscon"; + reg = <0x1a100800 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pciecfg: pciecfg@1a140000 { + compatible = "mediatek,generic-pciecfg", "syscon"; + reg = <0x1a140000 0x1000>; + }; + + pcie1: pcie@1a145000 { + compatible = "mediatek,mt7629-pcie"; + device_type = "pci"; + reg = <0x1a145000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P1_AUX_EN>, + <&pciesys CLK_PCIE_P1_AXI_EN>, + <&pciesys CLK_PCIE_P1_OBFF_EN>, + <&pciesys CLK_PCIE_P1_PIPE_EN>; + clock-names = "sys_ck1", "ahb_ck1", + "aux_ck1", "axi_ck1", + "obff_ck1", "pipe_ck1"; + assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>, + <&topckgen CLK_TOP_AXI_SEL>, + <&topckgen CLK_TOP_HIF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SYSPLL1_D2>, + <&topckgen CLK_TOP_UNIVPLL1_D2>; + phys = <&pcieport1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy1"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pciephy1: t-phy@1a14a000 { + compatible = "mediatek,mt7629-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1a14a000 0x1000>; + status = "disabled"; + + pcieport1: pcie-phy@0 { + reg = <0 0x1000>; + clocks = <&clk20m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7629-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt7629-eth","syscon"; + reg = <0x1b100000 0x20000>; + interrupts = , + , + ; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&topckgen CLK_TOP_F10M_REF_SEL>, + <ðsys CLK_ETH_ESW_EN>, + <ðsys CLK_ETH_GP0_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_FE_EN>, + <&sgmiisys0 CLK_SGMII_TX_EN>, + <&sgmiisys0 CLK_SGMII_RX_EN>, + <&sgmiisys0 CLK_SGMII_CDR_REF>, + <&sgmiisys0 CLK_SGMII_CDR_FB>, + <&sgmiisys1 CLK_SGMII_TX_EN>, + <&sgmiisys1 CLK_SGMII_RX_EN>, + <&sgmiisys1 CLK_SGMII_CDR_REF>, + <&sgmiisys1 CLK_SGMII_CDR_FB>, + <&apmixedsys CLK_APMIXED_SGMIPLL>, + <&apmixedsys CLK_APMIXED_ETH2PLL>; + clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", + "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "sgmii_ck", "eth2pll"; + assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&topckgen CLK_TOP_F10M_REF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, + <&topckgen CLK_TOP_SGMIIPLL_D2>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys0: syscon@1b128000 { + compatible = "mediatek,mt7629-sgmiisys", "syscon"; + reg = <0x1b128000 0x3000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@1b130000 { + compatible = "mediatek,mt7629-sgmiisys", "syscon"; + reg = <0x1b130000 0x3000>; + #clock-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt8127-moose.dts b/arch/arm/boot/dts/mediatek/mt8127-moose.dts new file mode 100644 index 000000000000..560687af87dc --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt8127-moose.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C + * + */ + +/dts-v1/; +#include "mt8127.dtsi" + +/ { + model = "MediaTek MT8127 Moose Board"; + compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt8127.dtsi b/arch/arm/boot/dts/mediatek/mt8127.dtsi new file mode 100644 index 000000000000..aced173c2a52 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt8127.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C + * + */ + +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mediatek,mt8127"; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt81xx-tz-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + trustzone-bootinfo@80002000 { + compatible = "mediatek,trustzone-bootinfo"; + reg = <0 0x80002000 0 0x1000>; + }; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + timer: timer@10008000 { + compatible = "mediatek,mt8127-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt8127-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200100 0 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt8135-evbp1.dts b/arch/arm/boot/dts/mediatek/mt8135-evbp1.dts new file mode 100644 index 000000000000..f6147fe62f41 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt8135-evbp1.dts @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C + * + */ + +/dts-v1/; +#include "mt8135.dtsi" + +/ { + model = "MediaTek MT8135 evaluation board"; + compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; +}; + +&pwrap { + pmic: mt6397 { + compatible = "mediatek,mt6397"; + + mt6397regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-name = "vpca15"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-name = "vpca7"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-name = "vsramca15"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-name = "vsramca7"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-name = "vcore"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-name = "va28"; + regulator-always-on; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-name = "vcamd"; + regulator-min-microvolt = <1220000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-name = "vcamio"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-name = "vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-name = "vgp6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt8135.dtsi b/arch/arm/boot/dts/mediatek/mt8135.dtsi new file mode 100644 index 000000000000..0f291ad22d3a --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt8135.dtsi @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C + * + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mediatek,mt8135"; + interrupt-parent = <&sysirq>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt81xx-tz-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x001>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + trustzone-bootinfo@80002000 { + compatible = "mediatek,trustzone-bootinfo"; + reg = <0 0x80002000 0 0x1000>; + }; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + clk26m: clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8135-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + #reset-cells = <1>; + #clock-cells = <1>; + compatible = "mediatek,mt8135-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + }; + + pericfg: pericfg@10003000 { + #reset-cells = <1>; + #clock-cells = <1>; + compatible = "mediatek,mt8135-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + }; + + /* + * Pinctrl access register at 0x10005000 and 0x1020c000 through + * regmap. Register 0x1000b000 is used by EINT. + */ + pio: pinctrl@10005000 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + ; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt8135-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + }; + + sysirq: interrupt-controller@10200030 { + compatible = "mediatek,mt8135-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200030 0 0x1c>; + }; + + apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt8135-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl_b: syscfg_pctl_b@1020c000 { + compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; + reg = <0 0x1020c000 0 0x1000>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x2000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + + uart0: serial@11006000 { + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; + reg = <0 0x11006000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11007000 { + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; + reg = <0 0x11007000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11008000 { + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; + reg = <0 0x11008000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11009000 { + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; + reg = <0 0x11009000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + }; +}; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi deleted file mode 100644 index 8e3860d5d916..000000000000 --- a/arch/arm/boot/dts/meson.dtsi +++ /dev/null @@ -1,334 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - cbus: cbus@c1100000 { - compatible = "simple-bus"; - reg = <0xc1100000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc1100000 0x200000>; - - hhi: system-controller@4000 { - compatible = "amlogic,meson-hhi-sysctrl", - "simple-mfd", - "syscon"; - reg = <0x4000 0x400>; - }; - - aiu: audio-controller@5400 { - compatible = "amlogic,aiu"; - #sound-dai-cells = <2>; - sound-name-prefix = "AIU"; - reg = <0x5400 0x2ac>; - interrupts = , - ; - interrupt-names = "i2s", "spdif"; - status = "disabled"; - }; - - assist: assist@7c00 { - compatible = "amlogic,meson-mx-assist", "syscon"; - reg = <0x7c00 0x200>; - }; - - hwrng: rng@8100 { - compatible = "amlogic,meson-rng"; - reg = <0x8100 0x8>; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson6-uart"; - reg = <0x84c0 0x18>; - interrupts = ; - fifo-size = <128>; - status = "disabled"; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson6-uart"; - reg = <0x84dc 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson6-i2c"; - reg = <0x8500 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-pwm"; - reg = <0x8550 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-pwm"; - reg = <0x8650 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: adc@8680 { - compatible = "amlogic,meson-saradc"; - reg = <0x8680 0x34>; - #io-channel-cells = <1>; - interrupts = ; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson6-uart"; - reg = <0x8700 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson6-i2c"; - reg = <0x87c0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb0_phy: phy@8800 { - compatible = "amlogic,meson-mx-usb2-phy"; - #phy-cells = <0>; - reg = <0x8800 0x20>; - status = "disabled"; - }; - - usb1_phy: phy@8820 { - compatible = "amlogic,meson-mx-usb2-phy"; - #phy-cells = <0>; - reg = <0x8820 0x20>; - status = "disabled"; - }; - - sdio: mmc@8c20 { - compatible = "amlogic,meson-mx-sdio"; - reg = <0x8c20 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0x8c80 0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdhc: mmc@8e00 { - compatible = "amlogic,meson-mx-sdhc"; - reg = <0x8e00 0x42>; - interrupts = ; - status = "disabled"; - }; - - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0x9880 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - - wdt: watchdog@9900 { - compatible = "amlogic,meson6-wdt"; - reg = <0x9900 0x8>; - interrupts = ; - }; - - timer_abcde: timer@9940 { - compatible = "amlogic,meson6-timer"; - reg = <0x9940 0x18>; - interrupts = , - , - , - ; - }; - }; - - L2: cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - periph: bus@c4300000 { - compatible = "simple-bus"; - reg = <0xc4300000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc4300000 0x10000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x1000 0x1000>, - <0x100 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; - - aobus: aobus@c8100000 { - compatible = "simple-bus"; - reg = <0xc8100000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8100000 0x100000>; - - ao_arc_rproc: remoteproc@1c { - compatible = "amlogic,meson-mx-ao-arc"; - reg = <0x1c 0x8>, <0x38 0x8>; - reg-names = "remap", "cpu"; - status = "disabled"; - }; - - ir_receiver: ir-receiver@480 { - compatible = "amlogic,meson6-ir"; - reg = <0x480 0x20>; - interrupts = ; - status = "disabled"; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart"; - reg = <0x4c0 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson6-i2c"; - reg = <0x500 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@740 { - compatible = "amlogic,meson6-rtc"; - reg = <0x740 0x14>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - }; - - usb0: usb@c9040000 { - compatible = "snps,dwc2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc9040000 0x40000>; - interrupts = ; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <500>; - g-tx-fifo-size = <256 192 128 128 128>; - dr_mode = "host"; - status = "disabled"; - }; - - usb1: usb@c90c0000 { - compatible = "snps,dwc2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc90c0000 0x40000>; - interrupts = ; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; - reg = <0xc9410000 0x10000 - 0xc1108108 0x4>; - interrupts = ; - interrupt-names = "macirq"; - status = "disabled"; - }; - - ahb_sram: sram@d9000000 { - compatible = "mmio-sram"; - reg = <0xd9000000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd9000000 0x20000>; - }; - - bootrom: bootrom@d9040000 { - compatible = "amlogic,meson-mx-bootrom", "syscon"; - reg = <0xd9040000 0x10000>; - }; - - secbus: secbus@da000000 { - compatible = "simple-bus"; - reg = <0xda000000 0x6000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xda000000 0x6000>; - - efuse: nvmem@0 { - compatible = "amlogic,meson6-efuse"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - }; - - thermal_sensor: thermal-sensor { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&saradc 8>; - io-channel-names = "sensor-channel"; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts deleted file mode 100644 index 98e1c94c0261..000000000000 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -/dts-v1/; -#include "meson6.dtsi" - -/ { - model = "Geniatech ATV1200"; - compatible = "geniatech,atv1200", "amlogic,meson6"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; -}; - -&uart_AO { - status = "okay"; -}; - -ðmac { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi deleted file mode 100644 index 4716030a48d0..000000000000 --- a/arch/arm/boot/dts/meson6.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -#include "meson.dtsi" - -/ { - model = "Amlogic Meson6 SoC"; - compatible = "amlogic,meson6"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x201>; - }; - }; - - apb2: bus@d0000000 { - compatible = "simple-bus"; - reg = <0xd0000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000000 0x40000>; - }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; -}; /* end of / */ - -&efuse { - status = "disabled"; -}; - -&timer_abcde { - clocks = <&xtal>, <&clk81>; - clock-names = "xtal", "pclk"; -}; - -&uart_AO { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_A { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts deleted file mode 100644 index c6d1c5a8a3bf..000000000000 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Beniamino Galvani - */ - -/dts-v1/; -#include -#include "meson8.dtsi" - -/ { - model = "MINIX NEO-X8"; - compatible = "minix,neo-x8", "amlogic,meson8"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-blue { - label = "x8:blue:power"; - gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_pins>; - pinctrl-names = "default"; - - pmic@32 { - compatible = "ricoh,rn5t618"; - reg = <0x32>; - system-power-controller; - - regulators { - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&spi_nor_pins>; - pinctrl-names = "default"; - - flash@0 { - compatible = "mxicy,mx25l1606e"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <30000000>; - - partition@0 { - label = "boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x10000>; - }; - }; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_pins>; - pnictrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi deleted file mode 100644 index 59932fbfd5d5..000000000000 --- a/arch/arm/boot/dts/meson8.dtsi +++ /dev/null @@ -1,806 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -#include -#include -#include -#include -#include -#include -#include -#include "meson.dtsi" - -/ { - model = "Amlogic Meson8 SoC"; - compatible = "amlogic,meson8"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x201>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x202>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x203>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-96000000 { - opp-hz = /bits/ 64 <96000000>; - opp-microvolt = <825000>; - }; - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - opp-microvolt = <825000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <825000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <825000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <825000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <850000>; - }; - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <850000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <875000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <975000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; - }; - opp-1800000000 { - status = "disabled"; - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1125000>; - }; - opp-1992000000 { - status = "disabled"; - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000>; - }; - }; - - gpu_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-182142857 { - opp-hz = /bits/ 64 <182142857>; - opp-microvolt = <1150000>; - }; - opp-318750000 { - opp-hz = /bits/ 64 <318750000>; - opp-microvolt = <1150000>; - }; - opp-425000000 { - opp-hz = /bits/ 64 <425000000>; - opp-microvolt = <1150000>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-microvolt = <1150000>; - }; - opp-637500000 { - opp-hz = /bits/ 64 <637500000>; - opp-microvolt = <1150000>; - turbo-mode; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* 2 MiB reserved for Hardware ROM Firmware? */ - hwrom@0 { - reg = <0x0 0x200000>; - no-map; - }; - - /* - * 1 MiB reserved for the "ARM Power Firmware": this is ARM - * code which is responsible for system suspend. It loads a - * piece of ARC code ("arc_power" in the vendor u-boot tree) - * into SRAM, executes that and shuts down the (last) ARM core. - * The arc_power firmware then checks various wakeup sources - * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or - * simply the power key) and re-starts the ARM core once it - * detects a wakeup request. - */ - power-firmware@4f00000 { - reg = <0x4f00000 0x100000>; - no-map; - }; - }; - - thermal-zones { - soc { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&thermal_sensor>; - - cooling-maps { - map0 { - trip = <&soc_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&soc_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - soc_passive: soc-passive { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - soc_hot: soc-hot { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - soc_critical: soc-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - }; - - mmcbus: bus@c8000000 { - compatible = "simple-bus"; - reg = <0xc8000000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000000 0x8000>; - - ddr_clkc: clock-controller@400 { - compatible = "amlogic,meson8-ddr-clkc"; - reg = <0x400 0x20>; - clocks = <&xtal>; - clock-names = "xtal"; - #clock-cells = <1>; - }; - - dmcbus: bus@6000 { - compatible = "simple-bus"; - reg = <0x6000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x400>; - - canvas: video-lut@20 { - compatible = "amlogic,meson8-canvas", - "amlogic,canvas"; - reg = <0x20 0x14>; - }; - }; - }; - - apb: bus@d0000000 { - compatible = "simple-bus"; - reg = <0xd0000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000000 0x200000>; - - mali: gpu@c0000 { - compatible = "amlogic,meson8-mali", "arm,mali-450"; - reg = <0xc0000 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2", "pp4", "ppmmu4", - "pp5", "ppmmu5", "pp6", "ppmmu6"; - resets = <&reset RESET_MALI>; - - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - assigned-clocks = <&clkc CLKID_MALI>; - assigned-clock-rates = <318750000>; - - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; -}; /* end of / */ - -&aiu { - compatible = "amlogic,aiu-meson8", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&aobus { - pmu: pmu@e0 { - compatible = "amlogic,meson8-pmu", "syscon"; - reg = <0xe0 0x18>; - }; - - pinctrl_aobus: pinctrl@84 { - compatible = "amlogic,meson8-aobus-pinctrl"; - reg = <0x84 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@14 { - reg = <0x14 0x4>, - <0x2c 0x4>, - <0x24 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - - i2s_am_clk_pins: i2s-am-clk-out { - mux { - groups = "i2s_am_clk_out_ao"; - function = "i2s_ao"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s-ao-clk-out { - mux { - groups = "i2s_ao_clk_out_ao"; - function = "i2s_ao"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s-lr-clk-out { - mux { - groups = "i2s_lr_clk_out_ao"; - function = "i2s_ao"; - bias-disable; - }; - }; - - i2s_out_ch01_ao_pins: i2s-out-ch01 { - mux { - groups = "i2s_out_ch01_ao"; - function = "i2s_ao"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_mst_ao { - mux { - groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; - function = "i2c_mst_ao"; - bias-disable; - }; - }; - - ir_recv_pins: remote { - mux { - groups = "remote_input"; - function = "remote"; - bias-disable; - }; - }; - - pwm_f_ao_pins: pwm-f-ao { - mux { - groups = "pwm_f_ao"; - function = "pwm_f_ao"; - bias-disable; - }; - }; - }; -}; - -&ao_arc_rproc { - compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; - amlogic,secbus2 = <&secbus2>; - sram = <&ao_arc_sram>; - resets = <&reset RESET_MEDIA_CPU>; - clocks = <&clkc CLKID_AO_MEDIA_CPU>; -}; - -&cbus { - reset: reset-controller@4404 { - compatible = "amlogic,meson8b-reset"; - reg = <0x4404 0x9c>; - #reset-cells = <1>; - }; - - analog_top: analog-top@81a8 { - compatible = "amlogic,meson8-analog-top", "syscon"; - reg = <0x81a8 0x14>; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; - reg = <0x86c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson8-clk-measure"; - reg = <0x8758 0x1c>; - }; - - pinctrl_cbus: pinctrl@9880 { - compatible = "amlogic,meson8-cbus-pinctrl"; - reg = <0x9880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@80b0 { - reg = <0x80b0 0x28>, - <0x80e8 0x18>, - <0x8120 0x18>, - <0x8030 0x30>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 120>; - }; - - sd_a_pins: sd-a { - mux { - groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", - "sd_d3_a", "sd_clk_a", "sd_cmd_a"; - function = "sd_a"; - bias-disable; - }; - }; - - sd_b_pins: sd-b { - mux { - groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", - "sd_d3_b", "sd_clk_b", "sd_cmd_b"; - function = "sd_b"; - bias-disable; - }; - }; - - sd_c_pins: sd-c { - mux { - groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", - "sd_d3_c", "sd_clk_c", "sd_cmd_c"; - function = "sd_c"; - bias-disable; - }; - }; - - sdxc_a_pins: sdxc-a { - mux { - groups = "sdxc_d0_a", "sdxc_d13_a", - "sdxc_clk_a", "sdxc_cmd_a"; - function = "sdxc_a"; - bias-pull-up; - }; - }; - - sdxc_b_pins: sdxc-b { - mux { - groups = "sdxc_d0_b", "sdxc_d13_b", - "sdxc_clk_b", "sdxc_cmd_b"; - function = "sdxc_b"; - bias-pull-up; - }; - }; - - spdif_out_pins: spdif-out { - mux { - groups = "spdif_out"; - function = "spdif"; - bias-disable; - }; - }; - - spi_nor_pins: nor { - mux { - groups = "nor_d", "nor_q", "nor_c", "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - eth_pins: ethernet { - mux { - groups = "eth_tx_clk_50m", "eth_tx_en", - "eth_txd1", "eth_txd0", - "eth_rx_clk_in", "eth_rx_dv", - "eth_rxd1", "eth_rxd0", "eth_mdio", - "eth_mdc"; - function = "ethernet"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - uart_a1_pins: uart-a1 { - mux { - groups = "uart_tx_a1", - "uart_rx_a1"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a1_cts_rts_pins: uart-a1-cts-rts { - mux { - groups = "uart_cts_a1", - "uart_rts_a1"; - function = "uart_a"; - bias-disable; - }; - }; - - xtal_32k_out_pins: xtal-32k-out { - mux { - groups = "xtal_32k_out"; - function = "xtal"; - bias-disable; - }; - }; - }; -}; - -&ahb_sram { - ao_arc_sram: ao-arc-sram@0 { - compatible = "amlogic,meson8-ao-arc-sram"; - reg = <0x0 0x8000>; - pool; - }; - - smp-sram@1ff80 { - compatible = "amlogic,meson8-smp-sram"; - reg = <0x1ff80 0x8>; - }; -}; - -&efuse { - compatible = "amlogic,meson8-efuse"; - clocks = <&clkc CLKID_EFUSE>; - clock-names = "core"; - - temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>; - clock-names = "stmmaceth"; - - power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; -}; - -&gpio_intc { - compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; - status = "okay"; -}; - -&hhi { - clkc: clock-controller { - compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pwrc: power-controller { - compatible = "amlogic,meson8-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&pmu>; - clocks = <&clkc CLKID_VPU>; - clock-names = "vpu"; - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <364285714>; - }; -}; - -&hwrng { - compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_AO { - clocks = <&clkc CLKID_CLK81>; -}; - -&i2c_A { - clocks = <&clkc CLKID_CLK81>; -}; - -&i2c_B { - clocks = <&clkc CLKID_CLK81>; -}; - -&L2 { - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x100000 0xc0000000>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,prefetch-offset = <7>; - arm,double-linefill = <1>; - arm,prefetch-drop = <1>; - arm,shared-override; -}; - -&periph { - scu@0 { - compatible = "arm,cortex-a9-scu"; - reg = <0x0 0x100>; - }; - - timer@200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x200 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - - /* - * the arm_global_timer driver currently does not handle clock - * rate changes. Keep it disabled for now. - */ - status = "disabled"; - }; - - timer@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - }; -}; - -&pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; -}; - -&pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; -}; - -&rtc { - compatible = "amlogic,meson8-rtc"; - resets = <&reset RESET_RTC>; -}; - -&saradc { - compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; - clock-names = "clkin", "core"; - amlogic,hhi-sysctrl = <&hhi>; - nvmem-cells = <&temperature_calib>; - nvmem-cell-names = "temperature_calib"; -}; - -&sdhc { - compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; - clocks = <&xtal>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV5>, - <&clkc CLKID_SDHC>; - clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; -}; - -&secbus { - secbus2: system-controller@4000 { - compatible = "amlogic,meson8-secbus2", "syscon"; - reg = <0x4000 0x2000>; - }; -}; - -&sdio { - compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; -}; - -&spifc { - clocks = <&clkc CLKID_CLK81>; -}; - -&timer_abcde { - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk"; -}; - -&uart_AO { - compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart"; - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_A { - compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&usb0 { - compatible = "amlogic,meson8-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb1 { - compatible = "amlogic,meson8-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb0_phy { - compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; - -&usb1_phy { - compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts deleted file mode 100644 index 3da47349eaaf..000000000000 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ /dev/null @@ -1,479 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Martin Blumenstingl . - */ - -/dts-v1/; - -#include -#include - -#include "meson8b.dtsi" - -/ { - model = "Endless Computers Endless Mini"; - compatible = "endless,ec100", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - pal-switch { - label = "pal"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; - }; - - ntsc-switch { - label = "ntsc"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>; - }; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio GPIOH_9 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - /* - * shutdown is managed by the EC (embedded micro-controller) - * which is configured through GPIOAO_2 (poweroff GPIO) and - * GPIOAO_7 (power LED, which has to go LOW as well). - */ - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - timeout-ms = <20000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "ec100:red:power"; - /* - * Needs to go LOW (together with the poweroff GPIO) - * during shutdown to allow the EC (embedded - * micro-controller) to shutdown the system. Setting - * the output to LOW signals the EC to start a - * "breathing"/pulsing effect until the power is fully - * turned off. - */ - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - rtc32k_xtal: rtc32k-xtal-clk { - /* X2 in the schematics */ - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "RTC32K"; - #clock-cells = <0>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "M8B-EC100"; - - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-rates = <270950400>, - <294912000>, - <393216000>; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&rt5640>; - }; - }; - }; - - usb_vbus: regulator-usb-vbus { - /* - * Silergy SY6288CCAC-GP 2A Power Distribution Switch. - */ - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vcc_5v>; - - /* - * signal name from the schematics: USB_PWR_EN - */ - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_5v: regulator-vcc5v { - /* - * supplied by the main power input which called PWR_5V_STB - * in the schematics - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC5V"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* - * signal name from the schematics: 3V3_5V_EN - */ - gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; - - regulator-boot-on; - regulator-always-on; - }; - - vcck: regulator-vcck { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&vcc_5v>; - - pwms = <&pwm_cd 0 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc1v8 { - /* - * ABLIC S-1339D18-M5001-GP - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&vcc_3v3>; - }; - - vcc_3v3: regulator-vcc3v3 { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. Also called - * VDDIO_AO3.3V in the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_5v>; - }; - - vcc_ddr3: regulator-vcc-ddr3 { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. Also called - * DDR3_1.5V in the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC_DDR3_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&vcc_5v>; - - regulator-boot-on; - regulator-always-on; - }; - - vcc_rtc: regulator-vcc-rtc { - /* - * Global Mixed-mode Technology Inc. G918T12U-GP - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC_RTC"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - /* - * When the board is powered then the input is VCC3V3, - * otherwise power is taken from the coin cell battery. - */ - vin-supply = <&vcc_3v3>; - }; - - vddee: regulator-vddee { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. Also called VDDAO - * in a part of the schematics. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDEE"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&vcc_5v>; - - pwms = <&pwm_cd 1 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&aiu { - status = "okay"; - - pinctrl-0 = <&i2s_am_clk_pins>, <&i2s_out_ao_clk_pins>, - <&i2s_out_lr_clk_pins>, <&i2s_out_ch01_ao_pins>; - pinctrl-names = "default"; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101A/G (0x02430c54) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - icplus,select-interrupt; - interrupt-parent = <&gpio_intc>; - /* GPIOH_3 */ - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; - - rt5640: codec@1c { - compatible = "realtek,rt5640"; - - reg = <0x1c>; - - #sound-dai-cells = <0>; - - interrupt-parent = <&gpio_intc>; - interrupts = <13 IRQ_TYPE_EDGE_BOTH>; /* GPIOAO_13 */ - - /* - * TODO: realtek,ldo1-en-gpios is connected to GPIO_BSD_EN. - * We currently cannot configure this pin correctly. - * Luckily for us it's in the "right" state by default. - */ - realtek,in1-differential; - }; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdhc { - status = "okay"; - - pinctrl-0 = <&sdxc_c_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - max-frequency = <50000000>; - - cap-mmc-highspeed; - disable-wp; - non-removable; - no-sdio; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - }; -}; - -&gpio_ao { - gpio-line-names = "Linux_TX", "Linux_RX", - "SLP_S5_N", "USB2_OC_FLAG#", - "HUB_RST", "USB_PWR_EN", - "I2S_IN", "SLP_S1_N", - "TCK", "TMS", "TDI", "TDO", - "HDMI_CEC", "5640_IRQ", - "MUTE", "S805_TEST#"; -}; - -&gpio { - gpio-line-names = /* Bank GPIOX */ - "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", - "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", - "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", - "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", - "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", - "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", - /* Bank GPIOY */ - "", "", "", "", "", "", "", "", "", "", - "", "", - /* Bank GPIODV */ - "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", - "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", - "VDDEE_PWM 3V3_5V_EN", - /* Bank GPIOH */ - "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", - "RMII_IRQ", "RMII_RST#", "RMII_TXD1", - "RMII_TXD0", "AV_select_1", "AV_select_2", - "MCU_Control_S", - /* Bank CARD */ - "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", - "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", - "CARD_EN_DET (CARD_DET)", - /* Bank BOOT */ - "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", - "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", - "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", - "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", - "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", - "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", - "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", - "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", - /* Bank DIF */ - "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", - "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", - "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", - "RMII_MDIO"; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; - pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; -}; - -&rtc { - status = "okay"; - clocks = <&rtc32k_xtal>; - vdd-supply = <&vcc_rtc>; -}; - -/* exposed through the pin headers labeled "URDUG1" on the top of the PCB */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* - * connected to the Bluetooth part of the RTL8723BS SDIO wifi / Bluetooth - * combo chip. This is only available on the variant with 2GB RAM. - */ -&uart_B { - status = "okay"; - pinctrl-0 = <&uart_b0_pins>, <&uart_b0_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts deleted file mode 100644 index 7adedd3258c3..000000000000 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include - -#include "meson8b.dtsi" - -/ { - model = "TRONFY MXQ S805"; - compatible = "tronfy,mxq", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - vcck: regulator-vcck { - compatible = "pwm-regulator"; - - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&vcc_5v>; - - pwms = <&pwm_cd 0 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&vcc_3v3>; - }; - - vcc_3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_5v>; - }; - - vcc_5v: regulator-vcc5v { - compatible = "regulator-fixed"; - - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - regulator-boot-on; - regulator-always-on; - }; - - vddee: regulator-vddee { - compatible = "pwm-regulator"; - - regulator-name = "VDDEE"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&vcc_5v>; - - pwms = <&pwm_cd 1 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101A/G (0x02430c54) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - icplus,select-interrupt; - interrupt-parent = <&gpio_intc>; - /* GPIOH_3 */ - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - }; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; - pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts deleted file mode 100644 index 941682844faf..000000000000 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ /dev/null @@ -1,383 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; -#include "meson8b.dtsi" -#include - -/ { - model = "Hardkernel ODROID-C1"; - compatible = "hardkernel,odroid-c1", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - mmc0 = &sd_card_slot; - mmc1 = &sdhc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - led-blue { - label = "c1:blue:alive"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - p5v0: regulator-p5v0 { - compatible = "regulator-fixed"; - - regulator-name = "P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - tflash_vdd: regulator-tflash_vdd { - /* - * signal name from schematics: TFLASH_VDD_EN - */ - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_3v3>; - - gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_3v3>; - - /* - * signal name from schematics: TF_3V3N_1V8_EN - */ - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0 - 1800000 1>; - }; - - rtc32k_xtal: rtc32k-xtal-clk { - /* X3 in the schematics */ - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "RTC32K"; - #clock-cells = <0>; - }; - - vcc_1v8: regulator-vcc-1v8 { - /* - * RICHTEK RT9179 configured for a fixed output voltage of - * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and - * VDD1V8 according to the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&p5v0>; - }; - - vcc_3v3: regulator-vcc-3v3 { - /* - * Monolithic Power Systems MP2161 configured for a fixed - * output voltage of 3.3V. This supplies not only VCC3V3 but - * also VDD3V3 and VDDIO_AO3V3 according to the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&p5v0>; - }; - - vcck: regulator-vcck { - /* Monolithic Power Systems MP2161 */ - compatible = "pwm-regulator"; - - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&p5v0>; - - pwms = <&pwm_cd 0 12218 0>; - pwm-dutycycle-range = <91 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddc_ddr: regulator-vddc-ddr { - /* - * Monolithic Power Systems MP2161 configured for a fixed - * output voltage of 1.5V. This supplies not only DDR_VDDC but - * also DDR3_1V5 according to the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "DDR_VDDC"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&p5v0>; - }; - - vddee: regulator-vddee { - /* Monolithic Power Systems MP2161 */ - compatible = "pwm-regulator"; - - regulator-name = "VDDEE"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&p5v0>; - - pwms = <&pwm_cd 1 12218 0>; - pwm-dutycycle-range = <91 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vdd_rtc: regulator-vdd-rtc { - /* - * Torex Semiconductor XC6215 configured for a fixed output of - * 0.9V. - */ - compatible = "regulator-fixed"; - - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&vcc_3v3>; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -&efuse { - ethernet_mac_address: mac@1b4 { - reg = <0x1b4 0x6>; - }; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy>; - phy-mode = "rgmii-id"; - - nvmem-cells = <ðernet_mac_address>; - nvmem-cell-names = "mac-address"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - /* Realtek RTL8211F (0x001cc916) */ - eth_phy: ethernet-phy@0 { - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* GPIOH_3 */ - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&gpio { - gpio-line-names = /* Bank GPIOX */ - "J2 Header Pin 35", "J2 Header Pin 36", - "J2 Header Pin 32", "J2 Header Pin 31", - "J2 Header Pin 29", "J2 Header Pin 18", - "J2 Header Pin 22", "J2 Header Pin 16", - "J2 Header Pin 23", "J2 Header Pin 21", - "J2 Header Pin 19", "J2 Header Pin 33", - "J2 Header Pin 8", "J2 Header Pin 10", - "J2 Header Pin 15", "J2 Header Pin 13", - "J2 Header Pin 24", "J2 Header Pin 26", - /* Bank GPIOY */ - "Revision (upper)", "Revision (lower)", - "J2 Header Pin 7", "", "J2 Header Pin 12", - "J2 Header Pin 11", "", "", "", - "TFLASH_VDD_EN", "", "", - /* Bank GPIODV */ - "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL", - "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)", - "", - /* Bank GPIOH */ - "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", - "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1", - "ETH_TXD0", "ETH_TXD3", "ETH_TXD2", - "ETH_RGMII_TX_CLK", - /* Bank CARD */ - "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)", - "SD_CLK", "SD_CMD", "SD_DATA3 (SDB_D3)", - "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)", - /* Bank BOOT */ - "SDC_D0 (EMMC)", "SDC_D1 (EMMC)", - "SDC_D2 (EMMC)", "SDC_D3 (EMMC)", - "SDC_D4 (EMMC)", "SDC_D5 (EMMC)", - "SDC_D6 (EMMC)", "SDC_D7 (EMMC)", - "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)", - "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "", - "", "", "", "", - /* Bank DIF */ - "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV", - "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2", - "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", - "ETH_MDC", "ETH_MDIO"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "", - "TF_3V3N_1V8_EN", "USB_HUB_RST_N", - "USB_OTG_PWREN", "J7 Header Pin 2", - "IR_IN", "J7 Header Pin 4", - "J7 Header Pin 6", "J7 Header Pin 5", - "J7 Header Pin 7", "HDMI_CEC", - "SYS_LED", "", ""; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdhc { - status = "okay"; - - pinctrl-0 = <&sdxc_c_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - max-frequency = <100000000>; - - disable-wp; - cap-mmc-highspeed; - mmc-hs200-1_8v; - no-sdio; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - }; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; - pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; -}; - -&rtc { - /* needs to be enabled manually when a battery is connected */ - clocks = <&rtc32k_xtal>; - vdd-supply = <&vdd_rtc>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - hub@1 { - /* Genesys Logic GL852G usb hub */ - compatible = "usb5e3,610"; - reg = <1>; - vdd-supply = <&p5v0>; - reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi deleted file mode 100644 index 5198f5177c2c..000000000000 --- a/arch/arm/boot/dts/meson8b.dtsi +++ /dev/null @@ -1,781 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -#include -#include -#include -#include -#include -#include -#include -#include "meson.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x200>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x201>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x202>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x203>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-96000000 { - opp-hz = /bits/ 64 <96000000>; - opp-microvolt = <860000>; - }; - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - opp-microvolt = <860000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <860000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <860000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <860000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <860000>; - }; - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <860000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1140000>; - }; - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <1140000>; - }; - opp-1488000000 { - opp-hz = /bits/ 64 <1488000000>; - opp-microvolt = <1140000>; - }; - opp-1536000000 { - opp-hz = /bits/ 64 <1536000000>; - opp-microvolt = <1140000>; - }; - }; - - gpu_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-255000000 { - opp-hz = /bits/ 64 <255000000>; - opp-microvolt = <1100000>; - }; - opp-364285714 { - opp-hz = /bits/ 64 <364285714>; - opp-microvolt = <1100000>; - }; - opp-425000000 { - opp-hz = /bits/ 64 <425000000>; - opp-microvolt = <1100000>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-microvolt = <1100000>; - }; - opp-637500000 { - opp-hz = /bits/ 64 <637500000>; - opp-microvolt = <1100000>; - turbo-mode; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* 2 MiB reserved for Hardware ROM Firmware? */ - hwrom@0 { - reg = <0x0 0x200000>; - no-map; - }; - }; - - thermal-zones { - soc { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&thermal_sensor>; - - cooling-maps { - map0 { - trip = <&soc_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&soc_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - soc_passive: soc-passive { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - soc_hot: soc-hot { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - soc_critical: soc-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - }; - - mmcbus: bus@c8000000 { - compatible = "simple-bus"; - reg = <0xc8000000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000000 0x8000>; - - ddr_clkc: clock-controller@400 { - compatible = "amlogic,meson8b-ddr-clkc"; - reg = <0x400 0x20>; - clocks = <&xtal>; - clock-names = "xtal"; - #clock-cells = <1>; - }; - - dmcbus: bus@6000 { - compatible = "simple-bus"; - reg = <0x6000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,meson8b-canvas", - "amlogic,canvas"; - reg = <0x48 0x14>; - }; - }; - }; - - apb: bus@d0000000 { - compatible = "simple-bus"; - reg = <0xd0000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000000 0x200000>; - - mali: gpu@c0000 { - compatible = "amlogic,meson8b-mali", "arm,mali-450"; - reg = <0xc0000 0x40000>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1"; - resets = <&reset RESET_MALI>; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; -}; /* end of / */ - -&aiu { - compatible = "amlogic,aiu-meson8b", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&aobus { - pmu: pmu@e0 { - compatible = "amlogic,meson8b-pmu", "syscon"; - reg = <0xe0 0x18>; - }; - - pinctrl_aobus: pinctrl@84 { - compatible = "amlogic,meson8b-aobus-pinctrl"; - reg = <0x84 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@14 { - reg = <0x14 0x4>, - <0x2c 0x4>, - <0x24 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - - i2s_am_clk_pins: i2s-am-clk-out { - mux { - groups = "i2s_am_clk_out"; - function = "i2s"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s-ao-clk-out { - mux { - groups = "i2s_ao_clk_out"; - function = "i2s"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s-lr-clk-out { - mux { - groups = "i2s_lr_clk_out"; - function = "i2s"; - bias-disable; - }; - }; - - i2s_out_ch01_ao_pins: i2s-out-ch01 { - mux { - groups = "i2s_out_01"; - function = "i2s"; - bias-disable; - }; - }; - - spdif_out_1_pins: spdif-out-1 { - mux { - groups = "spdif_out_1"; - function = "spdif_1"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - ir_recv_pins: remote { - mux { - groups = "remote_input"; - function = "remote"; - bias-disable; - }; - }; - }; -}; - -&ao_arc_rproc { - compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; - amlogic,secbus2 = <&secbus2>; - sram = <&ao_arc_sram>; - resets = <&reset RESET_MEDIA_CPU>; - clocks = <&clkc CLKID_AO_MEDIA_CPU>; -}; - -&cbus { - reset: reset-controller@4404 { - compatible = "amlogic,meson8b-reset"; - reg = <0x4404 0x9c>; - #reset-cells = <1>; - }; - - analog_top: analog-top@81a8 { - compatible = "amlogic,meson8b-analog-top", "syscon"; - reg = <0x81a8 0x14>; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; - reg = <0x86c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson8b-clk-measure"; - reg = <0x8758 0x1c>; - }; - - pinctrl_cbus: pinctrl@9880 { - compatible = "amlogic,meson8b-cbus-pinctrl"; - reg = <0x9880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@80b0 { - reg = <0x80b0 0x28>, - <0x80e8 0x18>, - <0x8120 0x18>, - <0x8030 0x38>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 83>; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_tx_clk", - "eth_tx_en", - "eth_txd1_0", - "eth_txd0_0", - "eth_rx_clk", - "eth_rx_dv", - "eth_rxd1", - "eth_rxd0", - "eth_mdio_en", - "eth_mdc", - "eth_ref_clk", - "eth_txd2", - "eth_txd3", - "eth_rxd3", - "eth_rxd2"; - function = "ethernet"; - bias-disable; - }; - }; - - eth_rmii_pins: eth-rmii { - mux { - groups = "eth_tx_en", - "eth_txd1_0", - "eth_txd0_0", - "eth_rx_clk", - "eth_rx_dv", - "eth_rxd1", - "eth_rxd0", - "eth_mdio_en", - "eth_mdc"; - function = "ethernet"; - bias-disable; - }; - }; - - i2c_a_pins: i2c-a { - mux { - groups = "i2c_sda_a", "i2c_sck_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - sd_b_pins: sd-b { - mux { - groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", - "sd_d3_b", "sd_clk_b", "sd_cmd_b"; - function = "sd_b"; - bias-disable; - }; - }; - - sdxc_c_pins: sdxc-c { - mux { - groups = "sdxc_d0_c", "sdxc_d13_c", - "sdxc_d47_c", "sdxc_clk_c", - "sdxc_cmd_c"; - function = "sdxc_c"; - bias-pull-up; - }; - }; - - pwm_c1_pins: pwm-c1 { - mux { - groups = "pwm_c1"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_pins: pwm-d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - uart_b0_pins: uart-b0 { - mux { - groups = "uart_tx_b0", - "uart_rx_b0"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b0_cts_rts_pins: uart-b0-cts-rts { - mux { - groups = "uart_cts_b0", - "uart_rts_b0"; - function = "uart_b"; - bias-disable; - }; - }; - }; -}; - -&ahb_sram { - ao_arc_sram: ao-arc-sram@0 { - compatible = "amlogic,meson8b-ao-arc-sram"; - reg = <0x0 0x8000>; - pool; - }; - - smp-sram@1ff80 { - compatible = "amlogic,meson8b-smp-sram"; - reg = <0x1ff80 0x8>; - }; -}; - - -&efuse { - compatible = "amlogic,meson8b-efuse"; - clocks = <&clkc CLKID_EFUSE>; - clock-names = "core"; - - temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -}; - -ðmac { - compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; - - reg = <0xc9410000 0x10000 - 0xc1108140 0x4>; - - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - - resets = <&reset RESET_ETHERNET>; - reset-names = "stmmaceth"; - - power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; -}; - -&gpio_intc { - compatible = "amlogic,meson8b-gpio-intc", - "amlogic,meson-gpio-intc"; - status = "okay"; -}; - -&hhi { - clkc: clock-controller { - compatible = "amlogic,meson8b-clkc"; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pwrc: power-controller { - compatible = "amlogic,meson8b-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&pmu>; - resets = <&reset RESET_DBLK>, - <&reset RESET_PIC_DC>, - <&reset RESET_HDMI_APB>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC_4>, - <&reset RESET_VENCL>, - <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_RDMA>; - reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", - "venci", "vencp", "vdac", "vencl", "viu", - "venc", "rdma"; - clocks = <&clkc CLKID_VPU>; - clock-names = "vpu"; - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <182142857>; - }; -}; - -&hwrng { - compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_AO { - clocks = <&clkc CLKID_CLK81>; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&L2 { - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x100000 0xc0000000>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,prefetch-offset = <7>; - arm,double-linefill = <1>; - arm,prefetch-drop = <1>; - arm,shared-override; -}; - -&periph { - scu@0 { - compatible = "arm,cortex-a5-scu"; - reg = <0x0 0x100>; - }; - - timer@200 { - compatible = "arm,cortex-a5-global-timer"; - reg = <0x200 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - - /* - * the arm_global_timer driver currently does not handle clock - * rate changes. Keep it disabled for now. - */ - status = "disabled"; - }; - - timer@600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - }; -}; - -&pwm_ab { - compatible = "amlogic,meson8b-pwm"; -}; - -&pwm_cd { - compatible = "amlogic,meson8b-pwm"; -}; - -&rtc { - compatible = "amlogic,meson8b-rtc"; - resets = <&reset RESET_RTC>; -}; - -&saradc { - compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; - clock-names = "clkin", "core"; - amlogic,hhi-sysctrl = <&hhi>; - nvmem-cells = <&temperature_calib>; - nvmem-cell-names = "temperature_calib"; -}; - -&sdhc { - compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; - clocks = <&xtal>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV5>, - <&clkc CLKID_SDHC>; - clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; -}; - -&secbus { - secbus2: system-controller@4000 { - compatible = "amlogic,meson8b-secbus2", "syscon"; - reg = <0x4000 0x2000>; - }; -}; - -&sdio { - compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; -}; - -&timer_abcde { - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk"; -}; - -&uart_AO { - compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_A { - compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&usb0 { - compatible = "amlogic,meson8b-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb1 { - compatible = "amlogic,meson8b-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb0_phy { - compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; - -&usb1_phy { - compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; - -&wdt { - compatible = "amlogic,meson8b-wdt"; -}; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts deleted file mode 100644 index aa4d4bf70629..000000000000 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Oleg Ivanov - * Copyright (c) 2018 Martin Blumenstingl - */ - -/dts-v1/; - -#include "meson8m2.dtsi" - -#include -#include - -/ { - model = "Tronsmart MXIII Plus"; - compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2"; - - aliases { - ethernet0 = ðmac; - i2c0 = &i2c_AO; - serial0 = &uart_AO; - mmc0 = &sd_card_slot; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - - pinctrl-0 = <&xtal_32k_out_pins>; - pinctrl-names = "default"; - - reset-gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>, - <&gpio_ao GPIOAO_6 GPIO_ACTIVE_LOW>; - - clocks = <&xtal_32k_out>; - clock-names = "ext_clock"; - }; - - vcc_3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - xtal_32k_out: xtal-32k-out-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xtal_32k_out"; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii-id"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_pins>; - pinctrl-names = "default"; - - pmic@32 { - compatible = "ricoh,rn5t618"; - reg = <0x32>; - system-power-controller; - - regulators { - vcck: DCDC1 { - regulator-name = "VCCK"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vddee: DCDC2 { - /* the output is also used as VDDAO */ - regulator-name = "VDD_EE"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - DCDC3 { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "VDDIO_AO28"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: LDO2 { - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "VCC2V8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "AVDD1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDORTC1 { - regulator-name = "VDD_LDO"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-boot-on; - regulator-always-on; - }; - - LDORTC2 { - regulator-name = "RTC_0V9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO wifi */ -&sdhc { - status = "okay"; - - pinctrl-0 = <&sdxc_a_pins>; - pinctrl-names = "default"; - - bus-width = <4>; - max-frequency = <50000000>; - - disable-wp; - non-removable; - cap-mmc-highspeed; - cap-sd-highspeed; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - }; -}; - -/* connected to the Bluetooth module */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm20702a1"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi deleted file mode 100644 index 6725dd9fd825..000000000000 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl . - */ - -#include "meson8.dtsi" - -/ { - model = "Amlogic Meson8m2 SoC"; - compatible = "amlogic,meson8m2"; -}; /* end of / */ - -&clkc { - compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc"; -}; - -&dmcbus { - /* the offset of the canvas registers has changed compared to Meson8 */ - /delete-node/ video-lut@20; - - canvas: video-lut@48 { - compatible = "amlogic,meson8m2-canvas", "amlogic,canvas"; - reg = <0x48 0x14>; - }; -}; - -ðmac { - compatible = "amlogic,meson8m2-dwmac", "snps,dwmac"; - reg = <0xc9410000 0x10000 - 0xc1108140 0x8>; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; - resets = <&reset RESET_ETHERNET>; - reset-names = "stmmaceth"; -}; - -&pinctrl_aobus { - compatible = "amlogic,meson8m2-aobus-pinctrl", - "amlogic,meson8-aobus-pinctrl"; -}; - -&pinctrl_cbus { - compatible = "amlogic,meson8m2-cbus-pinctrl", - "amlogic,meson8-cbus-pinctrl"; - - eth_rgmii_pins: ethernet { - mux { - groups = "eth_tx_clk_50m", "eth_tx_en", - "eth_txd3", "eth_txd2", - "eth_txd1", "eth_txd0", - "eth_rx_clk_in", "eth_rx_dv", - "eth_rxd3", "eth_rxd2", - "eth_rxd1", "eth_rxd0", - "eth_mdio", "eth_mdc"; - function = "ethernet"; - bias-disable; - }; - }; -}; - -&pwrc { - compatible = "amlogic,meson8m2-pwrc"; - resets = <&reset RESET_DBLK>, - <&reset RESET_PIC_DC>, - <&reset RESET_HDMI_APB>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC_4>, - <&reset RESET_VENCL>, - <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_RDMA>; - reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci", - "vencp", "vdac", "vencl", "viu", "venc", "rdma"; - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <364000000>; -}; - -&saradc { - compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; -}; - -&sdhc { - compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; -}; - -&usb0_phy { - compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; -}; - -&usb1_phy { - compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; -}; - -&wdt { - compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; -}; diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..0f5193d05a31 --- /dev/null +++ b/arch/arm/boot/dts/microchip/Makefile @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ +DTC_FLAGS_at91-sama7g5ek := -@ +dtb-$(CONFIG_SOC_AT91RM9200) += \ + at91rm9200ek.dtb \ + mpa1600.dtb +dtb-$(CONFIG_SOC_AT91SAM9) += \ + animeo_ip.dtb \ + at91-qil_a9260.dtb \ + aks-cdu.dtb \ + ethernut5.dtb \ + evk-pro3.dtb \ + tny_a9260.dtb \ + usb_a9260.dtb \ + at91sam9260ek.dtb \ + at91sam9261ek.dtb \ + at91sam9263ek.dtb \ + at91-sam9_l9260.dtb \ + tny_a9263.dtb \ + usb_a9263.dtb \ + at91-foxg20.dtb \ + at91-kizbox.dtb \ + at91-lmu5000.dtb \ + at91sam9g20ek.dtb \ + at91sam9g20ek_2mmc.dtb \ + tny_a9g20.dtb \ + usb_a9g20.dtb \ + usb_a9g20_lpw.dtb \ + at91sam9m10g45ek.dtb \ + pm9g45.dtb \ + at91sam9n12ek.dtb \ + at91sam9rlek.dtb \ + at91-ariag25.dtb \ + at91-ariettag25.dtb \ + at91-cosino_mega2560.dtb \ + at91-kizboxmini-base.dtb \ + at91-kizboxmini-mb.dtb \ + at91-kizboxmini-rd.dtb \ + at91-q5xr5.dtb \ + at91-smartkiz.dtb \ + at91-wb45n.dtb \ + at91sam9g15ek.dtb \ + at91sam9g25-gardena-smart-gateway.dtb \ + at91sam9g25ek.dtb \ + at91sam9g35ek.dtb \ + at91sam9x25ek.dtb \ + at91sam9x35ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ +dtb-$(CONFIG_SOC_SAM9X60) += \ + at91-sam9x60_curiosity.dtb \ + at91-sam9x60ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ +dtb-$(CONFIG_SOC_SAM_V7) += \ + at91-kizbox2-2.dtb \ + at91-kizbox3-hs.dtb \ + at91-nattis-2-natte-2.dtb \ + at91-sama5d27_som1_ek.dtb \ + at91-sama5d27_wlsom1_ek.dtb \ + at91-sama5d2_icp.dtb \ + at91-sama5d2_ptc_ek.dtb \ + at91-sama5d2_xplained.dtb \ + at91-sama5d3_eds.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ + at91-sama5d3_xplained.dtb \ + at91-dvk_som60.dtb \ + at91-gatwick.dtb \ + at91-tse850-3.dtb \ + at91-wb50n.dtb \ + sama5d31ek.dtb \ + sama5d33ek.dtb \ + sama5d34ek.dtb \ + sama5d35ek.dtb \ + sama5d36ek.dtb \ + sama5d36ek_cmp.dtb \ + at91-sama5d4_ma5d4evk.dtb \ + at91-sama5d4_xplained.dtb \ + at91-sama5d4ek.dtb \ + at91-vinco.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama7g5ek := -@ +dtb-$(CONFIG_SOC_SAMA7G5) += \ + at91-sama7g5ek.dtb + +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ + lan966x-kontron-kswitch-d10-mmt-8g.dtb \ + lan966x-pcb8290.dtb \ + lan966x-pcb8291.dtb \ + lan966x-pcb8309.dtb diff --git a/arch/arm/boot/dts/microchip/aks-cdu.dts b/arch/arm/boot/dts/microchip/aks-cdu.dts new file mode 100644 index 000000000000..742fcf525e1b --- /dev/null +++ b/arch/arm/boot/dts/microchip/aks-cdu.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * aks-cdu.dts - Device Tree file for AK signal CDU + * + * Copyright (C) 2012 AK signal Brno a.s. + * 2012 Jiri Prchal + */ + +/dts-v1/; + +#include "ge863-pro3.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + }; + + ahb { + apb { + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + usart2: serial@fffb8000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + usart3: serial@fffd0000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + + ebi: ebi@10000000 { + nand_controller: nand-controller { + nand: nand@3 { + partitions { + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "uboot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "ubootenv"; + reg = <0xc0000 0x40000>; + }; + + kernel@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + rootfs@500000 { + label = "rootfs"; + reg = <0x500000 0x7b00000>; + }; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + red { + gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + + green { + gpios = <&pioA 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "on"; + }; + + yellow { + gpios = <&pioB 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + blue { + gpios = <&pioB 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/animeo_ip.dts b/arch/arm/boot/dts/microchip/animeo_ip.dts new file mode 100644 index 000000000000..29936bfbeeb7 --- /dev/null +++ b/arch/arm/boot/dts/microchip/animeo_ip.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards + * + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +/dts-v1/; +#include "at91sam9260.dtsi" + +/ { + model = "Somfy Animeo IP"; + compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9"; + + aliases { + serial0 = &usart1; + serial1 = &usart2; + serial2 = &usart0; + serial3 = &dbgu; + serial4 = &usart3; + serial5 = &uart0; + serial6 = &uart1; + }; + + chosen { + stdout-path = &usart2; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>; + linux,rs485-enabled-at-boot-time; + status = "okay"; + }; + + usart1: serial@fffb4000 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>; + linux,rs485-enabled-at-boot-time; + status = "okay"; + }; + + usart2: serial@fffb8000 { + pinctrl-0 = <&pinctrl_usart2>; + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>; + phy-mode = "mii"; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = <&pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@1 { + reg = <1>; + bus-width = <4>; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x0 0x58000>; + }; + + u_boot_env@58000 { + label = "u_boot_env"; + reg = <0x58000 0x8000>; + }; + + ubi@60000 { + label = "ubi"; + reg = <0x60000 0x1FA0000>; + }; + }; + }; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green { + label = "power_green"; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + power_red { + label = "power_red"; + gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; + }; + + tx_green { + label = "tx_green"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + }; + + tx_red { + label = "tx_red"; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-switch-in { + label = "keyswitch_in"; + gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; + linux,code = <28>; + wakeup-source; + }; + + key-error-in { + label = "error_in"; + gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; + linux,code = <29>; + wakeup-source; + }; + + key-s { + label = "btn"; + gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; + linux,code = <31>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-ariag25.dts b/arch/arm/boot/dts/microchip/at91-ariag25.dts new file mode 100644 index 000000000000..713d18f80356 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-ariag25.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based) + * + * Copyright (C) 2013 Douglas Gilbert , + * Robert Nelson + */ +/dts-v1/; +#include "at91sam9g25.dtsi" + +/ { + model = "Acme Systems Aria G25"; + compatible = "acme,ariag25", "atmel,at91sam9x5ek", + "atmel,at91sam9x5", "atmel,at91sam9"; + + aliases { + serial5 = &uart0; + serial6 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; + }; + + memory@20000000 { + /* 128 MB, change this for 256 MB revision */ + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* little green LED in middle of Aria G25 module */ + aria_led { + label = "aria_led"; + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ + linux,default-trigger = "heartbeat"; + }; + + }; + + onewire { + compatible = "w1-gpio"; + gpios = <&pioA 21 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_w1_0>; + }; +}; + +&adc0 { + status = "okay"; + atmel,adc-channels-used = <0xf>; +}; + +&dbgu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */ + +&macb0 { + phy-mode = "rmii"; + /* + * following can be overwritten by bootloader: + * for example u-boot 'ftd set' command + */ + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; +}; + + +&mmc0 { + /* N.B. Aria has no SD card detect (CD), assumed present */ + + pinctrl-0 = < + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&pinctrl { + w1_0 { + pinctrl_w1_0: w1_0-0 { + atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */ + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +/* + * UART0/1 pins are marked as GPIO on + * Aria documentation. + * Change to "okay" if you need additional serial ports + */ +&uart0 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; +}; + +&usart0 { + pinctrl-0 = <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts>; + status = "okay"; +}; + +&usart1 { + pinctrl-0 = <&pinctrl_usart1 + /* &pinctrl_usart1_rts */ + /* &pinctrl_usart1_cts */ + >; + status = "okay"; +}; + +&usart2 { + /* cannot activate RTS2+CTS2, clash with + * ethernet on PB0 and PB1 */ + pinctrl-0 = <&pinctrl_usart2>; + status = "okay"; +}; + +&usart3 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <8 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3 + /* &pinctrl_usart3_rts */ + /* &pinctrl_usart3_cts */ + >; + status = "okay"; +}; + +&usb0 { + status = "okay"; + num-ports = <3>; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-ariettag25.dts b/arch/arm/boot/dts/microchip/at91-ariettag25.dts new file mode 100644 index 000000000000..2c52a71752c2 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-ariettag25.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Arietta G25 + * This device tree is minimal, to activate more peripherals, see: + * http://dts.acmesystems.it/arietta/ + */ +/dts-v1/; +#include "at91sam9g25.dtsi" + +/ { + model = "Acme Systems Arietta G25"; + compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + arietta_led { + label = "arietta_led"; + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&dbgu { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = < + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&rtc { + status = "okay"; +}; + +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { + num-ports = <3>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-cosino.dtsi b/arch/arm/boot/dts/microchip/at91-cosino.dtsi new file mode 100644 index 000000000000..ee0f5da6d819 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-cosino.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-cosino.dtsi - Device Tree file for Cosino core module + * + * Copyright (C) 2013 - Rodolfo Giometti + * HCE Engineering + * + * Derived from at91sam9x5ek.dtsi by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ + +#include "at91sam9g35.dtsi" + +/ { + model = "HCE Cosino core module"; + compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; +}; + +&adc0 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_addr_nand + &pinctrl_ebi_data_0_7>; + pinctrl-names = "default"; + status = "okay"; + + nand-controller { + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; +}; + +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts b/arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts new file mode 100644 index 000000000000..04cb7bee937d --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-cosino_mega2560.dts - Device Tree file for Cosino board with + * Mega 2560 extension + * + * Copyright (C) 2013 - Rodolfo Giometti + * HCE Engineering + * + * Derived from at91sam9g35ek.dts by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ + +/dts-v1/; +#include "at91-cosino.dtsi" + +/ { + model = "HCE Cosino Mega 2560"; + compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; +}; + +&adc0 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&mmc1 { + pinctrl-0 = < + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + non-removable; + }; +}; + +&rtc { + status = "okay"; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usb0 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-dvk_som60.dts b/arch/arm/boot/dts/microchip/at91-dvk_som60.dts new file mode 100644 index 000000000000..ededd5b0d27b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-dvk_som60.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ +/dts-v1/; +#include "at91-som60.dtsi" +#include "at91-dvk_su60_somc.dtsi" +#include "at91-dvk_su60_somc_lcm.dtsi" + +/ { + model = "Laird DVK SOM60"; + compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + tick-timer = &pit; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&ssc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&pit { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi new file mode 100644 index 000000000000..3542ad8a243e --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ + +/ { + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ DVK-SOM60"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "okay"; + }; +}; + +&mmc0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@0 { + bus-width = <4>; + cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; + cd-inverted; + }; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ + flash@0 { + compatible = "mxicy,mx25u4035", "jedec,spi-nor"; + spi-max-frequency = <33000000>; + reg = <0>; + }; +}; + +&ssc0 { + atmel,clk-from-rk-pin; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pmc PMC_TYPE_SYSTEM 10>; + clock-names = "mclk"; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom@57 { + compatible = "giantec,gt24c32a", "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&pit { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@7 { + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_geth_int>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; +}; + +&macb1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>; + interrupt-parent = <&pioC>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi new file mode 100644 index 000000000000..bea920b192b6 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + panel: panel { + compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92"; + backlight = <&backlight>; + power-supply = <&vcc_lcd_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + vcc_lcd_reg: fixedregulator_lcd { + compatible = "regulator-fixed"; + regulator-name = "VCC LCM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; +}; + +&pinctrl { + board { + pinctrl_lcd_ctp_int: lcd_ctp_int { + atmel,pins = + ; + }; + }; +}; + +&i2c1 { + status = "okay"; + + ft5426@38 { + compatible = "focaltech,ft5426", "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_ctp_int>; + + interrupt-parent = <&pioC>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&hlcdc { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-foxg20.dts b/arch/arm/boot/dts/microchip/at91-foxg20.dts new file mode 100644 index 000000000000..9dfd5de808d1 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-foxg20.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board + * + * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) + * + * Copyright (C) 2013 Douglas Gilbert + */ +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "Acme Systems FoxG20"; + compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@1 { + reg = <1>; + bus-width = <4>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + >; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + usart2: serial@fffb8000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usart3: serial@fffd0000 { + status = "okay"; + }; + + uart0: serial@fffd4000 { + status = "okay"; + }; + + uart1: serial@fffd8000 { + status = "okay"; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + ; + }; + }; + + mmc0_slot1 { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + ; /* CD pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* TWCK (SCL), open drain */ + }; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + i2c-gpio,delay-us = <5>; /* ~85 kHz */ + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + /* red LED marked "PC7" near mini USB (device) receptacle */ + user_led { + label = "user_led"; + gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button { + label = "Button"; + gpios = <&pioC 4 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-gatwick.dts b/arch/arm/boot/dts/microchip/at91-gatwick.dts new file mode 100644 index 000000000000..551300fd7746 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-gatwick.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-gatwick.dts - Device Tree file for the Gatwick board + * + * Copyright (C) 2018 Laird + * + */ +/dts-v1/; +#include "at91-wb50n.dtsi" +#include + +/ { + model = "Laird Workgroup Bridge 50N - Project Gatwick"; + compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&pioE 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-ethernet { + label = "gatwick:yellow:ethernet"; + gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-wifi { + label = "gatwick:green:wifi"; + gpios = <&pioA 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-ble { + label = "gatwick:blue:ble"; + gpios = <&pioA 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-lora { + label = "gatwick:orange:lora"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-blank { + label = "gatwick:green:blank"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-user { + label = "gatwick:yellow:user"; + gpios = <&pioA 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&pinctrl { + board { + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; /* PE31 GPIO with pullup deglitch */ + }; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +/* FTDI USART */ +&usart0 { + status = "okay"; +}; + +/* GPS USART */ +&usart1 { + pinctrl-0 = <&pinctrl_usart1>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + spidev@0 { + compatible = "semtech,sx1301"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&usb1 { + status = "okay"; + /delete-property/atmel,oc-gpio; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox.dts b/arch/arm/boot/dts/microchip/at91-kizbox.dts new file mode 100644 index 000000000000..307663b4eec2 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizbox.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board + * + * Copyright (C) 2012-2014 Boris BREZILLON + * 2014-2015 Gaël PORTAY + */ +/dts-v1/; +#include "at91sam9g20.dtsi" +#include + +/ { + model = "Overkiz Kizbox"; + compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = &dbgu; + }; + + memory@20000000 { + reg = <0x20000000 0x2000000>; + }; + + clocks { + main_xtal { + clock-frequency = <18432000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "PB_RST"; + gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + + button-user { + label = "PB_USER"; + gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; + linux,code = <0x101>; + wakeup-source; + }; + }; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + label = "pwm:green:network"; + pwms = <&tcb1_pwm1 0 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + led-2 { + label = "pwm:red:network"; + pwms = <&tcb1_pwm2 0 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + led-3 { + label = "pwm:green:user"; + pwms = <&tcb1_pwm0 0 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + led-4 { + label = "pwm:red:user"; + pwms = <&tcb1_pwm0 1 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; +}; + +&tcb1 { + tcb1_pwm0: pwm@0 { + compatible = "atmel,tcb-pwm"; + reg = <0>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa0 &pinctrl_tcb1_tiob0>; + }; + + tcb1_pwm1: pwm@1 { + compatible = "atmel,tcb-pwm"; + reg = <1>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa1>; + }; + + tcb1_pwm2: pwm@2 { + compatible = "atmel,tcb-pwm"; + reg = <2>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa2>; + }; +}; + +&ebi { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; +}; + +&macb0 { + phy-mode = "mii"; + pinctrl-0 = <&pinctrl_macb_rmii + &pinctrl_macb_rmii_mii_alt>; + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&watchdog { + timeout-sec = <15>; + atmel,max-heartbeat-sec = <16>; + atmel,min-heartbeat-sec = <0>; + status = "okay"; +}; + +&usb0 { + num-ports = <1>; + status = "okay"; +}; + +&i2c_gpio0 { + status = "okay"; + + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox2-2.dts b/arch/arm/boot/dts/microchip/at91-kizbox2-2.dts new file mode 100644 index 000000000000..cab8b3579efa --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizbox2-2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-kizbox2-2.dts - Device Tree file for the Kizbox2 with + * two head board + * + * Copyright (C) 2015 Overkiz SAS + * + * Authors: Antoine Aubert + * Kévin Raymond + */ +/dts-v1/; +#include "at91-kizbox2-common.dtsi" + +/ { + model = "Overkiz Kizbox 2 with two heads"; + compatible = "overkiz,kizbox2-2", "atmel,sama5d31", + "atmel,sama5d3", "atmel,sama5"; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi new file mode 100644 index 000000000000..e5e21dff882f --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-kizbox2_common.dtsi - Device Tree Include file for + * Overkiz Kizbox 2 family SoC + * + * Copyright (C) 2014-2018 Overkiz SAS + * + * Authors: Antoine Aubert + * Gaël Portay + * Kévin Raymond + */ +#include "sama5d31.dtsi" + +/ { + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = &dbgu; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-prog { + label = "PB_PROG"; + gpios = <&pioE 27 GPIO_ACTIVE_LOW>; + linux,code = <0x102>; + wakeup-source; + }; + + button-reset { + label = "PB_RST"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x100>; + wakeup-source; + }; + + button-user { + label = "PB_USER"; + gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; + linux,code = <0x101>; + wakeup-source; + }; + }; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + label = "pwm:blue:user"; + pwms = <&pwm0 2 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "none"; + }; + + led-2 { + label = "pwm:green:user"; + pwms = <&pwm0 1 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + led-3 { + label = "pwm:red:user"; + pwms = <&pwm0 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "okay"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG1 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vddana_reg: LDO_REG2 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vled_reg: LDO_REG3 { + regulator-name = "VLED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v8_rf_reg: LDO_REG4 { + regulator-name = "V3V8_RF"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-always-on; + }; + }; + }; +}; + +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&usart1 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&usart2 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 + &pinctrl_pwm0_pwmh1_1 + &pinctrl_pwm0_pwmh2_0>; + status = "okay"; +}; + +&adc0 { + atmel,adc-vref = <3333>; + status = "okay"; +}; + +&macb1 { + phy-mode = "rmii"; + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +/* WMBUS (inverted with IO in the latest schematic) */ +&pinctrl_usart0 { + atmel,pins = + ; +}; + +/* RTS */ +&pinctrl_usart1 { + atmel,pins = + ; +}; + +/* IO (inverted with WMBUS in the latest schematic) */ +&pinctrl_usart2 { + atmel,pins = + ; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts new file mode 100644 index 000000000000..fec7269088d1 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board + * + * Copyright (C) 2018 Overkiz SAS + * + * Authors: Dorian Rocipon + * Kevin Carli + * Mickael Gardet + */ +/dts-v1/; +#include "at91-kizbox3_common.dtsi" + +/ { + model = "Overkiz KIZBOX3-HS"; + compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5"; + + led-controller-1 { + status = "okay"; + + led-1 { + status = "okay"; + }; + + led-2 { + status = "okay"; + }; + + led-3 { + status = "okay"; + }; + + led-4 { + status = "okay"; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_red + &pinctrl_led_white>; + status = "okay"; + + led-5 { + label = "pio:red:user"; + gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-6 { + label = "pio:white:user"; + gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default" , "default", "default", + "default", "default" ; + pinctrl-0 = <&pinctrl_key_gpio_default>; + pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>; + pinctrl-2 = <&pinctrl_pio_io_boot + &pinctrl_pio_io_reset + &pinctrl_pio_io_test_radio>; + pinctrl-3 = <&pinctrl_pio_zbe_test_radio + &pinctrl_pio_zbe_rst>; + pinctrl-4 = <&pinctrl_pio_input>; + + switch-1 { + label = "SW1"; + gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; + linux,code = <0x101>; + wakeup-source; + }; + + switch-2 { + label = "SW2"; + gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>; + linux,code = <0x102>; + wakeup-source; + }; + + switch-3 { + label = "SW3"; + gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + wakeup-source; + }; + + switch-7 { + label = "SW7"; + gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>; + linux,code = <0x107>; + wakeup-source; + }; + + switch-8 { + label = "SW8"; + gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>; + linux,code = <0x108>; + wakeup-source; + }; + }; + + gpios { + compatible = "gpio"; + status = "okay"; + + rf_on { + label = "rf on"; + gpio = <&pioA PIN_PC19 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + wifi_on { + label = "wifi on"; + gpio = <&pioA PIN_PC20 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + zbe_test_radio { + label = "zbe test radio"; + gpio = <&pioA PIN_PB21 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + zbe_rst { + label = "zbe rst"; + gpio = <&pioA PIN_PB25 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + io_reset { + label = "io reset"; + gpio = <&pioA PIN_PB30 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + io_test_radio { + label = "io test radio"; + gpio = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + io_boot_0 { + label = "io boot 0"; + gpio = <&pioA PIN_PC11 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + io_boot_1 { + label = "io boot 1"; + gpio = <&pioA PIN_PC17 GPIO_ACTIVE_HIGH>; + output; + init-low; + }; + + verbose_bootloader { + label = "verbose bootloader"; + gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; + input; + }; + + nail_bed_detection { + label = "nail bed detection"; + gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>; + input; + }; + + id_usba { + label = "id usba"; + gpio = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; + input; + }; + }; +}; + +&pioA { + pinctrl_key_gpio_default: key_gpio_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_gpio { + pinctrl_pio_rf: gpio_rf { + pinmux = ; + bias-disable; + }; + pinctrl_pio_wifi: gpio_wifi { + pinmux = ; + bias-disable; + }; + pinctrl_pio_io_boot: gpio_io_boot { + pinmux = + , + ; + bias-disable; + }; + pinctrl_pio_io_test_radio: gpio_io_test_radio { + pinmux = ; + bias-disable; + }; + pinctrl_pio_zbe_test_radio: gpio_zbe_test_radio { + pinmux = ; + bias-disable; + }; + pinctrl_pio_zbe_rst: gpio_zbe_rst { + pinmux = ; + bias-disable; + }; + /* stm32 reset must be open drain (internal pull up) */ + pinctrl_pio_io_reset: gpio_io_reset { + pinmux = ; + bias-disable; + drive-open-drain; + output-low; + }; + pinctrl_pio_input: gpio_input { + pinmux = + , + , + ; + bias-disable; + }; + }; + + pinctrl_leds { + pinctrl_led_red: led_red { + pinmux = ; + bias-disable; + }; + pinctrl_led_white: led_white { + pinmux = ; + bias-disable; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&flx0 { + status = "okay"; + + uart5: serial@200 { + status = "okay"; + }; +}; + +&flx3 { + status = "okay"; + uart8: serial@200 { + status = "okay"; + }; +}; + +&flx4 { + status = "okay"; + + i2c6: i2c@600 { + status = "okay"; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi new file mode 100644 index 000000000000..465664628419 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3 + * family SoC boards + * + * Copyright (C) 2018 Overkiz SAS + * + * Authors: Dorian Rocipon + * Kevin Carli + * Mickael Gardet + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include +#include +#include + +/ { + model = "Overkiz Kizbox3"; + compatible = "overkiz,kizbox3", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart8; + }; + + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = "serial1:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + vdd_adc_vddana: supply_3v3_ana { + compatible = "regulator-fixed"; + regulator-name = "adc-vddana"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_adc_vref: supply_3v3_ref { + compatible = "regulator-fixed"; + regulator-name = "adc-vref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + led-controller-1 { + compatible = "pwm-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm_h0 + &pinctrl_pwm0_pwm_h1 + &pinctrl_pwm0_pwm_h2 + &pinctrl_pwm0_pwm_h3>; + status = "disabled"; + + led-1 { + label = "pwm:red:user"; + pwms = <&pwm0 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + status = "disabled"; + }; + + led-2 { + label = "pwm:green:user"; + pwms = <&pwm0 1 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + status = "disabled"; + }; + + led-3 { + label = "pwm:blue:user"; + pwms = <&pwm0 2 10000000 0>; + max-brightness = <255>; + status = "disabled"; + }; + + led-4 { + label = "pwm:white:user"; + pwms = <&pwm0 3 10000000 0>; + max-brightness = <255>; + status = "disabled"; + }; + }; +}; + +&ebi { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + reg = <0x3 0x0 0x800000>; + + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + u-boot@20000 { + label = "u-boot"; + reg = <0x20000 0x140000>; + }; + + u-boot-factory@160000 { + label = "u-boot-factory"; + reg = <0x160000 0x140000>; + }; + + ubi@2A0000 { + label = "ubi"; + reg = <0x2A0000 0x7D60000>; + }; + }; + + }; +}; + +&rtc { + status = "okay"; +}; + +&pioA { + pinctrl_ebi_nand_addr: ebi-addr-1 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_usart { + pinctrl_usart_0: usart0-0 { + pinmux = < PIN_PB26__URXD0>, ; + bias-disable; + }; + pinctrl_usart_1: usart1-0 { + pinmux = < PIN_PD2__URXD1>, ; + bias-disable; + }; + pinctrl_usart_2: usart2-0 { + pinmux = < PIN_PD4__URXD2>, ; + bias-disable; + }; + pinctrl_usart_3: usart3-0 { + pinmux = < PIN_PC12__URXD3>, ; + bias-disable; + }; + pinctrl_usart_4: usart4-0 { + pinmux = < PIN_PB3__URXD4>, ; + bias-disable; + }; + pinctrl_flx0_default: flx0_usart_default { + pinmux = , //TX + ; //RX + bias-disable; + }; + pinctrl_flx3_default: flx3_usart_default { + pinmux = , //RX + ; //TX + bias-disable; + }; + }; + + pinctrl_flx4_default: flx4_i2c6_default { + pinmux = , //DATA + ; //CLK + bias-disable; + drive-open-drain; + }; + + pinctrl_pwm0 { + pinctrl_pwm0_pwm_h0: pwm0_pwm_h0 { + pinmux = ; + bias-disable; + }; + pinctrl_pwm0_pwm_h1: pwm0_pwmh1 { + pinmux = ; + bias-disable; + }; + pinctrl_pwm0_pwm_h2: pwm0_pwm_h2 { + pinmux = ; + bias-disable; + }; + pinctrl_pwm0_pwm_h3: pwm0_pwm_h3 { + pinmux = ; + bias-disable; + }; + }; + + pinctrl_adc { + pinctrl_adc2: adc2 { + pinmux = ; + bias-disable; + }; + pinctrl_adc3: adc3 { + pinmux = ; + bias-disable; + }; + pinctrl_adc4: adc4 { + pinmux = ; + bias-disable; + }; + pinctrl_adc5: adc5 { + pinmux = ; + bias-disable; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart_0>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +/* debug uart */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart_1>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart_2>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart_3>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart_4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "disabled"; + + uart5: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "disabled"; + + uart8: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "disabled"; + + i2c6: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "disabled"; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + }; +}; + +&watchdog { + status = "okay"; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc2 + &pinctrl_adc3 + &pinctrl_adc4 + &pinctrl_adc5>; + + vddana-supply = <&vdd_adc_vddana>; + vref-supply = <&vdd_adc_vref>; + status = "disabled"; +}; + +&securam { + export; + + /* export overkiz u-boot mode/version and factory */ + uboot@1400 { + reg = <0x1400 0x20>; + export; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts new file mode 100644 index 000000000000..81c29ca5cc1b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini + * base board + * + * Copyright (C) 2015 Overkiz SAS + * Author: Antoine Aubert + * Kévin Raymond + */ +/dts-v1/; +#include "at91-kizboxmini-common.dtsi" + +/ { + model = "Overkiz Kizbox Mini"; + compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25", + "atmel,at91sam9x5", "atmel,at91sam9"; +}; + +&pinctrl_usart0 { + atmel,pins = + ; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi new file mode 100644 index 000000000000..42640fe6b6d0 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board + * + * Copyright (C) 2014-2018 Overkiz SAS + * Author: Antoine Aubert + * Gaël Portay + * Kévin Raymond + * Dorian Rocipon + */ +#include "at91sam9g25.dtsi" + +/ { + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = &dbgu; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + main_xtal { + clock-frequency = <12000000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + adc_op_clk { + status = "disabled"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + key-prog { + label = "PB_PROG"; + gpios = <&pioC 17 GPIO_ACTIVE_LOW>; + linux,code = <0x102>; + wakeup-source; + }; + + key-reset { + label = "PB_RST"; + gpios = <&pioC 16 GPIO_ACTIVE_LOW>; + linux,code = <0x100>; + wakeup-source; + }; + }; + + leds: led-controller-1 { + compatible = "pwm-leds"; + + led_blue: led-1 { + label = "pwm:blue:user"; + pwms = <&pwm0 2 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "none"; + status = "disabled"; + }; + + led_green: led-2 { + label = "pwm:green:user"; + pwms = <&pwm0 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + led_red: led-3 { + label = "pwm:red:user"; + pwms = <&pwm0 1 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm0_1 + &pinctrl_pwm0_pwm1_1 + &pinctrl_pwm0_pwm2_1>; + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&adc0 { + status = "disabled"; +}; + +&rtc { + status = "disabled"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_addr_nand + &pinctrl_ebi_data_0_7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; +}; + +&usb0 { + num-ports = <1>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts new file mode 100644 index 000000000000..c07d3076a9bc --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015-2018 Overkiz SAS + * Author: Mickael Gardet + * Kévin Raymond + */ +/dts-v1/; +#include "at91-kizboxmini-common.dtsi" + +/ { + model = "Overkiz Kizbox Mini Mother Board"; + compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25", + "atmel,at91sam9x5", "atmel,at91sam9"; +}; + +&usb0 { + num-ports = <2>; +}; + +&rtc { + status = "okay"; +}; + +&led_blue { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts new file mode 100644 index 000000000000..ab50f4d22387 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015-2018 Overkiz SAS + * Author: Mickael Gardet + * Kévin Raymond + */ +/dts-v1/; +#include "at91-kizboxmini-common.dtsi" + +/ { + model = "Overkiz Kizbox Mini RailDIN"; + compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25", + "atmel,at91sam9x5", "atmel,at91sam9"; + + clocks { + adc_op_clk { + status = "okay"; + }; + }; +}; + +&pinctrl { + adc0 { + pinctrl_adc0_ad5: adc0_ad5-0 { + /* pull-up disable */ + atmel,pins = ; + }; + }; +}; + +&usart0 { + status = "disabled"; +}; + +&rtc { + status = "okay"; +}; + +&led_blue { + status = "okay"; +}; + +&adc0 { + atmel,adc-vref = <2500>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_ad5>; + atmel,adc-channels-used = <0x0020>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-linea.dtsi b/arch/arm/boot/dts/microchip/at91-linea.dtsi new file mode 100644 index 000000000000..533a440d5583 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-linea.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module. + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin + */ + +#include "sama5d31.dtsi" + +/ { + compatible = "axentia,linea", + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-lmu5000.dts b/arch/arm/boot/dts/microchip/at91-lmu5000.dts new file mode 100644 index 000000000000..f8863d7c0798 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-lmu5000.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree file for CalAmp LMU5000 board + * + * Copyright (C) 2013 Adam Porter + */ + +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "CalAmp LMU5000"; + compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + status = "okay"; + + nand_controller: nand-controller { + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + kernel@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + user1@4000000 { + label = "user1"; + reg = <0x4000000 0x2000000>; + }; + + user2@6000000 { + label = "user2"; + reg = <0x6000000 0x2000000>; + }; + }; + }; + }; +}; + +&macb0 { + phy-mode = "mii"; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = ; + }; + }; + + usb0 { + pinctrl_usb1_vbus_gpio: usb0_vbus_gpio { + atmel,pins = ; + }; + }; +}; + +&ssc0 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usart0 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usb0 { + num-ports = <2>; + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus_gpio>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-natte.dtsi b/arch/arm/boot/dts/microchip/at91-natte.dtsi new file mode 100644 index 000000000000..49f0a0c46cde --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-natte.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * at91-natte.dts - Device Tree include file for the Natte board + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin + */ + +/ { + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, + <&ioexp 1 GPIO_ACTIVE_HIGH>, + <&ioexp 2 GPIO_ACTIVE_HIGH>; + }; + + batntc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 5>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "batntc0", "batntc1", "batntc2", "batntc3", + "batntc4", "batntc5", "batntc6", "batntc7"; + }; + + batv-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 6>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "batv0", "batv1", "batv2", "batv3", + "batv4", "batv5", "batv6", "batv7"; + }; + + iout-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 7>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "iout0", "iout1", "iout2", "iout3", + "iout4", "iout5", "iout6", "iout7"; + }; + + i2c-mux { + compatible = "i2c-mux"; + mux-locked; + i2c-parent = <&i2c0>; + mux-controls = <&mux>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + ioexp: ioexp@20 { + #gpio-cells = <2>; + compatible = "semtech,sx1502q"; + reg = <0x20>; + + gpio-controller; + ngpios = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio3_cfg_pins>; + + gpio3_cfg_pins: gpio3_cfg { + pins = "gpio3"; + bias-pull-up; + }; + }; + + adc: adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@5 { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <4>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts new file mode 100644 index 000000000000..f71377c9b757 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin + */ +/dts-v1/; +#include "at91-linea.dtsi" +#include "at91-natte.dtsi" + +/ { + model = "Axentia Linea-Nattis v2 Natte v2"; + compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "Wakeup"; + linux,code = <10>; + wakeup-source; + gpios = <&pioB 27 GPIO_ACTIVE_LOW>; + }; + }; + + panel_reg: panel-regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-VCC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + bl_reg: backlight-regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-VDD"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + panel_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <40>; + + power-supply = <&bl_reg>; + enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_blon>; + }; + + panel: panel { + compatible = "sharp,lq150x1lg11", "panel-lvds"; + + backlight = <&panel_bl>; + power-supply = <&panel_reg>; + + width-mm = <304>; + height-mm = <228>; + + data-mapping = "jeida-18"; + + panel-timing { + // 1024x768 @ 60Hz (typical) + clock-frequency = <50000000 65000000 80000000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <48 88 88>; + hback-porch = <96 168 168>; + hsync-len = <32 64 64>; + vsync-len = <3 13 74>; + vfront-porch = <3 13 74>; + vback-porch = <3 12 74>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,ds90c185", "lvds-encoder"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&hlcdc_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "nattis-tfa9879"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,widgets = "Line", "Line Out Jack"; + simple-audio-card,routing = "Line Out Jack", "LINEOUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssc0>; + }; + + simple-audio-card,codec { + sound-dai = <&>; + }; + }; +}; + +&pinctrl { + nattis { + pinctrl_usba_vbus: usba_vbus { + atmel,pins = ; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = ; + }; + + pinctrl_lvds_prlud0: lvds_prlud0 { + atmel,pins = ; + }; + + pinctrl_lvds_hipow0: lvds_hipow0 { + atmel,pins = ; + }; + + pinctrl_blon: blon { + atmel,pins = ; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <100000>; + + temp@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + smbus-timeout-disable; + }; + + eeprom@50 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + amp: amplifier@6c { + compatible = "nxp,tfa9879"; + reg = <0x6c>; + #sound-dai-cells = <0>; + }; +}; + +&ssc0 { + status = "okay"; + + atmel,clk-from-rk-pin; + #sound-dai-cells = <0>; +}; + +&hlcdc { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; + + port@0 { + hlcdc_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <16>; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 + &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_cd>; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cd-inverted; + }; +}; + +&usart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + atmel,use-dma-rx; +}; + +&nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + barebox@40000 { + label = "barebox"; + reg = <0x40000 0x60000>; + }; + + bareboxenv@c0000 { + label = "bareboxenv"; + reg = <0xc0000 0x40000>; + }; + + bareboxenv2@100000 { + label = "bareboxenv2"; + reg = <0x100000 0x40000>; + }; + + oftree@180000 { + label = "oftree"; + reg = <0x180000 0x20000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; +}; + +&dbgu { + status = "okay"; + + atmel,use-dma-rx; +}; + +&usb0 { + status = "okay"; + + atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; +}; diff --git a/arch/arm/boot/dts/microchip/at91-q5xr5.dts b/arch/arm/boot/dts/microchip/at91-q5xr5.dts new file mode 100644 index 000000000000..9cf60b6f695c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-q5xr5.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree file for Exegin Q5xR5 board + * + * Copyright (C) 2014 Owen Kirby + */ + +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "Exegin Q5x (rev5)"; + compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2"; + }; + + memory { + reg = <0x20000000 0x0>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + status = "okay"; + + flash: flash@0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x1000000 0x800000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + kernel@0 { + label = "kernel"; + reg = <0x0 0x200000>; + }; + + rootfs@200000 { + label = "rootfs"; + reg = <0x200000 0x600000>; + }; + }; + }; +}; + +&macb0 { + phy-mode = "mii"; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; + }; + + pinctrl_spi0_npcs0: spi0_npcs0 { + atmel,pins = ; + }; + + pinctrl_spi0_npcs1: spi0_npcs1 { + atmel,pins = ; + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; + }; + + pinctrl_spi1_npcs0: spi1_npcs0 { + atmel,pins = ; + }; + + pinctrl_spi1_npcs1: spi1_npcs1 { + atmel,pins = ; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>; + cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + at91boot@0 { + label = "at91boot"; + reg = <0x0 0x4000>; + }; + + uenv@4000 { + label = "uboot-env"; + reg = <0x4000 0x4000>; + }; + + uboot@8000 { + label = "uboot"; + reg = <0x8000 0x3E000>; + }; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>; + status = "okay"; +}; + +&usart0 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; +}; + +&usb0 { + num-ports = <2>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-qil_a9260.dts b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts new file mode 100644 index 000000000000..9d26f9996348 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board + * + * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9260.dtsi" +/ { + model = "Calao QIL A9260"; + compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + pinctrl-0 = + <&pinctrl_usart1 + &pinctrl_usart1_rts + &pinctrl_usart1_cts>; + status = "okay"; + }; + + usart2: serial@fffb8000 { + pinctrl-0 = + <&pinctrl_usart2 + &pinctrl_usart2_rts + &pinctrl_usart2_cts>; + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + spi0: spi@fffc8000 { + status = "okay"; + cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; + + m41t94@0 { + compatible = "st,m41t94"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@a0000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@c0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4c0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7cc0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-user { + label = "user_pb"; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; + linux,code = <28>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts new file mode 100644 index 000000000000..2fb51b9aca2a --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board + * + * Copyright (C) 2016 Raashid Muhammed + */ +/dts-v1/; +#include "at91sam9260.dtsi" + +/ { + model = "Olimex sam9-l9260"; + compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; + }; + }; + + macb0: ethernet@fffc4000 { + pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + spi0: spi@fffc8000 { + cs-gpios = <&pioC 11 0>, <0>, <0>, <0>; + status = "okay"; + + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* WP pin */ + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + + usb0: ohci@500000 { + status = "okay"; + }; + + }; + + i2c-gpio-0 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "sam9-l9260:yellow:pwr"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + }; + + status_led { + label = "sam9-l9260:green:status"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts new file mode 100644 index 000000000000..cb86a3a170ce --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Durai Manickam KR + */ +/dts-v1/; +#include "sam9x60.dtsi" +#include + +/ { + model = "Microchip SAM9X60 Curiosity"; + compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c6; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "PB_USER"; + gpios = <&pioA 29 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-red { + label = "red"; + gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioD 19 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + + vdd_1v8: regulator-0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; + + vdd_1v15: regulator-1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <1150000>; + regulator-name = "VDD_1V15"; + }; + + vdd1_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD1_3V3"; + }; +}; + +&adc { + vddana-supply = <&vdd1_3v3>; + vref-supply = <&vdd1_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + status = "disabled"; /* Conflict with dbgu. */ +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + status = "okay"; +}; + +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "okay"; /* Conflict with can0. */ +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_lsb>; + status = "okay"; + + nand_controller: nand-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label = "U-Boot Env Redundant"; + reg = <0x100000 0x40000>; + }; + + ubootenv@140000 { + label = "U-Boot Env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c0: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + #address-cells = <1>; + #size-cells = <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + }; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "disabled"; + }; +}; + +&flx7 { + atmel,flexcom-mode = ; + status = "okay"; + + uart7: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx7_default>; + status = "okay"; + }; +}; + +&macb0 { + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + status = "okay"; + + ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&pinctrl { + adc { + pinctrl_adc_default: adc-default { + atmel,pins = ; + }; + + pinctrl_adtrg_default: adtrg-default { + atmel,pins = ; + }; + }; + + can0 { + pinctrl_can0_rx_tx: can0-rx-tx { + atmel,pins = + ; /* Enable CAN Transceivers */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1-rx-tx { + atmel,pins = + ; /* Enable CAN Transceivers */ + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = ; + }; + }; + + ebi { + pinctrl_ebi_data_lsb: ebi-data-lsb { + atmel,pins = + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-nand { + atmel,pins = + ; + }; + }; + + flexcom { + pinctrl_flx0_default: flx0-twi { + atmel,pins = + ; + }; + + pinctrl_flx6_default: flx6-twi { + atmel,pins = + ; + }; + + pinctrl_flx7_default: flx7-usart { + atmel,pins = + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: pinctrl-key-gpio { + atmel,pins = ; + }; + }; + + leds { + pinctrl_gpio_leds: gpio-leds { + atmel,pins = ; + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0-rmii-0 { + atmel,pins = + ; /* PB10 periph A */ + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + pwm0 { + pinctrl_pwm0_0: pwm0-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_1: pwm0-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_2: pwm0-2 { + atmel,pins = ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins = + ; /* PA20 DAT3 periph A with pullup */ + }; + + pinctrl_sdmmc0_cd: sdmmc0-cd { + atmel,pins = + ; + }; + }; + + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins = + ; /* PA4 DAT3 periph B with pullup */ + }; + }; + + usb0 { + pinctrl_usba_vbus: usba-vbus { + atmel,pins = ; + }; + }; + + usb1 { + pinctrl_usb_default: usb-default { + atmel,pins = ; + }; + }; +}; /* pinctrl */ + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; + cd-gpios = <&pioA 25 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + disable-wp; + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 18 GPIO_ACTIVE_HIGH + &pioD 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts b/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts new file mode 100644 index 000000000000..5cd593028aff --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M + */ +/dts-v1/; +#include "sam9x60.dtsi" +#include + +/ { + model = "Microchip SAM9X60-EK"; + compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c6; + serial1 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-1 { + label = "SW1"; + gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + status = "okay"; /* Conflict with pwm0. */ + + red { + label = "red"; + gpios = <&pioB 11 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "green"; + gpios = <&pioB 12 GPIO_ACTIVE_HIGH>; + }; + + blue { + label = "blue"; + gpios = <&pioB 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_1v8: fixed-regulator-vdd_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v15: fixed-regulator-vdd_1v15 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + vdd1_3v3: fixed-regulator-vdd1_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD1_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd2_3v3: regulator-fixed-vdd2_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc { + vddana-supply = <&vdd1_3v3>; + vref-supply = <&vdd1_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + status = "disabled"; /* Conflict with dbgu. */ +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + status = "okay"; +}; + +&classd { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_classd_default>; + atmel,pwm-type = "diff"; + atmel,non-overlap-time = <10>; + status = "okay"; +}; + +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "okay"; /* Conflict with can0. */ +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; + status = "okay"; + + nand_controller: nand-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label = "U-Boot Env Redundant"; + reg = <0x100000 0x40000>; + }; + + ubootenv@140000 { + label = "U-Boot Env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c0: i2c@600 { + #address-cells = <1>; + #size-cells = <0>; + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + status = "okay"; + }; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "disabled"; + + spi4: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "disabled"; + }; +}; + +&flx5 { + atmel,flexcom-mode = ; + status = "okay"; + + uart5: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx5_default>; + status = "okay"; + }; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + #address-cells = <1>; + #size-cells = <0>; + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + gpio_exp: mcp23008@20 { + compatible = "microchip,mcp23008"; + reg = <0x20>; + }; + }; +}; + +&gpbr { + status = "okay"; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_default>; + #sound-dai-cells = <0>; + status = "disabled"; /* Conflict with QSPI. */ +}; + +&macb0 { + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + status = "okay"; + + ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&pinctrl { + adc { + pinctrl_adc_default: adc_default { + atmel,pins = ; + }; + + pinctrl_adtrg_default: adtrg_default { + atmel,pins = ; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = ; + }; + }; + + i2s { + pinctrl_i2s_default: i2s { + atmel,pins = + ; /* I2SMCK */ + }; + }; + + qspi { + pinctrl_qspi: qspi { + atmel,pins = + ; + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_0_15: ebi-data-msb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + ; + }; + }; + + flexcom { + pinctrl_flx0_default: flx0_twi { + atmel,pins = + ; + }; + + pinctrl_flx4_default: flx4_spi { + atmel,pins = + ; + }; + + pinctrl_flx5_default: flx5_uart { + atmel,pins = + ; + }; + + pinctrl_flx6_default: flx6_twi { + atmel,pins = + ; + }; + }; + + classd { + pinctrl_classd_default: classd { + atmel,pins = + ; + }; + }; + + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* Enable CAN Transceivers */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* Enable CAN Transceivers */ + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + ; /* PB10 periph A */ + }; + }; + + pwm0 { + pinctrl_pwm0_0: pwm0_0 { + atmel,pins = ; + }; + + pinctrl_pwm0_1: pwm0_1 { + atmel,pins = ; + }; + + pinctrl_pwm0_2: pwm0_2 { + atmel,pins = ; + }; + + pinctrl_pwm0_3: pwm0_3 { + atmel,pins = ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins = + ; /* PA20 DAT3 periph A with pullup */ + }; + pinctrl_sdmmc0_cd: sdmmc0_cd { + atmel,pins = + ; + }; + }; + + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins = + ; /* PA4 DAT3 periph B with pullup */ + }; + }; + + gpio_keys { + pinctrl_key_gpio_default: pinctrl_key_gpio { + atmel,pins = ; + }; + }; + + usb0 { + pinctrl_usba_vbus: usba_vbus { + atmel,pins = ; + }; + }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = ; + }; + }; + + leds { + pinctrl_gpio_leds: gpio_leds { + atmel,pins = ; + }; + }; +}; /* pinctrl */ + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>; + status = "disabled"; /* Conflict with leds. */ +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; + status = "okay"; + cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + no-1-8-v; + non-removable; + status = "disabled"; /* Conflict with flx4. */ +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; /* Conflict with i2s. */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "qspi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "qspi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "qspi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "qspi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "qspi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "qspi: kernel"; + reg = <0x200000 0x600000>; + }; + }; +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 15 GPIO_ACTIVE_HIGH + &pioD 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi new file mode 100644 index 000000000000..95ecb7d040a8 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board + * + * Copyright (c) 2017, Microchip Technology Inc. + * 2017 Cristian Birsan + * 2017 Claudiu Beznea + */ +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include + +/ { + model = "Atmel SAMA5D27 SoM1"; + compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + i2c0 = &i2c0; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + ahb { + sdmmc0: sdio-host@a0000000 { + microchip,sdcal-inverted; + }; + + apb { + qspi1: spi@f0024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; + }; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default>; + #address-cells = <1>; + #size-cells = <0>; + phy-mode = "rmii"; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioA>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_phy_irq>; + }; + }; + + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + at24@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + }; + }; + + pinctrl@fc038000 { + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_qspi1_default: qspi1_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts new file mode 100644 index 000000000000..52ddd0571f1c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board + * + * Copyright (c) 2017, Microchip Technology Inc. + * 2016 Nicolas Ferre + * 2017 Cristian Birsan + * 2017 Claudiu Beznea + */ +/dts-v1/; +#include "at91-sama5d27_som1.dtsi" +#include +#include +#include + +/ { + model = "Atmel SAMA5D27 SOM1 EK"; + compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart1; /* DBGU */ + serial1 = &uart4; /* mikro BUS 1 */ + serial2 = &uart2; /* mikro BUS 2 */ + i2c1 = &i2c1; + i2c2 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ahb { + usb0: gadget@300000 { + atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ + &pioA PIN_PA27 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@500000 { + status = "okay"; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + mmc-ddr-3_3v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; + }; + + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; + }; + + apb { + isc: isc@f0008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>; + }; + + qspi1: spi@f0024000 { + status = "okay"; + }; + + spi0: spi@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "okay"; + }; + + macb0: ethernet@f8008000 { + status = "okay"; + }; + + tcb0: timer@f800c000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + uart1: serial@f8020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + uart2: serial@f8024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + pwm0: pwm@f802c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; + status = "disabled"; /* Conflict with leds. */ + }; + + flx1: flexcom@f8038000 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c3: i2c@600 { + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_mikrobus_i2c>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&pioA PIN_PA24 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PA23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + }; + }; + + shdwc@f8048010 { + debounce-delay-us = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + }; + }; + + watchdog@f8048040 { + status = "okay"; + }; + + uart3: serial@fc008000 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_default>; + status = "disabled"; /* Conflict with isc. */ + }; + + uart4: serial@fc00c000 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + status = "okay"; + }; + + flx3: flexcom@fc014000 { + atmel,flexcom-mode = ; + status = "disabled"; + + uart8: serial@200 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "disabled"; /* Conflict with isc. */ + }; + + spi5: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "disabled"; /* Conflict with isc. */ + }; + }; + + flx4: flexcom@fc018000 { + atmel,flexcom-mode = ; + status = "okay"; + + uart9: serial@200 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "disabled"; /* Conflict with spi6 and i2c6. */ + }; + + spi6: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; + status = "okay"; /* Conflict with uart5 and i2c6. */ + }; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "disabled"; /* Conflict with uart5 and spi6. */ + }; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + }; + + adc: adc@fc030000 { + vddana-supply = <&vddana>; + vref-supply = <&advref>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an &pinctrl_mikrobus2_an>; + + status = "okay"; + }; + + pinctrl@fc038000 { + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx3_default: flx3_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = , + ; + bias-disable; + }; + + + pinctrl_isc_base: isc_base { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_isc_data_8bit: isc_data_8bit { + pinmux = , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_isc_data_9_10: isc_data_9_10 { + pinmux = , + ; + bias-disable; + }; + + pinctrl_isc_data_11_12: isc_data_11_12 { + pinmux = , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + ck_cd_vddsel { + pinmux = , + , + ; + bias-disable; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + conf-ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_spi0_default: spi0_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_uart1_default: uart1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_uart3_default: uart3_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_an: mikrobus1_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_an: mikrobus2_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_rst: mikrobus1_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_rst: mikrobus2_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus_spi: mikrobus_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus1_pwm: mikrobus1_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_pwm: mikrobus2_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_int: mikrobus1_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_int: mikrobus2_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus2_uart: mikrobus2_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus_i2c: mikrobus1_i2c { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c3_gpio: i2c3_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx4_default: flx4_uart_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + }; + + can1: can@fc050000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button { + label = "USER"; + gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* Conflict with pwm0. */ + + led-red { + label = "red"; + gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vddin_3v3: fixed-regulator-vddin_3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VDDIN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vddana: fixed-regulator-vddana { + compatible = "regulator-fixed"; + + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vddin_3v3>; + status = "okay"; + }; + + advref: fixed-regulator-advref { + compatible = "regulator-fixed"; + + regulator-name = "advref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vddana>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi new file mode 100644 index 000000000000..4617805c7748 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1 + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + * Author: Eugen Hristev + */ +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include +#include + +/ { + model = "Microchip SAMA5D27 WLSOM1"; + compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + i2c0 = &i2c0; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-wilc1000"; + reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_wilc_pwrseq>; + pinctrl-names = "default"; + }; +}; + +&flx1 { + atmel,flexcom-mode = ; + + uart6: serial@200 { + pinctrl-0 = <&pinctrl_flx1_default>; + pinctrl-names = "default"; + }; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + pinctrl-names = "default", "gpio"; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddio_ddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1200000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1200000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + }; + + vdd_core: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vdd_ddr: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&macb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default>; + #address-cells = <1>; + #size-cells = <0>; + phy-mode = "rmii"; + + ethernet-phy@0 { + reg = <0x0>; + interrupt-parent = <&pioA>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_phy_irq>; + }; +}; + +&pmc { + atmel,osc-bypass; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "disabled"; + + qspi1_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + m25p,fast-read; + status = "disabled"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + }; +}; + +&pioA { + pinctrl_flx1_default: flx1_usart_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_qspi1_default: qspi1_default { + pinmux = , + , + , + , + , + ; + bias-pull-up; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd-data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + conf-ck { + pinmux = ; + bias-disable; + }; + }; + + pinctrl_wilc_default: wilc_default { + conf-irq { + pinmux = ; + bias-disable; + }; + }; + + pinctrl_wilc_pwrseq: wilc_pwrseq { + conf-ce-nrst { + pinmux = , + ; + bias-disable; + }; + + conf-rtcclk { + pinmux = ; + bias-disable; + }; + }; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + mmc-pwrseq = <&wifi_pwrseq>; + no-1-8-v; + non-removable; + bus-width = <4>; + status = "okay"; + + wilc: wifi@0 { + reg = <0>; + compatible = "microchip,wilc1000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wilc_default>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; + clock-names = "rtc"; + interrupts = ; + interrupt-parent = <&pioA>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; + assigned-clock-rates = <32768>; + }; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts new file mode 100644 index 000000000000..e055b9e2fe34 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ +/dts-v1/; +#include "at91-sama5d27_wlsom1.dtsi" +#include + +/ { + model = "Microchip SAMA5D27 WLSOM1 EK"; + compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; /* DBGU */ + serial1 = &uart6; /* BT */ + serial2 = &uart5; /* mikro BUS 2 */ + serial3 = &uart3; /* mikro BUS 1 */ + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-1 { + label = "USER BUTTON"; + gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; + + led-red { + label = "red"; + gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc { + vddana-supply = <&vdd_3v3>; + vref-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default>; + status = "okay"; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + uart5: serial@200 { + pinctrl-0 = <&pinctrl_flx0_default>; + pinctrl-names = "default"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; +}; + +&flx1 { + status = "okay"; + + uart6: serial@200 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; +}; + +&macb0 { + status = "okay"; +}; + +&pioA { + /* + * There is no real pinmux for ADC, if the pin + * is not requested by another peripheral then + * the muxing is done when channel is enabled. + * Requesting pins for ADC is GPIO is + * encouraged to prevent conflicts and to + * disable bias in order to be in the same + * state when the pin is not muxed to the adc. + */ + pinctrl_adc_default: adc_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx0_default: flx0_usart_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-down; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + ck_cd_vddsel { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_uart3_default: uart3_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_pwm0_default: pwm0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default>; + status = "okay"; +}; + +&qspi1 { + status = "okay"; + + qspi1_flash: flash@0 { + status = "okay"; + }; +}; + +&sdmmc0 { + bus-width = <4>; + mmc-ddr-3_3v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PA10 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts new file mode 100644 index 000000000000..999adeca6f33 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Radu Pirea & Razvan Stefanescu, + * Codrin Ciubotariu , + * Cristian Birsan + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include +#include + +/ { + model = "Microchip SAMA5D2-ICP"; + compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ + serial1 = &uart1; /* mikro BUS 3 */ + serial3 = &uart3; /* mikro BUS 2 */ + serial5 = &uart7; /* flx2 */ + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-1 { + label = "USER_PB1"; + gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* conflict with pwm0 */ + + led-red { + label = "red"; + gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc { + vddana-supply = <&vdd_io_reg>; + vref-supply = <&vdd_io_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&flx0 { /* mikrobus2 spi */ + atmel,flexcom-mode = ; + status = "okay"; + + spi2: spi@400 { + dmas = <0>, <0>; + cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + switch0: ksz8563@0 { + compatible = "microchip,ksz8563"; + reg = <0>; + reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>; + + spi-max-frequency = <500000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "cpu"; + ethernet = <&macb0>; + phy-mode = "mii"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; + + uart7: serial@200 { + pinctrl-0 = <&pinctrl_flx2_default>; + pinctrl-names = "default"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; /* Conflict w/ qspi1. */ + }; +}; + +&flx3 { /* mikrobus1 spi */ + atmel,flexcom-mode = ; + status = "okay"; + + spi5: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>; + + regulators { + vdd_io_reg: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + }; + }; +}; + +&i2c0 { /* mikrobus i2c */ + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_mikrobus_i2c>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + status = "okay"; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + status = "disabled"; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + status = "disabled"; + }; +}; + +&macb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&pioA { + pinctrl_adc_default: adc_default { + pinmux = , + , + ; + bias-disable; + }; + + /* + * The ADTRG pin can work on any edge type. + * In here it's being pulled up, so need to + * connect it to ground to get an edge e.g. + * Trigger can be configured on falling, rise + * or any edge, and the pull-up can be changed + * to pull-down or left floating according to + * needs. + */ + pinctrl_adtrg_default: adtrg_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_flx4_default: flx4_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_qspi1_default: qspi1_default { + pinmux = , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + ; + bias-disable; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_mikrobus_i2c: mikrobus_i2c { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus1_an: mikrobus1_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_rst: mikrobus1_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi: mikrobus1_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus1_pwm: mikrobus1_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_int: mikrobus1_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus2_an: mikrobus2_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_rst: mikrobus2_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi: mikrobus2_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_ksz_spi_cs: ksz_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_pwm: mikrobus2_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_int: mikrobus2_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_uart: mikrobus2_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus3_an: mikrobus3_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_rst: mikrobus3_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_spi: mikrobus3_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus3_pwm: mikrobus3_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_int: mikrobus3_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_uart: mikrobus3_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_flx2_default: flx2_default { + pinmux = , + , + , + ; + bias-disable; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds, HSIC */ +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "qspi: at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@40000 { + label = "qspi: bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@100000 { + label = "qspi: bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@140000 { + label = "qspi: bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@180000 { + label = "qspi: device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@200000 { + label = "qspi: kernel"; + reg = <0x00200000 0x00600000>; + }; + }; +}; + +&sdmmc0 { + no-1-8-v; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + }; +}; + +&spi0 { /* mikrobus3 spi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts new file mode 100644 index 000000000000..bf1c9ca72a9f --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board + * + * Copyright (C) 2017 Microchip/Atmel, + * 2017 Wenyou Yang + * 2017 Ludovic Desroches + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include +#include +#include + +/ { + model = "Atmel SAMA5D2 PTC EK"; + compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; /* DBGU */ + i2c0 = &i2c0; /* mikroBUS 1 */ + i2c1 = &i2c1; /* XPRO EXT1 */ + i2c2 = &i2c2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + ahb { + usb0: gadget@300000 { + atmel,vbus-gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PB12 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@500000 { + status = "okay"; + }; + + ebi: ebi@10000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; /* conflicts with sdmmc1 and qspi0 */ + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; + }; + + apb { + spi0: spi@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "okay"; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + #address-cells = <1>; + #size-cells = <0>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioA>; + interrupts = <56 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + tcb0: timer@f800c000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + uart0: serial@f801c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + uart2: serial@f8024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + }; + + flx0: flexcom@f8034000 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c2: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_flx0_default>; + pinctrl-1 = <&pinctrl_flx0_gpio>; + sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + }; + }; + + shdwc@f8048010 { + debounce-delay-us = <976>; + + input@0 { + reg = <0>; + }; + }; + + watchdog@f8048040 { + status = "okay"; + }; + + spi1: spi@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + status = "okay"; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + at24@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + }; + }; + + pinctrl@fc038000 { + pinctrl_flx0_default: flx0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx0_gpio: flx0_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_nand_default: nand_default { + re_we_data { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + atmel,drive-strength = ; + }; + + ale_cle_rdy_cs { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + , + , + , + , + ; + bias-pull-up; + }; + + ck_cd_vddsel { + pinmux = , + , + ; + bias-disable; + }; + }; + + pinctrl_spi0_default: spi0_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_spi1_default: spi1_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_uart2_default: uart2_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + + }; + + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-1 { + label = "PB_USER"; + gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; + + led-red { + label = "red"; + gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts new file mode 100644 index 000000000000..2d53c47d7cc8 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts @@ -0,0 +1,745 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Nicolas Ferre + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include +#include +#include + +/ { + model = "Atmel SAMA5D2 Xplained"; + compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart1; /* DBGU */ + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; /* XPRO EXT2 */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + usb0: gadget@300000 { + atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ + &pioA PIN_PB10 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@500000 { + status = "okay"; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + non-removable; + mmc-ddr-3_3v; + status = "okay"; + }; + + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; /* conflict with qspi0 */ + vqmmc-supply = <&vdd_3v3_reg>; + vmmc-supply = <&vdd_3v3_reg>; + }; + + apb { + qspi0: spi@f0020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_default>; + status = "disabled"; /* conflict with sdmmc1 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; + + misc@800000 { + label = "misc"; + reg = <0x00800000 0x00000000>; + }; + }; + }; + + spi0: spi@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "okay"; + + flash@0 { + compatible = "atmel,at25df321a"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + #address-cells = <1>; + #size-cells = <0>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioA>; + interrupts = ; + }; + }; + + tcb0: timer@f800c000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + uart1: serial@f8020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-sda-hold-time-ns = <350>; + status = "okay"; + + pmic@5b { + compatible = "active-semi,act8945a"; + reg = <0x5b>; + active-semi,vsel-high; + status = "okay"; + + regulators { + vdd_1v35_reg: REG_DCDC1 { + regulator-name = "VDD_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1400000>; + regulator-suspend-max-microvolt = <1400000>; + regulator-changeable-in-suspend; + regulator-mode = ; + }; + }; + + vdd_1v2_reg: REG_DCDC2 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_3v3_reg: REG_DCDC3 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_fuse_reg: REG_LDO1 { + regulator-name = "VDD_FUSE"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_3v3_lp_reg: REG_LDO2 { + regulator-name = "VDD_3V3_LP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_led_reg: REG_LDO3 { + regulator-name = "VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_sdhc_1v8_reg: REG_LDO4 { + regulator-name = "VDD_SDHC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + compatible = "active-semi,act8945a-charger"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; + interrupt-parent = <&pioA>; + interrupts = ; + + active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; + active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; + status = "okay"; + }; + }; + }; + + pwm0: pwm@f802c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds */ + }; + + flx0: flexcom@f8034000 { + atmel,flexcom-mode = ; + status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ + + uart5: serial@200 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + status = "okay"; + }; + + i2c2: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_flx0_default>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-sda-hold-time-ns = <350>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ + }; + }; + + shdwc@f8048010 { + debounce-delay-us = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + }; + }; + + watchdog@f8048040 { + status = "okay"; + }; + + i2s0: i2s@f8050000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s0_default>; + status = "disabled"; /* conflict with can0 */ + }; + + can0: can@f8054000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; + }; + + uart3: serial@fc008000 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_default>; + status = "okay"; + }; + + flx4: flexcom@fc018000 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_flx4_default>; + pinctrl-1 = <&pinctrl_flx4_gpio>; + sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + }; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + at24@54 { + compatible = "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + }; + }; + + adc: adc@fc030000 { + vddana-supply = <&vdd_3v3_lp_reg>; + vref-supply = <&vdd_3v3_lp_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; + }; + + pinctrl@fc038000 { + /* + * There is no real pinmux for ADC, if the pin + * is not requested by another peripheral then + * the muxing is done when channel is enabled. + * Requesting pins for ADC is GPIO is + * encouraged to prevent conflicts and to + * disable bias in order to be in the same + * state when the pin is not muxed to the adc. + */ + pinctrl_adc_default: adc_default { + pinmux = ; + bias-disable; + }; + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + /* + * The ADTRG pin can work on any edge type. + * In here it's being pulled up, so need to + * connect it to ground to get an edge e.g. + * Trigger can be configured on falling, rise + * or any edge, and the pull-up can be changed + * to pull-down or left floating according to + * needs. + */ + pinctrl_adtrg_default: adtrg_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_charger_chglev: charger_chglev { + pinmux = ; + bias-disable; + }; + + pinctrl_charger_irq: charger_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_charger_lbo: charger_lbo { + pinmux = ; + bias-pull-up; + }; + + pinctrl_classd_default_pfets: classd_default_pfets { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_classd_default_nfets: classd_default_nfets { + pinmux = , + ; + bias-pull-down; + }; + + pinctrl_flx0_default: flx0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx4_default: flx4_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx4_gpio: flx4_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c2_gpio: i2c2_gpio { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2s0_default: i2s0_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_i2s1_default: i2s1_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_qspi0_default: qspi0_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + ck_cd_rstn { + pinmux = , + , + ; + bias-disable; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + conf-ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_spi0_default: spi0_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_uart1_default: uart1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_uart3_default: uart3_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = , + ; + bias-pull-up; + }; + }; + + classd: classd@fc048000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_classd_default_pfets &pinctrl_classd_default_nfets>; + atmel,pwm-type = "diff"; + atmel,non-overlap-time = <10>; + status = "okay"; + }; + + i2s1: i2s@fc04c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_default>; + status = "disabled"; /* conflict with spi0, sdmmc1 */ + }; + + can1: can@fc050000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button { + label = "PB_USER"; + gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* conflict with pwm0 */ + + led-red { + label = "red"; + gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; + }; + + + led-green { + label = "green"; + gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts new file mode 100644 index 000000000000..c287b03d768b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet + * Development System board. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Jerry Ray + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Ethernet Development System"; + compatible = "microchip,sama5d3-eds", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button-3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + vcc_3v3_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_2v5_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v8_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v2_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_mmc0_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_i2c2_pu: i2c2-pu { + atmel,pins = + , + ; + }; + + pinctrl_key_gpio: key-gpio-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = + ; + }; + + /* Reserved for reset signal to the RGMII connector. */ + pinctrl_rgmii_rstn: rgmii-rstn { + atmel,pins = + ; + }; + + /* Reserved for an interrupt line from the RMII and RGMII connectors. */ + pinctrl_spi_irqn: spi-irqn { + atmel,pins = + ; + }; + + pinctrl_spi0_cs: spi0-cs-default { + atmel,pins = + ; + }; + + pinctrl_spi1_cs: spi1-cs-default { + atmel,pins = ; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + + pinctrl_usb_default: usb-default { + atmel,pins = + ; + }; + + /* Reserved for VBUS fault interrupt. */ + pinctrl_vbusfault_irqn: vbusfault-irqn { + atmel,pins = + ; + }; + + pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default { + atmel,pins = ; + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { /* USB Device port with VBUS detection. */ + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { /* 3-port Host. First port is unused. */ + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_HIGH + &pioE 4 GPIO_ACTIVE_HIGH + >; + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts new file mode 100644 index 000000000000..14af1fd6d247 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Oleksij Rempel , Pengutronix + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "EVB-KSZ9477"; + compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcc0_vcc>; + regulator-name = "mmc0-vcc"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&macb0 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_vcc_mmc0>; + vqmmc-supply = <®_3v3>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, + <&pioD 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&pinctrl_spi_ksz>; + cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + switch@0 { + compatible = "microchip,ksz9477"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "internal"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "internal"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + phy-mode = "internal"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + phy-mode = "internal"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&macb0>; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = ; + }; + + pinctrl_mcc0_vcc: mmc0-vcc { + atmel,pins = ; + }; + + pinctrl_spi_ksz: spi-ksz { + atmel,pins = + < + /* SPI1_MISO */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + /* SPI1_MOSI */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE + /* SPI1_SPCK */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE + + /* SPI CS */ + AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + /* switch IRQ */ + AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH + /* switch PME_N, SoC IN */ + AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP + /* switch RST */ + AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH + >; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts new file mode 100644 index 000000000000..820033727088 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include + +/ { + model = "SAMA5D3 Xplained"; + compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; + }; + + mmc1: mmc@f8000000 { + vmmc-supply = <&vcc_3v3_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "disabled"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; + }; + }; + + spi0: spi@f0004000 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + tcb0: timer@f0010000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + i2c0: i2c@f0014000 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "disabled"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG1 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vddana_reg: LDO_REG2 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii-rxid"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + }; + }; + + pwm0: pwm@f002c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; + status = "okay"; + }; + + usart0: serial@f001c000 { + status = "okay"; + }; + + usart1: serial@f0020000 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + uart0: serial@f0024000 { + status = "okay"; + }; + + mmc1: mmc@f8000000 { + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; + }; + }; + + spi1: spi@f8008000 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioC 25 0>; + status = "okay"; + }; + + adc0: adc@f8018000 { + atmel,adc-vref = <3300>; + atmel,adc-channels-used = <0xfe>; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + >; + status = "okay"; + }; + + i2c2: i2c@f801c000 { + dmas = <0>, <0>; /* Do not use DMA for i2c2 */ + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + dbgu: serial@ffffee00 { + status = "okay"; + }; + + pinctrl@fffff200 { + board { + pinctrl_i2c0_pu: i2c0_pu { + atmel,pins = + , + ; + }; + + pinctrl_i2c2_pu: i2c2_pu { + atmel,pins = + , + ; + }; + + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; /* PE9, conflicts with A9 */ + }; + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; + + pinctrl_gpio_leds: gpio_leds_default { + atmel,pins = + ; + }; + + pinctrl_spi0_cs: spi0_cs_default { + atmel,pins = + ; + }; + + pinctrl_spi1_cs: spi1_cs_default { + atmel,pins = ; + }; + + pinctrl_vcc_mmc0_reg_gpio: vcc_mmc0_reg_gpio_default { + atmel,pins = ; + }; + }; + }; + }; + + usb0: gadget@500000 { + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@600000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_LOW + &pioE 4 GPIO_ACTIVE_LOW + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@700000 { + status = "okay"; + }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + }; + + vcc_mmc0_reg: fixedregulator_mmc0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + status = "okay"; + + led-d2 { + label = "d2"; + gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ + linux,default-trigger = "heartbeat"; + }; + + led-d3 { + label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */ + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi new file mode 100644 index 000000000000..fd1086f52b40 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015 Marek Vasut + */ + +#include "sama5d4.dtsi" + +/ { + model = "Aries/DENX MA5D4"; + compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + + clk20m: clk20m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "clk20m"; + }; + }; + + ahb { + apb { + mmc0: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + broken-cd; + }; + }; + + spi0: spi@f8010000 { + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + + flash@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + }; + + spi1: spi@fc018000 { + cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk20m>; + interrupt-parent = <&pioE>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + spi-max-frequency = <10000000>; + }; + + can1: can@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + clocks = <&clk20m>; + interrupt-parent = <&pioE>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + spi-max-frequency = <10000000>; + }; + }; + + tcb2: timer@fc024000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + atmel,adc-vref = <3300>; + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + }; + }; + + vcc_3v3_reg: fixedregulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_mmc0_reg: fixedregulator_mmc0 { + compatible = "regulator-fixed"; + gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; + regulator-name = "RST_n MCI0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_reg>; + regulator-boot-on; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts new file mode 100644 index 000000000000..8adf567f2f0f --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015 Marek Vasut + */ + +/dts-v1/; +#include "at91-sama5d4_ma5d4.dtsi" + +/ { + model = "Aries/DENX MA5D4EVK"; + compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + ahb { + usb0: gadget@400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_LOW + &pioE 14 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@600000 { + status = "okay"; + }; + + apb { + hlcdc: hlcdc@f0000000 { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + usart0: serial@f802c000 { + status = "okay"; + }; + + usart1: serial@f8030000 { + status = "okay"; + }; + + mmc1: mmc@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + vmmc-supply = <&vcc_mmc1_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 5 0>; + }; + }; + + adc0: adc@fc034000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + }; + + + pinctrl@fc06a000 { + board { + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led-user1 { + label = "user1"; + gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-user2 { + label = "user2"; + gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-user3 { + label = "user3"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel: panel { + /* Actually Ampire 800480R2 */ + compatible = "foxlink,fl500wvr00-a0t"; + backlight = <&backlight>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + vcc_mmc1_reg: fixedregulator_mmc1 { + compatible = "regulator-fixed"; + gpio = <&pioE 17 GPIO_ACTIVE_LOW>; + regulator-name = "VDD MCI1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_reg>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts new file mode 100644 index 000000000000..95d701d13fef --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Josh Wu + */ +/dts-v1/; +#include "sama5d4.dtsi" +#include + +/ { + model = "Atmel SAMA5D4 Xplained"; + compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + uart0: serial@f8004000 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + i2c0: i2c@f8014000 { + i2c-digital-filter; + status = "okay"; + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; + + mmc1: mmc@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + vmmc-supply = <&vcc_mmc1_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 3 0>; + }; + }; + + usart3: serial@fc00c000 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + spi1: spi@fc018000 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioB 21 0>; + status = "okay"; + }; + + tcb2: timer@fc024000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + atmel,adc-vref = <3300>; + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + pinctrl_macb0_phy_irq: macb0_phy_irq_0 { + atmel,pins = + ; + }; + pinctrl_spi1_cs: spi1_cs_default { + atmel,pins = + ; + }; + pinctrl_gpio_leds: gpio_leds_default { + atmel,pins = + ; + }; + pinctrl_vcc_mmc1_reg: vcc_mmc1_reg { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_HIGH + &pioE 14 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@600000 { + status = "okay"; + }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe + &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy + &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button { + label = "pb_user1"; + gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + status = "okay"; + + led-d8 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-d10 { + label = "d10"; + gpios = <&pioE 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_3v3_reg: fixedregulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_mmc1_reg: fixedregulator_mmc1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc1_reg>; + gpio = <&pioE 4 GPIO_ACTIVE_LOW>; + regulator-name = "VDD MCI1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_reg>; + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts new file mode 100644 index 000000000000..20ac775059ca --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4-EK"; + compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ + atmel,adc-vref = <3300>; + /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ + status = "okay"; /* Enable ADC IIO support */ + }; + + mmc0: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 5 0>; + }; + }; + + ssc0: ssc@f8008000 { + status = "okay"; + }; + + spi0: spi@f8010000 { + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + flash@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pmc PMC_TYPE_SYSTEM 10>; + clock-names = "mclk"; + }; + + qt1070:keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <25 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + + touchscreen@4c { + compatible = "atmel,maxtouch"; + reg = <0x4c>; + interrupt-parent = <&pioE>; + interrupts = <24 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + }; + }; + + macb0: ethernet@f8020000 { + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mmc1: mmc@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 6 0>; + }; + }; + + usart2: serial@fc008000 { + status = "okay"; + }; + + usart3: serial@fc00c000 { + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + tcb2: timer@fc024000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + pinctrl_macb0_phy_irq: macb0_phy_irq { + atmel,pins = + ; + }; + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; + }; + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; /* PE13 gpio */ + }; + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + pinctrl_mxt_ts: mxt_irq { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ + &pioE 11 GPIO_ACTIVE_LOW + &pioE 12 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@600000 { + status = "okay"; + }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe + &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy + &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button { + label = "pb_user1"; + gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led-d8 { + label = "d8"; + /* PE28, conflicts with usart4 rts pin */ + gpios = <&pioE 28 GPIO_ACTIVE_LOW>; + }; + + led-d9 { + label = "d9"; + gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; + }; + + led-d10 { + label = "d10"; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D4EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts new file mode 100644 index 000000000000..aa5cc0e98bba --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -0,0 +1,834 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev + * Author: Claudiu Beznea + * + */ +/dts-v1/; +#include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include +#include +#include +#include + +/ { + model = "Microchip SAMA7G5-EK"; + compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; + + chosen { + bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart3; + serial1 = &uart4; + serial2 = &uart7; + serial3 = &uart0; + i2c0 = &i2c1; + i2c1 = &i2c8; + i2c2 = &i2c9; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button { + label = "PB_USER"; + gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* Conflict with pwm. */ + + red_led { + label = "red"; + gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; + }; + + green_led { + label = "green"; + gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; + }; + + blue_led { + label = "blue"; + gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* 512 M */ + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sama7g5ek audio"; + #address-cells = <1>; + #size-cells = <0>; + simple-audio-card,dai-link@0 { + reg = <0>; + cpu { + sound-dai = <&spdiftx>; + }; + codec { + sound-dai = <&spdif_out>; + }; + }; + simple-audio-card,dai-link@1 { + reg = <1>; + cpu { + sound-dai = <&spdifrx>; + }; + codec { + sound-dai = <&spdif_in>; + }; + }; + }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&adc { + vddana-supply = <&vddout25>; + vref-supply = <&vddout25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + m25p,fast-read; + + at91bootstrap@0 { + label = "ospi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "ospi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "ospi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "ospi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "ospi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "ospi: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "ospi: rootfs"; + reg = <0x800000 0x7800000>; + }; + + }; +}; + +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "disabled"; + + uart0: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + status = "disabled"; + }; +}; + +&flx1 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c1: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-voltage = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + + regulator-state-standby { + regulator-suspend-voltage = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + uart4: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "okay"; + }; +}; + +&flx7 { + atmel,flexcom-mode = ; + status = "okay"; + + uart7: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx7_default>; + status = "okay"; + }; +}; + +&flx8 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c8: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + }; +}; + +&flx9 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c9: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + }; +}; + +&flx11 { + atmel,flexcom-mode = ; + status = "okay"; + + spi11: spi@400 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; + status = "okay"; + }; +}; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0_default + &pinctrl_gmac0_mdio_default + &pinctrl_gmac0_txck_default + &pinctrl_gmac0_phy_irq>; + phy-mode = "rgmii-id"; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioA>; + interrupts = ; + }; +}; + +&gmac1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac1_default + &pinctrl_gmac1_mdio_default + &pinctrl_gmac1_phy_irq>; + phy-mode = "rmii"; + status = "okay"; /* Conflict with pdmc0. */ + + ethernet-phy@0 { + reg = <0x0>; + interrupt-parent = <&pioA>; + interrupts = ; + }; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s0_default>; +}; + +&pdmc0 { + #sound-dai-cells = <0>; + microchip,mic-pos = , /* MIC 1 */ + , /* MIC 2 */ + , /* MIC 3 */ + ; /* MIC 4 */ + status = "disabled"; /* Conflict with gmac1. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdmc0_default>; +}; + +&pioA { + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx0_default: flx0_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_flx3_default: flx3_default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_flx4_default: flx4_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx7_default: flx7_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_gmac0_default: gmac0_default { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = <0>; + bias-disable; + }; + + pinctrl_gmac0_mdio_default: gmac0_mdio_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_gmac0_txck_default: gmac0_txck_default { + pinmux = ; + slew-rate = <0>; + bias-pull-up; + }; + + pinctrl_gmac0_phy_irq: gmac0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_gmac1_default: gmac1_default { + pinmux = , + , + , + , + , + , + , + ; + slew-rate = <0>; + bias-disable; + }; + + pinctrl_gmac1_mdio_default: gmac1_mdio_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_gmac1_phy_irq: gmac1_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c8_default: i2c8_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c9_default: i2c9_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2s0_default: i2s0_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_mikrobus1_an_default: mikrobus1_an_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_an_default: mikrobus2_an_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi: mikrobus1_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_pdmc0_default: pdmc0_default { + pinmux = , + , + ; + bias_disable; + }; + + pinctrl_qspi: qspi { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + atmel,drive-strength = ; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + + ck_cd_rstn_vddsel { + pinmux = , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + + ck_cd_rstn_vddsel { + pinmux = , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + }; + + pinctrl_sdmmc2_default: sdmmc2_default { + cmd_data { + pinmux = , + , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + + ck { + pinmux = ; + slew-rate = <0>; + bias-pull-up; + }; + }; + + pinctrl_spdifrx_default: spdifrx_default { + pinmux = ; + bias-disable; + }; + + pinctrl_spdiftx_default: spdiftx_default { + pinmux = ; + bias-disable; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; + status = "disabled"; /* Conflict with leds. */ +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width = <8>; + non-removable; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vldo1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + no-1-8-v; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + no-1-8-v; + sdhci-caps-mask = <0x0 0x00200000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc2_default>; +}; + +&shdwc { + atmel,shdwc-debouncer = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&spdifrx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdifrx_default>; + status = "okay"; +}; + +&spdiftx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdiftx_default>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&trng { + status = "okay"; +}; + +&vddout25 { + vin-supply = <&vdd_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-smartkiz.dts b/arch/arm/boot/dts/microchip/at91-smartkiz.dts new file mode 100644 index 000000000000..b76a6b5ac464 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-smartkiz.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2018 Overkiz SAS + * Author: Mickael Gardet + * Kévin Raymond + * Dorian Rocipon + */ +/dts-v1/; +#include "at91-kizboxmini-common.dtsi" + +/ { + model = "Overkiz SmartKiz"; + compatible = "overkiz,smartkiz", "atmel,at91sam9g25", + "atmel,at91sam9x5", "atmel,at91sam9"; + + clocks { + adc_op_clk { + status = "okay"; + }; + }; + + aliases { + serial5 = &uart0; + }; + + pio_keys { + hk_reset { + label = "HK_RESET"; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + }; + + power_rf { + label = "POWER_RF"; + gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; + }; + + power_wifi { + label = "POWER_WIFI"; + gpios = <&pioA 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; + }; + }; + + adc0 { + pinctrl_adc0_ad0: adc0_ad0-0 { + /* pull-up disable */ + atmel,pins = ; + }; + pinctrl_adc0_ad5: adc0_ad5-0 { + /* pull-up disable */ + atmel,pins = ; + }; + pinctrl_adc0_ad6: adc0_ad6-0 { + /* pull-up disable */ + atmel,pins = ; + }; + pinctrl_adc0_ad11: adc0_ad11-0 { + /* pull-up disable */ + atmel,pins = ; + }; + }; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +&macb0 { + status = "disabled"; +}; + +&rtc { + status = "okay"; +}; + +&led_blue { + status = "okay"; +}; + +&adc0 { + atmel,adc-vref = <2500>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad11 + >; + atmel,adc-channels-used = <0x0861>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-som60.dtsi b/arch/arm/boot/dts/microchip/at91-som60.dtsi new file mode 100644 index 000000000000..39474a112b16 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-som60.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-som60.dtsi - Device Tree file for the SOM60 module + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ +#include "sama5d36.dtsi" + +/ { + model = "Laird SOM60"; + compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; +}; + +&pinctrl { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + + pinctrl_mmc0_en: mmc0_en { + atmel,pins = + ; + }; + + pinctrl_nand0_wp: nand0_wp { + atmel,pins = + ; + }; + + pinctrl_usb_vbus: usb_vbus { + atmel,pins = + ; + /* Conflicts with USART2_SCK */ + }; + + pinctrl_usart2_sck: usart2_sck { + atmel,pins = + ; + /* Conflicts with USB_VBUS */ + }; + + pinctrl_usb_oc: usb_oc { + atmel,pins = + ; + /* Conflicts with USART3_SCK */ + }; + + pinctrl_usart3_sck: usart3_sck { + atmel,pins = + ; + /* Conflicts with USB_OC */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + + pinctrl_geth_int: geth_int { + atmel,pins = + ; + /* Conflicts with USART1_SCK */ + }; + + pinctrl_usart1_sck: usart1_sck { + atmel,pins = + ; + /* Conflicts with GETH_INT */ + }; + + pinctrl_eth_int: eth_int { + atmel,pins = + ; + }; + + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + ; + }; + }; +}; + +&mmc0 { + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc1 { + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&spi0 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; +}; + +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +}; + +&usart1 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +}; + +&usart2 { + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>; +}; + +&usart3 { + pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; +}; + +&adc0 { + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + >; +}; + +&macb0 { + phy-mode = "rgmii"; +}; + +&macb1 { + phy-mode = "rmii"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubootspl@0 { + label = "u-boot-spl"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x20000>; + }; + + ubi@e0000 { + label = "ubi"; + reg = <0xe0000 0xfe00000>; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>; + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 20 GPIO_ACTIVE_HIGH + 0>; + atmel,oc-gpio = <0 + &pioE 15 GPIO_ACTIVE_LOW + 0>; +}; diff --git a/arch/arm/boot/dts/microchip/at91-tse850-3.dts b/arch/arm/boot/dts/microchip/at91-tse850-3.dts new file mode 100644 index 000000000000..9d58a3931207 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-tse850-3.dts @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin + */ +/dts-v1/; +#include +#include "at91-linea.dtsi" + +/ { + model = "Axentia TSE-850 3.0"; + compatible = "axentia,tse850v3", "axentia,linea", + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + sck: oscillator { + compatible = "fixed-clock"; + + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "sck"; + }; + + reg_3v3: regulator { + compatible = "regulator-fixed"; + + regulator-name = "3v3-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ana: reg-ana { + compatible = "pwm-regulator"; + + regulator-name = "ANA"; + + pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; + pwm-dutycycle-unit = <1000>; + pwm-dutycycle-range = <100 1000>; + + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <20000000>; + regulator-ramp-delay = <1000>; + }; + + sound { + compatible = "axentia,tse850-pcm5142"; + + axentia,cpu-dai = <&ssc0>; + axentia,audio-codec = <&pcm5142>; + + axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; + axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; + + axentia,ana-supply = <&ana>; + }; + + dac: dpot-dac { + compatible = "dpot-dac"; + vref-supply = <®_3v3>; + io-channels = <&dpot 0>; + io-channel-names = "dpot"; + #io-channel-cells = <1>; + }; + + env_det: envelope-detector { + compatible = "axentia,tse850-envelope-detector"; + io-channels = <&dac 0>; + io-channel-names = "dac"; + #io-channel-cells = <1>; + + interrupt-parent = <&pioA>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "comp"; + }; + + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, + <&pioA 1 GPIO_ACTIVE_HIGH>, + <&pioA 2 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + + envelope-detector-mux { + compatible = "io-channel-mux"; + io-channels = <&env_det 0>; + io-channel-names = "parent"; + + mux-controls = <&mux>; + + channels = "", "", + "sync-1", + "in", + "out", + "sync-2", + "sys-reg", + "ana-reg"; + }; + + leds { + compatible = "gpio-leds"; + + led-ch1-red { + label = "ch-1:red"; + gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + }; + led-ch1-green { + label = "ch-1:green"; + gpios = <&pioA 22 GPIO_ACTIVE_LOW>; + }; + led-ch2-red { + label = "ch-2:red"; + gpios = <&pioA 21 GPIO_ACTIVE_LOW>; + }; + led-ch2-green { + label = "ch-2:green"; + gpios = <&pioA 20 GPIO_ACTIVE_LOW>; + }; + led-data-red { + label = "data:red"; + gpios = <&pioA 19 GPIO_ACTIVE_LOW>; + }; + led-data-green { + label = "data:green"; + gpios = <&pioA 18 GPIO_ACTIVE_LOW>; + }; + led-alarm-red { + label = "alarm:red"; + gpios = <&pioA 17 GPIO_ACTIVE_LOW>; + }; + led-alarm-green { + label = "alarm:green"; + gpios = <&pioA 16 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + barebox@40000 { + label = "bootloader"; + reg = <0x40000 0x60000>; + }; + + bareboxenv@c0000 { + label = "bareboxenv"; + reg = <0xc0000 0x40000>; + }; + + bareboxenv2@100000 { + label = "bareboxenv2"; + reg = <0x100000 0x40000>; + }; + + oftree@180000 { + label = "oftree"; + reg = <0x180000 0x20000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + + ovlfs@10000000 { + label = "ovlfs"; + reg = <0x10000000 0x10000000>; + }; + }; +}; + +&ssc0 { + #sound-dai-cells = <0>; + + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + jc42@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + smbus-timeout-disable; + }; + + dpot: mcp4651-104@28 { + compatible = "microchip,mcp4651-104"; + reg = <0x28>; + #io-channel-cells = <1>; + }; + + pcm5142: pcm5142@4c { + compatible = "ti,pcm5142"; + + reg = <0x4c>; + #sound-dai-cells = <0>; + + AVDD-supply = <®_3v3>; + DVDD-supply = <®_3v3>; + CPVDD-supply = <®_3v3>; + + clocks = <&sck>; + + pll-in = <3>; + pll-out = <6>; + }; + + eeprom@50 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&pinctrl { + tse850 { + pinctrl_usba_vbus: usba-vbus { + atmel,pins = ; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usart0 { + status = "okay"; + + atmel,use-dma-rx; +}; + +&pwm0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_pwm0_pwml2_1>; + pinctrl-names = "default"; +}; + +&macb1 { + status = "okay"; + + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@3 { + reg = <3>; + + interrupt-parent = <&pioE>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&usb0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioC 31 GPIO_ACTIVE_HIGH>; +}; + +&usb1 { + status = "okay"; + + num-ports = <1>; + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + atmel,oc-gpio = <&pioC 15 GPIO_ACTIVE_LOW>; +}; + +&usb2 { + status = "okay"; +}; + +&dbgu { + status = "okay"; + + dmas = <0>, <0>; /* Do not use DMA for dbgu */ +}; + +&pioA { + gpio-line-names = + /* 0 */ "SUP-A", "SUP-B", "SUP-C", "SIGLIN", + /* 28 */ "RXD", "TXD", "BRX", "BTX"; +}; + +&pioC { + gpio-line-names = + /* 0 */ "ETX0", "ETX1", "ERX0", "ERX1", + /* 4 */ "ETXEN", "ECRSDV", "ERXER", "EREFCK", + /* 8 */ "EMDC", "EMDIO", "", "", + /* 12 */ "", "", "", "/ILIM", + /* 16 */ "BCK", "LRCK", "DIN", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", "VBUS"; +}; + +&pioD { + gpio-line-names = + /* 0 */ "I1", "I2", "O1", "EXTVEN", + /* 4 */ "", "456KHZ", "VCTRL", "SYNCSEL", + /* 8 */ "STEREO", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", ">LIN", "LIN>", "", + /* 20 */ "VREFEN", "", "", "", + /* 24 */ "", "", "VINOK", "", + /* 28 */ "POEOK", "USBON", "POELOAD", ""; +}; + +&pioE { + gpio-line-names = + /* 0 */ "", "", "", "", + /* 4 */ "", "", "", "", + /* 8 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "ALE", "CLE", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", "/ETHINT"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-vinco.dts b/arch/arm/boot/dts/microchip/at91-vinco.dts new file mode 100644 index 000000000000..ebeaa6ab500e --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-vinco.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for VInCo platform + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + * 2015 Gregory CLEMENT + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "L+G VInCo platform"; + compatible = "l+g,vinco", "atmel,sama5d4", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + + adc0: adc@fc034000 { + status = "okay"; /* Enable ADC IIO support */ + }; + + mmc0: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 + &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7>; + vqmmc-supply = <&vcc_3v3_reg>; + vmmc-supply = <&vcc_3v3_reg>; + no-1-8-v; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + non-removable; + broken-cd; + status = "okay"; + }; + }; + + spi0: spi@f8010000 { + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + flash@0 { + compatible = "n25q32b", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + }; + + i2c1: i2c@f8018000 { + status = "okay"; + /* kerkey security module */ + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + interrupt-parent = <&pioB>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + }; + + }; + + i2c2: i2c@f8024000 { + status = "okay"; + + rtc1: rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + }; + + usart2: serial@fc008000 { + /* MBUS */ + status = "okay"; + }; + + usart3: serial@fc00c000 { + /* debug */ + status = "okay"; + }; + + usart4: serial@fc010000 { + /* LMN */ + pinctrl-0 = <&pinctrl_usart4 &pinctrl_usart4_rts>; + linux,rs485-enabled-at-boot-time; + status = "okay"; + }; + + tcb2: timer@fc024000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + macb1: ethernet@fc028000 { + phy-mode = "rmii"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>; + }; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "disable"; + }; + + usb1: ohci@500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_LOW + &pioE 12 GPIO_ACTIVE_LOW + >; + status = "disable"; + }; + + usb2: ehci@600000 { + /* 4G Modem */ + status = "okay"; + }; + + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led_err { + label = "err"; + gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_rssi { + label = "rssi"; + gpios = <&pioA 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_tls { + label = "tls"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_lmc { + label = "lmc"; + gpios = <&pioA 25 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_wmt { + label = "wmt"; + gpios = <&pioA 29 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_pwr { + label = "pwr"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + }; + + vcc_3v3_reg: fixedregulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91-wb45n.dts b/arch/arm/boot/dts/microchip/at91-wb45n.dts new file mode 100644 index 000000000000..ef73f727f7bd --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-wb45n.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb45n.dts - Device Tree file for WB45NBT board + * + * Copyright (C) 2018 Laird + * + */ +/dts-v1/; +#include "at91-wb45n.dtsi" + +/ { + model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; + compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; + + gpio-keys { + compatible = "gpio-keys"; + + button { + label = "IRQBTN"; + linux,code = <99>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&macb0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&usart0 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91-wb45n.dtsi b/arch/arm/boot/dts/microchip/at91-wb45n.dtsi new file mode 100644 index 000000000000..430c75358086 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-wb45n.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb45n.dtsi - Device Tree file for WB45NBT board + * + * Copyright (C) 2018 Laird + * + */ + +#include "at91sam9g25.dtsi" + +/ { + model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; + compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + atheros { + compatible = "atheros,ath6kl"; + atheros,board-id = "SD32"; + }; +}; + +&reset_controller { + compatible = "atmel,sama5d3-rstc"; +}; + +&shutdown_controller { + atmel,wakeup-mode = "low"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&ebi { + status = "okay"; + nand_controller: nand-controller { + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>; + pinctrl-names = "default"; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bs"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "redund-env"; + reg = <0xc0000 0x20000>; + }; + + kernel-a@e0000 { + label = "kernel-a"; + reg = <0xe0000 0x280000>; + }; + + kernel-b@360000 { + label = "kernel-b"; + reg = <0x360000 0x280000>; + }; + + rootfs-a@5e0000 { + label = "rootfs-a"; + reg = <0x5e0000 0x2600000>; + }; + + rootfs-b@2be0000 { + label = "rootfs-b"; + reg = <0x2be0000 0x2600000>; + }; + + user@51e0000 { + label = "user"; + reg = <0x51e0000 0x2dc0000>; + }; + + logs@7fa0000 { + label = "logs"; + reg = <0x7fa0000 0x60000>; + }; + + }; + }; + }; +}; + +&usb0 { + num-ports = <2>; + atmel,vbus-gpio = < + &pioB 12 GPIO_ACTIVE_HIGH + &pioA 31 GPIO_ACTIVE_HIGH + >; + atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; +}; + +&macb0 { + phy-mode = "rmii"; +}; + +&spi0 { + cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>; +}; + +&usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_usb2>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&pinctrl { + usb2 { + pinctrl_board_usb2: usb2-board { + atmel,pins = + ; /* PB11 gpio vbus sense, deglitch */ + }; + }; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-wb50n.dts b/arch/arm/boot/dts/microchip/at91-wb50n.dts new file mode 100644 index 000000000000..ec2becf6133b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-wb50n.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb50n.dts - Device Tree file for wb50n evaluation board + * + * Copyright (C) 2018 Laird + * + */ + +/dts-v1/; +#include "at91-wb50n.dtsi" + +/ { + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + label = "BTNESC"; + linux,code = <1>; /* ESC button */ + gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-1 { + label = "IRQBTN"; + linux,code = <99>; /* SysReq button */ + gpios = <&pioE 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "wb50n:blue:led0"; + gpios = <&pioA 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led1 { + label = "wb50n:green:led1"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "wb50n:red:led2"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +/* On BB40 this port is labeled UART1 */ +&usart0 { + status = "okay"; +}; + +/* On BB40 this port is labeled UART0 */ +&usart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/microchip/at91-wb50n.dtsi b/arch/arm/boot/dts/microchip/at91-wb50n.dtsi new file mode 100644 index 000000000000..74b249bb6351 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-wb50n.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module + * + * Copyright (C) 2018 Laird + * + */ + +#include "sama5d31.dtsi" + +/ { + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; +}; + +&pinctrl { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = ; /* PC26 GPIO with pullup deglitch */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = ; /* PB13 GPIO with deglitch */ + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&clk32k { + atmel,osc-bypass; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "okay"; + atheros@0 { + compatible = "atheros,ath6kl"; + atheros,board-id = "SD32"; + reg = <0>; + bus-width = <4>; + }; +}; + +&macb1 { + phy-mode = "rmii"; +}; + +&dbgu { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ +}; + +/* On BB40 this port is labeled UART1 */ +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +}; + +/* On BB40 this port is labeled UART0 */ +&usart1 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>; +}; + +/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */ +&usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; + status = "okay"; +}; + +&spi1 { + cs-gpios = <&pioC 25 0>, <0>, <0>, <0>; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bs"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x20000>; + }; + + kernel-a@e0000 { + label = "kernel-a"; + reg = <0xe0000 0x500000>; + }; + + kernel-b@5e0000 { + label = "kernel-b"; + reg = <0x5e0000 0x500000>; + }; + + rootfs-a@ae0000 { + label = "rootfs-a"; + reg = <0xae0000 0x3000000>; + }; + + rootfs-b@3ae0000 { + label = "rootfs-b"; + reg = <0x3ae0000 0x3000000>; + }; + + user@6ae0000 { + label = "user"; + reg = <0x6ae0000 0x14e0000>; + }; + }; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>; + atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi new file mode 100644 index 000000000000..37b500f6f395 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -0,0 +1,729 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre , + * 2012 Joachim Eastwood + * + * Based on at91sam9260.dtsi + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91RM9200 family SoC"; + compatible = "atmel,at91rm9200"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + ssc0 = &ssc0; + ssc1 = &ssc1; + ssc2 = &ssc2; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm920t"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x04000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram: sram@200000 { + compatible = "mmio-sram"; + reg = <0x00200000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00200000 0x4000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <25 26 27 28 29 30 31>; + }; + + ramc0: ramc@ffffff00 { + compatible = "atmel,at91rm9200-sdramc", "syscon"; + reg = <0xffffff00 0x100>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91rm9200-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; + }; + + st: timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; + + rtc: rtc@fffffe00 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffe00 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffa0000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + tcb1: timer@fffa4000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffa4000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 + 21 IRQ_TYPE_LEVEL_HIGH 0 + 22 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + i2c0: i2c@fffb8000 { + compatible = "atmel,at91rm9200-i2c"; + reg = <0xfffb8000 0x4000>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_twi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@fffb4000 { + compatible = "atmel,hsmci"; + reg = <0xfffb4000 0x4000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssc0: ssc@fffd0000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffd0000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc1: ssc@fffd4000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffd4000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc2: ssc@fffd8000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffd8000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "pclk"; + status = "disabled"; + }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at91rm9200-emac", "cdns,emac"; + reg = <0xfffbc000 0x4000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "ether_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + + atmel,mux-mask = < + /* A B */ + 0xffffffff 0xffffffff /* pioA */ + 0xffffffff 0x083fffff /* pioB */ + 0xffff3fff 0x00000000 /* pioC */ + 0x03ff87ff 0x0fffff80 /* pioD */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; + }; + + pinctrl_uart0_cts: uart0_cts-0 { + atmel,pins = + ; /* PA20 periph A */ + }; + + pinctrl_uart0_rts: uart0_rts-0 { + atmel,pins = + ; /* PA21 periph A */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; + }; + + pinctrl_uart1_rts: uart1_rts-0 { + atmel,pins = + ; /* PB24 periph A */ + }; + + pinctrl_uart1_cts: uart1_cts-0 { + atmel,pins = + ; /* PB26 periph A */ + }; + + pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { + atmel,pins = + ; /* PB25 periph A */ + }; + + pinctrl_uart1_dcd: uart1_dcd-0 { + atmel,pins = + ; /* PB23 periph A */ + }; + + pinctrl_uart1_ri: uart1_ri-0 { + atmel,pins = + ; /* PB18 periph A */ + }; + }; + + uart2 { + pinctrl_uart2: uart2-0 { + atmel,pins = + ; + }; + + pinctrl_uart2_rts: uart2_rts-0 { + atmel,pins = + ; /* PA30 periph B */ + }; + + pinctrl_uart2_cts: uart2_cts-0 { + atmel,pins = + ; /* PA31 periph B */ + }; + }; + + uart3 { + pinctrl_uart3: uart3-0 { + atmel,pins = + ; + }; + + pinctrl_uart3_rts: uart3_rts-0 { + atmel,pins = + ; /* PB0 periph B */ + }; + + pinctrl_uart3_cts: uart3_cts-0 { + atmel,pins = + ; /* PB1 periph B */ + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + ; /* PB1 gpio CD pin pull_up */ + }; + }; + + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + ; /* PA16 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + ; /* PB19 periph B */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; /* PA27 periph A */ + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + ; /* PA29 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PB5 periph B with pullup */ + }; + + pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { + atmel,pins = + ; /* PA9 periph B with pullup */ + }; + + pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { + atmel,pins = + ; /* PA12 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PB2 periph A */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PB5 periph A */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + ; /* PB8 periph A */ + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + ; /* PB11 periph A */ + }; + }; + + ssc2 { + pinctrl_ssc2_tx: ssc2_tx-0 { + atmel,pins = + ; /* PB14 periph A */ + }; + + pinctrl_ssc2_rx: ssc2_rx-0 { + atmel,pins = + ; /* PB17 periph A */ + }; + }; + + twi { + pinctrl_twi: twi-0 { + atmel,pins = + ; /* PA26 periph A with multi drive */ + }; + + pinctrl_twi_gpio: twi_gpio-0 { + atmel,pins = + ; /* PA26 GPIO with multi drive */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA2 periph A SPI0_SPCK pin */ + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + }; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@fffc0000 { + compatible = "atmel,at91rm9200-usart"; + reg = <0xfffc0000 0x200>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffc4000 { + compatible = "atmel,at91rm9200-usart"; + reg = <0xfffc4000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffc8000 { + compatible = "atmel,at91rm9200-usart"; + reg = <0xfffc8000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fffcc000 { + compatible = "atmel,at91rm9200-usart"; + reg = <0xfffcc000 0x200>; + atmel,usart-mode = ; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + status = "disabled"; + }; + + usb1: gadget@fffb0000 { + compatible = "atmel,at91rm9200-udc"; + reg = <0xfffb0000 0x4000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + spi0: spi@fffe0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffe0000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-ecc-mode = "soft"; + gpios = <&pioC 2 GPIO_ACTIVE_HIGH + 0 + &pioB 1 GPIO_ACTIVE_HIGH + >; + status = "disabled"; + }; + + usb0: ohci@300000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00300000 0x100000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ + &pioA 26 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_twi_gpio>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi b/arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi new file mode 100644 index 000000000000..c3d4177b9823 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC + * + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91rm9200.dtsi" + +/ { + compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200"; +}; + +&pioD { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/microchip/at91rm9200ek.dts b/arch/arm/boot/dts/microchip/at91rm9200ek.dts new file mode 100644 index 000000000000..4624a6f076f8 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91rm9200ek.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit + * + * Copyright (C) 2012 Joachim Eastwood + */ +/dts-v1/; +#include "at91rm9200.dtsi" + +/ { + model = "Atmel AT91RM9200 evaluation kit"; + compatible = "atmel,at91rm9200ek", "atmel,at91rm9200"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usb1: gadget@fffb0000 { + atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; + atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + + phy0: ethernet-phy { + interrupt-parent = <&pioC>; + interrupts = <4 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + usart1: serial@fffc4000 { + pinctrl-0 = + <&pinctrl_uart1 + &pinctrl_uart1_rts + &pinctrl_uart1_cts + &pinctrl_uart1_dtr_dsr + &pinctrl_uart1_dcd + &pinctrl_uart1_ri>; + status = "okay"; + }; + + spi0: spi@fffe0000 { + status = "okay"; + cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + rtc: rtc@fffffe00 { + status = "okay"; + }; + }; + + usb0: ohci@300000 { + num-ports = <2>; + status = "okay"; + }; + + flash@10000000 { + compatible = "cfi-flash"; + reg = <0x10000000 0x800000>; + linux,mtd-name = "physmap-flash.0"; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x00000 0x40000>; + }; + + bareboxenv@40000 { + label = "bareboxenv"; + reg = <0x40000 0x10000>; + }; + + kernel@50000 { + label = "kernel"; + reg = <0x50000 0x300000>; + }; + + root@350000 { + label = "root"; + reg = <0x350000 0x4B0000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds2 { + label = "green"; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + ds4 { + label = "yellow"; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + ds6 { + label = "red"; + gpios = <&pioB 2 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi new file mode 100644 index 000000000000..16e3b24b4ddd --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -0,0 +1,796 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre , + * 2011 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9260 family SoC"; + compatible = "atmel,at91sam9260"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &uart0; + serial6 = &uart1; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + ssc0 = &ssc0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x04000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; + }; + + sram0: sram@2ff000 { + compatible = "mmio-sram"; + reg = <0x002ff000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x002ff000 0x2000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <29 30 31>; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + smc: smc@ffffec00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffec00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9260-matrix", "syscon"; + reg = <0xffffee00 0x200>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9260-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; + }; + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffa0000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffdc000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 + 27 IRQ_TYPE_LEVEL_HIGH 0 + 28 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x600>; + + atmel,mux-mask = < + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + 0xffffffff 0x7fff3ccf /* pioB */ + 0xffffffff 0x007fffff /* pioC */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PB26 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PB27 periph A */ + }; + + pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { + atmel,pins = + ; /* PB22 periph A */ + }; + + pinctrl_usart0_dcd: usart0_dcd-0 { + atmel,pins = + ; /* PB23 periph A */ + }; + + pinctrl_usart0_ri: usart0_ri-0 { + atmel,pins = + ; /* PB25 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; /* PB28 periph A */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; /* PB29 periph A */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PA4 periph A */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PA5 periph A */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; + }; + }; + + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + ; /* PA21 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + ; /* PA29 periph B */ + }; + + pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { + atmel,pins = + ; /* PA29 periph B */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; /* PA8 periph A */ + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + ; /* PA6 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA11 periph A with pullup */ + }; + + pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { + atmel,pins = + ; /* PA0 periph B with pullup */ + }; + + pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { + atmel,pins = + ; /* PA3 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PB18 periph A */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PB21 periph A */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA2 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PB2 periph A SPI1_SPCK pin */ + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fffd0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd0000 0x200>; + atmel,usart-mode = ; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "usart"; + status = "disabled"; + }; + + uart0: serial@fffd4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd4000 0x200>; + atmel,usart-mode = ; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@fffd8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd8000 0x200>; + atmel,usart-mode = ; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; + clock-names = "usart"; + status = "disabled"; + }; + + macb0: ethernet@fffc4000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91sam9260-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffac000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + status = "disabled"; + }; + + mmc0: mmc@fffa8000 { + compatible = "atmel,hsmci"; + reg = <0xfffa8000 0x600>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffbc000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi0: spi@fffc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffc8000 0x200>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + adc0: adc@fffe0000 { + compatible = "atmel,at91sam9260-adc"; + reg = <0xfffe0000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0xf>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <15>; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + status = "disabled"; + }; + + watchdog: watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; + }; + + usb0: ohci@500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9260-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000 + 0x6 0x0 0x70000000 0x10000000 + 0x7 0x0 0x80000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9260-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + }; + + i2c_gpio0: i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ + &pioA 24 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9260ek.dts b/arch/arm/boot/dts/microchip/at91sam9260ek.dts new file mode 100644 index 000000000000..bb72f050a4fe --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9260ek.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Atmel at91sam9260 Evaluation Kit + * + * Copyright (C) 2016 Atmel, + * 2016 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9260.dtsi" +#include + +/ { + model = "Atmel at91sam9260ek"; + compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + stdout-path = &dbgu; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0_slot1 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + spi0: spi@fffc8000 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + flash@1 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + ; + }; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-3 { + label = "Button 3"; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + wakeup-source; + }; + + button-4 { + label = "Button 4"; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + + 24c512@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi new file mode 100644 index 000000000000..fe9ead867e2a --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi @@ -0,0 +1,667 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC + * + * Copyright (C) 2013 Jean-Jacques Hiblot + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9261 family SoC"; + compatible = "atmel,at91sam9261"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + i2c0 = &i2c0; + ssc0 = &ssc0; + ssc1 = &ssc1; + ssc2 = &ssc2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x08000000>; + }; + + clocks { + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x28000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: ohci@500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + fb0: fb@600000 { + compatible = "atmel,at91sam9261-lcdc"; + reg = <0x00600000 0x1000>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>; + clock-names = "lcdc_clk", "hclk"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9261-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000 + 0x6 0x0 0x70000000 0x10000000 + 0x7 0x0 0x80000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9261-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffa0000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91sam9261-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; + clock-names = "pclk", "hclk"; + atmel,matrix = <&matrix>; + status = "disabled"; + }; + + mmc0: mmc@fffa8000 { + compatible = "atmel,hsmci"; + reg = <0xfffa8000 0x600>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9261-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_twi>; + reg = <0xfffac000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000{ + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffbc000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc1: ssc@fffc0000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc0000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc2: ssc@fffc4000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc4000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi0: spi@fffc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffc8000 0x200>; + cs-gpios = <0>, <0>, <0>, <0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ramc: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + smc: smc@ffffec00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffec00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9261-matrix", "syscon"; + reg = <0xffffee00 0x200>; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <29 30 31>; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x600>; + + atmel,mux-mask = + /* A B */ + <0xffffffff 0xfffffff7>, /* pioA */ + <0xffffffff 0xfffffff4>, /* pioB */ + <0xffffffff 0xffffff07>; /* pioC */ + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + , + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; + }; + }; + + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc2 { + pinctrl_ssc2_tx: ssc2_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc2_rx: ssc2_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + , + , + ; + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + , + , + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + i2c0 { + pinctrl_i2c_bitbang: i2c-0-bitbang { + atmel,pins = + , + ; + }; + pinctrl_i2c_twi: i2c-0-twi { + atmel,pins = + , + ; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9261-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; + }; + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_bitbang>; + gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9261ek.dts b/arch/arm/boot/dts/microchip/at91sam9261ek.dts new file mode 100644 index 000000000000..88869ca874d1 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9261ek.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board + * + * Copyright (C) 2013 Jean-Jacques Hiblot + */ +/dts-v1/; +#include "at91sam9261.dtsi" + +/ { + model = "Atmel at91sam9261ek"; + compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + usb0: ohci@500000 { + status = "okay"; + }; + + fb0: fb@600000 { + display = <&display0>; + atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + display0: panel { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "BRG"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + + apb { + tcb0: timer@fffa0000 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer1: timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffc8000 { + cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; + status = "okay"; + + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <0>; + spi-max-frequency = <15000000>; + }; + + tsc2046@2 { + reg = <2>; + compatible = "ti,ads7843"; + interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; + spi-max-frequency = <3000000>; + pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <150>; + ti,x-max = /bits/ 16 <3830>; + ti,y-min = /bits/ 16 <190>; + ti,y-max = /bits/ 16 <3830>; + ti,vref-delay-usecs = /bits/ 16 <450>; + ti,x-plate-ohms = /bits/ 16 <450>; + ti,y-plate-ohms = /bits/ 16 <250>; + ti,pressure-max = /bits/ 16 <15000>; + ti,debounce-rep = /bits/ 16 <0>; + ti,debounce-tol = /bits/ 16 <65535>; + ti,debounce-max = /bits/ 16 <1>; + + wakeup-source; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + }; + }; + + leds { + compatible = "gpio-leds"; + + ds8 { + label = "ds8"; + gpios = <&pioA 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + ds7 { + label = "ds7"; + gpios = <&pioA 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + + ds1 { + label = "ds1"; + gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + label = "button_0"; + gpios = <&pioA 27 GPIO_ACTIVE_LOW>; + linux,code = <256>; + wakeup-source; + }; + + button-1 { + label = "button_1"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + linux,code = <257>; + wakeup-source; + }; + + button-2 { + label = "button_2"; + gpios = <&pioA 25 GPIO_ACTIVE_LOW>; + linux,code = <258>; + wakeup-source; + }; + + button-3 { + label = "button_3"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + linux,code = <259>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi new file mode 100644 index 000000000000..ee5e6ed44dd4 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9263.dtsi @@ -0,0 +1,839 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9263 family SoC"; + compatible = "atmel,at91sam9263"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + i2c0 = &i2c0; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x08000000>; + }; + + clocks { + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram0: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x14000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x14000>; + }; + + sram1: sram@500000 { + compatible = "mmio-sram"; + reg = <0x00500000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00500000 0x4000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <30 31>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9263-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; + }; + + ramc0: ramc@ffffe200 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe200 0x200>; + }; + + smc0: smc@ffffe400 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffe400 0x200>; + }; + + ramc1: ramc@ffffe800 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe800 0x200>; + }; + + smc1: smc@ffffea00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x200>; + }; + + matrix: matrix@ffffec00 { + compatible = "atmel,at91sam9263-matrix", "syscon"; + reg = <0xffffec00 0x200>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff7c000 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; + clock-names = "t0_clk", "slow_clk"; + }; + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; + }; + + pinctrl@fffff200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + + atmel,mux-mask = < + /* A B */ + 0xfffffffb 0xffffe07f /* pioA */ + 0x0007ffff 0x39072fff /* pioB */ + 0xffffffff 0x3ffffff8 /* pioC */ + 0xfffffbff 0xffffffff /* pioD */ + 0xffe00fff 0xfbfcff00 /* pioE */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PA28 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PA29 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; /* PD7 periph B */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; /* PD8 periph B */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PD5 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PD6 periph B */ + }; + }; + + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + ; /* PE30 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + ; /* PE22 periph B */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; /* PA12 periph A */ + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + ; /* PA0 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA5 periph A with pullup */ + }; + + pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { + atmel,pins = + ; /* PA17 periph A with pullup */ + }; + + pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { + atmel,pins = + ; /* PA20 periph A with pullup */ + }; + }; + + mmc1 { + pinctrl_mmc1_clk: mmc1_clk-0 { + atmel,pins = + ; /* PA6 periph A */ + }; + + pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { + atmel,pins = + ; /* PA8 periph A with pullup */ + }; + + pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { + atmel,pins = + ; /* PA11 periph A with pullup */ + }; + + pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { + atmel,pins = + ; /* PA22 periph A with pullup */ + }; + + pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { + atmel,pins = + ; /* PA25 periph A with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PB2 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PB5 periph B */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + ; /* PB8 periph A */ + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + ; /* PB11 periph A */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA2 periph B SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PB14 periph A SPI1_SPCK pin */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + ; /* PC27 periph A */ + }; + }; + + can { + pinctrl_can_rx_tx: can_rx_tx { + atmel,pins = + ; /* CANTX, conflicts with PCK0 */ + }; + }; + + ac97 { + pinctrl_ac97: ac97-0 { + atmel,pins = + ; /* PB14 periph A AC97RX pin */ + }; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; + atmel,usart-mode = ; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fff98000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfff98000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc1: ssc@fff9c000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfff9c000 0x4000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + clock-names = "pclk"; + status = "disabled"; + }; + + ac97: sound@fffa0000 { + compatible = "atmel,at91sam9263-ac97c"; + reg = <0xfffa0000 0x4000>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ac97>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + clock-names = "ac97_clk"; + status = "disabled"; + }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + usb1: gadget@fff78000 { + compatible = "atmel,at91sam9263-udc"; + reg = <0xfff78000 0x4000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + i2c0: i2c@fff88000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfff88000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + status = "disabled"; + }; + + mmc0: mmc@fff80000 { + compatible = "atmel,hsmci"; + reg = <0xfff80000 0x600>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + mmc1: mmc@fff84000 { + compatible = "atmel,hsmci"; + reg = <0xfff84000 0x600>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + spi0: spi@fffa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffa4000 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffa8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffa8000 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "pwm_clk"; + status = "disabled"; + }; + + can: can@fffac000 { + compatible = "atmel,at91sam9263-can"; + reg = <0xfffac000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "can_clk"; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + rtc@fffffd50 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd50 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x50>; + status = "disabled"; + }; + }; + + fb0: fb@700000 { + compatible = "atmel,at91sam9263-lcdc"; + reg = <0x00700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "lcdc_clk", "hclk"; + status = "disabled"; + }; + + usb0: ohci@a00000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00a00000 0x100000>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + ebi0: ebi@10000000 { + compatible = "atmel,at91sam9263-ebi0"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc0>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller0: nand-controller { + compatible = "atmel,at91sam9260-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + ebi1: ebi@70000000 { + compatible = "atmel,at91sam9263-ebi1"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc1>; + atmel,matrix = <&matrix>; + reg = <0x80000000 0x20000000>; + ranges = <0x0 0x0 0x80000000 0x10000000 + 0x1 0x0 0x90000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller1: nand-controller { + compatible = "atmel,at91sam9260-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9263ek.dts b/arch/arm/boot/dts/microchip/at91sam9263ek.dts new file mode 100644 index 000000000000..ce8baff6a9f4 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9263ek.dts @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9263.dtsi" + +/ { + model = "Atmel at91sam9263ek"; + compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16367660>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usart0: serial@fff8c000 { + pinctrl-0 = < + &pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts>; + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fff78000 { + atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fff80000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff200 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PE19 gpio WP pin pull up */ + }; + }; + }; + + spi0: spi@fffa4000 { + status = "okay"; + cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + fb0: fb@700000 { + display = <&display0>; + status = "okay"; + + display0: panel { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + ebi0: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + + usb0: ohci@a00000 { + num-ports = <2>; + status = "okay"; + atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH + &pioA 21 GPIO_ACTIVE_HIGH + >; + }; + }; + + leds { + compatible = "gpio-leds"; + + d3 { + label = "d3"; + gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + d2 { + label = "d2"; + gpios = <&pioC 29 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-left-click { + label = "left_click"; + gpios = <&pioC 5 GPIO_ACTIVE_LOW>; + linux,code = <272>; + wakeup-source; + }; + + button-right-click { + label = "right_click"; + gpios = <&pioC 4 GPIO_ACTIVE_LOW>; + linux,code = <273>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + + 24c512@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + pagesize = <128>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g15.dtsi b/arch/arm/boot/dts/microchip/at91sam9g15.dtsi new file mode 100644 index 000000000000..dde88276fe52 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g15.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" + +/ { + model = "Atmel AT91SAM9G15 SoC"; + compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; +}; + +&pinctrl { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0x00000000 /* pioA */ + 0x00040000 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; +}; + +&pmc { + compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g15ek.dts b/arch/arm/boot/dts/microchip/at91sam9g15ek.dts new file mode 100644 index 000000000000..889a5097eb2d --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g15ek.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9g15.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G15-EK"; + compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; +}; + +&hlcdc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g20.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20.dtsi new file mode 100644 index 000000000000..738a43ffd228 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g20.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9260.dtsi" + +/ { + model = "Atmel AT91SAM9G20 family SoC"; + compatible = "atmel,at91sam9g20"; + + memory@20000000 { + reg = <0x20000000 0x08000000>; + }; + + sram0: sram@2ff000 { + status = "disabled"; + }; + + sram1: sram@2fc000 { + compatible = "mmio-sram"; + reg = <0x002fc000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x002fc000 0x8000>; + }; + + ahb { + apb { + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9g20-i2c"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91sam9rl-ssc"; + }; + + adc0: adc@fffe0000 { + atmel,adc-startup-time = <40>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g20ek.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek.dts new file mode 100644 index 000000000000..6de7a7cd3c07 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9g20ek_common.dtsi" + +/ { + model = "Atmel at91sam9g20ek"; + compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts new file mode 100644 index 000000000000..2db95e8ffc64 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9g20ek_common.dtsi" + +/ { + model = "Atmel at91sam9g20ek 2 mmc"; + compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; + + ahb { + apb{ + mmc0: mmc@fffa8000 { + /* clk already mux wuth slot0 */ + pinctrl-0 = < + &pinctrl_board_mmc0_slot0 + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff400 { + mmc0_slot0 { + pinctrl_board_mmc0_slot0: mmc0_slot0-board { + atmel,pins = + ; /* PC2 gpio CD pin pull up and deglitch */ + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioB 8 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi new file mode 100644 index 000000000000..024af2db638e --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +#include "at91sam9g20.dtsi" +#include + +/ { + + chosen { + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + ; /* PC1 periph B */ + }; + + }; + + usb1 { + pinctrl_usb1_vbus_gpio: usb1_vbus_gpio { + atmel,pins = + ; /* PC5 GPIO */ + }; + }; + + mmc0_slot1 { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + ; /* PC9 gpio CD pin pull up and deglitch */ + }; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + pinctrl-0 = <&pinctrl_usb1_vbus_gpio>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0_slot1 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; + }; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + spi0: spi@fffc8000 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + flash@1 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + status = "okay"; + + 24c512@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + vcc-supply = <®_3v3>; + }; + + wm8731: wm8731@1b { + compatible = "wm8731"; + reg = <0x1b>; + + /* PCK0 at 12MHz */ + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "mclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; + assigned-clock-rates = <12000000>; + + HPVDD-supply = <&vcc_dac>; + AVDD-supply = <&vcc_dac>; + DCVDD-supply = <®_3v3>; + DBVDD-supply = <®_3v3>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-3 { + label = "Button 3"; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + wakeup-source; + }; + + button-4 { + label = "Button 4"; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + sound { + compatible = "atmel,at91sam9g20ek-wm8731-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_mck>; + + atmel,model = "wm8731 @ AT91SAMG20EK"; + + atmel,audio-routing = + "Ext Spk", "LHPOUT", + "Int Mic", "MICIN"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; + + reg_5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + vin-supply = <®_5v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1v: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "1V"; + vin-supply = <®_5v>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcc_dac: fixedregulator3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_DAC"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts new file mode 100644 index 000000000000..92f2c05c873f --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the GARDENA smart Gateway (Article No. 19000) + * + * Copyright (C) 2020 GARDENA GmbH + */ + +/dts-v1/; + +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" +#include + +/ { + model = "GARDENA smart Gateway (Article No. 19000)"; + compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9g25", "atmel,at91sam9x5", + "atmel,at91sam9"; + + aliases { + serial1 = &usart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button { + label = "USER_BTN1"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + 1wire_cm { + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat { + label = "smartgw:heartbeat"; + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + pb18 { + status = "disabled"; + }; + + pd21 { + status = "disabled"; + }; + }; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&usart0 { + status = "disabled"; +}; + +&usart2 { + status = "disabled"; +}; + +&usart3 { + status = "okay"; + + pinctrl-0 = <&pinctrl_usart3 + &pinctrl_usart3_rts + &pinctrl_usart3_cts + >; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + status = "disabled"; +}; + +&mmc1 { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&adc0 { + status = "disabled"; +}; + +&ssc0 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g25.dtsi b/arch/arm/boot/dts/microchip/at91sam9g25.dtsi new file mode 100644 index 000000000000..ec3c77221881 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g25.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_isi.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" + +/ { + model = "Atmel AT91SAM9G25 SoC"; + compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0xc000001c /* pioA */ + 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ + 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g25ek.dts b/arch/arm/boot/dts/microchip/at91sam9g25ek.dts new file mode 100644 index 000000000000..61b0bdb615dc --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g25ek.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G25-EK"; + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +}; + +&i2c0 { + camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "xvclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; + assigned-clock-rates = <25000000>; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; +}; + +&isi { + status = "okay"; + + port { + isi_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&mmc1 { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g35.dtsi b/arch/arm/boot/dts/microchip/at91sam9g35.dtsi new file mode 100644 index 000000000000..c9cfb93092ee --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g35.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" +#include "at91sam9x5_macb0.dtsi" + +/ { + model = "Atmel AT91SAM9G35 SoC"; + compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0xc000000c /* pioA */ + 0x000406ff 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g35ek.dts b/arch/arm/boot/dts/microchip/at91sam9g35ek.dts new file mode 100644 index 000000000000..f966b56de63c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g35ek.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9g35.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G35-EK"; + compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; +}; + +&hlcdc { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi new file mode 100644 index 000000000000..498cb92b29f9 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi @@ -0,0 +1,1023 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC + * applies to AT91SAM9G45, AT91SAM9M10, + * AT91SAM9G46, AT91SAM9M11 SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9G45 family SoC"; + compatible = "atmel,at91sam9g45"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + ramc0: ramc@ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; + clock-names = "ddrck"; + }; + + ramc1: ramc@ffffe600 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe600 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; + clock-names = "ddrck"; + }; + + smc: smc@ffffe800 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffe800 0x200>; + }; + + matrix: matrix@ffffea00 { + compatible = "atmel,at91sam9g45-matrix", "syscon"; + reg = <0xffffea00 0x200>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9g45-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + + shdwc@fffffd10 { + compatible = "atmel,at91sam9rl-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff7c000 0x100>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + tcb1: timer@fffd4000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffd4000 0x100>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "dma_clk"; + }; + + pinctrl@fffff200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + + atmel,mux-mask = < + /* A B */ + 0xffffffff 0xffc003ff /* pioA */ + 0xffffffff 0x800f8f00 /* pioB */ + 0xffffffff 0x00000e00 /* pioC */ + 0xffffffff 0xff0c1381 /* pioD */ + 0xffffffff 0x81ffff81 /* pioE */ + >; + + /* shared pinctrl settings */ + ac97 { + pinctrl_ac97: ac97-0 { + atmel,pins = + ; /* AC97CK */ + }; + }; + + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = ; + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = ; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = ; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = ; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = ; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = ; + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = ; + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = ; + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = ; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* PA20 periph A TWD0 */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* PB10 periph A TWD1 */ + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* HSYNC */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* D9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* D11 */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PB17 periph B */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PB15 periph B */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; /* PD16 periph A */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; /* PD17 periph A */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PC9 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PC11 periph B */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; /* PA23 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; /* PA24 periph B */ + }; + }; + + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + ; /* PA19 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + ; /* PA30 periph B */ + }; + }; + + mmc0 { + pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA2 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA5 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { + atmel,pins = + ; /* PA9 periph A with pullup */ + }; + }; + + mmc1 { + pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA23 periph A with pullup */ + }; + + pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { + atmel,pins = + ; /* PA26 periph A with pullup */ + }; + + pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { + atmel,pins = + ; /* PA30 periph A with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PD2 periph A */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PD5 periph A */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + ; /* PD12 periph A */ + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + ; /* PD15 periph A */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PB2 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PB16 periph A SPI1_SPCK pin */ + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + ; /* PE30 periph A */ + }; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + }; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + atmel,usart-mode = ; + reg = <0xffffee00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; + atmel,usart-mode = ; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fff98000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff98000 0x200>; + atmel,usart-mode = ; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "usart"; + status = "disabled"; + }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + trng@fffcc000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfffcc000 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + }; + + i2c0: i2c@fff84000 { + compatible = "atmel,at91sam9g10-i2c"; + reg = <0xfff84000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + status = "disabled"; + }; + + i2c1: i2c@fff88000 { + compatible = "atmel,at91sam9g10-i2c"; + reg = <0xfff88000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + status = "disabled"; + }; + + ssc0: ssc@fff9c000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfff9c000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc1: ssc@fffa0000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfffa0000 0x4000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + clock-names = "pclk"; + status = "disabled"; + }; + + ac97: sound@fffac000 { + compatible = "atmel,at91sam9263-ac97c"; + reg = <0xfffac000 0x4000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ac97>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "ac97_clk"; + status = "disabled"; + }; + + adc0: adc@fffb0000 { + compatible = "atmel,at91sam9g45-adc"; + reg = <0xfffb0000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0xff>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + }; + + isi@fffb4000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xfffb4000 0x4000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + status = "disabled"; + }; + + mmc0: mmc@fff80000 { + compatible = "atmel,hsmci"; + reg = <0xfff80000 0x600>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + mmc1: mmc@fffd0000 { + compatible = "atmel,hsmci"; + reg = <0xfffd0000 0x600>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; + dma-names = "rxtx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + spi0: spi@fffa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffa4000 0x200>; + interrupts = <14 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffa8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffa8000 0x200>; + interrupts = <15 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + usb2: gadget@fff78000 { + compatible = "atmel,at91sam9g45-udc"; + reg = <0x00600000 0x80000 + 0xfff78000 0x400>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + clk32k: clock-controller@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <0>; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + rtc@fffffdb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffdb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; + }; + + fb0: fb@500000 { + compatible = "atmel,at91sam9g45-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "hclk", "lcdc_clk"; + status = "disabled"; + }; + + usb0: ohci@700000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb1: ehci@800000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00800000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9g45-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ + &pioA 21 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <5>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts new file mode 100644 index 000000000000..7f45e81ca165 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9g45.dtsi" +#include + +/ { + model = "Atmel AT91SAM9M10G45-EK"; + compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; + stdout-path = "serial0:115200n8"; + }; + + memory@70000000 { + reg = <0x70000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usart1: serial@fff90000 { + pinctrl-0 = + <&pinctrl_usart1 + &pinctrl_usart1_rts + &pinctrl_usart1_cts>; + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + i2c0: i2c@fff84000 { + status = "okay"; + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; + clock-names = "xvclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + i2c1: i2c@fff88000 { + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + mmc0: mmc@fff80000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; + }; + }; + + mmc1: mmc@fffd0000 { + pinctrl-0 = < + &pinctrl_board_mmc1 + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff200 { + camera_sensor { + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + }; + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD10 gpio CD pin pull up and deglitch */ + }; + }; + + mmc1 { + pinctrl_board_mmc1: mmc1-board { + atmel,pins = + ; /* PD29 gpio WP pin pull up */ + }; + }; + + pwm0 { + pinctrl_pwm_leds: pwm-led { + atmel,pins = + ; /* PD31 periph B */ + }; + }; + }; + + spi0: spi@fffa4000{ + status = "okay"; + cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <13000000>; + reg = <0>; + }; + }; + + usb2: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ac97: sound@fffac000 { + status = "okay"; + }; + + adc0: adc@fffb0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + + isi@fffb4000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + status = "okay"; + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + pwm0: pwm@fffb8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_leds>; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + gpbr: syscon@fffffd60 { + status = "okay"; + }; + + rtc@fffffdb0 { + status = "okay"; + }; + }; + + fb0: fb@500000 { + display = <&display0>; + status = "okay"; + + display0: panel { + bits-per-pixel = <32>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <9>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <1>; + hfront-porch = <1>; + vback-porch = <40>; + vfront-porch = <1>; + hsync-len = <45>; + vsync-len = <1>; + }; + }; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "bootstrap/uboot/kernel"; + reg = <0x0 0x400000>; + }; + + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + data@4000000 { + label = "data"; + reg = <0x4000000 0xC000000>; + }; + }; + }; + }; + }; + + usb0: ohci@700000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW + &pioD 3 GPIO_ACTIVE_LOW>; + }; + + usb1: ehci@800000 { + status = "okay"; + }; + }; + + led-controller-1 { + compatible = "gpio-leds"; + + led-1 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-controller-2 { + compatible = "pwm-leds"; + + led-2 { + label = "d6"; + pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "nand-disk"; + }; + + led-3 { + label = "d7"; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "mmc0"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-left-click { + label = "left_click"; + gpios = <&pioB 6 GPIO_ACTIVE_LOW>; + linux,code = <272>; + wakeup-source; + }; + + button-right-click { + label = "right_click"; + gpios = <&pioB 7 GPIO_ACTIVE_LOW>; + linux,code = <273>; + wakeup-source; + }; + + button-left { + label = "Joystick Left"; + gpios = <&pioB 14 GPIO_ACTIVE_LOW>; + linux,code = <105>; + }; + + button-right { + label = "Joystick Right"; + gpios = <&pioB 15 GPIO_ACTIVE_LOW>; + linux,code = <106>; + }; + + button-up { + label = "Joystick Up"; + gpios = <&pioB 16 GPIO_ACTIVE_LOW>; + linux,code = <103>; + }; + + button-down { + label = "Joystick Down"; + gpios = <&pioB 17 GPIO_ACTIVE_LOW>; + linux,code = <108>; + }; + + button-enter { + label = "Joystick Press"; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + linux,code = <28>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi new file mode 100644 index 000000000000..0e28101b26bf --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi @@ -0,0 +1,799 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Hong Xu + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9N12 SoC"; + compatible = "atmel,at91sam9n12"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + ssc0 = &ssc0; + pwm0 = &pwm0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x8000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + matrix: matrix@ffffde00 { + compatible = "atmel,at91sam9n12-matrix", "syscon"; + reg = <0xffffde00 0x100>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x600>, + <0xffffe600 0x200>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; + clock-names = "ddrck"; + }; + + smc: smc@ffffea00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x200>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9n12-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + }; + + reset-controller@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + clk32k: clock-controller@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <0>; + }; + + mmc0: mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf8008000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf800c000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9n12-hlcdc"; + reg = <0xf8038000 0x2000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "dma_clk"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe07983 0x00000000 /* pioA */ + 0x00040000 0x00047e0f 0x00000000 /* pioB */ + 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; /* PA0 periph A */ + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PA2 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PA3 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; /* PA5 periph A */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; /* PA7 periph A */ + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PB0 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PB1 periph B */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; /* PC22 periph B */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; /* PC25 periph B */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* PC8 periph C */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; + }; + }; + + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA15 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA20 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { + atmel,pins = + ; /* PA14 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PA29 periph B */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA13 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PA23 periph B SPI1_SPCK pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, + <&dma 0 AT91_DMA_CFG_PER_ID(22)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x4000>; + atmel,usart-mode = ; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x4000>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x4000>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x4000>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma 1 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, + <&dma 1 AT91_DMA_CFG_PER_ID(16)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + status = "disabled"; + }; + + spi0: spi@f0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0000000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma 1 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + status = "disabled"; + }; + + usb1: gadget@f803c000 { + compatible = "atmel,at91sam9260-udc"; + reg = <0xf803c000 0x4000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + }; + + usb0: ohci@500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x00100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9x5-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9n12ek.dts b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts new file mode 100644 index 000000000000..4c644d4c6be7 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Hong Xu + */ +/dts-v1/; +#include "at91sam9n12.dtsi" + +/ { + model = "Atmel AT91SAM9N12-EK"; + compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; + + chosen { + bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + ssc0: ssc@f0010000 { + status = "okay"; + }; + + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "mclk"; + }; + + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + }; + }; + + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PA7 gpio CD pin pull up and deglitch */ + }; + }; + + qt1070 { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + }; + + sound { + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; + }; + }; + + usb1 { + pinctrl_usb1_vbus_sense: usb1_vbus_sense { + atmel,pins = + ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ + }; + }; + }; + + spi0: spi@f0000000 { + status = "okay"; + cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; + flash@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + hlcdc: hlcdc@f8038000 { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + usb1: gadget@f803c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus_sense>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-ecc-strength = <2>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; + }; + }; + + usb0: ohci@500000 { + num-ports = <1>; + atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "okay"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + d8 { + label = "d8"; + gpios = <&pioB 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + d9 { + label = "d9"; + gpios = <&pioB 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + + d10 { + label = "d10"; + gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-enter { + label = "Enter"; + gpios = <&pioB 3 GPIO_ACTIVE_LOW>; + linux,code = <28>; + wakeup-source; + }; + }; + + panel: panel { + compatible = "qiaodian,qd43003c0-40"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ AT91SAM9N12"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi new file mode 100644 index 000000000000..d7e8a115c916 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC + * + * Copyright (C) 2014 Microchip + * Alexandre Belloni + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9RL family SoC"; + compatible = "atmel,at91sam9rl", "atmel,at91sam9"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x04000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fb0: fb@500000 { + compatible = "atmel,at91sam9rl-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "hclk", "lcdc_clk"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9rl-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffa0000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, + <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + mmc0: mmc@fffa4000 { + compatible = "atmel,hsmci"; + reg = <0xfffa4000 0x600>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@fffa8000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffa8000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + status = "disabled"; + }; + + i2c1: i2c@fffac000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffac000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fffbc000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffbc000 0x200>; + atmel,usart-mode = ; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fffc0000 { + compatible = "atmel,at91sam9rl-ssc"; + reg = <0xfffc0000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + + ssc1: ssc@fffc4000 { + compatible = "atmel,at91sam9rl-ssc"; + reg = <0xfffc4000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + status = "disabled"; + }; + + pwm0: pwm@fffc8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffc8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "pwm_clk"; + status = "disabled"; + }; + + spi0: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + adc0: adc@fffd0000 { + compatible = "atmel,at91sam9rl-adc"; + reg = <0xfffd0000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0x3f>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + }; + + usb0: gadget@fffd4000 { + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00600000 0x100000>, + <0xfffd4000 0x4000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9rl-dma"; + reg = <0xffffe600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "dma_clk"; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + smc: smc@ffffec00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffec00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9rl-matrix", "syscon"; + reg = <0xffffee00 0x200>; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + + atmel,mux-mask = + /* A B */ + <0xffffffff 0xe05c6738>, /* pioA */ + <0xffffffff 0x0000c780>, /* pioB */ + <0xffffffff 0xe3ffff0e>, /* pioC */ + <0x003fffff 0x0001ff3c>; /* pioD */ + + /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_ts: adc0_ts-0 { + atmel,pins = + , + , + , + ; + }; + + pinctrl_adc0_ad0: adc0_ad0-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad1: adc0_ad1-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad2: adc0_ad2-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad3: adc0_ad3-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad4: adc0_ad4-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad5: adc0_ad5-0 { + atmel,pins = ; + }; + + pinctrl_adc0_adtrg: adc0_adtrg-0 { + atmel,pins = ; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + , + ; + }; + }; + + ebi { + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + , + ; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + , + ; + }; + }; + + i2c_gpio1 { + pinctrl_i2c_gpio1: i2c_gpio1-0 { + atmel,pins = + , + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + , + , + ; + }; + }; + + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + , + ; + }; + }; + + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_dcd: usart0_dcd-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_ri: usart0_ri-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + ; + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9rl-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + clk32k: clock-controller@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <0>; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; + + rtc@fffffe00 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffe00 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio1>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9rlek.dts b/arch/arm/boot/dts/microchip/at91sam9rlek.dts new file mode 100644 index 000000000000..a57351270551 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9rlek.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board + * + * Copyright (C) 2014 Microchip + * Alexandre Belloni + */ +/dts-v1/; +#include "at91sam9rl.dtsi" + +/ { + model = "Atmel at91sam9rlek"; + compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; + + chosen { + bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + fb0: fb@500000 { + display = <&display0>; + status = "okay"; + + display0: panel { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr_nand>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + mmc0: mmc@fffa4000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = < + &pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts>; + status = "okay"; + }; + + adc0: adc@fffd0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_adtrg>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + + usb0: gadget@fffd4000 { + atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffcc000 { + status = "okay"; + cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + pwm0: pwm@fffc8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, + <&pinctrl_pwm0_pwm2_2>; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; + }; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + }; + + rtc@fffffe00 { + status = "okay"; + }; + }; + }; + + led-controller-1 { + compatible = "pwm-leds"; + + led-1 { + label = "ds1"; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + }; + + led-2 { + label = "ds2"; + pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + + led-3 { + label = "ds3"; + gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-right-click { + label = "right_click"; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; + linux,code = <273>; + wakeup-source; + }; + + button-left-click { + label = "left_click"; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; + linux,code = <272>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; + + i2c-gpio-1 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x25.dtsi b/arch/arm/boot/dts/microchip/at91sam9x25.dtsi new file mode 100644 index 000000000000..7036f5f04571 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x25.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_macb1.dtsi" +#include "at91sam9x5_can.dtsi" + +/ { + model = "Atmel AT91SAM9X25 SoC"; + compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xc000001c /* pioA */ + 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ + 0x80000000 0xfffd0000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x25ek.dts b/arch/arm/boot/dts/microchip/at91sam9x25ek.dts new file mode 100644 index 000000000000..ad7c6b36f0ba --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x25ek.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9x25.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9X25-EK"; + compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&macb1 { + phy-mode = "rmii"; + status = "okay"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm0_1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x35.dtsi b/arch/arm/boot/dts/microchip/at91sam9x35.dtsi new file mode 100644 index 000000000000..eb03b0497e37 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x35.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_can.dtsi" + +/ { + model = "Atmel AT91SAM9X35 SoC"; + compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xc000000c /* pioA */ + 0x000406ff 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x35ek.dts b/arch/arm/boot/dts/microchip/at91sam9x35ek.dts new file mode 100644 index 000000000000..66675c787b97 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x35ek.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ +/dts-v1/; +#include "at91sam9x35.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9X35-EK"; + compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; +}; + +&backlight { + status = "okay"; +}; + +&bl_reg { + status = "okay"; +}; + +&hlcdc { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&panel_reg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi new file mode 100644 index 000000000000..0123ee47151c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi @@ -0,0 +1,978 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC + * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, + * AT91SAM9X25, AT91SAM9X35 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel AT91SAM9x5 family SoC"; + compatible = "atmel,at91sam9x5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + pwm0 = &pwm0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x8000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + matrix: matrix@ffffde00 { + compatible = "atmel,at91sam9x5-matrix", "syscon"; + reg = <0xffffde00 0x100>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x600>, + <0xffffe600 0x200>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; + clock-names = "ddrck"; + }; + + smc: smc@ffffea00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x200>; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,at91sam9x5-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + shutdown_controller: shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + clk32k: clock-controller@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <0>; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf8008000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf800c000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + dma0: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "dma_clk"; + }; + + dma1: dma-controller@ffffee00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffee00 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "dma_clk"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_8_15: ebi-data-msb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PA2 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PA3 periph A */ + }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + ; /* PA4 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; /* PC27 periph C */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; /* PC28 periph C */ + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + ; /* PC29 periph C */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PB0 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PB1 periph B */ + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + ; /* PB2 periph B */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* PC9 periph C with pullup */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* PC17 periph C with pullup */ + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA15 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA20 periph A with pullup */ + }; + }; + + mmc1 { + pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA11 periph B with pullup */ + }; + + pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { + atmel,pins = + ; /* PA4 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PA29 periph B */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA13 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PA23 periph B SPI1_SPCK pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* PA31 periph A I2C0 clock */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* PC1 periph C I2C1 clock */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* PB5 periph B I2C2 clock */ + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + ; /* PA31 gpio multidrive I2C0 clock */ + }; + }; + + i2c_gpio1 { + pinctrl_i2c_gpio1: i2c_gpio1-0 { + atmel,pins = + ; /* PC1 gpio multidrive I2C1 clock */ + }; + }; + + i2c_gpio2 { + pinctrl_i2c_gpio2: i2c_gpio2-0 { + atmel,pins = + ; /* PB5 gpio multidrive I2C2 clock */ + }; + }; + + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <19>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + }; + + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + status = "disabled"; + }; + + mmc0: mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + compatible = "atmel,hsmci"; + reg = <0xf000c000 0x600>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x200>; + atmel,usart-mode = ; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x200>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x200>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + status = "disabled"; + }; + + i2c2: i2c@f8018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8018000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + status = "disabled"; + }; + + uart0: serial@f8040000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8040000 0x200>; + atmel,usart-mode = ; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8044000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8044000 0x200>; + atmel,usart-mode = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + status = "disabled"; + }; + + adc0: adc@f804c000 { + compatible = "atmel,at91sam9x5-adc"; + reg = <0xf804c000 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0xffff>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + atmel,adc-sample-hold-time = <11>; + }; + + spi0: spi@f0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0000000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + usb2: gadget@f803c000 { + compatible = "atmel,at91sam9g45-udc"; + reg = <0x00500000 0x80000 + 0xf803c000 0x400>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + watchdog: watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + rtc: rtc@fffffeb0 { + compatible = "atmel,at91sam9x5-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + usb0: ohci@600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb1: ehci@700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9x5-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ + &pioC 1 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio1>; + status = "disabled"; + }; + + i2c-gpio-2 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi new file mode 100644 index 000000000000..04ccb25d342c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + can0: can@f8000000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; + clock-names = "can_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* CANTX0, conflicts with DTXD */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* CANTX1, conflicts with TXD1 */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi new file mode 100644 index 000000000000..4ce98f05d7db --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * Image Sensor Interface. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff400 { + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_VSYNC, conflicts with LCDDAT13 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with LCDDAT9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with LCDDAT11 */ + }; + }; + }; + + isi: isi@f8048000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf8048000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi new file mode 100644 index 000000000000..f81c9d1691e0 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * LCD controller. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9x5-hlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + }; + }; +}; + +&pinctrl { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi new file mode 100644 index 000000000000..222aa30f6860 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + ; /* PB10 periph A */ + }; + + pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { + atmel,pins = + ; /* PB17 periph A */ + }; + }; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi new file mode 100644 index 000000000000..26bf9b5de9ee --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 + * Ethernet interfaces. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + ; /* PC31 periph B */ + }; + }; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi new file mode 100644 index 000000000000..a47c765e1b20 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * 4 USART. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include +#include + +/ { + aliases { + serial4 = &usart3; + }; + + ahb { + apb { + pinctrl@fffff400 { + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; /* PC25 periph B */ + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + ; /* PC26 periph B */ + }; + }; + }; + + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + atmel,usart-mode = ; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi new file mode 100644 index 000000000000..cdd37f67280b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ + +/ { + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + tcb0: timer@f8008000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + pinctrl@fffff400 { + 1wire_cm { + pinctrl_1wire_cm: 1wire_cm-0 { + atmel,pins = ; /* PB18 multidrive, conflicts with led */ + }; + }; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr_nand + &pinctrl_ebi_data_0_7>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <2>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label = "U-Boot Env Redundant"; + reg = <0x100000 0x40000>; + }; + + ubootenv@140000 { + label = "U-Boot Env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pb18 { + label = "pb18"; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + pd21 { + label = "pd21"; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; + }; + }; + + 1wire_cm { + compatible = "w1-gpio"; + gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; + linux,open-drain; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_1wire_cm>; + status = "okay"; + }; + +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi new file mode 100644 index 000000000000..a9278038af3b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module + * + * Copyright (C) 2014 Atmel, + * 2014 Free Electrons + * + * Author: Boris Brezillon + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "disabled"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "disabled"; + }; + + panel: panel { + compatible = "foxlink,fl500wvr00-a0t"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; +}; + +&adc0 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; +}; + +&i2c0 { + keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <7 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; +}; + +&hlcdc { + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; +}; + +&pinctrl { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi new file mode 100644 index 000000000000..5f4eaa618ab4 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + */ +#include "at91sam9x5cm.dtsi" + +/ { + model = "Atmel AT91SAM9X5-EK"; + compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + sound { + compatible = "atmel,sam9x5-wm8731-audio"; + + atmel,model = "wm8731 @ AT91SAM9X5EK"; + + atmel,audio-routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; +}; + +&adc0 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + wm8731: wm8731@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; +}; + +&mmc0 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc1 { + pinctrl-0 = < + &pinctrl_board_mmc1 + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + camera_sensor { + pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { + atmel,pins = + ; /* ISI_MCK */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; + + mmc1 { + pinctrl_board_mmc1: mmc1-board { + atmel,pins = + ; /* PD14 gpio CD pin pull up and deglitch */ + }; + }; + + usb2 { + pinctrl_board_usb2: usb2-board { + atmel,pins = + ; /* PB16 gpio vbus sense, deglitch */ + }; + }; +}; + +&spi0 { + cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; + status = "disabled"; /* conflicts with mmc1 */ + + flash@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&ssc0 { + status = "okay"; +}; + +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_usb2>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9xe.dtsi b/arch/arm/boot/dts/microchip/at91sam9xe.dtsi new file mode 100644 index 000000000000..f571f77779c3 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91sam9xe.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC + * + * Copyright (C) 2015 Atmel, + * 2015 Alexandre Belloni + */ + +#include "at91sam9260.dtsi" + +/ { + model = "Atmel AT91SAM9XE family SoC"; + compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; + + sram0: sram@2ff000 { + status = "disabled"; + }; + + sram1: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x4000>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/ethernut5.dts b/arch/arm/boot/dts/microchip/ethernut5.dts new file mode 100644 index 000000000000..ad7a0850252a --- /dev/null +++ b/arch/arm/boot/dts/microchip/ethernut5.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ethernut5.dts - Device Tree file for Ethernut 5 board + * + * Copyright (C) 2012 egnite GmbH + */ +/dts-v1/; +#include "at91sam9xe.dtsi" + +/ { + model = "Ethernut 5"; + compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; + }; + + memory@20000000 { + reg = <0x20000000 0x08000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs>; + pinctrl-names = "default"; + + nand: nand@3 { + reg = <0x3 0x0 0x800000>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + root@0 { + label = "root"; + reg = <0x0 0x08000000>; + }; + + data@20000 { + label = "data"; + reg = <0x08000000 0x38000000>; + }; + }; + }; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + status = "okay"; + + pcf8563@50 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/evk-pro3.dts b/arch/arm/boot/dts/microchip/evk-pro3.dts new file mode 100644 index 000000000000..6d519d02d190 --- /dev/null +++ b/arch/arm/boot/dts/microchip/evk-pro3.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 + * + * Copyright (C) 2012 Telit, + * 2012 Fabio Porcedda + */ + +/dts-v1/; + +#include "ge863-pro3.dtsi" + +/ { + model = "Telit EVK-PRO3 for Telit GE863-PRO3"; + compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + }; + + ahb { + apb { + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart2: serial@fffb8000 { + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; + +}; diff --git a/arch/arm/boot/dts/microchip/ge863-pro3.dtsi b/arch/arm/boot/dts/microchip/ge863-pro3.dtsi new file mode 100644 index 000000000000..dbba33e5a06c --- /dev/null +++ b/arch/arm/boot/dts/microchip/ge863-pro3.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 + * + * Copyright (C) 2012 Telit, + * 2012 Fabio Porcedda + */ + +#include "at91sam9260.dtsi" + +/ { + clocks { + main_xtal { + clock-frequency = <6000000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "boot"; + reg = <0x0 0x7c0000>; + }; + + root@7c0000 { + label = "root"; + reg = <0x7c0000 0x7840000>; + }; + }; + }; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts new file mode 100644 index 000000000000..0f555eb45bda --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 6G-2GS"; + compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; + + aliases { + i2c0 = &i2c4; + i2c1 = &i2c1; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c4>; + los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx1 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c1: i2c@600 { + pinctrl-0 = <&fc1_c_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c4: i2c@600 { + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&gpio { + fc1_c_pins: fc1-c-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_47", "GPIO_48"; + function = "fc1_c"; + }; + + fc4_b_pins: fc4-b-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; +}; + +&port2 { + phys = <&serdes 2 SERDES6G(0)>; + sfp = <&sfp0>; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; + +&port3 { + phys = <&serdes 3 SERDES6G(1)>; + sfp = <&sfp1>; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts new file mode 100644 index 000000000000..5feef9a59a79 --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 8G + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 8G"; + compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; +}; + +&mdio0 { + phy2: ethernet-phy@3 { + reg = <3>; + }; + + phy3: ethernet-phy@4 { + reg = <4>; + }; +}; + +&port2 { + phys = <&serdes 2 SERDES6G(0)>; + phy-handle = <&phy2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&port3 { + phys = <&serdes 3 SERDES6G(1)>; + phy-handle = <&phy3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi new file mode 100644 index 000000000000..0097e72e3fb2 --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common part of the device tree for the Kontron KSwitch D10 MMT + */ + +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + aliases { + serial0 = &usart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + usart0: serial@200 { + pinctrl-0 = <&usart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + spi3: spi@400 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* SCK, MISO, MOSI */ + pins = "GPIO_51", "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + miim_c_pins: miim-c-pins { + /* MDC, MDIO */ + pins = "GPIO_59", "GPIO_60"; + function = "miim_c"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1 */ + pins = "GPIO_32", "GPIO_33", "GPIO_34"; + function = "sgpio_a"; + }; + + sgpio_b_pins: sgpio-b-pins { + /* LD */ + pins = "GPIO_64"; + function = "sgpio_b"; + }; + + usart0_pins: usart0-pins { + /* RXD, TXD */ + pins = "GPIO_25", "GPIO_26"; + function = "fc0_b"; + }; + + usbs_a_pins: usbs-a-pins { + /* VBUS_DET */ + pins = "GPIO_66"; + function = "gpio"; + }; +}; + +&mdio0 { + pinctrl-0 = <&miim_c_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + clock-frequency = <2500000>; + status = "okay"; + + phy4: ethernet-phy@5 { + reg = <5>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; + + phy5: ethernet-phy@6 { + reg = <6>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; + + phy6: ethernet-phy@7 { + reg = <7>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; + + phy7: ethernet-phy@8 { + reg = <8>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phys = <&serdes 0 CU(0)>; + phy-handle = <&phy0>; + phy-mode = "gmii"; + status = "okay"; +}; + +&port1 { + phys = <&serdes 1 CU(1)>; + phy-handle = <&phy1>; + phy-mode = "gmii"; + status = "okay"; +}; + +&port4 { + phys = <&serdes 4 SERDES6G(2)>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port5 { + phys = <&serdes 5 SERDES6G(2)>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port6 { + phys = <&serdes 6 SERDES6G(2)>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port7 { + phys = <&serdes 7 SERDES6G(2)>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>; + pinctrl-names = "default"; + bus-frequency = <8000000>; + /* arbitrary range because all GPIOs are in software mode */ + microchip,sgpio-port-ranges = <0 11>; + status = "okay"; + + sgpio_in: gpio@0 { + ngpios = <128>; + }; + + sgpio_out: gpio@1 { + ngpios = <128>; + }; +}; + +&switch { + status = "okay"; +}; + +&udc { + pinctrl-0 = <&usbs_a_pins>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts new file mode 100644 index 000000000000..8804e8ba5370 --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Horatiu Vultur + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB LAN9668"; + compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966"; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&gpio { + miim_a_pins: mdio-pins { + /* MDC, MDIO */ + pins = "GPIO_28", "GPIO_29"; + function = "miim_a"; + }; + + pps_out_pins: pps-out-pins { + /* 1pps output */ + pins = "GPIO_38"; + function = "ptpsync_3"; + }; + + ptp_ext_pins: ptp-ext-pins { + /* 1pps input */ + pins = "GPIO_35"; + function = "ptpsync_0"; + }; + + udc_pins: ucd-pins { + /* VBUS_DET B */ + pins = "GPIO_8"; + function = "usb_slave_b"; + }; +}; + +&mdio0 { + pinctrl-0 = <&miim_a_pins>; + pinctrl-names = "default"; + status = "okay"; + + ext_phy0: ethernet-phy@7 { + reg = <7>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy1: ethernet-phy@8 { + reg = <8>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy2: ethernet-phy@9 { + reg = <9>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy3: ethernet-phy@10 { + reg = <10>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy4: ethernet-phy@15 { + reg = <15>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy5: ethernet-phy@16 { + reg = <16>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy6: ethernet-phy@17 { + reg = <17>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy7: ethernet-phy@18 { + reg = <18>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; +}; + +&port0 { + reg = <2>; + phy-handle = <&ext_phy2>; + phy-mode = "qsgmii"; + phys = <&serdes 0 SERDES6G(1)>; + status = "okay"; +}; + +&port1 { + reg = <3>; + phy-handle = <&ext_phy3>; + phy-mode = "qsgmii"; + phys = <&serdes 1 SERDES6G(1)>; + status = "okay"; +}; + +&port2 { + reg = <0>; + phy-handle = <&ext_phy0>; + phy-mode = "qsgmii"; + phys = <&serdes 2 SERDES6G(1)>; + status = "okay"; +}; + +&port3 { + reg = <1>; + phy-handle = <&ext_phy1>; + phy-mode = "qsgmii"; + phys = <&serdes 3 SERDES6G(1)>; + status = "okay"; +}; + +&port4 { + reg = <6>; + phy-handle = <&ext_phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 4 SERDES6G(2)>; + status = "okay"; +}; + +&port5 { + reg = <7>; + phy-handle = <&ext_phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 5 SERDES6G(2)>; + status = "okay"; +}; + +&port6 { + reg = <4>; + phy-handle = <&ext_phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 6 SERDES6G(2)>; + status = "okay"; +}; + +&port7 { + reg = <5>; + phy-handle = <&ext_phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 7 SERDES6G(2)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&switch { + pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&udc { + pinctrl-0 = <&udc_pins>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts new file mode 100644 index 000000000000..3a3d76af8612 --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8291.dts - Device Tree file for PCB8291 + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &usart3; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + leds { + compatible = "gpio-leds"; + + led-s0-blue { + label = "s0:blue"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s0-green { + label = "s0:green"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-blue { + label = "s1:blue"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-green { + label = "s1:green"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* RX, TX */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + can0_b_pins: can0-b-pins { + /* RX, TX */ + pins = "GPIO_35", "GPIO_36"; + function = "can0_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; + function = "sgpio_a"; + }; +}; + +&can0 { + pinctrl-0 = <&can0_b_pins>; + pinctrl-names = "default"; + status = "disabled"; /* Conflict with switch */ +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phy-handle = <&phy0>; + phy-mode = "gmii"; + phys = <&serdes 0 CU(0)>; + status = "okay"; +}; + +&port1 { + phy-handle = <&phy1>; + phy-mode = "gmii"; + phys = <&serdes 1 CU(1)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 3>, <8 11>; + status = "okay"; + + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&switch { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8309.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8309.dts new file mode 100644 index 000000000000..0cb505f79ba1 --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8309.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8309.dts - Device Tree file for PCB8309 + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966"; + + aliases { + serial0 = &usart3; + i2c102 = &i2c102; + i2c103 = &i2c103; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux"; + #address-cells = <1>; + #size-cells = <0>; + mux-controls = <&mux>; + i2c-parent = <&i2c4>; + + i2c102: i2c-sfp@1 { + reg = <1>; + }; + + i2c103: i2c-sfp@2 { + reg = <2>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-s0-green { + label = "s0:green"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s0-red { + label = "s0:red"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-green { + label = "s1:green"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-red { + label = "s1:red"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */ + <&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */ + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c102>; + tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c103>; + tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&nic_clk>; + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; + }; +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* RXD, TXD */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + fc4_b_pins: fc4-b-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; + + pps_out_pins: pps-out-pins { + /* 1pps output */ + pins = "GPIO_38"; + function = "ptpsync_3"; + }; + + ptp_ext_pins: ptp-ext-pins { + /* 1pps input */ + pins = "GPIO_39"; + function = "ptpsync_4"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; + function = "sgpio_a"; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phy-handle = <&phy0>; + phy-mode = "gmii"; + phys = <&serdes 0 CU(0)>; + status = "okay"; +}; + +&port1 { + phy-handle = <&phy1>; + phy-mode = "gmii"; + phys = <&serdes 1 CU(1)>; + status = "okay"; +}; + +&port2 { + sfp = <&sfp2>; + managed = "in-band-status"; + phy-mode = "sgmii"; + phys = <&serdes 2 SERDES6G(0)>; + status = "okay"; +}; + +&port3 { + sfp = <&sfp3>; + managed = "in-band-status"; + phy-mode = "sgmii"; + phys = <&serdes 3 SERDES6G(1)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 3>, <8 11>; + status = "okay"; + + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&switch { + pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/lan966x.dtsi b/arch/arm/boot/dts/microchip/lan966x.dtsi new file mode 100644 index 000000000000..05b73f7cf0c7 --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x.dtsi @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Kavyasree Kotagiri + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + model = "Microchip LAN966 family SoC"; + compatible = "microchip,lan966"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <600000000>; + reg = <0x0>; + }; + }; + + clocks { + sys_clk: sys_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <165625000>; + }; + + cpu_clk: cpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + ddr_clk: ddr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + nic_clk: nic_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <37500000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + udc: usb@200000 { + compatible = "microchip,lan9662-udc", + "atmel,sama5d3-udc"; + reg = <0x00200000 0x80000>, + <0xe0808000 0x400>; + interrupts = ; + clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + switch: switch@e0000000 { + compatible = "microchip,lan966x-switch"; + reg = <0xe0000000 0x0100000>, + <0xe2000000 0x0800000>; + reg-names = "cpu", "gcb"; + interrupts = , + , + , + , + ; + interrupt-names = "xtr", "fdma", "ana", "ptp", + "ptp-ext"; + resets = <&reset 0>; + reset-names = "switch"; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + port4: port@4 { + reg = <4>; + status = "disabled"; + }; + + port5: port@5 { + reg = <5>; + status = "disabled"; + }; + + port6: port@6 { + reg = <6>; + status = "disabled"; + }; + + port7: port@7 { + reg = <7>; + status = "disabled"; + }; + }; + }; + + otp: otp@e0021000 { + compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc"; + reg = <0xe0021000 0x300>; + }; + + flx0: flexcom@e0040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + status = "disabled"; + + usart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx1: flexcom@e0044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0044000 0x800>; + status = "disabled"; + + usart1: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + trng: rng@e0048000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&nic_clk>; + }; + + aes: crypto@e004c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "aes_clk"; + }; + + flx2: flexcom@e0060000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0060000 0x800>; + status = "disabled"; + + usart2: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx3: flexcom@e0064000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + status = "disabled"; + + usart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + dma0: dma-controller@e0068000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&nic_clk>; + clock-names = "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&nic_clk>; + clock-names = "sha_clk"; + }; + + flx4: flexcom@e0070000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0070000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0070000 0x800>; + status = "disabled"; + + usart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + timer0: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&nic_clk>; + clock-names = "timer"; + interrupts = ; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = ; + clocks = <&nic_clk>; + status = "disabled"; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible = "microchip,lan966x-cpu-syscon", "syscon"; + reg = <0xe00c0000 0x350>; + }; + + can0: can@e081c000 { + compatible = "bosch,m_can"; + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN0>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e0820000 { + compatible = "bosch,m_can"; + reg = <0xe0820000 0xfc>, <0x00100000 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN1>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + reset: reset-controller@e200400c { + compatible = "microchip,lan966x-switch-reset"; + reg = <0xe200400c 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + + gpio: pinctrl@e2004064 { + compatible = "microchip,lan966x-pinctrl"; + reg = <0xe2004064 0xb4>, + <0xe2010024 0x138>; + resets = <&reset 0>; + reset-names = "switch"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 78>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + mdio0: mdio@e2004118 { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2004118 0x24>; + clocks = <&sys_clk>; + status = "disabled"; + }; + + mdio1: mdio@e200413c { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe200413c 0x24>, + <0xe2010020 0x4>; + clocks = <&sys_clk>; + status = "disabled"; + + phy0: ethernet-phy@1 { + reg = <1>; + interrupts = ; + status = "disabled"; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + interrupts = ; + status = "disabled"; + }; + }; + + sgpio: gpio@e2004190 { + compatible = "microchip,sparx5-sgpio"; + reg = <0xe2004190 0x118>; + clocks = <&sys_clk>; + resets = <&reset 0>; + reset-names = "switch"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgpio_in: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + + hwmon: hwmon@e2010180 { + compatible = "microchip,lan9668-hwmon"; + reg = <0xe2010180 0xc>, + <0xe20042a8 0xc>; + reg-names = "pvt", "fan"; + clocks = <&sys_clk>; + }; + + serdes: serdes@e202c000 { + compatible = "microchip,lan966x-serdes"; + reg = <0xe202c000 0x9c>, + <0xe2004010 0x4>; + #phy-cells = <2>; + status = "disabled"; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupts = ; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>, + <0xe8c14000 0x2000>, + <0xe8c16000 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/mpa1600.dts b/arch/arm/boot/dts/microchip/mpa1600.dts new file mode 100644 index 000000000000..005c2758e229 --- /dev/null +++ b/arch/arm/boot/dts/microchip/mpa1600.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mpa1600.dts - Device Tree file for Phontech MPA 1600 + * + * Copyright (C) 2013 Joachim Eastwood + */ +/dts-v1/; +#include "at91rm9200.dtsi" + +/ { + model = "Phontech MPA 1600"; + compatible = "phontech,mpa1600", "atmel,at91rm9200"; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + ssc0: ssc@fffd0000 { + status = "okay"; + }; + + ssc1: ssc@fffd4000 { + status = "okay"; + }; + }; + + usb0: ohci@300000 { + num-ports = <1>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; + + gpio_keys { + compatible = "gpio-keys"; + + monitor_mute { + label = "Monitor mute"; + gpios = <&pioC 1 GPIO_ACTIVE_LOW>; + linux,code = <113>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/pm9g45.dts b/arch/arm/boot/dts/microchip/pm9g45.dts new file mode 100644 index 000000000000..c349fd3758a6 --- /dev/null +++ b/arch/arm/boot/dts/microchip/pm9g45.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * pm9g45.dts - Device Tree file for Ronetix pm9g45 board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9g45.dtsi" + +/ { + model = "Ronetix pm9g45"; + compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@70000000 { + reg = <0x70000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + pinctrl@fffff200 { + nand { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + }; + + mmc { + pinctrl_board_mmc: mmc0-board { + atmel,pins = + ; /* PD6 gpio CD pin pull_up and deglitch */ + }; + }; + }; + + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + mmc0: mmc@fff80000 { + pinctrl-0 = < + &pinctrl_board_mmc + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; + }; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x1A0000>; + }; + + kernel@200000 { + label = "bareboxenv2"; + reg = <0x200000 0x300000>; + }; + + kernel@500000 { + label = "root"; + reg = <0x500000 0x400000>; + }; + + data@900000 { + label = "data"; + reg = <0x900000 0x8340000>; + }; + }; + }; + }; + }; + + usb0: ohci@700000 { + status = "okay"; + num-ports = <2>; + }; + + usb1: ehci@800000 { + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "led0"; + gpios = <&pioD 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + + led1 { + label = "led1"; + gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + right { + label = "SW4"; + gpios = <&pioE 7 GPIO_ACTIVE_LOW>; + linux,code = <106>; + }; + + up { + label = "SW3"; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + linux,code = <103>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi new file mode 100644 index 000000000000..c8bedfa987e5 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -0,0 +1,1353 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Microchip SAM9X60 SoC"; + compatible = "microchip,sam9x60"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x100000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: gadget@500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sam9x60-udc"; + reg = <0x00500000 0x100000 + 0xf803c000 0x400>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + usb1: ohci@600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "microchip,sam9x60-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + microchip,sfr = <&sfr>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "microchip,sam9x60-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + sdmmc0: sdio-host@80000000 { + compatible = "microchip,sam9x60-sdhci"; + reg = <0x80000000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + sdmmc1: sdio-host@90000000 { + compatible = "microchip,sam9x60-sdhci"; + reg = <0x90000000 0x300>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flx4: flexcom@f0000000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf0000000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0000000 0x800>; + status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf0004000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0004000 0x800>; + status = "disabled"; + + uart5: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; + reg = <0xf0008000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "dma_clk"; + }; + + ssc: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + status = "disabled"; + }; + + qspi: spi@f0014000 { + compatible = "microchip,sam9x60-qspi"; + reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(26))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; + clock-names = "pclk", "qspick"; + atmel,pmc = <&pmc>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2s: i2s@f001c000 { + compatible = "microchip,sam9x60-i2smcc"; + reg = <0xf001c000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf0020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0020000 0x800>; + status = "disabled"; + + uart11: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c11: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf0024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0024000 0x800>; + status = "disabled"; + + uart12: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c12: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + pit64b: timer@f0028000 { + compatible = "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf002c000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "sha_clk"; + }; + + trng: trng@f0030000 { + compatible = "microchip,sam9x60-trng"; + reg = <0xf0030000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + }; + + aes: crypto@f0034000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xf0034000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "aes_clk"; + }; + + tdes: crypto@f0038000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xf0038000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "tdes_clk"; + }; + + classd: classd@f003c000 { + compatible = "atmel,sama5d2-classd"; + reg = <0xf003c000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + can0: can@f8000000 { + compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; + clock-names = "can_clk"; + status = "disabled"; + }; + + tcb0: timer@f8008000 { + compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf8008000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f800c000 { + compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf800c000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; + clock-names = "t0_clk", "slow_clk"; + }; + + flx6: flexcom@f8010000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8010000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8010000 0x800>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8014000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8014000 0x800>; + status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8018000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8018000 0x800>; + status = "disabled"; + + uart8: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c8: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf801c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf801c000 0x800>; + status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8020000 0x800>; + status = "disabled"; + + uart1: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8024000 0x800>; + status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8028000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8028000 0x800>; + status = "disabled"; + + uart3: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,sam9x60-macb", "cdns,macb"; + reg = <0xf802c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,sam9x60-macb", "cdns,macb"; + reg = <0xf8030000 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "microchip,sam9x60-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells = <3>; + status = "disabled"; + }; + + hlcdc: hlcdc@f8038000 { + compatible = "microchip,sam9x60-hlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 25>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + #pwm-cells = <3>; + }; + }; + + flx9: flexcom@f8040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8040000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8040000 0x800>; + status = "disabled"; + + uart9: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c9: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8044000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8044000 0x800>; + status = "disabled"; + + uart10: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c10: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + isi: isi@f8048000 { + compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; + reg = <0xf8048000 0x100>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + adc: adc@f804c000 { + compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; + reg = <0xf804c000 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "adc_clk"; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; + dma-names = "rx"; + atmel,min-sample-rate-hz = <200000>; + atmel,max-sample-rate-hz = <20000000>; + atmel,startup-time-ms = <4>; + atmel,trigger-edge-type = ; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sfr: sfr@f8050000 { + compatible = "microchip,sam9x60-sfr", "syscon"; + reg = <0xf8050000 0x100>; + }; + + matrix: matrix@ffffde00 { + compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; + reg = <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; + clock-names = "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible = "microchip,sam9x60-aic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffff100 0x100>; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + atmel,usart-mode = ; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + + /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xef00019d /* pioA */ + 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ + 0xffffffff 0xffffffff 0xf83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <26>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible = "microchip,sam9x60-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible = "microchip,sam9x60-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k 0>; + }; + + shutdown_controller: shdwc@fffffe10 { + compatible = "microchip,sam9x60-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xfffffe20 0x20>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + pit: timer@fffffe40 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + clk32k: clock-controller@fffffe50 { + compatible = "microchip,sam9x60-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + gpbr: syscon@fffffe60 { + compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; + reg = <0xfffffea8 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible = "microchip,sam9x60-wdt"; + reg = <0xffffff80 0x24>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d2-pinfunc.h b/arch/arm/boot/dts/microchip/sama5d2-pinfunc.h new file mode 100644 index 000000000000..28a2e45752fe --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d2-pinfunc.h @@ -0,0 +1,881 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define PINMUX_PIN(no, func, ioset) \ +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) + +#define PIN_PA0 0 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) +#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) +#define PIN_PA1 1 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) +#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) +#define PIN_PA2 2 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) +#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) +#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) +#define PIN_PA3 3 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) +#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) +#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) +#define PIN_PA4 4 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) +#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) +#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) +#define PIN_PA5 5 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) +#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) +#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) +#define PIN_PA6 6 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) +#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) +#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) +#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) +#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) +#define PIN_PA7 7 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) +#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) +#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) +#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) +#define PIN_PA8 8 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) +#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) +#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) +#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) +#define PIN_PA9 9 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) +#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) +#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) +#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) +#define PIN_PA10 10 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) +#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) +#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) +#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) +#define PIN_PA11 11 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) +#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) +#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) +#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) +#define PIN_PA12 12 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) +#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) +#define PIN_PA13 13 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) +#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) +#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) +#define PIN_PA14 14 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) +#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) +#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) +#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) +#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) +#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) +#define PIN_PA15 15 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) +#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) +#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) +#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) +#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) +#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) +#define PIN_PA16 16 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) +#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) +#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) +#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) +#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) +#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) +#define PIN_PA17 17 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) +#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) +#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) +#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) +#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) +#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) +#define PIN_PA18 18 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) +#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) +#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) +#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) +#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) +#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) +#define PIN_PA19 19 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) +#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) +#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) +#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) +#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) +#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) +#define PIN_PA20 20 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) +#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) +#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) +#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) +#define PIN_PA21 21 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) +#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) +#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) +#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) +#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) +#define PIN_PA22 22 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) +#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) +#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) +#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) +#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) +#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) +#define PIN_PA23 23 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) +#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) +#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) +#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) +#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) +#define PIN_PA24 24 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) +#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) +#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) +#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) +#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) +#define PIN_PA25 25 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) +#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) +#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) +#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) +#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) +#define PIN_PA26 26 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) +#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) +#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) +#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) +#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) +#define PIN_PA27 27 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) +#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) +#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) +#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) +#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) +#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) +#define PIN_PA28 28 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) +#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) +#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) +#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) +#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) +#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) +#define PIN_PA29 29 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) +#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) +#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) +#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) +#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) +#define PIN_PA30 30 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) +#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) +#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) +#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) +#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) +#define PIN_PA31 31 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) +#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) +#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) +#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) +#define PIN_PB0 32 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) +#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) +#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) +#define PIN_PB1 33 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) +#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) +#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) +#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) +#define PIN_PB2 34 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) +#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) +#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) +#define PIN_PB3 35 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) +#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) +#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) +#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) +#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) +#define PIN_PB4 36 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) +#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) +#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) +#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) +#define PIN_PB5 37 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) +#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) +#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) +#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) +#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) +#define PIN_PB6 38 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) +#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) +#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) +#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) +#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) +#define PIN_PB7 39 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) +#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) +#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) +#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) +#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) +#define PIN_PB8 40 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) +#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) +#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) +#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) +#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) +#define PIN_PB9 41 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) +#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) +#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) +#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) +#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) +#define PIN_PB10 42 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) +#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) +#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) +#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) +#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) +#define PIN_PB11 43 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) +#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) +#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) +#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) +#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) +#define PIN_PB12 44 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) +#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) +#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) +#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) +#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) +#define PIN_PB13 45 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) +#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) +#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) +#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) +#define PIN_PB14 46 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) +#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) +#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) +#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) +#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) +#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) +#define PIN_PB15 47 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) +#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) +#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) +#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) +#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) +#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) +#define PIN_PB16 48 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) +#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) +#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) +#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) +#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) +#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) +#define PIN_PB17 49 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) +#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) +#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) +#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) +#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) +#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) +#define PIN_PB18 50 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) +#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) +#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) +#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) +#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) +#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) +#define PIN_PB19 51 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) +#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) +#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) +#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) +#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) +#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) +#define PIN_PB20 52 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) +#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) +#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) +#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) +#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) +#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) +#define PIN_PB21 53 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) +#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) +#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) +#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) +#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) +#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) +#define PIN_PB22 54 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) +#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) +#define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) +#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) +#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) +#define PIN_PB23 55 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) +#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) +#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) +#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) +#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) +#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) +#define PIN_PB24 56 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) +#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) +#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) +#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) +#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) +#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) +#define PIN_PB25 57 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) +#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) +#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) +#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) +#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) +#define PIN_PB26 58 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) +#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) +#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) +#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) +#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) +#define PIN_PB27 59 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) +#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) +#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) +#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) +#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) +#define PIN_PB28 60 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) +#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) +#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) +#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) +#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) +#define PIN_PB29 61 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) +#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) +#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) +#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) +#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) +#define PIN_PB30 62 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) +#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) +#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) +#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) +#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) +#define PIN_PB31 63 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) +#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) +#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) +#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) +#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) +#define PIN_PC0 64 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) +#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) +#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) +#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) +#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) +#define PIN_PC1 65 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) +#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) +#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) +#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) +#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) +#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) +#define PIN_PC2 66 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) +#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) +#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) +#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) +#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) +#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) +#define PIN_PC3 67 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) +#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) +#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) +#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) +#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) +#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) +#define PIN_PC4 68 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) +#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) +#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) +#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) +#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) +#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) +#define PIN_PC5 69 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) +#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) +#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) +#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) +#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) +#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) +#define PIN_PC6 70 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) +#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) +#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) +#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) +#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) +#define PIN_PC7 71 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) +#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) +#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) +#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) +#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) +#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) +#define PIN_PC8 72 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) +#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) +#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) +#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) +#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) +#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) +#define PIN_PC9 73 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) +#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) +#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1) +#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) +#define PIN_PC10 74 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) +#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) +#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) +#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) +#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) +#define PIN_PC11 75 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) +#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) +#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) +#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) +#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) +#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) +#define PIN_PC12 76 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) +#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) +#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) +#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) +#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) +#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) +#define PIN_PC13 77 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) +#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) +#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) +#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) +#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) +#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) +#define PIN_PC14 78 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) +#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) +#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) +#define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) +#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) +#define PIN_PC15 79 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) +#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) +#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) +#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) +#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) +#define PIN_PC16 80 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) +#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) +#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) +#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) +#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) +#define PIN_PC17 81 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) +#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) +#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) +#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) +#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) +#define PIN_PC18 82 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) +#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) +#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) +#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) +#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) +#define PIN_PC19 83 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) +#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) +#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) +#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) +#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) +#define PIN_PC20 84 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) +#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) +#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) +#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) +#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) +#define PIN_PC21 85 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) +#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) +#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) +#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) +#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) +#define PIN_PC22 86 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) +#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) +#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) +#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) +#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) +#define PIN_PC23 87 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) +#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) +#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) +#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) +#define PIN_PC24 88 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) +#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) +#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) +#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) +#define PIN_PC25 89 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) +#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) +#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) +#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) +#define PIN_PC26 90 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) +#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) +#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) +#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) +#define PIN_PC27 91 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) +#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) +#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) +#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) +#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) +#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) +#define PIN_PC28 92 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) +#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) +#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) +#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) +#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) +#define PIN_PC29 93 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) +#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) +#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) +#define PIN_PC30 94 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) +#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) +#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) +#define PIN_PC31 95 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) +#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) +#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) +#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) +#define PIN_PD0 96 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) +#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) +#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) +#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) +#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) +#define PIN_PD1 97 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) +#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) +#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) +#define PIN_PD2 98 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) +#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) +#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) +#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) +#define PIN_PD3 99 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) +#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) +#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) +#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) +#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) +#define PIN_PD4 100 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) +#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) +#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) +#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) +#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) +#define PIN_PD5 101 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) +#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) +#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) +#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) +#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) +#define PIN_PD6 102 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) +#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) +#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) +#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) +#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) +#define PIN_PD7 103 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) +#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) +#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) +#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) +#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) +#define PIN_PD8 104 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) +#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) +#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) +#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) +#define PIN_PD9 105 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) +#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) +#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) +#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) +#define PIN_PD10 106 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) +#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) +#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) +#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) +#define PIN_PD11 107 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) +#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) +#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) +#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) +#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) +#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) +#define PIN_PD12 108 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) +#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) +#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) +#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) +#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) +#define PIN_PD13 109 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) +#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) +#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) +#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) +#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) +#define PIN_PD14 110 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) +#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) +#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) +#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) +#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) +#define PIN_PD15 111 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) +#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) +#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) +#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) +#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) +#define PIN_PD16 112 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) +#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) +#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) +#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) +#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) +#define PIN_PD17 113 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) +#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) +#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) +#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) +#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) +#define PIN_PD18 114 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) +#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) +#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) +#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) +#define PIN_PD19 115 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) +#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) +#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) +#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) +#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) +#define PIN_PD20 116 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) +#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) +#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) +#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) +#define PIN_PD21 117 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) +#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) +#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) +#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) +#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) +#define PIN_PD22 118 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) +#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) +#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) +#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) +#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) +#define PIN_PD23 119 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) +#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) +#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) +#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) +#define PIN_PD24 120 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) +#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) +#define PIN_PD25 121 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) +#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) +#define PIN_PD26 122 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) +#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) +#define PIN_PD27 123 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) +#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) +#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) +#define PIN_PD28 124 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) +#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) +#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) +#define PIN_PD29 125 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) +#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) +#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) +#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) +#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) +#define PIN_PD30 126 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) +#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) +#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) +#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) +#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) +#define PIN_PD31 127 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) +#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) +#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) +#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) +#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi new file mode 100644 index 000000000000..7b6471655dee --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -0,0 +1,1166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC + * + * Copyright (C) 2015 Atmel, + * 2015 Ludovic Desroches + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel SAMA5D2 family SoC"; + compatible = "atmel,sama5d2"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &uart1; + serial1 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + etb@740000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x740000 0x1000>; + + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = <&etm_out>; + }; + }; + }; + }; + + etm@73c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x73c000 0x1000>; + + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + ns_sram: sram@200000 { + compatible = "mmio-sram"; + reg = <0x00200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00200000 0x20000>; + }; + + resistive_touch: resistive-touch { + compatible = "resistive-adc-touch"; + io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, + <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, + <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; + io-channel-names = "x", "y", "pressure"; + touchscreen-min-pressure = <50000>; + status = "disabled"; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nfc_sram: sram@100000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x00100000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00100000 0x2400>; + + }; + + usb0: gadget@300000 { + compatible = "atmel,sama5d3-udc"; + reg = <0x00300000 0x100000 + 0xfc02c000 0x400>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + usb1: ohci@400000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00400000 0x100000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@500000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00500000 0x100000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + L2: cache-controller@a00000 { + compatible = "arm,pl310-cache"; + reg = <0x00a00000 0x1000>; + interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; + cache-unified; + cache-level = <2>; + }; + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x10000000 0x10000000 + 0x60000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x60000000 0x10000000 + 0x2 0x0 0x70000000 0x10000000 + 0x3 0x0 0x80000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + sdmmc0: sdio-host@a0000000 { + compatible = "atmel,sama5d2-sdhci"; + reg = <0xa0000000 0x300>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; + clock-names = "hclock", "multclk", "baseclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 31>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + sdmmc1: sdio-host@b0000000 { + compatible = "atmel,sama5d2-sdhci"; + reg = <0xb0000000 0x300>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; + clock-names = "hclock", "multclk", "baseclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 32>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + nfc_io: nfc-io@c0000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0xc0000000 0x8000000>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d2-hlcdc"; + reg = <0xf0000000 0x2000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + #pwm-cells = <3>; + }; + }; + + isc: isc@f0008000 { + compatible = "atmel,sama5d2-isc"; + reg = <0xf0008000 0x4000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; + clock-names = "hclock", "iscck", "gck"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + status = "disabled"; + }; + + ramc0: ramc@f000c000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf000c000 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "ddrck", "mpddr"; + }; + + dma0: dma-controller@f0010000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0010000 0x1000>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "dma_clk"; + }; + + /* Place dma1 here despite its address */ + dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "dma_clk"; + }; + + pmc: clock-controller@f0014000 { + compatible = "atmel,sama5d2-pmc", "syscon"; + reg = <0xf0014000 0x160>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + + qspi0: spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@f0024000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sha: crypto@f0028000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf0028000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "sha_clk"; + }; + + aes: crypto@f002c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xf002c000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(26))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "aes_clk"; + }; + + spi0: spi@f8000000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8000000 0x100>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssc0: ssc@f8004000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf8004000 0x4000>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "pclk"; + status = "disabled"; + }; + + macb0: ethernet@f8008000 { + compatible = "atmel,sama5d2-gem"; + reg = <0xf8008000 0x1000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ + 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ + 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + tcb0: timer@f800c000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf800c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; + }; + + tcb1: timer@f8010000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf8010000 0x100>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; + }; + + hsmc: hsmc@f8014000 { + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; + reg = <0xf8014000 0x1000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@f8014070 { + compatible = "atmel,sama5d2-pmecc"; + reg = <0xf8014070 0x490>, + <0xf8014500 0x200>; + }; + }; + + pdmic: pdmic@f8018000 { + compatible = "atmel,sama5d2-pdmic"; + reg = <0xf8018000 0x124>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(50))>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + uart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x100>; + atmel,usart-mode = ; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + atmel,usart-mode = ; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; + clock-names = "usart"; + status = "disabled"; + }; + + uart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + atmel,usart-mode = ; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(40))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8028000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + status = "disabled"; + }; + + sfr: sfr@f8030000 { + compatible = "atmel,sama5d2-sfr", "syscon"; + reg = <0xf8030000 0x98>; + }; + + flx0: flexcom@f8034000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8034000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8034000 0x800>; + status = "disabled"; + + uart5: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx1: flexcom@f8038000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8038000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8038000 0x800>; + status = "disabled"; + + uart6: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + securam: sram@f8044000 { + compatible = "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xf8044000 0x1420>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + ranges = <0 0xf8044000 0x1420>; + }; + + reset_controller: reset-controller@f8048000 { + compatible = "atmel,sama5d3-rstc"; + reg = <0xf8048000 0x10>; + clocks = <&clk32k>; + }; + + shutdown_controller: shdwc@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + }; + + pit: timer@f8048030 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xf8048030 0x10>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; + }; + + watchdog: watchdog@f8048040 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xf8048040 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + clk32k: clock-controller@f8048050 { + compatible = "atmel,sama5d4-sckc"; + reg = <0xf8048050 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <0>; + }; + + rtc: rtc@f80480b0 { + compatible = "atmel,sama5d2-rtc"; + reg = <0xf80480b0 0x30>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + + i2s0: i2s@f8050000 { + compatible = "atmel,sama5d2-i2s"; + reg = <0xf8050000 0x100>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; + assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; + status = "disabled"; + }; + + can0: can@f8054000 { + compatible = "bosch,m_can"; + reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; + reg-names = "m_can", "message_ram"; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, + <64 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 56>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + spi1: spi@fc000000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc000000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart3: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + atmel,usart-mode = ; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(41))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(42))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "usart"; + status = "disabled"; + }; + + uart4: serial@fc00c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc00c000 0x100>; + atmel,usart-mode = ; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(43))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(44))>; + dma-names = "tx", "rx"; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "usart"; + status = "disabled"; + }; + + flx2: flexcom@fc010000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xfc010000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfc010000 0x800>; + status = "disabled"; + + uart7: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx3: flexcom@fc014000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xfc014000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfc014000 0x800>; + status = "disabled"; + + uart8: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + }; + + flx4: flexcom@fc018000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xfc018000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfc018000 0x800>; + status = "disabled"; + + uart9: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi6: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + trng@fc01c000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfc01c000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + }; + + aic: interrupt-controller@fc020000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d2-aic"; + interrupt-controller; + reg = <0xfc020000 0x200>; + atmel,external-irqs = <49>; + }; + + i2c1: i2c@fc028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xfc028000 0x100>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + adc: adc@fc030000 { + compatible = "atmel,sama5d2-adc"; + reg = <0xfc030000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "adc_clk"; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; + dma-names = "rx"; + atmel,min-sample-rate-hz = <200000>; + atmel,max-sample-rate-hz = <20000000>; + atmel,startup-time-ms = <4>; + atmel,trigger-edge-type = ; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pioA: pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; + reg = <0xfc038000 0x600>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, + <68 IRQ_TYPE_LEVEL_HIGH 7>, + <69 IRQ_TYPE_LEVEL_HIGH 7>, + <70 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + }; + + pioBU: secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + + gpio-controller; + #gpio-cells = <2>; + }; + + tdes: crypto@fc044000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xfc044000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "tdes_clk"; + }; + + classd: classd@fc048000 { + compatible = "atmel,sama5d2-classd"; + reg = <0xfc048000 0x100>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(47))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + i2s1: i2s@fc04c000 { + compatible = "atmel,sama5d2-i2s"; + reg = <0xfc04c000 0x100>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; + assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>; + status = "disabled"; + }; + + can1: can@fc050000 { + compatible = "bosch,m_can"; + reg = <0xfc050000 0x4000>, <0x210000 0x3800>; + reg-names = "m_can", "message_ram"; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, + <65 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 57>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + sfrbu: sfr@fc05c000 { + compatible = "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xfc05c000 0x20>; + }; + + chipid@fc069000 { + compatible = "atmel,sama5d2-chipid"; + reg = <0xfc069000 0x8>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d29.dtsi b/arch/arm/boot/dts/microchip/sama5d29.dtsi new file mode 100644 index 000000000000..17991c28a256 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d29.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d29.dtsi - Device Tree Include file for SAMA5D29 SoC of the SAMA5D2 + * family. + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Hari Prasath + * + */ + +#include "sama5d2.dtsi" + +&macb0 { + compatible = "atmel,sama5d29-gem"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi new file mode 100644 index 000000000000..0eebf6c760b3 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -0,0 +1,1126 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC + * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel SAMA5D3 family SoC"; + compatible = "atmel,sama5d3", "atmel,sama5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &uart0; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0x0>; + }; + }; + + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x20000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mmc0: mmc@f0000000 { + compatible = "atmel,hsmci"; + reg = <0xf0000000 0x600>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "mci_clk"; + }; + + spi0: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ssc0: ssc@f0008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0008000 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "pclk"; + status = "disabled"; + }; + + tcb0: timer@f0010000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0010000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + i2c0: i2c@f0014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0014000 0x4000>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + status = "disabled"; + }; + + i2c1: i2c@f0018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0018000 0x4000>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + status = "disabled"; + }; + + usart0: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f0020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0020000 0x100>; + atmel,usart-mode = ; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "usart"; + status = "disabled"; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x100>; + atmel,usart-mode = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + status = "disabled"; + }; + + pwm0: pwm@f002c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf002c000 0x300>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + status = "disabled"; + }; + + isi: isi@f0034000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0034000 0x4000>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sfr: sfr@f0038000 { + compatible = "atmel,sama5d3-sfr", "syscon"; + reg = <0xf0038000 0x60>; + }; + + mmc1: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "mci_clk"; + }; + + spi1: spi@f8008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8008000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ssc1: ssc@f800c000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf800c000 0x4000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "pclk"; + status = "disabled"; + }; + + adc0: adc@f8018000 { + compatible = "atmel,sama5d3-adc"; + reg = <0xf8018000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + &pinctrl_adc0_ad8 + &pinctrl_adc0_ad9 + &pinctrl_adc0_ad10 + &pinctrl_adc0_ad11 + >; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0xfff>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3000>; + atmel,adc-sample-hold-time = <11>; + status = "disabled"; + }; + + i2c2: i2c@f801c000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf801c000 0x4000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + status = "disabled"; + }; + + usart2: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + atmel,usart-mode = ; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + atmel,usart-mode = ; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + status = "disabled"; + }; + + sha: crypto@f8034000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf8034000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "sha_clk"; + }; + + aes: crypto@f8038000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xf8038000 0x100>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "aes_clk"; + }; + + tdes: crypto@f803c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xf803c000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names = "tdes_clk"; + }; + + trng@f8040000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xf8040000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; + }; + + hsmc: hsmc@ffffc000 { + compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; + reg = <0xffffc000 0x1000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@ffffc070 { + compatible = "atmel,at91sam9g45-pmecc"; + reg = <0xffffc070 0x490>, + <0xffffc500 0x100>; + }; + }; + + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe600 0x200>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; + clock-names = "dma_clk"; + }; + + dma1: dma-controller@ffffe800 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe800 0x200>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; + clock-names = "dma_clk"; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xffffea00 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; + clock-names = "ddrck", "mpddr"; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + atmel,usart-mode = ; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + clock-names = "usart"; + status = "disabled"; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d3-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <47>; + }; + + pinctrl: pinctrl@fffff200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ + 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ + 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ + 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ + 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ + >; + + /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + ; /* PD19 periph A ADTRG */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + ; /* PD20 periph A AD0 */ + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + ; /* PD21 periph A AD1 */ + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + ; /* PD22 periph A AD2 */ + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + ; /* PD23 periph A AD3 */ + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + ; /* PD24 periph A AD4 */ + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = + ; /* PD25 periph A AD5 */ + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = + ; /* PD26 periph A AD6 */ + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = + ; /* PD27 periph A AD7 */ + }; + pinctrl_adc0_ad8: adc0_ad8 { + atmel,pins = + ; /* PD28 periph A AD8 */ + }; + pinctrl_adc0_ad9: adc0_ad9 { + atmel,pins = + ; /* PD29 periph A AD9 */ + }; + pinctrl_adc0_ad10: adc0_ad10 { + atmel,pins = + ; /* PD30 periph A AD10, conflicts with PCK0 */ + }; + pinctrl_adc0_ad11: adc0_ad11 { + atmel,pins = + ; /* PD31 periph A AD11, conflicts with PCK1 */ + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + ebi { + pinctrl_ebi_addr: ebi-addr-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nand_addr: ebi-addr-1 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs0: ebi-cs0-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs1: ebi-cs1-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs2: ebi-cs2-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwait: ebi-nwait-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { + atmel,pins = + ; + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + atmel,pins = + ; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + atmel,pins = + ; + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ + }; + + pinctrl_i2c2_gpio: i2c2-gpio { + atmel,pins = + ; + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + atmel,pins = + ; /* PD1 periph A MCI0_DA0 with pullup */ + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + atmel,pins = + ; /* PD4 periph A MCI0_DA3 with pullup */ + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + atmel,pins = + ; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ + }; + }; + + mmc1 { + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + atmel,pins = + ; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + atmel,pins = + ; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ + }; + }; + + nand0 { + pinctrl_nand0_ale_cle: nand0_ale_cle-0 { + atmel,pins = + ; /* PE22 periph A with pullup */ + }; + }; + + pwm0 { + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { + atmel,pins = + ; /* conflicts with ISI_D4 and LCDDAT20 */ + }; + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { + atmel,pins = + ; /* conflicts with GTX0 */ + }; + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { + atmel,pins = + ; /* conflicts with ISI_D5 and LCDDAT21 */ + }; + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { + atmel,pins = + ; /* conflicts with GTX1 */ + }; + + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { + atmel,pins = + ; /* conflicts with ISI_D6 and LCDDAT22 */ + }; + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { + atmel,pins = + ; /* conflicts with GRX0 */ + }; + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { + atmel,pins = + ; /* conflicts with G125CKO and RTS1 */ + }; + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { + atmel,pins = + ; /* conflicts with ISI_D7 and LCDDAT23 */ + }; + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { + atmel,pins = + ; /* conflicts with GRX1 */ + }; + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { + atmel,pins = + ; /* conflicts with IRQ */ + }; + + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { + atmel,pins = + ; /* conflicts with GTXCK */ + }; + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { + atmel,pins = + ; /* conflicts with MCI0_DA4 and TIOA0 */ + }; + pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { + atmel,pins = + ; /* conflicts with GTXEN */ + }; + pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { + atmel,pins = + ; /* conflicts with MCI0_DA5 and TIOB0 */ + }; + + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { + atmel,pins = + ; /* conflicts with GRXDV */ + }; + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { + atmel,pins = + ; /* conflicts with MCI0_DA6 and TCLK0 */ + }; + pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { + atmel,pins = + ; /* conflicts with GRXER */ + }; + pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { + atmel,pins = + ; /* conflicts with MCI0_DA7 */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PD12 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PC24 periph A SPI1_SPCK pin */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + ; /* PC18 periph A TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + ; /* PC21 periph A RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + ; /* PB6 periph B TD1, conflicts with TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + ; /* PB11 periph B RD1, conflicts with GRXCK */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* conflicts with TWCK0, ISI_HSYNC */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_rts_cts: usart0_rts_cts-0 { + atmel,pins = + ; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_rts_cts: usart1_rts_cts-0 { + atmel,pins = + ; /* PB27 periph A, conflicts with G125CKO */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; /* conflicts NCS0 */ + }; + + pinctrl_usart2_rts_cts: usart2_rts_cts-0 { + atmel,pins = + ; /* PE24 periph B, conflicts with A24 */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; /* conflicts with A19 */ + }; + + pinctrl_usart3_rts_cts: usart3_rts_cts-0 { + atmel,pins = + ; /* PE17 periph B, conflicts with A17 */ + }; + }; + + + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible = "atmel,sama5d3-pmc", "syscon"; + reg = <0xfffffc00 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + shutdown_controller: shutdown-controller@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + watchdog: watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + clk32k: clock-controller@fffffe50 { + compatible = "atmel,sama5d3-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <0>; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + }; + + nfc_sram: sram@200000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x200000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x2400>; + }; + + usb0: gadget@500000 { + compatible = "atmel,sama5d3-udc"; + reg = <0x00500000 0x100000 + 0xf8030000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + usb1: ohci@600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x40000000 0x10000000 + 0x2 0x0 0x50000000 0x10000000 + 0x3 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + nfc_io: nfc-io@70000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x70000000 0x8000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d31.dtsi b/arch/arm/boot/dts/microchip/sama5d31.dtsi new file mode 100644 index 000000000000..cbe8f275ecc4 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d31.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC + * + * Copyright (C) 2013 Boris BREZILLON + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d31ek.dts b/arch/arm/boot/dts/microchip/sama5d31ek.dts new file mode 100644 index 000000000000..1f2dfb3127ab --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d31ek.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ +/dts-v1/; +#include "sama5d31.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xmb_emac.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D31-EK"; + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + leds { + led-d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d33.dtsi b/arch/arm/boot/dts/microchip/sama5d33.dtsi new file mode 100644 index 000000000000..146fd59acea5 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d33.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC + * + * Copyright (C) 2013 Boris BREZILLON + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" + +/ { + compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d33ek.dts b/arch/arm/boot/dts/microchip/sama5d33ek.dts new file mode 100644 index 000000000000..7d4ae1682933 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d33ek.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ +/dts-v1/; +#include "sama5d33.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xmb_gmac.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D33-EK"; + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d34.dtsi b/arch/arm/boot/dts/microchip/sama5d34.dtsi new file mode 100644 index 000000000000..132918c889a0 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d34.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC + * + * Copyright (C) 2013 Boris BREZILLON + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" + +/ { + compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d34ek.dts b/arch/arm/boot/dts/microchip/sama5d34ek.dts new file mode 100644 index 000000000000..bffd61397cb5 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d34ek.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ +/dts-v1/; +#include "sama5d34.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xmb_gmac.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D34-EK"; + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + 24c256@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + leds { + led-d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d35.dtsi b/arch/arm/boot/dts/microchip/sama5d35.dtsi new file mode 100644 index 000000000000..b2ccfa77c4be --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d35.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC + * + * Copyright (C) 2013 Boris BREZILLON + */ +#include "sama5d3.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" +#include "sama5d3_tcb1.dtsi" + +/ { + compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d35ek.dts b/arch/arm/boot/dts/microchip/sama5d35ek.dts new file mode 100644 index 000000000000..8edfcebb1df0 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d35ek.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ +/dts-v1/; +#include "sama5d35.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xmb_emac.dtsi" +#include "sama5d3xmb_gmac.dtsi" + +/ { + model = "Atmel SAMA5D35-EK"; + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + isi: isi@f0034000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d36.dtsi b/arch/arm/boot/dts/microchip/sama5d36.dtsi new file mode 100644 index 000000000000..5d88f9967138 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d36.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu + */ +#include "sama5d3.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_tcb1.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d36ek.dts b/arch/arm/boot/dts/microchip/sama5d36ek.dts new file mode 100644 index 000000000000..26950f9284c2 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d36ek.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" +#include "sama5d3xmb_emac.dtsi" +#include "sama5d3xmb_gmac.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts b/arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts new file mode 100644 index 000000000000..66695b9a3e77 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board + * + * Copyright (C) 2016 Atmel, + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb_cmp.dtsi" + +/ { + model = "Atmel SAMA5D36EK-CMP"; + compatible = "atmel,sama5d36ek-cmp", "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_can.dtsi b/arch/arm/boot/dts/microchip/sama5d3_can.dtsi new file mode 100644 index 000000000000..9ac29bf3f933 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_can.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with + * CAN support + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + + }; + + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "can_clk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_emac.dtsi b/arch/arm/boot/dts/microchip/sama5d3_emac.dtsi new file mode 100644 index 000000000000..5d7ce13de8cc --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_emac.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with + * Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + ; /* PC9 periph A EMDIO */ + }; + }; + }; + + pmc: clock-controller@fffffc00 { + }; + + macb1: ethernet@f802c000 { + compatible = "atmel,sama5d3-macb", "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi b/arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi new file mode 100644 index 000000000000..884df7a54dbb --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with + * Gigabit Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb0 { + pinctrl_macb0_data_rgmii: macb0_data_rgmii { + atmel,pins = + ; /* PB7 periph A GRX3, conflicts with RK1 */ + }; + pinctrl_macb0_data_gmii: macb0_data_gmii { + atmel,pins = + ; /* PB26 periph B GRX7, conflicts with CTS1 */ + }; + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { + atmel,pins = + ; /* PB18 periph A G125CK */ + }; + pinctrl_macb0_signal_gmii: macb0_signal_gmii { + atmel,pins = + ; /* PB27 periph B G125CKO */ + }; + + }; + }; + + macb0: ethernet@f0028000 { + compatible = "atmel,sama5d3-gem"; + reg = <0xf0028000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi b/arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi new file mode 100644 index 000000000000..308d2fc276d6 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with + * LCD support + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + pinctrl@fffff200 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + + pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi b/arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi new file mode 100644 index 000000000000..7141ee97ec3e --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with + * 3 MMC ports + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + mmc2 { + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { + atmel,pins = + ; /* PC11 periph A MCI2_DA0 with pullup */ + }; + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { + atmel,pins = + ; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + }; + }; + }; + + mmc2: mmc@f8004000 { + compatible = "atmel,hsmci"; + reg = <0xf8004000 0x600>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "mci_clk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi new file mode 100644 index 000000000000..2b18c5c2cc03 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with + * 2 TC blocks. + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include +#include + +/ { + aliases { + tcb1 = &tcb1; + }; + + ahb { + apb { + tcb1: timer@f8014000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf8014000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3_uart.dtsi b/arch/arm/boot/dts/microchip/sama5d3_uart.dtsi new file mode 100644 index 000000000000..44d1173f2ffb --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_uart.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with + * UART support + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include +#include +#include + +/ { + aliases { + serial5 = &uart0; + serial6 = &uart1; + }; + + ahb { + apb { + pinctrl@fffff200 { + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* conflicts with TWCK0, ISI_HSYNC */ + }; + }; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x100>; + atmel,usart-mode = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x100>; + atmel,usart-mode = ; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xcm.dtsi b/arch/arm/boot/dts/microchip/sama5d3xcm.dtsi new file mode 100644 index 000000000000..7d1d7859edb4 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xcm.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ + +/ { + compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + + tcb0: timer@f0010000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + }; + + ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>; + pinctr-name = "default"; + status = "okay"; + + nor: flash@0,0 { + compatible = "cfi-flash"; + linux,mtd-name = "physmap-flash.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x1000000>; + bank-width = <2>; + atmel,smc-read-mode = "nrd"; + atmel,smc-write-mode = "nwe"; + atmel,smc-bus-width = <16>; + atmel,smc-ncs-rd-setup-ns = <0>; + atmel,smc-ncs-wr-setup-ns = <0>; + atmel,smc-nwe-setup-ns = <8>; + atmel,smc-nrd-setup-ns = <16>; + atmel,smc-ncs-rd-pulse-ns = <84>; + atmel,smc-ncs-wr-pulse-ns = <84>; + atmel,smc-nrd-pulse-ns = <76>; + atmel,smc-nwe-pulse-ns = <76>; + atmel,smc-nrd-cycle-ns = <107>; + atmel,smc-nwe-cycle-ns = <84>; + atmel,smc-tdf-ns = <16>; + }; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-d2 { + label = "d2"; + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi new file mode 100644 index 000000000000..830a0954ba1b --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module + * + * Copyright (C) 2016 Atmel, + */ + +/ { + compatible = "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + + tcb0: timer@f0010000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + + i2c1: i2c@f0018000 { + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "disabled"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddana_reg: LDO_REG1 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG2 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + }; + }; + }; + }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-d2 { + label = "d2"; + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xdm.dtsi b/arch/arm/boot/dts/microchip/sama5d3xdm.dtsi new file mode 100644 index 000000000000..3c1c4d62fbf9 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xdm.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d3dm.dtsi - Device Tree file for SAMA5 display module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ + +/ { + ahb { + apb { + i2c1: i2c@f0018000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <31 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + + adc0: adc@f8018000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff200 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; /* PE31 GPIO with pull up deglith */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi new file mode 100644 index 000000000000..3652c9e24124 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + */ +#include "sama5d3xcm.dtsi" + +/ { + compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + }; + + spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + + flash@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "mclk"; + }; + }; + + i2c1: i2c@f0018000 { + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + /* use pck1 for the master clock of ov2640 */ + clocks = <&pmc PMC_TYPE_SYSTEM 9>; + clock-names = "xvclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + status = "okay"; + }; + + pinctrl@fffff200 { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; /* PD17 GPIO with pullup deglitch */ + }; + + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; /* PD18 GPIO with pullup deglitch */ + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; /* PD30 periph B */ + }; + + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + ; /* PD31 periph B ISI_MCK */ + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; /* PE24 gpio */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; /* PE29 gpio */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; /* PD29 GPIO with deglitch */ + }; + }; + }; + + dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@500000 { + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@600000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH + &pioD 26 GPIO_ACTIVE_LOW + &pioD 27 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@700000 { + status = "okay"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi new file mode 100644 index 000000000000..5d9e97fecf83 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board + * + * Copyright (C) 2016 Atmel, + */ +#include "sama5d3xcm_cmp.dtsi" + +/ { + compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + }; + + spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + + flash@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "mclk"; + }; + }; + + i2c1: i2c@f0018000 { + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + /* use pck1 for the master clock of ov2640 */ + clocks = <&pmc PMC_TYPE_SYSTEM 9>; + clock-names = "xvclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + pinctrl-1 = < + &pinctrl_adc0_adtrg_sleep + &pinctrl_adc0_ad0_sleep + &pinctrl_adc0_ad1_sleep + &pinctrl_adc0_ad2_sleep + &pinctrl_adc0_ad3_sleep + &pinctrl_adc0_ad4_sleep + >; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + /*interrupt-parent = <&pioE>;*/ + /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ + reg = <1>; + }; + }; + + pinctrl@fffff200 { + adc0 { + pinctrl_adc0_adtrg_sleep: adc0_adtrg_1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad0_sleep: adc0_ad0_1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad1_sleep: adc0_ad1_1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad2_sleep: adc0_ad2_1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad3_sleep: adc0_ad3_1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad4_sleep: adc0_ad4_1 { + atmel,pins = + ; + }; + }; + + board { + pinctrl_gpio_keys: gpio_keys { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; + }; + + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + }; + }; + + dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@500000 { + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "disabled"; + }; + + /* Conflict with LCD pins */ + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi new file mode 100644 index 000000000000..a5dd41cd9522 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board + * Ethernet + * + * Copyright (C) 2016 Atmel, + */ + +/ { + ahb { + apb { + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + reg = <1>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi new file mode 100644 index 000000000000..d750da38ff3c --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard + * Gigabit Ethernet + * + * Copyright (C) 2016 Atmel, + */ + +/ { + ahb { + apb { + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi new file mode 100644 index 000000000000..de6c82969232 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -0,0 +1,1453 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Atmel SAMA5D4 family SoC"; + compatible = "atmel,sama5d4"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &usart3; + serial1 = &usart4; + serial2 = &usart2; + serial3 = &usart0; + serial4 = &usart1; + serial5 = &uart0; + serial6 = &uart1; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + pwm0 = &pwm0; + ssc0 = &ssc0; + ssc1 = &ssc1; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + ns_sram: sram@210000 { + compatible = "mmio-sram"; + reg = <0x00210000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00210000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nfc_sram: sram@100000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x100000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x100000 0x2400>; + }; + + vdec0: vdec@300000 { + compatible = "microchip,sama5d4-vdec"; + reg = <0x00300000 0x100000>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + }; + + usb0: gadget@400000 { + compatible = "atmel,sama5d3-udc"; + reg = <0x00400000 0x100000 + 0xfc02c000 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + usb1: ohci@500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@600000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00600000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + L2: cache-controller@a00000 { + compatible = "arm,pl310-cache"; + reg = <0x00a00000 0x1000>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; + cache-unified; + cache-level = <2>; + }; + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x10000000 0x10000000 + 0x60000000 0x28000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x60000000 0x10000000 + 0x2 0x0 0x70000000 0x10000000 + 0x3 0x0 0x80000000 0x8000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + nfc_io: nfc-io@90000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x90000000 0x8000000>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d4-hlcdc"; + reg = <0xf0000000 0x4000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; + clock-names = "dma_clk"; + }; + + isi: isi@f0008000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0008000 0x4000>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ramc0: ramc@f0010000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf0010000 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "ddrck", "mpddr"; + }; + + dma0: dma-controller@f0014000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0014000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "dma_clk"; + }; + + pmc: clock-controller@f0018000 { + compatible = "atmel,sama5d4-pmc", "syscon"; + reg = <0xf0018000 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + + mmc0: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(0))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names = "mci_clk"; + }; + + uart0: serial@f8004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8004000 0x100>; + atmel,usart-mode = ; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@f8008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf8008000 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(26))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + clock-names = "pclk"; + status = "disabled"; + }; + + pwm0: pwm@f800c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf800c000 0x300>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + status = "disabled"; + }; + + spi0: spi@f8010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8010000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(10))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + i2c0: i2c@f8014000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8014000 0x4000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(2))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + status = "disabled"; + }; + + i2c1: i2c@f8018000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8018000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + status = "disabled"; + }; + + tcb0: timer@f801c000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf801c000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + macb0: ethernet@f8020000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xf8020000 0x100>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + i2c2: i2c@f8024000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8024000 0x4000>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(6))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + status = "disabled"; + }; + + sfr: sfr@f8028000 { + compatible = "atmel,sama5d4-sfr", "syscon"; + reg = <0xf8028000 0x60>; + }; + + usart0: serial@f802c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf802c000 0x100>; + atmel,usart-mode = ; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8030000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8030000 0x100>; + atmel,usart-mode = ; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + status = "disabled"; + }; + + mmc1: mmc@fc000000 { + compatible = "atmel,hsmci"; + reg = <0xfc000000 0x600>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(1))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names = "mci_clk"; + }; + + uart1: serial@fc004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc004000 0x100>; + atmel,usart-mode = ; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + atmel,usart-mode = ; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(16))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fc00c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc00c000 0x100>; + atmel,usart-mode = ; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(18))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; + clock-names = "usart"; + status = "disabled"; + }; + + usart4: serial@fc010000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc010000 0x100>; + atmel,usart-mode = ; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(20))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart4>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc1: ssc@fc014000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfc014000 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(28))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi1: spi@fc018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc018000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(12))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi2: spi@fc01c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc01c000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + tcb1: timer@fc020000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc020000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb2: timer@fc024000 { + compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc024000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + macb1: ethernet@fc028000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xfc028000 0x100>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + trng@fc030000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfc030000 0x100>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; + }; + + adc0: adc@fc034000 { + compatible = "atmel,at91sam9x5-adc"; + reg = <0xfc034000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0x01f>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3000>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "disabled"; + }; + + aes: crypto@fc044000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xfc044000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(41))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(40))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; + clock-names = "aes_clk"; + }; + + tdes: crpyto@fc04c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xfc04c000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(42))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(43))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "tdes_clk"; + }; + + sha: crypto@fc050000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xfc050000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(44))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "sha_clk"; + }; + + hsmc: smc@fc05c000 { + compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; + reg = <0xfc05c000 0x1000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@ffffc070 { + compatible = "atmel,sama5d4-pmecc"; + reg = <0xfc05c070 0x490>, + <0xfc05c500 0x100>; + }; + }; + + reset_controller: reset-controller@fc068600 { + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; + reg = <0xfc068600 0x10>; + clocks = <&clk32k>; + }; + + shutdown_controller: shdwc@fc068610 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfc068610 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fc068630 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfc068630 0x10>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; + }; + + watchdog: watchdog@fc068640 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xfc068640 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + clk32k: clock-controller@fc068650 { + compatible = "atmel,sama5d4-sckc"; + reg = <0xfc068650 0x4>; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + rtc@fc0686b0 { + compatible = "atmel,sama5d4-rtc"; + reg = <0xfc0686b0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + + dbgu: serial@fc069000 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfc069000 0x200>; + atmel,usart-mode = ; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; + clock-names = "usart"; + status = "disabled"; + }; + + + pinctrl: pinctrl@fc06a000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; + ranges = <0xfc068000 0xfc068000 0x100 + 0xfc06a000 0xfc06a000 0x4000>; + /* WARNING: revisit as pin spec has changed */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ + 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ + 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ + 0xb003ff00 0x8002a800 0x00000000 /* pioD */ + 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ + >; + + pioA: gpio@fc06a000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06a000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + }; + + pioB: gpio@fc06b000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06b000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + }; + + pioC: gpio@fc06c000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06c000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; + }; + + pioD: gpio@fc068000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc068000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + }; + + pioE: gpio@fc06d000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06d000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; + }; + + /* pinctrl pin settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + ; /* conflicts with USBA_VBUS */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + ; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + ; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + ; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + ; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; /* conflicts with D15 and TDO */ + }; + }; + + ebi { + pinctrl_ebi_addr: ebi-addr-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nand_addr: ebi-addr-1 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs0: ebi-cs0-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs1: ebi-cs1-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs2: ebi-cs2-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs3: ebi-cs3-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_8_15: ebi-data-msb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nandrdy: ebi-nandrdy-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwait: ebi-nwait-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { + atmel,pins = + ; + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + atmel,pins = + ; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* TWCK1, conflicts with UART0 TX and DIBN */ + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + atmel,pins = + ; + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* TWCK2, conflicts with RF0 */ + }; + + pinctrl_i2c2_gpio: i2c2-gpio { + atmel,pins = + ; + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_HSYNC */ + }; + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ + }; + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ + }; + }; + + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb777: lcd-rgb-3 { + atmel,pins = + /* LCDDAT0 conflicts with TMS */ + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb888: lcd-rgb-4 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + ; + }; + }; + + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + atmel,pins = + ; + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + atmel,pins = + ; + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + atmel,pins = + ; + }; + }; + + mmc1 { + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + atmel,pins = + ; + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + atmel,pins = + ; + }; + }; + + nand0 { + pinctrl_nand: nand-0 { + atmel,pins = + ; /* PC12 periph A Data bit 7 */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + ; /* TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + ; /* RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + ; /* TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + ; /* RD1 */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; + }; + }; + + spi2 { + pinctrl_spi2: spi2-0 { + atmel,pins = + ; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = ; + }; + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = ; + }; + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; + }; + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ + }; + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; + }; + }; + + usart4 { + pinctrl_usart4: usart4-0 { + atmel,pins = + ; + }; + pinctrl_usart4_rts: usart4_rts-0 { + atmel,pins = ; /* conflicts with NWAIT, A19 */ + }; + pinctrl_usart4_cts: usart4_cts-0 { + atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ + }; + }; + }; + + aic: interrupt-controller@fc06e000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d4-aic"; + interrupt-controller; + reg = <0xfc06e000 0x200>; + atmel,external-irqs = <56>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/sama7g5-pinfunc.h b/arch/arm/boot/dts/microchip/sama7g5-pinfunc.h new file mode 100644 index 000000000000..a67a156e26ab --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama7g5-pinfunc.h @@ -0,0 +1,923 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#define PINMUX_PIN(no, func, ioset) \ +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) + +#define PIN_PA0 0 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) +#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) +#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) +#define PIN_PA1 1 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) +#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) +#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) +#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) +#define PIN_PA2 2 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) +#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) +#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) +#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) +#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) +#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) +#define PIN_PA3 3 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) +#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) +#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) +#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) +#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) +#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) +#define PIN_PA4 4 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) +#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) +#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) +#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) +#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) +#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) +#define PIN_PA5 5 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) +#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) +#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) +#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) +#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) +#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) +#define PIN_PA6 6 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) +#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) +#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) +#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) +#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) +#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) +#define PIN_PA7 7 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) +#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) +#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) +#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) +#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) +#define PIN_PA8 8 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) +#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) +#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) +#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) +#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) +#define PIN_PA9 9 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) +#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) +#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) +#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) +#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) +#define PIN_PA10 10 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) +#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) +#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) +#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) +#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) +#define PIN_PA11 11 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) +#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) +#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) +#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) +#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) +#define PIN_PA12 12 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) +#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) +#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) +#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) +#define PIN_PA13 13 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) +#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) +#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) +#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) +#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) +#define PIN_PA14 14 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) +#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) +#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) +#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) +#define PIN_PA15 15 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) +#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) +#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) +#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) +#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) +#define PIN_PA16 16 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) +#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) +#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) +#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) +#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) +#define PIN_PA17 17 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) +#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) +#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) +#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) +#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) +#define PIN_PA18 18 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) +#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) +#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) +#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) +#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) +#define PIN_PA19 19 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) +#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) +#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) +#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) +#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) +#define PIN_PA20 20 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) +#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) +#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) +#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) +#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) +#define PIN_PA21 21 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) +#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) +#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) +#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) +#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) +#define PIN_PA22 22 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) +#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) +#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) +#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) +#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) +#define PIN_PA23 23 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) +#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) +#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) +#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) +#define PIN_PA24 24 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) +#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) +#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) +#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) +#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) +#define PIN_PA25 25 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) +#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) +#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) +#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) +#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) +#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) +#define PIN_PA26 26 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) +#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) +#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) +#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) +#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) +#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) +#define PIN_PA27 27 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) +#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) +#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) +#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) +#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) +#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) +#define PIN_PA28 28 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) +#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) +#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) +#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) +#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) +#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) +#define PIN_PA29 29 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) +#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) +#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) +#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) +#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) +#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) +#define PIN_PA30 30 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) +#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) +#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) +#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) +#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) +#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) +#define PIN_PA31 31 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) +#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) +#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) +#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) +#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) +#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) +#define PIN_PB0 32 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) +#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) +#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) +#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) +#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) +#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) +#define PIN_PB1 33 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) +#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) +#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) +#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) +#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) +#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) +#define PIN_PB2 34 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) +#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) +#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) +#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) +#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3) +#define PIN_PB3 35 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) +#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) +#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) +#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) +#define PIN_PB4 36 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) +#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) +#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) +#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) +#define PIN_PB5 37 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) +#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) +#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) +#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) +#define PIN_PB6 38 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) +#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) +#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) +#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) +#define PIN_PB7 39 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) +#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) +#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) +#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) +#define PIN_PB8 40 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) +#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) +#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) +#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) +#define PIN_PB9 41 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) +#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) +#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) +#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) +#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) +#define PIN_PB10 42 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) +#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) +#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) +#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) +#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) +#define PIN_PB11 43 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) +#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) +#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) +#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) +#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) +#define PIN_PB12 44 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) +#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) +#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) +#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) +#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) +#define PIN_PB13 45 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) +#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) +#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) +#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) +#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) +#define PIN_PB14 46 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) +#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) +#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) +#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) +#define PIN_PB15 47 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) +#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) +#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) +#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) +#define PIN_PB16 48 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) +#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) +#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) +#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) +#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) +#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) +#define PIN_PB17 49 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) +#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) +#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) +#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) +#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) +#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) +#define PIN_PB18 50 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) +#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) +#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) +#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) +#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) +#define PIN_PB19 51 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) +#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) +#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) +#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) +#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) +#define PIN_PB20 52 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) +#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) +#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) +#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) +#define PIN_PB21 53 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) +#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) +#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) +#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) +#define PIN_PB22 54 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) +#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) +#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) +#define PIN_PB23 55 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) +#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) +#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) +#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) +#define PIN_PB24 56 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) +#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) +#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) +#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) +#define PIN_PB25 57 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) +#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) +#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) +#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) +#define PIN_PB26 58 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) +#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) +#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) +#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) +#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) +#define PIN_PB27 59 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) +#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) +#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) +#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) +#define PIN_PB28 60 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) +#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) +#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) +#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) +#define PIN_PB29 61 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) +#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) +#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) +#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) +#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) +#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) +#define PIN_PB30 62 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) +#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) +#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) +#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) +#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) +#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) +#define PIN_PB31 63 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) +#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) +#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) +#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) +#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) +#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) +#define PIN_PC0 64 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) +#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) +#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) +#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) +#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) +#define PIN_PC1 65 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) +#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) +#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) +#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) +#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) +#define PIN_PC2 66 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) +#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) +#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) +#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) +#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) +#define PIN_PC3 67 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) +#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) +#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) +#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) +#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) +#define PIN_PC4 68 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) +#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) +#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) +#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) +#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) +#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) +#define PIN_PC5 69 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) +#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) +#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) +#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) +#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) +#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) +#define PIN_PC6 70 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) +#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) +#define PIN_PC7 71 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) +#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) +#define PIN_PC8 72 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) +#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) +#define PIN_PC9 73 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) +#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) +#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) +#define PIN_PC10 74 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) +#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) +#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) +#define PIN_PC11 75 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) +#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) +#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) +#define PIN_PC12 76 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) +#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) +#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) +#define PIN_PC13 77 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) +#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) +#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) +#define PIN_PC14 78 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) +#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) +#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) +#define PIN_PC15 79 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) +#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) +#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) +#define PIN_PC16 80 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) +#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) +#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) +#define PIN_PC17 81 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) +#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) +#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) +#define PIN_PC18 82 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) +#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) +#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) +#define PIN_PC19 83 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) +#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) +#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) +#define PIN_PC20 84 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) +#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) +#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) +#define PIN_PC21 85 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) +#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) +#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) +#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) +#define PIN_PC22 86 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) +#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) +#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) +#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) +#define PIN_PC23 87 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) +#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) +#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) +#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) +#define PIN_PC24 88 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) +#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) +#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) +#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) +#define PIN_PC25 89 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) +#define PIN_PC26 90 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) +#define PIN_PC27 91 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) +#define PIN_PC28 92 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) +#define PIN_PC29 93 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) +#define PIN_PC30 94 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) +#define PIN_PC31 95 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) +#define PIN_PD0 96 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) +#define PIN_PD1 97 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) +#define PIN_PD2 98 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) +#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) +#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) +#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) +#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) +#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) +#define PIN_PD3 99 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) +#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) +#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) +#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) +#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) +#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) +#define PIN_PD4 100 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) +#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) +#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) +#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) +#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) +#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) +#define PIN_PD5 101 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) +#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) +#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) +#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) +#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) +#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) +#define PIN_PD6 102 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) +#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) +#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) +#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) +#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) +#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) +#define PIN_PD7 103 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) +#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) +#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) +#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) +#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) +#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) +#define PIN_PD8 104 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) +#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) +#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) +#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) +#define PIN_PD9 105 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) +#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) +#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) +#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) +#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) +#define PIN_PD10 106 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) +#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) +#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) +#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) +#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) +#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) +#define PIN_PD11 107 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) +#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) +#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) +#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) +#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) +#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) +#define PIN_PD12 108 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) +#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) +#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) +#define PIN_PD13 109 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) +#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) +#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) +#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) +#define PIN_PD14 110 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) +#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) +#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) +#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) +#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) +#define PIN_PD15 111 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) +#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) +#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) +#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) +#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) +#define PIN_PD16 112 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) +#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) +#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) +#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) +#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) +#define PIN_PD17 113 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) +#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) +#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) +#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) +#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) +#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) +#define PIN_PD18 114 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) +#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) +#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) +#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) +#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) +#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) +#define PIN_PD19 115 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) +#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) +#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) +#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) +#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) +#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) +#define PIN_PD20 116 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) +#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) +#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) +#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) +#define PIN_PD21 117 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) +#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) +#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) +#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) +#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) +#define PIN_PD22 118 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) +#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) +#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) +#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) +#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) +#define PIN_PD23 119 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) +#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) +#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) +#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) +#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) +#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) +#define PIN_PD24 120 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) +#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) +#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) +#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) +#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) +#define PIN_PD25 121 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) +#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) +#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) +#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) +#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) +#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) +#define PIN_PD26 122 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) +#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) +#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) +#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) +#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) +#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) +#define PIN_PD27 123 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) +#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) +#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) +#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) +#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) +#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) +#define PIN_PD28 124 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) +#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) +#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) +#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) +#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) +#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) +#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) +#define PIN_PD29 125 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) +#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) +#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) +#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) +#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) +#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) +#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) +#define PIN_PD30 126 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) +#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) +#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) +#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) +#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) +#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) +#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) +#define PIN_PD31 127 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) +#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) +#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) +#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) +#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) +#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) +#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) +#define PIN_PE0 128 +#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) +#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) +#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) +#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) +#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) +#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) +#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) +#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) +#define PIN_PE1 129 +#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) +#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) +#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) +#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) +#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) +#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) +#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) +#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) +#define PIN_PE2 130 +#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) +#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) +#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) +#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) +#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) +#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) +#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) +#define PIN_PE3 131 +#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) +#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) +#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) +#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) +#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) +#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) +#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) +#define PIN_PE4 132 +#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) +#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) +#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) +#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) +#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) +#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) +#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) +#define PIN_PE5 133 +#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) +#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) +#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) +#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) +#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) +#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) +#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) +#define PIN_PE6 134 +#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) +#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) +#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) +#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) +#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) +#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) +#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) +#define PIN_PE7 135 +#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) +#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) +#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) +#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) +#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) +#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi new file mode 100644 index 000000000000..b55adb96a06e --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -0,0 +1,1016 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC + * + * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries + * + * Author: Eugen Hristev + * Author: Claudiu Beznea + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Microchip SAMA7G5 family SoC"; + compatible = "microchip,sama7g5"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-90000000 { + opp-hz = /bits/ 64 <90000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + opp-suspend; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1150000 1125000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-1000000002 { + opp-hz = /bits/ 64 <1000000002>; + opp-microvolt = <1250000 1225000 1300000>; + clock-latency-ns = <320000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&thermal_sensor>; + + trips { + cpu_normal: cpu-alert0 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu_hot: cpu-alert1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu_critical: cpu-critical { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_normal>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + usb_clk: usb_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + }; + + vddout25: fixed-regulator-vddout25 { + compatible = "regulator-fixed"; + + regulator-name = "VDDOUT25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + status = "disabled"; + }; + + ns_sram: sram@100000 { + compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100000 0x20000>; + ranges; + }; + + thermal_sensor: thermal-sensor { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; + io-channel-names = "sensor-channel"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nfc_sram: sram@600000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x00600000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00600000 0x2400>; + }; + + nfc_io: nfc-io@10000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x10000000 0x8000000>; + }; + + ebi: ebi@40000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x40000000 0x20000000>; + ranges = <0x0 0x0 0x40000000 0x8000000 + 0x1 0x0 0x48000000 0x8000000 + 0x2 0x0 0x50000000 0x8000000 + 0x3 0x0 0x58000000 0x8000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + securam: sram@e0000000 { + compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000000 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000000 0x4000>; + no-memory-wc; + }; + + secumod: secumod@e0004000 { + compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + + sfrbu: sfr@e0008000 { + compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + + pioA: pinctrl@e0014000 { + compatible = "microchip,sama7g5-pinctrl"; + reg = <0xe0014000 0x800>; + interrupts = , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + }; + + pmc: clock-controller@e0018000 { + compatible = "microchip,sama7g5-pmc", "syscon"; + reg = <0xe0018000 0x200>; + interrupts = ; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + + shdwc: shdwc@e001d010 { + compatible = "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d010 0x10>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@e001d020 { + compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d020 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + + clk32k: clock-controller@e001d050 { + compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; + reg = <0xe001d050 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + gpbr: gpbr@e001d060 { + compatible = "microchip,sama7g5-gpbr", "syscon"; + reg = <0xe001d060 0x48>; + }; + + rtc: rtc@e001d0a8 { + compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d0a8 0x30>; + interrupts = ; + clocks = <&clk32k 1>; + }; + + ps_wdt: watchdog@e001d180 { + compatible = "microchip,sama7g5-wdt"; + reg = <0xe001d180 0x24>; + interrupts = ; + clocks = <&clk32k 0>; + }; + + chipid@e0020000 { + compatible = "microchip,sama7g5-chipid"; + reg = <0xe0020000 0x8>; + }; + + tcb1: timer@e0800000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0800000 0x100>; + interrupts = , , ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + hsmc: hsmc@e0808000 { + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; + reg = <0xe0808000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@e0808070 { + compatible = "atmel,sama5d2-pmecc"; + reg = <0xe0808070 0x490>, + <0xe0808500 0x200>; + }; + }; + + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x100>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x100>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x100>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 63>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x100>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 64>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x100>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 65>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can5: can@e083c000 { + compatible = "bosch,m_can"; + reg = <0xe083c000 0x100>, <0x110000 0xcc00>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 66>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + adc: adc@e1000000 { + compatible = "microchip,sama7g5-adc"; + reg = <0xe1000000 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + clock-names = "adc_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; + dma-names = "rx"; + atmel,min-sample-rate-hz = <200000>; + atmel,max-sample-rate-hz = <20000000>; + atmel,startup-time-ms = <4>; + #io-channel-cells = <1>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; + status = "disabled"; + }; + + sdmmc0: mmc@e1204000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1204000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; + clock-names = "hclock", "multclk"; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clocks = <&pmc PMC_TYPE_GCK 80>; + assigned-clock-rates = <200000000>; + microchip,sdcal-inverted; + status = "disabled"; + }; + + sdmmc1: mmc@e1208000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1208000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; + clock-names = "hclock", "multclk"; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clocks = <&pmc PMC_TYPE_GCK 81>; + assigned-clock-rates = <200000000>; + microchip,sdcal-inverted; + status = "disabled"; + }; + + sdmmc2: mmc@e120c000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe120c000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; + clock-names = "hclock", "multclk"; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clocks = <&pmc PMC_TYPE_GCK 82>; + assigned-clock-rates = <200000000>; + microchip,sdcal-inverted; + status = "disabled"; + }; + + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + status = "disabled"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + + pwm: pwm@e1604000 { + compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; + reg = <0xe1604000 0x4000>; + interrupts = ; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; + status = "disabled"; + }; + + pdmc0: sound@e1608000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe1608000 0x1000>; + interrupts = ; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + pdmc1: sound@e160c000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe160c000 0x1000>; + interrupts = ; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + spdifrx: spdifrx@e1614000 { + #sound-dai-cells = <0>; + compatible = "microchip,sama7g5-spdifrx"; + reg = <0xe1614000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + spdiftx: spdiftx@e1618000 { + #sound-dai-cells = <0>; + compatible = "microchip,sama7g5-spdiftx"; + reg = <0xe1618000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; + clock-names = "pclk", "gclk"; + }; + + i2s0: i2s@e161c000 { + compatible = "microchip,sama7g5-i2smcc"; + #sound-dai-cells = <0>; + reg = <0xe161c000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + i2s1: i2s@e1620000 { + compatible = "microchip,sama7g5-i2smcc"; + #sound-dai-cells = <0>; + reg = <0xe1620000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0xec>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + status = "disabled"; + }; + + pit64b0: timer@e1800000 { + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1800000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; + clock-names = "pclk", "gclk"; + }; + + pit64b1: timer@e1804000 { + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1804000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; + clock-names = "pclk", "gclk"; + }; + + aes: crypto@e1810000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe1810000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1814000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe1814000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + + flx0: flexcom@e1818000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe1818000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe1818000 0x800>; + status = "disabled"; + + uart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + }; + + flx1: flexcom@e181c000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe181c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe181c000 0x800>; + status = "disabled"; + + i2c1: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx3: flexcom@e1824000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe1824000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe1824000 0x800>; + status = "disabled"; + + uart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, + <&dma1 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + }; + + trng: rng@e2010000 { + compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; + reg = <0xe2010000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; + status = "disabled"; + }; + + tdes: crypto@e2014000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xe2014000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + + flx4: flexcom@e2018000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2018000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2018000 0x800>; + status = "disabled"; + + uart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx7: flexcom@e2024000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2024000 0x800>; + status = "disabled"; + + uart7: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gmac0: ethernet@e2800000 { + compatible = "microchip,sama7g5-gem"; + reg = <0xe2800000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 51>; + assigned-clock-rates = <125000000>; + status = "disabled"; + }; + + gmac1: ethernet@e2804000 { + compatible = "microchip,sama7g5-emac"; + reg = <0xe2804000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + dma0: dma-controller@e2808000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe2808000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + dma1: dma-controller@e280c000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe280c000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + /* Place dma2 here despite it's address */ + dma2: dma-controller@e1200000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe1200000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "dma_clk"; + dma-requests = <0>; + status = "disabled"; + }; + + tcb0: timer@e2814000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2814000 0x100>; + interrupts = , , ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + flx8: flexcom@e2818000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2818000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2818000 0x800>; + status = "disabled"; + + i2c8: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx9: flexcom@e281c000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe281c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe281c000 0x800>; + status = "disabled"; + + i2c9: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx11: flexcom@e2824000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2824000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2824000 0x800>; + status = "disabled"; + + spi11: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, + <&dma0 AT91_XDMAC_DT_PERID(27)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + + otpc: efuse@e8c00000 { + compatible = "microchip,sama7g5-otpc", "syscon"; + reg = <0xe8c00000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + temperature_calib: calib@1 { + reg = ; + }; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/tny_a9260.dts b/arch/arm/boot/dts/microchip/tny_a9260.dts new file mode 100644 index 000000000000..ef6d586ce887 --- /dev/null +++ b/arch/arm/boot/dts/microchip/tny_a9260.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9260.dtsi" +#include "tny_a9260_common.dtsi" + +/ { + model = "Calao TNY A9260"; + compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9"; +}; diff --git a/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi new file mode 100644 index 000000000000..70e5635c78ed --- /dev/null +++ b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +/ { + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/tny_a9263.dts b/arch/arm/boot/dts/microchip/tny_a9263.dts new file mode 100644 index 000000000000..62b7d9f9a926 --- /dev/null +++ b/arch/arm/boot/dts/microchip/tny_a9263.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9263.dtsi" + +/ { + model = "Calao TNY A9263"; + compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + usb1: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + ebi0: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/tny_a9g20.dts b/arch/arm/boot/dts/microchip/tny_a9g20.dts new file mode 100644 index 000000000000..118d766a1265 --- /dev/null +++ b/arch/arm/boot/dts/microchip/tny_a9g20.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9g20.dtsi" +#include "tny_a9260_common.dtsi" + +/ { + model = "Calao TNY A9G20"; + compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts new file mode 100644 index 000000000000..6cfa83921ac2 --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * usb_a9260.dts - Device Tree file for Caloa USB A9260 board + * + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9260.dtsi" +#include "usb_a9260_common.dtsi" + +/ { + model = "Calao USB A9260"; + compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + ahb { + apb { + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi new file mode 100644 index 000000000000..8744b5f6f792 --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * usb_a926x.dts - Device Tree file for Caloa USB A926x board + * + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD + */ + +/ { + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + tcb0: timer@fffa0000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + ebi: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; + linux,code = <28>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts new file mode 100644 index 000000000000..b6cb9cdf8197 --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9263.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "at91sam9263.dtsi" + +/ { + model = "Calao USB A9263"; + compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + tcb0: timer@fff7c000 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffa4000 { + cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <0>; + spi-max-frequency = <15000000>; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + + ebi0: ebi@10000000 { + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + }; + }; + + usb0: ohci@a00000 { + num-ports = <2>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; + linux,code = <28>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi new file mode 100644 index 000000000000..08d58081201a --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + */ + +/ { + ahb { + apb { + usart1: serial@fffb4000 { + status = "okay"; + }; + + usart3: serial@fffd0000 { + status = "okay"; + }; + }; + }; + + i2c-gpio@0 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "user_led1"; + gpios = <&pioB 20 GPIO_ACTIVE_LOW>; + }; + +/* +* led already used by mother board but active as high +* user_led2 { +* label = "user_led2"; +* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; +* }; +*/ + user_led3 { + label = "user_led3"; + gpios = <&pioB 22 GPIO_ACTIVE_LOW>; + }; + + user_led4 { + label = "user_led4"; + gpios = <&pioB 23 GPIO_ACTIVE_LOW>; + }; + + red { + label = "red"; + gpios = <&pioB 24 GPIO_ACTIVE_LOW>; + }; + + orange { + label = "orange"; + gpios = <&pioB 30 GPIO_ACTIVE_LOW>; + }; + + green { + label = "green"; + gpios = <&pioB 31 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb1 { + label = "user_pb1"; + gpios = <&pioB 25 GPIO_ACTIVE_LOW>; + linux,code = <0x100>; + }; + + user_pb2 { + label = "user_pb2"; + gpios = <&pioB 13 GPIO_ACTIVE_LOW>; + linux,code = <0x101>; + }; + + user_pb3 { + label = "user_pb3"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + linux,code = <0x102>; + }; + + user_pb4 { + label = "user_pb4"; + gpios = <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts new file mode 100644 index 000000000000..2f667b083e81 --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9g20.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "usb_a9g20_common.dtsi" + +/ { + model = "Calao USB A9G20"; + compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi new file mode 100644 index 000000000000..7d10b36db1ee --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + */ + +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" + +/ { + chosen { + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + + i2c-gpio-0 { + rtc@56 { + compatible = "microcrystal,rv3029"; + reg = <0x56>; + }; + }; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts new file mode 100644 index 000000000000..f65712015d40 --- /dev/null +++ b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board + * + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD + */ +/dts-v1/; +#include "usb_a9g20_common.dtsi" + +/ { + model = "Calao USB A9G20 Low Power"; + compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; + + ahb { + apb { + spi1: spi@fffcc000 { + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + mmc-slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3200 3400>; + spi-max-frequency = <25000000>; + interrupt-parent = <&pioC>; + interrupts = <4 IRQ_TYPE_EDGE_BOTH>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts deleted file mode 100644 index 614f60c6b0a2..000000000000 --- a/arch/arm/boot/dts/milbeaut-m10v-evb.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Socionext Milbeaut M10V Evaluation Board */ -/dts-v1/; -#include "milbeaut-m10v.dtsi" - -/ { - model = "Socionext M10V EVB"; - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; - - aliases { - serial0 = &uart1; - }; - - chosen { - bootargs = "rootwait earlycon"; - stdout-path = "serial0:115200n8"; - }; - - clocks { - uclk40xi: uclk40xi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - -}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi deleted file mode 100644 index 75f0c0af2270..000000000000 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include - -/ { - compatible = "socionext,sc2000a"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,milbeaut-m10v-smp"; - cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - }; - cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - }; - cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - }; - }; - - timer { /* The Generic Timer */ - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <40000000>; - always-on; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&gic>; - - gic: interrupt-controller@1d000000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1d001000 0x1000>, - <0x1d002000 0x1000>; /* CPU I/f base and size */ - }; - - clk: clock-ctrl@1d021000 { - compatible = "socionext,milbeaut-m10v-ccu"; - #clock-cells = <1>; - reg = <0x1d021000 0x1000>; - clocks = <&uclk40xi>; - }; - - timer@1e000050 { /* 32-bit Reload Timers */ - compatible = "socionext,milbeaut-timer"; - reg = <0x1e000050 0x20>; - interrupts = <0 91 4>; - clocks = <&clk 4>; - }; - - uart1: serial@1e700010 { /* PE4, PE5 */ - /* Enable this as ttyUSI0 */ - compatible = "socionext,milbeaut-usio-uart"; - reg = <0x1e700010 0x10>; - interrupts = <0 141 0x4>, <0 149 0x4>; - interrupt-names = "rx", "tx"; - clocks = <&clk 2>; - }; - - }; - - sram@0 { - compatible = "mmio-sram"; - reg = <0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x10000>; - smp-sram@f100 { - compatible = "socionext,milbeaut-smp-sram"; - reg = <0xf100 0x20>; - }; - }; -}; diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts deleted file mode 100644 index 04f1ae1382e7..000000000000 --- a/arch/arm/boot/dts/mmp2-brownstone.dts +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; -#include "mmp2.dtsi" - -/ { - model = "Marvell MMP2 Brownstone Development Board"; - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; - - chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&uart3 { - status = "okay"; -}; - -&twsi1 { - status = "okay"; - pmic: max8925@3c { - compatible = "maxium,max8925"; - reg = <0x3c>; - interrupts = <1>; - interrupt-parent = <&intcmux4>; - interrupt-controller; - #interrupt-cells = <1>; - maxim,tsc-irq = <0>; - - regulators { - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - SDV2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2225000>; - regulator-boot-on; - regulator-always-on; - }; - SDV3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - }; - LDO11 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO15 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO16 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO17 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO18 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO19 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO20 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - backlight { - maxim,max8925-dual-string = <0>; - }; - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; - }; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts deleted file mode 100644 index 55ea87870af3..000000000000 --- a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * OLPC XO 1.75 Laptop. - * - * Copyright (C) 2018,2019,2020 Lubomir Rintel - */ - -/dts-v1/; -#include "mmp2.dtsi" -#include -#include -#include -#include - -/ { - model = "OLPC XO-1.75"; - compatible = "olpc,xo-1.75", "mrvl,mmp2"; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@1fc00000 { - compatible = "simple-framebuffer"; - reg = <0x1fc00000 (1200 * 900 * 2)>; - width = <1200>; - height = <900>; - stride = <(1200 * 2)>; - format = "r5g6b5"; - clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>, - <&soc_clocks MMP2_CLK_DISP0>; - }; - }; - - memory@0 { - available = <0xcf000 0x1ef31000 0x1000 0xbf000>; - reg = <0x0 0x20000000>; - device_type = "memory"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio 129 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - tablet_mode { - label = "E-Book Mode"; - gpios = <&gpio 128 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - i2c-gpio,timeout-ms = <1000>; - status = "okay"; - - camera@21 { - compatible = "ovti,ov7670"; - reg = <0x21>; - reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>; - clocks = <&camera0>; - clock-names = "xclk"; - - port { - ov7670_0: endpoint { - hsync-active = <1>; - vsync-active = <1>; - remote-endpoint = <&camera0_0>; - }; - }; - }; - }; - - battery { - compatible = "olpc,xo1.5-battery", "olpc,xo1-battery"; - }; - - wlan_reg: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "wlan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 34 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wlan_pwrseq: pwrseq0 { - compatible = "mmc-pwrseq-sd8787"; - powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; - }; - - sound-card { - compatible = "audio-graph-card"; - label = "OLPC XO"; - dais = <&sspa0_dai>; - routing = "Headphones", "HPOL", - "Headphones", "HPOR", - "MIC2", "Mic Jack"; - widgets = "Headphone", "Headphones", "Microphone", "Mic Jack"; - hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>; - mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>; - }; - - soc { - axi@d4200000 { - ap-sp@d4290000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "olpc,ap-sp"; - interrupts = <40>; - reg = <0xd4290000 0x1000>; - data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - }; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_otg0 { - status = "okay"; -}; - -&mmc1 { - clock-frequency = <50000000>; - no-1-8-v; - mrvl,clk-delay-cycles = <31>; - broken-cd; - status = "okay"; -}; - -&mmc2 { - clock-frequency = <50000000>; - no-1-8-v; - bus-width = <4>; - non-removable; - broken-cd; - wakeup-source; - keep-power-in-suspend; - mmc-pwrseq = <&wlan_pwrseq>; - vmmc-supply = <&wlan_reg>; - status = "okay"; -}; - -&mmc3 { - clock-frequency = <50000000>; - no-1-8-v; - bus-width = <8>; - non-removable; - broken-cd; - mrvl,clk-delay-cycles = <31>; - status = "okay"; -}; - -&twsi1 { - status = "okay"; - - audio-codec@1a { - compatible = "realtek,alc5631"; - reg = <0x1a>; - status = "okay"; - - port { - rt5631_0: endpoint { - mclk-fs = <256>; - clocks = <&audio_clk MMP2_CLK_AUDIO_SYSCLK>; - remote-endpoint = <&sspa0_0>; - }; - }; - }; -}; - -&twsi2 { - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - status = "okay"; - }; -}; - -&twsi6 { - status = "okay"; - - accelerometer@1d { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x1d>; - status = "okay"; - }; -}; - -&ssp3 { - #address-cells = <0>; - spi-slave; - status = "okay"; - ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>; - - slave { - compatible = "olpc,xo1.75-ec"; - spi-cpha; - cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>; - }; -}; - -&camera0 { - status = "okay"; - - port { - camera0_0: endpoint { - remote-endpoint = <&ov7670_0>; - }; - }; -}; - -&asram { - status = "okay"; -}; - -&adma0 { - status = "okay"; -}; - -&audio_clk { - status = "okay"; -}; - -&sspa0 { - status = "okay"; - dmas = <&adma0 0>, <&adma0 1>; - dma-names = "tx", "rx"; - - sspa0_dai: port { - sspa0_0: endpoint { - remote-endpoint = <&rt5631_0>; - frame-master; - bitclock-master; - dai-format = "i2s"; - }; - }; -}; - -&gpu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi deleted file mode 100644 index 987d792f67ea..000000000000 --- a/arch/arm/boot/dts/mmp2.dtsi +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - gpu: gpu@d420d000 { - compatible = "vivante,gc"; - reg = <0xd420d000 0x4000>; - interrupts = <8>; - status = "disabled"; - clocks = <&soc_clocks MMP2_CLK_GPU_3D>, - <&soc_clocks MMP2_CLK_GPU_BUS>; - clock-names = "core", "bus"; - power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; - }; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - intcmux4: interrupt-controller@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <4>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux5: interrupt-controller@d4282154 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <5>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x154 0x4>, <0x16c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - mrvl,clr-mfp-irq = <1>; - }; - - intcmux9: interrupt-controller@d4282180 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x180 0x4>, <0x17c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - intcmux17: interrupt-controller@d4282158 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <17>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x158 0x4>, <0x170 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - intcmux35: interrupt-controller@d428215c { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <35>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x15c 0x4>, <0x174 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <15>; - }; - - intcmux51: interrupt-controller@d4282160 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <51>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x160 0x4>, <0x178 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux55: interrupt-controller@d4282188 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <55>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x188 0x4>, <0x184 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - usb_phy0: usb-phy@d4207000 { - compatible = "marvell,mmp2-usb-phy"; - reg = <0xd4207000 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_otg0: usb-otg@d4208000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xd4208000 0x200>; - interrupts = <44>; - clocks = <&soc_clocks MMP2_CLK_USB>; - clock-names = "USBCLK"; - phys = <&usb_phy0>; - phy-names = "usb"; - status = "disabled"; - }; - - mmc1: mmc@d4280000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH0>; - clock-names = "io"; - interrupts = <39>; - status = "disabled"; - }; - - mmc2: mmc@d4280800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH1>; - clock-names = "io"; - interrupts = <52>; - status = "disabled"; - }; - - mmc3: mmc@d4281000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH2>; - clock-names = "io"; - interrupts = <53>; - status = "disabled"; - }; - - mmc4: mmc@d4281800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH3>; - clock-names = "io"; - interrupts = <54>; - status = "disabled"; - }; - - camera0: camera@d420a000 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a000 0x800>; - interrupts = <42>; - clocks = <&soc_clocks MMP2_CLK_CCIC0>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - - camera1: camera@d420a800 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a800 0x800>; - interrupts = <30>; - clocks = <&soc_clocks MMP2_CLK_CCIC1>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - - adma0: dma-controller@d42a0800 { - compatible = "marvell,adma-1.0"; - reg = <0xd42a0800 0x100>; - interrupts = <48>; - #dma-cells = <1>; - asram = <&asram>; - iram = <&asram>; - status = "disabled"; - }; - - adma1: dma-controller@d42a0900 { - compatible = "marvell,adma-1.0"; - reg = <0xd42a0900 0x100>; - interrupts = <48>; - #dma-cells = <1>; - status = "disabled"; - }; - - audio_clk: clocks@d42a0c30 { - compatible = "marvell,mmp2-audio-clock"; - reg = <0xd42a0c30 0x10>; - clock-names = "audio", "vctcxo", "i2s0", "i2s1"; - clocks = <&soc_clocks MMP2_CLK_AUDIO>, - <&soc_clocks MMP2_CLK_VCTCXO>, - <&soc_clocks MMP2_CLK_I2S0>, - <&soc_clocks MMP2_CLK_I2S1>; - power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; - #clock-cells = <1>; - status = "disabled"; - }; - - sspa0: audio-controller@d42a0c00 { - compatible = "marvell,mmp-sspa"; - reg = <0xd42a0c00 0x30>, - <0xd42a0c80 0x30>; - interrupts = <2>; - clock-names = "audio", "bitclk"; - clocks = <&soc_clocks MMP2_CLK_AUDIO>, - <&audio_clk MMP2_CLK_AUDIO_SSPA0>; - power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - sspa1: audio-controller@d42a0d00 { - compatible = "marvell,mmp-sspa"; - reg = <0xd42a0d00 0x30>, - <0xd42a0d80 0x30>; - interrupts = <3>; - clock-names = "audio", "bitclk"; - clocks = <&soc_clocks MMP2_CLK_AUDIO>, - <&audio_clk MMP2_CLK_AUDIO_SSPA1>; - power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <48>; - /* For backwards compatibility: */ - #dma-channels = <16>; - dma-channels = <16>; - status = "disabled"; - }; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - clocks = <&soc_clocks MMP2_CLK_TIMER>; - }; - - uart1: serial@d4030000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4030000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks MMP2_CLK_UART0>; - resets = <&soc_clocks MMP2_CLK_UART0>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@d4017000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks MMP2_CLK_UART1>; - resets = <&soc_clocks MMP2_CLK_UART1>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@d4018000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <24>; - clocks = <&soc_clocks MMP2_CLK_UART2>; - resets = <&soc_clocks MMP2_CLK_UART2>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@d4016000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4016000 0x1000>; - interrupts = <46>; - clocks = <&soc_clocks MMP2_CLK_UART3>; - resets = <&soc_clocks MMP2_CLK_UART3>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio: gpio@d4019000 { - compatible = "marvell,mmp2-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks MMP2_CLK_GPIO>; - resets = <&soc_clocks MMP2_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - - gcb4: gpio@d4019104 { - reg = <0xd4019104 0x4>; - }; - - gcb5: gpio@d4019108 { - reg = <0xd4019108 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks MMP2_CLK_TWSI0>; - resets = <&soc_clocks MMP2_CLK_TWSI0>; - #address-cells = <1>; - #size-cells = <0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4031000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4031000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <0>; - clocks = <&soc_clocks MMP2_CLK_TWSI1>; - resets = <&soc_clocks MMP2_CLK_TWSI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi3: i2c@d4032000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4032000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <1>; - clocks = <&soc_clocks MMP2_CLK_TWSI2>; - resets = <&soc_clocks MMP2_CLK_TWSI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi4: i2c@d4033000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <2>; - clocks = <&soc_clocks MMP2_CLK_TWSI3>; - resets = <&soc_clocks MMP2_CLK_TWSI3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - - twsi5: i2c@d4033800 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033800 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <3>; - clocks = <&soc_clocks MMP2_CLK_TWSI4>; - resets = <&soc_clocks MMP2_CLK_TWSI4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi6: i2c@d4034000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4034000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <4>; - clocks = <&soc_clocks MMP2_CLK_TWSI5>; - resets = <&soc_clocks MMP2_CLK_TWSI5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <1>, <0>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - interrupt-parent = <&intcmux5>; - clocks = <&soc_clocks MMP2_CLK_RTC>; - resets = <&soc_clocks MMP2_CLK_RTC>; - status = "disabled"; - }; - - ssp1: spi@d4035000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4035000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP0>; - interrupts = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp2: spi@d4036000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4036000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP1>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp3: spi@d4037000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4037000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP2>; - interrupts = <20>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp4: spi@d4039000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4039000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP3>; - interrupts = <21>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - asram: sram@e0000000 { - compatible = "mmio-sram"; - reg = <0xe0000000 0x10000>; - ranges = <0 0xe0000000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - soc_clocks: clocks { - compatible = "marvell,mmp2-clock"; - reg = <0xd4050000 0x2000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/mmp3-dell-ariel.dts deleted file mode 100644 index fe6df364a9eb..000000000000 --- a/arch/arm/boot/dts/mmp3-dell-ariel.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D) - * - * Copyright (C) 2019 Lubomir Rintel - */ - -/dts-v1/; -#include "mmp3.dtsi" -#include -#include - -/ { - model = "Dell Ariel"; - compatible = "dell,wyse-ariel", "marvell,mmp3"; - - aliases { - serial2 = &uart3; - }; - - chosen { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200"; - }; - - memory@0 { - available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>; - reg = <0x0 0x80000000>; - device_type = "memory"; - }; - - ec_input_spi: spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - num-chipselects = <0>; - sck-gpios = <&gpio 55 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&usb_otg0 { - status = "okay"; -}; - -&usb_otg_phy0 { - status = "okay"; -}; - -&hsic0 { - status = "okay"; - - usb1@1 { - compatible = "usb424,2640"; - reg = <0x01>; - #address-cells = <0x01>; - #size-cells = <0x00>; - - mass-storage@1 { - compatible = "usb424,4040"; - reg = <0x01>; - status = "disabled"; - }; - }; -}; - -&hsic_phy0 { - status = "okay"; - reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; -}; - -&mmc3 { - status = "okay"; - max-frequency = <50000000>; - status = "okay"; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; -}; - -&twsi1 { - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - status = "okay"; - }; -}; - -&twsi3 { - status = "okay"; -}; - -&twsi4 { - status = "okay"; - - embedded-controller@58 { - compatible = "dell,wyse-ariel-ec", "ene,kb3930"; - reg = <0x58>; - system-power-controller; - - off-gpios = <&gpio 126 GPIO_ACTIVE_HIGH>, - <&gpio 127 GPIO_ACTIVE_HIGH>; - }; -}; - -&ssp1 { - status = "okay"; - cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - - firmware-flash@0 { - compatible = "winbond,w25q32", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - m25p,fast-read; - }; -}; - -&ec_input_spi { - status = "okay"; - cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>; - - power-button@0 { - reg = <0>; - interrupt-parent = <&gpio>; - interrupts = <60 IRQ_TYPE_EDGE_RISING>; - compatible = "dell,wyse-ariel-ec-input", "ene,kb3930-input"; - spi-max-frequency = <33000000>; - }; -}; - -&gpu_2d { - status = "okay"; -}; - -&gpu_3d { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi deleted file mode 100644 index a4fb9203ec1f..000000000000 --- a/arch/arm/boot/dts/mmp3.dtsi +++ /dev/null @@ -1,608 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2019 Lubomir Rintel - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,mmp3-smp"; - - cpu@0 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - }; - - cpu@1 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - axi@d4200000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - interrupt-controller@d4282000 { - compatible = "marvell,mmp3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>, - <0xd4284000 0x100>; - mrvl,intc-nr-irqs = <64>; - }; - - pmic_mux: interrupt-controller@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <4>; - }; - - rtc_mux: interrupt-controller@d4282154 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x154 0x4>, <0x16c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - hsi3_mux: interrupt-controller@d42821bc { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1bc 0x4>, <0x1a4 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - gpu_mux: interrupt-controller@d42821c0 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1c0 0x4>, <0x1a8 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - twsi_mux: interrupt-controller@d4282158 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x158 0x4>, <0x170 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - hsi2_mux: interrupt-controller@d42821c4 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1c4 0x4>, <0x1ac 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - dxo_mux: interrupt-controller@d42821c8 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1c8 0x4>, <0x1b0 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - misc1_mux: interrupt-controller@d428215c { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x15c 0x4>, <0x174 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <31>; - }; - - ci_mux: interrupt-controller@d42821cc { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1cc 0x4>, <0x1b4 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - ssp_mux: interrupt-controller@d4282160 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x160 0x4>, <0x178 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - hsi1_mux: interrupt-controller@d4282184 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x184 0x4>, <0x17c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <4>; - }; - - misc2_mux: interrupt-controller@d4282188 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x188 0x4>, <0x180 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <20>; - }; - - hsi0_mux: interrupt-controller@d42821d0 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1d0 0x4>, <0x1b8 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - usb_otg_phy0: usb-phy@d4207000 { - compatible = "marvell,mmp3-usb-phy"; - reg = <0xd4207000 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_otg0: usb@d4208000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xd4208000 0x200>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_USB>; - clock-names = "USBCLK"; - phys = <&usb_otg_phy0>; - phy-names = "usb"; - status = "disabled"; - }; - - hsic_phy0: usb-phy@f0001800 { - compatible = "marvell,mmp3-hsic-phy"; - reg = <0xf0001800 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - hsic0: usb@f0001000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xf0001000 0x200>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_USBHSIC0>; - clock-names = "USBCLK"; - phys = <&hsic_phy0>; - phy-names = "usb"; - phy_type = "hsic"; - #address-cells = <0x01>; - #size-cells = <0x00>; - status = "disabled"; - }; - - hsic_phy1: usb-phy@f0002800 { - compatible = "marvell,mmp3-hsic-phy"; - reg = <0xf0002800 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - hsic1: usb@f0002000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xf0002000 0x200>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_USBHSIC1>; - clock-names = "USBCLK"; - phys = <&hsic_phy1>; - phy-names = "usb"; - phy_type = "hsic"; - #address-cells = <0x01>; - #size-cells = <0x00>; - status = "disabled"; - }; - - mmc1: mmc@d4280000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH0>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc2: mmc@d4280800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH1>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc3: mmc@d4281000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH2>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc4: mmc@d4281800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH3>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc5: mmc@d4217000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4217000 0x120>; - clocks = <&soc_clocks MMP3_CLK_SDH4>; - clock-names = "io"; - interrupt-parent = <&hsi1_mux>; - interrupts = <0>; - status = "disabled"; - }; - - camera0: camera@d420a000 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a000 0x800>; - interrupts = <1>; - interrupt-parent = <&ci_mux>; - clocks = <&soc_clocks MMP2_CLK_CCIC0>; - clock-names = "axi"; - power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - - camera1: camera@d420a800 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a800 0x800>; - interrupts = <2>; - interrupt-parent = <&ci_mux>; - clocks = <&soc_clocks MMP2_CLK_CCIC1>; - clock-names = "axi"; - power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - - gpu_3d: gpu@d420d000 { - compatible = "vivante,gc"; - reg = <0xd420d000 0x2000>; - interrupt-parent = <&gpu_mux>; - interrupts = <0>; - status = "disabled"; - clocks = <&soc_clocks MMP3_CLK_GPU_3D>, - <&soc_clocks MMP3_CLK_GPU_BUS>; - clock-names = "core", "bus"; - power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; - }; - - gpu_2d: gpu@d420f000 { - compatible = "vivante,gc"; - reg = <0xd420f000 0x2000>; - interrupt-parent = <&gpu_mux>; - interrupts = <2>; - status = "disabled"; - clocks = <&soc_clocks MMP3_CLK_GPU_2D>, - <&soc_clocks MMP3_CLK_GPU_BUS>; - clock-names = "core", "bus"; - power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; - }; - }; - - apb@d4000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_TIMER>; - }; - - uart1: serial@d4030000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4030000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART0>; - resets = <&soc_clocks MMP2_CLK_UART0>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@d4017000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4017000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART1>; - resets = <&soc_clocks MMP2_CLK_UART1>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@d4018000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4018000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART2>; - resets = <&soc_clocks MMP2_CLK_UART2>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@d4016000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4016000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART3>; - resets = <&soc_clocks MMP2_CLK_UART3>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio: gpio@d4019000 { - compatible = "marvell,mmp2-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks MMP2_CLK_GPIO>; - resets = <&soc_clocks MMP2_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - - gcb4: gpio@d4019104 { - reg = <0xd4019104 0x4>; - }; - - gcb5: gpio@d4019108 { - reg = <0xd4019108 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x70>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_TWSI0>; - resets = <&soc_clocks MMP2_CLK_TWSI0>; - #address-cells = <1>; - #size-cells = <0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4031000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4031000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <0>; - clocks = <&soc_clocks MMP2_CLK_TWSI1>; - resets = <&soc_clocks MMP2_CLK_TWSI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi3: i2c@d4032000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4032000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <1>; - clocks = <&soc_clocks MMP2_CLK_TWSI2>; - resets = <&soc_clocks MMP2_CLK_TWSI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi4: i2c@d4033000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <2>; - clocks = <&soc_clocks MMP2_CLK_TWSI3>; - resets = <&soc_clocks MMP2_CLK_TWSI3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - - twsi5: i2c@d4033800 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033800 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <3>; - clocks = <&soc_clocks MMP2_CLK_TWSI4>; - resets = <&soc_clocks MMP2_CLK_TWSI4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi6: i2c@d4034000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4034000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <4>; - clocks = <&soc_clocks MMP2_CLK_TWSI5>; - resets = <&soc_clocks MMP2_CLK_TWSI5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <1>, <0>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - interrupt-parent = <&rtc_mux>; - clocks = <&soc_clocks MMP2_CLK_RTC>; - resets = <&soc_clocks MMP2_CLK_RTC>; - status = "disabled"; - }; - - ssp1: spi@d4035000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4035000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp2: spi@d4036000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4036000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp3: spi@d4037000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4037000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp4: spi@d4039000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4039000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - l2: cache-controller@d0020000 { - compatible = "marvell,tauros3-cache", "arm,pl310-cache"; - reg = <0xd0020000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - soc_clocks: clocks@d4050000 { - compatible = "marvell,mmp3-clock"; - reg = <0xd4050000 0x2000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - snoop-control-unit@e0000000 { - compatible = "arm,arm11mp-scu"; - reg = <0xe0000000 0x100>; - }; - - gic: interrupt-controller@e0001000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xe0001000 0x1000>, - <0xe0000100 0x100>; - }; - - local-timer@e0000600 { - compatible = "arm,arm11mp-twd-timer"; - interrupts = ; - reg = <0xe0000600 0x20>; - }; - - watchdog@e0000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0xe0000620 0x20>; - interrupts = ; - }; - }; -}; diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi deleted file mode 100644 index ea02fd403a9b..000000000000 --- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common CPCAP configuration used on Motorola phones - */ - -&mcspi1 { - cpcap: pmic@0 { - compatible = "motorola,cpcap", "st,6556002"; - reg = <0>; /* cs0 */ - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <9600000>; - spi-cs-high; - spi-cpol; - spi-cpha; - - cpcap_adc: adc { - compatible = "motorola,mapphone-cpcap-adc"; - interrupts-extended = <&cpcap 8 0>; - interrupt-names = "adcdone"; - #io-channel-cells = <1>; - }; - - cpcap_battery: battery { - compatible = "motorola,cpcap-battery"; - interrupts-extended = - <&cpcap 6 0>, <&cpcap 5 0>, <&cpcap 3 0>, - <&cpcap 20 0>, <&cpcap 54 0>, <&cpcap 57 0>; - interrupt-names = - "eol", "lowbph", "lowbpl", - "chrgcurr1", "battdetb", "cccal"; - io-channels = <&cpcap_adc 0>, <&cpcap_adc 1>, - <&cpcap_adc 5>, <&cpcap_adc 6>; - io-channel-names = "battdetb", "battp", - "chg_isense", "batti"; - power-supplies = <&cpcap_charger>; - }; - - cpcap_charger: charger { - compatible = "motorola,mapphone-cpcap-charger"; - interrupts-extended = - <&cpcap 13 0>, <&cpcap 12 0>, <&cpcap 29 0>, - <&cpcap 28 0>, <&cpcap 22 0>, <&cpcap 21 0>, - <&cpcap 20 0>, <&cpcap 19 0>, <&cpcap 54 0>; - interrupt-names = - "chrg_det", "rvrs_chrg", "chrg_se1b", - "se0conn", "rvrs_mode", "chrgcurr2", - "chrgcurr1", "vbusvld", "battdetb"; - mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>, - <&gpio3 23 GPIO_ACTIVE_LOW>; - io-channels = <&cpcap_adc 0>, <&cpcap_adc 1>, - <&cpcap_adc 2>, <&cpcap_adc 5>, - <&cpcap_adc 6>; - io-channel-names = "battdetb", "battp", - "vbus", "chg_isense", - "batti"; - }; - - cpcap_regulator: regulator { - compatible = "motorola,mapphone-cpcap-regulator"; - - cpcap_regulators: regulators { - }; - }; - - cpcap_audio: audio-codec { - #sound-dai-cells = <1>; - - port@0 { - cpcap_audio_codec0: endpoint { - }; - }; - port@1 { - cpcap_audio_codec1: endpoint { - }; - }; - }; - - cpcap_rtc: rtc { - compatible = "motorola,cpcap-rtc"; - - interrupt-parent = <&cpcap>; - interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>; - }; - - power_button: button { - compatible = "motorola,cpcap-pwrbutton"; - - interrupts = <23 IRQ_TYPE_NONE>; - }; - - cpcap_usb2_phy: phy { - compatible = "motorola,mapphone-cpcap-usb-phy"; - pinctrl-0 = <&usb_gpio_mux_sel1>, <&usb_gpio_mux_sel2>; - pinctrl-1 = <&usb_ulpi_pins>; - pinctrl-2 = <&usb_utmi_pins>; - pinctrl-3 = <&uart3_pins>; - pinctrl-names = "default", "ulpi", "utmi", "uart"; - #phy-cells = <0>; - interrupts-extended = - <&cpcap 15 0>, <&cpcap 14 0>, <&cpcap 28 0>, - <&cpcap 19 0>, <&cpcap 18 0>, <&cpcap 17 0>, - <&cpcap 16 0>, <&cpcap 49 0>, <&cpcap 48 0>; - interrupt-names = - "id_ground", "id_float", "se0conn", - "vbusvld", "sessvld", "sessend", - "se1", "dm", "dp"; - mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, - <&gpio1 0 GPIO_ACTIVE_HIGH>; - io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>; - io-channel-names = "vbus", "id"; - vusb-supply = <&vusb>; - }; - - led_red: led-red { - compatible = "motorola,cpcap-led-red"; - vdd-supply = <&sw5>; - label = "status-led:red"; - }; - - led_green: led-green { - compatible = "motorola,cpcap-led-green"; - vdd-supply = <&sw5>; - label = "status-led:green"; - }; - - led_blue: led-blue { - compatible = "motorola,cpcap-led-blue"; - vdd-supply = <&sw5>; - label = "status-led:blue"; - }; - - led_adl: led-adl { - compatible = "motorola,cpcap-led-adl"; - vdd-supply = <&sw5>; - label = "button-backlight"; - }; - - led_cp: led-cp { - compatible = "motorola,cpcap-led-cp"; - vdd-supply = <&sw5>; - label = "shift-key-light"; - }; - }; -}; - -&cpcap_regulators { - sw5: SW5 { - regulator-min-microvolt = <5050000>; - regulator-max-microvolt = <5050000>; - regulator-enable-ramp-delay = <50000>; - regulator-boot-on; - }; - - vcam: VCAM { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - /* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */ - vcsi: VCSI { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <1000>; - regulator-always-on; - }; - - vdac: VDAC { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <1000>; - }; - - vdig: VDIG { - regulator-min-microvolt = <1875000>; - regulator-max-microvolt = <1875000>; - regulator-enable-ramp-delay = <1000>; - }; - - vfuse: VFUSE { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3150000>; - regulator-enable-ramp-delay = <1000>; - }; - - vhvio: VHVIO { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - regulator-always-on; - }; - - /* Used by eMMC at mmc2 */ - vsdio: VSDIO { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - vpll: VPLL { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <100>; - }; - - vrf1: VRF1 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - }; - - vrf2: VRF2 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - }; - - vrfref: VRFREF { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <100>; - }; - - vwlan1: VWLAN1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1900000>; - regulator-enable-ramp-delay = <1000>; - }; - - /* Used by micro-SDIO at mmc1 */ - vwlan2: VWLAN2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <1000>; - }; - - vsim: VSIM { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - vsimcard: VSIMCARD { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - vvib: VVIB { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <500>; - }; - - vusb: VUSB { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <1000>; - }; - - vaudio: VAUDIO { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - regulator-initial-mode = <0x00>; /* NORMAL */ - }; -}; diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi deleted file mode 100644 index 091ba310053e..000000000000 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ /dev/null @@ -1,737 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include -#include "omap443x.dtsi" -#include "motorola-cpcap-mapphone.dtsi" - -/ { - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &lcd0; - display1 = &hdmi0; - }; - - /* - * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, - * then 1023 - 1024 seems to contain mbm. - */ - memory { - device_type = "memory"; - reg = <0x80000000 0x3fd00000>; /* 1021 MB */ - }; - - /* Poweroff GPIO probably connected to CPCAP */ - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff_gpio>; - pinctrl-names = "default"; - gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */ - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - pinctrl-0 = <&hdmi_hpd_gpio>; - pinctrl-names = "default"; - label = "hdmi"; - type = "d"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - /* - * HDMI 5V regulator probably sourced from battery. Let's keep - * keep this as always enabled for HDMI to work until we've - * figured what the encoder chip is. - */ - hdmi_regulator: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "hdmi"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */ - enable-active-high; - regulator-always-on; - }; - - /* FS USB Host PHY on port 1 for mdm6600 */ - fsusb1_phy: usb-phy@1 { - compatible = "motorola,mapphone-mdm6600"; - pinctrl-0 = <&usb_mdm6600_pins>; - pinctrl-names = "default"; - enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ - power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ - reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ - /* mode: gpio_148 gpio_149 */ - motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, - <&gpio5 21 GPIO_ACTIVE_HIGH>; - /* cmd: gpio_103 gpio_104 gpio_142 */ - motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, - <&gpio4 8 GPIO_ACTIVE_HIGH>, - <&gpio5 14 GPIO_ACTIVE_HIGH>; - /* status: gpio_52 gpio_53 gpio_55 */ - motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, - <&gpio2 21 GPIO_ACTIVE_HIGH>, - <&gpio2 23 GPIO_ACTIVE_HIGH>; - #phy-cells = <0>; - }; - - /* HS USB host TLL nop-phy on port 2 for w3glte */ - hsusb2_phy: usb-phy@2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - /* LCD regulator from sw5 source */ - lcd_regulator: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd"; - regulator-min-microvolt = <5050000>; - regulator-max-microvolt = <5050000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ - enable-active-high; - vin-supply = <&sw5>; - }; - - /* This is probably coming straight from the battery.. */ - wl12xx_vmmc: regulator-wl12xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - soundcard { - compatible = "audio-graph-card"; - label = "Mapphone Audio"; - - widgets = - "Speaker", "Earpiece", - "Speaker", "Loudspeaker", - "Headphone", "Headphone Jack", - "Microphone", "Internal Mic"; - - routing = - "Earpiece", "EP", - "Loudspeaker", "SPKR", - "Headphone Jack", "HSL", - "Headphone Jack", "HSR", - "MICR", "Internal Mic"; - - dais = <&mcbsp2_port>, <&mcbsp3_port>; - }; - - pwm8: pwm-8 { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_direction_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer8>; - ti,clock-source = <0x01>; - }; - - pwm9: pwm-9 { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_enable_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x01>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; - pwm-names = "enable", "direction"; - direction-duty-cycle-ns = <10000000>; - }; - - backlight: backlight { - compatible = "led-backlight"; - - leds = <&backlight_led>; - brightness-levels = <31 63 95 127 159 191 223 255>; - default-brightness-level = <6>; - }; -}; - -&cpu_thermal { - polling-delay = <10000>; /* milliseconds */ -}; - -&cpu_alert0 { - temperature = <80000>; /* millicelsius */ -}; - -&cpu0 { - /* - * Note that the 1.2GiHz mode is enabled for all SoC variants for - * the Motorola Android Linux v3.0.8 based kernel. - */ - operating-points = < - /* kHz uV */ - 300000 1025000 - 600000 1200000 - 800000 1313000 - 1008000 1375000 - 1200000 1375000 - >; -}; - -&dss { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - vdd-supply = <&vcsi>; - - port { - dsi1_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd0: panel@0 { - compatible = "motorola,droid4-panel", "panel-dsi-cm"; - reg = <0>; - label = "lcd0"; - vddi-supply = <&lcd_regulator>; - reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - - backlight = <&backlight>; - - width-mm = <50>; - height-mm = <89>; - rotation = <90>; - - panel-timing { - clock-frequency = <0>; /* Calculated by dsi */ - - hback-porch = <2>; - hactive = <540>; - hfront-porch = <0>; - hsync-len = <2>; - - vback-porch = <1>; - vactive = <960>; - vfront-porch = <0>; - vsync-len = <1>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; - }; -}; - -&hdmi { - status = "okay"; - pinctrl-0 = <&dss_hdmi_pins>; - pinctrl-names = "default"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; - -/* Battery NVRAM on 1-wire handled by w1_ds250x driver */ -&hdqw1w { - pinctrl-0 = <&hdq_pins>; - pinctrl-names = "default"; - ti,mode = "1w"; -}; - -&i2c1 { - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - pinctrl-0 = <&tmp105_irq>; - pinctrl-names = "default"; - /* kpd_row0.gpio_178 */ - interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING - &omap4_pmx_core 0x14e>; - interrupt-names = "irq", "wakeup"; - wakeup-source; - }; -}; - -&mmc1 { - vmmc-supply = <&vwlan2>; - bus-width = <4>; - cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */ -}; - -&mmc2 { - vmmc-supply = <&vsdio>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - vmmc-supply = <&wl12xx_vmmc>; - /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0xde>; - interrupt-names = "irq", "wakeup"; - non-removable; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1285"; - reg = <2>; - /* gpio_100 with gpmc_wait2 pad as wakeirq */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, - <&omap4_pmx_core 0x4e>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&i2c2 { - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; - - reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; /* gpio173 */ - - /* gpio_183 with sys_nirq2 pad as wakeup */ - interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, - <&omap4_pmx_core 0x160>; - interrupt-names = "irq", "wakeup"; - wakeup-source; - }; - - isl29030@44 { - compatible = "isil,isl29030"; - reg = <0x44>; - - pinctrl-names = "default"; - pinctrl-0 = <&als_proximity_pins>; - - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ - }; -}; - -&omap4_pmx_core { - - /* hdmi_hpd.gpio_63 */ - hdmi_hpd_gpio: hdmi-hpd-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) - >; - }; - - hdq_pins: hdq-pins { - pinctrl-single,pins = < - /* 0x4a100120 hdq_sio.hdq_sio aa27 */ - OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) - >; - }; - - /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) - >; - }; - - /* - * Android uses PIN_OFF_INPUT_PULLDOWN | PIN_INPUT_PULLUP | MUX_MODE3 - * for gpio_100, but the internal pull makes wlan flakey on some - * devices. Off mode value should be tested if we have off mode working - * later on. - */ - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - /* 0x4a10008e gpmc_wait2.gpio_100 d23 */ - OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3) - - /* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */ - OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */ - OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */ - OMAP4_IOPAD(0x118, PIN_INPUT | MUX_MODE1) - - /* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */ - OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */ - OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1) - >; - }; - - /* gpmc_ncs0.gpio_50 */ - poweroff_gpio: poweroff-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) - >; - }; - - /* kpd_row0.gpio_178 */ - tmp105_irq: tmp105-irq-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - usb_gpio_mux_sel1: usb-gpio-mux-sel1-pins { - /* gpio_60 */ - pinctrl-single,pins = < - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) - >; - }; - - touchscreen_pins: touchscreen-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) - OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - als_proximity_pins: als-proximity-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - usb_mdm6600_pins: usb-mdm6600-pins { - pinctrl-single,pins = < - /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) - - /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ - OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) - - /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) - - /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ - OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) - - /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ - OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) - - /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ - OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) - - /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) - - /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ - OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) - - /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ - OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) - - /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ - OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) - - /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) - >; - }; - - usb_ulpi_pins: usb-ulpi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, MUX_MODE7) - OMAP4_IOPAD(0x198, MUX_MODE7) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - /* usb0_otg_dp and usb0_otg_dm */ - usb_utmi_pins: usb-utmi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; - - /* - * Note that the v3.0.8 stock userspace dynamically remuxes uart1 - * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 - * when not used. If needed, we can add rts pin remux later based - * on power measurements. - */ - uart1_pins: uart1-pins { - pinctrl-single,pins = < - /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ - OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ - OMAP4_IOPAD(0x13e, MUX_MODE1) - - /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ - OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) - - /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ - OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) - >; - }; - - /* uart3_tx_irtx and uart3_rx_irrx */ - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, MUX_MODE7) - OMAP4_IOPAD(0x198, MUX_MODE7) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1ba, MUX_MODE2) - OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; - - uart4_pins: uart4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ - OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ - OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ - OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ - >; - }; - - mcbsp3_pins: mcbsp3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ - OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ - OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ - OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ - >; - }; - - vibrator_direction_pin: vibrator-direction-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ - >; - }; - - vibrator_enable_pin: vibrator-enable-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ - >; - }; -}; - -&omap4_pmx_wkup { - usb_gpio_mux_sel2: usb-gpio-mux-sel2-pins { - /* gpio_wk0 */ - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -/* RNG is used by secure mode and not accessible */ -&rng_target { - status = "disabled"; -}; - -/* Configure pwm clock source for timers 8 & 9 */ -&timer8 { - assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; -}; - -&timer9 { - assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; -}; - -/* - * The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149 - * for wake-up events for both the USB PHY and the UART. We can use gpio_149 - * pad as the shared wakeirq for the UART rather than the RX or CTS pad as we - * have gpio_149 trigger before the UART transfer starts. - */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x110>; - uart-has-rtscts; - current-speed = <115200>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x17c>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - bluetooth { - compatible = "ti,wl1285-st"; - enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ - max-speed = <3686400>; - }; -}; - -&usbhsohci { - phys = <&fsusb1_phy>; - phy-names = "usb"; -}; - -&usbhsehci { - phys = <&hsusb2_phy>; -}; - -&usbhshost { - port1-mode = "ohci-phy-4pin-dpdm"; - port2-mode = "ehci-tll"; -}; - -/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - - /* - * Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4. - * VBUS Regulator Main Characteristics". Binding uses 2 mA units. - */ - power = <150>; -}; - -&i2c4 { - ak8975: magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */ - - rotation-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - - }; -}; - -&mcbsp2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; - - mcbsp2_port: port { - cpu_dai2: endpoint { - dai-format = "i2s"; - remote-endpoint = <&cpcap_audio_codec0>; - frame-master = <&cpcap_audio_codec0>; - bitclock-master = <&cpcap_audio_codec0>; - }; - }; -}; - -&mcbsp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; - status = "okay"; - - mcbsp3_port: port { - cpu_dai3: endpoint { - dai-format = "dsp_a"; - frame-master = <&cpcap_audio_codec1>; - bitclock-master = <&cpcap_audio_codec1>; - remote-endpoint = <&cpcap_audio_codec1>; - }; - }; -}; - -&cpcap_audio_codec0 { - remote-endpoint = <&cpu_dai2>; -}; - -&cpcap_audio_codec1 { - remote-endpoint = <&cpu_dai3>; -}; diff --git a/arch/arm/boot/dts/moxa/Makefile b/arch/arm/boot/dts/moxa/Makefile new file mode 100644 index 000000000000..d61ce8d4e732 --- /dev/null +++ b/arch/arm/boot/dts/moxa/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MOXART) += \ + moxart-uc7112lx.dtb diff --git a/arch/arm/boot/dts/moxa/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxa/moxart-uc7112lx.dts new file mode 100644 index 000000000000..e07b807b4cec --- /dev/null +++ b/arch/arm/boot/dts/moxa/moxart-uc7112lx.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX + * + * Copyright (C) 2013 Jonas Jensen + */ + +/dts-v1/; +#include "moxart.dtsi" + +/ { + model = "MOXA UC-7112-LX"; + compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; + + memory { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + clocks { + ref12: ref12M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + }; + + flash@80000000,0 { + compatible = "numonyx,js28f128", "cfi-flash"; + reg = <0x80000000 0x1000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0x0 0x40000>; + }; + partition@40000 { + label = "linux kernel"; + reg = <0x40000 0x1C0000>; + }; + partition@200000 { + label = "root filesystem"; + reg = <0x200000 0x800000>; + }; + partition@a00000 { + label = "user filesystem"; + reg = <0xa00000 0x600000>; + }; + }; + + leds { + compatible = "gpio-leds"; + user-led { + label = "ready-led"; + gpios = <&gpio 27 0x1>; + default-state = "on"; + linux,default-trigger = "default-on"; + }; + }; + + gpio_keys_polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <500>; + button@25 { + label = "GPIO Reset"; + linux,code = <116>; + gpios = <&gpio 25 1>; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; + }; +}; + +&clk_pll { + clocks = <&ref12>; +}; + +&mmc { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mdio1 { + status = "okay"; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac0 { + status = "okay"; +}; + +&mac1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/moxa/moxart.dtsi b/arch/arm/boot/dts/moxa/moxart.dtsi new file mode 100644 index 000000000000..11cbea5b94d2 --- /dev/null +++ b/arch/arm/boot/dts/moxa/moxart.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC + * + * Copyright (C) 2013 Jonas Jensen + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "moxa,moxart"; + model = "MOXART"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "faraday,fa526"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x90000000 0x10000000>; + ranges; + + intc: interrupt-controller@98800000 { + compatible = "moxa,moxart-ic", "faraday,ftintc010"; + reg = <0x98800000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-mask = <0x00080000>; + }; + + clk_pll: clk_pll@98100000 { + compatible = "moxa,moxart-pll-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + }; + + clk_apb: clk_apb@98100000 { + compatible = "moxa,moxart-apb-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + clocks = <&clk_pll>; + }; + + timer: timer@98400000 { + compatible = "moxa,moxart-timer", "faraday,fttmr010"; + reg = <0x98400000 0x42>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk_apb>; + clock-names = "PCLK"; + }; + + gpio: gpio@98700000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "moxa,moxart-gpio", "faraday,ftgpio010"; + reg = <0x98700000 0x100>; + }; + + rtc: rtc { + compatible = "moxa,moxart-rtc"; + gpio-rtc-sclk = <&gpio 5 0>; + gpio-rtc-data = <&gpio 6 0>; + gpio-rtc-reset = <&gpio 7 0>; + }; + + dma: dma@90500000 { + compatible = "moxa,moxart-dma"; + reg = <0x90500080 0x40>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + }; + + watchdog: watchdog@98500000 { + compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; + reg = <0x98500000 0x10>; + clocks = <&clk_apb>; + clock-names = "PCLK"; + }; + + mmc: mmc@98e00000 { + compatible = "moxa,moxart-mmc"; + reg = <0x98e00000 0x5C>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_apb>; + dmas = <&dma 5>, + <&dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mdio0: mdio@90900090 { + compatible = "moxa,moxart-mdio"; + reg = <0x90900090 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mdio1: mdio@92000090 { + compatible = "moxa,moxart-mdio"; + reg = <0x92000090 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac0: mac@90900000 { + compatible = "moxa,moxart-mac"; + reg = <0x90900000 0x90>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy0>; + phy-mode = "mii"; + status = "disabled"; + }; + + mac1: mac@92000000 { + compatible = "moxa,moxart-mac"; + reg = <0x92000000 0x90>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <ðphy1>; + phy-mode = "mii"; + status = "disabled"; + }; + + uart0: serial@98200000 { + compatible = "ns16550a"; + reg = <0x98200000 0x20>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14745600>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts deleted file mode 100644 index e07b807b4cec..000000000000 --- a/arch/arm/boot/dts/moxart-uc7112lx.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX - * - * Copyright (C) 2013 Jonas Jensen - */ - -/dts-v1/; -#include "moxart.dtsi" - -/ { - model = "MOXA UC-7112-LX"; - compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; - - memory { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - clocks { - ref12: ref12M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - }; - - flash@80000000,0 { - compatible = "numonyx,js28f128", "cfi-flash"; - reg = <0x80000000 0x1000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "bootloader"; - reg = <0x0 0x40000>; - }; - partition@40000 { - label = "linux kernel"; - reg = <0x40000 0x1C0000>; - }; - partition@200000 { - label = "root filesystem"; - reg = <0x200000 0x800000>; - }; - partition@a00000 { - label = "user filesystem"; - reg = <0xa00000 0x600000>; - }; - }; - - leds { - compatible = "gpio-leds"; - user-led { - label = "ready-led"; - gpios = <&gpio 27 0x1>; - default-state = "on"; - linux,default-trigger = "default-on"; - }; - }; - - gpio_keys_polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <500>; - button@25 { - label = "GPIO Reset"; - linux,code = <116>; - gpios = <&gpio 25 1>; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; - }; -}; - -&clk_pll { - clocks = <&ref12>; -}; - -&mmc { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - ethphy0: ethernet-phy@1 { - device_type = "ethernet-phy"; - compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mdio1 { - status = "okay"; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mac0 { - status = "okay"; -}; - -&mac1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi deleted file mode 100644 index 11cbea5b94d2..000000000000 --- a/arch/arm/boot/dts/moxart.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC - * - * Copyright (C) 2013 Jonas Jensen - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "moxa,moxart"; - model = "MOXART"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "faraday,fa526"; - reg = <0>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x90000000 0x10000000>; - ranges; - - intc: interrupt-controller@98800000 { - compatible = "moxa,moxart-ic", "faraday,ftintc010"; - reg = <0x98800000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-mask = <0x00080000>; - }; - - clk_pll: clk_pll@98100000 { - compatible = "moxa,moxart-pll-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - }; - - clk_apb: clk_apb@98100000 { - compatible = "moxa,moxart-apb-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - clocks = <&clk_pll>; - }; - - timer: timer@98400000 { - compatible = "moxa,moxart-timer", "faraday,fttmr010"; - reg = <0x98400000 0x42>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; - - gpio: gpio@98700000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "moxa,moxart-gpio", "faraday,ftgpio010"; - reg = <0x98700000 0x100>; - }; - - rtc: rtc { - compatible = "moxa,moxart-rtc"; - gpio-rtc-sclk = <&gpio 5 0>; - gpio-rtc-data = <&gpio 6 0>; - gpio-rtc-reset = <&gpio 7 0>; - }; - - dma: dma@90500000 { - compatible = "moxa,moxart-dma"; - reg = <0x90500080 0x40>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - }; - - watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; - reg = <0x98500000 0x10>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; - - mmc: mmc@98e00000 { - compatible = "moxa,moxart-mmc"; - reg = <0x98e00000 0x5C>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_apb>; - dmas = <&dma 5>, - <&dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mdio0: mdio@90900090 { - compatible = "moxa,moxart-mdio"; - reg = <0x90900090 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mdio1: mdio@92000090 { - compatible = "moxa,moxart-mdio"; - reg = <0x92000090 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac0: mac@90900000 { - compatible = "moxa,moxart-mac"; - reg = <0x90900000 0x90>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - phy-handle = <ðphy0>; - phy-mode = "mii"; - status = "disabled"; - }; - - mac1: mac@92000000 { - compatible = "moxa,moxart-mac"; - reg = <0x92000000 0x90>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - phy-handle = <ðphy1>; - phy-mode = "mii"; - status = "disabled"; - }; - - uart0: serial@98200000 { - compatible = "ns16550a"; - reg = <0x98200000 0x20>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <14745600>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts deleted file mode 100644 index 005c2758e229..000000000000 --- a/arch/arm/boot/dts/mpa1600.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * mpa1600.dts - Device Tree file for Phontech MPA 1600 - * - * Copyright (C) 2013 Joachim Eastwood - */ -/dts-v1/; -#include "at91rm9200.dtsi" - -/ { - model = "Phontech MPA 1600"; - compatible = "phontech,mpa1600", "atmel,at91rm9200"; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - ssc0: ssc@fffd0000 { - status = "okay"; - }; - - ssc1: ssc@fffd4000 { - status = "okay"; - }; - }; - - usb0: ohci@300000 { - num-ports = <1>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - monitor_mute { - label = "Monitor mute"; - gpios = <&pioC 1 GPIO_ACTIVE_LOW>; - linux,code = <113>; - }; - }; -}; diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/mps2-an385.dts deleted file mode 100644 index aebbebfc25d1..000000000000 --- a/arch/arm/boot/dts/mps2-an385.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "mps2.dtsi" - -/ { - model = "ARM MPS2 Application Note 385/386"; - compatible = "arm,mps2"; - - aliases { - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:9600n8"; - }; - - memory@21000000 { - device_type = "memory"; - reg = <0x21000000 0x1000000>; - }; - - smb { - ethernet@0,0 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0 0x0 0x10000>; - interrupts = <13>; - interrupt-parent = <&nvic>; - smsc,irq-active-high; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/mps2-an399.dts deleted file mode 100644 index 349abf70b2a5..000000000000 --- a/arch/arm/boot/dts/mps2-an399.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "mps2.dtsi" - -/ { - model = "ARM MPS2 Application Note 399/400"; - compatible = "arm,mps2"; - - aliases { - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:9600n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x1000000>; - }; - - smb { - ethernet@1,0 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <1 0x0 0x10000>; - interrupts = <13>; - interrupt-parent = <&nvic>; - smsc,irq-active-high; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi deleted file mode 100644 index b99577d411b1..000000000000 --- a/arch/arm/boot/dts/mps2.dtsi +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - oscclk0: clk-osc0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - oscclk1: clk-osc1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - oscclk2: clk-osc2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - cfgclk: clk-cfg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; - }; - - spicfgclk: clk-spicfg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <75000000>; - }; - - sysclk: clk-sys { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - audmclk: clk-audm { - compatible = "fixed-factor-clock"; - clocks = <&oscclk1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - audsclk: clk-auds { - compatible = "fixed-factor-clock"; - clocks = <&oscclk1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - - spiclcd: clk-cpiclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - spicon: clk-spicon { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2cclcd: clk-i2cclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2caud: clk-i2caud { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - soc { - compatible = "simple-bus"; - ranges; - - apb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x10000>; - - timer0: mps2-timer0@0 { - compatible = "arm,mps2-timer"; - reg = <0x0 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; - status = "disabled"; - }; - - timer1: mps2-timer1@1000 { - compatible = "arm,mps2-timer"; - reg = <0x1000 0x1000>; - interrupts = <9>; - clocks = <&sysclk>; - status = "disabled"; - }; - - timer2: dual-timer@2000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x2000 0x1000>; - clocks = <&sysclk>, <&sysclk>, <&sysclk>; - clock-names = "timer0clk", "timer1clk", - "apb_pclk"; - interrupts = <10>; - status = "disabled"; - }; - - uart0: serial@4000 { - compatible = "arm,mps2-uart"; - reg = <0x4000 0x1000>; - interrupts = <0>, <1>, <12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - uart1: serial@5000 { - compatible = "arm,mps2-uart"; - reg = <0x5000 0x1000>; - interrupts = <2>, <3>, <12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - uart2: serial@6000 { - compatible = "arm,mps2-uart"; - reg = <0x6000 0x1000>; - interrupts = <4>, <5>, <12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - wdt: watchdog@8000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0x8000 0x1000>; - interrupts = <0>; - clocks = <&sysclk>, <&sysclk>; - clock-names = "wdog_clk", "apb_pclk"; - status = "disabled"; - }; - }; - }; - - fpga@40020000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x10000>; - - fpgaio@8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x8000 0x10>; - - ranges = <0x0 0x8000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - - led@0,0 { - compatible = "register-bit-led"; - reg = <0x00 0x04>; - offset = <0x0>; - mask = <0x01>; - label = "userled:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led@0,1 { - compatible = "register-bit-led"; - reg = <0x00 0x04>; - offset = <0x0>; - mask = <0x02>; - label = "userled:1"; - linux,default-trigger = "usr"; - default-state = "off"; - }; - }; - }; - - smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40200000 0x10000>, - <1 0 0xa0000000 0x10000>; - }; -}; diff --git a/arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi b/arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi deleted file mode 100644 index 507ff2fba837..000000000000 --- a/arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include - -/ { - vcc_core: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_core"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - }; - - vcc_dram: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vcc_dram"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - vcc_io: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - red { - gpios = <&gpio MSC313_GPIO_SR_IO16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "activity"; - }; - yellow { - gpios = <&gpio MSC313_GPIO_SR_IO17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vcc_core>; -}; diff --git a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts deleted file mode 100644 index db4910dcb8a7..000000000000 --- a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-infinity-msc313.dtsi" -#include "mstar-infinity-breadbee-common.dtsi" - -/ { - model = "BreadBee Crust"; - compatible = "thingyjp,breadbee-crust", "mstar,infinity"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi deleted file mode 100644 index 3499fde263be..000000000000 --- a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-infinity.dtsi" - -/ { - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x4000000>; - }; -}; diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi deleted file mode 100644 index 441a917b88ba..000000000000 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-v7.dtsi" - -#include - -/ { - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-240000000 { - opp-hz = /bits/ 64 <240000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&imi { - reg = <0xa0000000 0x16000>; -}; - -&gpio { - compatible = "mstar,msc313-gpio"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi deleted file mode 100644 index 34df472fed71..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 thingy.jp. - * Author: Daniel Palmer - * Author: Romain Perier - */ - -/ { - reg_vcc_dram: regulator-vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc_dram"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts deleted file mode 100644 index f25a04c98ccb..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2021 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-infinity2m-ssd202d.dtsi" - -/ { - model = "DongShanPi One"; - compatible = "100ask,dongshanpione", "mstar,infinity2m"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts deleted file mode 100644 index 1bbbf47132dc..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2021 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-infinity2m-ssd202d.dtsi" - -/ { - model = "Miyoo Mini"; - compatible = "miyoo,miyoo-mini", "mstar,infinity2m"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts deleted file mode 100644 index 5d81641414a2..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-infinity2m-ssd202d.dtsi" - -/ { - model = "SSD201_HT_V2"; - compatible = "honestar,ssd201htv2", "mstar,infinity2m"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts deleted file mode 100644 index a81684002e45..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2021 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-infinity2m-ssd202d.dtsi" - -/ { - model = "UnitV2"; - compatible = "m5stack,unitv2", "mstar,infinity2m"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts deleted file mode 100644 index b15c40762bc0..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 thingy.jp. - * Author: Daniel Palmer - * Author: Romain Perier - */ - -/dts-v1/; -#include "mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi" -#include - -/ { - model = "Wireless Tag IDO-SBC2D06-1VB-22W"; - compatible = "wirelesstag,ido-sbc2d06-v1b-22w", "mstar,infinity2m"; - - leds { - compatible = "gpio-leds"; - sys_led { - gpios = <&gpio SSD20XD_GPIO_GPIO85 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi deleted file mode 100644 index d877aff85033..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 thingy.jp. - * Author: Daniel Palmer - * Author: Romain Perier - */ - -/dts-v1/; -#include "mstar-infinity2m-ssd202d.dtsi" -#include "mstar-infinity2m-ssd201-som2d01.dtsi" - -/ { - model = "Wireless Tag IDO-SOM2D01 (SSD202D)"; - compatible = "wirelesstag,ido-som2d01", "mstar,infinity2m"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -®_vcc_dram { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi deleted file mode 100644 index 176e10a29896..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-infinity2m-ssd20xd.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x20000000 0x8000000>; - }; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi deleted file mode 100644 index 6f067da61ba3..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-infinity2m.dtsi" - -&gpio { - compatible = "sstar,ssd20xd-gpio"; - status = "okay"; -}; - -&smpctrl { - compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi deleted file mode 100644 index 1b485efd7156..000000000000 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-infinity.dtsi" - -&cpu0_opp_table { - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; -}; - -&cpus { - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - operating-points-v2 = <&cpu0_opp_table>; - reg = <0x1>; - clocks = <&cpupll>; - clock-names = "cpuclk"; - }; -}; - -&riu { - smpctrl: smpctrl@204000 { - reg = <0x204000 0x200>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts deleted file mode 100644 index e64ca4ce1830..000000000000 --- a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-infinity3-msc313e.dtsi" -#include "mstar-infinity-breadbee-common.dtsi" - -/ { - model = "BreadBee"; - compatible = "thingyjp,breadbee", "mstar,infinity3"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi deleted file mode 100644 index f581b6f89555..000000000000 --- a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-infinity3.dtsi" - -/ { - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x4000000>; - }; -}; diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi deleted file mode 100644 index a56cf29e5d82..000000000000 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-infinity.dtsi" - -&cpu0_opp_table { - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - // overclock frequencies below, shown to work fine up to 1.3 GHz - opp-108000000 { - opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - - opp-1188000000 { - opp-hz = /bits/ 64 <1188000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - - opp-1350000000 { - opp-hz = /bits/ 64 <1350000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - - opp-1458000000 { - opp-hz = /bits/ 64 <1458000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - turbo-mode; - }; -}; - -&imi { - reg = <0xa0000000 0x20000>; -}; diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts deleted file mode 100644 index 7306b737d9c4..000000000000 --- a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mstar-mercury5-ssc8336n.dtsi" - -/ { - model = "70mai Midrive D08"; - compatible = "70mai,midrived08", "mstar,mercury5"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi deleted file mode 100644 index 3f5a4c029744..000000000000 --- a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-mercury5.dtsi" - -/ { - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x4000000>; - }; -}; diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi deleted file mode 100644 index a7d0dd9d6132..000000000000 --- a/arch/arm/boot/dts/mstar-mercury5.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-v7.dtsi" - -&imi { - reg = <0xa0000000 0x20000>; -}; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi deleted file mode 100644 index 3eeafd8c7121..000000000000 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&cpupll>; - clock-names = "cpuclk"; - }; - }; - - arch_timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - /* - * we shouldn't need this but the vendor - * u-boot is broken - */ - clock-frequency = <6000000>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>; - }; - - clocks: clocks { - xtal: xtal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - rtc_xtal: rtc_xtal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - status = "disabled"; - }; - - xtal_div2: xtal_div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&xtal>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x16001000 0x16001000 0x00007000>, - <0x1f000000 0x1f000000 0x00400000>, - <0xa0000000 0xa0000000 0x20000>; - - gic: interrupt-controller@16001000 { - compatible = "arm,cortex-a7-gic"; - reg = <0x16001000 0x1000>, - <0x16002000 0x2000>, - <0x16004000 0x2000>, - <0x16006000 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - riu: bus@1f000000 { - compatible = "simple-bus"; - reg = <0x1f000000 0x00400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1f000000 0x00400000>; - - pmsleep: syscon@1c00 { - compatible = "mstar,msc313-pmsleep", "syscon"; - reg = <0x1c00 0x100>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&pmsleep>; - offset = <0xb8>; - mask = <0x79>; - }; - - rtc@2400 { - compatible = "mstar,msc313-rtc"; - reg = <0x2400 0x40>; - clocks = <&xtal_div2>; - interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog@6000 { - compatible = "mstar,msc313e-wdt"; - reg = <0x6000 0x1f>; - clocks = <&xtal_div2>; - }; - - - intc_fiq: interrupt-controller@201310 { - compatible = "mstar,mst-intc"; - reg = <0x201310 0x40>; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&gic>; - mstar,irqs-map-range = <96 127>; - }; - - intc_irq: interrupt-controller@201350 { - compatible = "mstar,mst-intc"; - reg = <0x201350 0x40>; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&gic>; - mstar,irqs-map-range = <32 95>; - mstar,intc-no-eoi; - }; - - l3bridge: l3bridge@204400 { - compatible = "mstar,l3bridge"; - reg = <0x204400 0x200>; - }; - - mpll: mpll@206000 { - compatible = "mstar,msc313-mpll"; - #clock-cells = <1>; - reg = <0x206000 0x200>; - clocks = <&xtal>; - }; - - cpupll: cpupll@206400 { - compatible = "mstar,msc313-cpupll"; - reg = <0x206400 0x200>; - #clock-cells = <0>; - clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; - }; - - gpio: gpio@207800 { - #gpio-cells = <2>; - reg = <0x207800 0x200>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&intc_fiq>; - status = "disabled"; - }; - - pm_uart: serial@221000 { - compatible = "ns16550a"; - reg = <0x221000 0x100>; - reg-shift = <3>; - interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <172000000>; - status = "disabled"; - }; - }; - - imi: sram@a0000000 { - compatible = "mmio-sram"; - reg = <0xa0000000 0x10000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts deleted file mode 100644 index d1535f385f36..000000000000 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Erin Lo - * - */ - -/dts-v1/; -#include -#include "mt2701.dtsi" - -/ { - model = "MediaTek MT2701 evaluation board"; - compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - sound:sound { - compatible = "mediatek,mt2701-cs42448-machine"; - mediatek,platform = <&afe>; - /* CS42448 Machine name */ - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "AMIC", - "AIN1R", "AMIC", - "AIN2L", "Tuner In", - "AIN2R", "Tuner In", - "AIN3L", "Satellite Tuner In", - "AIN3R", "Satellite Tuner In", - "AIN3L", "AUX In", - "AIN3R", "AUX In"; - mediatek,audio-codec = <&cs42448>; - mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; - pinctrl-names = "default"; - pinctrl-0 = <&aud_pins_default>; - i2s1-in-sel-gpio1 = <&pio 53 0>; - i2s1-in-sel-gpio2 = <&pio 54 0>; - status = "okay"; - }; - - bt_sco_codec:bt_sco_codec { - compatible = "linux,bt-sco"; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&bls 0 100000>; - brightness-levels = < - 0 16 32 48 64 80 96 112 - 128 144 160 176 192 208 224 240 - 255 - >; - default-brightness-level = <9>; - }; - - usb_vbus: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 45 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&auxadc { - status = "okay"; -}; - -&bls { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_bls_gpio>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - cs42448: cs42448@48 { - compatible = "cirrus,cs42448"; - reg = <0x48>; - clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; - clock-names = "mclk"; - }; -}; - -&pio { - i2c0_pins_a: i2c0@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - pwm_bls_gpio: pwm_bls_gpio { - pins_cmd_dat { - pinmux = ; - }; - }; - - spi_pins_a: spi0@0 { - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - aud_pins_default: audiodefault { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - drive-strength = ; - bias-pull-down; - }; - }; - - spi_pins_b: spi1@0 { - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_c: spi2@0 { - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_a>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_b>; - status = "disabled"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_c>; - status = "disabled"; -}; - -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&nor_pins_default>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - -&pio { - nor_pins_default: nor { - pins1 { - pinmux = , - , - , - , - , - ; - drive-strength = ; - bias-pull-up; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb2 { - status = "okay"; - usb-role-switch; - connector{ - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; - vbus-supply = <&usb_vbus>; - }; -}; diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mt2701-pinfunc.h deleted file mode 100644 index 136a25a0ae28..000000000000 --- a/arch/arm/boot/dts/mt2701-pinfunc.h +++ /dev/null @@ -1,727 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Biao Huang - */ - -#ifndef __DTS_MT2701_PINFUNC_H -#define __DTS_MT2701_PINFUNC_H - -#include - -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) - -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) - -#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) - -#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) - -#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) - -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) - -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7) - -#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) -#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4) -#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7) - -#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) -#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) -#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4) -#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7) - -#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) -#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) -#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) -#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4) -#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7) - -#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) - -#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) - -#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) - -#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) - -#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) -#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2) -#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) -#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7) - -#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) -#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2) -#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7) - -#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) -#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) -#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) -#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) -#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6) -#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7) - -#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) -#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) -#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) -#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6) -#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7) - -#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) -#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2) -#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3) -#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) -#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) -#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6) -#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7) - -#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) -#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2) -#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3) -#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) -#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) -#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6) -#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7) - -#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1) -#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3) -#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) -#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) -#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7) -#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10) - -#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1) -#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3) -#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) -#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) -#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7) -#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10) - -#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1) -#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3) -#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) -#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7) -#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10) - -#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1) -#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3) -#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) -#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7) - -#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1) -#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) -#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3) -#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) -#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) -#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) -#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7) - -#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1) -#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) -#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3) -#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) -#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) -#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7) - -#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) -#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3) -#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) -#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) -#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7) - -#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1) -#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) -#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3) -#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) -#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) -#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7) -#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14) - -#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) -#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) -#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3) -#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) -#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) -#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6) -#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7) - -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7) - -#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) -#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) -#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) -#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6) -#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7) - -#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7) - -#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7) - -#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) -#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) -#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) -#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) - -#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) -#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) -#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) -#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) - -#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) -#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) -#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) - -#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) -#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) -#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) - -#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1) -#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) - -#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1) -#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2) - -#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1) -#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) - -#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1) - -#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1) -#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) - -#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1) -#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) - -#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) -#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) -#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3) -#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6) -#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7) - -#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) -#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3) -#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) -#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5) -#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7) - -#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) -#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) -#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) -#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7) - -#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) -#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) -#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) -#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) -#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5) -#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7) - -#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) -#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7) - -#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) - -#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) - -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7) - -#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7) - -#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) -#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) -#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6) -#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7) - -#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) - -#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) - -#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) - -#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) - -#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) -#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) -#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) - -#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) -#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) - -#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) -#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) - -#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) -#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) - -#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) -#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) -#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7) - -#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) -#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7) - -#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) -#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) - -#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) -#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) - -#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) -#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) - -#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) -#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) - -#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) -#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) - -#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) -#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) - -#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) -#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) - -#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) -#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) - -#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) -#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) - -#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) -#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) - -#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) -#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3) -#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4) - -#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) -#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) -#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3) -#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4) - -#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) -#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) -#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3) -#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4) - -#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) -#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3) -#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4) - -#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7) - -#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7) - -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7) - -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7) - -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7) - -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7) - -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4) - -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4) - -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4) - -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4) - -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4) - -#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) -#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4) - -#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) -#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4) - -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4) - -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4) - -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4) - -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) - -#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1) -#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4) -#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5) - -#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1) -#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4) -#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5) - -#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1) -#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4) -#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5) - -#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1) -#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4) -#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5) - -#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7) - -#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) -#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3) -#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4) -#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7) - -#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7) - -#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7) - -#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1) - -#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1) -#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) -#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5) -#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7) -#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9) - -#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1) -#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2) -#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5) -#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7) -#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9) - -#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1) -#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2) -#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5) -#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7) - -#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1) -#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2) -#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3) -#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5) -#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7) - -#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1) -#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2) -#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3) -#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5) -#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7) - -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11) - -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11) - -#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7) - -#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) -#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) -#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) - -#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) -#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) -#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2) - -#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) -#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) -#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2) - -#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) -#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) - -#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) -#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) - -#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) -#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1) -#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2) -#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3) -#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4) -#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7) - -#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) -#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1) -#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2) -#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3) -#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4) -#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7) - -#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) -#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1) - -#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) -#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1) - -#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) - -#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) -#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1) - -#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) -#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1) - -#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9) - -#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9) -#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14) - -#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9) -#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14) - -#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9) -#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14) - -#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9) -#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14) - -#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9) -#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14) - -#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9) -#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14) - -#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9) - -#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9) - -#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9) - -#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9) - -#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9) - -#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) -#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) -#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7) - -#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) -#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) - -#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) -#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) -#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6) - -#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) -#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) -#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6) - -#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) -#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) -#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6) - -#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) -#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) -#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6) - -#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) -#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1) - -#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) -#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1) - -#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) -#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) - -#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) -#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) - -#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0) -#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) - -#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0) -#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) - -#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0) -#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) - -#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0) -#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1) -#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6) - -#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0) -#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1) -#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6) - -#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0) -#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) - -#endif /* __DTS_MT2701_PINFUNC_H */ diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi deleted file mode 100644 index ce6a4015fed5..000000000000 --- a/arch/arm/boot/dts/mt2701.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Erin.Lo - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mt2701-pinfunc.h" - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt2701"; - interrupt-parent = <&cirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - rtc32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "rtc32k"; - }; - - thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&thermal 0>; - sustainable-power = <1000>; - - trips { - threshold: trip-point@0 { - temperature = <68000>; - hysteresis = <2000>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit@0 { - temperature = <115000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt2701-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt2701-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt2701-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - syscfg_pctl_a: syscfg@10005000 { - compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt2701-scpsys", "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - infracfg = <&infracfg>; - clocks = <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_MFG_SEL>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "mm", "mfg", "ethif"; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt2701-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt2701-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - pio: pinctrl@1000b000 { - compatible = "mediatek,mt2701-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - ; - }; - - smi_common: smi@1000c000 { - compatible = "mediatek,mt2701-smi-common"; - reg = <0 0x1000c000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_SMI>, - <&mmsys CLK_MM_SMI_COMMON>, - <&infracfg CLK_INFRA_SMI>; - clock-names = "apb", "smi", "async"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt2701-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - cirq: interrupt-controller@10204000 { - compatible = "mediatek,mt2701-cirq", - "mediatek,mtk-cirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&sysirq>; - reg = <0 0x10204000 0 0x400>; - mediatek,ext-irq-range = <32 200>; - }; - - iommu: mmsys_iommu@10205000 { - compatible = "mediatek,mt2701-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2>; - #iommu-cells = <1>; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt2701-apmixedsys", "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt2701-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt2701-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11007000 0 0x70>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt2701-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11008000 0 0x70>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt2701-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11009000 0 0x70>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <0>; - compatible = "mediatek,mt2701-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT2701_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - }; - - nandc: nand-controller@1100d000 { - compatible = "mediatek,mt2701-nfc"; - reg = <0 0x1100d000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names = "nfi_clk", "pad_clk"; - status = "disabled"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - }; - - bch: ecc@1100e000 { - compatible = "mediatek,mt2701-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_ECC>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - nor_flash: spi@11014000 { - compatible = "mediatek,mt2701-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; - clocks = <&pericfg CLK_PERI_FLASH>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11016000 { - compatible = "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI1_SEL>, - <&pericfg CLK_PERI_SPI1>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi2: spi@11017000 { - compatible = "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11017000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI2_SEL>, - <&pericfg CLK_PERI_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt2701-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - compatible = "mediatek,mt2701-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&audsys CLK_AUD_I2SO1>, - <&audsys CLK_AUD_I2SO2>, - <&audsys CLK_AUD_I2SO3>, - <&audsys CLK_AUD_I2SO4>, - <&audsys CLK_AUD_I2SIN1>, - <&audsys CLK_AUD_I2SIN2>, - <&audsys CLK_AUD_I2SIN3>, - <&audsys CLK_AUD_I2SIN4>, - <&audsys CLK_AUD_ASRCO1>, - <&audsys CLK_AUD_ASRCO2>, - <&audsys CLK_AUD_ASRCO3>, - <&audsys CLK_AUD_ASRCO4>, - <&audsys CLK_AUD_AFE>, - <&audsys CLK_AUD_AFE_CONN>, - <&audsys CLK_AUD_A1SYS>, - <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; - - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt2701-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - bls: pwm@1400a000 { - compatible = "mediatek,mt2701-disp-pwm"; - reg = <0 0x1400a000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - larb0: larb@14010000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt2701-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <2>; - clocks = <&imgsys CLK_IMG_SMI_COMM>, - <&imgsys CLK_IMG_SMI_COMM>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - }; - - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; - - jpegenc: jpegenc@1500a000 { - compatible = "mediatek,mt2701-jpgenc", - "mediatek,mtk-jpgenc"; - reg = <0 0x1500a000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_VENC>; - clock-names = "jpgenc"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, - <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt2701-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <1>; - clocks = <&vdecsys CLK_VDEC_CKGEN>, - <&vdecsys CLK_VDEC_LARB>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; - }; - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb0: usb@1a1c0000 { - compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci"; - reg = <0 0x1a1c0000 0 0x1000>, - <0 0x1a1c4700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB0PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy0: t-phy@1a1c4000 { - compatible = "mediatek,mt2701-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a1c4000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port0: usb-phy@1a1c4800 { - reg = <0 0x1a1c4800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@1a1c4900 { - reg = <0 0x1a1c4900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb1: usb@1a240000 { - compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci"; - reg = <0 0x1a240000 0 0x1000>, - <0 0x1a244700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB1PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy1: t-phy@1a244000 { - compatible = "mediatek,mt2701-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a244000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port1: usb-phy@1a244800 { - reg = <0 0x1a244800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port1: usb-phy@1a244900 { - reg = <0 0x1a244900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb2: usb@11200000 { - compatible = "mediatek,mt2701-musb", - "mediatek,mtk-musb"; - reg = <0 0x11200000 0 0x1000>; - interrupts = ; - interrupt-names = "mc"; - phys = <&u2port2 PHY_TYPE_USB2>; - dr_mode = "otg"; - clocks = <&pericfg CLK_PERI_USB0>, - <&pericfg CLK_PERI_USB0_MCU>, - <&pericfg CLK_PERI_USB_SLV>; - clock-names = "main","mcu","univpll"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - status = "disabled"; - }; - - u2phy0: t-phy@11210000 { - compatible = "mediatek,mt2701-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x11210000 0 0x0800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u2port2: usb-phy@1a1c4800 { - reg = <0 0x11210800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt2701-ethsys", "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt2701-eth", "syscon"; - reg = <0 0x1b100000 0 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_ESW>, - <ðsys CLK_ETHSYS_GP1>, - <ðsys CLK_ETHSYS_GP2>, - <&apmixedsys CLK_APMIXED_TRGPLL>; - clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; - resets = <ðsys MT2701_ETHSYS_FE_RST>, - <ðsys MT2701_ETHSYS_GMAC_RST>, - <ðsys MT2701_ETHSYS_PPE_RST>; - reset-names = "fe", "gmac", "ppe"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - mediatek,ethsys = <ðsys>; - mediatek,pctl = <&syscfg_pctl_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bdpsys: syscon@1c000000 { - compatible = "mediatek,mt2701-bdpsys", "syscon"; - reg = <0 0x1c000000 0 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/mt6323.dtsi b/arch/arm/boot/dts/mt6323.dtsi deleted file mode 100644 index 7fda40ab5fe8..000000000000 --- a/arch/arm/boot/dts/mt6323.dtsi +++ /dev/null @@ -1,269 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: John Crispin - * Sean Wang - * - */ - -&pwrap { - pmic: mt6323 { - compatible = "mediatek,mt6323"; - interrupt-parent = <&pio>; - interrupts = <150 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - - mt6323_leds: leds { - compatible = "mediatek,mt6323-led"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mt6323regulator: mt6323regulator{ - compatible = "mediatek,mt6323-regulator"; - - mt6323_vproc_reg: buck_vproc{ - regulator-name = "vproc"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vsys_reg: buck_vsys{ - regulator-name = "vsys"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <2987500>; - regulator-ramp-delay = <25000>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vpa_reg: buck_vpa{ - regulator-name = "vpa"; - regulator-min-microvolt = < 500000>; - regulator-max-microvolt = <3650000>; - }; - - mt6323_vtcxo_reg: ldo_vtcxo{ - regulator-name = "vtcxo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <90>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcn28_reg: ldo_vcn28{ - regulator-name = "vcn28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_vcn33_bt_reg: ldo_vcn33_bt{ - regulator-name = "vcn33_bt"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ - regulator-name = "vcn33_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_va_reg: ldo_va{ - regulator-name = "va"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcama_reg: ldo_vcama{ - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vio28_reg: ldo_vio28{ - regulator-name = "vio28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vusb_reg: ldo_vusb{ - regulator-name = "vusb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - regulator-boot-on; - }; - - mt6323_vmc_reg: ldo_vmc{ - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vmch_reg: ldo_vmch{ - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vemc3v3_reg: ldo_vemc3v3{ - regulator-name = "vemc3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vgp1_reg: ldo_vgp1{ - regulator-name = "vgp1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vgp2_reg: ldo_vgp2{ - regulator-name = "vgp2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vgp3_reg: ldo_vgp3{ - regulator-name = "vgp3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vcn18_reg: ldo_vcn18{ - regulator-name = "vcn18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vsim1_reg: ldo_vsim1{ - regulator-name = "vsim1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vsim2_reg: ldo_vsim2{ - regulator-name = "vsim2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vrtc_reg: ldo_vrtc{ - regulator-name = "vrtc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcamaf_reg: ldo_vcamaf{ - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vibr_reg: ldo_vibr{ - regulator-name = "vibr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - }; - - mt6323_vrf18_reg: ldo_vrf18{ - regulator-name = "vrf18"; - regulator-min-microvolt = <1825000>; - regulator-max-microvolt = <1825000>; - regulator-enable-ramp-delay = <187>; - }; - - mt6323_vm_reg: ldo_vm{ - regulator-name = "vm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vio18_reg: ldo_vio18{ - regulator-name = "vio18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcamd_reg: ldo_vcamd{ - regulator-name = "vcamd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vcamio_reg: ldo_vcamio{ - regulator-name = "vcamio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - }; - - mt6323keys: mt6323keys { - compatible = "mediatek,mt6323-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power { - linux,keycodes = <116>; - wakeup-source; - }; - - home { - linux,keycodes = <114>; - }; - }; - - codec: mt6397codec { - compatible = "mediatek,mt6397-codec"; - }; - - power-controller { - compatible = "mediatek,mt6323-pwrc"; - }; - - rtc { - compatible = "mediatek,mt6323-rtc"; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mt6580-evbp1.dts deleted file mode 100644 index 755a0774a8ee..000000000000 --- a/arch/arm/boot/dts/mt6580-evbp1.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - */ - -/dts-v1/; -#include "mt6580.dtsi" - -/ { - model = "MediaTek MT6580 evaluation board"; - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi deleted file mode 100644 index 9e17698c0609..000000000000 --- a/arch/arm/boot/dts/mt6580.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - */ - -#include -#include - -/ { - compatible = "mediatek,mt6580"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt6580-timer", - "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6580-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11005000 { - compatible = "mediatek,mt6580-uart", - "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11006000 { - compatible = "mediatek,mt6580-uart", - "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts b/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts deleted file mode 100644 index b057e037f940..000000000000 --- a/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2021 Maxim Kutnij - */ - -/dts-v1/; -#include "mt6582.dtsi" - -/ { - model = "Prestigio PMT5008 3G"; - compatible = "prestigio,pmt5008-3g", "mediatek,mt6582"; - - aliases { - bootargs = "console=ttyS0,921600n8 earlyprintk"; - serial0 = &uart0; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt6582.dtsi b/arch/arm/boot/dts/mt6582.dtsi deleted file mode 100644 index 4263371784cd..000000000000 --- a/arch/arm/boot/dts/mt6582.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2021 Maxim Kutnij - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt6582"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@11008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6582-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt6582-wdt", - "mediatek,mt6589-wdt"; - reg = <0x10007000 0x100>; - }; -}; diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts deleted file mode 100644 index 1e7079a3b449..000000000000 --- a/arch/arm/boot/dts/mt6589-aquaris5.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Matthias Brugger - * - */ - -/dts-v1/; -#include "mt6589.dtsi" - -/ { - model = "bq Aquaris5"; - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; - - chosen { - bootargs = "console=ttyS0,921600n8 earlyprintk"; - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - -}; - -&uart0 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts deleted file mode 100644 index c952347981de..000000000000 --- a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Luca Weiss - */ - -/dts-v1/; -#include "mt6589.dtsi" - -/ { - model = "Fairphone 1"; - compatible = "fairphone,fp1", "mediatek,mt6589"; - - chosen { - stdout-path = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&cpus { - /* SMP is not stable on this board, makes the kernel panic */ - /delete-property/ enable-method; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi deleted file mode 100644 index c6babc8ad2ba..000000000000 --- a/arch/arm/boot/dts/mt6589.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Matthias Brugger - * -*/ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt6589"; - interrupt-parent = <&sysirq>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt6589-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - timer: timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6589-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11007000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11008000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11009000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x44>; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts deleted file mode 100644 index 5e00c1cca2d1..000000000000 --- a/arch/arm/boot/dts/mt6592-evb.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Howard Chen - * - */ - -/dts-v1/; -#include "mt6592.dtsi" - -/ { - model = "mt6592 evb"; - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi deleted file mode 100644 index 3716f8db951c..000000000000 --- a/arch/arm/boot/dts/mt6592.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Howard Chen - * - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt6592"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x4>; - }; - cpu@5 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x5>; - }; - cpu@6 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x6>; - }; - cpu@7 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x7>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200220 { - compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200220 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x1000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi deleted file mode 100644 index f0b4a09004b3..000000000000 --- a/arch/arm/boot/dts/mt7623.dtsi +++ /dev/null @@ -1,1313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: John Crispin - * Sean Wang - * Ryder Lee - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7623"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-98000000 { - opp-hz = /bits/ 64 <98000000>; - opp-microvolt = <1050000>; - }; - - opp-198000000 { - opp-hz = /bits/ 64 <198000000>; - opp-microvolt = <1050000>; - }; - - opp-398000000 { - opp-hz = /bits/ 64 <398000000>; - opp-microvolt = <1050000>; - }; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt6589-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc32k: oscillator-1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "rtc32k"; - }; - - clk26m: oscillator-0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&thermal 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <57000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { - temperature = <67000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu-hot { - temperature = <87000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu-crit { - temperature = <107000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt7623-topckgen", - "mediatek,mt2701-topckgen", - "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt7623-infracfg", - "mediatek,mt2701-infracfg", - "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt7623-pericfg", - "mediatek,mt2701-pericfg", - "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt7623-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - ; - }; - - syscfg_pctl_a: syscfg@10005000 { - compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt7623-scpsys", - "mediatek,mt2701-scpsys", - "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - infracfg = <&infracfg>; - clocks = <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_MFG_SEL>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "mm", "mfg", "ethif"; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt7623-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt7623-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc32k>; - clock-names = "system-clk", "rtc-clk"; - }; - - pwrap: pwrap@1000d000 { - compatible = "mediatek,mt7623-pwrap", - "mediatek,mt2701-pwrap"; - reg = <0 0x1000d000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; - reset-names = "pwrap"; - clocks = <&infracfg CLK_INFRA_PMICSPI>, - <&infracfg CLK_INFRA_PMICWRAP>; - clock-names = "spi", "wrap"; - }; - - cir: cir@10013000 { - compatible = "mediatek,mt7623-cir"; - reg = <0 0x10013000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IRRX>; - clock-names = "clk"; - status = "disabled"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt7623-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - efuse: efuse@10206000 { - compatible = "mediatek,mt7623-efuse", - "mediatek,mt8173-efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - thermal_calibration_data: calib@424 { - reg = <0x424 0xc>; - }; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt7623-apmixedsys", - "mediatek,mt2701-apmixedsys", - "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - rng: rng@1020f000 { - compatible = "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt7623-auxadc", - "mediatek,mt2701-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, - <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, - <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, - <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, - <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt7623-pwm"; - reg = <0 0x11006000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM>, - <&pericfg CLK_PERI_PWM1>, - <&pericfg CLK_PERI_PWM2>, - <&pericfg CLK_PERI_PWM3>, - <&pericfg CLK_PERI_PWM4>, - <&pericfg CLK_PERI_PWM5>; - clock-names = "top", "main", "pwm1", "pwm2", - "pwm3", "pwm4", "pwm5"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7623-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11007000 0 0x70>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt7623-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11008000 0 0x70>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt7623-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11009000 0 0x70>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7623-spi", - "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7623-thermal", - "mediatek,mt2701-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT2701_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration_data>; - nvmem-cell-names = "calibration-data"; - }; - - btif: serial@1100c000 { - compatible = "mediatek,mt7623-btif", - "mediatek,mtk-btif"; - reg = <0 0x1100c000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_BTIF>; - clock-names = "main"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - nandc: nfi@1100d000 { - compatible = "mediatek,mt7623-nfc", - "mediatek,mt2701-nfc"; - reg = <0 0x1100d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - clocks = <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names = "nfi_clk", "pad_clk"; - status = "disabled"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - }; - - bch: ecc@1100e000 { - compatible = "mediatek,mt7623-ecc", - "mediatek,mt2701-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_ECC>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - nor_flash: spi@11014000 { - compatible = "mediatek,mt7623-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0x1000>; - clocks = <&pericfg CLK_PERI_FLASH>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11016000 { - compatible = "mediatek,mt7623-spi", - "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI1_SEL>, - <&pericfg CLK_PERI_SPI1>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi2: spi@11017000 { - compatible = "mediatek,mt7623-spi", - "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11017000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI2_SEL>, - <&pericfg CLK_PERI_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - usb0: usb@11200000 { - compatible = "mediatek,mt7623-musb", - "mediatek,mtk-musb"; - reg = <0 0x11200000 0 0x1000>; - interrupts = ; - interrupt-names = "mc"; - phys = <&u2port2 PHY_TYPE_USB2>; - dr_mode = "otg"; - clocks = <&pericfg CLK_PERI_USB0>, - <&pericfg CLK_PERI_USB0_MCU>, - <&pericfg CLK_PERI_USB_SLV>; - clock-names = "main","mcu","univpll"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - status = "disabled"; - }; - - u2phy1: t-phy@11210000 { - compatible = "mediatek,mt7623-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x11210000 0 0x0800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port2: usb-phy@11210800 { - reg = <0 0x11210800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - }; - }; - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7623-audsys", - "mediatek,mt2701-audsys", - "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - compatible = "mediatek,mt7623-audio", - "mediatek,mt2701-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&audsys CLK_AUD_I2SO1>, - <&audsys CLK_AUD_I2SO2>, - <&audsys CLK_AUD_I2SO3>, - <&audsys CLK_AUD_I2SO4>, - <&audsys CLK_AUD_I2SIN1>, - <&audsys CLK_AUD_I2SIN2>, - <&audsys CLK_AUD_I2SIN3>, - <&audsys CLK_AUD_I2SIN4>, - <&audsys CLK_AUD_ASRCO1>, - <&audsys CLK_AUD_ASRCO2>, - <&audsys CLK_AUD_ASRCO3>, - <&audsys CLK_AUD_ASRCO4>, - <&audsys CLK_AUD_AFE>, - <&audsys CLK_AUD_AFE_CONN>, - <&audsys CLK_AUD_A1SYS>, - <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; - - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7623-mmc", - "mediatek,mt2701-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC30_0_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt7623-mmc", - "mediatek,mt2701-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1>, - <&topckgen CLK_TOP_MSDC30_1_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt7623-vdecsys", - "mediatek,mt2701-vdecsys", - "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7623-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names = "subsys", "port0", "port1", "port2"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys = <&pcie0_port PHY_TYPE_PCIE>, - <&pcie1_port PHY_TYPE_PCIE>, - <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range = <0x00 0xff>; - status = "disabled"; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - status = "disabled"; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - status = "disabled"; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - status = "disabled"; - }; - }; - - pcie0_phy: t-phy@1a149000 { - compatible = "mediatek,mt7623-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a149000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - pcie0_port: pcie-phy@1a149900 { - reg = <0 0x1a149900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - pcie1_phy: t-phy@1a14a000 { - compatible = "mediatek,mt7623-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a14a000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - pcie1_port: pcie-phy@1a14a900 { - reg = <0 0x1a14a900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb1: usb@1a1c0000 { - compatible = "mediatek,mt7623-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x1a1c0000 0 0x1000>, - <0 0x1a1c4700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB0PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy1: t-phy@1a1c4000 { - compatible = "mediatek,mt7623-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a1c4000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port0: usb-phy@1a1c4800 { - reg = <0 0x1a1c4800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@1a1c4900 { - reg = <0 0x1a1c4900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb2: usb@1a240000 { - compatible = "mediatek,mt7623-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x1a240000 0 0x1000>, - <0 0x1a244700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB1PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy2: t-phy@1a244000 { - compatible = "mediatek,mt7623-tphy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a244000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port1: usb-phy@1a244800 { - reg = <0 0x1a244800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port1: usb-phy@1a244900 { - reg = <0 0x1a244900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7623-ethsys", - "mediatek,mt2701-ethsys", - "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7623-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = ; - clocks = <ðsys CLK_ETHSYS_HSDMA>; - clock-names = "hsdma"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - #dma-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt7623-eth", - "mediatek,mt2701-eth", - "syscon"; - reg = <0 0x1b100000 0 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_ESW>, - <ðsys CLK_ETHSYS_GP1>, - <ðsys CLK_ETHSYS_GP2>, - <&apmixedsys CLK_APMIXED_TRGPLL>; - clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; - resets = <ðsys MT2701_ETHSYS_FE_RST>, - <ðsys MT2701_ETHSYS_GMAC_RST>, - <ðsys MT2701_ETHSYS_PPE_RST>; - reset-names = "fe", "gmac", "ppe"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - mediatek,ethsys = <ðsys>; - mediatek,pctl = <&syscfg_pctl_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - status = "disabled"; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - status = "disabled"; - }; - }; - - crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , - , - ; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - status = "disabled"; - }; - - bdpsys: syscon@1c000000 { - compatible = "mediatek,mt7623-bdpsys", - "mediatek,mt2701-bdpsys", - "syscon"; - reg = <0 0x1c000000 0 0x1000>; - #clock-cells = <1>; - }; -}; - -&pio { - cir_pins_a:cir-default { - pins-cir { - pinmux = ; - bias-disable; - }; - }; - - i2c0_pins_a: i2c0-default { - pins-i2c0 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1-default { - pin-i2c1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_b: i2c1-alt { - pin-i2c1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2-default { - pin-i2c2 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_b: i2c2-alt { - pin-i2c2 { - pinmux = , - ; - bias-disable; - }; - }; - - i2s0_pins_a: i2s0-default { - pin-i2s0 { - pinmux = , - , - , - , - ; - drive-strength = ; - bias-pull-down; - }; - }; - - i2s1_pins_a: i2s1-default { - pin-i2s1 { - pinmux = , - , - , - , - ; - drive-strength = ; - bias-pull-down; - }; - }; - - key_pins_a: keys-alt { - pins-keys { - pinmux = , - ; - input-enable; - }; - }; - - led_pins_a: leds-alt { - pins-leds { - pinmux = , - , - ; - }; - }; - - mmc0_pins_default: mmc0default { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up; - }; - - pins-clk { - pinmux = ; - bias-pull-down; - }; - - pins-rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc0_pins_uhs: mmc0 { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_default: mmc1default { - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - bias-pull-down; - drive-strength = ; - }; - - pins-wp { - pinmux = ; - input-enable; - bias-pull-up; - }; - - pins-insert { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_uhs: mmc1 { - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - - nand_pins_default: nanddefault { - pins-ale { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up; - }; - - pins-we { - pinmux = ; - drive-strength = ; - bias-pull-up = ; - }; - }; - - pcie_default: pcie_pin_default { - pins_cmd_dat { - pinmux = , - ; - bias-disable; - }; - }; - - pwm_pins_a: pwm-default { - pins-pwm { - pinmux = , - , - , - , - ; - }; - }; - - spi0_pins_a: spi0-default { - pins-spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi1_pins_a: spi1-default { - pins-spi { - pinmux = , - , - , - ; - }; - }; - - spi2_pins_a: spi2-default { - pins-spi { - pinmux = , - , - , - ; - }; - }; - - uart0_pins_a: uart0-default { - pins-dat { - pinmux = , - ; - }; - }; - - uart1_pins_a: uart1-default { - pins-dat { - pinmux = , - ; - }; - }; - - uart2_pins_a: uart2-default { - pins-dat { - pinmux = , - ; - }; - }; - - uart2_pins_b: uart2-alt { - pins-dat { - pinmux = , - ; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts deleted file mode 100644 index 5654284bab01..000000000000 --- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623a.dtsi" -#include "mt6323.dtsi" - -/ { - model = "MediaTek MT7623A with eMMC reference board"; - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - button-factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins_a>; - }; -}; - -&btif { - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -&switch0 { - ports { - port@0 { - status = "okay"; - label = "lan0"; - }; - - port@1 { - status = "okay"; - label = "lan1"; - }; - - port@2 { - status = "okay"; - label = "lan2"; - }; - - port@3 { - status = "okay"; - label = "lan3"; - }; - - port@4 { - status = "okay"; - label = "wan"; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_b>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts deleted file mode 100644 index afd177b3b516..000000000000 --- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623a.dtsi" -#include "mt6323.dtsi" - -/ { - model = "MediaTek MT7623A with NAND reference board"; - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - button-factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins_a>; - }; -}; - -&bch { - status = "okay"; -}; - -&btif { - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -&switch0 { - ports { - port@0 { - status = "okay"; - label = "lan0"; - }; - - port@1 { - status = "okay"; - label = "lan1"; - }; - - port@2 { - status = "okay"; - label = "lan2"; - }; - - port@3 { - status = "okay"; - label = "lan3"; - }; - - port@4 { - status = "okay"; - label = "wan"; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&nandc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_default>; - status = "okay"; - - nand@0 { - reg = <0>; - spare_per_sector = <64>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <12>; - nand-ecc-step-size = <1024>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "preloader"; - reg = <0x0 0x40000>; - }; - - partition@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - - partition@c0000 { - label = "uboot-env"; - reg = <0xC0000 0x40000>; - }; - - partition@140000 { - label = "bootimg"; - reg = <0x140000 0x2000000>; - }; - - partition@2140000 { - label = "recovery"; - reg = <0x2140000 0x2000000>; - }; - - partition@4140000 { - label = "rootfs"; - reg = <0x4140000 0x1000000>; - }; - - partition@5140000 { - label = "usrdata"; - reg = <0x5140000 0x1000000>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_b>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi deleted file mode 100644 index bcf909d58a1c..000000000000 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623.dtsi" - -&afe { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&crypto { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; -}; - -&gmac0 { - status = "okay"; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; - -ð { - status = "okay"; - power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch@1f { - compatible = "mediatek,mt7530"; - reg = <0x1f>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - status = "disabled"; - reg = <0>; - label = "swp0"; - }; - - port@1 { - status = "disabled"; - reg = <1>; - label = "swp1"; - }; - - port@2 { - status = "disabled"; - reg = <2>; - label = "swp2"; - }; - - port@3 { - status = "disabled"; - reg = <3>; - label = "swp3"; - }; - - port@4 { - status = "disabled"; - reg = <4>; - label = "swp4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; -}; - -&nandc { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&pcie { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; - -&scpsys { - compatible = "mediatek,mt7623a-scpsys"; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "ethif"; -}; - -&usb0 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; - -&usb2 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts deleted file mode 100644 index a37f3fa223c7..000000000000 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright 2017-2018 Sean Wang - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -#include -#include "mt7623n.dtsi" -#include "mt6323.dtsi" - -/ { - model = "Bananapi BPI-R2"; - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "d"; - ddc-i2c-bus = <&hdmiddc0>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vgpu: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_fixed_vgpu"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - button-factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - - blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - red { - label = "bpi-r2:pio:red"; - gpios = <&pio 239 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x80000000>; - }; -}; - -&bls { - status = "okay"; -}; - -&btif { - status = "okay"; -}; - -&cec { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&cir_pins_a>; - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -&dpi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dpi0_out: endpoint { - remote-endpoint = <&hdmi0_in>; - }; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; - -ð { - status = "okay"; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@1f { - compatible = "mediatek,mt7530"; - reg = <0x1f>; - reset-gpios = <&pio 33 0>; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - }; - - port@1 { - reg = <1>; - label = "lan0"; - }; - - port@2 { - reg = <2>; - label = "lan1"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; -}; - -&hdmi0 { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins_a>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@1 { - reg = <1>; - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; -}; - -&hdmiddc0 { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ddc_pins_a>; - status = "okay"; -}; - -&hdmi_phy { - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&mali { - mali-supply = <®_vgpu>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&mt6323keys { - home { - status = "disabled"; - }; -}; - -&mt6323_leds { - status = "okay"; - - led@0 { - reg = <0>; - label = "bpi-r2:isink:green"; - default-state = "off"; - }; - - led@1 { - reg = <1>; - label = "bpi-r2:isink:red"; - default-state = "off"; - }; - - led@2 { - reg = <2>; - label = "bpi-r2:isink:blue"; - default-state = "off"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pio { - musb_pins: musb { - pins-musb { - pinmux = ; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&musb_pins>; - status = "okay"; - usb-role-switch; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; - }; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usb2 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; - -&u3phy2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts deleted file mode 100644 index 34994f3f5a4b..000000000000 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ /dev/null @@ -1,398 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623n.dtsi" -#include "mt6323.dtsi" - -/ { - model = "MediaTek MT7623N with eMMC reference board"; - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "d"; - ddc-i2c-bus = <&hdmiddc0>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - button-factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins_a>; - }; -}; - -&bls { - status = "okay"; -}; - -&btif { - status = "okay"; -}; - -&cec { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&cir_pins_a>; - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -&dpi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dpi0_out: endpoint { - remote-endpoint = <&hdmi0_in>; - }; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy5>; -}; - -ð { - status = "okay"; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii-rxid"; - }; - - switch@1f { - compatible = "mediatek,mt7530"; - reg = <0x1f>; - reset-gpios = <&pio 33 0>; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; -}; - -&hdmi0 { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins_a>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@1 { - reg = <1>; - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; -}; - -&hdmiddc0 { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ddc_pins_a>; - status = "okay"; -}; - -&hdmi_phy { - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi deleted file mode 100644 index 3adab5cd1fef..000000000000 --- a/arch/arm/boot/dts/mt7623n.dtsi +++ /dev/null @@ -1,301 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright © 2017-2020 MediaTek Inc. - * Author: Sean Wang - * Ryder Lee - * - */ - -#include "mt7623.dtsi" -#include - -/ { - aliases { - rdma0 = &rdma0; - rdma1 = &rdma1; - }; - - g3dsys: syscon@13000000 { - compatible = "mediatek,mt7623-g3dsys", - "mediatek,mt2701-g3dsys", - "syscon"; - reg = <0 0x13000000 0 0x200>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mali: gpu@13040000 { - compatible = "mediatek,mt7623-mali", "arm,mali-450"; - reg = <0 0x13040000 0 0x30000>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", - "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", - "pp"; - clocks = <&topckgen CLK_TOP_MMPLL>, - <&g3dsys CLK_G3DSYS_CORE>; - clock-names = "bus", "core"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; - resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt7623-mmsys", - "mediatek,mt2701-mmsys", - "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb0: larb@14010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <1>; - clocks = <&vdecsys CLK_VDEC_CKGEN>, - <&vdecsys CLK_VDEC_LARB>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <2>; - clocks = <&imgsys CLK_IMG_SMI_COMM>, - <&imgsys CLK_IMG_SMI_COMM>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt7623-imgsys", - "mediatek,mt2701-imgsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - iommu: mmsys_iommu@10205000 { - compatible = "mediatek,mt7623-m4u", - "mediatek,mt2701-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2>; - #iommu-cells = <1>; - }; - - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt7623-jpgdec", - "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; - - smi_common: smi@1000c000 { - compatible = "mediatek,mt7623-smi-common", - "mediatek,mt2701-smi-common"; - reg = <0 0x1000c000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_SMI>, - <&mmsys CLK_MM_SMI_COMMON>, - <&infracfg CLK_INFRA_SMI>; - clock-names = "apb", "smi", "async"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - ovl: ovl@14007000 { - compatible = "mediatek,mt7623-disp-ovl", - "mediatek,mt2701-disp-ovl"; - reg = <0 0x14007000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DISP_OVL>; - iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; - }; - - rdma0: rdma@14008000 { - compatible = "mediatek,mt7623-disp-rdma", - "mediatek,mt2701-disp-rdma"; - reg = <0 0x14008000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DISP_RDMA>; - iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; - }; - - wdma@14009000 { - compatible = "mediatek,mt7623-disp-wdma", - "mediatek,mt2701-disp-wdma"; - reg = <0 0x14009000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DISP_WDMA>; - iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; - }; - - bls: pwm@1400a000 { - compatible = "mediatek,mt7623-disp-pwm", - "mediatek,mt2701-disp-pwm"; - reg = <0 0x1400a000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_MDP_BLS_26M>, - <&mmsys CLK_MM_DISP_BLS>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - color: color@1400b000 { - compatible = "mediatek,mt7623-disp-color", - "mediatek,mt2701-disp-color"; - reg = <0 0x1400b000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DISP_COLOR>; - }; - - dsi: dsi@1400c000 { - compatible = "mediatek,mt7623-dsi", - "mediatek,mt2701-dsi"; - reg = <0 0x1400c000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DSI_ENGINE>, - <&mmsys CLK_MM_DSI_DIG>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - phys = <&mipi_tx0>; - phy-names = "dphy"; - status = "disabled"; - }; - - mutex: mutex@1400e000 { - compatible = "mediatek,mt7623-disp-mutex", - "mediatek,mt2701-disp-mutex"; - reg = <0 0x1400e000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_MUTEX_32K>; - }; - - rdma1: rdma@14012000 { - compatible = "mediatek,mt7623-disp-rdma", - "mediatek,mt2701-disp-rdma"; - reg = <0 0x14012000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DISP_RDMA1>; - iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; - }; - - dpi0: dpi@14014000 { - compatible = "mediatek,mt7623-dpi", - "mediatek,mt2701-dpi"; - reg = <0 0x14014000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DPI1_DIGL>, - <&mmsys CLK_MM_DPI1_ENGINE>, - <&apmixedsys CLK_APMIXED_TVDPLL>; - clock-names = "pixel", "engine", "pll"; - status = "disabled"; - }; - - hdmi0: hdmi@14015000 { - compatible = "mediatek,mt7623-hdmi", - "mediatek,mt2701-hdmi"; - reg = <0 0x14015000 0 0x400>; - clocks = <&mmsys CLK_MM_HDMI_PIXEL>, - <&mmsys CLK_MM_HDMI_PLL>, - <&mmsys CLK_MM_HDMI_AUDIO>, - <&mmsys CLK_MM_HDMI_SPDIF>; - clock-names = "pixel", "pll", "bclk", "spdif"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - mediatek,syscon-hdmi = <&mmsys 0x900>; - cec = <&cec>; - status = "disabled"; - }; - - mipi_tx0: dsi-phy@10010000 { - compatible = "mediatek,mt7623-mipi-tx", - "mediatek,mt2701-mipi-tx"; - reg = <0 0x10010000 0 0x90>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - cec: cec@10012000 { - compatible = "mediatek,mt7623-cec", - "mediatek,mt8173-cec"; - reg = <0 0x10012000 0 0xbc>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CEC>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@10209100 { - compatible = "mediatek,mt7623-hdmi-phy", - "mediatek,mt2701-hdmi-phy"; - reg = <0 0x10209100 0 0x24>; - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; - clock-names = "pll_ref"; - clock-output-names = "hdmitx_dig_cts"; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - hdmiddc0: i2c@11013000 { - compatible = "mediatek,mt7623-hdmi-ddc", - "mediatek,mt8173-hdmi-ddc"; - interrupts = ; - reg = <0 0x11013000 0 0x1C>; - clocks = <&pericfg CLK_PERI_I2C3>; - clock-names = "ddc-i2c"; - status = "disabled"; - }; -}; - -&pio { - hdmi_pins_a: hdmi-default { - pins-hdmi { - pinmux = ; - input-enable; - bias-pull-down; - }; - }; - - hdmi_ddc_pins_a: hdmi_ddc-default { - pins-hdmi-ddc { - pinmux = , - ; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts deleted file mode 100644 index 84e14bee7235..000000000000 --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Ryder Lee - */ - -/dts-v1/; -#include -#include "mt7629.dtsi" - -/ { - model = "MediaTek MT7629 reference board"; - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-reset { - label = "factory"; - linux,code = ; - gpios = <&pio 60 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&pio 58 GPIO_ACTIVE_LOW>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - pinctrl-1 = <&ephy_leds_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000 0x60000>; - read-only; - }; - - partition@60000 { - label = "u-boot-env"; - reg = <0x60000 0x10000>; - read-only; - }; - - factory: partition@70000 { - label = "factory"; - reg = <0x70000 0x40000>; - read-only; - }; - - partition@b0000 { - label = "kernel"; - reg = <0xb0000 0xb50000>; - }; - }; - }; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pciephy1 { - status = "okay"; -}; - -&pio { - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio"; - }; - }; - - ephy_leds_pins: ephy-leds-pins { - mux { - function = "led"; - groups = "gphy_leds_0", "ephy_leds"; - }; - }; - - i2c_pins: i2c-pins { - mux { - function = "i2c"; - groups = "i2c_0"; - }; - - conf { - pins = "I2C_SDA", "I2C_SCL"; - drive-strength = <4>; - bias-disable; - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clkreq", - "pcie_pereset", - "pcie_wake"; - }; - }; - - pwm_pins: pwm-pins { - mux { - function = "pwm"; - groups = "pwm_0"; - }; - }; - - /* SPI-NOR is shared pin with serial NAND */ - qspi_pins: qspi-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spi_pins: spi-pins { - mux { - function = "spi"; - groups = "spi_0"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_txd_rxd" ; - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1_0_tx_rx" ; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_0_txd_rxd" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi deleted file mode 100644 index acab0883a3bb..000000000000 --- a/arch/arm/boot/dts/mt7629.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 MediaTek Inc. - * - * Author: Ryder Lee - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7629"; - interrupt-parent = <&sysirq>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt6589-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clock-frequency = <1250000000>; - cci-control-port = <&cci_control2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - clock-frequency = <1250000000>; - cci-control-port = <&cci_control2>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - clk20m: oscillator-0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - - clk40m: oscillator-1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <20000000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - infracfg: syscon@10000000 { - compatible = "mediatek,mt7629-infracfg", "syscon"; - reg = <0x10000000 0x1000>; - #clock-cells = <1>; - }; - - pericfg: syscon@10002000 { - compatible = "mediatek,mt7629-pericfg", "syscon"; - reg = <0x10002000 0x1000>; - #clock-cells = <1>; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt7629-scpsys", - "mediatek,mt7622-scpsys"; - #power-domain-cells = <1>; - reg = <0x10006000 0x1000>; - clocks = <&topckgen CLK_TOP_HIF_SEL>; - clock-names = "hif_sel"; - assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; - infracfg = <&infracfg>; - }; - - timer: timer@10009000 { - compatible = "mediatek,mt7629-timer", - "mediatek,mt6765-timer"; - reg = <0x10009000 0x60>; - interrupts = ; - clocks = <&clk20m>; - clock-names = "clk20m"; - }; - - sysirq: interrupt-controller@10200a80 { - compatible = "mediatek,mt7629-sysirq", - "mediatek,mt6577-sysirq"; - reg = <0x10200a80 0x20>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt7629-apmixedsys", "syscon"; - reg = <0x10209000 0x1000>; - #clock-cells = <1>; - }; - - rng: rng@1020f000 { - compatible = "mediatek,mt7629-rng", - "mediatek,mt7623-rng"; - reg = <0x1020f000 0x100>; - clocks = <&infracfg CLK_INFRA_TRNG_PD>; - clock-names = "rng"; - }; - - topckgen: syscon@10210000 { - compatible = "mediatek,mt7629-topckgen", "syscon"; - reg = <0x10210000 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@10212000 { - compatible = "mediatek,mt7629-wdt", - "mediatek,mt6589-wdt"; - reg = <0x10212000 0x100>; - }; - - pio: pinctrl@10217000 { - compatible = "mediatek,mt7629-pinctrl"; - reg = <0x10217000 0x8000>, - <0x10005000 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - gpio-ranges = <&pio 0 0 79>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10310000 0x1000>, - <0x10320000 0x1000>, - <0x10340000 0x2000>, - <0x10360000 0x2000>; - }; - - cci: cci@10390000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10390000 0x1000>; - ranges = <0 0x10390000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - ; - }; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7629-uart", - "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART0_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7629-uart", - "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7629-uart", - "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART2_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt7629-pwm"; - reg = <0x11006000 0x1000>; - #pwm-cells = <2>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM_PD>, - <&pericfg CLK_PERI_PWM1_PD>; - clock-names = "top", "main", "pwm1"; - assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; - assigned-clock-parents = - <&topckgen CLK_TOP_UNIVPLL2_D4>; - status = "disabled"; - }; - - i2c: i2c@11007000 { - compatible = "mediatek,mt7629-i2c", - "mediatek,mt2712-i2c"; - reg = <0x11007000 0x90>, - <0x11000100 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C0_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1100a000 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0_PD>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - qspi: spi@11014000 { - compatible = "mediatek,mt7629-nor", - "mediatek,mt8173-nor"; - reg = <0x11014000 0xe0>; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssusbsys: syscon@1a000000 { - compatible = "mediatek,mt7629-ssusbsys", "syscon"; - reg = <0x1a000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - ssusb: usb@1a0c0000 { - compatible = "mediatek,mt7629-xhci", - "mediatek,mtk-xhci"; - reg = <0x1a0c0000 0x01000>, - <0x1a0c3e00 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, - <&ssusbsys CLK_SSUSB_REF_EN>, - <&ssusbsys CLK_SSUSB_MCU_EN>, - <&ssusbsys CLK_SSUSB_DMA_EN>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; - assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, - <&topckgen CLK_TOP_SATA_SEL>, - <&topckgen CLK_TOP_HIF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, - <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_UNIVPLL1_D2>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy0: t-phy@1a0c4000 { - compatible = "mediatek,mt7629-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1a0c4000 0xe00>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0 0x700>; - clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x700>; - clocks = <&clk20m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - pciesys: syscon@1a100800 { - compatible = "mediatek,mt7629-pciesys", "syscon"; - reg = <0x1a100800 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pciecfg: pciecfg@1a140000 { - compatible = "mediatek,generic-pciecfg", "syscon"; - reg = <0x1a140000 0x1000>; - }; - - pcie1: pcie@1a145000 { - compatible = "mediatek,mt7629-pcie"; - device_type = "pci"; - reg = <0x1a145000 0x1000>; - reg-names = "port1"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck1", "ahb_ck1", - "aux_ck1", "axi_ck1", - "obff_ck1", "pipe_ck1"; - assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>, - <&topckgen CLK_TOP_AXI_SEL>, - <&topckgen CLK_TOP_HIF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SYSPLL1_D2>, - <&topckgen CLK_TOP_UNIVPLL1_D2>; - phys = <&pcieport1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy1"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pciephy1: t-phy@1a14a000 { - compatible = "mediatek,mt7629-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1a14a000 0x1000>; - status = "disabled"; - - pcieport1: pcie-phy@0 { - reg = <0 0x1000>; - clocks = <&clk20m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7629-ethsys", "syscon"; - reg = <0x1b000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt7629-eth","syscon"; - reg = <0x1b100000 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETH_SEL>, - <&topckgen CLK_TOP_F10M_REF_SEL>, - <ðsys CLK_ETH_ESW_EN>, - <ðsys CLK_ETH_GP0_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_FE_EN>, - <&sgmiisys0 CLK_SGMII_TX_EN>, - <&sgmiisys0 CLK_SGMII_RX_EN>, - <&sgmiisys0 CLK_SGMII_CDR_REF>, - <&sgmiisys0 CLK_SGMII_CDR_FB>, - <&sgmiisys1 CLK_SGMII_TX_EN>, - <&sgmiisys1 CLK_SGMII_RX_EN>, - <&sgmiisys1 CLK_SGMII_CDR_REF>, - <&sgmiisys1 CLK_SGMII_CDR_FB>, - <&apmixedsys CLK_APMIXED_SGMIPLL>, - <&apmixedsys CLK_APMIXED_ETH2PLL>; - clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", - "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "eth2pll"; - assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, - <&topckgen CLK_TOP_F10M_REF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_SGMIIPLL_D2>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&infracfg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sgmiisys0: syscon@1b128000 { - compatible = "mediatek,mt7629-sgmiisys", "syscon"; - reg = <0x1b128000 0x3000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@1b130000 { - compatible = "mediatek,mt7629-sgmiisys", "syscon"; - reg = <0x1b130000 0x3000>; - #clock-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts deleted file mode 100644 index 560687af87dc..000000000000 --- a/arch/arm/boot/dts/mt8127-moose.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -/dts-v1/; -#include "mt8127.dtsi" - -/ { - model = "MediaTek MT8127 Moose Board"; - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi deleted file mode 100644 index aced173c2a52..000000000000 --- a/arch/arm/boot/dts/mt8127.dtsi +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt8127"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - timer: timer@10008000 { - compatible = "mediatek,mt8127-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt8127-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts deleted file mode 100644 index f6147fe62f41..000000000000 --- a/arch/arm/boot/dts/mt8135-evbp1.dts +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -/dts-v1/; -#include "mt8135.dtsi" - -/ { - model = "MediaTek MT8135 evaluation board"; - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&pwrap { - pmic: mt6397 { - compatible = "mediatek,mt6397"; - - mt6397regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-name = "vpca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-name = "vpca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-name = "vsramca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-name = "vsramca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vcore_reg: buck_vcore { - regulator-name = "vcore"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-name = "vdrm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-name = "vio18"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-name = "vtcxo"; - regulator-always-on; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-name = "va28"; - regulator-always-on; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-name = "vio28"; - regulator-always-on; - }; - - mt6397_vusb_reg: ldo_vusb { - regulator-name = "vusb"; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-name = "vcamd"; - regulator-min-microvolt = <1220000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - regulator-name = "vcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-name = "vgp6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-name = "vibr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi deleted file mode 100644 index 0f291ad22d3a..000000000000 --- a/arch/arm/boot/dts/mt8135.dtsi +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt8135"; - interrupt-parent = <&sysirq>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x001>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - clk26m: clk26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt8135-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: infracfg@10001000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - }; - - pericfg: pericfg@10003000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - }; - - /* - * Pinctrl access register at 0x10005000 and 0x1020c000 through - * regmap. Register 0x1000b000 is used by EINT. - */ - pio: pinctrl@10005000 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8135-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = ; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - }; - - sysirq: interrupt-controller@10200030 { - compatible = "mediatek,mt8135-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200030 0 0x1c>; - }; - - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt8135-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - syscfg_pctl_b: syscfg_pctl_b@1020c000 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020c000 0 0x1000>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11006000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11007000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11008000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11009000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - }; -}; diff --git a/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi b/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi deleted file mode 100644 index e172029a0c4d..000000000000 --- a/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Device Tree common file for gpio-fan on Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpio-fan,speed-map = - <0 3 - 1500 2 - 3250 1 - 5000 0>; - }; -}; - -&pinctrl { - pmx_fan_low: pmx-fan-low { - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi b/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi deleted file mode 100644 index c2d87ba6190a..000000000000 --- a/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Device Tree common file for gpio-{keys,leds} on Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_switch>; - pinctrl-names = "default"; - - power-on-switch { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - }; - - power-auto-switch { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info>; - pinctrl-names = "default"; - - blue-power-led { - label = "linkstation:blue:power"; - default-state = "keep"; - }; - - red-alarm-led { - label = "linkstation:red:alarm"; - }; - - amber-info-led { - label = "linkstation:amber:info"; - }; - }; -}; - -&pinctrl { - pmx_power_switch: pmx-power-switch { - marvell,function = "gpio"; - }; - - pmx_led_power: pmx-leds { - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h deleted file mode 100644 index 31297abcbc71..000000000000 --- a/arch/arm/boot/dts/mxs-pinfunc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - */ - -#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ -#define __DT_BINDINGS_MXS_PINCTRL_H__ - -/* fsl,drive-strength property */ -#define MXS_DRIVE_4mA 0 -#define MXS_DRIVE_8mA 1 -#define MXS_DRIVE_12mA 2 -#define MXS_DRIVE_16mA 3 - -/* fsl,voltage property */ -#define MXS_VOLTAGE_LOW 0 -#define MXS_VOLTAGE_HIGH 1 - -/* fsl,pull-up property */ -#define MXS_PULL_DISABLE 0 -#define MXS_PULL_ENABLE 1 - -#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi deleted file mode 100644 index 01e1bb7c3c6c..000000000000 --- a/arch/arm/boot/dts/nspire-classic.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-classic.dts - * - * Copyright (C) 2013 Daniel Tang - */ - -/include/ "nspire.dtsi" - -&lcd { - port { - clcd_pads: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&fast_timer { - /* compatible = "lsi,zevio-timer"; */ - reg = <0x90010000 0x1000>, <0x900a0010 0x8>; -}; - -&uart { - compatible = "ns16550"; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb_pclk>; - no-loopback-test; -}; - -&timer0 { - /* compatible = "lsi,zevio-timer"; */ - reg = <0x900c0000 0x1000>, <0x900a0018 0x8>; -}; - -&timer1 { - compatible = "lsi,zevio-timer"; - reg = <0x900d0000 0x1000>, <0x900a0020 0x8>; -}; - -&keypad { - active-low; - -}; - -&base_clk { - compatible = "lsi,nspire-classic-clock"; -}; - -&ahb_clk { - compatible = "lsi,nspire-classic-ahb-divider"; -}; - - -&vbus_reg { - gpio = <&gpio 5 0>; -}; - -/ { - memory { - device_type = "memory"; - reg = <0x10000000 0x2000000>; /* 32 MB */ - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - - intc: interrupt-controller@dc000000 { - compatible = "lsi,zevio-intc"; - interrupt-controller; - reg = <0xdc000000 0x1000>; - #interrupt-cells = <1>; - }; - }; - - panel { - compatible = "ti,nspire-classic-lcd-panel"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - chosen { - bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; - }; -}; diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts deleted file mode 100644 index f52f38c61588..000000000000 --- a/arch/arm/boot/dts/nspire-clp.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-clp.dts - * - * Copyright (C) 2013 Daniel Tang - */ -/dts-v1/; - -/include/ "nspire-classic.dtsi" - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00020039 - 0x0004002c 0x00050034 0x00060015 - 0x0007000b 0x0008002d 0x01000033 - 0x0101004e 0x01020011 0x01030004 - 0x0104002f 0x01050003 0x01060016 - 0x01070002 0x01080014 0x02000062 - 0x0201000c 0x0202001f 0x02030007 - 0x02040013 0x02050006 0x02060010 - 0x02070005 0x02080019 0x03000027 - 0x03010037 0x03020018 0x0303000a - 0x03040031 0x03050009 0x03060032 - 0x03070008 0x03080026 0x04000028 - 0x04010035 0x04020025 0x04040024 - 0x04060017 0x04080023 0x05000028 - 0x05020022 0x0503001b 0x05040021 - 0x0505001a 0x05060012 0x0507006f - 0x05080020 0x0509002a 0x0601001c - 0x0602002e 0x06030068 0x06040030 - 0x0605006d 0x0606001e 0x06070001 - 0x0608002b 0x0609000f 0x07000067 - 0x0702006a 0x0704006c 0x07060069 - 0x0707000e 0x0708001d 0x070a000d - >; -}; - -/ { - model = "TI-NSPIRE Clickpad"; - compatible = "ti,nspire-clp"; -}; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts deleted file mode 100644 index 590b7dff6ae5..000000000000 --- a/arch/arm/boot/dts/nspire-cx.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-cx.dts - * - * Copyright (C) 2013 Daniel Tang - */ -/dts-v1/; - -/include/ "nspire.dtsi" - -&lcd { - port { - clcd_pads: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&fast_timer { - /* compatible = "arm,sp804", "arm,primecell"; */ -}; - -&uart { - compatible = "arm,pl011", "arm,primecell"; - - clocks = <&uart_clk>, <&apb_pclk>; - clock-names = "uart_clk", "apb_pclk"; -}; - -&timer0 { - compatible = "arm,sp804", "arm,primecell"; -}; - -&timer1 { - compatible = "arm,sp804", "arm,primecell"; -}; - -&base_clk { - compatible = "lsi,nspire-cx-clock"; -}; - -&ahb_clk { - compatible = "lsi,nspire-cx-ahb-divider"; -}; - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; - -&vbus_reg { - gpio = <&gpio 2 0>; -}; - -/ { - model = "TI-NSPIRE CX"; - compatible = "ti,nspire-cx"; - - memory { - device_type = "memory"; - reg = <0x10000000 0x4000000>; /* 64 MB */ - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - - intc: interrupt-controller@dc000000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xdc000000 0x1000>; - #interrupt-cells = <1>; - }; - - apb@90000000 { - #address-cells = <1>; - #size-cells = <1>; - - i2c@90050000 { - compatible = "snps,designware-i2c"; - reg = <0x90050000 0x1000>; - interrupts = <20>; - }; - }; - }; - - panel { - compatible = "ti,nspire-cx-lcd-panel"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - chosen { - bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; - }; -}; diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts deleted file mode 100644 index f7d0faacd4cc..000000000000 --- a/arch/arm/boot/dts/nspire-tp.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-tp.dts - * - * Copyright (C) 2013 Daniel Tang - */ -/dts-v1/; - -/include/ "nspire-classic.dtsi" - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; - -/ { - model = "TI-NSPIRE Touchpad"; - compatible = "ti,nspire-tp"; -}; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi deleted file mode 100644 index bb240e6a3a6f..000000000000 --- a/arch/arm/boot/dts/nspire.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire.dtsi - * - * Copyright (C) 2013 Daniel Tang - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - cpu@0 { - compatible = "arm,arm926ej-s"; - }; - }; - - bootrom: bootrom@0 { - reg = <0x00000000 0x80000>; - }; - - sram: sram@a4000000 { - device = "memory"; - reg = <0xa4000000 0x20000>; - }; - - timer_clk: timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - base_clk: base_clk { - #clock-cells = <0>; - reg = <0x900b0024 0x4>; - }; - - ahb_clk: ahb_clk { - #clock-cells = <0>; - reg = <0x900b0024 0x4>; - clocks = <&base_clk>; - }; - - apb_pclk: apb_pclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&ahb_clk>; - }; - - usb_phy: usb_phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - vbus_reg: vbus_reg { - compatible = "regulator-fixed"; - - regulator-name = "USB VBUS output"; - regulator-type = "voltage"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - spi: spi@a9000000 { - reg = <0xa9000000 0x1000>; - }; - - usb0: usb@b0000000 { - compatible = "lsi,zevio-usb"; - reg = <0xb0000000 0x1000>; - interrupts = <8>; - - usb-phy = <&usb_phy>; - vbus-supply = <&vbus_reg>; - }; - - usb1: usb@b4000000 { - reg = <0xb4000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - lcd: lcd@c0000000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0xc0000000 0x1000>; - interrupts = <21>; - - /* - * We assume the same clock is fed to APB and CLCDCLK. - * There is some code to scale the clock down by a factor - * 48 for the display so likely the frequency to the - * display is 1MHz and the CLCDCLK is 48 MHz. - */ - clocks = <&apb_pclk>, <&apb_pclk>; - clock-names = "clcdclk", "apb_pclk"; - }; - - adc: adc@c4000000 { - reg = <0xc4000000 0x1000>; - interrupts = <11>; - }; - - tdes: crypto@c8010000 { - reg = <0xc8010000 0x1000>; - }; - - sha256: crypto@cc000000 { - reg = <0xcc000000 0x1000>; - }; - - apb@90000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - clock-ranges; - ranges; - - gpio: gpio@90000000 { - compatible = "lsi,zevio-gpio"; - reg = <0x90000000 0x1000>; - interrupts = <7>; - gpio-controller; - #gpio-cells = <2>; - }; - - fast_timer: timer@90010000 { - reg = <0x90010000 0x1000>; - interrupts = <17>; - }; - - uart: serial@90020000 { - reg = <0x90020000 0x1000>; - interrupts = <1>; - }; - - timer0: timer@900c0000 { - reg = <0x900c0000 0x1000>; - clocks = <&timer_clk>, <&timer_clk>, - <&timer_clk>; - clock-names = "timer0clk", "timer1clk", - "apb_pclk"; - }; - - timer1: timer@900d0000 { - reg = <0x900d0000 0x1000>; - interrupts = <19>; - clocks = <&timer_clk>, <&timer_clk>, - <&timer_clk>; - clock-names = "timer0clk", "timer1clk", - "apb_pclk"; - }; - - watchdog: watchdog@90060000 { - compatible = "arm,amba-primecell"; - reg = <0x90060000 0x1000>; - interrupts = <3>; - }; - - rtc: rtc@90090000 { - reg = <0x90090000 0x1000>; - interrupts = <4>; - }; - - misc: misc@900a0000 { - reg = <0x900a0000 0x1000>; - }; - - pwr: pwr@900b0000 { - reg = <0x900b0000 0x1000>; - interrupts = <15>; - }; - - keypad: input@900e0000 { - compatible = "ti,nspire-keypad"; - reg = <0x900e0000 0x1000>; - interrupts = <16>; - - scan-interval = <1000>; - row-delay = <200>; - - clocks = <&apb_pclk>; - }; - - contrast: contrast@900f0000 { - reg = <0x900f0000 0x1000>; - }; - - led: led@90110000 { - reg = <0x90110000 0x1000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/nspire/Makefile b/arch/arm/boot/dts/nspire/Makefile new file mode 100644 index 000000000000..82a2515bdd46 --- /dev/null +++ b/arch/arm/boot/dts/nspire/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NSPIRE) += \ + nspire-cx.dtb \ + nspire-tp.dtb \ + nspire-clp.dtb diff --git a/arch/arm/boot/dts/nspire/nspire-classic.dtsi b/arch/arm/boot/dts/nspire/nspire-classic.dtsi new file mode 100644 index 000000000000..01e1bb7c3c6c --- /dev/null +++ b/arch/arm/boot/dts/nspire/nspire-classic.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/boot/nspire-classic.dts + * + * Copyright (C) 2013 Daniel Tang + */ + +/include/ "nspire.dtsi" + +&lcd { + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&fast_timer { + /* compatible = "lsi,zevio-timer"; */ + reg = <0x90010000 0x1000>, <0x900a0010 0x8>; +}; + +&uart { + compatible = "ns16550"; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb_pclk>; + no-loopback-test; +}; + +&timer0 { + /* compatible = "lsi,zevio-timer"; */ + reg = <0x900c0000 0x1000>, <0x900a0018 0x8>; +}; + +&timer1 { + compatible = "lsi,zevio-timer"; + reg = <0x900d0000 0x1000>, <0x900a0020 0x8>; +}; + +&keypad { + active-low; + +}; + +&base_clk { + compatible = "lsi,nspire-classic-clock"; +}; + +&ahb_clk { + compatible = "lsi,nspire-classic-ahb-divider"; +}; + + +&vbus_reg { + gpio = <&gpio 5 0>; +}; + +/ { + memory { + device_type = "memory"; + reg = <0x10000000 0x2000000>; /* 32 MB */ + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@dc000000 { + compatible = "lsi,zevio-intc"; + interrupt-controller; + reg = <0xdc000000 0x1000>; + #interrupt-cells = <1>; + }; + }; + + panel { + compatible = "ti,nspire-classic-lcd-panel"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + chosen { + bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire/nspire-clp.dts b/arch/arm/boot/dts/nspire/nspire-clp.dts new file mode 100644 index 000000000000..f52f38c61588 --- /dev/null +++ b/arch/arm/boot/dts/nspire/nspire-clp.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/boot/nspire-clp.dts + * + * Copyright (C) 2013 Daniel Tang + */ +/dts-v1/; + +/include/ "nspire-classic.dtsi" + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00020039 + 0x0004002c 0x00050034 0x00060015 + 0x0007000b 0x0008002d 0x01000033 + 0x0101004e 0x01020011 0x01030004 + 0x0104002f 0x01050003 0x01060016 + 0x01070002 0x01080014 0x02000062 + 0x0201000c 0x0202001f 0x02030007 + 0x02040013 0x02050006 0x02060010 + 0x02070005 0x02080019 0x03000027 + 0x03010037 0x03020018 0x0303000a + 0x03040031 0x03050009 0x03060032 + 0x03070008 0x03080026 0x04000028 + 0x04010035 0x04020025 0x04040024 + 0x04060017 0x04080023 0x05000028 + 0x05020022 0x0503001b 0x05040021 + 0x0505001a 0x05060012 0x0507006f + 0x05080020 0x0509002a 0x0601001c + 0x0602002e 0x06030068 0x06040030 + 0x0605006d 0x0606001e 0x06070001 + 0x0608002b 0x0609000f 0x07000067 + 0x0702006a 0x0704006c 0x07060069 + 0x0707000e 0x0708001d 0x070a000d + >; +}; + +/ { + model = "TI-NSPIRE Clickpad"; + compatible = "ti,nspire-clp"; +}; diff --git a/arch/arm/boot/dts/nspire/nspire-cx.dts b/arch/arm/boot/dts/nspire/nspire-cx.dts new file mode 100644 index 000000000000..590b7dff6ae5 --- /dev/null +++ b/arch/arm/boot/dts/nspire/nspire-cx.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/boot/nspire-cx.dts + * + * Copyright (C) 2013 Daniel Tang + */ +/dts-v1/; + +/include/ "nspire.dtsi" + +&lcd { + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&fast_timer { + /* compatible = "arm,sp804", "arm,primecell"; */ +}; + +&uart { + compatible = "arm,pl011", "arm,primecell"; + + clocks = <&uart_clk>, <&apb_pclk>; + clock-names = "uart_clk", "apb_pclk"; +}; + +&timer0 { + compatible = "arm,sp804", "arm,primecell"; +}; + +&timer1 { + compatible = "arm,sp804", "arm,primecell"; +}; + +&base_clk { + compatible = "lsi,nspire-cx-clock"; +}; + +&ahb_clk { + compatible = "lsi,nspire-cx-ahb-divider"; +}; + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00040039 + 0x0005002c 0x00060015 0x0007000b + 0x0008000f 0x0100002d 0x01010011 + 0x0102002f 0x01030004 0x01040016 + 0x01050014 0x0106001f 0x01070002 + 0x010a006a 0x02000013 0x02010010 + 0x02020019 0x02030007 0x02040018 + 0x02050031 0x02060032 0x02070005 + 0x02080028 0x0209006c 0x03000026 + 0x03010025 0x03020024 0x0303000a + 0x03040017 0x03050023 0x03060022 + 0x03070008 0x03080035 0x03090069 + 0x04000021 0x04010012 0x04020020 + 0x0404002e 0x04050030 0x0406001e + 0x0407000d 0x04080037 0x04090067 + 0x05010038 0x0502000c 0x0503001b + 0x05040034 0x0505001a 0x05060006 + 0x05080027 0x0509000e 0x050a006f + 0x0600002b 0x0602004e 0x06030068 + 0x06040003 0x0605006d 0x06060009 + 0x06070001 0x0609000f 0x0708002a + 0x0709001d 0x070a0033 >; +}; + +&vbus_reg { + gpio = <&gpio 2 0>; +}; + +/ { + model = "TI-NSPIRE CX"; + compatible = "ti,nspire-cx"; + + memory { + device_type = "memory"; + reg = <0x10000000 0x4000000>; /* 64 MB */ + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@dc000000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xdc000000 0x1000>; + #interrupt-cells = <1>; + }; + + apb@90000000 { + #address-cells = <1>; + #size-cells = <1>; + + i2c@90050000 { + compatible = "snps,designware-i2c"; + reg = <0x90050000 0x1000>; + interrupts = <20>; + }; + }; + }; + + panel { + compatible = "ti,nspire-cx-lcd-panel"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + chosen { + bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire/nspire-tp.dts b/arch/arm/boot/dts/nspire/nspire-tp.dts new file mode 100644 index 000000000000..f7d0faacd4cc --- /dev/null +++ b/arch/arm/boot/dts/nspire/nspire-tp.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/boot/nspire-tp.dts + * + * Copyright (C) 2013 Daniel Tang + */ +/dts-v1/; + +/include/ "nspire-classic.dtsi" + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00040039 + 0x0005002c 0x00060015 0x0007000b + 0x0008000f 0x0100002d 0x01010011 + 0x0102002f 0x01030004 0x01040016 + 0x01050014 0x0106001f 0x01070002 + 0x010a006a 0x02000013 0x02010010 + 0x02020019 0x02030007 0x02040018 + 0x02050031 0x02060032 0x02070005 + 0x02080028 0x0209006c 0x03000026 + 0x03010025 0x03020024 0x0303000a + 0x03040017 0x03050023 0x03060022 + 0x03070008 0x03080035 0x03090069 + 0x04000021 0x04010012 0x04020020 + 0x0404002e 0x04050030 0x0406001e + 0x0407000d 0x04080037 0x04090067 + 0x05010038 0x0502000c 0x0503001b + 0x05040034 0x0505001a 0x05060006 + 0x05080027 0x0509000e 0x050a006f + 0x0600002b 0x0602004e 0x06030068 + 0x06040003 0x0605006d 0x06060009 + 0x06070001 0x0609000f 0x0708002a + 0x0709001d 0x070a0033 >; +}; + +/ { + model = "TI-NSPIRE Touchpad"; + compatible = "ti,nspire-tp"; +}; diff --git a/arch/arm/boot/dts/nspire/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi new file mode 100644 index 000000000000..bb240e6a3a6f --- /dev/null +++ b/arch/arm/boot/dts/nspire/nspire.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/boot/nspire.dtsi + * + * Copyright (C) 2013 Daniel Tang + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + cpus { + cpu@0 { + compatible = "arm,arm926ej-s"; + }; + }; + + bootrom: bootrom@0 { + reg = <0x00000000 0x80000>; + }; + + sram: sram@a4000000 { + device = "memory"; + reg = <0xa4000000 0x20000>; + }; + + timer_clk: timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + base_clk: base_clk { + #clock-cells = <0>; + reg = <0x900b0024 0x4>; + }; + + ahb_clk: ahb_clk { + #clock-cells = <0>; + reg = <0x900b0024 0x4>; + clocks = <&base_clk>; + }; + + apb_pclk: apb_pclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&ahb_clk>; + }; + + usb_phy: usb_phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + vbus_reg: vbus_reg { + compatible = "regulator-fixed"; + + regulator-name = "USB VBUS output"; + regulator-type = "voltage"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spi: spi@a9000000 { + reg = <0xa9000000 0x1000>; + }; + + usb0: usb@b0000000 { + compatible = "lsi,zevio-usb"; + reg = <0xb0000000 0x1000>; + interrupts = <8>; + + usb-phy = <&usb_phy>; + vbus-supply = <&vbus_reg>; + }; + + usb1: usb@b4000000 { + reg = <0xb4000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + lcd: lcd@c0000000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0xc0000000 0x1000>; + interrupts = <21>; + + /* + * We assume the same clock is fed to APB and CLCDCLK. + * There is some code to scale the clock down by a factor + * 48 for the display so likely the frequency to the + * display is 1MHz and the CLCDCLK is 48 MHz. + */ + clocks = <&apb_pclk>, <&apb_pclk>; + clock-names = "clcdclk", "apb_pclk"; + }; + + adc: adc@c4000000 { + reg = <0xc4000000 0x1000>; + interrupts = <11>; + }; + + tdes: crypto@c8010000 { + reg = <0xc8010000 0x1000>; + }; + + sha256: crypto@cc000000 { + reg = <0xcc000000 0x1000>; + }; + + apb@90000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + clock-ranges; + ranges; + + gpio: gpio@90000000 { + compatible = "lsi,zevio-gpio"; + reg = <0x90000000 0x1000>; + interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; + }; + + fast_timer: timer@90010000 { + reg = <0x90010000 0x1000>; + interrupts = <17>; + }; + + uart: serial@90020000 { + reg = <0x90020000 0x1000>; + interrupts = <1>; + }; + + timer0: timer@900c0000 { + reg = <0x900c0000 0x1000>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; + }; + + timer1: timer@900d0000 { + reg = <0x900d0000 0x1000>; + interrupts = <19>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; + }; + + watchdog: watchdog@90060000 { + compatible = "arm,amba-primecell"; + reg = <0x90060000 0x1000>; + interrupts = <3>; + }; + + rtc: rtc@90090000 { + reg = <0x90090000 0x1000>; + interrupts = <4>; + }; + + misc: misc@900a0000 { + reg = <0x900a0000 0x1000>; + }; + + pwr: pwr@900b0000 { + reg = <0x900b0000 0x1000>; + interrupts = <15>; + }; + + keypad: input@900e0000 { + compatible = "ti,nspire-keypad"; + reg = <0x900e0000 0x1000>; + interrupts = <16>; + + scan-interval = <1000>; + row-delay = <200>; + + clocks = <&apb_pclk>; + }; + + contrast: contrast@900f0000 { + reg = <0x900f0000 0x1000>; + }; + + led: led@90110000 { + reg = <0x90110000 0x1000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi deleted file mode 100644 index c7b5ef15b716..000000000000 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ /dev/null @@ -1,1123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com -// Copyright 2018 Google, Inc. - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - /* external reference clock */ - clk_refclk: clk_refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "refclk"; - }; - - /* external reference clock for cpu. float in normal operation */ - clk_sysbypck: clk_sysbypck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "sysbypck"; - }; - - /* external reference clock for MC. float in normal operation */ - clk_mcbypck: clk_mcbypck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "mcbypck"; - }; - - /* external clock signal rg1refck, supplied by the phy */ - clk_rg1refck: clk_rg1refck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk_rg1refck"; - }; - - /* external clock signal rg2refck, supplied by the phy */ - clk_rg2refck: clk_rg2refck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk_rg2refck"; - }; - - clk_xin: clk_xin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "clk_xin"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0xf0000000 0x00900000>; - - scu: scu@3fe000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x3fe000 0x1000>; - }; - - l2: cache-controller@3fc000 { - compatible = "arm,pl310-cache"; - reg = <0x3fc000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - clocks = <&clk NPCM7XX_CLK_AXI>; - arm,shared-override; - }; - - gic: interrupt-controller@3ff000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x3ff000 0x1000>, - <0x3fe100 0x100>; - }; - - gcr: gcr@800000 { - compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; - reg = <0x800000 0x1000>; - }; - - rst: rst@801000 { - compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; - reg = <0x801000 0x6C>; - }; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - rstc: rstc@f0801000 { - compatible = "nuvoton,npcm750-reset"; - reg = <0xf0801000 0x70>; - #reset-cells = <2>; - nuvoton,sysgcr = <&gcr>; - }; - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm750-clk", "syscon"; - #clock-cells = <1>; - clock-controller; - reg = <0xf0801000 0x1000>; - clock-names = "refclk", "sysbypck", "mcbypck"; - clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; - }; - - gmac0: eth@f0802000 { - device_type = "network"; - compatible = "snps,dwmac"; - reg = <0xf0802000 0x2000>; - interrupts = ; - interrupt-names = "macirq"; - ethernet = <0>; - clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; - clock-names = "stmmaceth", "clk_gmac"; - pinctrl-names = "default"; - pinctrl-0 = <&rg1_pins - &rg1mdio_pins>; - status = "disabled"; - }; - - ehci1: usb@f0806000 { - compatible = "nuvoton,npcm750-ehci"; - reg = <0xf0806000 0x1000>; - interrupts = ; - status = "disabled"; - }; - - fiu0: spi@fb000000 { - compatible = "nuvoton,npcm750-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfb000000 0x1000>; - reg-names = "control", "memory"; - clocks = <&clk NPCM7XX_CLK_SPI0>; - clock-names = "clk_spi0"; - status = "disabled"; - }; - - fiu3: spi@c0000000 { - compatible = "nuvoton,npcm750-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc0000000 0x1000>; - reg-names = "control", "memory"; - clocks = <&clk NPCM7XX_CLK_SPI3>; - clock-names = "clk_spi3"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins>; - status = "disabled"; - }; - - fiux: spi@fb001000 { - compatible = "nuvoton,npcm750-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfb001000 0x1000>; - reg-names = "control", "memory"; - clocks = <&clk NPCM7XX_CLK_SPIX>; - clock-names = "clk_spix"; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0xf0000000 0x00300000>; - - lpc_kcs: lpc_kcs@7000 { - compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; - reg = <0x7000 0x40>; - reg-io-width = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x40>; - - kcs1: kcs1@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = ; - kcs_chan = <1>; - status = "disabled"; - }; - - kcs2: kcs2@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = ; - kcs_chan = <2>; - status = "disabled"; - }; - - kcs3: kcs3@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = ; - kcs_chan = <3>; - status = "disabled"; - }; - }; - - spi0: spi@200000 { - compatible = "nuvoton,npcm750-pspi"; - reg = <0x200000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pspi1_pins>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_APB5>; - clock-names = "clk_apb5"; - resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; - status = "disabled"; - }; - - spi1: spi@201000 { - compatible = "nuvoton,npcm750-pspi"; - reg = <0x201000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pspi2_pins>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_APB5>; - clock-names = "clk_apb5"; - resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; - status = "disabled"; - }; - - timer0: timer@8000 { - compatible = "nuvoton,npcm750-timer"; - interrupts = ; - reg = <0x8000 0x1C>; - clocks = <&clk NPCM7XX_CLK_TIMER>; - }; - - watchdog0: watchdog@801C { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0x801C 0x4>; - status = "disabled"; - clocks = <&clk NPCM7XX_CLK_TIMER>; - }; - - watchdog1: watchdog@901C { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0x901C 0x4>; - status = "disabled"; - clocks = <&clk NPCM7XX_CLK_TIMER>; - }; - - watchdog2: watchdog@a01C { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0xa01C 0x4>; - status = "disabled"; - clocks = <&clk NPCM7XX_CLK_TIMER>; - }; - - serial0: serial@1000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x1000 0x1000>; - clocks = <&clk NPCM7XX_CLK_UART>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - serial1: serial@2000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x2000 0x1000>; - clocks = <&clk NPCM7XX_CLK_UART>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - serial2: serial@3000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x3000 0x1000>; - clocks = <&clk NPCM7XX_CLK_UART>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - serial3: serial@4000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x4000 0x1000>; - clocks = <&clk NPCM7XX_CLK_UART>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - rng: rng@b000 { - compatible = "nuvoton,npcm750-rng"; - reg = <0xb000 0x8>; - status = "disabled"; - }; - - adc: adc@c000 { - compatible = "nuvoton,npcm750-adc"; - reg = <0xc000 0x8>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_ADC>; - resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; - status = "disabled"; - }; - - pwm_fan: pwm-fan-controller@103000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,npcm750-pwm-fan"; - reg = <0x103000 0x2000>, <0x180000 0x8000>; - reg-names = "pwm", "fan"; - clocks = <&clk NPCM7XX_CLK_APB3>, - <&clk NPCM7XX_CLK_APB4>; - clock-names = "pwm","fan"; - interrupts = , - , - , - , - , - , - , - ; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins &pwm1_pins - &pwm2_pins &pwm3_pins - &pwm4_pins &pwm5_pins - &pwm6_pins &pwm7_pins - &fanin0_pins &fanin1_pins - &fanin2_pins &fanin3_pins - &fanin4_pins &fanin5_pins - &fanin6_pins &fanin7_pins - &fanin8_pins &fanin9_pins - &fanin10_pins &fanin11_pins - &fanin12_pins &fanin13_pins - &fanin14_pins &fanin15_pins>; - status = "disabled"; - }; - - i2c0: i2c@80000 { - reg = <0x80000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb0_pins>; - status = "disabled"; - }; - - i2c1: i2c@81000 { - reg = <0x81000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb1_pins>; - status = "disabled"; - }; - - i2c2: i2c@82000 { - reg = <0x82000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb2_pins>; - status = "disabled"; - }; - - i2c3: i2c@83000 { - reg = <0x83000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb3_pins>; - status = "disabled"; - }; - - i2c4: i2c@84000 { - reg = <0x84000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb4_pins>; - status = "disabled"; - }; - - i2c5: i2c@85000 { - reg = <0x85000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb5_pins>; - status = "disabled"; - }; - - i2c6: i2c@86000 { - reg = <0x86000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb6_pins>; - status = "disabled"; - }; - - i2c7: i2c@87000 { - reg = <0x87000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb7_pins>; - status = "disabled"; - }; - - i2c8: i2c@88000 { - reg = <0x88000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb8_pins>; - status = "disabled"; - }; - - i2c9: i2c@89000 { - reg = <0x89000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb9_pins>; - status = "disabled"; - }; - - i2c10: i2c@8a000 { - reg = <0x8a000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb10_pins>; - status = "disabled"; - }; - - i2c11: i2c@8b000 { - reg = <0x8b000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb11_pins>; - status = "disabled"; - }; - - i2c12: i2c@8c000 { - reg = <0x8c000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb12_pins>; - status = "disabled"; - }; - - i2c13: i2c@8d000 { - reg = <0x8d000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb13_pins>; - status = "disabled"; - }; - - i2c14: i2c@8e000 { - reg = <0x8e000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb14_pins>; - status = "disabled"; - }; - - i2c15: i2c@8f000 { - reg = <0x8f000 0x1000>; - compatible = "nuvoton,npcm750-i2c"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk NPCM7XX_CLK_APB2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&smb15_pins>; - status = "disabled"; - }; - }; - }; - - pinctrl: pinctrl@f0800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; - ranges = <0 0xf0010000 0x8000>; - gpio0: gpio@f0010000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 0 32>; - }; - gpio1: gpio@f0011000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 32 32>; - }; - gpio2: gpio@f0012000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 64 32>; - }; - gpio3: gpio@f0013000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x3000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 96 32>; - }; - gpio4: gpio@f0014000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x4000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 128 32>; - }; - gpio5: gpio@f0015000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x5000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 160 32>; - }; - gpio6: gpio@f0016000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x6000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 192 32>; - }; - gpio7: gpio@f0017000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x7000 0x80>; - interrupts = ; - gpio-ranges = <&pinctrl 0 224 32>; - }; - - iox1_pins: iox1-pins { - groups = "iox1"; - function = "iox1"; - }; - iox2_pins: iox2-pins { - groups = "iox2"; - function = "iox2"; - }; - smb1d_pins: smb1d-pins { - groups = "smb1d"; - function = "smb1d"; - }; - smb2d_pins: smb2d-pins { - groups = "smb2d"; - function = "smb2d"; - }; - lkgpo1_pins: lkgpo1-pins { - groups = "lkgpo1"; - function = "lkgpo1"; - }; - lkgpo2_pins: lkgpo2-pins { - groups = "lkgpo2"; - function = "lkgpo2"; - }; - ioxh_pins: ioxh-pins { - groups = "ioxh"; - function = "ioxh"; - }; - gspi_pins: gspi-pins { - groups = "gspi"; - function = "gspi"; - }; - smb5b_pins: smb5b-pins { - groups = "smb5b"; - function = "smb5b"; - }; - smb5c_pins: smb5c-pins { - groups = "smb5c"; - function = "smb5c"; - }; - lkgpo0_pins: lkgpo0-pins { - groups = "lkgpo0"; - function = "lkgpo0"; - }; - pspi2_pins: pspi2-pins { - groups = "pspi2"; - function = "pspi2"; - }; - smb4den_pins: smb4den-pins { - groups = "smb4den"; - function = "smb4den"; - }; - smb4b_pins: smb4b-pins { - groups = "smb4b"; - function = "smb4b"; - }; - smb4c_pins: smb4c-pins { - groups = "smb4c"; - function = "smb4c"; - }; - smb15_pins: smb15-pins { - groups = "smb15"; - function = "smb15"; - }; - smb4d_pins: smb4d-pins { - groups = "smb4d"; - function = "smb4d"; - }; - smb14_pins: smb14-pins { - groups = "smb14"; - function = "smb14"; - }; - smb5_pins: smb5-pins { - groups = "smb5"; - function = "smb5"; - }; - smb4_pins: smb4-pins { - groups = "smb4"; - function = "smb4"; - }; - smb3_pins: smb3-pins { - groups = "smb3"; - function = "smb3"; - }; - spi0cs1_pins: spi0cs1-pins { - groups = "spi0cs1"; - function = "spi0cs1"; - }; - spi0cs2_pins: spi0cs2-pins { - groups = "spi0cs2"; - function = "spi0cs2"; - }; - spi0cs3_pins: spi0cs3-pins { - groups = "spi0cs3"; - function = "spi0cs3"; - }; - smb3c_pins: smb3c-pins { - groups = "smb3c"; - function = "smb3c"; - }; - smb3b_pins: smb3b-pins { - groups = "smb3b"; - function = "smb3b"; - }; - bmcuart0a_pins: bmcuart0a-pins { - groups = "bmcuart0a"; - function = "bmcuart0a"; - }; - uart1_pins: uart1-pins { - groups = "uart1"; - function = "uart1"; - }; - jtag2_pins: jtag2-pins { - groups = "jtag2"; - function = "jtag2"; - }; - bmcuart1_pins: bmcuart1-pins { - groups = "bmcuart1"; - function = "bmcuart1"; - }; - uart2_pins: uart2-pins { - groups = "uart2"; - function = "uart2"; - }; - bmcuart0b_pins: bmcuart0b-pins { - groups = "bmcuart0b"; - function = "bmcuart0b"; - }; - r1err_pins: r1err-pins { - groups = "r1err"; - function = "r1err"; - }; - r1md_pins: r1md-pins { - groups = "r1md"; - function = "r1md"; - }; - smb3d_pins: smb3d-pins { - groups = "smb3d"; - function = "smb3d"; - }; - fanin0_pins: fanin0-pins { - groups = "fanin0"; - function = "fanin0"; - }; - fanin1_pins: fanin1-pins { - groups = "fanin1"; - function = "fanin1"; - }; - fanin2_pins: fanin2-pins { - groups = "fanin2"; - function = "fanin2"; - }; - fanin3_pins: fanin3-pins { - groups = "fanin3"; - function = "fanin3"; - }; - fanin4_pins: fanin4-pins { - groups = "fanin4"; - function = "fanin4"; - }; - fanin5_pins: fanin5-pins { - groups = "fanin5"; - function = "fanin5"; - }; - fanin6_pins: fanin6-pins { - groups = "fanin6"; - function = "fanin6"; - }; - fanin7_pins: fanin7-pins { - groups = "fanin7"; - function = "fanin7"; - }; - fanin8_pins: fanin8-pins { - groups = "fanin8"; - function = "fanin8"; - }; - fanin9_pins: fanin9-pins { - groups = "fanin9"; - function = "fanin9"; - }; - fanin10_pins: fanin10-pins { - groups = "fanin10"; - function = "fanin10"; - }; - fanin11_pins: fanin11-pins { - groups = "fanin11"; - function = "fanin11"; - }; - fanin12_pins: fanin12-pins { - groups = "fanin12"; - function = "fanin12"; - }; - fanin13_pins: fanin13-pins { - groups = "fanin13"; - function = "fanin13"; - }; - fanin14_pins: fanin14-pins { - groups = "fanin14"; - function = "fanin14"; - }; - fanin15_pins: fanin15-pins { - groups = "fanin15"; - function = "fanin15"; - }; - pwm0_pins: pwm0-pins { - groups = "pwm0"; - function = "pwm0"; - }; - pwm1_pins: pwm1-pins { - groups = "pwm1"; - function = "pwm1"; - }; - pwm2_pins: pwm2-pins { - groups = "pwm2"; - function = "pwm2"; - }; - pwm3_pins: pwm3-pins { - groups = "pwm3"; - function = "pwm3"; - }; - r2_pins: r2-pins { - groups = "r2"; - function = "r2"; - }; - r2err_pins: r2err-pins { - groups = "r2err"; - function = "r2err"; - }; - r2md_pins: r2md-pins { - groups = "r2md"; - function = "r2md"; - }; - ga20kbc_pins: ga20kbc-pins { - groups = "ga20kbc"; - function = "ga20kbc"; - }; - smb5d_pins: smb5d-pins { - groups = "smb5d"; - function = "smb5d"; - }; - lpc_pins: lpc-pins { - groups = "lpc"; - function = "lpc"; - }; - espi_pins: espi-pins { - groups = "espi"; - function = "espi"; - }; - rg1_pins: rg1-pins { - groups = "rg1"; - function = "rg1"; - }; - rg1mdio_pins: rg1mdio-pins { - groups = "rg1mdio"; - function = "rg1mdio"; - }; - rg2_pins: rg2-pins { - groups = "rg2"; - function = "rg2"; - }; - ddr_pins: ddr-pins { - groups = "ddr"; - function = "ddr"; - }; - smb0_pins: smb0-pins { - groups = "smb0"; - function = "smb0"; - }; - smb1_pins: smb1-pins { - groups = "smb1"; - function = "smb1"; - }; - smb2_pins: smb2-pins { - groups = "smb2"; - function = "smb2"; - }; - smb2c_pins: smb2c-pins { - groups = "smb2c"; - function = "smb2c"; - }; - smb2b_pins: smb2b-pins { - groups = "smb2b"; - function = "smb2b"; - }; - smb1c_pins: smb1c-pins { - groups = "smb1c"; - function = "smb1c"; - }; - smb1b_pins: smb1b-pins { - groups = "smb1b"; - function = "smb1b"; - }; - smb8_pins: smb8-pins { - groups = "smb8"; - function = "smb8"; - }; - smb9_pins: smb9-pins { - groups = "smb9"; - function = "smb9"; - }; - smb10_pins: smb10-pins { - groups = "smb10"; - function = "smb10"; - }; - smb11_pins: smb11-pins { - groups = "smb11"; - function = "smb11"; - }; - sd1_pins: sd1-pins { - groups = "sd1"; - function = "sd1"; - }; - sd1pwr_pins: sd1pwr-pins { - groups = "sd1pwr"; - function = "sd1pwr"; - }; - pwm4_pins: pwm4-pins { - groups = "pwm4"; - function = "pwm4"; - }; - pwm5_pins: pwm5-pins { - groups = "pwm5"; - function = "pwm5"; - }; - pwm6_pins: pwm6-pins { - groups = "pwm6"; - function = "pwm6"; - }; - pwm7_pins: pwm7-pins { - groups = "pwm7"; - function = "pwm7"; - }; - mmc8_pins: mmc8-pins { - groups = "mmc8"; - function = "mmc8"; - }; - mmc_pins: mmc-pins { - groups = "mmc"; - function = "mmc"; - }; - mmcwp_pins: mmcwp-pins { - groups = "mmcwp"; - function = "mmcwp"; - }; - mmccd_pins: mmccd-pins { - groups = "mmccd"; - function = "mmccd"; - }; - mmcrst_pins: mmcrst-pins { - groups = "mmcrst"; - function = "mmcrst"; - }; - clkout_pins: clkout-pins { - groups = "clkout"; - function = "clkout"; - }; - serirq_pins: serirq-pins { - groups = "serirq"; - function = "serirq"; - }; - lpcclk_pins: lpcclk-pins { - groups = "lpcclk"; - function = "lpcclk"; - }; - scipme_pins: scipme-pins { - groups = "scipme"; - function = "scipme"; - }; - sci_pins: sci-pins { - groups = "sci"; - function = "sci"; - }; - smb6_pins: smb6-pins { - groups = "smb6"; - function = "smb6"; - }; - smb7_pins: smb7-pins { - groups = "smb7"; - function = "smb7"; - }; - pspi1_pins: pspi1-pins { - groups = "pspi1"; - function = "pspi1"; - }; - faninx_pins: faninx-pins { - groups = "faninx"; - function = "faninx"; - }; - r1_pins: r1-pins { - groups = "r1"; - function = "r1"; - }; - spi3_pins: spi3-pins { - groups = "spi3"; - function = "spi3"; - }; - spi3cs1_pins: spi3cs1-pins { - groups = "spi3cs1"; - function = "spi3cs1"; - }; - spi3quad_pins: spi3quad-pins { - groups = "spi3quad"; - function = "spi3quad"; - }; - spi3cs2_pins: spi3cs2-pins { - groups = "spi3cs2"; - function = "spi3cs2"; - }; - spi3cs3_pins: spi3cs3-pins { - groups = "spi3cs3"; - function = "spi3cs3"; - }; - nprd_smi_pins: nprd-smi-pins { - groups = "nprd_smi"; - function = "nprd_smi"; - }; - smb0b_pins: smb0b-pins { - groups = "smb0b"; - function = "smb0b"; - }; - smb0c_pins: smb0c-pins { - groups = "smb0c"; - function = "smb0c"; - }; - smb0den_pins: smb0den-pins { - groups = "smb0den"; - function = "smb0den"; - }; - smb0d_pins: smb0d-pins { - groups = "smb0d"; - function = "smb0d"; - }; - ddc_pins: ddc-pins { - groups = "ddc"; - function = "ddc"; - }; - rg2mdio_pins: rg2mdio-pins { - groups = "rg2mdio"; - function = "rg2mdio"; - }; - wdog1_pins: wdog1-pins { - groups = "wdog1"; - function = "wdog1"; - }; - wdog2_pins: wdog2-pins { - groups = "wdog2"; - function = "wdog2"; - }; - smb12_pins: smb12-pins { - groups = "smb12"; - function = "smb12"; - }; - smb13_pins: smb13-pins { - groups = "smb13"; - function = "smb13"; - }; - spix_pins: spix-pins { - groups = "spix"; - function = "spix"; - }; - spixcs1_pins: spixcs1-pins { - groups = "spixcs1"; - function = "spixcs1"; - }; - clkreq_pins: clkreq-pins { - groups = "clkreq"; - function = "clkreq"; - }; - hgpio0_pins: hgpio0-pins { - groups = "hgpio0"; - function = "hgpio0"; - }; - hgpio1_pins: hgpio1-pins { - groups = "hgpio1"; - function = "hgpio1"; - }; - hgpio2_pins: hgpio2-pins { - groups = "hgpio2"; - function = "hgpio2"; - }; - hgpio3_pins: hgpio3-pins { - groups = "hgpio3"; - function = "hgpio3"; - }; - hgpio4_pins: hgpio4-pins { - groups = "hgpio4"; - function = "hgpio4"; - }; - hgpio5_pins: hgpio5-pins { - groups = "hgpio5"; - function = "hgpio5"; - }; - hgpio6_pins: hgpio6-pins { - groups = "hgpio6"; - function = "hgpio6"; - }; - hgpio7_pins: hgpio7-pins { - groups = "hgpio7"; - function = "hgpio7"; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts deleted file mode 100644 index 9e9eba8bad5e..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts +++ /dev/null @@ -1,1135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 Quanta Computer Inc. George.Hung@quantatw.com - -/dts-v1/; -#include "nuvoton-npcm730.dtsi" -#include - -/ { - model = "Quanta GBS Board (Device Tree)"; - compatible = "quanta,gbs-bmc","nuvoton,npcm730"; - - aliases { - ethernet1 = &gmac0; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - i2c16 = &i2c0_slotPE0_0; - i2c17 = &i2c0_slotPE1_1; - i2c18 = &i2c0_slotUSB_2; - i2c19 = &i2c0_3; - i2c20 = &i2c5_i2cool_0; - i2c21 = &i2c5_i2cool_1; - i2c22 = &i2c5_i2cool_2; - i2c23 = &i2c5_hsbp_fru_3; - i2c24 = &i2c6_u2_15_0; - i2c25 = &i2c6_u2_14_1; - i2c26 = &i2c6_u2_13_2; - i2c27 = &i2c6_u2_12_3; - i2c28 = &i2c7_u2_11_0; - i2c29 = &i2c7_u2_10_1; - i2c30 = &i2c7_u2_9_2; - i2c31 = &i2c7_u2_8_3; - i2c32 = &i2c9_vddcr_cpu; - i2c33 = &i2c9_vddcr_soc; - i2c34 = &i2c9_vddio_efgh; - i2c35 = &i2c9_vddio_abcd; - i2c36 = &i2c10_u2_7_0; - i2c37 = &i2c10_u2_6_1; - i2c38 = &i2c10_u2_5_2; - i2c39 = &i2c10_u2_4_3; - i2c40 = &i2c11_clk_buf0_0; - i2c41 = &i2c11_clk_buf1_1; - i2c42 = &i2c11_clk_buf2_2; - i2c43 = &i2c11_clk_buf3_3; - i2c44 = &i2c14_u2_3_0; - i2c45 = &i2c14_u2_2_1; - i2c46 = &i2c14_u2_1_2; - i2c47 = &i2c14_u2_0_3; - fiu0 = &fiu0; - fiu1 = &fiu3; - }; - - chosen { - stdout-path = &serial0; - }; - - memory { - reg = <0 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - sas-cable0 { - label = "sas-cable0"; - gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - linux,code = <73>; - }; - - sas-cable1 { - label = "sas-cable1"; - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - linux,code = <72>; - }; - - sas-cable2 { - label = "sas-cable2"; - gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - linux,code = <71>; - }; - - sas-cable3 { - label = "sas-cable3"; - gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - linux,code = <70>; - }; - - sata0 { - label = "sata0"; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - hsbp-cable { - label = "hsbp-cable"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - linux,code = <57>; - }; - - fanbd-cable { - label = "fanbd-cable"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,code = <58>; - }; - - bp12v-cable { - label = "bp12v-cable"; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - linux,code = <69>; - }; - - pe-slot0 { - label = "pe-slot0"; - gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - linux,code = <120>; - }; - - pe-slot1 { - label = "pe-slot1"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - linux,code = <121>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 1>, <&adc 2>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 0>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { /* gpio153 */ - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - attention { /* gpio215 */ - gpios = <&gpio6 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - sys_boot_status { /* gpio216 */ - gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - retain-state-shutdown; - }; - - bmc_fault { /* gpio217 */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "panic"; - panic-indicator; - }; - - led_u2_0_locate { - gpios = <&pca9535_ledlocate 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_1_locate { - gpios = <&pca9535_ledlocate 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_2_locate { - gpios = <&pca9535_ledlocate 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_3_locate { - gpios = <&pca9535_ledlocate 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_4_locate { - gpios = <&pca9535_ledlocate 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_5_locate { - gpios = <&pca9535_ledlocate 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_6_locate { - gpios = <&pca9535_ledlocate 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_7_locate { - gpios = <&pca9535_ledlocate 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_8_locate { - gpios = <&pca9535_ledlocate 11 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_9_locate { - gpios = <&pca9535_ledlocate 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_10_locate { - gpios = <&pca9535_ledlocate 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_11_locate { - gpios = <&pca9535_ledlocate 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_12_locate { - gpios = <&pca9535_ledlocate 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_13_locate { - gpios = <&pca9535_ledlocate 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_14_locate { - gpios = <&pca9535_ledlocate 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_15_locate { - gpios = <&pca9535_ledlocate 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_0_fault { - gpios = <&pca9535_ledfault 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_1_fault { - gpios = <&pca9535_ledfault 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_2_fault { - gpios = <&pca9535_ledfault 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_3_fault { - gpios = <&pca9535_ledfault 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_4_fault { - gpios = <&pca9535_ledfault 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_5_fault { - gpios = <&pca9535_ledfault 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_6_fault { - gpios = <&pca9535_ledfault 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_7_fault { - gpios = <&pca9535_ledfault 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_8_fault { - gpios = <&pca9535_ledfault 11 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_9_fault { - gpios = <&pca9535_ledfault 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_10_fault { - gpios = <&pca9535_ledfault 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_11_fault { - gpios = <&pca9535_ledfault 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_12_fault { - gpios = <&pca9535_ledfault 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_13_fault { - gpios = <&pca9535_ledfault 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_14_fault { - gpios = <&pca9535_ledfault 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_u2_15_fault { - gpios = <&pca9535_ledfault 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - }; - - seven-seg-disp { - compatible = "seven-seg-gpio-dev"; - refresh-interval-ms = /bits/ 16 <600>; - clock-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - data-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - clear-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - }; - - pcie-slot { - pcie1: pcie-slot@1 { - label = "PE0"; - }; - pcie2: pcie-slot@2 { - label = "PE1"; - }; - }; -}; - -&fiu0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0cs1_pins>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <2>; - label = "bmc"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - u-boot@0 { - label = "u-boot"; - reg = <0x0000000 0xf0000>; - }; - image-descriptor@f0000 { - label = "image-descriptor"; - reg = <0xf0000 0x10000>; - }; - hoth-update@100000 { - label = "hoth-update"; - reg = <0x100000 0x100000>; - }; - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; - }; - rofs@700000 { - label = "rofs"; - reg = <0x700000 0x35f0000>; - }; - rwfs@3cf0000 { - label = "rwfs"; - reg = <0x3cf0000 0x300000>; - }; - hoth-mailbox@3ff0000 { - label = "hoth-mailbox"; - reg = <0x3ff0000 0x10000>; - }; - }; - }; -}; - -&fiu3 { - pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - m25p,fast-read; - label = "pnor"; - }; - flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; - m25p,fast-read; - }; -}; - -&gcr { - serial_port_mux: uart-mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x38 0x07>; - idle-states = <2>; /* Serial port mode 3 (takeover) */ - }; - - uart1_mode_mux: uart1-mode-mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x64 0x01000000>; - idle-states = <0>; /* Set UART1 mode to normal (follow SPMOD) */ - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii-id"; - snps,eee-force-disable; -}; - -&ehci1 { - status = "okay"; -}; - -&watchdog1 { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&adc { - #io-channel-cells = <1>; - status = "okay"; -}; - -&lpc_kcs { - kcs1: kcs1@0 { - status = "okay"; - }; - - kcs2: kcs2@0 { - status = "okay"; - }; - - kcs3: kcs3@0 { - status = "okay"; - }; -}; - -&spi1 { - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* dummy - gpio147 */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio224ol_pins &gpio227o_pins - &gpio228_pins>; - status = "okay"; - - jtag_master@0 { - compatible = "nuvoton,npcm750-jtag-master"; - spi-max-frequency = <25000000>; - reg = <0>; - status = "okay"; - - pinctrl-names = "pspi", "gpio"; - pinctrl-0 = <&pspi2_pins>; - pinctrl-1 = <&gpio224ol_pins &gpio227o_pins - &gpio228_pins>; - - tck-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - tdi-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - tdo-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - tms-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - - i2c0_slotPE0_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - pcie-slot = &pcie1; - }; - - i2c0_slotPE1_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - pcie-slot = &pcie2; - }; - - i2c0_slotUSB_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c0_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; - - pca9535_ifdet: pca9535-ifdet@24 { - compatible = "nxp,pca9535"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9535_pwren: pca9535-pwren@20 { - compatible = "nxp,pca9535"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "pwr_u2_3_en","pwr_u2_2_en", - "pwr_u2_1_en","pwr_u2_0_en", - "pwr_u2_7_en","pwr_u2_6_en", - "pwr_u2_5_en","pwr_u2_4_en", - "pwr_u2_11_en","pwr_u2_10_en", - "pwr_u2_9_en","pwr_u2_8_en", - "pwr_u2_15_en","pwr_u2_14_en", - "pwr_u2_13_en","pwr_u2_12_en"; - }; - - pca9535_pwrgd: pca9535-pwrgd@21 { - compatible = "nxp,pca9535"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9535_ledlocate: pca9535-ledlocate@22 { - compatible = "nxp,pca9535"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - }; - - pca9535_ledfault: pca9535-ledfault@23 { - compatible = "nxp,pca9535"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - - }; - - pca9535_pwrdisable: pca9535-pwrdisable@25 { - compatible = "nxp,pca9535"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "u2_3_pwr_dis","u2_2_pwr_dis", - "u2_1_pwr_dis","u2_0_pwr_dis", - "u2_7_pwr_dis","u2_6_pwr_dis", - "u2_5_pwr_dis","u2_4_pwr_dis", - "u2_11_pwr_dis","u2_10_pwr_dis", - "u2_9_pwr_dis","u2_8_pwr_dis", - "u2_15_pwr_dis","u2_14_pwr_dis", - "u2_13_pwr_dis","u2_12_pwr_dis"; - }; - - pca9535_perst: pca9535-perst@26 { - compatible = "nxp,pca9535"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "u2_15_perst","u2_14_perst", - "u2_13_perst","u2_12_perst", - "u2_11_perst","u2_10_perst", - "u2_9_perst","u2_8_perst", - "u2_7_perst","u2_6_perst", - "u2_5_perst","u2_4_perst", - "u2_3_perst","u2_2_perst", - "u2_1_perst","u2_0_perst"; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - status = "okay"; - - sbtsi@4c { - compatible = "amd,sbtsi"; - reg = <0x4c>; - }; -}; - -&i2c5 { - clock-frequency = <100000>; - status = "okay"; - - mb_fru@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - i2c5_i2cool_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - max31725@54 { - compatible = "maxim,max31725"; - reg = <0x54>; - status = "okay"; - }; - }; - - i2c5_i2cool_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - max31725@55 { - compatible = "maxim,max31725"; - reg = <0x55>; - status = "okay"; - }; - }; - - i2c5_i2cool_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - max31725@5d { - compatible = "maxim,max31725"; - reg = <0x5d>; - status = "okay"; - }; - fan_fru@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - - i2c5_hsbp_fru_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - hsbp_fru@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - status = "okay"; - }; - }; - }; -}; - -&i2c6 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@73 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - i2c-mux-idle-disconnect; - - i2c6_u2_15_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c6_u2_14_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2c6_u2_13_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c6_u2_12_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c7 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@72 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - i2c-mux-idle-disconnect; - - i2c7_u2_11_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c7_u2_10_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2c7_u2_9_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c7_u2_8_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c8 { - clock-frequency = <100000>; - status = "okay"; - - i2c8_adm1272: adm1272@10 { - compatible = "adi,adm1272"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10>; - shunt-resistor-micro-ohms = <300>; - }; -}; - -&i2c9 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - - i2c9_vddcr_cpu: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - vrm@60 { - compatible = "isil,isl68137"; - reg = <0x60>; - }; - }; - - i2c9_vddcr_soc: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - vrm@61 { - compatible = "isil,isl68137"; - reg = <0x61>; - }; - }; - - i2c9_vddio_efgh: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - vrm@63 { - compatible = "isil,isl68137"; - reg = <0x63>; - }; - }; - - i2c9_vddio_abcd: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - vrm@45 { - compatible = "isil,isl68137"; - reg = <0x45>; - }; - }; - }; -}; - -&i2c10 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - i2c10_u2_7_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c10_u2_6_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2c10_u2_5_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c10_u2_4_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c11 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@76 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - i2c11_clk_buf0_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c11_clk_buf1_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2c11_clk_buf2_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c11_clk_buf3_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c12 { - clock-frequency = <100000>; - status = "okay"; - - max34451@4e { - compatible = "maxim,max34451"; - reg = <0x4e>; - }; - vrm@5d { - compatible = "isil,isl68137"; - reg = <0x5d>; - }; - vrm@5e { - compatible = "isil,isl68137"; - reg = <0x5e>; - }; -}; - -&i2c13 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c14 { - clock-frequency = <100000>; - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - i2c14_u2_3_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c14_u2_2_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c14_u2_1_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c14_u2_0_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&pwm_fan { - pinctrl-names = "default"; - pinctrl-0 = < - &pwm0_pins &pwm1_pins - &pwm2_pins &pwm3_pins - &pwm4_pins - &fanin0_pins &fanin1_pins - &fanin2_pins &fanin3_pins - &fanin4_pins - >; - status = "okay"; - - fan@0 { - reg = <0x00>; - fan-tach-ch = /bits/ 8 <0x00>; - }; - fan@1 { - reg = <0x01>; - fan-tach-ch = /bits/ 8 <0x01>; - }; - fan@2 { - reg = <0x02>; - fan-tach-ch = /bits/ 8 <0x02>; - }; - fan@3 { - reg = <0x04>; - fan-tach-ch = /bits/ 8 <0x04>; - }; - fan@4 { - reg = <0x03>; - fan-tach-ch = /bits/ 8 <0x03>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - - gpio0: gpio@f0010000 { - /* POWER_OUT=gpio07, RESET_OUT=gpio06, PS_PWROK=gpio13 */ - gpio-line-names = - /*0-31*/ - "","","","","","","RESET_OUT","POWER_OUT", - "","","","","","PS_PWROK","","", - "","","","","","","","", - "","","","","","","",""; - }; - gpio1: gpio@f0011000 { - /* SIO_POWER_GOOD=gpio59 */ - gpio-line-names = - /*32-63*/ - "","","","","","","","", - "","","","","","","","", - "","","","","","","","", - "","","","SIO_POWER_GOOD","","","",""; - }; - gpio2: gpio@f0012000 { - bmc_usb_mux_oe_n { - gpio-hog; - gpios = <25 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "bmc-usb-mux-oe-n"; - }; - bmc_usb_mux_sel { - gpio-hog; - gpios = <26 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "bmc-usb-mux-sel"; - }; - bmc_usb2517_reset_n { - gpio-hog; - gpios = <27 GPIO_ACTIVE_LOW>; - output-low; - line-name = "bmc-usb2517-reset-n"; - }; - }; - gpio3: gpio@f0013000 { - assert_cpu0_reset { - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "assert-cpu0-reset"; - }; - assert_pwrok_cpu0_n { - gpio-hog; - gpios = <15 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "assert-pwrok-cpu0-n"; - }; - assert_cpu0_prochot { - gpio-hog; - gpios = <16 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "assert-cpu0-prochot"; - }; - }; - gpio4: gpio@f0014000 { - /* POST_COMPLETE=gpio143 */ - gpio-line-names = - /*128-159*/ - "","","","","","","","", - "","","","","","","","POST_COMPLETE", - "","","","","","","","", - "","","","","","","",""; - }; - gpio5: gpio@f0015000 { - /* POWER_BUTTON=gpio177 */ - gpio-line-names = - /*160-191*/ - "","","","","","","","", - "","","","","","","","", - "","POWER_BUTTON","","","","","","", - "","","","","","","",""; - }; - gpio6: gpio@f0016000 { - /* SIO_S5=gpio199, RESET_BUTTON=gpio203 */ - gpio-line-names = - /*192-223*/ - "","","","","","","","SIO_S5", - "","","","RESET_BUTTON","","","","", - "","","","","","","","", - "","","","","","","",""; - }; - - gpio224ol_pins: gpio224ol-pins { - pins = "GPIO224/SPIXCK"; - bias-disable; - output-low; - }; - gpio227o_pins: gpio227o-pins { - pins = "GPIO227/nSPIXCS0"; - bias-disable; - output-high; - }; - gpio228_pins: gpio228-pins { - pins = "GPIO228/nSPIXCS1"; - bias-disable; - input-enable; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi deleted file mode 100644 index 53cfd15fa03f..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi +++ /dev/null @@ -1,477 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com - -/ { - pinctrl: pinctrl@f0800000 { - gpio0pp_pins: gpio0pp-pins { - pins = "GPIO0/IOX1DI"; - bias-disable; - drive-push-pull; - }; - gpio1pp_pins: gpio1pp-pins { - pins = "GPIO1/IOX1LD"; - bias-disable; - drive-push-pull; - }; - gpio2pp_pins: gpio2pp-pins { - pins = "GPIO2/IOX1CK"; - bias-disable; - drive-push-pull; - }; - gpio3pp_pins: gpio3pp-pins { - pins = "GPIO3/IOX1D0"; - bias-disable; - drive-push-pull; - }; - gpio4pp_pins: gpio4pp-pins { - pins = "GPIO4/IOX2DI/SMB1DSDA"; - bias-disable; - drive-push-pull; - }; - gpio5pp_pins: gpio5pp-pins { - pins = "GPIO5/IOX2LD/SMB1DSCL"; - bias-disable; - drive-push-pull; - }; - gpio6pp_pins: gpio6pp-pins { - pins = "GPIO6/IOX2CK/SMB2DSDA"; - bias-disable; - drive-push-pull; - }; - gpio7pp_pins: gpio7pp-pins { - pins = "GPIO7/IOX2D0/SMB2DSCL"; - bias-disable; - drive-push-pull; - }; - gpio8_pins: gpio8-pins { - pins = "GPIO8/LKGPO1"; - bias-disable; - input-enable; - }; - gpio9_pins: gpio9-pins { - pins = "GPIO9/LKGPO2"; - bias-disable; - input-enable; - }; - gpio10pp_pins: gpio10pp-pins { - pins = "GPIO10/IOXHLD"; - bias-disable; - drive-push-pull; - }; - gpio11pp_pins: gpio11pp-pins { - pins = "GPIO11/IOXHCK"; - bias-disable; - drive-push-pull; - }; - gpio12_pins: gpio12-pins { - pins = "GPIO12/GSPICK/SMB5BSCL"; - bias-disable; - input-enable; - }; - gpio13_pins: gpio13-pins { - pins = "GPIO13/GSPIDO/SMB5BSDA"; - bias-disable; - input-enable; - }; - gpio14_pins: gpio14-pins { - pins = "GPIO14/GSPIDI/SMB5CSCL"; - bias-disable; - input-enable; - }; - gpio15od_pins: gpio15od-pins { - pins = "GPIO15/GSPICS/SMB5CSDA"; - bias-disable; - drive-open-drain; - }; - gpio17pp_pins: gpio17pp-pins { - pins = "GPIO17/PSPI2DI/SMB4DEN"; - bias-disable; - drive-push-pull; - }; - gpio18pp_pins: gpio18pp-pins { - pins = "GPIO18/PSPI2D0/SMB4BSDA"; - bias-disable; - drive-push-pull; - }; - gpio19pp_pins: gpio19pp-pins { - pins = "GPIO19/PSPI2CK/SMB4BSCL"; - bias-disable; - drive-push-pull; - }; - gpio24pp_pins: gpio24pp-pins { - pins = "GPIO24/IOXHDO"; - bias-disable; - drive-push-pull; - }; - gpio25pp_pins: gpio25pp-pins { - pins = "GPIO25/IOXHDI"; - bias-disable; - drive-push-pull; - }; - gpio37od_pins: gpio37od-pins { - pins = "GPIO37/SMB3CSDA"; - bias-disable; - drive-open-drain; - }; - gpio59pp_pins: gpio59pp-pins { - pins = "GPIO59/SMB3DSDA"; - bias-disable; - drive-push-pull; - }; - gpio60_pins: gpio60-pins { - pins = "GPIO60/SMB3DSCL"; - bias-disable; - input-enable; - }; - gpio72od_pins: gpio72od-pins { - pins = "GPIO72/FANIN8"; - bias-disable; - drive-open-drain; - }; - gpio73od_pins: gpio73od-pins { - pins = "GPIO73/FANIN9"; - bias-disable; - drive-open-drain; - }; - gpio74od_pins: gpio74od-pins { - pins = "GPIO74/FANIN10"; - bias-disable; - drive-open-drain; - }; - gpio75od_pins: gpio75od-pins { - pins = "GPIO75/FANIN11"; - bias-disable; - drive-open-drain; - }; - gpio76od_pins: gpio76od-pins { - pins = "GPIO76/FANIN12"; - bias-disable; - drive-open-drain; - }; - gpio77od_pins: gpio77od-pins { - pins = "GPIO77/FANIN13"; - bias-disable; - drive-open-drain; - }; - gpio78od_pins: gpio78od-pins { - pins = "GPIO78/FANIN14"; - bias-disable; - drive-open-drain; - }; - gpio79od_pins: gpio79od-pins { - pins = "GPIO79/FANIN15"; - bias-disable; - drive-open-drain; - }; - gpio83_pins: gpio83-pins { - pins = "GPIO83/PWM3"; - bias-disable; - input-enable; - }; - gpio84pp_pins: gpio84pp-pins { - pins = "GPIO84/R2TXD0"; - bias-disable; - drive-push-pull; - }; - gpio85pp_pins: gpio85pp-pins { - pins = "GPIO85/R2TXD1"; - bias-disable; - drive-push-pull; - }; - gpio86pp_pins: gpio86pp-pins { - pins = "GPIO86/R2TXEN"; - bias-disable; - drive-push-pull; - }; - gpio87pp_pins: gpio87pp-pins { - pins = "GPIO87/R2RXD0"; - bias-disable; - drive-push-pull; - }; - gpio88pp_pins: gpio88pp-pins { - pins = "GPIO88/R2RXD1"; - bias-disable; - drive-push-pull; - }; - gpio89pp_pins: gpio89pp-pins { - pins = "GPIO89/R2CRSDV"; - bias-disable; - drive-push-pull; - }; - gpio90pp_pins: gpio90pp-pins { - pins = "GPIO90/R2RXERR"; - bias-disable; - drive-push-pull; - }; - gpio91_pins: gpio91-pins { - pins = "GPIO91/R2MDC"; - bias-disable; - input-enable; - }; - gpio92_pins: gpio92-pins { - pins = "GPIO92/R2MDIO"; - bias-disable; - input-enable; - }; - gpio93pp_pins: gpio93pp-pins { - pins = "GPIO93/GA20/SMB5DSCL"; - bias-disable; - drive-push-pull; - }; - gpio94pp_pins: gpio94pp-pins { - pins = "GPIO94/nKBRST/SMB5DSDA"; - bias-disable; - drive-push-pull; - }; - gpio95_pins: gpio95-pins { - pins = "GPIO95/nLRESET/nESPIRST"; - bias-disable; - input-enable; - }; - gpio125pp_pins: gpio125pp-pins { - pins = "GPIO125/SMB1CSCL"; - bias-disable; - drive-push-pull; - }; - gpio126od_pins: gpio126od-pins { - pins = "GPIO126/SMB1BSDA"; - bias-disable; - drive-open-drain; - }; - gpio127od_pins: gpio127od-pins { - pins = "GPIO127/SMB1BSCL"; - bias-disable; - drive-open-drain; - }; - gpio136_pins: gpio136-pins { - pins = "GPIO136/SD1DT0"; - bias-disable; - input-enable; - }; - gpio137_pins: gpio137-pins { - pins = "GPIO137/SD1DT1"; - bias-disable; - input-enable; - }; - gpio141_pins: gpio141-pins { - pins = "GPIO141/SD1WP"; - bias-disable; - input-enable; - }; - gpio142od_pins: gpio142od-pins { - pins = "GPIO142/SD1CMD"; - bias-disable; - drive-open-drain; - }; - gpio143ol_pins: gpio143ol-pins { - pins = "GPIO143/SD1CD/SD1PWR"; - bias-disable; - output-low; - }; - gpio144_pins: gpio144-pins { - pins = "GPIO144/PWM4"; - bias-disable; - input-enable; - }; - gpio145_pins: gpio145-pins { - pins = "GPIO145/PWM5"; - bias-disable; - input-enable; - }; - gpio146_pins: gpio146-pins { - pins = "GPIO146/PWM6"; - bias-disable; - input-enable; - }; - gpio147_pins: gpio147-pins { - pins = "GPIO147/PWM7"; - bias-disable; - input-enable; - }; - gpio148_pins: gpio148-pins { - pins = "GPIO148/MMCDT4"; - bias-disable; - input-enable; - }; - gpio149_pins: gpio149-pins { - pins = "GPIO149/MMCDT5"; - bias-disable; - input-enable; - }; - gpio150_pins: gpio150-pins { - pins = "GPIO150/MMCDT6"; - bias-disable; - input-enable; - }; - gpio151_pins: gpio151-pins { - pins = "GPIO151/MMCDT7"; - bias-disable; - input-enable; - }; - gpio152_pins: gpio152-pins { - pins = "GPIO152/MMCCLK"; - bias-disable; - input-enable; - }; - gpio153_pins: gpio153-pins { - pins = "GPIO153/MMCWP"; - bias-disable; - input-enable; - }; - gpio154_pins: gpio154-pins { - pins = "GPIO154/MMCCMD"; - bias-disable; - input-enable; - }; - gpio155_pins: gpio155-pins { - pins = "GPIO155/nMMCCD/nMMCRST"; - bias-disable; - input-enable; - }; - gpio156_pins: gpio156-pins { - pins = "GPIO156/MMCDT0"; - bias-disable; - input-enable; - }; - gpio157_pins: gpio157-pins { - pins = "GPIO157/MMCDT1"; - bias-disable; - input-enable; - }; - gpio158_pins: gpio158-pins { - pins = "GPIO158/MMCDT2"; - bias-disable; - input-enable; - }; - gpio159_pins: gpio159-pins { - pins = "GPIO159/MMCDT3"; - bias-disable; - input-enable; - }; - gpio161_pins: gpio161-pins { - pins = "GPIO161/nLFRAME/nESPICS"; - bias-disable; - input-enable; - }; - gpio162_pins: gpio162-pins { - pins = "GPIO162/SERIRQ"; - bias-disable; - input-enable; - }; - gpio163_pins: gpio163-pins { - pins = "GPIO163/LCLK/ESPICLK"; - bias-disable; - input-enable; - }; - gpio164_pins: gpio164-pins { - pins = "GPIO164/LAD0/ESPI_IO0"; - bias-disable; - input-enable; - }; - gpio165_pins: gpio165-pins { - pins = "GPIO165/LAD1/ESPI_IO1"; - bias-disable; - input-enable; - }; - gpio166_pins: gpio166-pins { - pins = "GPIO166/LAD2/ESPI_IO2"; - bias-disable; - input-enable; - }; - gpio167_pins: gpio167-pins { - pins = "GPIO167/LAD3/ESPI_IO3"; - bias-disable; - input-enable; - }; - gpio168_pins: gpio168-pins { - pins = "GPIO168/nCLKRUN/nESPIALERT"; - bias-disable; - input-enable; - }; - gpio169_pins: gpio169-pins { - pins = "GPIO169/nSCIPME"; - bias-disable; - input-enable; - }; - gpio170_pins: gpio170-pins { - pins = "GPIO170/nSMI"; - bias-disable; - input-enable; - }; - gpio175od_pins: gpio175od-pins { - pins = "GPIO175/PSPI1CK/FANIN19"; - bias-disable; - drive-open-drain; - }; - gpio176od_pins: gpio176od-pins { - pins = "GPIO176/PSPI1DO/FANIN18"; - bias-disable; - drive-open-drain; - }; - gpio177_pins: gpio177-pins { - pins = "GPIO177/PSPI1DI/FANIN17"; - bias-disable; - input-enable; - }; - gpio190od_pins: gpio190od-pins { - pins = "GPIO190/nPRD_SMI"; - bias-disable; - drive-open-drain; - }; - gpio191_pins: gpio191-pins { - pins = "GPIO191"; - bias-disable; - input-enable; - }; - gpio192_pins: gpio192-pins { - pins = "GPIO192"; - bias-disable; - input-enable; - }; - gpio194pp_pins: gpio194pp-pins { - pins = "GPIO194/SMB0BSCL"; - bias-disable; - drive-push-pull; - }; - gpio195od_pins: gpio195od-pins { - pins = "GPIO195/SMB0BSDA"; - bias-disable; - drive-open-drain; - }; - gpio196od_pins: gpio196od-pins { - pins = "GPIO196/SMB0CSCL"; - bias-disable; - drive-open-drain; - }; - gpio197od_pins: gpio197od-pins { - pins = "GPIO197/SMB0DEN"; - bias-disable; - drive-open-drain; - }; - gpio198od_pins: gpio198od-pins { - pins = "GPIO198/SMB0DSDA"; - bias-disable; - drive-open-drain; - }; - gpio199od_pins: gpio199od-pins { - pins = "GPIO199/SMB0DSCL"; - bias-disable; - drive-open-drain; - }; - gpio200pp_pins: gpio200pp-pins { - pins = "GPIO200/R2CK"; - bias-disable; - drive-push-pull; - }; - gpio202od_pins: gpio202od-pins { - pins = "GPIO202/SMB0CSDA"; - bias-disable; - drive-open-drain; - }; - gpio203_pins: gpio203-pins { - pins = "GPIO203/FANIN16"; - bias-disable; - input-enable; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts deleted file mode 100644 index 2a394cc15284..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts +++ /dev/null @@ -1,490 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com - -/dts-v1/; -#include "nuvoton-npcm730.dtsi" -#include "nuvoton-npcm730-gsj-gpio.dtsi" - -#include - -/ { - model = "Quanta GSJ Board (Device Tree v12)"; - compatible = "nuvoton,npcm750"; - - aliases { - ethernet1 = &gmac0; - serial3 = &serial3; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c15 = &i2c15; - fiu0 = &fiu0; - }; - - chosen { - stdout-path = &serial3; - }; - - memory { - reg = <0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-bmc-live { - gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - LED_U2_0_LOCATE { - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_1_LOCATE { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_2_LOCATE { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_3_LOCATE { - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_4_LOCATE { - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_5_LOCATE { - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_BMC_TRAY_PWRGD { - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_7_FAULT { - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_6_LOCATE { - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_7_LOCATE { - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_0_FAULT { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_1_FAULT { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_2_FAULT { - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_3_FAULT { - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_4_FAULT { - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_5_FAULT { - gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - LED_U2_6_FAULT { - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&fiu0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0cs1_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-rx-bus-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - bmc@0{ - label = "bmc"; - reg = <0x000000 0x2000000>; - }; - u-boot@0 { - label = "u-boot"; - reg = <0x0000000 0x80000>; - read-only; - }; - u-boot-env@100000{ - label = "u-boot-env"; - reg = <0x00100000 0x40000>; - }; - kernel@200000 { - label = "kernel"; - reg = <0x0200000 0x600000>; - }; - rofs@800000 { - label = "rofs"; - reg = <0x800000 0x1400000>; - }; - rwfs@1c00000 { - label = "rwfs"; - reg = <0x1c00000 0x300000>; - }; - reserved@1f00000 { - label = "reserved"; - reg = <0x1f00000 0x100000>; - }; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&watchdog1 { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - lm75@5c { - compatible = "maxim,max31725"; - reg = <0x5c>; - status = "okay"; - }; -}; - -&i2c2 { - status = "okay"; - - lm75@5c { - compatible = "maxim,max31725"; - reg = <0x5c>; - status = "okay"; - }; -}; - -&i2c3 { - status = "okay"; - - lm75@5c { - compatible = "maxim,max31725"; - reg = <0x5c>; - }; -}; - -&i2c4 { - status = "okay"; - - lm75@5c { - compatible = "maxim,max31725"; - reg = <0x5c>; - }; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; - - eeprom@55 { - compatible = "atmel,24c64"; - reg = <0x55>; - }; -}; - -&i2c10 { - status = "okay"; - - eeprom@55 { - compatible = "atmel,24c64"; - reg = <0x55>; - }; -}; - -&i2c11 { - status = "okay"; - - /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ - power-brick@36 { - compatible = "delta,dps800"; - reg = <0x36>; - }; - - hotswap@15 { - compatible = "ti,lm5066i"; - reg = <0x15>; - }; -}; - -&i2c12 { - status = "okay"; - - ucd90160@6b { - compatible = "ti,ucd90160"; - reg = <0x6b>; - }; -}; - -&i2c15 { - status = "okay"; - - i2c-switch@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - i2c_u20: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_u21: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_u22: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_u23: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c_u24: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c_u25: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c_u26: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c_u27: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&pwm_fan { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins - &fanin0_pins &fanin1_pins - &fanin2_pins &fanin3_pins - &fanin4_pins &fanin5_pins>; - status = "okay"; - - fan@0 { - reg = <0x00>; - fan-tach-ch = /bits/ 8 <0x00 0x01>; - cooling-levels = <127 255>; - }; - - fan@1 { - reg = <0x01>; - fan-tach-ch = /bits/ 8 <0x02 0x03>; - cooling-levels = /bits/ 8 <127 255>; - }; - - fan@2 { - reg = <0x02>; - fan-tach-ch = /bits/ 8 <0x04 0x05>; - cooling-levels = /bits/ 8 <127 255>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - /* GPI pins*/ - &gpio8_pins - &gpio9_pins - &gpio12_pins - &gpio13_pins - &gpio14_pins - &gpio60_pins - &gpio83_pins - &gpio91_pins - &gpio92_pins - &gpio95_pins - &gpio136_pins - &gpio137_pins - &gpio141_pins - &gpio144_pins - &gpio145_pins - &gpio146_pins - &gpio147_pins - &gpio148_pins - &gpio149_pins - &gpio150_pins - &gpio151_pins - &gpio152_pins - &gpio153_pins - &gpio154_pins - &gpio155_pins - &gpio156_pins - &gpio157_pins - &gpio158_pins - &gpio159_pins - &gpio161_pins - &gpio162_pins - &gpio163_pins - &gpio164_pins - &gpio165_pins - &gpio166_pins - &gpio167_pins - &gpio168_pins - &gpio169_pins - &gpio170_pins - &gpio177_pins - &gpio191_pins - &gpio192_pins - &gpio203_pins - /* GPO pins*/ - &gpio0pp_pins - &gpio1pp_pins - &gpio2pp_pins - &gpio3pp_pins - &gpio4pp_pins - &gpio5pp_pins - &gpio6pp_pins - &gpio7pp_pins - &gpio10pp_pins - &gpio11pp_pins - &gpio15od_pins - &gpio17pp_pins - &gpio18pp_pins - &gpio19pp_pins - &gpio24pp_pins - &gpio25pp_pins - &gpio37od_pins - &gpio59pp_pins - &gpio72od_pins - &gpio73od_pins - &gpio74od_pins - &gpio75od_pins - &gpio76od_pins - &gpio77od_pins - &gpio78od_pins - &gpio79od_pins - &gpio84pp_pins - &gpio85pp_pins - &gpio86pp_pins - &gpio87pp_pins - &gpio88pp_pins - &gpio89pp_pins - &gpio90pp_pins - &gpio93pp_pins - &gpio94pp_pins - &gpio125pp_pins - &gpio126od_pins - &gpio127od_pins - &gpio142od_pins - &gpio143ol_pins - &gpio175od_pins - &gpio176od_pins - &gpio190od_pins - &gpio194pp_pins - &gpio195od_pins - &gpio196od_pins - &gpio197od_pins - &gpio198od_pins - &gpio199od_pins - &gpio200pp_pins - &gpio202od_pins - >; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts deleted file mode 100644 index f7b38bee039b..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts +++ /dev/null @@ -1,826 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 Fii USA Inc. - -/dts-v1/; -#include "nuvoton-npcm730.dtsi" - -#include - -/ { - model = "Fii Kudo Board"; - compatible = "fii,kudo", "nuvoton,npcm730"; - - aliases { - ethernet1 = &gmac0; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - spi0 = &spi0; - spi1 = &spi1; - fiu0 = &fiu0; - fiu1 = &fiu3; - }; - - chosen { - stdout-path = &serial3; - }; - - memory { - reg = <0 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; - - jtag_master { - compatible = "nuvoton,npcm750-jtag-master"; - #address-cells = <1>; - #size-cells = <1>; - - // dev/jtag0 - dev-num = <0>; - // pspi or gpio - mode = "pspi"; - - // pspi2 - pspi-controller = <2>; - reg = <0xf0201000 0x1000>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_APB5>; - - // TCK, TDI, TDO, TMS - jtag-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>, - <&gpio0 18 GPIO_ACTIVE_HIGH>, - <&gpio0 17 GPIO_ACTIVE_HIGH>, - <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - heartbeat { - label = "heartbeat"; - gpios = <&gpio0 14 1>; - }; - }; - - pinctrl: pinctrl@f0800000 { - gpio61oh_pins: gpio61oh-pins { - pins = "GPO61/nDTR1_BOUT1/STRAP6"; - bias-disable; - output-high; - }; - gpio62oh_pins: gpio62oh-pins { - pins = "GPO62/nRTST1/STRAP5"; - bias-disable; - output-high; - }; - gpio161ol_pins: gpio161ol-pins { - pins = "GPIO161/nLFRAME/nESPICS"; - bias-disable; - output-low; - }; - gpio163i_pins: gpio163i-pins { - pins = "GPIO163/LCLK/ESPICLK"; - bias-disable; - input-enable; - }; - gpio167ol_pins: gpio167ol-pins { - pins = "GPIO167/LAD3/ESPI_IO3"; - bias-disable; - output-low; - }; - gpio95i_pins: gpio95i-pins { - pins = "GPIO95/nLRESET/nESPIRST"; - bias-disable; - input-enable; - }; - gpio65ol_pins: gpio65ol-pins { - pins = "GPIO65/FANIN1"; - bias-disable; - output-low; - }; - gpio66oh_pins: gpio66oh-pins { - pins = "GPIO66/FANIN2"; - bias-disable; - output-high; - }; - gpio67oh_pins: gpio67oh-pins { - pins = "GPIO67/FANIN3"; - bias-disable; - output-high; - }; - gpio68ol_pins: gpio68ol-pins { - pins = "GPIO68/FANIN4"; - bias-disable; - output-low; - }; - gpio69i_pins: gpio69i-pins { - pins = "GPIO69/FANIN5"; - bias-disable; - input-enable; - }; - gpio70ol_pins: gpio70ol-pins { - pins = "GPIO70/FANIN6"; - bias-disable; - output-low; - }; - gpio71i_pins: gpio71i-pins { - pins = "GPIO71/FANIN7"; - bias-disable; - input-enable; - }; - gpio72i_pins: gpio72i-pins { - pins = "GPIO72/FANIN8"; - bias-disable; - input-enable; - }; - gpio73i_pins: gpio73i-pins { - pins = "GPIO73/FANIN9"; - bias-disable; - input-enable; - }; - gpio74i_pins: gpio74i-pins { - pins = "GPIO74/FANIN10"; - bias-disable; - input-enable; - }; - gpio75i_pins: gpio75i-pins { - pins = "GPIO75/FANIN11"; - bias-disable; - input-enable; - }; - gpio76i_pins: gpio76i-pins { - pins = "GPIO76/FANIN12"; - bias-disable; - input-enable; - }; - gpio77i_pins: gpio77i-pins { - pins = "GPIO77/FANIN13"; - bias-disable; - input-enable; - }; - gpio78i_pins: gpio78i-pins { - pins = "GPIO78/FANIN14"; - bias-disable; - input-enable; - }; - gpio79ol_pins: gpio79ol-pins { - pins = "GPIO79/FANIN15"; - bias-disable; - output-low; - }; - gpio80oh_pins: gpio80oh-pins { - pins = "GPIO80/PWM0"; - bias-disable; - output-high; - }; - gpio81i_pins: gpio81i-pins { - pins = "GPIO81/PWM1"; - bias-disable; - input-enable; - }; - gpio82i_pins: gpio82i-pins { - pins = "GPIO82/PWM2"; - bias-disable; - input-enable; - }; - gpio83i_pins: gpio83i-pins { - pins = "GPIO83/PWM3"; - bias-disable; - input-enable; - }; - gpio144i_pins: gpio144i-pins { - pins = "GPIO144/PWM4"; - bias-disable; - input-enable; - }; - gpio145i_pins: gpio145i-pins { - pins = "GPIO145/PWM5"; - bias-disable; - input-enable; - }; - gpio146i_pins: gpio146i-pins { - pins = "GPIO146/PWM6"; - bias-disable; - input-enable; - }; - gpio147oh_pins: gpio147oh-pins { - pins = "GPIO147/PWM7"; - bias-disable; - output-high; - }; - gpio168ol_pins: gpio168ol-pins { - pins = "GPIO168/nCLKRUN/nESPIALERT"; - bias-disable; - output-low; - }; - gpio169oh_pins: gpio169oh-pins { - pins = "GPIO169/nSCIPME"; - bias-disable; - output-high; - }; - gpio170ol_pins: gpio170ol-pins { - pins = "GPIO170/nSMI"; - bias-disable; - output-low; - }; - gpio218oh_pins: gpio218oh-pins { - pins = "GPIO218/nWDO1"; - bias-disable; - output-high; - }; - gpio37i_pins: gpio37i-pins { - pins = "GPIO37/SMB3CSDA"; - bias-disable; - input-enable; - }; - gpio38i_pins: gpio38i-pins { - pins = "GPIO38/SMB3CSCL"; - bias-disable; - input-enable; - }; - gpio39i_pins: gpio39i-pins { - pins = "GPIO39/SMB3BSDA"; - bias-disable; - input-enable; - }; - gpio40i_pins: gpio40i-pins { - pins = "GPIO40/SMB3BSCL"; - bias-disable; - input-enable; - }; - gpio121i_pins: gpio121i-pins { - pins = "GPIO121/SMB2CSCL"; - bias-disable; - input-enable; - }; - gpio122i_pins: gpio122i-pins { - pins = "GPIO122/SMB2BSDA"; - bias-disable; - input-enable; - }; - gpio123i_pins: gpio123i-pins { - pins = "GPIO123/SMB2BSCL"; - bias-disable; - input-enable; - }; - gpio124i_pins: gpio124i-pins { - pins = "GPIO124/SMB1CSDA"; - bias-disable; - input-enable; - }; - gpio125i_pins: gpio125i-pins { - pins = "GPIO125/SMB1CSCL"; - bias-disable; - input-enable; - }; - gpio126i_pins: gpio126i-pins { - pins = "GPIO126/SMB1BSDA"; - bias-disable; - input-enable; - }; - gpio127i_pins: gpio127i-pins { - pins = "GPIO127/SMB1BSCL"; - bias-disable; - input-enable; - }; - gpio136i_pins: gpio136i-pins { - pins = "GPIO136/SD1DT0"; - bias-disable; - input-enable; - }; - gpio137oh_pins: gpio137oh-pins { - pins = "GPIO137/SD1DT1"; - bias-disable; - output-high; - }; - gpio138i_pins: gpio138i-pins { - pins = "GPIO138/SD1DT2"; - bias-disable; - input-enable; - }; - gpio139i_pins: gpio139i-pins { - pins = "GPIO139/SD1DT3"; - bias-disable; - input-enable; - }; - gpio140i_pins: gpio140i-pins { - pins = "GPIO140/SD1CLK"; - bias-disable; - input-enable; - }; - gpio141i_pins: gpio141i-pins { - pins = "GPIO141/SD1WP"; - bias-disable; - input-enable; - }; - gpio190oh_pins: gpio190oh-pins { - pins = "GPIO190/nPRD_SMI"; - bias-disable; - output-high; - }; - gpio191oh_pins: gpio191oh-pins { - pins = "GPIO191"; - bias-disable; - output-high; - }; - gpio195ol_pins: gpio195ol-pins { - pins = "GPIO195/SMB0BSDA"; - bias-disable; - output-low; - }; - gpio196ol_pins: gpio196ol-pins { - pins = "GPIO196/SMB0CSCL"; - bias-disable; - output-low; - }; - gpio199i_pins: gpio199i-pins { - pins = "GPIO199/SMB0DSCL"; - bias-disable; - input-enable; - }; - gpio202ol_pins: gpio202ol-pins { - pins = "GPIO202/SMB0CSDA"; - bias-disable; - output-low; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - snps,eee-force-disable; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&fiu0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0cs1_pins>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <5000000>; - spi-rx-bus-width = <2>; - label = "bmc"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - u-boot@0 { - label = "u-boot"; - reg = <0x0000000 0xC0000>; - read-only; - }; - u-boot-env@100000{ - label = "u-boot-env"; - reg = <0x00100000 0x40000>; - }; - kernel@200000 { - label = "kernel"; - reg = <0x0200000 0x600000>; - }; - rofs@800000 { - label = "rofs"; - reg = <0x800000 0x3500000>; - }; - rwfs@3d00000 { - label = "rwfs"; - reg = <0x3d00000 0x300000>; - }; - }; - }; - flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - spi-max-frequency = <5000000>; - spi-rx-bus-width = <2>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - spare1@0 { - label = "spi0-cs1-spare1"; - reg = <0x0 0x800000>; - }; - spare2@800000 { - label = "spi0-cs1-spare2"; - reg = <0x800000 0x0>; - }; - }; - }; -}; - -&fiu3 { - pinctrl-0 = <&spi3_pins>; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <5000000>; - spi-rx-bus-width = <2>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - system1@0 { - label = "bios"; - reg = <0x0 0x0>; - }; - system2@800000 { - label = "spi3-system2"; - reg = <0x800000 0x0>; - }; - }; - }; -}; - -&watchdog1 { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&adc { - #io-channel-cells = <1>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - i2c-switch@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c-mux-idle-disconnect; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - // Rear-Fan - max31790@58 { - compatible = "maxim,max31790"; - reg = <0x58>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - // Mid-Fan - max31790@58 { - compatible = "maxim,max31790"; - reg = <0x58>; - }; - }; - - i2c-bus@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - // INLET1_T - lm75@5c { - compatible = "ti,lm75"; - reg = <0x5c>; - }; - }; - - i2c-bus@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - // OUTLET1_T - lm75@5c { - compatible = "ti,lm75"; - reg = <0x5c>; - }; - }; - - i2c-bus@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - // OUTLET2_T - lm75@5c { - compatible = "ti,lm75"; - reg = <0x5c>; - }; - }; - - i2c-bus@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - // OUTLET3_T - lm75@5c { - compatible = "ti,lm75"; - reg = <0x5c>; - }; - }; - }; - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - i2c-bus@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - // STB-T - pmbus@74 { - compatible = "pmbus"; - reg = <0x74>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - smpro@4f { - compatible = "ampere,smpro"; - reg = <0x4f>; - }; - - smpro@4e { - compatible = "ampere,smpro"; - reg = <0x4e>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - i2c-bus@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - // ADC sensors - adm1266@40 { - compatible = "adi,adm1266"; - reg = <0x40>; - }; - }; - - i2c-bus@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - // ADC sensors - adm1266@41 { - compatible = "adi,adm1266"; - reg = <0x41>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; - ssif-bmc@10 { - compatible = "ssif-bmc"; - reg = <0x10>; - }; -}; - -&i2c13 { - status = "okay"; - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - i2c-bus@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - // M2_ZONE_T - lm75@28 { - compatible = "ti,lm75"; - reg = <0x28>; - }; - }; - - i2c-bus@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - // BATT_ZONE_T - lm75@29 { - compatible = "ti,lm75"; - reg = <0x29>; - }; - }; - - i2c-bus@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - // NBM1_ZONE_T - lm75@28 { - compatible = "ti,lm75"; - reg = <0x28>; - }; - }; - i2c-bus@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - // NBM2_ZONE_T - lm75@29 { - compatible = "ti,lm75"; - reg = <0x29>; - }; - }; - }; -}; - -&i2c14 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; - -&spi0 { - cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - &gpio61oh_pins - &gpio62oh_pins - &gpio161ol_pins - &gpio163i_pins - &gpio167ol_pins - &gpio95i_pins - &gpio65ol_pins - &gpio66oh_pins - &gpio67oh_pins - &gpio68ol_pins - &gpio69i_pins - &gpio70ol_pins - &gpio71i_pins - &gpio72i_pins - &gpio73i_pins - &gpio74i_pins - &gpio75i_pins - &gpio76i_pins - &gpio77i_pins - &gpio78i_pins - &gpio79ol_pins - &gpio80oh_pins - &gpio81i_pins - &gpio82i_pins - &gpio83i_pins - &gpio144i_pins - &gpio145i_pins - &gpio146i_pins - &gpio147oh_pins - &gpio168ol_pins - &gpio169oh_pins - &gpio170ol_pins - &gpio218oh_pins - &gpio37i_pins - &gpio38i_pins - &gpio39i_pins - &gpio40i_pins - &gpio121i_pins - &gpio122i_pins - &gpio123i_pins - &gpio124i_pins - &gpio125i_pins - &gpio126i_pins - &gpio127i_pins - &gpio136i_pins - &gpio137oh_pins - &gpio138i_pins - &gpio139i_pins - &gpio140i_pins - &gpio141i_pins - &gpio190oh_pins - &gpio191oh_pins - &gpio195ol_pins - &gpio196ol_pins - &gpio199i_pins - &gpio202ol_pins - >; -}; - -&gcr { - serial_port_mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - - mux-reg-masks = <0x38 0x07>; - idle-states = <2>; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi deleted file mode 100644 index 86ec12ec2b50..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm730.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 Nuvoton Technology - -#include "nuvoton-common-npcm7xx.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "nuvoton,npcm750-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk NPCM7XX_CLK_CPU>; - clock-names = "clk_cpu"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk NPCM7XX_CLK_CPU>; - clock-names = "clk_cpu"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - soc { - timer@3fe600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x3fe600 0x20>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_AHB>; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts deleted file mode 100644 index f53d45fa1de8..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com -// Copyright 2018 Google, Inc. - -/dts-v1/; -#include "nuvoton-npcm750.dtsi" -#include "dt-bindings/gpio/gpio.h" -#include "nuvoton-npcm750-pincfg-evb.dtsi" - -/ { - model = "Nuvoton npcm750 Development Board (Device Tree)"; - compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750"; - - aliases { - ethernet2 = &gmac0; - ethernet3 = &gmac1; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - spi0 = &spi0; - spi1 = &spi1; - fiu0 = &fiu0; - fiu1 = &fiu3; - fiu2 = &fiux; - }; - - chosen { - stdout-path = &serial3; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&fiu0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-rx-bus-width = <2>; - reg = <0>; - spi-max-frequency = <5000000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - bbuboot1@0 { - label = "bb-uboot-1"; - reg = <0x0000000 0x80000>; - read-only; - }; - bbuboot2@80000 { - label = "bb-uboot-2"; - reg = <0x0080000 0x80000>; - read-only; - }; - envparam@100000 { - label = "env-param"; - reg = <0x0100000 0x40000>; - read-only; - }; - spare@140000 { - label = "spare"; - reg = <0x0140000 0xC0000>; - }; - kernel@200000 { - label = "kernel"; - reg = <0x0200000 0x400000>; - }; - rootfs@600000 { - label = "rootfs"; - reg = <0x0600000 0x700000>; - }; - spare1@d00000 { - label = "spare1"; - reg = <0x0D00000 0x200000>; - }; - spare2@f00000 { - label = "spare2"; - reg = <0x0F00000 0x200000>; - }; - spare3@1100000 { - label = "spare3"; - reg = <0x1100000 0x200000>; - }; - spare4@1300000 { - label = "spare4"; - reg = <0x1300000 0x0>; - }; - }; - }; -}; - -&fiu3 { - pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-rx-bus-width = <2>; - reg = <0>; - spi-max-frequency = <5000000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - system1@0 { - label = "spi3-system1"; - reg = <0x0 0x0>; - }; - }; - }; -}; - -&fiux { - spix-mode; -}; - -&watchdog1 { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&lpc_kcs { - kcs1: kcs1@0 { - status = "okay"; - }; - - kcs2: kcs2@0 { - status = "okay"; - }; - - kcs3: kcs3@0 { - status = "okay"; - }; -}; - -/* lm75 on SVB */ -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - lm75@48 { - compatible = "lm75"; - reg = <0x48>; - status = "okay"; - }; -}; - -/* lm75 on EB */ -&i2c1 { - clock-frequency = <100000>; - status = "okay"; - lm75@48 { - compatible = "lm75"; - reg = <0x48>; - status = "okay"; - }; -}; - -/* tmp100 on EB */ -&i2c2 { - clock-frequency = <100000>; - status = "okay"; - tmp100@48 { - compatible = "tmp100"; - reg = <0x48>; - status = "okay"; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c5 { - clock-frequency = <100000>; - status = "okay"; -}; - -/* tmp100 on SVB */ -&i2c6 { - clock-frequency = <100000>; - status = "okay"; - tmp100@48 { - compatible = "tmp100"; - reg = <0x48>; - status = "okay"; - }; -}; - -&i2c7 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c8 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c9 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c10 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c11 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c14 { - clock-frequency = <100000>; - status = "okay"; -}; - -&pwm_fan { - status = "okay"; - fan@0 { - reg = <0x00>; - fan-tach-ch = /bits/ 8 <0x00 0x01>; - cooling-levels = <127 255>; - }; - fan@1 { - reg = <0x01>; - fan-tach-ch = /bits/ 8 <0x02 0x03>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@2 { - reg = <0x02>; - fan-tach-ch = /bits/ 8 <0x04 0x05>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@3 { - reg = <0x03>; - fan-tach-ch = /bits/ 8 <0x06 0x07>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@4 { - reg = <0x04>; - fan-tach-ch = /bits/ 8 <0x08 0x09>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@5 { - reg = <0x05>; - fan-tach-ch = /bits/ 8 <0x0A 0x0B>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@6 { - reg = <0x06>; - fan-tach-ch = /bits/ 8 <0x0C 0x0D>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@7 { - reg = <0x07>; - fan-tach-ch = /bits/ 8 <0x0E 0x0F>; - cooling-levels = /bits/ 8 <127 255>; - }; -}; - -&spi0 { - cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - status = "okay"; - flash@0 { - compatible = "winbond,w25q128", - "jedec,spi-nor"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <5000000>; - partition@0 { - label = "spi0_spare1"; - reg = <0x0000000 0x800000>; - }; - partition@1 { - label = "spi0_spare2"; - reg = <0x800000 0x0>; - }; - }; -}; - -&spi1 { - cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - status = "okay"; - flash@0 { - compatible = "winbond,w25q128fw", - "jedec,spi-nor"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <5000000>; - partition@0 { - label = "spi1_spare1"; - reg = <0x0000000 0x800000>; - }; - partition@1 { - label = "spi1_spare2"; - reg = <0x800000 0x0>; - }; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < &iox1_pins - &pin8_input - &pin9_output_high - &pin10_input - &pin11_output_high - &pin16_input - &pin24_output_high - &pin25_output_low - &pin32_output_high - &jtag2_pins - &pin61_output_high - &pin62_output_high - &pin63_output_high - &lpc_pins - &pin160_input - &pin162_input - &pin168_input - &pin169_input - &pin170_input - &pin187_output_high - &pin190_input - &pin191_output_high - &pin192_output_high - &pin197_output_low - &ddc_pins - &pin218_input - &pin219_output_low - &pin220_output_low - &pin221_output_high - &pin222_input - &pin223_output_low - &spix_pins - &pin228_output_low - &pin231_output_high - &pin255_input>; -}; - diff --git a/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi deleted file mode 100644 index 3b3806274adf..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology - -/ { - pinctrl: pinctrl@f0800000 { - pin8_input: pin8-input { - pins = "GPIO8/LKGPO1"; - bias-disable; - input-enable; - }; - pin9_output_high: pin9-output-high { - pins = "GPIO9/LKGPO2"; - bias-disable; - output-high; - }; - pin10_input: pin10-input { - pins = "GPIO10/IOXHLD"; - bias-disable; - input-enable; - }; - pin11_output_high: pin11-output-high { - pins = "GPIO11/IOXHCK"; - bias-disable; - output-high; - }; - pin16_input: pin16-input { - pins = "GPIO16/LKGPO0"; - bias-disable; - input-enable; - }; - pin24_output_high: pin24-output-high { - pins = "GPIO24/IOXHDO"; - bias-disable; - output-high; - }; - pin25_output_low: pin25-output-low { - pins = "GPIO25/IOXHDI"; - bias-disable; - output-low; - }; - pin32_output_high: pin32-output-high { - pins = "GPIO32/nSPI0CS1"; - bias-disable; - output-high; - }; - pin61_output_high: pin61-output-high { - pins = "GPO61/nDTR1_BOUT1/STRAP6"; - bias-disable; - output-high; - }; - pin62_output_high: pin62-output-high { - pins = "GPO62/nRTST1/STRAP5"; - bias-disable; - output-high; - }; - pin63_output_high: pin63-output-high { - pins = "GPO63/TXD1/STRAP4"; - bias-disable; - output-high; - }; - pin160_input: pin160-input { - pins = "GPIO160/CLKOUT/RNGOSCOUT"; - bias-disable; - input-enable; - }; - pin162_input: pin162-input { - pins = "GPIO162/SERIRQ"; - bias-disable; - input-enable; - }; - pin168_input: pin168-input { - pins = "GPIO168/nCLKRUN/nESPIALERT"; - bias-disable; - input-enable; - }; - pin169_input: pin169-input { - pins = "GPIO169/nSCIPME"; - bias-disable; - input-enable; - }; - pin170_input: pin170-input { - pins = "GPIO170/nSMI"; - bias-disable; - input-enable; - }; - pin187_output_high: pin187-output-high { - pins = "GPIO187/nSPI3CS1"; - bias-disable; - output-high; - }; - pin190_input: pin190-input { - pins = "GPIO190/nPRD_SMI"; - bias-disable; - input-enable; - }; - pin191_output_high: pin191-output-high { - pins = "GPIO191"; - bias-disable; - output-high; - }; - pin192_output_high: pin192-output-high { - pins = "GPIO192"; - bias-disable; - output-high; - }; - pin197_output_low: pin197-output-low { - pins = "GPIO197/SMB0DEN"; - bias-disable; - output-low; - }; - pin218_input: pin218-input { - pins = "GPIO218/nWDO1"; - bias-disable; - input-enable; - }; - pin219_output_low: pin219-output-low { - pins = "GPIO219/nWDO2"; - bias-disable; - output-low; - }; - pin220_output_low: pin220-output-low { - pins = "GPIO220/SMB12SCL"; - bias-disable; - output-low; - }; - pin221_output_high: pin221-output-high { - pins = "GPIO221/SMB12SDA"; - bias-disable; - output-high; - }; - pin222_input: pin222-input { - pins = "GPIO222/SMB13SCL"; - bias-disable; - input-enable; - }; - pin223_output_low: pin223-output-low { - pins = "GPIO223/SMB13SDA"; - bias-disable; - output-low; - }; - pin228_output_low: pin228-output-low { - pins = "GPIO228/nSPIXCS1"; - bias-disable; - output-low; - }; - pin231_output_high: pin231-output-high { - pins = "GPIO230/SPIXD3"; - bias-disable; - output-high; - }; - pin255_input: pin255-input { - pins = "GPI255/DACOSEL"; - bias-disable; - input-enable; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi deleted file mode 100644 index 230cb344b2e1..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com - -/ { - pinctrl: pinctrl@f0800000 { - gpio0ol_pins: gpio0ol-pins { - pins = "GPIO0/IOX1DI"; - bias-disable; - output-low; - }; - gpio1ol_pins: gpio1ol-pins { - pins = "GPIO1/IOX1LD"; - bias-disable; - output-low; - }; - gpio2ol_pins: gpio2ol-pins { - pins = "GPIO2/IOX1CK"; - bias-disable; - output-low; - }; - gpio3ol_pins: gpio3ol-pins { - pins = "GPIO3/IOX1D0"; - bias-disable; - output-low; - }; - gpio5_pins: gpio5-pins { - pins = "GPIO5/IOX2LD/SMB1DSCL"; - bias-disable; - input-enable; - }; - gpio6_pins: gpio6-pins { - pins = "GPIO6/IOX2CK/SMB2DSDA"; - bias-disable; - input-enable; - }; - gpio7_pins: gpio7-pins { - pins = "GPIO7/IOX2D0/SMB2DSCL"; - bias-disable; - input-enable; - }; - gpio8o_pins: gpio8o-pins { - pins = "GPIO8/LKGPO1"; - bias-disable; - output-high; - }; - gpio9ol_pins: gpio9ol-pins { - pins = "GPIO9/LKGPO2"; - bias-disable; - output-low; - }; - gpio10_pins: gpio10-pins { - pins = "GPIO10/IOXHLD"; - bias-disable; - input-enable; - }; - gpio11_pins: gpio11-pins { - pins = "GPIO11/IOXHCK"; - bias-disable; - input-enable; - }; - gpio12ol_pins: gpio12ol-pins { - pins = "GPIO12/GSPICK/SMB5BSCL"; - bias-disable; - output-low; - }; - gpio13ol_pins: gpio13ol-pins { - pins = "GPIO13/GSPIDO/SMB5BSDA"; - bias-disable; - output-low; - }; - gpio14ol_pins: gpio14ol-pins { - pins = "GPIO14/GSPIDI/SMB5CSCL"; - bias-disable; - output-low; - }; - gpio15ol_pins: gpio15ol-pins { - pins = "GPIO15/GSPICS/SMB5CSDA"; - bias-disable; - output-low; - }; - gpio20_pins: gpio20-pins { - pins = "GPIO20/SMB4CSDA/SMB15SDA"; - bias-disable; - input-enable; - }; - gpio21_pins: gpio21-pins { - pins = "GPIO21/SMB4CSCL/SMB15SCL"; - bias-disable; - input-enable; - }; - gpio22o_pins: gpio22o-pins { - pins = "GPIO22/SMB4DSDA/SMB14SDA"; - bias-disable; - output-high; - }; - gpio23_pins: gpio23-pins { - pins = "GPIO23/SMB4DSCL/SMB14SCL"; - bias-disable; - input-enable; - }; - gpio24_pins: gpio24-pins { - pins = "GPIO24/IOXHDO"; - bias-disable; - input-enable; - }; - gpio25_pins: gpio25-pins { - pins = "GPIO25/IOXHDI"; - bias-disable; - input-enable; - }; - gpio30_pins: gpio30-pins { - pins = "GPIO30/SMB3SDA"; - bias-disable; - input-enable; - }; - gpio31_pins: gpio31-pins { - pins = "GPIO31/SMB3SCL"; - bias-disable; - input-enable; - }; - gpio37o_pins: gpio37o-pins { - pins = "GPIO37/SMB3CSDA"; - bias-disable; - output-high; - }; - gpio38_pins: gpio38-pins { - pins = "GPIO38/SMB3CSCL"; - bias-disable; - input-enable; - }; - gpio39_pins: gpio39-pins { - pins = "GPIO39/SMB3BSDA"; - bias-disable; - input-enable; - }; - gpio40o_pins: gpio40o-pins { - pins = "GPIO40/SMB3BSCL"; - bias-disable; - output-high; - }; - gpio59_pins: gpio59-pins { - pins = "GPIO59/SMB3DSDA"; - bias-disable; - input-enable; - }; - gpio76_pins: gpio76-pins { - pins = "GPIO76/FANIN12"; - bias-disable; - input-enable; - }; - gpio77_pins: gpio77-pins { - pins = "GPIO77/FANIN13"; - bias-disable; - input-enable; - }; - gpio78o_pins: gpio78o-pins { - pins = "GPIO78/FANIN14"; - bias-disable; - output-high; - }; - gpio79_pins: gpio79-pins { - pins = "GPIO79/FANIN15"; - bias-disable; - input-enable; - }; - gpio82_pins: gpio82-pins { - pins = "GPIO82/PWM2"; - bias-disable; - input-enable; - }; - gpio83_pins: gpio83-pins { - pins = "GPIO83/PWM3"; - bias-disable; - input-enable; - }; - gpio84_pins: gpio84-pins { - pins = "GPIO84/R2TXD0"; - bias-disable; - input-enable; - }; - gpio85o_pins: gpio85o-pins { - pins = "GPIO85/R2TXD1"; - bias-disable; - output-high; - }; - gpio86ol_pins: gpio86ol-pins { - pins = "GPIO86/R2TXEN"; - bias-disable; - output-low; - }; - gpio87_pins: gpio87-pins { - pins = "GPIO87/R2RXD0"; - bias-disable; - input-enable; - }; - gpio88_pins: gpio88-pins { - pins = "GPIO88/R2RXD1"; - bias-disable; - input-enable; - }; - gpio89_pins: gpio89-pins { - pins = "GPIO89/R2CRSDV"; - bias-disable; - input-enable; - }; - gpio90_pins: gpio90-pins { - pins = "GPIO90/R2RXERR"; - bias-disable; - input-enable; - }; - gpio93_pins: gpio93-pins { - pins = "GPIO93/GA20/SMB5DSCL"; - bias-disable; - input-enable; - }; - gpio94ol_pins: gpio94ol-pins { - pins = "GPIO94/nKBRST/SMB5DSDA"; - bias-disable; - output-low; - }; - gpio108ol_pins: gpio108ol-pins { - pins = "GPIO108/RG1MDC"; - bias-disable; - output-low; - }; - gpio109ol_pins: gpio109ol-pins { - pins = "GPIO109/RG1MDIO"; - bias-disable; - output-low; - }; - gpio110ol_pins: gpio110ol-pins { - pins = "GPIO110/RG2TXD0/DDRV0"; - bias-disable; - output-low; - }; - gpio111ol_pins: gpio111ol-pins { - pins = "GPIO111/RG2TXD1/DDRV1"; - bias-disable; - output-low; - }; - gpio112ol_pins: gpio112ol-pins { - pins = "GPIO112/RG2TXD2/DDRV2"; - bias-disable; - output-low; - }; - gpio113ol_pins: gpio113ol-pins { - pins = "GPIO113/RG2TXD3/DDRV3"; - bias-disable; - output-low; - }; - gpio114o_pins: gpio114o-pins { - pins = "GPIO114/SMB0SCL"; - bias-disable; - output-high; - }; - gpio115_pins: gpio115-pins { - pins = "GPIO115/SMB0SDA"; - bias-disable; - input-enable; - }; - gpio120_pins: gpio120-pins { - pins = "GPIO120/SMB2CSDA"; - bias-disable; - input-enable; - }; - gpio121_pins: gpio121-pins { - pins = "GPIO121/SMB2CSCL"; - bias-disable; - input-enable; - }; - gpio122_pins: gpio122-pins { - pins = "GPIO122/SMB2BSDA"; - bias-disable; - input-enable; - }; - gpio123_pins: gpio123-pins { - pins = "GPIO123/SMB2BSCL"; - bias-disable; - input-enable; - }; - gpio124_pins: gpio124-pins { - pins = "GPIO124/SMB1CSDA"; - bias-disable; - input-enable; - }; - gpio125_pins: gpio125-pins { - pins = "GPIO125/SMB1CSCL"; - bias-disable; - input-enable; - }; - gpio126_pins: gpio126-pins { - pins = "GPIO126/SMB1BSDA"; - bias-disable; - input-enable; - }; - gpio127o_pins: gpio127o-pins { - pins = "GPIO127/SMB1BSCL"; - bias-disable; - output-high; - }; - gpio136_pins: gpio136-pins { - pins = "GPIO136/SD1DT0"; - bias-disable; - input-enable; - }; - gpio137_pins: gpio137-pins { - pins = "GPIO137/SD1DT1"; - bias-disable; - input-enable; - }; - gpio138_pins: gpio138-pins { - pins = "GPIO138/SD1DT2"; - bias-disable; - input-enable; - }; - gpio139_pins: gpio139-pins { - pins = "GPIO139/SD1DT3"; - bias-disable; - input-enable; - }; - gpio140_pins: gpio140-pins { - pins = "GPIO140/SD1CLK"; - bias-disable; - input-enable; - }; - gpio141_pins: gpio141-pins { - pins = "GPIO141/SD1WP"; - bias-disable; - input-enable; - }; - gpio142_pins: gpio142-pins { - pins = "GPIO142/SD1CMD"; - bias-disable; - input-enable; - }; - gpio143_pins: gpio143-pins { - pins = "GPIO143/SD1CD/SD1PWR"; - bias-disable; - input-enable; - }; - gpio144_pins: gpio144-pins { - pins = "GPIO144/PWM4"; - bias-disable; - input-enable; - }; - gpio145_pins: gpio145-pins { - pins = "GPIO145/PWM5"; - bias-disable; - input-enable; - }; - gpio146_pins: gpio146-pins { - pins = "GPIO146/PWM6"; - bias-disable; - input-enable; - }; - gpio147_pins: gpio147-pins { - pins = "GPIO147/PWM7"; - bias-disable; - input-enable; - }; - gpio153o_pins: gpio153o-pins { - pins = "GPIO153/MMCWP"; - bias-disable; - output-high; - }; - gpio155_pins: gpio155-pins { - pins = "GPIO155/nMMCCD/nMMCRST"; - bias-disable; - input-enable; - }; - gpio160o_pins: gpio160o-pins { - pins = "GPIO160/CLKOUT/RNGOSCOUT"; - bias-disable; - output-high; - }; - gpio169o_pins: gpio169o-pins { - pins = "GPIO169/nSCIPME"; - bias-disable; - output-high; - }; - gpio188o_pins: gpio188o-pins { - pins = "GPIO188/SPI3D2/nSPI3CS2"; - bias-disable; - output-high; - }; - gpio189_pins: gpio189-pins { - pins = "GPIO189/SPI3D3/nSPI3CS3"; - bias-disable; - input-enable; - }; - gpio196_pins: gpio196-pins { - pins = "GPIO196/SMB0CSCL"; - bias-disable; - input-enable; - }; - gpio197_pins: gpio197-pins { - pins = "GPIO197/SMB0DEN"; - bias-disable; - input-enable; - }; - gpio198o_pins: gpio198o-pins { - pins = "GPIO198/SMB0DSDA"; - bias-disable; - output-high; - }; - gpio199o_pins: gpio199o-pins { - pins = "GPIO199/SMB0DSCL"; - bias-disable; - output-high; - }; - gpio200_pins: gpio200-pins { - pins = "GPIO200/R2CK"; - input-enable; - bias-disable; - }; - gpio202_pins: gpio202-pins { - pins = "GPIO202/SMB0CSDA"; - bias-disable; - input-enable; - }; - gpio203o_pins: gpio203o-pins { - pins = "GPIO203/FANIN16"; - bias-disable; - output-high; - }; - gpio208_pins: gpio208-pins { - pins = "GPIO208/RG2TXC/DVCK"; - bias-disable; - input-enable; - }; - gpio209ol_pins: gpio209ol-pins { - pins = "GPIO209/RG2TXCTL/DDRV4"; - bias-disable; - output-low; - }; - gpio210ol_pins: gpio210ol-pins { - pins = "GPIO210/RG2RXD0/DDRV5"; - bias-disable; - output-low; - }; - gpio211ol_pins: gpio211ol-pins { - pins = "GPIO211/RG2RXD1/DDRV6"; - bias-disable; - output-low; - }; - gpio212ol_pins: gpio212ol-pins { - pins = "GPIO212/RG2RXD2/DDRV7"; - bias-disable; - output-low; - }; - gpio213ol_pins: gpio213ol-pins { - pins = "GPIO213/RG2RXD3/DDRV8"; - bias-disable; - output-low; - }; - gpio214ol_pins: gpio214ol-pins { - pins = "GPIO214/RG2RXC/DDRV9"; - bias-disable; - output-low; - }; - gpio215ol_pins: gpio215ol-pins { - pins = "GPIO215/RG2RXCTL/DDRV10"; - bias-disable; - output-low; - }; - gpio216ol_pins: gpio216ol-pins { - pins = "GPIO216/RG2MDC/DDRV11"; - bias-disable; - output-low; - }; - gpio217ol_pins: gpio217ol-pins { - pins = "GPIO217/RG2MDIO/DVHSYNC"; - bias-disable; - output-low; - }; - gpio224_pins: gpio224-pins { - pins = "GPIO224/SPIXCK"; - bias-disable; - input-enable; - }; - gpio225ol_pins: gpio225ol-pins { - pins = "GPO225/SPIXD0/STRAP12"; - bias-disable; - output-low; - }; - gpio226ol_pins: gpio226ol-pins { - pins = "GPO226/SPIXD1/STRAP13"; - bias-disable; - output-low; - }; - gpio227ol_pins: gpio227ol-pins { - pins = "GPIO227/nSPIXCS0"; - bias-disable; - output-low; - }; - gpio228o_pins: gpio228ol-pins { - pins = "GPIO228/nSPIXCS1"; - bias-disable; - output-high; - }; - gpio229o_pins: gpio229o-pins { - pins = "GPO229/SPIXD2/STRAP3"; - bias-disable; - output-high; - }; - gpio230_pins: gpio230-pins { - pins = "GPIO230/SPIXD3"; - bias-disable; - input-enable; - }; - gpio231o_pins: gpio231o-pins { - pins = "GPIO231/nCLKREQ"; - bias-disable; - output-high; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts deleted file mode 100644 index 87359ab05db3..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts +++ /dev/null @@ -1,1052 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2019 Nuvoton Technology -// Copyright (c) 2019 Quanta Computer Inc. - -/dts-v1/; -#include "nuvoton-npcm750.dtsi" -#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi" - -#include -#include - -/ { - model = "Nuvoton npcm750 RunBMC Olympus"; - compatible = "nuvoton,npcm750"; - - aliases { - ethernet1 = &gmac0; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - spi0 = &spi0; - spi1 = &spi1; - fiu0 = &fiu0; - fiu1 = &fiu3; - }; - - chosen { - stdout-path = &serial3; - }; - - memory { - reg = <0 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; - - leds { - compatible = "gpio-leds"; - heartbeat { - label = "heartbeat"; - gpios = <&gpio3 14 1>; - }; - - identify { - label = "identify"; - gpios = <&gpio3 15 1>; - }; - }; - - jtag { - compatible = "nuvoton,npcm750-jtag"; - enable_pspi_jtag = <1>; - pspi-index = <2>; - tck { - label = "tck"; - gpios = <&gpio0 19 0>; /* gpio19 */ - regbase = <0xf0010000 0x1000>; - }; - - tdi { - label = "tdi"; - gpios = <&gpio0 18 0>; /* gpio18 */ - regbase = <0xf0010000 0x1000>; - }; - - tdo { - label = "tdo"; - gpios = <&gpio0 17 0>; /* gpio17 */ - regbase = <0xf0010000 0x1000>; - }; - tms { - label = "tms"; - gpios = <&gpio0 16 0>; /* gpio16 */ - regbase = <0xf0010000 0x1000>; - }; - }; -}; - -&fiu0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0cs1_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-rx-bus-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - bmc@0{ - label = "bmc"; - reg = <0x000000 0x2000000>; - }; - u-boot@0 { - label = "u-boot"; - reg = <0x0000000 0x80000>; - read-only; - }; - u-boot-env@100000{ - label = "u-boot-env"; - reg = <0x00100000 0x40000>; - }; - kernel@200000 { - label = "kernel"; - reg = <0x0200000 0x600000>; - }; - rofs@800000 { - label = "rofs"; - reg = <0x800000 0x1500000>; - }; - rwfs@1d00000 { - label = "rwfs"; - reg = <0x1d00000 0x300000>; - }; - }; - }; - - flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - npcm,fiu-rx-bus-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - spare1@0 { - label = "spi0-cs1-spare1"; - reg = <0x0 0x800000>; - }; - spare2@800000 { - label = "spi0-cs1-spare2"; - reg = <0x800000 0x0>; - }; - }; - }; -}; - -&fiu3 { - pinctrl-0 = <&spi3_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-rx-bus-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - system1@0 { - label = "spi3-system1"; - reg = <0x0 0x800000>; - }; - system2@800000 { - label = "spi3-system2"; - reg = <0x800000 0x0>; - }; - }; - }; -}; - -&gcr { - mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - - mux-reg-masks = <0x38 0x07>; - idle-states = <6>; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - snps,eee-force-disable; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - i2c_slot1a: i2c-bus@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_slot1b: i2c-bus@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_slot2a: i2c-bus@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_slot2b: i2c-bus@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c_slot3: i2c-bus@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c_slot4: i2c-bus@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c_slot5: i2c-bus@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - }; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c_m2_s1: i2c-bus@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_m2_s2: i2c-bus@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2c_m2_s3: i2c-bus@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_m2_s4: i2c-bus@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c2 { - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - power-supply@58 { - compatible = "delta,dps800"; - reg = <0x58>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c5 { - status = "okay"; - - i2c-slave-mqueue@10 { - compatible = "i2c-slave-mqueue"; - reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>; - }; -}; - -&i2c6 { - status = "okay"; - - ina219@40 { - compatible = "ti,ina219"; - reg = <0x40>; - }; - ina219@41 { - compatible = "ti,ina219"; - reg = <0x41>; - }; - ina219@44 { - compatible = "ti,ina219"; - reg = <0x44>; - }; - ina219@45 { - compatible = "ti,ina219"; - reg = <0x45>; - }; - tps53679@60 { - compatible = "ti,tps53679"; - reg = <0x60>; - }; - tps53659@62 { - compatible = "ti,tps53659"; - reg = <0x62>; - }; - tps53659@64 { - compatible = "ti,tps53659"; - reg = <0x64>; - }; - tps53622@67 { - compatible = "ti,tps53622"; - reg = <0x67>; - }; - tps53622@69 { - compatible = "ti,tps53622"; - reg = <0x69>; - }; - tps53679@70 { - compatible = "ti,tps53679"; - reg = <0x70>; - }; - tps53659@72 { - compatible = "ti,tps53659"; - reg = <0x72>; - }; - tps53659@74 { - compatible = "ti,tps53659"; - reg = <0x74>; - }; - tps53622@77 { - compatible = "ti,tps53622"; - reg = <0x77>; - }; -}; - -&i2c7 { - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; -}; - -&i2c8 { - status = "okay"; - - adm1278@11 { - compatible = "adm1278"; - reg = <0x11>; - Rsense = <500>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; - - gpio: pca9555@27 { - compatible = "nxp,pca9555"; - reg = <0x27>; - - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c11 { - status = "okay"; - - pca9539_g1a: pca9539-g1a@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - G1A_P0_0 { - gpio-hog; - gpios = <0 0>; - output-high; - line-name = "TPM_BMC_ALERT_N"; - }; - G1A_P0_1 { - gpio-hog; - gpios = <1 0>; - input; - line-name = "FM_BIOS_TOP_SWAP"; - }; - G1A_P0_2 { - gpio-hog; - gpios = <2 0>; - input; - line-name = "FM_BIOS_PREFRB2_GOOD"; - }; - G1A_P0_3 { - gpio-hog; - gpios = <3 0>; - input; - line-name = "BMC_SATAXPCIE_0TO3_SEL"; - }; - G1A_P0_4 { - gpio-hog; - gpios = <4 0>; - input; - line-name = "BMC_SATAXPCIE_4TO7_SEL"; - }; - G1A_P0_5 { - gpio-hog; - gpios = <5 0>; - output-low; - line-name = "FM_UV_ADR_TRIGGER_EN_N"; - }; - G1A_P0_6 { - gpio-hog; - gpios = <6 0>; - input; - line-name = "RM_THROTTLE_EN_N"; - }; - G1A_P1_0 { - gpio-hog; - gpios = <8 0>; - input; - line-name = "FM_BMC_TPM_PRES_N"; - }; - G1A_P1_1 { - gpio-hog; - gpios = <9 0>; - input; - line-name = "FM_CPU0_SKTOCC_LVT3_N"; - }; - G1A_P1_2 { - gpio-hog; - gpios = <10 0>; - input; - line-name = "FM_CPU1_SKTOCC_LVT3_N"; - }; - G1A_P1_3 { - gpio-hog; - gpios = <11 0>; - input; - line-name = "PSU1_ALERT_N"; - }; - G1A_P1_4 { - gpio-hog; - gpios = <12 0>; - input; - line-name = "PSU2_ALERT_N"; - }; - G1A_P1_5 { - gpio-hog; - gpios = <13 0>; - input; - line-name = "H_CPU0_FAST_WAKE_LVT3_N"; - }; - G1A_P1_6 { - gpio-hog; - gpios = <14 0>; - output-high; - line-name = "I2C_MUX1_RESET_N"; - }; - G1A_P1_7 { - gpio-hog; - gpios = <15 0>; - input; - line-name = "FM_CPU_CATERR_LVT3_N"; - }; - }; - - pca9539_g1b: pca9539-g1b@75 { - compatible = "nxp,pca9539"; - reg = <0x75>; - gpio-controller; - #gpio-cells = <2>; - G1B_P0_0 { - gpio-hog; - gpios = <0 0>; - input; - line-name = "PVDDQ_ABC_PINALERT_N"; - }; - G1B_P0_1 { - gpio-hog; - gpios = <1 0>; - input; - line-name = "PVDDQ_DEF_PINALERT_N"; - }; - G1B_P0_2 { - gpio-hog; - gpios = <2 0>; - input; - line-name = "PVDDQ_GHJ_PINALERT_N"; - }; - G1B_P0_3 { - gpio-hog; - gpios = <3 0>; - input; - line-name = "PVDDQ_KLM_PINALERT_N"; - }; - G1B_P0_5 { - gpio-hog; - gpios = <5 0>; - input; - line-name = "FM_BOARD_REV_ID0"; - }; - G1B_P0_6 { - gpio-hog; - gpios = <6 0>; - input; - line-name = "FM_BOARD_REV_ID1"; - }; - G1B_P0_7 { - gpio-hog; - gpios = <7 0>; - input; - line-name = "FM_BOARD_REV_ID2"; - }; - G1B_P1_0 { - gpio-hog; - gpios = <8 0>; - input; - line-name = "FM_OC_DETECT_EN_N"; - }; - G1B_P1_1 { - gpio-hog; - gpios = <9 0>; - input; - line-name = "FM_FLASH_DESC_OVERRIDE"; - }; - G1B_P1_2 { - gpio-hog; - gpios = <10 0>; - output-low; - line-name = "FP_PWR_ID_LED_N"; - }; - G1B_P1_3 { - gpio-hog; - gpios = <11 0>; - output-low; - line-name = "BMC_LED_PWR_GRN"; - }; - G1B_P1_4 { - gpio-hog; - gpios = <12 0>; - output-low; - line-name = "BMC_LED_PWR_AMBER"; - }; - G1B_P1_5 { - gpio-hog; - gpios = <13 0>; - output-high; - line-name = "FM_BMC_FAULT_LED_N"; - }; - G1B_P1_6 { - gpio-hog; - gpios = <14 0>; - output-high; - line-name = "FM_CPLD_BMC_PWRDN_N"; - }; - G1B_P1_7 { - gpio-hog; - gpios = <15 0>; - output-high; - line-name = "BMC_LED_CATERR_N"; - }; - }; -}; - -&i2c12 { - status = "okay"; - - pca9539_g2a: pca9539-g2a@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; - G2A_P0_0 { - gpio-hog; - gpios = <0 0>; - output-high; - line-name = "BMC_PON_RST_REQ_N"; - }; - G2A_P0_1 { - gpio-hog; - gpios = <1 0>; - output-high; - line-name = "BMC_RST_IND_REQ_N"; - }; - G2A_P0_2 { - gpio-hog; - gpios = <2 0>; - input; - line-name = "RST_BMC_RTCRST"; - }; - G2A_P0_3 { - gpio-hog; - gpios = <3 0>; - output-high; - line-name = "FM_BMC_PWRBTN_OUT_N"; - }; - G2A_P0_4 { - gpio-hog; - gpios = <4 0>; - output-high; - line-name = "RST_BMC_SYSRST_BTN_OUT_N"; - }; - G2A_P0_5 { - gpio-hog; - gpios = <5 0>; - output-high; - line-name = "FM_BATTERY_SENSE_EN_N"; - }; - G2A_P0_6 { - gpio-hog; - gpios = <6 0>; - output-high; - line-name = "FM_BMC_READY_N"; - }; - G2A_P0_7 { - gpio-hog; - gpios = <7 0>; - input; - line-name = "IRQ_BMC_PCH_SMI_LPC_N"; - }; - G2A_P1_0 { - gpio-hog; - gpios = <8 0>; - input; - line-name = "FM_SLOT4_CFG0"; - }; - G2A_P1_1 { - gpio-hog; - gpios = <9 0>; - input; - line-name = "FM_SLOT4_CFG1"; - }; - G2A_P1_2 { - gpio-hog; - gpios = <10 0>; - input; - line-name = "FM_NVDIMM_EVENT_N"; - }; - G2A_P1_3 { - gpio-hog; - gpios = <11 0>; - input; - line-name = "PSU1_BLADE_EN_N"; - }; - G2A_P1_4 { - gpio-hog; - gpios = <12 0>; - input; - line-name = "BMC_PCH_FNM"; - }; - G2A_P1_5 { - gpio-hog; - gpios = <13 0>; - input; - line-name = "FM_SOL_UART_CH_SEL"; - }; - G2A_P1_6 { - gpio-hog; - gpios = <14 0>; - input; - line-name = "FM_BIOS_POST_CMPLT_N"; - }; - }; - - pca9539_g2b: pca9539-g2b@75 { - compatible = "nxp,pca9539"; - reg = <0x75>; - gpio-controller; - #gpio-cells = <2>; - G2B_P0_0 { - gpio-hog; - gpios = <0 0>; - input; - line-name = "FM_CPU_MSMI_LVT3_N"; - }; - G2B_P0_1 { - gpio-hog; - gpios = <1 0>; - input; - line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; - }; - G2B_P0_2 { - gpio-hog; - gpios = <2 0>; - input; - line-name = "FM_CPU1_DISABLE_BMC_N"; - }; - G2B_P0_3 { - gpio-hog; - gpios = <3 0>; - output-low; - line-name = "BMC_JTAG_SELECT"; - }; - G2B_P0_4 { - gpio-hog; - gpios = <4 0>; - output-high; - line-name = "PECI_MUX_SELECT"; - }; - G2B_P0_5 { - gpio-hog; - gpios = <5 0>; - output-high; - line-name = "I2C_MUX2_RESET_N"; - }; - G2B_P0_6 { - gpio-hog; - gpios = <6 0>; - input; - line-name = "FM_BMC_CPLD_PSU2_ON"; - }; - G2B_P0_7 { - gpio-hog; - gpios = <7 0>; - output-high; - line-name = "PSU2_ALERT_EN_N"; - }; - G2B_P1_0 { - gpio-hog; - gpios = <8 0>; - output-high; - line-name = "FM_CPU_BMC_INIT"; - }; - G2B_P1_1 { - gpio-hog; - gpios = <9 0>; - output-high; - line-name = "IRQ_BMC_PCH_SCI_LPC_N"; - }; - G2B_P1_2 { - gpio-hog; - gpios = <10 0>; - output-low; - line-name = "PMB_ALERT_EN_N"; - }; - G2B_P1_3 { - gpio-hog; - gpios = <11 0>; - output-high; - line-name = "FM_FAST_PROCHOT_EN_N"; - }; - G2B_P1_4 { - gpio-hog; - gpios = <12 0>; - output-high; - line-name = "BMC_NVDIMM_PRSNT_N"; - }; - G2B_P1_5 { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; - }; - G2B_P1_6 { - gpio-hog; - gpios = <14 0>; - output-high; - line-name = "FM_PWRBRK_N"; - }; - }; -}; - -&i2c13 { - status = "okay"; - - tmp75@4a { - compatible = "ti,tmp75"; - reg = <0x4a>; - status = "okay"; - }; - m24128_fru@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <64>; - status = "okay"; - }; -}; - -&pwm_fan { - pinctrl-names = "default"; - pinctrl-0 = < &pwm0_pins &pwm1_pins - &fanin0_pins &fanin1_pins - &fanin2_pins &fanin3_pins - &fanin4_pins &fanin5_pins - &fanin6_pins &fanin7_pins - &fanin8_pins &fanin9_pins - &fanin10_pins &fanin11_pins>; - status = "okay"; - - fan@0 { - reg = <0x00>; - fan-tach-ch = /bits/ 8 <0x00 0x01>; - cooling-levels = <127 255>; - }; - fan@1 { - reg = <0x01>; - fan-tach-ch = /bits/ 8 <0x02 0x03>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@2 { - reg = <0x02>; - fan-tach-ch = /bits/ 8 <0x04 0x05>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@3 { - reg = <0x03>; - fan-tach-ch = /bits/ 8 <0x06 0x07>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@4 { - reg = <0x04>; - fan-tach-ch = /bits/ 8 <0x08 0x09>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@5 { - reg = <0x05>; - fan-tach-ch = /bits/ 8 <0x0A 0x0B>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@6 { - reg = <0x06>; - fan-tach-ch = /bits/ 8 <0x0C 0x0D>; - cooling-levels = /bits/ 8 <127 255>; - }; - fan@7 { - reg = <0x07>; - fan-tach-ch = /bits/ 8 <0x0E 0x0F>; - cooling-levels = /bits/ 8 <127 255>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&watchdog1 { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&adc { - #io-channel-cells = <1>; - status = "okay"; -}; - -&kcs1 { - status = "okay"; -}; - -&kcs2 { - status = "okay"; -}; - -&kcs3 { - status = "okay"; -}; - -&spi0 { - cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - /******* RunBMC inside Module pins *******/ - &gpio0ol_pins - &gpio1ol_pins - &gpio2ol_pins - &gpio3ol_pins - &gpio8o_pins - &gpio9ol_pins - &gpio12ol_pins - &gpio13ol_pins - &gpio14ol_pins - &gpio15ol_pins - &gpio37o_pins - &gpio38_pins - &gpio39_pins - &gpio94ol_pins - &gpio108ol_pins - &gpio109ol_pins - &gpio111ol_pins - &gpio112ol_pins - &gpio113ol_pins - &gpio208_pins - &gpio209ol_pins - &gpio210ol_pins - &gpio211ol_pins - &gpio212ol_pins - &gpio213ol_pins - &gpio214ol_pins - &gpio215ol_pins - &gpio216ol_pins - &gpio217ol_pins - /******* RunBMC outside Connector pins *******/ - &gpio5_pins - &gpio6_pins - &gpio7_pins - &gpio10_pins - &gpio11_pins - &gpio20_pins - &gpio21_pins - &gpio22o_pins - &gpio23_pins - &gpio24_pins - &gpio25_pins - &gpio30_pins - &gpio31_pins - &gpio40o_pins - &gpio59_pins - &gpio76_pins - &gpio77_pins - &gpio78o_pins - &gpio79_pins - &gpio82_pins - &gpio83_pins - &gpio84_pins - &gpio85o_pins - &gpio86ol_pins - &gpio87_pins - &gpio88_pins - &gpio89_pins - &gpio90_pins - &gpio93_pins - &gpio114o_pins - &gpio115_pins - &gpio120_pins - &gpio121_pins - &gpio122_pins - &gpio123_pins - &gpio124_pins - &gpio125_pins - &gpio126_pins - &gpio127o_pins - &gpio136_pins - &gpio137_pins - &gpio138_pins - &gpio139_pins - &gpio140_pins - &gpio141_pins - &gpio142_pins - &gpio143_pins - &gpio144_pins - &gpio146_pins - &gpio145_pins - &gpio147_pins - &gpio153o_pins - &gpio155_pins - &gpio160o_pins - &gpio169o_pins - &gpio188o_pins - &gpio189_pins - &gpio196_pins - &gpio197_pins - &gpio198o_pins - &gpio199o_pins - &gpio200_pins - &gpio202_pins - &gpio203o_pins - &gpio224_pins - &gpio225ol_pins - &gpio226ol_pins - &gpio227ol_pins - &gpio228o_pins - &gpio229o_pins - &gpio230_pins - &gpio231o_pins - &ddc_pins - &wdog1_pins - &wdog2_pins - >; -}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi deleted file mode 100644 index 30eed40b89b5..000000000000 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com -// Copyright 2018 Google, Inc. - -#include "nuvoton-common-npcm7xx.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "nuvoton,npcm750-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk NPCM7XX_CLK_CPU>; - clock-names = "clk_cpu"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk NPCM7XX_CLK_CPU>; - clock-names = "clk_cpu"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - soc { - timer@3fe600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x3fe600 0x20>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_AHB>; - }; - }; - - ahb { - gmac1: eth@f0804000 { - device_type = "network"; - compatible = "snps,dwmac"; - reg = <0xf0804000 0x2000>; - interrupts = ; - interrupt-names = "macirq"; - ethernet = <1>; - clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; - clock-names = "stmmaceth", "clk_gmac"; - pinctrl-names = "default"; - pinctrl-0 = <&rg2_pins - &rg2mdio_pins>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts deleted file mode 100644 index b78c116cbc18..000000000000 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -// Copyright 2021 Jonathan Neuschäfer - -/dts-v1/; - -/* The last 16 MiB are dedicated to the GPU */ -/memreserve/ 0x07000000 0x01000000; - -#include "nuvoton-wpcm450.dtsi" - -#include -#include - -/ { - model = "Supermicro X9SCi-LN4F BMC"; - compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x08000000>; /* 128 MiB */ - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins>; - - uid { - label = "UID button"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - uid { - label = "UID"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - heartbeat { - label = "heartbeat"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fiu { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - }; -}; - -&gpio0 { - gpio-line-names = - /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "", - /* 8 */ "", "", "", "", "power-chassis-control-n", "", "uid-button", ""; -}; - -&gpio1 { - gpio-line-names = - /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid", - /* 8 */ "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - /* 0 */ "", "", "", "", "", "", "", "", - /* 8 */ "", "", "", "", "", "", "", "power-chassis-good"; -}; - -&pinctrl { - key_pins: mux-keys { - groups = "gspi", "sspi"; - function = "gpio"; - }; - - led_pins: mux-leds { - groups = "hg3", "hg0", "pwm4"; - function = "gpio"; - }; -}; - -&serial0 { - /* - * Debug serial port. TX is exposed on the right pad of unpopulated - * resistor R1247, RX on the right pad of R1162. - */ - status = "okay"; -}; - -&serial1 { - /* "Serial over LAN" port. Connected to ttyS2 of the host system. */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi deleted file mode 100644 index fd671c7a1e5d..000000000000 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ /dev/null @@ -1,493 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -// Copyright 2021 Jonathan Neuschäfer - -#include - -/ { - compatible = "nuvoton,wpcm450"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - refclk: clock-48mhz { - /* 48 MHz reference oscillator */ - compatible = "fixed-clock"; - clock-output-names = "ref"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&aic>; - ranges; - - gcr: syscon@b0000000 { - compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; - reg = <0xb0000000 0x200>; - }; - - clk: clock-controller@b0000200 { - compatible = "nuvoton,wpcm450-clk"; - reg = <0xb0000200 0x100>; - clocks = <&refclk>; - clock-names = "ref"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - serial0: serial@b8000000 { - compatible = "nuvoton,wpcm450-uart"; - reg = <0xb8000000 0x20>; - reg-shift = <2>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; - pinctrl-names = "default"; - pinctrl-0 = <&bsp_pins>; - status = "disabled"; - }; - - serial1: serial@b8000100 { - compatible = "nuvoton,wpcm450-uart"; - reg = <0xb8000100 0x20>; - reg-shift = <2>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; - status = "disabled"; - }; - - timer0: timer@b8001000 { - compatible = "nuvoton,wpcm450-timer"; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; - }; - - watchdog0: watchdog@b800101c { - compatible = "nuvoton,wpcm450-wdt"; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb800101c 0x4>; - clocks = <&clk24m>; - }; - - aic: interrupt-controller@b8002000 { - compatible = "nuvoton,wpcm450-aic"; - reg = <0xb8002000 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pinctrl: pinctrl@b8003000 { - compatible = "nuvoton,wpcm450-pinctrl"; - reg = <0xb8003000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio0: gpio@0 { - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <3 IRQ_TYPE_LEVEL_HIGH>, - <4 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - }; - - gpio1: gpio@1 { - reg = <1>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - }; - - gpio2: gpio@2 { - reg = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio3: gpio@3 { - reg = <3>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio4: gpio@4 { - reg = <4>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio5: gpio@5 { - reg = <5>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio6: gpio@6 { - reg = <6>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio7: gpio@7 { - reg = <7>; - gpio-controller; - #gpio-cells = <2>; - }; - - smb3_pins: mux-smb3 { - groups = "smb3"; - function = "smb3"; - }; - - smb4_pins: mux-smb4 { - groups = "smb4"; - function = "smb4"; - }; - - smb5_pins: mux-smb5 { - groups = "smb5"; - function = "smb5"; - }; - - scs1_pins: mux-scs1 { - groups = "scs1"; - function = "scs1"; - }; - - scs2_pins: mux-scs2 { - groups = "scs2"; - function = "scs2"; - }; - - scs3_pins: mux-scs3 { - groups = "scs3"; - function = "scs3"; - }; - - smb0_pins: mux-smb0 { - groups = "smb0"; - function = "smb0"; - }; - - smb1_pins: mux-smb1 { - groups = "smb1"; - function = "smb1"; - }; - - smb2_pins: mux-smb2 { - groups = "smb2"; - function = "smb2"; - }; - - bsp_pins: mux-bsp { - groups = "bsp"; - function = "bsp"; - }; - - hsp1_pins: mux-hsp1 { - groups = "hsp1"; - function = "hsp1"; - }; - - hsp2_pins: mux-hsp2 { - groups = "hsp2"; - function = "hsp2"; - }; - - r1err_pins: mux-r1err { - groups = "r1err"; - function = "r1err"; - }; - - r1md_pins: mux-r1md { - groups = "r1md"; - function = "r1md"; - }; - - rmii2_pins: mux-rmii2 { - groups = "rmii2"; - function = "rmii2"; - }; - - r2err_pins: mux-r2err { - groups = "r2err"; - function = "r2err"; - }; - - r2md_pins: mux-r2md { - groups = "r2md"; - function = "r2md"; - }; - - kbcc_pins: mux-kbcc { - groups = "kbcc"; - function = "kbcc"; - }; - - dvo0_pins: mux-dvo0 { - groups = "dvo"; - function = "dvo0"; - }; - - dvo3_pins: mux-dvo3 { - groups = "dvo"; - function = "dvo3"; - }; - - clko_pins: mux-clko { - groups = "clko"; - function = "clko"; - }; - - smi_pins: mux-smi { - groups = "smi"; - function = "smi"; - }; - - uinc_pins: mux-uinc { - groups = "uinc"; - function = "uinc"; - }; - - gspi_pins: mux-gspi { - groups = "gspi"; - function = "gspi"; - }; - - mben_pins: mux-mben { - groups = "mben"; - function = "mben"; - }; - - xcs2_pins: mux-xcs2 { - groups = "xcs2"; - function = "xcs2"; - }; - - xcs1_pins: mux-xcs1 { - groups = "xcs1"; - function = "xcs1"; - }; - - sdio_pins: mux-sdio { - groups = "sdio"; - function = "sdio"; - }; - - sspi_pins: mux-sspi { - groups = "sspi"; - function = "sspi"; - }; - - fi0_pins: mux-fi0 { - groups = "fi0"; - function = "fi0"; - }; - - fi1_pins: mux-fi1 { - groups = "fi1"; - function = "fi1"; - }; - - fi2_pins: mux-fi2 { - groups = "fi2"; - function = "fi2"; - }; - - fi3_pins: mux-fi3 { - groups = "fi3"; - function = "fi3"; - }; - - fi4_pins: mux-fi4 { - groups = "fi4"; - function = "fi4"; - }; - - fi5_pins: mux-fi5 { - groups = "fi5"; - function = "fi5"; - }; - - fi6_pins: mux-fi6 { - groups = "fi6"; - function = "fi6"; - }; - - fi7_pins: mux-fi7 { - groups = "fi7"; - function = "fi7"; - }; - - fi8_pins: mux-fi8 { - groups = "fi8"; - function = "fi8"; - }; - - fi9_pins: mux-fi9 { - groups = "fi9"; - function = "fi9"; - }; - - fi10_pins: mux-fi10 { - groups = "fi10"; - function = "fi10"; - }; - - fi11_pins: mux-fi11 { - groups = "fi11"; - function = "fi11"; - }; - - fi12_pins: mux-fi12 { - groups = "fi12"; - function = "fi12"; - }; - - fi13_pins: mux-fi13 { - groups = "fi13"; - function = "fi13"; - }; - - fi14_pins: mux-fi14 { - groups = "fi14"; - function = "fi14"; - }; - - fi15_pins: mux-fi15 { - groups = "fi15"; - function = "fi15"; - }; - - pwm0_pins: mux-pwm0 { - groups = "pwm0"; - function = "pwm0"; - }; - - pwm1_pins: mux-pwm1 { - groups = "pwm1"; - function = "pwm1"; - }; - - pwm2_pins: mux-pwm2 { - groups = "pwm2"; - function = "pwm2"; - }; - - pwm3_pins: mux-pwm3 { - groups = "pwm3"; - function = "pwm3"; - }; - - pwm4_pins: mux-pwm4 { - groups = "pwm4"; - function = "pwm4"; - }; - - pwm5_pins: mux-pwm5 { - groups = "pwm5"; - function = "pwm5"; - }; - - pwm6_pins: mux-pwm6 { - groups = "pwm6"; - function = "pwm6"; - }; - - pwm7_pins: mux-pwm7 { - groups = "pwm7"; - function = "pwm7"; - }; - - hg0_pins: mux-hg0 { - groups = "hg0"; - function = "hg0"; - }; - - hg1_pins: mux-hg1 { - groups = "hg1"; - function = "hg1"; - }; - - hg2_pins: mux-hg2 { - groups = "hg2"; - function = "hg2"; - }; - - hg3_pins: mux-hg3 { - groups = "hg3"; - function = "hg3"; - }; - - hg4_pins: mux-hg4 { - groups = "hg4"; - function = "hg4"; - }; - - hg5_pins: mux-hg5 { - groups = "hg5"; - function = "hg5"; - }; - - hg6_pins: mux-hg6 { - groups = "hg6"; - function = "hg6"; - }; - - hg7_pins: mux-hg7 { - groups = "hg7"; - function = "hg7"; - }; - }; - - fiu: spi-controller@c8000000 { - compatible = "nuvoton,wpcm450-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; - reg-names = "control", "memory"; - clocks = <&clk 0>; - nuvoton,shm = <&shm>; - status = "disabled"; - }; - - shm: syscon@c8001000 { - compatible = "nuvoton,wpcm450-shm", "syscon"; - reg = <0xc8001000 0x1000>; - reg-io-width = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/nuvoton/Makefile b/arch/arm/boot/dts/nuvoton/Makefile new file mode 100644 index 000000000000..89c157dad312 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NPCM7XX) += \ + nuvoton-npcm730-gsj.dtb \ + nuvoton-npcm730-gbs.dtb \ + nuvoton-npcm730-kudo.dtb \ + nuvoton-npcm750-evb.dtb \ + nuvoton-npcm750-runbmc-olympus.dtb +dtb-$(CONFIG_ARCH_WPCM450) += \ + nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi new file mode 100644 index 000000000000..c7b5ef15b716 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + /* external reference clock */ + clk_refclk: clk_refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk_sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk_mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk_rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk_rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00900000>; + + scu: scu@3fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x3fe000 0x1000>; + }; + + l2: cache-controller@3fc000 { + compatible = "arm,pl310-cache"; + reg = <0x3fc000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + clocks = <&clk NPCM7XX_CLK_AXI>; + arm,shared-override; + }; + + gic: interrupt-controller@3ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x3ff000 0x1000>, + <0x3fe100 0x100>; + }; + + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + }; + + rst: rst@801000 { + compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + reg = <0x801000 0x6C>; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + rstc: rstc@f0801000 { + compatible = "nuvoton,npcm750-reset"; + reg = <0xf0801000 0x70>; + #reset-cells = <2>; + nuvoton,sysgcr = <&gcr>; + }; + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk", "syscon"; + #clock-cells = <1>; + clock-controller; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + + gmac0: eth@f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg1_pins + &rg1mdio_pins>; + status = "disabled"; + }; + + ehci1: usb@f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = ; + status = "disabled"; + }; + + fiu0: spi@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPI0>; + clock-names = "clk_spi0"; + status = "disabled"; + }; + + fiu3: spi@c0000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPI3>; + clock-names = "clk_spi3"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + status = "disabled"; + }; + + fiux: spi@fb001000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb001000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPIX>; + clock-names = "clk_spix"; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00300000>; + + lpc_kcs: lpc_kcs@7000 { + compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; + reg = <0x7000 0x40>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x40>; + + kcs1: kcs1@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <1>; + status = "disabled"; + }; + + kcs2: kcs2@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <2>; + status = "disabled"; + }; + + kcs3: kcs3@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <3>; + status = "disabled"; + }; + }; + + spi0: spi@200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + status = "disabled"; + }; + + spi1: spi@201000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x201000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi2_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; + status = "disabled"; + }; + + timer0: timer@8000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = ; + reg = <0x8000 0x1C>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog0: watchdog@801C { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0x801C 0x4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog1: watchdog@901C { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0x901C 0x4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog2: watchdog@a01C { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xa01C 0x4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + serial0: serial@1000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x1000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial1: serial@2000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x2000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial2: serial@3000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x3000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial3: serial@4000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x4000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + rng: rng@b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xb000 0x8>; + status = "disabled"; + }; + + adc: adc@c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xc000 0x8>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_ADC>; + resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; + status = "disabled"; + }; + + pwm_fan: pwm-fan-controller@103000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,npcm750-pwm-fan"; + reg = <0x103000 0x2000>, <0x180000 0x8000>; + reg-names = "pwm", "fan"; + clocks = <&clk NPCM7XX_CLK_APB3>, + <&clk NPCM7XX_CLK_APB4>; + clock-names = "pwm","fan"; + interrupts = , + , + , + , + , + , + , + ; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins + &fanin12_pins &fanin13_pins + &fanin14_pins &fanin15_pins>; + status = "disabled"; + }; + + i2c0: i2c@80000 { + reg = <0x80000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + + i2c1: i2c@81000 { + reg = <0x81000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + + i2c2: i2c@82000 { + reg = <0x82000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + + i2c3: i2c@83000 { + reg = <0x83000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + + i2c4: i2c@84000 { + reg = <0x84000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + + i2c5: i2c@85000 { + reg = <0x85000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + + i2c6: i2c@86000 { + reg = <0x86000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + + i2c7: i2c@87000 { + reg = <0x87000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + + i2c8: i2c@88000 { + reg = <0x88000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + + i2c9: i2c@89000 { + reg = <0x89000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + + i2c10: i2c@8a000 { + reg = <0x8a000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + + i2c11: i2c@8b000 { + reg = <0x8b000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + + i2c12: i2c@8c000 { + reg = <0x8c000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + + i2c13: i2c@8d000 { + reg = <0x8d000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + + i2c14: i2c@8e000 { + reg = <0x8e000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + + i2c15: i2c@8f000 { + reg = <0x8f000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; + }; + }; + + pinctrl: pinctrl@f0800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; + ranges = <0 0xf0010000 0x8000>; + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + gpio1: gpio@f0011000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 32 32>; + }; + gpio2: gpio@f0012000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 64 32>; + }; + gpio3: gpio@f0013000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x3000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 96 32>; + }; + gpio4: gpio@f0014000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x4000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 128 32>; + }; + gpio5: gpio@f0015000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x5000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 160 32>; + }; + gpio6: gpio@f0016000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x6000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 192 32>; + }; + gpio7: gpio@f0017000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 224 32>; + }; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2-pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den-pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b-pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d-pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0cs2_pins: spi0cs2-pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3-pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c-pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a-pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1-pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2-pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1-pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2-pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b-pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d-pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc-pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1-pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio-pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2-pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8-pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-pins { + groups = "serirq"; + function = "serirq"; + }; + lpcclk_pins: lpcclk-pins { + groups = "lpcclk"; + function = "lpcclk"; + }; + scipme_pins: scipme-pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci-pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6-pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7-pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1-pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx-pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b-pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc-pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio-pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1-pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-pins { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-pins { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-pins { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-pins { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-pins { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-pins { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-pins { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-pins { + groups = "hgpio7"; + function = "hgpio7"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts new file mode 100644 index 000000000000..9e9eba8bad5e --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts @@ -0,0 +1,1135 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Quanta Computer Inc. George.Hung@quantatw.com + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" +#include + +/ { + model = "Quanta GBS Board (Device Tree)"; + compatible = "quanta,gbs-bmc","nuvoton,npcm730"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + i2c16 = &i2c0_slotPE0_0; + i2c17 = &i2c0_slotPE1_1; + i2c18 = &i2c0_slotUSB_2; + i2c19 = &i2c0_3; + i2c20 = &i2c5_i2cool_0; + i2c21 = &i2c5_i2cool_1; + i2c22 = &i2c5_i2cool_2; + i2c23 = &i2c5_hsbp_fru_3; + i2c24 = &i2c6_u2_15_0; + i2c25 = &i2c6_u2_14_1; + i2c26 = &i2c6_u2_13_2; + i2c27 = &i2c6_u2_12_3; + i2c28 = &i2c7_u2_11_0; + i2c29 = &i2c7_u2_10_1; + i2c30 = &i2c7_u2_9_2; + i2c31 = &i2c7_u2_8_3; + i2c32 = &i2c9_vddcr_cpu; + i2c33 = &i2c9_vddcr_soc; + i2c34 = &i2c9_vddio_efgh; + i2c35 = &i2c9_vddio_abcd; + i2c36 = &i2c10_u2_7_0; + i2c37 = &i2c10_u2_6_1; + i2c38 = &i2c10_u2_5_2; + i2c39 = &i2c10_u2_4_3; + i2c40 = &i2c11_clk_buf0_0; + i2c41 = &i2c11_clk_buf1_1; + i2c42 = &i2c11_clk_buf2_2; + i2c43 = &i2c11_clk_buf3_3; + i2c44 = &i2c14_u2_3_0; + i2c45 = &i2c14_u2_2_1; + i2c46 = &i2c14_u2_1_2; + i2c47 = &i2c14_u2_0_3; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial0; + }; + + memory { + reg = <0 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + sas-cable0 { + label = "sas-cable0"; + gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + linux,code = <73>; + }; + + sas-cable1 { + label = "sas-cable1"; + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + linux,code = <72>; + }; + + sas-cable2 { + label = "sas-cable2"; + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + linux,code = <71>; + }; + + sas-cable3 { + label = "sas-cable3"; + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + linux,code = <70>; + }; + + sata0 { + label = "sata0"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + hsbp-cable { + label = "hsbp-cable"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + linux,code = <57>; + }; + + fanbd-cable { + label = "fanbd-cable"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + linux,code = <58>; + }; + + bp12v-cable { + label = "bp12v-cable"; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + linux,code = <69>; + }; + + pe-slot0 { + label = "pe-slot0"; + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + linux,code = <120>; + }; + + pe-slot1 { + label = "pe-slot1"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + linux,code = <121>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 1>, <&adc 2>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 0>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { /* gpio153 */ + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + attention { /* gpio215 */ + gpios = <&gpio6 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + sys_boot_status { /* gpio216 */ + gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + retain-state-shutdown; + }; + + bmc_fault { /* gpio217 */ + gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "panic"; + panic-indicator; + }; + + led_u2_0_locate { + gpios = <&pca9535_ledlocate 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_1_locate { + gpios = <&pca9535_ledlocate 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_2_locate { + gpios = <&pca9535_ledlocate 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_3_locate { + gpios = <&pca9535_ledlocate 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_4_locate { + gpios = <&pca9535_ledlocate 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_5_locate { + gpios = <&pca9535_ledlocate 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_6_locate { + gpios = <&pca9535_ledlocate 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_7_locate { + gpios = <&pca9535_ledlocate 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_8_locate { + gpios = <&pca9535_ledlocate 11 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_9_locate { + gpios = <&pca9535_ledlocate 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_10_locate { + gpios = <&pca9535_ledlocate 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_11_locate { + gpios = <&pca9535_ledlocate 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_12_locate { + gpios = <&pca9535_ledlocate 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_13_locate { + gpios = <&pca9535_ledlocate 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_14_locate { + gpios = <&pca9535_ledlocate 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_15_locate { + gpios = <&pca9535_ledlocate 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_0_fault { + gpios = <&pca9535_ledfault 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_1_fault { + gpios = <&pca9535_ledfault 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_2_fault { + gpios = <&pca9535_ledfault 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_3_fault { + gpios = <&pca9535_ledfault 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_4_fault { + gpios = <&pca9535_ledfault 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_5_fault { + gpios = <&pca9535_ledfault 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_6_fault { + gpios = <&pca9535_ledfault 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_7_fault { + gpios = <&pca9535_ledfault 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_8_fault { + gpios = <&pca9535_ledfault 11 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_9_fault { + gpios = <&pca9535_ledfault 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_10_fault { + gpios = <&pca9535_ledfault 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_11_fault { + gpios = <&pca9535_ledfault 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_12_fault { + gpios = <&pca9535_ledfault 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_13_fault { + gpios = <&pca9535_ledfault 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_14_fault { + gpios = <&pca9535_ledfault 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_u2_15_fault { + gpios = <&pca9535_ledfault 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + }; + + seven-seg-disp { + compatible = "seven-seg-gpio-dev"; + refresh-interval-ms = /bits/ 16 <600>; + clock-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + data-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + clear-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + pcie-slot { + pcie1: pcie-slot@1 { + label = "PE0"; + }; + pcie2: pcie-slot@2 { + label = "PE1"; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <2>; + label = "bmc"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0xf0000>; + }; + image-descriptor@f0000 { + label = "image-descriptor"; + reg = <0xf0000 0x10000>; + }; + hoth-update@100000 { + label = "hoth-update"; + reg = <0x100000 0x100000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; + }; + rofs@700000 { + label = "rofs"; + reg = <0x700000 0x35f0000>; + }; + rwfs@3cf0000 { + label = "rwfs"; + reg = <0x3cf0000 0x300000>; + }; + hoth-mailbox@3ff0000 { + label = "hoth-mailbox"; + reg = <0x3ff0000 0x10000>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + label = "pnor"; + }; + flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + }; +}; + +&gcr { + serial_port_mux: uart-mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; /* Serial port mode 3 (takeover) */ + }; + + uart1_mode_mux: uart1-mode-mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x64 0x01000000>; + idle-states = <0>; /* Set UART1 mode to normal (follow SPMOD) */ + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + snps,eee-force-disable; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&lpc_kcs { + kcs1: kcs1@0 { + status = "okay"; + }; + + kcs2: kcs2@0 { + status = "okay"; + }; + + kcs3: kcs3@0 { + status = "okay"; + }; +}; + +&spi1 { + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* dummy - gpio147 */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio224ol_pins &gpio227o_pins + &gpio228_pins>; + status = "okay"; + + jtag_master@0 { + compatible = "nuvoton,npcm750-jtag-master"; + spi-max-frequency = <25000000>; + reg = <0>; + status = "okay"; + + pinctrl-names = "pspi", "gpio"; + pinctrl-0 = <&pspi2_pins>; + pinctrl-1 = <&gpio224ol_pins &gpio227o_pins + &gpio228_pins>; + + tck-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + tdi-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + tdo-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + tms-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + + i2c0_slotPE0_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + pcie-slot = &pcie1; + }; + + i2c0_slotPE1_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + pcie-slot = &pcie2; + }; + + i2c0_slotUSB_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + pca9535_ifdet: pca9535-ifdet@24 { + compatible = "nxp,pca9535"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9535_pwren: pca9535-pwren@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "pwr_u2_3_en","pwr_u2_2_en", + "pwr_u2_1_en","pwr_u2_0_en", + "pwr_u2_7_en","pwr_u2_6_en", + "pwr_u2_5_en","pwr_u2_4_en", + "pwr_u2_11_en","pwr_u2_10_en", + "pwr_u2_9_en","pwr_u2_8_en", + "pwr_u2_15_en","pwr_u2_14_en", + "pwr_u2_13_en","pwr_u2_12_en"; + }; + + pca9535_pwrgd: pca9535-pwrgd@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9535_ledlocate: pca9535-ledlocate@22 { + compatible = "nxp,pca9535"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + }; + + pca9535_ledfault: pca9535-ledfault@23 { + compatible = "nxp,pca9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + + }; + + pca9535_pwrdisable: pca9535-pwrdisable@25 { + compatible = "nxp,pca9535"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "u2_3_pwr_dis","u2_2_pwr_dis", + "u2_1_pwr_dis","u2_0_pwr_dis", + "u2_7_pwr_dis","u2_6_pwr_dis", + "u2_5_pwr_dis","u2_4_pwr_dis", + "u2_11_pwr_dis","u2_10_pwr_dis", + "u2_9_pwr_dis","u2_8_pwr_dis", + "u2_15_pwr_dis","u2_14_pwr_dis", + "u2_13_pwr_dis","u2_12_pwr_dis"; + }; + + pca9535_perst: pca9535-perst@26 { + compatible = "nxp,pca9535"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "u2_15_perst","u2_14_perst", + "u2_13_perst","u2_12_perst", + "u2_11_perst","u2_10_perst", + "u2_9_perst","u2_8_perst", + "u2_7_perst","u2_6_perst", + "u2_5_perst","u2_4_perst", + "u2_3_perst","u2_2_perst", + "u2_1_perst","u2_0_perst"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; +}; + +&i2c5 { + clock-frequency = <100000>; + status = "okay"; + + mb_fru@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + i2c5_i2cool_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + max31725@54 { + compatible = "maxim,max31725"; + reg = <0x54>; + status = "okay"; + }; + }; + + i2c5_i2cool_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + max31725@55 { + compatible = "maxim,max31725"; + reg = <0x55>; + status = "okay"; + }; + }; + + i2c5_i2cool_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + max31725@5d { + compatible = "maxim,max31725"; + reg = <0x5d>; + status = "okay"; + }; + fan_fru@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + + i2c5_hsbp_fru_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + hsbp_fru@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + status = "okay"; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@73 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + i2c6_u2_15_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c6_u2_14_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c6_u2_13_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c6_u2_12_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@72 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + i2c7_u2_11_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c7_u2_10_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c7_u2_9_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c7_u2_8_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c8 { + clock-frequency = <100000>; + status = "okay"; + + i2c8_adm1272: adm1272@10 { + compatible = "adi,adm1272"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + shunt-resistor-micro-ohms = <300>; + }; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + + i2c9_vddcr_cpu: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + }; + + i2c9_vddcr_soc: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + vrm@61 { + compatible = "isil,isl68137"; + reg = <0x61>; + }; + }; + + i2c9_vddio_efgh: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + vrm@63 { + compatible = "isil,isl68137"; + reg = <0x63>; + }; + }; + + i2c9_vddio_abcd: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + vrm@45 { + compatible = "isil,isl68137"; + reg = <0x45>; + }; + }; + }; +}; + +&i2c10 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + i2c10_u2_7_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c10_u2_6_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c10_u2_5_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c10_u2_4_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c11 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@76 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + i2c11_clk_buf0_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c11_clk_buf1_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c11_clk_buf2_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c11_clk_buf3_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c12 { + clock-frequency = <100000>; + status = "okay"; + + max34451@4e { + compatible = "maxim,max34451"; + reg = <0x4e>; + }; + vrm@5d { + compatible = "isil,isl68137"; + reg = <0x5d>; + }; + vrm@5e { + compatible = "isil,isl68137"; + reg = <0x5e>; + }; +}; + +&i2c13 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c14 { + clock-frequency = <100000>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c14_u2_3_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c14_u2_2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c14_u2_1_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c14_u2_0_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = < + &pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins + >; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x01>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x02>; + }; + fan@3 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x04>; + }; + fan@4 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x03>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + + gpio0: gpio@f0010000 { + /* POWER_OUT=gpio07, RESET_OUT=gpio06, PS_PWROK=gpio13 */ + gpio-line-names = + /*0-31*/ + "","","","","","","RESET_OUT","POWER_OUT", + "","","","","","PS_PWROK","","", + "","","","","","","","", + "","","","","","","",""; + }; + gpio1: gpio@f0011000 { + /* SIO_POWER_GOOD=gpio59 */ + gpio-line-names = + /*32-63*/ + "","","","","","","","", + "","","","","","","","", + "","","","","","","","", + "","","","SIO_POWER_GOOD","","","",""; + }; + gpio2: gpio@f0012000 { + bmc_usb_mux_oe_n { + gpio-hog; + gpios = <25 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "bmc-usb-mux-oe-n"; + }; + bmc_usb_mux_sel { + gpio-hog; + gpios = <26 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "bmc-usb-mux-sel"; + }; + bmc_usb2517_reset_n { + gpio-hog; + gpios = <27 GPIO_ACTIVE_LOW>; + output-low; + line-name = "bmc-usb2517-reset-n"; + }; + }; + gpio3: gpio@f0013000 { + assert_cpu0_reset { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "assert-cpu0-reset"; + }; + assert_pwrok_cpu0_n { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "assert-pwrok-cpu0-n"; + }; + assert_cpu0_prochot { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "assert-cpu0-prochot"; + }; + }; + gpio4: gpio@f0014000 { + /* POST_COMPLETE=gpio143 */ + gpio-line-names = + /*128-159*/ + "","","","","","","","", + "","","","","","","","POST_COMPLETE", + "","","","","","","","", + "","","","","","","",""; + }; + gpio5: gpio@f0015000 { + /* POWER_BUTTON=gpio177 */ + gpio-line-names = + /*160-191*/ + "","","","","","","","", + "","","","","","","","", + "","POWER_BUTTON","","","","","","", + "","","","","","","",""; + }; + gpio6: gpio@f0016000 { + /* SIO_S5=gpio199, RESET_BUTTON=gpio203 */ + gpio-line-names = + /*192-223*/ + "","","","","","","","SIO_S5", + "","","","RESET_BUTTON","","","","", + "","","","","","","","", + "","","","","","","",""; + }; + + gpio224ol_pins: gpio224ol-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + output-low; + }; + gpio227o_pins: gpio227o-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-high; + }; + gpio228_pins: gpio228-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + input-enable; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi new file mode 100644 index 000000000000..53cfd15fa03f --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0pp_pins: gpio0pp-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + drive-push-pull; + }; + gpio1pp_pins: gpio1pp-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + drive-push-pull; + }; + gpio2pp_pins: gpio2pp-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + drive-push-pull; + }; + gpio3pp_pins: gpio3pp-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + drive-push-pull; + }; + gpio4pp_pins: gpio4pp-pins { + pins = "GPIO4/IOX2DI/SMB1DSDA"; + bias-disable; + drive-push-pull; + }; + gpio5pp_pins: gpio5pp-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + drive-push-pull; + }; + gpio6pp_pins: gpio6pp-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + drive-push-pull; + }; + gpio7pp_pins: gpio7pp-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + drive-push-pull; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + input-enable; + }; + gpio10pp_pins: gpio10pp-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + drive-push-pull; + }; + gpio11pp_pins: gpio11pp-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + drive-push-pull; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + input-enable; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + input-enable; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + input-enable; + }; + gpio15od_pins: gpio15od-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + drive-open-drain; + }; + gpio17pp_pins: gpio17pp-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + drive-push-pull; + }; + gpio18pp_pins: gpio18pp-pins { + pins = "GPIO18/PSPI2D0/SMB4BSDA"; + bias-disable; + drive-push-pull; + }; + gpio19pp_pins: gpio19pp-pins { + pins = "GPIO19/PSPI2CK/SMB4BSCL"; + bias-disable; + drive-push-pull; + }; + gpio24pp_pins: gpio24pp-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + drive-push-pull; + }; + gpio25pp_pins: gpio25pp-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + drive-push-pull; + }; + gpio37od_pins: gpio37od-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + drive-open-drain; + }; + gpio59pp_pins: gpio59pp-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + drive-push-pull; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + input-enable; + }; + gpio72od_pins: gpio72od-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + drive-open-drain; + }; + gpio73od_pins: gpio73od-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + drive-open-drain; + }; + gpio74od_pins: gpio74od-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + drive-open-drain; + }; + gpio75od_pins: gpio75od-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + drive-open-drain; + }; + gpio76od_pins: gpio76od-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + drive-open-drain; + }; + gpio77od_pins: gpio77od-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + drive-open-drain; + }; + gpio78od_pins: gpio78od-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + drive-open-drain; + }; + gpio79od_pins: gpio79od-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + drive-open-drain; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84pp_pins: gpio84pp-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + drive-push-pull; + }; + gpio85pp_pins: gpio85pp-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + drive-push-pull; + }; + gpio86pp_pins: gpio86pp-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + drive-push-pull; + }; + gpio87pp_pins: gpio87pp-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + drive-push-pull; + }; + gpio88pp_pins: gpio88pp-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + drive-push-pull; + }; + gpio89pp_pins: gpio89pp-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + drive-push-pull; + }; + gpio90pp_pins: gpio90pp-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + drive-push-pull; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + input-enable; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + input-enable; + }; + gpio93pp_pins: gpio93pp-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + drive-push-pull; + }; + gpio94pp_pins: gpio94pp-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + drive-push-pull; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio125pp_pins: gpio125pp-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + drive-push-pull; + }; + gpio126od_pins: gpio126od-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + drive-open-drain; + }; + gpio127od_pins: gpio127od-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + drive-open-drain; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142od_pins: gpio142od-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + drive-open-drain; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + input-enable; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + input-enable; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + input-enable; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + input-enable; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + input-enable; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + input-enable; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMCCMD"; + bias-disable; + input-enable; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMCDT0"; + bias-disable; + input-enable; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + input-enable; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + input-enable; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + input-enable; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/LAD0/ESPI_IO0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/LAD1/ESPI_IO1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/LAD2/ESPI_IO2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + gpio175od_pins: gpio175od-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + drive-open-drain; + }; + gpio176od_pins: gpio176od-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + drive-open-drain; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + input-enable; + }; + gpio190od_pins: gpio190od-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + drive-open-drain; + }; + gpio191_pins: gpio191-pins { + pins = "GPIO191"; + bias-disable; + input-enable; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192"; + bias-disable; + input-enable; + }; + gpio194pp_pins: gpio194pp-pins { + pins = "GPIO194/SMB0BSCL"; + bias-disable; + drive-push-pull; + }; + gpio195od_pins: gpio195od-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + drive-open-drain; + }; + gpio196od_pins: gpio196od-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + drive-open-drain; + }; + gpio197od_pins: gpio197od-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + drive-open-drain; + }; + gpio198od_pins: gpio198od-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + drive-open-drain; + }; + gpio199od_pins: gpio199od-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + drive-open-drain; + }; + gpio200pp_pins: gpio200pp-pins { + pins = "GPIO200/R2CK"; + bias-disable; + drive-push-pull; + }; + gpio202od_pins: gpio202od-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + drive-open-drain; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + input-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts new file mode 100644 index 000000000000..2a394cc15284 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" +#include "nuvoton-npcm730-gsj-gpio.dtsi" + +#include + +/ { + model = "Quanta GSJ Board (Device Tree v12)"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet1 = &gmac0; + serial3 = &serial3; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c15 = &i2c15; + fiu0 = &fiu0; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-bmc-live { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + LED_U2_0_LOCATE { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_LOCATE { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_LOCATE { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_LOCATE { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_LOCATE { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_LOCATE { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_BMC_TRAY_PWRGD { + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_FAULT { + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_LOCATE { + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_LOCATE { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_0_FAULT { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_FAULT { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_FAULT { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_FAULT { + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_FAULT { + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_FAULT { + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_FAULT { + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1400000>; + }; + rwfs@1c00000 { + label = "rwfs"; + reg = <0x1c00000 0x300000>; + }; + reserved@1f00000 { + label = "reserved"; + reg = <0x1f00000 0x100000>; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + }; +}; + +&i2c4 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; +}; + +&i2c11 { + status = "okay"; + + /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ + power-brick@36 { + compatible = "delta,dps800"; + reg = <0x36>; + }; + + hotswap@15 { + compatible = "ti,lm5066i"; + reg = <0x15>; + }; +}; + +&i2c12 { + status = "okay"; + + ucd90160@6b { + compatible = "ti,ucd90160"; + reg = <0x6b>; + }; +}; + +&i2c15 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c_u20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_u21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_u22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_u23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_u24: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_u25: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_u26: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c_u27: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /* GPI pins*/ + &gpio8_pins + &gpio9_pins + &gpio12_pins + &gpio13_pins + &gpio14_pins + &gpio60_pins + &gpio83_pins + &gpio91_pins + &gpio92_pins + &gpio95_pins + &gpio136_pins + &gpio137_pins + &gpio141_pins + &gpio144_pins + &gpio145_pins + &gpio146_pins + &gpio147_pins + &gpio148_pins + &gpio149_pins + &gpio150_pins + &gpio151_pins + &gpio152_pins + &gpio153_pins + &gpio154_pins + &gpio155_pins + &gpio156_pins + &gpio157_pins + &gpio158_pins + &gpio159_pins + &gpio161_pins + &gpio162_pins + &gpio163_pins + &gpio164_pins + &gpio165_pins + &gpio166_pins + &gpio167_pins + &gpio168_pins + &gpio169_pins + &gpio170_pins + &gpio177_pins + &gpio191_pins + &gpio192_pins + &gpio203_pins + /* GPO pins*/ + &gpio0pp_pins + &gpio1pp_pins + &gpio2pp_pins + &gpio3pp_pins + &gpio4pp_pins + &gpio5pp_pins + &gpio6pp_pins + &gpio7pp_pins + &gpio10pp_pins + &gpio11pp_pins + &gpio15od_pins + &gpio17pp_pins + &gpio18pp_pins + &gpio19pp_pins + &gpio24pp_pins + &gpio25pp_pins + &gpio37od_pins + &gpio59pp_pins + &gpio72od_pins + &gpio73od_pins + &gpio74od_pins + &gpio75od_pins + &gpio76od_pins + &gpio77od_pins + &gpio78od_pins + &gpio79od_pins + &gpio84pp_pins + &gpio85pp_pins + &gpio86pp_pins + &gpio87pp_pins + &gpio88pp_pins + &gpio89pp_pins + &gpio90pp_pins + &gpio93pp_pins + &gpio94pp_pins + &gpio125pp_pins + &gpio126od_pins + &gpio127od_pins + &gpio142od_pins + &gpio143ol_pins + &gpio175od_pins + &gpio176od_pins + &gpio190od_pins + &gpio194pp_pins + &gpio195od_pins + &gpio196od_pins + &gpio197od_pins + &gpio198od_pins + &gpio199od_pins + &gpio200pp_pins + &gpio202od_pins + >; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts new file mode 100644 index 000000000000..f7b38bee039b --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Fii USA Inc. + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" + +#include + +/ { + model = "Fii Kudo Board"; + compatible = "fii,kudo", "nuvoton,npcm730"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + jtag_master { + compatible = "nuvoton,npcm750-jtag-master"; + #address-cells = <1>; + #size-cells = <1>; + + // dev/jtag0 + dev-num = <0>; + // pspi or gpio + mode = "pspi"; + + // pspi2 + pspi-controller = <2>; + reg = <0xf0201000 0x1000>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + + // TCK, TDI, TDO, TMS + jtag-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>, + <&gpio0 18 GPIO_ACTIVE_HIGH>, + <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio0 14 1>; + }; + }; + + pinctrl: pinctrl@f0800000 { + gpio61oh_pins: gpio61oh-pins { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + gpio62oh_pins: gpio62oh-pins { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + gpio161ol_pins: gpio161ol-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + output-low; + }; + gpio163i_pins: gpio163i-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio167ol_pins: gpio167ol-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + output-low; + }; + gpio95i_pins: gpio95i-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio65ol_pins: gpio65ol-pins { + pins = "GPIO65/FANIN1"; + bias-disable; + output-low; + }; + gpio66oh_pins: gpio66oh-pins { + pins = "GPIO66/FANIN2"; + bias-disable; + output-high; + }; + gpio67oh_pins: gpio67oh-pins { + pins = "GPIO67/FANIN3"; + bias-disable; + output-high; + }; + gpio68ol_pins: gpio68ol-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + output-low; + }; + gpio69i_pins: gpio69i-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + input-enable; + }; + gpio70ol_pins: gpio70ol-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + output-low; + }; + gpio71i_pins: gpio71i-pins { + pins = "GPIO71/FANIN7"; + bias-disable; + input-enable; + }; + gpio72i_pins: gpio72i-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + input-enable; + }; + gpio73i_pins: gpio73i-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + input-enable; + }; + gpio74i_pins: gpio74i-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + input-enable; + }; + gpio75i_pins: gpio75i-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + input-enable; + }; + gpio76i_pins: gpio76i-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77i_pins: gpio77i-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78i_pins: gpio78i-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + input-enable; + }; + gpio79ol_pins: gpio79ol-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + output-low; + }; + gpio80oh_pins: gpio80oh-pins { + pins = "GPIO80/PWM0"; + bias-disable; + output-high; + }; + gpio81i_pins: gpio81i-pins { + pins = "GPIO81/PWM1"; + bias-disable; + input-enable; + }; + gpio82i_pins: gpio82i-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83i_pins: gpio83i-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio144i_pins: gpio144i-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145i_pins: gpio145i-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146i_pins: gpio146i-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147oh_pins: gpio147oh-pins { + pins = "GPIO147/PWM7"; + bias-disable; + output-high; + }; + gpio168ol_pins: gpio168ol-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + output-low; + }; + gpio169oh_pins: gpio169oh-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio170ol_pins: gpio170ol-pins { + pins = "GPIO170/nSMI"; + bias-disable; + output-low; + }; + gpio218oh_pins: gpio218oh-pins { + pins = "GPIO218/nWDO1"; + bias-disable; + output-high; + }; + gpio37i_pins: gpio37i-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + input-enable; + }; + gpio38i_pins: gpio38i-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39i_pins: gpio39i-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40i_pins: gpio40i-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + input-enable; + }; + gpio121i_pins: gpio121i-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122i_pins: gpio122i-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123i_pins: gpio123i-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124i_pins: gpio124i-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125i_pins: gpio125i-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126i_pins: gpio126i-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127i_pins: gpio127i-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + input-enable; + }; + gpio136i_pins: gpio136i-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137oh_pins: gpio137oh-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + output-high; + }; + gpio138i_pins: gpio138i-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139i_pins: gpio139i-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140i_pins: gpio140i-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141i_pins: gpio141i-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio190oh_pins: gpio190oh-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-high; + }; + gpio191oh_pins: gpio191oh-pins { + pins = "GPIO191"; + bias-disable; + output-high; + }; + gpio195ol_pins: gpio195ol-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + output-low; + }; + gpio196ol_pins: gpio196ol-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + output-low; + }; + gpio199i_pins: gpio199i-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + input-enable; + }; + gpio202ol_pins: gpio202ol-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + output-low; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + label = "bmc"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0xC0000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x3500000>; + }; + rwfs@3d00000 { + label = "rwfs"; + reg = <0x3d00000 0x300000>; + }; + }; + }; + flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "bios"; + reg = <0x0 0x0>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // Rear-Fan + max31790@58 { + compatible = "maxim,max31790"; + reg = <0x58>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // Mid-Fan + max31790@58 { + compatible = "maxim,max31790"; + reg = <0x58>; + }; + }; + + i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + // INLET1_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + // OUTLET1_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + // OUTLET2_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + // OUTLET3_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + }; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // STB-T + pmbus@74 { + compatible = "pmbus"; + reg = <0x74>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; + + smpro@4e { + compatible = "ampere,smpro"; + reg = <0x4e>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + // ADC sensors + adm1266@40 { + compatible = "adi,adm1266"; + reg = <0x40>; + }; + }; + + i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // ADC sensors + adm1266@41 { + compatible = "adi,adm1266"; + reg = <0x41>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c13 { + status = "okay"; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // M2_ZONE_T + lm75@28 { + compatible = "ti,lm75"; + reg = <0x28>; + }; + }; + + i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + // BATT_ZONE_T + lm75@29 { + compatible = "ti,lm75"; + reg = <0x29>; + }; + }; + + i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + // NBM1_ZONE_T + lm75@28 { + compatible = "ti,lm75"; + reg = <0x28>; + }; + }; + i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + // NBM2_ZONE_T + lm75@29 { + compatible = "ti,lm75"; + reg = <0x29>; + }; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + &gpio61oh_pins + &gpio62oh_pins + &gpio161ol_pins + &gpio163i_pins + &gpio167ol_pins + &gpio95i_pins + &gpio65ol_pins + &gpio66oh_pins + &gpio67oh_pins + &gpio68ol_pins + &gpio69i_pins + &gpio70ol_pins + &gpio71i_pins + &gpio72i_pins + &gpio73i_pins + &gpio74i_pins + &gpio75i_pins + &gpio76i_pins + &gpio77i_pins + &gpio78i_pins + &gpio79ol_pins + &gpio80oh_pins + &gpio81i_pins + &gpio82i_pins + &gpio83i_pins + &gpio144i_pins + &gpio145i_pins + &gpio146i_pins + &gpio147oh_pins + &gpio168ol_pins + &gpio169oh_pins + &gpio170ol_pins + &gpio218oh_pins + &gpio37i_pins + &gpio38i_pins + &gpio39i_pins + &gpio40i_pins + &gpio121i_pins + &gpio122i_pins + &gpio123i_pins + &gpio124i_pins + &gpio125i_pins + &gpio126i_pins + &gpio127i_pins + &gpio136i_pins + &gpio137oh_pins + &gpio138i_pins + &gpio139i_pins + &gpio140i_pins + &gpio141i_pins + &gpio190oh_pins + &gpio191oh_pins + &gpio195ol_pins + &gpio196ol_pins + &gpio199i_pins + &gpio202ol_pins + >; +}; + +&gcr { + serial_port_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts new file mode 100644 index 000000000000..f53d45fa1de8 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" +#include "dt-bindings/gpio/gpio.h" +#include "nuvoton-npcm750-pincfg-evb.dtsi" + +/ { + model = "Nuvoton npcm750 Development Board (Device Tree)"; + compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750"; + + aliases { + ethernet2 = &gmac0; + ethernet3 = &gmac1; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + fiu2 = &fiux; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fiu0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + spi-max-frequency = <5000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bbuboot1@0 { + label = "bb-uboot-1"; + reg = <0x0000000 0x80000>; + read-only; + }; + bbuboot2@80000 { + label = "bb-uboot-2"; + reg = <0x0080000 0x80000>; + read-only; + }; + envparam@100000 { + label = "env-param"; + reg = <0x0100000 0x40000>; + read-only; + }; + spare@140000 { + label = "spare"; + reg = <0x0140000 0xC0000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x400000>; + }; + rootfs@600000 { + label = "rootfs"; + reg = <0x0600000 0x700000>; + }; + spare1@d00000 { + label = "spare1"; + reg = <0x0D00000 0x200000>; + }; + spare2@f00000 { + label = "spare2"; + reg = <0x0F00000 0x200000>; + }; + spare3@1100000 { + label = "spare3"; + reg = <0x1100000 0x200000>; + }; + spare4@1300000 { + label = "spare4"; + reg = <0x1300000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + spi-max-frequency = <5000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x0>; + }; + }; + }; +}; + +&fiux { + spix-mode; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&lpc_kcs { + kcs1: kcs1@0 { + status = "okay"; + }; + + kcs2: kcs2@0 { + status = "okay"; + }; + + kcs3: kcs3@0 { + status = "okay"; + }; +}; + +/* lm75 on SVB */ +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; +}; + +/* lm75 on EB */ +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; +}; + +/* tmp100 on EB */ +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + status = "okay"; +}; + +/* tmp100 on SVB */ +&i2c6 { + clock-frequency = <100000>; + status = "okay"; + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c8 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c10 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c11 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c14 { + clock-frequency = <100000>; + status = "okay"; +}; + +&pwm_fan { + status = "okay"; + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; + flash@0 { + compatible = "winbond,w25q128", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi0_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi0_spare2"; + reg = <0x800000 0x0>; + }; + }; +}; + +&spi1 { + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + status = "okay"; + flash@0 { + compatible = "winbond,w25q128fw", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi1_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi1_spare2"; + reg = <0x800000 0x0>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < &iox1_pins + &pin8_input + &pin9_output_high + &pin10_input + &pin11_output_high + &pin16_input + &pin24_output_high + &pin25_output_low + &pin32_output_high + &jtag2_pins + &pin61_output_high + &pin62_output_high + &pin63_output_high + &lpc_pins + &pin160_input + &pin162_input + &pin168_input + &pin169_input + &pin170_input + &pin187_output_high + &pin190_input + &pin191_output_high + &pin192_output_high + &pin197_output_low + &ddc_pins + &pin218_input + &pin219_output_low + &pin220_output_low + &pin221_output_high + &pin222_input + &pin223_output_low + &spix_pins + &pin228_output_low + &pin231_output_high + &pin255_input>; +}; + diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi new file mode 100644 index 000000000000..3b3806274adf --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology + +/ { + pinctrl: pinctrl@f0800000 { + pin8_input: pin8-input { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + pin9_output_high: pin9-output-high { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-high; + }; + pin10_input: pin10-input { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + pin11_output_high: pin11-output-high { + pins = "GPIO11/IOXHCK"; + bias-disable; + output-high; + }; + pin16_input: pin16-input { + pins = "GPIO16/LKGPO0"; + bias-disable; + input-enable; + }; + pin24_output_high: pin24-output-high { + pins = "GPIO24/IOXHDO"; + bias-disable; + output-high; + }; + pin25_output_low: pin25-output-low { + pins = "GPIO25/IOXHDI"; + bias-disable; + output-low; + }; + pin32_output_high: pin32-output-high { + pins = "GPIO32/nSPI0CS1"; + bias-disable; + output-high; + }; + pin61_output_high: pin61-output-high { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + pin62_output_high: pin62-output-high { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + pin63_output_high: pin63-output-high { + pins = "GPO63/TXD1/STRAP4"; + bias-disable; + output-high; + }; + pin160_input: pin160-input { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + input-enable; + }; + pin162_input: pin162-input { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + pin168_input: pin168-input { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + pin169_input: pin169-input { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + pin170_input: pin170-input { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + pin187_output_high: pin187-output-high { + pins = "GPIO187/nSPI3CS1"; + bias-disable; + output-high; + }; + pin190_input: pin190-input { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + input-enable; + }; + pin191_output_high: pin191-output-high { + pins = "GPIO191"; + bias-disable; + output-high; + }; + pin192_output_high: pin192-output-high { + pins = "GPIO192"; + bias-disable; + output-high; + }; + pin197_output_low: pin197-output-low { + pins = "GPIO197/SMB0DEN"; + bias-disable; + output-low; + }; + pin218_input: pin218-input { + pins = "GPIO218/nWDO1"; + bias-disable; + input-enable; + }; + pin219_output_low: pin219-output-low { + pins = "GPIO219/nWDO2"; + bias-disable; + output-low; + }; + pin220_output_low: pin220-output-low { + pins = "GPIO220/SMB12SCL"; + bias-disable; + output-low; + }; + pin221_output_high: pin221-output-high { + pins = "GPIO221/SMB12SDA"; + bias-disable; + output-high; + }; + pin222_input: pin222-input { + pins = "GPIO222/SMB13SCL"; + bias-disable; + input-enable; + }; + pin223_output_low: pin223-output-low { + pins = "GPIO223/SMB13SDA"; + bias-disable; + output-low; + }; + pin228_output_low: pin228-output-low { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-low; + }; + pin231_output_high: pin231-output-high { + pins = "GPIO230/SPIXD3"; + bias-disable; + output-high; + }; + pin255_input: pin255-input { + pins = "GPI255/DACOSEL"; + bias-disable; + input-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi new file mode 100644 index 000000000000..230cb344b2e1 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0ol_pins: gpio0ol-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + output-low; + }; + gpio1ol_pins: gpio1ol-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + output-low; + }; + gpio2ol_pins: gpio2ol-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + output-low; + }; + gpio3ol_pins: gpio3ol-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + output-low; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + input-enable; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + input-enable; + }; + gpio8o_pins: gpio8o-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + input-enable; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + output-low; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + output-low; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + output-low; + }; + gpio15ol_pins: gpio15ol-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + input-enable; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/SMB4CSCL/SMB15SCL"; + bias-disable; + input-enable; + }; + gpio22o_pins: gpio22o-pins { + pins = "GPIO22/SMB4DSDA/SMB14SDA"; + bias-disable; + output-high; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/SMB4DSCL/SMB14SCL"; + bias-disable; + input-enable; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + input-enable; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + input-enable; + }; + gpio30_pins: gpio30-pins { + pins = "GPIO30/SMB3SDA"; + bias-disable; + input-enable; + }; + gpio31_pins: gpio31-pins { + pins = "GPIO31/SMB3SCL"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + output-high; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + output-high; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + input-enable; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78o_pins: gpio78o-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-high; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + output-high; + }; + gpio86ol_pins: gpio86ol-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + output-low; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + input-enable; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + input-enable; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + input-enable; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + input-enable; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + input-enable; + }; + gpio94ol_pins: gpio94ol-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + output-low; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/RG1MDC"; + bias-disable; + output-low; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/RG1MDIO"; + bias-disable; + output-low; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2TXD0/DDRV0"; + bias-disable; + output-low; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2TXD1/DDRV1"; + bias-disable; + output-low; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio114o_pins: gpio114o-pins { + pins = "GPIO114/SMB0SCL"; + bias-disable; + output-high; + }; + gpio115_pins: gpio115-pins { + pins = "GPIO115/SMB0SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2CSDA"; + bias-disable; + input-enable; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127o_pins: gpio127o-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + output-high; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + input-enable; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + input-enable; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio153o_pins: gpio153o-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + output-high; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + output-high; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3D2/nSPI3CS2"; + bias-disable; + output-high; + }; + gpio189_pins: gpio189-pins { + pins = "GPIO189/SPI3D3/nSPI3CS3"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + input-enable; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + input-enable; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + output-high; + }; + gpio199o_pins: gpio199o-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + output-high; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2CK"; + input-enable; + bias-disable; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + output-high; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2TXCTL/DDRV4"; + bias-disable; + output-low; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + output-low; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + output-low; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + output-low; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + output-low; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2RXC/DDRV9"; + bias-disable; + output-low; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2RXCTL/DDRV10"; + bias-disable; + output-low; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + input-enable; + }; + gpio225ol_pins: gpio225ol-pins { + pins = "GPO225/SPIXD0/STRAP12"; + bias-disable; + output-low; + }; + gpio226ol_pins: gpio226ol-pins { + pins = "GPO226/SPIXD1/STRAP13"; + bias-disable; + output-low; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-low; + }; + gpio228o_pins: gpio228ol-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-high; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIXD2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/nCLKREQ"; + bias-disable; + output-high; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts new file mode 100644 index 000000000000..87359ab05db3 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -0,0 +1,1052 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology +// Copyright (c) 2019 Quanta Computer Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" +#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi" + +#include +#include + +/ { + model = "Nuvoton npcm750 RunBMC Olympus"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio3 14 1>; + }; + + identify { + label = "identify"; + gpios = <&gpio3 15 1>; + }; + }; + + jtag { + compatible = "nuvoton,npcm750-jtag"; + enable_pspi_jtag = <1>; + pspi-index = <2>; + tck { + label = "tck"; + gpios = <&gpio0 19 0>; /* gpio19 */ + regbase = <0xf0010000 0x1000>; + }; + + tdi { + label = "tdi"; + gpios = <&gpio0 18 0>; /* gpio18 */ + regbase = <0xf0010000 0x1000>; + }; + + tdo { + label = "tdo"; + gpios = <&gpio0 17 0>; /* gpio17 */ + regbase = <0xf0010000 0x1000>; + }; + tms { + label = "tms"; + gpios = <&gpio0 16 0>; /* gpio16 */ + regbase = <0xf0010000 0x1000>; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1500000>; + }; + rwfs@1d00000 { + label = "rwfs"; + reg = <0x1d00000 0x300000>; + }; + }; + }; + + flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + npcm,fiu-rx-bus-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x800000>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&gcr { + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <6>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c_slot1a: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_slot1b: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_slot2a: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_slot2b: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_slot3: i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_slot4: i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_slot5: i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c_m2_s1: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_m2_s2: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c_m2_s3: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_m2_s4: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + power-supply@58 { + compatible = "delta,dps800"; + reg = <0x58>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-slave-mqueue@10 { + compatible = "i2c-slave-mqueue"; + reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>; + }; +}; + +&i2c6 { + status = "okay"; + + ina219@40 { + compatible = "ti,ina219"; + reg = <0x40>; + }; + ina219@41 { + compatible = "ti,ina219"; + reg = <0x41>; + }; + ina219@44 { + compatible = "ti,ina219"; + reg = <0x44>; + }; + ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + }; + tps53679@60 { + compatible = "ti,tps53679"; + reg = <0x60>; + }; + tps53659@62 { + compatible = "ti,tps53659"; + reg = <0x62>; + }; + tps53659@64 { + compatible = "ti,tps53659"; + reg = <0x64>; + }; + tps53622@67 { + compatible = "ti,tps53622"; + reg = <0x67>; + }; + tps53622@69 { + compatible = "ti,tps53622"; + reg = <0x69>; + }; + tps53679@70 { + compatible = "ti,tps53679"; + reg = <0x70>; + }; + tps53659@72 { + compatible = "ti,tps53659"; + reg = <0x72>; + }; + tps53659@74 { + compatible = "ti,tps53659"; + reg = <0x74>; + }; + tps53622@77 { + compatible = "ti,tps53622"; + reg = <0x77>; + }; +}; + +&i2c7 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c8 { + status = "okay"; + + adm1278@11 { + compatible = "adm1278"; + reg = <0x11>; + Rsense = <500>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + gpio: pca9555@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c11 { + status = "okay"; + + pca9539_g1a: pca9539-g1a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + G1A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "TPM_BMC_ALERT_N"; + }; + G1A_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_TOP_SWAP"; + }; + G1A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_BIOS_PREFRB2_GOOD"; + }; + G1A_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "BMC_SATAXPCIE_0TO3_SEL"; + }; + G1A_P0_4 { + gpio-hog; + gpios = <4 0>; + input; + line-name = "BMC_SATAXPCIE_4TO7_SEL"; + }; + G1A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "FM_UV_ADR_TRIGGER_EN_N"; + }; + G1A_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "RM_THROTTLE_EN_N"; + }; + G1A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_BMC_TPM_PRES_N"; + }; + G1A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_CPU0_SKTOCC_LVT3_N"; + }; + G1A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_CPU1_SKTOCC_LVT3_N"; + }; + G1A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_ALERT_N"; + }; + G1A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "PSU2_ALERT_N"; + }; + G1A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "H_CPU0_FAST_WAKE_LVT3_N"; + }; + G1A_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "I2C_MUX1_RESET_N"; + }; + G1A_P1_7 { + gpio-hog; + gpios = <15 0>; + input; + line-name = "FM_CPU_CATERR_LVT3_N"; + }; + }; + + pca9539_g1b: pca9539-g1b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G1B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "PVDDQ_ABC_PINALERT_N"; + }; + G1B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "PVDDQ_DEF_PINALERT_N"; + }; + G1B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "PVDDQ_GHJ_PINALERT_N"; + }; + G1B_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "PVDDQ_KLM_PINALERT_N"; + }; + G1B_P0_5 { + gpio-hog; + gpios = <5 0>; + input; + line-name = "FM_BOARD_REV_ID0"; + }; + G1B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BOARD_REV_ID1"; + }; + G1B_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "FM_BOARD_REV_ID2"; + }; + G1B_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_OC_DETECT_EN_N"; + }; + G1B_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_FLASH_DESC_OVERRIDE"; + }; + G1B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "FP_PWR_ID_LED_N"; + }; + G1B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "BMC_LED_PWR_GRN"; + }; + G1B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "BMC_LED_PWR_AMBER"; + }; + G1B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "FM_BMC_FAULT_LED_N"; + }; + G1B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_CPLD_BMC_PWRDN_N"; + }; + G1B_P1_7 { + gpio-hog; + gpios = <15 0>; + output-high; + line-name = "BMC_LED_CATERR_N"; + }; + }; +}; + +&i2c12 { + status = "okay"; + + pca9539_g2a: pca9539-g2a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + G2A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "BMC_PON_RST_REQ_N"; + }; + G2A_P0_1 { + gpio-hog; + gpios = <1 0>; + output-high; + line-name = "BMC_RST_IND_REQ_N"; + }; + G2A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "RST_BMC_RTCRST"; + }; + G2A_P0_3 { + gpio-hog; + gpios = <3 0>; + output-high; + line-name = "FM_BMC_PWRBTN_OUT_N"; + }; + G2A_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "RST_BMC_SYSRST_BTN_OUT_N"; + }; + G2A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "FM_BATTERY_SENSE_EN_N"; + }; + G2A_P0_6 { + gpio-hog; + gpios = <6 0>; + output-high; + line-name = "FM_BMC_READY_N"; + }; + G2A_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + G2A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_SLOT4_CFG0"; + }; + G2A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_SLOT4_CFG1"; + }; + G2A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_NVDIMM_EVENT_N"; + }; + G2A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_BLADE_EN_N"; + }; + G2A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "BMC_PCH_FNM"; + }; + G2A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "FM_SOL_UART_CH_SEL"; + }; + G2A_P1_6 { + gpio-hog; + gpios = <14 0>; + input; + line-name = "FM_BIOS_POST_CMPLT_N"; + }; + }; + + pca9539_g2b: pca9539-g2b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G2B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "FM_CPU_MSMI_LVT3_N"; + }; + G2B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; + }; + G2B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_CPU1_DISABLE_BMC_N"; + }; + G2B_P0_3 { + gpio-hog; + gpios = <3 0>; + output-low; + line-name = "BMC_JTAG_SELECT"; + }; + G2B_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "PECI_MUX_SELECT"; + }; + G2B_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "I2C_MUX2_RESET_N"; + }; + G2B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BMC_CPLD_PSU2_ON"; + }; + G2B_P0_7 { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "PSU2_ALERT_EN_N"; + }; + G2B_P1_0 { + gpio-hog; + gpios = <8 0>; + output-high; + line-name = "FM_CPU_BMC_INIT"; + }; + G2B_P1_1 { + gpio-hog; + gpios = <9 0>; + output-high; + line-name = "IRQ_BMC_PCH_SCI_LPC_N"; + }; + G2B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PMB_ALERT_EN_N"; + }; + G2B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-high; + line-name = "FM_FAST_PROCHOT_EN_N"; + }; + G2B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BMC_NVDIMM_PRSNT_N"; + }; + G2B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; + }; + G2B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_PWRBRK_N"; + }; + }; +}; + +&i2c13 { + status = "okay"; + + tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + status = "okay"; + }; + m24128_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <64>; + status = "okay"; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = < &pwm0_pins &pwm1_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&kcs1 { + status = "okay"; +}; + +&kcs2 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /******* RunBMC inside Module pins *******/ + &gpio0ol_pins + &gpio1ol_pins + &gpio2ol_pins + &gpio3ol_pins + &gpio8o_pins + &gpio9ol_pins + &gpio12ol_pins + &gpio13ol_pins + &gpio14ol_pins + &gpio15ol_pins + &gpio37o_pins + &gpio38_pins + &gpio39_pins + &gpio94ol_pins + &gpio108ol_pins + &gpio109ol_pins + &gpio111ol_pins + &gpio112ol_pins + &gpio113ol_pins + &gpio208_pins + &gpio209ol_pins + &gpio210ol_pins + &gpio211ol_pins + &gpio212ol_pins + &gpio213ol_pins + &gpio214ol_pins + &gpio215ol_pins + &gpio216ol_pins + &gpio217ol_pins + /******* RunBMC outside Connector pins *******/ + &gpio5_pins + &gpio6_pins + &gpio7_pins + &gpio10_pins + &gpio11_pins + &gpio20_pins + &gpio21_pins + &gpio22o_pins + &gpio23_pins + &gpio24_pins + &gpio25_pins + &gpio30_pins + &gpio31_pins + &gpio40o_pins + &gpio59_pins + &gpio76_pins + &gpio77_pins + &gpio78o_pins + &gpio79_pins + &gpio82_pins + &gpio83_pins + &gpio84_pins + &gpio85o_pins + &gpio86ol_pins + &gpio87_pins + &gpio88_pins + &gpio89_pins + &gpio90_pins + &gpio93_pins + &gpio114o_pins + &gpio115_pins + &gpio120_pins + &gpio121_pins + &gpio122_pins + &gpio123_pins + &gpio124_pins + &gpio125_pins + &gpio126_pins + &gpio127o_pins + &gpio136_pins + &gpio137_pins + &gpio138_pins + &gpio139_pins + &gpio140_pins + &gpio141_pins + &gpio142_pins + &gpio143_pins + &gpio144_pins + &gpio146_pins + &gpio145_pins + &gpio147_pins + &gpio153o_pins + &gpio155_pins + &gpio160o_pins + &gpio169o_pins + &gpio188o_pins + &gpio189_pins + &gpio196_pins + &gpio197_pins + &gpio198o_pins + &gpio199o_pins + &gpio200_pins + &gpio202_pins + &gpio203o_pins + &gpio224_pins + &gpio225ol_pins + &gpio226ol_pins + &gpio227ol_pins + &gpio228o_pins + &gpio229o_pins + &gpio230_pins + &gpio231o_pins + &ddc_pins + &wdog1_pins + &wdog2_pins + >; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..30eed40b89b5 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; + + ahb { + gmac1: eth@f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg2_pins + &rg2mdio_pins>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts new file mode 100644 index 000000000000..b78c116cbc18 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +// Copyright 2021 Jonathan Neuschäfer + +/dts-v1/; + +/* The last 16 MiB are dedicated to the GPU */ +/memreserve/ 0x07000000 0x01000000; + +#include "nuvoton-wpcm450.dtsi" + +#include +#include + +/ { + model = "Supermicro X9SCi-LN4F BMC"; + compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0x08000000>; /* 128 MiB */ + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins>; + + uid { + label = "UID button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + uid { + label = "UID"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + heartbeat { + label = "heartbeat"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fiu { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; +}; + +&gpio0 { + gpio-line-names = + /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "", + /* 8 */ "", "", "", "", "power-chassis-control-n", "", "uid-button", ""; +}; + +&gpio1 { + gpio-line-names = + /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid", + /* 8 */ "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 0 */ "", "", "", "", "", "", "", "", + /* 8 */ "", "", "", "", "", "", "", "power-chassis-good"; +}; + +&pinctrl { + key_pins: mux-keys { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + led_pins: mux-leds { + groups = "hg3", "hg0", "pwm4"; + function = "gpio"; + }; +}; + +&serial0 { + /* + * Debug serial port. TX is exposed on the right pad of unpopulated + * resistor R1247, RX on the right pad of R1162. + */ + status = "okay"; +}; + +&serial1 { + /* "Serial over LAN" port. Connected to ttyS2 of the host system. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi new file mode 100644 index 000000000000..fd671c7a1e5d --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +// Copyright 2021 Jonathan Neuschäfer + +#include + +/ { + compatible = "nuvoton,wpcm450"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + clk24m: clock-24mhz { + /* 24 MHz dummy clock */ + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&aic>; + ranges; + + gcr: syscon@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + serial0: serial@b8000000 { + compatible = "nuvoton,wpcm450-uart"; + reg = <0xb8000000 0x20>; + reg-shift = <2>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk24m>; + pinctrl-names = "default"; + pinctrl-0 = <&bsp_pins>; + status = "disabled"; + }; + + serial1: serial@b8000100 { + compatible = "nuvoton,wpcm450-uart"; + reg = <0xb8000100 0x20>; + reg-shift = <2>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk24m>; + status = "disabled"; + }; + + timer0: timer@b8001000 { + compatible = "nuvoton,wpcm450-timer"; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb8001000 0x1c>; + clocks = <&clk24m>; + }; + + watchdog0: watchdog@b800101c { + compatible = "nuvoton,wpcm450-wdt"; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb800101c 0x4>; + clocks = <&clk24m>; + }; + + aic: interrupt-controller@b8002000 { + compatible = "nuvoton,wpcm450-aic"; + reg = <0xb8002000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio1: gpio@1 { + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio2: gpio@2 { + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@3 { + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@4 { + reg = <4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@5 { + reg = <5>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@6 { + reg = <6>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@7 { + reg = <7>; + gpio-controller; + #gpio-cells = <2>; + }; + + smb3_pins: mux-smb3 { + groups = "smb3"; + function = "smb3"; + }; + + smb4_pins: mux-smb4 { + groups = "smb4"; + function = "smb4"; + }; + + smb5_pins: mux-smb5 { + groups = "smb5"; + function = "smb5"; + }; + + scs1_pins: mux-scs1 { + groups = "scs1"; + function = "scs1"; + }; + + scs2_pins: mux-scs2 { + groups = "scs2"; + function = "scs2"; + }; + + scs3_pins: mux-scs3 { + groups = "scs3"; + function = "scs3"; + }; + + smb0_pins: mux-smb0 { + groups = "smb0"; + function = "smb0"; + }; + + smb1_pins: mux-smb1 { + groups = "smb1"; + function = "smb1"; + }; + + smb2_pins: mux-smb2 { + groups = "smb2"; + function = "smb2"; + }; + + bsp_pins: mux-bsp { + groups = "bsp"; + function = "bsp"; + }; + + hsp1_pins: mux-hsp1 { + groups = "hsp1"; + function = "hsp1"; + }; + + hsp2_pins: mux-hsp2 { + groups = "hsp2"; + function = "hsp2"; + }; + + r1err_pins: mux-r1err { + groups = "r1err"; + function = "r1err"; + }; + + r1md_pins: mux-r1md { + groups = "r1md"; + function = "r1md"; + }; + + rmii2_pins: mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + r2err_pins: mux-r2err { + groups = "r2err"; + function = "r2err"; + }; + + r2md_pins: mux-r2md { + groups = "r2md"; + function = "r2md"; + }; + + kbcc_pins: mux-kbcc { + groups = "kbcc"; + function = "kbcc"; + }; + + dvo0_pins: mux-dvo0 { + groups = "dvo"; + function = "dvo0"; + }; + + dvo3_pins: mux-dvo3 { + groups = "dvo"; + function = "dvo3"; + }; + + clko_pins: mux-clko { + groups = "clko"; + function = "clko"; + }; + + smi_pins: mux-smi { + groups = "smi"; + function = "smi"; + }; + + uinc_pins: mux-uinc { + groups = "uinc"; + function = "uinc"; + }; + + gspi_pins: mux-gspi { + groups = "gspi"; + function = "gspi"; + }; + + mben_pins: mux-mben { + groups = "mben"; + function = "mben"; + }; + + xcs2_pins: mux-xcs2 { + groups = "xcs2"; + function = "xcs2"; + }; + + xcs1_pins: mux-xcs1 { + groups = "xcs1"; + function = "xcs1"; + }; + + sdio_pins: mux-sdio { + groups = "sdio"; + function = "sdio"; + }; + + sspi_pins: mux-sspi { + groups = "sspi"; + function = "sspi"; + }; + + fi0_pins: mux-fi0 { + groups = "fi0"; + function = "fi0"; + }; + + fi1_pins: mux-fi1 { + groups = "fi1"; + function = "fi1"; + }; + + fi2_pins: mux-fi2 { + groups = "fi2"; + function = "fi2"; + }; + + fi3_pins: mux-fi3 { + groups = "fi3"; + function = "fi3"; + }; + + fi4_pins: mux-fi4 { + groups = "fi4"; + function = "fi4"; + }; + + fi5_pins: mux-fi5 { + groups = "fi5"; + function = "fi5"; + }; + + fi6_pins: mux-fi6 { + groups = "fi6"; + function = "fi6"; + }; + + fi7_pins: mux-fi7 { + groups = "fi7"; + function = "fi7"; + }; + + fi8_pins: mux-fi8 { + groups = "fi8"; + function = "fi8"; + }; + + fi9_pins: mux-fi9 { + groups = "fi9"; + function = "fi9"; + }; + + fi10_pins: mux-fi10 { + groups = "fi10"; + function = "fi10"; + }; + + fi11_pins: mux-fi11 { + groups = "fi11"; + function = "fi11"; + }; + + fi12_pins: mux-fi12 { + groups = "fi12"; + function = "fi12"; + }; + + fi13_pins: mux-fi13 { + groups = "fi13"; + function = "fi13"; + }; + + fi14_pins: mux-fi14 { + groups = "fi14"; + function = "fi14"; + }; + + fi15_pins: mux-fi15 { + groups = "fi15"; + function = "fi15"; + }; + + pwm0_pins: mux-pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + pwm1_pins: mux-pwm1 { + groups = "pwm1"; + function = "pwm1"; + }; + + pwm2_pins: mux-pwm2 { + groups = "pwm2"; + function = "pwm2"; + }; + + pwm3_pins: mux-pwm3 { + groups = "pwm3"; + function = "pwm3"; + }; + + pwm4_pins: mux-pwm4 { + groups = "pwm4"; + function = "pwm4"; + }; + + pwm5_pins: mux-pwm5 { + groups = "pwm5"; + function = "pwm5"; + }; + + pwm6_pins: mux-pwm6 { + groups = "pwm6"; + function = "pwm6"; + }; + + pwm7_pins: mux-pwm7 { + groups = "pwm7"; + function = "pwm7"; + }; + + hg0_pins: mux-hg0 { + groups = "hg0"; + function = "hg0"; + }; + + hg1_pins: mux-hg1 { + groups = "hg1"; + function = "hg1"; + }; + + hg2_pins: mux-hg2 { + groups = "hg2"; + function = "hg2"; + }; + + hg3_pins: mux-hg3 { + groups = "hg3"; + function = "hg3"; + }; + + hg4_pins: mux-hg4 { + groups = "hg4"; + function = "hg4"; + }; + + hg5_pins: mux-hg5 { + groups = "hg5"; + function = "hg5"; + }; + + hg6_pins: mux-hg6 { + groups = "hg6"; + function = "hg6"; + }; + + hg7_pins: mux-hg7 { + groups = "hg7"; + function = "hg7"; + }; + }; + + fiu: spi-controller@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; + reg-names = "control", "memory"; + clocks = <&clk 0>; + nuvoton,shm = <&shm>; + status = "disabled"; + }; + + shm: syscon@c8001000 { + compatible = "nuvoton,wpcm450-shm", "syscon"; + reg = <0xc8001000 0x1000>; + reg-io-width = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile new file mode 100644 index 000000000000..60091bf7e48b --- /dev/null +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-asus-tf701t.dtb \ + tegra114-dalmore.dtb \ + tegra114-roth.dtb \ + tegra114-tn7.dtb +dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ + tegra124-apalis-eval.dtb \ + tegra124-apalis-v1.2-eval.dtb \ + tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ + tegra124-nyan-big-fhd.dtb \ + tegra124-nyan-blaze.dtb \ + tegra124-venice2.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ + tegra20-acer-a500-picasso.dtb \ + tegra20-asus-tf101.dtb \ + tegra20-harmony.dtb \ + tegra20-colibri-eval-v3.dtb \ + tegra20-colibri-iris.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ + tegra30-apalis-eval.dtb \ + tegra30-apalis-v1.1-eval.dtb \ + tegra30-asus-nexus7-grouper-PM269.dtb \ + tegra30-asus-nexus7-grouper-E1565.dtb \ + tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf700t.dtb \ + tegra30-beaver.dtb \ + tegra30-cardhu-a02.dtb \ + tegra30-cardhu-a04.dtb \ + tegra30-colibri-eval-v3.dtb \ + tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts new file mode 100644 index 000000000000..84a3eb38e71d --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include +#include + +#include "tegra114.dtsi" + +/ { + model = "Asus Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000400"; /* uSD slot */ + mmc2 = "/mmc@78000000"; /* WiFi */ + + rtc0 = &palmas; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; + linux,cma-default; + reusable; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + nvidia,ganged-mode = <&dsib>; + + panel_primary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + + dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + asus_pad_ec_default: pinmux-asus-pad-ec-default { + ec-interrupt { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec-request { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + backlight_default: pinmux-backlight-default { + backlight-enable { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + codec_default: pinmux-codec-default { + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ldo1-en { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_keys_default: pinmux-gpio-keys-default { + power { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + volume { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + hp_det_default: pinmux-hp-det-default { + gmi_iordy_pi5 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + imu_default: pinmux-imu-default { + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pwm_default: pinmux-pwm-default { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + /* XXX make this something more sensible */ + pwm_sleep: pinmux-pwm-sleep { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + sdmmc3_default: pinmux-sdmmc3-default { + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + vdd_lcd_default: pinmux-vdd-lcd-default { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + /* GPS */ + }; + + serial@70006200 { + /* Bluetooth */ + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm_default>; + pinctrl-1 = <&pwm_sleep>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0xc>; + + vdd-supply = <&vdd_3v3_sys>; + }; + + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_default>; + }; + + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + motion-tracker@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_default>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@1c { + compatible = "dynaimage,al3320a"; + reg = <0x1c>; + + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c700 { + /* HDMI DDC */ + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldo1-in-supply = <&tps65913_smps7>; + ldo2-in-supply = <&tps65913_smps7>; + ldo4-in-supply = <&tps65913_smps8>; + ldo5-in-supply = <&tps65913_smps9>; + ldo6-in-supply = <&tps65913_smps9>; + ldo7-in-supply = <&tps65913_smps9>; + ldo9-in-supply = <&tps65913_smps9>; + + regulators { + tps65913_smps123: smps123 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <1>; + ti,mode-sleep = <3>; + }; + + tps65913_smps45: smps45 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps7: smps7 { + regulator-name = "vdd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps8: smps8 { + regulator-name = "vdd-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps9: smps9 { + regulator-name = "vdd-sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + tps65913_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_ldo1: ldo1 { + regulator-name = "vdd-hdmi-pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + ti,roof-floor = <3>; + }; + + tps65913_ldo2: ldo2 { + regulator-name = "vdd-2v8-dsi-csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4 { + regulator-name = "vdd-1v2-cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo5 { + regulator-name = "vdd-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6 { + regulator-name = "vdd-dev"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-boot-on; + }; + + ldo7 { + regulator-name = "vdd-2v8-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + tps65913_ldo8: ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + tps65913_ldo9: ldo9 { + regulator-name = "vdd-sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + }; + + tps65913_ldoln: ldoln { + regulator-name = "vdd-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "vdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + }; + }; + + ahub@70080000 { + i2s@70080300 { + status = "okay"; + }; + }; + + mmc@78000000 { + /* WiFi */ + }; + + /* MicroSD card */ + mmc@78000400 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&tps65913_ldo9>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_default>; + }; + + mmc@78000600 { + /* eMMC */ + }; + + usb@7d000000 { + compatible = "nvidia,tegra114-udc"; + status = "okay"; + dr_mode = "peripheral"; + + /* Peripheral USB via ASUS connector */ + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + + /* Host USB via dock */ + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_sys>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <224>; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_default>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + switch-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + label = "GPIO Buttons"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + button-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + button-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + button-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + + sound { + compatible = "asus,tegra-audio-rt5639-tf701t", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "Asus Transformer Pad TF701T RT5639"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&rt5639>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; + + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_default>; + }; + + vdd_5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_lcd: regulator-vdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&tps65913_smps8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + + pinctrl-names = "default"; + pinctrl-0 = <&vdd_lcd_default>; + }; + + vdd_usd: regulator-vdd-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd_slot"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + vin-supply = <&tps65913_smps9>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_vdd_default>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts b/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts new file mode 100644 index 000000000000..a685fcb129d0 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts @@ -0,0 +1,1287 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This dts file supports Dalmore A04. + * Other board revisions are not supported + */ + +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra114 Dalmore evaluation board"; + compatible = "nvidia,dalmore", "nvidia,tegra114"; + + aliases { + rtc0 = "/i2c@7000d000/tps65913@58"; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + vdd-supply = <&vdd_hdmi_reg>; + pll-supply = <&palmas_smps3_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_1v2_reg>; + + panel@0 { + compatible = "panasonic,vvx10f004b00"; + reg = <0>; + + power-supply = <&avdd_lcd_reg>; + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5", + "gmi_cs6_n_pi3", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1", + "dap3_sclk_pp3"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,rcv-sel = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb5", + "pbb6", + "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1", + "pcc2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad13_ph5", + "gmi_ad8_ph0", + "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0", + "gmi_cs0_n_pj0", + "gmi_cs2_n_pk3", + "gmi_cs4_n_pk2", + "gmi_cs7_n_pi6", + "gmi_dqs_p_pj3", + "gmi_iordy_pi5", + "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row4_pr4", + "kb_row6_pr6", + "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5", + "pu6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <1>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + battery: smart-battery@b { + compatible = "ti,bq20z45", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <100>; + power-supplies = <&charger>; + }; + + rt5640: rt5640@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&palmas_ldo6_reg>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + tps51632@43 { + compatible = "ti,tps51632"; + reg = <0x43>; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1520000>; + regulator-boot-on; + regulator-always-on; + }; + + tps65090@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + interrupt-parent = <&gpio>; + interrupts = ; + + vsys1-supply = <&vdd_ac_bat_reg>; + vsys2-supply = <&vdd_ac_bat_reg>; + vsys3-supply = <&vdd_ac_bat_reg>; + infet1-supply = <&vdd_ac_bat_reg>; + infet2-supply = <&vdd_ac_bat_reg>; + infet3-supply = <&tps65090_dcdc2_reg>; + infet4-supply = <&tps65090_dcdc2_reg>; + infet5-supply = <&tps65090_dcdc2_reg>; + infet6-supply = <&tps65090_dcdc2_reg>; + infet7-supply = <&tps65090_dcdc2_reg>; + vsys-l1-supply = <&vdd_ac_bat_reg>; + vsys-l2-supply = <&vdd_ac_bat_reg>; + + charger: charger { + compatible = "ti,tps65090-charger"; + ti,enable-low-current-chrg; + }; + + regulators { + tps65090_dcdc1_reg: dcdc1 { + regulator-name = "vdd-sys-5v0"; + regulator-always-on; + regulator-boot-on; + }; + + tps65090_dcdc2_reg: dcdc2 { + regulator-name = "vdd-sys-3v3"; + regulator-always-on; + regulator-boot-on; + }; + + tps65090_dcdc3_reg: dcdc3 { + regulator-name = "vdd-ao"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bl_reg: fet1 { + regulator-name = "vdd-lcd-bl"; + }; + + fet3 { + regulator-name = "vdd-modem-3v3"; + }; + + avdd_lcd_reg: fet4 { + regulator-name = "avdd-lcd"; + }; + + fet5 { + regulator-name = "vdd-lvds"; + }; + + fet6 { + regulator-name = "vdd-sd-slot"; + regulator-always-on; + regulator-boot-on; + }; + + fet7 { + regulator-name = "vdd-com-3v3"; + }; + + ldo1 { + regulator-name = "vdd-sby-5v0"; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "vdd-sby-3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + palmas: tps65913@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + smps1-in-supply = <&tps65090_dcdc3_reg>; + smps3-in-supply = <&tps65090_dcdc3_reg>; + smps4-in-supply = <&tps65090_dcdc2_reg>; + smps7-in-supply = <&tps65090_dcdc2_reg>; + smps8-in-supply = <&tps65090_dcdc2_reg>; + smps9-in-supply = <&tps65090_dcdc2_reg>; + ldo1-in-supply = <&tps65090_dcdc2_reg>; + ldo2-in-supply = <&tps65090_dcdc2_reg>; + ldo3-in-supply = <&palmas_smps3_reg>; + ldo4-in-supply = <&tps65090_dcdc2_reg>; + ldo5-in-supply = <&vdd_ac_bat_reg>; + ldo6-in-supply = <&tps65090_dcdc2_reg>; + ldo7-in-supply = <&tps65090_dcdc2_reg>; + ldo8-in-supply = <&tps65090_dcdc3_reg>; + ldo9-in-supply = <&palmas_smps9_reg>; + ldoln-in-supply = <&tps65090_dcdc1_reg>; + ldousb-in-supply = <&tps65090_dcdc1_reg>; + + regulators { + smps12 { + regulator-name = "vddio-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + palmas_smps3_reg: smps3 { + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + smps457 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8 { + regulator-name = "avdd-pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + palmas_smps9_reg: smps9 { + regulator-name = "sdhci-vdd-sd-slot"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo1 { + regulator-name = "avdd-cam1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo2 { + regulator-name = "avdd-cam2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + avdd_1v2_reg: ldo3 { + regulator-name = "avdd-dsi-csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo4 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + palmas_ldo6_reg: ldo6 { + regulator-name = "vdd-sensor-2v85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo7 { + regulator-name = "vdd-af-cam1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + ldo9 { + regulator-name = "vddio-sdmmc-2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "hvdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "avdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1 { + regulator-name = "rail-3v3"; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + regen2 { + regulator-name = "rail-5v0"; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + + mmc@78000400 { + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; + }; + + mmc@78000600 { + bus-width = <8>; + status = "okay"; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra114-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&usb3_vbus_reg>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + vdd_ac_bat_reg: regulator-acbat { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + dvdd_ts_reg: regulator-ts { + compatible = "regulator-fixed"; + regulator-name = "dvdd_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; + + usb1_vbus_reg: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&tps65090_dcdc1_reg>; + }; + + usb3_vbus_reg: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&tps65090_dcdc1_reg>; + }; + + vdd_hdmi_reg: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vdd_hdmi_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&tps65090_dcdc1_reg>; + }; + + vdd_cam_1v8_reg: regulator-cam { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam_1v8_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&palmas_gpio 6 0>; + }; + + vdd_5v0_hdmi: regulator-hdmicon { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&tps65090_dcdc1_reg>; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-dalmore", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Dalmore"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra114-roth.dts b/arch/arm/boot/dts/nvidia/tegra114-roth.dts new file mode 100644 index 000000000000..b9d00009d1f4 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114-roth.dts @@ -0,0 +1,1108 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "NVIDIA SHIELD"; + compatible = "nvidia,roth", "nvidia,tegra114"; + + chosen { + /* SHIELD's bootloader's arguments need to be overridden */ + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; + /* SHIELD's bootloader will place initrd at this address */ + linux,initrd-start = <0x82000000>; + linux,initrd-end = <0x82800000>; + }; + + aliases { + serial0 = &uartd; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + /* memory >= 0x79600000 is reserved for firmware usage */ + reg = <0x80000000 0x79600000>; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_1v2_ap>; + + panel@0 { + compatible = "lg,lh500wx1-sd03"; + reg = <0>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs6_n_pi13 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,rcv-sel = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb5", + "pbb6", + "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1", + "pcc2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad12_ph4", + "gmi_ad15_ph7", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3", + "gmi_ad13_ph5", + "gmi_ad8_ph0", + "gmi_clk_pk1", + "gmi_cs2_n_pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6", + "gmi_cs0_n_pj0", + "gmi_cs4_n_pk2", + "gmi_cs7_n_pi6", + "gmi_dqs_p_pj3", + "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row4_pr4", + "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + /* Usable on reworked devices only */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + regulator@43 { + compatible = "ti,tps51632"; + reg = <0x43>; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1520000>; + regulator-always-on; + regulator-boot-on; + }; + + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + regulators { + smps12 { + regulator-name = "vdd-ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: smps3 { + regulator-name = "vdd-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + smps457 { + regulator-name = "vdd-soc"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8 { + regulator-name = "avdd-pll-1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9 { + regulator-name = "vdd-2v85-emmc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + smps10_out1 { + regulator-name = "vdd-fan"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out2 { + regulator-name = "vdd-5v0-sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "vdd-2v8-display"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v2_ap: ldo3 { + regulator-name = "avdd-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5 { + regulator-name = "avdd-hdmi-pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo6 { + regulator-name = "vdd-sensor-2v8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + vddio_sdmmc3: ldo9 { + regulator-name = "vddio-sdmmc3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "avdd-usb-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regen1 { + regulator-name = "rail-3v3"; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + regen2 { + regulator-name = "rail-5v0"; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + }; + + /* SD card */ + mmc@78000400 { + status = "okay"; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc3>; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + }; + + /* eMMC */ + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* External USB port (must be powered) */ + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + interrupts = ; + /* Should be changed to "otg" once we have vbus_supply */ + /* As of now, USB devices need to be powered externally */ + dr_mode = "host"; + }; + + /* SHIELD controller */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 1 40000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + power-supply = <&lcd_bl_en>; + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Back"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-home { + label = "Home"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + lcd_bl_en: regulator-lcden { + compatible = "regulator-fixed"; + regulator-name = "lcd_bl_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vdd_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + regulator-1v8ts { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + regulator-3v3ts { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + regulator-1v8com { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_com"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + regulator-3v3com { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_sys>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra114-tn7.dts b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts new file mode 100644 index 000000000000..f02d8c79eee7 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "Tegra Note 7"; + compatible = "nvidia,tn7", "nvidia,tegra114"; + + chosen { + /* TN7's bootloader's arguments need to be overridden */ + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; + /* TN7's bootloader will place initrd at this address */ + linux,initrd-start = <0x82000000>; + linux,initrd-end = <0x82800000>; + }; + + aliases { + serial0 = &uartd; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + /* memory >= 0x37e00000 is reserved for firmware usage */ + reg = <0x80000000 0x37e00000>; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_1v2_ap>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldoln-in-supply = <&vdd_smps10_out2>; + + regulators { + smps123 { + regulator-name = "vd-cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45 { + regulator-name = "vd-soc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7 { + regulator-name = "vd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: smps8 { + regulator-name = "vs-pmu-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_2v9_sys: smps9 { + regulator-name = "vs-sys-2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1 { + regulator-name = "va-pllx"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v2_ap: ldo2 { + regulator-name = "va-ap-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vd-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vd-ts-hv"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5 { + regulator-name = "va-cam2-hv"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo6 { + regulator-name = "va-sns-hv"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo7 { + regulator-name = "va-cam1-hv"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo8 { + regulator-name = "va-ap-rtc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + ti,enable-ldo8-tracking; + regulator-always-on; + regulator-boot-on; + }; + + ldo9 { + regulator-name = "vi-sdcard"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + ldousb { + regulator-name = "avdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "va-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + }; + + /* eMMC */ + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + interrupts = ; + /* Should be changed to "otg" once we have vbus_supply */ + /* As of now, USB devices need to be powered externally */ + dr_mode = "host"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 1 40000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + power-supply = <&lcd_bl_en>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + /* FIXME: output of BQ24192 */ + vs_sys: regulator-vs { + compatible = "regulator-fixed"; + regulator-name = "VS_SYS"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + lcd_bl_en: regulator-lcden { + compatible = "regulator-fixed"; + regulator-name = "VDD_LCD_BL"; + regulator-min-microvolt = <16500000>; + regulator-max-microvolt = <16500000>; + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vs_sys>; + regulator-boot-on; + }; + + vdd_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "VD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + regulator-boot-on; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi new file mode 100644 index 000000000000..09996acad639 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -0,0 +1,850 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include + +/ { + compatible = "nvidia,tegra114"; + interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x0>; + }; + + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + + host1x@50000000 { + compatible = "nvidia,tegra114-host1x"; + reg = <0x50000000 0x00028000>; + interrupts = , /* syncpt */ + ; /* general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; + reset-names = "host1x", "mc"; + iommus = <&mc TEGRA_SWGROUP_HC>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + gr2d@54140000 { + compatible = "nvidia,tegra114-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_GR2D>; + resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; + reset-names = "2d", "mc"; + + iommus = <&mc TEGRA_SWGROUP_G2>; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra114-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_GR3D>; + resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; + reset-names = "3d", "mc"; + + iommus = <&mc TEGRA_SWGROUP_NV>; + }; + + dc@54200000 { + compatible = "nvidia,tegra114-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DISP1>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DC>; + + nvidia,head = <0>; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra114-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DISP2>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DCB>; + + nvidia,head = <1>; + + rgb { + status = "disabled"; + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_HDMI>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + dsia: dsi@54300000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIA>, + <&tegra_car TEGRA114_CLK_DSIALP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsib: dsi@54400000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gic: interrupt-controller@50041000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x1000>, + <0x50044000 0x2000>, + <0x50046000 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; + reg = <0x60004000 0x100>, + <0x60004100 0x50>, + <0x60004200 0x50>, + <0x60004300 0x50>, + <0x60004400 0x50>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + timer@60005000 { + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA114_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra114-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + flow-controller@60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra114-apbdma"; + reg = <0x6000a000 0x1400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA114_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + ahb: ahb@6000c000 { + compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; + reg = <0x6000c000 0x150>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinmux 0 0 246>; + }; + + vde@6001a000 { + compatible = "nvidia,tegra114-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA114_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; + }; + + apbmisc@70000800 { + compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; + + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra114-pinmux"; + reg = <0x70000868 0x148>, /* Pad control registers */ + <0x70003000 0x40c>; /* Mux registers */ + }; + + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the compatible is + * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". + */ + uarta: serial@70006000 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA114_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d800 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_RTC>; + }; + + kbc@7000e200 { + compatible = "nvidia,tegra114-kbc"; + reg = <0x7000e200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; + status = "disabled"; + }; + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra114-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra114-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA114_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + mc: memory-controller@70019000 { + compatible = "nvidia,tegra114-mc"; + reg = <0x70019000 0x1000>; + clocks = <&tegra_car TEGRA114_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #reset-cells = <1>; + #iommu-cells = <1>; + }; + + ahub@70080000 { + compatible = "nvidia,tegra114-ahub"; + reg = <0x70080000 0x200>, + <0x70080200 0x100>, + <0x70081000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, + <&tegra_car TEGRA114_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 154>; /* adx */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "adx"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70080300 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080300 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA114_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70080400 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080400 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA114_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70080500 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080500 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA114_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70080600 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080600 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA114_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70080700 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080700 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA114_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + + mipi: mipi@700e3000 { + compatible = "nvidia,tegra114-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + + mmc@78000000 { + compatible = "nvidia,tegra114-sdhci"; + reg = <0x78000000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; + clock-names = "sdhci"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@78000200 { + compatible = "nvidia,tegra114-sdhci"; + reg = <0x78000200 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; + clock-names = "sdhci"; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@78000400 { + compatible = "nvidia,tegra114-sdhci"; + reg = <0x78000400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; + clock-names = "sdhci"; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@78000600 { + compatible = "nvidia,tegra114-sdhci"; + reg = <0x78000600 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; + clock-names = "sdhci"; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disabled"; + }; + + usb@7d000000 { + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000>, + <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USBD>, + <&tegra_car TEGRA114_CLK_PLL_U>, + <&tegra_car TEGRA114_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USB3>, + <&tegra_car TEGRA114_CLK_PLL_U>, + <&tegra_car TEGRA114_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + interrupt-parent = <&gic>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi new file mode 100644 index 000000000000..970f33dd9101 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi @@ -0,0 +1,1487 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016-2019 Toradex AG + * + */ + +#include + +/ { + clock@60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 0x8000000a + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x77e30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 0x80000012 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x76230303 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 0x80000017 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74a30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 0x8000001e + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74230403 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 0x80000026 + 0x00000001 0x00000001 + 0x00000003 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0503 + 0x73c30504 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 0x80000040 + 0x00000001 0x00000001 + 0x00000004 0x00000002 + 0x00000003 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000004 0x00000006 + 0x06040203 0x000a0504 + 0x73840a05 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 0x80000040 + 0x00000001 0x00000002 + 0x00000007 0x00000004 + 0x00000004 0x00000001 + 0x00000002 0x00000007 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000b0607 + 0x77450e08 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 0x80000040 + 0x00000001 0x00000002 + 0x00000009 0x00000005 + 0x00000006 0x00000001 + 0x00000002 0x00000008 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000d0709 + 0x7586120a 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 0x80000040 + 0x00000002 0x00000003 + 0x0000000c 0x00000007 + 0x00000008 0x00000001 + 0x00000002 0x00000009 + 0x00000002 0x00000002 + 0x00000005 0x00000006 + 0x06050202 0x0010090c + 0x7428180d 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 0x80000040 + 0x00000003 0x00000004 + 0x0000000e 0x00000009 + 0x0000000a 0x00000001 + 0x00000003 0x0000000b + 0x00000002 0x00000002 + 0x00000005 0x00000007 + 0x07050202 0x00130b0e + 0x73a91b0f 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b 0x80000040 + 0x00000004 0x00000005 + 0x00000013 0x0000000c + 0x0000000d 0x00000002 + 0x00000003 0x0000000c + 0x00000002 0x00000002 + 0x00000006 0x00000008 + 0x08060202 0x00170e13 + 0x736c2414 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d 0x80000040 + 0x00000005 0x00000006 + 0x00000016 0x0000000e + 0x0000000f 0x00000002 + 0x00000004 0x0000000e + 0x00000002 0x00000002 + 0x00000006 0x00000009 + 0x09060202 0x001a1016 + 0x734e2a17 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 0x00000003 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000060 + 0x00000000 0x00000018 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000007 0x0000000f + 0x00000005 0x00000005 + 0x00000004 0x00000005 + 0x00000004 0x00000000 + 0x00000000 0x00000005 + 0x00000005 0x00000064 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000007 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 0x00000005 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x0000009a + 0x00000000 0x00000026 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000007 0x0000000f + 0x00000006 0x00000006 + 0x00000004 0x00000005 + 0x00000004 0x00000000 + 0x00000000 0x00000005 + 0x00000005 0x000000a0 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x0000000b 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 0x0000000a + 0x00000000 0x00000001 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000134 + 0x00000000 0x0000004d + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000008 0x0000000f + 0x0000000c 0x0000000c + 0x00000004 0x00000005 + 0x00000004 0x00000000 + 0x00000000 0x00000005 + 0x00000005 0x0000013f + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000015 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 0x00000011 + 0x00000000 0x00000002 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000202 + 0x00000000 0x00000080 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x0000000f 0x0000000f + 0x00000013 0x00000013 + 0x00000004 0x00000005 + 0x00000004 0x00000001 + 0x00000000 0x00000005 + 0x00000005 0x00000213 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000022 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 0x0000001a + 0x00000000 0x00000003 + 0x00000001 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000001 + 0x00000001 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000304 + 0x00000000 0x000000c1 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000018 0x0000000f + 0x0000001c 0x0000001c + 0x00000004 0x00000005 + 0x00000004 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x0000031c + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000033 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 0x00000035 + 0x00000000 0x00000006 + 0x00000002 0x00000005 + 0x0000000a 0x00000005 + 0x0000000b 0x00000002 + 0x00000002 0x00000003 + 0x00000003 0x00000000 + 0x00000005 0x00000005 + 0x00000006 0x00000002 + 0x00000000 0x00000004 + 0x00000006 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000003 + 0x0000000d 0x0000000f + 0x00000011 0x00000607 + 0x00000000 0x00000181 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000032 0x0000000f + 0x00000038 0x00000038 + 0x00000004 0x00000005 + 0x00000004 0x00000006 + 0x00000000 0x00000005 + 0x00000005 0x00000638 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00008000 0x00000000 + 0x00000000 0x00008000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00090000 0x00090000 + 0x00090000 0x00090000 + 0x00009000 0x00009000 + 0x00009000 0x00009000 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000707 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000066 0x00000000 + 0x00000100 0x000e000e + 0x00000000 0x00000003 + 0x0000d2b3 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d 0x0000004d + 0x00000000 0x00000009 + 0x00000003 0x00000004 + 0x00000008 0x00000002 + 0x00000009 0x00000003 + 0x00000003 0x00000002 + 0x00000002 0x00000000 + 0x00000003 0x00000003 + 0x00000005 0x00000002 + 0x00000000 0x00000002 + 0x00000007 0x00020000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000001 + 0x0000000e 0x00000010 + 0x00000012 0x000008e4 + 0x00000000 0x00000239 + 0x00000001 0x00000008 + 0x00000001 0x00000000 + 0x0000004b 0x0000000e + 0x00000052 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x00000008 + 0x00000000 0x00000005 + 0x00000005 0x00000924 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0x002c00a0 0x00008000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00098000 0x00098000 + 0x00000000 0x00098000 + 0x00098000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00050000 0x00050000 + 0x00050000 0x00050000 + 0x00005000 0x00005000 + 0x00005000 0x00005000 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000096 0x00000000 + 0x00000100 0x0173000e + 0x00000000 0x00000003 + 0x000052a3 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 0x00000066 + 0x00000000 0x0000000c + 0x00000004 0x00000004 + 0x00000008 0x00000002 + 0x0000000a 0x00000004 + 0x00000004 0x00000002 + 0x00000002 0x00000000 + 0x00000003 0x00000003 + 0x00000005 0x00000002 + 0x00000000 0x00000001 + 0x00000008 0x00020000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0000000f 0x00000010 + 0x00000012 0x00000bd1 + 0x00000000 0x000002f4 + 0x00000001 0x00000008 + 0x00000001 0x00000000 + 0x00000063 0x0000000f + 0x0000006c 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x0000000b + 0x00000000 0x00000005 + 0x00000005 0x00000c11 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0x002c00a0 0x00008000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00070000 0x00070000 + 0x00000000 0x00070000 + 0x00070000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00038000 0x00038000 + 0x00038000 0x00038000 + 0x00003800 0x00003800 + 0x00003800 0x00003800 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x000000c6 0x00000000 + 0x00000100 0x015b000e + 0x00000000 0x00000003 + 0x000052a3 0x8000188b + 0x00000009 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 0x00000088 + 0x00000000 0x00000010 + 0x00000006 0x00000006 + 0x00000009 0x00000002 + 0x0000000d 0x00000006 + 0x00000006 0x00000002 + 0x00000002 0x00000000 + 0x00000003 0x00000003 + 0x00000006 0x00000002 + 0x00000000 0x00000001 + 0x00000009 0x00030000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000010 0x00000012 + 0x00000014 0x00000fd6 + 0x00000000 0x000003f5 + 0x00000002 0x0000000b + 0x00000001 0x00000000 + 0x00000085 0x00000012 + 0x00000090 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x00000010 + 0x00000000 0x00000006 + 0x00000006 0x00001017 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0xe01200b1 0x00008000 + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00054000 0x00054000 + 0x00000000 0x00054000 + 0x00054000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0000000c 0x0000000c + 0x0000000c 0x0000000c + 0x0000000c 0x0000000c + 0x0000000c 0x0000000c + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0606003f + 0x00000000 0x00000000 + 0x00000100 0x0139000e + 0x00000000 0x00000003 + 0x000042a0 0x80002062 + 0x0000000a + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b 0x0000009b + 0x00000000 0x00000013 + 0x00000007 0x00000007 + 0x0000000b 0x00000003 + 0x00000010 0x00000007 + 0x00000007 0x00000002 + 0x00000002 0x00000000 + 0x00000005 0x00000005 + 0x0000000a 0x00000002 + 0x00000000 0x00000003 + 0x0000000b 0x00070000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000002 + 0x00000012 0x00000016 + 0x00000018 0x00001208 + 0x00000000 0x00000482 + 0x00000002 0x0000000d + 0x00000001 0x00000000 + 0x00000097 0x00000015 + 0x000000a3 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x00000013 + 0x00000000 0x00000006 + 0x00000006 0x00001248 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0xe00e00b1 0x00008000 + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00048000 0x00048000 + 0x00000000 0x00048000 + 0x00048000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0000000d 0x0000000d + 0x0000000d 0x0000000d + 0x0000000d 0x0000000d + 0x0000000d 0x0000000d + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0606003f + 0x00000000 0x00000000 + 0x00000100 0x0127000e + 0x00000000 0x00000003 + 0x000040a0 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 0x000000cd + 0x00000000 0x00000019 + 0x0000000a 0x00000008 + 0x0000000d 0x00000004 + 0x00000013 0x0000000a + 0x0000000a 0x00000004 + 0x00000002 0x00000000 + 0x00000006 0x00000006 + 0x0000000b 0x00000002 + 0x00000000 0x00000002 + 0x0000000d 0x00080000 + 0x00000004 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000001 + 0x00000014 0x00000018 + 0x0000001a 0x000017e2 + 0x00000000 0x000005f8 + 0x00000003 0x00000011 + 0x00000001 0x00000000 + 0x000000c7 0x00000018 + 0x000000d7 0x00000200 + 0x00000005 0x00000006 + 0x00000005 0x00000019 + 0x00000000 0x00000008 + 0x00000008 0x00001822 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0xe00700b1 0x00008000 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00034000 0x00034000 + 0x00000000 0x00034000 + 0x00034000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000000 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x61861820 + 0x00514514 0x00514514 + 0x61861800 0x0606003f + 0x00000000 0x00000000 + 0x00000100 0x00f7000e + 0x00000000 0x00000004 + 0x00004080 0x80003012 + 0x0000000f + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b 0x000000f0 + 0x00000000 0x0000001e + 0x0000000b 0x00000009 + 0x0000000f 0x00000005 + 0x00000016 0x0000000b + 0x0000000b 0x00000004 + 0x00000002 0x00000000 + 0x00000007 0x00000007 + 0x0000000d 0x00000002 + 0x00000000 0x00000002 + 0x0000000f 0x000a0000 + 0x00000004 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000001 + 0x00000016 0x0000001a + 0x0000001c 0x00001be7 + 0x00000000 0x000006f9 + 0x00000004 0x00000015 + 0x00000001 0x00000000 + 0x000000e7 0x0000001b + 0x000000fb 0x00000200 + 0x00000006 0x00000007 + 0x00000006 0x0000001e + 0x00000000 0x0000000a + 0x0000000a 0x00001c28 + 0x00000000 0x00000000 + 0x00000000 0x104ab898 + 0xe00400b1 0x00008000 + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0002c000 0x0002c000 + 0x00000000 0x0002c000 + 0x0002c000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000008 0x00000008 + 0x00000008 0x00000008 + 0x00000008 0x00000008 + 0x00000008 0x00000008 + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000000 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x5d75d720 + 0x00514514 0x00514514 + 0x5d75d700 0x0606003f + 0x00000000 0x00000000 + 0x00000128 0x00cd000e + 0x00000000 0x00000004 + 0x00004080 0x800037ea + 0x00000011 + >; + }; + }; + }; + + opp-table-actmon { + /delete-node/ opp-1200000000; + }; + + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts new file mode 100644 index 000000000000..2df2d8a6b552 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016-2019 Toradex AG + */ + +/dts-v1/; + +#include +#include "tegra124-apalis.dtsi" + +/ { + model = "Toradex Apalis TK1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", + "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@40"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie@1003000 { + pci@1,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + gpio: gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* + * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) + */ + i2c@7000c400 { + status = "okay"; + }; + + /* + * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor + * on carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* I2C4 (DDC): unused */ + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <50000000>; + }; + + /* SPI4: Apalis SPI2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <50000000>; + }; + + /* Apalis Serial ATA */ + sata@70020000 { + status = "okay"; + target-5v-supply = <®_5v0>; + target-12v-supply = <®_12v0>; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + status = "okay"; + }; + + /* Apalis MMC1 */ + mmc@700b0000 { + status = "okay"; + bus-width = <4>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vddio_sdmmc1>; + }; + + /* Apalis SD1 */ + mmc@700b0400 { + status = "okay"; + bus-width = <4>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V_SW"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts new file mode 100644 index 000000000000..f4521fd15f6a --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2016-2018 Toradex AG + */ + +/dts-v1/; + +#include +#include "tegra124-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis TK1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", + "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", + "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@40"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie@1003000 { + pci@1,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor + * on carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* + * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 + * (e.g. display EDID) + */ + i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <50000000>; + }; + + /* SPI4: Apalis SPI2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <50000000>; + }; + + /* Apalis Serial ATA */ + sata@70020000 { + status = "okay"; + target-5v-supply = <®_5v0>; + target-12v-supply = <®_12v0>; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + status = "okay"; + }; + + /* Apalis MMC1 */ + mmc@700b0000 { + status = "okay"; + bus-width = <4>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vddio_sdmmc1>; + }; + + /* Apalis SD1 */ + mmc@700b0400 { + status = "okay"; + bus-width = <4>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V_SW"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi new file mode 100644 index 000000000000..75cfe718737c --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi @@ -0,0 +1,2076 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2016-2018 Toradex AG + */ + +#include "tegra124.dtsi" +#include "tegra124-apalis-emc.dtsi" + +/* + * Toradex Apalis TK1 Module Device Tree + * Compatible for Revisions 2GB: V1.2A + */ +/ { + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + pcie@1003000 { + status = "okay"; + + avddio-pex-supply = <®_1v05_vdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; + + /* Apalis PCIe (additional lane Apalis type specific) */ + pci@1,0 { + /* PCIE1_RX/TX and TS_DIFF1/2 */ + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1"; + }; + + /* I210 Gigabit Ethernet Controller (On-module) */ + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; + phy-names = "pcie-0"; + status = "okay"; + + ethernet@0,0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v05_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + gpu@57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <®_vdd_gpu>; + }; + + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-din-pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-dout-pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-sclk-pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-mclk1-pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_ON */ + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAM1_MCLK */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + dap2-fs-pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-sclk-pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-din-pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-dout-pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { /* DAP1_RESET */ + nvidia,pins = "pbb3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out-pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis GPIO */ + usb-vbus-en0-pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb-vbus-en1-pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l1-rst-n-pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l1-clkreq-n-pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp-hpd-pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis HDMI1_CEC */ + hdmi-cec-pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis HDMI1_HPD */ + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis I2C1 */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1-i2c-sda-pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C3 (CAM) */ + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam-i2c-sda-pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C4 (DDC) */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc-sda-pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis MMC1 */ + sdmmc1-cd-n-pv3 { /* CD# GPIO */ + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-out-pw5 { /* D5 GPIO */ + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat3-py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat2-py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat1-py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat0-py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-clk-pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd-pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-req-pcc5 { /* D4 GPIO */ + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb-vbus-en2-pff1 { /* D7 GPIO */ + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM */ + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SATA1_ACT# */ + dap1-dout-pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cmd-pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat3-pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat2-pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat1-pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat0-pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cd-n-pv2 { /* CD# GPIO */ + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-in-pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + ulpi-clk-py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-dir-py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-nxt-py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-stp-py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI2 */ + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + pb1 { /* DCD GPIO */ + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { /* RI GPIO */ + nvidia,pins = "pk7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-txd-pu0 { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-rxd-pu1 { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-cts-n-pu2 { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-rts-n-pu3 { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-cts-n-pa1 { /* DSR GPIO */ + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rts-n-pc0 { /* DTR GPIO */ + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART2 */ + uart2-txd-pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rts-n-pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART3 */ + uart3-txd-pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rxd-pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART4 */ + uart4-rxd-pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart4-txd-pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_EN */ + gen2-i2c-sda-pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBH_OC# */ + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBO1_OC# */ + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pex-wake-n-pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE_PWR_REQ */ + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CPU_PWR_REQ */ + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* DVFS */ + dvfs-pwm-px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs-clk-px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC */ + sdmmc4-dat0-paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat1-paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat2-paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat3-paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat4-paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat5-paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat6-paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat7-paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-clk-pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-cmd-pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* JTAG_RTCK */ + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_DEV_OFF# */ + ulpi-data5-po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_RESET# */ + kb-row10-ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_WAKE# */ + ulpi-data4-po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT1# */ + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT2# */ + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT3# */ + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT4# */ + pj0 { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_RESET */ + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU SPI */ + gpio-x4-aud-px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x5-aud-px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud-px6 { /* MCU_CS */ + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x7-aud-px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w2-aud-pw2 { /* MCU_CSEZP */ + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CLK_32K */ + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CPU_OC_INT */ + clk-32k-out-pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWR_I2C */ + pwr-i2c-scl-pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr-i2c-sda-pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* PWR_INT_N */ + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_MOCI_CTRL */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_OUT_N */ + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_IN */ + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row1-pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Configure level-shifter as output for HDA */ + kb-row11-ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_OUT */ + kb-col5-pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col6-pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col7-pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_OE */ + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col1-pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col2-pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col4-pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row2-pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ + pi6 { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_INT */ + gpio-w3-aud-pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pc7 { /* NC */ + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { /* NC */ + nvidia,pins = "pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { /* NC */ + nvidia,pins = "pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { /* NC */ + nvidia,pins = "pg2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { /* NC */ + nvidia,pins = "pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { /* NC */ + nvidia,pins = "pg4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { /* NC */ + nvidia,pins = "ph4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { /* NC */ + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { /* NC */ + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { /* NC */ + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { /* NC */ + nvidia,pins = "pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { /* NC */ + nvidia,pins = "pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { /* NC */ + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { /* NC */ + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { /* NC */ + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { /* NC */ + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { /* NC */ + nvidia,pins = "pk1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { /* NC */ + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { /* NC */ + nvidia,pins = "pk4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-fs-pn0 { /* NC */ + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-din-pn1 { /* NC */ + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-sclk-pn3 { /* NC */ + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data7-po0 { /* NC */ + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data0-po1 { /* NC */ + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data1-po2 { /* NC */ + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data2-po3 { /* NC */ + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data3-po4 { /* NC */ + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data6-po7 { /* NC */ + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-fs-pp4 { /* NC */ + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-din-pp5 { /* NC */ + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-dout-pp6 { /* NC */ + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-sclk-pp7 { /* NC */ + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col3-pq3 { /* NC */ + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row3-pr3 { /* NC */ + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row4-pr4 { /* NC */ + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5-pr5 { /* NC */ + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row6-pr6 { /* NC */ + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row7-pr7 { /* NC */ + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row8-ps0 { /* NC */ + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row9-ps1 { /* NC */ + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row12-ps4 { /* NC */ + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row13-ps5 { /* NC */ + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row14-ps6 { /* NC */ + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row15-ps7 { /* NC */ + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row16-pt0 { /* NC */ + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row17-pt1 { /* NC */ + nvidia,pins = "kb_row17_pt1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { /* NC */ + nvidia,pins = "pu5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * PCB Version Indication: V1.2 and later have GPIO_PV0 + * wired to GND, was NC before + */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { /* NC */ + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x1-aud-px1 { /* NC */ + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud-px3 { /* NC */ + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { /* NC */ + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { /* NC */ + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { /* NC */ + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-req-pee1 { /* NC */ + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-mclk1-req-pee2 { /* NC */ + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output + * driver enabled aka not tristated and input driver + * enabled as well as it features some magic properties + * even though the external loopback is disabled and the + * internal loopback used as per + * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 + * bits being set to 0xfffd according to the TRM! + */ + sdmmc3-clk-lb-out-pee4 { /* NC */ + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006200 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006300 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; + }; + + /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vddio>; + VDDIO-supply = <®_1v8_vddio>; + clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + ams,system-power-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + + gpio2-7 { + pins = "gpio2", /* PWR_EN_+V3.3 */ + "gpio7"; /* +V1.6_LPO */ + function = "gpio"; + bias-pull-up; + }; + }; + + regulators { + vsup-sd2-supply = <®_module_3v3>; + vsup-sd3-supply = <®_module_3v3>; + vsup-sd4-supply = <®_module_3v3>; + vsup-sd5-supply = <®_module_3v3>; + vin-ldo0-supply = <®_1v35_vddio_ddr>; + vin-ldo1-6-supply = <®_module_3v3>; + vin-ldo2-5-7-supply = <®_1v8_vddio>; + vin-ldo3-4-supply = <®_module_3v3>; + vin-ldo9-10-supply = <®_module_3v3>; + vin-ldo11-supply = <®_module_3v3>; + + reg_vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + reg_1v35_vddio_ddr: sd2 { + regulator-name = + "+V1.35_VDDIO_DDR(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = + "+V1.35_VDDIO_DDR(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_1v05_vdd: sd4 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + reg_1v8_vddio: sd5 { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v05_avdd: ldo0 { + regulator-name = "+V1.05_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + vddio_sdmmc1: ldo1 { + regulator-name = "VDDIO_SDMMC1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "+V1.2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+V1.05_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + /* 1.8V for LVDS, 3.3V for eDP */ + ldo4 { + regulator-name = "AVDD_LVDS0_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* LDO5 not used */ + + vddio_sdmmc3: ldo6 { + regulator-name = "VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + /* LDO7 not used */ + + ldo9 { + regulator-name = "+V3.3_ETH(ldo9)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo10 { + regulator-name = "+V3.3_ETH(ldo10)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo11 { + regulator-name = "+V1.8_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + /* + * TMP451 temperature sensor + * Note: THERM_N directly connected to AS3722 PMIC THERM + */ + temp-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + #thermal-sensor-cells = <1>; + vcc-supply = <®_module_3v3>; + }; + }; + + /* SPI2: MCU SPI */ + spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set power_off bit in ResetControl register of AS3722 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; + }; + + sata@70020000 { + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; + phy-names = "sata-0"; + avdd-supply = <®_1v05_vdd>; + hvdd-supply = <®_module_3v3>; + vddio-supply = <®_1v05_vdd>; + }; + + usb@70090000 { + /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; + phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; + + avddio-pex-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-usb-ss-pll-supply = <®_1v05_vdd>; + avdd-usb-supply = <®_module_3v3>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-usb-ss-pll-e-supply = <®_module_3v3>; + hvdd-usb-ss-supply = <®_module_3v3>; + }; + + padctl@7009f000 { + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + status = "okay"; + nvidia,function = "xusb"; + }; + + usb2-1 { + status = "okay"; + nvidia,function = "xusb"; + }; + + usb2-2 { + status = "okay"; + nvidia,function = "xusb"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + status = "okay"; + nvidia,function = "usb3-ss"; + }; + + pcie-1 { + status = "okay"; + nvidia,function = "usb3-ss"; + }; + + pcie-2 { + status = "okay"; + nvidia,function = "pcie"; + }; + + pcie-3 { + status = "okay"; + nvidia,function = "pcie"; + }; + + pcie-4 { + status = "okay"; + nvidia,function = "pcie"; + }; + }; + }; + + sata { + status = "okay"; + + lanes { + sata-0 { + status = "okay"; + nvidia,function = "sata"; + }; + }; + }; + }; + + ports { + /* USBO1 */ + usb2-0 { + status = "okay"; + mode = "otg"; + usb-role-switch; + vbus-supply = <®_usbo1_vbus>; + }; + + /* USBH2 */ + usb2-1 { + status = "okay"; + mode = "host"; + vbus-supply = <®_usbh_vbus>; + }; + + /* USBH4 */ + usb2-2 { + status = "okay"; + mode = "host"; + vbus-supply = <®_usbh_vbus>; + }; + + usb3-0 { + status = "okay"; + nvidia,usb2-companion = <2>; + vbus-supply = <®_usbh_vbus>; + }; + + usb3-1 { + status = "okay"; + nvidia,usb2-companion = <0>; + vbus-supply = <®_usbo1_vbus>; + }; + }; + }; + + /* eMMC */ + mmc@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ + mmc-ddr-1_8v; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <®_vdd_cpu>; + }; + + ahub@70300000 { + i2s@70301200 { + status = "okay"; + }; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <®_vdd_cpu>; + }; + }; + + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.05_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <®_1v05_vdd>; + }; + + reg_3v3_mxm: regulator-3v3-mxm { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_MXM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_1v05_vdd>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + /* PWR_EN_+V3.3 */ + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3_mxm>; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis TK1"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem-thermal { + trips { + mem-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + trips { + gpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi new file mode 100644 index 000000000000..554c8089491c --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi @@ -0,0 +1,2068 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016-2019 Toradex AG + */ + +#include "tegra124.dtsi" +#include "tegra124-apalis-emc.dtsi" + +/* + * Toradex Apalis TK1 Module Device Tree + * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A + */ +/ { + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + pcie@1003000 { + status = "okay"; + avddio-pex-supply = <®_1v05_vdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; + + /* Apalis PCIe (additional lane Apalis type specific) */ + pci@1,0 { + /* PCIE1_RX/TX and TS_DIFF1/2 */ + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1"; + }; + + /* I210 Gigabit Ethernet Controller (On-module) */ + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; + phy-names = "pcie-0"; + status = "okay"; + + ethernet@0,0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v05_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + gpu@57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <®_vdd_gpu>; + }; + + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-din-pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-dout-pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-sclk-pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-mclk1-pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_ON */ + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAM1_MCLK */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + dap2-fs-pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-sclk-pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-din-pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-dout-pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { /* DAP1_RESET */ + nvidia,pins = "pbb3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out-pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis GPIO */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc-sda-pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l1-rst-n-pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex-l1-clkreq-n-pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp-hpd-pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis HDMI1_CEC */ + hdmi-cec-pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis HDMI1_HPD */ + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis I2C1 */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1-i2c-sda-pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C2 (DDC) */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2-i2c-sda-pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C3 (CAM) */ + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam-i2c-sda-pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis MMC1 */ + sdmmc1-cd-n-pv3 { /* CD# GPIO */ + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-out-pw5 { /* D5 GPIO */ + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat3-py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat2-py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat1-py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-dat0-py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-clk-pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd-pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-req-pcc5 { /* D4 GPIO */ + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb-vbus-en2-pff1 { /* D7 GPIO */ + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM */ + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SATA1_ACT# */ + dap1-dout-pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cmd-pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat3-pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat2-pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat1-pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-dat0-pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cd-n-pv2 { /* CD# GPIO */ + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-in-pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + ulpi-clk-py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-dir-py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-nxt-py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-stp-py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI2 */ + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + pb1 { /* DCD GPIO */ + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { /* RI GPIO */ + nvidia,pins = "pk7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-txd-pu0 { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-rxd-pu1 { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-cts-n-pu2 { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1-rts-n-pu3 { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-cts-n-pa1 { /* DSR GPIO */ + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rts-n-pc0 { /* DTR GPIO */ + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART2 */ + uart2-txd-pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rts-n-pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART3 */ + uart3-txd-pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rxd-pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART4 */ + uart4-rxd-pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart4-txd-pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_EN */ + usb-vbus-en1-pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBH_OC# */ + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + usb-vbus-en0-pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBO1_OC# */ + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pex-wake-n-pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE_PWR_REQ */ + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CPU_PWR_REQ */ + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* DVFS */ + dvfs-pwm-px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs-clk-px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC */ + sdmmc4-dat0-paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat1-paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat2-paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat3-paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat4-paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat5-paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat6-paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat7-paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-clk-pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-cmd-pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* JTAG_RTCK */ + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_DEV_OFF# */ + ulpi-data5-po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_RESET# */ + kb-row10-ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_WAKE# */ + ulpi-data4-po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT1# */ + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT2# */ + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT3# */ + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT4# */ + pj0 { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_RESET */ + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU SPI */ + gpio-x4-aud-px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x5-aud-px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud-px6 { /* MCU_CS */ + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x7-aud-px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w2-aud-pw2 { /* MCU_CSEZP */ + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CLK_32K */ + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CPU_OC_INT */ + clk-32k-out-pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWR_I2C */ + pwr-i2c-scl-pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr-i2c-sda-pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* PWR_INT_N */ + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_MOCI_CTRL */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_OUT_N */ + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_IN */ + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row1-pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Configure level-shifter as output for HDA */ + kb-row11-ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_OUT */ + kb-col5-pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col6-pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col7-pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_OE */ + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col1-pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col2-pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col4-pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row2-pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ + pi6 { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_INT */ + gpio-w3-aud-pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pc7 { /* NC */ + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { /* NC */ + nvidia,pins = "pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { /* NC */ + nvidia,pins = "pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { /* NC */ + nvidia,pins = "pg2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { /* NC */ + nvidia,pins = "pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { /* NC */ + nvidia,pins = "pg4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { /* NC */ + nvidia,pins = "ph4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { /* NC */ + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { /* NC */ + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { /* NC */ + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { /* NC */ + nvidia,pins = "pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { /* NC */ + nvidia,pins = "pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { /* NC */ + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { /* NC */ + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { /* NC */ + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { /* NC */ + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { /* NC */ + nvidia,pins = "pk1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { /* NC */ + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { /* NC */ + nvidia,pins = "pk4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-fs-pn0 { /* NC */ + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-din-pn1 { /* NC */ + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-sclk-pn3 { /* NC */ + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data7-po0 { /* NC */ + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data0-po1 { /* NC */ + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data1-po2 { /* NC */ + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data2-po3 { /* NC */ + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data3-po4 { /* NC */ + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data6-po7 { /* NC */ + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-fs-pp4 { /* NC */ + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-din-pp5 { /* NC */ + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-dout-pp6 { /* NC */ + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-sclk-pp7 { /* NC */ + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col3-pq3 { /* NC */ + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row3-pr3 { /* NC */ + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row4-pr4 { /* NC */ + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5-pr5 { /* NC */ + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row6-pr6 { /* NC */ + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row7-pr7 { /* NC */ + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row8-ps0 { /* NC */ + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row9-ps1 { /* NC */ + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row12-ps4 { /* NC */ + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row13-ps5 { /* NC */ + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row14-ps6 { /* NC */ + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row15-ps7 { /* NC */ + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row16-pt0 { /* NC */ + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row17-pt1 { /* NC */ + nvidia,pins = "kb_row17_pt1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { /* NC */ + nvidia,pins = "pu5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { /* NC */ + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { /* NC */ + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x1-aud-px1 { /* NC */ + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud-px3 { /* NC */ + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { /* NC */ + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { /* NC */ + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { /* NC */ + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-req-pee1 { /* NC */ + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-mclk1-req-pee2 { /* NC */ + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output + * driver enabled aka not tristated and input driver + * enabled as well as it features some magic properties + * even though the external loopback is disabled and the + * internal loopback used as per + * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 + * bits being set to 0xfffd according to the TRM! + */ + sdmmc3-clk-lb-out-pee4 { /* NC */ + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006200 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006300 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + hdmi_ddc: i2c@7000c400 { + clock-frequency = <10000>; + }; + + /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vddio>; + VDDIO-supply = <®_1v8_vddio>; + clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + ams,system-power-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + + gpio2-7 { + pins = "gpio2", /* PWR_EN_+V3.3 */ + "gpio7"; /* +V1.6_LPO */ + function = "gpio"; + bias-pull-up; + }; + }; + + regulators { + vsup-sd2-supply = <®_module_3v3>; + vsup-sd3-supply = <®_module_3v3>; + vsup-sd4-supply = <®_module_3v3>; + vsup-sd5-supply = <®_module_3v3>; + vin-ldo0-supply = <®_1v35_vddio_ddr>; + vin-ldo1-6-supply = <®_module_3v3>; + vin-ldo2-5-7-supply = <®_1v8_vddio>; + vin-ldo3-4-supply = <®_module_3v3>; + vin-ldo9-10-supply = <®_module_3v3>; + vin-ldo11-supply = <®_module_3v3>; + + reg_vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + reg_1v35_vddio_ddr: sd2 { + regulator-name = + "+V1.35_VDDIO_DDR(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = + "+V1.35_VDDIO_DDR(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_1v05_vdd: sd4 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + reg_1v8_vddio: sd5 { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v05_avdd: ldo0 { + regulator-name = "+V1.05_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + vddio_sdmmc1: ldo1 { + regulator-name = "VDDIO_SDMMC1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "+V1.2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+V1.05_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + /* 1.8V for LVDS, 3.3V for eDP */ + ldo4 { + regulator-name = "AVDD_LVDS0_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* LDO5 not used */ + + vddio_sdmmc3: ldo6 { + regulator-name = "VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + /* LDO7 not used */ + + ldo9 { + regulator-name = "+V3.3_ETH(ldo9)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo10 { + regulator-name = "+V3.3_ETH(ldo10)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo11 { + regulator-name = "+V1.8_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + /* + * TMP451 temperature sensor + * Note: THERM_N directly connected to AS3722 PMIC THERM + */ + temp-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + #thermal-sensor-cells = <1>; + vcc-supply = <®_module_3v3>; + }; + }; + + /* SPI2: MCU SPI */ + spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set power_off bit in ResetControl register of AS3722 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; + }; + + sata@70020000 { + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; + phy-names = "sata-0"; + avdd-supply = <®_1v05_vdd>; + hvdd-supply = <®_module_3v3>; + vddio-supply = <®_1v05_vdd>; + }; + + usb@70090000 { + /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; + phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; + avddio-pex-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-usb-ss-pll-supply = <®_1v05_vdd>; + avdd-usb-supply = <®_module_3v3>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-usb-ss-pll-e-supply = <®_module_3v3>; + hvdd-usb-ss-supply = <®_module_3v3>; + }; + + padctl@7009f000 { + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + status = "okay"; + nvidia,function = "xusb"; + }; + + usb2-1 { + status = "okay"; + nvidia,function = "xusb"; + }; + + usb2-2 { + status = "okay"; + nvidia,function = "xusb"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + status = "okay"; + nvidia,function = "usb3-ss"; + }; + + pcie-1 { + status = "okay"; + nvidia,function = "usb3-ss"; + }; + + pcie-2 { + status = "okay"; + nvidia,function = "pcie"; + }; + + pcie-3 { + status = "okay"; + nvidia,function = "pcie"; + }; + + pcie-4 { + status = "okay"; + nvidia,function = "pcie"; + }; + }; + }; + + sata { + status = "okay"; + + lanes { + sata-0 { + status = "okay"; + nvidia,function = "sata"; + }; + }; + }; + }; + + ports { + /* USBO1 */ + usb2-0 { + status = "okay"; + mode = "otg"; + usb-role-switch; + vbus-supply = <®_usbo1_vbus>; + }; + + /* USBH2 */ + usb2-1 { + status = "okay"; + mode = "host"; + vbus-supply = <®_usbh_vbus>; + }; + + /* USBH4 */ + usb2-2 { + status = "okay"; + mode = "host"; + vbus-supply = <®_usbh_vbus>; + }; + + usb3-0 { + status = "okay"; + nvidia,usb2-companion = <2>; + vbus-supply = <®_usbh_vbus>; + }; + + usb3-1 { + status = "okay"; + nvidia,usb2-companion = <0>; + vbus-supply = <®_usbo1_vbus>; + }; + }; + }; + + /* eMMC */ + mmc@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ + mmc-ddr-1_8v; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <®_vdd_cpu>; + }; + + ahub@70300000 { + i2s@70301200 { + status = "okay"; + }; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <®_vdd_cpu>; + }; + }; + + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.05_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <®_1v05_vdd>; + }; + + reg_3v3_mxm: regulator-3v3-mxm { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_MXM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_1v05_vdd>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + /* PWR_EN_+V3.3 */ + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3_mxm>; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis TK1"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem-thermal { + trips { + mem-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + trips { + gpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi new file mode 100644 index 000000000000..d10e5334a6c6 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi @@ -0,0 +1,2443 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + clock@60006000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + memory-controller@70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0503 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000004 + 0x00000002 + 0x00000003 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0504 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000006 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000007 + 0x00000008 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000a + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000d + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x0000000f + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000e0e + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000006 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000006 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00008000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000707 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000e000e + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004d + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004b + 0x0000000e + 0x00000052 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00098000 + 0x00098000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0173000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 + 0x00000066 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006c + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000b + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00070000 + 0x00070000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00003800 + 0x00003800 + 0x00003800 + 0x00003800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000e + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 + 0x00000088 + 0x00000000 + 0x00000010 + 0x00000006 + 0x00000006 + 0x00000009 + 0x00000002 + 0x0000000d + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000009 + 0x00030000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000010 + 0x00000012 + 0x00000014 + 0x00000fd6 + 0x00000000 + 0x000003f5 + 0x00000002 + 0x0000000b + 0x00000001 + 0x00000000 + 0x00000085 + 0x00000012 + 0x00000090 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001017 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe01200b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00054000 + 0x00054000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0139000e + 0x00000000 + 0x00000003 + 0x000042a0 + 0x80002062 + 0x0000000a + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b + 0x0000009b + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000097 + 0x00000015 + 0x000000a3 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000013 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0127000e + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 + 0x000000cd + 0x00000000 + 0x00000019 + 0x0000000a + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x0000000a + 0x0000000a + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c7 + 0x00000018 + 0x000000d7 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x00000019 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f7000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b + 0x000000f0 + 0x00000000 + 0x0000001e + 0x0000000b + 0x00000009 + 0x0000000f + 0x00000005 + 0x00000016 + 0x0000000b + 0x0000000b + 0x00000004 + 0x00000002 + 0x00000000 + 0x00000007 + 0x00000007 + 0x0000000d + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000f + 0x000a0000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000016 + 0x0000001a + 0x0000001c + 0x00001be7 + 0x00000000 + 0x000006f9 + 0x00000004 + 0x00000015 + 0x00000001 + 0x00000000 + 0x000000e7 + 0x0000001b + 0x000000fb + 0x00000200 + 0x00000006 + 0x00000007 + 0x00000006 + 0x0000001e + 0x00000000 + 0x0000000a + 0x0000000a + 0x00001c28 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab898 + 0xe00400b1 + 0x00008000 + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x5d75d720 + 0x00514514 + 0x00514514 + 0x5d75d700 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000128 + 0x00cd000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x800037ea + 0x00000011 + >; + }; + }; + }; + + opp-table-actmon { + /delete-node/ opp-1200000000; + }; + + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts new file mode 100644 index 000000000000..4196f2401c90 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts @@ -0,0 +1,2080 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra124.dtsi" + +#include "tegra124-jetson-tk1-emc.dtsi" + +/ { + model = "NVIDIA Tegra124 Jetson TK1"; + compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; + + /* This order keeps the mapping DB9 connector <-> ttyS0 */ + serial0 = &uartd; + serial1 = &uarta; + serial2 = &uartb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + pcie@1003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + vddio-pex-ctl-supply = <&vdd_3v3_lp0>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + + /* Mini PCIe */ + pci@1,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; + phy-names = "pcie-0"; + status = "okay"; + }; + + /* Gigabit Ethernet */ + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; + phy-names = "pcie-0"; + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + vdd-supply = <&vdd_3v3_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpu@57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + + pinmux: pinmux@70000868 { + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; + + state_boot: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vimclk2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pe"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dsi_b { + nvidia,pins = "mipi_pad_ctrl_dsi_b"; + nvidia,function = "dsi_b"; + }; + }; + }; + + /* + * First high speed UART, exposed on the expansion connector J3A2 + * Pin 41: BR_UART1_TXD + * Pin 44: BR_UART1_RXD + */ + serial@70006000 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + }; + + /* + * Second high speed UART, exposed on the expansion connector J3A2 + * Pin 65: UART2_RXD + * Pin 68: UART2_TXD + * Pin 71: UART2_CTS_L + * Pin 74: UART2_RTS_L + */ + serial@70006040 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + }; + + /* DB9 serial port */ + serial@70006300 { + status = "okay"; + }; + + /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + pagesize = <8>; + }; + }; + + /* Expansion GEN2_I2C_* */ + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion CAM_I2C_* */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* HDMI DDC */ + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion PWR_I2C_*, on-board components */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_5_6 { + pins = "gpio3", "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05_run: ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.05V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "+2.8V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+3.3V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + /* Expansion TS_SPI_* */ + spi@7000d400 { + status = "okay"; + }; + + /* Internal SPI */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; + }; + + cec@70015000 { + status = "okay"; + }; + + /* Serial ATA */ + sata@70020000 { + status = "okay"; + + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; + phy-names = "sata-0"; + + hvdd-supply = <&vdd_3v3_lp0>; + vddio-supply = <&vdd_1v05_run>; + avdd-supply = <&vdd_1v05_run>; + + target-5v-supply = <&vdd_5v0_sata>; + target-12v-supply = <&vdd_12v0_sata>; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-usb-ss-pll-supply = <&vdd_1v05_run>; + hvdd-usb-ss-supply = <&vdd_3v3_lp0>; + hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; + + status = "okay"; + }; + + padctl@7009f000 { + status = "okay"; + + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "snps"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-2 { + nvidia,function = "pcie"; + status = "okay"; + }; + + pcie-4 { + nvidia,function = "pcie"; + status = "okay"; + }; + }; + }; + + sata { + status = "okay"; + + lanes { + sata-0 { + nvidia,function = "sata"; + status = "okay"; + }; + }; + }; + }; + + ports { + /* Micro A/B */ + usb2-0 { + status = "okay"; + mode = "host"; + }; + + /* Mini PCIe */ + usb2-1 { + status = "okay"; + mode = "host"; + }; + + /* USB3 */ + usb2-2 { + status = "okay"; + mode = "host"; + + vbus-supply = <&vdd_usb3_vbus>; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + }; + }; + + /* SD card */ + mmc@700b0400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + /* eMMC */ + mmc@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + usb@7d000000 { + compatible = "nvidia,tegra124-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + /* mini-PCIe USB */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + }; + + /* USB A connector */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + vdd_mux: regulator-mux { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator-5v0sys { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator-3v3sys { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator-3v3run { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator-3v3hdmi { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_lp0: regulator-lp0 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator-hdmipll { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator-hdmicon { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + /* Molex power connector */ + vdd_5v0_sata: regulator-5v0sata { + compatible = "regulator-fixed"; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_12v0_sata: regulator-12v0sata { + compatible = "regulator-fixed"; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Jetson TK1"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5639>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem-thermal { + trips { + mem-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + trips { + gpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi new file mode 100644 index 000000000000..cadb1969f1cc --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi @@ -0,0 +1,6694 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + clock@60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + apbmisc@70000800 { + nvidia,long-ram-code; + }; + + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77430303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75430403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ + 0x7488180d /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x74691b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ + 0x746c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000005 /* EMC_DLL_XFORM_DQS0 */ + 0x00000005 /* EMC_DLL_XFORM_DQS1 */ + 0x00000005 /* EMC_DLL_XFORM_DQS2 */ + 0x00000005 /* EMC_DLL_XFORM_DQS3 */ + 0x00000005 /* EMC_DLL_XFORM_DQS4 */ + 0x00000005 /* EMC_DLL_XFORM_DQS5 */ + 0x00000005 /* EMC_DLL_XFORM_DQS6 */ + 0x00000005 /* EMC_DLL_XFORM_DQS7 */ + 0x00000005 /* EMC_DLL_XFORM_DQS8 */ + 0x00000005 /* EMC_DLL_XFORM_DQS9 */ + 0x00000005 /* EMC_DLL_XFORM_DQS10 */ + 0x00000005 /* EMC_DLL_XFORM_DQS11 */ + 0x00000005 /* EMC_DLL_XFORM_DQS12 */ + 0x00000005 /* EMC_DLL_XFORM_DQS13 */ + 0x00000005 /* EMC_DLL_XFORM_DQS14 */ + 0x00000005 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a /* EMC_DLL_XFORM_DQ4 */ + 0x0000000a /* EMC_DLL_XFORM_DQ5 */ + 0x0000000a /* EMC_DLL_XFORM_DQ6 */ + 0x0000000a /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000e /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000f /* EMC_TXSR */ + 0x0000000f /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000017 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000015 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000019 /* EMC_TXSR */ + 0x00000019 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x00000023 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000021 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000025 /* EMC_TXSR */ + 0x00000025 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000047 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000006 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000044 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000004a /* EMC_TXSR */ + 0x0000004a /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000321>; + nvidia,emc-mrs-wait-cnt = <0x0117000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x00000067 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000065 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0117000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000521>; + nvidia,emc-mrs-wait-cnt = <0x00f5000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 /* EMC_RC */ + 0x00000089 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000087 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000941>; + nvidia,emc-mrs-wait-cnt = <0x00c8000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x000000b7 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000010 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000b4 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x000000bf /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000b61>; + nvidia,emc-mrs-wait-cnt = <0x00b0000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b /* EMC_RC */ + 0x000000d0 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000cc /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000d71>; + nvidia,emc-mrs-wait-cnt = <0x006f000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 /* EMC_RC */ + 0x00000114 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000019 /* EMC_RAS */ + 0x0000000a /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x0000000a /* EMC_RD_RCD */ + 0x0000000a /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000010d /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x0000011e /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ + 0x007f400c /* EMC_DLL_XFORM_DQS2 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ + 0x007f400c /* EMC_DLL_XFORM_DQS10 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00492492 /* EMC_XM2DQSPADCTRL4 */ + 0x00492492 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x006f000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ + >; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000009 /* EMC_DLL_XFORM_DQS0 */ + 0x00000009 /* EMC_DLL_XFORM_DQS1 */ + 0x00000009 /* EMC_DLL_XFORM_DQS2 */ + 0x00000007 /* EMC_DLL_XFORM_DQS3 */ + 0x00000006 /* EMC_DLL_XFORM_DQS4 */ + 0x00000006 /* EMC_DLL_XFORM_DQS5 */ + 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ + 0x00000006 /* EMC_DLL_XFORM_DQS7 */ + 0x00000009 /* EMC_DLL_XFORM_DQS8 */ + 0x00000009 /* EMC_DLL_XFORM_DQS9 */ + 0x00000009 /* EMC_DLL_XFORM_DQS10 */ + 0x00000007 /* EMC_DLL_XFORM_DQS11 */ + 0x00000006 /* EMC_DLL_XFORM_DQS12 */ + 0x00000007 /* EMC_DLL_XFORM_DQS13 */ + 0x00000009 /* EMC_DLL_XFORM_DQS14 */ + 0x00000007 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ + >; + }; + }; + }; + + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; + + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts new file mode 100644 index 000000000000..4db43324dafa --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra124-nyan-big.dts" + +/ { + /* Version of Nyan Big with 1080p panel */ + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "auo,b133htn01"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts new file mode 100644 index 000000000000..8bca9599ad6e --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts @@ -0,0 +1,1348 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra124-nyan.dtsi" + +#include "tegra124-nyan-big-emc.dtsi" + +/ { + model = "Acer Chromebook 13 CB5-311"; + compatible = "google,nyan-big-rev7", "google,nyan-big-rev6", + "google,nyan-big-rev5", "google,nyan-big-rev4", + "google,nyan-big-rev3", "google,nyan-big-rev2", + "google,nyan-big-rev1", "google,nyan-big-rev0", + "google,nyan-big", "google,nyan", "nvidia,tegra124"; + + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "auo,b133xtn01"; + power-supply = <&vdd_3v3_panel>; + backlight = <&backlight>; + }; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + mmc@700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBig"; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi new file mode 100644 index 000000000000..e8dcc4f51fc5 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi @@ -0,0 +1,2071 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + clock@60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + /* TODO: Add 528MHz frequency */ + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000d + 0x00000008 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090d + 0x7428180e + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000007 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x0000009a + 0x00000000 + 0x00000026 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000006 + 0x00000006 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x000000a0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x0000000b + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 + 0x0000000a + 0x00000000 + 0x00000001 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000134 + 0x00000000 + 0x0000004d + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000008 + 0x0000000f + 0x0000000c + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000013f + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000015 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 + 0x00000011 + 0x00000000 + 0x00000002 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 + 0x00000000 + 0x00000080 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000001 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000213 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000022 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000304 + 0x00000000 + 0x000000c1 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000018 + 0x0000000f + 0x0000001c + 0x0000001c + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000031c + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000033 + 0x00000000 + 0x00000042 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000f2f3 + 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 + 0x00000035 + 0x00000000 + 0x00000007 + 0x00000002 + 0x00000005 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000004 + 0x00000006 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 + 0x00000000 + 0x00000181 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000007 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x0000c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x0000003f + 0x016eeeee + 0x51451400 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000066 + 0x00000000 + 0x00000100 + 0x000c000c + 0x00000000 + 0x00000003 + 0x0000d2b3 + 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d + 0x0000004c + 0x00000000 + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 + 0x00000003 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000007 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x0000000e + 0x00000010 + 0x00000012 + 0x000008e4 + 0x00000000 + 0x00000239 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x0000004a + 0x0000000e + 0x00000051 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000009 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000924 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00060000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x00006000 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x00000096 + 0x00000000 + 0x00000100 + 0x0174000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 + 0x00000065 + 0x00000000 + 0x0000000c + 0x00000004 + 0x00000005 + 0x00000008 + 0x00000002 + 0x0000000a + 0x00000004 + 0x00000004 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 + 0x00000002 + 0x00000000 + 0x00000001 + 0x00000008 + 0x00020000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 + 0x00000001 + 0x00000000 + 0x00000063 + 0x0000000f + 0x0000006b + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x0000000d + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000c11 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0x002c00a0 + 0x00008000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00068000 + 0x00068000 + 0x00000000 + 0x00068000 + 0x00068000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00058000 + 0x00058000 + 0x00058000 + 0x00058000 + 0x00005800 + 0x00005800 + 0x00005800 + 0x00005800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0000003f + 0x000000c6 + 0x00000000 + 0x00000100 + 0x015b000c + 0x00000000 + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c + 0x0000009a + 0x00000000 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b + 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x0000000a + 0x00000002 + 0x00000000 + 0x00000003 + 0x0000000b + 0x00070000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000002 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 + 0x00000000 + 0x00000482 + 0x00000002 + 0x0000000d + 0x00000001 + 0x00000000 + 0x00000096 + 0x00000015 + 0x000000a2 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000015 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00040000 + 0x00040000 + 0x00000000 + 0x00040000 + 0x00040000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000005 + 0x00000007 + 0x00000004 + 0x00000006 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000005 + 0x00000007 + 0x00000004 + 0x00000006 + 0x00000007 + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0128000c + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024a9 + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 + 0x000000cc + 0x00000000 + 0x0000001a + 0x00000009 + 0x00000008 + 0x0000000d + 0x00000004 + 0x00000013 + 0x00000009 + 0x00000009 + 0x00000003 + 0x00000002 + 0x00000000 + 0x00000006 + 0x00000006 + 0x0000000b + 0x00000002 + 0x00000000 + 0x00000002 + 0x0000000d + 0x00080000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 + 0x00000003 + 0x00000011 + 0x00000001 + 0x00000000 + 0x000000c6 + 0x00000018 + 0x000000d6 + 0x00000200 + 0x00000005 + 0x00000006 + 0x00000005 + 0x0000001d + 0x00000000 + 0x00000008 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000008 + 0x0000000a + 0x00000008 + 0x0000000a + 0x0000000a + 0x00000008 + 0x00000008 + 0x00000005 + 0x00000008 + 0x0000000a + 0x00000008 + 0x0000000a + 0x0000000a + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x0000000e + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000202 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00492492 + 0x00492492 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f8000c + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f + >; + }; + }; + }; + + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; + + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts new file mode 100644 index 000000000000..432540c10065 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts @@ -0,0 +1,1346 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra124-nyan.dtsi" + +#include "tegra124-nyan-blaze-emc.dtsi" + +/ { + model = "HP Chromebook 14"; + compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9", + "google,nyan-blaze-rev8", "google,nyan-blaze-rev7", + "google,nyan-blaze-rev6", "google,nyan-blaze-rev5", + "google,nyan-blaze-rev4", "google,nyan-blaze-rev3", + "google,nyan-blaze-rev2", "google,nyan-blaze-rev1", + "google,nyan-blaze-rev0", "google,nyan-blaze", + "google,nyan", "nvidia,tegra124"; + + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "samsung,ltn140at29-301"; + power-supply = <&vdd_3v3_panel>; + backlight = <&backlight>; + }; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-blaze", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBlaze"; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi new file mode 100644 index 000000000000..0c35ca2e9121 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -0,0 +1,836 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include "tegra124.dtsi" + +/ { + aliases { + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* + * Note that recent version of the device tree compiler (starting with + * version 1.4.2) warn about this node containing a reg property, but + * missing a unit-address. However, the bootloader on these Chromebook + * devices relies on the full name of this node to be exactly /memory. + * Adding the unit-address causes the bootloader to create a /memory + * node and write the memory bank configuration to that node, which in + * turn leads the kernel to believe that the device has 2 GiB of + * memory instead of the amount detected by the bootloader. + * + * The name of this node is effectively ABI and must not be changed. + */ + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + /delete-node/ memory@80000000; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@54540000 { + status = "okay"; + + avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; + vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + gpu@57000000 { + status = "okay"; + + vdd-supply = <&vdd_gpu>; + }; + + serial@70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + tmp451: temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio>; + interrupts = ; + wakeup-source; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05_run: ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + ti,external-control; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + cec@70015000 { + status = "okay"; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-usb-ss-pll-supply = <&vdd_1v05_run>; + hvdd-usb-ss-supply = <&vdd_3v3_lp0>; + hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; + + status = "okay"; + }; + + padctl@7009f000 { + status = "okay"; + + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-1 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + vbus-supply = <&vdd_usb1_vbus>; + status = "okay"; + mode = "otg"; + usb-role-switch; + }; + + usb2-1 { + vbus-supply = <&vdd_run_cam>; + status = "okay"; + mode = "host"; + }; + + usb2-2 { + vbus-supply = <&vdd_usb3_vbus>; + status = "okay"; + mode = "host"; + }; + + usb3-0 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + }; + }; + + mmc@700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&sdhci0_pwrseq>; + vmmc-supply = <&vdd_3v3_lp0>; + vqmmc-supply = <&vddio_1v8>; + keep-power-in-suspend; + }; + + mmc@700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + mmc@700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + #cooling-cells = <2>; + vdd-cpu-supply = <&vdd_cpu>; + }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + wakeup-source; + }; + + switch-lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = ; + debounce-interval = <1>; + wakeup-source; + }; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + sdhci0_pwrseq: pwrseq-sdhci0 { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + }; + + vdd_mux: regulator-mux { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator-5v0sys { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator-3v3sys { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator-3v3run { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator-3v3hdmi { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator-led { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator-ts { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator-lp0 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator-hdmipll { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator-hdmicon { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + nvidia,mic-det-gpios = + <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + }; + + thermal-zones { + cpu-skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tmp451 0>; + + trips { + cpu_passive_trip: cpu-alert0 { + /* throttle at 70C until temperature drops to 69.8C */ + temperature = <70000>; + hysteresis = <200>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_passive_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi new file mode 100644 index 000000000000..b262c1289da5 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: opp-table-emc { + compatible = "operating-points-v2"; + + opp-12750000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp-12750000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp-12750000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp-12750000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp-20400000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp-20400000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp-20400000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp-20400000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-40800000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp-40800000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp-40800000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp-68000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp-68000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp-102000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp-102000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + opp-suspend; + }; + + opp-204000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + opp-suspend; + }; + + opp-204000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + opp-suspend; + }; + + opp-204000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + opp-suspend; + }; + + opp-264000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp-264000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp-264000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp-264000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp-300000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp-300000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp-300000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp-348000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp-348000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp-348000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp-348000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp-396000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp-396000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp-396000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp-528000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp-528000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp-528000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp-528000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp-600000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp-600000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp-600000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp-600000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp-792000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp-792000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp-792000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp-924000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + emc_bw_dfs_opp_table: opp-table-actmon { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp-20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts new file mode 100644 index 000000000000..c697301c443c --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -0,0 +1,1256 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Tegra124 Venice2"; + compatible = "nvidia,venice2", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@54540000 { + status = "okay"; + + avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; + vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + + aux-bus { + panel: panel { + compatible = "lg,lp129qe"; + power-supply = <&vdd_3v3_panel>; + backlight = <&backlight>; + }; + }; + }; + }; + + gpu@57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + + pinmux: pinmux@70000868 { + pinctrl-names = "boot"; + pinctrl-0 = <&pinmux_boot>; + + pinmux_boot: pinmux { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pk0 { + nvidia,pins = "pk0", + "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,rcv-sel = ; + }; + pj7 { + nvidia,pins = "pj7", + "pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0", + "pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + nvidia,drive-type = <1>; + }; + als_irq_l { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + codec_irq_l { + nvidia,pins = "ph4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_bl_en { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch_irq_l { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + tpm_davint_l { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_irq_l { + nvidia,pins = "pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_reset_l { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_shdn_l { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_ap { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lid_open { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_sd { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ac_ok { + nvidia,pins = "pj0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sensor_irq_l { + nvidia,pins = "pi6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wifi_en { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wifi_rst_l { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp_det_l { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio>; + interrupts = ; + linux,gpio-keymap = <0 0 0 BTN_LEFT>; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05_run: ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-usb-ss-pll-supply = <&vdd_1v05_run>; + hvdd-usb-ss-supply = <&vdd_3v3_lp0>; + hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; + + status = "okay"; + }; + + padctl@7009f000 { + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-1 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "okay"; + mode = "otg"; + usb-role-switch; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb2-1 { + status = "okay"; + mode = "host"; + + vbus-supply = <&vdd_run_cam>; + }; + + usb2-2 { + status = "okay"; + mode = "host"; + + vbus-supply = <&vdd_usb3_vbus>; + }; + + usb3-0 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + }; + }; + + mmc@700b0400 { + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + status = "okay"; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + mmc@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + vdd_mux: regulator-mux { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator-5v0sys { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator-3v3sys { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator-3v3run { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator-led { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator-ts { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator-lp0 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator-hdmipll { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator-hdmicon { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-venice2", + "nvidia,tegra-audio-max98090"; + nvidia,model = "NVIDIA Tegra Venice2"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + }; +}; + +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi new file mode 100644 index 000000000000..b3fbecf5c818 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -0,0 +1,1366 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tegra124-peripherals-opp.dtsi" + +/ { + compatible = "nvidia,tegra124"; + interrupt-parent = <&lic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pcie@1003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ + <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ + <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + + host1x@50000000 { + compatible = "nvidia,tegra124-host1x"; + reg = <0x0 0x50000000 0x0 0x00034000>; + interrupts = , /* syncpt */ + ; /* general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; + reset-names = "host1x", "mc"; + iommus = <&mc TEGRA_SWGROUP_HC>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; + + dc@54200000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x0 0x54200000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + clock-names = "dc"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DC>; + + nvidia,head = <0>; + + interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, + <&mc TEGRA124_MC_DISPLAY0B &emc>, + <&mc TEGRA124_MC_DISPLAY0C &emc>, + <&mc TEGRA124_MC_DISPLAYHC &emc>, + <&mc TEGRA124_MC_DISPLAYD &emc>, + <&mc TEGRA124_MC_DISPLAYT &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor", + "wind", + "wint"; + }; + + dc@54240000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x0 0x54240000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DISP2>; + clock-names = "dc"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DCB>; + + nvidia,head = <1>; + + interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, + <&mc TEGRA124_MC_DISPLAY0BB &emc>, + <&mc TEGRA124_MC_DISPLAY0CB &emc>, + <&mc TEGRA124_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + }; + + hdmi: hdmi@54280000 { + compatible = "nvidia,tegra124-hdmi"; + reg = <0x0 0x54280000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + vic@54340000 { + compatible = "nvidia,tegra124-vic"; + reg = <0x0 0x54340000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_VIC03>; + clock-names = "vic"; + resets = <&tegra_car 178>; + reset-names = "vic"; + + iommus = <&mc TEGRA_SWGROUP_VIC>; + }; + + sor@54540000 { + compatible = "nvidia,tegra124-sor"; + reg = <0x0 0x54540000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_SOR0_OUT>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA124_CLK_PLL_DP>, + <&tegra_car TEGRA124_CLK_CLK_M>; + clock-names = "sor", "out", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + status = "disabled"; + }; + + dpaux: dpaux@545c0000 { + compatible = "nvidia,tegra124-dpaux"; + reg = <0x0 0x545c0000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DPAUX>, + <&tegra_car TEGRA124_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + status = "disabled"; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + gic: interrupt-controller@50041000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x50041000 0x0 0x1000>, + <0x0 0x50042000 0x0 0x1000>, + <0x0 0x50044000 0x0 0x2000>, + <0x0 0x50046000 0x0 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + gpu@57000000 { + compatible = "nvidia,gk20a"; + reg = <0x0 0x57000000 0x0 0x01000000>, + <0x0 0x58000000 0x0 0x01000000>; + interrupts = , + ; + interrupt-names = "stall", "nonstall"; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pwr"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + + iommus = <&mc TEGRA_SWGROUP_GPU>; + + status = "disabled"; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; + reg = <0x0 0x60004000 0x0 0x100>, + <0x0 0x60004100 0x0 0x100>, + <0x0 0x60004200 0x0 0x100>, + <0x0 0x60004300 0x0 0x100>, + <0x0 0x60004400 0x0 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + timer@60005000 { + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA124_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x0 0x60006000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; + }; + + flow-controller@60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + + actmon: actmon@6000c800 { + compatible = "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ACTMON>, + <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; + reg = <0x0 0x6000d000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinmux 0 0 251>; + }; + + apbdma: dma@60020000 { + compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x0 0x60020000 0x0 0x1400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA124_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + apbmisc@70000800 { + compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ + <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ + }; + + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra124-pinmux"; + reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ + <0x0 0x70003000 0x0 0x434>, /* Mux registers */ + <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ + }; + + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the compatible is + * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". + */ + uarta: serial@70006000 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006040 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006200 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006300 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; + reg = <0x0 0x7000a000 0x0 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA124_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra124-i2c"; + reg = <0x0 0x7000c000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra124-i2c"; + reg = <0x0 0x7000c400 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra124-i2c"; + reg = <0x0 0x7000c500 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra124-i2c"; + reg = <0x0 0x7000c700 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra124-i2c"; + reg = <0x0 0x7000d000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra124-i2c"; + reg = <0x0 0x7000d100 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C6>; + clock-names = "div-clk"; + resets = <&tegra_car 166>; + reset-names = "i2c"; + dmas = <&apbdma 30>, <&apbdma 30>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000d400 0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000d600 0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000d800 0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000da00 0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000dc00 0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000de00 0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; + reg = <0x0 0x7000e000 0x0 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_RTC>; + }; + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra124-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra124-efuse"; + reg = <0x0 0x7000f800 0x0 0x400>; + clocks = <&tegra_car TEGRA124_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; + + mc: memory-controller@70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #iommu-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; + + emc: external-memory-controller@7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "emc"; + + nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; + }; + + sata@70020000 { + compatible = "nvidia,tegra124-ahci"; + reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ + <0x0 0x70020000 0x0 0x7000>; /* SATA */ + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + resets = <&tegra_car 124>, + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; + status = "disabled"; + }; + + hda@70030000 { + compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; + reg = <0x0 0x70030000 0x0 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_HDA>, + <&tegra_car TEGRA124_CLK_HDA2HDMI>, + <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; + }; + + usb@70090000 { + compatible = "nvidia,tegra124-xusb"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + reg-names = "hcd", "fpci", "ipfs"; + + interrupts = , + ; + + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", + "xusb_falcon_src", "xusb_ss", + "xusb_ss_div2", "xusb_ss_src", + "xusb_hs_src", "xusb_fs_src", + "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_ss", "xusb_src"; + + nvidia,xusb-padctl = <&padctl>; + + status = "disabled"; + }; + + padctl: padctl@7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + pads { + usb2 { + status = "disabled"; + + lanes { + usb2-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + ulpi { + status = "disabled"; + + lanes { + ulpi-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + pcie { + status = "disabled"; + + lanes { + pcie-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-2 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-3 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-4 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + sata { + status = "disabled"; + + lanes { + sata-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + ulpi-0 { + status = "disabled"; + }; + + hsic-0 { + status = "disabled"; + }; + + hsic-1 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + }; + }; + + mmc@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x0 0x700b0000 0x0 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + clock-names = "sdhci"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x0 0x700b0200 0x0 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + clock-names = "sdhci"; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x0 0x700b0400 0x0 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + clock-names = "sdhci"; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x0 0x700b0600 0x0 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + clock-names = "sdhci"; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disabled"; + }; + + soctherm: thermal-sensor@700e2000 { + compatible = "nvidia,tegra124-soctherm"; + reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ + <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ + reg-names = "soctherm-reg", "car-reg"; + interrupts = , + ; + interrupt-names = "thermal", "edp"; + clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, + <&tegra_car TEGRA124_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + #thermal-sensor-cells = <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-percent = <85>; + nvidia,gpu-throt-level = ; + + #cooling-cells = <2>; + }; + }; + }; + + dfll: clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + + ahub@70300000 { + compatible = "nvidia,tegra124-ahub"; + reg = <0x0 0x70300000 0x0 0x200>, + <0x0 0x70300800 0x0 0x800>, + <0x0 0x70300200 0x0 0x600>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, + <&tegra_car TEGRA124_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 185>, /* amx1 */ + <&tegra_car 154>, /* adx */ + <&tegra_car 180>, /* adx1 */ + <&tegra_car 186>, /* afc0 */ + <&tegra_car 187>, /* afc1 */ + <&tegra_car 188>, /* afc2 */ + <&tegra_car 189>, /* afc3 */ + <&tegra_car 190>, /* afc4 */ + <&tegra_car 191>; /* afc5 */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "amx1", "adx", "adx1", + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + tegra_i2s0: i2s@70301000 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x0 0x70301000 0x0 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA124_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70301100 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x0 0x70301100 0x0 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA124_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70301200 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x0 0x70301200 0x0 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA124_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70301300 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x0 0x70301300 0x0 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA124_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70301400 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x0 0x70301400 0x0 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA124_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + + usb@7d000000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d000000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x0 0x7d004000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d004000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 1>; + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x0 0x7d008000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d008000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>, + <&{/cpus/cpu@2}>, + <&{/cpus/cpu@3}>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + cpu_throttle_trip: throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + mem-throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + gpu_throttle_trip: throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + pllx-throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts new file mode 100644 index 000000000000..08b42952f4de --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts @@ -0,0 +1,1525 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "Acer Iconia Tab A500"; + compatible = "acer,picasso", "nvidia,tegra20"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Docking station */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_5v0_sys>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "csus", "dap1", + "dap4", "dte", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", + "sdc", "sdd", "slxc", "slxd", "slxk", + "spdi", "spdo", "uac", "uad", "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", + "gmd", "owc", "spia", "spib", "spic", + "spid", "spie"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spig", + "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dte { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = ; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", + "uab", "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0"; + nvidia,pull = ; + }; + drive_ddc { + nvidia,pins = "drive_ddc", + "drive_vi1", + "drive_sdio1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = ; + nvidia,high-speed-mode = ; + nvidia,low-power-mode = ; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_dbg { + nvidia,pins = "drive_dbg", + "drive_vi2", + "drive_at1", + "drive_ao1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = ; + nvidia,high-speed-mode = ; + nvidia,low-power-mode = ; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + tegra_spdif: spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + tegra_i2s1: i2s@70002800 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; + /* GPS BCM4751 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + /* Azurewave AW-NH665 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&rtc_32k_wifi>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + uartd: serial@70006300 { + /* Docking station */ + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = < + 0x0000 /* MIC_LR_OUT# GPIO, output, low */ + 0x0000 /* FM2018-enable GPIO, output, low */ + 0x0000 /* Speaker-enable GPIO, output, low */ + 0x0200 /* Interrupt, output */ + 0x01a0 /* BCLK, input, active high */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + touchscreen@4c { + compatible = "atmel,maxtouch"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + + atmel,wakeup-method = ; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + vddio-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + }; + }; + }; + + i2c@7000c400 { + clock-frequency = <10000>; + status = "okay"; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vid-supply = <&vdd_1v8_sys>; + + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + + interrupts = ; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + avdd_vdac_reg: ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0>; /* elpida-8gb */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd510 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e1510 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@1 { + nvidia,ram-code = <1>; /* elpida-4gb */ + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@2 { + nvidia,ram-code = <2>; /* hynix-8gb */ + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e2010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@3 { + nvidia,ram-code = <3>; /* hynix-4gb */ + reg = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00078000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_sys>; + + /* Azurewave AW-NH611 BCM4329 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 41667>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + bat1010: battery-2s1p { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3260000>; + energy-full-design-microwatt-hours = <24000000>; + operating-range-celsius = <0 40>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "tps658621-out32k"; + }; + + /* + * This standalone onboard fixed-clock always-ON 32KHz + * oscillator is used as a reference clock-source by the + * Azurewave WiFi/BT module. + */ + rtc_32k_wifi: clock-32k-wifi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "kk3270032"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "auo,b101ew05", "panel-lvds"; + + ddc-i2c-bus = <&panel_ddc>; + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-rotation-lock { + label = "Rotate-lock"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + debounce-interval = <10>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + panel_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@58 { + compatible = "acer,a500-iconia-ec", "ene,kb930"; + reg = <0x58>; + + system-power-controller; + + monitored-battery = <&bat1010>; + power-supplies = <&mains>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-picasso", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Acer Iconia Tab A500 WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "LINEOUTL", + "Int Spk", "LINEOUTR", + "Mic Jack", "MICBIAS", + "IN2L", "Mic Jack", + "IN2R", "Mic Jack", + "IN1L", "Int Mic", + "IN1R", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; + nvidia,headset; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents A500 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&rtc_32k_wifi>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts new file mode 100644 index 000000000000..c2a9c3fb5b33 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -0,0 +1,1291 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "ASUS EeePad Transformer TF101"; + compatible = "asus,tf101", "nvidia,tegra20"; + chassis-type = "convertible"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi_en>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + gpio@6000d000 { + charging-enable-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap4", + "dte", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", "sdc", + "sdd", "slxc", "slxd", "slxk", "spdi", + "spdo", "uac", "uad", + "uda", "csus"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", + "owc", "spia", "spib", "spic", + "spid", "spie", "spig", "slxa"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + + conf_crtp { + nvidia,pins = "crtp", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_spif { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = ; + }; + + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab", + "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_csus { + nvidia,pins = "drive_csus"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + i2s@70002800 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; + /* GPS BCM4751 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0xe>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_sys>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0x83>; + micdet-delay = <100>; + + gpio-cfg = < + 0x00000600 /* DMIC_LR, output */ + 0x00000680 /* DMIC_DAT, input */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + /* Atmel MXT1386 Touchscreen */ + touchscreen@5b { + compatible = "atmel,maxtouch"; + reg = <0x5b>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + + atmel,wakeup-method = ; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0xf>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + vddio-supply = <&vdd_1v8_sys>; + + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + }; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@3 { + reg = <0x3>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dc010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e0 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id = <1 0>; + density = <2048>; + io-width = <16>; + }; + }; + }; + + /* Peripheral USB via ASUS connector */ + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <40000000>; + + max-frequency = <40000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + + /* Azurewave AW-NH615 BCM4329B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 4000000>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "auo,b101ew05", "panel-lvds"; + + /* AUO B101EW05 using custom timings */ + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + switch-dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c2>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&mains>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pcie_vdd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_hdmi_en: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_hdmi_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf101", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus EeePad Transformer WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; + nvidia,coupled-mic-hp-det; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents TF101 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <200>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts new file mode 100644 index 000000000000..612f4e54cb20 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +#include +#include "tegra20-colibri.dtsi" + +/ { + model = "Toradex Colibri T20 on Colibri Evaluation Board"; + compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20", + "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@34"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartd; + serial2 = &uartb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + pinmux@70000014 { + state_default: pinmux { + bl-on { + nvidia,tristate = ; + }; + + ddc { + nvidia,tristate = ; + }; + + hotplug-detect { + nvidia,tristate = ; + }; + + i2c { + nvidia,tristate = ; + }; + + lcd { + nvidia,tristate = ; + }; + + lm1 { + nvidia,tristate = ; + }; + + mmc { + nvidia,tristate = ; + }; + + mmccd { + nvidia,tristate = ; + }; + + sdc { + nvidia,tristate = ; + }; + + sdb_sdd { + nvidia,tristate = ; + }; + + ssp { + nvidia,tristate = ; + }; + + uart-a { + nvidia,tristate = ; + }; + + uart-b { + nvidia,tristate = ; + }; + + uart-c { + nvidia,tristate = ; + }; + + usbh-pen { + nvidia,tristate = ; + }; + }; + }; + + /* Colibri UART-A */ + serial@70006000 { + status = "okay"; + }; + + /* Colibri UART-C */ + serial@70006040 { + status = "okay"; + }; + + /* Colibri UART-B */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* CAM_I2C (I2C3): unused */ + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + i2c@7000c400 { + status = "okay"; + }; + + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + /* CAN_INT */ + interrupts = ; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; + }; + + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <®_usbc_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* SD/MMC */ + mmc@c8000600 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ + no-1-8-v; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* PWM */ + }; + + clk16m: clock-osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "SODIMM pin 45 wakeup"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbc_vbus: regulator-usbc-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB5"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + }; + + /* USBH_PEN resp. USB_P_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts new file mode 100644 index 000000000000..25a9f5dfe62d --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra20-colibri.dtsi" + +/ { + model = "Toradex Colibri T20 on Iris"; + compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20", + "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@34"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartd; + serial2 = &uartb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + pinmux@70000014 { + state_default: pinmux { + bl-on { + nvidia,tristate = ; + }; + + ddc { + nvidia,tristate = ; + }; + + hotplug-detect { + nvidia,tristate = ; + }; + + i2c { + nvidia,tristate = ; + }; + + lcd { + nvidia,tristate = ; + }; + + lm1 { + nvidia,tristate = ; + }; + + mmc { + nvidia,tristate = ; + }; + + mmccd { + nvidia,tristate = ; + }; + + sdc { + nvidia,tristate = ; + }; + + sdb_sdd { + nvidia,tristate = ; + }; + + ssp { + nvidia,tristate = ; + }; + + uart-a { + nvidia,tristate = ; + }; + + uart-b { + nvidia,tristate = ; + }; + + uart-c { + nvidia,tristate = ; + }; + + usbh-pen { + nvidia,tristate = ; + }; + }; + }; + + /* Colibri UART-A */ + serial@70006000 { + status = "okay"; + }; + + /* Colibri UART-C */ + serial@70006040 { + status = "okay"; + }; + + /* Colibri UART-B */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* CAM_I2C (I2C3): unused */ + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + i2c@7000c400 { + status = "okay"; + }; + + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <®_usbc_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* SD/MMC */ + mmc@c8000600 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ + no-1-8-v; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* PWM */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "SODIMM pin 45 wakeup"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbc_vbus: regulator-usbc-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + }; + + /* USBH_PEN resp. USB_P_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi new file mode 100644 index 000000000000..0e03910abbe6 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi @@ -0,0 +1,776 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra20.dtsi" + +/* + * Toradex Colibri T20 Module Device Tree + * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; + * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; + * Colibri T20 512MB IT V1.2A + */ +/ { + memory@0 { + /* + * Set memory to 256 MB to be safe as this could be used on + * 256 or 512 MB module. It is expected from bootloader + * to fix this up for 512 MB version. + */ + reg = <0x00000000 0x10000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; + + /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ + npwe-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "Tri-state nPWE"; + }; + + /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ + rdnwr-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "Not tri-state RDnWR"; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio AC97 to WM9712 (On-module) */ + audio-refclk { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ + * (All on-module), SODIMM Pin 45 Wakeup + */ + gpio-uac { + nvidia,pins = "uac"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Buffer Enables for nPWE and RDnWR (On-module, + * see GPIO hogging further down below) + */ + gpio-pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, + * SYS_CLK_REQ (All on-module) + */ + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + nvidia,tristate = ; + }; + + /* + * Colibri Address/Data Bus (GMI) + * Note: spid and spie optionally used for SPI1 + */ + gmi { + nvidia,pins = "atc", "atd", "ate", "dap1", + "dap2", "dap4", "gmd", "gpu", + "irrx", "irtx", "spia", "spib", + "spic", "spid", "spie", "uca", + "ucb"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Further pins may be used as GPIOs */ + gmi-gpio1 { + nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; + gmi-gpio2 { + nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; + nvidia,function = "rsvd4"; + nvidia,tristate = ; + }; + + /* Colibri BL_ON */ + bl-on { + nvidia,pins = "dta"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri Backlight PWM, PWM */ + sdc { + nvidia,pins = "sdc"; + nvidia,function = "pwm"; + nvidia,tristate = ; + }; + + /* Colibri DDC */ + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Colibri EXT_IO* + * Note: dtf optionally used for I2C3 + */ + ext-io { + nvidia,pins = "dtf", "spdi"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Colibri Ethernet (On-module) + * ULPI EHCI instance 1 USB2_DP/N -> AX88772B + */ + ulpi { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi-refclk { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri HOTPLUG_DETECT (HDMI) */ + hotplug-detect { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; + + /* Colibri I2C */ + i2c { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE + * today's display need DE, disable LCD_M1 + */ + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + nvidia,tristate = ; + }; + + /* Colibri LCD (L_* resp. LDD<*>) */ + lcd { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", + "ld16", "ld17", "lhs", "lsc0", + "lspi", "lvs"; + nvidia,function = "displaya"; + nvidia,tristate = ; + }; + /* Colibri LCD (Optional 24 BPP Support) */ + lcd-24 { + nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", + "lpp", "lvp1"; + nvidia,function = "displaya"; + nvidia,tristate = ; + }; + + /* Colibri MMC */ + mmc { + nvidia,pins = "atb", "gma"; + nvidia,function = "sdio4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri MMCCD */ + mmccd { + nvidia,pins = "gmb"; + nvidia,function = "gmi_int"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri MMC (Optional 8-bit) */ + mmc-8bit { + nvidia,pins = "gme"; + nvidia,function = "sdio4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Colibri Parallel Camera (Optional) + * pins multiplexed with others and therefore disabled + * Note: dta used for BL_ON by default + */ + cif-mclk { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + nvidia,pull = ; + nvidia,tristate = ; + }; + cif { + nvidia,pins = "dtb", "dtc", "dtd"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri PWM, PWM */ + sdb_sdd { + nvidia,pins = "sdb", "sdd"; + nvidia,function = "pwm"; + nvidia,tristate = ; + }; + + /* Colibri SSP */ + ssp { + nvidia,pins = "slxa", "slxc", "slxd", "slxk"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri UART-A */ + uart-a { + nvidia,pins = "sdio1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart-a-dsr { + nvidia,pins = "lpw1"; + nvidia,function = "rsvd3"; + nvidia,tristate = ; + }; + uart-a-dcd { + nvidia,pins = "lpw2"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; + + /* Colibri UART-B */ + uart-b { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri UART-C */ + uart-c { + nvidia,pins = "uad"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri USB_CDET */ + usb-cdet { + nvidia,pins = "spdo"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri USBH_OC */ + usbh-oc { + nvidia,pins = "spih"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri USBH_PEN */ + usbh-pen { + nvidia,pins = "spig"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri VGA not supported */ + vga { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* I2C3 (Optional) */ + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* JTAG_RTCK */ + jtag-rtck { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME + * (All On-module) + */ + gpio-gpv { + nvidia,pins = "gpv"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN + * (All On-module); Colibri CAN_INT + */ + gpio-dte { + nvidia,pins = "dte"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* NAND (On-module) */ + nand { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Onewire (Optional) */ + owr { + nvidia,pins = "owc"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Power I2C (On-module) */ + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* RESET_OUT */ + reset-out { + nvidia,pins = "ata"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * SPI1 (Optional) + * Note: spid and spie used for Colibri Address/Data + * Bus (GMI) + */ + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * THERMD_ALERT# (On-module), unlatched I2C address pin + * of LM95245 temperature sensor therefore requires + * disabling for now + */ + lvp0 { + nvidia,pins = "lvp0"; + nvidia,function = "rsvd3"; + nvidia,tristate = ; + }; + }; + }; + + tegra_ac97: ac97@70002000 { + status = "okay"; + nvidia,codec-reset-gpio = + <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + nvidia,codec-sync-gpio = + <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; + }; + + nand-controller@70008000 { + status = "okay"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-is-boot-medium; + nand-ecc-maximize; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + clock-frequency = <400000>; + }; + + /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ + hdmi_ddc: i2c@7000c400 { + clock-frequency = <10000>; + }; + + /* GEN2_I2C: unused */ + + /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ + + /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + ti,system-power-controller; + #gpio-cells = <2>; + gpio-controller; + sys-supply = <®_module_3v3>; + vin-sm0-supply = <®_3v3_vsys>; + vin-sm1-supply = <®_3v3_vsys>; + vin-sm2-supply = <®_3v3_vsys>; + vinldo01-supply = <®_1v8_vdd_ddr2>; + vinldo23-supply = <®_module_3v3>; + vinldo4-supply = <®_module_3v3>; + vinldo678-supply = <®_module_3v3>; + vinldo9-supply = <®_module_3v3>; + + regulators { + reg_3v3_vsys: sys { + regulator-name = "VSYS_3.3V"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "VDD_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "VDD_CPU_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_1v8_vdd_ddr2: sm2 { + regulator-name = "VDD_DDR2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + /* + * +3.3V_ENABLE_N switching via FET: + * AVDD_AUDIO_S and +3.3V + * see also +3.3V fixed supply + */ + ldo1 { + regulator-name = "AVDD_PLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "VDD_RTC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4 { + regulator-name = "VDDIO_SYS_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* Switched via FET from regular +3.3V */ + ldo5 { + regulator-name = "+3.3V_USB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "AVDD_VDAC_2.85V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + reg_3v3_avdd_hdmi: ldo7 { + regulator-name = "AVDD_HDMI_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1v8_avdd_hdmi_pll: ldo8 { + regulator-name = "AVDD_HDMI_PLL_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "VDDIO_RX_DDR_2.85V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "VCC_BATT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + /* LM95245 temperature sensor */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + }; + + pmc@7000e400 { + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <3>; + nvidia,bus-addr = <0x34>; + nvidia,reg-addr = <0x14>; + nvidia,reg-data = <0x8>; + }; + }; + + memory-controller@7000f400 { + emc-table@83250 { + reg = <83250>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <83250>; + nvidia,emc-registers = <0x00000005 0x00000011 + 0x00000004 0x00000002 0x00000004 0x00000004 + 0x00000001 0x0000000a 0x00000002 0x00000002 + 0x00000001 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x0000025f + 0x00000000 0x00000003 0x00000003 0x00000002 + 0x00000002 0x00000001 0x00000008 0x000000c8 + 0x00000003 0x00000005 0x00000003 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x00520006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + emc-table@133200 { + reg = <133200>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <133200>; + nvidia,emc-registers = <0x00000008 0x00000019 + 0x00000006 0x00000002 0x00000004 0x00000004 + 0x00000001 0x0000000a 0x00000002 0x00000002 + 0x00000002 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x0000039f + 0x00000000 0x00000003 0x00000003 0x00000002 + 0x00000002 0x00000001 0x00000008 0x000000c8 + 0x00000003 0x00000007 0x00000003 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x00510006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000021 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000a 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x00000009 0x000000c8 + 0x00000003 0x00000009 0x00000004 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x004f0006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000014 0x00000041 + 0x0000000f 0x00000005 0x00000004 0x00000005 + 0x00000003 0x0000000a 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x000009ff + 0x00000000 0x00000003 0x00000003 0x00000005 + 0x00000005 0x00000001 0x0000000e 0x000000c8 + 0x00000003 0x00000011 0x00000006 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x00380006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ + usb@c5004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "usbb95,772b"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = + <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + vbus-supply = <®_lan_v_bus>; + }; + + clk32k_in: clock-xtal3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + opp-table-emc { + /delete-node/ opp-760000000; + }; + + reg_lan_v_bus: regulator-lan-v-bus { + compatible = "regulator-fixed"; + regulator-name = "LAN_V_BUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "nvidia,tegra-audio-wm9712-colibri_t20", + "nvidia,tegra-audio-wm9712"; + nvidia,model = "Toradex Colibri T20"; + nvidia,audio-routing = + "Headphone", "HPOUTL", + "Headphone", "HPOUTR", + "LineIn", "LINEINL", + "LineIn", "LINEINR", + "Mic", "MIC1"; + nvidia,ac97-controller = <&tegra_ac97>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi new file mode 100644 index 000000000000..7330c1b13d93 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: opp-table-cpu0 { + opp-216000000-750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp-216000000-800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp-312000000-750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp-312000000-800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp-456000000-750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp-456000000-800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp-456000000-825 { + opp-microvolt = <825000 825000 1125000>; + }; + + opp-608000000-750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp-608000000-800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp-608000000-825 { + opp-microvolt = <825000 825000 1125000>; + }; + + opp-608000000-850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp-608000000-900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp-760000000-775 { + opp-microvolt = <775000 775000 1125000>; + }; + + opp-760000000-800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp-760000000-850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp-760000000-875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp-760000000-900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp-760000000-975 { + opp-microvolt = <975000 975000 1125000>; + }; + + opp-816000000-800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp-816000000-850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp-816000000-875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp-816000000-950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp-816000000-1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp-912000000-850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp-912000000-900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp-912000000-925 { + opp-microvolt = <925000 925000 1125000>; + }; + + opp-912000000-950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp-912000000-1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp-912000000-1050 { + opp-microvolt = <1050000 1050000 1125000>; + }; + + opp-1000000000-875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp-1000000000-900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp-1000000000-950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp-1000000000-975 { + opp-microvolt = <975000 975000 1125000>; + }; + + opp-1000000000-1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp-1000000000-1025 { + opp-microvolt = <1025000 1025000 1125000>; + }; + + opp-1000000000-1100 { + opp-microvolt = <1100000 1100000 1125000>; + }; + + opp-1200000000-1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp-1200000000-1050 { + opp-microvolt = <1050000 1050000 1125000>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1125000>; + }; + + opp-1200000000-1125 { + opp-microvolt = <1125000 1125000 1125000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi new file mode 100644 index 000000000000..47c8e78ca958 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-216000000-750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0003>; + opp-hz = /bits/ 64 <216000000>; + opp-suspend; + }; + + opp-216000000-800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0004>; + opp-hz = /bits/ 64 <216000000>; + opp-suspend; + }; + + opp-312000000-750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0003>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp-312000000-800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0004>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp-456000000-750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0C 0x0003>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp-456000000-800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>, + <0x08 0x0004>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp-456000000-825 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp-608000000-750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-608000000-800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-608000000-825 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-608000000-850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0006>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-608000000-900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-760000000-775 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0006>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-875 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>, + <0x01 0x0004>, <0x02 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-975 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-816000000-800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0007>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-816000000-850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-816000000-875 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0005>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-816000000-950 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0006>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-816000000-1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-912000000-850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0007>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp-912000000-900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp-912000000-925 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp-912000000-950 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>, + <0x04 0x0004>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp-912000000-1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp-912000000-1050 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp-1000000000-875 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0007>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-950 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-975 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-1025 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-1100 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1200000000-1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1050 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1100 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1125 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-harmony.dts b/arch/arm/boot/dts/nvidia/tegra20-harmony.dts new file mode 100644 index 000000000000..11f21aeba8e9 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-harmony.dts @@ -0,0 +1,761 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra20 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = ; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + }; + + hdmi_ddc: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + pci_clk_reg: ldo0 { + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + kbc@7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <2>; + nvidia,repeat-delay-ms = <160>; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = ; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + pcie@80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + usb@c5000000 { + status = "okay"; + }; + + usb-phy@c5000000 { + status = "okay"; + }; + + usb@c5004000 { + status = "okay"; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + mmc@c8000200 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + mmc@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <8>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel: panel { + compatible = "auo,b101aw03"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pci_vdd_reg: regulator-1v05 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_pnl_reg: regulator-pn1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-harmony", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Harmony"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_LOW>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts b/arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts new file mode 100644 index 000000000000..8c657182fff3 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Medcom-Wide board"; + compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; + + aliases { + serial0 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + /* close enough */ + power-supply = <&vdd_3v3_reg>; + }; + + panel: panel { + compatible = "innolux,n156bge-l21"; + + power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-medcom-wide", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Medcom-Wide"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + vcc_24v_reg: regulator-24v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8_reg: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts new file mode 100644 index 000000000000..e995f428dc2e --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts @@ -0,0 +1,721 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* MicroSD */ + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atc", "atd", "ate", + "dap2", "gmb", "gmc", "gmd", "spia", + "spib", "spic", "spid", "spie"; + nvidia,function = "gmi"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "pllc_out1"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gpu { + nvidia,pins = "gpu", "sdb", "sdd"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + kbcb { + nvidia,pins = "kbcb", "kbcd"; + nvidia,function = "sdio2"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdc { + nvidia,pins = "sdc"; + nvidia,function = "twc"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spi4"; + }; + spdi { + nvidia,pins = "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + spif { + nvidia,pins = "spif", "uac"; + nvidia,function = "rsvd4"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "spdif"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dap2", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", + "gpu", "gpu7", "gpv", "i2cp", "pta", + "rm", "sdio1", "slxk", "spdo", "uac", + "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_crtp { + nvidia,pins = "crtp", "dap3", "dap4", "dtb", + "dtc", "dte", "slxa", "slxc", "slxd", + "spdi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_csus { + nvidia,pins = "csus", "spia", "spib", "spid", + "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ddc { + nvidia,pins = "ddc", "irrx", "irtx", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "spic", "spig", "uaa", "uab"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dta { + nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", + "spie", "spih", "uad", "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhs", "lsc0", "lspi", + "lvs", "pmc"; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_lcsn { + nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", + "lm0", "lm1", "lpp", "lpw0", "lpw1", + "lpw2", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "lvp1", "sdb"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + }; + }; + + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + i2s@70002800 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + serial@70006000 { + status = "okay"; + }; + + serial@70006200 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + lvds_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + alc5632: alc5632@1e { + compatible = "realtek,alc5632"; + reg = <0x1e>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + hdmi_ddc: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + nvec@7000c500 { + compatible = "nvidia,nvec"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <80000>; + request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + slave-addr = <138>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&p5valw_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + core_vdd_reg: sm0 { + regulator-name = "+1.2vs_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + + nvidia,tegra-core-regulator; + }; + + cpu_vdd_reg: sm1 { + regulator-name = "+1.0vs_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1100000>; + regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "+3.7vs_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "+1.1vs_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd_reg: ldo2 { + regulator-name = "+1.2vs_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "+3.3vs_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "+2.85vs_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + /* + * Research indicates this should be + * 1.8v; other boards that use this + * rail for the same purpose need it + * set to 1.8v. The schematic signal + * name is incorrect; perhaps copied + * from an incorrect NVIDIA reference. + */ + regulator-name = "+2.85vs_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "+3.3vs_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "+3.3vs_rtc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + adt7461: temperature-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000016 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000a 0x000000c8 + 0x00000003 0x00000006 0x00000004 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe03b0323 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + }; + + usb@c5004000 { + status = "okay"; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <10>; + + /* close enough */ + power-supply = <&vdd_pnl_reg>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "Wakeup"; + gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + label = "wifi-led"; + gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "rfkill0"; + }; + }; + + opp-table-emc { + /delete-node/ opp-760000000; + }; + + panel: panel { + compatible = "samsung,ltn101nt05"; + + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + + p5valw_reg: regulator-5v0alw { + compatible = "regulator-fixed"; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-3v0 { + compatible = "regulator-fixed"; + regulator-name = "+3VS,vdd_pnl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "nvidia,tegra-audio-alc5632-paz00", + "nvidia,tegra-audio-alc5632"; + + nvidia,model = "Compal PAZ00"; + + nvidia,audio-routing = + "Int Spk", "SPKOUT", + "Int Spk", "SPKOUTN", + "Headset Mic", "MICBIAS1", + "MIC1", "Headset Mic", + "Headset Stereophone", "HPR", + "Headset Stereophone", "HPL", + "DMICDAT", "Digital Mic"; + + nvidia,audio-codec = <&alc5632>; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <500>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + thermal-sensors = <&adt7461 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 80C */ + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 85C */ + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi new file mode 100644 index 000000000000..1b808233a933 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi @@ -0,0 +1,1022 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1300000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-level = <1000000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-level = <1100000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-level = <1200000>; + }; + + core_opp_1225: opp-1225000 { + opp-microvolt = <1225000 1225000 1300000>; + opp-level = <1225000>; + }; + + core_opp_1275: opp-1275000 { + opp-microvolt = <1275000 1275000 1300000>; + opp-level = <1275000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-level = <1300000>; + }; + }; + + emc_icc_dvfs_opp_table: opp-table-emc { + compatible = "operating-points-v2"; + + opp-36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-47500000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <47500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-50000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <50000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-54000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-57000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <57000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-100000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-108000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-126666000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <126666000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-150000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-216000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + opp-suspend; + }; + + opp-300000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-333000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <333000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-380000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-600000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + + opp-666000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <666000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + + opp-760000000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <760000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1300>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-166000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-142500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <142500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-228000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-237500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-266000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <266000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-275500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1100>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-85000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <85000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-150000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-114000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-161500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-161500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-247000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-256500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-285000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-304000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-323000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-333500000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-333500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-351500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-380000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-400000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-400000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + dsi_dvfs_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-100000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-159500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <159500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-180500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <180500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-207000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <207000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-222500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <222500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-229500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <229500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-240000000-1225 { + opp-microvolt = <1225000 1225000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1225>; + }; + + opp-240000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-247000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-256500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-260000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <260000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-262000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <262000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1300>; + }; + + opp-264000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-277500000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <277500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1300>; + }; + + opp-285000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-292500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <292500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1275>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-237500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-275500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + }; + + ndflash_dvfs_opp_table: opp-table-ndflash { + compatible = "operating-points-v2"; + + opp-130000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-150000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-158000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-164000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-92000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <92000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc2_dvfs_opp_table: opp-table-sdmmc2 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-plutux.dts b/arch/arm/boot/dts/nvidia/tegra20-plutux.dts new file mode 100644 index 000000000000..71a8236491df --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-plutux.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Plutux board"; + compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + }; + }; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-plutux", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Plutux"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + vcc_24v_reg: regulator-24v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8_reg: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts b/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts new file mode 100644 index 000000000000..bd4ff8b40b20 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts @@ -0,0 +1,920 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra20.dtsi" + +/ { + model = "NVIDIA Seaboard"; + compatible = "nvidia,seaboard", "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", + "lsck", "lsda"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap2", + "dap4", "ddc", "dtf", "gma", "gmc", "gmd", + "gme", "gpu", "gpu7", "i2cp", "irrx", + "irtx", "pta", "rm", "sdc", "sdd", + "slxd", "slxk", "spdi", "spdo", "uac", + "uad", "uca", "ucb", "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ate { + nvidia,pins = "ate", "csus", "dap3", + "gpv", "owc", "slxc", "spib", "spid", + "spie"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spia", + "spig", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dte { + nvidia,pins = "dte", "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = ; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "spic", "uaa", + "uab"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + /* ALS and proximity sensor */ + isl29018@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + gyrometer@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0xc>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; + }; + + kbc@7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <32>; + nvidia,repeat-delay-ms = <160>; + nvidia,ghost-filter; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = ; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + emc-table@190000 { + reg = <190000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <190000>; + nvidia,emc-registers = <0x0000000c 0x00000026 + 0x00000009 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x0000059f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000b 0x000000c8 + 0x00000003 0x00000007 0x00000004 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xa06204ae + 0x007dc010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@380000 { + reg = <380000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <380000>; + nvidia,emc-registers = <0x00000017 0x0000004b + 0x00000012 0x00000006 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000b5f + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe044048b + 0x007d8010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; + dr_mode = "otg"; + }; + + usb@c5004000 { + status = "okay"; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + mmc@c8000000 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + + mmc@c8000400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + mmc@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + switch-lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + wakeup-source; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + }; + }; + }; + + panel: panel { + compatible = "chunghwa,claa101wa01a"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_reg: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_wup1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) 0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-seaboard", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Seaboard"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1R", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi b/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi new file mode 100644 index 000000000000..ddb84e4a9f8b --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten SOM"; + compatible = "ad,tamonten", "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "irrx", "irtx", "pta", + "rm", "slxa", "slxk", "spia", "spib", + "uac"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc", "uad", "uca"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = ; + }; + conf_sdd { + nvidia,pins = "sdd", "spic", "spie", "spih", + "uaa", "uab", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + status = "okay"; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + /* vdd_5v0_reg must be provided by the base board */ + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sys_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sys_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sys_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + pci_clk_reg: ldo0 { + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + pcie@80003000 { + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + mmc@c8000600 { + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pci_vdd_reg: regulator-1v05 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-tec.dts b/arch/arm/boot/dts/nvidia/tegra20-tec.dts new file mode 100644 index 000000000000..4f41c74384b2 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-tec.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + }; + }; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + pcie@80003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-tec", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design TEC"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + vcc_24v_reg: regulator-24v { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1v8_reg: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts new file mode 100644 index 000000000000..1944121e2dd6 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000c500/rtc@56"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc", "gmb"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gme", "pta"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc", "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "uarta"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "sdio3"; + }; + spdi { + nvidia,pins = "spdi", "spdo"; + nvidia,function = "spdif"; + }; + spia { + nvidia,pins = "spia", "spib", "spic"; + nvidia,function = "spi2"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atc", "atd", "ate", + "crtp", "dap2", "dap3", "dap4", "dta", + "dtb", "dtc", "dtd", "dte", "gmb", + "gme", "i2cp", "pta", "slxc", "slxd", + "spdi", "spdo", "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_atb { + nvidia,pins = "atb", "cdev1", "cdev2", "dap1", + "gma", "gmc", "gmd", "gpu", "gpu7", + "gpv", "sdio1", "slxa", "slxk", "uac"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_csus { + nvidia,pins = "csus", "spia", "spib", + "spid", "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ddc { + nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "pmc"; + nvidia,tristate = ; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "kbca", "kbcb", + "kbcc", "kbcd", "kbce", "kbcf", "owc", + "spic", "spie", "spig", "spih", "uaa", + "uab", "uad", "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "sdb"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + conf_spif { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006000 { + status = "okay"; + }; + + dvi_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + spi@7000c380 { + status = "okay"; + spi-max-frequency = <48000000>; + + flash@0 { + compatible = "winbond,w25q80bl", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <48000000>; + }; + }; + + hdmi_ddc: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + codec: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; + + rtc@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; + }; + + pmc@7000e400 { + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + pcie@80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + pci@1,0 { + status = "okay"; + }; + }; + + usb@c5000000 { + status = "okay"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; + }; + + usb@c5004000 { + status = "okay"; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + mmc@c8000000 { + status = "okay"; + broken-cd; + bus-width = <4>; + }; + + mmc@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + }; + + hdmi_vdd_reg: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hdmi_pll_reg: regulator-hdmipll { + compatible = "regulator-fixed"; + regulator-name = "avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vbus_reg: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(V, 2) 0>; + regulator-always-on; + regulator-boot-on; + }; + + pci_clk_reg: regulator-pciclk { + compatible = "regulator-fixed"; + regulator-name = "pci_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci_vdd_reg: regulator-pcivdd { + compatible = "regulator-fixed"; + regulator-name = "pci_vdd"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + vdd_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + sound { + compatible = "nvidia,tegra-audio-trimslice"; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&codec>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-ventana.dts b/arch/arm/boot/dts/nvidia/tegra20-ventana.dts new file mode 100644 index 000000000000..433575a6ad38 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-ventana.dts @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "NVIDIA Tegra20 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap2", + "dap4", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "i2cp", "irrx", + "irtx", "pta", "rm", "sdc", "sdd", + "slxc", "slxd", "slxk", "spdi", "spdo", + "uac", "uad", "uca", "ucb", "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ate { + nvidia,pins = "ate", "csus", "dap3", "gmd", + "gpv", "owc", "spia", "spib", "spic", + "spid", "spie", "spig"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dte { + nvidia,pins = "dte", "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = ; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + /* ALS and proximity sensor */ + isl29018@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + usb@c5000000 { + status = "okay"; + }; + + usb-phy@c5000000 { + status = "okay"; + }; + + usb@c5004000 { + status = "okay"; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + mmc@c8000000 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + + mmc@c8000400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + mmc@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + panel: panel { + compatible = "chunghwa,claa101wa01a"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-ventana", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Ventana"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 50C */ + temperature = <50000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi new file mode 100644 index 000000000000..4177d04265d8 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include + +#include "tegra20-peripherals-opp.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + + host1x@50000000 { + compatible = "nvidia,tegra20-host1x"; + reg = <0x50000000 0x00024000>; + interrupts = , /* syncpt */ + ; /* general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; + reset-names = "host1x", "mc"; + power-domains = <&pd_core>; + operating-points-v2 = <&host1x_dvfs_opp_table>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe@54040000 { + compatible = "nvidia,tegra20-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; + status = "disabled"; + }; + + vi@54080000 { + compatible = "nvidia,tegra20-vi"; + reg = <0x54080000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; + status = "disabled"; + }; + + epp@540c0000 { + compatible = "nvidia,tegra20-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; + power-domains = <&pd_core>; + operating-points-v2 = <&epp_dvfs_opp_table>; + status = "disabled"; + }; + + isp@54100000 { + compatible = "nvidia,tegra20-isp"; + reg = <0x54100000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; + power-domains = <&pd_venc>; + status = "disabled"; + }; + + gr2d@54140000 { + compatible = "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; + power-domains = <&pd_core>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; + power-domains = <&pd_3d>; + operating-points-v2 = <&gr3d_dvfs_opp_table>; + }; + + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_DISP1>, + <&tegra_car TEGRA20_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; + + nvidia,head = <0>; + + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_DISP2>, + <&tegra_car TEGRA20_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; + + nvidia,head = <1>; + + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + + rgb { + status = "disabled"; + }; + }; + + tegra_hdmi: hdmi@54280000 { + compatible = "nvidia,tegra20-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_HDMI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + tvo@542c0000 { + compatible = "nvidia,tegra20-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; + status = "disabled"; + }; + + dsi@54300000 { + compatible = "nvidia,tegra20-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsi_dvfs_opp_table>; + status = "disabled"; + }; + }; + + timer@50040600 { + compatible = "arm,cortex-a9-twd-timer"; + interrupt-parent = <&intc>; + reg = <0x50040600 0x20>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_TWD>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <5 5 2>; + arm,tag-latency = <4 4 2>; + cache-unified; + cache-level = <2>; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr"; + reg = <0x60004000 0x100>, + <0x60004100 0x50>, + <0x60004200 0x50>, + <0x60004300 0x50>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + timer@60005000 { + compatible = "nvidia,tegra20-timer"; + reg = <0x60005000 0x60>; + interrupts = , + , + , + ; + clocks = <&tegra_car TEGRA20_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; + }; + + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1200>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA20_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + ahb@6000c000 { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = , + , + , + , + , + , + ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinmux 0 0 224>; + }; + + vde@6001a000 { + compatible = "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x300>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA20_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; + }; + + pinmux: pinmux@70000014 { + compatible = "nvidia,tegra20-pinmux"; + reg = <0x70000014 0x10>, /* Tri-state registers */ + <0x70000080 0x20>, /* Mux registers */ + <0x700000a0 0x14>, /* Pull-up/down registers */ + <0x70000868 0xa8>; /* Pad control registers */ + }; + + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; + + das@70000c00 { + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + tegra_ac97: ac97@70002000 { + compatible = "nvidia,tegra20-ac97"; + reg = <0x70002000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_AC97>; + resets = <&tegra_car 3>; + reset-names = "ac97"; + dmas = <&apbdma 12>, <&apbdma 12>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tegra_spdif: spdif@70002400 { + compatible = "nvidia,tegra20-spdif"; + reg = <0x70002400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, + <&tegra_car TEGRA20_CLK_SPDIF_IN>; + clock-names = "out", "in"; + resets = <&tegra_car 10>; + dmas = <&apbdma 3>, <&apbdma 3>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; + }; + + tegra_i2s1: i2s@70002800 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + dmas = <&apbdma 2>, <&apbdma 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70002a00 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + dmas = <&apbdma 1>, <&apbdma 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra20-uart" and to enable the APB DMA based serial + * driver, the compatible is "nvidia,tegra20-hsuart". + */ + uarta: serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uarte: serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + assigned-clock-rates = <150000000>; + power-domains = <&pd_core>; + operating-points-v2 = <&ndflash_dvfs_opp_table>; + status = "disabled"; + }; + + gmi@70009000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xd0000000 0xfffffff>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; + status = "disabled"; + }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA20_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_I2C1>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000c380 { + compatible = "nvidia,tegra20-sflash"; + reg = <0x7000c380 0x80>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SPI>; + resets = <&tegra_car 43>; + reset-names = "spi"; + dmas = <&apbdma 11>, <&apbdma 11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c2: i2c@7000c400 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_I2C2>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra20-i2c-dvc"; + reg = <0x7000d000 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_DVC>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d800 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_RTC>; + }; + + kbc@7000e200 { + compatible = "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; + status = "disabled"; + }; + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra20-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d: td { + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&mc TEGRA20_MC_RESET_3D>, + <&tegra_car TEGRA20_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car TEGRA20_CLK_VI>, + <&tegra_car TEGRA20_CLK_CSI>; + resets = <&mc TEGRA20_MC_RESET_ISP>, + <&mc TEGRA20_MC_RESET_VI>, + <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; + }; + + mc: memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc-gart"; + reg = <0x7000f000 0x00000400>, /* controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ + clocks = <&tegra_car TEGRA20_CLK_MC>; + clock-names = "mc"; + interrupts = ; + #reset-cells = <1>; + #iommu-cells = <0>; + #interconnect-cells = <1>; + }; + + emc: memory-controller@7000f400 { + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f400 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_EMC>; + power-domains = <&pd_core>; + #address-cells = <1>; + #size-cells = <0>; + #interconnect-cells = <0>; + + nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + pcie@80003000 { + compatible = "nvidia,tegra20-pcie"; + device_type = "pci"; + reg = <0x80003000 0x00000800>, /* PADS registers */ + <0x80003800 0x00000200>, /* AFI registers */ + <0x90000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ + <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ + <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA20_CLK_PEX>, + <&tegra_car TEGRA20_CLK_AFI>, + <&tegra_car TEGRA20_CLK_PLL_E>; + clock-names = "pex", "afi", "pll_e"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; + + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; + status = "disabled"; + }; + + phy1: usb-phy@c5000000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5000000 0x4000>, + <0xc5000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USBD>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CLK_M>, + <&tegra_car TEGRA20_CLK_USBD>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,has-legacy-mode; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <1>; + nvidia,xcvr-lsrslew = <1>; + nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; + status = "disabled"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = ; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; + status = "disabled"; + }; + + phy2: usb-phy@c5004000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004000 0x4000>; + interrupts = ; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; + status = "disabled"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; + status = "disabled"; + }; + + phy3: usb-phy@c5008000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5008000 0x4000>, + <0xc5000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USB3>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CLK_M>, + <&tegra_car TEGRA20_CLK_USBD>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,pmc = <&tegra_pmc 2>; + status = "disabled"; + }; + + mmc@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + clock-names = "sdhci"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; + status = "disabled"; + }; + + mmc@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + clock-names = "sdhci"; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; + status = "disabled"; + }; + + mmc@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + clock-names = "sdhci"; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; + status = "disabled"; + }; + + mmc@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + clock-names = "sdhci"; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + ; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; + }; + + sound-hdmi { + compatible = "simple-audio-card"; + simple-audio-card,name = "NVIDIA Tegra20 HDMI"; + + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + + codec { + sound-dai = <&tegra_hdmi>; + }; + + cpu { + sound-dai = <&tegra_spdif>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts new file mode 100644 index 000000000000..842b5faba285 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra30-apalis.dtsi" + +/ { + model = "Toradex Apalis T30 on Apalis Evaluation Board"; + compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", + "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@2d"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie@3000 { + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on + * carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI5: Apalis SPI2 */ + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* Apalis SD1 */ + mmc@78000000 { + status = "okay"; + bus-width = <4>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + /* Apalis MMC1 */ + mmc@78000400 { + status = "okay"; + bus-width = <8>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* BKL1_PWM */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..ca277bf1df78 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +#include +#include "tegra30-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis T30 on Apalis Evaluation Board"; + compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval", + "toradex,apalis_t30-v1.1", "toradex,apalis_t30", + "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@2d"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie@3000 { + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on + * carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI5: Apalis SPI2 */ + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* Apalis SD1 */ + mmc@78000000 { + status = "okay"; + bus-width = <4>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + /* Apalis MMC1 */ + mmc@78000400 { + status = "okay"; + bus-width = <8>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + vqmmc-supply = <®_vddio_sdmmc3>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* BKL1_PWM */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* + * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on + * EN_+3.3_SDMMC3 GPIO + */ + reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-type = "voltage"; + gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + startup-delay-us = <100000>; + vin-supply = <&vddio_sdmmc_1v8_reg>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi new file mode 100644 index 000000000000..a4b7fe5c3d23 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi @@ -0,0 +1,1202 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +#include "tegra30.dtsi" + +/* + * Toradex Apalis T30 Module Device Tree + * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; + * 2GB: V1.1A, V1.1B + */ +/ { + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + pcie@3000 { + status = "okay"; + avdd-pexa-supply = <&vdd2_reg>; + avdd-pexb-supply = <&vdd2_reg>; + avdd-pex-pll-supply = <&vdd2_reg>; + avdd-plle-supply = <&ldo6_reg>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; + vdd-pexa-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; + + /* Apalis type specific */ + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + /* Apalis PCIe */ + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + /* I210/I211 Gigabit Ethernet Controller (on-module) */ + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + + ethernet@0,0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1-out-pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis BKL1_ON */ + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + uart3-rts-n-pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ + uart3-cts-n-pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN1 on SPI6 */ + spi2-cs0-n-px3 { + nvidia,pins = "spi2_cs0_n_px3", + "spi2_miso_px1", + "spi2_mosi_px0", + "spi2_sck_px2"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* CAN_INT1 */ + spi2-cs1-n-pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN2 on SPI4 */ + gmi-a16-pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* CAN_INT2 */ + spi2-cs2-n-pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + clk1-req-pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk2-out-pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-fs-pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis GPIO */ + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row10_ps2", + "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis HDMI1 */ + hdmi-cec-pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C1 */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C2 (DDC) */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C3 (CAM) */ + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis LCD1 */ + lcd-d0-pe0 { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_pclk_pb3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis MMC1 */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3-dat0-pb7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis MMC1_CD# */ + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Parallel Camera */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi-vsync-pd6 { + nvidia,pins = "vi_d0_pt4", + "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7", + "vi_d10_pt2", + "vi_d11_pt3", + "vi_hsync_pd7", + "vi_pclk_pt0", + "vi_vsync_pd6"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + kb-col2-pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5-pr5 { + nvidia,pins = "kb_row5_pr5", + "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * VI level-shifter direction + * (pull-down => default direction input) + */ + vi-mclk-pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM1 */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM2 */ + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM3 */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM4 */ + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis RESET_MOCI# */ + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SATA1_ACT# */ + pex-l0-prsnt-n-pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc1-clk-pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1-cmd-pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis SD1_CD# */ + clk2-req-pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF1 */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5", + "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + spi1-sck-px5 { + nvidia,pins = "spi1_sck_px5", + "spi1_mosi_px4", + "spi1_miso_px7", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SPI2 */ + lcd-sck-pz4 { + nvidia,pins = "lcd_sck_pz4", + "lcd_sdout_pn5", + "lcd_sdin_pz2", + "lcd_cs0_n_pn4"; + nvidia,function = "spi5"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Apalis TS (Low-speed type specific) + * pins may be used as GPIOs + */ + kb-col5-pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col6-pq6 { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7", + "kb_row8_ps0", + "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART2 */ + ulpi-clk-py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART3 */ + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART4 */ + uart3-rxd-pw7 { + nvidia,pins = "uart3_rxd_pw7", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBH_EN */ + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_OC# */ + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBO1_OC# */ + gen2-i2c-sda-pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis VGA1 not supported and therefore disabled */ + crt-hsync-pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC (On-module) */ + sdmmc4-clk-pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_cmd_pt7", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat0-paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EN_+3.3_SDMMC3 */ + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ + pex-l2-prsnt-n-pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7", + "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ + pex-wake-n-pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 SMB_ALERT_N (On-module) */ + sys-clk-req-pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LVDS Transceiver Configuration */ + pbb0 { + nvidia,pins = "pbb0", + "pbb7", + "pcc1", + "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb4", + "pbb5", + "pbb6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Not connected and therefore disabled */ + clk-32k-out-pa0 { + nvidia,pins = "clk3_out_pee0", + "clk3_req_pee1", + "clk_32k_out_pa0", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-fs-pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5", + "lcd_dc0_pn6", + "lcd_m1_pw1", + "lcd_pwr1_pc1", + "pex_l1_clkreq_n_pdd6", + "pex_l1_prsnt_n_pdd4", + "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_ad8_ph0", + "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6", + "gmi_ad15_ph7", + "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs4_n_pk2", + "gmi_cs2_n_pk3", + "gmi_dqs_pi2", + "gmi_iordy_pi5", + "gmi_oe_n_pi1", + "gmi_wait_pi7", + "gmi_wr_n_pi0", + "lcd_cs1_n_pw0", + "pu0", + "pu1", + "pu2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs0-n-pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr0-pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr2_pc6", + "lcd_wr_n_pz3"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rts-n-pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Power I2C (On-module) */ + pwr-i2c-scl-pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* + * THERMD_ALERT#, unlatched I2C address pin of LM95245 + * temperature sensor therefore requires disabling for + * now + */ + lcd-dc1-pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_PEN_INT# (On-module) */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vio>; + VDDIO-supply = <®_module_3v3>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <®_module_3v3>; + vcc2-supply = <®_module_3v3>; + vcc3-supply = <®_1v8_vio>; + vcc4-supply = <®_module_3v3>; + vcc5-supply = <®_module_3v3>; + vcc6-supply = <®_1v8_vio>; + vcc7-supply = <®_5v0_charge_pump>; + vccio-supply = <®_module_3v3>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "+V1.35_VDDIO_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddctrl_reg: vddctrl { + regulator-name = "+V1.0_VDD_CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + reg_1v8_vio: vio { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* + * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3 + * is off + */ + vddio_sdmmc_1v8_reg: ldo1 { + regulator-name = "+VDDIO_SDMMC3_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 + * see also +V3.3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "EN_+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "+V1.2_CSI"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo4_reg: ldo4 { + regulator-name = "+V1.2_VDD_RTC"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for (unsupported) analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "+V2.8_AVDD_VDAC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "+V1.05_AVDD_PLLE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "+V1.2_AVDD_PLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "+V1.0_VDD_DDR_HS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + /* STMPE811 touch screen controller */ + touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; + + /* + * LM95245 temperature sensor + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN + */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + + /* SW: +V1.2_VDD_CORE */ + regulator@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + + regulator-name = "tps62362-vout"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + /* SPI4: CAN2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + /* SPI6: CAN1 */ + spi@7000de00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x1>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + + /* eMMC */ + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; + }; + + clk16m: clock-osc4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + clk32k_in: clock-xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_1v8_vio>; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_module_3v3>; + }; + + reg_5v0_charge_pump: regulator-5v0-charge-pump { + compatible = "regulator-fixed"; + regulator-name = "+V5.0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi new file mode 100644 index 000000000000..d73103884000 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi @@ -0,0 +1,1185 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra30.dtsi" + +/* + * Toradex Apalis T30 Module Device Tree + * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E + */ +/ { + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + pcie@3000 { + status = "okay"; + avdd-pexa-supply = <&vdd2_reg>; + avdd-pexb-supply = <&vdd2_reg>; + avdd-pex-pll-supply = <&vdd2_reg>; + avdd-plle-supply = <&ldo6_reg>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; + vdd-pexa-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; + + /* Apalis type specific */ + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + /* Apalis PCIe */ + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + /* I210/I211 Gigabit Ethernet Controller (on-module) */ + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + + ethernet@0,0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1-out-pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis BKL1_ON */ + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + uart3-rts-n-pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ + uart3-cts-n-pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN1 on SPI6 */ + spi2-cs0-n-px3 { + nvidia,pins = "spi2_cs0_n_px3", + "spi2_miso_px1", + "spi2_mosi_px0", + "spi2_sck_px2"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* CAN_INT1 */ + spi2-cs1-n-pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN2 on SPI4 */ + gmi-a16-pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* CAN_INT2 */ + spi2-cs2-n-pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + clk1-req-pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk2-out-pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-fs-pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis GPIO */ + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row10_ps2", + "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis HDMI1 */ + hdmi-cec-pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C1 */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C2 (DDC) */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C3 (CAM) */ + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis LCD1 */ + lcd-d0-pe0 { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_pclk_pb3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis MMC1 */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3-dat0-pb7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis MMC1_CD# */ + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Parallel Camera */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi-vsync-pd6 { + nvidia,pins = "vi_d0_pt4", + "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7", + "vi_d10_pt2", + "vi_d11_pt3", + "vi_hsync_pd7", + "vi_pclk_pt0", + "vi_vsync_pd6"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + kb-col2-pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5-pr5 { + nvidia,pins = "kb_row5_pr5", + "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * VI level-shifter direction + * (pull-down => default direction input) + */ + vi-mclk-pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM1 */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM2 */ + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM3 */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM4 */ + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis RESET_MOCI# */ + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SATA1_ACT# */ + pex-l0-prsnt-n-pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc1-clk-pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1-cmd-pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis SD1_CD# */ + clk2-req-pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF1 */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5", + "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + spi1-sck-px5 { + nvidia,pins = "spi1_sck_px5", + "spi1_mosi_px4", + "spi1_miso_px7", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SPI2 */ + lcd-sck-pz4 { + nvidia,pins = "lcd_sck_pz4", + "lcd_sdout_pn5", + "lcd_sdin_pz2", + "lcd_cs0_n_pn4"; + nvidia,function = "spi5"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Apalis TS (Low-speed type specific) + * pins may be used as GPIOs + */ + kb-col5-pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col6-pq6 { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7", + "kb_row8_ps0", + "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART2 */ + ulpi-clk-py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART3 */ + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART4 */ + uart3-rxd-pw7 { + nvidia,pins = "uart3_rxd_pw7", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBH_EN */ + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_OC# */ + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBO1_OC# */ + gen2-i2c-sda-pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis VGA1 not supported and therefore disabled */ + crt-hsync-pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC (On-module) */ + sdmmc4-clk-pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_cmd_pt7", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat0-paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ + pex-l2-prsnt-n-pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7", + "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ + pex-wake-n-pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 SMB_ALERT_N (On-module) */ + sys-clk-req-pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LVDS Transceiver Configuration */ + pbb0 { + nvidia,pins = "pbb0", + "pbb7", + "pcc1", + "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb4", + "pbb5", + "pbb6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Not connected and therefore disabled */ + clk-32k-out-pa0 { + nvidia,pins = "clk3_out_pee0", + "clk3_req_pee1", + "clk_32k_out_pa0", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-fs-pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5", + "lcd_dc0_pn6", + "lcd_m1_pw1", + "lcd_pwr1_pc1", + "pex_l1_clkreq_n_pdd6", + "pex_l1_prsnt_n_pdd4", + "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_ad8_ph0", + "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6", + "gmi_ad15_ph7", + "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs4_n_pk2", + "gmi_cs2_n_pk3", + "gmi_dqs_pi2", + "gmi_iordy_pi5", + "gmi_oe_n_pi1", + "gmi_wait_pi7", + "gmi_wr_n_pi0", + "lcd_cs1_n_pw0", + "pu0", + "pu1", + "pu2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs0-n-pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr0-pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr2_pc6", + "lcd_wr_n_pz3"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Power I2C (On-module) */ + pwr-i2c-scl-pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* + * THERMD_ALERT#, unlatched I2C address pin of LM95245 + * temperature sensor therefore requires disabling for + * now + */ + lcd-dc1-pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_PEN_INT# (On-module) */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vio>; + VDDIO-supply = <®_module_3v3>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <®_module_3v3>; + vcc2-supply = <®_module_3v3>; + vcc3-supply = <®_1v8_vio>; + vcc4-supply = <®_module_3v3>; + vcc5-supply = <®_module_3v3>; + vcc6-supply = <®_1v8_vio>; + vcc7-supply = <®_5v0_charge_pump>; + vccio-supply = <®_module_3v3>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "+V1.35_VDDIO_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddctrl_reg: vddctrl { + regulator-name = "+V1.0_VDD_CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + reg_1v8_vio: vio { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO1: unused */ + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 + * see also +V3.3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "EN_+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "+V1.2_CSI"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo4_reg: ldo4 { + regulator-name = "+V1.2_VDD_RTC"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for (unsupported) analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "+V2.8_AVDD_VDAC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "+V1.05_AVDD_PLLE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "+V1.2_AVDD_PLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "+V1.0_VDD_DDR_HS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + /* STMPE811 touch screen controller */ + touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; + + /* + * LM95245 temperature sensor + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN + */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + + /* SW: +V1.2_VDD_CORE */ + regulator@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + + regulator-name = "tps62362-vout"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + /* SPI4: CAN2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + /* SPI6: CAN1 */ + spi@7000de00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x1>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + + /* eMMC */ + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; + }; + + clk16m: clock-osc4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + clk32k_in: clock-xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_1v8_vio>; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_module_3v3>; + }; + + reg_5v0_charge_pump: regulator-5v0-charge-pump { + compatible = "regulator-fixed"; + regulator-name = "+V5.0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi new file mode 100644 index 000000000000..bae09d82594d --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ + +#include + +/ { + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + display-panel { + power-supply = <&vdd_pnl>; + ddc-i2c-bus = <&lcd_ddc>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + /* Texas Instruments SN75LVDS83B LVDS Transmitter */ + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts new file mode 100644 index 000000000000..a25b8560b0cd --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" +#include "tegra30-asus-nexus7-grouper.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts new file mode 100644 index 000000000000..06ef13ea5df8 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-nexus7-grouper-ti-pmic.dtsi" +#include "tegra30-asus-nexus7-grouper.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi new file mode 100644 index 000000000000..c0062353c1f1 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi @@ -0,0 +1,1320 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + gpio@6000d000 { + init-low-power-mode-hog { + gpio-hog; + gpios = ; + input; + }; + + init-mode-hog { + gpio-hog; + gpios = , + , + ; + output-low; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_cs1_n_pw0", + "lcd_sdin_pz2", + "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad14_ph6", + "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad15_ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2", + "pu2", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0", + "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_miso_px1", + "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs0_n_px3 { + nvidia,pins = "spi2_cs0_n_px3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb0 { + nvidia,pins = "pbb0", + "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7", + "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + /* GPS BCM4751 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vcc_3v3_ts>; + vccio-supply = <&vcc_3v3_ts>; + + touchscreen-size-x = <2112>; + touchscreen-size-y = <1280>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + status = "okay"; + + compass@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + interrupt-parent = <&gpio>; + interrupts = ; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + + light-sensor@1c { + compatible = "dynaimage,al3010"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + }; + + accelerometer@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + status = "okay"; + + rt5640: audio-codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + + realtek,dmic1-data-pin = <1>; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + + fuel-gauge@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + power-supplies = <&power_supply>; + }; + + power_supply: charger@6a { + compatible = "summit,smb347"; + reg = <0x6a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + summit,enable-charge-control = ; + summit,inok-polarity = ; + summit,enable-usb-charging; + + monitored-battery = <&battery_cell>; + + usb_vbus: usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + + /* + * SMB347 INOK input pin is connected to PMIC's + * ACOK output, which is fixed to ACTIVE_LOW as + * long as battery voltage is in a good range. + * + * Active INOK disables SMB347 output, so polarity + * needs to be toggled when we want to get the + * output. + */ + summit,needs-inok-toggle; + }; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH665 BCM4330 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&usb_vbus>; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + power-supply = <&vdd_5v0_sys>; + pwms = <&pwm 0 50000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <15>; + }; + + battery_cell: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <1800000>; + operating-range-celsius = <0 45>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + /* + * Nexus 7 supports two compatible panel models: + * + * 1. hydis,hv070wx2-1e0 + * 2. chunghwa,claa070wp03xg + * + * We want to use timing which is optimized for Nexus 7, + * hence we need to customize the timing. + */ + compatible = "panel-lvds"; + + width-mm = <94>; + height-mm = <150>; + rotation = <180>; + + data-mapping = "jeida-24"; + + /* DDC unconnected on Nexus 7 */ + /delete-property/ ddc-i2c-bus; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vcc_3v3_ts: regulator-ts { + compatible = "regulator-fixed"; + regulator-name = "ldo_s-1167_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-grouper", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "ASUS Google Nexus 7 ALC5642"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "DMIC1", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents Nexus 7 + * from getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi new file mode 100644 index 000000000000..694c7fe37eb8 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +/ { + i2c@7000d000 { + pmic: pmic@3c { + compatible = "maxim,max77663"; + reg = <0x3c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + cpu-pwr-req-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + input; + }; + + fps { + fps0 { + maxim,fps-event-source = ; + }; + + fps1 { + maxim,fps-event-source = ; + }; + + fps2 { + maxim,fps-event-source = ; + }; + }; + + max77620_default: pinmux { + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_sys>; + in-sd1-supply = <&vdd_5v0_sys>; + in-sd2-supply = <&vdd_5v0_sys>; + in-sd3-supply = <&vdd_5v0_sys>; + in-sd4-supply = <&vdd_5v0_sys>; + + in-ldo0-1-supply = <&vdd_1v35>; + in-ldo2-supply = <&vdd_3v3_sys>; + in-ldo3-5-supply = <&vdd_3v3_sys>; + in-ldo4-6-supply = <&vdd_5v0_sys>; + in-ldo7-8-supply = <&vdd_1v35>; + + vdd_cpu: sd0 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_core: sd1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_1v8: sd2 { + regulator-name = "vdd_gen1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v35: sd3 { + regulator-name = "vdd_ddr3l_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo0 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo3 { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5 { + regulator-name = "vdd_camera"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo8 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + regulator-usb { + compatible = "regulator-fixed"; + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + pmc@7000e400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x3c>; + nvidia,reg-addr = <0x41>; + nvidia,reg-data = <0xe0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi new file mode 100644 index 000000000000..8944a4a5a8d7 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -0,0 +1,1577 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + memory-controller@7000f000 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < + 0x00020001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < + 0x00010001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x73430303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x72830504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x72440a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < + 0x00000005 /* MC_EMEM_ARB_CFG */ + 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ + 0x70850f09 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < + 0x00020001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < + 0x00010001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x73430303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x72830504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x72440a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < + 0x00000005 /* MC_EMEM_ARB_CFG */ + 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ + 0x70850f09 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x00000008 /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000009 /* EMC_TXSR */ + 0x00000009 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000005 /* EMC_RC */ + 0x00000010 /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000012 /* EMC_TXSR */ + 0x00000012 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000004 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000000a /* EMC_RC */ + 0x00000020 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000023 /* EMC_TXSR */ + 0x00000023 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < + 0x0000000f /* EMC_RC */ + 0x00000034 /* EMC_RFC */ + 0x0000000a /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x000009e9 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000039 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x0000000a /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000a2a /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x002600a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x00014000 /* EMC_DLL_XFORM_DQS4 */ + 0x00014000 /* EMC_DLL_XFORM_DQS5 */ + 0x00014000 /* EMC_DLL_XFORM_DQS6 */ + 0x00014000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x018b000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000001f /* EMC_RC */ + 0x00000069 /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000b /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000c /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0156000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xf8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x00000008 /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000009 /* EMC_TXSR */ + 0x00000009 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000005 /* EMC_RC */ + 0x00000010 /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000012 /* EMC_TXSR */ + 0x00000012 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000004 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000000a /* EMC_RC */ + 0x00000020 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000023 /* EMC_TXSR */ + 0x00000023 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < + 0x0000000f /* EMC_RC */ + 0x00000034 /* EMC_RFC */ + 0x0000000a /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x000009e9 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000039 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x0000000a /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000a2a /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x002600a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x00014000 /* EMC_DLL_XFORM_DQS4 */ + 0x00014000 /* EMC_DLL_XFORM_DQS5 */ + 0x00014000 /* EMC_DLL_XFORM_DQS6 */ + 0x00014000 /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x018b000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ + 0xf8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0400013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi new file mode 100644 index 000000000000..ee4a3f482769 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +/ { + i2c@7000d000 { + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_sys>; + vcc2-supply = <&vdd_5v0_sys>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_sys>; + vcc5-supply = <&vdd_5v0_sys>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_sys>; + vccio-supply = <&vdd_5v0_sys>; + + regulators { + vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd2_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pmc@7000e400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x80>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi new file mode 100644 index 000000000000..c19a0419112a --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra30-asus-nexus7-grouper-common.dtsi" +#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" + +/ { + compatible = "asus,grouper", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + i2c@7000c500 { + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&gpio>; + interrupts = ; + + enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + }; + }; + + display-panel { + panel-timing { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <32>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts new file mode 100644 index 000000000000..f1c63feb4af9 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" +#include "tegra30-asus-nexus7-tilapia.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi new file mode 100644 index 000000000000..9169de34fa00 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" + +/ { + /* + * Tilapia's memory timings are pretty much the same as the Grouper's + * ones. There are few minor tunings made for a higher clock rates, + * these differentiating timings are overridden here for Tilapia. + */ + + memory-controller@7000f400 { + emc-timings-0 { + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000001f /* EMC_RC */ + 0x00000069 /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000b /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000c /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0156000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < + 0x0000000f /* EMC_RC */ + 0x00000034 /* EMC_RFC */ + 0x0000000a /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x000009e9 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000039 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x0000000a /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000a2a /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x002600a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x00014000 /* EMC_DLL_XFORM_DQS4 */ + 0x00014000 /* EMC_DLL_XFORM_DQS5 */ + 0x00014000 /* EMC_DLL_XFORM_DQS6 */ + 0x00014000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x018b000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi new file mode 100644 index 000000000000..94c80134574e --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra30-asus-nexus7-grouper-common.dtsi" +#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi" + +/ { + compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; + + gpio@6000d000 { + init-mode-3g-hog { + gpio-hog; + gpios = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + i2c@7000c500 { + proximity-sensor@28 { + compatible = "microchip,cap1106"; + reg = <0x28>; + + /* + * Binding doesn't support specifying linux,input-type + * and this results in unwanted key-presses handled by + * applications, hence keep it disabled for now. + */ + status = "disabled"; + + interrupt-parent = <&gpio>; + interrupts = ; + + linux,keycodes = , + , + , + , + , + ; + }; + + nfc@2a { + compatible = "nxp,pn544-i2c"; + reg = <0x2a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; + }; + }; + + display-panel { + enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <81750000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts new file mode 100644 index 000000000000..0406c5a69c12 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Prime TF201"; + compatible = "asus,tf201", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Atmel MXT768E touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0x80000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x71c6120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emem-configuration = < 0x00000007 0x8000005a + 0x00000003 0x00000004 0x0000000e 0x00000009 + 0x0000000c 0x00000002 0x00000002 0x00000008 + 0x00000001 0x00000000 0x00000004 0x00000005 + 0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000a0000 0x000a0000 0x000a0000 + 0x000a0000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00120220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00074000 0x00074000 0x00074000 + 0x00074000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00078000 0x00078000 0x00078000 + 0x00078000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x0002c000 0x0002c000 0x0002c000 + 0x0002c000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000024 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000d0000 0x000d0000 0x000d0000 + 0x000d0000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020005>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000002d>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001d + 0x00000040 0x00000014 0x00000008 0x00000007 + 0x00000009 0x00000003 0x0000000d 0x00000008 + 0x00000008 0x00000004 0x00000002 0x00000000 + 0x00000004 0x00000008 0x00000005 0x0000000d + 0x0000000f 0x00000763 0x00000000 0x000001d8 + 0x00000003 0x00000003 0x00000008 0x00000000 + 0x00000001 0x0000000e 0x00000046 0x00000046 + 0x00000008 0x00000019 0x0000000b 0x00000004 + 0x00000002 0x00000820 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0140091 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000b4 0x000d000d 0xa0f10404 0x00000000 + 0x00000000 0x80000fde 0xe0000000 0xff00ff88 >; + }; + }; + }; + + usb-phy@7d000000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + usb-phy@7d008000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + display-panel { + compatible = "hannstar,hsd101pww2"; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + opp-table-actmon { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf201", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Prime TF201 RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts new file mode 100644 index 000000000000..970a1f08dc8c --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts @@ -0,0 +1,1032 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad TF300T"; + compatible = "asus,tf300t", "nvidia,tegra30"; + + gpio@6000d000 { + tf300t-init-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = < + 0x00000600 /* DMIC_LR, output */ + 0x00000680 /* DMIC_DAT, input */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0605 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000005 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000011 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b11 0x70ea1f12 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0f000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000003 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000b 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x0000006a 0x00000018 0x00000008 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0155000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xd8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000008 + 0x00000008 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; + + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf300t", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus Transformer Pad TF300T WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,audio-codec = <&wm8903>; + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts new file mode 100644 index 000000000000..4861db8e1e59 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts @@ -0,0 +1,1104 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad 3G TF300TG"; + compatible = "asus,tf300tg", "nvidia,tegra30"; + + gpio@6000d000 { + tf300tg-init-hog { + gpio-hog; + gpios = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0x8000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0x80000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0a000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00040000 0x00040000 0x00040000 + 0x00040000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0600013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; + + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf300tg", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Pad TF300TG RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts new file mode 100644 index 000000000000..efde7dad718a --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" + +/ { + model = "Asus Transformer Infinity TF700T"; + compatible = "asus,tf700t", "nvidia,tegra30"; + + host1x@50000000 { + lcd: dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2944>; + touchscreen-size-y = <1856>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + }; + + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&lcd_ddc>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsi@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + data-lines = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; + }; + + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf700t", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Infinity TF700T RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi new file mode 100644 index 000000000000..bdb898ad6262 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi @@ -0,0 +1,1788 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000000"; /* uSD slot */ + mmc2 = "/mmc@78000400"; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + gpio@6000d000 { + init-lpm-in-hog { + gpio-hog; + gpios = , + ; + input; + }; + + init-lpm-out-hog { + gpio-hog; + gpios = , + ; + output-low; + }; + + usb-charge-limit-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hp_detect { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + mic_detect { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWM pimnmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + bluetooth { + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_com>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "okay"; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_vio>; + }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3010"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_vio>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_bat>; + vcc2-supply = <&vdd_5v0_bat>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_5v0_sys>; + vcc5-supply = <&vdd_5v0_bat>; + vcc6-supply = <&vdd_3v3_sys>; + vcc7-supply = <&vdd_5v0_bat>; + vccio-supply = <&vdd_5v0_bat>; + + pmic-sleep-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Transformers */ + + vddio_ddr: vdd2 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + /* FIXME: Without this, voltage switching fails */ + regulator-always-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3100000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* LDO5 is not used by Transformers */ + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + /* FIXME: LP1 doesn't work at the moment */ + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + mmc@78000000 { + status = "okay"; + + /* FIXME: Full 208Mhz clock rate doesn't work reliably */ + max-frequency = <104000000>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_com>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + mmc-ddr-3_3v; + non-removable; + }; + + /* USB via ASUS connector */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_bat>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 4000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <40>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + switch-lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + vdd_5v0_bat: regulator-bat { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_cp: regulator-sby { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sby"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_1v5_ddr: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_com: regulator-com { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + nvidia,i2s-controller = <&tegra_i2s1>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + nvidia,coupled-mic-hp-det; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Transformers from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-beaver.dts b/arch/arm/boot/dts/nvidia/tegra30-beaver.dts new file mode 100644 index 000000000000..51769d5132ae --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-beaver.dts @@ -0,0 +1,2138 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + model = "NVIDIA Tegra30 Beaver evaluation board"; + compatible = "nvidia,beaver", "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000d000/tps65911@2d"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x80000000 0x7ff00000>; + }; + + pcie@3000 { + status = "okay"; + + avdd-pexa-supply = <&ldo1_reg>; + vdd-pexa-supply = <&ldo1_reg>; + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + avdd-plle-supply = <&ldo1_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_pexs_reg>; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + vdd-supply = <&sys_3v3_reg>; + pll-supply = <&vio_reg>; + + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmiddc>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <1>; + nvidia,slew-rate-falling = <1>; + }; + gpv { + nvidia,pins = "drive_gpv"; + nvidia,pull-up-strength = <16>; + }; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + hdmiddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + rt5640: rt5640@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; + }; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v_in_reg>; + vcc2-supply = <&vdd_5v_in_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v_in_reg>; + vcc5-supply = <&vdd_5v_in_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v_in_reg>; + vccio-supply = <&vdd_5v_in_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + core_vdd_reg: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@1 { + compatible = "winbond,w25q32", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; + }; + + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + + mmc@78000000 { + status = "okay"; + vqmmc-supply = <&ldo5_reg>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d004000 { + status = "okay"; + }; + + phy2: usb-phy@7d004000 { + vbus-supply = <&sys_3v3_reg>; + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + gpled1 { + label = "LED1"; /* CR5A1 (blue) */ + gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; + }; + gpled2 { + label = "LED2"; /* CR4A2 (green) */ + gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + vdd_5v_in_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_in"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + chargepump_5v_reg: regulator-chargepump { + compatible = "regulator-fixed"; + regulator-name = "chargepump_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + ddr_reg: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + vdd_5v_sata_reg: regulator-sata { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_sata"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + usb1_vbus_reg: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; + + usb3_vbus_reg: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; + + sys_3v3_reg: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3,vdd_3v3_alw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + sys_3v3_pexs_reg: regulator-pexs { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3_pexs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_5v0_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-beaver", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Beaver"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts new file mode 100644 index 000000000000..247185314f46 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A02 version of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; + compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; + + mmc@78000400 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + + ddr_reg: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; + + sys_3v3_reg: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; + + usb1_vbus_reg: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_bl_reg: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; + }; +}; + diff --git a/arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts new file mode 100644 index 000000000000..2911f08863a0 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A04 and later versions of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; + compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; + + mmc@78000400 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + + ddr_reg: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; + + sys_3v3_reg: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; + + usb1_vbus_reg: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + }; + + vdd_bl_reg: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; + + vdd_bl2_reg: regulator-bl2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi new file mode 100644 index 000000000000..37a9c5a0ca30 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/** + * This file contains common DT entry for all fab version of Cardhu. + * There is multiple fab version of Cardhu starting from A01 to A07. + * Cardhu fab version A01 and A03 are not supported. Cardhu fab version + * A02 will have different sets of GPIOs for fixed regulator compare to + * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are + * compatible with fab version A04. Based on Cardhu fab version, the + * related dts file need to be chosen like for Cardhu fab version A02, + * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use + * tegra30-cardhu-a04.dts. + * The identification of board is done in two ways, by looking the sticker + * on PCB and by reading board id eeprom. + * The sticker will have number like 600-81291-1000-002 C.3. In this 4th + * number is the fab version like here it is 002 and hence fab version A02. + * The (downstream internal) U-Boot of Cardhu display the board-id as + * follows: + * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 + * In this Fab version is 02 i.e. A02. + * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). + * The location 0x8 of this eeprom contains the Fab version. It is 1 byte + * wide. + */ + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000d000/tps65911@2d"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + pcie@3000 { + status = "okay"; + + /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + hvdd-pex-supply = <&pex_hvdd_3v3_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + avdd-plle-supply = <&ldo2_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6", + "uart3_cts_n_pa1", + "uart3_rts_n_pc0", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + panelddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + + /* ALS and Proximity sensor */ + isl29028@44 { + compatible = "isil,isl29028"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + i2cmux@70 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; + }; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + interrupt-parent = <&gpio>; + interrupts = ; + #thermal-sensor-cells = <1>; + }; + + vdd_core: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@1 { + compatible = "winbond,w25q32", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + + mmc@78000000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + interrupt-parent = <&pmic>; + interrupts = <2 0>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + + panel: panel { + compatible = "chunghwa,claa101wb01"; + ddc-i2c-bus = <&panelddc>; + + power-supply = <&vdd_pnl1_reg>; + enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + + vdd_ac_bat_reg: regulator-acbat { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + cam_1v8_reg: regulator-cam { + compatible = "regulator-fixed"; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vio_reg>; + }; + + cp_5v_reg: regulator-5v0cp { + compatible = "regulator-fixed"; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + emmc_3v3_reg: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + modem_3v3_reg: regulator-modem { + compatible = "regulator-fixed"; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + }; + + pex_hvdd_3v3_reg: regulator-pex { + compatible = "regulator-fixed"; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam1_ldo_reg: regulator-cam1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam2_ldo_reg: regulator-cam2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam3_ldo_reg: regulator-cam3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_com_reg: regulator-com { + compatible = "regulator-fixed"; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator-fuse { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_pnl1_reg: regulator-pnl1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_vid_reg: regulator-vid { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-cardhu", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Cardhu"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip0: cpu-alert0 { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts new file mode 100644 index 000000000000..36615c5fda2c --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra30-colibri.dtsi" + +/ { + model = "Toradex Colibri T30 on Colibri Evaluation Board"; + compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", + "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@2d"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + /* Colibri UART-A */ + serial@70006000 { + status = "okay"; + }; + + /* Colibri UART-C */ + serial@70006040 { + status = "okay"; + }; + + /* Colibri UART-B */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* CAM_I2C (I2C3): unused */ + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Colibri SSP */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + /* CAN_INT */ + interrupts = ; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; + }; + + /* SD/MMC */ + mmc@78000200 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ + no-1-8-v; + }; + + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbc_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* PWM */ + }; + + clk16m: clock-osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "SODIMM pin 45 wakeup"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbc_vbus: regulator-usbc-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB5"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + }; + + /* USBH_PEN resp. USB_P_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi new file mode 100644 index 000000000000..ed6106f1bea1 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi @@ -0,0 +1,1064 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra30.dtsi" + +/* + * Toradex Colibri T30 Module Device Tree + * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B + */ +/ { + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + gpio: gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1-out-pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri Address/Data Bus (GMI) */ + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_ad8_ph0", + "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6", + "gmi_ad15_ph7", + "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs4_n_pk2", + "gmi_cs2_n_pk3", + "gmi_iordy_pi5", + "gmi_oe_n_pi1", + "gmi_wait_pi7", + "gmi_wr_n_pi0", + "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3", + "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5", + "spi1_sck_px5", + "spi1_mosi_px4", + "spi1_cs0_n_px6", + "spi2_cs0_n_px3", + "spi2_miso_px1", + "spi2_mosi_px0", + "spi2_sck_px2", + "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Further pins may be used as GPIOs */ + dap4-din-pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7", + "pbb7", + "sdmmc1_clk_pz0", + "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat3_py4", + "uart3_cts_n_pa1", + "uart3_txd_pw6", + "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-d18-pm2 { + nvidia,pins = "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-cs0-n-pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdin_pz2", + "pu0", + "pu1", + "pu2", + "pu3", + "pu4", + "pu5", + "pu6", + "spi1_miso_px7", + "uart3_rts_n_pc0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr0-pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_sck_pz4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4", + "pbb5", + "pbb6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed RDnWR and therefore disabled */ + lcd-cs1-n-pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed GMI_CLK and therefore disabled */ + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */ + sdmmc3-dat4-pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */ + sdmmc3-dat5-pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri BL_ON */ + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri Backlight PWM */ + sdmmc3-dat3-pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri CAN_INT */ + kb-row8-ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri DDC */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri EXT_IO* */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-in-pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri GPIO */ + clk2-out-pw5 { + nvidia,pins = "clk2_out_pw5", + "pcc2", + "pv3", + "sdmmc1_dat2_py5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr1-pc1 { + nvidia,pins = "lcd_pwr1_pc1", + "pex_l1_clkreq_n_pdd6", + "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri HOTPLUG_DETECT (HDMI) */ + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri I2C */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Colibri LCD (L_* resp. LDD<*>) */ + lcd-d0-pe0 { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_pclk_pb3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE + * today's display need DE, disable LCD_M1 + */ + lcd-m1-pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri MMC */ + kb-row10-ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + kb-row11-ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Colibri MMC_CD */ + gmi-wp-n-pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb0 { + nvidia,pins = "pbb0", + "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri nRESET_OUT */ + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Colibri Parallel Camera (Optional) + * pins multiplexed with others and therefore disabled + */ + vi-vsync-pd6 { + nvidia,pins = "vi_d0_pt4", + "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7", + "vi_d10_pt2", + "vi_d11_pt3", + "vi_hsync_pd7", + "vi_mclk_pt1", + "vi_pclk_pt0", + "vi_vsync_pd6"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri PWM */ + sdmmc3-dat2-pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri PWM */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri PWM */ + sdmmc3-cmd-pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri SSP */ + ulpi-clk-py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Multiplexed SSPFRM, SSPTXD and therefore disabled */ + sdmmc3-dat6-pd3 { + nvidia,pins = "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri UART-A */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri UART-B */ + gmi-a16-pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri UART-C */ + uart2-rxd { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri USBC_DET */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri USBH_PEN */ + spi2-cs1-n-pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri USBH_OC */ + spi2-cs2-n-pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri VGA not supported and therefore disabled */ + crt-hsync-pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC (On-module) */ + sdmmc4-clk-pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_cmd_pt7", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat0-paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */ + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1", + "pex_wake_n_pdd3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN_V_BUS, LAN_RESET# (On-module) */ + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2", + "pex_l0_prsnt_n_pdd0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */ + pex-l2-rst-n-pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Not connected and therefore disabled */ + clk1-req-pee2 { + nvidia,pins = "clk1_req_pee2", + "pex_l1_prsnt_n_pdd4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-req-pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk3_out_pee0", + "clk3_req_pee1", + "clk_32k_out_pa0", + "hdmi_cec_pee3", + "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-pi2 { + nvidia,pins = "gmi_dqs_pi2", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col6_pq6", + "kb_col7_pq7", + "kb_row5_pr5", + "kb_row6_pr6", + "kb_row7_pr7", + "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr2-pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Power I2C (On-module) */ + pwr-i2c-scl-pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* + * THERMD_ALERT#, unlatched I2C address pin of LM95245 + * temperature sensor therefore requires disabling for + * now + */ + lcd-dc1-pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_PEN_INT# (On-module) */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + }; + + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller (On-module) + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vio>; + VDDIO-supply = <®_module_3v3>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <®_module_3v3>; + vcc2-supply = <®_module_3v3>; + vcc3-supply = <®_1v8_vio>; + vcc4-supply = <®_module_3v3>; + vcc5-supply = <®_module_3v3>; + vcc6-supply = <®_1v8_vio>; + vcc7-supply = <®_5v0_charge_pump>; + vccio-supply = <®_module_3v3>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "+V1.35_VDDIO_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + /* SW2: unused */ + + vddctrl_reg: vddctrl { + regulator-name = "+V1.0_VDD_CPU"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + reg_1v8_vio: vio { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO1: unused */ + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + * see also +V3.3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "EN_+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* LDO3: unused */ + + ldo4_reg: ldo4 { + regulator-name = "+V1.2_VDD_RTC"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for (unsupported) analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "+V2.8_AVDD_VDAC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "+V1.05_AVDD_PLLE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "+V1.2_AVDD_PLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "+V1.0_VDD_DDR_HS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + /* STMPE811 touch screen controller */ + touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* forbid to use ADC channels 3-0 (touch) */ + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; + + /* + * LM95245 temperature sensor + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN + */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + + /* SW: +V1.2_VDD_CORE */ + vdd_core: regulator@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + + regulator-name = "tps62362-vout"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x1>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + + /* eMMC */ + mmc@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; + }; + + /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */ + usb@7d004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "usbb95,772b"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_lan_v_bus>; + }; + + clk32k_in: clock-xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_1v8_vio>; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_module_3v3>; + }; + + reg_5v0_charge_pump: regulator-5v0-charge-pump { + compatible = "regulator-fixed"; + regulator-name = "+V5.0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_lan_v_bus: regulator-lan-v-bus { + compatible = "regulator-fixed"; + regulator-name = "LAN_V_BUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Colibri T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi new file mode 100644 index 000000000000..b8e0e9117021 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: opp-table-cpu0 { + opp-51000000-800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp-51000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-51000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp-102000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-102000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp-204000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-204000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-312000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-312000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-340000000-800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp-340000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-370000000-800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp-456000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-456000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-475000000-800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp-475000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-608000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-608000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-620000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-640000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-640000000-900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp-760000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-760000000-900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp-760000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-760000000-975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp-816000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-816000000-912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp-860000000-850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp-860000000-900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp-860000000-975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp-860000000-1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp-910000000-900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp-1000000000-900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp-1000000000-975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp-1000000000-1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp-1000000000-1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp-1100000000-900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp-1100000000-975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp-1100000000-1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp-1100000000-1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp-1100000000-1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp-1150000000-975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp-1200000000-975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp-1200000000-1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp-1200000000-1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp-1200000000-1050 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp-1200000000-1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp-1300000000-1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp-1300000000-1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp-1300000000-1050 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp-1300000000-1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp-1300000000-1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp-1300000000-1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp-1300000000-1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp-1300000000-1175 { + opp-microvolt = <1175000 1175000 1250000>; + }; + + opp-1400000000-1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp-1400000000-1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp-1400000000-1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp-1400000000-1175 { + opp-microvolt = <1175000 1175000 1250000>; + }; + + opp-1400000000-1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp-1500000000-1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp-1500000000-1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp-1500000000-1200 { + opp-microvolt = <1200000 1200000 1250000>; + }; + + opp-1500000000-1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp-1600000000-1212 { + opp-microvolt = <1212000 1212000 1250000>; + }; + + opp-1600000000-1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp-1700000000-1212 { + opp-microvolt = <1212000 1212000 1250000>; + }; + + opp-1700000000-1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi new file mode 100644 index 000000000000..5b9ebb75a09f --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-51000000-800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x31FE>; + opp-hz = /bits/ 64 <51000000>; + }; + + opp-51000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C01>; + opp-hz = /bits/ 64 <51000000>; + }; + + opp-51000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <51000000>; + }; + + opp-102000000-800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x31FE>; + opp-hz = /bits/ 64 <102000000>; + }; + + opp-102000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C01>; + opp-hz = /bits/ 64 <102000000>; + }; + + opp-102000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <102000000>; + }; + + opp-204000000-800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x31FE>; + opp-hz = /bits/ 64 <204000000>; + opp-suspend; + }; + + opp-204000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C01>; + opp-hz = /bits/ 64 <204000000>; + opp-suspend; + }; + + opp-204000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <204000000>; + opp-suspend; + }; + + opp-312000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C00>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp-312000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp-340000000-800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0192>; + opp-hz = /bits/ 64 <340000000>; + }; + + opp-340000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0F 0x0001>; + opp-hz = /bits/ 64 <340000000>; + }; + + opp-370000000-800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x306C>; + opp-hz = /bits/ 64 <370000000>; + }; + + opp-456000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C00>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp-456000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp-475000000-800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x31FE>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp-475000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>, + <0x01 0x0010>, <0x01 0x0080>, + <0x01 0x0100>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp-608000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0400>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-608000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp-620000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x306C>; + opp-hz = /bits/ 64 <620000000>; + }; + + opp-640000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>, + <0x04 0x0002>, <0x08 0x0002>, + <0x02 0x0010>, <0x04 0x0010>, + <0x08 0x0010>, <0x02 0x0080>, + <0x04 0x0080>, <0x08 0x0080>, + <0x10 0x0080>, <0x02 0x0100>, + <0x04 0x0100>, <0x08 0x0100>, + <0x10 0x0100>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp-640000000-900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp-760000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>, + <0x08 0x0004>, <0x08 0x0008>, + <0x08 0x0010>, <0x08 0x0080>, + <0x10 0x0080>, <0x08 0x0100>, + <0x10 0x0100>, <0x01 0x0400>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, + <0x04 0x0002>, <0x02 0x0004>, + <0x04 0x0004>, <0x02 0x0008>, + <0x04 0x0008>, <0x02 0x0010>, + <0x04 0x0010>, <0x02 0x0080>, + <0x04 0x0080>, <0x02 0x0100>, + <0x04 0x0100>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-760000000-975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp-816000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0400>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-816000000-912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp-860000000-850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0C 0x0001>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp-860000000-900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, + <0x08 0x0002>, <0x04 0x0004>, + <0x08 0x0004>, <0x04 0x0008>, + <0x08 0x0008>, <0x04 0x0010>, + <0x08 0x0010>, <0x04 0x0080>, + <0x08 0x0080>, <0x10 0x0080>, + <0x04 0x0100>, <0x08 0x0100>, + <0x10 0x0100>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp-860000000-975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, + <0x02 0x0004>, <0x02 0x0008>, + <0x02 0x0010>, <0x02 0x0080>, + <0x02 0x0100>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp-860000000-1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp-910000000-900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x18 0x3060>; + opp-hz = /bits/ 64 <910000000>; + }; + + opp-1000000000-900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0C 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>, + <0x08 0x0002>, <0x04 0x0004>, + <0x08 0x0004>, <0x04 0x0008>, + <0x08 0x0008>, <0x04 0x0010>, + <0x08 0x0010>, <0x04 0x0080>, + <0x08 0x0080>, <0x10 0x0080>, + <0x04 0x0100>, <0x08 0x0100>, + <0x10 0x0100>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1000000000-1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp-1100000000-900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp-1100000000-975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>, + <0x08 0x0004>, <0x08 0x0008>, + <0x08 0x0010>, <0x08 0x0080>, + <0x10 0x0080>, <0x08 0x0100>, + <0x10 0x0100>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp-1100000000-1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>, + <0x04 0x0004>, <0x04 0x0008>, + <0x04 0x0010>, <0x04 0x0080>, + <0x04 0x0100>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp-1100000000-1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp-1100000000-1075 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp-1150000000-975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x18 0x3060>; + opp-hz = /bits/ 64 <1150000000>; + }; + + opp-1200000000-975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, + <0x08 0x0004>, <0x08 0x0008>, + <0x08 0x0010>, <0x08 0x0080>, + <0x10 0x0080>, <0x08 0x0100>, + <0x10 0x0100>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, + <0x04 0x0004>, <0x04 0x0008>, + <0x04 0x0010>, <0x04 0x0080>, + <0x04 0x0100>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1050 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1075 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1200000000-1100 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp-1300000000-1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>, + <0x10 0x0100>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, + <0x08 0x0080>, <0x08 0x0100>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1050 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>, + <0x08 0x0004>, <0x08 0x0008>, + <0x08 0x0010>, <0x08 0x0020>, + <0x08 0x0040>, <0x04 0x0080>, + <0x04 0x0100>, <0x08 0x1000>, + <0x08 0x2000>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1075 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>, + <0x04 0x0008>, <0x04 0x0010>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1100 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x001C>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1125 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1150 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0182>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1300000000-1175 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp-1400000000-1100 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x18 0x307C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp-1400000000-1125 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x000C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp-1400000000-1150 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp-1400000000-1175 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp-1400000000-1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp-1500000000-1125 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>, + <0x10 0x0040>, <0x10 0x1000>, + <0x10 0x2000>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp-1500000000-1150 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>, + <0x08 0x0040>, <0x08 0x1000>, + <0x08 0x2000>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp-1500000000-1200 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp-1500000000-1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp-1600000000-1212 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1600000000>; + }; + + opp-1600000000-1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1600000000>; + }; + + opp-1700000000-1212 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1700000000>; + }; + + opp-1700000000-1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1700000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-ouya.dts b/arch/arm/boot/dts/nvidia/tegra30-ouya.dts new file mode 100644 index 000000000000..eef27c82987b --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-ouya.dts @@ -0,0 +1,4795 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + model = "Ouya Game Console"; + compatible = "ouya,ouya", "nvidia,tegra30"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* WiFi */ + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; /* Debug Port */ + serial1 = &uartc; /* Bluetooth */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + vdd-supply = <&vdd_vid_reg>; + pll-supply = <&ldo7_reg>; + hdmi-supply = <&sys_3v3_reg>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH660 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&sys_3v3_reg>; + vddio-supply = <&vdd_1v8>; + + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_reg>; + vcc2-supply = <&vdd_5v0_reg>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_5v0_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_reg>; + vccio-supply = <&vdd_5v0_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1270000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + + vdd_core: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f000 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74430504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x74040a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000f /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000010 /* EMC_TXSR */ + 0x00000010 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001e /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000020 /* EMC_TXSR */ + 0x00000020 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x0000003d /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000040 /* EMC_TXSR */ + 0x00000040 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000076 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000007c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00044000 /* EMC_DLL_XFORM_DQS0 */ + 0x00044000 /* EMC_DLL_XFORM_DQS1 */ + 0x00044000 /* EMC_DLL_XFORM_DQS2 */ + 0x00044000 /* EMC_DLL_XFORM_DQS3 */ + 0x00044000 /* EMC_DLL_XFORM_DQS4 */ + 0x00044000 /* EMC_DLL_XFORM_DQS5 */ + 0x00044000 /* EMC_DLL_XFORM_DQS6 */ + 0x00044000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00058000 /* EMC_DLL_XFORM_DQ0 */ + 0x00058000 /* EMC_DLL_XFORM_DQ1 */ + 0x00058000 /* EMC_DLL_XFORM_DQ2 */ + 0x00058000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0148000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ee /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000f8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000c /* EMC_DLL_XFORM_DQS0 */ + 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <&sdmmc_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH660 BCM4330 */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + + keep-power-in-suspend; + bus-width = <8>; + non-removable; + vmmc-supply = <&sys_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + nvidia,default-tap = <0x0F>; + max-frequency = <25500000>; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + usb@7d004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet@2 { /* SMSC 10/100T Ethernet Controller */ + compatible = "usb424,9e00"; + reg = <2>; + local-mac-address = [00 11 22 33 44 55]; + }; + }; + + usb-phy@7d004000 { + vbus-supply = <&vdd_smsc>; + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + }; + + fan: fan { + compatible = "gpio-fan"; + gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; + }; + + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_12v_in: regulator-vdd-12v-in { + compatible = "regulator-fixed"; + regulator-name = "vdd_12v_in"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + sdmmc_3v3_reg: regulator-sdmmc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "sdmmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + regulator-always-on; + }; + + vdd_vid_reg: regulator-vdd-vid { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + regulator-boot-on; + }; + + ddr_reg: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + sys_3v3_reg: regulator-sys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + vdd_5v0_reg: regulator-vdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + vdd_smsc: regulator-vdd-smsc { + compatible = "regulator-fixed"; + regulator-name = "vdd_smsc"; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; + }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + + thermal-sensors = <&cpu_temp 1>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts new file mode 100644 index 000000000000..8d10eb8b48b9 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts @@ -0,0 +1,2858 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Pegatron Chagall"; + compatible = "pegatron,chagall", "nvidia,tegra30"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + mmc2 = &sdmmc3; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* HDMI-CEC pinmux */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_pwr2_pc6", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_sdin_pz2", + "lcd_wr_n_pz3", + "lcd_sck_pz4", + "lcd_cs1_n_pw0", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row7_pr7", + "kb_row10_ps2", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs4_n_pk2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_ad12_ph4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI hot-plug-detect */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2", + "kb_row5_pr5"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <5>; + nvidia,pull-up-strength = <5>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_lcd2 { + nvidia,pins = "drive_lcd2"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-AH663 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Atmel touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c3: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + /* AsahiKASEI AK8975 magnetometer sensor */ + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + vdd-supply = <&vdd_3v3_sen>; + vid-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sen>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sen>; + vlogic-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c5: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_sys>; + vcc2-supply = <&vdd_5v0_sys>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_1v8_vio>; + vcc5-supply = <&vdd_5v0_sys>; + vcc6-supply = <&vddio_1v2_ddr>; + vcc7-supply = <&vdd_5v0_sys>; + vccio-supply = <&vdd_5v0_sys>; + + pmic-sleep-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>, + <2 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>, + <8 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Chagall */ + + vddio_1v2_ddr: vdd2 { + regulator-name = "vddio_1v2_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <3200000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_1v3_cam_isp"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_sen: regulator-sensors { + compatible = "regulator-fixed"; + regulator-name = "sen_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb1: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_micro_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb3: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_typea_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00038000 0x00038000 0x00038000 + 0x00038000 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10404 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x00060220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0200003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000a0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-AH663 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&vdd_vbus_usb1>; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_vbus_usb3>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <15>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "jeida-24"; + + panel-timing { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + vsync-len = <5>; + vfront-porch = <3>; + vback-porch = <12>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-insert { + label = "Chagall Dock"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + switch-lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + sound { + compatible = "pegatron,tegra-audio-wm8903-chagall", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Pegatron Chagall WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1R", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Chagall from getting too hot from a user's tactile + * perspective. The CPU zone is intended to protect + * silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi new file mode 100644 index 000000000000..a2d557155114 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi @@ -0,0 +1,1648 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1350000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-level = <1000000>; + }; + + core_opp_1050: opp-1050000 { + opp-microvolt = <1050000 1050000 1350000>; + opp-level = <1050000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1350000>; + opp-level = <1100000>; + }; + + core_opp_1150: opp-1150000 { + opp-microvolt = <1150000 1150000 1350000>; + opp-level = <1150000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1350000>; + opp-level = <1200000>; + }; + + core_opp_1250: opp-1250000 { + opp-microvolt = <1250000 1250000 1350000>; + opp-level = <1250000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1350000>; + opp-level = <1300000>; + }; + + core_opp_1350: opp-1350000 { + opp-microvolt = <1350000 1350000 1350000>; + opp-level = <1350000>; + }; + }; + + emc_icc_dvfs_opp_table: opp-table-emc { + compatible = "operating-points-v2"; + + opp-12750000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-12750000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-12750000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-25500000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-25500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-25500000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-27000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-27000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-27000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-51000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-51000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-51000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-54000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-54000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-54000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-102000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-102000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-102000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-108000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-108000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-204000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + opp-suspend; + }; + + opp-204000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + opp-suspend; + }; + + opp-266500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <266500000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-266500000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <266500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-333500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-333500000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-333500000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-375000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-375000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-375000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-400000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-400000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-400000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-416000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-450000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-450000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-500000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-533000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-533000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-625000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-625000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-667000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-750000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <750000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-800000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-900000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + emc_bw_dfs_opp_table: opp-table-actmon { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <102000>; + }; + + opp-25500000 { + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <204000>; + }; + + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <216000>; + }; + + opp-51000000 { + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <408000>; + }; + + opp-54000000 { + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <432000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <816000>; + }; + + opp-108000000 { + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <864000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <1632000>; + opp-suspend; + }; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <2132000>; + }; + + opp-333500000 { + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <2668000>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3200000>; + }; + + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3328000>; + }; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3600000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4000000>; + }; + + opp-533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4264000>; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x000E>; + opp-peak-kBps = <5000000>; + }; + + opp-667000000 { + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x0006>; + opp-peak-kBps = <5336000>; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <6400000>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <7200000>; + }; + }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-188000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <188000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-222000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <222000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-242000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <242000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-254000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <254000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-216000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-219000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <219000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-267000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-371000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <371000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1150>; + }; + + opp-409000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <409000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-425000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <425000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-470000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <470000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>, <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>, <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>, <&core_opp_1350>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + dsia_dvfs_opp_table: opp-table-dsia { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + dsib_dvfs_opp_table: opp-table-dsib { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-51000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-136000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <136000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-164000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-191000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <191000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-205000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <205000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-216000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1150>; + }; + + opp-227000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <227000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1100>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-334000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <334000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-378000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <378000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + pll_c_dvfs_opp_table: opp-table-pllc { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + + opp-1200000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1350>; + }; + }; + + pll_e_dvfs_opp_table: opp-table-plle { + compatible = "operating-points-v2"; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_m_dvfs_opp_table: opp-table-pllm { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-228000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-275000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-352000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <352000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-400000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-437000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <437000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + fuse_burn_dvfs_opp_table: opp-table-fuseburn { + compatible = "operating-points-v2"; + + opp-26000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <26000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1150>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-108000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-115000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <115000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-130000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-133000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + }; + + pwm_dvfs_opp_table: opp-table-pwm { + compatible = "operating-points-v2"; + + opp-408000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sbc1_dvfs_opp_table: opp-table-sbc1 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc2_dvfs_opp_table: opp-table-sbc2 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc3_dvfs_opp_table: opp-table-sbc3 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc4_dvfs_opp_table: opp-table-sbc4 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc5_dvfs_opp_table: opp-table-sbc5 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc6_dvfs_opp_table: opp-table-sbc6 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi new file mode 100644 index 000000000000..9cba67b54111 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -0,0 +1,1348 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include + +#include "tegra30-peripherals-opp.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x0>; + }; + + pcie@3000 { + compatible = "nvidia,tegra30-pcie"; + device_type = "pci"; + reg = <0x00003000 0x00000800>, /* PADS registers */ + <0x00003800 0x00000200>, /* AFI registers */ + <0x10000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ + <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ + <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PLL_E>, + <&tegra_car TEGRA30_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + bus-range = <0x00 0xff>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + + host1x@50000000 { + compatible = "nvidia,tegra30-host1x"; + reg = <0x50000000 0x00024000>; + interrupts = , /* syncpt */ + ; /* general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; + reset-names = "host1x", "mc"; + iommus = <&mc TEGRA_SWGROUP_HC>; + power-domains = <&pd_heg>; + operating-points-v2 = <&host1x_dvfs_opp_table>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe@54040000 { + compatible = "nvidia,tegra30-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_MPE>; + + status = "disabled"; + }; + + vi@54080000 { + compatible = "nvidia,tegra30-vi"; + reg = <0x54080000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; + }; + + epp@540c0000 { + compatible = "nvidia,tegra30-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; + power-domains = <&pd_heg>; + operating-points-v2 = <&epp_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_EPP>; + + status = "disabled"; + }; + + isp@54100000 { + compatible = "nvidia,tegra30-isp"; + reg = <0x54100000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; + power-domains = <&pd_venc>; + + iommus = <&mc TEGRA_SWGROUP_ISP>; + + status = "disabled"; + }; + + gr2d@54140000 { + compatible = "nvidia,tegra30-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_GR2D>; + resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; + reset-names = "2d", "mc"; + power-domains = <&pd_heg>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_G2>; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra30-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_GR3D>, + <&tegra_car TEGRA30_CLK_GR3D2>; + clock-names = "3d", "3d2"; + resets = <&tegra_car 24>, + <&tegra_car 98>, + <&mc TEGRA30_MC_RESET_3D>, + <&mc TEGRA30_MC_RESET_3D2>; + reset-names = "3d", "3d2", "mc", "mc2"; + power-domains = <&pd_3d0>, <&pd_3d1>; + power-domain-names = "3d0", "3d1"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_NV>, + <&mc TEGRA_SWGROUP_NV2>; + }; + + dc@54200000 { + compatible = "nvidia,tegra30-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_DC>; + + nvidia,head = <0>; + + interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, + <&mc TEGRA30_MC_DISPLAY0B &emc>, + <&mc TEGRA30_MC_DISPLAY1B &emc>, + <&mc TEGRA30_MC_DISPLAY0C &emc>, + <&mc TEGRA30_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra30-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_DISP2>, + <&tegra_car TEGRA30_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; + + iommus = <&mc TEGRA_SWGROUP_DCB>; + + nvidia,head = <1>; + + interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, + <&mc TEGRA30_MC_DISPLAY0BB &emc>, + <&mc TEGRA30_MC_DISPLAY1BB &emc>, + <&mc TEGRA30_MC_DISPLAY0CB &emc>, + <&mc TEGRA30_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + + rgb { + status = "disabled"; + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra30-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_HDMI>, + <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; + status = "disabled"; + }; + + tvo@542c0000 { + compatible = "nvidia,tegra30-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; + status = "disabled"; + }; + + dsi@54300000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsia_dvfs_opp_table>; + status = "disabled"; + }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsib_dvfs_opp_table>; + status = "disabled"; + }; + }; + + timer@50040600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x50040600 0x20>; + interrupt-parent = <&intc>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TWD>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <6 6 2>; + arm,tag-latency = <5 5 2>; + cache-unified; + cache-level = <2>; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra30-ictlr"; + reg = <0x60004000 0x100>, + <0x60004100 0x50>, + <0x60004200 0x50>, + <0x60004300 0x50>, + <0x60004400 0x50>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + timer@60005000 { + compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA30_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra30-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + + pll-c { + compatible = "nvidia,tegra30-pllc"; + clocks = <&tegra_car TEGRA30_CLK_PLL_C>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_c_dvfs_opp_table>; + }; + + pll-e { + compatible = "nvidia,tegra30-plle"; + clocks = <&tegra_car TEGRA30_CLK_PLL_E>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_e_dvfs_opp_table>; + }; + + pll-m { + compatible = "nvidia,tegra30-pllm"; + clocks = <&tegra_car TEGRA30_CLK_PLL_M>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_m_dvfs_opp_table>; + }; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; + }; + + flow-controller@60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA30_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + ahb: ahb@6000c000 { + compatible = "nvidia,tegra30-ahb"; + reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ + }; + + actmon: actmon@6000c800 { + compatible = "nvidia,tegra30-actmon"; + reg = <0x6000c800 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_ACTMON>, + <&tegra_car TEGRA30_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car TEGRA30_CLK_ACTMON>; + reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA30_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinmux 0 0 248>; + }; + + vde@6001a000 { + compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA30_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; + }; + + apbmisc@70000800 { + compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; + + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra30-pinmux"; + reg = <0x70000868 0x0d4>, /* Pad control registers */ + <0x70003000 0x3e4>; /* Mux registers */ + }; + + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the compatible is + * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". + */ + uarta: serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uarte: serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + gmi@70009000 { + compatible = "nvidia,tegra30-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x48000000 0x7ffffff>; + clocks = <&tegra_car TEGRA30_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; + status = "disabled"; + }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA30_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + power-domains = <&pd_core>; + operating-points-v2 = <&pwm_dvfs_opp_table>; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C1>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C2>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C3>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C4>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + resets = <&tegra_car 103>; + reset-names = "i2c"; + clock-names = "div-clk", "fast-clk"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000d000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C5>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra30-slink"; + reg = <0x7000d400 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc1_dvfs_opp_table>; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra30-slink"; + reg = <0x7000d600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc2_dvfs_opp_table>; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra30-slink"; + reg = <0x7000d800 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc3_dvfs_opp_table>; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra30-slink"; + reg = <0x7000da00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc4_dvfs_opp_table>; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra30-slink"; + reg = <0x7000dc00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_SBC5>; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc5_dvfs_opp_table>; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra30-slink"; + reg = <0x7000de00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_SBC6>; + resets = <&tegra_car 106>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc6_dvfs_opp_table>; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_RTC>; + }; + + kbc@7000e200 { + compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; + status = "disabled"; + }; + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra30-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d0: td { + clocks = <&tegra_car TEGRA30_CLK_GR3D>; + resets = <&mc TEGRA30_MC_RESET_3D>, + <&tegra_car TEGRA30_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d1: td2 { + clocks = <&tegra_car TEGRA30_CLK_GR3D2>; + resets = <&mc TEGRA30_MC_RESET_3D2>, + <&tegra_car TEGRA30_CLK_GR3D2>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car TEGRA30_CLK_VI>, + <&tegra_car TEGRA30_CLK_CSI>; + resets = <&mc TEGRA30_MC_RESET_ISP>, + <&mc TEGRA30_MC_RESET_VI>, + <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA30_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; + }; + + mc: memory-controller@7000f000 { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car TEGRA30_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #iommu-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; + + emc: memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_EMC>; + power-domains = <&pd_core>; + + nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra30-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA30_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + power-domains = <&pd_core>; + operating-points-v2 = <&fuse_burn_dvfs_opp_table>; + }; + + tsensor: tsensor@70014000 { + compatible = "nvidia,tegra30-tsensor"; + reg = <0x70014000 0x500>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; + resets = <&tegra_car TEGRA30_CLK_TSENSOR>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; + assigned-clock-rates = <500000>; + + #thermal-sensor-cells = <1>; + }; + + hda@70030000 { + compatible = "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_HDA>, + <&tegra_car TEGRA30_CLK_HDA2HDMI>, + <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; + }; + + ahub@70080000 { + compatible = "nvidia,tegra30-ahub"; + reg = <0x70080000 0x200>, + <0x70080200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, + <&tegra_car TEGRA30_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>; /* spdif */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70080300 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080300 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA30_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70080400 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080400 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA30_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70080500 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080500 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA30_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70080600 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080600 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA30_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70080700 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080700 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA30_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + + mmc@78000000 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + clock-names = "sdhci"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; + status = "disabled"; + }; + + mmc@78000200 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000200 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + clock-names = "sdhci"; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disabled"; + }; + + mmc@78000400 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + clock-names = "sdhci"; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; + status = "disabled"; + }; + + mmc@78000600 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000600 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + clock-names = "sdhci"; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disabled"; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000>, + <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USBD>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <1>; + nvidia,xcvr-lsrslew = <1>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; + status = "disabled"; + }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d004000 0x4000>, + <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB2>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,pmc = <&tegra_pmc 2>; + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB3>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,pmc = <&tegra_pmc 1>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + thermal-zones { + tsensor0-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsensor 0>; + + trips { + level1_trip: dvfs-alert { + /* throttle at 80C until temperature drops to 79.8C */ + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + + level2_trip: cpu-div2-throttle { + /* hardware CPU x2 freq throttle at 85C */ + temperature = <85000>; + hysteresis = <200>; + type = "hot"; + }; + + level3_trip: soc-critical { + /* hardware shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&level1_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + tsensor1-thermal { + status = "disabled"; + + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <0>; /* milliseconds */ + + thermal-sensors = <&tsensor 1>; + + trips { + dvfs-alert { + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/Makefile b/arch/arm/boot/dts/nxp/Makefile new file mode 100644 index 000000000000..db44e7a0a198 --- /dev/null +++ b/arch/arm/boot/dts/nxp/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += imx +subdir-y += lpc +subdir-y += ls +subdir-y += mxs +subdir-y += vf diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile new file mode 100644 index 000000000000..3629e343d322 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -0,0 +1,388 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_IMX1) += \ + imx1-ads.dtb \ + imx1-apf9328.dtb +dtb-$(CONFIG_SOC_IMX25) += \ + imx25-eukrea-mbimxsd25-baseboard.dtb \ + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ + imx25-karo-tx25.dtb \ + imx25-pdk.dtb +dtb-$(CONFIG_SOC_IMX27) += \ + imx27-apf27.dtb \ + imx27-apf27dev.dtb \ + imx27-eukrea-mbimxsd27-baseboard.dtb \ + imx27-pdk.dtb \ + imx27-phytec-phycore-rdk.dtb \ + imx27-phytec-phycard-s-rdk.dtb +dtb-$(CONFIG_SOC_IMX31) += \ + imx31-bug.dtb \ + imx31-lite.dtb +dtb-$(CONFIG_SOC_IMX35) += \ + imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx35-pdk.dtb +dtb-$(CONFIG_SOC_IMX50) += \ + imx50-evk.dtb \ + imx50-kobo-aura.dtb +dtb-$(CONFIG_SOC_IMX51) += \ + imx51-apf51.dtb \ + imx51-apf51dev.dtb \ + imx51-babbage.dtb \ + imx51-digi-connectcore-jsk.dtb \ + imx51-eukrea-mbimxsd51-baseboard.dtb \ + imx51-ts4800.dtb \ + imx51-zii-rdu1.dtb \ + imx51-zii-scu2-mezz.dtb \ + imx51-zii-scu3-esb.dtb +dtb-$(CONFIG_SOC_IMX53) += \ + imx53-ard.dtb \ + imx53-cx9020.dtb \ + imx53-kp-ddc.dtb \ + imx53-kp-hsc.dtb \ + imx53-m53evk.dtb \ + imx53-m53menlo.dtb \ + imx53-mba53.dtb \ + imx53-ppd.dtb \ + imx53-qsb.dtb \ + imx53-qsrb.dtb \ + imx53-sk-imx53.dtb \ + imx53-smd.dtb \ + imx53-tx53-x03x.dtb \ + imx53-tx53-x13x.dtb \ + imx53-usbarmory.dtb \ + imx53-voipac-bsb.dtb +dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-alti6p.dtb \ + imx6dl-apf6dev.dtb \ + imx6dl-aristainetos_4.dtb \ + imx6dl-aristainetos_7.dtb \ + imx6dl-aristainetos2_4.dtb \ + imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ + imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ + imx6dl-cubox-i.dtb \ + imx6dl-cubox-i-emmc-som-v15.dtb \ + imx6dl-cubox-i-som-v15.dtb \ + imx6dl-dfi-fs700-m60.dtb \ + imx6dl-dhcom-picoitx.dtb \ + imx6dl-eckelmann-ci4x10.dtb \ + imx6dl-emcon-avari.dtb \ + imx6dl-gw51xx.dtb \ + imx6dl-gw52xx.dtb \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ + imx6dl-gw551x.dtb \ + imx6dl-gw552x.dtb \ + imx6dl-gw553x.dtb \ + imx6dl-gw560x.dtb \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ + imx6dl-gw5912.dtb \ + imx6dl-gw5913.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ + imx6dl-hummingboard2.dtb \ + imx6dl-hummingboard2-emmc-som-v15.dtb \ + imx6dl-hummingboard2-som-v15.dtb \ + imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ + imx6dl-icore-rqs.dtb \ + imx6dl-lanmcu.dtb \ + imx6dl-mamoj.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ + imx6dl-nit6xlite.dtb \ + imx6dl-nitrogen6x.dtb \ + imx6dl-phytec-mira-rdk-nand.dtb \ + imx6dl-phytec-pbab01.dtb \ + imx6dl-pico-dwarf.dtb \ + imx6dl-pico-hobbit.dtb \ + imx6dl-pico-nymph.dtb \ + imx6dl-pico-pi.dtb \ + imx6dl-plybas.dtb \ + imx6dl-plym2m.dtb \ + imx6dl-prtmvt.dtb \ + imx6dl-prtrvt.dtb \ + imx6dl-prtvt7.dtb \ + imx6dl-rex-basic.dtb \ + imx6dl-riotboard.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabrelite.dtb \ + imx6dl-sabresd.dtb \ + imx6dl-savageboard.dtb \ + imx6dl-skov-revc-lt2.dtb \ + imx6dl-skov-revc-lt6.dtb \ + imx6dl-solidsense.dtb \ + imx6dl-ts4900.dtb \ + imx6dl-ts7970.dtb \ + imx6dl-tx6dl-comtft.dtb \ + imx6dl-tx6s-8034.dtb \ + imx6dl-tx6s-8034-mb7.dtb \ + imx6dl-tx6s-8035.dtb \ + imx6dl-tx6s-8035-mb7.dtb \ + imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-80xx-mb7.dtb \ + imx6dl-tx6u-8033.dtb \ + imx6dl-tx6u-8033-mb7.dtb \ + imx6dl-tx6u-811x.dtb \ + imx6dl-tx6u-81xx-mb7.dtb \ + imx6dl-udoo.dtb \ + imx6dl-victgo.dtb \ + imx6dl-vicut1.dtb \ + imx6dl-wandboard.dtb \ + imx6dl-wandboard-revb1.dtb \ + imx6dl-wandboard-revd1.dtb \ + imx6dl-yapp4-draco.dtb \ + imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-lynx.dtb \ + imx6dl-yapp4-orion.dtb \ + imx6dl-yapp4-phoenix.dtb \ + imx6dl-yapp4-ursa.dtb \ + imx6q-apalis-eval.dtb \ + imx6q-apalis-ixora.dtb \ + imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apalis-ixora-v1.2.dtb \ + imx6q-apf6dev.dtb \ + imx6q-arm2.dtb \ + imx6q-b450v3.dtb \ + imx6q-b650v3.dtb \ + imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ + imx6q-cm-fx6.dtb \ + imx6q-cubox-i.dtb \ + imx6q-cubox-i-emmc-som-v15.dtb \ + imx6q-cubox-i-som-v15.dtb \ + imx6q-dfi-fs700-m60.dtb \ + imx6q-dhcom-pdk2.dtb \ + imx6q-display5-tianma-tm070-1280x768.dtb \ + imx6q-dmo-edmqmx6.dtb \ + imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ + imx6q-emcon-avari.dtb \ + imx6q-evi.dtb \ + imx6dl-b105pv2.dtb \ + imx6dl-b105v2.dtb \ + imx6dl-b125v2.dtb \ + imx6dl-b125pv2.dtb \ + imx6dl-b155v2.dtb \ + imx6q-gk802.dtb \ + imx6q-gw51xx.dtb \ + imx6q-gw52xx.dtb \ + imx6q-gw53xx.dtb \ + imx6q-gw5400-a.dtb \ + imx6q-gw54xx.dtb \ + imx6q-gw551x.dtb \ + imx6q-gw552x.dtb \ + imx6q-gw553x.dtb \ + imx6q-gw560x.dtb \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ + imx6q-gw5912.dtb \ + imx6q-gw5913.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ + imx6q-hummingboard-som-v15.dtb \ + imx6q-hummingboard2.dtb \ + imx6q-hummingboard2-emmc-som-v15.dtb \ + imx6q-hummingboard2-som-v15.dtb \ + imx6q-icore.dtb \ + imx6q-icore-mipi.dtb \ + imx6q-icore-ofcap10.dtb \ + imx6q-icore-ofcap12.dtb \ + imx6q-icore-rqs.dtb \ + imx6q-kp-tpc.dtb \ + imx6q-logicpd.dtb \ + imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ + imx6q-mccmon6.dtb \ + imx6q-nitrogen6x.dtb \ + imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_som2.dtb \ + imx6q-novena.dtb \ + imx6q-phytec-mira-rdk-emmc.dtb \ + imx6q-phytec-mira-rdk-nand.dtb \ + imx6q-phytec-pbab01.dtb \ + imx6q-pico-dwarf.dtb \ + imx6q-pico-hobbit.dtb \ + imx6q-pico-nymph.dtb \ + imx6q-pico-pi.dtb \ + imx6q-pistachio.dtb \ + imx6q-prti6q.dtb \ + imx6q-prtwd2.dtb \ + imx6q-rex-pro.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb \ + imx6q-savageboard.dtb \ + imx6q-sbc6x.dtb \ + imx6q-skov-revc-lt2.dtb \ + imx6q-skov-revc-lt6.dtb \ + imx6q-skov-reve-mi1010ait-1cp1.dtb \ + imx6q-solidsense.dtb \ + imx6q-tbs2910.dtb \ + imx6q-ts4900.dtb \ + imx6q-ts7970.dtb \ + imx6q-tx6q-1010.dtb \ + imx6q-tx6q-1010-comtft.dtb \ + imx6q-tx6q-1020.dtb \ + imx6q-tx6q-1020-comtft.dtb \ + imx6q-tx6q-1036.dtb \ + imx6q-tx6q-1036-mb7.dtb \ + imx6q-tx6q-10x0-mb7.dtb \ + imx6q-tx6q-1110.dtb \ + imx6q-tx6q-11x0-mb7.dtb \ + imx6q-udoo.dtb \ + imx6q-utilite-pro.dtb \ + imx6q-var-dt6customboard.dtb \ + imx6q-vicut1.dtb \ + imx6q-wandboard.dtb \ + imx6q-wandboard-revb1.dtb \ + imx6q-wandboard-revd1.dtb \ + imx6q-yapp4-crux.dtb \ + imx6q-yapp4-pegasus.dtb \ + imx6q-zii-rdu2.dtb \ + imx6qp-mba6b.dtb \ + imx6qp-nitrogen6_max.dtb \ + imx6qp-nitrogen6_som2.dtb \ + imx6qp-phytec-mira-rdk-nand.dtb \ + imx6qp-prtwd3.dtb \ + imx6qp-sabreauto.dtb \ + imx6qp-sabresd.dtb \ + imx6qp-tx6qp-8037.dtb \ + imx6qp-tx6qp-8037-mb7.dtb \ + imx6qp-tx6qp-8137.dtb \ + imx6qp-tx6qp-8137-mb7.dtb \ + imx6qp-vicutp.dtb \ + imx6qp-wandboard-revd1.dtb \ + imx6qp-yapp4-crux-plus.dtb \ + imx6qp-yapp4-pegasus-plus.dtb \ + imx6qp-zii-rdu2.dtb \ + imx6s-dhcom-drc02.dtb +dtb-$(CONFIG_SOC_IMX6SL) += \ + imx6sl-evk.dtb \ + imx6sl-kobo-aura2.dtb \ + imx6sl-tolino-shine2hd.dtb \ + imx6sl-tolino-shine3.dtb \ + imx6sl-tolino-vision.dtb \ + imx6sl-tolino-vision5.dtb \ + imx6sl-warp.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-evk.dtb \ + imx6sll-kobo-clarahd.dtb \ + imx6sll-kobo-librah2o.dtb +dtb-$(CONFIG_SOC_IMX6SX) += \ + imx6sx-nitrogen6sx.dtb \ + imx6sx-sabreauto.dtb \ + imx6sx-sdb-reva.dtb \ + imx6sx-sdb-sai.dtb \ + imx6sx-sdb.dtb \ + imx6sx-sdb-mqs.dtb \ + imx6sx-softing-vining-2000.dtb \ + imx6sx-udoo-neo-basic.dtb \ + imx6sx-udoo-neo-extended.dtb \ + imx6sx-udoo-neo-full.dtb +dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk.dtb \ + imx6ul-ccimx6ulsbcexpress.dtb \ + imx6ul-ccimx6ulsbcpro.dtb \ + imx6ul-geam.dtb \ + imx6ul-isiot-emmc.dtb \ + imx6ul-isiot-nand.dtb \ + imx6ul-kontron-bl.dtb \ + imx6ul-kontron-bl-43.dtb \ + imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ + imx6ul-opos6uldev.dtb \ + imx6ul-pico-dwarf.dtb \ + imx6ul-pico-hobbit.dtb \ + imx6ul-pico-pi.dtb \ + imx6ul-phytec-segin-ff-rdk-emmc.dtb \ + imx6ul-phytec-segin-ff-rdk-nand.dtb \ + imx6ul-prti6g.dtb \ + imx6ul-tx6ul-0010.dtb \ + imx6ul-tx6ul-0011.dtb \ + imx6ul-tx6ul-mainboard.dtb \ + imx6ull-14x14-evk.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-emmc-aster.dtb \ + imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-emmc-iris.dtb \ + imx6ull-colibri-emmc-iris-v2.dtb \ + imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-wifi-aster.dtb \ + imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ + imx6ull-dhcom-drc02.dtb \ + imx6ull-dhcom-pdk2.dtb \ + imx6ull-dhcom-picoitx.dtb \ + imx6ull-dhcor-maveo-box.dtb \ + imx6ull-jozacp.dtb \ + imx6ull-kontron-bl.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-opos6uldev.dtb \ + imx6ull-phytec-segin-ff-rdk-nand.dtb \ + imx6ull-phytec-segin-ff-rdk-emmc.dtb \ + imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ + imx6ull-tarragon-master.dtb \ + imx6ull-tarragon-micro.dtb \ + imx6ull-tarragon-slave.dtb \ + imx6ull-tarragon-slavext.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ + imx6ulz-14x14-evk.dtb \ + imx6ulz-bsh-smm-m2.dtb +dtb-$(CONFIG_SOC_IMX7D) += \ + imx7d-cl-som-imx7.dtb \ + imx7d-colibri-aster.dtb \ + imx7d-colibri-emmc-aster.dtb \ + imx7d-colibri-emmc-iris.dtb \ + imx7d-colibri-emmc-iris-v2.dtb \ + imx7d-colibri-emmc-eval-v3.dtb \ + imx7d-colibri-eval-v3.dtb \ + imx7d-colibri-iris.dtb \ + imx7d-colibri-iris-v2.dtb \ + imx7d-flex-concentrator.dtb \ + imx7d-flex-concentrator-mfg.dtb \ + imx7d-mba7.dtb \ + imx7d-meerkat96.dtb \ + imx7d-nitrogen7.dtb \ + imx7d-pico-dwarf.dtb \ + imx7d-pico-hobbit.dtb \ + imx7d-pico-nymph.dtb \ + imx7d-pico-pi.dtb \ + imx7d-remarkable2.dtb \ + imx7d-sbc-imx7.dtb \ + imx7d-sdb.dtb \ + imx7d-sdb-reva.dtb \ + imx7d-sdb-sht11.dtb \ + imx7d-smegw01.dtb \ + imx7d-zii-rmu2.dtb \ + imx7d-zii-rpu2.dtb \ + imx7s-colibri-aster.dtb \ + imx7s-colibri-eval-v3.dtb \ + imx7s-colibri-iris.dtb \ + imx7s-colibri-iris-v2.dtb \ + imx7s-mba7.dtb \ + imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-com.dtb \ + imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb diff --git a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi new file mode 100644 index 000000000000..dd03e3860f97 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + * and + * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd + * + * Netronix E60K02 board common. + * This board is equipped with different SoCs and + * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and + * the Tolino Shine 3 (with i.MX6SL) + */ +#include + +/ { + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-cover { + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led { + label = "e60k02:white:on"; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + lm3630a: backlight@36 { + reg = <0x36>; + compatible = "ti,lm3630a"; + enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0>; + label = "backlight_warm"; + default-brightness = <0>; + max-brightness = <255>; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + label = "backlight_cold"; + default-brightness = <0>; + max-brightness = <255>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cyttsp5_gpio>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + vdd-supply = <&ldo5_reg>; + }; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3300000>; + regulator-suspend-min-microvolt = <3300000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + /* IR_3V3 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-always-on; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-boot-on; + }; + }; + }; +}; + +&snvs_rtc { + /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ + status = "disabled"; +}; + +&uart1 { + /* J4, through-hole */ + status = "okay"; +}; + +&uart4 { + /* TP198, next to J4, SMD pads */ + status = "okay"; +}; + +&usdhc2 { + non-removable; + status = "okay"; +}; + +&usdhc3 { + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi new file mode 100644 index 000000000000..4e1bf080eaca --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + * and + * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd + * + * Netronix E70K02 board common. + * This board is equipped with different SoCs and + * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and + * the Tolino Shine 3 (with i.MX6SL) + */ +#include + +/ { + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-cover { + label = "Cover"; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + key-pageup { + label = "PageUp"; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-pagedown { + label = "PageDown"; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led { + label = "e70k02:white:on"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + lm3630a: backlight@36 { + reg = <0x36>; + compatible = "ti,lm3630a"; + enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0>; + label = "backlight_warm"; + default-brightness = <0>; + max-brightness = <255>; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + label = "backlight_cold"; + default-brightness = <0>; + max-brightness = <255>; + }; + }; + + /* TODO: KX122 acceleration sensor a 0x1e */ + +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cyttsp5_gpio>; + interrupt-parent = <&gpio4>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + vdd-supply = <&ldo5_reg>; + }; + + /* TODO: SY7636 PMIC for E Ink at 0x62 */ + +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + reg = <0x32>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3300000>; + regulator-suspend-min-microvolt = <3300000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-boot-on; + }; + }; + }; +}; + +&snvs_rtc { + /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ + status = "disabled"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + non-removable; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts new file mode 100644 index 000000000000..5833fb6f15d8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +/dts-v1/; +#include "imx1.dtsi" + +/ { + model = "Freescale MX1 ADS"; + compatible = "fsl,imx1ads", "fsl,imx1"; + + chosen { + stdout-path = &uart1; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x04000000>; + }; +}; + +&cspi1 { + pinctrl-0 = <&pinctrl_cspi1>; + cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c>; + status = "okay"; + + extgpio0: pcf8575@22 { + compatible = "nxp,pcf8575"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + extgpio1: pcf8575@24 { + compatible = "nxp,pcf8575"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <4>; + fsl,weim-cs-timing = <0x00003e00 0x00000801>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&iomuxc { + imx1-ads { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 + MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 + MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 + MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 + MX1_PAD_SPI1_SS__GPIO3_15 0x0 + >; + }; + + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts new file mode 100644 index 000000000000..77b21aa7a146 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +/dts-v1/; +#include "imx1.dtsi" + +/ { + model = "Armadeus APF9328"; + compatible = "armadeus,imx1-apf9328", "fsl,imx1"; + + chosen { + stdout-path = &uart1; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x00800000>; + }; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00330e04 0x00000d01>; + #address-cells = <1>; + #size-cells = <1>; + }; + + eth: eth@4,c00000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth>; + compatible = "davicom,dm9000"; + reg = < + 4 0x00c00000 0x2 + 4 0x00c00002 0x2 + >; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + fsl,weim-cs-timing = <0x0000c700 0x19190d01>; + }; +}; + +&iomuxc { + imx1-apf9328 { + pinctrl_eth: ethgrp { + fsl,pins = < + MX1_PAD_SIM_SVEN__GPIO2_14 0x0 + >; + }; + + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h new file mode 100644 index 000000000000..bd2e679cb26c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +#ifndef __DTS_IMX1_PINFUNC_H +#define __DTS_IMX1_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + * mux_id consists of + * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) + * + * function: 0 - Primary function + * 1 - Alternate function + * 2 - GPIO + * direction: 0 - Input + * 1 - Output + * gpio_oconf: 0 - A_IN + * 1 - B_IN + * 2 - A_OUT + * 3 - Data Register + * gpio_iconfa/b: 0 - GPIO_IN + * 1 - Interrupt Status Register + * 2 - 0 + * 3 - 1 + * + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). + */ + +#define MX1_PAD_A24__A24 0x00 0x004 +#define MX1_PAD_A24__GPIO1_0 0x00 0x032 +#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 +#define MX1_PAD_TIN__TIN 0x01 0x000 +#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 +#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 +#define MX1_PAD_PWMO__PWMO 0x02 0x004 +#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 +#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 +#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 +#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 +#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 +#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 +#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 +#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 +#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 +#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 +#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 +#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 +#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 +#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 +#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 +#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 +#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 +#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 +#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 +#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 +#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 +#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 +#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 +#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 +#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 +#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 +#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 +#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 +#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 +#define MX1_PAD_DTACK__DTACK 0x11 0x000 +#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 +#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 +#define MX1_PAD_DTACK__A25 0x11 0x016 +#define MX1_PAD_BCLK__BCLK 0x12 0x004 +#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 +#define MX1_PAD_LBA__LBA 0x13 0x004 +#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 +#define MX1_PAD_ECB__ECB 0x14 0x000 +#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 +#define MX1_PAD_A0__A0 0x15 0x004 +#define MX1_PAD_A0__GPIO1_21 0x15 0x032 +#define MX1_PAD_CS4__CS4 0x16 0x004 +#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 +#define MX1_PAD_CS5__CS5 0x17 0x004 +#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 +#define MX1_PAD_A16__A16 0x18 0x004 +#define MX1_PAD_A16__GPIO1_24 0x18 0x032 +#define MX1_PAD_A17__A17 0x19 0x004 +#define MX1_PAD_A17__GPIO1_25 0x19 0x032 +#define MX1_PAD_A18__A18 0x1a 0x004 +#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 +#define MX1_PAD_A19__A19 0x1b 0x004 +#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 +#define MX1_PAD_A20__A20 0x1c 0x004 +#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 +#define MX1_PAD_A21__A21 0x1d 0x004 +#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 +#define MX1_PAD_A22__A22 0x1e 0x004 +#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 +#define MX1_PAD_A23__A23 0x1f 0x004 +#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 +#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 +#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 +#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 +#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 +#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 +#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 +#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 +#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 +#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 +#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 +#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 +#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 +#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 +#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 +#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 +#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 +#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 +#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 +#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 +#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 +#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 +#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 +#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 +#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 +#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 +#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 +#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 +#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 +#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 +#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 +#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 +#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 +#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 +#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 +#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 +#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 +#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 +#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 +#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 +#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 +#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 +#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 +#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 +#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 +#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 +#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 +#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 +#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 +#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 +#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 +#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 +#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 +#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 +#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 +#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 +#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 +#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 +#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 +#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 +#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 +#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 +#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 +#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 +#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 +#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 +#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 +#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 +#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 +#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 +#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 +#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 +#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 +#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 +#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 +#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 +#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 +#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 +#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 +#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 +#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 +#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 +#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 +#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 +#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 +#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 +#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 +#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 +#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 +#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 +#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 +#define MX1_PAD_BT13__BT13 0x53 0x004 +#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 +#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 +#define MX1_PAD_BT12__BT12 0x54 0x004 +#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 +#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 +#define MX1_PAD_BT11__BT11 0x55 0x004 +#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 +#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 +#define MX1_PAD_BT10__BT10 0x56 0x004 +#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 +#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 +#define MX1_PAD_BT9__BT9 0x57 0x004 +#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 +#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 +#define MX1_PAD_BT8__BT8 0x58 0x004 +#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 +#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 +#define MX1_PAD_BT8__UART3_RI 0x58 0x016 +#define MX1_PAD_BT7__BT7 0x59 0x004 +#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 +#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 +#define MX1_PAD_BT6__BT6 0x5a 0x004 +#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 +#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 +#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 +#define MX1_PAD_BT5__BT5 0x5b 0x000 +#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 +#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 +#define MX1_PAD_BT4__BT4 0x5c 0x000 +#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 +#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 +#define MX1_PAD_BT3__BT3 0x5d 0x000 +#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 +#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 +#define MX1_PAD_BT2__BT2 0x5e 0x004 +#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 +#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 +#define MX1_PAD_BT1__BT1 0x5f 0x000 +#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 +#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 +#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 +#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 +#define MX1_PAD_REV__REV 0x67 0x004 +#define MX1_PAD_REV__UART2_DTR 0x67 0x001 +#define MX1_PAD_REV__GPIO4_7 0x67 0x032 +#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 +#define MX1_PAD_CLS__CLS 0x68 0x004 +#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 +#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 +#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 +#define MX1_PAD_PS__PS 0x69 0x004 +#define MX1_PAD_PS__UART2_RI 0x69 0x005 +#define MX1_PAD_PS__GPIO4_9 0x69 0x032 +#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 +#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 +#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 +#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 +#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 +#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 +#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 +#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 +#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 +#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 +#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 +#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 +#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 +#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 +#define MX1_PAD_LD0__LD0 0x6f 0x004 +#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 +#define MX1_PAD_LD1__LD1 0x70 0x004 +#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 +#define MX1_PAD_LD2__LD2 0x71 0x004 +#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 +#define MX1_PAD_LD3__LD3 0x72 0x004 +#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 +#define MX1_PAD_LD4__LD4 0x73 0x004 +#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 +#define MX1_PAD_LD5__LD5 0x74 0x004 +#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 +#define MX1_PAD_LD6__LD6 0x75 0x004 +#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 +#define MX1_PAD_LD7__LD7 0x76 0x004 +#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 +#define MX1_PAD_LD8__LD8 0x77 0x004 +#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 +#define MX1_PAD_LD9__LD9 0x78 0x004 +#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 +#define MX1_PAD_LD10__LD10 0x79 0x004 +#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 +#define MX1_PAD_LD11__LD11 0x7a 0x004 +#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 +#define MX1_PAD_LD12__LD12 0x7b 0x004 +#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 +#define MX1_PAD_LD13__LD13 0x7c 0x004 +#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 +#define MX1_PAD_LD14__LD14 0x7d 0x004 +#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 +#define MX1_PAD_LD15__LD15 0x7e 0x004 +#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 +#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 +#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 +#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 + +#endif diff --git a/arch/arm/boot/dts/nxp/imx/imx1.dtsi b/arch/arm/boot/dts/nxp/imx/imx1.dtsi new file mode 100644 index 000000000000..e312f1e74e2f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx1.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2014 Alexander Shiyan + +#include "imx1-pinfunc.h" + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &i2c; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &cspi1; + spi1 = &cspi2; + }; + + aitc: aitc-interrupt-controller@223000 { + compatible = "fsl,imx1-aitc", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x00223000 0x1000>; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "arm,arm920t"; + operating-points = <200000 1900000>; + clock-latency = <62500>; + clocks = <&clks IMX1_CLK_MCU>; + voltage-tolerance = <5>; + }; + }; + + clocks { + clk32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&aitc>; + ranges; + + aipi@200000 { + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00200000 0x10000>; + ranges; + + gpt1: timer@202000 { + compatible = "fsl,imx1-gpt"; + reg = <0x00202000 0x1000>; + interrupts = <59>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@203000 { + compatible = "fsl,imx1-gpt"; + reg = <0x00203000 0x1000>; + interrupts = <58>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + fb: fb@205000 { + compatible = "fsl,imx1-fb"; + reg = <0x00205000 0x1000>; + interrupts = <14>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER2>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + uart1: serial@206000 { + compatible = "fsl,imx1-uart"; + reg = <0x00206000 0x1000>; + interrupts = <30 29 26>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@207000 { + compatible = "fsl,imx1-uart"; + reg = <0x00207000 0x1000>; + interrupts = <24 23 20>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm: pwm@208000 { + #pwm-cells = <3>; + compatible = "fsl,imx1-pwm"; + reg = <0x00208000 0x1000>; + interrupts = <34>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + dma: dma@209000 { + compatible = "fsl,imx1-dma"; + reg = <0x00209000 0x1000>; + interrupts = <61 60>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_DMA_GATE>; + clock-names = "ipg", "ahb"; + #dma-cells = <1>; + }; + + uart3: serial@20a000 { + compatible = "fsl,imx1-uart"; + reg = <0x0020a000 0x1000>; + interrupts = <54 4 1>; + clocks = <&clks IMX1_CLK_UART3_GATE>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + aipi@210000 { + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00210000 0x10000>; + ranges; + + cspi1: spi@213000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-cspi"; + reg = <0x00213000 0x1000>; + interrupts = <41>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c: i2c@217000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-i2c"; + reg = <0x00217000 0x1000>; + interrupts = <39>; + clocks = <&clks IMX1_CLK_HCLK>; + status = "disabled"; + }; + + cspi2: spi@219000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-cspi"; + reg = <0x00219000 0x1000>; + interrupts = <40>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + clks: ccm@21b000 { + compatible = "fsl,imx1-ccm"; + reg = <0x0021b000 0x1000>; + #clock-cells = <1>; + }; + + iomuxc: iomuxc@21c000 { + compatible = "fsl,imx1-iomuxc"; + reg = <0x0021c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@21c000 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c000 0x100>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@21c100 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c100 0x100>; + interrupts = <12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@21c200 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c200 0x100>; + interrupts = <13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@21c300 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c300 0x100>; + interrupts = <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + + weim: weim@220000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx1-weim"; + reg = <0x00220000 0x1000>; + clocks = <&clks IMX1_CLK_DUMMY>; + ranges = < + 0 0 0x10000000 0x02000000 + 1 0 0x12000000 0x01000000 + 2 0 0x13000000 0x01000000 + 3 0 0x14000000 0x01000000 + 4 0 0x15000000 0x01000000 + 5 0 0x16000000 0x01000000 + >; + status = "disabled"; + }; + + esram: esram@300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x20000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi new file mode 100644 index 000000000000..0703f62d10d1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +#include "imx25.dtsi" + +/ { + model = "Eukrea CPUIMX25"; + compatible = "eukrea,cpuimx25", "fsl,imx25"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; /* 64M */ + }; +}; + +&fec { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + imx25-eukrea-cpuimx25 { + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts new file mode 100644 index 000000000000..7d4301b22b90 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +#include "imx25-eukrea-mbimxsd25-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; + compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + cmo_qvga: display { + model = "CMO-QVGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xcad08b80>; + bus-width = <18>; + display-timings { + native-mode = <&qvga_timings>; + qvga_timings: 320x240 { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <30>; + hfront-porch = <38>; + vback-porch = <20>; + vfront-porch = <3>; + hsync-len = <15>; + vsync-len = <4>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_lcd_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { + fsl,pins = ; + }; + }; +}; + +&lcdc { + display = <&cmo_qvga>; + fsl,lpccr = <0x00a903ff>; + lcd-supply = <®_lcd_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts new file mode 100644 index 000000000000..80a7f96de4c6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +#include "imx25-eukrea-mbimxsd25-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; + compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + dvi_svga: display { + model = "DVI-SVGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xfa208b80>; + bus-width = <18>; + display-timings { + native-mode = <&dvi_svga_timings>; + dvi_svga_timings: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <75>; + hfront-porch = <75>; + vback-porch = <7>; + vfront-porch = <75>; + hsync-len = <7>; + vsync-len = <7>; + }; + }; + }; +}; + +&lcdc { + display = <&dvi_svga>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts new file mode 100644 index 000000000000..24027a1fb46d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +#include "imx25-eukrea-mbimxsd25-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; + compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + dvi_vga: display { + model = "DVI-VGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xfa208b80>; + bus-width = <18>; + display-timings { + native-mode = <&dvi_vga_timings>; + dvi_vga_timings: 640x480 { + clock-frequency = <31250000>; + hactive = <640>; + vactive = <480>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <7>; + vfront-porch = <100>; + hsync-len = <7>; + vsync-len = <7>; + }; + }; + }; +}; + +&lcdc { + display = <&dvi_vga>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts new file mode 100644 index 000000000000..c7207ea437c4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +/dts-v1/; + +#include +#include +#include "imx25-eukrea-cpuimx25.dtsi" + +/ { + model = "Eukrea MBIMXSD25"; + compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + button { + label = "BP1"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx25-eukrea-tlv320aic23"; + ssi-controller = <&ssi1>; + fsl,mux-int-port = <1>; + fsl,mux-ext-port = <5>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&iomuxc { + imx25-eukrea-mbimxsd25-baseboard { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 + MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 + MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 + MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = ; + }; + + pinctrl_lcdc: lcdcgrp { + fsl,pins = < + MX25_PAD_LD0__LD0 0x1 + MX25_PAD_LD1__LD1 0x1 + MX25_PAD_LD2__LD2 0x1 + MX25_PAD_LD3__LD3 0x1 + MX25_PAD_LD4__LD4 0x1 + MX25_PAD_LD5__LD5 0x1 + MX25_PAD_LD6__LD6 0x1 + MX25_PAD_LD7__LD7 0x1 + MX25_PAD_LD8__LD8 0x1 + MX25_PAD_LD9__LD9 0x1 + MX25_PAD_LD10__LD10 0x1 + MX25_PAD_LD11__LD11 0x1 + MX25_PAD_LD12__LD12 0x1 + MX25_PAD_LD13__LD13 0x1 + MX25_PAD_LD14__LD14 0x1 + MX25_PAD_LD15__LD15 0x1 + MX25_PAD_GPIO_E__LD16 0x1 + MX25_PAD_GPIO_F__LD17 0x1 + MX25_PAD_HSYNC__HSYNC 0x80000000 + MX25_PAD_VSYNC__VSYNC 0x80000000 + MX25_PAD_LSCLK__LSCLK 0x80000000 + MX25_PAD_OE_ACD__OE_ACD 0x80000000 + MX25_PAD_CONTRAST__CONTRAST 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 + MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 + MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 + MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 + >; + }; + }; +}; + +&ssi1 { + codec-handle = <&tlv320aic23>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbhost1 { + status = "okay"; +}; + +&usbotg { + external-vbus-divider; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts b/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts new file mode 100644 index 000000000000..0950eb66d3d9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Pengutronix + */ + +/dts-v1/; +#include "imx25.dtsi" + +/ { + model = "Ka-Ro TX25"; + compatible = "karo,imx25-tx25", "fsl,imx25"; + + chosen { + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_phy: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 0>; + enable-active-high; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x02000000 0x90000000 0x02000000>; + }; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 + MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 + MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ + MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX25_PAD_NF_CE0__NF_CE0 0x80000000 + MX25_PAD_NFWE_B__NFWE_B 0x80000000 + MX25_PAD_NFRE_B__NFRE_B 0x80000000 + MX25_PAD_NFALE__NFALE 0x80000000 + MX25_PAD_NFCLE__NFCLE 0x80000000 + MX25_PAD_NFWP_B__NFWP_B 0x80000000 + MX25_PAD_NFRB__NFRB 0x80000000 + MX25_PAD_D7__D7 0x80000000 + MX25_PAD_D6__D6 0x80000000 + MX25_PAD_D5__D5 0x80000000 + MX25_PAD_D4__D4 0x80000000 + MX25_PAD_D3__D3 0x80000000 + MX25_PAD_D2__D2 0x80000000 + MX25_PAD_D1__D1 0x80000000 + MX25_PAD_D0__D0 0x80000000 + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + phy-mode = "rmii"; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts new file mode 100644 index 000000000000..fb66884d8a2f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013 Freescale Semiconductor, Inc. + +/dts-v1/; +#include +#include +#include "imx25.dtsi" + +/ { + model = "Freescale i.MX25 Product Development Kit"; + compatible = "fsl,imx25-pdk", "fsl,imx25"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 3 0>; + enable-active-high; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_3v3: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 6 0>; + }; + }; + + sound { + compatible = "fsl,imx25-pdk-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx25-pdk-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + + wvga: display { + model = "CLAA057VC01CW"; + bits-per-pixel = <16>; + fsl,pcr = <0xfa208b80>; + bus-width = <18>; + display-timings { + native-mode = <&wvga_timings>; + wvga_timings: 640x480 { + hactive = <640>; + vactive = <480>; + hback-porch = <45>; + hfront-porch = <114>; + hsync-len = <1>; + vback-porch = <33>; + vfront-porch = <11>; + vsync-len = <1>; + clock-frequency = <25200000>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 129>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + imx25-pdk { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_RW__AUD4_TXFS 0xe0 + MX25_PAD_OE__AUD4_TXC 0xe0 + MX25_PAD_EB0__AUD4_TXD 0xe0 + MX25_PAD_EB1__AUD4_RXD 0xe0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX25_PAD_GPIO_A__CAN1_TX 0x0 + MX25_PAD_GPIO_B__CAN1_RX 0x0 + MX25_PAD_D14__GPIO_4_6 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + MX25_PAD_A14__GPIO_2_0 0x80000000 + MX25_PAD_A15__GPIO_2_1 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + MX25_PAD_A17__GPIO_2_3 0x80000000 + MX25_PAD_D12__GPIO_4_8 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 + MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 + MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 + MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 + MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 + MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 + MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 + MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX25_PAD_LD0__LD0 0xe0 + MX25_PAD_LD1__LD1 0xe0 + MX25_PAD_LD2__LD2 0xe0 + MX25_PAD_LD3__LD3 0xe0 + MX25_PAD_LD4__LD4 0xe0 + MX25_PAD_LD5__LD5 0xe0 + MX25_PAD_LD6__LD6 0xe0 + MX25_PAD_LD7__LD7 0xe0 + MX25_PAD_LD8__LD8 0xe0 + MX25_PAD_LD9__LD9 0xe0 + MX25_PAD_LD10__LD10 0xe0 + MX25_PAD_LD11__LD11 0xe0 + MX25_PAD_LD12__LD12 0xe0 + MX25_PAD_LD13__LD13 0xe0 + MX25_PAD_LD14__LD14 0xe0 + MX25_PAD_LD15__LD15 0xe0 + MX25_PAD_GPIO_E__LD16 0xe0 + MX25_PAD_GPIO_F__LD17 0xe0 + MX25_PAD_HSYNC__HSYNC 0xe0 + MX25_PAD_VSYNC__VSYNC 0xe0 + MX25_PAD_LSCLK__LSCLK 0xe0 + MX25_PAD_OE_ACD__OE_ACD 0xe0 + MX25_PAD_CONTRAST__CONTRAST 0xe0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; + }; +}; + +&lcdc { + display = <&wvga>; + fsl,lpccr = <0x00a903ff>; + fsl,lscr1 = <0x00120300>; + fsl,dmacr = <0x00020010>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; +}; + +&nfc { + nand-on-flash-bbt; + status = "okay"; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0x0, 0x0, KEY_UP) + MATRIX_KEY(0x0, 0x1, KEY_DOWN) + MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) + MATRIX_KEY(0x0, 0x3, KEY_HOME) + MATRIX_KEY(0x1, 0x0, KEY_RIGHT) + MATRIX_KEY(0x1, 0x1, KEY_LEFT) + MATRIX_KEY(0x1, 0x2, KEY_ENTER) + MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) + MATRIX_KEY(0x2, 0x0, KEY_F6) + MATRIX_KEY(0x2, 0x1, KEY_F8) + MATRIX_KEY(0x2, 0x2, KEY_F9) + MATRIX_KEY(0x2, 0x3, KEY_F10) + MATRIX_KEY(0x3, 0x0, KEY_F1) + MATRIX_KEY(0x3, 0x1, KEY_F2) + MATRIX_KEY(0x3, 0x2, KEY_F3) + MATRIX_KEY(0x3, 0x2, KEY_POWER) + >; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&tsc { + status = "okay"; +}; + +&tscadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&usbhost1 { + status = "okay"; +}; + +&usbotg { + external-vbus-divider; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h new file mode 100644 index 000000000000..908caf810351 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h @@ -0,0 +1,652 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Eukréa Electromatique + * Based on imx35-pinfunc.h in the same directory Which is: + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX25_PINFUNC_H +#define __DTS_IMX25_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 +#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 + +#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 +#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 +#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 + +#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 +#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 +#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 +#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 + +#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 +#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000 +#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000 +#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000 + +#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000 +#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000 +#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000 +#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000 + +#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000 +#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000 +#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000 +#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000 + +#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000 +#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000 +#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000 +#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000 + +#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000 +#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000 +#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000 +#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000 + +#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000 +#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000 +#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000 +#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000 + +#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000 +#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000 +#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000 +#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000 + +#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000 +#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000 +#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000 +#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 + +#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000 +#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000 +#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000 +#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000 + +#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000 +#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000 +#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000 +#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000 + +#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000 +#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000 +#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000 + +#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 +#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 +#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 +#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000 + +#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 +#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 +#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 +#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000 + +#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 +#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 +#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000 + +#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 +#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 + +#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 +#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 +#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 + +#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000 +#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 +#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 +#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 +#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000 + +#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 +#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 +#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 +#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 +#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 + +#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 +#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000 +#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 + +#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 +#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 +#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 +#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000 + +#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 +#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 +#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 +#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000 + +#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 +#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 + +#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000 +#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000 +#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000 + +#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000 + +#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000 + +#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000 + +#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000 + +#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000 + +#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000 +#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000 + +#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 +#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 +#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 +#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 + +#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 +#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 +#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 +#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 + +#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 +#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 +#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 +#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 + +#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 +#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 +#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 + +#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 +#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 +#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000 + +#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 +#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 +#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 + +#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 +#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 +#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 + +#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 +#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 +#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 + +#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 +#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 + +#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 +#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 + +#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 +#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 + +#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 +#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 + +#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 +#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 + +#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 +#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 + +#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 +#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 + +#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 +#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 + +#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000 +#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000 +#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000 + +#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000 +#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000 +#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000 + +#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000 +#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000 + +#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000 +#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000 + +#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000 +#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000 + +#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000 +#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000 + +#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000 +#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000 + +#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000 +#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000 + +#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 +#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 +#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 +/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000 + +#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 +#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 +#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 +#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 + +#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 +#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 +#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 + +#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 +#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 +#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 +#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 + +#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 +#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 +#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000 +#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 + +#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 +#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 +#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000 +#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 + +#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 +#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 +#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000 + +#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000 +#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 +#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001 + +#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000 +#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000 + +#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000 +#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000 + +#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000 +#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000 + +#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000 +#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 +#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 + +#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 +#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000 +#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 +#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 +#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 +#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 + +#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000 +#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000 +#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001 + +#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000 +#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 +#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 +#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 +#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001 + +#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 +#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 +#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 +#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000 +#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001 + +#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 +#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 +#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 +#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 +#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001 + +#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 +#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 +#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 +#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 +#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001 + +#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 +/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 +#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 +#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 +#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001 + +#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 +#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 +#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 +#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001 + +#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 +#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 +#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000 +#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000 + +#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000 +#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000 +#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000 +#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000 + +#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 +#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 +#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 +#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 + +#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 +#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 +#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 +#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 + +#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 +#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 +#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 +#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 + +#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 +#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 +#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 +#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 + +#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 +#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000 + +#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000 +#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000 + +#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000 +#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000 + +#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000 + +#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000 + +#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 +#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 + +#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000 + +#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000 + +#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 +#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 +#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000 + +#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000 +#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000 +#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000 + +#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 +#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 +#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000 +#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 +#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 + +#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000 +#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001 +#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 +#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 + +#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000 +#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000 + +#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000 +#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000 + +#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 +#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 +#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000 +#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 +#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 + +#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 +#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 +#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 +#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001 + +/* + * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD + * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM + * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon + * bug that configuring the ESDHCn_CMD function doesn't enable the input path + * for this pin. + * This might have side effects for other hardware units that are connected to + * that pin and use the respective function as input. + */ +#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000 +#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 +#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 +#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 + +#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000 +#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 +#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 +#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 + +#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 +#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 + +#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001 +#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 +#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 + +#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001 +#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 +#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 + +#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001 +#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 +#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 + +#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 +#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000 + +#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000 +#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000 + +#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000 +#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002 +#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000 + +#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000 +#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002 +#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 + +#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001 +#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000 + +#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000 +#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000 + +#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 +#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 + +#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000 +#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 + +#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 +/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002 +#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 +#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 + +#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000 +#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001 +#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000 + +#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000 +#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000 + +#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000 +#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001 +#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000 + +#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 +#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 +#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000 + +#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 +#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 +#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000 + +#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 +/* + * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, + * 01/2011) this is CAN1_TX but that's wrong. + */ +#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000 +#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000 + +#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000 +/* + * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, + * 01/2011) this is CAN1_RX but that's wrong. + */ +#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000 +#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000 + +#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000 +#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000 + +#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000 +#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000 +#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000 + +#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 + +#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 +#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 + +#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000 +#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 +#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 + +#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000 +#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 +#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 + +#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000 +#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 +#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 +#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 +#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000 +#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 +#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 +#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 + +#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000 +#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 +#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 +#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 + +#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000 +#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 +#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 +#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 +#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 + +#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000 +#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 +#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 +#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 + +#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000 +#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000 + +#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000 +#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000 + +#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 +#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 +#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 +#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 + +#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 +#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001 +#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 + +#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 +#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001 +#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000 +#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000 + +#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000 +#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000 + +#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 +#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 + +#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 +#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 + +/* + * Compatibility defines for out-of-tree users. You should update if you make + * use of one of them. + */ +#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7 +#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6 +#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5 +#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4 +#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD +#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK +#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1 +#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD +#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK +#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0 +#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 +#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 +#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 +#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD +#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK +#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 +#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 +#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 +#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 + +#endif /* __DTS_IMX25_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi new file mode 100644 index 000000000000..5f90d72b840b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Sascha Hauer, Pengutronix + +#include +#include "imx25-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + pwm0 = &pwm1; + pwm1 = &pwm2; + pwm2 = &pwm3; + pwm3 = &pwm4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; + usb0 = &usbotg; + usb1 = &usbhost1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + asic: asic-interrupt-controller@68000000 { + compatible = "fsl,imx25-asic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x68000000 0x8000000>; + }; + + clocks { + osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&asic>; + ranges; + + bus@43f00000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + aips1: bridge@43f00000 { + compatible = "fsl,imx25-aips"; + reg = <0x43f00000 0x4000>; + }; + + i2c1: i2c@43f80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + clocks = <&clks 48>; + clock-names = ""; + interrupts = <3>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + clocks = <&clks 48>; + clock-names = ""; + interrupts = <10>; + status = "disabled"; + }; + + can1: can@43f88000 { + compatible = "fsl,imx25-flexcan"; + reg = <0x43f88000 0x4000>; + interrupts = <43>; + clocks = <&clks 75>, <&clks 75>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: can@43f8c000 { + compatible = "fsl,imx25-flexcan"; + reg = <0x43f8c000 0x4000>; + interrupts = <44>; + clocks = <&clks 76>, <&clks 76>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@43f90000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + clocks = <&clks 120>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + interrupts = <32>; + clocks = <&clks 121>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@43f98000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + clocks = <&clks 48>; + clock-names = ""; + interrupts = <4>; + status = "disabled"; + }; + + owire@43f9c000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x43f9c000 0x4000>; + clocks = <&clks 51>; + clock-names = ""; + interrupts = <2>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; + reg = <0x43fa4000 0x4000>; + clocks = <&clks 78>, <&clks 78>; + clock-names = "ipg", "per"; + interrupts = <14>; + status = "disabled"; + }; + + kpp: kpp@43fa8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; + reg = <0x43fa8000 0x4000>; + clocks = <&clks 102>; + clock-names = ""; + interrupts = <24>; + status = "disabled"; + }; + + iomuxc: iomuxc@43fac000 { + compatible = "fsl,imx25-iomuxc"; + reg = <0x43fac000 0x4000>; + }; + + audmux: audmux@43fb0000 { + compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; + reg = <0x43fb0000 0x4000>; + status = "disabled"; + }; + }; + + spba-bus@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + spi3: spi@50004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; + reg = <0x50004000 0x4000>; + interrupts = <0>; + clocks = <&clks 80>, <&clks 80>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@50008000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x50008000 0x4000>; + interrupts = <5>; + clocks = <&clks 123>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@5000c000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <18>; + clocks = <&clks 122>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + spi2: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; + reg = <0x50010000 0x4000>; + clocks = <&clks 79>, <&clks 79>; + clock-names = "ipg", "per"; + interrupts = <13>; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <11>; + clocks = <&clks 118>; + clock-names = "ipg"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + esai@50018000 { + reg = <0x50018000 0x4000>; + interrupts = <7>; + }; + + uart5: serial@5002c000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x5002c000 0x4000>; + interrupts = <40>; + clocks = <&clks 124>, <&clks 57>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + tscadc: tscadc@50030000 { + compatible = "fsl,imx25-tsadc"; + reg = <0x50030000 0xc>; + interrupts = <46>; + clocks = <&clks 119>; + clock-names = "ipg"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + adc: adc@50030800 { + compatible = "fsl,imx25-gcq"; + reg = <0x50030800 0x60>; + interrupt-parent = <&tscadc>; + interrupts = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tsc: tcq@50030400 { + compatible = "fsl,imx25-tcq"; + reg = <0x50030400 0x60>; + interrupt-parent = <&tscadc>; + interrupts = <0>; + fsl,wires = <4>; + status = "disabled"; + }; + }; + + ssi1: ssi@50034000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; + reg = <0x50034000 0x4000>; + interrupts = <12>; + clocks = <&clks 117>; + clock-names = "ipg"; + dmas = <&sdma 28 1 0>, + <&sdma 29 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + fec: ethernet@50038000 { + compatible = "fsl,imx25-fec"; + reg = <0x50038000 0x4000>; + interrupts = <57>; + clocks = <&clks 88>, <&clks 65>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + }; + + bus@53f00000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x53f00000 0x100000>; + ranges; + + aips2: bridge@53f00000 { + compatible = "fsl,imx25-aips"; + reg = <0x53f00000 0x4000>; + }; + + clks: ccm@53f80000 { + compatible = "fsl,imx25-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + gpt4: timer@53f84000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f84000 0x4000>; + clocks = <&clks 95>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <1>; + }; + + gpt3: timer@53f88000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f88000 0x4000>; + clocks = <&clks 94>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <29>; + }; + + gpt2: timer@53f8c000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f8c000 0x4000>; + clocks = <&clks 93>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <53>; + }; + + gpt1: timer@53f90000 { + compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; + reg = <0x53f90000 0x4000>; + clocks = <&clks 92>, <&clks 47>; + clock-names = "ipg", "per"; + interrupts = <54>; + }; + + epit1: timer@53f94000 { + compatible = "fsl,imx25-epit"; + reg = <0x53f94000 0x4000>; + clocks = <&clks 83>, <&clks 43>; + clock-names = "ipg", "per"; + interrupts = <28>; + }; + + epit2: timer@53f98000 { + compatible = "fsl,imx25-epit"; + reg = <0x53f98000 0x4000>; + clocks = <&clks 84>, <&clks 43>; + clock-names = "ipg", "per"; + interrupts = <27>; + }; + + gpio4: gpio@53f9c000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53f9c000 0x4000>; + interrupts = <23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm2: pwm@53fa0000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <3>; + reg = <0x53fa0000 0x4000>; + clocks = <&clks 106>, <&clks 52>; + clock-names = "ipg", "per"; + interrupts = <36>; + }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <16>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm3: pwm@53fa8000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <3>; + reg = <0x53fa8000 0x4000>; + clocks = <&clks 107>, <&clks 52>; + clock-names = "ipg", "per"; + interrupts = <41>; + }; + + scc: crypto@53fac000 { + compatible = "fsl,imx25-scc"; + reg = <0x53fac000 0x4000>; + clocks = <&clks 111>; + clock-names = "ipg"; + interrupts = <49>, <50>; + interrupt-names = "scm", "smn"; + }; + + rngb: rngb@53fb0000 { + compatible = "fsl,imx25-rngb"; + reg = <0x53fb0000 0x4000>; + clocks = <&clks 109>; + interrupts = <22>; + }; + + esdhc1: mmc@53fb4000 { + compatible = "fsl,imx25-esdhc"; + reg = <0x53fb4000 0x4000>; + interrupts = <9>; + clocks = <&clks 86>, <&clks 63>, <&clks 45>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc2: mmc@53fb8000 { + compatible = "fsl,imx25-esdhc"; + reg = <0x53fb8000 0x4000>; + interrupts = <8>; + clocks = <&clks 87>, <&clks 64>, <&clks 46>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + lcdc: lcdc@53fbc000 { + compatible = "fsl,imx25-fb", "fsl,imx21-fb"; + reg = <0x53fbc000 0x4000>; + interrupts = <39>; + clocks = <&clks 103>, <&clks 66>, <&clks 49>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + slcdc@53fc0000 { + reg = <0x53fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + pwm4: pwm@53fc8000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <3>; + reg = <0x53fc8000 0x4000>; + clocks = <&clks 108>, <&clks 52>; + clock-names = "ipg", "per"; + interrupts = <42>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: dma-controller@53fd4000 { + compatible = "fsl,imx25-sdma"; + reg = <0x53fd4000 0x4000>; + clocks = <&clks 112>, <&clks 68>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + interrupts = <34>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; + }; + + watchdog@53fdc000 { + compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 126>; + clock-names = ""; + interrupts = <55>; + }; + + pwm1: pwm@53fe0000 { + compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; + #pwm-cells = <3>; + reg = <0x53fe0000 0x4000>; + clocks = <&clks 105>, <&clks 52>; + clock-names = "ipg", "per"; + interrupts = <26>; + }; + + iim: efuse@53ff0000 { + compatible = "fsl,imx25-iim", "fsl,imx27-iim"; + reg = <0x53ff0000 0x4000>; + interrupts = <19>; + clocks = <&clks 99>; + }; + + usbotg: usb@53ff4000 { + compatible = "fsl,imx25-usb", "fsl,imx27-usb"; + reg = <0x53ff4000 0x0200>; + interrupts = <37>; + clocks = <&clks 9>, <&clks 70>, <&clks 8>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; + phy_type = "utmi"; + dr_mode = "otg"; + status = "disabled"; + }; + + usbhost1: usb@53ff4400 { + compatible = "fsl,imx25-usb", "fsl,imx27-usb"; + reg = <0x53ff4400 0x0200>; + interrupts = <35>; + clocks = <&clks 9>, <&clks 70>, <&clks 8>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; + maximum-speed = "full-speed"; + phy_type = "serial"; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@53ff4600 { + #index-cells = <1>; + compatible = "fsl,imx25-usbmisc"; + reg = <0x53ff4600 0x00f>; + }; + + dryice@53ffc000 { + compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; + reg = <0x53ffc000 0x4000>; + clocks = <&clks 81>; + clock-names = "ipg"; + interrupts = <25 56>; + }; + }; + + iram: sram@78000000 { + compatible = "mmio-sram"; + reg = <0x78000000 0x20000>; + }; + + emi@80000000 { + compatible = "fsl,emi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x3b002000>; + ranges; + + nfc: nand@bb000000 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "fsl,imx25-nand"; + reg = <0xbb000000 0x2000>; + clocks = <&clks 50>; + clock-names = ""; + interrupts = <33>; + status = "disabled"; + }; + }; + }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts new file mode 100644 index 000000000000..745d5d409952 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Philippe Reynes + * Copyright 2012 Armadeus Systems + * + * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Armadeus Systems APF27 module"; + compatible = "armadeus,imx27-apf27", "fsl,imx27"; + + memory@a0000000 { + device_type = "memory"; + reg = <0xa0000000 0x04000000>; + }; +}; + +&clk_osc26m { + clock-frequency = <0>; +}; + +&iomuxc { + imx27-apf27 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&nfc { + status = "okay"; + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "env2"; + reg = <0x180000 0x80000>; + }; + + partition@200000 { + label = "firmware"; + reg = <0x200000 0x80000>; + }; + + partition@280000 { + label = "dtb"; + reg = <0x280000 0x80000>; + }; + + partition@300000 { + label = "kernel"; + reg = <0x300000 0x500000>; + }; + + partition@800000 { + label = "rootfs"; + reg = <0x800000 0xf800000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts new file mode 100644 index 000000000000..6f1e8ce9e76e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Armadeus Systems - + */ + +/* APF27Dev is a docking board for the APF27 SOM */ +#include "imx27-apf27.dts" + +/ { + model = "Armadeus Systems APF27Dev docking/development board"; + compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; + + display: display { + model = "Chimei-LW700AT9003"; + bits-per-pixel = <16>; /* non-standard but required */ + fsl,pcr = <0xfae80083>; /* non-standard but required */ + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user-key { + label = "user"; + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + linux,code = <276>; /* BTN_EXTRA */ + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + user { + label = "Heartbeat"; + gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_max5821: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "max5821-reg"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + }; +}; + +&cspi1 { + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; + status = "okay"; + + adc@0 { + compatible = "maxim,max1027"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max1027>; + spi-max-frequency = <10000000>; + }; +}; + +&cspi2 { + cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio2 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; + status = "okay"; +}; + +&fb { + display = <&display>; + fsl,dmacr = <0x00020010>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + max5821@38 { + compatible = "maxim,max5821"; + reg = <0x38>; + vref-supply = <®_max5821>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&iomuxc { + imx27-apf27dev { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + >; + }; + + pinctrl_cspi1_cs: cspi1csgrp { + fsl,pins = ; + }; + + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + >; + }; + + pinctrl_cspi2_cs: cspi2csgrp { + fsl,pins = < + MX27_PAD_CSI_D5__GPIO2_17 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = ; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = ; + }; + + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_max1027: max1027 { + fsl,pins = < + MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ + MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ + >; + }; + + pinctrl_pwm: pwmgrp { + fsl,pins = < + MX27_PAD_PWMO__PWMO 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; + + pinctrl_sdhc2_cd: sdhc2cdgrp { + fsl,pins = ; + }; + }; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi new file mode 100644 index 000000000000..74110bbcd9d4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Eukrea CPUIMX27"; + compatible = "eukrea,cpuimx27", "fsl,imx27"; + + memory@a0000000 { + device_type = "memory"; + reg = <0xa0000000 0x04000000>; + }; + + clk14745600: clk-uart { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire>; + status = "okay"; +}; + +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor: nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; + }; + + uart8250@3,200000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_1>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x200000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; + + uart8250@3,400000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_2>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x400000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; + + uart8250@3,800000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_3>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x800000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; + + uart8250@3,1000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8250_4>; + compatible = "ns8250"; + clocks = <&clk14745600>; + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; + interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; + reg = <3 0x1000000 0x1000>; + reg-shift = <1>; + reg-io-width = <1>; + no-loopback-test; + }; +}; + +&iomuxc { + imx27-eukrea-cpuimx27 { + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + + pinctrl_owire: owiregrp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 + MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 + MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 + MX27_PAD_USBH1_FS__UART4_RTS 0x0 + >; + }; + + pinctrl_uart8250_1: uart82501grp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 + >; + }; + + pinctrl_uart8250_2: uart82502grp { + fsl,pins = < + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 + >; + }; + + pinctrl_uart8250_3: uart82503grp { + fsl,pins = < + MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 + >; + }; + + pinctrl_uart8250_4: uart82504grp { + fsl,pins = < + MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts new file mode 100644 index 000000000000..9c3ec82ec7e5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +#include "imx27-eukrea-cpuimx27.dtsi" + +/ { + model = "Eukrea MBIMXSD27"; + compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; + + display0: CMO-QVGA { + model = "CMO-QVGA"; + bits-per-pixel = <16>; + fsl,pcr = <0xfad08b80>; + + display-timings { + native-mode = <&timing0>; + timing0: 320x240 { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <20>; + hsync-len = <30>; + hfront-porch = <38>; + vback-porch = <4>; + vsync-len = <3>; + vfront-porch = <15>; + }; + }; + }; + + backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds>; + + led1 { + label = "system::live"; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "system::user"; + gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + reg_lcd: regulator@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdreg>; + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "LCD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&cspi1 { + pinctrl-0 = <&pinctrl_cspi1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "okay"; + + ads7846@0 { + compatible = "ti,ads7846"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0>; + interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + spi-cpol; + spi-max-frequency = <1500000>; + ti,keep-vref-on; + }; +}; + +&fb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb>; + display = <&display0>; + lcd-supply = <®_lcd>; + fsl,dmacr = <0x00040060>; + fsl,lscr1 = <0x00120300>; + fsl,lpccr = <0x00a903ff>; + status = "okay"; +}; + +&i2c1 { + codec: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&kpp { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + >; + status = "okay"; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + codec-handle = <&codec>; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&iomuxc { + imx27-eukrea-cpuimx27-baseboard { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX27_PAD_PWMO__GPIO5_5 0x0 + >; + }; + + pinctrl_gpioleds: gpioledsgrp { + fsl,pins = < + MX27_PAD_PC_PWRON__GPIO6_16 0x0 + MX27_PAD_PC_CD2_B__GPIO6_19 0x0 + >; + }; + + pinctrl_imxfb: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + + pinctrl_lcdreg: lcdreggrp { + fsl,pins = < + MX27_PAD_CLS__GPIO1_25 0x0 + >; + }; + + pinctrl_sdhc1: sdhc1grp { + fsl,pins = < + MX27_PAD_SD1_CLK__SD1_CLK 0x0 + MX27_PAD_SD1_CMD__SD1_CMD 0x0 + MX27_PAD_SD1_D0__SD1_D0 0x0 + MX27_PAD_SD1_D1__SD1_D1 0x0 + MX27_PAD_SD1_D2__SD1_D2 0x0 + MX27_PAD_SD1_D3__SD1_D3 0x0 + >; + }; + + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 + MX27_PAD_SSI4_FS__SSI4_FS 0x0 + MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 + MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts new file mode 100644 index 000000000000..35123b7cb6b3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Sascha Hauer, Pengutronix + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Freescale i.MX27 Product Development Kit"; + compatible = "fsl,imx27-pdk", "fsl,imx27"; + + memory@a0000000 { + device_type = "memory"; + reg = <0xa0000000 0x08000000>; + }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks IMX27_CLK_DUMMY>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + }; +}; + +&cspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2>; + cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13783@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + regulators { + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { + regulator-always-on; + regulator-boot-on; + }; + + gpo3_reg: gpo3 { + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&fec { + phy-mode = "mii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&kpp { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + >; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + fsl,usbphy = <&usbphy0>; + phy_type = "ulpi"; + status = "okay"; +}; + +&iomuxc { + imx27-pdk { + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ + MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts new file mode 100644 index 000000000000..188639738dc3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Markus Pargmann, Pengutronix + */ + +#include "imx27-phytec-phycard-s-som.dtsi" + +/ { + model = "Phytec pca100 rapid development kit"; + compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; + + chosen { + stdout-path = &uart1; + }; + + display: display { + model = "Primeview-PD050VL1"; + bits-per-pixel = <16>; /* non-standard but required */ + fsl,pcr = <0xf0c88080>; /* non-standard but required */ + display-timings { + native-mode = <&timing0>; + timing0: 640x480 { + hactive = <640>; + vactive = <480>; + hback-porch = <112>; + hfront-porch = <36>; + hsync-len = <32>; + vback-porch = <33>; + vfront-porch = <33>; + vsync-len = <2>; + clock-frequency = <25000000>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&fb { + display = <&display>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + adc@64 { + compatible = "maxim,max1037"; + vcc-supply = <®_3v3>; + reg = <0x64>; + }; +}; + +&iomuxc { + imx27-phycard-s-rdk { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_owire1: owire1grp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 + >; + }; + }; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire1>; + status = "okay"; +}; + +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; + cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi new file mode 100644 index 000000000000..303f920201c5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar + * and Markus Pargmann, Pengutronix + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pca100"; + compatible = "phytec,imx27-pca100", "fsl,imx27"; + + memory@a0000000 { + device_type = "memory"; + reg = <0xa0000000 0x08000000>; /* 128MB */ + }; +}; + +&cspi1 { + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24@52 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&iomuxc { + imx27-phycard-s-som { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts new file mode 100644 index 000000000000..344e77790152 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + */ + +#include "imx27-phytec-phycore-som.dtsi" + +/ { + model = "Phytec pcm970"; + compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; + + chosen { + stdout-path = &uart1; + }; + + display0: LQ035Q7 { + model = "Sharp-LQ035Q7"; + bits-per-pixel = <16>; + fsl,pcr = <0xf00080c0>; + + display-timings { + native-mode = <&timing0>; + timing0: 240x320 { + clock-frequency = <5500000>; + hactive = <240>; + vactive = <320>; + hback-porch = <5>; + hsync-len = <7>; + hfront-porch = <16>; + vback-porch = <7>; + vsync-len = <1>; + vfront-porch = <9>; + pixelclk-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + }; + }; + }; + + regulators { + regulator@2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csien>; + reg = <2>; + regulator-name = "CSI_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; + + usbphy { + usbphy2: usbphy@2 { + compatible = "usb-nop-xceiv"; + reg = <2>; + vcc-supply = <®_5v0>; + clocks = <&clks IMX27_CLK_DUMMY>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + }; +}; + +&cspi1 { + pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; +}; + +&fb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb1>; + display = <&display0>; + lcd-supply = <®_5v0>; + fsl,dmacr = <0x00020010>; + fsl,lscr1 = <0x00120300>; + fsl,lpccr = <0x00a903ff>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + camgpio: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + imx27_phycore_rdk { + pinctrl_csien: csiengrp { + fsl,pins = < + MX27_PAD_USB_OC_B__GPIO2_24 0x0 + >; + }; + + pinctrl_cspi1cs1: cspi1cs1grp { + fsl,pins = < + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + /* Add pullup to DATA line */ + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x1 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_owire1: owire1grp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ + MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ + >; + }; + }; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire1>; + status = "okay"; +}; + +&pmicleds { + ledr1: led@3 { + reg = <3>; + label = "system:red1:user"; + }; + + ledg1: led@4 { + reg = <4>; + label = "system:green1:user"; + }; + + ledb1: led@5 { + reg = <5>; + label = "system:blue1:user"; + }; + + ledr2: led@6 { + reg = <6>; + label = "system:red2:user"; + }; + + ledg2: led@7 { + reg = <7>; + label = "system:green2:user"; + }; + + ledb2: led@8 { + reg = <8>; + label = "system:blue2:user"; + }; + + ledr3: led@9 { + reg = <9>; + label = "system:red3:nand"; + linux,default-trigger = "nand-disk"; + }; + + ledg3: led@10 { + reg = <10>; + label = "system:green3:live"; + linux,default-trigger = "heartbeat"; + }; + + ledb3: led@11 { + reg = <11>; + label = "system:blue3:cpu"; + linux,default-trigger = "cpu0"; + }; +}; + +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; + bus-width = <4>; + cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vmmc1_reg>; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + vbus-supply = <®_5v0>; + fsl,usbphy = <&usbphy2>; + disable-over-current; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + + can@4,0 { + compatible = "nxp,sja1000"; + reg = <4 0x00000000 0x00000100>; + interrupt-parent = <&gpio5>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + nxp,external-clock-frequency = <16000000>; + nxp,tx-output-config = <0x16>; + nxp,no-comparator-bypass; + fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..3d10273177e9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Pengutronix + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pcm038"; + compatible = "phytec,imx27-pcm038", "fsl,imx27"; + + memory@a0000000 { + device_type = "memory"; + reg = <0xa0000000 0x08000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + vcc-supply = <&sw3_reg>; + clocks = <&clks IMX27_CLK_DUMMY>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + }; +}; + +&audmux { + status = "okay"; + + /* SSI0 <=> PINS_4 (MC13783 Audio) */ + ssi0 { + fsl,audmux-port = <0>; + fsl,port-config = <0xcb205000>; + }; + + pins4 { + fsl,audmux-port = <2>; + fsl,port-config = <0x00001000>; + }; +}; + +&cspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13783@0 { + compatible = "fsl,mc13783"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0>; + spi-cs-high; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio2>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + pmicleds: leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; + }; + + regulators { + /* SW1A and SW1B joined operation */ + sw1_reg: sw1a { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1520000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SW2A and SW2B joined operation */ + sw2_reg: sw2a { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio_reg: vaudio { + regulator-always-on; + regulator-boot-on; + }; + + violo_reg: violo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi_reg: viohi { + regulator-always-on; + regulator-boot-on; + }; + + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vrf1_reg: vrf1 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vrf2_reg: vrf2 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { }; + + pwgt1spi_reg: pwgt1spi { + regulator-always-on; + }; + }; + }; +}; + +&fec { + phy-mode = "mii"; + phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + phy-supply = <®_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24@52 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x52>; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + lm75@4a { + compatible = "national,lm75"; + reg = <0x4a>; + }; +}; + +&iomuxc { + imx27_phycore_som { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI1_FS__SSI1_FS 0x0 + MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 + MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 + MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + phy_type = "ulpi"; + fsl,usbphy = <&usbphy0>; + vbus-supply = <&sw3_reg>; + disable-over-current; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; + #address-cells = <1>; + #size-cells = <1>; + }; + + sram: sram@1,0 { + compatible = "mtd-ram"; + reg = <1 0x00000000 0x00800000>; + bank-width = <2>; + linux,mtd-name = "mtd-ram.0"; + fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h new file mode 100644 index 000000000000..75aea0c701d4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h @@ -0,0 +1,474 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Markus Pargmann , Pengutronix + */ + +#ifndef __DTS_IMX27_PINFUNC_H +#define __DTS_IMX27_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + * mux_id consists of + * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) + * + * function: 0 - Primary function + * 1 - Alternate function + * 2 - GPIO + * direction: 0 - Input + * 1 - Output + * gpio_oconf: 0 - A_IN + * 1 - B_IN + * 2 - C_IN + * 3 - Data Register + * gpio_iconfa/b: 0 - GPIO_IN + * 1 - Interrupt Status Register + * 2 - 0 + * 3 - 1 + * + * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). + */ + +#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 +#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 +#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 +#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 +#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 +#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 +#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 +#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 +#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 +#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 +#define MX27_PAD_LSCLK__LSCLK 0x05 0x004 +#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 +#define MX27_PAD_LD0__LD0 0x06 0x004 +#define MX27_PAD_LD0__GPIO1_6 0x06 0x032 +#define MX27_PAD_LD1__LD1 0x07 0x004 +#define MX27_PAD_LD1__GPIO1_7 0x07 0x032 +#define MX27_PAD_LD2__LD2 0x08 0x004 +#define MX27_PAD_LD2__GPIO1_8 0x08 0x032 +#define MX27_PAD_LD3__LD3 0x09 0x004 +#define MX27_PAD_LD3__GPIO1_9 0x09 0x032 +#define MX27_PAD_LD4__LD4 0x0a 0x004 +#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 +#define MX27_PAD_LD5__LD5 0x0b 0x004 +#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 +#define MX27_PAD_LD6__LD6 0x0c 0x004 +#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 +#define MX27_PAD_LD7__LD7 0x0d 0x004 +#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 +#define MX27_PAD_LD8__LD8 0x0e 0x004 +#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 +#define MX27_PAD_LD9__LD9 0x0f 0x004 +#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 +#define MX27_PAD_LD10__LD10 0x10 0x004 +#define MX27_PAD_LD10__GPIO1_16 0x10 0x032 +#define MX27_PAD_LD11__LD11 0x11 0x004 +#define MX27_PAD_LD11__GPIO1_17 0x11 0x032 +#define MX27_PAD_LD12__LD12 0x12 0x004 +#define MX27_PAD_LD12__GPIO1_18 0x12 0x032 +#define MX27_PAD_LD13__LD13 0x13 0x004 +#define MX27_PAD_LD13__GPIO1_19 0x13 0x032 +#define MX27_PAD_LD14__LD14 0x14 0x004 +#define MX27_PAD_LD14__GPIO1_20 0x14 0x032 +#define MX27_PAD_LD15__LD15 0x15 0x004 +#define MX27_PAD_LD15__GPIO1_21 0x15 0x032 +#define MX27_PAD_LD16__LD16 0x16 0x004 +#define MX27_PAD_LD16__GPIO1_22 0x16 0x032 +#define MX27_PAD_LD17__LD17 0x17 0x004 +#define MX27_PAD_LD17__GPIO1_23 0x17 0x032 +#define MX27_PAD_REV__REV 0x18 0x004 +#define MX27_PAD_REV__GPIO1_24 0x18 0x032 +#define MX27_PAD_CLS__CLS 0x19 0x004 +#define MX27_PAD_CLS__GPIO1_25 0x19 0x032 +#define MX27_PAD_PS__PS 0x1a 0x004 +#define MX27_PAD_PS__GPIO1_26 0x1a 0x032 +#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 +#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 +#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 +#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 +#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 +#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 +#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 +#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 +#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 +#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 +#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 +#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 +#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 +#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 +#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 +#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 +#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 +#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 +#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 +#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 +#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 +#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 +#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 +#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 +#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 +#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 +#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 +#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 +#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 +#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 +#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 +#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 +#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 +#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 +#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 +#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 +#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 +#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 +#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 +#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 +#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 +#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 +#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 +#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 +#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 +#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 +#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 +#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 +#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 +#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 +#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 +#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 +#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 +#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 +#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 +#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 +#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 +#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 +#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 +#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 +#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 +#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 +#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 +#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 +#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 +#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 +#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 +#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 +#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 +#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 +#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 +#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 +#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 +#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 +#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 +#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 +#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 +#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 +#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 +#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 +#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 +#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 +#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 +#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 +#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 +#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 +#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 +#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 +#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 +#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 +#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 +#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 +#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 +#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 +#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 +#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 +#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 +#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 +#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 +#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 +#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 +#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 +#define MX27_PAD_TOUT__TOUT 0x4e 0x004 +#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 +#define MX27_PAD_TIN__TIN 0x4f 0x000 +#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 +#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 +#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 +#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 +#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 +#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 +#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 +#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 +#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 +#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 +#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 +#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 +#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 +#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 +#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 +#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 +#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 +#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 +#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 +#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 +#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 +#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 +#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 +#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 +#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 +#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 +#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 +#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 +#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 +#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 +#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 +#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 +#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 +#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 +#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 +#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 +#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 +#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 +#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 +#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 +#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 +#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 +#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 +#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 +#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 +#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 +#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 +#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 +#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 +#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 +#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 +#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 +#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 +#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 +#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 +#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 +#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 +#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 +#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 +#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 +#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 +#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 +#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 +#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 +#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 +#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 +#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 +#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 +#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 +#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 +#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 +#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 +#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 +#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 +#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 +#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 +#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 +#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 +#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 +#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 +#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 +#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 +#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 +#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 +#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 +#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 +#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 +#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 +#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 +#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 +#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 +#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 +#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 +#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 +#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 +#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 +#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 +#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 +#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 +#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 +#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 +#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 +#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 +#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 +#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 +#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 +#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 +#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 +#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 +#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 +#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 +#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 +#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 +#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 +#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 +#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 +#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 +#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 +#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 +#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 +#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 +#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 +#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 +#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 +#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 +#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 +#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 +#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 +#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 +#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 +#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 +#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 +#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 +#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 +#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 +#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 +#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 +#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 +#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 +#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 +#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 +#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 +#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 +#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 +#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 +#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 +#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 +#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 +#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 +#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 +#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 +#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 +#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 +#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 +#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 +#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 +#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 +#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 +#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 +#define MX27_PAD_PWMO__PWMO 0x85 0x004 +#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 +#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 +#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 +#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 +#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 +#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 +#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 +#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 +#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 +#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 +#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 +#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 +#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 +#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 +#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 +#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 +#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 +#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 +#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 +#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 +#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 +#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 +#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 +#define MX27_PAD_RTCK__RTCK 0x90 0x004 +#define MX27_PAD_RTCK__OWIRE 0x90 0x005 +#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 +#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 +#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 +#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 +#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 +#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 +#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 +#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 +#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 +#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 +#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 +#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 +#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 +#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 +#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 +#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 +#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 +#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 +#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 +#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 +#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 +#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 +#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 +#define MX27_PAD_NFRB__NFRB 0xa0 0x000 +#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 +#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 +#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 +#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 +#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 +#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 +#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 +#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 +#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 +#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 +#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 +#define MX27_PAD_NFALE__NFALE 0xa4 0x004 +#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 +#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 +#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 +#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 +#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 +#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 +#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 +#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 +#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 +#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 +#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 +#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 +#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 +#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 +#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 +#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 +#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 +#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 +#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 +#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 +#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 +#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 +#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 +#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 +#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 +#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 +#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 +#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 +#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 +#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 +#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 +#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 +#define MX27_PAD_CLKO__CLKO 0xaf 0x004 +#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 +#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 +#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 +#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 +#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 +#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 +#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 +#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 +#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 +#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 +#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 +#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 +#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 +#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 +#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 +#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 +#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 +#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 +#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 +#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 +#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 +#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 +#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 +#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 +#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 +#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 + +#endif /* __DTS_IMX27_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi new file mode 100644 index 000000000000..e140307be2e7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx27.dtsi @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Sascha Hauer, Pengutronix + +#include "imx27-pinfunc.h" + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + spi0 = &cspi1; + spi1 = &cspi2; + spi2 = &cspi3; + }; + + aitc: aitc-interrupt-controller@10040000 { + compatible = "fsl,imx27-aitc", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10040000 0x1000>; + }; + + clocks { + clk_osc26m: osc26m { + compatible = "fsl,imx-osc26m", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu: cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "arm,arm926ej-s"; + operating-points = < + /* kHz uV */ + 266000 1300000 + 399000 1450000 + >; + clock-latency = <62500>; + clocks = <&clks IMX27_CLK_CPU_DIV>; + voltage-tolerance = <5>; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&aitc>; + ranges; + + aipi1: aipi@10000000 { /* AIPI1 */ + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x20000>; + ranges; + + dma: dma@10001000 { + compatible = "fsl,imx27-dma"; + reg = <0x10001000 0x1000>; + interrupts = <32>; + clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, + <&clks IMX27_CLK_DMA_AHB_GATE>; + clock-names = "ipg", "ahb"; + #dma-cells = <1>; + dma-channels = <16>; + }; + + wdog: watchdog@10002000 { + compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; + reg = <0x10002000 0x1000>; + interrupts = <27>; + clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; + }; + + gpt1: timer@10003000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x10003000 0x1000>; + interrupts = <26>; + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@10004000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x10004000 0x1000>; + interrupts = <25>; + clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + + gpt3: timer@10005000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x10005000 0x1000>; + interrupts = <24>; + clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + + pwm: pwm@10006000 { + #pwm-cells = <3>; + compatible = "fsl,imx27-pwm"; + reg = <0x10006000 0x1000>; + interrupts = <23>; + clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + + rtc: rtc@10007000 { + compatible = "fsl,imx21-rtc"; + reg = <0x10007000 0x1000>; + interrupts = <22>; + clocks = <&clks IMX27_CLK_CKIL>, + <&clks IMX27_CLK_RTC_IPG_GATE>; + clock-names = "ref", "ipg"; + }; + + kpp: kpp@10008000 { + compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; + reg = <0x10008000 0x1000>; + interrupts = <21>; + clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; + status = "disabled"; + }; + + owire: owire@10009000 { + compatible = "fsl,imx27-owire", "fsl,imx21-owire"; + reg = <0x10009000 0x1000>; + clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; + status = "disabled"; + }; + + uart1: serial@1000a000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000a000 0x1000>; + interrupts = <20>; + clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@1000b000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000b000 0x1000>; + interrupts = <19>; + clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@1000c000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000c000 0x1000>; + interrupts = <18>; + clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@1000d000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000d000 0x1000>; + interrupts = <17>; + clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + cspi1: spi@1000e000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x1000e000 0x1000>; + interrupts = <16>; + clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + cspi2: spi@1000f000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x1000f000 0x1000>; + interrupts = <15>; + clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi@10010000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; + reg = <0x10010000 0x1000>; + interrupts = <14>; + clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; + dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; + dma-names = "rx0", "tx0", "rx1", "tx1"; + fsl,fifo-depth = <8>; + status = "disabled"; + }; + + ssi2: ssi@10011000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; + reg = <0x10011000 0x1000>; + interrupts = <13>; + clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; + dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; + dma-names = "rx0", "tx0", "rx1", "tx1"; + fsl,fifo-depth = <8>; + status = "disabled"; + }; + + i2c1: i2c@10012000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; + reg = <0x10012000 0x1000>; + interrupts = <12>; + clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; + status = "disabled"; + }; + + sdhci1: mmc@10013000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10013000 0x1000>; + interrupts = <11>; + clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; + clock-names = "ipg", "per"; + dmas = <&dma 7>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: mmc@10014000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10014000 0x1000>; + interrupts = <10>; + clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; + clock-names = "ipg", "per"; + dmas = <&dma 6>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + iomuxc: iomuxc@10015000 { + compatible = "fsl,imx27-iomuxc"; + reg = <0x10015000 0x600>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@10015000 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015000 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@10015100 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015100 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@10015200 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015200 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@10015300 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015300 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@10015400 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015400 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@10015500 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015500 0x100>; + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + audmux: audmux@10016000 { + compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; + reg = <0x10016000 0x1000>; + clocks = <&clks IMX27_CLK_DUMMY>; + clock-names = "audmux"; + status = "disabled"; + }; + + cspi3: spi@10017000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x10017000 0x1000>; + interrupts = <6>; + clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: timer@10019000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x10019000 0x1000>; + interrupts = <4>; + clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + + gpt5: timer@1001a000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x1001a000 0x1000>; + interrupts = <3>; + clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + + uart5: serial@1001b000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1001b000 0x1000>; + interrupts = <49>; + clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@1001c000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1001c000 0x1000>; + interrupts = <48>; + clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@1001d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; + reg = <0x1001d000 0x1000>; + interrupts = <1>; + clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; + status = "disabled"; + }; + + sdhci3: mmc@1001e000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x1001e000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, + <&clks IMX27_CLK_PER2_GATE>; + clock-names = "ipg", "per"; + dmas = <&dma 36>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + gpt6: timer@1001f000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x1001f000 0x1000>; + interrupts = <2>; + clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; + }; + + aipi2: aipi@10020000 { /* AIPI2 */ + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10020000 0x20000>; + ranges; + + fb: fb@10021000 { + compatible = "fsl,imx27-fb", "fsl,imx21-fb"; + interrupts = <61>; + reg = <0x10021000 0x1000>; + clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, + <&clks IMX27_CLK_LCDC_AHB_GATE>, + <&clks IMX27_CLK_PER3_GATE>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + coda: coda@10023000 { + compatible = "fsl,imx27-vpu", "cnm,codadx6"; + reg = <0x10023000 0x0200>; + interrupts = <53>; + clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, + <&clks IMX27_CLK_VPU_AHB_GATE>; + clock-names = "per", "ahb"; + iram = <&iram>; + }; + + usbotg: usb@10024000 { + compatible = "fsl,imx27-usb"; + reg = <0x10024000 0x200>; + interrupts = <56>; + clocks = <&clks IMX27_CLK_USB_IPG_GATE>, + <&clks IMX27_CLK_USB_AHB_GATE>, + <&clks IMX27_CLK_USB_DIV>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbh1: usb@10024200 { + compatible = "fsl,imx27-usb"; + reg = <0x10024200 0x200>; + interrupts = <54>; + clocks = <&clks IMX27_CLK_USB_IPG_GATE>, + <&clks IMX27_CLK_USB_AHB_GATE>, + <&clks IMX27_CLK_USB_DIV>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 1>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh2: usb@10024400 { + compatible = "fsl,imx27-usb"; + reg = <0x10024400 0x200>; + interrupts = <55>; + clocks = <&clks IMX27_CLK_USB_IPG_GATE>, + <&clks IMX27_CLK_USB_AHB_GATE>, + <&clks IMX27_CLK_USB_DIV>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@10024600 { + #index-cells = <1>; + compatible = "fsl,imx27-usbmisc"; + reg = <0x10024600 0x200>; + }; + + sahara2: crypto@10025000 { + compatible = "fsl,imx27-sahara"; + reg = <0x10025000 0x1000>; + interrupts = <59>; + clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, + <&clks IMX27_CLK_SAHARA_AHB_GATE>; + clock-names = "ipg", "ahb"; + }; + + clks: ccm@10027000{ + compatible = "fsl,imx27-ccm"; + reg = <0x10027000 0x1000>; + #clock-cells = <1>; + }; + + iim: efuse@10028000 { + compatible = "fsl,imx27-iim"; + reg = <0x10028000 0x1000>; + interrupts = <62>; + clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; + }; + + fec: ethernet@1002b000 { + compatible = "fsl,imx27-fec"; + reg = <0x1002b000 0x1000>; + interrupts = <50>; + clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, + <&clks IMX27_CLK_FEC_AHB_GATE>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + }; + + nfc: nand-controller@d8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx27-nand"; + reg = <0xd8000000 0x1000>; + interrupts = <29>; + clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; + status = "disabled"; + }; + + weim: weim@d8002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx27-weim"; + reg = <0xd8002000 0x1000>; + clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; + ranges = < + 0 0 0xc0000000 0x08000000 + 1 0 0xc8000000 0x08000000 + 2 0 0xd0000000 0x02000000 + 3 0 0xd2000000 0x02000000 + 4 0 0xd4000000 0x02000000 + 5 0 0xd6000000 0x02000000 + >; + status = "disabled"; + }; + + iram: sram@ffff4c00 { + compatible = "mmio-sram"; + reg = <0xffff4c00 0xb400>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts new file mode 100644 index 000000000000..d87eee3f9b3c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Denis 'GNUtoo' Carikli + */ + +/dts-v1/; +#include "imx31.dtsi" + +/ { + model = "Buglabs i.MX31 Bug 1.x"; + compatible = "buglabs,imx31-bug", "fsl,imx31"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128M */ + }; +}; + +&uart5 { + uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts new file mode 100644 index 000000000000..d17abdfb6330 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2018 Vladimir Zapolskiy + +/dts-v1/; + +#include "imx31.dtsi" + +#include +#include + +/ { + model = "LogicPD i.MX31 Lite"; + compatible = "logicpd,imx31-lite", "fsl,imx31"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ata { + status = "okay"; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b { /* NVCC10 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + violo { /* NVCC1 and NVCC7 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi { /* VIOHI */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio { /* VAUDIO */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vcam { /* NVCC4 */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc2 { /* NVCC3 */ + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart3 { + uart-has-rtscts; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x200000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; + }; + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + reg = <4 0x0 0x100>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi new file mode 100644 index 000000000000..95c05f17a6d5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2016-2018 Vladimir Zapolskiy +// Copyright 2012 Denis 'GNUtoo' Carikli + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1136jf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + avic: interrupt-controller@68000000 { + compatible = "fsl,imx31-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x68000000 0x100000>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + iram: sram@1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1fffc000 0x4000>; + }; + + aips1: bus@43f00000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + i2c1: i2c@43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata@43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + + uart1: serial@43f90000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + clocks = <&clks 10>, <&clks 30>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + interrupts = <32>; + clocks = <&clks 10>, <&clks 31>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + kpp: kpp@43fa8000 { + compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; + reg = <0x43fa8000 0x4000>; + interrupts = <24>; + clocks = <&clks 46>; + status = "disabled"; + }; + + uart4: serial@43fb0000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43fb0000 0x4000>; + clocks = <&clks 10>, <&clks 49>; + clock-names = "ipg", "per"; + interrupts = <46>; + status = "disabled"; + }; + + uart5: serial@43fb4000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43fb4000 0x4000>; + interrupts = <47>; + clocks = <&clks 10>, <&clks 50>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + spba-bus@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x100000>; + ranges; + + sdhci1: mmc@50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: mmc@50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + uart3: serial@5000c000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <18>; + clocks = <&clks 10>, <&clks 48>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + spi2: spi@50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + iim: efuse@5001c000 { + compatible = "fsl,imx31-iim", "fsl,imx27-iim"; + reg = <0x5001c000 0x1000>; + interrupts = <19>; + clocks = <&clks 25>; + }; + }; + + bus@53f00000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x53f00000 0x100000>; + ranges; + + clks: ccm@53f80000{ + compatible = "fsl,imx31-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>, <53>; + #clock-cells = <1>; + }; + + spi3: spi@53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpt: timer@53f90000 { + compatible = "fsl,imx31-gpt"; + reg = <0x53f90000 0x4000>; + interrupts = <29>; + clocks = <&clks 10>, <&clks 22>; + clock-names = "ipg", "per"; + }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng@53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: dma-controller@53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc@53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: watchdog@53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + interrupts = <55>; + }; + + pwm: pwm@53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + emi@b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand@b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim@b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi new file mode 100644 index 000000000000..17bd2a97609a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +#include "imx35.dtsi" + +/ { + model = "Eukrea CPUIMX35"; + compatible = "eukrea,cpuimx35", "fsl,imx35"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128M */ + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tsc2007: tsc2007@48 { + compatible = "ti,tsc2007"; + gpios = <&gpio3 2 0>; + interrupt-parent = <&gpio3>; + interrupts = <0x2 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_1>; + reg = <0x48>; + ti,x-plate-ohms = <180>; + }; +}; + +&iomuxc { + imx35-eukrea { + pinctrl_fec: fecgrp { + fsl,pins = < + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 + MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX35_PAD_FEC_COL__FEC_COL 0x80000000 + MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 + MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 + MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 + MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 + MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 + MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 + MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 + MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 + MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 + MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 + MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 + >; + }; + + pinctrl_tsc2007_1: tsc2007grp-1 { + fsl,pins = ; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts new file mode 100644 index 000000000000..7f4f812b0811 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +/dts-v1/; + +#include +#include +#include "imx35-eukrea-cpuimx35.dtsi" + +/ { + model = "Eukrea CPUIMX35"; + compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bp1>; + + button { + label = "BP1"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + linux,input-type = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led1>; + + led1 { + label = "led1"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx35-eukrea-tlv320aic23"; + ssi-controller = <&ssi1>; + fsl,mux-int-port = <1>; + fsl,mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&iomuxc { + imx35-eukrea { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 + MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 + MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 + >; + }; + + pinctrl_bp1: bp1grp { + fsl,pins = ; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ + >; + }; + + pinctrl_led1: led1grp { + fsl,pins = ; + }; + + pinctrl_reg_lcd_3v3: reg-lcd-3v3 { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 + MX35_PAD_CTS1__UART1_CTS 0x1c5 + MX35_PAD_RTS1__UART1_RTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 + MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 + MX35_PAD_RTS2__UART2_RTS 0x1c5 + MX35_PAD_CTS2__UART2_CTS 0x1c5 + >; + }; + }; +}; + +&ssi1 { + codec-handle = <&tlv320aic23>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx35-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx35-pdk.dts new file mode 100644 index 000000000000..ddce0a844758 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx35-pdk.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013 Eukréa Electromatique +// Copyright 2014 Freescale Semiconductor, Inc. + +/dts-v1/; +#include "imx35.dtsi" + +/ { + model = "Freescale i.MX35 Product Development Kit"; + compatible = "fsl,imx35-pdk", "fsl,imx35"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>, + <0x90000000 0x8000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + imx35-pdk { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 + MX35_PAD_CTS1__UART1_CTS 0x1c5 + MX35_PAD_RTS1__UART1_RTS 0x1c5 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h new file mode 100644 index 000000000000..9d6cc9564b72 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h @@ -0,0 +1,966 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX35_PINFUNC_H +#define __DTS_IMX35_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 +#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 +#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 +#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 +#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 +#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 +#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 +#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 +#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 +#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 +#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 +#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0 +#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0 +#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 +#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 +#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0 +#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0 +#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0 +#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0 +#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0 +#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0 +#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 +#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0 +#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0 +#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0 +#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0 +#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0 +#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0 +#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0 +#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0 +#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0 +#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 +#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0 +#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0 +#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0 +#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0 +#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0 +#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0 +#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 +#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0 +#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0 +#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0 +#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0 +#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0 +#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0 +#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0 +#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0 +#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0 +#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0 +#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0 +#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0 +#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0 +#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0 +#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0 +#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0 +#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0 +#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0 +#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0 +#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0 +#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0 +#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0 +#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0 +#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0 +#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0 +#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0 +#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0 +#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0 +#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0 +#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0 +#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0 +#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0 +#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0 +#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0 +#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0 +#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0 +#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0 +#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0 +#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0 +#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0 +#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0 +#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0 +#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0 +#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0 +#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0 +#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0 +#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0 +#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0 +#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0 +#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0 +#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0 +#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0 +#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0 +#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0 +#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0 +#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0 +#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0 +#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0 +#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0 +#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0 +#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0 +#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0 +#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0 +#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0 +#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0 +#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0 +#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0 +#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0 +#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0 +#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0 +#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 +#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0 +#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0 +#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0 +#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0 +#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 +#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 +#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0 +#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0 +#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1 +#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 +#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 +#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0 +#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 +#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0 +#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0 +#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0 +#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0 +#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0 +#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0 +#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0 +#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0 +#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0 +#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0 +#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0 +#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0 +#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0 +#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0 +#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0 +#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0 +#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0 +#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 +#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0 +#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0 +#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0 +#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0 +#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0 +#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0 +#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0 +#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0 +#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0 +#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0 +#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0 +#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0 +#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0 +#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0 +#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0 +#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0 +#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0 +#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0 +#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0 +#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0 +#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0 +#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0 +#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0 +#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0 +#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0 +#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0 +#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0 +#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0 +#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0 +#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0 +#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0 +#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0 +#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0 +#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0 +#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0 +#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0 +#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0 +#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0 +#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0 +#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0 +#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0 +#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0 +#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0 +#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1 +#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0 +#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0 +#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0 +#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1 +#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0 +#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0 +#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0 +#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1 +#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0 +#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0 +#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0 +#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0 +#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0 +#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0 +#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0 +#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0 +#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0 +#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0 +#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0 +#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0 +#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0 +#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0 +#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0 +#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0 +#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0 +#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0 +#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0 +#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0 +#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0 +#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0 +#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0 +#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0 +#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0 +#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0 +#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0 +#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0 +#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0 +#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0 +#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0 +#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0 +#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0 +#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0 +#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0 +#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0 +#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0 +#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0 +#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0 +#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0 +#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0 +#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0 +#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0 +#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0 +#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0 +#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0 +#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0 +#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0 +#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0 +#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0 +#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0 +#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0 +#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0 +#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0 +#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1 +#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0 +#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0 +#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0 +#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0 +#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1 +#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0 +#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0 +#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0 +#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0 +#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0 +#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0 +#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0 +#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0 +#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0 +#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0 +#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0 +#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1 +#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0 +#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0 +#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1 +#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0 +#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0 +#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0 +#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0 +#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 +#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1 +#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0 +#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0 +#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1 +#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0 +#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1 +#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0 +#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1 +#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0 +#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1 +#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0 +#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0 +#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0 +#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0 +#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1 +#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0 +#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0 +#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1 +#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 +#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0 +#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0 +#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0 +#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0 +#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0 +#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0 +#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0 +#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0 +#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0 +#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0 +#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1 +#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0 +#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0 +#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0 +#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0 +#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0 +#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1 +#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0 +#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0 +#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0 +#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0 +#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0 +#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1 +#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0 +#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1 +#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2 +#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0 +#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0 +#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0 +#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0 +#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1 +#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0 +#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1 +#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0 +#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1 +#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0 +#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0 +#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0 +#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1 +#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0 +#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0 +#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0 +#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0 +#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0 +#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0 +#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0 +#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1 +#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1 +#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0 +#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0 +#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0 +#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0 +#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1 +#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0 +#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0 +#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0 +#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0 +#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0 +#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0 +#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0 +#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0 +#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0 +#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0 +#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0 +#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0 +#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1 +#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0 +#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0 +#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0 +#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0 +#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1 +#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0 +#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0 +#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0 +#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0 +#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1 +#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1 +#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1 +#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0 +#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0 +#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0 +#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0 +#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0 +#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1 +#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1 +#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1 +#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0 +#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0 +#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0 +#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0 +#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0 +#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0 +#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0 +#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0 +#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2 +#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0 +#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0 +#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0 +#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1 +#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1 +#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1 +#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0 +#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0 +#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0 +#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0 +#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0 +#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0 +#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0 +#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1 +#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0 +#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0 +#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0 +#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0 +#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0 +#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0 +#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0 +#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0 +#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0 +#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0 +#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0 +#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0 +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0 +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0 +#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0 +#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0 +#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1 +#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0 +#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0 +#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1 +#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0 +#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0 +#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0 +#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0 +#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0 +#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0 +#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0 +#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0 +#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0 +#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0 +#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0 +#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0 +#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0 +#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0 +#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0 +#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0 +#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0 +#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0 +#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0 +#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0 +#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0 +#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0 +#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0 +#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0 +#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0 +#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0 +#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0 +#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0 +#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0 +#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0 +#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0 +#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0 +#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0 +#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0 +#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0 +#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0 +#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0 +#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0 +#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0 +#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0 +#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0 +#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0 +#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0 +#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0 +#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0 +#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0 +#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0 +#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0 +#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0 +#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0 +#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0 +#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0 +#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0 +#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0 +#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0 +#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0 +#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0 +#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0 +#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0 +#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0 +#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0 +#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0 +#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1 +#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1 +#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0 +#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0 +#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0 +#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0 +#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0 +#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0 +#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0 +#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0 +#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0 +#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0 +#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0 +#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0 +#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0 +#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0 +#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0 +#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0 +#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0 +#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0 +#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0 +#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0 +#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0 +#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0 +#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0 +#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0 +#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0 +#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0 +#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0 +#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0 +#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0 +#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0 +#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0 +#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0 +#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0 +#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0 +#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0 +#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0 +#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0 +#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0 +#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1 +#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0 +#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0 +#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0 +#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0 +#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0 +#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0 +#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2 +#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0 +#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0 +#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0 +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0 +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0 +#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0 +#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0 +#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0 +#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0 +#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0 +#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2 +#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0 +#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0 +#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0 +#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2 +#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0 +#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0 +#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0 +#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0 +#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1 +#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0 +#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0 +#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0 +#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0 +#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1 +#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0 +#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0 +#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0 +#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0 +#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2 +#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0 +#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0 +#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0 +#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2 +#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2 +#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0 +#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0 +#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0 +#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0 +#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2 +#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0 +#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2 +#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0 +#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0 +#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0 +#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0 +#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0 +#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2 +#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0 +#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0 +#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0 +#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0 +#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0 +#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2 +#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0 +#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0 +#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0 +#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0 +#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0 +#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1 +#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0 +#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0 +#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0 +#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0 +#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0 +#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1 +#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0 +#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0 +#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0 +#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0 +#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0 +#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1 +#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0 +#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0 +#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2 +#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0 +#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2 +#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0 +#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2 +#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0 +#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3 +#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0 +#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2 +#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0 +#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2 +#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0 +#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1 +#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2 +#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0 +#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0 +#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1 +#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0 +#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1 +#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0 +#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1 +#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3 +#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0 +#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0 +#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0 +#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1 +#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0 +#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1 +#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0 +#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0 +#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1 +#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1 +#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0 +#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1 +#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0 +#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0 +#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0 +#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1 +#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0 +#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1 +#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0 +#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1 +#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0 +#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1 +#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0 +#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0 +#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0 +#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0 +#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1 +#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1 +#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0 +#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0 +#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0 +#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1 +#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1 +#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0 +#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1 +#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1 +#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0 +#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0 +#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0 +#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1 +#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0 +#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0 +#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2 +#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1 +#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0 +#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0 +#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0 +#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1 +#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1 +#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2 +#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1 +#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0 +#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0 +#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0 +#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1 +#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1 +#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0 +#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2 +#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1 +#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0 +#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0 +#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0 +#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0 +#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1 +#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3 +#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0 +#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1 +#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0 +#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0 +#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1 +#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4 +#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0 +#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1 +#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0 +#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1 +#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0 +#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0 +#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1 +#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0 +#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1 +#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0 +#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0 +#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1 +#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1 +#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1 +#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2 +#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1 +#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1 +#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1 +#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1 +#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1 +#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1 +#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0 +#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0 +#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0 +#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0 +#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1 +#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2 +#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0 +#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0 +#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1 +#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1 +#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0 +#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0 +#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1 +#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0 +#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0 +#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0 +#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1 +#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2 +#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0 +#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1 +#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0 +#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0 +#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1 +#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3 +#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1 +#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3 +#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1 +#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2 +#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2 +#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1 +#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0 +#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0 +#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2 +#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2 +#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1 +#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0 +#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0 +#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3 +#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2 +#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1 +#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0 +#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0 +#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3 +#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2 +#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1 +#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0 +#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0 +#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2 +#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2 +#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1 +#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0 +#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0 +#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0 +#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2 +#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2 +#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1 +#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0 +#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0 +#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0 +#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2 +#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2 +#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0 +#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0 +#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0 +#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0 +#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2 +#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2 +#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0 +#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0 +#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0 +#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0 +#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0 +#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0 +#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1 +#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0 +#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1 +#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0 +#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1 +#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3 +#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1 +#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3 +#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1 +#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5 +#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0 +#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0 +#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1 +#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0 +#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0 +#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3 +#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1 +#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4 +#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0 +#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0 +#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1 +#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2 +#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1 +#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3 +#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1 +#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0 +#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0 +#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0 +#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1 +#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0 +#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1 +#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3 +#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1 +#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0 +#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0 +#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0 +#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0 +#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0 +#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1 +#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2 +#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1 +#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0 +#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0 +#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0 +#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0 +#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0 +#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1 +#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2 +#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1 +#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0 +#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0 +#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0 +#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3 +#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0 +#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1 +#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1 +#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0 +#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0 +#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0 +#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0 +#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0 +#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1 +#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1 +#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0 +#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0 +#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0 +#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2 +#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1 +#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1 +#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0 +#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0 +#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0 +#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2 +#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4 +#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1 +#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1 +#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3 +#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0 +#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0 +#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3 +#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1 +#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1 +#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0 +#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5 +#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0 +#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3 +#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0 +#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1 +#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0 +#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0 +#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0 +#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4 +#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0 +#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2 +#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1 +#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0 +#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0 +#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0 +#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4 +#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1 +#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1 +#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0 +#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0 +#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0 +#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3 +#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1 +#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1 +#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0 +#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0 +#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3 +#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1 +#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1 +#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0 +#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0 +#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3 +#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1 +#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1 +#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0 +#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0 +#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3 +#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1 +#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1 +#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0 +#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0 +#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0 + +#endif /* __DTS_IMX35_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi new file mode 100644 index 000000000000..2d20e5541acc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2012 Steffen Trumtrar, Pengutronix +// +// based on imx27.dtsi + +#include "imx35-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &spi1; + spi1 = &spi2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1136jf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + avic: avic-interrupt-controller@68000000 { + compatible = "fsl,imx35-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x68000000 0x10000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + L2: cache-controller@30000000 { + compatible = "arm,l210-cache"; + reg = <0x30000000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + aips1: bus@43f00000 { + compatible = "fsl,aips", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + i2c1: i2c@43f80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; + reg = <0x43f80000 0x4000>; + clocks = <&clks 51>; + clock-names = "ipg_per"; + interrupts = <10>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; + reg = <0x43f84000 0x4000>; + clocks = <&clks 53>; + clock-names = "ipg_per"; + interrupts = <3>; + status = "disabled"; + }; + + uart1: serial@43f90000 { + compatible = "fsl,imx35-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + clocks = <&clks 9>, <&clks 70>; + clock-names = "ipg", "per"; + interrupts = <45>; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx35-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + clocks = <&clks 9>, <&clks 71>; + clock-names = "ipg", "per"; + interrupts = <32>; + status = "disabled"; + }; + + i2c2: i2c@43f98000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; + reg = <0x43f98000 0x4000>; + clocks = <&clks 52>; + clock-names = "ipg_per"; + interrupts = <4>; + status = "disabled"; + }; + + ssi1: ssi@43fa0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; + reg = <0x43fa0000 0x4000>; + interrupts = <11>; + clocks = <&clks 68>; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-cspi"; + reg = <0x43fa4000 0x4000>; + clocks = <&clks 35 &clks 35>; + clock-names = "ipg", "per"; + interrupts = <14>; + status = "disabled"; + }; + + kpp: kpp@43fa8000 { + compatible = "fsl,imx35-kpp", "fsl,imx21-kpp"; + reg = <0x43fa8000 0x4000>; + interrupts = <24>; + clocks = <&clks 56>; + status = "disabled"; + }; + + iomuxc: iomuxc@43fac000 { + compatible = "fsl,imx35-iomuxc"; + reg = <0x43fac000 0x4000>; + }; + }; + + spba: spba-bus@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x100000>; + ranges; + + uart3: serial@5000c000 { + compatible = "fsl,imx35-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + clocks = <&clks 9>, <&clks 72>; + clock-names = "ipg", "per"; + interrupts = <18>; + status = "disabled"; + }; + + spi2: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 36 &clks 36>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + fec: ethernet@50038000 { + compatible = "fsl,imx35-fec", "fsl,imx27-fec"; + reg = <0x50038000 0x4000>; + clocks = <&clks 46>, <&clks 8>; + clock-names = "ipg", "ahb"; + interrupts = <57>; + status = "disabled"; + }; + }; + + aips2: bus@53f00000 { + compatible = "fsl,aips", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x53f00000 0x100000>; + ranges; + + clks: ccm@53f80000 { + compatible = "fsl,imx35-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + gpt: timer@53f90000 { + compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; + reg = <0x53f90000 0x4000>; + interrupts = <29>; + clocks = <&clks 9>, <&clks 50>; + clock-names = "ipg", "per"; + }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + esdhc1: mmc@53fb4000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fb4000 0x4000>; + interrupts = <7>; + clocks = <&clks 9>, <&clks 8>, <&clks 43>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc2: mmc@53fb8000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fb8000 0x4000>; + interrupts = <8>; + clocks = <&clks 9>, <&clks 8>, <&clks 44>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc3: mmc@53fbc000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fbc000 0x4000>; + interrupts = <9>; + clocks = <&clks 9>, <&clks 8>, <&clks 45>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + audmux: audmux@53fc4000 { + compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; + reg = <0x53fc4000 0x4000>; + status = "disabled"; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: dma-controller@53fd4000 { + compatible = "fsl,imx35-sdma"; + reg = <0x53fd4000 0x4000>; + clocks = <&clks 9>, <&clks 65>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + interrupts = <34>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; + }; + + wdog: watchdog@53fdc000 { + compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 74>; + interrupts = <55>; + }; + + can1: can@53fe4000 { + compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fe4000 0x1000>; + clocks = <&clks 33>, <&clks 33>; + clock-names = "ipg", "per"; + interrupts = <43>; + status = "disabled"; + }; + + can2: can@53fe8000 { + compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fe8000 0x1000>; + clocks = <&clks 34>, <&clks 34>; + clock-names = "ipg", "per"; + interrupts = <44>; + status = "disabled"; + }; + + efuse@53ff0000 { + compatible = "fsl,imx35-iim"; + reg = <0x53ff0000 0x4000>; + interrupts = <19>; + clocks = <&clks 80>; + }; + + usbotg: usb@53ff4000 { + compatible = "fsl,imx35-usb", "fsl,imx27-usb"; + reg = <0x53ff4000 0x0200>; + interrupts = <37>; + clocks = <&clks 9>, <&clks 73>, <&clks 28>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usbhost1: usb@53ff4400 { + compatible = "fsl,imx35-usb", "fsl,imx27-usb"; + reg = <0x53ff4400 0x0200>; + interrupts = <35>; + clocks = <&clks 9>, <&clks 73>, <&clks 28>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@53ff4600 { + #index-cells = <1>; + compatible = "fsl,imx35-usbmisc"; + reg = <0x53ff4600 0x00f>; + }; + }; + + emi@80000000 { /* External Memory Interface */ + compatible = "fsl,emi", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x40000000>; + ranges; + + nfc: nand@bb000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx35-nand", "fsl,imx25-nand"; + reg = <0xbb000000 0x2000>; + clocks = <&clks 29>; + clock-names = ""; + interrupts = <33>; + status = "disabled"; + }; + + weim: weim@b8002000 { + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clks 0>; + compatible = "fsl,imx35-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + ranges = < + 0 0 0xa0000000 0x8000000 + 1 0 0xa8000000 0x8000000 + 2 0 0xb0000000 0x2000000 + 3 0 0xb2000000 0x2000000 + 4 0 0xb4000000 0x2000000 + 5 0 0xb6000000 0x2000000 + >; + status = "disabled"; + }; + }; + }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx50-evk.dts b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts new file mode 100644 index 000000000000..4ea5c23f181b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013 Greg Ungerer +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; +#include "imx50.dtsi" + +/ { + model = "Freescale i.MX50 Evaluation Kit"; + compatible = "fsl,imx50-evk", "fsl,imx50"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x80000000>; + }; +}; + +&cspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: m25p32@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p32", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "kernel"; + reg = <0x100000 0x300000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + imx50-evk { + pinctrl_cspi: cspigrp { + fsl,pins = < + MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 + MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 + MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 + MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 + MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX50_PAD_SSI_RXFS__FEC_MDC 0x80 + MX50_PAD_SSI_RXC__FEC_MDIO 0x80 + MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 + MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 + MX50_PAD_DISP_D2__FEC_RX_DV 0x80 + MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 + MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 + MX50_PAD_DISP_D5__FEC_TX_EN 0x80 + MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 + MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 + MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 + MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 + MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts new file mode 100644 index 000000000000..467db6b4ed7f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 Jonathan Neuschäfer +// +// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B. + +/dts-v1/; +#include "imx50.dtsi" +#include +#include + +/ { + model = "Kobo Aura (N514)"; + compatible = "kobo,aura", "fsl,imx50"; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-on { + label = "kobo_aura:orange:on"; + gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + key-power { + label = "Power Button"; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + event-hallsensor { + label = "Hallsensor"; + gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + event-frontlight { + label = "Frontlight"; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sd2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_reset>; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + }; + + sd2_vmmc: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_vmmc>; + regulator-name = "vmmc"; + states = <3300000 0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + max-frequency = <50000000>; + bus-width = <4>; + cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; + + /* External µSD card */ +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2>; + bus-width = <4>; + max-frequency = <50000000>; + disable-wp; + mmc-pwrseq = <&sd2_pwrseq>; + vmmc-supply = <&sd2_vmmc>; + status = "okay"; + + /* CyberTan WC121 SDIO WiFi (BCM43362) */ +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd3>; + bus-width = <8>; + non-removable; + max-frequency = <50000000>; + disable-wp; + status = "okay"; + + /* Internal eMMC */ +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@15 { + reg = <0x15>; + compatible = "elan,ektf2132"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + embedded-controller@43 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ec>; + compatible = "netronix,ntxec"; + reg = <0x43>; + system-power-controller; + interrupts-extended = <&gpio4 11 IRQ_TYPE_EDGE_FALLING>; + #pwm-cells = <2>; + }; +}; + +&iomuxc { + pinctrl_ec: ecgrp { + fsl,pins = < + MX50_PAD_CSPI_SS0__GPIO4_11 0x0 /* INT */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + MX50_PAD_CSPI_MISO__GPIO4_10 0x0 + MX50_PAD_SD2_D7__GPIO5_15 0x0 + MX50_PAD_KEY_ROW0__GPIO4_1 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd + MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd + MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd + MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX50_PAD_PWM1__GPIO6_24 0x0 + >; + }; + + pinctrl_sd1: sd1grp { + fsl,pins = < + MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 + MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 + MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 + MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 + MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 + MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 + + MX50_PAD_SD2_CD__GPIO5_17 0x0 + >; + }; + + pinctrl_sd2: sd2grp { + fsl,pins = < + MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 + MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 + MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 + MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 + MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 + MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 + >; + }; + + pinctrl_sd2_reset: sd2-resetgrp { + fsl,pins = < + MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 + >; + }; + + pinctrl_sd2_vmmc: sd2-vmmcgrp { + fsl,pins = < + MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 + >; + }; + + pinctrl_sd3: sd3grp { + fsl,pins = < + MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 + MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 + MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 + MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 + MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 + MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 + MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 + MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 + MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 + MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX50_PAD_CSPI_MOSI__GPIO4_9 0x0 + MX50_PAD_SD2_D5__GPIO5_13 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 + MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 + >; + }; + + pinctrl_usbphy: usbphygrp { + fsl,pins = < + MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbphy>; + vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h new file mode 100644 index 000000000000..5e6b30247543 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h @@ -0,0 +1,919 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Greg Ungerer + */ + +#ifndef __DTS_IMX50_PINFUNC_H +#define __DTS_IMX50_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 +#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 +#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 +#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 +#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 +#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 +#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 +#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 +#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 +#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 +#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 +#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 +#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 +#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 +#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 +#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 +#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 +#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 +#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 +#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 +#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 +#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 +#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 +#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 +#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 +#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 +#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 +#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 +#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 +#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 +#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 +#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 +#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 +#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 +#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 +#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 +#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 +#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 +#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 +#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 +#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 +#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 +#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 +#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 +#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 +#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 +#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 +#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 +#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 +#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 +#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 +#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 +#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 +#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 +#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 +#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 +#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 +#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 +#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 +#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 +#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 +#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 +#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 +#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 +#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 +#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 +#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 +#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 +#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 +#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 +#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 +#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 +#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 +#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 +#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 +#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 +#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 +#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 +#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 +#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 +#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 +#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 +#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 +#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 +#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 +#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 +#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 +#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 +#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 +#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 +#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 +#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 +#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 +#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 +#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 +#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 +#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 +#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 +#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 +#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 +#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 +#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 +#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 +#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 +#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 +#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 +#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 +#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 +#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 +#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 +#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 +#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 +#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 +#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 +#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 +#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 +#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 +#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 +#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 +#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 +#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 +#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 +#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 +#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 +#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 +#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 +#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 +#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 +#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 +#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 +#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 +#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 +#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 +#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 +#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 +#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 +#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 +#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 +#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 +#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 +#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 +#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 +#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 +#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 +#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 +#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 +#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 +#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 +#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 +#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 +#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 +#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 +#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 +#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 +#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 +#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 +#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 +#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 +#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 +#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 +#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 +#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 +#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 +#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 +#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 +#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 +#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 +#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 +#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 +#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 +#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 +#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 +#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 +#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 +#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 +#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 +#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 +#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 +#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 +#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 +#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 +#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 +#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 +#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 +#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 +#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 +#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 +#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 +#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 +#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 +#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 +#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 +#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 +#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 +#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 +#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 +#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 +#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 +#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 +#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 +#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 +#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 +#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 +#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 +#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 +#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 +#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 +#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 +#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 +#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 +#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 +#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 +#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 +#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 +#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 +#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 +#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 +#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 +#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 +#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 +#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 +#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 +#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 +#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 +#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 +#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 +#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 +#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 +#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 +#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 +#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 +#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 +#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 +#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 +#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 +#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 +#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 +#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 +#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 +#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 +#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 +#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 +#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 +#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 +#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 +#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 +#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 +#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 +#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 +#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 +#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 +#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 +#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 +#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 +#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 +#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 +#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 +#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 +#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 +#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 +#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 +#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 +#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 +#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 +#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 +#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 +#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 +#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 +#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 +#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 +#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 +#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 +#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 +#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 +#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 +#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 +#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 +#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 +#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 +#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 +#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 +#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 +#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 +#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 +#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 +#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 +#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 +#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 +#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 +#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 +#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 +#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 +#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 +#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 +#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 +#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 +#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 +#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 +#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 +#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 +#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 +#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 +#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 +#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 +#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 +#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 +#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 +#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 +#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 +#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 +#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 +#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 +#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 +#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 +#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 +#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 +#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 +#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 +#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 +#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 +#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 +#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 +#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 +#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 +#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 +#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 +#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 +#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 +#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 +#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 +#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 +#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 +#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 +#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 +#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 +#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 +#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 +#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 +#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 +#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 +#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 +#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 +#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 +#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 +#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 +#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 +#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 +#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 +#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 +#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 +#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 +#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 +#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 +#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 +#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 +#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 +#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 +#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 +#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 +#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 +#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 +#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 +#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 +#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 +#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 +#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 +#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 +#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 +#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 +#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 +#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 +#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 +#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 +#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 +#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 +#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 +#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 +#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 +#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 +#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 +#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 +#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 +#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 +#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 +#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 +#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 +#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 +#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 +#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 +#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 +#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 +#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 +#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 +#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 +#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 +#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 +#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 +#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 +#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 +#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 +#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 +#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 +#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 +#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 +#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 +#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 +#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 +#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 +#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 +#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 +#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 +#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 +#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 +#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 +#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 +#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 +#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 +#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 +#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 +#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 +#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 +#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 +#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 +#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 +#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 +#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 +#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 +#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 +#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 +#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 +#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 +#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 +#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 +#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 +#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 +#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 +#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 +#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 +#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 +#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 +#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 +#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 +#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 +#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 +#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 +#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 +#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 +#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 +#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 +#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 +#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 +#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 +#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 +#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 +#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 +#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 +#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 +#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 +#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 +#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 +#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 +#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 +#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 +#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 +#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 +#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 +#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 +#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 +#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 +#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 +#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 +#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 +#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 +#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 +#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 +#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 +#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 +#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 +#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 +#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 +#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 +#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 +#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 +#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 +#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 +#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 +#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 +#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 +#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 +#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 +#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 +#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 +#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 +#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 +#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 +#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 +#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 +#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 +#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 +#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 +#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 +#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 +#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 +#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 +#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 +#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 +#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 +#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 +#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 +#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 +#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 +#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 +#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 +#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 +#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 +#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 +#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 +#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 +#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 +#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 +#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 +#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 +#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 +#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 +#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 +#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 +#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 +#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 +#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 +#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 +#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 +#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 +#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 +#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 +#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 +#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 +#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 +#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 +#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 +#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 +#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 +#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 +#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 +#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 +#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 +#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 +#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 +#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 +#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 +#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 +#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 +#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 +#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 +#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 +#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 +#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 +#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 +#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 +#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 +#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 +#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 + +#endif /* __DTS_IMX50_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi new file mode 100644 index 000000000000..3d9a9f37f672 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx50.dtsi @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013 Greg Ungerer +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include "imx50-pinfunc.h" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + tzic: tz-interrupt-controller@fffc000 { + compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x0fffc000 0x4000>; + }; + + clocks { + ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + aips1: bus@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + spba-bus@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + esdhc1: mmc@50004000 { + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; + reg = <0x50004000 0x4000>; + interrupts = <1>; + clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc2: mmc@50008000 { + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; + reg = <0x50008000 0x4000>; + interrupts = <2>; + clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + uart3: serial@5000c000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi1: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx50-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + esdhc3: mmc@50020000 { + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc4: mmc@50024000 { + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + }; + + usbotg: usb@53f80000 { + compatible = "fsl,imx50-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usbh1: usb@53f80200 { + compatible = "fsl,imx50-usb", "fsl,imx27-usb"; + reg = <0x53f80200 0x0200>; + interrupts = <14>; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + dr_mode = "host"; + status = "disabled"; + }; + + gpio1: gpio@53f84000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 151 28>; + }; + + gpio2: gpio@53f88000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, + <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, + <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, + <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; + }; + + gpio3: gpio@53f8c000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 108 32>; + }; + + gpio4: gpio@53f90000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, + <&iomuxc 20 140 11>; + }; + + wdog1: watchdog@53f98000 { + compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + gpt: timer@53fa0000 { + compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + pwm1: pwm@53fb4000 { + #pwm-cells = <3>; + compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@53fb8000 { + #pwm-cells = <3>; + compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@53fbc000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + src: reset-controller@53fd0000 { + compatible = "fsl,imx50-src", "fsl,imx51-src"; + reg = <0x53fd0000 0x4000>; + interrupts = <75>; + #reset-cells = <1>; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx50-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + + gpio5: gpio@53fdc000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53fdc000 0x4000>; + interrupts = <103 104>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; + }; + + gpio6: gpio@53fe0000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53fe0000 0x4000>; + interrupts = <105 106>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; + }; + + i2c3: i2c@53fec000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; + reg = <0x53fec000 0x4000>; + interrupts = <64>; + clocks = <&clks IMX5_CLK_I2C3_GATE>; + status = "disabled"; + }; + + uart4: serial@53ff0000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + aips2: bus@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + uart5: serial@63f90000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + owire: owire@63fa4000 { + compatible = "fsl,imx50-owire", "fsl,imx21-owire"; + reg = <0x63fa4000 0x4000>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: spi@63fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sdma: dma-controller@63fb0000 { + compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; + }; + + cspi: spi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@63fc4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; + reg = <0x63fc4000 0x4000>; + interrupts = <63>; + clocks = <&clks IMX5_CLK_I2C2_GATE>; + status = "disabled"; + }; + + i2c1: i2c@63fc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; + reg = <0x63fc8000 0x4000>; + interrupts = <62>; + clocks = <&clks IMX5_CLK_I2C1_GATE>; + status = "disabled"; + }; + + ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + audmux: audmux@63fd0000 { + compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; + }; + + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-apf51.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51.dts new file mode 100644 index 000000000000..ba28ffe06fe2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-apf51.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Armadeus Systems - + * Copyright 2012 Laurent Cans + * + * Based on mx51-babbage.dts + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; +#include "imx51.dtsi" + +/ { + model = "Armadeus Systems APF51 module"; + compatible = "armadeus,imx51-apf51", "fsl,imx51"; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x20000000>; + }; + + clocks { + osc { + clock-frequency = <33554432>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + status = "okay"; +}; + +&iomuxc { + imx51-apf51 { + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts new file mode 100644 index 000000000000..b61d55ca1467 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Armadeus Systems - + */ + +/* APF51Dev is a docking board for the APF51 SOM */ +#include "imx51-apf51.dts" + +/ { + model = "Armadeus Systems APF51Dev docking/development board"; + compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; + + backlight { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + compatible = "gpio-backlight"; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + default-on; + }; + + disp1 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + + display-timings { + lw700 { + native-mode; + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + port { + display_in: endpoint { + remote-endpoint = <&ipu_di0_disp1>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-key { + label = "user"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,code = <256>; /* BTN_0 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "Heartbeat"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, + <&gpio3 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx51-apf51dev { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 + MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 + MX51_PAD_EIM_CS4__GPIO2_29 0x100 + MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 + MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 + MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 + MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 + MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 + MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed + MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; + }; +}; + +&ipu_di0_disp1 { + remote-endpoint = <&display_in>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts new file mode 100644 index 000000000000..a1f9c6a72275 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; +#include "imx51.dtsi" + +/ { + model = "Freescale i.MX51 Babbage Board"; + compatible = "fsl,imx51-babbage", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x20000000>; + }; + + ckih1 { + clock-frequency = <22579200>; + }; + + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_osc_gate: clk-osc-gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz_osc>; + clocks = <&clk_osc>; + #clock-cells = <0>; + enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + clk_audio: clk-audio { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz_audio>; + clocks = <&clk_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + + clk_usb: clk-usb { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz_usb>; + clocks = <&clk_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + display1: disp1 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp1>; + }; + }; + + port@1 { + reg = <1>; + + parallel_display_out: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; + }; + + display2: disp2 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp2>; + status = "disabled"; + display-timings { + native-mode = <&timing1>; + timing1: claawvga { + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <60>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp2>; + }; + }; + }; + + dvi-connector { + compatible = "dvi-connector"; + digital; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-encoder { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <¶llel_display_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-power { + label = "Power Button"; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-diagnostic { + label = "diagnostic"; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_hub_reset: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgreg>; + reg = <0>; + regulator-name = "hub_reset"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx51-babbage-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx51-babbage-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; + clocks = <&clk_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic: mc13892@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-boot-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + }; + + flash: at45db321d@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_audio>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + }; +}; + +&ipu_di0_disp1 { + remote-endpoint = <&display0_in>; +}; + +&ipu_di1_disp2 { + remote-endpoint = <&display1_in>; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 3, KEY_HOME) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(1, 3, KEY_VOLUMEUP) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + MATRIX_KEY(3, 0, KEY_F1) + MATRIX_KEY(3, 1, KEY_F2) + MATRIX_KEY(3, 2, KEY_F3) + MATRIX_KEY(3, 3, KEY_POWER) + >; + status = "okay"; +}; + +&pmu { + secure-reg-access; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_hub_reset>; + fsl,usbphy = <&usbphy1>; + phy_type = "ulpi"; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb_reg>; +}; + +&usbotg { + dr_mode = "otg"; + disable-over-current; + phy_type = "utmi_wide"; + status = "okay"; +}; + +&iomuxc { + imx51-babbage { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 + >; + }; + + pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 + >; + }; + + pinctrl_clk26mhz_osc: clk26mhzoscgrp { + fsl,pins = < + MX51_PAD_DI1_PIN12__GPIO3_1 0x85 + >; + }; + + pinctrl_clk26mhz_usb: clk26mhzusbgrp { + fsl,pins = < + MX51_PAD_EIM_D17__GPIO2_1 0x85 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_GPIO1_0__GPIO1_0 0x100 + MX51_PAD_GPIO1_1__GPIO1_1 0x100 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ + MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 + MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 + MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 + MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 + MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX51_PAD_EIM_A27__GPIO2_21 0x5 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX51_PAD_EIM_D22__GPIO2_6 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed + MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; + + pinctrl_ipu_disp2: ipudisp2grp { + fsl,pins = < + MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 + MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 + MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 + MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 + MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 + MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 + MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 + MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 + MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 + MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 + MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 + MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 + MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 + MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 + MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 + MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 + MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 + MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + MX51_PAD_DI_GP4__DI2_PIN15 0x5 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 + MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 + MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 + MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 + MX51_PAD_KEY_COL0__KEY_COL0 0xe8 + MX51_PAD_KEY_COL1__KEY_COL1 0xe8 + MX51_PAD_KEY_COL2__KEY_COL2 0xe8 + MX51_PAD_KEY_COL3__KEY_COL3 0xe8 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + MX51_PAD_EIM_D27__UART3_RTS 0x1c5 + MX51_PAD_EIM_D24__UART3_CTS 0x1c5 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 + >; + }; + + pinctrl_usbh1reg: usbh1reggrp { + fsl,pins = < + MX51_PAD_EIM_D21__GPIO2_5 0x85 + >; + }; + + pinctrl_usbotgreg: usbotgreggrp { + fsl,pins = < + MX51_PAD_GPIO1_7__GPIO1_7 0x85 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts new file mode 100644 index 000000000000..10cae7c3a879 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +#include "imx51-digi-connectcore-som.dtsi" + +/ { + model = "Digi ConnectCore CC(W)-MX51 JSK"; + compatible = "digi,connectcore-ccxmx51-jsk", + "digi,connectcore-ccxmx51-som", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; +}; + +&esdhc1 { + status = "okay"; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire>; + status = "okay"; +}; + +&pmic { + fsl,mc13xxx-uses-rtc; + + regulators { + vcoincell_reg: vcoincell { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + imx51-digi-connectcore-jsk { + pinctrl_owire: owiregrp { + fsl,pins = < + MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi new file mode 100644 index 000000000000..f0809a16a2ce --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan + */ + +/dts-v1/; +#include "imx51.dtsi" + +/ { + model = "Digi ConnectCore CC(W)-MX51"; + compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x08000000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13892@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mc13892>; + compatible = "fsl,mc13892"; + spi-max-frequency = <16000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1275000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { }; + + viohi_reg: viohi { + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + gpo2_reg: gpo2 { }; + + gpo3_reg: gpo3 { }; + + gpo4_reg: gpo4 { }; + + pwgt2spi_reg: pwgt2spi { + regulator-always-on; + }; + }; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + max-frequency = <50000000>; + bus-width = <1>; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cap-sdio-irq; + wakeup-source; + keep-power-in-suspend; + max-frequency = <50000000>; + no-1-8-v; + non-removable; + vmmc-supply = <&gpo4_reg>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-supply = <&gpo3_reg>; + /* Pins shared with LCD2, keep status disabled */ +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mma7455l@1d { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mma7455l>; + compatible = "fsl,mma7455l"; + reg = <0x1d>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi_wide"; + disable-over-current; + vbus-supply = <&swbst_reg>; + /* Device role is not known, keep status disabled */ +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + lan9221: ethernet@5,0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lan9221>; + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0x00000000 0x1000>; + fsl,weim-cs-timing = < + 0x00420081 0x00000000 + 0x32260000 0x00000000 + 0x72080f00 0x00000000 + >; + clocks = <&clks IMX5_CLK_DUMMY>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + vdd33a-supply = <&gpo2_reg>; + vddvario-supply = <&gpo2_reg>; + }; +}; + +&iomuxc { + imx51-digi-connectcore-som { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed + MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed + MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 + MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 + MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 + MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 + MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 + MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 + MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 + MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 + MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 + MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 + MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 + MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 + MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 + MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 + MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 + >; + }; + + pinctrl_lan9221: lan9221grp { + fsl,pins = < + MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ + >; + }; + + pinctrl_mc13892: mc13892grp { + fsl,pins = < + MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ + >; + }; + + pinctrl_mma7455l: mma7455lgrp { + fsl,pins = < + MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ + MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 + MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 + MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 + MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 + MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 + MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 + MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 + MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 + MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 + MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 + MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 + MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 + MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 + MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 + MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 + MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 + MX51_PAD_EIM_A16__EIM_A16 0x80000000 + MX51_PAD_EIM_A17__EIM_A17 0x80000000 + MX51_PAD_EIM_A18__EIM_A18 0x80000000 + MX51_PAD_EIM_A19__EIM_A19 0x80000000 + MX51_PAD_EIM_A20__EIM_A20 0x80000000 + MX51_PAD_EIM_A21__EIM_A21 0x80000000 + MX51_PAD_EIM_A22__EIM_A22 0x80000000 + MX51_PAD_EIM_A23__EIM_A23 0x80000000 + MX51_PAD_EIM_A24__EIM_A24 0x80000000 + MX51_PAD_EIM_A25__EIM_A25 0x80000000 + MX51_PAD_EIM_A26__EIM_A26 0x80000000 + MX51_PAD_EIM_A27__EIM_A27 0x80000000 + MX51_PAD_EIM_D16__EIM_D16 0x80000000 + MX51_PAD_EIM_D17__EIM_D17 0x80000000 + MX51_PAD_EIM_D18__EIM_D18 0x80000000 + MX51_PAD_EIM_D19__EIM_D19 0x80000000 + MX51_PAD_EIM_D20__EIM_D20 0x80000000 + MX51_PAD_EIM_D21__EIM_D21 0x80000000 + MX51_PAD_EIM_D22__EIM_D22 0x80000000 + MX51_PAD_EIM_D23__EIM_D23 0x80000000 + MX51_PAD_EIM_D24__EIM_D24 0x80000000 + MX51_PAD_EIM_D25__EIM_D25 0x80000000 + MX51_PAD_EIM_D26__EIM_D26 0x80000000 + MX51_PAD_EIM_D27__EIM_D27 0x80000000 + MX51_PAD_EIM_D28__EIM_D28 0x80000000 + MX51_PAD_EIM_D29__EIM_D29 0x80000000 + MX51_PAD_EIM_D30__EIM_D30 0x80000000 + MX51_PAD_EIM_D31__EIM_D31 0x80000000 + MX51_PAD_EIM_OE__EIM_OE 0x80000000 + MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 + MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 + MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi new file mode 100644 index 000000000000..c2a929ba8ceb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +#include "imx51.dtsi" + +/ { + model = "Eukrea CPUIMX51"; + compatible = "eukrea,cpuimx51", "fsl,imx51"; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x10000000>; /* 256M */ + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tsc2007: tsc2007@49 { + compatible = "ti,tsc2007"; + gpios = <&gpio4 0 1>; + interrupt-parent = <&gpio4>; + interrupts = <0x0 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_1>; + reg = <0x49>; + ti,x-plate-ohms = <180>; + }; +}; + +&iomuxc { + imx51-eukrea { + pinctrl_tsc2007_1: tsc2007grp-1 { + fsl,pins = < + MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 + MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed + MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed + >; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts new file mode 100644 index 000000000000..b6d931e96a8f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + */ + +/dts-v1/; +#include "imx51-eukrea-cpuimx51.dtsi" +#include + +/ { + model = "Eukrea CPUIMX51"; + compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; + + clocks { + clk24M: can_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys_1>; + + button-1 { + label = "BP1"; + gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + linux,code = <256>; + wakeup-source; + linux,input-type = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "CAN_RST"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx51-eukrea-tlv320aic23"; + ssi-controller = <&ssi2>; + fsl,mux-int-port = <2>; + fsl,mux-ext-port = <3>; + }; + + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + #phy-cells = <0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk24M>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_can>; + }; +}; + +&i2c1 { + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&iomuxc { + imx51-eukrea { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 + >; + }; + + + pinctrl_can: cangrp { + fsl,pins = < + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ + MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_uart3_rtscts: uart3rtsctsgrp { + fsl,pins = < + MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 + MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 + >; + }; + + pinctrl_backlight_1: backlightgrp-1 { + fsl,pins = < + MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 + >; + }; + + pinctrl_esdhc1_cd: esdhc1_cd { + fsl,pins = < + MX51_PAD_GPIO1_0__GPIO1_0 0xd5 + >; + }; + + pinctrl_gpiokeys_1: gpiokeysgrp-1 { + fsl,pins = < + MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 + >; + }; + + pinctrl_gpioled: gpioledgrp-1 { + fsl,pins = < + MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 + >; + }; + + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { + fsl,pins = < + MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 + >; + }; + }; +}; + +&ssi2 { + codec-handle = <&tlv320aic23>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + phy_type = "ulpi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + phy_type = "utmi_wide"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h new file mode 100644 index 000000000000..910e0ec50ef3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h @@ -0,0 +1,768 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX51_PINFUNC_H +#define __DTS_IMX51_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 +#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 +#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 +#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 +#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 +#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 +#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 +#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 +#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 +#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 +#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 +#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 +#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 +#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 +#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 +#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 +#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 +#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 +#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 +#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 +#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 +#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 +#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 +#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 +#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 +#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 +#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 +#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 +#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 +#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 +#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 +#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 +#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 +#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 +#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 +#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 +#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 +#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 +#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 +#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 +#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 +#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 +#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 +#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 +#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 +#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 +#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 +#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 +#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 +#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 +#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 +#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 +#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 +#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 +#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 +#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 +#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 +#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 +#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 +#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 +#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 +#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 +#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 +#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 +#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 +#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 +#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 +#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 +#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 +#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 +#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 +#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 +#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 +#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 +#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 +#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 +#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 +#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 +#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 +#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 +#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 +#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 +#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 +#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 +#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 +#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 +#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 +#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 +#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 +#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 +#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 +#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 +#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 +#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 +#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 +#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 +#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 +#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 +#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 +#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 +#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 +#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 +#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 +#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 +#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 +#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 +#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 +#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 +#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 +#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 +#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 +#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 +#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 +#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 +#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 +#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 +#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 +#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 +#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 +#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 +#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 +#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 +#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 +#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 +#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 +#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 +#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 +#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 +#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 +#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 +#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 +#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 +#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 +#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 +#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 +#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 +#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 +#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 +#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 +#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 +#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 +#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 +#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 +#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 +#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 +#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 +#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 +#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 +#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 +#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 +#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 +#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 +#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 +#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 +#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 +#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 +#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 +#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 +#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 +#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 +#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 +#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 +#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 +#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 +#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 +#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 +#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 +#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 +#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 +#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 +#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 +#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 +#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 +#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 +#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 +#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 +#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 +#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 +#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 +#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 +#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 +#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 +#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 +#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 +#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 +#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 +#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 +#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 +#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 +#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 +#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 +#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 +#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 +#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 +#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 +#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 +#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 +#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 +#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 +#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 +#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 +#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 +#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 +#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 +#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 +#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 +#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 +#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 +#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 +#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 +#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 +#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 +#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 +#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 +#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 +#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 +#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 +#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 +#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 +#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 +#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 +#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 +#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 +#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 +#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 +#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 +#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 +#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 +#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 +#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 +#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 +#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 +#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 +#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 +#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 +#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 +#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 +#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 +#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 +#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 +#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 +#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 +#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 +#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 +#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 +#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 +#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 +#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 +#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 +#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 +#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 +#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 +#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 +#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 +#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 +#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 +#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 +#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 +#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 +#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 +#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 +#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 +#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 +#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 +#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 +#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 +#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 +#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 +#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 +#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 +#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 +#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 +#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 +#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 +#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 +#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 +#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 +#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 +#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 +#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 +#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 +#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 +#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 +#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 +#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 +#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 +#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 +#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 +#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 +#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 +#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 +#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 +#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 +#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 +#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 +#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 +#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 +#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 +#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 +#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 +#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 +#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 +#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 +#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 +#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 +#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 +#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 +#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 +#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 +#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 +#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 +#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 +#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 +#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 +#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 +#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 +#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 +#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 +#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 +#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 +#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 +#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 +#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 +#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 +#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 +#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 +#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 +#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 +#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 +#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 +#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 +#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 +#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 +#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 +#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 +#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 +#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 +#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 +#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 +#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 +#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 +#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 +#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 +#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 +#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 +#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 +#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 +#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 +#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 +#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 +#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 +#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 +#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 +#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 +#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 +#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 +#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 +#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 +#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 +#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 +#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 +#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 +#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 +#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 +#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 +#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 +#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 +#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 +#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 +#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 +#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 +#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 +#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 +#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 +#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 +#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 +#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 +#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 +#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 +#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 +#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 +#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 +#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 +#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 +#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 +#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 +#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 +#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 +#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 +#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 +#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 +#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 +#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 +#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 +#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 +#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 +#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 +#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 +#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 +#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 +#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 +#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 +#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 +#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 +#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 +#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 +#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 +#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 +#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 +#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 +#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 +#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 +#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 +#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 +#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 +#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 +#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 +#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 +#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 +#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 +#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 +#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 +#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 +#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 +#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 +#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 +#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 +#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 +#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 +#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 +#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 +#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 +#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 +#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 +#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 +#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 +#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 +#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 +#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 +#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 +#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 +#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 +#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 +#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 +#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 +#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 +#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 +#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 +#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 +#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 +#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 +#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 +#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 +#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 +#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 +#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 +#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 +#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 +#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 +#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 +#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 +#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 +#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 +#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 +#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 +#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 +#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 +#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 +#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 +#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 +#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 +#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 +#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 +#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 +#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 +#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 +#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 +#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 +#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 + +#endif /* __DTS_IMX51_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts new file mode 100644 index 000000000000..f7408722d68a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -0,0 +1,331 @@ +/* + * Copyright 2015 Savoir-faire Linux + * + * This device tree is based on imx51-babbage.dts + * + * Licensed under the X11 license or the GPL v2 (or later) + */ + +/dts-v1/; +#include "imx51.dtsi" + +/ { + model = "Technologic Systems TS-4800"; + compatible = "technologic,imx51-ts4800", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x10000000>; + }; + + clocks { + ckih1 { + clock-frequency = <22579200>; + }; + + ckih2 { + clock-frequency = <24576000>; + }; + }; + + backlight_reg: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_lcd>; + regulator-name = "enable_lcd_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 78770>; + brightness-levels = <0 150 200 255>; + default-brightness-level = <1>; + power-supply = <&backlight_reg>; + }; + + display1: disp1 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + + display-timings { + 800x480p60 { + native-mode; + clock-frequency = <30066000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <50>; + hback-porch = <70>; + hsync-len = <50>; + vback-porch = <0>; + vfront-porch = <0>; + vsync-len = <50>; + }; + }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp1>; + }; + }; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&ipu_di0_disp1 { + remote-endpoint = <&display0_in>; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_backlight>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + fpga@0 { + compatible = "simple-bus"; + fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 + 0x00000000 0x1c092480 0x00000000>; + reg = <0 0x0000000 0x1d000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x1d000>; + + syscon: syscon@10000 { + compatible = "syscon", "simple-mfd"; + reg = <0x10000 0x3d>; + reg-io-width = <2>; + + wdt { + compatible = "technologic,ts4800-wdt"; + syscon = <&syscon 0xe>; + }; + }; + + touchscreen@12000 { + compatible = "technologic,ts4800-ts"; + reg = <0x12000 0x1000>; + syscon = <&syscon 0x10 6>; + }; + + fpga_irqc: fpga-irqc@15000 { + compatible = "technologic,ts4800-irqc"; + reg = <0x15000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_interrupt_fpga>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + can@1a000 { + compatible = "technologic,sja1000"; + reg = <0x1a000 0x100>; + interrupt-parent = <&fpga_irqc>; + interrupts = <1>; + reg-io-width = <2>; + nxp,tx-output-config = <0x06>; + nxp,external-clock-frequency = <24000000>; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + >; + }; + + pinctrl_enable_lcd: enablelcdgrp { + fsl,pins = < + MX51_PAD_CSI2_D12__GPIO4_9 0x1c5 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_GPIO1_0__GPIO1_0 0x100 + MX51_PAD_GPIO1_1__GPIO1_1 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 + MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 + MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 + MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4 + MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_interrupt_fpga: fpgaicgrp { + fsl,pins = < + MX51_PAD_EIM_D27__GPIO2_9 0xe5 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + MX51_PAD_DI_GP4__DI2_PIN15 0x5 + >; + }; + + pinctrl_pwm_backlight: backlightgrp { + fsl,pins = < + MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX51_PAD_EIM_DTACK__EIM_DTACK 0x85 + MX51_PAD_EIM_CS0__EIM_CS0 0x0 + MX51_PAD_EIM_CS1__EIM_CS1 0x0 + MX51_PAD_EIM_EB0__EIM_EB0 0x85 + MX51_PAD_EIM_EB1__EIM_EB1 0x85 + MX51_PAD_EIM_OE__EIM_OE 0x85 + MX51_PAD_EIM_LBA__EIM_LBA 0x85 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts new file mode 100644 index 000000000000..5d4b29d76585 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts @@ -0,0 +1,894 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2017 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "imx51.dtsi" +#include + +/ { + model = "ZII RDU1 Board"; + compatible = "zii,imx51-rdu1", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0>; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + rtc0 = &ds1341; + }; + + clk_26M_osc: 26M_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_26M_osc_gate: 26M_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz>; + clocks = <&clk_26M_osc>; + #clock-cells = <0>; + enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + clk_26M_usb: usbhost_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbgate26mhz>; + clocks = <&clk_26M_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + }; + + clk_26M_snd: snd_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sndgate26mhz>; + clocks = <&clk_26M_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + disp0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu_di0_disp1>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + /* no compatible here, bootloader will patch in correct one */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <®_3p3v>; + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + i2c_gpio: i2c-gpio { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swi2c>; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <50>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clk_26M_snd>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + #sound-dai-cells = <0>; + }; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiospi0>; + status = "okay"; + + sck-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + + eeprom@0 { + compatible = "eeprom-93xx46"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cs-high; + data-size = <8>; + }; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "rev-mii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "netaux"; + }; + + port@3 { + reg = <3>; + label = "netright"; + }; + + port@4 { + reg = <4>; + label = "netleft"; + }; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Front"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "TPA6130A2 HPLEFT", + "Headphone Jack", "TPA6130A2 HPRIGHT"; + simple-audio-card,aux-devs = <&hpa1>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk_26M_snd>; + }; + }; + + usbh1phy: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1phy>; + clocks = <&clk_26M_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; + }; + + usbh2phy: usbphy2 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2phy>; + clocks = <&clk_26M_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCSEL(2) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled0@3 { + reg = <3>; + label = "system:green:status"; + linux,default-trigger = "default-on"; + }; + + sysled1@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-1-8-v; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-supply = <&vgen3_reg>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "hp-amp-shutdown-b", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + unused-sd3-wp-hog { + /* + * See pinctrl_esdhc1 below for more details on this + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + Vdd-supply = <®_3p3v>; + sound-name-prefix = "TPA6130A2"; + }; + + ds1341: rtc@68 { + compatible = "dallas,ds1341"; + reg = <0x68>; + }; + + /* touch nodes default disabled, bootloader will enable the right one */ + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + touchscreen@4c { + compatible = "atmel,maxtouch"; + reg = <0x4c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <2>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + syna,sensor-type = <1>; + }; + }; + +}; + +&ipu_di0_disp1 { + remote-endpoint = <&display_in>; +}; + +&pmu { + secure-reg-access; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-rdu1"; + current-speed = <38400>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + backlight { + compatible = "zii,rave-sp-backlight"; + }; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + + eeprom@ae { + compatible = "zii,rave-sp-eeprom"; + reg = <0xae 0x200>; + zii,eeprom-name = "switch-eeprom"; + /* + * Not all RDU1s have this functionality, so we + * rely on the bootloader to enable this + */ + status = "disabled"; + }; + }; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + dr_mode = "host"; + phy_type = "ulpi"; + fsl,usbphy = <&usbh1phy>; + disable-over-current; + maximum-speed = "full-speed"; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + fsl,usbphy = <&usbh2phy>; + disable-over-current; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb_reg>; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX51_PAD_GPIO1_9__GPIO1_9 0x5e + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 + >; + }; + + pinctrl_clk26mhz: clk26mhzgrp { + fsl,pins = < + MX51_PAD_DI1_PIN12__GPIO3_1 0x85 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + /* + * GPIO1_1 is not directly used by eSDHC1 in + * any capacity, but earlier versions of RDU1 + * used that pin as WP GPIO for eSDHC3 and + * because of that that pad has an external + * pull-up resistor. This is problematic + * because out of reset the pad is configured + * as ALT0 which serves as SD1_WP, which, when + * pulled high by and external pull-up, will + * inhibit execution of any write request to + * attached eMMC device. + * + * To avoid this problem we configure the pad + * to ALT1/GPIO and avoid driving SD1_WP + * signal high. + */ + MX51_PAD_GPIO1_1__GPIO1_1 0x0000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 + MX51_PAD_EIM_CS5__FEC_CRS 0x180 + MX51_PAD_NANDF_RB2__FEC_COL 0x2180 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 + MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_EIM_A20__GPIO2_14 0x85 + >; + }; + + pinctrl_gpiospi0: gpiospi0grp { + fsl,pins = < + MX51_PAD_CSI2_D18__GPIO4_11 0x85 + MX51_PAD_CSI2_D19__GPIO4_12 0x85 + MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 + MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 + >; + }; + + pinctrl_sndgate26mhz: sndgate26mhzgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 + >; + }; + + pinctrl_swi2c: swi2cgrp { + fsl,pins = < + MX51_PAD_GPIO1_2__GPIO1_2 0xc5 + MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 + MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX51_PAD_CSI1_D8__GPIO3_12 0x04 + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0xc5 + MX51_PAD_UART2_TXD__UART2_TXD 0xc5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usbgate26mhz: usbgate26mhzgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_STP__USBH1_STP 0x0 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 + >; + }; + + pinctrl_usbh1phy: usbh1phygrp { + fsl,pins = < + MX51_PAD_NANDF_D0__GPIO4_8 0x85 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX51_PAD_EIM_A26__USBH2_STP 0x0 + MX51_PAD_EIM_A24__USBH2_CLK 0x0 + MX51_PAD_EIM_A25__USBH2_DIR 0x0 + MX51_PAD_EIM_A27__USBH2_NXT 0x0 + MX51_PAD_EIM_D16__USBH2_DATA0 0x0 + MX51_PAD_EIM_D17__USBH2_DATA1 0x0 + MX51_PAD_EIM_D18__USBH2_DATA2 0x0 + MX51_PAD_EIM_D19__USBH2_DATA3 0x0 + MX51_PAD_EIM_D20__USBH2_DATA4 0x0 + MX51_PAD_EIM_D21__USBH2_DATA5 0x0 + MX51_PAD_EIM_D22__USBH2_DATA6 0x0 + MX51_PAD_EIM_D23__USBH2_DATA7 0x0 + >; + }; + + pinctrl_usbh2phy: usbh2phygrp { + fsl,pins = < + MX51_PAD_NANDF_D1__GPIO4_7 0x85 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts new file mode 100644 index 000000000000..625f9ac671ae --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU2 Mezz Board"; + compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0>; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port4"; + }; + + port@1 { + reg = <1>; + label = "port5"; + }; + + port@2 { + reg = <2>; + label = "port6"; + }; + + port@3 { + reg = <3>; + label = "port7"; + }; + + port@4 { + reg = <4>; + phy-mode = "rev-mii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "mezz2esb"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-supply = <&vgen3_reg>; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-mezz"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&vpu { + status = "disabled"; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + MX51_PAD_EIM_A20__GPIO2_14 0x0085 + MX51_PAD_EIM_A21__GPIO2_15 0x00e5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_EIM_D22__GPIO2_6 0x100 + MX51_PAD_EIM_D23__GPIO2_7 0x100 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts new file mode 100644 index 000000000000..19a3b142c964 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU3 ESB board"; + compatible = "zii,imx51-scu3-esb", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "scu2scu"; + }; + + port@4 { + reg = <4>; + label = "esb2host"; + }; + + port@5 { + reg = <5>; + label = "esb2mezz"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + phy-mode = "mii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&ipu { + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-esb"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&vpu { + status = "disabled"; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 + MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi new file mode 100644 index 000000000000..ba92a3ea6872 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx51.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include "imx51-pinfunc.h" +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &i2c1; + i2c1 = &i2c2; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + tzic: tz-interrupt-controller@e0000000 { + compatible = "fsl,imx51-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe0000000 0x4000>; + }; + + clocks { + ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + ckih2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0>; + clock-latency = <62500>; + clocks = <&clks IMX5_CLK_CPU_PODF>; + clock-names = "cpu"; + operating-points = < + 166000 1000000 + 600000 1050000 + 800000 1100000 + >; + voltage-tolerance = <5>; + }; + }; + + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + iram: sram@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 0x20000>; + ranges = <0 0x1ffe0000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + gpu: gpu@30000000 { + compatible = "amd,imageon-200.1", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; + + ipu: ipu@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ipu"; + reg = <0x40000000 0x20000000>; + interrupts = <11 10>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; + clock-names = "bus", "di0", "di1"; + resets = <&src 2>; + + ipu_csi0: port@0 { + reg = <0>; + }; + + ipu_csi1: port@1 { + reg = <1>; + }; + + ipu_di0: port@2 { + reg = <2>; + + ipu_di0_disp1: endpoint { + }; + }; + + ipu_di1: port@3 { + reg = <3>; + + ipu_di1_disp2: endpoint { + }; + }; + }; + + aips1: bus@70000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x10000000>; + ranges; + + spba-bus@70000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x40000>; + ranges; + + esdhc1: mmc@70004000 { + compatible = "fsl,imx51-esdhc"; + reg = <0x70004000 0x4000>; + interrupts = <1>; + clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc2: mmc@70008000 { + compatible = "fsl,imx51-esdhc"; + reg = <0x70008000 0x4000>; + interrupts = <2>; + clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + uart3: serial@7000c000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x7000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 43 5 1>, <&sdma 44 5 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi1: spi@70010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x70010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@70014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; + reg = <0x70014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + esdhc3: mmc@70020000 { + compatible = "fsl,imx51-esdhc"; + reg = <0x70020000 0x4000>; + interrupts = <3>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc4: mmc@70024000 { + compatible = "fsl,imx51-esdhc"; + reg = <0x70024000 0x4000>; + interrupts = <4>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + }; + + aipstz1: bridge@73f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x73f00000 0x60>; + }; + + usbotg: usb@73f80000 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usbh1: usb@73f80200 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80200 0x0200>; + interrupts = <14>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 1>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh2: usb@73f80400 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80400 0x0200>; + interrupts = <16>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh3: usb@73f80600 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80600 0x0200>; + interrupts = <17>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@73f80800 { + #index-cells = <1>; + compatible = "fsl,imx51-usbmisc"; + reg = <0x73f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + }; + + gpio1: gpio@73f84000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@73f88000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@73f8c000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@73f90000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@73f94000 { + compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; + reg = <0x73f94000 0x4000>; + interrupts = <60>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: watchdog@73f98000 { + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + wdog2: watchdog@73f9c000 { + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f9c000 0x4000>; + interrupts = <59>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + gpt: timer@73fa0000 { + compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; + reg = <0x73fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + iomuxc: iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc"; + reg = <0x73fa8000 0x4000>; + }; + + pwm1: pwm@73fb4000 { + #pwm-cells = <3>; + compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; + reg = <0x73fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@73fb8000 { + #pwm-cells = <3>; + compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; + reg = <0x73fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@73fbc000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@73fc0000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 16 4 1>, <&sdma 17 4 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + src: reset-controller@73fd0000 { + compatible = "fsl,imx51-src"; + reg = <0x73fd0000 0x4000>; + interrupts = <75>; + #reset-cells = <1>; + }; + + clks: ccm@73fd4000{ + compatible = "fsl,imx51-ccm"; + reg = <0x73fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + }; + + aips2: bus@80000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x10000000>; + ranges; + + aipstz2: bridge@83f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x83f00000 0x60>; + }; + + iim: efuse@83f98000 { + compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon"; + reg = <0x83f98000 0x4000>; + interrupts = <69>; + clocks = <&clks IMX5_CLK_IIM_GATE>; + }; + + tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; + }; + + owire: owire@83fa4000 { + compatible = "fsl,imx51-owire", "fsl,imx21-owire"; + reg = <0x83fa4000 0x4000>; + interrupts = <88>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: spi@83fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x83fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sdma: dma-controller@83fb0000 { + compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; + reg = <0x83fb0000 0x4000>; + interrupts = <6>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; + }; + + cspi: spi@83fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; + reg = <0x83fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@83fc4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; + reg = <0x83fc4000 0x4000>; + interrupts = <63>; + clocks = <&clks IMX5_CLK_I2C2_GATE>; + status = "disabled"; + }; + + i2c1: i2c@83fc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; + reg = <0x83fc8000 0x4000>; + interrupts = <62>; + clocks = <&clks IMX5_CLK_I2C1_GATE>; + status = "disabled"; + }; + + ssi1: ssi@83fcc000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; + reg = <0x83fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + audmux: audmux@83fd0000 { + compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; + reg = <0x83fd0000 0x4000>; + clocks = <&clks IMX5_CLK_DUMMY>; + clock-names = "audmux"; + status = "disabled"; + }; + + m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; + }; + + weim: weim@83fda000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx51-weim"; + reg = <0x83fda000 0x1000>; + clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; + ranges = < + 0 0 0xb0000000 0x08000000 + 1 0 0xb8000000 0x08000000 + 2 0 0xc0000000 0x08000000 + 3 0 0xc8000000 0x04000000 + 4 0 0xcc000000 0x02000000 + 5 0 0xce000000 0x02000000 + >; + status = "disabled"; + }; + + nfc: nand@83fdb000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx51-nand"; + reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; + interrupts = <8>; + clocks = <&clks IMX5_CLK_NFC_GATE>; + status = "disabled"; + }; + + pata: pata@83fe0000 { + compatible = "fsl,imx51-pata", "fsl,imx27-pata"; + reg = <0x83fe0000 0x4000>; + interrupts = <70>; + clocks = <&clks IMX5_CLK_PATA_GATE>; + status = "disabled"; + }; + + ssi3: ssi@83fe8000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; + reg = <0x83fe8000 0x4000>; + interrupts = <96>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + fec: ethernet@83fec000 { + compatible = "fsl,imx51-fec", "fsl,imx27-fec"; + reg = <0x83fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + vpu: vpu@83ff4000 { + compatible = "fsl,imx51-vpu", "cnm,codahx4"; + reg = <0x83ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&iram>; + }; + + sahara: crypto@83ff8000 { + compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; + reg = <0x83ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ard.dts b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts new file mode 100644 index 000000000000..23a7492e2929 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; +#include +#include "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Automotive Reference Design Board"; + compatible = "fsl,imx53-ard", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x40000000>; + }; + + eim-cs1@f4000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eim-bus", "simple-bus"; + reg = <0xf4000000 0x3ff0000>; + ranges; + + ethernet@f4000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0xf4000000 0x2000000>; + phy-mode = "mii"; + interrupt-parent = <&gpio2>; + interrupts = <31 0x8>; + reg-io-width = <4>; + /* + * VDD33A and VDDVARIO of LAN9220 are supplied by + * SW4_3V3 of LTC3589. Before the regulator driver + * for this PMIC is available, we use a fixed dummy + * 3V3 regulator to get LAN9220 driver probing work. + */ + vdd33a-supply = <®_3p3v>; + vddvario-supply = <®_3p3v>; + smsc,irq-push-pull; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpio5 10 0>; + linux,code = ; + wakeup-source; + }; + + key-back { + label = "Back"; + gpios = <&gpio5 11 0>; + linux,code = ; + wakeup-source; + }; + + key-program { + label = "Program"; + gpios = <&gpio5 12 0>; + linux,code = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio5 13 0>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio4 0 0>; + linux,code = ; + }; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-ard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_1__GPIO1_1 0x80000000 + MX53_PAD_GPIO_9__GPIO1_9 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_GPIO_10__GPIO4_0 0x80000000 + MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 + MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 + MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 + MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 + MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 + MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 + MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 + MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 + MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 + MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 + MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 + MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 + MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 + MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 + MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 + MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 + MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 + MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 + MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 + MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 + MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 + MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts new file mode 100644 index 000000000000..055d23a9aee7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2017 Beckhoff Automation GmbH & Co. KG + * based on imx53-qsb.dts + */ + +/dts-v1/; +#include "imx53.dtsi" + +/ { + model = "Beckhoff CX9020 Embedded PC"; + compatible = "bhf,cx9020", "fsl,imx53"; + + chosen { + stdout-path = &uart2; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + display-0 { + #address-cells =<1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; + }; + + dvi-connector { + compatible = "dvi-connector"; + ddc-i2c-bus = <&i2c2>; + digital; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-converter { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-pwr-r { + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-pwr-g { + gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-pwr-b { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-sd1-b { + linux,default-trigger = "mmc0"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + }; + + led-sd2-b { + linux,default-trigger = "mmc1"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + }; + + regulator-3p2v { + compatible = "regulator-fixed"; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_CLKO 0x1c4 + MX53_PAD_GPIO_16__I2C3_SDA 0x1c4 + MX53_PAD_EIM_D22__GPIO3_22 0x1c4 + MX53_PAD_EIM_D23__GPIO3_23 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + MX53_PAD_GPIO_3__GPIO1_3 0x1c4 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4 + MX53_PAD_EIM_D20__GPIO3_20 0x1e4 + MX53_PAD_GPIO_8__GPIO1_8 0x1c4 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_disp0: ipudisp0grp { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 + MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 + MX53_PAD_EIM_D28__UART2_RTS 0x1e4 + MX53_PAD_EIM_D29__UART2_CTS 0x1e4 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts new file mode 100644 index 000000000000..0e7f071fd10e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 DDC"; + compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + power-supply = <®_backlight>; + brightness-levels = <0 24 28 32 36 + 40 44 48 52 56 + 60 64 68 72 76 + 80 84 88 92 96 100>; + default-brightness-level = <20>; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp>; + + port@0 { + reg = <0>; + + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcd_panel: lcd-panel { + compatible = "koe,tx14d24vm1bpa"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight-supply"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + regulator-always-on; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c3 { + adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + + gpio-expander2@21 { + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iomuxc { + imx53-kp-ddc { + pinctrl_disp: dispgrp { + fsl,pins = < + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 + MX53_PAD_GPIO_1__PWM2_PWMO 0x4 + >; + }; + }; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + +&pmic { + fsl,mc13xxx-uses-touch; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts new file mode 100644 index 000000000000..6e3d71baac0f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 HSC"; + compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; +}; + +&fec { + status = "okay"; + + fixed-link { /* RMII fixed link to LAN9303 */ + speed = <100>; + full-duplex; + }; +}; + +&i2c3 { + switch: switch@a { + compatible = "smsc,lan9303-i2c"; + reg = <0xa>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <400>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { /* RMII fixed link to master */ + reg = <0>; + label = "cpu"; + ethernet = <&fec>; + }; + + port@1 { /* external port 1 */ + reg = <1>; + label = "lan1"; + }; + + port@2 { /* external port 2 */ + reg = <2>; + label = "lan2"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi new file mode 100644 index 000000000000..4508f34139a0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-tqma53.dtsi" +#include + +/ { + buzzer { + compatible = "pwm-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buzzer>; + pwms = <&pwm1 0 500000>; + }; + + gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button-kalt { + label = "Kaltstart"; + linux,code = ; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + button-pwr { + label = "PowerFailInterrupt"; + linux,code = ; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-bus { + label = "bus"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-error { + label = "error"; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-flash { + label = "flash"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + gpio-expander1@22 { + compatible = "nxp,pcf8574"; + reg = <0x22>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kp_common>; + + imx53-kp-common { + pinctrl_buzzer: buzzergrp { + fsl,pins = < + MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 + >; + }; + + pinctrl_gpiobuttons: gpiobuttonsgrp { + fsl,pins = < + MX53_PAD_EIM_RW__GPIO2_26 0x1e4 + MX53_PAD_EIM_D22__GPIO3_22 0x1e4 + >; + }; + + pinctrl_kp_common: kpcommongrp { + fsl,pins = < + MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 + MX53_PAD_GPIO_19__GPIO4_5 0x1e4 + MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 + MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 + MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 + MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 + MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 + MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 + MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 + >; + }; + + pinctrl_leds: ledgrp { + fsl,pins = < + MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 + MX53_PAD_EIM_D28__GPIO3_28 0x1d4 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&pinctrl_uart1 { + fsl,pins = < + MX53_PAD_EIM_D23__GPIO3_23 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D19__GPIO3_19 0x1e4 + MX53_PAD_EIM_D20__GPIO3_20 0x1e4 + >; +}; + +&pwm1 { + #pwm-cells = <2>; +}; + +&pwm2 { + #pwm-cells = <2>; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy0 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi new file mode 100644 index 000000000000..fe5e0d308e99 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Marek Vasut + */ + +#include "imx53.dtsi" + +/ { + model = "Aries/DENX M53"; + compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_backlight: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@41 { + compatible = "st,stmpe610"; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + interrupts = <6 0x0>; + interrupt-parent = <&gpio7>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <3>; + st,touch-det-delay = <3>; + st,settling = <4>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts new file mode 100644 index 000000000000..2bd2432d317f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2013 Marek Vasut + */ + +/dts-v1/; +#include "imx53-m53.dtsi" + +/ { + model = "Aries/DENX M53EVK"; + compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; + + display1: disp1 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + + display-timings { + 800x480p60 { + native-mode; + clock-frequency = <31500000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <128>; + vback-porch = <33>; + vfront-porch = <9>; + vsync-len = <3>; + vsync-active = <1>; + }; + }; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 3000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_backlight>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio>; + + led-user1 { + label = "user1"; + gpios = <&gpio2 8 0>; + linux,default-trigger = "heartbeat"; + }; + + led-user2 { + label = "user2"; + gpios = <&gpio2 9 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usbh1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 0>; + }; + + reg_usb_otg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 0>; + }; + }; + + sound { + compatible = "fsl,imx53-m53evk-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-m53evk-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Ext Spk", "LINE_OUT"; + mux-int-port = <2>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX53_PAD_GPIO_4__GPIO1_4 0x000b0 + >; + }; + + led_pin_gpio: led_gpio { + fsl,pins = < + MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 + MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 + MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 + MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 + MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 + MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; + }; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts new file mode 100644 index 000000000000..4d77b6077fc1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut + */ + +/dts-v1/; +#include "imx53-m53.dtsi" + +/ { + model = "MENLO M53 EMBEDDED DEVICE"; + compatible = "menlo,m53menlo", "fsl,imx53"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_power_button>; + pinctrl-names = "default"; + + power-button { + label = "Power button"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pinctrl_power_out>; + pinctrl-names = "default"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-user1 { + label = "TestLed601"; + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-user2 { + label = "TestLed602"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-eth { + label = "EthLedYe"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + }; + + lvds-decoder { + compatible = "ti,ds90cf364a", "lvds-decoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_decoder_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0dh6"; + pinctrl-0 = <&pinctrl_display_gpio>; + pinctrl-names = "default"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_decoder_out>; + }; + }; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 0>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, + <&clks IMX5_CLK_CKO1_PODF>, + <&clks IMX5_CLK_CKO1>; + assigned-clock-parents = <&clks IMX5_CLK_AHB>; + assigned-clock-rates = <133333334>, <33333334>, <33333334>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev@0 { + compatible = "menlo,m53cpld"; + spi-max-frequency = <25000000>; + reg = <0>; + }; + + spidev@1 { + compatible = "menlo,m53cpld"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "TestPin_SV2_3", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", + "", "CPLD_JTAG_TDO", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "CPLD_JTAG_TCK", "KBD_intK", + "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", + "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", + "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "", + "CPLD_reset", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "USB-OTG_OverCurrent", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + dac@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + }; +}; + +&i2c2 { + touchscreen@41 { + status = "disabled"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + hoggrp { + fsl,pins = < + MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 + MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 + MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 + >; + }; + + pinctrl_beeper: beepergrp { + fsl,pins = < + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 + >; + }; + + pinctrl_display_gpio: display-gpiogrp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ + + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 + MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 + MX53_PAD_EIM_RW__GPIO2_26 0xe4 + MX53_PAD_EIM_LBA__GPIO2_27 0xe4 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 + MX53_PAD_GPIO_9__GPIO1_9 0x1e4 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 + MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 + >; + }; + + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_power_button: powerbutgrp { + fsl,pins = < + MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 + >; + }; + + pinctrl_power_out: poweroutgrp { + fsl,pins = < + MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x1c4 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 + MX53_PAD_GPIO_4__GPIO1_4 0x1c4 + MX53_PAD_GPIO_18__GPIO7_13 0x1c4 + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&lvds_decoder_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts new file mode 100644 index 000000000000..09eee0dd44c1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer , Pengutronix + * Copyright 2012 Steffen Trumtrar , Pengutronix + */ + +/dts-v1/; +#include "imx53-tqma53.dtsi" + +/ { + model = "TQ MBa53 starter kit"; + compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; + + chosen { + stdout-path = &uart2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; + default-brightness-level = <10>; + enable-gpios = <&gpio7 7 0>; + power-supply = <®_backlight>; + }; + + disp1: disp1 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp1_1>; + interface-pix-fmt = "rgb24"; + status = "disabled"; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_backlight: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "lcd-supply"; + gpio = <&gpio2 5 0>; + startup-delay-us = <5000>; + }; + + reg_3p2v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; + + sound { + compatible = "tq,imx53-mba53-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-mba53-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_1>; + status = "disabled"; +}; + +&iomuxc { + lvds1 { + pinctrl_lvds1_1: lvds1-grp1 { + fsl,pins = < + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + >; + }; + + pinctrl_lvds1_2: lvds1-grp2 { + fsl,pins = < + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 + >; + }; + }; + + disp1 { + pinctrl_disp1_1: disp1-grp1 { + fsl,pins = < + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ + MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ + MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 + >; + }; + }; + + tve { + pinctrl_vga_sync_1: vgasync-grp1 { + fsl,pins = < + /* VGA_VSYNC, HSYNC with max drive strength */ + MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 + MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 + >; + }; + }; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + +&cspi { + status = "okay"; +}; + +&audmux { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; +}; + +&i2c2 { + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; + }; + + expander: pca9554@20 { + compatible = "pca9554"; + reg = <0x20>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; + + sensor2: lm75@49 { + compatible = "lm75"; + reg = <0x49>; + }; +}; + +&fec { + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&esdhc2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&tve { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vga_sync_1>; + ddc-i2c-bus = <&i2c3>; + fsl,tve-mode = "vga"; + fsl,hsync-pin = <4>; + fsl,vsync-pin = <6>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h new file mode 100644 index 000000000000..67bd06610fdf --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h @@ -0,0 +1,1189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX53_PINFUNC_H +#define __DTS_IMX53_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 +#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 +#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 +#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 +#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 +#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 +#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 +#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 +#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 +#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 +#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 +#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 +#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 +#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 +#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 +#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 +#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 +#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 +#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 +#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 +#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 +#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 +#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 +#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 +#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 +#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 +#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 +#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 +#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 +#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 +#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 +#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 +#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 +#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 +#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 +#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 +#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 +#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 +#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 +#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 +#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 +#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 +#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 +#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 +#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 +#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 +#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 +#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 +#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 +#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 +#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 +#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 +#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 +#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 +#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 +#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 +#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 +#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 +#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 +#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 +#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 +#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 +#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 +#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 +#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 +#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 +#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 +#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 +#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 +#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 +#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 +#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 +#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 +#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 +#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 +#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 +#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 +#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 +#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 +#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 +#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 +#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 +#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 +#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 +#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 +#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 +#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 +#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 +#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 +#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 +#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 +#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 +#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 +#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 +#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 +#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 +#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 +#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 +#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 +#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 +#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 +#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 +#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 +#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 +#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 +#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 +#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 +#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 +#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 +#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 +#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 +#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 +#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 +#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 +#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 +#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 +#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 +#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 +#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 +#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 +#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 +#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 +#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 +#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 +#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 +#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 +#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 +#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 +#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 +#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 +#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 +#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 +#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 +#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 +#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 +#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 +#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 +#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 +#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 +#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 +#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 +#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 +#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 +#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 +#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 +#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 +#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 +#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 +#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 +#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 +#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 +#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 +#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 +#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 +#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 +#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 +#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 +#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 +#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 +#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 +#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 +#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 +#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 +#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 +#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 +#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 +#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 +#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 +#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 +#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 +#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 +#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 +#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 +#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 +#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 +#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 +#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 +#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 +#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 +#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 +#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 +#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 +#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 +#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 +#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 +#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 +#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 +#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 +#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 +#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 +#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 +#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 +#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 +#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 +#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 +#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 +#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 +#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 +#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 +#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 +#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 + +#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts new file mode 100644 index 000000000000..70c4a4852256 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -0,0 +1,1122 @@ +/* + * Copyright 2014 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx53.dtsi" +#include + +/ { + model = "General Electric CS ONE"; + compatible = "ge,imx53-cpuvo", "fsl,imx53"; + + aliases { + spi0 = &cspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + cko2_11M: sgtl-clock-cko2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + achc_24M: achc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + sgtlsound: sound { + compatible = "fsl,imx53-cpuvo-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-cpuvo-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <6>; + }; + + reg_sgtl5k: regulator-sgtl5k { + compatible = "regulator-fixed"; + regulator-name = "regulator-sgtl5k"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-0 = <&pinctrl_usb_otg_vbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usbh2_vbus: regulator-usbh2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbh3_vbus: regulator-usbh3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh3_vbus>; + gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_tsiref: regulator-tsiref { + compatible = "regulator-fixed"; + regulator-name = "tsiref"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + /* TPS54320 */ + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_lcd: regulator-3v3-lcd { + /* MIC2009 */ + compatible = "regulator-fixed"; + regulator-name = "LCD_3V3"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pwm_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 + 38 40 43 45 48 51 53 56 58 61 63 66 68 71 + 73 76 79 81 84 86 89 91 94 96 99 102 104 + 107 109 112 114 117 119 122 124 127 130 + 132 135 137 140 142 145 147 150 153 155 + 158 160 163 165 168 170 173 175 178 181 + 183 186 188 191 193 196 198 201 204 206 + 209 211 214 216 219 221 224 226 229 232 + 234 237 239 242 244 247 249 252 255>; + default-brightness-level = <0>; + enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3_lcd>; + }; + + led-controller-1 { + compatible = "pwm-leds"; + + led-1 { + label = "alarm-brightness"; + pwms = <&pwm1 0 100000>; + max-brightness = <255>; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_alarmled_pins>; + + led-2 { + label = "alarm:red"; + gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "alarm:yellow"; + gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "alarm:blue"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "alarm:silenced"; + gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + active-delay = <100>; + inactive-delay = <10>; + wait-delay = <100>; + }; + + power-gpio-keys { + compatible = "gpio-keys"; + + power-button { + label = "Power button"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + touch-lock-key { + compatible = "gpio-keys"; + + touch-lock-button { + label = "Touch lock button"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + usbphy2: usbphy-2 { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; + reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; + clock-names = "main_clk"; + clock-frequency = <24000000>; + clocks = <&clks IMX5_CLK_CKO2>; + assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; + assigned-clock-parents = <&clks IMX5_CLK_OSC>; + }; + + usbphy3: usbphy-3 { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + clock-names = "main_clk"; + + clock-frequency = <24000000>; + clocks = <&clks IMX5_CLK_CKO2>; + assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; + assigned-clock-parents = <&clks IMX5_CLK_OSC>; + }; + + panel-lvds0 { + compatible = "nvd,9128"; + power-supply = <®_3v3_lcd>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&usbphy0 { + vcc-supply = <®_3v3>; +}; + +&usbphy1 { + vcc-supply = <®_3v3>; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&cpu0 { + /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ + operating-points = < + /* kHz uV */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + >; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW + &gpio4 11 GPIO_ACTIVE_LOW + &gpio4 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@1 { + compatible = "ge,achc", "nxp,kinetis-k20"; + reg = <1>, <0>; + vdd-supply = <®_3v3>; + vdda-supply = <®_3v3>; + clocks = <&achc_24M>; + reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + }; + + gpioxra0: gpio@2 { + compatible = "exar,xra1403"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + }; + + gpioxra1: gpio@3 { + compatible = "exar,xra1403"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + status = "okay"; + + da9053@0 { + compatible = "dlg,da9053-aa"; + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <1000000>; + dlg,tsi-as-adc; + tsiref-supply = <®_tsiref>; + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3650000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + }; + }; + +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + bus-width = <8>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_3v3>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + + i2c4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + VDDA-supply = <®_sgtl5k>; + VDDIO-supply = <®_sgtl5k>; + clocks = <&cko2_11M>; + status = "okay"; + }; + }; + + i2c5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + temp@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + mma8453q: accelerometer@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-names = "INT1"; + }; + + mpl3115: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; + }; + + i2c6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c8: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c9: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c10: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c11: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; + reg = <0x4b>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@2 { + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pmu { + secure-reg-access; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dma-info = <24 20>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,dma-info = <4096 4>; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + phy_type = "utmi"; + vbus-supply = <®_usb_otg_vbus>; + pinctrl-0 = <&pinctrl_usb_otg>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + phy_type = "ulpi"; + dr_mode = "host"; + fsl,usbphy = <&usbphy2>; + vbus-supply = <®_usbh2_vbus>; + status = "okay"; +}; + +&usbh3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh3>; + phy_type = "ulpi"; + dr_mode = "host"; + vbus-supply = <®_usbh3_vbus>; + fsl,usbphy = <&usbphy3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_rev6>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400 + MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400 + MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400 + MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400 + MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400 + MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400 + MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400 + MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400 + MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400 + MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400 + /* ECSPI1_SS0, must treat as GPIO for EzPort */ + MX53_PAD_DISP0_DAT23__GPIO5_17 0x400 + MX53_PAD_KEY_COL2__GPIO4_10 0x0 + MX53_PAD_KEY_ROW2__GPIO4_11 0x0 + MX53_PAD_KEY_COL3__GPIO4_12 0x0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0 + MX53_PAD_EIM_OE__ECSPI2_MISO 0x0 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0 + MX53_PAD_EIM_RW__GPIO2_26 0x0 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x0 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x0 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0 + >; + }; + + pinctrl_hog_rev6: hoggrp { + fsl,pins = < + /* CKO2 */ + MX53_PAD_GPIO_3__CCM_CLKO2 0x4 + /* DEFIB_SYNC_MARKER_IN_IRQ */ + MX53_PAD_GPIO_5__GPIO1_5 0x0 + /* ACCELEROMETER_DATA_RDY_N */ + MX53_PAD_GPIO_6__GPIO1_6 0x0 + /* TEMPERATURE_ALERT_N */ + MX53_PAD_GPIO_7__GPIO1_7 0x0 + /* BAROMETRIC_PRESSURE_DATA_RDY_N */ + MX53_PAD_GPIO_8__GPIO1_8 0x0 + /* DOCKING_I2C_INTERFACE_IRQ_N */ + MX53_PAD_PATA_DATA4__GPIO2_4 0x0 + /* PWR_OUT_TO_DOCK_FAULT_N */ + MX53_PAD_PATA_DATA5__GPIO2_5 0x0 + /* ENABLE_PWR_TO_DOCK_N */ + MX53_PAD_PATA_DATA6__GPIO2_6 0x0 + /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ + MX53_PAD_PATA_DATA7__GPIO2_7 0x0 + /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */ + MX53_PAD_PATA_DATA12__GPIO2_12 0x0 + /* DOCK_PRESENT_N */ + MX53_PAD_PATA_DATA13__GPIO2_13 0x0 + /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */ + MX53_PAD_PATA_DATA14__GPIO2_14 0x0 + /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */ + MX53_PAD_PATA_DATA15__GPIO2_15 0x0 + /* RESET_IMX535_ETHERNET_PHY_N */ + MX53_PAD_EIM_A22__GPIO2_16 0x0 + /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ + MX53_PAD_EIM_A21__GPIO2_17 0x0 + /* RESET_I2C1_BUS_SEGMENT_MUX_N */ + MX53_PAD_EIM_A20__GPIO2_18 0x0 + /* RESET_IMX535_USB_HOST3_PHY_N */ + MX53_PAD_EIM_A19__GPIO2_19 0x0 + /* ESDHC3_EMMC_NAND_RST_N */ + MX53_PAD_EIM_A18__GPIO2_20 0x0 + /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */ + MX53_PAD_EIM_A17__GPIO2_21 0x0 + /* POWER_DOWN_LVDS0_DESERIALIZER_N */ + MX53_PAD_EIM_A16__GPIO2_22 0x0 + /* POWER_DOWN_LVDS1_DESERIALIZER_N */ + MX53_PAD_EIM_LBA__GPIO2_27 0x0 + /* RESET_DP0_TRANSMITTER_N */ + MX53_PAD_EIM_EB0__GPIO2_28 0x0 + /* RESET_DP1_TRANSMITTER_N */ + MX53_PAD_EIM_EB1__GPIO2_29 0x0 + /* ENABLE_SPDIF_AUDIO_TO_DP0 */ + MX53_PAD_EIM_DA0__GPIO3_0 0x0 + /* ENABLE_SPDIF_AUDIO_TO_DP1 */ + MX53_PAD_EIM_DA1__GPIO3_1 0x0 + /* LVDS1_MUX_CTRL */ + MX53_PAD_EIM_DA2__GPIO3_2 0x0 + /* LVDS0_MUX_CTRL */ + MX53_PAD_EIM_DA3__GPIO3_3 0x0 + /* DP1_TRANSMITTER_IRQ */ + MX53_PAD_EIM_DA4__GPIO3_4 0x0 + /* DP0_TRANSMITTER_IRQ */ + MX53_PAD_EIM_DA5__GPIO3_5 0x0 + /* USB_RESET_N */ + MX53_PAD_EIM_DA6__GPIO3_6 0x0 + /* ENABLE_BATTERY_CHARGER */ + MX53_PAD_EIM_DA7__GPIO3_7 0x0 + /* SOFTWARE_CONTROLLED_PWR_CYCLE */ + MX53_PAD_EIM_DA8__GPIO3_8 0x0 + /* SOFTWARE_CONTROLLED_POWERDOWN */ + MX53_PAD_EIM_DA9__GPIO3_9 0x0 + /* DC_PWR_IN_OK */ + MX53_PAD_EIM_DA10__GPIO3_10 0x0 + /* BATT_PRESENT_N */ + MX53_PAD_EIM_DA11__GPIO3_11 0xe4 + /* PMIC_IRQ_N */ + MX53_PAD_EIM_DA12__GPIO3_12 0x0 + /* PMIC_VDD_FAULT_STATUS_N */ + MX53_PAD_EIM_DA13__GPIO3_13 0x0 + /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */ + MX53_PAD_EIM_DA14__GPIO3_14 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_DA15__GPIO3_15 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_D22__GPIO3_22 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_D24__GPIO3_24 0x0 + /* NBP_PUMP_VALVE_PWR_ENABLE */ + MX53_PAD_EIM_D25__GPIO3_25 0x0 + /* NIBP_RESET_N */ + MX53_PAD_EIM_D26__GPIO3_26 0x0 + /* LATCHED_OVERPRESSURE_N */ + MX53_PAD_EIM_D27__GPIO3_27 0x0 + /* NBP_SBWTCLK */ + MX53_PAD_EIM_D29__GPIO3_29 0x0 + /* ENABLE_WIFI_MODULE */ + MX53_PAD_GPIO_11__GPIO4_1 0x400 + /* WIFI_MODULE_IRQ_N */ + MX53_PAD_GPIO_12__GPIO4_2 0x400 + /* ENABLE_BLUETOOTH_MODULE */ + MX53_PAD_GPIO_13__GPIO4_3 0x400 + /* RESET_IMX535_USB_HOST2_PHY_N */ + MX53_PAD_GPIO_14__GPIO4_4 0x400 + /* ONKEY_IS_DEPRESSED */ + MX53_PAD_KEY_ROW3__GPIO4_13 0x0 + /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */ + MX53_PAD_EIM_WAIT__GPIO5_0 0x0 + /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */ + MX53_PAD_EIM_A25__GPIO5_2 0x0 + /* I2C_PCAP_TOUCHSCREEN_IRQ_N */ + MX53_PAD_EIM_A24__GPIO5_4 0x0 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT13__GPIO5_7 0x400 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT14__GPIO5_8 0x400 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT15__GPIO5_9 0x400 + /* HOST_CONTROLLED_RESET_TO_LCD_N */ + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0 + /* HOST_CONTROLLED_RESET_TO_PCAP_N */ + MX53_PAD_CSI0_MCLK__GPIO5_19 0x0 + /* LR_SCAN_CTRL */ + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0 + /* UD_SCAN_CTRL */ + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0 + /* DATA_WIDTH_CTRL */ + MX53_PAD_CSI0_DAT10__GPIO5_28 0x0 + /* BACKLIGHT_ENABLE */ + MX53_PAD_CSI0_DAT11__GPIO5_29 0x0 + /* MED_USB_PORT_1_HOST_SELECT */ + MX53_PAD_EIM_A23__GPIO6_6 0x0 + /* MED_USB_PORT_2_HOST_SELECT */ + MX53_PAD_NANDF_CLE__GPIO6_7 0x0 + /* MED_USB_PORT_3_HOST_SELECT */ + MX53_PAD_NANDF_ALE__GPIO6_8 0x0 + /* MED_USB_PORT_4_HOST_SELECT */ + MX53_PAD_NANDF_WP_B__GPIO6_9 0x0 + /* MED_USB_PORT_5_HOST_SELECT */ + MX53_PAD_NANDF_RB0__GPIO6_10 0x0 + /* MED_USB_PORT_6_HOST_SELECT */ + MX53_PAD_NANDF_CS0__GPIO6_11 0x0 + /* MED_USB_PORT_7_HOST_SELECT */ + MX53_PAD_NANDF_WE_B__GPIO6_12 0x0 + /* MED_USB_PORT_8_HOST_SELECT */ + MX53_PAD_NANDF_RE_B__GPIO6_13 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_0 */ + MX53_PAD_NANDF_CS1__GPIO6_14 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_1 */ + MX53_PAD_NANDF_CS2__GPIO6_15 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_2 */ + MX53_PAD_NANDF_CS3__GPIO6_16 0x0 + /* POWER_AND_BOOT_STATUS_INDICATOR */ + MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 + /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ + MX53_PAD_GPIO_16__GPIO7_11 0x0 + /* BATTERY_STATUS_INDICATOR_AMBER */ + MX53_PAD_GPIO_17__GPIO7_12 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D28__GPIO3_28 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 + MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D16__GPIO3_16 0x1e4 + MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 + MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_GPIO_9__PWM1_PWMO 0x5 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_EIM_D23__UART3_CTS 0x1e4 + MX53_PAD_EIM_EB3__UART3_RTS 0x1e4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 + >; + }; + + pinctrl_usb_otg_vbus: usb-otg-vbusgrp { + fsl,pins = < + /* USB_HS_OTG_VBUS_ENABLE */ + MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + /* USB H2 */ + MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180 + MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180 + MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180 + MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180 + MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180 + MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180 + MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180 + MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180 + MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180 + MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180 + MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180 + MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5 + MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180 + >; + }; + + pinctrl_usbh2_vbus: usbh2-vbusgrp { + fsl,pins = < + /* USB_HS_HOST2_VBUS_ENABLE */ + MX53_PAD_EIM_D31__GPIO3_31 0x0 + >; + }; + + pinctrl_usbh3_vbus: usbh3-vbusgrp { + fsl,pins = < + /* USB_HS_HOST3_VBUS_ENABLE */ + MX53_PAD_CSI0_DAT9__GPIO5_27 0x0 + >; + }; + + pinctrl_usbh3: usbh3grp { + fsl,pins = < + /* USB H3 */ + MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180 + MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180 + MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180 + MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180 + MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180 + MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180 + MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180 + MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180 + MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5 + MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180 + MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180 + MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180 + MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + /* USB_OTG_FAULT_N */ + MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 + >; + }; + + pinctrl_alarmled_pins: qmx6alarmledgrp { + fsl,pins = < + /* ACTIVATE_ALARM_LIGHT_RED */ + MX53_PAD_PATA_DIOR__GPIO7_3 0x0 + /* ACTIVATE_ALARM_LIGHT_YELLOW */ + MX53_PAD_PATA_DA_1__GPIO7_7 0x0 + /* ACTIVATE_ALARM_LIGHT_CYAN */ + MX53_PAD_PATA_DA_2__GPIO7_8 0x0 + /* AUDIO_ALARMS_SILENCED_INDICATOR */ + MX53_PAD_GPIO_18__GPIO7_13 0x0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi new file mode 100644 index 000000000000..50fef8dd3675 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include "imx53.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + display0: disp0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power Button"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio7_7>; + + led-user { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "sii,43wvf1g"; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx53-qsb-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-qsb-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; +}; + +&cpu0 { + /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ + operating-points = < + /* kHz uV */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + >; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&ssi2 { + status = "okay"; +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-qsb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_8__GPIO1_8 0x80000000 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 + MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 + MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + >; + }; + + led_pin_gpio7_7: led_gpio7_7 { + fsl,pins = < + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_EIM_DA13__GPIO3_13 0xe4 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + /* open drain */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec + MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_disp0: ipudisp0grp { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_vga_sync: vgasync-grp { + fsl,pins = < + /* VGA_HSYNC, VSYNC with max drive strength */ + MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 + MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&tve { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vga_sync>; + ddc-i2c-bus = <&i2c2>; + fsl,tve-mode = "vga"; + fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ + fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsb.dts new file mode 100644 index 000000000000..6831836bd726 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; +#include "imx53-qsb-common.dtsi" + +/ { + model = "Freescale i.MX53 Quick Start Board"; + compatible = "fsl,imx53-qsb", "fsl,imx53"; +}; + +&i2c1 { + pmic: dialog@48 { + compatible = "dlg,da9053-aa", "dlg,da9052"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ + + regulators { + buck1_reg: buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + ldo8_reg: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + }; + }; +}; + +&tve { + dac-supply = <&ldo7_reg>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts new file mode 100644 index 000000000000..1bbf24ad308a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx53-qsb-common.dtsi" + +/ { + model = "Freescale i.MX53 Quick Start-R Board"; + compatible = "fsl,imx53-qsrb", "fsl,imx53"; +}; + +&iomuxc { + imx53-qsrb { + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */ + >; + }; + }; +}; + +&i2c1 { + pmic: mc34708@8 { + compatible = "fsl,mc34708"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x08>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + regulators { + sw1_reg: sw1a { + regulator-name = "SW1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + }; + + sw1b_reg: sw1b { + regulator-name = "SW1B"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1425000>; + regulator-boot-on; + }; + + sw4a_reg: sw4a { + regulator-name = "SW4A"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4b_reg: sw4b { + regulator-name = "SW4B"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw5_reg: sw5 { + regulator-name = "SW5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-name = "SWBST"; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-name = "VPLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + vrefddr_reg: vrefddr { + regulator-name = "VREFDDR"; + regulator-boot-on; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-name = "VUSB"; + regulator-boot-on; + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-name = "VUSB2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vdac_reg: vdac { + regulator-name = "VDAC"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + vgen1_reg: vgen1 { + regulator-name = "VGEN1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-name = "VGEN2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&tve { + dac-supply = <&vdac_reg>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts new file mode 100644 index 000000000000..103e73176e47 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2023 Linaro Ltd. + +/dts-v1/; + +#include "imx53.dtsi" + +/ { + model = "StarterKit SK-iMX53 Board"; + compatible = "starterkit,sk-imx53", "fsl,imx53"; + + aliases { + /* + * iMX RTC is not battery powered on this board. + * Use the i2c RTC as rtc0. + */ + rtc0 = &rtc; + rtc1 = &srtc; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@70000000 { + device_type = "memory"; + /* v2 had only 256 MB, v3 has 512 MB */ + reg = <0x70000000 0x20000000>; + }; + + reg_usb1_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&esdhc1 { + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + }; + + rtc: rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x1e4 + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x1e4 + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x1e4 + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x1e4 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x1e4 + MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x1e4 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x1e4 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x1e4 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x1e4 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x1e4 + MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x1e4 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x1e4 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_EIM_DA14__GPIO3_14 0x1f0 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0x400001e4 + MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4 + MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x4 + MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x4 + MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x4 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_GPIO_9__PWM1_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_EIM_D24__UART3_TXD_MUX 0x1e4 + MX53_PAD_EIM_D25__UART3_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 + >; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00100000>; + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x00100000 0x00100000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x00200000 0x00100000>; + read-only; + }; + + partition@1000000 { + label = "kernel-safe"; + reg = <0x01000000 0x00a00000>; + read-only; + }; + + partition@1a00000 { + label = "kernel"; + reg = <0x01a00000 0x005e0000>; + }; + + partition@2000000 { + label = "ubifs"; + reg = <0x02000000 0x0e000000>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb1_vbus>; + phy_type = "utmi"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts new file mode 100644 index 000000000000..f8d17967a67e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; +#include +#include "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Smart Mobile Reference Design Board"; + compatible = "fsl,imx53-smd", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = ; + }; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + non-removable; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + zigbee: mc1323@0 { + compatible = "fsl,mc1323"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + + flash: m25p32@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "st,m25p", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-smd { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 + MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 + MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 + MX53_PAD_EIM_D19__GPIO3_19 0x80000000 + MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_csi0: ipucsi0grp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 + MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 + >; + }; + + pinctrl_ov5642: ov5642grp { + fsl,pins = < + MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 + MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + + magnetometer: mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + }; + + touchkey: mpr121@5a { + compatible = "fsl,mpr121"; + reg = <0x5a>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + camera: ov5642@3c { + compatible = "ovti,ov5642"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5642>; + assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>, + <&clks IMX5_CLK_SSI_EXT1_COM_SEL>; + assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>, + <&clks IMX5_CLK_SSI_EXT1_PODF>; + assigned-clock-rates = <0>, <24000000>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + clock-names = "xclk"; + DVDD-supply = <&ldo9_reg>; + AVDD-supply = <&ldo7_reg>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + + port { + ov5642_to_ipu_csi0: endpoint { + remote-endpoint = <&ipu_csi0_from_parallel_sensor>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + + pmic: dialog@48 { + compatible = "dlg,da9053", "dlg,da9052"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + ldo7_reg: ldo7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + }; + + ldo9_reg: ldo9 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3650000>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ipu_csi0_from_parallel_sensor { + remote-endpoint = <&ov5642_to_ipu_csi0>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_csi0>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi new file mode 100644 index 000000000000..d930739674a1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer , Pengutronix + * Copyright 2012 Steffen Trumtrar , Pengutronix + */ + +#include "imx53.dtsi" + +/ { + model = "TQ TQMa53"; + compatible = "tq,tqma53", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x40000000>; /* Up to 1GiB */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>, + <&pinctrl_esdhc2_cdwp>; + vmmc-supply = <®_3p3v>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, + <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&esdhc3 { /* EMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-tqma53 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ + MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ + MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ + MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ + MX53_PAD_GPIO_3__GPIO1_3 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 + MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 + >; + }; + + pinctrl_cspi: cspigrp { + fsl,pins = < + MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 + MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 + MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + >; + }; + + pinctrl_esdhc2_cdwp: esdhc2cdwp { + fsl,pins = < + MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; +}; + +&pwm2 { + #pwm-cells = <2>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&cspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi>; + cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>, + <&gpio1 21 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: mc34708@8 { + compatible = "fsl,mc34708"; + reg = <0x8>; + fsl,mc13xxx-uses-rtc; + interrupt-parent = <&gpio2>; + interrupts = <6 4>; /* PATA_DATA6, active high */ + }; + + sensor1: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x50>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts new file mode 100644 index 000000000000..a7f77527269d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts @@ -0,0 +1,351 @@ +/* + * Copyright 2013-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx53-tx53.dtsi" +#include +#include +#include + +/ { + model = "Ka-Ro electronics TX53 module (LCD)"; + compatible = "karo,tx53", "fsl,imx53"; + + aliases { + display = &display; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_vga1>; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_3v3>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06_1>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <660>; + wakeup-source; + }; +}; + +&iomuxc { + imx53-tx53-x03x { + pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { + fsl,pins = < + MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ + MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ + MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 + MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 + MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 + MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 + MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 + MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 + MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 + MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 + >; + }; + + pinctrl_rgb24_vga1: rgb24-vgagrp1 { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ + >; + }; + }; +}; + +&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + /* sample keymap */ + /* row/col 0,1 are mapped to KPP row/col 6,7 */ + linux,keymap = < + MATRIX_KEY(6, 6, KEY_POWER) + MATRIX_KEY(6, 7, KEY_KP0) + MATRIX_KEY(6, 2, KEY_KP1) + MATRIX_KEY(6, 3, KEY_KP2) + MATRIX_KEY(7, 6, KEY_KP3) + MATRIX_KEY(7, 7, KEY_KP4) + MATRIX_KEY(7, 2, KEY_KP5) + MATRIX_KEY(7, 3, KEY_KP6) + MATRIX_KEY(2, 6, KEY_KP7) + MATRIX_KEY(2, 7, KEY_KP8) + MATRIX_KEY(2, 2, KEY_KP9) + >; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts new file mode 100644 index 000000000000..6cdf2082c742 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts @@ -0,0 +1,262 @@ +/* + * Copyright 2013-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx53-tx53.dtsi" +#include + +/ { + model = "Ka-Ro electronics TX53 module (LVDS)"; + compatible = "karo,tx53", "fsl,imx53"; + + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_3v3>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_3v3>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; + + reg_lcd_pwr0: regulator-lvds0-pwr { + compatible = "regulator-fixed"; + regulator-name = "LVDS0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd_pwr1: regulator-lvds1-pwr { + compatible = "regulator-fixed"; + regulator-name = "LVDS1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; +}; + +&iomuxc { + imx53-tx53-x13x { + pinctrl_lvds0: lvds0grp { + fsl,pins = < + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + >; + }; + + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = ; + }; + + pinctrl_eeti1: eeti1grp { + fsl,pins = < + MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ + >; + }; + + pinctrl_eeti2: eeti2grp { + fsl,pins = < + MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds0_timing0>; + + lvds0_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hsync-len = <60>; + hfront-porch = <40>; + vback-porch = <21>; + vsync-len = <10>; + vfront-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + lvds0_timing1: nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hsync-len = <60>; + hfront-porch = <50>; + vback-porch = <5>; + vsync-len = <13>; + vfront-porch = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds1_timing0>; + + lvds1_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hsync-len = <60>; + hfront-porch = <40>; + vback-porch = <21>; + vsync-len = <10>; + vfront-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi new file mode 100644 index 000000000000..a439a47fb65a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi @@ -0,0 +1,584 @@ +/* + * Copyright 2012-2017 + * based on imx53-qsb.dts + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx53.dtsi" +#include + +/ { + model = "Ka-Ro electronics TX53 module"; + compatible = "karo,tx53", "fsl,imx53"; + + /* Will be filled by the bootloader */ + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0>; + }; + + aliases { + can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ + can1 = &can1; + ipu = &ipu; + reg-can-xcvr = ®_can_xcvr; + usbh1 = &usbh1; + usbotg = &usbotg; + }; + + clocks { + ckih1 { + clock-frequency = <0>; + }; + }; + + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key>; + + key-power { + label = "Power Button"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,code = <116>; /* KEY_POWER */ + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stk5led>; + + led-user { + label = "Heartbeat"; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; + model = "tx53-audio-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + /* '1' based port numbers according to datasheet names */ + mux-int-port = <1>; + mux-ext-port = <5>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + cs-gpios = < + &gpio2 30 GPIO_ACTIVE_HIGH + &gpio3 19 GPIO_ACTIVE_HIGH + >; + +}; + +&esdhc1 { + cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&esdhc2 { + cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + phy-handle = <&phy0>; + mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + device_type = "ethernet-phy"; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-0 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + clock-frequency = <400000>; + status = "okay"; + + rtc1: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ds1339>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-tx53 { + pinctrl_hog: hoggrp { + /* pins not in use by any device on the Starterkit board series */ + fsl,pins = < + /* CMOS Sensor Interface */ + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 + MX53_PAD_GPIO_0__GPIO1_0 0x1f4 + /* Module Specific Signal */ + /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ + /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ + MX53_PAD_EIM_D29__GPIO3_29 0x1f4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 + /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ + /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ + MX53_PAD_EIM_A19__GPIO2_19 0x1f4 + MX53_PAD_EIM_A20__GPIO2_18 0x1f4 + MX53_PAD_EIM_A21__GPIO2_17 0x1f4 + MX53_PAD_EIM_A22__GPIO2_16 0x1f4 + MX53_PAD_EIM_A23__GPIO6_6 0x1f4 + MX53_PAD_EIM_A24__GPIO5_4 0x1f4 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 + /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ + /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ + MX53_PAD_GPIO_13__GPIO4_3 0x1f4 + MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 + MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 + MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 + MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 + MX53_PAD_EIM_OE__GPIO2_25 0x1f4 + MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 + MX53_PAD_EIM_RW__GPIO2_26 0x1f4 + MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 + MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 + MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 + MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 + MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 + MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 + MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 + MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = ; /* Flexcan XCVR enable */ + }; + + pinctrl_ds1339: ds1339grp { + fsl,pins = ; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 + MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_EIM_D24__GPIO3_24 0x1f0 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + MX53_PAD_EIM_D25__GPIO3_25 0x1f0 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_gpio_key: gpio-keygrp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 + MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 + MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 + >; + }; + + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_ssi2: ssi2grp { + fsl,pins = < + MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 + MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 + MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 + MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 + MX53_PAD_EIM_D27__GPIO3_27 0x1f0 + >; + }; + + pinctrl_stk5led: stk5ledgrp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ + MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ + >; + }; + }; +}; + +&ipu { + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&sdma { + fsl,sdma-ram-script-name = "sdma-imx53.bin"; +}; + +&ssi1 { + status = "okay"; +}; + +&ssi2 { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + phy_type = "utmi"; + disable-over-current; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "peripheral"; + disable-over-current; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts b/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts new file mode 100644 index 000000000000..acc44010d510 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts @@ -0,0 +1,225 @@ +/* + * USB armory MkI device tree file + * https://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx53.dtsi" + +/ { + model = "Inverse Path USB armory"; + compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; +}; + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-user { + label = "LED"; + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* + * Not every i.MX53 P/N supports clock > 800MHz. + * As USB armory does not mount a specific P/N set a safe clock upper limit. + */ +&cpu0 { + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + >; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_i2c1_pmic: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x80 + MX53_PAD_EIM_D28__I2C1_SDA 0x80 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 + >; + }; + + /* + * UART mode pin header configuration + * 3 - GPIO5[26], pull-down 100K + * 4 - GPIO5[27], pull-down 100K + * 5 - TX, pull-up 100K + * 6 - RX, pull-up 100K + * 7 - GPIO5[30], pull-down 100K + */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 + MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 + >; + }; +}; + +&i2c1 { + pinctrl-0 = <&pinctrl_i2c1_pmic>; + status = "okay"; + + ltc3589: pmic@34 { + compatible = "lltc,ltc3589-2"; + reg = <0x34>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <591930>; + regulator-max-microvolt = <1224671>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456803>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1341250>; + regulator-max-microvolt = <2775000>; + lltc,fb-voltage-divider = <270000 100000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + bb_out_reg: bb-out { + regulator-min-microvolt = <3387341>; + regulator-max-microvolt = <3387341>; + lltc,fb-voltage-divider = <511000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-min-microvolt = <1306329>; + regulator-max-microvolt = <1306329>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456806>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3200000>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts b/arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts new file mode 100644 index 000000000000..ae53d178a683 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. + */ + +/dts-v1/; +#include "imx53-voipac-dmm-668.dtsi" + +/ { + sound { + compatible = "fsl,imx53-voipac-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-voipac-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio>; + + led1 { + label = "led-red"; + gpios = <&gpio3 29 0>; + default-state = "off"; + }; + + led2 { + label = "led-orange"; + gpios = <&gpio2 31 0>; + default-state = "off"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-voipac { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SD2_CD */ + MX53_PAD_EIM_D25__GPIO3_25 0x80000000 + /* SD2_WP */ + MX53_PAD_EIM_A19__GPIO2_19 0x80000000 + >; + }; + + led_pin_gpio: led_gpio { + fsl,pins = < + MX53_PAD_EIM_D29__GPIO3_29 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + >; + }; + + /* Keyboard controller */ + pinctrl_kpp_1: kppgrp-1 { + fsl,pins = < + MX53_PAD_GPIO_9__KPP_COL_6 0xe8 + MX53_PAD_GPIO_4__KPP_COL_7 0xe8 + MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 + MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 + MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 + MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 + MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 + MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 + MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 + MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + >; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&clks 150>; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp_1>; + linux,keymap = < + 0x0203003b /* KEY_F1 */ + 0x0603003c /* KEY_F2 */ + 0x0207003d /* KEY_F3 */ + 0x0607003e /* KEY_F4 */ + >; + keypad,num-rows = <8>; + keypad,num-columns = <1>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi new file mode 100644 index 000000000000..24859d0c09c1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. + */ + +#include "imx53.dtsi" + +/ { + model = "Voipac i.MX53 X53-DMM-668"; + compatible = "voipac,imx53-dmm-668", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 0>; /* PEN */ + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-voipac { + pinctrl_hog: hoggrp { + fsl,pins = < + /* Make DA9053 regulator functional */ + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + /* FEC Power enable */ + MX53_PAD_GPIO_11__GPIO4_1 0x80000000 + /* FEC RST */ + MX53_PAD_GPIO_12__GPIO4_2 0x80000000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, + <&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: dialog@48 { + compatible = "dlg,da9053-aa", "dlg,da9052"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1580000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <2370000>; + regulator-max-microvolt = <2630000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <2770000>; + regulator-max-microvolt = <2780000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1850000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1450000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi new file mode 100644 index 000000000000..17dc13719639 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53.dtsi @@ -0,0 +1,859 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include "imx53-pinfunc.h" +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + ipu0 = &ipu; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&clks IMX5_CLK_ARM>; + clock-latency = <61036>; + voltage-tolerance = <5>; + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + 1200000 1300000 + >; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + + capture_subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; + }; + + tzic: tz-interrupt-controller@fffc000 { + compatible = "fsl,imx53-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x0fffc000 0x4000>; + }; + + clocks { + ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + usbphy1: usbphy-1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks IMX5_CLK_SATA_GATE>, + <&clks IMX5_CLK_SATA_REF>, + <&clks IMX5_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + + ipu: ipu@18000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ipu"; + reg = <0x18000000 0x08000000>; + interrupts = <11 10>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; + clock-names = "bus", "di0", "di1"; + resets = <&src 2>; + + ipu_csi0: port@0 { + reg = <0>; + + ipu_csi0_from_parallel_sensor: endpoint { + }; + }; + + ipu_csi1: port@1 { + reg = <1>; + + ipu_csi1_from_parallel_sensor: endpoint { + }; + }; + + ipu_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu_di0_lvds0: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds0_in>; + }; + }; + + ipu_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu_di1_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in>; + }; + + ipu_di1_tve: endpoint@2 { + reg = <2>; + remote-endpoint = <&tve_in>; + }; + }; + }; + + gpu: gpu@30000000 { + compatible = "amd,imageon-200.0", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; + + aips1: bus@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + spba-bus@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + esdhc1: mmc@50004000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50004000 0x4000>; + interrupts = <1>; + clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc2: mmc@50008000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50008000 0x4000>; + interrupts = <2>; + clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + uart3: serial@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi1: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + esdhc3: mmc@50020000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc4: mmc@50024000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + }; + + aipstz1: bridge@53f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x53f00000 0x60>; + }; + + usbotg: usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usbh1: usb@53f80200 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80200 0x0200>; + interrupts = <14>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh2: usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh3: usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + }; + + gpio1: gpio@53f84000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53f88000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@53f8c000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@53f90000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@53f94000 { + compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; + reg = <0x53f94000 0x4000>; + interrupts = <60>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: watchdog@53f98000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + wdog2: watchdog@53f9c000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + gpt: timer@53fa0000 { + compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + srtc: rtc@53fa4000 { + compatible = "fsl,imx53-rtc"; + reg = <0x53fa4000 0x4000>; + interrupts = <24>; + clocks = <&clks IMX5_CLK_SRTC_GATE>; + }; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx53-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + ldb: ldb@53fa8008 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ldb"; + reg = <0x53fa8008 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_in: endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@1 { + reg = <1>; + + lvds1_in: endpoint { + remote-endpoint = <&ipu_di1_lvds1>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + }; + + pwm1: pwm@53fb4000 { + #pwm-cells = <3>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@53fb8000 { + #pwm-cells = <3>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + src: reset-controller@53fd0000 { + compatible = "fsl,imx53-src", "fsl,imx51-src"; + reg = <0x53fd0000 0x4000>; + interrupts = <75>; + #reset-cells = <1>; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + + gpio5: gpio@53fdc000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53fdc000 0x4000>; + interrupts = <103 104>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@53fe0000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53fe0000 0x4000>; + interrupts = <105 106>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@53fe4000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53fe4000 0x4000>; + interrupts = <107 108>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c3: i2c@53fec000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; + reg = <0x53fec000 0x4000>; + interrupts = <64>; + clocks = <&clks IMX5_CLK_I2C3_GATE>; + status = "disabled"; + }; + + uart4: serial@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + aips2: bus@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + aipstz2: bridge@63f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x63f00000 0x60>; + }; + + iim: efuse@63f98000 { + compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon"; + reg = <0x63f98000 0x4000>; + interrupts = <69>; + clocks = <&clks IMX5_CLK_IIM_GATE>; + }; + + uart5: serial@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + + owire: owire@63fa4000 { + compatible = "fsl,imx53-owire", "fsl,imx21-owire"; + reg = <0x63fa4000 0x4000>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: spi@63fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sdma: dma-controller@63fb0000 { + compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + cspi: spi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@63fc4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; + reg = <0x63fc4000 0x4000>; + interrupts = <63>; + clocks = <&clks IMX5_CLK_I2C2_GATE>; + status = "disabled"; + }; + + i2c1: i2c@63fc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; + reg = <0x63fc8000 0x4000>; + interrupts = <62>; + clocks = <&clks IMX5_CLK_I2C1_GATE>; + status = "disabled"; + }; + + ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + audmux: audmux@63fd0000 { + compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; + }; + + nfc: nand@63fdb000 { + compatible = "fsl,imx53-nand"; + reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; + interrupts = <8>; + clocks = <&clks IMX5_CLK_NFC_GATE>; + status = "disabled"; + }; + + ssi3: ssi@63fe8000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fe8000 0x4000>; + interrupts = <96>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + tve: tve@63ff0000 { + compatible = "fsl,imx53-tve"; + reg = <0x63ff0000 0x1000>; + interrupts = <92>; + clocks = <&clks IMX5_CLK_TVE_GATE>, + <&clks IMX5_CLK_IPU_DI1_SEL>; + clock-names = "tve", "di_sel"; + status = "disabled"; + + port { + tve_in: endpoint { + remote-endpoint = <&ipu_di1_tve>; + }; + }; + }; + + vpu: vpu@63ff4000 { + compatible = "fsl,imx53-vpu", "cnm,coda7541"; + reg = <0x63ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&ocram>; + }; + + sahara: crypto@63ff8000 { + compatible = "fsl,imx53-sahara"; + reg = <0x63ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; + }; + + ocram: sram@f8000000 { + compatible = "mmio-sram"; + reg = <0xf8000000 0x20000>; + ranges = <0 0xf8000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX5_CLK_OCRAM>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi new file mode 100644 index 000000000000..d477a937b47a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +/ { + keyboard { + compatible = "gpio-keys"; + + button-0 { + gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; + label = "btn0"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + button-1 { + gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; + label = "btn1"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + button-2 { + gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; + label = "btn2"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + button-3 { + gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; + label = "btn3"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + }; + + leds { + compatible = "gpio-leds"; + + gen-led0 { + label = "led0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led0>; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + }; + + gen-led1 { + label = "led1"; + gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; + }; + + gen-led2 { + label = "led2"; + gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + gen-led3 { + label = "led3"; + gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_3v3: regulator-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_3v3>; + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + }; + + reg_enet: regulator-ethernet { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_enet>; + compatible = "regulator-fixed"; + regulator-name = "ethernet-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&sw4_reg>; + }; + + reg_audio: regulator-audio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_audio>; + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_hdmi: regulator-hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_hdmi>; + compatible = "regulator-fixed"; + regulator-name = "hdmi-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_uart3: regulator-uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_uart3>; + compatible = "regulator-fixed"; + regulator-name = "uart3-supply"; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_1v8: regulator-1v8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_1v8>; + compatible = "regulator-fixed"; + regulator-name = "1v8-supply"; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mipi: regulator-mipi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_mipi>; + regulator-name = "mipi_pwr_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + phy-supply = <®_enet>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&i2c3 { + ov5640: camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_mipi>; + AVDD-supply = <®_mipi>; + DVDD-supply = <®_mipi>; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + pcf8575: gpio@20 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf8574>; + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + lines-initial-states = <0x0710>; + wakeup-source; + }; +}; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_3v3>; + no-1-8-v; + keep-power-in-suspend; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_led0: led0grp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 + >; + }; + + pinctrl_pcf8574: pcf8575grp { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_1v8: reg1v8grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_reg_3v3: reg3v3grp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + >; + }; + + pinctrl_reg_audio: reg-audiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_reg_enet: reg-enetgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_reg_hdmi: reg-hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_reg_mipi: reg-mipigrp { + fsl,pins = ; + }; + + pinctrl_reg_pcie: reg-pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_reg_uart3: reguart3grp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_reg_usb_h1_vbus: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_reg_usb_otg: reg-usb-otggrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 + >; + }; + + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi new file mode 100644 index 000000000000..547fb141ec0c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1837"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddcore"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddsoc"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_3v3"; + regulator-boot-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "sw3a_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "sw3b_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_rgmii"; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-name = "gen_5v0"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "gen_vsns"; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "gen_1v5"; + }; + + vgen2_reg: vgen2 { + regulator-name = "vgen2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-name = "gen_vadj_0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-name = "gen_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "gen_vadj_1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "gen_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + coin_reg: coin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp102"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +/* Reroute power feeding the CPU to come from the external PMIC */ +®_arm +{ + vin-supply = <&sw1a_reg>; +}; + +®_soc +{ + vin-supply = <&sw1c_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpmi_nand: gpmi-nandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < /* Enable ARM Debugger */ + MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ + >; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wl18xx_vmmc>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts new file mode 100644 index 000000000000..4989e8d069a1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Altesco I6P Board"; + compatible = "alt,alti6p", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + i2c2-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c2>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c4-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c4>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + i2c_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2cmux>; + + mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>, + <&gpio5 11 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&clks { + clocks = <&clock_ksz8081>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clock_ksz8081>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "USB_H1_OC", "", "", "", "", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "I2C_EN13", "I2C_EN24", "", "", "", "", + "", "", "", "", "", "AUDIO_RESET", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +/* DDC */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* external interface, device are configured from user space */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&i2c4 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T configure DDC + * pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 + MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2cmux: i2cmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058 + + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts new file mode 100644 index 000000000000..3dcce3454b08 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Armadeus Systems + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-apf6.dtsi" +#include "imx6qdl-apf6dev.dtsi" + +/ { + model = "Armadeus APF6 Solo Module on APF6Dev Board"; + compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts new file mode 100644 index 000000000000..dfa6f64d43cc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts @@ -0,0 +1,158 @@ +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2015 Heiko Schocher + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos2.dtsi" + +/ { + model = "aristainetos2 i.MX6 Dual Lite Board 4"; + compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + display0: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + + port@0 { + reg = <0>; + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <0>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts new file mode 100644 index 000000000000..5e15212eaf3a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts @@ -0,0 +1,98 @@ +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2015 Heiko Schocher + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos2.dtsi" + +/ { + model = "aristainetos2 i.MX6 Dual Lite Board 7"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + panel: panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts new file mode 100644 index 000000000000..cc861a43eb58 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * support fot the imx6 based aristainetos board + * + * Copyright (C) 2014 Heiko Schocher + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos.dtsi" + +/ { + model = "aristainetos i.MX6 Dual Lite Board 4"; + compatible = "abb,aristainetos-imx6dl-4", "fsl,imx6dl"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + status = "okay"; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + display0: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; + + display-timings { + 480x800p60 { + native-mode; + clock-frequency = <30000000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <59>; + hback-porch = <10>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&pwm1 { + #pwm-cells = <2>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts new file mode 100644 index 000000000000..b6cb78870cd5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * support fot the imx6 based aristainetos board + * + * Copyright (C) 2014 Heiko Schocher + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos.dtsi" + +/ { + model = "aristainetos i.MX6 Dual Lite Board 7"; + compatible = "abb,aristainetos-imx6dl-7", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + display0: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + status = "okay"; + + display-timings { + 800x480p60 { + native-mode; + clock-frequency = <33246000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <88>; + hback-porch = <88>; + hsync-len = <80>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <25>; + vsync-active = <1>; + }; + }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 3000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&pwm3 { + #pwm-cells = <2>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts new file mode 100644 index 000000000000..411aa72d344b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B105Pv2"; + compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts new file mode 100644 index 000000000000..d011127c635b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B105v2"; + compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts new file mode 100644 index 000000000000..ca840fa84052 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B125Pv2"; + compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts new file mode 100644 index 000000000000..81e5a9cb8900 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B125v2"; + compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts new file mode 100644 index 000000000000..c861937b30f6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B155v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B155v2"; + compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g156xtn01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h84"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi new file mode 100644 index 000000000000..37697fac9dea --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5Pv2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include +#include "imx6dl-qmx6.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + /* Do not allow frequencies above 800MHz */ + cpus { + cpu@0 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + + cpu@1 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + }; + + reg_syspwr: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "SYS_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_5v_pmc: regulator-5v-pmc { + compatible = "regulator-fixed"; + regulator-name = "5V PMC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_syspwr>; + }; + + reg_5v0_audio: regulator-5v0-audio { + compatible = "regulator-fixed"; + regulator-name = "5V0_AUDIO"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This must be always-on for da7212, which has some not + * properly documented dependencies for it's speaker supply + * pin. The issue manifests as speaker volume being very low. + */ + regulator-always-on; + }; + + + reg_3v3_audio: regulator-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-0 = <&pinctrl_q7_hda_reset>; + pinctrl-names = "default"; + gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5_audio: regulator-2v5-audio { + compatible = "regulator-fixed"; + regulator-name = "2V5_AUDIO"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <®_3v3_audio>; + + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "WLAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sdio_power>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; + + reg_bl: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "LED_VCC"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_syspwr>; + pinctrl-0 = <&pinctrl_q7_lcd_power>; + pinctrl-names = "default"; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + usb_power: regulator-usb-power { + compatible = "regulator-fixed"; + regulator-name = "USB POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + charger: battery-charger { + compatible = "gpio-charger"; /* ti,bq24172 */ + charger-type = "mains"; + gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>; + charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>, + <&tca6424a 12 GPIO_ACTIVE_HIGH>; + charge-current-limit-mapping = <1300000 0x0>, + <700000 0x1>, + <0 0x2>; + charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>; + }; + + poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_spi_cs1>; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; + + power-button-key { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sleep_button>; + + power-button { + label = "power button"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + rotary-encoder-key { + compatible = "gpio-keys"; + + rotary-encoder-event { + label = "rotary-encoder press"; + gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,can-disable; + }; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>; + rotary-encoder,relative-axis; + rotary-encoder,steps-per-period = <2>; + wakeup-source; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; + + led-alarm1 { + label = "alarm:red"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + led-alarm2 { + label = "alarm:yellow"; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + }; + + led-alarm3 { + label = "alarm:blue"; + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_backlight_enable>; + power-supply = <®_bl>; + pwms = <&pwm4 0 5000000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <179>; + enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + panel { + backlight = <&backlight>; + power-supply = <®_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = "Speaker", "Ext Spk"; + simple-audio-card,audio-routing = "Ext Spk", "LINE"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + battery: battery@b { + compatible = "ti,bq20z65", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>; + sbs,i2c-retry-count = <5>; + power-supplies = <&charger>; + }; + + codec: audio-codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5_audio>; + VDDSP-supply = <®_5v0_audio>; + VDDMIC-supply = <®_3v3_audio>; + VDDIO-supply = <®_3v3_audio>; + clocks = <&clk_ext_audio_codec>; + clock-names = "mclk"; + }; +}; + +&i2c5 { + tca6424a: gpio-controller@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN", + "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF", + "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0", + "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "", + "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", + "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2"; + + }; + + tmp75: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + vs-supply = <®_3v3>; + interrupt-parent = <&tca6424a>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&usb_power>; + disable-over-current; + dr_mode = "host"; + status = "okay"; + + /* + * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N. + * On QMX6 this is not connceted to the i.MX6, but to the USB Hub + * from &usbh1. This means, that we cannot easily detect and handle + * over-current events. Fortunately the regulator limits the current + * automatically, so the hardware is still protected. + */ +}; + +&usdhc4 { + /* WiFi module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + vmmc-supply = <®_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio7>; + + interrupt-parent = <&gpio4>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi new file mode 100644 index 000000000000..f028b6a191df --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5v2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include +#include "imx6dl-b1x5pv2.dtsi" + +/ { + reg_3v3_acm: regulator-3v3-acm { + compatible = "regulator-fixed"; + regulator-name = "3V3 ACM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_3v3>; + }; +}; + +&i2c1 { + tca6416: gpio-controller@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3v3_acm>; + gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2", + "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1", + "ACM2_CL2", "", "", "", + "", "", "", ""; + + /* + * The interrupt pin is connected to &tca6424a pin 1, but the Linux + * TCA6424 driver cannot handle low type interrupts at the moment + * (and support cannot be added without some ugly hacks). Since this + * controller does not have any input type GPIOs, just pretend + * that the interrupt pin is unconnected. + */ + }; +}; + +&i2c5 { + mpl3115a2: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + + /* + * The MPL3115 interrupts are connected to pin 22 and 23 + * of &tca6424a, but the binding does not yet support + * interrupts. + */ + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts new file mode 100644 index 000000000000..82a0d1a28d12 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; + compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + cs-gpios = < + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_csi_gpio_1 + &pinctrl_gpio_2 + &pinctrl_gpio_aster + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + &pinctrl_weim_gpio_5 + >; + + pinctrl_gpio_aster: gpioaster { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts new file mode 100644 index 000000000000..f50a26dd34c0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* Fixed crystal dedicated to mcp251x */ + clk16m: clock-16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; + + mcp251x0: mcp251x@0 { + compatible = "microchip,mcp2515"; + clocks = <&clk16m>; + interrupt-parent = <&gpio3>; + interrupts = <27 0x2>; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 + &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 + &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 + &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 + >; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; + +&weim { + status = "okay"; + + /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ + ranges = <0 0 0x08000000 0x02000000 + 1 0 0x0a000000 0x02000000 + 2 0 0x0c000000 0x02000000 + 3 0 0x0e000000 0x02000000>; + + /* SRAM on Colibri nEXT_CS0 */ + sram@0,0 { + compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; + reg = <0 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; + + /* SRAM on Colibri nEXT_CS1 */ + sram@1,0 { + compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; + reg = <1 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts new file mode 100644 index 000000000000..3a6d3889760d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>; + + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + cap-power-off-card; + /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */ + /* /delete-property/ no-1-8-v; */ + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts new file mode 100644 index 000000000000..4303c88bb2a9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; + compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>; + + /* + * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one + * wants to turn the transceiver off, that property has to be deleted + * and the gpio handled in userspace. + * The same applies to uart-b-c-on-x14-enable where the UART_B and + * UART_C transceiver is turned on. + */ + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; + + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_gpio_iris + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + >; + + pinctrl_gpio_iris: gpioirisgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1_forceoff: uart1forceoffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts new file mode 100644 index 000000000000..2b2fc360b865 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts new file mode 100644 index 000000000000..e09c565d1d1f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Solo/DualLite (1.5som)"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts new file mode 100644 index 000000000000..2b1b3e193f53 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Solo/DualLite"; + compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts new file mode 100644 index 000000000000..cece4aafdad8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer + */ + +#ifndef __DTS_V1__ +#define __DTS_V1__ +/dts-v1/; +#endif + +#include "imx6dl.dtsi" +#include "imx6qdl-dfi-fs700-m60.dtsi" + +/ { + model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; + compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts new file mode 100644 index 000000000000..038bb0025556 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 + * DHCOM PCB number: 493-300 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-picoitx.dtsi" + +/ { + model = "DH electronics i.MX6DL DHCOM on PicoITX"; + compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som", + "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts new file mode 100644 index 000000000000..33825b5a8f26 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Eckelmann AG. + * Copyright (C) 2013 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include + +#include "imx6dl.dtsi" + +/ { + model = "Eckelmann CI 4X10 Board"; + compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; + + chosen { + stdout-path = &uart3; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + rmii_clk: clock-rmii { + /* This clock is provided by the phy (KSZ8091RNB) */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + siox { + compatible = "eckelmann,siox-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_siox>; + din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + clocks = <&rmii_clk>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&rmii_clk>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "everspin,mr25h256"; + reg = <0>; + spi-max-frequency = <15000000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&gpio2 { + gpio-line-names = "buzzer", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "in2", + "prio2", "prio1", "aux", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "in1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + temperature-sensor@49 { + compatible = "ad,ad7414"; + reg = <0x49>; + }; + + rtc@51 { + compatible = "nxp,pcf2127"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ + + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + /* without SION i2c doesn't detect bus busy */ + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 + >; + }; + + pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 + >; + }; + + pinctrl_siox: sioxgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ + >; + }; + + pinctrl_uart1_dte: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ + >; + }; + + pinctrl_uart2_dte: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 + MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ + >; + }; + + pinctrl_uart3_dce: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 + >; + }; + + pinctrl_uart4_dce: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 + >; + }; + + pinctrl_uart5_dce: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 + >; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte>; + uart-has-rtscts; + fsl,dte-mode; + dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + uart-has-rtscts; + fsl,dte-mode; + dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dce>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_dce>; + rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_dce>; + rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..407ad8d43c84 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts new file mode 100644 index 000000000000..9956d12a1245 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw51xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; + compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts new file mode 100644 index 000000000000..9ea23dd54f3c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; + compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + bus-width = <8>; +}; + +&ipu1_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; + bus-width = <8>; +}; + +&ipu1_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi1: ipu1_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts new file mode 100644 index 000000000000..182e8194c249 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; + compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + bus-width = <8>; +}; + +&ipu1_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; + bus-width = <8>; +}; + +&ipu1_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi1: ipu1_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts new file mode 100644 index 000000000000..a106c4e3e329 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; + compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + bus-width = <8>; +}; + +&ipu1_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; + bus-width = <8>; +}; + +&ipu1_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi1: ipu1_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts new file mode 100644 index 000000000000..82d5f85722ea --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw551x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; + compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts new file mode 100644 index 000000000000..4864a36f9b36 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; + compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts new file mode 100644 index 000000000000..59b8afc36e66 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; + compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts new file mode 100644 index 000000000000..21bdfaf8df53 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw560x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X"; + compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts new file mode 100644 index 000000000000..103261ea9334 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw5903.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903"; + compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts new file mode 100644 index 000000000000..9c6d3cd3d6a7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw5904.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904"; + compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts new file mode 100644 index 000000000000..3fa2822beffc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw5907.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; + compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts new file mode 100644 index 000000000000..0d5e7e5da536 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw5910.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; + compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts new file mode 100644 index 000000000000..5260e0142d63 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw5912.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; + compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts new file mode 100644 index 000000000000..b74e533c8e67 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw5913.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; + compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts new file mode 100644 index 000000000000..a63f742f20d9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts new file mode 100644 index 000000000000..66a06cf3cdf3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Solo/DualLite (1.5som)"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts new file mode 100644 index 000000000000..cbd02eb486e1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Solo/DualLite"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts new file mode 100644 index 000000000000..80313c13bcdb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts @@ -0,0 +1,55 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts new file mode 100644 index 000000000000..e61ef1156f8b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts @@ -0,0 +1,54 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite (1.5som)"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts new file mode 100644 index 000000000000..b12cd87f3f94 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts new file mode 100644 index 000000000000..d8f3821a0ffd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2018 Engicam S.r.l. + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore-1.5.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts new file mode 100644 index 000000000000..73d710d34b9d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore-rqs.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit"; + compatible = "engicam,imx6-icore-rqs", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts new file mode 100644 index 000000000000..80fa60607ab1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c1 { + max11801: touchscreen@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi new file mode 100644 index 000000000000..a864fdbd5f16 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2019 (C) Pengutronix, Marco Felsch + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" + +/ { + model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; + compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts new file mode 100644 index 000000000000..7c62db91173b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2019 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Van der Laan LANMCU"; + compatible = "vdl,lanmcu", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 1000>; + num-interpolated-steps = <20>; + default-brightness-level = <19>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + clocks = <&clock_ksz8081>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clock_ksz8081>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "DEBUG_0", "BL_PWM", "", "", "", "", "", "", + "", "", "", "", "", "", "", "ENET_LED_GREEN", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", + "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "ENET_RST", "ENET_INT", + "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "WLAN_REG_ON", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "EMMC_RST", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts_edt>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + + touchscreen-fuzz-x = <0>; + touchscreen-fuzz-y = <0>; + + /* Touch screen calibration */ + threshold = <50>; + gain = <5>; + offset = <10>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_ts_edt: ts1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts new file mode 100644 index 000000000000..028951955bde --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 BTicino + * Copyright (C) 2018 Amarula Solutions B.V. + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" + +/ { + model = "BTicino i.MX6DL Mamoj board"; + compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ + brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; + default-brightness-level = <7>; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_lcd>; + power-supply = <®_lcd_lr>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_lcd_3v3: regulator-lcd-dvdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-dvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 0>; + enable-active-high; + startup-delay-us = <21000>; + }; + + reg_lcd_power: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "lcd-enable"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 6 0>; + enable-active-high; + vin-supply = <®_lcd_3v3>; + }; + + reg_lcd_vgl: regulator-lcd-vgl { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_power>; + }; + + reg_lcd_vgh: regulator-lcd-vgh { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgh"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_avdd>; + }; + + reg_lcd_vcom: regulator-lcd-vcom { + compatible = "regulator-fixed"; + regulator-name = "lcd-vcom"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <11000>; + enable-active-high; + vin-supply = <®_lcd_vgh>; + }; + + reg_lcd_lr: regulator-lcd-lr { + compatible = "regulator-fixed"; + regulator-name = "lcd-lr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_lcd_vcom>; + }; + + reg_lcd_avdd: regulator-lcd-avdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-avdd"; + regulator-min-microvolt = <10280000>; + regulator-max-microvolt = <10280000>; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_vgl>; + }; + + reg_usb_host: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbhost-vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhost>; + regulator-min-microvolt = <50000000>; + regulator-max-microvolt = <50000000>; + gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wl18xx_vmmc: regulator-wl18xx-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + /* CPU vdd_arm core */ + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* SOC vdd_soc */ + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* I/O power GEN_3V3 */ + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* DDR memory */ + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + /* DDR memory */ + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + /* not used */ + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + /* not used */ + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + /* PMIC vsnvs. EX boot mode */ + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* not used */ + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + /* not used */ + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + /* not used */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + /* 1v8 general power */ + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* 2v8 general power IMX6 */ + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* 3v3 Ethernet */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 + MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 + MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 + MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbhost: usbhostgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi new file mode 100644 index 000000000000..b749b424bbd6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <0>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <300>; + txd0-skew-ps = <120>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts new file mode 100644 index 000000000000..df0a96b28af0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", + "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts new file mode 100644 index 000000000000..610b19d2db0f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", + "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts new file mode 100644 index 000000000000..61fa30991d67 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2015 Boundary Devices, Inc. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-nit6xlite.dtsi" + +/ { + model = "Boundary Devices i.MX6 Solo Nitrogen6_Lite Board"; + compatible = "boundary,imx6dl-nit6xlite", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts new file mode 100644 index 000000000000..ef58d3b0ea0d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; + compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts new file mode 100644 index 000000000000..d906a7f05aaa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; + compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; +}; + +ðphy { + max-speed = <100>; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts new file mode 100644 index 000000000000..0a07cc6f815e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +/dts-v1/; +#include "imx6dl-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; + compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..6f8aaf524425 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; + compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts new file mode 100644 index 000000000000..d85b15a8c127 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; + compatible = "technexion,imx6dl-pico-dwarf", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts new file mode 100644 index 000000000000..08fedcbcc91b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-hobbit.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; + compatible = "technexion,imx6dl-pico-hobbit", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts new file mode 100644 index 000000000000..32ccfc5d41ce --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; + compatible = "technexion,imx6dl-pico-nymph", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts new file mode 100644 index 000000000000..4590e8ad9a91 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; + compatible = "technexion,imx6dl-pico-pi", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h new file mode 100644 index 000000000000..9d88d09f9bf6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h @@ -0,0 +1,1088 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX6DL_PINFUNC_H +#define __DTS_IMX6DL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 +#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 +#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 +#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 +#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 +#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 +#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 +#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 +#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 +#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 +#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 +#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 +#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 +#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 +#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 +#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 +#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 +#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 +#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 +#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 +#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 +#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 +#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 +#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 +#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 +#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 +#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 +#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 +#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 +#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 +#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 +#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 +#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 +#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 +#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 +#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 +#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 +#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 +#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 +#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 +#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 +#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 +#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 +#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 +#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 +#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 +#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 +#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 +#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 +#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 +#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 +#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 +#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 +#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 +#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 +#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 +#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 +#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 +#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 +#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 +#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 +#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 +#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 +#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 +#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 +#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 +#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0 +#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 +#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 +#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 +#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 +#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 +#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 +#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 +#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 +#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 +#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 +#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 +#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 +#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 +#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 +#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 +#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 +#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 +#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 +#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 +#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 +#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 +#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 +#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 +#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 +#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 +#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 +#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 +#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 +#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 +#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 +#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 +#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 +#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 +#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 +#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 +#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 +#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 +#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 +#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 +#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 +#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 +#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 +#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 +#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 +#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 +#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 +#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 +#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 +#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 +#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 +#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 +#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 +#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 +#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 +#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 +#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 +#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 +#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 +#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 +#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 +#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 +#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 +#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 +#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 +#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 +#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 +#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 +#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 +#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 +#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 +#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 +#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 +#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 +#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 +#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 +#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 +#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 +#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 +#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 +#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 +#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 +#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 +#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 +#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 +#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 +#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 +#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 +#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 +#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 +#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 +#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 +#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 +#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 +#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 +#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 +#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 +#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 +#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 +#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 +#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 +#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 +#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 +#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 +#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 +#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 +#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 +#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 +#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 +#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 +#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 +#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 + +#endif /* __DTS_IMX6DL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts new file mode 100644 index 000000000000..84f34da06267 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Plymovent BAS board"; + compatible = "ply,plybas", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + gpio_keys { + compatible = "gpio-keys"; + autorepeat; + + button-start { + label = "START"; + linux,code = <31>; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + }; + + button-clean { + label = "CLEAN"; + linux,code = <46>; + gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "debug1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "light_tower1"; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-3 { + label = "light_tower2"; + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "light_tower3"; + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "light_tower4"; + gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; + }; + + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "ECSPI1_SS1", "", "USB_EXT_PWR", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", + "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "IMX6_IN12", "IMX6_HMI", + "IMX6_IN11", "IMX6_BUZZER", "IMX6_LED1", "IMX6_LED2", + "IMX6_LED3", "IMX6_LED4", "ETH_RESET", "IMX6_ANA_OUT_SD", + "IMX6_ANA_OUT_ERR", "IMX6_ANA_OUT", "ETH_INTRP", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "IMX6_RELAY1", "IMX6_RELAY2", "", + "IMX6_IN1", "IMX6_IN2", "IMX6_IN3", "IMX6_IN4", "IMX6_IN5", + "IMX6_IN6", "IMX6_IN7", "IMX6_IN8", + "IMX6_IN9", "IMX6_IN10", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 20>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG_0 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + /* DEBUG_1 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + + /* LED1 (lighttower) */ + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x13070 + /* LED2 (lighttower) */ + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x13070 + /* LED3 (lighttower) */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x13070 + /* LED4 (lighttower) */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x13070 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts new file mode 100644 index 000000000000..dfa8110b1d97 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Plymovent M2M board"; + compatible = "ply,plym2m", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 1000>; + num-interpolated-steps = <20>; + default-brightness-level = <19>; + power-supply = <®_12v0>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; + reg = <0>; + pinctrl-0 = <&pinctrl_tsc2046>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@2 { + reg = <2>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + /* channel 6 is not connected */ + + channel@7 { + reg = <7>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "", "", "", "", "", "", + "DEBUG_0", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ECSPI2_SS0", "", "", "", "TSC_BUSY", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "ECSPI1_SS1", "TSC_PENIRQ", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "ETH_RESET", "ETH_INTRP", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x10000 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x3008 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x3008 + /* CS */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_tsc2046: tsc2046grp { + fsl,pins = < + /* TSC_PENIRQ */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 + /* TSC_BUSY */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts new file mode 100644 index 000000000000..773a84a5739d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Protonic MVT board"; + compatible = "prt,prtmvt", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <1>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = ; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + key-power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-f1 { + label = "GPIO Key F1"; + linux,code = ; + gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; + }; + + key-f2 { + label = "GPIO Key F2"; + linux,code = ; + gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; + }; + + key-f3 { + label = "GPIO Key F3"; + linux,code = ; + gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; + }; + + key-f4 { + label = "GPIO Key F4"; + linux,code = ; + gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; + }; + + key-f5 { + label = "GPIO Key F5"; + linux,code = ; + gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; + }; + + key-cycle { + label = "GPIO Key CYCLE"; + linux,code = ; + gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; + }; + + key-esc { + label = "GPIO Key ESC"; + linux,code = ; + gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; + }; + + key-up { + label = "GPIO Key UP"; + linux,code = ; + gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; + }; + + key-down { + label = "GPIO Key DOWN"; + linux,code = ; + gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; + }; + + key-ok { + label = "GPIO Key OK"; + linux,code = ; + gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; + }; + + key-f6 { + label = "GPIO Key F6"; + linux,code = ; + gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; + }; + + key-f7 { + label = "GPIO Key F7"; + linux,code = ; + gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; + }; + + key-f8 { + label = "GPIO Key F8"; + linux,code = ; + gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; + }; + + key-f9 { + label = "GPIO Key F9"; + linux,code = ; + gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; + }; + + key-f10 { + label = "GPIO Key F10"; + linux,code = ; + gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; + }; + + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "debug1"; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + + led-2 { + label = "power_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + panel { + compatible = "kyo,tcg070wvlq", "lg,lb070wv8"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <&rmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <3000>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", + "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "", "", "", "", "", "", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", + "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "", "", "", "", + "CPU_LIGHT_ON", "", "ETH_RESET", "", "BL_EN", + "BL_PWM", "ETH_INTRP", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + video@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; + + gpio_pca: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9539>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_h1_vbus>; + pinctrl-names = "default"; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* CAM1_MIRROR */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* CAM2_MIRROR */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 + /* CAM_nDETECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* ISB_IN1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + /* ISB_nIN2 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + /* WARN_LIGHT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 + /* ON2_FB */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 + /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 + /* YACO_nRESET */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + /* FORCE_ON1 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + + /* HW revision detect */ + /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + /* REV_ID4 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + + /* New in HW revision 1 */ + /* ON1_FB */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 + /* DIP1_FB */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG0 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + /* DEBUG1 */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* POWER_LED */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + >; + }; + + pinctrl_pca9539: pca9539 { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + /* YaCO Touchscreen UART */ + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts new file mode 100644 index 000000000000..36b031236e47 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include + +/ { + model = "Protonic RVT board"; + compatible = "prt,prtrvt", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + nfc@0 { + compatible = "ti,trf7970a"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + spi-max-frequency = <2000000>; + interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; + ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>; + vin-supply = <®_3v3>; + autosuspend-delay = <30000>; + irq-status-read-quirk; + en2-rf-quirk; + status = "okay"; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* nc */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* nc */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pcie { + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&usbotg { + disable-over-current; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + /* NFC_ASK_OOK */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 + /* NFC_PWR_EN */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 + /* NFC_EN2 */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 + /* NFC_EN */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + /* NFC_MOD */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + /* NFC_IRQ */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts new file mode 100644 index 000000000000..568e98cb62aa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include +#include +#include +#include + +/ { + model = "Protonic VT7"; + compatible = "prt,prtvt7", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + brightness-levels = <0 20 81 248 1000>; + default-brightness-level = <65>; + num-interpolated-steps = <21>; + power-supply = <®_bl_12v0>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + + key-esc { + label = "GPIO Key ESC"; + linux,code = ; + gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; + }; + + key-up { + label = "GPIO Key UP"; + linux,code = ; + gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; + }; + + key-down { + label = "GPIO Key DOWN"; + linux,code = ; + gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; + }; + + key-enter { + label = "GPIO Key Enter"; + linux,code = ; + gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; + }; + + key-cycle { + label = "GPIO Key CYCLE"; + linux,code = ; + gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; + }; + + key-f1 { + label = "GPIO Key F1"; + linux,code = ; + gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; + }; + + key-f2 { + label = "GPIO Key F2"; + linux,code = ; + gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; + }; + + key-f3 { + label = "GPIO Key F3"; + linux,code = ; + gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; + }; + + key-f4 { + label = "GPIO Key F4"; + linux,code = ; + gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; + }; + + key-f5 { + label = "GPIO Key F5"; + linux,code = ; + gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; + }; + + key-f6 { + label = "GPIO Key F6"; + linux,code = ; + gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; + }; + + key-f7 { + label = "GPIO Key F7"; + linux,code = ; + gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; + }; + + key-f8 { + label = "GPIO Key F8"; + linux,code = ; + gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; + }; + + key-f9 { + label = "GPIO Key F9"; + linux,code = ; + gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; + }; + + key-f10 { + label = "GPIO Key F10"; + linux,code = ; + gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "innolux,g070y2-t02"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = ; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + + reg_bl_12v0: regulator-bl-12v0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_bl_12v0>; + regulator-name = "bl-12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; + reg = <0>; + pinctrl-0 = <&pinctrl_tsc>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + }; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + video@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; +}; + +&i2c3 { + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; + + gpio_pca: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&ipu1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 + + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 + + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 + + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_reg_bl_12v0: 12blgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi new file mode 100644 index 000000000000..05fd8ff4da1e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for i.MX6DL based congatec QMX6 +// System on Module +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora +// Copyright 2016 congatec AG + +#include "imx6dl.dtsi" +#include +#include + +/ { + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c2>; + + i2c5: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + mux-ssi1 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) + >; + }; + + mux-aud6 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&clks { + clocks = <&rtc_sqw>; + clock-names = "ckil"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf032b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "bootloader"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "user"; + reg = <0x0100000 0x2fc000>; + }; + + partition@3fc000 { + label = "reserved"; + reg = <0x03fc000 0x4000>; + read-only; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@6 { + reg = <6>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + rtc: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + + rtc_sqw: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&i2c6 { + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* + * keep VGEN3, VGEN4 and VGEN5 enabled in order to + * maintain backward compatibility with hw-rev. A.0 + */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* supply voltage for eMMC */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&pcie { + reset-gpio = <&gpio1 20 0>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; +}; + +&usdhc2 { + /* MicroSD card slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + /* eMMC module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + qmx6mux: imx6qdl-qmx6 { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ + >; + }; + + /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ + pinctrl_enet: enet { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ + >; + }; + + pinctrl_i2c1: i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ + >; + }; + + pinctrl_i2c2: i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ + >; + }; + + pinctrl_i2c3: i2c3 { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ + >; + }; + + pinctrl_phy_reset: phy-reset { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ + >; + }; + + pinctrl_pwm4: pwm4 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ + >; + }; + + pinctrl_q7_backlight_enable: q7-backlight-enable { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ + >; + }; + + pinctrl_q7_gpio0: q7-gpio0 { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ + >; + }; + + pinctrl_q7_gpio1: q7-gpio1 { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ + >; + }; + + pinctrl_q7_gpio2: q7-gpio2 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ + >; + }; + + pinctrl_q7_gpio3: q7-gpio3 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ + >; + }; + + pinctrl_q7_gpio4: q7-gpio4 { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ + >; + }; + + pinctrl_q7_gpio5: q7-gpio5 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ + >; + }; + + pinctrl_q7_gpio6: q7-gpio6 { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ + >; + }; + + pinctrl_q7_gpio7: q7-gpio7 { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ + >; + }; + + pinctrl_q7_hda_reset: q7-hda-reset { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ + >; + }; + + pinctrl_q7_lcd_power: lcd-power { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ + >; + }; + + pinctrl_q7_sdio_power: q7-sdio-power { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ + >; + }; + + pinctrl_q7_sleep_button: q7-sleep-button { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ + >; + }; + + pinctrl_q7_spi_cs1: spi-cs1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ + >; + }; + + /* SPI1 bus does not leave System on Module */ + pinctrl_spi1: spi1 { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + /* Debug connector on Q7 module */ + pinctrl_uart2: uart2 { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ + >; + }; + + pinctrl_usbotg: usbotg { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ + >; + }; + + /* µSD card slot on Q7 module */ + pinctrl_usdhc2: usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ + >; + }; + + /* eMMC module on Q7 module */ + pinctrl_usdhc3: usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ + >; + }; + + pinctrl_wdog: wdog { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts new file mode 100644 index 000000000000..b72f8ea1e6f6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 FEDEVEL, Inc. + * + * Author: Robert Nelson + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-rex.dtsi" + +/ { + model = "Rex Basic i.MX6 Dual Lite Board"; + compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&ecspi3 { + flash: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts new file mode 100644 index 000000000000..0366d1037ef4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 Iain Paton + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include + +/ { + model = "RIoTboard i.MX6S"; + compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6-riotboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + fsl,pmic-stby-poweroff; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + qca,smarteee-tw-us-1g = <24>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", + "I2C3_SDA", "I2C4_SCL", + "I2C4_SDA", "", "", "", "", "", "", "", + "", "PWM3", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "USB_OTG_VBUS", "", + "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", + "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", + "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", + "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", + "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; +}; + +&gpio5 { + gpio-line-names = + "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", + "GPIO5_07", + "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", + "CSPI2_CS0", "CSPI2_CLK", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "SD3_CD", "SD3_WP", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + interrupt-parent = <&gpio5>; + interrupts = <16 8>; + fsl,pmic-stby-poweroff; + + regulators { + reg_vddcore: sw1ab { /* VDDARM_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { /* VDDSOC_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { /* VDDHIGH_IN */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_vtt: sw4 { /* MIPI conn */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { /* not used */ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { /* VREF_DDR */ + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { /* not used */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { /* not used */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&clks 116>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6-riotboard { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts new file mode 100644 index 000000000000..ff3283c83a39 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2013 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sabreauto.dtsi" + +/ { + model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; + compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1200000 + 792000 1175000 + 396000 1175000 + >; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts new file mode 100644 index 000000000000..33040761b253 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-sabrelite.dtsi" + +/ { + model = "Freescale i.MX6 DualLite SABRE Lite Board"; + compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts new file mode 100644 index 000000000000..cd6bbf22a16f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2013 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sabresd.dtsi" + +/ { + model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; + compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts new file mode 100644 index 000000000000..b95469c520a4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-savageboard.dtsi" + +/ { + model = "Poslab SavageBoard Dual"; + compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts new file mode 100644 index 000000000000..b12b5aabe70a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-skov-cpu.dtsi" +#include "imx6qdl-skov-cpu-revc.dtsi" +#include "imx6qdl-skov-revc-lt2.dtsi" + +/ { + model = "SKOV IMX6 CPU SoloCore"; + compatible = "skov,imx6dl-skov-revc-lt2", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts new file mode 100644 index 000000000000..5dcc433fe2af --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-skov-cpu.dtsi" +#include "imx6qdl-skov-cpu-revc.dtsi" + +/ { + model = "SKOV IMX6 CPU SoloCore"; + compatible = "skov,imx6dl-skov-revc-lt6", "fsl,imx6dl"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; + pwms = <&pwm2 0 20000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <17>; + default-brightness-level = <8>; + power-supply = <®_24v0>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l6wh-rt"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts new file mode 100644 index 000000000000..2a3699adbed0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-solidsense.dtsi" + +/ { + model = "SolidRun SolidSense Solo/DualLite (1.5som+emmc)"; + compatible = "solidrun,solidsense/dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi new file mode 100644 index 000000000000..e891ef9b0091 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi new file mode 100644 index 000000000000..38cd8501a886 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts new file mode 100644 index 000000000000..3d60cc725d9e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts4900.dtsi" + +/ { + model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; + compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts new file mode 100644 index 000000000000..5da6feba2e66 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts @@ -0,0 +1,56 @@ +/* + * Copyright 2015 Technologic Systems + * Copyright 2017 Savoir-faire Linux + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7970.dtsi" + +/ { + model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; + compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts new file mode 100644 index 000000000000..51a9bb9d6bc2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts @@ -0,0 +1,79 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; + +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&kpp { + status = "disabled"; +}; + +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + +®_can_xcvr { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts new file mode 100644 index 000000000000..fc23b4d291a1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6s-8034.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts new file mode 100644 index 000000000000..9eb2ef17339c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2015-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8034 Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + cpus { + /delete-node/ cpu@1; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&pinctrl_usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ + >; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts new file mode 100644 index 000000000000..4101c6597721 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6s-8035.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts new file mode 100644 index 000000000000..a5532ecc18c5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2015-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8035 Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + cpus { + /delete-node/ cpu@1; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts new file mode 100644 index 000000000000..67ed0452f5de --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-801x Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts new file mode 100644 index 000000000000..d34189fc52d9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-8033.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts new file mode 100644 index 000000000000..7030b2654bbd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts @@ -0,0 +1,82 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8033 Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts new file mode 100644 index 000000000000..aef5fcc42904 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-801x.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts new file mode 100644 index 000000000000..5342f2f5a8a8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-811x Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts new file mode 100644 index 000000000000..c4588fb0bf6f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2016-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-811x.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts new file mode 100644 index 000000000000..d871cac1711f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Udoo i.MX6 Dual-lite Board"; + compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts new file mode 100644 index 000000000000..4875afadb630 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland TGO"; + compatible = "kvg,victgo", "fsl,imx6dl"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + key-power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-enter { + label = "Rotary Key"; + gpios = <&gpio2 05 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; + }; + + panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-0 = <&pinctrl_rotary_ch>; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>, + <&gpio2 4 GPIO_ACTIVE_HIGH>; + linux,axis = ; + rotary-encoder,steps-per-period = <4>; + rotary-encoder,relative-axis; + rotary-encoder,rollover; + wakeup-source; + }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; + + vdiv_hitch_pos: voltage-divider-hitch-pos { + compatible = "voltage-divider"; + io-channels = <&adc_ts 6>; + output-ohms = <3300>; + full-ohms = <13300>; + #io-channel-cells = <0>; + }; +}; + +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + +&ecspi2 { + cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; + reg = <0>; + pinctrl-0 = <&pinctrl_touchscreen>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <&rmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "", "", "", "", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN", + "BL_PWM", "ETH_INT", "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO", + "ECSPI2_SS0", "ECSPI2_SCLK", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + keypad@70 { + compatible = "holtek,ht16k33"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keypad>; + reg = <0x70>; + refresh-rate-hz = <20>; + debounce-delay-ms = <50>; + interrupts-extended = <&gpio4 5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + keypad,num-rows = <12>; + keypad,num-columns = <3>; + linux,keymap = < + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(3, 0, KEY_F8) + MATRIX_KEY(4, 0, KEY_F10) + MATRIX_KEY(5, 0, KEY_F4) + MATRIX_KEY(6, 0, KEY_F2) + MATRIX_KEY(2, 1, KEY_F5) + MATRIX_KEY(3, 1, KEY_F7) + MATRIX_KEY(4, 1, KEY_F9) + MATRIX_KEY(5, 1, KEY_F3) + MATRIX_KEY(6, 1, KEY_F1) + >; + }; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* ROTARY_BTN */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; + + pinctrl_keypad: keypadgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_rotary_ch: rotarychgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts new file mode 100644 index 000000000000..5035d303447d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" + +/ { + model = "Kverneland UT1 Board"; + compatible = "kvg,vicut1", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts new file mode 100644 index 000000000000..c2946fbaa0dd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revb1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board rev B1"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts new file mode 100644 index 000000000000..6d1d863c2e3a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board revD1"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts new file mode 100644 index 000000000000..4a08d5a99452 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revc1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi new file mode 100644 index 000000000000..3be38a3c4bb1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +#include +#include +#include +#include +#include + +/ { + aliases: aliases { + ethernet1 = ð1; + ethernet2 = ð2; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 32 64 128 255>; + default-brightness-level = <32>; + num-interpolated-steps = <8>; + power-supply = <&sw2_reg>; + status = "disabled"; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + compatible = "dataimage,scf0700c48ggu18"; + power-supply = <&sw2_reg>; + backlight = <&backlight>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-supply = <&sw2_reg>; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + switch@10 { + compatible = "qca,qca8334"; + reg = <10>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "rgmii-id"; + ethernet = <&fec>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + eth2: port@2 { + reg = <2>; + label = "eth2"; + phy-handle = <&phy_port2>; + }; + + eth1: port@3 { + reg = <3>; + label = "eth1"; + phy-handle = <&phy_port3>; + }; + }; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c2>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze200"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vsnvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + leds: led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + clock-mode = /bits/ 8 <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + led@0 { + chan-name = "R"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <0>; + color = ; + }; + + led@1 { + chan-name = "G"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <1>; + color = ; + }; + + led@2 { + chan-name = "B"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <2>; + color = ; + }; + }; + + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + pagesize = <64>; + }; + + touchscreen: touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + status = "disabled"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + oled_1309: oled@3c { + compatible = "solomon,ssd1309fb-i2c"; + reg = <0x3c>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,segment-no-remap; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + oled_1305: oled@3d { + compatible = "solomon,ssd1305fb-i2c"; + reg = <0x3d>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,col-offset = <4>; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_oled: gpio@41 { + compatible = "nxp,pca9536"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x41>; + vcc-supply = <&sw2_reg>; + status = "disabled"; + }; + + touchkeys: keys@5a { + compatible = "fsl,mpr121-touchkey"; + reg = <0x5a>; + vdd-supply = <&sw2_reg>; + autorepeat; + linux,keycodes = , , , , , + , , , , + , , ; + poll-interval = <50>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + over-current-active-low; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <109>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&sw2_reg>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts new file mode 100644 index 000000000000..a38c407fd837 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Draco i.MX6Solo board"; + compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchscreen { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts new file mode 100644 index 000000000000..a19609c7c7c0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Hydra i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +®_pcie { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts new file mode 100644 index 000000000000..5c2cd517589b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Lynx i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-lynx", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchscreen { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts new file mode 100644 index 000000000000..884b236746bb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2020 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Orion i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts new file mode 100644 index 000000000000..e0292f11d03e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Phoenix i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-phoenix", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&aliases { + /delete-property/ ethernet1; +}; + +&gpio_keys { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&switch_ports { + /delete-node/ port@2; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts new file mode 100644 index 000000000000..f6ae24efd4aa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Ursa i.MX6Solo board"; + compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&aliases { + /delete-property/ ethernet1; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&switch_ports { + /delete-node/ port@3; +}; + +&touchscreen { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi new file mode 100644 index 000000000000..52a0f6ee426f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +#include +#include +#include +#include +#include + +/ { + aliases: aliases { + ethernet1 = ð1; + ethernet2 = ð2; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 32 64 128 255>; + default-brightness-level = <32>; + num-interpolated-steps = <8>; + power-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + button { + label = "Factory RESET"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + compatible = "dataimage,scf0700c48ggu18"; + power-supply = <&sw2_reg>; + backlight = <&backlight>; + enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-supply = <&sw2_reg>; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "rgmii-id"; + ethernet = <&fec>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + eth2: port@1 { + reg = <1>; + label = "eth2"; + phy-handle = <&phy_port1>; + }; + + eth1: port@2 { + reg = <2>; + label = "eth1"; + phy-handle = <&phy_port2>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: switchphy@11 { + reg = <0x11>; + }; + + phy_port2: switchphy@12 { + reg = <0x12>; + }; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze200"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vsnvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + leds: led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + clock-mode = /bits/ 8 <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + led@0 { + chan-name = "R"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <0>; + color = ; + }; + + led@1 { + chan-name = "G"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <1>; + color = ; + }; + + led@2 { + chan-name = "B"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <2>; + color = ; + }; + }; + + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + pagesize = <64>; + }; + + touchscreen: touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + status = "disabled"; + }; + + rtc: rtc@68 { + compatible = "dallas,ds1341"; + reg = <0x68>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + oled_1309: oled@3c { + compatible = "solomon,ssd1309fb-i2c"; + reg = <0x3c>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,segment-no-remap; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + oled_1305: oled@3d { + compatible = "solomon,ssd1305fb-i2c"; + reg = <0x3d>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,col-offset = <4>; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_oled: gpio@41 { + compatible = "nxp,pca9536"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x41>; + vcc-supply = <&sw2_reg>; + status = "disabled"; + }; + + touchkeys: keys@5a { + compatible = "fsl,mpr121-touchkey"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchkeys>; + reg = <0x5a>; + vdd-supply = <&sw2_reg>; + autorepeat; + linux,keycodes = , , , , , + , , , , + , , ; + poll-interval = <50>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 + >; + }; + + pinctrl_touchkeys: touchkeysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b098 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + over-current-active-low; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <109>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi new file mode 100644 index 000000000000..dc919e09a505 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. + +#include +#include "imx6dl-pinfunc.h" +#include "imx6qdl.dtsi" + +/ { + aliases { + i2c3 = &i2c4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + }; + + soc: soc { + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + aips1: bus@2000000 { + pxp: pxp@20f0000 { + reg = <0x020f0000 0x4000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + epdc: epdc@20f4000 { + reg = <0x020f4000 0x4000>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + aips2: bus@2100000 { + i2c4: i2c@21f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6DL_CLK_I2C4>; + status = "disabled"; + }; + }; + }; + + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu1_di0>, <&ipu1_di1>; + }; +}; + +&gpio1 { + gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, + <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, + <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, + <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, + <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, + <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, + <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; +}; + +&gpio2 { + gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, + <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, + <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, + <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, + <&iomuxc 28 113 4>; +}; + +&gpio3 { + gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, + <&iomuxc 16 81 16>; +}; + +&gpio4 { + gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, + <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, + <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, + <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, + <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; +}; + +&gpio5 { + gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, + <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, + <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, + <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; +}; + +&gpio6 { + gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, + <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, + <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, + <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, + <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, + <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; +}; + +&gpio7 { + gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, + <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, + <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; +}; + +&gpr { + ipu1_csi0_mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu1_csi0_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_csi0_mux_from_mipi_vc1: endpoint { + remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; + }; + }; + + port@2 { + reg = <2>; + + ipu1_csi0_mux_from_mipi_vc2: endpoint { + remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; + }; + }; + + port@3 { + reg = <3>; + + ipu1_csi0_mux_from_mipi_vc3: endpoint { + remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; + }; + }; + + port@4 { + reg = <4>; + + ipu1_csi0_mux_from_parallel_sensor: endpoint { + }; + }; + + port@5 { + reg = <5>; + + ipu1_csi0_mux_to_ipu1_csi0: endpoint { + remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; + }; + }; + }; + + ipu1_csi1_mux { + compatible = "video-mux"; + mux-controls = <&mux 1>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu1_csi1_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_csi1_mux_from_mipi_vc1: endpoint { + remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; + }; + }; + + port@2 { + reg = <2>; + + ipu1_csi1_mux_from_mipi_vc2: endpoint { + remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; + }; + }; + + port@3 { + reg = <3>; + + ipu1_csi1_mux_from_mipi_vc3: endpoint { + remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; + }; + }; + + port@4 { + reg = <4>; + + ipu1_csi1_mux_from_parallel_sensor: endpoint { + }; + }; + + port@5 { + reg = <5>; + + ipu1_csi1_mux_to_ipu1_csi1: endpoint { + remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; + }; + }; + }; +}; + +&gpt { + compatible = "fsl,imx6dl-gpt"; +}; + +&hdmi { + compatible = "fsl,imx6dl-hdmi"; +}; + +&iomuxc { + compatible = "fsl,imx6dl-iomuxc"; +}; + +&ipu1_csi1 { + ipu1_csi1_from_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; + }; +}; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; +}; + +&mipi_csi { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + + mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; + }; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; + }; + + mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; + }; + + mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; + }; + }; + + port@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; + }; + + mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; + }; + }; +}; + +&mux { + mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ + <0x34 0x00000038>, /* IPU_CSI1_MUX */ + <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ + <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ + <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ + <0x28 0x00000003>, /* DCIC1_MUX_CTL */ + <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ +}; + +&vpu { + compatible = "fsl,imx6dl-vpu", "cnm,coda960"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts new file mode 100644 index 000000000000..3fc079dfd61e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; + compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", + "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "pcie_switch"; + startup-delay-us = <100000>; + status = "okay"; + }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SW"; + }; +}; + +&can1 { + xceiver-supply = <®_3v3_sw>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_3v3_sw>; + status = "okay"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + status = "okay"; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + vpcie-supply = <®_pcie_switch>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + status = "okay"; +}; + +/* SD1 */ +&usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts new file mode 100644 index 000000000000..44637d606e61 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +#include "imx6q-apalis-ixora-v1.2.dts" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; + compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q", + "fsl,imx6q"; + + +}; + +/delete-node/ &eeprom; +/delete-node/ ®_3v3_vmmc; +/delete-node/ ®_can1_supply; +/delete-node/ ®_can2_supply; + +&can1 { + /delete-property/ xceiver-supply; +}; + +&can2 { + /delete-property/ xceiver-supply; +}; + +/* MMC1 */ +&usdhc1 { + /delete-property/ cap-power-off-card; + /delete-property/ pinctrl-1; + /delete-property/ vmmc-supply; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts new file mode 100644 index 000000000000..717decda0ceb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2"; + compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q", + "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + led4-green { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "LED_4_GREEN"; + }; + + led4-red { + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + label = "LED_4_RED"; + }; + + led5-green { + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED_5_GREEN"; + }; + + led5-red { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "LED_5_RED"; + }; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; + + reg_can1_supply: regulator-can1-supply { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "can1_supply"; + }; + + reg_can2_supply: regulator-can2-supply { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "can2_supply"; + }; +}; + +&can1 { + xceiver-supply = <®_can1_supply>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_can2_supply>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart24_forceoff>; + + /* + * uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis + * UART2 and UART3. If one wants to disable the transceiver force + * the GPIO to output-low, if one wants to control the transceiver + * from user space delete the hog node. + */ + uart-2-4-on-x21-enable-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */ + output-high; + }; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>; + bus-width = <4>; + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + >; + }; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + /* MMC1 CD */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0 + >; + }; + + pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts new file mode 100644 index 000000000000..f338be435277 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board"; + compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", + "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + led4-green { + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + label = "LED_4_GREEN"; + }; + + led4-red { + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + label = "LED_4_RED"; + }; + + led5-green { + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED_5_GREEN"; + }; + + led5-red { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "LED_5_RED"; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* SD1 */ +&usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + status = "okay"; +}; + +&iomuxc { + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts new file mode 100644 index 000000000000..664b0af8f0bb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Armadeus Systems + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-apf6.dtsi" +#include "imx6qdl-apf6dev.dtsi" + +/ { + model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; + compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts new file mode 100644 index 000000000000..75586299d9ca --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* gpmi nand conflicts with SD */ +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts new file mode 100644 index 000000000000..d994b32ad825 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts @@ -0,0 +1,157 @@ +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-bx50v3.dtsi" + +/ { + model = "General Electric B450v3"; + compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + chosen { + stdout-path = &uart3; + }; + + panel-lvds0 { + compatible = "innolux,g121x1-l03"; + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pca9539 { + gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", + "", "SM_D_ACT", "DP1_RST#", "", + "WD15S_EN", "WD15S_DIS#", "", "", + "", "", "", ""; + + P04-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "PCA9539-P04"; + }; + + P07-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; +}; + +&pci_root { + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00010000 0 0 0 0>; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "enacq"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport1"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; + + port@5 { + reg = <5>; + label = "enembc"; + + /* connected to Ethernet MAC of AT91RM9200 in MII mode */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts new file mode 100644 index 000000000000..fa1a1df37cde --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts @@ -0,0 +1,156 @@ +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-bx50v3.dtsi" + +/ { + model = "General Electric B650v3"; + compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + chosen { + stdout-path = &uart3; + }; + + panel-lvds0 { + compatible = "innolux,g121x1-l03"; + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pca9539 { + gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", + "", "SM_D_ACT", "DP1_RST#", "", + "WD15S_EN", "WD15S_DIS#", "", "", + "", "", "", ""; + + P07-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; +}; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <55>; + fsl,tx-cal-45-dp-ohms = <55>; + fsl,tx-d-cal = <100>; +}; + +&pci_root { + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00010000 0 0 0 0>; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "enacq"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport1"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; + + port@5 { + reg = <5>; + label = "enembc"; + + /* connected to Ethernet MAC of AT91RM9200 in MII mode */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts new file mode 100644 index 000000000000..db8c332df6a1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts @@ -0,0 +1,295 @@ +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-bx50v3.dtsi" + +/ { + model = "General Electric B850v3"; + compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + chosen { + stdout-path = &uart3; + }; +}; + +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&stdp4028_in>; + }; + }; + }; +}; + +&i2c2 { + pca9547_ddc: mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + mux2_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mux2_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + mux2_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + mux2_i2c4: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + mux2_i2c5: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + mux2_i2c6: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + mux2_i2c7: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + + mux2_i2c8: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&mux2_i2c1>; +}; + +&mux1_i2c1 { + ads7830@4a { + compatible = "ti,ads7830"; + reg = <0x4a>; + }; +}; + +&mux2_i2c2 { + clock-frequency = <100000>; + + stdp2690@72 { + compatible = "megachips,stdp2690-ge-b850v3-fw"; + reg = <0x72>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + stdp2690_in: endpoint { + remote-endpoint = <&stdp4028_out>; + }; + }; + + port@1 { + reg = <1>; + + stdp2690_out: endpoint { + /* Connector for external display */ + }; + }; + }; + }; + + stdp4028@73 { + compatible = "megachips,stdp4028-ge-b850v3-fw"; + reg = <0x73>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + stdp4028_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + + stdp4028_out: endpoint { + remote-endpoint = <&stdp2690_in>; + }; + }; + }; + }; +}; + +&pca9539 { + gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN", + "REMOTE_ON_PML#", "SM_D_ACT", "DP1_RST#", "DP2_RST#", + "", "", "", "", + "", "", "", ""; + + P10-hog { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "PCA9539-P10"; + }; + + P11-hog { + gpio-hog; + gpios = <9 0>; + output-low; + line-name = "PCA9539-P11"; + }; +}; + +&pci_root { + /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ + bridge@1,0 { + compatible = "pci10b5,8605"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bridge@2,1 { + compatible = "pci10b5,8605"; + reg = <0x00020800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Intel Corporation I210 Gigabit Network Connection */ + ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00030000 0 0 0 0>; + }; + }; + + bridge@2,2 { + compatible = "pci10b5,8605"; + reg = <0x00021000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@4,0 { + compatible = "pci8086,1533"; + reg = <0x00040000 0 0 0 0>; + }; + }; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "eneport1"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport2"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi new file mode 100644 index 000000000000..f266f1b7e0cf --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi @@ -0,0 +1,661 @@ +/* + * Support for imx6 based Advantech DMS-BA16 Qseven module + * + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6q.dtsi" +#include + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display>; + pwms = <&pwm1 0 5000000>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 101 102 103 104 105 106 107 108 109 + 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 + 130 131 132 133 134 135 136 137 138 139 + 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 + 170 171 172 173 174 175 176 177 178 179 + 180 181 182 183 184 185 186 187 188 189 + 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 208 209 + 210 211 212 213 214 215 216 217 218 219 + 220 221 222 223 224 225 226 227 228 229 + 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 + 250 251 252 253 254 255>; + default-brightness-level = <255>; + enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "lvds_ppen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usbh1vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "env"; + reg = <0xc0000 0x10000>; + }; + + partition@d0000 { + label = "spare"; + reg = <0xd0000 0x320000>; + }; + + partition@3f0000 { + label = "mfg"; + reg = <0x3f0000 0x10000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-supply = <®_3p3v>; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + onkey { + compatible = "dlg,da9063-onkey"; + }; + + regulators { + vdd_bcore1: bcore1 { + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1420000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bcore2: bcore2 { + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1420000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bpro: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bmem: bmem { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bio: bio { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bperi: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo1: ldo1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1860000>; + }; + + vdd_ldo2: ldo2 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1860000>; + }; + + vdd_ldo3: ldo3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3440000>; + }; + + vdd_ldo4: ldo4 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3440000>; + }; + + vdd_ldo5: ldo5 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo6: ldo6 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo7: ldo7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo8: ldo8 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo9: ldo9 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo10: ldo10 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo11: ldo11 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc@32 { + compatible = "epson,rx8010"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x32>; + interrupt-parent = <&gpio4>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + fsl,tx-swing-full = <103>; + fsl,tx-swing-low = <103>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&sata { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + vbus-supply = <®_usb_h1_vbus>; + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; + bus-width = <8>; + vmmc-supply = <&vdd_bperi>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_display: dispgrp { + fsl,pins = < + /* BLEN_OUT */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + /* LVDS_PPEN_OUT */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SPI1 CS */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* FEC Reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + /* AR8033 Interrupt */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO 0-7 */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + /* SUS_S3_OUT to CPLD */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* PCIe Reset */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* PCIe Wake */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC Interrupt */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + /* RTC_INT */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = < + /* HUB_RESET */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + /* uSDHC2 CD */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_reset: usdhc3grp-reset { + fsl,pins = < + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + /* uSDHC4 CD */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + /* uSDHC4 SDIO PWR */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + /* uSDHC4 SDIO WP */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + /* uSDHC4 SDIO LED */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts new file mode 100644 index 000000000000..8263bfef9bf8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker + * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner + */ + +/dts-v1/; + +#include +#include +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc4; + mmc1 = &usdhc2; + serial0 = &uart2; + serial1 = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <®_lcd>; + }; + + panel { + compatible = "dataimage,fg1001l0dsswmg01"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_red: led-0 { + color = ; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: led-1 { + color = ; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + led-2 { + color = ; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_5p0: regulator-5p0 { + compatible = "regulator-fixed"; + regulator-name = "5p0"; + }; + + reg_vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_h2_vbus: regulator-usb-h2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5p0> ; + regulator-always-on; + }; + + reg_vsnvs: regulator-vsnvs { + compatible = "regulator-fixed"; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_dac: regulator-dac { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <®_5p0> ; + regulator-boot-on; + }; + + reg_sw4: regulator-sw4 { + compatible = "regulator-fixed"; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_sys: regulator-sys { + compatible = "regulator-fixed"; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; +}; + +®_arm { + vin-supply = <&sw2_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <®_vsnvs>; +}; + +®_vdd2p5 { + vin-supply = <®_vsnvs>; +}; + +®_vdd3p0 { + vin-supply = <®_vsnvs>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <®_sw4>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1c_reg: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-name = "VDD_ARM (sw2)"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + sw3b_reg: sw3b { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + sw4_reg: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + lm75: sensor@49 { + compatible = "national,lm75b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + reg = <0x49>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + eeprom_ext: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + usb3503: usb@8 { + compatible = "smsc,usb3503"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + exc3000: touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + + vcnl4035: light-sensor@60 { + compatible = "vishay,vcnl4035"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + reg = <0x60>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + vbus-supply = <®_usb_h2_vbus>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphynop1 { + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + vcc-supply = <®_usb_h1_vbus>; +}; + +&usbphynop2 { + vcc-supply = <®_usb_h2_vbus>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + timeout-sec = <10>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_reset_gpio_led: reset-gpio-led-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd_enable: lcdenablegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: usb3503-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi new file mode 100644 index 000000000000..ead83091e193 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -0,0 +1,409 @@ +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6q-ba16.dtsi" + +/ { + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "3P3V_wlan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "fsl,imx6q-ba16-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-ba16-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + mdio0: mdio-gpio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; /* 88e6240*/ + reg = <0>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + interrupt-parent = <&switch>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy1: switchphy@1 { + reg = <1>; + interrupt-parent = <&switch>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy2: switchphy@2 { + reg = <2>; + interrupt-parent = <&switch>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy3: switchphy@3 { + reg = <3>; + interrupt-parent = <&switch>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy4: switchphy@4 { + reg = <4>; + interrupt-parent = <&switch>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; +}; + +&ecspi5 { + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + m25_eeprom: flash@0 { + compatible = "atmel,at25"; + spi-max-frequency = <10000000>; + size = <0x8000>; + pagesize = <64>; + reg = <0>; + address-width = <16>; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + pca9547: mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + mux1_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ads7830: ads7830@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + mma8453: mma8453@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + }; + }; + + mux1_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; + + mpl3115: mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + }; + + mux1_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + mux1_i2c4: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&mclk>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + }; + + mux1_i2c5: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + pca9539: pca9539@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + P12-hog { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PCA9539-P12"; + }; + + P13-hog { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "PCA9539-P13"; + }; + + P14-hog { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "PCA9539-P14"; + }; + + P15-hog { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "PCA9539-P15"; + }; + + P16-hog { + gpio-hog; + gpios = <14 0>; + output-low; + line-name = "PCA9539-P16"; + }; + + P17-hog { + gpio-hog; + gpios = <15 0>; + output-low; + line-name = "PCA9539-P17"; + }; + }; + }; + + mux1_i2c6: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + mux1_i2c7: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + + mux1_i2c8: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&iomuxc { + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + >; + }; +}; + +&pmu { + secure-reg-access; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&pcie { + /* Synopsys, Inc. Device */ + pci_root: root@0,0 { + compatible = "pci16c3,abcd"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts new file mode 100644 index 000000000000..ffb3b8eeae5d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts @@ -0,0 +1,491 @@ +/* + * Copyright 2013 CompuLab Ltd. + * + * Author: Valentin Raevsky + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "imx6q.dtsi" + +/ { + model = "CompuLab CM-FX6"; + compatible = "compulab,cm-fx6", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat-led { + label = "Heartbeat"; + gpios = <&gpio2 31 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + awnh387_pwrseq: pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwrseq>; + compatible = "mmc-pwrseq-sd8787"; + powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { + compatible = "regulator-fixed"; + regulator-name = "regulator-pcie-power-on-gpio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + }; + + reg_usb_h1_vbus: usb_h1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound-analog { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board analog audio"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out", + "Microphone", "Mic Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "MICIN", "Mic Bias", + "Mic Bias", "Mic Jack"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + sound_master: simple-audio-card,cpu { + sound-dai = <&ssi2>; + system-clock-frequency = <2822400>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8731>; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + spdif-in; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_RCSEL(3 | 0x8) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(3)) + IMX_AUDMUX_V2_PDCR_RXDSEL(3) + >; + }; + + mux-audmux4 { + fsl,audmux-port = <3>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(1) | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(1)) + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&cpu0 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + wm8731: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8731"; + reg = <0x1a>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059 + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 + >; + }; + + pinctrl_pwrseq: pwrseqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_power_on_gpio>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <786432000>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + mmc-pwrseq = <&awnh387_pwrseq>; + non-removable; + /* + * If the OS probes the Bluetooth AMP function advertised on this bus + * but the firmware in place does not support it, the WiFi/BT module + * gets unresponsive. + * Users who configured their OS properly can enable this node to gain + * WiFi and/or plain Bluetooth support. + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts new file mode 100644 index 000000000000..3e59ebbb3608 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts new file mode 100644 index 000000000000..dab70d1230a2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Dual/Quad (1.5som)"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts new file mode 100644 index 000000000000..1c7b262e3709 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-cubox-i.dtsi" + +/ { + model = "SolidRun Cubox-i Dual/Quad"; + compatible = "solidrun,cubox-i/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts new file mode 100644 index 000000000000..8bfe6337cd65 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer + */ + +#ifndef __DTS_V1__ +#define __DTS_V1__ +/dts-v1/; +#endif + +#include "imx6q.dtsi" +#include "imx6qdl-dfi-fs700-m60.dtsi" + +/ { + model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; + compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts new file mode 100644 index 000000000000..d4d57370615d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2021 DH electronics GmbH + * Copyright (C) 2018 Marek Vasut + * + * DHCOM iMX6 variant: + * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 + * DHCOM PCB number: 493-300 or newer + * PDK2 PCB number: 516-400 or newer + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-pdk2.dtsi" + +/ { + model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)"; + compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", + "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts new file mode 100644 index 000000000000..16658b76fc4e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-display5.dtsi" + +&panel { + compatible = "tianma,tm070jdhg30"; +}; + +&ldb { + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi new file mode 100644 index 000000000000..4ab31f2217cd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi @@ -0,0 +1,596 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +#include +#include +#include + +/ { + model = "Liebherr (LWN) display5 i.MX6 Quad Board"; + compatible = "lwn,display5", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 101 102 103 104 105 106 107 108 109 + 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 + 130 131 132 133 134 135 136 137 138 139 + 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 + 170 171 172 173 174 175 176 177 178 179 + 180 181 182 183 184 185 186 187 188 189 + 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 208 209 + 210 211 212 213 214 215 216 217 218 219 + 220 221 222 223 224 225 226 227 228 229 + 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 + 250 251 252 253 254 255>; + default-brightness-level = <250>; + enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "lvds_ppen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lvds>; + gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <300000>; + }; + + sound { + compatible = "simple-audio-card"; + label = "tfa9879-mono"; + + simple-audio-card,dai-link { + /* DAC */ + format = "i2s"; + bitclock-master = <&dailink_master>; + frame-master = <&dailink_master>; + + dailink_master: cpu { + sound-dai = <&ssi2>; + }; + codec { + sound-dai = <&codec>; + }; + }; + }; + + panel: panel-lvds0 { + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(5) | + IMX_AUDMUX_V2_PTCR_TCSEL(5) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(5) + >; + }; + + mux-aud6 { + fsl,audmux-port = <5>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_RFSEL(8) | + IMX_AUDMUX_V2_PTCR_RCSEL(8) | + IMX_AUDMUX_V2_PTCR_TFSEL(1) | + IMX_AUDMUX_V2_PTCR_TCSEL(1) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; + status = "okay"; + + s25fl256s: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partition@0 { + label = "SPL (spi)"; + reg = <0x0 0x20000>; + read-only; + }; + partition@1 { + label = "u-boot (spi)"; + reg = <0x20000 0x100000>; + read-only; + }; + partition@2 { + label = "uboot-env (spi)"; + reg = <0x120000 0x10000>; + }; + partition@3 { + label = "uboot-envr (spi)"; + reg = <0x130000 0x10000>; + }; + partition@4 { + label = "linux-recovery (spi)"; + reg = <0x140000 0x800000>; + }; + partition@5 { + label = "swupdate-fitImg (spi)"; + reg = <0x940000 0x400000>; + }; + partition@6 { + label = "swupdate-initramfs (spi)"; + reg = <0xD40000 0x800000>; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðernet_phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { + compatible = "marvell,88E1510"; + device_type = "ethernet-phy"; + /* Set LED0 control: */ + /* On - Link, Blink - Activity, Off - No Link */ + marvell,reg-init = <3 0x10 0 0x1011>; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: tfa9879@6c { + #sound-dai-cells = <0>; + compatible = "nxp,tfa9879"; + reg = <0x6C>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* I2S OUTPUT AUD6*/ + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + >; + }; + + pinctrl_backlight: dispgrp { + fsl,pins = < + /* BLEN_OUT */ + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_ecspi2_flwp: ecspi2flwpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3_cs: ecspi3csgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 + >; + }; + + pinctrl_ecspi3_flwp: ecspi3flwpgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_lvds: reqlvdsgrp { + fsl,pins = < + /* LVDS_PPEN_OUT */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbus_grp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts new file mode 100644 index 000000000000..3815cb660ff7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Data Modul AG + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" + +/ { + model = "Data Modul eDM-QMX6 Board"; + compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; + + chosen { + stdout-path = &uart2; + }; + + aliases { + gpio7 = &stmpe_gpio1; + gpio8 = &stmpe_gpio2; + stmpe-i2c0 = &stmpe1; + stmpe-i2c1 = &stmpe2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_switch: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_switch"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 0>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_host1: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_host1_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 0>; + enable-active-high; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + label = "blue"; + gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-green { + label = "green"; + gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + led-pink { + label = "pink"; + gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + led-red { + label = "red"; + gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: flash@0 { + compatible = "m25p80", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-supply = <&vgen2_1v2_eth>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2 + &pinctrl_stmpe1 + &pinctrl_stmpe2 + &pinctrl_pfuze>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + interrupt-parent = <&gpio3>; + interrupts = <20 8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vdd_high_in: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + stmpe1: stmpe1601@40 { + compatible = "st,stmpe1601"; + reg = <0x40>; + interrupts = <30 0>; + interrupt-parent = <&gpio3>; + vcc-supply = <&sw2_reg>; + vio-supply = <&sw2_reg>; + + stmpe_gpio1: stmpe_gpio { + #gpio-cells = <2>; + compatible = "st,stmpe-gpio"; + }; + }; + + stmpe2: stmpe1601@44 { + compatible = "st,stmpe1601"; + reg = <0x44>; + interrupts = <2 0>; + interrupt-parent = <&gpio5>; + vcc-supply = <&sw2_reg>; + vio-supply = <&sw2_reg>; + + stmpe_gpio2: stmpe_gpio { + #gpio-cells = <2>; + compatible = "st,stmpe-gpio"; + }; + }; + + temp1: ad7414@4c { + compatible = "ad,ad7414"; + reg = <0x4c>; + }; + + temp2: ad7414@4d { + compatible = "ad,ad7414"; + reg = <0x4d>; + }; + + rtc: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-dmo-edmqmx6 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_ecspi5: ecspi5rp-1 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 + >; + }; + + pinctrl_pfuze: pfuze100grp1 { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 + >; + }; + + pinctrl_stmpe1: stmpe1grp { + fsl,pins = ; + }; + + pinctrl_stmpe2: stmpe2grp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host1>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + vmmc-supply = <®_3p3v>; + non-removable; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts new file mode 100644 index 000000000000..137db38f0d27 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include "imx6q-ba16.dtsi" + +/ { + model = "Advantech DMS-BA16"; + compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q"; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + }; + + sound { + compatible = "fsl,imx6q-ba16-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-ba16-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&ecspi5 { + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + m25_eeprom: flash@0 { + compatible = "atmel,at25256B", "atmel,at25"; + spi-max-frequency = <20000000>; + size = <0x8000>; + pagesize = <64>; + reg = <0>; + address-width = <16>; + }; +}; + +&iomuxc { + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + >; + }; + + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 + >; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sys_mclk>; + lrclk-strength = <0x3>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sata { + fsl,no-spread-spectrum; + fsl,transmit-atten-16ths = <12>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-level-mV = <1133>; + fsl,receive-dpll-mode = <1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ds.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ds.dts new file mode 100644 index 000000000000..b0a63a133977 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ds.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-ds.dtsi" + +/ { + model = "DaSheng i.MX6 Quad Com-9xx Board"; + compatible = "ds,imx6q-sbc", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..0f582a9d4c0e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts new file mode 100644 index 000000000000..78d941fef5df --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts @@ -0,0 +1,518 @@ +/* + * Copyright 2016 United Western Technologies. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include +#include + +/ { + model = "Uniwest Evi"; + compatible = "uniwest,imx6q-evi", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_usbh1_vbus: regulator-usbhubreset { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_hubreset>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + panel { + compatible = "sharp,lq101k1ly04"; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; + status = "okay"; + + fpga: fpga@0 { + compatible = "altr,fpga-passive-serial"; + spi-max-frequency = <20000000>; + reg = <0>; + pinctrl-0 = <&pinctrl_fpgaspi>; + nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, + <&gpio4 25 GPIO_ACTIVE_LOW>, + <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>; + status = "okay"; +}; + +&ecspi5 { + cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, + <&gpio1 13 GPIO_ACTIVE_LOW>, + <&gpio1 12 GPIO_ACTIVE_LOW>, + <&gpio2 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; + status = "okay"; + + eeprom: m95m02@1 { + compatible = "st,m95m02", "atmel,at25"; + size = <262144>; + pagesize = <256>; + address-width = <24>; + spi-max-frequency = <5000000>; + reg = <1>; + }; + + pb_rtc: rtc@3 { + compatible = "nxp,rtc-pcf2123"; + spi-max-frequency = <2450000>; + spi-cs-high; + reg = <3>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpminand>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0x0b>; + sbs,poll-retry-count = <100>; + sbs,i2c-retry-count = <100>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; +}; + +&weim { + ranges = <0 0 0x08000000 0x08000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* pwr mcu alert irq */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + /* remainder ???? */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi1cs: ecspi1csgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068 + >; + }; + + pinctrl_ecspi3cs: ecspi3csgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1 + MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1 + MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1 + >; + }; + + pinctrl_ecspi5cs: ecspi5csgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_fpgaspi: fpgaspigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_gpminand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_weimcs: weimcsgrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 + >; + }; + + pinctrl_weimfpga: weimfpgagrp { + fsl,pins = < + /* weim misc */ + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1 + MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1 + MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1 + MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1 + MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1 + MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1 + /* weim data */ + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* weim address */ + MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1 + MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0 + /* usbh1_b OC */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_usbh1_hubreset: usbh1hubresetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts new file mode 100644 index 000000000000..2fda68f9d3f6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2013 Philipp Zabel + +/dts-v1/; +#include +#include +#include "imx6q.dtsi" + +/ { + model = "Zealz GK802"; + compatible = "zealz,imx6q-gk802", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + recovery-button { + label = "recovery"; + gpios = <&gpio3 16 1>; + linux,code = ; + wakeup-source; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +/* Internal I2C */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ + eeprom: dm2016@51 { + compatible = "sdmc,dm2016"; + reg = <0x51>; + }; +}; + +/* External I2C via HDMI */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-gk802 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* Recovery button, active-low */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 + /* RTL8192CU enable GPIO, active-low */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + >; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* External USB-A port (USBOTG) */ +&usbotg { + disable-over-current; + status = "okay"; +}; + +/* Internal USB port (USBH1), connected to RTL8192CU */ +&usbh1 { + disable-over-current; + status = "okay"; +}; + +/* External microSD */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* Internal microSD */ +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts new file mode 100644 index 000000000000..f80173458e3f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw51xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; + compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts new file mode 100644 index 000000000000..6e1c493c9c8c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; + compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu2_csi1_from_ipu2_csi1_mux { + bus-width = <8>; +}; + +&ipu2_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; + bus-width = <8>; +}; + +&ipu2_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu2_csi1: ipu2_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts new file mode 100644 index 000000000000..f13df8e9c8c4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; + compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu2_csi1_from_ipu2_csi1_mux { + bus-width = <8>; +}; + +&ipu2_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; + bus-width = <8>; +}; + +&ipu2_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_csi1>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu2_csi1: ipu2_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts new file mode 100644 index 000000000000..0ba802b891b5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "Gateworks Ventana GW5400-A"; + compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; + + /* these are used by bootloader for disabling nodes */ + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + led0 = &led0; + led1 = &led1; + led2 = &led2; + ssi0 = &ssi1; + spi0 = &ecspi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "sst,w25q256", "jedec,spi-nor"; + spi-max-frequency = <30000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <&sw4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; +}; + +&ldb { + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts new file mode 100644 index 000000000000..d5d46908cf6e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw54xx.dtsi" +#include + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; + compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&hdmi_receiver>; + }; + }; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; + + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <&sw4_reg>; + DVDD-supply = <&sw4_reg>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&ipu2_csi1_from_ipu2_csi1_mux { + bus-width = <8>; +}; + +&ipu2_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; + bus-width = <8>; +}; + +&ipu2_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_csi1>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ipu2_csi1: ipu2_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts new file mode 100644 index 000000000000..2c7feeef1b0e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw551x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; + compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts new file mode 100644 index 000000000000..c973b7304225 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; + compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts new file mode 100644 index 000000000000..e9c224cea752 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; + compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts new file mode 100644 index 000000000000..735f2bbf1439 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw560x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW560X"; + compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts new file mode 100644 index 000000000000..a182e4cb0e6e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw5903.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5903"; + compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts new file mode 100644 index 000000000000..ca1e2ae3341e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw5904.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5904"; + compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts new file mode 100644 index 000000000000..b25526ef5886 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw5907.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; + compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts new file mode 100644 index 000000000000..6aafa2fcee08 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw5910.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; + compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts new file mode 100644 index 000000000000..4dcbd943cd93 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw5912.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; + compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts new file mode 100644 index 000000000000..6f511f1665fd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw5913.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; + compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts new file mode 100644 index 000000000000..3fe4591e21f5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts @@ -0,0 +1,382 @@ +/* + * Copyright (C) 2015 Lucas Stach + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" + +/ { + model = "Auvidea H100"; + compatible = "auvidea,h100", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + hdmi_osc: hdmi-osc { + compatible = "fixed-clock"; + clock-output-names = "hdmi-osc"; + clock-frequency = <27000000>; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_leds>; + + led0: led-power { + label = "power"; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led1: led-stream { + label = "stream"; + gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2: led-rec { + label = "rec"; + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_hdmi: regulator-hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_reg_hdmi>; + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + regulator-name = "V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_usbh1_vbus>; + regulator-name = "USB_H1_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_usbotg_vbus>; + regulator-name = "USB_OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound-sgtl5000 { + compatible = "fsl,imx-audio-sgtl5000"; + model = "H100 on-board codec"; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-ext-port = <5>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_i2c1>; + status = "okay"; + + eeprom: eeprom@51 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x51>; + }; + + rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sgtl5000: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_sgtl5000>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; + + tc358743: tc358743@f { + compatible = "toshiba,tc358743"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_tc358743>; + clocks = <&hdmi_osc>; + clock-names = "refclk"; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + /* IRQ has a wrong pull resistor which renders it useless */ + + port { + tc358743_out: endpoint { + remote-endpoint = <&mipi_csi2_in>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <297000000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_i2c2>; + status = "okay"; +}; + +&iomuxc { + h100 { + pinctrl_h100_hdmi: h100-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_h100_i2c1: h100-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_h100_i2c2: h100-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_h100_leds: pinctrl-h100-leds { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + >; + }; + + pinctrl_h100_reg_hdmi: h100-reg-hdmi { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + >; + }; + + pinctrl_h100_sgtl5000: h100-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_h100_tc358743: h100-tc358743 { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + >; + }; + + pinctrl_h100_uart2: h100-uart2 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_h100_usbotg_id: hummingboard-usbotg-id { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_h100_usdhc2: h100-usdhc2 { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 + >; + }; + + pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 + >; + }; + + pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 + >; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + port { + mipi_csi2_in: endpoint { + remote-endpoint = <&tc358743_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <297000000>; + }; + }; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_uart2>; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_usbotg_id>; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_h100_usdhc2>; + pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts new file mode 100644 index 000000000000..c51b4e4fd71e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts new file mode 100644 index 000000000000..e4132d62ffa2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad (1.5som)"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts new file mode 100644 index 000000000000..8c9e94e648a7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts new file mode 100644 index 000000000000..1998ebfa0fe0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts @@ -0,0 +1,63 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts new file mode 100644 index 000000000000..d3ad7329cd6d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts @@ -0,0 +1,62 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad (1.5som)"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts new file mode 100644 index 000000000000..5249f53dcdbc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-brcm.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-hummingboard2-emmc.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts new file mode 100644 index 000000000000..d51745268dbf --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2017 Engicam S.r.l. + * Copyright (C) 2017 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore-1.5.dtsi" + +/ { + model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&mipi_csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts new file mode 100644 index 000000000000..02aca1e28ce3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts new file mode 100644 index 000000000000..241811c52b62 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 12 Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; + + panel { + compatible = "koe,tx31d200vm0baa"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + reg = <0>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts new file mode 100644 index 000000000000..cf6ba724f497 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * Copyright (C) 2015 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore-rqs.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; + compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore.dts new file mode 100644 index 000000000000..fe28c3cf54c0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c1 { + max11801: touchscreen@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <60000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <30>; + hfront-porch = <30>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <64>; + vsync-len = <20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi new file mode 100644 index 000000000000..4d6a0c3e8455 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2019 (C) Pengutronix, Marco Felsch + */ + +#include "imx6q.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include + +/ { + model = "Kontron SMARC sAMX6i Quad/Dual"; + compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; +}; + +/* Quad/Dual SoMs have 3 chip-select signals */ +&ecspi4 { + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 29 GPIO_ACTIVE_LOW>, + <&gpio3 25 GPIO_ACTIVE_LOW>; +}; + +&pinctrl_ecspi4 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + + /* SPI4_IMX_CS2# - connected to internal flash */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 + /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 + >; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts new file mode 100644 index 000000000000..50fbf46d17c2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; + +#include "imx6q-kp.dtsi" + +/ { + model = "Freescale i.MX6 Qwuad K+P TPC Board"; + compatible = "kiebackpeter,imx6q-tpc", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi new file mode 100644 index 000000000000..091903f53a56 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +#include +#include +#include + +/ { + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <250>; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 500000>; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcd_panel: lcd-panel { + compatible = "auo,g070vvn01"; + backlight = <&backlight_lcd>; + power-supply = <®_display>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-green { + label = "led1"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-red { + label = "led0"; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "sgtl5000-supply"; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_display: regulator-display { + compatible = "regulator-fixed"; + regulator-name = "display-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb_h1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6q-sgtl5000-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCSEL(2) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; + + ds1307: rtc@32 { + compatible = "dallas,ds1307"; + reg = <0x32>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + /* sgtl5000 sys_mclk clock routed to CLKO1 */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_flexcan1: can1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts new file mode 100644 index 000000000000..46a4ddedb423 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6-logicpd-som.dtsi" +#include "imx6-logicpd-baseboard.dtsi" + +/ { + model = "Logic PD i.MX6QD SOM-M3"; + compatible = "logicpd,imx6q-logicpd", "fsl,imx6q"; + + backlight: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 20000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_lcd>; + }; + + panel-lvds0 { + compatible = "okaya,rs800480t-7x0gp"; + power-supply = <®_lcd_reset>; + backlight = <&backlight>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_lcd: regulator-lcd { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reg>; + compatible = "regulator-fixed"; + regulator-name = "lcd_panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + startup-delay-us = <500000>; + }; + + reg_lcd_reset: regulator-lcd-reset { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reset>; + compatible = "regulator-fixed"; + regulator-name = "nLCD_RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_lcd>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + touchscreen@26 { + compatible = "ilitek,ili2117"; + reg = <0x26>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + +}; + +&pwm3 { + status = "okay"; +}; + +®_hdmi { + regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ +}; + +&iomuxc { + pinctrl_lcd_reg: lcdreg { + fsl,pins = < + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ + >; + }; + + pinctrl_lcd_reset: lcdreset { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts new file mode 100644 index 000000000000..2c9961333b0a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts @@ -0,0 +1,417 @@ +/* + * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include + +/ { + model = "Embest MarS Board i.MX6Dual"; + compatible = "embest,imx6q-marsboard", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-user1 { + label = "imx6:green:user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led-user2 { + label = "imx6:green:user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + /* RGMII_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi new file mode 100644 index 000000000000..0d7be4567291 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5_mba6x>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +}; + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <120>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <180>; + txd0-skew-ps = <360>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts new file mode 100644 index 000000000000..349a08605a5e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-a", "tq,mba6a", + "tq,imx6q-tqma6q-a", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts new file mode 100644 index 000000000000..02c9f3e91b8f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-b", "tq,mba6b", + "tq,imx6q-tqma6q-b", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts new file mode 100644 index 000000000000..f08b37010291 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +#include +#include + +/ { + model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; + compatible = "lwn,mccmon6", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 101 102 103 104 105 106 107 108 109 + 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 + 130 131 132 133 134 135 136 137 138 139 + 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 + 170 171 172 173 174 175 176 177 178 179 + 180 181 182 183 184 185 186 187 188 189 + 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 208 209 + 210 211 212 213 214 215 216 217 218 219 + 220 221 222 223 224 225 226 227 228 229 + 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 + 250 251 252 253 254 255>; + default-brightness-level = <50>; + enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "lvds_ppen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lvds>; + gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel-lvds0 { + compatible = "innolux,g121x1-l03"; + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; + status = "okay"; + + s25sl032p: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; + ranges = <0 0 0x08000000 0x08000000>; + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + use-advanced-sector-protection; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_backlight: dispgrp { + fsl,pins = < + /* BLEN_OUT */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3_cs: ecspi3csgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 + >; + }; + + pinctrl_ecspi3_flwp: ecspi3flwpgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_lvds: reqlvdsgrp { + fsl,pins = < + /* LVDS_PPEN_OUT */ + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor: weimnorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts new file mode 100644 index 000000000000..03bec0c53063 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2015 Boundary Devices, Inc. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6_MAX Board"; + compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts new file mode 100644 index 000000000000..eb4eecb6ed22 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016 Boundary Devices, Inc. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board"; + compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts new file mode 100644 index 000000000000..435445a34ad0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6x Board"; + compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts new file mode 100644 index 000000000000..a7d5a68110fc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -0,0 +1,803 @@ +/* + * Copyright 2015 Sutajio Ko-Usagi PTE LTD + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include +#include + +/ { + model = "Kosagi Novena Dual/Quad"; + compatible = "kosagi,imx6q-novena", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 10000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_novena>; + power-supply = <®_lvds_lcd>; + brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; + default-brightness-level = <12>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys_novena>; + + user-button { + label = "User Button"; + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + lid-event { + label = "Lid"; + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_novena>; + + led-heartbeat { + label = "novena:white:panel"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + panel: panel { + compatible = "innolux,n133hse-ea1"; + backlight = <&backlight>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_audio_codec: regulator-audio-codec { + compatible = "regulator-fixed"; + regulator-name = "es8328-power"; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <400000>; + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_display: regulator-display { + compatible = "regulator-fixed"; + regulator-name = "lcd-display-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_lcd: regulator-lvds-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd-lvds-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pcie-bus-power"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sata: regulator-sata { + compatible = "regulator-fixed"; + regulator-name = "sata-power"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <10000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-es8328"; + model = "imx-audio-es8328"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-amp-supply = <®_audio_codec>; + jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>; + audio-routing = + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Speaker", "audio-amp", + "Headphone", "ROUT1", + "Headphone", "LOUT1", + "LINPUT1", "Mic Jack", + "RINPUT1", "Mic Jack", + "Mic Jack", "Mic Bias"; + mux-int-port = <0x1>; + mux-ext-port = <0x3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_novena>; + status = "okay"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3_novena>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_novena>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; + txen-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <3000>; + txd1-skew-ps = <3000>; + txd2-skew-ps = <3000>; + txd3-skew-ps = <3000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_novena>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_novena>; + status = "okay"; + + accel: mma8452@1c { + compatible = "fsl,mma8452"; + reg = <0x1c>; + }; + + rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sbs_battery: bq20z75@b { + compatible = "sbs,sbs-battery"; + reg = <0x0b>; + sbs,i2c-retry-count = <50>; + }; + + touch: stmpe811@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe_novena>; + vio-supply = <®_3p3v>; + vcc-supply = <®_3p3v>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_novena>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw1c: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_sw3a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_sw3b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_sw4: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + }; + + reg_snvs: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vref: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + reg_vgen2: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + reg_vgen3: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vgen4: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_novena>; + status = "okay"; + + codec: es8328@11 { + compatible = "everest,es8328"; + reg = <0x11>; + DVDD-supply = <®_audio_codec>; + AVDD-supply = <®_audio_codec>; + PVDD-supply = <®_audio_codec>; + HPVDD-supply = <®_audio_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sound_novena>; + clocks = <&clks IMX6QDL_CLK_CKO1>; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO1_SEL>, + <&clks IMX6QDL_CLK_PLL4_AUDIO>, + <&clks IMX6QDL_CLK_CKO1>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, + <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_CKO1_PODF>; + assigned-clock-rates = <0 0 722534400 22579200>; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp_novena>; + linux,keymap = < + MATRIX_KEY(1, 1, KEY_CONFIG) + >; + status = "okay"; +}; + +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + fsl,panel = <&panel>; + status = "okay"; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_novena>; + reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + status = "okay"; +}; + +&sata { + target-supply = <®_sata>; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <8>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_novena>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_novena>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_novena>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_novena>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_swbst>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_novena>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_novena>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux_novena: audmuxgrp-novena { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight_novena: backlightgrp-novena { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 + >; + }; + + pinctrl_ecspi3_novena: ecspi3grp-novena { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_enet_novena: enetgrp-novena { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + /* Ethernet reset */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 + >; + }; + + pinctrl_fpga_gpio: fpgagpiogrp-novena { + fsl,pins = < + /* FPGA power */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 + /* Reset */ + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 + /* FPGA GPIOs */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 + >; + }; + + pinctrl_fpga_eim: fpgaeimgrp-novena { + fsl,pins = < + /* FPGA power */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 + /* Reset */ + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 + /* FPGA GPIOs */ + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1 + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1 + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1 + MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1 + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1 + MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1 + >; + }; + + pinctrl_gpio_keys_novena: gpiokeysgrp-novena { + fsl,pins = < + /* User button */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + /* PCIe Wakeup */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0 + /* Lid switch */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + >; + }; + + pinctrl_hdmi_novena: hdmigrp-novena { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 + >; + }; + + pinctrl_i2c1_novena: i2c1grp-novena { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_novena: i2c2grp-novena { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_novena: i2c3grp-novena { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_kpp_novena: kppgrp-novena { + fsl,pins = < + /* Front panel button */ + MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 + /* Fake column driver, not connected */ + MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1 + >; + }; + + pinctrl_leds_novena: ledsgrp-novena { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 + >; + }; + + pinctrl_pcie_novena: pciegrp-novena { + fsl,pins = < + /* Reset */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 + /* Power On */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + /* Wifi kill */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 + >; + }; + + pinctrl_sata_novena: satagrp-novena { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 + >; + }; + + pinctrl_senoko_novena: senokogrp-novena { + fsl,pins = < + /* Senoko IRQ line */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 + /* Senoko reset line */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 + >; + }; + + pinctrl_sound_novena: soundgrp-novena { + fsl,pins = < + /* Audio power regulator */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 + /* Headphone plug */ + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_stmpe_novena: stmpegrp-novena { + fsl,pins = < + /* Touchscreen interrupt */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 + >; + }; + + pinctrl_uart2_novena: uart2grp-novena { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3_novena: uart3grp-novena { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4_novena: uart4grp-novena { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg_novena: usbotggrp-novena { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2_novena: usdhc2grp-novena { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + /* Write protect */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 + /* Card detect */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 + >; + }; + + pinctrl_usdhc3_novena: usdhc3grp-novena { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts new file mode 100644 index 000000000000..322f071d972f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; + compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6q"; + + chosen { + stdout-path = &uart2; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&m25p80 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts new file mode 100644 index 000000000000..3f13726c8058 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; + compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6q"; + + chosen { + stdout-path = &uart2; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&m25p80 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts new file mode 100644 index 000000000000..affe30b02d5a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +/dts-v1/; +#include "imx6q-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; + compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi new file mode 100644 index 000000000000..500944bd2a05 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +#include "imx6q.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 Quad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts new file mode 100644 index 000000000000..479a63ed42af --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; + compatible = "technexion,imx6q-pico-dwarf", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts new file mode 100644 index 000000000000..b767131068f5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-hobbit.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; + compatible = "technexion,imx6q-pico-hobbit", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts new file mode 100644 index 000000000000..e8ad4c12b263 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; + compatible = "technexion,imx6q-pico-nymph", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts new file mode 100644 index 000000000000..cc2394ddad6c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; + compatible = "technexion,imx6q-pico-pi", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h new file mode 100644 index 000000000000..e40409d04b97 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h @@ -0,0 +1,1044 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX6Q_PINFUNC_H +#define __DTS_IMX6Q_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 +#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 +#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 +#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 +#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 +#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 +#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 +#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 +#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 +#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 +#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 +#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 +#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 +#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 +#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 +#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 +#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 +#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 +#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 +#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 +#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 +#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 +#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 +#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 +#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 +#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 +#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 +#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 +#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 +#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 +#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 +#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 +#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 +#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 +#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 +#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 +#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 +#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 +#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 +#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 +#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 +#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 +#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 +#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 +#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 +#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 +#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 +#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 +#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 +#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 +#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 +#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 +#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 +#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 +#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 +#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 +#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 +#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 +#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 +#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 +#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 +#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 +#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 +#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 +#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 +#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 +#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 +#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 +#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 +#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 +#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 +#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 +#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 +#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 +#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 +#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 +#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 +#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 +#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 +#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 +#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 +#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 +#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 +#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 +#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 +#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 +#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 +#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 +#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 +#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 +#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 +#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 +#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 +#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 +#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 +#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 +#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 +#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 +#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 +#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 +#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 +#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 +#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 +#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 +#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 +#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 +#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 +#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 +#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 +#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 +#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 +#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 +#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 +#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 +#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 +#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 +#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 +#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 +#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 +#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 +#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 +#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 +#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 +#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 +#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 +#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 +#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 +#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 +#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 +#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 +#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 +#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 +#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 +#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 +#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 +#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 +#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 +#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 +#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 +#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 +#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 +#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 +#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 +#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 +#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 +#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 +#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 +#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 +#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 +#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 +#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 +#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 +#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 +#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 +#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 +#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 +#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 +#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 +#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 +#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 +#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 +#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 +#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 +#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 +#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 +#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 +#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 +#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 +#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 +#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 +#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 +#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 +#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 +#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 +#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 +#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 +#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 +#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 +#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 +#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 + +#endif /* __DTS_IMX6Q_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts new file mode 100644 index 000000000000..109b46a22b5e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts @@ -0,0 +1,695 @@ +/* + * Copyright (C) 2017 NutsBoard.Org + * + * Author: Wig Cheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include +#include "imx6q.dtsi" + +/ { + model = "NutsBoard i.MX6 Quad Pistachio board"; + compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + wlan_en_reg: regulator-wlan_en { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-power { + label = "Power Button"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "audio-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + brightness-levels = < + 0 /*1 2 3 4 5 6*/ 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <94>; + status = "okay"; + }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ar1021@4d { + compatible = "microchip,ar1021-i2c"; + reg = <0x4d>; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/ + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + /* AR8035 reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00 + >; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <0x5>; +}; + +&usbphy2 { + fsl,tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + keep-power-in-suspend; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + vmmc-supply = <&wlan_en_reg>; + no-1-8-v; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts new file mode 100644 index 000000000000..d8fa83effd63 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include +#include + +/ { + model = "Protonic PRTI6Q board"; + compatible = "prt,prti6q", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <1>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + can_osc: can-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + enable-active-high; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "regulator-WL12xx"; + startup-delay-us = <70000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3>; + clocks = <&can_osc>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <5000000>; + }; + + adc@1 { + compatible = "ti,adc128s052"; + reg = <1>; + spi-max-frequency = <2000000>; + vref-supply = <®_3v3>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* can2_l */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can2_h */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + vmmc-supply = <®_wifi>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + wifi { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <19200000>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008 + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + /* ADC128S022 CS */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + /* DDC */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg_id: usbotgidgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* WL12xx IRQ */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts new file mode 100644 index 000000000000..792b8903d345 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2018 Protonic Holland + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include + +/ { + model = "Protonic WD2 board"; + compatible = "prt,prtwd2", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ + i2c { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <20>; /* ~10 kHz */ + i2c-gpio,scl-output-only; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; + status = "okay"; +}; + +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + status = "okay"; + + fixed-link { + speed = <100>; + pause; + full-duplex; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* V in */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* I charge */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* V bus */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* nc */ + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth_chg>; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0 + MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0 + >; + }; + + pinctrl_usb_eth_chg: usbethchggrp { + fsl,pins = < + /* USB charging control */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts new file mode 100644 index 000000000000..271f4b2d9b9f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 FEDEVEL, Inc. + * + * Author: Robert Nelson + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-rex.dtsi" + +/ { + model = "Rex Pro i.MX6 Quad Board"; + compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&ecspi3 { + flash: flash@0 { + compatible = "sst,sst25vf032b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts new file mode 100644 index 000000000000..6e981a3e0a83 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sabreauto.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Automotive Board"; + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts new file mode 100644 index 000000000000..7c6a2f234ccb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-sabrelite.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Lite Board"; + compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts new file mode 100644 index 000000000000..eec944673c0b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sabresd.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Smart Device Board"; + compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts new file mode 100644 index 000000000000..717ac62fc2cf --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-savageboard.dtsi" + +/ { + model = "Poslab SavageBoard Quad"; + compatible = "poslab,imx6q-savageboard", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts new file mode 100644 index 000000000000..9054c1d58b9d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Pavel Machek + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "MicroSys sbc6x board"; + compatible = "microsys,sbc6x", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&iomuxc { + imx6q-sbc6x { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts new file mode 100644 index 000000000000..ff97d22eb09f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-skov-cpu.dtsi" +#include "imx6qdl-skov-cpu-revc.dtsi" +#include "imx6qdl-skov-revc-lt2.dtsi" + +/ { + model = "SKOV IMX6 CPU QuadCore"; + compatible = "skov,imx6q-skov-revc-lt2", "fsl,imx6q"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + /* internal 22 k pull up required */ + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001f878 + /* internal 22 k pull up required */ + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001f878 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts new file mode 100644 index 000000000000..3e3b36ad362a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-skov-cpu.dtsi" +#include "imx6qdl-skov-cpu-revc.dtsi" + +/ { + model = "SKOV IMX6 CPU QuadCore"; + compatible = "skov,imx6q-skov-revc-lt6", "fsl,imx6q"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; + pwms = <&pwm2 0 20000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <17>; + default-brightness-level = <8>; + power-supply = <®_24v0>; + }; + + display { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l6wh-rt"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + /* internal 22 k pull up required */ + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 + /* internal 22 k pull up required */ + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts new file mode 100644 index 000000000000..a3f247c722b4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-skov-cpu.dtsi" + +/ { + model = "SKOV IMX6 CPU QuadCore"; + compatible = "skov,imx6q-skov-reve-mi1010ait-1cp1", "fsl,imx6q"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; + pwms = <&pwm2 0 20000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <17>; + default-brightness-level = <8>; + power-supply = <®_24v0>; + }; + + panel { + compatible = "multi-inno,mi1010ait-1cp"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + wakeup-source; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + /* external 1 k pull up */ + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x40010878 + /* external 1 k pull up */ + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x40010878 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + /* internal 22 k pull up required */ + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 + /* internal 22 k pull up required */ + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + /* external 10 k pull up */ + /* CTP_INT */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + /* CTP_RST */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + >; + }; +}; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts b/arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts new file mode 100644 index 000000000000..0e6a325df363 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * Based on dt work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sr-som.dtsi" +#include "imx6qdl-sr-som-emmc.dtsi" +#include "imx6qdl-sr-som-ti.dtsi" +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6qdl-solidsense.dtsi" + +/ { + model = "SolidRun SolidSense Dual/Quad (1.5som+emmc)"; + compatible = "solidrun,solidsense/q", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts new file mode 100644 index 000000000000..2f576e2ce73f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2014 Soeren Moch + +/dts-v1/; + +#include "imx6q.dtsi" +#include +#include + +/ { + model = "TBS2910 Matrix ARM mini PC"; + compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + mmc2 = &usdhc4; + /delete-property/ mmc3; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_fan>; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 3000 1>; + }; + + ir_recv { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-blue { + label = "blue_status_led"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "On-board SPDIF"; + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: sgtl5000@a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <16>; + fsl,receive-eq-mdB = <3000>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_5p0v>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + voltage-ranges = <3300 3300>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 + >; + }; + + pinctrl_gpio_fan: gpiofangrp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ir: irgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi new file mode 100644 index 000000000000..ab4c07c13a13 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi new file mode 100644 index 000000000000..7224c376c318 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts new file mode 100644 index 000000000000..dce1e8671ebe --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts4900.dtsi" + +/ { + model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; + compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts new file mode 100644 index 000000000000..570bd3c309a6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Technologic Systems + * Copyright 2017 Savoir-faire Linux + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7970.dtsi" + +/ { + model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; + compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts new file mode 100644 index 000000000000..ac3050a835e5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts @@ -0,0 +1,79 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&kpp { + status = "disabled"; +}; + +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + +®_can_xcvr { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts new file mode 100644 index 000000000000..4ee860b626ff --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010/-1030 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + +&ipu2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts new file mode 100644 index 000000000000..a773f252816c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts @@ -0,0 +1,110 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&kpp { + status = "disabled"; +}; + +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + +®_can_xcvr { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts new file mode 100644 index 000000000000..0a4daec8d3ad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1020 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts new file mode 100644 index 000000000000..9ffbb0fe7df8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1036.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts new file mode 100644 index 000000000000..cb2fcb4896c6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1036 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts new file mode 100644 index 000000000000..d43a5d8f1749 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1010.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts new file mode 100644 index 000000000000..f7b0acb65352 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts @@ -0,0 +1,58 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1110/-1130 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts new file mode 100644 index 000000000000..387edf2b3f96 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2016-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1110.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts b/arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts new file mode 100644 index 000000000000..52e9f4a211d0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Udoo i.MX6 Quad Board"; + compatible = "udoo,imx6q-udoo", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts new file mode 100644 index 000000000000..ad59b23ef27a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts @@ -0,0 +1,355 @@ +/* + * Copyright 2013 CompuLab Ltd. + * Copyright 2016 Christopher Spinrath + * + * Based on the devicetree distributed with the vendor kernel for the + * Utilite Pro: + * Copyright 2013 CompuLab Ltd. + * Author: Valentin Raevsky + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "imx6q-cm-fx6.dts" + +/ { + model = "CompuLab Utilite Pro"; + compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q"; + + aliases { + ethernet1 = ð1; + rtc0 = &em3027; + rtc1 = &snvs_rtc; + }; + + encoder { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <¶llel_display_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-power { + label = "Power Button"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hpd>; + type = "a"; + ddc-i2c-bus = <&i2c_dvi_ddc>; + hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1mux>; + #address-cells = <1>; + #size-cells = <0>; + + mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c1>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + em3027: rtc@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; + }; + + i2c_dvi_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + parallel-display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + + interface-pix-fmt = "rgb24"; + + port@0 { + reg = <0>; + + parallel_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + parallel_display_out: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; + }; +}; + +/* + * A single IPU is not able to drive both display interfaces available on the + * Utilite Pro at high resolution due to its bandwidth limitation. Since the + * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the + * SoC-internal Designware HDMI encoder forcing the latter to be connected to + * IPU2 instead of IPU1. + */ +/delete-node/&ipu1_di0_hdmi; +/delete-node/&hdmi_mux_0; +/delete-node/&ipu1_di1_hdmi; +/delete-node/&hdmi_mux_1; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hpd: hpdgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1mux: i2c1muxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <¶llel_display_in>; +}; + +&pcie { + pcie@0,0 { + reg = <0x000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + /* non-removable i211 ethernet card */ + eth1: intel,i211@pcie0,0 { + reg = <0x010000 0 0 0 0>; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + no-1-8-v; + broken-cd; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts new file mode 100644 index 000000000000..2290c1237634 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Support for Variscite DART-MX6 Carrier-board + * + * Copyright 2017 BayLibre, SAS + * Author: Neil Armstrong + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-var-dart.dtsi" +#include + +/ { + model = "Variscite DART-MX6 Carrier-board"; + compatible = "variscite,dt6customboard", "fsl,imx6q"; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 4 8 16 32 64 128 248>; + default-brightness-level = <7>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-back { + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "Key Back"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + key-home { + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "Key Home"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + key-menu { + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "Key Menu"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + panel1: lvds-panel { + compatible = "sgd,gktw70sdae4se", "panel-lvds"; + backlight = <&backlight_lvds>; + width-mm = <153>; + height-mm = <86>; + label = "gktw70sdae4se"; + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <32000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <39>; + hfront-porch = <39>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <47>; + vsync-len = <2>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_usb_h1_vbus: regulator-usbh1vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "dt6-customboard-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&clks IMX6QDL_CLK_CKO>; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 10 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + status = "okay"; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible = "isil,isl12057"; + reg = <0x68>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm2 { + #pwm-cells = <2>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc2 { + cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts new file mode 100644 index 000000000000..dd91aff3f9e2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" + +/ { + model = "Kverneland UT1Q Board"; + compatible = "kvg,vicut1q", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts new file mode 100644 index 000000000000..f6ccbecff92c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revb1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board rev B1"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts new file mode 100644 index 000000000000..55331021d80c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board revD1"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts new file mode 100644 index 000000000000..0be548beef86 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revc1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts new file mode 100644 index 000000000000..bddf3822ebf7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux i.MX6Quad board"; + compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_pu { + regulator-always-on; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts new file mode 100644 index 000000000000..ec6651ba4ba2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Pegasus i.MX6Quad board"; + compatible = "ysoft,imx6q-yapp4-pegasus", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_pu { + regulator-always-on; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts new file mode 100644 index 000000000000..a1c5e69d81ba --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2016-2017 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-zii-rdu2.dtsi" + +/ { + model = "ZII RDU2 Board"; + compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q.dtsi new file mode 100644 index 000000000000..df86049a695b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q.dtsi @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. + +#include +#include "imx6q-pinfunc.h" +#include "imx6qdl.dtsi" + +/ { + aliases { + ipu1 = &ipu2; + spi4 = &ecspi5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + }; + + soc: soc { + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x40000>; + ranges = <0 0x00900000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + aips1: bus@2000000 { /* AIPS1 */ + spba-bus@2000000 { + ecspi5: spi@2018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02018000 0x4000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6Q_CLK_ECSPI5>, + <&clks IMX6Q_CLK_ECSPI5>; + clock-names = "ipg", "per"; + dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + }; + + sata: sata@2200000 { + compatible = "fsl,imx6q-ahci"; + reg = <0x02200000 0x4000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_SATA>, + <&clks IMX6QDL_CLK_SATA_REF_100M>, + <&clks IMX6QDL_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + + gpu_vg: gpu@2204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + #cooling-cells = <2>; + }; + + ipu2: ipu@2800000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ipu"; + reg = <0x02800000 0x400000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, + <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "bus", "di0", "di1"; + resets = <&src 4>; + + ipu2_csi0: port@0 { + reg = <0>; + + ipu2_csi0_from_mipi_vc2: endpoint { + remote-endpoint = <&mipi_vc2_to_ipu2_csi0>; + }; + }; + + ipu2_csi1: port@1 { + reg = <1>; + + ipu2_csi1_from_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>; + }; + }; + + ipu2_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu2_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu2_di0_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_mux_2>; + }; + + ipu2_di0_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_mux_2>; + }; + + ipu2_di0_lvds0: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds0_mux_2>; + }; + + ipu2_di0_lvds1: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds1_mux_2>; + }; + }; + + ipu2_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu2_di1_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_mux_3>; + }; + + ipu2_di1_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_mux_3>; + }; + + ipu2_di1_lvds0: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds0_mux_3>; + }; + + ipu2_di1_lvds1: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds1_mux_3>; + }; + }; + }; + }; + + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; + }; +}; + +&gpio1 { + gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, + <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, + <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, + <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, + <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, + <&iomuxc 22 116 10>; +}; + +&gpio2 { + gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, + <&iomuxc 31 44 1>; +}; + +&gpio3 { + gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; +}; + +&gpio4 { + gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; +}; + +&gpio5 { + gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, + <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; +}; + +&gpio6 { + gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, + <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, + <&iomuxc 31 86 1>; +}; + +&gpio7 { + gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; +}; + +&gpr { + ipu1_csi0_mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu1_csi0_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_csi0_mux_from_parallel_sensor: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ipu1_csi0_mux_to_ipu1_csi0: endpoint { + remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; + }; + }; + }; + + ipu2_csi1_mux { + compatible = "video-mux"; + mux-controls = <&mux 1>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu2_csi1_mux_from_mipi_vc3: endpoint { + remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu2_csi1_mux_from_parallel_sensor: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ipu2_csi1_mux_to_ipu2_csi1: endpoint { + remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>; + }; + }; + }; +}; + +&hdmi { + compatible = "fsl,imx6q-hdmi"; + + ports { + port@2 { + reg = <2>; + + hdmi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_hdmi>; + }; + }; + + port@3 { + reg = <3>; + + hdmi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_hdmi>; + }; + }; + }; +}; + +&iomuxc { + compatible = "fsl,imx6q-iomuxc"; +}; + +&ipu1_csi1 { + ipu1_csi1_from_mipi_vc1: endpoint { + remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; + }; +}; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", "di2_sel", "di3_sel", + "di0", "di1"; + + lvds-channel@0 { + port@2 { + reg = <2>; + + lvds0_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_lvds0>; + }; + }; + + port@3 { + reg = <3>; + + lvds0_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + port@2 { + reg = <2>; + + lvds1_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_lvds1>; + }; + }; + + port@3 { + reg = <3>; + + lvds1_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_lvds1>; + }; + }; + }; +}; + +&mipi_csi { + port@1 { + reg = <1>; + + mipi_vc0_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + }; + + port@2 { + reg = <2>; + + mipi_vc1_to_ipu1_csi1: endpoint { + remote-endpoint = <&ipu1_csi1_from_mipi_vc1>; + }; + }; + + port@3 { + reg = <3>; + + mipi_vc2_to_ipu2_csi0: endpoint { + remote-endpoint = <&ipu2_csi0_from_mipi_vc2>; + }; + }; + + port@4 { + reg = <4>; + + mipi_vc3_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>; + }; + }; +}; + +&mipi_dsi { + ports { + port@2 { + reg = <2>; + + mipi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_mipi>; + }; + }; + + port@3 { + reg = <3>; + + mipi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_mipi>; + }; + }; + }; +}; + +&mux { + mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */ + <0x04 0x00100000>, /* MIPI_IPU2_MUX */ + <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ + <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ + <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ + <0x28 0x00000003>, /* DCIC1_MUX_CTL */ + <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ +}; + +&vpu { + compatible = "fsl,imx6q-vpu", "cnm,coda960"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi new file mode 100644 index 000000000000..4cc965277c52 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi @@ -0,0 +1,1371 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +#include +#include + +/ { + model = "Toradex Apalis iMX6Q/D Module"; + compatible = "toradex,apalis_imx6q", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + power-supply = <®_module_3v3>; + pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + clk_ov5640_osc: clk-ov5640-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-wakeup { + debounce-interval = <10>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + status = "disabled"; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_AUDIO"; + }; + + reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "DOVDD/DVDD_1.8V"; + /* Note: The CSI module uses on-board 3.3V_SW supply */ + vin-supply = <®_module_3v3>; + }; + + reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "AVDD/AFVDD_2.8V"; + /* Note: The CSI module uses on-board 3.3V_SW supply */ + vin-supply = <®_module_3v3>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; + status = "disabled"; + }; + + /* on module USB hub */ + reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus_hub"; + startup-delay-us = <2000>; + status = "okay"; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; + vin-supply = <®_usb_host_vbus_hub>; + status = "disabled"; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + model = "imx6q-apalis-sgtl5000"; + mux-ext-port = <4>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; + + sound_spdif: sound-spdif { + compatible = "fsl,imx-audio-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + model = "imx-spdif"; + status = "disabled"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1_default>; + pinctrl-1 = <&pinctrl_flexcan1_sleep>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2_default>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + status = "disabled"; +}; + +&clks { + fsl,pmic-stby-poweroff; +}; + +/* Apalis SPI1 */ +&ecspi1 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; +}; + +/* Apalis SPI2 */ +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "disabled"; +}; + +&gpio1 { + gpio-line-names = "MXM3_84", + "MXM3_4", + "MXM3_15/GPIO7", + "MXM3_96", + "MXM3_37", + "", + "MXM3_17/GPIO8", + "MXM3_14", + "MXM3_12", + "MXM3_2", + "MXM3_184", + "MXM3_180", + "MXM3_178", + "MXM3_176", + "MXM3_188", + "MXM3_186", + "MXM3_160", + "MXM3_162", + "MXM3_150", + "MXM3_144", + "MXM3_154", + "MXM3_146", + "", + "", + "MXM3_72"; +}; + +&gpio2 { + gpio-line-names = "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "MXM3_95", + "MXM3_6", + "MXM3_8", + "MXM3_123", + "MXM3_126", + "MXM3_128", + "MXM3_130", + "MXM3_132", + "MXM3_253", + "MXM3_251", + "MXM3_283", + "MXM3_281", + "MXM3_279", + "MXM3_277", + "MXM3_243", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_198", + "MXM3_275", + "MXM3_273", + "MXM3_207", + "MXM3_122"; +}; + +&gpio3 { + gpio-line-names = "MXM3_271", + "MXM3_269", + "MXM3_301", + "MXM3_299", + "MXM3_297", + "MXM3_295", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_286", + "MXM3_239", + "MXM3_35", + "MXM3_205", + "MXM3_203", + "MXM3_201", + "MXM3_116", + "MXM3_114", + "MXM3_262", + "MXM3_274", + "MXM3_124", + "MXM3_110", + "MXM3_120", + "MXM3_263", + "MXM3_265", + "", + "MXM3_135", + "MXM3_261", + "MXM3_259"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "MXM3_194", + "MXM3_136", + "MXM3_134", + "MXM3_140", + "MXM3_138", + "", + "MXM3_220", + "", + "", + "MXM3_18", + "MXM3_16", + "", + "", + "MXM3_214", + "MXM3_216", + "MXM3_164"; +}; + +&gpio5 { + gpio-line-names = "MXM3_159", + "", + "", + "", + "MXM3_257", + "", + "", + "", + "", + "", + "MXM3_200", + "MXM3_196", + "MXM3_204", + "MXM3_202", + "", + "", + "", + "", + "MXM3_191", + "MXM3_197", + "MXM3_77", + "MXM3_195", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_209", + "MXM3_211", + "MXM3_118", + "MXM3_112", + "MXM3_187", + "MXM3_185"; +}; + +&gpio6 { + gpio-line-names = "MXM3_183", + "MXM3_181", + "MXM3_179", + "MXM3_177", + "MXM3_175", + "MXM3_173", + "MXM3_255", + "MXM3_83", + "MXM3_91", + "MXM3_13/GPIO6", + "MXM3_11/GPIO5", + "MXM3_79", + "", + "", + "MXM3_190", + "MXM3_193", + "MXM3_89"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_99", + "MXM3_85", + "MXM3_217", + "MXM3_215"; +}; + +&gpr { + ipu1_csi0_mux { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + ipu1_csi0_mux_from_parallel_sensor: endpoint { + remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@7 { + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + reg = <7>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; + status = "disabled"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + /* These GPIOs are muxed with the iomuxc node */ + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ + reg = <0x4a>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ + status = "disabled"; + }; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; + }; + + swbst_reg: swbst { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; + }; + + snvs_reg: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; + }; + + vref_reg: vrefddr { + regulator-always-on; + regulator-boot-on; + }; + + vgen1_reg: vgen1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; + }; + + vgen2_reg: vgen2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; + }; + + vgen3_reg: vgen3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + vgen4_reg: vgen4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + vgen5_reg: vgen5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + vgen6_reg: vgen6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + blocks = <0x5>; + id = <0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + interrupt-parent = <&gpio4>; + irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC conversion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_ts: stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + status = "disabled"; + }; + + stmpe_adc: stmpe_adc { + compatible = "st,stmpe-adc"; + #io-channel-cells = <1>; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + adv_7280: adv7280@21 { + compatible = "adi,adv7280"; + adv,force-bt656-4; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + reg = <0x21>; + status = "disabled"; + + port { + adv7280_to_ipu1_csi0_mux: endpoint { + bus-width = <8>; + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; + + ov5640_csi_cam: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + AVDD-supply = <®_ov5640_2v8_a_vdd>; + DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; + DVDD-supply = <®_ov5640_1v8_d_o_vdd>; + clock-names = "xclk"; + clocks = <&clks IMX6QDL_CLK_CKO2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam_mclk>; + /* These GPIOs are muxed with the iomuxc node */ + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&mipi_csi_from_ov5640>; + }; + }; + }; +}; + +&ipu1_di1_disp1 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + }; + }; + }; +}; + +&mipi_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi_from_ov5640: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5640_to_mipi_csi2>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart2 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart4 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_dte>; + status = "disabled"; +}; + +&uart5 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_dte>; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "disabled"; +}; + +/* MMC1 */ +&usdhc1 { + bus-width = <8>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; + vqmmc-supply = <®_module_3v3>; + status = "disabled"; +}; + +/* SD1 */ +&usdhc2 { + bus-width = <4>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vqmmc-supply = <®_module_3v3>; + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; + status = "okay"; +}; + +&weim { + status = "disabled"; +}; + +&iomuxc { + /* Mux the Apalis GPIOs */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 + &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 + &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 + &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 + >; + + pinctrl_apalis_gpio1: apalisgpio1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 + >; + }; + + pinctrl_apalis_gpio2: apalisgpio2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 + >; + }; + + pinctrl_apalis_gpio3: apalisgpio3grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 + >; + }; + + pinctrl_apalis_gpio4: apalisgpio4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 + >; + }; + + pinctrl_apalis_gpio5: apalisgpio5grp { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 + >; + }; + + pinctrl_apalis_gpio6: apalisgpio6grp { + fsl,pins = < + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 + >; + }; + + pinctrl_apalis_gpio7: apalisgpio7grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 + >; + }; + + pinctrl_apalis_gpio8: apalisgpio8grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_cam_mclk: cammclkgrp { + fsl,pins = < + /* CAM sys_mclk */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 + /* SPI1 cs */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + /* SPI2 cs */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* Ethernet PHY reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 + /* Ethernet PHY interrupt */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 + >; + }; + + pinctrl_flexcan1_default: flexcan1defgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan1_sleep: flexcan1slpgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 + >; + }; + + pinctrl_flexcan2_default: flexcan2defgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + pinctrl_flexcan2_sleep: flexcan2slpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 + >; + }; + + pinctrl_gpio_bl_on: gpioblongrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio1io04grp { + fsl,pins = < + /* Power button */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 + >; + }; + + pinctrl_ipu1_lcdif: ipu1lcdifgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 + /* DE */ + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 + /* HSync */ + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 + /* VSync */ + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 + >; + }; + + pinctrl_ipu2_vdac: ipu2vdacgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 + >; + }; + + pinctrl_mmc_cd: mmccdgrp { + fsl,pins = < + /* MMC1 CD */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_regulator_usbh_pwr: regusbhpwrgrp { + fsl,pins = < + /* USBH_EN */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 + >; + }; + + pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { + fsl,pins = < + /* USBH_HUB_EN */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 + >; + }; + + pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { + fsl,pins = < + /* USBO1 power en */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 + >; + }; + + pinctrl_reset_moci: resetmocigrp { + fsl,pins = < + /* RESET_MOCI control */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 + >; + }; + + pinctrl_sd_cd: sdcdgrp { + fsl,pins = < + /* SD1 CD */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touch_int: touchintgrp { + fsl,pins = < + /* STMPE811 interrupt */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart1_dce: uart1dcegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart1_dte: uart1dtegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2_dce: uart2dcegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart2_dte: uart2dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4_dce: uart4dcegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart4_dte: uart4dtegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5_dce: uart5dcegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart5_dte: uart5dtegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1_4bit: usdhc1-4bitgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1-8bitgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi new file mode 100644 index 000000000000..b78ed7974ea9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Armadeus Systems + +#include +#include + +/ { + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_3p3v>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <15>; + power-off-delay-us = <70>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; + }; +}; + +/* Bluetooth */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +/* Wi-Fi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <38400000>; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi new file mode 100644 index 000000000000..2577eb4f535a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Armadeus Systems + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 191000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <0>; + power-supply = <®_5v>; + }; + + disp0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_disp0>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user-button { + label = "User button"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + user-led { + label = "User LED"; + gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + panel { + compatible = "armadeus,st0700-adapt"; + power-supply = <®_3p3v>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5v>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound { + compatible = "fsl,imx6-armadeus-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-armadeus-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 10 GPIO_ACTIVE_LOW>, + <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@48 { + compatible = "semtech,sx8654"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* GSM */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; + uart-has-rtscts; + status = "okay"; +}; + +/* console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_5v>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + dr_mode = "otg"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 + >; + }; + + pinctrl_gsm: gsmgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp0: ipu1disp0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi new file mode 100644 index 000000000000..baa197c90060 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * support fot the imx6 based aristainetos board + * + * Copyright (C) 2014 Heiko Schocher + */ + +#include + +/ { + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@68 { + compatible = "dallas,m41t00"; + reg = <0x68>; + }; +}; + +&ecspi4 { + cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; + + imx6qdl-aristainetos { + pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi new file mode 100644 index 000000000000..6b64b2fc3995 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi @@ -0,0 +1,637 @@ +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2015 Heiko Schocher + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW + &gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&ecspi4 { + cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + flash: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <04 0x8>; + + regulators { + bcore1 { + regulator-name = "bcore1"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bcore2 { + regulator-name = "bcore2"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bpro { + regulator-name = "bpro"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bperi { + regulator-name = "bperi"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bmem { + regulator-name = "bmem"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3 { + regulator-name = "ldo3"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4 { + regulator-name = "ldo4"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "ldo5"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "ldo6"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "ldo7"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo8 { + regulator-name = "ldo8"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9 { + regulator-name = "ldo9"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo10 { + regulator-name = "ldo10"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo11 { + regulator-name = "ldo11"; + regulator-always-on; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bio { + regulator-name = "bio"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + expander: tca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@68 { + compatible = "dallas,m41t00"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + eeprom@50{ + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi new file mode 100644 index 000000000000..570995707504 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -0,0 +1,1309 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +#include +#include + +/ { + model = "Toradex Colibri iMX6DL/S Module"; + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + power-supply = <®_module_3v3>; + pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + extcon_usbc_det: usbc-det { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-wakeup { + debounce-interval = <10>; + gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + panel_dpi: panel-dpi { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; + status = "disabled"; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias"; + model = "imx6dl-colibri-sgtl5000"; + mux-int-port = <1>; + mux-ext-port = <5>; + ssi-controller = <&ssi1>; + }; + + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ + sound_spdif: sound-spdif { + compatible = "fsl,imx-audio-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + model = "imx-spdif"; + status = "disabled"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; + status = "okay"; +}; + +/* Optional on SODIMM 55/63 */ +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +/* Optional on SODIMM 178/188 */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&clks { + fsl,pmic-stby-poweroff; +}; + +/* Colibri SSP */ +&ecspi4 { + cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "disabled"; +}; + +&fec { + phy-mode = "rmii"; + phy-handle = <ðphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + micrel,led-mode = <0>; + }; + }; +}; + +&gpio1 { + gpio-line-names = "", + "SODIMM_67", + "SODIMM_180", + "SODIMM_196", + "SODIMM_174", + "SODIMM_176", + "SODIMM_194", + "SODIMM_55", + "SODIMM_63", + "SODIMM_28", + "SODIMM_93", + "SODIMM_69", + "SODIMM_99", + "SODIMM_130", + "SODIMM_106", + "SODIMM_98", + "SODIMM_192", + "SODIMM_49", + "SODIMM_190", + "SODIMM_51", + "SODIMM_47", + "SODIMM_53", + "", + "SODIMM_22"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_132", + "SODIMM_134", + "SODIMM_135", + "SODIMM_133", + "SODIMM_102", + "SODIMM_43", + "SODIMM_127", + "SODIMM_37", + "SODIMM_104", + "SODIMM_59", + "SODIMM_30", + "SODIMM_100", + "SODIMM_38", + "SODIMM_34", + "SODIMM_32", + "SODIMM_36", + "SODIMM_59", + "SODIMM_67", + "SODIMM_97", + "SODIMM_79", + "SODIMM_103", + "SODIMM_101", + "SODIMM_45", + "SODIMM_105", + "SODIMM_107", + "SODIMM_91", + "SODIMM_89", + "SODIMM_150", + "SODIMM_126", + "SODIMM_128", + "", + "SODIMM_94"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_111", + "SODIMM_113", + "SODIMM_115", + "SODIMM_117", + "SODIMM_119", + "SODIMM_121", + "SODIMM_123", + "SODIMM_125", + "SODIMM_110", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_118", + "SODIMM_120", + "SODIMM_122", + "SODIMM_124", + "", + "SODIMM_96", + "SODIMM_77", + "SODIMM_25", + "SODIMM_27", + "SODIMM_88", + "SODIMM_90", + "SODIMM_31", + "SODIMM_23", + "SODIMM_29", + "SODIMM_71", + "SODIMM_73", + "SODIMM_92", + "SODIMM_81", + "SODIMM_131", + "SODIMM_129"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "SODIMM_168", + "", + "", + "", + "", + "SODIMM_184", + "SODIMM_186", + "HDMI_15", + "HDMI_16", + "SODIMM_178", + "SODIMM_188", + "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "SODIMM_24", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_95", + "", + "SODIMM_86", + "", + "SODIMM_65", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_136", + "SODIMM_138", + "SODIMM_140", + "SODIMM_142", + "SODIMM_144", + "SODIMM_146", + "SODIMM_172", + "SODIMM_170", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_155", + "SODIMM_157", + "SODIMM_159", + "SODIMM_161", + "SODIMM_163", + "SODIMM_33", + "SODIMM_35", + "SODIMM_165", + "SODIMM_167"; +}; + +&gpio6 { + gpio-line-names = "SODIMM_169", + "SODIMM_171", + "SODIMM_173", + "SODIMM_175", + "SODIMM_177", + "SODIMM_179", + "SODIMM_85", + "SODIMM_166", + "SODIMM_160", + "SODIMM_162", + "SODIMM_158", + "SODIMM_164", + "", + "", + "SODIMM_156", + "SODIMM_75", + "SODIMM_154", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_152"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_19", + "SODIMM_21", + "", + "SODIMM_137"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ddc>; + status = "disabled"; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; + }; + + swbst_reg: swbst { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; + }; + + snvs_reg: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; + }; + + vref_reg: vrefddr { + regulator-always-on; + regulator-boot-on; + }; + + /* vgen1: unused */ + + vgen2_reg: vgen2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; + }; + + /* + * +V3.3_1.8_SD1 coming off VGEN3 and supplying + * the i.MX 6 NVCC_SD1. + */ + vgen3_reg: vgen3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + vgen4_reg: vgen4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + vgen5_reg: vgen5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + vgen6_reg: vgen6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX6QDL_CLK_CKO>; + lrclk-strength = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + blocks = <0x5>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + interrupt-controller; + id = <0>; + irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_ts: stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + status = "disabled"; + }; + + stmpe_adc: stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + }; +}; + +/* + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ + status = "disabled"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +/* Colibri PWM */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "disabled"; +}; + +/* Optional S/PDIF out on SODIMM 137 */ +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Colibri UART_B */ +&uart2 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Colibri UART_C */ +&uart3 { + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dte>; + status = "disabled"; +}; + +/* Colibri USBH */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; +}; + +/* Colibri USBC */ +&usbotg { + dr_mode = "otg"; + extcon = <0>, <&extcon_usbc_det>; + status = "disabled"; +}; + +/* Colibri MMC */ +&usdhc1 { + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + bus-width = <4>; + no-1-8-v; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 + &pinctrl_weim_cs1 &pinctrl_weim_cs2 + &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_oc_1>; + + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pin group conflicts with pin groups + * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. + */ + pinctrl_atmel_adap: atmeladaptergrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ + >; + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and + * pinctrl_weim_cs2. Don't use them simultaneously. + */ + pinctrl_atmel_conn: atmelconnectorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 + >; + }; + + pinctrl_cam_mclk: cammclkgrp { + fsl,pins = < + /* Parallel Camera CAM sys_mclk */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 + >; + }; + + /* CSI pins used as GPIOs */ + pinctrl_csi_gpio_1: csigpio1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_csi_gpio_2: csigpio2grp { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_1: gpio1grp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + pinctrl_gpio_2: gpio2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_gpio_bl_on: gpioblongrp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + >; + }; + + pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 + /* Disable PWM pins on camera interface */ + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 + >; + }; + + pinctrl_ipu1_lcdif: ipu1lcdifgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 + >; + }; + + pinctrl_lvds_transceiver: lvdstxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ + >; + }; + + pinctrl_mic_gnd: micgndgrp { + fsl,pins = < + /* Controls Mic GND, PU or '1' pull Mic GND to GND */ + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 + >; + }; + + pinctrl_mmc_cd: mmccdgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 + >; + }; + + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + fsl,pins = < + /* SODIMM 129 / USBH_PEN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touch_int: gpiotouchintgrp { + fsl,pins = < + /* STMPE811 interrupt */ + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 + >; + }; + + pinctrl_uart1_dce: uart1dcegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart1_dte: uart1dtegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2_dte: uart2dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3_dte: uart3dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbc_det: usbcdetgrp { + fsl,pins = < + /* SODIMM 137 / USBC_DET */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* USBC_DET_OVERWRITE */ + MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 + /* USBC_DET_EN */ + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 + >; + }; + + pinctrl_usbc_id_1: usbcid1grp { + fsl,pins = < + /* USBC_ID */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_usbh_oc_1: usbhoc1grp { + fsl,pins = < + /* USBH_OC */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; + + /* avoid backfeeding with removed card power */ + pinctrl_usdhc1_sleep: usdhc1sleepgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + /* nEXT_CS0 */ + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_cs1: weimcs1grp { + fsl,pins = < + /* nEXT_CS1 */ + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 + >; + }; + + pinctrl_weim_cs2: weimcs2grp { + fsl,pins = < + /* nEXT_CS2 */ + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 + >; + }; + + /* ADDRESS[16:18] [25] used as GPIO */ + pinctrl_weim_gpio_1: weimgpio1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* ADDRESS[19:24] used as GPIO */ + pinctrl_weim_gpio_2: weimgpio2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* DATA[16:31] used as GPIO */ + pinctrl_weim_gpio_3: weimgpio3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + >; + }; + + /* DQM[0:3] used as GPIO */ + pinctrl_weim_gpio_4: weimgpio4grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + + /* RDY used as GPIO */ + pinctrl_weim_gpio_5: weimgpio5grp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + /* ADDRESS[16] DATA[30] used as GPIO */ + pinctrl_weim_gpio_6: weimgpio6grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_weim_npwe: weimnpwegrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 + >; + }; + + pinctrl_weim_sram: weimsramgrp { + fsl,pins = < + /* Data */ + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + /* Address */ + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + /* Ctrl */ + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + >; + }; + + pinctrl_weim_rdnwr: weimrdnwrgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi new file mode 100644 index 000000000000..1e530d892b76 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 9 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_ir>; + }; + + led-controller { + compatible = "pwm-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_pwm1>; + + led-1 { + active-low; + label = "imx6:red:front"; + max-brightness = <248>; + pwms = <&pwm1 0 50000>; + }; + }; + + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; + + v_usb2: regulator-v-usb2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "Integrated SPDIF"; + /* IMX6 doesn't implement this yet */ + spdif-controller = <&spdif>; + spdif-out; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_key>; + pinctrl-names = "default"; + + button_0 { + label = "Button 0"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_i2c3>; + + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&iomuxc { + cubox_i { + pinctrl_cubox_i_hdmi: cubox-i-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_cubox_i_i2c2: cubox-i-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_cubox_i_i2c3: cubox-i-i2c3 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_cubox_i_ir: cubox-i-ir { + fsl,pins = < + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + >; + }; + + pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { + fsl,pins = ; + }; + + pinctrl_cubox_i_spdif: cubox-i-spdif { + fsl,pins = ; + }; + + pinctrl_cubox_i_usbh1: cubox-i-usbh1 { + fsl,pins = ; + }; + + pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_cubox_i_usbotg: cubox-i-usbotg { + /* + * The Cubox-i pulls ID low, but as it's pointless + * leaving it as a pull-up, even if it is just 10uA. + */ + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 + >; + }; + + pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_gpio_key: gpio-key { + fsl,pins = < + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 + >; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_spdif>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbh1>; + vbus-supply = <&v_usb2>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbotg>; + vbus-supply = <&v_usb1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; + vmmc-supply = <&vcc_3v3>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&vcc_3v3 { + vin-supply = <&v_5v0>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi new file mode 100644 index 000000000000..2c1d6f28e695 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/ { + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + dummy_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "dummy-supply"; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf040b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + phy-mode = "rgmii"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-dfi-fs700-m60 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ + >; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { /* module slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { /* baseboard slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; +}; + +&usdhc4 { /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi new file mode 100644 index 000000000000..702cd4a1b2e6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* + * Special SoM hardware required which uses the pins from micro SD card. The + * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 + * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD + * card must be disabled and the uart1 rts/cts must be output on other DHCOM + * pins, see uart1 and usdhc3 node below. + */ +&can2 { + status = "okay"; +}; + +&gpio1 { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <18 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "DRC02-In1", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", + "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", + "", "", "", "", "DRC02-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&uart1 { + /* + * Due to the use of can2 the signals for can2 Tx and Rx are routed to + * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs + * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. + */ + /delete-property/ uart-has-rtscts; + cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; + pinctrl-names = "default"; + rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&uart5 { + /* + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is + * controlled by DHCOM GPIO P. So remove rts/cts pins and the property + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 + * node above. + */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; + pinctrl-names = "default"; + rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +&usbh1 { + disable-over-current; +}; + +&usdhc2 { /* SD card */ + status = "okay"; +}; + +&usdhc3 { + /* + * Due to the use of can2 the micro SD card on module have to be + * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as + * can2 Tx and Rx. + */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: uart1 rts + * M: uart1 cts + * P: uart5 rs485-tx-en + * Q: uart5 rs485-rx-en + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_uart5_core: uart5-core-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi new file mode 100644 index 000000000000..6248b126b557 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2021 DH electronics GmbH + * Copyright (C) 2018 Marek Vasut + */ + +#include +#include +#include +#include + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + #clock-cells = <0>; + clock-frequency = <24000000>; + compatible = "fixed-clock"; + }; + + display_bl: display-bl { + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */ + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + status = "okay"; + }; + + lcd_display: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; + pinctrl-names = "default"; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + gpio-keys { + #size-cells = <0>; + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_a>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-1 { + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_b>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-2 { + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_c>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-3 { + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_d>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + /* + * Disable led-5, because GPIO E is + * already used as touch interrupt. + */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + status = "disabled"; + }; + + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ + pinctrl-0 = <&pinctrl_dhcom_f>; + pinctrl-names = "default"; + }; + + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ + pinctrl-0 = <&pinctrl_dhcom_h>; + pinctrl-names = "default"; + }; + + led-8 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; + + panel { + backlight = <&display_bl>; + compatible = "edt,etm0700g0edh6"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + sound { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx-sgtl5000"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + pinctrl-0 = <&pinctrl_audmux_ext>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "disabled"; +}; + +/* 1G ethernet */ +/delete-node/ ðphy0; +&fec { + phy-mode = "rgmii"; + phy-handle = <ðphy7>; + pinctrl-0 = <&pinctrl_enet_1G>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy7: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy7>; + pinctrl-names = "default"; + reg = <7>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + sgtl5000: codec@a { + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <&sw2_reg>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + reg = <0x38>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pcie { + pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; + reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */ + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; +}; + +&usdhc2 { /* SD card */ + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * A: key TA1 + * B: key TA2 + * C: key TA3 + * D: key TA4 + * E: touchscreen + * F: led6 + * G: backlight enable + * H: led7 + * I: led8 + * J: PCIe reset + */ + &pinctrl_hog_base + &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_audmux_ext: audmux-ext-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + >; + }; + + pinctrl_enet_1G: enet-1G-grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + >; + }; + + pinctrl_ethphy7: ethphy7-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi new file mode 100644 index 000000000000..4cd4cb9543c8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +#include + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "", + "", "", "", "", "", "", "", "", + "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H", + "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "", + "", "", "", "", "PicoITX-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: yellow led + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi new file mode 100644 index 000000000000..eaa87b333164 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi @@ -0,0 +1,850 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2021 DH electronics GmbH + * Copyright (C) 2018 Marek Vasut + */ + +#include +#include +#include +#include + +/ { + aliases { + i2c0 = &i2c2; + i2c1 = &i2c1; + i2c2 = &i2c3; + mmc0 = &usdhc2; + mmc1 = &usdhc3; + mmc2 = &usdhc4; + mmc3 = &usdhc1; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart5; + serial2 = &uart4; + serial3 = &uart2; + serial4 = &uart3; + }; + + memory@10000000 { /* Appropriate memory size will be filled by U-Boot */ + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + reg_3p3v: regulator-3P3V { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3P3V"; + }; + + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio1 7 0>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&sw2_reg>; + }; + + /* OE pin of the latch is low active */ + reg_latch_oe_on: regulator-latch-oe-on { + compatible = "regulator-fixed"; + gpio = <&gpio3 22 0>; + regulator-always-on; + regulator-name = "latch_oe_on"; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 31 0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb_h1_vbus"; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * Special SoM hardware required which uses the pins from micro SD card. The + * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 + * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on + * the board device tree file, the micro SD card must be disabled and the uart1 + * rts/cts must be disabled or output on other DHCOM pins. + */ +&can2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { /* S25FL116K */ + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&fec { + phy-mode = "rmii"; + phy-handle = <ðphy0>; + pinctrl-0 = <&pinctrl_enet_100M>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0>; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "", + "", "", "", "", "", "", "", "", + "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "DHCOM-G", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H", + "DHCOM-I", "DHCOM-L", "", "", "", "", "", "", + "", "", "", "", "DHCOM-F", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "DHCOM-D", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "DHCOM-J", "DHCOM-K", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "DHCOM-M", "DHCOM-N", "", "", "", "", "", "", + "", "", "", "", "", "DHCOM-P", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + /* + * Info: According to erratum ERR007805 clock frequency limit is 375000. + * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2]. + * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf + * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf + */ + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c2 { + /* Info: Clock frequency limit is 375000 (for details see i2c1) */ + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + /* Info: Clock frequency limit is 375000 (for details see i2c1) */ + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + reg = <0x3c>; + + regulators { + sw1_reg: sw1 { + lltc,fb-voltage-divider = <100000 110000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1527272>; + regulator-min-microvolt = <787500>; + regulator-ramp-delay = <7000>; + regulator-suspend-mem-microvolt = <1040000>; + }; + + sw2_reg: sw2 { + lltc,fb-voltage-divider = <100000 28000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3657142>; + regulator-min-microvolt = <1885714>; + regulator-ramp-delay = <7000>; + }; + + sw3_reg: sw3 { + lltc,fb-voltage-divider = <100000 110000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1527272>; + regulator-min-microvolt = <787500>; + regulator-ramp-delay = <7000>; + regulator-suspend-mem-microvolt = <980000>; + }; + + sw4_reg: sw4 { + lltc,fb-voltage-divider = <100000 93100>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1659291>; + regulator-min-microvolt = <855571>; + regulator-ramp-delay = <7000>; + }; + + ldo1_reg: ldo1 { + lltc,fb-voltage-divider = <102000 29400>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3240306>; + regulator-min-microvolt = <3240306>; + }; + + ldo2_reg: ldo2 { + lltc,fb-voltage-divider = <100000 41200>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2484708>; + regulator-min-microvolt = <2484708>; + }; + }; + }; + + touchscreen@49 { /* TSC2004 */ + compatible = "ti,tsc2004"; + interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_tsc2004>; + pinctrl-names = "default"; + reg = <0x49>; + vio-supply = <®_3p3v>; + status = "disabled"; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + rtc_i2c: rtc@56 { + compatible = "microcrystal,rv3029"; + interrupt-parent = <&gpio7>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; + reg = <0x56>; + }; +}; + +&pcie { + pinctrl-0 = <&pinctrl_pcie>; + pinctrl-names = "default"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; +}; + +®_arm { + vin-supply = <&sw3_reg>; +}; + +®_pu { + vin-supply = <&sw1_reg>; +}; + +®_soc { + vin-supply = <&sw1_reg>; +}; + +®_vdd1p1 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&sw2_reg>; +}; + +&uart1 { /* DHCOM UART1 */ + dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { /* DHCOM UART3 */ + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart5 { /* DHCOM UART2 */ + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + pinctrl-0 = <&pinctrl_usbh1>; + pinctrl-names = "default"; + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + dr_mode = "otg"; + pinctrl-0 = <&pinctrl_usbotg>; + pinctrl-names = "default"; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usdhc2 { /* External SD card via DHCOM */ + cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&usdhc3 { /* Micro SD card on module */ + cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + keep-power-in-suspend; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc4 { /* eMMC on module */ + bus-width = <8>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + pinctrl-0 = <&pinctrl_usdhc4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&weim { + #address-cells = <2>; + #size-cells = <1>; + fsl,weim-cs-gpr = <&gpr>; + pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>; + pinctrl-names = "default"; + /* It is necessary to setup 2x 64MB otherwise setting gpr fails */ + ranges = <0 0 0x08000000 0x04000000>, /* CS0 */ + <1 0 0x0c000000 0x04000000>; /* CS1 */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-0 = < + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_hog_base: hog-base-grp { + fsl,pins = < + /* GPIOs for memory coding */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0 + /* GPIOs for hardware coding */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 + >; + }; + + /* DHCOM GPIOs */ + pinctrl_dhcom_a: dhcom-a-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_b: dhcom-b-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_c: dhcom-c-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_d: dhcom-d-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_e: dhcom-e-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_f: dhcom-f-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_g: dhcom-g-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_h: dhcom-h-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_i: dhcom-i-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_j: dhcom-j-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_k: dhcom-k-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_l: dhcom-l-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_m: dhcom-m-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_n: dhcom-n-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_o: dhcom-o-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_p: dhcom-p-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_q: dhcom-q-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_r: dhcom-r-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_s: dhcom-s-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_t: dhcom-t-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_u: dhcom-u-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_v: dhcom-v-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_w: dhcom-w-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_int: dhcom-int-grp { + fsl,pins = ; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; + + pinctrl_enet_100M: enet-100M-grp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_vio: enet-vio-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 + >; + }; + + pinctrl_ethphy0: ethphy0-grp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + >; + }; + + pinctrl_pcie: pcie-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0 + >; + }; + + pinctrl_tsc2004: tsc2004-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1 + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1 + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1 + >; + }; + + pinctrl_usbh1: usbh1-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotg-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0 + >; + }; + + pinctrl_usdhc4: usdhc4-grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_weim: weim-grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */ + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */ + >; + }; + + pinctrl_weim_cs0: weim-cs0-grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_cs1: weim-cs1-grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi new file mode 100644 index 000000000000..f7e517555697 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov2659_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>; + status = "okay"; + + m25p80: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov2659: camera@30 { + compatible = "ovti,ov2659"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2659>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xvclk"; + reg = <0x30>; + powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov2659_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + link-frequencies = /bits/ 64 <70000000>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + >; + }; + + pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ov2659: ov2659grp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi new file mode 100644 index 000000000000..c4e146f3341b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +/ { + aliases { + boardid = &boardid; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + mmc3 = &usdhc4; + }; + + reg_wall_5p0: reg-wall5p0 { + compatible = "regulator-fixed"; + regulator-name = "Main-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base3p3: reg-base3p3 { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base1p5: reg-base1p5 { + compatible = "regulator-fixed"; + vin-supply = <®_base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: reg-otgvbus { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + clk_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_codec>; + VDDA-supply = <®_base3p3>; + VDDIO-supply = <®_base3p3>; + }; + + captouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + boardid: gpio@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&pcie { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..ee2dd75cead6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi @@ -0,0 +1,834 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +#include +#include +#include + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &ds1307; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = ; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + led-green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led-red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = < + 0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; + + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + + rgb_encoder: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: lcd { + backlight = <&rgb_backlight>; + power-supply = <®_parallel_disp>; + + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + reg_parallel_disp: reg-parallel-display { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: reg-lvds-display { + compatible = "regulator-fixed"; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rgb_backlight: rgb-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = < + 250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 27 GPIO_ACTIVE_LOW>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + da9063: pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + wakeup-source; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <2>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <2>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <2>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <2>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; + + ds1307: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + #pwm-cells = <2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + +/*******Disabled HW following***********/ + +&snvs_rtc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi new file mode 100644 index 000000000000..e75e1a5364b8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi @@ -0,0 +1,638 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + bus-width = <8>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi new file mode 100644 index 000000000000..47d9a8d08197 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -0,0 +1,795 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi new file mode 100644 index 000000000000..fb1d29abe099 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -0,0 +1,784 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <11 2>; + wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi new file mode 100644 index 000000000000..a642be45ffe2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -0,0 +1,877 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_h1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound-analog { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ + status = "okay"; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + }; + + fan-controller@2c { + compatible = "gw,gsc-fan"; + reg = <0x2c>; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <&sw4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default", "state_dio"; + pinctrl-0 = <&pinctrl_pwm4_backlight>; + pinctrl-1 = <&pinctrl_pwm4_dio>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_ecspi2: escpi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4_backlight: pwm4grpbacklight { + fsl,pins = < + /* LVDS_PWM J6.5 */ + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4_dio: pwm4grpdio { + fsl,pins = < + /* DIO3 J16.4 */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi new file mode 100644 index 000000000000..29960d1cf6a0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -0,0 +1,695 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&hdmi_receiver>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8a"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0b"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_3P3 (1+R1/R2 = 1.281) */ + reg_3p3: sw4 { + regulator-name = "vdd3p3"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <3647000>; + lltc,fb-voltage-divider = <200000 56200>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ + reg_1p8a: ldo2 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1816125>; + regulator-max-microvolt = <1816125>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8b: HDMI In analog */ + reg_1p8b: ldo3 { + regulator-name = "vdd1p8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + gpio_exp: pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3>; + AVDD-supply = <®_1p8b>; + DVDD-supply = <®_1p8a>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi new file mode 100644 index 000000000000..77ae611b817a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; }; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi new file mode 100644 index 000000000000..7f16c602cc07 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi @@ -0,0 +1,738 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8a"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0b"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_3P3 (1+R1/R2 = 1.281) */ + reg_3p3v: sw4 { + regulator-name = "vdd3p3"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <3647000>; + lltc,fb-voltage-divider = <200000 56200>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ + reg_1p8a: ldo2 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1816125>; + regulator-max-microvolt = <1816125>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8b: microSD VDD_1P8 */ + reg_1p8b: ldo3 { + regulator-name = "vdd1p8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + bus-width = <8>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi new file mode 100644 index 000000000000..46cf4080fec3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -0,0 +1,931 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + backlight-keypad { + compatible = "gpio-backlight"; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + default-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_12p0v: regulator-12p0v { + compatible = "regulator-fixed"; + regulator-name = "12P0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1p4v: regulator-vddsoc { + compatible = "regulator-fixed"; + regulator-name = "vdd_soc"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an2"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + ds1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + }; + + tca8418: keypad@34 { + compatible = "ti,tca8418"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keypad>; + reg = <0x34>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) + MATRIX_KEY(0x00, 0x00, BTN_1) + MATRIX_KEY(0x01, 0x01, BTN_2) + MATRIX_KEY(0x01, 0x00, BTN_3) + MATRIX_KEY(0x02, 0x00, BTN_4) + MATRIX_KEY(0x00, 0x03, BTN_5) + MATRIX_KEY(0x00, 0x02, BTN_6) + MATRIX_KEY(0x01, 0x03, BTN_7) + MATRIX_KEY(0x01, 0x02, BTN_8) + MATRIX_KEY(0x02, 0x02, BTN_9) + >; + keypad,num-rows = <4>; + keypad,num-columns = <4>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.931) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <796551>; + regulator-max-microvolt = <1544827>; + lltc,fb-voltage-divider = <243000 261000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_arm>; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw4 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ + reg_1p0v: ldo2 { + regulator-name = "vdd1p0"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1050000>; + lltc,fb-voltage-divider = <78700 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + egalax_ts: touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio5>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + }; +}; + +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* AUD4 */ + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + /* AUD6 */ + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + >; + }; + + pinctrl_flexcan: flexcangrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 + >; + }; + + pinctrl_keypad: keypadgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi new file mode 100644 index 000000000000..a74cde050158 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -0,0 +1,793 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 30 0>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_12p0: regulator-12p0v { + compatible = "regulator-fixed"; + regulator-name = "12P0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-tlv320"; + model = "imx-tlv320"; + ssi-controller = <&ssi1>; + audio-codec = <&tlv320aic3105>; + /* routing of sink, source */ + audio-routing = + /* TLV320 LINE1L pin <-> Mic Jack connector */ + "LINE1L", "Mic Jack", + /* board Headphone Jack <-> HPOUT */ + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Mic Jack", "Mic Bias"; + mux-int-port = <1>; + mux-ext-port = <6>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + dts1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ + reg_1p8v: sw1 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_arm>; + }; + + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw4 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_soc>; + }; + + /* VDD_1P0 (1+R1/R2 = 1.38): */ + reg_1p0v: ldo2 { + regulator-name = "vdd1p0"; + regulator-min-microvolt = <1002777>; + regulator-max-microvolt = <1002777>; + lltc,fb-voltage-divider = <100000 261000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + tlv320aic3105: codec@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_CKO>; + ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ + /* Regulators */ + DRVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <®_1p8v>; + }; + + accelerometer@1d { + compatible = "fsl,mma8451"; + reg = <0x1d>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; + }; + + /* headphone detect */ + ts3a227e@3b { + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&gpio5>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + ti,micbias = <4>; /* 2.5V micbias */ + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: g101evn010 { + clock-frequency = <68930000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_3p3v>; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + max-frequency = <100000000>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + /* I2C3 */ + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + + /* Headphone Detect */ + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ + + /* Codec */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ + + /* Touch Controller */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ + + /* Stow Sensor */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ + + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi new file mode 100644 index 000000000000..9594bc5745ed --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -0,0 +1,820 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@5 { + reg = <5>; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + dts1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + crypto@60 { + compatible = "atmel,atecc508a"; + reg = <0x60>; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + egalax_ts: touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi new file mode 100644 index 000000000000..955a51226eda --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <0>; + ti,datarate = <5>; + }; + + channel@5 { + reg = <5>; + ti,gain = <0>; + ti,datarate = <5>; + }; + + channel@6 { + reg = <6>; + ti,gain = <0>; + ti,datarate = <5>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi new file mode 100644 index 000000000000..218d6e667ed2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_wl: regulator-wl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <22100 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_3p0"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_arm"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_1p5"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_an1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accel@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio7>; + interrupts = <13 0>; + interrupt-names = "INT1"; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +/* off-board RS232 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* serial console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* cc1352 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +/* Sterling-LWB Bluetooth */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; +}; + +/* GPS */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +/* Sterling-LWB SDIO WiFi */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_wl>; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_accel: accelmuxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_bten: btengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi new file mode 100644 index 000000000000..de5983cf7810 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi @@ -0,0 +1,604 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: led-user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + + fan-controller@a { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accel@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio7>; + interrupts = <13 0>; + interrupt-names = "INT1"; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_accel: accelmuxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + >; + }; + + pinctrl_ecspi2: escpi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi new file mode 100644 index 000000000000..82f47c295b08 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: led-user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: led-user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <22100 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_arm"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_soc"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_1p5"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_1p0"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_3p0"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_an1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi new file mode 100644 index 000000000000..bfade7149080 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi @@ -0,0 +1,368 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/ { + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; + }; + + v_3v2: regulator-v-3v2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_3v2"; + vin-supply = <&v_5v0>; + }; + + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; + + v_sd: regulator-v-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_sd"; + startup-delay-us = <1000>; + vin-supply = <&v_3v2>; + }; + + v_usb2: regulator-v-usb2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; + }; + + audio: sound-sgtl5000 { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board Codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = + "Microphone", "Headphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Headphone Jack", + "Headphone Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "On-board SPDIF"; + /* IMX6 doesn't implement this yet */ + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&audmux { + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCSEL(4) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c1>; + status = "okay"; + + /* Pro baseboard model */ + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + /* Pro baseboard model */ + sgtl5000: codec@a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; + #sound-dai-cells = <0>; + reg = <0x0a>; + VDDA-supply = <&v_3v2>; + VDDIO-supply = <&v_3v2>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c2>; + status = "okay"; +}; + +&iomuxc { + hummingboard { + pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { + fsl,pins = < + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 + >; + }; + + pinctrl_hummingboard_hdmi: hummingboard-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard_i2c1: hummingboard-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_i2c2: hummingboard-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { + fsl,pins = < + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 + >; + }; + + pinctrl_hummingboard_pwm1: pwm1grp { + fsl,pins = ; + }; + + pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_hummingboard_spdif: hummingboard-spdif { + fsl,pins = ; + }; + + pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { + /* + * We want it pulled down for a fixed host connection. + */ + fsl,pins = ; + }; + + pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + >; + }; + + pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + pinctrl_hummingboard_vmmc: hummingboard-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; + reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <&v_usb2>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; + vbus-supply = <&v_usb1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_hummingboard_usdhc2_aux + &pinctrl_hummingboard_usdhc2 + >; + vmmc-supply = <&v_sd>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&vcc_3v3 { + vin-supply = <&v_3v2>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi new file mode 100644 index 000000000000..f400405381a7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi @@ -0,0 +1,72 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&iomuxc { + hummingboard2 { + pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; + vmmc-supply = <&v_3v2>; + vqmmc-supply = <&v_3v2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi new file mode 100644 index 000000000000..0883ef99cded --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi @@ -0,0 +1,577 @@ +/* + * Copyright (C) 2015 Rabeeh Khoury + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/ { + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + v_3v2: regulator-v-3v2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_3v2"; + }; + + v_5v0: regulator-v-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_5v0"; + }; + + vcc_1p8: regulator-vcc-1p8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1p8"; + vin-supply = <&v_3v2>; + }; + + v_sd: regulator-v-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "v_sd"; + startup-delay-us = <1000>; + vin-supply = <&v_3v2>; + }; + + v_usb1: regulator-v-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb1"; + vin-supply = <&v_5v0>; + }; + + v_usb2: regulator-v-usb2 { + /* USB hub port 1 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb2"; + vin-supply = <&v_5v0>; + }; + + v_usb3: regulator-v-usb3 { + /* USB hub port 3 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb3"; + vin-supply = <&v_5v0>; + }; + + v_usb4: regulator-v-usb4 { + /* USB hub port 4 */ + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "v_usb4"; + vin-supply = <&v_5v0>; + }; + + audio: sound-sgtl5000 { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board Codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCSEL(4) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; + status = "okay"; + + pcf8523: rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sgtl5000: codec@a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <&v_3v2>; + VDDD-supply = <&vcc_1p8>; + VDDIO-supply = <&v_3v2>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hummingboard2 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 36 pin headers GPIO description. The pins + * numbering as following - + * + * 3.2v 5v 74 75 + * 73 72 71 70 + * 69 68 67 66 + * + * 77 78 79 76 + * 65 64 61 60 + * 53 52 51 50 + * 49 48 166 132 + * 95 94 90 91 + * GND 54 24 204 + * + * The GPIO numbers can be extracted using + * signal name from below. + * Example - + * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is + * GPIO(3,10) which is (3-1)*32+10 = gpio 74 + * + * i.e. The mapping of GPIO(X,Y) to Linux gpio + * number is : gpio number = (X-1) * 32 + Y + */ + /* DI1_PIN15 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 + /* DI1_PIN02 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 + /* DISP1_DATA00 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 + /* DISP1_DATA01 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 + /* DISP1_DATA02 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 + /* DISP1_DATA03 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 + /* DISP1_DATA04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 + /* DISP1_DATA05 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 + /* DISP1_DATA06 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 + /* DISP1_DATA07 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 + /* DI1_D0_CS */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 + /* DI1_D1_CS */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 + /* DI1_PIN01 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 + /* DI1_PIN03 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 + /* DISP1_DATA08 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 + /* DISP1_DATA09 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 + /* DISP1_DATA10 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 + /* DISP1_DATA11 */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 + /* DISP1_DATA12 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 + /* DISP1_DATA13 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 + /* DISP1_DATA14 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 + /* DISP1_DATA15 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 + /* DISP1_DATA16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 + /* DISP1_DATA17 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 + /* DISP1_DATA18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 + /* DISP1_DATA19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 + /* DISP1_DATA20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 + /* DISP1_DATA21 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 + /* DISP1_DATA22 */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 + /* DISP1_DATA23 */ + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 + /* DI1_DISP_CLK */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 + /* SPDIF_IN */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 + /* SPDIF_OUT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 + + /* MikroBUS GPIO pin number 10 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 + >; + }; + + pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ + >; + }; + + pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 + >; + }; + + pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_mipi: hummingboard2_mipi { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { + /* + * We want it pulled down for a fixed host connection. + */ + fsl,pins = ; + }; + + pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 + >; + }; + + pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 + >; + }; + + pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 + >; + }; + + pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hummingboard2_uart3: hummingboard2-uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; + reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; + vbus-supply = <&v_usb1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2 + >; + pinctrl-1 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_100mhz + >; + pinctrl-2 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_200mhz + >; + vmmc-supply = <&v_sd>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_uart3>; + status = "okay"; +}; + +&vcc_3v3 { + vin-supply = <&v_3v2>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi new file mode 100644 index 000000000000..0fd7f2e24d9c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Jacopo Mondi + */ + +#include "imx6qdl-icore.dtsi" + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi new file mode 100644 index 000000000000..d339957cc097 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * Copyright (C) 2015 Engicam S.r.l. + */ + +#include +#include +#include + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_sd3_vmmc: regulator-sd3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "P3V3_SD3_SWITCHED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + enable-active-high; + }; + + reg_sd4_vmmc: regulator-sd4-vmmc { + compatible = "regulator-fixed"; + regulator-name = "P3V3_SD4_SWITCHED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + usb_hub: usb-hub { + compatible = "smsc,usb3503a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; + clock-names = "refclk"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Speaker", "Line Out Jack", + "Speaker", "Ext Spk"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + mux-aud4 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ð_phy>; + phy-mode = "rgmii"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0x0>; + rxc-skew-ps = <1140>; + txc-skew-ps = <1140>; + txen-skew-ps = <600>; + rxdv-skew-ps = <240>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <600>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <240>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <240>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + disable-over-current; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <®_sd3_vmmc>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + vmmc-supply = <®_sd4_vmmc>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi new file mode 100644 index 000000000000..efe11524b885 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +#include +#include +#include + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + chosen { + stdout-path = &uart4; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 100000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + rmii_clk: clock-rmii-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; /* 25MHz for example */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6qdl-icore-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Speaker", "Line Out Jack", + "Speaker", "Ext Spk"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + + mux-ssi1 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + mux-aud4 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + phy-mode = "rmii"; + phy-handle = <ð_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <4000>; + reset-deassert-us = <4000>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + sgtl5000: codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; +}; + +&mipi_csi { + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + no-1-8-v; + non-removable; + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi new file mode 100644 index 000000000000..85aeebc9485d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -0,0 +1,821 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017 (C) Priit Laes + * Copyright 2018 (C) Pengutronix, Michael Grzeschik + * Copyright 2019 (C) Pengutronix, Marco Felsch + * + * Based on initial work by Nikita Yushchenko + */ + +#include +#include + +/ { + reg_1p0v_s0: regulator-1p0v-s0 { + compatible = "regulator-fixed"; + regulator-name = "V_1V0_S0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_smarc_suppy>; + }; + + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V35_VCOREDIG_S5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_1p8v_s5: regulator-1p8v-s5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_3p3v_s0: regulator-3p3v-s0 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_3p3v_s5: regulator-3p3v-s5 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_smarc_suppy>; + }; + + reg_smarc_lcdbklt: regulator-smarc-lcdbklt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdbklt_en>; + regulator-name = "LCD_BKLT_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_smarc_lcdvdd: regulator-smarc-lcdvdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdvdd_en>; + regulator-name = "LCD_VDD_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_smarc_rtc: regulator-smarc-rtc { + compatible = "regulator-fixed"; + regulator-name = "V_IN_RTC_BATT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* Module supply range can be 3.00V ... 5.25V */ + reg_smarc_suppy: regulator-smarc-supply { + compatible = "regulator-fixed"; + regulator-name = "V_IN_WIDE"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + lcd: lcd { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + lcd_out: endpoint { + }; + }; + }; + + lcd_backlight: lcd-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000 0>; + pwm-names = "LCD_BKLT_PWM"; + + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <4>; + + power-supply = <®_smarc_lcdbklt>; + status = "disabled"; + }; + + i2c_intern: i2c-gpio-intern { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_intern>; + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_lcd: i2c-gpio-lcd { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_cam: i2c-gpio-cam { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_cam>; + sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; + +/* I2S0, I2S1 */ +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + audmux_ssi1 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | + IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) + >; + }; + + audmux_adu3 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; + + audmux_ssi2 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + audmux_adu4 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) + >; + }; +}; + +/* CAN0 */ +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* CAN1 */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* SPI1 */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 27 GPIO_ACTIVE_LOW>; +}; + +/* SPI0 */ +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* default boot source: workaround #1 for errata ERR006282 */ + smarc_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +/* GBE */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; +}; + +&i2c_intern { + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + reg_v_core_s0: sw1ab { + regulator-name = "V_CORE_S0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vddsoc_s0: sw1c { + regulator-name = "V_VDDSOC_S0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p15v_s0: sw2 { + regulator-name = "V_3V15_S0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* sw3a/b is used in dual mode, but driver does not + * support it. Although, there's no need to control + * DDR power - so just leaving dummy entries for sw3a + * and sw3b for now. + */ + sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v_s0: sw4 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* Regulator for USB */ + reg_5p0v_s0: swbst { + regulator-name = "V_5V0_S0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + }; + + reg_vsnvs: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* + * Per schematics, of all VGEN's, only VGEN5 has some + * usage ... but even that - over DNI resistor + */ + vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + reg_2p5v_s0: vgen5 { + regulator-name = "V_2V5_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +/* I2C_GP */ +&i2c1 { + clock-frequency = <375000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; +}; + +/* HDMI_CTRL */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +/* I2C_PM */ +&i2c3 { + clock-frequency = <375000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + smarc_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + + /* AUDIO MCLK */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + + /* SPI_IMX_CS2# - connected to internal flash */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 + /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ + >; + }; + + pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ + >; + }; + + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ + >; + }; + + pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 + + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ + >; + }; + + pinctrl_lcdbklt_en: lcdbkltengrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 + >; + }; + + pinctrl_lcdvdd_en: lcdvddengrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + >; + }; + + pinctrl_mipi_csi: mipi-csigrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ + >; + }; + + pinctrl_mgmt_gpios: mgmt-gpiosgrp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 + /* power, oc muxed but not used by the driver */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wdog1: wdog1rp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; + +&mipi_csi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; +}; + +/* LCD_BKLT_PWM */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_arm { + vin-supply = <®_v_core_s0>; +}; + +®_pu { + vin-supply = <®_vddsoc_s0>; +}; + +®_soc { + vin-supply = <®_vddsoc_s0>; +}; + +/* SER0 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; +}; + +/* SER1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* SER2 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; +}; + +/* SER3 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +/* USB0 */ +&usbotg { + /* + * no 'imx6-usb-charger-detection' + * since USB_OTG_CHD_B pin is not wired + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; +}; + +/* USB1/2 via hub */ +&usbh1 { + vbus-supply = <®_5p0v_s0>; +}; + +/* SDIO */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + no-1-8-v; +}; + +/* SDMMC */ +&usdhc4 { + /* Internal eMMC, optional on some boards */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <®_3p3v_s0>; + vqmmc-supply = <®_1p8v_s0>; +}; + +&wdog1 { + /* CPLD is feeded by watchdog (hardwired) */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi new file mode 100644 index 000000000000..212c623418fc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include +#include +#include +#include + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + /delete-property/ mmc2; + /delete-property/ mmc3; + rtc0 = &rtc0; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper: gpio-beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobeeper>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button1 { + label = "s6"; + linux,code = ; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button2 { + label = "s7"; + linux,code = ; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button3 { + label = "s8"; + linux,code = ; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_mba6_3p3v: regulator-mba6-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regpcie>; + regulator-name = "supply-pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* PCIE.PWR_EN */ + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_mba6_3p3v>; + }; + + reg_vcc3v3_audio: regulator-vcc3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-audio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_mba6_3p3v>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&ssi1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + status = "okay"; + + mux-ssi0 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) + >; + }; + + mux-aud3 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; + cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; +}; + +&fec { + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <100000>; + micrel,force-master; + max-speed = <1000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + ldoin-supply = <®_vcc3v3_audio>; + iov-supply = <®_mba6_3p3v>; + }; +}; + +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,2517"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "usb424,9e00"; + reg = <1>; + nvmem-cells = <&mba_mac_address>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + power-active-high; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* SD card slot */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_mba6_3p3v>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* does not work on unmodified starter kit */ + /* fsl,ext-reset-output; */ + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ + >; + }; + + pinctrl_ecspi1_mba6: ecspimba6grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* FEC phy IRQ */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 + /* FEC phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 + /* DSE = 100, 100k up, SPEED = MED */ + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 + /* DSE = 111, pull 100k up */ + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 + /* DSE = 111, pull external */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 + /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 + >; + }; + + pinctrl_gpiobeeper: gpiobeepergrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 + >; + }; + + pinctrl_gpiobuttons: gpiobuttongrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 + >; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 + + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 + + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 + + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 + + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 + + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 + + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 + >; + }; + + pinctrl_regpcie: regpciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 + /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 + + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + /* Watchdog out */ + MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi new file mode 100644 index 000000000000..27fec340c380 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi new file mode 100644 index 000000000000..0a9f076eeb36 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi new file mode 100644 index 000000000000..6d4eab1942b9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2015 Boundary Devices, Inc. + */ +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + home { + label = "Home"; + gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; + linux,code = <102>; + }; + + back { + label = "Back"; + gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; + linux,code = <158>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-j14-pin1 { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + retain-state-suspended; + default-state = "off"; + }; + + led-j14-pin3 { + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + retain-state-suspended; + default-state = "off"; + }; + + led-j14-pins8-9 { + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + retain-state-suspended; + default-state = "off"; + }; + + led-j46-pin2 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + retain-state-suspended; + default-state = "off"; + }; + + led-j46-pin3 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + retain-state-suspended; + default-state = "off"; + }; + }; + + backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds0>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + sound { + compatible = "fsl,imx6dl-nit6xlite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6dl-nit6xlite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + rtc@6f { + compatible = "isil,isl1208"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x6f>; + interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j10>; + pinctrl-1 = <&pinctrl_j28>; + + imx6dl-nit6xlite { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* Phy reset */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Home Button: J14 pin 5 */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Back Button: J14 pin 7 */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + /* Touch IRQ: J7 pin 4 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + /* tcs2004 IRQ */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + /* tsc2004 reset */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 + >; + }; + + pinctrl_j10: j10grp { + fsl,pins = < + /* Broadcom WiFi module pins */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 + >; + }; + + pinctrl_j28: j28grp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_wlan_vmmc: wlan-vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_wlan_vmmc>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi new file mode 100644 index 000000000000..81a9a302aec1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -0,0 +1,849 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2015 Boundary Devices, Inc. + */ +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xF0000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_can_xcvr: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + i2c2mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH + &gpio4 15 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c2>; + idle-state = <0>; + + i2c2mux@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2mux@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c3mux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3mux@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-speaker-enable { + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + default-state = "off"; + }; + + led-ttymxc4-rs232 { + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + default-state = "on"; + }; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j15>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds0>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + panel-lvds1 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds1>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6_max-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&iomuxc { + imx6q-nitrogen6-max { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* Phy reset */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2mux: i2c2muxgrp { + fsl,pins = < + /* ov5642 camera i2c enable */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 + /* ov5640_mipi camera i2c enable */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + /* PCIe I2C enable */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 + >; + }; + + pinctrl_j15: j15grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* PCIe reset */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 + /* RS485 RX Enable: pull up */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 + /* RS485 DEN: pull down */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 + /* RS485/!RS232 Select: pull down (rs232) */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 + /* ON: pull down */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wlan_vmmc: wlan-vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + + lvds-channel@1 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_vmmc>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi new file mode 100644 index 000000000000..000e9dc97b1a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016 Boundary Devices, Inc. + */ +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds1>; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j15>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds0>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + panel-lvds1 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds1>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_1p8v: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6_som2-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight_lvds1: backlight-lvds1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + /* PCIe I2C enable */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 + >; + }; + + pinctrl_j15: j15grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* PCIe reset */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wlan_vmmc: wlan-vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_vmmc>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi new file mode 100644 index 000000000000..731759bdd7f5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -0,0 +1,693 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_can_xcvr: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_wlan_vmmc: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6x-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6x-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j15>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "env"; + reg = <0xc0000 0x2000>; + }; + + partition@c2000 { + label = "splash"; + reg = <0xc2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-nitrogen6x { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* Phy reset */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_j15: j15grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ + >; + }; + + pinctrl_wlan_vmmc: wlan-vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_vmmc>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi new file mode 100644 index 000000000000..0020dbb1722c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +/ { + display: display0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0>; + interface-pix-fmt = "rgb24"; + status = "disabled"; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&peb_panel_lcd_in>; + }; + }; + }; + + panel-lcd { + compatible = "edt,etm0700g0edh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_pwr>; + power-supply = <®_display>; + enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + peb_panel_lcd_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; + + reg_display: regulator-peb-display { + compatible = "regulator-fixed"; + regulator-name = "peb-display"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c1 { + edt_ft5x06: touchscreen@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_NONE>; + status = "disabled"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_disp0: disp0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_disp0_pwr: disp0pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_edt_ft5x06: edtft5x06grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi new file mode 100644 index 000000000000..037b60197598 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + sleep { + label = "Sleep Button"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + user-led1 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..84f884d6e55b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_bt>; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl_uart3_bt: uart3grp-bt { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */ + >; + }; + + pinctrl_usdhc3_wl: usdhc3grp-wl { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi new file mode 100644 index 000000000000..1a599c294ab8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + + +/ { + aliases { + rtc0 = &i2c_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_backlight>; + pwms = <&pwm1 0 5000000>; + status = "okay"; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds>; + status = "disabled"; + + led-red { + label = "phyboard-mira:red"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "phyboard-mira:green"; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "phyboard-mira:blue"; + gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_en_switch: regulator-en-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_en_switch>; + regulator-name = "Enable Switch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_flexcan1: regulator-flexcan1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_en>; + regulator-name = "flexcan1-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "mPCIe_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: usbotg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel { + compatible = "auo,g104sn02"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_en>; + power-supply = <®_panel>; + enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_flexcan1>; + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; + ddc-i2c-bus = <&i2c2>; + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <400000>; + status = "disabled"; + + stmpe: touchctrl@44 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + reg = <0x44>; + interrupt-parent = <&gpio7>; + interrupts = <12 IRQ_TYPE_NONE>; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + reg = <0x68>; + interrupt-parent = <&gpio7>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "disabled"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "disabled"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + disable-over-current; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usbotg_vbus>; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + status = "disabled"; +}; + +&iomuxc { + pinctrl_panel_en: panelen1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 + >; + }; + + pinctrl_en_switch: enswitchgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1 + >; + }; + + pinctrl_gpioleds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 + >; + }; + + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1_vbus: usbh1vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi new file mode 100644 index 000000000000..a41e47c06ef4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + regulators { + sound_1v8: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound_3v3: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + tlv320_mclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "tlv320-mclk"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "OnboardTLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&tlv320_mclk>; + }; + }; + +}; + +&audmux { + status = "okay"; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4)) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + codec: tlv320@18 { + compatible = "ti,tlv320aic3007"; + #sound-dai-cells = <0>; + reg = <0x18>; + ai3x-micbias-vg = <2>; + + AVDD-supply = <&sound_3v3>; + IOVDD-supply = <&sound_3v3>; + DRVDD-supply = <&sound_3v3>; + DVDD-supply = <&sound_1v8>; + }; + + stmpe@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + }; + + rtc@51 { + compatible = "epson,rtc8564"; + reg = <0x51>; + }; + + adc@64 { + compatible = "maxim,max1037"; + reg = <0x64>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..80adb2a02cc9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +#include + +/ { + model = "Phytec phyFLEX-i.MX6 Quad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + enable-active-high; + }; + }; + + gpio_leds: leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + compatible = "gpio-leds"; + + led_green: led-green { + label = "phyflex:green"; + gpios = <&gpio1 30 0>; + }; + + led_red: led-red { + label = "phyflex:red"; + gpios = <&gpio2 31 0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + + som_flash: flash@0 { + compatible = "m25p80", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; /* in msecs */ + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + phy-supply = <&vdd_eth_io_reg>; + status = "disabled"; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + som_eeprom: eeprom@50 { + compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + pmic@58 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ + interrupt-controller; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_buckmem_reg: bmem { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_eth_reg: bio { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_eth_io_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_3v3_pmic_io_reg: ldo6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_sd0_reg: ldo9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd1_reg: ldo10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_mx6_high_reg: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + + da9063_rtc: rtc { + compatible = "dlg,da9063-rtc"; + }; + + da9063_wdog: watchdog { + compatible = "dlg,da9063-watchdog"; + }; + + onkey { + compatible = "dlg,da9063-onkey"; + status = "disabled"; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; +}; + +&iomuxc { + imx6q-phytec-pfla02 { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = ; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = ; /* PMIC interrupt */ + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1_vbus: usbh1vbusgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_sd1_reg>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_sd0_reg>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..28a805384668 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +#include +#include + +/ { + aliases { + rtc1 = &da9062_rtc; + rtc2 = &snvs_rtc; + }; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x8000000>; + }; + + gpio_leds_som: somleds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds_som>; + + som-led-green { + label = "phycore:green"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + m25p80: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + status = "disabled"; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-supply = <&vdd_eth_io>; + phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "st,24c32", "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + pmic: pmic@58 { + compatible = "dlg,da9062"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + + da9062_rtc: rtc { + compatible = "dlg,da9062-rtc"; + }; + + da9062_onkey: onkey { + compatible = "dlg,da9062-onkey"; + }; + + watchdog { + compatible = "dlg,da9062-watchdog"; + dlg,use-sw-pm; + }; + + thermal { + compatible = "dlg,da9062-thermal"; + status = "disabled"; + }; + + gpio { + compatible = "dlg,da9062-gpio"; + status = "disabled"; + }; + + regulators { + vdd_arm: buck1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1380000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vdd_soc: buck2 { + regulator-name = "vdd_soc"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vdd_ddr3_1p5: buck3 { + regulator-name = "vdd_ddr3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vdd_eth_1p2: buck4 { + regulator-name = "vdd_eth"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vdd_snvs: ldo1 { + regulator-name = "vdd_snvs"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_high: ldo2 { + regulator-name = "vdd_high"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_eth_io: ldo3 { + regulator-name = "vdd_eth_io"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vdd_emmc_1p8: ldo4 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +®_arm { + vin-supply = <&vdd_arm>; +}; + +®_pu { + vin-supply = <&vdd_soc>; +}; + +®_soc { + vin-supply = <&vdd_soc>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "disabled"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + >; + }; + + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 + MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi new file mode 100644 index 000000000000..3a968782e854 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2017 NXP + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&i2c1 { + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + io-expander@25 { + compatible = "nxp,pca9554"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi new file mode 100644 index 000000000000..144c4727fbc7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2017 NXP + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&i2c2 { + status = "okay"; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi new file mode 100644 index 000000000000..3d56a4216448 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&i2c1 { + adc@52 { + compatible = "ti,adc081c"; + reg = <0x52>; + vref-supply = <®_2p5v>; + }; +}; + +&i2c2 { + io-expander@25 { + compatible = "nxp,pca9554"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; +}; + +&i2c3 { + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&pcie { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi new file mode 100644 index 000000000000..b823dce62e63 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2017 NXP + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&hdmi { + status = "disabled"; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi new file mode 100644 index 000000000000..c39a9ebdaba1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; + + codec_osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6-pico-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 50000 0>; + brightness-levels = <0 36 72 108 144 180 216 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel { + compatible = "vxt,vl050-8048nt-c01"; + backlight = <&backlight>; + power-supply = <®_lcd_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&codec_osc>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio5>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + wakeup-source; + }; + + camera@3c { + compatible = "ovti,ov5645"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5645>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-frequency = <24000000>; + vdddo-supply = <®_1p8v>; + vdda-supply = <®_2p8v>; + vddd-supply = <®_1p5v>; + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + + port { + ov5645_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5645_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reset>; + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { /* Bluetooth module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { /* Wifi/BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ov5645: ov5645grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 + >; + }; + + pinctrl_pcie_reset: pciegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_lcd: reglcdgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi new file mode 100644 index 000000000000..36f84f4da6b0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b008 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b008 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi new file mode 100644 index 000000000000..f804ff95a6ad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 FEDEVEL, Inc. + * + * Author: Robert Nelson + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led0: led-usr { + label = "usr"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "fsl,imx6-rex-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-rex-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca9535: gpio-expander@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9535>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-rex { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + /* user led */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; + + pinctrl_pca9535: pca9535grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + /* power enable, high active */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + /* CD */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* WP */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + /* CD */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + /* WP */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 + >; + }; + }; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi new file mode 100644 index 000000000000..68e97180d33e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-user { + label = "debug"; + gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + home { + label = "Home"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + back { + label = "Back"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + program { + label = "Program"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + clocks { + codec_osc: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai>; + audio-asrc = <&asrc>; + audio-codec = <&codec>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx-sabreauto-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + mux-gpios = <&gpio5 4 0>; + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + adv7180: camera@21 { + compatible = "adi,adv7180"; + reg = <0x21>; + powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max7310>; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + max7310_c: gpio@34 { + compatible = "maxim,max7310"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + }; + + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; + + accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mma8451_int>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + bus-width = <8>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, + <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + status = "disabled"; /* pin conflict with WEIM NOR */ + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + fsl,magic-packet; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "disabled"; /* pin conflict with fec */ +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&codec_osc>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio2>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabreauto { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax-intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_max7310: max7310grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_mma8451_int: mma8451intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 + >; + }; + + pinctrl_pwm3: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_gpt_input_capture0: gptinputcapture0grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 + >; + }; + + pinctrl_gpt_input_capture1: gptinputcapture1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor: weimnorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; + ranges = <0 0 0x08000000 0x08000000>; + status = "disabled"; /* pin conflict with SPI NOR */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi new file mode 100644 index 000000000000..12573e1f917c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + */ + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_can_xcvr: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_1p5v: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_1p8v: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + mipi_xclk: mipi_xclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_pwm3"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j15>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov5640: camera@40 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x40>; + clocks = <&mipi_xclk>; + clock-names = "xclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p5v>; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */ + powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */ + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + ov5642: camera@42 { + compatible = "ovti,ov5642"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "xclk"; + reg = <0x42>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + ov5642_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-sabrelite { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* Phy reset */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + >; + }; + + pinctrl_j15: j15grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 + >; + }; + + pinctrl_ov5642: ov5642grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi new file mode 100644 index 000000000000..4fe58764b929 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -0,0 +1,851 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sensors: regulator-sensors { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sensors_reg>; + regulator-name = "sensors-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-asrc = <&asrc>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; + mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-red { + gpios = <&gpio1 2 0>; + default-state = "on"; + }; + }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <®_sensors>; + vddio-supply = <®_sensors>; + }; + + ov5642: camera@3c { + compatible = "ovti,ov5642"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + reg = <0x3c>; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5642_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; + }; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio6>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + }; + + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <®_sensors>; + vddio-supply = <®_sensors>; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; + interrupt-parent = <&gpio3>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_sensors>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-sabresd { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 + >; + }; + + pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 + >; + }; + + pinctrl_ov5642: ov5642grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_sensors_reg: sensorsreggrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; + }; + + gpio_leds { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <&vgen5_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen5_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi new file mode 100644 index 000000000000..02e6d36e85fa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2017 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + label = "Power Button"; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "avic,tm097tdh02", "hannstar,hsd100pxn1"; + backlight = <&panel_bl>; + power-supply = <®_3p3v>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + panel_bl: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <4>; + power-supply = <®_3p3v>; + pwms = <&pwm1 0 10000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + reg = <0>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +/* SD card */ +&usdhc3 { + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd>; + status = "okay"; +}; + +/* eMMC */ +&usdhc4 { + bus-width = <8>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_emmc: emmcgrp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* PHY reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_sd: sdgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + /* CD pin */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi new file mode 100644 index 000000000000..b81799d7076a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +/ { + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <65000>; + touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + status = "okay"; + + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; + reg = <0>; + pinctrl-0 = <&pinctrl_touch>; + pinctrl-names ="default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x000b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x000b1 + /* *no* external pull up */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x40000058 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + /* external pull up */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x10040 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi new file mode 100644 index 000000000000..2731faede1cb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2020 Pengutronix, Ulrich Oelmann + +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + aliases { + can0 = &can1; + can1 = &can2; + mdio-gpio0 = &mdio; + nand = &gpmi; + rtc0 = &i2c_rtc; + rtc1 = &snvs; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, /* 24V */ + <&adc 1>; /* temperature */ + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "D1"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_STATUS; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "D2"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "D3"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mdio: mdio { + compatible = "microchip,mdio-smi0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, + <&gpio1 22 GPIO_ACTIVE_HIGH>; + + switch@0 { + compatible = "microchip,ksz8873"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + interrupt-parent = <&gpio3>; + interrupt = <30 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + reg = <0>; + phy-mode = "internal"; + label = "lan1"; + }; + + ports@1 { + reg = <1>; + phy-mode = "internal"; + label = "lan2"; + }; + + ports@2 { + reg = <2>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + + }; + + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + vin-supply = <®_5v0>; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_24v0: regulator-24v0 { + compatible = "regulator-fixed"; + regulator-name = "24v0"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_stby>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_stby>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; + }; + + reg_tft_vcom: regulator-tft-vcom { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 20000 0>; + regulator-name = "tft_vcom"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + voltage-table = <3600000 26>; + }; + + reg_vcc_mmc: regulator-vcc-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc>; + vin-supply = <®_3v3>; + regulator-name = "mmc_vcc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + }; + + reg_vcc_mmc_io: regulator-vcc-mmc-io { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc_io>; + vin-supply = <®_5v0>; + regulator-name = "mmc_io_supply"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + states = <1800000 0x1>, <3300000 0x0>; + startup-delay-us = <100>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <54000000>; + reg = <0>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + status = "okay"; + + adc: adc@0 { + compatible = "microchip,mcp3002"; + reg = <0>; + vref-supply = <®_3v3>; + spi-max-frequency = <1000000>; + #io-channel-cells = <1>; + }; +}; + +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-supply = <®_3v3>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + i2c_rtc: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <2>; + status = "okay"; +}; + +&pwm3 { + /* used for LCD contrast control */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_5v0>; + disable-over-current; + status = "okay"; +}; + +/* no usbh2 */ +&usbphynop1 { + status = "disabled"; +}; + +/* no usbh3 */ +&usbphynop2 { + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_5v0>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + cap-power-off-card; + full-pwr-cycle; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + mmc-ddr-1_8v; + vmmc-supply = <®_vcc_mmc>; + vqmmc-supply = <®_vcc_mmc_io>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000 + >; + }; + + pinctrl_can1_stby: can1stbygrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + >; + }; + + pinctrl_can2_stby: can2stbygrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1 + /* *no* external pull up */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1 + /* external pull up */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* RMII 50 MHz */ + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58 + /* GPIO for "link active" */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + /* external 10 k pull up */ + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878 + /* external 10 k pull up */ + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1 + MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + /* SoC internal pull up required */ + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + /* SoC internal pull up required */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040 + /* SoC internal pull up required */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040 + >; + }; + + pinctrl_vcc_mmc: vccmmcgrp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58 + >; + }; + + pinctrl_vcc_mmc_io: vccmmciogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi new file mode 100644 index 000000000000..48c9ce051f47 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2021 Pengutronix, Oleksij Rempel + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; + pwms = <&pwm2 0 20000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <17>; + default-brightness-level = <8>; + power-supply = <®_24v0>; + }; + + display { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l2rt"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi new file mode 100644 index 000000000000..234827e554d0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2021 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_solidsense_leds>; + + /* Red/Green LED1 - next to WiFi SMA */ + led-11 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + }; + + led-12 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + /* Red/Green LED2 - next to GPS SMA */ + led-21 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + }; + + led-22 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&audio { + status = "disabled"; +}; + +&ecspi2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>, <&pinctrl_solidsense_hog>; + + solidsense { + pinctrl_solidsense_hog: solidsense-hog { + fsl,pins = < + /* Nordic RESET_N */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x400130b1 + /* Nordic Chip 1 SWDIO - GPIO 125 */ + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x400130b1 + /* Nordic Chip 1 SWDCLK - GPIO 59 */ + /* already claimed in the HB2 hogs */ + /* MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 */ + /* Nordic Chip 2 SWDIO - GPIO 81 */ + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x400130b1 + /* Nordic Chip 2 SWCLK - GPIO 82 */ + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x400130b1 + >; + }; + + pinctrl_solidsense_leds: solidsense-leds { + fsl,pins = < + /* Red LED 1 - GPIO 58 */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x400130b1 + /* Green LED 1 - GPIO 55 */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x400130b1 + /* Red LED 2 - GPIO 57 */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x400130b1 + /* Green LED 2 - GPIO 56 */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x400130b1 + >; + }; + + pinctrl_solidsense_uart2: solidsense-uart2 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_solidsense_uart3: solidsense-uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&sgtl5000 { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_solidsense_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_solidsense_uart3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi new file mode 100644 index 000000000000..b55af61dfeca --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +/ { + clk_brcm: brcm-clock { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_osc>; + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + reg_brcm: brcm-reg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, + <&gpio6 0 GPIO_ACTIVE_LOW>; + clocks = <&clk_brcm>; + clock-names = "ext_clock"; + }; +}; + +&iomuxc { + microsom { + pinctrl_microsom_brcm_bt: microsom-brcm-bt { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 + >; + }; + + pinctrl_microsom_brcm_osc: microsom-brcm-osc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 + >; + }; + + pinctrl_microsom_brcm_reg: microsom-brcm-reg { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 + >; + }; + + pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { + fsl,pins = < + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 + >; + }; + + pinctrl_microsom_uart4: microsom-uart4 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_microsom_usdhc1: microsom-usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + }; +}; + +/* UART4 - Connected to optional BRCM Wifi/BT/FM */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_brcm>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi new file mode 100644 index 000000000000..5f3b8baab20f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&iomuxc { + microsom { + pinctrl_microsom_usdhc3: microsom-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + }; +}; + +/* USDHC3 - eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_usdhc3>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi new file mode 100644 index 000000000000..352ac585ca6b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/ { + nvcc_sd1: regulator-nvcc-sd1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "nvcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + clk_ti_wifi: ti-wifi-clock { + /* This is a hack around the kernel - using "fixed clock" + * results in the "pinctrl" properties being ignored, and + * the clock not being output. Instead, use a gated clock + * and the unrouted WL_XTAL_PU gpio. + */ + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_clk>; + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + pwrseq_ti_wifi: ti-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + clocks = <&clk_ti_wifi>; + clock-names = "ext_clock"; + }; +}; + +&iomuxc { + microsom { + pinctrl_microsom_ti_bt: microsom-ti-bt { + fsl,pins = < + /* BT_EN_SOC */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 + >; + }; + + pinctrl_microsom_ti_clk: microsom-ti-clk { + fsl,pins = < + /* EXT_32K */ + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 + /* WL_XTAL_PU (unrouted) */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 + >; + }; + + pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { + fsl,pins = < + /* WLAN_EN_SOC */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 + >; + }; + + pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { + fsl,pins = < + /* WLAN_IRQ */ + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 + >; + }; + + pinctrl_microsom_uart4: microsom-uart4 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_microsom_usdhc1: microsom-usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + }; +}; + +/* UART4 - Connected to optional TI Wi-Fi/BT/FM */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_uart4>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + clocks = <&clk_ti_wifi>; + clock-names = "ext_clock"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_bt>; + }; +}; + +/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_usdhc1>; + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&pwrseq_ti_wifi>; + cap-power-off-card; + non-removable; + vmmc-supply = <&vcc_3v3>; + /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi new file mode 100644 index 000000000000..ce543e325cd3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2013,2014 Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/ { + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-mode = "rgmii-id"; + + /* + * The PHY seems to require a long-enough reset duration to avoid + * some rare issues where the PHY gets stuck in an inconsistent and + * non-functional state at boot-up. 10ms proved to be fine . + */ + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* + * The PHY can appear at either address 0 or 4 due to the + * configuration (LED) pin not being pulled sufficiently. + */ + ethernet-phy@0 { + reg = <0>; + qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + }; + + ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + }; + + /* + * ADIN1300 (som rev 1.9 or later) is always at address 1. It + * will be enabled automatically by U-Boot if detected. + */ + ethernet-phy@1 { + reg = <1>; + adi,phy-output-clock = "125mhz-free-running"; + status = "disabled"; + }; + }; +}; + +&iomuxc { + microsom { + pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + /* AR8035 reset */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + + /* + * As the RMII pins are also connected to RGMII + * so that an AR8030 can be placed, set these + * to high-z with the same pulls as above. + * Use the GPIO settings to avoid changing the + * input select registers. + */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 + >; + }; + + pinctrl_microsom_uart1: microsom-uart1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_uart1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi new file mode 100644 index 000000000000..344ea935c7da --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include +#include + +/ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + m25p80: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 + /* eCSPI1 SS1 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; + + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; + +&pmic { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vddcore: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + reg_snvs_3v: vsnvs { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen4_1v8: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_1v8_eth: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + disable-wp; + no-sd; + no-sdio; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi new file mode 100644 index 000000000000..aff46f3040c1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include + +&fec { + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_3p3v>; + }; +}; + +&iomuxc { + /* + * This pinmuxing is required for the ERR006687 workaround. Board + * DTS files that enable the FEC controller with + * fsl,err006687-workaround-present must include this group. + */ + pinctrl_enet_fix: enetfixgrp { + fsl,pins = < + /* ENET ping patch */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi new file mode 100644 index 000000000000..a3f6543c3aaa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_3p3v>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi new file mode 100644 index 000000000000..f88da757edda --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi @@ -0,0 +1,479 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + aliases { + ethernet0 = &fec; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds1>; + compatible = "gpio-leds"; + + green-led { + label = "green-led"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + red-led { + label = "red-led"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + n25q064: flash@0 { + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + gpio8: gpio@28 { + compatible = "technologic,ts4900-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + ngpio = <32>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_leds1: leds1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + fsl,wp-controller; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi new file mode 100644 index 000000000000..1e0a041e9f60 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -0,0 +1,594 @@ +/* + * Copyright 2015 Technologic Systems + * Copyright 2017 Savoir-Faire Linux + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds1>; + compatible = "gpio-leds"; + + green-led { + label = "green-led"; + gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + red-led { + label = "red-led"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + yel-led { + label = "yellow-led"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-led { + label = "blue-led"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + en-usb-5v-led { + label = "en-usb-5v"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + sel-dc-usb-led { + label = "sel_dc_usb"; + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can1_3v3: reg_can1_3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_can1_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: en-reg_can2_3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_can2_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator_wlan_vmmc { + compatible = "regulator-fixed"; + regulator-name = "wlan_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + n25q064: flash@0 { + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = < + &gpio5 31 GPIO_ACTIVE_LOW + &gpio7 12 GPIO_ACTIVE_LOW + &gpio5 18 GPIO_ACTIVE_LOW + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + /delete-property/ interrupts; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + m41t00s: rtc@68 { + compatible = "m41t00"; + reg = <0x68>; + }; + + isl12022: rtc@6f { + compatible = "isl,isl12022"; + reg = <0x6f>; + }; + + gpio8: gpio@28 { + compatible = "technologic,ts7970-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <62>; + }; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */ + >; + }; + + pinctrl_ecspi2: ecspi2 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */ + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */ + >; + }; + + pinctrl_enet: enet { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Onboard */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */ + + /* Offboard */ + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */ + + /* Strapping only */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_leds1: leds1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */ + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_wlan_vmmc>; + bus-width = <4>; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + fsl,wp-controller; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi new file mode 100644 index 000000000000..79f2354886b7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi @@ -0,0 +1,251 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_pwr>; + enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + turn-on-delay-ms = <35>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0dh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + backlight = <&backlight>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_out>; + }; + }; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + u-boot,panel-name = "edt,et057090dhu"; + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + u-boot,panel-name = "edt,et0350g0dh6"; + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + u-boot,panel-name = "edt,et0430g0dh6"; + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + u-boot,panel-name = "edt,etm0700g0dh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + CoMTFT { /* same as ET0700 but with inverted pixel clock */ + u-boot,panel-name = "edt,etm0700g0edh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_in>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi new file mode 100644 index 000000000000..2ca2eb37e14f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi @@ -0,0 +1,286 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_lcd0_pwr>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_lcd1_pwr>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + lvds0_panel: lvds0-panel { + compatible = "nlt,nl12880bc20-spwg-24"; + backlight = <&backlight0>; + power-supply = <®_3v3>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + lvds1_panel: lvds1-panel { + compatible = "nlt,nl12880bc20-spwg-24"; + backlight = <&backlight1>; + power-supply = <®_3v3>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&kpp { + status = "disabled"; /* pad conflict with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + display-timings { + hsd100pxn1 { + u-boot,panel-name = "hannstar,hsd100pxn1"; + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + nl12880bc20 { + u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0700 { + u-boot,panel-name = "edt,etm0700g0dh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + u-boot,panel-name = "edt,et057090dhu"; + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + + display-timings { + hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +®_lcd0_pwr { + status = "okay"; +}; + +®_lcd1_pwr { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi new file mode 100644 index 000000000000..99ec7a838f8d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi @@ -0,0 +1,96 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + backlight0 { + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + turn-on-delay-ms = <35>; + power-supply = <®_lcd1_pwr>; + }; + + backlight1 { + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + turn-on-delay-ms = <35>; + power-supply = <®_lcd1_pwr>; + }; + + lcd-panel { + compatible = "edt,et057090dhu"; + pixelclk-active = <0>; + }; + + lvds0-panel { + compatible = "edt,etml1010g0dka"; + pixelclk-active = <0>; + }; + + lvds1-panel { + compatible = "edt,etml1010g0dka"; + pixelclk-active = <0>; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + /* + * The backup voltage of the module internal RTC is not wired + * by default on the MB7, so disable that RTC chip. + */ + status = "disabled"; +}; + +&i2c3 { + rtc: rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +®_lcd0_pwr { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi new file mode 100644 index 000000000000..e2fe337f7d9e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -0,0 +1,792 @@ +/* + * Copyright 2014-2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + can0 = &can2; + can1 = &can1; + ethernet0 = &fec; + lcdif-23bit-pins-a = &pinctrl_disp0_1; + lcdif-24bit-pins-a = &pinctrl_disp0_2; + pwm0 = &pwm1; + pwm1 = &pwm2; + reg-can-xcvr = ®_can_xcvr; + stk5led = &user_led; + usbotg = &usbotg; + sdhc0 = &usdhc1; + sdhc1 = &usdhc2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; /* will be filled by U-Boot */ + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + mclk: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led: led-user { + label = "Heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_led>; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3_etn: regulator-3v3-etn { + compatible = "regulator-fixed"; + regulator-name = "3V3_ETN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy_power>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + }; + + reg_lcd0_pwr: regulator-lcd0-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_lcd1_pwr: regulator-lcd1-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_pwr>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "karo,imx6qdl-tx6-sgtl5000", + "simple-audio-card"; + simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCSEL(4) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = < + &gpio2 30 GPIO_ACTIVE_HIGH + &gpio3 19 GPIO_ACTIVE_HIGH + >; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <10>; + phy-handle = <&etnphy>; + phy-supply = <®_3v3_etn>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + etnphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy_int>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + clock-frequency = <400000>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007>; + interrupt-parent = <&gpio3>; + interrupts = <26 0>; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <660>; + wakeup-source; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ + >; + }; + + pinctrl_disp0_1: disp0grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_disp0_2: disp0grp-2 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 + MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + >; + }; + + pinctrl_enet_mdio: enet-mdiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + >; + }; + + pinctrl_etnphy_int: etnphy-intgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ + >; + }; + + pinctrl_etnphy_power: etnphy-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ + >; + }; + + pinctrl_etnphy_rst: etnphy-rstgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan_xcvr: flexcan-xcvrgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 + MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 + MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 + MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 + MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 + MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 + MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 + >; + }; + + pinctrl_lcd0_pwr: lcd0-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ + >; + }; + + pinctrl_lcd1_pwr: lcd-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart1_rtscts: uart1_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_rtscts: uart2_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3_rtscts: uart3_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ + >; + }; + + pinctrl_user_led: user-ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ + >; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + /* sample keymap */ + /* row/col 0,1 are mapped to KPP row/col 6,7 */ + linux,keymap = < + MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ + MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ + MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ + MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ + MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ + MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ + MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ + MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ + MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ + MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ + MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ + >; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi new file mode 100644 index 000000000000..93a8123da27d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +#include + +/ { + aliases { + backlight = &backlight; + panelchan = &panelchan; + panel7 = &panel7; + touchscreenp7 = &touchscreenp7; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio1 4 0>; + default-on; + status = "disabled"; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio2 4 0>; + pinctrl-0 = <&pinctrl_power_off>; + pinctrl-names = "default"; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + panel7: panel7 { + /* + * in reality it is a -20t (parallel) model, + * but with LVDS bridge chip attached, + * so it is equivalent to -19t model in drive + * characteristics + */ + compatible = "urt,umsh-8596md-19t"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <®_panel>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_h1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ + gpio = <&gpio7 12 0>; + }; + + reg_panel: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd_panel"; + enable-active-high; + gpio = <&gpio1 2 0>; + }; + }; + + sound { + compatible = "fsl,imx6q-udoo-ac97", + "fsl,imx-audio-ac97"; + model = "fsl,imx6q-udoo-ac97"; + audio-cpu = <&ssi1>; + audio-routing = + "RX", "Mic Jack", + "Headphone Jack", "TX"; + mux-int-port = <1>; + mux-ext-port = <6>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreenp7: touchscreenp7@55 { + compatible = "sitronix,st1232"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreenp7>; + reg = <0x55>; + interrupt-parent = <&gpio1>; + interrupts = <13 8>; + gpios = <&gpio1 15 0>; + status = "disabled"; + }; +}; + +&iomuxc { + imx6q-udoo { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 + >; + }; + + pinctrl_power_off: poweroffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 + >; + }; + + pinctrl_touchscreenp7: touchscreenp7grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh: usbhgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_usbotg: usbotg { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_ac97_running: ac97running { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ac97_warm_reset: ac97warmreset { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ac97_reset: ac97reset { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + panelchan: lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh>; + vbus-supply = <®_usb_h1_vbus>; + clocks = <&clks IMX6QDL_CLK_CKO>; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&audmux { + status = "okay"; +}; + +&ssi1 { + cell-index = <0>; + fsl,mode = "ac97-slave"; + pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; + pinctrl-0 = <&pinctrl_ac97_running>; + pinctrl-1 = <&pinctrl_ac97_reset>; + pinctrl-2 = <&pinctrl_ac97_warm_reset>; + ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi new file mode 100644 index 000000000000..200559d7158d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Support for Variscite DART-MX6 Module + * + * Copyright 2017 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(2)) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; + ddc-i2c-bus = <&i2c1>; + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + tlv320aic3106: codec@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + #sound-dai-cells = <0>; + DRVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + ai3x-ocmv = <0>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + /* Audio Clock */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_bt: bt { + fsl,pins = < + /* Bluetooth enable */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1 + /* Bluetooth Slow Clock */ + MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + /* SPI1 CS0 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + /* SPI1 CS1 */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC INT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* WL_EN */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071 + /* WL_IRQ */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + fsl,tx-swing-full = <103>; + fsl,tx-swing-low = <103>; + reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbh1 { + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi new file mode 100644 index 000000000000..73f381e14467 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Protonic Holland + */ + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power-button { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi new file mode 100644 index 000000000000..96e4f4b0b248 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +#include +#include +#include +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + backlight_led: backlight-led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + + /* only for backwards compatibility with old HW */ + backlight_isb: backlight-isb { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 8 48 255>; + num-interpolated-steps = <5>; + default-brightness-level = <0>; + power-supply = <®_3v3>; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = ; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "debug1"; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + + led-2 { + label = "power_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-3 { + label = "isb_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + bitclock-master; + frame-master; + }; + }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&gpio2 { + gpio-line-names = + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", + "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; +}; + +&gpio7 { + gpio-line-names = + "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", + "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", + "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", + "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + video-decoder@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 + >; + }; + + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* CAM1_MIRROR */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* CAM2_MIRROR */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 + /* CAM_nDETECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* ISB_IN1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + /* ISB_nIN2 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + /* WARN_LIGHT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 + /* ON2_FB */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 + /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 + /* YACO_nRESET */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + /* FORCE_ON1 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + + /* New in HW revision 1 */ + /* ON1_FB */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 + /* DIP1_FB */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG0 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + /* DEBUG1 */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* POWER_LED */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + /* ISB_LED */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* YaCO Touchscreen UART */ + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi new file mode 100644 index 000000000000..e781a45785ed --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam + +#include "imx6qdl-wandboard.dtsi" + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi new file mode 100644 index 000000000000..3874e74703f0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam + +#include "imx6qdl-wandboard.dtsi" + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi new file mode 100644 index 000000000000..9b8c9c23ab54 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam + +#include "imx6qdl-wandboard.dtsi" + +/ { + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + regulator-name = "ETH_PHY"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&fec { + phy-supply = <®_eth_phy>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi new file mode 100644 index 000000000000..e4f63423d8ee --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + sound { + compatible = "fsl,imx6-wandboard-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-wandboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + codec: sgtl5000@a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mclk>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + lrclk-strength = <3>; + }; + + camera@3c { + compatible = "ovti,ov5645"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5645>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-frequency = <24000000>; + vdddo-supply = <®_1p8v>; + vdda-supply = <®_2p8v>; + vddd-supply = <®_1p5v>; + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + + port { + ov5645_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6qdl-wandboard { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_ov5645: ov5645grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5645_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi new file mode 100644 index 000000000000..9ff183e4e069 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi @@ -0,0 +1,1142 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2016-2017 Zodiac Inflight Innovations + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + mdio-gpio0 = &mdio1; + rtc0 = &ds1341; + }; + + mdio1: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + gpios = <&gpio6 5 GPIO_ACTIVE_HIGH + &gpio6 4 GPIO_ACTIVE_HIGH>; + + phy: ethernet-phy@0 { + pinctrl-0 = <&pinctrl_rmii_phy_irq>; + pinctrl-names = "default"; + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_28p0v: regulator-28p0v { + compatible = "regulator-fixed"; + regulator-name = "28V_IN"; + regulator-min-microvolt = <28000000>; + regulator-max-microvolt = <28000000>; + regulator-always-on; + }; + + reg_12p0v: regulator-12p0v { + compatible = "regulator-fixed"; + vin-supply = <®_28p0v>; + regulator-name = "12V_MAIN"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + vin-supply = <®_12p0v>; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_3p3v_pmic: regulator-3p3v-pmic { + compatible = "regulator-fixed"; + vin-supply = <®_12p0v>; + regulator-name = "PMIC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + vin-supply = <®_3p3v_pmic>; + regulator-name = "GEN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3p3v_sd: regulator-3p3v-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_3p3v_sd>; + vin-supply = <®_3p3v>; + regulator-name = "3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1000>; + enable-active-high; + regulator-always-on; + }; + + reg_3p3v_display: regulator-3p3v-display { + compatible = "regulator-fixed"; + vin-supply = <®_12p0v>; + regulator-name = "3V3_DISPLAY"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3p3v_ssd: regulator-3p3v-ssd { + compatible = "regulator-fixed"; + vin-supply = <®_12p0v>; + regulator-name = "3V3_SSD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "front"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound1_codec>; + simple-audio-card,frame-master = <&sound1_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPA1 HPLEFT", + "Headphone Jack", "HPA1 HPRIGHT", + "HPA1 LEFTIN", "HPL", + "HPA1 RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa1>; + + sound1_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound1_codec: simple-audio-card,codec { + sound-dai = <&codec1>; + clocks = <&cs2000>; + }; + }; + + sound2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "periph"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound2_codec>; + simple-audio-card,frame-master = <&sound2_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPA1 HPLEFT", + "Headphone Jack", "HPA1 HPRIGHT", + "HPA1 LEFTIN", "HPL", + "HPA1 RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa2>; + + sound2_cpu: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + sound2_codec: simple-audio-card,codec { + sound-dai = <&codec2>; + clocks = <&cs2000>; + }; + }; + + panel { + power-supply = <®_3p3v_display>; + backlight = <&sp_backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + disp0: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0>; + status = "disabled"; + + port@0 { + reg = <0>; + + disp0_in_0: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + disp0_out: endpoint { + remote-endpoint = <&tc358767_in>; + }; + }; + }; + + cs2000_ref: cs2000-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + cs2000_in_dummy: cs2000-in-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + edp_refclk: edp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&cpu0 { + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1300000 + 996000 1275000 + 852000 1275000 + 792000 1200000 + 396000 1200000 + >; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +&ldb { + lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + sp_backlight: backlight { + compatible = "zii,rave-sp-backlight"; + }; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "st,m25p128", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3_hog>; + + usb-emulation-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "usb-emulation"; + }; + + usb-mode1-hog { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-mode1"; + }; + + usb-pwr-hog { + gpio-hog; + gpios = <22 GPIO_ACTIVE_LOW>; + output-high; + line-name = "usb-pwr-ctrl-en-n"; + }; + + usb-mode2-hog { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-mode2"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + codec2: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec2>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + accel@1c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "fsl,mma8451"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupt-names = "INT2"; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; + }; + + hpa2: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa2>; + reg = <0x60>; + power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + sound-name-prefix = "HPA1"; + }; + + edp-bridge@68 { + compatible = "toshiba,tc358767"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc358767>; + reg = <0x68>; + shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + clock-names = "ref"; + clocks = <&edp_refclk>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + tc358767_in: endpoint { + remote-endpoint = <&disp0_out>; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pfuze100_irq>; + reg = <0x08>; + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; + + temp-sense@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + cs2000: clkgen@4e { + compatible = "cirrus,cs2000-cp"; + reg = <0x4e>; + #clock-cells = <0>; + clock-names = "clk_in", "ref_clk"; + clocks = <&cs2000_in_dummy>, <&cs2000_ref>; + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24000000>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + + ds1341: rtc@68 { + compatible = "dallas,ds1341"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + codec1: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec1>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <®_5p0v_main>; + vio-supply = <®_3p3v>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <2>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + syna,sensor-type = <1>; + syna,delta-x-threshold = <5>; + syna,delta-y-threshold = <10>; + }; + + rmi4-f12@12 { + reg = <0x12>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + syna,sensor-type = <1>; + }; + }; + + touchscreen@2a { + compatible = "eeti,exc3000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + reg = <0x2a>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + status = "disabled"; + }; + + reg_5p0v_user_usb: charger@32 { + compatible = "microchip,ucs1002"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ucs1002_pins>; + reg = <0x32>; + interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>, + <&gpio3 21 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "a_det", "alert"; + }; + + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa1>; + reg = <0x60>; + power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + sound-name-prefix = "HPA1"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&disp0_in_0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + host@0 { + reg = <0 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + i210: i210@0 { + reg = <0 0 0 0 0>; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_3p3v_sd>; + vqmmc-supply = <®_3p3v>; + no-1-8-v; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_3p3v_sd>; + vqmmc-supply = <®_3p3v>; + no-1-8-v; + no-sdio; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-1-8-v; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&sata { + target-supply = <®_3p3v_ssd>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <&phy>; + phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + phy-supply = <®_3p3v>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + pinctrl-0 = <&pinctrl_switch_irq>; + pinctrl-names = "default"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "gigabit_proc"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "netaux"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + phy-mode = "rev-rmii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@3 { + reg = <3>; + label = "netright"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "netleft"; + phy-handle = <&switchphy4>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + interrupt-parent = <&switch>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy1: switchphy@1 { + reg = <1>; + interrupt-parent = <&switch>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy2: switchphy@2 { + reg = <2>; + interrupt-parent = <&switch>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy3: switchphy@3 { + reg = <3>; + interrupt-parent = <&switch>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy4: switchphy@4 { + reg = <4>; + interrupt-parent = <&switch>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; +}; + +&usbh1 { + vbus-supply = <®_5p0v_main>; + disable-over-current; + maximum-speed = "full-speed"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v_user_usb>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCSEL(2) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCSEL(4) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + mux-aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&iomuxc { + pinctrl_accel: accelgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_codec1: dac1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038 + >; + }; + + pinctrl_codec2: dac2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038 + >; + }; + + pinctrl_disp0: disp0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + >; + }; + + pinctrl_gpio3_hog: gpio3hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b811 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b811 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b811 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b811 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b811 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b811 + >; + }; + + pinctrl_mdio1: bitbangmdiogrp { + fsl,pins = < + /* Bitbang MDIO for DEB Switch */ + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038 + >; + }; + + pinctrl_pfuze100_irq: pfuze100grp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000 + >; + }; + + pinctrl_reg_3p3v_sd: mmcsupply1grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858 + >; + }; + + pinctrl_rmii_phy_irq: phygrp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000 + >; + }; + + pinctrl_switch_irq: switchgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000 + >; + }; + + pinctrl_tc358767: tc358767grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10 + >; + }; + + pinctrl_tpa1: tpa6130-1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038 + >; + }; + + pinctrl_tpa2: tpa6130-2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_ucs1002_pins: ucs1002grp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040 + + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi new file mode 100644 index 000000000000..bda182edc589 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -0,0 +1,1393 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + can0 = &can1; + can1 = &can2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + ipu0 = &ipu1; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usb0 = &usbotg; + usb1 = &usbh1; + usb2 = &usbh2; + usb3 = &usbh3; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + clocks { + ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@1 { + reg = <1>; + + lvds0_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds1_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds1>; + }; + }; + + port@1 { + reg = <1>; + + lvds1_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds1>; + }; + }; + }; + }; + + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + dma_apbh: dma-controller@110000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x00110000 0x2000>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6QDL_CLK_APBH_DMA>; + }; + + gpmi: nand-controller@112000 { + compatible = "fsl,imx6q-gpmi-nand"; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX6QDL_CLK_GPMI_IO>, + <&clks IMX6QDL_CLK_GPMI_APB>, + <&clks IMX6QDL_CLK_GPMI_BCH>, + <&clks IMX6QDL_CLK_GPMI_BCH_APB>, + <&clks IMX6QDL_CLK_PER1_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + hdmi: hdmi@120000 { + reg = <0x00120000 0x9000>; + interrupts = <0 115 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HDMI_ISFR>; + clock-names = "iahb", "isfr"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_hdmi>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_hdmi>; + }; + }; + }; + }; + + gpu_3d: gpu@130000 { + compatible = "vivante,gc"; + reg = <0x00130000 0x4000>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "bus", "core", "shader"; + power-domains = <&pd_pu>; + #cooling-cells = <2>; + }; + + gpu_2d: gpu@134000 { + compatible = "vivante,gc"; + reg = <0x00134000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + #cooling-cells = <2>; + }; + + timer@a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + interrupt-parent = <&intc>; + clocks = <&clks IMX6QDL_CLK_TWD>; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + L2: cache-controller@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + arm,shared-override; + }; + + pcie: pcie@1ffc000 { + compatible = "fsl,imx6q-pcie"; + reg = <0x01ffc000 0x04000>, + <0x01f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, + <&clks IMX6QDL_CLK_LVDS1_GATE>, + <&clks IMX6QDL_CLK_PCIE_REF_125M>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + status = "disabled"; + }; + + aips1: bus@2000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, + <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, + <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ECSPI1>, + <&clks IMX6QDL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ECSPI2>, + <&clks IMX6QDL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ECSPI3>, + <&clks IMX6QDL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ECSPI4>, + <&clks IMX6QDL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + esai: esai@2024000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx35-esai"; + reg = <0x02024000 0x4000>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, + <&clks IMX6QDL_CLK_ESAI_MEM>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>, + <&clks IMX6QDL_CLK_ESAI_IPG>, + <&clks IMX6QDL_CLK_SPBA>; + clock-names = "core", "mem", "extal", "fsys", "spba"; + dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ssi1: ssi@2028000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, + <&clks IMX6QDL_CLK_SSI1>; + clock-names = "ipg", "baud"; + dmas = <&sdma 37 1 0>, + <&sdma 38 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi2: ssi@202c000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, + <&clks IMX6QDL_CLK_SSI2>; + clock-names = "ipg", "baud"; + dmas = <&sdma 41 1 0>, + <&sdma 42 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi3: ssi@2030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, + <&clks IMX6QDL_CLK_SSI3>; + clock-names = "ipg", "baud"; + dmas = <&sdma 45 1 0>, + <&sdma 46 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + asrc: asrc@2034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, + <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; + + spba-bus@203c000 { + reg = <0x0203c000 0x4000>; + }; + }; + + vpu: vpu@2040000 { + compatible = "cnm,coda960"; + reg = <0x02040000 0x3c000>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bit", "jpeg"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; + clock-names = "per", "ahb"; + power-domains = <&pd_pu>; + resets = <&src 1>; + iram = <&ocram>; + }; + + aipstz@207c000 { /* AIPSTZ1 */ + reg = <0x0207c000 0x4000>; + }; + + pwm1: pwm@2080000 { + #pwm-cells = <3>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm2: pwm@2084000 { + #pwm-cells = <3>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm3: pwm@2088000 { + #pwm-cells = <3>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm4: pwm@208c000 { + #pwm-cells = <3>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_PWM4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2090000 { + compatible = "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, + <&clks IMX6QDL_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x34 28>; + status = "disabled"; + }; + + can2: can@2094000 { + compatible = "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, + <&clks IMX6QDL_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x34 29>; + status = "disabled"; + }; + + gpt: timer@2098000 { + compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPT_IPG>, + <&clks IMX6QDL_CLK_GPT_IPG_PER>, + <&clks IMX6QDL_CLK_GPT_3M>; + clock-names = "ipg", "per", "osc_per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, + <0 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, + <0 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, + <0 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, + <0 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@20b0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, + <0 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@20b4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020b4000 0x4000>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, + <0 79 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + + reg_vdd1p1: regulator-1p1 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; + }; + + reg_vdd3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_vdd2p5: regulator-2p5 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2100000>; + anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddarm"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_pu: regulator-vddpu { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-enable-ramp-delay = <380>; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; + }; + }; + + usbphy1: usbphy@20c9000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@20ca000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBPHY2>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + status = "disabled"; + }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6q-snvs-lpgpr"; + }; + }; + + epit1: epit@20d0000 { /* EPIT1 */ + reg = <0x020d0000 0x4000>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + epit2: epit@20d4000 { /* EPIT2 */ + reg = <0x020d4000 0x4000>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6q-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, + <0 96 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@20dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + clocks = <&clks IMX6QDL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + }; + }; + }; + + gpr: iomuxc-gpr@20e0000 { + compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; + reg = <0x20e0000 0x38>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + }; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; + reg = <0x20e0000 0x4000>; + }; + + dcic1: dcic@20e4000 { + reg = <0x020e4000 0x4000>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcic2: dcic@20e8000 { + reg = <0x020e8000 0x4000>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>, + <&clks IMX6QDL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + }; + + aips2: bus@2100000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + crypto: crypto@2100000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2100000 0x10000>; + ranges = <0 0x2100000 0x10000>; + clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, + <&clks IMX6QDL_CLK_CAAM_ACLK>, + <&clks IMX6QDL_CLK_CAAM_IPG>, + <&clks IMX6QDL_CLK_EIM_SLOW>; + clock-names = "mem", "aclk", "ipg", "emi_slow"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + aipstz@217c000 { /* AIPSTZ2 */ + reg = <0x0217c000 0x4000>; + }; + + usbotg: usb@2184000 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbh1: usb@2184200 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + dr_mode = "host"; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbh2: usb@2184400 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; + phy_type = "hsic"; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbh3: usb@2184600 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184600 0x200>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop2>; + phy_type = "hsic"; + fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + }; + + fec: ethernet@2188000 { + compatible = "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, + <0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>, + <&clks IMX6QDL_CLK_ENET_REF_SEL>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + fsl,stop-mode = <&gpr 0x34 27>; + nvmem-cells = <&fec_mac_addr>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + }; + + mlb@218c000 { + reg = <0x0218c000 0x4000>; + interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, + <0 117 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USDHC1>, + <&clks IMX6QDL_CLK_USDHC1>, + <&clks IMX6QDL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USDHC2>, + <&clks IMX6QDL_CLK_USDHC2>, + <&clks IMX6QDL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USDHC3>, + <&clks IMX6QDL_CLK_USDHC3>, + <&clks IMX6QDL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc4: mmc@219c000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USDHC4>, + <&clks IMX6QDL_CLK_USDHC4>, + <&clks IMX6QDL_CLK_USDHC4>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_I2C3>; + status = "disabled"; + }; + + romcp@21ac000 { + reg = <0x021ac000 0x4000>; + }; + + mmdc0: memory-controller@21b0000 { /* MMDC0 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; + }; + + mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b4000 0x4000>; + status = "disabled"; + }; + + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: efuse@21bc000 { + compatible = "fsl,imx6q-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6QDL_CLK_IIM>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + + fec_mac_addr: mac-addr@88 { + reg = <0x88 6>; + }; + }; + + tzasc@21d0000 { /* TZASC1 */ + reg = <0x021d0000 0x4000>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + }; + + tzasc@21d4000 { /* TZASC2 */ + reg = <0x021d4000 0x4000>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + mipi_csi: mipi@21dc000 { + compatible = "fsl,imx6-mipi-csi2"; + reg = <0x021dc000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 100 0x04>, <0 101 0x04>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_VIDEO_27M>, + <&clks IMX6QDL_CLK_EIM_PODF>; + clock-names = "dphy", "ref", "pix"; + status = "disabled"; + }; + + mipi_dsi: mipi@21e0000 { + reg = <0x021e0000 0x4000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + }; + + vdoa@21e4000 { + compatible = "fsl,imx6q-vdoa"; + reg = <0x021e4000 0x4000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; + }; + + uart2: serial@21e8000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@21ec000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@21f0000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_UART_IPG>, + <&clks IMX6QDL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + ipu1: ipu@2400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ipu"; + reg = <0x02400000 0x400000>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, + <&clks IMX6QDL_CLK_IPU1_DI1>; + clock-names = "bus", "di0", "di1"; + resets = <&src 2>; + + ipu1_csi0: port@0 { + reg = <0>; + + ipu1_csi0_from_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; + }; + }; + + ipu1_csi1: port@1 { + reg = <1>; + }; + + ipu1_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu1_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu1_di0_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_mux_0>; + }; + + ipu1_di0_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_mux_0>; + }; + + ipu1_di0_lvds0: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds0_mux_0>; + }; + + ipu1_di0_lvds1: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds1_mux_0>; + }; + }; + + ipu1_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu1_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu1_di1_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_mux_1>; + }; + + ipu1_di1_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_mux_1>; + }; + + ipu1_di1_lvds0: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds0_mux_1>; + }; + + ipu1_di1_lvds1: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds1_mux_1>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts new file mode 100644 index 000000000000..eee2e09d6e94 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2015-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ +/dts-v1/; + +#include +#include "imx6qp-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6QP on MBa6x"; + compatible = "tq,imx6qp-mba6x-b", "tq,mba6b", + "tq,imx6qp-tqma6qp-b", "fsl,imx6qp"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts new file mode 100644 index 000000000000..741d1ed338ca --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016 Boundary Devices, Inc. + */ + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; + compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; +}; + +&pcie { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts new file mode 100644 index 000000000000..1593ac86b2a4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017 Boundary Devices, Inc. + */ + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_SOM2 Board"; + compatible = "boundary,imx6qp-nitrogen6_som2", "fsl,imx6qp"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts new file mode 100644 index 000000000000..a18266598d39 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Enrico Scholz + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; + compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6qp"; + + chosen { + stdout-path = &uart2; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&m25p80 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts new file mode 100644 index 000000000000..ae00d538a4df --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2018 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include "imx6qp.dtsi" + +/ { + model = "Protonic WD3 board"; + compatible = "prt,prtwd3", "fsl,imx6qp"; + + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_mcp251xfd: clock-mcp251xfd { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH>; + + /* Microchip KSZ8081 */ + usbeth_phy: ethernet-phy@3 { + reg = <0x3>; + + interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <1000>; + clocks = <&clock_ksz8081>; + clock-names = "rmii-ref"; + micrel,led-mode = <0>; + }; + + tja1102_phy0: ethernet-phy@4 { + reg = <0x4>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "usb"; + phy-handle = <&usbeth_phy>; + phy-mode = "rmii"; + }; + + port@1 { + reg = <1>; + label = "t1slave"; + phy-handle = <&tja1102_phy1>; + phy-mode = "rmii"; + }; + + port@2 { + reg = <2>; + label = "t1master"; + phy-handle = <&tja1102_phy0>; + phy-mode = "rmii"; + + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp251xfd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + reg = <0>; + clocks = <&clock_mcp251xfd>; + spi-max-frequency = <10000000>; + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>; + assigned-clock-rates = <125000000>; + status = "okay"; + + phy-mode = "rgmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031 */ + rgmii_phy: ethernet-phy@2 { + reg = <2>; + + interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", + "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "", "", "", "", "", "", "", + "", "", "ECSPI2_SS0", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", + "", "", "", "", "", "", "", "", + "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "SW_RESET", "", "", + "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", + "PHY0_INT", "", "", "", + "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", + "", "", + "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", + "DISP0_EN", "CAM_GPIO0"; +}; + +&gpio6 { + gpio-line-names = + "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", + "CAM_LOCK", "", "POWER_TG", + "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", + "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", + "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* VIN */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* VBUS */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* ICHG */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + /* CAN2_nINT */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Configure clock provider for RGMII ref clock */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + /* Configure clock consumer for RGMII ref clock */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + + /* SJA1105Q switch reset */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 + + /* phy3/rgmii_phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 + /* phy3/rgmii_phy int */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + /* phy0/usbeth_phy reset */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 + /* phy0/usbeth_phy int */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + + /* phy12/tja1102_phy0 reset */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 + /* phy12/tja1102_phy0 int */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 + /* phy12/tja1102_phy0 enable. Set 100K pull-up */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts new file mode 100644 index 000000000000..2bb3bfb18ec3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2016 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6qdl-sabreauto.dtsi" + +/ { + model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; + compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; +}; + +&i2c2 { + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + imx6qdl-sabreauto { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + }; +}; + +&pcie { + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&vgen3_reg { + regulator-always-on; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts new file mode 100644 index 000000000000..f69eec18d865 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2016 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6qdl-sabresd.dtsi" + +/ { + model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; + compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; +}; + +®_arm { + vin-supply = <&sw2_reg>; +}; + +&iomuxc { + imx6qdl-sabresd { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; + +&vgen3_reg { + regulator-always-on; +}; + +&pcie { + status = "okay"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi new file mode 100644 index 000000000000..bb6ff7c64b27 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + */ + +#include "imx6q.dtsi" +#include "imx6qp.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts new file mode 100644 index 000000000000..92b38e6699aa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp-tx6qp-8037.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts new file mode 100644 index 000000000000..ffc0f2ee11d2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6QP-8037 Module"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts new file mode 100644 index 000000000000..07ad70718aec --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp-tx6qp-8137.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts new file mode 100644 index 000000000000..dd494d587014 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts @@ -0,0 +1,90 @@ +/* + * Copyright 2017 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" + +/ { + model = "Ka-Ro electronics TX6QP-8137 Module"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts new file mode 100644 index 000000000000..49ff145fffe5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" + +/ { + model = "Kverneland UT1P Board"; + compatible = "kvg,vicutp", "fsl,imx6qp"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts new file mode 100644 index 000000000000..08d8b78a2096 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 QuadPlus Board revD1"; + compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts new file mode 100644 index 000000000000..afaf4a6759d4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux+ i.MX6QuadPlus board"; + compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_pu { + regulator-always-on; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts new file mode 100644 index 000000000000..4a961a33bf2d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Pegasus+ i.MX6QuadPlus board"; + compatible = "ysoft,imx6qp-yapp4-pegasus-plus", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_pu { + regulator-always-on; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts new file mode 100644 index 000000000000..57de447c4609 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2016-2017 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6qdl-zii-rdu2.dtsi" + +/ { + model = "ZII RDU2+ Board"; + compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; +}; + +&gpu_3d { + assigned-clocks = <&clks IMX6QDL_CLK_GPU3D_SHADER_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi new file mode 100644 index 000000000000..fc164991d2ae --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2016 Freescale Semiconductor, Inc. + +#include "imx6q.dtsi" + +/ { + soc { + ocram2: sram@940000 { + compatible = "mmio-sram"; + reg = <0x00940000 0x20000>; + ranges = <0 0x00940000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocram3: sram@960000 { + compatible = "mmio-sram"; + reg = <0x00960000 0x20000>; + ranges = <0 0x00960000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + bus@2100000 { + pre1: pre@21c8000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c8000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE0>; + clock-names = "axi"; + fsl,iram = <&ocram2>; + }; + + pre2: pre@21c9000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE1>; + clock-names = "axi"; + fsl,iram = <&ocram2>; + }; + + pre3: pre@21ca000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE2>; + clock-names = "axi"; + fsl,iram = <&ocram3>; + }; + + pre4: pre@21cb000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021cb000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE3>; + clock-names = "axi"; + fsl,iram = <&ocram3>; + }; + + prg1: prg@21cc000 { + compatible = "fsl,imx6qp-prg"; + reg = <0x021cc000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG0_APB>, + <&clks IMX6QDL_CLK_PRG0_AXI>; + clock-names = "ipg", "axi"; + fsl,pres = <&pre1>, <&pre2>, <&pre3>; + }; + + prg2: prg@21cd000 { + compatible = "fsl,imx6qp-prg"; + reg = <0x021cd000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG1_APB>, + <&clks IMX6QDL_CLK_PRG1_AXI>; + clock-names = "ipg", "axi"; + fsl,pres = <&pre4>, <&pre2>, <&pre3>; + }; + }; + }; +}; + +&fec { + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, + <0 119 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpc { + compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; +}; + +&ipu1 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + fsl,prg = <&prg1>; +}; + +&ipu2 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + fsl,prg = <&prg2>; +}; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", "di2_sel", "di3_sel", + "di0", "di1"; +}; + +&mmdc0 { + compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; +}; + +&pcie { + compatible = "fsl,imx6qp-pcie"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts b/arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts new file mode 100644 index 000000000000..4077b607c29e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 + * DHCOM PCB number: 493-400 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +/* + * The kernel only distinguishes between i.MX6 Quad and DualLite, + * but the Solo is actually a DualLite with only one CPU. So use + * DualLite for the Solo and disable one CPU node. + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-drc02.dtsi" + +/ { + model = "DH electronics i.MX6S DHCOM on DRC02"; + compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som", + "fsl,imx6dl"; + + cpus { + /delete-node/ cpu@1; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts new file mode 100644 index 000000000000..239bc6dfc584 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts @@ -0,0 +1,658 @@ +// SPDX-License-Identifier: GPL-2.0 +// +//Copyright (C) 2013 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include +#include +#include "imx6sl.dtsi" + +/ { + model = "Freescale i.MX6 SoloLite EVK Board"; + compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + backlight_display: backlight_display { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-user { + label = "debug"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_aud3v: regulator-aud3v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator-aud4v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6sl-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 + MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 + MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 + MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 + MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 + MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 + MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 + MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 + MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 + >; + }; + + pinctrl_fec_sleep: fecgrp-sleep { + fsl,pins = < + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 + MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 + MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 + MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 + MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 + MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 + MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 + MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 + MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 + MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 + MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 + MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 + MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 + MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 + MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 + MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 + MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 + MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 + MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 + MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 + MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 + MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 + MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 + MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 + MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 + MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 + MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 + MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 + MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 + MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 + MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 + MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 + MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 + MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 + MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 + MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 + >; + }; + + pinctrl_pwm1: pwmgrp { + fsl,pins = < + MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_reg_lcd_3v3: reglcd3v3grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ + MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ + MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ + MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ + MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ + MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ + MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ + MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ + >; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +®_vdd1p1 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&sw2_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts new file mode 100644 index 000000000000..657d0f1b6115 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Kobo Aura 2 ebook reader + * + * Name on mainboard is: 37NB-E60QL0+4B1 + * Serials start with: E60QL2 + * + * Copyright 2022 Andreas Kemnade + */ + +/dts-v1/; + +#include +#include +#include +#include "imx6sl.dtsi" + +/ { + model = "Kobo Aura 2"; + compatible = "kobo,aura2", "fsl,imx6sl"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-cover { + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + key-power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-0 { + label = "koboaura2:white:on"; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + color = ; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + lm3630a: backlight@36 { + compatible = "ti,lm3630a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; + reg = <0x36>; + enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0>; + label = "backlight"; + default-brightness = <0>; + max-brightness = <255>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; + + /* eKTF2232 at 0x15 */ + /* FP9928 at 0x48 */ +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; + reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3100000>; + regulator-suspend-min-microvolt = <3100000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + /* IR_3V3 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-always-on; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + /* J4, through-holes */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + /* TP198, next to J4, SMD pads */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + non-removable; + status = "okay"; + + /* internal uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* + * RTL8189F SDIO WiFi + */ +}; + +&usbotg1 { + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h new file mode 100644 index 000000000000..bcf16060ecdc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h @@ -0,0 +1,1073 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX6SL_PINFUNC_H +#define __DTS_IMX6SL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 +#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 +#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 +#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 +#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 +#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 +#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 +#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 +#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 +#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 +#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 +#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 +#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 +#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 +#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 +#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 +#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 +#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 +#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 +#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 +#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 +#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 +#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 +#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 +#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 +#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 +#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 +#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 +#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 +#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 +#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 +#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 +#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 +#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 +#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 +#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 +#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 +#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 +#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 +#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 +#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 +#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 +#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 +#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 +#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 +#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 +#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 +#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 +#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 +#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 +#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 +#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 +#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 +#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 +#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 +#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 +#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 +#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 +#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 +#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 +#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 +#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 +#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 +#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 +#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 +#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 +#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 +#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 +#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 +#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 +#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 +#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 +#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 +#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 +#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 +#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 +#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 +#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 +#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 +#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 +#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 +#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 +#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 +#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 +#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 +#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 +#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 +#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 +#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 +#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 +#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 +#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 +#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 +#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 +#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 +#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 +#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 +#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 +#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 +#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 +#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 +#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 +#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 +#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 +#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 +#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 +#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 +#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 +#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 +#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 +#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 +#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 +#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 +#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 +#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 +#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 +#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 +#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 +#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 +#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 +#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 +#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 +#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 +#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 +#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 +#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 +#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 +#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 +#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 +#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 +#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 +#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 +#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 +#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 +#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 +#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 +#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 +#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 +#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 +#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 +#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 +#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 +#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 +#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 +#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 +#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 +#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 +#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 +#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 +#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 +#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 +#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 +#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 +#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 +#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 +#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 +#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 +#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 +#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 +#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 +#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 +#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 +#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 +#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 +#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 +#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 +#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 +#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 +#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 +#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 +#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 +#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 +#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 +#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 +#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 +#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 +#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 +#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 +#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 +#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 +#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 +#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 +#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 +#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 +#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 +#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 +#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 +#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 +#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 +#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 +#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 +#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 +#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 +#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 +#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 +#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 +#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 +#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 +#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 +#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 +#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 +#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 +#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 +#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 +#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 +#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 +#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 +#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 +#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 +#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 +#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 +#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 +#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 +#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 +#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 +#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 +#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 +#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 +#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 +#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 +#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 +#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 +#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 +#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 +#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 +#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 +#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 +#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 +#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 +#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 +#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 +#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 +#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 +#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 +#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 +#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 +#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 +#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 +#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 +#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 +#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 +#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 +#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 +#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 +#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 +#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 +#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 +#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 +#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 +#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 +#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 +#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 +#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 +#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 +#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 +#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 +#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 +#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 +#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 +#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 +#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 +#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 +#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 +#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 +#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 +#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 +#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 +#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 +#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 +#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 +#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 +#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 +#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 +#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 +#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 +#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 +#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 +#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 +#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 +#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 +#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 +#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 +#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 +#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 +#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 +#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 +#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 +#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 +#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 +#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 +#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 +#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 +#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 +#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 +#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 +#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 +#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 +#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 +#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 +#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 +#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 +#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 +#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 +#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 +#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 +#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 +#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 +#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 +#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 +#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 +#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 +#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 +#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 +#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 +#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 +#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 +#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 +#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 +#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 +#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 +#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 +#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 +#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 +#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 +#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 +#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 +#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 +#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 +#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 +#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 +#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 +#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 +#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 +#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 +#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 +#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 +#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 +#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 +#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 +#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 +#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 +#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 +#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 +#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 +#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 +#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 +#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 +#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 +#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 +#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 +#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 +#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 +#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 +#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 +#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 +#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 +#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 +#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 +#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 +#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 +#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 +#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 +#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 +#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 +#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 +#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 +#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 +#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 +#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 +#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 +#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 +#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 +#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 +#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 +#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 +#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 +#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 +#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 +#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 +#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 +#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 +#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 +#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 +#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 +#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 +#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 +#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 +#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 +#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 +#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 +#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 +#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 +#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 +#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 +#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 +#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 +#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 +#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 +#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 +#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 +#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 +#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 +#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 +#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 +#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 +#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 +#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 +#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 +#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 +#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 +#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 +#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 +#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 +#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 +#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 +#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 +#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 +#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 +#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 +#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 +#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 +#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 +#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 +#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 +#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 +#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 +#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 +#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 +#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 +#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 +#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 +#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 +#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 +#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 +#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 +#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 +#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 +#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 +#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 +#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 +#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 +#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 +#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 +#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 +#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 +#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 +#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 +#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 +#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 +#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 +#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 +#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 +#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 +#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 +#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 +#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 +#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 +#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 +#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 +#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 +#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 +#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 +#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 +#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 +#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 +#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 +#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 +#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 +#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 +#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 +#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 +#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 +#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 +#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 +#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 +#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 +#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 +#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 +#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 +#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 +#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 +#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 +#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 +#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 +#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 +#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 +#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 +#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 +#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 +#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 +#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 +#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 +#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 +#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 +#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 +#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 +#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 +#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 +#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 +#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 +#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 +#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 +#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 +#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 +#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 +#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 +#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 +#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 +#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 +#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 +#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 +#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 +#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 +#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 +#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 +#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 +#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 +#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 +#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 +#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 +#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 +#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 +#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 +#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 +#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 +#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 +#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 +#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 +#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 +#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 +#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 +#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 +#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 +#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 +#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 +#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 +#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 +#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 +#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 +#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 +#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 +#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 +#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 +#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 +#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 +#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 +#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 +#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 +#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 +#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 +#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 +#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 +#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 +#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 +#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 +#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 +#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 +#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 +#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 +#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 +#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 +#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 +#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 +#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 +#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 +#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 +#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 +#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 +#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 +#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 +#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 +#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 +#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 +#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 +#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 +#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 +#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 +#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 +#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 +#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 +#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 +#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 +#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 +#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 +#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 +#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 +#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 +#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 +#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 +#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 +#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 +#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 +#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 +#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 +#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 +#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 +#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 +#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 +#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 + +#endif /* __DTS_IMX6SL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts new file mode 100644 index 000000000000..815119c12bd4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Tolino Shine 2 HD ebook reader + * + * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3 + * Serials start with: E60QF2 + * + * Copyright 2020 Andreas Kemnade + */ + +/dts-v1/; + +#include +#include +#include "imx6sl.dtsi" + +/ { + model = "Tolino Shine 2 HD"; + compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ec 0 50000>; + power-supply = <&backlight_regulator>; + }; + + backlight_regulator: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_power>; + regulator-name = "backlight"; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-cover { + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + key-fl { + label = "Frontlight"; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-home { + label = "Home"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-0 { + label = "tolinoshine2hd:white:on"; + gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + led-1 { + label = "tolinoshine2hd:white:backlightboost"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + ec: embedded-controller@43 { + compatible = "netronix,ntxec"; + reg = <0x43>; + #pwm-cells = <2>; + }; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; + + zforce: touchscreen@50 { + compatible = "neonode,zforce"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zforce>; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ldo1_reg>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + x-size = <1072>; + y-size = <1448>; + }; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; + reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3100000>; + regulator-suspend-min-microvolt = <3100000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + /* IR_3V3 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-always-on; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_backlight_power: backlight-powergrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 + MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059 + MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 + MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 + MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 + MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 + MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 + MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 + MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 + MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 + MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 + MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 + MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 + MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 + MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 + MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 + MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 + MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 + MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 + MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 + MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 + MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 + MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 + MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 + MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 + MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 + MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 + MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059 + >; + }; + + pinctrl_ricoh_gpio: ricoh_gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2grp-sleep { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grp-sleep { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; + + pinctrl_zforce: zforcegrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */ + >; + }; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + /* J4, through-holes */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + /* TP198, next to J4, SMD pads */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + non-removable; + status = "okay"; + + /* internal uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* + * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi + * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi + */ +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts new file mode 100644 index 000000000000..db5d8509935f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Device tree for the Tolino Shine 3 ebook reader + * + * Name on mainboard is: 37NB-E60K00+4A4 + * Serials start with: E60K02 (a number also seen in + * vendor kernel sources) + * + * This mainboard seems to be equipped with different SoCs. + * In the Toline Shine 3 ebook reader it is a i.MX6SL + * + * Copyright 2019 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include +#include "imx6sl.dtsi" +#include "e60k02.dtsi" + +/ { + model = "Tolino Shine 3"; + compatible = "kobo,tolino-shine3", "fsl,imx6sl"; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x10059 /* TP_RST */ + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 + MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 + MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 + MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 + MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 + MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 + MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 + MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 + MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 + MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 + MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 + MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 + MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 + MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 + MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 + MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 + MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 + MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 + MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 + MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 + MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 + MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 + MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 + MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 + MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh_gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2grp-sleep { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grp-sleep { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; +}; + +&lm3630a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +&ricoh619 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; +}; + +&wifi_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts new file mode 100644 index 000000000000..2694fe18a91b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Tolino Vison ebook reader + * + * Name on mainboard is: 37NB-E60Q30+4A3 + * Serials start with: 6032 + * + * Copyright 2023 Andreas Kemnade + */ + +/dts-v1/; + +#include +#include +#include +#include "imx6sl.dtsi" + +/ { + model = "Tolino Vision"; + compatible = "kobo,tolino-vision", "fsl,imx6sl"; + + aliases { + mmc0 = &usdhc4; + mmc1 = &usdhc2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ec 0 50000>; + power-supply = <&backlight_regulator>; + }; + + backlight_regulator: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_power>; + regulator-name = "backlight"; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-cover { + /* magnetic sensor in the corner next to the uSD slot */ + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + key-fl { + label = "Frontlight"; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + /* LED on home button */ + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* LED on power button */ + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + touchscreen@15 { + compatible = "elan,ektf2132"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + power-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio5 6 IRQ_TYPE_EDGE_FALLING>; + }; + + accelerometer@1d { + compatible = "fsl,mma8652"; + reg = <0x1d>; + }; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + ec: embedded-controller@43 { + compatible = "netronix,ntxec"; + reg = <0x43>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ec>; + interrupts-extended = <&gpio5 11 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + }; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + /* J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + /* J9 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + cd-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* removable uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* CyberTan WC121 (BCM43362) SDIO WiFi */ +}; + +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc4>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + pinctrl-3 = <&pinctrl_usdhc4_sleep>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; + + /* internal eMMC */ +}; + +&usbotg1 { + pinctrl-names = "default"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight_power: backlight-powergrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 + >; + }; + + pinctrl_ec: ecgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x17000 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x110B0 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x110B0 + MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x11030 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 + MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x17059 + MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x110B0 + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x1B0B1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x1b0b1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x17059 + MX6SL_PAD_FEC_MDIO__SD4_CLK 0x13059 + MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x17059 + MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x17059 + MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x17059 + MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x17059 + MX6SL_PAD_FEC_MDC__SD4_DATA4 0x17059 + MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x17059 + MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x17059 + MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x17059 + MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x17068 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170b9 + MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130b9 + MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170b9 + MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170b9 + MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170b9 + MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170b9 + MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170b9 + MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170b9 + MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170b9 + MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170f9 + MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130f9 + MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170f9 + MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170f9 + MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170f9 + MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170f9 + MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170f9 + MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170f9 + MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170f9 + MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_sleep: usdhc4-sleepgrp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x100c1 + MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x100c1 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x100c1 + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x100c1 + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x100c1 + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x100c1 + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x100c1 + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x100c1 + MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x100c1 + MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts new file mode 100644 index 000000000000..6bc342035e2b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Device tree for the Tolino Vision 5 ebook reader + * + * Name on mainboard is: 37NB-E70K0M+6A3 + * Serials start with: E70K02 (a number also seen in + * vendor kernel sources) + * + * This mainboard seems to be equipped with different SoCs. + * In the Tolino Vision 5 ebook reader it is a i.MX6SL + * + * Copyright 2021 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include +#include "imx6sl.dtsi" +#include "e70k02.dtsi" + +/ { + model = "Tolino Vision 5"; + compatible = "kobo,tolino-vision5", "fsl,imx6sl"; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x17059 /* TP_INT */ + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x10059 /* TP_RST */ + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x17059 /* HALL_EN */ + MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */ + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 + MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 + MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 + MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 + MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 + MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 + MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 + MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 + MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 + MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 + MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 + MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 + MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 + MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 + MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 + MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 + MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 + MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 + MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 + MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 + MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 + MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x79 + MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x79 + MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x10059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x10059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x10059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x10059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x10059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x10059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x10059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x10059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x10059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x10059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; +}; + +&lm3630a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&ricoh619 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1_sleep>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; +}; + +&wifi_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts new file mode 100644 index 000000000000..9d7c8884892a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts @@ -0,0 +1,234 @@ +/* + * Copyright 2014, 2015 O.S. Systems Software LTDA. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include "imx6sl.dtsi" + +/ { + model = "Revotics WaRP Board"; + compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ + <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ + <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ + <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ + <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + wakeup-source; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; +}; + +&iomuxc { + imx6sl-warp { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 + >; + }; + + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 + MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 + MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 + MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi new file mode 100644 index 000000000000..28111efb19a6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi @@ -0,0 +1,1008 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. + +#include +#include "imx6sl-pinfunc.h" +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + operating-points = + /* kHz uV */ + <996000 1275000>, + <792000 1175000>, + <396000 975000>; + fsl,soc-operating-points = + /* ARM kHz SOC-PU uV */ + <996000 1225000>, + <792000 1175000>, + <396000 1175000>; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + clocks { + ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + L2: cache-controller@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx6sl-spdif", + "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_ECSPI1>, + <&clks IMX6SL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_ECSPI2>, + <&clks IMX6SL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_ECSPI3>, + <&clks IMX6SL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_ECSPI4>, + <&clks IMX6SL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@2018000 { + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@2024000 { + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ssi1: ssi@2028000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sl-ssi", + "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_SSI1_IPG>, + <&clks IMX6SL_CLK_SSI1>; + clock-names = "ipg", "baud"; + dmas = <&sdma 37 1 0>, + <&sdma 38 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi2: ssi@202c000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sl-ssi", + "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_SSI2_IPG>, + <&clks IMX6SL_CLK_SSI2>; + clock-names = "ipg", "baud"; + dmas = <&sdma 41 1 0>, + <&sdma 42 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi3: ssi@2030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sl-ssi", + "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_SSI3_IPG>, + <&clks IMX6SL_CLK_SSI3>; + clock-names = "ipg", "baud"; + dmas = <&sdma 45 1 0>, + <&sdma 46 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + uart3: serial@2034000 { + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@2038000 { + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02038000 0x4000>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_UART>, + <&clks IMX6SL_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + pwm1: pwm@2080000 { + #pwm-cells = <3>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PERCLK>, + <&clks IMX6SL_CLK_PWM1>; + clock-names = "ipg", "per"; + }; + + pwm2: pwm@2084000 { + #pwm-cells = <3>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PERCLK>, + <&clks IMX6SL_CLK_PWM2>; + clock-names = "ipg", "per"; + }; + + pwm3: pwm@2088000 { + #pwm-cells = <3>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PERCLK>, + <&clks IMX6SL_CLK_PWM3>; + clock-names = "ipg", "per"; + }; + + pwm4: pwm@208c000 { + #pwm-cells = <3>; + compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PERCLK>, + <&clks IMX6SL_CLK_PWM4>; + clock-names = "ipg", "per"; + }; + + gpt: timer@2098000 { + compatible = "fsl,imx6sl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_GPT>, + <&clks IMX6SL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, + <0 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, + <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, + <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, + <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, + <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, + <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, + <0 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, + <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, + <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, + <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, + <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, + <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, + <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, + <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, + <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, + <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, + <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, + <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, + <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, + <&iomuxc 31 102 1>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, + <0 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, + <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, + <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, + <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, + <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, + <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, + <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, + <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, + <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, + <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, + <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, + <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, + <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, + <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, + <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, + <0 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, + <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, + <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, + <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, + <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, + <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, + <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, + <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, + <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, + <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, + <&iomuxc 21 161 1>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_IPG>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_IPG>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_IPG>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6sl-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6sl-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + + reg_vdd1p1: regulator-1p1 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; + }; + + reg_vdd3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_vdd2p5: regulator-2p5 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2100000>; + anatop-max-voltage = <2850000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddarm"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_pu: regulator-vddpu { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; + }; + }; + + usbphy1: usbphy@20c9000 { + compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USBPHY1>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@20ca000 { + compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USBPHY2>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + }; + + epit1: epit@20d0000 { + reg = <0x020d0000 0x4000>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + epit2: epit@20d4000 { + reg = <0x020d4000 0x4000>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6sl-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, + <0 96 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@20dc000 { + compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + clocks = <&clks IMX6SL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_GPU2D_PODF>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, + <&clks IMX6SL_CLK_PXP_AXI>; + }; + }; + }; + + gpr: iomuxc-gpr@20e0000 { + compatible = "fsl,imx6sl-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e0000 0x38>; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6sl-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + csi: csi@20e4000 { + reg = <0x020e4000 0x4000>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + spdc: spdc@20e8000 { + reg = <0x020e8000 0x4000>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_SDMA>, + <&clks IMX6SL_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + /* imx6sl reuses imx6q sdma firmware */ + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pxp: pxp@20f0000 { + reg = <0x020f0000 0x4000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + epdc: epdc@20f4000 { + reg = <0x020f4000 0x4000>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + }; + + lcdif: lcdif@20f8000 { + compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + power-domains = <&pd_disp>; + }; + + dcp: crypto@20fc000 { + compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, + <0 100 IRQ_TYPE_LEVEL_HIGH>, + <0 101 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + aips2: bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbh: usb@2184400 { + compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; + phy_type = "hsic"; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks IMX6SL_CLK_USBOH3>; + }; + + fec: ethernet@2188000 { + compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; + reg = <0x02188000 0x4000>; + interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_ENET>, + <&clks IMX6SL_CLK_ENET_REF>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USDHC1>, + <&clks IMX6SL_CLK_USDHC1>, + <&clks IMX6SL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USDHC2>, + <&clks IMX6SL_CLK_USDHC2>, + <&clks IMX6SL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USDHC3>, + <&clks IMX6SL_CLK_USDHC3>, + <&clks IMX6SL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc4: mmc@219c000 { + compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_USDHC4>, + <&clks IMX6SL_CLK_USDHC4>, + <&clks IMX6SL_CLK_USDHC4>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_I2C3>; + status = "disabled"; + }; + + memory-controller@21b0000 { + compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; + }; + + rngb: rngb@21b4000 { + compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; + reg = <0x021b4000 0x4000>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; + }; + + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; + reg = <0x021b8000 0x4000>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: efuse@21bc000 { + compatible = "fsl,imx6sl-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SL_CLK_OCOTP>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + }; + + gpu_2d: gpu@2200000 { + compatible = "vivante,gc"; + reg = <0x02200000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; + + gpu_vg: gpu@2204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts new file mode 100644 index 000000000000..e3e9b0ec4f73 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL EVK Board"; + compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + backlight_display: backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-user { + label = "debug"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_usb_otg1_vbus: regulator-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud3v: regulator-aud3v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator-aud4v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + reg_sd3_vmmc: regulator-sd3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + model = "wm8962-audio"; + audio-cpu = <&ssi2>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + >; + }; + + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 + >; + }; + + pinctrl_usb_otg1_vbus: vbus1grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: vbus2grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + >; + }; + + pinctrl_reg_lcd_3v3: reglcd3v3grp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 + >; + }; + + pinctrl_reg_sd1_vmmc: sd1vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x13059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts new file mode 100644 index 000000000000..c7cfe0b70f04 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Device tree for the Kobo Clara HD ebook reader + * + * Name on mainboard is: 37NB-E60K00+4A4 + * Serials start with: E60K02 (a number also seen in + * vendor kernel sources) + * + * This mainboard seems to be equipped with different SoCs. + * In the Kobo Clara HD ebook reader it is an i.MX6SLL + * + * Copyright 2019 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" +#include "e60k02.dtsi" + +/ { + model = "Kobo Clara HD"; + compatible = "kobo,clarahd", "fsl,imx6sll"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&dcdc3_reg>; + soc-supply = <&dcdc1_reg>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x10059 /* TP_RST */ + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ + MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79 + MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 + MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79 + MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79 + MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 + MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 + MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 + MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 + MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 + MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 + MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 + MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 + MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 + MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 + MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 + MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 + MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 + MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 + MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 + MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 + MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 + MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 + MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 + MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 + MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1 + MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2grp-sleep { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 + MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 + MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 + MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grp-sleep { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 + MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 + MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 + MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; +}; + +&lm3630a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; +}; + +&ricoh619 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; +}; + +&wifi_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts new file mode 100644 index 000000000000..7e4f38dd11e2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Device tree for the Kobo Libra H2O ebook reader + * + * Name on mainboard is: 37NB-E70K0M+6A3 + * Serials start with: E70K02 (a number also seen in + * vendor kernel sources) + * + * This mainboard seems to be equipped with different SoCs. + * In the Kobo Libra H2O ebook reader it is an i.MX6SLL + * + * Copyright 2021 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" +#include "e70k02.dtsi" + +/ { + model = "Kobo Libra H2O"; + compatible = "kobo,librah2o", "fsl,imx6sll"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&dcdc3_reg>; + soc-supply = <&dcdc1_reg>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* TP_INT */ + MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */ + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ + MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x17059 /* HALL_EN */ + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 + MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 + MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 + MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 + MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 + MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 + MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 + MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 + MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 + MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 + MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 + MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 + MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 + MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 + MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 + MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 + MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 + MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 + MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 + MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 + MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 + MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x79 + MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x79 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x10059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */ + MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */ + MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x17059 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x17059 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x17059 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1-sleepgrp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x10059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x10059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x10059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x10059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x10059 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x10059 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x10059 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x10059 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x10059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 + MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 + MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 + MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; +}; + +&lm3630a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; +}; + +&ricoh619 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1_sleep>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; +}; + +&wifi_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h new file mode 100644 index 000000000000..713a346f4c89 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h @@ -0,0 +1,880 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#ifndef __DTS_IMX6SLL_PINFUNC_H +#define __DTS_IMX6SLL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 + +#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi new file mode 100644 index 000000000000..2873369a57c0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi @@ -0,0 +1,839 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#include +#include +#include +#include "imx6sll-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = + /* kHz uV */ + <996000 1275000>, + <792000 1175000>, + <396000 1075000>, + <198000 975000>; + fsl,soc-operating-points = + /* ARM kHz SOC-PU uV */ + <996000 1175000>, + <792000 1175000>, + <396000 1175000>, + <198000 1175000>; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL2_PFD2>, + <&clks IMX6SLL_CLK_STEP>, + <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + ckil: clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + L2: cache-controller@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, + <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_SPDIF>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI1>, + <&clks IMX6SLL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI2>, + <&clks IMX6SLL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI3>, + <&clks IMX6SLL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI4>, + <&clks IMX6SLL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@2018000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts = ; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART4_IPG>, + <&clks IMX6SLL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@2024000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART2_IPG>, + <&clks IMX6SLL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi@2028000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, + <&clks IMX6SLL_CLK_SSI1>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi2: ssi@202c000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, + <&clks IMX6SLL_CLK_SSI2>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi3: ssi@2030000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, + <&clks IMX6SLL_CLK_SSI3>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + uart3: serial@2034000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = ; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-name = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART3_IPG>, + <&clks IMX6SLL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@2080000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM1>, + <&clks IMX6SLL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm2: pwm@2084000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM2>, + <&clks IMX6SLL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm3: pwm@2088000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM3>, + <&clks IMX6SLL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm4: pwm@208c000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM4>, + <&clks IMX6SLL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + gpt1: timer@2098000 { + compatible = "fsl,imx6sl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_GPT_BUS>, + <&clks IMX6SLL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 50 32>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>, + <&iomuxc 16 101 2>, <&iomuxc 18 5 1>, + <&iomuxc 21 6 11>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>, + <&iomuxc 16 151 1>, <&iomuxc 17 149 1>, + <&iomuxc 18 146 1>, <&iomuxc 19 144 1>, + <&iomuxc 20 142 1>, <&iomuxc 21 143 1>, + <&iomuxc 22 150 1>, <&iomuxc 23 148 1>, + <&iomuxc 24 147 1>, <&iomuxc 25 145 1>, + <&iomuxc 26 152 1>, <&iomuxc 27 125 1>, + <&iomuxc 28 131 1>, <&iomuxc 29 134 1>, + <&iomuxc 30 129 1>, <&iomuxc 31 133 1>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_GPIO5>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>, + <&iomuxc 2 132 1>, <&iomuxc 3 130 1>, + <&iomuxc 4 127 1>, <&iomuxc 5 126 1>, + <&iomuxc 6 120 1>, <&iomuxc 7 123 1>, + <&iomuxc 8 118 1>, <&iomuxc 9 122 1>, + <&iomuxc 10 124 1>, <&iomuxc 11 117 1>, + <&iomuxc 12 121 1>, <&iomuxc 13 119 1>, + <&iomuxc 14 116 1>, <&iomuxc 15 115 1>, + <&iomuxc 16 140 2>, <&iomuxc 18 136 1>, + <&iomuxc 19 138 1>, <&iomuxc 20 139 1>, + <&iomuxc 21 137 1>; + }; + + gpio6: gpio@20b0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_GPIO6>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG1>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + + assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; + assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6sll-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x020c8000 0x4000>; + interrupts = , + , + ; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p0: regulator-3p0@20c8120 { + compatible = "fsl,anatop-regulator"; + reg = <0x20c8120>; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + tempmon: temperature-sensor { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; + }; + + usbphy1: usb-phy@20c9000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usb-phy@20ca000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; + phy-reg_3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + status = "disabled"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + status = "disabled"; + }; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6sll-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: interrupt-controller@20dc000 { + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6sll-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@20e4000 { + compatible = "fsl,imx6sll-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + csi: csi@20e8000 { + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_CSI>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pxp: pxp@20f0000 { + compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp"; + reg = <0x20f0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_PXP>; + clock-names = "axi"; + }; + + lcdif: lcd-controller@20f8000 { + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, + <&clks IMX6SLL_CLK_LCDIF_APB>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + dcp: crypto@20fc000 { + compatible = "fsl,imx28-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SLL_CLK_DCP>; + clock-names = "dcp"; + }; + }; + + aips2: bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: memory-controller@21b0000 { + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; + }; + + rngb: rng@21b4000 { + compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>; + }; + + ocotp: efuse@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sll-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SLL_CLK_OCOTP>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = ; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART5_IPG>, + <&clks IMX6SLL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts new file mode 100644 index 000000000000..a2c79bcf9a11 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Boundary Devices, Inc. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; + compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_3p3v>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can1_3v3: regulator-can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan: regulator-wlan { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan>; + compatible = "regulator-fixed"; + clocks = <&clks IMX6SX_CLK_CKO>; + clock-names = "slow"; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6sx-nitrogen6sx-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <5>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: flash@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0xc0000>; + read-only; + }; + + partition@c0000 { + label = "env"; + reg = <0xc0000 0x2000>; + read-only; + }; + + partition@c2000 { + label = "Kernel"; + reg = <0xc2000 0x11e000>; + }; + + partition@1e0000 { + label = "M4"; + reg = <0x1e0000 0x20000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + reg = <4>; + }; + + ethphy2: ethernet-phy@5 { + reg = <5>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6SX_CLK_CKO2>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + VDDD-supply = <®_1p8v>; + assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, + <&clks IMX6SX_CLK_CKO2>; + assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; + assigned-clock-rates = <0>, <24000000>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + disable-over-current; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_wlan>; + cap-power-off-card; + cap-sdio-irq; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio7>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + }; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 + MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 + MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 + MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 + MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 + MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 + MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 + MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 + MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 + MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 + MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 + MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 + MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 + /* Test points */ + MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 + MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 + MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_reg_wlan: reg-wlangrp { + fsl,pins = < + MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 + MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1-vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h new file mode 100644 index 000000000000..f4dc46207954 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h @@ -0,0 +1,1668 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX6SX_PINFUNC_H +#define __DTS_IMX6SX_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 +#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 +#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 +#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 +#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 +#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 +#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 +#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 +#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 +#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 +#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 +#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 +#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 +#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 +#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 +#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 +#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 +#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 +#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 +#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 +#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 +#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 +#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 +#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 +#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 +#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 +#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 +#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 +#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 +#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 +#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 +#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 +#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 +#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 +#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0 +#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 +#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 +#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 +#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 +#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1 +#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 +#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 +#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 +#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 +#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 +#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 +#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1 +#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 +#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 +#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 +#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 +#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 +#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 +#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 +#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2 +#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 +#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 +#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 +#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 +#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3 +#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 +#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 +#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 +#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 +#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 +#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3 +#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 +#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 +#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 +#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 +#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 +#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 +#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 +#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 +#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 +#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 +#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 +#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 +#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 +#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 +#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +/* + * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is + * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a + * PHY in RMII mode. This configuration is valid if: + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset + * It seems to be a silicon bug that in this configuration ENET1_TX reference + * clock isn't provided automatically. According to i.MX6SX reference manual + * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it + * should be the case. + * So this might have unwanted side effects for other hardware units that are + * also connected to that pin and using respective function as input (e.g. + * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). + */ +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 +#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 +#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 +#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2 +#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 +#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 +#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 +#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 +#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3 +#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 +#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 +#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 +#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 +#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 +#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3 +#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 +#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 +#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 +#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 +#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 +#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 +#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 +#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2 +#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 +#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 +#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 +#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 +#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 +#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2 +#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 +#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 +#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 +#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 +#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3 +#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 +#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 +#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 +#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 +#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3 +#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 +#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 +#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 +#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 +#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 +#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3 +#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 +#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 +#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 +#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3 +#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 +#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 +#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 +#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 +#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 +#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 +#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 +#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 +#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 +#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 +#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 +#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 +#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 +#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 +#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 +#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 +#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 +#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 +#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 +#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 +#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 +#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 +#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 +#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 +#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 +#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 +#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 +#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 +#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 +#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 +#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 +#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 +#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 +#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 +#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 +#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 +#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 +#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 +#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 +#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 +#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 +#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 +#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 +#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 +#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 +#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 +#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 +#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 +#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 +#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 +#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 +#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 +#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 +#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 +#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1 +#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 +#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0 +#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 +#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1 +#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 +#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 +#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 +#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 +#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 +#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 +#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 +#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 +#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 +#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 +#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 +#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 +#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 +#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 +#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 +#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 +#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 +#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 +#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 +#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 +#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 +#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 +#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 +#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 +#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 +#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 +#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 +#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 +#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 +#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 +#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 +#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 +#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 +#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 +#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 +#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 +#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4 +#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 +#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 +#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 +#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 +#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 +#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 +#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 +#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 +#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 +#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 +#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 +#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5 +#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 +#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 +#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 +#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 +#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 +#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 +#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 +#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 +#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 +#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 +#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 +#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 +#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 +#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 +#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 +#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 +#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 +#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 +#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 +#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 +#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 +#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 +#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2 +#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 +#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3 +#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 +#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 +#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 +#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2 +#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 +#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 +#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 +#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 +#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 +#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 +#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 +#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 +#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 +#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 +#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 +#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 +#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 +#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 +#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 +#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 +#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 +#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4 +#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 +#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 +#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 +#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 +#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5 +#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 +#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 +#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 +#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 +#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 +#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4 +#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 +#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 +#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 +#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 +#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 +#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 +#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 +#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 +#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5 +#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 +#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 +#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 +#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 +#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0 +#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 +#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 +#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 +#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 +#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 +#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 +#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 +#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 +#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 +#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1 +#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 +#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 +#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 +#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 +#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2 +#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3 +#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 +#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3 +#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 +#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 +#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 +#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 +#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 +#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 +#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 +#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 +#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 +#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 +#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 +#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 +#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 +#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0 +#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 +#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1 +#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 +#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 +#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 +#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 +#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1 +#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 +#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 +#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 +#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 +#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 +#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 +#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 +#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 +#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 +#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 +#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 +#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 +#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 +#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 +#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 +#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 +#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 +#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 +#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 +#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 + +/* these are not supposed to be used any more and remove them after some time */ +#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX +#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX +#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX +#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX +#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX +#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX +#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS +#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX +#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX +#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS +#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS +#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS +#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX +#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX +#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX +#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX +#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS +#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS +#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS +#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX +#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX +#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX +#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX +#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS +#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX +#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX +#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX +#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX +#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS +#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS +#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS +#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX +#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX +#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS +#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX +#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX +#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS +#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX +#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX +#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS +#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX +#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX +#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS +#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS +#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX +#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX +#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX +#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX +#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS +#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS +#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX +#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX +#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX +#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX +#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX +#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX +#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS +#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS +#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX +#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX +#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX +#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX +#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX +#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX +#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX +#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX +#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS +#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX +#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX +#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS +#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX +#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX +#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX +#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX +#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX +#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX +#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS +#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS +#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX +#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX +#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX +#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX +#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS +#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS + +#endif /* __DTS_IMX6SX_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts new file mode 100644 index 000000000000..b0c27b9b0244 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX Sabre Auto Board"; + compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-user { + label = "debug"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_sd3: regulator-vcc-sd3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_wake: regulator-can-wake { + compatible = "regulator-fixed"; + regulator-name = "can-wake"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_wake>; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_cs42888: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai>; + audio-asrc = <&asrc>; + audio-codec = <&cs42888>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + }; +}; + +&anaclk2 { + clock-frequency = <24576000>; +}; + +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, + <&clks IMX6SX_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_egalax_int: egalax-intgrp { + fsl,pins = < + MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&anaclk2 0>; + clock-names = "mclk"; + VA-supply = <®_cs42888>; + VD-supply = <®_cs42888>; + VLS-supply = <®_cs42888>; + VLC-supply = <®_cs42888>; + }; + + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; + }; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts new file mode 100644 index 000000000000..a4ab2d3e960c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +#include "imx6sx-sdb.dts" +/ { + + sound { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-asrc = <&asrc>; + audio-codec = <&mqs>; + }; +}; + +&usdhc2 { + /* pin conflict with mqs*/ + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + pinctrl-0 = <>; + status = "okay"; +}; + +&ssi2 { + status = "disabled"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts new file mode 100644 index 000000000000..48f19dede467 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6sx-sdb.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB RevA Board"; + compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s", "jedec,spi-nor"; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; + + flash1: flash@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s", "jedec,spi-nor"; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +®_can_en { + /* Transceiver EN/STBY is active high on RevA board */ + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +®_can_stby { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; +}; + +®_vdd1p1 { + vin-supply = <&vgen6_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen6_reg>; +}; + +&snvs_pwrkey { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts new file mode 100644 index 000000000000..1c4eacd68e1b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. + +#include "imx6sx-sdb.dts" + +/ { + sound { + audio-cpu = <&sai1>; + }; +}; + +&audmux { + /* pin conflict with sai */ + status = "disabled"; +}; + +&sai1 { + status = "okay"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; + +&ssi2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts new file mode 100644 index 000000000000..e05a1be5553c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6sx-sdb.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB RevB Board"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; + + flash1: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <2>; + }; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_soc { + vin-supply = <&sw1a_reg>; +}; + +®_vdd1p1 { + vin-supply = <&vgen6_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen6_reg>; +}; + +®_can_stby { + /* Transceiver EN/STBY is active low on RevB board */ + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; +}; + +&snvs_pwrkey { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi new file mode 100644 index 000000000000..c6e85e4a0883 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include +#include +#include "imx6sx.dtsi" + +/ { + model = "Freescale i.MX6 SoloX SDB Board"; + compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + backlight_display: backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + vcc_sd3: regulator-vcc-sd3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_psu_5v: regulator-psu-5v { + compatible = "regulator-fixed"; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + }; + + reg_peri_3v3: regulator-peri-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet_3v3: regulator-enet-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + regulator-boot-on; + regulator-always-on; + }; + + reg_pcie_gpio: regulator-pcie-gpio { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <6>; + hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_enet_3v3>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SX_CLK_AUDIO>; + DCVDD-supply = <&vgen4_reg>; + DBVDD-supply = <&vgen4_reg>; + AVDD-supply = <&vgen4_reg>; + CPVDD-supply = <&vgen4_reg>; + MICVDD-supply = <&vgen3_reg>; + PLLVDD-supply = <&vgen4_reg>; + SPKVDD1-supply = <®_psu_5v>; + SPKVDD2-supply = <®_psu_5v>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_gpio>; + status = "okay"; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + imx6x-sdb { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + /* phy reset */ + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 + >; + }; + + pinctrl_enet_3v3: enet3v3grp { + fsl,pins = < + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 + >; + }; + + pinctrl_peri_3v3: peri3v3grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 + >; + }; + + pinctrl_pwm3: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_qspi2: qspi2grp { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 + >; + }; + + pinctrl_vcc_sd3: vccsd3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2: usbot2ggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts new file mode 100644 index 000000000000..bfcd8f7d86dd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Christoph Fritz + */ + +/dts-v1/; + +#include +#include +#include "imx6sx.dtsi" + +/ { + model = "Softing VIN|ING 2000"; + compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg1_vbus: regulator-usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_peri_3v3: regulator-peri_3v3 { + compatible = "regulator-fixed"; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + label = "red"; + max-brightness = <255>; + pwms = <&pwm6 0 50000>; + }; + + led-2 { + label = "green"; + max-brightness = <255>; + pwms = <&pwm2 0 50000>; + }; + + led-3 { + label = "blue"; + max-brightness = <255>; + pwms = <&pwm1 0 50000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_peri_3v3>; + status = "okay"; +}; + +&cpu0 { + /* + * This board has a shared rail of reg_arm and reg_soc (supplied by + * sw1a_reg) which is modeled below, but still this module behaves + * unstable without higher voltages. Hence, set higher voltages here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_peri_3v3>; + phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet0-phy@0 { + reg = <0>; + max-speed = <100>; + interrupt-parent = <&gpio2>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-supply = <®_peri_3v3>; + phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet1-phy@0 { + reg = <0>; + max-speed = <100>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + proximity: sx9500@28 { + compatible = "semtech,sx9500"; + reg = <0x28>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sx9500>; + interrupt-parent = <&gpio2>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + pmic: pmic@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 + MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 + /* LAN8720 PHY Reset */ + MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 + /* MDIO */ + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 + /* IRQ from PHY */ + MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 + MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 + /* LAN8720 PHY Reset */ + MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 + /* MDIO */ + MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 + MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 + /* IRQ from PHY */ + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + /* reset external uC */ + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 + /* IRQ from external uC */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 + /* overcurrent detection */ + MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 + >; + }; + + pinctrl_pwm1: pwm1grp-1 { + fsl,pins = < + /* blue LED */ + MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp-1 { + fsl,pins = < + /* green LED */ + MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm6: pwm6grp-1 { + fsl,pins = < + /* red LED */ + MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 + >; + }; + + pinctrl_sx9500: sx9500grp { + fsl,pins = < + /* Reset */ + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 + /* IRQ */ + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm6 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_soc { + vin-supply = <&sw1a_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + /* hs200-mode is currently unsupported because Vccq is on 3.1V, but + * not on necessary 1.8V. + */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + bus-width = <8>; + keep-power-in-suspend; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts new file mode 100644 index 000000000000..205ea26484e3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Basic"; + compatible = "udoo,neobasic", "fsl,imx6sx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&fec1 { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts new file mode 100644 index 000000000000..5817b4985391 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Extended"; + compatible = "udoo,neoextended", "fsl,imx6sx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&i2c4 { /* Onboard Motion sensors */ + status = "okay"; +}; + +&uart3 { /* Bluetooth */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts new file mode 100644 index 000000000000..96f4d89848a3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Full"; + compatible = "udoo,neofull", "fsl,imx6sx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&fec1 { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c4 { /* Onboard Motion sensors */ + status = "okay"; +}; + +&uart3 { /* Bluetooth */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi new file mode 100644 index 000000000000..725d0b5cb55f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + */ + +#include "imx6sx.dtsi" + +/ { + compatible = "fsl,imx6sx"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-red { + label = "udoo-neo:red:mmc"; + gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led-orange { + label = "udoo-neo:orange:user"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + reg_sdio_pwr: regulator-sdio-pwr { + compatible = "regulator-fixed"; + gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "SDIO_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_otg1_reg>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_otg2_reg>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { /* Brick snap in sensors connector */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>; + + ports { + port { + hdmi: endpoint { + remote-endpoint = <&lcdc>; + }; + }; + }; + }; +}; + +&i2c4 { /* Onboard Motion sensors */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + lcdc: endpoint { + remote-endpoint = <&hdmi>; + }; + }; +}; + +&iomuxc { + pinctrl_bt_reg: btreggrp { + fsl,pins = + ; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = + , + , + , + , + , + , + + , + , + , + , + , + , + + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = + , + ; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + , + , + , + ; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = + , + ; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = + , + , + , + , + , + , + , + ; + }; + + pinctrl_otg1_reg: otg1grp { + fsl,pins = + ; + }; + + pinctrl_otg2_reg: otg2grp { + fsl,pins = + ; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = + , + ; + }; + + pinctrl_usb_otg2: usbot2ggrp { + fsl,pins = + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , + , + , + , + , + , + ; /* CD */ + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + , + , + , + ; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Cortex-M4 serial */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&uart3 { /* Bluetooth - only on Extended/Full versions */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; + + bluetooth { + compatible = "ti,wl1831-st"; + enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_reg>; + max-speed = <921600>; + }; +}; + +/* Arduino serial */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbotg1 { /* J2 micro USB port */ + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + status = "okay"; +}; + +&usbotg2 { /* J3 host USB port */ + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_sdio_pwr>; + bus-width = <4>; + cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { /* Wi-Fi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + vmmc-supply = <®_wlan>; + cap-power-off-card; + wakeup-source; + keep-power-in-suspend; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1831"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <16 IRQ_TYPE_EDGE_RISING>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi new file mode 100644 index 000000000000..3a4308666552 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -0,0 +1,1469 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2014 Freescale Semiconductor, Inc. + +#include +#include +#include +#include +#include "imx6sx-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + spi4 = &ecspi5; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + clocks = <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_STEP>, + <&clks IMX6SX_CLK_PLL1_SW>, + <&clks IMX6SX_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + ckil: clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + anaclk1: clock-anaclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "anaclk1"; + }; + + anaclk2: clock-anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "anaclk2"; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = ; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram_s: sram@8f8000 { + compatible = "mmio-sram"; + reg = <0x008f8000 0x4000>; + ranges = <0 0x008f8000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + L2: cache-controller@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + gpu: gpu@1800000 { + compatible = "vivante,gc"; + reg = <0x01800000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_GPU>, + <&clks IMX6SX_CLK_GPU>, + <&clks IMX6SX_CLK_GPU>; + clock-names = "bus", "core", "shader"; + power-domains = <&pd_pu>; + }; + + dma_apbh: dma-controller@1804000 { + compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x01804000 0x2000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6SX_CLK_APBH_DMA>; + }; + + gpmi: nand-controller@1806000{ + compatible = "fsl,imx6sx-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01806000 0x2000>, <0x01808000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clks IMX6SX_CLK_GPMI_IO>, + <&clks IMX6SX_CLK_GPMI_APB>, + <&clks IMX6SX_CLK_GPMI_BCH>, + <&clks IMX6SX_CLK_GPMI_BCH_APB>, + <&clks IMX6SX_CLK_PER1_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, + <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_SPDIF>, + <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_IPG>, + <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI1>, + <&clks IMX6SX_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI2>, + <&clks IMX6SX_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI3>, + <&clks IMX6SX_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI4>, + <&clks IMX6SX_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + esai: esai@2024000 { + compatible = "fsl,imx6sx-esai", "fsl,imx35-esai"; + reg = <0x02024000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ESAI_IPG>, + <&clks IMX6SX_CLK_ESAI_MEM>, + <&clks IMX6SX_CLK_ESAI_EXTAL>, + <&clks IMX6SX_CLK_ESAI_IPG>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "core", "mem", "extal", + "fsys", "spba"; + dmas = <&sdma 23 21 0>, + <&sdma 24 21 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ssi1: ssi@2028000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SSI1_IPG>, + <&clks IMX6SX_CLK_SSI1>; + clock-names = "ipg", "baud"; + dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi2: ssi@202c000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SSI2_IPG>, + <&clks IMX6SX_CLK_SSI2>; + clock-names = "ipg", "baud"; + dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + ssi3: ssi@2030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SSI3_IPG>, + <&clks IMX6SX_CLK_SSI3>; + clock-names = "ipg", "baud"; + dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + asrc: asrc@2034000 { + compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, + <&sdma 19 23 1>, <&sdma 20 23 1>, + <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; + }; + + pwm1: pwm@2080000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM1>, + <&clks IMX6SX_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm2: pwm@2084000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM2>, + <&clks IMX6SX_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm3: pwm@2088000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM3>, + <&clks IMX6SX_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm4: pwm@208c000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM4>, + <&clks IMX6SX_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + flexcan1: can@2090000 { + compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_CAN1_IPG>, + <&clks IMX6SX_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1>; + status = "disabled"; + }; + + flexcan2: can@2094000 { + compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_CAN2_IPG>, + <&clks IMX6SX_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2>; + status = "disabled"; + }; + + gpt: timer@2098000 { + compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_GPT_BUS>, + <&clks IMX6SX_CLK_GPT_3M>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 5 26>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 31 20>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 51 29>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 80 32>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 112 24>; + }; + + gpio6: gpio@20b0000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; + }; + + gpio7: gpio@20b4000 { + compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; + reg = <0x020b4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6sx-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = , + , + ; + + reg_vdd1p1: regulator-1p1 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; + }; + + reg_vdd3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_vdd2p5: regulator-2p5 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2100000>; + anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddarm"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_pcie: regulator-vddpcie { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpcie"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; + }; + + usbphy1: usbphy@20c9000 { + compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBPHY1>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@20ca000 { + compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBPHY2>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + status = "disabled"; + }; + }; + + epit1: epit@20d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@20d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6sx-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@20dc000 { + compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_soc>; + clocks = <&clks IMX6SX_CLK_GPU>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + }; + + pd_pci: power-domain@3 { + reg = <3>; + #power-domain-cells = <0>; + power-supply = <®_pcie>; + }; + }; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6sx-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: syscon@20e4000 { + compatible = "fsl,imx6sx-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x020e4000 0x4000>; + + lvds_bridge: bridge@18 { + compatible = "fsl,imx6sx-ldb"; + reg = <0x18 0x4>; + clocks = <&clks IMX6SX_CLK_LDB_DI0>; + clock-names = "ldb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + }; + }; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>, + <&clks IMX6SX_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + /* imx6sx reuses imx6q sdma firmware */ + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + }; + + aips2: bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + crypto: crypto@2100000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2100000 0x10000>; + ranges = <0 0x2100000 0x10000>; + interrupt-parent = <&intc>; + clocks = <&clks IMX6SX_CLK_CAAM_MEM>, + <&clks IMX6SX_CLK_CAAM_ACLK>, + <&clks IMX6SX_CLK_CAAM_IPG>, + <&clks IMX6SX_CLK_EIM_SLOW>; + clock-names = "mem", "aclk", "ipg", "emi_slow"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbh: usb@2184400 { + compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc 2>; + phy_type = "hsic"; + fsl,anatop = <&anatop>; + dr_mode = "host"; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks IMX6SX_CLK_USBOH3>; + }; + + fec1: ethernet@2188000 { + compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; + interrupts = , + ; + clocks = <&clks IMX6SX_CLK_ENET>, + <&clks IMX6SX_CLK_ENET_AHB>, + <&clks IMX6SX_CLK_ENET_PTP>, + <&clks IMX6SX_CLK_ENET_REF>, + <&clks IMX6SX_CLK_ENET_PTP>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 3>; + status = "disabled"; + }; + + mlb: mlb@218c000 { + reg = <0x0218c000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SX_CLK_MLB>; + status = "disabled"; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC1>, + <&clks IMX6SX_CLK_USDHC1>, + <&clks IMX6SX_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC2>, + <&clks IMX6SX_CLK_USDHC2>, + <&clks IMX6SX_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC3>, + <&clks IMX6SX_CLK_USDHC3>, + <&clks IMX6SX_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc4: mmc@219c000 { + compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_USDHC4>, + <&clks IMX6SX_CLK_USDHC4>, + <&clks IMX6SX_CLK_USDHC4>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C3>; + status = "disabled"; + }; + + memory-controller@21b0000 { + compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; + }; + + fec2: ethernet@21b4000 { + compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; + reg = <0x021b4000 0x4000>; + interrupt-names = "int0", "pps"; + interrupts = , + ; + clocks = <&clks IMX6SX_CLK_ENET>, + <&clks IMX6SX_CLK_ENET_AHB>, + <&clks IMX6SX_CLK_ENET_PTP>, + <&clks IMX6SX_CLK_ENET2_REF_125M>, + <&clks IMX6SX_CLK_ENET_PTP>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: efuse@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sx-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCOTP>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + sai1: sai@21d4000 { + compatible = "fsl,imx6sx-sai"; + reg = <0x021d4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SAI1_IPG>, + <&clks IMX6SX_CLK_SAI1>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; + status = "disabled"; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + sai2: sai@21dc000 { + compatible = "fsl,imx6sx-sai"; + reg = <0x021dc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_SAI2_IPG>, + <&clks IMX6SX_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; + status = "disabled"; + }; + + qspi1: spi@21e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6SX_CLK_QSPI1>, + <&clks IMX6SX_CLK_QSPI1>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + qspi2: spi@21e4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-qspi"; + reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6SX_CLK_QSPI2>, + <&clks IMX6SX_CLK_QSPI2>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + uart2: serial@21e8000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@21ec000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@21f0000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@21f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_I2C4>; + status = "disabled"; + }; + }; + + aips3: bus@2200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02200000 0x100000>; + ranges; + + spba-bus@2240000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02240000 0x40000>; + ranges; + + csi1: csi@2214000 { + reg = <0x02214000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_DCIC1>; + clock-names = "disp-axi", "csi_mclk", "dcic"; + status = "disabled"; + }; + + pxp: pxp@2218000 { + compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; + reg = <0x02218000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PXP_AXI>; + clock-names = "axi"; + power-domains = <&pd_disp>; + status = "disabled"; + }; + + csi2: csi@221c000 { + reg = <0x0221c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_DCIC2>; + clock-names = "disp-axi", "csi_mclk", "dcic"; + status = "disabled"; + }; + + lcdif1: lcdif@2220000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; + reg = <0x02220000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; + status = "disabled"; + + ports { + port { + lcdif1_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif1>; + }; + }; + }; + }; + + lcdif2: lcdif@2224000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; + reg = <0x02224000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; + status = "disabled"; + }; + + vadc: vadc@2228000 { + reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; + reg-names = "vadc-vafe", "vadc-vdec"; + clocks = <&clks IMX6SX_CLK_VADC>, + <&clks IMX6SX_CLK_CSI>; + clock-names = "vadc", "csi"; + power-domains = <&pd_disp>; + status = "disabled"; + }; + }; + + adc1: adc@2280000 { + compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; + reg = <0x02280000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "adc"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + status = "disabled"; + }; + + adc2: adc@2284000 { + compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; + reg = <0x02284000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "adc"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + status = "disabled"; + }; + + wdog3: watchdog@2288000 { + compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; + reg = <0x02288000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_IPG>; + status = "disabled"; + }; + + ecspi5: spi@228c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; + reg = <0x0228c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_ECSPI5>, + <&clks IMX6SX_CLK_ECSPI5>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@22a0000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x022a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_UART_IPG>, + <&clks IMX6SX_CLK_UART_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm5: pwm@22a4000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM5>, + <&clks IMX6SX_CLK_PWM5>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm6: pwm@22a8000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM6>, + <&clks IMX6SX_CLK_PWM6>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm7: pwm@22ac000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022ac000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM7>, + <&clks IMX6SX_CLK_PWM7>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + + pwm8: pwm@22b0000 { + compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; + reg = <0x022b0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_PWM8>, + <&clks IMX6SX_CLK_PWM8>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + }; + }; + + pcie: pcie@8ffc000 { + compatible = "fsl,imx6sx-pcie"; + reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, + <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + power-domains = <&pd_disp>, <&pd_pci>; + power-domain-names = "pcie", "pcie_phy"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts new file mode 100644 index 000000000000..2438669f149a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6ul.dtsi" +#include "imx6ul-14x14-evk.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi new file mode 100644 index 000000000000..155515fe13fa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -0,0 +1,651 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + backlight_display: backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_peri_3v3: regulator-peri-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "VPERI_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; + /* + * If you want to want to make this dynamic please + * check schematics and test all affected peripherals: + * + * - sensors + * - ethernet phy + * - can + * - bluetooth + * - wm8960 audio codec + * - ov5640 camera + */ + regulator-always-on; + }; + + reg_can_3v3: regulator-can-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-asrc = <&asrc>; + hp-det-gpio = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "AMIC", + "RINPUT2", "AMIC", + "Mic Jack", "MICB", + "AMIC", "MICB"; + }; + + spi-4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + status = "okay"; + sck-gpios = <&gpio5 11 0>; + mosi-gpios = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + }; + }; + + panel { + compatible = "innolux,at043tn24"; + backlight = <&backlight_display>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8960"; + reg = <0x1a>; + wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + }; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera_clock>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "xclk"; + powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; + + port { + ov5640_to_parallel: endpoint { + remote-endpoint = <¶llel_from_ov5640>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; +}; + +&csi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + status = "okay"; + + port { + parallel_from_ov5640: endpoint { + remote-endpoint = <&ov5640_to_parallel>; + bus-type = ; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_peri_3v3>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_peri_3v3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1560"; + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1560"; + reg = <1>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpio_spi { + eth0-phy-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "eth0-phy"; + }; + + eth1-phy-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "eth1-phy"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + vdd-supply = <®_peri_3v3>; + vddio-supply = <®_peri_3v3>; + }; +}; + +&lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + broken-cd; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_camera_clock: cameraclockgrp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_peri_3v3: peri3v3grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sim2: sim2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts new file mode 100644 index 000000000000..3792679c0c90 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore6UL SBC Express board device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" +#include "imx6ul-ccimx6ulsom.dtsi" + +/ { + model = "Digi International ConnectCore 6UL SBC Express."; + compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", + "fsl,imx6ul"; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <&ext_3v3>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3_master>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + smsc,disable-energy-detect; + reg = <0>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + broken-cd; /* no carrier detect line (use polling) */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_ecspi3_master: ecspi3grp1 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_ecspi3_slave: ecspi3grp2 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + /* General purpose pinctrl */ + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIOs BANK 3 */ + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts new file mode 100644 index 000000000000..3ec042bfccba --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore6UL SBC Pro board device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" +#include "imx6ul-ccimx6ulsom.dtsi" + +/ { + model = "Digi International ConnectCore 6UL SBC Pro."; + compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul"; + + lcd_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 50000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + panel { + compatible = "auo,g101evn010"; + power-supply = <&ldo4_ext>; + backlight = <&lcd_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <&ext_3v3>; + status = "okay"; +}; + +/* CAN2 is multiplexed with UART2 RTS/CTS */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <&ext_3v3>; + status = "disabled"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_master>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + phy-reset-duration = <26>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + smsc,disable-energy-detect; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + smsc,disable-energy-detect; + reg = <1>; + }; + }; +}; + +&gpio5 { + emmc-usd-mux-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-high; + }; +}; + +&i2c1 { + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_goodix_touch>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat0_17 + &pinctrl_lcdif_clken + &pinctrl_lcdif_hvsync>; + lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */ + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&ldo4_ext { + regulator-max-microvolt = <1800000>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pwm5 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&pwm8 { + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-1 = <&pinctrl_sai2_sleep>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-rates = <0>, <786432000>, <12288000>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + status = "okay"; +}; + +/* UART2 RTS/CTS muxed with CAN2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_4wires>; + uart-has-rtscts; + status = "okay"; +}; + +/* UART3 RTS/CTS muxed with CAN 1 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2wires>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* USDHC2 (microSD conflicts with eMMC) */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + broken-cd; /* no carrier detect line (use polling) */ + status = "okay"; +}; + +&iomuxc { + pinctrl_adc1: adc1grp { + fsl,pins = < + /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_ecspi1_master: ecspi1grp1 { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051 + >; + }; + + pinctrl_enet2_mdio: mdioenet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + >; + }; + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_goodix_touch: goodixgrp{ + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 + >; + }; + + pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_lcdif_clken: lcdifctrlgrp1 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + >; + }; + + pinctrl_lcdif_hvsync: lcdifctrlgrp2 { + fsl,pins = < + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + /* Interrupt */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 + >; + }; + + pinctrl_sai2_sleep: sai2grp-sleep { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000 + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000 + /* Interrupt */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000 + >; + }; + + pinctrl_uart2_4wires: uart2grp-4wires { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3_2wires: uart3grp-2wires { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + /* Mux selector between eMMC/SD# */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi new file mode 100644 index 000000000000..7d1a391431bd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore 6UL System-On-Module device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <&vdda_adc_3v3>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + int_3v3: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm_soc_in: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <925000>; + }; + }; + + ext_3v3: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr3: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1300000>; + }; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vdd_snvs_3v3: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vdda_adc_3v3: vldo1 { + compatible = "regulator-fixed"; + regulator-name = "vref-adc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo2_ext: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vdda_wlan: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_high_in: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_int: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_ext: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vcoin_chg: coin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +/* UART1 (Bluetooth) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* USDHC1 (Wireless) */ +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>; + pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>; + non-removable; + no-1-8-v; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmigrp { + fsl,pins = < + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1grp-sleep { + fsl,pins = < + MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000 + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000 + MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000 + MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000 + MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000 + >; + }; + + pinctrl_wifibt_ctrl: wifibt-ctrl-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0 + >; + }; + + pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000 + >; + }; +}; + +®_arm { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts new file mode 100644 index 000000000000..a0097da03f38 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "Engicam GEAM6UL Starter Kit"; + compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x08000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm8 0 100000>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <100>; + }; + + chosen { + stdout-path = &uart1; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6ul-geam-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6UL_CLK_OSC>; + clock-names = "mclk"; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <28000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <30>; + hback-porch = <30>; + hsync-len = <64>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm8 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + +&tsc { + measure-delay-time = <0x1ffff>; + pre-charge-time = <0x1fff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi new file mode 100644 index 000000000000..f2386dcb9ff2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2019 Armadeus Systems + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-reset-duration = <1>; + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; + }; +}; + +/* Bluetooth */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + uart-has-rtscts; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + /* INT# */ + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 + /* RST# */ + MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 + /* BT_REG_ON */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 + /* WL_REG_ON */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 + /* WL_IRQ */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi new file mode 100644 index 000000000000..18cac19aa9b0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2019 Armadeus Systems + +/ { + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 191000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_5v>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user-button { + label = "User button"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + user-led { + label = "User"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + onewire { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_w1>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + + panel: panel { + compatible = "armadeus,st0700-adapt"; + power-supply = <®_3v3>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg1_vbus: regulator-usbotg1vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg1vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg2_vbus: regulator-usbotg2vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg2vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <®_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xffff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + vbus-supply = <®_usbotg1_vbus>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbotg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0 + MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0 + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0 + MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0 + MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts new file mode 100644 index 000000000000..1df3e376ae2c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6ul-isiot.dtsi" + +/ { + model = "Engicam Is.IoT MX6UL eMMC Starter kit"; + compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts new file mode 100644 index 000000000000..8c26d4d1a7bf --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +/dts-v1/; + +#include "imx6ul-isiot.dtsi" + +/ { + model = "Engicam Is.IoT MX6UL NAND Starter kit"; + compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi new file mode 100644 index 000000000000..14fc4828ba4e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + */ + +#include +#include +#include "imx6ul.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm8 0 100000>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <100>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6ul-isiot-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6UL_CLK_OSC>; + clock-names = "mclk"; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; + + stmpe811: gpio-expander@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + stmpe: touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <28000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <30>; + hback-porch = <30>; + hsync-len = <64>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm8 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + bus-width = <8>; + no-1-8-v; + status = "disabled"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts new file mode 100644 index 000000000000..0c643706a158 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include "imx6ul-kontron-bl.dts" + +/ { + model = "Kontron BL i.MX6UL 43 (N631X S 43)"; + compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", + "kontron,sl-imx6ul", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm7 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; +}; + +&i2c4 { + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cap_touch>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + /* Leave status disabled because of missing display panel node */ +}; + +&pwm7 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&iomuxc { + pinctrl_cap_touch: captouchgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi new file mode 100644 index 000000000000..43868311f48a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include + +/ { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "debug-led1"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "debug-led2"; + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "debug-led3"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm8 0 5000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_adc: regulator-vref-adc { + compatible = "regulator-fixed"; + regulator-name = "vref-adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_vref_adc>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32e61w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <8192>; + address-width = <16>; + }; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm8 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + rs485-rts-active-low; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 + >; + }; + + pinctrl_enet2_mdio: enet2mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 + /* + * mux unused RTS to make sure it doesn't cause + * any interrupts when it is undefined + */ + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts new file mode 100644 index 000000000000..dadf6d3d5f52 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +/dts-v1/; + +#include "imx6ul-kontron-sl.dtsi" +#include "imx6ul-kontron-bl-common.dtsi" + +/ { + model = "Kontron BL i.MX6UL (N631X S)"; + compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi new file mode 100644 index 000000000000..dcf88f610346 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@80000000 { + reg = <0x80000000 0x10000000>; + device_type = "memory"; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + flash@0 { + compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec2 { + phy-mode = "rmii"; + status = "disabled"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_out>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + >; + }; + + pinctrl_enet1_mdio: enet1mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_reset_out: rstoutgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi new file mode 100644 index 000000000000..0580d043e5ae --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include "imx6ul.dtsi" +#include "imx6ul-kontron-sl-common.dtsi" + +/ { + model = "Kontron SL i.MX6UL (N631X SOM)"; + compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts new file mode 100644 index 000000000000..1d863a16bcf0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts @@ -0,0 +1,151 @@ +/* + * Copyright 2016 Grinn + * + * Author: Marcin Niestroj + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul-litesom.dtsi" + +/ { + model = "Grinn i.MX6UL liteBoard"; + compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom", + "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usb_otg1_vbus: usb-otg1-vbus { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79 + >; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi new file mode 100644 index 000000000000..8d6893210842 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright 2016 Grinn + * + * Author: Marcin Niestroj + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" + +/ { + model = "Grinn i.MX6UL liteSOM"; + compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 + >; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi new file mode 100644 index 000000000000..6ce84f92b027 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2017 Armadeus Systems + +#include "imx6ul.dtsi" +#include "imx6ul-imx6ull-opos6ul.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts new file mode 100644 index 000000000000..375b98d7205a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2017 Armadeus Systems + +/dts-v1/; +#include "imx6ul-opos6ul.dtsi" +#include "imx6ul-imx6ull-opos6uldev.dtsi" + +/ { + model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board"; + compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>; + + pinctrl_tamper_gpios: tampergpiosgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_w1: w1grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..a3ea1b208462 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +#include +#include +#include + +/ { + model = "PHYTEC phyCORE-i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + gpio_leds_som: leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds_som>; + compatible = "gpio-leds"; + + led-phycore-green { + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + status = "disabled"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "okay"; + + eeprom@52 { + compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "disabled"; +}; + +&wdog1 { + fsl,suspend-in-wait; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 + >; + }; + + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = ; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2cgpiogrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts new file mode 100644 index 000000000000..cfc744f8fcad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-segin.dtsi" +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; + compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10", + "phytec,imx6ul-pcl063","fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts new file mode 100644 index 000000000000..607eddc5030f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-segin.dtsi" +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; + compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10", + "phytec,imx6ul-pcl063", "fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..ec042648bd98 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2016, 2020 PHYTEC Messtechnik + * Author: Christian Hemp + * Author: Stefan Riedmueller + */ + +/ { + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_backlight_en>; + pwms = <&pwm3 0 5000000 0>; + status = "disabled"; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&backlight_lcd>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_parallel_out>; + }; + }; + }; + + reg_backlight_en: regulator-backlight-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_en>; + regulator-name = "backlight-lcd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c1 { + edt_ft5406: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5406>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + wakeup-source; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat>; + status = "disabled"; + + port { + lcdif_parallel_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_backlight_en: bachlightengrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi new file mode 100644 index 000000000000..2f3fd32a1167 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + user-led1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..04477fd4b9a9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */ + >; + }; + + pinctrl_uart2_bt: uart2grp-bt { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059 + >; + }; + + pinctrl_usdhc2_wl: usdhc2grp-wl { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>; + uart-has-rtscts; + status = "disabled"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi new file mode 100644 index 000000000000..38ea4dcfa228 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "disabled"; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + + reg_can1_en: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&princtrl_flexcan1_en>; + regulator-name = "Can"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&tlv320>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; + +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_adc1_vref_3v3>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_en>; + status = "disabled"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "disabled"; +}; + +&i2c1 { + tlv320: codec@18 { + compatible = "ti,tlv320aic3007"; + #sound-dai-cells = <0>; + reg = <0x18>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + status = "disabled"; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "disabled"; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <19200000>; + fsl,sai-mclk-direction-output; + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "disabled"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + disable-wp; + status = "disabled"; +}; + +&iomuxc { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1 { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + princtrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts new file mode 100644 index 000000000000..5a74c7f68eb6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and DWARF baseboard"; + compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul"; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: audio-codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts new file mode 100644 index 000000000000..09f7ffa9ad8c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; + compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + status = "okay"; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts new file mode 100644 index 000000000000..6cd7d5877d20 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and PI baseboard"; + compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi new file mode 100644 index 000000000000..4ffe99ed55ca --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + /* Will be filled by the bootloader */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + chosen { + stdout-path = &uart6; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 6 0>; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + panel { + compatible = "vxt,vl050-8048nt-c01"; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + /* VDD_ARM_SOC_IN*/ + sw1b_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* DRAM */ + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + /* DRAM */ + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { /* Wifi SDIO */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_brcm>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ + MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* LCD reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h new file mode 100644 index 000000000000..380d2db13a9b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h @@ -0,0 +1,959 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX6UL_PINFUNC_H +#define __DTS_IMX6UL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 + +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 + +#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 +#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 +#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 +#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 +#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 +#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 +#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 +#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 +#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 +#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 +#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 +#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 +#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 +#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 +#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 +#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 +#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 +#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 +#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 +#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 +#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 +#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 +#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 +#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 +#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 +#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 +#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 +#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 +#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 +#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 +#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 +#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 +#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 +#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 +#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 +#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 +#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 +#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 +#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 +#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 +#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 +#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 +#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 +#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 +#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 +#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 +#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 +#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 +#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 +#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 +#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 +#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 +#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 +#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 +#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 +#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 +#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 +#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 +#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 +#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 +#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 +#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 +#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 +#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 +#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 +#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 +#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 +#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 +#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 +#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 +#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 +#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 +#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 +#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 +#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 +#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 +#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 +#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 +#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 +#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 +#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 +#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 +#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 +#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 +#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 +#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 +#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 +#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 +#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 +#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 +#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 +#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 +#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 +#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 +#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 +#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 +#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 +#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 +#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 +#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 +#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 +#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 +#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 +#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 +#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 +#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 +#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 +#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 +#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 +#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 +#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 +#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 +#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 +#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 +#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 +#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 +#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 +#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 +#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 +#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 +#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 +#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 +#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 +#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 +#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 +#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 +#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 +#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 +#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 +#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 +#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 +#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 +#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 +#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 +#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 +#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 +#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 +#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 +#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 +#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 +#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 +#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 +#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 +#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 +#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 +#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 +#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 +#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 +#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 +#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 +#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 +#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 +#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 +#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 +#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 +#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 +#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 +#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 +#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 +#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 +#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 +#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 +#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 +#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 +#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 +#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 +#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 +#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 +#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 +#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 +#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 +#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 +#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 +#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 +#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 +#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 +#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 +#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 +#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 +#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 +#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 +#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 +#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 +#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 +#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 +#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 +#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 +#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 +#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 +#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 +#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 +#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 +#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 +#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 +#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 +#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 +#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 +#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 +#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 +#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 +#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 +#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 +#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 +#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 +#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 +#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 +#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 +#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 +#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 +#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 +#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 +#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 +#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 +#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 +#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 +#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 +#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 +#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 +#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 +#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 +#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 +#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 +#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 +#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 +#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 +#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 +#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 +#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 +#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 +#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 +#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 +#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 +#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 +#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 +#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 +#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 +#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 +#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 +#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 +#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 +#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 +#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 +#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 +#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 +#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 +#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 +#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 +#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 +#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 +#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 +#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 +#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 +#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 +#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 +#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 +#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 +#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 +#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 +#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 +#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 +#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 +#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 +#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 +#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 +#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 +#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 +#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 +#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 +#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 +#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 +#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 +#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 +#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 +#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 +#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 +#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 +#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 +#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 +#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 +#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 +#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 +#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 +#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 +#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 +#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 +#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 +#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 +#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 +#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 +#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 +#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 +#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 +#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 +#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 +#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 +#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 +#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 +#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 +#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 +#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 +#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 +#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 +#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 +#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 +#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 +#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 +#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 +#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 +#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 +#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 +#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 +#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 +#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 +#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 +#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 +#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 +#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 +#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 +#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 +#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 +#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 +#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 +#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 +#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 +#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 +#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 +#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 +#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 +#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 +#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 +#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 +#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 +#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 +#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 +#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 +#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 +#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 +#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 +#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 +#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 +#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 +#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 +#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 +#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 +#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 +#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 +#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 +#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 +#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 +#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 +#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 +#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 +#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 +#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 +#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 +#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 +#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 +#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 +#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 +#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 +#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 +#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 +#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 +#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 +#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 +#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 +#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 +#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 +#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 +#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 +#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 +#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 +#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 +#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 +#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 +#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 +#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 +#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 +#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 +#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 +#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 +#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 +#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 +#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 +#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 +#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 +#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 +#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 +#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 +#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 +#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 +#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 +#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 +#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 +#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 +#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 +#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 +#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 +#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 +#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 + +#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts new file mode 100644 index 000000000000..c3c50f51a5a8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include + +/ { + model = "Protonic PRTI6G Board"; + compatible = "prt,prti6g", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + clock_ksz8081_in: clock-ksz8081-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_ksz8081_out: clock-ksz8081-out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet1_ref_pad"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v2: regulator-3v2 { + compatible = "regulator-fixed"; + regulator-name = "3v2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad"; + assigned-clocks = <&clks IMX6UL_CLK_ENET1_REF_SEL>; + assigned-clock-parents = <&clock_ksz8081_out>; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth1>; + phy-mode = "rmii"; + phy-handle = <&rmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + clocks = <&clock_ksz8081_in>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3v2>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + /* SR */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + /* TERM */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + /* nSMBALERT */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + /* SR */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0 + >; + }; + + pinctrl_eth1: eth1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000 + /* PHY ENET1_RST */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 + /* PHY ENET1_IRQ */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW revision detect */ + /* REV_ID0 */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + /* REV_ID1 */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 + /* REV_ID2 */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + /* REV_ID3 */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 + /* BOARD_ID0 */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 + /* BOARD_ID1 */ + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 + /* BOARD_ID2 */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 + /* BOARD_ID3 */ + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 + /* Safety controller IO */ + /* WAKE_SC */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 + /* PROGRAM_SC */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 + /* SD1 CD */ + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi new file mode 100644 index 000000000000..57e647fc3237 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULxL + * - TQMa6ULLx + * - TQMa6ULLxL + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <6250>; + /* not used */ + }; + + reg_sw1b_core: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sw3_ddr: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + /* not used */ + }; + + reg_snvs_3v0: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vccsd: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + reg_v33_3v3: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vldo1_3v3: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo2: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vldo3: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo4: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + jc42_1a: eeprom-temperature@1a { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + m24c02_52: eeprom@52 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + read-only; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + /* + * PMIC & temperature sensor IRQ + * Both do currently not use IRQ + * potentially dangerous if used on baseboard + */ + pmic-int-hog { + gpio-hog; + gpios = <24 0>; + input; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <33000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz" , "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + + bus-width = <8>; + disable-wp; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_recovery: i2c4recoverygrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 + >; + }; + + pinctrl_pmic: pmic { + fsl,pins = < + /* PMIC irq */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts new file mode 100644 index 000000000000..f2a5f17f312e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul1.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) + * and need to be disabled here again + */ +&can2 { + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&fec2 { + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&iomuxc { + pinctrl_enet1_mdc: enet1mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi new file mode 100644 index 000000000000..24192d012ef7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul-tqma6ul2.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM"; + compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * There are no module specific differences compared to TQMa6UL2, + * only external interfaces differ + */ + +/* + * Devices not available on i.MX6ULG1 and should not be enabled on + * mainboard level (again) + */ +&can2 { + status = "disabled"; +}; + +&csi { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 000000000000..0757df2b8f48 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi new file mode 100644 index 000000000000..e2e95dd92263 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2 SoM"; + compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..4b87e2dc70dc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi new file mode 100644 index 000000000000..5afb9046c202 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULLx + */ + +&m24c64_50 { + vcc-supply = <®_sw2>; +}; + +&m24c02_52 { + vcc-supply = <®_sw2>; +}; + +®_sw2 { + regulator-boot-on; + regulator-always-on; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_sw2>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts new file mode 100644 index 000000000000..8c2f3df79b47 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-tx6ul.dtsi" + +/ { + model = "Ka-Ro electronics TXUL-0010 Module"; + compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; + + aliases { + /delete-property/ mmc1; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts new file mode 100644 index 000000000000..d82698e7d50f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2015 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-tx6ul.dtsi" + +/ { + model = "Ka-Ro electronics TXUL-0011 Module"; + compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + }; +}; + +&gpmi { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + fsl,wp-controller; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts new file mode 100644 index 000000000000..92ac0edcb608 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts @@ -0,0 +1,271 @@ +/* + * Copyright 2015 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-tx6ul.dtsi" + +/ { + model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard"; + compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; + + aliases { + lcdif-24bit-pins-a = &pinctrl_disp0_3; + mmc0 = &usdhc1; + /delete-property/ mmc1; + serial2 = &uart3; + serial4 = &uart5; + }; + /delete-node/ sound; +}; + +&can1 { + xceiver-supply = <®_3v3>; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + status = "disabled"; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + phy-supply = <®_3v3_etn>; + phy-handle = <&etnphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + etnphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy0_int>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + etnphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy1_int>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + }; +}; + +&i2c_gpio { + status = "disabled"; +}; + +&i2c2 { + /delete-node/ codec@a; + /delete-node/ touchscreen@48; + + rtc: rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&kpp { + status = "disabled"; +}; + +&lcdif { + pinctrl-0 = <&pinctrl_disp0_3>; +}; + +®_usbotg_vbus{ + status = "disabled"; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + /delete-property/ cd-gpios; + cap-sdio-irq; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + /delete-property/ uart-has-rtscts; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + /delete-property/ uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "disabled"; /* conflicts with LCDIF */ +}; + +&iomuxc { + hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */ + >; + }; + + pinctrl_disp0_3: disp0grp-3 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 + /* LCD_DATA08..09 not wired */ + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 + /* LCD_DATA16..17 not wired */ + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi new file mode 100644 index 000000000000..6bd90473050b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -0,0 +1,947 @@ +/* + * Copyright 2015 Lothar Waßmann + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + aliases { + can0 = &can2; + can1 = &can1; + display = &display; + i2c0 = &i2c2; + i2c1 = &i2c_gpio; + i2c2 = &i2c1; + i2c3 = &i2c3; + i2c4 = &i2c4; + lcdif-23bit-pins-a = &pinctrl_disp0_1; + lcdif-24bit-pins-a = &pinctrl_disp0_2; + pwm0 = &pwm5; + reg-can-xcvr = ®_can_xcvr; + serial2 = &uart5; + serial4 = &uart3; + spi0 = &ecspi2; + spi1 = &spi_gpio; + stk5led = &user_led; + usbh1 = &usbotg2; + usbotg = &usbotg1; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + + clocks { + mclk: mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_rst>; + enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_lcd_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + i2c_gpio: i2c-gpio { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio>; + gpios = < + &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ + &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ + >; + clock-frequency = <400000>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + status = "disabled"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led: led-user { + label = "Heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3_etn: regulator-3v3etn { + compatible = "regulator-fixed"; + regulator-name = "3V3_ETN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy_power>; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-canxcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_xcvr>; + gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; + }; + + reg_lcd_pwr: regulator-lcdpwr { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwr>; + gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + spi_gpio: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi_gpio>; + mosi-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + num-chipselects = <2>; + cs-gpios = < + &gpio1 29 GPIO_ACTIVE_HIGH + &gpio1 10 GPIO_ACTIVE_HIGH + >; + status = "disabled"; + }; + + sound { + compatible = "karo,imx6ul-tx6ul-sgtl5000", + "simple-audio-card"; + simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = < + &gpio1 29 GPIO_ACTIVE_HIGH + &gpio1 10 GPIO_ACTIVE_HIGH + >; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + phy-supply = <®_3v3_etn>; + phy-handle = <&etnphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + etnphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy0_int>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + etnphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy1_int>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + phy-supply = <®_3v3_etn>; + phy-handle = <&etnphy1>; + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + polytouch: polytouch@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + touchscreen: touchscreen@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_NONE>; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <660>; + wakeup-source; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + /* sample keymap */ + /* row/col 0..3 are mapped to KPP row/col 4..7 */ + linux,keymap = < + MATRIX_KEY(4, 4, KEY_POWER) + MATRIX_KEY(4, 5, KEY_KP0) + MATRIX_KEY(4, 6, KEY_KP1) + MATRIX_KEY(4, 7, KEY_KP2) + MATRIX_KEY(5, 4, KEY_KP3) + MATRIX_KEY(5, 5, KEY_KP4) + MATRIX_KEY(5, 6, KEY_KP5) + MATRIX_KEY(5, 7, KEY_KP6) + MATRIX_KEY(6, 4, KEY_KP7) + MATRIX_KEY(6, 5, KEY_KP8) + MATRIX_KEY(6, 6, KEY_KP9) + >; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + lcd-supply = <®_lcd_pwr>; + display = <&display>; + status = "okay"; + + display: disp0 { + bits-per-pixel = <32>; + bus-width = <24>; + status = "okay"; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbotg_vbus>; + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ + >; + }; + + pinctrl_disp0_1: disp0grp-1 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ + /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 + >; + }; + + pinctrl_disp0_2: disp0grp-2 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_etnphy_power: etnphy-pwrgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ + >; + }; + + pinctrl_etnphy0_int: etnphy-intgrp-0 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ + >; + }; + + pinctrl_etnphy0_rst: etnphy-rstgrp-0 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ + >; + }; + + pinctrl_etnphy1_int: etnphy-intgrp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ + >; + }; + + pinctrl_etnphy1_rst: etnphy-rstgrp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan_xcvr: flexcan-xcvrgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c_gpio: i2c-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 + >; + }; + + pinctrl_lcd_pwr: lcd-pwrgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ + >; + }; + + pinctrl_lcd_rst: lcd-rstgrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ + >; + }; + + pinctrl_spi_gpio: spi-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ + >; + }; + + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart1_rtscts: uart1-rtsctsgrp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 + MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart2_rtscts: uart2-rtsctsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 + MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart5_rtscts: uart5-rtsctsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 + >; + }; + + pinctrl_usbh1_oc: usbh1-ocgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ + >; + }; + + pinctrl_usbotg_oc: usbotg-ocgrp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 + >; + }; + + pinctrl_usdhc1_cd: usdhc1cdgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 + /* eMMC RESET */ + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi new file mode 100644 index 000000000000..0174f3edbd16 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -0,0 +1,1124 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2015 Freescale Semiconductor, Inc. + +#include +#include +#include +#include +#include "imx6ul-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + sai1 = &sai1; + sai2 = &sai2; + sai3 = &sai3; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <696000000>; + clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; + operating-points = + /* kHz uV */ + <696000 1275000>, + <528000 1175000>, + <396000 1025000>, + <198000 950000>; + fsl,soc-operating-points = + /* KHz uV */ + <696000 1275000>, + <528000 1175000>, + <396000 1175000>, + <198000 1175000>; + clocks = <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL2_BUS>, + <&clks IMX6UL_CLK_PLL2_PFD2>, + <&clks IMX6UL_CA7_SECONDARY_SEL>, + <&clks IMX6UL_CLK_STEP>, + <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", + "secondary_sel", "step", "pll1_sw", + "pll1_sys"; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + ckil: clock-cli { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = ; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x00a01000 0x1000>, + <0x00a02000 0x2000>, + <0x00a04000 0x2000>, + <0x00a06000 0x2000>; + }; + + dma_apbh: dma-controller@1804000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x01804000 0x2000>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6UL_CLK_APBHDMA>; + }; + + gpmi: nand-controller@1806000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01806000 0x2000>, <0x01808000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX6UL_CLK_GPMI_IO>, + <&clks IMX6UL_CLK_GPMI_APB>, + <&clks IMX6UL_CLK_GPMI_BCH>, + <&clks IMX6UL_CLK_GPMI_BCH_APB>, + <&clks IMX6UL_CLK_PER_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + ecspi1: spi@2008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI1>, + <&clks IMX6UL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI2>, + <&clks IMX6UL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI3>, + <&clks IMX6UL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI4>, + <&clks IMX6UL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart7: serial@2018000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02018000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART7_IPG>, + <&clks IMX6UL_CLK_UART7_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART1_IPG>, + <&clks IMX6UL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart8: serial@2024000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sai1: sai@2028000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; + reg = <0x02028000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_SAI1>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 35 24 0>, + <&sdma 36 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai2: sai@202c000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; + reg = <0x0202c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_SAI2>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 37 24 0>, + <&sdma 38 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@2030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; + reg = <0x02030000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_SAI3>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 39 24 0>, + <&sdma 40 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + asrc: asrc@2034000 { + compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; + reg = <0x2034000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; + }; + + tsc: tsc@2040000 { + compatible = "fsl,imx6ul-tsc"; + reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_ADC2>; + clock-names = "tsc", "adc"; + status = "disabled"; + }; + + pwm1: pwm@2080000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM1>, + <&clks IMX6UL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@2084000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM2>, + <&clks IMX6UL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@2088000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM3>, + <&clks IMX6UL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@208c000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM4>, + <&clks IMX6UL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + can1: can@2090000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAN1_IPG>, + <&clks IMX6UL_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1>; + status = "disabled"; + }; + + can2: can@2094000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAN2_IPG>, + <&clks IMX6UL_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2>; + status = "disabled"; + }; + + gpt1: timer@2098000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, + <&clks IMX6UL_CLK_GPT1_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, + <&iomuxc 16 33 16>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 65 29>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_GPIO5>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; + }; + + fec2: ethernet@20b4000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x020b4000 0x4000>; + interrupt-names = "int0", "pps"; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET2_REF_SEL>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref"; + fsl,num-tx-queues = <1>; + fsl,num-rx-queues = <1>; + fsl,stop-mode = <&gpr 0x10 4>; + fsl,magic-packet; + status = "disabled"; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG1>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = , + , + ; + + reg_3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + }; + + usbphy1: usbphy@20c9000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@20ca000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + status = "disabled"; + }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6ul-snvs-lpgpr"; + }; + }; + + epit1: epit@20d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@20d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@20dc000 { + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clks IMX6UL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@20e4000 { + compatible = "fsl,imx6ul-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + gpt2: timer@20e8000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_GPT2_BUS>, + <&clks IMX6UL_CLK_GPT2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", + "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pwm5: pwm@20f0000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM5>, + <&clks IMX6UL_CLK_PWM5>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@20f4000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM6>, + <&clks IMX6UL_CLK_PWM6>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@20f8000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM7>, + <&clks IMX6UL_CLK_PWM7>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@20fc000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020fc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM8>, + <&clks IMX6UL_CLK_PWM8>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + aips2: bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + crypto: crypto@2140000 { + compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_MEM>; + clock-names = "ipg", "aclk", "mem"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + fec1: ethernet@2188000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET1_REF_SEL>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref"; + fsl,num-tx-queues = <1>; + fsl,num-rx-queues = <1>; + fsl,stop-mode = <&gpr 0x10 3>; + fsl,magic-packet; + status = "disabled"; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + adc1: adc@2198000 { + compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ADC1>; + clock-names = "adc"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C3>; + status = "disabled"; + }; + + memory-controller@21b0000 { + compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; + }; + + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_EIM>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: efuse@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6ul-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6UL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + }; + + csi: csi@21c4000 { + compatible = "fsl,imx6ul-csi"; + reg = <0x021c4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "mclk"; + status = "disabled"; + }; + + lcdif: lcdif@21c8000 { + compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x021c8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, + <&clks IMX6UL_CLK_LCDIF_APB>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + pxp: pxp@21cc000 { + compatible = "fsl,imx6ul-pxp"; + reg = <0x021cc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PXP>; + clock-names = "axi"; + }; + + qspi: spi@21e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6UL_CLK_QSPI>, + <&clks IMX6UL_CLK_QSPI>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + wdog3: watchdog@21e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + + uart2: serial@21e8000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART2_IPG>, + <&clks IMX6UL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@21ec000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART3_IPG>, + <&clks IMX6UL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@21f0000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART4_IPG>, + <&clks IMX6UL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART5_IPG>, + <&clks IMX6UL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c4: i2c@21f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C4>; + status = "disabled"; + }; + + uart6: serial@21fc000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021fc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART6_IPG>, + <&clks IMX6UL_CLK_UART6_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts new file mode 100644 index 000000000000..74aaa8a56a3d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx6ull.dtsi" +#include "imx6ul-14x14-evk.dtsi" + +/ { + model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + assigned-clock-rates = <320000000>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts new file mode 100644 index 000000000000..3e0897c3a296 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi new file mode 100644 index 000000000000..de4dc7c1a03a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + num-cs = <2>; + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */ + &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */ + >; +}; + +/* + * Following SODIMM Pins should not be accessed as GPIO on Aster board: + * 134 - AIN5_SCL (no connection) + * 127 - Voltage Level Translator OE# signal (IC11 and IC12) + * + * To configure GPIO to LED5, please disable FEC2 and uncomment the following: + * &iomuxc { + * pinctrl-names = "default"; + * pinctrl-0 = < + * &pinctrl_gpio1 + * &pinctrl_gpio2 + * &pinctrl_gpio3 + * &pinctrl_gpio4 + * &pinctrl_gpio6 - for non-WiFi modules only + * &pinctrl_gpio7 + * &pinctrl_gpio_aster + * >; + * + * pinctrl_gpio_aster: gpio-aster { + * fsl,pins = < + * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0 + * >; + * }; + * }; + */ + +&i2c1 { + status = "okay"; + + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts new file mode 100644 index 000000000000..919c0464d6cb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-emmc-aster", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts new file mode 100644 index 000000000000..61b93cb040c7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-emmc-eval", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..b9060c2f7977 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts new file mode 100644 index 000000000000..0ab71f2f5daa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-emmc-iris", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi new file mode 100644 index 000000000000..ea238525d5c0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx6ull-colibri.dtsi" + +/ { + aliases { + mmc0 = &usdhc2; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4-bit slot */ + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "SODIMM_89", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_140", + "SODIMM_59", + "SODIMM_142", + "SODIMM_144", + "SODIMM_133", + "SODIMM_146", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "SODIMM_81", + "SODIMM_94", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "SODIMM_93", + "", + "SODIMM_138", + "", + "SODIMM_105", + "SODIMM_127"; +}; + +/* NAND */ +&gpmi { + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7 + &pinctrl_gpmi_gpio>; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2emmc>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + bus-width = <8>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_module_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts new file mode 100644 index 000000000000..d6da984e518d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..692ef26fbab3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* fixed crystal dedicated to mcp2515 */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts new file mode 100644 index 000000000000..f6b31118be17 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..93649cad0cc0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull-colibri-iris.dtsi" + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + + +&usdhc1 { + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts new file mode 100644 index 000000000000..2a0d0fc3b9d6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi new file mode 100644 index 000000000000..f52f8b5ad8a6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&gpio1 { + /* + * uart25_tx_on turns the UART transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + * The same applies to uart1_tx_on. + */ + uart25_tx_on-hog { + gpio-hog; + gpios = <15 0>; + output-high; + }; +}; + +&gpio2 { + uart1_tx_on-hog { + gpio-hog; + gpios = <7 0>; + output-high; + }; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi new file mode 100644 index 000000000000..88901db255d6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull-colibri.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "SODIMM_89", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "SODIMM_81", + "SODIMM_94", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "SODIMM_93", + "", + "SODIMM_138", + "", + "SODIMM_105", + "SODIMM_127"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts new file mode 100644 index 000000000000..c7da5b41966f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-wifi-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts new file mode 100644 index 000000000000..917f5dbe64ba --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts new file mode 100644 index 000000000000..488da6df56fa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-wifi-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts new file mode 100644 index 000000000000..e63253254754 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-wifi-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi new file mode 100644 index 000000000000..db59ee6b1c86 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull-colibri.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + wifi_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_wifi_pdn>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "", + "", + "", + "", + "", + "", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "", + "", + "", + "", + "SODIMM_105"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio7>; + +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <25000000>; + mmc-pwrseq = <&wifi_pwrseq>; + no-1-8-v; + non-removable; + vmmc-supply = <®_module_3v3>; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi new file mode 100644 index 000000000000..fde8a19aac0f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull.dtsi" + +/ { + /* Ethernet aliases to ensure correct MAC addresses */ + aliases { + ethernet0 = &fec2; + ethernet1 = &fec1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + power-supply = <®_3v3>; + pwms = <&pwm4 0 5000000 1>; + status = "disabled"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_usbc_det>; + id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + label = "USBC"; + self-powered; + type = "micro"; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + key-wakeup { + debounce-interval = <10>; + gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vqmmc: regulator-sd1-vqmmc { + compatible = "regulator-gpio"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_reg_sd>; + regulator-always-on; + regulator-name = "+V3.3_1.8_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1 3300000 0x0>; + vin-supply = <®_module_3v3>; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed-clock"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; +}; + +&adc1 { + vref-supply = <®_module_3v3_avdd>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +/* Colibri SPI */ +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; +}; + +/* Ethernet */ +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2_sleep>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +/* NAND */ +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + status = "okay"; +}; + +/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + /* Use low frequency to compensate for the high pull-up values. */ + clock-frequency = <40000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + status = "disabled"; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "disabled"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +/* PWM */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +/* PWM */ +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; +}; + +/* PWM */ +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; +}; + +/* PWM */ +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; +}; + +&sdma { + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +/* Colibri UART_A */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + uart-has-rtscts; + fsl,dte-mode; +}; + +/* Colibri UART_B */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + fsl,dte-mode; +}; + +/* Colibri UART_C */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,dte-mode; +}; + +/* Colibri USBC */ +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + usb-role-switch; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Colibri USBH */ +&usbotg2 { + dr_mode = "host"; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + bus-width = <4>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ + disable-wp; + keep-power-in-suspend; + no-1-8-v; + vqmmc-supply = <®_sd1_vqmmc>; + wakeup-source; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ + >; + }; + + pinctrl_atmel_adap: atmeladapgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ + >; + }; + + pinctrl_atmel_conn: atmelconngrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ + >; + }; + + pinctrl_can_int: canintgrp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + + pinctrl_enet2_sleep: enet2-sleepgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 + MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_bl_on: gpioblongrp { + fsl,pins = < + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ + >; + }; + + pinctrl_gpio2: gpio2grp { /* Camera */ + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3grp { /* CAN2 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ + >; + }; + + pinctrl_gpio6: gpio6grp { /* Wifi pins */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ + >; + }; + + pinctrl_gpio7: gpio7grp { /* CAN1 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ + MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ + >; + }; + + /* + * With an eMMC instead of a raw NAND device the following pins + * are available at SODIMM pins. + */ + pinctrl_gpmi_gpio: gpmigpiogrp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ + MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ + MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ + MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ + MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ + MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ + >; + }; + + pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ + >; + }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ + MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ + >; + }; + + pinctrl_usbh_reg: usbhreggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 + + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 + >; + }; + + pinctrl_usdhc2emmc: usdhc2emmcgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_atmel_snvs_conn: atmelsnvsconngrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ + >; + }; + + pinctrl_snvs_gpio1: snvsgpio1grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ + >; + }; + + pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ + >; + }; + + pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 + >; + }; + + pinctrl_snvs_reg_sd: snvsregsdgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 + >; + }; + + pinctrl_snvs_usbc_det: snvsusbcdetgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 + >; + }; + + pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ + >; + }; + + pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ + >; + }; + + pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 + >; + }; + + pinctrl_snvs_wifi_pdn: snvswifipdngrp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts new file mode 100644 index 000000000000..b539975a872c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM) + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" +#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on DRC02"; + compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; +}; + +/* + * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. + * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1 + * node below. + */ +&can2 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "DRC02-In2", + "", "", "", "", + "", "", "DHCOM-I", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "DRC02-HW0", "DRC02-HW1", "DHCOM-M", + "DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6ULL UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <25 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2", + "DHCOM-E", "", "", "DRC02-Out1", + "DRC02-In1", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* DHCOM I2C2 */ +&i2c1 { + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; + +&uart1 { + /delete-property/ uart-has-rtscts; + rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ + cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */ +}; + +/* Use UART as RS485 */ +&uart2 { + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts new file mode 100644 index 000000000000..b29713831a74 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-RTC-WBT-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * PDK2 PCB number: 516-400 or newer + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on Premium Developer Kit (2)"; + compatible = "dh,imx6ull-dhcom-pdk2", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* GPIO G */ + power-supply = <®_panel_3v3>; + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = ; + wakeup-source; + }; + + button-1 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = ; + wakeup-source; + }; + + button-2 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = ; + wakeup-source; + }; + + button-3 { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = ; + wakeup-source; + }; + }; + + led: led { + compatible = "gpio-leds"; + + /* + * Disable PDK2 LED5, because GPIO E is + * already used as touch interrupt. + */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; /* PDK2 LED5 */ + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; /* GPIO E */ + status = "disabled"; + }; + + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <6>; /* PDK2 LED6 */ + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; /* GPIO F */ + }; + + /* + * Disable PDK2 LED7, because GPIO H is + * already used for WiFi pin WL_REG_ON. + */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <7>; /* PDK2 LED7 */ + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* GPIO H */ + status = "disabled"; + }; + + /* + * Disable PDK2 LED8, because GPIO I is + * already used for BT pin BT_REG_ON. + */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <8>; /* PDK2 LED8 */ + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ + status = "disabled"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + power-supply = <®_panel_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + /* Filtered supply voltage */ + reg_pdk2_24v: regulator-pdk2-24v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <24000000>; + regulator-min-microvolt = <24000000>; + regulator-name = "24V_PDK2"; + }; + + /* PDK2 U35 */ + reg_pdk2_3v3: regulator-pdk2-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3V3_PDK2"; + vin-supply = <®_pdk2_24v>; + }; + + /* 560-200 U1 */ + reg_panel_3v3: regulator-panel-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3V3_PANEL"; + vin-supply = <®_pdk2_24v>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "sgtl5000"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + clocks = <&clk_ext_audio_codec>; + sound-dai = <&sgtl5000>; + }; + }; +}; + +/* DHCOM I2C1 */ +&i2c2 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_pdk2_3v3>; + VDDIO-supply = <®_pdk2_3v3>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + power-supply = <®_panel_3v3>; + }; +}; + +&lcdif { + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts new file mode 100644 index 000000000000..e4cc2223583a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" +#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on PicoITX"; + compatible = "dh,imx6ull-dhcom-picoitx", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + }; + }; +}; + +&fec1 { + phy-handle = <&mdio1_phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mdio1_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; + pinctrl-names = "default"; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + }; +}; + +&fec2 { + status = "disabled"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "PicoITX-HW2", "PicoITX-HW1", "DHCOM-M", + "PicoITX-HW0", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2", + "PicoITX-In1", "", "", "PicoITX-Out1", + "DHCOM-G", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi new file mode 100644 index 000000000000..040421f9c970 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + */ + +/* + * Special SoM configuration: SD card + * + * Enabled: Micro SD card on module or + * external SD card via DHCOM depends on hardware variant + * GPIO H and GPIO I will be available + * DHCOM UART2 will be available + * Disabled: WiFi and BT + */ + +/* + * To use usdhc1 as SD card, the WiFi node must be deleted. + * BT is also not available, so remove BT from the UART node. + */ +/delete-node/ &brcmf; +/delete-node/ &bluetooth; + +/ { + aliases { + mmc1 = &usdhc1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +/* Micro SD card on module or external SD card via DHCOM */ +&usdhc1 { + /delete-property/ #address-cells; + /delete-property/ #size-cells; + /delete-property/ keep-power-in-suspend; + /delete-property/ mmc-pwrseq; + /delete-property/ non-removable; + /delete-property/ wakeup-source; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ + + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi new file mode 100644 index 000000000000..830b5a5064f2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi @@ -0,0 +1,631 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + */ + +#include "imx6ull-dhcor-som.dtsi" + +/ { + aliases { + /delete-property/ spi2; + /delete-property/ spi3; + i2c0 = &i2c2; + i2c1 = &i2c1; + mmc2 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart6; /* DHCOM UART2, special hardware required */ + serial2 = &uart3; + serial3 = &uart2; /* Use BT UART always as ttymxc3 */ + serial4 = &uart4; + serial5 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_ext_3v3_ref: regulator-ext-3v3-ref { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3_REF"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg1-vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg2-vbus"; + }; + + /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */ + /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */ + }; +}; + +/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */ +&bluetooth { + shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&can1 { + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. + * Only if this pins are used as CAN interface enable it on board layer. + */ +&can2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; +}; + +/* DHCOM SPI1 */ +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * DHCOM SPI2 + * Special hardware required that uses the pins of FEC2. Therefore this SPI + * interface can only be used if FEC2 is disabled. + */ +&ecspi4 { + cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi4>; + pinctrl-names = "default"; +}; + +/* DHCOM ETH1 */ +&fec1 { + phy-handle = <&mdio2_phy0>; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DHCOM ETH2 */ +&fec2 { + phy-handle = <&mdio2_phy1>; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_fec2>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mdio2_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; + pinctrl-names = "default"; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + + mdio2_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>; + pinctrl-names = "default"; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "DHCOM-INT", + "", "", "", "", + "", "", "DHCOM-I", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + pinctrl-0 = <&pinctrl_spi1_switch + &pinctrl_dhcom_i &pinctrl_dhcom_int>; + pinctrl-names = "default"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "DHCOM-L", "DHCOM-K", "DHCOM-M", + "DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; + pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k + &pinctrl_dhcom_l &pinctrl_dhcom_m + &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q + &pinctrl_dhcom_r &pinctrl_dhcom_s + &pinctrl_dhcom_t &pinctrl_dhcom_u>; + pinctrl-names = "default"; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D", + "DHCOM-E", "", "", "DHCOM-F", + "DHCOM-G", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b + &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d + &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f + &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>; + pinctrl-names = "default"; +}; + +/* DHCOM I2C2 */ +&i2c1 { + rtc_i2c: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + /* TI ADC101C027 */ + adc@51 { + compatible = "ti,adc101c"; + reg = <0x51>; + vref-supply = <®_ext_3v3_ref>; + }; + + /* TI ADC101C027 */ + adc@52 { + compatible = "ti,adc101c"; + reg = <0x52>; + vref-supply = <®_ext_3v3_ref>; + }; + + /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +/* DHCOM I2C1 */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&lcdif { + pinctrl-0 = <&pinctrl_lcdif>; + pinctrl-names = "default"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; +}; + +&sai2 { + assigned-clock-rates = <320000000>; + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; +}; + +&tsc { + measure-delay-time = <0xffff>; + pinctrl-0 = <&pinctrl_tsc>; + pinctrl-names = "default"; + pre-charge-time = <0xfff>; + touchscreen-average-samples = <32>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +}; + +/* DHCOM UART1 */ +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * DHCOM UART2 (alternative) + * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2. + * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are + * removed from GPIO hog muxing. + */ +&uart6 { + pinctrl-0 = <&pinctrl_uart6>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + pinctrl-0 = <&pinctrl_usbotg1>; + pinctrl-names = "default"; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; /* Overcurrent pin is used for TSC */ + dr_mode = "host"; + pinctrl-0 = <&pinctrl_usbotg2>; + pinctrl-names = "default"; + tpl-support; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +/* WiFi on LGA */ +&usdhc1 { + mmc-pwrseq = <&usdhc1_pwrseq>; +}; + +/* eMMC on module */ +&usdhc2 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&iomuxc { + /* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */ + pinctrl_dhcom_i: dhcom-i-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_j: dhcom-j-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_k: dhcom-k-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_l: dhcom-l-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_m: dhcom-m-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_n: dhcom-n-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_o: dhcom-o-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_p: dhcom-p-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_q: dhcom-q-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_r: dhcom-r-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_s: dhcom-s-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_t: dhcom-t-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_u: dhcom-u-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_int: dhcom-int-grp { + fsl,pins = ; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_ecspi4: ecspi4-grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + /* FEC1 uses MDIO bus from FEC2 */ + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + >; + }; + + pinctrl_fec1_phy: fec1-phy-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */ + >; + }; + + pinctrl_fec2: fec2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_fec2_phy: fec2-phy-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdif-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_tsc: tsc-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6-grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg2: usbotg2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ + >; + }; +}; + +&iomuxc_snvs { + /* DHCOM GPIOs A..H */ + pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp { + fsl,pins = ; + }; + + pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */ + >; + }; + + pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts new file mode 100644 index 000000000000..047f7b2d8526 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 DH electronics GmbH + * Copyright (C) 2023 Marantec electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCR-iMX6ULL-C080-R051-SPI-WBT-I-01LG + * DHCOR PCB number: 578-200 or newer + * maveo box PCB number: 525-200 or newer + */ + +/dts-v1/; + +#include "imx6ull-dhcor-som.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOR on maveo box"; + compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som", + "fsl,imx6ull"; + + aliases { + mmc2 = &usdhc2; + spi0 = &ecspi4; + spi3 = &ecspi1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg1-vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg2-vbus"; + }; + + /* WiFi pin WL_REG_ON is connected to GPIO 5.9 */ + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; +}; + +/* BT pin BT_REG_ON is connected to GPIO 1.18 */ +&bluetooth { + shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; +}; + +/* X10 connector */ +&ecspi4 { + cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi4>; + pinctrl-names = "default"; + status = "okay"; + + spidev@0 { + compatible = "dh,dhcom-board"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <54000000>; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "BUTTON-USER", "", "", + "BUTTON-RESET", "", "", "", + "", "", "", "", + "", "", "BT-REG-ON", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "PSOC-GPIO-1", "", "", "X10-12", + "X10-10", "PSOC-GPIO-2", "PSOC-GPIO-3", "", + "X10-11", "X10-9", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "DHCOR-HW0", "DHCOR-HW1", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "MAVEO-BOX-HW0", "LED-G", "MAVEO-BOX-VAR1", + "MAVEO-BOX-VAR0", "MAVEO-BOX-HW1", "MAVEO-BOX-HW2", "LED-B", + "LED-R", "", "", "", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "PSOC-SWD-IO", "PSOC-SWD-CLK", "PSOC-RESET", "ZIGBEE-PROG", + "ZIGBEE-RESET", "", "PSOC-PWR-FAIL-OUT", "NFC-ENABLE", + "NFC-IRQ", "WL-REG-ON", "DHCOR-BOOT-M0", "DHCOR-BOOT-M1", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* Console UART */ +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* BT on LGA */ +&uart2 { + pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt_gpio>; +}; + +/* Zigbee UART */ +&uart3 { + pinctrl-0 = <&pinctrl_uart3 &pinctrl_snvs_zigbee_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; /* Overcurrent pin isn't connected */ + dr_mode = "otg"; + hnp-disable; + pinctrl-0 = <&pinctrl_usbotg1>; + pinctrl-names = "default"; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; /* Overcurrent pin isn't connected */ + dr_mode = "host"; + pinctrl-0 = <&pinctrl_usbotg2>; + pinctrl-names = "default"; + tpl-support; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +/* WiFi on LGA */ +&usdhc1 { + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&pinctrl_usdhc1_wifi &pinctrl_snvs_wifi_gpio>; +}; + +/* eMMC */ +&usdhc2 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_maveo_box>; + pinctrl-names = "default"; + + pinctrl_hog_maveo_box: hog-maveo-box-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 /* BUTTON_USER */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x120b0 /* BUTTON_RESET */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0 /* LED_G */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0 /* LED_B */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0 /* LED_R */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x400120b0 /* X10_9 */ + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x400120b0 /* X10_10 */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x400120b0 /* X10_11 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x400120b0 /* X10_12 */ + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x400120b0 /* PSOC_GPIO_1 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x400120b0 /* PSOC_GPIO_2 */ + MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x400120b0 /* PSOC_GPIO_3 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x120b0 /* MAVEO_BOX_HW0 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x120b0 /* MAVEO_BOX_HW1 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x120b0 /* MAVEO_BOX_HW2 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x120b0 /* MAVEO_BOX_VAR0 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x120b0 /* MAVEO_BOX_VAR1 */ + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x120b0 /* DHCOR_HW0 */ + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x120b0 /* DHCOR_HW1 */ + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x120b0 + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x120b0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x120b0 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x120b0 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x120b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x120b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x120b0 + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x120b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x120b0 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x120b0 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x120b0 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x120b0 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x120b0 + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x120b0 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x120b0 + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x120b0 + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x120b0 + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x120b0 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x120b0 + >; + }; + + pinctrl_bt_gpio: bt-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0 /* BT_REG_ON */ + >; + }; + + pinctrl_ecspi4: ecspi4-grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x120b0 /* USB_OTG1_PWR */ + >; + }; + + pinctrl_usbotg2: usbotg2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x120b0 /* USB_OTG2_PWR */ + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ + >; + }; +}; + +&iomuxc_snvs { + pinctrl-0 = <&pinctrl_snvs_hog_maveo_box>; + pinctrl-names = "default"; + + pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0 /* PSOC_SWD_IO */ + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0 /* PSOC_SWD_CLK */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0 /* PSOC_RESET */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x400120b0 /* PSOC_PWR_FAIL_OUT */ + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0 /* NFC_ENABLE */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0 /* NFC_IRQ */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x120b0 /* DHCOR_BOOT_M0 */ + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x120b0 /* DHCOR_BOOT_M1 */ + >; + }; + + pinctrl_snvs_wifi_gpio: snvs-wifi-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0 /* WL_REG_ON */ + >; + }; + + pinctrl_snvs_zigbee_gpio: snvs-zigbee-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0 /* ZIGBEE_PROG */ + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0 /* ZIGBEE_RESET */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi new file mode 100644 index 000000000000..a386c1e9bed3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + */ + +#include +#include +#include +#include +#include +#include "imx6ull.dtsi" + +/ { + aliases { + /delete-property/ mmc0; + /delete-property/ mmc1; + }; + + memory@80000000 { + /* Appropriate memory size will be filled by U-Boot */ + reg = <0x80000000 0>; + device_type = "memory"; + }; +}; + +&cpu0 { + /* + * Due to the design as a solderable SOM, there are no capacitors + * below the SoC, therefore higher voltages are required. + */ + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1250000 /* Voltage increased */ + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1250000 + 792000 1250000 /* Voltage increased */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&gpio1 { + pinctrl-0 = <&pinctrl_spi1_switch>; + pinctrl-names = "default"; + /* + * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the + * DHCOM SPI1 interface or accessing the SPI bootflash. Both using + * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses + * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins + * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for + * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they + * are used for the bus interface to the SPI bootflash. The GPIOs are + * disconnected by a buffer which is also controlled via the pin + * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a + * special case and is disabled by setting GPIO 1.9 to high. + */ + spi1-switch-hog { + gpio-hog; + gpios = <9 0>; + output-high; + line-name = "spi1-switch"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9061"; + reg = <0x58>; + + onkey { + compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; + status = "disabled"; + }; + + regulators { + vdd_soc_in_1v4: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <1400000>; + regulator-name = "vdd_soc_in_1v4"; + }; + + vcc_3v3: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + }; + + /* + * The current DRR3 memory can be supplied with a + * voltage of either 1.35V or 1.5V. For reasons of + * backward compatibility to only 1.5V DDR3 memory, + * the voltage is set to 1.5V. + */ + vcc_ddr_1v35: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "vcc_ddr_1v35"; + }; + + vcc_2v5: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "vcc_2v5"; + }; + + vdd_snvs_in_3v3: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vdd_snvs_in_3v3"; + }; + + vcc_1v8: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + }; + + vcc_1v2: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "vcc_1v2"; + }; + }; + + thermal { + compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; + status = "disabled"; + }; + + watchdog { + compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog"; + status = "disabled"; + }; + }; +}; + +&ocotp { + /* Don't get write access by default */ + read-only; +}; + +®_arm { + vin-supply = <&vdd_soc_in_1v4>; +}; + +®_soc { + vin-supply = <&vdd_soc_in_1v4>; +}; + +/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */ +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + /* + * Actually, the maximum speed of the chip is 4MBdps, but there are + * limitations that prevent this speed. It hasn't yet been figured out + * what the reason for this is. Currently, the maximum speed of 3MBdps + * can be used without any problems. If the limitation can be overcome, + * the speed can be increased accordingly. + */ + bluetooth: bluetooth { + compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */ + max-speed = <3000000>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_3v3>; + }; +}; + +/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */ +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + pinctrl-0 = <&pinctrl_usdhc1_wifi>; + pinctrl-names = "default"; + wakeup-source; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */ + reg = <1>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + + pinctrl_spi1_switch: spi1-switch-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1_wifi: usdhc1-wifi-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts new file mode 100644 index 000000000000..a152eeb78e88 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; + +#include +#include +#include "imx6ull.dtsi" + +/ { + model = "JOZ Access Point"; + compatible = "joz,jozacp", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + /* On board name LED_RGB1 */ + led-controller-1 { + compatible = "pwm-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + pwms = <&pwm1 0 10000000 0>; + max-brightness = <255>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + pwms = <&pwm3 0 10000000 0>; + max-brightness = <255>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + pwms = <&pwm5 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* On board name LED_RGB2 */ + led-controller-2 { + compatible = "pwm-leds"; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + pwms = <&pwm2 0 10000000 0>; + max-brightness = <255>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <4>; + pwms = <&pwm4 0 10000000 0>; + max-brightness = <255>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; + pwms = <&pwm6 0 10000000 0>; + max-brightness = <255>; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v0>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vbus: regulator-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vbus>; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_vbus>; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_3v3>; + bus-width = <8>; + no-1-8-v; + non-removable; + cap-mmc-hw-reset; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sd; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW Revision */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + + /* HW ID */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 + + /* Digital inputs */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000 + + /* Isolated outputs */ + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010 + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 + MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0 + MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_vbus: vbus0grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_hog>; + + pinctrl_snvs_hog: snvs-hog-grp { + fsl,pins = < + /* Digital outputs */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020 + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020 + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020 + + /* Digital outputs fault feedback */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000 + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts new file mode 100644 index 000000000000..fa016465cdbc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ull-kontron-sl.dtsi" +#include "imx6ul-kontron-bl-common.dtsi" + +/ { + model = "Kontron BL i.MX6ULL (N641X S)"; + compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi new file mode 100644 index 000000000000..93f10eb3494f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ull.dtsi" +#include "imx6ul-kontron-sl-common.dtsi" + +/ { + model = "Kontron SL i.MX6ULL (N641X SOM)"; + compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts new file mode 100644 index 000000000000..79cc45728cd2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-myir-mys-6ulx.dtsi" + +/ { + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; + compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull"; +}; + +&gpmi { + fsl,use-minimum-ecc; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi new file mode 100644 index 000000000000..d03694feaf5c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +#include +#include +#include + +/ { + model = "MYiR MYS-6ULX Single Board Computer"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vdd_5v>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_vdd_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_vdd_3v3>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_vdd_3v3>; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi new file mode 100644 index 000000000000..155f941f2811 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2019 Armadeus Systems + +#include "imx6ull.dtsi" +#include "imx6ul-imx6ull-opos6ul.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts new file mode 100644 index 000000000000..198fdb72641b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2019 Armadeus Systems + +/dts-v1/; +#include "imx6ull-opos6ul.dtsi" +#include "imx6ul-imx6ull-opos6uldev.dtsi" + +/ { + model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board"; + compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull"; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tamper_gpios>; + + pinctrl_tamper_gpios: tampergpiosgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_w1: w1grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..56cd16e5a77f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-phycore-som.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 ULL"; + compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +&iomuxc { + /delete-node/ gpioledssomgrp; +}; + +&iomuxc_snvs { + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts new file mode 100644 index 000000000000..8e2a4c5d7765 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" +#include "imx6ull-phytec-segin.dtsi" +#include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; + compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10", + "phytec,imx6ull-pcl063","fsl,imx6ull"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts new file mode 100644 index 000000000000..1d7362b5ac91 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" +#include "imx6ull-phytec-segin.dtsi" +#include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; + compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts new file mode 100644 index 000000000000..4bcbae024d8d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" +#include "imx6ull-phytec-segin.dtsi" +#include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; + compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +&adc1 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..06bb7f327780 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin-peb-av-02.dtsi" + +&iomuxc { + /delete-node/ edtft5406grp; + /delete-node/ stmpegrp; +}; + +&iomuxc_snvs { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi new file mode 100644 index 000000000000..ff08d95a1aa2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" + +&iomuxc { + /delete-node/ gpio_keysgrp; +}; + +&iomuxc_snvs { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..df25814a3371 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" + +&iomuxc { + /delete-node/ wlgrp; +}; + +&iomuxc_snvs { + pinctrl_wl: wlgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi new file mode 100644 index 000000000000..e287a0453b5f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 ULL"; + compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull"; +}; + +&iomuxc { + /delete-node/ flexcan1engrp; + /delete-node/ rtcintgrp; +}; + +&iomuxc_snvs { + princtrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..ea627638e40c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h new file mode 100644 index 000000000000..54cfe72295aa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H +#define __DTS_IMX6ULL_PINFUNC_SNVS_H +/* + * The pin function ID is a tuple of + * + */ +#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 +#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h new file mode 100644 index 000000000000..7328d4ef8559 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_H +#define __DTS_IMX6ULL_PINFUNC_H + +#include "imx6ul-pinfunc.h" +/* + * The pin function ID is a tuple of + * + */ +/* signals common for i.MX6UL and i.MX6ULL */ +#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 +#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 +#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 +#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 +#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 + +/* signals for i.MX6ULL only */ +#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 +#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 +#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 +#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 +#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi new file mode 100644 index 000000000000..3fdece5bd31f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi @@ -0,0 +1,852 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +/dts-v1/; + +#include +#include +#include +#include "imx6ull.dtsi" + +/ { + aliases { + mmc0 = &usdhc2; /* eMMC */ + }; + + chosen { + stdout-path = &uart4; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&pinctrl_emmc_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + }; + + reg_dcdc_3v3: regulator-dcdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "dcdc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "ldo-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_status_leds>; + + led-1 { + function = LED_FUNCTION_BOOT; + color = ; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + + led-2 { + function = LED_FUNCTION_PROGRAMMING; + color = ; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_motor + &pinctrl_adc_cp + &pinctrl_adc_pp>; + vref-supply = <&vgen1_reg>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <3>; + cs-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH + &gpio3 2 GPIO_ACTIVE_HIGH + &gpio3 4 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + num-cs = <1>; + cs-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 + &pinctrl_enet1_phy_rst + &pinctrl_enet_mdio>; + phy-supply = <®_dcdc_3v3>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-handle = <ðphy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy_int>; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + max-speed = <100>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "CP_INVERT", + "", + "", /* 15 */ + "", + "", + "", + "MOTOR_1_FAULT_N", + "", /* 20 */ + "", + "ROTARY_SWITCH_1_2_N", + "ROTARY_SWITCH_1_4_N", + "ROTARY_SWITCH_1_8_N", + "MOTOR_2_FAULT_N"; /* 25 */ +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "EXT_GPIO", + "MOTOR_1_DRIVER_IN1_N", + "MOTOR_1_DRIVER_IN2", + "MOTOR_2_DRIVER_IN1", + "STM32_BOOT0", /* 10 */ + "STM32_RST_N", + "RELAY_1_ENABLE", + "RELAY_2_ENABLE", + "", + "", /* 15 */ + "QCA700X_MAINS_BOOTLOADER_N", + "QCA700X_CP_RST_N", + "QCA700X_CP_BOOTLOADER_N", + "", + "DIGITAL_OUT_1", /* 20 */ + "DIGITAL_OUT_2", + "DIGITAL_OUT_3", + "DIGITAL_OUT_4", + "DIGITAL_OUT_5", + "DIGITAL_OUT_6", /* 25 */ + "ROTARY_SWITCH_2_8_N", + "ROTARY_SWITCH_2_4_N", + "ROTARY_SWITCH_2_2_N"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "BOARD_VARIANT_1", + "BOARD_VARIANT_2", + "BOARD_VARIANT_0", /* 15 */ + "BOARD_VARIANT_3", + "", + "ROTARY_SWITCH_2_1_N", + "", + "DIGITAL_IN_5", /* 20 */ + "", + "", + "DIGITAL_IN_6", + "", + "DIGITAL_IN_1", /* 25 */ + "DIGITAL_IN_2", + "DIGITAL_IN_4", + "DIGITAL_IN_3"; + + pmic-int-hog { + gpio-hog; + gpios = <19 0>; + input; + }; +}; + +&gpio5 { + gpio-line-names = "ROTARY_SWITCH_1_1_N", /* 0 */ + "", + "RELAY_2_SENSE", + "RELAY_1_SENSE", + "", + "", /* 5 */ + "", + "QCA700X_MAINS_RST_N", + "MOTOR_2_DRIVER_IN2", + "", + "CP_POSITIVE_PEAK_RST", /* 10 */ + "CP_NEGATIVE_PEAK_RST"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3001: pmic@8 { + compatible = "fsl,pfuze3001"; + reg = <0x08>; + + regulators { + sw1_reg: sw1 { + regulator-name = "SW1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-name = "VSNVS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-name = "VLDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-name = "VLDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-name = "VCCSD"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-name = "V33"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-name = "VLDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-name = "VLDO4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + onewire@18 { + compatible = "maxim,ds2484"; + reg = <0x18>; + }; + + accelerometer@19 { + compatible = "st,iis328dq", "st,h3lis331dl-accel"; + reg = <0x19>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accelerometer_int1_snvs>; + vdd-supply = <®_dcdc_3v3>; + vddio-supply = <®_dcdc_3v3>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_var + &pinctrl_digital_input + &pinctrl_digital_output + &pinctrl_gpio_motor + &pinctrl_hog_pins + &pinctrl_rotary_switch1 + &pinctrl_rotary_switch2>; + + pinctrl_adc_cp: adc-cpgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_adc_motor: adc-motorgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_adc_pp: adc-ppgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0 + >; + }; + + pinctrl_board_var: board-vargrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__GPIO4_IO15 0xb0 + MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0xb0 + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0xb0 + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0 + >; + }; + + pinctrl_digital_input: digital-inputgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0xb0 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0xb0 + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0xb0 + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0xb0 + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0xb0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0xb0 + >; + }; + + pinctrl_digital_output: digital-outputgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400000b0 + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400000b0 + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400000b0 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400000b0 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400000b0 + MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400000b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0xb0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xb0 + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x10b0 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x10b0 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x10b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0 + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0 + >; + }; + + pinctrl_emmc_rst: emmc-rstgrp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x400010b0 + >; + }; + + pinctrl_enet_mdio: enet-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10b0 + >; + }; + + pinctrl_enet1_phy_int: enet1-phy-intgrp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x100b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x100b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0xb0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0xb0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0xb0 + >; + }; + + pinctrl_ext_uart: ext-uartgrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0xb0 + MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0xb0 + >; + }; + + pinctrl_fan_enable: fan-enablegrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400000b0 + >; + }; + + pinctrl_gpio_motor: gpio-motorgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400000b0 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400000b0 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400000b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0xb0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0xb0 + >; + }; + + pinctrl_hog_pins: hog-pinsgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400000b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400000b0 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x400070a0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400000b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400000b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x400008b0 + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x400008b0 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400008b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400008b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x70b1 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0xb0 + >; + }; + + pinctrl_pwm_cp: pinctrl-pwm-cpgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x60a0 + >; + }; + + pinctrl_pwm_digital_input_ref: pwm-digital-input-refgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0xb0 + >; + }; + + pinctrl_pwm_fan: pwm-fangrp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x60a0 + >; + }; + + pinctrl_qca700x_cp_btld: qca700x-cp-btldgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400000b0 + >; + }; + + pinctrl_qca700x_cp_int: qca700x-cp-intgrp { + fsl,pins = < + MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x10b0 + >; + }; + + pinctrl_qca700x_cp_rst: qca700x-cp-rstgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400000b0 + >; + }; + + pinctrl_qca700x_mains_btld: qca700x-mains-btldgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400000b0 + >; + }; + + pinctrl_rotary_switch1: rotary-switch1grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0xb0 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0xb0 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0xb0 + >; + }; + + pinctrl_rotary_switch2: rotary-switch2grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0xb0 + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0xb0 + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0xb0 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0xb0 + >; + }; + + pinctrl_rs485_1: rs485-1grp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0xb0 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0xb0 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0xb0 + >; + }; + + pinctrl_rs485_2: rs485-2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x10b0 + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x10b0 + >; + }; + + pinctrl_status_leds: status-ledsgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0xb0 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0xb0 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0xb0 + >; + }; + + pinctrl_stm32: stm32grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x10b0 + MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x10b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0xb0 + MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0xb0 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x70b0 + MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x70b0 + >; + }; + + pinctrl_usb_pwr: usb-pwrgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0xb0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x7071 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x7071 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x7071 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x7071 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x7071 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x7071 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x7071 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x7071 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x7071 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x7071 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70b1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70b1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70b1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70b1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70b1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70b1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70b1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70b1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70b1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70b1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70f1 + >; + }; + + pinctrl_wdog2: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x10b0 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_cp_peak_snvs + &pinctrl_gpio_motor_snvs + &pinctrl_relay_sense_snvs + &pinctrl_rotary_switch1_snvs>; + + pinctrl_accelerometer_int1_snvs: accelerometer-int1-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x130a0 + >; + }; + + pinctrl_cp_peak_snvs: cp-peak-snvsgrp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x130a0 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 + >; + }; + + pinctrl_enet1_phy_rst: enet1-phy-rstgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x100a0 + >; + }; + + pinctrl_fan_sense_snvs: fan-sense-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x100a0 + >; + }; + + pinctrl_gpio_motor_snvs: gpio-motor-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 + >; + }; + + pinctrl_qca700x_mains_int: qca700x-mains-intgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x130a0 + >; + }; + + pinctrl_qca700x_mains_rst: qca700x-mains-rstgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400100a0 + >; + }; + + pinctrl_relay_sense_snvs: relay-sense-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x100a0 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x100a0 + >; + }; + + pinctrl_rotary_switch1_snvs: rotary-switch1-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x110a0 + >; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_digital_input_ref>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_cp>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rs485_1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,dte-mode; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rs485_2>; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stm32>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ext_uart>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb + &pinctrl_usb_pwr>; + dr_mode = "host"; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <35>; + fsl,tx-cal-45-dp-ohms = <35>; +}; + +&usbphy2 { + fsl,tx-cal-45-dn-ohms = <35>; + fsl,tx-cal-45-dp-ohms = <35>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <&sw2_reg>; + vqmmc-supply = <®_1v8>; + mmc-pwrseq = <&emmc_pwrseq>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog2>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts new file mode 100644 index 000000000000..67007ce383e3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Master"; + compatible = "chargebyte,imx6ull-tarragon-master", "fsl,imx6ull"; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_sense_snvs>; + fan-supply = <®_fan>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + + reg_fan: regulator { + compatible = "regulator-fixed"; + regulator-name = "fan-supply"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_enable>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&ecspi4 { + status = "okay"; + + qca700x_mains: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_mains_int + &pinctrl_qca700x_mains_rst + &pinctrl_qca700x_mains_btld>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_fan>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts new file mode 100644 index 000000000000..e471c2005bee --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Micro"; + compatible = "chargebyte,imx6ull-tarragon-micro", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts new file mode 100644 index 000000000000..cee223b5f8e1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Slave"; + compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull"; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts new file mode 100644 index 000000000000..7fd53b7a4372 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon SlaveXT"; + compatible = "chargebyte,imx6ull-tarragon-slavext", "fsl,imx6ull"; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_sense_snvs>; + fan-supply = <®_fan>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + + reg_fan: regulator { + compatible = "regulator-fixed"; + regulator-name = "fan-supply"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_enable>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_fan>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..8541cb3f3b3e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..be593d47e3b1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi new file mode 100644 index 000000000000..2bccd45e9fc2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2016 Freescale Semiconductor, Inc. + +#include "imx6ul.dtsi" +#include "imx6ull-pinfunc.h" +#include "imx6ull-pinfunc-snvs.h" + +/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ +/delete-node/ &uart8; +/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ +/delete-node/ &crypto; + +&cpu0 { + clock-frequency = <900000000>; + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1250000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&ocotp { + compatible = "fsl,imx6ull-ocotp", "syscon"; +}; + +&pxp { + compatible = "fsl,imx6ull-pxp"; + interrupts = , + ; +}; + +&usdhc1 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + +/ { + soc: soc { + aips3: bus@2200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02200000 0x100000>; + ranges; + + dcp: crypto@2280000 { + compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; + reg = <0x02280000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6ULL_CLK_DCP_CLK>; + clock-names = "dcp"; + }; + + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + + iomuxc_snvs: iomuxc-snvs@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; + }; + + uart8: serial@2288000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02288000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts new file mode 100644 index 000000000000..483d9732c002 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2018 NXP. + +/dts-v1/; + +#include "imx6ulz.dtsi" +#include "imx6ul-14x14-evk.dtsi" + +/delete-node/ &fec1; +/delete-node/ &fec2; +/delete-node/ &can1; +/delete-node/ &can2; +/delete-node/ &lcdif; +/delete-node/ &tsc; + +/ { + model = "Freescale i.MX6 ULZ 14x14 EVK Board"; + compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; + + /delete-node/ panel; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts new file mode 100644 index 000000000000..c92e4e2f6ab9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include +#include "imx6ulz.dtsi" + +/ { + model = "BSH SMM M2"; + compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; + + chosen { + stdout-path = &uart4; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + bus-width = <4>; + no-1-8-v; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + cap-sdio-irq; + mmc-pwrseq = <&usdhc2_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ + MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi new file mode 100644 index 000000000000..0b5f1a763567 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2018 NXP. + +#include "imx6ull.dtsi" + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + /delete-property/ i2c2; + /delete-property/ i2c3; + /delete-property/ serial4; + /delete-property/ serial5; + /delete-property/ serial6; + /delete-property/ serial7; + /delete-property/ spi2; + /delete-property/ spi3; + }; +}; + +/delete-node/ &adc1; +/delete-node/ &ecspi3; +/delete-node/ &ecspi4; +/delete-node/ &epit2; +/delete-node/ &gpt2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; +/delete-node/ &pwm8; +/delete-node/ &uart5; +/delete-node/ &uart6; +/delete-node/ &uart7; +/delete-node/ &uart8; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi new file mode 100644 index 000000000000..01612741f792 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi3 { + cs-gpios = < + &gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or */ + &gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */ + &gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */ + >; + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..326440f2b4f4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016-2022 Toradex + */ + +/ { + /* Fixed crystal dedicated to MCP2515. */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; +}; + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ + pinctrl-0 = <&pinctrl_atmel_adapter>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ + status = "disabled"; +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; + + mcp2515: can@0 { + clocks = <&clk16m>; + compatible = "microchip,mcp2515"; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..b687727f956a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */ + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; +}; + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio2 { + /* + * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to + * turn the transceiver off, that property has to be deleted and the gpio handled in + * userspace. + * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on. + */ + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC/SD, UHS-I capable uSD slot */ +&usdhc1 { + cap-power-off-card; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi new file mode 100644 index 000000000000..6a9e5ab59691 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ + pinctrl-0 = <&pinctrl_atmel_adapter>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio2 { + /* + * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled in userspace. + * The same applies to uart1_tx_on where the UART1 transceiver is turned on. + */ + uart25-tx-on-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart1-tx-on-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + disable-over-current; + status = "okay"; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi new file mode 100644 index 000000000000..104580d51d74 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi @@ -0,0 +1,1142 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016-2022 Toradex + */ + +#include + +/ { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + compatible = "pwm-backlight"; + default-brightness-level = <4>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + power-supply = <®_module_3v3>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + extcon_usbc_det: usbc-det { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + key-wakeup { + debounce-interval = <10>; + gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + panel_dpi: panel-dpi { + backlight = <&backlight>; + compatible = "edt,et057090dhu"; + power-supply = <®_3v3>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5V"; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_AVDD_AUDIO"; + }; + + reg_module_3v3_eth: regulator-module-3v3-eth { + compatible = "regulator-fixed"; + off-on-delay-us = <200000>; + regulator-name = "+V3.3_ETH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + startup-delay-us = <200000>; + vin-supply = <®_LDO1>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VCC_USB[1-4]"; + vin-supply = <®_5v0>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx7-sgtl5000"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + sound-dai = <&codec>; + }; + }; +}; + +/* Colibri AD0 to AD3 */ +&adc1 { + vref-supply = <®_DCDC3>; +}; + +/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */ + +&cpu0 { + cpu-supply = <®_DCDC2>; +}; + +/* Colibri SSP */ +&ecspi3 { + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phy-supply = <®_module_3v3_eth>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Micrel KSZ8041RNL */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + micrel,led-mode = <0>; + reg = <0>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&gpio1 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_135", + "SODIMM_22", + "", + "", + "SODIMM_37", + "SODIMM_29", + "SODIMM_59", + "SODIMM_28", + "SODIMM_30", + "SODIMM_67", + "", + "", + "SODIMM_188", + "SODIMM_178"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_111", + "SODIMM_113", + "SODIMM_115", + "SODIMM_117", + "SODIMM_119", + "SODIMM_121", + "SODIMM_123", + "SODIMM_125", + "SODIMM_91", + "SODIMM_89", + "SODIMM_105", + "SODIMM_152", + "SODIMM_150", + "SODIMM_95", + "SODIMM_126", + "SODIMM_107", + "SODIMM_114", + "SODIMM_116", + "SODIMM_118", + "SODIMM_120", + "SODIMM_122", + "SODIMM_124", + "SODIMM_127", + "SODIMM_130", + "SODIMM_132", + "SODIMM_134", + "SODIMM_133", + "SODIMM_104", + "SODIMM_106", + "SODIMM_110", + "SODIMM_112", + "SODIMM_128"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "SODIMM_93", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_136", + "SODIMM_138", + "SODIMM_140", + "SODIMM_142", + "SODIMM_144", + "SODIMM_146"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_35", + "SODIMM_33", + "SODIMM_38", + "SODIMM_36", + "SODIMM_21", + "SODIMM_19", + "SODIMM_131", + "SODIMM_129", + "SODIMM_90", + "SODIMM_92", + "SODIMM_88", + "SODIMM_86", + "SODIMM_81", + "SODIMM_94", + "SODIMM_96", + "SODIMM_75", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_67", + "SODIMM_59", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_69", + "SODIMM_71", + "SODIMM_73", + "SODIMM_47", + "SODIMM_190", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53", + "", + "", + "SODIMM_98", + "SODIMM_184", + "SODIMM_186", + "SODIMM_23", + "SODIMM_31", + "SODIMM_100", + "SODIMM_102"; +}; + +&gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_169", + "", + "", + "", + "SODIMM_77", + "SODIMM_24", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_32", + "SODIMM_34"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "SODIMM_63", + "SODIMM_55", + "", + "", + "", + "", + "SODIMM_196", + "SODIMM_194", + "", + "SODIMM_99", + "", + "", + "SODIMM_137"; +}; + +/* NAND on such SKUs */ +&gpmi { + fsl,use-minimum-ecc; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; +}; + +/* On-module Power I2C */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; + pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + codec: sgtl5000@a { + #sound-dai-cells = <0>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + reg = <0xa>; + VDDA-supply = <®_module_3v3_avdd>; + VDDD-supply = <®_DCDC3>; + VDDIO-supply = <®_module_3v3>; + }; + + ad7879_ts: touchscreen@2c { + adi,acquisition-time = /bits/ 8 <1>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,median-filter-size = /bits/ 8 <2>; + adi,resistance-plate-x = <120>; + compatible = "adi,ad7879-1"; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reg = <0x2c>; + touchscreen-max-pressure = <4096>; + status = "disabled"; + }; + + pmic@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; + + regulators { + reg_DCDC1: DCDC1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1000000>; + regulator-name = "+V1.0_SOC"; + }; + + reg_DCDC2: DCDC2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <975000>; + regulator-name = "+V1.1_ARM"; + }; + + reg_DCDC3: DCDC3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8"; + }; + + reg_DCDC4: DCDC4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <1350000>; + regulator-name = "+V1.35_DRAM"; + }; + + reg_LDO1: LDO1 { + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3_ETH"; + }; + + reg_LDO2: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SD"; + }; + + reg_LDO3: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3_LPSR"; + }; + + reg_LDO4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_LPSR"; + }; + + reg_LDO5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3"; + }; + }; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_connector>; + reg = <0x4a>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + status = "disabled"; + }; +}; + +&lcdif { + assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "disabled"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +/* Colibri PWM */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Colibri PWM */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Colibri PWM */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +/* Colibri PWM */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_1p0d { + vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */ +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; + uart-has-rtscts; +}; + +/* Colibri UART_B */ +&uart2 { + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +/* Colibri UART_C */ +&uart3 { + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +/* Colibri USBC */ +&usbotg1 { + dr_mode = "otg"; + extcon = <0>, <&extcon_usbc_det>; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_LDO2>; + wakeup-source; +}; + +/* eMMC on 1GB (eMMC) SKUs */ +&usdhc3 { + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + sdhci-caps-mask = <0x80000000 0x0>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <®_DCDC3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; + + /* + * Atmel MXT touchsceen + Capacitive Touch Adapter + * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3. + * Don't use them simultaneously. + */ + pinctrl_atmel_adapter: atmeladaptergrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */ + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */ + >; + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + pinctrl_atmel_connector: atmelconnectorgrp { + fsl,pins = < + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */ + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */ + >; + }; + + pinctrl_can_int: canintgrp { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */ + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */ + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */ + >; + }; + + pinctrl_ecspi3_cs: ecspi3csgrp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + >; + }; + + pinctrl_enet1_sleep: enet1-sleepgrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ + MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ + >; + }; + + pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */ + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3grp { /* LCD 18-23 */ + fsl,pins = < + MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ + >; + }; + + pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */ + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ + >; + }; + + pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */ + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ + >; + }; + + pinctrl_gpio_bl_on: gpioblongrp { + fsl,pins = < + MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + >; + }; + + pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */ + fsl,pins = < + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */ + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */ + >; + }; + + pinctrl_i2c4_recovery: i2c4-recoverygrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */ + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */ + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */ + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */ + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */ + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */ + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */ + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */ + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */ + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */ + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */ + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */ + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */ + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */ + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */ + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */ + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */ + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */ + >; + }; + + pinctrl_lcdif_dat_24: lcdifdat24grp { + fsl,pins = < + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */ + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */ + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */ + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */ + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */ + >; + }; + + pinctrl_lvds_transceiver: lvdstx { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */ + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */ + MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */ + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */ + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */ + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */ + >; + }; + + pinctrl_uart1_ctrl1: uart1ctrl1grp { + fsl,pins = < + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */ + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */ + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */ + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */ + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */ + >; + }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */ + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */ + >; + }; + + pinctrl_usbc_det: usbcdetgrp { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */ + >; + }; + + pinctrl_usbh_reg: usbhreggrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */ + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */ + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */ + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */ + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */ + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + /* Avoid backfeeding with removed card power. */ + pinctrl_usdhc1_sleep: usdhc1-slpgrp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x10 + MX7D_PAD_SD1_CLK__SD1_CLK 0x10 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + >; + }; + + pinctrl_sai1_mclk: sai1mclkgrp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_lpsr>; + + pinctrl_cd_usdhc1: cdusdhc1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */ + >; + }; + + pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0 + >; + }; + + pinctrl_gpio_lpsr: gpiolpsrgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */ + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_recovery: i2c1-recoverygrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f + >; + }; + + pinctrl_uart1_ctrl2: uart1ctrl2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi new file mode 100644 index 000000000000..3df6dff7734a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi @@ -0,0 +1,640 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ-Systems MBa7 carrier board. + * + * Copyright (C) 2016 TQ-Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + * + * Note: This file does not include nodes for all peripheral devices. + * As device driver coverage increases additional nodes can be added. + */ + +#include +#include + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + /delete-property/ mmc2; + }; + + beeper { + compatible = "gpio-beeper"; + gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path = &uart6; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + + button-0 { + /* #SWITCH_A */ + label = "S11"; + linux,code = ; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + }; + + button-1 { + /* #SWITCH_B */ + label = "S12"; + linux,code = ; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + }; + + button-2 { + /* #SWITCH_C */ + label = "S13"; + linux,code = ; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + label = "led1"; + gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_fec1_pwdn: regulator-fec1-pwdn { + compatible = "regulator-fixed"; + regulator-name = "PWDN_FEC1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_pwdn: regulator-fec2-pwdn { + compatible = "regulator-fixed"; + regulator-name = "PWDN_FEC2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mba_12v0: regulator-mba-12v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC12V0_MBA7"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_transmitter: regulator-lvds-transmitter { + compatible = "regulator-fixed"; + regulator-name = "#SHTDN_LVDS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, + <&gpio4 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-supply = <®_fec1_pwdn>; + phy-handle = <ðphy1_0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot@0 { + label = "U-Boot"; + reg = <0x0 0xd0000>; + }; + + env1@d0000 { + label = "ENV1"; + reg = <0xd0000 0x10000>; + }; + + env2@e0000 { + label = "ENV2"; + reg = <0xe0000 0x10000>; + }; + + dtb@f0000 { + label = "DTB"; + reg = <0xf0000 0x10000>; + }; + + linux@100000 { + label = "Linux"; + reg = <0x100000 0x700000>; + }; + + rootfs@800000 { + label = "RootFS"; + reg = <0x800000 0x3800000>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + clock-names = "mclk"; + ldoin-supply = <®_audio_3v3>; + iov-supply = <®_audio_3v3>; + }; + + pca9555: gpio-expander@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9555>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio7>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_mba7_1>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 + /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 + /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 + >; + }; + + pinctrl_hog_mba7_1: hogmba71grp { + fsl,pins = < + /* Limitation: WDOG2_B / WDOG2_RESET not usable */ + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 + /* #BOOT_EN */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 + >; + }; + + pinctrl_pca9555: pca95550grp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 + /* Limitation: RTS is not connected */ + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grp_gpio { + fsl,pins = < + /* WP */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c + /* CD */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c + /* VSELECT */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5e + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* LCD_CONTRAST */ + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi new file mode 100644 index 000000000000..fe42b0a46831 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB. + * + * Copyright (C) 2016 TQ-Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/ { + memory@80000000 { + device_type = "memory"; + /* 512 MB - default configuration */ + reg = <0x80000000 0x20000000>; + }; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&gpio2 { + /* Configured as pullup by QSPI pin group */ + qspi-reset-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "qspi-reset"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pfuze3000: pmic@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic1>; + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: temperature-sensor-eeprom@1e { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1e>; + status = "okay"; + }; + + /* ST M24C64 */ + m24c64: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + status = "okay"; + }; + + at24c02: eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + pagesize = <16>; + status = "okay"; + }; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 + >; + }; + + pinctrl_pmic1: pmic1grp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 + >; + }; + + pinctrl_qspi_reset: qspi_resetgrp { + fsl,pins = < + /* #QSPI_RESET */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x56 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x51 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x51 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&sdma { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vgen4_reg>; + vqmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* + * Errata e10574: + * WDOG reset needs to run with WDOG_RESET_B signal enabled. + * X1-51 (WDOG1#) signal needs carrier board handling to reset + * TQMa7 on X1-22 (RESET_IN#). + */ + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts new file mode 100644 index 000000000000..713483c39c9d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts @@ -0,0 +1,294 @@ +/* + * Support for CompuLab CL-SOM-iMX7 System-on-Module + * + * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Author: Ilya Ledvich + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "CompuLab CL-SOM-iMX7"; + compatible = "compulab,cl-som-imx7", "fsl,imx7d"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ + }; + + reg_usb_otg1_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x8>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + pca9555: pca9555@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30 + MX7D_PAD_SD2_WP__ENET1_MDC 0x30 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts new file mode 100644 index 000000000000..00ab92e56da4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Aster Carrier Board"; + compatible = "toradex,colibri-imx7d-aster", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts new file mode 100644 index 000000000000..d9c7045a55ba --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + * + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-aster", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts new file mode 100644 index 000000000000..96b599439dde --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7d-emmc-eval-v3", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..5eccb837b158 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-iris-v2", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts new file mode 100644 index 000000000000..ae10e8a66ff1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-iris", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi new file mode 100644 index 000000000000..3740e34ef99f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +#include "imx7d.dtsi" +#include "imx7-colibri.dtsi" + +/ { + aliases { + /* Required to properly pass MAC addresses from bootloader. */ + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + +&gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_169", + "SODIMM_157", + "", + "SODIMM_163", + "SODIMM_77", + "SODIMM_24", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_32", + "SODIMM_34"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usbh_vbus>; +}; + +/* eMMC */ +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts new file mode 100644 index 000000000000..33d787617db0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016-2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7d-eval-v3", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts new file mode 100644 index 000000000000..afdb1d06c7f6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7d-iris-v2", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&gpio7 { + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; + + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts new file mode 100644 index 000000000000..531b0b99bd5a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Iris Carrier Board"; + compatible = "toradex,colibri-imx7d-iris", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi new file mode 100644 index 000000000000..531a45b176a1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016-2022 Toradex + */ + +#include "imx7d.dtsi" +#include "imx7-colibri.dtsi" + +/ { + aliases { + /* Required to properly pass MAC addresses from bootloader. */ + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + +/* NAND */ +&gpmi { + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usbh_vbus>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts new file mode 100644 index 000000000000..a6d68165fb1e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator in + * manufacturing/debugging mode. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-flex-concentrator.dts" + +/ { + model = "Kamstrup OMNIA Flex Concentrator - Manufacturing"; + compatible = "kam,imx7d-flex-concentrator-mfg", "fsl,imx7d"; + + chosen { + stdout-path = &uart4; + }; +}; + +&uart4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts new file mode 100644 index 000000000000..3a723843d562 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" + +/* One I2C device on TQMa7 SoM is not mounted */ +/delete-node/ &ds1339; + +/ { + model = "Kamstrup OMNIA Flex Concentrator"; + compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; + + memory@80000000 { + device_type = "memory"; + /* 1024 MB - TQMa7D board configuration */ + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + /* + * Human Machine Interface consists of 4 dual red/green LEDs. + * hmi-a:green is controlled directly by the switch-mode power supply. + * hmi-a:red is not used. + */ + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "hmi-b:red:heartbeat-degraded"; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hmi-b:green:heartbeat-running"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "hmi-c:red:mesh-error"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "hmi-c:green:mesh-activity"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "hmi-d:red:omnia-error"; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "hmi-d:green:omnia-activity"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * Errata e10574 board restart workaround. + */ + gpio-restart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restart>; + compatible = "gpio-restart"; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* + * Analog signals + * ADC1_IN0: SMPS - 5V output monitor (voltage divider: 1/0.2806) + */ +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + status = "okay"; + + pcf2127: rtc@0 { + compatible = "nxp,pcf2127"; + reg = <0>; + spi-max-frequency = <2000000>; + reset-source; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* + * ST chip maximum SPI clock frequency is 33 MHz. + * + * TCG specification - Section 6.4.1 Clocking: + * TPM shall support a SPI clock frequency range of 10-24 MHz. + */ + st33htph: tpm-tis@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + /* + * MDIO bus reset is used to generate PHY device reset before + * Ethernet PHY type ID auto-detection. Otherwise this communication + * fails as device does not answer when recommended reset circuit + * is used. + */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-delay-us = <100000>; + reset-post-delay-us = <500000>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + + /* Microchip/Micrel KSZ8081RNB */ + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; +}; + +/* + * Detection signals for internal USB modules. + * Used for robust USB plug and play handling such as USB downstream port + * power-cycle and USB hub reset in case of misbehaving or crashed modules. + * + * SMPS - AC input monitor based on zero crossing. + * Used for last gasp notification. + */ +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "smps-ac-monitor", "", "usb-hub-reset", "", + "", "", "", "", "", "", "", "", + "", "module-b-detection", "", "module-a-detection", "", "", "", ""; +}; + +/* + * Tamper IRQ trigger timestamp reading. + * Used for sealed cover opened/closed notification. + */ +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "rtc-tamper-irq", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_misc>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c /* X2-15 */ + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 /* X2-18 */ + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 /* X2-13 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* X2-20 */ + /* RTC - Tamper IRQ */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x7c /* X2-72 */ + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x74 /* X2-68 */ + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x74 /* X2-76 */ + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x74 /* X2-78 */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x03 /* X2-48 */ + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x03 /* X2-46 */ + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 /* X2-53 */ + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 /* X2-55 */ + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 /* X2-61 */ + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 /* X2-56 */ + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 /* X2-58 */ + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 /* X2-64 */ + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 /* X2-52 */ + /* PHY reset: SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* X1-96 */ + /* Clock from PHY to MAC: 100kPU */ + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x70 /* X3-4 */ + /* PHY interrupt: 100kPU, HYS */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x78 /* X1-80 */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x14 /* X2-82 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* X1-82 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* X1-84 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* X1-86 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* X1-88 */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x14 /* X1-90 */ + >; + }; + + pinctrl_misc: miscgrp { + fsl,pins = < + /* Module A detection (low = present) */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x7c /* X2-105 */ + /* Module B detection (low = present) */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x7c /* X2-103 */ + /* SMPS - AC input monitor (high = failure) */ + MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x7c /* X2-88 */ + /* USB - Hub reset */ + MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */ + >; + }; + + pinctrl_restart: restartgrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x74 /* X1-94 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e /* X3-14 */ + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 /* X3-16 */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c /* X3-11 */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 /* X3-9 */ + >; + }; + +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + dr_mode = "host"; + status = "okay"; +}; + +/* + * External watchdog feature provided by pcf2127. + */ +&wdog1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts new file mode 100644 index 000000000000..32bf9fa9d00e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board. + * + * Copyright (C) 2016 TQ-Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" +#include "imx7-mba7.dtsi" + +/ { + model = "TQ-Systems TQMa7D board on MBa7 carrier board"; + compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-supply = <®_fec2_pwdn>; + phy-handle = <ðphy2_0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_mba7_1>; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 + MX7D_PAD_SD2_WP__ENET2_MDC 0x00 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 + /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 + /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* #pcie_wake */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 + /* #pcie_rst */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 + /* #pcie_dis */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* 1.5V logically from 3.3V */ + /* probe deferral not supported */ + /* pcie-bus-supply = <®_mpcie_1v5>; */ + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts b/arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts new file mode 100644 index 000000000000..dd8003bd1fc0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Linaro Ltd. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "96Boards Meerkat96 Board"; + compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; + + chosen { + stdout-path = &uart6; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MB */ + }; + + reg_wlreg_on: regulator-wlreg-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlreg_on>; + regulator-name = "wlreg_on"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "green:user1"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led5 { + label = "yellow:wlan"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led6 { + label = "blue:bt"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + keep-power-in-suspend; + fsl,tuning-step = <2>; + vmmc-supply = <®_3p3v>; + no-1-8-v; + broken-cd; + status = "okay"; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + no-1-8-v; + no-mmc; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wlreg_on>; + vqmmc-supply =<®_3p3v>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_irq>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_bt_gpios: btgpiosgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 + MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 + MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x0D + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + >; + }; + + pinctrl_wlan_irq: wlanirqgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 + >; + }; + + pinctrl_wlreg_on: wlregongrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts new file mode 100644 index 000000000000..9c6476bda4a0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts @@ -0,0 +1,699 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2016 Boundary Devices, Inc. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Boundary Devices i.MX7 Nitrogen7 Board"; + compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + backlight-j9 { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_j9>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + default-on; + }; + + backlight_lcd: backlight-j20 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "reg_wlan"; + startup-delay-us = <70000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; + clock-names = "ext_clock"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, + <&clks IMX7D_CLKO2_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_CKIL>; + assigned-clock-rates = <0>, <32768>; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + reg = <4>; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_rv4162>; + reg = <0x68>; + interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touch@48 { + compatible = "ti,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tsc2004>; + interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; +}; + +&lcdif { + status = "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vgen3_reg>; + bus-width = <4>; + fsl,tuning-step = <2>; + wakeup-source; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan>; + mmc-pwrseq = <&usdhc2_pwrseq>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 + MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_rv4162: i2c2-rv4162grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_tsc2004: i2c3tsc2004grp { + fsl,pins = < + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_j2: j2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d + MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d + MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d + MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d + >; + }; + + pinctrl_backlight_j9: backlightj9grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts new file mode 100644 index 000000000000..fdc10563f147 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx7d-pico.dtsi" +/ { + model = "TechNexion PICO-IMX7D and DWARF baseboard"; + compatible = "technexion,imx7d-pico-dwarf", "fsl,imx7d"; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx7d-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9554: io-expander@25 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + reg = <0x25>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pca9554 4 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts new file mode 100644 index 000000000000..d917dc4f2f22 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2017 NXP + +#include "imx7d-pico.dtsi" + +/ { + model = "TechNexion PICO-IMX7D Board using Hobbit baseboard"; + compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + }; + }; +}; + +&i2c1 { + sgtl5000: codec@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_vref_1v8>; + }; +}; + +&i2c4 { + status = "okay"; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&ecspi3 { + ads7846@0 { + reg = <0>; + compatible = "ti,ads7846"; + interrupt-parent = <&gpio2>; + interrupts = <7 0>; + spi-max-frequency = <1000000>; + pendown-gpio = <&gpio2 7 0>; + vcc-supply = <®_3p3v>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <4095>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4095>; + ti,pressure-max = /bits/ 16 <1024>; + ti,x-plate-ohms = /bits/ 16 <90>; + ti,y-plate-ohms = /bits/ 16 <90>; + ti,debounce-max = /bits/ 16 <70>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <2>; + ti,settle-delay-usec = /bits/ 16 <150>; + wakeup-source; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts new file mode 100644 index 000000000000..5afb1674e012 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx7d-pico.dtsi" +/ { + model = "TechNexion PICO-IMX7 and NYMPH baseboard"; + compatible = "technexion,imx7d-pico-nymph", "fsl,imx7d"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx7d-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + adc@52 { + compatible = "ti,adc081c"; + reg = <0x52>; + vref-supply = <®_2p5v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts new file mode 100644 index 000000000000..f263e391e24c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2017 NXP + +#include "imx7d-pico.dtsi" + +/ { + model = "TechNexion PICO-IMX7D Board and PI baseboard"; + compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + }; + }; +}; + +&i2c1 { + sgtl5000: codec@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_vref_1v8>; + }; +}; + +&i2c4 { + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; + +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi new file mode 100644 index 000000000000..73d90845e85c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi @@ -0,0 +1,675 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2017 NXP + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 50000 0>; + brightness-levels = <0 36 72 108 144 180 216 255>; + default-brightness-level = <6>; + }; + + /* Will be filled by the bootloader */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + panel { + compatible = "vxt,vl050-8048nt-c01"; + backlight = <&backlight>; + power-supply = <®_lcd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcdreg_on>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlreg_on: regulator-wlreg_on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlreg_on>; + regulator-name = "wlreg_on"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; + clock-names = "ext_clock"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, + <&clks IMX7D_CLKO2_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_CKIL>; + assigned-clock-rates = <0>, <32768>; +}; + +&ecspi3 { + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + status = "okay"; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { /* Backlight */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { /* Bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + bus-width = <4>; + fsl,tuning-step = <2>; + vmmc-supply = <®_3p3v>; + wakeup-source; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { /* Wifi SDIO */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wlreg_on>; + mmc-pwrseq = <&usdhc2_pwrseq>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + no-1-8-v; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f + MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f + MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ + >; + }; + + pinctrl_can1: can1frp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_can2: can2frp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78 + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 + >; + }; + + pinctrl_pwm1: pwm1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f + >; + }; + + pinctrl_pwm2: pwm2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f + >; + }; + + pinctrl_pwm3: pwm3 { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f + >; + }; + + pinctrl_pwm4: pwm4grp{ + fsl,pins = < + MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f + >; + }; + + pinctrl_reg_wlreg_on: regregongrp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79 + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79 + MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79 + MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79 + MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79 + >; + }; + + pinctrl_usbotg1_pwr: usbotg_pwr { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wifi_clk: wificlkgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d + >; + }; + + pinctrl_reg_lcdreg_on: reglcdongrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h new file mode 100644 index 000000000000..69f2c1ec8254 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h @@ -0,0 +1,1154 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_IMX7D_PINFUNC_H +#define __DTS_IMX7D_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 +#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 +#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 +#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 +#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 +#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 +#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 +#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 +#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 +#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 +#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 +#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 +#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 +#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 +#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 +#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 +#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 +#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 +#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 +#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 +#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 +#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 +#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 +#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 +#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 +#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 +#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 +#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 +#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 +#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 +#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 +#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 +#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 +#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 +#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 +#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 +#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 +#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 +#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 +#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 +#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 +#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 +#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 +#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 +#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 +#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 +#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 +#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 +#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 +#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 +#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 +#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 +#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 +#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 +#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 +#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 +#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 +#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 +#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 +#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 +#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 +#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 +#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 +#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 +#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 +#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 +#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 +#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 +#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 +#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 +#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 +#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 +#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 +#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 +#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 +#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 +#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 +#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 +#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 +#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 +#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 +#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 +#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 +#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 +#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 +#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 +#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 +#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 +#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 +#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 +#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 +#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 +#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 +#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 +#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 +#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 +#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 +#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 +#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 +#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 +#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 +#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 +#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 +#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 +#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 +#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 +#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 +#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 +#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 +#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 +#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 +#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 +#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 +#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 +#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 +#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 +#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 +#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 +#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 +#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 +#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 +#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 +#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 +#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 +#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 +#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 +#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 +#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 +#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 +#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 +#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 +#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 +#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 +#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 +#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 +#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 +#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 +#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 +#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 +#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 +#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 +#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 +#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 +#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 +#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 +#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 +#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 +#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 +#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 +#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 +#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 +#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 +#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 +#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 +#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 +#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 +#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 +#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 +#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 +#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 +#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 +#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 +#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 +#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 +#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 +#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 +#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 +#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 +#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 +#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 +#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 +#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 +#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 +#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 +#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 +#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 +#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 +#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 +#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 +#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 +#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 +#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 +#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 +#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 +#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 +#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 +#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 +#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 +#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 +#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 +#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 +#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 +#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 +#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 +#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 +#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 +#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 +#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 +#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 +#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 +#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 +#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 +#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 +#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 +#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 +#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 +#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 +#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 +#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 +#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 +#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 +#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 +#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 +#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 +#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 +#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 +#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 +#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 +#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 +#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 +#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 +#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 +#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 +#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 +#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 +#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 +#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 +#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 +#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 +#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 +#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 +#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 +#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 +#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 +#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 +#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 +#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 +#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 +#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 +#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 +#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 +#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 +#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 +#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 +#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 +#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 +#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 +#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 +#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 +#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 +#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 +#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 +#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 +#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 +#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 +#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 +#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 +#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 +#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 +#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 +#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 +#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 +#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 +#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 +#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 +#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 +#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 +#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 +#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 +#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 +#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 +#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 +#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 +#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 +#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 +#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 +#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 +#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 +#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 +#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 +#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 +#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 +#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 +#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 +#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 +#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 +#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 +#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 +#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 +#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 +#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 +#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 +#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 +#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 +#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 +#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 +#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 +#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 +#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 +#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 +#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 +#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 +#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 +#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 +#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 +#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 +#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 +#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 +#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 +#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 +#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 +#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 +#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 +#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 +#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 +#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 +#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 +#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 +#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 +#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 +#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 +#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 +#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 +#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 +#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 +#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 +#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 +#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 +#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 +#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 +#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 +#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 +#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 +#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 +#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 +#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 +#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 +#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 +#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 +#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 +#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 +#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 +#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 +#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 +#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 +#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 +#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 +#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 +#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 +#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 +#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 +#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 +#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 +#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 +#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 +#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 +#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 +#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 +#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 +#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 +#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 +#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 +#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 +#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 +#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 +#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 +#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 +#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 + +#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts new file mode 100644 index 000000000000..92cb45dacda6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2019 reMarkable AS - http://www.remarkable.com/ + * + */ + +/dts-v1/; + +#include "imx7d.dtsi" +#include + +/ { + model = "reMarkable 2.0"; + compatible = "remarkable,imx7d-remarkable2", "fsl,imx7d"; + + chosen { + stdout-path = &uart6; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + thermal-zones { + epd-thermal { + thermal-sensors = <&sy7636a>; + polling-delay-passive = <30000>; + polling-delay = <30000>; + + trips { + trip0 { + temperature = <49000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <50000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <150>; + }; + + reg_digitizer: regulator-digitizer { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_DIGITIZER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_digitizer_reg>; + pinctrl-1 = <&pinctrl_digitizer_reg>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; /* 100 ms */ + }; + + reg_touch: regulator-touch { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_TOUCH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_reg>; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; + clock-names = "ext_clock"; + }; +}; + +&cpu0 { + cpu-supply = <&buck1>; +}; + +&clks { + assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, + <&clks IMX7D_CLKO2_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_CKIL>; + assigned-clock-rates = <0>, <32768>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + wacom_digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x09>; + hid-descr-addr = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wacom>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vdd-supply = <®_digitizer>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + bd71815: pmic@4b { + compatible = "rohm,bd71815"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bd71815>; + interrupt-parent = <&gpio6>; /* PMIC_INT_B GPIO6_IO16 */ + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + clocks = <&clks IMX7D_CLKO2_ROOT_SRC>; + clock-output-names = "bd71815-32k-out"; + #clock-cells = <0>; + #gpio-cells = <2>; + + regulators { + buck1: buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2: buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2700000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6: ldodvref { + regulator-name = "ldodvref"; + regulator-boot-on; + regulator-always-on; + }; + + ldo7: ldolpsr { + regulator-name = "ldolpsr"; + regulator-boot-on; + regulator-always-on; + }; + + boost: wled { + regulator-name = "wled"; + regulator-min-microamp = <10>; + regulator-max-microamp = <25000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + vdd-supply = <®_touch>; + touchscreen-size-x = <880>; + touchscreen-size-y = <1280>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + reg = <0>; + linux,keycodes = ; + }; + + button@1 { + reg = <1>; + linux,keycodes = ; + }; + + button@2 { + reg = <2>; + linux,keycodes = ; + }; + + button@3 { + reg = <3>; + linux,keycodes = ; + }; + + button@4 { + reg = <4>; + linux,keycodes = ; + }; + + button@5 { + reg = <5>; + linux,keycodes = ; + }; + + button@6 { + reg = <6>; + linux,keycodes = ; + }; + + button@7 { + reg = <7>; + linux,keycodes = ; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4>; + status = "okay"; + + sy7636a: pmic@62 { + compatible = "silergy,sy7636a"; + reg = <0x62>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdpmic>; + #thermal-sensor-cells = <0>; + epd-pwr-good-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; + + regulators { + reg_epdpmic: vcom { + regulator-name = "vcom"; + regulator-boot-on; + }; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&usbotg2 { + srp-disable; + hnp-disable; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <®_brcm>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + cap-power-off-card; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc_lpsr { + pinctrl_digitizer_reg: digitizerreggrp { + fsl,pins = < + /* DIGITIZER_PWR_EN */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 + >; + }; + + pinctrl_wacom: wacomgrp { + fsl,pins = < + /*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */ + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */ + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */ + /*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */ + /*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */ + >; + }; +}; + +&iomuxc { + pinctrl_bd71815: bd71815grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x59 + >; + }; + + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + /* WIFI_PWR_EN */ + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x14 + >; + }; + + pinctrl_epdpmic: epdpmicgrp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x00000074 + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x00000014 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + /* CYTTSP interrupt */ + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x54 + /* CYTTSP reset */ + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x04 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_touch_reg: touchreggrp { + fsl,pins = < + /* TOUCH_PWR_EN */ + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x14 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x74 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* WiFi Reg On */ + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x00000014 + /* WiFi Sleep 32k */ + MX7D_PAD_SD1_WP__CCM_CLKO2 0x00000014 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts new file mode 100644 index 000000000000..f8a868552707 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts @@ -0,0 +1,42 @@ +/* + * Support for CompuLab SBC-iMX7 Single Board Computer + * + * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Author: Ilya Ledvich + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + */ + +#include "imx7d-cl-som-imx7.dts" + +/ { + model = "CompuLab SBC-iMX7"; + compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts new file mode 100644 index 000000000000..cabdaa6dc518 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx7d-sdb.dts" + +/ { + model = "Freescale i.MX7 SabreSD RevA Board"; + compatible = "fsl,imx7d-sdb-reva", "fsl,imx7d"; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&fec2 { + /delete-property/phy-supply; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + >; + }; + + pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts new file mode 100644 index 000000000000..996555596d40 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx7d-sdb.dts" + +/ { + sensor { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sensor>; + compatible = "sensirion,sht15"; + clk-gpios = <&gpio4 12 0>; + data-gpios = <&gpio4 13 0>; + vcc-supply = <®_sht15>; + }; + + reg_sht15: regulator-sht15 { + compatible = "regulator-fixed"; + regulator-name = "reg_sht15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_sensor: sensorgrp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts new file mode 100644 index 000000000000..cc9b8570ed4d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -0,0 +1,904 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 SabreSD Board"; + compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + spi-4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + extended_io: gpio-expander@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + }; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <200000>; + off-on-delay-us = <20000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "brcm_reg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; + }; + + reg_fec2_3v3: regulator-fec2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec2-3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + panel { + compatible = "innolux,at043tn24"; + backlight = <&backlight>; + power-supply = <®_lcd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "AMIC", + "AMIC", "MICB"; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + audio-cpu = <&sai3>; + hdmi-out; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + tsc2046@0 { + compatible = "ti,tsc2046"; + reg = <0>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2046_pendown>; + interrupt-parent = <&gpio2>; + interrupts = <29 0>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + touchscreen-max-pressure = <255>; + wakeup-source; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_3v3>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <12288000>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pcie { + reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +®_1p0d { + vin-supply = <&sw2_reg>; +}; + +®_1p2 { + vin-supply = <&sw2_reg>; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <36864000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; + wakeup-source; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + wakeup-source; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_brcm>; + fsl,tuning-step = <2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx7d-sdb { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2_reg: enet2reggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts b/arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts new file mode 100644 index 000000000000..85b97b5f64e7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2020 PHYTEC Messtechnik GmbH +// Author: Jens Lang +// Copyright (C) 2021 Fabio Estevam + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "Storopack SMEGW01 board"; + compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + mmc0 = &usdhc1; + mmc1 = &usdhc3; + mmc2 = &usdhc2; + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_lte_on: regulator-lte-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_on>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lte_on"; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_lte_nreset: regulator-lte-nreset { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_nreset>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "LTE_nReset"; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "wifi_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wlan_rfkill: regulator-wlan-rfkill { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rfkill>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlan_rfkill"; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + sram@0 { + compatible = "microchip,48l640"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + i2c_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_lpsr>; + dr_mode = "otg"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + over-current-active-low; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + wakeup-source; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + vmmc-supply = <®_wifi>; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + max-frequency = <200000000>; + bus-width = <8>; + fsl,tuning-step = <1>; + non-removable; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0 + >; + }; + + pinctrl_lte_on: lteongrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_lte_nreset: ltenresetgrp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059 + >; + }; + + pinctrl_rfkill: rfkillgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74 + >; + }; + + pinctrl_usbotg1_lpsr: usbotg1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 + >; + }; + + pinctrl_usbotg1_pwr: usbotg1-pwrgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 + >; + }; + + pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x0f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi new file mode 100644 index 000000000000..3ee2017c1ab3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ-Systems TQMa7D board with NXP i.MX7Dual SoC. + * + * Copyright (C) 2016 TQ-Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +#include "imx7d.dtsi" +#include "imx7-tqma7.dtsi" + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts new file mode 100644 index 000000000000..521493342fe9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device tree file for ZII's RMU2 board + * + * RMU - Remote Modem Unit + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "ZII RMU2 Board"; + compatible = "zii,imx7d-rmu2", "fsl,imx7d"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <&fec1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + fec1_phy: ethernet-phy@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy_reset>, + <&pinctrl_enet1_phy_interrupt>; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sdio; + no-sd; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet1_phy_reset: enet1phyresetgrp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 + + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_leds_debug: ledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 + >; + }; + + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 + MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp { + fsl,phy = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts new file mode 100644 index 000000000000..decc19af3b83 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts @@ -0,0 +1,923 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device tree file for ZII's RPU2 board + * + * RPU - Remote Peripheral Unit + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "ZII RPU2 Board"; + compatible = "zii,imx7d-rpu2", "fsl,imx7d"; + + chosen { + stdout-path = &uart2; + }; + + cs2000_ref: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + cs2000_in_dummy: dummy-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc2 1>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_stby>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_stby>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "GEN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 1"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound1_codec>; + simple-audio-card,frame-master = <&sound1_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa1>; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + sound1_codec: simple-audio-card,codec { + sound-dai = <&codec1>; + clocks = <&cs2000>; + }; + }; + + sound2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 2"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound2_codec>; + simple-audio-card,frame-master = <&sound2_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa2>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + sound2_codec: simple-audio-card,codec { + sound-dai = <&codec2>; + clocks = <&cs2000>; + }; + }; + + sound3 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 3"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound3_codec>; + simple-audio-card,frame-master = <&sound3_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa3>; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + sound3_codec: simple-audio-card,codec { + sound-dai = <&codec3>; + clocks = <&cs2000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "pic"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "gigabit_proc"; + ethernet = <&fec2>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", + "usb_1_en_b", + "usb_2_en_b", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = "12v_out_en_1", + "12v_out_en_2", + "12v_out_en_3", + "28v_out_en_5", + "28v_out_en_1", + "28v_out_en_2", + "28v_out_en_3", + "28v_out_en_4", + "", "", + "usb_3_en_b", + "usb_4_en_b", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + cs2000: clkgen@4e { + compatible = "cirrus,cs2000-cp"; + reg = <0x4e>; + #clock-cells = <0>; + clock-names = "clk_in", "ref_clk"; + clocks = <&cs2000_in_dummy>, <&cs2000_ref>; + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24000000>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec2: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec2>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hpa2: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa2>; + reg = <0x60>; + power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec3: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec3>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hpa3: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa3>; + reg = <0x60>; + power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec1: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec1>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa1>; + reg = <0x60>; + power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, + <&clks IMX7D_SAI2_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sdio; + no-sd; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_flexcan1_stby: flexcan1stbygrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_flexcan2_stby: flexcan2stbygrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00 + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03 + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03 + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00 + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f + >; + }; + + pinctrl_leds_debug: debuggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_tpa1: tpa6130-1grp { + fsl,pins = < + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038 + >; + }; + + pinctrl_tpa2: tpa6130-2grp { + fsl,pins = < + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038 + >; + }; + + pinctrl_tpa3: tpa6130-3grp { + fsl,pins = < + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 + MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_codec1: dac1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038 + >; + }; + + pinctrl_codec2: dac2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038 + >; + }; + + pinctrl_codec3: dac3grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi new file mode 100644 index 000000000000..4b94b8afb55d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Freescale Semiconductor, Inc. +// Copyright 2016 Toradex AG + +#include "imx7s.dtsi" +#include + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + + cpus { + cpu0: cpu@0 { + clock-frequency = <996000000>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + nvmem-cells = <&fuse_grade>; + nvmem-cell-names = "speed_grade"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <996000000>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_sleep_wait>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xd>, <0x7>; + opp-suspend; + }; + + opp-996000000 { + opp-hz = /bits/ 64 <996000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xc>, <0x7>; + opp-suspend; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0x8>, <0x3>; + opp-suspend; + }; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + soc: soc { + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; + + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx7d-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + /* + * Reference manual lists pci irqs incorrectly + * Real hardware ordering is same as imx6: D+MSI, C, B, A + */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; + }; +}; + +&aips2 { + pcie_phy: pcie-phy@306d0000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x306d0000 0x10000>; + status = "disabled"; + }; + + pxp: pxp@30700000 { + compatible = "fsl,imx7d-pxp"; + reg = <0x30700000 0x10000>; + interrupts = , + ; + clocks = <&clks IMX7D_PXP_CLK>; + clock-names = "axi"; + }; +}; + +&aips3 { + usbotg2: usb@30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc2: usbmisc@30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; + + fec2: ethernet@30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = , + , + , + ; + clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; +}; + +&ca_funnel_in_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts new file mode 100644 index 000000000000..58ebb02d948a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + * + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Aster Carrier Board"; + compatible = "toradex,colibri-imx7s-aster", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts new file mode 100644 index 000000000000..38de76630d6a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016-2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7s-eval-v3", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts new file mode 100644 index 000000000000..72b5c17ab1ab --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7s-iris-v2", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&gpio7 { + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; + + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts new file mode 100644 index 000000000000..26ba72c17feb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Iris Carrier Board"; + compatible = "toradex,colibri-imx7s-iris", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM, PWM, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi new file mode 100644 index 000000000000..ef51395d3537 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2016-2022 Toradex + */ + +#include "imx7s.dtsi" +#include "imx7-colibri.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +/* NAND */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts new file mode 100644 index 000000000000..8e4cf589c92c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Source for TQ-Systems TQMa7S board on MBa7 carrier board. + * + * Copyright (C) 2016 TQ-Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7s-tqma7.dtsi" +#include "imx7-mba7.dtsi" + +/ { + model = "TQ-Systems TQMa7S board on MBa7 carrier board"; + compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi new file mode 100644 index 000000000000..7a190fdb2d30 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ-Systems TQMa7S board with NXP i.MX7Solo SoC. + * + * Copyright (C) 2016 TQ-Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +#include "imx7s.dtsi" +#include "imx7-tqma7.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts new file mode 100644 index 000000000000..ba7231b364bb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 NXP Semiconductors. + * Author: Fabio Estevam + */ + +/dts-v1/; + +#include +#include "imx7s.dtsi" + +/ { + model = "Element14 Warp i.MX7 Board"; + compatible = "element14,imx7s-warp", "fsl,imx7s"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio>; + autorepeat; + + back { + label = "Back"; + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + reg_bt: regulator-bt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_reg>; + enable-active-high; + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + regulator-name = "bt_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_peri_3p15v: regulator-peri-3p15v { + compatible = "regulator-fixed"; + regulator-name = "peri_3p15v_reg"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&csi { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov2680: camera@36 { + compatible = "ovti,ov2680"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2680>; + reg = <0x36>; + clocks = <&osc>; + clock-names = "xvclk"; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + DOVDD-supply = <&sw2_reg>; + DVDD-supply = <&sw2_reg>; + AVDD-supply = <®_peri_3p15v>; + + port { + ov2680_to_mipi: endpoint { + remote-endpoint = <&mipi_from_sensor>; + clock-lanes = <0>; + data-lanes = <1>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: sgtl5000@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <&vgen4_reg>; + VDDD-supply = <&vgen2_reg>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&mipi_csi { + clock-frequency = <166000000>; + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + fsl,dte-mode; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_brcm>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + no-1-8-v; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&video_mux { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ + >; + }; + + pinctrl_bt_reg: btreggrp { + fsl,pins = < + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_ov2680: ov2660grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + >; + }; + + pinctrl_sai1_mclk: sai1mclkgrp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi new file mode 100644 index 000000000000..54026c2c93fa --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -0,0 +1,1290 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Freescale Semiconductor, Inc. +// Copyright 2016 Toradex AG + +#include +#include +#include +#include +#include +#include +#include "imx7d-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_sleep_wait: cpu-sleep-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <50>; + min-residency-us = <1000>; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <792000000>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_CLK_ARM>; + cpu-idle-states = <&cpu_sleep_wait>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + nvmem-cells = <&fuse_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xf>, <0xf>; + }; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + power-domains = <&pgc_hsic_phy>; + #phy-cells = <0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = ; + interrupt-affinity = <&cpu0>; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + funnel@30041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ca_funnel_in_ports: in-ports { + port { + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + }; + }; + + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + funnel@30083000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + /* M4 input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + aips1: bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = , /* GPIO1_INT15_0 */ + ; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 13 32>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 45 29>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 74 24>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 98 18>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 116 23>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 139 16>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: watchdog@30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: watchdog@302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: watchdog@302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc_lpsr: pinctrl@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + gpt1: timer@302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_GPT2_ROOT_CLK>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: timer@302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_GPT3_ROOT_CLK>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: timer@30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x30300000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_GPT4_ROOT_CLK>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + kpp: keypad@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_KPP_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon", + "simple-mfd"; + reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x14 0x00000010>; + }; + + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; + }; + + ocotp: efuse@30350000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_OCOTP_CLK>; + + tempmon_calib: calib@3c { + reg = <0x3c 0x4>; + }; + + fuse_grade: fuse-grade@10 { + reg = <0x10 0x4>; + }; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x30360000 0x10000>; + interrupts = , + ; + + reg_1p0d: regulator-vdd1p0d { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <0>; + }; + + reg_1p2: regulator-vdd1p2 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0x14>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <0>; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&fuse_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-pwrkey"; + linux,keycode = ; + wakeup-source; + status = "disabled"; + }; + }; + + clks: clock-controller@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: reset-controller@30390000 { + compatible = "fsl,imx7d-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + #power-domain-cells = <1>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = <1>; + power-supply = <®_1p0d>; + }; + + pgc_hsic_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <2>; + power-supply = <®_1p2>; + }; + }; + }; + }; + + aips2: bus@30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30400000 0x400000>; + ranges; + + adc1: adc@30610000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30610000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc2: adc@30620000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30620000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + ecspi4: spi@30630000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30630000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, + <&clks IMX7D_ECSPI4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ftm1: pwm@30640000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0x30640000 0x10000>; + #pwm-cells = <3>; + interrupts = ; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; + status = "disabled"; + }; + + ftm2: pwm@30650000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0x30650000 0x10000>; + #pwm-cells = <3>; + interrupts = ; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; + status = "disabled"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, + <&clks IMX7D_PWM1_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, + <&clks IMX7D_PWM2_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, + <&clks IMX7D_PWM3_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, + <&clks IMX7D_PWM4_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + csi: csi@30710000 { + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "axi", "mclk", "dcic"; + status = "disabled"; + + port { + csi_from_csi_mux: endpoint { + remote-endpoint = <&csi_mux_to_csi>; + }; + }; + }; + + lcdif: lcdif@30730000 { + compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; + reg = <0x30730000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, + <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; + clock-names = "pix", "axi"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "pclk", "wrap", "phy"; + power-domains = <&pgc_mipi_phy>; + phy-supply = <®_1p0d>; + resets = <&src IMX7_RESET_MIPI_PHY_MRST>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; + }; + }; + }; + }; + + aips3: bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; + + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; + }; + + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + flexcan1: can@30a00000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a00000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN1_ROOT_CLK>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1>; + status = "disabled"; + }; + + flexcan2: can@30a10000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a10000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN2_ROOT_CLK>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2>; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + mu0a: mailbox@30aa0000 { + compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu0b: mailbox@30ab0000 { + compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; + reg = <0x30ab0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <2>; + fsl,mu-side-b; + status = "disabled"; + }; + + usbotg1: usb@30b10000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b10000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbh: usb@30b30000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b30000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop3>; + fsl,usbmisc = <&usbmisc3 0>; + phy_type = "hsic"; + dr_mode = "host"; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc1: usbmisc@30b10200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b10200 0x200>; + }; + + usbmisc3: usbmisc@30b30200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b30200 0x200>; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + qspi: spi@30bb0000 { + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + sdma: dma-controller@30bd0000 { + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_SDMA_CORE_CLK>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = , + , + , + ; + clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 3>; + status = "disabled"; + }; + }; + + dma_apbh: dma-controller@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: nand-controller@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts new file mode 100644 index 000000000000..d76fea3b35c6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2019 NXP + +/dts-v1/; + +#include "imx7ulp.dtsi" +#include + +/ { + model = "Embedded Artists i.MX7ULP COM"; + compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; + + chosen { + stdout-path = &lpuart4; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x4000000>; + }; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc0 { + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts new file mode 100644 index 000000000000..eff51e113db4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + + chosen { + stdout-path = &lpuart4; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&tpm4 1 50000 0>; + brightness-levels = <0 20 25 30 35 40 100>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_rst>; + gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usdhc0 { + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 + >; + bias-pull-up; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 + >; + }; + + pinctrl_usbotg1_vbus: otg1vbusgrp { + fsl,pins = < + IMX7ULP_PAD_PTC0__PTC0 0x20000 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ + >; + }; + + pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { + fsl,pins = < + IMX7ULP_PAD_PTD0__PTD0 0x3 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h new file mode 100644 index 000000000000..c0148d79b62d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h @@ -0,0 +1,478 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __DTS_IMX7ULP_PINFUNC_H +#define __DTS_IMX7ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 +#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 +#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 +#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 +#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 +#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 +#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 +#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 +#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 +#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 +#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 +#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 +#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 +#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 +#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 +#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 +#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 +#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 +#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 +#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 +#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 +#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 +#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 +#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 +#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 +#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 +#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 +#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 +#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 +#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 +#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 +#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 +#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 +#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 +#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 +#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 +#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 +#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 +#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 +#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 +#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 +#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 +#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 +#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 +#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 +#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 +#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 +#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 +#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 +#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 +#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 +#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 +#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 +#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 +#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 +#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 +#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 +#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 + +#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi new file mode 100644 index 000000000000..b01ddda7bd9e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +#include +#include +#include + +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio_ptc; + gpio1 = &gpio_ptd; + gpio2 = &gpio_pte; + gpio3 = &gpio_ptf; + i2c0 = &lpi2c6; + i2c1 = &lpi2c7; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + usbphy0 = &usbphy1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + }; + }; + + intc: interrupt-controller@40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x1000>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + sirc: clock-sirc { + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + #clock-cells = <0>; + }; + + firc: clock-firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + clock-output-names = "firc"; + #clock-cells = <0>; + }; + + upll: clock-upll { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "upll"; + #clock-cells = <0>; + }; + + ahbbridge0: bus@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + edma1: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clock-names = "dma", "dmamux0"; + clocks = <&pcc2 IMX7ULP_CLK_DMA1>, + <&pcc2 IMX7ULP_CLK_DMA_MUX1>; + }; + + crypto: crypto@40240000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40240000 0x10000>; + ranges = <0 0x40240000 0x10000>; + clocks = <&pcc2 IMX7ULP_CLK_CAAM>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + lpuart4: serial@402d0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402d0000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial@402e0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402e0000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + tpm4: pwm@40250000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&pcc2 IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; + + usbotg1: usb@40330000 { + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x40330000 0x200>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_USB0>; + phys = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@40330200 { + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x40330200 0x200>; + }; + + usbphy1: usb-phy@40350000 { + compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; + reg = <0x40350000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; + #phy-cells = <0>; + }; + + usdhc0: mmc@40370000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC0>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + usdhc1: mmc@40380000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + scg1: clock-controller@403e0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll"; + #clock-cells = <1>; + }; + + wdog1: watchdog@403d0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403d0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + }; + + pcc2: clock-controller@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", + "firc_bus_clk", "rosc", "spll_bus_clk"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + }; + + smc1: clock-controller@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; + clock-names = "divcore", "hsrun_divcore"; + }; + + pcc3: clock-controller@40b30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40b30000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", + "firc_bus_clk", "rosc", "spll_bus_clk"; + }; + }; + + ahbbridge1: bus@40800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + lpi2c6: i2c@40a40000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40a40000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: i2c@40a50000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40a50000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@40a60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40a60000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart7: serial@40a70000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40a70000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + memory-controller@40ab0000 { + compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; + reg = <0x40ab0000 0x1000>; + clocks = <&pcc3 IMX7ULP_CLK_MMDC>; + }; + + iomuxc1: pinctrl@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + }; + + gpio_ptc: gpio@40ae0000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40ae0000 0x1000 0x400f0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLC>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 20>; + }; + + gpio_ptd: gpio@40af0000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40af0000 0x1000 0x400f0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 12>; + }; + + gpio_pte: gpio@40b00000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40b00000 0x1000 0x400f0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 16>; + }; + + gpio_ptf: gpio@40b10000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40b10000 0x1000 0x400f00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 96 20>; + }; + }; + + m4aips1: bus@41080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x41080000 0x80000>; + ranges; + + sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; + + ocotp: efuse@410a6000 { + compatible = "fsl,imx7ulp-ocotp", "syscon"; + reg = <0x410a6000 0x4000>; + clocks = <&scg1 IMX7ULP_CLK_DUMMY>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts new file mode 100644 index 000000000000..6a9c10decf52 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +/dts-v1/; +#include "imxrt1050.dtsi" +#include "imxrt1050-pinfunc.h" + +/ { + model = "NXP IMXRT1050-evk board"; + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x2000000>; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h new file mode 100644 index 000000000000..22c14a3262ad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h @@ -0,0 +1,993 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * + */ + +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 +#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi new file mode 100644 index 000000000000..dd714d235d5f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include "../../armv7-m.dtsi" +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + osc3M: osc3M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + }; + + soc { + lpuart1: serial@40184000 { + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1050_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@400d8000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x400d8000 0x4000>; + }; + + clks: clock-controller@400fc000 { + compatible = "fsl,imxrt1050-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL2_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, + <&clks IMXRT1050_CLK_PLL1_ARM>, + <&clks IMXRT1050_CLK_PLL2_SYS>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL2_SYS>; + }; + + edma1: dma-controller@400e8000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x400e8000 0x4000>, + <0x400ec000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1050_CLK_DMA>, + <&clks IMXRT1050_CLK_DMA_MUX>; + }; + + usdhc1: mmc@402c0000 { + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x402c0000 0x4000>; + interrupts = <110>; + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, + <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <200000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <80>, <81>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <82>, <83>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <84>, <85>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@401c4000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c4000 0x4000>; + interrupts = <86>, <87>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <88>, <89>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt: timer@401ec000 { + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc3M>; + clock-names = "per"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h new file mode 100644 index 000000000000..3b9fff2f08e1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0 +#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0 +#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1 +#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1 +#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0 +#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1 +#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0 +#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1 +#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0 + +#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1 +#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2 +#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1 +#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1 +#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1 +#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0 +#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1 +#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2 + +#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1 +#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0 +#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2 +#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1 +#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1 + +#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1 +#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1 +#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1 + +#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1 +#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1 +#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1 +#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1 +#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1 +#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1 + +#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0 +#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1 + +#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0 +#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0 + +#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0 +#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0 + +#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0 + +#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0 + +#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0 + +#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0 +#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1 +#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1 +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1 +#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1 +#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0 +#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0 +#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1 +#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0 +#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1 +#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0 +#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1 +#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0 +#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1 +#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1 +#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1 +#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1 +#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1 +#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1 +#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0 +#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0 +#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1 +#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0 +#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0 +#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1 +#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0 +#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0 +#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0 +#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0 +#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0 +#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0 +#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0 +#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1 +#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0 +#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0 +#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0 +#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1 +#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0 +#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0 +#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0 + +#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0 +#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0 +#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0 +#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1 +#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2 +#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0 +#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1 + +#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0 +#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0 +#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1 +#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0 +#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0 +#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0 +#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0 +#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0 +#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0 +#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0 +#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0 +#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0 +#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0 +#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0 +#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0 +#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0 +#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0 +#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0 +#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1 +#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0 +#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0 +#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0 +#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0 +#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1 +#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0 + +#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0 +#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0 +#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1 +#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1 + +#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0 +#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0 +#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1 +#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1 +#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1 + +#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1 +#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1 +#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1 +#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0 +#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0 +#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1 +#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1 +#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1 +#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1 +#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1 +#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1 +#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1 +#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0 +#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1 +#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1 +#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1 +#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1 +#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0 +#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1 +#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3 +#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1 +#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0 +#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0 +#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0 +#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2 +#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0 +#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1 +#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1 +#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1 +#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1 +#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0 +#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2 +#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2 +#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0 +#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1 + +#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1 + +#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2 +#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0 +#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2 +#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1 +#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3 + +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2 +#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1 +#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */ diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi new file mode 100644 index 000000000000..e3b2d23068f7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + model = "TQ-Systems MBA6ULx Baseboard"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + rtc0 = &rtc0; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_mba6ul_3v3>; + enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buttons>; + + button1 { + label = "s14"; + linux,code = ; + gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s6"; + linux,code = ; + gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s7"; + linux,code = ; + gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + }; + + power-button { + label = "POWER"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + led1 { + label = "led1"; + gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "lcd-pwr"; + gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_mba6ul_3v3: regulator-mba6ul-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_mba6ul_5v0: regulator-mba6ul-5v0 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_mpcie: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mpcie-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <500000>; + vin-supply = <®_mba6ul_3v3>; + }; + + reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { + compatible = "regulator-fixed"; + gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "otg2-vbus-supply-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_mpcie>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <768000000>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + reg = <0>; + max-speed = <100>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + reg = <1>; + max-speed = <100>; + }; + }; +}; + +&i2c4 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + ldoin-supply = <®_mba6ul_3v3>; + iov-supply = <®_mba6ul_3v3>; + }; + + jc42: temperature-sensor@19 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander_out0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; + }; + + expander_in0: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander_in0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; + + enet1_int-hog { + gpio-hog; + gpios = <6 0>; + input; + }; + + enet2_int-hog { + gpio-hog; + gpios = <7 0>; + input; + }; + }; + + expander_out1: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; + }; + + analog_touch: touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio4>; + interrupt-controller; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,ave-ctrl = <3>; /* 8 sample average control */ + st,fraction-z = <7>; /* 7 length fractional part in z */ + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,settling = <3>; /* 1 ms panel driver settling time */ + st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + vcc-supply = <®_mba6ul_3v3>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24000000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart6dte>; */ + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* otg-port */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + power-active-high; + over-current-active-low; + /* we implement only dual role but not a fully featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* 7-port usb hub */ +/* id, pwr, oc pins not connected */ +&usbotg2 { + disable-over-current; + vbus-supply = <®_otg2vbus_5v0>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_mba6ul_3v3>; + vqmmc-supply = <®_vccsd>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_buttons: buttonsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + >; + }; + + pinctrl_enet2_mdc: enet2mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_expander_in0: expanderin0grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6dte: uart6dte { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 + MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/Makefile b/arch/arm/boot/dts/nxp/lpc/Makefile new file mode 100644 index 000000000000..56b9a0ebb917 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4337-ciaa.dtb \ + lpc4350-hitex-eval.dtb \ + lpc4357-ea4357-devkit.dtb \ + lpc4357-myd-lpc4357.dtb +dtb-$(CONFIG_ARCH_LPC32XX) += \ + lpc3250-ea3250.dtb \ + lpc3250-phy3250.dtb diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi new file mode 100644 index 000000000000..9cf09c183b85 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -0,0 +1,537 @@ +/* + * Common base for NXP LPC18xx and LPC43xx devices. + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +#include "../../armv7-m.dtsi" + +#include "dt-bindings/clock/lpc18xx-cgu.h" +#include "dt-bindings/clock/lpc18xx-ccu.h" + +#define LPC_PIN(port, pin) (0x##port * 32 + pin) +#define LPC_GPIO(port, pin) (port * 32 + pin) + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m3"; + device_type = "cpu"; + reg = <0x0>; + clocks = <&ccu1 CLK_CPU_CORE>; + }; + }; + + clocks { + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; + }; + }; + + soc { + sct_pwm: pwm@40000000 { + compatible = "nxp,lpc1850-sct-pwm"; + reg = <0x40000000 0x1000>; + clocks =<&ccu1 CLK_CPU_SCT>; + clock-names = "pwm"; + resets = <&rgu 37>; + #pwm-cells = <3>; + status = "disabled"; + }; + + dmac: dma-controller@40002000 { + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x00041080>; + reg = <0x40002000 0x1000>; + interrupts = <2>; + clocks = <&ccu1 CLK_CPU_DMA>; + clock-names = "apb_pclk"; + resets = <&rgu 19>; + #dma-cells = <2>; + dma-channels = <8>; + dma-requests = <16>; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb1; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + }; + + spifi: flash-controller@40003000 { + compatible = "nxp,lpc1773-spifi"; + reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; + reg-names = "spifi", "flash"; + interrupts = <30>; + clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; + clock-names = "spifi", "reg"; + resets = <&rgu 53>; + status = "disabled"; + }; + + mmcsd: mmcsd@40004000 { + compatible = "snps,dw-mshc"; + reg = <0x40004000 0x1000>; + interrupts = <6>; + clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; + clock-names = "ciu", "biu"; + resets = <&rgu 20>; + status = "disabled"; + }; + + usb0: usb@40006100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40006100 0x100>; + interrupts = <8>; + clocks = <&ccu1 CLK_CPU_USB0>; + resets = <&rgu 17>; + phys = <&usb0_otg_phy>; + phy-names = "usb"; + has-transaction-translator; + status = "disabled"; + }; + + usb1: usb@40007100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40007100 0x100>; + interrupts = <9>; + clocks = <&ccu1 CLK_CPU_USB1>; + resets = <&rgu 18>; + status = "disabled"; + }; + + emc: memory-controller@40005000 { + compatible = "arm,pl172", "arm,primecell"; + reg = <0x40005000 0x1000>; + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; + clock-names = "mpmcclk", "apb_pclk"; + resets = <&rgu 21>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x1c000000 0x1000000 + 1 0 0x1d000000 0x1000000 + 2 0 0x1e000000 0x1000000 + 3 0 0x1f000000 0x1000000>; + status = "disabled"; + }; + + lcdc: lcd-controller@40008000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x40008000 0x1000>; + interrupts = <7>; + interrupt-names = "combined"; + clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; + clock-names = "clcdclk", "apb_pclk"; + resets = <&rgu 16>; + status = "disabled"; + }; + + eeprom: eeprom@4000e000 { + compatible = "nxp,lpc1857-eeprom"; + reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; + reg-names = "reg", "mem"; + clocks = <&ccu1 CLK_CPU_EEPROM>; + clock-names = "eeprom"; + resets = <&rgu 27>; + interrupts = <4>; + status = "disabled"; + }; + + mac: ethernet@40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + resets = <&rgu 22>; + reset-names = "stmmaceth"; + rx-fifo-depth = <256>; + tx-fifo-depth = <256>; + snps,pbl = <4>; /* 32 (8x mode) */ + snps,force_thresh_dma_mode; + status = "disabled"; + }; + + creg: syscon@40043000 { + compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; + reg = <0x40043000 0x1000>; + clocks = <&ccu1 CLK_CPU_CREG>; + resets = <&rgu 5>; + + creg_clk: clock-controller { + compatible = "nxp,lpc1850-creg-clk"; + clocks = <&xtal32>; + #clock-cells = <1>; + }; + + usb0_otg_phy: phy { + compatible = "nxp,lpc1850-usb-otg-phy"; + clocks = <&ccu1 CLK_USB0>; + #phy-cells = <0>; + }; + + dmamux: dma-mux { + compatible = "nxp,lpc1850-dmamux"; + #dma-cells = <3>; + dma-requests = <64>; + dma-masters = <&dmac>; + }; + }; + + rtc: rtc@40046000 { + compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; + reg = <0x40046000 0x1000>; + interrupts = <47>; + clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; + clock-names = "rtc", "reg"; + }; + + cgu: clock-controller@40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + ccu1: clock-controller@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + + rgu: reset-controller@40053000 { + compatible = "nxp,lpc1850-rgu"; + reg = <0x40053000 0x1000>; + clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; + clock-names = "delay", "reg"; + #reset-cells = <1>; + }; + + watchdog@40080000 { + compatible = "nxp,lpc1850-wwdt"; + reg = <0x40080000 0x24>; + interrupts = <49>; + clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; + clock-names = "wdtclk", "reg"; + }; + + uart0: serial@40081000 { + compatible = "nxp,lpc1850-uart", "ns16550a"; + reg = <0x40081000 0x1000>; + reg-shift = <2>; + interrupts = <24>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; + clock-names = "uartclk", "reg"; + resets = <&rgu 44>; + dmas = <&dmamux 1 1 2 + &dmamux 2 1 2 + &dmamux 11 2 2 + &dmamux 12 2 2>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@40082000 { + compatible = "nxp,lpc1850-uart", "ns16550a"; + reg = <0x40082000 0x1000>; + reg-shift = <2>; + interrupts = <25>; + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + clock-names = "uartclk", "reg"; + resets = <&rgu 45>; + dmas = <&dmamux 3 1 2 + &dmamux 4 1 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + ssp0: spi@40083000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x40083000 0x1000>; + interrupts = <22>; + clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; + clock-names = "sspclk", "apb_pclk"; + resets = <&rgu 50>; + dmas = <&dmamux 9 0 2 + &dmamux 10 0 2>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + timer0: timer@40084000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40084000 0x1000>; + interrupts = <12>; + clocks = <&ccu1 CLK_CPU_TIMER0>; + clock-names = "timerclk"; + resets = <&rgu 32>; + }; + + timer1: timer@40085000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40085000 0x1000>; + interrupts = <13>; + clocks = <&ccu1 CLK_CPU_TIMER1>; + clock-names = "timerclk"; + resets = <&rgu 33>; + }; + + pinctrl: pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + }; + + i2c0: i2c@400a1000 { + compatible = "nxp,lpc1788-i2c"; + reg = <0x400a1000 0x1000>; + interrupts = <18>; + clocks = <&ccu1 CLK_APB1_I2C0>; + resets = <&rgu 48>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can1: can@400a4000 { + compatible = "bosch,c_can"; + reg = <0x400a4000 0x1000>; + interrupts = <43>; + clocks = <&ccu1 CLK_APB1_CAN1>; + resets = <&rgu 54>; + status = "disabled"; + }; + + uart2: serial@400c1000 { + compatible = "nxp,lpc1850-uart", "ns16550a"; + reg = <0x400c1000 0x1000>; + reg-shift = <2>; + interrupts = <26>; + clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; + clock-names = "uartclk", "reg"; + resets = <&rgu 46>; + dmas = <&dmamux 5 1 2 + &dmamux 6 1 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@400c2000 { + compatible = "nxp,lpc1850-uart", "ns16550a"; + reg = <0x400c2000 0x1000>; + reg-shift = <2>; + interrupts = <27>; + clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; + clock-names = "uartclk", "reg"; + resets = <&rgu 47>; + dmas = <&dmamux 7 1 2 + &dmamux 8 1 2 + &dmamux 13 3 2 + &dmamux 14 3 2>; + dma-names = "tx", "rx", "rx", "tx"; + status = "disabled"; + }; + + timer2: timer@400c3000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x400c3000 0x1000>; + interrupts = <14>; + clocks = <&ccu1 CLK_CPU_TIMER2>; + clock-names = "timerclk"; + resets = <&rgu 34>; + }; + + timer3: timer@400c4000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x400c4000 0x1000>; + interrupts = <15>; + clocks = <&ccu1 CLK_CPU_TIMER3>; + clock-names = "timerclk"; + resets = <&rgu 35>; + }; + + ssp1: spi@400c5000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x400c5000 0x1000>; + interrupts = <23>; + clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; + clock-names = "sspclk", "apb_pclk"; + resets = <&rgu 51>; + dmas = <&dmamux 11 2 2 + &dmamux 12 2 2 + &dmamux 3 3 2 + &dmamux 4 3 2 + &dmamux 5 2 2 + &dmamux 6 2 2 + &dmamux 13 2 2 + &dmamux 14 2 2>; + dma-names = "rx", "tx", "tx", "rx", + "tx", "rx", "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@400e0000 { + compatible = "nxp,lpc1788-i2c"; + reg = <0x400e0000 0x1000>; + interrupts = <19>; + clocks = <&ccu1 CLK_APB3_I2C1>; + resets = <&rgu 49>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dac: dac@400e1000 { + compatible = "nxp,lpc1850-dac"; + reg = <0x400e1000 0x1000>; + interrupts = <0>; + clocks = <&ccu1 CLK_APB3_DAC>; + resets = <&rgu 42>; + status = "disabled"; + }; + + can0: can@400e2000 { + compatible = "bosch,c_can"; + reg = <0x400e2000 0x1000>; + interrupts = <51>; + clocks = <&ccu1 CLK_APB3_CAN0>; + resets = <&rgu 55>; + status = "disabled"; + }; + + adc0: adc@400e3000 { + compatible = "nxp,lpc1850-adc"; + reg = <0x400e3000 0x1000>; + interrupts = <17>; + clocks = <&ccu1 CLK_APB3_ADC0>; + resets = <&rgu 40>; + status = "disabled"; + }; + + adc1: adc@400e4000 { + compatible = "nxp,lpc1850-adc"; + reg = <0x400e4000 0x1000>; + interrupts = <21>; + clocks = <&ccu1 CLK_APB3_ADC1>; + resets = <&rgu 41>; + status = "disabled"; + }; + + gpio: gpio@400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, + <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, + <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, + <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, + <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, + <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, + <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, + <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, + <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, + <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, + <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, + <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, + <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, + <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, + <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, + <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, + <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, + <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, + <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, + <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, + <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, + <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, + <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, + <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, + <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, + <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, + <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, + <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, + <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, + <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, + <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, + <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, + <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, + <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, + <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, + <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, + <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, + <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts new file mode 100644 index 000000000000..63c6f17bb7c9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Embedded Artists LPC3250 board + * + * Copyright 2012 Roland Stigge + */ + +/dts-v1/; +#include "lpc32xx.dtsi" + +/ { + model = "Embedded Artists LPC3250 board based on NXP LPC3250"; + compatible = "ea,ea3250", "nxp,lpc3250"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button { + label = "Interrupt Key"; + linux,code = <103>; + gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ + }; + + key1 { + label = "KEY1"; + linux,code = <1>; + gpios = <&pca9532 0 0>; + }; + + key2 { + label = "KEY2"; + linux,code = <2>; + gpios = <&pca9532 1 0>; + }; + + key3 { + label = "KEY3"; + linux,code = <3>; + gpios = <&pca9532 2 0>; + }; + + key4 { + label = "KEY4"; + linux,code = <4>; + gpios = <&pca9532 3 0>; + }; + + joy0 { + label = "Joystick Key 0"; + linux,code = <10>; + gpios = <&gpio 2 0 0>; /* P2.0 */ + }; + + joy1 { + label = "Joystick Key 1"; + linux,code = <11>; + gpios = <&gpio 2 1 0>; /* P2.1 */ + }; + + joy2 { + label = "Joystick Key 2"; + linux,code = <12>; + gpios = <&gpio 2 2 0>; /* P2.2 */ + }; + + joy3 { + label = "Joystick Key 3"; + linux,code = <13>; + gpios = <&gpio 2 3 0>; /* P2.3 */ + }; + + joy4 { + label = "Joystick Key 4"; + linux,code = <14>; + gpios = <&gpio 2 4 0>; /* P2.4 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + /* LEDs on OEM Board */ + + led1 { + gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio 2 10 1>; /* P2.10, active low */ + default-state = "off"; + }; + + led3 { + gpios = <&gpio 2 11 1>; /* P2.11, active low */ + default-state = "off"; + }; + + led4 { + gpios = <&gpio 2 12 1>; /* P2.12, active low */ + default-state = "off"; + }; + + /* LEDs on Base Board */ + + lede1 { + gpios = <&pca9532 8 0>; + default-state = "off"; + }; + lede2 { + gpios = <&pca9532 9 0>; + default-state = "off"; + }; + lede3 { + gpios = <&pca9532 10 0>; + default-state = "off"; + }; + lede4 { + gpios = <&pca9532 11 0>; + default-state = "off"; + }; + lede5 { + gpios = <&pca9532 12 0>; + default-state = "off"; + }; + lede6 { + gpios = <&pca9532 13 0>; + default-state = "off"; + }; + lede7 { + gpios = <&pca9532 14 0>; + default-state = "off"; + }; + lede8 { + gpios = <&pca9532 15 0>; + default-state = "off"; + }; + }; +}; + +/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ +&adc { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 3 10 0>; + reset-gpio = <&gpio 3 2 0>; + dac-clk = "wspll"; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; +}; + +&mac { + phy-mode = "rmii"; + use-iram; + status = "okay"; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; +}; + +/* 128MB Flash via SLC NAND controller */ +&slc { + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@0 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1@80000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2@140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts new file mode 100644 index 000000000000..21a6d0bca1e8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * PHYTEC phyCORE-LPC3250 board + * + * Copyright (C) 2015-2019 Vladimir Zapolskiy + * Copyright 2012 Roland Stigge + */ + +/dts-v1/; +#include "lpc32xx.dtsi" + +/ { + model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; + compatible = "phytec,phy3250", "nxp,lpc3250"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { /* red */ + gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ + default-state = "off"; + }; + + led1 { /* green */ + gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ + linux,default-trigger = "heartbeat"; + }; + }; + + panel: panel { + compatible = "sharp,lq035q7db03"; + power-supply = <®_lcd>; + + port { + panel_input: endpoint { + remote-endpoint = <&cldc_output>; + }; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 4 0>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 0 0>; + enable-active-high; + regulator-boot-on; + }; + + reg_sd: regulator-sd { + compatible = "regulator-fixed"; + regulator-name = "sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 5 5 0>; + enable-active-high; + regulator-boot-on; + }; +}; + +&clcd { + max-memory-bandwidth = <18710000>; + status = "okay"; + + port { + cldc_output: endpoint { + remote-endpoint = <&panel_input>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 3 10 0>; + reset-gpio = <&gpio 3 2 0>; + dac-clk = "wspll"; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2c { + compatible = "nxp,isp1301"; + reg = <0x2c>; + }; +}; + +&key { + keypad,num-rows = <1>; + keypad,num-columns = <1>; + nxp,debounce-delay-ms = <3>; + nxp,scan-delay-ms = <34>; + linux,keymap = <0x00000002>; + status = "okay"; +}; + +&mac { + phy-mode = "rmii"; + use-iram; + status = "okay"; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&gpio 3 0 0>; + cd-gpios = <&gpio 3 1 0>; + cd-inverted; + bus-width = <4>; + vmmc-supply = <®_sd>; + status = "okay"; +}; + +/* 64MB Flash via SLC NAND controller */ +&slc { + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <40000000>; + nxp,whold = <100000000>; + nxp,wsetup = <100000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <40000000>; + nxp,rhold = <66666666>; + nxp,rsetup = <100000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@0 { + label = "phy3250-boot"; + reg = <0x00000000 0x00064000>; + read-only; + }; + + mtd1@64000 { + label = "phy3250-uboot"; + reg = <0x00064000 0x00190000>; + read-only; + }; + + mtd2@1f4000 { + label = "phy3250-ubt-prms"; + reg = <0x001f4000 0x00010000>; + }; + + mtd3@204000 { + label = "phy3250-kernel"; + reg = <0x00204000 0x00400000>; + }; + + mtd4@604000 { + label = "phy3250-rootfs"; + reg = <0x00604000 0x039fc000>; + }; + }; +}; + +&ssp0 { + num-cs = <1>; + cs-gpios = <&gpio 3 5 0>; + status = "okay"; + + eeprom: at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + + pl022,interface = <0>; + pl022,com-mode = <0>; + pl022,rx-level-trig = <1>; + pl022,tx-level-trig = <1>; + pl022,ctrl-len = <11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + + at25,byte-len = <0x8000>; + at25,addr-mode = <2>; + at25,page-size = <64>; + }; +}; + +&tsc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi new file mode 100644 index 000000000000..974410918f35 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP LPC32xx SoC + * + * Copyright (C) 2015-2019 Vladimir Zapolskiy + * Copyright 2012 Roland Stigge + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nxp,lpc3220"; + interrupt-parent = <&mic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + clocks { + xtal_32k: xtal_32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32k"; + }; + + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + clock-output-names = "xtal"; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x00000000 0x00000000 0x10000000>, + <0x20000000 0x20000000 0x30000000>, + <0xe0000000 0xe0000000 0x04000000>; + + iram: sram@8000000 { + compatible = "mmio-sram"; + reg = <0x08000000 0x20000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x08000000 0x20000>; + }; + + /* + * Enable either SLC or MLC + */ + slc: flash@20020000 { + compatible = "nxp,lpc3220-slc"; + reg = <0x20020000 0x1000>; + clocks = <&clk LPC32XX_CLK_SLC>; + status = "disabled"; + }; + + mlc: flash@200a8000 { + compatible = "nxp,lpc3220-mlc"; + reg = <0x200a8000 0x11000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_MLC>; + status = "disabled"; + }; + + dma: dma@31000000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x31000000 0x1000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_DMA>; + clock-names = "apb_pclk"; + }; + + usb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x31020000 0x00001000>; + + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: ohci@0 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x0 0x300>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; + status = "disabled"; + }; + + usbd: usbd@0 { + compatible = "nxp,lpc3220-udc"; + reg = <0x0 0x300>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; + status = "disabled"; + }; + + i2cusb: i2c@300 { + compatible = "nxp,pnx-i2c"; + reg = <0x300 0x100>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbclk: clock-controller@f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0xf00 0x100>; + #clock-cells = <1>; + }; + }; + + clcd: clcd@31040000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x31040000 0x1000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + + mac: ethernet@31060000 { + compatible = "nxp,lpc-eth"; + reg = <0x31060000 0x1000>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_MAC>; + status = "disabled"; + }; + + emc: memory-controller@31080000 { + compatible = "arm,pl175", "arm,primecell"; + reg = <0x31080000 0x1000>; + clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe0000000 0x01000000>, + <1 0xe1000000 0x01000000>, + <2 0xe2000000 0x01000000>, + <3 0xe3000000 0x01000000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* + * ssp0 and spi1 are shared pins; + * enable one in your board dts, as needed. + */ + ssp0: spi@20084000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x20084000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SSP0>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20088000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20088000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * ssp1 and spi2 are shared pins; + * enable one in your board dts, as needed. + */ + ssp1: spi@2008c000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x2008c000 0x1000>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SSP1>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@20090000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20090000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2s0: i2s@20094000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x20094000 0x1000>; + status = "disabled"; + }; + + sd: sd@20098000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x20098000 0x1000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SD>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2s1: i2s@2009c000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x2009c000 0x1000>; + status = "disabled"; + }; + + /* UART5 first since it is the default console, ttyS0 */ + uart5: serial@40090000 { + /* actually, ns16550a w/ 64 byte fifos! */ + compatible = "nxp,lpc3220-uart"; + reg = <0x40090000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART5>; + status = "disabled"; + }; + + uart3: serial@40080000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40080000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART3>; + status = "disabled"; + }; + + uart4: serial@40088000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40088000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART4>; + status = "disabled"; + }; + + uart6: serial@40098000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40098000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART6>; + status = "disabled"; + }; + + i2c1: i2c@400a0000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400a0000 0x100>; + interrupt-parent = <&sic1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk LPC32XX_CLK_I2C1>; + }; + + i2c2: i2c@400a8000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400a8000 0x100>; + interrupt-parent = <&sic1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk LPC32XX_CLK_I2C2>; + }; + + mpwm: mpwm@400e8000 { + compatible = "nxp,lpc3220-motor-pwm"; + reg = <0x400e8000 0x78>; + status = "disabled"; + #pwm-cells = <2>; + }; + }; + + fab { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* System Control Block */ + scb { + compatible = "simple-bus"; + ranges = <0x0 0x40004000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + clk: clock-controller@0 { + compatible = "nxp,lpc3220-clk"; + reg = <0x00 0x114>; + #clock-cells = <1>; + + clocks = <&xtal_32k>, <&xtal>; + clock-names = "xtal_32k", "xtal"; + }; + }; + + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; + + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@40014000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40014000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@40018000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40018000 0x1000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart7: serial@4001c000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x4001c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + rtc: rtc@40024000 { + compatible = "nxp,lpc3220-rtc"; + reg = <0x40024000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_RTC>; + }; + + gpio: gpio@40028000 { + compatible = "nxp,lpc3220-gpio"; + reg = <0x40028000 0x1000>; + gpio-controller; + #gpio-cells = <3>; /* bank, pin, flags */ + }; + + timer4: timer@4002c000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4002c000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER4>; + clock-names = "timerclk"; + status = "disabled"; + }; + + timer5: timer@40030000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40030000 0x1000>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER5>; + clock-names = "timerclk"; + status = "disabled"; + }; + + watchdog: watchdog@4003c000 { + compatible = "nxp,pnx4008-wdt"; + reg = <0x4003c000 0x1000>; + clocks = <&clk LPC32XX_CLK_WDOG>; + }; + + timer0: timer@40044000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40044000 0x1000>; + clocks = <&clk LPC32XX_CLK_TIMER0>; + clock-names = "timerclk"; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; + + /* + * TSC vs. ADC: Since those two share the same + * hardware, you need to choose from one of the + * following two and do 'status = "okay";' for one of + * them + */ + + adc: adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_ADC>; + status = "disabled"; + }; + + tsc: tsc@40048000 { + compatible = "nxp,lpc3220-tsc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_ADC>; + status = "disabled"; + }; + + timer1: timer@4004c000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4004c000 0x1000>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER1>; + clock-names = "timerclk"; + }; + + key: key@40050000 { + compatible = "nxp,lpc3220-key"; + reg = <0x40050000 0x1000>; + clocks = <&clk LPC32XX_CLK_KEY>; + interrupt-parent = <&sic1>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@40058000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40058000 0x1000>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER2>; + clock-names = "timerclk"; + status = "disabled"; + }; + + pwm1: pwm@4005c000 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005c000 0x4>; + clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + status = "disabled"; + }; + + pwm2: pwm@4005c004 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005c004 0x4>; + clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + status = "disabled"; + }; + + timer3: timer@40060000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40060000 0x1000>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER3>; + clock-names = "timerclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts new file mode 100644 index 000000000000..beddaba85393 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts @@ -0,0 +1,221 @@ +/* + * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) + * + * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include "dt-bindings/gpio/gpio.h" + +/ { + model = "CIAA NXP LPC4337"; + compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; + + aliases { + serial0 = &uart2; + serial1 = &uart3; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart2; + }; + + memory@28000000 { + device_type = "memory"; + reg = <0x28000000 0x0800000>; /* 8 MB */ + }; +}; + +&pinctrl { + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "p7_7"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + ssp_pins: ssp-pins { + ssp1_cs { + pins = "p6_7"; + function = "gpio"; + bias-pull-up; + bias-disable; + }; + + ssp1_miso_mosi { + pins = "p1_3", "p1_4"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + input-enable; + input-schmitt-disable; + }; + + ssp1_sck { + pins = "pf_4"; + function = "ssp1"; + slew-rate = <1>; + bias-disable; + }; + }; + + uart2_pins: uart2-pins { + uart2_rx_cfg { + pins = "p7_2"; + function = "uart2"; + bias-disable; + input-enable; + }; + + uart2_tx_cfg { + pins = "p7_1"; + function = "uart2"; + bias-disable; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p2_3"; + function = "uart3"; + bias-disable; + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "microchip,24c512", "atmel,24c512"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "microchip,24c512", "atmel,24c512"; + reg = <0x54>; + }; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + +&sct_pwm { + status = "okay"; +}; + +&ssp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp_pins>; + cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; + num-cs = <1>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts new file mode 100644 index 000000000000..93d0c2e99e7c --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -0,0 +1,481 @@ +/* + * Hitex LPC4350 Evaluation Board + * + * Copyright 2015 Ariel D'Alessandro + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4350.dtsi" + +#include "dt-bindings/input/input.h" +#include "dt-bindings/gpio/gpio.h" + +/ { + model = "Hitex LPC4350 Evaluation Board"; + compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + memory@28000000 { + device_type = "memory"; + reg = <0x28000000 0x800000>; /* 8 MB */ + }; + + pca_buttons { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + autorepeat; + + button0 { + label = "joy:right"; + linux,code = ; + gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; + }; + + button1 { + label = "joy:up"; + linux,code = ; + gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; + }; + + + button2 { + label = "joy:enter"; + linux,code = ; + gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "joy:left"; + linux,code = ; + gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; + }; + + button4 { + label = "joy:down"; + linux,code = ; + gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; + }; + + button5 { + label = "user:sw3"; + linux,code = ; + gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; + }; + + button6 { + label = "user:sw4"; + linux,code = ; + gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; + }; + + button7 { + label = "user:sw5"; + linux,code = ; + gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; + }; + }; + + pca_leds { + compatible = "gpio-leds"; + + led0 { + label = "ext:led0"; + gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "ext:led1"; + gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; + }; + + led2 { + label = "ext:led2"; + gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "ext:led3"; + gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; + }; + }; + + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "3v3io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pinctrl { + adc1_pins: adc1-pins { + adc1_pins_cfg { + pins = "pf_9"; + function = "adc"; + input-disable; + bias-disable; + }; + }; + + emc_pins: emc-pins { + emc_addr0_23_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4", "pa_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_data0_15_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_bls0_3_cfg { + pins = "p1_4", "p6_6", "pd_13", "pd_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_cs0_cs2_cfg { + pins = "p1_5", "pd_12"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dqm0_3_cfg { + pins = "p6_12", "p6_10", "pd_0", "pe_13"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0", "clk1", "clk2", "clk3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + enet_mii_pins: enet-mii-pins { + enet_mii_rxd0_3_cfg { + pins = "p1_15", "p0_0", "p9_3", "p9_2"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_txd0_3_cfg { + pins = "p1_18", "p1_20", "p9_4", "p9_5"; + function = "enet"; + bias-disable; + }; + + enet_mii_crs_col_cfg { + pins = "p9_0", "p9_6"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_rx_clk_dv_er_cfg { + pins = "pc_0", "p1_16", "p9_1"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_tx_clk_en_cfg { + pins = "p1_19", "p0_1"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + bias-disable; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + spifi_pins: spifi-pins { + spifi_clk_cfg { + pins = "p3_3"; + function = "spifi"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + spifi_mosi_miso_sio2_3_cfg { + pins = "p3_7", "p3_6", "p3_5", "p3_4"; + function = "spifi"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + spifi_cs_cfg { + pins = "p3_8"; + function = "spifi"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; +}; + +&adc1 { + status = "okay"; + vref-supply = <&vcc>; + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins>; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash@0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition@1 { + label = "kernel"; + reg = <0x040000 0x2C0000>; /* 2.75 MiB */ + }; + + partition@2 { + label = "rootfs"; + reg = <0x300000 0x100000>; /* 1 MiB */ + }; + }; + }; + + cs2 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <2>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <30>; + mpmc,read-access-delay = <90>; + mpmc,page-mode-read-delay = <55>; + mpmc,write-access-delay = <55>; + mpmc,turn-round-delay = <55>; + + ext_sram: sram@2,0 { + compatible = "mmio-sram"; + reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <25000000>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + /* NXP SE97BTP with temperature sensor + eeprom */ + sensor@18 { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + + eeprom@50 { + compatible = "nxp,24c02", "atmel,24c02"; + reg = <0x50>; + }; + + pca_gpio: gpio@24 { + compatible = "nxp,pca9673"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&mac { + status = "okay"; + phy-mode = "mii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_mii_pins>; +}; + +&spifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifi_pins>; + + flash { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition@1 { + label = "kernel"; + reg = <0x040000 0x2c0000>; /* 2.75 MiB */ + }; + + partition@2 { + label = "rootfs"; + reg = <0x300000 0x500000>; /* 5 MiB */ + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi new file mode 100644 index 000000000000..c4422f587055 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi @@ -0,0 +1,39 @@ +/* + * NXP LPC4350 and LPC4330 SoC + * + * Copyright 2015 Ariel D'Alessandro + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4350", "nxp,lpc4330"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts new file mode 100644 index 000000000000..224f80a4a31d --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -0,0 +1,623 @@ +/* + * Embedded Artist LPC4357 Developer's Kit + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include "dt-bindings/input/input.h" +#include "dt-bindings/gpio/gpio.h" + +/ { + model = "Embedded Artists' LPC4357 Developer's Kit"; + compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + memory@28000000 { + device_type = "memory"; + reg = <0x28000000 0x2000000>; /* 32 MB */ + }; + + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "3v3-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* vmmc is controlled by sdmmc host internally */ + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + gpio_joystick { + compatible = "gpio-keys-polled"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_joystick_pins>; + poll-interval = <100>; + autorepeat; + + button0 { + label = "joy_enter"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; + }; + + button1 { + label = "joy_left"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "joy_up"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "joy_right"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; + }; + + button4 { + label = "joy_down"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; + }; + }; + + leds_mmio { + compatible = "gpio-leds"; + + led1 { + gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; + }; + + led3 { + gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; + }; + + led4 { + gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; + }; + + led5 { + gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; + }; + + led6 { + gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; + }; + + led7 { + gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; + }; + + led8 { + gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; + }; + + led9 { + gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; + }; + + led10 { + gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; + }; + + led11 { + gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; + }; + + led12 { + gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; + }; + + led13 { + gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; + }; + + led14 { + gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; + }; + + led15 { + gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; + }; + + led16 { + gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + emc_pins: emc-pins { + emc_addr0_23_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4", "pa_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_data0_31_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3", + "pd_2", "pd_3", "pd_4", "pd_5", + "pd_6", "pd_7", "pd_8", "pd_9", + "pe_5", "pe_6", "pe_7", "pe_8", + "pe_9", "pe_10", "pe_11", "pe_12"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_bls0_3_cfg { + pins = "p1_4", "p6_6", "pd_13", "pd_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_cs0_3_cfg { + pins = "p1_5", "p6_3", "pd_12", "pd_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dqm0_3_cfg { + pins = "p6_12", "p6_10", "pd_0", "pe_13"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0", "clk1", "clk2", "clk3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + gpio_joystick_pins: gpio-joystick-pins { + gpio_joystick_cfg { + pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + bias-pull-down; + input-enable; + }; + + sdmmc_pow_cfg { + pins = "pc_9"; + function = "sdmmc"; + bias-pull-down; + }; + }; + + spifi_pins: spifi-pins { + spifi_clk_cfg { + pins = "p3_3"; + function = "spifi"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + spifi_mosi_miso_sio2_3_cfg { + pins = "p3_7", "p3_6", "p3_5", "p3_4"; + function = "spifi"; + slew-rate = <0>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + spifi_cs_cfg { + pins = "p3_8"; + function = "spifi"; + bias-disable; + }; + }; + + ssp0_pins: ssp0-pins { + ssp0_sck_miso_mosi { + pins = "pf_0", "pf_2", "pf_3"; + function = "ssp0"; + slew-rate = <1>; + bias-pull-down; + input-enable; + input-schmitt-disable; + }; + + ssp0_ssel { + pins = "pf_1"; + function = "ssp0"; + bias-pull-up; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p9_3"; + function = "uart3"; + bias-pull-down; + }; + }; + + usb0_pins: usb0-pins { + usb0_pwr_enable { + pins = "p2_3"; + function = "usb0"; + }; + + usb0_pwr_fault { + pins = "p8_0"; + function = "usb0"; + bias-disable; + input-enable; + }; + }; +}; + +&adc0 { + status = "okay"; + vref-supply = <&vcc>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + mma7455@1d { + compatible = "fsl,mma7455"; + reg = <0x1d>; + }; + + lm75@48 { + compatible = "nxp,lm75"; + reg = <0x48>; + }; + + eeprom@57 { + compatible = "microchip,24c64", "atmel,24c64"; + reg = <0x57>; + }; +}; + +&dac { + status = "okay"; + vref-supply = <&vcc>; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash@0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition@1 { + label = "kernel"; + reg = <0x040000 0x2c0000>; /* 2.75 MiB */ + }; + + partition@2 { + label = "rootfs"; + reg = <0x300000 0x100000>; /* 1 MiB */ + }; + }; + }; + + cs2 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <2>; + mpmc,memory-width = <16>; + + mmio_leds: gpio@2,0 { + compatible = "ti,7416374"; + reg = <2 0 0x2>; + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + +&mmcsd { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; +}; + +&spifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifi_pins>; + + flash { + compatible = "jedec,spi-nor"; + spi-cpol; + spi-cpha; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "data"; + reg = <0 0x200000>; + }; + }; +}; + +&ssp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_pins>; + num-cs = <1>; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts new file mode 100644 index 000000000000..1f84654df50c --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel + * + * Copyright (C) 2016-2018 Vladimir Zapolskiy + */ + +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include + +/ { + model = "MYIR Tech LPC4357 Development Board"; + compatible = "myir,myd-lpc4357", "nxp,lpc4357"; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@28000000 { + device_type = "memory"; + reg = <0x28000000 0x2000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led4 { + gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led5 { + gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led6 { + gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + panel: panel { + compatible = "innolux,at070tn92"; + + port { + panel_input: endpoint { + remote-endpoint = <&lcdc_output>; + }; + }; + }; + + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vcc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pinctrl { + can0_pins: can0-pins { + can_rd_cfg { + pins = "p3_1"; + function = "can0"; + input-enable; + }; + + can_td_cfg { + pins = "p3_2"; + function = "can0"; + }; + }; + + can1_pins: can1-pins { + can_rd_cfg { + pins = "pe_1"; + function = "can1"; + input-enable; + }; + + can_td_cfg { + pins = "pe_0"; + function = "can1"; + }; + }; + + emc_pins: emc-pins { + emc_addr0_22_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_data0_15_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3"; + function = "emc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_cs0_cfg { + pins = "p1_5"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_dqm0_1_cfg { + pins = "p6_12", "p6_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0"; + function = "emc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + }; + + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + input-enable; + input-schmitt-disable; + bias-disable; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + i2c1_pins_cfg { + pins = "pe_15", "pe_13"; + function = "i2c1"; + input-enable; + }; + }; + + lcd_pins: lcd-pins { + lcd_vd0_23_cfg { + pins = "p4_1", "p4_4", "p4_3", "p4_2", + "p8_7", "p8_6", "p8_5", "p8_4", + "p7_5", "p4_8", "p4_10", "p4_9", + "p8_3", "pb_6", "pb_5", "pb_4", + "p7_4", "p7_3", "p7_2", "p7_1", + "pb_3", "pb_2", "pb_1", "pb_0"; + function = "lcd"; + }; + + lcd_vsync_en_dclk_lp_pwr_cfg { + pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; + function = "lcd"; + }; + }; + + led_pins: led-pins { + led_1_6_cfg { + pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; + function = "gpio"; + bias-pull-down; + }; + }; + + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + input-enable; + bias-pull-down; + }; + }; + + spifi_pins: spifi-pins { + spifi_sck_cfg { + pins = "p3_3"; + function = "spifi"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + spifi_mosi_miso_sio2_sio3_cfg { + pins = "p3_7", "p3_6", "p3_5", "p3_4"; + function = "spifi"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + spifi_cs_cfg { + pins = "p3_8"; + function = "spifi"; + bias-disable; + }; + }; + + ssp1_pins: ssp1-pins { + ssp1_sck_cfg { + pins = "pf_4"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_miso_cfg { + pins = "pf_6"; + function = "ssp1"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_mosi_cfg { + pins = "pf_7"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_ssel_cfg { + pins = "pf_5"; + function = "gpio"; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rxd_cfg { + pins = "pf_11"; + function = "uart0"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + uart0_clk_dir_txd_cfg { + pins = "pf_8", "pf_9", "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; + + uart1_pins: uart1-pins { + uart1_rxd_cfg { + pins = "pc_14"; + function = "uart1"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart1_dtr_txd_cfg { + pins = "pc_12", "pc_13"; + function = "uart1"; + bias-pull-down; + }; + }; + + uart2_pins: uart2-pins { + uart2_rxd_cfg { + pins = "pa_2"; + function = "uart2"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart2_txd_cfg { + pins = "pa_1"; + function = "uart2"; + bias-pull-down; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart3_tx_cfg { + pins = "p2_3"; + function = "uart3"; + bias-pull-down; + }; + }; + + usb0_pins: usb0-pins { + usb0_pwr_enable_cfg { + pins = "p6_3"; + function = "usb0"; + }; + + usb0_pwr_fault_cfg { + pins = "p8_0"; + function = "usb0"; + bias-disable; + input-enable; + }; + }; +}; + +&adc1 { + status = "okay"; + vref-supply = <&vcc>; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; +}; + +/* Pin conflict with EMC, muxed by JP5 and JP6 */ +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + /* SST/Microchip SST39VF1601 */ + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + sensor@49 { + compatible = "lm75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + }; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + max-memory-bandwidth = <92240000>; + + port { + lcdc_output: endpoint { + remote-endpoint = <&panel_input>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; + phy-handle = <&phy1>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&mmcsd { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; + bus-width = <4>; + vmmc-supply = <&vmmc>; +}; + +/* Pin conflict with SSP0, the latter is routed to J17 pin header */ +&spifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifi_pins>; + + /* Atmel AT25DF321A */ + flash { + compatible = "jedec,spi-nor"; + spi-max-frequency = <51000000>; + spi-cpol; + spi-cpha; + }; +}; + +&ssp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_pins>; + num-cs = <1>; + cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; +}; + +/* Routed to J17 pin header */ +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +/* RS485 */ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +/* Routed to J17 pin header */ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; +}; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi new file mode 100644 index 000000000000..72f12db8d53a --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi @@ -0,0 +1,43 @@ +/* + * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4357"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +}; + +&eeprom { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/Makefile b/arch/arm/boot/dts/nxp/ls/Makefile new file mode 100644 index 000000000000..3cb1d516f6fb --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-iot.dtb \ + ls1021a-moxa-uc-8410a.dtb \ + ls1021a-qds.dtb \ + ls1021a-tsn.dtb \ + ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts new file mode 100644 index 000000000000..ce8e26d7791f --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021-2022 NXP + * + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A-IOT Board"; + compatible = "fsl,ls1021a-iot", "fsl,ls1021a"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator-3V3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2V5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + frame-master; + bitclock-master; + }; + }; +}; + +&can0{ + status = "disabled"; +}; + +&can1{ + status = "disabled"; +}; + +&can2{ + status = "disabled"; +}; + +&can3{ + status = "okay"; +}; + +&dcu { + display = <&display>; + status = "okay"; + + display: display@0 { + bits-per-pixel = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: mode0 { + clock-frequency = <25000000>; + hactive = <640>; + vactive = <480>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <12>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&enet0 { + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&phy3>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&esdhc{ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9555: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgtl5000: audio-codec@2a { + #sound-dai-cells = <0x0>; + compatible = "fsl,sgtl5000"; + reg = <0x2a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_2p5v>; + clocks = <&sys_mclk>; + }; + + max1239: adc@35 { + compatible = "maxim,max1239"; + reg = <0x35>; + #io-channel-cells = <1>; + }; + + ina2201: core-monitor@44 { + compatible = "ti,ina220"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + ina2202: current-monitor@45 { + compatible = "ti,ina220"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + lm75b: thermal-monitor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + num-cs = <2>; + status = "okay"; + + s25fl128s: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts new file mode 100644 index 000000000000..d2cae8c7d7a6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/ + * + * Author: Harry YJ Jhou (周亞諄) + * Jimmy Chen (陳永達) + * SZ Lin (林上智) + */ + +/dts-v1/; + +#include +#include +#include "ls1021a.dtsi" + +/ { + model = "Moxa UC-8410A"; + compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; + + aliases { + enet0_rgmii_phy = &rgmii_phy0; + enet1_rgmii_phy = &rgmii_phy1; + enet2_rgmii_phy = &rgmii_phy2; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + cel-pwr { + label = "UC8410A:CEL-PWR"; + gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + cel-reset { + label = "UC8410A:CEL-RESET"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + str-led { + label = "UC8410A:RED:PROG"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + sw-ready { + label = "UC8410A:GREEN:SWRDY"; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + beeper { + label = "UC8410A:BEEP"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + prog-led0 { + label = "UC8410A:GREEN:PROG2"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + prog-led1 { + label = "UC8410A:GREEN:PROG1"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + prog-led2 { + label = "UC8410A:GREEN:PROG0"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + wifi-signal0 { + label = "UC8410A:GREEN:CEL2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + wifi-signal1 { + label = "UC8410A:GREEN:CEL1"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + wifi-signal2 { + label = "UC8410A:GREEN:CEL0"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + cpu-diag-red { + label = "UC8410A:RED:DIA"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + cpu-diag-green { + label = "UC8410A:GREEN:DIA"; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + cpu-diag-yellow { + label = "UC8410A:YELLOW:DIA"; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pushbtn-key { + label = "push button key"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,code = ; + default-state = "on"; + }; + }; +}; + +&enet0 { + phy-handle = <&rgmii_phy0>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&enet1 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + tpm@20 { + compatible = "infineon,slb9635tt"; + reg = <0x20>; + }; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "marvell,88e1118"; + reg = <0x0>; + marvell,reg-init = + <3 0x11 0 0x4415>, /* Reg 3,17 */ + <3 0x10 0 0x77>; /* Reg 3,16 */ + }; + + rgmii_phy1: ethernet-phy@1 { + compatible = "marvell,88e1118"; + reg = <0x1>; + marvell,reg-init = + <3 0x11 0 0x4415>, /* Reg 3,17 */ + <3 0x10 0 0x77>; /* Reg 3,16 */ + }; + + rgmii_phy2: ethernet-phy@2 { + compatible = "marvell,88e1118"; + reg = <0x2>; + marvell,reg-init = + <3 0x11 0 0x4415>, /* Reg 3,17 */ + <3 0x10 0 0x77>; /* Reg 3,16 */ + }; +}; + +&qspi { + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl064l", "spansion,s25fl164k"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + reg = <0>; + + partitions@0 { + label = "U-Boot"; + reg = <0x0 0x180000>; + }; + + partitions@180000 { + label = "U-Boot Env"; + reg = <0x180000 0x680000>; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts new file mode 100644 index 000000000000..f1acb97aee69 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + compatible = "fsl,ls1021a-qds", "fsl,ls1021a"; + + aliases { + enet0_rgmii_phy = &rgmii_phy1; + enet1_rgmii_phy = &rgmii_phy2; + enet2_rgmii_phy = &rgmii_phy3; + enet0_sgmii_phy = &sgmii_phy1c; + enet1_sgmii_phy = &sgmii_phy1d; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + }; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1c>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1d>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy3>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&esdhc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = ; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + codec: sgtl5000@2a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x2a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&sys_mclk>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000>, + <0x2 0x0 0x0 0x7e800000 0x00010000>, + <0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + big-endian; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-mfd"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1[2:0] */ + + /* Onboard PHYs */ + ls1021amdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + + ls1021amdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + ls1021amdio2: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + + ls1021amdio3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1c: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + ls1021amdio4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1d: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + }; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "disabled"; +}; + +&can3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts new file mode 100644 index 000000000000..1ea32fff4120 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright 2016-2018 NXP Semiconductors + * Copyright 2019 Vladimir Oltean + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "NXP LS1021A-TSN Board"; + compatible = "fsl,ls1021a-tsn", "fsl,ls1021a"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_vdda_codec: regulator-3V3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vddio_codec: regulator-2V5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + /* ADG704BRMZ 1:4 SPI mux/demux */ + sja1105: ethernet-switch@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,sja1105t"; + /* 12 MHz */ + spi-max-frequency = <12000000>; + /* Sample data on trailing clock edge */ + spi-cpha; + /* SPI controller settings for SJA1105 timing requirements */ + fsl,spi-cs-sck-delay = <1000>; + fsl,spi-sck-cs-delay = <1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + /* ETH5 written on chassis */ + label = "swp5"; + phy-handle = <&rgmii_phy6>; + phy-mode = "rgmii-id"; + reg = <0>; + }; + + port@1 { + /* ETH2 written on chassis */ + label = "swp2"; + phy-handle = <&rgmii_phy3>; + phy-mode = "rgmii-id"; + reg = <1>; + }; + + port@2 { + /* ETH3 written on chassis */ + label = "swp3"; + phy-handle = <&rgmii_phy4>; + phy-mode = "rgmii-id"; + reg = <2>; + }; + + port@3 { + /* ETH4 written on chassis */ + label = "swp4"; + phy-handle = <&rgmii_phy5>; + phy-mode = "rgmii-id"; + reg = <3>; + }; + + port@4 { + /* Internal port connected to eth2 */ + ethernet = <&enet2>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + reg = <4>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy2>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +/* RGMII delays added via PCB traces */ +&enet2 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&esdhc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + /* 3 axis accelerometer */ + accelerometer@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + }; + + /* Audio codec (SAI2) */ + audio-codec@2a { + compatible = "fsl,sgtl5000"; + VDDIO-supply = <®_vddio_codec>; + VDDA-supply = <®_vdda_codec>; + #sound-dai-cells = <0>; + clocks = <&sys_mclk>; + reg = <0x2a>; + }; + + /* Current sensing circuit for 1V VDDCORE PMIC rail */ + current-sensor@44 { + compatible = "ti,ina220"; + shunt-resistor = <1000>; + reg = <0x44>; + }; + + /* Current sensing circuit for 12V VCC rail */ + current-sensor@45 { + compatible = "ti,ina220"; + shunt-resistor = <1000>; + reg = <0x45>; + }; + + /* Thermal monitor - case */ + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + /* Thermal monitor - chip */ + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + }; + + /* Unsupported devices: + * - FXAS21002C Gyroscope at 0x20 + * - TI ADS7924 4-channel ADC at 0x49 + */ +}; + +&ifc { + status = "disabled"; +}; + +&lpuart0 { + status = "okay"; +}; + +&lpuart3 { + status = "okay"; +}; + +&mdio0 { + /* AR8031 */ + sgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + /* SGMII1_PHY_INT_B: connected to IRQ2, active low */ + interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; + }; + + /* AR8031 */ + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + /* SGMII2_PHY_INT_B: connected to IRQ2, active low */ + interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; + }; + + /* BCM5464 quad PHY */ + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + rgmii_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + + rgmii_phy5: ethernet-phy@5 { + reg = <0x5>; + }; + + rgmii_phy6: ethernet-phy@6 { + reg = <0x6>; + }; + + /* SGMII PCS for enet0 */ + tbi0: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + /* SGMII PCS for enet1 */ + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + status = "okay"; + + flash@0 { + /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RCW"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "U-Boot"; + reg = <0x40000 0x300000>; + }; + + partition@340000 { + label = "U-Boot Env"; + reg = <0x340000 0x100000>; + }; + }; + }; +}; + +&sai2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts new file mode 100644 index 000000000000..f5c03871b205 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A TWR Board"; + compatible = "fsl,ls1021a-twr", "fsl,ls1021a"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + }; + }; + + panel: panel { + compatible = "nec,nl4827hc19-05b"; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; + }; +}; + +&dcu { + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dspiflash: s25fl064k@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl064k"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy0>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + +}; + +&i2c1 { + status = "okay"; + codec: sgtl5000@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&sys_mclk>; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + big-endian; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi0: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&esdhc { + status = "okay"; +}; + +&qspi { + status = "okay"; + + n25q128a130: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&sai1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "disabled"; +}; + +&can3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi new file mode 100644 index 000000000000..49c78c84cd5d --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -0,0 +1,987 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + */ + +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + crypto = &crypto; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + rtc1 = &ftm_alarm0; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + serial5 = &lpuart5; + sysclk = &sysclk; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + clocks = <&clockgen 1 0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + clocks = <&clockgen 1 0>; + #cooling-cells = <2>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&dcfg>; + offset = <0xb0>; + mask = <0x02>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + device_type = "soc"; + interrupt-parent = <&gic>; + ranges; + + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + big-endian; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0x0 0x1000>, + <0x0 0x1402000 0x0 0x2000>, + <0x0 0x1404000 0x0 0x2000>, + <0x0 0x1406000 0x0 0x2000>; + interrupts = ; + + }; + + msi1: msi-controller@1570e00 { + compatible = "fsl,ls1021a-msi"; + reg = <0x0 0x1570e00 0x0 0x8>; + msi-controller; + interrupts = ; + }; + + msi2: msi-controller@1570e08 { + compatible = "fsl,ls1021a-msi"; + reg = <0x0 0x1570e08 0x0 0x8>; + msi-controller; + interrupts = ; + }; + + ifc: memory-controller@1530000 { + compatible = "fsl,ifc"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + }; + + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg", "syscon"; + reg = <0x0 0x1ee0000 0x0 0x1000>; + big-endian; + }; + + qspi: spi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x20000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + status = "disabled"; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = ; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x0 0x20220520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = ; + clocks = <&clockgen 4 1>; + dma-coherent; + status = "disabled"; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1570000 0x10000>; + + extirq: interrupt-controller@1ac { + compatible = "fsl,ls1021a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1ac 4>; + interrupt-map = + <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0x7 0x0>; + }; + }; + + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <7>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x1700000 0x0 0x100000>; + ranges = <0x0 0x0 0x1700000 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + + }; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1021a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + tmu: tmu@1f00000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f00000 0x0 0x10000>; + interrupts = ; + fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; + fsl,tmu-calibration = <0x00000000 0x00000020>, + <0x00000001 0x00000024>, + <0x00000002 0x0000002a>, + <0x00000003 0x00000032>, + <0x00000004 0x00000038>, + <0x00000005 0x0000003e>, + <0x00000006 0x00000043>, + <0x00000007 0x0000004a>, + <0x00000008 0x00000050>, + <0x00000009 0x00000059>, + <0x0000000a 0x0000005f>, + <0x0000000b 0x00000066>, + + <0x00010000 0x00000023>, + <0x00010001 0x0000002b>, + <0x00010002 0x00000033>, + <0x00010003 0x0000003a>, + <0x00010004 0x00000042>, + <0x00010005 0x0000004a>, + <0x00010006 0x00000054>, + <0x00010007 0x0000005c>, + <0x00010008 0x00000065>, + <0x00010009 0x0000006f>, + + <0x00020000 0x00000029>, + <0x00020001 0x00000033>, + <0x00020002 0x0000003d>, + <0x00020003 0x00000048>, + <0x00020004 0x00000054>, + <0x00020005 0x00000060>, + <0x00020006 0x0000006c>, + + <0x00030000 0x00000025>, + <0x00030001 0x00000033>, + <0x00030002 0x00000043>, + <0x00030003 0x00000055>; + #thermal-sensor-cells = <1>; + }; + + dspi0: spi@2100000 { + compatible = "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = ; + clock-names = "dspi"; + clocks = <&clockgen 4 1>; + spi-num-chipselects = <6>; + big-endian; + status = "disabled"; + }; + + dspi1: spi@2110000 { + compatible = "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = ; + clock-names = "dspi"; + clocks = <&clockgen 4 1>; + spi-num-chipselects = <6>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 38>, <&edma0 1 39>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 36>, <&edma0 1 37>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 34>, <&edma0 1 35>; + status = "disabled"; + }; + + uart0: serial@21c0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = ; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart1: serial@21c0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = ; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart2: serial@21d0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = ; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart3: serial@21d0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = ; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + counter0: counter@29d0000 { + compatible = "fsl,ftm-quaddec"; + reg = <0x0 0x29d0000 0x0 0x10000>; + big-endian; + status = "disabled"; + }; + + counter1: counter@29e0000 { + compatible = "fsl,ftm-quaddec"; + reg = <0x0 0x29e0000 0x0 0x10000>; + big-endian; + status = "disabled"; + }; + + counter2: counter@29f0000 { + compatible = "fsl,ftm-quaddec"; + reg = <0x0 0x29f0000 0x0 0x10000>; + big-endian; + status = "disabled"; + }; + + counter3: counter@2a00000 { + compatible = "fsl,ftm-quaddec"; + reg = <0x0 0x2a00000 0x0 0x10000>; + big-endian; + status = "disabled"; + }; + + gpio0: gpio@2300000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + pwm0: pwm@29d0000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x29d0000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm1: pwm@29e0000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x29e0000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm2: pwm@29f0000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x29f0000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm3: pwm@2a00000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a00000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm4: pwm@2a10000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a10000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm5: pwm@2a20000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a20000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm6: pwm@2a30000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a30000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm7: pwm@2a40000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a40000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + wdog0: watchdog@2ad0000 { + compatible = "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "wdog-en"; + big-endian; + }; + + sai1: sai@2b50000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b50000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 47>, + <&edma0 1 46>; + status = "disabled"; + }; + + sai2: sai@2b60000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b60000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 45>, + <&edma0 1 44>; + status = "disabled"; + }; + + edma0: dma-controller@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clockgen 4 1>, + <&clockgen 4 1>; + }; + + dcu: dcu@2ce0000 { + compatible = "fsl,ls1021a-dcu"; + reg = <0x0 0x2ce0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 0>, + <&clockgen 4 0>; + clock-names = "dcu", "pix"; + big-endian; + status = "disabled"; + }; + + mdio0: mdio@2d24000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2d24000 0x0 0x4000>, + <0x0 0x2d10030 0x0 0x4>; + }; + + mdio1: mdio@2d64000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2d64000 0x0 0x4000>, + <0x0 0x2d50030 0x0 0x4>; + }; + + ptp_clock@2d10e00 { + compatible = "fsl,etsec-ptp"; + reg = <0x0 0x2d10e00 0x0 0xb0>; + interrupts = ; + fsl,tclk-period = <5>; + fsl,tmr-prsc = <2>; + fsl,tmr-add = <0xaaaaaaab>; + fsl,tmr-fiper1 = <999999995>; + fsl,tmr-fiper2 = <999999995>; + fsl,max-adj = <499999999>; + fsl,extts-fifo; + }; + + enet0: ethernet@2d10000 { + compatible = "fsl,etsec2"; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + fsl,magic-packet; + ranges; + dma-coherent; + + queue-group@2d10000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d10000 0x0 0x1000>; + interrupts = , + , + ; + }; + + queue-group@2d14000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d14000 0x0 0x1000>; + interrupts = , + , + ; + }; + }; + + enet1: ethernet@2d50000 { + compatible = "fsl,etsec2"; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + ranges; + dma-coherent; + + queue-group@2d50000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d50000 0x0 0x1000>; + interrupts = , + , + ; + }; + + queue-group@2d54000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d54000 0x0 0x1000>; + interrupts = , + , + ; + }; + }; + + enet2: ethernet@2d90000 { + compatible = "fsl,etsec2"; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + ranges; + dma-coherent; + + queue-group@2d90000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d90000 0x0 0x1000>; + interrupts = , + , + ; + }; + + queue-group@2d94000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d94000 0x0 0x1000>; + interrupts = , + , + ; + }; + }; + + usb2: usb@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + interrupts = ; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + usb3: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + }; + + pcie@3400000 { + compatible = "fsl,ls1021a-pcie"; + reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = ; /* controller interrupt */ + fsl,pcie-scfg = <&scfg 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */ + <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi1>, <&msi2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,ls1021a-pcie"; + reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ + <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = ; + fsl,pcie-scfg = <&scfg 1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */ + <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi1>, <&msi2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + can0: can@2a70000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + can1: can@2a80000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + can2: can@2a90000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + can3: can@2aa0000 { + compatible = "fsl,ls1021ar2-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + big-endian; + status = "disabled"; + }; + + ocram1: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x0 0x10000000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x10000000 0x10000>; + }; + + ocram2: sram@10010000 { + compatible = "mmio-sram"; + reg = <0x0 0x10010000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x10010000 0x10000>; + }; + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8389000 0x0 0x1000>, /* Status regs */ + <0x0 0x838a000 0x0 0x2000>; /* Block regs */ + interrupts = , + , + ; + interrupt-names = "qdma-error", + "qdma-queue0", "qdma-queue1"; + #dma-cells = <2>; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x1000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + }; + + rcpm: power-controller@1ee2140 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x8>; + #fsl,rcpm-wakeup-cells = <2>; + #power-domain-cells = <0>; + }; + + ftm_alarm0: timer0@29d0000 { + compatible = "fsl,ls1021a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + reg-names = "ftm"; + fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; + interrupts = ; + big-endian; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile new file mode 100644 index 000000000000..a430d04f9c69 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MXS) += \ + imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx23-sansa.dtb \ + imx23-stmp378x_devb.dtb \ + imx23-xfi3.dtb \ + imx28-apf28.dtb \ + imx28-apf28dev.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ + imx28-cfa10037.dtb \ + imx28-cfa10049.dtb \ + imx28-cfa10055.dtb \ + imx28-cfa10056.dtb \ + imx28-cfa10057.dtb \ + imx28-cfa10058.dtb \ + imx28-duckbill-2-485.dtb \ + imx28-duckbill-2.dtb \ + imx28-duckbill-2-enocean.dtb \ + imx28-duckbill-2-spi.dtb \ + imx28-duckbill.dtb \ + imx28-eukrea-mbmx283lc.dtb \ + imx28-eukrea-mbmx287lc.dtb \ + imx28-evk.dtb \ + imx28-m28cu3.dtb \ + imx28-m28evk.dtb \ + imx28-sps1.dtb \ + imx28-ts4600.dtb \ + imx28-tx28.dtb \ + imx28-xea.dtb diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts new file mode 100644 index 000000000000..3b609d987d88 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. + +/dts-v1/; +#include "imx23.dtsi" + +/ { + model = "Freescale i.MX23 Evaluation Kit"; + compatible = "fsl,imx23-evk", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 18 0>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + apb@80000000 { + apbh@80000000 { + nand-controller@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; + status = "okay"; + }; + + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_LCD_RESET__GPIO_1_18 + MX23_PAD_PWM3__GPIO_1_29 + MX23_PAD_PWM4__GPIO_1_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + apbx@80040000 { + lradc@80050000 { + status = "okay"; + fsl,lradc-touchscreen-wires = <4>; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + status = "okay"; + }; + }; + + backlight_display: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts new file mode 100644 index 000000000000..0729e72f2283 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +/dts-v1/; +#include +#include "imx23.dtsi" + +/ { + model = "i.MX23 Olinuxino Low Cost Board"; + compatible = "olimex,imx23-olinuxino", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + broken-cd; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_ALE__GPIO_0_17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pin_gpio2_1: led_gpio2_1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DETECT__GPIO_2_1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + + ssp1: spi@80034000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + lradc@80050000 { + status = "okay"; + }; + + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_b>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "host"; + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio2_1>; + + user { + label = "green"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h new file mode 100644 index 000000000000..468c079f3c2b --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h @@ -0,0 +1,327 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header providing constants for i.MX23 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann + */ + +#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ +#define __DT_BINDINGS_MX23_PINCTRL_H__ + +#include "mxs-pinfunc.h" + +#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 +#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 +#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 +#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 +#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 +#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 +#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 +#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 +#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 +#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 +#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 +#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 +#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 +#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 +#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 +#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 +#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 +#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 +#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 +#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 +#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 +#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 +#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 +#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 +#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 +#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 +#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 +#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 +#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 +#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 +#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 +#define MX23_PAD_LCD_D00__LCD_D00 0x1000 +#define MX23_PAD_LCD_D01__LCD_D01 0x1010 +#define MX23_PAD_LCD_D02__LCD_D02 0x1020 +#define MX23_PAD_LCD_D03__LCD_D03 0x1030 +#define MX23_PAD_LCD_D04__LCD_D04 0x1040 +#define MX23_PAD_LCD_D05__LCD_D05 0x1050 +#define MX23_PAD_LCD_D06__LCD_D06 0x1060 +#define MX23_PAD_LCD_D07__LCD_D07 0x1070 +#define MX23_PAD_LCD_D08__LCD_D08 0x1080 +#define MX23_PAD_LCD_D09__LCD_D09 0x1090 +#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 +#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 +#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 +#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 +#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 +#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 +#define MX23_PAD_LCD_D16__LCD_D16 0x1100 +#define MX23_PAD_LCD_D17__LCD_D17 0x1110 +#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 +#define MX23_PAD_LCD_RS__LCD_RS 0x1130 +#define MX23_PAD_LCD_WR__LCD_WR 0x1140 +#define MX23_PAD_LCD_CS__LCD_CS 0x1150 +#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 +#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 +#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 +#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 +#define MX23_PAD_PWM0__PWM0 0x11a0 +#define MX23_PAD_PWM1__PWM1 0x11b0 +#define MX23_PAD_PWM2__PWM2 0x11c0 +#define MX23_PAD_PWM3__PWM3 0x11d0 +#define MX23_PAD_PWM4__PWM4 0x11e0 +#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 +#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 +#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 +#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 +#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 +#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 +#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 +#define MX23_PAD_ROTARYA__ROTARYA 0x2070 +#define MX23_PAD_ROTARYB__ROTARYB 0x2080 +#define MX23_PAD_EMI_A00__EMI_A00 0x2090 +#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 +#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 +#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 +#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 +#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 +#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 +#define MX23_PAD_EMI_A07__EMI_A07 0x2100 +#define MX23_PAD_EMI_A08__EMI_A08 0x2110 +#define MX23_PAD_EMI_A09__EMI_A09 0x2120 +#define MX23_PAD_EMI_A10__EMI_A10 0x2130 +#define MX23_PAD_EMI_A11__EMI_A11 0x2140 +#define MX23_PAD_EMI_A12__EMI_A12 0x2150 +#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 +#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 +#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 +#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 +#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 +#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 +#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 +#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 +#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 +#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 +#define MX23_PAD_EMI_D00__EMI_D00 0x3000 +#define MX23_PAD_EMI_D01__EMI_D01 0x3010 +#define MX23_PAD_EMI_D02__EMI_D02 0x3020 +#define MX23_PAD_EMI_D03__EMI_D03 0x3030 +#define MX23_PAD_EMI_D04__EMI_D04 0x3040 +#define MX23_PAD_EMI_D05__EMI_D05 0x3050 +#define MX23_PAD_EMI_D06__EMI_D06 0x3060 +#define MX23_PAD_EMI_D07__EMI_D07 0x3070 +#define MX23_PAD_EMI_D08__EMI_D08 0x3080 +#define MX23_PAD_EMI_D09__EMI_D09 0x3090 +#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 +#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 +#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 +#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 +#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 +#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 +#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 +#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 +#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 +#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 +#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 +#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 +#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 +#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 +#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 +#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 +#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 +#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 +#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 +#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 +#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 +#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 +#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 +#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 +#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 +#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 +#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 +#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 +#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 +#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 +#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 +#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 +#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 +#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 +#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 +#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 +#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 +#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 +#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 +#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 +#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 +#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 +#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 +#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 +#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 +#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 +#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 +#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 +#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 +#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 +#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 +#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 +#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 +#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 +#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 +#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 +#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 +#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 +#define MX23_PAD_PWM0__ROTARYA 0x11a1 +#define MX23_PAD_PWM1__ROTARYB 0x11b1 +#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 +#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 +#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 +#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 +#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 +#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 +#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 +#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 +#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 +#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 +#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 +#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 +#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 +#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 +#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 +#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 +#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 +#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 +#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 +#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 +#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 +#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 +#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 +#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 +#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 +#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 +#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 +#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 +#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 +#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 +#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 +#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 +#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 +#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 +#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 +#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 +#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 +#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 +#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 +#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 +#define MX23_PAD_PWM0__DUART_RX 0x11a2 +#define MX23_PAD_PWM1__DUART_TX 0x11b2 +#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 +#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 +#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 +#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 +#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 +#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 +#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 +#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 +#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 +#define MX23_PAD_ROTARYA__SPDIF 0x2072 +#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 +#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 +#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 +#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 +#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 +#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 +#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 +#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 +#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 +#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 +#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 +#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 +#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 +#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 +#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 +#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 +#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 +#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 +#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 +#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 +#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 +#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 +#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 +#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 +#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 +#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 +#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 +#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 +#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 +#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 +#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 +#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 +#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 +#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 +#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 +#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 +#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 +#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 +#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 +#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 +#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 +#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 +#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 +#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 +#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 +#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 +#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 +#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 +#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 +#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 +#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 +#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 +#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 +#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 +#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 +#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 +#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 +#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 +#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 +#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 +#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 +#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 +#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 +#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 +#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 +#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 +#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 +#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 +#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 +#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 +#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 +#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 +#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 +#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 +#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 +#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 +#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 +#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 +#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 +#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 +#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 +#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 +#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 +#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 +#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 +#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 +#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 +#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 +#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 +#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 +#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 +#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 +#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 +#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 +#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 + +#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts new file mode 100644 index 000000000000..46057d9bf555 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2013-2016 Marek Vasut + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/dts-v1/; +#include +#include "imx23.dtsi" + +/ { + model = "SanDisk Sansa Fuze+"; + compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + cd-inverted; + status = "okay"; + }; + + ssp1: spi@80034000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_vddio_sd1>; + non-removable; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D08__GPIO_0_8 + MX23_PAD_PWM3__GPIO_1_29 + MX23_PAD_AUART1_RTS__GPIO_0_27 + MX23_PAD_AUART1_CTS__GPIO_0_26 + MX23_PAD_I2C_SCL__I2C_SCL + MX23_PAD_I2C_SDA__I2C_SDA + MX23_PAD_LCD_DOTCK__GPIO_1_22 + MX23_PAD_LCD_HSYNC__GPIO_1_24 + MX23_PAD_PWM3__GPIO_1_29 + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + lradc@80050000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "peripheral"; + status = "okay"; + }; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 8 0>; + }; + + reg_vddio_sd1: regulator-vddio-sd1 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + + reg_vdd_touchpad: regulator-vdd-touchpad0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-touchpad0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + reg_vdd_tuner: regulator-vdd-tuner0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-tuner0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 29 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = < + &gpio1 24 0 /* SDA */ + &gpio1 22 0 /* SCL */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + }; + + i2c-1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = < + &gpio0 31 0 /* SDA */ + &gpio0 30 0 /* SCL */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + + touch: touch@20 { + compatible = "synaptics,synaptics_i2c"; + reg = <0x20>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts new file mode 100644 index 000000000000..da4b88f32eaa --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "imx23.dtsi" + +/ { + model = "Freescale STMP378x Development Board"; + compatible = "fsl,stmp378x-devb", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_PWM3__GPIO_1_29 + MX23_PAD_PWM4__GPIO_1_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + }; + + apbx@80040000 { + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_vddio_sd0: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts new file mode 100644 index 000000000000..b1d8210f3ecc --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2013-2016 Marek Vasut + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/dts-v1/; +#include "imx23.dtsi" + +/ { + model = "Creative ZEN X-Fi3"; + compatible = "creative,x-fi3", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + cd-inverted; + status = "okay"; + }; + + ssp1: spi@80034000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_4bit_pins_a>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + key_pins_a: keys@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_ROTARYA__GPIO_2_7 + MX23_PAD_ROTARYB__GPIO_2_8 + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + }; + }; + + apbx@80040000 { + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_a>; + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart1: serial@8006e000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + lradc@80050000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "peripheral"; + status = "okay"; + }; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 7 0>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + key-voldown { + label = "volume-down"; + linux,code = <114>; + gpios = <&gpio2 7 0>; + debounce-interval = <20>; + }; + + key-volup { + label = "volume-up"; + linux,code = <115>; + gpios = <&gpio2 8 0>; + debounce-interval = <20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi new file mode 100644 index 000000000000..a3668a0827fc --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. + +#include "imx23-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&icoll>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + serial0 = &auart0; + serial1 = &auart1; + spi0 = &ssp0; + spi1 = &ssp1; + usbphy0 = &usbphy0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + apb@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x80000>; + ranges; + + apbh@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x40000>; + ranges; + + icoll: interrupt-controller@80000000 { + compatible = "fsl,imx23-icoll", "fsl,icoll"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x80000000 0x2000>; + }; + + dma_apbh: dma-controller@80004000 { + compatible = "fsl,imx23-dma-apbh"; + reg = <0x80004000 0x2000>; + interrupts = <0 14 20 0 + 13 13 13 13>; + #dma-cells = <1>; + dma-channels = <8>; + clocks = <&clks 15>; + }; + + ecc@80008000 { + reg = <0x80008000 0x2000>; + status = "disabled"; + }; + + nand-controller@8000c000 { + compatible = "fsl,imx23-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <56>; + interrupt-names = "bch"; + clocks = <&clks 34>; + clock-names = "gpmi_io"; + dmas = <&dma_apbh 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp0: spi@80010000 { + reg = <0x80010000 0x2000>; + interrupts = <15>; + clocks = <&clks 33>; + dmas = <&dma_apbh 1>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + etm@80014000 { + reg = <0x80014000 0x2000>; + status = "disabled"; + }; + + pinctrl@80018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-pinctrl", "simple-bus"; + reg = <0x80018000 0x2000>; + + gpio0: gpio@0 { + compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; + reg = <0>; + interrupts = <16>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@1 { + compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; + reg = <1>; + interrupts = <17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2 { + compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; + reg = <2>; + interrupts = <18>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + duart_pins_a: duart@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_PWM0__DUART_RX + MX23_PAD_PWM1__DUART_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_AUART1_RX__AUART1_RX + MX23_PAD_AUART1_TX__AUART1_TX + MX23_PAD_AUART1_CTS__AUART1_CTS + MX23_PAD_AUART1_RTS__AUART1_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_I2C_SCL__AUART1_TX + MX23_PAD_I2C_SDA__AUART1_RX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D14__AUART2_RX + MX23_PAD_GPMI_D15__AUART2_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D00__GPMI_D00 + MX23_PAD_GPMI_D01__GPMI_D01 + MX23_PAD_GPMI_D02__GPMI_D02 + MX23_PAD_GPMI_D03__GPMI_D03 + MX23_PAD_GPMI_D04__GPMI_D04 + MX23_PAD_GPMI_D05__GPMI_D05 + MX23_PAD_GPMI_D06__GPMI_D06 + MX23_PAD_GPMI_D07__GPMI_D07 + MX23_PAD_GPMI_CLE__GPMI_CLE + MX23_PAD_GPMI_ALE__GPMI_ALE + MX23_PAD_GPMI_RDY0__GPMI_RDY0 + MX23_PAD_GPMI_RDY1__GPMI_RDY1 + MX23_PAD_GPMI_WPN__GPMI_WPN + MX23_PAD_GPMI_WRN__GPMI_WRN + MX23_PAD_GPMI_RDN__GPMI_RDN + MX23_PAD_GPMI_CE1N__GPMI_CE1N + MX23_PAD_GPMI_CE0N__GPMI_CE0N + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpmi_pins_fixup: gpmi-pins-fixup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_WPN__GPMI_WPN + MX23_PAD_GPMI_WRN__GPMI_WRN + MX23_PAD_GPMI_RDN__GPMI_RDN + >; + fsl,drive-strength = ; + }; + + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DATA0__SSP1_DATA0 + MX23_PAD_SSP1_DATA1__SSP1_DATA1 + MX23_PAD_SSP1_DATA2__SSP1_DATA2 + MX23_PAD_SSP1_DATA3__SSP1_DATA3 + MX23_PAD_SSP1_CMD__SSP1_CMD + MX23_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc0_8bit_pins_a: mmc0-8bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DATA0__SSP1_DATA0 + MX23_PAD_SSP1_DATA1__SSP1_DATA1 + MX23_PAD_SSP1_DATA2__SSP1_DATA2 + MX23_PAD_SSP1_DATA3__SSP1_DATA3 + MX23_PAD_GPMI_D08__SSP1_DATA4 + MX23_PAD_GPMI_D09__SSP1_DATA5 + MX23_PAD_GPMI_D10__SSP1_DATA6 + MX23_PAD_GPMI_D11__SSP1_DATA7 + MX23_PAD_SSP1_CMD__SSP1_CMD + MX23_PAD_SSP1_DETECT__SSP1_DETECT + MX23_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc0_pins_fixup: mmc0-pins-fixup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DETECT__SSP1_DETECT + MX23_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,pull-up = ; + }; + + mmc0_sck_cfg: mmc0-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,pull-up = ; + }; + + mmc1_4bit_pins_a: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D00__SSP2_DATA0 + MX23_PAD_GPMI_D01__SSP2_DATA1 + MX23_PAD_GPMI_D02__SSP2_DATA2 + MX23_PAD_GPMI_D03__SSP2_DATA3 + MX23_PAD_GPMI_RDY1__SSP2_CMD + MX23_PAD_GPMI_WRN__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc1_8bit_pins_a: mmc1-8bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D00__SSP2_DATA0 + MX23_PAD_GPMI_D01__SSP2_DATA1 + MX23_PAD_GPMI_D02__SSP2_DATA2 + MX23_PAD_GPMI_D03__SSP2_DATA3 + MX23_PAD_GPMI_D04__SSP2_DATA4 + MX23_PAD_GPMI_D05__SSP2_DATA5 + MX23_PAD_GPMI_D06__SSP2_DATA6 + MX23_PAD_GPMI_D07__SSP2_DATA7 + MX23_PAD_GPMI_RDY1__SSP2_CMD + MX23_PAD_GPMI_WRN__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_PWM2__PWM2 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_LCD_D00__LCD_D00 + MX23_PAD_LCD_D01__LCD_D01 + MX23_PAD_LCD_D02__LCD_D02 + MX23_PAD_LCD_D03__LCD_D03 + MX23_PAD_LCD_D04__LCD_D04 + MX23_PAD_LCD_D05__LCD_D05 + MX23_PAD_LCD_D06__LCD_D06 + MX23_PAD_LCD_D07__LCD_D07 + MX23_PAD_LCD_D08__LCD_D08 + MX23_PAD_LCD_D09__LCD_D09 + MX23_PAD_LCD_D10__LCD_D10 + MX23_PAD_LCD_D11__LCD_D11 + MX23_PAD_LCD_D12__LCD_D12 + MX23_PAD_LCD_D13__LCD_D13 + MX23_PAD_LCD_D14__LCD_D14 + MX23_PAD_LCD_D15__LCD_D15 + MX23_PAD_LCD_D16__LCD_D16 + MX23_PAD_LCD_D17__LCD_D17 + MX23_PAD_GPMI_D08__LCD_D18 + MX23_PAD_GPMI_D09__LCD_D19 + MX23_PAD_GPMI_D10__LCD_D20 + MX23_PAD_GPMI_D11__LCD_D21 + MX23_PAD_GPMI_D12__LCD_D22 + MX23_PAD_GPMI_D13__LCD_D23 + MX23_PAD_LCD_DOTCK__LCD_DOTCK + MX23_PAD_LCD_ENABLE__LCD_ENABLE + MX23_PAD_LCD_HSYNC__LCD_HSYNC + MX23_PAD_LCD_VSYNC__LCD_VSYNC + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_WRN__SSP2_SCK + MX23_PAD_GPMI_RDY1__SSP2_CMD + MX23_PAD_GPMI_D00__SSP2_DATA0 + MX23_PAD_GPMI_D03__SSP2_DATA3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c_pins_a: i2c@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_I2C_SCL__I2C_SCL + MX23_PAD_I2C_SDA__I2C_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c_pins_b: i2c@1 { + reg = <1>; + fsl,pinmux-ids = < + MX23_PAD_LCD_ENABLE__I2C_SCL + MX23_PAD_LCD_HSYNC__I2C_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c_pins_c: i2c@2 { + reg = <2>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DATA1__I2C_SCL + MX23_PAD_SSP1_DATA2__I2C_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + + digctl@8001c000 { + compatible = "fsl,imx23-digctl"; + reg = <0x8001c000 2000>; + status = "disabled"; + }; + + emi@80020000 { + reg = <0x80020000 0x2000>; + status = "disabled"; + }; + + dma_apbx: dma-apbx@80024000 { + compatible = "fsl,imx23-dma-apbx"; + reg = <0x80024000 0x2000>; + interrupts = <7 5 9 26 + 19 0 25 23 + 60 58 9 0 + 0 0 0 0>; + interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", + "saif0", "empty", "auart0-rx", "auart0-tx", + "auart1-rx", "auart1-tx", "saif1", "empty", + "empty", "empty", "empty", "empty"; + #dma-cells = <1>; + dma-channels = <16>; + clocks = <&clks 16>; + }; + + dcp: crypto@80028000 { + compatible = "fsl,imx23-dcp"; + reg = <0x80028000 0x2000>; + interrupts = <53 54>; + status = "okay"; + }; + + pxp@8002a000 { + reg = <0x8002a000 0x2000>; + status = "disabled"; + }; + + efuse@8002c000 { + compatible = "fsl,imx23-ocotp", "fsl,ocotp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8002c000 0x2000>; + clocks = <&clks 15>; + }; + + axi-ahb@8002e000 { + reg = <0x8002e000 0x2000>; + status = "disabled"; + }; + + lcdif@80030000 { + compatible = "fsl,imx23-lcdif"; + reg = <0x80030000 2000>; + interrupts = <46 45>; + clocks = <&clks 38>; + status = "disabled"; + }; + + ssp1: spi@80034000 { + reg = <0x80034000 0x2000>; + interrupts = <2>; + clocks = <&clks 33>; + dmas = <&dma_apbh 2>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + tvenc@80038000 { + reg = <0x80038000 0x2000>; + status = "disabled"; + }; + }; + + apbx@80040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80040000 0x40000>; + ranges; + + clks: clkctrl@80040000 { + compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; + + saif0: saif@80042000 { + reg = <0x80042000 0x2000>; + dmas = <&dma_apbx 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + power@80044000 { + reg = <0x80044000 0x2000>; + status = "disabled"; + }; + + saif1: saif@80046000 { + reg = <0x80046000 0x2000>; + dmas = <&dma_apbx 10>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + audio-out@80048000 { + reg = <0x80048000 0x2000>; + dmas = <&dma_apbx 1>; + dma-names = "tx"; + status = "disabled"; + }; + + audio-in@8004c000 { + reg = <0x8004c000 0x2000>; + dmas = <&dma_apbx 0>; + dma-names = "rx"; + status = "disabled"; + }; + + lradc: lradc@80050000 { + compatible = "fsl,imx23-lradc"; + reg = <0x80050000 0x2000>; + interrupts = <36 37 38 39 40 41 42 43 44>; + status = "disabled"; + clocks = <&clks 26>; + #io-channel-cells = <1>; + }; + + spdif@80054000 { + reg = <0x80054000 2000>; + dmas = <&dma_apbx 2>; + dma-names = "tx"; + status = "disabled"; + }; + + i2c: i2c@80058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-i2c"; + reg = <0x80058000 0x2000>; + interrupts = <27>; + clock-frequency = <100000>; + dmas = <&dma_apbx 3>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + rtc@8005c000 { + compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; + reg = <0x8005c000 0x2000>; + interrupts = <22>; + }; + + pwm: pwm@80064000 { + compatible = "fsl,imx23-pwm"; + reg = <0x80064000 0x2000>; + clocks = <&clks 30>; + #pwm-cells = <2>; + fsl,pwm-number = <5>; + status = "disabled"; + }; + + timrot@80068000 { + compatible = "fsl,imx23-timrot", "fsl,timrot"; + reg = <0x80068000 0x2000>; + interrupts = <28 29 30 31>; + clocks = <&clks 28>; + }; + + auart0: serial@8006c000 { + compatible = "fsl,imx23-auart"; + reg = <0x8006c000 0x2000>; + interrupts = <24>; + clocks = <&clks 32>; + dmas = <&dma_apbx 6>, <&dma_apbx 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + auart1: serial@8006e000 { + compatible = "fsl,imx23-auart"; + reg = <0x8006e000 0x2000>; + interrupts = <59>; + clocks = <&clks 32>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + duart: serial@80070000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80070000 0x2000>; + interrupts = <0>; + clocks = <&clks 32>, <&clks 16>; + clock-names = "uart", "apb_pclk"; + status = "disabled"; + }; + + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx23-usbphy"; + reg = <0x8007c000 0x2000>; + clocks = <&clks 41>; + status = "disabled"; + }; + }; + }; + + ahb@80080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80080000 0x80000>; + ranges; + + usb0: usb@80080000 { + compatible = "fsl,imx23-usb", "fsl,imx27-usb"; + reg = <0x80080000 0x40000>; + interrupts = <11>; + fsl,usbphy = <&usbphy0>; + clocks = <&clks 40>; + status = "disabled"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&lradc 8>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts new file mode 100644 index 000000000000..98672932e41b --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Armadeus Systems - + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "Armadeus Systems APF28 module"; + compatible = "armadeus,imx28-apf28", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x300000>; + }; + + partition@300000 { + label = "env"; + reg = <0x300000 0x80000>; + }; + + partition@380000 { + label = "env2"; + reg = <0x380000 0x80000>; + }; + + partition@400000 { + label = "dtb"; + reg = <0x400000 0x80000>; + }; + + partition@480000 { + label = "splash"; + reg = <0x480000 0x80000>; + }; + + partition@500000 { + label = "kernel"; + reg = <0x500000 0x800000>; + }; + + partition@d00000 { + label = "rootfs"; + reg = <0xd00000 0xf300000>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts new file mode 100644 index 000000000000..4704b6141836 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Armadeus Systems - + */ + +/* APF28Dev is a docking board for the APF28 SOM */ +#include "imx28-apf28.dts" + +/ { + model = "Armadeus Systems APF28Dev docking/development board"; + compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 23 1>; + enable-active-high; + }; + + reg_can0_vcc: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "can0_vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio0 21 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + + pwms = <&pwm 3 191000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-button { + label = "User button"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + linux,code = <0x100>; + wakeup-source; + }; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can0_vcc>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_16bit_pins_a + &lcdif_pins_apf28dev>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <16>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_apf28dev>; + + hog_pins_apf28dev: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D16__GPIO_1_16 + MX28_PAD_LCD_D17__GPIO_1_17 + MX28_PAD_LCD_D18__GPIO_1_18 + MX28_PAD_LCD_D19__GPIO_1_19 + MX28_PAD_LCD_D20__GPIO_1_20 + MX28_PAD_LCD_D21__GPIO_1_21 + MX28_PAD_LCD_D22__GPIO_1_22 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_apf28dev: lcdif-apf28dev@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_otg_apf28dev: otg-apf28dev@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_otg_apf28dev + &usb0_id_pins_b>; + vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts new file mode 100644 index 000000000000..f9bf40d96568 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "Bluegiga APX4 Development Kit"; + compatible = "bluegiga,apx4devkit", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "bluegiga,apx4devkit-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "apx4devkit-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio3 28 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_apx4>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <32>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_LCD_RESET__GPIO_3_30 + MX28_PAD_JTAG_RTCK__GPIO_4_20 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_apx4: lcdif-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_SSP0_DATA7__SSP2_SCK + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; + bus-width = <4>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usbphy1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts new file mode 100644 index 000000000000..d004b1cbb4ae --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Free Electrons + */ + +/dts-v1/; +#include "imx28.dtsi" +#include + +/ { + model = "Crystalfontz CFA-10036 Board"; + compatible = "crystalfontz,cfa10036", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_cfa10036>; + + power { + gpios = <&gpio3 4 1>; + default-state = "on"; + }; + }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pwr_cfa10036>; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_b>; + clock-frequency = <400000>; + status = "okay"; + + ssd1306: oled@3c { + compatible = "solomon,ssd1306fb-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&ssd1306_cfa10036>; + reg = <0x3c>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + solomon,height = <32>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,com-lrremap; + solomon,com-invdir; + solomon,com-offset = <32>; + }; +}; + +&pinctrl { + ssd1306_cfa10036: ssd1306-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__GPIO_2_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_cfa10036: leds-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__GPIO_3_4 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_otg_cfa10036: otg-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY0__USB0_ID + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31c3 /* + MX28_PAD_PWM3__GPIO_3_28 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + vmmc-supply = <®_vddio_sd0>; + bus-width = <4>; + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_otg_cfa10036>; + dr_mode = "peripheral"; + phy_type = "utmi"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts new file mode 100644 index 000000000000..d3e9a731525b --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Free Electrons + */ + +/* + * The CFA-10049 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +#include "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10037 Board"; + compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + usb_pins_cfa10037: usb-10037@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins_cfa10037: mac0-10037@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS2__GPIO_2_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + }; + + apbx@80040000 { + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a + &mac0_pins_cfa10037>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10037>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts new file mode 100644 index 000000000000..c5a7f56d83db --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Free Electrons + */ + +/* + * The CFA-10049 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +#include "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10049 Board"; + compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2cmux_pins_cfa10049>; + mux-gpios = <&gpio1 22 0 &gpio1 23 0>; + i2c-parent = <&i2c1>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adc0: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + adc1: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + adc2: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555: pca9555@20 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pca_pins_cfa10049>; + interrupt-parent = <&gpio2>; + interrupts = <19 0x2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10049>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; + + spi-2 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_cfa10049>; + status = "okay"; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; + cs-gpios = <&gpio3 5 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hx8357: hx8357@0 { + compatible = "himax,hx8357b", "himax,hx8357"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + gpios-reset = <&gpio3 30 0>; + im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>; + }; + }; + + spi-3 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_cfa10049>; + status = "okay"; + sck-gpios = <&gpio0 24 0>; + mosi-gpios = <&gpio0 28 0>; + cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; + num-chipselects = <3>; + #address-cells = <1>; + #size-cells = <0>; + + gpio5: gpio5@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <2>; + spi-max-frequency = <100000>; + }; + + gpio6: gpio6@1 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <1>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; + + dac0: dh2228@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + spi-max-frequency = <100000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_btn_pins_cfa10049>; + + rotary-button { + label = "rotary_button"; + gpios = <&gpio3 26 1>; + debounce-interval = <10>; + linux,code = <28>; + }; + }; + + rotary { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_pins_cfa10049>; + gpios = <&gpio3 24 1>, <&gpio3 25 1>; + linux,axis = <1>; /* REL_Y */ + rotary-encoder,relative-axis; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + }; + + onewire { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_gpio_pins>; + status = "okay"; + gpios = <&gpio1 21 0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10049 + &lcdif_pins_cfa10049 + &lcdif_pins_cfa10049_pullup>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9216000>; + hactive = <320>; + vactive = <480>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <15>; + vsync-len = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a + &mac0_pins_cfa10049>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&pinctrl { + usb_pins_cfa10049: usb-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2cmux_pins_cfa10049: i2cmux-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D22__GPIO_1_22 + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins_cfa10049: mac0-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS2__GPIO_2_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pca_pins_cfa10049: pca-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS0__GPIO_2_19 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + rotary_pins_cfa10049: rotary-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + rotary_btn_pins_cfa10049: rotary-btn-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF1_SDATA0__GPIO_3_26 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi2_pins_cfa10049: spi2-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi3_pins_cfa10049: spi3-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_RESETN__GPIO_0_28 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_ALE__GPIO_0_26 + MX28_PAD_GPMI_CLE__GPIO_0_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10049: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + w1_gpio_pins: w1-gpio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D21__GPIO_1_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; /* 0 will enable the keeper */ + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts new file mode 100644 index 000000000000..70e225a99fbe --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Crystalfontz America, Inc. + * Free Electrons + */ + +/* + * The CFA-10055 is an expansion board for the CFA-10036 module and + * CFA-10037, thus we need to include the CFA-10037 DTS. + */ +#include "imx28-cfa10037.dts" + +/ { + model = "Crystalfontz CFA-10055 Board"; + compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; + + spi-2 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_cfa10055>; + status = "okay"; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; + cs-gpios = <&gpio3 5 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hx8357: hx8357@0 { + compatible = "himax,hx8357b", "himax,hx8357"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + gpios-reset = <&gpio3 30 0>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10055 + &lcdif_pins_cfa10055 + &lcdif_pins_cfa10055_pullup>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9216000>; + hactive = <320>; + vactive = <480>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <15>; + vsync-len = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&pinctrl { + spi2_pins_cfa10055: spi2-cfa10055@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10055: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts new file mode 100644 index 000000000000..bc2d6fcad12f --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Free Electrons + */ + +/* + * The CFA-10055 is an expansion board for the CFA-10036 module and + * CFA-10037, thus we need to include the CFA-10037 DTS. + */ +#include "imx28-cfa10037.dts" + +/ { + model = "Crystalfontz CFA-10056 Board"; + compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; + + spi-2 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_cfa10056>; + status = "okay"; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; + cs-gpios = <&gpio3 5 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hx8369: hx8369@0 { + compatible = "himax,hx8369a", "himax,hx8369"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + gpios-reset = <&gpio3 30 0>; + }; + }; +}; + +&pinctrl { + spi2_pins_cfa10056: spi2-cfa10056@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10056: lcdif-10056@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_cfa10056 + &lcdif_pins_cfa10056_pullup >; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <32000000>; + hactive = <480>; + vactive = <800>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <5>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts new file mode 100644 index 000000000000..27602c01f162 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Crystalfontz America, Inc. + * Copyright 2012 Free Electrons + */ + +/* + * The CFA-10057 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +#include "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10057 Board"; + compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10057>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 4 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10057 + &lcdif_pins_cfa10057>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <12>; + hback-porch = <2>; + vfront-porch = <5>; + vback-porch = <3>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&pinctrl { + usb_pins_cfa10057: usb-10057@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10057: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts new file mode 100644 index 000000000000..931c4d089b26 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Crystalfontz America, Inc. + * Copyright 2013 Free Electrons + */ + +/* + * The CFA-10058 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +#include "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10058 Board"; + compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb1_vbus: regulator@0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10058>; + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_cfa10058>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <13>; + vfront-porch = <29>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&pinctrl { + usb_pins_cfa10058: usb-10058@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10058: lcdif-10058@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts new file mode 100644 index 000000000000..b73020ff1053 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015-2017 I2SE GmbH + * Copyright (C) 2016 Michael Heimpold + */ + +/dts-v1/; +#include "imx28-duckbill-2.dts" + +/ { + model = "I2SE Duckbill 2 485"; + compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; + + leds { + rs485-red { + label = "duckbill:red:rs485"; + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + }; + + rs485-green { + label = "duckbill:green:rs485"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c0 { + status = "disabled"; +}; + +&led_pins { + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 + MX28_PAD_SAIF0_LRCLK__GPIO_3_21 + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts new file mode 100644 index 000000000000..473d99b9b42f --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015-2017 I2SE GmbH + * Copyright (C) 2016 Michael Heimpold + */ + +/dts-v1/; +#include +#include "imx28-duckbill-2.dts" + +/ { + model = "I2SE Duckbill 2 EnOcean"; + compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; + + leds { + enocean-blue { + label = "duckbill:blue:enocean"; + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + }; + + enocean-red { + label = "duckbill:red:enocean"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + }; + + enocean-green { + label = "duckbill:green:enocean"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&enocean_button>; + + key-enocean { + label = "EnOcean"; + linux,code = ; + gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&i2c0 { + status = "disabled"; +}; + +&led_pins { + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 + MX28_PAD_SAIF0_LRCLK__GPIO_3_21 + MX28_PAD_AUART0_CTS__GPIO_3_2 + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; +}; + +&pinctrl { + enocean_button: enocean-button@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RTS__GPIO_3_3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts new file mode 100644 index 000000000000..859d97a5a775 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015-2017 I2SE GmbH + * Copyright (C) 2016 Michael Heimpold + */ + +/dts-v1/; +#include "imx28-duckbill-2.dts" + +/ { + model = "I2SE Duckbill 2 SPI"; + compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; + + aliases { + ethernet1 = &qca7000; + }; +}; + +&auart0 { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&pinctrl { + qca7000_pins: qca7000@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ + MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */ + MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */ + MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */ + MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */ + MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + /delete-property/ bus-width; + /delete-property/ vmmc-supply; + status = "okay"; + + qca7000: ethernet@0 { + reg = <0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&qca7000_pins>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <8000000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts new file mode 100644 index 000000000000..4e28212e9626 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015-2017 I2SE GmbH + * Copyright (C) 2016 Michael Heimpold + */ + +/dts-v1/; +#include +#include +#include "imx28.dtsi" + +/ { + model = "I2SE Duckbill 2"; + compatible = "i2se,duckbill-2", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + status-red { + label = "duckbill:red:status"; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + status-green { + label = "duckbill:green:status"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&lradc { + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; + phy-supply = <®_3p3v>; + phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_phy_int_pin>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + max-speed = <100>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_phy_reset_pin: mac0-phy-reset@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_phy_int_pin: mac0-phy-int@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins: leds@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 + MX28_PAD_SAIF0_LRCLK__GPIO_3_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + status = "okay"; + non-removable; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_b + &mmc2_cd_cfg &mmc2_sck_cfg_b>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts new file mode 100644 index 000000000000..13ffd533fdea --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2013-2014,2016 Michael Heimpold + * Copyright (C) 2015-2017 I2SE GmbH + */ + +/dts-v1/; +#include +#include "imx28.dtsi" + +/ { + model = "I2SE Duckbill"; + compatible = "i2se,duckbill", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + status-red { + label = "duckbill:red:status"; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + status-green { + label = "duckbill:green:status"; + gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&lradc { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; + phy-supply = <®_3p3v>; + phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_phy_reset_pin: mac0-phy-reset@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins: leds@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__GPIO_3_4 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts new file mode 100644 index 000000000000..29f8a3a245d4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2013 Eukréa Electromatique + */ + +/* + * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC + */ + +/dts-v1/; +#include "imx28-eukrea-mbmx28lc.dtsi" + +/ { + model = "Eukrea Electromatique MBMX283LC"; + compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl{ + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_cpuimx283>; + + hog_pins_cpuimx283: hog-cpuimx283@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts new file mode 100644 index 000000000000..cd875ace168d --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2013 Eukréa Electromatique + */ + +/* + * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC + */ + +#include "imx28-eukrea-mbmx283lc.dts" + +/ { + model = "Eukrea Electromatique MBMX287LC"; + compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; + hog_pins_cpuimx287: hog-cpuimx287@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SPDIF__GPIO_3_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi new file mode 100644 index 000000000000..b285a946e2c2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2013 Eukréa Electromatique + */ + +#include +#include +#include "imx28.dtsi" + +/ { + model = "Eukrea Electromatique MBMX28LC"; + compatible = "eukrea,mbmx28lc", "fsl,imx28"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 4 1000000>; + brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; + default-brightness-level = <10>; + }; + + gpio-keys-0 { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; + + switch-sw3 { + label = "SW3"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + gpio-keys-1 { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; + + switch-sw4 { + label = "SW4"; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + led-d6 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_d6_pins_mbmx28lc>; + + led1 { + label = "d6"; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-d7 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_d7_pins_mbmx28lc>; + + led1 { + label = "d7"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_lcd_3v3: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb0_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx28-mbmx28lc-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "imx28-mbmx28lc-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "okay"; + + display0: display0 { + model = "43WVF1G-0"; + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9072000>; + hactive = <480>; + vactive = <272>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <40>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&pinctrl { + gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D21__GPIO_1_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D20__GPIO_1_20 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_VSYNC__LCD_VSYNC + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D22__GPIO_1_22 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D18__GPIO_1_18 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D19__GPIO_1_19 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + cd-inverted; + status = "okay"; +}; + +&usb0 { + disable-over-current; + vbus-supply = <®_usb0_vbus>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_b>; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts new file mode 100644 index 000000000000..783abb82b2a8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "Freescale i.MX28 Evaluation Kit"; + compatible = "fsl,imx28-evk", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; + + reg_fec_3v3: regulator-fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 15 0>; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 9 0>; + enable-active-high; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 8 0>; + enable-active-high; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 0>; + enable-active-high; + }; + + reg_can_3v3: regulator-can-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 13 0>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + sound { + compatible = "fsl,imx28-evk-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "imx28-evk-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio3_5>; + + user { + label = "Heartbeat"; + gpios = <&gpio3 5 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight_display: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg + &gpmi_pins_evk>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_evk>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + fsl,ave-ctrl = <4>; + fsl,ave-delay = <2>; + fsl,settling = <10>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; + + at24@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP1_DATA3__GPIO_2_15 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_LCD_RESET__GPIO_3_30 + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_AUART2_TX__GPIO_3_9 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pin_gpio3_5: led_gpio3_5@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpmi_pins_evk: gpmi-nand-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE1N__GPMI_CE1N + MX28_PAD_GPMI_RDY1__GPMI_READY1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_evk: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio2 12 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + bus-width = <8>; + wp-gpios = <&gpio0 28 0>; +}; + +&ssp2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_a>; + vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi new file mode 100644 index 000000000000..bb971e660db8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + aliases { + spi2 = &ssp3; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1"; + }; + + memory@40000000 { + reg = <0x40000000 0x08000000>; + }; + + reg_3v3: regulator-reg-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_5v: regulator-reg-usb-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_fec_3v3: regulator-reg-fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&spi3_pins_a { + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + MX28_PAD_AUART2_TX__GPIO_3_9 + >; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_3v3>; + non-removable; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&ssp3 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_a>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x80000>; + read-only; + }; + + partition@80000 { + label = "env0"; + reg = <0x80000 0x10000>; + }; + + partition@90000 { + label = "env1"; + reg = <0x90000 0x10000>; + }; + + partition@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "swupdate"; + reg = <0x500000 0x800000>; + }; + }; + }; +}; + +&usb0 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_b>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi new file mode 100644 index 000000000000..c08b14ad7cd5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Marek Vasut + */ + +#include "imx28.dtsi" + +/ { + model = "Aries/DENX M28"; + compatible = "aries,m28", "denx,m28", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&gpmi { + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts new file mode 100644 index 000000000000..6b01de9efd02 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2013 Marek Vasut + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "MSR M28CU3"; + compatible = "msr,m28cu3", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_gpio>; + + user1 { + label = "sd0-led"; + gpios = <&gpio2 26 0>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "sd1-led"; + gpios = <&gpio2 24 0>; + linux,default-trigger = "mmc2"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vddio_sd0: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 0>; + }; + + reg_vddio_sd1: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vddio-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 0>; + }; + + reg_usb1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 8 0>; + enable-active-high; + }; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_2pins_b>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; +}; + +&gpmi { + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "gpmi-nfc-0-boot"; + reg = <0x00000000 0x01400000>; + read-only; + }; + + partition@1 { + label = "gpmi-nfc-general-use"; + reg = <0x01400000 0x0ec00000>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <6410256>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hfront-porch = <20>; + vback-porch = <15>; + vfront-porch = <5>; + hsync-len = <30>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&ocotp { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS0__GPIO_2_19 + MX28_PAD_PWM4__GPIO_3_29 + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_VSYNC__LCD_VSYNC + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_RESET__LCD_RESET + MX28_PAD_LCD_CS__LCD_ENABLE + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_gpio: leds-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_MISO__GPIO_2_26 + MX28_PAD_SSP3_SCK__GPIO_2_24 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_a + &mmc2_cd_cfg + &mmc2_sck_cfg_a>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd1>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts new file mode 100644 index 000000000000..e350d57a4cec --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + + * Copyright (C) 2012 Marek Vasut + */ + +/dts-v1/; +#include "imx28-m28.dtsi" + +/ { + model = "Aries/DENX M28EVK"; + compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 4 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + regulators { + reg_vddio_sd0: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; + + reg_usb0_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 12 0>; + }; + + reg_usb1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 13 0>; + }; + }; + + sound { + compatible = "denx,m28evk-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "m28evk-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_b>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; + + eeprom: eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <0>; + hfront-porch = <256>; + vback-porch = <0>; + vfront-porch = <45>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + status = "okay"; + fsl,lradc-touchscreen-wires = <4>; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_AUART2_CTS__GPIO_3_10 + MX28_PAD_AUART2_RTS__GPIO_3_11 + MX28_PAD_AUART3_RX__GPIO_3_12 + MX28_PAD_AUART3_TX__GPIO_3_13 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio3 10 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; + +&ssp2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_a>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h new file mode 100644 index 000000000000..d427e6c2fa78 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h @@ -0,0 +1,500 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header providing constants for i.MX28 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann + */ + +#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ +#define __DT_BINDINGS_MX28_PINCTRL_H__ + +#include "mxs-pinfunc.h" + +#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 +#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 +#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 +#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 +#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 +#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 +#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 +#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 +#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 +#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 +#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 +#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 +#define MX28_PAD_LCD_D00__LCD_D0 0x1000 +#define MX28_PAD_LCD_D01__LCD_D1 0x1010 +#define MX28_PAD_LCD_D02__LCD_D2 0x1020 +#define MX28_PAD_LCD_D03__LCD_D3 0x1030 +#define MX28_PAD_LCD_D04__LCD_D4 0x1040 +#define MX28_PAD_LCD_D05__LCD_D5 0x1050 +#define MX28_PAD_LCD_D06__LCD_D6 0x1060 +#define MX28_PAD_LCD_D07__LCD_D7 0x1070 +#define MX28_PAD_LCD_D08__LCD_D8 0x1080 +#define MX28_PAD_LCD_D09__LCD_D9 0x1090 +#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 +#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 +#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 +#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 +#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 +#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 +#define MX28_PAD_LCD_D16__LCD_D16 0x1100 +#define MX28_PAD_LCD_D17__LCD_D17 0x1110 +#define MX28_PAD_LCD_D18__LCD_D18 0x1120 +#define MX28_PAD_LCD_D19__LCD_D19 0x1130 +#define MX28_PAD_LCD_D20__LCD_D20 0x1140 +#define MX28_PAD_LCD_D21__LCD_D21 0x1150 +#define MX28_PAD_LCD_D22__LCD_D22 0x1160 +#define MX28_PAD_LCD_D23__LCD_D23 0x1170 +#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 +#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 +#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 +#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 +#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 +#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 +#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 +#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 +#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 +#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 +#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 +#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 +#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 +#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 +#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 +#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 +#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 +#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 +#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 +#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 +#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 +#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 +#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 +#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 +#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 +#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 +#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 +#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 +#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 +#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 +#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 +#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 +#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 +#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 +#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 +#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 +#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 +#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 +#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 +#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 +#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 +#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 +#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 +#define MX28_PAD_PWM0__PWM_0 0x3100 +#define MX28_PAD_PWM1__PWM_1 0x3110 +#define MX28_PAD_PWM2__PWM_2 0x3120 +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 +#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 +#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 +#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 +#define MX28_PAD_PWM3__PWM_3 0x31c0 +#define MX28_PAD_PWM4__PWM_4 0x31d0 +#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 +#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 +#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 +#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 +#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 +#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 +#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 +#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 +#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 +#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 +#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 +#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 +#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 +#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 +#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 +#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 +#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 +#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 +#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 +#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 +#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 +#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 +#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 +#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 +#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 +#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 +#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 +#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 +#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 +#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 +#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 +#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 +#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 +#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 +#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 +#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 +#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 +#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 +#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 +#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 +#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 +#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 +#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 +#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 +#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 +#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 +#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 +#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 +#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 +#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 +#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 +#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 +#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 +#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 +#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 +#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 +#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 +#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 +#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 +#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 +#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 +#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 +#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 +#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 +#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 +#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 +#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 +#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 +#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 +#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 +#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 +#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 +#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 +#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 +#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 +#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 +#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 +#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 +#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 +#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 +#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 +#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 +#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 +#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 +#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 +#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 +#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 +#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 +#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 +#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 +#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 +#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 +#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 +#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 +#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 +#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 +#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 +#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 +#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 +#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 +#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 +#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 +#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 +#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 +#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 +#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 +#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 +#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 +#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 +#define MX28_PAD_PWM0__I2C1_SCL 0x3101 +#define MX28_PAD_PWM1__I2C1_SDA 0x3111 +#define MX28_PAD_PWM2__USB0_ID 0x3121 +#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 +#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 +#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 +#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 +#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 +#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 +#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 +#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 +#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 +#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 +#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 +#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 +#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 +#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 +#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 +#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 +#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 +#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 +#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 +#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 +#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 +#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 +#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 +#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 +#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 +#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 +#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 +#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 +#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 +#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 +#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 +#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 +#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 +#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 +#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 +#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 +#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 +#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 +#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 +#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 +#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 +#define MX28_PAD_AUART1_RX__PWM_0 0x3042 +#define MX28_PAD_AUART1_TX__PWM_1 0x3052 +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 +#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 +#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 +#define MX28_PAD_PWM0__DUART_RX 0x3102 +#define MX28_PAD_PWM1__DUART_TX 0x3112 +#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 +#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 +#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 +#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 +#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 +#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 +#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 +#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 +#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 +#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 +#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 +#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 +#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 +#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 +#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 +#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 +#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 +#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 +#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 +#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 +#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 +#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 +#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 +#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 +#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 +#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 +#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 +#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 +#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 +#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 +#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 +#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 +#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 +#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 +#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 +#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 +#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 +#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 +#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 +#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 +#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 +#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 +#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 +#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 +#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 +#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 +#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 +#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 +#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 +#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 +#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 +#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 +#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 +#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 +#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 +#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 +#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 +#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 +#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 +#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 +#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 +#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 +#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 +#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 +#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 +#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 +#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 +#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 +#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 +#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 +#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 +#define MX28_PAD_PWM0__GPIO_3_16 0x3103 +#define MX28_PAD_PWM1__GPIO_3_17 0x3113 +#define MX28_PAD_PWM2__GPIO_3_18 0x3123 +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 +#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 +#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 +#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 +#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 +#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 +#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 +#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 +#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 +#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 +#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 + +#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts new file mode 100644 index 000000000000..5d74a68c56ff --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2012 Marek Vasut + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "SchulerControl GmbH, SC SPS 1"; + compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 9 0>; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + compatible = "gpio-leds"; + status = "okay"; + + led@1 { + label = "sps1-1:yellow:user"; + gpios = <&gpio0 6 0>; + linux,default-trigger = "heartbeat"; + reg = <0>; + }; + + led@2 { + label = "sps1-2:red:user"; + gpios = <&gpio0 3 0>; + linux,default-trigger = "heartbeat"; + reg = <1>; + }; + + led@3 { + label = "sps1-3:red:user"; + gpios = <&gpio0 0 0>; + default-trigger = "heartbeat"; + reg = <2>; + }; + + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom: eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D06__GPIO_0_6 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a>; + bus-width = <4>; + status = "okay"; +}; + +&ssp2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256", "mr25h256"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_b>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts new file mode 100644 index 000000000000..ae6ed5c41be3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Savoir-Faire Linux + * Author: Sebastien Bourdelin + */ + +/dts-v1/; +#include "imx28.dtsi" +#include "dt-bindings/gpio/gpio.h" + +/ { + + model = "Technologic Systems i.MX28 TS-4600"; + compatible = "technologic,imx28-ts4600", "fsl,imx28"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; /* 256MB */ + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; + }; + +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&pinctrl { + en_sd_pwr: en-sd-pwr@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_sck_cfg + &en_sd_pwr>; + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts new file mode 100644 index 000000000000..23ad7cd0a1de --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts @@ -0,0 +1,677 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2012 Shawn Guo + * Copyright 2013-2017 Lothar Waßmann + */ + +/dts-v1/; +#include "imx28.dtsi" +#include +#include + +/ { + model = "Ka-Ro electronics TX28 module"; + compatible = "karo,tx28", "fsl,imx28"; + + aliases { + can0 = &can0; + can1 = &can1; + display = &display0; + ds1339 = &ds1339; + gpio5 = &gpio5; + lcdif = &lcdif; + lcdif_23bit_pins = &tx28_lcdif_23bit_pins; + lcdif_24bit_pins = &lcdif_24bit_pins_a; + reg_can_xcvr = ®_can_xcvr; + spi_gpio = &spi_gpio; + spi_mxs = &ssp3; + stk5led = &user_led; + usbotg = &usb0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0>; /* will be filled in by U-Boot */ + }; + + onewire { + compatible = "w1-gpio"; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_flexcan_xcvr_pins>; + }; + + reg_lcd: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + sound { + compatible = "fsl,imx28-tx28-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "imx28-tx28-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user { + label = "Heartbeat"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 500000>; + /* + * a silly way to create a 1:1 relationship between the + * PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + matrix_keypad: matrix-keypad { + compatible = "gpio-matrix-keypad"; + col-gpios = < + &gpio5 0 GPIO_ACTIVE_HIGH + &gpio5 1 GPIO_ACTIVE_HIGH + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 3 GPIO_ACTIVE_HIGH + >; + row-gpios = < + &gpio5 4 GPIO_ACTIVE_HIGH + &gpio5 5 GPIO_ACTIVE_HIGH + &gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH + >; + /* sample keymap */ + linux,keymap = < + 0x00000074 /* row 0, col 0, KEY_POWER */ + 0x00010052 /* row 0, col 1, KEY_KP0 */ + 0x0002004f /* row 0, col 2, KEY_KP1 */ + 0x00030050 /* row 0, col 3, KEY_KP2 */ + 0x01000051 /* row 1, col 0, KEY_KP3 */ + 0x0101004b /* row 1, col 1, KEY_KP4 */ + 0x0102004c /* row 1, col 2, KEY_KP5 */ + 0x0103004d /* row 1, col 3, KEY_KP6 */ + 0x02000047 /* row 2, col 0, KEY_KP7 */ + 0x02010048 /* row 2, col 1, KEY_KP8 */ + 0x02020049 /* row 2, col 2, KEY_KP9 */ + >; + gpio-activelow; + wakeup-source; + debounce-delay-ms = <100>; + col-scan-delay-us = <5000>; + linux,no-autorepeat; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_spi_gpio_pins>; + + sck-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + num-chipselects = <3>; + cs-gpios = < + &gpio2 27 GPIO_ACTIVE_LOW + &gpio3 8 GPIO_ACTIVE_LOW + &gpio3 9 GPIO_ACTIVE_LOW + >; + /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ + status = "disabled"; + }; +}; + +/* 2nd TX-Std UART - (A)UART1 */ +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; +}; + +/* 3rd TX-Std UART - (A)UART3 */ +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&digctl { + status = "okay"; +}; + +/* 1st TX-Std UART - (D)UART */ +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + clocks = <&mclk>; + }; + + gpio5: pca953x@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_pca9554_pins>; + interrupt-parent = <&gpio3>; + interrupts = <28 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_edt_ft5x06_pins>; + interrupt-parent = <&gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_tsc2007_pins>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = /bits/ 16 <660>; + }; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; + lcd-supply = <®_lcd>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + display-timings { + native-mode = <&timing5>; + timing0: timing0 { + panel-name = "VGA"; + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing1: timing1 { + panel-name = "ETV570"; + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing2: timing2 { + panel-name = "ET0350"; + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing3: timing3 { + panel-name = "ET0430"; + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing4: timing4 { + panel-name = "ET0500", "ET0700"; + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing5: timing5 { + panel-name = "ETQ570"; + clock-frequency = <6400000>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default", "gpio_mode"; + pinctrl-0 = <&mac0_pins_a>; + pinctrl-1 = <&tx28_mac0_pins_gpio>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + /* not enabled by default */ +}; + +&mxs_rtc { + status = "okay"; +}; + +&ocotp { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ + MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ + MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__GPIO_1_0 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 { + reg = <0>; + fsl,pinmux-ids = < + /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + MX28_PAD_LCD_D18__LCD_D18 + MX28_PAD_LCD_D19__LCD_D19 + MX28_PAD_LCD_D20__LCD_D20 + MX28_PAD_LCD_D21__LCD_D21 + MX28_PAD_LCD_D22__LCD_D22 + MX28_PAD_LCD_D23__LCD_D23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ + MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__GPIO_4_0 + MX28_PAD_ENET0_MDIO__GPIO_4_1 + MX28_PAD_ENET0_RX_EN__GPIO_4_2 + MX28_PAD_ENET0_RXD0__GPIO_4_3 + MX28_PAD_ENET0_RXD1__GPIO_4_4 + MX28_PAD_ENET0_TX_EN__GPIO_4_6 + MX28_PAD_ENET0_TXD0__GPIO_4_7 + MX28_PAD_ENET0_TXD1__GPIO_4_8 + MX28_PAD_ENET_CLK__GPIO_4_16 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_pca9554_pins: tx28-pca9554-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_spi_gpio_pins: spi-gpiogrp@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_AUART2_TX__GPIO_3_9 + MX28_PAD_SSP3_SCK__GPIO_2_24 + MX28_PAD_SSP3_MOSI__GPIO_2_25 + MX28_PAD_SSP3_MISO__GPIO_2_26 + MX28_PAD_SSP3_SS0__GPIO_2_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_tsc2007_pins: tx28-tsc2007-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + + tx28_usbphy0_pins: tx28-usbphy0-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ + MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_usbphy1_pins: tx28-usbphy1-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ + MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_b>; + fsl,saif-master; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default", "special"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; +}; + +&ssp3 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_a>; + clock-frequency = <57600000>; + status = "okay"; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&tx28_usbphy0_pins>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbphy1 { + pinctrl-names = "default"; + pinctrl-0 = <&tx28_usbphy1_pins>; + phy_type = "utmi"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts new file mode 100644 index 000000000000..a400c108f66a --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + compatible = "lwn,imx28-xea", "fsl,imx28"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a &hog_pins_tiva>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D02__GPIO_0_2 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_CLE__GPIO_0_27 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_LCD_D00__GPIO_1_0 + MX28_PAD_LCD_D01__GPIO_1_1 + MX28_PAD_LCD_D02__GPIO_1_2 + MX28_PAD_LCD_D03__GPIO_1_3 + MX28_PAD_LCD_D04__GPIO_1_4 + MX28_PAD_LCD_D05__GPIO_1_5 + MX28_PAD_LCD_D06__GPIO_1_6 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + hog_pins_tiva: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_WRN__GPIO_0_25 + >; + fsl,voltage = ; + fsl,pull-up = ; + }; + + hog_pins_coding: hog@2 { + reg = <2>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D01__GPIO_0_1 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +®_fec_3v3 { + gpio = <&gpio0 0 0>; +}; + +®_usb_5v { + gpio = <&gpio0 2 0>; +}; + +&spi2_pins_a { + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__GPIO_2_19 + >; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi new file mode 100644 index 000000000000..29e37b1fae66 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi @@ -0,0 +1,1334 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. + +#include +#include "imx28-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&icoll>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + saif0 = &saif0; + saif1 = &saif1; + serial0 = &auart0; + serial1 = &auart1; + serial2 = &auart2; + serial3 = &auart3; + serial4 = &auart4; + spi0 = &ssp1; + spi1 = &ssp2; + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + apb@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x80000>; + ranges; + + apbh@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x3c900>; + ranges; + + icoll: interrupt-controller@80000000 { + compatible = "fsl,imx28-icoll", "fsl,icoll"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x80000000 0x2000>; + }; + + hsadc: hsadc@80002000 { + reg = <0x80002000 0x2000>; + interrupts = <13>; + dmas = <&dma_apbh 12>; + dma-names = "rx"; + status = "disabled"; + }; + + dma_apbh: dma-controller@80004000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x80004000 0x2000>; + interrupts = <82 83 84 85 + 88 88 88 88 + 88 88 88 88 + 87 86 0 0>; + #dma-cells = <1>; + dma-channels = <16>; + clocks = <&clks 25>; + }; + + perfmon: perfmon@80006000 { + reg = <0x80006000 0x800>; + interrupts = <27>; + status = "disabled"; + }; + + gpmi: nand-controller@8000c000 { + compatible = "fsl,imx28-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <41>; + interrupt-names = "bch"; + clocks = <&clks 50>; + clock-names = "gpmi_io"; + assigned-clocks = <&clks 13>; + assigned-clock-parents = <&clks 10>; + dmas = <&dma_apbh 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp0: spi@80010000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010000 0x2000>; + interrupts = <96>; + clocks = <&clks 46>; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp1: spi@80012000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80012000 0x2000>; + interrupts = <97>; + clocks = <&clks 47>; + dmas = <&dma_apbh 1>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp2: spi@80014000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80014000 0x2000>; + interrupts = <98>; + clocks = <&clks 48>; + dmas = <&dma_apbh 2>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp3: spi@80016000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80016000 0x2000>; + interrupts = <99>; + clocks = <&clks 49>; + dmas = <&dma_apbh 3>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pinctrl: pinctrl@80018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-pinctrl", "simple-bus"; + reg = <0x80018000 0x2000>; + + gpio0: gpio@0 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <0>; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@1 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <1>; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <2>; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@3 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <3>; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@4 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <4>; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + duart_pins_a: duart@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM0__DUART_RX + MX28_PAD_PWM1__DUART_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + duart_pins_b: duart@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_CTS__DUART_RX + MX28_PAD_AUART0_RTS__DUART_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + duart_4pins_a: duart-4pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_CTS__DUART_RX + MX28_PAD_AUART0_RTS__DUART_TX + MX28_PAD_AUART0_RX__DUART_CTS + MX28_PAD_AUART0_TX__DUART_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPMI_D0 + MX28_PAD_GPMI_D01__GPMI_D1 + MX28_PAD_GPMI_D02__GPMI_D2 + MX28_PAD_GPMI_D03__GPMI_D3 + MX28_PAD_GPMI_D04__GPMI_D4 + MX28_PAD_GPMI_D05__GPMI_D5 + MX28_PAD_GPMI_D06__GPMI_D6 + MX28_PAD_GPMI_D07__GPMI_D7 + MX28_PAD_GPMI_CE0N__GPMI_CE0N + MX28_PAD_GPMI_RDY0__GPMI_READY0 + MX28_PAD_GPMI_RDN__GPMI_RDN + MX28_PAD_GPMI_WRN__GPMI_WRN + MX28_PAD_GPMI_ALE__GPMI_ALE + MX28_PAD_GPMI_CLE__GPMI_CLE + MX28_PAD_GPMI_RESETN__GPMI_RESETN + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpmi_status_cfg: gpmi-status-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDN__GPMI_RDN + MX28_PAD_GPMI_WRN__GPMI_WRN + MX28_PAD_GPMI_RESETN__GPMI_RESETN + >; + fsl,drive-strength = ; + }; + + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RX__AUART0_RX + MX28_PAD_AUART0_TX__AUART0_TX + MX28_PAD_AUART0_CTS__AUART0_CTS + MX28_PAD_AUART0_RTS__AUART0_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RX__AUART0_RX + MX28_PAD_AUART0_TX__AUART0_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart1_pins_a: auart1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX + MX28_PAD_AUART1_CTS__AUART1_CTS + MX28_PAD_AUART1_RTS__AUART1_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart2_2pins_a: auart2-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__AUART2_RX + MX28_PAD_SSP2_MOSI__AUART2_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart2_2pins_b: auart2-2pins@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__AUART2_RX + MX28_PAD_AUART2_TX__AUART2_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart2_pins_a: auart2-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__AUART2_RX + MX28_PAD_AUART2_TX__AUART2_TX + MX28_PAD_AUART2_CTS__AUART2_CTS + MX28_PAD_AUART2_RTS__AUART2_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart3_pins_a: auart3@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART3_RX__AUART3_RX + MX28_PAD_AUART3_TX__AUART3_TX + MX28_PAD_AUART3_CTS__AUART3_CTS + MX28_PAD_AUART3_RTS__AUART3_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart3_2pins_a: auart3-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_MISO__AUART3_RX + MX28_PAD_SSP2_SS0__AUART3_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart3_2pins_b: auart3-2pins@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART3_RX__AUART3_RX + MX28_PAD_AUART3_TX__AUART3_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart4_2pins_a: auart4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_SCK__AUART4_TX + MX28_PAD_SSP3_MOSI__AUART4_RX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart4_2pins_b: auart4@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_CTS__AUART4_RX + MX28_PAD_AUART0_RTS__AUART4_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins_a: mac0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins_b: mac0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_RXD2__ENET0_RXD2 + MX28_PAD_ENET0_RXD3__ENET0_RXD3 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET0_TXD2__ENET0_TXD2 + MX28_PAD_ENET0_TXD3__ENET0_TXD3 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + MX28_PAD_ENET0_COL__ENET0_COL + MX28_PAD_ENET0_CRS__ENET0_CRS + MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK + MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac1_pins_a: mac1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_CRS__ENET1_RX_EN + MX28_PAD_ENET0_RXD2__ENET1_RXD0 + MX28_PAD_ENET0_RXD3__ENET1_RXD1 + MX28_PAD_ENET0_COL__ENET1_TX_EN + MX28_PAD_ENET0_TXD2__ENET1_TXD0 + MX28_PAD_ENET0_TXD3__ENET1_TXD1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc0_8bit_pins_a: mmc0-8bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_DATA4__SSP0_D4 + MX28_PAD_SSP0_DATA5__SSP0_D5 + MX28_PAD_SSP0_DATA6__SSP0_D6 + MX28_PAD_SSP0_DATA7__SSP0_D7 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc0_cd_cfg: mmc0-cd-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + >; + fsl,pull-up = ; + }; + + mmc0_sck_cfg: mmc0-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; + + mmc1_4bit_pins_a: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc1_cd_cfg: mmc1-cd-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + >; + fsl,pull-up = ; + }; + + mmc1_sck_cfg: mmc1-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; + + + mmc2_4bit_pins_a: mmc2-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP1_SCK__SSP2_D1 + MX28_PAD_SSP1_CMD__SSP2_D2 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_4bit_pins_b: mmc2-4bit@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__SSP2_D3 + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_cd_cfg: mmc2-cd-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + >; + fsl,pull-up = ; + }; + + mmc2_sck_cfg_a: mmc2-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; + + mmc2_sck_cfg_b: mmc2-sck-cfg@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; + + i2c0_pins_a: i2c0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__I2C0_SCL + MX28_PAD_I2C0_SDA__I2C0_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c0_pins_b: i2c0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RX__I2C0_SCL + MX28_PAD_AUART0_TX__I2C0_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c1_pins_a: i2c1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM0__I2C1_SCL + MX28_PAD_PWM1__I2C1_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c1_pins_b: i2c1@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_CTS__I2C1_SCL + MX28_PAD_AUART2_RTS__I2C1_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + saif0_pins_a: saif0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + saif0_pins_b: saif0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + saif1_pins_a: saif1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pwm0_pins_a: pwm0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM0__PWM_0 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM2__PWM_2 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pwm3_pins_a: pwm3@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__PWM_3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pwm3_pins_b: pwm3@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__PWM_3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pwm4_pins_a: pwm4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM4__PWM_4 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + MX28_PAD_LCD_D18__LCD_D18 + MX28_PAD_LCD_D19__LCD_D19 + MX28_PAD_LCD_D20__LCD_D20 + MX28_PAD_LCD_D21__LCD_D21 + MX28_PAD_LCD_D22__LCD_D22 + MX28_PAD_LCD_D23__LCD_D23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_a: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_16bit_pins_a: lcdif-16bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_sync_pins_a: lcdif-sync@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + can0_pins_a: can0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY2__CAN0_TX + MX28_PAD_GPMI_RDY3__CAN0_RX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + can1_pins_a: can1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE2N__CAN1_TX + MX28_PAD_GPMI_CE3N__CAN1_RX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__SSP2_D3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi3_pins_a: spi3@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi3_pins_b: spi3@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_pins_a: usb0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS2__USB0_OVERCURRENT + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_pins_b: usb0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb1_pins_a: usb1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS1__USB1_OVERCURRENT + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb1_pins_b: usb1@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_PWM2__USB1_OVERCURRENT + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_id_pins_a: usb0id@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RTS__USB0_ID + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_id_pins_b: usb0id1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM2__USB0_ID + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + }; + + digctl: digctl@8001c000 { + compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; + reg = <0x8001c000 0x2000>; + interrupts = <89>; + status = "disabled"; + }; + + etm: etm@80022000 { + reg = <0x80022000 0x2000>; + status = "disabled"; + }; + + dma_apbx: dma-apbx@80024000 { + compatible = "fsl,imx28-dma-apbx"; + reg = <0x80024000 0x2000>; + interrupts = <78 79 66 0 + 80 81 68 69 + 70 71 72 73 + 74 75 76 77>; + #dma-cells = <1>; + dma-channels = <16>; + clocks = <&clks 26>; + }; + + dcp: crypto@80028000 { + compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; + reg = <0x80028000 0x2000>; + interrupts = <52 53 54>; + status = "okay"; + }; + + pxp: pxp@8002a000 { + reg = <0x8002a000 0x2000>; + interrupts = <39>; + status = "disabled"; + }; + + ocotp: efuse@8002c000 { + compatible = "fsl,imx28-ocotp", "fsl,ocotp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8002c000 0x2000>; + clocks = <&clks 25>; + }; + + axi-ahb@8002e000 { + reg = <0x8002e000 0x2000>; + status = "disabled"; + }; + + lcdif: lcdif@80030000 { + compatible = "fsl,imx28-lcdif"; + reg = <0x80030000 0x2000>; + interrupts = <38>; + clocks = <&clks 55>; + dmas = <&dma_apbh 13>; + dma-names = "rx"; + status = "disabled"; + }; + + can0: can@80032000 { + compatible = "fsl,imx28-flexcan"; + reg = <0x80032000 0x2000>; + interrupts = <8>; + clocks = <&clks 58>, <&clks 58>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@80034000 { + compatible = "fsl,imx28-flexcan"; + reg = <0x80034000 0x2000>; + interrupts = <9>; + clocks = <&clks 59>, <&clks 59>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + simdbg: simdbg@8003c000 { + reg = <0x8003c000 0x200>; + status = "disabled"; + }; + + simgpmisel: simgpmisel@8003c200 { + reg = <0x8003c200 0x100>; + status = "disabled"; + }; + + simsspsel: simsspsel@8003c300 { + reg = <0x8003c300 0x100>; + status = "disabled"; + }; + + simmemsel: simmemsel@8003c400 { + reg = <0x8003c400 0x100>; + status = "disabled"; + }; + + gpiomon: gpiomon@8003c500 { + reg = <0x8003c500 0x100>; + status = "disabled"; + }; + + simenet: simenet@8003c700 { + reg = <0x8003c700 0x100>; + status = "disabled"; + }; + + armjtag: armjtag@8003c800 { + reg = <0x8003c800 0x100>; + status = "disabled"; + }; + }; + + apbx@80040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80040000 0x40000>; + ranges; + + clks: clkctrl@80040000 { + compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; + + saif0: saif@80042000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx28-saif"; + reg = <0x80042000 0x2000>; + interrupts = <59>; + #clock-cells = <0>; + clocks = <&clks 53>; + dmas = <&dma_apbx 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + power: power@80044000 { + reg = <0x80044000 0x2000>; + status = "disabled"; + }; + + saif1: saif@80046000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx28-saif"; + reg = <0x80046000 0x2000>; + interrupts = <58>; + clocks = <&clks 54>; + dmas = <&dma_apbx 5>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + lradc: lradc@80050000 { + compatible = "fsl,imx28-lradc"; + reg = <0x80050000 0x2000>; + interrupts = <10 14 15 16 17 18 19 + 20 21 22 23 24 25>; + status = "disabled"; + clocks = <&clks 41>; + #io-channel-cells = <1>; + }; + + spdif: spdif@80054000 { + reg = <0x80054000 0x2000>; + interrupts = <45>; + dmas = <&dma_apbx 2>; + dma-names = "tx"; + status = "disabled"; + }; + + mxs_rtc: rtc@80056000 { + compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; + reg = <0x80056000 0x2000>; + interrupts = <29>; + }; + + i2c0: i2c@80058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-i2c"; + reg = <0x80058000 0x2000>; + interrupts = <111>; + clock-frequency = <100000>; + dmas = <&dma_apbx 6>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + i2c1: i2c@8005a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-i2c"; + reg = <0x8005a000 0x2000>; + interrupts = <110>; + clock-frequency = <100000>; + dmas = <&dma_apbx 7>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pwm: pwm@80064000 { + compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; + reg = <0x80064000 0x2000>; + clocks = <&clks 44>; + #pwm-cells = <2>; + fsl,pwm-number = <8>; + status = "disabled"; + }; + + timer: timrot@80068000 { + compatible = "fsl,imx28-timrot", "fsl,timrot"; + reg = <0x80068000 0x2000>; + interrupts = <48 49 50 51>; + clocks = <&clks 26>; + }; + + auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart1: serial@8006c000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006c000 0x2000>; + interrupts = <113>; + dmas = <&dma_apbx 10>, <&dma_apbx 11>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart2: serial@8006e000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006e000 0x2000>; + interrupts = <114>; + dmas = <&dma_apbx 12>, <&dma_apbx 13>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart3: serial@80070000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x80070000 0x2000>; + interrupts = <115>; + dmas = <&dma_apbx 14>, <&dma_apbx 15>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart4: serial@80072000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x80072000 0x2000>; + interrupts = <116>; + dmas = <&dma_apbx 0>, <&dma_apbx 1>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + duart: serial@80074000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80074000 0x1000>; + interrupts = <47>; + clocks = <&clks 45>, <&clks 26>; + clock-names = "uart", "apb_pclk"; + status = "disabled"; + }; + + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; + reg = <0x8007c000 0x2000>; + clocks = <&clks 62>; + status = "disabled"; + }; + + usbphy1: usbphy@8007e000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; + reg = <0x8007e000 0x2000>; + clocks = <&clks 63>; + status = "disabled"; + }; + }; + }; + + ahb@80080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80080000 0x80000>; + ranges; + + usb0: usb@80080000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; + reg = <0x80080000 0x10000>; + interrupts = <93>; + clocks = <&clks 60>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usb1: usb@80090000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; + reg = <0x80090000 0x10000>; + interrupts = <92>; + clocks = <&clks 61>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + status = "disabled"; + }; + + dflpt: dflpt@800c0000 { + reg = <0x800c0000 0x10000>; + status = "disabled"; + }; + + mac0: ethernet@800f0000 { + compatible = "fsl,imx28-fec"; + reg = <0x800f0000 0x4000>; + interrupts = <101>; + clocks = <&clks 57>, <&clks 57>, <&clks 64>; + clock-names = "ipg", "ahb", "enet_out"; + status = "disabled"; + }; + + mac1: ethernet@800f4000 { + compatible = "fsl,imx28-fec"; + reg = <0x800f4000 0x4000>; + interrupts = <102>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + + eth_switch: switch@800f8000 { + reg = <0x800f8000 0x8000>; + status = "disabled"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&lradc 8>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h new file mode 100644 index 000000000000..31297abcbc71 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header providing constants for i.MX28 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann + */ + +#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ +#define __DT_BINDINGS_MXS_PINCTRL_H__ + +/* fsl,drive-strength property */ +#define MXS_DRIVE_4mA 0 +#define MXS_DRIVE_8mA 1 +#define MXS_DRIVE_12mA 2 +#define MXS_DRIVE_16mA 3 + +/* fsl,voltage property */ +#define MXS_VOLTAGE_LOW 0 +#define MXS_VOLTAGE_HIGH 1 + +/* fsl,pull-up property */ +#define MXS_PULL_DISABLE 0 +#define MXS_PULL_ENABLE 1 + +#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile new file mode 100644 index 000000000000..0a4a7f9dd43e --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_VF610) += \ + vf500-colibri-eval-v3.dtb \ + vf610-bk4.dtb \ + vf610-colibri-eval-v3.dtb \ + vf610m4-colibri.dtb \ + vf610-cosmic.dtb \ + vf610m4-cosmic.dtb \ + vf610-twr.dtb \ + vf610-zii-cfu1.dtb \ + vf610-zii-dev-rev-b.dtb \ + vf610-zii-dev-rev-c.dtb \ + vf610-zii-scu4-aib.dtb \ + vf610-zii-spb4.dtb \ + vf610-zii-ssmb-dtu.dtb \ + vf610-zii-ssmb-spu3.dtb diff --git a/arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..14c411f146f5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + panel: panel { + compatible = "edt,et057090dhu"; + backlight = <&bl>; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */ + vin-supply = <®_5v0>; + }; +}; + +&bl { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_3v3>; + status = "okay"; +}; + +&dcu0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dcu0_1>; + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&dspi1 { + status = "okay"; + + mcp2515can: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_module_3v3 { + vin-supply = <®_3v3>; +}; + +&tcon0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh_vbus>; +}; + +&iomuxc { + vf610-colibri { + pinctrl_can_int: can_int { + fsl,pins = < + VF610_PAD_PTB21__GPIO_43 0x22ed + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi new file mode 100644 index 000000000000..cc1e069c44e6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + * + */ + +/ { + aliases { + ethernet0 = &fec1; + ethernet1 = &fec0; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + pwms = <&pwm0 0 5000000 0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + status = "okay"; + vref-supply = <®_module_3v3_avdd>; +}; + +&adc1 { + status = "okay"; + vref-supply = <®_module_3v3_avdd>; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan0>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&clks { + assigned-clocks = <&clks VF610_CLK_ENET_SEL>, + <&clks VF610_CLK_ENET_TS_SEL>; + assigned-clock-parents = <&clks VF610_CLK_ENET_50M>, + <&clks VF610_CLK_ENET_50M>; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + disable-wp; +}; + +&fec1 { + phy-mode = "rmii"; + phy-supply = <®_module_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; + + nand@0 { + compatible = "fsl,vf610-nfc-nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <32>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&iomuxc { + vf610-colibri { + pinctrl_flexcan0: can0grp { + fsl,pins = < + VF610_PAD_PTB14__CAN0_RX 0x31F1 + VF610_PAD_PTB15__CAN0_TX 0x31F2 + >; + }; + + pinctrl_flexcan1: can1grp { + fsl,pins = < + VF610_PAD_PTB16__CAN1_RX 0x31F1 + VF610_PAD_PTB17__CAN1_TX 0x31F2 + >; + }; + + pinctrl_gpio_ext: gpio_ext { + fsl,pins = < + VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ + VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ + VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ + >; + }; + + pinctrl_dcu0_1: dcu0grp_1 { + fsl,pins = < + VF610_PAD_PTE0__DCU0_HSYNC 0x1902 + VF610_PAD_PTE1__DCU0_VSYNC 0x1902 + VF610_PAD_PTE2__DCU0_PCLK 0x1902 + VF610_PAD_PTE4__DCU0_DE 0x1902 + VF610_PAD_PTE5__DCU0_R0 0x1902 + VF610_PAD_PTE6__DCU0_R1 0x1902 + VF610_PAD_PTE7__DCU0_R2 0x1902 + VF610_PAD_PTE8__DCU0_R3 0x1902 + VF610_PAD_PTE9__DCU0_R4 0x1902 + VF610_PAD_PTE10__DCU0_R5 0x1902 + VF610_PAD_PTE11__DCU0_R6 0x1902 + VF610_PAD_PTE12__DCU0_R7 0x1902 + VF610_PAD_PTE13__DCU0_G0 0x1902 + VF610_PAD_PTE14__DCU0_G1 0x1902 + VF610_PAD_PTE15__DCU0_G2 0x1902 + VF610_PAD_PTE16__DCU0_G3 0x1902 + VF610_PAD_PTE17__DCU0_G4 0x1902 + VF610_PAD_PTE18__DCU0_G5 0x1902 + VF610_PAD_PTE19__DCU0_G6 0x1902 + VF610_PAD_PTE20__DCU0_G7 0x1902 + VF610_PAD_PTE21__DCU0_B0 0x1902 + VF610_PAD_PTE22__DCU0_B1 0x1902 + VF610_PAD_PTE23__DCU0_B2 0x1902 + VF610_PAD_PTE24__DCU0_B3 0x1902 + VF610_PAD_PTE25__DCU0_B4 0x1902 + VF610_PAD_PTE26__DCU0_B5 0x1902 + VF610_PAD_PTE27__DCU0_B6 0x1902 + VF610_PAD_PTE28__DCU0_B7 0x1902 + >; + }; + + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x33e2 + VF610_PAD_PTD6__DSPI1_SIN 0x33e1 + VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 + VF610_PAD_PTD8__DSPI1_SCK 0x33e2 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB20__GPIO_42 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_bl_on: gpio_bl_on { + fsl,pins = < + VF610_PAD_PTC0__GPIO_45 0x22ef + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c0_gpio: i2c0gpiogrp { + fsl,pins = < + VF610_PAD_PTB14__GPIO_36 0x37ff + VF610_PAD_PTB15__GPIO_37 0x37ff + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1182 + VF610_PAD_PTB1__FTM0_CH1 0x1182 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + VF610_PAD_PTB8__FTM1_CH0 0x1182 + VF610_PAD_PTB9__FTM1_CH1 0x1182 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + VF610_PAD_PTB12__UART0_RTS 0x21a2 + VF610_PAD_PTB13__UART0_CTS 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + + pinctrl_usbh1_reg: gpio_usb_vbus { + fsl,pins = < + VF610_PAD_PTD4__GPIO_83 0x22ed + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts new file mode 100644 index 000000000000..088964f8dc4b --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +/dts-v1/; +#include "vf500-colibri.dtsi" +#include "vf-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri VF50 on Colibri Evaluation Board"; + compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500"; +}; + +&touchscreen { + vf50-ts-min-pressure = <200>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi new file mode 100644 index 000000000000..8af7ed56e653 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +#include "vf500.dtsi" +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50 COM"; + compatible = "toradex,vf500-colibri_vf50", "fsl,vf500"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + touchscreen: vf50-touchscreen { + compatible = "toradex,vf50-touchscreen"; + io-channels = <&adc1 0>,<&adc0 0>, + <&adc0 1>,<&adc1 2>; + xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "idle","default","gpios"; + pinctrl-0 = <&pinctrl_touchctrl_idle>; + pinctrl-1 = <&pinctrl_touchctrl_default>; + pinctrl-2 = <&pinctrl_touchctrl_gpios>; + vf50-ts-min-pressure = <200>; + status = "disabled"; + }; +}; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; +}; + +&iomuxc { + vf610-colibri { + pinctrl_touchctrl_idle: touchctrl_idle { + fsl,pins = < + VF610_PAD_PTA18__GPIO_8 0x006d + VF610_PAD_PTA19__GPIO_9 0x006c + >; + }; + + pinctrl_touchctrl_default: touchctrl_default { + fsl,pins = < + VF610_PAD_PTA18__ADC0_SE0 0x0040 + VF610_PAD_PTA19__ADC0_SE1 0x0040 + VF610_PAD_PTA16__ADC1_SE0 0x0040 + VF610_PAD_PTB2__ADC1_SE2 0x0040 + >; + }; + + pinctrl_touchctrl_gpios: touchctrl_gpios { + fsl,pins = < + VF610_PAD_PTA23__GPIO_13 0x22e9 + VF610_PAD_PTB23__GPIO_93 0x22e9 + VF610_PAD_PTA22__GPIO_12 0x22e9 + VF610_PAD_PTA11__GPIO_4 0x22e9 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf500.dtsi b/arch/arm/boot/dts/nxp/vf/vf500.dtsi new file mode 100644 index 000000000000..0c0dd442300a --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf500.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2013 Freescale Semiconductor, Inc. + +#include "vfxxx.dtsi" +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a5_cpu: cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + soc { + bus@40000000 { + + intc: interrupt-controller@40003000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x40003000 0x1000>, + <0x40002100 0x100>; + }; + + global_timer: timer@40002200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x40002200 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clks VF610_CLK_PLATFORM_BUS>; + }; + }; + + bus@40080000 { + pmu@40089000 { + compatible = "arm,cortex-a5-pmu"; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a5_cpu>; + reg = <0x40089000 0x1000>; + }; + }; + + }; +}; + +&mscm_ir { + interrupt-parent = <&intc>; +}; + +&wdoga5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts new file mode 100644 index 000000000000..e4f691d601cc --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts @@ -0,0 +1,537 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "Liebherr BK4 controller"; + compatible = "lwn,bk4", "fsl,vf610"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + audio_ext: oscillator-audio { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + enet_ext: oscillator-ethernet { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + /* LED D5 */ + led0: led-heartbeat { + label = "heartbeat"; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vcc_3v3_mcu: regulator-vcc3v3mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + spi { + compatible = "spi-gpio"; + pinctrl-0 = <&pinctrl_gpio_spi>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + /* PTD12 ->RPIO[91] */ + sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + /* PTD10 ->RPIO[89] */ + miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + num-chipselects = <0>; + + gpio@0 { + compatible = "pisosr-gpio"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + /* PTB18 -> RGPIO[40] */ + load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + spi-max-frequency = <100000>; + }; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&clks { + clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; + clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; +}; + +&dspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi0>; + bus-num = <0>; + status = "okay"; + + spidev0@0 { + compatible = "lwn,bk4"; + spi-max-frequency = <30000000>; + reg = <0>; + fsl,spi-cs-sck-delay = <200>; + fsl,spi-sck-cs-delay = <400>; + }; +}; + +&dspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi3>; + bus-num = <3>; + status = "okay"; + spi-slave; + #address-cells = <0>; + + slave { + compatible = "lwn,bk4"; + spi-max-frequency = <30000000>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec0 { + phy-mode = "rmii"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + clocks = <&clks VF610_CLK_ENET_50M>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec1 { + phy-mode = "rmii"; + phy-handle = <ðphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + clocks = <&clks VF610_CLK_ENET_50M>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24c256: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + m41t62: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; + + nand@0 { + compatible = "fsl,vf610-nfc-nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <24>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; + }; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + status = "okay"; + + n25q128a13_4: flash@0 { + compatible = "n25q128a13", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + reg = <0>; + }; + + n25q128a13_2: flash@2 { + compatible = "n25q128a13", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <2>; + reg = <2>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + /delete-property/dma-names; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + /delete-property/dma-names; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + /delete-property/dma-names; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + /delete-property/dma-names; + status = "okay"; +}; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* One_Wire_PSU_EN */ + VF610_PAD_PTC29__GPIO_102 0x1183 + /* SPI ENABLE */ + VF610_PAD_PTB26__GPIO_96 0x1183 + /* EB control */ + VF610_PAD_PTE14__GPIO_119 0x1183 + VF610_PAD_PTE4__GPIO_109 0x1181 + /* Feedback_Lines */ + VF610_PAD_PTC31__GPIO_104 0x1181 + VF610_PAD_PTA7__GPIO_134 0x1181 + VF610_PAD_PTD9__GPIO_88 0x1181 + VF610_PAD_PTE1__GPIO_106 0x1183 + VF610_PAD_PTB2__GPIO_24 0x1181 + VF610_PAD_PTB3__GPIO_25 0x1181 + VF610_PAD_PTB1__GPIO_23 0x1181 + /* SDHC Enable */ + VF610_PAD_PTE19__GPIO_124 0x1183 + /* SDHC Overcurrent */ + VF610_PAD_PTB23__GPIO_93 0x1181 + /* GPI */ + VF610_PAD_PTE2__GPIO_107 0x1181 + VF610_PAD_PTE3__GPIO_108 0x1181 + VF610_PAD_PTE5__GPIO_110 0x1181 + VF610_PAD_PTE6__GPIO_111 0x1181 + /* GPO */ + VF610_PAD_PTE0__GPIO_105 0x1183 + VF610_PAD_PTE7__GPIO_112 0x1183 + /* RS485 Control */ + VF610_PAD_PTB8__GPIO_30 0x1183 + VF610_PAD_PTB9__GPIO_31 0x1183 + VF610_PAD_PTE8__GPIO_113 0x1183 + /* MPBUS MPB_EN */ + VF610_PAD_PTE28__GPIO_133 0x1183 + /* MISC */ + VF610_PAD_PTE10__GPIO_115 0x1183 + VF610_PAD_PTE11__GPIO_116 0x1183 + VF610_PAD_PTE17__GPIO_122 0x1183 + VF610_PAD_PTC30__GPIO_103 0x1183 + VF610_PAD_PTB0__GPIO_22 0x1181 + /* RESETINFO */ + VF610_PAD_PTE26__GPIO_131 0x1183 + VF610_PAD_PTD6__GPIO_85 0x1181 + VF610_PAD_PTE27__GPIO_132 0x1181 + VF610_PAD_PTE13__GPIO_118 0x1181 + VF610_PAD_PTE21__GPIO_126 0x1181 + VF610_PAD_PTE22__GPIO_127 0x1181 + /* EE_5V_EN */ + VF610_PAD_PTE18__GPIO_123 0x1183 + /* EE_5V_OC_N */ + VF610_PAD_PTE25__GPIO_130 0x1181 + >; + }; + + pinctrl_can0: can0grp { + fsl,pins = < + VF610_PAD_PTB14__CAN0_RX 0x1181 + VF610_PAD_PTB15__CAN0_TX 0x1182 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + VF610_PAD_PTB16__CAN1_RX 0x1181 + VF610_PAD_PTB17__CAN1_TX 0x1182 + >; + }; + + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB18__DSPI0_CS1 0x1182 + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_dspi3: dspi3grp { + fsl,pins = < + VF610_PAD_PTD10__DSPI3_CS0 0x1181 + VF610_PAD_PTD11__DSPI3_SIN 0x1181 + VF610_PAD_PTD12__DSPI3_SOUT 0x1182 + VF610_PAD_PTD13__DSPI3_SCK 0x1181 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30dd + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + /* Heart bit LED */ + VF610_PAD_PTE12__GPIO_117 0x1183 + /* LEDS */ + VF610_PAD_PTE15__GPIO_120 0x1183 + VF610_PAD_PTA12__GPIO_5 0x1183 + VF610_PAD_PTA16__GPIO_6 0x1183 + VF610_PAD_PTE9__GPIO_114 0x1183 + VF610_PAD_PTE20__GPIO_125 0x1183 + VF610_PAD_PTE23__GPIO_128 0x1183 + VF610_PAD_PTE16__GPIO_121 0x1183 + >; + }; + + pinctrl_gpio_spi: pinctrl-gpio-spi { + fsl,pins = < + VF610_PAD_PTB18__GPIO_40 0x1183 + VF610_PAD_PTD10__GPIO_89 0x1183 + VF610_PAD_PTD12__GPIO_91 0x1183 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x34df + VF610_PAD_PTA23__I2C2_SDA 0x34df + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f + VF610_PAD_PTD1__QSPI0_A_CS0 0x397f + VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f + VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f + VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f + VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f + VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f + VF610_PAD_PTD8__QSPI0_B_CS0 0x397f + VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f + VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTB6__UART2_TX 0x21a2 + VF610_PAD_PTB7__UART2_RX 0x21a1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA20__UART3_TX 0x21a2 + VF610_PAD_PTA21__UART3_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts new file mode 100644 index 000000000000..fb661e8a2dc6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +/dts-v1/; +#include "vf610-colibri.dtsi" +#include "vf-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri VF61 on Colibri Evaluation Board"; + compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi new file mode 100644 index 000000000000..607cec2df861 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +#include "vf610.dtsi" +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61 COM"; + compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <50000000>; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts new file mode 100644 index 000000000000..703f375d7e24 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013 Linaro Limited + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "PHYTEC Cosmic/Cosmic+ Board"; + compatible = "phytec,vf610-cosmic", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP1,115200"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + enet_ext: enet_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&clks { + clocks = <&sxosc>, <&fxosc>, <&enet_ext>; + clock-names = "sxosc", "fxosc", "enet_ext"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&iomuxc { + vf610-cosmic { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h b/arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h new file mode 100644 index 000000000000..b7b7322a2d1b --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h @@ -0,0 +1,856 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DTS_VF610_PINFUNC_H +#define __DTS_VF610_PINFUNC_H + +/* + * The pin function ID for VF610 is a tuple of: + * + */ + +#define ALT0 0x0 +#define ALT1 0x1 +#define ALT2 0x2 +#define ALT3 0x3 +#define ALT4 0x4 +#define ALT5 0x5 +#define ALT6 0x6 +#define ALT7 0x7 + + +#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 +#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 +#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 +#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 +#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 +#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 +#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 +#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 +#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 +#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 +#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 +#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 +#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 +#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 +#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 +#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 +#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 +#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 +#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 +#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 +#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 +#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 +#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 +#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 +#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 +#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 +#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 +#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 +#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 +#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 +#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 +#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 +#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 +#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 +#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 +#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 +#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 +#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 +#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 +#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 +#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 +#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 +#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 +#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 +#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 +#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 +#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 +#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 +#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 +#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 +#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 +#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 +#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 +#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 +#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 +#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 +#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 +#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 +#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 +#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 +#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 +#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 +#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 +#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 +#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 +#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 +#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 +#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 +#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 +#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 +#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 +#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 +#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 +#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 +#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 +#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 +#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 +#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 +#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 +#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 +#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 +#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 +#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 +#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 +#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 +#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 +#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 +#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 +#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 +#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 +#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 +#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 +#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 +#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 +#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 +#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 +#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 +#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 +#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 +#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 +#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 +#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 +#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 +#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 +#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 +#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 +#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 +#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 +#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 +#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 +#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 +#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 +#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 +#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 +#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 +#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 +#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 +#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 +#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 +#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 +#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 +#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 +#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 +#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 +#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 +#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 +#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 +#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 +#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 +#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 +#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 +#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 +#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 +#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 +#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 +#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 +#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 +#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 +#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 +#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 +#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 +#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 +#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 +#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 +#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 +#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 +#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 +#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 +#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 +#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 +#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 +#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 +#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 +#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 +#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 +#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 +#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 +#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 +#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 +#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 +#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 +#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 +#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 +#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 +#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 +#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 +#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 +#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 +#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 +#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 +#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 +#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 +#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 +#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 +#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 +#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 +#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 +#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 +#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 +#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 +#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 +#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 +#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 +#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 +#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 +#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 +#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 +#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 +#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 +#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 +#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 +#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 +#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 +#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 +#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 +#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 +#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 +#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 +#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 +#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 +#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 +#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 +#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 +#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 +#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 +#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 +#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 +#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 +#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 +#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 +#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 +#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 +#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 +#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 +#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 +#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 +#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 +#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 +#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 +#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 +#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 +#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 +#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 +#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 +#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 +#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 +#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 +#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 +#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 +#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 +#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 +#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 +#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 +#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 +#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 +#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 +#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 +#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 +#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 +#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 +#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 +#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 +#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 +#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 +#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 +#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 +#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 +#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 +#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 +#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 +#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 +#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 +#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 +#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 +#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 +#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 +#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 +#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 +#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 +#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 +#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 +#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 +#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 +#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 +#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 +#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 +#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 +#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 +#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 +#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 +#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 +#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 +#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 +#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 +#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 +#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 +#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 +#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 +#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 +#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 +#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 +#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 +#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 +#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 +#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 +#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 +#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 +#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 +#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 +#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 +#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 +#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 +#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 +#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 +#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 +#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 +#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 +#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 +#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 +#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 +#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 +#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 +#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 +#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 +#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 +#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 +#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 +#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 +#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 +#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 +#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 +#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 +#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 +#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 +#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 +#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 +#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 +#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 +#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 +#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 +#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 +#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 +#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 +#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 +#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 +#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 +#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 +#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 +#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 +#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 +#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 +#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 +#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 +#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 +#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 +#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 +#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 +#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 +#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 +#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 +#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 +#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 +#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 +#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 +#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 +#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 +#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 +#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 +#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 +#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 +#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 +#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 +#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 +#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 +#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 +#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 +#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 +#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 +#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 +#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 +#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 +#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 +#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 +#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 +#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 +#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 +#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 +#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 +#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 +#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 +#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 +#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 +#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 +#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 +#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 +#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 +#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 +#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 +#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 +#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 +#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 +#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 +#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 +#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 +#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 +#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 +#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 +#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 +#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 +#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 +#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 +#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 +#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 +#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 +#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 +#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 +#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 +#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 +#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 +#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 +#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 +#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 +#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 +#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 +#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 +#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 +#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 +#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 +#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 +#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 +#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 +#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 +#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 +#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 +#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 +#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 +#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 +#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 +#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 +#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 +#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 +#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 +#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 +#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 +#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 +#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 +#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 +#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 +#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 +#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 +#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 +#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 +#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 +#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 +#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 +#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 +#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 +#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 +#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 +#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 +#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 +#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 +#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 +#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 +#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 +#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 +#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 +#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 +#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 +#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 +#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 +#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 +#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 +#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 +#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 +#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 +#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 +#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 +#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 +#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 +#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 +#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 +#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 +#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 +#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 +#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 +#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 +#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 +#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 +#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 +#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 +#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 +#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 +#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 +#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 +#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 +#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 +#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 +#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 +#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 +#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 +#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 +#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 +#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 +#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 +#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 +#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 +#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 +#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 +#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 +#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 +#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 +#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 +#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 +#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 +#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 +#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 +#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 +#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 +#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 +#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 +#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 +#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 +#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 +#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 +#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 +#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 +#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 +#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 +#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 +#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 +#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 +#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 +#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 +#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 +#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 +#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 +#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 +#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 +#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 +#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 +#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 +#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 +#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 +#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 +#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 +#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 +#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 +#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 +#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 +#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 +#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 +#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 +#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 +#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 +#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 +#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 +#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 +#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 +#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 +#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 +#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 +#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 +#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 +#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 +#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 +#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 +#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 +#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 +#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 +#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 +#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 +#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 +#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 +#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 +#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 +#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 +#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 +#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 +#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 +#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 +#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 +#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 +#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 +#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 +#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 +#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 +#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 +#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 +#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 +#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 +#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 +#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 +#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 +#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 +#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 +#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 +#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 +#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 +#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 +#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 +#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 +#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 +#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 +#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 +#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 +#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 +#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 +#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 +#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 +#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 +#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 +#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 +#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 +#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 +#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 +#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 +#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 +#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 +#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 +#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 +#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 +#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 +#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 +#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 +#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 +#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 +#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 +#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 +#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 +#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 +#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 +#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 +#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 +#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 +#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 +#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 +#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 +#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 +#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 +#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 +#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 +#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 +#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 +#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 +#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 +#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 +#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 +#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 +#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 +#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 +#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 +#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 +#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 +#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 +#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 +#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 +#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 +#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 +#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 +#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 +#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 +#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 +#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 +#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 +#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 +#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 +#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 +#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 +#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 +#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 +#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 +#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 +#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 +#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 +#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 +#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 +#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 +#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 +#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 +#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 +#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 +#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 +#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 +#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 +#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 +#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 +#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 +#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 +#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 +#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 +#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 +#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 +#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 +#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 +#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 +#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 +#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 +#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 +#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 +#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 +#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 +#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 +#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 +#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 +#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 +#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 +#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 +#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 +#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 +#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 +#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 +#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 +#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 +#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 +#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 +#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 +#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 +#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 +#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 +#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 +#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 +#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 +#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 +#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 +#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 +#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 +#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 +#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 +#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 +#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 +#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 +#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 +#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 +#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 +#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 +#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 +#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 +#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 +#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 +#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 +#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 +#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 +#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 +#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 +#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 +#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 +#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 +#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 +#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 +#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 +#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 +#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 +#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 +#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 +#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 +#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 +#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 +#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 +#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 +#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 +#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 +#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 +#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 +#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 +#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 +#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 +#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 +#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 +#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 +#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 +#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 +#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 +#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 +#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 +#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 +#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 +#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 +#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 +#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 +#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 +#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 +#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 +#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 +#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 +#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 +#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 +#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 +#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 +#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 +#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 +#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 +#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 +#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 +#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 +#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 +#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 +#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 +#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 +#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 +#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 + +#endif diff --git a/arch/arm/boot/dts/nxp/vf/vf610-twr.dts b/arch/arm/boot/dts/nxp/vf/vf610-twr.dts new file mode 100644 index 000000000000..6c246d5aa032 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-twr.dts @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2013 Freescale Semiconductor, Inc. + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "VF610 Tower Board"; + compatible = "fsl,vf610-twr", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP1,115200"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + audio_ext: mclk_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + enet_ext: eth_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vcc_3v3_mcu: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_ad5>; + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&clks { + clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; + clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; + assigned-clocks = <&clks VF610_CLK_ENET_SEL>, + <&clks VF610_CLK_ENET_TS_SEL>; + assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, + <&clks VF610_CLK_ENET_EXT>; +}; + +&dspi0 { + bus-num = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi0>; + status = "okay"; + + sflash: at26df081a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at26df081a"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec0 { + phy-mode = "rmii"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&fec1 { + phy-mode = "rmii"; + phy-handle = <ðphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + codec: sgtl5000@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&clks VF610_CLK_SAI2>; + }; +}; + +&iomuxc { + vf610-twr { + pinctrl_adc0_ad5: adc0ad5grp { + fsl,pins = < + VF610_PAD_PTC30__ADC0_SE5 0xa1 + >; + }; + + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x30d3 + VF610_PAD_PTB15__I2C0_SDA 0x30d3 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD31__NF_IO15 0x28df + VF610_PAD_PTD30__NF_IO14 0x28df + VF610_PAD_PTD29__NF_IO13 0x28df + VF610_PAD_PTD28__NF_IO12 0x28df + VF610_PAD_PTD27__NF_IO11 0x28df + VF610_PAD_PTD26__NF_IO10 0x28df + VF610_PAD_PTD25__NF_IO9 0x28df + VF610_PAD_PTD24__NF_IO8 0x28df + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1582 + VF610_PAD_PTB1__FTM0_CH1 0x1582 + VF610_PAD_PTB2__FTM0_CH2 0x1582 + VF610_PAD_PTB3__FTM0_CH3 0x1582 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed + VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee + VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed + VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed + VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed + VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed + VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTB6__UART2_TX 0x21a2 + VF610_PAD_PTB7__UART2_RX 0x21a1 + >; + }; + }; +}; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; + + nand@0 { + compatible = "fsl,vf610-nfc-nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <24>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts new file mode 100644 index 000000000000..1a19aec8957b --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 CFU1 Board"; + compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-fail { + label = "zii:red:fail"; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-status { + label = "zii:green:status"; + gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-debug-a { + label = "zii:green:debug_a"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-debug-b { + label = "zii:green:debug_b"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sff: sfp { + compatible = "sff,sff"; + pinctrl-0 = <&pinctrl_optical>; + pinctrl-names = "default"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 28VDC_IN */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + /* + * Some CFU1s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_3"; + }; + + port@5 { + reg = <5>; + label = "eth_fc_1000_1"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff>; + }; + + port@6 { + reg = <6>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + label = "nvm"; + }; + + eeprom@54 { + compatible = "atmel,24c04"; + reg = <0x54>; + label = "nameplate"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + VF610_PAD_PTE3__GPIO_108 0x31c2 + VF610_PAD_PTE4__GPIO_109 0x31c2 + VF610_PAD_PTE5__GPIO_110 0x31c2 + VF610_PAD_PTE6__GPIO_111 0x31c2 + >; + }; + + pinctrl_optical: optical-grp { + fsl,pins = < + /* SFF SD input */ + VF610_PAD_PTE27__GPIO_132 0x3061 + + /* SFF Transmit disable output */ + VF610_PAD_PTE13__GPIO_118 0x3043 + >; + }; + + pinctrl_switch: switch-grp { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x3061 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts new file mode 100644 index 000000000000..16b4e06c4efa --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610-zii-dev.dtsi" + +/ { + model = "ZII VF610 Development Board, Rev B"; + compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; + + mdio-mux { + compatible = "mdio-mux-gpio"; + pinctrl-0 = <&pinctrl_mdio_mux>; + pinctrl-names = "default"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH + &gpio0 9 GPIO_ACTIVE_HIGH + &gpio0 24 GPIO_ACTIVE_HIGH + &gpio0 25 GPIO_ACTIVE_HIGH>; + mdio-parent-bus = <&mdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio_mux_1: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@0 { + compatible = "marvell,mv88e6085"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + dsa,member = <0 0>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + eeprom-length = <512>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&switch0phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&switch0phy2>; + }; + + switch0port5: port@5 { + reg = <5>; + label = "dsa"; + phy-mode = "rgmii-txid"; + link = <&switch1port6 + &switch2port9>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + switch0phy0: switch0phy0@0 { + reg = <0>; + interrupt-parent = <&switch0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + switch0phy1: switch1phy0@1 { + reg = <1>; + interrupt-parent = <&switch0>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + switch0phy2: switch1phy0@2 { + reg = <2>; + interrupt-parent = <&switch0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; + + mdio_mux_2: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + switch1: switch@0 { + compatible = "marvell,mv88e6085"; + pinctrl-0 = <&pinctrl_gpio_switch1>; + pinctrl-names = "default"; + reg = <0>; + dsa,member = <0 1>; + interrupt-parent = <&gpio0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + eeprom-length = <512>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + phy-handle = <&switch1phy0>; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-handle = <&switch1phy1>; + }; + + port@2 { + reg = <2>; + label = "lan5"; + phy-handle = <&switch1phy2>; + }; + + switch1port5: port@5 { + reg = <5>; + label = "dsa"; + link = <&switch2port9>; + phy-mode = "1000base-x"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch1port6: port@6 { + reg = <6>; + label = "dsa"; + phy-mode = "rgmii-txid"; + link = <&switch0port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch1phy0: switch1phy0@0 { + reg = <0>; + interrupt-parent = <&switch1>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch1phy1: switch1phy0@1 { + reg = <1>; + interrupt-parent = <&switch1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch1phy2: switch1phy0@2 { + reg = <2>; + interrupt-parent = <&switch1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; + + mdio_mux_4: mdio@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + switch2: switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan6"; + phy-handle = <&switch2phy0>; + phy-mode = "sgmii"; + }; + + port@1 { + reg = <1>; + label = "lan7"; + phy-handle = <&switch2phy1>; + phy-mode = "sgmii"; + }; + + port@2 { + reg = <2>; + label = "lan8"; + phy-handle = <&switch2phy2>; + }; + + port@3 { + reg = <3>; + label = "optical3"; + + fixed-link { + speed = <1000>; + full-duplex; + link-gpios = <&gpio6 2 + GPIO_ACTIVE_HIGH>; + }; + }; + + port@4 { + reg = <4>; + label = "optical4"; + + fixed-link { + speed = <1000>; + full-duplex; + link-gpios = <&gpio6 3 + GPIO_ACTIVE_HIGH>; + }; + }; + + switch2port9: port@9 { + reg = <9>; + label = "dsa"; + phy-mode = "1000base-x"; + link = <&switch1port5 + &switch0port5>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch2phy0: phy@0 { + reg = <0>; + }; + switch2phy1: phy@1 { + reg = <1>; + }; + switch2phy2: phy@2 { + reg = <2>; + }; + }; + }; + }; + + mdio_mux_8: mdio@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + spi-0 { + compatible = "spi-gpio"; + pinctrl-0 = <&pinctrl_gpio_spi0>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW + &gpio1 8 GPIO_ACTIVE_HIGH>; + num-chipselects = <2>; + + flash@0 { + compatible = "m25p128", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + at93c46d@1 { + compatible = "atmel,at93c46d"; + pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; + pinctrl-names = "default"; + reg = <1>; + spi-max-frequency = <500000>; + spi-cs-high; + data-size = <16>; + select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&i2c0 { + gpio5: io-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + }; + + gpio6: io-expander@22 { + compatible = "nxp,pca9554"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9554_22>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + i2c-mux@70 { + compatible = "nxp,pca9548"; + pinctrl-0 = <&pinctrl_i2c_mux_reset>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sfp1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + sfp2: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + sfp3: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + sfp4: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + }; +}; + +&mdio1 { + clock-frequency = <5000000>; +}; + +&iomuxc { + pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { + fsl,pins = < + VF610_PAD_PTE27__GPIO_132 0x33e2 + >; + }; + + pinctrl_gpio_spi0: pinctrl-gpio-spi0 { + fsl,pins = < + VF610_PAD_PTB22__GPIO_44 0x33e2 + VF610_PAD_PTB21__GPIO_43 0x33e2 + VF610_PAD_PTB20__GPIO_42 0x33e1 + VF610_PAD_PTB19__GPIO_41 0x33e2 + VF610_PAD_PTB18__GPIO_40 0x33e2 + >; + }; + + pinctrl_mdio_mux: pinctrl-mdio-mux { + fsl,pins = < + VF610_PAD_PTA18__GPIO_8 0x31c2 + VF610_PAD_PTA19__GPIO_9 0x31c2 + VF610_PAD_PTB2__GPIO_24 0x31c2 + VF610_PAD_PTB3__GPIO_25 0x31c2 + >; + }; + + pinctrl_pca9554_22: pinctrl-pca95540-22 { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts new file mode 100644 index 000000000000..6f9878f124c4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610-zii-dev.dtsi" + +/ { + model = "ZII VF610 Development Board, Rev C"; + compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610"; + + mdio-mux { + compatible = "mdio-mux-gpio"; + pinctrl-0 = <&pinctrl_mdio_mux>; + pinctrl-names = "default"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH + &gpio0 9 GPIO_ACTIVE_HIGH + &gpio0 25 GPIO_ACTIVE_HIGH>; + mdio-parent-bus = <&mdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio_mux_1: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <65536>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&switch0phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&switch0phy3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-handle = <&switch0phy4>; + }; + + switch0port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xaui"; + link = <&switch1port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy1: switch0phy@1 { + reg = <1>; + interrupt-parent = <&switch0>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch0phy2: switch0phy@2 { + reg = <2>; + interrupt-parent = <&switch0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch0phy3: switch0phy@3 { + reg = <3>; + interrupt-parent = <&switch0>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch0phy4: switch0phy@4 { + reg = <4>; + interrupt-parent = <&switch0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; + + mdio_mux_2: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + switch1: switch@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch1>; + pinctrl-names = "default"; + reg = <0>; + dsa,member = <0 1>; + eeprom-length = <65536>; + interrupt-parent = <&gpio0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan5"; + phy-handle = <&switch1phy1>; + }; + + port@2 { + reg = <2>; + label = "lan6"; + phy-handle = <&switch1phy2>; + }; + + port@3 { + reg = <3>; + label = "lan7"; + phy-handle = <&switch1phy3>; + }; + + port@4 { + reg = <4>; + label = "lan8"; + phy-handle = <&switch1phy4>; + }; + + port@9 { + reg = <9>; + label = "sff2"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff2>; + }; + + switch1port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xaui"; + link = <&switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; + }; + }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch1phy1: switch1phy@1 { + reg = <1>; + interrupt-parent = <&switch1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch1phy2: switch1phy@2 { + reg = <2>; + interrupt-parent = <&switch1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch1phy3: switch1phy@3 { + reg = <3>; + interrupt-parent = <&switch1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + switch1phy4: switch1phy@4 { + reg = <4>; + interrupt-parent = <&switch1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; + + mdio_mux_4: mdio@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sff2: sff2 { + /* lower */ + compatible = "sff,sff"; + i2c-bus = <&sff2_i2c>; + los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + }; + + sff3: sff3 { + /* upper */ + compatible = "sff,sff"; + i2c-bus = <&sff3_i2c>; + los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + }; +}; + +&dspi0 { + bus-num = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi0>; + status = "okay"; + spi-num-chipselects = <2>; + + flash@0 { + compatible = "m25p128", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + atzb-rf-233@1 { + compatible = "atmel,at86rf233"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctr_atzb_rf_233>; + + spi-max-frequency = <7500000>; + reg = <1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpio3>; + xtal-trim = /bits/ 8 <0x06>; + + sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio6 10 GPIO_ACTIVE_LOW>; + + fsl,spi-cs-sck-delay = <180>; + fsl,spi-sck-cs-delay = <250>; + }; +}; + +&i2c0 { + /* + * U712 + * + * Exposed signals: + * P1 - WE2_CMD + * P2 - WE2_CLK + */ + gpio5: io-expander@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* + * U121 + * + * Exposed signals: + * I/O0 - ENET_SWR_EN + * I/O1 - ESW1_RESETn + * I/O2 - ARINC_RESET + * I/O3 - DD1_IO_RESET + * I/O4 - ESW2_RESETn + * I/O5 - ESW3_RESETn + * I/O6 - ESW4_RESETn + * I/O8 - TP909 + * I/O9 - FEM_SEL + * I/O10 - WIFI_RESETn + * I/O11 - PHY_RSTn + * I/O12 - OPT1_SD + * I/O13 - OPT2_SD + * I/O14 - OPT1_TX_DIS + * I/O15 - OPT2_TX_DIS + */ + gpio6: sx1503@20 { + compatible = "semtech,sx1503q"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sx1503_20>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + interrupt-controller; + }; + + /* + * U715 + * + * Exposed signals: + * IO0 - WE1_CLK + * IO1 - WE1_CMD + */ + gpio7: io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + }; +}; + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + read-only; + }; +}; + +&i2c2 { + i2c-mux@70 { + compatible = "nxp,pca9548"; + pinctrl-0 = <&pinctrl_i2c_mux_reset>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sff2_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sff3_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&gpio0 { + eth0_intrp { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + input; + line-name = "sx1503-irq"; + }; +}; + +&gpio3 { + eth0_intrp { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "eth0-intrp"; + }; +}; + +&fec0 { + mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0_phy_int>; + + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + }; + }; +}; + +&iomuxc { + pinctr_atzb_rf_233: pinctrl-atzb-rf-233 { + fsl,pins = < + VF610_PAD_PTB2__GPIO_24 0x31c2 + VF610_PAD_PTE27__GPIO_132 0x33e2 + >; + }; + + + pinctrl_sx1503_20: pinctrl-sx1503-20 { + fsl,pins = < + VF610_PAD_PTB1__GPIO_23 0x219d + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA20__UART3_TX 0x21a2 + VF610_PAD_PTA21__UART3_RX 0x21a1 + >; + }; + + pinctrl_mdio_mux: pinctrl-mdio-mux { + fsl,pins = < + VF610_PAD_PTA18__GPIO_8 0x31c2 + VF610_PAD_PTA19__GPIO_9 0x31c2 + VF610_PAD_PTB3__GPIO_25 0x31c2 + >; + }; + + pinctrl_fec0_phy_int: pinctrl-fec0-phy-int { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi new file mode 100644 index 000000000000..ce5e52896b19 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi @@ -0,0 +1,450 @@ +/* + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "vf610.dtsi" + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-0 = <&pinctrl_usb_vbus>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 6 0>; + }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* VCC_1V5 */ + <&adc0 9>, /* VCC_1V8 */ + <&adc1 8>, /* VCC_1V0 */ + <&adc1 9>; /* VCC_1V2 */ + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_ad5>; + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; + status = "okay"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; + + ds1682@6b { + compatible = "dallas,ds1682"; + reg = <0x6b>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + status = "okay"; + + /* + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR + * modes, so, spi-max-frequency is limited to 90MHz + */ + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <0>; + m25p,fast-read; + }; + + flash@2 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <2>; + m25p,fast-read; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbdev0 { + disable-over-current; + vbus-supply = <&usb0_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&tempsensor { + io-channels = <&adc0 16>; +}; + +&iomuxc { + pinctrl_adc0_ad5: adc0ad5grp { + fsl,pins = < + VF610_PAD_PTC30__ADC0_SE5 0x00a1 + >; + }; + + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB18__DSPI0_CS1 0x1182 + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_dspi2: dspi2grp { + fsl,pins = < + VF610_PAD_PTD31__DSPI2_CS1 0x1182 + VF610_PAD_PTD30__DSPI2_CS0 0x1182 + VF610_PAD_PTD29__DSPI2_SIN 0x1181 + VF610_PAD_PTD28__DSPI2_SOUT 0x1182 + VF610_PAD_PTD27__DSPI2_SCK 0x1182 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_spi0: pinctrl-gpio-spi0 { + fsl,pins = < + VF610_PAD_PTB22__GPIO_44 0x33e2 + VF610_PAD_PTB21__GPIO_43 0x33e2 + VF610_PAD_PTB20__GPIO_42 0x33e1 + VF610_PAD_PTB19__GPIO_41 0x33e2 + VF610_PAD_PTB18__GPIO_40 0x33e2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTB5__GPIO_27 0x219d + >; + }; + + pinctrl_gpio_switch1: pinctrl-gpio-switch1 { + fsl,pins = < + VF610_PAD_PTB4__GPIO_26 0x219d + >; + }; + + pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { + fsl,pins = < + VF610_PAD_PTE14__GPIO_119 0x31c2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c0_gpio: i2c0grp-gpio { + fsl,pins = < + VF610_PAD_PTB14__GPIO_36 0x31c2 + VF610_PAD_PTB15__GPIO_37 0x31c2 + >; + }; + + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x37ff + VF610_PAD_PTA23__I2C2_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD20__GPIO_74 0x31c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 + VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 + VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 + VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 + VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 + VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 + VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 + VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 + VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD23__UART2_TX 0x21a2 + VF610_PAD_PTD22__UART2_RX 0x21a1 + >; + }; + + pinctrl_usb_vbus: pinctrl-usb-vbus { + fsl,pins = < + VF610_PAD_PTA16__GPIO_6 0x31c2 + >; + }; + + pinctrl_usb0_host: usb0-host-grp { + fsl,pins = < + VF610_PAD_PTD6__GPIO_85 0x0062 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts new file mode 100644 index 000000000000..df1335492a19 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts @@ -0,0 +1,876 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2016-2018 Zodiac Inflight Innovations + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SCU4 AIB"; + compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio-mux { + compatible = "mdio-mux-gpio"; + pinctrl-0 = <&pinctrl_mdio_mux>; + pinctrl-names = "default"; + gpios = <&gpio4 4 GPIO_ACTIVE_HIGH + &gpio4 5 GPIO_ACTIVE_HIGH + &gpio3 30 GPIO_ACTIVE_HIGH + &gpio3 31 GPIO_ACTIVE_HIGH>; + mdio-parent-bus = <&mdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio_mux_1: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "aib2main_1"; + }; + + port@2 { + reg = <2>; + label = "aib2main_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_5"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_6"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_4"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_7"; + }; + + port@7 { + reg = <7>; + label = "modem_pic"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + switch0port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch1port10 + &switch3port10 + &switch2port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; + }; + }; + }; + }; + + mdio_mux_2: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + switch1: switch1@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 1>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "eth_cu_1000_3"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_100_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_100_3"; + }; + + switch1port9: port@9 { + reg = <9>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch3port10 + &switch2port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; + }; + + switch1port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; + }; + }; + }; + }; + + mdio_mux_4: mdio@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + switch2: switch2@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 2>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + label = "eth_fc_1000_2"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff1>; + }; + + port@3 { + reg = <3>; + label = "eth_fc_1000_3"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff2>; + }; + + port@4 { + reg = <4>; + label = "eth_fc_1000_4"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff3>; + }; + + port@5 { + reg = <5>; + label = "eth_fc_1000_5"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff4>; + }; + + port@6 { + reg = <6>; + label = "eth_fc_1000_6"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff5>; + }; + + port@7 { + reg = <7>; + label = "eth_fc_1000_7"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff6>; + }; + + port@9 { + reg = <9>; + label = "eth_fc_1000_1"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff0>; + }; + + switch2port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "2500base-x"; + link = <&switch3port9 + &switch1port9 + &switch0port10>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + }; + }; + }; + + mdio_mux_8: mdio@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + + switch3: switch3@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 3>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + label = "eth_fc_1000_8"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff7>; + }; + + port@3 { + reg = <3>; + label = "eth_fc_1000_9"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff8>; + }; + + port@4 { + reg = <4>; + label = "eth_fc_1000_10"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sff9>; + }; + + switch3port9: port@9 { + reg = <9>; + label = "dsa"; + phy-mode = "2500base-x"; + link = <&switch2port10>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + switch3port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch1port9 + &switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; + }; + }; + }; + }; + }; + + sff0: sff0 { + compatible = "sff,sff"; + i2c-bus = <&sff0_i2c>; + los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + }; + + sff1: sff1 { + compatible = "sff,sff"; + i2c-bus = <&sff1_i2c>; + los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + }; + + sff2: sff2 { + compatible = "sff,sff"; + i2c-bus = <&sff2_i2c>; + los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + }; + + sff3: sff3 { + compatible = "sff,sff"; + i2c-bus = <&sff3_i2c>; + los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + }; + + sff4: sff4 { + compatible = "sff,sff"; + i2c-bus = <&sff4_i2c>; + los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + }; + + sff5: sff5 { + compatible = "sff,sff"; + i2c-bus = <&sff5_i2c>; + los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; + }; + + sff6: sff6 { + compatible = "sff,sff"; + i2c-bus = <&sff6_i2c>; + los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + }; + + sff7: sff7 { + compatible = "sff,sff"; + i2c-bus = <&sff7_i2c>; + los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + }; + + sff8: sff8 { + compatible = "sff,sff"; + i2c-bus = <&sff8_i2c>; + los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; + + sff9: sff9 { + compatible = "sff,sff"; + i2c-bus = <&sff9_i2c>; + los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dspi0 { + pinctrl-0 = <&pinctrl_dspi0>; + pinctrl-names = "default"; + bus-num = <0>; + status = "okay"; + + adc@5 { + compatible = "holt,hi8435"; + reg = <5>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-1"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sd; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio5: io-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + temp-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; + + elapsed-time-recorder@6b { + compatible = "dallas,ds1682"; + reg = <0x6b>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; + + adc@4a { + compatible = "adi,adt7411"; + reg = <0x4a>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + gpio9: io-expander@20 { + compatible = "semtech,sx1503q"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sx1503_20>; + #gpio-cells = <2>; + reg = <0x20>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; + + temp-sensor@4e { + compatible = "national,lm75"; + reg = <0x4e>; + }; + + temp-sensor@4f { + compatible = "national,lm75"; + reg = <0x4f>; + }; + + gpio7: io-expander@23 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x23>; + }; + + adc@4a { + compatible = "adi,adt7411"; + reg = <0x4a>; + }; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + sff0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sff1_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sff2_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + sff3_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + sff4_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + pinctrl-names = "default"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + sff5_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sff6_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sff7_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + sff8_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + sff9_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB18__DSPI0_CS1 0x1182 + VF610_PAD_PTB13__DSPI0_CS4 0x1182 + VF610_PAD_PTB12__DSPI0_CS5 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_dspi2: dspi2gpio { + fsl,pins = < + VF610_PAD_PTD30__GPIO_64 0x33e2 + VF610_PAD_PTD29__GPIO_65 0x33e1 + VF610_PAD_PTD28__GPIO_66 0x33e2 + VF610_PAD_PTD27__GPIO_67 0x33e2 + VF610_PAD_PTD26__GPIO_68 0x31c2 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x37ff + VF610_PAD_PTA23__I2C2_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTB26__GPIO_96 0x31c2 + >; + }; + + pinctrl_mdio_mux: pinctrl-mdio-mux { + fsl,pins = < + VF610_PAD_PTE27__GPIO_132 0x31c2 + VF610_PAD_PTE28__GPIO_133 0x31c2 + VF610_PAD_PTE21__GPIO_126 0x31c2 + VF610_PAD_PTE22__GPIO_127 0x31c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 + VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff + VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 + >; + }; + + pinctrl_sx1503_20: pinctrl-sx1503-20 { + fsl,pins = < + VF610_PAD_PTD31__GPIO_63 0x219d + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts new file mode 100644 index 000000000000..1461804ecaea --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SPB4 board + * + * SPB - Seat Power Box + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SPB4 Board"; + compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 28V_SW */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&wdoga5 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA30__UART3_TX 0x21a2 + VF610_PAD_PTA31__UART3_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts new file mode 100644 index 000000000000..463c2452b9b7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB DTU board + * + * SSMB - SPU3 Switch Management Board + * DTU - Digital Tapping Unit + * + * Copyright (C) 2015-2019 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB DTU Board"; + compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 12V_MAIN */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_100_3"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_4"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_5"; + }; + + port@8 { + reg = <8>; + label = "eth_cu_1000_1"; + }; + + port@9 { + reg = <9>; + label = "eth_cu_1000_2"; + phy-handle = <&phy9>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + + mdio1 { + compatible = "marvell,mv88e6xxx-mdio-external"; + #address-cells = <1>; + #size-cells = <0>; + + phy9: phy9@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + pinctrl-0 = <&pinctrl_gpio_phy9>; + pinctrl-names = "default"; + interrupt-parent = <&gpio2>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* On SSMB */ + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + /* On DSB */ + temperature-sensor@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_phy9: pinctrl-gpio-phy9 { + fsl,pins = < + VF610_PAD_PTB24__GPIO_94 0x219d + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts new file mode 100644 index 000000000000..f5ae0d5de315 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB SPU3 board + * + * SSMB - SPU3 Switch Management Board + * SPU - Seat Power Unit + * + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB SPU3 Board"; + compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 12V_MAIN */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + /* + * Some SPU3s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "rmii"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + + mcu { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&wdoga5 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610.dtsi b/arch/arm/boot/dts/nxp/vf/vf610.dtsi new file mode 100644 index 000000000000..2fba923821d0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2013 Freescale Semiconductor, Inc. + +#include "vf500.dtsi" + +&a5_cpu { + next-level-cache = <&L2>; +}; + +&aips0 { + L2: cache-controller@40006000 { + compatible = "arm,pl310-cache"; + reg = <0x40006000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts new file mode 100644 index 000000000000..2c2db47af441 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Device tree for Colibri VF61 Cortex-M4 support + * + * Copyright (C) 2015 Stefan Agner + */ + +/dts-v1/; +#include "vf610m4.dtsi" + +/ { + model = "VF610 Cortex-M4"; + compatible = "fsl,vf610m4"; + + chosen { + bootargs = "clk_ignore_unused init=/linuxrc rw"; + stdout-path = "serial2:115200"; + }; + + memory@8c000000 { + device_type = "memory"; + reg = <0x8c000000 0x3000000>; + }; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&gpio3 { + status = "disabled"; +}; + +&gpio4 { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&iomuxc { + vf610-colibri { + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts new file mode 100644 index 000000000000..f7474c11aabd --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts @@ -0,0 +1,90 @@ +/* + * Device tree for Cosmic+ VF6xx Cortex-M4 support + * + * Copyright (C) 2015 + * + * Based on vf610m4 Colibri + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "vf610m4.dtsi" + +/ { + model = "VF610 Cortex-M4"; + compatible = "fsl,vf610m4"; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&gpio3 { + status = "disabled"; +}; + +&gpio4 { + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&iomuxc { + vf610-cosmic { + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA20__UART3_TX 0x21a2 + VF610_PAD_PTA21__UART3_RX 0x21a1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi new file mode 100644 index 000000000000..2bb331a87721 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi @@ -0,0 +1,57 @@ +/* + * Device tree for VF6xx Cortex-M4 support + * + * Copyright (C) 2015 Stefan Agner + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "../../armv7-m.dtsi" +#include "vfxxx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; +}; + +&mscm_ir { + interrupt-parent = <&nvic>; +}; diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi new file mode 100644 index 000000000000..3f7dc787938e --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2013 Freescale Semiconductor, Inc. + +#include "vf610-pinfunc.h" +#include +#include +#include + +/ { + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &fec0; + ethernet1 = &fec1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; + }; + + fxosc: fxosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + sxosc: sxosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&src>; + offset = <0x0>; + mask = <0x1000>; + }; + + tempsensor: iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 16>, <&adc1 16>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&mscm_ir>; + ranges; + + aips0: bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x00070000>; + ranges; + + mscm_cpucfg: cpucfg@40001000 { + compatible = "fsl,vf610-mscm-cpucfg", "syscon"; + reg = <0x40001000 0x800>; + }; + + mscm_ir: interrupt-controller@40001800 { + compatible = "fsl,vf610-mscm-ir"; + reg = <0x40001800 0x400>; + fsl,cpucfg = <&mscm_cpucfg>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + edma0: dma-controller@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>, + <0x40024000 0x1000>, + <0x40025000 0x1000>; + dma-channels = <32>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX0>, + <&clks VF610_CLK_DMAMUX1>; + status = "disabled"; + }; + + can0: can@40020000 { + compatible = "fsl,vf610-flexcan"; + reg = <0x40020000 0x4000>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_FLEXCAN0>, + <&clks VF610_CLK_FLEXCAN0>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart0: serial@40027000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40027000 0x1000>; + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_UART0>; + clock-names = "ipg"; + dmas = <&edma0 0 2>, + <&edma0 0 3>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + uart1: serial@40028000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40028000 0x1000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_UART1>; + clock-names = "ipg"; + dmas = <&edma0 0 4>, + <&edma0 0 5>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + uart2: serial@40029000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40029000 0x1000>; + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_UART2>; + clock-names = "ipg"; + dmas = <&edma0 0 6>, + <&edma0 0 7>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + uart3: serial@4002a000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x4002a000 0x1000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_UART3>; + clock-names = "ipg"; + dmas = <&edma0 0 8>, + <&edma0 0 9>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + dspi0: spi@4002c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DSPI0>; + clock-names = "dspi"; + spi-num-chipselects = <6>; + dmas = <&edma1 1 12>, + <&edma1 1 13>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + dspi1: spi@4002d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002d000 0x1000>; + interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DSPI1>; + clock-names = "dspi"; + spi-num-chipselects = <4>; + dmas = <&edma1 1 14>, + <&edma1 1 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai0: sai@4002f000 { + compatible = "fsl,vf610-sai"; + reg = <0x4002f000 0x1000>; + interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_SAI0>, + <&clks VF610_CLK_SAI0_DIV>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 0 16>, <&edma0 0 17>; + status = "disabled"; + }; + + sai1: sai@40030000 { + compatible = "fsl,vf610-sai"; + reg = <0x40030000 0x1000>; + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_SAI1>, + <&clks VF610_CLK_SAI1_DIV>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 0 18>, <&edma0 0 19>; + status = "disabled"; + }; + + sai2: sai@40031000 { + compatible = "fsl,vf610-sai"; + reg = <0x40031000 0x1000>; + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_SAI2>, + <&clks VF610_CLK_SAI2_DIV>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 0 20>, <&edma0 0 21>; + status = "disabled"; + }; + + sai3: sai@40032000 { + compatible = "fsl,vf610-sai"; + reg = <0x40032000 0x1000>; + interrupts = <87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_SAI3>, + <&clks VF610_CLK_SAI3_DIV>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 1 8>, <&edma0 1 9>; + status = "disabled"; + }; + + pit: pit@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; + }; + + pwm0: pwm@40038000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x40038000 0x1000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks VF610_CLK_FTM0>, + <&clks VF610_CLK_FTM0_EXT_SEL>, + <&clks VF610_CLK_FTM0_FIX_SEL>, + <&clks VF610_CLK_FTM0_EXT_FIX_EN>; + status = "disabled"; + }; + + pwm1: pwm@40039000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x40039000 0x1000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks VF610_CLK_FTM1>, + <&clks VF610_CLK_FTM1_EXT_SEL>, + <&clks VF610_CLK_FTM1_FIX_SEL>, + <&clks VF610_CLK_FTM1_EXT_FIX_EN>; + status = "disabled"; + }; + + adc0: adc@4003b000 { + compatible = "fsl,vf610-adc"; + reg = <0x4003b000 0x1000>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_ADC0>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + }; + + tcon0: timing-controller@4003d000 { + compatible = "fsl,vf610-tcon"; + reg = <0x4003d000 0x1000>; + clocks = <&clks VF610_CLK_TCON0>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdoga5: watchdog@4003e000 { + compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; + reg = <0x4003e000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_WDT>; + status = "disabled"; + }; + + qspi0: spi@40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_QSPI0_EN>, + <&clks VF610_CLK_QSPI0>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + iomuxc: iomuxc@40048000 { + compatible = "fsl,vf610-iomuxc"; + reg = <0x40048000 0x1000>; + }; + + gpio0: gpio@40049000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40049000 0x1000 0x400ff000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + + gpio1: gpio@4004a000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004a000 0x1000 0x400ff040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio2: gpio@4004b000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004b000 0x1000 0x400ff080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio3: gpio@4004c000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio4: gpio@4004d000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004d000 0x1000 0x400ff100 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 128 7>; + }; + + anatop: anatop@40050000 { + compatible = "fsl,vf610-anatop", "syscon"; + reg = <0x40050000 0x400>; + }; + + usbphy0: usbphy@40050800 { + compatible = "fsl,vf610-usbphy"; + reg = <0x40050800 0x400>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBPHY0>; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + usbphy1: usbphy@40050c00 { + compatible = "fsl,vf610-usbphy"; + reg = <0x40050c00 0x400>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBPHY1>; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + dcu0: dcu@40058000 { + compatible = "fsl,vf610-dcu"; + reg = <0x40058000 0x1200>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DCU0>, + <&clks VF610_CLK_DCU0_DIV>; + clock-names = "dcu", "pix"; + fsl,tcon = <&tcon0>; + status = "disabled"; + }; + + i2c0: i2c@40066000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40066000 0x1000>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C0>; + clock-names = "ipg"; + dmas = <&edma0 0 50>, + <&edma0 0 51>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + i2c1: i2c@40067000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40067000 0x1000>; + interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C1>; + clock-names = "ipg"; + dmas = <&edma0 0 52>, + <&edma0 0 53>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + clks: ccm@4006b000 { + compatible = "fsl,vf610-ccm"; + reg = <0x4006b000 0x1000>; + clocks = <&sxosc>, <&fxosc>; + clock-names = "sxosc", "fxosc"; + #clock-cells = <1>; + }; + + usbdev0: usb@40034000 { + compatible = "fsl,vf610-usb", "fsl,imx27-usb"; + reg = <0x40034000 0x800>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBC0>; + fsl,usbphy = <&usbphy0>; + fsl,usbmisc = <&usbmisc0 0>; + dr_mode = "peripheral"; + status = "disabled"; + }; + + usbmisc0: usb@40034800 { + #index-cells = <1>; + compatible = "fsl,vf610-usbmisc"; + reg = <0x40034800 0x200>; + clocks = <&clks VF610_CLK_USBC0>; + status = "disabled"; + }; + + src: src@4006e000 { + compatible = "fsl,vf610-src", "syscon"; + reg = <0x4006e000 0x1000>; + interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + aips1: bus@40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40080000 0x0007f000>; + ranges; + + edma1: dma-controller@40098000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40098000 0x2000>, + <0x400a1000 0x1000>, + <0x400a2000 0x1000>; + dma-channels = <32>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX2>, + <&clks VF610_CLK_DMAMUX3>; + status = "disabled"; + }; + + ocotp: ocotp@400a5000 { + compatible = "fsl,vf610-ocotp", "syscon"; + reg = <0x400a5000 0x1000>; + clocks = <&clks VF610_CLK_OCOTP>; + }; + + snvs0: snvs@400a7000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x400a7000 0x2000>; + + snvsrtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs0>; + offset = <0x34>; + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_SNVS>; + clock-names = "snvs-rtc"; + }; + }; + + uart4: serial@400a9000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x400a9000 0x1000>; + interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_UART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart5: serial@400aa000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x400aa000 0x1000>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_UART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + dspi2: spi@400ac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x400ac000 0x1000>; + interrupts = <69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DSPI2>; + clock-names = "dspi"; + spi-num-chipselects = <2>; + dmas = <&edma1 0 10>, + <&edma1 0 11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + dspi3: spi@400ad000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x400ad000 0x1000>; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DSPI3>; + clock-names = "dspi"; + spi-num-chipselects = <2>; + dmas = <&edma1 0 12>, + <&edma1 0 13>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + adc1: adc@400bb000 { + compatible = "fsl,vf610-adc"; + reg = <0x400bb000 0x1000>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_ADC1>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + }; + + esdhc0: esdhc@400b1000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b1000 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC0>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc1: esdhc@400b2000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b2000 0x1000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC1>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + usbh1: usb@400b4000 { + compatible = "fsl,vf610-usb", "fsl,imx27-usb"; + reg = <0x400b4000 0x800>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBC1>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc1: usb@400b4800 { + #index-cells = <1>; + compatible = "fsl,vf610-usbmisc"; + reg = <0x400b4800 0x200>; + clocks = <&clks VF610_CLK_USBC1>; + status = "disabled"; + }; + + ftm: ftm@400b8000 { + compatible = "fsl,ftm-timer"; + reg = <0x400b8000 0x1000 0x400b9000 0x1000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm-evt", "ftm-src", + "ftm-evt-counter-en", "ftm-src-counter-en"; + clocks = <&clks VF610_CLK_FTM2>, + <&clks VF610_CLK_FTM3>, + <&clks VF610_CLK_FTM2_EXT_FIX_EN>, + <&clks VF610_CLK_FTM3_EXT_FIX_EN>; + status = "disabled"; + }; + + qspi1: spi@400c4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_QSPI1_EN>, + <&clks VF610_CLK_QSPI1>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + dac0: dac@400cc000 { + compatible = "fsl,vf610-dac"; + reg = <0x400cc000 1000>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dac"; + clocks = <&clks VF610_CLK_DAC0>; + status = "disabled"; + }; + + dac1: dac@400cd000 { + compatible = "fsl,vf610-dac"; + reg = <0x400cd000 1000>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dac"; + clocks = <&clks VF610_CLK_DAC1>; + status = "disabled"; + }; + + fec0: ethernet@400d0000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d0000 0x1000>; + interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_ENET0>, + <&clks VF610_CLK_ENET0>, + <&clks VF610_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + fec1: ethernet@400d1000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d1000 0x1000>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_ENET1>, + <&clks VF610_CLK_ENET1>, + <&clks VF610_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + can1: can@400d4000 { + compatible = "fsl,vf610-flexcan"; + reg = <0x400d4000 0x4000>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_FLEXCAN1>, + <&clks VF610_CLK_FLEXCAN1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + nfc: nand@400e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-nfc"; + reg = <0x400e0000 0x4000>; + interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_NFC>; + clock-names = "nfc"; + status = "disabled"; + }; + + i2c2: i2c@400e6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e6000 0x1000>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C2>; + clock-names = "ipg"; + dmas = <&edma0 1 36>, + <&edma0 1 37>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + i2c3: i2c@400e7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e7000 0x1000>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C3>; + clock-names = "ipg"; + dmas = <&edma0 1 38>, + <&edma0 1 39>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + crypto: crypto@400f0000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x400f0000 0x9000>; + ranges = <0 0x400f0000 0x9000>; + clocks = <&clks VF610_CLK_CAAM>; + clock-names = "ipg"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi deleted file mode 100644 index 3046ec572632..000000000000 --- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for GPMC connected smsc911x on omaps - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <150>; - gpmc,cs-wr-off-ns = <150>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <140>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <140>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <120>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <75>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi deleted file mode 100644 index bc8961f3690f..000000000000 --- a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for GPMC connected smsc9221 on omaps - * - * Compared to smsc911x, smsc9221 (and others like smsc9217 - * or smsc 9218) has faster timings, leading to higher - * bandwidth. - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221","smsc,lan9115"; - bank-width = <2>; - - gpmc,mux-add-data = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi deleted file mode 100644 index 8adc0ef01f6c..000000000000 --- a/arch/arm/boot/dts/omap-zoom-common.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common features on the Zoom debug board - */ - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ - <7 0 0x2c000000 0x01000000>; - - /* - * Four port TL16CP754C serial port on GPMC, - * they probably share the same GPIO IRQ - * REVISIT: Add timing support from slls644g.pdf - */ - serial@3,0 { - compatible = "ns16550a"; - reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <1>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <155>; - gpmc,cs-wr-off-ns = <155>; - gpmc,adv-on-ns = <15>; - gpmc,adv-rd-off-ns = <40>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <145>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <145>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <145>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <20>; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <45>; - gpmc,wr-access-ns = <145>; - }; - serial@3,1 { - compatible = "ns16550a"; - reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - serial@3,2 { - compatible = "ns16550a"; - reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - serial@3,3 { - compatible = "ns16550a"; - reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - - ethernet@gpmc { - reg = <7 0 0xff>; - interrupt-parent = <&gpio5>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ - }; -}; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi deleted file mode 100644 index afabb36a8ac1..000000000000 --- a/arch/arm/boot/dts/omap2.dtsi +++ /dev/null @@ -1,334 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP2 SoC - * - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &i2c1; - i2c1 = &i2c2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - }; - }; - - pmu { - compatible = "arm,arm1136-pmu"; - interrupts = <3>; - }; - - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap2-mpu"; - ti,hwmods = "mpu"; - }; - }; - - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - aes: aes@480a6000 { - compatible = "ti,omap2-aes"; - ti,hwmods = "aes"; - reg = <0x480a6000 0x50>; - dmas = <&sdma 9 &sdma 10>; - dma-names = "tx", "rx"; - }; - - hdq1w: 1w@480b2000 { - compatible = "ti,omap2420-1w"; - ti,hwmods = "hdq1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - }; - - intc: interrupt-controller@1 { - compatible = "ti,omap2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x480FE000 0x1000>; - }; - - target-module@48056000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x48056000 0x4>, - <0x4805602c 0x4>, - <0x48056028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,syss-mask = <1>; - clocks = <&core_l3_ck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48056000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap2420-sdma", "ti,omap-sdma"; - reg = <0 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <64>; - }; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48070000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <56>; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c2"; - reg = <0x48072000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <57>; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi1"; - reg = <0x48098000 0x100>; - interrupts = <65>; - dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 - &sdma 39 &sdma 40 &sdma 41 &sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi2"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - rng: rng@480a0000 { - compatible = "ti,omap2-rng"; - ti,hwmods = "rng"; - reg = <0x480a0000 0x50>; - interrupts = <52>; - }; - - sham: sham@480a4000 { - compatible = "ti,omap2-sham"; - ti,hwmods = "sham"; - reg = <0x480a4000 0x64>; - interrupts = <51>; - dmas = <&sdma 13>; - dma-names = "rx"; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart1"; - reg = <0x4806a000 0x2000>; - interrupts = <72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart2"; - reg = <0x4806c000 0x400>; - interrupts = <73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - uart3: serial@4806e000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart3"; - reg = <0x4806e000 0x400>; - interrupts = <74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - timer2_target: target-module@4802a000 { - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x4802a000 0x4>, - <0x4802a010 0x4>, - <0x4802a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&gpt2_fck>, <&gpt2_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4802a000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap2420-timer"; - reg = <0 0x400>; - interrupts = <38>; - }; - }; - - timer3: timer@48078000 { - compatible = "ti,omap2420-timer"; - reg = <0x48078000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; - }; - - timer4: timer@4807a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807a000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; - }; - - timer5: timer@4807c000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807c000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4807e000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807e000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@48080000 { - compatible = "ti,omap2420-timer"; - reg = <0x48080000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@48082000 { - compatible = "ti,omap2420-timer"; - reg = <0x48082000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; - ti,timer-dsp; - }; - - timer9: timer@48084000 { - compatible = "ti,omap2420-timer"; - reg = <0x48084000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap2420-timer"; - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap2420-timer"; - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer12: timer@4808a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4808a000 0x400>; - interrupts = <48>; - ti,hwmods = "timer12"; - ti,timer-pwm; - }; - - dss: dss@48050000 { - compatible = "ti,omap2-dss"; - reg = <0x48050000 0x400>; - status = "disabled"; - ti,hwmods = "dss_core"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@48050400 { - compatible = "ti,omap2-dispc"; - reg = <0x48050400 0x400>; - interrupts = <25>; - ti,hwmods = "dss_dispc"; - }; - - rfbi: encoder@48050800 { - compatible = "ti,omap2-rfbi"; - reg = <0x48050800 0x400>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - }; - - venc: encoder@48050c00 { - compatible = "ti,omap2-venc"; - reg = <0x48050c00 0x400>; - status = "disabled"; - ti,hwmods = "dss_venc"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi deleted file mode 100644 index 00a7a199a91c..000000000000 --- a/arch/arm/boot/dts/omap2420-clocks.dtsi +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP2420 clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - */ - -&prcm_clocks { - sys_clkout2_src_gate: sys_clkout2_src_gate@70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <15>; - reg = <0x0070>; - }; - - sys_clkout2_src_mux: sys_clkout2_src_mux@70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; - ti,bit-shift = <8>; - reg = <0x0070>; - }; - - sys_clkout2_src: sys_clkout2_src { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; - }; - - sys_clkout2: sys_clkout2@70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkout2_src>; - ti,bit-shift = <11>; - ti,max-div = <64>; - reg = <0x0070>; - ti,index-power-of-two; - }; - - dsp_gate_ick: dsp_gate_ick@810 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <1>; - reg = <0x0810>; - }; - - dsp_div_ick: dsp_div_ick@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0840>; - ti,index-starts-at-one; - }; - - dsp_ick: dsp_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dsp_gate_ick>, <&dsp_div_ick>; - }; - - iva1_gate_ifck: iva1_gate_ifck@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <10>; - reg = <0x0800>; - }; - - iva1_div_ifck: iva1_div_ifck@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <8>; - reg = <0x0840>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; - }; - - iva1_ifck: iva1_ifck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; - }; - - iva1_ifck_div: iva1_ifck_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&iva1_ifck>; - clock-mult = <1>; - clock-div = <2>; - }; - - iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&iva1_ifck_div>; - ti,bit-shift = <8>; - reg = <0x0800>; - }; - - wdt3_ick: wdt3_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <28>; - reg = <0x0210>; - }; - - wdt3_fck: wdt3_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <28>; - reg = <0x0200>; - }; - - mmc_ick: mmc_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <26>; - reg = <0x0210>; - }; - - mmc_fck: mmc_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <26>; - reg = <0x0200>; - }; - - eac_ick: eac_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <24>; - reg = <0x0210>; - }; - - eac_fck: eac_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <24>; - reg = <0x0200>; - }; - - i2c1_fck: i2c1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <19>; - reg = <0x0200>; - }; - - i2c2_fck: i2c2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <20>; - reg = <0x0200>; - }; - - vlynq_ick: vlynq_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <3>; - reg = <0x0210>; - }; - - vlynq_gate_fck: vlynq_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <3>; - reg = <0x0200>; - }; - - core_d18_ck: core_d18_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <18>; - }; - - vlynq_mux_fck: vlynq_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; - ti,bit-shift = <15>; - reg = <0x0240>; - }; - - vlynq_fck: vlynq_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; - }; -}; - -&prcm_clockdomains { - gfx_clkdm: gfx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_ick>; - }; - - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; - }; - - iva1_clkdm: iva1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&iva1_mpu_int_ifck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_ick>, <&dss_54m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, - <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, - <&uart3_ick>, <&uart3_fck>, <&cam_ick>, - <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, - <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, - <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, - <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, - <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, - <&pka_ick>; - }; -}; - -&func_96m_ck { - compatible = "fixed-factor-clock"; - clocks = <&apll96_ck>; - clock-mult = <1>; - clock-div = <1>; -}; - -&dsp_div_fck { - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; -}; - -&ssi_ssr_sst_div_fck { - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; -}; diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts deleted file mode 100644 index 5acf5dd87c59..000000000000 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap2420.dtsi" - -/ { - model = "TI OMAP2420 H4 board"; - compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; /* 64 MB */ - }; -}; - -&gpmc { - ranges = <0 0 0x08000000 0x04000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name = "intel,ge28f256l18b85"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x04000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <20>; - gpmc,adv-rd-off-ns = <50>; - gpmc,adv-wr-off-ns = <50>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <120>; - gpmc,we-on-ns = <60>; - gpmc,we-off-ns = <120>; - gpmc,rd-cycle-ns = <170>; - gpmc,wr-cycle-ns = <170>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - - partition@0 { - label = "bootloader"; - reg = <0 0x20000>; - }; - partition@20000 { - label = "params"; - reg = <0x20000 0x20000>; - }; - partition@40000 { - label = "kernel"; - reg = <0x40000 0x200000>; - }; - partition@240000 { - label = "file-system"; - reg = <0x240000 0x3dc0000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap2420-n800.dts b/arch/arm/boot/dts/omap2420-n800.dts deleted file mode 100644 index f06d767e818b..000000000000 --- a/arch/arm/boot/dts/omap2420-n800.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N800"; - compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; diff --git a/arch/arm/boot/dts/omap2420-n810-wimax.dts b/arch/arm/boot/dts/omap2420-n810-wimax.dts deleted file mode 100644 index ac9acbd609b6..000000000000 --- a/arch/arm/boot/dts/omap2420-n810-wimax.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N810 WiMax"; - compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts deleted file mode 100644 index 3bf8175d85a8..000000000000 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N810"; - compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; - - vio_ape: vio_ape { - compatible = "regulator-fixed"; - regulator-name = "vio_ape"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - v28_aic: v28_aic { - compatible = "regulator-fixed"; - regulator-name = "v28_aic"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; -}; - -&omap2420_pmx { - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */ - OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */ - OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */ - OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ - >; - }; - - aic33_pins: aic33-pins { - pinctrl-single,pins = < - OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ - OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ - >; - }; -}; - -&i2c2 { - aic33@18 { - compatible = "ti,tlv320aic33"; - reg = <0x18>; - - pinctrl-names = "default"; - pinctrl-0 = <&aic33_pins>; - - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ - - ai3x-gpio-func = < - 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */ - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ - >; - ai3x-micbias-vg = <1>; /* 2V */ - - AVDD-supply = <&v28_aic>; - DRVDD-supply = <&v28_aic>; - IOVDD-supply = <&vio_ape>; - DVDD-supply = <&vio_ape>; - - assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>; - assigned-clock-parents = <&func_96m_ck>; - assigned-clock-rates = <0>, <12000000>; - }; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi deleted file mode 100644 index 63b0b4921e4e..000000000000 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "omap2420.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - ocp { - i2c0 { - compatible = "i2c-cbus-gpio"; - gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */ - &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */ - &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */ - >; - #address-cells = <1>; - #size-cells = <0>; - retu: retu@1 { - compatible = "nokia,retu"; - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - reg = <0x1>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - pmic@72 { - compatible = "menelaus"; - reg = <0x72>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - /* gpio-irq for dma: 26 */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <127>; - gpmc,cs-wr-off-ns = <109>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <27>; - gpmc,oe-off-ns = <127>; - gpmc,we-on-ns = <27>; - gpmc,we-off-ns = <72>; - gpmc,rd-cycle-ns = <145>; - gpmc,wr-cycle-ns = <136>; - gpmc,access-ns = <118>; - gpmc,page-burst-access-ns = <27>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <9>; - gpmc,sync-clk-ps = <27000>; - - /* MTD partition table corresponding to old board-n8x0 file. */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "kernel"; - reg = <0x00080000 0x00200000>; - }; - partition@3 { - label = "initfs"; - reg = <0x00280000 0x00400000>; - }; - partition@4 { - label = "rootfs"; - reg = <0x00680000 0x0f980000>; - }; - partition@5 { - label = "omap2-onenand"; - reg = <0x00000000 0x10000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi deleted file mode 100644 index 821da51cb870..000000000000 --- a/arch/arm/boot/dts/omap2420.dtsi +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP2420 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "omap2.dtsi" - -/ { - compatible = "ti,omap2420", "ti,omap2"; - - ocp { - l4: l4@48000000 { - compatible = "ti,omap2-l4", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x100000>; - - prcm: prcm@8000 { - compatible = "ti,omap2-prcm"; - reg = <0x8000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@0 { - compatible = "ti,omap2-scm", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x0 0x1000>; - - omap2420_pmx: pinmux@30 { - compatible = "ti,omap2420-padconf", - "pinctrl-single"; - reg = <0x30 0x0113>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon"; - reg = <0x270 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; - }; - - target-module@4000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - clocks = <&func_32k_ck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0 0x20>; - }; - }; - }; - - gpio1: gpio@48018000 { - compatible = "ti,omap2-gpio"; - reg = <0x48018000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4801a000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801a000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@4801c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801c000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@4801e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801e000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6800a000 { - compatible = "ti,omap2420-gpmc"; - reg = <0x6800a000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap2420-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <59>, /* TX interrupt */ - <60>; /* RX interrupt */ - interrupt-names = "tx", "rx"; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@48076000 { - compatible = "ti,omap2420-mcbsp"; - reg = <0x48076000 0xff>; - reg-names = "mpu"; - interrupts = <62>, /* TX interrupt */ - <63>; /* RX interrupt */ - interrupt-names = "tx", "rx"; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>, <34>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <6>; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_iva: mbox-iva { - ti,mbox-tx = <2 1 3>; - ti,mbox-rx = <3 1 3>; - }; - }; - - timer1_target: target-module@48028000 { - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x48028000 0x4>, - <0x48028010 0x4>, - <0x48028014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&gpt1_fck>, <&gpt1_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48028000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap2420-timer"; - reg = <0 0x400>; - interrupts = <37>; - ti,timer-alwon; - }; - }; - - wd_timer2: wdt@48022000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x48022000 0x80>; - }; - }; -}; - -&i2c1 { - compatible = "ti,omap2420-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2420-i2c"; -}; - -#include "omap24xx-clocks.dtsi" -#include "omap2420-clocks.dtsi" - -/* Preferred always-on timer for clockevent */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt1_fck>; - assigned-clock-parents = <&func_32k_ck>; - }; -}; diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi deleted file mode 100644 index 4e5ab5189476..000000000000 --- a/arch/arm/boot/dts/omap2430-clocks.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP2430 clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - */ - -&scm_clocks { - mcbsp3_mux_fck: mcbsp3_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - reg = <0x78>; - }; - - mcbsp3_fck: mcbsp3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; - }; - - mcbsp4_mux_fck: mcbsp4_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x78>; - }; - - mcbsp4_fck: mcbsp4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; - }; - - mcbsp5_mux_fck: mcbsp5_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x78>; - }; - - mcbsp5_fck: mcbsp5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; - }; -}; - -&prcm_clocks { - iva2_1_gate_ick: iva2_1_gate_ick@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <0>; - reg = <0x0800>; - }; - - iva2_1_div_ick: iva2_1_div_ick@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0840>; - ti,index-starts-at-one; - }; - - iva2_1_ick: iva2_1_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; - }; - - mdm_gate_ick: mdm_gate_ick@c10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0c10>; - }; - - mdm_div_ick: mdm_div_ick@c40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - reg = <0x0c40>; - ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; - }; - - mdm_ick: mdm_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mdm_gate_ick>, <&mdm_div_ick>; - }; - - mdm_osc_ck: mdm_osc_ck@c00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&osc_ck>; - ti,bit-shift = <1>; - reg = <0x0c00>; - }; - - mcbsp3_ick: mcbsp3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <3>; - reg = <0x0214>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <3>; - reg = <0x0204>; - }; - - mcbsp4_ick: mcbsp4_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x0214>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x0204>; - }; - - mcbsp5_ick: mcbsp5_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <5>; - reg = <0x0214>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <5>; - reg = <0x0204>; - }; - - mcspi3_ick: mcspi3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <9>; - reg = <0x0214>; - }; - - mcspi3_fck: mcspi3_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <9>; - reg = <0x0204>; - }; - - icr_ick: icr_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0410>; - }; - - i2chs1_fck: i2chs1_fck@204 { - #clock-cells = <0>; - compatible = "ti,omap2430-interface-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <19>; - reg = <0x0204>; - }; - - i2chs2_fck: i2chs2_fck@204 { - #clock-cells = <0>; - compatible = "ti,omap2430-interface-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <20>; - reg = <0x0204>; - }; - - usbhs_ick: usbhs_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <6>; - reg = <0x0214>; - }; - - mmchs1_ick: mmchs1_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <7>; - reg = <0x0214>; - }; - - mmchs1_fck: mmchs1_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <7>; - reg = <0x0204>; - }; - - mmchs2_ick: mmchs2_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <8>; - reg = <0x0214>; - }; - - mmchs2_fck: mmchs2_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <8>; - reg = <0x0204>; - }; - - gpio5_ick: gpio5_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <10>; - reg = <0x0214>; - }; - - gpio5_fck: gpio5_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <10>; - reg = <0x0204>; - }; - - mdm_intc_ick: mdm_intc_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <11>; - reg = <0x0214>; - }; - - mmchsdb1_fck: mmchsdb1_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <16>; - reg = <0x0204>; - }; - - mmchsdb2_fck: mmchsdb2_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <17>; - reg = <0x0204>; - }; -}; - -&prcm_clockdomains { - gfx_clkdm: gfx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_ick>; - }; - - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, - <&icr_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_ick>, <&dss_54m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, - <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, - <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, - <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, - <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, - <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, - <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, - <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, - <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, - <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, - <&mmchsdb2_fck>; - }; - - mdm_clkdm: mdm_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mdm_osc_ck>; - }; -}; - -&func_96m_ck { - compatible = "ti,mux-clock"; - clocks = <&apll96_ck>, <&alt_ck>; - ti,bit-shift = <4>; - reg = <0x0540>; -}; - -&dsp_div_fck { - ti,max-div = <4>; - ti,index-starts-at-one; -}; - -&ssi_ssr_sst_div_fck { - ti,max-div = <5>; - ti,index-starts-at-one; -}; diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts deleted file mode 100644 index 207070677e3a..000000000000 --- a/arch/arm/boot/dts/omap2430-sdp.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap2430.dtsi" - -/ { - model = "TI OMAP2430 SDP"; - compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; -}; - -&i2c2 { - clock-frequency = <100000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -#include "twl4030.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -&gpmc { - ranges = <5 0 0x08000000 0x01000000>; - ethernet@gpmc { - compatible = "smsc,lan91c94"; - interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ - reg = <5 0x300 0xf>; - bank-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,mux-add-data = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <187>; - gpmc,cs-wr-off-ns = <187>; - gpmc,adv-on-ns = <18>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <169>; - gpmc,we-on-ns = <66>; - gpmc,we-off-ns = <169>; - gpmc,rd-cycle-ns = <187>; - gpmc,wr-cycle-ns = <187>; - gpmc,access-ns = <187>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <24>; - gpmc,cycle2cycle-delay-ns = <24>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - }; -}; - diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi deleted file mode 100644 index b9a9e6e45266..000000000000 --- a/arch/arm/boot/dts/omap2430.dtsi +++ /dev/null @@ -1,366 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP243x SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "omap2.dtsi" - -/ { - compatible = "ti,omap2430", "ti,omap2"; - - ocp { - l4_wkup: l4_wkup@49000000 { - compatible = "ti,omap2-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x49000000 0x31000>; - - prcm: prcm@6000 { - compatible = "ti,omap2-prcm"; - reg = <0x6000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@2000 { - compatible = "ti,omap2-scm", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x2000 0x1000>; - - omap2430_pmx: pinmux@30 { - compatible = "ti,omap2430-padconf", - "pinctrl-single"; - reg = <0x30 0x0154>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon", - "simple-bus"; - reg = <0x270 0x240>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x270 0x240>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - pbias_regulator: pbias_regulator@230 { - compatible = "ti,pbias-omap2", "ti,pbias-omap"; - reg = <0x230 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - - scm_clockdomains: clockdomains { - }; - }; - - target-module@20000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20000 0x4>, - <0x20004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - clocks = <&func_32k_ck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0 0x20>; - }; - }; - }; - - gpio1: gpio@4900c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900c000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4900e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900e000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@49010000 { - compatible = "ti,omap2-gpio"; - reg = <0x49010000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@49012000 { - compatible = "ti,omap2-gpio"; - reg = <0x49012000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@480b6000 { - compatible = "ti,omap2-gpio"; - reg = <0x480b6000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap2430-gpmc"; - reg = <0x6e000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <64>, /* OCP compliant interrupt */ - <59>, /* TX interrupt */ - <60>, /* RX interrupt */ - <61>; /* RX overflow interrupt */ - interrupt-names = "common", "tx", "rx", "rx_overflow"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@48076000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48076000 0xff>; - reg-names = "mpu"; - interrupts = <16>, /* OCP compliant interrupt */ - <62>, /* TX interrupt */ - <63>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@4808c000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x4808c000 0xff>; - reg-names = "mpu"; - interrupts = <17>, /* OCP compliant interrupt */ - <89>, /* TX interrupt */ - <90>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp4: mcbsp@4808e000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x4808e000 0xff>; - reg-names = "mpu"; - interrupts = <18>, /* OCP compliant interrupt */ - <54>, /* TX interrupt */ - <55>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp5: mcbsp@48096000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48096000 0xff>; - reg-names = "mpu"; - interrupts = <19>, /* OCP compliant interrupt */ - <81>, /* TX interrupt */ - <82>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <6>; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - }; - - timer1_target: target-module@49018000 { - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x49018000 0x4>, - <0x49018010 0x4>, - <0x49018014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&gpt1_fck>, <&gpt1_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49018000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap2420-timer"; - reg = <0 0x400>; - interrupts = <37>; - ti,timer-alwon; - }; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi3"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - usb_otg_hs: usb_otg_hs@480ac000 { - compatible = "ti,omap2-musb"; - ti,hwmods = "usb_otg_hs"; - reg = <0x480ac000 0x1000>; - interrupts = <93>; - }; - - wd_timer2: wdt@49016000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x49016000 0x80>; - }; - }; -}; - -&sdma { - compatible = "ti,omap2430-sdma", "ti,omap-sdma"; -}; - -&i2c1 { - compatible = "ti,omap2430-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2430-i2c"; -}; - -#include "omap24xx-clocks.dtsi" -#include "omap2430-clocks.dtsi" - -/* Preferred always-on timer for clockevent */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt1_fck>; - assigned-clock-parents = <&func_32k_ck>; - }; -}; diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi deleted file mode 100644 index 07af87edf0e2..000000000000 --- a/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ /dev/null @@ -1,1241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP24xx clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - */ -&scm_clocks { - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x4>; - }; - - mcbsp1_fck: mcbsp1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; - }; - - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x4>; - }; - - mcbsp2_fck: mcbsp2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; - }; -}; - -&prcm_clocks { - func_32k_ck: func_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12m_ck: virt_12m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13m_ck: virt_13m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26m_ck: virt_26m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - aplls_clkin_ck: aplls_clkin_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; - ti,bit-shift = <23>; - reg = <0x0540>; - }; - - aplls_clkin_x2_ck: aplls_clkin_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&aplls_clkin_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - osc_ck: osc_ck@60 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; - ti,bit-shift = <6>; - reg = <0x0060>; - ti,index-starts-at-one; - }; - - sys_ck: sys_ck@60 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&osc_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x0060>; - ti,index-starts-at-one; - }; - - alt_ck: alt_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <54000000>; - }; - - mcbsp_clks: mcbsp_clks { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - dpll_ck: dpll_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0500>, <0x0540>; - }; - - apll96_ck: apll96_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - ti,idlest-shift = <8>; - ti,clock-frequency = <96000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; - - apll54_ck: apll54_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - ti,idlest-shift = <9>; - ti,clock-frequency = <54000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; - - func_54m_ck: func_54m_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&apll54_ck>, <&alt_ck>; - ti,bit-shift = <5>; - reg = <0x0540>; - }; - - core_ck: core_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - func_96m_ck: func_96m_ck@540 { - #clock-cells = <0>; - }; - - apll96_d2_ck: apll96_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll96_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_48m_ck: func_48m_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&apll96_d2_ck>, <&alt_ck>; - ti,bit-shift = <3>; - reg = <0x0540>; - }; - - func_12m_ck: func_12m_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&func_48m_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - sys_clkout_src_gate: sys_clkout_src_gate@70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0070>; - }; - - sys_clkout_src_mux: sys_clkout_src_mux@70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; - reg = <0x0070>; - }; - - sys_clkout_src: sys_clkout_src { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; - }; - - sys_clkout: sys_clkout@70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkout_src>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0070>; - ti,index-power-of-two; - }; - - emul_ck: emul_ck@78 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_54m_ck>; - ti,bit-shift = <0>; - reg = <0x0078>; - }; - - mpu_ck: mpu_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <31>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dsp_gate_fck: dsp_gate_fck@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0800>; - }; - - dsp_div_fck: dsp_div_fck@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - reg = <0x0840>; - }; - - dsp_fck: dsp_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dsp_gate_fck>, <&dsp_div_fck>; - }; - - core_l3_ck: core_l3_ck@240 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <31>; - reg = <0x0240>; - ti,index-starts-at-one; - }; - - gfx_3d_gate_fck: gfx_3d_gate_fck@300 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <2>; - reg = <0x0300>; - }; - - gfx_3d_div_fck: gfx_3d_div_fck@340 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,max-div = <4>; - reg = <0x0340>; - ti,index-starts-at-one; - }; - - gfx_3d_fck: gfx_3d_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; - }; - - gfx_2d_gate_fck: gfx_2d_gate_fck@300 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <1>; - reg = <0x0300>; - }; - - gfx_2d_div_fck: gfx_2d_div_fck@340 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,max-div = <4>; - reg = <0x0340>; - ti,index-starts-at-one; - }; - - gfx_2d_fck: gfx_2d_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; - }; - - gfx_ick: gfx_ick@310 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <0>; - reg = <0x0310>; - }; - - l4_ck: l4_ck@240 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0240>; - ti,index-starts-at-one; - }; - - dss_ick: dss_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <0>; - reg = <0x0210>; - }; - - dss1_gate_fck: dss1_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0200>; - }; - - core_d2_ck: core_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - core_d3_ck: core_d3_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - core_d4_ck: core_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - core_d5_ck: core_d5_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <5>; - }; - - core_d6_ck: core_d6_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <6>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - core_d8_ck: core_d8_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - core_d9_ck: core_d9_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <9>; - }; - - core_d12_ck: core_d12_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <12>; - }; - - core_d16_ck: core_d16_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dss1_mux_fck: dss1_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; - ti,bit-shift = <8>; - reg = <0x0240>; - }; - - dss1_fck: dss1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; - }; - - dss2_gate_fck: dss2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <1>; - reg = <0x0200>; - }; - - dss2_mux_fck: dss2_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&func_48m_ck>; - ti,bit-shift = <13>; - reg = <0x0240>; - }; - - dss2_fck: dss2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; - }; - - dss_54m_fck: dss_54m_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_54m_ck>; - ti,bit-shift = <2>; - reg = <0x0200>; - }; - - ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <1>; - reg = <0x0204>; - }; - - ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <20>; - reg = <0x0240>; - }; - - ssi_ssr_sst_fck: ssi_ssr_sst_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@214 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <0>; - reg = <0x0214>; - }; - - usb_l4_div_ick: usb_l4_div_ick@240 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <25>; - reg = <0x0240>; - ti,dividers = <0>, <1>, <2>, <0>, <4>; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - ssi_l4_ick: ssi_l4_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <1>; - reg = <0x0214>; - }; - - gpt1_ick: gpt1_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0410>; - }; - - gpt1_gate_fck: gpt1_gate_fck@400 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <0>; - reg = <0x0400>; - }; - - gpt1_mux_fck: gpt1_mux_fck@440 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - reg = <0x0440>; - }; - - gpt1_fck: gpt1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; - }; - - gpt2_ick: gpt2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x0210>; - }; - - gpt2_gate_fck: gpt2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <4>; - reg = <0x0200>; - }; - - gpt2_mux_fck: gpt2_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <2>; - reg = <0x0244>; - }; - - gpt2_fck: gpt2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; - }; - - gpt3_ick: gpt3_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <5>; - reg = <0x0210>; - }; - - gpt3_gate_fck: gpt3_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <5>; - reg = <0x0200>; - }; - - gpt3_mux_fck: gpt3_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <4>; - reg = <0x0244>; - }; - - gpt3_fck: gpt3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; - }; - - gpt4_ick: gpt4_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <6>; - reg = <0x0210>; - }; - - gpt4_gate_fck: gpt4_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <6>; - reg = <0x0200>; - }; - - gpt4_mux_fck: gpt4_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <6>; - reg = <0x0244>; - }; - - gpt4_fck: gpt4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; - }; - - gpt5_ick: gpt5_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <7>; - reg = <0x0210>; - }; - - gpt5_gate_fck: gpt5_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <7>; - reg = <0x0200>; - }; - - gpt5_mux_fck: gpt5_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <8>; - reg = <0x0244>; - }; - - gpt5_fck: gpt5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; - }; - - gpt6_ick: gpt6_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <8>; - reg = <0x0210>; - }; - - gpt6_gate_fck: gpt6_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0200>; - }; - - gpt6_mux_fck: gpt6_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <10>; - reg = <0x0244>; - }; - - gpt6_fck: gpt6_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; - }; - - gpt7_ick: gpt7_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <9>; - reg = <0x0210>; - }; - - gpt7_gate_fck: gpt7_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <9>; - reg = <0x0200>; - }; - - gpt7_mux_fck: gpt7_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <12>; - reg = <0x0244>; - }; - - gpt7_fck: gpt7_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; - }; - - gpt8_ick: gpt8_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <10>; - reg = <0x0210>; - }; - - gpt8_gate_fck: gpt8_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <10>; - reg = <0x0200>; - }; - - gpt8_mux_fck: gpt8_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <14>; - reg = <0x0244>; - }; - - gpt8_fck: gpt8_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; - }; - - gpt9_ick: gpt9_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <11>; - reg = <0x0210>; - }; - - gpt9_gate_fck: gpt9_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <11>; - reg = <0x0200>; - }; - - gpt9_mux_fck: gpt9_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <16>; - reg = <0x0244>; - }; - - gpt9_fck: gpt9_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; - }; - - gpt10_ick: gpt10_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <12>; - reg = <0x0210>; - }; - - gpt10_gate_fck: gpt10_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <12>; - reg = <0x0200>; - }; - - gpt10_mux_fck: gpt10_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <18>; - reg = <0x0244>; - }; - - gpt10_fck: gpt10_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; - }; - - gpt11_ick: gpt11_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <13>; - reg = <0x0210>; - }; - - gpt11_gate_fck: gpt11_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <13>; - reg = <0x0200>; - }; - - gpt11_mux_fck: gpt11_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <20>; - reg = <0x0244>; - }; - - gpt11_fck: gpt11_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; - }; - - gpt12_ick: gpt12_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <14>; - reg = <0x0210>; - }; - - gpt12_gate_fck: gpt12_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <14>; - reg = <0x0200>; - }; - - gpt12_mux_fck: gpt12_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <22>; - reg = <0x0244>; - }; - - gpt12_fck: gpt12_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; - }; - - mcbsp1_ick: mcbsp1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <15>; - reg = <0x0210>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <15>; - reg = <0x0200>; - }; - - mcbsp2_ick: mcbsp2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <16>; - reg = <0x0210>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <16>; - reg = <0x0200>; - }; - - mcspi1_ick: mcspi1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <17>; - reg = <0x0210>; - }; - - mcspi1_fck: mcspi1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <17>; - reg = <0x0200>; - }; - - mcspi2_ick: mcspi2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <18>; - reg = <0x0210>; - }; - - mcspi2_fck: mcspi2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <18>; - reg = <0x0200>; - }; - - uart1_ick: uart1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <21>; - reg = <0x0210>; - }; - - uart1_fck: uart1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <21>; - reg = <0x0200>; - }; - - uart2_ick: uart2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <22>; - reg = <0x0210>; - }; - - uart2_fck: uart2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <22>; - reg = <0x0200>; - }; - - uart3_ick: uart3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - uart3_fck: uart3_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <2>; - reg = <0x0204>; - }; - - gpios_ick: gpios_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x0410>; - }; - - gpios_fck: gpios_fck@400 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <2>; - reg = <0x0400>; - }; - - mpu_wdt_ick: mpu_wdt_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x0410>; - }; - - mpu_wdt_fck: mpu_wdt_fck@400 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <3>; - reg = <0x0400>; - }; - - sync_32k_ick: sync_32k_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x0410>; - }; - - wdt1_ick: wdt1_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x0410>; - }; - - omapctrl_ick: omapctrl_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x0410>; - }; - - cam_fck: cam_fck@200 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <31>; - reg = <0x0200>; - }; - - cam_ick: cam_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <31>; - reg = <0x0210>; - }; - - mailboxes_ick: mailboxes_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <30>; - reg = <0x0210>; - }; - - wdt4_ick: wdt4_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <29>; - reg = <0x0210>; - }; - - wdt4_fck: wdt4_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <29>; - reg = <0x0200>; - }; - - mspro_ick: mspro_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <27>; - reg = <0x0210>; - }; - - mspro_fck: mspro_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <27>; - reg = <0x0200>; - }; - - fac_ick: fac_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <25>; - reg = <0x0210>; - }; - - fac_fck: fac_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <25>; - reg = <0x0200>; - }; - - hdq_ick: hdq_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <23>; - reg = <0x0210>; - }; - - hdq_fck: hdq_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <23>; - reg = <0x0200>; - }; - - i2c1_ick: i2c1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <19>; - reg = <0x0210>; - }; - - i2c2_ick: i2c2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <20>; - reg = <0x0210>; - }; - - gpmc_fck: gpmc_fck@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <1>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - sdma_fck: sdma_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sdma_ick: sdma_ick@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <0>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - sdrc_ick: sdrc_ick@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <2>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - des_ick: des_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <0>; - reg = <0x021c>; - }; - - sha_ick: sha_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <1>; - reg = <0x021c>; - }; - - rng_ick: rng_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; - - aes_ick: aes_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <3>; - reg = <0x021c>; - }; - - pka_ick: pka_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x021c>; - }; - - usb_fck: usb_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <0>; - reg = <0x0204>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-beagle-ab4.dts b/arch/arm/boot/dts/omap3-beagle-ab4.dts deleted file mode 100644 index 990ff2d84686..000000000000 --- a/arch/arm/boot/dts/omap3-beagle-ab4.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "omap3-beagle.dts" - -/ { - model = "TI OMAP3 BeagleBoard A to B4"; - compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; -}; - -/* - * Workaround for capacitor C70 issue, see "Boards revision A and < B5" - * section at https://elinux.org/BeagleBoard_Community - */ - -/* Unusable as clocksource because of unreliable oscillator */ -&counter32k { - status = "disabled"; -}; - -/* Unusable as clockevent because of unreliable oscillator, allow to idle */ -&timer1_target { - /delete-property/ti,no-reset-on-init; - /delete-property/ti,no-idle; - timer@0 { - /delete-property/ti,timer-alwon; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer12_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - /* Always clocked by secure_32k_fck */ - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt2_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts b/arch/arm/boot/dts/omap3-beagle-xm-ab.dts deleted file mode 100644 index cb6968a8bce8..000000000000 --- a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "omap3-beagle-xm.dts" - -/ { - /* HS USB Port 2 Power enable was inverted with the xM C */ - hsusb2_power: hsusb2_power_reg { - enable-active-high; - }; -}; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts deleted file mode 100644 index 08ee0f8ea68f..000000000000 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ /dev/null @@ -1,419 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard xM"; - compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &dvi0; - display1 = &tv0; - ethernet = ðernet; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - led-controller-1 { - compatible = "gpio-leds"; - - led-1 { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - led-controller-2 { - compatible = "pwm-leds"; - - led-3 { - label = "beagleboard::pmu_stat"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - linux,code = <0x114>; - wakeup-source; - }; - - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; - - /* XXX pinctrl from twl */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - etb@5401b000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x5401b000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&etm_out>; - }; - }; - }; - }; - - etm@54010000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x54010000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - out-ports { - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: gpio1-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - - dss_dpi_pins2: dss-dpi1-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ - >; - }; - - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - dss_dpi_pins1: dss-dpi2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - - twl_power: power { - compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,9514"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mcbsp2 { - status = "okay"; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts deleted file mode 100644 index 4d9a8eab6abf..000000000000 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ /dev/null @@ -1,436 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - leds { - compatible = "gpio-leds"; - led-pmu-stat { - label = "beagleboard::pmu_stat"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - }; - - led-heartbeat { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - led-mmc { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,code = <0x114>; - wakeup-source; - }; - - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - etb@540000000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x5401b000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&etm_out>; - }; - }; - }; - }; - - etm@54010000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x54010000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - out-ports { - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: gpio1-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - tfp410_pins: tfp410-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mcbsp2 { - status = "okay"; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&gpmc { - status = "okay"; - ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ - - /* Chip select 0 */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* NAND I/O window, 4 bytes */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "ham1"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <16>; - #address-cells = <1>; - #size-cells = <1>; - - gpmc,device-width = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - partition@1c0000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0xf980000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts deleted file mode 100644 index f776e0527049..000000000000 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T3517 - */ -/dts-v1/; - -#include "am3517.dtsi" -#include "omap3-cm-t3x.dtsi" - -/ { - model = "CompuLab CM-T3517"; - compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vw1271"; - pinctrl-names = "default"; - pinctrl-0 = < - &wl12xx_wkup_pins - &wl12xx_core_pins - >; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ - startup-delay-us = <20000>; - enable-active-high; - }; - - wl12xx_vaux2: wl12xx_vaux2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271_vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&omap3_pmx_wkup { - - wl12xx_wkup_pins: wl12xx-wkup-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ - >; - }; -}; - -&omap3_pmx_core { - - phy1_reset_pins: hsusb1-phy-reset-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ - >; - }; - - phy2_reset_pins: hsusb2-phy-reset-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ - >; - }; - - otg_drv_vbus: otg-drv-vbus-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - wl12xx_core_pins: wl12xx-core-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ - OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - usb_hub_pins: usb-hub-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ - >; - }; -}; - -&hsusb1_phy { - pinctrl-names = "default"; - pinctrl-0 = <&phy1_reset_pins>; - reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&phy2_reset_pins>; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&am35x_otg_hs { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv_vbus>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - vqmmc-supply = <&wl12xx_vaux2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */ - ref-clock-frequency = <38400000>; - }; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t35x - >; -}; - diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts deleted file mode 100644 index 0c6f14963e5e..000000000000 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T3530 - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-cm-t3x30.dtsi" - -/ { - model = "CompuLab CM-T3530"; - compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; - - /* Regulator to trigger the reset signal of the Wifi module */ - mmc2_sdio_reset: regulator-mmc2-sdio-reset { - compatible = "regulator-fixed"; - regulator-name = "regulator-mmc2-sdio-reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&mmc2_sdio_reset>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t35x - >; -}; - diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts deleted file mode 100644 index f1a8f0fd7a83..000000000000 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T3730 - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-cm-t3x30.dtsi" - -/ { - model = "CompuLab CM-T3730"; - compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3"; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vw1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ - startup-delay-us = <20000>; - enable-active-high; - }; - - wl12xx_vaux2: wl12xx_vaux2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271_vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vaux2>; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins_cm_t3730: dss-dpi-cm-t3730-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core { - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - vqmmc-supply = <&wl12xx_vaux2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ - ref-clock-frequency = <38400000>; - }; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t3730 - >; -}; - diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi deleted file mode 100644 index f6cd7a3aef1f..000000000000 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for CompuLab CM-T3x CoMs - */ - -/ { - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&green_led_pins>; - ledb { - label = "cm-t3x:green"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ - linux,default-trigger = "heartbeat"; - }; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&hsusb1_power>; - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - tv0: svideo-connector { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; -}; - -&omap3_pmx_core { - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - green_led_pins: green-led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ - >; - }; - - dss_dpi_pins_common: dss-dpi-common-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - dss_dpi_pins_cm_t35x: dss-dpi-cm-t35x-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - >; - }; - - ads7846_pins: ads7846-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; - - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; -}; - -&mmc3 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy &hsusb2_phy>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio2>; - interrupts = <25 0>; /* gpio_57 */ - pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&venc { - status = "okay"; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&mcbsp2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <8>; - gpmc,device-width = <1>; - ti,nand-ecc-opt = "sw"; - - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <120>; - gpmc,cs-wr-off-ns = <120>; - - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <120>; - gpmc,adv-wr-off-ns = <120>; - - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <90>; - - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <90>; - - gpmc,page-burst-access-ns = <6>; - gpmc,access-ns = <72>; - gpmc,cycle2cycle-delay-ns = <60>; - - gpmc,rd-cycle-ns = <120>; - gpmc,wr-cycle-ns = <120>; - gpmc,wr-access-ns = <186>; - gpmc,wr-data-mux-bus-ns = <90>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xloader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "uboot"; - reg = <0x80000 0x1e0000>; - }; - partition@260000 { - label = "uboot environment"; - reg = <0x260000 0x40000>; - }; - partition@2a0000 { - label = "linux"; - reg = <0x2a0000 0x400000>; - }; - partition@6a0000 { - label = "rootfs"; - reg = <0x6a0000 0x1f880000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi deleted file mode 100644 index 0e942513560d..000000000000 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for CompuLab CM-T3x30 CoMs - */ - -#include "omap3-cm-t3x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "cm-t35"; - - ti,mcbsp = <&mcbsp2>; - }; -}; - -&omap3_pmx_core { - - smsc1_pins: smsc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ - >; - }; - - hsusb0_pins: hsusb0-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; -}; - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ - - smsc1: ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc1_pins>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - reg = <5 0 0xff>; - }; -}; - -&i2c1 { - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include - -&venc { - vdda-supply = <&vdac>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(0) */ - ti,pullups = <0x000001>; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(0x00, 0x01, KEY_A) - MATRIX_KEY(0x00, 0x02, KEY_B) - MATRIX_KEY(0x00, 0x03, KEY_LEFT) - - MATRIX_KEY(0x01, 0x01, KEY_UP) - MATRIX_KEY(0x01, 0x02, KEY_ENTER) - MATRIX_KEY(0x01, 0x03, KEY_DOWN) - - MATRIX_KEY(0x02, 0x01, KEY_RIGHT) - MATRIX_KEY(0x02, 0x02, KEY_C) - MATRIX_KEY(0x02, 0x03, KEY_D) - >; -}; - -&hsusb1_phy { - reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; -}; - -&hsusb2_phy { - reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb0_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi deleted file mode 100644 index 0da759f8e2c2..000000000000 --- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 SoC CPU thermal - * - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include - -cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - coefficients = <0 20000>; - - /* sensor ID */ - thermal-sensors = <&bandgap 0>; - - cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi deleted file mode 100644 index 3b9838f1bb6b..000000000000 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ /dev/null @@ -1,392 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anil Kumar - */ - -#include - -#include "omap34xx.dtsi" -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led-heartbeat { - label = "devkit8000::led1"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-mmc { - label = "devkit8000::led2"; - gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ - default-state = "on"; - linux,default-trigger = "none"; - }; - - led-usr { - label = "devkit8000::led3"; - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ - default-state = "on"; - linux,default-trigger = "usr"; - }; - - led-pmu-stat { - label = "devkit8000::pmu_stat"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "devkit8000"; - - ti,mcbsp = <&mcbsp2>; - ti,audio-routing = - "Ext Spk", "PREDRIVEL", - "Ext Spk", "PREDRIVER", - "MAINMIC", "Main Mic", - "Main Mic", "Mic Bias 1"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_dvi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c2>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - status = "disabled"; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -/* Unusable as clockevent because if unreliable oscillator, allow to idle */ -&timer1_target { - /delete-property/ti,no-reset-on-init; - /delete-property/ti,no-idle; - timer@0 { - /delete-property/ti,timer-alwon; - }; -}; - -/* Preferred timer for clockevent */ -&timer12_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - /* Always clocked by secure_32k_fck */ - }; -}; - -&twl_gpio { - ti,use-leds; - /* - * pulldowns: - * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c6>; -}; - -&twl_keypad { - linux,keymap = ; -}; - -&wdt2 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; - - ethernet@6,0 { - compatible = "davicom,dm9000"; - reg = <6 0x000 2 - 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ - bank-width = <2>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - davicom,no-eeprom; - - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <0>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - }; -}; - -&omap3_pmx_core { - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&vpll1 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - vdds_dsi-supply = <&vpll1>; - vdda_dac-supply = <&vdac>; - - port { - #address-cells = <1>; - #size-cells = <0>; - dpi_dvi_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - - endpoint@1 { - reg = <1>; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi deleted file mode 100644 index 3decc2d78a6c..000000000000 --- a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ - -#include "omap3-devkit8000-common.dtsi" -/ { - aliases { - display0 = &lcd0; - display1 = &dvi0; - display2 = &tv0; - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "lcd"; - - enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; -}; - -&dss { - port { - #address-cells = <1>; - #size-cells = <0>; - dpi_lcd_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&vio { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcspi2 { - - /* touch controller */ - ads7846@0 { - compatible = "ti,ads7846"; - vcc-supply = <&vio>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <27 0>; /* gpio_27 */ - pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - ti,debounce-max = /bits/ 16 <10>; - ti,debounce-tol = /bits/ 16 <5>; - ti,debounce-rep = /bits/ 16 <1>; - ti,keep-vref-on = <1>; - ti,settle-delay-usec = /bits/ 16 <150>; - - wakeup-source; - }; -}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts deleted file mode 100644 index afed85078ad8..000000000000 --- a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ -/dts-v1/; - -/* - * 4.3'' LCD panel sold with devkit8000 board - */ - -#include "omap3-devkit8000-lcd-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; - - lcd0: display { - panel-timing { - clock-frequency = <10164705>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <2>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts deleted file mode 100644 index 07c51a105c0d..000000000000 --- a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ -/dts-v1/; - -/* - * 7.0'' LCD panel sold with some devkit8000 board - */ - -#include "omap3-devkit8000-lcd-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; - - lcd0: display { - panel-timing { - clock-frequency = <40000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <1>; - hback-porch = <1>; - hsync-len = <48>; - vback-porch = <25>; - vfront-porch = <12>; - vsync-len = <3>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts deleted file mode 100644 index 162d0726b008..000000000000 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ -/dts-v1/; - -#include "omap3-devkit8000-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000"; - compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; - - aliases { - display1 = &dvi0; - display2 = &tv0; - }; -}; diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/omap3-echo.dts deleted file mode 100644 index 263e517944dd..000000000000 --- a/arch/arm/boot/dts/omap3-echo.dts +++ /dev/null @@ -1,724 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2019 André Hentschel - */ -/dts-v1/; - -#include "dm3725.dtsi" - -#include -#include - -/ { - model = "Amazon Echo (first generation)"; - compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0xc600000>; /* 198 MB */ - }; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc1v8: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <40>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - - mute-button { - label = "mute"; - linux,code = ; - gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */ - wakeup-source; - }; - - help-button { - label = "help"; - linux,code = ; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */ - wakeup-source; - }; - }; - - rotary: rotary-encoder { - compatible = "rotary-encoder"; - gpios = < - &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */ - &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */ - >; - linux,axis = ; - rotary-encoder,relative-axis; - }; - - speaker_amp: speaker-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* gpio_129 */ - sound-name-prefix = "Speaker Amp"; - VCC-supply = <&vcc1v8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Misto Speaker"; - simple-audio-card,widgets = - "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker Amp INL", "HPL", - "Speaker Amp INR", "HPR", - "Speaker", "Speaker Amp OUTL", - "Speaker", "Speaker Amp OUTR"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,aux-devs = <&speaker_amp>; - - simple-audio-card,cpu { - sound-dai = <&mcbsp2>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&codec0>; - system-clock-frequency = <19200000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&mcbsp2 { - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&i2c2 { - clock-frequency = <400000>; - - lp5523A: lp5523A@32 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "national,lp5523"; - label = "q1"; - reg = <0x32>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - color = ; - - led@0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x0>; - color = ; - }; - - led@1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x1>; - color = ; - }; - - led@6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x6>; - color = ; - }; - }; - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - color = ; - - led@2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x2>; - color = ; - }; - - led@3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x3>; - color = ; - }; - - led@7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x7>; - color = ; - }; - }; - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - color = ; - - led@4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x4>; - color = ; - }; - - led@5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x5>; - color = ; - }; - - led@8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x8>; - color = ; - }; - }; - }; - - lp5523B: lp5523B@33 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "national,lp5523"; - label = "q3"; - reg = <0x33>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - color = ; - - led@0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x0>; - color = ; - }; - - led@1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x1>; - color = ; - }; - - led@6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x6>; - color = ; - }; - }; - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - color = ; - - led@2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x2>; - color = ; - }; - - led@3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x3>; - color = ; - }; - - led@7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x7>; - color = ; - }; - }; - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - color = ; - - led@4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x4>; - color = ; - }; - - led@5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x5>; - color = ; - }; - - led@8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x8>; - color = ; - }; - }; - }; - - lp5523C: lp5523C@34 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "national,lp5523"; - label = "q4"; - reg = <0x34>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - color = ; - - led@0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x0>; - color = ; - }; - - led@1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x1>; - color = ; - }; - - led@6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x6>; - color = ; - }; - }; - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - color = ; - - led@2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x2>; - color = ; - }; - - led@3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x3>; - color = ; - }; - - led@7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x7>; - color = ; - }; - }; - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - color = ; - - led@4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x4>; - color = ; - }; - - led@5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x5>; - color = ; - }; - - led@8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x8>; - color = ; - }; - }; - }; - - lp5523D: lp552D@35 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "national,lp5523"; - label = "q2"; - reg = <0x35>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - color = ; - - led@0 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x0>; - color = ; - }; - - led@1 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x1>; - color = ; - }; - - led@6 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x6>; - color = ; - }; - }; - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - color = ; - - led@2 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x2>; - color = ; - }; - - led@3 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x3>; - color = ; - }; - - led@7 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x7>; - color = ; - }; - }; - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - color = ; - - led@4 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x4>; - color = ; - }; - - led@5 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x5>; - color = ; - }; - - led@8 { - led-cur = /bits/ 8 <12>; - max-cur = /bits/ 8 <15>; - reg = <0x8>; - color = ; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - - codec0: codec@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&sys_clkout1>; - clock-names = "mclk"; - ldoin-supply = <&vcc1v8>; - iov-supply = <&vcc1v8>; - reset-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; /* gpio_74 */ - }; -}; - - -#include "tps65910.dtsi" - -&omap3_pmx_core { - tps_pins: tps-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* dss_data4.gpio_74 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data15.gpio_85 */ - OMAP3_CORE1_IOPAD(0x2a1a, PIN_OUTPUT | MUX_MODE0) /* sys_clkout1.sys_clkout1 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; -}; - -&mmc1 { - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc_reg>; -}; - -&mmc2 { - status = "okay"; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmc_reg>; -}; - -&mmc3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - non-removable; - disable-wp; - mmc-pwrseq = <&sdio_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; - atheros@0 { - compatible = "atheros,ath6kl"; - reg = <0>; - bus-width = <4>; - }; -}; - -&tps { - pinctrl-names = "default"; - pinctrl-0 = <&tps_pins>; - - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - ti,en-ck32k-xtal; - ti,system-power-controller; - - vcc1-supply = <&vcc5v>; - vcc2-supply = <&vcc5v>; - vcc3-supply = <&vcc5v>; - vcc4-supply = <&vcc5v>; - vcc5-supply = <&vcc5v>; - vcc6-supply = <&vcc5v>; - vcc7-supply = <&vcc5v>; - vccio-supply = <&vcc5v>; - - regulators { - - vio_reg: regulator@1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd_dsp"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts deleted file mode 100644 index e0346bf842fc..000000000000 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-evm-common.dtsi" -#include "omap3-evm-processor-common.dtsi" - -/ { - model = "TI OMAP37XX EVM (TMDSEVM3730)"; - compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - - ehci_phy_pins: ehci-phy-pins { - pinctrl-single,pins = < - - /* EHCI PHY reset GPIO etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) - - /* EHCI VBUS etk_d8.gpio_22 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - - /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) - - /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) - - /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d15.hsusb2_data1 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "hynix,h8kds0un0mer-4em"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0x1f880000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi deleted file mode 100644 index 1b6023c4cdf3..000000000000 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for omap3 EVM boards - */ - -#include -#include "omap-gpmc-smsc911x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - ledb { - label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - linux,default-trigger = "default-on"; - }; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&lcd_3v3 { - gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ -}; - -&lcd0 { - enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ - reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ - mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ - &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ - &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio6>; - interrupts = <15 0>; /* gpio175 */ - pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - /* gpio_149 with uart1_rts pad as wakeirq */ - interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, - <&omap3_pmx_core 0x14e>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <38400000>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(2, 2, KEY_1) - MATRIX_KEY(1, 1, KEY_2) - MATRIX_KEY(0, 0, KEY_3) - MATRIX_KEY(3, 2, KEY_4) - MATRIX_KEY(2, 1, KEY_5) - MATRIX_KEY(1, 0, KEY_6) - MATRIX_KEY(1, 3, KEY_7) - MATRIX_KEY(3, 1, KEY_8) - MATRIX_KEY(2, 0, KEY_9) - MATRIX_KEY(2, 3, KEY_KPASTERISK) - MATRIX_KEY(0, 2, KEY_0) - MATRIX_KEY(3, 0, KEY_KPDOT) - /* s4 not wired */ - MATRIX_KEY(1, 2, KEY_BACKSPACE) - MATRIX_KEY(0, 1, KEY_ENTER) - >; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ethernet@gpmc { - interrupt-parent = <&gpio6>; - interrupts = <16 8>; - reg = <5 0 0xff>; - }; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi deleted file mode 100644 index e27837093e43..000000000000 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Common support for omap3 EVM 35xx/37xx processor modules - */ - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&dss { - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&lcd_3v3>; - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&ehci_phy_pins>; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - - dss_dpi_pins1: dss-dpi2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: ehci-port-select-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - - /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; - - /* - * Note that gpio_150 pulled high with internal pull to prevent wlcore - * reset on return from off mode in idle. - */ - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: smsc911x-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins2: dss-dpi1-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -/* - * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface - * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. - */ -&gpio2 { - en-usb2-port-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ - output-low; - line-name = "enable usb2 port"; - }; -}; - -/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ -&twl_gpio { - en_on_board_gpio_61 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "en_hsusb2_clk"; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts deleted file mode 100644 index a2a1613c45c3..000000000000 --- a/arch/arm/boot/dts/omap3-evm.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-evm-common.dtsi" -#include "omap3-evm-processor-common.dtsi" - -/ { - model = "TI OMAP35XX EVM (TMDSEVM3530)"; - compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - - ehci_phy_pins: ehci-phy-pins { - pinctrl-single,pins = < - - /* EHCI PHY reset GPIO etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) - - /* EHCI VBUS etk_d8.gpio_22 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - - /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) - - /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) - - /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d15.hsusb2_data1 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f2g16abdhc"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi deleted file mode 100644 index b6b27e93857f..000000000000 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ /dev/null @@ -1,893 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Marek Belisko - * - * Based on omap3-beagle-xm.dts - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include - -/ { - model = "OMAP3 GTA04"; - compatible = "goldelico,gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &lcd; - display1 = &tv0; - /delete-property/ mmc2; - /delete-property/ mmc3; - }; - - ldo_3v3: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "ldo_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - aux-button { - label = "aux"; - linux,code = ; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - }; - - antenna-detect { - compatible = "gpio-keys"; - - gps_antenna_button: gps-antenna-button { - label = "GPS_EXT_ANT"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* GPIO144 */ - interrupt-parent = <&gpio5>; - interrupts = <16 IRQ_TYPE_EDGE_BOTH>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "gta04"; - - ti,mcbsp = <&mcbsp2>; - }; - - /* GSM audio */ - sound_telephony { - compatible = "simple-audio-card"; - simple-audio-card,name = "GTA04 voice"; - simple-audio-card,bitclock-master = <&telephony_link_master>; - simple-audio-card,frame-master = <&telephony_link_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-inversion; - simple-audio-card,cpu { - sound-dai = <&mcbsp4>; - }; - - telephony_link_master: simple-audio-card,codec { - sound-dai = <>m601_codec>; - }; - }; - - gtm601_codec: gsm_codec { - compatible = "option,gtm601"; - #sound-dai-cells = <0>; - }; - - spi_lcd: spi { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_pins>; - - sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - /* lcd panel */ - lcd: td028ttec1@0 { - compatible = "tpo,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - backlight = <&backlight>; - label = "lcd"; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm11 0 12000000 0>; - pwm-names = "backlight"; - brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <9>; /* => 90 */ - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - }; - - pwm11: pwm-11 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer11>; - #pwm-cells = <3>; - ti,clock-source = <0x01>; - }; - - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - #phy-cells = <0>; - }; - - tv0: connector { - compatible = "composite-video-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&opa_out>; - }; - }; - }; - - tv_amp: opa362 { - compatible = "ti,opa362"; - enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; /* GPIO_23 to enable video out amplifier */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - opa_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - - port@1 { - reg = <1>; - opa_out: endpoint { - remote-endpoint = <&tv_connector_in>; - }; - }; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ - }; - - /* devconf0 setup for mcbsp1 clock pins */ - pinmux@48002274 { - compatible = "pinctrl-single"; - reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7>; /* MCBSP1 CLK pinmux */ - #pinctrl-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_devconf0_pins>; - mcbsp1_devconf0_pins: mcbsp1-devconf0-pins { - /* offset bits mask */ - pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ - }; - }; - - /* devconf1 setup for tvout pins */ - pinmux@480022d8 { - compatible = "pinctrl-single"; - reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x81>; /* TV out pin control */ - #pinctrl-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&tv_acbias_devconf1_pins>; - tv_acbias_devconf1_pins: tv-acbias-devconf1-pins { - /* offset bits mask */ - pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: gpio1-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - backlight_pins: backlight-pinmux-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - gps_pins: gps-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ - >; - }; - - hdq_pins: hdq-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ - >; - }; - - bmp085_pins: bmp085-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ - >; - }; - - bma180_pins: bma180-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ - >; - }; - - itg3200_pins: itg3200-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ - >; - }; - - hmc5843_pins: hmc5843-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ - >; - }; - - penirq_pins: penirq-pins { - pinctrl-single,pins = < - /* here we could enable to wakeup the cpu from suspend by a pen touch */ - OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ - >; - }; - - camera_pins: camera-pins { - pinctrl-single,pins = < - /* set up parallel camera interface */ - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_pclk */ - OMAP3_CORE1_IOPAD(0x2114, PIN_OUTPUT | MUX_MODE4) /* cam_fld = gpio_98 */ - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d7 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d8 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d9 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE0) /* cam_xclkb */ - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* cam_wen = gpio_167 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */ - >; - }; - - mcbsp1_pins: mcbsp1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ - /* mcbsp_clks is used as PENIRQ */ - /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) mcbsp_clks.mcbsp_clks */ - OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dx */ - >; - }; - - mcbsp3_pins: mcbsp3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ - OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ - OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_clkx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_fsx */ - >; - }; - - mcbsp4_pins: mcbsp4-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ - OMAP3_CORE1_IOPAD(0x218a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_dx.mcbsp4_fsx */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - spi_gpio_pins: spi-gpio-pinmux-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - codec { - ti,ramp_delay_value = <3>; - }; - }; - - twl_power: power { - compatible = "ti,twl4030-power-idle"; - ti,system-power-controller; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; - - /* pressure sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - pinctrl-names = "default"; - pinctrl-0 = <&bmp085_pins>; - interrupt-parent = <&gpio4>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */ - vdda-supply = <&vio>; - vddd-supply = <&vio>; - }; - - /* accelerometer */ - bma180@41 { - compatible = "bosch,bma180"; - reg = <0x41>; - pinctrl-names = "default"; - pinctrl-0 = <&bma180_pins>; - interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ - }; - - /* gyroscope */ - itg3200@68 { - compatible = "invensense,itg3200"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&itg3200_pins>; - interrupt-parent = <&gpio2>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ - }; - - /* leds + gpios */ - tca6507: tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gpio-controller; - #gpio-cells = <2>; - - gta04_led0: led@0 { - label = "gta04:red:aux"; - reg = <0x0>; - }; - - gta04_led1: led@1 { - label = "gta04:green:aux"; - reg = <0x1>; - }; - - gta04_led3: led@3 { - label = "gta04:red:power"; - reg = <0x3>; - linux,default-trigger = "default-on"; - }; - - gta04_led4: led@4 { - label = "gta04:green:power"; - reg = <0x4>; - }; - - wifi_reset: led@6 { - /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */ - reg = <0x6>; - compatible = "gpio"; - }; - }; - - /* compass aka magnetometer */ - hmc5843@1e { - compatible = "honeywell,hmc5883l"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&hmc5843_pins>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ - }; - - /* touchscreen */ - tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&penirq_pins>; - interrupt-parent = <&gpio6>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ - gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* GPIO_160 */ - ti,x-plate-ohms = <600>; - touchscreen-size-x = <480>; - touchscreen-size-y = <640>; - touchscreen-max-pressure = <1000>; - touchscreen-fuzz-x = <3>; - touchscreen-fuzz-y = <8>; - touchscreen-fuzz-pressure = <10>; - touchscreen-inverted-y; - }; - - /* RFID EEPROM */ - m24lr64@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&mcspi1 { - status = "disabled"; -}; - -&mcspi2 { - status = "disabled"; -}; - -&mcspi3 { - status = "disabled"; -}; - -&mcspi4 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - ti,non-removable; - broken-cd; /* hardware has no CD */ -}; - -&mmc2 { - vmmc-supply = <&vaux4>; - bus-width = <4>; - ti,non-removable; - cap-power-off-card; - mmc-pwrseq = <&wifi_pwrseq>; -}; - -&mmc3 { - status = "disabled"; -}; - -#define BIT(x) (1 << (x)) -&twl_gpio { - /* pullups: BIT(2) */ - ti,pullups = ; - /* - * pulldowns: - * BIT(0), BIT(1), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | - BIT(13) | BIT(15) | BIT(16) | BIT(17))>; -}; - -&twl_keypad { - status = "disabled"; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - gnss: gnss { - compatible = "wi2wi,w2sg0004"; - pinctrl-names = "default"; - pinctrl-0 = <&gps_pins>; - sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - lna-supply = <&vsim>; - vcc-supply = <&ldo_3v3>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -/* spare */ -&vaux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; -}; - -/* sensors */ -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; /* we should never switch off while vio is on! */ -}; - -/* camera */ -&vaux3 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; -}; - -/* WLAN/BT */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* GPS LNA */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* Needed to power the DPI pins */ - -&vpll2 { - regulator-always-on; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "okay"; - vdds_dsi-supply = <&vpll2>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&opa_in>; - ti,channels = <1>; - ti,invert-polarity; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "ham1"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <16>; - #address-cells = <1>; - #size-cells = <1>; - - gpmc,device-width = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,oe-off-ns = <54>; - gpmc,we-off-ns = <40>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,sync-clk-ps = <0>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - - bootloaders_env@240000 { - label = "U-Boot Env"; - reg = <0x240000 0x40000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x600000>; - }; - - filesystem@880000 { - label = "File System"; - reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&mcbsp1 { /* FM Transceiver PCM */ - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; -}; - -&mcbsp2 { /* TPS65950 I2S */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&mcbsp3 { /* Bluetooth PCM */ - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; -}; - -&mcbsp4 { /* GSM voice PCM */ - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp4_pins>; -}; - -&hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - -/* image signal processor within OMAP3 SoC */ -&isp { - ports { - port@0 { - reg = <0>; - parallel_ep: endpoint { - ti,isp-clock-divisor = <1>; - ti,strobe-mode; - bus-width = <8>;/* Used data lines */ - data-shift = <2>; /* Lines 9:2 are used */ - hsync-active = <0>; /* Active low */ - vsync-active = <1>; /* Active high */ - data-active = <1>;/* Active high */ - pclk-sample = <1>;/* Falling */ - }; - }; - /* port@1 and port@2 are not used by GTA04 */ - }; -}; diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts deleted file mode 100644 index bfae1a9ceeac..000000000000 --- a/arch/arm/boot/dts/omap3-gta04a3.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 H. Nikolaus Schaller - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A3/Letux 2804"; -}; - -&i2c2 { - - /* alternate accelerometer that might be installed on some GTA04A3 boards */ - lis302@1d { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x1d>; - interrupt-parent = <&gpio3>; - interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - Vdd-supply = <&vaux2>; - Vdd_IO-supply = <&vaux2>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <8>; - st,click-thresh-y = <8>; - st,click-thresh-z = <10>; - st,click-click-time-limit = <9>; - st,click-latency = <50>; - st,irq1-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <32>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - st,max-limit-x = <3>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts deleted file mode 100644 index f1cf24d55e6f..000000000000 --- a/arch/arm/boot/dts/omap3-gta04a4.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Marek Belisko - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A4/Letux 2804"; -}; diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts deleted file mode 100644 index 8bd6b4b1f30b..000000000000 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-18 H. Nikolaus Schaller - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A5/Letux 2804"; - - sound { - ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; /* GTA04A5 only */ - }; - - wlan_en: wlan_en_regulator { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* GPIO_138 */ - - startup-delay-us = <70000>; - enable-active-high; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pps_pins>; - - gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; /* GPIN_114 */ - }; - -}; - -&gpio5 { - irda-en-hog { - gpio-hog; - gpios = <(175-160) GPIO_ACTIVE_HIGH>; - output-high; /* activate gpio_175 to disable IrDA receiver */ - }; -}; - -&omap3_pmx_core { - bt_pins: bt-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat5 = mmc3_dat1 = gpio137 */ - >; - }; - - wlan_pins: wlan-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat6 = mmc3_dat2 = gpio138 */ - >; - }; - - wlan_irq_pin: wlan-irq-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */ - >; - }; - - irda_pins: irda-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4) /* mcspi1_cs1 = gpio175 */ - >; - }; - - pps_pins: pps-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */ - >; - }; - - bno050_pins: pinmux-bno050-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT | MUX_MODE4) /* gpin113 */ - >; - }; -}; - -/* - * for WL183x module see - * Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml - */ - -&wifi_pwrseq { - /delete-property/ reset-gpios; -}; - -&mmc2 { - vmmc-supply = <&wlan_en>; - bus-width = <4>; - cap-power-off-card; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_irq_pin>; - - #address-cells = <1>; - #size-cells = <0>; - - /delete-property/ mmc-pwrseq; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_139 */ - ref-clock-frequency = <26000000>; - }; -}; - -&i2c2 { - /delete-node/ bmp085@77; - /delete-node/ bma180@41; - /delete-node/ itg3200@68; - /delete-node/ hmc5843@1e; - - gyrometer@69 { - compatible = "bosch,bmg160"; - reg = <0x69>; - }; - - accelerometer@10 { - compatible = "bosch,bmc150_accel"; - reg = <0x10>; - }; - - magnetometer@12 { - compatible = "bosch,bmc150_magn"; - reg = <0x12>; - }; - - bme280@76 { - compatible = "bosch,bme280"; - reg = <0x76>; - vdda-supply = <&vio>; - vddd-supply = <&vio>; - }; - - imu@29 { - compatible = "bosch,bno055"; - reg = <0x29>; - pinctrl-names = "default"; - pinctrl-0 = <&bno050_pins>; - /* interrupt at &gpio4 17 */ - }; -}; diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/omap3-gta04a5one.dts deleted file mode 100644 index 1e5703d1b02e..000000000000 --- a/arch/arm/boot/dts/omap3-gta04a5one.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-18 H. Nikolaus Schaller - */ - -#include "omap3-gta04a5.dts" - -/ { - model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; -}; - -&omap3_pmx_core { - gpmc_pins: gpmc-pins { - pinctrl-single,pins = < - - /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ - - /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ - - /* - * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable - * according to TRM. OneNAND seems to require PIN_INPUT on clock. - */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; -}; - -&gpmc { - /* switch inherited setup to OneNAND */ - - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - /delete-node/ nand@0,0; - - onenand@0,0 { - - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - - bootloaders_env@240000 { - label = "U-Boot Env"; - reg = <0x240000 0x40000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x600000>; - }; - - filesystem@880000 { - label = "File System"; - reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - - }; -}; diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi deleted file mode 100644 index 3a258a692757..000000000000 --- a/arch/arm/boot/dts/omap3-ha-common.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-tao3530.dtsi" - -/ { - gpio_poweroff { - pinctrl-names = "default"; - pinctrl-0 = <&poweroff_pins>; - - compatible = "gpio-poweroff"; - gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ - }; -}; - -&omap3_pmx_core { - sound2_pins: sound2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ - >; - }; - - led_blue_pins: led-blue-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ - >; - }; - - led_green_pins: led-green-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ - >; - }; - - led_red_pins: led-red-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ - >; - }; - - poweroff_pins: poweroff-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ - >; - }; - - powerdown_input_pins: powerdown-input-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ - >; - }; - - fpga_boot0_pins: fpga-boot0-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ - >; - }; - - fpga_boot1_pins: fpga-boot1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ - >; - }; -}; - -/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts deleted file mode 100644 index 94f6b7931e33..000000000000 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-ha-common.dtsi" - -/ { - model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - &powerdown_input_pins - &fpga_boot0_pins - &fpga_boot1_pins - &led_blue_pins - &led_green_pins - &led_red_pins - &touchscreen_wake_pins - >; - - touchscreen_irq_pins: touchscreen-irq-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ - >; - }; - - touchscreen_wake_pins: touchscreen-wake-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: lte430-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; -}; - -/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <31250000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <86>; - hsync-len = <1>; - vback-porch = <30>; - vfront-porch = <13>; - vsync-len = <3>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ - - default-on; - }; -}; diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts deleted file mode 100644 index 19e471eb3b4e..000000000000 --- a/arch/arm/boot/dts/omap3-ha.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-ha-common.dtsi" - -/ { - model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - &powerdown_input_pins - &fpga_boot0_pins - &fpga_boot1_pins - &led_blue_pins - &led_green_pins - &led_red_pins - >; -}; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi deleted file mode 100644 index e068ecf86b8f..000000000000 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common device tree for IGEP boards based on AM/DM37x - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "igep2"; - ti,mcbsp = <&mcbsp2>; - }; - - vdd33: regulator-vdd33 { - compatible = "regulator-fixed"; - regulator-name = "vdd33"; - regulator-always-on; - }; - -}; - -&omap3_pmx_core { - gpmc_pins: gpmc-pins { - pinctrl-single,pins = < - /* OneNAND seems to require PIN_INPUT on clock. */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29c4g96maz"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - }; - - onenand@0,0 { - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-wrap; - gpmc,burst-read; - gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <96>; - gpmc,cs-wr-off-ns = <96>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <18>; - gpmc,oe-off-ns = <96>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <96>; - gpmc,rd-cycle-ns = <114>; - gpmc,wr-cycle-ns = <114>; - gpmc,access-ns = <90>; - gpmc,page-burst-access-ns = <12>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <6>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <90>; - gpmc,sync-clk-ps = <12000>; - - #address-cells = <1>; - #size-cells = <1>; - - status = "disabled"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <4>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi deleted file mode 100644 index 13f434625407..000000000000 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ /dev/null @@ -1,261 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common Device Tree Source for IGEPv2 - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - */ - -#include "omap3-igep.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user1 { - label = "omap3:red:user1"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user2 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; - }; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ - vcc-supply = <&hsusb1_power>; - #phy-cells = <0>; - }; - - tfp410: encoder { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &tfp410_pins - &dss_dpi_pins - >; - - tfp410_pins: tfp410-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - >; - }; - - smsc9221_pins: smsc9221-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - hsusbb1_pins: hsusbb1-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; - }; - - leds_pins: leds-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ - >; - }; - - mmc1_wp_pins: mmc1-cd-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ - >; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc9221_pins>; - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&vpll2 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; -}; - -&dss { - status = "okay"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&mmc1 { - pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ -}; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts deleted file mode 100644 index 316e8e6b39cd..000000000000 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) - * - * Copyright (C) Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ - -#include "omap3-igep0020-common.dtsi" - -/ { - model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap3"; - - /* Regulator to trigger the WL_EN signal of the Wifi module */ - lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { - compatible = "regulator-fixed"; - regulator-name = "regulator-lbep5clwmc-wlen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ - enable-active-high; - }; -}; - -&omap3_pmx_core { - lbep5clwmc_pins: lbep5clwmc-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; - vmmc-supply = <&lbep5clwmc_wlen>; - bus-width = <4>; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ - }; -}; - -&uart2 { - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ - max-speed = <300000>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts deleted file mode 100644 index 232cf9187822..000000000000 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ - -#include "omap3-igep0020-common.dtsi" - -/ { - model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap3"; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ - <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ - }; -}; - -&omap3_pmx_core { - lbee1usjyc_pins: lbee1usjyc-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ - >; - }; -}; - -/* On board Wifi module */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; -}; diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi deleted file mode 100644 index d434f75aadac..000000000000 --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common Device Tree Source for IGEP COM MODULE - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - */ - -#include "omap3-igep.dtsi" - -/ { - leds: gpio_leds { - compatible = "gpio-leds"; - - user0 { - label = "omap3:red:user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - default-state = "off"; - }; - - user1 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ - default-state = "off"; - }; - - user2 { - label = "omap3:red:user1"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ - default-state = "off"; - }; - }; - - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ - #phy-cells = <0>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; - - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_core2_pins>; - - hsusb2_core2_pins: hsusb2-core2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - leds_core2_pins: leds-core2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ -}; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts deleted file mode 100644 index fddd7c86fec4..000000000000 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - */ - -#include "omap3-igep0030-common.dtsi" - -/ { - model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap3"; - - /* Regulator to trigger the WL_EN signal of the Wifi module */ - lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { - compatible = "regulator-fixed"; - regulator-name = "regulator-lbep5clwmc-wlen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ - enable-active-high; - }; -}; - -&omap3_pmx_core { - lbep5clwmc_pins: lbep5clwmc-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ - >; - }; - - leds_pins: leds-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ - >; - }; - -}; - -&i2c2 { - status = "disabled"; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins &leds_core2_pins>; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; - vmmc-supply = <&lbep5clwmc_wlen>; - bus-width = <4>; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ - }; -}; - -&uart2 { - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ - max-speed = <300000>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts deleted file mode 100644 index e3f99dbef2a1..000000000000 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ - -#include "omap3-igep0030-common.dtsi" - -/ { - model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap3"; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ - <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ - }; -}; - -&omap3_pmx_core { - lbee1usjyc_pins: lbee1usjyc-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_core2_pins>; - - boot { - label = "omap3:green:boot"; - gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ - default-state = "on"; - }; -}; - -/* On board Wifi module */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; -}; - diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts deleted file mode 100644 index bb6fab9fa47d..000000000000 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ /dev/null @@ -1,305 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include -#include "omap34xx.dtsi" -#include "omap-gpmc-smsc911x.dtsi" - -/ { - model = "TI OMAP3430 LDP (Zoom1 Labrador)"; - compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - key_enter { - label = "enter"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ - linux,code = ; - wakeup-source; - }; - - key_f1 { - label = "f1"; - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ - linux,code = ; - wakeup-source; - }; - - key_f2 { - label = "f2"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ - linux,code = ; - wakeup-source; - }; - - key_f3 { - label = "f3"; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ - linux,code = ; - wakeup-source; - }; - - key_f4 { - label = "f4"; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ - linux,code = ; - wakeup-source; - }; - - key_left { - label = "left"; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ - linux,code = ; - wakeup-source; - }; - - key_right { - label = "right"; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ - linux,code = ; - wakeup-source; - }; - - key_up { - label = "up"; - gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ - linux,code = ; - wakeup-source; - }; - - key_down { - label = "down"; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ - linux,code = ; - wakeup-source; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ - <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,nand"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x140000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x1c0000 0x40000>; - }; - partition@200000 { - label = "Kernel"; - reg = <0x200000 0x1e00000>; - }; - partition@2000000 { - label = "Filesystem"; - reg = <0x2000000 0x6000000>; - }; - }; - - ethernet@gpmc { - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - reg = <1 0 0xff>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power-idle"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -/* tps61130rsa enabled by twl4030 regen */ -&lcd_3v3 { - regulator-always-on; -}; - -&lcd0 { - enable-gpios = <&twl_gpio 15 GPIO_ACTIVE_HIGH>; /* lcd INI */ - reset-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; /* gpio55, lcd RESB */ - mode-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio56, lcd MO */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio2>; - interrupts = <22 0>; /* gpio54 */ - pendown-gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - /* See 35xx errata 2.1.1.128 in SPRZ278F */ - compatible = "ti,omap3-pre-es3-hsmmc"; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&omap3_pmx_core { - gpio_key_pins: gpio-key-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ - >; - }; - - musb_pins: musb-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - >; - }; -}; - -&twl_keypad { - linux,keymap = ; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&musb_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; - -&vaux1 { - /* Needed for ads7846 */ - regulator-name = "vcc"; -}; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi deleted file mode 100644 index 005a3d67f3ed..000000000000 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ /dev/null @@ -1,459 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Christoph Fritz - */ - -#include "omap36xx.dtsi" - -/ { - model = "INCOstartec LILLY-A83X module (DM3730)"; - compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; - - chosen { - bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "lilly-a83x::led1"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "lilly-a83x"; - - ti,mcbsp = <&mcbsp2>; - }; - - reg_vcc3: vcc3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_vcc3>; - #phy-cells = <0>; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - - lan9221_pins: lan9221-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - tsc2048_pins: tsc2048-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; - - mmc1cd_pins: mmc1cd-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - hsusb1_pins: hsusb1-pins { - pinctrl-single,pins = < - - /* GPIO 182 controls USB-Hub reset. But USB-Phy its - * reset can't be controlled. So we clamp this GPIO to - * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. - */ - - OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ - >; - }; - - hsusb_otg_pins: hsusb-otg-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - spi2_pins: spi2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - - hsusb1_2_pins: hsusb1-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - >; - }; - - gpio1_pins: gpio1-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ - >; - }; - -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&gpio6 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; -}; - -&i2c1 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - vmmc1: regulator-vmmc1 { - regulator-always-on; - }; - - vdd1: regulator-vdd1 { - regulator-always-on; - }; - - vdd2: regulator-vdd2 { - regulator-always-on; - }; -}; - -&i2c2 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&i2c3 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - gpiom1: gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&mmc1 { - cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; - cd-inverted; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mcspi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins>; - - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* boot6 / gpio_8 */ - spi-max-frequency = <1000000>; - pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - vcc-supply = <®_vcc3>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2048_pins>; - - ti,x-min = /bits/ 16 <300>; - ti,x-max = /bits/ 16 <3000>; - ti,y-min = /bits/ 16 <600>; - ti,y-max = /bits/ 16 <3600>; - ti,x-plate-ohms = /bits/ 16 <80>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - - wakeup-source; - }; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_2_pins>; - num-ports = <2>; - port1-mode = "ehci-phy"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, - <7 0 0x15000000 0x01000000>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - /* no elm on omap3 */ - - gpmc,mux-add-data = <0>; - gpmc,device-width = <2>; - gpmc,wait-pin = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,burst-length = <4>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <100>; - gpmc,cs-wr-off-ns = <100>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <100>; - gpmc,adv-wr-off-ns = <100>; - gpmc,oe-on-ns = <5>; - gpmc,oe-off-ns = <75>; - gpmc,we-on-ns = <5>; - gpmc,we-off-ns = <75>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <60>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <50>; - gpmc,wr-data-mux-bus-ns = <75>; - gpmc,wr-access-ns = <155>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "MLO"; - reg = <0 0x80000>; - }; - - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - partition@260000 { - label = "u-boot-environment"; - reg = <0x260000 0x20000>; - }; - - partition@280000 { - label = "kernel"; - reg = <0x280000 0x500000>; - }; - - partition@780000 { - label = "filesystem"; - reg = <0x780000 0xf880000>; - }; - }; - - ethernet@7,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <60>; - gpmc,cs-wr-off-ns = <60>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <60>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <50>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wr-data-mux-bus-ns = <15>; - gpmc,wr-access-ns = <75>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <®_vcc3>; - vdd33a-supply = <®_vcc3>; - reg-io-width = <4>; - interrupt-parent = <&gpio5>; - interrupts = <1 0x2>; - reg = <7 0 0xff>; - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - phy-mode = "mii"; - }; -}; diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts deleted file mode 100644 index 0891c6682a67..000000000000 --- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Christoph Fritz - */ -/dts-v1/; - -#include "omap3-lilly-a83x.dtsi" - -/ { - model = "INCOstartec LILLY-DBB056 (DM3730)"; - compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap3"; -}; - -&twl { - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - lan9117_pins: lan9117-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ - >; - }; - - gpio4_pins: gpio4-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ - >; - }; - - gpio5_pins: gpio5-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ - >; - }; - - lcd_pins: lcd-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ - OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ - >; - }; - - spi1_pins: spi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio4_pins>; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio5_pins>; -}; - -&mmc2 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vmmc1>; - cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ - wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - ti,dual-volt; -}; - -&mcspi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ - <4 0 0x20000000 0x01000000>, - <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ - - ethernet@4,0 { - compatible = "smsc,lan9117", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <65>; - gpmc,cs-wr-off-ns = <65>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <65>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <65>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <60>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wr-data-mux-bus-ns = <15>; - gpmc,wr-access-ns = <75>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <®_vcc3>; - vdd33a-supply = <®_vcc3>; - reg-io-width = <4>; - interrupt-parent = <&gpio4>; - interrupts = <2 0x2>; - reg = <4 0 0xff>; - pinctrl-names = "default"; - pinctrl-0 = <&lan9117_pins>; - phy-mode = "mii"; - smsc,force-internal-phy; - }; -}; diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts deleted file mode 100644 index a3cf3f443785..000000000000 --- a/arch/arm/boot/dts/omap3-n9.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * omap3-n9.dts - Device Tree file for Nokia N9 - * - * Written by: Aaro Koskinen - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" -#include - -/ { - model = "Nokia N9"; - compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap3"; -}; - -&i2c2 { - smia_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - /* No reset gpio */ - vana-supply = <&vaux3>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - flash-leds = <&as3645a_flash &as3645a_indicator>; - port { - smia_1_1: endpoint { - link-frequencies = /bits/ 64 <199200000 210000000 499200000>; - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; - -&i2c3 { - ak8975@f { - compatible = "asahi-kasei,ak8975"; - reg = <0x0f>; - }; -}; - -&isp { - vdd-csiphy1-supply = <&vaux2>; - vdd-csiphy2-supply = <&vaux2>; - ports { - port@2 { - reg = <2>; - csi2a_ep: endpoint { - remote-endpoint = <&smia_1_1>; - clock-lanes = <2>; - data-lanes = <1 3>; - crc = <1>; - lane-polarities = <1 1 1>; - }; - }; - }; -}; - -&modem { - compatible = "nokia,n9-modem"; -}; - -&lis302 { - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-46)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <46>; - st,max-limit-z = <46>; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(6, 8, KEY_VOLUMEUP) - MATRIX_KEY(7, 8, KEY_VOLUMEDOWN) - >; -}; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts deleted file mode 100644 index d33485341251..000000000000 --- a/arch/arm/boot/dts/omap3-n900.dts +++ /dev/null @@ -1,1159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013 Pavel Machek - * Copyright (C) 2013-2014 Aaro Koskinen - */ - -/dts-v1/; - -#include "omap34xx.dtsi" -#include -#include -#include - -/* - * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall - * for omap AES HW crypto support. When linux kernel try to access memory of AES - * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" - * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no - * crash anymore) omap AES support will be disabled for all Nokia N900 devices. - * There is "unofficial" version of bootloader which enables AES in L3 firewall - * but it is not widely used and to prevent kernel crash rather AES is disabled. - * There is also no runtime detection code if AES is disabled in L3 firewall... - */ -&aes1_target { - status = "disabled"; -}; - -&aes2_target { - status = "disabled"; -}; - -/ { - model = "Nokia N900"; - compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; - - aliases { - i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - display0 = &lcd; - display1 = &tv; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-heartbeat { - label = "debug::sleep"; - gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */ - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&debug_leds>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - gpio_keys { - compatible = "gpio-keys"; - - camera_lens_cover { - label = "Camera Lens Cover"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - camera_focus { - label = "Camera Focus"; - gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ - linux,code = ; - linux,can-disable; - }; - - camera_capture { - label = "Camera Capture"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ - linux,code = ; - linux,can-disable; - }; - - lock_button { - label = "Lock Button"; - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ - linux,code = ; - linux,can-disable; - }; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - proximity_sensor { - label = "Proximity Sensor"; - gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - machine_cover { - label = "Machine Cover"; - gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - }; - - isp1707: isp1707 { - compatible = "nxp,isp1707"; - nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; - usb-phy = <&usb2_phy>; - }; - - tv: connector { - compatible = "composite-video-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - sound: n900-audio { - compatible = "nokia,n900-audio"; - - nokia,cpu-dai = <&mcbsp2>; - nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; - nokia,headphone-amplifier = <&tpa6130a2>; - - tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ - jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ - eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ - speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; - }; - - battery: n900-battery { - compatible = "nokia,n900-battery"; - io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; - io-channel-names = "temp", "bsi", "vbat"; - }; - - pwm9: pwm-9 { - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x00>; /* timer_sys_ck */ - }; - - ir: n900-ir { - compatible = "nokia,n900-ir"; - pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ - }; - - rom_rng: rng { - compatible = "nokia,n900-rom-rng"; - clocks = <&rng_ick>; - clock-names = "ick"; - }; - - /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */ - vctcxo: vctcxo { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&isp { - vdds_csib-supply = <&vaux2>; - - pinctrl-names = "default"; - pinctrl-0 = <&camera_pins>; - - ports { - port@1 { - reg = <1>; - - csi_isp: endpoint { - remote-endpoint = <&csi_cam1>; - bus-type = ; - clock-lanes = <1>; - data-lanes = <0>; - lane-polarity = <0 0>; - /* Select strobe = <1> for back camera, <0> for front camera */ - strobe = <1>; - }; - }; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ - >; - }; - - ethernet_pins: ethernet-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ - >; - }; - - gpmc_pins: gpmc-pins { - pinctrl-single,pins = < - - /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ - - /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ - - /* - * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable - * according to TRM. OneNAND seems to require PIN_INPUT on clock. - */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - debug_leds: debug-led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ - >; - }; - - mcspi4_pins: mcspi4-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - acx565akm_pins: acx565akm-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ - >; - }; - - dss_sdi_pins: dss-sdi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ - - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ - >; - }; - - wl1251_pins: wl1251-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ - OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ - >; - }; - - ssi_pins: ssi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ - >; - }; - - modem_pins: modem-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ - >; - }; - - camera_pins: camera-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ - OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */ - OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2200000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux1 { - regulator-name = "V28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; /* due to battery cover sensor */ -}; - -&vaux2 { - regulator-name = "VCSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vaux3 { - regulator-name = "VMMC2_30"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vaux4 { - regulator-name = "VCAM_ANA_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vmmc1 { - regulator-name = "VMMC1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vmmc2 { - regulator-name = "V28_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; /* due VIO leak to AIC34 VDDs */ -}; - -&vpll1 { - regulator-name = "VPLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; -}; - -&vpll2 { - regulator-name = "VSDI_CSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; -}; - -&vsim { - regulator-name = "VMMC2_IO_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vio { - regulator-name = "VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vintana1 { - regulator-name = "VINTANA1"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&vintana2 { - regulator-name = "VINTANA2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; -}; - -&vintdig { - regulator-name = "VINTDIG"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -/* First two dma channels are reserved on secure omap3 */ -&sdma { - dma-channel-mask = <0xfffffffc>; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; - - twl_power: power { - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; - ti,use_poweroff; - }; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) - MATRIX_KEY(0x00, 0x01, KEY_O) - MATRIX_KEY(0x00, 0x02, KEY_P) - MATRIX_KEY(0x00, 0x03, KEY_COMMA) - MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) - MATRIX_KEY(0x00, 0x06, KEY_A) - MATRIX_KEY(0x00, 0x07, KEY_S) - - MATRIX_KEY(0x01, 0x00, KEY_W) - MATRIX_KEY(0x01, 0x01, KEY_D) - MATRIX_KEY(0x01, 0x02, KEY_F) - MATRIX_KEY(0x01, 0x03, KEY_G) - MATRIX_KEY(0x01, 0x04, KEY_H) - MATRIX_KEY(0x01, 0x05, KEY_J) - MATRIX_KEY(0x01, 0x06, KEY_K) - MATRIX_KEY(0x01, 0x07, KEY_L) - - MATRIX_KEY(0x02, 0x00, KEY_E) - MATRIX_KEY(0x02, 0x01, KEY_DOT) - MATRIX_KEY(0x02, 0x02, KEY_UP) - MATRIX_KEY(0x02, 0x03, KEY_ENTER) - MATRIX_KEY(0x02, 0x05, KEY_Z) - MATRIX_KEY(0x02, 0x06, KEY_X) - MATRIX_KEY(0x02, 0x07, KEY_C) - MATRIX_KEY(0x02, 0x08, KEY_F9) - - MATRIX_KEY(0x03, 0x00, KEY_R) - MATRIX_KEY(0x03, 0x01, KEY_V) - MATRIX_KEY(0x03, 0x02, KEY_B) - MATRIX_KEY(0x03, 0x03, KEY_N) - MATRIX_KEY(0x03, 0x04, KEY_M) - MATRIX_KEY(0x03, 0x05, KEY_SPACE) - MATRIX_KEY(0x03, 0x06, KEY_SPACE) - MATRIX_KEY(0x03, 0x07, KEY_LEFT) - - MATRIX_KEY(0x04, 0x00, KEY_T) - MATRIX_KEY(0x04, 0x01, KEY_DOWN) - MATRIX_KEY(0x04, 0x02, KEY_RIGHT) - MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) - MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) - MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) - MATRIX_KEY(0x04, 0x08, KEY_F10) - - MATRIX_KEY(0x05, 0x00, KEY_Y) - MATRIX_KEY(0x05, 0x08, KEY_F11) - - MATRIX_KEY(0x06, 0x00, KEY_U) - - MATRIX_KEY(0x07, 0x00, KEY_I) - MATRIX_KEY(0x07, 0x01, KEY_F7) - MATRIX_KEY(0x07, 0x02, KEY_F8) - >; -}; - -&twl_gpio { - ti,pullups = <0x0>; - ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; - - tlv320aic3x: tlv320aic3x@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ - ai3x-gpio-func = < - 0 /* AIC3X_GPIO1_FUNC_DISABLED */ - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ - >; - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - - ai3x-micbias-vg = <1>; - }; - - tlv320aic3x_aux: tlv320aic3x@19 { - compatible = "ti,tlv320aic3x"; - reg = <0x19>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - - ai3x-micbias-vg = <2>; - }; - - tsl2563: tsl2563@29 { - compatible = "amstaos,tsl2563"; - reg = <0x29>; - - amstaos,cover-comp-gain = <16>; - }; - - adp1653: led-controller@30 { - compatible = "adi,adp1653"; - reg = <0x30>; - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ - - flash { - flash-timeout-us = <500000>; - flash-max-microamp = <320000>; - led-max-microamp = <50000>; - }; - indicator { - led-max-microamp = <17500>; - }; - }; - - lp5523: lp5523@32 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - - led@0 { - reg = <0>; - chan-name = "lp5523:kb1"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_KBD_BACKLIGHT; - }; - - led@1 { - reg = <1>; - chan-name = "lp5523:kb2"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_KBD_BACKLIGHT; - }; - - led@2 { - reg = <2>; - chan-name = "lp5523:kb3"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_KBD_BACKLIGHT; - }; - - led@3 { - reg = <3>; - chan-name = "lp5523:kb4"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_KBD_BACKLIGHT; - }; - - led@4 { - reg = <4>; - chan-name = "lp5523:b"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led@5 { - reg = <5>; - chan-name = "lp5523:g"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led@6 { - reg = <6>; - chan-name = "lp5523:r"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led@7 { - reg = <7>; - chan-name = "lp5523:kb5"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_KBD_BACKLIGHT; - }; - - led@8 { - reg = <8>; - chan-name = "lp5523:kb6"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - color = ; - function = LED_FUNCTION_KBD_BACKLIGHT; - }; - }; - - bq27200: bq27200@55 { - compatible = "ti,bq27200"; - reg = <0x55>; - power-supplies = <&bq24150a>; - }; - - /* Stereo headphone amplifier */ - tpa6130a2: tpa6130a2@60 { - compatible = "ti,tpa6130a2"; - reg = <0x60>; - - Vdd-supply = <&vmmc2>; - - power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ - }; - - si4713: si4713@63 { - compatible = "silabs,si4713"; - reg = <0x63>; - - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ - vio-supply = <&vio>; - vdd-supply = <&vaux1>; - }; - - bq24150a: bq24150a@6b { - compatible = "ti,bq24150a"; - reg = <0x6b>; - - ti,current-limit = <100>; - ti,weak-battery-voltage = <3400>; - ti,battery-regulation-voltage = <4200>; - ti,charge-current = <650>; - ti,termination-current = <100>; - ti,resistor-sense = <68>; - - ti,usb-charger-detection = <&isp1707>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - accelerometer@1d { - compatible = "st,lis302dl"; - reg = <0x1d>; - - vdd-supply = <&vaux1>; - vddio-supply = <&vio>; - - interrupt-parent = <&gpio6>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>, - <20 IRQ_TYPE_EDGE_RISING>; /* 181 and 180 */ - - mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "1"; - }; - - cam1: camera@3e { - compatible = "toshiba,et8ek8"; - reg = <0x3e>; - - vana-supply = <&vaux4>; - - clocks = <&isp 0>; - clock-names = "extclk"; - clock-frequency = <9600000>; - - reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ - - lens-focus = <&ad5820>; - - port { - csi_cam1: endpoint { - bus-type = ; - strobe = <1>; - clock-inv = <0>; - crc = <1>; - - remote-endpoint = <&csi_isp>; - }; - }; - }; - - /* D/A converter for auto-focus */ - ad5820: dac@c { - compatible = "adi,ad5820"; - reg = <0x0c>; - - VANA-supply = <&vaux4>; - - #io-channel-cells = <0>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -/* most boards use vaux3, only some old versions use vmmc2 instead */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vaux3>; - vqmmc-supply = <&vsim>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ - <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - /* - * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported - * bootloader set values when booted with v5.1 - * (OneNAND Manufacturer: Samsung): - * - * cs0 GPMC_CS_CONFIG1: 0xfb001202 - * cs0 GPMC_CS_CONFIG2: 0x00111100 - * cs0 GPMC_CS_CONFIG3: 0x00020200 - * cs0 GPMC_CS_CONFIG4: 0x11001102 - * cs0 GPMC_CS_CONFIG5: 0x03101616 - * cs0 GPMC_CS_CONFIG6: 0x90060000 - */ - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <102>; - gpmc,cs-wr-off-ns = <102>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <12>; - gpmc,oe-off-ns = <102>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <102>; - gpmc,rd-cycle-ns = <132>; - gpmc,wr-cycle-ns = <132>; - gpmc,access-ns = <96>; - gpmc,page-burst-access-ns = <18>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <6>; - gpmc,wr-data-mux-bus-ns = <36>; - gpmc,wr-access-ns = <96>; - gpmc,sync-clk-ps = <15000>; - - /* - * MTD partition table corresponding to Nokia's - * Maemo 5 (Fremantle) release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "log"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "kernel"; - reg = <0x000c0000 0x00200000>; - }; - partition@4 { - label = "initfs"; - reg = <0x002c0000 0x00200000>; - }; - partition@5 { - label = "rootfs"; - reg = <0x004c0000 0x0fb40000>; - }; - }; - - /* Ethernet is on some early development boards and qemu */ - ethernet@gpmc { - compatible = "smsc,lan91c94"; - interrupt-parent = <&gpio2>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ - reg = <1 0 0xf>; /* 16 byte IO range */ - bank-width = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; - power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ - reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <48>; - gpmc,cs-wr-off-ns = <24>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <0>; - gpmc,adv-wr-off-ns = <0>; - gpmc,we-on-ns = <12>; - gpmc,we-off-ns = <18>; - gpmc,oe-on-ns = <12>; - gpmc,oe-off-ns = <48>; - gpmc,page-burst-access-ns = <0>; - gpmc,access-ns = <42>; - gpmc,rd-cycle-ns = <180>; - gpmc,wr-cycle-ns = <180>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <0>; - gpmc,wr-data-mux-bus-ns = <12>; - }; -}; - -&mcspi1 { - /* - * For some reason, touchscreen is necessary for screen to work at - * all on real hw. It works well without it on emulator. - * - * Also... order in the device tree actually matters here. - */ - tsc2005@0 { - compatible = "ti,tsc2005"; - spi-max-frequency = <6000000>; - reg = <0>; - - vio-supply = <&vio>; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; - - lcd: acx565akm@2 { - compatible = "sony,acx565akm"; - spi-max-frequency = <6000000>; - reg = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&acx565akm_pins>; - - label = "lcd"; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&sdi_out>; - }; - }; - }; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi4_pins>; - - wl1251@0 { - pinctrl-names = "default"; - pinctrl-0 = <&wl1251_pins>; - - vio-supply = <&vio>; - - compatible = "ti,wl1251"; - reg = <0>; - spi-max-frequency = <48000000>; - - spi-cpol; - spi-cpha; - - ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ - - clocks = <&vctcxo>; - }; -}; - -/* RNG not directly accessible on n900, see omap3-rom-rng instead */ -&rng_target { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <2>; - power = <50>; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bcm2048: bluetooth { - compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth"; - reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */ - host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ - bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ - clocks = <&vctcxo>; - clock-names = "sysclk"; - }; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_sdi_pins>; - - vdds_sdi-supply = <&vaux1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - sdi_out: endpoint { - remote-endpoint = <&lcd_in>; - datapairs = <2>; - }; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <1>; - }; - }; -}; - -&mcbsp2 { - status = "okay"; -}; - -&ssi_port1 { - pinctrl-names = "default"; - pinctrl-0 = <&ssi_pins>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - - modem: hsi-client { - compatible = "nokia,n900-modem"; - - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <55000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ - - gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ - <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ - <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ - <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ - <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en", - "cmt_rst", - "cmt_bsi"; - }; -}; - -&ssi_port2 { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi deleted file mode 100644 index aa4fcdbedd8f..000000000000 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) - * - * Written by: Aaro Koskinen - */ - -#include "omap36xx.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vemmc: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "VEMMC"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */ - startup-delay-us = <150>; - enable-active-high; - }; - - vwlan_fixed: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "VWLAN"; - gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "debug::sleep"; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&debug_leds>; - }; - }; - - /* controlled (enabled/disabled) directly by wl1271 */ - vctcxo: vctcxo { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&omap3_pmx_core { - accelerator_pins: accelerator-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ - >; - }; - - debug_leds: debug-led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - >; - }; - - wlan_pins: wlan-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ - OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ - >; - }; - - ssi_pins: ssi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ - >; - }; - - ssi_pins_idle: ssi-idle-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ - >; - }; - - modem_pins1: modem-core1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - >; - }; -}; - -&omap3_pmx_core2 { - modem_pins2: modem-core2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2900000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -/include/ "twl4030.dtsi" - -&twl { - compatible = "ti,twl5031"; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,pullups = <0x000001>; /* BIT(0) */ - ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ -}; - -&vdac { - regulator-name = "vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vpll1 { - regulator-name = "vpll1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vpll2 { - regulator-name = "vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vaux1 { - regulator-name = "vaux1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* CSI-2 receiver */ -&vaux2 { - regulator-name = "vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -/* Cameras */ -&vaux3 { - regulator-name = "vaux3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vaux4 { - regulator-name = "vaux4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vmmc1 { - regulator-name = "vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -&vmmc2 { - regulator-name = "vmmc2"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vintana1 { - regulator-name = "vintana1"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; - -&vintana2 { - regulator-name = "vintana2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; -}; - -&vintdig { - regulator-name = "vintdig"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; - -&vsim { - regulator-name = "vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vio { - regulator-name = "vio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&i2c2 { - clock-frequency = <400000>; - - as3645a@30 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30>; - compatible = "ams,as3645a"; - as3645a_flash: flash@0 { - reg = <0x0>; - flash-timeout-us = <150000>; - flash-max-microamp = <320000>; - led-max-microamp = <60000>; - ams,input-max-microamp = <1750000>; - }; - as3645a_indicator: indicator@1 { - reg = <0x1>; - led-max-microamp = <10000>; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - - lis302: lis302@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; - - pinctrl-names = "default"; - pinctrl-0 = <&accelerator_pins>; - - interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ - - st,highpass-cutoff-hz = <2>; - - /* Interrupt line 1 for thresholds */ - st,irq1-ff-wu-1; - st,irq1-ff-wu-2; - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wu-duration-1 = <8>; - st,wu-duration-2 = <8>; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vemmc>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -/* RNG not directly accessible on N950/N9. */ -&rng_target { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - /* - * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported - * bootloader set values when booted with v4.19 using both N950 - * and N9 devices (OneNAND Manufacturer: Samsung): - * - * gpmc cs0 before gpmc_cs_program_settings: - * cs0 GPMC_CS_CONFIG1: 0xfd001202 - * cs0 GPMC_CS_CONFIG2: 0x00181800 - * cs0 GPMC_CS_CONFIG3: 0x00030300 - * cs0 GPMC_CS_CONFIG4: 0x18001804 - * cs0 GPMC_CS_CONFIG5: 0x03171d1d - * cs0 GPMC_CS_CONFIG6: 0x97080000 - */ - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <122>; - gpmc,cs-wr-off-ns = <122>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <15>; - gpmc,oe-on-ns = <20>; - gpmc,oe-off-ns = <122>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <122>; - gpmc,rd-cycle-ns = <148>; - gpmc,wr-cycle-ns = <148>; - gpmc,access-ns = <117>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <10>; - gpmc,wr-data-mux-bus-ns = <40>; - gpmc,wr-access-ns = <117>; - - gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */ - - /* - * MTD partition table corresponding to Nokia's MeeGo 1.2 - * Harmattan release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "config"; - reg = <0x00100000 0x002c0000>; - }; - partition@2 { - label = "kernel"; - reg = <0x003c0000 0x01000000>; - }; - partition@3 { - label = "log"; - reg = <0x013c0000 0x00200000>; - }; - partition@4 { - label = "var"; - reg = <0x015c0000 0x1ca40000>; - }; - partition@5 { - label = "moslo"; - reg = <0x1e000000 0x02000000>; - }; - partition@6 { - label = "omap2-onenand"; - reg = <0x00000000 0x20000000>; - }; - }; -}; - -&ssi_port1 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&ssi_pins>; - pinctrl-1 = <&ssi_pins_idle>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - - modem: hsi-client { - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins1 &modem_pins2>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <96000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ - - gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ - <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ - <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en"; - }; -}; - -&ssi_port2 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth"; - - reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */ - host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ - bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ - - clocks = <&vctcxo>; - clock-names = "sysclk"; - }; -}; - -&aes1_target { - status = "disabled"; -}; - -&aes2_target { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts deleted file mode 100644 index b99f97880204..000000000000 --- a/arch/arm/boot/dts/omap3-n950.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * omap3-n950.dts - Device Tree file for Nokia N950 - * - * Written by: Aaro Koskinen - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" -#include - -/ { - model = "Nokia N950"; - compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap3"; - - keys { - compatible = "gpio-keys"; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ - linux,input-type = ; - linux,code = ; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_slide_pins>; - }; - }; -}; - -&omap3_pmx_core { - keypad_slide_pins: debug-led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ - >; - }; -}; - -&omap3_pmx_core { - spi4_pins: spi4-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; -}; - -&omap3_pmx_core { - dsi_pins: dsi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - data1+ */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ - >; - }; - - display_pins: display-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ - >; - }; -}; - -&i2c2 { - smia_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - /* No reset gpio */ - vana-supply = <&vaux3>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - flash-leds = <&as3645a_flash &as3645a_indicator>; - port { - smia_1_1: endpoint { - link-frequencies = /bits/ 64 <210000000 333600000 398400000>; - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; - -&isp { - vdd-csiphy1-supply = <&vaux2>; - vdd-csiphy2-supply = <&vaux2>; - ports { - port@2 { - reg = <2>; - csi2a_ep: endpoint { - remote-endpoint = <&smia_1_1>; - clock-lanes = <2>; - data-lanes = <3 1>; - crc = <1>; - lane-polarities = <1 1 1>; - }; - }; - }; -}; - -&mcspi4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - - wlcore: wlcore@0 { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - reg = <0>; - spi-max-frequency = <48000000>; - clock-xtal; - ref-clock-frequency = <38400000>; - interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ - vwlan-supply = <&vwlan_fixed>; - }; -}; - -&modem { - compatible = "nokia,n950-modem"; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) - MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) - MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) - MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) - MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) - MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) - MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) - MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) - - MATRIX_KEY(0x03, 0x01, KEY_Z) - MATRIX_KEY(0x04, 0x01, KEY_A) - MATRIX_KEY(0x05, 0x01, KEY_Q) - MATRIX_KEY(0x06, 0x01, KEY_W) - MATRIX_KEY(0x07, 0x01, KEY_E) - - MATRIX_KEY(0x03, 0x02, KEY_X) - MATRIX_KEY(0x04, 0x02, KEY_S) - MATRIX_KEY(0x05, 0x02, KEY_D) - MATRIX_KEY(0x06, 0x02, KEY_C) - MATRIX_KEY(0x07, 0x02, KEY_V) - - MATRIX_KEY(0x03, 0x03, KEY_O) - MATRIX_KEY(0x04, 0x03, KEY_I) - MATRIX_KEY(0x05, 0x03, KEY_U) - MATRIX_KEY(0x06, 0x03, KEY_L) - MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) - - MATRIX_KEY(0x03, 0x04, KEY_Y) - MATRIX_KEY(0x04, 0x04, KEY_K) - MATRIX_KEY(0x05, 0x04, KEY_J) - MATRIX_KEY(0x06, 0x04, KEY_H) - MATRIX_KEY(0x07, 0x04, KEY_G) - - MATRIX_KEY(0x03, 0x05, KEY_B) - MATRIX_KEY(0x04, 0x05, KEY_COMMA) - MATRIX_KEY(0x05, 0x05, KEY_M) - MATRIX_KEY(0x06, 0x05, KEY_N) - MATRIX_KEY(0x07, 0x05, KEY_DOT) - - MATRIX_KEY(0x00, 0x06, KEY_SPACE) - MATRIX_KEY(0x03, 0x06, KEY_T) - MATRIX_KEY(0x04, 0x06, KEY_UP) - MATRIX_KEY(0x05, 0x06, KEY_LEFT) - MATRIX_KEY(0x06, 0x06, KEY_RIGHT) - MATRIX_KEY(0x07, 0x06, KEY_DOWN) - - MATRIX_KEY(0x03, 0x07, KEY_P) - MATRIX_KEY(0x04, 0x07, KEY_ENTER) - MATRIX_KEY(0x05, 0x07, KEY_SLASH) - MATRIX_KEY(0x06, 0x07, KEY_F) - MATRIX_KEY(0x07, 0x07, KEY_R) - >; -}; - -&lis302 { - st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; -}; - -&dss { - status = "okay"; - - vdda_video-supply = <&vdac>; -}; - -&dsi { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dsi_pins>; - - vdd-supply = <&vpll2>; - - port { - dsi_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <2 3 0 1 4 5>; - }; - }; - - lcd0: panel@0 { - compatible = "nokia,himalaya", "panel-dsi-cm"; - reg = <0>; - label = "lcd0"; - - pinctrl-names = "default"; - pinctrl-0 = <&display_pins>; - - vpnl-supply = <&vmmc2>; - vddi-supply = <&vio>; - - reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ - - width-mm = <49>; /* 48.960 mm */ - height-mm = <88>; /* 88.128 mm */ - - /* TODO: - * - panel is upside-down - * - top + bottom 5px are not visible - */ - panel-timing { - clock-frequency = <0>; /* Calculated by dsi */ - - hback-porch = <2>; - hactive = <480>; - hfront-porch = <0>; - hsync-len = <2>; - - vback-porch = <1>; - vactive = <864>; - vfront-porch = <0>; - vsync-len = <1>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi_out_ep>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi deleted file mode 100644 index 7f1671bf3dfa..000000000000 --- a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd35.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - led-gpio148 { - label = "overo:red:gpio148"; - gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ - }; - led-gpio150 { - label = "overo:yellow:gpio150"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ - }; - led-gpio151 { - label = "overo:blue:gpio151"; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ - }; - led-gpio170 { - label = "overo:green:gpio170"; - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ - wakeup-source; - }; - }; -}; - -&omap3_pmx_core { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; -}; - -&omap3_pmx_wkup { - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ - >; - }; -}; - -&usbhshost { - status = "disabled"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-alto35.dts b/arch/arm/boot/dts/omap3-overo-alto35.dts deleted file mode 100644 index 37c64dd5f672..000000000000 --- a/arch/arm/boot/dts/omap3-overo-alto35.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-alto35-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi deleted file mode 100644 index cc57626ea607..000000000000 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * The Gumstix Overo must be combined with an expansion board. - */ - -/ { - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "overo:blue:COM"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - linux,default-trigger = "mmc0"; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "overo"; - - ti,mcbsp = <&mcbsp2>; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - /* Regulator to trigger the nPoweron signal of the Wifi module */ - w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-npoweron"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */ - enable-active-high; - }; - - /* Regulator to trigger the nReset signal of the Wifi module */ - w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset { - pinctrl-names = "default"; - pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>; - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-wifi-nreset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ - startup-delay-us = <10000>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - /* WiFi/BT combo */ - w3cbw003c_pins: w3cbw003c-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ - >; - }; - - hsusb2_pins: hsusb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -/* i2c2 pins are used for gpio */ -&i2c2 { - status = "disabled"; -}; - -/* on board microSD slot */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -/* optional on board WiFi */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&w3cbw003c_npoweron>; - vqmmc-supply = <&w3cbw003c_wifi_nreset>; - bus-width = <4>; - cap-sdio-irq; - non-removable; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0 */ - <4 0 0x2b000000 0x1000000>, /* CS4 */ - <5 0 0x2c000000 0x1000000>; /* CS5 */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name = "micron,mt29c4g96maz"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x80000>; /* 512KiB */ - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1C0000>; /* 1792KiB */ - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x800000>; /* 8192KiB */ - }; - partition@780000 { - label = "Filesystem"; - reg = <0xA80000 0>; - /* HACK: MTDPART_SIZ_FULL=0 so fill to end */ - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi deleted file mode 100644 index 0d0e62c00916..000000000000 --- a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - led-heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - led-gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-chestnut43.dts deleted file mode 100644 index bb53c76fff6c..000000000000 --- a/arch/arm/boot/dts/omap3-overo-chestnut43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-chestnut43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi deleted file mode 100644 index b1a800f2e940..000000000000 --- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * DVI output for some Gumstix Overo boards (Tobi and Summit) - */ - -&omap3_pmx_core { - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &dvi0; - }; - - tfp410: encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi deleted file mode 100644 index 5a8cb309c71a..000000000000 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) - */ - -&omap3_pmx_core { - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lb035_pins: lb035-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ - >; - }; - - ads7846_pins: ads7846-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ - - default-on; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - lcd0: display@1 { - compatible = "lgphilips,lb035q02"; - label = "lcd35"; - - reg = <1>; /* CS1 */ - spi-max-frequency = <500000>; - spi-cpol; - spi-cpha; - - pinctrl-names = "default"; - pinctrl-0 = <&lb035_pins>; - enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio4>; - interrupts = <18 0>; /* gpio_114 */ - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; -}; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi deleted file mode 100644 index c489c06f6cc7..000000000000 --- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) - */ - -&omap3_pmx_core { - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: lte430-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - ads7846_pins: ads7846-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd43"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ - - default-on; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio4>; - interrupts = <18 0>; /* gpio_114 */ - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi deleted file mode 100644 index 00369f699e20..000000000000 --- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) - */ - -/ { - lis33_3v3: lis33-3v3-reg { - compatible = "regulator-fixed"; - regulator-name = "lis33-3v3-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lis33_1v8: lis33-1v8-reg { - compatible = "regulator-fixed"; - regulator-name = "lis33-1v8-reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&omap3_pmx_core { - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - - /* optional 1K EEPROM with revision information */ - eeprom@51 { - compatible = "atmel,24c01"; - reg = <0x51>; - pagesize = <8>; - }; - - lis33de: lis33de@1d { - compatible = "st,lis33de", "st,lis3lv02d"; - reg = <0x1d>; - Vdd-supply = <&lis33_1v8>; - Vdd_IO-supply = <&lis33_3v3>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi deleted file mode 100644 index 5f6721326f86..000000000000 --- a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - led-heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - led-gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - -&usbhshost { - status = "disabled"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts b/arch/arm/boot/dts/omap3-overo-gallop43.dts deleted file mode 100644 index d882a58028c1..000000000000 --- a/arch/arm/boot/dts/omap3-overo-gallop43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-gallop43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi deleted file mode 100644 index 4b66f622ac13..000000000000 --- a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix Inc. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd35.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - led-heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - led-gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-overo-palo35.dts b/arch/arm/boot/dts/omap3-overo-palo35.dts deleted file mode 100644 index 39c8e9ce5776..000000000000 --- a/arch/arm/boot/dts/omap3-overo-palo35.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix Inc. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-palo35-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi deleted file mode 100644 index a8f163a899f0..000000000000 --- a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - led-heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - led-gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts b/arch/arm/boot/dts/omap3-overo-palo43.dts deleted file mode 100644 index 2c0f755ec8cc..000000000000 --- a/arch/arm/boot/dts/omap3-overo-palo43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-palo43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts deleted file mode 100644 index 3eb935df04dc..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-alto35-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts deleted file mode 100644 index 25e82efe4f3b..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-chestnut43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts deleted file mode 100644 index 0c93ea3f9774..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-gallop43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts deleted file mode 100644 index 9468ef9f9742..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-palo35-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts deleted file mode 100644 index 9feead584479..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-palo43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts deleted file mode 100644 index 92f56b9d009d..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-summit-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts deleted file mode 100644 index 6d14466c180a..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-tobi-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts deleted file mode 100644 index bcf20ff3f281..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-tobiduo-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; -}; diff --git a/arch/arm/boot/dts/omap3-overo-storm.dtsi b/arch/arm/boot/dts/omap3-overo-storm.dtsi deleted file mode 100644 index da583b47ed8d..000000000000 --- a/arch/arm/boot/dts/omap3-overo-storm.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -#include "omap36xx.dtsi" -#include "omap3-overo-base.dtsi" - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - w3cbw003c_2_pins: w3cbw003c-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi deleted file mode 100644 index ec03ca17e98b..000000000000 --- a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-dvi.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - led-heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts b/arch/arm/boot/dts/omap3-overo-summit.dts deleted file mode 100644 index da5ca80430ae..000000000000 --- a/arch/arm/boot/dts/omap3-overo-summit.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-summit-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: led-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - >; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi deleted file mode 100644 index 5432e4e16ab5..000000000000 --- a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-dvi.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - led-heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi.dts deleted file mode 100644 index ce3f2404f329..000000000000 --- a/arch/arm/boot/dts/omap3-overo-tobi.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-tobi-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi deleted file mode 100644 index 218a10c0d815..000000000000 --- a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - smsc1: ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; - - smsc2: ethernet@4,0 { - compatible = "smsc,lan9221","smsc,lan9115"; - bank-width = <2>; - - gpmc,mux-add-data = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - - reg = <4 0 0xff>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* GPIO 65 */ - }; -}; - -&lis33de { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-tobiduo.dts deleted file mode 100644 index fc6163eae45e..000000000000 --- a/arch/arm/boot/dts/omap3-overo-tobiduo.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-tobiduo-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi deleted file mode 100644 index 7dc044e87226..000000000000 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -#include "omap34xx.dtsi" -#include "omap3-overo-base.dtsi" - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - w3cbw003c_2_pins: w3cbw003c-2-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts deleted file mode 100644 index 8d8c9085e6ff..000000000000 --- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - * Nikolaus Schaller - */ - -/* - * device tree for OpenPandora 1GHz with DM3730 - */ - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-pandora-common.dtsi" - -/ { - model = "Pandora Handheld Console 1GHz"; - - compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - &control_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; - - control_pins: control-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ - OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ - OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ - OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ - - >; - }; -}; diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts deleted file mode 100644 index 2d5eac3ffc6c..000000000000 --- a/arch/arm/boot/dts/omap3-pandora-600mhz.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - * Nikolaus Schaller - */ - -/* - * device tree for OpenPandora with OMAP3530 - */ - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-pandora-common.dtsi" - -/ { - model = "Pandora Handheld Console"; - - compatible = "openpandora,omap3-pandora-600mhz", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - &control_pins - >; - - hsusb2_2_pins: hsusb2-2-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; - - control_pins: control-pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ - OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ - OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ - OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ - >; - }; -}; diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi deleted file mode 100644 index e91000f5f304..000000000000 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ /dev/null @@ -1,730 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - * Nikolaus Schaller - * - * Common device tree include for OpenPandora devices. - */ - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &lcd; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tv: connector { - compatible = "connector-analog-tv"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - gpio-leds { - - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "pandora::sd1"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "pandora::sd2"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "pandora::bluetooth"; - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led4 { - label = "pandora::wifi"; - gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - - up-button { - label = "up"; - linux,code = ; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ - wakeup-source; - }; - - down-button { - label = "down"; - linux,code = ; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ - wakeup-source; - }; - - left-button { - label = "left"; - linux,code = ; - gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ - wakeup-source; - }; - - right-button { - label = "right"; - linux,code = ; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ - wakeup-source; - }; - - pageup-button { - label = "game 1"; - linux,code = ; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ - wakeup-source; - }; - - pagedown-button { - label = "game 3"; - linux,code = ; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ - wakeup-source; - }; - - home-button { - label = "game 4"; - linux,code = ; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ - wakeup-source; - }; - - end-button { - label = "game 2"; - linux,code = ; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ - wakeup-source; - }; - - right-shift { - label = "l"; - linux,code = ; - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ - wakeup-source; - }; - - kp-plus { - label = "l2"; - linux,code = ; - gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ - wakeup-source; - }; - - right-ctrl { - label = "r"; - linux,code = ; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ - wakeup-source; - }; - - kp-minus { - label = "r2"; - linux,code = ; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ - wakeup-source; - }; - - left-ctrl { - label = "ctrl"; - linux,code = ; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ - wakeup-source; - }; - - menu { - label = "menu"; - linux,code = ; - gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ - wakeup-source; - }; - - hold { - label = "hold"; - linux,code = ; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ - wakeup-source; - }; - - left-alt { - label = "alt"; - linux,code = ; - gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ - wakeup-source; - }; - - lid { - label = "lid"; - linux,code = <0x00>; /* SW_LID lid shut */ - linux,input-type = <0x05>; /* EV_SW */ - gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ - }; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ - vcc-supply = <&vaux2>; - #phy-cells = <0>; - }; - - /* HS USB Host VBUS supply - * disabling this regulator causes current leakage, and LCD flicker - * on earlier (CC) board revisions, so keep it always on */ - usb_host_5v: fixed-regulator-usb_host_5v { - compatible = "regulator-fixed"; - regulator-name = "usb_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */ - }; - - /* wl1251 wifi+bt module */ - wlan_en: fixed-regulator-wg7210_en { - compatible = "regulator-fixed"; - regulator-name = "vwlan"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <50000>; - enable-active-high; - gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* wg7210 (wifi+bt module) 32k clock buffer */ - wg7210_32k: fixed-regulator-wg7210_32k { - compatible = "regulator-fixed"; - regulator-name = "wg7210_32k"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - enable-active-high; - gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&omap3_pmx_core { - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - led_pins: leds-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ - OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ - OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ - >; - }; - - penirq_pins: penirq-pins { - pinctrl-single,pins = < - /* here we could enable to wakeup the cpu from suspend by a pen touch */ - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ - >; - }; - -}; - -&omap3_pmx_core2 { - /* define in CPU specific file that includes this one - * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() - */ -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_power: power { - compatible = "ti,twl4030-power-reset"; - ti,use_poweroff; - }; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - - codec { - ti,ramp_delay_value = <3>; - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl_keypad { - keypad,num-rows = <8>; - keypad,num-columns = <6>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(0, 1, KEY_8) - MATRIX_KEY(0, 2, KEY_I) - MATRIX_KEY(0, 3, KEY_J) - MATRIX_KEY(0, 4, KEY_N) - MATRIX_KEY(0, 5, KEY_M) - MATRIX_KEY(1, 0, KEY_0) - MATRIX_KEY(1, 1, KEY_7) - MATRIX_KEY(1, 2, KEY_U) - MATRIX_KEY(1, 3, KEY_H) - MATRIX_KEY(1, 4, KEY_B) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(2, 0, KEY_BACKSPACE) - MATRIX_KEY(2, 1, KEY_6) - MATRIX_KEY(2, 2, KEY_Y) - MATRIX_KEY(2, 3, KEY_G) - MATRIX_KEY(2, 4, KEY_V) - MATRIX_KEY(2, 5, KEY_FN) - MATRIX_KEY(3, 0, KEY_O) - MATRIX_KEY(3, 1, KEY_5) - MATRIX_KEY(3, 2, KEY_T) - MATRIX_KEY(3, 3, KEY_F) - MATRIX_KEY(3, 4, KEY_C) - MATRIX_KEY(4, 0, KEY_P) - MATRIX_KEY(4, 1, KEY_4) - MATRIX_KEY(4, 2, KEY_R) - MATRIX_KEY(4, 3, KEY_D) - MATRIX_KEY(4, 4, KEY_X) - MATRIX_KEY(5, 0, KEY_K) - MATRIX_KEY(5, 1, KEY_3) - MATRIX_KEY(5, 2, KEY_E) - MATRIX_KEY(5, 3, KEY_S) - MATRIX_KEY(5, 4, KEY_Z) - MATRIX_KEY(6, 0, KEY_L) - MATRIX_KEY(6, 1, KEY_2) - MATRIX_KEY(6, 2, KEY_W) - MATRIX_KEY(6, 3, KEY_A) - MATRIX_KEY(6, 4, KEY_RIGHTBRACE) - MATRIX_KEY(7, 0, KEY_ENTER) - MATRIX_KEY(7, 1, KEY_1) - MATRIX_KEY(7, 2, KEY_Q) - MATRIX_KEY(7, 3, KEY_LEFTSHIFT) - MATRIX_KEY(7, 4, KEY_LEFTBRACE ) - >; -}; - -/* backup battery charger */ -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -/* MMC2 */ -&vmmc2 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -/* LCD */ -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -/* USB Host PHY */ -&vaux2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -/* available on expansion connector */ -&vaux3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* ADS7846 and nubs */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* power audio DAC and LID sensor */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -&i2c2 { - clock-frequency = <100000>; - /* no clients so we should disable clock */ -}; - -&i2c3 { - clock-frequency = <100000>; - - bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; - -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -/* - * Many pandora boards have been produced with defective write-protect switches - * on either slot, so it was decided not to use this feature. If you know - * your board has good switches, feel free to uncomment wp-gpios below. - */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmc2>; - bus-width = <4>; - cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; - /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ -}; - -&mmc3 { - vmmc-supply = <&wlan_en>; - - bus-width = <4>; - non-removable; - ti,non-removable; - cap-power-off-card; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - - #address-cells = <1>; - #size-cells = <0>; - - wlan: wifi@1 { - compatible = "ti,wl1251"; - - reg = <1>; - - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */ - - ti,wl1251-has-eeprom; - }; -}; - -/* bluetooth*/ -&uart1 { -}; - -/* spare (expansion connector) */ -&uart2 { -}; - -/* console (expansion connector) */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ - - x-loader@0 { - label = "xloader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "uboot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "uboot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "boot"; - reg = <0x280000 0xa00000>; - }; - - filesystem@c80000 { - label = "rootfs"; - reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&penirq_pins>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */ - pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - vcc-supply = <&vaux4>; - - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; - - lcd: lcd@1 { - reg = <1>; /* CS1 */ - compatible = "tpo,td043mtea1"; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ - vcc-supply = <&vaux1>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - -}; - -/* n/a - used as GPIOs */ -&mcbsp1 { -}; - -/* audio DAC */ -&mcbsp2 { -}; - -/* bluetooth */ -&mcbsp3 { -}; - -/* to twl4030*/ -&mcbsp4 { -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "okay"; - vdds_dsi-supply = <&vpll2>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi deleted file mode 100644 index 2dbb687d4df2..000000000000 --- a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for omap dpi panels with QVGA and reset pins - * - * Note that the board specifc DTS file needs to specify - * at minimum the GPIO enable-gpios for display, and - * gpios for gpio-backlight. - */ - -/ { - aliases { - display0 = &lcd0; - }; - - backlight0: backlight { - compatible = "gpio-backlight"; - default-on; - }; - - /* 3.3V GPIO controlled regulator for LCD_ENVDD */ - lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - lcd0: display { - compatible = "sharp,ls037v7dw01"; - label = "lcd"; - power-supply = <&lcd_3v3>; - envdd-supply = <&lcd_3v3>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <18>; - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - vcc-supply = <&lcd_3v3>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - wakeup-source; - }; -}; diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi deleted file mode 100644 index 6730c749d5ea..000000000000 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 - */ - -/ { - tfp410: encoder { - compatible = "ti,tfp410"; - - powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: dvi-connector { - compatible = "dvi-connector"; - label = "dvi"; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - audio_amp: audio_amp { - compatible = "regulator-fixed"; - regulator-name = "audio_amp"; - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_audio_amp>; - gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ - regulator-always-on; - }; -}; - -&omap3_pmx_core { - smsc2_pins: smsc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ - OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ - >; - }; - - tfp410_pins: tfp410-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - sb_t35_audio_amp: sb-t35-audio-amp-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ - >; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <4 0 0x2d000000 0x01000000>; - - smsc2: ethernet@4,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc2_pins>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - reg = <4 0 0xff>; - bank-width = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <150>; - gpmc,cs-wr-off-ns = <150>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <140>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <140>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <120>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <75>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts deleted file mode 100644 index 07bec48dc441..000000000000 --- a/arch/arm/boot/dts/omap3-sbc-t3517.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab SBC-T3517 with CM-T3517 - */ - -#include "omap3-cm-t3517.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3517 with CM-T3517"; - compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ - vddvario: regulator-vddvario-sb-t35 { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a-sb-t35 { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &sb_t35_usb_hub_pins - &usb_hub_pins - >; - - mmc1_aux_pins: mmc1-aux-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc1_pins - &mmc1_aux_pins - >; - - wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ - cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&gpmc { - ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts deleted file mode 100644 index 1beefc319422..000000000000 --- a/arch/arm/boot/dts/omap3-sbc-t3530.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab SBC-T3530 with CM-T3530 - */ - -#include "omap3-cm-t3530.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3530 with CM-T3530"; - compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_usb_hub_pins>; - - sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ - >; - }; -}; - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; - -&mmc1 { - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts deleted file mode 100644 index aefc1187ebc9..000000000000 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab SBC-T3730 with CM-T3730 - */ - -#include "omap3-cm-t3730.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3730 with CM-T3730"; - compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_usb_hub_pins>; - - sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ - >; - }; -}; - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts deleted file mode 100644 index 79e004057482..000000000000 --- a/arch/arm/boot/dts/omap3-sniper.dts +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Paul Kocialkowski - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include - -/ { - model = "LG Optimus Black"; - compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - dp3t_sel_pins: dp3t-sel-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - lp8720_en_pin: lp8720-en-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - usb_otg_hs_pins: usb-otg-hs-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ - >; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - - mmc1_cd_pin: mmc1-cd-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ - >; - }; -}; - -&gpio2 { - ti,no-reset-on-init; -}; - -&gpio5 { - ti,no-reset-on-init; -}; - -&gpio6 { - ti,no-reset-on-init; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &dp3t_sel_pins>; - - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - lp8720@7d { - pinctrl-names = "default"; - pinctrl-0 = <&lp8720_en_pin>; - - compatible = "ti,lp8720"; - reg = <0x7d>; - - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */ - - lp8720_ldo1: ldo1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>; - - vmmc-supply = <&lp8720_ldo1>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */ - bus-width = <4>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; -}; - -&mmc3 { - status = "disabled"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP) - MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN) - MATRIX_KEY(0x02, 0x00, KEY_SELECT) - >; -}; - -/* - * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3. - * When not powered, these sensors cause the I2C3 clock to stay low at all times, - * making it impossible to reach other devices on I2C3. - */ - -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -&vdac { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi deleted file mode 100644 index 92a5846048bd..000000000000 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes1_target { - status = "disabled"; -}; - -&aes2_target { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - /* McBSP2 is used for onboard sound, same as on beagle */ - ti,mcbsp = <&mcbsp2>; - }; - - /* Regulator to enable/switch the vcc of the Wifi module */ - mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { - compatible = "regulator-fixed"; - regulator-name = "regulator-mmc2-sdio-poweron"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ - startup-delay-us = <10000>; - }; -}; - -&omap3_pmx_core { - hsusbb2_pins: hsusbb2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - /* wlan GPIO output for WLAN_EN */ - wlan_gpio: wlan-gpio-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - mcspi3_pins: mcspi3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ - >; - }; - - mcbsp3_pins: mcbsp3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ - >; - }; -}; - -/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ -&mcbsp1 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - bus-width = <8>; -}; - -// WiFi (Marvell 88W8686) on MMC2/SDIO -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&mmc2_sdio_poweron>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mcbsp3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - ti,nand-ecc-opt = "sw"; - - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts deleted file mode 100644 index c87956c59b08..000000000000 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-tao3530.dtsi" - -/ { - model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; - compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: lte430-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <2>; - vfront-porch = <3>; - vsync-len = <11>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ - - default-on; - }; -}; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts deleted file mode 100644 index 9f1e125fd77b..000000000000 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap-zoom-common.dtsi" - -/ { - model = "TI Zoom3"; - compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - /* REVISIT: twl gpio0 is mmc0_cd */ - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_2_pins: mmc3-2-pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - >; - }; -}; - -&omap3_pmx_wkup { - wlan_host_wkup: wlan-host-wkup-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; -/* -&mmc2 { - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; -*/ -&mmc3 { - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ - ref-clock-frequency = <26000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi deleted file mode 100644 index 92cd4c99dae7..000000000000 --- a/arch/arm/boot/dts/omap3.dtsi +++ /dev/null @@ -1,1039 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 SoC - * - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - compatible = "ti,omap3430", "ti,omap3"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &mmc1; - mmc1 = &mmc2; - mmc2 = &mmc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0x0>; - - clocks = <&dpll1_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - pmu@54000000 { - compatible = "arm,cortex-a8-pmu"; - reg = <0x54000000 0x800000>; - interrupts = <3>; - ti,hwmods = "debugss"; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - - iva: iva { - compatible = "ti,iva2.2"; - ti,hwmods = "iva"; - - dsp { - compatible = "ti,omap3-c64"; - }; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp@68000000 { - compatible = "ti,omap3-l3-smx", "simple-bus"; - reg = <0x68000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - l4_core: l4@48000000 { - compatible = "ti,omap3-l4-core", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x1000000>; - - scm: scm@2000 { - compatible = "ti,omap3-scm", "simple-bus"; - reg = <0x2000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x2000>; - - omap3_pmx_core: pinmux@30 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0x30 0x238>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon", "simple-bus"; - reg = <0x270 0x330>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x270 0x330>; - - pbias_regulator: pbias_regulator@2b0 { - compatible = "ti,pbias-omap3", "ti,pbias-omap"; - reg = <0x2b0 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; - - omap3_pmx_wkup: pinmux@a00 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0xa00 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - }; - }; - - aes1_target: target-module@480a6000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x480a6044 0x4>, - <0x480a6048 0x4>, - <0x480a604c 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&aes1_ick>; - clock-names = "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480a6000 0x2000>; - - aes1: aes1@0 { - compatible = "ti,omap3-aes"; - reg = <0 0x50>; - interrupts = <0>; - dmas = <&sdma 9 &sdma 10>; - dma-names = "tx", "rx"; - }; - }; - - aes2_target: target-module@480c5000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x480c5044 0x4>, - <0x480c5048 0x4>, - <0x480c504c 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&aes2_ick>; - clock-names = "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480c5000 0x2000>; - - aes2: aes2@0 { - compatible = "ti,omap3-aes"; - reg = <0 0x50>; - interrupts = <0>; - dmas = <&sdma 65 &sdma 66>; - dma-names = "tx", "rx"; - }; - }; - - prm: prm@48306000 { - compatible = "ti,omap3-prm"; - reg = <0x48306000 0x4000>; - interrupts = <11>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - cm: cm@48004000 { - compatible = "ti,omap3-cm"; - reg = <0x48004000 0x4000>; - - cm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_clockdomains: clockdomains { - }; - }; - - target-module@48320000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x48320000 0x4>, - <0x48320004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48320000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x20>; - }; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,omap3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - target-module@48056000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x48056000 0x4>, - <0x4805602c 0x4>, - <0x48056028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ - clocks = <&core_l3_ick>; - clock-names = "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48056000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap3430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <96>; - }; - }; - - gpio1: gpio@48310000 { - compatible = "ti,omap3-gpio"; - reg = <0x48310000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@49050000 { - compatible = "ti,omap3-gpio"; - reg = <0x49050000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@49052000 { - compatible = "ti,omap3-gpio"; - reg = <0x49052000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@49054000 { - compatible = "ti,omap3-gpio"; - reg = <0x49054000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@49056000 { - compatible = "ti,omap3-gpio"; - reg = <0x49056000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@49058000 { - compatible = "ti,omap3-gpio"; - reg = <0x49058000 0x200>; - interrupts = <34>; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap3-uart"; - reg = <0x4806a000 0x2000>; - interrupts-extended = <&intc 72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap3-uart"; - reg = <0x4806c000 0x400>; - interrupts-extended = <&intc 73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@49020000 { - compatible = "ti,omap3-uart"; - reg = <0x49020000 0x400>; - interrupts-extended = <&intc 74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap3-i2c"; - reg = <0x48070000 0x80>; - interrupts = <56>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap3-i2c"; - reg = <0x48072000 0x80>; - interrupts = <57>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap3-i2c"; - reg = <0x48060000 0x80>; - interrupts = <61>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap3-mailbox"; - ti,hwmods = "mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - #mbox-cells = <1>; - ti,mbox-num-users = <2>; - ti,mbox-num-fifos = <2>; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap2-mcspi"; - reg = <0x48098000 0x100>; - interrupts = <65>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap2-mcspi"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap2-mcspi"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, - <&sdma 16>, - <&sdma 23>, - <&sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap2-mcspi"; - reg = <0x480ba000 0x100>; - interrupts = <48>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - ti,hwmods = "hdq1w"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x480ad000 0x200>; - interrupts = <94>; - ti,hwmods = "mmc3"; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmu_isp: mmu@480bd400 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x480bd400 0x80>; - interrupts = <24>; - ti,hwmods = "mmu_isp"; - ti,#tlb-entries = <8>; - }; - - mmu_iva: mmu@5d000000 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x5d000000 0x80>; - interrupts = <28>; - ti,hwmods = "mmu_iva"; - status = "disabled"; - }; - - wdt2: wdt@48314000 { - compatible = "ti,omap3-wdt"; - reg = <0x48314000 0x80>; - ti,hwmods = "wd_timer2"; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <16>, /* OCP compliant interrupt */ - <59>, /* TX interrupt */ - <60>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - clocks = <&mcbsp1_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - /* Likely needs to be tagged disabled on HS devices */ - rng_target: target-module@480a0000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x480a003c 0x4>, - <0x480a0040 0x4>, - <0x480a0044 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&rng_ick>; - clock-names = "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480a0000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap2-rng"; - reg = <0x0 0x2000>; - interrupts = <52>; - }; - }; - - mcbsp2: mcbsp@49022000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49022000 0xff>, - <0x49028000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <17>, /* OCP compliant interrupt */ - <62>, /* TX interrupt */ - <63>, /* RX interrupt */ - <4>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - ti,buffer-size = <1280>; - ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; - clock-names = "fck", "ick"; - status = "disabled"; - }; - - mcbsp3: mcbsp@49024000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49024000 0xff>, - <0x4902a000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <22>, /* OCP compliant interrupt */ - <89>, /* TX interrupt */ - <90>, /* RX interrupt */ - <5>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; - clock-names = "fck", "ick"; - status = "disabled"; - }; - - mcbsp4: mcbsp@49026000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49026000 0xff>; - reg-names = "mpu"; - interrupts = <23>, /* OCP compliant interrupt */ - <54>, /* TX interrupt */ - <55>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - clocks = <&mcbsp4_fck>; - clock-names = "fck"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - mcbsp5: mcbsp@48096000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x48096000 0xff>; - reg-names = "mpu"; - interrupts = <27>, /* OCP compliant interrupt */ - <81>, /* TX interrupt */ - <82>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - clocks = <&mcbsp5_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - sham: sham@480c3000 { - compatible = "ti,omap3-sham"; - ti,hwmods = "sham"; - reg = <0x480c3000 0x64>; - interrupts = <49>; - dmas = <&sdma 69>; - dma-names = "rx"; - }; - - timer1_target: target-module@48318000 { - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x48318000 0x4>, - <0x48318010 0x4>, - <0x48318014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&gpt1_fck>, <&gpt1_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48318000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&gpt1_fck>; - clock-names = "fck"; - interrupts = <37>; - ti,timer-alwon; - }; - }; - - timer2_target: target-module@49032000 { - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x49032000 0x4>, - <0x49032010 0x4>, - <0x49032014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&gpt2_fck>, <&gpt2_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x49032000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0 0x400>; - interrupts = <38>; - }; - }; - - timer3: timer@49034000 { - compatible = "ti,omap3430-timer"; - reg = <0x49034000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; - }; - - timer4: timer@49036000 { - compatible = "ti,omap3430-timer"; - reg = <0x49036000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; - }; - - timer5: timer@49038000 { - compatible = "ti,omap3430-timer"; - reg = <0x49038000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4903a000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903a000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@4903c000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903c000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4903e000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903e000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; - ti,timer-pwm; - ti,timer-dsp; - }; - - timer9: timer@49040000 { - compatible = "ti,omap3430-timer"; - reg = <0x49040000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap3430-timer"; - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer12_target: target-module@48304000 { - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x48304000 0x4>, - <0x48304010 0x4>, - <0x48304014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&gpt12_fck>, <&gpt12_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48304000 0x1000>; - - timer12: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0 0x400>; - interrupts = <95>; - ti,timer-alwon; - ti,timer-secure; - }; - }; - - usbhstll: usbhstll@48062000 { - compatible = "ti,usbhs-tll"; - reg = <0x48062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@48064000 { - compatible = "ti,usbhs-host"; - reg = <0x48064000 0x400>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@48064400 { - compatible = "ti,ohci-omap3"; - reg = <0x48064400 0x400>; - interrupts = <76>; - remote-wakeup-connected; - }; - - usbhsehci: ehci@48064800 { - compatible = "ti,ehci-omap"; - reg = <0x48064800 0x400>; - interrupts = <77>; - }; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x02d0>; - interrupts = <20>; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - usb_otg_target: target-module@480ab000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x480ab400 0x4>, - <0x480ab404 0x4>, - <0x480ab408 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Clock defined in the SoC specific dtsi file */ - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x480ab000 0x1000>; - - usb_otg_hs: usb@0 { - compatible = "ti,omap3-musb"; - reg = <0 0x1000>; - interrupts = <92>, <93>; - interrupt-names = "mc", "dma"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - }; - }; - - dss: dss@48050000 { - compatible = "ti,omap3-dss"; - reg = <0x48050000 0x200>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss1_alwon_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@48050400 { - compatible = "ti,omap3-dispc"; - reg = <0x48050400 0x400>; - interrupts = <25>; - ti,hwmods = "dss_dispc"; - clocks = <&dss1_alwon_fck>; - clock-names = "fck"; - }; - - dsi: encoder@4804fc00 { - compatible = "ti,omap3-dsi"; - reg = <0x4804fc00 0x200>, - <0x4804fe00 0x40>, - <0x4804ff00 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = <25>; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; - clock-names = "fck", "sys_clk"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - rfbi: encoder@48050800 { - compatible = "ti,omap3-rfbi"; - reg = <0x48050800 0x100>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss1_alwon_fck>, <&dss_ick>; - clock-names = "fck", "ick"; - }; - - venc: encoder@48050c00 { - compatible = "ti,omap3-venc"; - reg = <0x48050c00 0x100>; - status = "disabled"; - ti,hwmods = "dss_venc"; - clocks = <&dss_tv_fck>; - clock-names = "fck"; - }; - }; - - ssi: ssi-controller@48058000 { - compatible = "ti,omap3-ssi"; - ti,hwmods = "ssi"; - - status = "disabled"; - - reg = <0x48058000 0x1000>, - <0x48059000 0x1000>; - reg-names = "sys", - "gdd"; - - interrupts = <71>; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ssi_port1: ssi-port@4805a000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805a000 0x800>, - <0x4805a800 0x800>; - reg-names = "tx", - "rx"; - - interrupts = <67>, - <68>; - }; - - ssi_port2: ssi-port@4805b000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805b000 0x800>, - <0x4805b800 0x800>; - reg-names = "tx", - "rx"; - - interrupts = <69>, - <70>; - }; - }; - }; -}; - -#include "omap3xxx-clocks.dtsi" - -/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt1_fck>; - assigned-clock-parents = <&omap_32k_fck>; - }; -}; diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts deleted file mode 100644 index 258ecd9e4519..000000000000 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TI OMAP3430 SDP"; - compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - /* - * S6-3 must be in ON position for 8 bit mode to function - * Else, use 4 bit mode - */ - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x10000000 0x08000000>, - <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ - <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name = "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; - - nand@1,0 { - compatible = "ti,omap2-nand"; - reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f1g08abb"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "sw"; - nand-bus-width = <8>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "xloader-nand"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "bootloader-nand"; - reg = <0x80000 0x140000>; - }; - partition@1c0000 { - label = "params-nand"; - reg = <0x1c0000 0xc0000>; - }; - partition@280000 { - label = "kernel-nand"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "filesystem-nand"; - reg = <0x780000 0x7880000>; - }; - }; - - onenand@2,0 { - linux,mtd-name = "samsung,kfm2g16q2m-deb8"; - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ - - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <84>; - gpmc,cs-wr-off-ns = <72>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <30>; - gpmc,oe-off-ns = <84>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <42>; - gpmc,rd-cycle-ns = <108>; - gpmc,wr-cycle-ns = <96>; - gpmc,access-ns = <78>; - gpmc,wr-data-mux-bus-ns = <30>; - - partition@0 { - label = "xloader-onenand"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "bootloader-onenand"; - reg = <0x80000 0x40000>; - }; - partition@c0000 { - label = "params-onenand"; - reg = <0xc0000 0x20000>; - }; - partition@e0000 { - label = "kernel-onenand"; - reg = <0xe0000 0x200000>; - }; - partition@2e0000 { - label = "filesystem-onenand"; - reg = <0x2e0000 0xfd20000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi deleted file mode 100644 index 24adfac26be0..000000000000 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3430 ES1 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - gfx_l3_ck: gfx_l3_ck@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - gfx_l3_fck: gfx_l3_fck@b40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,max-div = <7>; - reg = <0x0b40>; - ti,index-starts-at-one; - }; - - gfx_l3_ick: gfx_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gfx_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gfx_cg1_ck: gfx_cg1_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <1>; - }; - - gfx_cg2_ck: gfx_cg2_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <2>; - }; - - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <0>; - - d2d_26m_fck: clock-d2d-26m-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "d2d_26m_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - }; - - fshostusb_fck: clock-fshostusb-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "fshostusb_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <5>; - }; - - ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "ssi_ssr_gate_fck_3430es1"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - }; - }; - - clock@a40 { - compatible = "ti,clksel"; - reg = <0xa40>; - #clock-cells = <2>; - #address-cells = <0>; - - ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "ssi_ssr_div_fck_3430es1"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - usb_l4_div_ick: clock-usb-l4-div-ick { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "usb_l4_div_ick"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - ti,index-starts-at-one; - }; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <0>; - - hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clock-output-names = "hsotgusb_ick_3430es1"; - clocks = <&core_l3_ick>; - ti,bit-shift = <4>; - }; - - fac_ick: clock-fac-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "fac_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <8>; - }; - - ssi_ick: clock-ssi-ick-3430es1 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clock-output-names = "ssi_ick_3430es1"; - clocks = <&ssi_l4_ick>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: clock-usb-l4-gate-ick { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clock-output-names = "usb_l4_gate_ick"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - }; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - clock@e00 { - compatible = "ti,clksel"; - reg = <0xe00>; - #clock-cells = <2>; - #address-cells = <0>; - - dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss1_alwon_fck_3430es1"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - ti,set-rate-parent; - }; - }; - - dss_ick: dss_ick_3430es1@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; - }; - - gfx_3430es1_clkdm: gfx_3430es1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&d2d_26m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; - }; -}; diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi deleted file mode 100644 index 8374532f20e2..000000000000 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ /dev/null @@ -1,310 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP34XX/OMAP36XX clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - security_l4_ick2: security_l4_ick2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - clock@a14 { - compatible = "ti,clksel"; - reg = <0xa14>; - #clock-cells = <2>; - #address-cells = <0>; - - aes1_ick: clock-aes1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "aes1_ick"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - }; - - rng_ick: clock-rng-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "rng_ick"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <2>; - }; - - sha11_ick: clock-sha11-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "sha11_ick"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <1>; - }; - - des1_ick: clock-des1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "des1_ick"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <0>; - }; - - pka_ick: clock-pka-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "pka_ick"; - clocks = <&security_l3_ick>; - ti,bit-shift = <4>; - }; - }; - - /* CM_FCLKEN_CAM */ - clock@f00 { - compatible = "ti,clksel"; - reg = <0xf00>; - #clock-cells = <2>; - #address-cells = <0>; - - cam_mclk: clock-cam-mclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "cam_mclk"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - ti,set-rate-parent; - }; - - csi2_96m_fck: clock-csi2-96m-fck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "csi2_96m_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <1>; - }; - }; - - cam_ick: cam_ick@f10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0f10>; - ti,bit-shift = <0>; - }; - - security_l3_ick: security_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <0>; - - icr_ick: clock-icr-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "icr_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <29>; - }; - - des2_ick: clock-des2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "des2_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <26>; - }; - - mspro_ick: clock-mspro-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mspro_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <23>; - }; - - mailboxes_ick: clock-mailboxes-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mailboxes_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <7>; - }; - - sad2d_ick: clock-sad2d-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "sad2d_ick"; - clocks = <&l3_ick>; - ti,bit-shift = <3>; - }; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - clock@c00 { - compatible = "ti,clksel"; - reg = <0xc00>; - #clock-cells = <2>; - #address-cells = <0>; - - sr1_fck: clock-sr1-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "sr1_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - }; - - sr2_fck: clock-sr2-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "sr2_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - }; - }; - - sr_l4_ick: sr_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll2_fck: dpll2_fck@40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <19>; - ti,max-div = <7>; - reg = <0x0040>; - ti,index-starts-at-one; - }; - - dpll2_ck: dpll2_ck@4 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll2_fck>; - reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; - ti,low-power-stop; - ti,lock; - ti,low-power-bypass; - }; - - dpll2_m2_ck: dpll2_m2_ck@44 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll2_ck>; - ti,max-div = <31>; - reg = <0x0044>; - ti,index-starts-at-one; - }; - - iva2_ck: iva2_ck@0 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&dpll2_m2_ck>; - reg = <0x0000>; - ti,bit-shift = <0>; - }; - - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <0>; - - modem_fck: clock-modem-fck { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "modem_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <31>; - }; - - mspro_fck: clock-mspro-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mspro_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <23>; - }; - }; - - /* CM_ICLKEN3_CORE */ - clock@a18 { - compatible = "ti,clksel"; - reg = <0xa18>; - #clock-cells = <2>; - #address-cells = <0>; - - mad2d_ick: clock-mad2d-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mad2d_ick"; - clocks = <&l3_ick>; - ti,bit-shift = <3>; - }; - }; - -}; - -&cm_clockdomains { - cam_clkdm: cam_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_ick>, <&csi2_96m_fck>; - }; - - iva2_clkdm: iva2_clkdm { - compatible = "ti,clockdomain"; - clocks = <&iva2_ck>; - }; - - dpll2_clkdm: dpll2_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll2_ck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, - <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, - <&rng_ick>, <&mspro_fck>; - }; -}; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi deleted file mode 100644 index 9dbf62797f0f..000000000000 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP34xx/OMAP35xx SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include - -#include "omap3.dtsi" - -/ { - cpus { - cpu: cpu@0 { - /* OMAP343x/OMAP35xx variants OPP1-6 */ - operating-points-v2 = <&cpu0_opp_table>; - - clock-latency = <300000>; /* From legacy driver */ - #cooling-cells = <2>; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - opp1-125000000 { - opp-hz = /bits/ 64 <125000000>; - /* - * we currently only select the max voltage from table - * Table 3-3 of the omap3530 Data sheet (SPRS507F). - * Format is: - */ - opp-microvolt = <975000 975000 975000>; - /* - * first value is silicon revision bit mask - * second one 720MHz Device Identification bit mask - */ - opp-supported-hw = <0xffffffff 3>; - }; - - opp2-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <1075000 1075000 1075000>; - opp-supported-hw = <0xffffffff 3>; - opp-suspend; - }; - - opp3-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1200000 1200000 1200000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp4-550000000 { - opp-hz = /bits/ 64 <550000000>; - opp-microvolt = <1275000 1275000 1275000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp5-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1350000 1350000 1350000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp6-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1350000 1350000 1350000>; - /* only high-speed grade omap3530 devices */ - opp-supported-hw = <0xffffffff 2>; - turbo-mode; - }; - }; - - ocp@68000000 { - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - isp: isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x017c>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x6c>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - bandgap: bandgap@48002524 { - reg = <0x48002524 0x4>; - compatible = "ti,omap34xx-bandgap"; - #thermal-sensor-cells = <0>; - }; - - target-module@480cb000 { - compatible = "ti,sysc-omap3430-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb024 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - clocks = <&sr2_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480cb000 0x001000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap3-smartreflex-core"; - reg = <0 0x400>; - interrupts = <19>; - }; - }; - - target-module@480c9000 { - compatible = "ti,sysc-omap3430-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9024 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - clocks = <&sr1_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480c9000 0x001000>; - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-mpu-iva"; - reg = <0 0x400>; - interrupts = <18>; - }; - }; - - /* - * On omap34xx the OCP registers do not seem to be accessible - * at all unlike on 36xx. Maybe SGX is permanently set to - * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is - * write-only at 0x50000e10. We detect SGX based on the SGX - * revision register instead of the unreadable OCP revision - * register. Also note that on early 34xx es1 revision there - * are also different clocks, but we do not have any dts users - * for it. - */ - sgx_module: target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000014 0x4>; - reg-names = "rev"; - clocks = <&sgx_fck>, <&sgx_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; - - thermal_zones: thermal-zones { - #include "omap3-cpu-thermal.dtsi" - }; -}; - -&ssi { - status = "okay"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; -}; - -&usb_otg_target { - clocks = <&hsotgusb_ick_3430es2>; -}; - -/include/ "omap34xx-omap36xx-clocks.dtsi" -/include/ "omap36xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi deleted file mode 100644 index dcc5cfcd1fe6..000000000000 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - corex2_d3_fck: corex2_d3_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&corex2_fck>; - clock-mult = <1>; - clock-div = <3>; - }; - - corex2_d5_fck: corex2_d5_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&corex2_fck>; - clock-mult = <1>; - clock-div = <5>; - }; -}; -&cm_clocks { - dpll5_ck: dpll5_ck@d04 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; - ti,low-power-stop; - ti,lock; - }; - - dpll5_m2_ck: dpll5_m2_ck@d50 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll5_ck>; - ti,max-div = <31>; - reg = <0x0d50>; - ti,index-starts-at-one; - }; - - sgx_gate_fck: sgx_gate_fck@b00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <1>; - reg = <0x0b00>; - }; - - core_d3_ck: core_d3_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - core_d4_ck: core_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - core_d6_ck: core_d6_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <6>; - }; - - omap_192m_alwon_fck: omap_192m_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_d2_ck: core_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - sgx_mux_fck: sgx_mux_fck@b40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; - reg = <0x0b40>; - }; - - sgx_fck: sgx_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; - }; - - sgx_ick: sgx_ick@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - cpefuse_fck: cpefuse_fck@a08 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a08>; - ti,bit-shift = <0>; - }; - - ts_fck: ts_fck@a08 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_32k_fck>; - reg = <0x0a08>; - ti,bit-shift = <1>; - }; - - usbtll_fck: usbtll_fck@a08 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&dpll5_m2_ck>; - reg = <0x0a08>; - ti,bit-shift = <2>; - }; - - /* CM_ICLKEN3_CORE */ - clock@a18 { - compatible = "ti,clksel"; - reg = <0xa18>; - #clock-cells = <2>; - #address-cells = <0>; - - usbtll_ick: clock-usbtll-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "usbtll_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <2>; - }; - }; - - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <0>; - - mmchs3_ick: clock-mmchs3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mmchs3_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <30>; - }; - }; - - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <0>; - - mmchs3_fck: clock-mmchs3-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mmchs3_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <30>; - }; - }; - - clock@e00 { - compatible = "ti,clksel"; - reg = <0xe00>; - #clock-cells = <2>; - #address-cells = <0>; - - dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clock-output-names = "dss1_alwon_fck_3430es2"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - ti,set-rate-parent; - }; - }; - - dss_ick: dss_ick_3430es2@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-dss-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; - - usbhost_120m_fck: usbhost_120m_fck@1400 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll5_m2_ck>; - reg = <0x1400>; - ti,bit-shift = <1>; - }; - - usbhost_48m_fck: usbhost_48m_fck@1400 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&omap_48m_fck>; - reg = <0x1400>; - ti,bit-shift = <0>; - }; - - usbhost_ick: usbhost_ick@1410 { - #clock-cells = <0>; - compatible = "ti,omap3-dss-interface-clock"; - clocks = <&l4_ick>; - reg = <0x1410>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - dpll5_clkdm: dpll5_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll5_ck>; - }; - - sgx_clkdm: sgx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sgx_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; - }; - - usbhost_clkdm: usbhost_clkdm { - compatible = "ti,clockdomain"; - clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, - <&usbhost_ick>; - }; -}; diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi deleted file mode 100644 index c5fdb2bd765d..000000000000 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP36xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - dpll4_ck: dpll4_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-per-j-type-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; - }; - - dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m5x2_mul_ck>; - ti,bit-shift = <0x1e>; - reg = <0x0d00>; - ti,set-rate-parent; - ti,set-bit-to-disable; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll3_m3x2_mul_ck>; - ti,bit-shift = <0xc>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m3x2_mul_ck>; - ti,bit-shift = <0x1c>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m6x2_mul_ck>; - ti,bit-shift = <0x1f>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - clock@1000 { - compatible = "ti,clksel"; - reg = <0x1000>; - #clock-cells = <2>; - #address-cells = <0>; - - uart4_fck: clock-uart4-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "uart4_fck"; - clocks = <&per_48m_fck>; - ti,bit-shift = <18>; - }; - }; -}; - -&dpll4_m2x2_mul_ck { - clock-mult = <1>; -}; - -&dpll4_m3x2_mul_ck { - clock-mult = <1>; -}; - -&dpll4_m4x2_mul_ck { - ti,clock-mult = <1>; -}; - -&dpll4_m5x2_mul_ck { - ti,clock-mult = <1>; -}; - -&dpll4_m6x2_mul_ck { - clock-mult = <1>; -}; - -&cm_clockdomains { - dpll4_clkdm: dpll4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll4_ck>; - }; - - per_clkdm: per_clkdm { - compatible = "ti,clockdomain"; - clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, - <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, - <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, - <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, - <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, - <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, - <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>, <&uart4_fck>; - }; -}; - -&dpll4_m4_ck { - ti,max-div = <31>; -}; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi deleted file mode 100644 index c94eb86d3da7..000000000000 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP34xx/OMAP36xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <0>; - - ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "ssi_ssr_gate_fck_3430es2"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - }; - }; - - clock@a40 { - compatible = "ti,clksel"; - reg = <0xa40>; - #clock-cells = <2>; - #address-cells = <0>; - - ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "ssi_ssr_div_fck_3430es2"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <0>; - - hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clock-output-names = "hsotgusb_ick_3430es2"; - clocks = <&core_l3_ick>; - ti,bit-shift = <4>; - }; - - ssi_ick: clock-ssi-ick-3430es2 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clock-output-names = "ssi_ick_3430es2"; - clocks = <&ssi_l4_ick>; - ti,bit-shift = <0>; - }; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - clock@c00 { - compatible = "ti,clksel"; - reg = <0xc00>; - #clock-cells = <2>; - #address-cells = <0>; - - usim_gate_fck: clock-usim-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "usim_gate_fck"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - }; - }; - - sys_d2_ck: sys_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_96m_d2_fck: omap_96m_d2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_96m_d4_fck: omap_96m_d4_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <4>; - }; - - omap_96m_d8_fck: omap_96m_d8_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <8>; - }; - - omap_96m_d10_fck: omap_96m_d10_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll5_m2_d4_ck: dpll5_m2_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll5_m2_d8_ck: dpll5_m2_d8_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - dpll5_m2_d16_ck: dpll5_m2_d16_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll5_m2_d20_ck: dpll5_m2_d20_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <20>; - }; - - clock@c40 { - compatible = "ti,clksel"; - reg = <0xc40>; - #clock-cells = <2>; - #address-cells = <0>; - - usim_mux_fck: clock-usim-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "usim_mux_fck"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - ti,index-starts-at-one; - }; - }; - - usim_fck: usim_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usim_gate_fck>, <&usim_mux_fck>; - }; - - clock@c10 { - compatible = "ti,clksel"; - reg = <0xc10>; - #clock-cells = <2>; - #address-cells = <0>; - - usim_ick: clock-usim-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "usim_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <9>; - }; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>, <&usim_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&ssi_ick>; - }; -}; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi deleted file mode 100644 index fff9c3d34193..000000000000 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include - -#include "omap3.dtsi" - -/ { - aliases { - serial3 = &uart4; - }; - - cpus { - /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */ - cpu: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - - vbb-supply = <&abb_mpu_iva>; - clock-latency = <300000>; /* From omap-cpufreq driver */ - #cooling-cells = <2>; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - /* - * we currently only select the max voltage from table - * Table 4-19 of the DM3730 Data sheet (SPRS685B) - * Format is: cpu0-supply: - * vbb-supply: - */ - opp-microvolt = <1012500 1012500 1012500>, - <1012500 1012500 1012500>; - /* - * first value is silicon revision bit mask - * second one is "speed binned" bit mask - */ - opp-supported-hw = <0xffffffff 3>; - opp-suspend; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1200000 1200000>, - <1200000 1200000 1200000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp130-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1325000 1325000 1325000>, - <1325000 1325000 1325000>; - opp-supported-hw = <0xffffffff 3>; - }; - - opp1g-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1375000 1375000 1375000>, - <1375000 1375000 1375000>; - /* only on am/dm37x with speed-binned bit set */ - opp-supported-hw = <0xffffffff 2>; - }; - }; - - opp_supply_mpu_iva: opp_supply { - compatible = "ti,omap-opp-supply"; - ti,absolute-max-voltage-uv = <1375000>; - }; - - ocp@68000000 { - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - abb_mpu_iva: regulator-abb-mpu { - compatible = "ti,abb-v1"; - regulator-name = "abb_mpu_iva"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0x483072f0 0x8>, <0x48306818 0x4>; - reg-names = "base-address", "int-address"; - ti,tranxdone-status-mask = <0x4000000>; - clocks = <&sys_ck>; - ti,settling-time = <30>; - ti,clock-cycles = <8>; - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1012500 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1325000 0 0 0 0 0 - 1375000 1 0 0 0 0 - >; - }; - - omap3_pmx_core2: pinmux@480025a0 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025a0 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - isp: isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x0600>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x2f0>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - bandgap: bandgap@48002524 { - reg = <0x48002524 0x4>; - compatible = "ti,omap36xx-bandgap"; - #thermal-sensor-cells = <0>; - }; - - target-module@480cb000 { - compatible = "ti,sysc-omap3630-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - clocks = <&sr2_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480cb000 0x001000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap3-smartreflex-core"; - reg = <0 0x400>; - interrupts = <19>; - }; - }; - - target-module@480c9000 { - compatible = "ti,sysc-omap3630-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - clocks = <&sr1_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480c9000 0x001000>; - - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-mpu-iva"; - reg = <0 0x400>; - interrupts = <18>; - }; - }; - - /* - * Note that the sysconfig register layout is a subset of the - * "ti,sysc-omap4" type register with just sidle and midle bits - * available while omap34xx has "ti,sysc-omap2" type sysconfig. - */ - sgx_module: target-module@50000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5000fe00 0x4>, - <0x5000fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&sgx_fck>, <&sgx_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; - - thermal_zones: thermal-zones { - #include "omap3-cpu-thermal.dtsi" - }; -}; - -&sdma { - compatible = "ti,omap3630-sdma", "ti,omap-sdma"; -}; - -/* OMAP3630 needs dss_96m_fck for VENC */ -&venc { - clocks = <&dss_tv_fck>, <&dss_96m_fck>; - clock-names = "fck", "tv_dac_clk"; -}; - -&ssi { - status = "okay"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; -}; - -&usb_otg_target { - clocks = <&hsotgusb_ick_3430es2>; -}; - -/include/ "omap34xx-omap36xx-clocks.dtsi" -/include/ "omap36xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi deleted file mode 100644 index 2e13ca11ceea..000000000000 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ /dev/null @@ -1,1790 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - virt_16_8m_ck: virt_16_8m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - osc_sys_ck: osc_sys_ck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; - reg = <0x0d40>; - }; - - sys_ck: sys_ck@1270 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&osc_sys_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1270>; - ti,index-starts-at-one; - }; - - sys_clkout1: sys_clkout1@d70 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&osc_sys_ck>; - reg = <0x0d70>; - ti,bit-shift = <7>; - }; - - dpll3_x2_ck: dpll3_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll3_m2x2_ck: dpll3_m2x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_x2_ck: dpll4_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - corex2_fck: corex2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkup_l4_ick: wkup_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_ck>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&scm_clocks { - /* CONTROL_DEVCONF1 */ - clock@68 { - compatible = "ti,clksel"; - reg = <0x68>; - #clock-cells = <2>; - #address-cells = <0>; - - mcbsp5_mux_fck: clock-mcbsp5-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "mcbsp5_mux_fck"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - }; - - mcbsp3_mux_fck: clock-mcbsp3-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "mcbsp3_mux_fck"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - }; - - mcbsp4_mux_fck: clock-mcbsp4-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "mcbsp4_mux_fck"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - }; - }; - - mcbsp5_fck: mcbsp5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; - }; - - /* CONTROL_DEVCONF0 */ - clock@4 { - compatible = "ti,clksel"; - reg = <0x4>; - #clock-cells = <2>; - #address-cells = <0>; - - mcbsp1_mux_fck: clock-mcbsp1-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "mcbsp1_mux_fck"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - }; - - mcbsp2_mux_fck: clock-mcbsp2-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "mcbsp2_mux_fck"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - }; - }; - - mcbsp1_fck: mcbsp1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; - }; - - mcbsp2_fck: mcbsp2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; - }; - - mcbsp3_fck: mcbsp3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; - }; - - mcbsp4_fck: mcbsp4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; - }; -}; -&cm_clocks { - dummy_apb_pclk: dummy_apb_pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - omap_32k_fck: omap_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12m_ck: virt_12m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13m_ck: virt_13m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_38_4m_ck: virt_38_4m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - dpll4_ck: dpll4_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-per-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; - }; - - dpll4_m2_ck: dpll4_m2_ck@d48 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <63>; - reg = <0x0d48>; - ti,index-starts-at-one; - }; - - dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - omap_96m_alwon_fck: omap_96m_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll3_ck: dpll3_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; - }; - - /* CM_CLKSEL1_EMU */ - clock@1140 { - compatible = "ti,clksel"; - reg = <0x1140>; - #clock-cells = <2>; - #address-cells = <0>; - - dpll3_m3_ck: clock-dpll3-m3 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll3_m3_ck"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; - ti,index-starts-at-one; - }; - - dpll4_m6_ck: clock-dpll4-m6 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll4_m6_ck"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - ti,index-starts-at-one; - }; - - emu_src_mux_ck: clock-emu-src-mux { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "emu_src_mux_ck"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - }; - - pclk_fck: clock-pclk-fck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "pclk_fck"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - ti,index-starts-at-one; - }; - - pclkx2_fck: clock-pclkx2-fck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "pclkx2_fck"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - ti,index-starts-at-one; - }; - - atclk_fck: clock-atclk-fck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "atclk_fck"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: clock-traceclk-src-fck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "traceclk_src_fck"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - }; - - traceclk_fck: clock-traceclk-fck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "traceclk_fck"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - ti,index-starts-at-one; - }; - }; - - dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll3_m3x2_mul_ck>; - ti,bit-shift = <0xc>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - emu_core_alwon_ck: emu_core_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m3x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sys_altclk: sys_altclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - mcbsp_clks: mcbsp_clks { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - core_ck: core_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll1_fck: dpll1_fck@940 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <19>; - ti,max-div = <7>; - reg = <0x0940>; - ti,index-starts-at-one; - }; - - dpll1_ck: dpll1_ck@904 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll1_fck>; - reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; - }; - - dpll1_x2_ck: dpll1_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll1_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll1_x2m2_ck: dpll1_x2m2_ck@944 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll1_x2_ck>; - ti,max-div = <31>; - reg = <0x0944>; - ti,index-starts-at-one; - }; - - cm_96m_fck: cm_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_alwon_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_CLKSEL1_PLL */ - clock@d40 { - compatible = "ti,clksel"; - reg = <0xd40>; - #clock-cells = <2>; - #address-cells = <0>; - - dpll3_m2_ck: clock-dpll3-m2 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll3_m2_ck"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - ti,index-starts-at-one; - }; - - omap_96m_fck: clock-omap-96m-fck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "omap_96m_fck"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - }; - - omap_54m_fck: clock-omap-54m-fck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "omap_54m_fck"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - }; - - omap_48m_fck: clock-omap-48m-fck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "omap_48m_fck"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - }; - }; - - /* CM_CLKSEL_DSS */ - clock@e40 { - compatible = "ti,clksel"; - reg = <0xe40>; - #clock-cells = <2>; - #address-cells = <0>; - - dpll4_m3_ck: clock-dpll4-m3 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll4_m3_ck"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-starts-at-one; - }; - - dpll4_m4_ck: clock-dpll4-m4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll4_m4_ck"; - clocks = <&dpll4_ck>; - ti,max-div = <16>; - ti,index-starts-at-one; - }; - }; - - dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m3x2_mul_ck>; - ti,bit-shift = <0x1c>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - cm_96m_d2_fck: cm_96m_d2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cm_96m_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_12m_fck: omap_12m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll4_m4_ck>; - ti,clock-mult = <2>; - ti,clock-div = <1>; - ti,set-rate-parent; - }; - - dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_mul_ck>; - ti,bit-shift = <0x1d>; - reg = <0x0d00>; - ti,set-bit-to-disable; - ti,set-rate-parent; - }; - - dpll4_m5_ck: dpll4_m5_ck@f40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <63>; - reg = <0x0f40>; - ti,index-starts-at-one; - }; - - dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll4_m5_ck>; - ti,clock-mult = <2>; - ti,clock-div = <1>; - ti,set-rate-parent; - }; - - dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_mul_ck>; - ti,bit-shift = <0x1e>; - reg = <0x0d00>; - ti,set-bit-to-disable; - ti,set-rate-parent; - }; - - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m6_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m6x2_mul_ck>; - ti,bit-shift = <0x1f>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - emu_per_alwon_ck: emu_per_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m6x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_CLKOUT_CTRL */ - clock@d70 { - compatible = "ti,clksel"; - reg = <0xd70>; - #clock-cells = <2>; - #address-cells = <0>; - - clkout2_src_gate_ck: clock-clkout2-src-gate { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "clkout2_src_gate_ck"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - }; - - clkout2_src_mux_ck: clock-clkout2-src-mux { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "clkout2_src_mux_ck"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - }; - - sys_clkout2: clock-sys-clkout2 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "sys_clkout2"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - ti,index-power-of-two; - }; - }; - - clkout2_src_ck: clkout2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; - }; - - mpu_ck: mpu_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll1_x2m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - arm_fck: arm_fck@924 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mpu_ck>; - reg = <0x0924>; - ti,max-div = <2>; - }; - - emu_mpu_alwon_ck: emu_mpu_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mpu_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_CLKSEL_CORE */ - clock@a40 { - compatible = "ti,clksel"; - reg = <0xa40>; - #clock-cells = <2>; - #address-cells = <0>; - - l3_ick: clock-l3-ick { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3_ick"; - clocks = <&core_ck>; - ti,max-div = <3>; - ti,index-starts-at-one; - }; - - l4_ick: clock-l4-ick { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l4_ick"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - ti,index-starts-at-one; - }; - - gpt10_mux_fck: clock-gpt10-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt10_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - }; - - gpt11_mux_fck: clock-gpt11-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt11_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - }; - }; - - /* CM_CLKSEL_WKUP */ - clock@c40 { - compatible = "ti,clksel"; - reg = <0xc40>; - #clock-cells = <2>; - #address-cells = <0>; - - rm_ick: clock-rm-ick { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "rm_ick"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - ti,index-starts-at-one; - }; - - gpt1_mux_fck: clock-gpt1-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt1_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - }; - }; - - /* CM_FCLKEN1_CORE */ - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <0>; - - gpt10_gate_fck: clock-gpt10-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt10_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - }; - - gpt11_gate_fck: clock-gpt11-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt11_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - }; - - mmchs2_fck: clock-mmchs2-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mmchs2_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: clock-mmchs1-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mmchs1_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <24>; - }; - - i2c3_fck: clock-i2c3-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "i2c3_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <17>; - }; - - i2c2_fck: clock-i2c2-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "i2c2_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <16>; - }; - - i2c1_fck: clock-i2c1-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "i2c1_fck"; - clocks = <&core_96m_fck>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: clock-mcbsp5-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "mcbsp5_gate_fck"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - }; - - mcbsp1_gate_fck: clock-mcbsp1-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "mcbsp1_gate_fck"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - }; - - mcspi4_fck: clock-mcspi4-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mcspi4_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: clock-mcspi3-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mcspi3_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: clock-mcspi2-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mcspi2_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: clock-mcspi1-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "mcspi1_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <18>; - }; - - uart2_fck: clock-uart2-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "uart2_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <14>; - }; - - uart1_fck: clock-uart1-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "uart1_fck"; - clocks = <&core_48m_fck>; - ti,bit-shift = <13>; - }; - - hdq_fck: clock-hdq-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "hdq_fck"; - clocks = <&core_12m_fck>; - ti,bit-shift = <22>; - }; - }; - - gpt10_fck: gpt10_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; - }; - - gpt11_fck: gpt11_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; - }; - - core_96m_fck: core_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_48m_fck: core_48m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_12m_fck: core_12m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_12m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_l3_ick: core_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_ICLKEN1_CORE */ - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <0>; - - sdrc_ick: clock-sdrc-ick { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "sdrc_ick"; - clocks = <&core_l3_ick>; - ti,bit-shift = <1>; - }; - - mmchs2_ick: clock-mmchs2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mmchs2_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: clock-mmchs1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mmchs1_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <24>; - }; - - hdq_ick: clock-hdq-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "hdq_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: clock-mcspi4-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcspi4_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: clock-mcspi3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcspi3_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: clock-mcspi2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcspi2_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: clock-mcspi1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcspi1_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <18>; - }; - - i2c3_ick: clock-i2c3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "i2c3_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <17>; - }; - - i2c2_ick: clock-i2c2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "i2c2_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <16>; - }; - - i2c1_ick: clock-i2c1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "i2c1_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <15>; - }; - - uart2_ick: clock-uart2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "uart2_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <14>; - }; - - uart1_ick: clock-uart1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "uart1_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <13>; - }; - - gpt11_ick: clock-gpt11-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt11_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <12>; - }; - - gpt10_ick: clock-gpt10-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt10_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: clock-mcbsp5-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcbsp5_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: clock-mcbsp1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcbsp1_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: clock-omapctrl-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "omapctrl_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <6>; - }; - - aes2_ick: clock-aes2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "aes2_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - }; - - sha12_ick: clock-sha12-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "sha12_ick"; - clocks = <&core_l4_ick>; - ti,bit-shift = <27>; - }; - }; - - gpmc_fck: gpmc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_l4_ick: core_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_FCLKEN_DSS */ - clock@e00 { - compatible = "ti,clksel"; - reg = <0xe00>; - #clock-cells = <2>; - #address-cells = <0>; - - dss_tv_fck: clock-dss-tv-fck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss_tv_fck"; - clocks = <&omap_54m_fck>; - ti,bit-shift = <2>; - }; - - dss_96m_fck: clock-dss-96m-fck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss_96m_fck"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <2>; - }; - - dss2_alwon_fck: clock-dss2-alwon-fck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss2_alwon_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <1>; - }; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - /* CM_FCLKEN_WKUP */ - clock@c00 { - compatible = "ti,clksel"; - reg = <0xc00>; - #clock-cells = <2>; - #address-cells = <0>; - - gpt1_gate_fck: clock-gpt1-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt1_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - }; - - gpio1_dbck: clock-gpio1-dbck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "gpio1_dbck"; - clocks = <&wkup_32k_fck>; - ti,bit-shift = <3>; - }; - - wdt2_fck: clock-wdt2-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "wdt2_fck"; - clocks = <&wkup_32k_fck>; - ti,bit-shift = <5>; - }; - }; - - gpt1_fck: gpt1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; - }; - - wkup_32k_fck: wkup_32k_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_ICLKEN_WKUP */ - clock@c10 { - compatible = "ti,clksel"; - reg = <0xc10>; - #clock-cells = <2>; - #address-cells = <0>; - - wdt2_ick: clock-wdt2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "wdt2_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <5>; - }; - - wdt1_ick: clock-wdt1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "wdt1_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <4>; - }; - - gpio1_ick: clock-gpio1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpio1_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <3>; - }; - - omap_32ksync_ick: clock-omap-32ksync-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "omap_32ksync_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <2>; - }; - - gpt12_ick: clock-gpt12-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt12_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <1>; - }; - - gpt1_ick: clock-gpt1-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt1_ick"; - clocks = <&wkup_l4_ick>; - ti,bit-shift = <0>; - }; - }; - - per_96m_fck: per_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_alwon_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_48m_fck: per_48m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_FCLKEN_PER */ - clock@1000 { - compatible = "ti,clksel"; - reg = <0x1000>; - #clock-cells = <2>; - #address-cells = <0>; - - uart3_fck: clock-uart3-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "uart3_fck"; - clocks = <&per_48m_fck>; - ti,bit-shift = <11>; - }; - - gpt2_gate_fck: clock-gpt2-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt2_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - }; - - gpt3_gate_fck: clock-gpt3-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt3_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - }; - - gpt4_gate_fck: clock-gpt4-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt4_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - }; - - gpt5_gate_fck: clock-gpt5-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt5_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - }; - - gpt6_gate_fck: clock-gpt6-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt6_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - }; - - gpt7_gate_fck: clock-gpt7-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt7_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - }; - - gpt8_gate_fck: clock-gpt8-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt8_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - }; - - gpt9_gate_fck: clock-gpt9-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "gpt9_gate_fck"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - }; - - gpio6_dbck: clock-gpio6-dbck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "gpio6_dbck"; - clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: clock-gpio5-dbck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "gpio5_dbck"; - clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: clock-gpio4-dbck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "gpio4_dbck"; - clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: clock-gpio3-dbck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "gpio3_dbck"; - clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: clock-gpio2-dbck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "gpio2_dbck"; - clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <13>; - }; - - wdt3_fck: clock-wdt3-fck { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "wdt3_fck"; - clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <12>; - }; - - mcbsp2_gate_fck: clock-mcbsp2-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "mcbsp2_gate_fck"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - }; - - mcbsp3_gate_fck: clock-mcbsp3-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "mcbsp3_gate_fck"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - }; - - mcbsp4_gate_fck: clock-mcbsp4-gate-fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clock-output-names = "mcbsp4_gate_fck"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - }; - }; - - /* CM_CLKSEL_PER */ - clock@1040 { - compatible = "ti,clksel"; - reg = <0x1040>; - #clock-cells = <2>; - #address-cells = <0>; - - gpt2_mux_fck: clock-gpt2-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt2_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - }; - - gpt3_mux_fck: clock-gpt3-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt3_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - }; - - gpt4_mux_fck: clock-gpt4-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt4_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - }; - - gpt5_mux_fck: clock-gpt5-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt5_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - }; - - gpt6_mux_fck: clock-gpt6-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt6_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - }; - - gpt7_mux_fck: clock-gpt7-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt7_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - }; - - gpt8_mux_fck: clock-gpt8-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt8_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - }; - - gpt9_mux_fck: clock-gpt9-mux-fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "gpt9_mux_fck"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - }; - }; - - gpt2_fck: gpt2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; - }; - - gpt3_fck: gpt3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; - }; - - gpt4_fck: gpt4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; - }; - - gpt5_fck: gpt5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; - }; - - gpt6_fck: gpt6_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; - }; - - gpt7_fck: gpt7_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; - }; - - gpt8_fck: gpt8_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; - }; - - gpt9_fck: gpt9_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; - }; - - per_32k_alwon_fck: per_32k_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_l4_ick: per_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - /* CM_ICLKEN_PER */ - clock@1010 { - compatible = "ti,clksel"; - reg = <0x1010>; - #clock-cells = <2>; - #address-cells = <0>; - - gpio6_ick: clock-gpio6-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpio6_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <17>; - }; - - gpio5_ick: clock-gpio5-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpio5_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <16>; - }; - - gpio4_ick: clock-gpio4-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpio4_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <15>; - }; - - gpio3_ick: clock-gpio3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpio3_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <14>; - }; - - gpio2_ick: clock-gpio2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpio2_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <13>; - }; - - wdt3_ick: clock-wdt3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "wdt3_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <12>; - }; - - uart3_ick: clock-uart3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "uart3_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <11>; - }; - - uart4_ick: clock-uart4-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "uart4_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <18>; - }; - - gpt9_ick: clock-gpt9-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt9_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <10>; - }; - - gpt8_ick: clock-gpt8-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt8_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <9>; - }; - - gpt7_ick: clock-gpt7-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt7_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <8>; - }; - - gpt6_ick: clock-gpt6-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt6_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <7>; - }; - - gpt5_ick: clock-gpt5-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt5_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <6>; - }; - - gpt4_ick: clock-gpt4-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt4_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <5>; - }; - - gpt3_ick: clock-gpt3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt3_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <4>; - }; - - gpt2_ick: clock-gpt2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "gpt2_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <3>; - }; - - mcbsp2_ick: clock-mcbsp2-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcbsp2_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <0>; - }; - - mcbsp3_ick: clock-mcbsp3-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcbsp3_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <1>; - }; - - mcbsp4_ick: clock-mcbsp4-ick { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "mcbsp4_ick"; - clocks = <&per_l4_ick>; - ti,bit-shift = <2>; - }; - }; - - emu_src_ck: emu_src_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clocks = <&emu_src_mux_ck>; - }; - - secure_32k_fck: secure_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - gpt12_fck: gpt12_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&secure_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - wdt1_fck: wdt1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&secure_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>; - }; - - dpll3_clkdm: dpll3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll3_ck>; - }; - - dpll1_clkdm: dpll1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll1_ck>; - }; - - per_clkdm: per_clkdm { - compatible = "ti,clockdomain"; - clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, - <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, - <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, - <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, - <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, - <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, - <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>; - }; - - emu_clkdm: emu_clkdm { - compatible = "ti,clockdomain"; - clocks = <&emu_src_ck>; - }; - - dpll4_clkdm: dpll4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll4_ck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; - }; -}; diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi deleted file mode 100644 index 801b4f10350c..000000000000 --- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4/5 SoC CPU thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * Contact: Eduardo Valentin - */ - -#include - -cpu_thermal: cpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 0>; - - cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts deleted file mode 100644 index ccf03a743678..000000000000 --- a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "motorola-mapphone-common.dtsi" - -/ { - model = "Motorola Droid Bionic XT875"; - compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4"; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = < - MATRIX_KEY(5, 0, KEY_VOLUMEUP) - MATRIX_KEY(3, 0, KEY_VOLUMEDOWN) - >; -}; - -&i2c1 { - led-controller@38 { - compatible = "ti,lm3532"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x38>; - - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - - ramp-up-us = <1024>; - ramp-down-us = <8193>; - - backlight_led: led@0 { - reg = <0>; - led-sources = <2>; - ti,led-mode = <0>; - label = ":backlight"; - }; - }; -}; - -&i2c4 { - kxtf9: accelerometer@f { - compatible = "kionix,kxtf9"; - reg = <0x0f>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - - rotation-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - }; -}; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts deleted file mode 100644 index e833c21f1c01..000000000000 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "motorola-mapphone-common.dtsi" - -/ { - gpio_keys { - compatible = "gpio-keys"; - - volume_down { - label = "Volume Down"; - gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - - /* - * We use pad 0x4a100116 abe_dmic_din3.gpio_122 as the irq instead - * of the gpio interrupt to avoid lost events in deeper idle states. - */ - slider { - label = "Keypad Slide"; - interrupts-extended = <&omap4_pmx_core 0xd6>; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - }; -}; - -/ { - model = "Motorola Droid 4 XT894"; - compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = < - - /* Row 1 */ - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 6, KEY_2) - MATRIX_KEY(2, 3, KEY_3) - MATRIX_KEY(0, 7, KEY_4) - MATRIX_KEY(0, 4, KEY_5) - MATRIX_KEY(5, 5, KEY_6) - MATRIX_KEY(0, 1, KEY_7) - MATRIX_KEY(0, 5, KEY_8) - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(1, 6, KEY_0) - - /* Row 2 */ - MATRIX_KEY(3, 4, KEY_APOSTROPHE) - MATRIX_KEY(7, 6, KEY_Q) - MATRIX_KEY(7, 7, KEY_W) - MATRIX_KEY(7, 2, KEY_E) - MATRIX_KEY(1, 0, KEY_R) - MATRIX_KEY(4, 4, KEY_T) - MATRIX_KEY(1, 2, KEY_Y) - MATRIX_KEY(6, 7, KEY_U) - MATRIX_KEY(2, 2, KEY_I) - MATRIX_KEY(5, 6, KEY_O) - MATRIX_KEY(3, 7, KEY_P) - MATRIX_KEY(6, 5, KEY_BACKSPACE) - - /* Row 3 */ - MATRIX_KEY(5, 4, KEY_TAB) - MATRIX_KEY(5, 7, KEY_A) - MATRIX_KEY(2, 7, KEY_S) - MATRIX_KEY(7, 0, KEY_D) - MATRIX_KEY(2, 6, KEY_F) - MATRIX_KEY(6, 2, KEY_G) - MATRIX_KEY(6, 6, KEY_H) - MATRIX_KEY(1, 4, KEY_J) - MATRIX_KEY(3, 1, KEY_K) - MATRIX_KEY(2, 1, KEY_L) - MATRIX_KEY(4, 6, KEY_ENTER) - - /* Row 4 */ - MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ - MATRIX_KEY(6, 1, KEY_Z) - MATRIX_KEY(7, 4, KEY_X) - MATRIX_KEY(5, 1, KEY_C) - MATRIX_KEY(1, 7, KEY_V) - MATRIX_KEY(2, 4, KEY_B) - MATRIX_KEY(4, 1, KEY_N) - MATRIX_KEY(1, 1, KEY_M) - MATRIX_KEY(3, 5, KEY_COMMA) - MATRIX_KEY(5, 2, KEY_DOT) - MATRIX_KEY(6, 3, KEY_UP) - MATRIX_KEY(7, 3, KEY_OK) - - /* Row 5 */ - MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ - MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ - MATRIX_KEY(6, 0, KEY_MINUS) - MATRIX_KEY(4, 7, KEY_EQUAL) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(3, 2, KEY_SLASH) - MATRIX_KEY(4, 3, KEY_LEFT) - MATRIX_KEY(5, 3, KEY_DOWN) - MATRIX_KEY(3, 3, KEY_RIGHT) - - /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ - MATRIX_KEY(5, 0, KEY_VOLUMEUP) - >; -}; - -&i2c1 { - led-controller@38 { - compatible = "ti,lm3532"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x38>; - - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - - ramp-up-us = <1024>; - ramp-down-us = <8193>; - - backlight_led: led@0 { - reg = <0>; - led-sources = <2>; - ti,led-mode = <0>; - label = ":backlight"; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - ti,led-mode = <0>; - label = ":kbd_backlight"; - }; - }; -}; - -&i2c4 { - lis3dh: accelerometer@18 { - compatible = "st,lis3dh-accel"; - reg = <0x18>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ - - rotation-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - }; -}; diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts deleted file mode 100644 index 6d1beb453234..000000000000 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ -/dts-v1/; - -#include "omap4-duovero.dtsi" - -#include - -/ { - model = "OMAP4430 Gumstix Duovero on Parlor"; - compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - - aliases { - display0 = &hdmi0; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "duovero:blue:led0"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - wakeup-source; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "d"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-0 = < - &led_pins - &button_pins - &smsc_pins - >; - - led_pins: led-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - smsc_pins: smsc-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ - OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ - OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ - >; - }; - - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* optional 1K EEPROM with revision information */ - eeprom@51 { - compatible = "atmel,24c01"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&mmc3 { - status = "disabled"; -}; - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ - - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ - - phy-mode = "mii"; - - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <50>; - gpmc,cs-wr-off-ns = <50>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <50>; - gpmc,we-on-ns = <15>; - gpmc,we-off-ns = <50>; - gpmc,rd-cycle-ns = <50>; - gpmc,wr-cycle-ns = <50>; - gpmc,access-ns = <50>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <35>; - gpmc,cycle2cycle-delay-ns = <35>; - gpmc,wr-data-mux-bus-ns = <35>; - gpmc,wr-access-ns = <50>; - - gpmc,mux-add-data = <2>; - gpmc,sync-read; - gpmc,sync-write; - gpmc,clk-activation-ns = <5>; - gpmc,sync-clk-ps = <20000>; - }; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&vdac>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi deleted file mode 100644 index b8af455b411a..000000000000 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -#include "omap443x.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - model = "Gumstix Duovero"; - compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - - chosen { - stdout-path = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - sound { - compatible = "ti,abe-twl6040"; - ti,model = "DuoVero"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias"; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - #phy-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1phy_pins>; - - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* regulator for w2cbw0015 on sdio5 */ - w2cbw0015_vmmc: w2cbw0015_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&w2cbw0015_pins>; - compatible = "regulator-fixed"; - regulator-name = "w2cbw0015"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ - startup-delay-us = <70000>; - enable-active-high; - regulator-boot-on; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6040_pins - &hsusbb1_pins - >; - - twl6040_pins: twl6040-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcbsp1_pins: mcbsp1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - hsusbb1_pins: hsusbb1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - hsusb1phy_pins: hsusb1phy-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ - >; - }; - - w2cbw0015_pins: w2cbw0015-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ - OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ - OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc5_pins: mmc5-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ - >; - }; -}; - -/* PMIC */ -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -/* on-board bluetooth / WiFi module */ -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - vmmc-supply = <&vmmc>; - ti,bus-width = <4>; - ti,non-removable; /* FIXME: use PMIC_MMC detect */ -}; - -&mmc2 { - status = "disabled"; -}; - -/* mmc3 is available to the expansion board */ - -&mmc4 { - status = "disabled"; -}; - -/* on-board WiFi module */ -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc5_pins>; - - vmmc-supply = <&w2cbw0015_vmmc>; - ti,bus-width = <4>; - ti,non-removable; - cap-power-off-card; - keep-power-in-suspend; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - diff --git a/arch/arm/boot/dts/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/omap4-epson-embt2ws.dts deleted file mode 100644 index e119e2cccc4e..000000000000 --- a/arch/arm/boot/dts/omap4-epson-embt2ws.dts +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2023 Andreas Kemnade - */ -/dts-v1/; - -#include -#include "omap4460.dtsi" - -/ { - model = "Epson Moverio BT-200"; - compatible = "epson,embt2ws", "ti,omap4460", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1024M */ - }; - - backlight-left { - compatible = "pwm-backlight"; - pwms = <&twl_pwm 1 7812500>; - power-supply = <&unknown_supply>; - }; - - backlight-right { - compatible = "pwm-backlight"; - pwms = <&twl_pwm 0 7812500>; - power-supply = <&unknown_supply>; - }; - - chosen { - stdout-path = &uart3; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - - key-lock { - label = "Lock"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; /* SW_TOUCHPAD_LOCK */ - linux,input-type = ; - }; - }; - - unknown_supply: unknown-supply { - compatible = "regulator-fixed"; - regulator-name = "unknown"; - }; - - /* regulator for wl12xx on sdio2 */ - wl12xx_vmmc: wl12xx-vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: pmic@48 { - compatible = "ti,twl6032"; - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - ldo2: regulator-ldo2 { - compatible = "ti,twl6032-ldo2"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo4: regulator-ldo4 { - compatible = "ti,twl6032-ldo4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - }; - - ldo3: regulator-ldo3 { - compatible = "ti,twl6032-ldo3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo5: regulator-ldo5 { - compatible = "ti,twl6032-ldo5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - ti,retain-on-reset; - }; - - ldo1: regulator-ldo1 { - compatible = "ti,twl6032-ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - }; - - ldo7: regulator-ldo7 { - compatible = "ti,twl6032-ldo7"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2900000>; - }; - - ldoln: regulator-ldoln { - compatible = "ti,twl6032-ldoln"; - regulator-always-on; - }; - - ldo6: regulator-ldo6 { - compatible = "ti,twl6032-ldo6"; - regulator-always-on; - }; - - ldousb: regulator-ldousb { - compatible = "ti,twl6032-ldousb"; - regulator-always-on; - }; - - vio: regulator-vio { - compatible = "ti,twl6032-vio"; - regulator-always-on; - }; - - twl_usb_comparator: usb-comparator { - compatible = "ti,twl6030-usb"; - interrupts = <4>, <10>; - }; - - twl_pwm: pwm { - /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - /* provides one PWM (id 0 for Charging indicator LED) */ - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; - }; - - gpadc { - compatible = "ti,twl6032-gpadc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; - - }; -}; - -#include "twl6030_omap4.dtsi" - -&twl_usb_comparator { - usb-supply = <&ldousb>; -}; - - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <200000>; - - /* at head/glasses */ - mpu9150h: imu@68 { - compatible = "invensense,mpu9150"; - reg = <0x68>; - - pinctrl-names = "default"; - pinctrl-0 = <&mpu9150h_pins>; - interrupt-parent = <&gpio2>; - interrupt = <19 IRQ_TYPE_LEVEL_HIGH>; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* TODO: BD2606MVV at 0x66 */ -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <360000>; - - /* TODO: KXTI9 at 0xf */ - - tlv320aic3x: codec@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - pinctrl-names = "default"; - pinctrl-0 = <&tlv320aic3x_pins>; - #sound-dai-cells = <0>; - - reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - }; - - /* TODO: mpu9150 at control unit, seems to require quirks */ -}; - -&keypad { - pinctrl-names = "default"; - pinctrl-0 = <&keypad_pins>; - keypad,num-rows = <2>; - keypad,num-columns = <3>; - linux,keymap = ; - linux,input-no-autorepeat; -}; - -&mcbsp2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - - -&mmc1 { - /* sdcard */ - vmmc-supply = <&ldo5>; - broken-cd; - bus-width = <4>; -}; - -&mmc2 { - /* emmc */ - vmmc-supply = <&ldo2>; - bus-width = <8>; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x12e>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1283"; - reg = <2>; - interrupts-extended = <&gpio1 23 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&omap4_pmx_core { - bt_pins: pinmux-bt-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE3) /* gpio25 */ - >; - }; - - gpio_keys_pins: pinmux-gpio-key-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x56, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio35 */ - >; - }; - - i2c1_pins: pinmux-i2c1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux-i2c2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux-i2c3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux-i2c4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ - >; - }; - - keypad_pins: pinmux-keypad-pins { - pinctrl-single,pins = < - /* kpd_row0 */ - OMAP4_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE1) - /* kpd_row1 */ - OMAP4_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE1) - /* kpd_row2 */ - OMAP4_IOPAD(0x0054, PIN_INPUT_PULLUP | MUX_MODE1) - /* kpd_col0 */ - OMAP4_IOPAD(0x0058, PIN_OUTPUT | MUX_MODE1) - /* kpd_col1 */ - OMAP4_IOPAD(0x005a, PIN_OUTPUT | MUX_MODE1) - /* kpd_col2 */ - OMAP4_IOPAD(0x005c, PIN_OUTPUT | MUX_MODE1) - >; - }; - - mcbsp2_pins: pinmux-mcbsp2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ - >; - }; - - mpu9150h_pins: pinmux-mpu9150h-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x76, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - tlv320aic3x_pins: pinmux-tlv320aic3x-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x7e, PIN_OUTPUT | MUX_MODE3) - >; - }; - - uart2_pins: pinmux-uart2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux-uart3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - usb_otg_hs_pins: pinmux-usb-otg-hs-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ - >; - }; - - wl12xx_pins: pinmux-wl12xx-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1c6, PIN_INPUT | MUX_MODE3) /* gpio_23 / IRQ */ - OMAP4_IOPAD(0x16c, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat2 */ - OMAP4_IOPAD(0x16e, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat1 */ - OMAP4_IOPAD(0x170, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat0 */ - OMAP4_IOPAD(0x172, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat3 */ - OMAP4_IOPAD(0x174, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_cmd */ - OMAP4_IOPAD(0x176, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_clk */ - >; - }; - - wl12xx_gpio: pinmux-wl12xx-gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE3) /* gpio_24 / WLAN_EN */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins &bt_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; - - /* - * BT + GPS in WL1283 in WG7500 requiring CLK32KAUDIO of pmic - * which does not have a driver - */ -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/omap4-kc1.dts deleted file mode 100644 index c6b79ba8bbc9..000000000000 --- a/arch/arm/boot/dts/omap4-kc1.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Paul Kocialkowski - */ -/dts-v1/; - -#include "omap443x.dtsi" - -/ { - model = "Amazon Kindle Fire (first generation)"; - compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "green"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - led-2 { - label = "orange"; - pwms = <&twl_pwm 1 7812500>; - max-brightness = <127>; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ - OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ - OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */ - OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */ - OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */ - OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */ - OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */ - OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */ - OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */ - OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ - >; - }; - - usb_otg_hs_pins: usb-otg-hs-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ - >; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - - twl_power: power { - compatible = "ti,twl6030-power"; - ti,system-power-controller; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - vmmc-supply = <&vaux1>; - ti,non-removable; - bus-width = <8>; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi deleted file mode 100644 index 7ae8b620515c..000000000000 --- a/arch/arm/boot/dts/omap4-l4-abe.dtsi +++ /dev/null @@ -1,497 +0,0 @@ -&l4_abe { /* 0x40100000 */ - compatible = "ti,omap4-l4-abe", "simple-pm-bus"; - reg = <0x40100000 0x400>, - <0x40100400 0x400>; - reg-names = "la", "ap"; - power-domains = <&prm_abe>; - /* OMAP4_L4_ABE_CLKCTRL is read-only */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ - <0x49000000 0x49000000 0x100000>; - segment@0 { /* 0x40100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = - /* CPU to L4 ABE mapping */ - <0x00000000 0x00000000 0x000400>, /* ap 0 */ - <0x00000400 0x00000400 0x000400>, /* ap 1 */ - <0x00022000 0x00022000 0x001000>, /* ap 2 */ - <0x00023000 0x00023000 0x001000>, /* ap 3 */ - <0x00024000 0x00024000 0x001000>, /* ap 4 */ - <0x00025000 0x00025000 0x001000>, /* ap 5 */ - <0x00026000 0x00026000 0x001000>, /* ap 6 */ - <0x00027000 0x00027000 0x001000>, /* ap 7 */ - <0x00028000 0x00028000 0x001000>, /* ap 8 */ - <0x00029000 0x00029000 0x001000>, /* ap 9 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ - <0x00030000 0x00030000 0x001000>, /* ap 14 */ - <0x00031000 0x00031000 0x001000>, /* ap 15 */ - <0x00032000 0x00032000 0x001000>, /* ap 16 */ - <0x00033000 0x00033000 0x001000>, /* ap 17 */ - <0x00038000 0x00038000 0x001000>, /* ap 18 */ - <0x00039000 0x00039000 0x001000>, /* ap 19 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ - <0x00080000 0x00080000 0x010000>, /* ap 26 */ - <0x00080000 0x00080000 0x001000>, /* ap 27 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ - <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ - <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ - <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ - <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ - - /* L3 to L4 ABE mapping */ - <0x49000000 0x49000000 0x000400>, /* ap 0 */ - <0x49000400 0x49000400 0x000400>, /* ap 1 */ - <0x49022000 0x49022000 0x001000>, /* ap 2 */ - <0x49023000 0x49023000 0x001000>, /* ap 3 */ - <0x49024000 0x49024000 0x001000>, /* ap 4 */ - <0x49025000 0x49025000 0x001000>, /* ap 5 */ - <0x49026000 0x49026000 0x001000>, /* ap 6 */ - <0x49027000 0x49027000 0x001000>, /* ap 7 */ - <0x49028000 0x49028000 0x001000>, /* ap 8 */ - <0x49029000 0x49029000 0x001000>, /* ap 9 */ - <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ - <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ - <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ - <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ - <0x49030000 0x49030000 0x001000>, /* ap 14 */ - <0x49031000 0x49031000 0x001000>, /* ap 15 */ - <0x49032000 0x49032000 0x001000>, /* ap 16 */ - <0x49033000 0x49033000 0x001000>, /* ap 17 */ - <0x49038000 0x49038000 0x001000>, /* ap 18 */ - <0x49039000 0x49039000 0x001000>, /* ap 19 */ - <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ - <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ - <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ - <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ - <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ - <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ - <0x49080000 0x49080000 0x010000>, /* ap 26 */ - <0x49080000 0x49080000 0x001000>, /* ap 27 */ - <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ - <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ - <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ - <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ - <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ - <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ - - target-module@22000 { /* 0x40122000, ap 2 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2208c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>, - <0x49022000 0x49022000 0x1000>; - - mcbsp1: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x40124000, ap 4 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2408c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>, - <0x49024000 0x49024000 0x1000>; - - mcbsp2: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x40126000, ap 6 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>, - <0x49026000 0x49026000 0x1000>; - - mcbsp3: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x40128000, ap 8 08.0 */ - /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc-mcasp", "ti,sysc"; - reg = <0x28000 0x4>, - <0x28004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>, - <0x2000 0x2a000 0x1000>, - <0x4902a000 0x4902a000 0x1000>; - - mcasp0: mcasp@0 { - compatible = "ti,omap4-mcasp-audio"; - reg = <0x0 0x2000>, - <0x4902a000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = ; - interrupt-names = "tx"; - dmas = <&sdma 8>; - dma-names = "tx"; - clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; - clock-names = "fck"; - op-mode = <1>; /* MCASP_DIT_MODE */ - serial-dir = < 1 >; /* 1 TX serializers */ - status = "disabled"; - }; - }; - - target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>, - <0x4902e000 0x4902e000 0x1000>; - - dmic: dmic@0 { - compatible = "ti,omap4-dmic"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x40130000, ap 14 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x30000 0x4>, - <0x30010 0x4>, - <0x30014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>, - <0x49030000 0x49030000 0x1000>; - - wdt3: wdt@0 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>, - <0x49032000 0x49032000 0x1000>; - - /* Must be only enabled for boards with pdmclk wired */ - status = "disabled"; - - mcpdm: mcpdm@0 { - compatible = "ti,omap4-mcpdm"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - }; - }; - - target-module@38000 { /* 0x40138000, ap 18 12.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x38000 0x4>, - <0x38010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>, - <0x49038000 0x49038000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, - <&syc_clk_div_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>, - <0x4903a000 0x4903a000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, - <&syc_clk_div_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>, - <0x4903c000 0x4903c000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, - <&syc_clk_div_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>, - <0x4903e000 0x4903e000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, - <&syc_clk_div_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - ti,timer-dsp; - }; - }; - - target-module@80000 { /* 0x40180000, ap 26 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>, - <0x49080000 0x49080000 0x10000>; - }; - - target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>, - <0x490a0000 0x490a0000 0x10000>; - }; - - target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x10000>, - <0x490c0000 0x490c0000 0x10000>; - }; - - target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf1000 0x4>, - <0xf1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf1000 0x1000>, - <0x490f1000 0x490f1000 0x1000>; - - /* - * No child device binding or driver in mainline. - * See Android tree and related upstreaming efforts - * for the old driver. - */ - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi deleted file mode 100644 index 46b8f9efd413..000000000000 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ /dev/null @@ -1,2483 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap4-l4-cfg", "simple-pm-bus"; - power-domains = <&prm_core>; - clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ - <0x00080000 0x4a080000 0x080000>, /* segment 1 */ - <0x00100000 0x4a100000 0x080000>, /* segment 2 */ - <0x00180000 0x4a180000 0x080000>, /* segment 3 */ - <0x00200000 0x4a200000 0x080000>, /* segment 4 */ - <0x00280000 0x4a280000 0x080000>, /* segment 5 */ - <0x00300000 0x4a300000 0x080000>; /* segment 6 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00002000 0x00002000 0x001000>, /* ap 3 */ - <0x00003000 0x00003000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 5 */ - <0x00005000 0x00005000 0x001000>, /* ap 6 */ - <0x00056000 0x00056000 0x001000>, /* ap 7 */ - <0x00057000 0x00057000 0x001000>, /* ap 8 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ - <0x00058000 0x00058000 0x004000>, /* ap 10 */ - <0x00062000 0x00062000 0x001000>, /* ap 11 */ - <0x00063000 0x00063000 0x001000>, /* ap 12 */ - <0x00008000 0x00008000 0x002000>, /* ap 23 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ - <0x00066000 0x00066000 0x001000>, /* ap 25 */ - <0x00067000 0x00067000 0x001000>, /* ap 26 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ - <0x00060000 0x00060000 0x001000>, /* ap 81 */ - <0x00064000 0x00064000 0x001000>, /* ap 86 */ - <0x00065000 0x00065000 0x001000>; /* ap 87 */ - - target-module@2000 { /* 0x4a002000, ap 3 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - omap4_scm_core: scm@0 { - compatible = "ti,omap4-scm-core", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - - omap_control_usb2phy: control-phy@300 { - compatible = "ti,control-phy-usb2"; - reg = <0x300 0x4>; - reg-names = "power"; - }; - - omap_control_usbotg: control-phy@33c { - compatible = "ti,control-phy-otghs"; - reg = <0x33c 0x4>; - reg-names = "otghs_control"; - }; - }; - }; - - target-module@4000 { /* 0x4a004000, ap 5 02.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - cm1: cm1@0 { - compatible = "ti,omap4-cm1", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm1_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 23 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm2: cm2@0 { - compatible = "ti,omap4-cm2", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm2_clockdomains: clockdomains { - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ - clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58000 0x4>, - <0x58010 0x4>, - <0x58014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58000 0x5000>; - - hsi: hsi@0 { - compatible = "ti,omap4-hsi"; - reg = <0x0 0x4000>, - <0x5000 0x1000>; - reg-names = "sys", "gdd"; - - clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; - clock-names = "hsi_fck"; - - interrupts = ; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x4000>; - - hsi_port1: hsi-port@2000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x2000 0x800>, - <0x2800 0x800>; - reg-names = "tx", "rx"; - interrupts = ; - }; - - hsi_port2: hsi-port@3000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x3000 0x800>, - <0x3800 0x800>; - reg-names = "tx", "rx"; - interrupts = ; - }; - }; - }; - - target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@62000 { /* 0x4a062000, ap 11 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x62000 0x4>, - <0x62010 0x4>, - <0x62014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - usbhstll: usbhstll@0 { - compatible = "ti,usbhs-tll"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x64000 0x4>, - <0x64010 0x4>, - <0x64014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - usbhshost: usbhshost@0 { - compatible = "ti,usbhs-host"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - clocks = <&init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@800 { - compatible = "ti,ohci-omap3"; - reg = <0x800 0x400>; - interrupts = ; - remote-wakeup-connected; - }; - - usbhsehci: ehci@c00 { - compatible = "ti,ehci-omap"; - reg = <0xc00 0x400>; - interrupts = ; - }; - }; - }; - - target-module@66000 { /* 0x4a066000, ap 25 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66000 0x4>, - <0x66010 0x4>, - <0x66014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ - clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; - clock-names = "fck"; - power-domains = <&prm_tesla>; - resets = <&prm_tesla 1>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - mmu_dsp: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - }; - }; - }; - - segment@80000 { /* 0x4a080000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ - <0x0005a000 0x000da000 0x001000>, /* ap 14 */ - <0x0005b000 0x000db000 0x001000>, /* ap 15 */ - <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ - <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ - <0x0005e000 0x000de000 0x001000>, /* ap 18 */ - <0x00060000 0x000e0000 0x001000>, /* ap 19 */ - <0x00061000 0x000e1000 0x001000>, /* ap 20 */ - <0x00074000 0x000f4000 0x001000>, /* ap 27 */ - <0x00075000 0x000f5000 0x001000>, /* ap 28 */ - <0x00076000 0x000f6000 0x001000>, /* ap 29 */ - <0x00077000 0x000f7000 0x001000>, /* ap 30 */ - <0x00036000 0x000b6000 0x001000>, /* ap 69 */ - <0x00037000 0x000b7000 0x001000>, /* ap 70 */ - <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ - <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ - <0x00029000 0x000a9000 0x001000>, /* ap 82 */ - <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ - <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ - <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ - <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ - <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ - - target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x29000 0x1000>; - }; - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2b000 0x1000>; - - usb_otg_hs: usb_otg_hs@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = , ; - interrupt-names = "mc", "dma"; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ctrl-module = <&omap_control_usbotg>; - }; - }; - - target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2d000 0x4>, - <0x2d010 0x4>, - <0x2d014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2d000 0x1000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - reg = <0x0 0x1f>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - usb2_phy: usb2phy@80 { - compatible = "ti,omap-usb2"; - reg = <0x80 0x58>; - ctrl-module = <&omap_control_usb2phy>; - clocks = <&usb_phy_cm_clk32k>; - clock-names = "wkupclk"; - #phy-cells = <0>; - }; - }; - }; - - /* d2d mdm */ - target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>, - <0x36014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ - clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - /* d2d mpu */ - target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4d000 0x4>, - <0x4d010 0x4>, - <0x4d014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ - clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000 0x1000>; - }; - - target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - reg = <0x59038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - smartreflex_mpu: smartreflex@0 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - reg = <0x5b038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - smartreflex_iva: smartreflex@0 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - reg = <0x5d038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - }; - - target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x74000 0x4>, - <0x74010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox-ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - }; - - target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x76000 0x4>, - <0x76010 0x4>, - <0x76014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ - <0x00001000 0x00101000 0x001000>, /* ap 22 */ - <0x00002000 0x00102000 0x001000>, /* ap 61 */ - <0x00003000 0x00103000 0x001000>, /* ap 62 */ - <0x00008000 0x00108000 0x001000>, /* ap 63 */ - <0x00009000 0x00109000 0x001000>, /* ap 64 */ - <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ - <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ - - target-module@0 { /* 0x4a100000, ap 21 2a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - omap4_pmx_core: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: omap4_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0x170>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0x170>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap4", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - }; - - target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 63 62.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>, - <0xa010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,sysc-delay-us = <2>; - /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ - clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - /* No child device binding or driver in mainline */ - }; - }; - - segment@180000 { /* 0x4a180000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ - <0x00004000 0x00204000 0x001000>, /* ap 35 */ - <0x00005000 0x00205000 0x001000>, /* ap 36 */ - <0x00006000 0x00206000 0x001000>, /* ap 37 */ - <0x00007000 0x00207000 0x001000>, /* ap 38 */ - <0x00012000 0x00212000 0x001000>, /* ap 39 */ - <0x00013000 0x00213000 0x001000>, /* ap 40 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ - <0x00010000 0x00210000 0x001000>, /* ap 43 */ - <0x00011000 0x00211000 0x001000>, /* ap 44 */ - <0x00016000 0x00216000 0x001000>, /* ap 45 */ - <0x00017000 0x00217000 0x001000>, /* ap 46 */ - <0x00014000 0x00214000 0x001000>, /* ap 47 */ - <0x00015000 0x00215000 0x001000>, /* ap 48 */ - <0x00018000 0x00218000 0x001000>, /* ap 49 */ - <0x00019000 0x00219000 0x001000>, /* ap 50 */ - <0x00020000 0x00220000 0x001000>, /* ap 51 */ - <0x00021000 0x00221000 0x001000>, /* ap 52 */ - <0x00026000 0x00226000 0x001000>, /* ap 53 */ - <0x00027000 0x00227000 0x001000>, /* ap 54 */ - <0x00028000 0x00228000 0x001000>, /* ap 55 */ - <0x00029000 0x00229000 0x001000>, /* ap 56 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ - <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ - - target-module@4000 { /* 0x4a204000, ap 35 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 43 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 39 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 47 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x4a216000, ap 45 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 49 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 51 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 53 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - }; - - segment@280000 { /* 0x4a280000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ - <0x00040000 0x00340000 0x001000>, /* ap 68 */ - <0x00020000 0x00320000 0x004000>, /* ap 71 */ - <0x00024000 0x00324000 0x002000>, /* ap 72 */ - <0x00026000 0x00326000 0x001000>, /* ap 73 */ - <0x00027000 0x00327000 0x001000>, /* ap 74 */ - <0x00028000 0x00328000 0x001000>, /* ap 75 */ - <0x00029000 0x00329000 0x001000>, /* ap 76 */ - <0x00030000 0x00330000 0x010000>, /* ap 77 */ - <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ - <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ - - l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00020000>, - <0x00020000 0x00020000 0x00004000>, - <0x00024000 0x00024000 0x00002000>, - <0x00026000 0x00026000 0x00001000>, - <0x00027000 0x00027000 0x00001000>, - <0x00028000 0x00028000 0x00001000>, - <0x00029000 0x00029000 0x00001000>, - <0x0002a000 0x0002a000 0x00002000>, - <0x0002c000 0x0002c000 0x00004000>, - <0x00030000 0x00030000 0x00010000>; - }; - }; -}; - -&l4_wkup { /* 0x4a300000 */ - compatible = "ti,omap4-l4-wkup", "simple-pm-bus"; - power-domains = <&prm_wkup>; - clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4a300000 0x800>, - <0x4a300800 0x800>, - <0x4a301000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ - <0x00010000 0x4a310000 0x010000>, /* segment 1 */ - <0x00020000 0x4a320000 0x010000>; /* segment 2 */ - - segment@0 { /* 0x4a300000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ - <0x00004000 0x00004000 0x001000>, /* ap 17 */ - <0x00005000 0x00005000 0x001000>, /* ap 18 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ - - target-module@4000 { /* 0x4a304000, ap 17 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x20>; - }; - }; - - target-module@6000 { /* 0x4a306000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,omap4-prm", "simple-bus"; - reg = <0x0 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - scrm: scrm@0 { - compatible = "ti,omap4-scrm"; - reg = <0x0 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>, - <0xc010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - omap4_scm_wkup: scm@c000 { - compatible = "ti,omap4-scm-wkup"; - reg = <0xc000 0x1000>; - }; - }; - }; - - segment@10000 { /* 0x4a310000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ - <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ - <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ - - gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, - <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4a314000, ap 7 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x8000 0x4>, - <0x8010 0x4>, - <0x8014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xc000 0x4>, - <0xc010 0x4>, - <0xc014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - keypad: keypad@0 { - compatible = "ti,omap4-keypad"; - reg = <0x0 0x80>; - interrupts = ; - reg-names = "mpu"; - }; - }; - - target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xe000 0x4>, - <0xe010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - - omap4_pmx_wkup: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - }; - }; - - segment@20000 { /* 0x4a320000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 23 */ - <0x00001000 0x00021000 0x001000>, /* ap 24 */ - <0x00002000 0x00022000 0x001000>, /* ap 25 */ - <0x00003000 0x00023000 0x001000>, /* ap 26 */ - <0x00004000 0x00024000 0x001000>, /* ap 27 */ - <0x00005000 0x00025000 0x001000>, /* ap 28 */ - <0x00007000 0x00027000 0x000400>, /* ap 29 */ - <0x00008000 0x00028000 0x000800>, /* ap 30 */ - <0x00009000 0x00029000 0x000400>; /* ap 31 */ - - target-module@0 { /* 0x4a320000, ap 23 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@4000 { /* 0x4a324000, ap 27 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a326000, ap 13 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00003000 0x00009000 0x00000400>; - }; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,omap4-l4-per", "simple-pm-bus"; - power-domains = <&prm_l4per>; - clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00040000 0x00040000 0x010000>, /* ap 13 */ - <0x00050000 0x00050000 0x001000>, /* ap 14 */ - <0x00055000 0x00055000 0x001000>, /* ap 15 */ - <0x00056000 0x00056000 0x001000>, /* ap 16 */ - <0x00057000 0x00057000 0x001000>, /* ap 17 */ - <0x00058000 0x00058000 0x001000>, /* ap 18 */ - <0x00059000 0x00059000 0x001000>, /* ap 19 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ - <0x00060000 0x00060000 0x001000>, /* ap 25 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ - <0x00070000 0x00070000 0x001000>, /* ap 32 */ - <0x00071000 0x00071000 0x001000>, /* ap 33 */ - <0x00072000 0x00072000 0x001000>, /* ap 34 */ - <0x00073000 0x00073000 0x001000>, /* ap 35 */ - <0x00061000 0x00061000 0x001000>, /* ap 36 */ - <0x00096000 0x00096000 0x001000>, /* ap 37 */ - <0x00097000 0x00097000 0x001000>, /* ap 38 */ - <0x00076000 0x00076000 0x001000>, /* ap 39 */ - <0x00077000 0x00077000 0x001000>, /* ap 40 */ - <0x00078000 0x00078000 0x001000>, /* ap 41 */ - <0x00079000 0x00079000 0x001000>, /* ap 42 */ - <0x00086000 0x00086000 0x001000>, /* ap 43 */ - <0x00087000 0x00087000 0x001000>, /* ap 44 */ - <0x00088000 0x00088000 0x001000>, /* ap 45 */ - <0x00089000 0x00089000 0x001000>, /* ap 46 */ - <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ - <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ - <0x00098000 0x00098000 0x001000>, /* ap 49 */ - <0x00099000 0x00099000 0x001000>, /* ap 50 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ - <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ - <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ - <0x00090000 0x00090000 0x002000>, /* ap 57 */ - <0x00092000 0x00092000 0x001000>, /* ap 58 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ - <0x00001400 0x00001400 0x000400>, /* ap 81 */ - <0x00001800 0x00001800 0x000400>, /* ap 82 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ - <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 02.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>, - <0x32014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 04.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 0e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - /* Unused DSS L4 access, see L3 instead */ - target-module@40000 { /* 0x48040000, ap 13 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - }; - - target-module@55000 { /* 0x48055000, ap 15 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 19 10.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 25 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@70000 { /* 0x48070000, ap 32 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@72000 { /* 0x48072000, ap 34 30.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@76000 { /* 0x48076000, ap 39 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x76000 0x4>, - <0x76010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - /* No child device binding or driver in mainline */ - }; - - target-module@78000 { /* 0x48078000, ap 41 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x78000 0x4>, - <0x78010 0x4>, - <0x78014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@86000 { /* 0x48086000, ap 43 24.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - reg = <0x86000 0x4>, - <0x86010 0x4>, - <0x86014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@88000 { /* 0x48088000, ap 45 2e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, - <&sys_clkin_ck>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - ; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - }; - }; - - target-module@96000 { /* 0x48096000, ap 37 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x96000 0x1000>; - - mcbsp4: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>; /* L4 Interconnect */ - reg-names = "mpu"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@98000 { /* 0x48098000, ap 49 22.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - }; - - target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9e000 0x1000>; - }; - - target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - des_target: target-module@a5000 { /* 0x480a5000 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa5030 0x4>, - <0xa5034 0x4>, - <0xa5038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa5000 0x00001000>; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - }; - }; - - target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb0000 0x1000>; - }; - - target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xb2000 0x4>, - <0xb2014 0x4>, - <0xb2018 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - ti,no-reset-on-init; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - - hdqw1w: 1w@0 { - compatible = "ti,omap3-1w"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd5000 0x4>, - <0xd5010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - - mmc5: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ - <0x00151000 0x00351000 0x001000>; /* ap 78 */ - - target-module@150000 { /* 0x48350000, ap 77 4c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x150000 0x8>, - <0x150010 0x8>, - <0x150090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x150000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/omap4-mcpdm.dtsi deleted file mode 100644 index 03ade47431fb..000000000000 --- a/arch/arm/boot/dts/omap4-mcpdm.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common omap4 mcpdm configuration - * - * Only include this file if your board has pdmclk wired from the - * pmic to ABE as mcpdm uses an external clock for the module. - */ - -&omap4_pmx_core { - mcpdm_pins: mcpdm-pins { - pinctrl-single,pins = < - /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) - - /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) - - /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) - - /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) - - /* 0x4a10010e abe_clks.abe_clks ah26 */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&mcpdm_module { - /* - * McPDM pads must be muxed at the interconnect target module - * level as the module on the SoC needs external clock from - * the PMIC - */ - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - status = "okay"; -}; - -&mcpdm { - clocks = <&twl6040>; - clock-names = "pdmclk"; -}; diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts deleted file mode 100644 index 8fd076e5d1b0..000000000000 --- a/arch/arm/boot/dts/omap4-panda-a4.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "omap4-panda-common.dtsi" - -/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi deleted file mode 100644 index f528511c2537..000000000000 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ /dev/null @@ -1,607 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include -#include "elpida_ecb240abacn.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dsp_memory_region: dsp-memory@98000000 { - compatible = "shared-dma-pool"; - reg = <0x98000000 0x800000>; - reusable; - status = "okay"; - }; - - ipu_memory_region: ipu-memory@98800000 { - compatible = "shared-dma-pool"; - reg = <0x98800000 0x7000000>; - reusable; - status = "okay"; - }; - }; - - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &dvi0; - display1 = &hdmi0; - ethernet = ðernet; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = < - &led_wkgpio_pins - >; - - led-heartbeat { - label = "pandaboard::status1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-mmc { - label = "pandaboard::status2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys: gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = < - &button_pins - >; - - buttonS2 { - label = "button S2"; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ - linux,code = ; - wakeup-source; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "PandaBoard"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */ - startup-delay-us = <70000>; - enable-active-high; - /* - * boot-on is required along with always-on as the - * regulator framework doesn't enable the regulator - * if boot-on is not there. - */ - regulator-always-on; - regulator-boot-on; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - #phy-cells = <0>; - vcc-supply = <&hsusb1_power>; - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* regulator for wl12xx on sdio5 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tpd12s015: encoder1 { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector1 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins - &tfp410_pins - &dss_hdmi_pins - &tpd12s015_pins - &hsusbb1_pins - >; - - twl6040_pins: twl6040-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcbsp1_pins: mcbsp1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - - OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - - OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - tfp410_pins: tfp410-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ - >; - }; - - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - tpd12s015_pins: tpd12s015-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - hsusbb1_pins: hsusbb1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - /* - * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP - * REVISIT: Are the pull-ups needed for GPIO 48 and 49? - */ - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ - >; - }; - - /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: wl12xx-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ - >; - }; -}; - -&omap4_pmx_wkup { - led_wkgpio_pins: leds-wkpins-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ - OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* IRQ# = 119 */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in their EEPROM as EDID data. - * The EEPROM is connected as I2C slave device. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x10e>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - /* gpio_53 with gpmc_ncs3 pad as wakeup */ - interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>, - <&omap4_pmx_core 0x3a>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <38400000>; - }; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&uart2 { - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&uart4 { - interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART4_RX>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; - -&dss { - status = "okay"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "okay"; - vdd-supply = <&vcxio>; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&dsp { - status = "okay"; - memory-region = <&dsp_memory_region>; - ti,timers = <&timer5>; - ti,watchdog-timers = <&timer6>; -}; - -&ipu { - status = "okay"; - memory-region = <&ipu_memory_region>; - ti,timers = <&timer3>; - ti,watchdog-timers = <&timer9>, <&timer11>; -}; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts deleted file mode 100644 index fe7b156d10ed..000000000000 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap4460.dtsi" -#include "omap4-panda-common.dtsi" - -/ { - model = "TI OMAP4 PandaBoard-ES"; - compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; -}; - -/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ -&sound { - ti,model = "PandaBoardES"; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "AFML", "Line In", - "AFMR", "Line In"; -}; - -/* PandaboardES has external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; - -&omap4_pmx_core { - led_gpio_pins: gpio-led-pmx-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ - >; - }; - - button_pins: button-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ - >; - }; - - bt_pins: bt-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ - OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; -}; - -&led_wkgpio_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; -}; - -&leds { - pinctrl-0 = < - &led_gpio_pins - &led_wkgpio_pins - >; - - led-heartbeat { - gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - }; - led-mmc { - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio_keys { - buttonS2 { - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */ - }; -}; - -&gpio1_target { - ti,no-reset-on-init; -}; - -&wl12xx_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ - >; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins &bt_pins>; - bluetooth: tiwi { - compatible = "ti,wl1271-st"; - enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ - }; -}; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts deleted file mode 100644 index 529d5bcceaaf..000000000000 --- a/arch/arm/boot/dts/omap4-panda.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "omap4-panda-common.dtsi" - -/ { - model = "TI OMAP4 PandaBoard"; - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; -}; diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts deleted file mode 100644 index 869f6279b5be..000000000000 --- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include "omap4-sdp.dts" - -/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts deleted file mode 100644 index b2cb93edbc3a..000000000000 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ /dev/null @@ -1,717 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "elpida_ecb240abacn.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - model = "TI OMAP4 SDP board"; - compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - aliases { - display0 = &lcd0; - display1 = &lcd1; - display2 = &hdmi0; - }; - - vdd_eth: fixedregulator-vdd-eth { - pinctrl-names = "default"; - pinctrl-0 = <&enet_enable_gpio>; - - compatible = "regulator-fixed"; - regulator-name = "VDD_ETH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */ - enable-active-high; - regulator-boot-on; - startup-delay-us = <25000>; - }; - - vbat: fixedregulator-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - regulator-min-microvolt = <3750000>; - regulator-max-microvolt = <3750000>; - regulator-boot-on; - }; - - led-controller-1 { - compatible = "gpio-leds"; - - led-1 { - label = "omap4:green:debug0"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ - }; - - led-2 { - label = "omap4:green:debug1"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ - }; - - led-3 { - label = "omap4:green:debug2"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ - }; - - led-4 { - label = "omap4:green:debug3"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ - }; - - led-5 { - label = "omap4:green:debug4"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ - }; - - led-6 { - label = "omap4:blue:user"; - gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ - }; - - led-7 { - label = "omap4:red:user"; - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ - }; - - led-8 { - label = "omap4:green:user"; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ - }; - }; - - led-controller-2 { - compatible = "pwm-leds"; - - led-9 { - label = "omap4::keypad"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - led-10 { - label = "omap4:green:chrg"; - pwms = <&twl_pwmled 0 7812500>; - max-brightness = <255>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&twl_pwm 1 7812500>; - brightness-levels = < - 0 10 20 30 40 - 50 60 70 80 90 - 100 110 120 127 - >; - default-brightness-level = <13>; - }; - - sound { - compatible = "ti,abe-twl6040"; - ti,model = "SDP4430"; - - ti,jack-detection = <1>; - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - ti,dmic = <&dmic>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Earphone Spk", "EP", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "Vibrator", "VIBRAL", - "Vibrator", "VIBRAR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "MAINMIC", "Main Handset Mic", - "Main Handset Mic", "Main Mic Bias", - "SUBMIC", "Sub Handset Mic", - "Sub Handset Mic", "Main Mic Bias", - "AFML", "Line In", - "AFMR", "Line In", - "DMic", "Digital Mic", - "Digital Mic", "Digital Mic1 Bias"; - }; - - /* regulator for wl12xx on sdio5 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "c"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_hdmi_pins - &tpd12s015_pins - >; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - uart4_pins: uart4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ - OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ - >; - }; - - twl6040_pins: twl6040-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - dmic_pins: dmic-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ - OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ - OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ - OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ - >; - }; - - mcbsp1_pins: mcbsp1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ - >; - }; - - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - tpd12s015_pins: tpd12s015-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: wl12xx-gpio-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ - >; - }; - - /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: wl12xx-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - /* gpio_48 for ENET_ENABLE */ - enet_enable_gpio: enet-enable-gpio-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ - >; - }; - - ks8851_pins: ks8851-pins { - pinctrl-single,pins = < - /* ENET_INT */ - OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ - /* - * Misterious pin which makes the ethernet working - * The legacy board file requested this pin on boot - * (ETH_KS8851_QUART) and set it to high, similarly to - * the ENET_ENABLE pin. - * We could use gpio-hog to keep it high, but let's use - * it as a reset GPIO for ks8851. - */ - OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - - /* regulators for vibra motor */ - vddvibl-supply = <&vbat>; - vddvibr-supply = <&vbat>; - - vibra { - /* Vibra driver, motor resistance parameters */ - ti,vibldrv-res = <8>; - ti,vibrdrv-res = <3>; - ti,viblmotor-res = <10>; - ti,vibrmotor-res = <10>; - }; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - /* - * Temperature Sensor - * https://www.ti.com/lit/ds/symlink/tmp105.pdf - */ - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - }; - - /* - * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf - */ - bh1780@29 { - compatible = "rohm,bh1780"; - reg = <0x29>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - /* - * 3-Axis Digital Compass - * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf - */ - hmc5843@1e { - compatible = "honeywell,hmc5843"; - reg = <0x1e>; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - eth@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ks8851_pins>; - - compatible = "ks8851"; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ - vdd-supply = <&vdd_eth>; - reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - vmmc-supply = <&vaux1>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1281"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x00000012 /* KEY_E */ - 0x00010013 /* KEY_R */ - 0x00020014 /* KEY_T */ - 0x00030066 /* KEY_HOME */ - 0x0004003f /* KEY_F5 */ - 0x000500f0 /* KEY_UNKNOWN */ - 0x00060017 /* KEY_I */ - 0x0007002a /* KEY_LEFTSHIFT */ - 0x01000020 /* KEY_D*/ - 0x01010021 /* KEY_F */ - 0x01020022 /* KEY_G */ - 0x010300e7 /* KEY_SEND */ - 0x01040040 /* KEY_F6 */ - 0x010500f0 /* KEY_UNKNOWN */ - 0x01060025 /* KEY_K */ - 0x0107001c /* KEY_ENTER */ - 0x0200002d /* KEY_X */ - 0x0201002e /* KEY_C */ - 0x0202002f /* KEY_V */ - 0x0203006b /* KEY_END */ - 0x02040041 /* KEY_F7 */ - 0x020500f0 /* KEY_UNKNOWN */ - 0x02060034 /* KEY_DOT */ - 0x0207003a /* KEY_CAPSLOCK */ - 0x0300002c /* KEY_Z */ - 0x0301004e /* KEY_KPLUS */ - 0x03020030 /* KEY_B */ - 0x0303003b /* KEY_F1 */ - 0x03040042 /* KEY_F8 */ - 0x030500f0 /* KEY_UNKNOWN */ - 0x03060018 /* KEY_O */ - 0x03070039 /* KEY_SPACE */ - 0x04000011 /* KEY_W */ - 0x04010015 /* KEY_Y */ - 0x04020016 /* KEY_U */ - 0x0403003c /* KEY_F2 */ - 0x04040073 /* KEY_VOLUMEUP */ - 0x040500f0 /* KEY_UNKNOWN */ - 0x04060026 /* KEY_L */ - 0x04070069 /* KEY_LEFT */ - 0x0500001f /* KEY_S */ - 0x05010023 /* KEY_H */ - 0x05020024 /* KEY_J */ - 0x0503003d /* KEY_F3 */ - 0x05040043 /* KEY_F9 */ - 0x05050072 /* KEY_VOLUMEDOWN */ - 0x05060032 /* KEY_M */ - 0x0507006a /* KEY_RIGHT */ - 0x06000010 /* KEY_Q */ - 0x0601001e /* KEY_A */ - 0x06020031 /* KEY_N */ - 0x0603009e /* KEY_BACK */ - 0x0604000e /* KEY_BACKSPACE */ - 0x060500f0 /* KEY_UNKNOWN */ - 0x06060019 /* KEY_P */ - 0x06070067 /* KEY_UP */ - 0x07000094 /* KEY_PROG1 */ - 0x07010095 /* KEY_PROG2 */ - 0x070200ca /* KEY_PROG3 */ - 0x070300cb /* KEY_PROG4 */ - 0x0704003e /* KEY_F4 */ - 0x070500f0 /* KEY_UNKNOWN */ - 0x07060160 /* KEY_OK */ - 0x0707006c>; /* KEY_DOWN */ - linux,input-no-autorepeat; -}; - -&uart2 { - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART4_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&dmic { - pinctrl-names = "default"; - pinctrl-0 = <&dmic_pins>; - status = "okay"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&dss { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - vdd-supply = <&vcxio>; - - port { - dsi1_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd0: panel@0 { - compatible = "tpo,taal", "panel-dsi-cm"; - reg = <0>; - label = "lcd0"; - - reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; - }; -}; - -&dsi2 { - status = "okay"; - vdd-supply = <&vcxio>; - - port { - dsi2_out_ep: endpoint { - remote-endpoint = <&lcd1_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd1: panel@0 { - compatible = "tpo,taal", "panel-dsi-cm"; - reg = <0>; - label = "lcd1"; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - - port { - lcd1_in: endpoint { - remote-endpoint = <&dsi2_out_ep>; - }; - }; - }; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/omap4-var-dvk-om44.dts deleted file mode 100644 index 84fd17fb0822..000000000000 --- a/arch/arm/boot/dts/omap4-var-dvk-om44.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ -/dts-v1/; - -#include "omap4-var-som-om44.dtsi" -#include "omap4-var-som-om44-wlan.dtsi" -#include "omap4-var-om44customboard.dtsi" - -/ { - model = "Variscite VAR-DVK-OM44"; - compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - - aliases { - display0 = &lcd0; - display1 = &hdmi0; - }; - - lcd0: display { - compatible = "innolux,at070tn83", "panel-dpi"; - label = "lcd"; - panel-timing { - clock-frequency = <33333333>; - - hback-porch = <40>; - hactive = <800>; - hfront-porch = <40>; - hsync-len = <48>; - - vback-porch = <29>; - vactive = <480>; - vfront-porch = <13>; - vsync-len = <3>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "okay"; - vdd-supply = <&vcxio>; -}; diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi deleted file mode 100644 index cadc7e02592b..000000000000 --- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ - -#include - -/ { - aliases { - display0 = &hdmi0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_led_pins>; - - led0 { - label = "var:green:led0"; - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "var:green:led1"; - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - #address-cells = <1>; - #size-cells = <0>; - - user-key@184 { - label = "user"; - gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ - linux,code = ; - wakeup-source; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins>; - label = "hdmi"; - type = "a"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - uart1_pins: uart1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ - OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ - OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ - >; - }; - - mcspi1_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - mcasp_pins: mcsasp-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc5_pins: mmc5-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - gpio_led_pins: gpio-led-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ - OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ - >; - }; - - gpio_key_pins: gpio-key-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ - >; - }; - - ks8851_irq_pins: ks8851-irq-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ - >; - }; - - hdmi_hpd_pins: hdmi-hpd-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - backlight_pins: backlight-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ - >; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - status = "okay"; - - eth@0 { - compatible = "ks8851"; - pinctrl-names = "default"; - pinctrl-0 = <&ks8851_irq_pins>; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ - }; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc5_pins>; - vmmc-supply = <&vbat>; - bus-width = <4>; - cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ - status = "okay"; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi deleted file mode 100644 index de779d2d7c3e..000000000000 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ - -/ { - /* regulator for wl12xx on sdio4 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_ctrl_pins>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* gpio 43 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap4_pmx_core { - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - wl12xx_ctrl_pins: wl12xx-ctrl-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ - OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ - >; - }; - - mmc4_pins: mmc4-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ - OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ - OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ - OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ - OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ - OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&mmc4 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc4_pins>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ - ref-clock-frequency = <38400000>; - }; -}; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi deleted file mode 100644 index 37d56b3010cf..000000000000 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com - */ -#include "omap4460.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - model = "Variscite VAR-SOM-OM44"; - compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "VAR-SOM-OM44"; - - ti,mclk-freq = <38400000>; - ti,mcpdm = <&mcpdm>; - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "AFML", "Line In", - "AFMR", "Line In"; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_phy_clk_pins - &hsusbb1_phy_rst_pins - >; - - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ - vcc-supply = <&vbat>; - #phy-cells = <0>; - - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - vbat: fixedregulator-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - twl6040_pins: twl6040-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - tsc2004_pins: tsc2004-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ - OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - hsusbb1_pins: hsusbb1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - hsusbb1_phy_rst_pins: hsusbb1-phy-rst-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c3_pins: i2c3-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; -}; - -&omap4_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_hub_rst_pins - &lan7500_rst_pins - >; - - hsusbb1_phy_clk_pins: hsusbb1-phy-clk-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ - >; - }; - - hsusbb1_hub_rst_pins: hsusbb1-hub-rst-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ - >; - }; - - lan7500_rst_pins: lan7500-rst-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio 182 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&vusim { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - - clock-frequency = <400000>; - - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ - status = "disabled"; - }; - - tmp105@49 { - compatible = "ti,tmp105"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "microchip,24c32", "atmel,24c32"; - reg = <0x50>; - }; -}; - -&i2c4 { - status = "disabled"; -}; - -&gpmc { - status = "disabled"; -}; - -&mcspi1 { - status = "disabled"; -}; - -&mcspi2 { - status = "disabled"; -}; - -&mcspi3 { - status = "disabled"; -}; - -&mcspi4 { - status = "disabled"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc>; - bus-width = <4>; - ti,non-removable; - status = "okay"; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&keypad { - status = "disabled"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; diff --git a/arch/arm/boot/dts/omap4-var-stk-om44.dts b/arch/arm/boot/dts/omap4-var-stk-om44.dts deleted file mode 100644 index 656fb29c2a15..000000000000 --- a/arch/arm/boot/dts/omap4-var-stk-om44.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ -/dts-v1/; - -#include "omap4-var-som-om44.dtsi" -#include "omap4-var-som-om44-wlan.dtsi" -#include "omap4-var-om44customboard.dtsi" - -/ { - model = "Variscite VAR-STK-OM44"; - compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; -}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi deleted file mode 100644 index 2bbff9032be3..000000000000 --- a/arch/arm/boot/dts/omap4.dtsi +++ /dev/null @@ -1,868 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include -#include -#include - -/ { - compatible = "ti,omap4430", "ti,omap4"; - interrupt-parent = <&wakeupgen>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &mmc1; - mmc1 = &mmc2; - mmc2 = &mmc3; - mmc3 = &mmc4; - mmc4 = &mmc5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - rproc0 = &dsp; - rproc1 = &ipu; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x0>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - /* - * Needed early by omap4_sram_init() for barrier, do not move to l3 - * interconnect as simple-pm-bus probes at module_init() time. - */ - ocmcram: sram@40304000 { - compatible = "mmio-sram"; - reg = <0x40304000 0xa000>; /* 40k */ - }; - - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - interrupt-parent = <&gic>; - }; - - L2: cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - local-timer@48240600 { - compatible = "arm,cortex-a9-twd-timer"; - clocks = <&mpu_periphclk>; - reg = <0x48240600 0x20>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * XXX: Use a flat representation of the OMAP4 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "simple-pm-bus"; - power-domains = <&prm_l4per>; - clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>, - <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>, - <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l3-noc@44000000 { - compatible = "ti,omap4-l3-noc"; - reg = <0x44000000 0x1000>, - <0x44800000 0x2000>, - <0x45000000 0x1000>; - interrupts = , - ; - }; - - l4_wkup: interconnect@4a300000 { - }; - - l4_cfg: interconnect@4a000000 { - }; - - l4_per: interconnect@48000000 { - }; - - target-module@48210000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - power-domains = <&prm_mpu>; - clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48210000 0x1f0000>; - - mpu { - compatible = "ti,omap4-mpu"; - sram = <&ocmcram>; - }; - }; - - l4_abe: interconnect@40100000 { - }; - - target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000000 4>, - <0x50000010 4>, - <0x50000014 4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - ti,no-idle-on-init; - clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ - <0x00000000 0x00000000 0x40000000>; /* data */ - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - clocks = <&l3_div_ck>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - target-module@52000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x52000000 0x4>, - <0x52000010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,sysc-delay-us = <2>; - power-domains = <&prm_cam>; - clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x52000000 0x1000000>; - - /* No child device binding, driver in staging */ - }; - - /* - * Note that 4430 needs cross trigger interface (CTI) supported - * before we can configure the interrupts. This means sampling - * events are not supported for pmu. Note that 4460 does not use - * CTI, see also 4460.dtsi. - */ - target-module@54000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - power-domains = <&prm_emu>; - clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x54000000 0x1000000>; - - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - }; - }; - - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - ranges = <0x0 0x55082000 0x100>; - #size-cells = <1>; - #address-cells = <1>; - - mmu_ipu: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - }; - - target-module@4012c000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4012c000 0x4>, - <0x4012c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ - <0x4902c000 0x4902c000 0x1000>; /* L3 */ - - /* No child device binding or driver in mainline */ - }; - - target-module@4e000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4e000000 0x4>, - <0x4e000010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - ranges = <0x0 0x4e000000 0x2000000>; - #size-cells = <1>; - #address-cells = <1>; - - dmm@0 { - compatible = "ti,omap4-dmm"; - reg = <0 0x800>; - interrupts = ; - }; - }; - - target-module@4c000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x4c000000 0x4>; - reg-names = "rev"; - clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000000 0x1000000>; - - emif1: emif@0 { - compatible = "ti,emif-4d"; - reg = <0 0x100>; - interrupts = ; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - }; - - target-module@4d000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x4d000000 0x4>; - reg-names = "rev"; - clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000000 0x1000000>; - - emif2: emif@0 { - compatible = "ti,emif-4d"; - reg = <0 0x100>; - interrupts = ; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - }; - - dsp: dsp { - compatible = "ti,omap4-dsp"; - ti,bootreg = <&scm_conf 0x304 0>; - iommus = <&mmu_dsp>; - resets = <&prm_tesla 0>; - clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; - firmware-name = "omap4-dsp-fw.xe64T"; - mboxes = <&mailbox &mbox_dsp>; - status = "disabled"; - }; - - ipu: ipu@55020000 { - compatible = "ti,omap4-ipu"; - reg = <0x55020000 0x10000>; - reg-names = "l2ram"; - iommus = <&mmu_ipu>; - resets = <&prm_core 0>, <&prm_core 1>; - clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; - firmware-name = "omap4-ipu-fw.xem3"; - mboxes = <&mailbox &mbox_ipu>; - status = "disabled"; - }; - - aes1_target: target-module@4b501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b501080 0x4>, - <0x4b501084 0x4>, - <0x4b501088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b501000 0x1000>; - - aes1: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; - }; - }; - - aes2_target: target-module@4b701000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b701080 0x4>, - <0x4b701084 0x4>, - <0x4b701088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b701000 0x1000>; - - aes2: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 114>, <&sdma 113>; - dma-names = "tx", "rx"; - }; - }; - - sham_target: target-module@4b100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x4b100100 0x4>, - <0x4b100110 0x4>, - <0x4b100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ - clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap4-sham"; - reg = <0 0x300>; - interrupts = ; - dmas = <&sdma 119>; - dma-names = "rx"; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - ti,tranxdone-status-mask = <0x80>; - clocks = <&sys_clkin_ck>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - status = "disabled"; - }; - - abb_iva: regulator-abb-iva { - compatible = "ti,abb-v2"; - regulator-name = "abb_iva"; - #address-cells = <0>; - #size-cells = <0>; - ti,tranxdone-status-mask = <0x80000000>; - clocks = <&sys_clkin_ck>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - status = "disabled"; - }; - - sgx_module: target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - power-domains = <&prm_gfx>; - clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - - /* - * DSS is only using l3 mapping without l4 as noted in the TRM - * "10.1.3 DSS Register Manual" for omap4460. - */ - target-module@58000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58000000 4>, - <0x58000014 4>; - reg-names = "rev", "syss"; - ti,syss-mask = <1>; - power-domains = <&prm_dss>; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; - clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x58000000 0x1000000>; - - dss: dss@0 { - compatible = "ti,omap4-dss"; - reg = <0 0x80>; - status = "disabled"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000000>; - - target-module@1000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x1000 0x4>, - <0x1010 0x4>, - <0x1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-midle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x1000>; - - dispc@0 { - compatible = "ti,omap4-dispc"; - reg = <0 0x1000>; - interrupts = ; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@2000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2010 0x4>, - <0x2014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - - rfbi: encoder@0 { - reg = <0 0x1000>; - status = "disabled"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; - clock-names = "fck", "ick"; - }; - }; - - target-module@3000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x3000 0x4>; - reg-names = "rev"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "sys_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x3000 0x1000>; - - venc: encoder@0 { - compatible = "ti,omap4-venc"; - reg = <0 0x1000>; - status = "disabled"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; - clock-names = "fck"; - }; - }; - - target-module@4000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4000 0x1000>; - - dsi1: encoder@0 { - compatible = "ti,omap4-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@5000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5000 0x4>, - <0x5010 0x4>, - <0x5014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5000 0x1000>; - - dsi2: encoder@0 { - compatible = "ti,omap4-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@6000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>, - <0x6010 0x4>; - reg-names = "rev", "sysc"; - /* - * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP - * but HDMI audio will fail with them. - */ - ti,sysc-sidle = , - ; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck", "dss_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x6000 0x2000>; - - hdmi: encoder@0 { - compatible = "ti,omap4-hdmi"; - reg = <0 0x200>, - <0x200 0x100>, - <0x300 0x100>, - <0x400 0x1000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - }; - }; - - iva_hd_target: target-module@5a000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5a05a400 0x4>, - <0x5a05a410 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - power-domains = <&prm_ivahd>; - resets = <&prm_ivahd 2>; - reset-names = "rstctrl"; - clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5a000000 0x5a000000 0x1000000>, - <0x5b000000 0x5b000000 0x1000000>; - - iva { - compatible = "ti,ivahd"; - }; - }; - }; -}; - -#include "omap4-l4.dtsi" -#include "omap4-l4-abe.dtsi" -#include "omap44xx-clocks.dtsi" - -&prm { - prm_mpu: prm@300 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x300 0x100>; - #power-domain-cells = <0>; - }; - - prm_tesla: prm@400 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_abe: prm@500 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x500 0x100>; - #power-domain-cells = <0>; - }; - - prm_always_on_core: prm@600 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x600 0x100>; - #power-domain-cells = <0>; - }; - - prm_core: prm@700 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_ivahd: prm@f00 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0xf00 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_cam: prm@1000 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1000 0x100>; - #power-domain-cells = <0>; - }; - - prm_dss: prm@1100 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1100 0x100>; - #power-domain-cells = <0>; - }; - - prm_gfx: prm@1200 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #power-domain-cells = <0>; - }; - - prm_l3init: prm@1300 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1300 0x100>; - #power-domain-cells = <0>; - }; - - prm_l4per: prm@1400 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1400 0x100>; - #power-domain-cells = <0>; - }; - - prm_cefuse: prm@1600 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1600 0x100>; - #power-domain-cells = <0>; - }; - - prm_wkup: prm@1700 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1700 0x100>; - #power-domain-cells = <0>; - }; - - prm_emu: prm@1900 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1900 0x100>; - #power-domain-cells = <0>; - }; - - prm_dss: prm@1100 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1100 0x40>; - #power-domain-cells = <0>; - }; - - prm_device: prm@1b00 { - compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; - reg = <0x1b00 0x40>; - #reset-cells = <1>; - }; -}; - -/* Preferred always-on timer for clockevent */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - assigned-clock-parents = <&sys_32k_ck>; - }; -}; diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi deleted file mode 100644 index 581e088231b5..000000000000 --- a/arch/arm/boot/dts/omap443x-clocks.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - bandgap_fclk: bandgap_fclk@1888 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "bandgap_fclk"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1888>; - }; -}; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi deleted file mode 100644 index 238aceb799f8..000000000000 --- a/arch/arm/boot/dts/omap443x.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP443x SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "omap4.dtsi" - -/ { - cpus { - cpu0: cpu@0 { - /* OMAP443x variants OPP50-OPPNT */ - operating-points = < - /* kHz uV */ - 300000 1025000 - 600000 1200000 - 800000 1313000 - 1008000 1375000 - >; - clock-latency = <300000>; /* From legacy driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - }; - - ocp { - /* 4430 has only gpio_86 tshut and no talert interrupt */ - bandgap: bandgap@4a002260 { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4>; - compatible = "ti,omap4430-bandgap"; - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - - #thermal-sensor-cells = <0>; - }; - }; - - ocp { - abb_mpu: regulator-abb-mpu { - status = "okay"; - - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; - reg-names = "base-address", "int-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1313000 0 0 0 0 0 - 1375000 1 0 0 0 0 - 1389000 1 0 0 0 0 - >; - }; - - /* Default unused, just provide register info for record */ - abb_iva: regulator-abb-iva { - reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; - reg-names = "base-address", "int-address"; - }; - - }; - -}; - -&cpu_thermal { - coefficients = <0 20000>; -}; - -/include/ "omap443x-clocks.dtsi" - -/* - * Use dpll_per for sgx at 307.2MHz like droid4 stock v3.0.8 Android kernel - */ -&sgx_module { - assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>, - <&dpll_per_m7x2_ck>; - assigned-clock-rates = <0>, <307200000>; - assigned-clock-parents = <&dpll_per_m7x2_ck>; -}; diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi deleted file mode 100644 index 1b27a862ae81..000000000000 --- a/arch/arm/boot/dts/omap4460.dtsi +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4460 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include "omap4.dtsi" - -/ { - cpus { - /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ - cpu0: cpu@0 { - operating-points = < - /* kHz uV */ - 350000 1025000 - 700000 1200000 - 920000 1313000 - >; - clock-latency = <300000>; /* From legacy driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - }; - - ocp { - bandgap: bandgap@4a002260 { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4 - 0x4a002378 0x18>; - compatible = "ti,omap4460-bandgap"; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */ - - #thermal-sensor-cells = <0>; - }; - - abb_mpu: regulator-abb-mpu { - status = "okay"; - - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, - <0x4A002268 0x4>; - reg-names = "base-address", "int-address", - "efuse-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1313000 0 0 0x100000 0x40000 0 - 1375000 1 0 0 0 0 - 1389000 1 0 0 0 0 - >; - }; - - abb_iva: regulator-abb-iva { - status = "okay"; - - reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, - <0x4A002268 0x4>; - reg-names = "base-address", "int-address", - "efuse-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 950000 0 0 0 0 0 - 1140000 0 0 0 0 0 - 1291000 0 0 0x200000 0 0 - 1375000 1 0 0 0 0 - 1376000 1 0 0 0 0 - >; - }; - }; - -}; - -&cpu_thermal { - coefficients = <348 (-9301)>; -}; - -/* Only some L4 CFG interconnect ranges are different on 4460 */ -&l4_cfg_segment_300000 { - ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ - <0x00040000 0x00340000 0x001000>, /* ap 68 */ - <0x00020000 0x00320000 0x004000>, /* ap 71 */ - <0x00024000 0x00324000 0x002000>, /* ap 72 */ - <0x00026000 0x00326000 0x001000>, /* ap 73 */ - <0x00027000 0x00327000 0x001000>, /* ap 74 */ - <0x00028000 0x00328000 0x001000>, /* ap 75 */ - <0x00029000 0x00329000 0x001000>, /* ap 76 */ - <0x00030000 0x00330000 0x010000>, /* ap 77 */ - <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ - <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ - <0x00010000 0x00310000 0x008000>, /* ap 92 */ - <0x00018000 0x00318000 0x004000>, /* ap 93 */ - <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ - <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ -}; - -&l4_cfg_target_0 { - ranges = <0x00000000 0x00000000 0x00010000>, - <0x00010000 0x00010000 0x00008000>, - <0x00018000 0x00018000 0x00004000>, - <0x0001c000 0x0001c000 0x00002000>, - <0x0001e000 0x0001e000 0x00002000>, - <0x00020000 0x00020000 0x00004000>, - <0x00024000 0x00024000 0x00002000>, - <0x00026000 0x00026000 0x00001000>, - <0x00027000 0x00027000 0x00001000>, - <0x00028000 0x00028000 0x00001000>, - <0x00029000 0x00029000 0x00001000>, - <0x0002a000 0x0002a000 0x00002000>, - <0x0002c000 0x0002c000 0x00004000>, - <0x00030000 0x00030000 0x00010000>; -}; - -&pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; -}; - -/include/ "omap446x-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi deleted file mode 100644 index d9362fef6720..000000000000 --- a/arch/arm/boot/dts/omap446x-clocks.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - div_ts_ck: div_ts_ck@1888 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "div_ts_ck"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <24>; - reg = <0x1888>; - ti,dividers = <8>, <16>, <32>; - }; - - bandgap_ts_fclk: bandgap_ts_fclk@1888 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "bandgap_ts_fclk"; - clocks = <&div_ts_ck>; - ti,bit-shift = <8>; - reg = <0x1888>; - }; -}; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi deleted file mode 100644 index 8df73d285638..000000000000 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ /dev/null @@ -1,1483 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm1_clocks { - extalt_clkin_ck: extalt_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "extalt_clkin_ck"; - clock-frequency = <59000000>; - }; - - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "pad_clks_src_ck"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "pad_clks_ck"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "pad_slimbus_core_clks_ck"; - clock-frequency = <12000000>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "secure_32k_clk_src_ck"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "slimbus_src_clk"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "slimbus_clk"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "sys_32k_ck"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_12000000_ck"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_13000000_ck"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_16800000_ck"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_19200000_ck"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_26000000_ck"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_27000000_ck"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_38400000_ck"; - clock-frequency = <38400000>; - }; - - tie_low_clock_ck: tie_low_clock_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "tie_low_clock_ck"; - clock-frequency = <0>; - }; - - utmi_phy_clkout_ck: utmi_phy_clkout_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "utmi_phy_clkout_ck"; - clock-frequency = <60000000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "xclk60mhsp1_ck"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "xclk60mhsp2_ck"; - clock-frequency = <60000000>; - }; - - xclk60motg_ck: xclk60motg_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "xclk60motg_ck"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clock-output-names = "dpll_abe_ck"; - clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_abe_x2_ck"; - clocks = <&dpll_abe_ck>; - reg = <0x01f0>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m2x2_ck"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "abe_24m_fclk"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_clk"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m3x2_ck"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "core_hsd_byp_clk_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clock-output-names = "dpll_core_ck"; - clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_core_x2_ck"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m6x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0140>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m2_ck"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0130>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - ddrphy_ck: ddrphy_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "ddrphy_ck"; - clocks = <&dpll_core_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m5x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x013c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - div_core_ck: div_core_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "div_core_ck"; - clocks = <&dpll_core_m5x2_ck>; - reg = <0x0100>; - ti,max-div = <2>; - }; - - div_iva_hs_clk: div_iva_hs_clk@1dc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "div_iva_hs_clk"; - clocks = <&dpll_core_m5x2_ck>; - ti,max-div = <4>; - reg = <0x01dc>; - ti,index-power-of-two; - }; - - div_mpu_hs_clk: div_mpu_hs_clk@19c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "div_mpu_hs_clk"; - clocks = <&dpll_core_m5x2_ck>; - ti,max-div = <4>; - reg = <0x019c>; - ti,index-power-of-two; - }; - - dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m4x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0138>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dll_clk_div_ck: dll_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dll_clk_div_ck"; - clocks = <&dpll_core_m4x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m2_ck"; - clocks = <&dpll_abe_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "dpll_core_m3x2_gate_ck"; - clocks = <&dpll_core_x2_ck>; - ti,bit-shift = <8>; - reg = <0x0134>; - }; - - dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "dpll_core_m3x2_div_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "dpll_core_m3x2_ck"; - clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; - }; - - dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m7x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0144>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "iva_hsd_byp_clk_mux_ck"; - clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_iva_ck"; - clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <931200000>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_iva_x2_ck"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_iva_m4x2_ck"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01b8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_iva_m4x2_ck>; - assigned-clock-rates = <465600000>; - }; - - dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_iva_m5x2_ck"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01bc>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_iva_m5x2_ck>; - assigned-clock-rates = <266100000>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_mpu_ck"; - clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_mpu_m2_ck"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0170>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - per_hs_clk_div_ck: per_hs_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "per_hs_clk_div_ck"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_hs_clk_div_ck: usb_hs_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "usb_hs_clk_div_ck"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_div_ck: l3_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3_div_ck"; - clocks = <&div_core_ck>; - ti,bit-shift = <4>; - ti,max-div = <2>; - reg = <0x0100>; - }; - - l4_div_ck: l4_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l4_div_ck"; - clocks = <&l3_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <2>; - reg = <0x0100>; - }; - - lp_clk_div_ck: lp_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "lp_clk_div_ck"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - mpu_periphclk: mpu_periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mpu_periphclk"; - clocks = <&dpll_mpu_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - ocp_abe_iclk: ocp_abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "ocp_abe_iclk"; - clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - per_abe_24m_fclk: per_abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "per_abe_24m_fclk"; - clocks = <&dpll_abe_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "dummy_ck"; - clock-frequency = <0>; - }; -}; - -&prm_clocks { - sys_clkin_ck: sys_clkin_ck@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sys_clkin_ck"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_bypass_clk_mux_ck"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0108>; - }; - - abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_refclk_mux_ck"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - dbgclk_mux_ck: dbgclk_mux_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dbgclk_mux_ck"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "l4_wkup_clk_mux_ck"; - clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; - reg = <0x0108>; - }; - - syc_clk_div_ck: syc_clk_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "syc_clk_div_ck"; - clocks = <&sys_clkin_ck>; - reg = <0x0100>; - ti,max-div = <2>; - }; - - usim_ck: usim_ck@1858 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "usim_ck"; - clocks = <&dpll_per_m4x2_ck>; - ti,bit-shift = <24>; - reg = <0x1858>; - ti,dividers = <14>, <18>; - }; - - usim_fclk: usim_fclk@1858 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usim_fclk"; - clocks = <&usim_ck>; - ti,bit-shift = <8>; - reg = <0x1858>; - }; - - trace_clk_div_ck: trace_clk_div_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clock-output-names = "trace_clk_div_ck"; - clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; - }; -}; - -&prm_clockdomains { - emu_sys_clkdm: emu_sys_clkdm { - compatible = "ti,clockdomain"; - clock-output-names = "emu_sys_clkdm"; - clocks = <&trace_clk_div_ck>; - }; -}; - -&cm2_clocks { - per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "per_hsd_byp_clk_mux_ck"; - clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_per_ck"; - clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2_ck"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_x2_ck: dpll_per_x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_per_x2_ck"; - clocks = <&dpll_per_ck>; - reg = <0x0150>; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "dpll_per_m3x2_gate_ck"; - clocks = <&dpll_per_x2_ck>; - ti,bit-shift = <8>; - reg = <0x0154>; - }; - - dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "dpll_per_m3x2_div_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "dpll_per_m3x2_ck"; - clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; - }; - - dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m4x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m5x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m6x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0160>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m7x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0164>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clock-output-names = "dpll_usb_ck"; - clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clock-output-names = "dpll_usb_clkdcoldo_ck"; - clocks = <&dpll_usb_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x01b4>; - ti,clock-mult = <1>; - ti,invert-autoidle-bit; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_usb_m2_ck"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0190>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - ducati_clk_mux_ck: ducati_clk_mux_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "ducati_clk_mux_ck"; - clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; - reg = <0x0100>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_12m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_24m_clk"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_24mc_fclk: func_24mc_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_24mc_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_48m_fclk: func_48m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "func_48m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - reg = <0x0108>; - ti,dividers = <4>, <8>; - }; - - func_48mc_fclk: func_48mc_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_48mc_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_64m_fclk: func_64m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "func_64m_fclk"; - clocks = <&dpll_per_m4x2_ck>; - reg = <0x0108>; - ti,dividers = <2>, <4>; - }; - - func_96m_fclk: func_96m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "func_96m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - reg = <0x0108>; - ti,dividers = <2>, <4>; - }; - - init_60m_fclk: init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "init_60m_fclk"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - per_abe_nc_fclk: per_abe_nc_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "per_abe_nc_fclk"; - clocks = <&dpll_abe_m2_ck>; - reg = <0x0108>; - ti,max-div = <2>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy_cm_clk32k"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; -}; - -&cm2_clockdomains { - l3_init_clkdm: l3_init_clkdm { - compatible = "ti,clockdomain"; - clock-output-names = "l3_init_clkdm"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk0_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk0_src_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk0_src_ck"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk0_ck"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk1_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk1_src_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk1_src_ck"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk1_ck"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk2_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk2_src_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk2_src_ck"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk2_ck"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk3_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk3_src_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk3_src_ck"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk3_ck"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk4_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk4_src_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk4_src_ck"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk4_ck"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk5_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0324>; - }; - - auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk5_src_mux_ck"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0324>; - }; - - auxclk5_src_ck: auxclk5_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk5_src_ck"; - clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; - }; - - auxclk5_ck: auxclk5_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk5_ck"; - clocks = <&auxclk5_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0324>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq0_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq1_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq2_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq3_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; - - auxclkreq4_ck: auxclkreq4_ck@220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq4_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0220>; - }; - - auxclkreq5_ck: auxclkreq5_ck@224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq5_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0224>; - }; -}; - -&cm1 { - mpuss_cm: mpuss_cm@300 { - compatible = "ti,omap4-cm"; - clock-output-names = "mpuss_cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpuss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "mpuss_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - tesla_cm: tesla_cm@400 { - compatible = "ti,omap4-cm"; - clock-output-names = "tesla_cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - tesla_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "tesla_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - abe_cm: abe_cm@500 { - compatible = "ti,omap4-cm"; - clock-output-names = "abe_cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - abe_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "abe_clkctrl"; - reg = <0x20 0x6c>; - #clock-cells = <2>; - }; - }; - -}; - -&cm2 { - l4_ao_cm: l4_ao_cm@600 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_ao_cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - l4_ao_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_ao_clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l3_1_cm: l3_1_cm@700 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_1_cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3_1_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_1_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_2_cm: l3_2_cm@800 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_2_cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l3_2_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_2_clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - ducati_cm: ducati_cm@900 { - compatible = "ti,omap4-cm"; - clock-output-names = "ducati_cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ducati_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "ducati_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_dma_cm: l3_dma_cm@a00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_dma_cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - l3_dma_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_dma_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_emif_cm: l3_emif_cm@b00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_emif_cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - l3_emif_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_emif_clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - d2d_cm: d2d_cm@c00 { - compatible = "ti,omap4-cm"; - clock-output-names = "d2d_cm"; - reg = <0xc00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xc00 0x100>; - - d2d_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "d2d_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l4_cfg_cm: l4_cfg_cm@d00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_cfg_cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4_cfg_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_cfg_clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3_instr_cm: l3_instr_cm@e00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_instr_cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3_instr_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_instr_clkctrl"; - reg = <0x20 0x24>; - #clock-cells = <2>; - }; - }; - - ivahd_cm: ivahd_cm@f00 { - compatible = "ti,omap4-cm"; - clock-output-names = "ivahd_cm"; - reg = <0xf00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xf00 0x100>; - - ivahd_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "ivahd_clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - iss_cm: iss_cm@1000 { - compatible = "ti,omap4-cm"; - clock-output-names = "iss_cm"; - reg = <0x1000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x100>; - - iss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "iss_clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - l3_dss_cm: l3_dss_cm@1100 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_dss_cm"; - reg = <0x1100 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1100 0x100>; - - l3_dss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_dss_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_gfx_cm: l3_gfx_cm@1200 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_gfx_cm"; - reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1200 0x100>; - - l3_gfx_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_gfx_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_init_cm: l3_init_cm@1300 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3_init_cm"; - reg = <0x1300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1300 0x100>; - - l3_init_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3_init_clkctrl"; - reg = <0x20 0xc4>; - #clock-cells = <2>; - }; - }; - - l4_per_cm: clock@1400 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_per_cm"; - reg = <0x1400 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x200>; - - l4_per_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_per_clkctrl"; - reg = <0x20 0x144>; - #clock-cells = <2>; - }; - - l4_secure_clkctrl: clock@1a0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_secure_clkctrl"; - reg = <0x1a0 0x3c>; - #clock-cells = <2>; - }; - }; -}; - -&prm { - l4_wkup_cm: l4_wkup_cm@1800 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4_wkup_cm"; - reg = <0x1800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1800 0x100>; - - l4_wkup_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_wkup_clkctrl"; - reg = <0x20 0x5c>; - #clock-cells = <2>; - }; - }; - - emu_sys_cm: emu_sys_cm@1a00 { - compatible = "ti,omap4-cm"; - clock-output-names = "emu_sys_cm"; - reg = <0x1a00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1a00 0x100>; - - emu_sys_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "emu_sys_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi deleted file mode 100644 index 6f46f1ecf1e5..000000000000 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ /dev/null @@ -1,755 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include "omap5.dtsi" -#include -#include - -/ { - aliases { - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vsys_cobra: fixedregulator-vsys_cobra { - compatible = "regulator-fixed"; - regulator-name = "vsys_cobra"; - vin-supply = <&vmain>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vmmcsd_fixed: fixedregulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - mmc3_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clk32kgaudio>; - clock-names = "ext_clock"; - }; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ - enable-active-high; - startup-delay-us = <70000>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ - clocks = <&auxclk1_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ - #phy-cells = <0>; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - /* gpios defined in the board specific dts */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "b"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "omap5-uevm"; - - ti,jack-detection; - ti,mclk-freq = <19200000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; -}; - -&gpio8 { - /* TI trees use GPIO instead of msecure, see also muxing */ - msecure-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "gpio8_234/msecure"; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_pins - &led_gpio_pins - >; - - twl6040_pins: twl6040-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; - }; - - mcpdm_pins: mcpdm-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ - OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ - OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ - OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ - >; - }; - - mcbsp1_pins: mcbsp1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ - OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ - OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ - OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ - >; - }; - - mcbsp2_pins: mcbsp2-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ - OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ - OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ - OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcspi2_pins: mcspi2-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; - - mcspi3_pins: mcspi3-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ - OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ - OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ - OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_pins: wlan-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ - >; - }; - - /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas-msecure-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ - >; - }; - - usbhost_pins: usbhost-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ - OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ - >; - }; - - led_gpio_pins: led-gpio-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ - >; - }; - - uart1_pins: uart1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ - OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ - >; - }; - - uart3_pins: uart3-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ - OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ - >; - }; - - uart5_pins: uart5-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ - OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ - OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ - OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ - >; - }; - - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; - - tpd12s015_pins: tpd12s015-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; -}; - -&omap5_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_wkup_pins - >; - - palmas_sys_nirq_pins: palmas-sys-nirq-pins { - pinctrl-single,pins = < - /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - usbhost_wkup_pins: usbhost-wkup-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ - >; - }; - - wlcore_irq_pin: wlcore-irq-pin-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x16a>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wlcore_irq_pin>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ - ref-clock-frequency = <26000000>; - }; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - palmas: palmas@48 { - compatible = "ti,palmas"; - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = ; - reg = <0x48>; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - ti,mux-pad1 = <0xa1>; - ti,mux-pad2 = <0x1b>; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; - }; - - clk32kgaudio: palmas_clk32k@1 { - compatible = "ti,palmas-clk32kgaudio"; - #clock-cells = <0>; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - - gpadc: gpadc { - compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; - #io-channel-cells = <1>; - ti,channel0-current-microamp = <5>; - ti,channel3-current-microamp = <10>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - smps123-in-supply = <&vsys_cobra>; - smps45-in-supply = <&vsys_cobra>; - smps6-in-supply = <&vsys_cobra>; - smps7-in-supply = <&vsys_cobra>; - smps8-in-supply = <&vsys_cobra>; - smps9-in-supply = <&vsys_cobra>; - smps10_out2-in-supply = <&vsys_cobra>; - smps10_out1-in-supply = <&vsys_cobra>; - ldo1-in-supply = <&vsys_cobra>; - ldo2-in-supply = <&vsys_cobra>; - ldo3-in-supply = <&vdds_1v8_main>; - ldo4-in-supply = <&vdds_1v8_main>; - ldo5-in-supply = <&vsys_cobra>; - ldo6-in-supply = <&vdds_1v8_main>; - ldo7-in-supply = <&vsys_cobra>; - ldo8-in-supply = <&vsys_cobra>; - ldo9-in-supply = <&vmmcsd_fixed>; - ldoln-in-supply = <&vsys_cobra>; - ldousb-in-supply = <&vsys_cobra>; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdds_1v8_main: - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - ti,smps-range = <0x80>; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VCC_2V8_DISP: Does not go anywhere */ - regulator-name = "ldo2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* Unused */ - status = "disabled"; - }; - - ldo3_reg: ldo3 { - /* VDDAPHY_MDM: vdda_lli */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - /* Only if Modem is used */ - status = "disabled"; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3v0: Does not go anywhere */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - /* Unused */ - status = "disabled"; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas_power_button: palmas_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&palmas>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = ; - - /* audpwron gpio defined in the board specific dts */ - - vio-supply = <&smps7_reg>; - v2v1-supply = <&smps9_reg>; - enable-active-high; - - clocks = <&clk32kgaudio>, <&fref_xtal_ck>; - clock-names = "clk32k", "mclk"; - }; -}; - -&mcpdm_module { - /* Module on the SoC needs external clock from the PMIC */ - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - status = "okay"; -}; - -&mcpdm { - clocks = <&twl6040>; - clock-names = "pdmclk"; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&dwc3 { - extcon = <&extcon_usb3>; - dr_mode = "otg"; -}; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&omap5_pmx_core 0x19c>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - - /* vdda-supply populated in board specific dts file */ - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts deleted file mode 100644 index abe0b389ad76..000000000000 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ /dev/null @@ -1,697 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T54 - */ -/dts-v1/; - -#include "omap5.dtsi" -#include -#include - -/ { - model = "CompuLab CM-T54"; - compatible = "compulab,omap5-cm-t54", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ - }; - - aliases { - display0 = &hdmi0; - display1 = &dvi0; - display2 = &lcd0; - }; - - vmmcsd_fixed: fixed-regulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { - compatible = "regulator-fixed"; - regulator-name = "vwlan_pdn_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ldo2_reg>; - gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ - startup-delay-us = <1000>; - enable-active-high; - }; - - vwlan_fixed: fixed-regulator-vwlan { - compatible = "regulator-fixed"; - regulator-name = "vwlan_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vwlan_pdn_fixed>; - gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ - startup-delay-us = <1000>; - enable-active-high; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2-phy-pins { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ - #phy-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "Heartbeat"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; - - hdmi0: connector0 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_conn_pins>; - - hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_dvi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector1 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c2>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - -&omap5_pmx_wkup { - - ads7846_pins: ads7846-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ - >; - }; - - palmas_sys_nirq_pins: palmas-sys-nirq-pins { - pinctrl-single,pins = < - /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &led_gpio_pins - &usbhost_pins - >; - - led_gpio_pins: led-gpio-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ - >; - }; - - i2c1_pins: i2c1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ - OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ - >; - }; - - i2c2_pins: i2c2-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ - OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ - OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ - OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ - OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ - OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ - >; - }; - - mmc2_pins: mmc2-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ - OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ - OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ - OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ - OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ - OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ - OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ - OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ - OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ - OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ - >; - }; - - mmc3_pins: mmc3-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_gpios_pins: wlan-gpios-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ - OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ - >; - }; - - usbhost_pins: usbhost-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ - OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ - >; - }; - - dss_hdmi_pins: dss-hdmi-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ - OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ - OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ - >; - }; - - lcd_pins: lcd-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ - >; - }; - - hdmi_conn_pins: hdmi-conn-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; - - dss_dpi_pins: dss-dpi-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ - OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ - OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ - OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ - OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ - OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ - OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ - OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ - OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ - OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ - OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ - OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ - OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ - OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ - OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ - OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ - OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ - OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ - OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ - OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ - OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ - OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ - OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ - OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ - OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ - OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ - OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ - OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ - >; - }; - - mcspi2_pins: mcspi1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <15 0>; /* gpio1_wk15 */ - pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc3_pins - &wlan_gpios_pins - >; - vmmc-supply = <&vwlan_fixed>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; - - palmas: palmas@48 { - compatible = "ti,palmas"; - reg = <0x48>; - pinctrl-0 = <&palmas_sys_nirq_pins>; - pinctrl-names = "default"; - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - ti,smps-range = <0x80>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VDD_3V3_WLAN */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <1000>; - }; - - ldo3_reg: ldo3 { - /* VCC_1V5_AUD */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3V_GP: act led/serial console */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dpi_dvi_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - - dpi_lcd_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "okay"; - vdd-supply = <&ldo4_reg>; -}; - -&hdmi { - status = "okay"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi deleted file mode 100644 index e0d8e39a0014..000000000000 --- a/arch/arm/boot/dts/omap5-core-thermal.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP543x SoC CORE thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * Contact: Eduardo Valentin - */ - -#include - -core_thermal: core_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 2>; - - trips { - core_crit: core_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi deleted file mode 100644 index 1b4b7d9136c8..000000000000 --- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP543x SoC GPU thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * Contact: Eduardo Valentin - */ - -#include - -gpu_thermal: gpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 1>; - - trips { - gpu_crit: gpu_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts deleted file mode 100644 index d4ca2e3a14dd..000000000000 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ - */ -/dts-v1/; - -#include -#include "omap5-board-common.dtsi" - -/ { - model = "IGEPv5"; - compatible = "isee,omap5-igep0050", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - aliases { - ethernet = ðernet; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led@1 { - label = "board:green:usr0"; - gpios = <&tca6416 1 0>; - default-state = "off"; - }; - led@2 { - label = "board:red:usr1"; - gpios = <&tca6416 2 0>; - default-state = "off"; - }; - led@3 { - label = "board:blue:usr1"; - gpios = <&tca6416 3 0>; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo7_reg>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - tca6416: tca6416@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/* LDO4 is VPP1 - ball AD9 */ -&ldo4_reg { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; -}; - -/* - * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, - * VDDA_HDMI - ball AN25 - */ -&ldo7_reg { - status = "okay"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&omap5_pmx_core { - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ - OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ - >; - }; - - power_button_pin: power-button-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&tca6416 11 0>, /* TCA6416 P01, CT_CP_HDP */ - <&tca6416 12 0>, /* TCA6416 P00, LS_OE*/ - <&gpio7 1 0>, /* 193, HPD */ - <&gpio7 2 0>, /* 194, SCL */ - <&gpio7 3 0>; /* 195, SDA */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ - OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@3 { - compatible = "usb424,7500"; - reg = <3>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi deleted file mode 100644 index a03bca5a3584..000000000000 --- a/arch/arm/boot/dts/omap5-l4-abe.dtsi +++ /dev/null @@ -1,456 +0,0 @@ -&l4_abe { /* 0x40100000 */ - compatible = "ti,omap5-l4-abe", "simple-pm-bus"; - reg = <0x40100000 0x400>, - <0x40100400 0x400>; - reg-names = "la", "ap"; - power-domains = <&prm_abe>; - /* OMAP5_L4_ABE_CLKCTRL is read-only */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ - <0x49000000 0x49000000 0x100000>; - segment@0 { /* 0x40100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = - /* CPU to L4 ABE mapping */ - <0x00000000 0x00000000 0x000400>, /* ap 0 */ - <0x00000400 0x00000400 0x000400>, /* ap 1 */ - <0x00022000 0x00022000 0x001000>, /* ap 2 */ - <0x00023000 0x00023000 0x001000>, /* ap 3 */ - <0x00024000 0x00024000 0x001000>, /* ap 4 */ - <0x00025000 0x00025000 0x001000>, /* ap 5 */ - <0x00026000 0x00026000 0x001000>, /* ap 6 */ - <0x00027000 0x00027000 0x001000>, /* ap 7 */ - <0x00028000 0x00028000 0x001000>, /* ap 8 */ - <0x00029000 0x00029000 0x001000>, /* ap 9 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ - <0x00030000 0x00030000 0x001000>, /* ap 14 */ - <0x00031000 0x00031000 0x001000>, /* ap 15 */ - <0x00032000 0x00032000 0x001000>, /* ap 16 */ - <0x00033000 0x00033000 0x001000>, /* ap 17 */ - <0x00038000 0x00038000 0x001000>, /* ap 18 */ - <0x00039000 0x00039000 0x001000>, /* ap 19 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ - <0x00080000 0x00080000 0x010000>, /* ap 26 */ - <0x00080000 0x00080000 0x001000>, /* ap 27 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ - <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ - <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ - <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ - <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ - - /* L3 to L4 ABE mapping */ - <0x49000000 0x49000000 0x000400>, /* ap 0 */ - <0x49000400 0x49000400 0x000400>, /* ap 1 */ - <0x49022000 0x49022000 0x001000>, /* ap 2 */ - <0x49023000 0x49023000 0x001000>, /* ap 3 */ - <0x49024000 0x49024000 0x001000>, /* ap 4 */ - <0x49025000 0x49025000 0x001000>, /* ap 5 */ - <0x49026000 0x49026000 0x001000>, /* ap 6 */ - <0x49027000 0x49027000 0x001000>, /* ap 7 */ - <0x49028000 0x49028000 0x001000>, /* ap 8 */ - <0x49029000 0x49029000 0x001000>, /* ap 9 */ - <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ - <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ - <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ - <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ - <0x49030000 0x49030000 0x001000>, /* ap 14 */ - <0x49031000 0x49031000 0x001000>, /* ap 15 */ - <0x49032000 0x49032000 0x001000>, /* ap 16 */ - <0x49033000 0x49033000 0x001000>, /* ap 17 */ - <0x49038000 0x49038000 0x001000>, /* ap 18 */ - <0x49039000 0x49039000 0x001000>, /* ap 19 */ - <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ - <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ - <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ - <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ - <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ - <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ - <0x49080000 0x49080000 0x010000>, /* ap 26 */ - <0x49080000 0x49080000 0x001000>, /* ap 27 */ - <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ - <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ - <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ - <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ - <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ - <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ - - target-module@22000 { /* 0x40122000, ap 2 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2208c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>, - <0x49022000 0x49022000 0x1000>; - - mcbsp1: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x40124000, ap 4 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2408c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>, - <0x49024000 0x49024000 0x1000>; - - mcbsp2: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x40126000, ap 6 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>, - <0x49026000 0x49026000 0x1000>; - - mcbsp3: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x40128000, ap 8 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>; - }; - - target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>, - <0x4902a000 0x4902a000 0x1000>; - }; - - target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>, - <0x4902e000 0x4902e000 0x1000>; - - dmic: dmic@0 { - compatible = "ti,omap4-dmic"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x40130000, ap 14 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>, - <0x49030000 0x49030000 0x1000>; - }; - - mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>, - <0x49032000 0x49032000 0x1000>; - - /* Must be only enabled for boards with pdmclk wired */ - status = "disabled"; - - mcpdm: mcpdm@0 { - compatible = "ti,omap4-mcpdm"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - }; - }; - - target-module@38000 { /* 0x40138000, ap 18 12.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x38000 0x4>, - <0x38010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>, - <0x49038000 0x49038000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>, - <&dss_syc_gfclk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>, - <0x4903a000 0x4903a000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>, - <&dss_syc_gfclk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>, - <0x4903c000 0x4903c000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>, - <&dss_syc_gfclk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>, - <0x4903e000 0x4903e000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>, - <&dss_syc_gfclk_div>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@80000 { /* 0x40180000, ap 26 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>, - <0x49080000 0x49080000 0x10000>; - }; - - target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>, - <0x490a0000 0x490a0000 0x10000>; - }; - - target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x10000>, - <0x490c0000 0x490c0000 0x10000>; - }; - - target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf1000 0x4>, - <0xf1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf1000 0x1000>, - <0x490f1000 0x490f1000 0x1000>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi deleted file mode 100644 index 3b505fe415ed..000000000000 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ /dev/null @@ -1,2502 +0,0 @@ -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap5-l4-cfg", "simple-pm-bus"; - power-domains = <&prm_core>; - clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ - <0x00080000 0x4a080000 0x080000>, /* segment 1 */ - <0x00100000 0x4a100000 0x080000>, /* segment 2 */ - <0x00180000 0x4a180000 0x080000>, /* segment 3 */ - <0x00200000 0x4a200000 0x080000>, /* segment 4 */ - <0x00280000 0x4a280000 0x080000>, /* segment 5 */ - <0x00300000 0x4a300000 0x080000>; /* segment 6 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00002000 0x00002000 0x001000>, /* ap 3 */ - <0x00003000 0x00003000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 5 */ - <0x00005000 0x00005000 0x001000>, /* ap 6 */ - <0x00056000 0x00056000 0x001000>, /* ap 7 */ - <0x00057000 0x00057000 0x001000>, /* ap 8 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ - <0x00058000 0x00058000 0x001000>, /* ap 10 */ - <0x00062000 0x00062000 0x001000>, /* ap 11 */ - <0x00063000 0x00063000 0x001000>, /* ap 12 */ - <0x00008000 0x00008000 0x002000>, /* ap 21 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ - <0x00066000 0x00066000 0x001000>, /* ap 23 */ - <0x00067000 0x00067000 0x001000>, /* ap 24 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ - <0x00060000 0x00060000 0x001000>, /* ap 70 */ - <0x00064000 0x00064000 0x001000>, /* ap 71 */ - <0x00065000 0x00065000 0x001000>, /* ap 72 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ - <0x00070000 0x00070000 0x004000>, /* ap 79 */ - <0x00074000 0x00074000 0x001000>, /* ap 80 */ - <0x00075000 0x00075000 0x001000>, /* ap 81 */ - <0x00076000 0x00076000 0x001000>, /* ap 82 */ - <0x00020000 0x00020000 0x020000>, /* ap 109 */ - <0x00040000 0x00040000 0x001000>, /* ap 110 */ - <0x00059000 0x00059000 0x001000>; /* ap 111 */ - - target-module@2000 { /* 0x4a002000, ap 3 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - scm_core: scm@0 { - compatible = "ti,omap5-scm-core", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - scm_padconf_core: scm@800 { - compatible = "ti,omap5-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x800>; - - omap5_pmx_core: pinmux@40 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x40 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0xec>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0xec>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap5", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - }; - - target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - cm_core_aon: cm_core_aon@0 { - compatible = "ti,omap5-cm-core-aon", - "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm_core: cm_core@0 { - compatible = "ti,omap5-cm-core", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - target-module@20000 { /* 0x4a020000, ap 109 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x20000 0x4>, - <0x20010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x20000>; - - usb3: omap_dwc3@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - dwc3: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "peripheral"; - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 7 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ - clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@58000 { /* 0x4a058000, ap 10 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00058000 0x00001000>, - <0x00001000 0x00059000 0x00001000>, - <0x00002000 0x0005a000 0x00001000>, - <0x00003000 0x0005b000 0x00001000>; - }; - - target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x62000 0x4>, - <0x62010 0x4>, - <0x62014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - usbhstll: usbhstll@0 { - compatible = "ti,usbhs-tll"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x64000 0x4>, - <0x64010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - usbhshost: usbhshost@0 { - compatible = "ti,usbhs-host"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - clocks = <&l3init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@800 { - compatible = "ti,ohci-omap3"; - reg = <0x800 0x400>; - interrupts = ; - remote-wakeup-connected; - }; - - usbhsehci: ehci@c00 { - compatible = "ti,ehci-omap"; - reg = <0xc00 0x400>; - interrupts = ; - }; - }; - }; - - target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66000 0x4>, - <0x66010 0x4>, - <0x66014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ - clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp 1>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - mmu_dsp: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - }; - }; - - target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x4000>; - }; - - target-module@75000 { /* 0x4a075000, ap 81 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x75000 0x1000>; - }; - }; - - segment@80000 { /* 0x4a080000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ - <0x0005a000 0x000da000 0x001000>, /* ap 14 */ - <0x0005b000 0x000db000 0x001000>, /* ap 15 */ - <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ - <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ - <0x0005e000 0x000de000 0x001000>, /* ap 18 */ - <0x00060000 0x000e0000 0x001000>, /* ap 19 */ - <0x00061000 0x000e1000 0x001000>, /* ap 20 */ - <0x00074000 0x000f4000 0x001000>, /* ap 25 */ - <0x00075000 0x000f5000 0x001000>, /* ap 26 */ - <0x00076000 0x000f6000 0x001000>, /* ap 27 */ - <0x00077000 0x000f7000 0x001000>, /* ap 28 */ - <0x00036000 0x000b6000 0x001000>, /* ap 65 */ - <0x00037000 0x000b7000 0x001000>, /* ap 66 */ - <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ - <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ - <0x00000000 0x00080000 0x004000>, /* ap 83 */ - <0x00004000 0x00084000 0x001000>, /* ap 84 */ - <0x00005000 0x00085000 0x001000>, /* ap 85 */ - <0x00006000 0x00086000 0x001000>, /* ap 86 */ - <0x00007000 0x00087000 0x001000>, /* ap 87 */ - <0x00008000 0x00088000 0x001000>, /* ap 88 */ - <0x00010000 0x00090000 0x004000>, /* ap 89 */ - <0x00014000 0x00094000 0x001000>, /* ap 90 */ - <0x00015000 0x00095000 0x001000>, /* ap 91 */ - <0x00016000 0x00096000 0x001000>, /* ap 92 */ - <0x00017000 0x00097000 0x001000>, /* ap 93 */ - <0x00018000 0x00098000 0x001000>, /* ap 94 */ - <0x00020000 0x000a0000 0x004000>, /* ap 95 */ - <0x00024000 0x000a4000 0x001000>, /* ap 96 */ - <0x00025000 0x000a5000 0x001000>, /* ap 97 */ - <0x00026000 0x000a6000 0x001000>, /* ap 98 */ - <0x00027000 0x000a7000 0x001000>, /* ap 99 */ - <0x00028000 0x000a8000 0x001000>; /* ap 100 */ - - target-module@0 { /* 0x4a080000, ap 83 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x14 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00004000>, - <0x00004000 0x00004000 0x00001000>, - <0x00005000 0x00005000 0x00001000>, - <0x00006000 0x00006000 0x00001000>, - <0x00007000 0x00007000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x20>; - }; - - usb2_phy: usb2phy@4000 { - compatible = "ti,omap-usb2"; - reg = <0x4000 0x7c>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4400 { - compatible = "ti,omap-usb3"; - reg = <0x4400 0x80>, - <0x4800 0x64>, - <0x4c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@10000 { /* 0x4a090000, ap 89 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x10000 0x4>, - <0x10010 0x4>, - <0x10014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x00004000>, - <0x00004000 0x00014000 0x00001000>, - <0x00005000 0x00015000 0x00001000>, - <0x00006000 0x00016000 0x00001000>, - <0x00007000 0x00017000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x20>; - }; - - sata_phy: phy@6000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x6400 0x64>, /* phy_tx */ - <0x6800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00020000 0x00004000>, - <0x00004000 0x00024000 0x00001000>, - <0x00005000 0x00025000 0x00001000>, - <0x00006000 0x00026000 0x00001000>, - <0x00007000 0x00027000 0x00001000>; - }; - - target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000 0x1000>; - }; - - target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - }; - - target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - }; - - target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x74000 0x4>, - <0x74010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox-ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - }; - - target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x76000 0x4>, - <0x76010 0x4>, - <0x76014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ - <0x00003000 0x00103000 0x001000>, /* ap 60 */ - <0x00008000 0x00108000 0x001000>, /* ap 61 */ - <0x00009000 0x00109000 0x001000>, /* ap 62 */ - <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ - <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ - <0x00040000 0x00140000 0x010000>, /* ap 101 */ - <0x00050000 0x00150000 0x001000>; /* ap 102 */ - - target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 61 26.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@40000 { /* 0x4a140000, ap 101 16.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x400fc 4>, - <0x41100 4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - power-domains = <&prm_l3init>; - clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>; - clock-names = "fck"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - - sata: sata@0 { - compatible = "snps,dwc-ahci"; - reg = <0 0x1100>, <0x1100 0x8>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - ports-implemented = <0x1>; - }; - }; - }; - - segment@180000 { /* 0x4a180000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ - <0x00006000 0x00206000 0x001000>, /* ap 33 */ - <0x00007000 0x00207000 0x001000>, /* ap 34 */ - <0x00004000 0x00204000 0x001000>, /* ap 35 */ - <0x00005000 0x00205000 0x001000>, /* ap 36 */ - <0x00012000 0x00212000 0x001000>, /* ap 37 */ - <0x00013000 0x00213000 0x001000>, /* ap 38 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ - <0x00010000 0x00210000 0x001000>, /* ap 41 */ - <0x00011000 0x00211000 0x001000>, /* ap 42 */ - <0x00016000 0x00216000 0x001000>, /* ap 43 */ - <0x00017000 0x00217000 0x001000>, /* ap 44 */ - <0x00014000 0x00214000 0x001000>, /* ap 45 */ - <0x00015000 0x00215000 0x001000>, /* ap 46 */ - <0x00018000 0x00218000 0x001000>, /* ap 47 */ - <0x00019000 0x00219000 0x001000>, /* ap 48 */ - <0x00020000 0x00220000 0x001000>, /* ap 49 */ - <0x00021000 0x00221000 0x001000>, /* ap 50 */ - <0x00026000 0x00226000 0x001000>, /* ap 51 */ - <0x00027000 0x00227000 0x001000>, /* ap 52 */ - <0x00028000 0x00228000 0x001000>, /* ap 53 */ - <0x00029000 0x00229000 0x001000>, /* ap 54 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ - <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ - <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ - <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ - <0x00024000 0x00224000 0x001000>, /* ap 75 */ - <0x00025000 0x00225000 0x001000>, /* ap 76 */ - <0x00002000 0x00202000 0x001000>, /* ap 103 */ - <0x00003000 0x00203000 0x001000>, /* ap 104 */ - <0x00008000 0x00208000 0x001000>, /* ap 105 */ - <0x00009000 0x00209000 0x001000>, /* ap 106 */ - <0x00022000 0x00222000 0x001000>, /* ap 107 */ - <0x00023000 0x00223000 0x001000>; /* ap 108 */ - - target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@4000 { /* 0x4a204000, ap 35 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - }; - - target-module@8000 { /* 0x4a208000, ap 105 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 41 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 37 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x4a216000, ap 43 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - }; - - target-module@24000 { /* 0x4a224000, ap 75 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 51 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x4a228000, ap 53 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - }; - - segment@280000 { /* 0x4a280000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@300000 { /* 0x4a300000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,omap5-l4-per", "simple-pm-bus"; - power-domains = <&prm_core>; - clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00055000 0x00055000 0x001000>, /* ap 13 */ - <0x00056000 0x00056000 0x001000>, /* ap 14 */ - <0x00057000 0x00057000 0x001000>, /* ap 15 */ - <0x00058000 0x00058000 0x001000>, /* ap 16 */ - <0x00059000 0x00059000 0x001000>, /* ap 17 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ - <0x00060000 0x00060000 0x001000>, /* ap 23 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ - <0x00070000 0x00070000 0x001000>, /* ap 30 */ - <0x00071000 0x00071000 0x001000>, /* ap 31 */ - <0x00072000 0x00072000 0x001000>, /* ap 32 */ - <0x00073000 0x00073000 0x001000>, /* ap 33 */ - <0x00061000 0x00061000 0x001000>, /* ap 34 */ - <0x00053000 0x00053000 0x001000>, /* ap 35 */ - <0x00054000 0x00054000 0x001000>, /* ap 36 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x001000>, /* ap 39 */ - <0x00079000 0x00079000 0x001000>, /* ap 40 */ - <0x00086000 0x00086000 0x001000>, /* ap 41 */ - <0x00087000 0x00087000 0x001000>, /* ap 42 */ - <0x00088000 0x00088000 0x001000>, /* ap 43 */ - <0x00089000 0x00089000 0x001000>, /* ap 44 */ - <0x00051000 0x00051000 0x001000>, /* ap 45 */ - <0x00052000 0x00052000 0x001000>, /* ap 46 */ - <0x00098000 0x00098000 0x001000>, /* ap 47 */ - <0x00099000 0x00099000 0x001000>, /* ap 48 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ - <0x00068000 0x00068000 0x001000>, /* ap 53 */ - <0x00069000 0x00069000 0x001000>, /* ap 54 */ - <0x00090000 0x00090000 0x002000>, /* ap 55 */ - <0x00092000 0x00092000 0x001000>, /* ap 56 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ - <0x000a5000 0x000a5000 0x001000>, - <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ - <0x00066000 0x00066000 0x001000>, /* ap 63 */ - <0x00067000 0x00067000 0x001000>, /* ap 64 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ - <0x00001400 0x00001400 0x000400>, /* ap 77 */ - <0x00001800 0x00001800 0x000400>, /* ap 78 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ - <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ - <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ - <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ - <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 3e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 46.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 4e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@51000 { /* 0x48051000, ap 45 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x51000 0x4>, - <0x51010 0x4>, - <0x51114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - - gpio7: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@53000 { /* 0x48053000, ap 35 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53000 0x4>, - <0x53010 0x4>, - <0x53114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - - gpio8: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 15 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 23 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@66000 { /* 0x48066000, ap 63 4c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66050 0x4>, - <0x66054 0x4>, - <0x66058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - uart5: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@68000 { /* 0x48068000, ap 53 54.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x68050 0x4>, - <0x68054 0x4>, - <0x68058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x1000>; - - uart6: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@70000 { /* 0x48070000, ap 30 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@72000 { /* 0x48072000, ap 32 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@78000 { /* 0x48078000, ap 39 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - }; - - target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7a000 0x8>, - <0x7a010 0x8>, - <0x7a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7a000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7c000 0x8>, - <0x7c010 0x8>, - <0x7c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x1000>; - - i2c5: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@86000 { /* 0x48086000, ap 41 5e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x86000 0x4>, - <0x86010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@88000 { /* 0x48088000, ap 43 66.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - ; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - }; - }; - - target-module@98000 { /* 0x48098000, ap 47 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - }; - - target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - des_target: target-module@a5000 { /* 0x480a5000 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xa5030 0x4>, - <0xa5034 0x4>, - <0xa5038 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa5000 0x00001000>; - status = "disabled"; - - des: des@0 { - compatible = "ti,omap4-des"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - }; - }; - - target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - }; - - target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd5000 0x4>, - <0xd5010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - - mmc5: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_wkup { /* 0x4ae00000 */ - compatible = "ti,omap5-l4-wkup", "simple-pm-bus"; - power-domains = <&prm_wkupaon>; - clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>; - clock-names = "fck"; - reg = <0x4ae00000 0x800>, - <0x4ae00800 0x800>, - <0x4ae01000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ - <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ - <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ - - segment@0 { /* 0x4ae00000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ - <0x00004000 0x00004000 0x001000>, /* ap 17 */ - <0x00005000 0x00005000 0x001000>, /* ap 18 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ - - target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,omap5-prm", "simple-bus"; - reg = <0x0 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - scrm: scrm@0 { - compatible = "ti,omap5-scrm"; - reg = <0x0 0x1000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - omap5_pmx_wkup: pinmux@840 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x840 0x003c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { - compatible = "ti,omap5-scm-wkup-pad-conf", - "simple-bus"; - reg = <0xda0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60>; - - scm_wkup_pad_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x60>; - - scm_wkup_pad_conf_clocks: clocks@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; - }; - - segment@10000 { /* 0x4ae10000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ - - target-module@0 { /* 0x4ae10000, ap 5 10.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, - <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x8000 0x4>, - <0x8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>, - <&sys_clkin>; - clock-names = "fck", "timer_sys_ck"; - interrupts = ; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xc000 0x4>, - <0xc010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - keypad: keypad@0 { - compatible = "ti,omap4-keypad"; - reg = <0x0 0x400>; - }; - }; - }; - - segment@20000 { /* 0x4ae20000 */ - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 21 */ - <0x00001000 0x00021000 0x001000>, /* ap 22 */ - <0x00002000 0x00022000 0x001000>, /* ap 23 */ - <0x00003000 0x00023000 0x001000>, /* ap 24 */ - <0x00007000 0x00027000 0x000400>, /* ap 25 */ - <0x00008000 0x00028000 0x000800>, /* ap 26 */ - <0x00009000 0x00029000 0x000100>, /* ap 27 */ - <0x00008800 0x00028800 0x000200>, /* ap 28 */ - <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ - - target-module@0 { /* 0x4ae20000, ap 21 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00002800 0x00008800 0x00000200>, - <0x00002a00 0x00008a00 0x00000100>, - <0x00003000 0x00009000 0x00000100>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts deleted file mode 100644 index 02716fb796bd..000000000000 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab CM-T54 on SB-T54 baseboard - */ - -#include "omap5-cm-t54.dts" - -/ { - model = "CompuLab CM-T54 on SB-T54"; - compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; -}; - -&omap5_pmx_core { - i2c4_pins: i2c4-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc1_aux_pins: mmc1-aux-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ - OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc1_pins - &mmc1_aux_pins - >; - cd-inverted; - wp-inverted; - cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ - wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts deleted file mode 100644 index 933de05d3ca1..000000000000 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap5-board-common.dtsi" - -/ { - model = "TI OMAP5 uEVM board"; - compatible = "ti,omap5-uevm", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_memory_region: dsp-memory@95000000 { - compatible = "shared-dma-pool"; - reg = <0 0x95000000 0 0x800000>; - reusable; - status = "okay"; - }; - - ipu_memory_region: ipu-memory@95800000 { - compatible = "shared-dma-pool"; - reg = <0 0x95800000 0 0x3800000>; - reusable; - status = "okay"; - }; - }; - - aliases { - ethernet = ðernet; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - evm_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&evm_keys_pins>; - - #address-cells = <7>; - #size-cells = <0>; - - btn1 { - label = "BTN1"; - linux,code = <169>; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ - wakeup-source; - autorepeat; - debounce-interval = <50>; - }; - }; - - evm_leds { - compatible = "gpio-leds"; - - led1 { - label = "omap5:red:led"; - gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "omap5:green:led"; - gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "omap5:blue:led"; - gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - - led4 { - label = "omap5:green:led1"; - gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led5 { - label = "omap5:green:led2"; - gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led6 { - label = "omap5:green:led3"; - gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led7 { - label = "omap5:green:led4"; - gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led8 { - label = "omap5:green:led5"; - gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo4_reg>; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; - - gpio9: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ -}; - -&omap5_pmx_core { - evm_keys_pins: evm-keys-gpio-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ - >; - }; - - i2c5_pins: i2c5-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ - OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ - >; - }; - - mmc1_pins: mmc1-pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ - <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ - <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ethernet: ethernet@3 { - compatible = "usb424,9730"; - reg = <3>; - }; -}; - -&wlcore { - compatible = "ti,wl1837"; -}; - -&dsp { - status = "okay"; - memory-region = <&dsp_memory_region>; - ti,timers = <&timer5>; - ti,watchdog-timers = <&timer6>; -}; - -&ipu { - status = "okay"; - memory-region = <&ipu_memory_region>; - ti,timers = <&timer3>; - ti,watchdog-timers = <&timer9>, <&timer11>; -}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi deleted file mode 100644 index bac6fa838793..000000000000 --- a/arch/arm/boot/dts/omap5.dtsi +++ /dev/null @@ -1,831 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,omap5"; - interrupt-parent = <&wakeupgen>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - mmc0 = &mmc1; - mmc1 = &mmc2; - mmc2 = &mmc3; - mmc3 = &mmc4; - mmc4 = &mmc5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - rproc0 = &dsp; - rproc1 = &ipu; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - }; - - timer { - compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ */ - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - ; - }; - - /* - * Needed early by omap4_sram_init() for barrier, do not move to l3 - * interconnect as simple-pm-bus probes at module_init() time. - */ - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0 0x40300000 0 0x20000>; /* 128k */ - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48211000 0 0x1000>, - <0 0x48212000 0 0x2000>, - <0 0x48214000 0 0x2000>, - <0 0x48216000 0 0x2000>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48281000 0 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "simple-pm-bus"; - power-domains = <&prm_core>; - clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>, - <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>, - <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xc0000000>; - dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; - - l3-noc@44000000 { - compatible = "ti,omap5-l3-noc"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>, - <0x45000000 0x4000>; - interrupts = , - ; - }; - - l4_wkup: interconnect@4ae00000 { - }; - - l4_cfg: interconnect@4a000000 { - }; - - l4_per: interconnect@48000000 { - }; - - target-module@48210000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - power-domains = <&prm_mpu>; - clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48210000 0x1f0000>; - - mpu { - compatible = "ti,omap4-mpu"; - sram = <&ocmcram>; - }; - }; - - l4_abe: interconnect@40100000 { - }; - - target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000000 4>, - <0x50000010 4>, - <0x50000014 4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - ti,no-idle-on-init; - clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ - <0x00000000 0x00000000 0x40000000>; /* data */ - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - ranges = <0x0 0x55082000 0x100>; - #size-cells = <1>; - #address-cells = <1>; - - mmu_ipu: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = ; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - }; - - dsp: dsp { - compatible = "ti,omap5-dsp"; - ti,bootreg = <&scm_conf 0x304 0>; - iommus = <&mmu_dsp>; - resets = <&prm_dsp 0>; - clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; - firmware-name = "omap5-dsp-fw.xe64T"; - mboxes = <&mailbox &mbox_dsp>; - status = "disabled"; - }; - - ipu: ipu@55020000 { - compatible = "ti,omap5-ipu"; - reg = <0x55020000 0x10000>; - reg-names = "l2ram"; - iommus = <&mmu_ipu>; - resets = <&prm_core 0>, <&prm_core 1>; - clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; - firmware-name = "omap5-ipu-fw.xem4"; - mboxes = <&mailbox &mbox_ipu>; - status = "disabled"; - }; - - target-module@4e000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4e000000 0x4>, - <0x4e000010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - ranges = <0x0 0x4e000000 0x2000000>; - #size-cells = <1>; - #address-cells = <1>; - - dmm@0 { - compatible = "ti,omap5-dmm"; - reg = <0 0x800>; - interrupts = ; - }; - }; - - target-module@4c000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x4c000000 0x4>; - reg-names = "rev"; - clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000000 0x1000000>; - - emif1: emif@0 { - compatible = "ti,emif-4d5"; - reg = <0 0x400>; - interrupts = ; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - }; - - target-module@4d000000 { - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x4d000000 0x4>; - reg-names = "rev"; - clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>; - clock-names = "fck"; - ti,no-idle; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000000 0x1000000>; - - emif2: emif@0 { - compatible = "ti,emif-4d5"; - reg = <0 0x400>; - interrupts = ; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - }; - - aes1_target: target-module@4b501000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b501080 0x4>, - <0x4b501084 0x4>, - <0x4b501088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b501000 0x1000>; - - aes1: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; - }; - }; - - aes2_target: target-module@4b701000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4b701080 0x4>, - <0x4b701084 0x4>, - <0x4b701088 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b701000 0x1000>; - - aes2: aes@0 { - compatible = "ti,omap4-aes"; - reg = <0 0xa0>; - interrupts = ; - dmas = <&sdma 114>, <&sdma 113>; - dma-names = "tx", "rx"; - }; - }; - - sham_target: target-module@4b100000 { - compatible = "ti,sysc-omap3-sham", "ti,sysc"; - reg = <0x4b100100 0x4>, - <0x4b100110 0x4>, - <0x4b100114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4b100000 0x1000>; - - sham: sham@0 { - compatible = "ti,omap4-sham"; - reg = <0 0x300>; - interrupts = ; - dmas = <&sdma 119>; - dma-names = "rx"; - }; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c>; - interrupts = ; - compatible = "ti,omap5430-bandgap"; - - #thermal-sensor-cells = <1>; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - - target-module@58000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58000000 4>, - <0x58000014 4>; - reg-names = "rev", "syss"; - ti,syss-mask = <1>; - power-domains = <&prm_dss>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; - clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x58000000 0x1000000>; - - dss: dss@0 { - compatible = "ti,omap5-dss"; - reg = <0 0x80>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000000>; - - target-module@1000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x1000 0x4>, - <0x1010 0x4>, - <0x1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-midle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x1000>; - - dispc@0 { - compatible = "ti,omap5-dispc"; - reg = <0 0x1000>; - interrupts = ; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@2000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2010 0x4>, - <0x2014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - - rfbi: encoder@0 { - compatible = "ti,omap5-rfbi"; - reg = <0 0x100>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; - clock-names = "fck", "ick"; - }; - }; - - target-module@4000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4000 0x1000>; - - dsi1: encoder@0 { - compatible = "ti,omap5-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@9000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9000 0x4>, - <0x9010 0x4>, - <0x9014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = , - , - ; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x9000 0x1000>; - - dsi2: encoder@0 { - compatible = "ti,omap5-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@40000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck", "dss_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000 0x40000>; - - hdmi: encoder@0 { - compatible = "ti,omap5-hdmi"; - reg = <0 0x200>, - <0x200 0x80>, - <0x300 0x80>, - <0x20000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, - <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1250000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - - abb_mm: regulator-abb-mm { - compatible = "ti,abb-v2"; - regulator-name = "abb_mm"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, - <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80000000>; - /* LDOVBBMM_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMM_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0x0 0 0x02000000 0x01F00000 - 1120000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - }; -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ - coefficients = <65 (-1791)>; -}; - -#include "omap5-l4.dtsi" -#include "omap54xx-clocks.dtsi" - -&gpu_thermal { - coefficients = <117 (-2992)>; -}; - -&core_thermal { - coefficients = <0 2000>; -}; - -#include "omap5-l4-abe.dtsi" -#include "omap54xx-clocks.dtsi" - -&prm { - prm_mpu: prm@300 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x300 0x100>; - #power-domain-cells = <0>; - }; - - prm_dsp: prm@400 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_abe: prm@500 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x500 0x100>; - #power-domain-cells = <0>; - }; - - prm_coreaon: prm@600 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x600 0x100>; - #power-domain-cells = <0>; - }; - - prm_core: prm@700 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_iva: prm@1200 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #reset-cells = <1>; - #power-domain-cells = <0>; - }; - - prm_cam: prm@1300 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1300 0x100>; - #power-domain-cells = <0>; - }; - - prm_dss: prm@1400 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1400 0x100>; - #power-domain-cells = <0>; - }; - - prm_gpu: prm@1500 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1500 0x100>; - #power-domain-cells = <0>; - }; - - prm_l3init: prm@1600 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1600 0x100>; - #power-domain-cells = <0>; - }; - - prm_custefuse: prm@1700 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1700 0x100>; - #power-domain-cells = <0>; - }; - - prm_wkupaon: prm@1800 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1800 0x100>; - #power-domain-cells = <0>; - }; - - prm_emu: prm@1a00 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1a00 0x100>; - #power-domain-cells = <0>; - }; - - prm_device: prm@1c00 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c00 0x100>; - #reset-cells = <1>; - }; -}; - -/* Preferred always-on timer for clockevent */ -&timer1_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - assigned-clock-parents = <&sys_32k_ck>; - }; -}; diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi deleted file mode 100644 index 5cf3b0e78c15..000000000000 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ /dev/null @@ -1,1362 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP5 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_core_aon_clocks { - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "pad_clks_src_ck"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "pad_clks_ck"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "secure_32k_clk_src_ck"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "slimbus_src_clk"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "slimbus_clk"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "sys_32k_ck"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_12000000_ck"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_13000000_ck"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_16800000_ck"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_19200000_ck"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_26000000_ck"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_27000000_ck"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "virt_38400000_ck"; - clock-frequency = <38400000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "xclk60mhsp1_ck"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "xclk60mhsp2_ck"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clock-output-names = "dpll_abe_ck"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_abe_x2_ck"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m2x2_ck"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "abe_24m_fclk"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_clk"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - abe_iclk: abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "abe_iclk"; - clocks = <&aess_fclk>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - abe_lp_clk_div: abe_lp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "abe_lp_clk_div"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_abe_m3x2_ck"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f4>; - ti,index-starts-at-one; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_core_byp_mux"; - clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clock-output-names = "dpll_core_ck"; - clocks = <&sys_clkin>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_core_x2_ck"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h21x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - c2c_fclk: c2c_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "c2c_fclk"; - clocks = <&dpll_core_h21x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - c2c_iclk: c2c_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "c2c_iclk"; - clocks = <&c2c_fclk>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h11x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0138>; - ti,index-starts-at-one; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h12x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x013c>; - ti,index-starts-at-one; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h13x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h14x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0144>; - ti,index-starts-at-one; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h22x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h23x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_h24x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m2_ck"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - reg = <0x0130>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_core_m3x2_ck"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "iva_dpll_hs_clk_div"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_iva_byp_mux"; - clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_iva_ck"; - clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <1165000000>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_iva_x2_ck"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_iva_h11x2_ck"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01b8>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h11x2_ck>; - assigned-clock-rates = <465920000>; - }; - - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_iva_h12x2_ck"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01bc>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h12x2_ck>; - assigned-clock-rates = <388300000>; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "mpu_dpll_hs_clk_div"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clock-output-names = "dpll_mpu_ck"; - clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_mpu_m2_ck"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x0170>; - ti,index-starts-at-one; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "per_dpll_hs_clk_div"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "usb_dpll_hs_clk_div"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3_iclk_div"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - gpu_l3_iclk: gpu_l3_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "gpu_l3_iclk"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_root_clk_div: l4_root_clk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l4_root_clk_div"; - ti,max-div = <2>; - ti,bit-shift = <8>; - reg = <0x100>; - clocks = <&l3_iclk_div>; - ti,index-power-of-two; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "slimbus1_slimbus_clk"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "aess_fclk"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "mcasp_sync_mux_ck"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0540>; - }; - - mcasp_gfclk: mcasp_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "mcasp_gfclk"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-output-names = "dummy_ck"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin: sys_clkin@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "sys_clkin"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_bypass_clk_mux"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x0108>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_clk_mux"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "custefuse_sys_gfclk_div"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <2>; - }; - - dss_syc_gfclk_div: dss_syc_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dss_syc_gfclk_div"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "wkupaon_iclk_mux"; - clocks = <&sys_clkin>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "l3instr_ts_gclk_div"; - clocks = <&wkupaon_iclk_mux>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_core_clocks { - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_per_byp_mux"; - clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_per_ck"; - clocks = <&sys_clkin>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clock-output-names = "dpll_per_x2_ck"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h11x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h12x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_h14x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0164>; - ti,index-starts-at-one; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2_ck"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m2x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_per_m3x2_ck"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_unipro1_ck: dpll_unipro1_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_unipro1_ck"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_unipro1_clkdcoldo"; - clocks = <&dpll_unipro1_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_unipro1_m2_ck"; - clocks = <&dpll_unipro1_ck>; - ti,max-div = <127>; - reg = <0x0210>; - ti,index-starts-at-one; - }; - - dpll_unipro2_ck: dpll_unipro2_ck@1c0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clock-output-names = "dpll_unipro2_ck"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; - }; - - dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_unipro2_clkdcoldo"; - clocks = <&dpll_unipro2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_unipro2_m2_ck"; - clocks = <&dpll_unipro2_ck>; - ti,max-div = <127>; - reg = <0x01d0>; - ti,index-starts-at-one; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_usb_byp_mux"; - clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clock-output-names = "dpll_usb_ck"; - clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "dpll_usb_clkdcoldo"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dpll_usb_m2_ck"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x0190>; - ti,index-starts-at-one; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_128m_clk"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_12m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_24m_clk"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_48m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-output-names = "func_96m_fclk"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3init_60m_fclk"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - iss_ctrlclk: iss_ctrlclk@1320 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "iss_ctrlclk"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1320>; - }; - - lli_txphy_clk: lli_txphy_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "lli_txphy_clk"; - clocks = <&dpll_unipro1_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x0f20>; - }; - - lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "lli_txphy_ls_clk"; - clocks = <&dpll_unipro1_m2_ck>; - ti,bit-shift = <9>; - reg = <0x0f20>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "usb_phy_cm_clk32k"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - fdif_fclk: fdif_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "fdif_fclk"; - clocks = <&dpll_per_h11x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1328>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gpu_core_gclk_mux"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <24>; - reg = <0x1520>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "gpu_hyd_gclk_mux"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <25>; - reg = <0x1520>; - }; - - hsi_fclk: hsi_fclk@1638 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "hsi_fclk"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1638>; - }; -}; - -&cm_core_clockdomains { - l3init_clkdm: l3init_clkdm { - compatible = "ti,clockdomain"; - clock-output-names = "l3init_clkdm"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk0_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk0_src_mux_ck"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk0_src_ck"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk0_ck"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk1_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk1_src_mux_ck"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk1_src_ck"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk1_ck"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk2_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk2_src_mux_ck"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk2_src_ck"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk2_ck"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk3_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk3_src_mux_ck"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk3_src_ck"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk3_ck"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "auxclk4_src_gate_ck"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clock-output-names = "auxclk4_src_mux_ck"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clock-output-names = "auxclk4_src_ck"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "auxclk4_ck"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq0_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq1_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq2_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "auxclkreq3_ck"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; -}; - -&cm_core_aon { - mpu_cm: mpu_cm@300 { - compatible = "ti,omap4-cm"; - clock-output-names = "mpu_cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "mpu_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dsp_cm: dsp_cm@400 { - compatible = "ti,omap4-cm"; - clock-output-names = "dsp_cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - dsp_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dsp_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - abe_cm: abe_cm@500 { - compatible = "ti,omap4-cm"; - clock-output-names = "abe_cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - abe_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "abe_clkctrl"; - reg = <0x20 0x64>; - #clock-cells = <2>; - }; - }; - -}; - -&cm_core { - l3main1_cm: l3main1_cm@700 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3main1_cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3main1_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3main1_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3main2_cm: l3main2_cm@800 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3main2_cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l3main2_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3main2_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - ipu_cm: ipu_cm@900 { - compatible = "ti,omap4-cm"; - clock-output-names = "ipu_cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ipu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "ipu_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dma_cm: dma_cm@a00 { - compatible = "ti,omap4-cm"; - clock-output-names = "dma_cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - dma_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dma_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - emif_cm: emif_cm@b00 { - compatible = "ti,omap4-cm"; - clock-output-names = "emif_cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - emif_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "emif_clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l4cfg_cm: l4cfg_cm@d00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4cfg_cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4cfg_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4cfg_clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3instr_cm: l3instr_cm@e00 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3instr_cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3instr_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3instr_clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - l4per_cm: clock@1000 { - compatible = "ti,omap4-cm"; - clock-output-names = "l4per_cm"; - reg = <0x1000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x200>; - - l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4per_clkctrl"; - reg = <0x20 0x15c>; - #clock-cells = <2>; - }; - - l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl"; - clock-output-names = "l4sec_clkctrl"; - reg = <0x1a0 0x3c>; - #clock-cells = <2>; - }; - }; - - dss_cm: dss_cm@1400 { - compatible = "ti,omap4-cm"; - clock-output-names = "dss_cm"; - reg = <0x1400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x100>; - - dss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "dss_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gpu_cm: gpu_cm@1500 { - compatible = "ti,omap4-cm"; - clock-output-names = "gpu_cm"; - reg = <0x1500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1500 0x100>; - - gpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "gpu_clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3init_cm: l3init_cm@1600 { - compatible = "ti,omap4-cm"; - clock-output-names = "l3init_cm"; - reg = <0x1600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1600 0x100>; - - l3init_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l3init_clkctrl"; - reg = <0x20 0xd4>; - #clock-cells = <2>; - }; - }; -}; - -&prm { - wkupaon_cm: wkupaon_cm@1900 { - compatible = "ti,omap4-cm"; - clock-output-names = "wkupaon_cm"; - reg = <0x1900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1900 0x100>; - - wkupaon_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - clock-output-names = "wkupaon_clkctrl"; - reg = <0x20 0x5c>; - #clock-cells = <2>; - }; - }; -}; - -&scm_wkup_pad_conf_clocks { - fref_xtal_ck: fref_xtal_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "fref_xtal_ck"; - clocks = <&sys_clkin>; - ti,bit-shift = <28>; - reg = <0x14>; - }; -}; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi deleted file mode 100644 index 05101a38c5bd..000000000000 --- a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x5600000>; // 86MB - label = "rofs"; - }; - - rwfs@6000000 { - reg = <0x6000000 0x2000000>; // 32MB - label = "rwfs"; - }; -}; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi deleted file mode 100644 index 650525867561..000000000000 --- a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Bytedance. - */ - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "alt-u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "alt-u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "alt-kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x2000000>; // 32MB - label = "alt-rofs"; - }; - - rwfs@6000000 { - reg = <0x2a00000 0x1600000>; // 22MB - label = "alt-rwfs"; - }; -}; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi deleted file mode 100644 index 7af41361c480..000000000000 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Bytedance. - */ - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x2000000>; // 32MB - label = "rofs"; - }; - - rwfs@2a00000 { - reg = <0x2a00000 0x1600000>; // 22MB - label = "rwfs"; - }; -}; diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi deleted file mode 100644 index b47e14063c38..000000000000 --- a/arch/arm/boot/dts/openbmc-flash-layout.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0x60000>; - label = "u-boot"; - }; - - u-boot-env@60000 { - reg = <0x60000 0x20000>; - label = "u-boot-env"; - }; - - kernel@80000 { - reg = <0x80000 0x440000>; - label = "kernel"; - }; - - rofs@4c0000 { - reg = <0x4c0000 0x1740000>; - label = "rofs"; - }; - - rwfs@1c00000 { - reg = <0x1c00000 0x400000>; - label = "rwfs"; - }; -}; diff --git a/arch/arm/boot/dts/orion5x-kuroboxpro.dts b/arch/arm/boot/dts/orion5x-kuroboxpro.dts deleted file mode 100644 index e28b568e741a..000000000000 --- a/arch/arm/boot/dts/orion5x-kuroboxpro.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Device Tree file for Buffalo/Revogear Kurobox Pro - * - * Copyright (C) 2016 - * Roger Shimizu - * - * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c - * Copyright (C) Ronen Shitrit - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include - -/ { - model = "Buffalo/Revogear Kurobox Pro"; - compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x"; - - soc { - ranges = , - , - , - ; - }; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; -}; - -&devbus_cs0 { - status = "okay"; - compatible = "marvell,orion-nand"; - reg = ; - cle = <0>; - ale = <1>; - bank-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - uImage@0 { /* 4 MB */ - reg = <0 0x400000>; - read-only; - }; - - rootfs@400000 { /* 64 MB */ - reg = <0x400000 0x4000000>; - read-only; - }; - - extra@4400000 { /* 188 MB */ - reg = <0x4400000 0xBC00000>; - read-only; - }; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; - -&ehci1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts deleted file mode 100644 index 03471d30bfd9..000000000000 --- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Thomas Petazzoni - * Copyright (C) 2009 Simon Guinot - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "LaCie d2 Network"; - compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - front_button { - label = "Front Push Button"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - }; - - power_rocker_sw_on { - label = "Power rocker switch (on|auto)"; - linux,input-type = <5>; /* EV_SW */ - linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - power_rocker_sw_off { - label = "Power rocker switch (auto|off)"; - linux,input-type = <5>; /* EV_SW */ - linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; - pinctrl-names = "default"; - - sata0_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full512Kb"; - reg = <0 0x80000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372b"; - reg = <0x32>; - }; - - fan@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - - /* Not enough HW info */ - status = "disabled"; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; - pinctrl-names = "default"; - - pmx_board_id: pmx-board-id { - marvell,pins = "mpp0", "mpp1", "mpp2"; - marvell,function = "gpio"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp8", "mpp9", "mpp18"; - marvell,function = "gpio"; - }; - - pmx_fan_fail: pmx-fan-fail { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - /* - * MPP6: Red front LED - * MPP16: Blue front LED blink control - */ - pmx_leds: pmx-leds { - marvell,pins = "mpp6", "mpp16"; - marvell,function = "gpio"; - }; - - pmx_sata0_led_active: pmx-sata0-led-active { - marvell,pins = "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata0_power: pmx-sata0-power { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_sata1_led_active: pmx-sata1-led-active { - marvell,pins = "mpp15"; - marvell,function = "sata1"; - }; - - pmx_sata1_power: pmx-sata1-power { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - /* - * Non MPP GPIOs: - * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) - * GPIO 23: Blue front LED off - * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) - */ -}; - -&sata { - pinctrl-0 = <&pmx_sata0_led_active - &pmx_sata1_led_active>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts deleted file mode 100644 index f17e25ac98dd..000000000000 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2012 Thomas Petazzoni - -/* - * TODO: add Orion USB device port init when kernel.org support is added. - * TODO: add flash write support: see below. - * TODO: add power-off support. - * TODO: add I2C EEPROM support. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "LaCie Ethernet Disk mini V2"; - compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_power_button>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - button@1 { - label = "Power-on Switch"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_power_led>; - pinctrl-names = "default"; - - led@1 { - label = "power:blue"; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full512Kb"; - reg = <0 0x80000>; - read-only; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; - pinctrl-names = "default"; - - pmx_power_button: pmx-power-button { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_power_led: pmx-power-led { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_power_led_ctrl: pmx-power-led-ctrl { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; -}; - -&sata { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/orion5x-linkstation-lschl.dts deleted file mode 100644 index ee751995c8d0..000000000000 --- a/arch/arm/boot/dts/orion5x-linkstation-lschl.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-CHLv3 - * - * Copyright (C) 2016 Ash Hughes - * Copyright (C) 2015-2017 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include "mvebu-linkstation-gpio-simple.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include - -/ { - model = "Buffalo Linkstation LiveV3 (LS-CHL)"; - compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - gpio_keys { - func { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>; - blue-power-led { - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - red-alarm-led { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - amber-info-led { - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - - func { - label = "lschl:func:blue:top"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW - &gpio0 16 GPIO_ACTIVE_LOW>; - - alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - pmx_led_power: pmx-leds { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp8", "mpp10", "mpp15"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_func: pmx-leds { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_sw_init: pmx-sw-init { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - diff --git a/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts b/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts deleted file mode 100644 index 9f6fedd39170..000000000000 --- a/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-GL - * (also known as Buffalo Linkstation Pro/Live) - * - * Copyright (C) 2016 - * Roger Shimizu - * - * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c - * Copyright (C) Ronen Shitrit - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include - -/ { - model = "Buffalo Linkstation Pro/Live"; - compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; - -&ehci1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts b/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts deleted file mode 100644 index 7f77ce8cc1fc..000000000000 --- a/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WTGL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include "mvebu-linkstation-gpio-simple.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include - -/ { - model = "Buffalo Linkstation LS-WTGL"; - compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 64 MB */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - gpio_keys { - power-on-switch { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - blue-power-led { - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - red-alarm-led { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - amber-info-led { - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW - &gpio0 17 GPIO_ACTIVE_LOW>; - - alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - pmx_led_power: pmx-leds { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp8", "mpp10"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; diff --git a/arch/arm/boot/dts/orion5x-linkstation.dtsi b/arch/arm/boot/dts/orion5x-linkstation.dtsi deleted file mode 100644 index b6c9b85951ea..000000000000 --- a/arch/arm/boot/dts/orion5x-linkstation.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Device Tree common file for orion5x based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "orion5x-mv88f5182.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,function = "gpio"; - }; -}; - -&devbus_bootcs { - status = "okay"; - devbus,keep-config; - - flash@0 { - compatible = "jedec-flash"; - reg = <0 0x40000>; - bank-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - header@0 { - reg = <0 0x30000>; - read-only; - }; - - uboot@30000 { - reg = <0x30000 0xF000>; - read-only; - }; - - uboot_env@3F000 { - reg = <0x3F000 0x1000>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c { - status = "okay"; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; -}; - -&wdt { - status = "disabled"; -}; - -&sata { - status = "okay"; - nr-ports = <1>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts deleted file mode 100644 index 2fbc17d6dfa4..000000000000 --- a/arch/arm/boot/dts/orion5x-lswsgl.dts +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (C) 2015 Benjamin Cama - * Copyright (C) 2014 Thomas Petazzoni - * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c, - * Copyright (C) 2008 Alexey Kopytko - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Buffalo Linkstation Mini (LS-WSGL)"; - compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - func { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - power { - label = "Power-on Switch"; - linux,input-type = <5>; /* EV_SW */ - linux,code = ; /* LSMINI_SW_POWER */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - - autopower { - label = "Power-auto Switch"; - linux,input-type = <5>; /* EV_SW */ - linux,code = ; /* LSMINI_SW_AUTOPOWER */ - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func - &pmx_led_power>; - pinctrl-names = "default"; - - alarm { - label = "lswsgl:alarm:red"; - gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lswsgl:info:amber"; - gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - - func { - label = "lswsgl:func:blue:top"; - gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lswsgl:power:blue:bottom"; - gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>; - pinctrl-names = "default"; - - sata0_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; - }; - - usb_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x40000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full256Kb"; - reg = <0 0x40000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; -}; - -&pinctrl { - pmx_buttons: pmx-buttons { - marvell,pins = "mpp15", "mpp17", "mpp18"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_led_func: pmx-leds { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_led_power: pmx-leds { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_sata0_power: pmx-sata0-power { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_sata1_power: pmx-sata1-power { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts deleted file mode 100644 index d57859998350..000000000000 --- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Thomas Petazzoni - * Copyright (C) Sylver Bruneau - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Maxtor Shared Storage II"; - compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - power { - label = "Power"; - linux,code = ; - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x40000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@68 { - compatible = "st,m41t81"; - reg = <0x68>; - pinctrl-0 = <&pmx_rtc>; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_leds &pmx_misc>; - pinctrl-names = "default"; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp11", "mpp12"; - marvell,function = "gpio"; - }; - - /* - * MPP0: Power LED - * MPP1: Error LED - */ - pmx_leds: pmx-leds { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "gpio"; - }; - - /* - * MPP4: HDD ind. (Single/Dual) - * MPP5: HD0 5V control - * MPP6: HD0 12V control - * MPP7: HD1 5V control - * MPP8: HD1 12V control - */ - pmx_misc: pmx-misc { - marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_sata0_led_active: pmx-sata0-led-active { - marvell,pins = "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata1_led_active: pmx-sata1-led-active { - marvell,pins = "mpp15"; - marvell,function = "sata1"; - }; - - /* - * Non MPP GPIOs: - * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) - * GPIO 23: Blue front LED off - * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) - */ -}; - -&sata { - pinctrl-0 = <&pmx_sata0_led_active - &pmx_sata1_led_active>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi deleted file mode 100644 index 819f9efb7058..000000000000 --- a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2016 Jamie Lentin - -#include "orion5x.dtsi" - -/ { - compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; - - soc { - compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; - - internal-regs { - pinctrl: pinctrl@10000 { - compatible = "marvell,88f5181-pinctrl"; - reg = <0x10000 0x8>, <0x10050 0x4>; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,mv88f5181-core-clock"; - reg = <0x10010 0x4>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x1500 0x20>; - }; - }; - }; -}; - -&pinctrl { - pmx_ge: pmx-ge { - marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19"; - marvell,function = "ge"; - }; -}; - -ð { - pinctrl-0 = <&pmx_ge>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi deleted file mode 100644 index 86b87fb26dc9..000000000000 --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2014 Thomas Petazzoni - -#include "orion5x.dtsi" - -/ { - compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; - - soc { - compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; - - internal-regs { - pinctrl: pinctrl@10000 { - compatible = "marvell,88f5182-pinctrl"; - reg = <0x10000 0x8>, <0x10050 0x4>; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp12", "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp13", "mpp15"; - marvell,function = "sata1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,mv88f5182-core-clock"; - reg = <0x10010 0x4>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x1500 0x20>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts deleted file mode 100644 index fb203e7d37f5..000000000000 --- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2016 Jamie Lentin - -/dts-v1/; - -#include -#include -#include "orion5x-mv88f5181.dtsi" - -/ { - model = "Netgear WNR854-t"; - compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", - "marvell,orion5x"; - aliases { - serial0 = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x2000000>; /* 32 MB */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_reset_button>; - pinctrl-names = "default"; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; - pinctrl-names = "default"; - - led@0 { - label = "wnr854t:green:power"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - led@1 { - label = "wnr854t:blink:power"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - led@2 { - label = "wnr854t:green:wan"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x800000>; - bank-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "rootfs"; - reg = <0x100000 0x660000>; - }; - - partition@760000 { - label = "uboot_env"; - reg = <0x760000 0x20000>; - }; - - partition@780000 { - label = "uboot"; - reg = <0x780000 0x80000>; - read-only; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&lan3phy>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&lan4phy>; - }; - - port@2 { - reg = <2>; - label = "wan"; - phy-handle = <&wanphy>; - }; - - port@3 { - reg = <3>; - ethernet = <ðport>; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@5 { - reg = <5>; - label = "lan1"; - phy-handle = <&lan1phy>; - }; - - port@7 { - reg = <7>; - label = "lan2"; - phy-handle = <&lan2phy>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - lan3phy: ethernet-phy@0 { - /* Marvell 88E1121R (port 1) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan4phy: ethernet-phy@1 { - /* Marvell 88E1121R (port 2) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - wanphy: ethernet-phy@2 { - /* Marvell 88E1121R (port 1) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <2>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan1phy: ethernet-phy@5 { - /* Marvell 88E1112 */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <5>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan2phy: ethernet-phy@7 { - /* Marvell 88E1112 */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <7>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - }; - }; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - /* Hardwired to DSA switch */ - speed = <1000>; - duplex = <1>; - phy-mode = "rgmii"; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_pci_gpios>; - pinctrl-names = "default"; - - pmx_power_led: pmx-power-led { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_led_blink: pmx-power-led-blink { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_wan_led: pmx-wan-led { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_pci_gpios: pmx-pci-gpios { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts deleted file mode 100644 index fd78aa02a3c5..000000000000 --- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2014 Thomas Petazzoni - -/dts-v1/; - -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Marvell Reference Design 88F5182 NAS"; - compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - , - ; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_debug_led>; - pinctrl-names = "default"; - - led@0 { - label = "rd88f5182:cpu"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - }; -}; - -&devbus_cs1 { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <1>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@68 { - pinctrl-0 = <&pmx_rtc>; - pinctrl-names = "default"; - compatible = "dallas,ds1338"; - reg = <0x68>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios - &pmx_pci_gpios>; - pinctrl-names = "default"; - - /* - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication - * MPP[23] USB 1 over current indication - * MPP[24] USB 1 over current enable - * MPP[25] USB 0 over current enable - */ - - pmx_debug_led: pmx-debug_led { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_reset_switch: pmx-reset-switch { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_misc_gpios: pmx-misc-gpios { - marvell,pins = "mpp4", "mpp5"; - marvell,function = "gpio"; - }; - - pmx_pci_gpios: pmx-pci-gpios { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "gpio"; - }; -}; - -&sata { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi deleted file mode 100644 index 2d41f5c166ee..000000000000 --- a/arch/arm/boot/dts/orion5x.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2012 Thomas Petazzoni - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Marvell Orion5x SoC"; - compatible = "marvell,orion5x"; - interrupt-parent = <&intc>; - - aliases { - gpio0 = &gpio0; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <6>, <7>, <8>, <9>; - }; - - spi: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - status = "disabled"; - }; - - i2c: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <3>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <4>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <4>; - }; - - intc: interrupt-controller@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x08>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&core_clk 0>; - status = "okay"; - }; - - ehci0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <17>; - status = "disabled"; - }; - - xor: dma-controller@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; - - xor00 { - interrupts = <30>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <31>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethport: ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <21>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; - }; - - cesa: crypto@90000 { - compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <28>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - ehci1: ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - }; - - crypto_sram: sa-sram { - compatible = "mmio-sram"; - reg = ; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts deleted file mode 100644 index c2b02895910c..000000000000 --- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Cubietech CubieBoard6 - * - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "owl-s500.dtsi" - -/ { - compatible = "cubietech,cubieboard6", "actions,s500"; - model = "CubieBoard6"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts deleted file mode 100644 index 7ae34a23e320..000000000000 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Andreas Färber - */ - -/dts-v1/; - -#include "owl-s500-guitar.dtsi" - -/ { - compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500"; - model = "LeMaker Guitar Base Board rev. B"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/owl-s500-guitar.dtsi b/arch/arm/boot/dts/owl-s500-guitar.dtsi deleted file mode 100644 index 81cc39871f17..000000000000 --- a/arch/arm/boot/dts/owl-s500-guitar.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * LeMaker Guitar SoM - * - * Copyright (c) 2016-2017 Andreas Färber - */ - -#include "owl-s500.dtsi" - -/ { - compatible = "lemaker,guitar", "actions,s500"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&timer { - clocks = <&hosc>; -}; diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts deleted file mode 100644 index 1585e33f703b..000000000000 --- a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Caninos Labrador Base Board - * - * Copyright (c) 2019-2020 Matheus Castello - */ - -/dts-v1/; - -#include "owl-s500-labrador-v2.dtsi" - -/ { - model = "Caninos Labrador Core v2 on Labrador Base-M v1"; - compatible = "caninos,labrador-base-m", - "caninos,labrador-v2", "actions,s500"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi deleted file mode 100644 index 883ff2f9886d..000000000000 --- a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Caninos Labrador SoM V2 - * - * Copyright (c) 2019-2020 Matheus Castello - */ - -#include "owl-s500.dtsi" - -/ { - model = "Caninos Labrador Core V2.1"; - compatible = "caninos,labrador-v2", "actions,s500"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; -}; - -&timer { - clocks = <&hosc>; -}; diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts deleted file mode 100644 index eb555f385283..000000000000 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Roseapple Pi - * - * Copyright (C) 2020-2021 Cristian Ciocaltea - */ - -/dts-v1/; - -#include "owl-s500.dtsi" - -/ { - compatible = "roseapplepi,roseapplepi", "actions,s500"; - model = "Roseapple Pi"; - - aliases { - mmc0 = &mmc0; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; /* 2GB */ - }; - - syspwr: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "SYSPWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - atc260x: pmic@65 { - compatible = "actions,atc2603c"; - reg = <0x65>; - interrupt-parent = <&sirq>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - reset-time-sec = <6>; - - regulators { - compatible = "actions,atc2603c-regulator"; - - dcdc1-supply = <&syspwr>; - dcdc2-supply = <&syspwr>; - dcdc3-supply = <&syspwr>; - ldo1-supply = <&syspwr>; - ldo2-supply = <&syspwr>; - ldo3-supply = <&syspwr>; - ldo5-supply = <&syspwr>; - ldo6-supply = <&syspwr>; - ldo7-supply = <&syspwr>; - ldo8-supply = <&syspwr>; - ldo11-supply = <&syspwr>; - ldo12-supply = <&syspwr>; - switchldo1-supply = <&vcc>; - - vdd_cpu: dcdc1 { - regulator-name = "VDD_CPU"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - vddq: dcdc2 { - regulator-name = "VDDQ"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <2150000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc: dcdc3 { - regulator-name = "VCC"; - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_3v3: ldo1 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - avcc: ldo2 { - regulator-name = "AVCC"; - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8: ldo3 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vcc_3v1: ldo5 { - regulator-name = "VCC_3V1"; - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <3300000>; - }; - - avdd: ldo6 { - regulator-name = "AVDD"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - sens_1v8: ldo7 { - regulator-name = "SENS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8: ldo8 { - regulator-name = "LDO8"; - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3300000>; - }; - - svcc: ldo11 { - regulator-name = "SVCC"; - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - rtc_vdd: ldo12 { - regulator-name = "RTC_VDD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sd_vcc: switchldo1 { - regulator-name = "SD_VCC"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; -}; - -&i2c2 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&pinctrl { - i2c0_pins: i2c0-pins { - pinmux { - groups = "i2c0_mfp"; - function = "i2c0"; - }; - - pinconf { - pins = "i2c0_sclk", "i2c0_sdata"; - bias-pull-up; - }; - }; - - i2c1_pins: i2c1-pins { - pinconf { - pins = "i2c1_sclk", "i2c1_sdata"; - bias-pull-up; - }; - }; - - i2c2_pins: i2c2-pins { - pinconf { - pins = "i2c2_sclk", "i2c2_sdata"; - bias-pull-up; - }; - }; - - mmc0_pins: mmc0-pins { - pinmux { - groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", - "sd0_cmd_mfp", "sd0_clk_mfp"; - function = "sd0"; - }; - - drv-pinconf { - groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; - drive-strength = <8>; - }; - - bias0-pinconf { - pins = "sd0_d0", "sd0_d1", "sd0_d2", - "sd0_d3", "sd0_cmd"; - bias-pull-up; - }; - - bias1-pinconf { - pins = "sd0_clk"; - bias-pull-down; - }; - }; - - ethernet_pins: ethernet-pins { - eth_rmii-pinmux { - groups = "rmii_txd0_mfp", "rmii_txd1_mfp", - "rmii_rxd0_mfp", "rmii_rxd1_mfp", - "rmii_txen_mfp", "rmii_rxen_mfp", - "rmii_crs_dv_mfp", "rmii_ref_clk_mfp"; - function = "eth_rmii"; - }; - - phy_clk-pinmux { - groups = "clko_25m_mfp"; - function = "clko_25m"; - }; - - ref_clk-pinconf { - groups = "rmii_ref_clk_drv"; - drive-strength = <2>; - }; - - }; -}; - -/* uSD */ -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - no-sdio; - no-mmc; - no-1-8-v; - cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <&sd_vcc>; - vqmmc-supply = <&sd_vcc>; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; - phy-mode = "rmii"; - phy-handle = <ð_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&pinctrl 88 GPIO_ACTIVE_LOW>; /* GPIOC24 */ - reset-delay-us = <10000>; - reset-post-delay-us = <150000>; - - eth_phy: ethernet-phy@3 { - reg = <0x3>; - max-speed = <100>; - interrupt-parent = <&sirq>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&twd_timer { - status = "okay"; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts deleted file mode 100644 index 9d8f7336bec0..000000000000 --- a/arch/arm/boot/dts/owl-s500-sparky.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Allo.com Sparky - * - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "owl-s500.dtsi" - -/ { - compatible = "allo,sparky", "actions,s500"; - model = "Allo.com Sparky"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 or 2 GiB */ - }; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi deleted file mode 100644 index 739b4b9cec8c..000000000000 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Actions Semi S500 SoC - * - * Copyright (c) 2016-2017 Andreas Färber - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "actions,s500"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - enable-method = "actions,s500-smp"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x1>; - enable-method = "actions,s500-smp"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x2>; - enable-method = "actions,s500-smp"; - power-domains = <&sps S500_PD_CPU2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x3>; - enable-method = "actions,s500-smp"; - power-domains = <&sps S500_PD_CPU3>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - hosc: hosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - losc: losc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - scu: scu@b0020000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xb0020000 0x100>; - }; - - global_timer: timer@b0020200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xb0020200 0x100>; - interrupts = ; - status = "disabled"; - }; - - twd_timer: timer@b0020600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xb0020600 0x20>; - interrupts = ; - status = "disabled"; - }; - - twd_wdt: wdt@b0020620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xb0020620 0xe0>; - interrupts = ; - status = "disabled"; - }; - - gic: interrupt-controller@b0021000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xb0021000 0x1000>, - <0xb0020100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - l2: cache-controller@b0022000 { - compatible = "arm,pl310-cache"; - reg = <0xb0022000 0x1000>; - cache-unified; - cache-level = <2>; - interrupts = ; - arm,tag-latency = <3 3 2>; - arm,data-latency = <5 3 3>; - }; - - uart0: serial@b0120000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0120000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART0>; - status = "disabled"; - }; - - uart1: serial@b0122000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0122000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART1>; - status = "disabled"; - }; - - uart2: serial@b0124000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0124000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART2>; - status = "disabled"; - }; - - uart3: serial@b0126000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0126000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART3>; - status = "disabled"; - }; - - uart4: serial@b0128000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0128000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART4>; - status = "disabled"; - }; - - uart5: serial@b012a000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb012a000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART5>; - status = "disabled"; - }; - - uart6: serial@b012c000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb012c000 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART6>; - status = "disabled"; - }; - - cmu: clock-controller@b0160000 { - compatible = "actions,s500-cmu"; - reg = <0xb0160000 0x8000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@b0170000 { - compatible = "actions,s500-i2c"; - reg = <0xb0170000 0x4000>; - clocks = <&cmu CLK_I2C0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@b0174000 { - compatible = "actions,s500-i2c"; - reg = <0xb0174000 0x4000>; - clocks = <&cmu CLK_I2C1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@b0178000 { - compatible = "actions,s500-i2c"; - reg = <0xb0178000 0x4000>; - clocks = <&cmu CLK_I2C2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@b017c000 { - compatible = "actions,s500-i2c"; - reg = <0xb017c000 0x4000>; - clocks = <&cmu CLK_I2C3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sirq: interrupt-controller@b01b0200 { - compatible = "actions,s500-sirq"; - reg = <0xb01b0200 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , /* SIRQ0 */ - , /* SIRQ1 */ - ; /* SIRQ2 */ - }; - - timer: timer@b0168000 { - compatible = "actions,s500-timer"; - reg = <0xb0168000 0x8000>; - interrupts = , - , - , - ; - interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; - }; - - sps: power-controller@b01b0100 { - compatible = "actions,s500-sps"; - reg = <0xb01b0100 0x100>; - #power-domain-cells = <1>; - }; - - pinctrl: pinctrl@b01b0000 { - compatible = "actions,s500-pinctrl"; - reg = <0xb01b0000 0x40>, /* GPIO */ - <0xb01b0040 0x10>, /* Multiplexing Control */ - <0xb01b0060 0x18>, /* PAD Control */ - <0xb01b0080 0xc>; /* PAD Drive Capacity */ - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 132>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , /* GPIOA */ - , /* GPIOB */ - , /* GPIOC */ - , /* GPIOD */ - ; /* GPIOE */ - }; - - dma: dma-controller@b0260000 { - compatible = "actions,s500-dma"; - reg = <0xb0260000 0xd00>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <12>; - dma-requests = <46>; - clocks = <&cmu CLK_DMAC>; - power-domains = <&sps S500_PD_DMA>; - }; - - mmc0: mmc@b0230000 { - compatible = "actions,s500-mmc", "actions,owl-mmc"; - reg = <0xb0230000 0x38>; - interrupts = ; - clocks = <&cmu CLK_SD0>; - resets = <&cmu RESET_SD0>; - dmas = <&dma 2>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc1: mmc@b0234000 { - compatible = "actions,s500-mmc", "actions,owl-mmc"; - reg = <0xb0234000 0x38>; - interrupts = ; - clocks = <&cmu CLK_SD1>; - resets = <&cmu RESET_SD1>; - dmas = <&dma 3>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc2: mmc@b0238000 { - compatible = "actions,s500-mmc", "actions,owl-mmc"; - reg = <0xb0238000 0x38>; - interrupts = ; - clocks = <&cmu CLK_SD2>; - resets = <&cmu RESET_SD2>; - dmas = <&dma 4>; - dma-names = "mmc"; - status = "disabled"; - }; - - ethernet: ethernet@b0310000 { - compatible = "actions,s500-emac", "actions,owl-emac"; - reg = <0xb0310000 0x10000>; - interrupts = ; - clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>; - clock-names = "eth", "rmii"; - resets = <&cmu RESET_ETHERNET>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts deleted file mode 100644 index c349fd3758a6..000000000000 --- a/arch/arm/boot/dts/pm9g45.dts +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * pm9g45.dts - Device Tree file for Ronetix pm9g45 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g45.dtsi" - -/ { - model = "Ronetix pm9g45"; - compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@70000000 { - reg = <0x70000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - pinctrl@fffff200 { - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - }; - - mmc { - pinctrl_board_mmc: mmc0-board { - atmel,pins = - ; /* PD6 gpio CD pin pull_up and deglitch */ - }; - }; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - pinctrl-names = "default"; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 3 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x1A0000>; - }; - - kernel@200000 { - label = "bareboxenv2"; - reg = <0x200000 0x300000>; - }; - - kernel@500000 { - label = "root"; - reg = <0x500000 0x400000>; - }; - - data@900000 { - label = "data"; - reg = <0x900000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@700000 { - status = "okay"; - num-ports = <2>; - }; - - usb1: ehci@800000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "led0"; - gpios = <&pioD 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - led1 { - label = "led1"; - gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - right { - label = "SW4"; - gpios = <&pioE 7 GPIO_ACTIVE_LOW>; - linux,code = <106>; - }; - - up { - label = "SW3"; - gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - linux,code = <103>; - }; - }; -}; diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts deleted file mode 100644 index 8bade6bf395b..000000000000 --- a/arch/arm/boot/dts/pxa168-aspenite.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; -#include "pxa168.dtsi" - -/ { - model = "Marvell PXA168 Aspenite Development Board"; - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x04000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&twsi1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi deleted file mode 100644 index 16212b912b94..000000000000 --- a/arch/arm/boot/dts/pxa168.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - clocks = <&soc_clocks PXA168_CLK_TIMER>; - resets = <&soc_clocks PXA168_CLK_TIMER>; - }; - - uart1: serial@d4017000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4017000 0x1000>; - reg-shift = <2>; - interrupts = <27>; - clocks = <&soc_clocks PXA168_CLK_UART0>; - resets = <&soc_clocks PXA168_CLK_UART0>; - status = "disabled"; - }; - - uart2: serial@d4018000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4018000 0x1000>; - reg-shift = <2>; - interrupts = <28>; - clocks = <&soc_clocks PXA168_CLK_UART1>; - resets = <&soc_clocks PXA168_CLK_UART1>; - status = "disabled"; - }; - - uart3: serial@d4026000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4026000 0x1000>; - reg-shift = <2>; - interrupts = <29>; - clocks = <&soc_clocks PXA168_CLK_UART2>; - resets = <&soc_clocks PXA168_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - clocks = <&soc_clocks PXA168_CLK_GPIO>; - resets = <&soc_clocks PXA168_CLK_GPIO>; - interrupt-names = "gpio_mux"; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA168_CLK_TWSI0>; - resets = <&soc_clocks PXA168_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - clocks = <&soc_clocks PXA168_CLK_TWSI1>; - resets = <&soc_clocks PXA168_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5>, <6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA168_CLK_RTC>; - resets = <&soc_clocks PXA168_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa168-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi deleted file mode 100644 index 5f8300e356ad..000000000000 --- a/arch/arm/boot/dts/pxa25x.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2016 Robert Jarzmik - */ -#include "pxa2xx.dtsi" -#include "dt-bindings/clock/pxa-clock.h" - -/ { - model = "Marvell PXA25x family SoC"; - compatible = "marvell,pxa250"; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa250-core-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - - /* timer oscillator */ - clktimer: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3686400>; - clock-output-names = "ostimer"; - }; - }; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <16>; - dma-channels = <16>; - #dma-requests = <40>; - dma-requests = <40>; - status = "okay"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <32>; - }; - - pinctrl: pinctrl@40e00000 { - reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 - 0x40f00020 0x10>; - compatible = "marvell,pxa25x-pinctrl"; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa25x-gpio"; - gpio-ranges = <&pinctrl 0 0 84>; - clocks = <&clks CLK_NONE>; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - rtc@40900000 { - clocks = <&clks CLK_OSC32k768>; - }; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clktimer>; - status = "okay"; - }; - - pxa250_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - opp-99532800 { - opp-hz = /bits/ 64 <99532800>; - opp-microvolt = <1000000 950000 1650000>; - clock-latency-ns = <20>; - }; - opp-199065600 { - opp-hz = /bits/ 64 <199065600>; - opp-microvolt = <1000000 950000 1650000>; - clock-latency-ns = <20>; - }; - opp-298598400 { - opp-hz = /bits/ 64 <298598400>; - opp-microvolt = <1100000 1045000 1650000>; - clock-latency-ns = <20>; - }; - opp-398131200 { - opp-hz = /bits/ 64 <398131200>; - opp-microvolt = <1300000 1235000 1650000>; - clock-latency-ns = <20>; - }; - }; -}; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi deleted file mode 100644 index a2cbfb3be609..000000000000 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* The pxa3xx skeleton simply augments the 2xx version */ -#include "pxa2xx.dtsi" -#include "dt-bindings/clock/pxa-clock.h" - -/ { - model = "Marvell PXA27x familiy SoC"; - compatible = "marvell,pxa27x"; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <32>; - dma-channels = <32>; - #dma-requests = <75>; - dma-requests = <75>; - status = "okay"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <34>; - }; - - pinctrl: pinctrl@40e00000 { - reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 - 0x40f00020 0x10>; - compatible = "marvell,pxa27x-pinctrl"; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa27x-gpio"; - gpio-ranges = <&pinctrl 0 0 128>; - clocks = <&clks CLK_NONE>; - }; - - usb0: usb@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - clocks = <&clks CLK_USBHOST>; - status = "disabled"; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - pwm2: pwm@40c00000 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40c00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm3: pwm@40c00010 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40c00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - pwri2c: i2c@40f00180 { - compatible = "mrvl,pxa-i2c"; - reg = <0x40f00180 0x24>; - interrupts = <6>; - clocks = <&clks CLK_PWRI2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - pxa27x_udc: udc@40600000 { - compatible = "marvell,pxa270-udc"; - reg = <0x40600000 0x10000>; - interrupts = <11>; - clocks = <&clks CLK_USB>; - status = "disabled"; - }; - - keypad: keypad@41500000 { - compatible = "marvell,pxa27x-keypad"; - reg = <0x41500000 0x4c>; - interrupts = <4>; - clocks = <&clks CLK_KEYPAD>; - status = "disabled"; - }; - - pxa_camera: imaging@50000000 { - compatible = "marvell,pxa270-qci"; - reg = <0x50000000 0x1000>; - interrupts = <33>; - dmas = <&pdma 68 0 /* Y channel */ - &pdma 69 0 /* U channel */ - &pdma 70 0>; /* V channel */ - dma-names = "CI_Y", "CI_U", "CI_V"; - - clocks = <&clks CLK_CAMERA>; - clock-names = "ciclk"; - clock-frequency = <5000000>; - clock-output-names = "qci_mclk"; - - status = "disabled"; - }; - - rtc@40900000 { - clocks = <&clks CLK_OSC32k768>; - }; - }; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa270-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; - - pxa270_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - opp-104000000 { - opp-hz = /bits/ 64 <104000000>; - opp-microvolt = <900000 900000 1705000>; - clock-latency-ns = <20>; - }; - opp-156000000 { - opp-hz = /bits/ 64 <156000000>; - opp-microvolt = <1000000 1000000 1705000>; - clock-latency-ns = <20>; - }; - opp-208000000 { - opp-hz = /bits/ 64 <208000000>; - opp-microvolt = <1180000 1180000 1705000>; - clock-latency-ns = <20>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <1250000 1250000 1705000>; - clock-latency-ns = <20>; - }; - opp-416000000 { - opp-hz = /bits/ 64 <416000000>; - opp-microvolt = <1350000 1350000 1705000>; - clock-latency-ns = <20>; - }; - opp-520000000 { - opp-hz = /bits/ 64 <520000000>; - opp-microvolt = <1450000 1450000 1705000>; - clock-latency-ns = <20>; - }; - opp-624000000 { - opp-hz = /bits/ 64 <624000000>; - opp-microvolt = <1550000 1550000 1705000>; - clock-latency-ns = <20>; - }; - }; -}; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi deleted file mode 100644 index 84154c43fe65..000000000000 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC - * - * Copyright (C) 2011 Marek Vasut - */ - -#include "dt-bindings/clock/pxa-clock.h" - -#define PMGROUP(pin) #pin -#define PMMUX(func, pin, af) \ - mux- ## func { \ - groups = PMGROUP(P ## pin); \ - function = #af; \ - } -#define PMMUX_LPM_LOW(func, pin, af) \ - mux- ## func { \ - groups = PMGROUP(P ## pin); \ - function = #af; \ - low-power-disable; \ - } -#define PMMUX_LPM_HIGH(func, pin, af) \ - mux- ## func { \ - groups = PMGROUP(P ## pin); \ - function = #af; \ - low-power-enable; \ - } - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Marvell PXA2xx family SoC"; - compatible = "marvell,pxa2xx"; - interrupt-parent = <&pxairq>; - - aliases { - serial0 = &ffuart; - serial1 = &btuart; - serial2 = &stuart; - serial3 = &hwuart; - i2c0 = &pwri2c; - i2c1 = &pxai2c1; - }; - - cpus { - cpu { - compatible = "marvell,xscale"; - device_type = "cpu"; - }; - }; - - pxabus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pxairq: interrupt-controller@40d00000 { - #interrupt-cells = <1>; - compatible = "marvell,pxa-intc"; - interrupt-controller; - interrupt-parent; - marvell,intc-nr-irqs = <32>; - reg = <0x40d00000 0xd0>; - }; - - gpio: gpio@40e00000 { - compatible = "mrvl,pxa-gpio"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x40e00000 0x10000>; - gpio-controller; - #gpio-cells = <0x2>; - interrupts = <8>, <9>, <10>; - interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupt-controller; - #interrupt-cells = <0x2>; - ranges; - - gcb0: gpio@40e00000 { - reg = <0x40e00000 0x4>; - }; - - gcb1: gpio@40e00004 { - reg = <0x40e00004 0x4>; - }; - - gcb2: gpio@40e00008 { - reg = <0x40e00008 0x4>; - }; - gcb3: gpio@40e0000c { - reg = <0x40e0000c 0x4>; - }; - }; - - ffuart: serial@40100000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40100000 0x30>; - interrupts = <22>; - clocks = <&clks CLK_FFUART>; - status = "disabled"; - }; - - btuart: serial@40200000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40200000 0x30>; - interrupts = <21>; - clocks = <&clks CLK_BTUART>; - status = "disabled"; - }; - - stuart: serial@40700000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40700000 0x30>; - interrupts = <20>; - clocks = <&clks CLK_STUART>; - status = "disabled"; - }; - - hwuart: serial@41600000 { - compatible = "mrvl,pxa-uart"; - reg = <0x41600000 0x30>; - interrupts = <7>; - status = "disabled"; - }; - - pxai2c1: i2c@40301680 { - compatible = "mrvl,pxa-i2c"; - reg = <0x40301680 0x30>; - interrupts = <18>; - clocks = <&clks CLK_I2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - clocks = <&clks CLK_MMC>; - dmas = <&pdma 21 3 - &pdma 22 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@40900000 { - compatible = "marvell,pxa-rtc"; - reg = <0x40900000 0x3c>; - interrupts = <30 31>; - }; - - lcdc: lcd-controller@40500000 { - compatible = "marvell,pxa2xx-lcdc"; - reg = <0x44000000 0x10000>; - interrupts = <17>; - clocks = <&clks CLK_LCD>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi deleted file mode 100644 index 147c99191dc2..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "pxa3xx.dtsi" -#include -#include -#include - -/ { - /* Will be overridden by bootloader */ - hw-revision = <0>; - - chosen { - bootargs = "root=ubi0:RootFS rootfstype=ubifs rw ubi.mtd=3"; - stdout-path = &ffuart; - }; - - memory { - device_type = "memory"; - reg = <0xa0000000 0x8000000>; /* 128 MB */ - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8-fixed-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_va_5v0: regulator-va-5v0 { - compatible = "regulator-fixed"; - regulator-name = "va-5v0-fixed-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 124 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ssp_dai0: ssp-dai0 { - compatible = "mrvl,pxa-ssp-dai"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_dai_pins>; - port = <&ssp1>; - #sound-dai-cells = <0>; - dmas = <&pdma 13 3 - &pdma 14 3>; - dma-names = "rx", "tx"; - clock-names = "extclk"; - }; - - ssp_dai1: ssp-dai1 { - compatible = "mrvl,pxa-ssp-dai"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp1_dai_pins>; - port = <&ssp2>; - #sound-dai-cells = <0>; - dmas = <&pdma 15 3 - &pdma 16 3>; - dma-names = "rx", "tx"; - clock-names = "extclk"; - }; - - spi: spi { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - gpio-sck = <&gpio 95 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio 98 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio 97 GPIO_ACTIVE_HIGH>; - cs-gpios = < - &gpio 34 GPIO_ACTIVE_HIGH - &gpio 125 GPIO_ACTIVE_HIGH - &gpio 96 GPIO_ACTIVE_HIGH - >; - num-chipselects = <3>; - - dac: dac@2 { - compatible = "ti,dac7512"; - reg = <2>; - spi-max-frequency = <1000000>; - vcc-supply = <®_3v3>; - }; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - - on-off { - label = "on_off button"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - rescue-boot { - label = "rescue boot button"; - gpios = <&gpio 115 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - - setup { - label = "setup"; - gpios = <&gpio 119 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - rotary: rotary-encoder { - compatible = "rotary-encoder"; - gpios = < - &gpio 19 GPIO_ACTIVE_LOW - &gpio 20 GPIO_ACTIVE_HIGH - >; - linux,axis = ; - rotary-encoder,relative-axis; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a &led_pins_b>; - - left { - label = "raumfeld:1"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - - right { - label = "raumfeld:2"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - }; - }; - - poweroff { - compatible = "gpio-poweroff"; - pinctrl-names = "default"; - pinctrl-0 = <&poweroff_pins>; - gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - }; - - mmc0_pwrseq: mmc-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pwrseq_pins>; - reset-gpios = < - &gpio 113 GPIO_ACTIVE_LOW /* W2W_RESET */ - &gpio 114 GPIO_ACTIVE_LOW /* W2W_PDN */ - >; - }; - - ethernet: ethernet@10000000 { - compatible = "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc_pins &smsc_bus_pins>; - reg = <0x10000000 0x100000>; - phy-mode = "mii"; - interrupt-parent = <&gpio>; - interrupts = <40 IRQ_TYPE_EDGE_FALLING>; - vdd33a-supply = <®_3v3>; - vddvario-supply = <®_1v8>; - reset-gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - reg-io-width = <4>; - smsc,save-mac-address; - smsc,irq-push-pull; - }; -}; - -&ffuart { - status = "okay"; -}; - -&pwri2c { - status = "okay"; - - max8660: regulator@34 { - compatible = "maxim,max8660"; - reg = <0x34>; - - regulators { - regulator-v3 { - regulator-compatible = "V3(DCDC)"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1800000>; - }; - - regulator-v4 { - regulator-compatible = "V4(DCDC)"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1800000>; - }; - - regulator-v5 { - regulator-compatible = "V5(LDO)"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2000000>; - }; - - reg_vcc_sdio: regulator-v6 { - regulator-compatible = "V6(LDO)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - regulator-v7 { - regulator-compatible = "V7(LDO)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&pxai2c1 { - status = "okay"; - mrvl,i2c-fast-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pxai2c1_pins>; -}; - -&ssp1 { - status = "okay"; -}; - -&ssp2 { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - nand-rb = <0>; - nand-ecc-mode = "hw"; - marvell,nand-keep-config; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Bootloader"; - reg = <0x0000000 0xa0000>; - read-only; - }; - - partition@a0000 { - label = "BootloaderEnvironment"; - reg = <0x0a0000 0x20000>; - }; - - partition@c0000 { - label = "BootloaderSplashScreen"; - reg = <0x0c0000 0x60000>; - }; - - partition@120000 { - label = "UBI"; - reg = <0x120000 0x7ee0000>; - }; - }; - }; -}; - -&usb0 { - status = "okay"; - marvell,enable-port1; - marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ - pinctrl-names = "default"; - pinctrl-0 = <&pxa3xx_ohci_pins>; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - pxa-mmc,detect-delay-ms = <200>; - vmmc-supply = <®_vcc_sdio>; - mmc-pwrseq = <&mmc0_pwrseq>; - non-removable; - bus-width = <4>; -}; - -&pinctrl { - poweroff_pins: poweroff-pins { - pinctrl-single,pins = ; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - led_pins_a: led-pins-a { - pinctrl-single,pins = ; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - led_pins_b: led-pins-b { - pinctrl-single,pins = ; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); - }; - - pxai2c1_pins: pxai2c1-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(21) MFP_AF1 /* I2C_SCL */ - MFP_PIN_PXA300(22) MFP_AF1 /* I2C_SDA */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); - }; - - gpio_keys_pins: gpio-keys-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(14) MFP_AF0 /* on-off */ - MFP_PIN_PXA300(115) MFP_AF0 /* rescue boot */ - MFP_PIN_PXA300(119) MFP_AF0 /* setup */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - spi_pins: spi-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(95) MFP_AF0 /* SCK */ - MFP_PIN_PXA300(97) MFP_AF0 /* MOSI */ - MFP_PIN_PXA300(98) MFP_AF0 /* MISO */ - MFP_PIN_PXA300(34) MFP_AF0 /* CS#0 */ - MFP_PIN_PXA300(125) MFP_AF0 /* CS#1 */ - MFP_PIN_PXA300(96) MFP_AF0 /* CS#2 */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - pxa3xx_ohci_pins: pxa3xx-ohci-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300_2(0) MFP_AF1 /* USBHPEN */ - MFP_PIN_PXA300_2(1) MFP_AF1 /* USBHPWR */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - smsc_pins: smsc-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(39) MFP_AF0 /* RESET */ - MFP_PIN_PXA300(40) MFP_AF0 /* IRQ */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - smsc_bus_pins: smsc-bus-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(1) MFP_AF1 /* nCS2 */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - mmc0_pins: mmc0-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(3) MFP_AF4 /* MMC1_DAT0 */ - MFP_PIN_PXA300(4) MFP_AF4 /* MMC1_DAT1 */ - MFP_PIN_PXA300(5) MFP_AF4 /* MMC1_DAT2 */ - MFP_PIN_PXA300(6) MFP_AF4 /* MMC1_DAT3 */ - MFP_PIN_PXA300(7) MFP_AF4 /* MMC1_CLK */ - MFP_PIN_PXA300(8) MFP_AF4 /* MMC1_CMD */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); - }; - - mmc0_pwrseq_pins: mmc0-pwrseq-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(113) MFP_AF0 /* W2W_RESET */ - MFP_PIN_PXA300(114) MFP_AF0 /* W2W_PDN */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - ssp0_dai_pins: ssp0-dai-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(85) MFP_AF1 /* SSP1_SCLK */ - MFP_PIN_PXA300(86) MFP_AF1 /* SSP1_FRM */ - MFP_PIN_PXA300(87) MFP_AF1 /* SSP1_TXD */ - MFP_PIN_PXA300(88) MFP_AF1 /* SSP1_RXD */ - MFP_PIN_PXA300(89) MFP_AF1 /* SSP1_EXTCLK */ - MFP_PIN_PXA300(90) MFP_AF1 /* SSP1_SYSCLK */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - ssp1_dai_pins: ssp1-dai-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(25) MFP_AF2 /* SSP2_SCLK */ - MFP_PIN_PXA300(26) MFP_AF2 /* SSP2_FRM */ - MFP_PIN_PXA300(27) MFP_AF2 /* SSP2_TXD */ - MFP_PIN_PXA300(29) MFP_AF2 /* SSP2_EXTCLK */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-connector.dts b/arch/arm/boot/dts/pxa300-raumfeld-connector.dts deleted file mode 100644 index 3e9445419e39..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-connector.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Connector (PXA3xx)"; - compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300"; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Raumfeld Connector"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "i2s"; - bitclock-master = <&dailink_master_analog>; - frame-master = <&dailink_master_analog>; - mclk-fs = <256>; - - dailink_master_analog: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&cs4270>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - format = "i2s"; - bitclock-master = <&dailink_master_digital>; - frame-master = <&dailink_master_digital>; - mclk-fs = <256>; - - dailink_master_digital: cpu { - sound-dai = <&ssp_dai1>; - }; - - codec { - sound-dai = <&ak4104>; - }; - }; - }; -}; - -&ssp1 { - status = "okay"; -}; - -&ssp2 { - status = "okay"; -}; - -&spi { - ak4104: optical-transmitter@0 { - compatible = "asahi-kasei,ak4104"; - reg = <0>; - vdd-supply = <®_3v3>; - spi-max-frequency = <5000000>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; -}; - -&rotary { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts b/arch/arm/boot/dts/pxa300-raumfeld-controller.dts deleted file mode 100644 index 12b15945ac6d..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" - -/ { - model = "Raumfeld Controller (PXA3xx)"; - compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300"; - - reg_vbatt: regulator-vbatt { - compatible = "regulator-fixed"; - regulator-name = "vbatt-fixed-supply"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - lcd_supply: regulator-va-tft { - compatible = "regulator-fixed"; - regulator-name = "va-tft-fixed-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&w1_pins>; - gpios = < - &gpio 126 GPIO_OPEN_DRAIN /* W1 I/O */ - &gpio 105 GPIO_ACTIVE_HIGH /* pullup */ - >; - - w1_ds2760: slave-ds2760 { - compatible = "maxim,ds2760"; - power-supplies = <&charger>; - }; - }; - - charger: charger { - pinctrl-names = "default"; - pinctrl-0 = <&charger_pins>; - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio 101 GPIO_ACTIVE_LOW>; - }; - - /* - * One of the following two will be set to "okay" by the bootloader, - * depending on the hardware revision. - */ - backlight-controller-pwm { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - pwms = <&pwm0 10000>; - power-supply = <®_vbatt>; - status = "disabled"; - - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; - - backlight-controller { - compatible = "lltc,lt3593"; - pinctrl-names = "default"; - pinctrl-0 = <<3593_pins>; - lltc,ctrl-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - led { - label = "backlight"; - default-state = "on"; - }; - }; -}; - -®_va_5v0 { - status = "disabled"; -}; - -ðernet { - status = "disabled"; -}; - -&leds { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&pwm0 { - status = "okay"; -}; - -&keys { - pinctrl-0 = <&gpio_keys_pins &dock_detect_pins>; - dock-detect { - label = "dock detect"; - gpios = <&gpio 116 GPIO_ACTIVE_LOW>; - linux,code = ; - }; -}; - -&spi { - accelerometer@1 { - compatible = "st,lis302dl-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&lis302_pins>; - reg = <1>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <104 IRQ_TYPE_EDGE_FALLING>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - }; -}; - -&lcdc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc_pins>; - lcd-supply = <&lcd_supply>; - - port { - lcdc_out: endpoint { - remote-endpoint = <&panel_in>; - bus-width = <16>; - }; - }; - - panel { - compatible = "sharp,lq043t3dx0-panel"; - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <9009000>; - pixelclk-active = <0>; /* negative edge */ - hactive = <480>; - vactive = <272>; - hsync-len = <41>; - hback-porch = <2>; - hfront-porch = <1>; - vsync-len = <10>; - vback-porch = <3>; - vfront-porch = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdc_out>; - }; - }; - }; -}; - -&gcu { - status = "okay"; -}; - -&pxai2c1 { - touchscreen@a { - compatible = "eeti,exc3000-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&eeti_ts_pins>; - reg = <0xa>; - interrupt-parent = <&gpio>; - interrupts = <32 IRQ_TYPE_EDGE_RISING>; - attn-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-y; - }; -}; - -&pinctrl { - lis302_pins: lis302-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(104) MFP_AF0 /* IRQ */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - eeti_ts_pins: eeti-ts-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(32) MFP_AF0 /* IRQ */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - lt3593_pins: lt3593-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(17) MFP_AF0 /* Backlight */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - pwm0_pins: pwm0-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(17) MFP_AF1 /* PWM */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - w1_pins: w1-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(126) MFP_AF0 /* PWM */ - MFP_PIN_PXA300(105) MFP_AF0 /* PWM */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - charger_pins: charger_pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(31) MFP_AF0 /* PEN2 */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); - pinctrl-single,bias-pullup = MPF_PULL_UP; - }; - - dock_detect_pins: dock_detect_pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(116) MFP_AF0 /* DOCK_DETECT */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); - pinctrl-single,bias-pullup = MPF_PULL_UP; - }; - - lcdc_pins: lcdc-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */ - MFP_PIN_PXA300(55) MFP_AF1 /* LDD_1 */ - MFP_PIN_PXA300(56) MFP_AF1 /* LDD_2 */ - MFP_PIN_PXA300(57) MFP_AF1 /* LDD_3 */ - MFP_PIN_PXA300(58) MFP_AF1 /* LDD_4 */ - MFP_PIN_PXA300(59) MFP_AF1 /* LDD_5 */ - MFP_PIN_PXA300(60) MFP_AF1 /* LDD_6 */ - MFP_PIN_PXA300(61) MFP_AF1 /* LDD_7 */ - MFP_PIN_PXA300(62) MFP_AF1 /* LDD_8 */ - MFP_PIN_PXA300(63) MFP_AF1 /* LDD_9 */ - MFP_PIN_PXA300(64) MFP_AF1 /* LDD_10 */ - MFP_PIN_PXA300(65) MFP_AF1 /* LDD_11 */ - MFP_PIN_PXA300(66) MFP_AF1 /* LDD_12 */ - MFP_PIN_PXA300(67) MFP_AF1 /* LDD_13 */ - MFP_PIN_PXA300(68) MFP_AF1 /* LDD_14 */ - MFP_PIN_PXA300(69) MFP_AF1 /* LDD_15 */ - MFP_PIN_PXA300(70) MFP_AF1 /* LDD_16 */ - MFP_PIN_PXA300(71) MFP_AF1 /* LDD_17 */ - MFP_PIN_PXA300(72) MFP_AF1 /* LCD_FCLK */ - MFP_PIN_PXA300(73) MFP_AF1 /* LCD_LCLK */ - MFP_PIN_PXA300(74) MFP_AF1 /* LCD_PCLK */ - MFP_PIN_PXA300(75) MFP_AF1 /* LCD_BIAS */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts deleted file mode 100644 index 5a0f7f17856f..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Speaker L (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-l-pxa303", "marvell,pxa300"; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts deleted file mode 100644 index fa10d896282c..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Speaker M (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-m-pxa303", "marvell,pxa300"; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts deleted file mode 100644 index a70560a8ea92..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" - -/ { - model = "Raumfeld Speaker One (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300"; - - wm8782: wm8782 { - compatible = "wm8782"; - #sound-dai-cells = <0>; - Vdd-supply = <®_3v3>; - Vdda-supply = <®_va_5v0>; - }; - - xo_11mhz: oscillator-11mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - clock-accuracy = <100>; - }; - - xo_audio: clock-gate { - compatible = "gpio-gate-clock"; - pinctrlnames = "default"; - pinctrl-0 = <&xo_audio_pins>; - clocks = <&xo_11mhz>; - #clock-cells = <0>; - enable-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; - }; - - reg_va_30v0: regulator-va-30v0 { - compatible = "regulator-fixed"; - regulator-name = "va-30v0-fixed-supply"; - regulator-min-microvolt = <30000000>; - regulator-max-microvolt = <30000000>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Raumfeld Speaker"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "i2s"; - bitclock-master = <&dailink_master_analog_out>; - frame-master = <&dailink_master_analog_out>; - mclk-fs = <256>; - - dailink_master_analog_out: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&sta320>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - format = "i2s"; - bitclock-master = <&dailink_master_analog_in>; - frame-master = <&dailink_master_analog_in>; - mclk-fs = <256>; - - dailink_master_analog_in: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&wm8782>; - }; - }; - }; -}; - -&ssp_dai0 { - clocks = <&xo_audio>; -}; - -&spi { - dac@2 { - compatible = "ti,dac7512"; - reg = <2>; - spi-max-frequency = <1000000>; - vcc-supply = <®_3v3>; - }; -}; - -&rotary { - status = "okay"; -}; - -&pxai2c1 { - sta320: codec@1a { - compatible = "st,sta32x"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&sta320_pins>; - clocks = <&xo_audio>; - clock-names = "xti"; - reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; - Vdda-supply = <®_3v3>; - Vdd3-supply = <®_3v3>; - Vcc-supply = <®_va_30v0>; - #sound-dai-cells = <0>; - st,thermal-warning-adjustment; - st,thermal-warning-recovery; - st,fault-detect-recovery; - st,drop-compensation-ns = <80>; - st,max-power-use-mpcc; - st,invalid-input-detect-mute; - /* 2 (half-bridge) and 1 (full-bridge) on-board power */ - st,output-conf = /bits/ 8 <0x1>; - st,ch1-output-mapping = /bits/ 8 <0>; - st,ch2-output-mapping = /bits/ 8 <1>; - st,ch3-output-mapping = /bits/ 8 <2>; - st,needs_esd_watchdog; - }; -}; - -&pinctrl { - xo_audio_pins: xo-audio-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(111) MFP_AF0 /* ENABLE */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - sta320_pins: sta320-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(120) MFP_AF0 /* CODEC_RESET */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts deleted file mode 100644 index 36e20cbf8704..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Speaker S (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-s-pxa303", "marvell,pxa300"; -}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi deleted file mode 100644 index 561483b93989..000000000000 --- a/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -/ { - xo_27mhz: oscillator-27mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-accuracy = <100>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Raumfeld Speaker"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "i2s"; - bitclock-master = <&dailink_master_analog>; - frame-master = <&dailink_master_analog>; - mclk-fs = <256>; - - dailink_master_analog: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&cs4270>; - }; - }; - }; -}; - -&ssp_dai0 { - clocks = <&max9485 MAX9485_CLKOUT1>; -}; - -&ssp_dai1 { - clocks = <&max9485 MAX9485_CLKOUT1>; -}; - -&pxai2c1 { - cs4270: codec@48 { - compatible = "cirrus,cs4270"; - pinctrl-names = "default"; - pinctrl-0 = <&cs4270_pins>; - reg = <0x48>; - va-supply = <®_va_5v0>; - vd-supply = <®_3v3>; - vlc-supply = <®_3v3>; - reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; - - max9485: clock-generator@63 { - compatible = "maxim,max9485"; - pinctrl-names = "default"; - pinctrl-0 = <&max9485_pins>; - reg = <0x63>; - vdd-supply = <®_3v3>; - clock-names = "xclk"; - clocks = <&xo_27mhz>; - reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; - #clock-cells = <1>; - }; -}; - -&pinctrl { - cs4270_pins: cs4270-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(120) MFP_AF0 /* RESET */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - max9485_pins: max9485-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(111) MFP_AF0 /* RESET */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; -}; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi deleted file mode 100644 index f9c216f91865..000000000000 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* The pxa3xx skeleton simply augments the 2xx version */ -#include "pxa2xx.dtsi" - -#define MFP_PIN_PXA300(gpio) \ - ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ - (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ - (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - 0) -#define MFP_PIN_PXA300_2(gpio) \ - ((gpio <= 1) ? (0x674 + 4 * gpio) : \ - (gpio <= 6) ? (0x2dc + 4 * gpio) : \ - 0) - -#define MFP_PIN_PXA310(gpio) \ - ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ - (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ - (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - (gpio <= 262) ? 0 : \ - (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ - 0) -#define MFP_PIN_PXA310_2(gpio) \ - ((gpio <= 1) ? (0x674 + 4 * gpio) : \ - (gpio <= 6) ? (0x2dc + 4 * gpio) : \ - (gpio <= 10) ? (0x52c + 4 * gpio) : \ - 0) - -#define MFP_PIN_PXA320(gpio) \ - ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ - (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ - (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ - (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ - (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ - (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ - (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - 0) -#define MFP_PIN_PXA320_2(gpio) \ - ((gpio <= 3) ? (0x674 + 4 * gpio) : \ - (gpio <= 5) ? (0x284 + 4 * gpio) : \ - 0) - -/* - * MFP Alternate functions for pins having a gpio. - * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > - */ -#define MFP_AF0 (0 << 0) -#define MFP_AF1 (1 << 0) -#define MFP_AF2 (2 << 0) -#define MFP_AF3 (3 << 0) -#define MFP_AF4 (4 << 0) -#define MFP_AF5 (5 << 0) -#define MFP_AF6 (6 << 0) - -/* - * MFP drive strength functions for pins. - * Example of use: pinctrl-single,drive-strength = MFP_DS03X; - */ -#define MFP_DSMSK (0x7 << 10) -#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > -#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > -#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > -#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > -#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > -#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > -#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > -#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > - -/* - * MFP bias pull mode for pins. - * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; - */ -#define MPF_PULL_MSK (0x7 << 13) -#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > -#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > - -/* - * MFP low power mode for pins. - * Example of use: - * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); - * - * Table that determines the low power modes outputs, with actual settings - * used in parentheses for don't-care values. Except for the float output, - * the configured driven and pulled levels match, so if there is a need for - * non-LPM pulled output, the same configuration could probably be used. - * - * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel - * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) - * - * Input 0 X(0) X(0) X(0) 0 - * Drive 0 0 0 0 X(1) 0 - * Drive 1 0 1 X(1) 0 0 - * Pull hi (1) 1 X(1) 1 0 0 - * Pull lo (0) 1 X(0) 0 1 0 - * Z (float) 1 X(0) 0 0 0 - */ -#define MFP_LPM(x) < (x) MFP_LPM_MSK > - -#define MFP_LPM_MSK 0xe1f0 -#define MFP_LPM_INPUT 0x0000 -#define MFP_LPM_DRIVE_LOW 0x2000 -#define MFP_LPM_DRIVE_HIGH 0x4100 -#define MFP_LPM_PULL_LOW 0x2080 -#define MFP_LPM_PULL_HIGH 0x4180 -#define MFP_LPM_FLOAT 0x0080 - -#define MFP_LPM_EDGE_NONE 0x0000 -#define MFP_LPM_EDGE_RISE 0x0010 -#define MFP_LPM_EDGE_FALL 0x0020 -#define MFP_LPM_EDGE_BOTH 0x0030 - -/ { - model = "Marvell PXA3xx familiy SoC"; - compatible = "marvell,pxa3xx"; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-cells = <2>; - /* For backwards compatibility: */ - #dma-channels = <32>; - dma-channels = <32>; - #dma-requests = <100>; - dma-requests = <100>; - status = "okay"; - }; - - pwri2c: i2c@40f500c0 { - compatible = "mrvl,pwri2c"; - reg = <0x40f500c0 0x30>; - interrupts = <6>; - clocks = <&clks CLK_PWRI2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - nand_controller: nand-controller@43100000 { - compatible = "marvell,pxa3xx-nand-controller"; - reg = <0x43100000 90>; - interrupts = <45>; - clocks = <&clks CLK_NAND>; - clock-names = "core"; - dmas = <&pdma 97 3>; - dma-names = "data"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <56>; - }; - - pinctrl: pinctrl@40e10000 { - compatible = "pinconf-single"; - reg = <0x40e10000 0xffff>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7>; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa3xx-gpio"; - reg = <0x40e00000 0x10000>; - clocks = <&clks CLK_GPIO>; - gpio-ranges = <&pinctrl 0 0 128>; - interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8>, <9>, <10>; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - clocks = <&clks CLK_MMC1>; - dmas = <&pdma 21 3 - &pdma 22 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mmc1: mmc@42000000 { - compatible = "marvell,pxa-mmc"; - reg = <0x42000000 0x1000>; - interrupts = <41>; - clocks = <&clks CLK_MMC2>; - dmas = <&pdma 93 3 - &pdma 94 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mmc2: mmc@42500000 { - compatible = "marvell,pxa-mmc"; - reg = <0x42500000 0x1000>; - interrupts = <55>; - clocks = <&clks CLK_MMC3>; - dmas = <&pdma 46 3 - &pdma 47 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usb0: usb@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - clocks = <&clks CLK_USBH>; - status = "disabled"; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - status = "disabled"; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - status = "disabled"; - }; - - pwm2: pwm@40c00000 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40c00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - status = "disabled"; - }; - - pwm3: pwm@40c00010 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40c00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - status = "disabled"; - }; - - ssp1: ssp@41000000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41000000 0x40>; - interrupts = <24>; - clocks = <&clks CLK_SSP1>; - status = "disabled"; - }; - - ssp2: ssp@41700000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41700000 0x40>; - interrupts = <16>; - clocks = <&clks CLK_SSP2>; - status = "disabled"; - }; - - ssp3: ssp@41900000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41900000 0x40>; - interrupts = <0>; - clocks = <&clks CLK_SSP3>; - status = "disabled"; - }; - - ssp4: ssp@41a00000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41a00000 0x40>; - interrupts = <13>; - clocks = <&clks CLK_SSP4>; - status = "disabled"; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; - - gcu: display-controller@54000000 { - compatible = "marvell,pxa300-gcu"; - reg = <0x54000000 0x1000>; - interrupts = <39>; - clocks = <&clks CLK_PXA300_GCU>; - status = "disabled"; - }; - }; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: clocks { - compatible = "marvell,pxa300-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts deleted file mode 100644 index ce76158867c7..000000000000 --- a/arch/arm/boot/dts/pxa910-dkb.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; -#include "pxa910.dtsi" - -/ { - model = "Marvell PXA910 DKB Development Board"; - compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x10000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&twsi1 { - status = "okay"; - - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - interrupts = <4>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <1>; - - marvell,88pm860x-irq-read-clr; - marvell,88pm860x-slave-addr = <0x11>; - - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - rtc { - marvell,88pm860x-vrtc = <1>; - }; - touch { - marvell,88pm860x-gpadc-prebias = <1>; - marvell,88pm860x-gpadc-slot-cycle = <1>; - marvell,88pm860x-tsi-prebias = <6>; - marvell,88pm860x-pen-prebias = <16>; - marvell,88pm860x-pen-prechg = <2>; - marvell,88pm860x-resistor-X = <300>; - }; - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; - }; - leds { - led0-red { - marvell,88pm860x-iset = <12>; - }; - led0-green { - marvell,88pm860x-iset = <12>; - }; - led0-blue { - marvell,88pm860x-iset = <12>; - }; - }; - }; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi deleted file mode 100644 index 352a39357810..000000000000 --- a/arch/arm/boot/dts/pxa910.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - timer1: timer@d4016000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4016000 0x100>; - interrupts = <29>; - status = "disabled"; - }; - - uart1: serial@d4017000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4017000 0x1000>; - reg-shift = <2>; - interrupts = <27>; - clocks = <&soc_clocks PXA910_CLK_UART0>; - resets = <&soc_clocks PXA910_CLK_UART0>; - status = "disabled"; - }; - - uart2: serial@d4018000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4018000 0x1000>; - reg-shift = <2>; - interrupts = <28>; - clocks = <&soc_clocks PXA910_CLK_UART1>; - resets = <&soc_clocks PXA910_CLK_UART1>; - status = "disabled"; - }; - - uart3: serial@d4036000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0xd4036000 0x1000>; - reg-shift = <2>; - interrupts = <59>; - clocks = <&soc_clocks PXA910_CLK_UART2>; - resets = <&soc_clocks PXA910_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks PXA910_CLK_GPIO>; - resets = <&soc_clocks PXA910_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA910_CLK_TWSI0>; - resets = <&soc_clocks PXA910_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4037000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4037000 0x1000>; - interrupts = <54>; - clocks = <&soc_clocks PXA910_CLK_TWSI1>; - resets = <&soc_clocks PXA910_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5>, <6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA910_CLK_RTC>; - resets = <&soc_clocks PXA910_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa910-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>, - <0xd403b000 0x1000>; - reg-names = "mpmu", "apmu", "apbc", "apbcp"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom-apq8016-sbc.dts deleted file mode 100644 index 4ccd2dca74a2..000000000000 --- a/arch/arm/boot/dts/qcom-apq8016-sbc.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "arm64/qcom/apq8016-sbc.dts" diff --git a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts deleted file mode 100644 index 7a80e1c9f126..000000000000 --- a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2022, Luca Weiss - */ - -/dts-v1/; - -#include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" - -/delete-node/ &adsp_region; - -/ { - model = "ASUS ZenWatch 2"; - compatible = "asus,sparrow", "qcom,apq8026"; - chassis-type = "watch"; - qcom,msm-id = <199 0x20000>; - qcom,board-id = <8 3005>; - - reserved-memory { - sbl_region: sbl@2f00000 { - reg = <0x02f00000 0x100000>; - no-map; - }; - external_image_region: external-image@3100000 { - reg = <0x3100000 0x200000>; - no-map; - }; - peripheral_region: peripheral@3300000 { - reg = <0x3300000 0x600000>; - no-map; - }; - adsp_region: adsp@3900000 { - reg = <0x3900000 0x1400000>; - no-map; - }; - modem_region: modem@4d00000 { - reg = <0x4d00000 0x1b00000>; - no-map; - }; - modem_efs_region: modem-efs@7f00000 { - reg = <0x7f00000 0x100000>; - no-map; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_default_state>; - }; -}; - -&adsp { - status = "okay"; -}; - -&blsp1_uart1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart1_default_state>; - - bluetooth { - compatible = "brcm,bcm43430a1-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_state>; - - host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; - }; -}; - -&pm8226_vib { - status = "okay"; -}; - -&rpm_requests { - regulators { - compatible = "qcom,rpm-pm8226-regulators"; - - pm8226_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - pm8226_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2200000>; - }; - pm8226_s5: s5 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - pm8226_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - pm8226_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - pm8226_l3: l3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1337500>; - }; - pm8226_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - pm8226_l5: l5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - pm8226_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l7: l7 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - }; - pm8226_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l14: l14 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - pm8226_l15: l15 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - pm8226_l16: l16 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - pm8226_l17: l17 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l18: l18 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l19: l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - pm8226_l20: l20 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - pm8226_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l22: l22 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l23: l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l24: l24 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - pm8226_l25: l25 { - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <2125000>; - }; - pm8226_l26: l26 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - pm8226_l27: l27 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - pm8226_l28: l28 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_lvs1: lvs1 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8226_l17>; - vqmmc-supply = <&pm8226_l6>; - - bus-width = <8>; - non-removable; -}; - -&sdhc_3 { - status = "okay"; - - max-frequency = <100000000>; - non-removable; - - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8226_l6>; - - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_hostwake_default_state>; - }; -}; - -&smbb { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <350000>; - qcom,fast-charge-safe-voltage = <4430000>; - qcom,fast-charge-high-threshold-voltage = <4400000>; - qcom,auto-recharge-threshold-voltage = <4300000>; - qcom,minimum-input-voltage = <4400000>; -}; - -&tlmm { - blsp1_uart1_default_state: blsp1-uart1-default-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - drive-strength = <8>; - bias-disable; - }; - - bluetooth_default_state: bluetooth-default-state { - pins = "gpio48", "gpio61"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - input-enable; - }; - - wlan_hostwake_default_state: wlan-hostwake-default-state { - pins = "gpio46"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - wlan_regulator_default_state: wlan-regulator-default-state { - pins = "gpio35"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&usb { - status = "okay"; - extcon = <&smbb>; - dr_mode = "peripheral"; -}; - -&usb_hs_phy { - extcon = <&smbb>; - v1p8-supply = <&pm8226_l10>; - v3p3-supply = <&pm8226_l20>; -}; diff --git a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts deleted file mode 100644 index eb73b992a696..000000000000 --- a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2022, Luca Weiss - */ - -/dts-v1/; - -#include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" -#include - -/delete-node/ &adsp_region; - -/ { - model = "Huawei Watch"; - compatible = "huawei,sturgeon", "qcom,apq8026"; - chassis-type = "watch"; - qcom,msm-id = <199 0x20000>; - qcom,board-id = <8 4>; - - reserved-memory { - sbl_region: sbl@2f00000 { - reg = <0x02f00000 0x100000>; - no-map; - }; - - external_image_region: external-image@3100000 { - reg = <0x3100000 0x200000>; - no-map; - }; - - peripheral_region: peripheral@3300000 { - reg = <0x3300000 0x600000>; - no-map; - }; - - adsp_region: adsp@3900000 { - reg = <0x3900000 0x1400000>; - no-map; - }; - - modem_region: modem@4d00000 { - reg = <0x4d00000 0x1b00000>; - no-map; - }; - - modem_efs_region: modem-efs@7f00000 { - reg = <0x7f00000 0x100000>; - no-map; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_default_state>; - }; -}; - -&adsp { - status = "okay"; -}; - -&blsp1_i2c2 { - clock-frequency = <384000>; - - status = "okay"; - - vibrator@5a { - compatible = "ti,drv2605"; - reg = <0x5a>; - enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; - - mode = ; - library-sel = ; - vib-rated-mv = <2765>; - vib-overdrive-mv = <3525>; - - pinctrl-0 = <&vibrator_default_state>; - pinctrl-names = "default"; - }; -}; - -&blsp1_i2c5 { - clock-frequency = <384000>; - - status = "okay"; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8226_l19>; - vio-supply = <&pm8226_lvs1>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_default_state>; - - syna,startup-delay-ms = <160>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; -}; - -&blsp1_uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart4_default_state>; - - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43430a0-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_state>; - - host-wakeup-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; - }; -}; - -&rpm_requests { - regulators { - compatible = "qcom,rpm-pm8226-regulators"; - - pm8226_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2200000>; - }; - - pm8226_s5: s5 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - pm8226_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8226_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l3: l3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1337500>; - }; - - pm8226_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l5: l5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - }; - - pm8226_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l9: l9 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8226_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l14: l14 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - pm8226_l15: l15 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8226_l16: l16 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3350000>; - }; - - pm8226_l17: l17 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l18: l18 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l19: l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8226_l20: l20 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8226_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l22: l22 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l23: l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l24: l24 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - pm8226_l25: l25 { - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <2125000>; - }; - - pm8226_l26: l26 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8226_l27: l27 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8226_l28: l28 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_lvs1: lvs1 {}; - }; -}; - -&sdhc_1 { - vmmc-supply = <&pm8226_l17>; - vqmmc-supply = <&pm8226_l6>; - - bus-width = <8>; - non-removable; - - status = "okay"; -}; - -&sdhc_3 { - max-frequency = <100000000>; - non-removable; - - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8226_l6>; - - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_hostwake_default_state>; - }; -}; - -&smbb { - qcom,fast-charge-safe-voltage = <4370000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,minimum-input-voltage = <4350000>; - qcom,fast-charge-current-limit = <300000>; - qcom,fast-charge-safe-current = <600000>; - qcom,auto-recharge-threshold-voltage = <4240000>; -}; - -&tlmm { - blsp1_uart4_default_state: blsp1-uart4-default-state { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "blsp_uart4"; - drive-strength = <8>; - bias-disable; - }; - - bluetooth_default_state: bluetooth-default-state { - pins = "gpio63", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - touch_default_state: touch-default-state { - irq-pins { - pins = "gpio17"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; - - reset-pins { - pins = "gpio16"; - function = "gpio"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - vibrator_default_state: vibrator-default-state { - pins = "gpio59", "gpio60"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - wlan_hostwake_default_state: wlan-hostwake-default-state { - pins = "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - wlan_regulator_default_state: wlan-regulator-default-state { - pins = "gpio110"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; -}; - -&usb { - extcon = <&smbb>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb_hs_phy { - extcon = <&smbb>; - v1p8-supply = <&pm8226_l10>; - v3p3-supply = <&pm8226_l20>; -}; diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts deleted file mode 100644 index b82381229adf..000000000000 --- a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Luca Weiss - */ - -/dts-v1/; - -#include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" - -/delete-node/ &adsp_region; - -/ { - model = "LG G Watch R"; - compatible = "lg,lenok", "qcom,apq8026"; - chassis-type = "watch"; - qcom,board-id = <132 0x0a>; - qcom,msm-id = <199 0x20000>; - - aliases { - serial0 = &blsp1_uart3; - serial1 = &blsp1_uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - sbl_region: sbl@2f00000 { - reg = <0x02f00000 0x100000>; - no-map; - }; - - external_image_region: external-image@3100000 { - reg = <0x03100000 0x200000>; - no-map; - }; - - adsp_region: adsp@3300000 { - reg = <0x03300000 0x1400000>; - no-map; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_default_state>; - }; -}; - -&adsp { - status = "okay"; -}; - -&blsp1_i2c1 { - status = "okay"; - - fuel-gauge@55 { - compatible = "ti,bq27421"; - reg = <0x55>; - }; -}; - -&blsp1_i2c5 { - status = "okay"; - clock-frequency = <384000>; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8226_l15>; - vio-supply = <&pm8226_l22>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pins>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; - -&blsp1_uart4 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart4_default_state>; - - bluetooth { - compatible = "brcm,bcm43430a0-bt"; - - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_state>; - - host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; - }; -}; - -&rpm_requests { - regulators { - compatible = "qcom,rpm-pm8226-regulators"; - - pm8226_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - }; - pm8226_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2200000>; - }; - pm8226_s5: s5 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - pm8226_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - pm8226_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - pm8226_l3: l3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1337500>; - }; - pm8226_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - pm8226_l5: l5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - pm8226_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - }; - pm8226_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l9: l9 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - pm8226_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l14: l14 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - pm8226_l15: l15 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - pm8226_l16: l16 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3350000>; - }; - pm8226_l17: l17 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l18: l18 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - pm8226_l19: l19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - pm8226_l20: l20 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - pm8226_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l22: l22 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - pm8226_l23: l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - pm8226_l24: l24 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - pm8226_l25: l25 { - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <2125000>; - }; - pm8226_l26: l26 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - pm8226_l27: l27 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - pm8226_l28: l28 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_lvs1: lvs1 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8226_l17>; - vqmmc-supply = <&pm8226_l6>; - - bus-width = <8>; - non-removable; -}; - -&sdhc_3 { - status = "okay"; - - max-frequency = <100000000>; - non-removable; - - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8226_l6>; - - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_hostwake_default_state>; - }; -}; - -&smbb { - qcom,fast-charge-safe-current = <450000>; - qcom,fast-charge-current-limit = <400000>; - qcom,fast-charge-safe-voltage = <4350000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,auto-recharge-threshold-voltage = <4240000>; - qcom,minimum-input-voltage = <4450000>; -}; - -&tlmm { - blsp1_uart4_default_state: blsp1-uart4-default-state { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "blsp_uart4"; - drive-strength = <8>; - bias-disable; - }; - - bluetooth_default_state: bluetooth-default-state { - pins = "gpio47", "gpio48"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - touch_pins: touch-state { - irq-pins { - pins = "gpio17"; - function = "gpio"; - - drive-strength = <8>; - bias-pull-down; - input-enable; - }; - - reset-pins { - pins = "gpio16"; - function = "gpio"; - - drive-strength = <8>; - bias-disable; - output-high; - }; - }; - - wlan_hostwake_default_state: wlan-hostwake-default-state { - pins = "gpio37"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - wlan_regulator_default_state: wlan-regulator-default-state { - pins = "gpio46"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&usb { - status = "okay"; - extcon = <&smbb>; - dr_mode = "peripheral"; -}; - -&usb_hs_phy { - extcon = <&smbb>; - v1p8-supply = <&pm8226_l10>; - v3p3-supply = <&pm8226_l20>; -}; diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts deleted file mode 100644 index 884d99297d4c..000000000000 --- a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2022, Matti Lehtimäki - */ - -/dts-v1/; - -#include -#include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" - -/delete-node/ &adsp_region; -/delete-node/ &smem_region; - -/ { - model = "Samsung Galaxy Tab 4 10.1"; - compatible = "samsung,matisse-wifi", "qcom,apq8026"; - chassis-type = "tablet"; - - aliases { - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - display0 = &framebuffer0; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - stdout-path = "display0"; - - framebuffer0: framebuffer@3200000 { - compatible = "simple-framebuffer"; - reg = <0x03200000 0x800000>; - width = <1280>; - height = <800>; - stride = <(1280 * 3)>; - format = "r8g8b8"; - }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - event-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - interrupts = <&tlmm 110 IRQ_TYPE_EDGE_FALLING>; - linux,input-type = ; - linux,code = ; - debounce-interval = <15>; - wakeup-source; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-home { - label = "Home"; - gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - }; - - i2c-backlight { - compatible = "i2c-gpio"; - sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - pinctrl-0 = <&backlight_i2c_default_state>; - pinctrl-names = "default"; - - i2c-gpio,delay-us = <4>; - - #address-cells = <1>; - #size-cells = <0>; - - backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - - dev-ctrl = /bits/ 8 <0x80>; - init-brt = /bits/ 8 <0x3f>; - - pwms = <&backlight_pwm 0 100000>; - pwm-names = "lp8556"; - - rom-a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0x44>; - }; - - rom-a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x6c>; - }; - - rom-a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x24>; - }; - }; - }; - - backlight_pwm: pwm { - compatible = "clk-pwm"; - #pwm-cells = <2>; - clocks = <&mmcc CAMSS_GP0_CLK>; - pinctrl-0 = <&backlight_pwm_default_state>; - pinctrl-names = "default"; - }; - - reg_tsp_1p8v: regulator-tsp-1p8v { - compatible = "regulator-fixed"; - regulator-name = "tsp_1p8v"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_en_default_state>; - }; - - reg_tsp_3p3v: regulator-tsp-3p3v { - compatible = "regulator-fixed"; - regulator-name = "tsp_3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_en1_default_state>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@3200000 { - reg = <0x03200000 0x800000>; - no-map; - }; - - mpss@8400000 { - reg = <0x08400000 0x1f00000>; - no-map; - }; - - mba@a300000 { - reg = <0x0a300000 0x100000>; - no-map; - }; - - reserved@cb00000 { - reg = <0x0cb00000 0x700000>; - no-map; - }; - - wcnss@d200000 { - reg = <0x0d200000 0x700000>; - no-map; - }; - - adsp_region: adsp@d900000 { - reg = <0x0d900000 0x1800000>; - no-map; - }; - - venus@f100000 { - reg = <0x0f100000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0x0fa00000 0x100000>; - no-map; - }; - - reserved@fb00000 { - reg = <0x0fb00000 0x260000>; - no-map; - }; - - rfsa@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; - }; - }; -}; - -&adsp { - status = "okay"; -}; - -&blsp1_i2c2 { - status = "okay"; - - accelerometer@1d { - compatible = "st,lis2hh12"; - reg = <0x1d>; - - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&accel_int_default_state>; - - st,drdy-int-pin = <1>; - - vdd-supply = <&pm8226_l19>; - vddio-supply = <&pm8226_lvs1>; - }; -}; - -&blsp1_i2c4 { - status = "okay"; - - muic: usb-switch@25 { - compatible = "siliconmitus,sm5502-muic"; - reg = <0x25>; - - interrupt-parent = <&tlmm>; - interrupts = <67 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&muic_int_default_state>; - }; -}; - -&blsp1_i2c5 { - status = "okay"; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - - interrupt-parent = <&tlmm>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_int_rst_default_state>; - - reset-gpios = <&pm8226_gpios 6 GPIO_ACTIVE_LOW>; - - vdd-supply = <®_tsp_1p8v>; - vdda-supply = <®_tsp_3p3v>; - }; -}; - -&rpm_requests { - regulators { - compatible = "qcom,rpm-pm8226-regulators"; - - pm8226_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_s5: s5 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - pm8226_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8226_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l3: l3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1337500>; - regulator-always-on; - }; - - pm8226_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l5: l5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8226_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - }; - - pm8226_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8226_l9: l9 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8226_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l14: l14 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - pm8226_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8226_l16: l16 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3350000>; - }; - - pm8226_l17: l17 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-always-on; - }; - - pm8226_l18: l18 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l19: l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_l20: l20 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8226_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l22: l22 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_l23: l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8226_l24: l24 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - pm8226_l25: l25 { - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <2125000>; - }; - - pm8226_l26: l26 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_l27: l27 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l28: l28 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_lvs1: lvs1 {}; - }; -}; - -&sdhc_1 { - vmmc-supply = <&pm8226_l17>; - vqmmc-supply = <&pm8226_l6>; - - bus-width = <8>; - non-removable; - - status = "okay"; -}; - -&sdhc_2 { - vmmc-supply = <&pm8226_l18>; - vqmmc-supply = <&pm8226_l21>; - - bus-width = <4>; - cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&tlmm { - accel_int_default_state: accel-int-default-state { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - backlight_i2c_default_state: backlight-i2c-default-state { - pins = "gpio20", "gpio21"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - backlight_pwm_default_state: backlight-pwm-default-state { - pins = "gpio33"; - function = "gp0_clk"; - }; - - muic_int_default_state: muic-int-default-state { - pins = "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tsp_en_default_state: tsp-en-default-state { - pins = "gpio31"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tsp_en1_default_state: tsp-en1-default-state { - pins = "gpio73"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tsp_int_rst_default_state: tsp-int-rst-default-state { - pins = "gpio17"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; -}; - -&usb { - extcon = <&muic>, <&muic>; - status = "okay"; -}; - -&usb_hs_phy { - extcon = <&muic>; - v1p8-supply = <&pm8226_l10>; - v3p3-supply = <&pm8226_l20>; -}; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts deleted file mode 100644 index db4c791b2e2f..000000000000 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ /dev/null @@ -1,973 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -#include -#include -#include -#include -#include -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm APQ8060 Dragonboard"; - compatible = "qcom,apq8060-dragonboard", "qcom,msm8660"; - - aliases { - serial0 = &gsbi12_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* Main power of the board: 3.7V */ - vph: regulator-fixed { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-always-on; - regulator-boot-on; - }; - - /* GPIO controlled ethernet power regulator */ - dragon_veth: xc622a331mrg { - compatible = "regulator-fixed"; - regulator-name = "XC6222A331MR-G"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vph>; - gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_veth_gpios>; - regulator-always-on; - }; - - /* VDDvario fixed regulator */ - dragon_vario: nds332p { - compatible = "regulator-fixed"; - regulator-name = "NDS332P"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&pm8058_s3>; - }; - - /* This is a levelshifter for SDCC5 */ - dragon_vio_txb: txb0104rgyr { - compatible = "regulator-fixed"; - regulator-name = "Dragon SDCC levelshifter"; - vin-supply = <&pm8058_l14>; - regulator-always-on; - }; - - /* - * Capella CM3605 light and proximity sensor mounted directly - * on the sensor board. - */ - cm3605 { - compatible = "capella,cm3605"; - vdd-supply = <&pm8058_l14>; // 2.85V - aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>; - capella,aset-resistance-ohms = <100000>; - /* Trig on both edges - getting close or far away */ - interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>; - /* MPP05 analog input to the XOADC */ - io-channels = <&xoadc 0x00 0x05>; - io-channel-names = "aout"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>; - }; -}; - -&ebi2 { - /* The EBI2 will instantiate first, then populate its children */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ebi2_pins>; - status = "okay"; - - /* - * An on-board SMSC LAN9221 chip for "debug ethernet", - * which is actually just an ordinary ethernet on the - * EBI2. This has a 25MHz chrystal next to it, so no - * clocking is needed. - */ - ethernet@2,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <2 0x0 0x100>; - /* - * The second interrupt is the PME interrupt - * for network wakeup, connected to the TLMM. - */ - interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>, - <&tlmm 29 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; - vdd33a-supply = <&dragon_veth>; - vddvario-supply = <&dragon_vario>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ethernet_gpios>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,force-external-phy; - smsc,irq-push-pull; - - /* - * SLOW chipselect config - * Delay 9 cycles (140ns@64MHz) between SMSC - * LAN9221 Ethernet controller reads and writes - * on CS2. - */ - qcom,xmem-recovery-cycles = <0>; - qcom,xmem-write-hold-cycles = <3>; - qcom,xmem-write-delta-cycles = <31>; - qcom,xmem-read-delta-cycles = <28>; - qcom,xmem-write-wait-cycles = <9>; - qcom,xmem-read-wait-cycles = <9>; - }; -}; - -&gsbi3 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi3_i2c { - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi3_i2c_pins>; - status = "okay"; - - touchscreen@24 { - compatible = "cypress,cy8ctma340"; - reg = <0x24>; - /* Certainly we can do at least 400 kHz */ - clock-frequency = <400000>; - /* IRQ on GPIO61 called /CTP_INT */ - interrupt-parent = <&tlmm>; - interrupts = <61 IRQ_TYPE_EDGE_FALLING>; - /* - * The I2C bus is using a PCA9306 level translator from L16A - * to L2B so these two voltages are needed and L16A is - * kind of the IO voltage, however L16Aisn't really fed to - * the TMA340, which relies entirely on L2B (PM8901 L2). - */ - vcpin-supply = <&pm8058_l16>; - vdd-supply = <&pm8901_l2>; - /* GPIO58, called WAKE_CTP */ - reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - active-interval-ms = <0>; - touch-timeout-ms = <255>; - lowpower-interval-ms = <10>; - bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_tma340_gpios>; - }; -}; - -&gsbi8 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi8_i2c { - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi8_i2c_pins>; - status = "okay"; - - eeprom@52 { - /* A 16KiB Platform ID EEPROM on the CPU carrier board */ - compatible = "atmel,24c128"; - reg = <0x52>; - vcc-supply = <&pm8058_s3>; - pagesize = <64>; - }; - wm8903: wm8903@1a { - /* This Woolfson Micro device has an unrouted interrupt line */ - compatible = "wlf,wm8903"; - reg = <0x1a>; - - AVDD-supply = <&pm8058_l16>; - CPVDD-supply = <&pm8058_l16>; - DBVDD-supply = <&pm8058_s3>; - DCVDD-supply = <&pm8058_l0>; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; -}; - -&gsbi12 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi12_serial { - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi12_serial_pins>; - status = "okay"; -}; - -&gsbi12_i2c { - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi12_i2c_pins>; - status = "okay"; - - ak8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - interrupt-parent = <&pm8058_gpio>; - interrupts = <33 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ak8975_gpios>; - vid-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - }; - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&pm8058_gpio>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_bmp085_gpios>; - vddd-supply = <&pm8058_lvs0>; // 1.8V - vdda-supply = <&pm8058_l14>; // 2.85V - }; - mpu3050@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - /* - * GPIO17 is pulled high by a 10k - * resistor to VLOGIC so needs to be - * active low/falling edge. - */ - interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_mpu3050_gpios>; - vlogic-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - - /* - * The MPU-3050 acts as a hub for the - * accelerometer. - */ - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - kxsd9@18 { - compatible = "kionix,kxsd9"; - reg = <0x18>; - interrupt-parent = <&tlmm>; - interrupts = <57 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_kxsd9_gpios>; - iovdd-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - }; - }; - }; -}; - -&pm8058_gpio { - dragon_ethernet_gpios: ethernet-state { - pinconf { - pins = "gpio7"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_bmp085_gpios: bmp085-state { - pinconf { - pins = "gpio16"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_mpu3050_gpios: mpu3050-state { - pinconf { - pins = "gpio17"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_sdcc3_gpios: sdcc3-state { - pinconf { - pins = "gpio22"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_sdcc5_gpios: sdcc5-state { - pinconf { - pins = "gpio26"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = ; - }; - }; - dragon_ak8975_gpios: ak8975-state { - pinconf { - pins = "gpio33"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_cm3605_gpios: cm3605-state { - /* Pin 34 connected to the proxy IRQ */ - gpio34-pins { - pins = "gpio34"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - /* Pin 35 connected to ASET */ - gpio35-pins { - pins = "gpio35"; - function = "normal"; - output-high; - bias-disable; - power-source = ; - }; - }; - dragon_veth_gpios: veth-state { - pinconf { - pins = "gpio40"; - function = "normal"; - bias-disable; - drive-push-pull; - }; - }; -}; - -&pm8058_keypad { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_MENU) - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 3, KEY_4) - MATRIX_KEY(0, 4, KEY_7) - MATRIX_KEY(1, 0, KEY_UP) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_5) - MATRIX_KEY(1, 3, KEY_8) - MATRIX_KEY(2, 0, KEY_HOME) - MATRIX_KEY(2, 1, KEY_REPLY) - MATRIX_KEY(2, 2, KEY_2) - MATRIX_KEY(2, 3, KEY_6) - MATRIX_KEY(3, 0, KEY_VOLUMEUP) - MATRIX_KEY(3, 1, KEY_RIGHT) - MATRIX_KEY(3, 2, KEY_3) - MATRIX_KEY(3, 3, KEY_9) - MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE) - MATRIX_KEY(4, 0, KEY_VOLUMEDOWN) - MATRIX_KEY(4, 1, KEY_BACK) - MATRIX_KEY(4, 2, KEY_CAMERA) - MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; -}; - -&pm8058_led48 { - /* - * The keypad LED @0x48 is routed to - * the sensor board where it is - * connected to an infrared LED - * SFH4650 (60mW, @850nm) next to the - * ambient light and proximity sensor - * Capella Microsystems CM3605. - */ - label = "pm8058:infrared:proximitysensor"; - default-state = "off"; - linux,default-trigger = "cm3605"; - status = "okay"; -}; - -&pm8058_led131 { - label = "pm8058:red"; - color = ; - default-state = "off"; - status = "okay"; -}; - -&pm8058_led132 { - /* - * This is actually green too on my - * board, but documented as yellow. - */ - label = "pm8058:yellow"; - color = ; - default-state = "off"; - linux,default-trigger = "mmc0"; - status = "okay"; -}; - -&pm8058_led133 { - label = "pm8058:green"; - function = LED_FUNCTION_HEARTBEAT; - color = ; - default-state = "on"; - linux,default-trigger = "heartbeat"; - status = "okay"; -}; - -&pm8058_mpps { - dragon_cm3605_mpps: cm3605-mpps-state { - pins = "mpp5"; - function = "analog"; - input-enable; - bias-high-impedance; - /* Let's use channel 5 */ - qcom,amux-route = ; - power-source = ; - }; -}; - -&rpm { - /* - * Set up of the PMIC RPM regulators for this board - * PM8901 supplies "preliminary regulators" whatever - * that means - */ - regulators-0 { - vdd_l0-supply = <&pm8901_s4>; - vdd_l1-supply = <&vph>; - vdd_l2-supply = <&vph>; - vdd_l3-supply = <&vph>; - vdd_l4-supply = <&vph>; - vdd_l5-supply = <&vph>; - vdd_l6-supply = <&vph>; - /* vdd_s0-supply, vdd_s1-supply: SAW regulators */ - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - lvs0_in-supply = <&pm8058_s3>; - lvs1_in-supply = <&pm8901_s4>; - lvs2_in-supply = <&pm8058_l0>; - lvs3_in-supply = <&pm8058_s2>; - mvs_in-supply = <&pm8058_s3>; - - l0 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l2 { - /* TMA340 requires strictly 3.3V */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l4 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l6 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - bias-pull-down; - }; - - /* s0 and s1 are SAW regulators controlled over SPM */ - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* LVS0 thru 3 and mvs are just switches */ - lvs0 { - regulator-always-on; - }; - lvs1 { }; - lvs2 { }; - lvs3 { }; - mvs { }; - - }; - - regulators-1 { - vdd_l0_l1_lvs-supply = <&pm8058_s3>; - vdd_l2_l11_l12-supply = <&vph>; - vdd_l3_l4_l5-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l8-supply = <&vph>; - vdd_l9-supply = <&vph>; - vdd_l10-supply = <&vph>; - vdd_l13_l16-supply = <&pm8058_s4>; - vdd_l14_l15-supply = <&vph>; - vdd_l17_l18-supply = <&vph>; - vdd_l19_l20-supply = <&vph>; - vdd_l21-supply = <&pm8058_s3>; - vdd_l22-supply = <&pm8058_s3>; - vdd_l23_l24_l25-supply = <&pm8058_s3>; - vdd_s0-supply = <&vph>; - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_ncp-supply = <&vph>; - - l0 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l4 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l6 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; - }; - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3050000>; - bias-pull-down; - }; - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l10 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l11 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - bias-pull-down; - }; - l12 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - bias-pull-down; - }; - l13 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - bias-pull-down; - }; - l14 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - l15 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - regulator-always-on; - }; - l17 { - // 1.5V according to schematic - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l18 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - bias-pull-down; - }; - l19 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - bias-pull-down; - }; - l20 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l21 { - // 1.1 V according to schematic - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - regulator-always-on; - }; - l22 { - // 1.2 V according to schematic - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - l23 { - // Unused - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l24 { - // Unused - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l25 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - s0 { - // regulator-min-microvolt = <500000>; - // regulator-max-microvolt = <1325000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s1 { - // regulator-min-microvolt = <500000>; - // regulator-max-microvolt = <1250000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s2 { - // 1.3 V according to schematic - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - regulator-always-on; - bias-pull-down; - }; - s4 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - regulator-always-on; - bias-pull-down; - }; - - /* LVS0 and LVS1 are just switches */ - lvs0 { - bias-pull-down; - }; - lvs1 { - bias-pull-down; - }; - - ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; -}; - -/* Internal 3.69 GiB eMMC */ -&sdcc1 { - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc1_pins>; - vmmc-supply = <&pm8901_l5>; - vqmmc-supply = <&pm8901_lvs0>; - status = "okay"; -}; - -/* External micro SD card, directly connected, pulled up to 2.85 V */ -&sdcc3 { - /* Enable SSBI GPIO 22 as input, use for card detect */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>; - cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&pm8058_l14>; - status = "okay"; -}; - -/* - * Second external micro SD card, using two TXB104RGYR levelshifters - * to lift from 1.8 V to 2.85 V - */ -&sdcc5 { - /* Enable SSBI GPIO 26 as input, use for card detect */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>; - cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>; - wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&pm8058_l14>; - vqmmc-supply = <&dragon_vio_txb>; - status = "okay"; -}; - -&tlmm { - /* eMMC pins, all 8 data lines connected */ - dragon_sdcc1_pins: sdcc1-state { - clk-pins { - pins = "gpio167"; /* SDC1 CLK */ - function = "sdc1"; - drive-strength = <16>; - bias-disable; - }; - cmd-pins { - pins = "gpio168"; /* SDC1 CMD */ - function = "sdc1"; - drive-strength = <10>; - bias-pull-up; - }; - data-pins { - /* SDC1 D0 to D7 */ - pins = "gpio159", "gpio160", "gpio161", "gpio162", - "gpio163", "gpio164", "gpio165", "gpio166"; - function = "sdc1"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - /* - * The SDCC3 pins are hardcoded (non-muxable) but need some pin - * configuration. - */ - dragon_sdcc3_pins: sdcc3-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <8>; - bias-disable; - }; - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - data-pins { - pins = "sdc3_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - /* Second SD card slot pins */ - dragon_sdcc5_pins: sdcc5-state { - clk-pins { - pins = "gpio97"; /* SDC5 CLK */ - function = "sdc5"; - drive-strength = <16>; - bias-disable; - }; - cmd-pins { - pins = "gpio95"; /* SDC5 CMD */ - function = "sdc5"; - drive-strength = <10>; - bias-pull-up; - }; - data-pins { - /* SDC5 D0 to D3 */ - pins = "gpio96", "gpio98", "gpio99", "gpio100"; - function = "sdc5"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - dragon_gsbi3_i2c_pins: gsbi3-i2c-state { - pins = "gpio43", "gpio44"; - function = "gsbi3"; - drive-strength = <8>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; - - dragon_gsbi8_i2c_pins: gsbi8-i2c-state { - pins = "gpio64", "gpio65"; - function = "gsbi8"; - drive-strength = <16>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; - - dragon_gsbi12_i2c_pins: gsbi12-i2c-state { - pins = "gpio115", "gpio116"; - function = "gsbi12"; - drive-strength = <16>; - /* These have external pull-up 4.7kOhm to 1.8V */ - bias-disable; - }; - - /* Primary serial port uart 0 pins */ - dragon_gsbi12_serial_pins: gsbi12-serial-state { - tx-pins { - pins = "gpio117"; - function = "gsbi12"; - drive-strength = <8>; - bias-disable; - }; - rx-pins { - pins = "gpio118"; - function = "gsbi12"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - dragon_ebi2_pins: ebi2-state { - /* - * Pins used by EBI2 on the Dragonboard, actually only - * CS2 is used by a real peripheral. CS0 is just - * routed to a test point. - */ - mux0-pins { - pins = - /* "gpio39", CS1A_N this is not good to mux */ - "gpio40", /* CS2A_N */ - "gpio134"; /* CS0_N testpoint TP29 */ - function = "ebi2cs"; - }; - mux1-pins { - pins = - /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ - "gpio123", "gpio124", "gpio125", "gpio126", - "gpio127", "gpio128", "gpio129", "gpio130", - /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ - "gpio135", "gpio136", "gpio137", "gpio138", - "gpio139", "gpio140", "gpio141", "gpio142", - "gpio143", "gpio144", "gpio145", "gpio146", - "gpio147", "gpio148", "gpio149", "gpio150", - "gpio151", /* EBI2_OE_N */ - "gpio153", /* EBI2_ADV */ - "gpio157"; /* EBI2_WE_N */ - function = "ebi2"; - }; - }; - - /* Interrupt line for the KXSD9 accelerometer */ - dragon_kxsd9_gpios: kxsd9-state { - pins = "gpio57"; /* IRQ line */ - function = "gpio"; - bias-pull-up; - }; - - dragon_tma340_gpios: tma340-state { - reset-pins { - /* RESET line, TS_ATTN, WAKE_CTP */ - pins = "gpio58"; - function = "gpio"; - drive-strength = <6>; - bias-disable; - }; - irq-pins { - pins = "gpio61"; /* IRQ line */ - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&xoadc { - /* Reference voltage 2.2 V */ - xoadc-ref-supply = <&pm8058_l18>; - - /* Board-specific channels */ - mpp5@5 { - /* Connected to AOUT of ALS sensor */ - reg = <0x00 0x05>; - }; - mpp6@6 { - /* Connected to test point TP43 */ - reg = <0x00 0x06>; - }; - mpp7@7 { - /* Connected to battery thermistor */ - reg = <0x00 0x07>; - }; - mpp8@8 { - /* Connected to battery ID detector */ - reg = <0x00 0x08>; - }; - mpp9@9 { - /* Connected to XO thermistor */ - reg = <0x00 0x09>; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts deleted file mode 100644 index c57c27cd8a20..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ /dev/null @@ -1,348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include -/ { - model = "Asus Nexus7(flo)"; - compatible = "asus,nexus7-flo", "qcom,apq8064"; - chassis-type = "tablet"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi6_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@88d00000 { - compatible = "ramoops"; - reg = <0x88d00000 0x100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; - }; - }; - - ext_3p3v: regulator-ext-3p3v { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ext_3p3v"; - regulator-type = "voltage"; - startup-delay-us = <0>; - gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - key-volume-up { - label = "Volume Up"; - gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - key-volume-down { - label = "Volume Down"; - gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - soc { - sram@2a03f000 { - compatible = "qcom,apq8064-imem", "syscon", "simple-mfd"; - reg = <0x2a03f000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - }; -}; - -&dsi0 { - vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ - vdd-supply = <&pm8921_l8>; - vddio-supply = <&pm8921_lvs7>; - avdd-supply = <&pm8921_l11>; - status = "okay"; - - panel@0 { - reg = <0>; - compatible = "jdi,lt070me05000"; - - vddp-supply = <&pm8921_l17>; - iovcc-supply = <&pm8921_lvs7>; - - enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; - reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; - dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_in { - remote-endpoint = <&mdp_dsi1_out>; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ - status = "okay"; -}; - -&gsbi1 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi1_i2c { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; - - bq27541@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - }; - -}; - -&gsbi3 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi3_i2c { - clock-frequency = <200000>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "okay"; - - trackpad@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&gsbi6 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi6_serial { - pinctrl-names = "default"; - pinctrl-0 = <&gsbi6_uart_4pins>; - status = "okay"; -}; - -&gsbi7 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi7_serial { - status = "okay"; -}; - -&mdp { - status = "okay"; -}; - -/* eMMC */ -&sdcc1 { - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - status = "okay"; -}; - -&mdp_dsi1_out { - remote-endpoint = <&dsi0_in>; -}; - -&rpm { - regulators { - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vin_lvs2-supply = <&pm8921_s1>; - - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - vdd_ncp-supply = <&pm8921_l6>; - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - /* msm otg HSUSB_VDDCX */ - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - }; - - /* - * msm_sdcc.1-sdc-vdd_io - * tabla2x-slim-CDC_VDDA_RX - * tabla2x-slim-CDC_VDDA_TX - * tabla2x-slim-CDC_VDD_CP - * tabla2x-slim-VDDIO_CDC - */ - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - /* mipi_dsi.1-dsi1_pll_vdda */ - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* msm_otg-HSUSB_3p3 */ - l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - /* msm_otg-HSUSB_1p8 */ - l4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - /* msm_sdcc.1-sdc_vdd */ - l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - /* mipi_dsi.1-dsi1_avdd */ - l11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-always-on; - }; - - /* pwm_power for backlight */ - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - /* camera, qdsp6 */ - l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - /* - * tabla2x-slim-CDC_VDDA_A_1P2V - * tabla2x-slim-VDDD_CDC_D - */ - l25 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - lvs1 { - bias-pull-down; - }; - - lvs4 { - bias-pull-down; - }; - - lvs5 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - /* - * mipi_dsi.1-dsi1_vddio - * pil_riva-pll_vdd - */ - lvs7 { - bias-pull-down; - }; - }; -}; - -&usb_hs1_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; -}; - -/* OTG */ -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts deleted file mode 100644 index d6ecfd8addb7..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include - -/ { - model = "CompuLab CM-QS600"; - compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sdcc4_pwrseq: pwrseq-sdcc4 { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; - }; - - /* on board fixed 3.3v supply */ - v3p3_fixed: regulator-v3p3 { - compatible = "regulator-fixed"; - regulator-name = "PCIE V3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&gsbi1 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi1_i2c { - clock-frequency = <200000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&gsbi7 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi7_serial { - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - status = "okay"; -}; - -&pcie { - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&v3p3_fixed>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pm8921_gpio { - wlan_default_gpios: wlan-gpios-state { - pinconf { - pins = "gpio43"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; -}; - -&rpm { - regulators { - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - }; -}; - -/* eMMC */ -&sdcc1 { - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - status = "okay"; -}; - -/* External micro SD card */ -&sdcc3 { - vmmc-supply = <&v3p3_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* WLAN */ -&sdcc4 { - status = "okay"; - vmmc-supply = <&v3p3_fixed>; - vqmmc-supply = <&v3p3_fixed>; - mmc-pwrseq = <&sdcc4_pwrseq>; -}; - -&tlmm_pinmux { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; -}; - -&usb_hs1_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; -}; - -&usb_hs3_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; -}; - -&usb_hs4_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; -}; - -/* OTG */ -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb4 { - dr_mode = "host"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts deleted file mode 100644 index 96307550523a..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include - -/ { - model = "Qualcomm APQ8064/IFC6410"; - compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi6_serial; - i2c0 = &gsbi1_i2c; - i2c1 = &gsbi2_i2c; - i2c2 = &gsbi3_i2c; - i2c3 = &gsbi4_i2c; - spi0 = &gsbi5_spi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <¬ify_led>; - - led-user1 { - label = "apq8064:green:user1"; - color = ; - gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "d"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - sdcc4_pwrseq: pwrseq-sdcc4 { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; - }; - - ext_3p3v: regulator-ext-3p3v { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ext_3p3v"; - regulator-type = "voltage"; - startup-delay-us = <0>; - gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&gsbi1 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi1_i2c { - clock-frequency = <200000>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -&gsbi3 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi3_i2c { - status = "okay"; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; -}; - -/* CAM I2C MIPI-CSI connector */ -&gsbi4_i2c { - status = "okay"; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi5_spi { - num-cs = <1>; - cs-gpios = <&tlmm_pinmux 53 0>; - status = "okay"; -}; - -&gsbi6 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi6_serial { - pinctrl-names = "default"; - pinctrl-0 = <&gsbi6_uart_4pins>; - status = "okay"; -}; - -&gsbi7 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi7_serial { - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - status = "okay"; -}; - -&hdmi { - core-vdda-supply = <&pm8921_hdmi_switch>; - hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi_in { - remote-endpoint = <&mdp_dtv_out>; -}; - -&hdmi_out { - remote-endpoint = <&hdmi_con>; -}; - -&hdmi_phy { - status = "okay"; - core-vdda-supply = <&pm8921_hdmi_switch>; -}; - -&mdp { - status = "okay"; -}; - -&mdp_dtv_out { - remote-endpoint = <&hdmi_in>; -}; - -&pcie { - status = "okay"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&ext_3p3v>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; -}; - -&pm8921_gpio { - wlan_default_gpios: wlan-gpios-state { - pinconf { - pins = "gpio43"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - - notify_led: nled-state { - pinconf { - pins = "gpio18"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; -}; - -&rpm { - regulators { - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs1 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata0 { - target-supply = <&pm8921_s4>; - status = "okay"; -}; - -/* eMMC */ -&sdcc1 { - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - status = "okay"; -}; - -/* External micro SD card */ -&sdcc3 { - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* WLAN */ -&sdcc4 { - vmmc-supply = <&ext_3p3v>; - vqmmc-supply = <&pm8921_lvs1>; - mmc-pwrseq = <&sdcc4_pwrseq>; - status = "okay"; -}; - -&tlmm_pinmux { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; -}; - -&usb_hs1_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; -}; - -&usb_hs3_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; -}; - -&usb_hs4_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; -}; - -/* OTG */ -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb4 { - dr_mode = "host"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi deleted file mode 100644 index b4d286a6fab1..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -&tlmm_pinmux { - sdc4_gpios: sdc4-gpios { - pios { - pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "sdc4"; - }; - }; - - sdcc1_pins: sdcc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strengh = <16>; - bias-disable; - }; - - cmd { - pins = "sdc1_cmd"; - drive-strengh = <10>; - bias-pull-up; - }; - - data { - pins = "sdc1_data"; - drive-strengh = <10>; - bias-pull-up; - }; - }; - - sdcc3_pins: sdcc3-pin-active { - clk { - pins = "sdc3_clk"; - drive-strengh = <8>; - bias-disable; - }; - - cmd { - pins = "sdc3_cmd"; - drive-strengh = <8>; - bias-pull-up; - }; - - data { - pins = "sdc3_data"; - drive-strengh = <8>; - bias-pull-up; - }; - }; - - ps_hold: ps_hold { - mux { - pins = "gpio78"; - function = "ps_hold"; - }; - }; - - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c1_pins_sleep: i2c1_pins_sleep { - mux { - pins = "gpio20", "gpio21"; - function = "gpio"; - }; - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable; - }; - }; - - gsbi1_uart_2pins: gsbi1_uart_2pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi1"; - }; - }; - - gsbi1_uart_4pins: gsbi1_uart_4pins { - mux { - pins = "gpio18", "gpio19", "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c2_pins_sleep: i2c2_pins_sleep { - mux { - pins = "gpio24", "gpio25"; - function = "gpio"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi3"; - }; - - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c3_pins_sleep: i2c3_pins_sleep { - mux { - pins = "gpio8", "gpio9"; - function = "gpio"; - }; - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c4_pins: i2c4 { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - }; - - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c4_pins_sleep: i2c4_pins_sleep { - mux { - pins = "gpio12", "gpio13"; - function = "gpio"; - }; - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable; - }; - }; - - spi5_default: spi5_default { - pinmux { - pins = "gpio51", "gpio52", "gpio54"; - function = "gsbi5"; - }; - - pinmux_cs { - function = "gpio"; - pins = "gpio53"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio54"; - drive-strength = <16>; - bias-disable; - }; - - pinconf_cs { - pins = "gpio53"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio16", "gpio17"; - function = "gsbi6"; - }; - - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c6_pins_sleep: i2c6_pins_sleep { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - }; - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable; - }; - }; - - gsbi6_uart_2pins: gsbi6_uart_2pins { - mux { - pins = "gpio14", "gpio15"; - function = "gsbi6"; - }; - }; - - gsbi6_uart_4pins: gsbi6_uart_4pins { - mux { - pins = "gpio14", "gpio15", "gpio16", "gpio17"; - function = "gsbi6"; - }; - }; - - gsbi7_uart_2pins: gsbi7_uart_2pins { - mux { - pins = "gpio82", "gpio83"; - function = "gsbi7"; - }; - }; - - gsbi7_uart_4pins: gsbi7_uart_4pins { - mux { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "gsbi7"; - }; - }; - - i2c7_pins: i2c7 { - mux { - pins = "gpio84", "gpio85"; - function = "gsbi7"; - }; - - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c7_pins_sleep: i2c7_pins_sleep { - mux { - pins = "gpio84", "gpio85"; - function = "gpio"; - }; - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <2>; - bias-disable; - }; - }; - - riva_fm_pin_a: riva-fm-active { - pins = "gpio14", "gpio15"; - function = "riva_fm"; - }; - - riva_bt_pin_a: riva-bt-active { - pins = "gpio16", "gpio17"; - function = "riva_bt"; - }; - - riva_wlan_pin_a: riva-wlan-active { - pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "riva_wlan"; - - drive-strength = <6>; - bias-pull-down; - }; - - hdmi_pinctrl: hdmi-pinctrl { - mux { - pins = "gpio70", "gpio71", "gpio72"; - function = "hdmi"; - }; - - pinconf_ddc { - pins = "gpio70", "gpio71"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf_hpd { - pins = "gpio72"; - bias-pull-down; - drive-strength = <16>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts deleted file mode 100644 index 9244512b74d1..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include -#include - -/ { - model = "Sony Xperia Z"; - compatible = "sony,xperia-yuga", "qcom,apq8064"; - chassis-type = "handset"; - - aliases { - serial0 = &gsbi5_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-camera-focus { - label = "camera_focus"; - gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-volume-down { - label = "volume_down"; - gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi5_serial { - pinctrl-names = "default"; - pinctrl-0 = <&gsbi5_uart_pin_a>; - status = "okay"; -}; - -&pm8921_gpio { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio3", "gpio4", "gpio29", "gpio35"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - input-enable; - power-source = <2>; - qcom,drive-strength = ; - qcom,pull-up-strength = <0>; - }; -}; - -&riva { - pinctrl-names = "default"; - pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; - status = "okay"; -}; - -&rpm { - regulators { - vin_l1_l2_l12_l18-supply = <&pm8921_s4>; - vin_lvs_1_3_6-supply = <&pm8921_s4>; - vin_lvs_4_5_7-supply = <&pm8921_s4>; - vin_ncp-supply = <&pm8921_l6>; - vin_lvs2-supply = <&pm8921_s4>; - vin_l24-supply = <&pm8921_s1>; - vin_l25-supply = <&pm8921_s1>; - vin_l27-supply = <&pm8921_s7>; - vin_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s8 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - }; - - /* PMOS LDO */ - l1 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - bias-pull-down; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l10 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - bias-pull-down; - }; - - l11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - l17 { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - bias-pull-down; - }; - - l18 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l21 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - l22 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - l27 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - l28 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - l29 { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - lvs1 { - bias-pull-down; - }; - - lvs2 { - bias-pull-down; - }; - - lvs3 { - bias-pull-down; - }; - - lvs4 { - bias-pull-down; - }; - - lvs5 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - - usb-switch {}; - - hdmi-switch {}; - - ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; -}; - -&sdcc1 { - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - status = "okay"; -}; - -&sdcc3 { - vmmc-supply = <&pm8921_l6>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; - - status = "okay"; -}; - -&tlmm_pinmux { - gsbi5_uart_pin_a: gsbi5-uart-pin-active { - rx { - pins = "gpio52"; - function = "gsbi5"; - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio51"; - function = "gsbi5"; - drive-strength = <4>; - bias-disable; - }; - }; - - - sdcc3_cd_pin_a: sdcc3-cd-pin-active { - pins = "gpio26"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; -}; - -&usb_hs1_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi deleted file mode 100644 index 46ed48f0244f..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi deleted file mode 100644 index 672b246afbba..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ /dev/null @@ -1,1895 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm APQ8064"; - compatible = "qcom,apq8064"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_region: smem@80000000 { - reg = <0x80000000 0x200000>; - no-map; - }; - - wcnss_mem: wcnss@8f000000 { - reg = <0x8f000000 0x700000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU2: cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU3: cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <400>; - exit-latency-us = <900>; - min-residency-us = <3000>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - coefficients = <1199 0>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - coefficients = <1132 0>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - coefficients = <1199 0>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 10>; - coefficients = <1132 0>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - - hwlocks = <&sfpb_mutex 3>; - }; - - smd { - compatible = "qcom,smd"; - - modem-edge { - interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 3>; - qcom,smd-edge = <0>; - - status = "disabled"; - }; - - q6-edge { - interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 15>; - qcom,smd-edge = <1>; - - status = "disabled"; - }; - - dsps-edge { - interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&sps_sic_non_secure 0x4080 0>; - qcom,smd-edge = <3>; - - status = "disabled"; - }; - - riva-edge { - interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - status = "disabled"; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&l2cc 8 4>; - qcom,ipc-2 = <&l2cc 8 14>; - qcom,ipc-3 = <&l2cc 8 23>; - qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; - - apps_smsm: apps@0 { - reg = <0>; - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - q6_smsm: q6@2 { - reg = <2>; - interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@3 { - reg = <3>; - interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dsps_smsm: dsps@4 { - reg = <4>; - interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-apq8064", "qcom,scm"; - - clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; - clock-names = "core"; - }; - }; - - - /* - * These channels from the ADC are simply hardware monitors. - * That is why the ADC is referred to as "HKADC" - HouseKeeping - * ADC. - */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&xoadc 0x00 0x01>, /* Battery */ - <&xoadc 0x00 0x02>, /* DC in (charger) */ - <&xoadc 0x00 0x04>, /* VPH the main system voltage */ - <&xoadc 0x00 0x0b>, /* Die temperature */ - <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ - <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ - <&xoadc 0x00 0x0e>; /* Charger temperature */ - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - tlmm_pinmux: pinctrl@800000 { - compatible = "qcom,apq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - gpio-ranges = <&tlmm_pinmux 0 0 90>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&ps_hold>; - }; - - sfpb_wrapper_mutex: syscon@1200000 { - compatible = "syscon"; - reg = <0x01200000 0x8000>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - #clock-cells = <0>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu1_aux"; - #clock-cells = <0>; - }; - - acc2: clock-controller@20a8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu2_aux"; - #clock-cells = <0>; - }; - - acc3: clock-controller@20b8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu3_aux"; - #clock-cells = <0>; - }; - - saw0: power-controller@2089000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: power-controller@2099000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw2: power-controller@20a9000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw3: power-controller@20b9000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; - }; - - gsbi1: gsbi@12440000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x12440000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi1_serial: serial@12450000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12450000 0x100>, - <0x12400000 0x03>; - interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi1_i2c: i2c@12460000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x12460000 0x1000>; - interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - }; - - gsbi2: gsbi@12480000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_pins_sleep>; - pinctrl-names = "default", "sleep"; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi3: gsbi@16200000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <3>; - reg = <0x16200000 0x100>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - gsbi3_i2c: i2c@16280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c3_pins>; - pinctrl-1 = <&i2c3_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16280000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI3_QUP_CLK>, - <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi4: gsbi@16300000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x03>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi4_i2c: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c4_pins>; - pinctrl-1 = <&i2c4_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16380000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_QUP_CLK>, - <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi5: gsbi@1a200000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x03>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x100>, - <0x1a200000 0x03>; - interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi5_spi: spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; - pinctrl-names = "default", "sleep"; - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi6: gsbi@16500000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <6>; - reg = <0x16500000 0x03>; - clocks = <&gcc GSBI6_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi6_serial: serial@16540000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16540000 0x100>, - <0x16500000 0x03>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi6_i2c: i2c@16580000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c6_pins>; - pinctrl-1 = <&i2c6_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16580000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_QUP_CLK>, - <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi7_i2c: i2c@16680000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c7_pins>; - pinctrl-1 = <&i2c7_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16680000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_QUP_CLK>, - <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - ssbi@c00000 { - compatible = "qcom,ssbi"; - reg = <0x00c00000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pm8821: pmic { - compatible = "qcom,pm8821"; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <76 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8821_mpps: mpps@50 { - compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; - reg = <0x50>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8821_mpps 0 0 4>; - }; - }; - }; - - ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic { - compatible = "qcom,pm8921"; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <74 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8921_gpio: gpio@150 { - - compatible = "qcom,pm8921-gpio", - "qcom,ssbi-gpio"; - reg = <0x150>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - gpio-ranges = <&pm8921_gpio 0 0 44>; - #gpio-cells = <2>; - - }; - - pm8921_mpps: mpps@50 { - compatible = "qcom,pm8921-mpp", - "qcom,ssbi-mpp"; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8921_mpps 0 0 12>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - xoadc: xoadc@197 { - compatible = "qcom,pm8921-adc"; - reg = <197>; - interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; - #address-cells = <2>; - #size-cells = <0>; - #io-channel-cells = <2>; - - vcoin: adc-channel@0 { - reg = <0x00 0x00>; - }; - vbat: adc-channel@1 { - reg = <0x00 0x01>; - }; - dcin: adc-channel@2 { - reg = <0x00 0x02>; - }; - vph_pwr: adc-channel@4 { - reg = <0x00 0x04>; - }; - batt_therm: adc-channel@8 { - reg = <0x00 0x08>; - }; - batt_id: adc-channel@9 { - reg = <0x00 0x09>; - }; - usb_vbus: adc-channel@a { - reg = <0x00 0x0a>; - }; - die_temp: adc-channel@b { - reg = <0x00 0x0b>; - }; - ref_625mv: adc-channel@c { - reg = <0x00 0x0c>; - }; - ref_1250mv: adc-channel@d { - reg = <0x00 0x0d>; - }; - chg_temp: adc-channel@e { - reg = <0x00 0x0e>; - }; - ref_muxoff: adc-channel@f { - reg = <0x00 0x0f>; - }; - }; - }; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - tsens_calib: calib@404 { - reg = <0x404 0x10>; - }; - tsens_backup: backup_calib@414 { - reg = <0x414 0x10>; - }; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064", "syscon"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&cxo_board>, - <&pxo_board>, - <&lcc PLL4>; - clock-names = "cxo", "pxo", "pll4"; - - tsens: thermal-sensor { - compatible = "qcom,msm8960-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = ; - interrupt-names = "uplow"; - - #qcom,sensors = <11>; - #thermal-sensor-cells = <1>; - }; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-apq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names = "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; - }; - - mmcc: clock-controller@4000000 { - compatible = "qcom,mmcc-apq8064"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, - <&hdmi_phy>; - clock-names = "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - #clock-cells = <0>; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&pxo_board>, <&cxo_board>; - clock-names = "pxo", "cxo"; - }; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - - pm8921_s1: s1 {}; - pm8921_s2: s2 {}; - pm8921_s3: s3 {}; - pm8921_s4: s4 {}; - pm8921_s7: s7 {}; - pm8921_s8: s8 {}; - - pm8921_l1: l1 {}; - pm8921_l2: l2 {}; - pm8921_l3: l3 {}; - pm8921_l4: l4 {}; - pm8921_l5: l5 {}; - pm8921_l6: l6 {}; - pm8921_l7: l7 {}; - pm8921_l8: l8 {}; - pm8921_l9: l9 {}; - pm8921_l10: l10 {}; - pm8921_l11: l11 {}; - pm8921_l12: l12 {}; - pm8921_l14: l14 {}; - pm8921_l15: l15 {}; - pm8921_l16: l16 {}; - pm8921_l17: l17 {}; - pm8921_l18: l18 {}; - pm8921_l21: l21 {}; - pm8921_l22: l22 {}; - pm8921_l23: l23 {}; - pm8921_l24: l24 {}; - pm8921_l25: l25 {}; - pm8921_l26: l26 {}; - pm8921_l27: l27 {}; - pm8921_l28: l28 {}; - pm8921_l29: l29 {}; - - pm8921_lvs1: lvs1 {}; - pm8921_lvs2: lvs2 {}; - pm8921_lvs3: lvs3 {}; - pm8921_lvs4: lvs4 {}; - pm8921_lvs5: lvs5 {}; - pm8921_lvs6: lvs6 {}; - pm8921_lvs7: lvs7 {}; - - pm8921_usb_switch: usb-switch {}; - - pm8921_hdmi_switch: hdmi-switch { - bias-pull-down; - }; - - pm8921_ncp: ncp {}; - }; - }; - - usb1: usb@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x200>, - <0x12500200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS1_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs1_phy>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs1_phy: phy { - compatible = "qcom,usb-hs-phy-apq8064", - "qcom,usb-hs-phy"; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb1 0>; - reset-names = "por"; - #phy-cells = <0>; - }; - }; - }; - - usb3: usb@12520000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12520000 0x200>, - <0x12520200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS3_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs3_phy>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs3_phy: phy { - compatible = "qcom,usb-hs-phy-apq8064", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb3 0>; - reset-names = "por"; - }; - }; - }; - - usb4: usb@12530000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12530000 0x200>, - <0x12530200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS4_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs4_phy>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs4_phy: phy { - compatible = "qcom,usb-hs-phy-apq8064", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb4 0>; - reset-names = "por"; - }; - }; - }; - - sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; - }; - - sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = ; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3bam: dma-controller@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = ; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&sdc4_gpios>; - }; - - sdcc4bam: dma-controller@121c2000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x121c2000 0x8000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC4_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc1bam: dma-controller@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-apq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gpu: adreno-3xx@4300000 { - compatible = "qcom,adreno-320.2", "qcom,adreno"; - reg = <0x04300000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core", - "iface", - "mem", - "mem_iface"; - clocks = - <&mmcc GFX3D_CLK>, - <&mmcc GFX3D_AHB_CLK>, - <&mmcc GFX3D_AXI_CLK>, - <&mmcc MMSS_IMEM_AHB_CLK>; - - iommus = <&gfx3d 0 - &gfx3d 1 - &gfx3d 2 - &gfx3d 3 - &gfx3d 4 - &gfx3d 5 - &gfx3d 6 - &gfx3d 7 - &gfx3d 8 - &gfx3d 9 - &gfx3d 10 - &gfx3d 11 - &gfx3d 12 - &gfx3d 13 - &gfx3d 14 - &gfx3d 15 - &gfx3d 16 - &gfx3d 17 - &gfx3d 18 - &gfx3d 19 - &gfx3d 20 - &gfx3d 21 - &gfx3d 22 - &gfx3d 23 - &gfx3d 24 - &gfx3d 25 - &gfx3d 26 - &gfx3d 27 - &gfx3d 28 - &gfx3d 29 - &gfx3d 30 - &gfx3d 31 - &gfx3d1 0 - &gfx3d1 1 - &gfx3d1 2 - &gfx3d1 3 - &gfx3d1 4 - &gfx3d1 5 - &gfx3d1 6 - &gfx3d1 7 - &gfx3d1 8 - &gfx3d1 9 - &gfx3d1 10 - &gfx3d1 11 - &gfx3d1 12 - &gfx3d1 13 - &gfx3d1 14 - &gfx3d1 15 - &gfx3d1 16 - &gfx3d1 17 - &gfx3d1 18 - &gfx3d1 19 - &gfx3d1 20 - &gfx3d1 21 - &gfx3d1 22 - &gfx3d1 23 - &gfx3d1 24 - &gfx3d1 25 - &gfx3d1 26 - &gfx3d1 27 - &gfx3d1 28 - &gfx3d1 29 - &gfx3d1 30 - &gfx3d1 31>; - - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-450000000 { - opp-hz = /bits/ 64 <450000000>; - }; - - opp-27000000 { - opp-hz = /bits/ 64 <27000000>; - }; - }; - }; - - mmss_sfpb: syscon@5700000 { - compatible = "syscon"; - reg = <0x5700000 0x70>; - }; - - dsi0: dsi@4700000 { - compatible = "qcom,apq8064-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - label = "MDSS DSI CTRL->0"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - reg = <0x04700000 0x200>; - reg-names = "dsi_ctrl"; - - clocks = <&mmcc DSI_M_AHB_CLK>, - <&mmcc DSI_S_AHB_CLK>, - <&mmcc AMP_AHB_CLK>, - <&mmcc DSI_CLK>, - <&mmcc DSI1_BYTE_CLK>, - <&mmcc DSI_PIXEL_CLK>, - <&mmcc DSI1_ESC_CLK>; - clock-names = "iface", "bus", "core_mmss", - "src", "byte", "pixel", - "core"; - - assigned-clocks = <&mmcc DSI1_BYTE_SRC>, - <&mmcc DSI1_ESC_SRC>, - <&mmcc DSI_SRC>, - <&mmcc DSI_PIXEL_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi0_phy 1>; - syscon-sfpb = <&mmss_sfpb>; - phys = <&dsi0_phy>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - - dsi0_phy: phy@4700200 { - compatible = "qcom,dsi-phy-28nm-8960"; - #clock-cells = <1>; - #phy-cells = <0>; - - reg = <0x04700200 0x100>, - <0x04700300 0x200>, - <0x04700500 0x5c>; - reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface", "ref"; - clocks = <&mmcc DSI_M_AHB_CLK>, - <&pxo_board>; - status = "disabled"; - }; - - dsi1: dsi@5800000 { - compatible = "qcom,mdss-dsi-ctrl"; - interrupts = ; - reg = <0x05800000 0x200>; - reg-names = "dsi_ctrl"; - - clocks = <&mmcc DSI2_M_AHB_CLK>, - <&mmcc DSI2_S_AHB_CLK>, - <&mmcc AMP_AHB_CLK>, - <&mmcc DSI2_CLK>, - <&mmcc DSI2_BYTE_CLK>, - <&mmcc DSI2_PIXEL_CLK>, - <&mmcc DSI2_ESC_CLK>; - clock-names = "iface", - "bus", - "core_mmss", - "src", - "byte", - "pixel", - "core"; - - assigned-clocks = <&mmcc DSI2_BYTE_SRC>, - <&mmcc DSI2_ESC_SRC>, - <&mmcc DSI2_SRC>, - <&mmcc DSI2_PIXEL_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 1>; - - syscon-sfpb = <&mmss_sfpb>; - phys = <&dsi1_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - dsi1_out: endpoint { - }; - }; - }; - }; - - - dsi1_phy: dsi-phy@5800200 { - compatible = "qcom,dsi-phy-28nm-8960"; - reg = <0x05800200 0x100>, - <0x05800300 0x200>, - <0x05800500 0x5c>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - clock-names = "iface", - "ref"; - clocks = <&mmcc DSI2_M_AHB_CLK>, - <&pxo_board>; - #clock-cells = <1>; - #phy-cells = <0>; - - status = "disabled"; - }; - - mdp_port0: iommu@7500000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc MDP_AXI_CLK>; - reg = <0x07500000 0x100000>; - interrupts = - , - ; - qcom,ncb = <2>; - }; - - mdp_port1: iommu@7600000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc MDP_AXI_CLK>; - reg = <0x07600000 0x100000>; - interrupts = - , - ; - qcom,ncb = <2>; - }; - - gfx3d: iommu@7c00000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc GFX3D_AXI_CLK>; - reg = <0x07c00000 0x100000>; - interrupts = - , - ; - qcom,ncb = <3>; - }; - - gfx3d1: iommu@7d00000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc GFX3D_AXI_CLK>; - reg = <0x07d00000 0x100000>; - interrupts = - , - ; - qcom,ncb = <3>; - }; - - pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064"; - reg = <0x1b500000 0x1000>, - <0x1b502000 0x80>, - <0x1b600000 0x100>, - <0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ - <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_REF_CLK>; - clock-names = "core", "iface", "phy"; - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; - status = "disabled"; - }; - - hdmi: hdmi-tx@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pinctrl>; - reg = <0x04a00000 0x2f0>; - reg-names = "core_physical"; - interrupts = ; - clocks = <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - clock-names = "core", - "master_iface", - "slave_iface"; - - phys = <&hdmi_phy>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hdmi_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - hdmi_out: endpoint { - }; - }; - }; - }; - - hdmi_phy: phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - reg-names = "hdmi_phy", - "hdmi_pll"; - - clocks = <&mmcc HDMI_S_AHB_CLK>; - clock-names = "slave_iface"; - #phy-cells = <0>; - #clock-cells = <0>; - - status = "disabled"; - }; - - mdp: display-controller@5100000 { - compatible = "qcom,mdp4"; - reg = <0x05100000 0xf0000>; - interrupts = ; - clocks = <&mmcc MDP_CLK>, - <&mmcc MDP_AHB_CLK>, - <&mmcc MDP_AXI_CLK>, - <&mmcc MDP_LUT_CLK>, - <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; - clock-names = "core_clk", - "iface_clk", - "bus_clk", - "lut_clk", - "hdmi_clk", - "tv_clk"; - - iommus = <&mdp_port0 0 - &mdp_port0 2 - &mdp_port1 0 - &mdp_port1 2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp_lvds_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - mdp_dsi1_out: endpoint { - }; - }; - - port@2 { - reg = <2>; - mdp_dsi2_out: endpoint { - }; - }; - - port@3 { - reg = <3>; - mdp_dtv_out: endpoint { - }; - }; - }; - }; - - riva: riva-pil@3200800 { - compatible = "qcom,riva-pil"; - - reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; - reg-names = "ccu", "dxe", "pmu"; - - interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal"; - - memory-region = <&wcnss_mem>; - - vddcx-supply = <&pm8921_s3>; - vddmx-supply = <&pm8921_l24>; - vddpx-supply = <&pm8921_s4>; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3660"; - - clocks = <&cxo_board>; - clock-names = "xo"; - - vddxo-supply = <&pm8921_l4>; - vddrfa-supply = <&pm8921_s2>; - vddpa-supply = <&pm8921_l10>; - vdddig-supply = <&pm8921_lvs2>; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - label = "riva"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&riva>; - - bluetooth { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - etb@1a01000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x1a01000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - tpiu@1a03000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x1a03000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&funnel_out>; - }; - }; - }; - }; - - funnel@1a04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x1a04000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 2 - connected to STM component - * 3 - not-connected - * 6 - not-connected - * 7 - not-connected - */ - port@0 { - reg = <0>; - funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@4 { - reg = <4>; - funnel_in4: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@5 { - reg = <5>; - funnel_in5: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - funnel_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - }; - - etm@1a1c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1c000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel_in0>; - }; - }; - }; - }; - - etm@1a1d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1d000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel_in1>; - }; - }; - }; - }; - - etm@1a1e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1e000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel_in4>; - }; - }; - }; - }; - - etm@1a1f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1f000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel_in5>; - }; - }; - }; - }; - }; -}; -#include "qcom-apq8064-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts deleted file mode 100644 index e0679436000b..000000000000 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" - -/delete-node/ &mpss_region; - -/ { - model = "Qualcomm APQ8074 Dragonboard"; - compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; - - aliases { - serial0 = &blsp1_uart2; - usid0 = &pm8941_0; - usid4 = &pm8841_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-0 = <&msm_keys_default>; - pinctrl-names = "default"; - - button-volup { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - }; - - button-general { - label = "General"; - linux,code = ; - gpios = <&pm8941_gpios 23 GPIO_ACTIVE_LOW>; - }; - }; - - reserved-memory { - mpss_region: mpss@ac00000 { - reg = <0x0ac00000 0x2500000>; - no-map; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_dma { - qcom,controlled-remotely; -}; - -&blsp2_i2c5 { - status = "okay"; - clock-frequency = <200000>; - - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - read-only; - }; -}; - -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - vdda-supply = <&pm8941_l2>; - vdd-supply = <&pm8941_l22>; - vddio-supply = <&pm8941_l12>; - - status = "okay"; - - panel: panel@0 { - compatible = "sharp,ls043t1le01-qhd"; - reg = <0>; - - avdd-supply = <&pm8941_l22>; - backlight = <&pm8941_wled>; - reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - status = "okay"; - - vddio-supply = <&pm8941_l12>; -}; - -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&pm8941_gpios { - msm_keys_default: pm8941-gpio-keys-state { - pins = "gpio5", "gpio23"; - function = "normal"; - input-enable; - drive-push-pull; - bias-pull-up; - qcom,drive-strength = ; - power-source = ; /* 1.8V */ - }; -}; - -&pm8941_lpg { - qcom,power-source = <1>; - status = "okay"; - - led@5 { - reg = <5>; - color = ; - function = LED_FUNCTION_INDICATOR; - }; - - led@6 { - reg = <6>; - color = ; - function = LED_FUNCTION_INDICATOR; - }; - - led@7 { - reg = <7>; - color = ; - function = LED_FUNCTION_INDICATOR; - }; -}; - -&pm8941_wled { - qcom,cs-out; - qcom,switching-freq = <3200>; - qcom,ovp = <32>; - qcom,num-strings = <1>; - - status = "okay"; -}; - -&remoteproc_adsp { - cx-supply = <&pm8841_s2>; - - firmware-name = "qcom/apq8074/adsp.mbn"; - - status = "okay"; -}; - -&remoteproc_mss { - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - firmware-name = "qcom/apq8074/mba.mbn", "qcom/apq8074/modem.mbn"; - - status = "okay"; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vin_5vs-supply = <&pm8941_5v>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8941_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l19: l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - regulator-boot-on; - }; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; -}; - -&tlmm { - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdc2_on: sdc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - - cd-pins { - pins = "gpio62"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs2_phy>; - phy-select = <&tcsr 0xb000 1>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs2_phy { - status = "okay"; - v3p3-supply = <&pm8941_l24>; - v1p8-supply = <&pm8941_l6>; - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x63>; -}; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts deleted file mode 100644 index 116e59a3b76d..000000000000 --- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" - -/ { - model = "Qualcomm APQ8084/IFC6540"; - compatible = "qcom,apq8084-sbc", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; - -&sdhc_1 { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhc_2 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; -}; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts deleted file mode 100644 index c6b6680248a6..000000000000 --- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" - -/ { - model = "Qualcomm APQ 8084-MTP"; - compatible = "qcom,apq8084-mtp", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi deleted file mode 100644 index 207124d68128..000000000000 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ /dev/null @@ -1,852 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm APQ 8084"; - compatible = "qcom,apq8084"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_mem: smem_region@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <0>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <1>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <2>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <3>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - firmware { - scm { - compatible = "qcom,scm-apq8084", "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; - - smem { - compatible = "qcom,smem"; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - memory-region = <&smem_mem>; - - hwlocks = <&tcsr_mutex 3>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - sram@fc190000 { - compatible = "qcom,apq8084-rpm-stats"; - reg = <0xfc190000 0x10000>; - }; - - qfprom: qfprom@fc4bc000 { - compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_base1: base1@d0 { - reg = <0xd0 0x1>; - bits = <0 8>; - }; - - tsens_s0_p1: s0-p1@d1 { - reg = <0xd1 0x1>; - bits = <0 6>; - }; - - tsens_s1_p1: s1-p1@d2 { - reg = <0xd1 0x2>; - bits = <6 6>; - }; - - tsens_s2_p1: s2-p1@d2 { - reg = <0xd2 0x2>; - bits = <4 6>; - }; - - tsens_s3_p1: s3-p1@d3 { - reg = <0xd3 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1: s4-p1@d4 { - reg = <0xd4 0x1>; - bits = <0 6>; - }; - - tsens_s5_p1: s5-p1@d4 { - reg = <0xd4 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1: s6-p1@d5 { - reg = <0xd5 0x2>; - bits = <4 6>; - }; - - tsens_s7_p1: s7-p1@d6 { - reg = <0xd6 0x1>; - bits = <2 6>; - }; - - tsens_s8_p1: s8-p1@d7 { - reg = <0xd7 0x1>; - bits = <0 6>; - }; - - tsens_mode: mode@d7 { - reg = <0xd7 0x1>; - bits = <6 2>; - }; - - tsens_s9_p1: s9-p1@d8 { - reg = <0xd8 0x1>; - bits = <0 6>; - }; - - tsens_s10_p1: s10_p1@d8 { - reg = <0xd8 0x2>; - bits = <6 6>; - }; - - tsens_base2: base2@d9 { - reg = <0xd9 0x2>; - bits = <4 8>; - }; - - tsens_s0_p2: s0-p2@da { - reg = <0xda 0x2>; - bits = <4 6>; - }; - - tsens_s1_p2: s1-p2@db { - reg = <0xdb 0x1>; - bits = <2 6>; - }; - - tsens_s2_p2: s2-p2@dc { - reg = <0xdc 0x1>; - bits = <0 6>; - }; - - tsens_s3_p2: s3-p2@dc { - reg = <0xdc 0x2>; - bits = <6 6>; - }; - - tsens_s4_p2: s4-p2@dd { - reg = <0xdd 0x2>; - bits = <4 6>; - }; - - tsens_s5_p2: s5-p2@de { - reg = <0xde 0x2>; - bits = <2 6>; - }; - - tsens_s6_p2: s6-p2@df { - reg = <0xdf 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2: s7-p2@e0 { - reg = <0xe0 0x1>; - bits = <0 6>; - }; - - tsens_s8_p2: s8-p2@e0 { - reg = <0xe0 0x2>; - bits = <6 6>; - }; - - tsens_s9_p2: s9-p2@e1 { - reg = <0xe1 0x2>; - bits = <4 6>; - }; - - tsens_s10_p2: s10_p2@e2 { - reg = <0xe2 0x2>; - bits = <2 6>; - }; - - tsens_s5_p2_backup: s5-p2_backup@e3 { - reg = <0xe3 0x2>; - bits = <0 6>; - }; - - tsens_mode_backup: mode_backup@e3 { - reg = <0xe3 0x1>; - bits = <6 2>; - }; - - tsens_s6_p2_backup: s6-p2_backup@e4 { - reg = <0xe4 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2_backup: s7-p2_backup@e4 { - reg = <0xe4 0x2>; - bits = <6 6>; - }; - - tsens_s8_p2_backup: s8-p2_backup@e5 { - reg = <0xe5 0x2>; - bits = <4 6>; - }; - - tsens_s9_p2_backup: s9-p2_backup@e6 { - reg = <0xe6 0x2>; - bits = <2 6>; - }; - - tsens_s10_p2_backup: s10_p2_backup@e7 { - reg = <0xe7 0x1>; - bits = <0 6>; - }; - - tsens_base1_backup: base1_backup@440 { - reg = <0x440 0x1>; - bits = <0 8>; - }; - - tsens_s0_p1_backup: s0-p1_backup@441 { - reg = <0x441 0x1>; - bits = <0 6>; - }; - - tsens_s1_p1_backup: s1-p1_backup@442 { - reg = <0x441 0x2>; - bits = <6 6>; - }; - - tsens_s2_p1_backup: s2-p1_backup@442 { - reg = <0x442 0x2>; - bits = <4 6>; - }; - - tsens_s3_p1_backup: s3-p1_backup@443 { - reg = <0x443 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1_backup: s4-p1_backup@444 { - reg = <0x444 0x1>; - bits = <0 6>; - }; - - tsens_s5_p1_backup: s5-p1_backup@444 { - reg = <0x444 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1_backup: s6-p1_backup@445 { - reg = <0x445 0x2>; - bits = <4 6>; - }; - - tsens_s7_p1_backup: s7-p1_backup@446 { - reg = <0x446 0x1>; - bits = <2 6>; - }; - - tsens_use_backup: use_backup@447 { - reg = <0x447 0x1>; - bits = <5 3>; - }; - - tsens_s8_p1_backup: s8-p1_backup@448 { - reg = <0x448 0x1>; - bits = <0 6>; - }; - - tsens_s9_p1_backup: s9-p1_backup@448 { - reg = <0x448 0x2>; - bits = <6 6>; - }; - - tsens_s10_p1_backup: s10_p1_backup@449 { - reg = <0x449 0x2>; - bits = <4 6>; - }; - - tsens_base2_backup: base2_backup@44a { - reg = <0x44a 0x2>; - bits = <2 8>; - }; - - tsens_s0_p2_backup: s0-p2_backup@44b { - reg = <0x44b 0x3>; - bits = <2 6>; - }; - - tsens_s1_p2_backup: s1-p2_backup@44c { - reg = <0x44c 0x1>; - bits = <0 6>; - }; - - tsens_s2_p2_backup: s2-p2_backup@44c { - reg = <0x44c 0x2>; - bits = <6 6>; - }; - - tsens_s3_p2_backup: s3-p2_backup@44d { - reg = <0x44d 0x2>; - bits = <4 6>; - }; - - tsens_s4_p2_backup: s4-p2_backup@44e { - reg = <0x44e 0x1>; - bits = <2 6>; - }; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_mode>, - <&tsens_base1>, <&tsens_base2>, - <&tsens_use_backup>, - <&tsens_mode_backup>, - <&tsens_base1_backup>, <&tsens_base2_backup>, - <&tsens_s0_p1>, <&tsens_s0_p2>, - <&tsens_s1_p1>, <&tsens_s1_p2>, - <&tsens_s2_p1>, <&tsens_s2_p2>, - <&tsens_s3_p1>, <&tsens_s3_p2>, - <&tsens_s4_p1>, <&tsens_s4_p2>, - <&tsens_s5_p1>, <&tsens_s5_p2>, - <&tsens_s6_p1>, <&tsens_s6_p2>, - <&tsens_s7_p1>, <&tsens_s7_p2>, - <&tsens_s8_p1>, <&tsens_s8_p2>, - <&tsens_s9_p1>, <&tsens_s9_p2>, - <&tsens_s10_p1>, <&tsens_s10_p2>, - <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, - <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, - <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, - <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, - <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, - <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, - <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, - <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, - <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, - <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, - <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; - nvmem-cell-names = "mode", - "base1", "base2", - "use_backup", - "mode_backup", - "base1_backup", "base2_backup", - "s0_p1", "s0_p2", - "s1_p1", "s1_p2", - "s2_p1", "s2_p2", - "s3_p1", "s3_p2", - "s4_p1", "s4_p2", - "s5_p1", "s5_p2", - "s6_p1", "s6_p2", - "s7_p1", "s7_p2", - "s8_p1", "s8_p2", - "s9_p1", "s9_p2", - "s10_p1", "s10_p2", - "s0_p1_backup", "s0_p2_backup", - "s1_p1_backup", "s1_p2_backup", - "s2_p1_backup", "s2_p2_backup", - "s3_p1_backup", "s3_p2_backup", - "s4_p1_backup", "s4_p2_backup", - "s5_p1_backup", "s5_p2_backup", - "s6_p1_backup", "s6_p2_backup", - "s7_p1_backup", "s7_p2_backup", - "s8_p1_backup", "s8_p2_backup", - "s9_p1_backup", "s9_p2_backup", - "s10_p1_backup", "s10_p2_backup"; - #qcom,sensors = <11>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: power-manager@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc1: power-manager@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc2: power-manager@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc3: power-manager@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, - <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-apq8084"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - clocks = <&xo_board>, - <&sleep_clk>, - <0>, /* ufs */ - <0>, - <0>, - <0>, - <0>, /* sata */ - <0>, - <0>; /* pcie */ - clock-names = "xo", - "sleep_clk", - "ufs_rx_symbol_0_clk_src", - "ufs_rx_symbol_1_clk_src", - "ufs_tx_symbol_0_clk_src", - "ufs_tx_symbol_1_clk_src", - "sata_asic0_clk", - "sata_rx_clk", - "pcie_pipe"; - }; - - tcsr_mutex: hwlock@fd484000 { - compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex"; - reg = <0xfd484000 0x1000>; - #hwlock-cells = <1>; - }; - - rpm_msg_ram: sram@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,apq8084-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 147>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhc_1: mmc@f9824900 { - compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc", "core"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - status = "disabled"; - }; - - sdhc_2: mmc@f98a4900 { - compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc", "core"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - status = "disabled"; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm-requests { - compatible = "qcom,rpm-apq8084"; - qcom,smd-channels = "rpm_requests"; - - regulators-0 { - compatible = "qcom,rpm-pma8084-regulators"; - - pma8084_s1: s1 {}; - pma8084_s2: s2 {}; - pma8084_s3: s3 {}; - pma8084_s4: s4 {}; - pma8084_s5: s5 {}; - pma8084_s6: s6 {}; - pma8084_s7: s7 {}; - pma8084_s8: s8 {}; - pma8084_s9: s9 {}; - pma8084_s10: s10 {}; - pma8084_s11: s11 {}; - pma8084_s12: s12 {}; - - pma8084_l1: l1 {}; - pma8084_l2: l2 {}; - pma8084_l3: l3 {}; - pma8084_l4: l4 {}; - pma8084_l5: l5 {}; - pma8084_l6: l6 {}; - pma8084_l7: l7 {}; - pma8084_l8: l8 {}; - pma8084_l9: l9 {}; - pma8084_l10: l10 {}; - pma8084_l11: l11 {}; - pma8084_l12: l12 {}; - pma8084_l13: l13 {}; - pma8084_l14: l14 {}; - pma8084_l15: l15 {}; - pma8084_l16: l16 {}; - pma8084_l17: l17 {}; - pma8084_l18: l18 {}; - pma8084_l19: l19 {}; - pma8084_l20: l20 {}; - pma8084_l21: l21 {}; - pma8084_l22: l22 {}; - pma8084_l23: l23 {}; - pma8084_l24: l24 {}; - pma8084_l25: l25 {}; - pma8084_l26: l26 {}; - pma8084_l27: l27 {}; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts deleted file mode 100644 index 1b27edce9d4f..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include -#include "qcom-ipq4018-ap120c-ac.dtsi" - -/ { - model = "ALFA Network AP120C-AC Bit"; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "ap120c-ac:green:power"; - function = LED_FUNCTION_POWER; - color = ; - gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led-wlan { - label = "ap120c-ac:green:wlan"; - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; - }; - - led-support { - label = "ap120c-ac:green:support"; - color = ; - gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; - panic-indicator; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts deleted file mode 100644 index a707057c887d..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include -#include "qcom-ipq4018-ap120c-ac.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - - status: led-status { - label = "ap120c-ac:blue:status"; - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - led-wlan2g { - label = "ap120c-ac:green:wlan2g"; - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tpt"; - }; - - led-wlan5g { - label = "ap120c-ac:red:wlan5g"; - function = LED_FUNCTION_WLAN; - color = ; - gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy1tpt"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi deleted file mode 100644 index d90b4f4c63af..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq4019.dtsi" -#include -#include - -/ { - model = "ALFA Network AP120C-AC"; - compatible = "alfa-network,ap120c-ac", "qcom,ipq4018"; - - aliases { - serial0 = &blsp1_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - keys { - compatible = "gpio-keys"; - - key-reset { - label = "reset"; - gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&tlmm { - i2c0_pins: i2c0_pinmux { - mux_i2c { - function = "blsp_i2c0"; - pins = "gpio58", "gpio59"; - drive-strength = <16>; - bias-disable; - }; - }; - - mdio_pins: mdio_pinmux { - mux_mdio { - pins = "gpio53"; - function = "mdio"; - bias-pull-up; - }; - - mux_mdc { - pins = "gpio52"; - function = "mdc"; - bias-pull-up; - }; - }; - - serial0_pins: serial0_pinmux { - mux_uart { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi0_pins: spi0_pinmux { - mux_spi { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <12>; - bias-disable; - }; - - mux_cs { - function = "gpio"; - pins = "gpio54", "gpio4"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - - usb-power-hog { - line-name = "USB-power"; - gpios = <1 GPIO_ACTIVE_HIGH>; - gpio-hog; - output-high; - }; -}; - -&watchdog { - status = "okay"; -}; - -&prng { - status = "okay"; -}; - -&blsp_dma { - status = "okay"; -}; - -&blsp1_i2c3 { - status = "okay"; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - tpm@29 { - compatible = "atmel,at97sc3204t"; - reg = <0x29>; - }; -}; - -&blsp1_spi1 { - status = "okay"; - - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <24000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x00000000 0x00040000>; - read-only; - }; - - partition@40000 { - label = "MIBIB"; - reg = <0x00040000 0x00020000>; - read-only; - }; - - partition@60000 { - label = "QSEE"; - reg = <0x00060000 0x00060000>; - read-only; - }; - - partition@c0000 { - label = "CDT"; - reg = <0x000c0000 0x00010000>; - read-only; - }; - - partition@d0000 { - label = "DDRPARAMS"; - reg = <0x000d0000 0x00010000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x000e0000 0x00010000>; - }; - - partition@f0000 { - label = "u-boot"; - reg = <0x000f0000 0x00080000>; - read-only; - }; - - partition@170000 { - label = "ART"; - reg = <0x00170000 0x00010000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@180000 { - label = "priv_data1"; - reg = <0x00180000 0x00010000>; - read-only; - }; - - partition@190000 { - label = "priv_data2"; - reg = <0x00190000 0x00010000>; - read-only; - }; - }; - }; - - flash@1 { - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x04000000>; - }; - - partition@4000000 { - label = "ubi2"; - reg = <0x04000000 0x04000000>; - }; - }; - }; -}; - -&blsp1_uart1 { - status = "okay"; - - pinctrl-0 = <&serial0_pins>; - pinctrl-names = "default"; -}; - -&cryptobam { - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -&mdio { - status = "okay"; - - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; -}; - -&wifi0 { - status = "okay"; - nvmem-cell-names = "pre-calibration"; - nvmem-cells = <&precal_art_1000>; -}; - -&wifi1 { - status = "okay"; - nvmem-cell-names = "pre-calibration"; - nvmem-cells = <&precal_art_5000>; - qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; -}; - -&usb3_hs_phy { - status = "okay"; -}; - -&usb3 { - status = "okay"; - - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; - }; -}; - -&usb2_hs_phy { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts deleted file mode 100644 index 365fbac417fd..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -// Copyright (c) 2018, Robert Marko - -#include "qcom-ipq4019.dtsi" -#include -#include - -/ { - model = "8devices Jalapeno"; - compatible = "8dev,jalapeno", "qcom,ipq4018"; -}; - -&tlmm { - mdio_pins: mdio_pinmux { - pinmux_1 { - pins = "gpio53"; - function = "mdio"; - }; - - pinmux_2 { - pins = "gpio52"; - function = "mdc"; - }; - - pinconf { - pins = "gpio52", "gpio53"; - bias-pull-up; - }; - }; - - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi_0_pins: spi_0_pinmux { - pin { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <2>; - bias-disable; - }; - - pin_cs { - function = "gpio"; - pins = "gpio54", "gpio59"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&prng { - status = "okay"; -}; - -&blsp_dma { - status = "okay"; -}; - -&blsp1_spi1 { - status = "okay"; - - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>; - - flash@0 { - status = "okay"; - - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <24000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x00000000 0x00040000>; - read-only; - }; - - partition@40000 { - label = "MIBIB"; - reg = <0x00040000 0x00020000>; - read-only; - }; - - partition@60000 { - label = "QSEE"; - reg = <0x00060000 0x00060000>; - read-only; - }; - - partition@c0000 { - label = "CDT"; - reg = <0x000c0000 0x00010000>; - read-only; - }; - - partition@d0000 { - label = "DDRPARAMS"; - reg = <0x000d0000 0x00010000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x000e0000 0x00010000>; - }; - - partition@f0000 { - label = "u-boot"; - reg = <0x000f0000 0x00080000>; - read-only; - }; - - partition@170000 { - label = "ART"; - reg = <0x00170000 0x00010000>; - read-only; - }; - }; - }; - - spi-nand@1 { - status = "okay"; - - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <24000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x04000000>; - }; - - partition@4000000 { - label = "ubi2"; - reg = <0x04000000 0x04000000>; - }; - }; - }; -}; - -&blsp1_uart1 { - status = "okay"; - - pinctrl-0 = <&serial_pins>; - pinctrl-names = "default"; -}; - -&cryptobam { - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -&mdio { - status = "okay"; - - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; -}; - -&wifi0 { - status = "okay"; - - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; -}; - -&wifi1 { - status = "okay"; - - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; -}; - -&usb3_ss_phy { - status = "okay"; -}; - -&usb3_hs_phy { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -&usb2_hs_phy { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts deleted file mode 100644 index ddaa273f72ca..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "qcom-ipq4019-ap.dk01.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; - compatible = "qcom,ipq4019-ap-dk01.1-c1", "qcom,ipq4019"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi deleted file mode 100644 index 0505270cf508..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include -#include "qcom-ipq4019.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; - - aliases { - serial0 = &blsp1_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - rng@22000 { - status = "okay"; - }; - - pinctrl@1000000 { - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi_0_pins: spi_0_pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio54"; - }; - pinconf { - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio54"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - }; - - blsp_dma: dma-controller@7884000 { - status = "okay"; - }; - - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "okay"; - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; - - mx25l25635e@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "mx25l25635e"; - spi-max-frequency = <24000000>; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - cryptobam: dma-controller@8e04000 { - status = "okay"; - }; - - crypto@8e3a000 { - status = "okay"; - }; - - watchdog@b017000 { - status = "okay"; - }; - - wifi@a000000 { - status = "okay"; - }; - - wifi@a800000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts deleted file mode 100644 index 0993f840d1fc..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk04.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1"; - compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019"; - - soc { - dma-controller@7984000 { - status = "okay"; - }; - }; -}; - -&nand { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts deleted file mode 100644 index 7765247125e4..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk04.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3"; - compatible = "qcom,ipq4019-ap-dk04.1-c3", "qcom,ipq4019"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi deleted file mode 100644 index 468ebc40d2ad..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019.dtsi" -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1"; - - aliases { - serial0 = &blsp1_uart1; - serial1 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256MB */ - }; - - soc { - pinctrl@1000000 { - serial_0_pins: serial0-pinmux { - pins = "gpio16", "gpio17"; - function = "blsp_uart0"; - bias-disable; - }; - - serial_1_pins: serial1-pinmux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "blsp_uart1"; - bias-disable; - }; - - spi_0_pins: spi-0-pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio13", "gpio14", "gpio15"; - bias-disable; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio12"; - bias-disable; - output-high; - }; - }; - - i2c_0_pins: i2c-0-pinmux { - pins = "gpio20", "gpio21"; - function = "blsp_i2c0"; - bias-disable; - }; - - nand_pins: nand-pins { - pins = "gpio53", "gpio55", "gpio56", - "gpio57", "gpio58", "gpio59", - "gpio60", "gpio62", "gpio63", - "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68", "gpio69"; - function = "qpic"; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - serial@78b0000 { - pinctrl-0 = <&serial_1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - dma-controller@7884000 { - status = "okay"; - }; - - spi@78b5000 { /* BLSP1 QUP1 */ - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "okay"; - cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <24000000>; - }; - }; - - pci@40000000 { - status = "okay"; - perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts deleted file mode 100644 index ea2987fcbff8..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include -#include "qcom-ipq4019-ap.dk07.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1"; - compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019"; - - soc { - pci@40000000 { - status = "okay"; - perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - }; - - spi@78b6000 { - status = "okay"; - }; - - pinctrl@1000000 { - serial_1_pins: serial1-pinmux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "blsp_uart1"; - bias-disable; - }; - - spi_0_pins: spi-0-pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio13", "gpio14", "gpio15"; - bias-disable; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio12"; - bias-disable; - output-high; - }; - }; - }; - - serial@78b0000 { - pinctrl-0 = <&serial_1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "okay"; - cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <24000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts deleted file mode 100644 index bd3553dd2070..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk07.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2"; - compatible = "qcom,ipq4019-ap-dk07.1-c2", "qcom,ipq4019"; - - soc { - pinctrl@1000000 { - serial_1_pins: serial1-pinmux { - pins = "gpio8", "gpio9"; - function = "blsp_uart1"; - bias-disable; - }; - }; - - serial@78b0000 { - pinctrl-0 = <&serial_1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi deleted file mode 100644 index 7ef635997efa..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019.dtsi" -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MB */ - }; - - aliases { - serial0 = &blsp1_uart1; - serial1 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinctrl@1000000 { - serial_0_pins: serial0-pinmux { - pins = "gpio16", "gpio17"; - function = "blsp_uart0"; - bias-disable; - }; - - i2c_0_pins: i2c-0-pinmux { - pins = "gpio20", "gpio21"; - function = "blsp_i2c0"; - bias-disable; - }; - - nand_pins: nand-pins { - pins = "gpio53", "gpio55", "gpio56", - "gpio57", "gpio58", "gpio59", - "gpio60", "gpio62", "gpio63", - "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68", "gpio69"; - function = "qpic"; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - dma-controller@7884000 { - status = "okay"; - }; - - i2c@78b7000 { /* BLSP1 QUP2 */ - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - dma-controller@7984000 { - status = "okay"; - }; - }; -}; - -&nand { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi deleted file mode 100644 index dfcfb3339c23..000000000000 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ /dev/null @@ -1,697 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Qualcomm Technologies, Inc. IPQ4019"; - compatible = "qcom,ipq4019"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - - smem_region: smem@87e00000 { - reg = <0x87e00000 0x080000>; - no-map; - }; - - tz@87e80000 { - reg = <0x87e80000 0x180000>; - no-map; - }; - }; - - aliases { - spi0 = &blsp1_spi1; - spi1 = &blsp1_spi2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp1_i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - reg = <0x0>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - reg = <0x1>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - reg = <0x2>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - reg = <0x3>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-48000000 { - opp-hz = /bits/ 64 <48000000>; - clock-latency-ns = <256000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - clock-latency-ns = <256000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <256000>; - }; - opp-716000000 { - opp-hz = /bits/ 64 <716000000>; - clock-latency-ns = <256000>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq4019", "qcom,scm"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <48000000>; - always-on; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, - <0x0b002000 0x1000>; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-ipq4019"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x1800000 0x60000>; - clocks = <&xo>, <&sleep_clk>; - clock-names = "xo", "sleep_clk"; - }; - - prng: rng@22000 { - compatible = "qcom,prng"; - reg = <0x22000 0x140>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - status = "disabled"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x01000000 0x300000>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 100>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - vqmmc: regulator@1948000 { - compatible = "qcom,vqmmc-ipq4019-regulator"; - reg = <0x01948000 0x4>; - regulator-name = "vqmmc"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - status = "disabled"; - }; - - sdhci: mmc@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x11c>, <0x7824000 0x800>; - reg-names = "hc", "core"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - bus-width = <8>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_DCD_XO_CLK>; - clock-names = "iface", "core", "xo"; - status = "disabled"; - }; - - blsp_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x78b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 4>, <&blsp_dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x78b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 6>, <&blsp_dma 7>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 8>, <&blsp_dma 9>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b8000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 10>, <&blsp_dma 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - cryptobam: dma-controller@8e04000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x08e04000 0x20000>; - interrupts = ; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,controlled-remotely; - status = "disabled"; - }; - - crypto: crypto@8e3a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x08e3a000 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - acc0: power-manager@b088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; - }; - - acc1: power-manager@b098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; - }; - - acc2: power-manager@b0a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; - }; - - acc3: power-manager@b0b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; - }; - - saw0: regulator@b089000 { - compatible = "qcom,saw2"; - reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw1: regulator@b099000 { - compatible = "qcom,saw2"; - reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw2: regulator@b0a9000 { - compatible = "qcom,saw2"; - reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw3: regulator@b0b9000 { - compatible = "qcom,saw2"; - reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw_l2: regulator@b012000 { - compatible = "qcom,saw2"; - reg = <0xb012000 0x1000>; - regulator; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = ; - status = "disabled"; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 0>, <&blsp_dma 1>; - dma-names = "tx", "rx"; - }; - - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; - interrupts = ; - status = "disabled"; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 2>, <&blsp_dma 3>; - dma-names = "tx", "rx"; - }; - - watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; - reg = <0xb017000 0x40>; - clocks = <&sleep_clk>; - timeout-sec = <10>; - status = "disabled"; - }; - - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; - }; - - pcie0: pci@40000000 { - compatible = "qcom,pcie-ipq4019"; - reg = <0x40000000 0xf1d - 0x40000f20 0xa8 - 0x80000 0x2000 - 0x40100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, - <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_AHB_CLK>, - <&gcc GCC_PCIE_AXI_M_CLK>, - <&gcc GCC_PCIE_AXI_S_CLK>; - clock-names = "aux", - "master_bus", - "slave_bus"; - - resets = <&gcc PCIE_AXI_M_ARES>, - <&gcc PCIE_AXI_S_ARES>, - <&gcc PCIE_PIPE_ARES>, - <&gcc PCIE_AXI_M_VMIDMT_ARES>, - <&gcc PCIE_AXI_S_XPU_ARES>, - <&gcc PCIE_PARF_XPU_ARES>, - <&gcc PCIE_PHY_ARES>, - <&gcc PCIE_AXI_M_STICKY_ARES>, - <&gcc PCIE_PIPE_STICKY_ARES>, - <&gcc PCIE_PWR_ARES>, - <&gcc PCIE_AHB_ARES>, - <&gcc PCIE_PHY_AHB_ARES>; - reset-names = "axi_m", - "axi_s", - "pipe", - "axi_m_vmid", - "axi_s_xpu", - "parf", - "phy", - "axi_m_sticky", - "pipe_sticky", - "pwr", - "ahb", - "phy_ahb"; - - status = "disabled"; - }; - - qpic_bam: dma-controller@7984000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1a000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - nand: nand-controller@79b0000 { - compatible = "qcom,ipq4019-nand"; - reg = <0x79b0000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - status = "disabled"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - wifi0: wifi@a000000 { - compatible = "qcom,ipq4019-wifi"; - reg = <0xa000000 0x200000>; - resets = <&gcc WIFI0_CPU_INIT_RESET>, - <&gcc WIFI0_RADIO_SRIF_RESET>, - <&gcc WIFI0_RADIO_WARM_RESET>, - <&gcc WIFI0_RADIO_COLD_RESET>, - <&gcc WIFI0_CORE_WARM_RESET>, - <&gcc WIFI0_CORE_COLD_RESET>; - reset-names = "wifi_cpu_init", "wifi_radio_srif", - "wifi_radio_warm", "wifi_radio_cold", - "wifi_core_warm", "wifi_core_cold"; - clocks = <&gcc GCC_WCSS2G_CLK>, - <&gcc GCC_WCSS2G_REF_CLK>, - <&gcc GCC_WCSS2G_RTC_CLK>; - clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", - "wifi_wcss_rtc"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", - "msi12", "msi13", "msi14", "msi15", - "legacy"; - status = "disabled"; - }; - - wifi1: wifi@a800000 { - compatible = "qcom,ipq4019-wifi"; - reg = <0xa800000 0x200000>; - resets = <&gcc WIFI1_CPU_INIT_RESET>, - <&gcc WIFI1_RADIO_SRIF_RESET>, - <&gcc WIFI1_RADIO_WARM_RESET>, - <&gcc WIFI1_RADIO_COLD_RESET>, - <&gcc WIFI1_CORE_WARM_RESET>, - <&gcc WIFI1_CORE_COLD_RESET>; - reset-names = "wifi_cpu_init", "wifi_radio_srif", - "wifi_radio_warm", "wifi_radio_cold", - "wifi_core_warm", "wifi_core_cold"; - clocks = <&gcc GCC_WCSS5G_CLK>, - <&gcc GCC_WCSS5G_REF_CLK>, - <&gcc GCC_WCSS5G_RTC_CLK>; - clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", - "wifi_wcss_rtc"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", - "msi12", "msi13", "msi14", "msi15", - "legacy"; - status = "disabled"; - }; - - mdio: mdio@90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,ipq4019-mdio"; - reg = <0x90000 0x64>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; - }; - - ethphy4: ethernet-phy@4 { - reg = <4>; - }; - }; - - usb3_ss_phy: ssphy@9a000 { - compatible = "qcom,usb-ss-ipq4019-phy"; - #phy-cells = <0>; - reg = <0x9a000 0x800>; - reg-names = "phy_base"; - resets = <&gcc USB3_UNIPHY_PHY_ARES>; - reset-names = "por_rst"; - status = "disabled"; - }; - - usb3_hs_phy: hsphy@a6000 { - compatible = "qcom,usb-hs-ipq4019-phy"; - #phy-cells = <0>; - reg = <0xa6000 0x40>; - reg-names = "phy_base"; - resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; - reset-names = "por_rst", "srif_rst"; - status = "disabled"; - }; - - usb3: usb3@8af8800 { - compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; - reg = <0x8af8800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gcc GCC_USB3_MASTER_CLK>, - <&gcc GCC_USB3_SLEEP_CLK>, - <&gcc GCC_USB3_MOCK_UTMI_CLK>; - clock-names = "core", "sleep", "mock_utmi"; - ranges; - status = "disabled"; - - dwc3@8a00000 { - compatible = "snps,dwc3"; - reg = <0x8a00000 0xf8000>; - interrupts = ; - phys = <&usb3_hs_phy>, <&usb3_ss_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - }; - }; - - usb2_hs_phy: hsphy@a8000 { - compatible = "qcom,usb-hs-ipq4019-phy"; - #phy-cells = <0>; - reg = <0xa8000 0x40>; - reg-names = "phy_base"; - resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; - reset-names = "por_rst", "srif_rst"; - status = "disabled"; - }; - - usb2: usb2@60f8800 { - compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; - reg = <0x60f8800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gcc GCC_USB2_MASTER_CLK>, - <&gcc GCC_USB2_SLEEP_CLK>, - <&gcc GCC_USB2_MOCK_UTMI_CLK>; - clock-names = "master", "sleep", "mock_utmi"; - ranges; - status = "disabled"; - - dwc3@6000000 { - compatible = "snps,dwc3"; - reg = <0x6000000 0xf8000>; - interrupts = ; - phys = <&usb2_hs_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi deleted file mode 100644 index 9d06255104c7..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "qcom-ipq8062.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom-ipq8062.dtsi deleted file mode 100644 index 5d3ebd3e2e51..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8062.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "qcom-ipq8064-v2.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8062"; - compatible = "qcom,ipq8062", "qcom,ipq8064"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts deleted file mode 100644 index a654d3c22c4f..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - soc { - pinmux@800000 { - buttons_pins: buttons_pins { - mux { - pins = "gpio54", "gpio65"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - gsbi@16300000 { - i2c@16380000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts deleted file mode 100644 index 104eb729c2d6..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ /dev/null @@ -1,474 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064.dtsi" -#include -#include - -/ { - model = "MikroTik RB3011UiAS-RM"; - compatible = "mikrotik,rb3011", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi7_serial; - ethernet0 = &gmac0; - ethernet1 = &gmac3; - mdio-gpio0 = &mdio0; - mdio-gpio1 = &mdio1; - }; - - chosen { - bootargs = "loglevel=8 console=ttyMSM0,115200"; - stdout-path = "serial0:115200n8"; - }; - - memory@42000000 { - reg = <0x42000000 0x3e000000>; - device_type = "memory"; - }; - - mdio0: mdio-0 { - status = "okay"; - compatible = "virtual,mdio-gpio"; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - switch0: switch@10 { - compatible = "qca,qca8337"; - - dsa,member = <0 0>; - - pinctrl-0 = <&sw0_reset_pin>; - pinctrl-names = "default"; - - reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - reg = <0x10>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - switch0cpu: port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "sw1"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@2 { - reg = <2>; - label = "sw2"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@3 { - reg = <3>; - label = "sw3"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@4 { - reg = <4>; - label = "sw4"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@5 { - reg = <5>; - label = "sw5"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - }; - }; - }; - - mdio1: mdio-1 { - status = "okay"; - compatible = "virtual,mdio-gpio"; - gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&mdio1_pins>; - pinctrl-names = "default"; - - switch1: switch@14 { - compatible = "qca,qca8337"; - - dsa,member = <1 0>; - - pinctrl-0 = <&sw1_reset_pin>; - pinctrl-names = "default"; - - reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>; - reg = <0x10>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - switch1cpu: port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&gmac3>; - phy-mode = "sgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "sw6"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@2 { - reg = <2>; - label = "sw7"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@3 { - reg = <3>; - label = "sw8"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@4 { - reg = <4>; - label = "sw9"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - - port@5 { - reg = <5>; - label = "sw10"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - function = LED_FUNCTION_LAN; - default-state = "keep"; - }; - }; - }; - }; - }; - }; - - soc { - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - norflash: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "RouterBoot"; - reg = <0x0 0x40000>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - button { - label = "reset"; - linux,code = ; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led-0 { - label = "rb3011:green:user"; - color = ; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&switch0cpu>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac3 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&switch1cpu>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_serial { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "RouterBoard NAND 1 Boot"; - reg = <0x0000000 0x0800000>; - }; - - main@800000 { - label = "RouterBoard NAND 1 Main"; - reg = <0x0800000 0x7800000>; - }; - }; - }; -}; - -&qcom_pinmux { - buttons_pins: buttons_pins { - mux { - pins = "gpio66"; - drive-strength = <16>; - bias-disable; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio33"; - drive-strength = <16>; - bias-disable; - }; - }; - - mdio1_pins: mdio1_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - - sw0_reset_pin: sw0_reset_pin { - mux { - pins = "gpio16"; - drive-strength = <16>; - function = "gpio"; - bias-disable; - input-disable; - }; - }; - - sw1_reset_pin: sw1_reset_pin { - mux { - pins = "gpio17"; - drive-strength = <16>; - function = "gpio"; - bias-disable; - input-disable; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio4"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi deleted file mode 100644 index ac9c44f0c164..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi deleted file mode 100644 index c5abe7151f14..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064.dtsi" -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - gsbi@16300000 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: flash@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "rootfs"; - reg = <0x0 0x1000000>; - }; - - partition@1 { - label = "scratch"; - reg = <0x1000000 0x1000000>; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - ports-implemented = <0x1>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - button-1 { - label = "reset"; - linux,code = ; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - button-2 { - label = "wps"; - linux,code = ; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led-0 { - label = "led_usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbdev"; - default-state = "off"; - }; - - led-1 { - label = "led_usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbdev"; - default-state = "off"; - }; - - led-2 { - label = "status_led_fail"; - function = LED_FUNCTION_STATUS; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "sata_led"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - label = "status_led_pass"; - function = LED_FUNCTION_STATUS; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi deleted file mode 100644 index 0442580b22de..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064-v2.0.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi deleted file mode 100644 index 2f117d576daf..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&sata { - ports-implemented = <0x1>; -}; - -&ss_phy_0 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&ss_phy_1 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi deleted file mode 100644 index 5ef5026fb7bc..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ /dev/null @@ -1,1376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm IPQ8064"; - compatible = "qcom,ipq8064"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - thermal-zones { - sensor0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 0>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 1>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 2>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 3>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 4>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 5>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor6-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 6>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor7-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 7>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor8-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 8>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor9-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 9>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - sensor10-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 10>; - - trips { - cpu-critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu-hot { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem: smem@41000000 { - compatible = "qcom,smem"; - reg = <0x41000000 0x200000>; - no-map; - - hwlocks = <&sfpb_mutex 3>; - }; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq806x", "qcom,scm"; - }; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <7>; - snps,rd_osr_lmt = <7>; - snps,blen = <16 0 0 0 0 0 0>; - }; - - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - rpm: rpm@108000 { - compatible = "qcom,rpm-ipq8064"; - reg = <0x00108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - speedbin_efuse: speedbin@c0 { - reg = <0xc0 0x4>; - }; - tsens_calib: calib@400 { - reg = <0x400 0xb>; - }; - tsens_calib_backup: calib_backup@410 { - reg = <0x410 0xb>; - }; - }; - - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x00800000 0x4000>; - - gpio-controller; - gpio-ranges = <&qcom_pinmux 0 0 69>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - pcie0_pins: pcie0_pinmux { - mux { - pins = "gpio3"; - function = "pcie1_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - pcie1_pins: pcie1_pinmux { - mux { - pins = "gpio48"; - function = "pcie2_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - pcie2_pins: pcie2_pinmux { - mux { - pins = "gpio63"; - function = "pcie3_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - i2c4_pins: i2c4-default { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio54"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - nand_pins: nand_pins { - mux { - pins = "gpio34", "gpio35", "gpio36", - "gpio37", "gpio38", "gpio39", - "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-disable; - }; - - pullups { - pins = "gpio39"; - function = "nand"; - drive-strength = <10>; - bias-pull-up; - }; - - hold { - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "nand"; - drive-strength = <10>; - bias-bus-hold; - }; - }; - - mdio0_pins: mdio0-pins { - mux { - pins = "gpio0", "gpio1"; - function = "mdio"; - drive-strength = <8>; - bias-disable; - }; - }; - - rgmii2_pins: rgmii2-pins { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", - "gpio60", "gpio61", "gpio62"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064", "syscon"; - clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; - clock-names = "pxo", "cxo", "pll4"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - tsens: thermal-sensor { - compatible = "qcom,ipq8064-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = ; - interrupt-names = "uplow"; - - #qcom,sensors = <11>; - #thermal-sensor-cells = <1>; - }; - }; - - sfpb_mutex: hwlock@1200600 { - compatible = "qcom,sfpb-mutex"; - reg = <0x01200600 0x100>; - - #hwlock-cells = <1>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = , - , - , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <25000000>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; - reg = <0x02011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - #clock-cells = <0>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - #clock-cells = <0>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu1_aux"; - #clock-cells = <0>; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - nss_common: syscon@3000000 { - compatible = "syscon"; - reg = <0x03000000 0x0000FFFF>; - }; - - usb3_0: usb@100f8800 { - compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x100f8800 0x8000>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_0: usb@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = ; - phys = <&hs_phy_0>, <&ss_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - hs_phy_0: phy@100f8800 { - compatible = "qcom,ipq806x-usb-phy-hs"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - ss_phy_0: phy@100f8830 { - compatible = "qcom,ipq806x-usb-phy-ss"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb3_1: usb@110f8800 { - compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x110f8800 0x8000>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_1: usb@11000000 { - compatible = "snps,dwc3"; - reg = <0x11000000 0xcd00>; - interrupts = ; - phys = <&hs_phy_1>, <&ss_phy_1>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - hs_phy_1: phy@110f8800 { - compatible = "qcom,ipq806x-usb-phy-hs"; - reg = <0x110f8800 0x30>; - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - ss_phy_1: phy@110f8830 { - compatible = "qcom,ipq806x-usb-phy-ss"; - reg = <0x110f8830 0x30>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - sdcc3bam: dma-controller@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = ; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc1bam: dma-controller@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - sd-uhs-sdr104; - sd-uhs-ddr50; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - }; - - gsbi1: gsbi@12440000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x12440000 0x100>; - cell-index = <1>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi1_serial: serial@12450000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12450000 0x100>, - <0x12400000 0x03>; - interrupts = ; - clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - - status = "disabled"; - }; - - gsbi1_i2c: i2c@12460000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x12460000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi2_serial: serial@12490000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12490000 0x1000>, - <0x12480000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi4_serial: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi6: gsbi@16500000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x16500000 0x100>; - cell-index = <6>; - clocks = <&gcc GSBI6_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi6_i2c: i2c@16580000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16580000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - gsbi6_spi: spi@16580000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x16580000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi7_i2c: i2c@16680000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16680000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - adm_dma: dma-controller@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = ; - #dma-cells = <1>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_PBUS_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "pbus", "c0", "c1", "c2"; - qcom,ee = <0>; - - status = "disabled"; - }; - - gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@1a280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-ipq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - nand: nand-controller@1ac00000 { - compatible = "qcom,ipq806x-nand"; - reg = <0x1ac00000 0x800>; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - clocks = <&gcc EBI2_CLK>, - <&gcc EBI2_AON_CLK>; - clock-names = "core", "aon"; - - dmas = <&adm_dma 3>; - dma-names = "rxtx"; - qcom,cmd-crci = <15>; - qcom,data-crci = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - - pcie0: pci@1b500000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ - 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>, - <&gcc PCIE_AUX_CLK>, - <&gcc PCIE_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>, - <&gcc PCIE_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - status = "disabled"; - perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - }; - - pcie1: pci@1b700000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b700000 0x1000 - 0x1b702000 0x80 - 0x1b800000 0x100 - 0x31f00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ - 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_1_A_CLK>, - <&gcc PCIE_1_H_CLK>, - <&gcc PCIE_1_PHY_CLK>, - <&gcc PCIE_1_AUX_CLK>, - <&gcc PCIE_1_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_1_ACLK_RESET>, - <&gcc PCIE_1_HCLK_RESET>, - <&gcc PCIE_1_POR_RESET>, - <&gcc PCIE_1_PCI_RESET>, - <&gcc PCIE_1_PHY_RESET>, - <&gcc PCIE_1_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - - status = "disabled"; - perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - }; - - pcie2: pci@1b900000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b900000 0x1000 - 0x1b902000 0x80 - 0x1ba00000 0x100 - 0x35f00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <2>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ - 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_2_A_CLK>, - <&gcc PCIE_2_H_CLK>, - <&gcc PCIE_2_PHY_CLK>, - <&gcc PCIE_2_AUX_CLK>, - <&gcc PCIE_2_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_2_ACLK_RESET>, - <&gcc PCIE_2_HCLK_RESET>, - <&gcc PCIE_2_POR_RESET>, - <&gcc PCIE_2_PCI_RESET>, - <&gcc PCIE_2_PHY_RESET>, - <&gcc PCIE_2_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; - - status = "disabled"; - perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; - }; - - qsgmii_csr: syscon@1bb00000 { - compatible = "syscon"; - reg = <0x1bb00000 0x000001FF>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = ; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; - }; - - sata: sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = ; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - gmac0: ethernet@37000000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE1_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE1_RESET>, - <&gcc GMAC_AHB_RESET>; - reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; - - gmac1: ethernet@37200000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE2_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE2_RESET>, - <&gcc GMAC_AHB_RESET>; - reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; - - gmac2: ethernet@37400000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE3_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE3_RESET>, - <&gcc GMAC_AHB_RESET>; - reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; - - gmac3: ethernet@37600000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - snps,axi-config = <&stmmac_axi_setup>; - snps,pbl = <32>; - snps,aal; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE4_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE4_RESET>, - <&gcc GMAC_AHB_RESET>; - reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi deleted file mode 100644 index 803e6ff99ef8..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8065.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi deleted file mode 100644 index ea49f6cc416d..000000000000 --- a/arch/arm/boot/dts/qcom-ipq8065.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064-v2.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; -}; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts deleted file mode 100644 index a8304769b509..000000000000 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Device Tree Source for mangOH Green Board with WP8548 Module - * - * Copyright (C) 2016 BayLibre, SAS. - * Author : Neil Armstrong - */ - -#include - -#include "qcom-mdm9615-wp8548.dtsi" -#include -#include - -/ { - model = "MangOH Green with WP8548 Module"; - compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; - - aliases { - spi0 = &gsbi3_spi; - serial0 = &gsbi4_serial; - serial1 = &gsbi5_serial; - i2c0 = &gsbi5_i2c; - mmc0 = &sdcc1; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; - -&msmgpio { - /* MangOH GPIO Mapping : - * - 2 : GPIOEXP_INT2 - * - 7 : IOT1_GPIO2 - * - 8 : IOT0_GPIO4 - * - 13: IOT0_GPIO3 - * - 21: IOT1_GPIO4 - * - 22: IOT2_GPIO1 - * - 23: IOT2_GPIO2 - * - 24: IOT2_GPIO3 - * - 25: IOT1_GPIO1 - * - 32: IOT1_GPIO3 - * - 33: IOT0_GPIO2 - * - 42: IOT0_GPIO1 and SD Card Detect - */ - - gpioext1_pins: gpioext1-state { - gpioext1-pins { - pins = "gpio2"; - function = "gpio"; - input-enable; - bias-disable; - }; - }; - - sdc_cd_pins: sdc-cd-state { - sdc-cd-pins { - pins = "gpio42"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&gsbi3_spi { - spi@0 { - compatible = "swir,mangoh-iotport-spi"; - spi-max-frequency = <24000000>; - reg = <0>; - }; -}; - -&gsbi5_i2c { - mux@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c_iot0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_iot1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_iot2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - usbhub: hub@8 { - compatible = "smsc,usb3503a"; - reg = <0x8>; - connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; - intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>; - initial-mode = <1>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - gpioext0: pinctrl@3e { - /* GPIO Expander 0 Mapping : - * - 0: ARDUINO_RESET_Level shift - * - 1: BattChrgr_PG_N - * - 2: BattGauge_GPIO - * - 3: LED_ON (out active high) - * - 4: ATmega_reset_GPIO - * - 5: X - * - 6: PCM_ANALOG_SELECT (out active high) - * - 7: X - * - 8: Board_rev_res1 (in) - * - 9: Board_rev_res2 (in) - * - 10: UART_EXP1_ENn (out active low / pull-down) - * - 11: UART_EXP1_IN (out pull-down) - * - 12: UART_EXP2_IN (out pull-down) - * - 13: SDIO_SEL (out pull-down) - * - 14: SPI_EXP1_ENn (out active low / pull-down) - * - 15: SPI_EXP1_IN (out pull-down) - */ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1509q"; - reg = <0x3e>; - interrupt-parent = <&gpioext1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - - semtech,probe-reset; - - gpio-controller; - interrupt-controller; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - gpioext1: pinctrl@3f { - /* GPIO Expander 1 Mapping : - * - 0: GPIOEXP_INT1 - * - 1: Battery detect - * - 2: GPIO_SCF3_RESET - * - 3: LED_CARD_DETECT_IOT0 (in) - * - 4: LED_CARD_DETECT_IOT1 (in) - * - 5: LED_CARD_DETECT_IOT2 (in) - * - 6: UIM2_PWM_SELECT - * - 7: UIM2_M2_S_SELECT - * - 8: TP900 - * - 9: SENSOR_INT1 (in) - * - 10: SENSOR_INT2 (in) - * - 11: CARD_DETECT_IOT0 (in pull-up) - * - 12: CARD_DETECT_IOT2 (in pull-up) - * - 13: CARD_DETECT_IOT1 (in pull-up) - * - 14: GPIOEXP_INT3 (in active low / pull-up) - * - 15: BattChrgr_INT_N - */ - pinctrl-0 = <&gpioext1_pins>; - pinctrl-names = "default"; - - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1509q"; - reg = <0x3f>; - interrupt-parent = <&msmgpio>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - - semtech,probe-reset; - - gpio-controller; - interrupt-controller; - }; - }; - - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - gpioext2: pinctrl@70 { - /* GPIO Expander 2 Mapping : - * - 0: USB_HUB_INTn - * - 1: HUB_CONNECT - * - 2: GPIO_IOT2_RESET (out active low / pull-up) - * - 3: GPIO_IOT1_RESET (out active low / pull-up) - * - 4: GPIO_IOT0_RESET (out active low / pull-up) - * - 5: TP901 - * - 6: TP902 - * - 7: TP903 - * - 8: UART_EXP2_ENn (out active low / pull-down) - * - 9: PCM_EXP1_ENn (out active low) - * - 10: PCM_EXP1_SEL (out) - * - 11: ARD_FTDI - * - 12: TP904 - * - 13: TP905 - * - 14: TP906 - * - 15: RS232_Enable (out active high / pull-up) - */ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1509q"; - reg = <0x70>; - interrupt-parent = <&gpioext1>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - - semtech,probe-reset; - - gpio-controller; - interrupt-controller; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&sdcc1 { - pinctrl-0 = <&sdc_cd_pins>; - pinctrl-names = "default"; - disable-wp; - cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ -}; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi deleted file mode 100644 index 92c8003dac25..000000000000 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Device Tree Source for Sierra Wireless WP8548 Module - * - * Copyright (C) 2016 BayLibre, SAS. - * Author : Neil Armstrong - */ - -#include "qcom-mdm9615.dtsi" - -/ { - model = "Sierra Wireless WP8548 Module"; - compatible = "swir,wp8548", "qcom,mdm9615"; - - memory@48000000 { - device_type = "memory"; - reg = <0x48000000 0x7F00000>; - }; -}; - -&msmgpio { - pinctrl-0 = <&reset_out_pins>; - pinctrl-names = "default"; - - gsbi3_pins: gsbi3-state { - gsbi3-pins { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gsbi3"; - drive-strength = <8>; - bias-disable; - }; - }; - - gsbi4_pins: gsbi4-state { - gsbi4-pins { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gsbi4"; - drive-strength = <8>; - bias-disable; - }; - }; - - gsbi5_i2c_pins: gsbi5-i2c-state { - sda-pins { - pins = "gpio16"; - function = "gsbi5_i2c"; - drive-strength = <8>; - bias-disable; - }; - - scl-pins { - pins = "gpio17"; - function = "gsbi5_i2c"; - drive-strength = <2>; - bias-disable; - }; - }; - - gsbi5_uart_pins: gsbi5-uart-state { - gsbi5-uart-pins { - pins = "gpio18", "gpio19"; - function = "gsbi5_uart"; - drive-strength = <8>; - bias-disable; - }; - }; - - reset_out_pins: reset-out-state { - reset-out-pins { - pins = "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - }; -}; - -&pmicgpio { - usb_vbus_5v_pins: usb-vbus-5v-state { - pins = "gpio4"; - function = "normal"; - output-high; - bias-disable; - qcom,drive-strength = <1>; - power-source = <2>; - }; -}; - -&gsbi3 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi3_spi { - status = "okay"; - pinctrl-0 = <&gsbi3_pins>; - pinctrl-names = "default"; - assigned-clocks = <&gcc GSBI3_QUP_CLK>; - assigned-clock-rates = <24000000>; -}; - -&gsbi4 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "okay"; - pinctrl-0 = <&gsbi4_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi5_i2c { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&gsbi5_i2c_pins>; - pinctrl-names = "default"; -}; - -&gsbi5_serial { - status = "okay"; - pinctrl-0 = <&gsbi5_uart_pins>; - pinctrl-names = "default"; -}; - -&sdcc1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi deleted file mode 100644 index b40c52ddf9b4..000000000000 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ /dev/null @@ -1,507 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Device Tree Source for Qualcomm MDM9615 SoC - * - * Copyright (C) 2016 BayLibre, SAS. - * Author : Neil Armstrong - */ - -/dts-v1/; - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MDM9615"; - compatible = "qcom,mdm9615"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a5"; - reg = <0>; - device_type = "cpu"; - next-level-cache = <&L2>; - }; - }; - - cpu-pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = ; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - }; - - regulators { - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - L2: cache-controller@2040000 { - compatible = "arm,pl310-cache"; - reg = <0x02040000 0x1000>; - arm,data-latency = <2 2 0>; - cache-unified; - cache-level = <2>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>; - cpu-offset = <0x80000>; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,mdm9615-pinctrl"; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 88>; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-mdm9615"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-mdm9615"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; - reg = <0x02011000 0x1000>; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - assigned-clocks = <&gcc PRNG_CLK>; - assigned-clock-rates = <32000000>; - }; - - gsbi2: gsbi@16100000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x16100000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi2_i2c: i2c@16180000 { - compatible = "qcom,i2c-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16180000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi3: gsbi@16200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <3>; - reg = <0x16200000 0x100>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi3_spi: spi@16280000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi4_serial: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi5_i2c: i2c@16480000 { - compatible = "qcom,i2c-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16480000 0x1000>; - interrupts = ; - - /* QUP clock is not initialized, set rate */ - assigned-clocks = <&gcc GSBI5_QUP_CLK>; - assigned-clock-rates = <24000000>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic { - compatible = "qcom,pm8018", "qcom,pm8921"; - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 IRQ_TYPE_EDGE_RISING>, - <51 IRQ_TYPE_EDGE_RISING>; - debounce = <15625>; - pull-up; - }; - - pmicmpp: mpps@50 { - compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmicmpp 0 0 6>; - }; - - rtc@11d { - compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 IRQ_TYPE_EDGE_RISING>; - reg = <0x11d>; - allow-set-time; - }; - - pmicgpio: gpio@150 { - compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; - reg = <0x150>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - gpio-ranges = <&pmicgpio 0 0 6>; - #gpio-cells = <2>; - }; - }; - }; - - sdcc1bam: dma-controller@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc2bam: dma-controller@12142000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12142000 0x8000>; - interrupts = ; - clocks = <&gcc SDC2_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc1: mmc@12180000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12180000 0x2000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - assigned-clocks = <&gcc SDC1_CLK>; - assigned-clock-rates = <400000>; - }; - - sdcc2: mmc@12140000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12140000 0x2000>; - interrupts = ; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; - dma-names = "tx", "rx"; - assigned-clocks = <&gcc SDC2_CLK>; - assigned-clock-rates = <400000>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-mdm9615", "syscon"; - reg = <0x1a400000 0x100>; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-mdm9615"; - reg = <0x108000 0x1000>; - - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8018-regulators"; - - vin_lvs1-supply = <&pm8018_s3>; - - vdd_l7-supply = <&pm8018_s4>; - vdd_l8-supply = <&pm8018_s3>; - vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; - - /* Buck SMPS */ - pm8018_s1: s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s2: s2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s3: s3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s4: s4 { - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s5: s5 { - regulator-always-on; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8018_l2: l2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8018_l3: l3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8018_l4: l4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - pm8018_l5: l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8018_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8018_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8018_l8: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8018_l9: l9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8018_l10: l10 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8018_l11: l11 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8018_l12: l12 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8018_l13: l13 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8018_l14: l14 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8018_lvs1: lvs1 { - bias-pull-down; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts deleted file mode 100644 index 288cacd5d1fa..000000000000 --- a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#include "qcom-msm8226.dtsi" - -/ { - model = "Samsung Galaxy S III Neo"; - compatible = "samsung,s3ve3g", "qcom,msm8226"; - chassis-type = "handset"; - - aliases { - serial0 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi deleted file mode 100644 index 313a726f4704..000000000000 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ /dev/null @@ -1,857 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - chosen { }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8226", "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_region: smem@3000000 { - reg = <0x3000000 0x100000>; - no-map; - }; - - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8226"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8226-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - sdhc_1: mmc@f9824900 { - compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_default_state>; - status = "disabled"; - }; - - sdhc_2: mmc@f98a4900 { - compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_default_state>; - status = "disabled"; - }; - - sdhc_3: mmc@f9864900 { - compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_AHB_CLK>, - <&gcc GCC_SDCC3_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_default_state>; - status = "disabled"; - }; - - blsp1_uart1: serial@f991d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991d000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart3: serial@f991f000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991f000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart4: serial@f9920000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf9920000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_i2c1: i2c@f9923000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9923000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c1_pins>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c2: i2c@f9924000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9924000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c2_pins>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c3: i2c@f9925000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9925000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c3_pins>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c4: i2c@f9926000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9926000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c4_pins>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c5: i2c@f9927000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9927000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c5_pins>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci: cci@fda0c000 { - compatible = "qcom,msm8226-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfda0c000 0x1000>; - interrupts = ; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_CLK>; - clock-names = "camss_top_ahb", - "cci_ahb", - "cci"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cci_default>; - pinctrl-1 = <&cci_sleep>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb: usb@f9a55000 { - compatible = "qcom,ci-hdrc"; - reg = <0xf9a55000 0x200>, - <0xf9a55200 0x200>; - interrupts = ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <75000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - phys = <&usb_hs_phy>; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs_phy: phy { - compatible = "qcom,usb-hs-phy-msm8226", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; - reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44 - 0x1 0x68 0x2 0x24 0x3 0x13>; - }; - }; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8226"; - reg = <0xfc400000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&sleep_clk>; - clock-names = "xo", - "sleep_clk"; - }; - - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8226"; - reg = <0xfd8c0000 0x6000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_MMSS_GPLL0_CLK_SRC>, - <&gcc GPLL0_VOTE>, - <&gcc GPLL1_VOTE>, - <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <0>, - <0>; - clock-names = "xo", - "mmss_gpll0_vote", - "gpll0_vote", - "gpll1_vote", - "gfx3d_clk_src", - "dsi0pll", - "dsi0pllbyte"; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8226-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 117>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - blsp1_i2c1_pins: blsp1-i2c1-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c2_pins: blsp1-i2c2-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c3_pins: blsp1-i2c3-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c4_pins: blsp1-i2c4-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c5_pins: blsp1-i2c5-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - cci_default: cci-default-state { - pins = "gpio29", "gpio30"; - function = "cci_i2c0"; - - drive-strength = <2>; - bias-disable; - }; - - cci_sleep: cci-sleep-state { - pins = "gpio29", "gpio30"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc1_default_state: sdhc1-default-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_default_state: sdhc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc3_default_state: sdhc3-default-state { - clk-pins { - pins = "gpio44"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio43"; - function = "sdc3"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "sdc3"; - drive-strength = <8>; - bias-pull-up; - }; - }; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_mode>, - <&tsens_base1>, <&tsens_base2>, - <&tsens_s0_p1>, <&tsens_s0_p2>, - <&tsens_s1_p1>, <&tsens_s1_p2>, - <&tsens_s2_p1>, <&tsens_s2_p2>, - <&tsens_s3_p1>, <&tsens_s3_p2>, - <&tsens_s4_p1>, <&tsens_s4_p2>, - <&tsens_s5_p1>, <&tsens_s5_p2>, - <&tsens_s6_p1>, <&tsens_s6_p2>; - nvmem-cell-names = "mode", - "base1", "base2", - "s0_p1", "s0_p2", - "s1_p1", "s1_p2", - "s2_p1", "s2_p2", - "s3_p1", "s3_p2", - "s4_p1", "s4_p2", - "s5_p1", "s5_p2", - "s6_p1", "s6_p2"; - #qcom,sensors = <6>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - qfprom: qfprom@fc4bc000 { - compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_base1: base1@1c1 { - reg = <0x1c1 0x2>; - bits = <5 8>; - }; - - tsens_s0_p1: s0-p1@1c2 { - reg = <0x1c2 0x2>; - bits = <5 6>; - }; - - tsens_s1_p1: s1-p1@1c4 { - reg = <0x1c4 0x1>; - bits = <0 6>; - }; - - tsens_s2_p1: s2-p1@1c4 { - reg = <0x1c4 0x2>; - bits = <6 6>; - }; - - tsens_s3_p1: s3-p1@1c5 { - reg = <0x1c5 0x2>; - bits = <4 6>; - }; - - tsens_s4_p1: s4-p1@1c6 { - reg = <0x1c6 0x1>; - bits = <2 6>; - }; - - tsens_s5_p1: s5-p1@1c7 { - reg = <0x1c7 0x1>; - bits = <0 6>; - }; - - tsens_s6_p1: s6-p1@1ca { - reg = <0x1ca 0x2>; - bits = <4 6>; - }; - - tsens_base2: base2@1cc { - reg = <0x1cc 0x1>; - bits = <0 8>; - }; - - tsens_s0_p2: s0-p2@1cd { - reg = <0x1cd 0x1>; - bits = <0 6>; - }; - - tsens_s1_p2: s1-p2@1cd { - reg = <0x1cd 0x2>; - bits = <6 6>; - }; - - tsens_s2_p2: s2-p2@1ce { - reg = <0x1ce 0x2>; - bits = <4 6>; - }; - - tsens_s3_p2: s3-p2@1cf { - reg = <0x1cf 0x1>; - bits = <2 6>; - }; - - tsens_s4_p2: s4-p2@446 { - reg = <0x446 0x2>; - bits = <4 6>; - }; - - tsens_s5_p2: s5-p2@447 { - reg = <0x447 0x1>; - bits = <2 6>; - }; - - tsens_s6_p2: s6-p2@44e { - reg = <0x44e 0x1>; - bits = <1 6>; - }; - - tsens_mode: mode@44f { - reg = <0x44f 0x1>; - bits = <5 3>; - }; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - timer@f9020000 { - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - sram@fc190000 { - compatible = "qcom,msm8226-rpm-stats"; - reg = <0xfc190000 0x10000>; - }; - - rpm_msg_ram: sram@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - tcsr_mutex: hwlock@fd484000 { - compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; - reg = <0xfd484000 0x1000>; - #hwlock-cells = <1>; - }; - - adsp: remoteproc@fe200000 { - compatible = "qcom,msm8226-adsp-pil"; - reg = <0xfe200000 0x100>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - power-domains = <&rpmpd MSM8226_VDDCX>; - power-domain-names = "cx"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - - label = "lpass"; - }; - }; - - sram@fe805000 { - compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; - reg = <0xfe805000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - - mode-bootloader = <0x77665500>; - mode-normal = <0x77665501>; - mode-recovery = <0x77665502>; - }; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts deleted file mode 100644 index be18f1be29a1..000000000000 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm MSM8660 SURF"; - compatible = "qcom,msm8660-surf", "qcom,msm8660"; - - aliases { - serial0 = &gsbi12_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; -}; - -&gsbi12 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi12_serial { - status = "okay"; -}; - -&pm8058 { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_FN_F1) - MATRIX_KEY(0, 1, KEY_UP) - MATRIX_KEY(0, 2, KEY_LEFT) - MATRIX_KEY(0, 3, KEY_VOLUMEUP) - MATRIX_KEY(1, 0, KEY_FN_F2) - MATRIX_KEY(1, 1, KEY_RIGHT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) - MATRIX_KEY(2, 3, KEY_ENTER) - MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) - MATRIX_KEY(4, 1, KEY_UP) - MATRIX_KEY(4, 2, KEY_LEFT) - MATRIX_KEY(4, 3, KEY_HOME) - MATRIX_KEY(4, 4, KEY_FN_F3) - MATRIX_KEY(5, 0, KEY_CAMERA) - MATRIX_KEY(5, 1, KEY_RIGHT) - MATRIX_KEY(5, 2, KEY_DOWN) - MATRIX_KEY(5, 3, KEY_BACK) - MATRIX_KEY(5, 4, KEY_MENU) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; - }; -}; - -/* eMMC */ -&sdcc1 { - vmmc-supply = <&vsdcc_fixed>; - status = "okay"; -}; - -/* External micro SD card */ -&sdcc3 { - vmmc-supply = <&vsdcc_fixed>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi deleted file mode 100644 index f601b40ebcf4..000000000000 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ /dev/null @@ -1,650 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MSM8660"; - compatible = "qcom,msm8660"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - cpu-pmu { - compatible = "qcom,scorpion-mp-pmu"; - interrupts = <1 9 0x304>; - }; - - clocks { - cxo_board: cxo-board-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board: pxo-board-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - - /* - * These channels from the ADC are simply hardware monitors. - * That is why the ADC is referred to as "HKADC" - HouseKeeping - * ADC. - */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&xoadc 0x00 0x01>, /* Battery */ - <&xoadc 0x00 0x02>, /* DC in (charger) */ - <&xoadc 0x00 0x04>, /* VPH the main system voltage */ - <&xoadc 0x00 0x0b>, /* Die temperature */ - <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ - <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ - <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; - - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; - - tlmm: pinctrl@800000 { - compatible = "qcom,msm8660-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - gpio-ranges = <&tlmm 0 0 173>; - #gpio-cells = <2>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - clocks = <&pxo_board>, <&cxo_board>; - clock-names = "pxo", "cxo"; - }; - - gsbi1: gsbi@16000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi1_spi: spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x16080000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi3: gsbi@16200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x16200000 0x100>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - status = "disabled"; - - gsbi3_i2c: i2c@16280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16280000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi6: gsbi@16500000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x16500000 0x100>; - clocks = <&gcc GSBI6_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi6_serial: serial@16540000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16540000 0x1000>, - <0x16500000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi6_i2c: i2c@16580000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16580000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi7: gsbi@16600000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi7_i2c: i2c@16680000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16680000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi8: gsbi@19800000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x19800000 0x100>; - clocks = <&gcc GSBI8_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - status = "disabled"; - - gsbi8_i2c: i2c@19880000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x19880000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi12: gsbi@19c00000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x19c00000 0x100>; - clocks = <&gcc GSBI12_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi12_serial: serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi12_i2c: i2c@19c80000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - ebi2: external-bus@1a100000 { - compatible = "qcom,msm8660-ebi2"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x0 0x1a800000 0x00800000>, - <1 0x0 0x1b000000 0x00800000>, - <2 0x0 0x1b800000 0x00800000>, - <3 0x0 0x1d000000 0x08000000>, - <4 0x0 0x1c800000 0x00800000>, - <5 0x0 0x1c000000 0x00800000>; - reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; - reg-names = "ebi2", "xmem"; - clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; - clock-names = "ebi2x", "ebi2"; - status = "disabled"; - }; - - ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pm8058: pmic { - compatible = "qcom,pm8058"; - interrupt-parent = <&tlmm>; - interrupts = <88 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8058_gpio: gpio@150 { - compatible = "qcom,pm8058-gpio", - "qcom,ssbi-gpio"; - reg = <0x150>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - gpio-ranges = <&pm8058_gpio 0 0 44>; - #gpio-cells = <2>; - - }; - - pm8058_mpps: mpps@50 { - compatible = "qcom,pm8058-mpp", - "qcom,ssbi-mpp"; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8058_mpps 0 0 12>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwrkey@1c { - compatible = "qcom,pm8058-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pm8058>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - pm8058_keypad: keypad@148 { - compatible = "qcom,pm8058-keypad"; - reg = <0x148>; - interrupt-parent = <&pm8058>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - xoadc: xoadc@197 { - compatible = "qcom,pm8058-adc"; - reg = <0x197>; - interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; - #address-cells = <2>; - #size-cells = <0>; - #io-channel-cells = <2>; - - vcoin: adc-channel@0 { - reg = <0x00 0x00>; - }; - vbat: adc-channel@1 { - reg = <0x00 0x01>; - }; - dcin: adc-channel@2 { - reg = <0x00 0x02>; - }; - ichg: adc-channel@3 { - reg = <0x00 0x03>; - }; - vph_pwr: adc-channel@4 { - reg = <0x00 0x04>; - }; - usb_vbus: adc-channel@a { - reg = <0x00 0x0a>; - }; - die_temp: adc-channel@b { - reg = <0x00 0x0b>; - }; - ref_625mv: adc-channel@c { - reg = <0x00 0x0c>; - }; - ref_1250mv: adc-channel@d { - reg = <0x00 0x0d>; - }; - ref_325mv: adc-channel@e { - reg = <0x00 0x0e>; - }; - ref_muxoff: adc-channel@f { - reg = <0x00 0x0f>; - }; - }; - - rtc@1e8 { - compatible = "qcom,pm8058-rtc"; - reg = <0x1e8>; - interrupt-parent = <&pm8058>; - interrupts = <39 1>; - allow-set-time; - }; - - vibrator@4a { - compatible = "qcom,pm8058-vib"; - reg = <0x4a>; - }; - - pm8058_led48: led@48 { - compatible = "qcom,pm8058-keypad-led"; - reg = <0x48>; - status = "disabled"; - }; - - pm8058_led131: led@131 { - compatible = "qcom,pm8058-led"; - reg = <0x131>; - status = "disabled"; - }; - - pm8058_led132: led@132 { - compatible = "qcom,pm8058-led"; - reg = <0x132>; - status = "disabled"; - }; - - pm8058_led133: led@133 { - compatible = "qcom,pm8058-led"; - reg = <0x133>; - status = "disabled"; - }; - - }; - }; - - l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; - reg = <0x02082000 0x1000>; - }; - - rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&pxo_board>; - clock-names = "pxo"; - }; - - regulators-0 { - compatible = "qcom,rpm-pm8901-regulators"; - - pm8901_l0: l0 {}; - pm8901_l1: l1 {}; - pm8901_l2: l2 {}; - pm8901_l3: l3 {}; - pm8901_l4: l4 {}; - pm8901_l5: l5 {}; - pm8901_l6: l6 {}; - - /* S0 and S1 Handled as SAW regulators by SPM */ - pm8901_s2: s2 {}; - pm8901_s3: s3 {}; - pm8901_s4: s4 {}; - - pm8901_lvs0: lvs0 {}; - pm8901_lvs1: lvs1 {}; - pm8901_lvs2: lvs2 {}; - pm8901_lvs3: lvs3 {}; - - pm8901_mvs: mvs {}; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8058-regulators"; - - pm8058_l0: l0 {}; - pm8058_l1: l1 {}; - pm8058_l2: l2 {}; - pm8058_l3: l3 {}; - pm8058_l4: l4 {}; - pm8058_l5: l5 {}; - pm8058_l6: l6 {}; - pm8058_l7: l7 {}; - pm8058_l8: l8 {}; - pm8058_l9: l9 {}; - pm8058_l10: l10 {}; - pm8058_l11: l11 {}; - pm8058_l12: l12 {}; - pm8058_l13: l13 {}; - pm8058_l14: l14 {}; - pm8058_l15: l15 {}; - pm8058_l16: l16 {}; - pm8058_l17: l17 {}; - pm8058_l18: l18 {}; - pm8058_l19: l19 {}; - pm8058_l20: l20 {}; - pm8058_l21: l21 {}; - pm8058_l22: l22 {}; - pm8058_l23: l23 {}; - pm8058_l24: l24 {}; - pm8058_l25: l25 {}; - - pm8058_s0: s0 {}; - pm8058_s1: s1 {}; - pm8058_s2: s2 {}; - pm8058_s3: s3 {}; - pm8058_s4: s4 {}; - - pm8058_lvs0: lvs0 {}; - pm8058_lvs1: lvs1 {}; - - pm8058_ncp: ncp {}; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc2: mmc@12140000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12140000 0x8000>; - interrupts = ; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - }; - - sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x8000>; - interrupts = ; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc5: mmc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = ; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8660", "syscon"; - reg = <0x1a400000 0x100>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts deleted file mode 100644 index c8d34de8a71e..000000000000 --- a/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts +++ /dev/null @@ -1,3 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "arm64/qcom/msm8916-samsung-e5.dts" -#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts deleted file mode 100644 index 85be286c8608..000000000000 --- a/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts +++ /dev/null @@ -1,3 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "arm64/qcom/msm8916-samsung-e7.dts" -#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts deleted file mode 100644 index d3abe0536238..000000000000 --- a/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts +++ /dev/null @@ -1,3 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "arm64/qcom/msm8916-samsung-grandmax.dts" -#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts deleted file mode 100644 index dee2c20af355..000000000000 --- a/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts +++ /dev/null @@ -1,3 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "arm64/qcom/msm8916-samsung-serranove.dts" -#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom-msm8916-smp.dtsi deleted file mode 100644 index 36328dbe4212..000000000000 --- a/arch/arm/boot/dts/qcom-msm8916-smp.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - cpus { - cpu@0 { - enable-method = "qcom,msm8916-smp"; - }; - cpu@1 { - enable-method = "qcom,msm8916-smp"; - }; - cpu@2 { - enable-method = "qcom,msm8916-smp"; - }; - cpu@3 { - enable-method = "qcom,msm8916-smp"; - }; - - idle-states { - /delete-property/ entry-method; - }; - }; - - psci { - status = "disabled"; - }; -}; - -&CPU_SLEEP_0 { - compatible = "qcom,idle-state-spc"; -}; - -&cpu0_acc { - status = "okay"; -}; - -&cpu0_saw { - status = "okay"; -}; - -&cpu1_acc { - status = "okay"; -}; - -&cpu1_saw { - status = "okay"; -}; - -&cpu2_acc { - status = "okay"; -}; - -&cpu2_saw { - status = "okay"; -}; - -&cpu3_acc { - status = "okay"; -}; - -&cpu3_saw { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts deleted file mode 100644 index 6c1bc3818883..000000000000 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ /dev/null @@ -1,348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "qcom-msm8960.dtsi" - -/ { - model = "Qualcomm MSM8960 CDP"; - compatible = "qcom,msm8960-cdp", "qcom,msm8960"; - - aliases { - serial0 = &gsbi5_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ext_l2: gpio-regulator { - compatible = "regulator-fixed"; - regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; - startup-delay-us = <10000>; - enable-active-high; - }; -}; - -&gsbi1 { - qcom,mode = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_default>; - status = "okay"; -}; - -&gsbi1_spi { - status = "okay"; - - ethernet@0 { - compatible = "micrel,ks8851"; - reg = <0>; - interrupt-parent = <&msmgpio>; - interrupts = <90 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <5400000>; - vdd-supply = <&ext_l2>; - vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi5_serial { - status = "okay"; -}; - -&msmgpio { - spi1_default: spi1-default-state { - mosi-pins { - pins = "gpio6"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - }; - - miso-pins { - pins = "gpio7"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio8"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - output-low; - }; - - clk-pins { - pins = "gpio9"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - }; - }; -}; - -&pmicintc { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - }; -}; - -&rpm { - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - vdd_ncp-supply = <&pm8921_l6>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l21_l23_l29-supply = <&pm8921_s8>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - pm8921_s1: s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s2: s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8921_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - pm8921_s4: s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - pm8921_s7: s7 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s8: s8 { - regulator-always-on; - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8921_l1: l1 { - regulator-always-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8921_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l3: l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - pm8921_l4: l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l5: l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l6: l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l7: l7 { - regulator-always-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l8: l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l9: l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l10: l10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l11: l11 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8921_l12: l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l16: l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l18: l18 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - bias-pull-down; - }; - - pm8921_l21: l21 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_l22: l22 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - bias-pull-down; - }; - - pm8921_l23: l23 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l24: l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8921_l25: l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8921_lvs1: lvs1 { - bias-pull-down; - }; - - pm8921_lvs2: lvs2 { - bias-pull-down; - }; - - pm8921_lvs3: lvs3 { - bias-pull-down; - }; - - pm8921_lvs4: lvs4 { - bias-pull-down; - }; - - pm8921_lvs5: lvs5 { - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - pm8921_lvs7: lvs7 { - bias-pull-down; - }; - - pm8921_ncp: ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; -}; - -/* eMMC */ -&sdcc1 { - status = "okay"; -}; - -/* External micro SD card */ -&sdcc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts deleted file mode 100644 index 13e85c287498..000000000000 --- a/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "qcom-msm8960.dtsi" -#include - -/ { - model = "Samsung Galaxy Express SGH-I437"; - compatible = "samsung,expressatt", "qcom,msm8960"; - chassis-type = "handset"; - - aliases { - serial0 = &gsbi5_serial; - mmc0 = &sdcc1; /* SDCC1 eMMC slot */ - mmc1 = &sdcc3; /* SDCC3 SD card slot */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi5_serial { - status = "okay"; -}; - -&sdcc1 { - vmmc-supply = <&pm8921_l5>; - status = "okay"; -}; - -&sdcc3 { - vmmc-supply = <&pm8921_l6>; - vqmmc-supply = <&pm8921_l7>; - status = "okay"; -}; - -&gsbi1 { - qcom,mode = ; - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gsbi1_spi { - status = "okay"; -}; - -&msmgpio { - spi1_default: spi1-default-state { - mosi-pins { - pins = "gpio6"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - }; - - miso-pins { - pins = "gpio7"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio8"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - output-low; - }; - - clk-pins { - pins = "gpio9"; - function = "gsbi1"; - drive-strength = <12>; - bias-disable; - }; - }; -}; - -&rpm { - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - vdd_ncp-supply = <&pm8921_l6>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l21_l23_l29-supply = <&pm8921_s8>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - pm8921_s1: s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s2: s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8921_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - pm8921_s4: s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - pm8921_s7: s7 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s8: s8 { - regulator-always-on; - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8921_l1: l1 { - regulator-always-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8921_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l3: l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - pm8921_l4: l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l5: l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l6: l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l7: l7 { - regulator-always-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l8: l8 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3100000>; - bias-pull-down; - }; - - pm8921_l9: l9 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8921_l10: l10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l11: l11 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - pm8921_l12: l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l16: l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - pm8921_l18: l18 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - bias-pull-down; - }; - - pm8921_l21: l21 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_l22: l22 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - bias-pull-down; - }; - - pm8921_l23: l23 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l24: l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8921_l25: l25 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8921_lvs1: lvs1 { - bias-pull-down; - }; - - pm8921_lvs2: lvs2 { - bias-pull-down; - }; - - pm8921_lvs3: lvs3 { - bias-pull-down; - }; - - pm8921_lvs4: lvs4 { - bias-pull-down; - }; - - pm8921_lvs5: lvs5 { - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - pm8921_lvs7: lvs7 { - bias-pull-down; - }; - - pm8921_ncp: ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; -}; - -&usb_hs1_phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi deleted file mode 100644 index 581b3ab5c4ca..000000000000 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MSM8960"; - compatible = "qcom,msm8960"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - qcom,no-pc-write; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>; - cpu-offset = <0x80000>; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8960-pinctrl"; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - clocks = <&cxo_board>, - <&pxo_board>, - <&lcc PLL4>; - clock-names = "cxo", "pxo", "pll4"; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-msm8960"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names = "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names = "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - #clock-cells = <0>; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - }; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - #clock-cells = <0>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu1_aux"; - #clock-cells = <0>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic { - compatible = "qcom,pm8921"; - interrupt-parent = <&msmgpio>; - interrupts = <104 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 IRQ_TYPE_EDGE_RISING>, - <51 IRQ_TYPE_EDGE_RISING>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 IRQ_TYPE_EDGE_RISING>, - <75 IRQ_TYPE_EDGE_RISING>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 IRQ_TYPE_EDGE_RISING>; - reg = <0x11d>; - allow-set-time; - }; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - }; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gsbi1: gsbi@16000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi1_spi: spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16080000 0x1000>; - interrupts = ; - spi-max-frequency = <24000000>; - cs-gpios = <&msmgpio 8 0>; - - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - usb1: usb@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x200>, - <0x12500200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS1_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs1_phy>; - phy-names = "usb-phy"; - #reset-cells = <1>; - status = "disabled"; - - ulpi { - usb_hs1_phy: phy { - compatible = "qcom,usb-hs-phy-msm8960", - "qcom,usb-hs-phy"; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb1 0>; - reset-names = "por"; - #phy-cells = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts deleted file mode 100644 index e2a7ab7de89b..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ /dev/null @@ -1,698 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "LGE MSM 8974 HAMMERHEAD"; - compatible = "lge,hammerhead", "qcom,msm8974"; - chassis-type = "handset"; - - aliases { - serial0 = &blsp1_uart1; - serial1 = &blsp2_uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - clk_pwm: pwm { - compatible = "clk-pwm"; - clocks = <&mmcc CAMSS_GP1_CLK>; - - pinctrl-0 = <&vibrator_pin>; - pinctrl-names = "default"; - - #pwm-cells = <2>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&clk_pwm 0 100000>; - pwm-names = "enable"; - - vcc-supply = <&pm8941_l19>; - enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_pin>; - }; -}; - -&blsp1_i2c1 { - status = "okay"; - clock-frequency = <100000>; - - charger: bq24192@6b { - compatible = "ti,bq24192"; - reg = <0x6b>; - interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; - - omit-battery-class; - - usb_otg_vbus: usb-otg-vbus { }; - }; - - fuelgauge: max17048@36 { - compatible = "maxim,max17048"; - reg = <0x36>; - - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x4d>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; - - maxim,alert-low-soc-level = <2>; - }; -}; - -&blsp1_i2c2 { - status = "okay"; - clock-frequency = <355000>; - - synaptics@70 { - compatible = "syna,rmi4-i2c"; - reg = <0x70>; - - interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; -}; - -&blsp1_i2c3 { - status = "okay"; - clock-frequency = <100000>; - - avago_apds993@39 { - compatible = "avago,apds9930"; - reg = <0x39>; - interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l17>; - vddio-supply = <&pm8941_lvs1>; - led-max-microamp = <100000>; - amstaos,proximity-diodes = <0>; - }; -}; - -&blsp2_i2c5 { - status = "okay"; - clock-frequency = <355000>; - - led-controller@38 { - compatible = "ti,lm3630a"; - status = "okay"; - reg = <0x38>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0 1>; - label = "lcd-backlight"; - default-brightness = <200>; - }; - }; -}; - -&blsp2_i2c6 { - status = "okay"; - clock-frequency = <100000>; - - mpu6515@68 { - compatible = "invensense,mpu6515"; - reg = <0x68>; - interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>; - vddio-supply = <&pm8941_lvs1>; - - pinctrl-names = "default"; - pinctrl-0 = <&mpu6515_pin>; - - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "1"; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ak8963@f { - compatible = "asahi-kasei,ak8963"; - reg = <0x0f>; - gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; - vid-supply = <&pm8941_lvs1>; - vdd-supply = <&pm8941_l17>; - }; - - bmp280@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - vdda-supply = <&pm8941_lvs1>; - vddd-supply = <&pm8941_l17>; - }; - }; - }; -}; - -&blsp1_uart1 { - status = "okay"; -}; - -&blsp2_uart4 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bt_pin>; - - host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - status = "okay"; - - vdda-supply = <&pm8941_l2>; - vdd-supply = <&pm8941_lvs3>; - vddio-supply = <&pm8941_l12>; - - panel: panel@0 { - reg = <0>; - compatible = "lg,acx467akm-7"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_pin>; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - status = "okay"; - - vddio-supply = <&pm8941_l12>; -}; - -&pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio2", "gpio3"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - fuelgauge_pin: fuelgauge-int-state { - pins = "gpio9"; - function = "normal"; - - bias-disable; - input-enable; - power-source = ; - }; - - wlan_sleep_clk_pin: wl-sleep-clk-state { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active-state { - pins = "gpio17"; - function = "normal"; - - bias-disable; - power-source = ; - }; - - otg { - gpio-hog; - gpios = <35 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "otg-gpio"; - }; -}; - -&pm8941_lpg { - status = "okay"; - - qcom,power-source = <1>; - - multi-led { - color = ; - function = LED_FUNCTION_STATUS; - - #address-cells = <1>; - #size-cells = <0>; - - led@7 { - reg = <7>; - color = ; - }; - - led@6 { - reg = <6>; - color = ; - }; - - led@5 { - reg = <5>; - color = ; - }; - }; -}; - -&remoteproc_adsp { - cx-supply = <&pm8841_s2>; -}; - -&remoteproc_mss { - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l19: l19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - regulator-boot-on; - }; - - pm8941_lvs1: lvs1 {}; - pm8941_lvs3: lvs3 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - - max-frequency = <100000000>; - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8941_s3>; - non-removable; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; -}; - -&tlmm { - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdc2_on: sdc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - mpu6515_pin: mpu6515-state { - pins = "gpio73"; - function = "gpio"; - bias-disable; - input-enable; - }; - - touch_pin: touch-state { - int-pins { - pins = "gpio5"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - - reset-pins { - pins = "gpio8"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - panel_pin: panel-state { - pins = "gpio12"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - }; - - bt_pin: bt-state { - hostwake-pins { - pins = "gpio42"; - function = "gpio"; - }; - - devwake-pins { - pins = "gpio62"; - function = "gpio"; - }; - - shutdown-pins { - pins = "gpio41"; - function = "gpio"; - }; - }; - - vibrator_pin: vibrator-state { - core-pins { - pins = "gpio27"; - function = "gp1_clk"; - drive-strength = <6>; - bias-disable; - }; - - enable-pins { - pins = "gpio60"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - - extcon = <&charger>, <&usb_id>; - vbus-supply = <&usb_otg_vbus>; - - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - qcom,init-seq = /bits/ 8 <0x1 0x64>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts deleted file mode 100644 index 9f2ab5c122d0..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974-sony-xperia-rhine.dtsi" - -/ { - model = "Sony Xperia Z1 Compact"; - compatible = "sony,xperia-amami", "qcom,msm8974"; - chassis-type = "handset"; -}; - -&smbb { - qcom,fast-charge-safe-current = <1300000>; - qcom,fast-charge-current-limit = <1300000>; - qcom,dc-current-limit = <1300000>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts deleted file mode 100644 index 9028f17e5c4a..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974-sony-xperia-rhine.dtsi" - -/ { - model = "Sony Xperia Z1"; - compatible = "sony,xperia-honami", "qcom,msm8974"; - chassis-type = "handset"; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi deleted file mode 100644 index d3bec03b126c..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ /dev/null @@ -1,496 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@3e8e0000 { - compatible = "ramoops"; - reg = <0x3e8e0000 0x200000>; - - console-size = <0x100000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x80000>; - }; - }; -}; - -&blsp1_i2c2 { - status = "okay"; - clock-frequency = <355000>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; -}; - -&blsp1_i2c6 { - status = "okay"; - clock-frequency = <355000>; - - nfc@28 { - compatible = "nxp,pn544-i2c"; - reg = <0x28>; - - interrupt-parent = <&tlmm>; - interrupts = <59 IRQ_TYPE_EDGE_RISING>; - - enable-gpios = <&pm8941_gpios 23 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_dma { - qcom,controlled-remotely; -}; - -&blsp2_i2c5 { - status = "okay"; - clock-frequency = <355000>; - - /* sii8334 MHL HDMI bridge */ -}; - -&pm8941_coincell { - status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; -}; - -&pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; -}; - -&pm8941_lpg { - status = "okay"; - - qcom,power-source = <1>; - - multi-led { - color = ; - function = LED_FUNCTION_STATUS; - - #address-cells = <1>; - #size-cells = <0>; - - led@5 { - reg = <5>; - color = ; - }; - - led@6 { - reg = <6>; - color = ; - }; - - led@7 { - reg = <7>; - color = ; - }; - }; -}; - -&pm8941_wled { - status = "okay"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; -}; - -&remoteproc_adsp { - cx-supply = <&pm8841_s2>; -}; - -&remoteproc_mss { - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s4: s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l19: l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - regulator-boot-on; - }; - - pm8941_lvs3: lvs3 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; -}; - -&smbb { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; -}; - -&tlmm { - ts_int_pin: touch-int-state { - pins = "gpio61"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdc2_on: sdc-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - - cd-pins { - pins = "gpio62"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi deleted file mode 100644 index 21fae1f8966f..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ /dev/null @@ -1,2405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - - CPU0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU2: cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU3: cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8974", "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_region: mpss@8000000 { - reg = <0x08000000 0x5100000>; - no-map; - }; - - mba_region: mba@d100000 { - reg = <0x0d100000 0x100000>; - no-map; - }; - - wcnss_region: wcnss@d200000 { - reg = <0x0d200000 0xa00000>; - no-map; - }; - - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - - venus_region: memory@f500000 { - reg = <0x0f500000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - - tz_region: memory@fc00000 { - reg = <0x0fc00000 0x160000>; - no-map; - }; - - rfsa_mem: memory@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - adsp_smsm: adsp@2 { - reg = <2>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@7 { - reg = <7>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - }; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: power-manager@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; - }; - - acc1: power-manager@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; - }; - - acc2: power-manager@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; - }; - - acc3: power-manager@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; - }; - - sdhc_1: mmc@f9824900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - bus-width = <8>; - non-removable; - - status = "disabled"; - }; - - sdhc_3: mmc@f9864900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_AHB_CLK>, - <&gcc GCC_SDCC3_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - bus-width = <4>; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - sdhc_2: mmc@f98a4900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - bus-width = <4>; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - blsp1_uart1: serial@f991d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991d000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_default>; - status = "disabled"; - }; - - blsp1_i2c1: i2c@f9923000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9923000 0x1000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c1_default>; - pinctrl-1 = <&blsp1_i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c2: i2c@f9924000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9924000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c2_default>; - pinctrl-1 = <&blsp1_i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c3: i2c@f9925000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9925000 0x1000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c3_default>; - pinctrl-1 = <&blsp1_i2c3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c6: i2c@f9928000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9928000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c6_default>; - pinctrl-1 = <&blsp1_i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_dma: dma-controller@f9944000 { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9944000 0x19000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp2_uart1: serial@f995d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995d000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_default>; - pinctrl-1 = <&blsp2_uart1_sleep>; - status = "disabled"; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart4: serial@f9960000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf9960000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart4_default>; - status = "disabled"; - }; - - blsp2_i2c2: i2c@f9964000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9964000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c2_default>; - pinctrl-1 = <&blsp2_i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c5: i2c@f9967000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9967000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c5_default>; - pinctrl-1 = <&blsp2_i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c6: i2c@f9968000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9968000 0x1000>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c6_default>; - pinctrl-1 = <&blsp2_i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb: usb@f9a55000 { - compatible = "qcom,ci-hdrc"; - reg = <0xf9a55000 0x200>, - <0xf9a55200 0x200>; - interrupts = ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <75000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs1_phy: phy-0 { - compatible = "qcom,usb-hs-phy-msm8974", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - usb_hs2_phy: phy-1 { - compatible = "qcom,usb-hs-phy-msm8974", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; - reset-names = "phy", "por"; - status = "disabled"; - }; - }; - }; - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - pronto: remoteproc@fb204000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_region>; - - interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3680"; - - clocks = <&rpmcc RPM_SMD_CXO_A2>; - clock-names = "xo"; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - status = "disabled"; - - qcom,mmio = <&pronto>; - - bluetooth { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", - "tx-rings-empty"; - }; - }; - }; - }; - - sram@fc190000 { - compatible = "qcom,msm8974-rpm-stats"; - reg = <0xfc190000 0x10000>; - }; - - etf@fc307000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc307000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merger_out>; - }; - }; - }; - }; - - tpiu@fc318000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0xfc318000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@fc31a000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31a000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - not-connected - * 1 - connected trought funnel to Multimedia CPU - * 2 - connected to Wireless CPU - * 3 - not-connected - * 4 - not-connected - * 6 - not-connected - * 7 - connected to STM - */ - port@5 { - reg = <5>; - funnel1_in5: endpoint { - remote-endpoint = <&kpss_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merger_in1>; - }; - }; - }; - }; - - funnel@fc31b000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31b000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected trought funnel to Audio, Modem and - * Resource and Power Manager CPU's - * 2...7 - not-connected - */ - port@1 { - reg = <1>; - merger_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - - out-ports { - port { - merger_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - }; - - replicator@fc31c000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0xfc31c000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etr@fc322000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc322000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - etm@fc33c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33c000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&kpss_in0>; - }; - }; - }; - }; - - etm@fc33d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33d000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&kpss_in1>; - }; - }; - }; - }; - - etm@fc33e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33e000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&kpss_in2>; - }; - }; - }; - }; - - etm@fc33f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33f000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&kpss_in3>; - }; - }; - }; - }; - - /* KPSS funnel, only 4 inputs are used */ - funnel@fc345000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc345000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - kpss_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - kpss_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - kpss_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - kpss_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - kpss_out: endpoint { - remote-endpoint = <&funnel1_in5>; - }; - }; - }; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&sleep_clk>; - clock-names = "xo", - "sleep_clk"; - }; - - rpm_msg_ram: sram@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - bimc: interconnect@fc380000 { - reg = <0xfc380000 0x6a000>; - compatible = "qcom,msm8974-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - snoc: interconnect@fc460000 { - reg = <0xfc460000 0x4000>; - compatible = "qcom,msm8974-snoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - pnoc: interconnect@fc468000 { - reg = <0xfc468000 0x4000>; - compatible = "qcom,msm8974-pnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; - }; - - ocmemnoc: interconnect@fc470000 { - reg = <0xfc470000 0x4000>; - compatible = "qcom,msm8974-ocmemnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; - }; - - mmssnoc: interconnect@fc478000 { - reg = <0xfc478000 0x4000>; - compatible = "qcom,msm8974-mmssnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&mmcc MMSS_S0_AXI_CLK>, - <&mmcc MMSS_S0_AXI_CLK>; - }; - - cnoc: interconnect@fc480000 { - reg = <0xfc480000 0x4000>; - compatible = "qcom,msm8974-cnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_mode>, - <&tsens_base1>, <&tsens_base2>, - <&tsens_use_backup>, - <&tsens_mode_backup>, - <&tsens_base1_backup>, <&tsens_base2_backup>, - <&tsens_s0_p1>, <&tsens_s0_p2>, - <&tsens_s1_p1>, <&tsens_s1_p2>, - <&tsens_s2_p1>, <&tsens_s2_p2>, - <&tsens_s3_p1>, <&tsens_s3_p2>, - <&tsens_s4_p1>, <&tsens_s4_p2>, - <&tsens_s5_p1>, <&tsens_s5_p2>, - <&tsens_s6_p1>, <&tsens_s6_p2>, - <&tsens_s7_p1>, <&tsens_s7_p2>, - <&tsens_s8_p1>, <&tsens_s8_p2>, - <&tsens_s9_p1>, <&tsens_s9_p2>, - <&tsens_s10_p1>, <&tsens_s10_p2>, - <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, - <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, - <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, - <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, - <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, - <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, - <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, - <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, - <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, - <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, - <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; - nvmem-cell-names = "mode", - "base1", "base2", - "use_backup", - "mode_backup", - "base1_backup", "base2_backup", - "s0_p1", "s0_p2", - "s1_p1", "s1_p2", - "s2_p1", "s2_p2", - "s3_p1", "s3_p2", - "s4_p1", "s4_p2", - "s5_p1", "s5_p2", - "s6_p1", "s6_p2", - "s7_p1", "s7_p2", - "s8_p1", "s8_p2", - "s9_p1", "s9_p2", - "s10_p1", "s10_p2", - "s0_p1_backup", "s0_p2_backup", - "s1_p1_backup", "s1_p2_backup", - "s2_p1_backup", "s2_p2_backup", - "s3_p1_backup", "s3_p2_backup", - "s4_p1_backup", "s4_p2_backup", - "s5_p1_backup", "s5_p2_backup", - "s6_p1_backup", "s6_p2_backup", - "s7_p1_backup", "s7_p2_backup", - "s8_p1_backup", "s8_p2_backup", - "s9_p1_backup", "s9_p2_backup", - "s10_p1_backup", "s10_p2_backup"; - #qcom,sensors = <11>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - qfprom: qfprom@fc4bc000 { - compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_base1: base1@d0 { - reg = <0xd0 0x1>; - bits = <0 8>; - }; - - tsens_s0_p1: s0-p1@d1 { - reg = <0xd1 0x1>; - bits = <0 6>; - }; - - tsens_s1_p1: s1-p1@d2 { - reg = <0xd1 0x2>; - bits = <6 6>; - }; - - tsens_s2_p1: s2-p1@d2 { - reg = <0xd2 0x2>; - bits = <4 6>; - }; - - tsens_s3_p1: s3-p1@d3 { - reg = <0xd3 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1: s4-p1@d4 { - reg = <0xd4 0x1>; - bits = <0 6>; - }; - - tsens_s5_p1: s5-p1@d4 { - reg = <0xd4 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1: s6-p1@d5 { - reg = <0xd5 0x2>; - bits = <4 6>; - }; - - tsens_s7_p1: s7-p1@d6 { - reg = <0xd6 0x1>; - bits = <2 6>; - }; - - tsens_s8_p1: s8-p1@d7 { - reg = <0xd7 0x1>; - bits = <0 6>; - }; - - tsens_mode: mode@d7 { - reg = <0xd7 0x1>; - bits = <6 2>; - }; - - tsens_s9_p1: s9-p1@d8 { - reg = <0xd8 0x1>; - bits = <0 6>; - }; - - tsens_s10_p1: s10_p1@d8 { - reg = <0xd8 0x2>; - bits = <6 6>; - }; - - tsens_base2: base2@d9 { - reg = <0xd9 0x2>; - bits = <4 8>; - }; - - tsens_s0_p2: s0-p2@da { - reg = <0xda 0x2>; - bits = <4 6>; - }; - - tsens_s1_p2: s1-p2@db { - reg = <0xdb 0x1>; - bits = <2 6>; - }; - - tsens_s2_p2: s2-p2@dc { - reg = <0xdc 0x1>; - bits = <0 6>; - }; - - tsens_s3_p2: s3-p2@dc { - reg = <0xdc 0x2>; - bits = <6 6>; - }; - - tsens_s4_p2: s4-p2@dd { - reg = <0xdd 0x2>; - bits = <4 6>; - }; - - tsens_s5_p2: s5-p2@de { - reg = <0xde 0x2>; - bits = <2 6>; - }; - - tsens_s6_p2: s6-p2@df { - reg = <0xdf 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2: s7-p2@e0 { - reg = <0xe0 0x1>; - bits = <0 6>; - }; - - tsens_s8_p2: s8-p2@e0 { - reg = <0xe0 0x2>; - bits = <6 6>; - }; - - tsens_s9_p2: s9-p2@e1 { - reg = <0xe1 0x2>; - bits = <4 6>; - }; - - tsens_s10_p2: s10_p2@e2 { - reg = <0xe2 0x2>; - bits = <2 6>; - }; - - tsens_s5_p2_backup: s5-p2_backup@e3 { - reg = <0xe3 0x2>; - bits = <0 6>; - }; - - tsens_mode_backup: mode_backup@e3 { - reg = <0xe3 0x1>; - bits = <6 2>; - }; - - tsens_s6_p2_backup: s6-p2_backup@e4 { - reg = <0xe4 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2_backup: s7-p2_backup@e4 { - reg = <0xe4 0x2>; - bits = <6 6>; - }; - - tsens_s8_p2_backup: s8-p2_backup@e5 { - reg = <0xe5 0x2>; - bits = <4 6>; - }; - - tsens_s9_p2_backup: s9-p2_backup@e6 { - reg = <0xe6 0x2>; - bits = <2 6>; - }; - - tsens_s10_p2_backup: s10_p2_backup@e7 { - reg = <0xe7 0x1>; - bits = <0 6>; - }; - - tsens_base1_backup: base1_backup@440 { - reg = <0x440 0x1>; - bits = <0 8>; - }; - - tsens_s0_p1_backup: s0-p1_backup@441 { - reg = <0x441 0x1>; - bits = <0 6>; - }; - - tsens_s1_p1_backup: s1-p1_backup@442 { - reg = <0x441 0x2>; - bits = <6 6>; - }; - - tsens_s2_p1_backup: s2-p1_backup@442 { - reg = <0x442 0x2>; - bits = <4 6>; - }; - - tsens_s3_p1_backup: s3-p1_backup@443 { - reg = <0x443 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1_backup: s4-p1_backup@444 { - reg = <0x444 0x1>; - bits = <0 6>; - }; - - tsens_s5_p1_backup: s5-p1_backup@444 { - reg = <0x444 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1_backup: s6-p1_backup@445 { - reg = <0x445 0x2>; - bits = <4 6>; - }; - - tsens_s7_p1_backup: s7-p1_backup@446 { - reg = <0x446 0x1>; - bits = <2 6>; - }; - - tsens_use_backup: use_backup@447 { - reg = <0x447 0x1>; - bits = <5 3>; - }; - - tsens_s8_p1_backup: s8-p1_backup@448 { - reg = <0x448 0x1>; - bits = <0 6>; - }; - - tsens_s9_p1_backup: s9-p1_backup@448 { - reg = <0x448 0x2>; - bits = <6 6>; - }; - - tsens_s10_p1_backup: s10_p1_backup@449 { - reg = <0x449 0x2>; - bits = <4 6>; - }; - - tsens_base2_backup: base2_backup@44a { - reg = <0x44a 0x2>; - bits = <2 8>; - }; - - tsens_s0_p2_backup: s0-p2_backup@44b { - reg = <0x44b 0x3>; - bits = <2 6>; - }; - - tsens_s1_p2_backup: s1-p2_backup@44c { - reg = <0x44c 0x1>; - bits = <0 6>; - }; - - tsens_s2_p2_backup: s2-p2_backup@44c { - reg = <0x44c 0x2>; - bits = <6 6>; - }; - - tsens_s3_p2_backup: s3-p2_backup@44d { - reg = <0x44d 0x2>; - bits = <4 6>; - }; - - tsens_s4_p2_backup: s4-p2_backup@44e { - reg = <0x44e 0x1>; - bits = <2 6>; - }; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - bam_dmux_dma: dma-controller@fc834000 { - compatible = "qcom,bam-v1.4.0"; - reg = <0xfc834000 0x7000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - - num-channels = <6>; - qcom,num-ees = <1>; - qcom,powered-remotely; - }; - - remoteproc_mss: remoteproc@fc880000 { - compatible = "qcom,msm8974-mss-pil"; - reg = <0xfc880000 0x100>, <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - bam_dmux: bam-dmux { - compatible = "qcom,bam-dmux"; - - interrupt-parent = <&modem_smsm>; - interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pc", "pc-ack"; - - qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; - qcom,smem-state-names = "pc", "pc-ack"; - - dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; - dma-names = "tx", "rx"; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - - label = "modem"; - }; - }; - - tcsr_mutex: hwlock@fd484000 { - compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; - reg = <0xfd484000 0x2000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@fd4a0000 { - compatible = "qcom,tcsr-msm8974", "syscon"; - reg = <0xfd4a0000 0x10000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - sdc1_off: sdc1-off-state { - clk-pins { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd-pins { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data-pins { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_off: sdc2-off-state { - clk-pins { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - cd-pins { - pins = "gpio54"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - }; - - blsp1_uart2_default: blsp1-uart2-default-state { - rx-pins { - pins = "gpio5"; - function = "blsp_uart2"; - drive-strength = <2>; - bias-pull-up; - }; - - tx-pins { - pins = "gpio4"; - function = "blsp_uart2"; - drive-strength = <4>; - bias-disable; - }; - }; - - blsp2_uart1_default: blsp2-uart1-default-state { - tx-rts-pins { - pins = "gpio41", "gpio44"; - function = "blsp_uart7"; - drive-strength = <2>; - bias-disable; - }; - - rx-cts-pins { - pins = "gpio42", "gpio43"; - function = "blsp_uart7"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - blsp2_uart1_sleep: blsp2-uart1-sleep-state { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_uart4_default: blsp2-uart4-default-state { - tx-rts-pins { - pins = "gpio53", "gpio56"; - function = "blsp_uart10"; - drive-strength = <2>; - bias-disable; - }; - - rx-cts-pins { - pins = "gpio54", "gpio55"; - function = "blsp_uart10"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - blsp1_i2c1_default: blsp1-i2c1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-pull-up; - }; - - blsp1_i2c2_default: blsp1-i2c2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-pull-up; - }; - - blsp1_i2c3_default: blsp1-i2c3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-pull-up; - }; - - /* BLSP1_I2C4 info is missing */ - - /* BLSP1_I2C5 info is missing */ - - blsp1_i2c6_default: blsp1-i2c6-default-state { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-pull-up; - }; - /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ - - /* BLSP2_I2C1 info is missing */ - - blsp2_i2c2_default: blsp2-i2c2-default-state { - pins = "gpio47", "gpio48"; - function = "blsp_i2c8"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { - pins = "gpio47", "gpio48"; - function = "blsp_i2c8"; - drive-strength = <2>; - bias-pull-up; - }; - - /* BLSP2_I2C3 info is missing */ - - /* BLSP2_I2C4 info is missing */ - - blsp2_i2c5_default: blsp2-i2c5-default-state { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - drive-strength = <2>; - bias-pull-up; - }; - - blsp2_i2c6_default: blsp2-i2c6-default-state { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <2>; - bias-pull-up; - }; - - cci_default: cci-default-state { - cci_i2c0_default: cci-i2c0-default-pins { - pins = "gpio19", "gpio20"; - function = "cci_i2c0"; - drive-strength = <2>; - bias-disable; - }; - - cci_i2c1_default: cci-i2c1-default-pins { - pins = "gpio21", "gpio22"; - function = "cci_i2c1"; - drive-strength = <2>; - bias-disable; - }; - }; - - cci_sleep: cci-sleep-state { - cci_i2c0_sleep: cci-i2c0-sleep-pins { - pins = "gpio19", "gpio20"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - cci_i2c1_sleep: cci-i2c1-sleep-pins { - pins = "gpio21", "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; - - spi8_default: spi8_default-state { - mosi-pins { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso-pins { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs-pins { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk-pins { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - }; - - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfd8c0000 0x6000>; - clocks = <&xo_board>, - <&gcc GCC_MMSS_GPLL0_CLK_SRC>, - <&gcc GPLL0_VOTE>, - <&gcc GPLL1_VOTE>, - <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, - <0>, - <0>, - <0>; - clock-names = "xo", - "mmss_gpll0_vote", - "gpll0_vote", - "gpll1_vote", - "gfx3d_clk_src", - "dsi0pll", - "dsi0pllbyte", - "dsi1pll", - "dsi1pllbyte", - "hdmipll", - "edp_link_clk", - "edp_vco_div"; - }; - - mdss: display-subsystem@fd900000 { - compatible = "qcom,mdss"; - reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&mmcc MDSS_GDSC>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "vsync"; - - interrupts = ; - - interrupt-controller; - #interrupt-cells = <1>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: display-controller@fd900000 { - compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; - reg = <0xfd900100 0x22000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; - interconnect-names = "mdp0-mem"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - mdp5_intf2_out: endpoint { - remote-endpoint = <&mdss_dsi1_in>; - }; - }; - }; - }; - - mdss_dsi0: dsi@fd922800 { - compatible = "qcom,msm8974-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0xfd922800 0x1f8>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_PCLK0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core", - "core_mmss"; - - phys = <&mdss_dsi0_phy>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi0_out: endpoint { - }; - }; - }; - }; - - mdss_dsi0_phy: phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x280>, - <0xfd922d80 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - - mdss_dsi1: dsi@fd922e00 { - compatible = "qcom,msm8974-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0xfd922e00 0x1f8>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE1_CLK>, - <&mmcc MDSS_PCLK1_CLK>, - <&mmcc MDSS_ESC1_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core", - "core_mmss"; - - phys = <&mdss_dsi1_phy>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi1_in: endpoint { - remote-endpoint = <&mdp5_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi1_out: endpoint { - }; - }; - }; - }; - - mdss_dsi1_phy: phy@fd923000 { - compatible = "qcom,dsi-phy-28nm-hpm"; - reg = <0xfd923000 0xd4>, - <0xfd923100 0x280>, - <0xfd923380 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - }; - - cci: cci@fda0c000 { - compatible = "qcom,msm8974-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfda0c000 0x1000>; - interrupts = ; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_CLK>; - clock-names = "camss_top_ahb", - "cci_ahb", - "cci"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cci_default>; - pinctrl-1 = <&cci_sleep>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gpu: adreno@fdb00000 { - compatible = "qcom,adreno-330.1", "qcom,adreno"; - reg = <0xfdb00000 0x10000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - - clocks = <&mmcc OXILI_GFX3D_CLK>, - <&mmcc OXILICX_AHB_CLK>, - <&mmcc OXILICX_AXI_CLK>; - clock-names = "core", "iface", "mem_iface"; - - sram = <&gmu_sram>; - power-domains = <&mmcc OXILICX_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - - interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, - <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; - interconnect-names = "gfx-mem", "ocmem"; - - // iommus = <&gpu_iommu 0>; - - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-320000000 { - opp-hz = /bits/ 64 <320000000>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - - opp-27000000 { - opp-hz = /bits/ 64 <27000000>; - }; - }; - }; - - sram@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", "mem"; - ranges = <0 0xfec00000 0x180000>; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", "iface"; - - #address-cells = <1>; - #size-cells = <1>; - - gmu_sram: gmu-sram@0 { - reg = <0x0 0x100000>; - }; - }; - - remoteproc_adsp: remoteproc@fe200000 { - compatible = "qcom,msm8974-adsp-pil"; - reg = <0xfe200000 0x100>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - label = "lpass"; - }; - }; - - imem: sram@fe805000 { - compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; - reg = <0xfe805000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - }; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - q6_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modemtx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - modemtx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 3>; - - trips { - video_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - wlan_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 10>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; - - vreg_boost: vreg-boost { - compatible = "regulator-fixed"; - - regulator-name = "vreg-boost"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - regulator-always-on; - regulator-boot-on; - - gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&boost_bypass_n_pin>; - }; - - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts deleted file mode 100644 index f531d2679f6c..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ /dev/null @@ -1,463 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "Fairphone 2"; - compatible = "fairphone,fp2", "qcom,msm8974pro", "qcom,msm8974"; - chassis-type = "handset"; - - aliases { - mmc0 = &sdhc_1; - mmc1 = &sdhc_2; - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - key-volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - }; - - vibrator { - compatible = "gpio-vibrator"; - enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; - vcc-supply = <&pm8941_l18>; - }; -}; - -&blsp1_i2c2 { - status = "okay"; - - touchscreen@41 { - compatible = "ilitek,ili2120"; - reg = <0x41>; - interrupt-parent = <&tlmm>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <1080>; - touchscreen-size-y = <1920>; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&imem { - reboot-mode { - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; -}; - -&pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio1", "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; -}; - -&pm8941_lpg { - status = "okay"; - - qcom,power-source = <1>; - - multi-led { - color = ; - function = LED_FUNCTION_STATUS; - - #address-cells = <1>; - #size-cells = <0>; - - led@7 { - reg = <7>; - color = ; - }; - - led@6 { - reg = <6>; - color = ; - }; - - led@5 { - reg = <5>; - color = ; - }; - }; -}; - -&pronto { - status = "okay"; - - vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; - vddpx-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - iris { - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - qcom,remote-pid = <4>; - label = "pronto"; - - wcnss { - status = "okay"; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; - cx-supply = <&pm8841_s2>; -}; - -&remoteproc_mss { - status = "okay"; - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l11: l11 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1350000>; - }; - - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l19: l19 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3350000>; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - regulator-boot-on; - }; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; -}; - -&smbb { - usb-charge-current-limit = <1500000>; - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,fast-charge-safe-voltage = <4380000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,auto-recharge-threshold-voltage = <4240000>; - qcom,minimum-input-voltage = <4450000>; -}; - -&tlmm { - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdc2_on: sdc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - wcnss_pin_a: wcnss-pin-active-state { - wlan-pins { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "wlan"; - - drive-strength = <6>; - bias-pull-down; - }; - - bt-pins { - pins = "gpio35", "gpio43", "gpio44"; - function = "bt"; - - drive-strength = <2>; - bias-pull-down; - }; - - fm-pins { - pins = "gpio41", "gpio42"; - function = "fm"; - - drive-strength = <2>; - bias-pull-down; - }; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts deleted file mode 100644 index 8d2a054d8fee..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts +++ /dev/null @@ -1,513 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include - -/ { - model = "OnePlus One"; - compatible = "oneplus,bacon", "qcom,msm8974pro", "qcom,msm8974"; - chassis-type = "handset"; - qcom,msm-id = <194 0x10000>; - qcom,board-id = <8 0>; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&gpio_keys_default>, <&gpio_hall_sensor_default>; - pinctrl-names = "default"; - - key-volume-down { - label = "Volume Down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - event-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&tlmm 68 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - linux,can-disable; - debounce-interval = <150>; - }; - }; -}; - -&blsp1_i2c1 { - status = "okay"; - - fuel-gauge@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - power-supplies = <&bq24196_charger>; - }; -}; - -&blsp1_i2c2 { - status = "okay"; - - rmi4-i2c-dev@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - syna,startup-delay-ms = <100>; - - interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_default_state>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - /* - * Touchscreen size is 2040x1080, y-values between - * 1920-2040 are used for touchkey (menu, home & back). - * For now clip it off so we don't get touch events - * outside of the display area. - */ - syna,clip-y-high = <1920>; - }; - }; - - led-controller@36 { - compatible = "ti,lm3630a"; - reg = <0x36>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0 1>; - label = "lcd-backlight"; - default-brightness = <80>; - }; - }; - - led-controller@68 { - compatible = "si-en,sn3193"; - reg = <0x68>; - - shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - led@1 { - reg = <1>; - label = "red:status"; - led-max-microamp = <17500>; - }; - - led@2 { - reg = <2>; - label = "green:status"; - led-max-microamp = <17500>; - }; - - led@3 { - reg = <3>; - label = "blue:status"; - led-max-microamp = <17500>; - }; - }; -}; - -&blsp1_i2c6 { - status = "okay"; - - bq24196_charger: charger@6b { - compatible = "ti,bq24196"; - reg = <0x6b>; - interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; - omit-battery-class; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&gcc { - compatible = "qcom,gcc-msm8974pro-ac"; -}; - -&pm8941_coincell { - qcom,rset-ohms = <800>; - qcom,vset-millivolts = <3200>; - - status = "okay"; -}; - -&pm8941_gpios { - gpio_keys_default: gpio-keys-active-state { - pins = "gpio2", "gpio5"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; -}; - -&pm8941_vib { - status = "okay"; -}; - -&pronto { - vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; - vddpx-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - status = "okay"; - - iris { - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - qcom,remote-pid = <4>; - label = "pronto"; - - wcnss { - status = "okay"; - }; - }; -}; - -&remoteproc_adsp { - cx-supply = <&pm8841_s2>; - - status = "okay"; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <154000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l11: l11 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1350000>; - }; - - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l19: l19 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3350000>; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-allow-set-load; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - - pm8941_lvs3: lvs3 {}; - }; -}; - -&sdhc_1 { - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - - status = "okay"; -}; - -&tlmm { - gpio_hall_sensor_default: gpio-hall-sensor-default-state { - pins = "gpio68"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; - - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <4>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <4>; - bias-pull-up; - }; - }; - - touch_default_state: touch-default-state { - int-pins { - pins = "gpio61"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - reset-pins { - pins = "gpio60"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - wcnss_pin_a: wcnss-pin-active-state { - wlan-pins { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "wlan"; - drive-strength = <6>; - bias-pull-down; - }; - - bt-pins { - pins = "gpio35", "gpio43", "gpio44"; - function = "bt"; - drive-strength = <2>; - bias-pull-down; - }; - }; -}; - -&usb { - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - status = "okay"; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts deleted file mode 100644 index cfbcd521f74d..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ /dev/null @@ -1,814 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "qcom-pma8084.dtsi" -#include -#include -#include - -/ { - model = "Samsung Galaxy S5"; - compatible = "samsung,klte", "qcom,msm8974pro", "qcom,msm8974"; - chassis-type = "handset"; - - aliases { - serial0 = &blsp1_uart1; - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_3; /* SDC2 SD card slot */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-volume-down { - label = "volume_down"; - gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - - key-home { - label = "home_key"; - gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - }; - - i2c-gpio-touchkey { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_touchkey_pins>; - - touchkey@20 { - compatible = "cypress,tm2-touchkey"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_pin>; - - vcc-supply = <&max77826_ldo15>; - vdd-supply = <&pma8084_l19>; - - linux,keycodes = ; - }; - }; - - i2c-gpio-led { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_led_gpioex_pins>; - - i2c-gpio,delay-us = <2>; - - gpio_expander: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - - gpio-controller; - #gpio-cells = <2>; - - vcc-supply = <&pma8084_s4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gpioex_pin>; - - reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - }; - - led-controller@30 { - compatible = "panasonic,an30259a"; - reg = <0x30>; - - #address-cells = <1>; - #size-cells = <0>; - - led@1 { - reg = <1>; - function = LED_FUNCTION_STATUS; - color = ; - }; - - led@2 { - reg = <2>; - function = LED_FUNCTION_STATUS; - color = ; - }; - - led@3 { - reg = <3>; - function = LED_FUNCTION_STATUS; - color = ; - }; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vreg_panel: panel-regulator { - compatible = "regulator-fixed"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_en_pin>; - - regulator-name = "panel-vddr-reg"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /delete-node/ vreg-boost; -}; - -&blsp1_i2c2 { - status = "okay"; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - vdd-supply = <&max77826_ldo13>; - vio-supply = <&pma8084_lvs2>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - syna,startup-delay-ms = <100>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; -}; - -&blsp1_i2c6 { - status = "okay"; - - pmic@60 { - reg = <0x60>; - compatible = "maxim,max77826"; - - regulators { - max77826_ldo1: LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo2: LDO2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - max77826_ldo3: LDO3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo4: LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo5: LDO5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo6: LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo7: LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo8: LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo9: LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo10: LDO10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo11: LDO11 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo12: LDO12 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo13: LDO13 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo14: LDO14 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo15: LDO15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_buck: BUCK { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - max77826_buckboost: BUCKBOOST { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - }; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_i2c6 { - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max17048"; - reg = <0x36>; - - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x56>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; - }; -}; - -&blsp2_uart2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_pins_active>; - pinctrl-1 = <&blsp2_uart2_pins_sleep>; - - bluetooth { - compatible = "brcm,bcm43540-bt"; - max-speed = <3000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_pins>; - device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&tlmm>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - }; -}; - -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - status = "okay"; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - panel: panel@0 { - reg = <0>; - compatible = "samsung,s6e3fa2"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_te_pin &panel_rst_pin>; - - iovdd-supply = <&pma8084_lvs4>; - vddr-supply = <&vreg_panel>; - - reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; - te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - status = "okay"; - - vddio-supply = <&pma8084_l12>; -}; - -&pma8084_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio2", "gpio3", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - touchkey_pin: touchkey-int-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; - }; - - touch_pin: touchscreen-int-state { - pins = "gpio8"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; - }; - - panel_en_pin: panel-en-state { - pins = "gpio14"; - function = "normal"; - bias-pull-up; - power-source = ; - qcom,drive-strength = ; - }; - - wlan_sleep_clk_pin: wlan-sleep-clk-state { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = ; - qcom,drive-strength = ; - }; - - panel_rst_pin: panel-rst-state { - pins = "gpio17"; - function = "normal"; - bias-disable; - power-source = ; - qcom,drive-strength = ; - }; - - fuelgauge_pin: fuelgauge-int-state { - pins = "gpio21"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; - }; -}; - -&remoteproc_adsp { - status = "okay"; - cx-supply = <&pma8084_s2>; -}; - -&remoteproc_mss { - status = "okay"; - cx-supply = <&pma8084_s2>; - mss-supply = <&pma8084_s6>; - mx-supply = <&pma8084_s1>; - pll-supply = <&pma8084_l12>; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pma8084-regulators"; - - pma8084_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - pma8084_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pma8084_s6: s6 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l3: l3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pma8084_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pma8084_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l19: l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - pma8084_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - pma8084_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pma8084_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pma8084_l25: l25 { - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - }; - - pma8084_l26: l26 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l27: l27 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pma8084_l20>; - vqmmc-supply = <&pma8084_s4>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - max-frequency = <100000000>; - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pma8084_s4>; - non-removable; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - - interrupt-parent = <&tlmm>; - interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; - }; -}; - -&sdhc_3 { - status = "okay"; - max-frequency = <100000000>; - vmmc-supply = <&pma8084_l21>; - vqmmc-supply = <&pma8084_l13>; - - /* - * cd-gpio is intentionally disabled. If enabled, an SD card - * present during boot is not initialized correctly. Without - * cd-gpios the driver resorts to polling, so hotplug works. - */ - pinctrl-names = "default"; - pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; - /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ -}; - -&tlmm { - /* This seems suspicious, but somebody with this device should look into it. */ - blsp2_uart2_pins_active: blsp2-uart2-pins-active-state { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "blsp_uart8"; - drive-strength = <8>; - bias-disable; - }; - - blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep-state { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - bt_pins: bt-pins-state { - hostwake-pins { - pins = "gpio75"; - function = "gpio"; - drive-strength = <16>; - input-enable; - }; - - devwake-pins { - pins = "gpio91"; - function = "gpio"; - drive-strength = <2>; - }; - }; - - sdc1_on: sdhc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <4>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <4>; - bias-pull-up; - }; - }; - - sdc3_on: sdc3-on-state { - pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - - sdhc3_cd_pin: sdc3-cd-on-state { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdc2_on: sdhc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - i2c_touchkey_pins: i2c-touchkey-state { - pins = "gpio95", "gpio96"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - i2c_led_gpioex_pins: i2c-led-gpioex-state { - pins = "gpio120", "gpio121"; - function = "gpio"; - input-enable; - bias-pull-down; - }; - - gpioex_pin: gpioex-state { - pins = "gpio145"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - - wifi_pin: wifi-state { - pins = "gpio92"; - function = "gpio"; - input-enable; - bias-pull-down; - }; - - panel_te_pin: panel-state { - pins = "gpio12"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pma8084_l6>; - v3p3-supply = <&pma8084_l24>; - - qcom,init-seq = /bits/ 8 <0x1 0x64>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts deleted file mode 100644 index 2396253f953a..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ /dev/null @@ -1,675 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "Sony Xperia Z2 Tablet"; - compatible = "sony,xperia-castor", "qcom,msm8974pro", "qcom,msm8974"; - chassis-type = "tablet"; - - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp2_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - vreg_bl_vddio: lcd-backlight-vddio { - compatible = "regulator-fixed"; - regulator-name = "vreg_bl_vddio"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - gpio = <&tlmm 69 0>; - enable-active-high; - - vin-supply = <&pm8941_s3>; - startup-delay-us = <70000>; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_backlight_en_pin_a>; - }; - - vreg_vsp: lcd-dcdc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_vsp"; - regulator-min-microvolt = <5600000>; - regulator-max-microvolt = <5600000>; - - gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_dcdc_en_pin_a>; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_pin>; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_i2c2 { - status = "okay"; - clock-frequency = <355000>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupt-parent = <&tlmm>; - interrupts = <86 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <100>; - - rmi-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - - rmi-f11@11 { - reg = <0x11>; - syna,f11-flip-x = <1>; - syna,sensor-type = <1>; - }; - }; -}; - -&blsp2_i2c5 { - status = "okay"; - clock-frequency = <355000>; - - lp8566_wled: backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - power-supply = <&vreg_bl_vddio>; - - bl-name = "backlight"; - dev-ctrl = /bits/ 8 <0x05>; - init-brt = /bits/ 8 <0x3f>; - - rom-a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0xff>; - }; - rom-a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x3f>; - }; - rom-a2h { - rom-addr = /bits/ 8 <0xa2>; - rom-val = /bits/ 8 <0x20>; - }; - rom-a3h { - rom-addr = /bits/ 8 <0xa3>; - rom-val = /bits/ 8 <0x5e>; - }; - rom-a4h { - rom-addr = /bits/ 8 <0xa4>; - rom-val = /bits/ 8 <0x02>; - }; - rom-a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x04>; - }; - rom-a6h { - rom-addr = /bits/ 8 <0xa6>; - rom-val = /bits/ 8 <0x80>; - }; - rom-a7h { - rom-addr = /bits/ 8 <0xa7>; - rom-val = /bits/ 8 <0xf7>; - }; - rom-a9h { - rom-addr = /bits/ 8 <0xa9>; - rom-val = /bits/ 8 <0x80>; - }; - rom-aah { - rom-addr = /bits/ 8 <0xaa>; - rom-val = /bits/ 8 <0x0f>; - }; - rom-aeh { - rom-addr = /bits/ 8 <0xae>; - rom-val = /bits/ 8 <0x0f>; - }; - }; -}; - -&blsp2_uart1 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>; - - host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; - }; -}; - -&pm8941_coincell { - status = "okay"; - - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; -}; - -&pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - bt_reg_on_pin: bt-reg-on-state { - pins = "gpio16"; - function = "normal"; - - output-low; - power-source = ; - }; - - wlan_sleep_clk_pin: wl-sleep-clk-state { - pins = "gpio17"; - function = "func2"; - - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active-state { - pins = "gpio18"; - function = "normal"; - - bias-disable; - power-source = ; - }; - - lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { - pins = "gpio20"; - function = "normal"; - - bias-disable; - power-source = ; - input-disable; - output-low; - }; - -}; - -&pm8941_lpg { - status = "okay"; - - qcom,power-source = <1>; - - multi-led { - color = ; - function = LED_FUNCTION_STATUS; - - #address-cells = <1>; - #size-cells = <0>; - - led@5 { - reg = <5>; - color = ; - }; - - led@6 { - reg = <6>; - color = ; - }; - - led@7 { - reg = <7>; - color = ; - }; - }; -}; - -&remoteproc_adsp { - cx-supply = <&pm8841_s2>; -}; - -&remoteproc_mss { - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <154000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s4: s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8941_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l19: l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <500000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - regulator-boot-on; - }; - - pm8941_lvs3: lvs3 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; -}; - -&sdhc_3 { - status = "okay"; - - max-frequency = <100000000>; - vmmc-supply = <&vreg_wlan>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc3_on>; - - #address-cells = <1>; - #size-cells = <0>; - - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; -}; - -&smbb { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - usb-charge-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; -}; - -&tlmm { - lcd_backlight_en_pin_a: lcd-backlight-vddio-state { - pins = "gpio69"; - function = "gpio"; - drive-strength = <10>; - output-low; - bias-disable; - }; - - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdc2_on: sdc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - - cd-pins { - pins = "gpio62"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; - - sdc3_on: sdc3-on-state { - clk-pins { - pins = "gpio40"; - function = "sdc3"; - drive-strength = <10>; - bias-disable; - }; - - cmd-pins { - pins = "gpio39"; - function = "sdc3"; - drive-strength = <10>; - bias-pull-up; - }; - - data-pins { - pins = "gpio35", "gpio36", "gpio37", "gpio38"; - function = "sdc3"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - ts_int_pin: ts-int-pin-state { - pins = "gpio86"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - input-enable; - }; - - bt_host_wake_pin: bt-host-wake-state { - pins = "gpio95"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - bt_dev_wake_pin: bt-dev-wake-state { - pins = "gpio96"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi deleted file mode 100644 index 58df6e75ab6d..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" - -&gcc { - compatible = "qcom,gcc-msm8974pro"; -}; - -&gpu { - compatible = "qcom,adreno-330.2", "qcom,adreno"; -}; - -&sdhc_1 { - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>, - <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, - <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "iface", "core", "xo", "cal", "sleep"; -}; diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi deleted file mode 100644 index 3b8ad28cecb0..000000000000 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -#include -#include -#include -#include - -/ { - thermal-zones { - pm8226-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pm8226_temp>; - - trips { - trip0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "hot"; - }; - - crit { - temperature = <145000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pm8226_0: pm8226@0 { - compatible = "qcom,pm8226", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - pm8226_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - status = "disabled"; - }; - }; - - smbb: charger@1000 { - compatible = "qcom,pm8226-charger"; - reg = <0x1000>; - interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "chg-done", - "chg-fast", - "chg-trkl", - "bat-temp-ok", - "bat-present", - "chg-gone", - "usb-valid", - "dc-valid"; - - chg_otg: otg-vbus { }; - }; - - pm8226_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8226_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8226_vadc: adc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@7 { - reg = ; - qcom,pre-scaling = <1 3>; - label = "vph_pwr"; - }; - adc-chan@8 { - reg = ; - label = "die_temp"; - }; - adc-chan@9 { - reg = ; - label = "ref_625mv"; - }; - adc-chan@a { - reg = ; - label = "ref_1250mv"; - }; - adc-chan@e { - reg = ; - }; - adc-chan@f { - reg = ; - }; - }; - - pm8226_iadc: adc@3600 { - compatible = "qcom,pm8226-iadc", "qcom,spmi-iadc"; - reg = <0x3600>; - interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8226_mpps: mpps@a000 { - compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8226_mpps 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm8226_gpios: gpio@c000 { - compatible = "qcom,pm8226-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8226_gpios 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8226_1: pm8226@1 { - compatible = "qcom,pm8226", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8226_spmi_regulators: regulators { - compatible = "qcom,pm8226-regulators"; - }; - - pm8226_vib: vibrator@c000 { - compatible = "qcom,pm8916-vib"; - reg = <0xc000>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi deleted file mode 100644 index 3bf2ce5c86a6..000000000000 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - - -/ { - thermal-zones { - pm8841-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pm8841_temp>; - - trips { - trip0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "hot"; - }; - - crit { - temperature = <140000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - - pm8841_0: pm8841@4 { - compatible = "qcom,pm8841", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8841_mpps: mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8841_mpps 0 0 4>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm8841_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; - #thermal-sensor-cells = <0>; - }; - }; - - pm8841_1: pm8841@5 { - compatible = "qcom,pm8841", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi deleted file mode 100644 index b3e246bacd78..000000000000 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - - -/ { - thermal-zones { - pm8941-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pm8941_temp>; - - trips { - trip0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "hot"; - }; - - crit { - temperature = <145000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - - pm8941_0: pm8941@0 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, - <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - }; - - usb_id: usb-detect@900 { - compatible = "qcom,pm8941-misc"; - reg = <0x900>; - interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "usb_id"; - }; - - smbb: charger@1000 { - compatible = "qcom,pm8941-charger"; - reg = <0x1000>; - interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "chg-done", - "chg-fast", - "chg-trkl", - "bat-temp-ok", - "bat-present", - "chg-gone", - "usb-valid", - "dc-valid"; - - usb-otg-in-supply = <&pm8941_5vs1>; - - chg_otg: otg-vbus { }; - }; - - pm8941_gpios: gpio@c000 { - compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8941_gpios 0 0 36>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - boost_bypass_n_pin: boost-bypass-state { - pins = "gpio21"; - function = "normal"; - }; - }; - - pm8941_mpps: mpps@a000 { - compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pm8941_mpps 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm8941_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8941_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8941_vadc: adc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - - adc-chan@6 { - reg = ; - }; - - adc-chan@8 { - reg = ; - }; - - adc-chan@9 { - reg = ; - }; - - adc-chan@a { - reg = ; - }; - - adc-chan@e { - reg = ; - }; - - adc-chan@f { - reg = ; - }; - - adc-chan@30 { - reg = ; - }; - }; - - pm8941_iadc: adc@3600 { - compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc"; - reg = <0x3600>; - interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; - qcom,external-resistor-micro-ohms = <10000>; - }; - - pm8941_coincell: charger@2800 { - compatible = "qcom,pm8941-coincell"; - reg = <0x2800>; - status = "disabled"; - }; - }; - - pm8941_1: pm8941@1 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8941_lpg: pwm { - compatible = "qcom,pm8941-lpg"; - - #address-cells = <1>; - #size-cells = <0>; - #pwm-cells = <2>; - - status = "disabled"; - }; - - pm8941_vib: vibrator@c000 { - compatible = "qcom,pm8916-vib"; - reg = <0xc000>; - status = "disabled"; - }; - - pm8941_wled: wled@d800 { - compatible = "qcom,pm8941-wled"; - reg = <0xd800>; - label = "backlight"; - - status = "disabled"; - }; - - regulators { - compatible = "qcom,pm8941-regulators"; - interrupts = <0x1 0x83 0x2 0>, <0x1 0x84 0x2 0>; - interrupt-names = "ocp-5vs1", "ocp-5vs2"; - vin_5vs-supply = <&pm8941_5v>; - - pm8941_5v: s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-enable-ramp-delay = <500>; - }; - - pm8941_5vs1: 5vs1 { - regulator-enable-ramp-delay = <1000>; - regulator-pull-down; - regulator-over-current-protection; - qcom,ocp-max-retries = <10>; - qcom,ocp-retry-delay = <30>; - qcom,vs-soft-start-strength = <0>; - regulator-initial-mode = <1>; - }; - - pm8941_5vs2: 5vs2 { - regulator-enable-ramp-delay = <1000>; - regulator-pull-down; - regulator-over-current-protection; - qcom,ocp-max-retries = <10>; - qcom,ocp-retry-delay = <30>; - qcom,vs-soft-start-strength = <0>; - regulator-initial-mode = <1>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi deleted file mode 100644 index 2dd4c6aa71c9..000000000000 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -&spmi_bus { - - pma8084_0: pma8084@0 { - compatible = "qcom,pma8084", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, - <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - }; - - pma8084_gpios: gpio@c000 { - compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pma8084_gpios 0 0 22>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pma8084_mpps: mpps@a000 { - compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pma8084_mpps 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pma8084_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - #thermal-sensor-cells = <0>; - io-channels = <&pma8084_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - }; - - pma8084_vadc: adc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@8 { - reg = ; - }; - - adc-chan@9 { - reg = ; - }; - - adc-chan@a { - reg = ; - }; - - adc-chan@c { - reg = ; - }; - - adc-chan@e { - reg = ; - }; - - adc-chan@f { - reg = ; - }; - }; - }; - - pma8084_1: pma8084@1 { - compatible = "qcom,pma8084", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi deleted file mode 100644 index e1b869480bbd..000000000000 --- a/arch/arm/boot/dts/qcom-pmx55.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause - -/* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2020, Linaro Limited - */ - -#include -#include -#include - -&spmi_bus { - pmic@8 { - compatible = "qcom,pmx55", "qcom,spmi-pmic"; - reg = <0x8 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - - status = "disabled"; - }; - - pmx55_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; - io-channels = <&pmx55_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pmx55_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - - chg-temp@9 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "chg_temp"; - }; - }; - - pmx55_gpios: gpio@c000 { - compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmx55_gpios 0 0 11>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@9 { - compatible = "qcom,pmx55", "qcom,spmi-pmic"; - reg = <0x9 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi deleted file mode 100644 index 1c7fdf59c1f5..000000000000 --- a/arch/arm/boot/dts/qcom-pmx65.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include - -&spmi_bus { - pmic@1 { - compatible = "qcom,pmx65", "qcom,spmi-pmic"; - reg = <1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmx65_temp: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmx65_gpios: gpio@8800 { - compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmx65_gpios 0 0 16>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts deleted file mode 100644 index 7e97ad5803d8..000000000000 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2020, Linaro Ltd. - */ - -/dts-v1/; - -#include "qcom-sdx55.dtsi" -#include -#include -#include "qcom-pmx55.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SDX55 MTP"; - compatible = "qcom,sdx55-mtp", "qcom,sdx55"; - qcom,board-id = <0x5010008 0x0>; - - aliases { - serial0 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_debug_mem: memory@8ef00000 { - no-map; - reg = <0x8ef00000 0x800000>; - }; - - ipa_fw_mem: memory@8fced000 { - no-map; - reg = <0x8fced000 0x10000>; - }; - - mpss_adsp_mem: memory@90c00000 { - no-map; - reg = <0x90c00000 0xd400000>; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_bob_3p3: pmx55-bob { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - vreg_s7e_mx_0p752: pmx55-s7e { - compatible = "regulator-fixed"; - regulator-name = "vreg_s7e_mx_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - - vin-supply = <&vph_pwr>; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmx55-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-l1-l2-supply = <&vreg_s2e_1p224>; - vdd-l3-l9-supply = <&vreg_s3e_0p824>; - vdd-l4-l12-supply = <&vreg_s4e_1p904>; - vdd-l5-l6-supply = <&vreg_s4e_1p904>; - vdd-l7-l8-supply = <&vreg_s3e_0p824>; - vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; - vdd-l14-supply = <&vreg_s7e_mx_0p752>; - vdd-l15-supply = <&vreg_s2e_1p224>; - vdd-l16-supply = <&vreg_s4e_1p904>; - - vreg_s2e_1p224: smps2 { - regulator-min-microvolt = <1280000>; - regulator-max-microvolt = <1400000>; - }; - - vreg_s3e_0p824: smps3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - }; - - vreg_s4e_1p904: smps4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1960000>; - }; - - vreg_l1e_bb_1p2: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo2 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - ldo3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l4e_bb_0p875: ldo4 { - regulator-min-microvolt = <872000>; - regulator-max-microvolt = <872000>; - regulator-initial-mode = ; - }; - - vreg_l5e_bb_1p7: ldo5 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1900000>; - regulator-initial-mode = ; - }; - - ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - ldo7 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <900000>; - regulator-initial-mode = ; - }; - - ldo8 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <900000>; - regulator-initial-mode = ; - }; - - ldo9 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l10e_3p1: ldo10 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - ldo11 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo13 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo14 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - ldo15 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo16 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - status = "okay"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; -}; - -&remoteproc_mpss { - memory-region = <&mpss_adsp_mem>; -}; - -&usb { - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_hsphy { - status = "okay"; - vdda-pll-supply = <&vreg_l4e_bb_0p875>; - vdda33-supply = <&vreg_l10e_3p1>; - vdda18-supply = <&vreg_l5e_bb_1p7>; -}; - -&usb_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l4e_bb_0p875>; - vdda-pll-supply = <&vreg_l1e_bb_1p2>; -}; diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts deleted file mode 100644 index 51058b065279..000000000000 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include "qcom-sdx55.dtsi" -#include "qcom-pmx55.dtsi" - -/ { - model = "Thundercomm T55 Development Kit"; - compatible = "qcom,sdx55-t55", "qcom,sdx55"; - qcom,board-id = <0xb010008 0x4>; - - aliases { - serial0 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_debug_mem: memory@8ef00000 { - no-map; - reg = <0x8ef00000 0x800000>; - }; - - ipa_fw_mem: memory@8fced000 { - no-map; - reg = <0x8fced000 0x10000>; - }; - - mpss_adsp_mem: memory@90800000 { - no-map; - reg = <0x90800000 0xf800000>; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_bob_3p3: pmx55-bob { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - vreg_s7e_mx_0p752: pmx55-s7e { - compatible = "regulator-fixed"; - regulator-name = "vreg_s7e_mx_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - - vin-supply = <&vph_pwr>; - }; - - vreg_sd_vdd: sd-vdd { - compatible = "regulator-fixed"; - regulator-name = "vreg_sd_vdd"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - vin-supply = <&vreg_vddpx_2>; - }; - - vreg_vddpx_2: vddpx-2 { - compatible = "regulator-gpio"; - regulator-name = "vreg_vddpx_2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2850000>; - enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; - gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; - states = <1800000 0>, <2850000 1>; - startup-delay-us = <200000>; - enable-active-high; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmx55-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-l1-l2-supply = <&vreg_s2e_1p224>; - vdd-l3-l9-supply = <&vreg_s3e_0p824>; - vdd-l4-l12-supply = <&vreg_s4e_1p904>; - vdd-l5-l6-supply = <&vreg_s4e_1p904>; - vdd-l7-l8-supply = <&vreg_s3e_0p824>; - vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; - vdd-l14-supply = <&vreg_s7e_mx_0p752>; - vdd-l15-supply = <&vreg_s2e_1p224>; - vdd-l16-supply = <&vreg_s4e_1p904>; - - vreg_s2e_1p224: smps2 { - regulator-min-microvolt = <1280000>; - regulator-max-microvolt = <1400000>; - }; - - vreg_s3e_0p824: smps3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - }; - - vreg_s4e_1p904: smps4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1960000>; - }; - - vreg_l1e_bb_1p2: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo2 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - ldo3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l4e_bb_0p875: ldo4 { - regulator-min-microvolt = <872000>; - regulator-max-microvolt = <872000>; - regulator-initial-mode = ; - }; - - vreg_l5e_bb_1p7: ldo5 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1900000>; - regulator-initial-mode = ; - }; - - ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - ldo7 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <900000>; - regulator-initial-mode = ; - }; - - ldo8 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <900000>; - regulator-initial-mode = ; - }; - - ldo9 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l10e_3p1: ldo10 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - ldo11 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo13 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo14 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - ldo15 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo16 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; - -&ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - status = "okay"; -}; - -&pcie_phy { - vdda-phy-supply = <&vreg_l1e_bb_1p2>; - vdda-pll-supply = <&vreg_l4e_bb_0p875>; - - status = "okay"; -}; - -&pcie_rc { - perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&pcie_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - status = "okay"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - /* efs2 partition is secured */ - secure-regions = /bits/ 64 <0x500000 0xb00000>; - }; -}; - -&remoteproc_mpss { - memory-region = <&mpss_adsp_mem>; - status = "okay"; -}; - -&tlmm { - pcie_default: pcie-default-state { - clkreq-pins { - pins = "gpio56"; - function = "pcie_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-pins { - pins = "gpio57"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - wake-pins { - pins = "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&usb_hsphy { - vdda-pll-supply = <&vreg_l4e_bb_0p875>; - vdda33-supply = <&vreg_l10e_3p1>; - vdda18-supply = <&vreg_l5e_bb_1p7>; - - status = "okay"; -}; - -&usb_qmpphy { - vdda-phy-supply = <&vreg_l4e_bb_0p875>; - vdda-pll-supply = <&vreg_l1e_bb_1p2>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "peripheral"; -}; diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts deleted file mode 100644 index 8fadc6e70692..000000000000 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include "qcom-sdx55.dtsi" -#include "qcom-pmx55.dtsi" - -/ { - model = "Telit FN980 TLB"; - compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55"; - qcom,board-id = <0xb010008 0x0>; - - aliases { - serial0 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_debug_mem: memory@8ef00000 { - no-map; - reg = <0x8ef00000 0x800000>; - }; - - ipa_fw_mem: memory@8fced000 { - no-map; - reg = <0x8fced000 0x10000>; - }; - - mpss_adsp_mem: memory@90800000 { - no-map; - reg = <0x90800000 0xf800000>; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_bob_3p3: pmx55-bob { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - vreg_s7e_mx_0p752: pmx55-s7e { - compatible = "regulator-fixed"; - regulator-name = "vreg_s7e_mx_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - - vin-supply = <&vph_pwr>; - }; - - vreg_sd_vdd: sd-vdd { - compatible = "regulator-fixed"; - regulator-name = "vreg_sd_vdd"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - vin-supply = <&vreg_vddpx_2>; - }; - - vreg_vddpx_2: vddpx-2 { - compatible = "regulator-gpio"; - regulator-name = "vreg_vddpx_2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2850000>; - enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; - gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; - states = <1800000 0>, <2850000 1>; - startup-delay-us = <200000>; - enable-active-high; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmx55-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-l1-l2-supply = <&vreg_s2e_1p224>; - vdd-l3-l9-supply = <&vreg_s3e_0p824>; - vdd-l4-l12-supply = <&vreg_s4e_1p904>; - vdd-l5-l6-supply = <&vreg_s4e_1p904>; - vdd-l7-l8-supply = <&vreg_s3e_0p824>; - vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; - vdd-l14-supply = <&vreg_s7e_mx_0p752>; - vdd-l15-supply = <&vreg_s2e_1p224>; - vdd-l16-supply = <&vreg_s4e_1p904>; - - vreg_s2e_1p224: smps2 { - regulator-min-microvolt = <1280000>; - regulator-max-microvolt = <1400000>; - }; - - vreg_s3e_0p824: smps3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - }; - - vreg_s4e_1p904: smps4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1960000>; - }; - - vreg_l1e_bb_1p2: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo2 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - ldo3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l4e_bb_0p875: ldo4 { - regulator-min-microvolt = <872000>; - regulator-max-microvolt = <872000>; - regulator-initial-mode = ; - }; - - vreg_l5e_bb_1p7: ldo5 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1900000>; - regulator-initial-mode = ; - }; - - ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - ldo7 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <900000>; - regulator-initial-mode = ; - }; - - ldo8 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <900000>; - regulator-initial-mode = ; - }; - - ldo9 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l10e_3p1: ldo10 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - ldo11 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo13 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo14 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - ldo15 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo16 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; - -&ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - status = "okay"; -}; - -&pcie_phy { - vdda-phy-supply = <&vreg_l1e_bb_1p2>; - vdda-pll-supply = <&vreg_l4e_bb_0p875>; - - status = "okay"; -}; - -&pcie_ep { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default - &pcie_ep_wake_default>; - - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - status = "okay"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - /* ico and efs2 partitions are secured */ - secure-regions = /bits/ 64 <0x500000 0x500000 - 0xa00000 0xb00000>; - }; -}; - -&remoteproc_mpss { - memory-region = <&mpss_adsp_mem>; - status = "okay"; -}; - -&tlmm { - pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { - pins = "gpio56"; - function = "pcie_clkreq"; - drive-strength = <2>; - bias-disable; - }; - - pcie_ep_perst_default: pcie-ep-perst-default-state { - pins = "gpio57"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - pcie_ep_wake_default: pcie-ep-wake-default-state { - pins = "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb_hsphy { - vdda-pll-supply = <&vreg_l4e_bb_0p875>; - vdda33-supply = <&vreg_l10e_3p1>; - vdda18-supply = <&vreg_l5e_bb_1p7>; - - status = "okay"; -}; - -&usb_qmpphy { - vdda-phy-supply = <&vreg_l4e_bb_0p875>; - vdda-pll-supply = <&vreg_l1e_bb_1p2>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "peripheral"; -}; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi deleted file mode 100644 index df3cd9c4ffb9..000000000000 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ /dev/null @@ -1,881 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SDX55 SoC device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2020, Linaro Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0 0>; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - - nand_clk_dummy: nand-clk-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - enable-method = "psci"; - clocks = <&apcs>; - power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-sdx55", "qcom,scm"; - }; - }; - - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-345600000 { - opp-hz = /bits/ 64 <345600000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - required-opps = <&rpmhpd_opp_turbo>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hyp_mem: memory@8fc00000 { - no-map; - reg = <0x8fc00000 0x80000>; - }; - - ac_db_mem: memory@8fc80000 { - no-map; - reg = <0x8fc80000 0x40000>; - }; - - secdata_mem: memory@8fcfd000 { - no-map; - reg = <0x8fcfd000 0x1000>; - }; - - sbl_mem: memory@8fd00000 { - no-map; - reg = <0x8fd00000 0x100000>; - }; - - aop_image: memory@8fe00000 { - no-map; - reg = <0x8fe00000 0x20000>; - }; - - aop_cmd_db: memory@8fe20000 { - compatible = "qcom,cmd-db"; - reg = <0x8fe20000 0x20000>; - no-map; - }; - - smem_mem: memory@8fe40000 { - no-map; - reg = <0x8fe40000 0xc0000>; - }; - - tz_mem: memory@8ff00000 { - no-map; - reg = <0x8ff00000 0x100000>; - }; - - tz_apps_mem: memory@90000000 { - no-map; - reg = <0x90000000 0x500000>; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdx55"; - reg = <0x100000 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; - }; - - blsp1_uart3: serial@831000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x00831000 0x200>; - interrupts = ; - clocks = <&gcc 30>, - <&gcc 9>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - usb_hsphy: phy@ff4000 { - compatible = "qcom,sdx55-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0x00ff4000 0x114>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_BCR>; - }; - - usb_qmpphy: phy@ff6000 { - compatible = "qcom,sdx55-qmp-usb3-uni-phy"; - reg = <0x00ff6000 0x1c0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3PHY_PHY_BCR>, - <&gcc GCC_USB3_PHY_BCR>; - reset-names = "phy", "common"; - - usb_ssphy: phy@ff6200 { - reg = <0x00ff6200 0x170>, - <0x00ff6400 0x200>, - <0x00ff6800 0x800>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - mc_virt: interconnect@1100000 { - compatible = "qcom,sdx55-mc-virt"; - reg = <0x01100000 0x400000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mem_noc: interconnect@9680000 { - compatible = "qcom,sdx55-mem-noc"; - reg = <0x09680000 0x40000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@162c000 { - compatible = "qcom,sdx55-system-noc"; - reg = <0x0162c000 0x31200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - qpic_bam: dma-controller@1b04000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x01b04000 0x1c000>; - interrupts = ; - clocks = <&rpmhcc RPMH_QPIC_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - status = "disabled"; - }; - - qpic_nand: nand-controller@1b30000 { - compatible = "qcom,sdx55-nand"; - reg = <0x01b30000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&rpmhcc RPMH_QPIC_CLK>, - <&nand_clk_dummy>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - status = "disabled"; - }; - - pcie_rc: pcie@1c00000 { - compatible = "qcom,pcie-sdx55"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40100000 0x100000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; - - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "msi", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "msi8"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_PIPE_CLK>, - <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "sleep"; - - assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; - assigned-clock-rates = <19200000>; - - iommu-map = <0x0 &apps_smmu 0x0200 0x1>, - <0x100 &apps_smmu 0x0201 0x1>, - <0x200 &apps_smmu 0x0202 0x1>, - <0x300 &apps_smmu 0x0203 0x1>, - <0x400 &apps_smmu 0x0204 0x1>; - - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_GDSC>; - - phys = <&pcie_lane>; - phy-names = "pciephy"; - - status = "disabled"; - }; - - pcie_ep: pcie-ep@1c00000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "sleep", - "ref"; - - interrupts = , - ; - interrupt-names = "global", - "doorbell"; - - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "pcie-mem"; - - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - - pcie_phy: phy@1c07000 { - compatible = "qcom,sdx55-qmp-pcie-phy"; - reg = <0x01c07000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "refgen"; - - resets = <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie_lane: lanes@1c06000 { - reg = <0x01c06000 0x104>, /* tx0 */ - <0x01c06200 0x328>, /* rx0 */ - <0x01c07200 0x1e8>, /* pcs */ - <0x01c06800 0x104>, /* tx1 */ - <0x01c06a00 0x328>, /* rx1 */ - <0x01c07600 0x800>; /* pcs_misc */ - clocks = <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - }; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sdx55-ipa"; - - iommus = <&apps_smmu 0x5e0 0x0>, - <&apps_smmu 0x5e2 0x0>; - reg = <0x1e40000 0x7000>, - <0x1e50000 0x4b20>, - <0x1e04000 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, - <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, - <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01f40000 0x40000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@1fc0000 { - compatible = "qcom,sdx55-tcsr", "syscon"; - reg = <0x01fc0000 0x1000>; - }; - - sdhc_1: mmc@8804000 { - compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x08804000 0x1000>; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "iface", "core"; - status = "disabled"; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sdx55-mpss-pas"; - reg = <0x04080000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SDX55_CX>, - <&rpmhpd SDX55_MSS>; - power-domain-names = "cx", "mss"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "mpss"; - qcom,remote-pid = <1>; - mboxes = <&apcs 15>; - }; - }; - - usb: usb@a6f8800 { - compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; - reg = <0x0a6f8800 0x400>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_USB30_MSTR_AXI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_GDSC>; - - resets = <&gcc GCC_USB30_BCR>; - - usb_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0x0a600000 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x1a0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_hsphy>, <&usb_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - pdc: interrupt-controller@b210000 { - compatible = "qcom,sdx55-pdc", "qcom,pdc"; - reg = <0x0b210000 0x30000>; - qcom,pdc-ranges = <0 179 52>; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - restart@c264000 { - compatible = "qcom,pshold"; - reg = <0x0c264000 0x1000>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0c440000 0x0000d00>, - <0x0c600000 0x2000000>, - <0x0e600000 0x0100000>, - <0x0e700000 0x00a0000>, - <0x0c40a000 0x0000700>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sdx55-pinctrl"; - reg = <0xf100000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 108>; - }; - - sram@1468f000 { - compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; - reg = <0x1468f000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x0 0x1468f000 0x1000>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0x200>; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x15000000 0x20000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17800000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - interrupt-parent = <&intc>; - #interrupt-cells = <3>; - reg = <0x17800000 0x1000>, - <0x17802000 0x1000>; - }; - - a7pll: clock@17808000 { - compatible = "qcom,sdx55-a7pll"; - reg = <0x17808000 0x1000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <0>; - }; - - apcs: mailbox@17810000 { - compatible = "qcom,sdx55-apcs-gcc", "syscon"; - reg = <0x17810000 0x2000>; - #mbox-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; - clock-names = "ref", "pll", "aux"; - #clock-cells = <0>; - }; - - watchdog@17817000 { - compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; - reg = <0x17817000 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17820000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17820000 0x1000>; - clock-frequency = <19200000>; - - frame@17821000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17821000 0x1000>, - <0x17822000 0x1000>; - }; - - frame@17823000 { - frame-number = <1>; - interrupts = ; - reg = <0x17823000 0x1000>; - status = "disabled"; - }; - - frame@17824000 { - frame-number = <2>; - interrupts = ; - reg = <0x17824000 0x1000>; - status = "disabled"; - }; - - frame@17825000 { - frame-number = <3>; - interrupts = ; - reg = <0x17825000 0x1000>; - status = "disabled"; - }; - - frame@17826000 { - frame-number = <4>; - interrupts = ; - reg = <0x17826000 0x1000>; - status = "disabled"; - }; - - frame@17827000 { - frame-number = <5>; - interrupts = ; - reg = <0x17827000 0x1000>; - status = "disabled"; - }; - - frame@17828000 { - frame-number = <6>; - interrupts = ; - reg = <0x17828000 0x1000>; - status = "disabled"; - }; - - frame@17829000 { - frame-number = <7>; - interrupts = ; - reg = <0x17829000 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17830000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x17830000 0x10000>, <0x17840000 0x10000>; - reg-names = "drv-0", "drv-1"; - interrupts = , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <1>; - qcom,tcs-config = , , - , ; - - rpmhcc: clock-controller { - compatible = "qcom,sdx55-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdx55-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; -}; diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts deleted file mode 100644 index 02d8d6e241ae..000000000000 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. - */ -/dts-v1/; - -#include "qcom-sdx65.dtsi" -#include -#include -#include -#include "qcom-pmx65.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SDX65 MTP"; - compatible = "qcom,sdx65-mtp", "qcom,sdx65"; - qcom,board-id = <0x2010008 0x302>; - - aliases { - serial0 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_dsm: memory@8c400000 { - no-map; - reg = <0x8c400000 0x3200000>; - }; - - ipa_fw_mem: memory@8fced000 { - no-map; - reg = <0x8fced000 0x10000>; - }; - - mpss_adsp_mem: memory@90800000 { - no-map; - reg = <0x90800000 0x10000000>; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_bob_3p3: pmx65_bob { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmx65-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-l1-supply = <&vreg_s2b_1p224>; - vdd-l2-l18-supply = <&vreg_s2b_1p224>; - vdd-l3-supply = <&vreg_s8b_0p824>; - vdd-l4-supply = <&vreg_s7b_0p936>; - vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>; - vdd-l7-supply = <&vreg_s3b_0p776>; - vdd-l8-l9-supply = <&vreg_s8b_0p824>; - vdd-l10-supply = <&vreg_bob_3p3>; - vdd-l11-l13-supply = <&vreg_bob_3p3>; - vdd-l12-supply = <&vreg_s2b_1p224>; - vdd-l14-supply = <&vreg_s3b_0p776>; - vdd-l15-supply = <&vreg_s2b_1p224>; - vdd-l17-supply = <&vreg_s8b_0p824>; - vdd-l19-supply = <&vreg_s3b_0p776>; - vdd-l20-supply = <&vreg_s7b_0p936>; - vdd-l21-supply = <&vreg_s7b_0p936>; - - vreg_s2b_1p224: smps2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - }; - - vreg_s3b_0p776: smps3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1040000>; - }; - - vreg_s4b_1p824: smps4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2024000>; - }; - - vreg_s7b_0p936: smps7 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1040000>; - }; - - vreg_s8b_0p824: smps8 { - regulator-min-microvolt = <304000>; - regulator-max-microvolt = <1300000>; - }; - - vreg_l1b_1p2: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo2 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - ldo3 { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <960000>; - regulator-initial-mode = ; - }; - - vreg_l4b_0p88: ldo4 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - vreg_l5b_1p8: ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - ldo7 { - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - ldo8 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - ldo9 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l10b_3p08: ldo10 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - ldo11 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo13 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - ldo14 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - ldo15 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ldo16 { - regulator-min-microvolt = <1776000>; - regulator-max-microvolt = <1776000>; - regulator-initial-mode = ; - }; - - ldo17 { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <960000>; - regulator-initial-mode = ; - }; - - ldo19 { - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - ldo20 { - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - ldo21 { - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; - -&ipa { - qcom,gsi-loader = "skip"; - status = "okay"; -}; - -&pcie_ep { - pinctrl-0 = <&pcie_ep_clkreq_default - &pcie_ep_perst_default - &pcie_ep_wake_default>; - pinctrl-names = "default"; - - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&pcie_phy { - vdda-phy-supply = <&vreg_l1b_1p2>; - vdda-pll-supply = <&vreg_l4b_0p88>; - - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - status = "okay"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - /* ico and efs2 partitions are secured */ - secure-regions = /bits/ 64 <0x500000 0x500000 - 0xa00000 0xb00000>; - }; -}; - -&remoteproc_mpss { - memory-region = <&mpss_adsp_mem>; - status = "okay"; -}; - -&tlmm { - pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { - pins = "gpio56"; - function = "pcie_clkreq"; - drive-strength = <2>; - bias-disable; - }; - - pcie_ep_perst_default: pcie-ep-perst-default-state { - pins = "gpio57"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - pcie_ep_wake_default: pcie-ep-wake-default-state { - pins = "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_hsphy { - vdda-pll-supply = <&vreg_l4b_0p88>; - vdda33-supply = <&vreg_l10b_3p08>; - vdda18-supply = <&vreg_l5b_1p8>; - status = "okay"; -}; - -&usb_qmpphy { - vdda-phy-supply = <&vreg_l4b_0p88>; - vdda-pll-supply = <&vreg_l1b_1p2>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi deleted file mode 100644 index 1a3583029a64..000000000000 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ /dev/null @@ -1,811 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SDX65 SoC device tree source - * - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0 0>; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <76800000>; - clock-output-names = "xo_board"; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - #clock-cells = <0>; - }; - - nand_clk_dummy: nand-clk-dummy { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - enable-method = "psci"; - clocks = <&apcs>; - power-domains = <&rpmhpd SDX65_CX_AO>; - power-domain-names = "rpmhpd"; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-sdx65", "qcom,scm"; - }; - }; - - mc_virt: interconnect-mc-virt { - compatible = "qcom,sdx65-mc-virt"; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-345600000 { - opp-hz = /bits/ 64 <345600000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - required-opps = <&rpmhpd_opp_turbo>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved_memory: reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tz_heap_mem: memory@8fcad000 { - no-map; - reg = <0x8fcad000 0x40000>; - }; - - secdata_mem: memory@8fcfd000 { - no-map; - reg = <0x8fcfd000 0x1000>; - }; - - hyp_mem: memory@8fd00000 { - no-map; - reg = <0x8fd00000 0x80000>; - }; - - access_control_mem: memory@8fd80000 { - no-map; - reg = <0x8fd80000 0x80000>; - }; - - aop_mem: memory@8fe00000 { - no-map; - reg = <0x8fe00000 0x20000>; - }; - - smem_mem: memory@8fe20000 { - compatible = "qcom,smem"; - reg = <0x8fe20000 0xc0000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - - cmd_db: reserved-memory@8fee0000 { - compatible = "qcom,cmd-db"; - reg = <0x8fee0000 0x20000>; - no-map; - }; - - tz_mem: memory@8ff00000 { - no-map; - reg = <0x8ff00000 0x100000>; - }; - - tz_apps_mem: memory@90000000 { - no-map; - reg = <0x90000000 0x500000>; - }; - - llcc_tcm_mem: memory@15800000 { - no-map; - reg = <0x15800000 0x800000>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdx65"; - reg = <0x00100000 0x001f7400>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - #power-domain-cells = <1>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - blsp1_uart3: serial@831000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x00831000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - usb_hsphy: phy@ff4000 { - compatible = "qcom,sdx65-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0xff4000 0x120>; - #phy-cells = <0>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - resets = <&gcc GCC_QUSB2PHY_BCR>; - status = "disabled"; - }; - - usb_qmpphy: phy@ff6000 { - compatible = "qcom,sdx65-qmp-usb3-uni-phy"; - reg = <0x00ff6000 0x1c8>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_EN>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3PHY_PHY_BCR>, - <&gcc GCC_USB3_PHY_BCR>; - reset-names = "phy", "common"; - - status = "disabled"; - - usb_ssphy: phy@ff6200 { - reg = <0x00ff6e00 0x160>, - <0x00ff7000 0x1ec>, - <0x00ff6200 0x1e00>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sdx65-system-noc"; - reg = <0x01620000 0x31200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - qpic_bam: dma-controller@1b04000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x01b04000 0x1c000>; - interrupts = ; - clocks = <&rpmhcc RPMH_QPIC_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - status = "disabled"; - }; - - qpic_nand: nand-controller@1b30000 { - compatible = "qcom,sdx55-nand"; - reg = <0x01b30000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&rpmhcc RPMH_QPIC_CLK>, - <&nand_clk_dummy>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - status = "disabled"; - }; - - pcie_ep: pcie-ep@1c00000 { - compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xa8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_EN>; - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "sleep", - "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - - power-domains = <&gcc PCIE_GDSC>; - - phys = <&pcie_phy>; - phy-names = "pcie-phy"; - - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - - pcie_phy: phy@1c06000 { - compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; - reg = <0x01c06000 0x2000>; - - clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>, - <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe"; - - resets = <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc PCIE_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01f40000 0x40000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@1fcb000 { - compatible = "qcom,sdx65-tcsr", "syscon"; - reg = <0x01fc0000 0x1000>; - }; - - ipa: ipa@3f40000 { - compatible = "qcom,sdx65-ipa"; - - reg = <0x03f40000 0x10000>, - <0x03f50000 0x5000>, - <0x03e04000 0xfc000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - iommus = <&apps_smmu 0x5e0 0x0>, - <&apps_smmu 0x5e2 0x0>; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; - interconnect-names = "memory", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sdx55-mpss-pas"; - reg = <0x04080000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SDX65_CX>, - <&rpmhpd SDX65_MSS>; - power-domain-names = "cx", "mss"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "mpss"; - qcom,remote-pid = <1>; - mboxes = <&apcs 15>; - }; - }; - - sdhc_1: mmc@8804000 { - compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x08804000 0x1000>; - reg-names = "hc"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - mem_noc: interconnect@9680000 { - compatible = "qcom,sdx65-mem-noc"; - reg = <0x09680000 0x27200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb: usb@a6f8800 { - compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; - reg = <0x0a6f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_USB30_MSTR_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 18 IRQ_TYPE_EDGE_BOTH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", - "dm_hs_phy_irq", - "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_GDSC>; - - resets = <&gcc GCC_USB30_BCR>; - - status = "disabled"; - - usb_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0a600000 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x1a0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_hsphy>, <&usb_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - restart@c264000 { - compatible = "qcom,pshold"; - reg = <0x0c264000 0x1000>; - }; - - spmi_bus: qcom,spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xc440000 0xd00>, - <0xc600000 0x2000000>, - <0xe600000 0x100000>, - <0xe700000 0xa0000>, - <0xc40a000 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <0>; - cell-index = <0>; - qcom,channel = <0>; - qcom,ee = <0>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sdx65-tlmm"; - reg = <0xf100000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 109>; - interrupt-controller; - interrupt-parent = <&intc>; - #interrupt-cells = <2>; - }; - - pdc: interrupt-controller@b210000 { - compatible = "qcom,sdx65-pdc", "qcom,pdc"; - reg = <0xb210000 0x10000>; - qcom,pdc-ranges = <0 147 52>, <52 266 32>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - sram@1468f000 { - compatible = "qcom,sdx65-imem", "syscon", "simple-mfd"; - reg = <0x1468f000 0x1000>; - ranges = <0x0 0x1468f000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0xc8>; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x15000000 0x40000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17800000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - interrupt-parent = <&intc>; - #interrupt-cells = <3>; - reg = <0x17800000 0x1000>, - <0x17802000 0x1000>; - }; - - a7pll: clock@17808000 { - compatible = "qcom,sdx55-a7pll"; - reg = <0x17808000 0x1000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <0>; - }; - - apcs: mailbox@17810000 { - compatible = "qcom,sdx55-apcs-gcc", "syscon"; - reg = <0x17810000 0x2000>; - #mbox-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; - clock-names = "ref", "pll", "aux"; - #clock-cells = <0>; - }; - - watchdog@17817000 { - compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; - reg = <0x17817000 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17820000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17820000 0x1000>; - clock-frequency = <19200000>; - - frame@17821000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17821000 0x1000>, - <0x17822000 0x1000>; - }; - - frame@17823000 { - frame-number = <1>; - interrupts = ; - reg = <0x17823000 0x1000>; - status = "disabled"; - }; - - frame@17824000 { - frame-number = <2>; - interrupts = ; - reg = <0x17824000 0x1000>; - status = "disabled"; - }; - - frame@17825000 { - frame-number = <3>; - interrupts = ; - reg = <0x17825000 0x1000>; - status = "disabled"; - }; - - frame@17826000 { - frame-number = <4>; - interrupts = ; - reg = <0x17826000 0x1000>; - status = "disabled"; - }; - - frame@17827000 { - frame-number = <5>; - interrupts = ; - reg = <0x17827000 0x1000>; - status = "disabled"; - }; - - frame@17828000 { - frame-number = <6>; - interrupts = ; - reg = <0x17828000 0x1000>; - status = "disabled"; - }; - - frame@17829000 { - frame-number = <7>; - interrupts = ; - reg = <0x17829000 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17830000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x17830000 0x10000>, - <0x17840000 0x10000>; - reg-names = "drv-0", "drv-1"; - interrupts = , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <1>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sdx65-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdx65-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 12 0xf08>, - <1 10 0xf08>, - <1 11 0xf08>; - clock-frequency = <19200000>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile new file mode 100644 index 000000000000..3dfb1c8cefb8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/Makefile @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8016-sbc.dtb \ + qcom-apq8026-asus-sparrow.dtb \ + qcom-apq8026-huawei-sturgeon.dtb \ + qcom-apq8026-lg-lenok.dtb \ + qcom-apq8026-samsung-matisse-wifi.dtb \ + qcom-apq8060-dragonboard.dtb \ + qcom-apq8064-cm-qs600.dtb \ + qcom-apq8064-ifc6410.dtb \ + qcom-apq8064-sony-xperia-lagan-yuga.dtb \ + qcom-apq8064-asus-nexus7-flo.dtb \ + qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-ifc6540.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-ipq4018-ap120c-ac.dtb \ + qcom-ipq4018-ap120c-ac-bit.dtb \ + qcom-ipq4018-jalapeno.dtb \ + qcom-ipq4019-ap.dk01.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c3.dtb \ + qcom-ipq4019-ap.dk07.1-c1.dtb \ + qcom-ipq4019-ap.dk07.1-c2.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-rb3011.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8916-samsung-e5.dtb \ + qcom-msm8916-samsung-e7.dtb \ + qcom-msm8916-samsung-grandmax.dtb \ + qcom-msm8916-samsung-serranove.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8960-samsung-expressatt.dtb \ + qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-sony-xperia-rhine-amami.dtb \ + qcom-msm8974-sony-xperia-rhine-honami.dtb \ + qcom-msm8974pro-fairphone-fp2.dtb \ + qcom-msm8974pro-oneplus-bacon.dtb \ + qcom-msm8974pro-samsung-klte.dtb \ + qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ + qcom-mdm9615-wp8548-mangoh-green.dtb \ + qcom-sdx55-mtp.dtb \ + qcom-sdx55-t55.dtb \ + qcom-sdx55-telit-fn980-tlb.dtb \ + qcom-sdx65-mtp.dtb diff --git a/arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts new file mode 100644 index 000000000000..4ccd2dca74a2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/apq8016-sbc.dts" diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts new file mode 100644 index 000000000000..7a80e1c9f126 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Luca Weiss + */ + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "qcom-pm8226.dtsi" + +/delete-node/ &adsp_region; + +/ { + model = "ASUS ZenWatch 2"; + compatible = "asus,sparrow", "qcom,apq8026"; + chassis-type = "watch"; + qcom,msm-id = <199 0x20000>; + qcom,board-id = <8 3005>; + + reserved-memory { + sbl_region: sbl@2f00000 { + reg = <0x02f00000 0x100000>; + no-map; + }; + external_image_region: external-image@3100000 { + reg = <0x3100000 0x200000>; + no-map; + }; + peripheral_region: peripheral@3300000 { + reg = <0x3300000 0x600000>; + no-map; + }; + adsp_region: adsp@3900000 { + reg = <0x3900000 0x1400000>; + no-map; + }; + modem_region: modem@4d00000 { + reg = <0x4d00000 0x1b00000>; + no-map; + }; + modem_efs_region: modem-efs@7f00000 { + reg = <0x7f00000 0x100000>; + no-map; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart1_default_state>; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + }; +}; + +&pm8226_vib { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l7: l7 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + }; + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + pm8226_l15: l15 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <350000>; + qcom,fast-charge-safe-voltage = <4430000>; + qcom,fast-charge-high-threshold-voltage = <4400000>; + qcom,auto-recharge-threshold-voltage = <4300000>; + qcom,minimum-input-voltage = <4400000>; +}; + +&tlmm { + blsp1_uart1_default_state: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <8>; + bias-disable; + }; + + bluetooth_default_state: bluetooth-default-state { + pins = "gpio48", "gpio61"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + status = "okay"; + extcon = <&smbb>; + dr_mode = "peripheral"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts new file mode 100644 index 000000000000..eb73b992a696 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Luca Weiss + */ + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "qcom-pm8226.dtsi" +#include + +/delete-node/ &adsp_region; + +/ { + model = "Huawei Watch"; + compatible = "huawei,sturgeon", "qcom,apq8026"; + chassis-type = "watch"; + qcom,msm-id = <199 0x20000>; + qcom,board-id = <8 4>; + + reserved-memory { + sbl_region: sbl@2f00000 { + reg = <0x02f00000 0x100000>; + no-map; + }; + + external_image_region: external-image@3100000 { + reg = <0x3100000 0x200000>; + no-map; + }; + + peripheral_region: peripheral@3300000 { + reg = <0x3300000 0x600000>; + no-map; + }; + + adsp_region: adsp@3900000 { + reg = <0x3900000 0x1400000>; + no-map; + }; + + modem_region: modem@4d00000 { + reg = <0x4d00000 0x1b00000>; + no-map; + }; + + modem_efs_region: modem-efs@7f00000 { + reg = <0x7f00000 0x100000>; + no-map; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_i2c2 { + clock-frequency = <384000>; + + status = "okay"; + + vibrator@5a { + compatible = "ti,drv2605"; + reg = <0x5a>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + mode = ; + library-sel = ; + vib-rated-mv = <2765>; + vib-overdrive-mv = <3525>; + + pinctrl-0 = <&vibrator_default_state>; + pinctrl-names = "default"; + }; +}; + +&blsp1_i2c5 { + clock-frequency = <384000>; + + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8226_l19>; + vio-supply = <&pm8226_lvs1>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_default_state>; + + syna,startup-delay-ms = <160>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart4_default_state>; + + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43430a0-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; + }; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_3 { + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-voltage = <4370000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,minimum-input-voltage = <4350000>; + qcom,fast-charge-current-limit = <300000>; + qcom,fast-charge-safe-current = <600000>; + qcom,auto-recharge-threshold-voltage = <4240000>; +}; + +&tlmm { + blsp1_uart4_default_state: blsp1-uart4-default-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + drive-strength = <8>; + bias-disable; + }; + + bluetooth_default_state: bluetooth-default-state { + pins = "gpio63", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + touch_default_state: touch-default-state { + irq-pins { + pins = "gpio17"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + reset-pins { + pins = "gpio16"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + vibrator_default_state: vibrator-default-state { + pins = "gpio59", "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&usb { + extcon = <&smbb>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts new file mode 100644 index 000000000000..b82381229adf --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Luca Weiss + */ + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "qcom-pm8226.dtsi" + +/delete-node/ &adsp_region; + +/ { + model = "LG G Watch R"; + compatible = "lg,lenok", "qcom,apq8026"; + chassis-type = "watch"; + qcom,board-id = <132 0x0a>; + qcom,msm-id = <199 0x20000>; + + aliases { + serial0 = &blsp1_uart3; + serial1 = &blsp1_uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + sbl_region: sbl@2f00000 { + reg = <0x02f00000 0x100000>; + no-map; + }; + + external_image_region: external-image@3100000 { + reg = <0x03100000 0x200000>; + no-map; + }; + + adsp_region: adsp@3300000 { + reg = <0x03300000 0x1400000>; + no-map; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_i2c1 { + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27421"; + reg = <0x55>; + }; +}; + +&blsp1_i2c5 { + status = "okay"; + clock-frequency = <384000>; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8226_l15>; + vio-supply = <&pm8226_l22>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&blsp1_uart4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart4_default_state>; + + bluetooth { + compatible = "brcm,bcm43430a0-bt"; + + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + pm8226_l15: l15 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l18: l18 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + pm8226_l19: l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + pm8226_l28: l28 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <450000>; + qcom,fast-charge-current-limit = <400000>; + qcom,fast-charge-safe-voltage = <4350000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4240000>; + qcom,minimum-input-voltage = <4450000>; +}; + +&tlmm { + blsp1_uart4_default_state: blsp1-uart4-default-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + drive-strength = <8>; + bias-disable; + }; + + bluetooth_default_state: bluetooth-default-state { + pins = "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + touch_pins: touch-state { + irq-pins { + pins = "gpio17"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-down; + input-enable; + }; + + reset-pins { + pins = "gpio16"; + function = "gpio"; + + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + status = "okay"; + extcon = <&smbb>; + dr_mode = "peripheral"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts new file mode 100644 index 000000000000..884d99297d4c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki + */ + +/dts-v1/; + +#include +#include "qcom-msm8226.dtsi" +#include "qcom-pm8226.dtsi" + +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + +/ { + model = "Samsung Galaxy Tab 4 10.1"; + compatible = "samsung,matisse-wifi", "qcom,apq8026"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + display0 = &framebuffer0; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <1280>; + height = <800>; + stride = <(1280 * 3)>; + format = "r8g8b8"; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + interrupts = <&tlmm 110 IRQ_TYPE_EDGE_FALLING>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-home { + label = "Home"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + + pwms = <&backlight_pwm 0 100000>; + pwm-names = "lp8556"; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0x44>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x6c>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + }; + }; + + backlight_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + clocks = <&mmcc CAMSS_GP0_CLK>; + pinctrl-0 = <&backlight_pwm_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default_state>; + }; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en1_default_state>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + + mpss@8400000 { + reg = <0x08400000 0x1f00000>; + no-map; + }; + + mba@a300000 { + reg = <0x0a300000 0x100000>; + no-map; + }; + + reserved@cb00000 { + reg = <0x0cb00000 0x700000>; + no-map; + }; + + wcnss@d200000 { + reg = <0x0d200000 0x700000>; + no-map; + }; + + adsp_region: adsp@d900000 { + reg = <0x0d900000 0x1800000>; + no-map; + }; + + venus@f100000 { + reg = <0x0f100000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x260000>; + no-map; + }; + + rfsa@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_i2c2 { + status = "okay"; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_int_default_state>; + + st,drdy-int-pin = <1>; + + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + }; +}; + +&blsp1_i2c4 { + status = "okay"; + + muic: usb-switch@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_int_default_state>; + }; +}; + +&blsp1_i2c5 { + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&tlmm>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_int_rst_default_state>; + + reset-gpios = <&pm8226_gpios 6 GPIO_ACTIVE_LOW>; + + vdd-supply = <®_tsp_1p8v>; + vdda-supply = <®_tsp_3p3v>; + }; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + regulator-always-on; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + accel_int_default_state: accel-int-default-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default_state: backlight-pwm-default-state { + pins = "gpio33"; + function = "gp0_clk"; + }; + + muic_int_default_state: muic-int-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default_state: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en1_default_state: tsp-en1-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default_state: tsp-int-rst-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts new file mode 100644 index 000000000000..db4c791b2e2f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts @@ -0,0 +1,973 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +#include +#include +#include +#include +#include +#include "qcom-msm8660.dtsi" + +/ { + model = "Qualcomm APQ8060 Dragonboard"; + compatible = "qcom,apq8060-dragonboard", "qcom,msm8660"; + + aliases { + serial0 = &gsbi12_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* Main power of the board: 3.7V */ + vph: regulator-fixed { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-always-on; + regulator-boot-on; + }; + + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; + + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; + + /* This is a levelshifter for SDCC5 */ + dragon_vio_txb: txb0104rgyr { + compatible = "regulator-fixed"; + regulator-name = "Dragon SDCC levelshifter"; + vin-supply = <&pm8058_l14>; + regulator-always-on; + }; + + /* + * Capella CM3605 light and proximity sensor mounted directly + * on the sensor board. + */ + cm3605 { + compatible = "capella,cm3605"; + vdd-supply = <&pm8058_l14>; // 2.85V + aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>; + capella,aset-resistance-ohms = <100000>; + /* Trig on both edges - getting close or far away */ + interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>; + /* MPP05 analog input to the XOADC */ + io-channels = <&xoadc 0x00 0x05>; + io-channel-names = "aout"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>; + }; +}; + +&ebi2 { + /* The EBI2 will instantiate first, then populate its children */ + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ebi2_pins>; + status = "okay"; + + /* + * An on-board SMSC LAN9221 chip for "debug ethernet", + * which is actually just an ordinary ethernet on the + * EBI2. This has a 25MHz chrystal next to it, so no + * clocking is needed. + */ + ethernet@2,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <2 0x0 0x100>; + /* + * The second interrupt is the PME interrupt + * for network wakeup, connected to the TLMM. + */ + interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>, + <&tlmm 29 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + vdd33a-supply = <&dragon_veth>; + vddvario-supply = <&dragon_vario>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ethernet_gpios>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,force-external-phy; + smsc,irq-push-pull; + + /* + * SLOW chipselect config + * Delay 9 cycles (140ns@64MHz) between SMSC + * LAN9221 Ethernet controller reads and writes + * on CS2. + */ + qcom,xmem-recovery-cycles = <0>; + qcom,xmem-write-hold-cycles = <3>; + qcom,xmem-write-delta-cycles = <31>; + qcom,xmem-read-delta-cycles = <28>; + qcom,xmem-write-wait-cycles = <9>; + qcom,xmem-read-wait-cycles = <9>; + }; +}; + +&gsbi3 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi3_i2c { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi3_i2c_pins>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,cy8ctma340"; + reg = <0x24>; + /* Certainly we can do at least 400 kHz */ + clock-frequency = <400000>; + /* IRQ on GPIO61 called /CTP_INT */ + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_EDGE_FALLING>; + /* + * The I2C bus is using a PCA9306 level translator from L16A + * to L2B so these two voltages are needed and L16A is + * kind of the IO voltage, however L16Aisn't really fed to + * the TMA340, which relies entirely on L2B (PM8901 L2). + */ + vcpin-supply = <&pm8058_l16>; + vdd-supply = <&pm8901_l2>; + /* GPIO58, called WAKE_CTP */ + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + active-interval-ms = <0>; + touch-timeout-ms = <255>; + lowpower-interval-ms = <10>; + bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_tma340_gpios>; + }; +}; + +&gsbi8 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi8_i2c { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi8_i2c_pins>; + status = "okay"; + + eeprom@52 { + /* A 16KiB Platform ID EEPROM on the CPU carrier board */ + compatible = "atmel,24c128"; + reg = <0x52>; + vcc-supply = <&pm8058_s3>; + pagesize = <64>; + }; + wm8903: wm8903@1a { + /* This Woolfson Micro device has an unrouted interrupt line */ + compatible = "wlf,wm8903"; + reg = <0x1a>; + + AVDD-supply = <&pm8058_l16>; + CPVDD-supply = <&pm8058_l16>; + DBVDD-supply = <&pm8058_s3>; + DCVDD-supply = <&pm8058_l0>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; +}; + +&gsbi12 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi12_serial { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi12_serial_pins>; + status = "okay"; +}; + +&gsbi12_i2c { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi12_i2c_pins>; + status = "okay"; + + ak8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + interrupt-parent = <&pm8058_gpio>; + interrupts = <33 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ak8975_gpios>; + vid-supply = <&pm8058_lvs0>; // 1.8V + vdd-supply = <&pm8058_l14>; // 2.85V + }; + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + interrupt-parent = <&pm8058_gpio>; + interrupts = <16 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_bmp085_gpios>; + vddd-supply = <&pm8058_lvs0>; // 1.8V + vdda-supply = <&pm8058_l14>; // 2.85V + }; + mpu3050@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + /* + * GPIO17 is pulled high by a 10k + * resistor to VLOGIC so needs to be + * active low/falling edge. + */ + interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_mpu3050_gpios>; + vlogic-supply = <&pm8058_lvs0>; // 1.8V + vdd-supply = <&pm8058_l14>; // 2.85V + + /* + * The MPU-3050 acts as a hub for the + * accelerometer. + */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + kxsd9@18 { + compatible = "kionix,kxsd9"; + reg = <0x18>; + interrupt-parent = <&tlmm>; + interrupts = <57 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_kxsd9_gpios>; + iovdd-supply = <&pm8058_lvs0>; // 1.8V + vdd-supply = <&pm8058_l14>; // 2.85V + }; + }; + }; +}; + +&pm8058_gpio { + dragon_ethernet_gpios: ethernet-state { + pinconf { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_bmp085_gpios: bmp085-state { + pinconf { + pins = "gpio16"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_mpu3050_gpios: mpu3050-state { + pinconf { + pins = "gpio17"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_sdcc3_gpios: sdcc3-state { + pinconf { + pins = "gpio22"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_sdcc5_gpios: sdcc5-state { + pinconf { + pins = "gpio26"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = ; + }; + }; + dragon_ak8975_gpios: ak8975-state { + pinconf { + pins = "gpio33"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_cm3605_gpios: cm3605-state { + /* Pin 34 connected to the proxy IRQ */ + gpio34-pins { + pins = "gpio34"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + /* Pin 35 connected to ASET */ + gpio35-pins { + pins = "gpio35"; + function = "normal"; + output-high; + bias-disable; + power-source = ; + }; + }; + dragon_veth_gpios: veth-state { + pinconf { + pins = "gpio40"; + function = "normal"; + bias-disable; + drive-push-pull; + }; + }; +}; + +&pm8058_keypad { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_MENU) + MATRIX_KEY(0, 2, KEY_1) + MATRIX_KEY(0, 3, KEY_4) + MATRIX_KEY(0, 4, KEY_7) + MATRIX_KEY(1, 0, KEY_UP) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_DOWN) + MATRIX_KEY(1, 3, KEY_5) + MATRIX_KEY(1, 3, KEY_8) + MATRIX_KEY(2, 0, KEY_HOME) + MATRIX_KEY(2, 1, KEY_REPLY) + MATRIX_KEY(2, 2, KEY_2) + MATRIX_KEY(2, 3, KEY_6) + MATRIX_KEY(3, 0, KEY_VOLUMEUP) + MATRIX_KEY(3, 1, KEY_RIGHT) + MATRIX_KEY(3, 2, KEY_3) + MATRIX_KEY(3, 3, KEY_9) + MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE) + MATRIX_KEY(4, 0, KEY_VOLUMEDOWN) + MATRIX_KEY(4, 1, KEY_BACK) + MATRIX_KEY(4, 2, KEY_CAMERA) + MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) + >; + keypad,num-rows = <6>; + keypad,num-columns = <5>; +}; + +&pm8058_led48 { + /* + * The keypad LED @0x48 is routed to + * the sensor board where it is + * connected to an infrared LED + * SFH4650 (60mW, @850nm) next to the + * ambient light and proximity sensor + * Capella Microsystems CM3605. + */ + label = "pm8058:infrared:proximitysensor"; + default-state = "off"; + linux,default-trigger = "cm3605"; + status = "okay"; +}; + +&pm8058_led131 { + label = "pm8058:red"; + color = ; + default-state = "off"; + status = "okay"; +}; + +&pm8058_led132 { + /* + * This is actually green too on my + * board, but documented as yellow. + */ + label = "pm8058:yellow"; + color = ; + default-state = "off"; + linux,default-trigger = "mmc0"; + status = "okay"; +}; + +&pm8058_led133 { + label = "pm8058:green"; + function = LED_FUNCTION_HEARTBEAT; + color = ; + default-state = "on"; + linux,default-trigger = "heartbeat"; + status = "okay"; +}; + +&pm8058_mpps { + dragon_cm3605_mpps: cm3605-mpps-state { + pins = "mpp5"; + function = "analog"; + input-enable; + bias-high-impedance; + /* Let's use channel 5 */ + qcom,amux-route = ; + power-source = ; + }; +}; + +&rpm { + /* + * Set up of the PMIC RPM regulators for this board + * PM8901 supplies "preliminary regulators" whatever + * that means + */ + regulators-0 { + vdd_l0-supply = <&pm8901_s4>; + vdd_l1-supply = <&vph>; + vdd_l2-supply = <&vph>; + vdd_l3-supply = <&vph>; + vdd_l4-supply = <&vph>; + vdd_l5-supply = <&vph>; + vdd_l6-supply = <&vph>; + /* vdd_s0-supply, vdd_s1-supply: SAW regulators */ + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + lvs0_in-supply = <&pm8058_s3>; + lvs1_in-supply = <&pm8901_s4>; + lvs2_in-supply = <&pm8058_l0>; + lvs3_in-supply = <&pm8058_s2>; + mvs_in-supply = <&pm8058_s3>; + + l0 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + l2 { + /* TMA340 requires strictly 3.3V */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + l3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + l4 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l6 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + bias-pull-down; + }; + + /* s0 and s1 are SAW regulators controlled over SPM */ + s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* LVS0 thru 3 and mvs are just switches */ + lvs0 { + regulator-always-on; + }; + lvs1 { }; + lvs2 { }; + lvs3 { }; + mvs { }; + + }; + + regulators-1 { + vdd_l0_l1_lvs-supply = <&pm8058_s3>; + vdd_l2_l11_l12-supply = <&vph>; + vdd_l3_l4_l5-supply = <&vph>; + vdd_l6_l7-supply = <&vph>; + vdd_l8-supply = <&vph>; + vdd_l9-supply = <&vph>; + vdd_l10-supply = <&vph>; + vdd_l13_l16-supply = <&pm8058_s4>; + vdd_l14_l15-supply = <&vph>; + vdd_l17_l18-supply = <&vph>; + vdd_l19_l20-supply = <&vph>; + vdd_l21-supply = <&pm8058_s3>; + vdd_l22-supply = <&pm8058_s3>; + vdd_l23_l24_l25-supply = <&pm8058_s3>; + vdd_s0-supply = <&vph>; + vdd_s1-supply = <&vph>; + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + vdd_ncp-supply = <&vph>; + + l0 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l4 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l6 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + bias-pull-down; + }; + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3050000>; + bias-pull-down; + }; + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l10 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l11 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + bias-pull-down; + }; + l12 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + bias-pull-down; + }; + l13 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + bias-pull-down; + }; + l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + l15 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + regulator-always-on; + }; + l17 { + // 1.5V according to schematic + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l18 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + bias-pull-down; + }; + l19 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + bias-pull-down; + }; + l20 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l21 { + // 1.1 V according to schematic + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + regulator-always-on; + }; + l22 { + // 1.2 V according to schematic + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + l23 { + // Unused + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l24 { + // Unused + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l25 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + s0 { + // regulator-min-microvolt = <500000>; + // regulator-max-microvolt = <1325000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s1 { + // regulator-min-microvolt = <500000>; + // regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s2 { + // 1.3 V according to schematic + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + regulator-always-on; + bias-pull-down; + }; + s4 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + regulator-always-on; + bias-pull-down; + }; + + /* LVS0 and LVS1 are just switches */ + lvs0 { + bias-pull-down; + }; + lvs1 { + bias-pull-down; + }; + + ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* Internal 3.69 GiB eMMC */ +&sdcc1 { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_sdcc1_pins>; + vmmc-supply = <&pm8901_l5>; + vqmmc-supply = <&pm8901_lvs0>; + status = "okay"; +}; + +/* External micro SD card, directly connected, pulled up to 2.85 V */ +&sdcc3 { + /* Enable SSBI GPIO 22 as input, use for card detect */ + pinctrl-names = "default"; + pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>; + cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm8058_l14>; + status = "okay"; +}; + +/* + * Second external micro SD card, using two TXB104RGYR levelshifters + * to lift from 1.8 V to 2.85 V + */ +&sdcc5 { + /* Enable SSBI GPIO 26 as input, use for card detect */ + pinctrl-names = "default"; + pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>; + cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>; + wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm8058_l14>; + vqmmc-supply = <&dragon_vio_txb>; + status = "okay"; +}; + +&tlmm { + /* eMMC pins, all 8 data lines connected */ + dragon_sdcc1_pins: sdcc1-state { + clk-pins { + pins = "gpio167"; /* SDC1 CLK */ + function = "sdc1"; + drive-strength = <16>; + bias-disable; + }; + cmd-pins { + pins = "gpio168"; /* SDC1 CMD */ + function = "sdc1"; + drive-strength = <10>; + bias-pull-up; + }; + data-pins { + /* SDC1 D0 to D7 */ + pins = "gpio159", "gpio160", "gpio161", "gpio162", + "gpio163", "gpio164", "gpio165", "gpio166"; + function = "sdc1"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + /* + * The SDCC3 pins are hardcoded (non-muxable) but need some pin + * configuration. + */ + dragon_sdcc3_pins: sdcc3-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <8>; + bias-disable; + }; + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + data-pins { + pins = "sdc3_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + /* Second SD card slot pins */ + dragon_sdcc5_pins: sdcc5-state { + clk-pins { + pins = "gpio97"; /* SDC5 CLK */ + function = "sdc5"; + drive-strength = <16>; + bias-disable; + }; + cmd-pins { + pins = "gpio95"; /* SDC5 CMD */ + function = "sdc5"; + drive-strength = <10>; + bias-pull-up; + }; + data-pins { + /* SDC5 D0 to D3 */ + pins = "gpio96", "gpio98", "gpio99", "gpio100"; + function = "sdc5"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + dragon_gsbi3_i2c_pins: gsbi3-i2c-state { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + drive-strength = <8>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; + }; + + dragon_gsbi8_i2c_pins: gsbi8-i2c-state { + pins = "gpio64", "gpio65"; + function = "gsbi8"; + drive-strength = <16>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; + }; + + dragon_gsbi12_i2c_pins: gsbi12-i2c-state { + pins = "gpio115", "gpio116"; + function = "gsbi12"; + drive-strength = <16>; + /* These have external pull-up 4.7kOhm to 1.8V */ + bias-disable; + }; + + /* Primary serial port uart 0 pins */ + dragon_gsbi12_serial_pins: gsbi12-serial-state { + tx-pins { + pins = "gpio117"; + function = "gsbi12"; + drive-strength = <8>; + bias-disable; + }; + rx-pins { + pins = "gpio118"; + function = "gsbi12"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + dragon_ebi2_pins: ebi2-state { + /* + * Pins used by EBI2 on the Dragonboard, actually only + * CS2 is used by a real peripheral. CS0 is just + * routed to a test point. + */ + mux0-pins { + pins = + /* "gpio39", CS1A_N this is not good to mux */ + "gpio40", /* CS2A_N */ + "gpio134"; /* CS0_N testpoint TP29 */ + function = "ebi2cs"; + }; + mux1-pins { + pins = + /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ + "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", + /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ + "gpio135", "gpio136", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", + "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", + "gpio151", /* EBI2_OE_N */ + "gpio153", /* EBI2_ADV */ + "gpio157"; /* EBI2_WE_N */ + function = "ebi2"; + }; + }; + + /* Interrupt line for the KXSD9 accelerometer */ + dragon_kxsd9_gpios: kxsd9-state { + pins = "gpio57"; /* IRQ line */ + function = "gpio"; + bias-pull-up; + }; + + dragon_tma340_gpios: tma340-state { + reset-pins { + /* RESET line, TS_ATTN, WAKE_CTP */ + pins = "gpio58"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + irq-pins { + pins = "gpio61"; /* IRQ line */ + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&xoadc { + /* Reference voltage 2.2 V */ + xoadc-ref-supply = <&pm8058_l18>; + + /* Board-specific channels */ + mpp5@5 { + /* Connected to AOUT of ALS sensor */ + reg = <0x00 0x05>; + }; + mpp6@6 { + /* Connected to test point TP43 */ + reg = <0x00 0x06>; + }; + mpp7@7 { + /* Connected to battery thermistor */ + reg = <0x00 0x07>; + }; + mpp8@8 { + /* Connected to battery ID detector */ + reg = <0x00 0x08>; + }; + mpp9@9 { + /* Connected to XO thermistor */ + reg = <0x00 0x09>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts new file mode 100644 index 000000000000..c57c27cd8a20 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8064-v2.0.dtsi" +#include +#include +#include +/ { + model = "Asus Nexus7(flo)"; + compatible = "asus,nexus7-flo", "qcom,apq8064"; + chassis-type = "tablet"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000 { + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + + ext_3p3v: regulator-ext-3p3v { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ext_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + key-volume-up { + label = "Volume Up"; + gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + key-volume-down { + label = "Volume Down"; + gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + soc { + sram@2a03f000 { + compatible = "qcom,apq8064-imem", "syscon", "simple-mfd"; + reg = <0x2a03f000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; + }; +}; + +&dsi0 { + vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ + vdd-supply = <&pm8921_l8>; + vddio-supply = <&pm8921_lvs7>; + avdd-supply = <&pm8921_l11>; + status = "okay"; + + panel@0 { + reg = <0>; + compatible = "jdi,lt070me05000"; + + vddp-supply = <&pm8921_l17>; + iovcc-supply = <&pm8921_lvs7>; + + enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; + dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_in { + remote-endpoint = <&mdp_dsi1_out>; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ + status = "okay"; +}; + +&gsbi1 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi1_i2c { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + }; + + bq27541@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; + +}; + +&gsbi3 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi3_i2c { + clock-frequency = <200000>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + trackpad@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&gsbi6 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi6_serial { + pinctrl-names = "default"; + pinctrl-0 = <&gsbi6_uart_4pins>; + status = "okay"; +}; + +&gsbi7 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi7_serial { + status = "okay"; +}; + +&mdp { + status = "okay"; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + status = "okay"; +}; + +&mdp_dsi1_out { + remote-endpoint = <&dsi0_in>; +}; + +&rpm { + regulators { + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vin_lvs2-supply = <&pm8921_s1>; + + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + vdd_ncp-supply = <&pm8921_l6>; + + /* Buck SMPS */ + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + /* msm otg HSUSB_VDDCX */ + s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + }; + + /* + * msm_sdcc.1-sdc-vdd_io + * tabla2x-slim-CDC_VDDA_RX + * tabla2x-slim-CDC_VDDA_TX + * tabla2x-slim-CDC_VDD_CP + * tabla2x-slim-VDDIO_CDC + */ + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + regulator-always-on; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + /* mipi_dsi.1-dsi1_pll_vdda */ + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* msm_otg-HSUSB_3p3 */ + l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_1p8 */ + l4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* msm_sdcc.1-sdc_vdd */ + l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + bias-pull-down; + }; + + l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + /* mipi_dsi.1-dsi1_avdd */ + l11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + regulator-always-on; + }; + + /* pwm_power for backlight */ + l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + /* camera, qdsp6 */ + l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * tabla2x-slim-CDC_VDDA_A_1P2V + * tabla2x-slim-VDDD_CDC_D + */ + l25 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + bias-pull-down; + }; + + lvs1 { + bias-pull-down; + }; + + lvs4 { + bias-pull-down; + }; + + lvs5 { + bias-pull-down; + }; + + lvs6 { + bias-pull-down; + }; + /* + * mipi_dsi.1-dsi1_vddio + * pil_riva-pll_vdd + */ + lvs7 { + bias-pull-down; + }; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +/* OTG */ +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts new file mode 100644 index 000000000000..d6ecfd8addb7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8064-v2.0.dtsi" +#include +#include + +/ { + model = "CompuLab CM-QS600"; + compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sdcc4_pwrseq: pwrseq-sdcc4 { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; + }; + + /* on board fixed 3.3v supply */ + v3p3_fixed: regulator-v3p3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE V3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&gsbi1 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi1_i2c { + clock-frequency = <200000>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&gsbi7 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi7_serial { + pinctrl-names = "default"; + pinctrl-0 = <&gsbi7_uart_2pins>; + status = "okay"; +}; + +&pcie { + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&v3p3_fixed>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pm8921_gpio { + wlan_default_gpios: wlan-gpios-state { + pinconf { + pins = "gpio43"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; +}; + +&rpm { + regulators { + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + + /* Buck SMPS */ + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + lvs6 { + bias-pull-down; + }; + + }; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + vmmc-supply = <&v3p3_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* WLAN */ +&sdcc4 { + status = "okay"; + vmmc-supply = <&v3p3_fixed>; + vqmmc-supply = <&v3p3_fixed>; + mmc-pwrseq = <&sdcc4_pwrseq>; +}; + +&tlmm_pinmux { + card_detect: card_detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; + + pcie_pins: pcie_pinmux { + mux { + pins = "gpio27"; + function = "gpio"; + }; + conf { + pins = "gpio27"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb_hs3_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; +}; + +&usb_hs4_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; +}; + +/* OTG */ +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + status = "okay"; +}; + +&usb4 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts new file mode 100644 index 000000000000..96307550523a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8064-v2.0.dtsi" +#include +#include +#include + +/ { + model = "Qualcomm APQ8064/IFC6410"; + compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + i2c0 = &gsbi1_i2c; + i2c1 = &gsbi2_i2c; + i2c2 = &gsbi3_i2c; + i2c3 = &gsbi4_i2c; + spi0 = &gsbi5_spi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <¬ify_led>; + + led-user1 { + label = "apq8064:green:user1"; + color = ; + gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + + sdcc4_pwrseq: pwrseq-sdcc4 { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; + }; + + ext_3p3v: regulator-ext-3p3v { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ext_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&gsbi1 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi1_i2c { + clock-frequency = <200000>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +&gsbi3 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi3_i2c { + status = "okay"; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; +}; + +/* CAM I2C MIPI-CSI connector */ +&gsbi4_i2c { + status = "okay"; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi5_spi { + num-cs = <1>; + cs-gpios = <&tlmm_pinmux 53 0>; + status = "okay"; +}; + +&gsbi6 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi6_serial { + pinctrl-names = "default"; + pinctrl-0 = <&gsbi6_uart_4pins>; + status = "okay"; +}; + +&gsbi7 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi7_serial { + pinctrl-names = "default"; + pinctrl-0 = <&gsbi7_uart_2pins>; + status = "okay"; +}; + +&hdmi { + core-vdda-supply = <&pm8921_hdmi_switch>; + hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi_in { + remote-endpoint = <&mdp_dtv_out>; +}; + +&hdmi_out { + remote-endpoint = <&hdmi_con>; +}; + +&hdmi_phy { + status = "okay"; + core-vdda-supply = <&pm8921_hdmi_switch>; +}; + +&mdp { + status = "okay"; +}; + +&mdp_dtv_out { + remote-endpoint = <&hdmi_in>; +}; + +&pcie { + status = "okay"; + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&ext_3p3v>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; +}; + +&pm8921_gpio { + wlan_default_gpios: wlan-gpios-state { + pinconf { + pins = "gpio43"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + + notify_led: nled-state { + pinconf { + pins = "gpio18"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; +}; + +&rpm { + regulators { + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + + /* Buck SMPS */ + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + lvs1 { + bias-pull-down; + }; + + lvs6 { + bias-pull-down; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata0 { + target-supply = <&pm8921_s4>; + status = "okay"; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + vmmc-supply = <&pm8921_l6>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* WLAN */ +&sdcc4 { + vmmc-supply = <&ext_3p3v>; + vqmmc-supply = <&pm8921_lvs1>; + mmc-pwrseq = <&sdcc4_pwrseq>; + status = "okay"; +}; + +&tlmm_pinmux { + card_detect: card_detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; + + pcie_pins: pcie_pinmux { + mux { + pins = "gpio27"; + function = "gpio"; + }; + conf { + pins = "gpio27"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb_hs3_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; +}; + +&usb_hs4_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; +}; + +/* OTG */ +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + status = "okay"; +}; + +&usb4 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi new file mode 100644 index 000000000000..b4d286a6fab1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 + +&tlmm_pinmux { + sdc4_gpios: sdc4-gpios { + pios { + pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; + function = "sdc4"; + }; + }; + + sdcc1_pins: sdcc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strengh = <16>; + bias-disable; + }; + + cmd { + pins = "sdc1_cmd"; + drive-strengh = <10>; + bias-pull-up; + }; + + data { + pins = "sdc1_data"; + drive-strengh = <10>; + bias-pull-up; + }; + }; + + sdcc3_pins: sdcc3-pin-active { + clk { + pins = "sdc3_clk"; + drive-strengh = <8>; + bias-disable; + }; + + cmd { + pins = "sdc3_cmd"; + drive-strengh = <8>; + bias-pull-up; + }; + + data { + pins = "sdc3_data"; + drive-strengh = <8>; + bias-pull-up; + }; + }; + + ps_hold: ps_hold { + mux { + pins = "gpio78"; + function = "ps_hold"; + }; + }; + + i2c1_pins: i2c1 { + mux { + pins = "gpio20", "gpio21"; + function = "gsbi1"; + }; + + pinconf { + pins = "gpio20", "gpio21"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c1_pins_sleep: i2c1_pins_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + pinconf { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + gsbi1_uart_2pins: gsbi1_uart_2pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi1"; + }; + }; + + gsbi1_uart_4pins: gsbi1_uart_4pins { + mux { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + + i2c2_pins: i2c2 { + mux { + pins = "gpio24", "gpio25"; + function = "gsbi2"; + }; + + pinconf { + pins = "gpio24", "gpio25"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c2_pins_sleep: i2c2_pins_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + pinconf { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c3_pins: i2c3 { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi3"; + }; + + pinconf { + pins = "gpio8", "gpio9"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c3_pins_sleep: i2c3_pins_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + pinconf { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c4_pins: i2c4 { + mux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + }; + + pinconf { + pins = "gpio12", "gpio13"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c4_pins_sleep: i2c4_pins_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + pinconf { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi5_default: spi5_default { + pinmux { + pins = "gpio51", "gpio52", "gpio54"; + function = "gsbi5"; + }; + + pinmux_cs { + function = "gpio"; + pins = "gpio53"; + }; + + pinconf { + pins = "gpio51", "gpio52", "gpio54"; + drive-strength = <16>; + bias-disable; + }; + + pinconf_cs { + pins = "gpio53"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi5_sleep: spi5_sleep { + pinmux { + function = "gpio"; + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + }; + + pinconf { + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + i2c6_pins: i2c6 { + mux { + pins = "gpio16", "gpio17"; + function = "gsbi6"; + }; + + pinconf { + pins = "gpio16", "gpio17"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c6_pins_sleep: i2c6_pins_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + pinconf { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + gsbi6_uart_2pins: gsbi6_uart_2pins { + mux { + pins = "gpio14", "gpio15"; + function = "gsbi6"; + }; + }; + + gsbi6_uart_4pins: gsbi6_uart_4pins { + mux { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "gsbi6"; + }; + }; + + gsbi7_uart_2pins: gsbi7_uart_2pins { + mux { + pins = "gpio82", "gpio83"; + function = "gsbi7"; + }; + }; + + gsbi7_uart_4pins: gsbi7_uart_4pins { + mux { + pins = "gpio82", "gpio83", "gpio84", "gpio85"; + function = "gsbi7"; + }; + }; + + i2c7_pins: i2c7 { + mux { + pins = "gpio84", "gpio85"; + function = "gsbi7"; + }; + + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c7_pins_sleep: i2c7_pins_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + riva_fm_pin_a: riva-fm-active { + pins = "gpio14", "gpio15"; + function = "riva_fm"; + }; + + riva_bt_pin_a: riva-bt-active { + pins = "gpio16", "gpio17"; + function = "riva_bt"; + }; + + riva_wlan_pin_a: riva-wlan-active { + pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; + function = "riva_wlan"; + + drive-strength = <6>; + bias-pull-down; + }; + + hdmi_pinctrl: hdmi-pinctrl { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "hdmi"; + }; + + pinconf_ddc { + pins = "gpio70", "gpio71"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf_hpd { + pins = "gpio72"; + bias-pull-down; + drive-strength = <16>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts new file mode 100644 index 000000000000..9244512b74d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8064-v2.0.dtsi" +#include +#include +#include +#include + +/ { + model = "Sony Xperia Z"; + compatible = "sony,xperia-yuga", "qcom,apq8064"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi5_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi5_serial { + pinctrl-names = "default"; + pinctrl-0 = <&gsbi5_uart_pin_a>; + status = "okay"; +}; + +&pm8921_gpio { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio3", "gpio4", "gpio29", "gpio35"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + input-enable; + power-source = <2>; + qcom,drive-strength = ; + qcom,pull-up-strength = <0>; + }; +}; + +&riva { + pinctrl-names = "default"; + pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; + status = "okay"; +}; + +&rpm { + regulators { + vin_l1_l2_l12_l18-supply = <&pm8921_s4>; + vin_lvs_1_3_6-supply = <&pm8921_s4>; + vin_lvs_4_5_7-supply = <&pm8921_s4>; + vin_ncp-supply = <&pm8921_l6>; + vin_lvs2-supply = <&pm8921_s4>; + vin_l24-supply = <&pm8921_s1>; + vin_l25-supply = <&pm8921_s1>; + vin_l27-supply = <&pm8921_s7>; + vin_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + s8 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + }; + + /* PMOS LDO */ + l1 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + bias-pull-down; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + bias-pull-down; + }; + + l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + l10 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + bias-pull-down; + }; + + l11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + bias-pull-down; + }; + + l17 { + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + bias-pull-down; + }; + + l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + l21 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + l22 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + + l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + l25 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + bias-pull-down; + }; + + l27 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + l28 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + l29 { + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + lvs1 { + bias-pull-down; + }; + + lvs2 { + bias-pull-down; + }; + + lvs3 { + bias-pull-down; + }; + + lvs4 { + bias-pull-down; + }; + + lvs5 { + bias-pull-down; + }; + + lvs6 { + bias-pull-down; + }; + + lvs7 { + bias-pull-down; + }; + + usb-switch {}; + + hdmi-switch {}; + + ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + status = "okay"; +}; + +&sdcc3 { + vmmc-supply = <&pm8921_l6>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; + + status = "okay"; +}; + +&tlmm_pinmux { + gsbi5_uart_pin_a: gsbi5-uart-pin-active { + rx { + pins = "gpio52"; + function = "gsbi5"; + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio51"; + function = "gsbi5"; + drive-strength = <4>; + bias-disable; + }; + }; + + + sdcc3_cd_pin_a: sdcc3-cd-pin-active { + pins = "gpio26"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi new file mode 100644 index 000000000000..46ed48f0244f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi new file mode 100644 index 000000000000..672b246afbba --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -0,0 +1,1895 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm APQ8064"; + compatible = "qcom,apq8064"; + interrupt-parent = <&intc>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_region: smem@80000000 { + reg = <0x80000000 0x200000>; + no-map; + }; + + wcnss_mem: wcnss@8f000000 { + reg = <0x8f000000 0x700000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU1: cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU2: cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU3: cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + coefficients = <1199 0>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + coefficients = <1132 0>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + coefficients = <1199 0>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + coefficients = <1132 0>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + }; + + clocks { + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + sfpb_mutex: hwmutex { + compatible = "qcom,sfpb-mutex"; + syscon = <&sfpb_wrapper_mutex 0x604 0x4>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + + hwlocks = <&sfpb_mutex 3>; + }; + + smd { + compatible = "qcom,smd"; + + modem-edge { + interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 3>; + qcom,smd-edge = <0>; + + status = "disabled"; + }; + + q6-edge { + interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 15>; + qcom,smd-edge = <1>; + + status = "disabled"; + }; + + dsps-edge { + interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&sps_sic_non_secure 0x4080 0>; + qcom,smd-edge = <3>; + + status = "disabled"; + }; + + riva-edge { + interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 25>; + qcom,smd-edge = <6>; + + status = "disabled"; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&l2cc 8 4>; + qcom,ipc-2 = <&l2cc 8 14>; + qcom,ipc-3 = <&l2cc 8 23>; + qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + q6_smsm: q6@2 { + reg = <2>; + interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@3 { + reg = <3>; + interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + dsps_smsm: dsps@4 { + reg = <4>; + interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-apq8064", "qcom,scm"; + + clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; + clock-names = "core"; + }; + }; + + + /* + * These channels from the ADC are simply hardware monitors. + * That is why the ADC is referred to as "HKADC" - HouseKeeping + * ADC. + */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xoadc 0x00 0x01>, /* Battery */ + <&xoadc 0x00 0x02>, /* DC in (charger) */ + <&xoadc 0x00 0x04>, /* VPH the main system voltage */ + <&xoadc 0x00 0x0b>, /* Die temperature */ + <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ + <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ + <&xoadc 0x00 0x0e>; /* Charger temperature */ + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + tlmm_pinmux: pinctrl@800000 { + compatible = "qcom,apq8064-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + gpio-ranges = <&tlmm_pinmux 0 0 90>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&ps_hold>; + }; + + sfpb_wrapper_mutex: syscon@1200000 { + compatible = "syscon"; + reg = <0x01200000 0x8000>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", + "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; + }; + + acc2: clock-controller@20a8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu2_aux"; + #clock-cells = <0>; + }; + + acc3: clock-controller@20b8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu3_aux"; + #clock-cells = <0>; + }; + + saw0: power-controller@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: power-controller@2099000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw2: power-controller@20a9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw3: power-controller@20b9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + sps_sic_non_secure: sps-sic-non-secure@12100000 { + compatible = "syscon"; + reg = <0x12100000 0x10000>; + }; + + gsbi1: gsbi@12440000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <1>; + reg = <0x12440000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi1_i2c: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x12460000 0x1000>; + interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + }; + + gsbi2: gsbi@12480000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi2_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_pins_sleep>; + pinctrl-names = "default", "sleep"; + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&i2c3_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16280000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI3_QUP_CLK>, + <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi4: gsbi@16300000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x03>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi4_i2c: i2c@16380000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16380000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI4_QUP_CLK>, + <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi@1a200000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x1a200000 0x03>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi5_serial: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x100>, + <0x1a200000 0x03>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_spi: spi@1a280000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; + pinctrl-names = "default", "sleep"; + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi6: gsbi@16500000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <6>; + reg = <0x16500000 0x03>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi6_serial: serial@16540000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16540000 0x100>, + <0x16500000 0x03>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c6_pins>; + pinctrl-1 = <&i2c6_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16580000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI6_QUP_CLK>, + <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c7_pins>; + pinctrl-1 = <&i2c7_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16680000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + ssbi@c00000 { + compatible = "qcom,ssbi"; + reg = <0x00c00000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pm8821: pmic { + compatible = "qcom,pm8821"; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <76 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pm8821_mpps: mpps@50 { + compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; + reg = <0x50>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8821_mpps 0 0 4>; + }; + }; + }; + + ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic { + compatible = "qcom,pm8921"; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <74 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pm8921_gpio: gpio@150 { + + compatible = "qcom,pm8921-gpio", + "qcom,ssbi-gpio"; + reg = <0x150>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + gpio-ranges = <&pm8921_gpio 0 0 44>; + #gpio-cells = <2>; + + }; + + pm8921_mpps: mpps@50 { + compatible = "qcom,pm8921-mpp", + "qcom,ssbi-mpp"; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8921_mpps 0 0 12>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rtc@11d { + compatible = "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 1>; + reg = <0x11d>; + allow-set-time; + }; + + pwrkey@1c { + compatible = "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 1>, <51 1>; + debounce = <15625>; + pull-up; + }; + + xoadc: xoadc@197 { + compatible = "qcom,pm8921-adc"; + reg = <197>; + interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; + #address-cells = <2>; + #size-cells = <0>; + #io-channel-cells = <2>; + + vcoin: adc-channel@0 { + reg = <0x00 0x00>; + }; + vbat: adc-channel@1 { + reg = <0x00 0x01>; + }; + dcin: adc-channel@2 { + reg = <0x00 0x02>; + }; + vph_pwr: adc-channel@4 { + reg = <0x00 0x04>; + }; + batt_therm: adc-channel@8 { + reg = <0x00 0x08>; + }; + batt_id: adc-channel@9 { + reg = <0x00 0x09>; + }; + usb_vbus: adc-channel@a { + reg = <0x00 0x0a>; + }; + die_temp: adc-channel@b { + reg = <0x00 0x0b>; + }; + ref_625mv: adc-channel@c { + reg = <0x00 0x0c>; + }; + ref_1250mv: adc-channel@d { + reg = <0x00 0x0d>; + }; + chg_temp: adc-channel@e { + reg = <0x00 0x0e>; + }; + ref_muxoff: adc-channel@f { + reg = <0x00 0x0f>; + }; + }; + }; + }; + + qfprom: qfprom@700000 { + compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + tsens_calib: calib@404 { + reg = <0x404 0x10>; + }; + tsens_backup: backup_calib@414 { + reg = <0x414 0x10>; + }; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-apq8064", "syscon"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-apq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + + mmcc: clock-controller@4000000 { + compatible = "qcom,mmcc-apq8064"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <&hdmi_phy>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; + + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + + pm8921_s1: s1 {}; + pm8921_s2: s2 {}; + pm8921_s3: s3 {}; + pm8921_s4: s4 {}; + pm8921_s7: s7 {}; + pm8921_s8: s8 {}; + + pm8921_l1: l1 {}; + pm8921_l2: l2 {}; + pm8921_l3: l3 {}; + pm8921_l4: l4 {}; + pm8921_l5: l5 {}; + pm8921_l6: l6 {}; + pm8921_l7: l7 {}; + pm8921_l8: l8 {}; + pm8921_l9: l9 {}; + pm8921_l10: l10 {}; + pm8921_l11: l11 {}; + pm8921_l12: l12 {}; + pm8921_l14: l14 {}; + pm8921_l15: l15 {}; + pm8921_l16: l16 {}; + pm8921_l17: l17 {}; + pm8921_l18: l18 {}; + pm8921_l21: l21 {}; + pm8921_l22: l22 {}; + pm8921_l23: l23 {}; + pm8921_l24: l24 {}; + pm8921_l25: l25 {}; + pm8921_l26: l26 {}; + pm8921_l27: l27 {}; + pm8921_l28: l28 {}; + pm8921_l29: l29 {}; + + pm8921_lvs1: lvs1 {}; + pm8921_lvs2: lvs2 {}; + pm8921_lvs3: lvs3 {}; + pm8921_lvs4: lvs4 {}; + pm8921_lvs5: lvs5 {}; + pm8921_lvs6: lvs6 {}; + pm8921_lvs7: lvs7 {}; + + pm8921_usb_switch: usb-switch {}; + + pm8921_hdmi_switch: hdmi-switch { + bias-pull-down; + }; + + pm8921_ncp: ncp {}; + }; + }; + + usb1: usb@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-apq8064", + "qcom,usb-hs-phy"; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + #phy-cells = <0>; + }; + }; + }; + + usb3: usb@12520000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12520000 0x200>, + <0x12520200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS3_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs3_phy>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs3_phy: phy { + compatible = "qcom,usb-hs-phy-apq8064", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb3 0>; + reset-names = "por"; + }; + }; + }; + + usb4: usb@12530000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12530000 0x200>, + <0x12530200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS4_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs4_phy>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs4_phy: phy { + compatible = "qcom,usb-hs-phy-apq8064", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb4 0>; + reset-names = "por"; + }; + }; + }; + + sata_phy0: phy@1b400000 { + compatible = "qcom,apq8064-sata-phy"; + status = "disabled"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; + }; + + sata0: sata@29000000 { + compatible = "qcom,apq8064-ahci", "generic-ahci"; + status = "disabled"; + reg = <0x29000000 0x180>; + interrupts = ; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", + "iface", + "bus", + "rxoob", + "core_pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + }; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc4: mmc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = ; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&sdc4_gpios>; + }; + + sdcc4bam: dma-controller@121c2000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x121c2000 0x8000>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC4_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + pinctrl-names = "default"; + pinctrl-0 = <&sdcc1_pins>; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-apq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + + gpu: adreno-3xx@4300000 { + compatible = "qcom,adreno-320.2", "qcom,adreno"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core", + "iface", + "mem", + "mem_iface"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + + iommus = <&gfx3d 0 + &gfx3d 1 + &gfx3d 2 + &gfx3d 3 + &gfx3d 4 + &gfx3d 5 + &gfx3d 6 + &gfx3d 7 + &gfx3d 8 + &gfx3d 9 + &gfx3d 10 + &gfx3d 11 + &gfx3d 12 + &gfx3d 13 + &gfx3d 14 + &gfx3d 15 + &gfx3d 16 + &gfx3d 17 + &gfx3d 18 + &gfx3d 19 + &gfx3d 20 + &gfx3d 21 + &gfx3d 22 + &gfx3d 23 + &gfx3d 24 + &gfx3d 25 + &gfx3d 26 + &gfx3d 27 + &gfx3d 28 + &gfx3d 29 + &gfx3d 30 + &gfx3d 31 + &gfx3d1 0 + &gfx3d1 1 + &gfx3d1 2 + &gfx3d1 3 + &gfx3d1 4 + &gfx3d1 5 + &gfx3d1 6 + &gfx3d1 7 + &gfx3d1 8 + &gfx3d1 9 + &gfx3d1 10 + &gfx3d1 11 + &gfx3d1 12 + &gfx3d1 13 + &gfx3d1 14 + &gfx3d1 15 + &gfx3d1 16 + &gfx3d1 17 + &gfx3d1 18 + &gfx3d1 19 + &gfx3d1 20 + &gfx3d1 21 + &gfx3d1 22 + &gfx3d1 23 + &gfx3d1 24 + &gfx3d1 25 + &gfx3d1 26 + &gfx3d1 27 + &gfx3d1 28 + &gfx3d1 29 + &gfx3d1 30 + &gfx3d1 31>; + + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + }; + + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; + }; + }; + }; + + mmss_sfpb: syscon@5700000 { + compatible = "syscon"; + reg = <0x5700000 0x70>; + }; + + dsi0: dsi@4700000 { + compatible = "qcom,apq8064-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x04700000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI_M_AHB_CLK>, + <&mmcc DSI_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI_CLK>, + <&mmcc DSI1_BYTE_CLK>, + <&mmcc DSI_PIXEL_CLK>, + <&mmcc DSI1_ESC_CLK>; + clock-names = "iface", "bus", "core_mmss", + "src", "byte", "pixel", + "core"; + + assigned-clocks = <&mmcc DSI1_BYTE_SRC>, + <&mmcc DSI1_ESC_SRC>, + <&mmcc DSI_SRC>, + <&mmcc DSI_PIXEL_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi0_phy 1>; + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi0_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + + dsi0_phy: phy@4700200 { + compatible = "qcom,dsi-phy-28nm-8960"; + #clock-cells = <1>; + #phy-cells = <0>; + + reg = <0x04700200 0x100>, + <0x04700300 0x200>, + <0x04700500 0x5c>; + reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; + clock-names = "iface", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, + <&pxo_board>; + status = "disabled"; + }; + + dsi1: dsi@5800000 { + compatible = "qcom,mdss-dsi-ctrl"; + interrupts = ; + reg = <0x05800000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&mmcc DSI2_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI2_CLK>, + <&mmcc DSI2_BYTE_CLK>, + <&mmcc DSI2_PIXEL_CLK>, + <&mmcc DSI2_ESC_CLK>; + clock-names = "iface", + "bus", + "core_mmss", + "src", + "byte", + "pixel", + "core"; + + assigned-clocks = <&mmcc DSI2_BYTE_SRC>, + <&mmcc DSI2_ESC_SRC>, + <&mmcc DSI2_SRC>, + <&mmcc DSI2_PIXEL_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 1>; + + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + + dsi1_phy: dsi-phy@5800200 { + compatible = "qcom,dsi-phy-28nm-8960"; + reg = <0x05800200 0x100>, + <0x05800300 0x200>, + <0x05800500 0x5c>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + clock-names = "iface", + "ref"; + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&pxo_board>; + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdp_port0: iommu@7500000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07500000 0x100000>; + interrupts = + , + ; + qcom,ncb = <2>; + }; + + mdp_port1: iommu@7600000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07600000 0x100000>; + interrupts = + , + ; + qcom,ncb = <2>; + }; + + gfx3d: iommu@7c00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07c00000 0x100000>; + interrupts = + , + ; + qcom,ncb = <3>; + }; + + gfx3d1: iommu@7d00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07d00000 0x100000>; + interrupts = + , + ; + qcom,ncb = <3>; + }; + + pcie: pci@1b500000 { + compatible = "qcom,pcie-apq8064"; + reg = <0x1b500000 0x1000>, + <0x1b502000 0x80>, + <0x1b600000 0x100>, + <0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ + <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_REF_CLK>; + clock-names = "core", "iface", "phy"; + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy"; + status = "disabled"; + }; + + hdmi: hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + reg = <0x04a00000 0x2f0>; + reg-names = "core_physical"; + interrupts = ; + clocks = <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + clock-names = "core", + "master_iface", + "slave_iface"; + + phys = <&hdmi_phy>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + hdmi_out: endpoint { + }; + }; + }; + }; + + hdmi_phy: phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + reg-names = "hdmi_phy", + "hdmi_pll"; + + clocks = <&mmcc HDMI_S_AHB_CLK>; + clock-names = "slave_iface"; + #phy-cells = <0>; + #clock-cells = <0>; + + status = "disabled"; + }; + + mdp: display-controller@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = ; + clocks = <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + clock-names = "core_clk", + "iface_clk", + "bus_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + + iommus = <&mdp_port0 0 + &mdp_port0 2 + &mdp_port1 0 + &mdp_port1 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp_lvds_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + mdp_dsi1_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + mdp_dsi2_out: endpoint { + }; + }; + + port@3 { + reg = <3>; + mdp_dtv_out: endpoint { + }; + }; + }; + }; + + riva: riva-pil@3200800 { + compatible = "qcom,riva-pil"; + + reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; + reg-names = "ccu", "dxe", "pmu"; + + interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal"; + + memory-region = <&wcnss_mem>; + + vddcx-supply = <&pm8921_s3>; + vddmx-supply = <&pm8921_l24>; + vddpx-supply = <&pm8921_s4>; + + status = "disabled"; + + iris { + compatible = "qcom,wcn3660"; + + clocks = <&cxo_board>; + clock-names = "xo"; + + vddxo-supply = <&pm8921_l4>; + vddrfa-supply = <&pm8921_s2>; + vddpa-supply = <&pm8921_l10>; + vdddig-supply = <&pm8921_lvs2>; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&l2cc 8 25>; + qcom,smd-edge = <6>; + + label = "riva"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&riva>; + + bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; + }; + + etb@1a01000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x1a01000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; + }; + + tpiu@1a03000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x1a03000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&funnel_out>; + }; + }; + }; + }; + + funnel@1a04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x1a04000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 2 - connected to STM component + * 3 - not-connected + * 6 - not-connected + * 7 - not-connected + */ + port@0 { + reg = <0>; + funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + port@4 { + reg = <4>; + funnel_in4: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + port@5 { + reg = <5>; + funnel_in5: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + funnel_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etm@1a1c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1c000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_in0>; + }; + }; + }; + }; + + etm@1a1d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1d000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_in1>; + }; + }; + }; + }; + + etm@1a1e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1e000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_in4>; + }; + }; + }; + }; + + etm@1a1f000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1f000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_in5>; + }; + }; + }; + }; + }; +}; +#include "qcom-apq8064-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts new file mode 100644 index 000000000000..e0679436000b --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" + +/delete-node/ &mpss_region; + +/ { + model = "Qualcomm APQ8074 Dragonboard"; + compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; + + aliases { + serial0 = &blsp1_uart2; + usid0 = &pm8941_0; + usid4 = &pm8841_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-0 = <&msm_keys_default>; + pinctrl-names = "default"; + + button-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + }; + + button-general { + label = "General"; + linux,code = ; + gpios = <&pm8941_gpios 23 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + mpss_region: mpss@ac00000 { + reg = <0x0ac00000 0x2500000>; + no-map; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + qcom,controlled-remotely; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <200000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + read-only; + }; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + + status = "okay"; + + panel: panel@0 { + compatible = "sharp,ls043t1le01-qhd"; + reg = <0>; + + avdd-supply = <&pm8941_l22>; + backlight = <&pm8941_wled>; + reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + + vddio-supply = <&pm8941_l12>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm8941_gpios { + msm_keys_default: pm8941-gpio-keys-state { + pins = "gpio5", "gpio23"; + function = "normal"; + input-enable; + drive-push-pull; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; /* 1.8V */ + }; +}; + +&pm8941_lpg { + qcom,power-source = <1>; + status = "okay"; + + led@5 { + reg = <5>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led@6 { + reg = <6>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led@7 { + reg = <7>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; +}; + +&pm8941_wled { + qcom,cs-out; + qcom,switching-freq = <3200>; + qcom,ovp = <32>; + qcom,num-strings = <1>; + + status = "okay"; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + + firmware-name = "qcom/apq8074/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + + firmware-name = "qcom/apq8074/mba.mbn", "qcom/apq8074/modem.mbn"; + + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vin_5vs-supply = <&pm8941_5v>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&tlmm { + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + + cd-pins { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs2_phy>; + phy-select = <&tcsr 0xb000 1>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs2_phy { + status = "okay"; + v3p3-supply = <&pm8941_l24>; + v1p8-supply = <&pm8941_l6>; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x63>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts new file mode 100644 index 000000000000..116e59a3b76d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8084.dtsi" +#include "qcom-pma8084.dtsi" + +/ { + model = "Qualcomm APQ8084/IFC6540"; + compatible = "qcom,apq8084-sbc", "qcom,apq8084"; + + aliases { + serial0 = &blsp2_uart2; + usid0 = &pma8084_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f995e000 { + status = "okay"; + }; + }; +}; + +&sdhc_1 { + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts new file mode 100644 index 000000000000..c6b6680248a6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-apq8084.dtsi" +#include "qcom-pma8084.dtsi" + +/ { + model = "Qualcomm APQ 8084-MTP"; + compatible = "qcom,apq8084-mtp", "qcom,apq8084"; + + aliases { + serial0 = &blsp2_uart2; + usid0 = &pma8084_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f995e000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi new file mode 100644 index 000000000000..207124d68128 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -0,0 +1,852 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm APQ 8084"; + compatible = "qcom,apq8084"; + interrupt-parent = <&intc>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_mem: smem_region@fa00000 { + reg = <0xfa00000 0x200000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <1>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <2>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <3>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + qcom,saw = <&saw_l2>; + }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + firmware { + scm { + compatible = "qcom,scm-apq8084", "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + smem { + compatible = "qcom,smem"; + + qcom,rpm-msg-ram = <&rpm_msg_ram>; + memory-region = <&smem_mem>; + + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + apcs: syscon@f9011000 { + compatible = "syscon"; + reg = <0xf9011000 0x1000>; + }; + + sram@fc190000 { + compatible = "qcom,apq8084-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + + qfprom: qfprom@fc4bc000 { + compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; + }; + }; + + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; + #qcom,sensors = <11>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { + compatible = "qcom,saw2"; + reg = <0xf9012000 0x1000>; + regulator; + }; + + acc0: power-manager@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc1: power-manager@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc2: power-manager@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc3: power-manager@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, + <0xf9008000 0x1000>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-apq8084"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x4000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, /* ufs */ + <0>, + <0>, + <0>, + <0>, /* sata */ + <0>, + <0>; /* pcie */ + clock-names = "xo", + "sleep_clk", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src", + "ufs_tx_symbol_1_clk_src", + "sata_asic0_clk", + "sata_rx_clk", + "pcie_pipe"; + }; + + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: sram@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,apq8084-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 147>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + blsp2_uart2: serial@f995e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995e000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhc_1: mmc@f9824900 { + compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc", "core"; + interrupts = , ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + sdhc_2: mmc@f98a4900 { + compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc", "core"; + interrupts = , ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm-requests { + compatible = "qcom,rpm-apq8084"; + qcom,smd-channels = "rpm_requests"; + + regulators-0 { + compatible = "qcom,rpm-pma8084-regulators"; + + pma8084_s1: s1 {}; + pma8084_s2: s2 {}; + pma8084_s3: s3 {}; + pma8084_s4: s4 {}; + pma8084_s5: s5 {}; + pma8084_s6: s6 {}; + pma8084_s7: s7 {}; + pma8084_s8: s8 {}; + pma8084_s9: s9 {}; + pma8084_s10: s10 {}; + pma8084_s11: s11 {}; + pma8084_s12: s12 {}; + + pma8084_l1: l1 {}; + pma8084_l2: l2 {}; + pma8084_l3: l3 {}; + pma8084_l4: l4 {}; + pma8084_l5: l5 {}; + pma8084_l6: l6 {}; + pma8084_l7: l7 {}; + pma8084_l8: l8 {}; + pma8084_l9: l9 {}; + pma8084_l10: l10 {}; + pma8084_l11: l11 {}; + pma8084_l12: l12 {}; + pma8084_l13: l13 {}; + pma8084_l14: l14 {}; + pma8084_l15: l15 {}; + pma8084_l16: l16 {}; + pma8084_l17: l17 {}; + pma8084_l18: l18 {}; + pma8084_l19: l19 {}; + pma8084_l20: l20 {}; + pma8084_l21: l21 {}; + pma8084_l22: l22 {}; + pma8084_l23: l23 {}; + pma8084_l24: l24 {}; + pma8084_l25: l25 {}; + pma8084_l26: l26 {}; + pma8084_l27: l27 {}; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts new file mode 100644 index 000000000000..1b27edce9d4f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include "qcom-ipq4018-ap120c-ac.dtsi" + +/ { + model = "ALFA Network AP120C-AC Bit"; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "ap120c-ac:green:power"; + function = LED_FUNCTION_POWER; + color = ; + gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-wlan { + label = "ap120c-ac:green:wlan"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + }; + + led-support { + label = "ap120c-ac:green:support"; + color = ; + gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts new file mode 100644 index 000000000000..a707057c887d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include "qcom-ipq4018-ap120c-ac.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + status: led-status { + label = "ap120c-ac:blue:status"; + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + led-wlan2g { + label = "ap120c-ac:green:wlan2g"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + led-wlan5g { + label = "ap120c-ac:red:wlan5g"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi new file mode 100644 index 000000000000..d90b4f4c63af --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq4019.dtsi" +#include +#include + +/ { + model = "ALFA Network AP120C-AC"; + compatible = "alfa-network,ap120c-ac", "qcom,ipq4018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&tlmm { + i2c0_pins: i2c0_pinmux { + mux_i2c { + function = "blsp_i2c0"; + pins = "gpio58", "gpio59"; + drive-strength = <16>; + bias-disable; + }; + }; + + mdio_pins: mdio_pinmux { + mux_mdio { + pins = "gpio53"; + function = "mdio"; + bias-pull-up; + }; + + mux_mdc { + pins = "gpio52"; + function = "mdc"; + bias-pull-up; + }; + }; + + serial0_pins: serial0_pinmux { + mux_uart { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi0_pins: spi0_pinmux { + mux_spi { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; + }; + + mux_cs { + function = "gpio"; + pins = "gpio54", "gpio4"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + usb-power-hog { + line-name = "USB-power"; + gpios = <1 GPIO_ACTIVE_HIGH>; + gpio-hog; + output-high; + }; +}; + +&watchdog { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_i2c3 { + status = "okay"; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + tpm@29 { + compatible = "atmel,at97sc3204t"; + reg = <0x29>; + }; +}; + +&blsp1_spi1 { + status = "okay"; + + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x00000000 0x00040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x00040000 0x00020000>; + read-only; + }; + + partition@60000 { + label = "QSEE"; + reg = <0x00060000 0x00060000>; + read-only; + }; + + partition@c0000 { + label = "CDT"; + reg = <0x000c0000 0x00010000>; + read-only; + }; + + partition@d0000 { + label = "DDRPARAMS"; + reg = <0x000d0000 0x00010000>; + read-only; + }; + + partition@e0000 { + label = "u-boot-env"; + reg = <0x000e0000 0x00010000>; + }; + + partition@f0000 { + label = "u-boot"; + reg = <0x000f0000 0x00080000>; + read-only; + }; + + partition@170000 { + label = "ART"; + reg = <0x00170000 0x00010000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + partition@180000 { + label = "priv_data1"; + reg = <0x00180000 0x00010000>; + read-only; + }; + + partition@190000 { + label = "priv_data2"; + reg = <0x00190000 0x00010000>; + read-only; + }; + }; + }; + + flash@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x04000000>; + }; + + partition@4000000 { + label = "ubi2"; + reg = <0x04000000 0x04000000>; + }; + }; + }; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial0_pins>; + pinctrl-names = "default"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +}; + +&wifi0 { + status = "okay"; + nvmem-cell-names = "pre-calibration"; + nvmem-cells = <&precal_art_1000>; +}; + +&wifi1 { + status = "okay"; + nvmem-cell-names = "pre-calibration"; + nvmem-cells = <&precal_art_5000>; + qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; + + dwc3@8a00000 { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; + }; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts new file mode 100644 index 000000000000..365fbac417fd --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +// Copyright (c) 2018, Robert Marko + +#include "qcom-ipq4019.dtsi" +#include +#include + +/ { + model = "8devices Jalapeno"; + compatible = "8dev,jalapeno", "qcom,ipq4018"; +}; + +&tlmm { + mdio_pins: mdio_pinmux { + pinmux_1 { + pins = "gpio53"; + function = "mdio"; + }; + + pinmux_2 { + pins = "gpio52"; + function = "mdc"; + }; + + pinconf { + pins = "gpio52", "gpio53"; + bias-pull-up; + }; + }; + + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + pin { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + + pin_cs { + function = "gpio"; + pins = "gpio54", "gpio59"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_spi1 { + status = "okay"; + + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>; + + flash@0 { + status = "okay"; + + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x00000000 0x00040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x00040000 0x00020000>; + read-only; + }; + + partition@60000 { + label = "QSEE"; + reg = <0x00060000 0x00060000>; + read-only; + }; + + partition@c0000 { + label = "CDT"; + reg = <0x000c0000 0x00010000>; + read-only; + }; + + partition@d0000 { + label = "DDRPARAMS"; + reg = <0x000d0000 0x00010000>; + read-only; + }; + + partition@e0000 { + label = "u-boot-env"; + reg = <0x000e0000 0x00010000>; + }; + + partition@f0000 { + label = "u-boot"; + reg = <0x000f0000 0x00080000>; + read-only; + }; + + partition@170000 { + label = "ART"; + reg = <0x00170000 0x00010000>; + read-only; + }; + }; + }; + + spi-nand@1 { + status = "okay"; + + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x04000000>; + }; + + partition@4000000 { + label = "ubi2"; + reg = <0x04000000 0x04000000>; + }; + }; + }; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +}; + +&wifi0 { + status = "okay"; + + qcom,ath10k-calibration-variant = "8devices-Jalapeno"; +}; + +&wifi1 { + status = "okay"; + + qcom,ath10k-calibration-variant = "8devices-Jalapeno"; +}; + +&usb3_ss_phy { + status = "okay"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts new file mode 100644 index 000000000000..ddaa273f72ca --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "qcom-ipq4019-ap.dk01.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; + compatible = "qcom,ipq4019-ap-dk01.1-c1", "qcom,ipq4019"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi new file mode 100644 index 000000000000..0505270cf508 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi @@ -0,0 +1,113 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include "qcom-ipq4019.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + rng@22000 { + status = "okay"; + }; + + pinctrl@1000000 { + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio54"; + }; + pinconf { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio54"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + blsp_dma: dma-controller@7884000 { + status = "okay"; + }; + + spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + + mx25l25635e@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "mx25l25635e"; + spi-max-frequency = <24000000>; + }; + }; + + serial@78af000 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + cryptobam: dma-controller@8e04000 { + status = "okay"; + }; + + crypto@8e3a000 { + status = "okay"; + }; + + watchdog@b017000 { + status = "okay"; + }; + + wifi@a000000 { + status = "okay"; + }; + + wifi@a800000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts new file mode 100644 index 000000000000..0993f840d1fc --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019-ap.dk04.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1"; + compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019"; + + soc { + dma-controller@7984000 { + status = "okay"; + }; + }; +}; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts new file mode 100644 index 000000000000..7765247125e4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019-ap.dk04.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3"; + compatible = "qcom,ipq4019-ap-dk04.1-c3", "qcom,ipq4019"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi new file mode 100644 index 000000000000..468ebc40d2ad --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019.dtsi" +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1"; + + aliases { + serial0 = &blsp1_uart1; + serial1 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256MB */ + }; + + soc { + pinctrl@1000000 { + serial_0_pins: serial0-pinmux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + + serial_1_pins: serial1-pinmux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_uart1"; + bias-disable; + }; + + spi_0_pins: spi-0-pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + bias-disable; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio12"; + bias-disable; + output-high; + }; + }; + + i2c_0_pins: i2c-0-pinmux { + pins = "gpio20", "gpio21"; + function = "blsp_i2c0"; + bias-disable; + }; + + nand_pins: nand-pins { + pins = "gpio53", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", + "gpio60", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68", "gpio69"; + function = "qpic"; + }; + }; + + serial@78af000 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + dma-controller@7884000 { + status = "okay"; + }; + + spi@78b5000 { /* BLSP1 QUP1 */ + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <24000000>; + }; + }; + + pci@40000000 { + status = "okay"; + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts new file mode 100644 index 000000000000..ea2987fcbff8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include +#include "qcom-ipq4019-ap.dk07.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1"; + compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019"; + + soc { + pci@40000000 { + status = "okay"; + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + }; + + spi@78b6000 { + status = "okay"; + }; + + pinctrl@1000000 { + serial_1_pins: serial1-pinmux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_uart1"; + bias-disable; + }; + + spi_0_pins: spi-0-pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + bias-disable; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio12"; + bias-disable; + output-high; + }; + }; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <24000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts new file mode 100644 index 000000000000..bd3553dd2070 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019-ap.dk07.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2"; + compatible = "qcom,ipq4019-ap-dk07.1-c2", "qcom,ipq4019"; + + soc { + pinctrl@1000000 { + serial_1_pins: serial1-pinmux { + pins = "gpio8", "gpio9"; + function = "blsp_uart1"; + bias-disable; + }; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi new file mode 100644 index 000000000000..7ef635997efa --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019.dtsi" +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MB */ + }; + + aliases { + serial0 = &blsp1_uart1; + serial1 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + pinctrl@1000000 { + serial_0_pins: serial0-pinmux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + + i2c_0_pins: i2c-0-pinmux { + pins = "gpio20", "gpio21"; + function = "blsp_i2c0"; + bias-disable; + }; + + nand_pins: nand-pins { + pins = "gpio53", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", + "gpio60", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68", "gpio69"; + function = "qpic"; + }; + }; + + serial@78af000 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + dma-controller@7884000 { + status = "okay"; + }; + + i2c@78b7000 { /* BLSP1 QUP2 */ + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + dma-controller@7984000 { + status = "okay"; + }; + }; +}; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi new file mode 100644 index 000000000000..dfcfb3339c23 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -0,0 +1,697 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Qualcomm Technologies, Inc. IPQ4019"; + compatible = "qcom,ipq4019"; + interrupt-parent = <&intc>; + + reserved-memory { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + smem_region: smem@87e00000 { + reg = <0x87e00000 0x080000>; + no-map; + }; + + tz@87e80000 { + reg = <0x87e80000 0x180000>; + no-map; + }; + }; + + aliases { + spi0 = &blsp1_spi1; + spi1 = &blsp1_spi2; + i2c0 = &blsp1_i2c3; + i2c1 = &blsp1_i2c4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + reg = <0x0>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + reg = <0x1>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + reg = <0x2>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + reg = <0x3>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + qcom,saw = <&saw_l2>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-48000000 { + opp-hz = /bits/ 64 <48000000>; + clock-latency-ns = <256000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <256000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <256000>; + }; + opp-716000000 { + opp-hz = /bits/ 64 <716000000>; + clock-latency-ns = <256000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq4019", "qcom,scm"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <48000000>; + always-on; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq4019"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x1800000 0x60000>; + clocks = <&xo>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; + }; + + prng: rng@22000 { + compatible = "qcom,prng"; + reg = <0x22000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + status = "disabled"; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x01000000 0x300000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 100>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + vqmmc: regulator@1948000 { + compatible = "qcom,vqmmc-ipq4019-regulator"; + reg = <0x01948000 0x4>; + regulator-name = "vqmmc"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + status = "disabled"; + }; + + sdhci: mmc@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names = "hc", "core"; + interrupts = , ; + interrupt-names = "hc_irq", "pwr_irq"; + bus-width = <8>; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_DCD_XO_CLK>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b8000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + cryptobam: dma-controller@8e04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x08e04000 0x20000>; + interrupts = ; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + status = "disabled"; + }; + + crypto: crypto@8e3a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x08e3a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + acc0: power-manager@b088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; + }; + + acc1: power-manager@b098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; + }; + + acc2: power-manager@b0a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; + }; + + acc3: power-manager@b0b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; + }; + + saw0: regulator@b089000 { + compatible = "qcom,saw2"; + reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw1: regulator@b099000 { + compatible = "qcom,saw2"; + reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw2: regulator@b0a9000 { + compatible = "qcom,saw2"; + reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw3: regulator@b0b9000 { + compatible = "qcom,saw2"; + reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw_l2: regulator@b012000 { + compatible = "qcom,saw2"; + reg = <0xb012000 0x1000>; + regulator; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = ; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = ; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + }; + + watchdog: watchdog@b017000 { + compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; + reg = <0xb017000 0x40>; + clocks = <&sleep_clk>; + timeout-sec = <10>; + status = "disabled"; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + + pcie0: pci@40000000 { + compatible = "qcom,pcie-ipq4019"; + reg = <0x40000000 0xf1d + 0x40000f20 0xa8 + 0x80000 0x2000 + 0x40100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_AHB_CLK>, + <&gcc GCC_PCIE_AXI_M_CLK>, + <&gcc GCC_PCIE_AXI_S_CLK>; + clock-names = "aux", + "master_bus", + "slave_bus"; + + resets = <&gcc PCIE_AXI_M_ARES>, + <&gcc PCIE_AXI_S_ARES>, + <&gcc PCIE_PIPE_ARES>, + <&gcc PCIE_AXI_M_VMIDMT_ARES>, + <&gcc PCIE_AXI_S_XPU_ARES>, + <&gcc PCIE_PARF_XPU_ARES>, + <&gcc PCIE_PHY_ARES>, + <&gcc PCIE_AXI_M_STICKY_ARES>, + <&gcc PCIE_PIPE_STICKY_ARES>, + <&gcc PCIE_PWR_ARES>, + <&gcc PCIE_AHB_ARES>, + <&gcc PCIE_PHY_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "pipe", + "axi_m_vmid", + "axi_s_xpu", + "parf", + "phy", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb", + "phy_ahb"; + + status = "disabled"; + }; + + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x7984000 0x1a000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + nand: nand-controller@79b0000 { + compatible = "qcom,ipq4019-nand"; + reg = <0x79b0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; + }; + + wifi0: wifi@a000000 { + compatible = "qcom,ipq4019-wifi"; + reg = <0xa000000 0x200000>; + resets = <&gcc WIFI0_CPU_INIT_RESET>, + <&gcc WIFI0_RADIO_SRIF_RESET>, + <&gcc WIFI0_RADIO_WARM_RESET>, + <&gcc WIFI0_RADIO_COLD_RESET>, + <&gcc WIFI0_CORE_WARM_RESET>, + <&gcc WIFI0_CORE_COLD_RESET>; + reset-names = "wifi_cpu_init", "wifi_radio_srif", + "wifi_radio_warm", "wifi_radio_cold", + "wifi_core_warm", "wifi_core_cold"; + clocks = <&gcc GCC_WCSS2G_CLK>, + <&gcc GCC_WCSS2G_REF_CLK>, + <&gcc GCC_WCSS2G_RTC_CLK>; + clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", + "wifi_wcss_rtc"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "legacy"; + status = "disabled"; + }; + + wifi1: wifi@a800000 { + compatible = "qcom,ipq4019-wifi"; + reg = <0xa800000 0x200000>; + resets = <&gcc WIFI1_CPU_INIT_RESET>, + <&gcc WIFI1_RADIO_SRIF_RESET>, + <&gcc WIFI1_RADIO_WARM_RESET>, + <&gcc WIFI1_RADIO_COLD_RESET>, + <&gcc WIFI1_CORE_WARM_RESET>, + <&gcc WIFI1_CORE_COLD_RESET>; + reset-names = "wifi_cpu_init", "wifi_radio_srif", + "wifi_radio_warm", "wifi_radio_cold", + "wifi_core_warm", "wifi_core_cold"; + clocks = <&gcc GCC_WCSS5G_CLK>, + <&gcc GCC_WCSS5G_REF_CLK>, + <&gcc GCC_WCSS5G_RTC_CLK>; + clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", + "wifi_wcss_rtc"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "legacy"; + status = "disabled"; + }; + + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; + }; + }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3: usb3@8af8800 { + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "core", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + interrupts = ; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2: usb2@60f8800 { + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + interrupts = ; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi new file mode 100644 index 000000000000..9d06255104c7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8062.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi new file mode 100644 index 000000000000..5d3ebd3e2e51 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts new file mode 100644 index 000000000000..a654d3c22c4f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + + soc { + pinmux@800000 { + buttons_pins: buttons_pins { + mux { + pins = "gpio54", "gpio65"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + gsbi@16300000 { + i2c@16380000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts new file mode 100644 index 000000000000..104eb729c2d6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064.dtsi" +#include +#include + +/ { + model = "MikroTik RB3011UiAS-RM"; + compatible = "mikrotik,rb3011", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi7_serial; + ethernet0 = &gmac0; + ethernet1 = &gmac3; + mdio-gpio0 = &mdio0; + mdio-gpio1 = &mdio1; + }; + + chosen { + bootargs = "loglevel=8 console=ttyMSM0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory@42000000 { + reg = <0x42000000 0x3e000000>; + device_type = "memory"; + }; + + mdio0: mdio-0 { + status = "okay"; + compatible = "virtual,mdio-gpio"; + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, + <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch0: switch@10 { + compatible = "qca,qca8337"; + + dsa,member = <0 0>; + + pinctrl-0 = <&sw0_reset_pin>; + pinctrl-names = "default"; + + reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch0cpu: port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "sw1"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@2 { + reg = <2>; + label = "sw2"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@3 { + reg = <3>; + label = "sw3"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@4 { + reg = <4>; + label = "sw4"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@5 { + reg = <5>; + label = "sw5"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + }; + }; + }; + + mdio1: mdio-1 { + status = "okay"; + compatible = "virtual,mdio-gpio"; + gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>, + <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + + switch1: switch@14 { + compatible = "qca,qca8337"; + + dsa,member = <1 0>; + + pinctrl-0 = <&sw1_reset_pin>; + pinctrl-names = "default"; + + reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch1cpu: port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac3>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "sw6"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@2 { + reg = <2>; + label = "sw7"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@3 { + reg = <3>; + label = "sw8"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@4 { + reg = <4>; + label = "sw9"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + port@5 { + reg = <5>; + label = "sw10"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + }; + }; + }; + + soc { + gsbi5: gsbi@1a200000 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + norflash: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "RouterBoot"; + reg = <0x0 0x40000>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + button { + label = "reset"; + linux,code = ; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led-0 { + label = "rb3011:green:user"; + color = ; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + }; +}; + +&adm_dma { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <0>; + phy-handle = <&switch0cpu>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac3 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&switch1cpu>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi7_serial { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "RouterBoard NAND 1 Boot"; + reg = <0x0000000 0x0800000>; + }; + + main@800000 { + label = "RouterBoard NAND 1 Main"; + reg = <0x0800000 0x7800000>; + }; + }; + }; +}; + +&qcom_pinmux { + buttons_pins: buttons_pins { + mux { + pins = "gpio66"; + drive-strength = <16>; + bias-disable; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio33"; + drive-strength = <16>; + bias-disable; + }; + }; + + mdio1_pins: mdio1_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + + sw0_reset_pin: sw0_reset_pin { + mux { + pins = "gpio16"; + drive-strength = <16>; + function = "gpio"; + bias-disable; + input-disable; + }; + }; + + sw1_reset_pin: sw1_reset_pin { + mux { + pins = "gpio17"; + drive-strength = <16>; + function = "gpio"; + bias-disable; + input-disable; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio4"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi new file mode 100644 index 000000000000..ac9c44f0c164 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi new file mode 100644 index 000000000000..c5abe7151f14 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064.dtsi" +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + gsbi@16300000 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + }; + + gsbi5: gsbi@1a200000 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 0>; + + flash: flash@0 { + compatible = "s25fl256s1"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "rootfs"; + reg = <0x0 0x1000000>; + }; + + partition@1 { + label = "scratch"; + reg = <0x1000000 0x1000000>; + }; + }; + }; + }; + + sata-phy@1b400000 { + status = "okay"; + }; + + sata@29000000 { + ports-implemented = <0x1>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + button-1 { + label = "reset"; + linux,code = ; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + button-2 { + label = "wps"; + linux,code = ; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led-0 { + label = "led_usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbdev"; + default-state = "off"; + }; + + led-1 { + label = "led_usb3"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbdev"; + default-state = "off"; + }; + + led-2 { + label = "status_led_fail"; + function = LED_FUNCTION_STATUS; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "sata_led"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + label = "status_led_pass"; + function = LED_FUNCTION_STATUS; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi new file mode 100644 index 000000000000..0442580b22de --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064-v2.0.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi new file mode 100644 index 000000000000..2f117d576daf --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi new file mode 100644 index 000000000000..5ef5026fb7bc --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -0,0 +1,1376 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm IPQ8064"; + compatible = "qcom,ipq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu1: cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + thermal-zones { + sensor0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 0>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor8-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor9-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor10-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem: smem@41000000 { + compatible = "qcom,smem"; + reg = <0x41000000 0x200000>; + no-map; + + hwlocks = <&sfpb_mutex 3>; + }; + }; + + clocks { + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq806x", "qcom,scm"; + }; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <7>; + snps,rd_osr_lmt = <7>; + snps,blen = <16 0 0 0 0 0 0>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + rpm: rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x00108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + qfprom: qfprom@700000 { + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + speedbin_efuse: speedbin@c0 { + reg = <0xc0 0x4>; + }; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; + tsens_calib_backup: calib_backup@410 { + reg = <0x410 0xb>; + }; + }; + + qcom_pinmux: pinmux@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x00800000 0x4000>; + + gpio-controller; + gpio-ranges = <&qcom_pinmux 0 0 69>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + pcie0_pins: pcie0_pinmux { + mux { + pins = "gpio3"; + function = "pcie1_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + pcie1_pins: pcie1_pinmux { + mux { + pins = "gpio48"; + function = "pcie2_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + pcie2_pins: pcie2_pinmux { + mux { + pins = "gpio63"; + function = "pcie3_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + i2c4_pins: i2c4-default { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", + "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + nand_pins: nand_pins { + mux { + pins = "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-disable; + }; + + pullups { + pins = "gpio39"; + function = "nand"; + drive-strength = <10>; + bias-pull-up; + }; + + hold { + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <8>; + bias-disable; + }; + }; + + rgmii2_pins: rgmii2-pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; + clock-names = "pxo", "cxo", "pll4"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + + sfpb_mutex: hwlock@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + + #hwlock-cells = <1>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", + "qcom,msm-timer"; + interrupts = , + , + , + , + ; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + nss_common: syscon@3000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; + }; + + usb3_0: usb@100f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100f8800 0x8000>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_0: usb@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = ; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_0: phy@100f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_0: phy@100f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x100f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_1: usb@110f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x110f8800 0x8000>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_1_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_1: usb@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = ; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = ; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + sd-uhs-sdr104; + sd-uhs-ddr50; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + }; + + gsbi1: gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = ; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + + status = "disabled"; + }; + + gsbi1_i2c: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + syscon-tcsr = <&tcsr>; + + gsbi2_serial: serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi2_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@16380000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16380000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16500000 0x100>; + cell-index = <6>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + gsbi6_spi: spi@16580000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = ; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + + #size-cells = <1>; + ranges; + status = "disabled"; + + syscon-tcsr = <&tcsr>; + + gsbi5_serial: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@1a280000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + nand: nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + sata_phy: sata-phy@1b400000 { + compatible = "qcom,ipq806x-sata-phy"; + reg = <0x1b400000 0x200>; + + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie0: pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000 + 0x1b502000 0x80 + 0x1b600000 0x100 + 0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + status = "disabled"; + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + }; + + pcie1: pci@1b700000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b700000 0x1000 + 0x1b702000 0x80 + 0x1b800000 0x100 + 0x31f00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_1_A_CLK>, + <&gcc PCIE_1_H_CLK>, + <&gcc PCIE_1_PHY_CLK>, + <&gcc PCIE_1_AUX_CLK>, + <&gcc PCIE_1_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_1_ACLK_RESET>, + <&gcc PCIE_1_HCLK_RESET>, + <&gcc PCIE_1_POR_RESET>, + <&gcc PCIE_1_PCI_RESET>, + <&gcc PCIE_1_PHY_RESET>, + <&gcc PCIE_1_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + + status = "disabled"; + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + }; + + pcie2: pci@1b900000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b900000 0x1000 + 0x1b902000 0x80 + 0x1ba00000 0x100 + 0x35f00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_2_A_CLK>, + <&gcc PCIE_2_H_CLK>, + <&gcc PCIE_2_PHY_CLK>, + <&gcc PCIE_2_AUX_CLK>, + <&gcc PCIE_2_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_2_ACLK_RESET>, + <&gcc PCIE_2_HCLK_RESET>, + <&gcc PCIE_2_POR_RESET>, + <&gcc PCIE_2_PCI_RESET>, + <&gcc PCIE_2_PHY_RESET>, + <&gcc PCIE_2_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; + + status = "disabled"; + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + }; + + qsgmii_csr: syscon@1bb00000 { + compatible = "syscon"; + reg = <0x1bb00000 0x000001FF>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix-clk", + "mi2s-osr-clk", + "mi2s-bit-clk"; + interrupts = ; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif"; + }; + + sata: sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; + + interrupts = ; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_face", "iface", "core", + "rxoob", "pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + + gmac1: ethernet@37200000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37200000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE2_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE2_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + + gmac2: ethernet@37400000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37400000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE3_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE3_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + + gmac3: ethernet@37600000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37600000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE4_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE4_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi new file mode 100644 index 000000000000..803e6ff99ef8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8065.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi new file mode 100644 index 000000000000..ea49f6cc416d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts new file mode 100644 index 000000000000..a8304769b509 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Device Tree Source for mangOH Green Board with WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + */ + +#include + +#include "qcom-mdm9615-wp8548.dtsi" +#include +#include + +/ { + model = "MangOH Green with WP8548 Module"; + compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; + + aliases { + spi0 = &gsbi3_spi; + serial0 = &gsbi4_serial; + serial1 = &gsbi5_serial; + i2c0 = &gsbi5_i2c; + mmc0 = &sdcc1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&msmgpio { + /* MangOH GPIO Mapping : + * - 2 : GPIOEXP_INT2 + * - 7 : IOT1_GPIO2 + * - 8 : IOT0_GPIO4 + * - 13: IOT0_GPIO3 + * - 21: IOT1_GPIO4 + * - 22: IOT2_GPIO1 + * - 23: IOT2_GPIO2 + * - 24: IOT2_GPIO3 + * - 25: IOT1_GPIO1 + * - 32: IOT1_GPIO3 + * - 33: IOT0_GPIO2 + * - 42: IOT0_GPIO1 and SD Card Detect + */ + + gpioext1_pins: gpioext1-state { + gpioext1-pins { + pins = "gpio2"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + sdc_cd_pins: sdc-cd-state { + sdc-cd-pins { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi3_spi { + spi@0 { + compatible = "swir,mangoh-iotport-spi"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; + +&gsbi5_i2c { + mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c_iot0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_iot1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_iot2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + usbhub: hub@8 { + compatible = "smsc,usb3503a"; + reg = <0x8>; + connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>; + initial-mode = <1>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpioext0: pinctrl@3e { + /* GPIO Expander 0 Mapping : + * - 0: ARDUINO_RESET_Level shift + * - 1: BattChrgr_PG_N + * - 2: BattGauge_GPIO + * - 3: LED_ON (out active high) + * - 4: ATmega_reset_GPIO + * - 5: X + * - 6: PCM_ANALOG_SELECT (out active high) + * - 7: X + * - 8: Board_rev_res1 (in) + * - 9: Board_rev_res2 (in) + * - 10: UART_EXP1_ENn (out active low / pull-down) + * - 11: UART_EXP1_IN (out pull-down) + * - 12: UART_EXP2_IN (out pull-down) + * - 13: SDIO_SEL (out pull-down) + * - 14: SPI_EXP1_ENn (out active low / pull-down) + * - 15: SPI_EXP1_IN (out pull-down) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&gpioext1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + semtech,probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + gpioext1: pinctrl@3f { + /* GPIO Expander 1 Mapping : + * - 0: GPIOEXP_INT1 + * - 1: Battery detect + * - 2: GPIO_SCF3_RESET + * - 3: LED_CARD_DETECT_IOT0 (in) + * - 4: LED_CARD_DETECT_IOT1 (in) + * - 5: LED_CARD_DETECT_IOT2 (in) + * - 6: UIM2_PWM_SELECT + * - 7: UIM2_M2_S_SELECT + * - 8: TP900 + * - 9: SENSOR_INT1 (in) + * - 10: SENSOR_INT2 (in) + * - 11: CARD_DETECT_IOT0 (in pull-up) + * - 12: CARD_DETECT_IOT2 (in pull-up) + * - 13: CARD_DETECT_IOT1 (in pull-up) + * - 14: GPIOEXP_INT3 (in active low / pull-up) + * - 15: BattChrgr_INT_N + */ + pinctrl-0 = <&gpioext1_pins>; + pinctrl-names = "default"; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3f>; + interrupt-parent = <&msmgpio>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + semtech,probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + gpioext2: pinctrl@70 { + /* GPIO Expander 2 Mapping : + * - 0: USB_HUB_INTn + * - 1: HUB_CONNECT + * - 2: GPIO_IOT2_RESET (out active low / pull-up) + * - 3: GPIO_IOT1_RESET (out active low / pull-up) + * - 4: GPIO_IOT0_RESET (out active low / pull-up) + * - 5: TP901 + * - 6: TP902 + * - 7: TP903 + * - 8: UART_EXP2_ENn (out active low / pull-down) + * - 9: PCM_EXP1_ENn (out active low) + * - 10: PCM_EXP1_SEL (out) + * - 11: ARD_FTDI + * - 12: TP904 + * - 13: TP905 + * - 14: TP906 + * - 15: RS232_Enable (out active high / pull-up) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x70>; + interrupt-parent = <&gpioext1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + semtech,probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&sdcc1 { + pinctrl-0 = <&sdc_cd_pins>; + pinctrl-names = "default"; + disable-wp; + cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ +}; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi new file mode 100644 index 000000000000..92c8003dac25 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Device Tree Source for Sierra Wireless WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + */ + +#include "qcom-mdm9615.dtsi" + +/ { + model = "Sierra Wireless WP8548 Module"; + compatible = "swir,wp8548", "qcom,mdm9615"; + + memory@48000000 { + device_type = "memory"; + reg = <0x48000000 0x7F00000>; + }; +}; + +&msmgpio { + pinctrl-0 = <&reset_out_pins>; + pinctrl-names = "default"; + + gsbi3_pins: gsbi3-state { + gsbi3-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi4_pins: gsbi4-state { + gsbi4-pins { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gsbi4"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi5_i2c_pins: gsbi5-i2c-state { + sda-pins { + pins = "gpio16"; + function = "gsbi5_i2c"; + drive-strength = <8>; + bias-disable; + }; + + scl-pins { + pins = "gpio17"; + function = "gsbi5_i2c"; + drive-strength = <2>; + bias-disable; + }; + }; + + gsbi5_uart_pins: gsbi5-uart-state { + gsbi5-uart-pins { + pins = "gpio18", "gpio19"; + function = "gsbi5_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + reset_out_pins: reset-out-state { + reset-out-pins { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; + +&pmicgpio { + usb_vbus_5v_pins: usb-vbus-5v-state { + pins = "gpio4"; + function = "normal"; + output-high; + bias-disable; + qcom,drive-strength = <1>; + power-source = <2>; + }; +}; + +&gsbi3 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi3_spi { + status = "okay"; + pinctrl-0 = <&gsbi3_pins>; + pinctrl-names = "default"; + assigned-clocks = <&gcc GSBI3_QUP_CLK>; + assigned-clock-rates = <24000000>; +}; + +&gsbi4 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi4_serial { + status = "okay"; + pinctrl-0 = <&gsbi4_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi5_i2c { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&gsbi5_i2c_pins>; + pinctrl-names = "default"; +}; + +&gsbi5_serial { + status = "okay"; + pinctrl-0 = <&gsbi5_uart_pins>; + pinctrl-names = "default"; +}; + +&sdcc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi new file mode 100644 index 000000000000..b40c52ddf9b4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Device Tree Source for Qualcomm MDM9615 SoC + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm MDM9615"; + compatible = "qcom,mdm9615"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a5"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = ; + }; + + clocks { + cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + regulators { + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + L2: cache-controller@2040000 { + compatible = "arm,pl310-cache"; + reg = <0x02040000 0x1000>; + arm,data-latency = <2 2 0>; + cache-unified; + cache-level = <2>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", + "qcom,msm-timer"; + interrupts = , + , + ; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 88>; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-mdm9615"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc PRNG_CLK>; + assigned-clock-rates = <32000000>; + }; + + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x16100000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16180000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi3_spi: spi@16280000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16280000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_i2c: i2c@16480000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16480000 0x1000>; + interrupts = ; + + /* QUP clock is not initialized, set rate */ + assigned-clocks = <&gcc GSBI5_QUP_CLK>; + assigned-clock-rates = <24000000>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic { + compatible = "qcom,pm8018", "qcom,pm8921"; + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + pmicmpp: mpps@50 { + compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmicmpp 0 0 6>; + }; + + rtc@11d { + compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + + pmicgpio: gpio@150 { + compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + reg = <0x150>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + gpio-ranges = <&pmicgpio 0 0 6>; + #gpio-cells = <2>; + }; + }; + }; + + sdcc1bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc2bam: dma-controller@12142000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12142000 0x8000>; + interrupts = ; + clocks = <&gcc SDC2_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1: mmc@12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; + + sdcc2: mmc@12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = ; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-mdm9615", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-mdm9615"; + reg = <0x108000 0x1000>; + + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8018-regulators"; + + vin_lvs1-supply = <&pm8018_s3>; + + vdd_l7-supply = <&pm8018_s4>; + vdd_l8-supply = <&pm8018_s3>; + vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; + + /* Buck SMPS */ + pm8018_s1: s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s2: s2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s3: s3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s4: s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s5: s5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8018_l2: l2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l3: l3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l4: l4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8018_l5: l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8018_l8: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8018_l9: l9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8018_l10: l10 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l11: l11 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l13: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8018_l14: l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8018_lvs1: lvs1 { + bias-pull-down; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts new file mode 100644 index 000000000000..288cacd5d1fa --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "qcom-msm8226.dtsi" + +/ { + model = "Samsung Galaxy S III Neo"; + compatible = "samsung,s3ve3g", "qcom,msm8226"; + chassis-type = "handset"; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi new file mode 100644 index 000000000000..313a726f4704 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-msm8226", "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_region: smem@3000000 { + reg = <0x3000000 0x100000>; + no-map; + }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8226"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8226-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apcs: syscon@f9011000 { + compatible = "syscon"; + reg = <0xf9011000 0x1000>; + }; + + sdhc_1: mmc@f9824900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_default_state>; + status = "disabled"; + }; + + sdhc_2: mmc@f98a4900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_default_state>; + status = "disabled"; + }; + + sdhc_3: mmc@f9864900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_default_state>; + status = "disabled"; + }; + + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart3: serial@f991f000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991f000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart4: serial@f9920000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf9920000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_i2c1: i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c1_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c2_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@f9925000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9925000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c3_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c4: i2c@f9926000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9926000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c4_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c5: i2c@f9927000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9927000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c5_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci: cci@fda0c000 { + compatible = "qcom,msm8226-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfda0c000 0x1000>; + interrupts = ; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci_default>; + pinctrl-1 = <&cci_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + usb: usb@f9a55000 { + compatible = "qcom,ci-hdrc"; + reg = <0xf9a55000 0x200>, + <0xf9a55200 0x200>; + interrupts = ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <75000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8226", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + qcom,init-seq = /bits/ 8 <0x0 0x44 + 0x1 0x68 0x2 0x24 0x3 0x13>; + }; + }; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8226"; + reg = <0xfc400000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>; + clock-names = "xo", + "sleep_clk"; + }; + + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8226"; + reg = <0xfd8c0000 0x6000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte"; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + blsp1_i2c1_pins: blsp1-i2c1-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_pins: blsp1-i2c2-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_pins: blsp1-i2c3-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_pins: blsp1-i2c4-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c5_pins: blsp1-i2c5-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + cci_default: cci-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c0"; + + drive-strength = <2>; + bias-disable; + }; + + cci_sleep: cci-sleep-state { + pins = "gpio29", "gpio30"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc1_default_state: sdhc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_default_state: sdhc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc3_default_state: sdhc3-default-state { + clk-pins { + pins = "gpio44"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio43"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio39", "gpio40", "gpio41", "gpio42"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2"; + #qcom,sensors = <6>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + qfprom: qfprom@fc4bc000 { + compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@1c1 { + reg = <0x1c1 0x2>; + bits = <5 8>; + }; + + tsens_s0_p1: s0-p1@1c2 { + reg = <0x1c2 0x2>; + bits = <5 6>; + }; + + tsens_s1_p1: s1-p1@1c4 { + reg = <0x1c4 0x1>; + bits = <0 6>; + }; + + tsens_s2_p1: s2-p1@1c4 { + reg = <0x1c4 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1c5 { + reg = <0x1c5 0x2>; + bits = <4 6>; + }; + + tsens_s4_p1: s4-p1@1c6 { + reg = <0x1c6 0x1>; + bits = <2 6>; + }; + + tsens_s5_p1: s5-p1@1c7 { + reg = <0x1c7 0x1>; + bits = <0 6>; + }; + + tsens_s6_p1: s6-p1@1ca { + reg = <0x1ca 0x2>; + bits = <4 6>; + }; + + tsens_base2: base2@1cc { + reg = <0x1cc 0x1>; + bits = <0 8>; + }; + + tsens_s0_p2: s0-p2@1cd { + reg = <0x1cd 0x1>; + bits = <0 6>; + }; + + tsens_s1_p2: s1-p2@1cd { + reg = <0x1cd 0x2>; + bits = <6 6>; + }; + + tsens_s2_p2: s2-p2@1ce { + reg = <0x1ce 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1cf { + reg = <0x1cf 0x1>; + bits = <2 6>; + }; + + tsens_s4_p2: s4-p2@446 { + reg = <0x446 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@447 { + reg = <0x447 0x1>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@44e { + reg = <0x44e 0x1>; + bits = <1 6>; + }; + + tsens_mode: mode@44f { + reg = <0x44f 0x1>; + bits = <5 3>; + }; + }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + timer@f9020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + sram@fc190000 { + compatible = "qcom,msm8226-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + + rpm_msg_ram: sram@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; + #hwlock-cells = <1>; + }; + + adsp: remoteproc@fe200000 { + compatible = "qcom,msm8226-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + + label = "lpass"; + }; + }; + + sram@fe805000 { + compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-bootloader = <0x77665500>; + mode-normal = <0x77665501>; + mode-recovery = <0x77665502>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts new file mode 100644 index 000000000000..be18f1be29a1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include "qcom-msm8660.dtsi" + +/ { + model = "Qualcomm MSM8660 SURF"; + compatible = "qcom,msm8660-surf", "qcom,msm8660"; + + aliases { + serial0 = &gsbi12_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; +}; + +&gsbi12 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi12_serial { + status = "okay"; +}; + +&pm8058 { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_FN_F1) + MATRIX_KEY(0, 1, KEY_UP) + MATRIX_KEY(0, 2, KEY_LEFT) + MATRIX_KEY(0, 3, KEY_VOLUMEUP) + MATRIX_KEY(1, 0, KEY_FN_F2) + MATRIX_KEY(1, 1, KEY_RIGHT) + MATRIX_KEY(1, 2, KEY_DOWN) + MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) + MATRIX_KEY(2, 3, KEY_ENTER) + MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) + MATRIX_KEY(4, 1, KEY_UP) + MATRIX_KEY(4, 2, KEY_LEFT) + MATRIX_KEY(4, 3, KEY_HOME) + MATRIX_KEY(4, 4, KEY_FN_F3) + MATRIX_KEY(5, 0, KEY_CAMERA) + MATRIX_KEY(5, 1, KEY_RIGHT) + MATRIX_KEY(5, 2, KEY_DOWN) + MATRIX_KEY(5, 3, KEY_BACK) + MATRIX_KEY(5, 4, KEY_MENU) + >; + keypad,num-rows = <6>; + keypad,num-columns = <5>; + }; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&vsdcc_fixed>; + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + vmmc-supply = <&vsdcc_fixed>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi new file mode 100644 index 000000000000..f601b40ebcf4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm MSM8660"; + compatible = "qcom,msm8660"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + cpu-pmu { + compatible = "qcom,scorpion-mp-pmu"; + interrupts = <1 9 0x304>; + }; + + clocks { + cxo_board: cxo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "cxo_board"; + }; + + pxo_board: pxo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "pxo_board"; + }; + + sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sleep_clk"; + }; + }; + + /* + * These channels from the ADC are simply hardware monitors. + * That is why the ADC is referred to as "HKADC" - HouseKeeping + * ADC. + */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xoadc 0x00 0x01>, /* Battery */ + <&xoadc 0x00 0x02>, /* DC in (charger) */ + <&xoadc 0x00 0x04>, /* VPH the main system voltage */ + <&xoadc 0x00 0x0b>, /* Die temperature */ + <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ + <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ + <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2080000 { + compatible = "qcom,msm-8660-qgic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02080000 0x1000 >, + < 0x02081000 0x1000 >; + }; + + timer@2000000 { + compatible = "qcom,scss-timer", "qcom,msm-timer"; + interrupts = <1 0 0x301>, + <1 1 0x301>, + <1 2 0x301>; + reg = <0x02000000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x40000>; + }; + + tlmm: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + gpio-ranges = <&tlmm 0 0 173>; + #gpio-cells = <2>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8660"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16000000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16500000 0x100>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + syscon-tcsr = <&tcsr>; + + gsbi6_serial: serial@16540000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16540000 0x1000>, + <0x16500000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi8: gsbi@19800000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x19800000 0x100>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + status = "disabled"; + + gsbi8_i2c: i2c@19880000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19880000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi12: gsbi@19c00000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x19c00000 0x100>; + clocks = <&gcc GSBI12_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi12_serial: serial@19c40000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi12_i2c: i2c@19c80000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19c80000 0x1000>; + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + ebi2: external-bus@1a100000 { + compatible = "qcom,msm8660-ebi2"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x1a800000 0x00800000>, + <1 0x0 0x1b000000 0x00800000>, + <2 0x0 0x1b800000 0x00800000>, + <3 0x0 0x1d000000 0x08000000>, + <4 0x0 0x1c800000 0x00800000>, + <5 0x0 0x1c000000 0x00800000>; + reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; + reg-names = "ebi2", "xmem"; + clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; + clock-names = "ebi2x", "ebi2"; + status = "disabled"; + }; + + ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pm8058: pmic { + compatible = "qcom,pm8058"; + interrupt-parent = <&tlmm>; + interrupts = <88 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pm8058_gpio: gpio@150 { + compatible = "qcom,pm8058-gpio", + "qcom,ssbi-gpio"; + reg = <0x150>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + gpio-ranges = <&pm8058_gpio 0 0 44>; + #gpio-cells = <2>; + + }; + + pm8058_mpps: mpps@50 { + compatible = "qcom,pm8058-mpp", + "qcom,ssbi-mpp"; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8058_mpps 0 0 12>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwrkey@1c { + compatible = "qcom,pm8058-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pm8058>; + interrupts = <50 1>, <51 1>; + debounce = <15625>; + pull-up; + }; + + pm8058_keypad: keypad@148 { + compatible = "qcom,pm8058-keypad"; + reg = <0x148>; + interrupt-parent = <&pm8058>; + interrupts = <74 1>, <75 1>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + + xoadc: xoadc@197 { + compatible = "qcom,pm8058-adc"; + reg = <0x197>; + interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; + #address-cells = <2>; + #size-cells = <0>; + #io-channel-cells = <2>; + + vcoin: adc-channel@0 { + reg = <0x00 0x00>; + }; + vbat: adc-channel@1 { + reg = <0x00 0x01>; + }; + dcin: adc-channel@2 { + reg = <0x00 0x02>; + }; + ichg: adc-channel@3 { + reg = <0x00 0x03>; + }; + vph_pwr: adc-channel@4 { + reg = <0x00 0x04>; + }; + usb_vbus: adc-channel@a { + reg = <0x00 0x0a>; + }; + die_temp: adc-channel@b { + reg = <0x00 0x0b>; + }; + ref_625mv: adc-channel@c { + reg = <0x00 0x0c>; + }; + ref_1250mv: adc-channel@d { + reg = <0x00 0x0d>; + }; + ref_325mv: adc-channel@e { + reg = <0x00 0x0e>; + }; + ref_muxoff: adc-channel@f { + reg = <0x00 0x0f>; + }; + }; + + rtc@1e8 { + compatible = "qcom,pm8058-rtc"; + reg = <0x1e8>; + interrupt-parent = <&pm8058>; + interrupts = <39 1>; + allow-set-time; + }; + + vibrator@4a { + compatible = "qcom,pm8058-vib"; + reg = <0x4a>; + }; + + pm8058_led48: led@48 { + compatible = "qcom,pm8058-keypad-led"; + reg = <0x48>; + status = "disabled"; + }; + + pm8058_led131: led@131 { + compatible = "qcom,pm8058-led"; + reg = <0x131>; + status = "disabled"; + }; + + pm8058_led132: led@132 { + compatible = "qcom,pm8058-led"; + reg = <0x132>; + status = "disabled"; + }; + + pm8058_led133: led@133 { + compatible = "qcom,pm8058-led"; + reg = <0x133>; + status = "disabled"; + }; + + }; + }; + + l2cc: clock-controller@2082000 { + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; + reg = <0x02082000 0x1000>; + }; + + rpm: rpm@104000 { + compatible = "qcom,rpm-msm8660"; + reg = <0x00104000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; + }; + + regulators-0 { + compatible = "qcom,rpm-pm8901-regulators"; + + pm8901_l0: l0 {}; + pm8901_l1: l1 {}; + pm8901_l2: l2 {}; + pm8901_l3: l3 {}; + pm8901_l4: l4 {}; + pm8901_l5: l5 {}; + pm8901_l6: l6 {}; + + /* S0 and S1 Handled as SAW regulators by SPM */ + pm8901_s2: s2 {}; + pm8901_s3: s3 {}; + pm8901_s4: s4 {}; + + pm8901_lvs0: lvs0 {}; + pm8901_lvs1: lvs1 {}; + pm8901_lvs2: lvs2 {}; + pm8901_lvs3: lvs3 {}; + + pm8901_mvs: mvs {}; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8058-regulators"; + + pm8058_l0: l0 {}; + pm8058_l1: l1 {}; + pm8058_l2: l2 {}; + pm8058_l3: l3 {}; + pm8058_l4: l4 {}; + pm8058_l5: l5 {}; + pm8058_l6: l6 {}; + pm8058_l7: l7 {}; + pm8058_l8: l8 {}; + pm8058_l9: l9 {}; + pm8058_l10: l10 {}; + pm8058_l11: l11 {}; + pm8058_l12: l12 {}; + pm8058_l13: l13 {}; + pm8058_l14: l14 {}; + pm8058_l15: l15 {}; + pm8058_l16: l16 {}; + pm8058_l17: l17 {}; + pm8058_l18: l18 {}; + pm8058_l19: l19 {}; + pm8058_l20: l20 {}; + pm8058_l21: l21 {}; + pm8058_l22: l22 {}; + pm8058_l23: l23 {}; + pm8058_l24: l24 {}; + pm8058_l25: l25 {}; + + pm8058_s0: s0 {}; + pm8058_s1: s1 {}; + pm8058_s2: s2 {}; + pm8058_s3: s3 {}; + pm8058_s4: s4 {}; + + pm8058_lvs0: lvs0 {}; + pm8058_lvs1: lvs1 {}; + + pm8058_ncp: ncp {}; + }; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + + sdcc2: mmc@12140000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12140000 0x8000>; + interrupts = ; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = ; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + }; + + sdcc4: mmc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = ; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + + sdcc5: mmc@12200000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = ; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8660", "syscon"; + reg = <0x1a400000 0x100>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts new file mode 100644 index 000000000000..c8d34de8a71e --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-e5.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts new file mode 100644 index 000000000000..85be286c8608 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-e7.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts new file mode 100644 index 000000000000..d3abe0536238 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-grandmax.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts new file mode 100644 index 000000000000..dee2c20af355 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-serranove.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi new file mode 100644 index 000000000000..36328dbe4212 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/ { + cpus { + cpu@0 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@1 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@2 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@3 { + enable-method = "qcom,msm8916-smp"; + }; + + idle-states { + /delete-property/ entry-method; + }; + }; + + psci { + status = "disabled"; + }; +}; + +&CPU_SLEEP_0 { + compatible = "qcom,idle-state-spc"; +}; + +&cpu0_acc { + status = "okay"; +}; + +&cpu0_saw { + status = "okay"; +}; + +&cpu1_acc { + status = "okay"; +}; + +&cpu1_saw { + status = "okay"; +}; + +&cpu2_acc { + status = "okay"; +}; + +&cpu2_saw { + status = "okay"; +}; + +&cpu3_acc { + status = "okay"; +}; + +&cpu3_saw { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts new file mode 100644 index 000000000000..6c1bc3818883 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include "qcom-msm8960.dtsi" + +/ { + model = "Qualcomm MSM8960 CDP"; + compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + + aliases { + serial0 = &gsbi5_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_l2: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "ext_l2"; + gpio = <&msmgpio 91 0>; + startup-delay-us = <10000>; + enable-active-high; + }; +}; + +&gsbi1 { + qcom,mode = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_default>; + status = "okay"; +}; + +&gsbi1_spi { + status = "okay"; + + ethernet@0 { + compatible = "micrel,ks8851"; + reg = <0>; + interrupt-parent = <&msmgpio>; + interrupts = <90 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <5400000>; + vdd-supply = <&ext_l2>; + vdd-io-supply = <&pm8921_lvs6>; + reset-gpios = <&msmgpio 89 0>; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi5_serial { + status = "okay"; +}; + +&msmgpio { + spi1_default: spi1-default-state { + mosi-pins { + pins = "gpio6"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + miso-pins { + pins = "gpio7"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio8"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk-pins { + pins = "gpio9"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + +&pmicintc { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEUP) + MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) + MATRIX_KEY(0, 3, KEY_CAMERA) + >; + keypad,num-rows = <1>; + keypad,num-columns = <5>; + }; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* eMMC */ +&sdcc1 { + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts new file mode 100644 index 000000000000..13e85c287498 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include "qcom-msm8960.dtsi" +#include + +/ { + model = "Samsung Galaxy Express SGH-I437"; + compatible = "samsung,expressatt", "qcom,msm8960"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi5_serial; + mmc0 = &sdcc1; /* SDCC1 eMMC slot */ + mmc1 = &sdcc3; /* SDCC3 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi5_serial { + status = "okay"; +}; + +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + status = "okay"; +}; + +&sdcc3 { + vmmc-supply = <&pm8921_l6>; + vqmmc-supply = <&pm8921_l7>; + status = "okay"; +}; + +&gsbi1 { + qcom,mode = ; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gsbi1_spi { + status = "okay"; +}; + +&msmgpio { + spi1_default: spi1-default-state { + mosi-pins { + pins = "gpio6"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + miso-pins { + pins = "gpio7"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio8"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk-pins { + pins = "gpio9"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi new file mode 100644 index 000000000000..581b3ab5c4ca --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm MSM8960"; + compatible = "qcom,msm8960"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + + cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + qcom,no-pc-write; + }; + + clocks { + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "cxo_board"; + }; + + pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "pxo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sleep_clk"; + }; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; + interrupts = , + , + ; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8960-pinctrl"; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 152>; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-msm8960"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + }; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic { + compatible = "qcom,pm8921"; + interrupt-parent = <&msmgpio>; + interrupts = <104 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + keypad@148 { + compatible = "qcom,pm8921-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 IRQ_TYPE_EDGE_RISING>, + <75 IRQ_TYPE_EDGE_RISING>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + + rtc@11d { + compatible = "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + }; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = ; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <1>; + reg = <0x16000000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16080000 0x1000>; + interrupts = ; + spi-max-frequency = <24000000>; + cs-gpios = <&msmgpio 8 0>; + + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + usb1: usb@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + #reset-cells = <1>; + status = "disabled"; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-msm8960", + "qcom,usb-hs-phy"; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + #phy-cells = <0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts new file mode 100644 index 000000000000..e2a7ab7de89b --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -0,0 +1,698 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include +#include +#include + +/ { + model = "LGE MSM 8974 HAMMERHEAD"; + compatible = "lge,hammerhead", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + serial0 = &blsp1_uart1; + serial1 = &blsp2_uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; + + clk_pwm: pwm { + compatible = "clk-pwm"; + clocks = <&mmcc CAMSS_GP1_CLK>; + + pinctrl-0 = <&vibrator_pin>; + pinctrl-names = "default"; + + #pwm-cells = <2>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <&pm8941_l19>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; +}; + +&blsp1_i2c1 { + status = "okay"; + clock-frequency = <100000>; + + charger: bq24192@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; + + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; + }; + + fuelgauge: max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x4d>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + + maxim,alert-low-soc-level = <2>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + clock-frequency = <355000>; + + synaptics@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; + + interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + clock-frequency = <100000>; + + avago_apds993@39 { + compatible = "avago,apds9930"; + reg = <0x39>; + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l17>; + vddio-supply = <&pm8941_lvs1>; + led-max-microamp = <100000>; + amstaos,proximity-diodes = <0>; + }; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + led-controller@38 { + compatible = "ti,lm3630a"; + status = "okay"; + reg = <0x38>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <200>; + }; + }; +}; + +&blsp2_i2c6 { + status = "okay"; + clock-frequency = <100000>; + + mpu6515@68 { + compatible = "invensense,mpu6515"; + reg = <0x68>; + interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>; + vddio-supply = <&pm8941_lvs1>; + + pinctrl-names = "default"; + pinctrl-0 = <&mpu6515_pin>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ak8963@f { + compatible = "asahi-kasei,ak8963"; + reg = <0x0f>; + gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; + vid-supply = <&pm8941_lvs1>; + vdd-supply = <&pm8941_l17>; + }; + + bmp280@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + vdda-supply = <&pm8941_lvs1>; + vddd-supply = <&pm8941_l17>; + }; + }; + }; +}; + +&blsp1_uart1 { + status = "okay"; +}; + +&blsp2_uart4 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_pin>; + + host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; + + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_lvs3>; + vddio-supply = <&pm8941_l12>; + + panel: panel@0 { + reg = <0>; + compatible = "lg,acx467akm-7"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + + vddio-supply = <&pm8941_l12>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio9"; + function = "normal"; + + bias-disable; + input-enable; + power-source = ; + }; + + wlan_sleep_clk_pin: wl-sleep-clk-state { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active-state { + pins = "gpio17"; + function = "normal"; + + bias-disable; + power-source = ; + }; + + otg { + gpio-hog; + gpios = <35 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "otg-gpio"; + }; +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@7 { + reg = <7>; + color = ; + }; + + led@6 { + reg = <6>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + + pm8941_lvs1: lvs1 {}; + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8941_s3>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; +}; + +&tlmm { + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + mpu6515_pin: mpu6515-state { + pins = "gpio73"; + function = "gpio"; + bias-disable; + input-enable; + }; + + touch_pin: touch-state { + int-pins { + pins = "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + + reset-pins { + pins = "gpio8"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + panel_pin: panel-state { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; + + bt_pin: bt-state { + hostwake-pins { + pins = "gpio42"; + function = "gpio"; + }; + + devwake-pins { + pins = "gpio62"; + function = "gpio"; + }; + + shutdown-pins { + pins = "gpio41"; + function = "gpio"; + }; + }; + + vibrator_pin: vibrator-state { + core-pins { + pins = "gpio27"; + function = "gp1_clk"; + drive-strength = <6>; + bias-disable; + }; + + enable-pins { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + extcon = <&charger>, <&usb_id>; + vbus-supply = <&usb_otg_vbus>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts new file mode 100644 index 000000000000..9f2ab5c122d0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974-sony-xperia-rhine.dtsi" + +/ { + model = "Sony Xperia Z1 Compact"; + compatible = "sony,xperia-amami", "qcom,msm8974"; + chassis-type = "handset"; +}; + +&smbb { + qcom,fast-charge-safe-current = <1300000>; + qcom,fast-charge-current-limit = <1300000>; + qcom,dc-current-limit = <1300000>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts new file mode 100644 index 000000000000..9028f17e5c4a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974-sony-xperia-rhine.dtsi" + +/ { + model = "Sony Xperia Z1"; + compatible = "sony,xperia-honami", "qcom,msm8974"; + chassis-type = "handset"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi new file mode 100644 index 000000000000..d3bec03b126c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@3e8e0000 { + compatible = "ramoops"; + reg = <0x3e8e0000 0x200000>; + + console-size = <0x100000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x80000>; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + clock-frequency = <355000>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + clock-frequency = <355000>; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <59 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&pm8941_gpios 23 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + qcom,controlled-remotely; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + /* sii8334 MHL HDMI bridge */ +}; + +&pm8941_coincell { + status = "okay"; + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio4", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = ; + }; + + led@6 { + reg = <6>; + color = ; + }; + + led@7 { + reg = <7>; + color = ; + }; + }; +}; + +&pm8941_wled { + status = "okay"; + + qcom,cs-out; + qcom,current-limit = <20>; + qcom,current-boost-limit = <805>; + qcom,switching-freq = <1600>; + qcom,ovp = <29>; + qcom,num-strings = <2>; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; +}; + +&tlmm { + ts_int_pin: touch-int-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + + cd-pins { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi new file mode 100644 index 000000000000..21fae1f8966f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -0,0 +1,2405 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + + CPU0: cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU1: cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU2: cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU3: cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + qcom,saw = <&saw_l2>; + }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-msm8974", "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_region: mpss@8000000 { + reg = <0x08000000 0x5100000>; + no-map; + }; + + mba_region: mba@d100000 { + reg = <0x0d100000 0x100000>; + no-map; + }; + + wcnss_region: wcnss@d200000 { + reg = <0x0d200000 0xa00000>; + no-map; + }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; + + venus_region: memory@f500000 { + reg = <0x0f500000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0xfa00000 0x200000>; + no-map; + }; + + tz_region: memory@fc00000 { + reg = <0x0fc00000 0x160000>; + no-map; + }; + + rfsa_mem: memory@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-2 = <&apcs 8 9>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + }; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + apcs: syscon@f9011000 { + compatible = "syscon"; + reg = <0xf9011000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + saw0: power-controller@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { + compatible = "qcom,saw2"; + reg = <0xf9012000 0x1000>; + regulator; + }; + + acc0: power-manager@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + }; + + acc1: power-manager@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + }; + + acc2: power-manager@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + }; + + acc3: power-manager@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + }; + + sdhc_1: mmc@f9824900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <8>; + non-removable; + + status = "disabled"; + }; + + sdhc_3: mmc@f9864900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + sdhc_2: mmc@f98a4900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; + status = "disabled"; + }; + + blsp1_i2c1: i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c1_default>; + pinctrl-1 = <&blsp1_i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@f9925000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9925000 0x1000>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c6: i2c@f9928000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c6_default>; + pinctrl-1 = <&blsp1_i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_dma: dma-controller@f9944000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xf9944000 0x19000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart1: serial@f995d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995d000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart1_default>; + pinctrl-1 = <&blsp2_uart1_sleep>; + status = "disabled"; + }; + + blsp2_uart2: serial@f995e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995e000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_uart4: serial@f9960000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf9960000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart4_default>; + status = "disabled"; + }; + + blsp2_i2c2: i2c@f9964000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9964000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c5: i2c@f9967000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9967000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c5_default>; + pinctrl-1 = <&blsp2_i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c6: i2c@f9968000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9968000 0x1000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb: usb@f9a55000 { + compatible = "qcom,ci-hdrc"; + reg = <0xf9a55000 0x200>, + <0xf9a55200 0x200>; + interrupts = ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <75000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs1_phy: phy-0 { + compatible = "qcom,usb-hs-phy-msm8974", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb_hs2_phy: phy-1 { + compatible = "qcom,usb-hs-phy-msm8974", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; + reset-names = "phy", "por"; + status = "disabled"; + }; + }; + }; + + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + pronto: remoteproc@fb204000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_region>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + iris { + compatible = "qcom,wcn3680"; + + clocks = <&rpmcc RPM_SMD_CXO_A2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + status = "disabled"; + + qcom,mmio = <&pronto>; + + bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + sram@fc190000 { + compatible = "qcom,msm8974-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + + etf@fc307000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0xfc307000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merger_out>; + }; + }; + }; + }; + + tpiu@fc318000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xfc318000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; + }; + + funnel@fc31a000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc31a000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - not-connected + * 1 - connected trought funnel to Multimedia CPU + * 2 - connected to Wireless CPU + * 3 - not-connected + * 4 - not-connected + * 6 - not-connected + * 7 - connected to STM + */ + port@5 { + reg = <5>; + funnel1_in5: endpoint { + remote-endpoint = <&kpss_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merger_in1>; + }; + }; + }; + }; + + funnel@fc31b000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc31b000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - connected trought funnel to Audio, Modem and + * Resource and Power Manager CPU's + * 2...7 - not-connected + */ + port@1 { + reg = <1>; + merger_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; + + out-ports { + port { + merger_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + }; + + replicator@fc31c000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0xfc31c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etr@fc322000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0xfc322000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; + }; + + etm@fc33c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&kpss_in0>; + }; + }; + }; + }; + + etm@fc33d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33d000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&kpss_in1>; + }; + }; + }; + }; + + etm@fc33e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33e000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&kpss_in2>; + }; + }; + }; + }; + + etm@fc33f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33f000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&kpss_in3>; + }; + }; + }; + }; + + /* KPSS funnel, only 4 inputs are used */ + funnel@fc345000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc345000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + kpss_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + kpss_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + kpss_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + kpss_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + kpss_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; + }; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x4000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>; + clock-names = "xo", + "sleep_clk"; + }; + + rpm_msg_ram: sram@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + bimc: interconnect@fc380000 { + reg = <0xfc380000 0x6a000>; + compatible = "qcom,msm8974-bimc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + snoc: interconnect@fc460000 { + reg = <0xfc460000 0x4000>; + compatible = "qcom,msm8974-snoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + pnoc: interconnect@fc468000 { + reg = <0xfc468000 0x4000>; + compatible = "qcom,msm8974-pnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PNOC_CLK>, + <&rpmcc RPM_SMD_PNOC_A_CLK>; + }; + + ocmemnoc: interconnect@fc470000 { + reg = <0xfc470000 0x4000>; + compatible = "qcom,msm8974-ocmemnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; + }; + + mmssnoc: interconnect@fc478000 { + reg = <0xfc478000 0x4000>; + compatible = "qcom,msm8974-mmssnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&mmcc MMSS_S0_AXI_CLK>, + <&mmcc MMSS_S0_AXI_CLK>; + }; + + cnoc: interconnect@fc480000 { + reg = <0xfc480000 0x4000>; + compatible = "qcom,msm8974-cnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; + #qcom,sensors = <11>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + qfprom: qfprom@fc4bc000 { + compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; + }; + }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + + remoteproc_mss: remoteproc@fc880000 { + compatible = "qcom,msm8974-mss-pil"; + reg = <0xfc880000 0x100>, <0xfc820000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; + reg = <0xfd484000 0x2000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@fd4a0000 { + compatible = "qcom,tcsr-msm8974", "syscon"; + reg = <0xfd4a0000 0x10000>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + sdc1_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + cd-pins { + pins = "gpio54"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + rx-pins { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-pull-up; + }; + + tx-pins { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <4>; + bias-disable; + }; + }; + + blsp2_uart1_default: blsp2-uart1-default-state { + tx-rts-pins { + pins = "gpio41", "gpio44"; + function = "blsp_uart7"; + drive-strength = <2>; + bias-disable; + }; + + rx-cts-pins { + pins = "gpio42", "gpio43"; + function = "blsp_uart7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp2_uart1_sleep: blsp2-uart1-sleep-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_uart4_default: blsp2-uart4-default-state { + tx-rts-pins { + pins = "gpio53", "gpio56"; + function = "blsp_uart10"; + drive-strength = <2>; + bias-disable; + }; + + rx-cts-pins { + pins = "gpio54", "gpio55"; + function = "blsp_uart10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_i2c1_default: blsp1-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP1_I2C4 info is missing */ + + /* BLSP1_I2C5 info is missing */ + + blsp1_i2c6_default: blsp1-i2c6-default-state { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-pull-up; + }; + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ + + /* BLSP2_I2C1 info is missing */ + + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP2_I2C3 info is missing */ + + /* BLSP2_I2C4 info is missing */ + + blsp2_i2c5_default: blsp2-i2c5-default-state { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c6_default: blsp2-i2c6-default-state { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-pull-up; + }; + + cci_default: cci-default-state { + cci_i2c0_default: cci-i2c0-default-pins { + pins = "gpio19", "gpio20"; + function = "cci_i2c0"; + drive-strength = <2>; + bias-disable; + }; + + cci_i2c1_default: cci-i2c1-default-pins { + pins = "gpio21", "gpio22"; + function = "cci_i2c1"; + drive-strength = <2>; + bias-disable; + }; + }; + + cci_sleep: cci-sleep-state { + cci_i2c0_sleep: cci-i2c0-sleep-pins { + pins = "gpio19", "gpio20"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci_i2c1_sleep: cci-i2c1-sleep-pins { + pins = "gpio21", "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi8_default: spi8_default-state { + mosi-pins { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso-pins { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs-pins { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk-pins { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; + }; + + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfd8c0000 0x6000>; + clocks = <&xo_board>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll", + "edp_link_clk", + "edp_vco_div"; + }; + + mdss: display-subsystem@fd900000 { + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: display-controller@fd900000 { + compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; + interconnect-names = "mdp0-mem"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@fd922800 { + compatible = "qcom,msm8974-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@fd922e00 { + compatible = "qcom,msm8974-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922e00 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@fd923000 { + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd923000 0xd4>, + <0xfd923100 0x280>, + <0xfd923380 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + cci: cci@fda0c000 { + compatible = "qcom,msm8974-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfda0c000 0x1000>; + interrupts = ; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci_default>; + pinctrl-1 = <&cci_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gpu: adreno@fdb00000 { + compatible = "qcom,adreno-330.1", "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + clock-names = "core", "iface", "mem_iface"; + + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, + <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; + interconnect-names = "gfx-mem", "ocmem"; + + // iommus = <&gpu_iommu 0>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; + }; + }; + }; + + sram@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x180000>; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x100000>; + }; + }; + + remoteproc_adsp: remoteproc@fe200000 { + compatible = "qcom,msm8974-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + label = "lpass"; + }; + }; + + imem: sram@fe805000 { + compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modemtx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + modemtx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + video_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + wlan_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + vreg_boost: vreg-boost { + compatible = "regulator-fixed"; + + regulator-name = "vreg-boost"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + regulator-always-on; + regulator-boot-on; + + gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&boost_bypass_n_pin>; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts new file mode 100644 index 000000000000..f531d2679f6c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include +#include +#include + +/ { + model = "Fairphone 2"; + compatible = "fairphone,fp2", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + vcc-supply = <&pm8941_l18>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@41 { + compatible = "ilitek,ili2120"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&imem { + reboot-mode { + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio1", "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@7 { + reg = <7>; + color = ; + }; + + led@6 { + reg = <6>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; +}; + +&pronto { + status = "okay"; + + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; + vddpx-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + iris { + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; + + wcnss { + status = "okay"; + }; + }; +}; + +&remoteproc_adsp { + status = "okay"; + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + status = "okay"; + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&smbb { + usb-charge-current-limit = <1500000>; + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,fast-charge-safe-voltage = <4380000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4240000>; + qcom,minimum-input-voltage = <4450000>; +}; + +&tlmm { + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-pin-active-state { + wlan-pins { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + + drive-strength = <6>; + bias-pull-down; + }; + + bt-pins { + pins = "gpio35", "gpio43", "gpio44"; + function = "bt"; + + drive-strength = <2>; + bias-pull-down; + }; + + fm-pins { + pins = "gpio41", "gpio42"; + function = "fm"; + + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts new file mode 100644 index 000000000000..8d2a054d8fee --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include +#include + +/ { + model = "OnePlus One"; + compatible = "oneplus,bacon", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + qcom,msm-id = <194 0x10000>; + qcom,board-id = <8 0>; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>, <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 68 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + debounce-interval = <150>; + }; + }; +}; + +&blsp1_i2c1 { + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + power-supplies = <&bq24196_charger>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + rmi4-i2c-dev@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + syna,startup-delay-ms = <100>; + + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_default_state>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + /* + * Touchscreen size is 2040x1080, y-values between + * 1920-2040 are used for touchkey (menu, home & back). + * For now clip it off so we don't get touch events + * outside of the display area. + */ + syna,clip-y-high = <1920>; + }; + }; + + led-controller@36 { + compatible = "ti,lm3630a"; + reg = <0x36>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <80>; + }; + }; + + led-controller@68 { + compatible = "si-en,sn3193"; + reg = <0x68>; + + shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + label = "red:status"; + led-max-microamp = <17500>; + }; + + led@2 { + reg = <2>; + label = "green:status"; + led-max-microamp = <17500>; + }; + + led@3 { + reg = <3>; + label = "blue:status"; + led-max-microamp = <17500>; + }; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + + bq24196_charger: charger@6b { + compatible = "ti,bq24196"; + reg = <0x6b>; + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + omit-battery-class; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&gcc { + compatible = "qcom,gcc-msm8974pro-ac"; +}; + +&pm8941_coincell { + qcom,rset-ohms = <800>; + qcom,vset-millivolts = <3200>; + + status = "okay"; +}; + +&pm8941_gpios { + gpio_keys_default: gpio-keys-active-state { + pins = "gpio2", "gpio5"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; +}; + +&pm8941_vib { + status = "okay"; +}; + +&pronto { + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; + vddpx-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + status = "okay"; + + iris { + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; + + wcnss { + status = "okay"; + }; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <154000>; + + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-allow-set-load; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "okay"; +}; + +&tlmm { + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio68"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + touch_default_state: touch-default-state { + int-pins { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + reset-pins { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-pin-active-state { + wlan-pins { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + drive-strength = <6>; + bias-pull-down; + }; + + bt-pins { + pins = "gpio35", "gpio43", "gpio44"; + function = "bt"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&usb { + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + status = "okay"; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts new file mode 100644 index 000000000000..cfbcd521f74d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pma8084.dtsi" +#include +#include +#include + +/ { + model = "Samsung Galaxy S5"; + compatible = "samsung,klte", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + serial0 = &blsp1_uart1; + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_3; /* SDC2 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + key-home { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + i2c-gpio-touchkey { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_touchkey_pins>; + + touchkey@20 { + compatible = "cypress,tm2-touchkey"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_pin>; + + vcc-supply = <&max77826_ldo15>; + vdd-supply = <&pma8084_l19>; + + linux,keycodes = ; + }; + }; + + i2c-gpio-led { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_led_gpioex_pins>; + + i2c-gpio,delay-us = <2>; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + + gpio-controller; + #gpio-cells = <2>; + + vcc-supply = <&pma8084_s4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpioex_pin>; + + reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + }; + + led-controller@30 { + compatible = "panasonic,an30259a"; + reg = <0x30>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + }; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_panel: panel-regulator { + compatible = "regulator-fixed"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_en_pin>; + + regulator-name = "panel-vddr-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /delete-node/ vreg-boost; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&max77826_ldo13>; + vio-supply = <&pma8084_lvs2>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c6 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + }; +}; + +&blsp2_uart2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_pins_active>; + pinctrl-1 = <&blsp2_uart2_pins_sleep>; + + bluetooth { + compatible = "brcm,bcm43540-bt"; + max-speed = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&tlmm>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + }; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + panel: panel@0 { + reg = <0>; + compatible = "samsung,s6e3fa2"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_te_pin &panel_rst_pin>; + + iovdd-supply = <&pma8084_lvs4>; + vddr-supply = <&vreg_panel>; + + reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; + te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + + vddio-supply = <&pma8084_l12>; +}; + +&pma8084_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + touchkey_pin: touchkey-int-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + touch_pin: touchscreen-int-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + panel_en_pin: panel-en-state { + pins = "gpio14"; + function = "normal"; + bias-pull-up; + power-source = ; + qcom,drive-strength = ; + }; + + wlan_sleep_clk_pin: wlan-sleep-clk-state { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + qcom,drive-strength = ; + }; + + panel_rst_pin: panel-rst-state { + pins = "gpio17"; + function = "normal"; + bias-disable; + power-source = ; + qcom,drive-strength = ; + }; + + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio21"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; +}; + +&remoteproc_adsp { + status = "okay"; + cx-supply = <&pma8084_s2>; +}; + +&remoteproc_mss { + status = "okay"; + cx-supply = <&pma8084_s2>; + mss-supply = <&pma8084_s6>; + mx-supply = <&pma8084_s1>; + pll-supply = <&pma8084_l12>; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pma8084-regulators"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pma8084_s4>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + interrupt-parent = <&tlmm>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; + }; +}; + +&sdhc_3 { + status = "okay"; + max-frequency = <100000000>; + vmmc-supply = <&pma8084_l21>; + vqmmc-supply = <&pma8084_l13>; + + /* + * cd-gpio is intentionally disabled. If enabled, an SD card + * present during boot is not initialized correctly. Without + * cd-gpios the driver resorts to polling, so hotplug works. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; + /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ +}; + +&tlmm { + /* This seems suspicious, but somebody with this device should look into it. */ + blsp2_uart2_pins_active: blsp2-uart2-pins-active-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_uart8"; + drive-strength = <8>; + bias-disable; + }; + + blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + bt_pins: bt-pins-state { + hostwake-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <16>; + input-enable; + }; + + devwake-pins { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + }; + }; + + sdc1_on: sdhc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + sdc3_on: sdc3-on-state { + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + sdhc3_cd_pin: sdc3-cd-on-state { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdc2_on: sdhc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + i2c_touchkey_pins: i2c-touchkey-state { + pins = "gpio95", "gpio96"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + i2c_led_gpioex_pins: i2c-led-gpioex-state { + pins = "gpio120", "gpio121"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + + gpioex_pin: gpioex-state { + pins = "gpio145"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + wifi_pin: wifi-state { + pins = "gpio92"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + + panel_te_pin: panel-state { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts new file mode 100644 index 000000000000..2396253f953a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -0,0 +1,675 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include +#include +#include + +/ { + model = "Sony Xperia Z2 Tablet"; + compatible = "sony,xperia-castor", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "tablet"; + + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; + + vreg_bl_vddio: lcd-backlight-vddio { + compatible = "regulator-fixed"; + regulator-name = "vreg_bl_vddio"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + gpio = <&tlmm 69 0>; + enable-active-high; + + vin-supply = <&pm8941_s3>; + startup-delay-us = <70000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_backlight_en_pin_a>; + }; + + vreg_vsp: lcd-dcdc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_vsp"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + + gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_dcdc_en_pin_a>; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c2 { + status = "okay"; + clock-frequency = <355000>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupt-parent = <&tlmm>; + interrupts = <86 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <100>; + + rmi-f01@1 { + reg = <0x1>; + syna,nosleep = <1>; + }; + + rmi-f11@11 { + reg = <0x11>; + syna,f11-flip-x = <1>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + lp8566_wled: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + power-supply = <&vreg_bl_vddio>; + + bl-name = "backlight"; + dev-ctrl = /bits/ 8 <0x05>; + init-brt = /bits/ 8 <0x3f>; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + rom-a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + rom-a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x02>; + }; + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x04>; + }; + rom-a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf7>; + }; + rom-a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0x80>; + }; + rom-aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x0f>; + }; + rom-aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; +}; + +&blsp2_uart1 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>; + + host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; + }; +}; + +&pm8941_coincell { + status = "okay"; + + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + bt_reg_on_pin: bt-reg-on-state { + pins = "gpio16"; + function = "normal"; + + output-low; + power-source = ; + }; + + wlan_sleep_clk_pin: wl-sleep-clk-state { + pins = "gpio17"; + function = "func2"; + + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active-state { + pins = "gpio18"; + function = "normal"; + + bias-disable; + power-source = ; + }; + + lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { + pins = "gpio20"; + function = "normal"; + + bias-disable; + power-source = ; + input-disable; + output-low; + }; + +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = ; + }; + + led@6 { + reg = <6>; + color = ; + }; + + led@7 { + reg = <7>; + color = ; + }; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <154000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <500000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc3_on>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + usb-charge-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; +}; + +&tlmm { + lcd_backlight_en_pin_a: lcd-backlight-vddio-state { + pins = "gpio69"; + function = "gpio"; + drive-strength = <10>; + output-low; + bias-disable; + }; + + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + + cd-pins { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc3_on: sdc3-on-state { + clk-pins { + pins = "gpio40"; + function = "sdc3"; + drive-strength = <10>; + bias-disable; + }; + + cmd-pins { + pins = "gpio39"; + function = "sdc3"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "gpio35", "gpio36", "gpio37", "gpio38"; + function = "sdc3"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + ts_int_pin: ts-int-pin-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + bt_host_wake_pin: bt-host-wake-state { + pins = "gpio95"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + bt_dev_wake_pin: bt-dev-wake-state { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi new file mode 100644 index 000000000000..58df6e75ab6d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" + +&gcc { + compatible = "qcom,gcc-msm8974pro"; +}; + +&gpu { + compatible = "qcom,adreno-330.2", "qcom,adreno"; +}; + +&sdhc_1 { + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, + <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; + clock-names = "iface", "core", "xo", "cal", "sleep"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi new file mode 100644 index 000000000000..3b8ad28cecb0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include +#include + +/ { + thermal-zones { + pm8226-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8226_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm8226_0: pm8226@0 { + compatible = "qcom,pm8226", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + + pm8226_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + smbb: charger@1000 { + compatible = "qcom,pm8226-charger"; + reg = <0x1000>; + interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "chg-done", + "chg-fast", + "chg-trkl", + "bat-temp-ok", + "bat-present", + "chg-gone", + "usb-valid", + "dc-valid"; + + chg_otg: otg-vbus { }; + }; + + pm8226_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8226_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8226_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@7 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + adc-chan@8 { + reg = ; + label = "die_temp"; + }; + adc-chan@9 { + reg = ; + label = "ref_625mv"; + }; + adc-chan@a { + reg = ; + label = "ref_1250mv"; + }; + adc-chan@e { + reg = ; + }; + adc-chan@f { + reg = ; + }; + }; + + pm8226_iadc: adc@3600 { + compatible = "qcom,pm8226-iadc", "qcom,spmi-iadc"; + reg = <0x3600>; + interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8226_mpps: mpps@a000 { + compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8226_mpps 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8226_gpios: gpio@c000 { + compatible = "qcom,pm8226-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8226_gpios 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8226_1: pm8226@1 { + compatible = "qcom,pm8226", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8226_spmi_regulators: regulators { + compatible = "qcom,pm8226-regulators"; + }; + + pm8226_vib: vibrator@c000 { + compatible = "qcom,pm8916-vib"; + reg = <0xc000>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi new file mode 100644 index 000000000000..3bf2ce5c86a6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + + +/ { + thermal-zones { + pm8841-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8841_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <140000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + + pm8841_0: pm8841@4 { + compatible = "qcom,pm8841", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8841_mpps: mpps@a000 { + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpps 0 0 4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8841_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8841_1: pm8841@5 { + compatible = "qcom,pm8841", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi new file mode 100644 index 000000000000..b3e246bacd78 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + + +/ { + thermal-zones { + pm8941-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8941_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + + pm8941_0: pm8941@0 { + compatible = "qcom,pm8941", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, + <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + usb_id: usb-detect@900 { + compatible = "qcom,pm8941-misc"; + reg = <0x900>; + interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_id"; + }; + + smbb: charger@1000 { + compatible = "qcom,pm8941-charger"; + reg = <0x1000>; + interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "chg-done", + "chg-fast", + "chg-trkl", + "bat-temp-ok", + "bat-present", + "chg-gone", + "usb-valid", + "dc-valid"; + + usb-otg-in-supply = <&pm8941_5vs1>; + + chg_otg: otg-vbus { }; + }; + + pm8941_gpios: gpio@c000 { + compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8941_gpios 0 0 36>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + boost_bypass_n_pin: boost-bypass-state { + pins = "gpio21"; + function = "normal"; + }; + }; + + pm8941_mpps: mpps@a000 { + compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8941_mpps 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8941_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8941_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8941_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + + adc-chan@6 { + reg = ; + }; + + adc-chan@8 { + reg = ; + }; + + adc-chan@9 { + reg = ; + }; + + adc-chan@a { + reg = ; + }; + + adc-chan@e { + reg = ; + }; + + adc-chan@f { + reg = ; + }; + + adc-chan@30 { + reg = ; + }; + }; + + pm8941_iadc: adc@3600 { + compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc"; + reg = <0x3600>; + interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + qcom,external-resistor-micro-ohms = <10000>; + }; + + pm8941_coincell: charger@2800 { + compatible = "qcom,pm8941-coincell"; + reg = <0x2800>; + status = "disabled"; + }; + }; + + pm8941_1: pm8941@1 { + compatible = "qcom,pm8941", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8941_lpg: pwm { + compatible = "qcom,pm8941-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + + pm8941_vib: vibrator@c000 { + compatible = "qcom,pm8916-vib"; + reg = <0xc000>; + status = "disabled"; + }; + + pm8941_wled: wled@d800 { + compatible = "qcom,pm8941-wled"; + reg = <0xd800>; + label = "backlight"; + + status = "disabled"; + }; + + regulators { + compatible = "qcom,pm8941-regulators"; + interrupts = <0x1 0x83 0x2 0>, <0x1 0x84 0x2 0>; + interrupt-names = "ocp-5vs1", "ocp-5vs2"; + vin_5vs-supply = <&pm8941_5v>; + + pm8941_5v: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <500>; + }; + + pm8941_5vs1: 5vs1 { + regulator-enable-ramp-delay = <1000>; + regulator-pull-down; + regulator-over-current-protection; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,vs-soft-start-strength = <0>; + regulator-initial-mode = <1>; + }; + + pm8941_5vs2: 5vs2 { + regulator-enable-ramp-delay = <1000>; + regulator-pull-down; + regulator-over-current-protection; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,vs-soft-start-strength = <0>; + regulator-initial-mode = <1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi new file mode 100644 index 000000000000..2dd4c6aa71c9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + +&spmi_bus { + + pma8084_0: pma8084@0 { + compatible = "qcom,pma8084", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, + <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + pma8084_gpios: gpio@c000 { + compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pma8084_gpios 0 0 22>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pma8084_mpps: mpps@a000 { + compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pma8084_mpps 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pma8084_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + io-channels = <&pma8084_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + }; + + pma8084_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@8 { + reg = ; + }; + + adc-chan@9 { + reg = ; + }; + + adc-chan@a { + reg = ; + }; + + adc-chan@c { + reg = ; + }; + + adc-chan@e { + reg = ; + }; + + adc-chan@f { + reg = ; + }; + }; + }; + + pma8084_1: pma8084@1 { + compatible = "qcom,pma8084", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi new file mode 100644 index 000000000000..e1b869480bbd --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Limited + */ + +#include +#include +#include + +&spmi_bus { + pmic@8 { + compatible = "qcom,pmx55", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmx55_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmx55_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmx55_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + + chg-temp@9 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "chg_temp"; + }; + }; + + pmx55_gpios: gpio@c000 { + compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pmx55_gpios 0 0 11>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@9 { + compatible = "qcom,pmx55", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi new file mode 100644 index 000000000000..1c7fdf59c1f5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + pmic@1 { + compatible = "qcom,pmx65", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_temp: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_gpios: gpio@8800 { + compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmx65_gpios 0 0 16>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts new file mode 100644 index 000000000000..7e97ad5803d8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +/dts-v1/; + +#include "qcom-sdx55.dtsi" +#include +#include +#include "qcom-pmx55.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX55 MTP"; + compatible = "qcom,sdx55-mtp", "qcom,sdx55"; + qcom,board-id = <0x5010008 0x0>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_debug_mem: memory@8ef00000 { + no-map; + reg = <0x8ef00000 0x800000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90c00000 { + no-map; + reg = <0x90c00000 0xd400000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx55-bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s7e_mx_0p752: pmx55-s7e { + compatible = "regulator-fixed"; + regulator-name = "vreg_s7e_mx_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmx55-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-l1-l2-supply = <&vreg_s2e_1p224>; + vdd-l3-l9-supply = <&vreg_s3e_0p824>; + vdd-l4-l12-supply = <&vreg_s4e_1p904>; + vdd-l5-l6-supply = <&vreg_s4e_1p904>; + vdd-l7-l8-supply = <&vreg_s3e_0p824>; + vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l14-supply = <&vreg_s7e_mx_0p752>; + vdd-l15-supply = <&vreg_s2e_1p224>; + vdd-l16-supply = <&vreg_s4e_1p904>; + + vreg_s2e_1p224: smps2 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3e_0p824: smps3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s4e_1p904: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1960000>; + }; + + vreg_l1e_bb_1p2: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l4e_bb_0p875: ldo4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <872000>; + regulator-initial-mode = ; + }; + + vreg_l5e_bb_1p7: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_3p1: ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; + +&remoteproc_mpss { + memory-region = <&mpss_adsp_mem>; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + vdda33-supply = <&vreg_l10e_3p1>; + vdda18-supply = <&vreg_l5e_bb_1p7>; +}; + +&usb_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l4e_bb_0p875>; + vdda-pll-supply = <&vreg_l1e_bb_1p2>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts new file mode 100644 index 000000000000..51058b065279 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include "qcom-sdx55.dtsi" +#include "qcom-pmx55.dtsi" + +/ { + model = "Thundercomm T55 Development Kit"; + compatible = "qcom,sdx55-t55", "qcom,sdx55"; + qcom,board-id = <0xb010008 0x4>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_debug_mem: memory@8ef00000 { + no-map; + reg = <0x8ef00000 0x800000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0xf800000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx55-bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s7e_mx_0p752: pmx55-s7e { + compatible = "regulator-fixed"; + regulator-name = "vreg_s7e_mx_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + + vin-supply = <&vph_pwr>; + }; + + vreg_sd_vdd: sd-vdd { + compatible = "regulator-fixed"; + regulator-name = "vreg_sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + vin-supply = <&vreg_vddpx_2>; + }; + + vreg_vddpx_2: vddpx-2 { + compatible = "regulator-gpio"; + regulator-name = "vreg_vddpx_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmx55-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-l1-l2-supply = <&vreg_s2e_1p224>; + vdd-l3-l9-supply = <&vreg_s3e_0p824>; + vdd-l4-l12-supply = <&vreg_s4e_1p904>; + vdd-l5-l6-supply = <&vreg_s4e_1p904>; + vdd-l7-l8-supply = <&vreg_s3e_0p824>; + vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l14-supply = <&vreg_s7e_mx_0p752>; + vdd-l15-supply = <&vreg_s2e_1p224>; + vdd-l16-supply = <&vreg_s4e_1p904>; + + vreg_s2e_1p224: smps2 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3e_0p824: smps3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s4e_1p904: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1960000>; + }; + + vreg_l1e_bb_1p2: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l4e_bb_0p875: ldo4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <872000>; + regulator-initial-mode = ; + }; + + vreg_l5e_bb_1p7: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_3p1: ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; +}; + +&pcie_rc { + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* efs2 partition is secured */ + secure-regions = /bits/ 64 <0x500000 0xb00000>; + }; +}; + +&remoteproc_mpss { + memory-region = <&mpss_adsp_mem>; + status = "okay"; +}; + +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&usb_hsphy { + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + vdda33-supply = <&vreg_l10e_3p1>; + vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l4e_bb_0p875>; + vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts new file mode 100644 index 000000000000..8fadc6e70692 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include "qcom-sdx55.dtsi" +#include "qcom-pmx55.dtsi" + +/ { + model = "Telit FN980 TLB"; + compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55"; + qcom,board-id = <0xb010008 0x0>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_debug_mem: memory@8ef00000 { + no-map; + reg = <0x8ef00000 0x800000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0xf800000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx55-bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s7e_mx_0p752: pmx55-s7e { + compatible = "regulator-fixed"; + regulator-name = "vreg_s7e_mx_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + + vin-supply = <&vph_pwr>; + }; + + vreg_sd_vdd: sd-vdd { + compatible = "regulator-fixed"; + regulator-name = "vreg_sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + vin-supply = <&vreg_vddpx_2>; + }; + + vreg_vddpx_2: vddpx-2 { + compatible = "regulator-gpio"; + regulator-name = "vreg_vddpx_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmx55-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-l1-l2-supply = <&vreg_s2e_1p224>; + vdd-l3-l9-supply = <&vreg_s3e_0p824>; + vdd-l4-l12-supply = <&vreg_s4e_1p904>; + vdd-l5-l6-supply = <&vreg_s4e_1p904>; + vdd-l7-l8-supply = <&vreg_s3e_0p824>; + vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l14-supply = <&vreg_s7e_mx_0p752>; + vdd-l15-supply = <&vreg_s2e_1p224>; + vdd-l16-supply = <&vreg_s4e_1p904>; + + vreg_s2e_1p224: smps2 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3e_0p824: smps3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s4e_1p904: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1960000>; + }; + + vreg_l1e_bb_1p2: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l4e_bb_0p875: ldo4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <872000>; + regulator-initial-mode = ; + }; + + vreg_l5e_bb_1p7: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_3p1: ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; +}; + +&pcie_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + +&remoteproc_mpss { + memory-region = <&mpss_adsp_mem>; + status = "okay"; +}; + +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&usb_hsphy { + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + vdda33-supply = <&vreg_l10e_3p1>; + vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l4e_bb_0p875>; + vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi new file mode 100644 index 000000000000..df3cd9c4ffb9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -0,0 +1,881 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX55 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX55_CX>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdx55", "qcom,scm"; + }; + }; + + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hyp_mem: memory@8fc00000 { + no-map; + reg = <0x8fc00000 0x80000>; + }; + + ac_db_mem: memory@8fc80000 { + no-map; + reg = <0x8fc80000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + sbl_mem: memory@8fd00000 { + no-map; + reg = <0x8fd00000 0x100000>; + }; + + aop_image: memory@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + aop_cmd_db: memory@8fe20000 { + compatible = "qcom,cmd-db"; + reg = <0x8fe20000 0x20000>; + no-map; + }; + + smem_mem: memory@8fe40000 { + no-map; + reg = <0x8fe40000 0xc0000>; + }; + + tz_mem: memory@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx55"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc 30>, + <&gcc 9>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + usb_hsphy: phy@ff4000 { + compatible = "qcom,sdx55-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0x00ff4000 0x114>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_BCR>; + }; + + usb_qmpphy: phy@ff6000 { + compatible = "qcom,sdx55-qmp-usb3-uni-phy"; + reg = <0x00ff6000 0x1c0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3PHY_PHY_BCR>, + <&gcc GCC_USB3_PHY_BCR>; + reset-names = "phy", "common"; + + usb_ssphy: phy@ff6200 { + reg = <0x00ff6200 0x170>, + <0x00ff6400 0x200>, + <0x00ff6800 0x800>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + mc_virt: interconnect@1100000 { + compatible = "qcom,sdx55-mc-virt"; + reg = <0x01100000 0x400000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mem_noc: interconnect@9680000 { + compatible = "qcom,sdx55-mem-noc"; + reg = <0x09680000 0x40000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@162c000 { + compatible = "qcom,sdx55-system-noc"; + reg = <0x0162c000 0x31200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", + "doorbell"; + + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "pcie-mem"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + + pcie_phy: phy@1c07000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c07000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie_lane: lanes@1c06000 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + + ipa: ipa@1e40000 { + compatible = "qcom,sdx55-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x1e40000 0x7000>, + <0x1e50000 0x4b20>, + <0x1e04000 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, + <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "qcom,sdx55-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + + sdhc_1: mmc@8804000 { + compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; + status = "disabled"; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SDX55_CX>, + <&rpmhpd SDX55_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs 15>; + }; + }; + + usb: usb@a6f8800 { + compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; + reg = <0x0a6f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_GDSC>; + + resets = <&gcc GCC_USB30_BCR>; + + usb_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x1a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_hsphy>, <&usb_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx55-pdc", "qcom,pdc"; + reg = <0x0b210000 0x30000>; + qcom,pdc-ranges = <0 179 52>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0c440000 0x0000d00>, + <0x0c600000 0x2000000>, + <0x0e600000 0x0100000>, + <0x0e700000 0x00a0000>, + <0x0c40a000 0x0000700>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx55-pinctrl"; + reg = <0xf100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 108>; + }; + + sram@1468f000 { + compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; + reg = <0x1468f000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x1468f000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0x200>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + + watchdog@17817000 { + compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; + reg = <0x17817000 0x1000>; + clocks = <&sleep_clk>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17830000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , , + , ; + + rpmhcc: clock-controller { + compatible = "qcom,sdx55-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sdx55-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts new file mode 100644 index 000000000000..02d8d6e241ae --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "qcom-sdx65.dtsi" +#include +#include +#include +#include "qcom-pmx65.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX65 MTP"; + compatible = "qcom,sdx65-mtp", "qcom,sdx65"; + qcom,board-id = <0x2010008 0x302>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_dsm: memory@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0x10000000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx65_bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmx65-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-supply = <&vreg_s2b_1p224>; + vdd-l2-l18-supply = <&vreg_s2b_1p224>; + vdd-l3-supply = <&vreg_s8b_0p824>; + vdd-l4-supply = <&vreg_s7b_0p936>; + vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>; + vdd-l7-supply = <&vreg_s3b_0p776>; + vdd-l8-l9-supply = <&vreg_s8b_0p824>; + vdd-l10-supply = <&vreg_bob_3p3>; + vdd-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l12-supply = <&vreg_s2b_1p224>; + vdd-l14-supply = <&vreg_s3b_0p776>; + vdd-l15-supply = <&vreg_s2b_1p224>; + vdd-l17-supply = <&vreg_s8b_0p824>; + vdd-l19-supply = <&vreg_s3b_0p776>; + vdd-l20-supply = <&vreg_s7b_0p936>; + vdd-l21-supply = <&vreg_s7b_0p936>; + + vreg_s2b_1p224: smps2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3b_0p776: smps3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s4b_1p824: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s7b_0p936: smps7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s8b_0p824: smps8 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1300000>; + }; + + vreg_l1b_1p2: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + vreg_l4b_0p88: ldo4 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l5b_1p8: ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10b_3p08: ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + regulator-initial-mode = ; + }; + + ldo17 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + ldo19 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + ldo20 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + ldo21 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + +&pcie_ep { + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l1b_1p2>; + vdda-pll-supply = <&vreg_l4b_0p88>; + + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + +&remoteproc_mpss { + memory-region = <&mpss_adsp_mem>; + status = "okay"; +}; + +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_hsphy { + vdda-pll-supply = <&vreg_l4b_0p88>; + vdda33-supply = <&vreg_l10b_3p08>; + vdda18-supply = <&vreg_l5b_1p8>; + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l4b_0p88>; + vdda-pll-supply = <&vreg_l1b_1p2>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi new file mode 100644 index 000000000000..1a3583029a64 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -0,0 +1,811 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX65 SoC device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX65_CX_AO>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdx65", "qcom,scm"; + }; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sdx65-mc-virt"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tz_heap_mem: memory@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + hyp_mem: memory@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + access_control_mem: memory@8fd80000 { + no-map; + reg = <0x8fd80000 0x80000>; + }; + + aop_mem: memory@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + smem_mem: memory@8fe20000 { + compatible = "qcom,smem"; + reg = <0x8fe20000 0xc0000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + cmd_db: reserved-memory@8fee0000 { + compatible = "qcom,cmd-db"; + reg = <0x8fee0000 0x20000>; + no-map; + }; + + tz_mem: memory@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + + llcc_tcm_mem: memory@15800000 { + no-map; + reg = <0x15800000 0x800000>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x00100000 0x001f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + usb_hsphy: phy@ff4000 { + compatible = "qcom,sdx65-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0xff4000 0x120>; + #phy-cells = <0>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_BCR>; + status = "disabled"; + }; + + usb_qmpphy: phy@ff6000 { + compatible = "qcom,sdx65-qmp-usb3-uni-phy"; + reg = <0x00ff6000 0x1c8>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3PHY_PHY_BCR>, + <&gcc GCC_USB3_PHY_BCR>; + reset-names = "phy", "common"; + + status = "disabled"; + + usb_ssphy: phy@ff6200 { + reg = <0x00ff6e00 0x160>, + <0x00ff7000 0x1ec>, + <0x00ff6200 0x1e00>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdx65-system-noc"; + reg = <0x01620000 0x31200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fcb000 { + compatible = "qcom,sdx65-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + + ipa: ipa@3f40000 { + compatible = "qcom,sdx65-ipa"; + + reg = <0x03f40000 0x10000>, + <0x03f50000 0x5000>, + <0x03e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; + interconnect-names = "memory", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SDX65_CX>, + <&rpmhpd SDX65_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs 15>; + }; + }; + + sdhc_1: mmc@8804000 { + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + mem_noc: interconnect@9680000 { + compatible = "qcom,sdx65-mem-noc"; + reg = <0x09680000 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + usb: usb@a6f8800 { + compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; + reg = <0x0a6f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 18 IRQ_TYPE_EDGE_BOTH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_GDSC>; + + resets = <&gcc GCC_USB30_BCR>; + + status = "disabled"; + + usb_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x1a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_hsphy>, <&usb_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0xf100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx65-pdc", "qcom,pdc"; + reg = <0xb210000 0x10000>; + qcom,pdc-ranges = <0 147 52>, <52 266 32>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + sram@1468f000 { + compatible = "qcom,sdx65-imem", "syscon", "simple-mfd"; + reg = <0x1468f000 0x1000>; + ranges = <0x0 0x1468f000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + + watchdog@17817000 { + compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; + reg = <0x17817000 0x1000>; + clocks = <&sleep_clk>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17830000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, + <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , + , + , + ; + + rpmhcc: clock-controller { + compatible = "qcom,sdx65-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sdx65-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 12 0xf08>, + <1 10 0xf08>, + <1 11 0xf08>; + clock-frequency = <19200000>; + }; +}; diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts deleted file mode 100644 index 1e8447176b10..000000000000 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Genmai board - * - * Copyright (C) 2013-14 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - */ - -/dts-v1/; -#include "r7s72100.dtsi" -#include -#include - -/ { - model = "Genmai"; - compatible = "renesas,genmai", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x08000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - status = "okay"; - compatible = "gpio-leds"; - - led1 { - gpios = <&port4 10 GPIO_ACTIVE_LOW>; - }; - - led2 { - gpios = <&port4 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - - scif2_pins: serial2 { - /* P3_0 as TxD2; P3_2 as RxD2 */ - pinmux = , ; - }; - - i2c2_pins: i2c2 { - /* RIIC2: P1_4 as SCL, P1_5 as SDA */ - pinmux = , ; - }; - - ether_pins: ether { - /* Ethernet on Ports 1,2,3,5 */ - pinmux = ,/* P1_14 = ET_COL */ - , /* P5_9 = ET_MDC */ - , /* P3_3 = ET_MDIO */ - , /* P3_4 = ET_RXCLK */ - , /* P3_5 = ET_RXER */ - , /* P3_6 = ET_RXDV */ - , /* P2_0 = ET_TXCLK */ - , /* P2_1 = ET_TXER */ - , /* P2_2 = ET_TXEN */ - , /* P2_3 = ET_CRS */ - , /* P2_4 = ET_TXD0 */ - , /* P2_5 = ET_TXD1 */ - , /* P2_6 = ET_TXD2 */ - , /* P2_7 = ET_TXD3 */ - , /* P2_8 = ET_RXD0 */ - , /* P2_9 = ET_RXD1 */ - ,/* P2_10 = ET_RXD2 */ - ;/* P2_11 = ET_RXD3 */ - }; -}; - -&extal_clk { - clock-frequency = <13330000>; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&rtc_x1_clk { - clock-frequency = <32768>; -}; - -&mtu2 { - status = "okay"; -}; - -ðer { - pinctrl-names = "default"; - pinctrl-0 = <ðer_pins>; - - status = "okay"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-idb824.2814", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - eeprom@50 { - compatible = "renesas,r1ex24128", "atmel,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&rtc { - status = "okay"; -}; - -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - - status = "okay"; -}; - -&spi4 { - status = "okay"; - - codec: codec@0 { - compatible = "wlf,wm8978"; - reg = <0>; - spi-max-frequency = <5000000>; - }; -}; diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts deleted file mode 100644 index 105f9c71f9fd..000000000000 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach board - * - * Copyright (C) 2017 Jacopo Mondi - * Copyright (C) 2016 Renesas Electronics - */ - -/dts-v1/; -#include "r7s72100.dtsi" -#include -#include - -/ { - model = "GR-Peach"; - compatible = "renesas,gr-peach", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x00a00000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - flash@18000000 { - compatible = "mtd-rom"; - probe-type = "map_rom"; - reg = <0x18000000 0x00800000>; - bank-width = <4>; - device-width = <1>; - - clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; - power-domains = <&cpg_clocks>; - - #address-cells = <1>; - #size-cells = <1>; - - rootfs@600000 { - label = "rootfs"; - reg = <0x00600000 0x00200000>; - }; - }; - - leds { - status = "okay"; - compatible = "gpio-leds"; - - led1 { - gpios = <&port6 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - scif2_pins: serial2 { - /* P6_2 as RxD2; P6_3 as TxD2 */ - pinmux = , ; - }; - - ether_pins: ether { - /* Ethernet on Ports 1,3,5,10 */ - pinmux = , /* P1_14 = ET_COL */ - , /* P3_0 = ET_TXCLK */ - , /* P3_3 = ET_MDIO */ - , /* P3_4 = ET_RXCLK */ - , /* P3_5 = ET_RXER */ - , /* P3_6 = ET_RXDV */ - , /* P5_9 = ET_MDC */ - , /* P10_1 = ET_TXER */ - , /* P10_2 = ET_TXEN */ - , /* P10_3 = ET_CRS */ - , /* P10_4 = ET_TXD0 */ - , /* P10_5 = ET_TXD1 */ - , /* P10_6 = ET_TXD2 */ - , /* P10_7 = ET_TXD3 */ - , /* P10_8 = ET_RXD0 */ - , /* P10_9 = ET_RXD1 */ - ,/* P10_10 = ET_RXD2 */ - ;/* P10_11 = ET_RXD3 */ - }; -}; - -&extal_clk { - clock-frequency = <13333000>; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&mtu2 { - status = "okay"; -}; - -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; -}; - -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - - status = "okay"; -}; - -ðer { - pinctrl-names = "default"; - pinctrl-0 = <ðer_pins>; - - status = "okay"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.c0f0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - - reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <5>; - }; -}; diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts deleted file mode 100644 index 1c5acf694407..000000000000 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/A1H RSK board - * - * Copyright (C) 2016 Renesas Electronics - */ - -/dts-v1/; -#include "r7s72100.dtsi" -#include -#include -#include - -/ { - model = "RSKRZA1"; - compatible = "renesas,rskrza1", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x02000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - key-1 { - interrupt-parent = <&irqc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW1"; - wakeup-source; - }; - - key-2 { - interrupt-parent = <&irqc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW2"; - wakeup-source; - }; - - key-3 { - interrupt-parent = <&irqc>; - interrupts = <5 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&port7 1 GPIO_ACTIVE_LOW>; - }; - - led1 { - gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>; - }; - - led2 { - gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>; - }; - - led3 { - gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&extal_clk { - clock-frequency = <13330000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - - clock-frequency = <400000>; - - io_expander1: gpio@20 { - compatible = "onnn,cat9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - io_expander2: gpio@21 { - compatible = "onnn,cat9554"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "renesas,r1ex24016", "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&rtc_x1_clk { - clock-frequency = <32768>; -}; - -&pinctrl { - /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */ - i2c3_pins: i2c3 { - pinmux = , /* RIIC3SCL */ - ; /* RIIC3SDA */ - }; - - keyboard_pins: keyboard { - pinmux = , /* IRQ3 */ - , /* IRQ2 */ - ; /* IRQ5 */ - }; - - /* Serial Console */ - scif2_pins: serial2 { - pinmux = , /* TxD2 */ - ; /* RxD2 */ - }; - - /* Ethernet */ - ether_pins: ether { - /* Ethernet on Ports 1,2,3,5 */ - pinmux = , /* ET_COL */ - , /* ET_MDC */ - , /* ET_MDIO */ - , /* ET_RXCLK */ - , /* ET_RXER */ - , /* ET_RXDV */ - , /* ET_TXCLK */ - , /* ET_TXER */ - , /* ET_TXEN */ - , /* ET_CRS */ - , /* ET_TXD0 */ - , /* ET_TXD1 */ - , /* ET_TXD2 */ - , /* ET_TXD3 */ - , /* ET_RXD0 */ - , /* ET_RXD1 */ - , /* ET_RXD2 */ - ; /* ET_RXD3 */ - }; - - /* SDHI ch1 on CN1 */ - sdhi1_pins: sdhi1 { - pinmux = , /* SD_CD_1 */ - , /* SD_WP_1 */ - , /* SD_D1_1 */ - , /* SD_D0_1 */ - , /* SD_CLK_1 */ - , /* SD_CMD_1 */ - , /* SD_D3_1 */ - ; /* SD_D2_1 */ - }; -}; - -&mtu2 { - status = "okay"; -}; - -ðer { - pinctrl-names = "default"; - pinctrl-0 = <ðer_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-idb824.2814", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&sdhi1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - bus-width = <4>; - status = "okay"; -}; - -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi deleted file mode 100644 index b07b71307f24..000000000000 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r7s72100 SoC - * - * Copyright (C) 2013-14 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - */ - -#include -#include -#include - -/ { - compatible = "renesas,r7s72100"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - /* Fixed factor clocks */ - b_clk: b { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <400000000>; - clocks = <&cpg_clocks R7S72100_CLK_I>; - next-level-cache = <&L2>; - }; - }; - - /* External clocks */ - extal_clk: extal { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; - - p0_clk: p0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <12>; - }; - - p1_clk: p1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <6>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; - }; - - rtc_x1_clk: rtc_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 32678 */ - clock-frequency = <0>; - }; - - rtc_x3_clk: rtc_x3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 4000000 */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - L2: cache-controller@3ffff000 { - compatible = "arm,pl310-cache"; - reg = <0x3ffff000 0x1000>; - interrupts = ; - arm,early-bresp-disable; - arm,full-line-zero-disable; - cache-unified; - cache-level = <2>; - }; - - scif0: serial@e8007000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@e8007800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@e8008000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@e8008800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@e8009000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@e8009800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif6: serial@e800a000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif7: serial@e800a800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI0>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e800d000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI1>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@e800d800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI2>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@e800e000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI3>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@e800e800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI4>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usbhs0: usb@e8010000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8010000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB0>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - usbhs1: usb@e8207000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8207000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB1>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - mmcif: mmc@e804c800 { - compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; - reg = <0xe804c800 0x80>; - interrupts = , - , - ; - clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; - power-domains = <&cpg_clocks>; - reg-io-width = <4>; - bus-width = <8>; - status = "disabled"; - }; - - sdhi0: mmc@e804e000 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e000 0x100>; - interrupts = , - , - ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, - <&mstp12_clks R7S72100_CLK_SDHI01>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: mmc@e804e800 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e800 0x100>; - interrupts = , - , - ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, - <&mstp12_clks R7S72100_CLK_SDHI11>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - gic: interrupt-controller@e8201000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; - - ether: ethernet@e8203000 { - compatible = "renesas,ether-r7s72100"; - reg = <0xe8203000 0x800>, - <0xe8204800 0x200>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ceu: camera@e8210000 { - reg = <0xe8210000 0x3000>; - compatible = "renesas,r7s72100-ceu"; - interrupts = ; - clocks = <&mstp6_clks R7S72100_CLK_CEU>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - wdt: watchdog@fcfe0000 { - compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; - reg = <0xfcfe0000 0x6>; - interrupts = ; - clocks = <&p0_clk>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - #power-domain-cells = <0>; - }; - - /* MSTP clocks */ - mstp3_clks: mstp3_clks@fcfe0420 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0420 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "mtu2"; - }; - - mstp4_clks: mstp4_clks@fcfe0424 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0424 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 - R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 - >; - clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; - }; - - mstp5_clks: mstp5_clks@fcfe0428 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0428 4>; - clocks = <&p0_clk>, <&p0_clk>; - clock-indices = ; - clock-output-names = "ostm0", "ostm1"; - }; - - mstp6_clks: mstp6_clks@fcfe042c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe042c 4>; - clocks = <&b_clk>, <&p0_clk>; - clock-indices = ; - clock-output-names = "ceu", "rtc"; - }; - - mstp7_clks: mstp7_clks@fcfe0430 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0430 4>; - clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = ; - clock-output-names = "ether", "usb0", "usb1"; - }; - - mstp8_clks: mstp8_clks@fcfe0434 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0434 4>; - clocks = <&p1_clk>; - clock-indices = ; - clock-output-names = "mmcif"; - }; - - mstp9_clks: mstp9_clks@fcfe0438 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0438 4>; - clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; - clock-indices = < - R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 - R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 - >; - clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; - }; - - mstp10_clks: mstp10_clks@fcfe043c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe043c 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>; - clock-indices = < - R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 - R7S72100_CLK_SPI4 - >; - clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; - }; - mstp12_clks: mstp12_clks@fcfe0444 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0444 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 - R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 - >; - clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; - }; - - pinctrl: pinctrl@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; - - port0: gpio-0 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 6>; - }; - - port1: gpio-1 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - port2: gpio-2 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - port4: gpio-4 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - port5: gpio-5 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 80 11>; - }; - - port6: gpio-6 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - port7: gpio-7 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - port8: gpio-8 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - port9: gpio-9 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 144 8>; - }; - - port10: gpio-10 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 160 16>; - }; - - port11: gpio-11 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 176 16>; - }; - }; - - ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - ostm1: timer@fcfec400 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec400 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c0: i2c@fcfee000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&mstp9_clks R7S72100_CLK_I2C0>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c1: i2c@fcfee400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee400 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&mstp9_clks R7S72100_CLK_I2C1>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c2: i2c@fcfee800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee800 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&mstp9_clks R7S72100_CLK_I2C2>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c3: i2c@fcfeec00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfeec00 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&mstp9_clks R7S72100_CLK_I2C3>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - irqc: interrupt-controller@fcfef800 { - compatible = "renesas,r7s72100-irqc", - "renesas,rza1-irqc"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0xfcfef800 0x6>; - interrupt-map = - <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <7 0>; - }; - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = ; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - rtc: rtc@fcff1000 { - compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; - reg = <0xfcff1000 0x2e>; - interrupts = , - , - ; - interrupt-names = "alarm", "period", "carry"; - clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, - <&rtc_x3_clk>, <&extal_clk>; - clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - }; - - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts deleted file mode 100644 index 69a5a44b8a2f..000000000000 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZA2MEVB board - * - * Copyright (C) 2018 Renesas Electronics - * - * As upstream Linux does not support XIP, it cannot run in 8 MiB of HyperRAM. - * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has - * the following ramifications: - * - SCIF4 connected to the on-board USB-serial can no longer be used as the - * serial console, - * - Instead, SCIF2 is used as the serial console, by connecting a 3.3V TTL - * USB-to-Serial adapter to the CMOS camera connector: - * - RXD = CN17-9, - * - TXD = CN17-10, - * - GND = CN17-2 or CN17-17, - * - The first Ethernet channel can no longer be used, - * - USB Channel 1 loses the overcurrent input signal. - * - * Please make sure your sub-board matches the following switch settings: - * - * SW6 SW6-1 set to SDRAM - * ON SW6-2 set to Audio - * +---------------------+ SW6-3 set to DRP - * | = = = = = | SW6-4 set to CEU - * | = = | SW6-5 set to Ether2 - * | 1 2 3 4 5 6 7 8 9 0 | SW6-6 set to VDC6 - * +---------------------+ SW6-7 set to VDC6 - */ - -/dts-v1/; -#include "r7s9210.dtsi" -#include -#include -#include - -/ { - model = "RZA2MEVB"; - compatible = "renesas,rza2mevb", "renesas,r7s9210"; - - aliases { - serial0 = &scif2; - ethernet0 = ðer1; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - key-3 { - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - compatible = "gpio-leds"; - - led-red { - gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; - }; - led-green { - gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@c000000 { - device_type = "memory"; - reg = <0x0c000000 0x04000000>; /* SDRAM */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -ðer1 { - pinctrl-names = "default"; - pinctrl-0 = <ð1_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy1>; - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c816", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -/* EXTAL */ -&extal_clk { - clock-frequency = <24000000>; /* 24MHz */ -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - eeprom@50 { - compatible = "renesas,r1ex24128", "atmel,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -/* High resolution System tick timers */ -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; -}; - -&pinctrl { - eth0_pins: eth0 { - pinmux = , /* REF50CK0 */ - , /* RMMI0_TXDEN */ - , /* RMII0_TXD0 */ - , /* RMII0_TXD1 */ - , /* RMII0_CRSDV */ - , /* RMII0_RXD0 */ - , /* RMII0_RXD1 */ - , /* RMII0_RXER */ - , /* ET0_MDC */ - , /* ET0_MDIO */ - ; /* IRQ4 */ - }; - - eth1_pins: eth1 { - pinmux = , /* REF50CK1 */ - , /* RMMI1_TXDEN */ - , /* RMII1_TXD0 */ - , /* RMII1_TXD1 */ - , /* RMII1_CRSDV */ - , /* RMII1_RXD0 */ - , /* RMII1_RXD1 */ - , /* RMII1_RXER */ - , /* ET1_MDC */ - , /* ET1_MDIO */ - ; /* IRQ5 */ - }; - - i2c3_pins: i2c3 { - pinmux = , /* RIIC3SCL */ - ; /* RIIC3SDA */ - }; - - keyboard_pins: keyboard { - pinmux = ; /* IRQ0 */ - }; - - /* Serial Console */ - scif2_pins: serial2 { - pinmux = , /* TxD2 */ - ; /* RxD2 */ - }; - - sdhi0_pins: sdhi0 { - pinmux = , /* SD0_CD */ - ; /* SD0_WP */ - }; - - sdhi1_pins: sdhi1 { - pinmux = , /* SD1_CD */ - ; /* SD1_WP */ - }; - - usb0_pins: usb0 { - pinmux = , /* VBUSIN0 */ - , /* VBUSEN0 */ - ; /* OVRCUR0 */ - }; - - usb1_pins: usb1 { - pinmux = , /* VBUSIN1 */ - ; /* VBUSEN1 */ - }; -}; - -/* RTC_X1 */ -&rtc_x1_clk { - clock-frequency = <32768>; -}; - -/* Serial Console */ -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - bus-width = <4>; - status = "okay"; -}; - -/* USB-0 as Host */ -&usb2_phy0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; /* Requires JP3 to be fitted */ - status = "okay"; -}; - -/* USB-1 as Host */ -&usb2_phy1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; - status = "okay"; -}; - -/* USB_X1 */ -&usb_x1_clk { - clock-frequency = <48000000>; -}; diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi deleted file mode 100644 index fdeb0bc12cb7..000000000000 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ /dev/null @@ -1,509 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R7S9210 SoC - * - * Copyright (C) 2018 Renesas Electronics Corporation - * - */ - -#include -#include - -/ { - compatible = "renesas,r7s9210"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - /* External clocks */ - extal_clk: extal { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* Value must be set by board */ - clock-frequency = <0>; - }; - - rtc_x1_clk: rtc_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value (32678) must be set by board */ - clock-frequency = <0>; - }; - - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value (48000000) must be set by board */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <528000000>; - next-level-cache = <&L2>; - }; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - L2: cache-controller@1f003000 { - compatible = "arm,pl310-cache"; - reg = <0x1f003000 0x1000>; - interrupts = ; - arm,early-bresp-disable; - arm,full-line-zero-disable; - cache-unified; - cache-level = <2>; - }; - - scif0: serial@e8007000 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8007000 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 47>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif1: serial@e8007800 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8007800 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 46>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif2: serial@e8008000 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8008000 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 45>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif3: serial@e8008800 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8008800 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 44>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif4: serial@e8009000 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8009000 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 43>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD 97>; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e800d000 { - compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; - reg = <0xe800d000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD 96>; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@e800d800 { - compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; - reg = <0xe800d800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD 95>; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ether0: ethernet@e8204000 { - compatible = "renesas,ether-r7s9210"; - reg = <0xe8204000 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 65>; - power-domains = <&cpg>; - - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ether1: ethernet@e8204200 { - compatible = "renesas,ether-r7s9210"; - reg = <0xe8204200 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 64>; - power-domains = <&cpg>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@e803a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803a000 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD 87>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@e803a400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803a400 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD 86>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c2: i2c@e803a800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803a800 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD 85>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c3: i2c@e803ac00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803ac00 0x44>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "tei", "ri", "ti", "spi", "sti", - "naki", "ali", "tmoi"; - clocks = <&cpg CPG_MOD 84>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - ostm0: timer@e803b000 { - compatible = "renesas,r7s9210-ostm", "renesas,ostm"; - reg = <0xe803b000 0x30>; - interrupts = ; - clocks = <&cpg CPG_MOD 36>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm1: timer@e803c000 { - compatible = "renesas,r7s9210-ostm", "renesas,ostm"; - reg = <0xe803c000 0x30>; - interrupts = ; - clocks = <&cpg CPG_MOD 35>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm2: timer@e803d000 { - compatible = "renesas,r7s9210-ostm", "renesas,ostm"; - reg = <0xe803d000 0x30>; - interrupts = ; - clocks = <&cpg CPG_MOD 34>; - power-domains = <&cpg>; - status = "disabled"; - }; - - ohci0: usb@e8218000 { - compatible = "generic-ohci"; - reg = <0xe8218000 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ehci0: usb@e8218100 { - compatible = "generic-ehci"; - reg = <0xe8218100 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@e8218200 { - compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; - reg = <0xe8218200 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>; - clock-names = "fck", "usb_x1"; - power-domains = <&cpg>; - #phy-cells = <0>; - status = "disabled"; - }; - - usbhs0: usb@e8219000 { - compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; - reg = <0xe8219000 0x724>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>; - renesas,buswait = <7>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ohci1: usb@e821a000 { - compatible = "generic-ohci"; - reg = <0xe821a000 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ehci1: usb@e821a100 { - compatible = "generic-ehci"; - reg = <0xe821a100 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@e821a200 { - compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; - reg = <0xe821a200 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>; - clock-names = "fck", "usb_x1"; - power-domains = <&cpg>; - #phy-cells = <0>; - status = "disabled"; - }; - - usbhs1: usb@e821b000 { - compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; - reg = <0xe821b000 0x724>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>; - renesas,buswait = <7>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - sdhi0: mmc@e8228000 { - compatible = "renesas,sdhi-r7s9210"; - reg = <0xe8228000 0x8c0>; - interrupts = ; - clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; - clock-names = "core", "cd"; - power-domains = <&cpg>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: mmc@e822a000 { - compatible = "renesas,sdhi-r7s9210"; - reg = <0xe822a000 0x8c0>; - interrupts = ; - clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; - clock-names = "core", "cd"; - power-domains = <&cpg>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - gic: interrupt-controller@e8221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8221000 0x1000>, - <0xe8222000 0x1000>; - }; - - cpg: clock-controller@fcfe0010 { - compatible = "renesas,r7s9210-cpg-mssr"; - reg = <0xfcfe0010 0x455>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - }; - - wdt: watchdog@fcfe7000 { - compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; - reg = <0xfcfe7000 0x26>; - interrupts = ; - clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; - }; - - bsid: chipid@fcfe8004 { - compatible = "renesas,bsid"; - reg = <0xfcfe8004 4>; - }; - - irqc: interrupt-controller@fcfef800 { - compatible = "renesas,r7s9210-irqc", - "renesas,rza1-irqc"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0xfcfef800 0x6>; - interrupt-map = - <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <7 0>; - }; - - pinctrl: pinctrl@fcffe000 { - compatible = "renesas,r7s9210-pinctrl"; - reg = <0xfcffe000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 176>; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts deleted file mode 100644 index e81a7213d304..000000000000 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the APE6EVM board - * - * Copyright (C) 2013 Renesas Solutions Corp. - */ - -/dts-v1/; -#include "r8a73a4.dtsi" -#include -#include - -/ { - model = "APE6EVM"; - compatible = "renesas,ape6evm", "renesas,r8a73a4"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_mmc0: regulator-mmc0 { - compatible = "regulator-fixed"; - regulator-name = "MMC0 Vcc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_sdhi0: regulator-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */ - ape6evm_fixed_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ape6evm_fixed_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; - label = "GNSS_EN"; - }; - led2 { - gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; - label = "NFC_NRST"; - }; - led3 { - gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; - label = "GNSS_NRST"; - }; - led4 { - gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; - label = "BT_WAKEUP"; - }; - led5 { - gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; - label = "STROBE"; - }; - led6 { - gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; - label = "BBRESETOUT"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - zero-key { - gpios = <&pfc 324 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S16"; - wakeup-source; - }; - - menu-key { - gpios = <&pfc 325 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S17"; - }; - - home-key { - gpios = <&pfc 326 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S18"; - }; - - back-key { - gpios = <&pfc 327 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S19"; - }; - - volup-key { - gpios = <&pfc 328 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S20"; - }; - - voldown-key { - gpios = <&pfc 329 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S21"; - }; - }; -}; - -&i2c5 { - status = "okay"; - vdd_dvfs: regulator@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = <1950000 1115000>, /* kHz uV */ - <1462500 995000>; - voltage-tolerance = <1>; /* 1% */ -}; - -&bsc { - flash@0 { - compatible = "cfi-flash", "mtd-rom"; - reg = <0x0 0x08000000>; - bank-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "uboot-env"; - reg = <0x00040000 0x00040000>; - read-only; - }; - partition@80000 { - label = "flash"; - reg = <0x00080000 0x07f80000>; - }; - }; - }; - - ethernet@8000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x08000000 0x1000>; - interrupt-parent = <&irqc1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - reset-gpios = <&pfc 270 GPIO_ACTIVE_LOW>; - vdd33a-supply = <&ape6evm_fixed_3v3>; - vddvario-supply = <&ape6evm_fixed_1v8>; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&pfc { - scifa0_pins: scifa0 { - groups = "scifa0_data"; - function = "scifa0"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl"; - function = "mmc0"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - keyboard_pins: keyboard { - pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", - "PORT329"; - bias-pull-up; - }; -}; - -&mmcif0 { - vmmc-supply = <&vcc_mmc0>; - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "okay"; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - vmmc-supply = <&vcc_sdhi0>; - bus-width = <4>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - status = "okay"; -}; - -&sdhi1 { - vmmc-supply = <&ape6evm_fixed_3v3>; - bus-width = <4>; - broken-cd; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi deleted file mode 100644 index c39066967053..000000000000 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ /dev/null @@ -1,861 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a73a4 SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a73a4"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - clock-frequency = <1500000000>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - power-domains = <&pd_a3sm>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller-1 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z2>; - power-domains = <&pd_a3km>; - cache-unified; - cache-level = <2>; - }; - }; - - ptm { - compatible = "arm,coresight-etm3x"; - power-domains = <&pd_d4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - dbsc1: memory-controller@e6790000 { - compatible = "renesas,dbsc-r8a73a4"; - reg = <0 0xe6790000 0 0x10000>; - power-domains = <&pd_a3bc>; - }; - - dbsc2: memory-controller@e67a0000 { - compatible = "renesas,dbsc-r8a73a4"; - reg = <0 0xe67a0000 0 0x10000>; - power-domains = <&pd_a3bc>; - }; - - i2c5: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; - power-domains = <&pd_a3sp>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; - power-domains = <&pd_c4>; - }; - - irqc1: interrupt-controller@e61c0200 { - compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0200 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; - power-domains = <&pd_c4>; - }; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = - <&pfc 0 0 31>, <&pfc 32 32 9>, - <&pfc 64 64 22>, <&pfc 96 96 31>, - <&pfc 128 128 7>, <&pfc 160 160 19>, - <&pfc 192 192 31>, <&pfc 224 224 27>, - <&pfc 256 256 28>, <&pfc 288 288 21>, - <&pfc 320 320 10>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - power-domains = <&pd_c5>; - }; - - thermal@e61f0000 { - compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, - <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; - interrupts = ; - clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; - power-domains = <&pd_c5>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c3: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6530000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c4: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6540000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c6: i2c@e6550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6550000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c7: i2c@e6560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6560000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c8: i2c@e6570000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6570000 0 0x428>; - interrupts = ; - clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb3: serial@e6cf0000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6cf0000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; - clock-names = "fck"; - power-domains = <&pd_c4>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee100000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee120000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; - clock-names = "clk"; - power-domains = <&pd_c4>; - }; - - bsc: bus@fec10000 { - compatible = "renesas,bsc-r8a73a4", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - reg = <0 0xfec10000 0 0x400>; - clocks = <&zb_clk>; - power-domains = <&pd_c4>; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clocks */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a73a4-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll2s", "pll2h", "z", "z2", - "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; - }; - - /* Variable factor clocks (DIV6) */ - zb_clk: zb_clk@e6150010 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150010 0 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; - #clock-cells = <0>; - clock-output-names = "zb"; - }; - sdhi0_clk: sdhi0ck@e6150074 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150074 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - sdhi1_clk: sdhi1ck@e6150078 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - sdhi2_clk: sdhi2ck@e615007c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150008 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615000c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk3_clk: vclk3@e615001c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615001c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk4_clk: vclk4@e6150014 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150014 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk5_clk: vclk5@e6150034 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150034 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150018 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&fsiack_clk>, <0>; - #clock-cells = <0>; - }; - fsib_clk: fsib@e6150090 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150090 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&fsibck_clk>, <0>; - #clock-cells = <0>; - }; - mp_clk: mp@e6150080 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150080 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - m4_clk: m4@e6150098 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150098 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; - #clock-cells = <0>; - }; - hsi_clk: hsi@e615026c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, - <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; - #clock-cells = <0>; - }; - spuv_clk: spuv@e6150094 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150094 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - main_div2_clk: main_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll0_div2_clk: pll0_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - extal1_div2_clk: extal1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&extal1_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 - R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 - R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 - R8A73A4_CLK_DMAC - >; - clock-output-names = - "scifa0", "scifa1", "scifb0", "scifb1", - "scifb2", "scifb3", "dmac"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, - <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, - <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, - <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks - R8A73A4_CLK_HP>, <&cpg_clocks - R8A73A4_CLK_HP>, <&extalr_clk>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 - R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 - R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 - R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 - R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 - R8A73A4_CLK_CMT1 - >; - clock-output-names = - "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "iic6", "iic7", "iic0", "iic1", - "cmt1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, - <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS - R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 - R8A73A4_CLK_IIC3 - >; - clock-output-names = - "irqc", "intc-sys", "iic5", "iic4", "iic3"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 - >; - clock-output-names = - "thermal", "iic8"; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; - reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_c4: c4@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sg: a3sg@16 { - reg = <16>; - #power-domain-cells = <0>; - }; - - pd_a3ex: a3ex@17 { - reg = <17>; - #power-domain-cells = <0>; - }; - - pd_a3sp: a3sp@18 { - reg = <18>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2us: a2us@19 { - reg = <19>; - #power-domain-cells = <0>; - }; - }; - - pd_a3sm: a3sm@20 { - reg = <20>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2sl: a2sl@21 { - reg = <21>; - #power-domain-cells = <0>; - }; - }; - - pd_a3km: a3km@22 { - reg = <22>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2kl: a2kl@23 { - reg = <23>; - #power-domain-cells = <0>; - }; - }; - }; - - pd_c4ma: c4ma@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_c4cl: c4cl@2 { - reg = <2>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@3 { - reg = <3>; - #power-domain-cells = <0>; - }; - - pd_a4bc: a4bc@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3bc: a3bc@5 { - reg = <5>; - #power-domain-cells = <0>; - }; - }; - - pd_a4l: a4l@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - - pd_a4lc: a4lc@7 { - reg = <7>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3mp: a3mp@9 { - reg = <9>; - #power-domain-cells = <0>; - }; - - pd_a3vc: a3vc@10 { - reg = <10>; - #power-domain-cells = <0>; - }; - }; - - pd_a4sf: a4sf@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - - pd_a3r: a3r@12 { - reg = <12>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2rv: a2rv@13 { - reg = <13>; - #power-domain-cells = <0>; - }; - - pd_a2is: a2is@14 { - reg = <14>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts deleted file mode 100644 index fa09295052c6..000000000000 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the armadillo 800 eva board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -/dts-v1/; -#include "r8a7740.dtsi" -#include -#include -#include -#include - -/ { - model = "armadillo 800 eva"; - compatible = "renesas,armadillo800eva", "renesas,r8a7740"; - - aliases { - serial0 = &scifa1; - }; - - chosen { - bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sdhi0>; - - enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; - gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; - states = <3300000 0>, <1800000 1>; - - enable-active-high; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5.0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - keyboard { - compatible = "gpio-keys"; - - power-key { - gpios = <&pfc 99 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - - back-key { - gpios = <&pfc 100 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4"; - }; - - menu-key { - gpios = <&pfc 97 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW5"; - }; - - home-key { - gpios = <&pfc 98 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW6"; - }; - }; - - leds { - compatible = "gpio-leds"; - led3 { - gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; - label = "LED4"; - }; - led5 { - gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; - label = "LED5"; - }; - led6 { - gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - }; - - i2c2: i2c-2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - power-supply = <®_5p0v>; - enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - bitclock-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - bitclock-master; - frame-master; - system-clock-frequency = <12288000>; - }; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.c0f1", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&pfc 18 GPIO_ACTIVE_LOW>; - }; -}; - -&extal1_clk { - clock-frequency = <24000000>; -}; -&extal2_clk { - clock-frequency = <48000000>; -}; -&fsibck_clk { - clock-frequency = <12288000>; -}; -&cpg_clocks { - renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */ -}; - -&cmt1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; - - eeprom@50 { - compatible = "st,24c01", "atmel,24c01"; - reg = <0x50>; - pagesize = <16>; - }; - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&st1232_pins>; - pinctrl-names = "default"; - gpios = <&pfc 166 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c2 { - status = "okay"; - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; -}; - -&pfc { - pinctrl-0 = <&lcd0_pins>; - pinctrl-names = "default"; - - ether_pins: ether { - groups = "gether_mii", "gether_int"; - function = "gether"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - st1232_pins: touchscreen { - groups = "intc_irq10"; - function = "intc"; - }; - - backlight_pins: backlight { - groups = "tpu0_to2_1"; - function = "tpu0"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8_1", "mmc0_ctrl_1"; - function = "mmc0"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - function = "sdhi0"; - }; - - fsia_pins: sounda { - groups = "fsia_sclk_in", "fsia_mclk_out", - "fsia_data_in_1", "fsia_data_out_0"; - function = "fsia"; - }; - - lcd0_pins: lcd0 { - groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; - function = "lcd0"; - }; - - lcd0-mux-hog { - /* DBGMD/LCDC0/FSIA MUX */ - gpio-hog; - gpios = <176 0>; - output-high; - }; -}; - -&tpu { - status = "okay"; -}; - -&mmcif0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&tmu0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi deleted file mode 100644 index 1b2cf5fa322b..000000000000 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ /dev/null @@ -1,736 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Mobile A1 (R8A77400) SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a7740"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - clock-frequency = <800000000>; - power-domains = <&pd_a3sm>; - next-level-cache = <&L2>; - }; - }; - - gic: interrupt-controller@c2800000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xc2800000 0x1000>, - <0xc2000000 0x1000>; - }; - - L2: cache-controller@f0100000 { - compatible = "arm,pl310-cache"; - reg = <0xf0100000 0x1000>; - interrupts = ; - power-domains = <&pd_a3sm>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,shared-override; - cache-unified; - cache-level = <2>; - }; - - dbsc3: memory-controller@fe400000 { - compatible = "renesas,dbsc3-r8a7740"; - reg = <0xfe400000 0x400>; - power-domains = <&pd_a4s>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - ptm { - compatible = "arm,coresight-etm3x"; - power-domains = <&pd_d4>; - }; - - ceu0: ceu@fe910000 { - reg = <0xfe910000 0x3000>; - compatible = "renesas,r8a7740-ceu"; - interrupts = ; - clocks = <&mstp1_clks R8A7740_CLK_CEU20>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - ceu1: ceu@fe914000 { - reg = <0xfe914000 0x3000>; - compatible = "renesas,r8a7740-ceu"; - interrupts = ; - clocks = <&mstp1_clks R8A7740_CLK_CEU21>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - cmt1: timer@e6138000 { - compatible = "renesas,r8a7740-cmt1"; - reg = <0xe6138000 0x170>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - /* irqpin0: IRQ0 - IRQ7 */ - irqpin0: interrupt-controller@e6900000 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin1: IRQ8 - IRQ15 */ - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin2: IRQ16 - IRQ23 */ - irqpin2: interrupt-controller@e6900008 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin3: IRQ24 - IRQ31 */ - irqpin3: interrupt-controller@e690000c { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - ether: ethernet@e9a00000 { - compatible = "renesas,gether-r8a7740"; - reg = <0xe9a00000 0x800>, - <0xe9a01800 0x800>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_GETHER>; - power-domains = <&pd_a4s>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@fff20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; - reg = <0xfff20000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_IIC0>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - i2c1: i2c@e6c20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; - reg = <0xe6c20000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp3_clks R8A7740_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c40000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c50000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c60000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c70000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa5: serial@e6cb0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cb0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa6: serial@e6cc0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cc0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa7: serial@e6cd0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cd0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb: serial@e6c30000 { - compatible = "renesas,scifb-r8a7740", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a7740"; - reg = <0xe6050000 0x8000>, - <0xe605800c 0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 212>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - power-domains = <&pd_c5>; - }; - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x148>; - clocks = <&mstp3_clks R8A7740_CLK_TPU0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - #pwm-cells = <3>; - }; - - mmcif0: mmc@e6bd0000 { - compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks R8A7740_CLK_MMC>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - sdhi0: mmc@e6850000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6850000 0x100>; - interrupts = , - , - ; - clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: mmc@e6860000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6860000 0x100>; - interrupts = , - , - ; - clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi2: mmc@e6870000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6870000 0x100>; - interrupts = , - , - ; - clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sh_fsi2: sound@fe1f0000 { - #sound-dai-cells = <1>; - compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; - reg = <0xfe1f0000 0x400>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; - power-domains = <&pd_a4mp>; - status = "disabled"; - }; - - tmu0: timer@fff80000 { - compatible = "renesas,tmu-r8a7740", "renesas,tmu"; - reg = <0xfff80000 0x2c>; - interrupts = , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&pd_a4r>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@fff90000 { - compatible = "renesas,tmu-r8a7740", "renesas,tmu"; - reg = <0xfff90000 0x2c>; - interrupts = , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&pd_a4r>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clock */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - dv_clk: dv { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - fmsick_clk: fmsick { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fmsock_clk: fmsock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7740-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; - #clock-cells = <1>; - clock-output-names = "system", "pllc0", "pllc1", - "pllc2", "r", - "usb24s", - "i", "zg", "b", "m1", "hp", - "hpp", "usbp", "s", "zb", "m3", - "cp"; - }; - - /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150008 4>; - clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, - <&extal1_div2_clk>, <&extalr_clk>, <0>, - <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615000c 4>; - clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, - <&extal1_div2_clk>, <&extalr_clk>, <0>, - <0>; - #clock-cells = <0>; - }; - fmsi_clk: fmsi@e6150010 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150010 4>; - clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fmso_clk: fmso@e6150014 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150014 4>; - clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150018 4>; - clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; - #clock-cells = <0>; - }; - sub_clk: sub@e6150080 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150080 4>; - clocks = <&pllc1_div2_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; - #clock-cells = <0>; - }; - spu_clk: spu@e6150084 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150084 4>; - clocks = <&pllc1_div2_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; - #clock-cells = <0>; - }; - vou_clk: vou@e6150088 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150088 4>; - clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, - <0>; - #clock-cells = <0>; - }; - stpro_clk: stpro@e615009c { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615009c 4>; - clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pllc1_div2_clk: pllc1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - extal1_div2_clk: extal1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&extal1_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - subck_clks: subck_clks@e6150080 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150080 4>; - clocks = <&sub_clk>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 - >; - clock-output-names = - "subck", "subck2"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150134 4>, <0xe6150038 4>; - clocks = <&cpg_clocks R8A7740_CLK_S>, - <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_B>, - <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_B>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 - R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 - R8A7740_CLK_LCDC0 - >; - clock-output-names = - "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", - "tmu1", "lcdc0"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA - R8A7740_CLK_SCIFA7 - R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 - R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC - R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB - R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 - R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 - R8A7740_CLK_SCIFA4 - >; - clock-output-names = - "scifa6", "intca", - "scifa7", "dmac1", "dmac2", "dmac3", - "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", - "scifa2", "scifa3", "scifa4"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe615013c 4>, <0xe6150048 4>; - clocks = <&cpg_clocks R8A7740_CLK_R>, - <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 - R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 - R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 - >; - clock-output-names = - "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", - "mmc", "gether", "tpu0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150140 4>, <0xe615004c 4>; - clocks = <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_USBH R8A7740_CLK_SDHI2 - R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY - >; - clock-output-names = - "usbhost", "sdhi2", "usbfunc", "usphy"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a4lc: a4lc@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@2 { - reg = <2>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@3 { - reg = <3>; - #power-domain-cells = <0>; - }; - - pd_a4r: a4r@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3rv: a3rv@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - }; - - pd_a4s: a4s@10 { - reg = <10>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - - pd_a3sm: a3sm@12 { - reg = <12>; - #power-domain-cells = <0>; - }; - - pd_a3sg: a3sg@13 { - reg = <13>; - #power-domain-cells = <0>; - }; - }; - - pd_a4su: a4su@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts deleted file mode 100644 index 33ac4bd1e63b..000000000000 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ /dev/null @@ -1,350 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1H Qseven board development - * platform with camera daughter board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; - -#include - -#include "r8a7742-iwg21d-q7.dts" - -/ { - model = "iWave Systems RZ/G1H Qseven development platform with camera add-on"; - compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - serial3 = &scifb1; - serial5 = &hscif0; - ethernet1 = ðer; - }; - - mclk_cam1: mclk-cam1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - mclk_cam2: mclk-cam2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - mclk_cam3: mclk-cam3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - mclk_cam4: mclk-cam4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - reg_1p8v: 1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p8v: 2p8v { - compatible = "regulator-fixed"; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; -}; - -&avb { - /* Pins shared with VIN0, keep status disabled */ - status = "disabled"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1560", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - micrel,led-mode = <1>; - }; -}; - -&gpio0 { - /* Disable hogging GP0_18 to output LOW */ - /delete-node/ qspi-en-hog; - - /* Hog GP0_18 to output HIGH to enable VIN2 */ - vin2-en-hog { - gpio-hog; - gpios = <18 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "VIN2_EN"; - }; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - /* status set to "okay" when needed by camera configuration below */ - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - /* status set to "okay" when needed by camera configuration below */ - clock-frequency = <400000>; -}; - -&pfc { - can0_pins: can0 { - groups = "can0_data_d"; - function = "can0"; - }; - - ether_pins: ether { - groups = "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1_c"; - function = "i2c1"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3"; - function = "i2c3"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data"; - function = "scif1"; - }; - - scifb1_pins: scifb1 { - groups = "scifb1_data"; - function = "scifb1"; - }; - - vin0_8bit_pins: vin0 { - groups = "vin0_data8", "vin0_clk", "vin0_sync"; - function = "vin0"; - }; - - vin1_8bit_pins: vin1 { - groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; - function = "vin1"; - }; - - vin2_pins: vin2 { - groups = "vin2_g8", "vin2_clk"; - function = "vin2"; - }; - - vin3_pins: vin3 { - groups = "vin3_data8", "vin3_clk", "vin3_sync"; - function = "vin3"; - }; -}; - -&qspi { - /* Pins shared with VIN2, keep status disabled */ - status = "disabled"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&scifb1 { - pinctrl-0 = <&scifb1_pins>; - pinctrl-names = "default"; - status = "okay"; - - rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; -}; - -/* - * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints - * - * (un)comment the #include statements to change configuration - */ - -/* 8bit CMOS Camera 1 (J13) */ -#define CAM_PARENT_I2C i2c0 -#define MCLK_CAM mclk_cam1 -#define CAM_EP cam0ep -#define VIN_EP vin0ep -#undef CAM_ENABLED -#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" -//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" - -#ifdef CAM_ENABLED -&vin0 { - /* - * Set SW2 switch on the SOM to 'ON' - * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode - */ - status = "okay"; - pinctrl-0 = <&vin0_8bit_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&cam0ep>; - bus-width = <8>; - bus-type = ; - }; - }; -}; -#endif /* CAM_ENABLED */ - -#undef CAM_PARENT_I2C -#undef MCLK_CAM -#undef CAM_EP -#undef VIN_EP - -/* 8bit CMOS Camera 2 (J14) */ -#define CAM_PARENT_I2C i2c1 -#define MCLK_CAM mclk_cam2 -#define CAM_EP cam1ep -#define VIN_EP vin1ep -#undef CAM_ENABLED -#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" -//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" - -#ifdef CAM_ENABLED -&vin1 { - /* Set SW1 switch on the SOM to 'ON' */ - status = "okay"; - pinctrl-0 = <&vin1_8bit_pins>; - pinctrl-names = "default"; - - port { - vin1ep: endpoint { - remote-endpoint = <&cam1ep>; - bus-width = <8>; - bus-type = ; - }; - }; -}; - -#endif /* CAM_ENABLED */ - -#undef CAM_PARENT_I2C -#undef MCLK_CAM -#undef CAM_EP -#undef VIN_EP - -/* 8bit CMOS Camera 3 (J12) */ -#define CAM_PARENT_I2C i2c2 -#define MCLK_CAM mclk_cam3 -#define CAM_EP cam2ep -#define VIN_EP vin2ep -#undef CAM_ENABLED -#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" -//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" - -#ifdef CAM_ENABLED -&vin2 { - status = "okay"; - pinctrl-0 = <&vin2_pins>; - pinctrl-names = "default"; - - port { - vin2ep: endpoint { - remote-endpoint = <&cam2ep>; - bus-width = <8>; - data-shift = <8>; - bus-type = ; - }; - }; -}; -#endif /* CAM_ENABLED */ - -#undef CAM_PARENT_I2C -#undef MCLK_CAM -#undef CAM_EP -#undef VIN_EP - -/* 8bit CMOS Camera 4 (J11) */ -#define CAM_PARENT_I2C i2c3 -#define MCLK_CAM mclk_cam4 -#define CAM_EP cam3ep -#define VIN_EP vin3ep -#undef CAM_ENABLED -#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" -//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" - -#ifdef CAM_ENABLED -&vin3 { - status = "okay"; - pinctrl-0 = <&vin3_pins>; - pinctrl-names = "default"; - - port { - vin3ep: endpoint { - remote-endpoint = <&cam3ep>; - bus-width = <8>; - bus-type = ; - }; - }; -}; -#endif /* CAM_ENABLED */ - -#undef CAM_PARENT_I2C -#undef MCLK_CAM -#undef CAM_EP -#undef VIN_EP diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi deleted file mode 100644 index c73160df619d..000000000000 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This include file ties a VIN interface with a single ov5640 sensor on - * the iWave-RZ/G1H Qseven board development platform connected with the - * camera daughter board. - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include - -#define CAM_ENABLED 1 - -&CAM_PARENT_I2C { - status = "okay"; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - clocks = <&MCLK_CAM>; - clock-names = "xclk"; - AVDD-supply = <®_2p8v>; - DOVDD-supply = <®_2p8v>; - DVDD-supply = <®_1p8v>; - status = "okay"; - - port { - CAM_EP: endpoint { - bus-width = <8>; - data-shift = <2>; - bus-type = ; - pclk-sample = <1>; - remote-endpoint = <&VIN_EP>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi deleted file mode 100644 index a7f5cfec64b8..000000000000 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This include file ties a VIN interface with a single ov7725 sensor on - * the iWave-RZ/G1H Qseven board development platform connected with the - * camera daughter board. - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include - -#define CAM_ENABLED 1 - -&CAM_PARENT_I2C { - status = "okay"; - - ov7725@21 { - compatible = "ovti,ov7725"; - reg = <0x21>; - clocks = <&MCLK_CAM>; - status = "okay"; - - port { - CAM_EP: endpoint { - bus-width = <8>; - bus-type = ; - remote-endpoint = <&VIN_EP>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts deleted file mode 100644 index 64102b664055..000000000000 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1H Qseven board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/* - * SSI-SGTL5000 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7742-iwg21m.dtsi" -#include - -/ { - model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; - compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; - - aliases { - serial2 = &scifa2; - serial4 = &scifb2; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; - stdout-path = "serial2:115200n8"; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - lcd_backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 2 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - default-brightness-level = <7>; - enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - - sdhi2_led { - label = "sdio-led"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - }; - }; - - lvds-receiver { - compatible = "ti,ds90cf384a", "lvds-decoder"; - power-supply = <&vcc_3v3_tft1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_receiver_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - port@1 { - reg = <1>; - lvds_receiver_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; - - panel { - compatible = "edt,etm0700g0dh6"; - backlight = <&lcd_backlight>; - power-supply = <&vcc_3v3_tft1>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_receiver_out>; - }; - }; - }; - - reg_1p5v: 1p5v { - compatible = "regulator-fixed"; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - vcc_3v3_tft1: regulator-panel { - compatible = "regulator-fixed"; - - regulator-name = "vcc-3v3-tft1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - startup-delay-us = <500>; - gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p5v>; - }; - - touch: touchpanel@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpio0>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - /* GP1_29 is also shared with audio codec reset pin */ - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - vcc-supply = <&vcc_3v3_tft1>; - }; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&cmt0 { - status = "okay"; -}; - -&du { - status = "okay"; -}; - -&gpio0 { - touch-interrupt-hog { - gpio-hog; - gpios = <24 GPIO_ACTIVE_LOW>; - input; - }; -}; - -&gpio1 { - can-trx-en-hog { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "can-trx-en-gpio"; - }; -}; - -&hsusb { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&lvds0 { - status = "okay"; - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&lvds_receiver_in>; - }; - }; - }; -}; - -&msiof0 { - pinctrl-0 = <&msiof0_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - - status = "okay"; - - flash1: flash@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "user"; - reg = <0x00000000 0x00200000>; - }; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - /* Disable hsusb to enable USB2.0 host mode support on J2 */ - /* status = "okay"; */ -}; - -&pci1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pci2 { - /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */ - /* status = "okay"; */ -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - /* SW2[6] determines which connector is activated - * ON = PCIe X4 (connector-J7) - * OFF = mini-PCIe (connector-J26) - */ - status = "okay"; -}; - -&pfc { - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - backlight_pins: backlight { - groups = "tpu0_to2"; - function = "tpu0"; - }; - - can1_pins: can1 { - groups = "can1_data_b"; - function = "can1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2_b"; - function = "i2c2"; - }; - - msiof0_pins: msiof0 { - groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx"; - function = "msiof0"; - }; - - scifa2_pins: scifa2 { - groups = "scifa2_data_c"; - function = "scifa2"; - }; - - scifb2_pins: scifb2 { - groups = "scifb2_data", "scifb2_ctrl"; - function = "scifb2"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1_pwen"; - function = "usb1"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi4>, <&src4>, <&dvc1>; - capture = <&ssi3>, <&src3>, <&dvc0>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scifa2 { - pinctrl-0 = <&scifa2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifb2 { - pinctrl-0 = <&scifb2_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&ssi4 { - shared-pin; -}; - -&tpu { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi deleted file mode 100644 index b281a4d164b0..000000000000 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave RZ/G1H Qseven SOM - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a7742.dtsi" -#include - -/ { - compatible = "iwave,g21m", "renesas,r8a7742"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&gpio0 { - /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ - qspi-en-hog { - gpio-hog; - gpios = <18 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "QSPI_EN"; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&mmcif1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&pfc { - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc1_pins: mmc1 { - groups = "mmc1_data4", "mmc1_ctrl"; - function = "mmc1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x000c0000>; - read-only; - }; - partition@c0000 { - label = "env"; - reg = <0x000c0000 0x00002000>; - }; - partition@c2000 { - label = "user"; - reg = <0x000c2000 0x0013e000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi deleted file mode 100644 index 16d146db824a..000000000000 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ /dev/null @@ -1,1891 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7742 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7742"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1400000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; - power-domains = <&sysc R8A7742_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1400000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; - power-domains = <&sysc R8A7742_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - clock-frequency = <1400000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; - power-domains = <&sysc R8A7742_PD_CA15_CPU2>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - clock-frequency = <1400000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; - power-domains = <&sysc R8A7742_PD_CA15_CPU3>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; - power-domains = <&sysc R8A7742_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; - power-domains = <&sysc R8A7742_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; - power-domains = <&sysc R8A7742_PD_CA7_CPU2>; - next-level-cache = <&L2_CA7>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; - power-domains = <&sysc R8A7742_PD_CA7_CPU3>; - next-level-cache = <&L2_CA7>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7742_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7742_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu-0 { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - pmu-1 { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7742-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7742", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7742", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7742", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7742", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7742", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7742", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7742"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7742", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7742-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7742-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7742-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7742-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7742-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7742", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7742", - "renesas,rcar-gen2-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7742", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7742", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7742", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7742", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7742", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7742", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7742", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7742", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7742", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7742", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7742", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7742", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 300>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7742", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7742", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7742", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7742-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7742-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7742", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7742", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7742", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7742", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7742", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7742", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7742", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7742", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7742", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7742", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7742", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7742", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7742", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e56000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7742", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7742", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7742", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7742", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7742", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7742", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 215>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 215>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7742", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7742", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7742", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7742", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7742", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7742", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7742", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7742_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7742", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7742", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7742", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7742", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7742", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; - - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7742", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 703>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x20800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x21000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7742", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7742", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7742", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7742", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7742", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7742", - "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 305>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 305>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7742", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7742", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7742", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7742", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 130>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 130>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7742"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7742-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds@feb94000 { - compatible = "renesas,r8a7742-lvds"; - reg = <0 0xfeb94000 0 0x14>; - clocks = <&cpg CPG_MOD 725>; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 725>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7742-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7742-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts deleted file mode 100644 index 0d006aea99da..000000000000 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7743-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" -#include "iwg20d-q7-dbcm-ca.dtsi" - -/ { - model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; -}; - -&pciec { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts deleted file mode 100644 index 498e223a5f93..000000000000 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1M Qseven board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7743-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" - -/ { - model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; -}; - -&pciec { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi deleted file mode 100644 index b3fee1d61c87..000000000000 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1M-20M Qseven SOM - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -#include "r8a7743.dtsi" -#include - -/ { - compatible = "iwave,g20m", "renesas,r8a7743"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x20000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x20000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - mmcif0_pins: mmc { - groups = "mmc_data8_b", "mmc_ctrl"; - function = "mmc"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts deleted file mode 100644 index ff274bfcb664..000000000000 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SK-RZG1M board - * - * Copyright (C) 2016-2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7743.dtsi" -#include - -/ { - model = "SK-RZG1M"; - compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi deleted file mode 100644 index 2245d19a23bb..000000000000 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ /dev/null @@ -1,1799 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7743 SoC - * - * Copyright (C) 2016-2017 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7743"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7743_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7743_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7743_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7743-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7743"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7743", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7743-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7743-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7743-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7743-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7743", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7743", - "renesas,rcar-gen2-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7743", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7743", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7743-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7743-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7743", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7743", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7743", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7743", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7743", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7743", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7743", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7743", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7743", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7743", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7743", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7743", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7743_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7743", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7743_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7743", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7743", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7743", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7743", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7743_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - /* - * pci1 and xhci share the same phy, therefore only one of them - * can be active at any one time. If both of them are enabled, - * a race condition will determine who'll control the phy. - * A firmware file is needed by the xhci driver in order for - * USB 3.0 to work properly. - */ - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7743", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7743", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7743", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7743", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7743", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7743", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7743"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7743-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7743-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7743-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts deleted file mode 100644 index 3e58c2e92e03..000000000000 --- a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave Systems RZ/G1N Qseven board development - * platform with camera daughter board - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7744-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" -#include "iwg20d-q7-dbcm-ca.dtsi" - -/ { - model = "iWave Systems RZ/G1N Qseven development platform with camera add-on"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; -}; diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts deleted file mode 100644 index 1fdac528f274..000000000000 --- a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1N Qseven board - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7744-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" - -/ { - model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; -}; diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi deleted file mode 100644 index 82ee3c1140ef..000000000000 --- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave RZ/G1N Qseven SOM - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include "r8a7744.dtsi" -#include - -/ { - compatible = "iwave,g20m", "renesas,r8a7744"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - mmcif0_pins: mmc { - groups = "mmc_data8_b", "mmc_ctrl"; - function = "mmc"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi deleted file mode 100644 index aa13841f9781..000000000000 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ /dev/null @@ -1,1785 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7744 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7744"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7744_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7744_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7744_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7744-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7744"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7744", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7744-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7744-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7744-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7744-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7744", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7744", - "renesas,rcar-gen2-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7744", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7744", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7744", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7744", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7744", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7744-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7744-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7744", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7744", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7744", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7744", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7744", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7744", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7744", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7744", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7744", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7744_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7744", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7744_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7744", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7744", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7744", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7744", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7744_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - /* - * pci1 and xhci share the same phy, therefore only one of them - * can be active at any one time. If both of them are enabled, - * a race condition will determine who'll control the phy. - * A firmware file is needed by the xhci driver in order for - * USB 3.0 to work properly. - */ - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7744", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7744", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7744", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7744", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7744", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7744", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7744", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7744", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7744"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7744-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7744-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7744-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts deleted file mode 100644 index b1f679da36b2..000000000000 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter - * board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -#include "r8a7745-iwg22d-sodimm.dts" - -/ { - model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on"; - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; - - aliases { - serial0 = &scif1; - serial4 = &scif5; - serial6 = &hscif2; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hscif2 { - pinctrl-0 = <&hscif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lcd_panel { - status = "disabled"; - - /delete-node/ port; -}; - -&pfc { - can1_pins: can1 { - groups = "can1_data_b"; - function = "can1"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - hscif2_pins: hscif2 { - groups = "hscif2_data"; - function = "hscif2"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1_d"; - function = "i2c1"; - }; - - scif1_pins: scif1 { - groups = "scif1_data"; - function = "scif1"; - }; - - scif5_pins: scif5 { - groups = "scif5_data_d"; - function = "scif5"; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif5 { - pinctrl-0 = <&scif5_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts deleted file mode 100644 index c105932f642e..000000000000 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1E SODIMM carrier board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/* - * SSI-SGTL5000 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7745-iwg22m.dtsi" -#include - -/ { - model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; - - aliases { - ethernet0 = &avb; - serial3 = &scif4; - serial5 = &hscif1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial3:115200n8"; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - lcd_panel: lcd { - compatible = "edt,etm043080dh6gp"; - power-supply = <&vccq_panel>; - backlight = <&backlight_lcd>; - - port { - lcd_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - }; - - vccq_panel: regulator-vccq-panel { - compatible = "regulator-fixed"; - regulator-name = "Panel VccQ"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - /* - * On some older versions of the platform (before R4.0) the phy address - * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. - */ - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&lcd_in>; - }; - }; - }; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&i2c5 { - pinctrl-0 = <&i2c5_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; - - stmpe811@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupt-parent = <&gpio4>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* ADC conversion time: 80 clocks */ - st,sample-time = <4>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&pfc { - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - backlight_pins: backlight { - groups = "tpu_to3_c"; - function = "tpu"; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - du0_pins: du0 { - groups = "du0_rgb666", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data", "hscif1_ctrl"; - function = "hscif1"; - }; - - i2c5_pins: i2c5 { - groups = "i2c5_b"; - function = "i2c5"; - }; - - scif4_pins: scif4 { - groups = "scif4_data_b"; - function = "scif4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sound_pins: sound { - groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi3>, <&src3>, <&dvc0>; - capture = <&ssi4>, <&src4>, <&dvc1>; - }; - }; -}; - -&scif4 { - pinctrl-0 = <&scif4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi4 { - shared-pin; -}; - -&tpu { - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi deleted file mode 100644 index 41f111b99a75..000000000000 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -#include "r8a7745.dtsi" -#include - -/ { - compatible = "iwave,g22m", "renesas,r8a7745"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - mmcif0_pins: mmc { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - i2c3_pins: i2c3 { - groups = "i2c3_b"; - function = "i2c3"; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts deleted file mode 100644 index 0a75e8c79acc..000000000000 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SK-RZG1E board - * - * Copyright (C) 2016-2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7745.dtsi" -#include - -/ { - model = "SK-RZG1E"; - compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi deleted file mode 100644 index 44688b8431c3..000000000000 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ /dev/null @@ -1,1589 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7745 SoC - * - * Copyright (C) 2016-2017 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7745"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic0; - i2c7 = &iic1; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; - power-domains = <&sysc R8A7745_PD_CA7_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; - power-domains = <&sysc R8A7745_PD_CA7_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7745_PD_CA7_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7745"; - reg = <0 0xe6060000 0 0x11c>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7745", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7745-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7745-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7745-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7745-wdt", - "renesas,rcar-gen2-wdt"; - interrupts = ; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7745-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7745", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7745", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7745", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7745", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7745", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7745-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7745-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7745", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7745", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7745", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7745_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7745", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7745_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7745", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7745", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7745", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7745_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", - "src.2", "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, - <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, - <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7745", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7745", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7745", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7745", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7745"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7745-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7745-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts deleted file mode 100644 index 644802285249..000000000000 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1C single board computer - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include -#include "r8a77470.dtsi" -/ { - model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; - compatible = "iwave,g23s", "renesas,r8a77470"; - - aliases { - ethernet0 = &avb; - serial1 = &scif1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial1:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_1p8v: reg-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: reg-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - interrupt-parent = <&gpio5>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&gpio2 { - interrupt-fixup-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "hdmi-hpd-int"; - input; - }; -}; - -&hsusb0 { - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <100000>; - - hdmi@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - bridge_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&pfc { - avb_pins: avb { - groups = "avb_mdio", "avb_gmii_tx_rx"; - function = "avb"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_e"; - function = "i2c4"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3_c"; - function = "i2c3"; - }; - - mmc_pins_uhs: mmc_uhs { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data2"; - function = "qspi0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_b"; - function = "scif1"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&qspi0 { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "issi,is25lp016d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <133000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&mmc_pins_uhs>; - pinctrl-names = "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi2>; - bus-width = <4>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&usb2_phy0 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usbphy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usbphy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi deleted file mode 100644 index a5cf663a0118..000000000000 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ /dev/null @@ -1,1028 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a77470 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include -/ { - compatible = "renesas,r8a77470"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; - power-domains = <&sysc R8A77470_PD_CA7_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; - power-domains = <&sysc R8A77470_PD_CA7_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A77470_PD_CA7_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77470-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 30>; - gpio-reserved-ranges = <17 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77470"; - reg = <0 0xe6060000 0 0x118>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77470-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a77470-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77470-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77470-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a77470", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x20000>; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hsusb0: hsusb@e6590000 { - compatible = "renesas,usbhs-r8a77470", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac00 0>, <&usb_dmac00 1>, - <&usb_dmac10 0>, <&usb_dmac10 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - }; - - usbphy0: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a77470", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - }; - - hsusb1: hsusb@e6598000 { - compatible = "renesas,usbhs-r8a77470", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6598000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>; - dmas = <&usb_dmac01 0>, <&usb_dmac01 1>, - <&usb_dmac11 0>, <&usb_dmac11 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <4>; - /* We need to turn on usbphy0 to make usbphy1 to work */ - phys = <&usb1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 706>; - status = "disabled"; - }; - - usbphy1: usb-phy-controller@e6598100 { - compatible = "renesas,usb-phy-r8a77470", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6598100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 706>; - clock-names = "usbhs"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 706>; - status = "disabled"; - - usb1: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - }; - - usb_dmac00: dma-controller@e65a0000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac10: dma-controller@e65b0000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac01: dma-controller@e65a8000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a8000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac11: dma-controller@e65b8000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b8000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 327>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77470", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a77470", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77470", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi0: spi@e6b10000 { - compatible = "renesas,qspi-r8a77470", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 918>; - status = "disabled"; - }; - - qspi1: spi@ee200000 { - compatible = "renesas,qspi-r8a77470", "renesas,qspi"; - reg = <0 0xee200000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a77470", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a77470", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a77470", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77470", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77470", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb0 0>, <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb0 0>, <&usb2_phy0>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77470"; - reg = <0 0xee080200 0 0x700>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; - }; - - ohci1: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - ehci1: usb@ee0c0100 { - compatible = "generic-ehci"; - reg = <0 0xee0c0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a77470"; - reg = <0 0xee0c0200 0 0x700>; - clocks = <&cpg CPG_MOD 705>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 705>; - #phy-cells = <0>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a77470", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <156000000>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee300000 { - compatible = "renesas,sdhi-mmc-r8a77470"; - reg = <0 0xee300000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <156000000>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a77470", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <78000000>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77470"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a77470-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77470-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts deleted file mode 100644 index 9b65d246e583..000000000000 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -/dts-v1/; -#include "r8a7778.dtsi" -#include -#include - -/ { - model = "bockw"; - compatible = "renesas,bockw", "renesas,r8a7778"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x10000000>; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - system-clock-frequency = <11289600>; - }; - }; -}; - -&bsc { - ethernet@18300000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0x18300000 0x1000>; - - phy-mode = "mii"; - interrupt-parent = <&irqpin>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; -}; - -&extal_clk { - clock-frequency = <33333333>; -}; - -&i2c0 { - status = "okay"; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - camera@41 { - compatible = "oki,ml86v7667"; - reg = <0x41>; - }; - - camera@43 { - compatible = "oki,ml86v7667"; - reg = <0x43>; - }; - - rx8581: rtc@51 { - compatible = "epson,rx8581"; - reg = <0x51>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmc_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - broken-cd; - status = "okay"; -}; - -&irqpin { - status = "okay"; -}; - -&tmu0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif0_pins: scif0 { - groups = "scif0_data_a", "scif0_ctrl"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - sdhi0_pup_pins: sd0_pup { - groups = "sdhi0_cd", "sdhi0_wp"; - function = "sdhi0"; - bias-pull-up; - }; - - hspi0_pins: hspi0 { - groups = "hspi0_a"; - function = "hspi0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; -}; - -&rcar_sound { - /* Single DAI */ - #sound-dai-cells = <0>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>, <&sdhi0_pup_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <4>; - status = "okay"; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; -}; - -&hspi0 { - pinctrl-0 = <&hspi0_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl008k", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data(spi)"; - reg = <0x00000000 0x00100000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi deleted file mode 100644 index 8d4530ed2fc6..000000000000 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ /dev/null @@ -1,671 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M1A (R8A77781) SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a7778"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <800000000>; - clocks = <&z_clk>; - }; - }; - - aliases { - spi0 = &hspi0; - spi1 = &hspi1; - spi2 = &hspi2; - }; - - bsc: bus@1c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1c000000>; - }; - - ether: ethernet@fde00000 { - compatible = "renesas,ether-r8a7778", - "renesas,rcar-gen1-ether"; - reg = <0xfde00000 0x400>; - interrupts = ; - clocks = <&mstp1_clks R8A7778_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe438000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfe438000 0x1000>, - <0xfe430000 0x100>; - }; - - /* irqpin: IRQ0 - IRQ3 */ - irqpin: interrupt-controller@fe78001c { - compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - status = "disabled"; /* default off */ - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>, - <0xfe780000 4>; - interrupts = , - , - , - ; - sense-bitfield-width = <2>; - }; - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc40000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc41000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc42000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc43000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc44000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 27>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - pfc: pinctrl@fffc0000 { - compatible = "renesas,pfc-r8a7778"; - reg = <0xfffc0000 0x118>; - }; - - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc70000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc71000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C1>; - power-domains = <&cpg_clocks>; - i2c-scl-internal-delay-ns = <5>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc72000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C2>; - power-domains = <&cpg_clocks>; - i2c-scl-internal-delay-ns = <5>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc73000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C3>; - power-domains = <&cpg_clocks>; - i2c-scl-internal-delay-ns = <5>; - status = "disabled"; - }; - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@ffd81000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd81000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu2: timer@ffd82000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd82000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - rcar_sound: sound@ffd90000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; - reg = <0xffd90000 0x1000>, /* SRU */ - <0xffd91000 0x240>, /* SSI */ - <0xfffe0000 0x24>; /* ADG */ - clocks = <&mstp3_clks R8A7778_CLK_SSI8>, - <&mstp3_clks R8A7778_CLK_SSI7>, - <&mstp3_clks R8A7778_CLK_SSI6>, - <&mstp3_clks R8A7778_CLK_SSI5>, - <&mstp3_clks R8A7778_CLK_SSI4>, - <&mstp0_clks R8A7778_CLK_SSI3>, - <&mstp0_clks R8A7778_CLK_SSI2>, - <&mstp0_clks R8A7778_CLK_SSI1>, - <&mstp0_clks R8A7778_CLK_SSI0>, - <&mstp5_clks R8A7778_CLK_SRU_SRC8>, - <&mstp5_clks R8A7778_CLK_SRU_SRC7>, - <&mstp5_clks R8A7778_CLK_SRU_SRC6>, - <&mstp5_clks R8A7778_CLK_SRU_SRC5>, - <&mstp5_clks R8A7778_CLK_SRU_SRC4>, - <&mstp5_clks R8A7778_CLK_SRU_SRC3>, - <&mstp5_clks R8A7778_CLK_SRU_SRC2>, - <&mstp5_clks R8A7778_CLK_SRU_SRC1>, - <&mstp5_clks R8A7778_CLK_SRU_SRC0>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg_clocks R8A7778_CLK_S1>; - clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", - "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.8", "src.7", "src.6", "src.5", "src.4", - "src.3", "src.2", "src.1", "src.0", - "clk_a", "clk_b", "clk_c", "clk_i"; - - status = "disabled"; - - rcar_sound,src { - src3: src-3 { }; - src4: src-4 { }; - src5: src-5 { }; - src6: src-6 { }; - src7: src-7 { }; - src8: src-8 { }; - src9: src-9 { }; - }; - - rcar_sound,ssi { - ssi3: ssi-3 { interrupts = ; }; - ssi4: ssi-4 { interrupts = ; }; - ssi5: ssi-5 { interrupts = ; }; - ssi6: ssi-6 { interrupts = ; }; - ssi7: ssi-7 { interrupts = ; }; - ssi8: ssi-8 { interrupts = ; }; - ssi9: ssi-9 { interrupts = ; }; - }; - }; - - scif0: serial@ffe40000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe40000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@ffe41000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe41000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@ffe42000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe42000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@ffe43000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe43000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@ffe44000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe44000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@ffe45000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe45000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hscif0: serial@ffe48000 { - compatible = "renesas,hscif-r8a7778", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe48000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, - <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hscif1: serial@ffe49000 { - compatible = "renesas,hscif-r8a7778", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe49000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, - <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - mmcif: mmc@ffe4e000 { - compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; - reg = <0xffe4e000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_MMC>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi0: mmc@ffe4c000 { - compatible = "renesas,sdhi-r8a7778", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4c000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi1: mmc@ffe4d000 { - compatible = "renesas,sdhi-r8a7778", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4d000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi2: mmc@ffe4f000 { - compatible = "renesas,sdhi-r8a7778", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4f000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hspi1: spi@fffc8000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc8000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hspi2: spi@fffc6000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc6000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External input clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7778-cpg-clocks"; - reg = <0xffc80000 0x80>; - #clock-cells = <1>; - clocks = <&extal_clk>; - clock-output-names = "plla", "pllb", "b", - "out", "p", "s", "s1"; - #power-domain-cells = <0>; - }; - - /* Audio clocks; frequencies are set by boards if applicable. */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Fixed ratio clocks */ - g_clk: g { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - s3_clk: s3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - s4_clk: s4 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - z_clk: z { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLB>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@ffc80030 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 - R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 - R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 - R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 - R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 - R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 - R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 - R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 - R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 - R8A7778_CLK_SSI3 R8A7778_CLK_SRU - R8A7778_CLK_HSPI - >; - clock-output-names = - "i2c0", "i2c1", "i2c2", "i2c3", "scif0", - "scif1", "scif2", "scif3", "scif4", "scif5", - "hscif0", "hscif1", - "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", - "ssi2", "ssi3", "sru", "hspi"; - }; - mstp1_clks: mstp1_clks@ffc80034 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80034 4>, <0xffc80044 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_ETHER R8A7778_CLK_VIN0 - R8A7778_CLK_VIN1 R8A7778_CLK_USB - >; - clock-output-names = - "ether", "vin0", "vin1", "usb"; - }; - mstp3_clks: mstp3_clks@ffc8003c { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc8003c 4>; - clocks = <&s4_clk>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_MMC R8A7778_CLK_SDHI0 - R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 - R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 - R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 - R8A7778_CLK_SSI8 - >; - clock-output-names = - "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", - "ssi5", "ssi6", "ssi7", "ssi8"; - }; - mstp5_clks: mstp5_clks@ffc80054 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80054 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 - R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 - R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 - R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 - R8A7778_CLK_SRU_SRC8 - >; - clock-output-names = - "sru-src0", "sru-src1", "sru-src2", - "sru-src3", "sru-src4", "sru-src5", - "sru-src6", "sru-src7", "sru-src8"; - }; - }; - - rst: reset-controller@ffcc0000 { - compatible = "renesas,r8a7778-reset-wdt"; - reg = <0xffcc0000 0x40>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts deleted file mode 100644 index fd40890bd77b..000000000000 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H1 (R8A77790) Marzen board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -/dts-v1/; -#include "r8a7779.dtsi" -#include -#include -#include - -/ { - model = "marzen"; - compatible = "renesas,marzen", "renesas,r8a7779"; - - aliases { - serial0 = &scif2; - serial1 = &scif4; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0x18000000 0x100>; - pinctrl-0 = <ðernet_pins>; - pinctrl-names = "default"; - - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; - - keyboard-irq { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_irq_pins>; - pinctrl-names = "default"; - - interrupt-parent = <&gpio0>; - - key-1 { - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - linux,code = ; - label = "SW1-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - linux,code = ; - label = "SW1-2"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - keyboard-gpio { - compatible = "gpio-keys-polled"; - poll-interval = <50>; - - pinctrl-0 = <&keyboard_gpio_pins>; - pinctrl-names = "default"; - - key-3 { - gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW1-3"; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW1-4"; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led2 { - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - }; - led3 { - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - }; - led4 { - gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - vga_enc_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - port@1 { - reg = <1>; - vga_enc_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&vga_enc_out>; - }; - }; - }; - - lvds-encoder { - compatible = "thine,thc63lvdm83d"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_enc_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - lvds_connector: endpoint { - }; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; - clock-names = "du.0", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&vga_enc_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&lvds_enc_in>; - }; - }; - }; -}; - -&gpio0 { - keyboard-irq-hog { - gpio-hog; - gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>; - input; - }; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <100000>; -}; - -&irqpin0 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <31250000>; -}; - -&tmu0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - du0 { - groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; - function = "du0"; - }; - du1 { - groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; - function = "du1"; - }; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; - - ethernet_pins: ethernet { - intc { - groups = "intc_irq1_b"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - scif2_pins: scif2 { - groups = "scif2_data_c"; - function = "scif2"; - }; - - scif4_pins: scif4 { - groups = "scif4_data"; - function = "scif4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - function = "sdhi0"; - }; - - hspi0_pins: hspi0 { - groups = "hspi0"; - function = "hspi0"; - }; - - keyboard_irq_pins: keyboard-irq { - pins = "GP_0_17", "GP_0_18"; - bias-pull-up; - }; - keyboard_gpio_pins: keyboard-gpio { - pins = "GP_0_19", "GP_0_20"; - bias-pull-up; - }; -}; - -&sata { - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif4 { - pinctrl-0 = <&scif4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&hspi0 { - pinctrl-0 = <&hspi0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi deleted file mode 100644 index 97b767d81d92..000000000000 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ /dev/null @@ -1,717 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H1 (R8A77790) SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7779"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - power-domains = <&sysc R8A7779_PD_ARM1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - power-domains = <&sysc R8A7779_PD_ARM2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - power-domains = <&sysc R8A7779_PD_ARM3>; - }; - }; - - aliases { - spi0 = &hspi0; - spi1 = &hspi1; - spi2 = &hspi2; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - timer@f0000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf0000200 0x100>; - interrupts = ; - clocks = <&cpg_clocks R8A7779_CLK_ZS>; - }; - - timer@f0000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf0000600 0x20>; - interrupts = ; - clocks = <&cpg_clocks R8A7779_CLK_ZS>; - }; - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc40000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc41000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc42000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc43000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc44000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@ffc45000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc45000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc46000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 9>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - irqpin0: interrupt-controller@fe78001c { - compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - status = "disabled"; - interrupt-controller; - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>, - <0xfe780000 4>; - interrupts = , - , - , - ; - sense-bitfield-width = <2>; - }; - - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc70000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C0>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc71000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C1>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <5>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc72000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C2>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <5>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc73000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C3>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <5>; - status = "disabled"; - }; - - scif0: serial@ffe40000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe40000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@ffe41000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe41000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@ffe42000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe42000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@ffe43000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe43000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif4: serial@ffe44000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe44000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif5: serial@ffe45000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe45000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@ffe48000 { - compatible = "renesas,hscif-r8a7779", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe48000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, - <&cpg_clocks R8A7779_CLK_S>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@ffe49000 { - compatible = "renesas,hscif-r8a7779", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe49000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, - <&cpg_clocks R8A7779_CLK_S>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm0: pwm@ffe50000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe50000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@ffe51000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe51000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@ffe52000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe52000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@ffe53000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe53000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@ffe54000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe54000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@ffe55000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe55000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@ffe56000 { - compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; - reg = <0xffe56000 0x8>; - clocks = <&mstp0_clks R8A7779_CLK_PWM>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pfc: pinctrl@fffc0000 { - compatible = "renesas,pfc-r8a7779"; - reg = <0xfffc0000 0x23c>; - }; - - thermal@ffc48000 { - compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; - }; - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@ffd81000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd81000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu2: timer@ffd82000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd82000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU2>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779"; - reg = <0xfc600000 0x200000>; - interrupts = ; - clocks = <&mstp1_clks R8A7779_CLK_SATA>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi0: mmc@ffe4c000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4c000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: mmc@ffe4d000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4d000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: mmc@ffe4e000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4e000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi3: mmc@ffe4f000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4f000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi1: spi@fffc8000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc8000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi2: spi@fffc6000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc6000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - du: display@fff80000 { - compatible = "renesas,du-r8a7779"; - reg = <0xfff80000 0x40000>; - interrupts = ; - clocks = <&mstp1_clks R8A7779_CLK_DU>; - clock-names = "du.0"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: clocks@ffc80000 { - compatible = "renesas,r8a7779-cpg-clocks"; - reg = <0xffc80000 0x30>; - clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "plla", "z", "zs", "s", - "s1", "p", "b", "out"; - #power-domain-cells = <0>; - }; - - /* Fixed factor clocks */ - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - s3_clk: s3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - s4_clk: s4 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <16>; - clock-mult = <1>; - }; - g_clk: g { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: clocks@ffc80030 { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_PWM R8A7779_CLK_HSPI - R8A7779_CLK_TMU2 R8A7779_CLK_TMU1 - R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1 - R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5 - R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3 - R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1 - R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 - R8A7779_CLK_I2C2 R8A7779_CLK_I2C1 - R8A7779_CLK_I2C0 - >; - clock-output-names = - "pwm", "hspi", "tmu2", "tmu1", "tmu0", - "hscif1", "hscif0", "scif5", "scif4", "scif3", - "scif2", "scif1", "scif0", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; - mstp1_clks: clocks@ffc80034 { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc80034 4>, <0xffc80044 4>; - clocks = <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_USB01 R8A7779_CLK_USB2 - R8A7779_CLK_DU R8A7779_CLK_VIN2 - R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 - R8A7779_CLK_ETHER R8A7779_CLK_SATA - R8A7779_CLK_PCIE R8A7779_CLK_VIN3 - >; - clock-output-names = - "usb01", "usb2", - "du", "vin2", - "vin1", "vin0", - "ether", "sata", - "pcie", "vin3"; - }; - mstp3_clks: clocks@ffc8003c { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc8003c 4>; - clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, - <&s4_clk>, <&s4_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 - R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 - R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 - >; - clock-output-names = - "sdhi3", "sdhi2", "sdhi1", "sdhi0", - "mmc1", "mmc0"; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0xff000044 4>; - }; - - rst: reset-controller@ffcc0000 { - compatible = "renesas,r8a7779-reset-wdt"; - reg = <0xffcc0000 0x48>; - }; - - sysc: system-controller@ffd85000 { - compatible = "renesas,r8a7779-sysc"; - reg = <0xffd85000 0x0200>; - #power-domain-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts deleted file mode 100644 index 5ad5349a50dc..000000000000 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ /dev/null @@ -1,947 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Lager board - * - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - * Copyright (C) 2015-2016 Renesas Electronics Corporation - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Lager"; - compatible = "renesas,lager", "renesas,r8a7790"; - - aliases { - serial0 = &scif0; - serial1 = &scifa1; - i2c8 = &gpioi2c1; - i2c9 = &gpioi2c2; - i2c10 = &i2cexio0; - i2c11 = &i2cexio1; - i2c12 = &i2chdmi; - i2c13 = &i2cpwr; - mmc0 = &mmcif1; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@140000000 { - device_type = "memory"; - reg = <1 0x40000000 0 0xc0000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - one { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - two { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - three { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - four { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-8 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. - * We use the I2C demuxer, so the desired IP core can be selected at runtime - * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0). - * Note: For testing the I2C slave feature, it is convenient to connect this - * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and - * instantiate the slave device at runtime according to the documentation. - * You can then communicate with the slave via IIC3. - * - * IIC0/I2C0 does not appear to support fallback to GPIO. - */ - i2cexio0: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic0>, <&i2c0>; - i2c-bus-name = "i2c-exio0"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). - * This is similar to the arangement described for i2cexio0 (above) - * with a fallback to GPIO also provided. - */ - i2cexio1: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-exio1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * IIC2 and I2C2 may be switched using pinmux. - * A fallback to GPIO is also provided. - */ - i2chdmi: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - }; - - /* - * IIC3 and I2C3 may be switched using pinmux. - * IIC3/I2C3 does not appear to support fallback to GPIO. - */ - i2cpwr: i2c-13 { - compatible = "i2c-demux-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - i2c-parent = <&iic3>, <&i2c3>; - i2c-bus-name = "i2c-pwr"; - #address-cells = <1>; - #size-cells = <0>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds1 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - mmc1_pins: mmc1 { - groups = "mmc1_data8", "mmc1_ctrl"; - function = "mmc1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof1_pins: msiof1 { - groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", - "msiof1_tx"; - function = "msiof1"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - iic0_pins: iic0 { - groups = "iic0"; - function = "iic0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - iic1_pins: iic1 { - groups = "iic1"; - function = "iic1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - iic2_pins: iic2 { - groups = "iic2"; - function = "iic2"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3"; - function = "i2c3"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - hsusb_pins: hsusb { - groups = "usb0_ovc_vbus"; - function = "usb0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - keyboard_pins: keyboard { - pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28"; - bias-pull-up; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&mmcif1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&msiof1 { - pinctrl-0 = <&msiof1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "i2c-exio0"; -}; - -&iic0 { - pinctrl-0 = <&iic0_pins>; - pinctrl-names = "i2c-exio0"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&iic1 { - pinctrl-0 = <&iic1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&iic2 { - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "i2c-pwr"; -}; - -&iic3 { - pinctrl-0 = <&iic3_pins>; - pinctrl-names = "i2c-pwr"; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&xhci { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&pci2 { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&hsusb_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -/* HDMI video input */ -&vin0 { - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep0: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src2>, <&dvc0>; - capture = <&ssi1>, <&src3>, <&dvc1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts deleted file mode 100644 index fe14727eefe1..000000000000 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Stout board - * - * Copyright (C) 2018 Marek Vasut - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Stout"; - compatible = "renesas,stout", "renesas,r8a7790"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; - led2 { - gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; - }; - led3 { - gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - }; - led5 { - gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - osc1_clk: osc1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - osc4_clk: osc4-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&osc1_clk>; - clock-names = "du.0", "du.1", "du.2", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector0: endpoint { - }; - }; - }; -}; - -&lvds1 { - ports { - port@1 { - lvds_connector1: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb888", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scifa0_pins: scifa0 { - groups = "scifa0_data_b"; - function = "scifa0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq1"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - iic2_pins: iic2 { - groups = "iic2_b"; - function = "iic2"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "uboot"; - reg = <0x00080000 0x00040000>; - read-only; - }; - partition@c0000 { - label = "uboot-env"; - reg = <0x000c0000 0x00040000>; - read-only; - }; - partition@100000 { - label = "flash"; - reg = <0x00100000 0x03f00000>; - }; - }; - }; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&iic2 { - status = "okay"; - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "default"; - - clock-frequency = <100000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - clocks = <&osc4_clk>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&iic3 { - pinctrl-names = "default"; - pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd: regulator@70 { - compatible = "dlg,da9210"; - reg = <0x70>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi deleted file mode 100644 index 46fb81f5062f..000000000000 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ /dev/null @@ -1,1965 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H2 (R8A77900) SoC - * - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7790"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &iic0; - i2c5 = &iic1; - i2c6 = &iic2; - i2c7 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - spi4 = &msiof3; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU2>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU3>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU2>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU3>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu-0 { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - pmu-1 { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7790-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7790"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7790", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7790-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7790-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7790-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 300>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7790", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7790-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7790", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7790", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e56000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 215>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 215>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7790", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7790", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7790", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7790_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; - - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x20800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x21000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7790", - "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 305>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 305>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7790", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 130>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 130>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 117>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7790"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds@feb94000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb94000 0 0x1c>; - clocks = <&cpg CPG_MOD 725>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 725>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts deleted file mode 100644 index 26a40782cc89..000000000000 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ /dev/null @@ -1,912 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include -#include - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - i2c9 = &gpioi2c1; - i2c10 = &gpioi2c2; - i2c11 = &gpioi2c4; - i2c12 = &i2cexio1; - i2c13 = &i2chdmi; - i2c14 = &i2cexio4; - mmc0 = &sdhi0; - mmc1 = &sdhi1; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c2: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c4: i2c-11 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio1: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-exio1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-13 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-14 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_c"; - function = "i2c4"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof0_pins: msiof0 { - groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", - "msiof0_tx"; - function = "msiof0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - keyboard_pins: keyboard { - pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; - bias-pull-up; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x00580000>; - read-only; - }; - partition@600000 { - label = "flash"; - reg = <0x00600000 0x03a00000>; - }; - }; - }; -}; - -&msiof0 { - pinctrl-0 = <&msiof0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* HDMI video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - status = "okay"; - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - port { - vin1ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src2>, <&dvc0>; - capture = <&ssi1>, <&src3>, <&dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts deleted file mode 100644 index ec0a20d5130d..000000000000 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ /dev/null @@ -1,523 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Porter board - * - * Copyright (C) 2015 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4642 - * - * JP3: 2-1: AK4642 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include - -/ { - model = "Porter"; - compatible = "renesas,porter", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - i2c9 = &gpioi2c2; - i2c10 = &i2chdmi; - mmc0 = &sdhi0; - mmc1 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x16_clk: x16-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x14_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4642>; - clocks = <&x14_clk>; - }; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4642: codec@12 { - compatible = "asahi-kasei,ak4642"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader_prg"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user_prg"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash_fs"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@5a { - compatible = "dlg,da9063l"; - reg = <0x5a>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&sata0 { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pci1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hsusb { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x3_clk>, <&x16_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi deleted file mode 100644 index b9d34147628e..000000000000 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ /dev/null @@ -1,1891 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M2-W (R8A77910) SoC - * - * Copyright (C) 2013-2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7791"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - power-domains = <&sysc R8A7791_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - power-domains = <&sysc R8A7791_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7791-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7791"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7791", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7791-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7791-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7791", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7791", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7791", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7791", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7791-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7791-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7791", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - adc: adc@e6e54000 { - compatible = "renesas,r8a7791-gyroadc", - "renesas,rcar-gyroadc"; - reg = <0 0xe6e54000 0 64>; - clocks = <&cpg CPG_MOD 901>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 901>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7791", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7791", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7791_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", "src.9", "src.8", - "src.7", "src.6", "src.5", "src.4", - "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7791", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7791", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7791", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7791"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7791-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7791-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7791-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts deleted file mode 100644 index c66de9dd12df..000000000000 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Blanche board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Blanche"; - compatible = "renesas,blanche", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - serial1 = &scif3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x1_clk: x1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x2_clk: x2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-1 { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - }; - key-2 { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - }; - key-3 { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - }; - key-4 { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - key-a { - linux,code = ; - label = "SW24"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW25"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led17 { - gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; - }; - led18 { - gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; - }; - led19 { - gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; - }; - led20 { - gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&can_clk { - clock-frequency = <48000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif3_pins: scif3 { - groups = "scif3_data"; - function = "scif3"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data", "can_clk"; - function = "can0"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp"; - function = "du1"; - }; - - keyboard_pins: keyboard { - pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02"; - bias-pull-up; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif3 { - pinctrl-0 = <&scif3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&irqc>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&iic3 { - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - interrupt-parent = <&irqc>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins>, <&du1_pins>; - pinctrl-names = "default"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts deleted file mode 100644 index 434e4655be9d..000000000000 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Wheat board - * - * Copyright (C) 2016 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Wheat"; - compatible = "renesas,wheat", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - smsc,save-mac-address; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - keyboard { - compatible = "gpio-keys"; - - key-a { - linux,code = ; - label = "SW2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-out0 { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con0: endpoint { - remote-endpoint = <&adv7513_0_out>; - }; - }; - }; - - hdmi-out1 { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con1: endpoint { - remote-endpoint = <&adv7513_1_out>; - }; - }; - }; - - osc2_clk: osc2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp"; - function = "du1"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - /* - * The adv75xx resets its addresses to defaults during low power mode. - * Because we have two ADV7513 devices on the same bus, we must change - * both of them away from the defaults so that they do not conflict. - */ - hdmi@3d { - compatible = "adi,adv7513"; - reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; - reg-names = "main", "edid", "cec", "packet"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_0_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7513_0_out: endpoint { - remote-endpoint = <&hdmi_con0>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7513"; - reg = <0x39>, <0x49>, <0x29>, <0x59>; - reg-names = "main", "edid", "cec", "packet"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_1_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - - port@1 { - reg = <1>; - adv7513_1_out: endpoint { - remote-endpoint = <&hdmi_con1>; - }; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins>, <&du1_pins>; - pinctrl-names = "default"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7513_0_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7513_1_in>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi deleted file mode 100644 index a6d9367f8fa0..000000000000 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ /dev/null @@ -1,928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V2H (R8A77920) SoC - * - * Copyright (C) 2016 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7792"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - vin4 = &vin4; - vin5 = &vin5; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7792_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7792-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055100 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055100 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055200 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055200 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - gpio8: gpio@e6055300 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055300 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 921>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 921>; - }; - - gpio9: gpio@e6055400 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 919>; - }; - - gpio10: gpio@e6055500 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055500 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 914>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 914>; - }; - - gpio11: gpio@e6055600 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055600 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 352 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 913>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 913>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7792"; - reg = <0 0xe6060000 0 0x144>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7792-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7792-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7792-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7792-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7792", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* I2C doesn't need pinmux */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7792", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7792", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7792", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7792", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7792", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 805>; - status = "disabled"; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 804>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7792", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7792", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7792"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7792-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7792-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts deleted file mode 100644 index 79b537b24642..000000000000 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ /dev/null @@ -1,818 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Gose board - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7793.dtsi" -#include -#include - -/ { - model = "Gose"; - compatible = "renesas,gose", "renesas,r8a7793"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - i2c9 = &gpioi2c2; - i2c10 = &gpioi2c4; - i2c11 = &i2chdmi; - i2c12 = &i2cexio4; - mmc0 = &sdhi0; - mmc1 = &sdhi1; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - composite-in { - compatible = "composite-video-connector"; - - port { - composite_con_in: endpoint { - remote-endpoint = <&adv7180_in>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c4: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - adv7180_out: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_c"; - function = "i2c4"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - keyboard_pins: keyboard { - pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; - bias-pull-up; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - status = "okay"; - clock-frequency = <100000>; - -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src2>, <&dvc0>; - capture = <&ssi1>, <&src3>, <&dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; - -/* HDMI video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep: endpoint { - remote-endpoint = <&adv7180_out>; - bus-width = <8>; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi deleted file mode 100644 index f51bf687f4bd..000000000000 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ /dev/null @@ -1,1470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M2-N (R8A77930) SoC - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7793"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - power-domains = <&sysc R8A7793_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - power-domains = <&sysc R8A7793_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7793_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7793-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7793"; - reg = <0 0xe6060000 0 0x250>; - }; - - /* Special CPG clocks */ - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7793-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7793-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7793-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7793-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7793", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7793", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7793", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7793", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7793", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7793", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7793_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7793", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7793"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7793-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 726>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7793-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7793-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts deleted file mode 100644 index 4d93319674c6..000000000000 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Alt board - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include -#include - -/ { - model = "Alt"; - compatible = "renesas,alt", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - i2c9 = &gpioi2c1; - i2c10 = &gpioi2c4; - i2c11 = &i2chdmi; - i2c12 = &i2cexio4; - mmc0 = &mmcif0; - mmc1 = &sdhi0; - mmc2 = &sdhi1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - one { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - }; - two { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - }; - three { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - }; - four { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - }; - - gpioi2c4: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C1. - */ - i2chdmi: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-14 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4"; - function = "i2c4"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - keyboard_pins: keyboard { - pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; - bias-pull-up; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&pfc { - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "system"; - reg = <0x00040000 0x00040000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x03f80000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts deleted file mode 100644 index b7af1befa126..000000000000 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ /dev/null @@ -1,578 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SILK board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014-2015 Renesas Solutions Corp. - * Copyright (C) 2014-2015 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4643 - * - * SW1: 2-1: AK4643 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include -#include - -/ { - model = "SILK"; - compatible = "renesas,silk", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - i2c9 = &gpioi2c1; - i2c10 = &i2chdmi; - mmc0 = &mmcif0; - mmc1 = &sdhi1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-3 { - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4"; - wakeup-source; - debounce-interval = <20>; - }; - key-6 { - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW6"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-4"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x9_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&x9_clk>; - }; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C1. - */ - i2chdmi: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - keyboard_pins: keyboard { - pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; - bias-pull-up; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clkc"; - function = "audio_clk"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins>, <&du1_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x2_clk>, <&x3_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi deleted file mode 100644 index 371dd4715dde..000000000000 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ /dev/null @@ -1,1437 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car E2 (R8A77940) SoC - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014 Ulrich Hecht - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7794"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - spi0 = &qspi; - vin0 = &vin0; - vin1 = &vin1; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; - power-domains = <&sysc R8A7794_PD_CA7_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; - power-domains = <&sysc R8A7794_PD_CA7_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7794-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7794"; - reg = <0 0xe6060000 0 0x11c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7794-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7794-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7794-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7794-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7794", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 931>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 930>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 929>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 928>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 927>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 925>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e6500000 { - compatible = "renesas,iic-r8a7794", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 318>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@e6510000 { - compatible = "renesas,iic-r8a7794", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 323>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7794", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7794", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7794", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7794", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7794", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7794", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7794", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7794_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", - "src.2", "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7794", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7794", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7794", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7794"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7794-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7794-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi deleted file mode 100644 index 6e7589ea7562..000000000000 --- a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA121TD01 panel connected to Renesas R-Car boards - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - - width-mm = <261>; - height-mm = <163>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts deleted file mode 100644 index c18bbd7141c4..000000000000 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZN1D-DB Board - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - */ - -/dts-v1/; - -#include -#include - -#include "r9a06g032.dtsi" - -/ { - model = "RZN1D-DB Board"; - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; -}; - -&can0 { - pinctrl-0 = <&pins_can0>; - pinctrl-names = "default"; - - /* Assuming CN10/CN11 are wired for CAN1 */ - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&pins_can1>; - pinctrl-names = "default"; - - /* Please only enable can0 or can1, depending on CN10/CN11 */ - /* status = "okay"; */ -}; - -ð_miic { - status = "okay"; - renesas,miic-switch-portin = ; -}; - -&gmac2 { - status = "okay"; - phy-mode = "gmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&mii_conv4 { - renesas,miic-input = ; - status = "okay"; -}; - -&mii_conv5 { - renesas,miic-input = ; - status = "okay"; -}; - -&pinctrl{ - pins_can0: pins_can0 { - pinmux = , /* CAN0_TXD */ - ; /* CAN0_RXD */ - drive-strength = <6>; - }; - - pins_can1: pins_can1 { - pinmux = , /* CAN1_TXD */ - ; /* CAN1_RXD */ - drive-strength = <6>; - }; - - pins_eth3: pins_eth3 { - pinmux = , - , - , - , - , - , - , - , - , - , - , - ; - drive-strength = <6>; - bias-disable; - }; - - pins_eth4: pins_eth4 { - pinmux = , - , - , - , - , - , - , - , - , - , - , - ; - drive-strength = <6>; - bias-disable; - }; - - pins_mdio1: pins_mdio1 { - pinmux = , - ; - }; -}; - -&rtc0 { - status = "okay"; -}; - -&switch { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; - - dsa,member = <0 0>; - - mdio { - clock-frequency = <2500000>; - - #address-cells = <1>; - #size-cells = <0>; - - switch0phy4: ethernet-phy@4 { - reg = <4>; - micrel,led-mode = <1>; - }; - - switch0phy5: ethernet-phy@5 { - reg = <5>; - micrel,led-mode = <1>; - }; - }; -}; - -&switch_port0 { - label = "lan0"; - phy-mode = "mii"; - phy-handle = <&switch0phy5>; - status = "okay"; -}; - -&switch_port1 { - label = "lan1"; - phy-mode = "mii"; - phy-handle = <&switch0phy4>; - status = "okay"; -}; - -&switch_port4 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&wdt0 { - timeout-sec = <60>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi deleted file mode 100644 index 0fa565a1c3ad..000000000000 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ /dev/null @@ -1,477 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - */ - -#include -#include - -/ { - compatible = "renesas,r9a06g032"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clocks = <&sysctrl R9A06G032_CLK_A7MP>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clocks = <&sysctrl R9A06G032_CLK_A7MP>; - enable-method = "renesas,r9a06g032-smp"; - cpu-release-addr = <0 0x4000c204>; - }; - }; - - ext_jtag_clk: extjtagclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ext_mclk: extmclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - - ext_rgmii_ref: extrgmiiref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ext_rtc_clk: extrtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - rtc0: rtc@40006000 { - compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; - reg = <0x40006000 0x1000>; - interrupts = , - , - ; - interrupt-names = "alarm", "timer", "pps"; - clocks = <&sysctrl R9A06G032_HCLK_RTC>; - clock-names = "hclk"; - power-domains = <&sysctrl>; - status = "disabled"; - }; - - wdt0: watchdog@40008000 { - compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; - reg = <0x40008000 0x1000>; - interrupts = ; - clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; - status = "disabled"; - }; - - wdt1: watchdog@40009000 { - compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; - reg = <0x40009000 0x1000>; - interrupts = ; - clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; - status = "disabled"; - }; - - sysctrl: system-controller@4000c000 { - compatible = "renesas,r9a06g032-sysctrl"; - reg = <0x4000c000 0x1000>; - status = "okay"; - #clock-cells = <1>; - #power-domain-cells = <0>; - - clocks = <&ext_mclk>, <&ext_rtc_clk>, - <&ext_jtag_clk>, <&ext_rgmii_ref>; - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - #address-cells = <1>; - #size-cells = <1>; - - dmamux: dma-router@a0 { - compatible = "renesas,rzn1-dmamux"; - reg = <0xa0 4>; - #dma-cells = <6>; - dma-requests = <32>; - dma-masters = <&dma0 &dma1>; - }; - }; - - udc: usb@4001e000 { - compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; - reg = <0x4001e000 0x2000>; - interrupts = , - ; - clocks = <&sysctrl R9A06G032_HCLK_USBF>, - <&sysctrl R9A06G032_HCLK_USBPM>; - clock-names = "hclkf", "hclkpm"; - power-domains = <&sysctrl>; - status = "disabled"; - }; - - pci_usb: pci@40030000 { - compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; - device_type = "pci"; - clocks = <&sysctrl R9A06G032_HCLK_USBH>, - <&sysctrl R9A06G032_HCLK_USBPM>, - <&sysctrl R9A06G032_CLK_PCI_USB>; - clock-names = "hclkh", "hclkpm", "pciclk"; - power-domains = <&sysctrl>; - reg = <0x40030000 0xc00>, - <0x40020000 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; - /* Should map all possible DDR as inbound ranges, but - * the IP only supports a 256MB, 512MB, or 1GB window. - * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) - */ - dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usbphy>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usbphy>; - phy-names = "usb"; - }; - }; - - uart0: serial@40060000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; - reg = <0x40060000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart1: serial@40061000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; - reg = <0x40061000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@40062000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; - reg = <0x40062000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart3: serial@50000000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@50001000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50001000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@50002000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50002000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart6: serial@50003000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50003000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart7: serial@50004000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50004000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pinctrl: pinctrl@40067000 { - compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; - reg = <0x40067000 0x1000>, <0x51000000 0x480>; - clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; - clock-names = "bus"; - status = "okay"; - }; - - nand_controller: nand-controller@40102000 { - compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; - reg = <0x40102000 0x2000>; - interrupts = ; - clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; - clock-names = "hclk", "eclk"; - power-domains = <&sysctrl>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dma0: dma-controller@40104000 { - compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; - reg = <0x40104000 0x1000>; - interrupts = ; - clock-names = "hclk"; - clocks = <&sysctrl R9A06G032_HCLK_DMA0>; - dma-channels = <8>; - dma-requests = <16>; - dma-masters = <1>; - #dma-cells = <3>; - block_size = <0xfff>; - data-width = <8>; - }; - - dma1: dma-controller@40105000 { - compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; - reg = <0x40105000 0x1000>; - interrupts = ; - clock-names = "hclk"; - clocks = <&sysctrl R9A06G032_HCLK_DMA1>; - dma-channels = <8>; - dma-requests = <16>; - dma-masters = <1>; - #dma-cells = <3>; - block_size = <0xfff>; - data-width = <8>; - }; - - gmac2: ethernet@44002000 { - compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; - reg = <0x44002000 0x2000>; - interrupt-parent = <&gic>; - interrupts = , - , - ; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; - clock-names = "stmmaceth"; - power-domains = <&sysctrl>; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <2048>; - rx-fifo-depth = <4096>; - status = "disabled"; - }; - - eth_miic: eth-miic@44030000 { - compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x44030000 0x10000>; - clocks = <&sysctrl R9A06G032_CLK_MII_REF>, - <&sysctrl R9A06G032_CLK_RGMII_REF>, - <&sysctrl R9A06G032_CLK_RMII_REF>, - <&sysctrl R9A06G032_HCLK_SWITCH_RG>; - clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; - power-domains = <&sysctrl>; - status = "disabled"; - - mii_conv1: mii-conv@1 { - reg = <1>; - status = "disabled"; - }; - - mii_conv2: mii-conv@2 { - reg = <2>; - status = "disabled"; - }; - - mii_conv3: mii-conv@3 { - reg = <3>; - status = "disabled"; - }; - - mii_conv4: mii-conv@4 { - reg = <4>; - status = "disabled"; - }; - - mii_conv5: mii-conv@5 { - reg = <5>; - status = "disabled"; - }; - }; - - switch: switch@44050000 { - compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; - reg = <0x44050000 0x10000>; - clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, - <&sysctrl R9A06G032_CLK_SWITCH>; - clock-names = "hclk", "clk"; - power-domains = <&sysctrl>; - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - switch_port0: port@0 { - reg = <0>; - pcs-handle = <&mii_conv5>; - status = "disabled"; - }; - - switch_port1: port@1 { - reg = <1>; - pcs-handle = <&mii_conv4>; - status = "disabled"; - }; - - switch_port2: port@2 { - reg = <2>; - pcs-handle = <&mii_conv3>; - status = "disabled"; - }; - - switch_port3: port@3 { - reg = <3>; - pcs-handle = <&mii_conv2>; - status = "disabled"; - }; - - switch_port4: port@4 { - reg = <4>; - ethernet = <&gmac2>; - label = "cpu"; - phy-mode = "internal"; - status = "disabled"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - gic: interrupt-controller@44101000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x44101000 0x1000>, /* Distributer */ - <0x44102000 0x2000>, /* CPU interface */ - <0x44104000 0x2000>, /* Virt interface control */ - <0x44106000 0x2000>; /* Virt CPU interface */ - interrupts = - ; - }; - - can0: can@52104000 { - compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; - reg = <0x52104000 0x800>; - reg-io-width = <4>; - interrupts = ; - clocks = <&sysctrl R9A06G032_HCLK_CAN0>; - power-domains = <&sysctrl>; - status = "disabled"; - }; - - can1: can@52105000 { - compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; - reg = <0x52105000 0x800>; - reg-io-width = <4>; - interrupts = ; - clocks = <&sysctrl R9A06G032_HCLK_CAN1>; - power-domains = <&sysctrl>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - arm,cpu-registers-not-fw-configured; - always-on; - interrupts = - , - , - , - ; - }; - - usbphy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts b/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts deleted file mode 100644 index 98e34248ae80..000000000000 --- a/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "rda8810pl.dtsi" - -/ { - compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; - model = "Orange Pi 2G-IoT"; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial2:921600n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&uart1 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart2 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart3 { - status = "okay"; - clocks = <&uart_clk>; -}; diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts b/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts deleted file mode 100644 index 728f76931b99..000000000000 --- a/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "rda8810pl.dtsi" - -/ { - compatible = "xunlong,orangepi-i96", "rda,8810pl"; - model = "Orange Pi i96"; - - aliases { - serial0 = &uart2; - serial1 = &uart1; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial2:921600n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&uart1 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart2 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart3 { - status = "okay"; - clocks = <&uart_clk>; -}; diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/rda8810pl.dtsi deleted file mode 100644 index f30d6ece49fb..000000000000 --- a/arch/arm/boot/dts/rda8810pl.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * RDA8810PL SoC - * - * Copyright (c) 2017 Andreas Färber - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -#include - -/ { - compatible = "rda,8810pl"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0x0>; - }; - }; - - sram@100000 { - compatible = "mmio-sram"; - reg = <0x100000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - modem@10000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000000 0xfffffff>; - - gpioc@1a08000 { - compatible = "rda,8810pl-gpio"; - reg = <0x1a08000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - }; - }; - - apb@20800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20800000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "rda,8810pl-intc"; - reg = <0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - apb@20900000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20900000 0x100000>; - - timer@10000 { - compatible = "rda,8810pl-timer"; - reg = <0x10000 0x1000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, - <17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hwtimer", "ostimer"; - }; - - gpioa@30000 { - compatible = "rda,8810pl-gpio"; - reg = <0x30000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - }; - - gpiob@31000 { - compatible = "rda,8810pl-gpio"; - reg = <0x31000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; - - gpiod@32000 { - compatible = "rda,8810pl-gpio"; - reg = <0x32000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - apb@20a00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20a00000 0x100000>; - - uart1: serial@0 { - compatible = "rda,8810pl-uart"; - reg = <0x0 0x1000>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart2: serial@10000 { - compatible = "rda,8810pl-uart"; - reg = <0x10000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart3: serial@90000 { - compatible = "rda,8810pl-uart"; - reg = <0x90000 0x1000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; - - l2: cache-controller@21100000 { - compatible = "arm,pl310-cache"; - reg = <0x21100000 0x1000>; - cache-unified; - cache-level = <2>; - }; -}; diff --git a/arch/arm/boot/dts/realtek/Makefile b/arch/arm/boot/dts/realtek/Makefile new file mode 100644 index 000000000000..c83671b5560f --- /dev/null +++ b/arch/arm/boot/dts/realtek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-horseradish.dtb \ + rtd1195-mele-x1000.dtb diff --git a/arch/arm/boot/dts/realtek/rtd1195-horseradish.dts b/arch/arm/boot/dts/realtek/rtd1195-horseradish.dts new file mode 100644 index 000000000000..9d06d3d34c74 --- /dev/null +++ b/arch/arm/boot/dts/realtek/rtd1195-horseradish.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "realtek,horseradish", "realtek,rtd1195"; + model = "Realtek Horseradish EVB"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts new file mode 100644 index 000000000000..c7951b9a2c97 --- /dev/null +++ b/arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "mele,x1000", "realtek,rtd1195"; + model = "MeLE X1000"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/realtek/rtd1195.dtsi b/arch/arm/boot/dts/realtek/rtd1195.dtsi new file mode 100644 index 000000000000..21897210d9d0 --- /dev/null +++ b/arch/arm/boot/dts/realtek/rtd1195.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/memreserve/ 0x00000000 0x0000a800; /* boot code */ +/memreserve/ 0x0000a800 0x000f5800; +/memreserve/ 0x17fff000 0x00001000; + +#include +#include + +/ { + compatible = "realtek,rtd1195"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1000000000>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@b000 { + reg = <0x0000b000 0x1000>; + }; + + audio@1b00000 { + reg = <0x01b00000 0x400000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x01ffe000 0x4000>; + }; + + secure@10000000 { + reg = <0x10000000 0x100000>; + no-map; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <27000000>; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x0000a800>, + <0x18000000 0x18000000 0x00070000>, + <0x18100000 0x18100000 0x01000000>, + <0x80000000 0x80000000 0x80000000>; + + rbus: bus@18000000 { + compatible = "simple-bus"; + reg = <0x18000000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x70000>; + + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; + }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x1000>; + }; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&reset2 RTD1195_RSTN_UR1>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..833a02447ecf --- /dev/null +++ b/arch/arm/boot/dts/renesas/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_RENESAS) += \ + emev2-kzm9d.dtb \ + r7s72100-genmai.dtb \ + r7s72100-gr-peach.dtb \ + r7s72100-rskrza1.dtb \ + r7s9210-rza2mevb.dtb \ + r8a73a4-ape6evm.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7742-iwg21d-q7.dtb \ + r8a7742-iwg21d-q7-dbcm-ca.dtb \ + r8a7743-iwg20d-q7.dtb \ + r8a7743-iwg20d-q7-dbcm-ca.dtb \ + r8a7743-sk-rzg1m.dtb \ + r8a7744-iwg20d-q7.dtb \ + r8a7744-iwg20d-q7-dbcm-ca.dtb \ + r8a7745-iwg22d-sodimm.dtb \ + r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ + r8a7745-sk-rzg1e.dtb \ + r8a77470-iwg23s-sbc.dtb \ + r8a7778-bockw.dtb \ + r8a7779-marzen.dtb \ + r8a7790-lager.dtb \ + r8a7790-stout.dtb \ + r8a7791-koelsch.dtb \ + r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ + r8a7792-wheat.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + r8a7794-silk.dtb \ + r9a06g032-rzn1d400-db.dtb \ + sh73a0-kzm9g.dtb diff --git a/arch/arm/boot/dts/renesas/emev2-kzm9d.dts b/arch/arm/boot/dts/renesas/emev2-kzm9d.dts new file mode 100644 index 000000000000..89495dd37358 --- /dev/null +++ b/arch/arm/boot/dts/renesas/emev2-kzm9d.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the KZM9D board + * + * Copyright (C) 2013 Renesas Solutions Corp. + */ +/dts-v1/; + +#include "emev2.dtsi" +#include +#include +#include + +/ { + model = "EMEV2 KZM9D Board"; + compatible = "renesas,kzm9d", "renesas,emev2"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x8000000>; + }; + + aliases { + serial1 = &uart1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial1:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + one { + debounce-interval = <50>; + wakeup-source; + label = "DSW2-1"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + two { + debounce-interval = <50>; + wakeup-source; + label = "DSW2-2"; + linux,code = ; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + three { + debounce-interval = <50>; + wakeup-source; + label = "DSW2-3"; + linux,code = ; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + four { + debounce-interval = <50>; + wakeup-source; + label = "DSW2-4"; + linux,code = ; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ethernet@20000000 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <0x20000000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; +}; + +&iic0 { + status = "okay"; +}; + +&iic1 { + status = "okay"; +}; + +&pfc { + uart1_pins: uart1 { + groups = "uart1_ctrl", "uart1_data"; + function = "uart1"; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/emev2.dtsi b/arch/arm/boot/dts/renesas/emev2.dtsi new file mode 100644 index 000000000000..ecfaa0b7523e --- /dev/null +++ b/arch/arm/boot/dts/renesas/emev2.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Emma Mobile EV2 SoC + * + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +#include +#include + +/ { + compatible = "renesas,emev2"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &iic0; + i2c1 = &iic1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <533000000>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clock-frequency = <533000000>; + }; + }; + + gic: interrupt-controller@e0020000 { + compatible = "arm,pl390"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xe0028000 0x1000>, + <0xe0020000 0x0100>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + clocks@e0110000 { + compatible = "renesas,emev2-smu"; + reg = <0xe0110000 0x10000>; + #address-cells = <2>; + #size-cells = <0>; + + c32ki: c32ki { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + iic0_sclkdiv: iic0_sclkdiv@624,0 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x624 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + iic0_sclk: iic0_sclk@48c,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x48c 1>; + clocks = <&iic0_sclkdiv>; + #clock-cells = <0>; + }; + iic1_sclkdiv: iic1_sclkdiv@624,16 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x624 16>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + iic1_sclk: iic1_sclk@490,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x490 1>; + clocks = <&iic1_sclkdiv>; + #clock-cells = <0>; + }; + pll3_fo: pll3_fo { + compatible = "fixed-factor-clock"; + clocks = <&c32ki>; + clock-div = <1>; + clock-mult = <7000>; + #clock-cells = <0>; + }; + usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x610 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x65c 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x65c 16>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x660 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usia_u0_sclk: usia_u0_sclk@4a0,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4a0 1>; + clocks = <&usia_u0_sclkdiv>; + #clock-cells = <0>; + }; + usib_u1_sclk: usib_u1_sclk@4b8,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4b8 1>; + clocks = <&usib_u1_sclkdiv>; + #clock-cells = <0>; + }; + usib_u2_sclk: usib_u2_sclk@4bc,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4bc 1>; + clocks = <&usib_u2_sclkdiv>; + #clock-cells = <0>; + }; + usib_u3_sclk: usib_u3_sclk@4c0,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4c0 1>; + clocks = <&usib_u3_sclkdiv>; + #clock-cells = <0>; + }; + sti_sclk: sti_sclk@528,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x528 1>; + clocks = <&c32ki>; + #clock-cells = <0>; + }; + }; + + timer@e0180000 { + compatible = "renesas,em-sti"; + reg = <0xe0180000 0x54>; + interrupts = ; + clocks = <&sti_sclk>; + clock-names = "sclk"; + }; + + uart0: serial@e1020000 { + compatible = "renesas,em-uart"; + reg = <0xe1020000 0x38>; + interrupts = ; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; + }; + + uart1: serial@e1030000 { + compatible = "renesas,em-uart"; + reg = <0xe1030000 0x38>; + interrupts = ; + clocks = <&usib_u1_sclk>; + clock-names = "sclk"; + }; + + uart2: serial@e1040000 { + compatible = "renesas,em-uart"; + reg = <0xe1040000 0x38>; + interrupts = ; + clocks = <&usib_u2_sclk>; + clock-names = "sclk"; + }; + + uart3: serial@e1050000 { + compatible = "renesas,em-uart"; + reg = <0xe1050000 0x38>; + interrupts = ; + clocks = <&usib_u3_sclk>; + clock-names = "sclk"; + }; + + pfc: pinctrl@e0140200 { + compatible = "renesas,pfc-emev2"; + reg = <0xe0140200 0x100>; + }; + + gpio0: gpio@e0050000 { + compatible = "renesas,em-gio"; + reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; + interrupts = , + ; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e0050080 { + compatible = "renesas,em-gio"; + reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; + interrupts = , + ; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e0050100 { + compatible = "renesas,em-gio"; + reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; + interrupts = , + ; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e0050180 { + compatible = "renesas,em-gio"; + reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; + interrupts = , + ; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@e0050200 { + compatible = "renesas,em-gio"; + reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; + interrupts = , + ; + gpio-controller; + gpio-ranges = <&pfc 0 128 31>; + #gpio-cells = <2>; + ngpios = <31>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + iic0: i2c@e0070000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe0070000 0x28>; + interrupts = ; + clocks = <&iic0_sclk>; + clock-names = "sclk"; + status = "disabled"; + }; + + iic1: i2c@e10a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe10a0000 0x28>; + interrupts = ; + clocks = <&iic1_sclk>; + clock-names = "sclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi new file mode 100644 index 000000000000..8d77579807ec --- /dev/null +++ b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the GR-Peach audiocamera shield expansion board + * + * Copyright (C) 2017 Jacopo Mondi + */ + +#include "r7s72100.dtsi" +#include +#include + +/ { + /* On-board camera clock. */ + camera_clk: camera_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&pinctrl { + i2c1_pins: i2c1 { + /* P1_2 as SCL; P1_3 as SDA */ + pinmux = , ; + }; + + vio_pins: vio { + /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ + pinmux = , /* VIO_VD */ + , /* VIO_HD */ + , /* VIO_D0 */ + , /* VIO_D1 */ + , /* VIO_D2 */ + , /* VIO_D3 */ + , /* VIO_D4 */ + , /* VIO_D5 */ + , /* VIO_D6 */ + , /* VIO_D7 */ + ; /* VIO_CLK */ + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + camera@48 { + compatible = "aptina,mt9v111"; + reg = <0x48>; + + clocks = <&camera_clk>; + + port { + mt9v111_out: endpoint { + remote-endpoint = <&ceu_in>; + }; + }; + }; +}; + +&ceu { + pinctrl-names = "default"; + pinctrl-0 = <&vio_pins>; + + status = "okay"; + + port { + ceu_in: endpoint { + remote-endpoint = <&mt9v111_out>; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi new file mode 100644 index 000000000000..4351c5a02fa5 --- /dev/null +++ b/arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/ { + aliases { + serial0 = &scif0; + serial3 = &scifb1; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + lcd_backlight: backlight { + compatible = "pwm-backlight"; + + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + }; + + lvds-receiver { + compatible = "ti,ds90cf384a", "lvds-decoder"; + power-supply = <&vcc_3v3_tft1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_receiver_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + port@1 { + reg = <1>; + lvds_receiver_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0dh6"; + backlight = <&lcd_backlight>; + power-supply = <&vcc_3v3_tft1>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_receiver_out>; + }; + }; + }; + + reg_1p5v: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + + vcc_3v3_tft1: regulator-panel { + compatible = "regulator-fixed"; + + regulator-name = "vcc-3v3-tft1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <500>; + gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&cmt0 { + status = "okay"; +}; + +&du { + status = "okay"; +}; + +&gpio2 { + touch-interrupt-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + input; + }; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p5v>; + }; + + touch: touchpanel@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <&vcc_3v3_tft1>; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&lvds_receiver_in>; + }; + }; + }; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pfc { + can0_pins: can0 { + groups = "can0_data_d"; + function = "can0"; + }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + pwm3_pins: pwm3 { + groups = "pwm3"; + function = "pwm3"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + scifb1_pins: scifb1 { + groups = "scifb1_data_d", "scifb1_ctrl"; + function = "scifb1"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&pwm3 { + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi1>, <&src3>, <&dvc1>; + capture = <&ssi0>, <&src2>, <&dvc0>; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scifb1 { + pinctrl-0 = <&scifb1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi new file mode 100644 index 000000000000..e10f99278c77 --- /dev/null +++ b/arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +/ { + aliases { + serial1 = &scif1; + serial4 = &hscif1; + }; + + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&pfc { + can1_pins: can1 { + groups = "can1_data_d"; + function = "can1"; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; + function = "du"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data_c", "hscif1_ctrl_c"; + function = "hscif1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_d"; + function = "scif1"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts new file mode 100644 index 000000000000..1e8447176b10 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Genmai board + * + * Copyright (C) 2013-14 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering + */ + +/dts-v1/; +#include "r7s72100.dtsi" +#include +#include + +/ { + model = "Genmai"; + compatible = "renesas,genmai", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x08000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port4 10 GPIO_ACTIVE_LOW>; + }; + + led2 { + gpios = <&port4 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + + scif2_pins: serial2 { + /* P3_0 as TxD2; P3_2 as RxD2 */ + pinmux = , ; + }; + + i2c2_pins: i2c2 { + /* RIIC2: P1_4 as SCL, P1_5 as SDA */ + pinmux = , ; + }; + + ether_pins: ether { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = ,/* P1_14 = ET_COL */ + , /* P5_9 = ET_MDC */ + , /* P3_3 = ET_MDIO */ + , /* P3_4 = ET_RXCLK */ + , /* P3_5 = ET_RXER */ + , /* P3_6 = ET_RXDV */ + , /* P2_0 = ET_TXCLK */ + , /* P2_1 = ET_TXER */ + , /* P2_2 = ET_TXEN */ + , /* P2_3 = ET_CRS */ + , /* P2_4 = ET_TXD0 */ + , /* P2_5 = ET_TXD1 */ + , /* P2_6 = ET_TXD2 */ + , /* P2_7 = ET_TXD3 */ + , /* P2_8 = ET_RXD0 */ + , /* P2_9 = ET_RXD1 */ + ,/* P2_10 = ET_RXD2 */ + ;/* P2_11 = ET_RXD3 */ + }; +}; + +&extal_clk { + clock-frequency = <13330000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&rtc_x1_clk { + clock-frequency = <32768>; +}; + +&mtu2 { + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-idb824.2814", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + eeprom@50 { + compatible = "renesas,r1ex24128", "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&rtc { + status = "okay"; +}; + +&scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + + status = "okay"; +}; + +&spi4 { + status = "okay"; + + codec: codec@0 { + compatible = "wlf,wm8978"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts new file mode 100644 index 000000000000..105f9c71f9fd --- /dev/null +++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the GR-Peach board + * + * Copyright (C) 2017 Jacopo Mondi + * Copyright (C) 2016 Renesas Electronics + */ + +/dts-v1/; +#include "r7s72100.dtsi" +#include +#include + +/ { + model = "GR-Peach"; + compatible = "renesas,gr-peach", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x00a00000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + flash@18000000 { + compatible = "mtd-rom"; + probe-type = "map_rom"; + reg = <0x18000000 0x00800000>; + bank-width = <4>; + device-width = <1>; + + clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; + power-domains = <&cpg_clocks>; + + #address-cells = <1>; + #size-cells = <1>; + + rootfs@600000 { + label = "rootfs"; + reg = <0x00600000 0x00200000>; + }; + }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port6 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + scif2_pins: serial2 { + /* P6_2 as RxD2; P6_3 as TxD2 */ + pinmux = , ; + }; + + ether_pins: ether { + /* Ethernet on Ports 1,3,5,10 */ + pinmux = , /* P1_14 = ET_COL */ + , /* P3_0 = ET_TXCLK */ + , /* P3_3 = ET_MDIO */ + , /* P3_4 = ET_RXCLK */ + , /* P3_5 = ET_RXER */ + , /* P3_6 = ET_RXDV */ + , /* P5_9 = ET_MDC */ + , /* P10_1 = ET_TXER */ + , /* P10_2 = ET_TXEN */ + , /* P10_3 = ET_CRS */ + , /* P10_4 = ET_TXD0 */ + , /* P10_5 = ET_TXD1 */ + , /* P10_6 = ET_TXD2 */ + , /* P10_7 = ET_TXD3 */ + , /* P10_8 = ET_RXD0 */ + , /* P10_9 = ET_RXD1 */ + ,/* P10_10 = ET_RXD2 */ + ;/* P10_11 = ET_RXD3 */ + }; +}; + +&extal_clk { + clock-frequency = <13333000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&mtu2 { + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <5>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts new file mode 100644 index 000000000000..1c5acf694407 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/A1H RSK board + * + * Copyright (C) 2016 Renesas Electronics + */ + +/dts-v1/; +#include "r7s72100.dtsi" +#include +#include +#include + +/ { + model = "RSKRZA1"; + compatible = "renesas,rskrza1", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x02000000>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + key-1 { + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW1"; + wakeup-source; + }; + + key-2 { + interrupt-parent = <&irqc>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW2"; + wakeup-source; + }; + + key-3 { + interrupt-parent = <&irqc>; + interrupts = <5 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW3"; + wakeup-source; + }; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&port7 1 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>; + }; + + led2 { + gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>; + }; + + led3 { + gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&extal_clk { + clock-frequency = <13330000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + clock-frequency = <400000>; + + io_expander1: gpio@20 { + compatible = "onnn,cat9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander2: gpio@21 { + compatible = "onnn,cat9554"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "renesas,r1ex24016", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&rtc_x1_clk { + clock-frequency = <32768>; +}; + +&pinctrl { + /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */ + i2c3_pins: i2c3 { + pinmux = , /* RIIC3SCL */ + ; /* RIIC3SDA */ + }; + + keyboard_pins: keyboard { + pinmux = , /* IRQ3 */ + , /* IRQ2 */ + ; /* IRQ5 */ + }; + + /* Serial Console */ + scif2_pins: serial2 { + pinmux = , /* TxD2 */ + ; /* RxD2 */ + }; + + /* Ethernet */ + ether_pins: ether { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = , /* ET_COL */ + , /* ET_MDC */ + , /* ET_MDIO */ + , /* ET_RXCLK */ + , /* ET_RXER */ + , /* ET_RXDV */ + , /* ET_TXCLK */ + , /* ET_TXER */ + , /* ET_TXEN */ + , /* ET_CRS */ + , /* ET_TXD0 */ + , /* ET_TXD1 */ + , /* ET_TXD2 */ + , /* ET_TXD3 */ + , /* ET_RXD0 */ + , /* ET_RXD1 */ + , /* ET_RXD2 */ + ; /* ET_RXD3 */ + }; + + /* SDHI ch1 on CN1 */ + sdhi1_pins: sdhi1 { + pinmux = , /* SD_CD_1 */ + , /* SD_WP_1 */ + , /* SD_D1_1 */ + , /* SD_D0_1 */ + , /* SD_CLK_1 */ + , /* SD_CMD_1 */ + , /* SD_D3_1 */ + ; /* SD_D2_1 */ + }; +}; + +&mtu2 { + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-idb824.2814", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&sdhi1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; + bus-width = <4>; + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi new file mode 100644 index 000000000000..b07b71307f24 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r7s72100 SoC + * + * Copyright (C) 2013-14 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering + */ + +#include +#include +#include + +/ { + compatible = "renesas,r7s72100"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + + /* Fixed factor clocks */ + b_clk: b { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <3>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; + next-level-cache = <&L2>; + }; + }; + + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; + + p0_clk: p0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <12>; + }; + + p1_clk: p1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <6>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 32678 */ + clock-frequency = <0>; + }; + + rtc_x3_clk: rtc_x3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 4000000 */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e8009800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif6: serial@e800a000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif7: serial@e800a800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + spi0: spi@e800c800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800c800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@e800d000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d000 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@e800d800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@e800e000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e000 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@e800e800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usbhs0: usb@e8010000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8010000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB0>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + usbhs1: usb@e8207000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8207000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB1>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + mmcif: mmc@e804c800 { + compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; + reg = <0xe804c800 0x80>; + interrupts = , + , + ; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + power-domains = <&cpg_clocks>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; + }; + + sdhi0: mmc@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = , + , + ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: mmc@e804e800 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e800 0x100>; + interrupts = , + , + ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, + <&mstp12_clks R7S72100_CLK_SDHI11>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + gic: interrupt-controller@e8201000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8201000 0x1000>, + <0xe8202000 0x1000>; + }; + + ether: ethernet@e8203000 { + compatible = "renesas,ether-r7s72100"; + reg = <0xe8203000 0x800>, + <0xe8204800 0x200>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ceu: camera@e8210000 { + reg = <0xe8210000 0x3000>; + compatible = "renesas,r7s72100-ceu"; + interrupts = ; + clocks = <&mstp6_clks R7S72100_CLK_CEU>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + wdt: watchdog@fcfe0000 { + compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; + reg = <0xfcfe0000 0x6>; + interrupts = ; + clocks = <&p0_clk>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-cpg-clocks", + "renesas,rz-cpg-clocks"; + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; + #power-domain-cells = <0>; + }; + + /* MSTP clocks */ + mstp3_clks: mstp3_clks@fcfe0420 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0420 4>; + clocks = <&p0_clk>; + clock-indices = ; + clock-output-names = "mtu2"; + }; + + mstp4_clks: mstp4_clks@fcfe0424 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0424 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 + R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 + >; + clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; + }; + + mstp5_clks: mstp5_clks@fcfe0428 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0428 4>; + clocks = <&p0_clk>, <&p0_clk>; + clock-indices = ; + clock-output-names = "ostm0", "ostm1"; + }; + + mstp6_clks: mstp6_clks@fcfe042c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe042c 4>; + clocks = <&b_clk>, <&p0_clk>; + clock-indices = ; + clock-output-names = "ceu", "rtc"; + }; + + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; + clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = ; + clock-output-names = "ether", "usb0", "usb1"; + }; + + mstp8_clks: mstp8_clks@fcfe0434 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0434 4>; + clocks = <&p1_clk>; + clock-indices = ; + clock-output-names = "mmcif"; + }; + + mstp9_clks: mstp9_clks@fcfe0438 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0438 4>; + clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; + clock-indices = < + R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 + R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 + >; + clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; + }; + + mstp10_clks: mstp10_clks@fcfe043c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe043c 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>; + clock-indices = < + R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 + R7S72100_CLK_SPI4 + >; + clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; + }; + mstp12_clks: mstp12_clks@fcfe0444 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0444 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 + R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 + >; + clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; + }; + + pinctrl: pinctrl@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + port0: gpio-0 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 6>; + }; + + port1: gpio-1 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + port2: gpio-2 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + port4: gpio-4 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + port5: gpio-5 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 80 11>; + }; + + port6: gpio-6 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + port7: gpio-7 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + port8: gpio-8 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + port9: gpio-9 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 144 8>; + }; + + port10: gpio-10 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 160 16>; + }; + + port11: gpio-11 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 176 16>; + }; + }; + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c1: i2c@fcfee400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee400 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c2: i2c@fcfee800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee800 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c3: i2c@fcfeec00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfeec00 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + irqc: interrupt-controller@fcfef800 { + compatible = "renesas,r7s72100-irqc", + "renesas,rza1-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xfcfef800 0x6>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <7 0>; + }; + + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = ; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + rtc: rtc@fcff1000 { + compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; + reg = <0xfcff1000 0x2e>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, + <&rtc_x3_clk>, <&extal_clk>; + clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + }; + + usb_x1_clk: usb_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts new file mode 100644 index 000000000000..69a5a44b8a2f --- /dev/null +++ b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZA2MEVB board + * + * Copyright (C) 2018 Renesas Electronics + * + * As upstream Linux does not support XIP, it cannot run in 8 MiB of HyperRAM. + * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has + * the following ramifications: + * - SCIF4 connected to the on-board USB-serial can no longer be used as the + * serial console, + * - Instead, SCIF2 is used as the serial console, by connecting a 3.3V TTL + * USB-to-Serial adapter to the CMOS camera connector: + * - RXD = CN17-9, + * - TXD = CN17-10, + * - GND = CN17-2 or CN17-17, + * - The first Ethernet channel can no longer be used, + * - USB Channel 1 loses the overcurrent input signal. + * + * Please make sure your sub-board matches the following switch settings: + * + * SW6 SW6-1 set to SDRAM + * ON SW6-2 set to Audio + * +---------------------+ SW6-3 set to DRP + * | = = = = = | SW6-4 set to CEU + * | = = | SW6-5 set to Ether2 + * | 1 2 3 4 5 6 7 8 9 0 | SW6-6 set to VDC6 + * +---------------------+ SW6-7 set to VDC6 + */ + +/dts-v1/; +#include "r7s9210.dtsi" +#include +#include +#include + +/ { + model = "RZA2MEVB"; + compatible = "renesas,rza2mevb", "renesas,r7s9210"; + + aliases { + serial0 = &scif2; + ethernet0 = ðer1; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + key-3 { + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW3"; + wakeup-source; + }; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + leds { + compatible = "gpio-leds"; + + led-red { + gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; + }; + led-green { + gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x04000000>; /* SDRAM */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ðer1 { + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c816", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +/* EXTAL */ +&extal_clk { + clock-frequency = <24000000>; /* 24MHz */ +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + eeprom@50 { + compatible = "renesas,r1ex24128", "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +/* High resolution System tick timers */ +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = , /* REF50CK0 */ + , /* RMMI0_TXDEN */ + , /* RMII0_TXD0 */ + , /* RMII0_TXD1 */ + , /* RMII0_CRSDV */ + , /* RMII0_RXD0 */ + , /* RMII0_RXD1 */ + , /* RMII0_RXER */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + ; /* IRQ4 */ + }; + + eth1_pins: eth1 { + pinmux = , /* REF50CK1 */ + , /* RMMI1_TXDEN */ + , /* RMII1_TXD0 */ + , /* RMII1_TXD1 */ + , /* RMII1_CRSDV */ + , /* RMII1_RXD0 */ + , /* RMII1_RXD1 */ + , /* RMII1_RXER */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + ; /* IRQ5 */ + }; + + i2c3_pins: i2c3 { + pinmux = , /* RIIC3SCL */ + ; /* RIIC3SDA */ + }; + + keyboard_pins: keyboard { + pinmux = ; /* IRQ0 */ + }; + + /* Serial Console */ + scif2_pins: serial2 { + pinmux = , /* TxD2 */ + ; /* RxD2 */ + }; + + sdhi0_pins: sdhi0 { + pinmux = , /* SD0_CD */ + ; /* SD0_WP */ + }; + + sdhi1_pins: sdhi1 { + pinmux = , /* SD1_CD */ + ; /* SD1_WP */ + }; + + usb0_pins: usb0 { + pinmux = , /* VBUSIN0 */ + , /* VBUSEN0 */ + ; /* OVRCUR0 */ + }; + + usb1_pins: usb1 { + pinmux = , /* VBUSIN1 */ + ; /* VBUSEN1 */ + }; +}; + +/* RTC_X1 */ +&rtc_x1_clk { + clock-frequency = <32768>; +}; + +/* Serial Console */ +&scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi0_pins>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; + bus-width = <4>; + status = "okay"; +}; + +/* USB-0 as Host */ +&usb2_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; /* Requires JP3 to be fitted */ + status = "okay"; +}; + +/* USB-1 as Host */ +&usb2_phy1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; + status = "okay"; +}; + +/* USB_X1 */ +&usb_x1_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm/boot/dts/renesas/r7s9210.dtsi b/arch/arm/boot/dts/renesas/r7s9210.dtsi new file mode 100644 index 000000000000..fdeb0bc12cb7 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r7s9210.dtsi @@ -0,0 +1,509 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R7S9210 SoC + * + * Copyright (C) 2018 Renesas Electronics Corporation + * + */ + +#include +#include + +/ { + compatible = "renesas,r7s9210"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* Value must be set by board */ + clock-frequency = <0>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value (32678) must be set by board */ + clock-frequency = <0>; + }; + + usb_x1_clk: usb_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value (48000000) must be set by board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <528000000>; + next-level-cache = <&L2>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + L2: cache-controller@1f003000 { + compatible = "arm,pl310-cache"; + reg = <0x1f003000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 47>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007800 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 46>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 45>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008800 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 44>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8009000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 43>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + spi0: spi@e800c800 { + compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; + reg = <0xe800c800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD 97>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@e800d000 { + compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; + reg = <0xe800d000 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD 96>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@e800d800 { + compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; + reg = <0xe800d800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD 95>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ether0: ethernet@e8204000 { + compatible = "renesas,ether-r7s9210"; + reg = <0xe8204000 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 65>; + power-domains = <&cpg>; + + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ether1: ethernet@e8204200 { + compatible = "renesas,ether-r7s9210"; + reg = <0xe8204200 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 64>; + power-domains = <&cpg>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@e803a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803a000 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 87>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@e803a400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803a400 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 86>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@e803a800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803a800 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 85>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@e803ac00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803ac00 0x44>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 84>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + ostm0: timer@e803b000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803b000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 36>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@e803c000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803c000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 35>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@e803d000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803d000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 34>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci0: usb@e8218000 { + compatible = "generic-ohci"; + reg = <0xe8218000 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 61>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@e8218100 { + compatible = "generic-ehci"; + reg = <0xe8218100 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 61>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@e8218200 { + compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; + reg = <0xe8218200 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>; + clock-names = "fck", "usb_x1"; + power-domains = <&cpg>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbhs0: usb@e8219000 { + compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; + reg = <0xe8219000 0x724>; + interrupts = ; + clocks = <&cpg CPG_MOD 61>; + renesas,buswait = <7>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@e821a000 { + compatible = "generic-ohci"; + reg = <0xe821a000 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 60>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@e821a100 { + compatible = "generic-ehci"; + reg = <0xe821a100 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 60>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@e821a200 { + compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; + reg = <0xe821a200 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>; + clock-names = "fck", "usb_x1"; + power-domains = <&cpg>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbhs1: usb@e821b000 { + compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; + reg = <0xe821b000 0x724>; + interrupts = ; + clocks = <&cpg CPG_MOD 60>; + renesas,buswait = <7>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi0: mmc@e8228000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe8228000 0x8c0>; + interrupts = ; + clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: mmc@e822a000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe822a000 0x8c0>; + interrupts = ; + clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + gic: interrupt-controller@e8221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8221000 0x1000>, + <0xe8222000 0x1000>; + }; + + cpg: clock-controller@fcfe0010 { + compatible = "renesas,r7s9210-cpg-mssr"; + reg = <0xfcfe0010 0x455>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + wdt: watchdog@fcfe7000 { + compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; + reg = <0xfcfe7000 0x26>; + interrupts = ; + clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; + }; + + bsid: chipid@fcfe8004 { + compatible = "renesas,bsid"; + reg = <0xfcfe8004 4>; + }; + + irqc: interrupt-controller@fcfef800 { + compatible = "renesas,r7s9210-irqc", + "renesas,rza1-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xfcfef800 0x6>; + interrupt-map = + <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <7 0>; + }; + + pinctrl: pinctrl@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts new file mode 100644 index 000000000000..e81a7213d304 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the APE6EVM board + * + * Copyright (C) 2013 Renesas Solutions Corp. + */ + +/dts-v1/; +#include "r8a73a4.dtsi" +#include +#include + +/ { + model = "APE6EVM"; + compatible = "renesas,ape6evm", "renesas,r8a73a4"; + + aliases { + serial0 = &scifa0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + vcc_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "MMC0 Vcc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vcc_sdhi0: regulator-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */ + ape6evm_fixed_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ape6evm_fixed_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; + label = "GNSS_EN"; + }; + led2 { + gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; + label = "NFC_NRST"; + }; + led3 { + gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; + label = "GNSS_NRST"; + }; + led4 { + gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; + label = "BT_WAKEUP"; + }; + led5 { + gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; + label = "STROBE"; + }; + led6 { + gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; + label = "BBRESETOUT"; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + zero-key { + gpios = <&pfc 324 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "S16"; + wakeup-source; + }; + + menu-key { + gpios = <&pfc 325 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "S17"; + }; + + home-key { + gpios = <&pfc 326 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "S18"; + }; + + back-key { + gpios = <&pfc 327 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "S19"; + }; + + volup-key { + gpios = <&pfc 328 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "S20"; + }; + + voldown-key { + gpios = <&pfc 329 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "S21"; + }; + }; +}; + +&i2c5 { + status = "okay"; + vdd_dvfs: regulator@1b { + compatible = "maxim,max8973"; + reg = <0x1b>; + + regulator-min-microvolt = <935000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; + operating-points = <1950000 1115000>, /* kHz uV */ + <1462500 995000>; + voltage-tolerance = <1>; /* 1% */ +}; + +&bsc { + flash@0 { + compatible = "cfi-flash", "mtd-rom"; + reg = <0x0 0x08000000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "uboot-env"; + reg = <0x00040000 0x00040000>; + read-only; + }; + partition@80000 { + label = "flash"; + reg = <0x00080000 0x07f80000>; + }; + }; + }; + + ethernet@8000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x08000000 0x1000>; + interrupt-parent = <&irqc1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + reset-gpios = <&pfc 270 GPIO_ACTIVE_LOW>; + vdd33a-supply = <&ape6evm_fixed_3v3>; + vddvario-supply = <&ape6evm_fixed_1v8>; + }; +}; + +&cmt1 { + status = "okay"; +}; + +&pfc { + scifa0_pins: scifa0 { + groups = "scifa0_data"; + function = "scifa0"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl"; + function = "mmc0"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + function = "sdhi0"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + }; + + keyboard_pins: keyboard { + pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", + "PORT329"; + bias-pull-up; + }; +}; + +&mmcif0 { + vmmc-supply = <&vcc_mmc0>; + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "okay"; +}; + +&scifa0 { + pinctrl-0 = <&scifa0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + vmmc-supply = <&vcc_sdhi0>; + bus-width = <4>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdhi0_pins>; + status = "okay"; +}; + +&sdhi1 { + vmmc-supply = <&ape6evm_fixed_3v3>; + bus-width = <4>; + broken-cd; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi new file mode 100644 index 000000000000..c39066967053 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a73a4 SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a73a4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + clock-frequency = <1500000000>; + power-domains = <&pd_a2sl>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; + cache-level = <2>; + }; + }; + + ptm { + compatible = "arm,coresight-etm3x"; + power-domains = <&pd_d4>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + dbsc1: memory-controller@e6790000 { + compatible = "renesas,dbsc-r8a73a4"; + reg = <0 0xe6790000 0 0x10000>; + power-domains = <&pd_a3bc>; + }; + + dbsc2: memory-controller@e67a0000 { + compatible = "renesas,dbsc-r8a73a4"; + reg = <0 0xe67a0000 0 0x10000>; + power-domains = <&pd_a3bc>; + }; + + i2c5: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x428>; + interrupts = ; + clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; + power-domains = <&pd_a3sp>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; + status = "disabled"; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; + power-domains = <&pd_c4>; + }; + + irqc1: interrupt-controller@e61c0200 { + compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0200 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; + power-domains = <&pd_c4>; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a73a4"; + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&pfc 0 0 31>, <&pfc 32 32 9>, + <&pfc 64 64 22>, <&pfc 96 96 31>, + <&pfc 128 128 7>, <&pfc 160 160 19>, + <&pfc 192 192 31>, <&pfc 224 224 27>, + <&pfc 256 256 28>, <&pfc 288 288 21>, + <&pfc 320 320 10>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; + power-domains = <&pd_c5>; + }; + + thermal@e61f0000 { + compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, + <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; + interrupts = ; + clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; + power-domains = <&pd_c5>; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x428>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x428>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x428>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c3: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6530000 0 0x428>; + interrupts = ; + clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c4: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6540000 0 0x428>; + interrupts = ; + clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c6: i2c@e6550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6550000 0 0x428>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c7: i2c@e6560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6560000 0 0x428>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c8: i2c@e6570000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe6570000 0 0x428>; + interrupts = ; + clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifb3: serial@e6cf0000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6cf0000 0 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; + clock-names = "fck"; + power-domains = <&pd_c4>; + status = "disabled"; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a73a4"; + reg = <0 0xee100000 0 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a73a4"; + reg = <0 0xee120000 0 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a73a4"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; + power-domains = <&pd_a3sp>; + reg-io-width = <4>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = ; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; + power-domains = <&pd_a3sp>; + reg-io-width = <4>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; + clock-names = "clk"; + power-domains = <&pd_c4>; + }; + + bsc: bus@fec10000 { + compatible = "renesas,bsc-r8a73a4", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + reg = <0 0xfec10000 0 0x400>; + clocks = <&zb_clk>; + power-domains = <&pd_c4>; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clocks */ + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + extal1_clk: extal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + extal2_clk: extal2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + fsiack_clk: fsiack { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + fsibck_clk: fsibck { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a73a4-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll2s", "pll2h", "z", "z2", + "i", "m3", "b", "m1", "m2", + "zx", "zs", "hp"; + }; + + /* Variable factor clocks (DIV6) */ + zb_clk: zb_clk@e6150010 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150010 0 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; + #clock-cells = <0>; + clock-output-names = "zb"; + }; + sdhi0_clk: sdhi0ck@e6150074 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150074 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + }; + sdhi1_clk: sdhi1ck@e6150078 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + }; + sdhi2_clk: sdhi2ck@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + }; + mmc0_clk: mmc0@e6150240 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + }; + mmc1_clk: mmc1@e6150244 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150244 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + }; + vclk1_clk: vclk1@e6150008 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150008 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + }; + vclk2_clk: vclk2@e615000c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615000c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + }; + vclk3_clk: vclk3@e615001c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615001c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + }; + vclk4_clk: vclk4@e6150014 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150014 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + }; + vclk5_clk: vclk5@e6150034 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150034 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + }; + fsia_clk: fsia@e6150018 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150018 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&fsiack_clk>, <0>; + #clock-cells = <0>; + }; + fsib_clk: fsib@e6150090 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150090 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&fsibck_clk>, <0>; + #clock-cells = <0>; + }; + mp_clk: mp@e6150080 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150080 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + }; + m4_clk: m4@e6150098 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150098 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; + #clock-cells = <0>; + }; + hsi_clk: hsi@e615026c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615026c 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, + <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; + #clock-cells = <0>; + }; + spuv_clk: spuv@e6150094 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150094 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + }; + + /* Fixed factor clocks */ + main_div2_clk: main_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + pll0_div2_clk: pll0_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + extal1_div2_clk: extal1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&extal1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 + R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 + R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 + R8A73A4_CLK_DMAC + >; + clock-output-names = + "scifa0", "scifa1", "scifb0", "scifb1", + "scifb2", "scifb3", "dmac"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, + <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, + <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks + R8A73A4_CLK_HP>, <&cpg_clocks + R8A73A4_CLK_HP>, <&extalr_clk>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 + R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 + R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 + R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 + R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 + R8A73A4_CLK_CMT1 + >; + clock-output-names = + "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", + "mmcif0", "iic6", "iic7", "iic0", "iic1", + "cmt1"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, + <&main_div2_clk>, + <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS + R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 + R8A73A4_CLK_IIC3 + >; + clock-output-names = + "irqc", "intc-sys", "iic5", "iic4", "iic3"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 + >; + clock-output-names = + "thermal", "iic8"; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; + reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_c4: c4@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sg: a3sg@16 { + reg = <16>; + #power-domain-cells = <0>; + }; + + pd_a3ex: a3ex@17 { + reg = <17>; + #power-domain-cells = <0>; + }; + + pd_a3sp: a3sp@18 { + reg = <18>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2us: a2us@19 { + reg = <19>; + #power-domain-cells = <0>; + }; + }; + + pd_a3sm: a3sm@20 { + reg = <20>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2sl: a2sl@21 { + reg = <21>; + #power-domain-cells = <0>; + }; + }; + + pd_a3km: a3km@22 { + reg = <22>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2kl: a2kl@23 { + reg = <23>; + #power-domain-cells = <0>; + }; + }; + }; + + pd_c4ma: c4ma@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_c4cl: c4cl@2 { + reg = <2>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@3 { + reg = <3>; + #power-domain-cells = <0>; + }; + + pd_a4bc: a4bc@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3bc: a3bc@5 { + reg = <5>; + #power-domain-cells = <0>; + }; + }; + + pd_a4l: a4l@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + + pd_a4lc: a4lc@7 { + reg = <7>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3mp: a3mp@9 { + reg = <9>; + #power-domain-cells = <0>; + }; + + pd_a3vc: a3vc@10 { + reg = <10>; + #power-domain-cells = <0>; + }; + }; + + pd_a4sf: a4sf@11 { + reg = <11>; + #power-domain-cells = <0>; + }; + + pd_a3r: a3r@12 { + reg = <12>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2rv: a2rv@13 { + reg = <13>; + #power-domain-cells = <0>; + }; + + pd_a2is: a2is@14 { + reg = <14>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts new file mode 100644 index 000000000000..fa09295052c6 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the armadillo 800 eva board + * + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +/dts-v1/; +#include "r8a7740.dtsi" +#include +#include +#include +#include + +/ { + model = "armadillo 800 eva"; + compatible = "renesas,armadillo800eva", "renesas,r8a7740"; + + aliases { + serial0 = &scifa1; + }; + + chosen { + bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sdhi0>; + + enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; + gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; + states = <3300000 0>, <1800000 1>; + + enable-active-high; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + keyboard { + compatible = "gpio-keys"; + + power-key { + gpios = <&pfc 99 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW3"; + wakeup-source; + }; + + back-key { + gpios = <&pfc 100 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4"; + }; + + menu-key { + gpios = <&pfc 97 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW5"; + }; + + home-key { + gpios = <&pfc 98 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW6"; + }; + }; + + leds { + compatible = "gpio-leds"; + led3 { + gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + led4 { + gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; + label = "LED4"; + }; + led5 { + gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; + label = "LED5"; + }; + led6 { + gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; + label = "LED6"; + }; + }; + + i2c2: i2c-2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; + brightness-levels = <0 1 2 4 8 16 32 64 128 255>; + default-brightness-level = <9>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + power-supply = <®_5p0v>; + enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + bitclock-inversion; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + bitclock-master; + frame-master; + system-clock-frequency = <12288000>; + }; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f1", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&pfc 18 GPIO_ACTIVE_LOW>; + }; +}; + +&extal1_clk { + clock-frequency = <24000000>; +}; +&extal2_clk { + clock-frequency = <48000000>; +}; +&fsibck_clk { + clock-frequency = <12288000>; +}; +&cpg_clocks { + renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */ +}; + +&cmt1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + wm8978: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; + + eeprom@50 { + compatible = "st,24c01", "atmel,24c01"; + reg = <0x50>; + pagesize = <16>; + }; + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&st1232_pins>; + pinctrl-names = "default"; + gpios = <&pfc 166 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c2 { + status = "okay"; + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + +&pfc { + pinctrl-0 = <&lcd0_pins>; + pinctrl-names = "default"; + + ether_pins: ether { + groups = "gether_mii", "gether_int"; + function = "gether"; + }; + + scifa1_pins: scifa1 { + groups = "scifa1_data"; + function = "scifa1"; + }; + + st1232_pins: touchscreen { + groups = "intc_irq10"; + function = "intc"; + }; + + backlight_pins: backlight { + groups = "tpu0_to2_1"; + function = "tpu0"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8_1", "mmc0_ctrl_1"; + function = "mmc0"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; + function = "sdhi0"; + }; + + fsia_pins: sounda { + groups = "fsia_sclk_in", "fsia_mclk_out", + "fsia_data_in_1", "fsia_data_out_0"; + function = "fsia"; + }; + + lcd0_pins: lcd0 { + groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; + function = "lcd0"; + }; + + lcd0-mux-hog { + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; +}; + +&tpu { + status = "okay"; +}; + +&mmcif0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&scifa1 { + pinctrl-0 = <&scifa1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tmu0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi new file mode 100644 index 000000000000..1b2cf5fa322b --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Mobile A1 (R8A77400) SoC + * + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a7740"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x0>; + clock-frequency = <800000000>; + power-domains = <&pd_a3sm>; + next-level-cache = <&L2>; + }; + }; + + gic: interrupt-controller@c2800000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xc2800000 0x1000>, + <0xc2000000 0x1000>; + }; + + L2: cache-controller@f0100000 { + compatible = "arm,pl310-cache"; + reg = <0xf0100000 0x1000>; + interrupts = ; + power-domains = <&pd_a3sm>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,shared-override; + cache-unified; + cache-level = <2>; + }; + + dbsc3: memory-controller@fe400000 { + compatible = "renesas,dbsc3-r8a7740"; + reg = <0xfe400000 0x400>; + power-domains = <&pd_a4s>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + ptm { + compatible = "arm,coresight-etm3x"; + power-domains = <&pd_d4>; + }; + + ceu0: ceu@fe910000 { + reg = <0xfe910000 0x3000>; + compatible = "renesas,r8a7740-ceu"; + interrupts = ; + clocks = <&mstp1_clks R8A7740_CLK_CEU20>; + power-domains = <&pd_a4r>; + status = "disabled"; + }; + + ceu1: ceu@fe914000 { + reg = <0xfe914000 0x3000>; + compatible = "renesas,r8a7740-ceu"; + interrupts = ; + clocks = <&mstp1_clks R8A7740_CLK_CEU21>; + power-domains = <&pd_a4r>; + status = "disabled"; + }; + + cmt1: timer@e6138000 { + compatible = "renesas,r8a7740-cmt1"; + reg = <0xe6138000 0x170>; + interrupts = ; + clocks = <&mstp3_clks R8A7740_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; + status = "disabled"; + }; + + /* irqpin0: IRQ0 - IRQ7 */ + irqpin0: interrupt-controller@e6900000 { + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900000 4>, + <0xe6900010 4>, + <0xe6900020 1>, + <0xe6900040 1>, + <0xe6900060 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; + + /* irqpin1: IRQ8 - IRQ15 */ + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; + + /* irqpin2: IRQ16 - IRQ23 */ + irqpin2: interrupt-controller@e6900008 { + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900008 4>, + <0xe6900018 4>, + <0xe6900028 1>, + <0xe6900048 1>, + <0xe6900068 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; + + /* irqpin3: IRQ24 - IRQ31 */ + irqpin3: interrupt-controller@e690000c { + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe690000c 4>, + <0xe690001c 4>, + <0xe690002c 1>, + <0xe690004c 1>, + <0xe690006c 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; + + ether: ethernet@e9a00000 { + compatible = "renesas,gether-r8a7740"; + reg = <0xe9a00000 0x800>, + <0xe9a01800 0x800>; + interrupts = ; + clocks = <&mstp3_clks R8A7740_CLK_GETHER>; + power-domains = <&pd_a4s>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@fff20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; + reg = <0xfff20000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp1_clks R8A7740_CLK_IIC0>; + power-domains = <&pd_a4r>; + status = "disabled"; + }; + + i2c1: i2c@e6c20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; + reg = <0xe6c20000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp3_clks R8A7740_CLK_IIC1>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c40000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c50000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c60000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c70000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa4: serial@e6c80000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6c80000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa5: serial@e6cb0000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6cb0000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa6: serial@e6cc0000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6cc0000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa7: serial@e6cd0000 { + compatible = "renesas,scifa-r8a7740", "renesas,scifa"; + reg = <0xe6cd0000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifb: serial@e6c30000 { + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a7740"; + reg = <0xe6050000 0x8000>, + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + }; + + tpu: pwm@e6600000 { + compatible = "renesas,tpu-r8a7740", "renesas,tpu"; + reg = <0xe6600000 0x148>; + clocks = <&mstp3_clks R8A7740_CLK_TPU0>; + power-domains = <&pd_a3sp>; + status = "disabled"; + #pwm-cells = <3>; + }; + + mmcif0: mmc@e6bd0000 { + compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupts = , + ; + clocks = <&mstp3_clks R8A7740_CLK_MMC>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + sdhi0: mmc@e6850000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6850000 0x100>; + interrupts = , + , + ; + clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: mmc@e6860000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6860000 0x100>; + interrupts = , + , + ; + clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi2: mmc@e6870000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6870000 0x100>; + interrupts = , + , + ; + clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sh_fsi2: sound@fe1f0000 { + #sound-dai-cells = <1>; + compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; + reg = <0xfe1f0000 0x400>; + interrupts = ; + clocks = <&mstp3_clks R8A7740_CLK_FSI>; + power-domains = <&pd_a4mp>; + status = "disabled"; + }; + + tmu0: timer@fff80000 { + compatible = "renesas,tmu-r8a7740", "renesas,tmu"; + reg = <0xfff80000 0x2c>; + interrupts = , + , + ; + clocks = <&mstp1_clks R8A7740_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&pd_a4r>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@fff90000 { + compatible = "renesas,tmu-r8a7740", "renesas,tmu"; + reg = <0xfff90000 0x2c>; + interrupts = , + , + ; + clocks = <&mstp1_clks R8A7740_CLK_TMU1>; + clock-names = "fck"; + power-domains = <&pd_a4r>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External root clock */ + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + extal1_clk: extal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + extal2_clk: extal2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + dv_clk: dv { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + fmsick_clk: fmsick { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + fmsock_clk: fmsock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + fsiack_clk: fsiack { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + fsibck_clk: fsibck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7740-cpg-clocks"; + reg = <0xe6150000 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; + #clock-cells = <1>; + clock-output-names = "system", "pllc0", "pllc1", + "pllc2", "r", + "usb24s", + "i", "zg", "b", "m1", "hp", + "hpp", "usbp", "s", "zb", "m3", + "cp"; + }; + + /* Variable factor clocks (DIV6) */ + vclk1_clk: vclk1@e6150008 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150008 4>; + clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, + <&extal1_div2_clk>, <&extalr_clk>, <0>, + <0>; + #clock-cells = <0>; + }; + vclk2_clk: vclk2@e615000c { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615000c 4>; + clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, + <&extal1_div2_clk>, <&extalr_clk>, <0>, + <0>; + #clock-cells = <0>; + }; + fmsi_clk: fmsi@e6150010 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150010 4>; + clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; + #clock-cells = <0>; + }; + fmso_clk: fmso@e6150014 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150014 4>; + clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; + #clock-cells = <0>; + }; + fsia_clk: fsia@e6150018 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150018 4>; + clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; + #clock-cells = <0>; + }; + sub_clk: sub@e6150080 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150080 4>; + clocks = <&pllc1_div2_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; + #clock-cells = <0>; + }; + spu_clk: spu@e6150084 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150084 4>; + clocks = <&pllc1_div2_clk>, + <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; + #clock-cells = <0>; + }; + vou_clk: vou@e6150088 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150088 4>; + clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, + <0>; + #clock-cells = <0>; + }; + stpro_clk: stpro@e615009c { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615009c 4>; + clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; + #clock-cells = <0>; + }; + + /* Fixed factor clocks */ + pllc1_div2_clk: pllc1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + extal1_div2_clk: extal1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&extal1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* Gate clocks */ + subck_clks: subck_clks@e6150080 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150080 4>; + clocks = <&sub_clk>, <&sub_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 + >; + clock-output-names = + "subck", "subck2"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150134 4>, <0xe6150038 4>; + clocks = <&cpg_clocks R8A7740_CLK_S>, + <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, + <&cpg_clocks R8A7740_CLK_B>, + <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, + <&cpg_clocks R8A7740_CLK_B>; + #clock-cells = <1>; + clock-indices = < + R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 + R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 + R8A7740_CLK_LCDC0 + >; + clock-output-names = + "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", + "tmu1", "lcdc0"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150138 4>, <0xe6150040 4>; + clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA + R8A7740_CLK_SCIFA7 + R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 + R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC + R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB + R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 + R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 + R8A7740_CLK_SCIFA4 + >; + clock-output-names = + "scifa6", "intca", + "scifa7", "dmac1", "dmac2", "dmac3", + "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", + "scifa2", "scifa3", "scifa4"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe615013c 4>, <0xe6150048 4>; + clocks = <&cpg_clocks R8A7740_CLK_R>, + <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 + R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 + R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 + >; + clock-output-names = + "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", + "mmc", "gether", "tpu0"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150140 4>, <0xe615004c 4>; + clocks = <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A7740_CLK_USBH R8A7740_CLK_SDHI2 + R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY + >; + clock-output-names = + "usbhost", "sdhi2", "usbfunc", "usphy"; + }; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; + reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a4lc: a4lc@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@2 { + reg = <2>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@3 { + reg = <3>; + #power-domain-cells = <0>; + }; + + pd_a4r: a4r@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3rv: a3rv@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + }; + + pd_a4s: a4s@10 { + reg = <10>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sp: a3sp@11 { + reg = <11>; + #power-domain-cells = <0>; + }; + + pd_a3sm: a3sm@12 { + reg = <12>; + #power-domain-cells = <0>; + }; + + pd_a3sg: a3sg@13 { + reg = <13>; + #power-domain-cells = <0>; + }; + }; + + pd_a4su: a4su@20 { + reg = <20>; + #power-domain-cells = <0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..33ac4bd1e63b --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board development + * platform with camera daughter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include + +#include "r8a7742-iwg21d-q7.dts" + +/ { + model = "iWave Systems RZ/G1H Qseven development platform with camera add-on"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial0 = &scif0; + serial1 = &scif1; + serial3 = &scifb1; + serial5 = &hscif0; + ethernet1 = ðer; + }; + + mclk_cam1: mclk-cam1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam2: mclk-cam2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam3: mclk-cam3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam4: mclk-cam4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&avb { + /* Pins shared with VIN0, keep status disabled */ + status = "disabled"; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1560", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + micrel,led-mode = <1>; + }; +}; + +&gpio0 { + /* Disable hogging GP0_18 to output LOW */ + /delete-node/ qspi-en-hog; + + /* Hog GP0_18 to output HIGH to enable VIN2 */ + vin2-en-hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VIN2_EN"; + }; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + /* status set to "okay" when needed by camera configuration below */ + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + /* status set to "okay" when needed by camera configuration below */ + clock-frequency = <400000>; +}; + +&pfc { + can0_pins: can0 { + groups = "can0_data_d"; + function = "can0"; + }; + + ether_pins: ether { + groups = "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1_c"; + function = "i2c1"; + }; + + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif1_pins: scif1 { + groups = "scif1_data"; + function = "scif1"; + }; + + scifb1_pins: scifb1 { + groups = "scifb1_data"; + function = "scifb1"; + }; + + vin0_8bit_pins: vin0 { + groups = "vin0_data8", "vin0_clk", "vin0_sync"; + function = "vin0"; + }; + + vin1_8bit_pins: vin1 { + groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; + function = "vin1"; + }; + + vin2_pins: vin2 { + groups = "vin2_g8", "vin2_clk"; + function = "vin2"; + }; + + vin3_pins: vin3 { + groups = "vin3_data8", "vin3_clk", "vin3_sync"; + function = "vin3"; + }; +}; + +&qspi { + /* Pins shared with VIN2, keep status disabled */ + status = "disabled"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scifb1 { + pinctrl-0 = <&scifb1_pins>; + pinctrl-names = "default"; + status = "okay"; + + rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; +}; + +/* + * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints + * + * (un)comment the #include statements to change configuration + */ + +/* 8bit CMOS Camera 1 (J13) */ +#define CAM_PARENT_I2C i2c0 +#define MCLK_CAM mclk_cam1 +#define CAM_EP cam0ep +#define VIN_EP vin0ep +#undef CAM_ENABLED +#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" + +#ifdef CAM_ENABLED +&vin0 { + /* + * Set SW2 switch on the SOM to 'ON' + * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode + */ + status = "okay"; + pinctrl-0 = <&vin0_8bit_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&cam0ep>; + bus-width = <8>; + bus-type = ; + }; + }; +}; +#endif /* CAM_ENABLED */ + +#undef CAM_PARENT_I2C +#undef MCLK_CAM +#undef CAM_EP +#undef VIN_EP + +/* 8bit CMOS Camera 2 (J14) */ +#define CAM_PARENT_I2C i2c1 +#define MCLK_CAM mclk_cam2 +#define CAM_EP cam1ep +#define VIN_EP vin1ep +#undef CAM_ENABLED +#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" + +#ifdef CAM_ENABLED +&vin1 { + /* Set SW1 switch on the SOM to 'ON' */ + status = "okay"; + pinctrl-0 = <&vin1_8bit_pins>; + pinctrl-names = "default"; + + port { + vin1ep: endpoint { + remote-endpoint = <&cam1ep>; + bus-width = <8>; + bus-type = ; + }; + }; +}; + +#endif /* CAM_ENABLED */ + +#undef CAM_PARENT_I2C +#undef MCLK_CAM +#undef CAM_EP +#undef VIN_EP + +/* 8bit CMOS Camera 3 (J12) */ +#define CAM_PARENT_I2C i2c2 +#define MCLK_CAM mclk_cam3 +#define CAM_EP cam2ep +#define VIN_EP vin2ep +#undef CAM_ENABLED +#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" + +#ifdef CAM_ENABLED +&vin2 { + status = "okay"; + pinctrl-0 = <&vin2_pins>; + pinctrl-names = "default"; + + port { + vin2ep: endpoint { + remote-endpoint = <&cam2ep>; + bus-width = <8>; + data-shift = <8>; + bus-type = ; + }; + }; +}; +#endif /* CAM_ENABLED */ + +#undef CAM_PARENT_I2C +#undef MCLK_CAM +#undef CAM_EP +#undef VIN_EP + +/* 8bit CMOS Camera 4 (J11) */ +#define CAM_PARENT_I2C i2c3 +#define MCLK_CAM mclk_cam4 +#define CAM_EP cam3ep +#define VIN_EP vin3ep +#undef CAM_ENABLED +#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" +//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" + +#ifdef CAM_ENABLED +&vin3 { + status = "okay"; + pinctrl-0 = <&vin3_pins>; + pinctrl-names = "default"; + + port { + vin3ep: endpoint { + remote-endpoint = <&cam3ep>; + bus-width = <8>; + bus-type = ; + }; + }; +}; +#endif /* CAM_ENABLED */ + +#undef CAM_PARENT_I2C +#undef MCLK_CAM +#undef CAM_EP +#undef VIN_EP diff --git a/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi new file mode 100644 index 000000000000..c73160df619d --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file ties a VIN interface with a single ov5640 sensor on + * the iWave-RZ/G1H Qseven board development platform connected with the + * camera daughter board. + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include + +#define CAM_ENABLED 1 + +&CAM_PARENT_I2C { + status = "okay"; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&MCLK_CAM>; + clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p8v>; + status = "okay"; + + port { + CAM_EP: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = ; + pclk-sample = <1>; + remote-endpoint = <&VIN_EP>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi new file mode 100644 index 000000000000..a7f5cfec64b8 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file ties a VIN interface with a single ov7725 sensor on + * the iWave-RZ/G1H Qseven board development platform connected with the + * camera daughter board. + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include + +#define CAM_ENABLED 1 + +&CAM_PARENT_I2C { + status = "okay"; + + ov7725@21 { + compatible = "ovti,ov7725"; + reg = <0x21>; + clocks = <&MCLK_CAM>; + status = "okay"; + + port { + CAM_EP: endpoint { + bus-width = <8>; + bus-type = ; + remote-endpoint = <&VIN_EP>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts new file mode 100644 index 000000000000..64102b664055 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7742-iwg21m.dtsi" +#include + +/ { + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial2 = &scifa2; + serial4 = &scifb2; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial2:115200n8"; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + lcd_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + default-brightness-level = <7>; + enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + + sdhi2_led { + label = "sdio-led"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + + lvds-receiver { + compatible = "ti,ds90cf384a", "lvds-decoder"; + power-supply = <&vcc_3v3_tft1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_receiver_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + port@1 { + reg = <1>; + lvds_receiver_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0dh6"; + backlight = <&lcd_backlight>; + power-supply = <&vcc_3v3_tft1>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_receiver_out>; + }; + }; + }; + + reg_1p5v: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + + vcc_3v3_tft1: regulator-panel { + compatible = "regulator-fixed"; + + regulator-name = "vcc-3v3-tft1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <500>; + gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; + }; + + vcc_sdhi2: regulator-vcc-sdhi2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p5v>; + }; + + touch: touchpanel@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + /* GP1_29 is also shared with audio codec reset pin */ + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc_3v3_tft1>; + }; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&cmt0 { + status = "okay"; +}; + +&du { + status = "okay"; +}; + +&gpio0 { + touch-interrupt-hog { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + input; + }; +}; + +&gpio1 { + can-trx-en-hog { + gpio-hog; + gpios = <28 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can-trx-en-gpio"; + }; +}; + +&hsusb { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lvds0 { + status = "okay"; + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&lvds_receiver_in>; + }; + }; + }; +}; + +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + flash1: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "user"; + reg = <0x00000000 0x00200000>; + }; + }; + }; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + /* Disable hsusb to enable USB2.0 host mode support on J2 */ + /* status = "okay"; */ +}; + +&pci1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pci2 { + /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */ + /* status = "okay"; */ +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + /* SW2[6] determines which connector is activated + * ON = PCIe X4 (connector-J7) + * OFF = mini-PCIe (connector-J26) + */ + status = "okay"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + backlight_pins: backlight { + groups = "tpu0_to2"; + function = "tpu0"; + }; + + can1_pins: can1 { + groups = "can1_data_b"; + function = "can1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_b"; + function = "i2c2"; + }; + + msiof0_pins: msiof0 { + groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx"; + function = "msiof0"; + }; + + scifa2_pins: scifa2 { + groups = "scifa2_data_c"; + function = "scifa2"; + }; + + scifb2_pins: scifb2 { + groups = "scifb2_data", "scifb2_ctrl"; + function = "scifb2"; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1_pwen"; + function = "usb1"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi4>, <&src4>, <&dvc1>; + capture = <&ssi3>, <&src3>, <&dvc0>; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scifa2 { + pinctrl-0 = <&scifa2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scifb2 { + pinctrl-0 = <&scifb2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi4 { + shared-pin; +}; + +&tpu { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi new file mode 100644 index 000000000000..b281a4d164b0 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1H Qseven SOM + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a7742.dtsi" +#include + +/ { + compatible = "iwave,g21m", "renesas,r8a7742"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&gpio0 { + /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ + qspi-en-hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "QSPI_EN"; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pfc { + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x000c0000>; + read-only; + }; + partition@c0000 { + label = "env"; + reg = <0x000c0000 0x00002000>; + }; + partition@c2000 { + label = "user"; + reg = <0x000c2000 0x0013e000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi new file mode 100644 index 000000000000..16d146db824a --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7742.dtsi @@ -0,0 +1,1891 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7742 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7742"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU2>; + next-level-cache = <&L2_CA7>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU3>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7742-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7742"; + reg = <0 0xe6060000 0 0x250>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7742", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7742-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6151000 { + compatible = "renesas,r8a7742-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7742-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7742-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7742-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7742", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7742", + "renesas,rcar-gen2-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 300>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>, + <&dmac1 0x69>, <&dmac1 0x6a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7742", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7742", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7742-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7742-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7742", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7742", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e56000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 205>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 215>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>, + <&dmac1 0x45>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 215>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7742", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7742_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7742", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x20800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x21000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee120000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7742", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7742", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7742", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7742", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 130>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7742"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7742-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds1: lvds@feb94000 { + compatible = "renesas,r8a7742-lvds"; + reg = <0 0xfeb94000 0 0x14>; + clocks = <&cpg CPG_MOD 725>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 725>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7742-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7742-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..0d006aea99da --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" +#include "iwg20d-q7-dbcm-ca.dtsi" + +/ { + model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +}; + +&pciec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts new file mode 100644 index 000000000000..498e223a5f93 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1M Qseven board + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" + +/ { + model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +}; + +&pciec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi new file mode 100644 index 000000000000..b3fee1d61c87 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZG1M-20M Qseven SOM + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +#include "r8a7743.dtsi" +#include + +/ { + compatible = "iwave,g20m", "renesas,r8a7743"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x20000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8_b", "mmc_ctrl"; + function = "mmc"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts new file mode 100644 index 000000000000..ff274bfcb664 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SK-RZG1M board + * + * Copyright (C) 2016-2017 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a7743.dtsi" +#include + +/ { + model = "SK-RZG1M"; + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq0"; + function = "intc"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi new file mode 100644 index 000000000000..2245d19a23bb --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7743.dtsi @@ -0,0 +1,1799 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016-2017 Cogent Embedded Inc. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7743-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7743", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7743"; + reg = <0 0xe6060000 0 0x250>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7743", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7743-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7743", + "renesas,rcar-gen2-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: iommu@e62a0000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7743", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7743", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7743", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7743", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7743", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7743_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7743", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7743_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7743", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7743", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7743", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7743", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7743_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7743", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7743", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7743", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7743", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7743"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7743-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7743-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7743-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..3e58c2e92e03 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave Systems RZ/G1N Qseven board development + * platform with camera daughter board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7744-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" +#include "iwg20d-q7-dbcm-ca.dtsi" + +/ { + model = "iWave Systems RZ/G1N Qseven development platform with camera add-on"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts new file mode 100644 index 000000000000..1fdac528f274 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1N Qseven board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7744-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" + +/ { + model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi new file mode 100644 index 000000000000..82ee3c1140ef --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1N Qseven SOM + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include "r8a7744.dtsi" +#include + +/ { + compatible = "iwave,g20m", "renesas,r8a7744"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8_b", "mmc_ctrl"; + function = "mmc"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi new file mode 100644 index 000000000000..aa13841f9781 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7744.dtsi @@ -0,0 +1,1785 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7744 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7744"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7744_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7744_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7744_PD_CA15_SCU>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7744-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7744"; + reg = <0 0xe6060000 0 0x250>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7744", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7744-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7744-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7744-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7744-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7744", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7744", + "renesas,rcar-gen2-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: iommu@e62a0000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7744", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7744", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7744", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7744", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7744", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7744-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7744-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7744", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7744", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7744", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7744_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7744", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7744_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7744", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7744", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7744", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7744", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7744_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7744", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7744", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7744", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7744", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7744", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7744", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7744", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7744", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7744"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7744-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7744-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7744-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts new file mode 100644 index 000000000000..b1f679da36b2 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter + * board + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +#include "r8a7745-iwg22d-sodimm.dts" + +/ { + model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + serial0 = &scif1; + serial4 = &scif5; + serial6 = &hscif2; + }; + + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&hscif2 { + pinctrl-0 = <&hscif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lcd_panel { + status = "disabled"; + + /delete-node/ port; +}; + +&pfc { + can1_pins: can1 { + groups = "can1_data_b"; + function = "can1"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + hscif2_pins: hscif2 { + groups = "hscif2_data"; + function = "hscif2"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1_d"; + function = "i2c1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data"; + function = "scif1"; + }; + + scif5_pins: scif5 { + groups = "scif5_data_d"; + function = "scif5"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif5 { + pinctrl-0 = <&scif5_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts new file mode 100644 index 000000000000..c105932f642e --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7745-iwg22m.dtsi" +#include + +/ { + model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + ethernet0 = &avb; + serial3 = &scif4; + serial5 = &hscif1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial3:115200n8"; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + lcd_panel: lcd { + compatible = "edt,etm043080dh6gp"; + power-supply = <&vccq_panel>; + backlight = <&backlight_lcd>; + + port { + lcd_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + }; + + vccq_panel: regulator-vccq-panel { + compatible = "regulator-fixed"; + regulator-name = "Panel VccQ"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + /* + * On some older versions of the platform (before R4.0) the phy address + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. + */ + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&lcd_in>; + }; + }; + }; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&i2c5 { + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; + + stmpe811@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupt-parent = <&gpio4>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* ADC conversion time: 80 clocks */ + st,sample-time = <4>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + backlight_pins: backlight { + groups = "tpu_to3_c"; + function = "tpu"; + }; + + can0_pins: can0 { + groups = "can0_data"; + function = "can0"; + }; + + du0_pins: du0 { + groups = "du0_rgb666", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; + + i2c5_pins: i2c5 { + groups = "i2c5_b"; + function = "i2c5"; + }; + + scif4_pins: scif4 { + groups = "scif4_data_b"; + function = "scif4"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sound_pins: sound { + groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi3>, <&src3>, <&dvc0>; + capture = <&ssi4>, <&src4>, <&dvc1>; + }; + }; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ssi4 { + shared-pin; +}; + +&tpu { + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi new file mode 100644 index 000000000000..41f111b99a75 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +#include "r8a7745.dtsi" +#include + +/ { + compatible = "iwave,g22m", "renesas,r8a7745"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + i2c3_pins: i2c3 { + groups = "i2c3_b"; + function = "i2c3"; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts new file mode 100644 index 000000000000..0a75e8c79acc --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SK-RZG1E board + * + * Copyright (C) 2016-2017 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a7745.dtsi" +#include + +/ { + model = "SK-RZG1E"; + compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi new file mode 100644 index 000000000000..44688b8431c3 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7745.dtsi @@ -0,0 +1,1589 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7745 SoC + * + * Copyright (C) 2016-2017 Cogent Embedded Inc. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7745"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &iic0; + i2c7 = &iic1; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + vin0 = &vin0; + vin1 = &vin1; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; + power-domains = <&sysc R8A7745_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; + power-domains = <&sysc R8A7745_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + }; + + L2_CA7: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7745_PD_CA7_SCU>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7745"; + reg = <0 0xe6060000 0 0x11c>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7745", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7745-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6151000 { + compatible = "renesas,r8a7745-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7745-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7745-wdt", + "renesas,rcar-gen2-wdt"; + interrupts = ; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7745-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: iommu@e62a0000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7745", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7745", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7745", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7745", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7745-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7745-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7745", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7745", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7745", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7745", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7745", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&cpg CPG_CORE R8A7745_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", + "src.2", "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, + <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, + <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src-0 { + status = "disabled"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7745", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7745", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7745"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7745-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7745-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts new file mode 100644 index 000000000000..644802285249 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1C single board computer + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include +#include "r8a77470.dtsi" +/ { + model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; + compatible = "iwave,g23s", "renesas,r8a77470"; + + aliases { + ethernet0 = &avb; + serial1 = &scif1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial1:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_1p8v: reg-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: reg-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&gpio2 { + interrupt-fixup-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "hdmi-hpd-int"; + input; + }; +}; + +&hsusb0 { + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <100000>; + + hdmi@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii_tx_rx"; + function = "avb"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4_e"; + function = "i2c4"; + }; + + i2c3_pins: i2c3 { + groups = "i2c3_c"; + function = "i2c3"; + }; + + mmc_pins_uhs: mmc_uhs { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data2"; + function = "qspi0"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_b"; + function = "scif1"; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&qspi0 { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "issi,is25lp016d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&mmc_pins_uhs>; + pinctrl-names = "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi2>; + bus-width = <4>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + status = "okay"; +}; + +&usb2_phy0 { + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usbphy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usbphy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi new file mode 100644 index 000000000000..a5cf663a0118 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a77470.dtsi @@ -0,0 +1,1028 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a77470 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +/ { + compatible = "renesas,r8a77470"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; + power-domains = <&sysc R8A77470_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; + power-domains = <&sysc R8A77470_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + }; + + L2_CA7: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A77470_PD_CA7_SCU>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77470-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 30>; + gpio-reserved-ranges = <17 10>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a77470"; + reg = <0 0xe6060000 0 0x118>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77470-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6151000 { + compatible = "renesas,r8a77470-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77470-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77470-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a77470", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x20000>; + }; + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + hsusb0: hsusb@e6590000 { + compatible = "renesas,usbhs-r8a77470", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac00 0>, <&usb_dmac00 1>, + <&usb_dmac10 0>, <&usb_dmac10 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + usbphy0: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a77470", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + }; + + hsusb1: hsusb@e6598000 { + compatible = "renesas,usbhs-r8a77470", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6598000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>; + dmas = <&usb_dmac01 0>, <&usb_dmac01 1>, + <&usb_dmac11 0>, <&usb_dmac11 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <4>; + /* We need to turn on usbphy0 to make usbphy1 to work */ + phys = <&usb1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 706>; + status = "disabled"; + }; + + usbphy1: usb-phy-controller@e6598100 { + compatible = "renesas,usb-phy-r8a77470", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6598100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 706>; + clock-names = "usbhs"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 706>; + status = "disabled"; + + usb1: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + }; + + usb_dmac00: dma-controller@e65a0000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac10: dma-controller@e65b0000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac01: dma-controller@e65a8000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a8000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 326>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 326>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac11: dma-controller@e65b8000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b8000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 327>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 327>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77470", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi0: spi@e6b10000 { + compatible = "renesas,qspi-r8a77470", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 918>; + status = "disabled"; + }; + + qspi1: spi@ee200000 { + compatible = "renesas,qspi-r8a77470", "renesas,qspi"; + reg = <0 0xee200000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a77470", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a77470", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a77470", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77470", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77470", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb0 0>, <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb0 0>, <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77470"; + reg = <0 0xee080200 0 0x700>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + ohci1: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; + phy-names = "usb"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + ehci1: usb@ee0c0100 { + compatible = "generic-ehci"; + reg = <0 0xee0c0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a77470"; + reg = <0 0xee0c0200 0 0x700>; + clocks = <&cpg CPG_MOD 705>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 705>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a77470", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <156000000>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee300000 { + compatible = "renesas,sdhi-mmc-r8a77470"; + reg = <0 0xee300000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <156000000>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a77470", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <78000000>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77470"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a77470-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77470-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7778-bockw.dts b/arch/arm/boot/dts/renesas/r8a7778-bockw.dts new file mode 100644 index 000000000000..9b65d246e583 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7778-bockw.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + */ + +/dts-v1/; +#include "r8a7778.dtsi" +#include +#include + +/ { + model = "bockw"; + compatible = "renesas,bockw", "renesas,r8a7778"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x10000000>; + }; + + fixedregulator3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; + }; +}; + +&bsc { + ethernet@18300000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0x18300000 0x1000>; + + phy-mode = "mii"; + interrupt-parent = <&irqpin>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; +}; + +&extal_clk { + clock-frequency = <33333333>; +}; + +&i2c0 { + status = "okay"; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + camera@41 { + compatible = "oki,ml86v7667"; + reg = <0x41>; + }; + + camera@43 { + compatible = "oki,ml86v7667"; + reg = <0x43>; + }; + + rx8581: rtc@51 { + compatible = "epson,rx8581"; + reg = <0x51>; + }; +}; + +&mmcif { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + broken-cd; + status = "okay"; +}; + +&irqpin { + status = "okay"; +}; + +&tmu0 { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + groups = "scif0_data_a", "scif0_ctrl"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + sdhi0_pup_pins: sd0_pup { + groups = "sdhi0_cd", "sdhi0_wp"; + function = "sdhi0"; + bias-pull-up; + }; + + hspi0_pins: hspi0 { + groups = "hspi0_a"; + function = "hspi0"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + vin0_pins: vin0 { + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; + }; + + vin1_pins: vin1 { + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; + }; +}; + +&rcar_sound { + /* Single DAI */ + #sound-dai-cells = <0>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>, <&sdhi0_pup_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl008k", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "data(spi)"; + reg = <0x00000000 0x00100000>; + }; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi new file mode 100644 index 000000000000..8d4530ed2fc6 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7778.dtsi @@ -0,0 +1,671 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car M1A (R8A77781) SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a7778"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <800000000>; + clocks = <&z_clk>; + }; + }; + + aliases { + spi0 = &hspi0; + spi1 = &hspi1; + spi2 = &hspi2; + }; + + bsc: bus@1c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1c000000>; + }; + + ether: ethernet@fde00000 { + compatible = "renesas,ether-r8a7778", + "renesas,rcar-gen1-ether"; + reg = <0xfde00000 0x400>; + interrupts = ; + clocks = <&mstp1_clks R8A7778_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@fe438000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfe438000 0x1000>, + <0xfe430000 0x100>; + }; + + /* irqpin: IRQ0 - IRQ3 */ + irqpin: interrupt-controller@fe78001c { + compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + status = "disabled"; /* default off */ + reg = <0xfe78001c 4>, + <0xfe780010 4>, + <0xfe780024 4>, + <0xfe780044 4>, + <0xfe780064 4>, + <0xfe780000 4>; + interrupts = , + , + , + ; + sense-bitfield-width = <2>; + }; + + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; + reg = <0xffc40000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@ffc41000 { + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; + reg = <0xffc41000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@ffc42000 { + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; + reg = <0xffc42000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@ffc43000 { + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; + reg = <0xffc43000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@ffc44000 { + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; + reg = <0xffc44000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 27>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pfc: pinctrl@fffc0000 { + compatible = "renesas,pfc-r8a7778"; + reg = <0xfffc0000 0x118>; + }; + + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc70000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_I2C0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc71000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_I2C1>; + power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; + status = "disabled"; + }; + + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc72000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_I2C2>; + power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; + status = "disabled"; + }; + + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; + reg = <0xffc73000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_I2C3>; + power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; + status = "disabled"; + }; + + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = , + , + ; + clocks = <&mstp0_clks R8A7778_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@ffd81000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd81000 0x30>; + interrupts = , + , + ; + clocks = <&mstp0_clks R8A7778_CLK_TMU1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu2: timer@ffd82000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd82000 0x30>; + interrupts = , + , + ; + clocks = <&mstp0_clks R8A7778_CLK_TMU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + rcar_sound: sound@ffd90000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; + reg = <0xffd90000 0x1000>, /* SRU */ + <0xffd91000 0x240>, /* SSI */ + <0xfffe0000 0x24>; /* ADG */ + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, + <&mstp3_clks R8A7778_CLK_SSI7>, + <&mstp3_clks R8A7778_CLK_SSI6>, + <&mstp3_clks R8A7778_CLK_SSI5>, + <&mstp3_clks R8A7778_CLK_SSI4>, + <&mstp0_clks R8A7778_CLK_SSI3>, + <&mstp0_clks R8A7778_CLK_SSI2>, + <&mstp0_clks R8A7778_CLK_SSI1>, + <&mstp0_clks R8A7778_CLK_SSI0>, + <&mstp5_clks R8A7778_CLK_SRU_SRC8>, + <&mstp5_clks R8A7778_CLK_SRU_SRC7>, + <&mstp5_clks R8A7778_CLK_SRU_SRC6>, + <&mstp5_clks R8A7778_CLK_SRU_SRC5>, + <&mstp5_clks R8A7778_CLK_SRU_SRC4>, + <&mstp5_clks R8A7778_CLK_SRU_SRC3>, + <&mstp5_clks R8A7778_CLK_SRU_SRC2>, + <&mstp5_clks R8A7778_CLK_SRU_SRC1>, + <&mstp5_clks R8A7778_CLK_SRU_SRC0>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg_clocks R8A7778_CLK_S1>; + clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", + "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.8", "src.7", "src.6", "src.5", "src.4", + "src.3", "src.2", "src.1", "src.0", + "clk_a", "clk_b", "clk_c", "clk_i"; + + status = "disabled"; + + rcar_sound,src { + src3: src-3 { }; + src4: src-4 { }; + src5: src-5 { }; + src6: src-6 { }; + src7: src-7 { }; + src8: src-8 { }; + src9: src-9 { }; + }; + + rcar_sound,ssi { + ssi3: ssi-3 { interrupts = ; }; + ssi4: ssi-4 { interrupts = ; }; + ssi5: ssi-5 { interrupts = ; }; + ssi6: ssi-6 { interrupts = ; }; + ssi7: ssi-7 { interrupts = ; }; + ssi8: ssi-8 { interrupts = ; }; + ssi9: ssi-9 { interrupts = ; }; + }; + }; + + scif0: serial@ffe40000 { + compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe40000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@ffe41000 { + compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe41000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif2: serial@ffe42000 { + compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe42000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@ffe43000 { + compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe43000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@ffe44000 { + compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe44000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@ffe45000 { + compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe45000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif0: serial@ffe48000 { + compatible = "renesas,hscif-r8a7778", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe48000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, + <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif1: serial@ffe49000 { + compatible = "renesas,hscif-r8a7778", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe49000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, + <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + mmcif: mmc@ffe4e000 { + compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; + reg = <0xffe4e000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7778_CLK_MMC>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi0: mmc@ffe4c000 { + compatible = "renesas,sdhi-r8a7778", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4c000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi1: mmc@ffe4d000 { + compatible = "renesas,sdhi-r8a7778", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4d000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi2: mmc@ffe4f000 { + compatible = "renesas,sdhi-r8a7778", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4f000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hspi0: spi@fffc7000 { + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; + reg = <0xfffc7000 0x18>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hspi1: spi@fffc8000 { + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; + reg = <0xfffc8000 0x18>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hspi2: spi@fffc6000 { + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; + reg = <0xfffc6000 0x18>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External input clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; + reg = <0xffc80000 0x80>; + #clock-cells = <1>; + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; + #power-domain-cells = <0>; + }; + + /* Audio clocks; frequencies are set by boards if applicable. */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* Fixed ratio clocks */ + g_clk: g { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; + i_clk: i { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + s3_clk: s3 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + s4_clk: s4 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + z_clk: z { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLB>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@ffc80030 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80030 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 + R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 + R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 + R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 + R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 + R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 + R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 + R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 + R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 + R8A7778_CLK_SSI3 R8A7778_CLK_SRU + R8A7778_CLK_HSPI + >; + clock-output-names = + "i2c0", "i2c1", "i2c2", "i2c3", "scif0", + "scif1", "scif2", "scif3", "scif4", "scif5", + "hscif0", "hscif1", + "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", + "ssi2", "ssi3", "sru", "hspi"; + }; + mstp1_clks: mstp1_clks@ffc80034 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80034 4>, <0xffc80044 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_ETHER R8A7778_CLK_VIN0 + R8A7778_CLK_VIN1 R8A7778_CLK_USB + >; + clock-output-names = + "ether", "vin0", "vin1", "usb"; + }; + mstp3_clks: mstp3_clks@ffc8003c { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc8003c 4>; + clocks = <&s4_clk>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_MMC R8A7778_CLK_SDHI0 + R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 + R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 + R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 + R8A7778_CLK_SSI8 + >; + clock-output-names = + "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", + "ssi5", "ssi6", "ssi7", "ssi8"; + }; + mstp5_clks: mstp5_clks@ffc80054 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80054 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 + R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 + R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 + R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 + R8A7778_CLK_SRU_SRC8 + >; + clock-output-names = + "sru-src0", "sru-src1", "sru-src2", + "sru-src3", "sru-src4", "sru-src5", + "sru-src6", "sru-src7", "sru-src8"; + }; + }; + + rst: reset-controller@ffcc0000 { + compatible = "renesas,r8a7778-reset-wdt"; + reg = <0xffcc0000 0x40>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7779-marzen.dts b/arch/arm/boot/dts/renesas/r8a7779-marzen.dts new file mode 100644 index 000000000000..fd40890bd77b --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7779-marzen.dts @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car H1 (R8A77790) Marzen board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + */ + +/dts-v1/; +#include "r8a7779.dtsi" +#include +#include +#include + +/ { + model = "marzen"; + compatible = "renesas,marzen", "renesas,r8a7779"; + + aliases { + serial0 = &scif2; + serial1 = &scif4; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + fixedregulator3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0x18000000 0x100>; + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + + phy-mode = "mii"; + interrupt-parent = <&irqpin0>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; + + keyboard-irq { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_irq_pins>; + pinctrl-names = "default"; + + interrupt-parent = <&gpio0>; + + key-1 { + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW1-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW1-2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + keyboard-gpio { + compatible = "gpio-keys-polled"; + poll-interval = <50>; + + pinctrl-0 = <&keyboard_gpio_pins>; + pinctrl-names = "default"; + + key-3 { + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW1-3"; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW1-4"; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + led2 { + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + led3 { + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + }; + led4 { + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + vga_enc_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + port@1 { + reg = <1>; + vga_enc_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&vga_enc_out>; + }; + }; + }; + + lvds-encoder { + compatible = "thine,thc63lvdm83d"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_enc_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + lvds_connector: endpoint { + }; + }; + }; + }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <65000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; + clock-names = "du.0", "dclkin.0"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&vga_enc_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&lvds_enc_in>; + }; + }; + }; +}; + +&gpio0 { + keyboard-irq-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>; + input; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <100000>; +}; + +&irqpin0 { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <31250000>; +}; + +&tmu0 { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + du_pins: du { + du0 { + groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; + function = "du0"; + }; + du1 { + groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; + function = "du1"; + }; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; + + ethernet_pins: ethernet { + intc { + groups = "intc_irq1_b"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; + + scif2_pins: scif2 { + groups = "scif2_data_c"; + function = "scif2"; + }; + + scif4_pins: scif4 { + groups = "scif4_data"; + function = "scif4"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + function = "sdhi0"; + }; + + hspi0_pins: hspi0 { + groups = "hspi0"; + function = "hspi0"; + }; + + keyboard_irq_pins: keyboard-irq { + pins = "GP_0_17", "GP_0_18"; + bias-pull-up; + }; + keyboard_gpio_pins: keyboard-gpio { + pins = "GP_0_19", "GP_0_20"; + bias-pull-up; + }; +}; + +&sata { + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + status = "okay"; +}; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi new file mode 100644 index 000000000000..97b767d81d92 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7779.dtsi @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car H1 (R8A77790) SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7779"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; + power-domains = <&sysc R8A7779_PD_ARM1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; + power-domains = <&sysc R8A7779_PD_ARM2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; + power-domains = <&sysc R8A7779_PD_ARM3>; + }; + }; + + aliases { + spi0 = &hspi0; + spi1 = &hspi1; + spi2 = &hspi2; + }; + + gic: interrupt-controller@f0001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xf0001000 0x1000>, + <0xf0000100 0x100>; + }; + + timer@f0000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf0000200 0x100>; + interrupts = ; + clocks = <&cpg_clocks R8A7779_CLK_ZS>; + }; + + timer@f0000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf0000600 0x20>; + interrupts = ; + clocks = <&cpg_clocks R8A7779_CLK_ZS>; + }; + + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc40000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@ffc41000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc41000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@ffc42000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc42000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@ffc43000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc43000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@ffc44000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc44000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio5: gpio@ffc45000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc45000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio6: gpio@ffc46000 { + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; + reg = <0xffc46000 0x2c>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 9>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + irqpin0: interrupt-controller@fe78001c { + compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + status = "disabled"; + interrupt-controller; + reg = <0xfe78001c 4>, + <0xfe780010 4>, + <0xfe780024 4>, + <0xfe780044 4>, + <0xfe780064 4>, + <0xfe780000 4>; + interrupts = , + , + , + ; + sense-bitfield-width = <2>; + }; + + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc70000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_I2C0>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc71000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_I2C1>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; + status = "disabled"; + }; + + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc72000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_I2C2>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; + status = "disabled"; + }; + + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; + reg = <0xffc73000 0x1000>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_I2C3>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; + status = "disabled"; + }; + + scif0: serial@ffe40000 { + compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe40000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@ffe41000 { + compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe41000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@ffe42000 { + compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe42000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@ffe43000 { + compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe43000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@ffe44000 { + compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe44000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@ffe45000 { + compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", + "renesas,scif"; + reg = <0xffe45000 0x100>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@ffe48000 { + compatible = "renesas,hscif-r8a7779", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe48000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, + <&cpg_clocks R8A7779_CLK_S>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@ffe49000 { + compatible = "renesas,hscif-r8a7779", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe49000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, + <&cpg_clocks R8A7779_CLK_S>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm0: pwm@ffe50000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe50000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@ffe51000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe51000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@ffe52000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe52000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@ffe53000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe53000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@ffe54000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe54000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@ffe55000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe55000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@ffe56000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe56000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pfc: pinctrl@fffc0000 { + compatible = "renesas,pfc-r8a7779"; + reg = <0xfffc0000 0x23c>; + }; + + thermal@ffc48000 { + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; + reg = <0xffc48000 0x38>; + }; + + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = , + , + ; + clocks = <&mstp0_clks R8A7779_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@ffd81000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd81000 0x30>; + interrupts = , + , + ; + clocks = <&mstp0_clks R8A7779_CLK_TMU1>; + clock-names = "fck"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu2: timer@ffd82000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd82000 0x30>; + interrupts = , + , + ; + clocks = <&mstp0_clks R8A7779_CLK_TMU2>; + clock-names = "fck"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + sata: sata@fc600000 { + compatible = "renesas,sata-r8a7779"; + reg = <0xfc600000 0x200000>; + interrupts = ; + clocks = <&mstp1_clks R8A7779_CLK_SATA>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi0: mmc@ffe4c000 { + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4c000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi1: mmc@ffe4d000 { + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4d000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi2: mmc@ffe4e000 { + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4e000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi3: mmc@ffe4f000 { + compatible = "renesas,sdhi-r8a7779", + "renesas,rcar-gen1-sdhi"; + reg = <0xffe4f000 0x100>; + interrupts = ; + clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hspi0: spi@fffc7000 { + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; + reg = <0xfffc7000 0x18>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hspi1: spi@fffc8000 { + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; + reg = <0xfffc8000 0x18>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hspi2: spi@fffc6000 { + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; + reg = <0xfffc6000 0x18>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + }; + + du: display@fff80000 { + compatible = "renesas,du-r8a7779"; + reg = <0xfff80000 0x40000>; + interrupts = ; + clocks = <&mstp1_clks R8A7779_CLK_DU>; + clock-names = "du.0"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* Special CPG clocks */ + cpg_clocks: clocks@ffc80000 { + compatible = "renesas,r8a7779-cpg-clocks"; + reg = <0xffc80000 0x30>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "plla", "z", "zs", "s", + "s1", "p", "b", "out"; + #power-domain-cells = <0>; + }; + + /* Fixed factor clocks */ + i_clk: i { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + s3_clk: s3 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + s4_clk: s4 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + g_clk: g { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp0_clks: clocks@ffc80030 { + compatible = "renesas,r8a7779-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xffc80030 4>; + clocks = <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7779_CLK_PWM R8A7779_CLK_HSPI + R8A7779_CLK_TMU2 R8A7779_CLK_TMU1 + R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1 + R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5 + R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3 + R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1 + R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 + R8A7779_CLK_I2C2 R8A7779_CLK_I2C1 + R8A7779_CLK_I2C0 + >; + clock-output-names = + "pwm", "hspi", "tmu2", "tmu1", "tmu0", + "hscif1", "hscif0", "scif5", "scif4", "scif3", + "scif2", "scif1", "scif0", "i2c3", "i2c2", + "i2c1", "i2c0"; + }; + mstp1_clks: clocks@ffc80034 { + compatible = "renesas,r8a7779-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xffc80034 4>, <0xffc80044 4>; + clocks = <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>; + #clock-cells = <1>; + clock-indices = < + R8A7779_CLK_USB01 R8A7779_CLK_USB2 + R8A7779_CLK_DU R8A7779_CLK_VIN2 + R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 + R8A7779_CLK_ETHER R8A7779_CLK_SATA + R8A7779_CLK_PCIE R8A7779_CLK_VIN3 + >; + clock-output-names = + "usb01", "usb2", + "du", "vin2", + "vin1", "vin0", + "ether", "sata", + "pcie", "vin3"; + }; + mstp3_clks: clocks@ffc8003c { + compatible = "renesas,r8a7779-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xffc8003c 4>; + clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, + <&s4_clk>, <&s4_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 + R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 + R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 + >; + clock-output-names = + "sdhi3", "sdhi2", "sdhi1", "sdhi0", + "mmc1", "mmc0"; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0xff000044 4>; + }; + + rst: reset-controller@ffcc0000 { + compatible = "renesas,r8a7779-reset-wdt"; + reg = <0xffcc0000 0x48>; + }; + + sysc: system-controller@ffd85000 { + compatible = "renesas,r8a7779-sysc"; + reg = <0xffd85000 0x0200>; + #power-domain-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts new file mode 100644 index 000000000000..5ad5349a50dc --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -0,0 +1,947 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Lager board + * + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. + * Copyright (C) 2015-2016 Renesas Electronics Corporation + */ + +/* + * SSI-AK4643 + * + * SW1: 1: AK4643 + * 2: CN22 + * 3: ADV7511 + * + * This command is required when Playback/Capture + * + * amixer set "LINEOUT Mixer DACL" on + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7790.dtsi" +#include +#include + +/ { + model = "Lager"; + compatible = "renesas,lager", "renesas,r8a7790"; + + aliases { + serial0 = &scif0; + serial1 = &scifa1; + i2c8 = &gpioi2c1; + i2c9 = &gpioi2c2; + i2c10 = &i2cexio0; + i2c11 = &i2cexio1; + i2c12 = &i2chdmi; + i2c13 = &i2cpwr; + mmc0 = &mmcif1; + mmc1 = &sdhi0; + mmc2 = &sdhi2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@140000000 { + device_type = "memory"; + reg = <1 0x40000000 0 0xc0000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + one { + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + two { + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; + three { + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + four { + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + }; + }; + + fixedregulator3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi2: regulator-vcc-sdhi2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4643: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&audio_clock>; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + gpioi2c1: i2c-8 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. + * We use the I2C demuxer, so the desired IP core can be selected at runtime + * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0). + * Note: For testing the I2C slave feature, it is convenient to connect this + * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and + * instantiate the slave device at runtime according to the documentation. + * You can then communicate with the slave via IIC3. + * + * IIC0/I2C0 does not appear to support fallback to GPIO. + */ + i2cexio0: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic0>, <&i2c0>; + i2c-bus-name = "i2c-exio0"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* + * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). + * This is similar to the arangement described for i2cexio0 (above) + * with a fallback to GPIO also provided. + */ + i2cexio1: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-exio1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* + * IIC2 and I2C2 may be switched using pinmux. + * A fallback to GPIO is also provided. + */ + i2chdmi: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep0>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + }; + + /* + * IIC3 and I2C3 may be switched using pinmux. + * IIC3/I2C3 does not appear to support fallback to GPIO. + */ + i2cpwr: i2c-13 { + compatible = "i2c-demux-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; + i2c-parent = <&iic3>, <&i2c3>; + i2c-bus-name = "i2c-pwr"; + #address-cells = <1>; + #size-cells = <0>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&lvds1 { + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + du_pins: du { + groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; + function = "du"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq0"; + function = "intc"; + }; + + scifa1_pins: scifa1 { + groups = "scifa1_data"; + function = "scifa1"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + mmc1_pins: mmc1 { + groups = "mmc1_data8", "mmc1_ctrl"; + function = "mmc1"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + msiof1_pins: msiof1 { + groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", + "msiof1_tx"; + function = "msiof1"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + iic0_pins: iic0 { + groups = "iic0"; + function = "iic0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + iic1_pins: iic1 { + groups = "iic1"; + function = "iic1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + iic2_pins: iic2 { + groups = "iic2"; + function = "iic2"; + }; + + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + + iic3_pins: iic3 { + groups = "iic3"; + function = "iic3"; + }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + + hsusb_pins: hsusb { + groups = "usb0_ovc_vbus"; + function = "usb0"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + usb2_pins: usb2 { + groups = "usb2"; + function = "usb2"; + }; + + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + + vin1_pins: vin1 { + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; + }; + + sound_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a"; + function = "audio_clk"; + }; + + keyboard_pins: keyboard { + pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28"; + bias-pull-up; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpha; + spi-cpol; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scifa1 { + pinctrl-0 = <&scifa1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic: pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "i2c-exio0"; +}; + +&iic0 { + pinctrl-0 = <&iic0_pins>; + pinctrl-names = "i2c-exio0"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-exio1"; +}; + +&iic1 { + pinctrl-0 = <&iic1_pins>; + pinctrl-names = "i2c-exio1"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "i2c-hdmi"; + + clock-frequency = <100000>; +}; + +&iic2 { + pinctrl-0 = <&iic2_pins>; + pinctrl-names = "i2c-hdmi"; + + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "i2c-pwr"; +}; + +&iic3 { + pinctrl-0 = <&iic3_pins>; + pinctrl-names = "i2c-pwr"; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&xhci { + status = "okay"; + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; +}; + +&pci2 { + status = "okay"; + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&hsusb_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + +/* HDMI video input */ +&vin0 { + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + +/* composite video input */ +&vin1 { + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + vin1ep0: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>, <&src2>, <&dvc0>; + capture = <&ssi1>, <&src3>, <&dvc1>; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts new file mode 100644 index 000000000000..fe14727eefe1 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Stout board + * + * Copyright (C) 2018 Marek Vasut + */ + +/dts-v1/; +#include "r8a7790.dtsi" +#include +#include + +/ { + model = "Stout"; + compatible = "renesas,stout", "renesas,r8a7790"; + + aliases { + serial0 = &scifa0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; + led2 { + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + }; + led3 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + }; + led5 { + gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; + }; + + fixedregulator3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + osc1_clk: osc1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + osc4_clk: osc4-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&osc1_clk>; + clock-names = "du.0", "du.1", "du.2", "dclkin.0"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&lvds0 { + ports { + port@1 { + lvds_connector0: endpoint { + }; + }; + }; +}; + +&lvds1 { + ports { + port@1 { + lvds_connector1: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + du_pins: du { + groups = "du_rgb888", "du_sync_1", "du_clk_out_0"; + function = "du"; + }; + + scifa0_pins: scifa0 { + groups = "scifa0_data_b"; + function = "scifa0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq1"; + function = "intc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + iic2_pins: iic2 { + groups = "iic2_b"; + function = "iic2"; + }; + + iic3_pins: iic3 { + groups = "iic3"; + function = "iic3"; + }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpha; + spi-cpol; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "uboot"; + reg = <0x00080000 0x00040000>; + read-only; + }; + partition@c0000 { + label = "uboot-env"; + reg = <0x000c0000 0x00040000>; + read-only; + }; + partition@100000 { + label = "flash"; + reg = <0x00100000 0x03f00000>; + }; + }; + }; +}; + +&scifa0 { + pinctrl-0 = <&scifa0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + +&iic2 { + status = "okay"; + pinctrl-0 = <&iic2_pins>; + pinctrl-names = "default"; + + clock-frequency = <100000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + clocks = <&osc4_clk>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&iic3 { + pinctrl-names = "default"; + pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + }; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd: regulator@70 { + compatible = "dlg,da9210"; + reg = <0x70>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi new file mode 100644 index 000000000000..46fb81f5062f --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -0,0 +1,1965 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car H2 (R8A77900) SoC + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded Inc. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7790"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &iic0; + i2c5 = &iic1; + i2c6 = &iic2; + i2c7 = &iic3; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + spi4 = &msiof3; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; + power-domains = <&sysc R8A7790_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; + power-domains = <&sysc R8A7790_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; + power-domains = <&sysc R8A7790_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; + power-domains = <&sysc R8A7790_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; + power-domains = <&sysc R8A7790_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; + power-domains = <&sysc R8A7790_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; + power-domains = <&sysc R8A7790_PD_CA7_CPU2>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; + power-domains = <&sysc R8A7790_PD_CA7_CPU3>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7790_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7790_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7790-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7790"; + reg = <0 0xe6060000 0 0x250>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7790", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6151000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7790-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7790-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7790", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: iommu@ffc80000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 300>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>, + <&dmac1 0x69>, <&dmac1 0x6a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7790", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7790", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7790-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7790-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7790", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e56000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7790", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7790", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 205>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 215>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>, + <&dmac1 0x45>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 215>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7790", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7790", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7790", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7790_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7790", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x20800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x21000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee120000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7790", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7790", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7790", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7790", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7790", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7790", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 130>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 117>; + }; + + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7790", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7790"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds1: lvds@feb94000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb94000 0 0x1c>; + clocks = <&cpg CPG_MOD 725>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 725>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7790-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7790-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts new file mode 100644 index 000000000000..26a40782cc89 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Koelsch board + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. + */ + +/* + * SSI-AK4643 + * + * SW1: 1: AK4643 + * 2: CN22 + * 3: ADV7511 + * + * This command is required when Playback/Capture + * + * amixer set "LINEOUT Mixer DACL" on + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7791.dtsi" +#include +#include + +/ { + model = "Koelsch"; + compatible = "renesas,koelsch", "renesas,r8a7791"; + + aliases { + serial0 = &scif0; + serial1 = &scif1; + i2c9 = &gpioi2c1; + i2c10 = &gpioi2c2; + i2c11 = &gpioi2c4; + i2c12 = &i2cexio1; + i2c13 = &i2chdmi; + i2c14 = &i2cexio4; + mmc0 = &sdhi0; + mmc1 = &sdhi1; + mmc2 = &sdhi2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW30"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW31"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW32"; + wakeup-source; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW33"; + wakeup-source; + debounce-interval = <20>; + }; + key-e { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW34"; + wakeup-source; + debounce-interval = <20>; + }; + key-f { + gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW35"; + wakeup-source; + debounce-interval = <20>; + }; + key-g { + gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW36"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + label = "LED6"; + }; + led7 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + label = "LED7"; + }; + led8 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + label = "LED8"; + }; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi2: regulator-vcc-sdhi2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4643: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&audio_clock>; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c2: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c4: i2c-11 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio1: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-exio1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-13 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-14 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&lvds0 { + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4_c"; + function = "i2c4"; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_d"; + function = "scif1"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq0"; + function = "intc"; + }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + msiof0_pins: msiof0 { + groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", + "msiof0_tx"; + function = "msiof0"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + + vin1_pins: vin1 { + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; + }; + + sound_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a"; + function = "audio_clk"; + }; + + keyboard_pins: keyboard { + pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; + bias-pull-up; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpha; + spi-cpol; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "user"; + reg = <0x00080000 0x00580000>; + read-only; + }; + partition@600000 { + label = "flash"; + reg = <0x00600000 0x03a00000>; + }; + }; + }; +}; + +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic: pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-exio1"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "i2c-hdmi"; + + clock-frequency = <100000>; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; + status = "okay"; + clock-frequency = <100000>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + +/* HDMI video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + +/* composite video input */ +&vin1 { + status = "okay"; + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + port { + vin1ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>, <&src2>, <&dvc0>; + capture = <&ssi1>, <&src3>, <&dvc1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts new file mode 100644 index 000000000000..ec0a20d5130d --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Porter board + * + * Copyright (C) 2015 Cogent Embedded, Inc. + */ + +/* + * SSI-AK4642 + * + * JP3: 2-1: AK4642 + * 2-3: ADV7511 + * + * This command is required before playback/capture: + * + * amixer set "LINEOUT Mixer DACL" on + */ + +/dts-v1/; +#include "r8a7791.dtsi" +#include + +/ { + model = "Porter"; + compatible = "renesas,porter", "renesas,r8a7791"; + + aliases { + serial0 = &scif0; + i2c9 = &gpioi2c2; + i2c10 = &i2chdmi; + mmc0 = &sdhi0; + mmc1 = &sdhi2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi2: regulator-vcc-sdhi2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x16_clk: x16-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x14_clk: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&soundcodec>; + simple-audio-card,frame-master = <&soundcodec>; + + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + soundcodec: simple-audio-card,codec { + sound-dai = <&ak4642>; + clocks = <&x14_clk>; + }; + }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4642: codec@12 { + compatible = "asahi-kasei,ak4642"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq0"; + function = "intc"; + }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + vin0_pins: vin0 { + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; + }; + + can0_pins: can0 { + groups = "can0_data"; + function = "can0"; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; + }; + + ssi_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + audio_clk_pins: audio_clk { + groups = "audio_clk_a"; + function = "audio_clk"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader_prg"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user_prg"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash_fs"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "i2c-hdmi"; + + clock-frequency = <400000>; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; + status = "okay"; + clock-frequency = <100000>; + + pmic@5a { + compatible = "dlg,da9063l"; + reg = <0x5a>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&sata0 { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + +/* composite video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pci1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&hsusb { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&x3_clk>, <&x16_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&lvds0 { + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>; + capture = <&ssi1>; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi new file mode 100644 index 000000000000..b9d34147628e --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -0,0 +1,1891 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car M2-W (R8A77910) SoC + * + * Copyright (C) 2013-2015 Renesas Electronics Corporation + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded Inc. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7791"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; + power-domains = <&sysc R8A7791_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; + power-domains = <&sysc R8A7791_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7791-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7791"; + reg = <0 0xe6060000 0 0x250>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7791", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7791-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7791", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7791", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: iommu@ffc80000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: iommu@e62a0000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7791", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7791", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7791-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7791-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7791", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 205>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + adc: adc@e6e54000 { + compatible = "renesas,r8a7791-gyroadc", + "renesas,rcar-gyroadc"; + reg = <0 0xe6e54000 0 64>; + clocks = <&cpg CPG_MOD 901>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 901>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7791", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7791", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7791", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7791_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", "src.9", "src.8", + "src.7", "src.6", "src.5", "src.4", + "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7791", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7791", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7791", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7791", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7791", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7791", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7791", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7791", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7791", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7791"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7791-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7791-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7791-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts new file mode 100644 index 000000000000..c66de9dd12df --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Blanche board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a7792.dtsi" +#include +#include + +/ { + model = "Blanche"; + compatible = "renesas,blanche", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + serial1 = &scif3; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + d3_3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0 0x18000000 0 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + x1_clk: x1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x2_clk: x2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <65000000>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + key-1 { + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + key-2 { + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + }; + key-3 { + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + }; + key-4 { + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + key-a { + linux,code = ; + label = "SW24"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + }; + key-b { + linux,code = ; + label = "SW25"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led17 { + gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; + }; + led18 { + gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; + }; + led19 { + gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; + }; + led20 { + gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&can_clk { + clock-frequency = <48000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif3_pins: scif3 { + groups = "scif3_data"; + function = "scif3"; + }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; + + can0_pins: can0 { + groups = "can0_data", "can_clk"; + function = "can0"; + }; + + sdhi0_pins: sdhi0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp"; + function = "du1"; + }; + + keyboard_pins: keyboard { + pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02"; + bias-pull-up; + }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&iic3 { + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; + interrupt-parent = <&irqc>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins>, <&du1_pins>; + pinctrl-names = "default"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts new file mode 100644 index 000000000000..434e4655be9d --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Wheat board + * + * Copyright (C) 2016 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a7792.dtsi" +#include +#include + +/ { + model = "Wheat"; + compatible = "renesas,wheat", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + d3_3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0 0x18000000 0 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + smsc,save-mac-address; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; + + keyboard { + compatible = "gpio-keys"; + + key-a { + linux,code = ; + label = "SW2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + }; + key-b { + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; + }; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + hdmi-out0 { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con0: endpoint { + remote-endpoint = <&adv7513_0_out>; + }; + }; + }; + + hdmi-out1 { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con1: endpoint { + remote-endpoint = <&adv7513_1_out>; + }; + }; + }; + + osc2_clk: osc2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; + + can0_pins: can0 { + groups = "can0_data"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; + + sdhi0_pins: sdhi0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp"; + function = "du1"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + /* + * The adv75xx resets its addresses to defaults during low power mode. + * Because we have two ADV7513 devices on the same bus, we must change + * both of them away from the defaults so that they do not conflict. + */ + hdmi@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; + reg-names = "main", "edid", "cec", "packet"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_0_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7513_0_out: endpoint { + remote-endpoint = <&hdmi_con0>; + }; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7513"; + reg = <0x39>, <0x49>, <0x29>, <0x59>; + reg-names = "main", "edid", "cec", "packet"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_1_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + + port@1 { + reg = <1>; + adv7513_1_out: endpoint { + remote-endpoint = <&hdmi_con1>; + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins>, <&du1_pins>; + pinctrl-names = "default"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7513_0_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7513_1_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi new file mode 100644 index 000000000000..a6d9367f8fa0 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -0,0 +1,928 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car V2H (R8A77920) SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7792"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &iic3; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; + vin4 = &vin4; + vin5 = &vin5; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; + power-domains = <&sysc R8A7792_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; + power-domains = <&sysc R8A7792_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7792_PD_CA15_SCU>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7792-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055100 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055100 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055200 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055200 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; + + gpio8: gpio@e6055300 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055300 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 921>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 921>; + }; + + gpio9: gpio@e6055400 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 919>; + }; + + gpio10: gpio@e6055500 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055500 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 914>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 914>; + }; + + gpio11: gpio@e6055600 { + compatible = "renesas,gpio-r8a7792", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055600 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 352 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 913>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 913>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7792"; + reg = <0 0xe6060000 0 0x144>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7792-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7792-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7792-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7792", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7792", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7792", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7792", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7792", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7792", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7792", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7792", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7792", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 805>; + status = "disabled"; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 804>; + status = "disabled"; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7792", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + clocks = <&cpg CPG_MOD 314>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7792", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7792"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7792-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7792-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts new file mode 100644 index 000000000000..79b537b24642 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -0,0 +1,818 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Gose board + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + */ + +/* + * SSI-AK4643 + * + * SW1: 1: AK4643 + * 2: CN22 + * 3: ADV7511 + * + * This command is required when Playback/Capture + * + * amixer set "LINEOUT Mixer DACL" on + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7793.dtsi" +#include +#include + +/ { + model = "Gose"; + compatible = "renesas,gose", "renesas,r8a7793"; + + aliases { + serial0 = &scif0; + serial1 = &scif1; + i2c9 = &gpioi2c2; + i2c10 = &gpioi2c4; + i2c11 = &i2chdmi; + i2c12 = &i2cexio4; + mmc0 = &sdhi0; + mmc1 = &sdhi1; + mmc2 = &sdhi2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW30"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW31"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW32"; + wakeup-source; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW33"; + wakeup-source; + debounce-interval = <20>; + }; + key-e { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW34"; + wakeup-source; + debounce-interval = <20>; + }; + key-f { + gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW35"; + wakeup-source; + debounce-interval = <20>; + }; + key-g { + gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW36"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + label = "LED6"; + }; + led7 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + label = "LED7"; + }; + led8 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + label = "LED8"; + }; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi2: regulator-vcc-sdhi2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4643: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&audio_clock>; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c4: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; +}; + +&lvds0 { + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4_c"; + function = "i2c4"; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_d"; + function = "scif1"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq0"; + function = "intc"; + }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + sound_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a"; + function = "audio_clk"; + }; + + keyboard_pins: keyboard { + pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; + bias-pull-up; + }; + + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + + vin1_pins: vin1 { + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "i2c-hdmi"; + + status = "okay"; + clock-frequency = <100000>; + +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; + status = "okay"; + clock-frequency = <100000>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>, <&src2>, <&dvc0>; + capture = <&ssi1>, <&src3>, <&dvc1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; + +/* HDMI video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + +/* composite video input */ +&vin1 { + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + vin1ep: endpoint { + remote-endpoint = <&adv7180_out>; + bus-width = <8>; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi new file mode 100644 index 000000000000..f51bf687f4bd --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -0,0 +1,1470 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car M2-N (R8A77930) SoC + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7793"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + spi0 = &qspi; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; + power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + next-level-cache = <&L2_CA15>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; + power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7793_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7793-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7793"; + reg = <0 0xe6060000 0 0x250>; + }; + + /* Special CPG clocks */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7793-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7793-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7793-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7793", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7793", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: iommu@ffc80000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: iommu@e62a0000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7793", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7793", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7793", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7793", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7793_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7793", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7793", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7793"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7793-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 726>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7793-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7793-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts new file mode 100644 index 000000000000..4d93319674c6 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Alt board + * + * Copyright (C) 2014 Renesas Electronics Corporation + */ + +/dts-v1/; +#include "r8a7794.dtsi" +#include +#include + +/ { + model = "Alt"; + compatible = "renesas,alt", "renesas,r8a7794"; + + aliases { + serial0 = &scif2; + i2c9 = &gpioi2c1; + i2c10 = &gpioi2c4; + i2c11 = &i2chdmi; + i2c12 = &i2cexio4; + mmc0 = &mmcif0; + mmc1 = &sdhi0; + mmc2 = &sdhi1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + d3_3v: regulator-d3-3v { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + one { + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + }; + two { + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + three { + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + }; + four { + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x13_clk: x13-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + }; + + gpioi2c4: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C1. + */ + i2chdmi: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-14 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + du_pins: du { + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; + function = "du1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + vin0_pins: vin0 { + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; + }; + + mmcif0_pins: mmcif0 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + keyboard_pins: keyboard { + pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; + bias-pull-up; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&pfc { + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&d3_3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-hdmi"; + + clock-frequency = <400000>; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <100000>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; +}; + +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "system"; + reg = <0x00040000 0x00040000>; + read-only; + }; + partition@80000 { + label = "user"; + reg = <0x00080000 0x03f80000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts new file mode 100644 index 000000000000..b7af1befa126 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SILK board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014-2015 Renesas Solutions Corp. + * Copyright (C) 2014-2015 Cogent Embedded, Inc. + */ + +/* + * SSI-AK4643 + * + * SW1: 2-1: AK4643 + * 2-3: ADV7511 + * + * This command is required before playback/capture: + * + * amixer set "LINEOUT Mixer DACL" on + */ + +/dts-v1/; +#include "r8a7794.dtsi" +#include +#include + +/ { + model = "SILK"; + compatible = "renesas,silk", "renesas,r8a7794"; + + aliases { + serial0 = &scif2; + i2c9 = &gpioi2c1; + i2c10 = &i2chdmi; + mmc0 = &mmcif0; + mmc1 = &sdhi1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + key-3 { + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4"; + wakeup-source; + debounce-interval = <20>; + }; + key-6 { + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW6"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + d3_3v: regulator-d3-3v { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x9_clk: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&soundcodec>; + simple-audio-card,frame-master = <&soundcodec>; + + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + soundcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&x9_clk>; + }; + }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C1. + */ + i2chdmi: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmcif0_pins: mmcif0 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + vin0_pins: vin0 { + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; + function = "du1"; + }; + + keyboard_pins: keyboard { + pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; + bias-pull-up; + }; + + ssi_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + audio_clk_pins: audio_clk { + groups = "audio_clkc"; + function = "audio_clk"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +ðer { + pinctrl-0 = <ðer_pins>, <&phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-hdmi"; + + clock-frequency = <400000>; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <100000>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + }; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + }; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&d3_3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; + +/* composite video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; + +&du { + pinctrl-0 = <&du0_pins>, <&du1_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&x2_clk>, <&x3_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>; + capture = <&ssi1>; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi new file mode 100644 index 000000000000..371dd4715dde --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -0,0 +1,1437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car E2 (R8A77940) SoC + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014 Ulrich Hecht + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7794"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + spi0 = &qspi; + vin0 = &vin0; + vin1 = &vin1; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; + power-domains = <&sysc R8A7794_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; + power-domains = <&sysc R8A7794_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; + next-level-cache = <&L2_CA7>; + }; + + L2_CA7: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7794_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7794-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7794"; + reg = <0 0xe6060000 0 0x11c>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6151000 { + compatible = "renesas,r8a7794-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0>, <&cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7794-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7794-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7794", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: iommu@e62a0000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 931>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 930>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 929>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 928>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 927>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 925>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c6: i2c@e6500000 { + compatible = "renesas,iic-r8a7794", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 318>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@e6510000 { + compatible = "renesas,iic-r8a7794", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 323>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7794", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7794", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7794", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7794", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7794", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7794", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7794", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7794", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required if simple-card + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7794", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&cpg CPG_CORE R8A7794_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", + "src.2", "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src-0 { + status = "disabled"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7794", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7794", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7794", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7794", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7794"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7794-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7794-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi new file mode 100644 index 000000000000..6e7589ea7562 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common file for the AA121TD01 panel connected to Renesas R-Car boards + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +/ { + panel { + compatible = "mitsubishi,aa121td01", "panel-lvds"; + + width-mm = <261>; + height-mm = <163>; + data-mapping = "jeida-18"; + + panel-timing { + /* 1280x800 @60Hz */ + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hsync-len = <70>; + hfront-porch = <20>; + hback-porch = <70>; + vsync-len = <5>; + vfront-porch = <3>; + vback-porch = <15>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_connector>; + }; + }; + }; +}; + +&lvds_connector { + remote-endpoint = <&panel_in>; +}; diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts new file mode 100644 index 000000000000..c18bbd7141c4 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZN1D-DB Board + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +/dts-v1/; + +#include +#include + +#include "r9a06g032.dtsi" + +/ { + model = "RZN1D-DB Board"; + compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; +}; + +&can0 { + pinctrl-0 = <&pins_can0>; + pinctrl-names = "default"; + + /* Assuming CN10/CN11 are wired for CAN1 */ + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&pins_can1>; + pinctrl-names = "default"; + + /* Please only enable can0 or can1, depending on CN10/CN11 */ + /* status = "okay"; */ +}; + +ð_miic { + status = "okay"; + renesas,miic-switch-portin = ; +}; + +&gmac2 { + status = "okay"; + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&mii_conv4 { + renesas,miic-input = ; + status = "okay"; +}; + +&mii_conv5 { + renesas,miic-input = ; + status = "okay"; +}; + +&pinctrl{ + pins_can0: pins_can0 { + pinmux = , /* CAN0_TXD */ + ; /* CAN0_RXD */ + drive-strength = <6>; + }; + + pins_can1: pins_can1 { + pinmux = , /* CAN1_TXD */ + ; /* CAN1_RXD */ + drive-strength = <6>; + }; + + pins_eth3: pins_eth3 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <6>; + bias-disable; + }; + + pins_eth4: pins_eth4 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <6>; + bias-disable; + }; + + pins_mdio1: pins_mdio1 { + pinmux = , + ; + }; +}; + +&rtc0 { + status = "okay"; +}; + +&switch { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; + + dsa,member = <0 0>; + + mdio { + clock-frequency = <2500000>; + + #address-cells = <1>; + #size-cells = <0>; + + switch0phy4: ethernet-phy@4 { + reg = <4>; + micrel,led-mode = <1>; + }; + + switch0phy5: ethernet-phy@5 { + reg = <5>; + micrel,led-mode = <1>; + }; + }; +}; + +&switch_port0 { + label = "lan0"; + phy-mode = "mii"; + phy-handle = <&switch0phy5>; + status = "okay"; +}; + +&switch_port1 { + label = "lan1"; + phy-mode = "mii"; + phy-handle = <&switch0phy4>; + status = "okay"; +}; + +&switch_port4 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi new file mode 100644 index 000000000000..0fa565a1c3ad --- /dev/null +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include +#include + +/ { + compatible = "renesas,r9a06g032"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clocks = <&sysctrl R9A06G032_CLK_A7MP>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clocks = <&sysctrl R9A06G032_CLK_A7MP>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0 0x4000c204>; + }; + }; + + ext_jtag_clk: extjtagclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_mclk: extmclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + + ext_rgmii_ref: extrgmiiref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_rtc_clk: extrtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + rtc0: rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = , + , + ; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + wdt0: watchdog@40008000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + wdt1: watchdog@40009000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40009000 0x1000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + #power-domain-cells = <0>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #address-cells = <1>; + #size-cells = <1>; + + dmamux: dma-router@a0 { + compatible = "renesas,rzn1-dmamux"; + reg = <0xa0 4>; + #dma-cells = <6>; + dma-requests = <32>; + dma-masters = <&dma0 &dma1>; + }; + }; + + udc: usb@4001e000 { + compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; + reg = <0x4001e000 0x2000>; + interrupts = , + ; + clocks = <&sysctrl R9A06G032_HCLK_USBF>, + <&sysctrl R9A06G032_HCLK_USBPM>; + clock-names = "hclkf", "hclkpm"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + }; + + uart0: serial@40060000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@40061000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40061000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@40062000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40062000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@50000000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50000000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@50001000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50001000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@50002000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50002000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart6: serial@50003000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50003000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart7: serial@50004000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50004000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pinctrl: pinctrl@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + status = "okay"; + }; + + nand_controller: nand-controller@40102000 { + compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; + reg = <0x40102000 0x2000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; + clock-names = "hclk", "eclk"; + power-domains = <&sysctrl>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dma0: dma-controller@40104000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40104000 0x1000>; + interrupts = ; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + dma1: dma-controller@40105000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40105000 0x1000>; + interrupts = ; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA1>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + gmac2: ethernet@44002000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + + eth_miic: eth-miic@44030000 { + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44030000 0x10000>; + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, + <&sysctrl R9A06G032_CLK_RGMII_REF>, + <&sysctrl R9A06G032_CLK_RMII_REF>, + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + + mii_conv4: mii-conv@4 { + reg = <4>; + status = "disabled"; + }; + + mii_conv5: mii-conv@5 { + reg = <5>; + status = "disabled"; + }; + }; + + switch: switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, + <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + power-domains = <&sysctrl>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0>; + pcs-handle = <&mii_conv5>; + status = "disabled"; + }; + + switch_port1: port@1 { + reg = <1>; + pcs-handle = <&mii_conv4>; + status = "disabled"; + }; + + switch_port2: port@2 { + reg = <2>; + pcs-handle = <&mii_conv3>; + status = "disabled"; + }; + + switch_port3: port@3 { + reg = <3>; + pcs-handle = <&mii_conv2>; + status = "disabled"; + }; + + switch_port4: port@4 { + reg = <4>; + ethernet = <&gmac2>; + label = "cpu"; + phy-mode = "internal"; + status = "disabled"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gic: interrupt-controller@44101000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + ; + }; + + can0: can@52104000 { + compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + can1: can@52105000 { + compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; + reg = <0x52105000 0x800>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysctrl R9A06G032_HCLK_CAN1>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + , + , + , + ; + }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts b/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts new file mode 100644 index 000000000000..98897f710063 --- /dev/null +++ b/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the KZM-A9-GT board + * + * Copyright (C) 2012 Horms Solutions Ltd. + * + * Based on sh73a0-kzm9g.dts + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +/dts-v1/; +#include "sh73a0.dtsi" +#include +#include +#include + +/ { + model = "KZM-A9-GT"; + compatible = "renesas,kzm9g", "renesas,sh73a0"; + + aliases { + serial0 = &scifa4; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd_dvfs>; + operating-points = <1196000 1315000>, /* kHz uV */ + < 598000 1175000>, + < 398667 1065000>; + voltage-tolerance = <1>; /* 1% */ + }; + }; + + chosen { + bootargs = "root=/dev/nfs ip=on ignore_loglevel rw"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc_sdhi0: regulator-vmmc-sdhi0 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vmmc_sdhi2: regulator-vmmc-sdhi2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&pfc 20 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + led2 { + gpios = <&pfc 21 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + led3 { + gpios = <&pfc 22 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + led4 { + gpios = <&pfc 23 GPIO_ACTIVE_LOW>; + label = "LED4"; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + back-key { + gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW3"; + }; + + right-key { + gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-R"; + }; + + left-key { + gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-L"; + }; + + enter-key { + gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-P"; + }; + + up-key { + gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-U"; + }; + + down-key { + gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-D"; + }; + + home-key { + gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW1"; + wakeup-source; + }; + + wakeup-key { + gpios = <&pfc 159 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "NMI"; + wakeup-source; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "left_j"; + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + }; + simple-audio-card,codec { + sound-dai = <&ak4648>; + bitclock-master; + frame-master; + system-clock-frequency = <11289600>; + }; + }; +}; + +&bsc { + ethernet@10000000 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <0x10000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqpin0>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + reg-io-width = <4>; + smsc,irq-push-pull; + smsc,save-mac-address; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; +}; + +&cmt1 { + status = "okay"; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&i2c0 { + status = "okay"; + + compass@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + interrupt-parent = <&irqpin3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + + ak4648: codec@12 { + compatible = "asahi-kasei,ak4648"; + reg = <0x12>; + #sound-dai-cells = <0>; + }; + + accelerometer@1d { + compatible = "adi,adxl345"; + reg = <0x1d>; + interrupt-parent = <&irqpin3>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + rtc@32 { + compatible = "ricoh,r2025sd"; + reg = <0x32>; + }; + + as3711@40 { + compatible = "ams,as3711"; + reg = <0x40>; + + regulators { + vdd_dvfs: sd1 { + regulator-name = "1.315V CPU"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + sd2 { + regulator-name = "1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sd4 { + regulator-name = "1.215V"; + regulator-min-microvolt = <1215000>; + regulator-max-microvolt = <1235000>; + regulator-always-on; + regulator-boot-on; + }; + ldo2 { + regulator-name = "2.8V CPU"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo3 { + regulator-name = "3.0V CPU"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + ldo4 { + regulator-name = "2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo5 { + regulator-name = "2.8V #2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo7 { + regulator-name = "1.15V CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + ldo8 { + regulator-name = "1.15V CPU #2"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + pcf8575: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&mmcif { + pinctrl-0 = <&mmcif_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + vmmc-supply = <®_1p8v>; + status = "okay"; +}; + +&pfc { + i2c3_pins: i2c3 { + groups = "i2c3_1"; + function = "i2c3"; + }; + + mmcif_pins: mmc { + mux { + groups = "mmc0_data8_0", "mmc0_ctrl_0"; + function = "mmc0"; + }; + cfg { + groups = "mmc0_data8_0"; + pins = "PORT279"; + bias-pull-up; + }; + }; + + scifa4_pins: scifa4 { + groups = "scifa4_data", "scifa4_ctrl"; + function = "scifa4"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; + function = "sdhi0"; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + }; + + fsia_pins: sounda { + groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + function = "fsia"; + }; +}; + +&scifa4 { + pinctrl-0 = <&scifa4_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi0>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi2>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/renesas/sh73a0.dtsi b/arch/arm/boot/dts/renesas/sh73a0.dtsi new file mode 100644 index 000000000000..30c67acc4e35 --- /dev/null +++ b/arch/arm/boot/dts/renesas/sh73a0.dtsi @@ -0,0 +1,949 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC + * + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,sh73a0"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; + power-domains = <&pd_a2sl>; + next-level-cache = <&L2>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; + power-domains = <&pd_a2sl>; + next-level-cache = <&L2>; + }; + }; + + timer@f0000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf0000200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + timer@f0000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf0000600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@f0001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xf0001000 0x1000>, + <0xf0000100 0x100>; + }; + + L2: cache-controller@f0100000 { + compatible = "arm,pl310-cache"; + reg = <0xf0100000 0x1000>; + interrupts = ; + power-domains = <&pd_a3sm>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,shared-override; + cache-unified; + cache-level = <2>; + }; + + sbsc2: memory-controller@fb400000 { + compatible = "renesas,sbsc-sh73a0"; + reg = <0xfb400000 0x400>; + interrupts = , + ; + interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc1>; + }; + + sbsc1: memory-controller@fe400000 { + compatible = "renesas,sbsc-sh73a0"; + reg = <0xfe400000 0x400>; + interrupts = , + ; + interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + cmt1: timer@e6138000 { + compatible = "renesas,sh73a0-cmt1"; + reg = <0xe6138000 0x200>; + interrupts = ; + clocks = <&mstp3_clks SH73A0_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; + status = "disabled"; + }; + + irqpin0: interrupt-controller@e6900000 { + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900000 4>, + <0xe6900010 4>, + <0xe6900020 1>, + <0xe6900040 1>, + <0xe6900060 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; + }; + + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; + }; + + irqpin2: interrupt-controller@e6900008 { + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900008 4>, + <0xe6900018 4>, + <0xe6900028 1>, + <0xe6900048 1>, + <0xe6900068 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; + }; + + irqpin3: interrupt-controller@e690000c { + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe690000c 4>, + <0xe690001c 4>, + <0xe690002c 1>, + <0xe690004c 1>, + <0xe690006c 1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; + control-parent; + }; + + i2c0: i2c@e6820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; + reg = <0xe6820000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp1_clks SH73A0_CLK_IIC0>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c1: i2c@e6822000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; + reg = <0xe6822000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp3_clks SH73A0_CLK_IIC1>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c2: i2c@e6824000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; + reg = <0xe6824000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp0_clks SH73A0_CLK_IIC2>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c3: i2c@e6826000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; + reg = <0xe6826000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks SH73A0_CLK_IIC3>; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + i2c4: i2c@e6828000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; + reg = <0xe6828000 0x425>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks SH73A0_CLK_IIC4>; + power-domains = <&pd_c5>; + status = "disabled"; + }; + + mmcif: mmc@e6bd0000 { + compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupts = , + ; + clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; + power-domains = <&pd_a3sp>; + reg-io-width = <4>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; + reg = <0xe6e20000 0x0064>; + interrupts = ; + clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; + power-domains = <&pd_a3sp>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; + reg = <0xe6e10000 0x0064>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; + power-domains = <&pd_a3sp>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; + reg = <0xe6e00000 0x0064>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; + power-domains = <&pd_a3sp>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; + reg = <0xe6c90000 0x0064>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; + power-domains = <&pd_a3sp>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-sh73a0"; + reg = <0xee100000 0x100>; + interrupts = , + , + ; + clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; + power-domains = <&pd_a3sp>; + cap-sd-highspeed; + status = "disabled"; + }; + + /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-sh73a0"; + reg = <0xee120000 0x100>; + interrupts = , + ; + clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; + power-domains = <&pd_a3sp>; + disable-wp; + cap-sd-highspeed; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-sh73a0"; + reg = <0xee140000 0x100>; + interrupts = , + ; + clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; + power-domains = <&pd_a3sp>; + disable-wp; + cap-sd-highspeed; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c40000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c50000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c60000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c70000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa4: serial@e6c80000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6c80000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa5: serial@e6cb0000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6cb0000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa6: serial@e6cc0000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6cc0000 0x100>; + interrupts = ; + clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifa7: serial@e6cd0000 { + compatible = "renesas,scifa-sh73a0", "renesas,scifa"; + reg = <0xe6cd0000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + scifb: serial@e6c30000 { + compatible = "renesas,scifb-sh73a0", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = ; + clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + status = "disabled"; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-sh73a0"; + reg = <0xe6050000 0x8000>, + <0xe605801c 0x1c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, + <&pfc 288 288 22>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; + reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_c4: c4@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_a4bc0: a4bc0@4 { + reg = <4>; + #power-domain-cells = <0>; + }; + + pd_a4bc1: a4bc1@5 { + reg = <5>; + #power-domain-cells = <0>; + }; + + pd_a4lc0: a4lc0@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + + pd_a4lc1: a4lc1@7 { + reg = <7>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3mp: a3mp@9 { + reg = <9>; + #power-domain-cells = <0>; + }; + + pd_a3vc: a3vc@10 { + reg = <10>; + #power-domain-cells = <0>; + }; + }; + + pd_a4rm: a4rm@12 { + reg = <12>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3r: a3r@13 { + reg = <13>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2rv: a2rv@14 { + reg = <14>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + }; + }; + }; + + pd_a4s: a4s@16 { + reg = <16>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sp: a3sp@17 { + reg = <17>; + #power-domain-cells = <0>; + }; + + pd_a3sg: a3sg@18 { + reg = <18>; + #power-domain-cells = <0>; + }; + + pd_a3sm: a3sm@19 { + reg = <19>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2sl: a2sl@20 { + reg = <20>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + }; + + sh_fsi2: sound@ec230000 { + #sound-dai-cells = <1>; + compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; + reg = <0xec230000 0x400>; + interrupts = ; + clocks = <&mstp3_clks SH73A0_CLK_FSI>; + power-domains = <&pd_a4mp>; + status = "disabled"; + }; + + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = ; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External root clocks */ + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + extal1_clk: extal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + extal2_clk: extal2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + extcki_clk: extcki { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value can be overridden by the board. */ + clock-frequency = <0>; + }; + fsiack_clk: fsiack { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value can be overridden by the board. */ + clock-frequency = <0>; + }; + fsibck_clk: fsibck { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value can be overridden by the board. */ + clock-frequency = <0>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,sh73a0-cpg-clocks"; + reg = <0xe6150000 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll3", "dsi0phy", "dsi1phy", + "zg", "m3", "b", "m1", "m2", + "z", "zx", "hp"; + }; + + /* Variable factor clocks (DIV6) */ + vclk1_clk: vclk1@e6150008 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150008 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; + #clock-cells = <0>; + }; + vclk2_clk: vclk2@e615000c { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615000c 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; + #clock-cells = <0>; + }; + vclk3_clk: vclk3@e615001c { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615001c 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, + <0>; + #clock-cells = <0>; + }; + zb_clk: zb_clk@e6150010 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150010 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; + #clock-cells = <0>; + clock-output-names = "zb"; + }; + flctl_clk: flctlck@e6150014 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150014 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; + #clock-cells = <0>; + }; + sdhi0_clk: sdhi0ck@e6150074 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150074 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; + #clock-cells = <0>; + }; + sdhi1_clk: sdhi1ck@e6150078 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150078 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; + #clock-cells = <0>; + }; + sdhi2_clk: sdhi2ck@e615007c { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615007c 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>, <0>; + #clock-cells = <0>; + }; + fsia_clk: fsia@e6150018 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150018 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsiack_clk>, <&fsiack_clk>; + #clock-cells = <0>; + }; + fsib_clk: fsib@e6150090 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150090 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsibck_clk>, <&fsibck_clk>; + #clock-cells = <0>; + }; + sub_clk: sub@e6150080 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150080 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + }; + spua_clk: spua@e6150084 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150084 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + }; + spuv_clk: spuv@e6150094 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150094 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + }; + msu_clk: msu@e6150088 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150088 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; + #clock-cells = <0>; + }; + hsi_clk: hsi@e615008c { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615008c 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div7_clk>, <0>; + #clock-cells = <0>; + }; + mfg1_clk: mfg1@e6150098 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150098 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; + #clock-cells = <0>; + }; + mfg2_clk: mfg2@e615009c { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615009c 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; + #clock-cells = <0>; + }; + dsit_clk: dsit@e6150060 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150060 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks SH73A0_CLK_PLL2>, <0>; + #clock-cells = <0>; + }; + dsi0p_clk: dsi0pck@e6150064 { + compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150064 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, + <&extcki_clk>, <0>, <0>, <0>; + #clock-cells = <0>; + }; + + /* Fixed factor clocks */ + main_div2_clk: main_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks SH73A0_CLK_MAIN>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks SH73A0_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + pll1_div7_clk: pll1_div7 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks SH73A0_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + pll1_div13_clk: pll1_div13 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks SH73A0_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <13>; + clock-mult = <1>; + }; + periph_clk: periph { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks SH73A0_CLK_Z>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150130 4>, <0xe6150030 4>; + clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 + >; + clock-output-names = + "iic2", "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150134 4>, <0xe6150038 4>; + clocks = <&cpg_clocks SH73A0_CLK_B>, + <&cpg_clocks SH73A0_CLK_B>, + <&cpg_clocks SH73A0_CLK_B>, + <&cpg_clocks SH73A0_CLK_B>, + <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, + <&cpg_clocks SH73A0_CLK_HP>, + <&cpg_clocks SH73A0_CLK_ZG>, + <&cpg_clocks SH73A0_CLK_B>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 + SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 + SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 + SH73A0_CLK_IIC0 SH73A0_CLK_SGX + SH73A0_CLK_LCDC0 + >; + clock-output-names = + "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", + "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150138 4>, <0xe6150040 4>; + clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, + <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC + SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 + SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 + SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 + SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 + SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 + SH73A0_CLK_SCIFA4 + >; + clock-output-names = + "scifa7", "sy_dmac", "mp_dmac", "msiof3", + "msiof1", "scifa5", "scifb", "msiof2", + "scifa0", "scifa1", "scifa2", "scifa3", + "scifa4"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe615013c 4>, <0xe6150048 4>; + clocks = <&sub_clk>, <&extalr_clk>, + <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, + <&cpg_clocks SH73A0_CLK_HP>, + <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, + <&sdhi0_clk>, <&sdhi1_clk>, + <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, + <&main_div2_clk>, <&main_div2_clk>, + <&main_div2_clk>, <&main_div2_clk>, + <&main_div2_clk>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 + SH73A0_CLK_FSI SH73A0_CLK_IRDA + SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL + SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 + SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 + SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 + SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 + SH73A0_CLK_TPU4 + >; + clock-output-names = + "scifa6", "cmt1", "fsi", "irda", "iic1", + "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", + "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150140 4>, <0xe615004c 4>; + clocks = <&cpg_clocks SH73A0_CLK_HP>, + <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 + SH73A0_CLK_KEYSC + >; + clock-output-names = + "iic3", "iic4", "keysc"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150144 4>, <0xe615003c 4>; + clocks = <&cpg_clocks SH73A0_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + SH73A0_CLK_INTCA0 + >; + clock-output-names = + "intca0"; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts deleted file mode 100644 index becdc0b664bf..000000000000 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "Rockchip RK3036 Evaluation board"; - compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; -}; - -&emac { - phy = <&phy0>; - phy-reset-duration = <10>; /* millisecond */ - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts deleted file mode 100644 index 67e1e04139e7..000000000000 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "Rockchip RK3036 KylinBoard"; - compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x20000000>; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - work_led: led-0 { - gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - label = "kylin:red:led"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_wake_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - SDIO_RESET_L_WL_RST - * - SDIO_RESET_L_BT_EN - */ - reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */ - <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rt5616-codec"; - simple-audio-card,mclk-fs = <512>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC1", "Microphone Jack", - "MIC2", "Microphone Jack", - "Microphone Jack", "micbias1", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5616>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&acodec { - status = "okay"; -}; - -&emac { - phy = <&phy0>; - phy-reset-duration = <10>; /* millisecond */ - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&emmc { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vout5: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vout5"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - - rt5616: rt5616@1b { - compatible = "rt5616"; - reg = <0x1b>; - clocks = <&cru SCLK_I2S_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s { - status = "okay"; -}; - -&sdio { - status = "okay"; - - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - rockchip,default-sample-phase = <90>; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&pinctrl { - leds { - led_ctl: led-ctl { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - bt_wake_h: bt-wake-h { - rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - suspend { - global_pwroff: global-pwroff { - rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi deleted file mode 100644 index 78686fc72ce6..000000000000 --- a/arch/arm/boot/dts/rk3036.dtsi +++ /dev/null @@ -1,871 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rk3036"; - - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi = &spi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3036-smp"; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - bus_intmem: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - gpu: gpu@10090000 { - compatible = "rockchip,rk3036-mali", "arm,mali-400"; - reg = <0x10090000 0x10000>; - interrupts = , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0"; - assigned-clocks = <&cru SCLK_GPU>; - assigned-clock-rates = <100000000>; - clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; - clock-names = "bus", "core"; - power-domains = <&power RK3036_PD_GPU>; - resets = <&cru SRST_GPU>; - status = "disabled"; - }; - - vpu: video-codec@10108000 { - compatible = "rockchip,rk3036-vpu"; - reg = <0x10108000 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3036_PD_VPU>; - }; - - vpu_mmu: iommu@10108800 { - compatible = "rockchip,iommu"; - reg = <0x10108800 0x100>; - interrupts = ; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3036_PD_VPU>; - #iommu-cells = <0>; - }; - - vop: vop@10118000 { - compatible = "rockchip,rk3036-vop"; - reg = <0x10118000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - power-domains = <&power RK3036_PD_VIO>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@10118300 { - compatible = "rockchip,iommu"; - reg = <0x10118300 0x100>; - interrupts = ; - clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3036_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - qos_gpu: qos@1012d000 { - compatible = "rockchip,rk3036-qos", "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { - compatible = "rockchip,rk3036-qos", "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_vio: qos@1012f000 { - compatible = "rockchip,rk3036-qos", "syscon"; - reg = <0x1012f000 0x20>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x10139000 0x1000>, - <0x1013a000 0x2000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = ; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - status = "disabled"; - }; - - emac: ethernet@10200000 { - compatible = "rockchip,rk3036-emac"; - reg = <0x10200000 0x4000>; - interrupts = ; - rockchip,grf = <&grf>; - clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref", "macclk"; - /* - * Fix the emac parent clock is DPLL instead of APLL. - * since that will cause some unstable things if the cpufreq - * is working. (e.g: the accurate 50MHz what mac_ref need) - */ - assigned-clocks = <&cru SCLK_MACPLL>; - assigned-clock-parents = <&cru PLL_DPLL>; - max-speed = <100>; - phy-mode = "rmii"; - status = "disabled"; - }; - - sdmmc: mmc@10214000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio: mmc@10218000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10218000 0x4000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - interrupts = ; - bus-width = <8>; - cap-mmc-highspeed; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - rockchip,default-sample-phase = <158>; - disable-wp; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <0x100>; - mmc-ddr-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - i2s: i2s@10220000 { - compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; - reg = <0x10220000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - nfc: nand-controller@10500000 { - compatible = "rockchip,rk3036-nfc", - "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - assigned-clocks = <&cru SCLK_NANDC>; - assigned-clock-rates = <150000000>; - pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 - &flash_rdn &flash_rdy &flash_wrn>; - pinctrl-names = "default"; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; - reg = <0x20008000 0x1000>; - - power: power-controller { - compatible = "rockchip,rk3036-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3036_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC>, - <&cru HCLK_LCDC>, - <&cru SCLK_LCDC>; - pm_qos = <&qos_vio>; - #power-domain-cells = <0>; - }; - - power-domain@RK3036_PD_VPU { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3036_PD_GPU { - reg = ; - clocks = <&cru SCLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x1d8>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - acodec: acodec-ana@20030000 { - compatible = "rk3036-codec"; - reg = <0x20030000 0x4000>; - rockchip,grf = <&grf>; - clock-names = "acodec_pclk"; - clocks = <&cru PCLK_ACODEC>; - status = "disabled"; - }; - - hdmi: hdmi@20034000 { - compatible = "rockchip,rk3036-inno-hdmi"; - reg = <0x20034000 0x4000>; - interrupts = ; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ctl>; - status = "disabled"; - - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - - timer: timer@20044000 { - compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; - reg = <0x20044000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x20072000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - spi: spi@20074000 { - compatible = "rockchip,rockchip-spi"; - reg = <0x20074000 0x1000>; - interrupts = ; - clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; - clock-names = "apb-pclk","spi_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pdma: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3036-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg-pull-default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, - <1 RK_PC3 1 &pcfg_pull_default>, - <1 RK_PC4 1 &pcfg_pull_default>, - <1 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - sdio { - sdio_bus1: sdio-bus1 { - rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, - <0 RK_PB4 1 &pcfg_pull_default>, - <0 RK_PB5 1 &pcfg_pull_default>, - <0 RK_PB6 1 &pcfg_pull_default>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; - }; - - sdio_clk: sdio-clk { - rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, - <1 RK_PD1 2 &pcfg_pull_default>, - <1 RK_PD2 2 &pcfg_pull_default>, - <1 RK_PD3 2 &pcfg_pull_default>, - <1 RK_PD4 2 &pcfg_pull_default>, - <1 RK_PD5 2 &pcfg_pull_default>, - <1 RK_PD6 2 &pcfg_pull_default>, - <1 RK_PD7 2 &pcfg_pull_default>; - }; - }; - - nfc { - flash_ale: flash-ale { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, - <1 RK_PD1 1 &pcfg_pull_default>, - <1 RK_PD2 1 &pcfg_pull_default>, - <1 RK_PD3 1 &pcfg_pull_default>, - <1 RK_PD4 1 &pcfg_pull_default>, - <1 RK_PD5 1 &pcfg_pull_default>, - <1 RK_PD6 1 &pcfg_pull_default>, - <1 RK_PD7 1 &pcfg_pull_default>; - }; - - flash_cle: flash-cle { - rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; - }; - - flash_csn0: flash-csn0 { - rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; - }; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ - <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ - <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ - <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ - <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ - <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ - <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ - <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ - <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2s { - i2s_bus: i2s-bus { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>, - <1 RK_PA2 1 &pcfg_pull_default>, - <1 RK_PA3 1 &pcfg_pull_default>, - <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; - }; - }; - - hdmi { - hdmi_ctl: hdmi-ctl { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, - <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart1 */ - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - spi-pins { - spi_txd:spi-txd { - rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; - }; - - spi_rxd:spi-rxd { - rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; - }; - - spi_clk:spi-clk { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; - }; - - spi_cs0:spi-cs0 { - rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; - - }; - - spi_cs1:spi-cs1 { - rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; - - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts deleted file mode 100644 index 962b4d1291db..000000000000 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "bq Curie 2"; - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vcc_sd0: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-power { - gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - key-volume-down { - gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = ; - label = "GPIO Key Vol-"; - linux,input-type = <1>; - debounce-interval = <100>; - }; - /* VOL+ comes somehow thru the ADC */ - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - - interrupt-parent = <&gpio6>; - interrupts = ; - - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc18_cif: regulator@5 { - regulator-name = "vcc18_cif"; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-always-on; - }; - - vcc_18: regulator@8 { - regulator-name = "vcc_18"; - regulator-always-on; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-always-on; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-always-on; - }; - - vcc_tp: regulator@11 { - regulator-name = "vcc_tp"; - regulator-always-on; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-always-on; - }; - }; - }; -}; - -/* must be included after &tps gets defined */ -#include "tps65910.dtsi" - -&mmc0 { /* sdmmc */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&mmc1 { /* wifi */ - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - bus-width = <4>; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts deleted file mode 100644 index 8beecd628282..000000000000 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014 Romain Perier - */ - -/dts-v1/; -#include "rk3066a.dtsi" - -/ { - model = "MarsBoard RK3066"; - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - - aliases { - mmc0 = &mmc0; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - - interrupt-parent = <&gpio6>; - interrupts = ; - - vcc1-supply = <&vsys>; - vcc2-supply = <&vsys>; - vcc3-supply = <&vsys>; - vcc4-supply = <&vsys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - vcc7-supply = <&vsys>; - vccio-supply = <&vsys>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc18_cif: regulator@5 { - regulator-name = "vcc18_cif"; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-always-on; - }; - - vcc_18: regulator@8 { - regulator-name = "vcc_18"; - regulator-always-on; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-always-on; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-always-on; - }; - - vcc_rmii: regulator@11 { - regulator-name = "vcc_rmii"; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-always-on; - }; - }; - }; -}; - -/* must be included after &tps gets defined */ -#include "tps65910.dtsi" - -&emac { - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = ; - }; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; -}; - -&pinctrl { - lan8720a { - phy_int: phy-int { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts deleted file mode 100644 index 06790f05b395..000000000000 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Paweł Jarosz - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "Rikomagic MK808"; - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@60000000 { - reg = <0x60000000 0x40000000>; - device_type = "memory"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <2500000>; - poll-interval = <100>; - - button-recovery { - label = "recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue_led: led-0 { - label = "mk808:blue:power"; - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "default-on"; - }; - }; - - hdmi_con { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vcc_2v5: vcc-2v5 { - compatible = "regulator-fixed"; - regulator-name = "vcc_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&host_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&otg_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_wifi: sdio-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wifi_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_in_vop1 { - status = "disabled"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - non-removable; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_wifi>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&nfc { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - nand@0 { - reg = <0>; - label = "rk-nand"; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-step-size = <1024>; - nand-ecc-strength = <40>; - nand-is-boot-medium; - rockchip,boot-blks = <8>; - rockchip,boot-ecc-strength = <24>; - }; -}; - -&pinctrl { - usb-host { - host_drv: host-drv { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb-otg { - otg_drv: otg-drv { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - wifi_pwr: wifi-pwr { - rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_2v5>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vop0 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts deleted file mode 100644 index 3eee42137b6d..000000000000 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ /dev/null @@ -1,462 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "Rayeager PX2"; - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - mmc2 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio6 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - key-power { - wakeup-source; - gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ - vcc_stdby: stdby-regulator { - compatible = "regulator-fixed"; - regulator-name = "5v_stdby"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_emmc: emmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "emmc_vccq"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vsys>; - }; - - vcc_sata: sata-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_pwr>; - regulator-name = "usb_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv>; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&emac { - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; - vmmc-supply = <&vcc_emmc>; - vqmmc-supply = <&vcc_emmc>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - ak8963: ak8963@d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - tps: tps@2d { - reg = <0x2d>; - interrupt-parent = <&gpio6>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&pwr_hold>; - - vcc1-supply = <&vsys>; - vcc2-supply = <&vsys>; - vcc3-supply = <&vsys>; - vcc4-supply = <&vsys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - vcc7-supply = <&vsys>; - vccio-supply = <&vsys>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18: regulator@5 { - regulator-name = "vcc18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vccio_wl: regulator@8 { - regulator-name = "vccio_wl"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_rmii: regulator@11 { - regulator-name = "vcc_rmii"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - }; - }; -}; - -#include "tps65910.dtsi" - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - cap-mmc-highspeed; - cap-sd-highspeed; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; - vmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - ak8963 { - comp_int: comp-int { - rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - emac { - rmii_rst: rmii-rst { - rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <6 RK_PA1 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <6 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - mmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb_host { - host_drv: host-drv { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - hub_rst: hub-rst { - rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; - }; - - sata_pwr: sata-pwr { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - sata_reset: sata-reset { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_drv: otg-drv { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - tps { - pmic_int: pmic-int { - rockchip,pins = <6 RK_PA4 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - pwr_hold: pwr-hold { - rockchip,pins = <6 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_25>; - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>, <&uart3_cts>, <&uart3_rts>; - status = "okay"; -}; - -&usb_host { - pinctrl-names = "default"; - pinctrl-0 = <&hub_rst>, <&sata_reset>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi deleted file mode 100644 index de9915d946f7..000000000000 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ /dev/null @@ -1,880 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3066a"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - operating-points = - /* kHz uV */ - <1416000 1300000>, - <1200000 1175000>, - <1008000 1125000>, - <816000 1125000>, - <600000 1100000>, - <504000 1100000>, - <312000 1075000>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010c000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC0>, - <&cru DCLK_LCDC0>, - <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, - <&cru SRST_LCDC0_AHB>, - <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop0_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop0>; - }; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010e000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, - <&cru SRST_LCDC1_AHB>, - <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop1_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop1>; - }; - }; - }; - - hdmi: hdmi@10116000 { - compatible = "rockchip,rk3066-hdmi"; - reg = <0x10116000 0x2000>; - interrupts = ; - clocks = <&cru HCLK_HDMI>; - clock-names = "hclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; - power-domains = <&power RK3066_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vop0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop0_out_hdmi>; - }; - - hdmi_in_vop1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vop1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - i2s0: i2s@10118000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x10118000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 4>, <&dmac1_s 5>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@1011a000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@1011c000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011c000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 9>, <&dmac1_s 10>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <400000000>, <594000000>, - <300000000>, <150000000>, - <75000000>, <300000000>, - <150000000>, <75000000>; - }; - - timer2: timer@2000e000 { - compatible = "snps,dw-apb-timer"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3066a-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - timer0: timer@20038000 { - compatible = "snps,dw-apb-timer"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer1: timer@2003a000 { - compatible = "snps,dw-apb-timer"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - tsadc: tsadc@20060000 { - compatible = "rockchip,rk3066-tsadc"; - reg = <0x20060000 0x100>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "saradc", "apb_pclk"; - interrupts = ; - #io-channel-cells = <1>; - resets = <&cru SRST_TSADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg-pull-default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ - <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ - <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ - <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ - <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ - <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ - <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ - <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ - <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, - <2 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, - <2 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, - <3 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, - <3 RK_PA3 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, - <1 RK_PB1 1 &pcfg_pull_default>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, - <3 RK_PD4 1 &pcfg_pull_default>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, - <3 RK_PB3 1 &pcfg_pull_default>, - <3 RK_PB4 1 &pcfg_pull_default>, - <3 RK_PB5 1 &pcfg_pull_default>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, - <3 RK_PC2 1 &pcfg_pull_default>, - <3 RK_PC3 1 &pcfg_pull_default>, - <3 RK_PC4 1 &pcfg_pull_default>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, - <0 RK_PB0 1 &pcfg_pull_default>, - <0 RK_PB1 1 &pcfg_pull_default>, - <0 RK_PB2 1 &pcfg_pull_default>, - <0 RK_PB3 1 &pcfg_pull_default>, - <0 RK_PB4 1 &pcfg_pull_default>, - <0 RK_PB5 1 &pcfg_pull_default>, - <0 RK_PB6 1 &pcfg_pull_default>, - <0 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, - <0 RK_PC1 1 &pcfg_pull_default>, - <0 RK_PC2 1 &pcfg_pull_default>, - <0 RK_PC3 1 &pcfg_pull_default>, - <0 RK_PC4 1 &pcfg_pull_default>, - <0 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - i2s2 { - i2s2_bus: i2s2-bus { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, - <0 RK_PD1 1 &pcfg_pull_default>, - <0 RK_PD2 1 &pcfg_pull_default>, - <0 RK_PD3 1 &pcfg_pull_default>, - <0 RK_PD4 1 &pcfg_pull_default>, - <0 RK_PD5 1 &pcfg_pull_default>; - }; - }; - }; -}; - -&gpu { - compatible = "rockchip,rk3066-mali", "arm,mali-400"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3066_PD_GPU>; -}; - -&grf { - compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; - - usbphy: usbphy { - compatible = "rockchip,rk3066a-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@188 { - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&mmc0 { - clock-frequency = <50000000>; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - max-frequency = <50000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; -}; - -&mmc1 { - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; -}; - -&emmc { - dmas = <&dmac2 4>; - dma-names = "rx-tx"; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3066-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3066_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF1>, - <&cru ACLK_CIF1>, - <&cru HCLK_CIF1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru HCLK_HDMI>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_cif1>, - <&qos_ipp>, - <&qos_rga>; - #power-domain-cells = <0>; - }; - - power-domain@RK3066_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3066_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 0>, <&dmac1_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 2>, <&dmac1_s 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 8>, <&dmac2 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&vpu { - power-domains = <&power RK3066_PD_VIDEO>; -}; - -&wdt { - compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; -}; - -&emac { - compatible = "rockchip,rk3066-emac"; -}; diff --git a/arch/arm/boot/dts/rk3128-evb.dts b/arch/arm/boot/dts/rk3128-evb.dts deleted file mode 100644 index c38f42497cbd..000000000000 --- a/arch/arm/boot/dts/rk3128-evb.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3128.dtsi" - -/ { - model = "Rockchip RK3128 Evaluation board"; - compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c1 = &i2c1; - mmc0 = &emmc; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&emmc { - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; -}; - -&usb2phy { - status = "okay"; -}; - -&usb2phy_host { - status = "okay"; -}; - -&usb2phy_otg { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb-host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rk3128.dtsi deleted file mode 100644 index b63bd4ad3143..000000000000 --- a/arch/arm/boot/dts/rk3128.dtsi +++ /dev/null @@ -1,916 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3128"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - ; - arm,cpu-registers-not-fw-configured; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - pmu: syscon@100a0000 { - compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; - reg = <0x100a0000 0x1000>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,cortex-a7-gic"; - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - phys = <&usb2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host_ehci: usb@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x20000>; - interrupts = ; - phys = <&usb2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@101e0000 { - compatible = "generic-ohci"; - reg = <0x101e0000 0x20000>; - interrupts = ; - phys = <&usb2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - sdmmc: mmc@10214000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - dmas = <&pdma 10>; - dma-names = "rx-tx"; - fifo-depth = <256>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio: mmc@10218000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10218000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - dmas = <&pdma 11>; - dma-names = "rx-tx"; - fifo-depth = <256>; - max-frequency = <150000000>; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <256>; - max-frequency = <150000000>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - nfc: nand-controller@10500000 { - compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - pinctrl-names = "default"; - pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 - &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; - reg = <0x20008000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - usb2phy: usb2phy@17c { - compatible = "rockchip,rk3128-usb2phy"; - reg = <0x017c 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - status = "disabled"; - - usb2phy_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy_otg: otg-port { - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - timer0: timer@20044000 { - compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; - reg = <0x20044000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - timer1: timer@20044020 { - compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; - reg = <0x20044020 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - timer2: timer@20044040 { - compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; - reg = <0x20044040 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - timer3: timer@20044060 { - compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; - reg = <0x20044060 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - timer4: timer@20044080 { - compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; - reg = <0x20044080 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - timer5: timer@200440a0 { - compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; - reg = <0x200440a0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - watchdog: watchdog@2004c000 { - compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_WDT>; - status = "disabled"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050000 0x10>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050010 0x10>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050020 0x10>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050030 0x10>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@2005e000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 2>, <&pdma 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 4>, <&pdma 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 6>, <&pdma 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <20072000 0x1000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@20074000 { - compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; - reg = <0x20074000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pdma: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3128-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20088000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20088000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg-pull-default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; - }; - - emmc_cmd1: emmc-cmd1 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, - <1 RK_PD1 2 &pcfg_pull_default>, - <1 RK_PD2 2 &pcfg_pull_default>, - <1 RK_PD3 2 &pcfg_pull_default>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, - <1 RK_PD1 2 &pcfg_pull_default>, - <1 RK_PD2 2 &pcfg_pull_default>, - <1 RK_PD3 2 &pcfg_pull_default>, - <1 RK_PD4 2 &pcfg_pull_default>, - <1 RK_PD5 2 &pcfg_pull_default>, - <1 RK_PD6 2 &pcfg_pull_default>, - <1 RK_PD7 2 &pcfg_pull_default>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, - <2 RK_PB1 3 &pcfg_pull_default>, - <2 RK_PB3 3 &pcfg_pull_default>, - <2 RK_PB4 3 &pcfg_pull_default>, - <2 RK_PB5 3 &pcfg_pull_default>, - <2 RK_PB6 3 &pcfg_pull_default>, - <2 RK_PC0 3 &pcfg_pull_default>, - <2 RK_PC1 3 &pcfg_pull_default>, - <2 RK_PC2 3 &pcfg_pull_default>, - <2 RK_PC3 3 &pcfg_pull_default>, - <2 RK_PD1 3 &pcfg_pull_default>, - <2 RK_PC4 4 &pcfg_pull_default>, - <2 RK_PC5 4 &pcfg_pull_default>, - <2 RK_PC6 4 &pcfg_pull_default>, - <2 RK_PC7 4 &pcfg_pull_default>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, - <2 RK_PB4 3 &pcfg_pull_default>, - <2 RK_PB5 3 &pcfg_pull_default>, - <2 RK_PB6 3 &pcfg_pull_default>, - <2 RK_PB7 3 &pcfg_pull_default>, - <2 RK_PC0 3 &pcfg_pull_default>, - <2 RK_PC1 3 &pcfg_pull_default>, - <2 RK_PC2 3 &pcfg_pull_default>, - <2 RK_PC3 3 &pcfg_pull_default>, - <2 RK_PD1 3 &pcfg_pull_default>; - }; - }; - - hdmi { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, - <2 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - i2s { - i2s_bus: i2s-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s1_bus: i2s1-bus { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, - <1 RK_PA1 1 &pcfg_pull_none>, - <1 RK_PA2 1 &pcfg_pull_none>, - <1 RK_PA3 1 &pcfg_pull_none>, - <1 RK_PA4 1 &pcfg_pull_none>, - <1 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_dclk: lcdc-dclk { - rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; - }; - - lcdc_den: lcdc-den { - rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; - }; - - lcdc_hsync: lcdc-hsync { - rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; - }; - - lcdc_vsync: lcdc-vsync { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; - }; - - lcdc_rgb24: lcdc-rgb24 { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC2 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none>, - <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>, - <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>, - <2 RK_PD0 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - nfc { - flash_ale: flash-ale { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { - rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; - }; - - flash_cs0: flash-cs0 { - rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; - }; - - flash_dqs: flash-dqs { - rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>, - <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>, - <1 RK_PD4 1 &pcfg_pull_none>, - <1 RK_PD5 1 &pcfg_pull_none>, - <1 RK_PD6 1 &pcfg_pull_none>, - <1 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; - }; - - sdio_pwren: sdio-pwren { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, - <1 RK_PA2 2 &pcfg_pull_default>, - <1 RK_PA4 2 &pcfg_pull_default>, - <1 RK_PA5 2 &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; - }; - - sdmmc_wp: sdmmc-wp { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, - <1 RK_PC3 1 &pcfg_pull_default>, - <1 RK_PC4 1 &pcfg_pull_default>, - <1 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; - }; - - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; - }; - - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; - }; - - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; - }; - - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; - }; - - spi1_clk: spi1-clk { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; - }; - - spi1_cs0: spi1-cs0 { - rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; - }; - - spi1_tx: spi1-tx { - rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; - }; - - spi1_rx: spi1-rx { - rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; - }; - - spi1_cs1: spi1-cs1 { - rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; - }; - - spi2_clk: spi2-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; - }; - - spi2_cs0: spi2-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; - }; - - spi2_tx: spi2-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; - }; - - spi2_rx: spi2-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, - <2 RK_PD3 2 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, - <1 RK_PB2 2 &pcfg_pull_default>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts deleted file mode 100644 index 9312be362a7a..000000000000 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ /dev/null @@ -1,739 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 MundoReader S.L. - * Author: Heiko Stuebner - */ - -/dts-v1/; -#include -#include -#include -#include "rk3188.dtsi" - -/ { - model = "BQ Edison2 Quad-Core"; - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - mmc2 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vsys>; - pwms = <&pwm1 0 25000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key &usb_int>; - - key-power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - - wake_on_usb: key-wake-on-usb { - label = "Wake-on-USB"; - gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_hold>; - /* only drive the pin low until device is off */ - active-delay-ms = <3000>; - }; - - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_in_vop0: endpoint { - remote-endpoint = <&vop0_out_lvds>; - }; - }; - - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; - }; - - panel { - compatible = "innolux,ee101ia-01d", "panel-lvds"; - backlight = <&backlight>; - - /* pin LCD_CS, Nshtdn input of lvds-encoder */ - enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_cs>; - power-supply = <&vcc_lcd>; - - data-mapping = "vesa-24"; - height-mm = <163>; - width-mm = <261>; - - panel-timing { - clock-frequency = <72000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <160>; - hfront-porch = <16>; - hsync-len = <10>; - vback-porch = <23>; - vfront-porch = <12>; - vsync-len = <3>; - }; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on>; - reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; - }; - - avdd_cif: cif-avdd-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd-cif"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_avdd_en>; - startup-delay-us = <100000>; - vin-supply = <&vcc28_cif>; - }; - - vcc_5v: vcc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&v5_drv>; - vin-supply = <&vsys>; - }; - - vcc_lcd: lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-lcd"; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - startup-delay-us = <50000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv>; - startup-delay-us = <100000>; - vin-supply = <&vcc_5v>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vccq_emmc: emmc-vccq-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccq-emmc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - /* supplied from the bq24196 */ - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&cru { - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <504000000>, - <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vccq_emmc>; - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - lis3de: accelerometer@29 { - compatible = "st,lis3de"; - reg = <0x29>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - rotation-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "1"; - vdd-supply = <&vcc_io>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - tmp108@48 { - compatible = "ti,tmp108"; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&tmp_alrt>; - #thermal-sensor-cells = <0>; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - bat: battery@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - power-supplies = <&bq24196>; - }; - - act8846: pmic@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&dvs0_ctl &pmic_int>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: vcc_hdmi: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_12: REG6 { - regulator-name = "VDD_12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc18_cif: REG7 { - regulator-name = "VCC18_CIF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_tp: REG9 { - regulator-name = "VCC_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28_cif: REG12 { - regulator-name = "VCC28_CIF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; - - bq24196: charger@6b { - compatible = "ti,bq24196"; - reg = <0x6b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&charger_int &chg_ctl &otg_en>; - ti,system-minimum-microvolt = <3200000>; - monitored-battery = <&bat>; - omit-battery-class; - - usb_otg_vbus: usb-otg-vbus { }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - - ft5606: touchscreen@3e { - compatible = "edt,edt-ft5506"; - reg = <0x3e>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int &tp_rst>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - touchscreen-inverted-y; - /* hw ts resolution does not match display */ - touchscreen-size-y = <1024>; - touchscreen-size-x = <768>; - touchscreen-swapped-x-y; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - - rt5616: codec@1b { - compatible = "realtek,rt5616"; - reg = <0x1b>; - clocks = <&cru SCLK_I2S0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; - vqmmc-supply = <&vccio_wl>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio3>; - interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake>; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - dvs0_ctl: dvs0-ctl { - rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - bq24196 { - charger_int: charger-int { - rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* pin hog to make it select usb profile */ - chg_ctl: chg-ctl { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - /* low: charging, high: complete, fault: blinking */ - chg_det: chg-det { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* charging enabled when pin low and register set */ - chg_en: chg-en { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - /* bq29196 powergood (when low) signal */ - dc_det: dc-det { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* wire bq24196 otg pin to high, to enable 500mA charging */ - otg_en: otg-en { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - camera { - cif0_pdn: cif0-pdn { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif1_pdn: cif1-pdn { - rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif_avdd_en: cif-avdd-en { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - display { - lcd_cs: lcd-cs { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lcd_en: lcd-en { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ft5606 { - tp_int: tp-int { - rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - tp_rst: tp-rst { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_int: hdmi-int { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - hdmi_rst: hdmi-rst { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lis3de { - gsensor_int: gsensor-int { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - mmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tmp108 { - tmp_alrt: tmp-alrt { - rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - v5_drv: v5-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otg_drv: otg-drv { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb_int: usb-int { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rk903 { - bt_host_wake: bt-host-wake { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - bt_reg_on: bt-reg-on { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* pin hog to pull the reset high */ - bt_rst: bt-rst { - rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - bt_wake: bt-wake { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake: wifi-host-wake { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wifi_reg_on: wifi-reg-on { - rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop0 { - status = "okay"; -}; - -&vop0_out { - vop0_out_lvds: endpoint { - remote-endpoint = <&lvds_in_vop0>; - }; -}; - -&vop1 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync - &lcdc1_vsync &lcdc1_rgb24>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts deleted file mode 100644 index 0a1ae689b162..000000000000 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ /dev/null @@ -1,305 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andy Yan - */ - -/dts-v1/; -#include -#include "rk3188.dtsi" - -/ { - model = "Rockchip PX3-EVB"; - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - - aliases { - mmc0 = &mmc0; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@60000000 { - reg = <0x60000000 0x80000000>; - device_type = "memory"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - accelerometer@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_cif: LDO_REG1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_cif"; - }; - - vcc_jetta33: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_jetta33"; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - lvds_12: LDO_REG4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "lvds_12"; - }; - - lvds_25: LDO_REG5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "lvds_25"; - }; - - cif_18: LDO_REG6 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "cif_18"; - }; - - vcc_sd: LDO_REG7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - wl_18: LDO_REG8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "wl_18"; - }; - - lcd_33: SWITCH_REG { - regulator-name = "lcd_33"; - }; - }; - }; - -}; - -&i2c2 { - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; - interrupt-parent = <&gpio1>; - interrupts = ; - power-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - silead,max-fingers = <5>; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts deleted file mode 100644 index 118deacd38c4..000000000000 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3188.dtsi" - -/ { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; - - aliases { - mmc0 = &mmc0; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green_led: led-0 { - label = "rock:green:user1"; - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue_led: led-1 { - label = "rock:blue:user2"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep_led: led-2 { - label = "rock:red:power"; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&emac { - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = ; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&gpu { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - system-power-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&act8846_dvs0_ctl>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_hdmi: REG6 { - regulator-name = "VDD_HDMI"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vcc18: REG7 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_rmii: REG9 { - regulator-name = "VCC_RMII"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC18_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28: REG12 { - regulator-name = "VCC_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lan8720a { - phy_int: phy-int { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd0 { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi deleted file mode 100644 index 44b54af0bbf9..000000000000 --- a/arch/arm/boot/dts/rk3188.dtsi +++ /dev/null @@ -1,815 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE1>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE2>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE3>; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <875000>; - clock-latency-ns = <40000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <925000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <975000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1075000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1150000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1250000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010c000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010e000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - timer3: timer@2000e000 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x2000e000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; - clock-names = "pclk", "timer"; - }; - - timer6: timer@200380a0 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x200380a0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; - clock-names = "pclk", "timer"; - }; - - i2s0: i2s@1011a000 { - compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: sound@1011e000 { - compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; - reg = <0x1011e000 0x2000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1_s 8>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3188-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ - <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ - <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ - <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ - <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ - <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ - <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ - <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, - <3 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, - <1 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, - <3 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, - <1 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - lcdc1 { - lcdc1_dclk: lcdc1-dclk { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; - }; - - lcdc1_den: lcdc1-den { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; - }; - - lcdc1_hsync: lcdc1-hsync { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; - }; - - lcdc1_vsync: lcdc1-vsync { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; - }; - - lcdc1_rgb24: lcdc1-rgb24 { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, - <2 RK_PA1 1 &pcfg_pull_none>, - <2 RK_PA2 1 &pcfg_pull_none>, - <2 RK_PA3 1 &pcfg_pull_none>, - <2 RK_PA4 1 &pcfg_pull_none>, - <2 RK_PA5 1 &pcfg_pull_none>, - <2 RK_PA6 1 &pcfg_pull_none>, - <2 RK_PA7 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB1 1 &pcfg_pull_none>, - <2 RK_PB2 1 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC2 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none>, - <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>, - <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, - <1 RK_PA1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, - <1 RK_PB1 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>, - <3 RK_PA6 1 &pcfg_pull_none>, - <3 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, - <3 RK_PC2 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, - <1 RK_PC1 1 &pcfg_pull_none>, - <1 RK_PC2 1 &pcfg_pull_none>, - <1 RK_PC3 1 &pcfg_pull_none>, - <1 RK_PC4 1 &pcfg_pull_none>, - <1 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; - }; - }; - }; -}; - -&emac { - compatible = "rockchip,rk3188-emac"; -}; - -&global_timer { - interrupts = ; -}; - -&local_timer { - interrupts = ; -}; - -&gpu { - compatible = "rockchip,rk3188-mali", "arm,mali-400"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3188_PD_GPU>; -}; - -&grf { - compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; - - io_domains: io-domains { - compatible = "rockchip,rk3188-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3188-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@11c { - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - }; -}; - -&i2c0 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3188-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3188_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_ipp>, - <&qos_rga>; - #power-domain-cells = <0>; - }; - - power-domain@RK3188_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3188_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&vpu { - compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; - power-domains = <&power RK3188_PD_VIDEO>; -}; - -&wdt { - compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; -}; diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts deleted file mode 100644 index 69a5e239ed1a..000000000000 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk322x.dtsi" - -/ { - model = "Rockchip RK3228 Evaluation board"; - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc { - cap-mmc-highspeed; - mmc-ddr-1_8v; - disable-wp; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_SRC>; - assigned-clock-rates = <50000000>; - clock_in_out = "output"; - phy-supply = <&vcc_phy>; - phy-mode = "rmii"; - phy-handle = <&phy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC_PHY>; - resets = <&cru SRST_MACPHY>; - phy-is-integrated; - }; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts deleted file mode 100644 index 5c3d08e3eea3..000000000000 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "rk3229.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power_key: power-key { - label = "GPIO Key Power"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts deleted file mode 100644 index 7bfbfd11fb55..000000000000 --- a/arch/arm/boot/dts/rk3229-xms6.dts +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "rk3229.dtsi" - -/ { - model = "Mecer Xtreme Mini S6"; - compatible = "mecer,xms6", "rockchip,rk3229"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - power-led { - compatible = "gpio-leds"; - - blue_led: led-0 { - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, - <&gpio2 29 GPIO_ACTIVE_LOW>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_SRC>; - assigned-clock-rates = <50000000>; - clock_in_out = "output"; - phy-handle = <&phy>; - phy-mode = "rmii"; - phy-supply = <&vcc_phy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy-id1234.d400", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC_PHY>; - phy-is-integrated; - resets = <&cru SRST_MACPHY>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_log>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_phy { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - vqmmc-supply = <&vccio_1v8>; - status = "okay"; -}; - -&sdmmc { - cap-mmc-highspeed; - disable-wp; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy0_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart21_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi deleted file mode 100644 index c340fb30e775..000000000000 --- a/arch/arm/boot/dts/rk3229.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "rk322x.dtsi" - -/ { - compatible = "rockchip,rk3229"; - - /delete-node/ opp-table0; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1325000>; - }; - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1375000>; - }; - opp-1464000000 { - opp-hz = /bits/ 64 <1464000000>; - opp-microvolt = <1400000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi deleted file mode 100644 index ffc16d6b97e1..000000000000 --- a/arch/arm/boot/dts/rk322x.dtsi +++ /dev/null @@ -1,1295 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &spi0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - enable-method = "psci"; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip,rk3228-spdif"; - reg = <0x100d0000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&pdma 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; - reg = <0x11000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3228-io-voltage-domain"; - status = "disabled"; - }; - - power: power-controller { - compatible = "rockchip,rk3228-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3228_PD_VIO { - reg = ; - clocks = <&cru ACLK_HDCP>, - <&cru SCLK_HDCP>, - <&cru ACLK_IEP>, - <&cru HCLK_IEP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>, - <&cru SCLK_RGA>; - pm_qos = <&qos_hdcp>, - <&qos_iep>, - <&qos_rga_r>, - <&qos_rga_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VOP { - reg = ; - clocks =<&cru ACLK_VOP>, - <&cru DCLK_VOP>, - <&cru HCLK_VOP>; - pm_qos = <&qos_vop>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_RKVDEC { - reg = ; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - pm_qos = <&qos_rkvdec_r>, - <&qos_rkvdec_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - - u2phy0: usb2phy@760 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0760 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; - status = "disabled"; - - u2phy0_otg: otg-port { - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - u2phy1: usb2phy@800 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0800 0x0c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; - status = "disabled"; - - u2phy1_otg: otg-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - efuse: efuse@11040000 { - compatible = "rockchip,rk3228-efuse"; - reg = <0x11040000 0x20>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x7 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@11090000 { - compatible = "rockchip,rk3228-spi"; - reg = <0x11090000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; - status = "disabled"; - }; - - wdt: watchdog@110a0000 { - compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; - reg = <0x110a0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_CPU>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru ARMCLK>, - <&cru PLL_CPLL>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; - assigned-clock-rates = - <594000000>, <816000000>, - <500000000>, <150000000>, - <150000000>, <75000000>, - <150000000>, <150000000>, - <75000000>; - }; - - pdma: dma-controller@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <32768>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmiphy_phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@20000000 { - compatible = "rockchip,rk3228-mali", "arm,mali-400"; - reg = <0x20000000 0x10000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - power-domains = <&power RK3228_PD_GPU>; - resets = <&cru SRST_GPU_A>; - status = "disabled"; - }; - - vpu: video-codec@20020000 { - compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; - reg = <0x20020000 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3228_PD_VPU>; - }; - - vpu_mmu: iommu@20020800 { - compatible = "rockchip,iommu"; - reg = <0x20020800 0x100>; - interrupts = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VPU>; - #iommu-cells = <0>; - }; - - vdec: video-codec@20030000 { - compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; - reg = <0x20030000 0x480>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <300000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3228_PD_RKVDEC>; - }; - - vdec_mmu: iommu@20030480 { - compatible = "rockchip,iommu"; - reg = <0x20030480 0x40>, <0x200304c0 0x40>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_RKVDEC>; - #iommu-cells = <0>; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-vop"; - reg = <0x20050000 0x1ffc>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - power-domains = <&power RK3228_PD_VOP>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@20053f00 { - compatible = "rockchip,iommu"; - reg = <0x20053f00 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VOP>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@20060000 { - compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; - reg = <0x20060000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3228_PD_VIO>; - resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; - reset-names = "core", "axi", "ahb"; - }; - - iep_mmu: iommu@20070800 { - compatible = "rockchip,iommu"; - reg = <0x20070800 0x100>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - reg = <0x200a0000 0x20000>; - reg-io-width = <4>; - interrupts = ; - assigned-clocks = <&cru SCLK_HDMI_PHY>; - assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "cec"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; - resets = <&cru SRST_HDMI_P>; - reset-names = "hdmi"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - sdmmc: mmc@30000000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30000000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "disabled"; - }; - - sdio: mmc@30010000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30010000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - status = "disabled"; - }; - - emmc: mmc@30020000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - rockchip,default-sample-phase = <158>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - usb_otg: usb@30040000 { - compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ehci: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ohci: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - qos_iep: qos@31030080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030080 0x20>; - }; - - qos_rga_w: qos@31030100 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030100 0x20>; - }; - - qos_hdcp: qos@31030180 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030180 0x20>; - }; - - qos_rga_r: qos@31030200 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030200 0x20>; - }; - - qos_vpu: qos@31040000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31040000 0x20>; - }; - - qos_gpu: qos@31050000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31050000 0x20>; - }; - - qos_vop: qos@31060000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31060000 0x20>; - }; - - qos_rkvdec_r: qos@31070000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070000 0x20>; - }; - - qos_rkvdec_w: qos@31070080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070080 0x20>; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC5 2 &pcfg_pull_none>, - <2 RK_PC4 2 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, - <2 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>, - <1 RK_PA2 2 &pcfg_pull_none>, - <1 RK_PA4 2 &pcfg_pull_none>, - <1 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, - <2 RK_PD3 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts deleted file mode 100644 index 8a635c243127..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - model = "Rockchip RK3288 EVB ACT8846"; - compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; - - vcc_lcd: vcc-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - regulator-name = "vcc_lcd"; - vin-supply = <&vcc_io>; - }; - - vcc_wl: vcc-wl { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwr>; - regulator-name = "vcc_wl"; - vin-supply = <&vcc_18>; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&panel { - power-supply = <&vcc_lcd>; -}; - -&pinctrl { - lcd { - lcd_en: lcd-en { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_pwr: wifi-pwr { - rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts deleted file mode 100644 index 42384ea4ca21..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - model = "Rockchip RK3288 EVB RK808"; - compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; -}; - -&i2c0 { - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&panel { - power-supply = <&vcc_lcd>; -}; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi deleted file mode 100644 index 382d2839cf47..000000000000 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - button-menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <640000>; - }; - - button-esc { - label = "Esc"; - linux,code = ; - press-threshold-microvolt = <1000000>; - }; - - button-home { - label = "Home"; - linux,code = ; - press-threshold-microvolt = <1300000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - panel: panel { - compatible = "lg,lp079qx1-sp0v"; - backlight = <&backlight>; - enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lcd_cs>; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - key-power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_pwr>; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from - * vcc_io directly. Those boards won't be able to power cycle SD cards - * but it shouldn't hurt to toggle this pin there anyway. - */ - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&edp { - force-hpd; - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp_phy { - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_cs: lcd-cs { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on EVB board so bump up to 8ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts deleted file mode 100644 index 135e8832141f..000000000000 --- a/arch/arm/boot/dts/rk3288-firefly-beta.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288 Beta"; - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; -}; - -&ir { - gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi deleted file mode 100644 index 36efa36b7190..000000000000 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Firefly Rockchip RK3288 Core board - * Copyright (c) 2016 Randy Li - */ - -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_lan: REG9 { - regulator-name = "vcca_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vccio_wl: vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vccio_wl>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts deleted file mode 100644 index a5a0826341e6..000000000000 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ /dev/null @@ -1,392 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Firefly Rockchip RK3288 Core board - * Copyright (c) 2016 Randy Li - */ - -/dts-v1/; -#include "rk3288-firefly-reload-core.dtsi" - -/ { - model = "Firefly-RK3288-reload"; - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - wakeup-source; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; - label = "firefly:blue:power"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led_pin>; - panic-indicator; - }; - - work_led: led-1 { - gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_pin>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_5v: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - af_28: af_28-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "af_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - dvdd_1v2: af_28-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_pwr>; - regulator-name = "dvdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc_io>; - }; - - vbat_wl: wifi-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat_wl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; - status = "okay"; -}; - -&i2c0 { - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; -}; - -&i2c2 { - status = "okay"; - - codec: es8328@10 { - compatible = "everest,es8328"; - DVDD-supply = <&vcca_33>; - AVDD-supply = <&vcca_33>; - PVDD-supply = <&vcca_33>; - HPVDD-supply = <&vcca_33>; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - clock-names = "i2s_hclk", "i2s_clk"; - reg = <0x10>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - vmmc-supply = <&vbat_wl>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif_pwr: cif-pwr { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led_pin: power-led-pin { - rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led_pin: work-led-pin { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts deleted file mode 100644 index 313459dab2e4..000000000000 --- a/arch/arm/boot/dts/rk3288-firefly.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288"; - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; -}; - -&ir { - gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi deleted file mode 100644 index 3836c61cfb76..000000000000 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ /dev/null @@ -1,573 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - key-power { - wakeup-source; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - leds { - compatible = "gpio-leds"; - - work_led: led-0 { - gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_pin>; - }; - - power_led: led-1 { - gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; - label = "firefly:green:power"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led_pin>; - }; - }; - - vbat_wl: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - /* - * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vccio_wl: vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led_pin: power-led-pin { - rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led_pin: work-led-pin { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vbat_wl>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts deleted file mode 100644 index db1eb648e0e1..000000000000 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3288.dtsi" - -/ { - model = "mqmaker MiQi"; - compatible = "mqmaker,miqi", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds { - compatible = "gpio-leds"; - - work_led: led-0 { - gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "miqi:green:user"; - linux,default-trigger = "timer"; - }; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - /* - * The otg controller is the only system power source, - * so needs to always stay in device mode. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts deleted file mode 100644 index 1a5156951492..000000000000 --- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Phytec PCM-947 carrier board - * Copyright (C) 2017 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -/dts-v1/; - -#include -#include -#include "rk3288-phycore-som.dtsi" - -/ { - model = "Phytec RK3288 PCM-947"; - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - - user_buttons: user-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&user_button_pins>; - - button-0 { - label = "home"; - linux,code = ; - gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - button-1 { - label = "menu"; - linux,code = ; - gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - }; - - vcc_host0_5v: usb-host0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host0_vbus_drv>; - regulator-name = "vcc_host0_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_in_otg_out>; - }; - - vcc_host1_5v: usb-host1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_vbus_drv>; - regulator-name = "vcc_host1_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_in_otg_out>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_in_otg_out>; - }; -}; - -&gmac { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - }; - - adc@64 { - compatible = "maxim,max1037"; - reg = <0x64>; - }; - - i2c_rtc: rtc@68 { - compatible = "rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_rtc_int>; - interrupt-parent = <&gpio5>; - interrupts = <10 0>; - }; -}; - -&i2c3 { - status = "okay"; - - i2c_eeprom_cb: eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&i2c4 { - status = "okay"; - - /* PCA9533 - 4-bit LED dimmer */ - leddim: leddimmer@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led1 { - label = "red:user1"; - linux,default-trigger = "none"; - type = ; - }; - - led2 { - label = "green:user2"; - linux,default-trigger = "none"; - type = ; - }; - - led3 { - label = "blue:user3"; - linux,default-trigger = "none"; - type = ; - }; - - led4 { - label = "red:user4"; - linux,default-trigger = "none"; - type = ; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - buttons { - user_button_pins: user-button-pins { - /* button 1 */ - rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, - /* button 2 */ - <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rv4162 { - i2c_rtc_int: i2c-rtc-int { - rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on pcm-947 board so bump up to 12 mA. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - ts_irq_pin: ts-irq-pin { - rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host0_vbus_drv: host0-vbus-drv { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - host1_vbus_drv: host1-vbus-drv { - rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&vdd_io_sd>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi deleted file mode 100644 index e43887c9635f..000000000000 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ /dev/null @@ -1,439 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Phytec phyCORE-RK3288 SoM - * Copyright (C) 2017 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -#include -#include "rk3288.dtsi" - -/ { - model = "Phytec RK3288 phyCORE"; - compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; - - /* - * Set the minimum memory size here and - * let the bootloader set the real size. - */ - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x8000000>; - }; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &rk818; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_pin>; - - user_led: led-0 { - label = "green_led"; - gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "keep"; - }; - }; - - vdd_emmc_io: vdd-emmc-io { - compatible = "regulator-fixed"; - regulator-name = "vdd_emmc_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_3v3_io>; - }; - - vdd_in_otg_out: vdd-in-otg-out { - compatible = "regulator-fixed"; - regulator-name = "vdd_in_otg_out"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_misc_1v8: vdd-misc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_misc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&emmc { - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vdd_3v3_io>; - vqmmc-supply = <&vdd_emmc_io>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; - phy-handle = <&phy0>; - phy-supply = <&vdd_eth_2v5>; - phy-mode = "rgmii-id"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - tx_delay = <0x0>; - rx_delay = <0x0>; - - mdio0 { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - enet-phy-lane-no-swap; - ti,clk-output-sel = ; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; -}; - -&io_domains { - status = "okay"; - sdcard-supply = <&vdd_io_sd>; - flash0-supply = <&vdd_emmc_io>; - flash1-supply = <&vdd_misc_1v8>; - gpio1830-supply = <&vdd_3v3_io>; - gpio30-supply = <&vdd_3v3_io>; - bb-supply = <&vdd_3v3_io>; - dvp-supply = <&vdd_3v3_io>; - lcdc-supply = <&vdd_3v3_io>; - wifi-supply = <&vdd_3v3_io>; - audio-supply = <&vdd_3v3_io>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vdd_sys>; - vcc2-supply = <&vdd_sys>; - vcc3-supply = <&vdd_sys>; - vcc4-supply = <&vdd_sys>; - boost-supply = <&vdd_in_otg_out>; - vcc6-supply = <&vdd_sys>; - vcc7-supply = <&vdd_misc_1v8>; - vcc8-supply = <&vdd_misc_1v8>; - vcc9-supply = <&vdd_3v3_io>; - vddio-supply = <&vdd_3v3_io>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_3v3_io: DCDC_REG4 { - regulator-name = "vdd_3v3_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_sys: DCDC_BOOST { - regulator-name = "vdd_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <5000000>; - }; - }; - - /* vcc9 */ - vdd_sd: SWITCH_REG { - regulator-name = "vdd_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* vcc6 */ - vdd_eth_2v5: LDO_REG2 { - regulator-name = "vdd_eth_2v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2500000>; - }; - }; - - /* vcc7 */ - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - /* vcc8 */ - vdd_1v8_lcd_ldo: LDO_REG4 { - regulator-name = "vdd_1v8_lcd_ldo"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* vcc8 */ - vdd_1v0_lcd: LDO_REG6 { - regulator-name = "vdd_1v0_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - /* vcc7 */ - vdd_1v8_ldo: LDO_REG7 { - regulator-name = "vdd_1v8_ldo"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* vcc9 */ - vdd_io_sd: LDO_REG9 { - regulator-name = "vdd_io_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - /* M24C32-D */ - i2c_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - vdd_cpu: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1430000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vdd_sys>; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>, - <3 RK_PA1 2 &pcfg_pull_none_12ma>, - <3 RK_PA2 2 &pcfg_pull_none_12ma>, - <3 RK_PA3 2 &pcfg_pull_none_12ma>, - <3 RK_PA4 2 &pcfg_pull_none_12ma>, - <3 RK_PA5 2 &pcfg_pull_none_12ma>, - <3 RK_PA6 2 &pcfg_pull_none_12ma>, - <3 RK_PA7 2 &pcfg_pull_none_12ma>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - leds { - user_led_pin: user-led-pin { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* Pin for switching state between sleep and non-sleep state */ - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vdd_1v8_ldo>; -}; - -&spi2 { - status = "okay"; - - serial_flash: flash@0 { - compatible = "micron,n25q128a13", "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - }; -}; - -&tsadc { - status = "okay"; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts deleted file mode 100644 index fd90f3b8fc32..000000000000 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ /dev/null @@ -1,513 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 Andy Yan - */ - -/dts-v1/; -#include -#include "rk3288.dtsi" - -/ { - model = "PopMetal-RK3288"; - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - key-power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc18_dvp: vcc18-dvp-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc18-dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lan: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - ldo5: LDO_REG5 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ldo5"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_33: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vccio_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - ak8963: ak8963@d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio8>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - vdd-supply = <&vcc_io>; - vid-supply = <&vcc_io>; - }; - - l3g4200d: l3g4200d@69 { - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x69>; - vdd-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio8>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - ak8963 { - comp_int: comp-int { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts deleted file mode 100644 index 633e5a032463..000000000000 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ /dev/null @@ -1,400 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2015 Heiko Stuebner - */ - -/dts-v1/; -#include -#include -#include "rk3288.dtsi" - -/ { - model = "Netxeon R89"; - compatible = "netxeon,r89", "rockchip,rk3288"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - key-power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_otg: vcc-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdmmc: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "sys-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: pmic@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "VDD_CPU"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: pmic@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "VDD_GPU"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - }; - - act8846: pmic@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_wl: REG7 { - regulator-name = "VCC_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_lan: REG9 { - regulator-name = "VCC_LAN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sdmmc>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts deleted file mode 100644 index b19593021713..000000000000 --- a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -/dts-v1/; -#include "rk3288.dtsi" -#include -#include "rk3288-vmarc-som.dtsi" - -/ { - model = "Radxa ROCK Pi N8"; - compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", - "rockchip,rk3288"; -}; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi deleted file mode 100644 index 76363b8afcb9..000000000000 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <150>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - mmc-pwrseq = <&emmc_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vccio_pmu>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - rx_delay = <0x10>; - tx_delay = <0x30>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - system-power-controller; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: vccio_codec: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcc_io>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vccio_pmu>; - gpio30-supply = <&vccio_pmu>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts deleted file mode 100644 index 13cfdaa95cc7..000000000000 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include -#include "rk3288-rock2-som.dtsi" - -/ { - model = "Radxa Rock 2 Square"; - compatible = "radxa,rock2-square", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - heartbeat_led: led-0 { - gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; - label = "rock2:green:state1"; - linux,default-trigger = "heartbeat"; - }; - - mmc_led: led-1 { - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; - label = "rock2:blue:state2"; - linux,default-trigger = "mmc0"; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - sata_pwr: sata-prw-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_pwr_en>; - /* Always turn on the 5V sata power connector */ - regulator-always-on; - regulator-name = "sata_pwr"; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - sound-i2s { - compatible = "rockchip,rk3288-hdmi-analog"; - pinctrl-names = "default"; - pinctrl-0 = <&phone_ctl>, <&hp_det>; - rockchip,audio-codec = <&es8388>; - rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; - rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; - rockchip,i2s-controller = <&i2s>; - rockchip,model = "I2S"; - rockchip,routing = "Analog", "LOUT2", - "Analog", "ROUT2"; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - vcc_usb_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - }; -}; - -&i2c2 { - status = "okay"; - - es8388: es8388@10 { - compatible = "everest,es8388", "everest,es8328"; - reg = <0x10>; - AVDD-supply = <&vccio_codec>; - DVDD-supply = <&vccio_codec>; - HPVDD-supply = <&vccio_codec>; - PVDD-supply = <&vccio_codec>; - clocks = <&cru SCLK_I2S0_OUT>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - phone_ctl: phone-ctl { - rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sata { - sata_pwr_en: sata-pwr-en { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usbphy1 { - vbus-supply = <&vcc_usb_host>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts deleted file mode 100644 index 970e13859198..000000000000 --- a/arch/arm/boot/dts/rk3288-tinker-s.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "rk3288-tinker.dtsi" - -/ { - model = "Rockchip RK3288 Asus Tinker Board S"; - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - max-frequency = <150000000>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; -}; diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts deleted file mode 100644 index 1e43527aa196..000000000000 --- a/arch/arm/boot/dts/rk3288-tinker.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "rk3288-tinker.dtsi" - -/ { - model = "Rockchip RK3288 Asus Tinker Board"; - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; -}; diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi deleted file mode 100644 index 09618bb7d872..000000000000 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ /dev/null @@ -1,546 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -#include "rk3288.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - button { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - act_led: led-0 { - gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - heartbeat_led: led-1 { - gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - pwr_led: led-2 { - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 RK808_CLKOUT1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>, - <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,tinker-codec"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&cpu_opp_table { - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1400000>; - }; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vcc33_lan>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, - <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd_arm"; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc18_ldo1: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_ldo1"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_mipi: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_mipi"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_codec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc33_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s { - #sound-dai-cells = <0>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - dvs_1: dvs-1 { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pwr_3g: pwr-3g { - rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc18_ldo1>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - broken-cd; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <50000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi deleted file mode 100644 index 51208d161d65..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron (and derivatives) fragment for the max98090 audio - * codec and analog headphone jack. - * - * Copyright 2016 Google, Inc - */ - -/ { - sound { - compatible = "rockchip,rockchip-audio-max98090"; - pinctrl-names = "default"; - pinctrl-0 = <&mic_det>, <&hp_det>; - rockchip,model = "VEYRON-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&max98090>; - rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>; - rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>; - rockchip,headset-codec = <&headsetcodec>; - rockchip,hdmi-codec = <&hdmi>; - }; -}; - -&i2c2 { - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio6>; - interrupts = ; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S0_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&int_codec>; - }; -}; - -&i2c4 { - headsetcodec: ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&ts3a227e_int_l>; - ti,micbias = <7>; /* MICBIAS = 2.8V */ - }; -}; - -&i2s { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcc18_codec>; -}; - -&rk808 { - vcc10-supply = <&vcc33_sys>; - - regulators { - vcc18_codec: LDO_REG6 { - regulator-name = "vcc18_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&pinctrl { - codec { - hp_det: hp-det { - rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* - * HACK: We're going to _pull down_ this _active low_ interrupt - * so that it never fires. We don't need this interrupt because - * we've got a ts3a227e chip but the driver requires it. - */ - int_codec: int-codec { - rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - mic_det: mic-det { - rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headset { - ts3a227e_int_l: ts3a227e-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts deleted file mode 100644 index aa33d09184ad..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-brain.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Brain Rev 0 board device tree source - * - * Copyright 2014 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" - -/ { - model = "Google Brain"; - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - - vcc33_sys: vcc33-sys { - vin-supply = <&vcc_5v>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - /* This is gated by vcc_18 too */ - }; - - /* This turns on vbus for host2 and otg (dwc2) */ - vcc5_host2: vcc5-host2-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - >; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-host { - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_hdmi: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc18_hdmi"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi deleted file mode 100644 index f9dde0eef527..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth - * chip. - * - * Copyright 2019 Google, Inc - */ - -&uart0 { - bluetooth { - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>, - <&bt_dev_wake>; - - compatible = "brcm,bcm43540-bt"; - host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - brcm,bt-pcm-int-params = [01 02 00 01 01]; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi deleted file mode 100644 index 700bb548d6b2..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) board device tree source - * Chromebook specific parts - * - * Copyright 2015 Google, Inc - */ - -#include -#include -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-analog-audio.dtsi" -#include "rk3288-veyron-edp.dtsi" -#include "rk3288-veyron-sdmmc.dtsi" - -/ { - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - }; - - gpio-charger { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ac_present_ap>; - }; - - lid_switch: lid-switch { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&ap_lid_int_l>; - - switch-lid { - label = "Lid"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - linux,input-type = ; - debounce-interval = <1>; - }; - }; - - /* A non-regulated voltage from power supply or battery */ - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc33_sys: vcc33-sys { - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - vin-supply = <&vccsys>; - }; - - /* This turns on vbus for host1 (dwc2) */ - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_pwren_h>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&rk808 { - vcc11-supply = <&vcc_5v>; - - regulators { - vcc33_ccd: LDO_REG8 { - regulator-name = "vcc33_ccd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - google,cros-ec-spi-pre-delay = <30>; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&ec_int>; - spi-max-frequency = <3000000>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c4 { - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&pinctrl { - buttons { - ap_lid_int_l: ap-lid-int-l { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - charger { - ac_present_ap: ac-present-ap { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - cros-ec { - ec_int: ec-int { - rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - suspend { - suspend_l_wake: suspend-l-wake { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - suspend_l_sleep: suspend-l-sleep { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - trackpad { - trackpad_int: trackpad-int { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-host { - host1_pwr_en: host1-pwr-en { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbotg_pwren_h: usbotg-pwren-h { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi deleted file mode 100644 index 32c0f10765dd..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) fragment for the edp displays - * - * Copyright 2019 Google LLC - */ - -/ { - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 0>; - post-pwm-on-delay-ms = <10>; - pwm-off-delay-ms = <10>; - power-supply = <&backlight_regulator>; - }; - - panel: panel { - compatible = "innolux,n116bge"; - status = "okay"; - power-supply = <&panel_regulator>; - backlight = <&backlight>; - - panel-timing { - clock-frequency = <74250000>; - hactive = <1366>; - hfront-porch = <136>; - hback-porch = <60>; - hsync-len = <30>; - hsync-active = <0>; - vactive = <768>; - vfront-porch = <8>; - vback-porch = <12>; - vsync-len = <12>; - vsync-active = <0>; - }; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; -}; - -&edp { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp_phy { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl_en: bl-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rk3288-veyron-fievel.dts deleted file mode 100644 index 309b122b4d0d..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-fievel.dts +++ /dev/null @@ -1,528 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Fievel Rev 0+ board device tree source - * - * Copyright 2016 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-analog-audio.dtsi" - -/ { - model = "Google Fievel"; - compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7", - "google,veyron-fievel-rev6", "google,veyron-fievel-rev5", - "google,veyron-fievel-rev4", "google,veyron-fievel-rev3", - "google,veyron-fievel-rev2", "google,veyron-fievel-rev1", - "google,veyron-fievel-rev0", "google,veyron-fievel", - "google,veyron", "rockchip,rk3288"; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - /* - * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys, - * enabled by vcc_18 - */ - vcc33_io: vcc33-io { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_io"; - }; - - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hub_usb1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5_host2: vcc5-host2-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hub_usb2_pwr_en>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_pwr_en>; - regulator-name = "vcc5_otg"; - regulator-always-on; - regulator-boot-on; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; -}; - -&gmac { - status = "okay"; - - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-supply = <&vcc33_lan>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - rx_delay = <0x10>; - tx_delay = <0x30>; - - /* - * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low) - * with a 30ms settling time. - */ - snps,reset-gpio = <&gpio4 RK_PB0 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - wakeup-source; - - mdio0 { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&rk808 { - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - vcc6-supply = <&vcc33_sys>; - vcc10-supply = <&vcc33_sys>; - vcc11-supply = <&vcc_5v>; - vcc12-supply = <&vcc33_sys>; - - regulators { - /delete-node/ LDO_REG1; - - /* - * According to the schematic, vcc18_lcdt is for - * HDMI_AVDD_1V8 - */ - vcc18_lcdt: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd18_lcdt"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* - * This is not a pwren anymore, but the real power supply, - * vdd10_lcd for HDMI_AVDD_1V0 - */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* for usb camera */ - vcc33_ccd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_ccd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_lan: SWITCH_REG2 { - regulator-name = "vcc33_lan"; - }; - }; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - - btmrvl: btmrvl@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = ; - marvell,wakeup-pin = /bits/ 16 <13>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - }; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "HUB_USB1_nFALUT", - "PHY_PMEB", - - "PHY_INT", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "", - "USB_OTG_POWER_EN", - "AP_WARM_RESET_H", - "USB_OTG_nFALUT", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "DEVMODE_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "", - "TOUCH_INT", - "TOUCH_RST", - - "I2C3_SCL_TP", - "I2C3_SDA_TP"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "VCC5V_GOOD_H", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO", - "", - "", - "", - "", - "", - - "PHY_TXD2", - "PHY_TXD3", - "MAC_RXD2", - "MAC_RXD3", - "PHY_TXD0", - "PHY_TXD1", - "MAC_RXD0", - "MAC_RXD1"; -}; - -&gpio4 { - gpio-line-names = "MAC_MDC", - "MAC_RXDV", - "MAC_RXER", - "MAC_CLK", - "PHY_TXEN", - "MAC_MDIO", - "MAC_RXCLK", - "", - - "PHY_RST", - "PHY_TXCLK", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS_L", - "UART0_RTS_L", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "USB_OTG_CTL1", - "HUB_USB2_CTL1", - "HUB_USB2_PWR_EN", - "HUB_USB_ILIM_SEL", - - "USB_OTG_STATUS_L", - "HUB_USB1_CTL1", - "HUB_USB1_PWR_EN", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "HUB_USB2_nFALUT", - "USB_OTG_ILIM_SEL"; -}; - -&gpio7 { - gpio-line-names = "LCD_BL_PWM", - "PWM_LOG", - "BL_EN", - "PWR_LED1", - "TPM_INT_H", - "SPK_ON", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "", - - "CPU_NMI", - "DVSOK", - "", - "EDP_HPD", - "DVS1", - "", - "LCD_EN", - "DVS2", - - "HDMI_CEC", - "I2C4_SDA", - "I2C4_SCL", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* For usb bc1.2 */ - &usb_otg_ilim_sel - &usb_usb_ilim_sel - - /* Wake only */ - &bt_dev_wake_awake - &pwr_led1_on - >; - - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* For usb bc1.2 */ - &usb_otg_ilim_sel - &usb_usb_ilim_sel - - /* Sleep only */ - &bt_dev_wake_sleep - &pwr_led1_blink - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_int: phy-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - pwr_led1_on: pwr-led1-on { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pwr_led1_blink: pwr-led1-blink { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-bc12 { - usb_otg_ilim_sel: usb-otg-ilim-sel { - rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - usb_usb_ilim_sel: usb-usb-ilim-sel { - rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - usb-host { - hub_usb1_pwr_en: hub_usb1_pwr_en { - rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hub_usb2_pwr_en: hub_usb2_pwr_en { - rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb_otg_pwr_en: usb_otg_pwr_en { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts deleted file mode 100644 index 4a148cf1defc..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ /dev/null @@ -1,334 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Jaq Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; - -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jaq"; - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; -}; - -&backlight { - /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ - brightness-levels = <8 255>; - num-interpolated-steps = <247>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-name = "mic_vcc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - - btmrvl: btmrvl@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = ; - marvell,wakeup-pin = /bits/ 16 <13>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFALUT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", /* Maybe missing from mighty? */ - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "ALS_INT", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVSOK", - "SDMMC_WP", /* mighty only */ - "EDP_HPD", - "DVS1", - "nFALUT1", /* nFAULT1 on jaq */ - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts deleted file mode 100644 index 2c916c50dda5..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ /dev/null @@ -1,494 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Jerry Rev 3+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jerry"; - compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", - "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", - "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", - "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-name = "mic_vcc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - - mwifiex: wifi@1 { - compatible = "marvell,sd8897"; - reg = <1>; - - marvell,caldata-txpwrlimit-2g = /bits/ 8 < -0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09>; - - marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 < -0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 -0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 -0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 -0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 -0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 -0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30 -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 -0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 -0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c -0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 -0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 -0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 -0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c -0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a -0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 -0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 -0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c -0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a -0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 -0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 -0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a -0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 -0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; - - marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 < -0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 -0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 -0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 -0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 -0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 -0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70 -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 -0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 -0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c -0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 -0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 -0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 -0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c -0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a -0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 -0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 -0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c -0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a -0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 -0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 -0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a -0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 -0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 -0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 -0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 -0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 -0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 -0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; - - marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 < -0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 -0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 -0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 -0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 -0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 -0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1 -0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 -0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 -0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 -0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b -0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 -0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 -0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 -0x1a 0x05 0x1b 0x05>; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFAULT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVSOK", - "", - "EDP_HPD", - "DVS1", - "nFAULT1", - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&i2c4 { - status = "okay"; - - /* - * Trackpad pin control is shared between Elan and Synaptics devices - * so we have to pull it up to the bus level. - */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer &trackpad_int>; - - trackpad@15 { - /* - * Remove the inherited pinctrl settings to avoid clashing - * with bus-wide ones. - */ - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - }; - - trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&gpio7>; - interrupts = ; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts deleted file mode 100644 index ffd1121d19be..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ /dev/null @@ -1,453 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Mickey Rev 0 board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" - -/ { - model = "Google Mickey"; - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - - vcc_5v: vcc-5v { - vin-supply = <&vcc33_sys>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - }; - - sound { - compatible = "rockchip,rockchip-audio-max98090"; - rockchip,model = "VEYRON-HDMI"; - rockchip,hdmi-codec = <&hdmi>; - rockchip,i2s-controller = <&i2s>; - }; -}; - -&cpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - cpu_alert_almost_warm: cpu_alert_almost_warm { - temperature = <63000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_warm: cpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_almost_hot: cpu_alert_almost_hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hot: cpu_alert_hot { - temperature = <82000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hotter: cpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_very_hot: cpu_alert_very_hot { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * After 1st level, throttle the CPU down to as low as 1.4 GHz - * and don't let the GPU go faster than 400 MHz. - */ - cpu_warm_limit_cpu { - trip = <&cpu_alert_warm>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, - <&cpu1 THERMAL_NO_LIMIT 4>, - <&cpu2 THERMAL_NO_LIMIT 4>, - <&cpu3 THERMAL_NO_LIMIT 4>; - }; - cpu_warm_limit_gpu { - trip = <&cpu_alert_warm>; - cooling-device = <&gpu 1 1>; - }; - - /* - * Add some discrete steps to help throttling system deal - * with the fact that there are two passive cooling devices: - * the CPU and the GPU. - * - * - 1.2 GHz - 1.0 GHz (almost hot) - * - 800 MHz (hot) - * - 800 MHz - 696 MHz (hotter) - * - 696 MHz - min (very hot) - * - * Note: - * - 800 MHz appears to be a "sweet spot" for me. I can run - * some pretty serious workload here and be happy. - * - After 696 MHz we stop lowering voltage, so throttling - * past there is less effective. - */ - cpu_almost_hot_limit_cpu { - trip = <&cpu_alert_almost_hot>; - cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, - <&cpu3 5 6>; - }; - cpu_hot_limit_cpu { - trip = <&cpu_alert_hot>; - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, - <&cpu3 7 7>; - }; - cpu_hotter_limit_cpu { - trip = <&cpu_alert_hotter>; - cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, - <&cpu3 7 8>; - }; - cpu_very_hot_limit_cpu { - trip = <&cpu_alert_very_hot>; - cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, - <&cpu1 8 THERMAL_NO_LIMIT>, - <&cpu2 8 THERMAL_NO_LIMIT>, - <&cpu3 8 THERMAL_NO_LIMIT>; - }; - - /* At very hot, don't let GPU go over 300 MHz */ - cpu_very_hot_limit_gpu { - trip = <&cpu_alert_very_hot>; - cooling-device = <&gpu 2 2>; - }; - }; -}; - -&gpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - gpu_alert_warmish: gpu_alert_warmish { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_alert_warm: gpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_alert_hotter: gpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_alert_very_very_hot: gpu_alert_very_very_hot { - temperature = <86000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* After 1st level throttle the GPU down to as low as 400 MHz */ - gpu_warmish_limit_gpu { - trip = <&gpu_alert_warmish>; - cooling-device = <&gpu THERMAL_NO_LIMIT 1>; - }; - - /* - * Slightly after we throttle the GPU, we'll also make sure that - * the CPU can't go faster than 1.4 GHz. Note that we won't - * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll - * let the CPU do the rest itself. - */ - gpu_warm_limit_cpu { - trip = <&gpu_alert_warm>; - cooling-device = <&cpu0 4 4>, - <&cpu1 4 4>, - <&cpu2 4 4>, - <&cpu3 4 4>; - }; - - /* When hot, GPU goes down to 300 MHz */ - gpu_hotter_limit_gpu { - trip = <&gpu_alert_hotter>; - cooling-device = <&gpu 2 2>; - }; - - /* When really hot, don't let GPU go _above_ 300 MHz */ - gpu_very_very_hot_limit_gpu { - trip = <&gpu_alert_very_very_hot>; - cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&i2s { - status = "okay"; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - /delete-property/ vcc12-supply; - - vcc11-supply = <&vcc33_sys>; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - /delete-node/ LDO_REG7; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "", - "", - "", - "PMIC_INT_L", - "POWER_BUTTON_L", - "", - "", - - "", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OT_RESET", - "", - "", - "AP_WARM_RESET_H", - "", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "", - "nFALUT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS_L", - "UART0_RTS_L", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio7 { - gpio-line-names = "", - "PWM_LOG", - "", - "", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "", - - "CPU_NMI", - "DVSOK", - "HDMI_WAKE", - "POWER_HDMI_ON", - "DVS1", - "", - "", - "DVS2", - - "HDMI_CEC", - "", - "", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - >; - - hdmi { - power_hdmi_on: power-hdmi-on { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host1 { - status = "disabled"; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&power_hdmi_on>; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts deleted file mode 100644 index fa695a88f236..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Mighty Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; - -#include "rk3288-veyron-jaq.dts" - -/ { - model = "Google Mighty"; - compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4", - "google,veyron-mighty-rev3", "google,veyron-mighty-rev2", - "google,veyron-mighty-rev1", "google,veyron-mighty", - "google,veyron", "rockchip,rk3288"; -}; - -&sdmmc { - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin - &sdmmc_wp_pin &sdmmc_bus4>; - wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; - - /delete-property/ disable-wp; -}; - -&pinctrl { - sdmmc { - sdmmc_wp_pin: sdmmc-wp-pin { - rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts deleted file mode 100644 index dcdcc55c4098..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Minnie Rev 0+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" - -/ { - model = "Google Minnie"; - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - - volume_buttons: volume-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&volum_down_l &volum_up_l>; - - key-volum-down { - label = "Volum_down"; - gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - - key-volum-up { - label = "Volum_up"; - gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - }; -}; - -&backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <3 255>; - num-interpolated-steps = <252>; -}; - -&i2c_tunnel { - battery: bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_touch>; - vccio-supply = <&vcc33_touch>; - }; -}; - -&panel { - compatible = "auo,b101ean01"; - - /delete-node/ panel-timing; - - panel-timing { - clock-frequency = <66666667>; - hactive = <1280>; - hfront-porch = <18>; - hback-porch = <21>; - hsync-len = <32>; - vactive = <800>; - vfront-porch = <4>; - vback-porch = <8>; - vsync-len = <18>; - }; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - regulators { - vcc33_touch: LDO_REG2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v_touch: SWITCH_REG2 { - regulator-name = "vcc5v_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFALUT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "PROCHOT#", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN", - "TOUCH_INT", - "TOUCH_RST", - - "I2C3_SCL_TP", - "I2C3_SDA_TP"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "dev_wake", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "Volum_Up#", - "Volum_Down#", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVS_OK", - "SDMMC_WP", - "EDP_HPD", - "DVS1", - "nFALUT1", - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - volum_down_l: volum-down-l { - rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - volum_up_l: volum-up-l { - rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - prochot { - gpio_prochot: gpio-prochot { - rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts deleted file mode 100644 index e2a4e6232eb5..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Pinky Rev 2 board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Pinky"; - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - - /delete-node/backlight-regulator; - /delete-node/panel-regulator; - /delete-node/emmc-pwrseq; - /delete-node/vcc18-lcd; -}; - -&backlight { - /delete-property/power-supply; -}; - -&emmc { - /* - * Use a pullup instead of a drive since the output is 3.3V and - * really should be 1.8V (oops). The external pulldown will help - * bring the voltage down if we only drive with a pullup here. - * Therefore disable the powerseq (and actual reset) for pinky. - */ - /delete-property/mmc-pwrseq; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&lid_switch { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - - key-power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - }; -}; - -/* Touchpad connector */ -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -&panel { - power-supply = <&vcc33_lcd>; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - /delete-node/ lcd; - - backlight { - /delete-node/ bl_pwr_en; - }; - - buttons { - pwr_key_h: pwr-key-h { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_wp_pin: sdmmc-wp-pin { - rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&rk808 { - regulators { - vcc18_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin - &sdmmc_wp_pin &sdmmc_bus4>; - wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>; -}; - -&tsadc { - /* Some connection is flaky making the tsadc hang the system */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi deleted file mode 100644 index 8b58773e592e..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) fragment for sdmmc cards - * - * Copyright 2015 Google, Inc - */ - -/ { - aliases { - mmc1 = &sdmmc; - }; -}; - -&io_domains { - sdcard-supply = <&vccio_sd>; -}; - -&pinctrl { - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * Builtin CD line is hooked to ground to prevent JTAG at boot - * (and also to get the voltage rail correct). - * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't - * think there's a card inserted - */ - sdmmc_cd_disabled: sdmmc-cd-disabled { - rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD */ - sdmmc_cd_pin: sdmmc-cd-pin { - rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rk808 { - vcc9-supply = <&vcc_5v>; - - regulators { - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_sd: LDO_REG5 { - regulator-name = "vcc33_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - status = "okay"; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; - rockchip,default-sample-phase = <90>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts deleted file mode 100644 index 4a3ea934d03e..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Speedy Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Speedy"; - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&cpu_crit { - temperature = <90000>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&gpu_alert0 { - temperature = <80000>; -}; - -&gpu_crit { - temperature = <90000>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFALUT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "PWRLIMIT#_CPU", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "ALS_INT", /* not connected */ - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVS_OK", - "", - "EDP_HOTPLUG", - "DVS1", - "nFALUT1", - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts deleted file mode 100644 index 52a84cbe7a90..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Tiger Rev 0+ board device tree source - * - * Copyright 2016 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-fievel.dts" -#include "rk3288-veyron-edp.dtsi" - -/ { - model = "Google Tiger"; - compatible = "google,veyron-tiger-rev8", "google,veyron-tiger-rev7", - "google,veyron-tiger-rev6", "google,veyron-tiger-rev5", - "google,veyron-tiger-rev4", "google,veyron-tiger-rev3", - "google,veyron-tiger-rev2", "google,veyron-tiger-rev1", - "google,veyron-tiger-rev0", "google,veyron-tiger", - "google,veyron", "rockchip,rk3288"; - - /delete-node/ vcc18-lcd; -}; - -&backlight { - /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <3 255>; - num-interpolated-steps = <252>; -}; - -&backlight_regulator { - vin-supply = <&vccsys>; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_io>; - vccio-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&panel { - compatible = "auo,b101ean01"; - - /delete-node/ panel-timing; - - panel-timing { - clock-frequency = <66666667>; - hactive = <1280>; - hfront-porch = <18>; - hback-porch = <21>; - hsync-len = <32>; - vactive = <800>; - vfront-porch = <4>; - vback-porch = <8>; - vsync-len = <18>; - }; -}; - -&pinctrl { - lcd { - /delete-node/ avdd-1v8-disp-en; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi deleted file mode 100644 index d838bf0d5d9a..000000000000 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ /dev/null @@ -1,597 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2015 Google, Inc - */ - -#include -#include -#include "rk3288.dtsi" - -/ { - aliases { - mmc0 = &emmc; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - /* - * The default coreboot on veyron devices ignores memory@0 nodes - * and would instead create another memory node. - */ - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - - power_button: power-button { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - - key-power { - label = "Power"; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_warm_reset_h>; - priority = <200>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 RK808_CLKOUT1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * Depending on the actual card populated GPIO4 D4 - * correspond to one of these signals on the module: - * - * D4: - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - vcc_5v: vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc33_sys: vcc33-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc33_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_5v>; - }; - - vdd_logic: vdd-logic { - compatible = "pwm-regulator"; - regulator-name = "vdd_logic"; - - pwms = <&pwm1 0 1994 0>; - pwm-supply = <&vcc33_sys>; - - pwm-dutycycle-range = <0x7b 0>; - pwm-dutycycle-unit = <0x94>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <4000>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&cpu_crit { - temperature = <100000>; -}; - -/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ -&cpu_opp_table { - /delete-node/ opp-312000000; - - opp-1512000000 { - opp-microvolt = <1250000>; - }; - opp-1608000000 { - opp-microvolt = <1300000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1400000>; - }; -}; - -&emmc { - status = "okay"; - - bus-width = <8>; - cap-mmc-highspeed; - rockchip,default-sample-phase = <158>; - disable-wp; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gpu_alert0 { - temperature = <72500>; -}; - -&gpu_crit { - temperature = <100000>; -}; - -&hdmi { - pinctrl-names = "default", "unwedge"; - pinctrl-0 = <&hdmi_ddc>; - pinctrl-1 = <&hdmi_ddc_unwedge>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc33_sys>; - vcc2-supply = <&vcc33_sys>; - vcc3-supply = <&vcc33_sys>; - vcc4-supply = <&vcc33_sys>; - vcc6-supply = <&vcc_5v>; - vcc7-supply = <&vcc33_sys>; - vcc8-supply = <&vcc33_sys>; - vcc12-supply = <&vcc_18>; - vddio-supply = <&vcc33_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc135_ddr: DCDC_REG3 { - regulator-name = "vcc135_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* - * vcc_18 has several aliases. (vcc18_flashio and - * vcc18_wl). We'll add those aliases here just to - * make it easier to follow the schematic. The signals - * are actually hooked together and only separated for - * power measurement purposes). - */ - vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* - * Note that both vcc33_io and vcc33_pmuio are always - * powered together. To simplify the logic in the dts - * we just refer to vcc33_io every time something is - * powered from vcc33_pmuio. In fact, on later boards - * (such as danger) they're the same net. - */ - vcc33_io: LDO_REG1 { - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd10_lcd_pwren_h: LDO_REG7 { - regulator-name = "vdd10_lcd_pwren_h"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_lcd: SWITCH_REG1 { - regulator-name = "vcc33_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 40ns measured */ - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&i2c2 { - status = "okay"; - - /* 100kHz since 4.7k resistors don't rise fast enough */ - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <50>; /* 10ns measured */ - i2c-scl-rising-time-ns = <800>; /* 600ns measured */ -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 11ns measured */ - i2c-scl-rising-time-ns = <300>; /* 225ns measured */ -}; - -&io_domains { - status = "okay"; - - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - wifi-supply = <&vcc18_wl>; -}; - -&pwm1 { - status = "okay"; -}; - -&sdio0 { - status = "okay"; - - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc33_sys>; - vqmmc-supply = <&vcc18_wl>; -}; - -&spi2 { - status = "okay"; - - rx-sample-delay-ns = <12>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-temp = <125000>; -}; - -&uart0 { - status = "okay"; - - /* Pins don't include flow control by default; add that in */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; - - needs-reset-on-resume; -}; - -&usb_host1 { - status = "okay"; - snps,need-phy-for-wake; -}; - -&usb_otg { - status = "okay"; - - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&usbphy0>; - dr_mode = "host"; - snps,need-phy-for-wake; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - buttons { - pwr_key_l: pwr-key-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - reboot { - ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - recovery-switch { - rec_mode_l: rec-mode-l { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio0 { - wifi_enable_h: wifienable-h { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* NOTE: mislabelled on schematic; should be bt_enable_h */ - bt_enable_l: bt-enable-l { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake: bt-host-wake { - rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run sdio0 at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, - <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, - <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, - <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * These pins are only present on very new veyron boards; on - * older boards bt_dev_wake is simply always high. Note that - * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt - * to map this pin everywhere - */ - bt_dev_wake_sleep: bt-dev-wake-sleep { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; - }; - - bt_dev_wake_awake: bt-dev-wake-awake { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; - }; - - bt_dev_wake: bt-dev-wake { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tpm { - tpm_int_h: tpm-int-h { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - write-protect { - fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi deleted file mode 100644 index 793951655b73..000000000000 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include -#include - -/ { - compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; - - vccio_flash: vccio-flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_codec: LDO_REG2 { - regulator-name = "vcca_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_wl: LDO_REG4 { - regulator-name = "vcc_wl"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-name = "vcc_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio5>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - bb-supply = <&vcc_io>; - flash0-supply = <&vccio_flash>; - gpio1830-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_wl>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - }; - - vbus_host { - usb1_en_oc: usb1-en-oc { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - vbus_typec { - usb0_en_oc: usb0-en-oc { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdio_pwrseq { - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vbus_host { - enable-active-high; - gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ -}; - -&vbus_typec { - enable-active-high; - gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ -}; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts deleted file mode 100644 index b156a83eb7d7..000000000000 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ /dev/null @@ -1,500 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Jagan Teki - */ - -/dts-v1/; -#include "rk3288.dtsi" - -/ { - model = "Amarula Vyasa-RK3288"; - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - dc12_vbat: dc12-vbat { - compatible = "regulator-fixed"; - regulator-name = "dc12_vbat"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vboot_3v3: vboot-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vboot_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vboot_5v: vboot-5v { - compatible = "regulator-fixed"; - regulator-name = "vboot_sv"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - v3g_3v3: v3g-3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3g_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vsus_5v: vsus-5v { - compatible = "regulator-fixed"; - regulator-name = "vsus_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - enable-active-high; - gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - vusb1_5v: vusb1-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb1_5v"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vsus_5v>; - }; - - vusb2_5v: vusb2-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb2_5v"; - enable-active-high; - gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_codec: LDO_REG2 { - regulator-name = "vcc_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_gps: LDO_REG4 { - regulator-name = "vcc_gps"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcc_18>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_io>; - flash0-supply = <&vcc_18>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&phy_pwr_en>; - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vusb1_5v>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb_host { - phy_pwr_en: phy-pwr-en { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi deleted file mode 100644 index cb9cdaddffd4..000000000000 --- a/arch/arm/boot/dts/rk3288.dtsi +++ /dev/null @@ -1,2026 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "rockchip,rk3288"; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - arm-pmu { - compatible = "arm,cortex-a12-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - rockchip,pmu = <&pmu>; - - cpu0: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x500>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu1: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x501>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu2: cpu@502 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x502>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu3: cpu@503 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x503>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - }; - - cpu_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-126000000 { - opp-hz = /bits/ 64 <126000000>; - opp-microvolt = <900000>; - }; - opp-216000000 { - opp-hz = /bits/ 64 <216000000>; - opp-microvolt = <900000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <900000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - }; - opp-696000000 { - opp-hz = /bits/ 64 <696000000>; - opp-microvolt = <950000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1050000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1200000>; - }; - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1300000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * The rk3288 cannot use the memory area above 0xfe000000 - * for dma operations for some reason. While there is - * probably a better solution available somewhere, we - * haven't found it yet and while devices with 2GB of ram - * are not affected, this issue prevents 4GB from booting. - * So to make these devices at least bootable, block - * this area for the time being until the real solution - * is found. - */ - dma-unusable@fe000000 { - reg = <0x0 0xfe000000 0x0 0x1000000>; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - }; - - timer: timer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff810000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - sdmmc: mmc@ff0c0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0c0000 0x0 0x4000>; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio0: mmc@ff0d0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0d0000 0x0 0x4000>; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio1: mmc@ff0e0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, - <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0e0000 0x0 0x4000>; - resets = <&cru SRST_SDIO1>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@ff0f0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0f0000 0x0 0x4000>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 11>, <&dmac_peri 12>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - reg = <0x0 0xff110000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 13>, <&dmac_peri 14>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - reg = <0x0 0xff120000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff130000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 15>, <&dmac_peri 16>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - reg = <0x0 0xff130000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff140000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 1>, <&dmac_peri 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 3>, <&dmac_peri 4>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 7>, <&dmac_peri 8>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff1c0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1c0000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 9>, <&dmac_peri 10>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - reserve_thermal: reserve-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - }; - - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 2>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - gmac: ethernet@ff290000 { - compatible = "rockchip,rk3288-gmac"; - reg = <0x0 0xff290000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - resets = <&cru SRST_MAC>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ - usb_host0_ohci: usb@ff520000 { - compatible = "generic-ohci"; - reg = <0x0 0xff520000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1: usb@ff540000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff540000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USBHOST1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy2>; - phy-names = "usb2-phy"; - snps,reset-phy-on-wake; - status = "disabled"; - }; - - usb_otg: usb@ff580000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_hsic: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_HSIC>; - status = "disabled"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff660000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff660000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - bus_intmem: sram@ff700000 { - compatible = "mmio-sram"; - reg = <0x0 0xff700000 0x0 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xff700000 0x18000>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - pmu_sram: sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0x0 0xff720000 0x0 0x1000>; - }; - - pmu: power-management@ff730000 { - compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff730000 0x0 0x100>; - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - - /* - * Note: Although SCLK_* are the working clocks - * of device without including on the NOC, needed for - * synchronous reset. - * - * The clocks on the which NOC: - * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. - * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. - * ACLK_RGA is on ACLK_RGA_NIU. - * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. - * - * Which clock are device clocks: - * clocks devices - * *_IEP IEP:Image Enhancement Processor - * *_ISP ISP:Image Signal Processing - * *_VIP VIP:Video Input Processor - * *_VOP* VOP:Visual Output Processor - * *_RGA RGA - * *_EDP* EDP - * *_LVDS_* LVDS - * *_HDMI HDMI - * *_MIPI_* MIPI - */ - power-domain@RK3288_PD_VIO { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru ACLK_ISP>, - <&cru ACLK_RGA>, - <&cru ACLK_VIP>, - <&cru ACLK_VOP0>, - <&cru ACLK_VOP1>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru HCLK_IEP>, - <&cru HCLK_ISP>, - <&cru HCLK_RGA>, - <&cru HCLK_VIP>, - <&cru HCLK_VOP0>, - <&cru HCLK_VOP1>, - <&cru PCLK_EDP_CTRL>, - <&cru PCLK_HDMI_CTRL>, - <&cru PCLK_LVDS_PHY>, - <&cru PCLK_MIPI_CSI>, - <&cru PCLK_MIPI_DSI0>, - <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_EDP_24M>, - <&cru SCLK_EDP>, - <&cru SCLK_ISP_JPE>, - <&cru SCLK_ISP>, - <&cru SCLK_RGA>; - pm_qos = <&qos_vio0_iep>, - <&qos_vio1_vop>, - <&qos_vio1_isp_w0>, - <&qos_vio1_isp_w1>, - <&qos_vio0_vop>, - <&qos_vio0_vip>, - <&qos_vio2_rga_r>, - <&qos_vio2_rga_w>, - <&qos_vio1_isp_r>; - #power-domain-cells = <0>; - }; - - /* - * Note: The following 3 are HEVC(H.265) clocks, - * and on the ACLK_HEVC_NIU (NOC). - */ - power-domain@RK3288_PD_HEVC { - reg = ; - clocks = <&cru ACLK_HEVC>, - <&cru SCLK_HEVC_CABAC>, - <&cru SCLK_HEVC_CORE>; - pm_qos = <&qos_hevc_r>, - <&qos_hevc_w>; - #power-domain-cells = <0>; - }; - - /* - * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC - * (video endecoder & decoder) clocks that on the - * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). - */ - power-domain@RK3288_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_video>; - #power-domain-cells = <0>; - }; - - /* - * Note: ACLK_GPU is the GPU clock, - * and on the ACLK_GPU_NIU (NOC). - */ - power-domain@RK3288_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu_r>, - <&qos_gpu_w>; - #power-domain-cells = <0>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x94>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - sgrf: syscon@ff740000 { - compatible = "rockchip,rk3288-sgrf", "syscon"; - reg = <0x0 0xff740000 0x0 0x1000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3288-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, - <500000000>, <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x1000>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - status = "disabled"; - }; - - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBOTG_PHY>; - reset-names = "phy-reset"; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST0_PHY>; - reset-names = "phy-reset"; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST1_PHY>; - reset-names = "phy-reset"; - }; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; - reg = <0x0 0xff800000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - spdif: sound@ff8b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff8b0000 0x0 0x10000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2s: i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x10000>; - #sound-dai-cells = <0>; - interrupts = ; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - crypto: crypto@ff8a0000 { - compatible = "rockchip,rk3288-crypto"; - reg = <0x0 0xff8a0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - }; - - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - rockchip,disable-mmu-reset; - status = "disabled"; - }; - - rga: rga@ff920000 { - compatible = "rockchip,rk3288-rga"; - reg = <0x0 0xff920000 0x0 0x180>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; - reset-names = "core", "axi", "ahb"; - }; - - vopb: vop@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopb>; - }; - - vopb_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff940000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopl>; - }; - - vopl_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff940300 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_dsi: dsi@ff960000 { - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - - mipi_out: port@1 { - reg = <1>; - }; - }; - }; - - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0x0 0xff96c000 0x0 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - - lvds_out: port@1 { - reg = <1>; - }; - }; - }; - - edp: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0x0 0xff970000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&edp_phy>; - phy-names = "dp"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_EDP>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - - edp_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0x0 0xff980000 0x0 0x20000>; - reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "cec"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - vpu_mmu: iommu@ff9a0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760"; - reg = <0x0 0xffa30000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3288_PD_GPU>; - status = "disabled"; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <950000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1100000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1250000>; - }; - }; - - qos_gpu_r: qos@ffaa0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xffb20000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; - reg = <0x0 0xffb40000 0x0 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - cpu_id: cpu-id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3288-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff7b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@ff7c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO5>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@ff7d0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@ff7e0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO7>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@ff7f0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7f0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO8>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hdmi { - hdmi_cec_c0: hdmi-cec-c0 { - rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; - }; - - hdmi_cec_c7: hdmi-cec-c7 { - rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; - }; - - hdmi_ddc: hdmi-ddc { - rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - - hdmi_ddc_unwedge: hdmi-ddc-unwedge { - rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - suspend { - global_pwroff: global-pwroff { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; - }; - - ddr0_retention: ddr0-retention { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; - }; - - ddr1_retention: ddr1-retention { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, - <8 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, - <6 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, - <7 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, - <7 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, - <6 RK_PA1 1 &pcfg_pull_none>, - <6 RK_PA2 1 &pcfg_pull_none>, - <6 RK_PA3 1 &pcfg_pull_none>, - <6 RK_PA4 1 &pcfg_pull_none>, - <6 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_ctl: lcdc-ctl { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>, - <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, - <6 RK_PC1 1 &pcfg_pull_up>, - <6 RK_PC2 1 &pcfg_pull_up>, - <6 RK_PC3 1 &pcfg_pull_up>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, - <4 RK_PC5 1 &pcfg_pull_up>, - <4 RK_PC6 1 &pcfg_pull_up>, - <4 RK_PC7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; - }; - }; - - sdio1 { - sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; - }; - - sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, - <3 RK_PD1 4 &pcfg_pull_up>, - <3 RK_PD2 4 &pcfg_pull_up>, - <3 RK_PD3 4 &pcfg_pull_up>; - }; - - sdio1_cd: sdio1-cd { - rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; - }; - - sdio1_wp: sdio1-wp { - rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; - }; - - sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; - }; - - sdio1_int: sdio1-int { - rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; - }; - - sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; - }; - - sdio1_clk: sdio1-clk { - rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; - }; - - sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>, - <3 RK_PA4 2 &pcfg_pull_up>, - <3 RK_PA5 2 &pcfg_pull_up>, - <3 RK_PA6 2 &pcfg_pull_up>, - <3 RK_PA7 2 &pcfg_pull_up>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; - }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_cs1: spi2-cs1 { - rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; - }; - spi2_clk: spi2-clk { - rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, - <4 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, - <5 RK_PB1 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, - <7 RK_PC7 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, - <7 RK_PB0 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, - <5 RK_PB6 3 &pcfg_pull_none>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD2 3 &pcfg_pull_none>, - <3 RK_PD3 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none_12ma>, - <3 RK_PD5 3 &pcfg_pull_none_12ma>, - <3 RK_PD0 3 &pcfg_pull_none_12ma>, - <3 RK_PD1 3 &pcfg_pull_none_12ma>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA6 3 &pcfg_pull_none>, - <4 RK_PB1 3 &pcfg_pull_none_12ma>, - <4 RK_PA4 3 &pcfg_pull_none_12ma>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none>, - <3 RK_PD5 3 &pcfg_pull_none>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA4 3 &pcfg_pull_none>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA2 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi deleted file mode 100644 index cb4e42ede56a..000000000000 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ /dev/null @@ -1,488 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &emac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - spi0 = &spi0; - spi1 = &spi1; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - clock-output-names = "xin24m"; - }; - - gpu: gpu@10090000 { - compatible = "arm,mali-400"; - reg = <0x10090000 0x10000>; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - assigned-clocks = <&cru ACLK_GPU>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_GPU>; - status = "disabled"; - }; - - vpu: video-codec@10104000 { - compatible = "rockchip,rk3066-vpu"; - reg = <0x10104000 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, - <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; - clock-names = "aclk_vdpu", "hclk_vdpu", - "aclk_vepu", "hclk_vepu"; - }; - - L2: cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - global_timer: global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - status = "disabled"; - /* The clock source and the sched_clock provided by the arm_global_timer - * on Rockchip rk3066a/rk3188 are quite unstable because their rates - * depend on the CPU frequency. - * Keep the arm_global_timer disabled in order to have the - * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default. - */ - }; - - local_timer: local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - status = "disabled"; - }; - - qos_gpu: qos@1012d000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_lcdc0: qos@1012f000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f000 0x20>; - }; - - qos_cif0: qos@1012f080 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f080 0x20>; - }; - - qos_ipp: qos@1012f100 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f100 0x20>; - }; - - qos_lcdc1: qos@1012f180 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f180 0x20>; - }; - - qos_cif1: qos@1012f200 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f200 0x20>; - }; - - qos_rga: qos@1012f280 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f280 0x20>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy1>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - emac: ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x3c>; - interrupts = ; - - rockchip,grf = <&grf>; - - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref"; - max-speed = <100>; - phy-mode = "rmii"; - - status = "disabled"; - }; - - mmc0: mmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - mmc1: mmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x1021c000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 4>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - nfc: nand-controller@10500000 { - compatible = "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_NANDC0>; - clock-names = "ahb"; - status = "disabled"; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - grf: grf@20008000 { - compatible = "syscon", "simple-mfd"; - reg = <0x20008000 0x200>; - }; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@2002d000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - status = "disabled"; - }; - - i2c1: i2c@2002f000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002f000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C1>; - clock-names = "i2c"; - - status = "disabled"; - }; - - pwm0: pwm@20030000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030000 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - pwm1: pwm@20030010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030010 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - wdt: watchdog@2004c000 { - compatible = "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - i2c2: i2c@20056000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C2>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c3: i2c@2005a000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C3>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c4: i2c@2005e000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C4>; - clock-names = "i2c"; - - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - status = "disabled"; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@20070000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20070000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 10>, <&dmac2 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi1: spi@20074000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20074000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; -}; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi deleted file mode 100644 index da1d548b7330..000000000000 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include - -/ { - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vbus_host: vbus-host { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_en_oc>; - regulator-name = "vbus_host"; /* HOST-5V */ - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_en_oc>; - regulator-name = "vbus_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&gmac { - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile new file mode 100644 index 000000000000..0f46e18fe275 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1108-elgin-r1.dtb \ + rv1108-evb.dtb \ + rv1126-edgeble-neu2-io.dtb \ + rk3036-evb.dtb \ + rk3036-kylin.dtb \ + rk3066a-bqcurie2.dtb \ + rk3066a-marsboard.dtb \ + rk3066a-mk808.dtb \ + rk3066a-rayeager.dtb \ + rk3128-evb.dtb \ + rk3188-bqedison2qc.dtb \ + rk3188-px3-evb.dtb \ + rk3188-radxarock.dtb \ + rk3228-evb.dtb \ + rk3229-evb.dtb \ + rk3229-xms6.dtb \ + rk3288-evb-act8846.dtb \ + rk3288-evb-rk808.dtb \ + rk3288-firefly-beta.dtb \ + rk3288-firefly.dtb \ + rk3288-firefly-reload.dtb \ + rk3288-miqi.dtb \ + rk3288-phycore-rdk.dtb \ + rk3288-popmetal.dtb \ + rk3288-r89.dtb \ + rk3288-rock2-square.dtb \ + rk3288-rock-pi-n8.dtb \ + rk3288-tinker.dtb \ + rk3288-tinker-s.dtb \ + rk3288-veyron-brain.dtb \ + rk3288-veyron-fievel.dtb \ + rk3288-veyron-jaq.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-mickey.dtb \ + rk3288-veyron-mighty.dtb \ + rk3288-veyron-minnie.dtb \ + rk3288-veyron-pinky.dtb \ + rk3288-veyron-speedy.dtb \ + rk3288-veyron-tiger.dtb \ + rk3288-vyasa.dtb diff --git a/arch/arm/boot/dts/rockchip/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts new file mode 100644 index 000000000000..becdc0b664bf --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3036-evb.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3036.dtsi" + +/ { + model = "Rockchip RK3036 Evaluation board"; + compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&emac { + phy = <&phy0>; + phy-reset-duration = <10>; /* millisecond */ + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts new file mode 100644 index 000000000000..67e1e04139e7 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3036.dtsi" + +/ { + model = "Rockchip RK3036 KylinBoard"; + compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + work_led: led-0 { + gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + label = "kylin:red:led"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - SDIO_RESET_L_WL_RST + * - SDIO_RESET_L_BT_EN + */ + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */ + <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5616-codec"; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC1", "Microphone Jack", + "MIC2", "Microphone Jack", + "Microphone Jack", "micbias1", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + simple-audio-card,cpu { + sound-dai = <&i2s>; + }; + + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&acodec { + status = "okay"; +}; + +&emac { + phy = <&phy0>; + phy-reset-duration = <10>; /* millisecond */ + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&emmc { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vccio_pmu>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vout5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vout5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + rt5616: rt5616@1b { + compatible = "rt5616"; + reg = <0x1b>; + clocks = <&cru SCLK_I2S_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2s { + status = "okay"; +}; + +&sdio { + status = "okay"; + + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + rockchip,default-sample-phase = <90>; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&pinctrl { + leds { + led_ctl: led-ctl { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdio { + bt_wake_h: bt-wake-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + suspend { + global_pwroff: global-pwroff { + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi new file mode 100644 index 000000000000..78686fc72ce6 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -0,0 +1,871 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rk3036"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + mshc0 = &emmc; + mshc1 = &sdmmc; + mshc2 = &sdio; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + spi = &spi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + bus_intmem: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; + }; + }; + + gpu: gpu@10090000 { + compatible = "rockchip,rk3036-mali", "arm,mali-400"; + reg = <0x10090000 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0"; + assigned-clocks = <&cru SCLK_GPU>; + assigned-clock-rates = <100000000>; + clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; + clock-names = "bus", "core"; + power-domains = <&power RK3036_PD_GPU>; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + + vpu: video-codec@10108000 { + compatible = "rockchip,rk3036-vpu"; + reg = <0x10108000 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3036_PD_VPU>; + }; + + vpu_mmu: iommu@10108800 { + compatible = "rockchip,iommu"; + reg = <0x10108800 0x100>; + interrupts = ; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3036_PD_VPU>; + #iommu-cells = <0>; + }; + + vop: vop@10118000 { + compatible = "rockchip,rk3036-vop"; + reg = <0x10118000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + power-domains = <&power RK3036_PD_VIO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@10118300 { + compatible = "rockchip,iommu"; + reg = <0x10118300 0x100>; + interrupts = ; + clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3036_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_vio: qos@1012f000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x10139000 0x1000>, + <0x1013a000 0x2000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = ; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + status = "disabled"; + }; + + emac: ethernet@10200000 { + compatible = "rockchip,rk3036-emac"; + reg = <0x10200000 0x4000>; + interrupts = ; + rockchip,grf = <&grf>; + clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; + clock-names = "hclk", "macref", "macclk"; + /* + * Fix the emac parent clock is DPLL instead of APLL. + * since that will cause some unstable things if the cpufreq + * is working. (e.g: the accurate 50MHz what mac_ref need) + */ + assigned-clocks = <&cru SCLK_MACPLL>; + assigned-clock-parents = <&cru PLL_DPLL>; + max-speed = <100>; + phy-mode = "rmii"; + status = "disabled"; + }; + + sdmmc: mmc@10214000 { + compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10214000 0x4000>; + clock-frequency = <37500000>; + max-frequency = <37500000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio: mmc@10218000 { + compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10218000 0x4000>; + max-frequency = <37500000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@1021c000 { + compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x1021c000 0x4000>; + interrupts = ; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <37500000>; + max-frequency = <37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + rockchip,default-sample-phase = <158>; + disable-wp; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <0x100>; + mmc-ddr-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + i2s: i2s@10220000 { + compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; + reg = <0x10220000 0x4000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + nfc: nand-controller@10500000 { + compatible = "rockchip,rk3036-nfc", + "rockchip,rk2928-nfc"; + reg = <0x10500000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 + &flash_rdn &flash_rdy &flash_wrn>; + pinctrl-names = "default"; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; + reg = <0x20008000 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3036-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3036_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC>, + <&cru HCLK_LCDC>, + <&cru SCLK_LCDC>; + pm_qos = <&qos_vio>; + #power-domain-cells = <0>; + }; + + power-domain@RK3036_PD_VPU { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3036_PD_GPU { + reg = ; + clocks = <&cru SCLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x1d8>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; + }; + + acodec: acodec-ana@20030000 { + compatible = "rk3036-codec"; + reg = <0x20030000 0x4000>; + rockchip,grf = <&grf>; + clock-names = "acodec_pclk"; + clocks = <&cru PCLK_ACODEC>; + status = "disabled"; + }; + + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3036-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = ; + clocks = <&cru PCLK_HDMI>; + clock-names = "pclk"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ctl>; + status = "disabled"; + + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + + timer: timer@20044000 { + compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; + reg = <0x20044000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@2005a000 { + compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + i2c0: i2c@20072000 { + compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; + reg = <0x20072000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + spi: spi@20074000 { + compatible = "rockchip,rockchip-spi"; + reg = <0x20074000 0x1000>; + interrupts = ; + clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; + clock-names = "apb-pclk","spi_pclk"; + dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pdma: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3036-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, + <1 RK_PC3 1 &pcfg_pull_default>, + <1 RK_PC4 1 &pcfg_pull_default>, + <1 RK_PC5 1 &pcfg_pull_default>; + }; + }; + + sdio { + sdio_bus1: sdio-bus1 { + rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, + <0 RK_PB4 1 &pcfg_pull_default>, + <0 RK_PB5 1 &pcfg_pull_default>, + <0 RK_PB6 1 &pcfg_pull_default>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; + }; + + sdio_clk: sdio-clk { + rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, + <1 RK_PD1 2 &pcfg_pull_default>, + <1 RK_PD2 2 &pcfg_pull_default>, + <1 RK_PD3 2 &pcfg_pull_default>, + <1 RK_PD4 2 &pcfg_pull_default>, + <1 RK_PD5 2 &pcfg_pull_default>, + <1 RK_PD6 2 &pcfg_pull_default>, + <1 RK_PD7 2 &pcfg_pull_default>; + }; + }; + + nfc { + flash_ale: flash-ale { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, + <1 RK_PD1 1 &pcfg_pull_default>, + <1 RK_PD2 1 &pcfg_pull_default>, + <1 RK_PD3 1 &pcfg_pull_default>, + <1 RK_PD4 1 &pcfg_pull_default>, + <1 RK_PD5 1 &pcfg_pull_default>, + <1 RK_PD6 1 &pcfg_pull_default>, + <1 RK_PD7 1 &pcfg_pull_default>; + }; + + flash_cle: flash-cle { + rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; + }; + + flash_csn0: flash-csn0 { + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; + }; + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ + <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ + <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ + <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ + <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ + <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ + <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ + <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ + <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + i2s { + i2s_bus: i2s-bus { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, + <1 RK_PA1 1 &pcfg_pull_default>, + <1 RK_PA2 1 &pcfg_pull_default>, + <1 RK_PA3 1 &pcfg_pull_default>, + <1 RK_PA4 1 &pcfg_pull_default>, + <1 RK_PA5 1 &pcfg_pull_default>; + }; + }; + + hdmi { + hdmi_ctl: hdmi-ctl { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, + <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>, + <1 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, + <2 RK_PC7 1 &pcfg_pull_none>; + }; + /* no rts / cts for uart1 */ + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, + <1 RK_PC3 2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + spi-pins { + spi_txd:spi-txd { + rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; + }; + + spi_rxd:spi-rxd { + rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; + }; + + spi_clk:spi-clk { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; + }; + + spi_cs0:spi-cs0 { + rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; + + }; + + spi_cs1:spi-cs1 { + rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; + + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts new file mode 100644 index 000000000000..f924d4d64c3d --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + */ + +/dts-v1/; +#include +#include "rk3066a.dtsi" + +/ { + model = "bq Curie 2"; + compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 1000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + voltage-table = <1000000 100>, + <1200000 42>; + status = "okay"; + }; + + vcc_sd0: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-power { + gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + key-volume-down { + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ + linux,code = ; + label = "GPIO Key Vol-"; + linux,input-type = <1>; + debounce-interval = <100>; + }; + /* VOL+ comes somehow thru the ADC */ + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + + interrupt-parent = <&gpio6>; + interrupts = ; + + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vcc_rtc: regulator@0 { + regulator-name = "vcc_rtc"; + regulator-always-on; + }; + + vcc_io: regulator@1 { + regulator-name = "vcc_io"; + regulator-always-on; + }; + + vdd_arm: regulator@2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_ddr: regulator@3 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc18_cif: regulator@5 { + regulator-name = "vcc18_cif"; + regulator-always-on; + }; + + vdd_11: regulator@6 { + regulator-name = "vdd_11"; + regulator-always-on; + }; + + vcc_25: regulator@7 { + regulator-name = "vcc_25"; + regulator-always-on; + }; + + vcc_18: regulator@8 { + regulator-name = "vcc_18"; + regulator-always-on; + }; + + vcc25_hdmi: regulator@9 { + regulator-name = "vcc25_hdmi"; + regulator-always-on; + }; + + vcca_33: regulator@10 { + regulator-name = "vcca_33"; + regulator-always-on; + }; + + vcc_tp: regulator@11 { + regulator-name = "vcc_tp"; + regulator-always-on; + }; + + vcc28_cif: regulator@12 { + regulator-name = "vcc28_cif"; + regulator-always-on; + }; + }; + }; +}; + +/* must be included after &tps gets defined */ +#include "../tps65910.dtsi" + +&mmc0 { /* sdmmc */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd0>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; +}; + +&mmc1 { /* wifi */ + status = "okay"; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + + bus-width = <4>; +}; + +&pwm3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts new file mode 100644 index 000000000000..f6e8d49a02ef --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2014 Romain Perier + */ + +/dts-v1/; +#include "rk3066a.dtsi" + +/ { + model = "MarsBoard RK3066"; + compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; + + aliases { + mmc0 = &mmc0; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 1000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + voltage-table = <1000000 100>, + <1200000 42>; + status = "okay"; + }; + + vcc_sd0: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + + interrupt-parent = <&gpio6>; + interrupts = ; + + vcc1-supply = <&vsys>; + vcc2-supply = <&vsys>; + vcc3-supply = <&vsys>; + vcc4-supply = <&vsys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + vcc7-supply = <&vsys>; + vccio-supply = <&vsys>; + + regulators { + vcc_rtc: regulator@0 { + regulator-name = "vcc_rtc"; + regulator-always-on; + }; + + vcc_io: regulator@1 { + regulator-name = "vcc_io"; + regulator-always-on; + }; + + vdd_arm: regulator@2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_ddr: regulator@3 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc18_cif: regulator@5 { + regulator-name = "vcc18_cif"; + regulator-always-on; + }; + + vdd_11: regulator@6 { + regulator-name = "vdd_11"; + regulator-always-on; + }; + + vcc_25: regulator@7 { + regulator-name = "vcc_25"; + regulator-always-on; + }; + + vcc_18: regulator@8 { + regulator-name = "vcc_18"; + regulator-always-on; + }; + + vcc25_hdmi: regulator@9 { + regulator-name = "vcc25_hdmi"; + regulator-always-on; + }; + + vcca_33: regulator@10 { + regulator-name = "vcca_33"; + regulator-always-on; + }; + + vcc_rmii: regulator@11 { + regulator-name = "vcc_rmii"; + }; + + vcc28_cif: regulator@12 { + regulator-name = "vcc28_cif"; + regulator-always-on; + }; + }; + }; +}; + +/* must be included after &tps gets defined */ +#include "../tps65910.dtsi" + +&emac { + phy = <&phy0>; + phy-supply = <&vcc_rmii>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = ; + }; + }; +}; + +&mmc0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd0>; +}; + +&pinctrl { + lan8720a { + phy_int: phy-int { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts new file mode 100644 index 000000000000..06790f05b395 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Paweł Jarosz + */ + +/dts-v1/; +#include +#include "rk3066a.dtsi" + +/ { + model = "Rikomagic MK808"; + compatible = "rikomagic,mk808", "rockchip,rk3066a"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x40000000>; + device_type = "memory"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <2500000>; + poll-interval = <100>; + + button-recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue_led: led-0 { + label = "mk808:blue:power"; + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "default-on"; + }; + }; + + hdmi_con { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_2v5: vcc-2v5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&host_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_wifi: sdio-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + non-removable; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&nfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + label = "rk-nand"; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <40>; + nand-is-boot-medium; + rockchip,boot-blks = <8>; + rockchip,boot-ecc-strength = <24>; + }; +}; + +&pinctrl { + usb-host { + host_drv: host-drv { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + usb-otg { + otg_drv: otg-drv { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdio { + wifi_pwr: wifi-pwr { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_2v5>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&vop0 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts new file mode 100644 index 000000000000..29d8e5bf88f5 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2014, 2015 FUKAUMI Naoki + */ + +/dts-v1/; +#include +#include "rk3066a.dtsi" + +/ { + model = "Rayeager PX2"; + compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &emmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio6 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + + key-power { + wakeup-source; + gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 1000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + voltage-table = <1000000 100>, + <1200000 42>; + status = "okay"; + }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ + vcc_stdby: stdby-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_stdby"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_emmc: emmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "emmc_vccq"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vsys>; + }; + + vcc_sata: sata-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sata_pwr>; + regulator-name = "usb_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_stdby>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_drv>; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_stdby>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv>; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_stdby>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&emac { + phy = <&phy0>; + phy-supply = <&vcc_rmii>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; + vmmc-supply = <&vcc_emmc>; + vqmmc-supply = <&vcc_emmc>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + ak8963: ak8963@d { + compatible = "asahi-kasei,ak8975"; + reg = <0x0d>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&comp_int>; + }; + + mma8452: mma8452@1d { + compatible = "fsl,mma8452"; + reg = <0x1d>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + tps: tps@2d { + reg = <0x2d>; + interrupt-parent = <&gpio6>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pwr_hold>; + + vcc1-supply = <&vsys>; + vcc2-supply = <&vsys>; + vcc3-supply = <&vsys>; + vcc4-supply = <&vsys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + vcc7-supply = <&vsys>; + vccio-supply = <&vsys>; + + regulators { + vcc_rtc: regulator@0 { + regulator-name = "vcc_rtc"; + regulator-always-on; + }; + + vcc_io: regulator@1 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_arm: regulator@2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_ddr: regulator@3 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc18: regulator@5 { + regulator-name = "vcc18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_11: regulator@6 { + regulator-name = "vdd_11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_25: regulator@7 { + regulator-name = "vcc_25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vccio_wl: regulator@8 { + regulator-name = "vccio_wl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc25_hdmi: regulator@9 { + regulator-name = "vcc25_hdmi"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vcca_33: regulator@10 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_rmii: regulator@11 { + regulator-name = "vcc_rmii"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc28_cif: regulator@12 { + regulator-name = "vcc28_cif"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + }; +}; + +#include "../tps65910.dtsi" + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + cap-mmc-highspeed; + cap-sd-highspeed; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; + vmmc-supply = <&vccio_wl>; + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + ak8963 { + comp_int: comp-int { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + emac { + rmii_rst: rmii-rst { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <6 RK_PA1 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <6 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + mma8452 { + gsensor_int: gsensor-int { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + mmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + usb_host { + host_drv: host-drv { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; + }; + + hub_rst: hub-rst { + rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; + }; + + sata_pwr: sata-pwr { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_default>; + }; + + sata_reset: sata-reset { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_drv: otg-drv { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + tps { + pmic_int: pmic-int { + rockchip,pins = <6 RK_PA4 RK_FUNC_GPIO &pcfg_pull_default>; + }; + + pwr_hold: pwr-hold { + rockchip,pins = <6 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_25>; + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>, <&uart3_cts>, <&uart3_rts>; + status = "okay"; +}; + +&usb_host { + pinctrl-names = "default"; + pinctrl-0 = <&hub_rst>, <&sata_reset>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi new file mode 100644 index 000000000000..de9915d946f7 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3066a.dtsi @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#include +#include +#include +#include +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + operating-points = + /* kHz uV */ + <1416000 1300000>, + <1200000 1175000>, + <1008000 1125000>, + <816000 1125000>, + <600000 1100000>, + <504000 1100000>, + <312000 1075000>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + vop0: vop@1010c000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010c000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, + <&cru DCLK_LCDC0>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, + <&cru SRST_LCDC0_AHB>, + <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop0_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop0>; + }; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010e000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop1_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop1>; + }; + }; + }; + + hdmi: hdmi@10116000 { + compatible = "rockchip,rk3066-hdmi"; + reg = <0x10116000 0x2000>; + interrupts = ; + clocks = <&cru HCLK_HDMI>; + clock-names = "hclk"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vop0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop0_out_hdmi>; + }; + + hdmi_in_vop1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vop1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; + }; + + timer2: timer@2000e000 { + compatible = "snps,dw-apb-timer"; + reg = <0x2000e000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rk3066a-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + timer0: timer@20038000 { + compatible = "snps,dw-apb-timer"; + reg = <0x20038000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer1: timer@2003a000 { + compatible = "snps,dw-apb-timer"; + reg = <0x2003a000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + + tsadc: tsadc@20060000 { + compatible = "rockchip,rk3066-tsadc"; + reg = <0x20060000 0x100>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = ; + #io-channel-cells = <1>; + resets = <&cru SRST_TSADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ + <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ + <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ + <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ + <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ + <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ + <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ + <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ + <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, + <2 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, + <2 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, + <3 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, + <1 RK_PA1 1 &pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, + <1 RK_PA5 1 &pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, + <3 RK_PD4 1 &pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, + <3 RK_PB3 1 &pcfg_pull_default>, + <3 RK_PB4 1 &pcfg_pull_default>, + <3 RK_PB5 1 &pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, + <3 RK_PC2 1 &pcfg_pull_default>, + <3 RK_PC3 1 &pcfg_pull_default>, + <3 RK_PC4 1 &pcfg_pull_default>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, + <0 RK_PB0 1 &pcfg_pull_default>, + <0 RK_PB1 1 &pcfg_pull_default>, + <0 RK_PB2 1 &pcfg_pull_default>, + <0 RK_PB3 1 &pcfg_pull_default>, + <0 RK_PB4 1 &pcfg_pull_default>, + <0 RK_PB5 1 &pcfg_pull_default>, + <0 RK_PB6 1 &pcfg_pull_default>, + <0 RK_PB7 1 &pcfg_pull_default>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, + <0 RK_PC1 1 &pcfg_pull_default>, + <0 RK_PC2 1 &pcfg_pull_default>, + <0 RK_PC3 1 &pcfg_pull_default>, + <0 RK_PC4 1 &pcfg_pull_default>, + <0 RK_PC5 1 &pcfg_pull_default>; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, + <0 RK_PD1 1 &pcfg_pull_default>, + <0 RK_PD2 1 &pcfg_pull_default>, + <0 RK_PD3 1 &pcfg_pull_default>, + <0 RK_PD4 1 &pcfg_pull_default>, + <0 RK_PD5 1 &pcfg_pull_default>; + }; + }; + }; +}; + +&gpu { + compatible = "rockchip,rk3066-mali", "arm,mali-400"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + power-domains = <&power RK3066_PD_GPU>; +}; + +&grf { + compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3066a-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@17c { + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@188 { + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&mmc0 { + clock-frequency = <50000000>; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; +}; + +&mmc1 { + dmas = <&dmac2 3>; + dma-names = "rx-tx"; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +}; + +&emmc { + dmas = <&dmac2 4>; + dma-names = "rx-tx"; +}; + +&pmu { + power: power-controller { + compatible = "rockchip,rk3066-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3066_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF1>, + <&cru ACLK_CIF1>, + <&cru HCLK_CIF1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru HCLK_HDMI>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_cif1>, + <&qos_ipp>, + <&qos_rga>; + #power-domain-cells = <0>; + }; + + power-domain@RK3066_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3066_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 0>, <&dmac1_s 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 2>, <&dmac1_s 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 6>, <&dmac2 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 8>, <&dmac2 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + +&wdt { + compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; +}; + +&emac { + compatible = "rockchip,rk3066-emac"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3128-evb.dts b/arch/arm/boot/dts/rockchip/rk3128-evb.dts new file mode 100644 index 000000000000..c38f42497cbd --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3128-evb.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3128.dtsi" + +/ { + model = "Rockchip RK3128 Evaluation board"; + compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c1 = &i2c1; + mmc0 = &emmc; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&emmc { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&pinctrl { + usb-host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi new file mode 100644 index 000000000000..b63bd4ad3143 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3128"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + ; + arm,cpu-registers-not-fw-configured; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + pmu: syscon@100a0000 { + compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; + reg = <0x100a0000 0x1000>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ehci: usb@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x20000>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@101e0000 { + compatible = "generic-ohci"; + reg = <0x101e0000 0x20000>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + sdmmc: mmc@10214000 { + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10214000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + dmas = <&pdma 10>; + dma-names = "rx-tx"; + fifo-depth = <256>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio: mmc@10218000 { + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10218000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + dmas = <&pdma 11>; + dma-names = "rx-tx"; + fifo-depth = <256>; + max-frequency = <150000000>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@1021c000 { + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x1021c000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <256>; + max-frequency = <150000000>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + nfc: nand-controller@10500000 { + compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; + reg = <0x10500000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + pinctrl-names = "default"; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 + &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; + reg = <0x20008000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usb2phy: usb2phy@17c { + compatible = "rockchip,rk3128-usb2phy"; + reg = <0x017c 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + usb2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + timer0: timer@20044000 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer1: timer@20044020 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044020 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer2: timer@20044040 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044040 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer3: timer@20044060 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044060 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer4: timer@20044080 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044080 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer5: timer@200440a0 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x200440a0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + watchdog: watchdog@2004c000 { + compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; + reg = <0x2004c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_WDT>; + status = "disabled"; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050000 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050010 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050020 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050030 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@2005a000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@2005e000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 2>, <&pdma 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 4>, <&pdma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 6>, <&pdma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + i2c0: i2c@20072000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <20072000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@20074000 { + compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; + reg = <0x20074000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pdma: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3128-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20088000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20088000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; + }; + + emmc_cmd1: emmc-cmd1 { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, + <1 RK_PD1 2 &pcfg_pull_default>, + <1 RK_PD2 2 &pcfg_pull_default>, + <1 RK_PD3 2 &pcfg_pull_default>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, + <1 RK_PD1 2 &pcfg_pull_default>, + <1 RK_PD2 2 &pcfg_pull_default>, + <1 RK_PD3 2 &pcfg_pull_default>, + <1 RK_PD4 2 &pcfg_pull_default>, + <1 RK_PD5 2 &pcfg_pull_default>, + <1 RK_PD6 2 &pcfg_pull_default>, + <1 RK_PD7 2 &pcfg_pull_default>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, + <2 RK_PB1 3 &pcfg_pull_default>, + <2 RK_PB3 3 &pcfg_pull_default>, + <2 RK_PB4 3 &pcfg_pull_default>, + <2 RK_PB5 3 &pcfg_pull_default>, + <2 RK_PB6 3 &pcfg_pull_default>, + <2 RK_PC0 3 &pcfg_pull_default>, + <2 RK_PC1 3 &pcfg_pull_default>, + <2 RK_PC2 3 &pcfg_pull_default>, + <2 RK_PC3 3 &pcfg_pull_default>, + <2 RK_PD1 3 &pcfg_pull_default>, + <2 RK_PC4 4 &pcfg_pull_default>, + <2 RK_PC5 4 &pcfg_pull_default>, + <2 RK_PC6 4 &pcfg_pull_default>, + <2 RK_PC7 4 &pcfg_pull_default>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, + <2 RK_PB4 3 &pcfg_pull_default>, + <2 RK_PB5 3 &pcfg_pull_default>, + <2 RK_PB6 3 &pcfg_pull_default>, + <2 RK_PB7 3 &pcfg_pull_default>, + <2 RK_PC0 3 &pcfg_pull_default>, + <2 RK_PC1 3 &pcfg_pull_default>, + <2 RK_PC2 3 &pcfg_pull_default>, + <2 RK_PC3 3 &pcfg_pull_default>, + <2 RK_PD1 3 &pcfg_pull_default>; + }; + }; + + hdmi { + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, + <2 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + i2s { + i2s_bus: i2s-bus { + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB1 1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB5 1 &pcfg_pull_none>, + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + i2s1_bus: i2s1-bus { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, + <1 RK_PA1 1 &pcfg_pull_none>, + <1 RK_PA2 1 &pcfg_pull_none>, + <1 RK_PA3 1 &pcfg_pull_none>, + <1 RK_PA4 1 &pcfg_pull_none>, + <1 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + lcdc { + lcdc_dclk: lcdc-dclk { + rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; + }; + + lcdc_den: lcdc-den { + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; + }; + + lcdc_hsync: lcdc-hsync { + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; + }; + + lcdc_vsync: lcdc-vsync { + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; + }; + + lcdc_rgb24: lcdc-rgb24 { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>, + <2 RK_PD0 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + nfc { + flash_ale: flash-ale { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; + }; + + flash_cle: flash-cle { + rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; + }; + + flash_cs0: flash-cs0 { + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; + }; + + flash_dqs: flash-dqs { + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>, + <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>, + <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>, + <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; + }; + + sdio_pwren: sdio-pwren { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, + <1 RK_PA2 2 &pcfg_pull_default>, + <1 RK_PA4 2 &pcfg_pull_default>, + <1 RK_PA5 2 &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, + <1 RK_PC3 1 &pcfg_pull_default>, + <1 RK_PC4 1 &pcfg_pull_default>, + <1 RK_PC5 1 &pcfg_pull_default>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; + }; + + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; + }; + + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; + }; + + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; + }; + + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; + }; + + spi1_clk: spi1-clk { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; + }; + + spi1_cs0: spi1-cs0 { + rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; + }; + + spi1_tx: spi1-tx { + rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; + }; + + spi1_rx: spi1-rx { + rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; + }; + + spi1_cs1: spi1-cs1 { + rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; + }; + + spi2_clk: spi2-clk { + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; + }; + + spi2_cs0: spi2-cs0 { + rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; + }; + + spi2_tx: spi2-tx { + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; + }; + + spi2_rx: spi2-rx { + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, + <2 RK_PD3 2 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, + <1 RK_PB2 2 &pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts new file mode 100644 index 000000000000..9312be362a7a --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 MundoReader S.L. + * Author: Heiko Stuebner + */ + +/dts-v1/; +#include +#include +#include +#include "rk3188.dtsi" + +/ { + model = "BQ Edison2 Quad-Core"; + compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &emmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vsys>; + pwms = <&pwm1 0 25000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key &usb_int>; + + key-power { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + wake_on_usb: key-wake-on-usb { + label = "Wake-on-USB"; + gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_hold>; + /* only drive the pin low until device is off */ + active-delay-ms = <3000>; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_vop0: endpoint { + remote-endpoint = <&vop0_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + + panel { + compatible = "innolux,ee101ia-01d", "panel-lvds"; + backlight = <&backlight>; + + /* pin LCD_CS, Nshtdn input of lvds-encoder */ + enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_cs>; + power-supply = <&vcc_lcd>; + + data-mapping = "vesa-24"; + height-mm = <163>; + width-mm = <261>; + + panel-timing { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <160>; + hfront-porch = <16>; + hsync-len = <10>; + vback-porch = <23>; + vfront-porch = <12>; + vsync-len = <3>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + }; + + avdd_cif: cif-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd-cif"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_avdd_en>; + startup-delay-us = <100000>; + vin-supply = <&vcc28_cif>; + }; + + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&v5_drv>; + vin-supply = <&vsys>; + }; + + vcc_lcd: lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-lcd"; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + startup-delay-us = <50000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv>; + startup-delay-us = <100000>; + vin-supply = <&vcc_5v>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vccq_emmc: emmc-vccq-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccq-emmc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + /* supplied from the bq24196 */ + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <504000000>, + <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccq_emmc>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lis3de: accelerometer@29 { + compatible = "st,lis3de"; + reg = <0x29>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + rotation-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + vdd-supply = <&vcc_io>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + tmp108@48 { + compatible = "ti,tmp108"; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tmp_alrt>; + #thermal-sensor-cells = <0>; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + bat: battery@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + power-supplies = <&bq24196>; + }; + + act8846: pmic@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&dvs0_ctl &pmic_int>; + + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vcc_io: vcc_hdmi: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_12: REG6 { + regulator-name = "VDD_12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc18_cif: REG7 { + regulator-name = "VCC18_CIF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_tp: REG9 { + regulator-name = "VCC_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28_cif: REG12 { + regulator-name = "VCC28_CIF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; + + bq24196: charger@6b { + compatible = "ti,bq24196"; + reg = <0x6b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_int &chg_ctl &otg_en>; + ti,system-minimum-microvolt = <3200000>; + monitored-battery = <&bat>; + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + ft5606: touchscreen@3e { + compatible = "edt,edt-ft5506"; + reg = <0x3e>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int &tp_rst>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + touchscreen-inverted-y; + /* hw ts resolution does not match display */ + touchscreen-size-y = <1024>; + touchscreen-size-x = <768>; + touchscreen-swapped-x-y; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + rt5616: codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + clocks = <&cru SCLK_I2S0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; + vqmmc-supply = <&vccio_wl>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio3>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + dvs0_ctl: dvs0-ctl { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + bq24196 { + charger_int: charger-int { + rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* pin hog to make it select usb profile */ + chg_ctl: chg-ctl { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + /* low: charging, high: complete, fault: blinking */ + chg_det: chg-det { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* charging enabled when pin low and register set */ + chg_en: chg-en { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + /* bq29196 powergood (when low) signal */ + dc_det: dc-det { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* wire bq24196 otg pin to high, to enable 500mA charging */ + otg_en: otg-en { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + camera { + cif0_pdn: cif0-pdn { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif1_pdn: cif1-pdn { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif_avdd_en: cif-avdd-en { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + display { + lcd_cs: lcd-cs { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_en: lcd-en { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ft5606 { + tp_int: tp-int { + rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst: tp-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_int: hdmi-int { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdmi_rst: hdmi-rst { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_hold: pwr-hold { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lis3de { + gsensor_int: gsensor-int { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tmp108 { + tmp_alrt: tmp-alrt { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + v5_drv: v5-drv { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_drv: otg-drv { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_int: usb-int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rk903 { + bt_host_wake: bt-host-wake { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_reg_on: bt-reg-on { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* pin hog to pull the reset high */ + bt_rst: bt-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop0 { + status = "okay"; +}; + +&vop0_out { + vop0_out_lvds: endpoint { + remote-endpoint = <&lvds_in_vop0>; + }; +}; + +&vop1 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync + &lcdc1_vsync &lcdc1_rgb24>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts b/arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts new file mode 100644 index 000000000000..0a1ae689b162 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andy Yan + */ + +/dts-v1/; +#include +#include "rk3188.dtsi" + +/ { + model = "Rockchip PX3-EVB"; + compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + + aliases { + mmc0 = &mmc0; + mmc1 = &emmc; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x80000000>; + device_type = "memory"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-power { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = ; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_cif: LDO_REG1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_cif"; + }; + + vcc_jetta33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_jetta33"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + lvds_12: LDO_REG4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "lvds_12"; + }; + + lvds_25: LDO_REG5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lvds_25"; + }; + + cif_18: LDO_REG6 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "cif_18"; + }; + + vcc_sd: LDO_REG7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + wl_18: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wl_18"; + }; + + lcd_33: SWITCH_REG { + regulator-name = "lcd_33"; + }; + }; + }; + +}; + +&i2c2 { + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio1>; + interrupts = ; + power-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts new file mode 100644 index 000000000000..118deacd38c4 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 Heiko Stuebner + */ + +/dts-v1/; +#include +#include "rk3188.dtsi" + +/ { + model = "Radxa Rock"; + compatible = "radxa,rock", "rockchip,rk3188"; + + aliases { + mmc0 = &mmc0; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-power { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green_led: led-0 { + label = "rock:green:user1"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue_led: led-1 { + label = "rock:blue:user2"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + sleep_led: led-2 { + label = "rock:red:power"; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ + cpu { sound-dai = <&spdif>; }; + codec { sound-dai = <&spdif_out>; }; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_recv_pin>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd0: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&emac { + phy = <&phy0>; + phy-supply = <&vcc_rmii>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = ; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&act8846_dvs0_ctl>; + + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vcc_io: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_hdmi: REG6 { + regulator-name = "VDD_HDMI"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vcc18: REG7 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_rmii: REG9 { + regulator-name = "VCC_RMII"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC18_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28: REG12 { + regulator-name = "VCC_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd0>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + act8846_dvs0_ctl: act8846-dvs0-ctl { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lan8720a { + phy_int: phy-int { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir-receiver { + ir_recv_pin: ir-recv-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd0 { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi new file mode 100644 index 000000000000..44b54af0bbf9 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3188.dtsi @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#include +#include +#include +#include +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3188"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE1>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x2>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE2>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x3>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE3>; + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <875000>; + clock-latency-ns = <40000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <925000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + opp-suspend; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1075000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + vop0: vop@1010c000 { + compatible = "rockchip,rk3188-vop"; + reg = <0x1010c000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3188-vop"; + reg = <0x1010e000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + timer3: timer@2000e000 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x2000e000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; + clock-names = "pclk", "timer"; + }; + + timer6: timer@200380a0 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x200380a0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; + clock-names = "pclk", "timer"; + }; + + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif: sound@1011e000 { + compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; + reg = <0x1011e000 0x2000>; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1_s 8>; + dma-names = "tx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rk3188-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3188-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ + <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ + <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ + <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ + <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ + <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ + <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ + <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, + <3 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, + <3 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + lcdc1 { + lcdc1_dclk: lcdc1-dclk { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; + }; + + lcdc1_den: lcdc1-den { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; + }; + + lcdc1_hsync: lcdc1-hsync { + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; + }; + + lcdc1_vsync: lcdc1-vsync { + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; + }; + + lcdc1_rgb24: lcdc1-rgb24 { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_none>, + <2 RK_PA2 1 &pcfg_pull_none>, + <2 RK_PA3 1 &pcfg_pull_none>, + <2 RK_PA4 1 &pcfg_pull_none>, + <2 RK_PA5 1 &pcfg_pull_none>, + <2 RK_PA6 1 &pcfg_pull_none>, + <2 RK_PA7 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB1 1 &pcfg_pull_none>, + <2 RK_PB2 1 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, + <1 RK_PA1 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, + <1 RK_PB1 1 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; + }; + + sd0_pwr: sd0-pwr { + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, + <3 RK_PC2 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, + <1 RK_PC1 1 &pcfg_pull_none>, + <1 RK_PC2 1 &pcfg_pull_none>, + <1 RK_PC3 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>, + <1 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; + }; + }; + }; +}; + +&emac { + compatible = "rockchip,rk3188-emac"; +}; + +&global_timer { + interrupts = ; +}; + +&local_timer { + interrupts = ; +}; + +&gpu { + compatible = "rockchip,rk3188-mali", "arm,mali-400"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + power-domains = <&power RK3188_PD_GPU>; +}; + +&grf { + compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; + + io_domains: io-domains { + compatible = "rockchip,rk3188-io-voltage-domain"; + status = "disabled"; + }; + + usbphy: usbphy { + compatible = "rockchip,rk3188-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@11c { + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + +&i2c0 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&pmu { + power: power-controller { + compatible = "rockchip,rk3188-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3188_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_ipp>, + <&qos_rga>; + #power-domain-cells = <0>; + }; + + power-domain@RK3188_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3188_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + +&wdt { + compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3228-evb.dts b/arch/arm/boot/dts/rockchip/rk3228-evb.dts new file mode 100644 index 000000000000..69a5e239ed1a --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3228-evb.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk322x.dtsi" + +/ { + model = "Rockchip RK3228 Evaluation board"; + compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; + + aliases { + mmc0 = &emmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-supply = <&vcc_phy>; + phy-mode = "rmii"; + phy-handle = <&phy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC_PHY>; + resets = <&cru SRST_MACPHY>; + phy-is-integrated; + }; + }; +}; + +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3229-evb.dts b/arch/arm/boot/dts/rockchip/rk3229-evb.dts new file mode 100644 index 000000000000..5c3d08e3eea3 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3229-evb.dts @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include "rk3229.dtsi" + +/ { + model = "Rockchip RK3229 Evaluation board"; + compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + + aliases { + mmc0 = &emmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vccio_1v8>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power_key: power-key { + label = "GPIO Key Power"; + gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + non-removable; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio4-supply = <&vccio_3v3>; +}; + +&pinctrl { + keys { + pwr_key: pwr-key { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3229-xms6.dts b/arch/arm/boot/dts/rockchip/rk3229-xms6.dts new file mode 100644 index 000000000000..7bfbfd11fb55 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3229-xms6.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include "rk3229.dtsi" + +/ { + model = "Mecer Xtreme Mini S6"; + compatible = "mecer,xms6", "rockchip,rk3229"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &emmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + power-led { + compatible = "gpio-leds"; + + blue_led: led-0 { + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 29 GPIO_ACTIVE_LOW>; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vccio_1v8>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + non-removable; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_phy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id1234.d400", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC_PHY>; + phy-is-integrated; + resets = <&cru SRST_MACPHY>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_log>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio4-supply = <&vccio_3v3>; +}; + +&pinctrl { + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + vqmmc-supply = <&vccio_1v8>; + status = "okay"; +}; + +&sdmmc { + cap-mmc-highspeed; + disable-wp; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart21_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3229.dtsi b/arch/arm/boot/dts/rockchip/rk3229.dtsi new file mode 100644 index 000000000000..c340fb30e775 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3229.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "rk322x.dtsi" + +/ { + compatible = "rockchip,rk3229"; + + /delete-node/ opp-table0; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1325000>; + }; + opp-1392000000 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <1375000>; + }; + opp-1464000000 { + opp-hz = /bits/ 64 <1464000000>; + opp-microvolt = <1400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi new file mode 100644 index 000000000000..ffc16d6b97e1 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -0,0 +1,1295 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + spi0 = &spi0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + enable-method = "psci"; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + i2s1: i2s1@100b0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100b0000 0x4000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; + + i2s0: i2s0@100c0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100c0000 0x4000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + dmas = <&pdma 11>, <&pdma 12>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spdif: spdif@100d0000 { + compatible = "rockchip,rk3228-spdif"; + reg = <0x100d0000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 10>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + + i2s2: i2s2@100e0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100e0000 0x4000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + grf: syscon@11000000 { + compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; + reg = <0x11000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3228-io-voltage-domain"; + status = "disabled"; + }; + + power: power-controller { + compatible = "rockchip,rk3228-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3228_PD_VIO { + reg = ; + clocks = <&cru ACLK_HDCP>, + <&cru SCLK_HDCP>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA>; + pm_qos = <&qos_hdcp>, + <&qos_iep>, + <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VOP { + reg = ; + clocks =<&cru ACLK_VOP>, + <&cru DCLK_VOP>, + <&cru HCLK_VOP>; + pm_qos = <&qos_vop>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_RKVDEC { + reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, + <&qos_rkvdec_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + + u2phy0: usb2phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2phy@800 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0800 0x0c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + uart0: serial@11010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11010000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@11020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11020000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@11030000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11030000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + efuse: efuse@11040000 { + compatible = "rockchip,rk3228-efuse"; + reg = <0x11040000 0x20>; + clocks = <&cru PCLK_EFUSE_256>; + clock-names = "pclk_efuse"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x7 0x10>; + }; + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + i2c0: i2c@11050000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11050000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@11060000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11060000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@11070000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11070000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@11080000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11080000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + spi0: spi@11090000 { + compatible = "rockchip,rk3228-spi"; + reg = <0x11090000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; + status = "disabled"; + }; + + wdt: watchdog@110a0000 { + compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; + reg = <0x110a0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_CPU>; + status = "disabled"; + }; + + pwm0: pwm@110b0000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm@110b0010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm@110b0020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm@110b0030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + timer: timer@110c0000 { + compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; + reg = <0x110c0000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + cru: clock-controller@110e0000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x110e0000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; + }; + + pdma: dma-controller@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@11150000 { + compatible = "rockchip,rk3228-tsadc"; + reg = <0x11150000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <32768>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_pin>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + hdmi_phy: hdmi-phy@12030000 { + compatible = "rockchip,rk3228-hdmi-phy"; + reg = <0x12030000 0x10000>; + clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + #clock-cells = <0>; + clock-output-names = "hdmiphy_phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@20000000 { + compatible = "rockchip,rk3228-mali", "arm,mali-400"; + reg = <0x20000000 0x10000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + power-domains = <&power RK3228_PD_GPU>; + resets = <&cru SRST_GPU_A>; + status = "disabled"; + }; + + vpu: video-codec@20020000 { + compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; + reg = <0x20020000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3228_PD_VPU>; + }; + + vpu_mmu: iommu@20020800 { + compatible = "rockchip,iommu"; + reg = <0x20020800 0x100>; + interrupts = ; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VPU>; + #iommu-cells = <0>; + }; + + vdec: video-codec@20030000 { + compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; + reg = <0x20030000 0x480>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <300000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3228_PD_RKVDEC>; + }; + + vdec_mmu: iommu@20030480 { + compatible = "rockchip,iommu"; + reg = <0x20030480 0x40>, <0x200304c0 0x40>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_RKVDEC>; + #iommu-cells = <0>; + }; + + vop: vop@20050000 { + compatible = "rockchip,rk3228-vop"; + reg = <0x20050000 0x1ffc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + power-domains = <&power RK3228_PD_VOP>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@20053f00 { + compatible = "rockchip,iommu"; + reg = <0x20053f00 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VOP>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga: rga@20060000 { + compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; + reg = <0x20060000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3228_PD_VIO>; + resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; + reset-names = "core", "axi", "ahb"; + }; + + iep_mmu: iommu@20070800 { + compatible = "rockchip,iommu"; + reg = <0x20070800 0x100>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@200a0000 { + compatible = "rockchip,rk3228-dw-hdmi"; + reg = <0x200a0000 0x20000>; + reg-io-width = <4>; + interrupts = ; + assigned-clocks = <&cru SCLK_HDMI_PHY>; + assigned-clock-parents = <&hdmi_phy>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + resets = <&cru SRST_HDMI_P>; + reset-names = "hdmi"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + + sdmmc: mmc@30000000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30000000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "disabled"; + }; + + sdio: mmc@30010000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30010000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + status = "disabled"; + }; + + emmc: mmc@30020000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30020000 0x4000>; + interrupts = ; + clock-frequency = <37500000>; + max-frequency = <37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <8>; + rockchip,default-sample-phase = <158>; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + usb_otg: usb@30040000 { + compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x30040000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@30080000 { + compatible = "generic-ehci"; + reg = <0x30080000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@300a0000 { + compatible = "generic-ohci"; + reg = <0x300a0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@300c0000 { + compatible = "generic-ehci"; + reg = <0x300c0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@300e0000 { + compatible = "generic-ohci"; + reg = <0x300e0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ehci: usb@30100000 { + compatible = "generic-ehci"; + reg = <0x30100000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ohci: usb@30120000 { + compatible = "generic-ohci"; + reg = <0x30120000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + gmac: ethernet@30200000 { + compatible = "rockchip,rk3228-gmac"; + reg = <0x30200000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + qos_iep: qos@31030080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030080 0x20>; + }; + + qos_rga_w: qos@31030100 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030100 0x20>; + }; + + qos_hdcp: qos@31030180 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030180 0x20>; + }; + + qos_rga_r: qos@31030200 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030200 0x20>; + }; + + qos_vpu: qos@31040000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31040000 0x20>; + }; + + qos_gpu: qos@31050000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31050000 0x20>; + }; + + qos_vop: qos@31060000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31060000 0x20>; + }; + + qos_rkvdec_r: qos@31070000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070000 0x20>; + }; + + qos_rkvdec_w: qos@31070080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070080 0x20>; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x2000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@11110000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11110000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@11120000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11120000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@11130000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11130000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@11140000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11140000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC5 2 &pcfg_pull_none>, + <2 RK_PC4 2 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + phy_pins: phy-pins { + rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, + <2 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB1 1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB5 1 &pcfg_pull_none>, + <0 RK_PB6 1 &pcfg_pull_none>, + <1 RK_PA2 2 &pcfg_pull_none>, + <1 RK_PA4 2 &pcfg_pull_none>, + <1 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_pin: otp-pin { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, + <2 RK_PD3 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + uart21_xfer: uart21-xfer { + rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts new file mode 100644 index 000000000000..8a635c243127 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3288-evb.dtsi" + +/ { + model = "Rockchip RK3288 EVB ACT8846"; + compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + regulator-name = "vcc_lcd"; + vin-supply = <&vcc_io>; + }; + + vcc_wl: vcc-wl { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwr>; + regulator-name = "vcc_wl"; + vin-supply = <&vcc_18>; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "VCCA_CODEC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_tp: REG8 { + regulator-name = "VCCA_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_pmu: REG9 { + regulator-name = "VCCIO_PMU"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&panel { + power-supply = <&vcc_lcd>; +}; + +&pinctrl { + lcd { + lcd_en: lcd-en { + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_pwr: wifi-pwr { + rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts new file mode 100644 index 000000000000..42384ea4ca21 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3288-evb.dtsi" + +/ { + model = "Rockchip RK3288 EVB RK808"; + compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; +}; + +&i2c0 { + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vccio_pmu>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&panel { + power-supply = <&vcc_lcd>; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi b/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi new file mode 100644 index 000000000000..382d2839cf47 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include "rk3288.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + button-menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <640000>; + }; + + button-esc { + label = "Esc"; + linux,code = ; + press-threshold-microvolt = <1000000>; + }; + + button-home { + label = "Home"; + linux,code = ; + press-threshold-microvolt = <1300000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + panel: panel { + compatible = "lg,lp079qx1-sp0v"; + backlight = <&backlight>; + enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lcd_cs>; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + key-power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_pwr>; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from + * vcc_io directly. Those boards won't be able to power cycle SD cards + * but it shouldn't hurt to toggle this pin there anyway. + */ + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&edp { + force-hpd; + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + backlight { + bl_en: bl-en { + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_cs: lcd-cs { + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on EVB board so bump up to 8ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_pwr: eth-phy-pwr { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts new file mode 100644 index 000000000000..135e8832141f --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2014, 2015 FUKAUMI Naoki + */ + +/dts-v1/; +#include "rk3288-firefly.dtsi" + +/ { + model = "Firefly-RK3288 Beta"; + compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; +}; + +&ir { + gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; +}; + +&pinctrl { + act8846 { + pmic_vsel: pmic-vsel { + rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi new file mode 100644 index 000000000000..36efa36b7190 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree file for Firefly Rockchip RK3288 Core board + * Copyright (c) 2016 Randy Li + */ + +#include +#include "rk3288.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_lan: REG9 { + regulator-name = "vcca_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vccio_wl: vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vccio_wl>; + bb-supply = <&vcc_io>; + dvp-supply = <&dovdd_1v8>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pwr_hold: pwr-hold { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + pmic_vsel: pmic-vsel { + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts new file mode 100644 index 000000000000..a5a0826341e6 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree file for Firefly Rockchip RK3288 Core board + * Copyright (c) 2016 Randy Li + */ + +/dts-v1/; +#include "rk3288-firefly-reload-core.dtsi" + +/ { + model = "Firefly-RK3288-reload"; + compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + wakeup-source; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + power_led: led-0 { + gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; + label = "firefly:blue:power"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led_pin>; + panic-indicator; + }; + + work_led: led-1 { + gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; + label = "firefly:blue:user"; + linux,default-trigger = "rc-feedback"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_pin>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ + cpu { sound-dai = <&spdif>; }; + codec { sound-dai = <&spdif_out>; }; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc_host_5v: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + vcc_5v: vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + dovdd_1v8: dovdd-1v8-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "dovdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc28_dvp: vcc28-dvp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "vcc28_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + af_28: af_28-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "af_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + dvdd_1v2: af_28-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_pwr>; + regulator-name = "dvdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_io>; + }; + + vbat_wl: wifi-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; + status = "okay"; +}; + +&i2c0 { + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio7>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; +}; + +&i2c2 { + status = "okay"; + + codec: es8328@10 { + compatible = "everest,es8328"; + DVDD-supply = <&vcca_33>; + AVDD-supply = <&vcca_33>; + PVDD-supply = <&vcca_33>; + HPVDD-supply = <&vcca_33>; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + clock-names = "i2s_hclk", "i2s_clk"; + reg = <0x10>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2s { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + vmmc-supply = <&vbat_wl>; + vqmmc-supply = <&vccio_wl>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&usbhub_rst>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif_pwr: cif-pwr { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + power_led_pin: power-led-pin { + rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led_pin: work-led-pin { + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbhub_rst: usbhub-rst { + rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly.dts new file mode 100644 index 000000000000..313459dab2e4 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2014, 2015 FUKAUMI Naoki + */ + +/dts-v1/; +#include "rk3288-firefly.dtsi" + +/ { + model = "Firefly-RK3288"; + compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; +}; + +&ir { + gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; +}; + +&pinctrl { + act8846 { + pmic_vsel: pmic-vsel { + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi new file mode 100644 index 000000000000..3836c61cfb76 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2014, 2015 FUKAUMI Naoki + */ + +#include +#include "rk3288.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + dovdd_1v8: dovdd-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "dovdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc28_dvp>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + + key-power { + wakeup-source; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + leds { + compatible = "gpio-leds"; + + work_led: led-0 { + gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; + label = "firefly:blue:user"; + linux,default-trigger = "rc-feedback"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_pin>; + }; + + power_led: led-1 { + gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; + label = "firefly:green:power"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led_pin>; + }; + }; + + vbat_wl: vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_5v: usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host_5v: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + /* + * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled + * by the dvp_pwr pin. + */ + vcc28_dvp: vcc28-dvp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "vcc28_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio7>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcca_33: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_lan: REG9 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vccio_wl: vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&dovdd_1v8>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pwr_hold: pwr-hold { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + power_led_pin: power-led-pin { + rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led_pin: work-led-pin { + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbhub_rst: usbhub-rst { + rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; + vmmc-supply = <&vbat_wl>; + vqmmc-supply = <&vccio_wl>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&usbhub_rst>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts new file mode 100644 index 000000000000..db1eb648e0e1 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Heiko Stuebner + */ + +/dts-v1/; +#include +#include "rk3288.dtsi" + +/ { + model = "mqmaker MiQi"; + compatible = "mqmaker,miqi", "rockchip,rk3288"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + leds { + compatible = "gpio-leds"; + + work_led: led-0 { + gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "miqi:green:user"; + linux,default-trigger = "timer"; + }; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcca_33: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_lan: REG9 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_vsel: pmic-vsel { + rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + /* + * The otg controller is the only system power source, + * so needs to always stay in device mode. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts new file mode 100644 index 000000000000..1a5156951492 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree file for Phytec PCM-947 carrier board + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +/dts-v1/; + +#include +#include +#include "rk3288-phycore-som.dtsi" + +/ { + model = "Phytec RK3288 PCM-947"; + compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; + + user_buttons: user-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_button_pins>; + + button-0 { + label = "home"; + linux,code = ; + gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + button-1 { + label = "menu"; + linux,code = ; + gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + }; + + vcc_host0_5v: usb-host0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host0_vbus_drv>; + regulator-name = "vcc_host0_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; + + vcc_host1_5v: usb-host1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host1_vbus_drv>; + regulator-name = "vcc_host1_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; +}; + +&gmac { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + }; + + adc@64 { + compatible = "maxim,max1037"; + reg = <0x64>; + }; + + i2c_rtc: rtc@68 { + compatible = "rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_rtc_int>; + interrupt-parent = <&gpio5>; + interrupts = <10 0>; + }; +}; + +&i2c3 { + status = "okay"; + + i2c_eeprom_cb: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c4 { + status = "okay"; + + /* PCA9533 - 4-bit LED dimmer */ + leddim: leddimmer@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led1 { + label = "red:user1"; + linux,default-trigger = "none"; + type = ; + }; + + led2 { + label = "green:user2"; + linux,default-trigger = "none"; + type = ; + }; + + led3 { + label = "blue:user3"; + linux,default-trigger = "none"; + type = ; + }; + + led4 { + label = "red:user4"; + linux,default-trigger = "none"; + type = ; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + buttons { + user_button_pins: user-button-pins { + /* button 1 */ + rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* button 2 */ + <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rv4162 { + i2c_rtc_int: i2c-rtc-int { + rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on pcm-947 board so bump up to 12 mA. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + ts_irq_pin: ts-irq-pin { + rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host0_vbus_drv: host0-vbus-drv { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host1_vbus_drv: host1-vbus-drv { + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&vdd_io_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi new file mode 100644 index 000000000000..e43887c9635f --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree file for Phytec phyCORE-RK3288 SoM + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#include +#include "rk3288.dtsi" + +/ { + model = "Phytec RK3288 phyCORE"; + compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x8000000>; + }; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &rk818; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + + user_led: led-0 { + label = "green_led"; + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "keep"; + }; + }; + + vdd_emmc_io: vdd-emmc-io { + compatible = "regulator-fixed"; + regulator-name = "vdd_emmc_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3_io>; + }; + + vdd_in_otg_out: vdd-in-otg-out { + compatible = "regulator-fixed"; + regulator-name = "vdd_in_otg_out"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_misc_1v8: vdd-misc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_misc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vdd_3v3_io>; + vqmmc-supply = <&vdd_emmc_io>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; + phy-handle = <&phy0>; + phy-supply = <&vdd_eth_2v5>; + phy-mode = "rgmii-id"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + tx_delay = <0x0>; + rx_delay = <0x0>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; +}; + +&io_domains { + status = "okay"; + sdcard-supply = <&vdd_io_sd>; + flash0-supply = <&vdd_emmc_io>; + flash1-supply = <&vdd_misc_1v8>; + gpio1830-supply = <&vdd_3v3_io>; + gpio30-supply = <&vdd_3v3_io>; + bb-supply = <&vdd_3v3_io>; + dvp-supply = <&vdd_3v3_io>; + lcdc-supply = <&vdd_3v3_io>; + wifi-supply = <&vdd_3v3_io>; + audio-supply = <&vdd_3v3_io>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vdd_sys>; + vcc2-supply = <&vdd_sys>; + vcc3-supply = <&vdd_sys>; + vcc4-supply = <&vdd_sys>; + boost-supply = <&vdd_in_otg_out>; + vcc6-supply = <&vdd_sys>; + vcc7-supply = <&vdd_misc_1v8>; + vcc8-supply = <&vdd_misc_1v8>; + vcc9-supply = <&vdd_3v3_io>; + vddio-supply = <&vdd_3v3_io>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_3v3_io: DCDC_REG4 { + regulator-name = "vdd_3v3_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_sys: DCDC_BOOST { + regulator-name = "vdd_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + /* vcc9 */ + vdd_sd: SWITCH_REG { + regulator-name = "vdd_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* vcc6 */ + vdd_eth_2v5: LDO_REG2 { + regulator-name = "vdd_eth_2v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2500000>; + }; + }; + + /* vcc7 */ + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + /* vcc8 */ + vdd_1v8_lcd_ldo: LDO_REG4 { + regulator-name = "vdd_1v8_lcd_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* vcc8 */ + vdd_1v0_lcd: LDO_REG6 { + regulator-name = "vdd_1v0_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + /* vcc7 */ + vdd_1v8_ldo: LDO_REG7 { + regulator-name = "vdd_1v8_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* vcc9 */ + vdd_io_sd: LDO_REG9 { + regulator-name = "vdd_io_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + /* M24C32-D */ + i2c_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + vdd_cpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1430000>; + regulator-ramp-delay = <8000>; + vin-supply = <&vdd_sys>; + }; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>, + <3 RK_PA1 2 &pcfg_pull_none_12ma>, + <3 RK_PA2 2 &pcfg_pull_none_12ma>, + <3 RK_PA3 2 &pcfg_pull_none_12ma>, + <3 RK_PA4 2 &pcfg_pull_none_12ma>, + <3 RK_PA5 2 &pcfg_pull_none_12ma>, + <3 RK_PA6 2 &pcfg_pull_none_12ma>, + <3 RK_PA7 2 &pcfg_pull_none_12ma>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + leds { + user_led_pin: user-led-pin { + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* Pin for switching state between sleep and non-sleep state */ + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_ldo>; +}; + +&spi2 { + status = "okay"; + + serial_flash: flash@0 { + compatible = "micron,n25q128a13", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-popmetal.dts b/arch/arm/boot/dts/rockchip/rk3288-popmetal.dts new file mode 100644 index 000000000000..fd90f3b8fc32 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-popmetal.dts @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2014, 2015 Andy Yan + */ + +/dts-v1/; +#include +#include "rk3288.dtsi" + +/ { + model = "PopMetal-RK3288"; + compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + key-power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled + * by the dvp_pwr pin. + */ + vcc18_dvp: vcc18-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc18-dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc28_dvp>; + }; + + vcc28_dvp: vcc28-dvp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "vcc28_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lan: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + ldo5: LDO_REG5 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ldo5"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_33: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + ak8963: ak8963@d { + compatible = "asahi-kasei,ak8975"; + reg = <0x0d>; + interrupt-parent = <&gpio8>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&comp_int>; + vdd-supply = <&vcc_io>; + vid-supply = <&vcc_io>; + }; + + l3g4200d: l3g4200d@69 { + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x69>; + vdd-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + }; + + mma8452: mma8452@1d { + compatible = "fsl,mma8452"; + reg = <0x1d>; + interrupt-parent = <&gpio8>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc18_dvp>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pinctrl { + ak8963 { + comp_int: comp-int { + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + mma8452 { + gsensor_int: gsensor-int { + rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-r89.dts b/arch/arm/boot/dts/rockchip/rk3288-r89.dts new file mode 100644 index 000000000000..633e5a032463 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-r89.dts @@ -0,0 +1,400 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2015 Heiko Stuebner + */ + +/dts-v1/; +#include +#include +#include "rk3288.dtsi" + +/ { + model = "Netxeon R89"; + compatible = "netxeon,r89", "rockchip,rk3288"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + key-power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_otg: vcc-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sdmmc: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "sys-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: pmic@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "VDD_CPU"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: pmic@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "VDD_GPU"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + }; + + act8846: pmic@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; + system-power-controller; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_wl: REG7 { + regulator-name = "VCC_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_lan: REG9 { + regulator-name = "VCC_LAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + pmic_vsel: pmic-vsel { + rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pwr_hold: pwr-hold { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sdmmc>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts new file mode 100644 index 000000000000..673466d264be --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3288.dtsi" +#include +#include "rk3288-vmarc-som.dtsi" + +/ { + model = "Radxa ROCK Pi N8"; + compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", + "rockchip,rk3288"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi new file mode 100644 index 000000000000..76363b8afcb9 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include "rk3288.dtsi" + +/ { + memory@0 { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <150>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vccio_pmu>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &phy_rst>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; + rx_delay = <0x10>; + tx_delay = <0x30>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + system-power-controller; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: vccio_codec: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "VCCA_CODEC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcca_tp: REG8 { + regulator-name = "VCCA_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_pmu: REG9 { + regulator-name = "VCCIO_PMU"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcc_io>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vccio_pmu>; + gpio30-supply = <&vccio_pmu>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts b/arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts new file mode 100644 index 000000000000..13cfdaa95cc7 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include "rk3288-rock2-som.dtsi" + +/ { + model = "Radxa Rock 2 Square"; + compatible = "radxa,rock2-square", "rockchip,rk3288"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + heartbeat_led: led-0 { + gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; + label = "rock2:green:state1"; + linux,default-trigger = "heartbeat"; + }; + + mmc_led: led-1 { + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + label = "rock2:blue:state2"; + linux,default-trigger = "mmc0"; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ + cpu { sound-dai = <&spdif>; }; + codec { sound-dai = <&spdif_out>; }; + }; + }; + + sata_pwr: sata-prw-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sata_pwr_en>; + /* Always turn on the 5V sata power connector */ + regulator-always-on; + regulator-name = "sata_pwr"; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sound-i2s { + compatible = "rockchip,rk3288-hdmi-analog"; + pinctrl-names = "default"; + pinctrl-0 = <&phone_ctl>, <&hp_det>; + rockchip,audio-codec = <&es8388>; + rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; + rockchip,i2s-controller = <&i2s>; + rockchip,model = "I2S"; + rockchip,routing = "Analog", "LOUT2", + "Analog", "ROUT2"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc_usb_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&gmac { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + + }; +}; + +&i2c2 { + status = "okay"; + + es8388: es8388@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + AVDD-supply = <&vccio_codec>; + DVDD-supply = <&vccio_codec>; + HPVDD-supply = <&vccio_codec>; + PVDD-supply = <&vccio_codec>; + clocks = <&cru SCLK_I2S0_OUT>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2s { + status = "okay"; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + phone_ctl: phone-ctl { + rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + sata_pwr_en: sata-pwr-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usbphy1 { + vbus-supply = <&vcc_usb_host>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts new file mode 100644 index 000000000000..970e13859198 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3288-tinker.dtsi" + +/ { + model = "Rockchip RK3288 Asus Tinker Board S"; + compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + max-frequency = <150000000>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts new file mode 100644 index 000000000000..1e43527aa196 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3288-tinker.dtsi" + +/ { + model = "Rockchip RK3288 Asus Tinker Board"; + compatible = "asus,rk3288-tinker", "rockchip,rk3288"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi new file mode 100644 index 000000000000..09618bb7d872 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include "rk3288.dtsi" +#include +#include + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + act_led: led-0 { + gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + heartbeat_led: led-1 { + gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + pwr_led: led-2 { + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>, + <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,tinker-codec"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&cpu_opp_table { + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <1350000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1400000>; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc33_lan>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, + <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd_arm"; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc18_ldo1: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_ldo1"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_mipi: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_mipi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_codec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc33_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lan"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2s { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + backlight { + bl_en: bl-en { + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + eth_phy { + eth_phy_pwr: eth-phy-pwr { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dvs_1: dvs-1 { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pwr_3g: pwr-3g { + rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc18_ldo1>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + broken-cd; + disable-wp; /* wp not hooked up */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; + vmmc-supply = <&vcc33_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi new file mode 100644 index 000000000000..51208d161d65 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Veyron (and derivatives) fragment for the max98090 audio + * codec and analog headphone jack. + * + * Copyright 2016 Google, Inc + */ + +/ { + sound { + compatible = "rockchip,rockchip-audio-max98090"; + pinctrl-names = "default"; + pinctrl-0 = <&mic_det>, <&hp_det>; + rockchip,model = "VEYRON-I2S"; + rockchip,i2s-controller = <&i2s>; + rockchip,audio-codec = <&max98090>; + rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>; + rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>; + rockchip,headset-codec = <&headsetcodec>; + rockchip,hdmi-codec = <&hdmi>; + }; +}; + +&i2c2 { + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = ; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&int_codec>; + }; +}; + +&i2c4 { + headsetcodec: ts3a227e@3b { + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&ts3a227e_int_l>; + ti,micbias = <7>; /* MICBIAS = 2.8V */ + }; +}; + +&i2s { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcc18_codec>; +}; + +&rk808 { + vcc10-supply = <&vcc33_sys>; + + regulators { + vcc18_codec: LDO_REG6 { + regulator-name = "vcc18_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&pinctrl { + codec { + hp_det: hp-det { + rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* + * HACK: We're going to _pull down_ this _active low_ interrupt + * so that it never fires. We don't need this interrupt because + * we've got a ts3a227e chip but the driver requires it. + */ + int_codec: int-codec { + rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + mic_det: mic-det { + rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headset { + ts3a227e_int_l: ts3a227e-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts new file mode 100644 index 000000000000..aa33d09184ad --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Brain Rev 0 board device tree source + * + * Copyright 2014 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron.dtsi" +#include "rk3288-veyron-broadcom-bluetooth.dtsi" + +/ { + model = "Google Brain"; + compatible = "google,veyron-brain-rev0", "google,veyron-brain", + "google,veyron", "rockchip,rk3288"; + + vcc33_sys: vcc33-sys { + vin-supply = <&vcc_5v>; + }; + + vcc33_io: vcc33_io { + compatible = "regulator-fixed"; + regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc33_sys>; + /* This is gated by vcc_18 too */ + }; + + /* This turns on vbus for host2 and otg (dwc2) */ + vcc5_host2: vcc5-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pwr_en>; + regulator-name = "vcc5_host2"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + >; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb-host { + usb2_pwr_en: usb2-pwr-en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>, + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; + + /delete-property/ vcc6-supply; + + regulators { + /* vcc33_io is sourced directly from vcc33_sys */ + /delete-node/ LDO_REG1; + + /* This is not a pwren anymore, but the real power supply */ + vdd10_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-suspend-mem-disabled; + }; + + vcc18_hdmi: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc18_hdmi"; + regulator-suspend-mem-disabled; + }; + }; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi new file mode 100644 index 000000000000..f9dde0eef527 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth + * chip. + * + * Copyright 2019 Google, Inc + */ + +&uart0 { + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>, + <&bt_dev_wake>; + + compatible = "brcm,bcm43540-bt"; + host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + brcm,bt-pcm-int-params = [01 02 00 01 01]; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi new file mode 100644 index 000000000000..092316be67f7 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron (and derivatives) board device tree source + * Chromebook specific parts + * + * Copyright 2015 Google, Inc + */ + +#include +#include +#include "rk3288-veyron.dtsi" +#include "rk3288-veyron-analog-audio.dtsi" +#include "rk3288-veyron-edp.dtsi" +#include "rk3288-veyron-sdmmc.dtsi" + +/ { + aliases { + /* Assign 20 so we don't get confused w/ builtin ones */ + i2c20 = &i2c_tunnel; + }; + + gpio-charger { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ac_present_ap>; + }; + + lid_switch: lid-switch { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&ap_lid_int_l>; + + switch-lid { + label = "Lid"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + linux,input-type = ; + debounce-interval = <1>; + }; + }; + + /* A non-regulated voltage from power supply or battery */ + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vccsys"; + regulator-boot-on; + regulator-always-on; + }; + + vcc33_sys: vcc33-sys { + vin-supply = <&vccsys>; + }; + + vcc_5v: vcc-5v { + vin-supply = <&vccsys>; + }; + + /* This turns on vbus for host1 (dwc2) */ + vcc5_host1: vcc5-host1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host1_pwr_en>; + regulator-name = "vcc5_host1"; + regulator-always-on; + regulator-boot-on; + }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host2"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&rk808 { + vcc11-supply = <&vcc_5v>; + + regulators { + vcc33_ccd: LDO_REG8 { + regulator-name = "vcc33_ccd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + google,cros-ec-spi-pre-delay = <30>; + interrupt-parent = <&gpio7>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&ec_int>; + spi-max-frequency = <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c4 { + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio7>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int>; + vcc-supply = <&vcc33_io>; + wakeup-source; + }; +}; + +&pinctrl { + buttons { + ap_lid_int_l: ap-lid-int-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + charger { + ac_present_ap: ac-present-ap { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + cros-ec { + ec_int: ec-int { + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + suspend { + suspend_l_wake: suspend-l-wake { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + suspend_l_sleep: suspend-l-sleep { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + trackpad { + trackpad_int: trackpad-int { + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-host { + host1_pwr_en: host1-pwr-en { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbotg_pwren_h: usbotg-pwren-h { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi new file mode 100644 index 000000000000..32c0f10765dd --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron (and derivatives) fragment for the edp displays + * + * Copyright 2019 Google LLC + */ + +/ { + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 0>; + post-pwm-on-delay-ms = <10>; + pwm-off-delay-ms = <10>; + power-supply = <&backlight_regulator>; + }; + + panel: panel { + compatible = "innolux,n116bge"; + status = "okay"; + power-supply = <&panel_regulator>; + backlight = <&backlight>; + + panel-timing { + clock-frequency = <74250000>; + hactive = <1366>; + hfront-porch = <136>; + hback-porch = <60>; + hsync-len = <30>; + hsync-active = <0>; + vactive = <768>; + vfront-porch = <8>; + vback-porch = <12>; + vsync-len = <12>; + vsync-active = <0>; + }; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts new file mode 100644 index 000000000000..309b122b4d0d --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Fievel Rev 0+ board device tree source + * + * Copyright 2016 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron.dtsi" +#include "rk3288-veyron-analog-audio.dtsi" + +/ { + model = "Google Fievel"; + compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7", + "google,veyron-fievel-rev6", "google,veyron-fievel-rev5", + "google,veyron-fievel-rev4", "google,veyron-fievel-rev3", + "google,veyron-fievel-rev2", "google,veyron-fievel-rev1", + "google,veyron-fievel-rev0", "google,veyron-fievel", + "google,veyron", "rockchip,rk3288"; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vccsys"; + regulator-boot-on; + regulator-always-on; + }; + + /* + * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys, + * enabled by vcc_18 + */ + vcc33_io: vcc33-io { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_io"; + }; + + vcc5_host1: vcc5-host1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_usb1_pwr_en>; + regulator-name = "vcc5_host1"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5_host2: vcc5-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_usb2_pwr_en>; + regulator-name = "vcc5_host2"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwr_en>; + regulator-name = "vcc5_otg"; + regulator-always-on; + regulator-boot-on; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; +}; + +&gmac { + status = "okay"; + + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-supply = <&vcc33_lan>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + rx_delay = <0x10>; + tx_delay = <0x30>; + + /* + * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low) + * with a 30ms settling time. + */ + snps,reset-gpio = <&gpio4 RK_PB0 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; + wakeup-source; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&rk808 { + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + + vcc6-supply = <&vcc33_sys>; + vcc10-supply = <&vcc33_sys>; + vcc11-supply = <&vcc_5v>; + vcc12-supply = <&vcc33_sys>; + + regulators { + /delete-node/ LDO_REG1; + + /* + * According to the schematic, vcc18_lcdt is for + * HDMI_AVDD_1V8 + */ + vcc18_lcdt: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd18_lcdt"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * This is not a pwren anymore, but the real power supply, + * vdd10_lcd for HDMI_AVDD_1V0 + */ + vdd10_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* for usb camera */ + vcc33_ccd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_ccd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc33_lan: SWITCH_REG2 { + regulator-name = "vcc33_lan"; + }; + }; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = ; + marvell,wakeup-pin = /bits/ 16 <13>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + }; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "HUB_USB1_nFALUT", + "PHY_PMEB", + + "PHY_INT", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "", + "USB_OTG_POWER_EN", + "AP_WARM_RESET_H", + "USB_OTG_nFALUT", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "DEVMODE_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "", + "TOUCH_INT", + "TOUCH_RST", + + "I2C3_SCL_TP", + "I2C3_SDA_TP"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "VCC5V_GOOD_H", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO", + "", + "", + "", + "", + "", + + "PHY_TXD2", + "PHY_TXD3", + "MAC_RXD2", + "MAC_RXD3", + "PHY_TXD0", + "PHY_TXD1", + "MAC_RXD0", + "MAC_RXD1"; +}; + +&gpio4 { + gpio-line-names = "MAC_MDC", + "MAC_RXDV", + "MAC_RXER", + "MAC_CLK", + "PHY_TXEN", + "MAC_MDIO", + "MAC_RXCLK", + "", + + "PHY_RST", + "PHY_TXCLK", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS_L", + "UART0_RTS_L", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "USB_OTG_CTL1", + "HUB_USB2_CTL1", + "HUB_USB2_PWR_EN", + "HUB_USB_ILIM_SEL", + + "USB_OTG_STATUS_L", + "HUB_USB1_CTL1", + "HUB_USB1_PWR_EN", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "HUB_USB2_nFALUT", + "USB_OTG_ILIM_SEL"; +}; + +&gpio7 { + gpio-line-names = "LCD_BL_PWM", + "PWM_LOG", + "BL_EN", + "PWR_LED1", + "TPM_INT_H", + "SPK_ON", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "", + + "CPU_NMI", + "DVSOK", + "", + "EDP_HPD", + "DVS1", + "", + "LCD_EN", + "DVS2", + + "HDMI_CEC", + "I2C4_SDA", + "I2C4_SCL", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* For usb bc1.2 */ + &usb_otg_ilim_sel + &usb_usb_ilim_sel + + /* Wake only */ + &bt_dev_wake_awake + &pwr_led1_on + >; + + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* For usb bc1.2 */ + &usb_otg_ilim_sel + &usb_usb_ilim_sel + + /* Sleep only */ + &bt_dev_wake_sleep + &pwr_led1_blink + >; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_int: phy-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + pwr_led1_on: pwr-led1-on { + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pwr_led1_blink: pwr-led1-blink { + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb-bc12 { + usb_otg_ilim_sel: usb-otg-ilim-sel { + rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + usb_usb_ilim_sel: usb-usb-ilim-sel { + rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + usb-host { + hub_usb1_pwr_en: hub_usb1_pwr_en { + rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hub_usb2_pwr_en: hub_usb2_pwr_en { + rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwr_en: usb_otg_pwr_en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts new file mode 100644 index 000000000000..0d4c50e05558 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Jaq Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; + +#include "rk3288-veyron-chromebook.dtsi" +#include "../cros-ec-sbs.dtsi" + +/ { + model = "Google Jaq"; + compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", + "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", + "google,veyron-jaq-rev1", "google,veyron-jaq", + "google,veyron", "rockchip,rk3288"; +}; + +&backlight { + /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ + brightness-levels = <8 255>; + num-interpolated-steps = <247>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; + + regulators { + mic_vcc: LDO_REG2 { + regulator-name = "mic_vcc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = ; + marvell,wakeup-pin = /bits/ 16 <13>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFALUT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", /* Maybe missing from mighty? */ + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "ALS_INT", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVSOK", + "SDMMC_WP", /* mighty only */ + "EDP_HPD", + "DVS1", + "nFALUT1", /* nFAULT1 on jaq */ + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Wake only */ + &suspend_l_wake + &bt_dev_wake_awake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Sleep only */ + &suspend_l_sleep + &bt_dev_wake_sleep + >; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts new file mode 100644 index 000000000000..6894763979f0 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Jerry Rev 3+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "../cros-ec-sbs.dtsi" + +/ { + model = "Google Jerry"; + compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", + "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", + "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", + "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", + "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", + "google,veyron-jerry-rev3", "google,veyron-jerry", + "google,veyron", "rockchip,rk3288"; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; + + regulators { + mic_vcc: LDO_REG2 { + regulator-name = "mic_vcc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + + mwifiex: wifi@1 { + compatible = "marvell,sd8897"; + reg = <1>; + + marvell,caldata-txpwrlimit-2g = /bits/ 8 < +0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 +0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c +0x0d 0x09 0x0e 0x09 0x0f 0x09>; + + marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 < +0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01 +0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a +0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 +0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a +0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 +0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 +0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 +0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 +0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30 +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 +0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 +0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c +0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 +0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 +0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 +0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c +0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a +0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 +0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 +0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c +0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a +0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 +0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 +0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a +0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 +0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; + + marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 < +0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01 +0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a +0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 +0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a +0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 +0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 +0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 +0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 +0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70 +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 +0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 +0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 +0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c +0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 +0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 +0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 +0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c +0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a +0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 +0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 +0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c +0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a +0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 +0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 +0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a +0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 +0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 +0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a +0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 +0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a +0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 +0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 +0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 +0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 +0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; + + marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 < +0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01 +0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a +0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 +0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 +0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 +0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a +0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 +0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 +0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 +0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 +0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 +0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1 +0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 +0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 +0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 +0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b +0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 +0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 +0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 +0x1a 0x05 0x1b 0x05>; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFAULT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVSOK", + "", + "EDP_HPD", + "DVS1", + "nFAULT1", + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Wake only */ + &suspend_l_wake + &bt_dev_wake_awake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Sleep only */ + &suspend_l_sleep + &bt_dev_wake_sleep + >; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /* + * Trackpad pin control is shared between Elan and Synaptics devices + * so we have to pull it up to the bus level. + */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer &trackpad_int>; + + trackpad@15 { + /* + * Remove the inherited pinctrl settings to avoid clashing + * with bus-wide ones. + */ + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + }; + + trackpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&gpio7>; + interrupts = ; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + vcc-supply = <&vcc33_io>; + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts new file mode 100644 index 000000000000..ffd1121d19be --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Mickey Rev 0 board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron.dtsi" +#include "rk3288-veyron-broadcom-bluetooth.dtsi" + +/ { + model = "Google Mickey"; + compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", + "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", + "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", + "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", + "google,veyron-mickey-rev0", "google,veyron-mickey", + "google,veyron", "rockchip,rk3288"; + + vcc_5v: vcc-5v { + vin-supply = <&vcc33_sys>; + }; + + vcc33_io: vcc33_io { + compatible = "regulator-fixed"; + regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc33_sys>; + }; + + sound { + compatible = "rockchip,rockchip-audio-max98090"; + rockchip,model = "VEYRON-HDMI"; + rockchip,hdmi-codec = <&hdmi>; + rockchip,i2s-controller = <&i2s>; + }; +}; + +&cpu_thermal { + /delete-node/ trips; + /delete-node/ cooling-maps; + + trips { + cpu_alert_almost_warm: cpu_alert_almost_warm { + temperature = <63000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_warm: cpu_alert_warm { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_almost_hot: cpu_alert_almost_hot { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_hot: cpu_alert_hot { + temperature = <82000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_hotter: cpu_alert_hotter { + temperature = <84000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_very_hot: cpu_alert_very_hot { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * After 1st level, throttle the CPU down to as low as 1.4 GHz + * and don't let the GPU go faster than 400 MHz. + */ + cpu_warm_limit_cpu { + trip = <&cpu_alert_warm>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, + <&cpu1 THERMAL_NO_LIMIT 4>, + <&cpu2 THERMAL_NO_LIMIT 4>, + <&cpu3 THERMAL_NO_LIMIT 4>; + }; + cpu_warm_limit_gpu { + trip = <&cpu_alert_warm>; + cooling-device = <&gpu 1 1>; + }; + + /* + * Add some discrete steps to help throttling system deal + * with the fact that there are two passive cooling devices: + * the CPU and the GPU. + * + * - 1.2 GHz - 1.0 GHz (almost hot) + * - 800 MHz (hot) + * - 800 MHz - 696 MHz (hotter) + * - 696 MHz - min (very hot) + * + * Note: + * - 800 MHz appears to be a "sweet spot" for me. I can run + * some pretty serious workload here and be happy. + * - After 696 MHz we stop lowering voltage, so throttling + * past there is less effective. + */ + cpu_almost_hot_limit_cpu { + trip = <&cpu_alert_almost_hot>; + cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, + <&cpu3 5 6>; + }; + cpu_hot_limit_cpu { + trip = <&cpu_alert_hot>; + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, + <&cpu3 7 7>; + }; + cpu_hotter_limit_cpu { + trip = <&cpu_alert_hotter>; + cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, + <&cpu3 7 8>; + }; + cpu_very_hot_limit_cpu { + trip = <&cpu_alert_very_hot>; + cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, + <&cpu1 8 THERMAL_NO_LIMIT>, + <&cpu2 8 THERMAL_NO_LIMIT>, + <&cpu3 8 THERMAL_NO_LIMIT>; + }; + + /* At very hot, don't let GPU go over 300 MHz */ + cpu_very_hot_limit_gpu { + trip = <&cpu_alert_very_hot>; + cooling-device = <&gpu 2 2>; + }; + }; +}; + +&gpu_thermal { + /delete-node/ trips; + /delete-node/ cooling-maps; + + trips { + gpu_alert_warmish: gpu_alert_warmish { + temperature = <60000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert_warm: gpu_alert_warm { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert_hotter: gpu_alert_hotter { + temperature = <84000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert_very_very_hot: gpu_alert_very_very_hot { + temperature = <86000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* After 1st level throttle the GPU down to as low as 400 MHz */ + gpu_warmish_limit_gpu { + trip = <&gpu_alert_warmish>; + cooling-device = <&gpu THERMAL_NO_LIMIT 1>; + }; + + /* + * Slightly after we throttle the GPU, we'll also make sure that + * the CPU can't go faster than 1.4 GHz. Note that we won't + * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll + * let the CPU do the rest itself. + */ + gpu_warm_limit_cpu { + trip = <&gpu_alert_warm>; + cooling-device = <&cpu0 4 4>, + <&cpu1 4 4>, + <&cpu2 4 4>, + <&cpu3 4 4>; + }; + + /* When hot, GPU goes down to 300 MHz */ + gpu_hotter_limit_gpu { + trip = <&gpu_alert_hotter>; + cooling-device = <&gpu 2 2>; + }; + + /* When really hot, don't let GPU go _above_ 300 MHz */ + gpu_very_very_hot_limit_gpu { + trip = <&gpu_alert_very_very_hot>; + cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&i2s { + status = "okay"; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; + + /delete-property/ vcc6-supply; + /delete-property/ vcc12-supply; + + vcc11-supply = <&vcc33_sys>; + + regulators { + /* vcc33_io is sourced directly from vcc33_sys */ + /delete-node/ LDO_REG1; + /delete-node/ LDO_REG7; + + /* This is not a pwren anymore, but the real power supply */ + vdd10_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-suspend-mem-disabled; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-suspend-mem-disabled; + }; + }; +}; + +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "", + "", + "", + "PMIC_INT_L", + "POWER_BUTTON_L", + "", + "", + + "", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OT_RESET", + "", + "", + "AP_WARM_RESET_H", + "", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "", + "nFALUT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS_L", + "UART0_RTS_L", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio7 { + gpio-line-names = "", + "PWM_LOG", + "", + "", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "", + + "CPU_NMI", + "DVSOK", + "HDMI_WAKE", + "POWER_HDMI_ON", + "DVS1", + "", + "", + "DVS2", + + "HDMI_CEC", + "", + "", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + >; + + hdmi { + power_hdmi_on: power-hdmi-on { + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host1 { + status = "disabled"; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&power_hdmi_on>; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts new file mode 100644 index 000000000000..fa695a88f236 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Mighty Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; + +#include "rk3288-veyron-jaq.dts" + +/ { + model = "Google Mighty"; + compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4", + "google,veyron-mighty-rev3", "google,veyron-mighty-rev2", + "google,veyron-mighty-rev1", "google,veyron-mighty", + "google,veyron", "rockchip,rk3288"; +}; + +&sdmmc { + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_wp_pin &sdmmc_bus4>; + wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; + + /delete-property/ disable-wp; +}; + +&pinctrl { + sdmmc { + sdmmc_wp_pin: sdmmc-wp-pin { + rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts new file mode 100644 index 000000000000..dcdcc55c4098 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Minnie Rev 0+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "rk3288-veyron-broadcom-bluetooth.dtsi" + +/ { + model = "Google Minnie"; + compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", + "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", + "google,veyron-minnie-rev0", "google,veyron-minnie", + "google,veyron", "rockchip,rk3288"; + + volume_buttons: volume-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&volum_down_l &volum_up_l>; + + key-volum-down { + label = "Volum_down"; + gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; + + key-volum-up { + label = "Volum_up"; + gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; + }; +}; + +&backlight { + /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = <3 255>; + num-interpolated-steps = <252>; +}; + +&i2c_tunnel { + battery: bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; + vcc33-supply = <&vcc33_touch>; + vccio-supply = <&vcc33_touch>; + }; +}; + +&panel { + compatible = "auo,b101ean01"; + + /delete-node/ panel-timing; + + panel-timing { + clock-frequency = <66666667>; + hactive = <1280>; + hfront-porch = <18>; + hback-porch = <21>; + hsync-len = <32>; + vactive = <800>; + vfront-porch = <4>; + vback-porch = <8>; + vsync-len = <18>; + }; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + + regulators { + vcc33_touch: LDO_REG2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_touch: SWITCH_REG2 { + regulator-name = "vcc5v_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFALUT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "PROCHOT#", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN", + "TOUCH_INT", + "TOUCH_RST", + + "I2C3_SCL_TP", + "I2C3_SDA_TP"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "dev_wake", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "Volum_Up#", + "Volum_Down#", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVS_OK", + "SDMMC_WP", + "EDP_HPD", + "DVS1", + "nFALUT1", + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Wake only */ + &suspend_l_wake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Sleep only */ + &suspend_l_sleep + >; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + volum_down_l: volum-down-l { + rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + volum_up_l: volum-up-l { + rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + prochot { + gpio_prochot: gpio-prochot { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts new file mode 100644 index 000000000000..6337238891eb --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Pinky Rev 2 board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "../cros-ec-sbs.dtsi" + +/ { + model = "Google Pinky"; + compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", + "google,veyron", "rockchip,rk3288"; + + /delete-node/backlight-regulator; + /delete-node/panel-regulator; + /delete-node/emmc-pwrseq; + /delete-node/vcc18-lcd; +}; + +&backlight { + /delete-property/power-supply; +}; + +&emmc { + /* + * Use a pullup instead of a drive since the output is 3.3V and + * really should be 1.8V (oops). The external pulldown will help + * bring the voltage down if we only drive with a pullup here. + * Therefore disable the powerseq (and actual reset) for pinky. + */ + /delete-property/mmc-pwrseq; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; +}; + +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&lid_switch { + pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; + + key-power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + }; +}; + +/* Touchpad connector */ +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +&panel { + power-supply = <&vcc33_lcd>; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Wake only */ + &suspend_l_wake + &bt_dev_wake_awake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Sleep only */ + &suspend_l_sleep + &bt_dev_wake_sleep + >; + + /delete-node/ lcd; + + backlight { + /delete-node/ bl_pwr_en; + }; + + buttons { + pwr_key_h: pwr-key-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_wp_pin: sdmmc-wp-pin { + rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rk808 { + regulators { + vcc18_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_wp_pin &sdmmc_bus4>; + wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&tsadc { + /* Some connection is flaky making the tsadc hang the system */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi new file mode 100644 index 000000000000..8b58773e592e --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron (and derivatives) fragment for sdmmc cards + * + * Copyright 2015 Google, Inc + */ + +/ { + aliases { + mmc1 = &sdmmc; + }; +}; + +&io_domains { + sdcard-supply = <&vccio_sd>; +}; + +&pinctrl { + sdmmc { + /* + * We run sdmmc at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; + }; + + /* + * Builtin CD line is hooked to ground to prevent JTAG at boot + * (and also to get the voltage rail correct). + * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't + * think there's a card inserted + */ + sdmmc_cd_disabled: sdmmc-cd-disabled { + rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* This is where we actually hook up CD */ + sdmmc_cd_pin: sdmmc-cd-pin { + rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk808 { + vcc9-supply = <&vcc_5v>; + + regulators { + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc33_sd: LDO_REG5 { + regulator-name = "vcc33_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + status = "okay"; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc33_sd>; + vqmmc-supply = <&vccio_sd>; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts new file mode 100644 index 000000000000..336cd2be5265 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "rk3288-veyron-broadcom-bluetooth.dtsi" +#include "../cros-ec-sbs.dtsi" + +/ { + model = "Google Speedy"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&cpu_crit { + temperature = <90000>; +}; + +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&gpu_alert0 { + temperature = <80000>; +}; + +&gpu_crit { + temperature = <90000>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFALUT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "PWRLIMIT#_CPU", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "ALS_INT", /* not connected */ + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVS_OK", + "", + "EDP_HOTPLUG", + "DVS1", + "nFALUT1", + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Wake only */ + &suspend_l_wake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff + + /* Sleep only */ + &suspend_l_sleep + >; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts new file mode 100644 index 000000000000..52a84cbe7a90 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Tiger Rev 0+ board device tree source + * + * Copyright 2016 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-fievel.dts" +#include "rk3288-veyron-edp.dtsi" + +/ { + model = "Google Tiger"; + compatible = "google,veyron-tiger-rev8", "google,veyron-tiger-rev7", + "google,veyron-tiger-rev6", "google,veyron-tiger-rev5", + "google,veyron-tiger-rev4", "google,veyron-tiger-rev3", + "google,veyron-tiger-rev2", "google,veyron-tiger-rev1", + "google,veyron-tiger-rev0", "google,veyron-tiger", + "google,veyron", "rockchip,rk3288"; + + /delete-node/ vcc18-lcd; +}; + +&backlight { + /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = <3 255>; + num-interpolated-steps = <252>; +}; + +&backlight_regulator { + vin-supply = <&vccsys>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; + vcc33-supply = <&vcc33_io>; + vccio-supply = <&vcc33_io>; + wakeup-source; + }; +}; + +&panel { + compatible = "auo,b101ean01"; + + /delete-node/ panel-timing; + + panel-timing { + clock-frequency = <66666667>; + hactive = <1280>; + hfront-porch = <18>; + hback-porch = <21>; + hsync-len = <32>; + vactive = <800>; + vfront-porch = <4>; + vback-porch = <8>; + vsync-len = <18>; + }; +}; + +&pinctrl { + lcd { + /delete-node/ avdd-1v8-disp-en; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi new file mode 100644 index 000000000000..d838bf0d5d9a --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron (and derivatives) board device tree source + * + * Copyright 2015 Google, Inc + */ + +#include +#include +#include "rk3288.dtsi" + +/ { + aliases { + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + /* + * The default coreboot on veyron devices ignores memory@0 nodes + * and would instead create another memory node. + */ + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + + power_button: power-button { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; + + key-power { + label = "Power"; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + }; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_warm_reset_h>; + priority = <200>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * Depending on the actual card populated GPIO4 D4 + * correspond to one of these signals on the module: + * + * D4: + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc_5v: vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc33_sys: vcc33-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc33_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc50_hdmi: vcc50-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vcc50_hdmi"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_5v>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + regulator-name = "vdd_logic"; + + pwms = <&pwm1 0 1994 0>; + pwm-supply = <&vcc33_sys>; + + pwm-dutycycle-range = <0x7b 0>; + pwm-dutycycle-unit = <0x94>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <4000>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&cpu_crit { + temperature = <100000>; +}; + +/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ +&cpu_opp_table { + /delete-node/ opp-312000000; + + opp-1512000000 { + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-microvolt = <1300000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <1350000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1400000>; + }; +}; + +&emmc { + status = "okay"; + + bus-width = <8>; + cap-mmc-highspeed; + rockchip,default-sample-phase = <158>; + disable-wp; + mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_alert0 { + temperature = <72500>; +}; + +&gpu_crit { + temperature = <100000>; +}; + +&hdmi { + pinctrl-names = "default", "unwedge"; + pinctrl-0 = <&hdmi_ddc>; + pinctrl-1 = <&hdmi_ddc_unwedge>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ + i2c-scl-rising-time-ns = <100>; /* 45ns measured */ + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc33_sys>; + vcc2-supply = <&vcc33_sys>; + vcc3-supply = <&vcc33_sys>; + vcc4-supply = <&vcc33_sys>; + vcc6-supply = <&vcc_5v>; + vcc7-supply = <&vcc33_sys>; + vcc8-supply = <&vcc33_sys>; + vcc12-supply = <&vcc_18>; + vddio-supply = <&vcc33_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc135_ddr: DCDC_REG3 { + regulator-name = "vcc135_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* + * vcc_18 has several aliases. (vcc18_flashio and + * vcc18_wl). We'll add those aliases here just to + * make it easier to follow the schematic. The signals + * are actually hooked together and only separated for + * power measurement purposes). + */ + vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* + * Note that both vcc33_io and vcc33_pmuio are always + * powered together. To simplify the logic in the dts + * we just refer to vcc33_io every time something is + * powered from vcc33_pmuio. In fact, on later boards + * (such as danger) they're the same net. + */ + vcc33_io: LDO_REG1 { + regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd10_lcd_pwren_h: LDO_REG7 { + regulator-name = "vdd10_lcd_pwren_h"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc33_lcd: SWITCH_REG1 { + regulator-name = "vcc33_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ + i2c-scl-rising-time-ns = <100>; /* 40ns measured */ + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +&i2c2 { + status = "okay"; + + /* 100kHz since 4.7k resistors don't rise fast enough */ + clock-frequency = <100000>; + i2c-scl-falling-time-ns = <50>; /* 10ns measured */ + i2c-scl-rising-time-ns = <800>; /* 600ns measured */ +}; + +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; /* 11ns measured */ + i2c-scl-rising-time-ns = <300>; /* 225ns measured */ +}; + +&io_domains { + status = "okay"; + + bb-supply = <&vcc33_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc18_flashio>; + gpio1830-supply = <&vcc33_io>; + gpio30-supply = <&vcc33_io>; + lcdc-supply = <&vcc33_lcd>; + wifi-supply = <&vcc18_wl>; +}; + +&pwm1 { + status = "okay"; +}; + +&sdio0 { + status = "okay"; + + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc33_sys>; + vqmmc-supply = <&vcc18_wl>; +}; + +&spi2 { + status = "okay"; + + rx-sample-delay-ns = <12>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-temp = <125000>; +}; + +&uart0 { + status = "okay"; + + /* Pins don't include flow control by default; add that in */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; + + needs-reset-on-resume; +}; + +&usb_host1 { + status = "okay"; + snps,need-phy-for-wake; +}; + +&usb_otg { + status = "okay"; + + assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; + assigned-clock-parents = <&usbphy0>; + dr_mode = "host"; + snps,need-phy-for-wake; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + buttons { + pwr_key_l: pwr-key-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + reboot { + ap_warm_reset_h: ap-warm-reset-h { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + recovery-switch { + rec_mode_l: rec-mode-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio0 { + wifi_enable_h: wifienable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* NOTE: mislabelled on schematic; should be bt_enable_h */ + bt_enable_l: bt-enable-l { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* + * We run sdio0 at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; + }; + + /* + * These pins are only present on very new veyron boards; on + * older boards bt_dev_wake is simply always high. Note that + * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt + * to map this pin everywhere + */ + bt_dev_wake_sleep: bt-dev-wake-sleep { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + bt_dev_wake_awake: bt-dev-wake-awake { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_dev_wake: bt-dev-wake { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tpm { + tpm_int_h: tpm-int-h { + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + write-protect { + fw_wp_ap: fw-wp-ap { + rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi new file mode 100644 index 000000000000..793951655b73 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include +#include + +/ { + compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + phy-supply = <&vcc_io>; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_codec: LDO_REG2 { + regulator-name = "vcca_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-name = "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio5>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&io_domains { + bb-supply = <&vcc_io>; + flash0-supply = <&vccio_flash>; + gpio1830-supply = <&vcc_18>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_wl>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + }; + + vbus_host { + usb1_en_oc: usb1-en-oc { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vbus_typec { + usb0_en_oc: usb0-en-oc { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vbus_host { + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ +}; + +&vbus_typec { + enable-active-high; + gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288-vyasa.dts b/arch/arm/boot/dts/rockchip/rk3288-vyasa.dts new file mode 100644 index 000000000000..b156a83eb7d7 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288-vyasa.dts @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Jagan Teki + */ + +/dts-v1/; +#include "rk3288.dtsi" + +/ { + model = "Amarula Vyasa-RK3288"; + compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + dc12_vbat: dc12-vbat { + compatible = "regulator-fixed"; + regulator-name = "dc12_vbat"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vboot_3v3: vboot-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vboot_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vboot_5v: vboot-5v { + compatible = "regulator-fixed"; + regulator-name = "vboot_sv"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + v3g_3v3: v3g-3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3g_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vsus_5v: vsus-5v { + compatible = "regulator-fixed"; + regulator-name = "vsus_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc50_hdmi: vcc50-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vcc50_hdmi"; + enable-active-high; + gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + + vusb1_5v: vusb1-5v { + compatible = "regulator-fixed"; + regulator-name = "vusb1_5v"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vsus_5v>; + }; + + vusb2_5v: vusb2-5v { + compatible = "regulator-fixed"; + regulator-name = "vusb2_5v"; + enable-active-high; + gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pwr_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_codec: LDO_REG2 { + regulator-name = "vcc_codec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_gps: LDO_REG4 { + regulator-name = "vcc_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcc_18>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_io>; + flash0-supply = <&vcc_18>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&phy_pwr_en>; + status = "okay"; +}; + +&usb_otg { + vbus-supply = <&vusb1_5v>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb_host { + phy_pwr_en: phy-pwr-en { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + usb2_pwr_en: usb2-pwr-en { + rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi new file mode 100644 index 000000000000..cb9cdaddffd4 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -0,0 +1,2026 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "rockchip,rk3288"; + + interrupt-parent = <&gic>; + + aliases { + ethernet0 = &gmac; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + mshc0 = &emmc; + mshc1 = &sdmmc; + mshc2 = &sdio0; + mshc3 = &sdio1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + arm-pmu { + compatible = "arm,cortex-a12-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + rockchip,pmu = <&pmu>; + + cpu0: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x500>; + resets = <&cru SRST_CORE0>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; + }; + cpu1: cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x501>; + resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; + }; + cpu2: cpu@502 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x502>; + resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; + }; + cpu3: cpu@503 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x503>; + resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-126000000 { + opp-hz = /bits/ 64 <126000000>; + opp-microvolt = <900000>; + }; + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <900000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <900000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <950000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1200000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The rk3288 cannot use the memory area above 0xfe000000 + * for dma operations for some reason. While there is + * probably a better solution available somewhere, we + * haven't found it yet and while devices with 2GB of ram + * are not affected, this issue prevents 4GB from booting. + * So to make these devices at least bootable, block + * this area for the time being until the real solution + * is found. + */ + dma-unusable@fe000000 { + reg = <0x0 0xfe000000 0x0 0x1000000>; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + }; + + timer: timer@ff810000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; + }; + + sdmmc: mmc@ff0c0000 { + compatible = "rockchip,rk3288-dw-mshc"; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x0 0xff0c0000 0x0 0x4000>; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio0: mmc@ff0d0000 { + compatible = "rockchip,rk3288-dw-mshc"; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, + <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x0 0xff0d0000 0x0 0x4000>; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio1: mmc@ff0e0000 { + compatible = "rockchip,rk3288-dw-mshc"; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, + <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x0 0xff0e0000 0x0 0x4000>; + resets = <&cru SRST_SDIO1>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@ff0f0000 { + compatible = "rockchip,rk3288-dw-mshc"; + max-frequency = <150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x0 0xff0f0000 0x0 0x4000>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + saradc: saradc@ff100000 { + compatible = "rockchip,saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + spi0: spi@ff110000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 11>, <&dmac_peri 12>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + reg = <0x0 0xff110000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff120000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 13>, <&dmac_peri 14>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + reg = <0x0 0xff120000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff130000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 15>, <&dmac_peri 16>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + reg = <0x0 0xff130000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ff140000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff150000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + i2c4: i2c@ff160000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + status = "disabled"; + }; + + i2c5: i2c@ff170000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + status = "disabled"; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 1>, <&dmac_peri 2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 3>, <&dmac_peri 4>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@ff690000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 7>, <&dmac_peri 8>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + uart4: serial@ff1c0000 { + compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1c0000 0x0 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 9>, <&dmac_peri 10>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "disabled"; + }; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + + thermal-zones { + reserve_thermal: reserve-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + }; + + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3288-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_pin>; + #thermal-sensor-cells = <1>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + gmac: ethernet@ff290000 { + compatible = "rockchip,rk3288-gmac"; + reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, + <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + usb_host0_ehci: usb@ff500000 { + compatible = "generic-ehci"; + reg = <0x0 0xff500000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; + + /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ + usb_host0_ohci: usb@ff520000 { + compatible = "generic-ohci"; + reg = <0x0 0xff520000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1: usb@ff540000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff540000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBHOST1>; + clock-names = "otg"; + dr_mode = "host"; + phys = <&usbphy2>; + phy-names = "usb2-phy"; + snps,reset-phy-on-wake; + status = "disabled"; + }; + + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_hsic: usb@ff5c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xff5c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_HSIC>; + status = "disabled"; + }; + + dmac_bus_ns: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c2: i2c@ff660000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff660000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_RKPWM>; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_RKPWM>; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_RKPWM>; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_RKPWM>; + status = "disabled"; + }; + + bus_intmem: sram@ff700000 { + compatible = "mmio-sram"; + reg = <0x0 0xff700000 0x0 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xff700000 0x18000>; + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; + }; + }; + + pmu_sram: sram@ff720000 { + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; + reg = <0x0 0xff720000 0x0 0x1000>; + }; + + pmu: power-management@ff730000 { + compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff730000 0x0 0x100>; + + power: power-controller { + compatible = "rockchip,rk3288-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&cru SCLK_EDP_24M>; + assigned-clock-parents = <&xin24m>; + + /* + * Note: Although SCLK_* are the working clocks + * of device without including on the NOC, needed for + * synchronous reset. + * + * The clocks on the which NOC: + * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. + * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. + * ACLK_RGA is on ACLK_RGA_NIU. + * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. + * + * Which clock are device clocks: + * clocks devices + * *_IEP IEP:Image Enhancement Processor + * *_ISP ISP:Image Signal Processing + * *_VIP VIP:Video Input Processor + * *_VOP* VOP:Visual Output Processor + * *_RGA RGA + * *_EDP* EDP + * *_LVDS_* LVDS + * *_HDMI HDMI + * *_MIPI_* MIPI + */ + power-domain@RK3288_PD_VIO { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_RGA>, + <&cru ACLK_VIP>, + <&cru ACLK_VOP0>, + <&cru ACLK_VOP1>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP0>, + <&cru HCLK_VOP1>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_LVDS_PHY>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_ISP_JPE>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>; + pm_qos = <&qos_vio0_iep>, + <&qos_vio1_vop>, + <&qos_vio1_isp_w0>, + <&qos_vio1_isp_w1>, + <&qos_vio0_vop>, + <&qos_vio0_vip>, + <&qos_vio2_rga_r>, + <&qos_vio2_rga_w>, + <&qos_vio1_isp_r>; + #power-domain-cells = <0>; + }; + + /* + * Note: The following 3 are HEVC(H.265) clocks, + * and on the ACLK_HEVC_NIU (NOC). + */ + power-domain@RK3288_PD_HEVC { + reg = ; + clocks = <&cru ACLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_hevc_r>, + <&qos_hevc_w>; + #power-domain-cells = <0>; + }; + + /* + * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC + * (video endecoder & decoder) clocks that on the + * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). + */ + power-domain@RK3288_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video>; + #power-domain-cells = <0>; + }; + + /* + * Note: ACLK_GPU is the GPU clock, + * and on the ACLK_GPU_NIU (NOC). + */ + power-domain@RK3288_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu_r>, + <&qos_gpu_w>; + #power-domain-cells = <0>; + }; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x94>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; + }; + + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3288-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <500000000>, <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff770000 0x0 0x1000>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + status = "disabled"; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + status = "disabled"; + }; + + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@320 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBOTG_PHY>; + reset-names = "phy-reset"; + }; + + usbphy1: usb-phy@334 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBHOST0_PHY>; + reset-names = "phy-reset"; + }; + + usbphy2: usb-phy@348 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBHOST1_PHY>; + reset-names = "phy-reset"; + }; + }; + }; + + wdt: watchdog@ff800000 { + compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; + reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + spdif: sound@ff8b0000 { + compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; + reg = <0x0 0xff8b0000 0x0 0x10000>; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac_bus_s 3>; + dma-names = "tx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + i2s: i2s@ff890000 { + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x10000>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + crypto: crypto@ff8a0000 { + compatible = "rockchip,rk3288-crypto"; + reg = <0x0 0xff8a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, + <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; + clock-names = "aclk", "hclk", "sclk", "apb_pclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + }; + + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rga: rga@ff920000 { + compatible = "rockchip,rk3288-rga"; + reg = <0x0 0xff920000 0x0 0x180>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; + reset-names = "core", "axi", "ahb"; + }; + + vopb: vop@ff930000 { + compatible = "rockchip,rk3288-vop"; + reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopb_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vopb>; + }; + + vopb_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopb>; + }; + + vopb_out_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_in_vopb>; + }; + + vopb_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3288_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vopl: vop@ff940000 { + compatible = "rockchip,rk3288-vop"; + reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopl_mmu>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopl_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vopl>; + }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + + vopl_out_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_in_vopl>; + }; + + vopl_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopl>; + }; + }; + }; + + vopl_mmu: iommu@ff940300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff940300 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3288_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi_dsi: dsi@ff960000 { + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + + mipi_out: port@1 { + reg = <1>; + }; + }; + }; + + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0x0 0xff96c000 0x0 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + pinctrl-names = "lcdc"; + pinctrl-0 = <&lcdc_ctl>; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + + lvds_out: port@1 { + reg = <1>; + }; + }; + }; + + edp: dp@ff970000 { + compatible = "rockchip,rk3288-dp"; + reg = <0x0 0xff970000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&edp_phy>; + phy-names = "dp"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_EDP>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + + edp_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0x0 0xff980000 0x0 0x20000>; + reg-io-width = <4>; + #sound-dai-cells = <0>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; + power-domains = <&power RK3288_PD_VIO>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + + vpu: video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; + reg = <0x0 0xff9a0000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3288_PD_VIDEO>; + }; + + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3288_PD_VIDEO>; + }; + + hevc_mmu: iommu@ff9c0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; + reg = <0x0 0xffa30000 0x0 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + + qos_gpu_r: qos@ffaa0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffaa0000 0x0 0x20>; + }; + + qos_gpu_w: qos@ffaa0080 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffaa0080 0x0 0x20>; + }; + + qos_vio1_vop: qos@ffad0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_vio1_isp_w0: qos@ffad0100 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0100 0x0 0x20>; + }; + + qos_vio1_isp_w1: qos@ffad0180 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0180 0x0 0x20>; + }; + + qos_vio0_vop: qos@ffad0400 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0400 0x0 0x20>; + }; + + qos_vio0_vip: qos@ffad0480 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0480 0x0 0x20>; + }; + + qos_vio0_iep: qos@ffad0500 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0500 0x0 0x20>; + }; + + qos_vio2_rga_r: qos@ffad0800 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0800 0x0 0x20>; + }; + + qos_vio2_rga_w: qos@ffad0880 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0880 0x0 0x20>; + }; + + qos_vio1_isp_r: qos@ffad0900 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0900 0x0 0x20>; + }; + + qos_video: qos@ffae0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + + qos_hevc_r: qos@ffaf0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffaf0000 0x0 0x20>; + }; + + qos_hevc_w: qos@ffaf0080 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffaf0080 0x0 0x20>; + }; + + dmac_bus_s: dma-controller@ffb20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xffb20000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + }; + + efuse: efuse@ffb40000 { + compatible = "rockchip,rk3288-efuse"; + reg = <0x0 0xffb40000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_id: cpu-id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffc01000 0x0 0x1000>, + <0x0 0xffc02000 0x0 0x2000>, + <0x0 0xffc04000 0x0 0x2000>, + <0x0 0xffc06000 0x0 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3288-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff7b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@ff7c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO5>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@ff7d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@ff7e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7e0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO7>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@ff7f0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7f0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO8>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hdmi { + hdmi_cec_c0: hdmi-cec-c0 { + rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; + }; + + hdmi_cec_c7: hdmi-cec-c7 { + rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; + }; + + hdmi_ddc: hdmi-ddc { + rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, + <7 RK_PC4 2 &pcfg_pull_none>; + }; + + hdmi_ddc_unwedge: hdmi-ddc-unwedge { + rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, + <7 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + suspend { + global_pwroff: global-pwroff { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; + }; + + ddrio_pwroff: ddrio-pwroff { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; + }; + + ddr0_retention: ddr0-retention { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; + }; + + ddr1_retention: ddr1-retention { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, + <8 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, + <6 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, + <7 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, + <7 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, + <6 RK_PA1 1 &pcfg_pull_none>, + <6 RK_PA2 1 &pcfg_pull_none>, + <6 RK_PA3 1 &pcfg_pull_none>, + <6 RK_PA4 1 &pcfg_pull_none>, + <6 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + lcdc { + lcdc_ctl: lcdc-ctl { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>, + <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, + <6 RK_PC1 1 &pcfg_pull_up>, + <6 RK_PC2 1 &pcfg_pull_up>, + <6 RK_PC3 1 &pcfg_pull_up>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, + <4 RK_PC5 1 &pcfg_pull_up>, + <4 RK_PC6 1 &pcfg_pull_up>, + <4 RK_PC7 1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; + }; + }; + + sdio1 { + sdio1_bus1: sdio1-bus1 { + rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; + }; + + sdio1_bus4: sdio1-bus4 { + rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, + <3 RK_PD1 4 &pcfg_pull_up>, + <3 RK_PD2 4 &pcfg_pull_up>, + <3 RK_PD3 4 &pcfg_pull_up>; + }; + + sdio1_cd: sdio1-cd { + rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; + }; + + sdio1_wp: sdio1-wp { + rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; + }; + + sdio1_bkpwr: sdio1-bkpwr { + rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; + }; + + sdio1_int: sdio1-int { + rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; + }; + + sdio1_cmd: sdio1-cmd { + rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; + }; + + sdio1_clk: sdio1-clk { + rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; + }; + + sdio1_pwr: sdio1-pwr { + rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, + <3 RK_PA1 2 &pcfg_pull_up>, + <3 RK_PA2 2 &pcfg_pull_up>, + <3 RK_PA3 2 &pcfg_pull_up>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, + <3 RK_PA1 2 &pcfg_pull_up>, + <3 RK_PA2 2 &pcfg_pull_up>, + <3 RK_PA3 2 &pcfg_pull_up>, + <3 RK_PA4 2 &pcfg_pull_up>, + <3 RK_PA5 2 &pcfg_pull_up>, + <3 RK_PA6 2 &pcfg_pull_up>, + <3 RK_PA7 2 &pcfg_pull_up>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; + }; + }; + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_cs1: spi2-cs1 { + rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; + }; + spi2_clk: spi2-clk { + rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, + <4 RK_PC1 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, + <5 RK_PB1 1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, + <7 RK_PC7 1 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, + <7 RK_PB0 1 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, + <5 RK_PB6 3 &pcfg_pull_none>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_pin: otp-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD2 3 &pcfg_pull_none>, + <3 RK_PD3 3 &pcfg_pull_none>, + <3 RK_PD4 3 &pcfg_pull_none_12ma>, + <3 RK_PD5 3 &pcfg_pull_none_12ma>, + <3 RK_PD0 3 &pcfg_pull_none_12ma>, + <3 RK_PD1 3 &pcfg_pull_none_12ma>, + <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA6 3 &pcfg_pull_none>, + <4 RK_PB1 3 &pcfg_pull_none_12ma>, + <4 RK_PA4 3 &pcfg_pull_none_12ma>, + <4 RK_PA1 3 &pcfg_pull_none>, + <4 RK_PA3 3 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD4 3 &pcfg_pull_none>, + <3 RK_PD5 3 &pcfg_pull_none>, + <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA4 3 &pcfg_pull_none>, + <4 RK_PA1 3 &pcfg_pull_none>, + <4 RK_PA2 3 &pcfg_pull_none>, + <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi new file mode 100644 index 000000000000..cb4e42ede56a --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + ethernet0 = &emac; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + clock-output-names = "xin24m"; + }; + + gpu: gpu@10090000 { + compatible = "arm,mali-400"; + reg = <0x10090000 0x10000>; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + + L2: cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + global_timer: global-timer@1013c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1013c200 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + status = "disabled"; + /* The clock source and the sched_clock provided by the arm_global_timer + * on Rockchip rk3066a/rk3188 are quite unstable because their rates + * depend on the CPU frequency. + * Keep the arm_global_timer disabled in order to have the + * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default. + */ + }; + + local_timer: local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = ; + clocks = <&cru CORE_PERI>; + }; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + status = "disabled"; + }; + + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_lcdc0: qos@1012f000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_cif0: qos@1012f080 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f080 0x20>; + }; + + qos_ipp: qos@1012f100 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc1: qos@1012f180 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_cif1: qos@1012f200 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f200 0x20>; + }; + + qos_rga: qos@1012f280 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f280 0x20>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + phys = <&usbphy1>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + emac: ethernet@10204000 { + compatible = "snps,arc-emac"; + reg = <0x10204000 0x3c>; + interrupts = ; + + rockchip,grf = <&grf>; + + clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; + clock-names = "hclk", "macref"; + max-speed = <100>; + phy-mode = "rmii"; + + status = "disabled"; + }; + + mmc0: mmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; + fifo-depth = <256>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + mmc1: mmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; + clock-names = "biu", "ciu"; + dmas = <&dmac2 3>; + dma-names = "rx-tx"; + fifo-depth = <256>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@1021c000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x1021c000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + dmas = <&dmac2 4>; + dma-names = "rx-tx"; + fifo-depth = <256>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + nfc: nand-controller@10500000 { + compatible = "rockchip,rk2928-nfc"; + reg = <0x10500000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC0>; + clock-names = "ahb"; + status = "disabled"; + }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; + reg = <0x20004000 0x100>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x40>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; + }; + + grf: grf@20008000 { + compatible = "syscon", "simple-mfd"; + reg = <0x20008000 0x200>; + }; + + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@2002d000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002d000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + + status = "disabled"; + }; + + i2c1: i2c@2002f000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002f000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C1>; + clock-names = "i2c"; + + status = "disabled"; + }; + + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + wdt: watchdog@2004c000 { + compatible = "snps,dw-wdt"; + reg = <0x2004c000 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + i2c2: i2c@20056000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C2>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c3: i2c@2005a000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C3>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c4: i2c@2005e000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C4>; + clock-names = "i2c"; + + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + status = "disabled"; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + spi0: spi@20070000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20070000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@20074000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20074000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi new file mode 100644 index 000000000000..da1d548b7330 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include + +/ { + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus_host: vbus-host { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_oc>; + regulator-name = "vbus_host"; /* HOST-5V */ + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_oc>; + regulator-name = "vbus_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts new file mode 100644 index 000000000000..2d9994379eb2 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (C) 2018 O.S. Systems Software LTDA. + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Elgin RV1108 R1 board"; + compatible = "elgin,rv1108-r1", "rockchip,rv1108"; + + aliases { + mmc0 = &emmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = ; + rockchip,system-power-controller; + #clock-cells = <0>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vdd_buck2>; + vcc6-supply = <&vdd_buck2>; + + regulators { + vdd_core: DCDC_REG1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_buck2: DCDC_REG2 { + regulator-name = "vdd_buck2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG1 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG2 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd10_pmu: LDO_REG3 { + regulator-name = "vdd10_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>; + status = "okay"; + + dh2228fv: dac@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-cpha; + spi-cpol; + }; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1108-evb.dts b/arch/arm/boot/dts/rockchip/rv1108-evb.dts new file mode 100644 index 000000000000..ef150f4ee99d --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1108-evb.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Rockchip RV1108 Evaluation board"; + compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; + + aliases { + mmc0 = &sdmmc; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + clock-frequency = <400000>; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = ; + rockchip,system-power-controller; + #clock-cells = <0>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_core: DCDC_REG1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cam: DCDC_REG2 { + regulator-name = "vdd_cam"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG1 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG2 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd10_pmu: LDO_REG3 { + regulator-name = "vdd10_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; + + bma250: accelerometer@19 { + compatible = "bosch,bma250e"; + reg = <0x19>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi new file mode 100644 index 000000000000..abf3006f0a84 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -0,0 +1,986 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1108"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <75>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <975000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1150000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + arm,cpu-registers-not-fw-configured; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + bus_intmem: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + + uart2: serial@10210000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10210000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 6>, <&pdma 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart1: serial@10220000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10220000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 4>, <&pdma 5>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart0: serial@10230000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 2>, <&pdma 3>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + i2c1: i2c@10240000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x10240000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + i2c2: i2c@10250000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x10250000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + i2c3: i2c@10260000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x10260000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + spi: spi@10270000 { + compatible = "rockchip,rv1108-spi"; + reg = <0x10270000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm4: pwm@10280000 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x10280000 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@10280010 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x10280010 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@10280020 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x10280020 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm6_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@10280030 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x10280030 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pdma: dma-controller@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + grf: syscon@10300000 { + compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; + reg = <0x10300000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rv1108-io-voltage-domain"; + status = "disabled"; + }; + + u2phy: usb2phy@100 { + compatible = "rockchip,rv1108-usb2phy"; + reg = <0x100 0x0c>; + clocks = <&cru SCLK_USBPHY>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usbphy"; + rockchip,usbgrf = <&usbgrf>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = ; + interrupt-names = "otg-mux"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + timer: timer@10350000 { + compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; + reg = <0x10350000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + watchdog: watchdog@10360000 { + compatible = "rockchip,rv1108-wdt", "snps,dw-wdt"; + reg = <0x10360000 0x100>; + interrupts = ; + clocks = <&cru PCLK_WDT>; + status = "disabled"; + }; + + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <50>; + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + }; + + tsadc: tsadc@10370000 { + compatible = "rockchip,rv1108-tsadc"; + reg = <0x10370000 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_pin>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,hw-tshut-temp = <120000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + adc: adc@1038c000 { + compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; + reg = <0x1038c000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@20000000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x20000000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + pwm0: pwm@20040000 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x20040000 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@20040010 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x20040010 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@20040020 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x20040020 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@20040030 { + compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; + reg = <0x20040030 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmugrf: syscon@20060000 { + compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd"; + reg = <0x20060000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1108-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + usbgrf: syscon@202a0000 { + compatible = "rockchip,rv1108-usbgrf", "syscon"; + reg = <0x202a0000 0x1000>; + }; + + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + nfc: nand-controller@30100000 { + compatible = "rockchip,rv1108-nfc"; + reg = <0x30100000 0x1000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + status = "disabled"; + }; + + emmc: mmc@30110000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30110000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + sdio: mmc@30120000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30120000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + sdmmc: mmc@30130000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30130000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <100000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "disabled"; + }; + + usb_host_ehci: usb@30140000 { + compatible = "generic-ehci"; + reg = <0x30140000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@30160000 { + compatible = "generic-ohci"; + reg = <0x30160000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_otg: usb@30180000 { + compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x30180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + sfc: spi@301c0000 { + compatible = "rockchip,sfc"; + reg = <0x301c0000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + + gmac: ethernet@30200000 { + compatible = "rockchip,rv1108-gmac"; + reg = <0x30200000 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + /* rv1108 only supports an rmii interface */ + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x2000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1108-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20030000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20030000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0_PMU>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@10310000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10310000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@10320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10320000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@10330000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10330000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { + drive-strength = <4>; + }; + + pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; + }; + }; + + sfc { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>, + <2 RK_PA1 3 &pcfg_pull_none>, + <2 RK_PA2 3 &pcfg_pull_none>, + <2 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>, + <2 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <2 RK_PB4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + gmac { + rmii_pins: rmii-pins { + rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, + <1 RK_PC3 2 &pcfg_pull_none>, + <1 RK_PC4 2 &pcfg_pull_none>, + <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB5 3 &pcfg_pull_none>, + <1 RK_PB6 3 &pcfg_pull_none>, + <1 RK_PB7 3 &pcfg_pull_none>, + <1 RK_PC2 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, + <2 RK_PD4 1 &pcfg_pull_up>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, + <0 RK_PC6 3 &pcfg_pull_none>; + }; + + i2c2m1_pins: i2c2m1-pins { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c2m05v { + i2c2m05v_xfer: i2c2m05v-xfer { + rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>; + }; + + i2c2m05v_pins: i2c2m05v-pins { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, + <0 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + pwm4_pin: pwm4-pin { + rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pwm5 { + pwm5_pin: pwm5-pin { + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; + }; + }; + + pwm6 { + pwm6_pin: pwm6-pin { + rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + pwm7 { + pwm7_pin: pwm7-pin { + rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; + }; + }; + + spim0 { + spim0_clk: spim0-clk { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; + }; + + spim0_cs0: spim0-cs0 { + rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; + }; + + spim0_tx: spim0-tx { + rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; + }; + + spim0_rx: spim0-rx { + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; + }; + }; + + spim1 { + spim1_clk: spim1-clk { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; + }; + + spim1_cs0: spim1-cs0 { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; + }; + + spim1_rx: spim1-rx { + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; + }; + + spim1_tx: spim1-tx { + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; + }; + }; + + tsadc { + otp_out: otp-out { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; + }; + + otp_pin: otp-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; + }; + + uart0_rts_pin: uart0-rts-pin { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, + <1 RK_PD2 1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + uart2m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, + <2 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + uart2m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, + <3 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + uart2_5v { + uart2_5v_cts: uart2_5v-cts { + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; + }; + + uart2_5v_rts: uart2_5v-rts { + rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts new file mode 100644 index 000000000000..3340fc3f0739 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-edgeble-neu2.dtsi" + +/ { + model = "Edgeble Neu2 IO Board"; + compatible = "edgeble,neural-compute-module-2-io", + "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; + tx_delay = <0x2a>; + rx_delay = <0x1a>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi new file mode 100644 index 000000000000..cc64ba4be344 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + mmc0 = &emmc; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_vol_sel>; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_vol_sel: flash-vol-sel { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vccio_flash>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&rk809 1>; + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>; + vddxo-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi new file mode 100644 index 000000000000..b77021772781 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk_out_ethernet { + /omit-if-no-ref/ + clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + }; + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + rgmii { + /omit-if-no-ref/ + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi new file mode 100644 index 000000000000..1f07d0a4fa73 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1126"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x20000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + qos_emmc: qos@fe860000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860000 0x20>; + }; + + qos_nandc: qos@fe860080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860080 0x20>; + }; + + qos_sfc: qos@fe860200 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860200 0x20>; + }; + + qos_sdio: qos@fe86c000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe86c000 0x20>; + }; + + gic: interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xfeff1000 0x1000>, + <0xfeff2000 0x2000>, + <0xfeff4000 0x2000>, + <0xfeff6000 0x2000>; + interrupts = ; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RV1126_PD_NVM { + reg = ; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>; + #power-domain-cells = <0>; + }; + + power-domain@RV1126_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 7>, <&dmac 6>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dmac: dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + uart0: serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 5>, <&dmac 4>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 9>, <&dmac 8>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 11>, <&dmac 10>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + saradc: adc@ff5e0000 { + compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + timer0: timer@ff660000 { + compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; + reg = <0xff660000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + emmc: mmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + + sdmmc: mmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdio: mmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_SDIO>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/rtd1195-horseradish.dts b/arch/arm/boot/dts/rtd1195-horseradish.dts deleted file mode 100644 index 9d06d3d34c74..000000000000 --- a/arch/arm/boot/dts/rtd1195-horseradish.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1195.dtsi" - -/ { - compatible = "realtek,horseradish", "realtek,rtd1195"; - model = "Realtek Horseradish EVB"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@a800 { - device_type = "memory"; - reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ - <0x18070000 0x00090000>, /* r-bus to NOR flash */ - <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/rtd1195-mele-x1000.dts deleted file mode 100644 index c7951b9a2c97..000000000000 --- a/arch/arm/boot/dts/rtd1195-mele-x1000.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017-2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1195.dtsi" - -/ { - compatible = "mele,x1000", "realtek,rtd1195"; - model = "MeLE X1000"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@a800 { - device_type = "memory"; - reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ - <0x18070000 0x00090000>, /* r-bus to NOR flash */ - <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi deleted file mode 100644 index 21897210d9d0..000000000000 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017-2019 Andreas Färber - */ - -/memreserve/ 0x00000000 0x0000a800; /* boot code */ -/memreserve/ 0x0000a800 0x000f5800; -/memreserve/ 0x17fff000 0x00001000; - -#include -#include - -/ { - compatible = "realtek,rtd1195"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clock-frequency = <1000000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - clock-frequency = <1000000000>; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rpc_comm: rpc@b000 { - reg = <0x0000b000 0x1000>; - }; - - audio@1b00000 { - reg = <0x01b00000 0x400000>; - }; - - rpc_ringbuf: rpc@1ffe000 { - reg = <0x01ffe000 0x4000>; - }; - - secure@10000000 { - reg = <0x10000000 0x100000>; - no-map; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <27000000>; - }; - - osc27M: osc { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - clock-output-names = "osc27M"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x0000a800>, - <0x18000000 0x18000000 0x00070000>, - <0x18100000 0x18100000 0x01000000>, - <0x80000000 0x80000000 0x80000000>; - - rbus: bus@18000000 { - compatible = "simple-bus"; - reg = <0x18000000 0x70000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x70000>; - - crt: syscon@0 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - iso: syscon@7000 { - compatible = "syscon", "simple-mfd"; - reg = <0x7000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - }; - - sb2: syscon@1a000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1a000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - misc: syscon@1b000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1b000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b000 0x1000>; - }; - - scpu_wrapper: syscon@1d000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1d000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1d000 0x1000>; - }; - }; - - gic: interrupt-controller@ff011000 { - compatible = "arm,cortex-a7-gic"; - reg = <0xff011000 0x1000>, - <0xff012000 0x2000>, - <0xff014000 0x2000>, - <0xff016000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; -}; - -&crt { - reset1: reset-controller@0 { - compatible = "snps,dw-low-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@4 { - compatible = "snps,dw-low-reset"; - reg = <0x4 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@8 { - compatible = "snps,dw-low-reset"; - reg = <0x8 0x4>; - #reset-cells = <1>; - }; -}; - -&iso { - iso_reset: reset-controller@88 { - compatible = "snps,dw-low-reset"; - reg = <0x88 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@800 { - compatible = "snps,dw-apb-uart"; - reg = <0x800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; - clock-frequency = <27000000>; - status = "disabled"; - }; -}; - -&misc { - uart1: serial@200 { - compatible = "snps,dw-apb-uart"; - reg = <0x200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&reset2 RTD1195_RSTN_UR1>; - clock-frequency = <27000000>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts deleted file mode 100644 index 2d9994379eb2..000000000000 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/* - * Copyright (C) 2018 O.S. Systems Software LTDA. - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Elgin RV1108 R1 board"; - compatible = "elgin,rv1108-r1", "rockchip,rv1108"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - no-sd; - no-sdio; - non-removable; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <275>; - i2c-scl-falling-time-ns = <16>; - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - #clock-cells = <0>; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vdd_buck2>; - vcc6-supply = <&vdd_buck2>; - - regulators { - vdd_core: DCDC_REG1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_buck2: DCDC_REG2 { - regulator-name = "vdd_buck2"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG1 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG2 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd10_pmu: LDO_REG3 { - regulator-name = "vdd10_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>; - status = "okay"; - - dh2228fv: dac@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <24000000>; - spi-cpha; - spi-cpol; - }; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts deleted file mode 100644 index ef150f4ee99d..000000000000 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RV1108 Evaluation board"; - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - - aliases { - mmc0 = &sdmmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - pwms = <&pwm0 0 25000 0>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <275>; - i2c-scl-falling-time-ns = <16>; - clock-frequency = <400000>; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - #clock-cells = <0>; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_core: DCDC_REG1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cam: DCDC_REG2 { - regulator-name = "vdd_cam"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG1 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG2 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd10_pmu: LDO_REG3 { - regulator-name = "vdd10_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; - - bma250: accelerometer@19 { - compatible = "bosch,bma250e"; - reg = <0x19>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi deleted file mode 100644 index abf3006f0a84..000000000000 --- a/arch/arm/boot/dts/rv1108.dtsi +++ /dev/null @@ -1,986 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1108"; - - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <75>; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - cpu_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <975000>; - clock-latency-ns = <40000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1150000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - arm,cpu-registers-not-fw-configured; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - bus_intmem: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 6>, <&pdma 7>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 4>, <&pdma 5>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 2>, <&pdma 3>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - i2c1: i2c@10240000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x10240000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2c2: i2c@10250000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x10250000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m1_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2c3: i2c@10260000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x10260000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - spi: spi@10270000 { - compatible = "rockchip,rv1108-spi"; - reg = <0x10270000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm4: pwm@10280000 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280000 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@10280010 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280010 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@10280020 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280020 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@10280030 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280030 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pdma: dma-controller@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; - reg = <0x10300000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rv1108-io-voltage-domain"; - status = "disabled"; - }; - - u2phy: usb2phy@100 { - compatible = "rockchip,rv1108-usb2phy"; - reg = <0x100 0x0c>; - clocks = <&cru SCLK_USBPHY>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usbphy"; - rockchip,usbgrf = <&usbgrf>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = ; - interrupt-names = "otg-mux"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - timer: timer@10350000 { - compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; - reg = <0x10350000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - watchdog: watchdog@10360000 { - compatible = "rockchip,rv1108-wdt", "snps,dw-wdt"; - reg = <0x10360000 0x100>; - interrupts = ; - clocks = <&cru PCLK_WDT>; - status = "disabled"; - }; - - thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <50>; - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - }; - - tsadc: tsadc@10370000 { - compatible = "rockchip,rv1108-tsadc"; - reg = <0x10370000 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <750000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,hw-tshut-temp = <120000>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - adc: adc@1038c000 { - compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; - reg = <0x1038c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@20000000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x20000000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - pwm0: pwm@20040000 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040000 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@20040010 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040010 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@20040020 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040020 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@20040030 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040030 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd"; - reg = <0x20060000 0x1000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rv1108-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - usbgrf: syscon@202a0000 { - compatible = "rockchip,rv1108-usbgrf", "syscon"; - reg = <0x202a0000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - nfc: nand-controller@30100000 { - compatible = "rockchip,rv1108-nfc"; - reg = <0x30100000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - assigned-clocks = <&cru SCLK_NANDC>; - assigned-clock-rates = <150000000>; - status = "disabled"; - }; - - emmc: mmc@30110000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30110000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@30120000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30120000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdmmc: mmc@30130000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30130000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <100000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "disabled"; - }; - - usb_host_ehci: usb@30140000 { - compatible = "generic-ehci"; - reg = <0x30140000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@30160000 { - compatible = "generic-ohci"; - reg = <0x30160000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - sfc: spi@301c0000 { - compatible = "rockchip,sfc"; - reg = <0x301c0000 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rv1108-gmac"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - /* rv1108 only supports an rmii interface */ - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0_PMU>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - emmc { - emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; - }; - }; - - sfc { - sfc_bus4: sfc-bus4 { - rockchip,pins = - <2 RK_PA0 3 &pcfg_pull_none>, - <2 RK_PA1 3 &pcfg_pull_none>, - <2 RK_PA2 3 &pcfg_pull_none>, - <2 RK_PA3 3 &pcfg_pull_none>; - }; - - sfc_bus2: sfc-bus2 { - rockchip,pins = - <2 RK_PA0 3 &pcfg_pull_none>, - <2 RK_PA1 3 &pcfg_pull_none>; - }; - - sfc_cs0: sfc-cs0 { - rockchip,pins = - <2 RK_PB4 3 &pcfg_pull_none>; - }; - - sfc_clk: sfc-clk { - rockchip,pins = - <2 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, - <1 RK_PC3 2 &pcfg_pull_none>, - <1 RK_PC4 2 &pcfg_pull_none>, - <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 3 &pcfg_pull_none>, - <1 RK_PB6 3 &pcfg_pull_none>, - <1 RK_PB7 3 &pcfg_pull_none>, - <1 RK_PC2 3 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, - <0 RK_PB2 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, - <2 RK_PD4 1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, - <0 RK_PC6 3 &pcfg_pull_none>; - }; - - i2c2m1_pins: i2c2m1-pins { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>; - }; - - i2c2m05v_pins: i2c2m05v-pins { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, - <0 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; - }; - }; - - spim0 { - spim0_clk: spim0-clk { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; - }; - - spim0_cs0: spim0-cs0 { - rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; - }; - - spim0_tx: spim0-tx { - rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; - }; - - spim0_rx: spim0-rx { - rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; - }; - }; - - spim1 { - spim1_clk: spim1-clk { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; - }; - - spim1_cs0: spim1-cs0 { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; - }; - - spim1_rx: spim1-rx { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; - }; - - spim1_tx: spim1-tx { - rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; - }; - }; - - tsadc { - otp_out: otp-out { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; - }; - - otp_pin: otp-pin { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, - <3 RK_PA5 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; - }; - - uart0_rts_pin: uart0-rts-pin { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, - <1 RK_PD2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, - <3 RK_PC2 2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts deleted file mode 100644 index 3340fc3f0739..000000000000 --- a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. - */ - -/dts-v1/; -#include "rv1126.dtsi" -#include "rv1126-edgeble-neu2.dtsi" - -/ { - model = "Edgeble Neu2 IO Board"; - compatible = "edgeble,neural-compute-module-2-io", - "edgeble,neural-compute-module-2", "rockchip,rv1126"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&gmac { - assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, - <&cru CLK_GMAC_ETHERNET_OUT>; - assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; - assigned-clock-rates = <125000000>, <0>, <25000000>; - clock_in_out = "input"; - phy-handle = <&phy>; - phy-mode = "rgmii"; - phy-supply = <&vcc_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; - tx_delay = <0x2a>; - rx_delay = <0x1a>; - status = "okay"; -}; - -&mdio { - phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - ethernet { - eth_phy_rst: eth-phy-rst { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; - rockchip,default-sample-phase = <90>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr104; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi deleted file mode 100644 index cc64ba4be344..000000000000 --- a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. - */ - -/ { - compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126"; - - aliases { - mmc0 = &emmc; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vccio_flash: vccio-flash-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&flash_vol_sel>; - regulator-name = "vccio_flash"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; - - sdio_pwrseq: pwrseq-sdio { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; - rockchip,default-sample-phase = <90>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_buck5>; - vcc6-supply = <&vcc_buck5>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_npu_vepu: DCDC_REG1 { - regulator-name = "vdd_npu_vepu"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_sys: DCDC_REG4 { - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_buck5: DCDC_REG5 { - regulator-name = "vcc_buck5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2200000>; - }; - }; - - vcc_0v8: LDO_REG1 { - regulator-name = "vcc_0v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG2 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd0v8_pmu: LDO_REG3 { - regulator-name = "vcc0v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <800000>; - }; - }; - - vcc_1v8: LDO_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_dovdd: LDO_REG5 { - regulator-name = "vcc_dovdd"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_dvdd: LDO_REG6 { - regulator-name = "vcc_dvdd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_avdd: LDO_REG7 { - regulator-name = "vcc_avdd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG8 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: LDO_REG9 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_5v0: SWITCH_REG1 { - regulator-name = "vcc_5v0"; - }; - - vcc_3v3: SWITCH_REG2 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&pinctrl { - bt { - bt_enable: bt-enable { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - flash { - flash_vol_sel: flash-vol-sel { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wifi { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio0-supply = <&vcc1v8_pmu>; - pmuio1-supply = <&vcc3v3_sys>; - vccio1-supply = <&vccio_flash>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_1v8>; - vccio4-supply = <&vcc_dovdd>; - vccio5-supply = <&vcc_1v8>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_dovdd>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <100000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; - rockchip,default-sample-phase = <90>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; - status = "okay"; - - bluetooth { - compatible = "qcom,qca9377-bt"; - clocks = <&rk809 1>; - enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */ - max-speed = <2000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_enable>; - vddxo-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi deleted file mode 100644 index b77021772781..000000000000 --- a/arch/arm/boot/dts/rv1126-pinctrl.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - clk_out_ethernet { - /omit-if-no-ref/ - clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { - rockchip,pins = - /* clk_out_ethernet_m1 */ - <2 RK_PC5 2 &pcfg_pull_none>; - }; - }; - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <1 RK_PA3 2 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clko */ - <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; - }; - }; - i2c0 { - /omit-if-no-ref/ - i2c0_xfer: i2c0-xfer { - rockchip,pins = - /* i2c0_scl */ - <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, - /* i2c0_sda */ - <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; - }; - }; - rgmii { - /omit-if-no-ref/ - rgmiim1_pins: rgmiim1-pins { - rockchip,pins = - /* rgmii_mdc_m1 */ - <2 RK_PC2 2 &pcfg_pull_none>, - /* rgmii_mdio_m1 */ - <2 RK_PC1 2 &pcfg_pull_none>, - /* rgmii_rxclk_m1 */ - <2 RK_PD3 2 &pcfg_pull_none>, - /* rgmii_rxd0_m1 */ - <2 RK_PB5 2 &pcfg_pull_none>, - /* rgmii_rxd1_m1 */ - <2 RK_PB6 2 &pcfg_pull_none>, - /* rgmii_rxd2_m1 */ - <2 RK_PC7 2 &pcfg_pull_none>, - /* rgmii_rxd3_m1 */ - <2 RK_PD0 2 &pcfg_pull_none>, - /* rgmii_rxdv_m1 */ - <2 RK_PB4 2 &pcfg_pull_none>, - /* rgmii_txclk_m1 */ - <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txd0_m1 */ - <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txd1_m1 */ - <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txd2_m1 */ - <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txd3_m1 */ - <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txen_m1 */ - <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; - }; - }; - sdmmc0 { - /omit-if-no-ref/ - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - /* sdmmc0_d0 */ - <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d1 */ - <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d2 */ - <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d3 */ - <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - /* sdmmc0_clk */ - <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - /* sdmmc0_cmd */ - <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - sdmmc0_det: sdmmc0-det { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - sdmmc0_pwr: sdmmc0-pwr { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - sdmmc1 { - /omit-if-no-ref/ - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - /* sdmmc1_d0 */ - <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d1 */ - <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d2 */ - <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d3 */ - <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - /* sdmmc1_clk */ - <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - /* sdmmc1_cmd */ - <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; - }; - /omit-if-no-ref/ - sdmmc1_det: sdmmc1-det { - rockchip,pins = - <1 RK_PD0 2 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - sdmmc1_pwr: sdmmc1-pwr { - rockchip,pins = - <1 RK_PD1 2 &pcfg_pull_none>; - }; - }; - uart0 { - /omit-if-no-ref/ - uart0_xfer: uart0-xfer { - rockchip,pins = - /* uart0_rx */ - <1 RK_PC2 1 &pcfg_pull_up>, - /* uart0_tx */ - <1 RK_PC3 1 &pcfg_pull_up>; - }; - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - <1 RK_PC1 1 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - <1 RK_PC0 1 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - uart0_rtsn_gpio: uart0-rts-pin { - rockchip,pins = - <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rx_m0 */ - <0 RK_PB7 2 &pcfg_pull_up>, - /* uart1_tx_m0 */ - <0 RK_PB6 2 &pcfg_pull_up>; - }; - }; - uart2 { - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rx_m1 */ - <3 RK_PA3 1 &pcfg_pull_up>, - /* uart2_tx_m1 */ - <3 RK_PA2 1 &pcfg_pull_up>; - }; - }; - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rx_m0 */ - <3 RK_PC7 4 &pcfg_pull_up>, - /* uart3_tx_m0 */ - <3 RK_PC6 4 &pcfg_pull_up>; - }; - }; - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rx_m0 */ - <3 RK_PA5 4 &pcfg_pull_up>, - /* uart4_tx_m0 */ - <3 RK_PA4 4 &pcfg_pull_up>; - }; - }; - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rx_m0 */ - <3 RK_PA7 4 &pcfg_pull_up>, - /* uart5_tx_m0 */ - <3 RK_PA6 4 &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi deleted file mode 100644 index 1f07d0a4fa73..000000000000 --- a/arch/arm/boot/dts/rv1126.dtsi +++ /dev/null @@ -1,487 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1126"; - - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - grf: syscon@fe000000 { - compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; - reg = <0xfe000000 0x20000>; - }; - - pmugrf: syscon@fe020000 { - compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; - reg = <0xfe020000 0x1000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rv1126-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - qos_emmc: qos@fe860000 { - compatible = "rockchip,rv1126-qos", "syscon"; - reg = <0xfe860000 0x20>; - }; - - qos_nandc: qos@fe860080 { - compatible = "rockchip,rv1126-qos", "syscon"; - reg = <0xfe860080 0x20>; - }; - - qos_sfc: qos@fe860200 { - compatible = "rockchip,rv1126-qos", "syscon"; - reg = <0xfe860200 0x20>; - }; - - qos_sdio: qos@fe86c000 { - compatible = "rockchip,rv1126-qos", "syscon"; - reg = <0xfe86c000 0x20>; - }; - - gic: interrupt-controller@feff0000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0xfeff1000 0x1000>, - <0xfeff2000 0x2000>, - <0xfeff4000 0x2000>, - <0xfeff6000 0x2000>; - interrupts = ; - }; - - pmu: power-management@ff3e0000 { - compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; - reg = <0xff3e0000 0x1000>; - - power: power-controller { - compatible = "rockchip,rv1126-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RV1126_PD_NVM { - reg = ; - clocks = <&cru HCLK_EMMC>, - <&cru CLK_EMMC>, - <&cru HCLK_NANDC>, - <&cru CLK_NANDC>, - <&cru HCLK_SFC>, - <&cru HCLK_SFCXIP>, - <&cru SCLK_SFC>; - pm_qos = <&qos_emmc>, - <&qos_nandc>, - <&qos_sfc>; - #power-domain-cells = <0>; - }; - - power-domain@RV1126_PD_SDIO { - reg = ; - clocks = <&cru HCLK_SDIO>, - <&cru CLK_SDIO>; - pm_qos = <&qos_sdio>; - #power-domain-cells = <0>; - }; - }; - }; - - i2c0: i2c@ff3f0000 { - compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; - reg = <0xff3f0000 0x1000>; - interrupts = ; - rockchip,grf = <&pmugrf>; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@ff410000 { - compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; - reg = <0xff410000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 7>, <&dmac 6>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - pmucru: clock-controller@ff480000 { - compatible = "rockchip,rv1126-pmucru"; - reg = <0xff480000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff490000 { - compatible = "rockchip,rv1126-cru"; - reg = <0xff490000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - dmac: dma-controller@ff4e0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xff4e0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - uart0: serial@ff560000 { - compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; - reg = <0xff560000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 5>, <&dmac 4>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@ff570000 { - compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; - reg = <0xff570000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 9>, <&dmac 8>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@ff580000 { - compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; - reg = <0xff580000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 11>, <&dmac 10>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3m0_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@ff590000 { - compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; - reg = <0xff590000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 13>, <&dmac 12>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4m0_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@ff5a0000 { - compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; - reg = <0xff5a0000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 15>, <&dmac 14>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5m0_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - saradc: adc@ff5e0000 { - compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; - reg = <0xff5e0000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - timer0: timer@ff660000 { - compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; - reg = <0xff660000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - gmac: ethernet@ffc40000 { - compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; - reg = <0xffc40000 0x4000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, - <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, - <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_GMAC_A>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&stmmac_axi_setup>; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - emmc: mmc@ffc50000 { - compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0xffc50000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - power-domains = <&power RV1126_PD_NVM>; - status = "disabled"; - }; - - sdmmc: mmc@ffc60000 { - compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0xffc60000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - status = "disabled"; - }; - - sdio: mmc@ffc70000 { - compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0xffc70000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - power-domains = <&power RV1126_PD_SDIO>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1126-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@ff460000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff460000 0x100>; - interrupts = ; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff620000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff620000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff630000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff630000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff640000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff640000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff650000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff650000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rv1126-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi deleted file mode 100644 index 7cc785a63866..000000000000 --- a/arch/arm/boot/dts/s3c6400.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - */ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts deleted file mode 100644 index 17097da36f5e..000000000000 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6410 based Mini6410 board device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for FriendlyARM Mini6410 board which is based on - * Samsung's S3C6410 SoC. - */ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "FriendlyARM Mini6410 board based on S3C6410"; - compatible = "friendlyarm,mini6410", "samsung,s3c6410"; - - memory@50000000 { - device_type = "memory"; - reg = <0x50000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - fin_pll: oscillator-0 { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator-1 { - compatible = "fixed-clock"; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - srom-cs1-bus@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - davicom,no-eeprom; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - autorepeat; - - button-k1 { - label = "K1"; - gpios = <&gpn 0 GPIO_ACTIVE_LOW>; - linux,code = <2>; - debounce-interval = <20>; - }; - - button-k2 { - label = "K2"; - gpios = <&gpn 1 GPIO_ACTIVE_LOW>; - linux,code = <3>; - debounce-interval = <20>; - }; - - button-k3 { - label = "K3"; - gpios = <&gpn 2 GPIO_ACTIVE_LOW>; - linux,code = <4>; - debounce-interval = <20>; - }; - - button-k4 { - label = "K4"; - gpios = <&gpn 3 GPIO_ACTIVE_LOW>; - linux,code = <5>; - debounce-interval = <20>; - }; - - button-k5 { - label = "K5"; - gpios = <&gpn 4 GPIO_ACTIVE_LOW>; - linux,code = <6>; - debounce-interval = <20>; - }; - - button-k6 { - label = "K6"; - gpios = <&gpn 5 GPIO_ACTIVE_LOW>; - linux,code = <7>; - debounce-interval = <20>; - }; - - button-k7 { - label = "K7"; - gpios = <&gpl 11 GPIO_ACTIVE_LOW>; - linux,code = <8>; - debounce-interval = <20>; - }; - - button-k8 { - label = "K8"; - gpios = <&gpl 12 GPIO_ACTIVE_LOW>; - linux,code = <9>; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds>; - - led-1 { - label = "LED1"; - gpios = <&gpk 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "LED2"; - gpios = <&gpk 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - led-3 { - label = "LED3"; - gpios = <&gpk 6 GPIO_ACTIVE_LOW>; - }; - - led-4 { - label = "LED4"; - gpios = <&gpk 7 GPIO_ACTIVE_LOW>; - }; - }; - - buzzer { - compatible = "pwm-beeper"; - pwms = <&pwm 0 1000000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; - }; -}; - -&clocks { - clocks = <&fin_pll>; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; - -&pinctrl0 { - gpio_leds: gpio-leds-pins { - samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = ; - }; - - gpio_keys: gpio-keys-pins { - samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", - "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts deleted file mode 100644 index 581309e7f15e..000000000000 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung S3C6410 based SMDK6410 board device tree source. - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for Samsung SMDK6410 board which is based on - * Samsung's S3C6410 SoC. - */ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "Samsung SMDK6410 board based on S3C6410"; - compatible = "samsung,smdk6410", "samsung,s3c6410"; - - memory@50000000 { - device_type = "memory"; - reg = <0x50000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - fin_pll: oscillator-0 { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator-1 { - compatible = "fixed-clock"; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - srom-cs1-bus@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "smsc,lan9115"; - reg = <0x18000000 0x10000>; - interrupt-parent = <&gpn>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,force-internal-phy; - }; - }; -}; - -&clocks { - clocks = <&fin_pll>; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi deleted file mode 100644 index 13e9cc69b8a8..000000000000 --- a/arch/arm/boot/dts/s3c6410.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6410 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional - * nodes can be added to this file. - */ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6410"; - - aliases { - i2c1 = &i2c1; - }; -}; - -&vic0 { - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6410-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - - i2c1: i2c@7f00f000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f00f000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi deleted file mode 100644 index f53959b7d031..000000000000 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ /dev/null @@ -1,682 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C64xx SoC series common device tree source - * - pin control-related definitions - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are - * listed as device tree nodes in this file. - */ - -#include "s3c64xx-pinctrl.h" - -&pinctrl0 { - /* - * Pin banks - */ - - gpa: gpa-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc: gpc-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd: gpd-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe: gpe-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpi: gpi-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm: gpm-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpn: gpn-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpo: gpo-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpp: gpp-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpq: gpq-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data-pins { - samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ext_dma_0: ext-dma-0-pins { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ext_dma_1: ext-dma-1-pins { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_data_0: irda-data-0-pins { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_data_1: irda-data-1-pins { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_sdbw: irda-sdbw-pins { - samsung,pins = "gpb-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2c1_bus: i2c1-bus-pins { - /* S3C6410-only */ - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi0_cs: spi0-cs-pins { - samsung,pins = "gpc-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi1_cs: spi1-cs-pins { - samsung,pins = "gpc-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpg-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpg-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_bus1: sd0-bus1-pins { - samsung,pins = "gpg-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_bus4: sd0-bus4-pins { - samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpg-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gph-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gph-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus1: sd1-bus1-pins { - samsung,pins = "gph-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus4: sd1-bus4-pins { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus8: sd1-bus8-pins { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", - "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpg-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpc-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpc-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_bus1: sd2-bus1-pins { - samsung,pins = "gph-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_bus4: sd2-bus4-pins { - samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s0_bus: i2s0-bus-pins { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s0_cdclk: i2s0-cdclk-pins { - samsung,pins = "gpd-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s1_cdclk: i2s1-cdclk-pins { - samsung,pins = "gpe-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s2_bus: i2s2-bus-pins { - /* S3C6410-only */ - samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", - "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s2_cdclk: i2s2-cdclk-pins { - /* S3C6410-only */ - samsung,pins = "gph-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm0_bus: pcm0-bus-pins { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm0_extclk: pcm0-extclk-pins { - samsung,pins = "gpd-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm1_extclk: pcm1-extclk-pins { - samsung,pins = "gpe-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ac97_bus_0: ac97-bus-0-pins { - samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ac97_bus_1: ac97-bus-1-pins { - samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_port: cam-port-pins { - samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", - "gpf-5", "gpf-6", "gpf-7", "gpf-8", - "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_rst: cam-rst-pins { - samsung,pins = "gpf-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_field: cam-field-pins { - /* S3C6410-only */ - samsung,pins = "gpb-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm_extclk: pwm-extclk-pins { - samsung,pins = "gpf-13"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpf-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpf-15"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - clkout0: clkout-0-pins { - samsung,pins = "gpf-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col0_0: keypad-col0-0-pins { - samsung,pins = "gph-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col1_0: keypad-col1-0-pins { - samsung,pins = "gph-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col2_0: keypad-col2-0-pins { - samsung,pins = "gph-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col3_0: keypad-col3-0-pins { - samsung,pins = "gph-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col4_0: keypad-col4-0-pins { - samsung,pins = "gph-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col5_0: keypad-col5-0-pins { - samsung,pins = "gph-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col6_0: keypad-col6-0-pins { - samsung,pins = "gph-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col7_0: keypad-col7-0-pins { - samsung,pins = "gph-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col0_1: keypad-col0-1-pins { - samsung,pins = "gpl-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col1_1: keypad-col1-1-pins { - samsung,pins = "gpl-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col2_1: keypad-col2-1-pins { - samsung,pins = "gpl-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col3_1: keypad-col3-1-pins { - samsung,pins = "gpl-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col4_1: keypad-col4-1-pins { - samsung,pins = "gpl-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col5_1: keypad-col5-1-pins { - samsung,pins = "gpl-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col6_1: keypad-col6-1-pins { - samsung,pins = "gpl-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col7_1: keypad-col7-1-pins { - samsung,pins = "gpl-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row0_0: keypad-row0-0-pins { - samsung,pins = "gpk-8"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row1_0: keypad-row1-0-pins { - samsung,pins = "gpk-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row2_0: keypad-row2-0-pins { - samsung,pins = "gpk-10"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row3_0: keypad-row3-0-pins { - samsung,pins = "gpk-11"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row4_0: keypad-row4-0-pins { - samsung,pins = "gpk-12"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row5_0: keypad-row5-0-pins { - samsung,pins = "gpk-13"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row6_0: keypad-row6-0-pins { - samsung,pins = "gpk-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row7_0: keypad-row7-0-pins { - samsung,pins = "gpk-15"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row0_1: keypad-row0-1-pins { - samsung,pins = "gpn-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row1_1: keypad-row1-1-pins { - samsung,pins = "gpn-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row2_1: keypad-row2-1-pins { - samsung,pins = "gpn-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row3_1: keypad-row3-1-pins { - samsung,pins = "gpn-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row4_1: keypad-row4-1-pins { - samsung,pins = "gpn-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row5_1: keypad-row5-1-pins { - samsung,pins = "gpn-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row6_1: keypad-row6-1-pins { - samsung,pins = "gpn-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row7_1: keypad-row7-1-pins { - samsung,pins = "gpn-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_ctrl: lcd-ctrl-pins { - samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data16: lcd-data-width16-pins { - samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", - "gpi-7", "gpi-10", "gpi-11", "gpi-12", - "gpi-13", "gpi-14", "gpi-15", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data18: lcd-data-width18-pins { - samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", - "gpi-6", "gpi-7", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-2", "gpj-3", "gpj-4", "gpj-5", - "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data24: lcd-data-width24-pins { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6", "gpi-7", - "gpi-8", "gpi-9", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-0", "gpj-1", "gpj-2", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hsi_bus: hsi-bus-pins { - samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", - "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/s3c64xx-pinctrl.h deleted file mode 100644 index 645c591db357..000000000000 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung S3C64xx DTS pinctrl constants - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Linaro Ltd - * Author: Krzysztof Kozlowski - */ - -#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ -#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ - -#define S3C64XX_PIN_PULL_NONE 0 -#define S3C64XX_PIN_PULL_DOWN 1 -#define S3C64XX_PIN_PULL_UP 2 - -#define S3C64XX_PIN_FUNC_INPUT 0 -#define S3C64XX_PIN_FUNC_OUTPUT 1 -#define S3C64XX_PIN_FUNC_2 2 -#define S3C64XX_PIN_FUNC_3 3 -#define S3C64XX_PIN_FUNC_4 4 -#define S3C64XX_PIN_FUNC_5 5 -#define S3C64XX_PIN_FUNC_6 6 -#define S3C64XX_PIN_FUNC_EINT 7 - -#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi deleted file mode 100644 index 0b59135ffe88..000000000000 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C64xx SoC series common device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoC series device nodes are listed in this file. - * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional - * nodes can be added to this file. - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - pinctrl0 = &pinctrl0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s"; - reg = <0x0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic0: interrupt-controller@71200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@71300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71300000 0x1000>; - #interrupt-cells = <1>; - }; - - sdhci0: mmc@7c200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c200000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: mmc@7c300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c300000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <25>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: mmc@7c400000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c400000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <17>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - watchdog: watchdog@7e004000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x7e004000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks PCLK_WDT>; - }; - - i2c0: i2c@7f004000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f004000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <18>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@7f005000 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <5>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart1: serial@7f005400 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005400 0x100>; - interrupt-parent = <&vic1>; - interrupts = <6>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart2: serial@7f005800 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005800 0x100>; - interrupt-parent = <&vic1>; - interrupts = <7>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart3: serial@7f005c00 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005c00 0x100>; - interrupt-parent = <&vic1>; - interrupts = <8>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - pwm: pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clock-names = "timers"; - clocks = <&clocks PCLK_PWM>; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - }; - - pinctrl0: pinctrl@7f008000 { - compatible = "samsung,s3c64xx-pinctrl"; - reg = <0x7f008000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <21>; - - wakeup-interrupt-controller { - compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts-extended = <&vic0 0>, - <&vic0 1>, - <&vic1 0>, - <&vic1 1>; - }; - }; - }; -}; - -#include "s3c64xx-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts deleted file mode 100644 index 0f5c6cd0f3a1..000000000000 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ /dev/null @@ -1,398 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Samsung Aquila board. - */ - -/dts-v1/; -#include -#include -#include "s5pv210.dtsi" - -/ { - model = "Samsung Aquila based on S5PC110"; - compatible = "samsung,aquila", "samsung,s5pv210"; - - aliases { - i2c3 = &i2c_pmic; - }; - - chosen { - bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>; - }; - - pmic_ap_clk: clock-0 { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - vtf_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pda_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - bat_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - i2c_pmic: i2c-pmic { - compatible = "i2c-gpio"; - sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, - <&gph0 4 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VCC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC+VCAM_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_IO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_ISP_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_CIF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_8M_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VARM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VINT_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-always-on; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gph2 6 1>; - linux,code = ; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; - status = "okay"; - - key-1 { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key-2 { - keypad,row = <0>; - keypad,column = <2>; - linux,code = ; - }; - - key-3 { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key-4 { - keypad,row = <1>; - keypad,column = <2>; - linux,code = ; - }; - - key-5 { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; - - key-6 { - keypad,row = <2>; - keypad,column = <2>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - status = "okay"; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; - pinctrl-names = "default"; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 1>; - vmmc-supply = <&vtf_reg>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>; - pinctrl-names = "default"; - status = "okay"; -}; - -&onenand { - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo3_reg>; - vusb_d-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <0>; - hactive = <800>; - vactive = <480>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vback-porch = <3>; - vfront-porch = <28>; - vsync-len = <1>; - }; - }; -}; - -&pinctrl0 { - t_flash_detect: t-flash-detect-pins { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi deleted file mode 100644 index f628d3660493..000000000000 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ /dev/null @@ -1,916 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 based Galaxy Aries board device tree source - */ - -/dts-v1/; -#include -#include -#include "s5pv210.dtsi" - -/ { - compatible = "samsung,aries", "samsung,s5pv210"; - - aliases: aliases { - i2c4 = &i2c_sound; - i2c5 = &i2c_accel; - i2c6 = &i2c_pmic; - i2c7 = &i2c_musb; - i2c9 = &i2c_fuel; - i2c10 = &i2c_touchkey; - i2c11 = &i2c_prox; - i2c12 = &i2c_magnetometer; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000>, - <0x40000000 0x10000000>, - <0x50000000 0x08000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x2000000>; - }; - - mfc_right: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x2000000>; - }; - }; - - pmic_ap_clk: clock-0 { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - bt_codec: bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <0>; - }; - - vibrator_pwr: regulator-fixed-0 { - compatible = "regulator-fixed"; - regulator-name = "vibrator-en"; - enable-active-high; - gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_ena>; - }; - - touchkey_vdd: regulator-fixed-1 { - compatible = "regulator-fixed"; - regulator-name = "VTOUCH_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_vdd_ena>; - }; - - gp2a_vled: regulator-fixed-2 { - compatible = "regulator-fixed"; - regulator-name = "VLED"; - enable-active-high; - gpio = <&gpj1 4 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gp2a_power>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_gpio_rst>; - post-power-on-delay-ms = <500>; - power-off-delay-us = <500>; - }; - - i2c_sound: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&sound_i2c_pins>; - - wm8994: audio-codec@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; - - #sound-dai-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - clocks = <&clocks MOUT_CLKOUT>; - clock-names = "MCLK1"; - - AVDD2-supply = <&buck3_reg>; - DBVDD-supply = <&buck3_reg>; - CPVDD-supply = <&buck3_reg>; - SPKVDD1-supply = <&buck3_reg>; - SPKVDD2-supply = <&buck3_reg>; - - wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100 - 0xa101 0x0100 0x8100 0x0100 0x0100 - 0x0100>; - - wlf,ldo1ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>; - - wlf,lineout1-se; - wlf,lineout2-se; - - assigned-clocks = <&clocks MOUT_CLKOUT>; - assigned-clock-rates = <0>; - assigned-clock-parents = <&xusbxti>; - - pinctrl-names = "default"; - pinctrl-0 = <&codec_ldo>; - }; - }; - - i2c_accel: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&accel_i2c_pins>; - - accelerometer@38 { - compatible = "bosch,bma023"; - reg = <0x38>; - - vdd-supply = <&ldo9_reg>; - vddio-supply = <&ldo9_reg>; - }; - }; - - i2c_pmic: i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_i2c_pins>; - - pmic@66 { - compatible = "maxim,max8998"; - reg = <0x66>; - interrupt-parent = <&gph0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - - max8998,pmic-buck1-default-dvs-idx = <1>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, - <&gph0 4 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, - <1050000>, <950000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_dvs_pins &pmic_irq>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3600000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_AF_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "VGA_VDDIO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "VGA_DVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_ISP_HOST_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VGA_AVDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "vddarm"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1250000>; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vddint"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - cp32khz_reg: EN32KHz-CP { - regulator-name = "32KHz CP"; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - }; - }; - }; - }; - - i2c_musb: i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&musb_i2c_pins>; - - fsa9480: musb@25 { - compatible = "fcs,fsa9480"; - reg = <0x25>; - interrupt-parent = <&gph2>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&musb_irq>; - }; - }; - - i2c_fuel: i2c-gpio-4 { - compatible = "i2c-gpio"; - sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&fg_i2c_pins>; - - fg: fuelgauge@36 { - compatible = "maxim,max17040"; - reg = <0x36>; - }; - }; - - i2c_touchkey: i2c-gpio-5 { - compatible = "i2c-gpio"; - sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_i2c_pins>; - - touchkey@20 { - compatible = "cypress,aries-touchkey"; - reg = <0x20>; - vdd-supply = <&touchkey_vdd>; - vcc-supply = <&buck3_reg>; - linux,keycodes = ; - interrupt-parent = <&gpj4>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_irq>; - }; - }; - - i2c_prox: i2c-gpio-6 { - compatible = "i2c-gpio"; - sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&prox_i2c_pins>; - - light-sensor@44 { - compatible = "sharp,gp2ap002a00f"; - reg = <0x44>; - interrupt-parent = <&gph0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&gp2a_vled>; - vio-supply = <&gp2a_vled>; - io-channels = <&gp2a_shunt>; - io-channel-names = "alsout"; - sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; - sharp,proximity-close-hysteresis = /bits/ 8 <0x20>; - - pinctrl-names = "default"; - pinctrl-0 = <&gp2a_irq>; - }; - }; - - i2c_magnetometer: i2c-gpio-7 { - compatible = "i2c-gpio"; - sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&magnetometer_i2c_pins>; - - status = "disabled"; - - /* Yamaha yas529 magnetometer, no mainline binding */ - }; - - vibrator: pwm-vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm 1 44642 0>; - pwm-names = "enable"; - vcc-supply = <&vibrator_pwr>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; - }; - - poweroff: syscon-poweroff { - compatible = "syscon-poweroff"; - regmap = <&pmu_syscon>; - offset = <0x681c>; /* PS_HOLD_CONTROL */ - value = <0x5200>; - }; - - spi_lcd: spi-2 { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>; - cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_spi_pins>; - - panel@0 { - compatible = "samsung,s6e63m0"; - reg = <0>; - reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; - vdd3-supply = <&ldo7_reg>; - vci-supply = <&ldo17_reg>; - spi-max-frequency = <1200000>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_rst>; - - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_ep>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo4_reg>; - - status = "okay"; - - gp2a_shunt: current-sense-shunt { - compatible = "current-sense-shunt"; - io-channels = <&adc 9>; - shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */ - #io-channel-cells = <0>; - }; -}; - -&fimd { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_clk &lcd_data24>; - status = "okay"; - - samsung,invert-vden; - samsung,invert-vclk; - - #address-cells = <1>; - #size-cells = <0>; - - port@3 { - reg = <3>; - fimd_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; -}; - -&hsotg { - vusb_a-supply = <&ldo8_reg>; - vusb_d-supply = <&ldo3_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpj0>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_irq>; - reset-gpios = <&gpj1 3 GPIO_ACTIVE_LOW>; - }; -}; - -&i2s0 { - dmas = <&pdma0 10>, <&pdma0 9>, <&pdma0 11>; - status = "okay"; -}; - -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - -&pinctrl0 { - bt_reset: bt-reset-pins { - samsung,pins = "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wlan_bt_en: wlan-bt-en-pins { - samsung,pins = "gpb-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-val = <1>; - }; - - codec_ldo: codec-ldo-pins { - samsung,pins = "gpf3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - prox_i2c_pins: gp2a-i2c-pins { - samsung,pins = "gpg0-2", "gpg2-2"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wlan_gpio_rst: wlan-gpio-rst-pins { - samsung,pins = "gpg1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - bt_wake: bt-wake-pins { - samsung,pins = "gpg3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - gp2a_irq: gp2a-irq-pins { - samsung,pins = "gph0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_pins: pmic-dvs-pins { - samsung,pins = "gph0-3", "gph0-4", "gph0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - pmic_irq: pmic-irq-pins { - samsung,pins = "gph0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wifi_host_wake: wifi-host-wake-pins { - samsung,pins = "gph2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - bt_host_wake: bt-host-wake-pins { - samsung,pins = "gph2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - musb_irq: musq-irq-pins { - samsung,pins = "gph2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tf_detect: tf-detect-pins { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wifi_wake: wifi-wake-pins { - samsung,pins = "gph3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - magnetometer_i2c_pins: yas529-i2c-pins { - samsung,pins = "gpj0-0", "gpj0-1"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ts_irq: ts-irq-pins { - samsung,pins = "gpj0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - vibrator_ena: vibrator-ena-pins { - samsung,pins = "gpj1-1"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - gp2a_power: gp2a-power-pins { - samsung,pins = "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - touchkey_i2c_pins: touchkey-i2c-pins { - samsung,pins = "gpj3-0", "gpj3-1"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - touchkey_vdd_ena: touchkey-vdd-ena-pins { - samsung,pins = "gpj3-2"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - musb_i2c_pins: musb-i2c-pins { - samsung,pins = "gpj3-4", "gpj3-5"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - accel_i2c_pins: accel-i2c-pins { - samsung,pins = "gpj3-6", "gpj3-7"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_i2c_pins: pmic-i2c-pins { - samsung,pins = "gpj4-0", "gpj4-3"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - touchkey_irq: touchkey-irq-pins { - samsung,pins = "gpj4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_spi_pins: spi-lcd-pins { - samsung,pins = "mp01-1", "mp04-1", "mp04-3"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fg_i2c_pins: fg-i2c-pins { - samsung,pins = "mp05-0", "mp05-1"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sound_i2c_pins: sound-i2c-pins { - samsung,pins = "mp05-2", "mp05-3"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - panel_rst: panel-rst-pins { - samsung,pins = "mp05-5"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - samsung,pwm-outputs = <1>; -}; - -&rtc { - clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci1 { - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - max-frequency = <38400000>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; - pinctrl-names = "default"; - cap-sd-highspeed; - cap-mmc-highspeed; - keep-power-in-suspend; - - mmc-pwrseq = <&wifi_pwrseq>; - non-removable; - status = "okay"; - - assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>; - assigned-clock-rates = <0>, <50000000>; - assigned-clock-parents = <&clocks MOUT_MPLL>; - - wlan@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gph2>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>; - assigned-clock-rates = <0>, <50000000>; - assigned-clock-parents = <&clocks MOUT_MPLL>; -}; - -&uart0 { - assigned-clocks = <&clocks MOUT_UART0>, <&clocks SCLK_UART0>; - assigned-clock-rates = <0>, <111166667>; - assigned-clock-parents = <&clocks MOUT_MPLL>; - - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4329-bt"; - max-speed = <3000000>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake - &bt_reset &bt_wake>; - shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&gph2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; - vbus-supply = <&safe1_sreg>; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts deleted file mode 100644 index eaa7c4f0e257..000000000000 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; -#include -#include -#include "s5pv210-aries.dtsi" - -/ { - model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; - compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; - chassis-type = "handset"; - - chosen { - stdout-path = &uart2; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "power"; - gpios = <&gph2 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-vol-down { - label = "volume_down"; - gpios = <&gph3 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-vol-up { - label = "volume_up"; - gpios = <&gph3 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - headset_micbias_reg: regulator-fixed-3 { - compatible = "regulator-fixed"; - regulator-name = "Headset_Micbias"; - gpio = <&gpj2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&headset_micbias_ena>; - }; - - main_micbias_reg: regulator-fixed-4 { - compatible = "regulator-fixed"; - regulator-name = "Main_Micbias"; - gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&main_micbias_ena>; - }; - - sound { - compatible = "samsung,fascinate4g-wm8994"; - - model = "Fascinate4G"; - - extcon = <&fsa9480>; - - main-micbias-supply = <&main_micbias_reg>; - headset-micbias-supply = <&headset_micbias_reg>; - - earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; - - io-channels = <&adc 3>; - io-channel-names = "headset-detect"; - headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>; - headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; - - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", - - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", - - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", - - "IN1LP", "Main Mic", - "IN1LN", "Main Mic", - - "IN1RP", "Headset Mic", - "IN1RN", "Headset Mic", - - "Modem Out", "Modem TX", - "Modem RX", "Modem In", - - "Bluetooth SPK", "TX", - "RX", "Bluetooth Mic"; - - pinctrl-names = "default"; - pinctrl-0 = <&headset_det &earpath_sel>; - - cpu { - sound-dai = <&i2s0>, <&bt_codec>; - }; - - codec { - sound-dai = <&wm8994>; - }; - }; -}; - -&fg { - compatible = "maxim,max77836-battery"; - - interrupt-parent = <&gph3>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fg_irq>; -}; - -&pinctrl0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep_cfg>; - - headset_det: headset-det-pins { - samsung,pins = "gph0-6", "gph3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - fg_irq: fg-irq-pins { - samsung,pins = "gph3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - headset_micbias_ena: headset-micbias-ena-pins { - samsung,pins = "gpj2-5"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - earpath_sel: earpath-sel-pins { - samsung,pins = "gpj2-6"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - main_micbias_ena: main-micbias-ena-pins { - samsung,pins = "gpj4-2"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* Based on vendor kernel v2.6.35.7 */ - sleep_cfg: sleep-state { - PIN_SLP(gpa0-0, PREV, NONE); - PIN_SLP(gpa0-1, PREV, NONE); - PIN_SLP(gpa0-2, PREV, NONE); - PIN_SLP(gpa0-3, OUT1, NONE); - PIN_SLP(gpa0-4, PREV, NONE); - PIN_SLP(gpa0-5, PREV, NONE); - PIN_SLP(gpa0-6, PREV, NONE); - PIN_SLP(gpa0-7, PREV, NONE); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, OUT0, NONE); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, OUT0, NONE); - - PIN_SLP(gpb-0, OUT0, NONE); - PIN_SLP(gpb-1, OUT1, NONE); - PIN_SLP(gpb-2, OUT0, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, NONE); - PIN_SLP(gpb-5, PREV, NONE); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, OUT0, NONE); - - PIN_SLP(gpc0-0, OUT0, NONE); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, OUT0, NONE); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, OUT0, NONE); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, OUT0, NONE); - PIN_SLP(gpd0-2, INPUT, DOWN); - PIN_SLP(gpd0-3, INPUT, DOWN); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, DOWN); - PIN_SLP(gpd1-3, INPUT, DOWN); - PIN_SLP(gpd1-4, INPUT, DOWN); - PIN_SLP(gpd1-5, INPUT, DOWN); - - PIN_SLP(gpe0-0, INPUT, DOWN); - PIN_SLP(gpe0-1, INPUT, DOWN); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, DOWN); - PIN_SLP(gpe0-4, INPUT, DOWN); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, INPUT, DOWN); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, OUT0, NONE); - PIN_SLP(gpe1-4, INPUT, DOWN); - - PIN_SLP(gpf0-0, OUT0, NONE); - PIN_SLP(gpf0-1, OUT0, NONE); - PIN_SLP(gpf0-2, OUT0, NONE); - PIN_SLP(gpf0-3, OUT0, NONE); - PIN_SLP(gpf0-4, OUT0, NONE); - PIN_SLP(gpf0-5, OUT0, NONE); - PIN_SLP(gpf0-6, OUT0, NONE); - PIN_SLP(gpf0-7, OUT0, NONE); - - PIN_SLP(gpf1-0, OUT0, NONE); - PIN_SLP(gpf1-1, OUT0, NONE); - PIN_SLP(gpf1-2, OUT0, NONE); - PIN_SLP(gpf1-3, OUT0, NONE); - PIN_SLP(gpf1-4, OUT0, NONE); - PIN_SLP(gpf1-5, OUT0, NONE); - PIN_SLP(gpf1-6, OUT0, NONE); - PIN_SLP(gpf1-7, OUT0, NONE); - - PIN_SLP(gpf2-0, OUT0, NONE); - PIN_SLP(gpf2-1, OUT0, NONE); - PIN_SLP(gpf2-2, OUT0, NONE); - PIN_SLP(gpf2-3, OUT0, NONE); - PIN_SLP(gpf2-4, OUT0, NONE); - PIN_SLP(gpf2-5, OUT0, NONE); - PIN_SLP(gpf2-6, OUT0, NONE); - PIN_SLP(gpf2-7, OUT0, NONE); - - PIN_SLP(gpf3-0, OUT0, NONE); - PIN_SLP(gpf3-1, OUT0, NONE); - PIN_SLP(gpf3-2, OUT0, NONE); - PIN_SLP(gpf3-3, OUT0, NONE); - PIN_SLP(gpf3-4, PREV, NONE); - PIN_SLP(gpf3-5, INPUT, DOWN); - - PIN_SLP(gpg0-0, INPUT, DOWN); - PIN_SLP(gpg0-1, INPUT, DOWN); - PIN_SLP(gpg0-2, INPUT, NONE); - PIN_SLP(gpg0-3, INPUT, DOWN); - PIN_SLP(gpg0-4, INPUT, DOWN); - PIN_SLP(gpg0-5, INPUT, DOWN); - PIN_SLP(gpg0-6, INPUT, DOWN); - - PIN_SLP(gpg1-0, OUT0, NONE); - PIN_SLP(gpg1-1, OUT1, NONE); - PIN_SLP(gpg1-2, PREV, NONE); - PIN_SLP(gpg1-3, OUT1, NONE); - PIN_SLP(gpg1-4, OUT1, NONE); - PIN_SLP(gpg1-5, OUT1, NONE); - PIN_SLP(gpg1-6, OUT1, NONE); - - PIN_SLP(gpg2-0, OUT0, NONE); - PIN_SLP(gpg2-1, OUT0, NONE); - PIN_SLP(gpg2-2, INPUT, NONE); - PIN_SLP(gpg2-3, OUT0, NONE); - PIN_SLP(gpg2-4, OUT0, NONE); - PIN_SLP(gpg2-5, OUT0, NONE); - PIN_SLP(gpg2-6, OUT0, NONE); - - PIN_SLP(gpg3-0, PREV, UP); - PIN_SLP(gpg3-1, PREV, UP); - PIN_SLP(gpg3-2, INPUT, NONE); - PIN_SLP(gpg3-3, INPUT, DOWN); - PIN_SLP(gpg3-4, OUT0, NONE); - PIN_SLP(gpg3-5, OUT0, NONE); - PIN_SLP(gpg3-6, INPUT, DOWN); - - PIN_SLP(gpi-0, PREV, NONE); - PIN_SLP(gpi-1, INPUT, DOWN); - PIN_SLP(gpi-2, PREV, NONE); - PIN_SLP(gpi-3, PREV, NONE); - PIN_SLP(gpi-4, PREV, NONE); - PIN_SLP(gpi-5, INPUT, DOWN); - PIN_SLP(gpi-6, INPUT, DOWN); - - PIN_SLP(gpj0-0, INPUT, NONE); - PIN_SLP(gpj0-1, INPUT, NONE); - PIN_SLP(gpj0-2, INPUT, NONE); - PIN_SLP(gpj0-3, INPUT, NONE); - PIN_SLP(gpj0-4, INPUT, NONE); - PIN_SLP(gpj0-5, INPUT, DOWN); - PIN_SLP(gpj0-6, OUT0, NONE); - PIN_SLP(gpj0-7, INPUT, NONE); - - PIN_SLP(gpj1-0, OUT1, NONE); - PIN_SLP(gpj1-1, OUT0, NONE); - PIN_SLP(gpj1-2, INPUT, DOWN); - PIN_SLP(gpj1-3, PREV, NONE); - PIN_SLP(gpj1-4, PREV, NONE); - PIN_SLP(gpj1-5, OUT0, NONE); - - PIN_SLP(gpj2-0, INPUT, DOWN); - PIN_SLP(gpj2-1, INPUT, DOWN); - PIN_SLP(gpj2-2, OUT0, NONE); - PIN_SLP(gpj2-3, INPUT, DOWN); - PIN_SLP(gpj2-4, INPUT, DOWN); - PIN_SLP(gpj2-5, PREV, NONE); - PIN_SLP(gpj2-6, PREV, NONE); - PIN_SLP(gpj2-7, INPUT, DOWN); - - PIN_SLP(gpj3-0, INPUT, NONE); - PIN_SLP(gpj3-1, INPUT, NONE); - PIN_SLP(gpj3-2, OUT0, NONE); - PIN_SLP(gpj3-3, INPUT, DOWN); - PIN_SLP(gpj3-4, INPUT, NONE); - PIN_SLP(gpj3-5, INPUT, NONE); - PIN_SLP(gpj3-6, INPUT, NONE); - PIN_SLP(gpj3-7, INPUT, NONE); - - PIN_SLP(gpj4-0, INPUT, NONE); - PIN_SLP(gpj4-1, INPUT, DOWN); - PIN_SLP(gpj4-2, PREV, NONE); - PIN_SLP(gpj4-3, INPUT, NONE); - PIN_SLP(gpj4-4, INPUT, DOWN); - - PIN_SLP(mp01-0, OUT1, NONE); - PIN_SLP(mp01-1, OUT0, NONE); - PIN_SLP(mp01-2, INPUT, DOWN); - PIN_SLP(mp01-3, INPUT, DOWN); - PIN_SLP(mp01-4, OUT1, NONE); - PIN_SLP(mp01-5, INPUT, DOWN); - PIN_SLP(mp01-6, INPUT, DOWN); - PIN_SLP(mp01-7, INPUT, DOWN); - - PIN_SLP(mp02-0, INPUT, DOWN); - PIN_SLP(mp02-1, INPUT, DOWN); - PIN_SLP(mp02-2, INPUT, NONE); - PIN_SLP(mp02-3, INPUT, DOWN); - - PIN_SLP(mp03-0, INPUT, DOWN); - PIN_SLP(mp03-1, INPUT, DOWN); - PIN_SLP(mp03-2, OUT1, NONE); - PIN_SLP(mp03-3, OUT0, NONE); - PIN_SLP(mp03-4, INPUT, NONE); - PIN_SLP(mp03-5, OUT0, NONE); - PIN_SLP(mp03-6, INPUT, DOWN); - PIN_SLP(mp03-7, INPUT, DOWN); - - PIN_SLP(mp04-0, INPUT, DOWN); - PIN_SLP(mp04-1, OUT0, NONE); - PIN_SLP(mp04-2, INPUT, DOWN); - PIN_SLP(mp04-3, OUT0, NONE); - PIN_SLP(mp04-4, INPUT, DOWN); - PIN_SLP(mp04-5, INPUT, DOWN); - PIN_SLP(mp04-6, OUT0, NONE); - PIN_SLP(mp04-7, INPUT, DOWN); - - PIN_SLP(mp05-0, INPUT, NONE); - PIN_SLP(mp05-1, INPUT, NONE); - PIN_SLP(mp05-2, INPUT, NONE); - PIN_SLP(mp05-3, INPUT, NONE); - PIN_SLP(mp05-4, INPUT, DOWN); - PIN_SLP(mp05-5, OUT0, NONE); - PIN_SLP(mp05-6, INPUT, DOWN); - PIN_SLP(mp05-7, PREV, NONE); - - PIN_SLP(mp06-0, INPUT, DOWN); - PIN_SLP(mp06-1, INPUT, DOWN); - PIN_SLP(mp06-2, INPUT, DOWN); - PIN_SLP(mp06-3, INPUT, DOWN); - PIN_SLP(mp06-4, INPUT, DOWN); - PIN_SLP(mp06-5, INPUT, DOWN); - PIN_SLP(mp06-6, INPUT, DOWN); - PIN_SLP(mp06-7, INPUT, DOWN); - - PIN_SLP(mp07-0, INPUT, DOWN); - PIN_SLP(mp07-1, INPUT, DOWN); - PIN_SLP(mp07-2, INPUT, DOWN); - PIN_SLP(mp07-3, INPUT, DOWN); - PIN_SLP(mp07-4, INPUT, DOWN); - PIN_SLP(mp07-5, INPUT, DOWN); - PIN_SLP(mp07-6, INPUT, DOWN); - PIN_SLP(mp07-7, INPUT, DOWN); - }; -}; - -&wm8994 { - /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */ - wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101 - 0x0100 0x8100 0x0100 0x0100 0x0100>; -}; diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts deleted file mode 100644 index 532d3f5bceb1..000000000000 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; -#include -#include -#include "s5pv210-aries.dtsi" - -/ { - model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; - compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; - chassis-type = "handset"; - - chosen { - stdout-path = &uart2; - }; - - nand_pwrseq: nand-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&massmemory_en>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "power"; - gpios = <&gph2 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-vol-down { - label = "volume_down"; - gpios = <&gph3 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-vol-up { - label = "volume_up"; - gpios = <&gph3 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-home { - label = "home"; - gpios = <&gph3 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - i2c_fmradio: i2c-gpio-8 { - compatible = "i2c-gpio"; - sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&fm_i2c_pins>; - - fmradio@10 { - compatible = "silabs,si470x"; - reg = <0x10>; - interrupt-parent = <&gpj2>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&fm_irq &fm_rst>; - }; - }; - - micbias_reg: regulator-fixed-3 { - compatible = "regulator-fixed"; - regulator-name = "MICBIAS"; - gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&micbias_reg_ena>; - }; - - sound { - compatible = "samsung,aries-wm8994"; - - model = "Aries"; - - extcon = <&fsa9480>; - - main-micbias-supply = <&micbias_reg>; - headset-micbias-supply = <&micbias_reg>; - - earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; - - io-channels = <&adc 3>; - io-channel-names = "headset-detect"; - headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>; - headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; - - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", - - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", - - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", - - "IN1LP", "Main Mic", - "IN1LN", "Main Mic", - - "IN1RP", "Headset Mic", - "IN1RN", "Headset Mic", - - "IN2LN", "FM In", - "IN2RN", "FM In", - - "Modem Out", "Modem TX", - "Modem RX", "Modem In", - - "Bluetooth SPK", "TX", - "RX", "Bluetooth Mic"; - - pinctrl-names = "default"; - pinctrl-0 = <&headset_det &earpath_sel>; - - cpu { - sound-dai = <&i2s0>, <&bt_codec>; - }; - - codec { - sound-dai = <&wm8994>; - }; - }; -}; - -&aliases { - i2c8 = &i2c_fmradio; -}; - -&pinctrl0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep_cfg>; - - fm_i2c_pins: fm-i2c-pins { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - headset_det: headset-det-pins { - samsung,pins = "gph0-6", "gph3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - fm_irq: fm-irq-pins { - samsung,pins = "gpj2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fm_rst: fm-rst-pins { - samsung,pins = "gpj2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - earpath_sel: earpath-sel-pins { - samsung,pins = "gpj2-6"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - massmemory_en: massmemory-en-pins { - samsung,pins = "gpj2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - micbias_reg_ena: micbias-reg-ena-pins { - samsung,pins = "gpj4-2"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* Based on CyanogenMod 3.0.101 kernel */ - sleep_cfg: sleep-state { - PIN_SLP(gpa0-0, PREV, NONE); - PIN_SLP(gpa0-1, PREV, NONE); - PIN_SLP(gpa0-2, PREV, NONE); - PIN_SLP(gpa0-3, OUT1, NONE); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, OUT0, NONE); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, OUT1, NONE); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, OUT0, NONE); - PIN_SLP(gpa1-2, INPUT, NONE); - PIN_SLP(gpa1-3, OUT0, NONE); - - PIN_SLP(gpb-0, OUT0, NONE); - PIN_SLP(gpb-1, OUT1, NONE); - PIN_SLP(gpb-2, OUT0, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, NONE); - PIN_SLP(gpb-5, PREV, NONE); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, OUT0, NONE); - - PIN_SLP(gpc0-0, OUT0, NONE); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, OUT0, NONE); - PIN_SLP(gpc0-3, INPUT, NONE); - PIN_SLP(gpc0-4, OUT0, NONE); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, OUT0, NONE); - PIN_SLP(gpd0-2, INPUT, DOWN); - PIN_SLP(gpd0-3, INPUT, DOWN); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - PIN_SLP(gpd1-4, INPUT, DOWN); - PIN_SLP(gpd1-5, INPUT, DOWN); - - PIN_SLP(gpe0-0, INPUT, DOWN); - PIN_SLP(gpe0-1, INPUT, DOWN); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, DOWN); - PIN_SLP(gpe0-4, INPUT, DOWN); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, INPUT, DOWN); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, OUT0, NONE); - PIN_SLP(gpe1-4, INPUT, DOWN); - - PIN_SLP(gpf0-0, OUT0, NONE); - PIN_SLP(gpf0-1, OUT0, NONE); - PIN_SLP(gpf0-2, OUT0, NONE); - PIN_SLP(gpf0-3, OUT0, NONE); - PIN_SLP(gpf0-4, OUT0, NONE); - PIN_SLP(gpf0-5, OUT0, NONE); - PIN_SLP(gpf0-6, OUT0, NONE); - PIN_SLP(gpf0-7, OUT0, NONE); - - PIN_SLP(gpf1-0, OUT0, NONE); - PIN_SLP(gpf1-1, OUT0, NONE); - PIN_SLP(gpf1-2, OUT0, NONE); - PIN_SLP(gpf1-3, OUT0, NONE); - PIN_SLP(gpf1-4, OUT0, NONE); - PIN_SLP(gpf1-5, OUT0, NONE); - PIN_SLP(gpf1-6, OUT0, NONE); - PIN_SLP(gpf1-7, OUT0, NONE); - - PIN_SLP(gpf2-0, OUT0, NONE); - PIN_SLP(gpf2-1, OUT0, NONE); - PIN_SLP(gpf2-2, OUT0, NONE); - PIN_SLP(gpf2-3, OUT0, NONE); - PIN_SLP(gpf2-4, OUT0, NONE); - PIN_SLP(gpf2-5, OUT0, NONE); - PIN_SLP(gpf2-6, OUT0, NONE); - PIN_SLP(gpf2-7, OUT0, NONE); - - PIN_SLP(gpf3-0, OUT0, NONE); - PIN_SLP(gpf3-1, OUT0, NONE); - PIN_SLP(gpf3-2, OUT0, NONE); - PIN_SLP(gpf3-3, OUT0, NONE); - PIN_SLP(gpf3-4, PREV, NONE); - PIN_SLP(gpf3-5, INPUT, DOWN); - - PIN_SLP(gpg0-0, OUT0, NONE); - PIN_SLP(gpg0-1, INPUT, NONE); - PIN_SLP(gpg0-2, INPUT, NONE); - PIN_SLP(gpg0-3, INPUT, NONE); - PIN_SLP(gpg0-4, INPUT, NONE); - PIN_SLP(gpg0-5, INPUT, NONE); - PIN_SLP(gpg0-6, INPUT, NONE); - - PIN_SLP(gpg1-0, OUT0, NONE); - PIN_SLP(gpg1-1, OUT1, NONE); - PIN_SLP(gpg1-2, PREV, NONE); - PIN_SLP(gpg1-3, OUT1, NONE); - PIN_SLP(gpg1-4, OUT1, NONE); - PIN_SLP(gpg1-5, OUT1, NONE); - PIN_SLP(gpg1-6, OUT1, NONE); - - PIN_SLP(gpg2-0, OUT0, NONE); - PIN_SLP(gpg2-1, OUT0, NONE); - PIN_SLP(gpg2-2, INPUT, NONE); - PIN_SLP(gpg2-3, OUT0, NONE); - PIN_SLP(gpg2-4, OUT0, NONE); - PIN_SLP(gpg2-5, OUT0, NONE); - PIN_SLP(gpg2-6, OUT0, NONE); - - PIN_SLP(gpg3-0, OUT1, NONE); - PIN_SLP(gpg3-1, OUT0, NONE); - PIN_SLP(gpg3-2, INPUT, NONE); - PIN_SLP(gpg3-3, INPUT, DOWN); - PIN_SLP(gpg3-4, OUT0, NONE); - PIN_SLP(gpg3-5, OUT0, NONE); - PIN_SLP(gpg3-6, INPUT, DOWN); - - PIN_SLP(gpi-0, PREV, NONE); - PIN_SLP(gpi-1, INPUT, DOWN); - PIN_SLP(gpi-2, PREV, NONE); - PIN_SLP(gpi-3, PREV, NONE); - PIN_SLP(gpi-4, PREV, NONE); - PIN_SLP(gpi-5, INPUT, DOWN); - PIN_SLP(gpi-6, INPUT, DOWN); - - PIN_SLP(gpj0-0, INPUT, NONE); - PIN_SLP(gpj0-1, INPUT, NONE); - PIN_SLP(gpj0-2, INPUT, NONE); - PIN_SLP(gpj0-3, INPUT, NONE); - PIN_SLP(gpj0-4, INPUT, NONE); - PIN_SLP(gpj0-5, INPUT, DOWN); - PIN_SLP(gpj0-6, OUT0, NONE); - PIN_SLP(gpj0-7, INPUT, NONE); - - PIN_SLP(gpj1-0, INPUT, DOWN); - PIN_SLP(gpj1-1, OUT0, NONE); - PIN_SLP(gpj1-2, INPUT, DOWN); - PIN_SLP(gpj1-3, PREV, NONE); - PIN_SLP(gpj1-4, PREV, NONE); - PIN_SLP(gpj1-5, OUT0, NONE); - - PIN_SLP(gpj2-0, INPUT, DOWN); - PIN_SLP(gpj2-1, INPUT, DOWN); - PIN_SLP(gpj2-2, OUT0, NONE); - PIN_SLP(gpj2-3, INPUT, DOWN); - PIN_SLP(gpj2-4, INPUT, UP); - PIN_SLP(gpj2-5, PREV, NONE); - PIN_SLP(gpj2-6, PREV, NONE); - PIN_SLP(gpj2-7, OUT1, NONE); - - PIN_SLP(gpj3-0, INPUT, NONE); - PIN_SLP(gpj3-1, INPUT, NONE); - PIN_SLP(gpj3-2, OUT0, NONE); - PIN_SLP(gpj3-3, INPUT, DOWN); - PIN_SLP(gpj3-4, INPUT, NONE); - PIN_SLP(gpj3-5, INPUT, NONE); - PIN_SLP(gpj3-6, INPUT, NONE); - PIN_SLP(gpj3-7, INPUT, NONE); - - PIN_SLP(gpj4-0, INPUT, NONE); - PIN_SLP(gpj4-1, INPUT, DOWN); - PIN_SLP(gpj4-2, PREV, NONE); - PIN_SLP(gpj4-3, INPUT, NONE); - PIN_SLP(gpj4-4, INPUT, DOWN); - - PIN_SLP(mp01-0, INPUT, DOWN); - PIN_SLP(mp01-1, OUT0, NONE); - PIN_SLP(mp01-2, INPUT, DOWN); - PIN_SLP(mp01-3, INPUT, DOWN); - PIN_SLP(mp01-4, OUT1, NONE); - PIN_SLP(mp01-5, INPUT, DOWN); - PIN_SLP(mp01-6, INPUT, DOWN); - PIN_SLP(mp01-7, INPUT, DOWN); - - PIN_SLP(mp02-0, INPUT, DOWN); - PIN_SLP(mp02-1, INPUT, DOWN); - PIN_SLP(mp02-2, INPUT, NONE); - PIN_SLP(mp02-3, INPUT, DOWN); - - PIN_SLP(mp03-0, INPUT, DOWN); - PIN_SLP(mp03-1, INPUT, DOWN); - PIN_SLP(mp03-2, OUT1, NONE); - PIN_SLP(mp03-3, OUT0, NONE); - PIN_SLP(mp03-4, INPUT, NONE); - PIN_SLP(mp03-5, OUT1, NONE); - PIN_SLP(mp03-6, INPUT, DOWN); - PIN_SLP(mp03-7, INPUT, DOWN); - - PIN_SLP(mp04-0, INPUT, DOWN); - PIN_SLP(mp04-1, OUT0, NONE); - PIN_SLP(mp04-2, INPUT, DOWN); - PIN_SLP(mp04-3, OUT0, NONE); - PIN_SLP(mp04-4, INPUT, DOWN); - PIN_SLP(mp04-5, INPUT, DOWN); - PIN_SLP(mp04-6, OUT0, NONE); - PIN_SLP(mp04-7, INPUT, DOWN); - - PIN_SLP(mp05-0, INPUT, NONE); - PIN_SLP(mp05-1, INPUT, NONE); - PIN_SLP(mp05-2, INPUT, NONE); - PIN_SLP(mp05-3, INPUT, NONE); - PIN_SLP(mp05-4, INPUT, DOWN); - PIN_SLP(mp05-5, OUT0, NONE); - PIN_SLP(mp05-6, INPUT, DOWN); - PIN_SLP(mp05-7, PREV, NONE); - - PIN_SLP(mp06-0, INPUT, DOWN); - PIN_SLP(mp06-1, INPUT, DOWN); - PIN_SLP(mp06-2, INPUT, DOWN); - PIN_SLP(mp06-3, INPUT, DOWN); - PIN_SLP(mp06-4, INPUT, DOWN); - PIN_SLP(mp06-5, INPUT, DOWN); - PIN_SLP(mp06-6, INPUT, DOWN); - PIN_SLP(mp06-7, INPUT, DOWN); - - PIN_SLP(mp07-0, INPUT, DOWN); - PIN_SLP(mp07-1, INPUT, DOWN); - PIN_SLP(mp07-2, INPUT, DOWN); - PIN_SLP(mp07-3, INPUT, DOWN); - PIN_SLP(mp07-4, INPUT, DOWN); - PIN_SLP(mp07-5, INPUT, DOWN); - PIN_SLP(mp07-6, INPUT, DOWN); - PIN_SLP(mp07-7, INPUT, DOWN); - }; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - mmc-pwrseq = <&nand_pwrseq>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>; - assigned-clock-rates = <0>, <52000000>; - assigned-clock-parents = <&clocks MOUT_MPLL>; -}; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts deleted file mode 100644 index d32f42dd1bf5..000000000000 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Samsung Goni board. - */ - -/dts-v1/; -#include -#include -#include -#include "s5pv210.dtsi" - -/ { - model = "Samsung Goni based on S5PC110"; - compatible = "samsung,goni", "samsung,s5pv210"; - - aliases { - i2c3 = &i2c_pmic; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000>, - <0x40000000 0x10000000>, - <0x50000000 0x08000000>; - }; - - pmic_ap_clk: clock-0 { - /* Workaround for missing clock on PMIC */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - vtf_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pda_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - bat_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - tsp_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "TSP_VDD"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - i2c_pmic: i2c-pmic { - compatible = "i2c-gpio"; - sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, - <&gph0 4 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VCC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC+VCAM_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_IO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_ISP_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_CIF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_8M_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VARM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - buck2_reg: BUCK2 { - regulator-name = "VINT_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gph2 6 1>; - linux,code = ; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; - status = "okay"; - - key-1 { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key-2 { - keypad,row = <0>; - keypad,column = <2>; - linux,code = ; - }; - - key-3 { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key-4 { - keypad,row = <1>; - keypad,column = <2>; - linux,code = ; - }; - - key-5 { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; - - key-6 { - keypad,row = <2>; - keypad,column = <2>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 1>; - vmmc-supply = <&vtf_reg>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo3_reg>; - vusb_d-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&i2c2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpj0>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&tsp_reg>; - }; -}; - -&i2c0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - noon010pc30: sensor@30 { - compatible = "siliconfile,noon010pc30"; - reg = <0x30>; - vddio-supply = <&ldo11_reg>; - vdda-supply = <&ldo13_reg>; - vdd_core-supply = <&ldo14_reg>; - - clock-frequency = <16000000>; - clocks = <&camera 0>; - clock-names = "mclk"; - nreset-gpios = <&gpb 2 GPIO_ACTIVE_HIGH>; - nstby-gpios = <&gpb 0 GPIO_ACTIVE_HIGH>; - - port { - noon010pc30_ep: endpoint { - remote-endpoint = <&fimc0_ep>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <1>; - pclk-sample = <1>; - }; - }; - }; -}; - -&camera { - pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>; - pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>; - pinctrl-names = "default", "idle"; - - parallel-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* camera A input */ - port@1 { - reg = <1>; - fimc0_ep: endpoint { - remote-endpoint = <&noon010pc30_ep>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - /* 480x800@55Hz */ - clock-frequency = <23439570>; - hactive = <480>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vactive = <800>; - vback-porch = <2>; - vfront-porch = <28>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&onenand { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi deleted file mode 100644 index af740abd9e0f..000000000000 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ /dev/null @@ -1,845 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - pin control-related - * definitions - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are - * listed as device tree nodes in this file. - */ - -#include "s5pv210-pinctrl.h" - -#define PIN_SLP(_pin, _mode, _pull) \ - pin- ## _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -&pinctrl0 { - gpa0: gpa0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj2: gpj2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj3: gpj3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpi: gpi-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp01: mp01-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp02: mp02-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp03: mp03-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp04: mp04-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp05: mp05-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp06: mp06-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - mp07: mp07-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gph0: gph0-gpio-bank { - gpio-controller; - interrupt-controller; - interrupt-parent = <&vic0>; - interrupts = <0>, <1>, <2>, <3>, - <4>, <5>, <6>, <7>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph1: gph1-gpio-bank { - gpio-controller; - interrupt-controller; - interrupt-parent = <&vic0>; - interrupts = <8>, <9>, <10>, <11>, - <12>, <13>, <14>, <15>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph2: gph2-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph3: gph3-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data-pins { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio: uart-audio-pins { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus-pins { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s0_bus: i2s0-bus-pins { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus-pins { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus-pins { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus-pins { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus-pins { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus-pins { - samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out-pins { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out-pins { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out-pins { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out-pins { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row0: keypad-row-0-pins { - samsung,pins = "gph3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row1: keypad-row-1-pins { - samsung,pins = "gph3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row2: keypad-row-2-pins { - samsung,pins = "gph3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row3: keypad-row-3-pins { - samsung,pins = "gph3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row4: keypad-row-4-pins { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row5: keypad-row-5-pins { - samsung,pins = "gph3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row6: keypad-row-6-pins { - samsung,pins = "gph3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row7: keypad-row-7-pins { - samsung,pins = "gph3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col0: keypad-col-0-pins { - samsung,pins = "gph2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col1: keypad-col-1-pins { - samsung,pins = "gph2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col2: keypad-col-2-pins { - samsung,pins = "gph2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col3: keypad-col-3-pins { - samsung,pins = "gph2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col4: keypad-col-4-pins { - samsung,pins = "gph2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col5: keypad-col-5-pins { - samsung,pins = "gph2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col6: keypad-col-6-pins { - samsung,pins = "gph2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col7: keypad-col-7-pins { - samsung,pins = "gph2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpg0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpg0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd-pins { - samsung,pins = "gpg0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1-pins { - samsung,pins = "gpg0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4-pins { - samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8-pins { - samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpg1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpg1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd-pins { - samsung,pins = "gpg1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1-pins { - samsung,pins = "gpg1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4-pins { - samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk-pins { - samsung,pins = "gpg2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd-pins { - samsung,pins = "gpg2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd-pins { - samsung,pins = "gpg2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1-pins { - samsung,pins = "gpg2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4-pins { - samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8-pins { - samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk-pins { - samsung,pins = "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd-pins { - samsung,pins = "gpg3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd-pins { - samsung,pins = "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1-pins { - samsung,pins = "gpg3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4-pins { - samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0-pins { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8-pins { - samsung,pins = "gph1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15-pins { - samsung,pins = "gph1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16-pins { - samsung,pins = "gph2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31-pins { - samsung,pins = "gph3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io-pins { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active-pins { - samsung,pins = "gpe1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle-pins { - samsung,pins = "gpe1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io-pins { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active-pins { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle-pins { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl-pins { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync-pins { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk-pins { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24-pins { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/s5pv210-pinctrl.h deleted file mode 100644 index 29bdf376d8f1..000000000000 --- a/arch/arm/boot/dts/s5pv210-pinctrl.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung S5PV210 DTS pinctrl constants - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Linaro Ltd - * Author: Krzysztof Kozlowski - */ - -#ifndef __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ -#define __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ - -#define S5PV210_PIN_PULL_NONE 0 -#define S5PV210_PIN_PULL_DOWN 1 -#define S5PV210_PIN_PULL_UP 2 - -/* Pin function in power down mode */ -#define S5PV210_PIN_PDN_OUT0 0 -#define S5PV210_PIN_PDN_OUT1 1 -#define S5PV210_PIN_PDN_INPUT 2 -#define S5PV210_PIN_PDN_PREV 3 - -#define S5PV210_PIN_DRV_LV1 0 -#define S5PV210_PIN_DRV_LV2 2 -#define S5PV210_PIN_DRV_LV3 1 -#define S5PV210_PIN_DRV_LV4 3 - -#define S5PV210_PIN_FUNC_INPUT 0 -#define S5PV210_PIN_FUNC_OUTPUT 1 -#define S5PV210_PIN_FUNC_2 2 -#define S5PV210_PIN_FUNC_3 3 -#define S5PV210_PIN_FUNC_4 4 -#define S5PV210_PIN_FUNC_5 5 -#define S5PV210_PIN_FUNC_6 6 -#define S5PV210_PIN_FUNC_EINT 0xf -#define S5PV210_PIN_FUNC_F S5PV210_PIN_FUNC_EINT - -#endif /* __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts deleted file mode 100644 index 0c623b78af72..000000000000 --- a/arch/arm/boot/dts/s5pv210-smdkc110.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for YIC System SMDC110 board. - * - * NOTE: This file is completely based on original board file for mach-smdkc110 - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "YIC System SMDKC110 based on S5PC110"; - compatible = "yic,smdkc110", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; - - pmic_ap_clk: clock-0 { - /* Workaround for missing PMIC and its clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&i2c0 { - status = "okay"; - - audio-codec@1b { - compatible = "wlf,wm8580"; - reg = <0x1b>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts deleted file mode 100644 index 6e26c67e0a26..000000000000 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for YIC System SMDV210 board. - * - * NOTE: This file is completely based on original board file for mach-smdkv210 - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - */ - -/dts-v1/; -#include -#include -#include "s5pv210.dtsi" - -/ { - model = "YIC System SMDKV210 based on S5PV210"; - compatible = "yic,smdkv210", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x40000000>; - }; - - pmic_ap_clk: clock-0 { - /* Workaround for missing PMIC and its clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ethernet@a8000000 { - compatible = "davicom,dm9000"; - reg = <0xA8000000 0x2 0xA8000002 0x2>; - interrupt-parent = <&gph1>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - local-mac-address = [00 00 de ad be ef]; - davicom,no-eeprom; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; - power-supply = <&dc5v_reg>; - }; - - dc5v_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "DC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <8>; - samsung,keypad-num-columns = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_row3>, <&keypad_row4>, <&keypad_row5>, - <&keypad_row6>, <&keypad_row7>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>, - <&keypad_col3>, <&keypad_col4>, <&keypad_col5>, - <&keypad_col6>, <&keypad_col7>; - status = "okay"; - - key-1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = ; - }; - - key-2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = ; - }; - - key-3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = ; - }; - - key-4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = ; - }; - - key-5 { - keypad,row = <0 - >; - keypad,column = <7>; - linux,code = ; - }; - - key-6 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = ; - }; - key-7 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = ; - }; - - key-8 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = ; - }; - - key-9 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = ; - }; - - key-10 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci3 { - bus-width = <4>; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 800x480@60Hz */ - clock-frequency = <24373920>; - hactive = <800>; - vactive = <480>; - hfront-porch = <8>; - hback-porch = <13>; - hsync-len = <3>; - vback-porch = <7>; - vfront-porch = <5>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; - -&pwm { - samsung,pwm-outputs = <3>; -}; - -&i2c0 { - status = "okay"; - - audio-codec@1b { - compatible = "wlf,wm8580"; - reg = <0x1b>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts deleted file mode 100644 index e18259737684..000000000000 --- a/arch/arm/boot/dts/s5pv210-torbreck.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Torbreck board. - * - * NOTE: This file is completely based on original board file for mach-torbreck - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "aESOP Torbreck based on S5PV210"; - compatible = "aesop,torbreck", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; - - pmic_ap_clk: clock-0 { - /* Workaround for missing PMIC and its clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci3 { - bus-width = <4>; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi deleted file mode 100644 index f7de5b5f2f38..000000000000 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ /dev/null @@ -1,632 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - csis0 = &csis0; - dmc0 = &dmc0; - dmc1 = &dmc1; - fimc0 = &fimc0; - fimc1 = &fimc1; - fimc2 = &fimc2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2s0 = &i2s0; - i2s1 = &i2s1; - i2s2 = &i2s2; - pinctrl0 = &pinctrl0; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - }; - }; - - xxti: oscillator-0 { - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "xxti"; - #clock-cells = <0>; - }; - - xusbxti: oscillator-1 { - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "xusbxti"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - onenand: onenand@b0600000 { - compatible = "samsung,s5pv210-onenand"; - reg = <0xb0600000 0x2000>, - <0xb0000000 0x20000>, - <0xb0040000 0x20000>; - interrupt-parent = <&vic1>; - interrupts = <31>; - clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; - clock-names = "bus", "onenand"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - chipid@e0000000 { - compatible = "samsung,s5pv210-chipid"; - reg = <0xe0000000 0x1000>; - }; - - clocks: clock-controller@e0100000 { - compatible = "samsung,s5pv210-clock"; - reg = <0xe0100000 0x10000>; - clock-names = "xxti", "xusbxti"; - clocks = <&xxti>, <&xusbxti>; - #clock-cells = <1>; - }; - - pmu_syscon: syscon@e0108000 { - compatible = "samsung-s5pv210-pmu", "syscon"; - reg = <0xe0108000 0x8000>; - }; - - pinctrl0: pinctrl@e0200000 { - compatible = "samsung,s5pv210-pinctrl"; - reg = <0xe0200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <30>; - - wakeup-interrupt-controller { - compatible = "samsung,s5pv210-wakeup-eint"; - interrupts = <16>; - interrupt-parent = <&vic0>; - }; - }; - - pdma0: dma-controller@e0900000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <19>; - clocks = <&clocks CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - pdma1: dma-controller@e0a00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0a00000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <20>; - clocks = <&clocks CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - adc: adc@e1700000 { - compatible = "samsung,s5pv210-adc"; - reg = <0xe1700000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <23>, <24>; - clocks = <&clocks CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - spi0: spi@e1300000 { - compatible = "samsung,s5pv210-spi"; - reg = <0xe1300000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <15>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e1400000 { - compatible = "samsung,s5pv210-spi"; - reg = <0xe1400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <16>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - keypad: keypad@e1600000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0xe1600000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <25>; - clocks = <&clocks CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - i2c0: i2c@e1800000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <14>; - clocks = <&clocks CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e1a00000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xe1a00000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <19>; - clocks = <&clocks CLK_I2C2>; - clock-names = "i2c"; - pinctrl-0 = <&i2c2_bus>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clk_audss: clock-controller@eee10000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xeee10000 0x1000>; - clock-names = "hclk", "xxti", - "fout_epll", - "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, - <&clocks SCLK_AUDIO0>; - #clock-cells = <1>; - }; - - i2s0: i2s@eee30000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0xeee30000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <16>; - dma-names = "tx", "rx", "tx-sec"; - dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 11>; - clock-names = "iis", - "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, - <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - samsung,idma-addr = <0xc0010000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@e2100000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0xe2100000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <17>; - dma-names = "tx", "rx"; - dmas = <&pdma1 13>, <&pdma1 12>; - clock-names = "iis", "i2s_opclk0"; - clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@e2a00000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0xe2a00000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <18>; - dma-names = "tx", "rx"; - dmas = <&pdma1 15>, <&pdma1 14>; - clock-names = "iis", "i2s_opclk0"; - clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@e2500000 { - compatible = "samsung,s5pc100-pwm"; - reg = <0xe2500000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <21>, <22>, <23>, <24>, <25>; - clock-names = "timers"; - clocks = <&clocks CLK_PWM>; - #pwm-cells = <3>; - }; - - watchdog: watchdog@e2700000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0xe2700000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks CLK_WDT>; - }; - - rtc: rtc@e2800000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0xe2800000 0x100>; - interrupt-parent = <&vic0>; - interrupts = <28>, <29>; - clocks = <&clocks CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - uart0: serial@e2900000 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900000 0x400>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>, - <&clocks SCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@e2900400 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900400 0x400>; - interrupt-parent = <&vic1>; - interrupts = <11>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>, - <&clocks SCLK_UART1>; - status = "disabled"; - }; - - uart2: serial@e2900800 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900800 0x400>; - interrupt-parent = <&vic1>; - interrupts = <12>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>, - <&clocks SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@e2900c00 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900c00 0x400>; - interrupt-parent = <&vic1>; - interrupts = <13>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>, - <&clocks SCLK_UART3>; - status = "disabled"; - }; - - sdhci0: mmc@eb000000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb000000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: mmc@eb100000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb100000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: mmc@eb200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb200000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <28>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - sdhci3: mmc@eb300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb300000 0x100000>; - interrupt-parent = <&vic3>; - interrupts = <2>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3"; - clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>, - <&clocks SCLK_MMC3>; - status = "disabled"; - }; - - hsotg: usb@ec000000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0xec000000 0x20000>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clocks = <&clocks CLK_USB_OTG>; - clock-names = "otg"; - phy-names = "usb2-phy"; - phys = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: usbphy@ec100000 { - compatible = "samsung,s5pv210-usb2-phy"; - reg = <0xec100000 0x100>; - samsung,pmureg-phandle = <&pmu_syscon>; - clocks = <&clocks CLK_USB_OTG>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - ehci: usb@ec200000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0xec200000 0x100>; - interrupts = <23>; - interrupt-parent = <&vic1>; - clocks = <&clocks CLK_USB_HOST>; - clock-names = "usbhost"; - phys = <&usbphy 1>; - phy-names = "host"; - status = "disabled"; - }; - - ohci: usb@ec300000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0xec300000 0x100>; - interrupts = <23>; - interrupt-parent = <&vic1>; - clocks = <&clocks CLK_USB_HOST>; - clock-names = "usbhost"; - phys = <&usbphy 1>; - phy-names = "host"; - status = "disabled"; - }; - - mfc: codec@f1700000 { - compatible = "samsung,mfc-v5"; - reg = <0xf1700000 0x10000>; - interrupt-parent = <&vic2>; - interrupts = <14>; - clocks = <&clocks CLK_MFC>, <&clocks DOUT_MFC>; - clock-names = "mfc", "sclk_mfc"; - }; - - vic0: interrupt-controller@f2000000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2000000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@f2100000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2100000 0x1000>; - #interrupt-cells = <1>; - }; - - vic2: interrupt-controller@f2200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic3: interrupt-controller@f2300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2300000 0x1000>; - #interrupt-cells = <1>; - }; - - fimd: fimd@f8000000 { - compatible = "samsung,s5pv210-fimd"; - interrupt-parent = <&vic2>; - reg = <0xf8000000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0>, <1>, <2>; - clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>; - clock-names = "sclk_fimd", "fimd"; - status = "disabled"; - }; - - dmc0: dmc@f0000000 { - compatible = "samsung,s5pv210-dmc"; - reg = <0xf0000000 0x1000>; - }; - - dmc1: dmc@f1400000 { - compatible = "samsung,s5pv210-dmc"; - reg = <0xf1400000 0x1000>; - }; - - g2d: g2d@fa000000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0xfa000000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <9>; - clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - }; - - mdma1: dma-controller@fa200000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfa200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <18>; - clocks = <&clocks CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - rotator: rotator@fa300000 { - compatible = "samsung,s5pv210-rotator"; - reg = <0xfa300000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <4>; - clocks = <&clocks CLK_ROTATOR>; - clock-names = "rotator"; - }; - - i2c1: i2c@fab00000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xfab00000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <13>; - clocks = <&clocks CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - camera: camera@fa600000 { - compatible = "samsung,fimc"; - clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; - clock-names = "sclk_cam0", "sclk_cam1"; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - - csis0: csis@fa600000 { - compatible = "samsung,s5pv210-csis"; - reg = <0xfa600000 0x4000>; - interrupt-parent = <&vic2>; - interrupts = <29>; - clocks = <&clocks CLK_CSIS>, - <&clocks SCLK_CSIS>; - clock-names = "csis", - "sclk_csis"; - bus-width = <4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - fimc0: fimc@fb200000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb200000 0x1000>; - interrupts = <5>; - interrupt-parent = <&vic2>; - clocks = <&clocks CLK_FIMC0>, - <&clocks SCLK_FIMC0>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,min-pix-alignment = <16 8>; - samsung,cam-if; - }; - - fimc1: fimc@fb300000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb300000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <6>; - clocks = <&clocks CLK_FIMC1>, - <&clocks SCLK_FIMC1>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,min-pix-alignment = <1 1>; - samsung,mainscaler-ext; - samsung,cam-if; - samsung,lcd-wb; - }; - - fimc2: fimc@fb400000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb400000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <7>; - clocks = <&clocks CLK_FIMC2>, - <&clocks SCLK_FIMC2>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <1920 8192 1280 1920>; - samsung,min-pix-alignment = <16 8>; - samsung,rotators = <0>; - samsung,cam-if; - }; - }; - - jpeg_codec: jpeg-codec@fb600000 { - compatible = "samsung,s5pv210-jpeg"; - reg = <0xfb600000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <8>; - clocks = <&clocks CLK_JPEG>; - clock-names = "jpeg"; - }; - }; -}; - -#include "s5pv210-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi deleted file mode 100644 index c8bedfa987e5..000000000000 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ /dev/null @@ -1,1353 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Sandeep Sheriker M - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Microchip SAM9X60 SoC"; - compatible = "microchip,sam9x60"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x100000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb0: gadget@500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "microchip,sam9x60-udc"; - reg = <0x00500000 0x100000 - 0xf803c000 0x400>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - usb1: ohci@600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usb_clk", "ehci_clk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "microchip,sam9x60-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - microchip,sfr = <&sfr>; - reg = <0x10000000 0x60000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "microchip,sam9x60-nand-controller"; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - sdmmc0: sdio-host@80000000 { - compatible = "microchip,sam9x60-sdhci"; - reg = <0x80000000 0x300>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; - clock-names = "hclock", "multclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 12>; - assigned-clock-rates = <100000000>; - status = "disabled"; - }; - - sdmmc1: sdio-host@90000000 { - compatible = "microchip,sam9x60-sdhci"; - reg = <0x90000000 0x300>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; - clock-names = "hclock", "multclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 26>; - assigned-clock-rates = <100000000>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flx4: flexcom@f0000000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0000000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0000000 0x800>; - status = "disabled"; - - uart4: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(8))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(9))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - spi4: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(8))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(9))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c4: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(8))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(9))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx5: flexcom@f0004000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0004000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0004000 0x800>; - status = "disabled"; - - uart5: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(10))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - spi5: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(10))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c5: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(10))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - dma0: dma-controller@f0008000 { - compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; - reg = <0xf0008000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "dma_clk"; - }; - - ssc: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(38))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(39))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "pclk"; - status = "disabled"; - }; - - qspi: spi@f0014000 { - compatible = "microchip,sam9x60-qspi"; - reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(26))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; - clock-names = "pclk", "qspick"; - atmel,pmc = <&pmc>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2s: i2s@f001c000 { - compatible = "microchip,sam9x60-i2smcc"; - reg = <0xf001c000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - flx11: flexcom@f0020000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0020000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0020000 0x800>; - status = "disabled"; - - uart11: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(22))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(23))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c11: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(22))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(23))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx12: flexcom@f0024000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0024000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0024000 0x800>; - status = "disabled"; - - uart12: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(24))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(25))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c12: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(24))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(25))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - pit64b: timer@f0028000 { - compatible = "microchip,sam9x60-pit64b"; - reg = <0xf0028000 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; - clock-names = "pclk", "gclk"; - }; - - sha: crypto@f002c000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf002c000 0x100>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(34))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; - clock-names = "sha_clk"; - }; - - trng: trng@f0030000 { - compatible = "microchip,sam9x60-trng"; - reg = <0xf0030000 0x100>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - }; - - aes: crypto@f0034000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf0034000 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(32))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(33))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - clock-names = "aes_clk"; - }; - - tdes: crypto@f0038000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xf0038000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(31))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(30))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; - clock-names = "tdes_clk"; - }; - - classd: classd@f003c000 { - compatible = "atmel,sama5d2-classd"; - reg = <0xf003c000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(35))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - can0: can@f8000000 { - compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; - reg = <0xf8000000 0x300>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8004000 { - compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; - reg = <0xf8004000 0x300>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "can_clk"; - status = "disabled"; - }; - - tcb0: timer@f8008000 { - compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; - clock-names = "t0_clk", "slow_clk"; - }; - - flx6: flexcom@f8010000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8010000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8010000 0x800>; - status = "disabled"; - - uart6: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c6: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx7: flexcom@f8014000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8014000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8014000 0x800>; - status = "disabled"; - - uart7: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(15))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c7: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(15))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx8: flexcom@f8018000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8018000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8018000 0x800>; - status = "disabled"; - - uart8: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(16))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(17))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c8: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(16))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(17))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx0: flexcom@f801c000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf801c000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf801c000 0x800>; - status = "disabled"; - - uart0: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(0))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(1))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - spi0: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(0))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(1))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c0: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(0))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(1))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx1: flexcom@f8020000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8020000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8020000 0x800>; - status = "disabled"; - - uart1: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(2))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - spi1: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(2))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c1: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(2))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx2: flexcom@f8024000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8024000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8024000 0x800>; - status = "disabled"; - - uart2: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(4))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(5))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - spi2: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(4))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(5))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c2: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(4))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(5))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx3: flexcom@f8028000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8028000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8028000 0x800>; - status = "disabled"; - - uart3: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(6))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - spi3: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(6))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c3: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(6))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,sam9x60-macb", "cdns,macb"; - reg = <0xf802c000 0x1000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,sam9x60-macb", "cdns,macb"; - reg = <0xf8030000 0x1000>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "microchip,sam9x60-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - #pwm-cells = <3>; - status = "disabled"; - }; - - hlcdc: hlcdc@f8038000 { - compatible = "microchip,sam9x60-hlcdc"; - reg = <0xf8038000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 25>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - #pwm-cells = <3>; - }; - }; - - flx9: flexcom@f8040000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8040000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8040000 0x800>; - status = "disabled"; - - uart9: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(18))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(19))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c9: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(18))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(19))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx10: flexcom@f8044000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8044000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8044000 0x800>; - status = "disabled"; - - uart10: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(20))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(21))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c10: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(20))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(21))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - isi: isi@f8048000 { - compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; - reg = <0xf8048000 0x100>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - adc: adc@f804c000 { - compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; - reg = <0xf804c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "adc_clk"; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; - dma-names = "rx"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - atmel,trigger-edge-type = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - sfr: sfr@f8050000 { - compatible = "microchip,sam9x60-sfr", "syscon"; - reg = <0xf8050000 0x100>; - }; - - matrix: matrix@ffffde00 { - compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; - reg = <0xffffde00 0x200>; - }; - - pmecc: ecc-engine@ffffe000 { - compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; - reg = <0xffffe000 0x300>, - <0xffffe600 0x100>; - }; - - mpddrc: mpddrc@ffffe800 { - compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; - clock-names = "ddrck", "mpddr"; - }; - - smc: smc@ffffea00 { - compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x100>; - }; - - aic: interrupt-controller@fffff100 { - compatible = "microchip,sam9x60-aic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffff100 0x100>; - atmel,external-irqs = <31>; - }; - - dbgu: serial@fffff200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - atmel,usart-mode = ; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(28))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl: pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xef00019d /* pioA */ - 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ - 0xffffffff 0xffffffff 0xf83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - - pioA: gpio@fffff400 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <26>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; - }; - }; - - pmc: clock-controller@fffffc00 { - compatible = "microchip,sam9x60-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; - clock-names = "td_slck", "md_slck", "main_xtal"; - }; - - reset_controller: reset-controller@fffffe00 { - compatible = "microchip,sam9x60-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k 0>; - }; - - shutdown_controller: shdwc@fffffe10 { - compatible = "microchip,sam9x60-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k 0>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - atmel,wakeup-rtt-timer; - status = "disabled"; - }; - - rtt: rtc@fffffe20 { - compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; - reg = <0xfffffe20 0x20>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 0>; - }; - - pit: timer@fffffe40 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - clk32k: clock-controller@fffffe50 { - compatible = "microchip,sam9x60-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <1>; - }; - - gpbr: syscon@fffffe60 { - compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffe60 0x10>; - }; - - rtc: rtc@fffffea8 { - compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; - reg = <0xfffffea8 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 0>; - }; - - watchdog: watchdog@ffffff80 { - compatible = "microchip,sam9x60-wdt"; - reg = <0xffffff80 0x24>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 0>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/sama5d2-pinfunc.h deleted file mode 100644 index 28a2e45752fe..000000000000 --- a/arch/arm/boot/dts/sama5d2-pinfunc.h +++ /dev/null @@ -1,881 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define PINMUX_PIN(no, func, ioset) \ -(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) - -#define PIN_PA0 0 -#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) -#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) -#define PIN_PA1 1 -#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) -#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) -#define PIN_PA2 2 -#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) -#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) -#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) -#define PIN_PA3 3 -#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) -#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) -#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) -#define PIN_PA4 4 -#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) -#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) -#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) -#define PIN_PA5 5 -#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) -#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) -#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) -#define PIN_PA6 6 -#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) -#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) -#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) -#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) -#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) -#define PIN_PA7 7 -#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) -#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) -#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) -#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) -#define PIN_PA8 8 -#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) -#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) -#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) -#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) -#define PIN_PA9 9 -#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) -#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) -#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) -#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) -#define PIN_PA10 10 -#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) -#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) -#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) -#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) -#define PIN_PA11 11 -#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) -#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) -#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) -#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) -#define PIN_PA12 12 -#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) -#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) -#define PIN_PA13 13 -#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) -#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) -#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) -#define PIN_PA14 14 -#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) -#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) -#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) -#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) -#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) -#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) -#define PIN_PA15 15 -#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) -#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) -#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) -#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) -#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) -#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) -#define PIN_PA16 16 -#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) -#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) -#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) -#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) -#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) -#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) -#define PIN_PA17 17 -#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) -#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) -#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) -#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) -#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) -#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) -#define PIN_PA18 18 -#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) -#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) -#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) -#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) -#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) -#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) -#define PIN_PA19 19 -#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) -#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) -#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) -#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) -#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) -#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) -#define PIN_PA20 20 -#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) -#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) -#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) -#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) -#define PIN_PA21 21 -#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) -#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) -#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) -#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) -#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) -#define PIN_PA22 22 -#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) -#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) -#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) -#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) -#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) -#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) -#define PIN_PA23 23 -#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) -#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) -#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) -#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) -#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) -#define PIN_PA24 24 -#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) -#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) -#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) -#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) -#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) -#define PIN_PA25 25 -#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) -#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) -#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) -#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) -#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) -#define PIN_PA26 26 -#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) -#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) -#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) -#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) -#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) -#define PIN_PA27 27 -#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) -#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) -#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) -#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) -#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) -#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) -#define PIN_PA28 28 -#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) -#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) -#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) -#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) -#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) -#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) -#define PIN_PA29 29 -#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) -#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) -#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) -#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) -#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) -#define PIN_PA30 30 -#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) -#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) -#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) -#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) -#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) -#define PIN_PA31 31 -#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) -#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) -#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) -#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) -#define PIN_PB0 32 -#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) -#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) -#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) -#define PIN_PB1 33 -#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) -#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) -#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) -#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) -#define PIN_PB2 34 -#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) -#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) -#define PIN_PB3 35 -#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) -#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) -#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) -#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) -#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) -#define PIN_PB4 36 -#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) -#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) -#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) -#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) -#define PIN_PB5 37 -#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) -#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) -#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) -#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) -#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) -#define PIN_PB6 38 -#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) -#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) -#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) -#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) -#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) -#define PIN_PB7 39 -#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) -#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) -#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) -#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) -#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) -#define PIN_PB8 40 -#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) -#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) -#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) -#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) -#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) -#define PIN_PB9 41 -#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) -#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) -#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) -#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) -#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) -#define PIN_PB10 42 -#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) -#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) -#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) -#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) -#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) -#define PIN_PB11 43 -#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) -#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) -#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) -#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) -#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) -#define PIN_PB12 44 -#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) -#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) -#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) -#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) -#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) -#define PIN_PB13 45 -#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) -#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) -#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) -#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) -#define PIN_PB14 46 -#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) -#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) -#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) -#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) -#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) -#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) -#define PIN_PB15 47 -#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) -#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) -#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) -#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) -#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) -#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) -#define PIN_PB16 48 -#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) -#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) -#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) -#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) -#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) -#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) -#define PIN_PB17 49 -#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) -#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) -#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) -#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) -#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) -#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) -#define PIN_PB18 50 -#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) -#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) -#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) -#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) -#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) -#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) -#define PIN_PB19 51 -#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) -#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) -#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) -#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) -#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) -#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) -#define PIN_PB20 52 -#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) -#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) -#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) -#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) -#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) -#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) -#define PIN_PB21 53 -#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) -#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) -#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) -#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) -#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) -#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) -#define PIN_PB22 54 -#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) -#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) -#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) -#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) -#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) -#define PIN_PB23 55 -#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) -#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) -#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) -#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) -#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) -#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) -#define PIN_PB24 56 -#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) -#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) -#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) -#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) -#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) -#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) -#define PIN_PB25 57 -#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) -#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) -#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) -#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) -#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) -#define PIN_PB26 58 -#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) -#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) -#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) -#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) -#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) -#define PIN_PB27 59 -#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) -#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) -#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) -#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) -#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) -#define PIN_PB28 60 -#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) -#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) -#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) -#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) -#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) -#define PIN_PB29 61 -#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) -#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) -#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) -#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) -#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) -#define PIN_PB30 62 -#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) -#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) -#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) -#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) -#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) -#define PIN_PB31 63 -#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) -#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) -#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) -#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) -#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) -#define PIN_PC0 64 -#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) -#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) -#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) -#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) -#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) -#define PIN_PC1 65 -#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) -#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) -#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) -#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) -#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) -#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) -#define PIN_PC2 66 -#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) -#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) -#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) -#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) -#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) -#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) -#define PIN_PC3 67 -#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) -#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) -#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) -#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) -#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) -#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) -#define PIN_PC4 68 -#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) -#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) -#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) -#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) -#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) -#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) -#define PIN_PC5 69 -#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) -#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) -#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) -#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) -#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) -#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) -#define PIN_PC6 70 -#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) -#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) -#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) -#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) -#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) -#define PIN_PC7 71 -#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) -#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) -#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) -#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) -#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) -#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) -#define PIN_PC8 72 -#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) -#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) -#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) -#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) -#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) -#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) -#define PIN_PC9 73 -#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) -#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) -#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1) -#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) -#define PIN_PC10 74 -#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) -#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) -#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) -#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) -#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) -#define PIN_PC11 75 -#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) -#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) -#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) -#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) -#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) -#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) -#define PIN_PC12 76 -#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) -#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) -#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) -#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) -#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) -#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) -#define PIN_PC13 77 -#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) -#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) -#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) -#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) -#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) -#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) -#define PIN_PC14 78 -#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) -#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) -#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) -#define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) -#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) -#define PIN_PC15 79 -#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) -#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) -#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) -#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) -#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) -#define PIN_PC16 80 -#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) -#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) -#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) -#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) -#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) -#define PIN_PC17 81 -#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) -#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) -#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) -#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) -#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) -#define PIN_PC18 82 -#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) -#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) -#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) -#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) -#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) -#define PIN_PC19 83 -#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) -#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) -#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) -#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) -#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) -#define PIN_PC20 84 -#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) -#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) -#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) -#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) -#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) -#define PIN_PC21 85 -#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) -#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) -#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) -#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) -#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) -#define PIN_PC22 86 -#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) -#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) -#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) -#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) -#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) -#define PIN_PC23 87 -#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) -#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) -#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) -#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) -#define PIN_PC24 88 -#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) -#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) -#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) -#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) -#define PIN_PC25 89 -#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) -#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) -#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) -#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) -#define PIN_PC26 90 -#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) -#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) -#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) -#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) -#define PIN_PC27 91 -#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) -#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) -#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) -#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) -#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) -#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) -#define PIN_PC28 92 -#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) -#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) -#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) -#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) -#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) -#define PIN_PC29 93 -#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) -#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) -#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) -#define PIN_PC30 94 -#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) -#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) -#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) -#define PIN_PC31 95 -#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) -#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) -#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) -#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) -#define PIN_PD0 96 -#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) -#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) -#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) -#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) -#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) -#define PIN_PD1 97 -#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) -#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) -#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) -#define PIN_PD2 98 -#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) -#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) -#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) -#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) -#define PIN_PD3 99 -#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) -#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) -#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) -#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) -#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) -#define PIN_PD4 100 -#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) -#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) -#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) -#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) -#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) -#define PIN_PD5 101 -#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) -#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) -#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) -#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) -#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) -#define PIN_PD6 102 -#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) -#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) -#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) -#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) -#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) -#define PIN_PD7 103 -#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) -#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) -#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) -#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) -#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) -#define PIN_PD8 104 -#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) -#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) -#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) -#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) -#define PIN_PD9 105 -#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) -#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) -#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) -#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) -#define PIN_PD10 106 -#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) -#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) -#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) -#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) -#define PIN_PD11 107 -#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) -#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) -#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) -#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) -#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) -#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) -#define PIN_PD12 108 -#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) -#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) -#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) -#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) -#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) -#define PIN_PD13 109 -#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) -#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) -#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) -#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) -#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) -#define PIN_PD14 110 -#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) -#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) -#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) -#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) -#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) -#define PIN_PD15 111 -#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) -#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) -#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) -#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) -#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) -#define PIN_PD16 112 -#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) -#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) -#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) -#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) -#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) -#define PIN_PD17 113 -#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) -#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) -#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) -#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) -#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) -#define PIN_PD18 114 -#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) -#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) -#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) -#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) -#define PIN_PD19 115 -#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) -#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) -#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) -#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) -#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) -#define PIN_PD20 116 -#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) -#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) -#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) -#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) -#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) -#define PIN_PD21 117 -#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) -#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) -#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) -#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) -#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) -#define PIN_PD22 118 -#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) -#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) -#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) -#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) -#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) -#define PIN_PD23 119 -#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) -#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) -#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) -#define PIN_PD24 120 -#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) -#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) -#define PIN_PD25 121 -#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) -#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) -#define PIN_PD26 122 -#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) -#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) -#define PIN_PD27 123 -#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) -#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) -#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) -#define PIN_PD28 124 -#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) -#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) -#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) -#define PIN_PD29 125 -#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) -#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) -#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) -#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) -#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) -#define PIN_PD30 126 -#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) -#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) -#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) -#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) -#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) -#define PIN_PD31 127 -#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) -#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) -#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) -#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) -#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi deleted file mode 100644 index 7b6471655dee..000000000000 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ /dev/null @@ -1,1166 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Ludovic Desroches - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel SAMA5D2 family SoC"; - compatible = "atmel,sama5d2"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &uart1; - serial1 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - etb@740000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x740000 0x1000>; - - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&etm_out>; - }; - }; - }; - }; - - etm@73c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x73c000 0x1000>; - - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - ns_sram: sram@200000 { - compatible = "mmio-sram"; - reg = <0x00200000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00200000 0x20000>; - }; - - resistive_touch: resistive-touch { - compatible = "resistive-adc-touch"; - io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; - io-channel-names = "x", "y", "pressure"; - touchscreen-min-pressure = <50000>; - status = "disabled"; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nfc_sram: sram@100000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x00100000 0x2400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00100000 0x2400>; - - }; - - usb0: gadget@300000 { - compatible = "atmel,sama5d3-udc"; - reg = <0x00300000 0x100000 - 0xfc02c000 0x400>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - usb1: ohci@400000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00400000 0x100000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@500000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00500000 0x100000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - L2: cache-controller@a00000 { - compatible = "arm,pl310-cache"; - reg = <0x00a00000 0x1000>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; - cache-unified; - cache-level = <2>; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x60000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x60000000 0x10000000 - 0x2 0x0 0x70000000 0x10000000 - 0x3 0x0 0x80000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - sdmmc0: sdio-host@a0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xa0000000 0x300>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; - clock-names = "hclock", "multclk", "baseclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 31>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - sdmmc1: sdio-host@b0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xb0000000 0x300>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; - clock-names = "hclock", "multclk", "baseclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 32>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - nfc_io: nfc-io@c0000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0xc0000000 0x8000000>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d2-hlcdc"; - reg = <0xf0000000 0x2000>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - #pwm-cells = <3>; - }; - }; - - isc: isc@f0008000 { - compatible = "atmel,sama5d2-isc"; - reg = <0xf0008000 0x4000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; - clock-names = "hclock", "iscck", "gck"; - #clock-cells = <0>; - clock-output-names = "isc-mck"; - status = "disabled"; - }; - - ramc0: ramc@f000c000 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xf000c000 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "ddrck", "mpddr"; - }; - - dma0: dma-controller@f0010000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0010000 0x1000>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "dma_clk"; - }; - - /* Place dma1 here despite its address */ - dma1: dma-controller@f0004000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0004000 0x1000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "dma_clk"; - }; - - pmc: clock-controller@f0014000 { - compatible = "atmel,sama5d2-pmc", "syscon"; - reg = <0xf0014000 0x160>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - qspi0: spi@f0020000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi1: spi@f0024000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sha: crypto@f0028000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf0028000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(30))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "sha_clk"; - }; - - aes: crypto@f002c000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf002c000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(26))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "aes_clk"; - }; - - spi0: spi@f8000000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8000000 0x100>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(6))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - clock-names = "spi_clk"; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssc0: ssc@f8004000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf8004000 0x4000>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(21))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(22))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - clock-names = "pclk"; - status = "disabled"; - }; - - macb0: ethernet@f8008000 { - compatible = "atmel,sama5d2-gem"; - reg = <0xf8008000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ - 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ - 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - tcb0: timer@f800c000 { - compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; - clock-names = "t0_clk", "gclk", "slow_clk"; - }; - - tcb1: timer@f8010000 { - compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8010000 0x100>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; - clock-names = "t0_clk", "gclk", "slow_clk"; - }; - - hsmc: hsmc@f8014000 { - compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; - reg = <0xf8014000 0x1000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@f8014070 { - compatible = "atmel,sama5d2-pmecc"; - reg = <0xf8014070 0x490>, - <0xf8014500 0x200>; - }; - }; - - pdmic: pdmic@f8018000 { - compatible = "atmel,sama5d2-pdmic"; - reg = <0xf8018000 0x124>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(50))>; - dma-names = "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - uart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x100>; - atmel,usart-mode = ; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(35))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x100>; - atmel,usart-mode = ; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(38))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "usart"; - status = "disabled"; - }; - - uart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x100>; - atmel,usart-mode = ; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(39))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(40))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8028000 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xf8028000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(0))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(1))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - pwm0: pwm@f802c000 { - compatible = "atmel,sama5d2-pwm"; - reg = <0xf802c000 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - status = "disabled"; - }; - - sfr: sfr@f8030000 { - compatible = "atmel,sama5d2-sfr", "syscon"; - reg = <0xf8030000 0x98>; - }; - - flx0: flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - status = "disabled"; - - uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi2: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx1: flexcom@f8038000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8038000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8038000 0x800>; - status = "disabled"; - - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "usart"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi3: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c3: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - securam: sram@f8044000 { - compatible = "atmel,sama5d2-securam", "mmio-sram"; - reg = <0xf8044000 0x1420>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; - #address-cells = <1>; - #size-cells = <1>; - no-memory-wc; - ranges = <0 0xf8044000 0x1420>; - }; - - reset_controller: reset-controller@f8048000 { - compatible = "atmel,sama5d3-rstc"; - reg = <0xf8048000 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - - pit: timer@f8048030 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xf8048030 0x10>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; - }; - - watchdog: watchdog@f8048040 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xf8048040 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - clk32k: clock-controller@f8048050 { - compatible = "atmel,sama5d4-sckc"; - reg = <0xf8048050 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc: rtc@f80480b0 { - compatible = "atmel,sama5d2-rtc"; - reg = <0xf80480b0 0x30>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - - i2s0: i2s@f8050000 { - compatible = "atmel,sama5d2-i2s"; - reg = <0xf8050000 0x100>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(31))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(32))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; - assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; - status = "disabled"; - }; - - can0: can@f8054000 { - compatible = "bosch,m_can"; - reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; - reg-names = "m_can", "message_ram"; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, - <64 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 56>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - spi1: spi@fc000000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc000000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(8))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(9))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; - clock-names = "spi_clk"; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart3: serial@fc008000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc008000 0x100>; - atmel,usart-mode = ; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(41))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(42))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "usart"; - status = "disabled"; - }; - - uart4: serial@fc00c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc00c000 0x100>; - atmel,usart-mode = ; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(43))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(44))>; - dma-names = "tx", "rx"; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "usart"; - status = "disabled"; - }; - - flx2: flexcom@fc010000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc010000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc010000 0x800>; - status = "disabled"; - - uart7: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "usart"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(15))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(16))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi4: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(15))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(16))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c4: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(15))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(16))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx3: flexcom@fc014000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc014000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc014000 0x800>; - status = "disabled"; - - uart8: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi5: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c5: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - }; - - flx4: flexcom@fc018000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc018000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc018000 0x800>; - status = "disabled"; - - uart9: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - status = "disabled"; - }; - - spi6: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "spi_clk"; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - i2c6: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | - AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - trng@fc01c000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfc01c000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; - }; - - aic: interrupt-controller@fc020000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d2-aic"; - interrupt-controller; - reg = <0xfc020000 0x200>; - atmel,external-irqs = <49>; - }; - - i2c1: i2c@fc028000 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xfc028000 0x100>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(2))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - adc: adc@fc030000 { - compatible = "atmel,sama5d2-adc"; - reg = <0xfc030000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; - clock-names = "adc_clk"; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; - dma-names = "rx"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - atmel,trigger-edge-type = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - pioA: pinctrl@fc038000 { - compatible = "atmel,sama5d2-pinctrl"; - reg = <0xfc038000 0x600>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, - <68 IRQ_TYPE_LEVEL_HIGH 7>, - <69 IRQ_TYPE_LEVEL_HIGH 7>, - <70 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - }; - - pioBU: secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - - gpio-controller; - #gpio-cells = <2>; - }; - - tdes: crypto@fc044000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xfc044000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(28))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - clock-names = "tdes_clk"; - }; - - classd: classd@fc048000 { - compatible = "atmel,sama5d2-classd"; - reg = <0xfc048000 0x100>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(47))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - i2s1: i2s@fc04c000 { - compatible = "atmel,sama5d2-i2s"; - reg = <0xfc04c000 0x100>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(33))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(34))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; - assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>; - status = "disabled"; - }; - - can1: can@fc050000 { - compatible = "bosch,m_can"; - reg = <0xfc050000 0x4000>, <0x210000 0x3800>; - reg-names = "m_can", "message_ram"; - interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, - <65 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 57>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - sfrbu: sfr@fc05c000 { - compatible = "atmel,sama5d2-sfrbu", "syscon"; - reg = <0xfc05c000 0x20>; - }; - - chipid@fc069000 { - compatible = "atmel,sama5d2-chipid"; - reg = <0xfc069000 0x8>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d29.dtsi b/arch/arm/boot/dts/sama5d29.dtsi deleted file mode 100644 index 17991c28a256..000000000000 --- a/arch/arm/boot/dts/sama5d29.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d29.dtsi - Device Tree Include file for SAMA5D29 SoC of the SAMA5D2 - * family. - * - * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries - * - * Author: Hari Prasath - * - */ - -#include "sama5d2.dtsi" - -&macb0 { - compatible = "atmel,sama5d29-gem"; -}; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi deleted file mode 100644 index 0eebf6c760b3..000000000000 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ /dev/null @@ -1,1126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC - * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel SAMA5D3 family SoC"; - compatible = "atmel,sama5d3", "atmel,sama5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0x0>; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00300000 0x20000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mmc0: mmc@f0000000 { - compatible = "atmel,hsmci"; - reg = <0xf0000000 0x600>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "mci_clk"; - }; - - spi0: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ssc0: ssc@f0008000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0008000 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - clock-names = "pclk"; - status = "disabled"; - }; - - tcb0: timer@f0010000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf0010000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - i2c0: i2c@f0014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf0014000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - status = "disabled"; - }; - - i2c1: i2c@f0018000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf0018000 0x4000>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - status = "disabled"; - }; - - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - atmel,usart-mode = ; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f0020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0020000 0x100>; - atmel,usart-mode = ; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "usart"; - status = "disabled"; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x100>; - atmel,usart-mode = ; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "usart"; - status = "disabled"; - }; - - pwm0: pwm@f002c000 { - compatible = "atmel,sama5d3-pwm"; - reg = <0xf002c000 0x300>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - status = "disabled"; - }; - - isi: isi@f0034000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0034000 0x4000>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sfr: sfr@f0038000 { - compatible = "atmel,sama5d3-sfr", "syscon"; - reg = <0xf0038000 0x60>; - }; - - mmc1: mmc@f8000000 { - compatible = "atmel,hsmci"; - reg = <0xf8000000 0x600>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "mci_clk"; - }; - - spi1: spi@f8008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8008000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ssc1: ssc@f800c000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf800c000 0x4000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - clock-names = "pclk"; - status = "disabled"; - }; - - adc0: adc@f8018000 { - compatible = "atmel,sama5d3-adc"; - reg = <0xf8018000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7 - &pinctrl_adc0_ad8 - &pinctrl_adc0_ad9 - &pinctrl_adc0_ad10 - &pinctrl_adc0_ad11 - >; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xfff>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3000>; - atmel,adc-sample-hold-time = <11>; - status = "disabled"; - }; - - i2c2: i2c@f801c000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf801c000 0x4000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - status = "disabled"; - }; - - usart2: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x100>; - atmel,usart-mode = ; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x100>; - atmel,usart-mode = ; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "usart"; - status = "disabled"; - }; - - sha: crypto@f8034000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf8034000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; - clock-names = "sha_clk"; - }; - - aes: crypto@f8038000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf8038000 0x100>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - clock-names = "aes_clk"; - }; - - tdes: crypto@f803c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xf803c000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; - clock-names = "tdes_clk"; - }; - - trng@f8040000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xf8040000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; - }; - - hsmc: hsmc@ffffc000 { - compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; - reg = <0xffffc000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@ffffc070 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffc070 0x490>, - <0xffffc500 0x100>; - }; - }; - - dma0: dma-controller@ffffe600 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffe600 0x200>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "dma_clk"; - }; - - dma1: dma-controller@ffffe800 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffe800 0x200>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; - clock-names = "dma_clk"; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xffffea00 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; - clock-names = "ddrck", "mpddr"; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - atmel,usart-mode = ; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - clock-names = "usart"; - status = "disabled"; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d3-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <47>; - }; - - pinctrl: pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ - 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ - 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ - 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ - 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ - >; - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = - ; /* PD19 periph A ADTRG */ - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = - ; /* PD20 periph A AD0 */ - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = - ; /* PD21 periph A AD1 */ - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = - ; /* PD22 periph A AD2 */ - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = - ; /* PD23 periph A AD3 */ - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = - ; /* PD24 periph A AD4 */ - }; - pinctrl_adc0_ad5: adc0_ad5 { - atmel,pins = - ; /* PD25 periph A AD5 */ - }; - pinctrl_adc0_ad6: adc0_ad6 { - atmel,pins = - ; /* PD26 periph A AD6 */ - }; - pinctrl_adc0_ad7: adc0_ad7 { - atmel,pins = - ; /* PD27 periph A AD7 */ - }; - pinctrl_adc0_ad8: adc0_ad8 { - atmel,pins = - ; /* PD28 periph A AD8 */ - }; - pinctrl_adc0_ad9: adc0_ad9 { - atmel,pins = - ; /* PD29 periph A AD9 */ - }; - pinctrl_adc0_ad10: adc0_ad10 { - atmel,pins = - ; /* PD30 periph A AD10, conflicts with PCK0 */ - }; - pinctrl_adc0_ad11: adc0_ad11 { - atmel,pins = - ; /* PD31 periph A AD11, conflicts with PCK1 */ - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - ebi { - pinctrl_ebi_addr: ebi-addr-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nand_addr: ebi-addr-1 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs0: ebi-cs0-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs1: ebi-cs1-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs2: ebi-cs2-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwait: ebi-nwait-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { - atmel,pins = - ; - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ - }; - - pinctrl_i2c0_gpio: i2c0-gpio { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - atmel,pins = - ; - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ - }; - - pinctrl_i2c2_gpio: i2c2-gpio { - atmel,pins = - ; - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { - atmel,pins = - ; /* PD1 periph A MCI0_DA0 with pullup */ - }; - pinctrl_mmc0_dat1_3: mmc0_dat1_3 { - atmel,pins = - ; /* PD4 periph A MCI0_DA3 with pullup */ - }; - pinctrl_mmc0_dat4_7: mmc0_dat4_7 { - atmel,pins = - ; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ - }; - }; - - mmc1 { - pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { - atmel,pins = - ; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ - }; - pinctrl_mmc1_dat1_3: mmc1_dat1_3 { - atmel,pins = - ; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ - }; - }; - - nand0 { - pinctrl_nand0_ale_cle: nand0_ale_cle-0 { - atmel,pins = - ; /* PE22 periph A with pullup */ - }; - }; - - pwm0 { - pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { - atmel,pins = - ; /* conflicts with ISI_D4 and LCDDAT20 */ - }; - pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { - atmel,pins = - ; /* conflicts with GTX0 */ - }; - pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { - atmel,pins = - ; /* conflicts with ISI_D5 and LCDDAT21 */ - }; - pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { - atmel,pins = - ; /* conflicts with GTX1 */ - }; - - pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { - atmel,pins = - ; /* conflicts with ISI_D6 and LCDDAT22 */ - }; - pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { - atmel,pins = - ; /* conflicts with GRX0 */ - }; - pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { - atmel,pins = - ; /* conflicts with G125CKO and RTS1 */ - }; - pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { - atmel,pins = - ; /* conflicts with ISI_D7 and LCDDAT23 */ - }; - pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { - atmel,pins = - ; /* conflicts with GRX1 */ - }; - pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { - atmel,pins = - ; /* conflicts with IRQ */ - }; - - pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { - atmel,pins = - ; /* conflicts with GTXCK */ - }; - pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { - atmel,pins = - ; /* conflicts with MCI0_DA4 and TIOA0 */ - }; - pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { - atmel,pins = - ; /* conflicts with GTXEN */ - }; - pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { - atmel,pins = - ; /* conflicts with MCI0_DA5 and TIOB0 */ - }; - - pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { - atmel,pins = - ; /* conflicts with GRXDV */ - }; - pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { - atmel,pins = - ; /* conflicts with MCI0_DA6 and TCLK0 */ - }; - pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { - atmel,pins = - ; /* conflicts with GRXER */ - }; - pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { - atmel,pins = - ; /* conflicts with MCI0_DA7 */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PD12 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PC24 periph A SPI1_SPCK pin */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx { - atmel,pins = - ; /* PC18 periph A TD0 */ - }; - - pinctrl_ssc0_rx: ssc0_rx { - atmel,pins = - ; /* PC21 periph A RD0 */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx { - atmel,pins = - ; /* PB6 periph B TD1, conflicts with TD1 */ - }; - - pinctrl_ssc1_rx: ssc1_rx { - atmel,pins = - ; /* PB11 periph B RD1, conflicts with GRXCK */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* conflicts with TWCK0, ISI_HSYNC */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts_cts: usart0_rts_cts-0 { - atmel,pins = - ; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts_cts: usart1_rts_cts-0 { - atmel,pins = - ; /* PB27 periph A, conflicts with G125CKO */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* conflicts NCS0 */ - }; - - pinctrl_usart2_rts_cts: usart2_rts_cts-0 { - atmel,pins = - ; /* PE24 periph B, conflicts with A24 */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* conflicts with A19 */ - }; - - pinctrl_usart3_rts_cts: usart3_rts_cts-0 { - atmel,pins = - ; /* PE17 periph B, conflicts with A17 */ - }; - }; - - - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - }; - }; - - pmc: clock-controller@fffffc00 { - compatible = "atmel,sama5d3-pmc", "syscon"; - reg = <0xfffffc00 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - reset_controller: reset-controller@fffffe00 { - compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shutdown-controller@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - watchdog: watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - clk32k: clock-controller@fffffe50 { - compatible = "atmel,sama5d3-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - }; - - nfc_sram: sram@200000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x200000 0x2400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x200000 0x2400>; - }; - - usb0: gadget@500000 { - compatible = "atmel,sama5d3-udc"; - reg = <0x00500000 0x100000 - 0xf8030000 0x4000>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - usb1: ohci@600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x40000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x40000000 0x10000000 - 0x2 0x0 0x50000000 0x10000000 - 0x3 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - nfc_io: nfc-io@70000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x70000000 0x8000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi deleted file mode 100644 index cbe8f275ecc4..000000000000 --- a/arch/arm/boot/dts/sama5d31.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts deleted file mode 100644 index 1f2dfb3127ab..000000000000 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d31.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D31-EK"; - compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - leds { - led-d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi deleted file mode 100644 index 146fd59acea5..000000000000 --- a/arch/arm/boot/dts/sama5d33.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" - -/ { - compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts deleted file mode 100644 index 7d4ae1682933..000000000000 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d33.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_gmac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D33-EK"; - compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi deleted file mode 100644 index 132918c889a0..000000000000 --- a/arch/arm/boot/dts/sama5d34.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" - -/ { - compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts deleted file mode 100644 index bffd61397cb5..000000000000 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d34.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_gmac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D34-EK"; - compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - - 24c256@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - }; - }; - - leds { - led-d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi deleted file mode 100644 index b2ccfa77c4be..000000000000 --- a/arch/arm/boot/dts/sama5d35.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" -#include "sama5d3_tcb1.dtsi" - -/ { - compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts deleted file mode 100644 index 8edfcebb1df0..000000000000 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d35.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xmb_gmac.dtsi" - -/ { - model = "Atmel SAMA5D35-EK"; - compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - isi: isi@f0034000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi deleted file mode 100644 index 5d88f9967138..000000000000 --- a/arch/arm/boot/dts/sama5d36.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC - * - * Copyright (C) 2013 Atmel, - * 2013 Josh Wu - */ -#include "sama5d3.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_tcb1.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts deleted file mode 100644 index 26950f9284c2..000000000000 --- a/arch/arm/boot/dts/sama5d36ek.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Josh Wu - */ -/dts-v1/; -#include "sama5d36.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xdm.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xmb_gmac.dtsi" - -/ { - model = "Atmel SAMA5D36-EK"; - compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/sama5d36ek_cmp.dts b/arch/arm/boot/dts/sama5d36ek_cmp.dts deleted file mode 100644 index 66695b9a3e77..000000000000 --- a/arch/arm/boot/dts/sama5d36ek_cmp.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board - * - * Copyright (C) 2016 Atmel, - */ -/dts-v1/; -#include "sama5d36.dtsi" -#include "sama5d3xmb_cmp.dtsi" - -/ { - model = "Atmel SAMA5D36EK-CMP"; - compatible = "atmel,sama5d36ek-cmp", "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi deleted file mode 100644 index 9ac29bf3f933..000000000000 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with - * CAN support - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* PB15 periph B TX, conflicts with GCOL */ - }; - }; - - }; - - can0: can@f000c000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf000c000 0x300>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8010000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8010000 0x300>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; - clock-names = "can_clk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi deleted file mode 100644 index 5d7ce13de8cc..000000000000 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with - * Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; /* PC9 periph A EMDIO */ - }; - }; - }; - - pmc: clock-controller@fffffc00 { - }; - - macb1: ethernet@f802c000 { - compatible = "atmel,sama5d3-macb", "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi deleted file mode 100644 index 884df7a54dbb..000000000000 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with - * Gigabit Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb0 { - pinctrl_macb0_data_rgmii: macb0_data_rgmii { - atmel,pins = - ; /* PB7 periph A GRX3, conflicts with RK1 */ - }; - pinctrl_macb0_data_gmii: macb0_data_gmii { - atmel,pins = - ; /* PB26 periph B GRX7, conflicts with CTS1 */ - }; - pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { - atmel,pins = - ; /* PB18 periph A G125CK */ - }; - pinctrl_macb0_signal_gmii: macb0_signal_gmii { - atmel,pins = - ; /* PB27 periph B G125CKO */ - }; - - }; - }; - - macb0: ethernet@f0028000 { - compatible = "atmel,sama5d3-gem"; - reg = <0xf0028000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi deleted file mode 100644 index 308d2fc276d6..000000000000 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with - * LCD support - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - pinctrl@fffff200 { - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - - pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi deleted file mode 100644 index 7141ee97ec3e..000000000000 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with - * 3 MMC ports - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - mmc2 { - pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { - atmel,pins = - ; /* PC11 periph A MCI2_DA0 with pullup */ - }; - pinctrl_mmc2_dat1_3: mmc2_dat1_3 { - atmel,pins = - ; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ - }; - }; - }; - - mmc2: mmc@f8004000 { - compatible = "atmel,hsmci"; - reg = <0xf8004000 0x600>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "mci_clk"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi deleted file mode 100644 index 2b18c5c2cc03..000000000000 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with - * 2 TC blocks. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include - -/ { - aliases { - tcb1 = &tcb1; - }; - - ahb { - apb { - tcb1: timer@f8014000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8014000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi deleted file mode 100644 index 44d1173f2ffb..000000000000 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with - * UART support - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include -#include - -/ { - aliases { - serial5 = &uart0; - serial6 = &uart1; - }; - - ahb { - apb { - pinctrl@fffff200 { - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* conflicts with TWCK0, ISI_HSYNC */ - }; - }; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x100>; - atmel,usart-mode = ; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x100>; - atmel,usart-mode = ; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; - clock-names = "usart"; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi deleted file mode 100644 index 7d1d7859edb4..000000000000 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ - -/ { - compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; - }; - - tcb0: timer@f0010000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - }; - - ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>; - pinctr-name = "default"; - status = "okay"; - - nor: flash@0,0 { - compatible = "cfi-flash"; - linux,mtd-name = "physmap-flash.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x1000000>; - bank-width = <2>; - atmel,smc-read-mode = "nrd"; - atmel,smc-write-mode = "nwe"; - atmel,smc-bus-width = <16>; - atmel,smc-ncs-rd-setup-ns = <0>; - atmel,smc-ncs-wr-setup-ns = <0>; - atmel,smc-nwe-setup-ns = <8>; - atmel,smc-nrd-setup-ns = <16>; - atmel,smc-ncs-rd-pulse-ns = <84>; - atmel,smc-ncs-wr-pulse-ns = <84>; - atmel,smc-nrd-pulse-ns = <76>; - atmel,smc-nwe-pulse-ns = <76>; - atmel,smc-nrd-cycle-ns = <107>; - atmel,smc-nwe-cycle-ns = <84>; - atmel,smc-tdf-ns = <16>; - }; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-d2 { - label = "d2"; - gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi deleted file mode 100644 index 830a0954ba1b..000000000000 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module - * - * Copyright (C) 2016 Atmel, - */ - -/ { - compatible = "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; - }; - - tcb0: timer@f0010000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - }; - - i2c1: i2c@f0018000 { - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "disabled"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddana_reg: LDO_REG1 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG2 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - }; - }; - }; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-d2 { - label = "d2"; - gpios = <&pioE 25 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi deleted file mode 100644 index 3c1c4d62fbf9..000000000000 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3dm.dtsi - Device Tree file for SAMA5 display module - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ - -/ { - ahb { - apb { - i2c1: i2c@f0018000 { - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioE>; - interrupts = <31 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - }; - - adc0: adc@f8018000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; /* PE31 GPIO with pull up deglith */ - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi deleted file mode 100644 index 3652c9e24124..000000000000 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -#include "sama5d3xcm.dtsi" - -/ { - compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - }; - }; - - spi0: spi@f0004000 { - dmas = <0>, <0>; /* Do not use DMA for spi0 */ - - flash@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - ssc0: ssc@f0008000 { - atmel,clk-from-rk-pin; - }; - - /* - * i2c0 conflicts with ISI: - * disable it to allow the use of ISI - * can not enable audio when i2c0 disabled - */ - i2c0: i2c@f0014000 { - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pmc PMC_TYPE_SYSTEM 8>; - clock-names = "mclk"; - }; - }; - - i2c1: i2c@f0018000 { - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - /* use pck1 for the master clock of ov2640 */ - clocks = <&pmc PMC_TYPE_SYSTEM 9>; - clock-names = "xvclk"; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - usart1: serial@f0020000 { - dmas = <0>, <0>; /* Do not use DMA for usart1 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - isi: isi@f0034000 { - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - mmc1: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; - }; - }; - - adc0: adc@f8018000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; /* PD17 GPIO with pullup deglitch */ - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; /* PD18 GPIO with pullup deglitch */ - }; - - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; /* PD30 periph B */ - }; - - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; /* PD31 periph B ISI_MCK */ - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; /* PE24 gpio */ - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; /* PE29 gpio */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; /* PD29 GPIO with deglitch */ - }; - }; - }; - - dbgu: serial@ffffee00 { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: gadget@500000 { - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@600000 { - num-ports = <3>; - atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH - &pioD 26 GPIO_ACTIVE_LOW - &pioD 27 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@700000 { - status = "okay"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D3EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi deleted file mode 100644 index 5d9e97fecf83..000000000000 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board - * - * Copyright (C) 2016 Atmel, - */ -#include "sama5d3xcm_cmp.dtsi" - -/ { - compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - }; - }; - - spi0: spi@f0004000 { - dmas = <0>, <0>; /* Do not use DMA for spi0 */ - - flash@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - ssc0: ssc@f0008000 { - atmel,clk-from-rk-pin; - }; - - /* - * i2c0 conflicts with ISI: - * disable it to allow the use of ISI - * can not enable audio when i2c0 disabled - */ - i2c0: i2c@f0014000 { - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pmc PMC_TYPE_SYSTEM 8>; - clock-names = "mclk"; - }; - }; - - i2c1: i2c@f0018000 { - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - /* use pck1 for the master clock of ov2640 */ - clocks = <&pmc PMC_TYPE_SYSTEM 9>; - clock-names = "xvclk"; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - usart1: serial@f0020000 { - dmas = <0>, <0>; /* Do not use DMA for usart1 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - isi: isi@f0034000 { - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - mmc1: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; - }; - }; - - adc0: adc@f8018000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - pinctrl-1 = < - &pinctrl_adc0_adtrg_sleep - &pinctrl_adc0_ad0_sleep - &pinctrl_adc0_ad1_sleep - &pinctrl_adc0_ad2_sleep - &pinctrl_adc0_ad3_sleep - &pinctrl_adc0_ad4_sleep - >; - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - /*interrupt-parent = <&pioE>;*/ - /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ - reg = <1>; - }; - }; - - pinctrl@fffff200 { - adc0 { - pinctrl_adc0_adtrg_sleep: adc0_adtrg_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad0_sleep: adc0_ad0_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad1_sleep: adc0_ad1_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad2_sleep: adc0_ad2_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad3_sleep: adc0_ad3_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad4_sleep: adc0_ad4_1 { - atmel,pins = - ; - }; - }; - - board { - pinctrl_gpio_keys: gpio_keys { - atmel,pins = - ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; - }; - - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - - dbgu: serial@ffffee00 { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: gadget@500000 { - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D3EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "disabled"; - }; - - /* Conflict with LCD pins */ - gpio_keys { - compatible = "gpio-keys"; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xmb_emac.dtsi b/arch/arm/boot/dts/sama5d3xmb_emac.dtsi deleted file mode 100644 index a5dd41cd9522..000000000000 --- a/arch/arm/boot/dts/sama5d3xmb_emac.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board - * Ethernet - * - * Copyright (C) 2016 Atmel, - */ - -/ { - ahb { - apb { - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; - reg = <1>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi b/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi deleted file mode 100644 index d750da38ff3c..000000000000 --- a/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard - * Gigabit Ethernet - * - * Copyright (C) 2016 Atmel, - */ - -/ { - ahb { - apb { - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi deleted file mode 100644 index de6c82969232..000000000000 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ /dev/null @@ -1,1453 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel SAMA5D4 family SoC"; - compatible = "atmel,sama5d4"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &usart3; - serial1 = &usart4; - serial2 = &usart2; - serial3 = &usart0; - serial4 = &usart1; - serial5 = &uart0; - serial6 = &uart1; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - pwm0 = &pwm0; - ssc0 = &ssc0; - ssc1 = &ssc1; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - ns_sram: sram@210000 { - compatible = "mmio-sram"; - reg = <0x00210000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00210000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nfc_sram: sram@100000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x100000 0x2400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x100000 0x2400>; - }; - - vdec0: vdec@300000 { - compatible = "microchip,sama5d4-vdec"; - reg = <0x00300000 0x100000>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - }; - - usb0: gadget@400000 { - compatible = "atmel,sama5d3-udc"; - reg = <0x00400000 0x100000 - 0xfc02c000 0x4000>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - usb1: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@600000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00600000 0x100000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - L2: cache-controller@a00000 { - compatible = "arm,pl310-cache"; - reg = <0x00a00000 0x1000>; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; - cache-unified; - cache-level = <2>; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x60000000 0x28000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x60000000 0x10000000 - 0x2 0x0 0x70000000 0x10000000 - 0x3 0x0 0x80000000 0x8000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - nfc_io: nfc-io@90000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x90000000 0x8000000>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d4-hlcdc"; - reg = <0xf0000000 0x4000>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - dma1: dma-controller@f0004000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0004000 0x200>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; - clock-names = "dma_clk"; - }; - - isi: isi@f0008000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0008000 0x4000>; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ramc0: ramc@f0010000 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xf0010000 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "ddrck", "mpddr"; - }; - - dma0: dma-controller@f0014000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0014000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "dma_clk"; - }; - - pmc: clock-controller@f0018000 { - compatible = "atmel,sama5d4-pmc", "syscon"; - reg = <0xf0018000 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - mmc0: mmc@f8000000 { - compatible = "atmel,hsmci"; - reg = <0xf8000000 0x600>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(0))>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; - clock-names = "mci_clk"; - }; - - uart0: serial@f8004000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8004000 0x100>; - atmel,usart-mode = ; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(22))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(23))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@f8008000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf8008000 0x4000>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(26))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; - clock-names = "pclk"; - status = "disabled"; - }; - - pwm0: pwm@f800c000 { - compatible = "atmel,sama5d3-pwm"; - reg = <0xf800c000 0x300>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - status = "disabled"; - }; - - spi0: spi@f8010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8010000 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(10))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - i2c0: i2c@f8014000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8014000 0x4000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(2))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; - status = "disabled"; - }; - - i2c1: i2c@f8018000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8018000 0x4000>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(4))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(5))>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - status = "disabled"; - }; - - tcb0: timer@f801c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf801c000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - macb0: ethernet@f8020000 { - compatible = "atmel,sama5d4-gem"; - reg = <0xf8020000 0x100>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - i2c2: i2c@f8024000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8024000 0x4000>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(6))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; - status = "disabled"; - }; - - sfr: sfr@f8028000 { - compatible = "atmel,sama5d4-sfr", "syscon"; - reg = <0xf8028000 0x60>; - }; - - usart0: serial@f802c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf802c000 0x100>; - atmel,usart-mode = ; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(36))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8030000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8030000 0x100>; - atmel,usart-mode = ; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(38))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(39))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - mmc1: mmc@fc000000 { - compatible = "atmel,hsmci"; - reg = <0xfc000000 0x600>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(1))>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; - clock-names = "mci_clk"; - }; - - uart1: serial@fc004000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc004000 0x100>; - atmel,usart-mode = ; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(24))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(25))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fc008000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc008000 0x100>; - atmel,usart-mode = ; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(16))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fc00c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc00c000 0x100>; - atmel,usart-mode = ; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "usart"; - status = "disabled"; - }; - - usart4: serial@fc010000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc010000 0x100>; - atmel,usart-mode = ; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(21))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc1: ssc@fc014000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfc014000 0x4000>; - interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(28))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi1: spi@fc018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc018000 0x100>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(13))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi2: spi@fc01c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc01c000 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(14))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(15))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - tcb1: timer@fc020000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc020000 0x100>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb2: timer@fc024000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc024000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - macb1: ethernet@fc028000 { - compatible = "atmel,sama5d4-gem"; - reg = <0xfc028000 0x100>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - trng@fc030000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfc030000 0x100>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; - }; - - adc0: adc@fc034000 { - compatible = "atmel,at91sam9x5-adc"; - reg = <0xfc034000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0x01f>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3000>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "disabled"; - }; - - aes: crypto@fc044000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xfc044000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(41))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(40))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "aes_clk"; - }; - - tdes: crpyto@fc04c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xfc04c000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(42))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(43))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "tdes_clk"; - }; - - sha: crypto@fc050000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xfc050000 0x100>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(44))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "sha_clk"; - }; - - hsmc: smc@fc05c000 { - compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; - reg = <0xfc05c000 0x1000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@ffffc070 { - compatible = "atmel,sama5d4-pmecc"; - reg = <0xfc05c070 0x490>, - <0xfc05c500 0x100>; - }; - }; - - reset_controller: reset-controller@fc068600 { - compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; - reg = <0xfc068600 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shdwc@fc068610 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfc068610 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fc068630 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfc068630 0x10>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; - }; - - watchdog: watchdog@fc068640 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xfc068640 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - clk32k: clock-controller@fc068650 { - compatible = "atmel,sama5d4-sckc"; - reg = <0xfc068650 0x4>; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - rtc@fc0686b0 { - compatible = "atmel,sama5d4-rtc"; - reg = <0xfc0686b0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - - dbgu: serial@fc069000 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfc069000 0x200>; - atmel,usart-mode = ; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; - clock-names = "usart"; - status = "disabled"; - }; - - - pinctrl: pinctrl@fc06a000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; - ranges = <0xfc068000 0xfc068000 0x100 - 0xfc06a000 0xfc06a000 0x4000>; - /* WARNING: revisit as pin spec has changed */ - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ - 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ - 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ - 0xb003ff00 0x8002a800 0x00000000 /* pioD */ - 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ - >; - - pioA: gpio@fc06a000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06a000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - }; - - pioB: gpio@fc06b000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06b000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - }; - - pioC: gpio@fc06c000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06c000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - }; - - pioD: gpio@fc068000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc068000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - - pioE: gpio@fc06d000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06d000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - }; - - /* pinctrl pin settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = - ; /* conflicts with USBA_VBUS */ - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = - ; - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = - ; - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = - ; - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = - ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* conflicts with D15 and TDO */ - }; - }; - - ebi { - pinctrl_ebi_addr: ebi-addr-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nand_addr: ebi-addr-1 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs0: ebi-cs0-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs1: ebi-cs1-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs2: ebi-cs2-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs3: ebi-cs3-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_8_15: ebi-data-msb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nandrdy: ebi-nandrdy-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwait: ebi-nwait-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { - atmel,pins = - ; - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; - }; - - pinctrl_i2c0_gpio: i2c0-gpio { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* TWCK1, conflicts with UART0 TX and DIBN */ - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - atmel,pins = - ; - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* TWCK2, conflicts with RF0 */ - }; - - pinctrl_i2c2_gpio: i2c2-gpio { - atmel,pins = - ; - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* ISI_HSYNC */ - }; - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ - }; - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ - }; - }; - - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD23 pin */ - }; - pinctrl_lcd_rgb777: lcd-rgb-3 { - atmel,pins = - /* LCDDAT0 conflicts with TMS */ - ; /* LCDD23 pin */ - }; - pinctrl_lcd_rgb888: lcd-rgb-4 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; - }; - }; - - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { - atmel,pins = - ; - }; - pinctrl_mmc0_dat1_3: mmc0_dat1_3 { - atmel,pins = - ; - }; - pinctrl_mmc0_dat4_7: mmc0_dat4_7 { - atmel,pins = - ; - }; - }; - - mmc1 { - pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { - atmel,pins = - ; - }; - pinctrl_mmc1_dat1_3: mmc1_dat1_3 { - atmel,pins = - ; - }; - }; - - nand0 { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PC12 periph A Data bit 7 */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx { - atmel,pins = - ; /* TD0 */ - }; - - pinctrl_ssc0_rx: ssc0_rx { - atmel,pins = - ; /* RD0 */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx { - atmel,pins = - ; /* TD1 */ - }; - - pinctrl_ssc1_rx: ssc1_rx { - atmel,pins = - ; /* RD1 */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; - }; - }; - - spi2 { - pinctrl_spi2: spi2-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = ; - }; - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = ; - }; - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ - }; - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - }; - - usart4 { - pinctrl_usart4: usart4-0 { - atmel,pins = - ; - }; - pinctrl_usart4_rts: usart4_rts-0 { - atmel,pins = ; /* conflicts with NWAIT, A19 */ - }; - pinctrl_usart4_cts: usart4_cts-0 { - atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ - }; - }; - }; - - aic: interrupt-controller@fc06e000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d4-aic"; - interrupt-controller; - reg = <0xfc06e000 0x200>; - atmel,external-irqs = <56>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h deleted file mode 100644 index a67a156e26ab..000000000000 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ /dev/null @@ -1,923 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -#define PINMUX_PIN(no, func, ioset) \ -(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) - -#define PIN_PA0 0 -#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) -#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) -#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) -#define PIN_PA1 1 -#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) -#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) -#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) -#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) -#define PIN_PA2 2 -#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) -#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) -#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) -#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) -#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) -#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) -#define PIN_PA3 3 -#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) -#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) -#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) -#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) -#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) -#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) -#define PIN_PA4 4 -#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) -#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) -#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) -#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) -#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) -#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) -#define PIN_PA5 5 -#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) -#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) -#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) -#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) -#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) -#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) -#define PIN_PA6 6 -#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) -#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) -#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) -#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) -#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) -#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) -#define PIN_PA7 7 -#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) -#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) -#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) -#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) -#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) -#define PIN_PA8 8 -#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) -#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) -#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) -#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) -#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) -#define PIN_PA9 9 -#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) -#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) -#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) -#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) -#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) -#define PIN_PA10 10 -#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) -#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) -#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) -#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) -#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) -#define PIN_PA11 11 -#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) -#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) -#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) -#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) -#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) -#define PIN_PA12 12 -#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) -#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) -#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) -#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) -#define PIN_PA13 13 -#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) -#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) -#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) -#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) -#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) -#define PIN_PA14 14 -#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) -#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) -#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) -#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) -#define PIN_PA15 15 -#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) -#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) -#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) -#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) -#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) -#define PIN_PA16 16 -#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) -#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) -#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) -#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) -#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) -#define PIN_PA17 17 -#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) -#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) -#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) -#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) -#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) -#define PIN_PA18 18 -#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) -#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) -#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) -#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) -#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) -#define PIN_PA19 19 -#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) -#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) -#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) -#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) -#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) -#define PIN_PA20 20 -#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) -#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) -#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) -#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) -#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) -#define PIN_PA21 21 -#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) -#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) -#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) -#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) -#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) -#define PIN_PA22 22 -#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) -#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) -#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) -#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) -#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) -#define PIN_PA23 23 -#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) -#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) -#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) -#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) -#define PIN_PA24 24 -#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) -#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) -#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) -#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) -#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) -#define PIN_PA25 25 -#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) -#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) -#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) -#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) -#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) -#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) -#define PIN_PA26 26 -#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) -#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) -#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) -#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) -#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) -#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) -#define PIN_PA27 27 -#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) -#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) -#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) -#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) -#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) -#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) -#define PIN_PA28 28 -#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) -#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) -#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) -#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) -#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) -#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) -#define PIN_PA29 29 -#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) -#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) -#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) -#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) -#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) -#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) -#define PIN_PA30 30 -#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) -#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) -#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) -#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) -#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) -#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) -#define PIN_PA31 31 -#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) -#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) -#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) -#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) -#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) -#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) -#define PIN_PB0 32 -#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) -#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) -#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) -#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) -#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) -#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) -#define PIN_PB1 33 -#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) -#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) -#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) -#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) -#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) -#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) -#define PIN_PB2 34 -#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) -#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) -#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) -#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3) -#define PIN_PB3 35 -#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) -#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) -#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) -#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) -#define PIN_PB4 36 -#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) -#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) -#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) -#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) -#define PIN_PB5 37 -#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) -#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) -#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) -#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) -#define PIN_PB6 38 -#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) -#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) -#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) -#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) -#define PIN_PB7 39 -#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) -#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) -#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) -#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) -#define PIN_PB8 40 -#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) -#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) -#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) -#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) -#define PIN_PB9 41 -#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) -#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) -#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) -#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) -#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) -#define PIN_PB10 42 -#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) -#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) -#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) -#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) -#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) -#define PIN_PB11 43 -#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) -#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) -#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) -#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) -#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) -#define PIN_PB12 44 -#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) -#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) -#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) -#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) -#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) -#define PIN_PB13 45 -#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) -#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) -#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) -#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) -#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) -#define PIN_PB14 46 -#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) -#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) -#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) -#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) -#define PIN_PB15 47 -#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) -#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) -#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) -#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) -#define PIN_PB16 48 -#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) -#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) -#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) -#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) -#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) -#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) -#define PIN_PB17 49 -#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) -#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) -#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) -#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) -#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) -#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) -#define PIN_PB18 50 -#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) -#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) -#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) -#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) -#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) -#define PIN_PB19 51 -#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) -#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) -#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) -#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) -#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) -#define PIN_PB20 52 -#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) -#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) -#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) -#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) -#define PIN_PB21 53 -#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) -#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) -#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) -#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) -#define PIN_PB22 54 -#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) -#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) -#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) -#define PIN_PB23 55 -#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) -#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) -#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) -#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) -#define PIN_PB24 56 -#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) -#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) -#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) -#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) -#define PIN_PB25 57 -#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) -#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) -#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) -#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) -#define PIN_PB26 58 -#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) -#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) -#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) -#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) -#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) -#define PIN_PB27 59 -#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) -#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) -#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) -#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) -#define PIN_PB28 60 -#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) -#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) -#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) -#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) -#define PIN_PB29 61 -#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) -#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) -#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) -#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) -#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) -#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) -#define PIN_PB30 62 -#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) -#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) -#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) -#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) -#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) -#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) -#define PIN_PB31 63 -#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) -#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) -#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) -#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) -#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) -#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) -#define PIN_PC0 64 -#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) -#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) -#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) -#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) -#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) -#define PIN_PC1 65 -#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) -#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) -#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) -#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) -#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) -#define PIN_PC2 66 -#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) -#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) -#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) -#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) -#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) -#define PIN_PC3 67 -#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) -#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) -#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) -#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) -#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) -#define PIN_PC4 68 -#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) -#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) -#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) -#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) -#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) -#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) -#define PIN_PC5 69 -#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) -#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) -#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) -#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) -#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) -#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) -#define PIN_PC6 70 -#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) -#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) -#define PIN_PC7 71 -#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) -#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) -#define PIN_PC8 72 -#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) -#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) -#define PIN_PC9 73 -#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) -#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) -#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) -#define PIN_PC10 74 -#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) -#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) -#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) -#define PIN_PC11 75 -#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) -#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) -#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) -#define PIN_PC12 76 -#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) -#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) -#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) -#define PIN_PC13 77 -#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) -#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) -#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) -#define PIN_PC14 78 -#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) -#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) -#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) -#define PIN_PC15 79 -#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) -#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) -#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) -#define PIN_PC16 80 -#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) -#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) -#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) -#define PIN_PC17 81 -#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) -#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) -#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) -#define PIN_PC18 82 -#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) -#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) -#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) -#define PIN_PC19 83 -#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) -#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) -#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) -#define PIN_PC20 84 -#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) -#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) -#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) -#define PIN_PC21 85 -#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) -#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) -#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) -#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) -#define PIN_PC22 86 -#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) -#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) -#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) -#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) -#define PIN_PC23 87 -#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) -#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) -#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) -#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) -#define PIN_PC24 88 -#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) -#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) -#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) -#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) -#define PIN_PC25 89 -#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) -#define PIN_PC26 90 -#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) -#define PIN_PC27 91 -#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) -#define PIN_PC28 92 -#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) -#define PIN_PC29 93 -#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) -#define PIN_PC30 94 -#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) -#define PIN_PC31 95 -#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) -#define PIN_PD0 96 -#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) -#define PIN_PD1 97 -#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) -#define PIN_PD2 98 -#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) -#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) -#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) -#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) -#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) -#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) -#define PIN_PD3 99 -#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) -#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) -#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) -#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) -#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) -#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) -#define PIN_PD4 100 -#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) -#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) -#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) -#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) -#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) -#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) -#define PIN_PD5 101 -#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) -#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) -#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) -#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) -#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) -#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) -#define PIN_PD6 102 -#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) -#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) -#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) -#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) -#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) -#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) -#define PIN_PD7 103 -#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) -#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) -#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) -#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) -#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) -#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) -#define PIN_PD8 104 -#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) -#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) -#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) -#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) -#define PIN_PD9 105 -#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) -#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) -#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) -#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) -#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) -#define PIN_PD10 106 -#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) -#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) -#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) -#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) -#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) -#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) -#define PIN_PD11 107 -#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) -#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) -#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) -#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) -#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) -#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) -#define PIN_PD12 108 -#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) -#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) -#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) -#define PIN_PD13 109 -#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) -#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) -#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) -#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) -#define PIN_PD14 110 -#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) -#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) -#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) -#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) -#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) -#define PIN_PD15 111 -#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) -#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) -#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) -#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) -#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) -#define PIN_PD16 112 -#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) -#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) -#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) -#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) -#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) -#define PIN_PD17 113 -#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) -#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) -#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) -#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) -#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) -#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) -#define PIN_PD18 114 -#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) -#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) -#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) -#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) -#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) -#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) -#define PIN_PD19 115 -#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) -#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) -#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) -#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) -#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) -#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) -#define PIN_PD20 116 -#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) -#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) -#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) -#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) -#define PIN_PD21 117 -#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) -#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) -#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) -#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) -#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) -#define PIN_PD22 118 -#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) -#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) -#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) -#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) -#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) -#define PIN_PD23 119 -#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) -#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) -#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) -#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) -#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) -#define PIN_PD24 120 -#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) -#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) -#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) -#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) -#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) -#define PIN_PD25 121 -#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) -#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) -#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) -#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) -#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) -#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) -#define PIN_PD26 122 -#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) -#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) -#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) -#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) -#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) -#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) -#define PIN_PD27 123 -#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) -#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) -#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) -#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) -#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) -#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) -#define PIN_PD28 124 -#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) -#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) -#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) -#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) -#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) -#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) -#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) -#define PIN_PD29 125 -#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) -#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) -#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) -#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) -#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) -#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) -#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) -#define PIN_PD30 126 -#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) -#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) -#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) -#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) -#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) -#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) -#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) -#define PIN_PD31 127 -#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) -#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) -#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) -#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) -#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) -#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) -#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) -#define PIN_PE0 128 -#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) -#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) -#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) -#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) -#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) -#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) -#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) -#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) -#define PIN_PE1 129 -#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) -#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) -#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) -#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) -#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) -#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) -#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) -#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) -#define PIN_PE2 130 -#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) -#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) -#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) -#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) -#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) -#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) -#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) -#define PIN_PE3 131 -#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) -#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) -#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) -#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) -#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) -#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) -#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) -#define PIN_PE4 132 -#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) -#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) -#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) -#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) -#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) -#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) -#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) -#define PIN_PE5 133 -#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) -#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) -#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) -#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) -#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) -#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) -#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) -#define PIN_PE6 134 -#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) -#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) -#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) -#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) -#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) -#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) -#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) -#define PIN_PE7 135 -#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) -#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) -#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) -#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) -#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) -#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi deleted file mode 100644 index b55adb96a06e..000000000000 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ /dev/null @@ -1,1016 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC - * - * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries - * - * Author: Eugen Hristev - * Author: Claudiu Beznea - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - model = "Microchip SAMA7G5 family SoC"; - compatible = "microchip,sama7g5"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-90000000 { - opp-hz = /bits/ 64 <90000000>; - opp-microvolt = <1050000 1050000 1225000>; - clock-latency-ns = <320000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <1050000 1050000 1225000>; - clock-latency-ns = <320000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1050000 1050000 1225000>; - clock-latency-ns = <320000>; - opp-suspend; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1150000 1125000 1225000>; - clock-latency-ns = <320000>; - }; - - opp-1000000002 { - opp-hz = /bits/ 64 <1000000002>; - opp-microvolt = <1250000 1225000 1300000>; - clock-latency-ns = <320000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&thermal_sensor>; - - trips { - cpu_normal: cpu-alert0 { - temperature = <90000>; - hysteresis = <0>; - type = "passive"; - }; - - cpu_hot: cpu-alert1 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - cpu_critical: cpu-critical { - temperature = <100000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_normal>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - usb_clk: usb_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - }; - - vddout25: fixed-regulator-vddout25 { - compatible = "regulator-fixed"; - - regulator-name = "VDDOUT25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - status = "disabled"; - }; - - ns_sram: sram@100000 { - compatible = "mmio-sram"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x100000 0x20000>; - ranges; - }; - - thermal_sensor: thermal-sensor { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; - io-channel-names = "sensor-channel"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nfc_sram: sram@600000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x00600000 0x2400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00600000 0x2400>; - }; - - nfc_io: nfc-io@10000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x10000000 0x8000000>; - }; - - ebi: ebi@40000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x40000000 0x20000000>; - ranges = <0x0 0x0 0x40000000 0x8000000 - 0x1 0x0 0x48000000 0x8000000 - 0x2 0x0 0x50000000 0x8000000 - 0x3 0x0 0x58000000 0x8000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - securam: sram@e0000000 { - compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; - reg = <0xe0000000 0x4000>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe0000000 0x4000>; - no-memory-wc; - }; - - secumod: secumod@e0004000 { - compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; - reg = <0xe0004000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - }; - - sfrbu: sfr@e0008000 { - compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; - reg = <0xe0008000 0x20>; - }; - - pioA: pinctrl@e0014000 { - compatible = "microchip,sama7g5-pinctrl"; - reg = <0xe0014000 0x800>; - interrupts = , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - }; - - pmc: clock-controller@e0018000 { - compatible = "microchip,sama7g5-pmc", "syscon"; - reg = <0xe0018000 0x200>; - interrupts = ; - #clock-cells = <2>; - clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; - clock-names = "td_slck", "md_slck", "main_xtal"; - }; - - reset_controller: reset-controller@e001d000 { - compatible = "microchip,sama7g5-rstc"; - reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; - #reset-cells = <1>; - clocks = <&clk32k 0>; - }; - - shdwc: shdwc@e001d010 { - compatible = "microchip,sama7g5-shdwc", "syscon"; - reg = <0xe001d010 0x10>; - clocks = <&clk32k 0>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - atmel,wakeup-rtt-timer; - status = "disabled"; - }; - - rtt: rtc@e001d020 { - compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; - reg = <0xe001d020 0x30>; - interrupts = ; - clocks = <&clk32k 0>; - }; - - clk32k: clock-controller@e001d050 { - compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; - reg = <0xe001d050 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <1>; - }; - - gpbr: gpbr@e001d060 { - compatible = "microchip,sama7g5-gpbr", "syscon"; - reg = <0xe001d060 0x48>; - }; - - rtc: rtc@e001d0a8 { - compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; - reg = <0xe001d0a8 0x30>; - interrupts = ; - clocks = <&clk32k 1>; - }; - - ps_wdt: watchdog@e001d180 { - compatible = "microchip,sama7g5-wdt"; - reg = <0xe001d180 0x24>; - interrupts = ; - clocks = <&clk32k 0>; - }; - - chipid@e0020000 { - compatible = "microchip,sama7g5-chipid"; - reg = <0xe0020000 0x8>; - }; - - tcb1: timer@e0800000 { - compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xe0800000 0x100>; - interrupts = , , ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - hsmc: hsmc@e0808000 { - compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; - reg = <0xe0808000 0x1000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@e0808070 { - compatible = "atmel,sama5d2-pmecc"; - reg = <0xe0808070 0x490>, - <0xe0808500 0x200>; - }; - }; - - qspi0: spi@e080c000 { - compatible = "microchip,sama7g5-ospi"; - reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, - <&dma0 AT91_XDMAC_DT_PERID(40)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; - clock-names = "pclk", "gclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi1: spi@e0810000 { - compatible = "microchip,sama7g5-qspi"; - reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, - <&dma0 AT91_XDMAC_DT_PERID(42)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; - clock-names = "pclk", "gclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e0828000 { - compatible = "bosch,m_can"; - reg = <0xe0828000 0x100>, <0x100000 0x7800>; - reg-names = "m_can", "message_ram"; - interrupts = ; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 61>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - can1: can@e082c000 { - compatible = "bosch,m_can"; - reg = <0xe082c000 0x100>, <0x100000 0xbc00>; - reg-names = "m_can", "message_ram"; - interrupts = ; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 62>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - can2: can@e0830000 { - compatible = "bosch,m_can"; - reg = <0xe0830000 0x100>, <0x100000 0x10000>; - reg-names = "m_can", "message_ram"; - interrupts = ; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 63>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - can3: can@e0834000 { - compatible = "bosch,m_can"; - reg = <0xe0834000 0x100>, <0x110000 0x4400>; - reg-names = "m_can", "message_ram"; - interrupts = ; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 64>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - can4: can@e0838000 { - compatible = "bosch,m_can"; - reg = <0xe0838000 0x100>, <0x110000 0x8800>; - reg-names = "m_can", "message_ram"; - interrupts = ; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 65>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - can5: can@e083c000 { - compatible = "bosch,m_can"; - reg = <0xe083c000 0x100>, <0x110000 0xcc00>; - reg-names = "m_can", "message_ram"; - interrupts = ; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 66>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - adc: adc@e1000000 { - compatible = "microchip,sama7g5-adc"; - reg = <0xe1000000 0x200>; - interrupts = ; - clocks = <&pmc PMC_TYPE_GCK 26>; - assigned-clocks = <&pmc PMC_TYPE_GCK 26>; - assigned-clock-rates = <100000000>; - clock-names = "adc_clk"; - dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; - dma-names = "rx"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - #io-channel-cells = <1>; - nvmem-cells = <&temperature_calib>; - nvmem-cell-names = "temperature_calib"; - status = "disabled"; - }; - - sdmmc0: mmc@e1204000 { - compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; - reg = <0xe1204000 0x4000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; - clock-names = "hclock", "multclk"; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clocks = <&pmc PMC_TYPE_GCK 80>; - assigned-clock-rates = <200000000>; - microchip,sdcal-inverted; - status = "disabled"; - }; - - sdmmc1: mmc@e1208000 { - compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; - reg = <0xe1208000 0x4000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; - clock-names = "hclock", "multclk"; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clocks = <&pmc PMC_TYPE_GCK 81>; - assigned-clock-rates = <200000000>; - microchip,sdcal-inverted; - status = "disabled"; - }; - - sdmmc2: mmc@e120c000 { - compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; - reg = <0xe120c000 0x4000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; - clock-names = "hclock", "multclk"; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; - assigned-clocks = <&pmc PMC_TYPE_GCK 82>; - assigned-clock-rates = <200000000>; - microchip,sdcal-inverted; - status = "disabled"; - }; - - csi2dc: csi2dc@e1404000 { - compatible = "microchip,sama7g5-csi2dc"; - reg = <0xe1404000 0x500>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; - clock-names = "pclk", "scck"; - assigned-clocks = <&xisc>; - assigned-clock-rates = <266000000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - csi2dc_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - csi2dc_out: endpoint { - bus-width = <14>; - hsync-active = <1>; - vsync-active = <1>; - remote-endpoint = <&xisc_in>; - }; - }; - }; - }; - - xisc: xisc@e1408000 { - compatible = "microchip,sama7g5-isc"; - reg = <0xe1408000 0x2000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; - clock-names = "hclock"; - #clock-cells = <0>; - clock-output-names = "isc-mck"; - status = "disabled"; - - port { - xisc_in: endpoint { - bus-type = <5>; /* Parallel */ - bus-width = <14>; - hsync-active = <1>; - vsync-active = <1>; - remote-endpoint = <&csi2dc_out>; - }; - }; - }; - - pwm: pwm@e1604000 { - compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; - reg = <0xe1604000 0x4000>; - interrupts = ; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; - status = "disabled"; - }; - - pdmc0: sound@e1608000 { - compatible = "microchip,sama7g5-pdmc"; - reg = <0xe1608000 0x1000>; - interrupts = ; - #sound-dai-cells = <0>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; - dma-names = "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - pdmc1: sound@e160c000 { - compatible = "microchip,sama7g5-pdmc"; - reg = <0xe160c000 0x1000>; - interrupts = ; - #sound-dai-cells = <0>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; - dma-names = "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - spdifrx: spdifrx@e1614000 { - #sound-dai-cells = <0>; - compatible = "microchip,sama7g5-spdifrx"; - reg = <0xe1614000 0x4000>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; - dma-names = "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - spdiftx: spdiftx@e1618000 { - #sound-dai-cells = <0>; - compatible = "microchip,sama7g5-spdiftx"; - reg = <0xe1618000 0x4000>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; - clock-names = "pclk", "gclk"; - }; - - i2s0: i2s@e161c000 { - compatible = "microchip,sama7g5-i2smcc"; - #sound-dai-cells = <0>; - reg = <0xe161c000 0x4000>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - i2s1: i2s@e1620000 { - compatible = "microchip,sama7g5-i2smcc"; - #sound-dai-cells = <0>; - reg = <0xe1620000 0x4000>; - interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - eic: interrupt-controller@e1628000 { - compatible = "microchip,sama7g5-eic"; - reg = <0xe1628000 0xec>; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; - clock-names = "pclk"; - status = "disabled"; - }; - - pit64b0: timer@e1800000 { - compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; - reg = <0xe1800000 0x4000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; - clock-names = "pclk", "gclk"; - }; - - pit64b1: timer@e1804000 { - compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; - reg = <0xe1804000 0x4000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; - clock-names = "pclk", "gclk"; - }; - - aes: crypto@e1810000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xe1810000 0x100>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "aes_clk"; - dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, - <&dma0 AT91_XDMAC_DT_PERID(2)>; - dma-names = "tx", "rx"; - }; - - sha: crypto@e1814000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xe1814000 0x100>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; - clock-names = "sha_clk"; - dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; - dma-names = "tx"; - }; - - flx0: flexcom@e1818000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe1818000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe1818000 0x800>; - status = "disabled"; - - uart0: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - clock-names = "usart"; - dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, - <&dma1 AT91_XDMAC_DT_PERID(5)>; - dma-names = "tx", "rx"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; - }; - - flx1: flexcom@e181c000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe181c000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe181c000 0x800>; - status = "disabled"; - - i2c1: i2c@600 { - compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, - <&dma0 AT91_XDMAC_DT_PERID(7)>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - flx3: flexcom@e1824000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe1824000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe1824000 0x800>; - status = "disabled"; - - uart3: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; - clock-names = "usart"; - dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, - <&dma1 AT91_XDMAC_DT_PERID(11)>; - dma-names = "tx", "rx"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; - }; - - trng: rng@e2010000 { - compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; - reg = <0xe2010000 0x100>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; - status = "disabled"; - }; - - tdes: crypto@e2014000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xe2014000 0x100>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; - clock-names = "tdes_clk"; - dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, - <&dma0 AT91_XDMAC_DT_PERID(53)>; - dma-names = "tx", "rx"; - }; - - flx4: flexcom@e2018000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe2018000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe2018000 0x800>; - status = "disabled"; - - uart4: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; - clock-names = "usart"; - dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, - <&dma1 AT91_XDMAC_DT_PERID(13)>; - dma-names = "tx", "rx"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - flx7: flexcom@e2024000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe2024000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe2024000 0x800>; - status = "disabled"; - - uart7: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; - clock-names = "usart"; - dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, - <&dma1 AT91_XDMAC_DT_PERID(19)>; - dma-names = "tx", "rx"; - atmel,use-dma-rx; - atmel,use-dma-tx; - atmel,fifo-size = <16>; - status = "disabled"; - }; - }; - - gmac0: ethernet@e2800000 { - compatible = "microchip,sama7g5-gem"; - reg = <0xe2800000 0x1000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; - clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 51>; - assigned-clock-rates = <125000000>; - status = "disabled"; - }; - - gmac1: ethernet@e2804000 { - compatible = "microchip,sama7g5-emac"; - reg = <0xe2804000 0x1000>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - dma0: dma-controller@e2808000 { - compatible = "microchip,sama7g5-dma"; - reg = <0xe2808000 0x1000>; - interrupts = ; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "dma_clk"; - status = "disabled"; - }; - - dma1: dma-controller@e280c000 { - compatible = "microchip,sama7g5-dma"; - reg = <0xe280c000 0x1000>; - interrupts = ; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "dma_clk"; - status = "disabled"; - }; - - /* Place dma2 here despite it's address */ - dma2: dma-controller@e1200000 { - compatible = "microchip,sama7g5-dma"; - reg = <0xe1200000 0x1000>; - interrupts = ; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "dma_clk"; - dma-requests = <0>; - status = "disabled"; - }; - - tcb0: timer@e2814000 { - compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xe2814000 0x100>; - interrupts = , , ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - flx8: flexcom@e2818000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe2818000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe2818000 0x800>; - status = "disabled"; - - i2c8: i2c@600 { - compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; - atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, - <&dma0 AT91_XDMAC_DT_PERID(21)>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - flx9: flexcom@e281c000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe281c000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe281c000 0x800>; - status = "disabled"; - - i2c9: i2c@600 { - compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; - atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, - <&dma0 AT91_XDMAC_DT_PERID(23)>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - flx11: flexcom@e2824000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe2824000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe2824000 0x800>; - status = "disabled"; - - spi11: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; - clock-names = "spi_clk"; - #address-cells = <1>; - #size-cells = <0>; - atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, - <&dma0 AT91_XDMAC_DT_PERID(27)>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - uddrc: uddrc@e3800000 { - compatible = "microchip,sama7g5-uddrc"; - reg = <0xe3800000 0x4000>; - }; - - ddr3phy: ddr3phy@e3804000 { - compatible = "microchip,sama7g5-ddr3phy"; - reg = <0xe3804000 0x1000>; - }; - - otpc: efuse@e8c00000 { - compatible = "microchip,sama7g5-otpc", "syscon"; - reg = <0xe8c00000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - temperature_calib: calib@1 { - reg = ; - }; - }; - - gic: interrupt-controller@e8c11000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8c11000 0x1000>, - <0xe8c12000 0x2000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/samsung/Makefile b/arch/arm/boot/dts/samsung/Makefile new file mode 100644 index 000000000000..c8d067abdd59 --- /dev/null +++ b/arch/arm/boot/dts/samsung/Makefile @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_EXYNOS3) += \ + exynos3250-artik5-eval.dtb \ + exynos3250-monk.dtb \ + exynos3250-rinato.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += \ + exynos4210-i9100.dtb \ + exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos4210-trats.dtb \ + exynos4210-universal_c210.dtb \ + exynos4412-i9300.dtb \ + exynos4412-i9305.dtb \ + exynos4412-itop-elite.dtb \ + exynos4412-n710x.dtb \ + exynos4412-odroidu3.dtb \ + exynos4412-odroidx.dtb \ + exynos4412-odroidx2.dtb \ + exynos4412-origen.dtb \ + exynos4412-p4note-n8010.dtb \ + exynos4412-smdk4412.dtb \ + exynos4412-tiny4412.dtb \ + exynos4412-trats2.dtb +dtb-$(CONFIG_ARCH_EXYNOS5) += \ + exynos5250-arndale.dtb \ + exynos5250-smdk5250.dtb \ + exynos5250-snow.dtb \ + exynos5250-snow-rev5.dtb \ + exynos5250-spring.dtb \ + exynos5260-xyref5260.dtb \ + exynos5410-odroidxu.dtb \ + exynos5410-smdk5410.dtb \ + exynos5420-arndale-octa.dtb \ + exynos5420-peach-pit.dtb \ + exynos5420-smdk5420.dtb \ + exynos5420-chagall-wifi.dtb \ + exynos5420-klimt-wifi.dtb \ + exynos5422-odroidhc1.dtb \ + exynos5422-odroidxu3.dtb \ + exynos5422-odroidxu3-lite.dtb \ + exynos5422-odroidxu4.dtb \ + exynos5422-samsung-k3g.dtb \ + exynos5800-peach-pi.dtb +dtb-$(CONFIG_ARCH_S3C64XX) += \ + s3c6410-mini6410.dtb \ + s3c6410-smdk6410.dtb +dtb-$(CONFIG_ARCH_S5PV210) += \ + s5pv210-aquila.dtb \ + s5pv210-fascinate4g.dtb \ + s5pv210-galaxys.dtb \ + s5pv210-goni.dtb \ + s5pv210-smdkc110.dtb \ + s5pv210-smdkv210.dtb \ + s5pv210-torbreck.dtb diff --git a/arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi new file mode 100644 index 000000000000..597ade3e252f --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd + */ + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mfc_left: region-mfc-left { + compatible = "shared-dma-pool"; + no-map; + size = <0x2400000>; + alignment = <0x100000>; + }; + + mfc_right: region-mfc-right { + compatible = "shared-dma-pool"; + no-map; + size = <0x800000>; + alignment = <0x100000>; + }; + }; +}; + +&mfc { + memory-region = <&mfc_left>, <&mfc_right>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos-pinctrl.h b/arch/arm/boot/dts/samsung/exynos-pinctrl.h new file mode 100644 index 000000000000..e3a6df95281c --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos-pinctrl.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski + */ + +#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +#define EXYNOS4_PIN_DRV_LV1 0 +#define EXYNOS4_PIN_DRV_LV2 2 +#define EXYNOS4_PIN_DRV_LV3 1 +#define EXYNOS4_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5260 */ +#define EXYNOS5260_PIN_DRV_LV1 0 +#define EXYNOS5260_PIN_DRV_LV2 1 +#define EXYNOS5260_PIN_DRV_LV4 2 +#define EXYNOS5260_PIN_DRV_LV6 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi new file mode 100644 index 000000000000..bc9a78f6d4b7 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. + */ + +&pmu_system_controller { + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330c>; /* PS_HOLD_CONTROL */ + mask = <0x5200>; /* reset value */ + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; /* SWRESET */ + mask = <0x1>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts new file mode 100644 index 000000000000..660cc7fac4db --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's ARTIK5 evaluation board + * which is based on Samsung Exynos3250 SoC. + */ + +/dts-v1/; +#include "exynos3250-artik5.dtsi" + +/ { + model = "Samsung ARTIK5 evaluation board"; + compatible = "samsung,artik5-eval", "samsung,artik5", + "samsung,exynos3250", "samsung,exynos3"; + + aliases { + mmc0 = &mshc_2; + }; +}; + +&mshc_2 { + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&ldo3_reg>; + card-detect-delay = <200>; + clock-frequency = <100000000>; + max-frequency = <100000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&spi_0 { + status = "okay"; + cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; + + assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ + <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ + <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ + + ethernet@0 { + compatible = "asix,ax88796c"; + reg = <0x0>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */ + interrupt-parent = <&gpx2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <40000000>; + reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; + + controller-data { + samsung,spi-feedback-delay = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi b/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi new file mode 100644 index 000000000000..3fdd922e635c --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos3250 based ARTIK5 module device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's ARTIK5 module which is based on + * Samsung Exynos3250 SoC. + */ + +#include "exynos3250.dtsi" +#include +#include +#include + +/ { + compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; + + aliases { + mmc0 = &mshc_0; + mmc1 = &mshc_1; + }; + + chosen { + stdout-path = &serial_2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x1f800000>; + }; + + firmware@205f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0205f000 0x1000>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 500MHz */ + cooling-device = <&cpu0 5 5>, + <&cpu1 5 5>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 8 8>, + <&cpu1 8 8>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo7_reg>; + assigned-clocks = <&cmu CLK_SCLK_TSADC>; + assigned-clock-rates = <6000000>; +}; + +&cmu { + clocks = <&xusbxti>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps14-pmic"; + interrupt-parent = <&gpx3>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps14_irq>; + reg = <0x66>; + + s2mps14_osc: clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", + "s2mps14_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + /* VDD_ALIVE15x */ + regulator-name = "VLDO1_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + /* VDDQM176 ~ VDDQM185 */ + regulator-name = "VLDO2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + /* + * VDD1_E106 ~ VDD1_E111 + * DVDD_RTC_AP, DVDD_MMC2_AP + */ + regulator-name = "VLDO3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + /* AVDD_PLL1120 ~ AVDD_PLL11201 */ + regulator-name = "VLDO4_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */ + regulator-name = "VLDO5_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* VDD_USB, VDD10_HSIC */ + regulator-name = "VLDO6_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + /* + * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2, + * AVDD_ADC, AVDD_ABB_0, M4S_VDD18 + */ + regulator-name = "VLDO7_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + /* AVDD33_UOTG */ + regulator-name = "VLDO8_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + /* VDDQ_E86 ~ VDDQ_E105*/ + regulator-name = "VLDO9_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VLDO10_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo11_reg: LDO11 { + /* VDD74 ~ VDD75 */ + regulator-name = "VLDO11_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo12_reg: LDO12 { + /* VDD72 ~ VDD73 */ + regulator-name = "VLDO12_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VLDO13_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VLDO14_2.7V"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VLDO_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VLDO16_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VLDO17_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo18_reg: LDO18 { + /* DVDD_MMC2_AP */ + regulator-name = "VLDO18_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VLDO19_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "VLDO20_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "VLDO21_1.25V"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + ldo22_reg: LDO22 { + regulator-name = "VLDO22_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo23_reg: LDO23 { + /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */ + regulator-name = "VLDO23_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "VLDO24_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "VLDO25_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: BUCK1 { + /* VDD_MIF */ + regulator-name = "VBUCK1_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + /* VDD_CPU */ + regulator-name = "VBUCK2_1.2V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + /* VDD_G3D */ + regulator-name = "VBUCK3_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VBUCK4_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "VBUCK5_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&mshc_0 { + non-removable; + cap-mmc-highspeed; + card-detect-delay = <200>; + vmmc-supply = <&ldo12_reg>; + clock-frequency = <100000000>; + max-frequency = <100000000>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + status = "okay"; +}; + +&mshc_1 { + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + non-removable; + keep-power-in-suspend; + fifo-depth = <0x40>; + vqmmc-supply = <&ldo11_reg>; + /* + * Voltage negotiation is broken for the SDIO periph so we + * can't actually set the voltage here. + * vmmc-supply = <&ldo23_reg>; + */ + card-detect-delay = <500>; + clock-frequency = <100000000>; + max-frequency = <100000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>; + bus-width = <4>; + status = "okay"; +}; + +&pinctrl_1 { + bten: bten-pins { + samsung,pins = "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + wlanen: wlanen-pins { + samsung,pins = "gpx2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <1>; + }; + + s2mps14_irq: s2mps14-irq-pins { + samsung,pins = "gpx3-5"; + samsung,pin-pud = ; + }; + + bthostwake: bthostwake-pins { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + btwake: btwake-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&rtc { + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&serial_0 { + assigned-clocks = <&cmu CLK_SCLK_UART0>; + assigned-clock-rates = <100000000>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bten &btwake &bthostwake>; + max-speed = <3000000>; + shutdown-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx3 6 GPIO_ACTIVE_HIGH>; + clocks = <&s2mps14_osc S2MPS11_CLK_BT>; + }; +}; + +&tmu { + status = "okay"; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos3250-monk.dts b/arch/arm/boot/dts/samsung/exynos3250-monk.dts new file mode 100644 index 000000000000..2de877d4ccc5 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos3250-monk.dts @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos3250 based Monk board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Monk board which is based on + * Samsung Exynos3250 SoC. + */ + +/dts-v1/; +#include "exynos3250.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include +#include +#include + +/ { + model = "Samsung Monk board"; + compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; + + aliases { + i2c7 = &i2c_max77836; + mmc0 = &mshc_0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x1ff00000>; + }; + + firmware@205f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0205f000 0x1000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power key"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + vemmc_reg: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_EMMC_2.8V-fixed"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + i2c_max77836: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + max77836: pmic@25 { + compatible = "maxim,max77836"; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_NONE>; + reg = <0x25>; + wakeup-source; + + extcon { + compatible = "maxim,max77836-muic"; + }; + + regulators { + compatible = "maxim,max77836-regulator"; + safeout_reg: SAFEOUT { + regulator-name = "SAFEOUT"; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <45000>; + regulator-max-microamp = <475000>; + regulator-boot-on; + }; + + motor_reg: LDO1 { + regulator-name = "MOT_2.7V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2700000>; + }; + + LDO2 { + regulator-name = "UNUSED_LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + }; + + charger { + compatible = "maxim,max77836-charger"; + + maxim,constant-uvolt = <4350000>; + maxim,fast-charge-uamp = <225000>; + maxim,eoc-uamp = <7500>; + maxim,ovp-uvolt = <6500000>; + }; + }; + }; + + haptics { + compatible = "regulator-haptic"; + haptic-supply = <&motor_reg>; + min-microvolt = <1100000>; + max-microvolt = <2700000>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Correspond to 500MHz at freq_table */ + cooling-device = <&cpu0 5 5>, + <&cpu1 5 5>; + }; + map1 { + /* Correspond to 200MHz at freq_table */ + cooling-device = <&cpu0 8 8>, + <&cpu1 8 8>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; + assigned-clocks = <&cmu CLK_SCLK_TSADC>; + assigned-clock-rates = <6000000>; + + thermistor-ap { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 0>; + }; + + thermistor-battery { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 1>; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&cmu { + clocks = <&xusbxti>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&exynos_usbphy { + vbus-supply = <&safeout_reg>; + status = "okay"; +}; + +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps14-pmic"; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + reg = <0x66>; + wakeup-source; + + s2mps14_osc: clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", + "s2mps14_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VAP_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VAP_M1_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_AP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VAP_AVDD_PLL1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VAP_PLL_ISO_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VAP_MIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VAP_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "VAP_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "V_LPDDR_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "UNUSED_LDO10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo11_reg: LDO11 { + regulator-name = "V_EMMC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo12_reg: LDO12 { + regulator-name = "V_EMMC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VSENSOR_2.85V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "UNUSED_LDO14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "LCD_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "UNUSED_LDO17"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "UNUSED_LDO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "LCD_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "UNUSED_LDO21"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo22_reg: LDO22 { + regulator-name = "UNUSED_LDO22"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "UNUSED_LDO23"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "UNUSED_LDO24"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "UNUSED_LDO25"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VAP_MIF_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VAP_ARM_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VAP_INT3D_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VCC_SUB_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max77836-battery"; + interrupt-parent = <&gpx1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reg = <0x36>; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&mshc_0 { + #address-cells = <1>; + #size-cells = <0>; + broken-cd; + non-removable; + cap-mmc-highspeed; + mmc-hs200-1_8v; + card-detect-delay = <200>; + vmmc-supply = <&vemmc_reg>; + clock-frequency = <100000000>; + max-frequency = <100000000>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + status = "okay"; +}; + +&serial_0 { + assigned-clocks = <&cmu CLK_SCLK_UART0>; + assigned-clock-rates = <100000000>; + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&rtc { + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, DOWN); + PIN_SLP(gpa0-1, INPUT, DOWN); + PIN_SLP(gpa0-2, INPUT, DOWN); + PIN_SLP(gpa0-3, INPUT, DOWN); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, DOWN); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, PREV, NONE); + PIN_SLP(gpb-1, PREV, NONE); + PIN_SLP(gpb-2, PREV, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&initial1 &sleep1>; + + initial1: initial-state { + PIN_IN(gpk2-0, DOWN, LV1); + PIN_IN(gpk2-1, DOWN, LV1); + PIN_IN(gpk2-2, DOWN, LV1); + PIN_IN(gpk2-3, DOWN, LV1); + PIN_IN(gpk2-4, DOWN, LV1); + PIN_IN(gpk2-5, DOWN, LV1); + PIN_IN(gpk2-6, DOWN, LV1); + }; + + sleep1: sleep-state { + PIN_SLP(gpe0-0, PREV, NONE); + PIN_SLP(gpe0-1, PREV, NONE); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, PREV, NONE); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, PREV, NONE); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, INPUT, DOWN); + PIN_SLP(gpe1-4, INPUT, DOWN); + PIN_SLP(gpe1-5, INPUT, DOWN); + PIN_SLP(gpe1-6, INPUT, DOWN); + PIN_SLP(gpe1-7, INPUT, NONE); + + PIN_SLP(gpe2-0, INPUT, NONE); + PIN_SLP(gpe2-1, INPUT, NONE); + PIN_SLP(gpe2-2, INPUT, NONE); + + PIN_SLP(gpk0-0, INPUT, DOWN); + PIN_SLP(gpk0-1, INPUT, DOWN); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, INPUT, DOWN); + PIN_SLP(gpk0-4, INPUT, DOWN); + PIN_SLP(gpk0-5, INPUT, DOWN); + PIN_SLP(gpk0-6, INPUT, DOWN); + PIN_SLP(gpk0-7, INPUT, DOWN); + + PIN_SLP(gpk1-0, PREV, NONE); + PIN_SLP(gpk1-1, PREV, NONE); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, DOWN); + PIN_SLP(gpm1-3, INPUT, DOWN); + PIN_SLP(gpm1-4, INPUT, DOWN); + PIN_SLP(gpm1-5, INPUT, DOWN); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, DOWN); + PIN_SLP(gpm2-1, INPUT, DOWN); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, INPUT, DOWN); + PIN_SLP(gpm3-1, INPUT, DOWN); + PIN_SLP(gpm3-2, INPUT, DOWN); + PIN_SLP(gpm3-3, INPUT, DOWN); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi new file mode 100644 index 000000000000..07828551d4b3 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include "exynos-pinctrl.h" + +#define PIN_IN(_pin, _pull, _drv) \ + pin- ## _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = ; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ + } + +#define PIN_SLP(_pin, _mode, _pull) \ + pin- ## _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ + } + +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpd0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + mipi0_clk: mipi0-clk-pins { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs: sd0-rdqs-pins { + samsung,pins = "gpk0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpk1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpk1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpk1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpk1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpk2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpk2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpk2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpk2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_io: cam-port-b-io-pins { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_active: cam-port-b-clk-active-pins { + samsung,pins = "gpm2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { + samsung,pins = "gpm2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_i2c0: fimc-is-i2c0-pins { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_i2c1: fimc-is-i2c1-pins { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_uart: fimc-is-uart-pins { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos3250-rinato.dts b/arch/arm/boot/dts/samsung/exynos3250-rinato.dts new file mode 100644 index 000000000000..88fb3e68ff02 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos3250-rinato.dts @@ -0,0 +1,921 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos3250 based Rinato board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Rinato board which is based on + * Samsung Exynos3250 SoC. + */ + +/dts-v1/; +#include "exynos3250.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include +#include +#include + +/ { + model = "Samsung Rinato board"; + compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; + chassis-type = "watch"; + + aliases { + i2c7 = &i2c_max77836; + mmc0 = &mshc_0; + mmc1 = &mshc_1; + }; + + chosen { + stdout-path = &serial_1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x1ff00000>; + }; + + firmware@205f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0205f000 0x1000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power key"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + wlan_pwrseq: mshc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; + }; + + i2c_max77836: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + max77836: pmic@25 { + compatible = "maxim,max77836"; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_NONE>; + reg = <0x25>; + wakeup-source; + + extcon { + compatible = "maxim,max77836-muic"; + }; + + regulators { + compatible = "maxim,max77836-regulator"; + safeout_reg: SAFEOUT { + regulator-name = "SAFEOUT"; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <45000>; + regulator-max-microamp = <475000>; + regulator-boot-on; + }; + + motor_reg: LDO1 { + regulator-name = "MOT_2.7V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2700000>; + }; + + LDO2 { + regulator-name = "UNUSED_LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + }; + + charger { + compatible = "maxim,max77836-charger"; + + maxim,constant-uvolt = <4350000>; + maxim,fast-charge-uamp = <225000>; + maxim,eoc-uamp = <7500>; + maxim,ovp-uvolt = <6500000>; + }; + }; + }; + + haptics { + compatible = "regulator-haptic"; + haptic-supply = <&motor_reg>; + min-microvolt = <1100000>; + max-microvolt = <2700000>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 500MHz */ + cooling-device = <&cpu0 5 5>, + <&cpu1 5 5>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 8 8>, + <&cpu1 8 8>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; + assigned-clocks = <&cmu CLK_SCLK_TSADC>; + assigned-clock-rates = <6000000>; + + thermistor-ap { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 0>; + }; + + thermistor-battery { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 1>; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_lcd0 { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mcuisp { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_isp { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peril { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cmu { + clocks = <&xusbxti>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&exynos_usbphy { + status = "okay"; + vbus-supply = <&safeout_reg>; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&dsi_0 { + vddcore-supply = <&ldo6_reg>; + vddio-supply = <&ldo6_reg>; + samsung,burst-clock-frequency = <250000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e63j0x03"; + reg = <0>; + vdd3-supply = <&ldo16_reg>; + vci-supply = <&ldo20_reg>; + reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; + te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&fimd { + status = "okay"; + + i80-if-timings { + cs-setup = <0>; + wr-setup = <0>; + wr-active = <1>; + wr-hold = <0>; + }; +}; + +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps14-pmic"; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + reg = <0x66>; + wakeup-source; + + s2mps14_osc: clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", + "s2mps14_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VAP_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo2_reg: LDO2 { + regulator-name = "VAP_M1_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_AP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VAP_AVDD_PLL1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VAP_PLL_ISO_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "VAP_VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VAP_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VAP_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "V_LPDDR_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "UNUSED_LDO10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "V_EMMC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo12_reg: LDO12 { + regulator-name = "V_EMMC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo13_reg: LDO13 { + regulator-name = "CAM_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "UNUSED_LDO14"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "LCD_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "V_IRLED_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo18_reg: LDO18 { + regulator-name = "CAM_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "LCD_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "CAM_DVDD_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "HRM_VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "HRM_VCC_3.3V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "UNUSED_LDO25"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "VAP_MIF_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VAP_ARM_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VAP_INT3D_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VCC_SUB_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max77836-battery"; + interrupt-parent = <&gpx1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reg = <0x36>; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&jpeg { + status = "okay"; +}; + +&mshc_0 { + broken-cd; + non-removable; + cap-mmc-highspeed; + mmc-hs200-1_8v; + card-detect-delay = <200>; + vmmc-supply = <&ldo12_reg>; + clock-frequency = <100000000>; + max-frequency = <100000000>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + status = "okay"; +}; + +&mshc_1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + assigned-clocks = <&cmu CLK_SCLK_UART0>; + assigned-clock-rates = <100000000>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&s2mps14_osc S2MPS11_CLK_BT>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&rtc { + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&initial0 &sleep0>; + + initial0: initial-state { + PIN_IN(gpa1-4, DOWN, LV1); + PIN_IN(gpa1-5, DOWN, LV1); + + PIN_IN(gpc0-0, DOWN, LV1); + PIN_IN(gpc0-1, DOWN, LV1); + PIN_IN(gpc0-2, DOWN, LV1); + PIN_IN(gpc0-3, DOWN, LV1); + PIN_IN(gpc0-4, DOWN, LV1); + + PIN_IN(gpd0-0, DOWN, LV1); + PIN_IN(gpd0-1, DOWN, LV1); + }; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, DOWN); + PIN_SLP(gpa0-1, INPUT, DOWN); + PIN_SLP(gpa0-2, INPUT, DOWN); + PIN_SLP(gpa0-3, INPUT, DOWN); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, DOWN); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, PREV, NONE); + PIN_SLP(gpb-1, PREV, NONE); + PIN_SLP(gpb-2, PREV, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&initial1 &sleep1>; + + initial1: initial-state { + PIN_IN(gpe0-6, DOWN, LV1); + PIN_IN(gpe0-7, DOWN, LV1); + + PIN_IN(gpe1-0, DOWN, LV1); + PIN_IN(gpe1-3, DOWN, LV1); + PIN_IN(gpe1-4, DOWN, LV1); + PIN_IN(gpe1-5, DOWN, LV1); + PIN_IN(gpe1-6, DOWN, LV1); + + PIN_IN(gpk2-0, DOWN, LV1); + PIN_IN(gpk2-1, DOWN, LV1); + PIN_IN(gpk2-2, DOWN, LV1); + PIN_IN(gpk2-3, DOWN, LV1); + PIN_IN(gpk2-4, DOWN, LV1); + PIN_IN(gpk2-5, DOWN, LV1); + PIN_IN(gpk2-6, DOWN, LV1); + + PIN_IN(gpm0-0, DOWN, LV1); + PIN_IN(gpm0-1, DOWN, LV1); + PIN_IN(gpm0-2, DOWN, LV1); + PIN_IN(gpm0-3, DOWN, LV1); + PIN_IN(gpm0-4, DOWN, LV1); + PIN_IN(gpm0-5, DOWN, LV1); + PIN_IN(gpm0-6, DOWN, LV1); + PIN_IN(gpm0-7, DOWN, LV1); + + PIN_IN(gpm1-0, DOWN, LV1); + PIN_IN(gpm1-1, DOWN, LV1); + PIN_IN(gpm1-2, DOWN, LV1); + PIN_IN(gpm1-3, DOWN, LV1); + PIN_IN(gpm1-4, DOWN, LV1); + PIN_IN(gpm1-5, DOWN, LV1); + PIN_IN(gpm1-6, DOWN, LV1); + + PIN_IN(gpm2-0, DOWN, LV1); + PIN_IN(gpm2-1, DOWN, LV1); + + PIN_IN(gpm3-0, DOWN, LV1); + PIN_IN(gpm3-1, DOWN, LV1); + PIN_IN(gpm3-2, DOWN, LV1); + PIN_IN(gpm3-3, DOWN, LV1); + PIN_IN(gpm3-4, DOWN, LV1); + + PIN_IN(gpm4-1, DOWN, LV1); + PIN_IN(gpm4-2, DOWN, LV1); + PIN_IN(gpm4-3, DOWN, LV1); + PIN_IN(gpm4-4, DOWN, LV1); + PIN_IN(gpm4-5, DOWN, LV1); + PIN_IN(gpm4-6, DOWN, LV1); + PIN_IN(gpm4-7, DOWN, LV1); + }; + + sleep1: sleep-state { + PIN_SLP(gpe0-0, PREV, NONE); + PIN_SLP(gpe0-1, PREV, NONE); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, UP); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, PREV, NONE); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, INPUT, DOWN); + PIN_SLP(gpe1-4, INPUT, DOWN); + PIN_SLP(gpe1-5, INPUT, DOWN); + PIN_SLP(gpe1-6, INPUT, DOWN); + PIN_SLP(gpe1-7, INPUT, NONE); + + PIN_SLP(gpe2-0, INPUT, NONE); + PIN_SLP(gpe2-1, INPUT, NONE); + PIN_SLP(gpe2-2, INPUT, NONE); + + PIN_SLP(gpk0-0, INPUT, DOWN); + PIN_SLP(gpk0-1, INPUT, DOWN); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, INPUT, DOWN); + PIN_SLP(gpk0-4, INPUT, DOWN); + PIN_SLP(gpk0-5, INPUT, DOWN); + PIN_SLP(gpk0-6, INPUT, DOWN); + PIN_SLP(gpk0-7, INPUT, DOWN); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, INPUT, DOWN); + PIN_SLP(gpk1-4, INPUT, DOWN); + PIN_SLP(gpk1-5, INPUT, DOWN); + PIN_SLP(gpk1-6, INPUT, DOWN); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, DOWN); + PIN_SLP(gpm1-3, INPUT, DOWN); + PIN_SLP(gpm1-4, INPUT, DOWN); + PIN_SLP(gpm1-5, INPUT, DOWN); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, DOWN); + PIN_SLP(gpm2-1, INPUT, DOWN); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, INPUT, DOWN); + PIN_SLP(gpm3-1, INPUT, DOWN); + PIN_SLP(gpm3-2, INPUT, DOWN); + PIN_SLP(gpm3-3, INPUT, DOWN); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos3250.dtsi b/arch/arm/boot/dts/samsung/exynos3250.dtsi new file mode 100644 index 000000000000..3f1015edab43 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos3250.dtsi @@ -0,0 +1,950 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos3250 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4-cpu-thermal.dtsi" +#include +#include +#include + +/ { + compatible = "samsung,exynos3250"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + spi0 = &spi_0; + spi1 = &spi_1; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_isp: bus-isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + + bus_isp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + }; + + bus_lcd0: bus-lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus-mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + + bus_mcuisp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peril: bus-peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + + bus_peril_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cmu CLK_ARM_CLK>; + clock-names = "cpu"; + #cooling-cells = <2>; + + operating-points = < + 1000000 1150000 + 900000 1112500 + 800000 1075000 + 700000 1037500 + 600000 1000000 + 500000 962500 + 400000 925000 + 300000 887500 + 200000 850000 + 100000 850000 + >; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + clocks = <&cmu CLK_ARM_CLK>; + clock-names = "cpu"; + #cooling-cells = <2>; + + operating-points = < + 1000000 1150000 + 900000 1112500 + 800000 1075000 + 700000 1037500 + 600000 1000000 + 500000 962500 + 400000 925000 + 300000 887500 + 200000 850000 + 100000 850000 + >; + }; + }; + + xusbxti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; + + xxti: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; + + xtcxo: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xtcxo"; + }; + + bus_leftbus_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@3f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x3f000 0x1000>; + }; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sys_reg: syscon@10010000 { + compatible = "samsung,exynos3-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon"; + reg = <0x10020000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + clock-names = "clkout8"; + clocks = <&cmu CLK_FIN_PLL>; + #clock-cells = <1>; + + mipi_phy: mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; + }; + + pd_cam: power-domain@10023c00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c00 0x20>; + #power-domain-cells = <0>; + label = "CAM"; + }; + + pd_mfc: power-domain@10023c40 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c40 0x20>; + #power-domain-cells = <0>; + label = "MFC"; + }; + + pd_g3d: power-domain@10023c60 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c60 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; + + pd_lcd0: power-domain@10023c80 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c80 0x20>; + #power-domain-cells = <0>; + label = "LCD0"; + }; + + pd_isp: power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023ca0 0x20>; + #power-domain-cells = <0>; + label = "ISP"; + }; + + cmu: clock-controller@10030000 { + compatible = "samsung,exynos3250-cmu"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, + <&cmu CLK_MOUT_ACLK_266_SUB>; + assigned-clock-parents = <&cmu CLK_FIN_PLL>, + <&cmu CLK_FIN_PLL>; + }; + + cmu_dmc: clock-controller@105c0000 { + compatible = "samsung,exynos3250-cmu-dmc"; + reg = <0x105c0000 0x2000>; + #clock-cells = <1>; + }; + + rtc: rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = , + ; + interrupt-parent = <&pmu_system_controller>; + status = "disabled"; + }; + + tmu: tmu@100c0000 { + compatible = "samsung,exynos3250-tmu"; + reg = <0x100c0000 0x100>; + interrupts = ; + clocks = <&cmu CLK_TMU_APBIF>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = ; + }; + + timer@10050000 { + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos3250-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupts = ; + }; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos3250-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + }; + + jpeg: codec@11830000 { + compatible = "samsung,exynos3250-jpeg"; + reg = <0x11830000 0x1000>; + interrupts = ; + clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; + clock-names = "jpeg", "sclk"; + power-domains = <&pd_cam>; + assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; + assigned-clock-rates = <0>, <150000000>; + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; + iommus = <&sysmmu_jpeg>; + status = "disabled"; + }; + + sysmmu_jpeg: sysmmu@11a60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a60000 0x1000>; + interrupts = ; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + fimd: fimd@11c00000 { + compatible = "samsung,exynos3250-fimd"; + reg = <0x11c00000 0x30000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = , + , + ; + clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; + clock-names = "sclk_fimd", "fimd"; + power-domains = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + dsi_0: dsi@11c80000 { + compatible = "samsung,exynos3250-mipi-dsi"; + reg = <0x11c80000 0x10000>; + interrupts = ; + samsung,phy-type = <0>; + power-domains = <&pd_lcd0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; + clock-names = "bus_clk", "pll_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sysmmu_fimd0: sysmmu@11e20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11e20000 0x1000>; + interrupts = ; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + + hsotg: usb@12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = ; + clocks = <&cmu CLK_USBOTG>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + mshc_0: mmc@12510000 { + compatible = "samsung,exynos5420-dw-mshc"; + reg = <0x12510000 0x1000>; + interrupts = ; + clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_1: mmc@12520000 { + compatible = "samsung,exynos5420-dw-mshc"; + reg = <0x12520000 0x1000>; + interrupts = ; + clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_2: mmc@12530000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12530000 0x1000>; + interrupts = ; + clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + exynos_usbphy: usb-phy@125b0000 { + compatible = "samsung,exynos3250-usb2-phy"; + reg = <0x125b0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + pdma0: dma-controller@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = ; + clocks = <&cmu CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = ; + clocks = <&cmu CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + adc: adc@126c0000 { + compatible = "samsung,exynos3250-adc"; + reg = <0x126c0000 0x100>; + interrupts = ; + clock-names = "adc", "sclk"; + clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; + #io-channel-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + clocks = <&cmu CLK_G3D>, + <&cmu CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + /* TODO: operating points for DVFS, assigned clock as 134 MHz */ + }; + + mfc: codec@13400000 { + compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7"; + reg = <0x13400000 0x10000>; + interrupts = ; + clock-names = "mfc", "sclk_mfc"; + clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; + power-domains = <&pd_mfc>; + iommus = <&sysmmu_mfc>; + }; + + sysmmu_mfc: sysmmu@13620000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13620000 0x1000>; + interrupts = ; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = ; + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data &uart0_fctl>; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = ; + clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>; + status = "disabled"; + }; + + serial_2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + status = "disabled"; + }; + + i2c_0: i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; + + i2c_4: i2c@138a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138a0000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c@138b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138b0000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c@138c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138c0000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c@138d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138d0000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = ; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = ; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + i2s2: i2s@13970000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0x13970000 0x100>; + interrupts = ; + clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0"; + dmas = <&pdma0 14>, <&pdma0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2s2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + pwm: pwm@139d0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139d0000 0x1000>; + interrupts = , + , + , + , + ; + #pwm-cells = <3>; + status = "disabled"; + }; + + ppmu_dmc0: ppmu@106a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106a0000 0x2000>; + status = "disabled"; + }; + + ppmu_dmc1: ppmu@106b0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106b0000 0x2000>; + status = "disabled"; + }; + + ppmu_cpu: ppmu@106c0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106c0000 0x2000>; + status = "disabled"; + }; + + ppmu_rightbus: ppmu@112a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x112a0000 0x2000>; + clocks = <&cmu CLK_PPMURIGHT>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_leftbus: ppmu@116a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x116a0000 0x2000>; + clocks = <&cmu CLK_PPMULEFT>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_camif: ppmu@11ac0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x11ac0000 0x2000>; + clocks = <&cmu CLK_PPMUCAMIF>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_lcd0: ppmu@11e40000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x11e40000 0x2000>; + clocks = <&cmu CLK_PPMULCD0>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_fsys: ppmu@12630000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12630000 0x2000>; + clocks = <&cmu CLK_PPMUFILE>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_g3d: ppmu@13220000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13220000 0x2000>; + clocks = <&cmu CLK_PPMUG3D>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_mfc: ppmu@13660000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13660000 0x2000>; + clocks = <&cmu CLK_PPMUMFC_L>; + clock-names = "ppmu"; + status = "disabled"; + }; + }; +}; + +#include "exynos3250-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi new file mode 100644 index 000000000000..27a1a8952665 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree sources for Exynos4 thermal zone + * + * Copyright (c) 2014 Lukasz Majewski + */ + +#include + +/ { +thermal-zones { + cpu_thermal: cpu-thermal { + thermal-sensors = <&tmu>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + cpu_alert0: cpu-alert-0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu_alert1: cpu-alert-1 { + temperature = <95000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + }; + map1 { + trip = <&cpu_alert1>; + }; + }; + }; +}; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4.dtsi b/arch/arm/boot/dts/samsung/exynos4.dtsi new file mode 100644 index 000000000000..f775b9377a38 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4.dtsi @@ -0,0 +1,1007 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4 SoC series common device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular + * SoCs from Exynos4 series can include this file and provide values for SoCs + * specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional + * nodes can be added to this file. + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + i2c8 = &i2c_8; + csis0 = &csis_0; + csis1 = &csis_1; + fimc0 = &fimc_0; + fimc1 = &fimc_1; + fimc2 = &fimc_2; + fimc3 = &fimc_3; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + serial3 = &serial_3; + }; + + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + status = "disabled"; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock_audss: clock-controller@3810000 { + compatible = "samsung,exynos4210-audss-clock"; + reg = <0x03810000 0x0c>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_AUDIO0>, + <&clock CLK_SCLK_AUDIO0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", + "sclk_pcm_in"; + }; + + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx", "tx-sec"; + samsung,idma-addr = <0x03000000>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + scu: snoop-control-unit@10500000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x10500000 0x2000>; + }; + + memory-controller@12570000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12570000 0x14>; + }; + + pd_mfc: power-domain@10023c40 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c40 0x20>; + #power-domain-cells = <0>; + label = "MFC"; + }; + + pd_g3d: power-domain@10023c60 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c60 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; + + pd_lcd0: power-domain@10023c80 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c80 0x20>; + #power-domain-cells = <0>; + label = "LCD0"; + }; + + pd_tv: power-domain@10023c20 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c20 0x20>; + #power-domain-cells = <0>; + power-domains = <&pd_lcd0>; + label = "TV"; + }; + + pd_cam: power-domain@10023c00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023c00 0x20>; + #power-domain-cells = <0>; + label = "CAM"; + }; + + pd_gps: power-domain@10023ce0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023ce0 0x20>; + #power-domain-cells = <0>; + label = "GPS"; + }; + + pd_gps_alive: power-domain@10023d00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023d00 0x20>; + #power-domain-cells = <0>; + label = "GPS alive"; + }; + + gic: interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x10000>, <0x10480000 0x10000>; + }; + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + }; + + sys_reg: syscon@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4210-pmu", "simple-mfd", "syscon"; + reg = <0x10020000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + + mipi_phy: mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; + }; + + dsi_0: dsi@11c80000 { + compatible = "samsung,exynos4210-mipi-dsi"; + reg = <0x11c80000 0x10000>; + interrupts = ; + power-domains = <&pd_lcd0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; + clock-names = "bus_clk", "sclk_mipi"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + camera: camera@11800000 { + compatible = "samsung,fimc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + clock-output-names = "cam_a_clkout", "cam_b_clkout"; + ranges; + + fimc_0: fimc@11800000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc0>; + status = "disabled"; + }; + + fimc_1: fimc@11810000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11810000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc1>; + status = "disabled"; + }; + + fimc_2: fimc@11820000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11820000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc2>; + status = "disabled"; + }; + + fimc_3: fimc@11830000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11830000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc3>; + status = "disabled"; + }; + + csis_0: csis@11880000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11880000 0x4000>; + interrupts = ; + clocks = <&clock CLK_CSIS0>, + <&clock CLK_SCLK_CSIS0>; + clock-names = "csis", "sclk_csis"; + bus-width = <4>; + power-domains = <&pd_cam>; + phys = <&mipi_phy 0>; + phy-names = "csis"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csis_1: csis@11890000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11890000 0x4000>; + interrupts = ; + clocks = <&clock CLK_CSIS1>, + <&clock CLK_SCLK_CSIS1>; + clock-names = "csis", "sclk_csis"; + bus-width = <2>; + power-domains = <&pd_cam>; + phys = <&mipi_phy 2>; + phy-names = "csis"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rtc: rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupt-parent = <&pmu_system_controller>; + interrupts = , + ; + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + status = "disabled"; + }; + + keypad: keypad@100a0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100a0000 0x100>; + interrupts = ; + clocks = <&clock CLK_KEYIF>; + clock-names = "keypad"; + status = "disabled"; + }; + + sdhci_0: mmc@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "hsmmc", "mmc_busclk.2"; + status = "disabled"; + }; + + sdhci_1: mmc@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "hsmmc", "mmc_busclk.2"; + status = "disabled"; + }; + + sdhci_2: mmc@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "hsmmc", "mmc_busclk.2"; + status = "disabled"; + }; + + sdhci_3: mmc@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; + clock-names = "hsmmc", "mmc_busclk.2"; + status = "disabled"; + }; + + exynos_usbphy: usb-phy@125b0000 { + compatible = "samsung,exynos4210-usb2-phy"; + reg = <0x125b0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + hsotg: usb@12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = ; + clocks = <&clock CLK_USB_DEVICE>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + ehci: usb@12580000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12580000 0x100>; + interrupts = ; + clocks = <&clock CLK_USB_HOST>; + clock-names = "usbhost"; + status = "disabled"; + phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>; + phy-names = "host", "hsic0", "hsic1"; + }; + + ohci: usb@12590000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12590000 0x100>; + interrupts = ; + clocks = <&clock CLK_USB_HOST>; + clock-names = "usbhost"; + status = "disabled"; + phys = <&exynos_usbphy 1>; + phy-names = "host"; + }; + + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + /* + * CLK_G3D is not actually bus clock but a IP-level clock. + * The bus clock is not described in hardware manual. + */ + clocks = <&clock CLK_G3D>, + <&clock CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + }; + + i2s1: i2s@13960000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0x13960000 0x100>; + clocks = <&clock CLK_I2S1>; + clock-names = "iis"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk1"; + dmas = <&pdma1 12>, <&pdma1 11>; + dma-names = "tx", "rx"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + i2s2: i2s@13970000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0x13970000 0x100>; + clocks = <&clock CLK_I2S2>; + clock-names = "iis"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk2"; + dmas = <&pdma0 14>, <&pdma0 13>; + dma-names = "tx", "rx"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + mfc: codec@13400000 { + compatible = "samsung,mfc-v5"; + reg = <0x13400000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; + clock-names = "mfc", "sclk_mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + serial_2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 17>, <&pdma0 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + serial_3: serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c_0: i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; + + i2c_4: i2c@138a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138a0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c@138b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138b0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c@138c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138c0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c@138d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138d0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + i2c_8: i2c@138e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-hdmiphy-i2c"; + reg = <0x138e0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C_HDMI>; + clock-names = "i2c"; + status = "disabled"; + + hdmi_i2c_phy: hdmi-phy@38 { + compatible = "samsung,exynos4210-hdmiphy"; + reg = <0x38>; + }; + }; + + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = ; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = ; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = ; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + pwm: pwm@139d0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139d0000 0x1000>; + interrupts = , + , + , + , + ; + clocks = <&clock CLK_PWM>; + clock-names = "timers"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pdma0: dma-controller@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + mdma1: dma-controller@12850000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12850000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + fimd: fimd@11c00000 { + compatible = "samsung,exynos4210-fimd"; + interrupt-parent = <&combiner>; + reg = <0x11c00000 0x20000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <11 0>, <11 1>, <11 2>; + clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; + clock-names = "sclk_fimd", "fimd"; + power-domains = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + tmu: tmu@100c0000 { + interrupt-parent = <&combiner>; + reg = <0x100c0000 0x100>; + interrupts = <2 4>; + status = "disabled"; + #thermal-sensor-cells = <0>; + }; + + jpeg_codec: jpeg-codec@11840000 { + compatible = "samsung,exynos4210-jpeg"; + reg = <0x11840000 0x1000>; + interrupts = ; + clocks = <&clock CLK_JPEG>; + clock-names = "jpeg"; + power-domains = <&pd_cam>; + iommus = <&sysmmu_jpeg>; + }; + + rotator: rotator@12810000 { + compatible = "samsung,exynos4210-rotator"; + reg = <0x12810000 0x64>; + interrupts = ; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; + + hdmi: hdmi@12d00000 { + compatible = "samsung,exynos4210-hdmi"; + reg = <0x12d00000 0x70000>; + interrupts = ; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_SCLK_PIXEL>, + <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + phy = <&hdmi_i2c_phy>; + power-domains = <&pd_tv>; + samsung,syscon-phandle = <&pmu_system_controller>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hdmicec: cec@100b0000 { + compatible = "samsung,s5p-cec"; + reg = <0x100b0000 0x200>; + interrupts = ; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; + + mixer: mixer@12c10000 { + compatible = "samsung,exynos4210-mixer"; + interrupts = ; + reg = <0x12c10000 0x2100>, <0x12c00000 0x300>; + power-domains = <&pd_tv>; + iommus = <&sysmmu_tv>; + status = "disabled"; + }; + + ppmu_dmc0: ppmu@106a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106a0000 0x2000>; + clocks = <&clock CLK_PPMUDMC0>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_dmc1: ppmu@106b0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106b0000 0x2000>; + clocks = <&clock CLK_PPMUDMC1>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_cpu: ppmu@106c0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106c0000 0x2000>; + clocks = <&clock CLK_PPMUCPU>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_rightbus: ppmu@112a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x112a0000 0x2000>; + clocks = <&clock CLK_PPMURIGHT>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_leftbus: ppmu@116a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x116a0000 0x2000>; + clocks = <&clock CLK_PPMULEFT>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_camif: ppmu@11ac0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x11ac0000 0x2000>; + clocks = <&clock CLK_PPMUCAMIF>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_lcd0: ppmu@11e40000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x11e40000 0x2000>; + clocks = <&clock CLK_PPMULCD0>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_fsys: ppmu@12630000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12630000 0x2000>; + status = "disabled"; + }; + + ppmu_image: ppmu@12aa0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12aa0000 0x2000>; + clocks = <&clock CLK_PPMUIMAGE>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_tv: ppmu@12e40000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12e40000 0x2000>; + clocks = <&clock CLK_PPMUTV>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_g3d: ppmu@13220000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13220000 0x2000>; + clocks = <&clock CLK_PPMUG3D>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_mfc_left: ppmu@13660000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13660000 0x2000>; + clocks = <&clock CLK_PPMUMFC_L>; + clock-names = "ppmu"; + status = "disabled"; + }; + + ppmu_mfc_right: ppmu@13670000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13670000 0x2000>; + clocks = <&clock CLK_PPMUMFC_R>; + clock-names = "ppmu"; + status = "disabled"; + }; + + sysmmu_mfc_l: sysmmu@13620000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13620000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@13630000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13630000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@12e20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12e20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; + power-domains = <&pd_tv>; + #iommu-cells = <0>; + }; + + sysmmu_fimc0: sysmmu@11a20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_fimc1: sysmmu@11a30000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a30000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 3>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_fimc2: sysmmu@11a40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_fimc3: sysmmu@11a50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg: sysmmu@11a60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@12a30000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12a30000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, + <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; + + sysmmu_fimd0: sysmmu@11e20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11e20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = ; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; + + prng: rng@10830400 { + compatible = "samsung,exynos4-rng"; + reg = <0x10830400 0x200>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; + }; +}; + +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos4210-i9100.dts b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts new file mode 100644 index 000000000000..37cd4dde53e4 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Stenkin Evgeniy + * Copyright (c) 2020 Paul Cercueil + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include + +/ { + model = "Samsung Galaxy S2 (GT-I9100)"; + compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4"; + chassis-type = "handset"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + mmc2 = &sdhci_3; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-vol-down { + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + key-vol-up { + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + key-ok { + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "ok"; + debounce-interval = <10>; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + + i2c_max17042_fuel: i2c-gpio-0 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + + battery@36 { + compatible = "maxim,max17042"; + + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&max17042_fuel_irq>; + pinctrl-names = "default"; + + reg = <0x36>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + }; + }; + + i2c_s5k5baf: i2c-gpio-1 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sda-gpios = <&gpc1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpc1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + + image-sensor@2d { + compatible = "samsung,s5k5baf"; + reg = <0x2d>; + vdda-supply = <&cam_io_en_reg>; + vddreg-supply = <&vt_core_15v_reg>; + vddio-supply = <&vtcam_reg>; + clocks = <&camera 0>; + clock-names = "mclk"; + stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>; + rstn-gpios = <&gpl2 1 GPIO_ACTIVE_LOW>; + clock-frequency = <24000000>; + + port { + s5k5bafx_ep: endpoint { + remote-endpoint = <&csis1_ep>; + data-lanes = <1>; + }; + }; + }; + }; + + spi-3 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + num-chipselects = <1>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; + + lcd@0 { + compatible = "samsung,ld9040"; + reg = <0>; + + spi-max-frequency = <1200000>; + + vdd3-supply = <&vmipi_reg>; + vci-supply = <&vcclcd_reg>; + + reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + power-on-delay = <10>; + reset-delay = <10>; + + panel-width-mm = <90>; + panel-height-mm = <154>; + + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&camera { + pinctrl-0 = <&cam_port_a_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>, <&clock CLK_MOUT_CAM1>; + assigned-clock-parents = <&clock CLK_XUSBXTI>, <&clock CLK_XUSBXTI>; +}; + +&csis_1 { + status = "okay"; + vddcore-supply = <&vusb_reg>; + vddio-supply = <&vmipi_reg>; + clock-frequency = <160000000>; + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + csis1_ep: endpoint { + remote-endpoint = <&s5k5bafx_ep>; + data-lanes = <1>; + samsung,csis-hs-settle = <6>; + }; + }; +}; + +&cpu0 { + cpu0-supply = <&varm_breg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + +&ehci { + status = "okay"; + + phys = <&exynos_usbphy 1>; + phy-names = "host"; +}; + +&exynos_usbphy { + status = "okay"; + + vbus-supply = <&safe1_sreg>; +}; + +&fimc_0 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + /* Back camera not implemented */ + status = "disabled"; + + assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + /* Back camera not implemented */ + status = "disabled"; + + assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimd { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + samsung,invert-vden; + samsung,invert-vclk; + + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + + port@3 { + reg = <3>; + + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&gpu { + status = "okay"; + + mali-supply = <&vg3d_breg>; +}; + +&hsotg { + status = "okay"; + + dr_mode = "otg"; + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; +}; + +&i2c_3 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c_5 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + + pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + + interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>, + <&gpl0 0 GPIO_ACTIVE_HIGH>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; + pinctrl-names = "default"; + + charger-supply = <&charger_reg>; + + regulators { + vadc_reg: LDO1 { + regulator-name = "VADC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + }; + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vhsic_reg: LDO5 { + regulator-name = "VHSIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vtouch_reg: LDO11 { + regulator-name = "TOUCH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vmotor_reg: LDO14 { + regulator-name = "VCC_2.8V_MOTOR"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vled_reg: LDO15 { + regulator-name = "LED_A_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtf_reg: LDO17 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtouchled_reg: LDO18 { + regulator-name = "TOUCH_LED_3.3V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vg3d_breg: BUCK3 { + regulator-name = "G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-microvolt-offset = <50000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <200000>; + regulator-max-microamp = <950000>; + }; + + chargercv_reg: CHARGER_CV { + regulator-name = "CHARGER_CV"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + CHARGER_TOPOFF { + regulator-name = "CHARGER_TOPOFF"; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_7 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-1-pin { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-2-pin { + samsung,pins = "gpa0-2"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-3-pin { + samsung,pins = "gpa0-3"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + }; +}; + +&pinctrl_1 { + mhl_int: mhl-int-pins { + samsung,pins = "gpf3-5"; + samsung,pin-pud = ; + }; + + i2c_mhl_bus: i2c-mhl-bus-pins { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb_sel: usb-sel-pins { + samsung,pins = "gpl0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + bt_en: bt-en-pins { + samsung,pins = "gpl0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + bt_res: bt-res-pins { + samsung,pins = "gpl1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + otg_gp: otg-gp-pins { + samsung,pins = "gpx3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + mag_mhl_gpio: mag-mhl-pins { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max8997_irq: max8997-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + max17042_fuel_irq: max17042-fuel-irq-pins { + samsung,pins = "gpx2-3"; + samsung,pin-pud = ; + }; + + tsp224_irq: tsp224-irq-pins { + samsung,pins = "gpx0-4"; + samsung,pin-pud = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_0 { + status = "okay"; + + bus-width = <8>; + non-removable; + vmmc-supply = <&vemmc_reg>; + + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>; + pinctrl-names = "default"; +}; + +&sdhci_2 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vtf_reg>; + + pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>; + pinctrl-names = "default"; +}; + +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&vtf_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + + shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + + interrupt-parent = <&gpx2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4210-origen.dts b/arch/arm/boot/dts/samsung/exynos4210-origen.dts new file mode 100644 index 000000000000..f1927ca15e08 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210-origen.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Insignal's Origen board which is based on + * Samsung's Exynos4210 SoC. + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include +#include +#include +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000>; + }; + + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial2:115200n8"; + }; + + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-up { + label = "Up"; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-down { + label = "Down"; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-back { + label = "Back"; + gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-home { + label = "Home"; + gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-menu { + label = "Menu"; + gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + led-status { + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <47500000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <64>; + hback-porch = <16>; + hsync-len = <48>; + vback-porch = <64>; + vfront-porch = <16>; + vsync-len = <3>; + }; + }; +}; + +&cpu0 { + cpu0-supply = <&buck1_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo3_reg>; + vusb_a-supply = <&ldo8_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + + pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max8997_irq>; + + max8997,pmic-buck1-dvs-voltage = <1350000>; + max8997,pmic-buck2-dvs-voltage = <1100000>; + max8997,pmic-buck5-dvs-voltage = <1200000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ABB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_ALIVE_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VMIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_RTC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_AUD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "DVDD_SWB_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD_PLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_AUD_3V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "AVDD18_SWB_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDD_SWB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_MIF_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_ARM_1.2V"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_INT_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VDD_LCD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + }; + }; +}; + +&pinctrl_1 { + max8997_irq: max8997-irq-pins { + samsung,pins = "gpx0-3", "gpx0-4"; + samsung,pin-pud = ; + }; +}; + +&sdhci_0 { + bus-width = <4>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; + pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi new file mode 100644 index 000000000000..70d268f9fcb1 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi @@ -0,0 +1,863 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2011-2012 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include "exynos-pinctrl.h" + +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe3: gpe3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe4: gpe4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_a: uart-audio-a-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_b: uart-audio-b-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ac97_bus: ac97-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpd0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ctrl: lcd-ctrl-pins { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_sync: lcd-sync-pins { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_en: lcd-en-pins { + samsung,pins = "gpe3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_clk: lcd-clk-pins { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data16: lcd-data-width16-pins { + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data18: lcd-data-width18-pins { + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", + "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data24: lcd-data-width24-pins { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpj0: gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_clk: sd4-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cmd: sd4-cmd-pins { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cd: sd4-cd-pins { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus1: sd4-bus-width1-pins { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus4: sd4-bus-width4-pins { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus8: sd4-bus-width8-pins { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpk1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpk1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpk1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpk1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpk2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpk2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpk2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpk2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus8: sd2-bus-width8-pins { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_clk: sd3-clk-pins { + samsung,pins = "gpk3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cmd: sd3-cmd-pins { + samsung,pins = "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cd: sd3-cd-pins { + samsung,pins = "gpk3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus1: sd3-bus-width1-pins { + samsung,pins = "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus4: sd3-bus-width4-pins { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint0: ext-int0-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint8: ext-int8-pins { + samsung,pins = "gpx1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint15: ext-int15-pins { + samsung,pins = "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint16: ext-int16-pins { + samsung,pins = "gpx2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint31: ext-int31-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_io: cam-port-a-io-pins { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_active: cam-port-a-clk-active-pins { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_cec: hdmi-cec-pins { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpz: gpz-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm0_bus: pcm0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts new file mode 100644 index 000000000000..b566f878ed84 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based SMDKV310 board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Samsung's SMDKV310 board which is based on + * Samsung's Exynos4210 SoC. + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + model = "Samsung smdkv310 evaluation board based on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + mmc0 = &sdhci_2; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial1:115200n8"; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <12000000>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + eeprom@50 { + compatible = "samsung,24ad0xd1"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "samsung,24ad0xd1"; + reg = <0x52>; + }; +}; + +&keypad { + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_rows &keypad_cols>; + status = "okay"; + + key-1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key-2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + + key-3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <4>; + }; + + key-4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = <5>; + }; + + key-5 { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <6>; + }; + + key-a { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <30>; + }; + + key-b { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <48>; + }; + + key-c { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <46>; + }; + + key-d { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <32>; + }; + + key-e { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <18>; + }; +}; + +&pinctrl_1 { + keypad_rows: keypad-rows-pins { + samsung,pins = "gpx2-0", "gpx2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_cols: keypad-cols-pins { + samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", + "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&spi_2 { + cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25x80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4210-trats.dts b/arch/arm/boot/dts/samsung/exynos4210-trats.dts new file mode 100644 index 000000000000..bfb04b31e11b --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210-trats.dts @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Trats board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Trats board which is based on + * Samsung's Exynos4210 SoC. + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include + +/ { + model = "Samsung Trats based on Exynos4210"; + compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; + chassis-type = "handset"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000>; + }; + + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + mmc2 = &sdhci_3; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + stdout-path = "serial2:115200n8"; + }; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + vol-down-key { + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = <114>; + label = "volume down"; + debounce-interval = <10>; + }; + + vol-up-key { + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = <115>; + label = "volume up"; + debounce-interval = <10>; + }; + + power-key { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + ok-key { + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,code = <352>; + label = "ok"; + debounce-interval = <10>; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&camera { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&varm_breg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; + }; + }; +}; + +&dsi_0 { + vddcore-supply = <&vusb_reg>; + vddio-supply = <&vmipi_reg>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + panel@0 { + reg = <0>; + compatible = "samsung,s6e8aa0"; + vdd3-supply = <&vcclcd_reg>; + vci-supply = <&vlcd_reg>; + reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + power-on-delay = <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <57153600>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; + vbus-supply = <&safe1_sreg>; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimd { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + avdd-supply = <&tsp_reg>; + vdd-supply = <&tsp_reg>; + }; +}; + +&i2c_5 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + status = "okay"; + + pmic@66 { + compatible = "maxim,max8997-pmic"; + + reg = <0x66>; + interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>, + <&gpl0 0 GPIO_ACTIVE_HIGH>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + regulators { + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.3V_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vlcd_reg: LDO15 { + regulator-name = "VLCD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + tflash_reg: LDO17 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V_C210"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; + }; + }; + }; +}; + +&pinctrl_1 { + bt_shutdown: bt-shutdown-pins { + samsung,pins = "gpl1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup-pins { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_0 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&vemmc_reg>; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&tflash_reg>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&tflash_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + status = "okay"; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + shutdown-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts new file mode 100644 index 000000000000..c84af3d27c1c --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts @@ -0,0 +1,689 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Universal C210 board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Universal C210 board which is based on + * Samsung's Exynos4210 rev0 SoC. + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include + +/ { + model = "Samsung Universal C210 based on Exynos4210 rev0"; + compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; + chassis-type = "handset"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000>; + }; + + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + mmc2 = &sdhci_3; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; + stdout-path = "serial2:115200n8"; + }; + + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + vemmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2_8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + vol-up-key { + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = <115>; + label = "volume up"; + debounce-interval = <1>; + }; + + vol-down-key { + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = <114>; + label = "volume down"; + debounce-interval = <1>; + }; + + config-key { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = <171>; + label = "config"; + debounce-interval = <1>; + wakeup-source; + }; + + camera-key { + gpios = <&gpx2 3 GPIO_ACTIVE_LOW>; + linux,code = <212>; + label = "camera"; + debounce-interval = <1>; + }; + + power-key { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + debounce-interval = <1>; + wakeup-source; + }; + + ok-key { + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,code = <352>; + label = "ok"; + debounce-interval = <1>; + }; + }; + + tsp_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "TSP_2_8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + spi-3 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; + + lcd@0 { + compatible = "samsung,ld9040"; + reg = <0>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <1200000>; + power-on-delay = <10>; + reset-delay = <10>; + panel-width-mm = <90>; + panel-height-mm = <154>; + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + + hdmi_en: voltage-regulator-hdmi-5v { + compatible = "regulator-fixed"; + regulator-name = "HDMI_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpe0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + hdmi_ddc: i2c-ddc { + compatible = "i2c-gpio"; + sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <100>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&i2c_ddc_bus>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&camera { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_arm_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + +&ehci { + status = "okay"; + phys = <&exynos_usbphy 1>; + phy-names = "host"; +}; + +&exynos_usbphy { + status = "okay"; + vbus-supply = <&safeout1_reg>; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimd { + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + status = "okay"; + samsung,invert-vden; + samsung,invert-vclk; + #address-cells = <1>; + #size-cells = <0>; + port@3 { + reg = <3>; + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&gpu { + mali-supply = <&buck2_reg>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + hdmi-en-supply = <&hdmi_en>; + vdd-supply = <&ldo3_reg>; + vdd_osc-supply = <&ldo4_reg>; + vdd_pll-supply = <&ldo3_reg>; + ddc = <&hdmi_ddc>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo3_reg>; + vusb_a-supply = <&ldo8_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + tsp@4a { + /* TBD: Atmel maXtouch touchscreen */ + reg = <0x4a>; + }; +}; + +&i2c_5 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + status = "okay"; + + vdd_arm_reg: pmic@60 { + compatible = "maxim,max8952"; + reg = <0x60>; + + max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>, + <&gpx0 4 GPIO_ACTIVE_HIGH>; + max8952,default-mode = <0>; + max8952,dvs-mode-microvolt = <1250000>, <1200000>, + <1050000>, <950000>; + max8952,sync-freq = <0>; + max8952,ramp-speed = <0>; + + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <770000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + pmic@66 { + compatible = "national,lp3974"; + interrupts-extended = <&gpx0 7 0>, <&gpx2 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&lp3974_irq>; + reg = <0x66>; + + max8998,pmic-buck1-default-dvs-idx = <0>; + max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, + <1100000>, <1000000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB+MIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD+VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo12_reg: LDO12 { + regulator-name = "PS_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VHIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "CAM_I_HOST_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "CAM_S_ANA_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VINT_1.1V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VG3D_1.1V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + }; + + safeout1_reg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safeout2_reg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + }; + }; +}; + +&i2c_8 { + status = "okay"; +}; + +&mct { + status = "disabled"; +}; + +&mdma1 { + /* Use the secure mdma0 */ + status = "disabled"; +}; + +&mixer { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pinctrl_1 { + bt_shutdown: bt-shutdown-pins { + samsung,pins = "gpe1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup-pins { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lp3974_irq: lp3974-irq-pins { + samsung,pins = "gpx0-7", "gpx2-7"; + samsung,pin-pud = ; + }; + + hdmi_hpd: hdmi-hpd-pins { + samsung,pins = "gpx3-7"; + samsung,pin-pud = ; + }; +}; + +&pinctrl_0 { + i2c_ddc_bus: i2c-ddc-bus-pins { + samsung,pins = "gpe4-2", "gpe4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + compatible = "samsung,s5p6440-pwm"; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_0 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&vemmc_reg>; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo5_reg>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&ldo5_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + shutdown-gpios = <&gpe1 4 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&serial_1 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&serial_2 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&serial_3 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&soc { + mdma0: dma-controller@12840000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12840000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + power-domains = <&pd_lcd0>; + }; +}; + +&sysram { + smp-sram@0 { + status = "disabled"; + }; + + smp-sram@5000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x5000 0x1000>; + }; + + smp-sram@1f000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4210.dtsi b/arch/arm/boot/dts/samsung/exynos4210.dtsi new file mode 100644 index 000000000000..0e27c3375e2e --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4210.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4.dtsi" +#include "exynos4-cpu-thermal.dtsi" + +/ { + compatible = "samsung,exynos4210", "samsung,exynos4"; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + }; + + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + opp-suspend; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_lcd0: bus-lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x900>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x901>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + bus_leftbus_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-suspend; + }; + }; + + soc: soc { + sysram: sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x20000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@1f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x1f000 0x1000>; + }; + }; + + pd_lcd1: power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023ca0 0x20>; + #power-domain-cells = <0>; + label = "LCD1"; + }; + + l2c: cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; + + mct: timer@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&combiner 12 6>, + <&combiner 12 7>, + <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@10060000 { + compatible = "samsung,s3c6410-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + }; + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_2: pinctrl@3860000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x03860000 0x1000>; + }; + + g2d: g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + power-domains = <&pd_lcd0>; + iommus = <&sysmmu_g2d>; + }; + + ppmu_acp: ppmu@10ae0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10ae0000 0x2000>; + status = "disabled"; + }; + + ppmu_lcd1: ppmu@12240000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12240000 0x2000>; + clocks = <&clock CLK_PPMULCD1>; + clock-names = "ppmu"; + status = "disabled"; + }; + + sysmmu_g2d: sysmmu@12a20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12a20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1: sysmmu@12220000 { + compatible = "samsung,exynos-sysmmu"; + interrupt-parent = <&combiner>; + reg = <0x12220000 0x1000>; + interrupts = <5 3>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; + power-domains = <&pd_lcd1>; + #iommu-cells = <0>; + }; + }; +}; + +&cpu_alert0 { + temperature = <85000>; /* millicelsius */ +}; + +&cpu_alert1 { + temperature = <100000>; /* millicelsius */ +}; + +&cpu_alert2 { + temperature = <110000>; /* millicelsius */ +}; + +&cpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; +}; + +&gic { + cpu-offset = <0x8000>; +}; + +&camera { + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; +}; + +&combiner { + samsung,combiner-nr = <16>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&fimc_0 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; +}; + +&fimc_1 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; +}; + +&fimc_2 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,lcd-wb; +}; + +&fimc_3 { + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,lcd-wb; +}; + +&gpu { + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + }; +}; + +&mdma1 { + power-domains = <&pd_lcd0>; +}; + +&mixer { + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", + "sclk_mixer"; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, + <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; +}; + +&pmu { + interrupts = <2 2>, <3 2>; + interrupt-affinity = <&cpu0>, <&cpu1>; + status = "okay"; +}; + +&pmu_system_controller { + clock-names = "clkout0", "clkout1", "clkout2", "clkout3", + "clkout4", "clkout8", "clkout9"; + clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, + <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, + <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; + #clock-cells = <1>; +}; + +&rotator { + power-domains = <&pd_lcd0>; +}; + +&sysmmu_rotator { + power-domains = <&pd_lcd0>; +}; + +&tmu { + compatible = "samsung,exynos4210-tmu"; + clocks = <&clock CLK_TMU_APBIF>; + clock-names = "tmu_apbif"; +}; + +#include "exynos4210-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos4212.dtsi b/arch/arm/boot/dts/samsung/exynos4212.dtsi new file mode 100644 index 000000000000..aa984601ee06 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4212.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4212", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + opp-suspend; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + cpu0_opp_1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; + }; + }; +}; + +&clock { + compatible = "samsung,exynos4212-clock"; +}; + +&combiner { + samsung,combiner-nr = <18>; +}; + +&gic { + cpu-offset = <0x8000>; +}; + +&pmu { + interrupts = <2 2>, <3 2>; + interrupt-affinity = <&cpu0>, <&cpu1>; + status = "okay"; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4212-pmu", "simple-mfd", "syscon"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi new file mode 100644 index 000000000000..94122e9c6625 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based Galaxy S3 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include +#include "exynos4412-midas.dtsi" + +/ { + aliases { + i2c9 = &i2c_ak8975; + i2c10 = &i2c_cm36651; + }; + + led-controller { + compatible = "skyworks,aat1290"; + flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; + enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "host", "isp"; + pinctrl-0 = <&camera_flash_host>; + pinctrl-1 = <&camera_flash_host>; + pinctrl-2 = <&camera_flash_isp>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + led-max-microamp = <520833>; + flash-max-microamp = <1012500>; + flash-max-timeout-us = <1940000>; + }; + }; + + lcd_vdd3_reg: voltage-regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "LCD_VDD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + ps_als_reg: voltage-regulator-11 { + compatible = "regulator-fixed"; + regulator-name = "LED_A_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + i2c_ak8975: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c_cm36651: i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@18 { + compatible = "capella,cm36651"; + reg = <0x18>; + interrupt-parent = <&gpx0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + vled-supply = <&ps_als_reg>; + }; + }; +}; + +&buck9_reg { + maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; +}; + +&cam_af_reg { + gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cam_io_reg { + gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi_0 { + status = "okay"; + + panel@0 { + compatible = "samsung,s6e8aa0"; + reg = <0>; + vdd3-supply = <&lcd_vdd3_reg>; + vci-supply = <&ldo25_reg>; + reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; + power-on-delay = <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <57153600>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + }; +}; + +&i2c_3 { + touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + avdd-supply = <&ldo23_reg>; + vdd-supply = <&ldo24_reg>; + }; +}; + +&ldo25_reg { + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&pinctrl_0 { + camera_flash_host: camera-flash-host-pins { + samsung,pins = "gpj1-0"; + samsung,pin-function = ; + samsung,pin-val = <0>; + }; + + camera_flash_isp: camera-flash-isp-pins { + samsung,pins = "gpj1-0"; + samsung,pin-function = ; + samsung,pin-val = <1>; + }; +}; + +&s5c73m3 { + standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ + vdda-supply = <&ldo17_reg>; + status = "okay"; +}; + +&sound { + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + "SPK", "SPKOUTRN", + "SPK", "SPKOUTRP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "MICBIAS1", + "IN1LN", "MICBIAS1", + "Main Mic", "MICBIAS1", + + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", + + "IN2LP:VXRN", "MICBIAS2", + "Headset Mic", "MICBIAS2", + + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; +}; + +&submic_bias_reg { + gpio = <&gpf2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&touchkey_reg { + gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-i9300.dts b/arch/arm/boot/dts/samsung/exynos4412-i9300.dts new file mode 100644 index 000000000000..61aca5798f38 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-i9300.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412-galaxy-s3.dtsi" + +/ { + model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412"; + compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + chassis-type = "handset"; + + /* bootargs are passed in by bootloader */ + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; +}; + +&sound { + fm-sel-gpios = <&gpl0 3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-i9305.dts b/arch/arm/boot/dts/samsung/exynos4412-i9305.dts new file mode 100644 index 000000000000..77083f1a8273 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-i9305.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "exynos4412-galaxy-s3.dtsi" + +/ { + model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412"; + compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + chassis-type = "handset"; + + /* bootargs are passed in by bootloader */ + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; +}; + +&i2c0_bus { + /* SCL and SDA pins are swapped */ + samsung,pins = "gpd1-1", "gpd1-0"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts b/arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts new file mode 100644 index 000000000000..ded232b04e0d --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TOPEET's Exynos4412 based itop board device tree source + * + * Copyright (c) 2016 SUMOMO Computer Association + * https://www.sumomo.mobi + * Randy Li + * + * Device tree source file for TOPEET iTop Exynos 4412 core board + * which is based on Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include +#include +#include +#include "exynos4412-itop-scp-core.dtsi" + +/ { + model = "TOPEET iTop 4412 Elite board based on Exynos4412"; + compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; + + aliases { + mmc1 = &sdhci_2; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; + stdout-path = "serial2:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led2 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led3 { + label = "red:user"; + color = ; + gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "GPIO Key Home"; + linux,code = ; + gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; + }; + + key-back { + label = "GPIO Key Back"; + linux,code = ; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + }; + + key-sleep { + label = "GPIO Key Sleep"; + linux,code = ; + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + }; + + key-vol-up { + label = "GPIO Key Vol+"; + linux,code = ; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + }; + + key-vol-down { + label = "GPIO Key Vol-"; + linux,code = ; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm-sound"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "Speaker", "SPK_RP", + "Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + system-clock-frequency = <11289600>; + }; + }; + + beep { + compatible = "pwm-beeper"; + pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; +}; + +&camera { + pinctrl-0 = <&cam_port_a_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, <0>, <112896000>, <11289600>; +}; + +&ehci { + status = "okay"; + /* In order to reset USB ethernet */ + samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; + + phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>; + phy-names = "host", "hsic1"; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&hsotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c4_bus>; + pinctrl-names = "default"; + status = "okay"; + + codec: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl_1 { + ether-reset-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + status = "okay"; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + cd-gpios = <&gpx0 7 GPIO_ACTIVE_LOW>; + cap-sd-highspeed; + vmmc-supply = <&ldo23_reg>; + vqmmc-supply = <&ldo17_reg>; + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi new file mode 100644 index 000000000000..7bc6968af9c3 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi @@ -0,0 +1,509 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TOPEET's Exynos4412 based itop board device tree source + * + * Copyright (c) 2016 SUMOMO Computer Association + * https://www.sumomo.mobi + * Randy Li + * + * Device tree source file for TOPEET iTop Exynos 4412 SCP package core + * board which is based on Samsung's Exynos4412 SoC. + */ + +#include +#include +#include +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + mmc0 = &mshc_0; + }; + + firmware@203f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203f000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, + <&cpu1 13 13>, + <&cpu2 13 13>, + <&cpu3 13 13>; + }; + }; + }; + }; + + usb-hub { + compatible = "smsc,usb3503a"; + reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>; + connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsic_reset>; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5m8767: pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + + s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>, + <&gpb 6 GPIO_ACTIVE_HIGH>, + <&gpb 7 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, + <&gpm3 6 GPIO_ACTIVE_HIGH>, + <&gpm3 7 GPIO_ACTIVE_HIGH>; + + /* VDD_ARM */ + s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>, + <1243750>, <1118750>, + <1068750>, <1012500>, + <956250>, <900000>; + /* VDD_INT */ + s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>, + <925000>, <925000>, + <887500>, <887500>, + <850000>, <850000>; + /* VDD_G3D */ + s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>, + <1025000>, <950000>, + <918750>, <900000>, + <875000>, <831250>; + wakeup-source; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + /* SCP uses 1.5v, POP uses 1.2v */ + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M12"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDIOAP_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_LDO5"; + op_mode = <0>; /* Always off Mode */ + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD10_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD33_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD18_MIPI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_UOTG"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDIOPERI_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB02"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_USH"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDIOAP_MMC012_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + /* Used by HSIC */ + ldo18_reg: LDO18 { + regulator-name = "VDDIOPERI_28"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_LDO19"; + op_mode = <0>; /* Always off Mode */ + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD28_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD28_AF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo22_reg: LDO22 { + regulator-name = "VDDA28_2M"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD28_TF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD33_A31"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD18_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD18_A31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo27_reg: LDO27 { + regulator-name = "GPS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo28_reg: LDO28 { + regulator-name = "DVDD12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; /* Normal Mode */ + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1456250>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_m12"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd12_5m"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck7_reg: BUCK7 { + regulator-name = "pvdd_buck7"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck8_reg: BUCK8 { + regulator-name = "pvdd_buck8"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck9_reg: BUCK9 { + regulator-name = "vddf28_emmc"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; /* Normal Mode */ + }; + }; + + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", + "s5m8767_cp", "s5m8767_bt"; + }; + + }; +}; + +&mfc { + status = "okay"; +}; + +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + vmmc-supply = <&buck9_reg>; + broken-cd; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&pinctrl_1 { + hsic_reset: hsic-reset-pins { + samsung,pins = "gpm2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu { + vtmu-supply = <&ldo16_reg>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi new file mode 100644 index 000000000000..e6b949c1a00f --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi @@ -0,0 +1,1459 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based Trats 2 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Trats 2 board which is based on + * Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include +#include +#include +#include "exynos-pinctrl.h" + +/ { + compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + + aliases { + i2c11 = &i2c_max77693; + i2c12 = &i2c_max77693_fuel; + mmc0 = &mshc_0; + mmc2 = &sdhci_2; + mmc3 = &sdhci_3; + }; + + chosen { + stdout-path = &serial_2; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204f000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + cam_io_reg: voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "CAM_SENSOR_A"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + status = "disabled"; + }; + + cam_af_reg: voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + status = "disabled"; + }; + + vsil12: voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VSIL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&buck7_reg>; + }; + + vcc33mhl: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3.3_MHL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc18mhl: voltage-regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8_MHL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + touchkey_reg: voltage-regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "LED_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + status = "disabled"; + }; + + vbatt_reg: voltage-regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "VBATT"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + mic_bias_reg: voltage-regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpf1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + submic_bias_reg: voltage-regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "SUB_MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-down { + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + linux,code = <114>; + label = "volume down"; + debounce-interval = <10>; + }; + + key-up { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = <115>; + label = "volume up"; + debounce-interval = <10>; + }; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + key-ok { + gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; + linux,code = <139>; + label = "ok"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + i2c_max77693: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max77693"; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_irq>; + reg = <0x66>; + + regulators { + esafeout1_reg: ESAFEOUT1 { + regulator-name = "ESAFEOUT1"; + }; + esafeout2_reg: ESAFEOUT2 { + regulator-name = "ESAFEOUT2"; + }; + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + }; + }; + + motor-driver { + compatible = "maxim,max77693-haptic"; + haptic-supply = <&ldo26_reg>; + pwms = <&pwm 0 38022 0>; + }; + + charger { + compatible = "maxim,max77693-charger"; + + maxim,constant-microvolt = <4350000>; + maxim,min-system-microvolt = <3600000>; + maxim,thermal-regulation-celsius = <100>; + maxim,battery-overcurrent-microamp = <3500000>; + maxim,charge-input-threshold-microvolt = <4300000>; + }; + }; + }; + + i2c_max77693_fuel: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuel-gauge@36 { + compatible = "maxim,max17047"; + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_fuel_irq>; + reg = <0x36>; + + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + }; + }; + + i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "cypress,midas-touchkey"; + reg = <0x20>; + vdd-supply = <&touchkey_reg>; + vcc-supply = <&ldo5_reg>; + interrupt-parent = <&gpj0>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + linux,keycodes = ; + }; + }; + + i2c-mhl { + compatible = "i2c-gpio"; + sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <100>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&i2c_mhl_bus>; + pinctrl-names = "default"; + + sii9234: hdmi-bridge@39 { + compatible = "sil,sii9234"; + avcc33-supply = <&vcc33mhl>; + iovcc18-supply = <&vcc18mhl>; + avcc12-supply = <&vsil12>; + cvcc12-supply = <&vsil12>; + reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpf3>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x39>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + }; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; + + sound: sound { + compatible = "samsung,midas-audio"; + model = "Midas"; + mic-bias-supply = <&mic_bias_reg>; + submic-bias-supply = <&submic_bias_reg>; + + cpu { + sound-dai = <&i2s0 0>; + }; + codec { + sound-dai = <&wm1811>; + }; + }; + + thermistor-ap { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; /* VCC_1.8V_AP */ + pullup-ohm = <100000>; /* 100K */ + pulldown-ohm = <100000>; /* 100K */ + io-channels = <&adc 1>; /* AP temperature */ + }; + + thermistor-battery { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; /* VCC_1.8V_AP */ + pullup-ohm = <100000>; /* 100K */ + pulldown-ohm = <100000>; /* 100K */ + io-channels = <&adc 2>; /* Battery temperature */ + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&camera { + pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>, + <&clock CLK_MOUT_CAM1>; + assigned-clock-parents = <&clock CLK_XUSBXTI>, + <&clock CLK_XUSBXTI>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&csis_0 { + status = "okay"; + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + assigned-clocks = <&clock CLK_MOUT_CSIS0>, + <&clock CLK_SCLK_CSIS0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; + + /* Camera C (3) MIPI CSI-2 (CSIS0) */ + port@3 { + reg = <3>; + csis0_ep: endpoint { + remote-endpoint = <&s5c73m3_ep>; + data-lanes = <1 2 3 4>; + samsung,csis-hs-settle = <12>; + }; + }; +}; + +&csis_1 { + status = "okay"; + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + assigned-clocks = <&clock CLK_MOUT_CSIS1>, + <&clock CLK_SCLK_CSIS1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; + + /* Camera D (4) MIPI CSI-2 (CSIS1) */ + port@4 { + reg = <4>; + csis1_ep: endpoint { + remote-endpoint = <&is_s5k6a3_ep>; + data-lanes = <1>; + samsung,csis-hs-settle = <18>; + samsung,csis-wclk; + }; + }; +}; + +&dsi_0 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <24000000>; +}; + +&exynos_usbphy { + vbus-supply = <&esafeout1_reg>; + status = "okay"; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_is { + pinctrl-0 = <&fimc_is_uart>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fimc_lite_0 { + status = "okay"; +}; + +&fimc_lite_1 { + status = "okay"; +}; + +&fimd { + status = "okay"; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + vdd-supply = <&ldo3_reg>; + vdd_osc-supply = <&ldo4_reg>; + vdd_pll-supply = <&ldo3_reg>; + ddc = <&i2c_5>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + hdmi_to_mhl: endpoint { + remote-endpoint = <&mhl_to_hdmi>; + }; + }; + }; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_0 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5c73m3: image-sensor@3c { + compatible = "samsung,s5c73m3"; + reg = <0x3c>; + xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ + vdd-int-supply = <&buck9_reg>; + vddio-cis-supply = <&ldo9_reg>; + vddio-host-supply = <&ldo18_reg>; + vdd-af-supply = <&cam_af_reg>; + vdd-reg-supply = <&cam_io_reg>; + clock-frequency = <24000000>; + /* CAM_A_CLKOUT */ + clocks = <&camera 0>; + clock-names = "cis_extclk"; + status = "disabled"; + port { + s5c73m3_ep: endpoint { + remote-endpoint = <&csis0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c1_isp { + pinctrl-0 = <&fimc_is_i2c1>; + pinctrl-names = "default"; + + image-sensor@10 { + compatible = "samsung,s5k6a3"; + reg = <0x10>; + svdda-supply = <&cam_io_reg>; + svddio-supply = <&ldo19_reg>; + afvdd-supply = <&ldo19_reg>; + clock-frequency = <24000000>; + /* CAM_B_CLKOUT */ + clocks = <&camera 1>; + clock-names = "extclk"; + gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; + + port { + is_s5k6a3_ep: endpoint { + remote-endpoint = <&csis1_ep>; + data-lanes = <1>; + }; + }; + }; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c4_bus>; + pinctrl-names = "default"; + status = "okay"; + + wm1811: audio-codec@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + clocks = <&pmu_system_controller 0>, + <&max77686 MAX77686_CLK_PMIC>; + clock-names = "MCLK1", "MCLK2"; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpx3>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <0>; + + wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0 + 0x0 0x8000 0x0 0x0 0x0>; + wlf,micbias-cfg = <0x2f 0x2b>; + + wlf,lineout1-feedback; + wlf,lineout1-se; + wlf,lineout2-se; + wlf,ldoena-always-driven; + + AVDD2-supply = <&vbatt_reg>; + DBVDD1-supply = <&ldo3_reg>; + DBVDD2-supply = <&vbatt_reg>; + DBVDD3-supply = <&vbatt_reg>; + DCVDD-supply = <&ldo3_reg>; + CPVDD-supply = <&vbatt_reg>; + SPKVDD1-supply = <&vbatt_reg>; + SPKVDD2-supply = <&vbatt_reg>; + wlf,ldo1ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_5 { + status = "okay"; +}; + +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; + wakeup-source; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VMPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "CAM_ISP_MIPI_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VABB1_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "NFC_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VABB2_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "CAM_ISP_SEN_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDDQ_PRE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; + }; + + ldo22_reg: LDO22 { + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo23_reg: LDO23 { + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "LDO25"; + }; + + ldo26_reg: LDO26 { + regulator-name = "MOTOR_VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VMEM_VDDF_3.0V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + buck9_reg: BUCK9 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; +}; + +&i2c_8 { + status = "okay"; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +&mshc_0 { + broken-cd; + non-removable; + card-detect-delay = <200>; + vmmc-supply = <&ldo22_reg>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + mmc-ddr-1_8v; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + mhl_int: mhl-int-pins { + samsung,pins = "gpf3-5"; + samsung,pin-pud = ; + }; + + i2c_mhl_bus: i2c-mhl-bus-pins { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, NONE); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, UP); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, UP); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, NONE); + PIN_SLP(gpc1-1, PREV, NONE); + PIN_SLP(gpc1-2, INPUT, NONE); + PIN_SLP(gpc1-3, INPUT, NONE); + PIN_SLP(gpc1-4, INPUT, NONE); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, INPUT, NONE); + PIN_SLP(gpf0-1, INPUT, NONE); + PIN_SLP(gpf0-2, INPUT, DOWN); + PIN_SLP(gpf0-3, INPUT, DOWN); + PIN_SLP(gpf0-4, INPUT, NONE); + PIN_SLP(gpf0-5, INPUT, DOWN); + PIN_SLP(gpf0-6, INPUT, NONE); + PIN_SLP(gpf0-7, INPUT, DOWN); + + PIN_SLP(gpf1-0, INPUT, DOWN); + PIN_SLP(gpf1-1, INPUT, DOWN); + PIN_SLP(gpf1-2, INPUT, DOWN); + PIN_SLP(gpf1-3, INPUT, DOWN); + PIN_SLP(gpf1-4, INPUT, NONE); + PIN_SLP(gpf1-5, INPUT, NONE); + PIN_SLP(gpf1-6, INPUT, DOWN); + PIN_SLP(gpf1-7, PREV, NONE); + + PIN_SLP(gpf2-0, PREV, NONE); + PIN_SLP(gpf2-1, INPUT, DOWN); + PIN_SLP(gpf2-2, INPUT, DOWN); + PIN_SLP(gpf2-3, INPUT, DOWN); + PIN_SLP(gpf2-4, INPUT, DOWN); + PIN_SLP(gpf2-5, INPUT, DOWN); + PIN_SLP(gpf2-6, INPUT, NONE); + PIN_SLP(gpf2-7, INPUT, NONE); + + PIN_SLP(gpf3-0, INPUT, NONE); + PIN_SLP(gpf3-1, PREV, NONE); + PIN_SLP(gpf3-2, PREV, NONE); + PIN_SLP(gpf3-3, PREV, NONE); + PIN_SLP(gpf3-4, OUT1, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpj0-0, PREV, NONE); + PIN_SLP(gpj0-1, PREV, NONE); + PIN_SLP(gpj0-2, PREV, NONE); + PIN_SLP(gpj0-3, INPUT, DOWN); + PIN_SLP(gpj0-4, PREV, NONE); + PIN_SLP(gpj0-5, PREV, NONE); + PIN_SLP(gpj0-6, INPUT, DOWN); + PIN_SLP(gpj0-7, INPUT, DOWN); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, PREV, NONE); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, INPUT, DOWN); + PIN_SLP(gpj1-4, INPUT, DOWN); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + gpio_keys: gpio-keys-pins { + samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; + samsung,pin-pud = ; + }; + + bt_shutdown: bt-shutdown-pins { + samsung,pins = "gpl0-6"; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup-pins { + samsung,pins = "gpx3-1"; + samsung,pin-pud = ; + }; + + max77686_irq: max77686-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + max77693_irq: max77693-irq-pins { + samsung,pins = "gpx1-5"; + samsung,pin-pud = ; + }; + + max77693_fuel_irq: max77693-fuel-irq-pins { + samsung,pins = "gpx2-3"; + samsung,pin-pud = ; + }; + + sdhci2_cd: sdhci2-cd-irq-pins { + samsung,pins = "gpx3-4"; + samsung,pin-pud = ; + }; + + hdmi_hpd: hdmi-hpd-pins { + samsung,pins = "gpx3-7"; + samsung,pin-pud = ; + }; + + sleep1: sleep-state { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, PREV, NONE); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, INPUT, DOWN); + PIN_SLP(gpl1-1, INPUT, DOWN); + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, INPUT, DOWN); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, PREV, NONE); + PIN_SLP(gpl2-7, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, DOWN); + PIN_SLP(gpy0-3, INPUT, DOWN); + PIN_SLP(gpy0-4, INPUT, DOWN); + PIN_SLP(gpy0-5, INPUT, DOWN); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-state { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-state { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + status = "okay"; +}; + +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_NONE>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + max-speed = <3000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&spi_1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + + s5c73m3_spi: image-sensor@0 { + compatible = "samsung,s5c73m3"; + spi-max-frequency = <50000000>; + reg = <0>; + controller-data { + samsung,spi-feedback-delay = <2>; + }; + }; +}; + +&tmu { + vtmu-supply = <&ldo10_reg>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-n710x.dts b/arch/arm/boot/dts/samsung/exynos4412-n710x.dts new file mode 100644 index 000000000000..9ae05b0d684c --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-n710x.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "exynos4412-midas.dtsi" + +/ { + compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412"; + chassis-type = "handset"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + /* bootargs are passed in by bootloader */ + + cam_vdda_reg: voltage-regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&buck9_reg { + maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>; +}; + +&cam_af_reg { + gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cam_io_reg { + gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms152"; + reg = <0x48>; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + avdd-supply = <&ldo23_reg>; + vdd-supply = <&ldo24_reg>; + }; +}; + +&ldo13_reg { + regulator-name = "VCC_1.8V_LCD"; + regulator-always-on; +}; + +&ldo25_reg { + regulator-name = "VCI_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&s5c73m3 { + standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ + vdda-supply = <&cam_vdda_reg>; + status = "okay"; +}; + +&sound { + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "MICBIAS2", + "IN1LN", "MICBIAS2", + "Headset Mic", "MICBIAS2", + + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", + + "IN2LP:VXRN", "Main Mic", + "IN2LN", "Main Mic", + + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; +}; + +&submic_bias_reg { + regulator-always-on; +}; + +&touchkey_reg { + gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi new file mode 100644 index 000000000000..93ddbd4b0a18 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards + * device tree source + */ + +#include +#include +#include +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + aliases { + mmc0 = &mshc_0; + mmc2 = &sdhci_2; + }; + + chosen { + stdout-path = &serial_1; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204f000 0x1000>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_power_key>; + + power-key { + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power key"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + sound: sound { + compatible = "hardkernel,odroid-xu4-audio"; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&hdmi>, <&max98090>; + }; + }; + + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_rstn>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&camera { + status = "okay"; +}; + +&clock { + clocks = <&clock CLK_XUSBXTI>; + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <45158401>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + + assigned-clock-rates = <0>, <0>, + <196608001>, + <(196608001 / 2)>, + <(196608001 / 8)>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu0_opp_table { + opp-1000000000 { + opp-suspend; + }; + opp-800000000 { + /delete-property/opp-suspend; + }; +}; + +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&pinctrl_1 { + gpio_power_key: power-key-pins { + samsung,pins = "gpx1-3"; + samsung,pin-pud = ; + }; + + max77686_irq: max77686-irq-pins { + samsung,pins = "gpx3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd: hdmi-hpd-pins { + samsung,pins = "gpx3-7"; + samsung,pin-pud = ; + }; + + emmc_rstn: emmc-rstn-pins { + samsung,pins = "gpk1-2"; + samsung,pin-pud = ; + }; +}; + +&ehci { + status = "okay"; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + ddc = <&i2c_2>; + status = "okay"; +}; + +&hdmicec { + status = "okay"; +}; + +&hsotg { + status = "okay"; + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; +}; + +&i2c_0 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + usb3503: usb-hub@8 { + compatible = "smsc,usb3503"; + reg = <0x08>; + + intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; + connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; + wakeup-source; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M1_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDQ_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_MMC2_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDDQ_MMC1_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD10_HDMI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_MIPIHSI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_USB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_HSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "LDO20_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "TFLASH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo22_reg: LDO22 { + /* + * Only U3 uses it, so let it define the + * constraints + */ + regulator-name = "LDO22"; + regulator-boot-on; + }; + + ldo25_reg: LDO25 { + regulator-name = "VDDQ_LCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-microvolt-offset = <50000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDDQ_CKEM1_2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "BUCK6_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "BUCK7_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + /* + * Constraints set by specific board: X, + * X2 and U3. + */ + regulator-name = "BUCK8_2.8V"; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + max98090: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpx0>; + interrupts = <0 IRQ_TYPE_NONE>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2c_2 { + status = "okay"; +}; + +&i2c_8 { + status = "okay"; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; +}; + +&mixer { + status = "okay"; +}; + +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&ldo20_reg>; + mmc-pwrseq = <&emmc_pwrseq>; + status = "okay"; + + broken-cd; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + vqmmc-supply = <&ldo4_reg>; + cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo10_reg>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts new file mode 100644 index 000000000000..42812da1f882 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel's Exynos4412 based ODROID-U3 board device tree source + * + * Copyright (c) 2014 Marek Szyprowski + * + * Device tree source file for Hardkernel's ODROID-U3 board which is based + * on Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include +#include "exynos4412-odroid-common.dtsi" +#include "exynos4412-prime.dtsi" + +/ { + model = "Hardkernel ODROID-U3 board based on Exynos4412"; + compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; + + aliases { + ethernet = ðernet; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x7ff00000>; + }; + + vbus_otg_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VBUS_VDD_5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpl2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + led1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 10000 0>; + #cooling-cells = <2>; + cooling-levels = <0 102 170 230>; + }; +}; + +&adc { + vdd-supply = <&ldo10_reg>; + /* Nothing connected to ADC inputs, keep it disabled */ +}; + +/* Supply for LAN9730/SMSC95xx */ +&buck8_reg { + regulator-name = "BUCK8_P3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, + <&cpu2 9 9>, <&cpu3 9 9>, + <&fan0 1 2>; + }; + map1 { + trip = <&cpu_alert2>; + cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, + <&cpu2 15 15>, <&cpu3 15 15>, + <&fan0 2 3>; + }; + map2 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + }; +}; + +&hdmicec { + needs-hpd; +}; + +/* VDDQ for MSHC (eMMC card) */ +&ldo22_reg { + regulator-name = "LDO22_VDDQ_MMC4_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&mshc_0 { + vqmmc-supply = <&ldo22_reg>; +}; + +&pwm { + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; + status = "okay"; +}; + +&usb3503 { + clock-names = "refclk"; + clocks = <&pmu_system_controller 0>; + refclk-frequency = <24000000>; +}; + +&ehci { + #address-cells = <1>; + #size-cells = <0>; + phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; + phy-names = "hsic0", "hsic1"; + + ethernet: ethernet@2 { + compatible = "usb424,9730"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; +}; + +&hsotg { + dr_mode = "otg"; + vbus-supply = <&vbus_otg_reg>; +}; + +&sound { + model = "Odroid-U3"; + samsung,audio-widgets = + "Headphone", "Headphone Jack", + "Speakers", "Speakers"; + samsung,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; +}; + +&spi_1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts new file mode 100644 index 000000000000..d5316cf2fbb6 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel's Exynos4412 based ODROID-X board device tree source + * + * Copyright (c) 2012 Dongjin Kim + * + * Device tree source file for Hardkernel's ODROID-X board which is based + * on Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include +#include "exynos4412-odroid-common.dtsi" + +/ { + model = "Hardkernel ODROID-X board based on Exynos4412"; + compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; + + aliases { + ethernet = ðernet; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x3ff00000>; + }; + + leds { + compatible = "gpio-leds"; + led1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led2 { + label = "led2:mmc0"; + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "mmc0"; + }; + }; + + regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "p3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adc { + vdd-supply = <&ldo10_reg>; + status = "okay"; +}; + +/* VDDQ for MSHC (eMMC card) */ +&buck8_reg { + regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&ehci { + #address-cells = <1>; + #size-cells = <0>; + phys = <&exynos_usbphy 2>; + phy-names = "hsic0"; + + hub@2 { + compatible = "usb424,3503"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + /* Filled in by a bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&gpio_keys { + pinctrl-0 = <&gpio_power_key &gpio_home_key>; + + home-key { + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + linux,code = ; + label = "home key"; + debounce-interval = <10>; + wakeup-source; + }; +}; + +&hsotg { + dr_mode = "peripheral"; +}; + +&mshc_0 { + vqmmc-supply = <&buck8_reg>; +}; + +&pinctrl_1 { + gpio_home_key: home-key-pins { + samsung,pins = "gpx2-2"; + samsung,pin-pud = ; + }; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&sound { + model = "Odroid-X"; + samsung,audio-widgets = + "Headphone", "Headphone Jack", + "Microphone", "Mic Jack", + "Microphone", "DMIC"; + samsung,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "IN1", "Mic Jack", + "Mic Jack", "MICBIAS"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts new file mode 100644 index 000000000000..7be4cbdc4413 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel's Exynos4412 based ODROID-X2 board device tree source + * + * Copyright (c) 2012 Dongjin Kim + * + * Device tree source file for Hardkernel's ODROID-X2 board which is based + * on Samsung's Exynos4412 SoC. + */ + +#include "exynos4412-odroidx.dts" +#include "exynos4412-prime.dtsi" + +/ { + model = "Hardkernel ODROID-X2 board based on Exynos4412"; + compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x7ff00000>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-origen.dts b/arch/arm/boot/dts/samsung/exynos4412-origen.dts new file mode 100644 index 000000000000..23b151645d66 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-origen.dts @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Insignal's Exynos4412 based Origen board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Insignal's Origen board which is based on + * Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include +#include +#include +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4412"; + compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + mmc0 = &mshc_0; + mmc1 = &sdhci_2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + firmware@203f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203f000 0x1000>; + }; + + mmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <47500000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <64>; + hback-porch = <16>; + hsync-len = <48>; + vback-porch = <64>; + vfront-porch = <16>; + vsync-len = <3>; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&ehci { + samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; + phy-names = "hsic0", "hsic1"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + + s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, + <&gpx2 4 GPIO_ACTIVE_HIGH>, + <&gpx2 5 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, + <&gpm3 6 GPIO_ACTIVE_HIGH>, + <&gpm3 7 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + wakeup-source; + + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", "s5m8767_cp", + "s5m8767_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDIOAP_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD18_2M"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD10_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD33_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD18_MIPI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_UOTG"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDIOPERI_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB02"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_USH"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDIOAP_MMC012_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo18_reg: LDO18 { + regulator-name = "VDDIOPERI_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo19_reg: LDO19 { + regulator-name = "DVDD25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD28_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD28_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo22_reg: LDO22 { + regulator-name = "VDDA28_2M"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD28_TF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD33_A31"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD18_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD18_A31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo27_reg: LDO27 { + regulator-name = "GPS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo28_reg: LDO28 { + regulator-name = "DVDD12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_M12"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD12_5M"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck9_reg: BUCK9 { + regulator-name = "VDDF28_EMMC"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + }; + }; +}; + +&keypad { + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <2>; + linux,keypad-no-autorepeat; + wakeup-source; + pinctrl-0 = <&keypad_rows &keypad_cols>; + pinctrl-names = "default"; + status = "okay"; + + key-home { + keypad,row = <0>; + keypad,column = <0>; + linux,code = ; + }; + + key-down { + keypad,row = <0>; + keypad,column = <1>; + linux,code = ; + }; + + key-up { + keypad,row = <1>; + keypad,column = <0>; + linux,code = ; + }; + + key-menu { + keypad,row = <1>; + keypad,column = <1>; + linux,code = ; + }; + + key-back { + keypad,row = <2>; + keypad,column = <0>; + linux,code = ; + }; + + key-enter { + keypad,row = <2>; + keypad,column = <1>; + linux,code = ; + }; +}; + +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + + broken-cd; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&pinctrl_1 { + keypad_rows: keypad-rows-pins { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_cols: keypad-cols-pins { + samsung,pins = "gpx1-0", "gpx1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts b/arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts new file mode 100644 index 000000000000..0932ec5866cc --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Galaxy Note 10.1 - N801x (wifi only version) + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412-p4note.dtsi" + +/ { + model = "Samsung Galaxy Note 10.1 (GT-N8010/N8013) based on Exynos4412"; + compatible = "samsung,n8010", "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; + chassis-type = "tablet"; + + /* this is the base variant without any kind of modem */ +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi new file mode 100644 index 000000000000..0b89d5682f85 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi @@ -0,0 +1,1229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based p4note device family base DT. + * Based on exynos4412-midas.dtsi. + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include +#include +#include +#include +#include "exynos-pinctrl.h" + +/ { + compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + mmc0 = &mshc_0; + mmc2 = &sdhci_2; + mmc3 = &sdhci_3; + }; + + chosen { + stdout-path = &serial_2; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204f000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-down { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + key-up { + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO1"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_1>; + gpios = <&gpm4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO2"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_2>; + gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO3"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_3>; + gpios = <&gpb 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-always-on; + }; + + panel_vdd: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "LCD_ENABLE"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable>; + gpios = <&gpc0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&wifi_reset>; + pinctrl-names = "default"; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; + + battery_cell: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + constant-charge-current-max-microamp = <2200000>; + precharge-current-microamp = <250000>; + charge-term-current-microamp = <250000>; + constant-charge-voltage-max-microvolt = <4200000>; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + pinctrl-0 = <&ak8975_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpm4>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuel-gauge@36 { + compatible = "maxim,max17042"; + reg = <0x36>; + pinctrl-0 = <&fuel_alert_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4300>; + }; + }; + + i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + adc@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + pinctrl-0 = <&stmpe_adc_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpx0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + st,adc-freq = <3>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,sample-time = <3>; + + adc { + compatible = "st,stmpe-adc"; + #io-channel-cells = <1>; + st,norequest-mask = <0x2f>; + }; + }; + }; + + i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + power_supply: charger@6 { + compatible = "summit,smb347"; + reg = <0x6>; + summit,enable-usb-charging; + summit,enable-charge-control = ; + summit,fast-voltage-threshold-microvolt = <2600000>; + summit,chip-temperature-threshold-celsius = <130>; + summit,usb-current-limit-microamp = <1800000>; + + monitored-battery = <&battery_cell>; + }; + }; + + panel { + compatible = "samsung,ltl101al01"; + pinctrl-0 = <&lvds_nshdn>; + pinctrl-names = "default"; + power-supply = <&panel_vdd>; + enable-gpios = <&gpm0 5 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-0 = <&led_bl_reset>; + pinctrl-names = "default"; + enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>; + power-supply = <&panel_vdd>; + pwms = <&pwm 1 78770 0>; + brightness-levels = <0 48 128 255>; + num-interpolated-steps = <8>; + default-brightness-level = <12>; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + /* not verified */ + status = "okay"; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + samsung,invert-vclk; + + port@3 { + reg = <3>; + + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hsotg { + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-0 = <&tsp_rst &tsp_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpm0 4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; + wakeup-source; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-always-on; + }; + + /* WM8994 audio */ + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "ldo7"; + regulator-always-on; + }; + + /* CSI IP block */ + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* IR LED on/off */ + ldo9_reg: LDO9 { + regulator-name = "VLED_IC_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* CSI IP block */ + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VABB1_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* USB OTG */ + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* not connected */ + ldo13_reg: LDO13 { + regulator-name = "ldo13"; + }; + + ldo14_reg: LDO14 { + regulator-name = "VABB2_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "ldo15"; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "ldo16"; + regulator-always-on; + }; + + /* not connected */ + ldo17_reg: LDO17 { + regulator-name = "ldo17"; + }; + + /* Camera ISX012 */ + ldo18_reg: LDO18 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera S5K6A3 */ + ldo19_reg: LDO19 { + regulator-name = "VT_CORE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* not connected */ + ldo20_reg: LDO20 { + regulator-name = "ldo20"; + }; + + /* MMC2 */ + ldo21_reg: LDO21 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; + }; + + /* not connected */ + ldo22_reg: LDO22 { + regulator-name = "ldo22"; + }; + + /* ADC */ + ldo23_reg: LDO23 { + regulator-name = "VDD_ADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera S5K6A3 */ + ldo24_reg: LDO24 { + regulator-name = "CAM_A2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "VLED_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera ISX012 */ + ldo26_reg: LDO26 { + regulator-name = "3MP_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1075000>; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-always-on; + }; + + /* not connected */ + buck8_reg: BUCK8 { + regulator-name = "buck8"; + }; + + buck9_reg: BUCK9 { + regulator-name = "3MP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mshc_0 { + broken-cd; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + mmc-ddr-1_8v; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + status = "okay"; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + tsp_reg_gpio_2: tsp-reg-gpio-2-pins { + samsung,pins = "gpb-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_reg_gpio_3: tsp-reg-gpio-3-pins { + samsung,pins = "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lcd_enable: lcd-enable-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, NONE); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, UP); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, UP); + PIN_SLP(gpc1-1, PREV, NONE); + PIN_SLP(gpc1-2, INPUT, UP); + PIN_SLP(gpc1-3, INPUT, UP); + PIN_SLP(gpc1-4, INPUT, UP); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, OUT0, NONE); + PIN_SLP(gpf3-5, OUT0, NONE); + + PIN_SLP(gpj0-0, INPUT, DOWN); + PIN_SLP(gpj0-1, INPUT, DOWN); + PIN_SLP(gpj0-2, INPUT, DOWN); + PIN_SLP(gpj0-3, PREV, NONE); + PIN_SLP(gpj0-4, PREV, NONE); + PIN_SLP(gpj0-5, OUT0, NONE); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, OUT0, NONE); + + PIN_SLP(gpj1-0, OUT0, NONE); + PIN_SLP(gpj1-1, INPUT, DOWN); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, OUT0, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sd3_wifi: sd3-wifi-pins { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_shutdown: bt-shutdown-pins { + samsung,pins = "gpl0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart_sel: uart-sel-pins { + samsung,pins = "gpl2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + /* 0 = CP, 1 = AP (serial output) */ + }; + + led_bl_reset: led-bl-reset-pins { + samsung,pins = "gpm0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_rst: tsp-rst-pins { + samsung,pins = "gpm0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lvds_nshdn: lvds-nshdn-pins { + samsung,pins = "gpm0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_irq: tsp-irq-pins { + samsung,pins = "gpm2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_reset: wifi-reset-pins { + samsung,pins = "gpm3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_reg_gpio_1: tsp-reg-gpio-1-pins { + samsung,pins = "gpm4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ak8975_irq: ak8975-irq-pins { + samsung,pins = "gpm4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + stmpe_adc_irq: stmpe-adc-irq-pins { + samsung,pins = "gpx0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max77686_irq: max77686-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + gpio_keys: gpio-keys-pins { + samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; + samsung,pin-pud = ; + }; + + fuel_alert_irq: fuel-alert-irq-pins { + samsung,pins = "gpx2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_host_wake: wifi-host-wake-pins { + samsung,pins = "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup-pins { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sdhci2_cd: sdhci2-cd-pins { + samsung,pins = "gpx3-4"; + samsung,pin-pud = ; + }; + + sleep1: sleep-state { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, PREV, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, OUT0, NONE); + PIN_SLP(gpl0-1, INPUT, NONE); + PIN_SLP(gpl0-2, INPUT, NONE); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, PREV, NONE); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, OUT0, NONE); + PIN_SLP(gpl1-1, OUT0, NONE); + + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, PREV, NONE); + PIN_SLP(gpl2-7, PREV, NONE); + + PIN_SLP(gpm0-0, PREV, NONE); + PIN_SLP(gpm0-1, OUT0, NONE); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, NONE); + PIN_SLP(gpm0-4, OUT0, NONE); + PIN_SLP(gpm0-5, OUT0, NONE); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, OUT0, NONE); + + PIN_SLP(gpm1-0, INPUT, NONE); + PIN_SLP(gpm1-1, INPUT, NONE); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, OUT0, NONE); + PIN_SLP(gpm2-3, OUT0, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); + PIN_SLP(gpm3-4, OUT0, DOWN); + PIN_SLP(gpm3-5, PREV, NONE); + PIN_SLP(gpm3-6, PREV, NONE); + PIN_SLP(gpm3-7, OUT0, NONE); + + PIN_SLP(gpm4-0, INPUT, NONE); + PIN_SLP(gpm4-1, INPUT, NONE); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, PREV, NONE); + PIN_SLP(gpm4-5, OUT0, NONE); + PIN_SLP(gpm4-6, OUT0, NONE); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, NONE); + PIN_SLP(gpy0-3, INPUT, NONE); + PIN_SLP(gpy0-4, INPUT, NONE); + PIN_SLP(gpy0-5, INPUT, NONE); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-state { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-state { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + PIN_SLP(gpv4-1, INPUT, DOWN); + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&pwm { + pinctrl-0 = <&pwm1_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <1>; + status = "okay"; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + status = "okay"; +}; + +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_wifi>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + + max-speed = <2000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "lpo"; + }; +}; + +&serial_2 { + pinctrl-0 = <&uart_sel>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi new file mode 100644 index 000000000000..7f187a3dedcc --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree sources for Exynos4412 PPMU common device tree + * + * Copyright (C) 2015 Samsung Electronics + * Author: Chanwoo Choi + */ + +&ppmu_dmc0 { + status = "okay"; + + events { + ppmu_dmc0_3: ppmu-event3-dmc0 { + event-name = "ppmu-event3-dmc0"; + }; + }; +}; + +&ppmu_dmc1 { + status = "okay"; + + events { + ppmu_dmc1_3: ppmu-event3-dmc1 { + event-name = "ppmu-event3-dmc1"; + }; + }; +}; + +&ppmu_leftbus { + status = "okay"; + + events { + ppmu_leftbus_3: ppmu-event3-leftbus { + event-name = "ppmu-event3-leftbus"; + }; + }; +}; + +&ppmu_rightbus { + status = "okay"; + + events { + ppmu_rightbus_3: ppmu-event3-rightbus { + event-name = "ppmu-event3-rightbus"; + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-prime.dtsi b/arch/arm/boot/dts/samsung/exynos4412-prime.dtsi new file mode 100644 index 000000000000..3731a225f779 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-prime.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 Prime SoC device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/* + * Exynos4412 Prime SoC revision supports higher CPU frequencies than + * non-Prime version. Therefore we need to update OPPs table and + * thermal maps accordingly. + */ + +&cpu0_opp_1500 { + /delete-property/turbo-mode; +}; + +&cpu0_opp_table { + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + }; +}; + +&cooling_map0 { + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, + <&cpu2 9 9>, <&cpu3 9 9>; +}; + +&cooling_map1 { + cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, + <&cpu2 15 15>, <&cpu3 15 15>; +}; + +&gpu_opp_table { + opp-533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <1075000>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts new file mode 100644 index 000000000000..715dfcba1417 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based SMDK board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's SMDK4412 board which is based on + * Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + model = "Samsung SMDK evaluation board based on Exynos4412"; + compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + mmc0 = &sdhci_2; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial1:115200n8"; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&keypad { + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + wakeup-source; + pinctrl-0 = <&keypad_rows &keypad_cols>; + pinctrl-names = "default"; + status = "okay"; + + key-1 { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <2>; + }; + + key-2 { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <3>; + }; + + key-3 { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <4>; + }; + + key-4 { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <5>; + }; + + key-5 { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <6>; + }; + + key-A { + keypad,row = <2>; + keypad,column = <6>; + linux,code = <30>; + }; + + key-B { + keypad,row = <2>; + keypad,column = <7>; + linux,code = <48>; + }; + + key-C { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <46>; + }; + + key-D { + keypad,row = <2>; + keypad,column = <5>; + linux,code = <32>; + }; + + key-E { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <18>; + }; +}; + +&pinctrl_1 { + keypad_rows: keypad-rows-pins { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_cols: keypad-cols-pins { + samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", + "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts b/arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts new file mode 100644 index 000000000000..5a2dcdc5c28b --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FriendlyARM's Exynos4412 based TINY4412 board device tree source + * + * Copyright (c) 2013 Alex Ling + * + * Device tree source file for FriendlyARM's TINY4412 board which is based on + * Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include +#include + +/ { + model = "FriendlyARM TINY4412 board based on Exynos4412"; + compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; + + aliases { + mmc0 = &sdhci_2; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "led1"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpm4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "led3"; + gpios = <&gpm4 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led4 { + label = "led4"; + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + panel { + compatible = "innolux,at070tn92"; + power-supply = <&vddq_lcd>; + + port { + panel_input: endpoint { + remote-endpoint = <&lcdc_output>; + }; + }; + }; + + vddq_lcd: regulator-vddq-lcd { + compatible = "regulator-fixed"; + regulator-name = "vddq-lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&fimd { + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@3 { + reg = <3>; + lcdc_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-trats2.dts b/arch/arm/boot/dts/samsung/exynos4412-trats2.dts new file mode 100644 index 000000000000..3c2d2a7836da --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412-trats2.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based Trats 2 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Trats 2 board which is based on + * Samsung's Exynos4412 SoC. + */ + +/dts-v1/; +#include "exynos4412-galaxy-s3.dtsi" + +/ { + model = "Samsung Trats 2 based on Exynos4412"; + compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + chassis-type = "handset"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4412.dtsi new file mode 100644 index 000000000000..dcbe0ce6180f --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412.dtsi @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4412", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu2: cpu@a02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa02>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu3: cpu@a03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa03>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + opp-suspend; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + cpu0_opp_1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; + }; + }; +}; + +&clock { + compatible = "samsung,exynos4412-clock"; +}; + +&combiner { + samsung,combiner-nr = <20>; +}; + +&gic { + cpu-offset = <0x4000>; +}; + +&pmu { + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi new file mode 100644 index 000000000000..04935fbe2f2a --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi @@ -0,0 +1,979 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include "exynos-pinctrl.h" + +#define PIN_SLP(_pin, _mode, _pull) \ + pin- ## _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ + } + +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj0: gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_a: uart-audio-a-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_b: uart-audio-b-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ac97_bus: ac97-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpd0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ctrl: lcd-ctrl-pins { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + mipi0_clk: mipi0-clk-pins { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + mipi1_clk: mipi1-clk-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_clk: lcd-clk-pins { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data16: lcd-data-width16-pins { + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data18: lcd-data-width18-pins { + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", + "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data24: lcd-data-width24-pins { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ldi: lcd-ldi-pins { + samsung,pins = "gpf3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_io: cam-port-a-io-pins { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_active: cam-port-a-clk-active-pins { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_clk: sd4-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cmd: sd4-cmd-pins { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cd: sd4-cd-pins { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus1: sd4-bus-width1-pins { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus4: sd4-bus-width4-pins { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus8: sd4-bus-width8-pins { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpk1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpk1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpk1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpk1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpk2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpk2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpk2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpk2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus8: sd2-bus-width8-pins { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_clk: sd3-clk-pins { + samsung,pins = "gpk3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cmd: sd3-cmd-pins { + samsung,pins = "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cd: sd3-cd-pins { + samsung,pins = "gpk3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus1: sd3-bus-width1-pins { + samsung,pins = "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus4: sd3-bus-width4-pins { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_io: cam-port-b-io-pins { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_active: cam-port-b-clk-active-pins { + samsung,pins = "gpm2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { + samsung,pins = "gpm2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint0: ext-int0-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint8: ext-int8-pins { + samsung,pins = "gpx1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint15: ext-int15-pins { + samsung,pins = "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint16: ext-int16-pins { + samsung,pins = "gpx2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint31: ext-int31-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_i2c0: fimc-is-i2c0-pins { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_i2c1: fimc-is-i2c1-pins { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_uart: fimc-is-uart-pins { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_cec: hdmi-cec-pins { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpz: gpz-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm0_bus: pcm0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_3 { + gpv0: gpv0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + c2c_bus: c2c-bus-pins { + samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", + "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", + "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", + "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", + "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", + "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", + "gpv4-0", "gpv4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4x12.dtsi b/arch/arm/boot/dts/samsung/exynos4x12.dtsi new file mode 100644 index 000000000000..84c1db221c98 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4x12.dtsi @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoC series device nodes are listed in this file. + * Particular SoCs from Exynos4x12 series can include this file and provide + * values for SoCs specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4x12 SoCs. As device tree coverage for Exynos4x12 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4.dtsi" + +#include "exynos4-cpu-thermal.dtsi" + +/ { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + fimc-lite0 = &fimc_lite_0; + fimc-lite1 = &fimc_lite_1; + }; + + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + }; + + bus_c2c: bus-c2c { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_C2C>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <900000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <900000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-suspend; + }; + }; + + bus_leftbus_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + }; + + soc: soc { + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_2: pinctrl@3860000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; + }; + + pinctrl_3: pinctrl@106e0000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106e0000 0x1000>; + interrupts = ; + }; + + sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + + pd_isp: power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023ca0 0x20>; + #power-domain-cells = <0>; + label = "ISP"; + }; + + l2c: cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + + clock: clock-controller@10030000 { + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + + timer@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&combiner 12 5>, + <&combiner 12 6>, + <&combiner 12 7>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@10060000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + adc: adc@126c0000 { + compatible = "samsung,exynos4212-adc"; + reg = <0x126c0000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <10 3>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + g2d: g2d@10800000 { + compatible = "samsung,exynos4212-g2d"; + reg = <0x10800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + iommus = <&sysmmu_g2d>; + }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + sysmmu_g2d: sysmmu@10a40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10a40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_isp: sysmmu@12260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 2>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_drc: sysmmu@12270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 3>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_fd: sysmmu@122a0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122a0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 4>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_mcuctl: sysmmu@122b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 5>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite0: sysmmu@123b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite1: sysmmu@123c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123c0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 1>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; + #iommu-cells = <0>; + }; + }; +}; + +&combiner { + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&camera { + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + /* fimc_[0-3] are configured outside, under phandles */ + fimc_lite_0: fimc-lite@12390000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x12390000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite0>; + status = "disabled"; + }; + + fimc_lite_1: fimc-lite@123a0000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x123a0000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite1>; + status = "disabled"; + }; + + fimc_is: fimc-is@12000000 { + compatible = "samsung,exynos4212-fimc-is"; + reg = <0x12000000 0x260000>; + interrupts = , + ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, + <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>, + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; + clock-names = "lite0", "lite1", "ppmuispx", + "ppmuispmx", "isp", + "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", + "ispdiv0", "ispdiv1", "mcuispdiv0", + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; + iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, + <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; + iommu-names = "isp", "drc", "fd", "mcuctl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pmu@10020000 { + reg = <0x10020000 0x3000>; + }; + + i2c1_isp: i2c-isp@12140000 { + compatible = "samsung,exynos4212-i2c-isp"; + reg = <0x12140000 0x100>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; + clock-names = "i2c_isp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&exynos_usbphy { + compatible = "samsung,exynos4x12-usb2-phy"; + samsung,sysreg-phandle = <&sys_reg>; +}; + +&fimc_0 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_1 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_2 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; + samsung,cam-if; +}; + +&fimc_3 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; +}; + +&gpu { + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <875000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <900000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <950000>; + }; + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-microvolt = <1025000>; + }; + }; +}; + +&hdmi { + compatible = "samsung,exynos4212-hdmi"; +}; + +&jpeg_codec { + compatible = "samsung,exynos4212-jpeg"; +}; + +&rotator { + compatible = "samsung,exynos4212-rotator"; +}; + +&mixer { + compatible = "samsung,exynos4212-mixer"; + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; + interconnects = <&bus_display &bus_dmc>; +}; + +&pmu_system_controller { + clock-names = "clkout0", "clkout1", "clkout2", "clkout3", + "clkout4", "clkout8", "clkout9"; + clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, + <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, + <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; + #clock-cells = <1>; +}; + +&tmu { + compatible = "samsung,exynos4412-tmu"; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + reg = <0x100c0000 0x100>; + clocks = <&clock CLK_TMU_APBIF>; + clock-names = "tmu_apbif"; + status = "disabled"; +}; + +#include "exynos4x12-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5.dtsi b/arch/arm/boot/dts/samsung/exynos5.dtsi new file mode 100644 index 000000000000..4a17a19586bb --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5 SoC series common device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular + * SoCs from Exynos5 series can include this file and provide values for SoCs + * specific bindings. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + serial3 = &serial_3; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sromc: memory-controller@12250000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12250000 0x14>; + }; + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = ; + }; + + sysreg_system_controller: syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; + + serial_0: serial@12c00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c00000 0x100>; + interrupts = ; + }; + + serial_1: serial@12c10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c10000 0x100>; + interrupts = ; + }; + + serial_2: serial@12c20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c20000 0x100>; + interrupts = ; + }; + + serial_3: serial@12c30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c30000 0x100>; + interrupts = ; + }; + + i2c_0: i2c@12c60000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12c60000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_1: i2c@12c70000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12c70000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_2: i2c@12c80000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12c80000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_3: i2c@12c90000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12c90000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + interrupts = , + , + , + , + ; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + }; + + rtc: rtc@101e0000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x101e0000 0x100>; + interrupts = , + ; + status = "disabled"; + }; + + fimd: fimd@14400000 { + compatible = "samsung,exynos5250-fimd"; + interrupt-parent = <&combiner>; + reg = <0x14400000 0x40000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <18 4>, <18 5>, <18 6>; + samsung,sysreg = <&sysreg_system_controller>; + status = "disabled"; + }; + + dp: dp-controller@145b0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x1000>; + interrupts = <10 3>; + interrupt-parent = <&combiner>; + status = "disabled"; + }; + + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = ; + }; + + prng: rng@10830400 { + compatible = "samsung,exynos5250-prng"; + reg = <0x10830400 0x200>; + }; + + trng: rng@10830600 { + compatible = "samsung,exynos5250-trng"; + reg = <0x10830600 0x100>; + }; + + g2d: g2d@10850000 { + compatible = "samsung,exynos5250-g2d"; + reg = <0x10850000 0x1000>; + interrupts = ; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5250-arndale.dts b/arch/arm/boot/dts/samsung/exynos5250-arndale.dts new file mode 100644 index 000000000000..d586189966da --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-arndale.dts @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5250 based Arndale board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "exynos5250.dtsi" + +/ { + model = "Insignal Arndale evaluation board based on Exynos5250"; + compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-menu { + label = "SW-TACT2"; + gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-home { + label = "SW-TACT3"; + gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-up { + label = "SW-TACT4"; + gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-down { + label = "SW-TACT5"; + gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-back { + label = "SW-TACT6"; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-wakeup { + label = "SW-TACT7"; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + /* + * For unknown reasons HDMI-DDC does not work with Exynos I2C + * controllers. Lets use software I2C over GPIO pins as a workaround. + */ + i2c_ddc: i2c-10 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_gpio_bus>; + sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + }; + + panel: panel { + compatible = "boe,hv070wsa-100"; + power-supply = <&vcc_3v3_reg>; + enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; + port { + panel_ep: endpoint { + remote-endpoint = <&bridge_out_ep>; + }; + }; + }; + + main_dc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "MAIN_DC"; + regulator-always-on; + }; + + mmc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_MMC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + reg_hdmi_en: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-en"; + regulator-always-on; + }; + + vcc_1v2_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_1v8_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_3v3_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "samsung,arndale-wm1811"; + samsung,audio-cpu = <&i2s0>; + samsung,audio-codec = <&wm1811>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; + + // SMSC USB3503 connected in hardware only mode as a PHY + usb_hub: usb-hub { + compatible = "smsc,usb3503a"; + + reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&clock { + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <49152000>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&dsi_0 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + samsung,pll-clock-frequency = <24000000>; + samsung,burst-clock-frequency = <320000000>; + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + bridge@0 { + reg = <0>; + compatible = "toshiba,tc358764"; + vddc-supply = <&vcc_1v2_reg>; + vddio-supply = <&vcc_1v8_reg>; + vddlvds-supply = <&vcc_3v3_reg>; + reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + bridge_out_ep: endpoint { + remote-endpoint = <&panel_ep>; + }; + }; + }; + }; +}; + +&fimd { + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + status = "okay"; + ddc = <&i2c_ddc>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + samsung,i2c-slave-addr = <0x66>; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq>; + wakeup-source; + + vinb1-supply = <&main_dc_reg>; + vinb2-supply = <&main_dc_reg>; + vinb3-supply = <&main_dc_reg>; + vinb4-supply = <&main_dc_reg>; + vinb5-supply = <&main_dc_reg>; + vinb6-supply = <&main_dc_reg>; + vinb7-supply = <&main_dc_reg>; + vinb8-supply = <&main_dc_reg>; + vinb9-supply = <&main_dc_reg>; + + vinl1-supply = <&buck7_reg>; + vinl2-supply = <&buck7_reg>; + vinl3-supply = <&buck7_reg>; + vinl4-supply = <&main_dc_reg>; + vinl5-supply = <&main_dc_reg>; + vinl6-supply = <&main_dc_reg>; + vinl7-supply = <&main_dc_reg>; + vinl8-supply = <&buck8_reg>; + vinl9-supply = <&buck8_reg>; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, + <&gpd1 1 GPIO_ACTIVE_HIGH>, + <&gpd1 2 GPIO_ACTIVE_HIGH>; + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, + <&gpx2 4 GPIO_ACTIVE_HIGH>, + <&gpx2 5 GPIO_ACTIVE_HIGH>; + + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", "unused1", "unused2"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_28IO_DP_1.35V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_COMMON1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_IOPERI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_XPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_COMMON2_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_33ON_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD_COMMON3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_ABB2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_COMMON4_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDQ_MMC2_3_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_33ON_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo22_reg: LDO22 { + regulator-name = "EXT_33_OFF"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo23_reg: LDO23 { + regulator-name = "EXT_28_OFF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo25_reg: LDO25 { + regulator-name = "PVDD_LDO25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + }; + + ldo26_reg: LDO26 { + regulator-name = "EXT_18_OFF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1.35V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1355000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck7_reg: BUCK7 { + regulator-name = "PVDD_BUCK7"; + regulator-always-on; + op_mode = <1>; + }; + + buck8_reg: BUCK8 { + regulator-name = "PVDD_BUCK8"; + regulator-always-on; + op_mode = <1>; + }; + + buck9_reg: BUCK9 { + regulator-name = "VDD_33_OFF_EXT1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + wm1811: audio-codec@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + clock-names = "MCLK1"; + + AVDD2-supply = <&main_dc_reg>; + CPVDD-supply = <&main_dc_reg>; + DBVDD1-supply = <&main_dc_reg>; + DBVDD2-supply = <&main_dc_reg>; + DBVDD3-supply = <&main_dc_reg>; + LDO1VDD-supply = <&main_dc_reg>; + SPKVDD1-supply = <&main_dc_reg>; + SPKVDD2-supply = <&main_dc_reg>; + + wlf,ldo1ena-gpios = <&gpb0 0 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpb0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_8 { + status = "okay"; + /* used by HDMI PHY */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_9 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; +}; + +&i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; + status = "okay"; +}; + +&i2s0_bus { + samsung,pin-drv = ; +}; + +&mali { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; +}; + +&pinctrl_0 { + s5m8767_irq: s5m8767-irq-pins { + samsung,pins = "gpx3-2"; + samsung,pin-pud = ; + }; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +}; + +&sata_phy_i2c { + status = "okay"; +}; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi new file mode 100644 index 000000000000..d956540a2d88 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi @@ -0,0 +1,833 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include "exynos-pinctrl.h" + +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_hs_bus: i2c2-hs-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_gpio_bus: i2c2-gpio-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_hs_bus: i2c3-hs-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ac97_bus: ac97-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpb2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpb2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpb2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_hs_bus: i2c0-hs-bus-pins { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_hs_bus: i2c1-hs-bus-pins { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpc0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpc2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpc2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpc3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpc3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpc3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpc3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus8: sd2-bus-width8-pins { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_clk: sd3-clk-pins { + samsung,pins = "gpc4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cmd: sd3-cmd-pins { + samsung,pins = "gpc4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cd: sd3-cd-pins { + samsung,pins = "gpc4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus1: sd3-bus-width1-pins { + samsung,pins = "gpc4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus4: sd3-bus-width4-pins { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + dp_hpd: dp-hpd-pins { + samsung,pins = "gpx0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_cec: hdmi-cec-pins { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd: hdmi-hpd-pins { + samsung,pins = "gpx3-7"; + samsung,pin-pud = ; + }; +}; + +&pinctrl_1 { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + cam_gpio_a: cam-gpio-a-pins { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_gpio_b: cam-gpio-b-pins { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c2_bus: cam-i2c2-bus-pins { + samsung,pins = "gpe0-6", "gpe1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_spi1_bus: cam-spi1-bus-pins { + samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c1_bus: cam-i2c1-bus-pins { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c0_bus: cam-i2c0-bus-pins { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_spi0_bus: cam-spi0-bus-pins { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_bayrgb_bus: cam-bayrgb-bus-pins { + samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", + "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", + "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", + "gpg2-0", "gpg2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a: cam-port-a-pins { + samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", + "gph1-0", "gph1-1", "gph1-2", "gph1-3", + "gph1-4", "gph1-5", "gph1-6", "gph1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpv0: gpv0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + c2c_rxd: c2c-rxd-pins { + samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", + "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", + "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + c2c_txd: c2c-txd-pins { + samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", + "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", + "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_3 { + gpz: gpz-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts new file mode 100644 index 000000000000..bb623726ef1e --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung SMDK5250 board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include +#include +#include +#include "exynos5250.dtsi" + +/ { + model = "Samsung SMDK5250 board based on Exynos5250"; + compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; + stdout-path = "serial2:115200n8"; + }; + + vdd: fixed-regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + dbvdd: fixed-regulator-dbvdd { + compatible = "regulator-fixed"; + regulator-name = "dbvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + spkvdd: fixed-regulator-spkvdd { + compatible = "regulator-fixed"; + regulator-name = "spkvdd-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound { + compatible = "samsung,smdk-wm8994"; + + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&wm8994>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + + codec_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16934000>; + }; + }; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&dp { + samsung,color-space = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing { + /* 1280x800 */ + clock-frequency = <50000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <4>; + hback-porch = <4>; + hsync-len = <4>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <4>; + }; + }; +}; + +&ehci { + samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; +}; + +&hdmi { + status = "okay"; + ddc = <&i2c_2>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + + eeprom@50 { + compatible = "samsung,s524ad0xd1", "atmel,24c128"; + reg = <0x50>; + }; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + reg = <0x09>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; + #clock-cells = <1>; + wakeup-source; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "P1.2V_LDO_OUT2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "P2.8V_LDO_OUT4"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "P1.8V_LDO_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "P1.1V_LDO_OUT6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + + eeprom@51 { + compatible = "samsung,s524ad0xd1", "atmel,24c128"; + reg = <0x51>; + }; + + wm8994: audio-codec@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&codec_mclk>; + clock-names = "MCLK1"; + + AVDD2-supply = <&vdd>; + CPVDD-supply = <&vdd>; + DBVDD-supply = <&dbvdd>; + SPKVDD1-supply = <&spkvdd>; + SPKVDD2-supply = <&spkvdd>; + }; +}; + +&i2c_2 { + status = "okay"; + /* used by HDMI DDC */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_8 { + status = "okay"; + /* used by HDMI PHY */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_9 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; +}; + +&i2s0 { + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +}; + +&sata_phy_i2c { + status = "okay"; +}; + +&spi_1 { + status = "okay"; + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25x80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; +}; + +&pinctrl_0 { + max77686_irq: max77686-irq-pins { + samsung,pins = "gpx3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi new file mode 100644 index 000000000000..c82e2762e07c --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Snow board device tree source + * + * Copyright (c) 2012 Google, Inc + */ + +#include +#include +#include +#include +#include +#include "exynos5250.dtsi" + +/ { + aliases { + i2c104 = &i2c_104; + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_2; /* SD */ + mmc2 = &mmc_3; /* WiFi */ + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq &lid_irq>; + + power-key { + label = "Power"; + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + wakeup-source; + }; + }; + + vbat: vbat-fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat-supply"; + regulator-boot-on; + }; + + i2c-arbitrator { + compatible = "i2c-arb-gpio-challenge"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c_4>; + + our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; + their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; + slew-delay-us = <10>; + wait-retry-us = <3000>; + wait-free-us = <50000>; + + pinctrl-names = "default"; + pinctrl-0 = <&arb_our_claim &arb_their_claim>; + + /* Use ID 104 as a hint that we're on physical bus 4 */ + i2c_104: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + }; + + cros_ec: embedded-controller@1e { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_irq>; + wakeup-source; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + /* + * Config irq to disable internal pulls + * even though we run in polling mode. + */ + pinctrl-names = "default"; + pinctrl-0 = <&tps65090_irq>; + + vsys1-supply = <&vbat>; + vsys2-supply = <&vbat>; + vsys3-supply = <&vbat>; + infet1-supply = <&vbat>; + infet2-supply = <&vbat>; + infet3-supply = <&vbat>; + infet4-supply = <&vbat>; + infet5-supply = <&vbat>; + infet6-supply = <&vbat>; + infet7-supply = <&vbat>; + vsys-l1-supply = <&vbat>; + vsys-l2-supply = <&vbat>; + + regulators { + dcdc1 { + ti,enable-ext-control; + }; + dcdc2 { + ti,enable-ext-control; + }; + dcdc3 { + ti,enable-ext-control; + }; + fet1: fet1 { + regulator-name = "vcd_led"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet4 { + regulator-name = "sdcard"; + ti,overcurrent-wait = <3>; + }; + fet5 { + regulator-name = "camout"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet6: fet6 { + regulator-name = "lcd_vdd"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + ldo1 { + }; + ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; + + sound { + samsung,i2s-controller = <&i2s0>; + }; + + usb3_vbus_reg: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_en>; + enable-active-high; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; + power-supply = <&fet1>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; + + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + mmc3_pwrseq: mmc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ + <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; +}; + +&clock { + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <49152000>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; + + ports { + port { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&ehci { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + status = "okay"; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&hdmicec { + status = "okay"; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; + wakeup-source; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "P1.8V_LDO_OUT2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.35V_BUCK_OUT6"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "P2.0V_BUCK_OUT7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "P2.85V_BUCK_OUT8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + trackpad@67 { + reg = <0x67>; + compatible = "cypress,cyapa"; + interrupts = <2 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + wakeup-source; + }; +}; + +/* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ +&i2c2_bus { + samsung,pin-pud = ; +}; + +&i2c_2 { + status = "okay"; + /* used by HDMI DDC */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + ptn3460: lvds-bridge@20 { + compatible = "nxp,ptn3460"; + reg = <0x20>; + powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; + edid-emulation = <5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; +}; + +&i2c_8 { + status = "okay"; + /* used by HDMI PHY */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; +}; + +&i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; + status = "okay"; +}; + +&mali { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +/* eMMC flash */ +&mmc_0 { + status = "okay"; + non-removable; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; +}; + +/* uSD card */ +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; + cap-sd-highspeed; +}; + +/* + * On Snow we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + * + * WiFi SDIO module + */ +&mmc_3 { + status = "okay"; + non-removable; + cap-sdio-irq; + keep-power-in-suspend; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc3_pwrseq>; +}; + +&pinctrl_0 { + wifi_en: wifi-en-pins { + samsung,pins = "gpx0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wifi_rst: wifi-rst-pins { + samsung,pins = "gpx0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + power_key_irq: power-key-irq-pins { + samsung,pins = "gpx1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ec_irq: ec-irq-pins { + samsung,pins = "gpx1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + tps65090_irq: tps65090-irq-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_vbus_en: usb3-vbus-en-pins { + samsung,pins = "gpx2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + max77686_irq: max77686-irq-pins { + samsung,pins = "gpx3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lid_irq: lid-irq-pins { + samsung,pins = "gpx3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + arb_their_claim: arb-their-claim-pins { + samsung,pins = "gpe0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + arb_our_claim: arb-our-claim-pins { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sd3_bus4 { + samsung,pin-drv = ; +}; + +&sd3_clk { + samsung,pin-drv = ; +}; + +&sd3_cmd { + samsung,pin-pud = ; + samsung,pin-drv = ; +}; + +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; +}; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; +}; + +&usbdrd_phy { + vbus-supply = <&usb3_vbus_reg>; +}; + +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts new file mode 100644 index 000000000000..3d32c3476e84 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Snow Rev 5+ board device tree source + * + * Copyright (c) 2012 Google, Inc + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5250-snow-common.dtsi" + +/ { + model = "Google Snow Rev 5+"; + compatible = "google,snow-rev5", "samsung,exynos5250", + "samsung,exynos5"; + chassis-type = "laptop"; + + sound { + compatible = "google,snow-audio-max98090"; + + samsung,model = "Snow-I2S-MAX98090"; + samsung,audio-codec = <&max98090>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98090>, <&hdmi>; + }; + }; +}; + +&i2c_7 { + max98090: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupts = <4 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98090_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&pinctrl_0 { + max98090_irq: max98090-irq-pins { + samsung,pins = "gpx0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5250-snow.dts b/arch/arm/boot/dts/samsung/exynos5250-snow.dts new file mode 100644 index 000000000000..906aa7aae710 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-snow.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Snow board device tree source + * + * Copyright (c) 2012 Google, Inc + */ + +/dts-v1/; +#include "exynos5250-snow-common.dtsi" + +/ { + model = "Google Snow"; + compatible = "google,snow-rev4", "google,snow", "samsung,exynos5250", + "samsung,exynos5"; + chassis-type = "laptop"; + + sound { + compatible = "google,snow-audio-max98095"; + + samsung,model = "Snow-I2S-MAX98095"; + samsung,audio-codec = <&max98095>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98095 0>, <&hdmi>; + }; + }; +}; + +&i2c_7 { + max98095: audio-codec@11 { + compatible = "maxim,max98095"; + reg = <0x11>; + pinctrl-names = "default"; + pinctrl-0 = <&max98095_en>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; + #sound-dai-cells = <1>; + }; +}; + +&pinctrl_0 { + max98095_en: max98095-en-pins { + samsung,pins = "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5250-spring.dts b/arch/arm/boot/dts/samsung/exynos5250-spring.dts new file mode 100644 index 000000000000..d126fccdcaf3 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-spring.dts @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Spring board device tree source + * + * Copyright (c) 2013 Google, Inc + * Copyright (c) 2014 SUSE LINUX Products GmbH + */ + +/dts-v1/; +#include +#include +#include +#include +#include "exynos5250.dtsi" + +/ { + model = "Google Spring"; + compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; + chassis-type = "laptop"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_1; + }; + + chosen { + bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq>, <&lid_irq>; + + power-key { + label = "Power"; + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + wakeup-source; + }; + }; + + usb-hub { + compatible = "smsc,usb3503a"; + reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hsic_reset>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <1>; + hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; +}; + +&ehci { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + status = "okay"; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; + hdmi-en-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ + + /* + * The following arrays of DVS voltages are not used, since we are + * not using GPIOs to control PMIC bucks, but they must be defined + * to please the driver. + */ + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", + "en32khz_cp", + "en32khz_bt"; + }; + + regulators { + ldo4_reg: LDO4 { + regulator-name = "P1.0V_LDO_OUT4"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo5_reg: LDO5 { + regulator-name = "P1.0V_LDO_OUT5"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_mydp"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo17_reg: LDO17 { + regulator-name = "P2.8V_LDO_OUT17"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo25_reg: LDO25 { + regulator-name = "vdd_bridge"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + op_mode = <3>; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.2V_BUCK_OUT6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <0>; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_ummc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = ; + wakeup-source; + }; +}; + +/* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ +&i2c2_bus { + samsung,pin-pud = ; +}; + +&i2c_2 { + status = "okay"; + /* used by HDMI DDC */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + cros_ec: embedded-controller@1e { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&ec_irq>; + }; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + temperature-sensor@4c { + compatible = "gmt,g781"; + reg = <0x4c>; + }; +}; + +&i2c_8 { + status = "okay"; + /* used by HDMI PHY */ + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; +}; + +&i2s0 { + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; +}; + +/* + * On Spring we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + */ +&mmc_1 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; + bus-width = <4>; + cap-sd-highspeed; +}; + +&pinctrl_0 { + s5m8767_dvs: s5m8767-dvs-pins { + samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + dp_hpd_gpio: dp-hpd-pins { + samsung,pins = "gpc3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + trackpad_irq: trackpad-irq-pins { + samsung,pins = "gpx1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + power_key_irq: power-key-irq-pins { + samsung,pins = "gpx1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ec_irq: ec-irq-pins { + samsung,pins = "gpx1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + s5m8767_ds: s5m8767-ds-pins { + samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + s5m8767_irq: s5m8767-irq-pins { + samsung,pins = "gpx3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lid_irq: lid-irq-pins { + samsung,pins = "gpx3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + hsic_reset: hsic-reset-pins { + samsung,pins = "gpe1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sd1_bus4 { + samsung,pin-drv = ; +}; + +&sd1_cd { + samsung,pin-drv = ; +}; + +&sd1_clk { + samsung,pin-drv = ; +}; + +&sd1_cmd { + samsung,pin-pud = ; + samsung,pin-drv = ; +}; + +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; +}; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi new file mode 100644 index 000000000000..99c84bebf25a --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5250 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung Exynos5250 SoC device nodes are listed in this file. + * Exynos5250 based board files can include this file and provide + * values for board specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, + * additional nodes can be added to this file. + */ + +#include +#include "exynos5.dtsi" +#include "exynos4-cpu-thermal.dtsi" +#include + +/ { + compatible = "samsung,exynos5250", "samsung,exynos5"; + + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + gsc0 = &gsc_0; + gsc1 = &gsc_1; + gsc2 = &gsc_2; + gsc3 = &gsc_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + i2c8 = &i2c_8; + i2c9 = &i2c_9; + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <925000>; + clock-latency-ns = <140000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + clock-latency-ns = <140000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <140000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1050000>; + clock-latency-ns = <140000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1075000>; + clock-latency-ns = <140000>; + opp-suspend; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1125000>; + clock-latency-ns = <140000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1150000>; + clock-latency-ns = <140000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <140000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <140000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <140000>; + }; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, <22 4>; + }; + + soc: soc { + sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x30000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + + pd_gsc: power-domain@10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + #power-domain-cells = <0>; + label = "GSC"; + }; + + pd_mfc: power-domain@10044040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044040 0x20>; + #power-domain-cells = <0>; + label = "MFC"; + }; + + pd_g3d: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; + + pd_disp1: power-domain@100440a0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440a0 0x20>; + #power-domain-cells = <0>; + label = "DISP1"; + }; + + pd_mau: power-domain@100440c0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440c0 0x20>; + #power-domain-cells = <0>; + label = "MAU"; + }; + + clock: clock-controller@10010000 { + compatible = "samsung,exynos5250-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0c>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + power-domains = <&pd_mau>; + }; + + timer@101c0000 { + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; + reg = <0x101c0000 0x800>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts-extended = <&combiner 23 3>, + <&combiner 23 4>, + <&combiner 25 2>, + <&combiner 25 3>, + <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_1: pinctrl@13400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = ; + }; + + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x10d10000 0x1000>; + interrupts = ; + }; + + pinctrl_3: pinctrl@3860000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = ; + power-domains = <&pd_mau>; + }; + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon"; + reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + #clock-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + + dp_phy: dp-phy { + compatible = "samsung,exynos5250-dp-video-phy"; + #phy-cells = <0>; + }; + + mipi_phy: mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; + }; + + watchdog@101d0000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x101d0000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + mfc: codec@11000000 { + compatible = "samsung,mfc-v6"; + reg = <0x11000000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>; + clock-names = "mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; + + rotator: rotator@11c00000 { + compatible = "samsung,exynos5250-rotator"; + reg = <0x11c00000 0x64>; + interrupts = ; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; + + mali: gpu@11800000 { + compatible = "samsung,exynos5250-mali", "arm,mali-t604"; + reg = <0x11800000 0x5000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&clock CLK_G3D>; + clock-names = "core"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&pd_g3d>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <925000>; + }; + opp-266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <1025000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <1075000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1125000>; + }; + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <1150000>; + }; + opp-533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <1250000>; + }; + }; + }; + + tmu: tmu@10060000 { + compatible = "samsung,exynos5250-tmu"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + sata: sata@122f0000 { + compatible = "snps,dwc-ahci"; + reg = <0x122f0000 0x1ff>; + interrupts = ; + clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; + clock-names = "sata", "pclk"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + sata_phy: sata-phy@12170000 { + compatible = "samsung,exynos5250-sata-phy"; + reg = <0x12170000 0x1ff>; + clocks = <&clock CLK_SATA_PHYCTRL>; + clock-names = "sata_phyctrl"; + #phy-cells = <0>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + /* i2c_0-3 are defined in exynos5.dtsi */ + i2c_4: i2c@12ca0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12ca0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c@12cb0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12cb0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c@12cc0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12cc0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c@12cd0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12cd0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + i2c_8: i2c@12ce0000 { + compatible = "samsung,s3c2440-hdmiphy-i2c"; + reg = <0x12ce0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C_HDMI>; + clock-names = "i2c"; + status = "disabled"; + + hdmiphy: hdmi-phy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; + }; + + i2c_9: i2c@121d0000 { + compatible = "samsung,exynos5-sata-phy-i2c"; + reg = <0x121d0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SATA_PHYI2C>; + clock-names = "i2c"; + status = "disabled"; + + sata_phy_i2c: sata-phy-i2c@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; + status = "disabled"; + }; + }; + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + status = "disabled"; + reg = <0x12d20000 0x100>; + interrupts = ; + dmas = <&pdma0 5>, <&pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + }; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + status = "disabled"; + reg = <0x12d30000 0x100>; + interrupts = ; + dmas = <&pdma1 5>, <&pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + }; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + status = "disabled"; + reg = <0x12d40000 0x100>; + interrupts = ; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + }; + + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x1000>; + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x1000>; + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_3: mmc@12230000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12230000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + status = "disabled"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10>, + <&pdma0 9>, + <&pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + power-domains = <&pd_mau>; + #clock-cells = <1>; + #sound-dai-cells = <1>; + }; + + i2s1: i2s@12d60000 { + compatible = "samsung,s3c6410-i2s"; + status = "disabled"; + reg = <0x12d60000 0x100>; + dmas = <&pdma1 12>, + <&pdma1 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; + clock-names = "iis", "i2s_opclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + power-domains = <&pd_mau>; + #sound-dai-cells = <1>; + }; + + i2s2: i2s@12d70000 { + compatible = "samsung,s3c6410-i2s"; + status = "disabled"; + reg = <0x12d70000 0x100>; + dmas = <&pdma0 12>, + <&pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; + clock-names = "iis", "i2s_opclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + power-domains = <&pd_mau>; + #sound-dai-cells = <1>; + }; + + usbdrd: usb@12000000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USB3>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000000 0x10000>; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy: phy@12100000 { + compatible = "samsung,exynos5250-usbdrd-phy"; + reg = <0x12100000 0x100>; + clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + ehci: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = ; + + clocks = <&clock CLK_USB2>; + clock-names = "usbhost"; + phys = <&usb2_phy_gen 1>; + phy-names = "host"; + }; + + ohci: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = ; + + clocks = <&clock CLK_USB2>; + clock-names = "usbhost"; + phys = <&usb2_phy_gen 1>; + phy-names = "host"; + }; + + usb2_phy_gen: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; + + pdma0: dma-controller@121a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121a0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@121b0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121b0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + mdma0: dma-controller@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + mdma1: dma-controller@11c10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11c10000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + gsc_0: gsc@13e00000 { + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = ; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + iommus = <&sysmmu_gsc0>; + }; + + gsc_1: gsc@13e10000 { + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = ; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL1>; + clock-names = "gscl"; + iommus = <&sysmmu_gsc1>; + }; + + gsc_2: gsc@13e20000 { + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; + reg = <0x13e20000 0x1000>; + interrupts = ; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL2>; + clock-names = "gscl"; + iommus = <&sysmmu_gsc2>; + }; + + gsc_3: gsc@13e30000 { + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; + reg = <0x13e30000 0x1000>; + interrupts = ; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL3>; + clock-names = "gscl"; + iommus = <&sysmmu_gsc3>; + }; + + hdmi: hdmi@14530000 { + compatible = "samsung,exynos4212-hdmi"; + reg = <0x14530000 0x70000>; + power-domains = <&pd_disp1>; + interrupts = ; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + samsung,syscon-phandle = <&pmu_system_controller>; + phy = <&hdmiphy>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hdmicec: cec@101b0000 { + compatible = "samsung,s5p-cec"; + reg = <0x101b0000 0x200>; + interrupts = ; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; + + mixer: mixer@14450000 { + compatible = "samsung,exynos5250-mixer"; + reg = <0x14450000 0x10000>; + power-domains = <&pd_disp1>; + interrupts = ; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>; + clock-names = "mixer", "hdmi", "sclk_hdmi"; + iommus = <&sysmmu_tv>; + status = "disabled"; + }; + + dsi_0: dsi@14500000 { + compatible = "samsung,exynos4210-mipi-dsi"; + reg = <0x14500000 0x10000>; + interrupts = ; + samsung,power-domain = <&pd_disp1>; + phys = <&mipi_phy 3>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; + clock-names = "bus_clk", "sclk_mipi"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + adc: adc@12d10000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x12d10000 0x100>; + interrupts = ; + clocks = <&clock CLK_ADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + sysmmu_g2d: sysmmu@10a60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10a60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + power-domains = <&pd_mfc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + power-domains = <&pd_mfc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@11d40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11d40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg: sysmmu@11f20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11f20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_isp: sysmmu@13260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_ISP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_drc: sysmmu@13270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <11 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DRC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_fd: sysmmu@132a0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132a0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 0>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_FD>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_scc: sysmmu@13280000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13280000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 2>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_SCC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_scp: sysmmu@13290000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13290000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_SCP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_mcuctl: sysmmu@132b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_MCU>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_odc: sysmmu@132c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132c0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <11 0>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_ODC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_dis0: sysmmu@132d0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132d0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DIS0>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_dis1: sysmmu@132e0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132e0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <9 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DIS1>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_3dnr: sysmmu@132f0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132f0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_3DNR>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite0: sysmmu@13c40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13c40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 4>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite1: sysmmu@13c50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13c50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 1>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; + #iommu-cells = <0>; + }; + + sysmmu_gsc0: sysmmu@13e80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13e80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_gsc1: sysmmu@13e90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13e90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_gsc2: sysmmu@13ea0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13ea0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_gsc3: sysmmu@13eb0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13eb0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 6>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1: sysmmu@14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + power-domains = <&pd_disp1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + power-domains = <&pd_disp1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; + #iommu-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * Unfortunately we need this since some versions + * of U-Boot on Exynos don't set the CNTFRQ register, + * so we need the value from DT. + */ + clock-frequency = <24000000>; + }; +}; + +&cpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu>; + + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 15 15>, + <&cpu1 15 15>; + }; + }; +}; + +&dp { + power-domains = <&pd_disp1>; + clocks = <&clock CLK_DP>; + clock-names = "dp"; + phys = <&dp_phy>; + phy-names = "dp"; +}; + +&fimd { + power-domains = <&pd_disp1>; + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; + clock-names = "sclk_fimd", "fimd"; + iommus = <&sysmmu_fimd1>; +}; + +&g2d { + iommus = <&sysmmu_g2d>; + clocks = <&clock CLK_G2D>; + clock-names = "fimg2d"; + status = "okay"; +}; + +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&prng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; + +&rtc { + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&pmu_system_controller>; + status = "disabled"; +}; + +&serial_0 { + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 13>, <&pdma0 14>; + dma-names = "rx", "tx"; +}; + +&serial_1 { + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; +}; + +&serial_2 { + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; +}; + +&serial_3 { + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; +}; + +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&trng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +#include "exynos5250-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi new file mode 100644 index 000000000000..d15494b4bda9 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include "exynos-pinctrl.h" + +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_vbus0_en: usb3-vbus0-en-pins { + samsung,pins = "gpa2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif1_bus: spdif1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_hs_bus: i2c0-hs-bus-pins { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_hs_bus: i2c1-hs-bus-pins { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_hs_bus: i2c2-hs-bus-pins { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_hs_bus: i2c3-hs-bus-pins { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpb4-2", "gpb4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpb4-4", "gpb4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpb4-6", "gpb4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c8_bus: i2c8-bus-pins { + samsung,pins = "gpb5-0", "gpb5-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c9_bus: i2c9-bus-pins { + samsung,pins = "gpb5-2", "gpb5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c10_bus: i2c10-bus-pins { + samsung,pins = "gpb5-4", "gpb5-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c11_bus: i2c11-bus-pins { + samsung,pins = "gpb5-6", "gpb5-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_gpio_a: cam-gpio-a-pins { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_gpio_b: cam-gpio-b-pins { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c1_bus: cam-i2c1-bus-pins { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c0_bus: cam-i2c0-bus-pins { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_spi0_bus: cam-spi0-bus-pins { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_spi1_bus: cam-spi1-bus-pins { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs: sd0-rdqs-pins { + samsung,pins = "gpc0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpc1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpc1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus8: sd1-bus-width8-pins { + samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpc2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpc2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpz0: gpz0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts b/arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts new file mode 100644 index 000000000000..d072a7398866 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung XYREF5260 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5260.dtsi" + +/ { + model = "Samsung XYREF5260 board based on Exynos5260"; + compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; + }; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + ioclk_pcm: clock-pcm-ext { + compatible = "fixed-clock"; + clock-frequency = <2048000>; + clock-output-names = "ioclk_pcm_extclk"; + #clock-cells = <0>; + }; + + ioclk_i2s: clock-i2s-cd { + compatible = "fixed-clock"; + clock-frequency = <147456000>; + clock-output-names = "ioclk_i2s_cdclk"; + #clock-cells = <0>; + }; + + ioclk_spdif: clock-spdif-ext { + compatible = "fixed-clock"; + clock-frequency = <49152000>; + clock-output-names = "ioclk_spdif_extclk"; + #clock-cells = <0>; + }; + + xrtcxti: xrtcxti { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xrtcxti"; + #clock-cells = <0>; + }; +}; + +&pinctrl_0 { + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + cap-mmc-highspeed; + mmc-hs200-1_8v; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; +}; + +&mmc_2 { + status = "okay"; + cap-sd-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + disable-wp; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5260.dtsi b/arch/arm/boot/dts/samsung/exynos5260.dtsi new file mode 100644 index 000000000000..a97449b4640c --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5260.dtsi @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5260 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +#include +#include + +/ { + compatible = "samsung,exynos5260", "samsung,exynos5"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + core2 { + cpu = <&cpu4>; + }; + core3 { + cpu = <&cpu5>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + cci-control-port = <&cci_control1>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + cci-control-port = <&cci_control1>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control0>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control0>; + }; + + cpu4: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cci-control-port = <&cci_control0>; + }; + + cpu5: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cci-control-port = <&cci_control0>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock_top: clock-controller@10010000 { + compatible = "samsung,exynos5260-clock-top"; + reg = <0x10010000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEM_PLL>, + <&clock_mif MIF_DOUT_BUS_PLL>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_mem_pll", + "dout_bus_pll", + "dout_media_pll"; + }; + + clock_peri: clock-controller@10200000 { + compatible = "samsung,exynos5260-clock-peri"; + reg = <0x10200000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&ioclk_pcm>, + <&ioclk_i2s>, + <&ioclk_spdif>, + <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_PERI_66>, + <&clock_top TOP_DOUT_SCLK_PERI_UART0>, + <&clock_top TOP_DOUT_SCLK_PERI_UART1>, + <&clock_top TOP_DOUT_SCLK_PERI_UART2>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>, + <&clock_top TOP_DOUT_ACLK_PERI_AUD>; + clock-names = "fin_pll", + "ioclk_pcm_extclk", + "ioclk_i2s_cdclk", + "ioclk_spdif_extclk", + "phyclk_hdmi_phy_ref_cko", + "dout_aclk_peri_66", + "dout_sclk_peri_uart0", + "dout_sclk_peri_uart1", + "dout_sclk_peri_uart2", + "dout_sclk_peri_spi0_b", + "dout_sclk_peri_spi1_b", + "dout_sclk_peri_spi2_b", + "dout_aclk_peri_aud"; + }; + + clock_egl: clock-controller@10600000 { + compatible = "samsung,exynos5260-clock-egl"; + reg = <0x10600000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_BUS_PLL>; + clock-names = "fin_pll", + "dout_bus_pll"; + }; + + clock_kfc: clock-controller@10700000 { + compatible = "samsung,exynos5260-clock-kfc"; + reg = <0x10700000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_media_pll"; + }; + + clock_g2d: clock-controller@10a00000 { + compatible = "samsung,exynos5260-clock-g2d"; + reg = <0x10a00000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_G2D_333>; + clock-names = "fin_pll", + "dout_aclk_g2d_333"; + }; + + clock_mif: clock-controller@10ce0000 { + compatible = "samsung,exynos5260-clock-mif"; + reg = <0x10ce0000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_mfc: clock-controller@11090000 { + compatible = "samsung,exynos5260-clock-mfc"; + reg = <0x11090000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_MFC_333>; + clock-names = "fin_pll", + "dout_aclk_mfc_333"; + }; + + clock_g3d: clock-controller@11830000 { + compatible = "samsung,exynos5260-clock-g3d"; + reg = <0x11830000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_fsys: clock-controller@122e0000 { + compatible = "samsung,exynos5260-clock-fsys"; + reg = <0x122e0000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_FSYS_200>; + clock-names = "fin_pll", + "phyclk_usbhost20_phy_phyclock", + "phyclk_usbhost20_phy_freeclk", + "phyclk_usbhost20_phy_clk48mohci", + "phyclk_usbdrd30_udrd30_pipe_pclk", + "phyclk_usbdrd30_udrd30_phyclock", + "dout_aclk_fsys_200"; + }; + + clock_aud: clock-controller@128c0000 { + compatible = "samsung,exynos5260-clock-aud"; + reg = <0x128c0000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_FOUT_AUD_PLL>, + <&ioclk_i2s>, + <&ioclk_pcm>; + clock-names = "fin_pll", + "fout_aud_pll", + "ioclk_i2s_cdclk", + "ioclk_pcm_extclk"; + }; + + clock_isp: clock-controller@133c0000 { + compatible = "samsung,exynos5260-clock-isp"; + reg = <0x133c0000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_ISP1_266>, + <&clock_top TOP_DOUT_ACLK_ISP1_400>, + <&clock_top TOP_MOUT_ACLK_ISP1_266>; + clock-names = "fin_pll", + "dout_aclk_isp1_266", + "dout_aclk_isp1_400", + "mout_aclk_isp1_266"; + }; + + clock_gscl: clock-controller@13f00000 { + compatible = "samsung,exynos5260-clock-gscl"; + reg = <0x13f00000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_GSCL_400>, + <&clock_top TOP_DOUT_ACLK_GSCL_333>; + clock-names = "fin_pll", + "dout_aclk_gscl_400", + "dout_aclk_gscl_333"; + }; + + clock_disp: clock-controller@14550000 { + compatible = "samsung,exynos5260-clock-disp"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&ioclk_spdif>, + <&clock_top TOP_DOUT_ACLK_PERI_AUD>, + <&clock_top TOP_DOUT_ACLK_DISP_222>, + <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>, + <&clock_top TOP_DOUT_ACLK_DISP_333>; + clock-names = "fin_pll", + "phyclk_dptx_phy_ch3_txd_clk", + "phyclk_dptx_phy_ch2_txd_clk", + "phyclk_dptx_phy_ch1_txd_clk", + "phyclk_dptx_phy_ch0_txd_clk", + "phyclk_hdmi_phy_tmds_clko", + "phyclk_hdmi_phy_ref_clko", + "phyclk_hdmi_phy_pixel_clko", + "phyclk_hdmi_link_o_tmds_clkhi", + "phyclk_mipi_dphy_4l_m_txbyte_clkhs", + "phyclk_dptx_phy_o_ref_clk_24m", + "phyclk_dptx_phy_clk_div2", + "phyclk_mipi_dphy_4l_m_rxclkesc0", + "phyclk_hdmi_phy_ref_cko", + "ioclk_spdif_extclk", + "dout_aclk_peri_aud", + "dout_aclk_disp_222", + "dout_sclk_disp_pixel", + "dout_aclk_disp_333"; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = ; + }; + + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + mct: timer@100b0000 { + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; + reg = <0x100b0000 0x1000>; + clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + cci: cci@10f00000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10f00000 0x1000>; + ranges = <0x0 0x10f00000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + pinctrl_0: pinctrl@11600000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x11600000 0x1000>; + interrupts = ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_1: pinctrl@12290000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x12290000 0x1000>; + interrupts = ; + }; + + pinctrl_2: pinctrl@128b0000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x128b0000 0x1000>; + interrupts = ; + }; + + pmu_system_controller: system-controller@10d50000 { + compatible = "samsung,exynos5260-pmu", "syscon"; + reg = <0x10d50000 0x10000>; + }; + + uart0: serial@12c00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c00000 0x100>; + interrupts = ; + clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart1: serial@12c10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c10000 0x100>; + interrupts = ; + clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart2: serial@12c20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12c20000 0x100>; + interrupts = ; + clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart3: serial@12860000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12860000 0x100>; + interrupts = ; + clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + mmc_0: mmc@12140000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12140000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; + clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC0>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; + fifo-depth = <64>; + status = "disabled"; + }; + + mmc_1: mmc@12150000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12150000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; + clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC1>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; + fifo-depth = <64>; + status = "disabled"; + }; + + mmc_2: mmc@12160000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12160000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; + clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC2>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; + fifo-depth = <64>; + status = "disabled"; + }; + + hsi2c_0: i2c@12da0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12da0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: i2c@12db0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12db0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: i2c@12dc0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12dc0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: i2c@12dd0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12dd0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + }; +}; + +#include "exynos5260-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts b/arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts new file mode 100644 index 000000000000..882fc77c4bc4 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2016 Krzysztof Kozlowski + */ + +/dts-v1/; +#include "exynos5410.dtsi" +#include +#include +#include +#include +#include "exynos54xx-odroidxu-leds.dtsi" + +/ { + model = "Hardkernel Odroid XU"; + compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x7ea00000>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_nrst_pin>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 20972 0>; + #cooling-cells = <2>; + cooling-levels = <0 130 170 230>; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "Odroid-XU"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speakers", "Speakers"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,cpu { + sound-dai = <&audi2s0 0>; + system-clock-frequency = <19200000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&max98090>; + clocks = <&audi2s0 CLK_I2S_CDCLK>; + }; + }; +}; + +&adc { + vdd-supply = <&ldo10_reg>; + status = "okay"; +}; + +&audi2s0 { + status = "okay"; +}; + +&clock { + clocks = <&fin_pll>; + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <192000000>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + + assigned-clock-rates = <0>, + <0>, + <96000000>, + <19200000>; +}; + +&cpu0_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + trips { + cpu_alert0: cpu-alert-0 { + temperature = <50000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert1: cpu-alert-1 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert2: cpu-alert-2 { + temperature = <70000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + }; +}; + +&hsi2c_4 { + clock-frequency = <400000>; + status = "okay"; + + usb3503: usb-hub@8 { + compatible = "smsc,usb3503"; + reg = <0x08>; + + intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; + connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + + clock-names = "refclk"; + clocks = <&pmu_system_controller 0>; + refclk-frequency = <24000000>; + }; + + max77802: pmic@9 { + compatible = "maxim,max77802"; + reg = <0x9>; + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>; + wakeup-source; + #clock-cells = <1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&buck10_reg>; + inl7-supply = <&buck9_reg>; + /* inl9 supply is BOOST, not configured here */ + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + /* vdd_mmc0 */ + regulator-name = "vddf_2v85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "buck9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "buck10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_alive"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vddq_m1_m2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vddq_gpio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + /* Having it off prevents reboot */ + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd18_hsic"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd18_bpll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vddq_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* Supplies also GPK and GPJ */ + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd10_hdmi"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "ldo9"; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd18_mipi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vddq_mmc01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* + * Having it off prevents accessing MMC after + * reboot with error: + * MMC Device 1: Clock OFF has been failed. + */ + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd33_usb3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vddq_abbg0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "vddq_abbg1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd10_usb3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "cam_sensor_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo19"; + }; + + ldo20_reg: LDO20 { + regulator-name = "vdd_mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + /* vdd_mmc2 */ + regulator-name = "vddf_2v8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "dp_p3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "cam_af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "eth_p3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "usb30_extclk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo27"; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo28"; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo29"; + }; + + ldo30_reg: LDO30 { + regulator-name = "vddq_e1_e2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* On revisions with ti,ina231 this is sensor VS */ + ldo32_reg: LDO32 { + regulator-name = "vs_power_meter"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo33"; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo34"; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo35"; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + max98090: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpj3>; + interrupts = <0 IRQ_TYPE_NONE>; + clocks = <&audi2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&mmc_0 { + status = "okay"; + mmc-pwrseq = <&emmc_pwrseq>; + cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&ldo20_reg>; + vqmmc-supply = <&ldo11_reg>; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4 &sd2_wp>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <&ldo21_reg>; + vqmmc-supply = <&ldo4_reg>; +}; + +&pinctrl_0 { + emmc_nrst_pin: emmc-nrst-pins { + samsung,pins = "gpd1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_wp: sd2-wp-pins { + samsung,pins = "gpm5-0"; + samsung,pin-function = ; + /* Pin is floating so be sure to disable write-protect */ + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpx0-0", "gpx0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_dvs_1: pmic-dvs-1-pins { + samsung,pins = "gpx0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <1>; + }; + + max77802_irq: max77802-irq-pins { + samsung,pins = "gpx0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + /* + * PWM 0 -- fan + * PWM 1 -- Green LED + * PWM 2 -- Blue LED + * PWM 3 -- on MIPI connector for backlight + */ + pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&usb3_0_oc { + /* External pull up */ + samsung,pin-pud = ; +}; + +&usb3_1_oc { + /* External pull up */ + samsung,pin-pud = ; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo12_reg>; + vdd10-supply = <&ldo15_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo12_reg>; + vdd10-supply = <&ldo15_reg>; +}; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@2 { + compatible = "usb424,9730"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi new file mode 100644 index 000000000000..f7b923382892 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi @@ -0,0 +1,652 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Exynos5410 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Hardkernel Co., Ltd. + * https://www.hardkernel.com + */ + +#include "exynos-pinctrl.h" + +&pinctrl_0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm5: gpm5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm7: gpm7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy0: gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy7: gpy7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, + <24 0>, + <25 0>, + <25 1>, + <26 0>, + <26 1>, + <27 0>, + <27 1>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, + <28 1>, + <29 0>, + <29 1>, + <30 0>, + <30 1>, + <31 0>, + <31 1>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_hs_bus: i2c4-hs-bus-pins { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_hs_bus: i2c5-hs-bus-pins { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_hs_bus: i2c6-hs-bus-pins { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpb2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpb2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpb2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_hs_bus: i2c7-hs-bus-pins { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpc0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpc2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpc2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpj0: gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj2: gpj2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj3: gpj3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + usb3_1_oc: usb3-1-oc-pins { + samsung,pins = "gpk2-4", "gpk2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_1_vbusctrl: usb3-1-vbusctrl-pins { + samsung,pins = "gpk2-6", "gpk2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_0_oc: usb3-0-oc-pins { + samsung,pins = "gpk3-0", "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_0_vbusctrl: usb3-0-vbusctrl-pins { + samsung,pins = "gpk3-2", "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpv0: gpv0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_3 { + gpz: gpz-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + audi2s0_bus: audi2s0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + +}; diff --git a/arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts b/arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts new file mode 100644 index 000000000000..bb29b76f6f6a --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung SMDK5410 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5410.dtsi" +#include +/ { + model = "Samsung SMDK5410 board based on Exynos5410"; + compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + firmware@2037000 { + compatible = "samsung,secure-firmware"; + reg = <0x02037000 0x1000>; + }; + + vdd10_usb3: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VDD10_USB3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vdd33_usb3: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VDD33_USB3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc_0 { + status = "okay"; + cap-mmc-highspeed; + broken-cd; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; +}; + +&mmc_2 { + status = "okay"; + cap-sd-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <4>; + disable-wp; +}; + +&pinctrl_0 { + srom_ctl: srom-ctl-pins { + samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", + "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; + samsung,pin-function = ; + samsung,pin-drv = ; + }; + + srom_ebi: srom-ebi-pins { + samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", + "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", + "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", + "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", + "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", + "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sromc { + pinctrl-names = "default"; + pinctrl-0 = <&srom_ctl>, <&srom_ebi>; + + ethernet@3,0 { + compatible = "smsc,lan9115"; + reg = <3 0 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gpx0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reg-io-width = <2>; + smsc,irq-push-pull; + smsc,force-internal-phy; + + samsung,srom-page-mode; + samsung,srom-timing = <9 12 1 9 1 1>; + }; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&usbdrd3_0 { + vdd10-supply = <&vdd10_usb3>; + vdd33-supply = <&vdd33_usb3>; +}; + +&usbdrd3_1 { + vdd10-supply = <&vdd10_usb3>; + vdd33-supply = <&vdd33_usb3>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5410.dtsi b/arch/arm/boot/dts/samsung/exynos5410.dtsi new file mode 100644 index 000000000000..546035e78f40 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5410.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5410 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung Exynos5410 SoC device nodes are listed in this file. + * Exynos5410 based board files can include this file and provide + * values for board specific bindings. + */ + +#include "exynos54xx.dtsi" +#include +#include +#include + +/ { + compatible = "samsung,exynos5410", "samsung,exynos5"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1600000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1600000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1600000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1600000000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5410-pmu", "syscon"; + reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&fin_pll>; + #clock-cells = <1>; + }; + + clock: clock-controller@10010000 { + compatible = "samsung,exynos5410-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5410-audss-clock"; + reg = <0x03810000 0x0c>; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; + clock-names = "pll_ref", "pll_in"; + }; + + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10068000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x1006c000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12200000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12210000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12220000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5410-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_1: pinctrl@14000000 { + compatible = "samsung,exynos5410-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = ; + }; + + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,exynos5410-pinctrl"; + reg = <0x10d10000 0x1000>; + interrupts = ; + }; + + pinctrl_3: pinctrl@3860000 { + compatible = "samsung,exynos5410-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = ; + }; + + pdma0: dma-controller@121a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121a0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@121b0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121b0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + audi2s0: i2s@3830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10>, + <&pdma0 9>, + <&pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&audi2s0_bus>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + #include "exynos5420-trip-points.dtsi" + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" + }; + }; +}; + +&adc { + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&hsi2c_4 { + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; +}; + +&hsi2c_5 { + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; +}; + +&hsi2c_6 { + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; +}; + +&hsi2c_7 { + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; +}; + +&mct { + clocks = <&fin_pll>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; +}; + +&prng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; + +&rtc { + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + status = "disabled"; +}; + +&serial_0 { + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 13>, <&pdma0 14>; + dma-names = "rx", "tx"; +}; + +&serial_1 { + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; +}; + +&serial_2 { + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; +}; + +&serial_3 { + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; +}; + +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&sromc { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x04000000 0x20000 + 1 0 0x05000000 0x20000 + 2 0 0x06000000 0x20000 + 3 0 0x07000000 0x20000>; +}; + +&trng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&usbdrd3_0 { + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>; +}; + +&usbdrd_phy0 { + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbdrd3_1 { + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>; +}; + +&usbdrd_dwc3_1 { + interrupts = ; +}; + +&usbdrd_phy1 { + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbhost1 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usbhost2 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usb2_phy { + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; +}; + +&watchdog { + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + +#include "exynos5410-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts new file mode 100644 index 000000000000..809ddda02e53 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts @@ -0,0 +1,843 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 based Arndale Octa board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5420.dtsi" +#include "exynos5420-cpus.dtsi" +#include +#include +#include +#include + +/ { + model = "Insignal Arndale Octa evaluation board based on Exynos5420"; + compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; + }; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-wakeup { + label = "SW-TACT1"; + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; +}; + +&adc { + vdd-supply = <&ldo4_reg>; + status = "okay"; +}; + +&cci { + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&cpu0_thermal { + trips { + cpu0_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu0_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu0_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu0_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * Reduce the CPU speed by 2 steps, down to: 1600 MHz + * and 1100 MHz. + */ + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + /* + * Reduce the CPU speed down to 1200 MHz big (6 steps) + * and 800 MHz LITTLE (5 steps). + */ + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + /* + * Reduce the CPU speed as much as possible, down to 700 MHz + * big (11 steps) and 600 MHz LITTLE (7 steps). + */ + map2 { + trip = <&cpu0_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 5 7>, + <&cpu5 5 7>, + <&cpu6 5 7>, + <&cpu7 5 7>; + }; + }; +}; + +&cpu1_thermal { + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu1_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + map2 { + trip = <&cpu1_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 5 7>, + <&cpu5 5 7>, + <&cpu6 5 7>, + <&cpu7 5 7>; + }; + }; +}; + +&cpu2_thermal { + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu2_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + map2 { + trip = <&cpu2_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 6 7>, + <&cpu5 6 7>, + <&cpu6 6 7>, + <&cpu7 6 7>; + }; + }; +}; + +&cpu3_thermal { + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu3_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 3 6>, + <&cpu1 3 6>, + <&cpu2 3 6>, + <&cpu3 3 6>, + <&cpu4 3 5>, + <&cpu5 3 5>, + <&cpu6 3 5>, + <&cpu7 3 5>; + }; + + map2 { + trip = <&cpu3_alert2>; + cooling-device = <&cpu0 6 11>, + <&cpu1 6 11>, + <&cpu2 6 11>, + <&cpu3 6 11>, + <&cpu4 5 7>, + <&cpu5 5 7>, + <&cpu6 5 7>, + <&cpu7 5 7>; + }; + }; +}; + +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; + vdd-supply = <&ldo6_reg>; + ddc = <&i2c_2>; + status = "okay"; +}; + +&hsi2c_4 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + wakeup-source; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "PVDD_ALIVE_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "PVDD_APIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "PVDD_APIO_MMCON_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* + * Must be always on, even though there is + * a consumer (mmc_0). Otherwise the board + * does not reboot with vendor U-Boot + * (Linaro for Arndale Octa, v2012.07). + */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "PVDD_ADC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "PVDD_PLL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "PVDD_ANAIP_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "PVDD_ANAIP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "PVDD_ABB_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "PVDD_USB_3V3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "PVDD_PRE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "PVDD_USB_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "PVDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "PVDD_APIO_MMCOFF_2V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + /* Unused */ + regulator-name = "PVDD_LDO14"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "PVDD_PERI_2V8"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "PVDD_PERI_3V3"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + /* Unused */ + regulator-name = "PVDD_LDO17"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "PVDD_EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* + * Must stay in "off" mode during shutdown for + * proper eMMC reset. The "off" mode is in + * fact controlled by LDO18EN. The eMMC does + * not have reset pin connected so the reset + * will be triggered by falling edge of + * LDO18EN. + */ + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "PVDD_TFLASH_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "PVDD_BTWIFI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "PVDD_CAM1IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo22_reg: LDO22 { + /* Unused */ + regulator-name = "PVDD_LDO22"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "PVDD_MIFS_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "PVDD_CAM1_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + /* Unused */ + regulator-name = "PVDD_LDO25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "PVDD_CAM0_AF_2V8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "PVDD_G3DS_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "PVDD_TSP_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "PVDD_AUDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + /* Unused */ + regulator-name = "PVDD_LDO30"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo31_reg: LDO31 { + regulator-name = "PVDD_PERI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo32_reg: LDO32 { + regulator-name = "PVDD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "PVDD_CAM0IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo34_reg: LDO34 { + /* Unused */ + regulator-name = "PVDD_LDO34"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "PVDD_CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "PVDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "PVDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "PVDD_CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "PVDD_MIF_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "PVDD_ARM_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "PVDD_INT_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "PVDD_G3D_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "PVDD_LPDDR3_1V2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "PVDD_KFC_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO_1V4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO_2V0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO_3V5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "PVDD_EMMCF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + /* + * Must stay in "off" mode during shutdown for + * proper eMMC reset. The "off" mode is in + * fact controlled by BUCK10EN. The eMMC does + * not have reset pin connected so the reset + * will be triggered by falling edge of + * BUCK10EN. + */ + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c_2 { + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + non-removable; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + vmmc-supply = <&ldo18_reg>; + vqmmc-supply = <&ldo3_reg>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&usbdrd3_0 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts b/arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts new file mode 100644 index 000000000000..1319344a2c74 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 Chagall WiFi board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420-galaxy-tab-common.dtsi" + +/ { + model = "Samsung Chagall WiFi based on Exynos5420"; + compatible = "samsung,chagall-wifi", "samsung,exynos5420", \ + "samsung,exynos5"; +}; + +&ldo15_reg { + /* Unused */ + regulator-name = "VDD_LDO15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo17_reg { + regulator-name = "VDD_IRLED_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo28_reg { + /* Unused */ + regulator-name = "VDD_LDO28"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo29_reg { + regulator-name = "VDD_TCON_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo31_reg { + regulator-name = "VDD_GRIP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo32_reg { + regulator-name = "VDD_TSP_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi new file mode 100644 index 000000000000..e9f4eb75b50f --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5420 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This file provides desired ordering for Exynos5420 and Exynos5800 + * boards: CPU[0123] being the A15. + * + * The Exynos5420, 5422 and 5800 actually share the same CPU configuration + * but particular boards choose different booting order. + * + * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 + * booting cluster (big or LITTLE) is chosen by IROM code by reading + * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting + * from the LITTLE: Cortex-A7. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + }; +}; + +&arm_a7_pmu { + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi new file mode 100644 index 000000000000..f525b2f5e4e0 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi @@ -0,0 +1,696 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base DT for Samsung's family of tablets based on Exynos5420. + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420.dtsi" +#include "exynos5420-cpus.dtsi" +#include +#include +#include + +/ { + chassis-type = "tablet"; + + /* + * To successfully boot the mainline kernel with the stock + * bootloader (SBOOT), the tlb needs to be flushed after the + * page table pointer has been updated in __common_mmu_cache_on. + * The same hack is also needed to boot exynos4412-i9300 with + * stock bootloader, and probably other Samsung devices of + * similar age. See + * https://lore.kernel.org/all/1355276466-18295-1-git-send-email-arve@android.com + * for more details. + */ + + aliases { + mmc0 = &mmc_0; + mmc2 = &mmc_2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0xc0000000>; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + debounce-interval = <10>; + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = ; + wakeup-source; + }; + + key-home { + debounce-interval = <10>; + gpios = <&gpx0 5 GPIO_ACTIVE_LOW>; + label = "Home"; + linux,code = ; + wakeup-source; + }; + + key-volume-up { + debounce-interval = <10>; + gpios = <&gpx0 2 GPIO_ACTIVE_LOW>; + label = "Volume Up"; + linux,code = ; + }; + + key-volume-down { + debounce-interval = <10>; + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + label = "Volume Down"; + linux,code = ; + }; + }; +}; + +&cci { + /* CCI is disabled in hardware */ + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&gpu { + status = "okay"; + mali-supply = <&buck4_reg>; +}; + +&hsi2c_7 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", "s2mps11_cp", + "s2mps11_bt"; + }; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF_1V1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D_1V0"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_KFC_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO_1V4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO_2V0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO_3V5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "VDD_CAM_ISP_1V0"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3550000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_APIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_APIO_MMC01_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_ADC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + /* Unused */ + regulator-name = "VDD_LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MIPI_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_MIPI_PLL_ABB1_18V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + /* Unused */ + regulator-name = "VDD_LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_UOTG_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_PRE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_HSIC_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_APIO_MMC2_2V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD_MOTOR_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD_LDO15"; + /* + * LDO15 varies between devices and is + * specified in the device dts + */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD_AP_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDD_LDO17"; + /* + * LDO17 varies between devices and is + * specified in the device dts + */ + }; + + ldo18_reg: LDO18 { + /* Unused */ + regulator-name = "VDD_LDO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_VTF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD_CAM1_CAM_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_CAM_IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "VDD_CAM0_S_CORE_1V1"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD_MIFS_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD_TSP_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + /* Unused */ + regulator-name = "VDD_LDO25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD_CAM0_AF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "VDD_G3DS_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "VDD_LDO28"; + /* + * LDO28 varies between devices and is + * specified in the device dts + */ + }; + + ldo29_reg: LDO29 { + regulator-name = "VDD_LDO29"; + /* + * LDO29 varies between devices and is + * specified in the device dts + */ + }; + + ldo30_reg: LDO30 { + regulator-name = "VDD_TOUCH_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo31_reg: LDO31 { + regulator-name = "VDD_LDO31"; + /* + * LDO31 varies between devices and is + * specified in the device dts + */ + }; + + ldo32_reg: LDO32 { + regulator-name = "VDD_LDO32"; + /* + * LDO32 varies between devices and is + * specified in the device dts + */ + }; + + ldo33_reg: LDO33 { + regulator-name = "VDD_MHL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo34_reg: LDO34 { + regulator-name = "VDD_MHL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo35_reg: LDO35 { + regulator-name = "VDD_SIL_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "VDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "VDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VDD_KEY_LED_3V3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mixer { + status = "okay"; +}; + +/* Internal storage */ +&mmc_0 { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-names = "default"; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + vqmmc-supply = <&ldo3_reg>; +}; + +/* External sdcard */ +&mmc_2 { + status = "okay"; + bus-width = <4>; + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &mmc2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-names = "default"; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + sd-uhs-sdr50; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; +}; + +&pinctrl_0 { + mmc2_cd: mmc2-cd-pins { + samsung,pins = "gpx2-4"; + samsung,pin-pud = ; + }; + + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts b/arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts new file mode 100644 index 000000000000..011787b1bbf0 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 Klimt WiFi board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420-galaxy-tab-common.dtsi" + +/ { + model = "Samsung Klimt WiFi based on Exynos5420"; + compatible = "samsung,klimt-wifi", "samsung,exynos5420", \ + "samsung,exynos5"; +}; + +&ldo15_reg { + /* Unused */ + regulator-name = "VDD_LDO15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo17_reg { + regulator-name = "VDD_VCI_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo28_reg { + regulator-name = "VDD3_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo29_reg { + regulator-name = "VDDR_1V6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo31_reg { + /* Unused */ + regulator-name = "VDD_LDO31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&ldo32_reg { + regulator-name = "VDD_TSP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&mmc_2 { + sd-uhs-sdr104; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts new file mode 100644 index 000000000000..4e757b6e28e1 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -0,0 +1,1126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Peach Pit Rev 6+ board device tree source + * + * Copyright (c) 2014 Google, Inc + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "exynos5420.dtsi" +#include "exynos5420-cpus.dtsi" + +/ { + model = "Google Peach Pit Rev 6+"; + + compatible = "google,pit-rev16", + "google,pit-rev15", "google,pit-rev14", + "google,pit-rev13", "google,pit-rev12", + "google,pit-rev11", "google,pit-rev10", + "google,pit-rev9", "google,pit-rev8", + "google,pit-rev7", "google,pit-rev6", + "google,pit", "google,peach","samsung,exynos5420", + "samsung,exynos5"; + chassis-type = "laptop"; + + aliases { + /* Assign 20 so we don't get confused w/ builtin ones */ + i2c20 = &i2c_tunnel; + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_2; /* uSD */ + mmc2 = &mmc_1; /* WiFi */ + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + power-supply = <&tps65090_fet1>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq &lid_irq>; + + power-key { + label = "Power"; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + wakeup-source; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; + }; + + sound { + compatible = "google,snow-audio-max98090"; + + samsung,model = "Peach-Pit-I2S-MAX98090"; + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98090>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98090>, <&hdmi>; + }; + }; + + usb300_vbus_reg: regulator-usb300 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb300_vbus_en>; + enable-active-high; + }; + + usb301_vbus_reg: regulator-usb301 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb301_vbus_en>; + enable-active-high; + }; + + vbat: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat-supply"; + regulator-boot-on; + regulator-always-on; + }; + + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + mmc1_pwrseq: mmc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77802 MAX77802_CLK_32K_CP>; + clock-names = "ext_clock"; + }; +}; + +&adc { + status = "okay"; + vdd-supply = <&ldo9_reg>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_MAU_EPLL>; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x06>; + samsung,lane-count = <2>; + hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + ports { + port { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + status = "okay"; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; + + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&hsi2c_4 { + status = "okay"; + clock-frequency = <400000>; + + max77802: pmic@9 { + compatible = "maxim,max77802"; + interrupt-parent = <&gpx3>; + interrupts = <1 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_selb>, + <&pmic_dvs_1>, <&pmic_dvs_2>; + wakeup-source; + reg = <0x9>; + #clock-cells = <1>; + + inb1-supply = <&tps65090_dcdc2>; + inb2-supply = <&tps65090_dcdc1>; + inb3-supply = <&tps65090_dcdc2>; + inb4-supply = <&tps65090_dcdc2>; + inb5-supply = <&tps65090_dcdc1>; + inb6-supply = <&tps65090_dcdc2>; + inb7-supply = <&tps65090_dcdc1>; + inb8-supply = <&tps65090_dcdc1>; + inb9-supply = <&tps65090_dcdc1>; + inb10-supply = <&tps65090_dcdc1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&tps65090_dcdc2>; + inl7-supply = <&buck9_reg>; + inl9-supply = <&tps65090_dcdc2>; + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2v"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_1v2_2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_1v8_3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + vqmmc_sdcard: ldo4_reg: LDO4 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_1v8_5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_1v8_6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_1v8_7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo_19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "ldo_20"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "ldo_21"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "ldo_23"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ldo24_reg: LDO24 { + regulator-name = "ldo_24"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "ldo_25"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "ldo_26"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo_27"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo_28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo_29"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo32_reg: LDO32 { + regulator-name = "ldo_32"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo_33"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo_34"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo_35"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; +}; + +&hsi2c_7 { + status = "okay"; + clock-frequency = <400000>; + + max98090: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupts = <2 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98090_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + light-sensor@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + vcc-supply = <&tps65090_fet5>; + }; + + ps8625: lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; + lane-count = <2>; + use-external-pwm; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + + }; +}; + +&hsi2c_8 { + status = "okay"; + clock-frequency = <333000>; + + /* Atmel mXT336S */ + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = ; /* GPIO3 */ + }; +}; + +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; + }; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; +}; + +&i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +/* eMMC flash */ +&mmc_0 { + status = "okay"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + cap-mmc-highspeed; + non-removable; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; + bus-width = <8>; +}; + +/* WiFi SDIO module */ +&mmc_1 { + status = "okay"; + non-removable; + cap-sdio-irq; + keep-power-in-suspend; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc1_pwrseq>; + vqmmc-supply = <&buck10_reg>; +}; + +/* uSD card */ +&mmc_2 { + status = "okay"; + cap-sd-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; +}; + + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&mask_tpm_reset>; + + wifi_en: wifi-en-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + max98090_irq: max98090-irq-pins { + samsung,pins = "gpx0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* We need GPX0_6 to be low at sleep time; just keep it low always */ + mask_tpm_reset: mask-tpm-reset-pins { + samsung,pins = "gpx0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + tpm_irq: tpm-irq-pins { + samsung,pins = "gpx1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + trackpad_irq: trackpad-irq-pins { + samsung,pins = "gpx1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + power_key_irq: power-key-irq-pins { + samsung,pins = "gpx1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ec_irq: ec-irq-pins { + samsung,pins = "gpx1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + tps65090_irq: tps65090-irq-pins { + samsung,pins = "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + dp_hpd_gpio: dp-hpd-gpio-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + max77802_irq: max77802-irq-pins { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lid_irq: lid-irq-pins { + samsung,pins = "gpx3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_dvs_1: pmic-dvs-1-pins { + samsung,pins = "gpy7-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +/* pinctrl_1 */ +/* Adjust WiFi drive strengths lower for EMI */ +&sd1_bus1 { + samsung,pin-drv = ; +}; + +&sd1_bus4 { + samsung,pin-drv = ; +}; + +&sd1_bus8 { + samsung,pin-drv = ; +}; + +&sd1_clk { + samsung,pin-drv = ; +}; + +&sd1_cmd { + samsung,pin-drv = ; +}; + +&pinctrl_2 { + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpj4-2", "gpj4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +/* pinctrl_3*/ +/* Drive SPI lines at x2 for better integrity */ +&spi2_bus { + samsung,pin-drv = ; +}; + +&pinctrl_3 { + /* Drive SPI chip select at x2 for better integrity */ + ec_spi_cs: ec-spi-cs-pins { + samsung,pins = "gpb1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb300_vbus_en: usb300-vbus-en-pins { + samsung,pins = "gph0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb301_vbus_en: usb301-vbus-en-pins { + samsung,pins = "gph0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_selb: pmic-selb-pins { + samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", + "gph0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&spi_2 { + status = "okay"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_spi_cs &ec_irq>; + reg = <0>; + spi-max-frequency = <3125000>; + google,has-vbc-nvram; + + controller-data { + samsung,spi-feedback-delay = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + google,remote-bus = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + sbs,i2c-retry-count = <2>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + /* + * Config irq to disable internal pulls + * even though we run in polling mode. + */ + pinctrl-names = "default"; + pinctrl-0 = <&tps65090_irq>; + + vsys1-supply = <&vbat>; + vsys2-supply = <&vbat>; + vsys3-supply = <&vbat>; + infet1-supply = <&vbat>; + infet2-supply = <&tps65090_dcdc1>; + infet3-supply = <&tps65090_dcdc2>; + infet4-supply = <&tps65090_dcdc2>; + infet5-supply = <&tps65090_dcdc2>; + infet6-supply = <&tps65090_dcdc2>; + infet7-supply = <&tps65090_dcdc1>; + vsys-l1-supply = <&vbat>; + vsys-l2-supply = <&vbat>; + + regulators { + tps65090_dcdc1: dcdc1 { + ti,enable-ext-control; + }; + tps65090_dcdc2: dcdc2 { + ti,enable-ext-control; + }; + tps65090_dcdc3: dcdc3 { + ti,enable-ext-control; + }; + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + }; + tps65090_fet3: fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + }; + tps65090_fet4: fet4 { + regulator-name = "sdcard"; + regulator-always-on; + }; + tps65090_fet5: fet5 { + regulator-name = "camout"; + regulator-always-on; + }; + tps65090_fet6: fet6 { + regulator-name = "lcd_vdd"; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + }; + tps65090_ldo1: ldo1 { + }; + tps65090_ldo2: ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; +}; + +&serial_3 { + status = "okay"; +}; + +&timer { + arm,cpu-registers-not-fw-configured; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd3_0 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&usbdrd_phy0 { + vbus-supply = <&usb300_vbus_reg>; +}; + +&usbdrd_phy1 { + vbus-supply = <&usb301_vbus_reg>; +}; + +/* + * Use longest HW watchdog in SoC (32 seconds) since the hardware + * watchdog provides no debugging information (compared to soft/hard + * lockup detectors) and so should be last resort. + */ +&watchdog { + timeout-sec = <32>; +}; + +#include "../cros-ec-keyboard.dtsi" +#include "../cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi new file mode 100644 index 000000000000..93b9873fa84f --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include "exynos-pinctrl.h" + +&pinctrl_0 { + gpy7: gpy7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + dp_hpd: dp-hpd-pins { + samsung,pins = "gpx0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_cec: hdmi-cec-pins { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpc0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rclk: sd0-rclk-pins { + samsung,pins = "gpc0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpc1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpc1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_int: sd1-int-pins { + samsung,pins = "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus8: sd1-bus-width8-pins { + samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpc2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpc2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_wp: sd2-wp-pins { + samsung,pins = "gpc4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + cam_gpio_a: cam-gpio-a-pins { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_gpio_b: cam-gpio-b-pins { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c2_bus: cam-i2c2-bus-pins { + samsung,pins = "gpf0-4", "gpf0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_spi1_bus: cam-spi1-bus-pins { + samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c1_bus: cam-i2c1-bus-pins { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_i2c0_bus: cam-i2c0-bus-pins { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_spi0_bus: cam-spi0-bus-pins { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_bayrgb_bus: cam-bayrgb-bus-pins { + samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", + "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", + "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", + "gpg2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_3 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_hs_bus: i2c4-hs-bus-pins { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_hs_bus: i2c5-hs-bus-pins { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_hs_bus: i2c6-hs-bus-pins { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpb2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpb2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpb2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_hs_bus: i2c7-hs-bus-pins { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c8_hs_bus: i2c8-hs-bus-pins { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c9_hs_bus: i2c9-hs-bus-pins { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c10_hs_bus: i2c10-hs-bus-pins { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_4 { + gpz: gpz-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts b/arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts new file mode 100644 index 000000000000..e299344e427a --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung SMDK5420 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5420.dtsi" +#include "exynos5420-cpus.dtsi" +#include +#include + +/ { + model = "Samsung SMDK5420 board based on Exynos5420"; + compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; + }; + + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + + chosen { + bootargs = "init=/linuxrc"; + stdout-path = "serial2:115200n8"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + vdd: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + dbvdd: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "dbvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + spkvdd: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "spkvdd-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + usb300_vbus_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpg0 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb300_vbus_en>; + enable-active-high; + }; + + usb301_vbus_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VBUS1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpg1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb301_vbus_en>; + enable-active-high; + }; + +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&dp { + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <50000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vback-porch = <16>; + vfront-porch = <8>; + vsync-len = <6>; + }; + }; +}; + +&fimd { + status = "okay"; +}; + +&hdmi { + status = "okay"; + ddc = <&i2c_2>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + vdd-supply = <&ldo6_reg>; + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; +}; + +&hsi2c_4 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + wakeup-source; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "tsp_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c_2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + /* used by HDMI DDC */ + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + mmc-ddr-1_8v; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 + &sd0_rclk>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; +}; + +&pinctrl_0 { + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + usb300_vbus_en: usb300-vbus-en-pins { + samsung,pins = "gpg0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb301_vbus_en: usb301-vbus-en-pins { + samsung,pins = "gpg1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&usbdrd3_0 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd_phy0 { + vbus-supply = <&usb300_vbus_reg>; +}; + +&usbdrd_phy1 { + vbus-supply = <&usb301_vbus_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi new file mode 100644 index 000000000000..a67a380717ec --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree sources for default Exynos5420 thermal zone definition + * + * Copyright (c) 2014 Lukasz Majewski + */ + +polling-delay-passive = <0>; +polling-delay = <0>; +trips { + cpu-alert-0 { + temperature = <85000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu-alert-1 { + temperature = <103000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5420.dtsi b/arch/arm/boot/dts/samsung/exynos5420.dtsi new file mode 100644 index 000000000000..25ed90374679 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5420.dtsi @@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5420 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung Exynos5420 SoC device nodes are listed in this file. + * Exynos5420 based board files can include this file and provide + * values for board specific bindings. + */ + +#include "exynos54xx.dtsi" +#include +#include +#include + +/ { + compatible = "samsung,exynos5420", "samsung,exynos5"; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + i2c8 = &hsi2c_8; + i2c9 = &hsi2c_9; + i2c10 = &hsi2c_10; + gsc0 = &gsc_0; + gsc1 = &gsc_1; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + + bus_disp1: bus-disp1 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_DISP1>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_disp1_fimd: bus-disp1-fimd { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_DISP1>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys2: bus-fsys2 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys_apb: bus-fsys-apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_PCLK200_FSYS>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_g2d: bus-g2d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333_G2D>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_g2d_acp: bus-g2d-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266_G2D>; + clock-names = "bus"; + status = "disabled"; + }; + bus_gen: bus-gen { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_gscl_scaler: bus-gscl-scaler { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_GSCL>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_jpeg: bus-jpeg { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_JPEG>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_jpeg_apb: bus-jpeg-apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK166>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_mscl: bus-mscl { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_MSCL>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_noc: bus-noc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK100_NOC>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK66>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_wcore: bus-wcore { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_WCORE>; + clock-names = "bus"; + status = "disabled"; + }; + + /* + * The 'cpus' node is not present here but instead it is provided + * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. + */ + + cluster_a15_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000 1250000 1500000>; + clock-latency-ns = <140000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1212500 1212500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1175000 1175000 1500000>; + clock-latency-ns = <140000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1137500 1137500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1112500 1112500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500 1062500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500 1037500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500 1012500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = < 987500 987500 1500000>; + clock-latency-ns = <140000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = < 962500 962500 1500000>; + clock-latency-ns = <140000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = < 937500 937500 1500000>; + clock-latency-ns = <140000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = < 912500 912500 1500000>; + clock-latency-ns = <140000>; + }; + }; + + cluster_a7_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1162500>; + clock-latency-ns = <140000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + }; + + soc: soc { + cci: cci@10d20000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10d20000 0x1000>; + ranges = <0x0 0x10d20000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + clock: clock-controller@10010000 { + compatible = "samsung,exynos5420-clock", "syscon"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5420-audss-clock"; + reg = <0x03810000 0x0c>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, + <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + power-domains = <&mau_pd>; + }; + + mfc: codec@11000000 { + compatible = "samsung,mfc-v7"; + reg = <0x11000000 0x10000>; + interrupts = ; + clocks = <&clock CLK_MFC>; + clock-names = "mfc"; + power-domains = <&mfc_pd>; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; + + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + + nocp_mem0_0: nocp@10ca1000 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10ca1000 0x200>; + status = "disabled"; + }; + + nocp_mem0_1: nocp@10ca1400 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10ca1400 0x200>; + status = "disabled"; + }; + + nocp_mem1_0: nocp@10ca1800 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10ca1800 0x200>; + status = "disabled"; + }; + + nocp_mem1_1: nocp@10ca1c00 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10ca1c00 0x200>; + status = "disabled"; + }; + + nocp_g3d_0: nocp@11a51000 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x11a51000 0x200>; + status = "disabled"; + }; + + nocp_g3d_1: nocp@11a51400 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x11a51400 0x200>; + status = "disabled"; + }; + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 { + event-name = "ppmu-event3-dmc0-0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 { + event-name = "ppmu-event3-dmc0-1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 { + event-name = "ppmu-event3-dmc1-0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 { + event-name = "ppmu-event3-dmc1-1"; + }; + }; + }; + + gsc_pd: power-domain@10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + #power-domain-cells = <0>; + label = "GSC"; + }; + + isp_pd: power-domain@10044020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044020 0x20>; + #power-domain-cells = <0>; + label = "ISP"; + }; + + mfc_pd: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + #power-domain-cells = <0>; + label = "MFC"; + }; + + g3d_pd: power-domain@10044080 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044080 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; + + disp_pd: power-domain@100440c0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440c0 0x20>; + #power-domain-cells = <0>; + label = "DISP"; + }; + + mau_pd: power-domain@100440e0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440e0 0x20>; + #power-domain-cells = <0>; + label = "MAU"; + }; + + msc_pd: power-domain@10044120 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044120 0x20>; + #power-domain-cells = <0>; + label = "MSC"; + }; + + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = ; + }; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = ; + }; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = ; + }; + + pinctrl_4: pinctrl@3860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = ; + power-domains = <&mau_pd>; + }; + + adma: dma-controller@3880000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x03880000 0x1000>; + interrupts = ; + clocks = <&clock_audss EXYNOS_ADMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + power-domains = <&mau_pd>; + }; + + pdma0: dma-controller@121a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121a0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@121b0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121b0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + mdma0: dma-controller@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + mdma1: dma-controller@11c10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11c10000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + /* + * MDMA1 can support both secure and non-secure + * AXI transactions. When this is enabled in + * the kernel for boards that run in secure + * mode, we are getting imprecise external + * aborts causing the kernel to oops. + */ + status = "disabled"; + }; + + i2s0: i2s@3830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&adma 0>, + <&adma 2>, + <&adma 1>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + power-domains = <&mau_pd>; + status = "disabled"; + }; + + i2s1: i2s@12d60000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12d60000 0x100>; + dmas = <&pdma1 12>, + <&pdma1 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; + clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk1"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; + + i2s2: i2s@12d70000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12d70000 0x100>; + dmas = <&pdma0 12>, + <&pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; + clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk2"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + status = "disabled"; + }; + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = ; + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = ; + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = ; + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + dsi: dsi@14500000 { + compatible = "samsung,exynos5410-mipi-dsi"; + reg = <0x14500000 0x10000>; + interrupts = ; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; + clock-names = "bus_clk", "pll_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_8: i2c@12e00000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12e00000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_hs_bus>; + clocks = <&clock CLK_USI4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_9: i2c@12e10000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12e10000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_hs_bus>; + clocks = <&clock CLK_USI5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_10: i2c@12e20000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12e20000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c10_hs_bus>; + clocks = <&clock CLK_USI6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hdmi: hdmi@14530000 { + compatible = "samsung,exynos5420-hdmi"; + reg = <0x14530000 0x70000>; + interrupts = ; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + phy = <&hdmiphy>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + power-domains = <&disp_pd>; + #sound-dai-cells = <0>; + }; + + hdmiphy: hdmi-phy@145d0000 { + reg = <0x145d0000 0x20>; + }; + + hdmicec: cec@101b0000 { + compatible = "samsung,s5p-cec"; + reg = <0x101b0000 0x200>; + interrupts = ; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; + + mixer: mixer@14450000 { + compatible = "samsung,exynos5420-mixer"; + reg = <0x14450000 0x10000>; + interrupts = ; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>; + clock-names = "mixer", "hdmi", "sclk_hdmi"; + power-domains = <&disp_pd>; + iommus = <&sysmmu_tv>; + status = "disabled"; + }; + + rotator: rotator@11c00000 { + compatible = "samsung,exynos5250-rotator"; + reg = <0x11c00000 0x64>; + interrupts = ; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; + + gsc_0: video-scaler@13e00000 { + compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = ; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl0>; + }; + + gsc_1: video-scaler@13e10000 { + compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = ; + clocks = <&clock CLK_GSCL1>; + clock-names = "gscl"; + power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl1>; + }; + + gpu: gpu@11800000 { + compatible = "samsung,exynos5420-mali", "arm,mali-t628"; + reg = <0x11800000 0x5000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&clock CLK_G3D>; + clock-names = "core"; + power-domains = <&g3d_pd>; + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + #cooling-cells = <2>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-microvolt = <812500>; + }; + opp-266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <862500>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <912500>; + }; + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <962500>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1000000>; + }; + opp-543000000 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <1037500>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1150000>; + }; + }; + }; + + scaler_0: scaler@12800000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12800000 0x1294>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL0>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; + }; + + scaler_1: scaler@12810000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12810000 0x1294>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL1>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; + }; + + scaler_2: scaler@12820000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12820000 0x1294>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL2>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; + }; + + jpeg_0: jpeg@11f50000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11f50000 0x1000>; + interrupts = ; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG>; + iommus = <&sysmmu_jpeg0>; + }; + + jpeg_1: jpeg@11f60000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11f60000 0x1000>; + interrupts = ; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG2>; + iommus = <&sysmmu_jpeg1>; + }; + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon"; + reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + #clock-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + + dp_phy: dp-phy { + compatible = "samsung,exynos5420-dp-video-phy"; + #phy-cells = <0>; + }; + + mipi_phy: mipi-phy { + compatible = "samsung,exynos5420-mipi-video-phy"; + #phy-cells = <1>; + }; + }; + + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x10068000 0x100>, <0x1006c000 0x4>; + interrupts = ; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x1006c000 0x100>, <0x100a0000 0x4>; + interrupts = ; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #thermal-sensor-cells = <0>; + }; + + tmu_gpu: tmu@100a0000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x100a0000 0x100>, <0x10068000 0x4>; + interrupts = ; + clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #thermal-sensor-cells = <0>; + }; + + sysmmu_g2dr: sysmmu@10a60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10a60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_g2dw: sysmmu@10a70000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10a70000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl0: sysmmu@13e80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13e80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl1: sysmmu@13e90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13e90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0r: sysmmu@12880000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12880000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1r: sysmmu@12890000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12890000 0x1000>; + interrupts = ; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2r: sysmmu@128a0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128a0000 0x1000>; + interrupts = ; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0w: sysmmu@128c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128c0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <27 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1w: sysmmu@128d0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128d0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2w: sysmmu@128e0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128e0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <19 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@11d40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11d40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg0: sysmmu@11f10000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11f10000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg1: sysmmu@11f20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11f20000 0x1000>; + interrupts = ; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_0: sysmmu@14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_1: sysmmu@14680000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14680000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + #include "exynos5420-trip-points.dtsi" + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" + }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu>; + #include "exynos5420-trip-points.dtsi" + }; + }; +}; + +&adc { + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + +&dp { + clocks = <&clock CLK_DP1>; + clock-names = "dp"; + phys = <&dp_phy>; + phy-names = "dp"; + power-domains = <&disp_pd>; +}; + +&fimd { + compatible = "samsung,exynos5420-fimd"; + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; + clock-names = "sclk_fimd", "fimd"; + power-domains = <&disp_pd>; + iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; + iommu-names = "m0", "m1"; +}; + +&g2d { + iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; + clocks = <&clock CLK_G2D>; + clock-names = "fimg2d"; + status = "okay"; +}; + +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&hsi2c_4 { + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; +}; + +&hsi2c_5 { + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; +}; + +&hsi2c_6 { + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; +}; + +&hsi2c_7 { + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; +}; + +&mct { + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; +}; + +&prng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; + +&rtc { + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&pmu_system_controller>; + status = "disabled"; +}; + +&serial_0 { + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 13>, <&pdma0 14>; + dma-names = "rx", "tx"; +}; + +&serial_1 { + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; +}; + +&serial_2 { + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; +}; + +&serial_3 { + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; +}; + +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&trng { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + +&usbdrd3_0 { + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy0 { + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbdrd3_1 { + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; +}; + +&usbdrd_dwc3_1 { + interrupts = ; +}; + +&usbdrd_phy1 { + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbhost1 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usbhost2 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usb2_phy { + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; +}; + +&watchdog { + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + +#include "exynos5420-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi new file mode 100644 index 000000000000..412a0bb4b988 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. + * + * The Exynos5420, 5422 and 5800 actually share the same CPU configuration + * but particular boards choose different booting order. + * + * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 + * booting cluster (big or LITTLE) is chosen by IROM code by reading + * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting + * from the LITTLE: Cortex-A7. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; + }; + + cpu1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; + }; + + cpu2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; + }; + + cpu3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; + }; + + cpu4: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; + }; + + cpu5: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; + }; + + cpu6: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; + }; + + cpu7: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; + }; + }; +}; + +&arm_a7_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi new file mode 100644 index 000000000000..2f5b8602e020 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi @@ -0,0 +1,1072 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source + * + * Copyright (c) 2017 Marek Szyprowski + * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +#include +#include +#include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x7ea00000>; + }; + + aliases { + mmc2 = &mmc_2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + bus_wcore_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + /* derived from 532MHz MPLL */ + opp00 { + opp-hz = /bits/ 64 <88700000>; + opp-microvolt = <925000 925000 1400000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + opp-microvolt = <950000 950000 1400000>; + }; + opp02 { + opp-hz = /bits/ 64 <177400000>; + opp-microvolt = <950000 950000 1400000>; + }; + opp03 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <950000 950000 1400000>; + }; + opp04 { + opp-hz = /bits/ 64 <532000000>; + opp-microvolt = <1000000 1000000 1400000>; + }; + }; + + bus_noc_opp_table: opp-table-3 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <66600000>; + }; + opp01 { + opp-hz = /bits/ 64 <74000000>; + }; + opp02 { + opp-hz = /bits/ 64 <83250000>; + }; + opp03 { + opp-hz = /bits/ 64 <111000000>; + }; + }; + + bus_fsys_apb_opp_table: opp-table-4 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <111000000>; + }; + opp01 { + opp-hz = /bits/ 64 <222000000>; + }; + }; + + bus_fsys2_opp_table: opp-table-5 { + compatible = "operating-points-v2"; + + /* derived from 600MHz DPLL */ + opp00 { + opp-hz = /bits/ 64 <75000000>; + }; + opp01 { + opp-hz = /bits/ 64 <120000000>; + }; + opp02 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_mfc_opp_table: opp-table-6 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <83250000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <166500000>; + }; + opp03 { + opp-hz = /bits/ 64 <222000000>; + }; + opp04 { + opp-hz = /bits/ 64 <333000000>; + }; + }; + + bus_gen_opp_table: opp-table-7 { + compatible = "operating-points-v2"; + + /* derived from 532MHz MPLL */ + opp00 { + opp-hz = /bits/ 64 <88700000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + }; + opp02 { + opp-hz = /bits/ 64 <178000000>; + }; + opp03 { + opp-hz = /bits/ 64 <266000000>; + }; + }; + + bus_peri_opp_table: opp-table-8 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <66600000>; + }; + }; + + bus_g2d_opp_table: opp-table-9 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <83250000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <166500000>; + }; + opp03 { + opp-hz = /bits/ 64 <222000000>; + }; + opp04 { + opp-hz = /bits/ 64 <333000000>; + }; + }; + + bus_g2d_acp_opp_table: opp-table-10 { + compatible = "operating-points-v2"; + + /* derived from 532MHz MPLL */ + opp00 { + opp-hz = /bits/ 64 <66500000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + }; + opp02 { + opp-hz = /bits/ 64 <178000000>; + }; + opp03 { + opp-hz = /bits/ 64 <266000000>; + }; + }; + + bus_jpeg_opp_table: opp-table-11 { + compatible = "operating-points-v2"; + + /* derived from 600MHz DPLL */ + opp00 { + opp-hz = /bits/ 64 <75000000>; + }; + opp01 { + opp-hz = /bits/ 64 <150000000>; + }; + opp02 { + opp-hz = /bits/ 64 <200000000>; + }; + opp03 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_jpeg_apb_opp_table: opp-table-12 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <83250000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <133000000>; + }; + opp03 { + opp-hz = /bits/ 64 <166500000>; + }; + }; + + bus_disp1_fimd_opp_table: opp-table-13 { + compatible = "operating-points-v2"; + + /* derived from 600MHz DPLL */ + opp00 { + opp-hz = /bits/ 64 <120000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_disp1_opp_table: opp-table-14 { + compatible = "operating-points-v2"; + + /* derived from 600MHz DPLL */ + opp00 { + opp-hz = /bits/ 64 <120000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_gscl_opp_table: opp-table-15 { + compatible = "operating-points-v2"; + + /* derived from 600MHz DPLL */ + opp00 { + opp-hz = /bits/ 64 <150000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_mscl_opp_table: opp-table-16 { + compatible = "operating-points-v2"; + + /* derived from 666MHz CPLL */ + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <167000000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + }; + opp03 { + opp-hz = /bits/ 64 <333000000>; + }; + opp04 { + opp-hz = /bits/ 64 <666000000>; + }; + }; + + dmc_opp_table: opp-table-17 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: timings { + compatible = "jedec,lpddr3-timings"; + max-freq = <800000000>; + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; +}; + +&adc { + vdd-supply = <&ldo4_reg>; + status = "okay"; +}; + +&bus_wcore { + operating-points-v2 = <&bus_wcore_opp_table>; + devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, + <&nocp_mem1_0>, <&nocp_mem1_1>; + vdd-supply = <&buck3_reg>; + exynos,saturation-ratio = <100>; + status = "okay"; +}; + +&bus_noc { + operating-points-v2 = <&bus_noc_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys_apb { + operating-points-v2 = <&bus_fsys_apb_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys2 { + operating-points-v2 = <&bus_fsys2_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_mfc { + operating-points-v2 = <&bus_mfc_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_gen { + operating-points-v2 = <&bus_gen_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_peri { + operating-points-v2 = <&bus_peri_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_g2d { + operating-points-v2 = <&bus_g2d_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_g2d_acp { + operating-points-v2 = <&bus_g2d_acp_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_jpeg { + operating-points-v2 = <&bus_jpeg_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_jpeg_apb { + operating-points-v2 = <&bus_jpeg_apb_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_disp1_fimd { + operating-points-v2 = <&bus_disp1_fimd_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_disp1 { + operating-points-v2 = <&bus_disp1_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_gscl_scaler { + operating-points-v2 = <&bus_gscl_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_mscl { + operating-points-v2 = <&bus_mscl_opp_table>; + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&buck6_reg>; +}; + +&cpu4 { + cpu-supply = <&buck2_reg>; +}; + +&dmc { + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&hsi2c_4 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + samsung,s2mps11-acokb-ground; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + wakeup-source; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vddq_mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + /* Unused */ + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + /* Unused */ + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + /* Unused */ + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_ldo17"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo18_reg: LDO18 { + regulator-name = "vdd_emmc_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + /* Unused */ + regulator-name = "vdd_ldo20"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo21_reg: LDO21 { + /* Unused */ + regulator-name = "vdd_ldo21"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo22_reg: LDO22 { + /* Unused */ + regulator-name = "vdd_ldo22"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + /* Unused */ + regulator-name = "vdd_ldo24"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo25_reg: LDO25 { + /* Unused */ + regulator-name = "vdd_ldo25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo26_reg: LDO26 { + /* Used on XU3, XU3-Lite and XU4 */ + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + /* Used on XU3 */ + regulator-name = "vdd_ldo28"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo29_reg: LDO29 { + /* Unused */ + regulator-name = "vdd_ldo29"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo30_reg: LDO30 { + /* Unused */ + regulator-name = "vdd_ldo30"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo31_reg: LDO31 { + /* Unused */ + regulator-name = "vdd_ldo31"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo32_reg: LDO32 { + /* Unused */ + regulator-name = "vdd_ldo32"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo33_reg: LDO33 { + /* Unused */ + regulator-name = "vdd_ldo33"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo34_reg: LDO34 { + /* Unused */ + regulator-name = "vdd_ldo34"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo35_reg: LDO35 { + /* Unused */ + regulator-name = "vdd_ldo35"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "vdd_ldo36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "vdd_ldo37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + /* Unused */ + regulator-name = "vdd_ldo38"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.35v_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_2.0v_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <200000000>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&nocp_mem0_0 { + status = "okay"; +}; + +&nocp_mem0_1 { + status = "okay"; +}; + +&nocp_mem1_0 { + status = "okay"; +}; + +&nocp_mem1_1 { + status = "okay"; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo7_reg>; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +/* usbdrd_dwc3_1 mode customized in each board */ + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts new file mode 100644 index 000000000000..5e4280393706 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid HC1 board device tree source + * + * Copyright (c) 2017 Marek Szyprowski + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include +#include "exynos5422-odroid-core.dtsi" + +/ { + model = "Hardkernel Odroid HC1"; + compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ + "samsung,exynos5"; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + trips { + cpu0_alert0: cpu-alert-0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu0_alert1: cpu-alert-1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu0_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * When reaching cpu0_alert0, reduce CPU + * by 2 steps. On Exynos5422/5800 that would + * be: 1600 MHz and 1100 MHz. + */ + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + /* + * When reaching cpu0_alert1, reduce CPU + * further, down to 600 MHz (12 steps for big, + * 7 steps for LITTLE). + */ + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu>; + trips { + gpu_alert0: gpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + gpu_alert1: gpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + gpu_crit0: gpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu 0 2>; + }; + map1 { + trip = <&gpu_alert1>; + cooling-device = <&gpu 3 6>; + }; + }; + }; + }; + +}; + +&pwm { + /* + * PWM 2 -- Blue LED + */ + pinctrl-0 = <&pwm2_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <2>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi new file mode 100644 index 000000000000..86b96f9706db --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU3 audio subsystem device tree source + * + * Copyright (c) 2015 Krzysztof Kozlowski + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include + +/ { + sound: sound { + compatible = "samsung,odroid-xu3-audio"; + model = "Odroid-XU3"; + + samsung,audio-widgets = + "Headphone", "Headphone Jack", + "Speakers", "Speakers"; + samsung,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN12", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR", + "I2S Playback", "Mixer DAI TX", + "HiFi Playback", "Mixer DAI TX", + "Mixer DAI RX", "HiFi Capture"; + + cpu { + sound-dai = <&i2s0 0>, <&i2s0 1>; + }; + codec { + sound-dai = <&hdmi>, <&max98090>; + }; + }; +}; + +&hsi2c_5 { + status = "okay"; + max98090: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_NONE>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; + +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi new file mode 100644 index 000000000000..b4a851aa8881 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2015 Lukasz Majewski + * Anand Moon + */ + +#include +#include "exynos5422-odroid-core.dtsi" + +/ { + aliases { + mmc0 = &mmc_0; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power-key { + /* + * The power button (SW2) is connected to the PWRON + * pin (active high) of the S2MPS11 PMIC, which acts + * as a 16ms debouce filter and signal inverter with + * output on ONOB pin (active low). ONOB PMIC pin is + * then connected to XEINT3 SoC pin. + */ + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power key"; + debounce-interval = <0>; + wakeup-source; + }; + }; + + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_nrst_pin>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 20972 0>; + #cooling-cells = <2>; + cooling-levels = <0 130 170 230>; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu0_alert0: cpu-alert-0 { + temperature = <50000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu0_alert1: cpu-alert-1 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu0_alert2: cpu-alert-2 { + temperature = <70000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu0_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + /* + * Exynos542x supports only 4 trip-points + * so for these polling mode is required. + * Start polling at temperature level of last + * interrupt-driven trip: cpu0_alert2 + */ + cpu0_alert3: cpu-alert-3 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu0_alert4: cpu-alert-4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu0_alert2>; + cooling-device = <&fan0 2 3>; + }; + /* + * When reaching cpu0_alert3, reduce CPU + * by 2 steps. On Exynos5422/5800 that would + * (usually) be: 1800 MHz and 1200 MHz. + */ + map3 { + trip = <&cpu0_alert3>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + /* + * When reaching cpu0_alert4, reduce CPU + * further, down to 600 MHz (14 steps for big, + * 8 steps for LITTLE). + */ + cpu0_cooling_map4: map4 { + trip = <&cpu0_alert4>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu1_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu1_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu1_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu1_alert3>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + cpu1_cooling_map4: map4 { + trip = <&cpu1_alert4>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu2_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu2_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu2_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu2_alert3>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + cpu2_cooling_map4: map4 { + trip = <&cpu2_alert4>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu3_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu3_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu3_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu3_alert3>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; + }; + cpu3_cooling_map4: map4 { + trip = <&cpu3_alert4>; + cooling-device = <&cpu0 3 8>, + <&cpu1 3 8>, + <&cpu2 3 8>, + <&cpu3 3 8>, + <&cpu4 3 14>, + <&cpu5 3 14>, + <&cpu6 3 14>, + <&cpu7 3 14>; + }; + }; + }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + gpu_alert0: gpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_alert1: gpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_alert2: gpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_crit0: gpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + gpu_alert3: gpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + gpu_alert4: gpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&gpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&gpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&gpu_alert3>; + cooling-device = <&gpu 0 2>; + }; + map4 { + trip = <&gpu_alert4>; + cooling-device = <&gpu 3 6>; + }; + }; + }; + }; +}; + +&buck10_reg { + /* Supplies vmmc-supply of mmc_0 */ + regulator-always-on; + regulator-boot-on; +}; + +&hdmi { + status = "okay"; + ddc = <&i2c_2>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; + vdd-supply = <&ldo6_reg>; +}; + +&hdmicec { + status = "okay"; + needs-hpd; +}; + +&i2c_2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + /* used by HDMI DDC */ + status = "okay"; +}; + +&ldo26_reg { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; +}; + +&mixer { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + mmc-pwrseq = <&emmc_pwrseq>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + max-frequency = <200000000>; + vmmc-supply = <&ldo18_reg>; + vqmmc-supply = <&ldo3_reg>; +}; + +&pinctrl_0 { + power_key: power-key-pins { + samsung,pins = "gpx0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + emmc_nrst_pin: emmc-nrst-pins { + samsung,pins = "gpd1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts new file mode 100644 index 000000000000..e3154a1cae23 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU3-Lite board device tree source + * + * Copyright (c) 2015 Krzysztof Kozlowski + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5422-odroidxu3-common.dtsi" +#include "exynos5422-odroidxu3-audio.dtsi" +#include "exynos54xx-odroidxu-leds.dtsi" + +/ { + model = "Hardkernel Odroid XU3 Lite"; + compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + }; +}; + +&arm_a7_pmu { + status = "disabled"; +}; + +&arm_a15_pmu { + status = "disabled"; +}; + +&chipid { + samsung,asv-bin = <2>; +}; + +/* + * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies + * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores. + * Therefore we need to update OPPs tables and thermal maps accordingly. + */ +&cluster_a15_opp_table { + /delete-node/opp-2000000000; + /delete-node/opp-1900000000; +}; + +&cluster_a7_opp_table { + /delete-node/opp-1400000000; +}; + +&cpu0_cooling_map4 { + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; +}; + +&cpu1_cooling_map4 { + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; +}; + +&cpu2_cooling_map4 { + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; +}; + +&cpu3_cooling_map4 { + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; +}; + +&pwm { + /* + * PWM 0 -- fan + * PWM 1 -- Green LED + * PWM 2 -- Blue LED + * PWM 3 -- on MIPI connector for backlight + */ + pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts new file mode 100644 index 000000000000..a378d4937ff7 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU3 board device tree source + * + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos5422-odroidxu3-common.dtsi" +#include "exynos5422-odroidxu3-audio.dtsi" +#include "exynos54xx-odroidxu-leds.dtsi" + +/ { + model = "Hardkernel Odroid XU3"; + compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + }; +}; + +&i2c_0 { + status = "okay"; + + /* A15 cluster: VDD_ARM */ + power-sensor@40 { + compatible = "ti,ina231"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* memory: VDD_MEM */ + power-sensor@41 { + compatible = "ti,ina231"; + reg = <0x41>; + shunt-resistor = <10000>; + }; + + /* GPU: VDD_G3D */ + power-sensor@44 { + compatible = "ti,ina231"; + reg = <0x44>; + shunt-resistor = <10000>; + }; + + /* A7 cluster: VDD_KFC */ + power-sensor@45 { + compatible = "ti,ina231"; + reg = <0x45>; + shunt-resistor = <10000>; + }; +}; + +&ldo28_reg { + regulator-name = "dp_p3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&pwm { + /* + * PWM 0 -- fan + * PWM 1 -- Green LED + * PWM 2 -- Blue LED + * PWM 3 -- on MIPI connector for backlight + */ + pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts new file mode 100644 index 000000000000..f5fb617f46bd --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU4 board device tree source + * + * Copyright (c) 2015 Krzysztof Kozlowski + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include +#include +#include "exynos5422-odroidxu3-common.dtsi" + +/ { + model = "Hardkernel Odroid XU4"; + compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ + "samsung,exynos5"; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound: sound { + compatible = "samsung,odroid-xu3-audio"; + model = "Odroid-XU4"; + + samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; + + cpu { + sound-dai = <&i2s0 0>, <&i2s0 1>; + }; + + codec { + sound-dai = <&hdmi>; + }; + }; +}; + +&i2s0 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; +}; + +&pwm { + /* + * PWM 0 -- fan + * PWM 2 -- Blue LED + */ + pinctrl-0 = <&pwm0_out &pwm2_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>, <2>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts new file mode 100644 index 000000000000..c35261a338ff --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts @@ -0,0 +1,679 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy S5 (SM-G900H) device-tree source + * + * Copyright (c) 2023 Markuss Broks + */ + +/dts-v1/; +#include +#include +#include +#include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" + +/ { + model = "Samsung Galaxy S5 (SM-G900H)"; + compatible = "samsung,k3g", "samsung,exynos5800", \ + "samsung,exynos5"; + + chassis-type = "handset"; + + aliases { + mmc0 = &mmc_0; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; /* 2 GiB */ + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + tsp_vdd: regulator-tsp-vdd-en { + compatible = "regulator-fixed"; + regulator-name = "tsp_vdd_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpy3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&gpu { + status = "okay"; + mali-supply = <&buck4_reg>; +}; + +&hsi2c_7 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_KFC"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "VDD_CAM_ISP"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3550000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_APIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_APIO_MMC01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_ADC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_HRM_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_MIPI_PLL_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_VTF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_UOTG"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_HSIC_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_APIO_MMC2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD_MOTOR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD_CAM1_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + /* Unused */ + regulator-name = "VDD_LDO17"; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_CODEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_VMMC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD_CAM1_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_CAM_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "VDD_CAM0_S_CORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD_MIFS"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD_MHL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD_CAM0_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "VDD_G3DS"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "VDD_LCD_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo29_reg: LDO29 { + /* Unused */ + regulator-name = "VDD_LDO29"; + }; + + ldo30_reg: LDO30 { + regulator-name = "VDD_TOUCH"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo31_reg: LDO31 { + regulator-name = "VDD_COMP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo32_reg: LDO32 { + regulator-name = "VDD_TOUCH_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo33_reg: LDO33 { + regulator-name = "VDD_MHL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo34_reg: LDO34 { + regulator-name = "VDD_HRM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo35_reg: LDO35 { + regulator-name = "VDD_SIL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "VDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "VDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VDD_KEY_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c_0 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupt-parent = <&gpx1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + vio-supply = <&ldo32_reg>; + vdd-supply = <&tsp_vdd>; + syna,startup-delay-ms = <100>; + + pinctrl-0 = <&touch_irq>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +/* eMMC flash */ +&mmc_0 { + status = "okay"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + cap-mmc-highspeed; + non-removable; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; + bus-width = <8>; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touch_irq: touch-irq-pins { + samsung,pins = "gpx1-6"; + samsung,pin-pud = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&timer { + arm,cpu-registers-not-fw-configured; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi new file mode 100644 index 000000000000..8c0e1716c0b3 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardkernel Odroid XU/XU3 LED device tree source + * + * Copyright (c) 2015,2016 Krzysztof Kozlowski + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +#include + +/ { + led-controller-1 { + compatible = "pwm-leds"; + + led-1 { + label = "green:mmc0"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = ; + pwms = <&pwm 1 2000000 0>; + pwm-names = "pwm1"; + /* + * Green LED is much brighter than the others + * so limit its max brightness + */ + max-brightness = <127>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + + led-3 { + label = "red:microSD"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = ; + gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos54xx.dtsi b/arch/arm/boot/dts/samsung/exynos54xx.dtsi new file mode 100644 index 000000000000..5c799886c275 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos54xx.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos54xx SoC series common device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2016 Krzysztof Kozlowski + * + * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific + * Exynos 54xx SoCs should include this file and customize it further + * (e.g. with clocks). + */ + +#include "exynos5.dtsi" + +/ { + compatible = "samsung,exynos5"; + + aliases { + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + usbdrdphy0 = &usbdrd_phy0; + usbdrdphy1 = &usbdrd_phy1; + }; + + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + status = "disabled"; + }; + + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + + timer: timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + soc: soc { + sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; + + mct: timer@101c0000 { + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; + reg = <0x101c0000 0xb00>; + interrupts-extended = <&combiner 23 3>, + <&combiner 23 4>, + <&combiner 25 2>, + <&combiner 25 3>, + <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@101d0000 { + compatible = "samsung,exynos5420-wdt"; + reg = <0x101d0000 0x100>; + interrupts = ; + }; + + adc: adc@12d10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12d10000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + status = "disabled"; + }; + + /* i2c_0-3 are defined in exynos5.dtsi */ + hsi2c_4: i2c@12ca0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12ca0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_5: i2c@12cb0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12cb0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_6: i2c@12cc0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12cc0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_7: i2c@12cd0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12cd0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usbdrd3_0: usb@12000000 { + compatible = "samsung,exynos5250-dwusb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000000 0x10000>; + + usbdrd_dwc3_0: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; + }; + }; + + usbdrd_phy0: phy@12100000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12100000 0x100>; + #phy-cells = <1>; + }; + + usbdrd3_1: usb@12400000 { + compatible = "samsung,exynos5250-dwusb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12400000 0x10000>; + + usbdrd_dwc3_1: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; + }; + }; + + usbdrd_phy1: phy@12500000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12500000 0x100>; + #phy-cells = <1>; + }; + + usbhost2: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = ; + phys = <&usb2_phy 0>; + phy-names = "host"; + }; + + usbhost1: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = ; + phys = <&usb2_phy 0>; + phy-names = "host"; + }; + + usb2_phy: phy@12130000 { + compatible = "samsung,exynos5420-usb2-phy"; + reg = <0x12130000 0x100>; + #phy-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts new file mode 100644 index 000000000000..f91bc4ae008e --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -0,0 +1,1108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Peach Pi Rev 10+ board device tree source + * + * Copyright (c) 2014 Google, Inc + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "exynos5800.dtsi" +#include "exynos5420-cpus.dtsi" + +/ { + model = "Google Peach Pi Rev 10+"; + + compatible = "google,pi-rev16", + "google,pi-rev15", "google,pi-rev14", + "google,pi-rev13", "google,pi-rev12", + "google,pi-rev11", "google,pi-rev10", + "google,pi", "google,peach", "samsung,exynos5800", + "samsung,exynos5"; + chassis-type = "laptop"; + + aliases { + /* Assign 20 so we don't get confused w/ builtin ones */ + i2c20 = &i2c_tunnel; + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_2; /* SD */ + mmc2 = &mmc_1; /* WiFi */ + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + power-supply = <&tps65090_fet1>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq &lid_irq>; + + power-key { + label = "Power"; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + wakeup-source; + }; + + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; + }; + + sound { + compatible = "google,snow-audio-max98091"; + + samsung,model = "Peach-Pi-I2S-MAX98091"; + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98091>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98091>, <&hdmi>; + }; + }; + + usb300_vbus_reg: regulator-usb300 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb300_vbus_en>; + enable-active-high; + }; + + usb301_vbus_reg: regulator-usb301 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb301_vbus_en>; + enable-active-high; + }; + + vbat: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat-supply"; + regulator-boot-on; + regulator-always-on; + }; + + panel: panel { + compatible = "auo,b133htn01"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + + mmc1_pwrseq: mmc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + clocks = <&max77802 MAX77802_CLK_32K_CP>; + clock-names = "ext_clock"; + }; +}; + +&adc { + status = "okay"; + vdd-supply = <&ldo9_reg>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_MAU_EPLL>; +}; + +/* + * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores + * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to + * update A7 OPPs table accordingly. + */ +&cluster_a7_opp_table { + /delete-node/opp-1400000000; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + ports { + port { + dp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + status = "okay"; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; + + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&hsi2c_4 { + status = "okay"; + clock-frequency = <400000>; + + max77802: pmic@9 { + compatible = "maxim,max77802"; + interrupt-parent = <&gpx3>; + interrupts = <1 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_selb>, + <&pmic_dvs_1>, <&pmic_dvs_2>; + wakeup-source; + reg = <0x9>; + #clock-cells = <1>; + + inb1-supply = <&tps65090_dcdc2>; + inb2-supply = <&tps65090_dcdc1>; + inb3-supply = <&tps65090_dcdc2>; + inb4-supply = <&tps65090_dcdc2>; + inb5-supply = <&tps65090_dcdc1>; + inb6-supply = <&tps65090_dcdc2>; + inb7-supply = <&tps65090_dcdc1>; + inb8-supply = <&tps65090_dcdc1>; + inb9-supply = <&tps65090_dcdc1>; + inb10-supply = <&tps65090_dcdc1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&tps65090_dcdc2>; + inl7-supply = <&buck9_reg>; + inl9-supply = <&tps65090_dcdc2>; + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2v"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_1v2_2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_1v8_3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + vqmmc_sdcard: ldo4_reg: LDO4 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_1v8_5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_1v8_6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_1v8_7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo_19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "ldo_20"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "ldo_21"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "ldo_23"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ldo24_reg: LDO24 { + regulator-name = "ldo_24"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "ldo_25"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "ldo_26"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo_27"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo_28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo_29"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo32_reg: LDO32 { + regulator-name = "ldo_32"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo_33"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo_34"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo_35"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; +}; + +&hsi2c_7 { + status = "okay"; + clock-frequency = <400000>; + + max98091: codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + interrupts = <2 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98091_irq>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + light-sensor@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + vcc-supply = <&tps65090_fet5>; + }; +}; + +&hsi2c_8 { + status = "okay"; + clock-frequency = <333000>; + /* Atmel mXT540S */ + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = ; /* GPIO 3 */ + }; +}; + +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; + }; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; +}; + +&i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; + status = "okay"; +}; + +&mixer { + status = "okay"; +}; + +/* eMMC flash */ +&mmc_0 { + status = "okay"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + clock-frequency = <800000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; + bus-width = <8>; +}; + +/* WiFi SDIO module */ +&mmc_1 { + status = "okay"; + non-removable; + cap-sdio-irq; + keep-power-in-suspend; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; + bus-width = <4>; + cap-sd-highspeed; + mmc-pwrseq = <&mmc1_pwrseq>; + vqmmc-supply = <&buck10_reg>; +}; + +/* uSD card */ +&mmc_2 { + status = "okay"; + cap-sd-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; +}; + + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&mask_tpm_reset>; + + wifi_en: wifi-en-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + max98091_irq: max98091-irq-pins { + samsung,pins = "gpx0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* We need GPX0_6 to be low at sleep time; just keep it low always */ + mask_tpm_reset: mask-tpm-reset-pins { + samsung,pins = "gpx0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + tpm_irq: tpm-irq-pins { + samsung,pins = "gpx1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + trackpad_irq: trackpad-irq-pins { + samsung,pins = "gpx1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + power_key_irq: power-key-irq-pins { + samsung,pins = "gpx1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ec_irq: ec-irq-pins { + samsung,pins = "gpx1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + tps65090_irq: tps65090-irq-pins { + samsung,pins = "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + dp_hpd_gpio: dp-hpd-gpio-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + max77802_irq: max77802-irq-pins { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lid_irq: lid-irq-pins { + samsung,pins = "gpx3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_hpd_irq: hdmi-hpd-irq-pins { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_dvs_1: pmic-dvs-1-pins { + samsung,pins = "gpy7-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +/* pinctrl_1 */ +/* Adjust WiFi drive strengths lower for EMI */ +&sd1_bus1 { + samsung,pin-drv = ; +}; + +&sd1_bus4 { + samsung,pin-drv = ; +}; + +&sd1_bus8 { + samsung,pin-drv = ; +}; + +&sd1_clk { + samsung,pin-drv = ; +}; + +&sd1_cmd { + samsung,pin-drv = ; +}; + +&pinctrl_2 { + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpj4-2", "gpj4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +/* pinctrl_3*/ +/* Drive SPI lines at x2 for better integrity */ +&spi2_bus { + samsung,pin-drv = ; +}; + +&pinctrl_3 { + /* Drive SPI chip select at x2 for better integrity */ + ec_spi_cs: ec-spi-cs-pins { + samsung,pins = "gpb1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb300_vbus_en: usb300-vbus-en-pins { + samsung,pins = "gph0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb301_vbus_en: usb301-vbus-en-pins { + samsung,pins = "gph0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_selb: pmic-selb-pins { + samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", + "gph0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&spi_2 { + status = "okay"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_spi_cs &ec_irq>; + reg = <0>; + spi-max-frequency = <3125000>; + google,has-vbc-nvram; + + controller-data { + samsung,spi-feedback-delay = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + google,remote-bus = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + sbs,i2c-retry-count = <2>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + /* + * Config irq to disable internal pulls + * even though we run in polling mode. + */ + pinctrl-names = "default"; + pinctrl-0 = <&tps65090_irq>; + + vsys1-supply = <&vbat>; + vsys2-supply = <&vbat>; + vsys3-supply = <&vbat>; + infet1-supply = <&vbat>; + infet2-supply = <&tps65090_dcdc1>; + infet3-supply = <&tps65090_dcdc2>; + infet4-supply = <&tps65090_dcdc2>; + infet5-supply = <&tps65090_dcdc2>; + infet6-supply = <&tps65090_dcdc2>; + infet7-supply = <&tps65090_dcdc1>; + vsys-l1-supply = <&vbat>; + vsys-l2-supply = <&vbat>; + + regulators { + tps65090_dcdc1: dcdc1 { + ti,enable-ext-control; + }; + tps65090_dcdc2: dcdc2 { + ti,enable-ext-control; + }; + tps65090_dcdc3: dcdc3 { + ti,enable-ext-control; + }; + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + }; + tps65090_fet3: fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + }; + tps65090_fet4: fet4 { + regulator-name = "sdcard"; + regulator-always-on; + }; + tps65090_fet5: fet5 { + regulator-name = "camout"; + regulator-always-on; + }; + tps65090_fet6: fet6 { + regulator-name = "lcd_vdd"; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + }; + tps65090_ldo1: ldo1 { + }; + tps65090_ldo2: ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; +}; + +&serial_3 { + status = "okay"; +}; + +&timer { + arm,cpu-registers-not-fw-configured; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd3_0 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&usbdrd_phy0 { + vbus-supply = <&usb300_vbus_reg>; +}; + +&usbdrd_phy1 { + vbus-supply = <&usb301_vbus_reg>; +}; + +/* + * Use longest HW watchdog in SoC (32 seconds) since the hardware + * watchdog provides no debugging information (compared to soft/hard + * lockup detectors) and so should be last resort. + */ +&watchdog { + timeout-sec = <32>; +}; + +#include "../cros-ec-keyboard.dtsi" +#include "../cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/samsung/exynos5800.dtsi b/arch/arm/boot/dts/samsung/exynos5800.dtsi new file mode 100644 index 000000000000..72d3a3535a7a --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5800.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos5800 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung Exynos5800 SoC device nodes are listed in this file. + * Exynos5800 based board files can include this file and provide + * values for board specific bindings. + */ + +#include "exynos5420.dtsi" + +/ { + compatible = "samsung,exynos5800", "samsung,exynos5"; +}; + +&clock { + compatible = "samsung,exynos5800-clock", "syscon"; +}; + +&cluster_a15_opp_table { + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <1312500 1312500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1262500 1262500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1237500 1237500 1500000>; + clock-latency-ns = <140000>; + }; + opp-1700000000 { + opp-microvolt = <1250000 1250000 1500000>; + }; + opp-1600000000 { + opp-microvolt = <1250000 1250000 1500000>; + }; + opp-1500000000 { + opp-microvolt = <1100000 1100000 1500000>; + }; + opp-1400000000 { + opp-microvolt = <1100000 1100000 1500000>; + }; + opp-1300000000 { + opp-microvolt = <1100000 1100000 1500000>; + }; + opp-1200000000 { + opp-microvolt = <1000000 1000000 1500000>; + }; + opp-1100000000 { + opp-microvolt = <1000000 1000000 1500000>; + }; + opp-1000000000 { + opp-microvolt = <1000000 1000000 1500000>; + }; + opp-900000000 { + opp-microvolt = <1000000 1000000 1500000>; + }; + opp-800000000 { + opp-microvolt = <900000 900000 1500000>; + }; + opp-700000000 { + opp-microvolt = <900000 900000 1500000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1500000>; + clock-latency-ns = <140000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <900000 900000 1500000>; + clock-latency-ns = <140000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000 900000 1500000>; + clock-latency-ns = <140000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000 900000 1500000>; + clock-latency-ns = <140000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000 900000 1500000>; + clock-latency-ns = <140000>; + }; +}; + +&cluster_a7_opp_table { + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp-1300000000 { + opp-microvolt = <1250000>; + }; + opp-1200000000 { + opp-microvolt = <1250000>; + }; + opp-1100000000 { + opp-microvolt = <1250000>; + }; + opp-1000000000 { + opp-microvolt = <1100000>; + }; + opp-900000000 { + opp-microvolt = <1100000>; + }; + opp-800000000 { + opp-microvolt = <1100000>; + }; + opp-700000000 { + opp-microvolt = <1000000>; + }; + opp-600000000 { + opp-microvolt = <1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <140000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <140000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <140000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <140000>; + }; +}; + +&dsi { + compatible = "samsung,exynos5422-mipi-dsi"; +}; + +&mfc { + compatible = "samsung,mfc-v8"; +}; + +&soc { + cam_pd: power-domain@10045100 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10045100 0x20>; + #power-domain-cells = <0>; + label = "CAM"; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s3c6400.dtsi b/arch/arm/boot/dts/samsung/s3c6400.dtsi new file mode 100644 index 000000000000..7cc785a63866 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c6400.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S3C6400 SoC device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional + * nodes can be added to this file. + */ + +#include "s3c64xx.dtsi" + +/ { + compatible = "samsung,s3c6400"; +}; + +&vic0 { + valid-mask = <0xfffffe1f>; + valid-wakeup-mask = <0x00200004>; +}; + +&vic1 { + valid-mask = <0xffffffff>; + valid-wakeup-mask = <0x53020000>; +}; + +&soc { + clocks: clock-controller@7e00f000 { + compatible = "samsung,s3c6400-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts b/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts new file mode 100644 index 000000000000..17097da36f5e --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S3C6410 based Mini6410 board device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Device tree source file for FriendlyARM Mini6410 board which is based on + * Samsung's S3C6410 SoC. + */ + +/dts-v1/; + +#include +#include + +#include "s3c6410.dtsi" + +/ { + model = "FriendlyARM Mini6410 board based on S3C6410"; + compatible = "friendlyarm,mini6410", "samsung,s3c6410"; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; + }; + + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + srom-cs1-bus@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18000000 0x8000000>; + ranges; + + ethernet@18000000 { + compatible = "davicom,dm9000"; + reg = <0x18000000 0x2 0x18000004 0x2>; + interrupt-parent = <&gpn>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + davicom,no-eeprom; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + autorepeat; + + button-k1 { + label = "K1"; + gpios = <&gpn 0 GPIO_ACTIVE_LOW>; + linux,code = <2>; + debounce-interval = <20>; + }; + + button-k2 { + label = "K2"; + gpios = <&gpn 1 GPIO_ACTIVE_LOW>; + linux,code = <3>; + debounce-interval = <20>; + }; + + button-k3 { + label = "K3"; + gpios = <&gpn 2 GPIO_ACTIVE_LOW>; + linux,code = <4>; + debounce-interval = <20>; + }; + + button-k4 { + label = "K4"; + gpios = <&gpn 3 GPIO_ACTIVE_LOW>; + linux,code = <5>; + debounce-interval = <20>; + }; + + button-k5 { + label = "K5"; + gpios = <&gpn 4 GPIO_ACTIVE_LOW>; + linux,code = <6>; + debounce-interval = <20>; + }; + + button-k6 { + label = "K6"; + gpios = <&gpn 5 GPIO_ACTIVE_LOW>; + linux,code = <7>; + debounce-interval = <20>; + }; + + button-k7 { + label = "K7"; + gpios = <&gpl 11 GPIO_ACTIVE_LOW>; + linux,code = <8>; + debounce-interval = <20>; + }; + + button-k8 { + label = "K8"; + gpios = <&gpl 12 GPIO_ACTIVE_LOW>; + linux,code = <9>; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds>; + + led-1 { + label = "LED1"; + gpios = <&gpk 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "LED2"; + gpios = <&gpk 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + led-3 { + label = "LED3"; + gpios = <&gpk 6 GPIO_ACTIVE_LOW>; + }; + + led-4 { + label = "LED4"; + gpios = <&gpk 7 GPIO_ACTIVE_LOW>; + }; + }; + + buzzer { + compatible = "pwm-beeper"; + pwms = <&pwm 0 1000000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; + }; +}; + +&clocks { + clocks = <&fin_pll>; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>, <&uart1_fctl>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; + status = "okay"; +}; + +&pinctrl0 { + gpio_leds: gpio-leds-pins { + samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; + samsung,pin-pud = ; + }; + + gpio_keys: gpio-keys-pins { + samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", + "gpn-4", "gpn-5", "gpl-11", "gpl-12"; + samsung,pin-pud = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts b/arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts new file mode 100644 index 000000000000..581309e7f15e --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung S3C6410 based SMDK6410 board device tree source. + * + * Copyright (c) 2013 Tomasz Figa + * + * Device tree source file for Samsung SMDK6410 board which is based on + * Samsung's S3C6410 SoC. + */ + +/dts-v1/; + +#include +#include + +#include "s3c6410.dtsi" + +/ { + model = "Samsung SMDK6410 board based on S3C6410"; + compatible = "samsung,smdk6410", "samsung,s3c6410"; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; + }; + + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + srom-cs1-bus@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18000000 0x8000000>; + ranges; + + ethernet@18000000 { + compatible = "smsc,lan9115"; + reg = <0x18000000 0x10000>; + interrupt-parent = <&gpn>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,force-internal-phy; + }; + }; +}; + +&clocks { + clocks = <&fin_pll>; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>, <&uart0_fctl>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/s3c6410.dtsi b/arch/arm/boot/dts/samsung/s3c6410.dtsi new file mode 100644 index 000000000000..13e9cc69b8a8 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c6410.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S3C6410 SoC device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional + * nodes can be added to this file. + */ + +#include "s3c64xx.dtsi" + +/ { + compatible = "samsung,s3c6410"; + + aliases { + i2c1 = &i2c1; + }; +}; + +&vic0 { + valid-mask = <0xffffff7f>; + valid-wakeup-mask = <0x00200004>; +}; + +&vic1 { + valid-mask = <0xffffffff>; + valid-wakeup-mask = <0x53020000>; +}; + +&soc { + clocks: clock-controller@7e00f000 { + compatible = "samsung,s3c6410-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; + + i2c1: i2c@7f00f000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x7f00f000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <5>; + clock-names = "i2c"; + clocks = <&clocks PCLK_IIC1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi new file mode 100644 index 000000000000..f53959b7d031 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi @@ -0,0 +1,682 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S3C64xx SoC series common device tree source + * - pin control-related definitions + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are + * listed as device tree nodes in this file. + */ + +#include "s3c64xx-pinctrl.h" + +&pinctrl0 { + /* + * Pin banks + */ + + gpa: gpa-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc: gpc-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd: gpd-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe: gpe-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf: gpf-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg: gpg-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph: gph-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpi: gpi-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj: gpj-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk: gpk-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl: gpl-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm: gpm-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpn: gpn-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpo: gpo-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp: gpp-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpq: gpq-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* + * Pin groups + */ + + uart0_data: uart0-data-pins { + samsung,pins = "gpa-0", "gpa-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa-2", "gpa-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa-4", "gpa-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa-6", "gpa-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ext_dma_0: ext-dma-0-pins { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ext_dma_1: ext-dma-1-pins { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + irda_data_0: irda-data-0-pins { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + irda_data_1: irda-data-1-pins { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + irda_sdbw: irda-sdbw-pins { + samsung,pins = "gpb-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpb-5", "gpb-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2c1_bus: i2c1-bus-pins { + /* S3C6410-only */ + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpc-0", "gpc-1", "gpc-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi0_cs: spi0-cs-pins { + samsung,pins = "gpc-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpc-4", "gpc-5", "gpc-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi1_cs: spi1-cs-pins { + samsung,pins = "gpc-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpg-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpg-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd0_bus1: sd0-bus1-pins { + samsung,pins = "gpg-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd0_bus4: sd0-bus4-pins { + samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpg-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gph-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gph-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd1_bus1: sd1-bus1-pins { + samsung,pins = "gph-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd1_bus4: sd1-bus4-pins { + samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd1_bus8: sd1-bus8-pins { + samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", + "gph-6", "gph-7", "gph-8", "gph-9"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpg-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpc-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpc-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd2_bus1: sd2-bus1-pins { + samsung,pins = "gph-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sd2_bus4: sd2-bus4-pins { + samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2s0_cdclk: i2s0-cdclk-pins { + samsung,pins = "gpd-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2s1_cdclk: i2s1-cdclk-pins { + samsung,pins = "gpe-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2s2_bus: i2s2-bus-pins { + /* S3C6410-only */ + samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", + "gph-8", "gph-9"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2s2_cdclk: i2s2-cdclk-pins { + /* S3C6410-only */ + samsung,pins = "gph-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pcm0_bus: pcm0-bus-pins { + samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pcm0_extclk: pcm0-extclk-pins { + samsung,pins = "gpd-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pcm1_extclk: pcm1-extclk-pins { + samsung,pins = "gpe-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ac97_bus_0: ac97-bus-0-pins { + samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ac97_bus_1: ac97-bus-1-pins { + samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cam_port: cam-port-pins { + samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", + "gpf-5", "gpf-6", "gpf-7", "gpf-8", + "gpf-9", "gpf-10", "gpf-11", "gpf-12"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cam_rst: cam-rst-pins { + samsung,pins = "gpf-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cam_field: cam-field-pins { + /* S3C6410-only */ + samsung,pins = "gpb-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pwm_extclk: pwm-extclk-pins { + samsung,pins = "gpf-13"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpf-14"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpf-15"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + clkout0: clkout-0-pins { + samsung,pins = "gpf-14"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col0_0: keypad-col0-0-pins { + samsung,pins = "gph-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col1_0: keypad-col1-0-pins { + samsung,pins = "gph-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col2_0: keypad-col2-0-pins { + samsung,pins = "gph-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col3_0: keypad-col3-0-pins { + samsung,pins = "gph-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col4_0: keypad-col4-0-pins { + samsung,pins = "gph-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col5_0: keypad-col5-0-pins { + samsung,pins = "gph-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col6_0: keypad-col6-0-pins { + samsung,pins = "gph-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col7_0: keypad-col7-0-pins { + samsung,pins = "gph-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col0_1: keypad-col0-1-pins { + samsung,pins = "gpl-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col1_1: keypad-col1-1-pins { + samsung,pins = "gpl-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col2_1: keypad-col2-1-pins { + samsung,pins = "gpl-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col3_1: keypad-col3-1-pins { + samsung,pins = "gpl-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col4_1: keypad-col4-1-pins { + samsung,pins = "gpl-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col5_1: keypad-col5-1-pins { + samsung,pins = "gpl-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col6_1: keypad-col6-1-pins { + samsung,pins = "gpl-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_col7_1: keypad-col7-1-pins { + samsung,pins = "gpl-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row0_0: keypad-row0-0-pins { + samsung,pins = "gpk-8"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row1_0: keypad-row1-0-pins { + samsung,pins = "gpk-9"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row2_0: keypad-row2-0-pins { + samsung,pins = "gpk-10"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row3_0: keypad-row3-0-pins { + samsung,pins = "gpk-11"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row4_0: keypad-row4-0-pins { + samsung,pins = "gpk-12"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row5_0: keypad-row5-0-pins { + samsung,pins = "gpk-13"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row6_0: keypad-row6-0-pins { + samsung,pins = "gpk-14"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row7_0: keypad-row7-0-pins { + samsung,pins = "gpk-15"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row0_1: keypad-row0-1-pins { + samsung,pins = "gpn-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row1_1: keypad-row1-1-pins { + samsung,pins = "gpn-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row2_1: keypad-row2-1-pins { + samsung,pins = "gpn-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row3_1: keypad-row3-1-pins { + samsung,pins = "gpn-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row4_1: keypad-row4-1-pins { + samsung,pins = "gpn-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row5_1: keypad-row5-1-pins { + samsung,pins = "gpn-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row6_1: keypad-row6-1-pins { + samsung,pins = "gpn-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + keypad_row7_1: keypad-row7-1-pins { + samsung,pins = "gpn-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lcd_ctrl: lcd-ctrl-pins { + samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lcd_data16: lcd-data-width16-pins { + samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", + "gpi-7", "gpi-10", "gpi-11", "gpi-12", + "gpi-13", "gpi-14", "gpi-15", "gpj-3", + "gpj-4", "gpj-5", "gpj-6", "gpj-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lcd_data18: lcd-data-width18-pins { + samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", + "gpi-6", "gpi-7", "gpi-10", "gpi-11", + "gpi-12", "gpi-13", "gpi-14", "gpi-15", + "gpj-2", "gpj-3", "gpj-4", "gpj-5", + "gpj-6", "gpj-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lcd_data24: lcd-data-width24-pins { + samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", + "gpi-4", "gpi-5", "gpi-6", "gpi-7", + "gpi-8", "gpi-9", "gpi-10", "gpi-11", + "gpi-12", "gpi-13", "gpi-14", "gpi-15", + "gpj-0", "gpj-1", "gpj-2", "gpj-3", + "gpj-4", "gpj-5", "gpj-6", "gpj-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + hsi_bus: hsi-bus-pins { + samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", + "gpk-4", "gpk-5", "gpk-6", "gpk-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h new file mode 100644 index 000000000000..645c591db357 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C64xx DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ + +#define S3C64XX_PIN_PULL_NONE 0 +#define S3C64XX_PIN_PULL_DOWN 1 +#define S3C64XX_PIN_PULL_UP 2 + +#define S3C64XX_PIN_FUNC_INPUT 0 +#define S3C64XX_PIN_FUNC_OUTPUT 1 +#define S3C64XX_PIN_FUNC_2 2 +#define S3C64XX_PIN_FUNC_3 3 +#define S3C64XX_PIN_FUNC_4 4 +#define S3C64XX_PIN_FUNC_5 5 +#define S3C64XX_PIN_FUNC_6 6 +#define S3C64XX_PIN_FUNC_EINT 7 + +#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/samsung/s3c64xx.dtsi b/arch/arm/boot/dts/samsung/s3c64xx.dtsi new file mode 100644 index 000000000000..0b59135ffe88 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s3c64xx.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S3C64xx SoC series common device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C64xx SoC series device nodes are listed in this file. + * Particular SoCs from S3C64xx series can include this file and provide + * values for SoCs specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional + * nodes can be added to this file. + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + i2c0 = &i2c0; + pinctrl0 = &pinctrl0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + reg = <0x0>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic0: interrupt-controller@71200000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x71200000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@71300000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x71300000 0x1000>; + #interrupt-cells = <1>; + }; + + sdhci0: mmc@7c200000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x7c200000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <24>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, + <&clocks SCLK_MMC0>; + status = "disabled"; + }; + + sdhci1: mmc@7c300000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x7c300000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <25>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, + <&clocks SCLK_MMC1>; + status = "disabled"; + }; + + sdhci2: mmc@7c400000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x7c400000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <17>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, + <&clocks SCLK_MMC2>; + status = "disabled"; + }; + + watchdog: watchdog@7e004000 { + compatible = "samsung,s3c6410-wdt"; + reg = <0x7e004000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <26>; + clock-names = "watchdog"; + clocks = <&clocks PCLK_WDT>; + }; + + i2c0: i2c@7f004000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x7f004000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <18>; + clock-names = "i2c"; + clocks = <&clocks PCLK_IIC0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + uart1: serial@7f005400 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005400 0x100>; + interrupt-parent = <&vic1>; + interrupts = <6>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + uart2: serial@7f005800 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005800 0x100>; + interrupt-parent = <&vic1>; + interrupts = <7>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + uart3: serial@7f005c00 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005c00 0x100>; + interrupt-parent = <&vic1>; + interrupts = <8>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + pwm: pwm@7f006000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x7f006000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <23>, <24>, <25>, <27>, <28>; + clock-names = "timers"; + clocks = <&clocks PCLK_PWM>; + samsung,pwm-outputs = <0>, <1>; + #pwm-cells = <3>; + }; + + pinctrl0: pinctrl@7f008000 { + compatible = "samsung,s3c64xx-pinctrl"; + reg = <0x7f008000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <21>; + + wakeup-interrupt-controller { + compatible = "samsung,s3c64xx-wakeup-eint"; + interrupts-extended = <&vic0 0>, + <&vic0 1>, + <&vic1 0>, + <&vic1 1>; + }; + }; + }; +}; + +#include "s3c64xx-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/samsung/s5pv210-aquila.dts b/arch/arm/boot/dts/samsung/s5pv210-aquila.dts new file mode 100644 index 000000000000..0f5c6cd0f3a1 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-aquila.dts @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Board device tree source for Samsung Aquila board. + */ + +/dts-v1/; +#include +#include +#include "s5pv210.dtsi" + +/ { + model = "Samsung Aquila based on S5PC110"; + compatible = "samsung,aquila", "samsung,s5pv210"; + + aliases { + i2c3 = &i2c_pmic; + }; + + chosen { + bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>; + }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + vtf_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_TF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pda_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + bat_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_BAT"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + i2c_pmic: i2c-pmic { + compatible = "i2c-gpio"; + sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "national,lp3974"; + reg = <0x66>; + + max8998,pmic-buck1-default-dvs-idx = <0>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB+MIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VCC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC+VCAM_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_IO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "CAM_ISP_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "CAM_A_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "CAM_CIF_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_AF_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "CAM_8M_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "VARM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VINT_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "CAM_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + }; + + safeout1_reg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + regulator-always-on; + }; + + safeout2_reg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + }; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&gph2 6 1>; + linux,code = ; + label = "power"; + debounce-interval = <1>; + wakeup-source; + }; + }; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&keypad { + linux,input-no-autorepeat; + wakeup-source; + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, + <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; + status = "okay"; + + key-1 { + keypad,row = <0>; + keypad,column = <1>; + linux,code = ; + }; + + key-2 { + keypad,row = <0>; + keypad,column = <2>; + linux,code = ; + }; + + key-3 { + keypad,row = <1>; + keypad,column = <1>; + linux,code = ; + }; + + key-4 { + keypad,row = <1>; + keypad,column = <2>; + linux,code = ; + }; + + key-5 { + keypad,row = <2>; + keypad,column = <1>; + linux,code = ; + }; + + key-6 { + keypad,row = <2>; + keypad,column = <2>; + linux,code = ; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci0 { + bus-width = <4>; + non-removable; + status = "okay"; + vmmc-supply = <&ldo5_reg>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; + pinctrl-names = "default"; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gph3 4 1>; + vmmc-supply = <&vtf_reg>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>; + pinctrl-names = "default"; + status = "okay"; +}; + +&onenand { + status = "okay"; +}; + +&hsotg { + vusb_a-supply = <&ldo3_reg>; + vusb_d-supply = <&ldo8_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <0>; + hactive = <800>; + vactive = <480>; + hfront-porch = <16>; + hback-porch = <16>; + hsync-len = <2>; + vback-porch = <3>; + vfront-porch = <28>; + vsync-len = <1>; + }; + }; +}; + +&pinctrl0 { + t_flash_detect: t-flash-detect-pins { + samsung,pins = "gph3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi new file mode 100644 index 000000000000..f628d3660493 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 based Galaxy Aries board device tree source + */ + +/dts-v1/; +#include +#include +#include "s5pv210.dtsi" + +/ { + compatible = "samsung,aries", "samsung,s5pv210"; + + aliases: aliases { + i2c4 = &i2c_sound; + i2c5 = &i2c_accel; + i2c6 = &i2c_pmic; + i2c7 = &i2c_musb; + i2c9 = &i2c_fuel; + i2c10 = &i2c_touchkey; + i2c11 = &i2c_prox; + i2c12 = &i2c_magnetometer; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mfc_left: region@43000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x43000000 0x2000000>; + }; + + mfc_right: region@51000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x51000000 0x2000000>; + }; + }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + bt_codec: bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <0>; + }; + + vibrator_pwr: regulator-fixed-0 { + compatible = "regulator-fixed"; + regulator-name = "vibrator-en"; + enable-active-high; + gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_ena>; + }; + + touchkey_vdd: regulator-fixed-1 { + compatible = "regulator-fixed"; + regulator-name = "VTOUCH_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_vdd_ena>; + }; + + gp2a_vled: regulator-fixed-2 { + compatible = "regulator-fixed"; + regulator-name = "VLED"; + enable-active-high; + gpio = <&gpj1 4 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gp2a_power>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_gpio_rst>; + post-power-on-delay-ms = <500>; + power-off-delay-us = <500>; + }; + + i2c_sound: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sound_i2c_pins>; + + wm8994: audio-codec@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + #sound-dai-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&clocks MOUT_CLKOUT>; + clock-names = "MCLK1"; + + AVDD2-supply = <&buck3_reg>; + DBVDD-supply = <&buck3_reg>; + CPVDD-supply = <&buck3_reg>; + SPKVDD1-supply = <&buck3_reg>; + SPKVDD2-supply = <&buck3_reg>; + + wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100 + 0xa101 0x0100 0x8100 0x0100 0x0100 + 0x0100>; + + wlf,ldo1ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>; + + wlf,lineout1-se; + wlf,lineout2-se; + + assigned-clocks = <&clocks MOUT_CLKOUT>; + assigned-clock-rates = <0>; + assigned-clock-parents = <&xusbxti>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_ldo>; + }; + }; + + i2c_accel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_i2c_pins>; + + accelerometer@38 { + compatible = "bosch,bma023"; + reg = <0x38>; + + vdd-supply = <&ldo9_reg>; + vddio-supply = <&ldo9_reg>; + }; + }; + + i2c_pmic: i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_i2c_pins>; + + pmic@66 { + compatible = "maxim,max8998"; + reg = <0x66>; + interrupt-parent = <&gph0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + max8998,pmic-buck1-default-dvs-idx = <1>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, + <1050000>, <950000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_dvs_pins &pmic_irq>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3600000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VGA_VDDIO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VGA_DVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_ISP_HOST_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VGA_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "vddarm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1250000>; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vddint"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + }; + }; + }; + }; + + i2c_musb: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_i2c_pins>; + + fsa9480: musb@25 { + compatible = "fcs,fsa9480"; + reg = <0x25>; + interrupt-parent = <&gph2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_irq>; + }; + }; + + i2c_fuel: i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_i2c_pins>; + + fg: fuelgauge@36 { + compatible = "maxim,max17040"; + reg = <0x36>; + }; + }; + + i2c_touchkey: i2c-gpio-5 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_i2c_pins>; + + touchkey@20 { + compatible = "cypress,aries-touchkey"; + reg = <0x20>; + vdd-supply = <&touchkey_vdd>; + vcc-supply = <&buck3_reg>; + linux,keycodes = ; + interrupt-parent = <&gpj4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_irq>; + }; + }; + + i2c_prox: i2c-gpio-6 { + compatible = "i2c-gpio"; + sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&prox_i2c_pins>; + + light-sensor@44 { + compatible = "sharp,gp2ap002a00f"; + reg = <0x44>; + interrupt-parent = <&gph0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&gp2a_vled>; + vio-supply = <&gp2a_vled>; + io-channels = <&gp2a_shunt>; + io-channel-names = "alsout"; + sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&gp2a_irq>; + }; + }; + + i2c_magnetometer: i2c-gpio-7 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&magnetometer_i2c_pins>; + + status = "disabled"; + + /* Yamaha yas529 magnetometer, no mainline binding */ + }; + + vibrator: pwm-vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm 1 44642 0>; + pwm-names = "enable"; + vcc-supply = <&vibrator_pwr>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; + }; + + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_syscon>; + offset = <0x681c>; /* PS_HOLD_CONTROL */ + value = <0x5200>; + }; + + spi_lcd: spi-2 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_spi_pins>; + + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + spi-max-frequency = <1200000>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_rst>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo4_reg>; + + status = "okay"; + + gp2a_shunt: current-sense-shunt { + compatible = "current-sense-shunt"; + io-channels = <&adc 9>; + shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */ + #io-channel-cells = <0>; + }; +}; + +&fimd { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_clk &lcd_data24>; + status = "okay"; + + samsung,invert-vden; + samsung,invert-vclk; + + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&hsotg { + vusb_a-supply = <&ldo8_reg>; + vusb_d-supply = <&ldo3_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + samsung,i2c-slave-addr = <0x10>; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpj0>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq>; + reset-gpios = <&gpj1 3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2s0 { + dmas = <&pdma0 10>, <&pdma0 9>, <&pdma0 11>; + status = "okay"; +}; + +&mfc { + memory-region = <&mfc_left>, <&mfc_right>; +}; + +&pinctrl0 { + bt_reset: bt-reset-pins { + samsung,pins = "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wlan_bt_en: wlan-bt-en-pins { + samsung,pins = "gpb-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + }; + + codec_ldo: codec-ldo-pins { + samsung,pins = "gpf3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + prox_i2c_pins: gp2a-i2c-pins { + samsung,pins = "gpg0-2", "gpg2-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wlan_gpio_rst: wlan-gpio-rst-pins { + samsung,pins = "gpg1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_wake: bt-wake-pins { + samsung,pins = "gpg3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + gp2a_irq: gp2a-irq-pins { + samsung,pins = "gph0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_dvs_pins: pmic-dvs-pins { + samsung,pins = "gph0-3", "gph0-4", "gph0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + pmic_irq: pmic-irq-pins { + samsung,pins = "gph0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wifi_host_wake: wifi-host-wake-pins { + samsung,pins = "gph2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + bt_host_wake: bt-host-wake-pins { + samsung,pins = "gph2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + musb_irq: musq-irq-pins { + samsung,pins = "gph2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + tf_detect: tf-detect-pins { + samsung,pins = "gph3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wifi_wake: wifi-wake-pins { + samsung,pins = "gph3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + magnetometer_i2c_pins: yas529-i2c-pins { + samsung,pins = "gpj0-0", "gpj0-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ts_irq: ts-irq-pins { + samsung,pins = "gpj0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + vibrator_ena: vibrator-ena-pins { + samsung,pins = "gpj1-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + gp2a_power: gp2a-power-pins { + samsung,pins = "gpj1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_i2c_pins: touchkey-i2c-pins { + samsung,pins = "gpj3-0", "gpj3-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_vdd_ena: touchkey-vdd-ena-pins { + samsung,pins = "gpj3-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + musb_i2c_pins: musb-i2c-pins { + samsung,pins = "gpj3-4", "gpj3-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + accel_i2c_pins: accel-i2c-pins { + samsung,pins = "gpj3-6", "gpj3-7"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_i2c_pins: pmic-i2c-pins { + samsung,pins = "gpj4-0", "gpj4-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_irq: touchkey-irq-pins { + samsung,pins = "gpj4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_spi_pins: spi-lcd-pins { + samsung,pins = "mp01-1", "mp04-1", "mp04-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fg_i2c_pins: fg-i2c-pins { + samsung,pins = "mp05-0", "mp05-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sound_i2c_pins: sound-i2c-pins { + samsung,pins = "mp05-2", "mp05-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + panel_rst: panel-rst-pins { + samsung,pins = "mp05-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + samsung,pwm-outputs = <1>; +}; + +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci1 { + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + max-frequency = <38400000>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; + pinctrl-names = "default"; + cap-sd-highspeed; + cap-mmc-highspeed; + keep-power-in-suspend; + + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; + + wlan@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gph2>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&ldo5_reg>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; + pinctrl-names = "default"; + status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; +}; + +&uart0 { + assigned-clocks = <&clocks MOUT_UART0>, <&clocks SCLK_UART0>; + assigned-clock-rates = <0>, <111166667>; + assigned-clock-parents = <&clocks MOUT_MPLL>; + + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4329-bt"; + max-speed = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake + &bt_reset &bt_wake>; + shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gph2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; + vbus-supply = <&safe1_sreg>; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts new file mode 100644 index 000000000000..eaa7c4f0e257 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; + compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; + chassis-type = "handset"; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-vol-down { + label = "volume_down"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-vol-up { + label = "volume_up"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + headset_micbias_reg: regulator-fixed-3 { + compatible = "regulator-fixed"; + regulator-name = "Headset_Micbias"; + gpio = <&gpj2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_micbias_ena>; + }; + + main_micbias_reg: regulator-fixed-4 { + compatible = "regulator-fixed"; + regulator-name = "Main_Micbias"; + gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&main_micbias_ena>; + }; + + sound { + compatible = "samsung,fascinate4g-wm8994"; + + model = "Fascinate4G"; + + extcon = <&fsa9480>; + + main-micbias-supply = <&main_micbias_reg>; + headset-micbias-supply = <&headset_micbias_reg>; + + earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; + + io-channels = <&adc 3>; + io-channel-names = "headset-detect"; + headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>; + headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", + + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", + + "Modem Out", "Modem TX", + "Modem RX", "Modem In", + + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_det &earpath_sel>; + + cpu { + sound-dai = <&i2s0>, <&bt_codec>; + }; + + codec { + sound-dai = <&wm8994>; + }; + }; +}; + +&fg { + compatible = "maxim,max77836-battery"; + + interrupt-parent = <&gph3>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_irq>; +}; + +&pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + headset_det: headset-det-pins { + samsung,pins = "gph0-6", "gph3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + fg_irq: fg-irq-pins { + samsung,pins = "gph3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + headset_micbias_ena: headset-micbias-ena-pins { + samsung,pins = "gpj2-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + earpath_sel: earpath-sel-pins { + samsung,pins = "gpj2-6"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + main_micbias_ena: main-micbias-ena-pins { + samsung,pins = "gpj4-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* Based on vendor kernel v2.6.35.7 */ + sleep_cfg: sleep-state { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, PREV, NONE); + PIN_SLP(gpa0-5, PREV, NONE); + PIN_SLP(gpa0-6, PREV, NONE); + PIN_SLP(gpa0-7, PREV, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, DOWN); + PIN_SLP(gpd1-3, INPUT, DOWN); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, INPUT, DOWN); + PIN_SLP(gpg0-1, INPUT, DOWN); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, DOWN); + PIN_SLP(gpg0-4, INPUT, DOWN); + PIN_SLP(gpg0-5, INPUT, DOWN); + PIN_SLP(gpg0-6, INPUT, DOWN); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, PREV, UP); + PIN_SLP(gpg3-1, PREV, UP); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, OUT1, NONE); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, DOWN); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, INPUT, DOWN); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, OUT1, NONE); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT0, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; +}; + +&wm8994 { + /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */ + wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101 + 0x0100 0x8100 0x0100 0x0100 0x0100>; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts b/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts new file mode 100644 index 000000000000..532d3f5bceb1 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; + compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; + chassis-type = "handset"; + + chosen { + stdout-path = &uart2; + }; + + nand_pwrseq: nand-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&massmemory_en>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + key-vol-down { + label = "volume_down"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-vol-up { + label = "volume_up"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-home { + label = "home"; + gpios = <&gph3 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + i2c_fmradio: i2c-gpio-8 { + compatible = "i2c-gpio"; + sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_i2c_pins>; + + fmradio@10 { + compatible = "silabs,si470x"; + reg = <0x10>; + interrupt-parent = <&gpj2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_irq &fm_rst>; + }; + }; + + micbias_reg: regulator-fixed-3 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS"; + gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&micbias_reg_ena>; + }; + + sound { + compatible = "samsung,aries-wm8994"; + + model = "Aries"; + + extcon = <&fsa9480>; + + main-micbias-supply = <&micbias_reg>; + headset-micbias-supply = <&micbias_reg>; + + earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; + + io-channels = <&adc 3>; + io-channel-names = "headset-detect"; + headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>; + headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", + + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", + + "IN2LN", "FM In", + "IN2RN", "FM In", + + "Modem Out", "Modem TX", + "Modem RX", "Modem In", + + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_det &earpath_sel>; + + cpu { + sound-dai = <&i2s0>, <&bt_codec>; + }; + + codec { + sound-dai = <&wm8994>; + }; + }; +}; + +&aliases { + i2c8 = &i2c_fmradio; +}; + +&pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + fm_i2c_pins: fm-i2c-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + headset_det: headset-det-pins { + samsung,pins = "gph0-6", "gph3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + fm_irq: fm-irq-pins { + samsung,pins = "gpj2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_rst: fm-rst-pins { + samsung,pins = "gpj2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + earpath_sel: earpath-sel-pins { + samsung,pins = "gpj2-6"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + massmemory_en: massmemory-en-pins { + samsung,pins = "gpj2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + micbias_reg_ena: micbias-reg-ena-pins { + samsung,pins = "gpj4-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* Based on CyanogenMod 3.0.101 kernel */ + sleep_cfg: sleep-state { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, OUT0, NONE); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, OUT1, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, NONE); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, NONE); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, OUT0, NONE); + PIN_SLP(gpg0-1, INPUT, NONE); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, NONE); + PIN_SLP(gpg0-4, INPUT, NONE); + PIN_SLP(gpg0-5, INPUT, NONE); + PIN_SLP(gpg0-6, INPUT, NONE); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, OUT1, NONE); + PIN_SLP(gpg3-1, OUT0, NONE); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, UP); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, OUT1, NONE); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, INPUT, DOWN); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT1, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; +}; + +&sdhci0 { + bus-width = <4>; + non-removable; + mmc-pwrseq = <&nand_pwrseq>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>; + assigned-clock-rates = <0>, <52000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-goni.dts b/arch/arm/boot/dts/samsung/s5pv210-goni.dts new file mode 100644 index 000000000000..d32f42dd1bf5 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-goni.dts @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Board device tree source for Samsung Goni board. + */ + +/dts-v1/; +#include +#include +#include +#include "s5pv210.dtsi" + +/ { + model = "Samsung Goni based on S5PC110"; + compatible = "samsung,goni", "samsung,s5pv210"; + + aliases { + i2c3 = &i2c_pmic; + }; + + chosen { + bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; + }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + vtf_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_TF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pda_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + bat_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_BAT"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + tsp_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "TSP_VDD"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + i2c_pmic: i2c-pmic { + compatible = "i2c-gpio"; + sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "national,lp3974"; + reg = <0x66>; + + max8998,pmic-buck1-default-dvs-idx = <0>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB+MIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VCC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC+VCAM_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_IO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo12_reg: LDO12 { + regulator-name = "CAM_ISP_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "CAM_A_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "CAM_CIF_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_AF_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "CAM_8M_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "VARM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "VINT_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "CAM_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&gph2 6 1>; + linux,code = ; + label = "power"; + debounce-interval = <1>; + wakeup-source; + }; + }; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&keypad { + linux,input-no-autorepeat; + wakeup-source; + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, + <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; + status = "okay"; + + key-1 { + keypad,row = <0>; + keypad,column = <1>; + linux,code = ; + }; + + key-2 { + keypad,row = <0>; + keypad,column = <2>; + linux,code = ; + }; + + key-3 { + keypad,row = <1>; + keypad,column = <1>; + linux,code = ; + }; + + key-4 { + keypad,row = <1>; + keypad,column = <2>; + linux,code = ; + }; + + key-5 { + keypad,row = <2>; + keypad,column = <1>; + linux,code = ; + }; + + key-6 { + keypad,row = <2>; + keypad,column = <2>; + linux,code = ; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci0 { + bus-width = <4>; + non-removable; + vmmc-supply = <&ldo5_reg>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gph3 4 1>; + vmmc-supply = <&vtf_reg>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hsotg { + vusb_a-supply = <&ldo3_reg>; + vusb_d-supply = <&ldo8_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&i2c2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + samsung,i2c-slave-addr = <0x10>; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpj0>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&tsp_reg>; + }; +}; + +&i2c0 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <100000>; + samsung,i2c-slave-addr = <0x10>; + status = "okay"; + + noon010pc30: sensor@30 { + compatible = "siliconfile,noon010pc30"; + reg = <0x30>; + vddio-supply = <&ldo11_reg>; + vdda-supply = <&ldo13_reg>; + vdd_core-supply = <&ldo14_reg>; + + clock-frequency = <16000000>; + clocks = <&camera 0>; + clock-names = "mclk"; + nreset-gpios = <&gpb 2 GPIO_ACTIVE_HIGH>; + nstby-gpios = <&gpb 0 GPIO_ACTIVE_HIGH>; + + port { + noon010pc30_ep: endpoint { + remote-endpoint = <&fimc0_ep>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&camera { + pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>; + pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>; + pinctrl-names = "default", "idle"; + + parallel-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* camera A input */ + port@1 { + reg = <1>; + fimc0_ep: endpoint { + remote-endpoint = <&noon010pc30_ep>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24>; + pinctrl-names = "default"; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: timing { + /* 480x800@55Hz */ + clock-frequency = <23439570>; + hactive = <480>; + hfront-porch = <16>; + hback-porch = <16>; + hsync-len = <2>; + vactive = <800>; + vback-porch = <2>; + vfront-porch = <28>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +&onenand { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi new file mode 100644 index 000000000000..af740abd9e0f --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi @@ -0,0 +1,845 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source - pin control-related + * definitions + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are + * listed as device tree nodes in this file. + */ + +#include "s5pv210-pinctrl.h" + +#define PIN_SLP(_pin, _mode, _pull) \ + pin- ## _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ + } + +&pinctrl0 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj0: gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj2: gpj2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj3: gpj3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpi: gpi-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp01: mp01-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp02: mp02-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp03: mp03-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp04: mp04-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp05: mp05-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp06: mp06-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + mp07: mp07-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0-gpio-bank { + gpio-controller; + interrupt-controller; + interrupt-parent = <&vic0>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gph1: gph1-gpio-bank { + gpio-controller; + interrupt-controller; + interrupt-parent = <&vic0>; + interrupts = <8>, <9>, <10>, <11>, + <12>, <13>, <14>, <15>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gph2: gph2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph3: gph3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl-pins { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl-pins { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data-pins { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio: uart-audio-pins { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", + "gpi-4", "gpi-5", "gpi-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ac97_bus: ac97-bus-pins { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpd1-4", "gpd1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpd0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins = "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row0: keypad-row-0-pins { + samsung,pins = "gph3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row1: keypad-row-1-pins { + samsung,pins = "gph3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row2: keypad-row-2-pins { + samsung,pins = "gph3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row3: keypad-row-3-pins { + samsung,pins = "gph3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row4: keypad-row-4-pins { + samsung,pins = "gph3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row5: keypad-row-5-pins { + samsung,pins = "gph3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row6: keypad-row-6-pins { + samsung,pins = "gph3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_row7: keypad-row-7-pins { + samsung,pins = "gph3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col0: keypad-col-0-pins { + samsung,pins = "gph2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col1: keypad-col-1-pins { + samsung,pins = "gph2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col2: keypad-col-2-pins { + samsung,pins = "gph2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col3: keypad-col-3-pins { + samsung,pins = "gph2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col4: keypad-col-4-pins { + samsung,pins = "gph2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col5: keypad-col-5-pins { + samsung,pins = "gph2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col6: keypad-col-6-pins { + samsung,pins = "gph2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + keypad_col7: keypad-col-7-pins { + samsung,pins = "gph2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpg0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpg0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd-pins { + samsung,pins = "gpg0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpg0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpg1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpg1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd-pins { + samsung,pins = "gpg1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpg1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpg2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpg2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpg2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpg2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus8: sd2-bus-width8-pins { + samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_clk: sd3-clk-pins { + samsung,pins = "gpg3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cmd: sd3-cmd-pins { + samsung,pins = "gpg3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cd: sd3-cd-pins { + samsung,pins = "gpg3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus1: sd3-bus-width1-pins { + samsung,pins = "gpg3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus4: sd3-bus-width4-pins { + samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint0: ext-int0-pins { + samsung,pins = "gph0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint8: ext-int8-pins { + samsung,pins = "gph1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint15: ext-int15-pins { + samsung,pins = "gph1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint16: ext-int16-pins { + samsung,pins = "gph2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint31: ext-int31-pins { + samsung,pins = "gph3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_io: cam-port-a-io-pins { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_active: cam-port-a-clk-active-pins { + samsung,pins = "gpe1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { + samsung,pins = "gpe1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_io: cam-port-b-io-pins { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_active: cam-port-b-clk-active-pins { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ctrl: lcd-ctrl-pins { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_sync: lcd-sync-pins { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_clk: lcd-clk-pins { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data24: lcd-data-width24-pins { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-pinctrl.h b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.h new file mode 100644 index 000000000000..29bdf376d8f1 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S5PV210 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski + */ + +#ifndef __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ + +#define S5PV210_PIN_PULL_NONE 0 +#define S5PV210_PIN_PULL_DOWN 1 +#define S5PV210_PIN_PULL_UP 2 + +/* Pin function in power down mode */ +#define S5PV210_PIN_PDN_OUT0 0 +#define S5PV210_PIN_PDN_OUT1 1 +#define S5PV210_PIN_PDN_INPUT 2 +#define S5PV210_PIN_PDN_PREV 3 + +#define S5PV210_PIN_DRV_LV1 0 +#define S5PV210_PIN_DRV_LV2 2 +#define S5PV210_PIN_DRV_LV3 1 +#define S5PV210_PIN_DRV_LV4 3 + +#define S5PV210_PIN_FUNC_INPUT 0 +#define S5PV210_PIN_FUNC_OUTPUT 1 +#define S5PV210_PIN_FUNC_2 2 +#define S5PV210_PIN_FUNC_3 3 +#define S5PV210_PIN_FUNC_4 4 +#define S5PV210_PIN_FUNC_5 5 +#define S5PV210_PIN_FUNC_6 6 +#define S5PV210_PIN_FUNC_EINT 0xf +#define S5PV210_PIN_FUNC_F S5PV210_PIN_FUNC_EINT + +#endif /* __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts new file mode 100644 index 000000000000..0c623b78af72 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Board device tree source for YIC System SMDC110 board. + * + * NOTE: This file is completely based on original board file for mach-smdkc110 + * available in Linux 3.15 and intends to provide equivalent level of hardware + * support. Due to lack of hardware, _no_ testing has been performed. + */ + +/dts-v1/; +#include +#include "s5pv210.dtsi" + +/ { + model = "YIC System SMDKC110 based on S5PC110"; + compatible = "yic,smdkc110", "samsung,s5pv210"; + + chosen { + bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&i2c0 { + status = "okay"; + + audio-codec@1b { + compatible = "wlf,wm8580"; + reg = <0x1b>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&i2s0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts new file mode 100644 index 000000000000..6e26c67e0a26 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Board device tree source for YIC System SMDV210 board. + * + * NOTE: This file is completely based on original board file for mach-smdkv210 + * available in Linux 3.15 and intends to provide equivalent level of hardware + * support. Due to lack of hardware, _no_ testing has been performed. + */ + +/dts-v1/; +#include +#include +#include "s5pv210.dtsi" + +/ { + model = "YIC System SMDKV210 based on S5PV210"; + compatible = "yic,smdkv210", "samsung,s5pv210"; + + chosen { + bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x40000000>; + }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ethernet@a8000000 { + compatible = "davicom,dm9000"; + reg = <0xA8000000 0x2 0xA8000002 0x2>; + interrupt-parent = <&gph1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + local-mac-address = [00 00 de ad be ef]; + davicom,no-eeprom; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; + power-supply = <&dc5v_reg>; + }; + + dc5v_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "DC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&keypad { + linux,input-no-autorepeat; + wakeup-source; + samsung,keypad-num-rows = <8>; + samsung,keypad-num-columns = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, + <&keypad_row3>, <&keypad_row4>, <&keypad_row5>, + <&keypad_row6>, <&keypad_row7>, + <&keypad_col0>, <&keypad_col1>, <&keypad_col2>, + <&keypad_col3>, <&keypad_col4>, <&keypad_col5>, + <&keypad_col6>, <&keypad_col7>; + status = "okay"; + + key-1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = ; + }; + + key-2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = ; + }; + + key-3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = ; + }; + + key-4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = ; + }; + + key-5 { + keypad,row = <0 + >; + keypad,column = <7>; + linux,code = ; + }; + + key-6 { + keypad,row = <1>; + keypad,column = <3>; + linux,code = ; + }; + key-7 { + keypad,row = <1>; + keypad,column = <4>; + linux,code = ; + }; + + key-8 { + keypad,row = <1>; + keypad,column = <5>; + linux,code = ; + }; + + key-9 { + keypad,row = <1>; + keypad,column = <6>; + linux,code = ; + }; + + key-10 { + keypad,row = <1>; + keypad,column = <7>; + linux,code = ; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci0 { + bus-width = <4>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci3 { + bus-width = <4>; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hsotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24>; + pinctrl-names = "default"; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing { + /* 800x480@60Hz */ + clock-frequency = <24373920>; + hactive = <800>; + vactive = <480>; + hfront-porch = <8>; + hback-porch = <13>; + hsync-len = <3>; + vback-porch = <7>; + vfront-porch = <5>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; +}; + +&pwm { + samsung,pwm-outputs = <3>; +}; + +&i2c0 { + status = "okay"; + + audio-codec@1b { + compatible = "wlf,wm8580"; + reg = <0x1b>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&i2s0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210-torbreck.dts b/arch/arm/boot/dts/samsung/s5pv210-torbreck.dts new file mode 100644 index 000000000000..e18259737684 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210-torbreck.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Board device tree source for Torbreck board. + * + * NOTE: This file is completely based on original board file for mach-torbreck + * available in Linux 3.15 and intends to provide equivalent level of hardware + * support. Due to lack of hardware, _no_ testing has been performed. + */ + +/dts-v1/; +#include +#include "s5pv210.dtsi" + +/ { + model = "aESOP Torbreck based on S5PV210"; + compatible = "aesop,torbreck", "samsung,s5pv210"; + + chosen { + bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci0 { + bus-width = <4>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci3 { + bus-width = <4>; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi new file mode 100644 index 000000000000..f7de5b5f2f38 --- /dev/null +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 SoC device tree source + * + * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. + * + * Mateusz Krawczuk + * Tomasz Figa + * + * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional + * nodes can be added to this file. + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + csis0 = &csis0; + dmc0 = &dmc0; + dmc1 = &dmc1; + fimc0 = &fimc0; + fimc1 = &fimc1; + fimc2 = &fimc2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2s0 = &i2s0; + i2s1 = &i2s1; + i2s2 = &i2s2; + pinctrl0 = &pinctrl0; + spi0 = &spi0; + spi1 = &spi1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0>; + }; + }; + + xxti: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xxti"; + #clock-cells = <0>; + }; + + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xusbxti"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + onenand: onenand@b0600000 { + compatible = "samsung,s5pv210-onenand"; + reg = <0xb0600000 0x2000>, + <0xb0000000 0x20000>, + <0xb0040000 0x20000>; + interrupt-parent = <&vic1>; + interrupts = <31>; + clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; + clock-names = "bus", "onenand"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + chipid@e0000000 { + compatible = "samsung,s5pv210-chipid"; + reg = <0xe0000000 0x1000>; + }; + + clocks: clock-controller@e0100000 { + compatible = "samsung,s5pv210-clock"; + reg = <0xe0100000 0x10000>; + clock-names = "xxti", "xusbxti"; + clocks = <&xxti>, <&xusbxti>; + #clock-cells = <1>; + }; + + pmu_syscon: syscon@e0108000 { + compatible = "samsung-s5pv210-pmu", "syscon"; + reg = <0xe0108000 0x8000>; + }; + + pinctrl0: pinctrl@e0200000 { + compatible = "samsung,s5pv210-pinctrl"; + reg = <0xe0200000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <30>; + + wakeup-interrupt-controller { + compatible = "samsung,s5pv210-wakeup-eint"; + interrupts = <16>; + interrupt-parent = <&vic0>; + }; + }; + + pdma0: dma-controller@e0900000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xe0900000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <19>; + clocks = <&clocks CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pdma1: dma-controller@e0a00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xe0a00000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <20>; + clocks = <&clocks CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + adc: adc@e1700000 { + compatible = "samsung,s5pv210-adc"; + reg = <0xe1700000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <23>, <24>; + clocks = <&clocks CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + spi0: spi@e1300000 { + compatible = "samsung,s5pv210-spi"; + reg = <0xe1300000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <15>; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@e1400000 { + compatible = "samsung,s5pv210-spi"; + reg = <0xe1400000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <16>; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + keypad: keypad@e1600000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0xe1600000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <25>; + clocks = <&clocks CLK_KEYIF>; + clock-names = "keypad"; + status = "disabled"; + }; + + i2c0: i2c@e1800000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0xe1800000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <14>; + clocks = <&clocks CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e1a00000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0xe1a00000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <19>; + clocks = <&clocks CLK_I2C2>; + clock-names = "i2c"; + pinctrl-0 = <&i2c2_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clk_audss: clock-controller@eee10000 { + compatible = "samsung,s5pv210-audss-clock"; + reg = <0xeee10000 0x1000>; + clock-names = "hclk", "xxti", + "fout_epll", + "sclk_audio0"; + clocks = <&clocks DOUT_HCLKP>, <&xxti>, + <&clocks FOUT_EPLL>, + <&clocks SCLK_AUDIO0>; + #clock-cells = <1>; + }; + + i2s0: i2s@eee30000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0xeee30000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <16>; + dma-names = "tx", "rx", "tx-sec"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 11>; + clock-names = "iis", + "i2s_opclk0", + "i2s_opclk1"; + clocks = <&clk_audss CLK_I2S>, + <&clk_audss CLK_I2S>, + <&clk_audss CLK_DOUT_AUD_BUS>; + samsung,idma-addr = <0xc0010000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@e2100000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0xe2100000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <17>; + dma-names = "tx", "rx"; + dmas = <&pdma1 13>, <&pdma1 12>; + clock-names = "iis", "i2s_opclk0"; + clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@e2a00000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0xe2a00000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <18>; + dma-names = "tx", "rx"; + dmas = <&pdma1 15>, <&pdma1 14>; + clock-names = "iis", "i2s_opclk0"; + clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@e2500000 { + compatible = "samsung,s5pc100-pwm"; + reg = <0xe2500000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <21>, <22>, <23>, <24>, <25>; + clock-names = "timers"; + clocks = <&clocks CLK_PWM>; + #pwm-cells = <3>; + }; + + watchdog: watchdog@e2700000 { + compatible = "samsung,s3c6410-wdt"; + reg = <0xe2700000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <26>; + clock-names = "watchdog"; + clocks = <&clocks CLK_WDT>; + }; + + rtc: rtc@e2800000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0xe2800000 0x100>; + interrupt-parent = <&vic0>; + interrupts = <28>, <29>; + clocks = <&clocks CLK_RTC>; + clock-names = "rtc"; + status = "disabled"; + }; + + uart0: serial@e2900000 { + compatible = "samsung,s5pv210-uart"; + reg = <0xe2900000 0x400>; + interrupt-parent = <&vic1>; + interrupts = <10>; + clock-names = "uart", "clk_uart_baud0", + "clk_uart_baud1"; + clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>, + <&clocks SCLK_UART0>; + status = "disabled"; + }; + + uart1: serial@e2900400 { + compatible = "samsung,s5pv210-uart"; + reg = <0xe2900400 0x400>; + interrupt-parent = <&vic1>; + interrupts = <11>; + clock-names = "uart", "clk_uart_baud0", + "clk_uart_baud1"; + clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>, + <&clocks SCLK_UART1>; + status = "disabled"; + }; + + uart2: serial@e2900800 { + compatible = "samsung,s5pv210-uart"; + reg = <0xe2900800 0x400>; + interrupt-parent = <&vic1>; + interrupts = <12>; + clock-names = "uart", "clk_uart_baud0", + "clk_uart_baud1"; + clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>, + <&clocks SCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@e2900c00 { + compatible = "samsung,s5pv210-uart"; + reg = <0xe2900c00 0x400>; + interrupt-parent = <&vic1>; + interrupts = <13>; + clock-names = "uart", "clk_uart_baud0", + "clk_uart_baud1"; + clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>, + <&clocks SCLK_UART3>; + status = "disabled"; + }; + + sdhci0: mmc@eb000000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0xeb000000 0x100000>; + interrupt-parent = <&vic1>; + interrupts = <26>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>, + <&clocks SCLK_MMC0>; + status = "disabled"; + }; + + sdhci1: mmc@eb100000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0xeb100000 0x100000>; + interrupt-parent = <&vic1>; + interrupts = <27>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>, + <&clocks SCLK_MMC1>; + status = "disabled"; + }; + + sdhci2: mmc@eb200000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0xeb200000 0x100000>; + interrupt-parent = <&vic1>; + interrupts = <28>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>, + <&clocks SCLK_MMC2>; + status = "disabled"; + }; + + sdhci3: mmc@eb300000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0xeb300000 0x100000>; + interrupt-parent = <&vic3>; + interrupts = <2>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3"; + clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>, + <&clocks SCLK_MMC3>; + status = "disabled"; + }; + + hsotg: usb@ec000000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0xec000000 0x20000>; + interrupt-parent = <&vic1>; + interrupts = <24>; + clocks = <&clocks CLK_USB_OTG>; + clock-names = "otg"; + phy-names = "usb2-phy"; + phys = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: usbphy@ec100000 { + compatible = "samsung,s5pv210-usb2-phy"; + reg = <0xec100000 0x100>; + samsung,pmureg-phandle = <&pmu_syscon>; + clocks = <&clocks CLK_USB_OTG>, <&xusbxti>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + ehci: usb@ec200000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0xec200000 0x100>; + interrupts = <23>; + interrupt-parent = <&vic1>; + clocks = <&clocks CLK_USB_HOST>; + clock-names = "usbhost"; + phys = <&usbphy 1>; + phy-names = "host"; + status = "disabled"; + }; + + ohci: usb@ec300000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0xec300000 0x100>; + interrupts = <23>; + interrupt-parent = <&vic1>; + clocks = <&clocks CLK_USB_HOST>; + clock-names = "usbhost"; + phys = <&usbphy 1>; + phy-names = "host"; + status = "disabled"; + }; + + mfc: codec@f1700000 { + compatible = "samsung,mfc-v5"; + reg = <0xf1700000 0x10000>; + interrupt-parent = <&vic2>; + interrupts = <14>; + clocks = <&clocks CLK_MFC>, <&clocks DOUT_MFC>; + clock-names = "mfc", "sclk_mfc"; + }; + + vic0: interrupt-controller@f2000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0xf2000000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@f2100000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0xf2100000 0x1000>; + #interrupt-cells = <1>; + }; + + vic2: interrupt-controller@f2200000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0xf2200000 0x1000>; + #interrupt-cells = <1>; + }; + + vic3: interrupt-controller@f2300000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0xf2300000 0x1000>; + #interrupt-cells = <1>; + }; + + fimd: fimd@f8000000 { + compatible = "samsung,s5pv210-fimd"; + interrupt-parent = <&vic2>; + reg = <0xf8000000 0x20000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <0>, <1>, <2>; + clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>; + clock-names = "sclk_fimd", "fimd"; + status = "disabled"; + }; + + dmc0: dmc@f0000000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf0000000 0x1000>; + }; + + dmc1: dmc@f1400000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf1400000 0x1000>; + }; + + g2d: g2d@fa000000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0xfa000000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <9>; + clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + }; + + mdma1: dma-controller@fa200000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xfa200000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <18>; + clocks = <&clocks CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + rotator: rotator@fa300000 { + compatible = "samsung,s5pv210-rotator"; + reg = <0xfa300000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <4>; + clocks = <&clocks CLK_ROTATOR>; + clock-names = "rotator"; + }; + + i2c1: i2c@fab00000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0xfab00000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <13>; + clocks = <&clocks CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + camera: camera@fa600000 { + compatible = "samsung,fimc"; + clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; + clock-names = "sclk_cam0", "sclk_cam1"; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + clock-output-names = "cam_a_clkout", "cam_b_clkout"; + ranges; + + csis0: csis@fa600000 { + compatible = "samsung,s5pv210-csis"; + reg = <0xfa600000 0x4000>; + interrupt-parent = <&vic2>; + interrupts = <29>; + clocks = <&clocks CLK_CSIS>, + <&clocks SCLK_CSIS>; + clock-names = "csis", + "sclk_csis"; + bus-width = <4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + fimc0: fimc@fb200000 { + compatible = "samsung,s5pv210-fimc"; + reg = <0xfb200000 0x1000>; + interrupts = <5>; + interrupt-parent = <&vic2>; + clocks = <&clocks CLK_FIMC0>, + <&clocks SCLK_FIMC0>; + clock-names = "fimc", + "sclk_fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,min-pix-alignment = <16 8>; + samsung,cam-if; + }; + + fimc1: fimc@fb300000 { + compatible = "samsung,s5pv210-fimc"; + reg = <0xfb300000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <6>; + clocks = <&clocks CLK_FIMC1>, + <&clocks SCLK_FIMC1>; + clock-names = "fimc", + "sclk_fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,min-pix-alignment = <1 1>; + samsung,mainscaler-ext; + samsung,cam-if; + samsung,lcd-wb; + }; + + fimc2: fimc@fb400000 { + compatible = "samsung,s5pv210-fimc"; + reg = <0xfb400000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <7>; + clocks = <&clocks CLK_FIMC2>, + <&clocks SCLK_FIMC2>; + clock-names = "fimc", + "sclk_fimc"; + samsung,pix-limits = <1920 8192 1280 1920>; + samsung,min-pix-alignment = <16 8>; + samsung,rotators = <0>; + samsung,cam-if; + }; + }; + + jpeg_codec: jpeg-codec@fb600000 { + compatible = "samsung,s5pv210-jpeg"; + reg = <0xfb600000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <8>; + clocks = <&clocks CLK_JPEG>; + clock-names = "jpeg"; + }; + }; +}; + +#include "s5pv210-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts deleted file mode 100644 index 69381819e07b..000000000000 --- a/arch/arm/boot/dts/sd5203.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2020 HiSilicon Limited. - * - * DTS file for Hisilicon SD5203 Board - */ - -/dts-v1/; - -/ { - model = "Hisilicon SD5203"; - compatible = "H836ASDJ", "hisilicon,sd5203"; - interrupt-parent = <&vic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; - }; - - aliases { - serial0 = &uart0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - reg = <0x0>; - }; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x8000000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - vic: interrupt-controller@10130000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x10130000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - refclk125mhz: refclk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - timer0: timer@16002000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x16002000 0x1000>; - interrupts = <4>; - clocks = <&refclk125mhz>; - clock-names = "apb_pclk"; - }; - - timer1: timer@16003000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x16003000 0x1000>; - interrupts = <5>; - clocks = <&refclk125mhz>; - clock-names = "apb_pclk"; - }; - - uart0: serial@1600d000 { - compatible = "snps,dw-apb-uart"; - reg = <0x1600d000 0x1000>; - bus_id = "uart0"; - clocks = <&refclk125mhz>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - interrupts = <17>; - }; - - uart1: serial@1600c000 { - compatible = "snps,dw-apb-uart"; - reg = <0x1600c000 0x1000>; - clocks = <&refclk125mhz>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - interrupts = <16>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts deleted file mode 100644 index 98897f710063..000000000000 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the KZM-A9-GT board - * - * Copyright (C) 2012 Horms Solutions Ltd. - * - * Based on sh73a0-kzm9g.dts - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -/dts-v1/; -#include "sh73a0.dtsi" -#include -#include -#include - -/ { - model = "KZM-A9-GT"; - compatible = "renesas,kzm9g", "renesas,sh73a0"; - - aliases { - serial0 = &scifa4; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = <1196000 1315000>, /* kHz uV */ - < 598000 1175000>, - < 398667 1065000>; - voltage-tolerance = <1>; /* 1% */ - }; - }; - - chosen { - bootargs = "root=/dev/nfs ip=on ignore_loglevel rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc_sdhi0: regulator-vmmc-sdhi0 { - compatible = "regulator-fixed"; - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vmmc_sdhi2: regulator-vmmc-sdhi2 { - compatible = "regulator-fixed"; - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - label = "LED1"; - }; - led2 { - gpios = <&pfc 21 GPIO_ACTIVE_LOW>; - label = "LED2"; - }; - led3 { - gpios = <&pfc 22 GPIO_ACTIVE_LOW>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 23 GPIO_ACTIVE_LOW>; - label = "LED4"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - back-key { - gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - }; - - right-key { - gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-R"; - }; - - left-key { - gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-L"; - }; - - enter-key { - gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-P"; - }; - - up-key { - gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-U"; - }; - - down-key { - gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-D"; - }; - - home-key { - gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW1"; - wakeup-source; - }; - - wakeup-key { - gpios = <&pfc 159 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "NMI"; - wakeup-source; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - simple-audio-card,codec { - sound-dai = <&ak4648>; - bitclock-master; - frame-master; - system-clock-frequency = <11289600>; - }; - }; -}; - -&bsc { - ethernet@10000000 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <0x10000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - smsc,irq-push-pull; - smsc,save-mac-address; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&extal2_clk { - clock-frequency = <48000000>; -}; - -&i2c0 { - status = "okay"; - - compass@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - interrupt-parent = <&irqpin3>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - - ak4648: codec@12 { - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - #sound-dai-cells = <0>; - }; - - accelerometer@1d { - compatible = "adi,adxl345"; - reg = <0x1d>; - interrupt-parent = <&irqpin3>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - rtc@32 { - compatible = "ricoh,r2025sd"; - reg = <0x32>; - }; - - as3711@40 { - compatible = "ams,as3711"; - reg = <0x40>; - - regulators { - vdd_dvfs: sd1 { - regulator-name = "1.315V CPU"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - sd2 { - regulator-name = "1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - sd4 { - regulator-name = "1.215V"; - regulator-min-microvolt = <1215000>; - regulator-max-microvolt = <1235000>; - regulator-always-on; - regulator-boot-on; - }; - ldo2 { - regulator-name = "2.8V CPU"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo3 { - regulator-name = "3.0V CPU"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - ldo4 { - regulator-name = "2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo5 { - regulator-name = "2.8V #2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo7 { - regulator-name = "1.15V CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - ldo8 { - regulator-name = "1.15V CPU #2"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "okay"; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pfc { - i2c3_pins: i2c3 { - groups = "i2c3_1"; - function = "i2c3"; - }; - - mmcif_pins: mmc { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - fsia_pins: sounda { - groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - function = "fsia"; - }; -}; - -&scifa4 { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi2>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi deleted file mode 100644 index 30c67acc4e35..000000000000 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ /dev/null @@ -1,949 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,sh73a0"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <1196000000>; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <1196000000>; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2>; - }; - }; - - timer@f0000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf0000200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - timer@f0000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf0000600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - L2: cache-controller@f0100000 { - compatible = "arm,pl310-cache"; - reg = <0xf0100000 0x1000>; - interrupts = ; - power-domains = <&pd_a3sm>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,shared-override; - cache-unified; - cache-level = <2>; - }; - - sbsc2: memory-controller@fb400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfb400000 0x400>; - interrupts = , - ; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc1>; - }; - - sbsc1: memory-controller@fe400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfe400000 0x400>; - interrupts = , - ; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc0>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - cmt1: timer@e6138000 { - compatible = "renesas,sh73a0-cmt1"; - reg = <0xe6138000 0x200>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - irqpin0: interrupt-controller@e6900000 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin2: interrupt-controller@e6900008 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin3: interrupt-controller@e690000c { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - i2c0: i2c@e6820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6820000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp1_clks SH73A0_CLK_IIC0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c1: i2c@e6822000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6822000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp3_clks SH73A0_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c2: i2c@e6824000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6824000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp0_clks SH73A0_CLK_IIC2>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c3: i2c@e6826000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6826000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks SH73A0_CLK_IIC3>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c4: i2c@e6828000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6828000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks SH73A0_CLK_IIC4>; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - mmcif: mmc@e6bd0000 { - compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e20000 0x0064>; - interrupts = ; - clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e10000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e00000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6c90000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee100000 0x100>; - interrupts = , - , - ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee120000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - disable-wp; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee140000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - disable-wp; - cap-sd-highspeed; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c40000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c50000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c60000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c70000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa5: serial@e6cb0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cb0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa6: serial@e6cc0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cc0000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa7: serial@e6cd0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cd0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb: serial@e6c30000 { - compatible = "renesas,scifb-sh73a0", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = - <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, - <&pfc 288 288 22>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - power-domains = <&pd_c5>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_c4: c4@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_a4bc0: a4bc0@4 { - reg = <4>; - #power-domain-cells = <0>; - }; - - pd_a4bc1: a4bc1@5 { - reg = <5>; - #power-domain-cells = <0>; - }; - - pd_a4lc0: a4lc0@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - - pd_a4lc1: a4lc1@7 { - reg = <7>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3mp: a3mp@9 { - reg = <9>; - #power-domain-cells = <0>; - }; - - pd_a3vc: a3vc@10 { - reg = <10>; - #power-domain-cells = <0>; - }; - }; - - pd_a4rm: a4rm@12 { - reg = <12>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3r: a3r@13 { - reg = <13>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2rv: a2rv@14 { - reg = <14>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - }; - }; - }; - - pd_a4s: a4s@16 { - reg = <16>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@17 { - reg = <17>; - #power-domain-cells = <0>; - }; - - pd_a3sg: a3sg@18 { - reg = <18>; - #power-domain-cells = <0>; - }; - - pd_a3sm: a3sm@19 { - reg = <19>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2sl: a2sl@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; - }; - - sh_fsi2: sound@ec230000 { - #sound-dai-cells = <1>; - compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_FSI>; - power-domains = <&pd_a4mp>; - status = "disabled"; - }; - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = ; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clocks */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - extcki_clk: extcki { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value can be overridden by the board. */ - clock-frequency = <0>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value can be overridden by the board. */ - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value can be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,sh73a0-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll3", "dsi0phy", "dsi1phy", - "zg", "m3", "b", "m1", "m2", - "z", "zx", "hp"; - }; - - /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150008 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615000c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - vclk3_clk: vclk3@e615001c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615001c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - zb_clk: zb_clk@e6150010 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150010 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - clock-output-names = "zb"; - }; - flctl_clk: flctlck@e6150014 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150014 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - sdhi0_clk: sdhi0ck@e6150074 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150074 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - sdhi1_clk: sdhi1ck@e6150078 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150078 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - sdhi2_clk: sdhi2ck@e615007c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615007c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150018 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&fsiack_clk>, <&fsiack_clk>; - #clock-cells = <0>; - }; - fsib_clk: fsib@e6150090 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150090 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&fsibck_clk>, <&fsibck_clk>; - #clock-cells = <0>; - }; - sub_clk: sub@e6150080 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150080 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - spua_clk: spua@e6150084 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150084 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - spuv_clk: spuv@e6150094 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150094 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - msu_clk: msu@e6150088 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150088 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - hsi_clk: hsi@e615008c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615008c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div7_clk>, <0>; - #clock-cells = <0>; - }; - mfg1_clk: mfg1@e6150098 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150098 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - mfg2_clk: mfg2@e615009c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615009c 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - dsit_clk: dsit@e6150060 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150060 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - dsi0p_clk: dsi0pck@e6150064 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150064 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, - <&extcki_clk>, <0>, <0>, <0>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - main_div2_clk: main_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_MAIN>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div7_clk: pll1_div7 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <7>; - clock-mult = <1>; - }; - pll1_div13_clk: pll1_div13 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <13>; - clock-mult = <1>; - }; - periph_clk: periph { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150130 4>, <0xe6150030 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 - >; - clock-output-names = - "iic2", "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150134 4>, <0xe6150038 4>; - clocks = <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_ZG>, - <&cpg_clocks SH73A0_CLK_B>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 - SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 - SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 - SH73A0_CLK_IIC0 SH73A0_CLK_SGX - SH73A0_CLK_LCDC0 - >; - clock-output-names = - "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", - "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC - SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 - SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 - SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 - SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 - SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 - SH73A0_CLK_SCIFA4 - >; - clock-output-names = - "scifa7", "sy_dmac", "mp_dmac", "msiof3", - "msiof1", "scifa5", "scifb", "msiof2", - "scifa0", "scifa1", "scifa2", "scifa3", - "scifa4"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe615013c 4>, <0xe6150048 4>; - clocks = <&sub_clk>, <&extalr_clk>, - <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, - <&sdhi0_clk>, <&sdhi1_clk>, - <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, - <&main_div2_clk>, <&main_div2_clk>, - <&main_div2_clk>, <&main_div2_clk>, - <&main_div2_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 - SH73A0_CLK_FSI SH73A0_CLK_IRDA - SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL - SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 - SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 - SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 - SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 - SH73A0_CLK_TPU4 - >; - clock-output-names = - "scifa6", "cmt1", "fsi", "irda", "iic1", - "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", - "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150140 4>, <0xe615004c 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 - SH73A0_CLK_KEYSC - >; - clock-output-names = - "iic3", "iic4", "keysc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150144 4>, <0xe615003c 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_INTCA0 - >; - clock-output-names = - "intca0"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sigmastar/Makefile b/arch/arm/boot/dts/sigmastar/Makefile new file mode 100644 index 000000000000..b07eaf5d8add --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MSTARV7) += \ + mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ + mstar-infinity2m-ssd202d-miyoo-mini.dtb \ + mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ + mstar-infinity2m-ssd202d-ssd201htv2.dtb \ + mstar-infinity2m-ssd202d-unitv2.dtb \ + mstar-infinity3-msc313e-breadbee.dtb \ + mstar-mercury5-ssc8336n-midrived08.dtb diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi new file mode 100644 index 000000000000..507ff2fba837 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include + +/ { + vcc_core: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + }; + + vcc_dram: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + vcc_io: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + red { + gpios = <&gpio MSC313_GPIO_SR_IO16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "activity"; + }; + yellow { + gpios = <&gpio MSC313_GPIO_SR_IO17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vcc_core>; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts new file mode 100644 index 000000000000..db4910dcb8a7 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity-msc313.dtsi" +#include "mstar-infinity-breadbee-common.dtsi" + +/ { + model = "BreadBee Crust"; + compatible = "thingyjp,breadbee-crust", "mstar,infinity"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi new file mode 100644 index 000000000000..3499fde263be --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi new file mode 100644 index 000000000000..441a917b88ba --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" + +#include + +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&imi { + reg = <0xa0000000 0x16000>; +}; + +&gpio { + compatible = "mstar,msc313-gpio"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi new file mode 100644 index 000000000000..34df472fed71 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/ { + reg_vcc_dram: regulator-vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts new file mode 100644 index 000000000000..f25a04c98ccb --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "DongShanPi One"; + compatible = "100ask,dongshanpione", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts new file mode 100644 index 000000000000..1bbbf47132dc --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "Miyoo Mini"; + compatible = "miyoo,miyoo-mini", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts new file mode 100644 index 000000000000..5d81641414a2 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "SSD201_HT_V2"; + compatible = "honestar,ssd201htv2", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts new file mode 100644 index 000000000000..a81684002e45 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "UnitV2"; + compatible = "m5stack,unitv2", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts new file mode 100644 index 000000000000..b15c40762bc0 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi" +#include + +/ { + model = "Wireless Tag IDO-SBC2D06-1VB-22W"; + compatible = "wirelesstag,ido-sbc2d06-v1b-22w", "mstar,infinity2m"; + + leds { + compatible = "gpio-leds"; + sys_led { + gpios = <&gpio SSD20XD_GPIO_GPIO85 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi new file mode 100644 index 000000000000..d877aff85033 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" +#include "mstar-infinity2m-ssd201-som2d01.dtsi" + +/ { + model = "Wireless Tag IDO-SOM2D01 (SSD202D)"; + compatible = "wirelesstag,ido-som2d01", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +®_vcc_dram { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi new file mode 100644 index 000000000000..176e10a29896 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m-ssd20xd.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x20000000 0x8000000>; + }; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi new file mode 100644 index 000000000000..6f067da61ba3 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m.dtsi" + +&gpio { + compatible = "sstar,ssd20xd-gpio"; + status = "okay"; +}; + +&smpctrl { + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi new file mode 100644 index 000000000000..1b485efd7156 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +&cpu0_opp_table { + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; +}; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + operating-points-v2 = <&cpu0_opp_table>; + reg = <0x1>; + clocks = <&cpupll>; + clock-names = "cpuclk"; + }; +}; + +&riu { + smpctrl: smpctrl@204000 { + reg = <0x204000 0x200>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts new file mode 100644 index 000000000000..e64ca4ce1830 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity3-msc313e.dtsi" +#include "mstar-infinity-breadbee-common.dtsi" + +/ { + model = "BreadBee"; + compatible = "thingyjp,breadbee", "mstar,infinity3"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi new file mode 100644 index 000000000000..f581b6f89555 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity3.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi new file mode 100644 index 000000000000..a56cf29e5d82 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +&cpu0_opp_table { + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + // overclock frequencies below, shown to work fine up to 1.3 GHz + opp-108000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; + +&imi { + reg = <0xa0000000 0x20000>; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts new file mode 100644 index 000000000000..7306b737d9c4 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-mercury5-ssc8336n.dtsi" + +/ { + model = "70mai Midrive D08"; + compatible = "70mai,midrived08", "mstar,mercury5"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi new file mode 100644 index 000000000000..3f5a4c029744 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-mercury5.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi b/arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi new file mode 100644 index 000000000000..a7d0dd9d6132 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; diff --git a/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi b/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi new file mode 100644 index 000000000000..3eeafd8c7121 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&cpupll>; + clock-names = "cpuclk"; + }; + }; + + arch_timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * we shouldn't need this but the vendor + * u-boot is broken + */ + clock-frequency = <6000000>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + }; + + clocks: clocks { + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + rtc_xtal: rtc_xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + status = "disabled"; + }; + + xtal_div2: xtal_div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&xtal>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x16001000 0x16001000 0x00007000>, + <0x1f000000 0x1f000000 0x00400000>, + <0xa0000000 0xa0000000 0x20000>; + + gic: interrupt-controller@16001000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x16001000 0x1000>, + <0x16002000 0x2000>, + <0x16004000 0x2000>, + <0x16006000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + riu: bus@1f000000 { + compatible = "simple-bus"; + reg = <0x1f000000 0x00400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1f000000 0x00400000>; + + pmsleep: syscon@1c00 { + compatible = "mstar,msc313-pmsleep", "syscon"; + reg = <0x1c00 0x100>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&pmsleep>; + offset = <0xb8>; + mask = <0x79>; + }; + + rtc@2400 { + compatible = "mstar,msc313-rtc"; + reg = <0x2400 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog@6000 { + compatible = "mstar,msc313e-wdt"; + reg = <0x6000 0x1f>; + clocks = <&xtal_div2>; + }; + + + intc_fiq: interrupt-controller@201310 { + compatible = "mstar,mst-intc"; + reg = <0x201310 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <96 127>; + }; + + intc_irq: interrupt-controller@201350 { + compatible = "mstar,mst-intc"; + reg = <0x201350 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <32 95>; + mstar,intc-no-eoi; + }; + + l3bridge: l3bridge@204400 { + compatible = "mstar,l3bridge"; + reg = <0x204400 0x200>; + }; + + mpll: mpll@206000 { + compatible = "mstar,msc313-mpll"; + #clock-cells = <1>; + reg = <0x206000 0x200>; + clocks = <&xtal>; + }; + + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + + gpio: gpio@207800 { + #gpio-cells = <2>; + reg = <0x207800 0x200>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc_fiq>; + status = "disabled"; + }; + + pm_uart: serial@221000 { + compatible = "ns16550a"; + reg = <0x221000 0x100>; + reg-shift = <3>; + interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <172000000>; + status = "disabled"; + }; + }; + + imi: sram@a0000000 { + compatible = "mmio-sram"; + reg = <0xa0000000 0x10000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi deleted file mode 100644 index 4c1d140f40f8..000000000000 --- a/arch/arm/boot/dts/socfpga.dtsi +++ /dev/null @@ -1,984 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "altr,socfpga-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - pmu: pmu@ff111000 { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 176 4>, <0 177 4>; - interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; - }; - - intc: interrupt-controller@fffed000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffed000 0x1000>, - <0xfffec100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffe01000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffe01000 0x1000>; - interrupts = <0 104 4>, - <0 105 4>, - <0 106 4>, - <0 107 4>, - <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>; - #dma-cells = <1>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - resets = <&rst DMA_RESET>; - reset-names = "dma"; - }; - }; - - base_fpga_region { - compatible = "fpga-region"; - fpga-mgr = <&fpgamgr0>; - - #address-cells = <0x1>; - #size-cells = <0x1>; - }; - - can0: can@ffc00000 { - compatible = "bosch,d_can"; - reg = <0xffc00000 0x1000>; - interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; - clocks = <&can0_clk>; - resets = <&rst CAN0_RESET>; - status = "disabled"; - }; - - can1: can@ffc01000 { - compatible = "bosch,d_can"; - reg = <0xffc01000 0x1000>; - interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; - clocks = <&can1_clk>; - resets = <&rst CAN1_RESET>; - status = "disabled"; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc2: osc2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_periph_ref_clk: f2s_periph_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_sdram_ref_clk: f2s_sdram_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll@40 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; - reg = <0x40>; - - mpuclk: mpuclk@48 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe0 0 9>; - reg = <0x48>; - }; - - mainclk: mainclk@4c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe4 0 9>; - reg = <0x4C>; - }; - - dbg_base_clk: dbg_base_clk@50 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>, <&osc1>; - div-reg = <0xe8 0 9>; - reg = <0x50>; - }; - - main_qspi_clk: main_qspi_clk@54 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x54>; - }; - - main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x58>; - }; - - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x5C>; - }; - }; - - periph_pll: periph_pll@80 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; - reg = <0x80>; - - emac0_clk: emac0_clk@88 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x88>; - }; - - emac1_clk: emac1_clk@8c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x8C>; - }; - - per_qspi_clk: per_qsi_clk@90 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x90>; - }; - - per_nand_mmc_clk: per_nand_mmc_clk@94 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x94>; - }; - - per_base_clk: per_base_clk@98 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x98>; - }; - - h2f_usr1_clk: h2f_usr1_clk@9c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x9C>; - }; - }; - - sdram_pll: sdram_pll@c0 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; - reg = <0xC0>; - - ddr_dqs_clk: ddr_dqs_clk@c8 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xC8>; - }; - - ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xCC>; - }; - - ddr_dq_clk: ddr_dq_clk@d0 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD0>; - }; - - h2f_usr2_clk: h2f_usr2_clk@d4 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD4>; - }; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <4>; - }; - - mpu_l2_ram_clk: mpu_l2_ram_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <2>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - clk-gate = <0x60 0>; - }; - - l3_main_clk: l3_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mainclk>; - fixed-divider = <1>; - }; - - l3_mp_clk: l3_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 0 2>; - clk-gate = <0x60 1>; - }; - - l3_sp_clk: l3_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&l3_mp_clk>; - div-reg = <0x64 2 2>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 4 3>; - clk-gate = <0x60 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 7 3>; - clk-gate = <0x60 3>; - }; - - dbg_at_clk: dbg_at_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 0 2>; - clk-gate = <0x60 4>; - }; - - dbg_clk: dbg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_at_clk>; - div-reg = <0x68 2 2>; - clk-gate = <0x60 5>; - }; - - dbg_trace_clk: dbg_trace_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x6C 0 3>; - clk-gate = <0x60 6>; - }; - - dbg_timer_clk: dbg_timer_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - clk-gate = <0x60 7>; - }; - - cfg_clk: cfg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 8>; - }; - - h2f_user0_clk: h2f_user0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 9>; - }; - - emac_0_clk: emac_0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac0_clk>; - clk-gate = <0xa0 0>; - }; - - emac_1_clk: emac_1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac1_clk>; - clk-gate = <0xa0 1>; - }; - - usb_mp_clk: usb_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 2>; - div-reg = <0xa4 0 3>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 3>; - div-reg = <0xa4 3 3>; - }; - - can0_clk: can0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 4>; - div-reg = <0xa4 6 3>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 5>; - div-reg = <0xa4 9 3>; - }; - - gpio_db_clk: gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 6>; - div-reg = <0xa8 0 24>; - }; - - h2f_user1_clk: h2f_user1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr1_clk>; - clk-gate = <0xa0 7>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 8>; - }; - - sdmmc_clk_divided: sdmmc_clk_divided { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&sdmmc_clk>; - clk-gate = <0xa0 8>; - fixed-divider = <4>; - }; - - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 9>; - }; - - nand_ecc_clk: nand_ecc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&nand_x_clk>; - clk-gate = <0xa0 9>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&nand_x_clk>; - clk-gate = <0xa0 10>; - fixed-divider = <4>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; - clk-gate = <0xa0 11>; - }; - - ddr_dqs_clk_gate: ddr_dqs_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_dqs_clk>; - clk-gate = <0xd8 0>; - }; - - ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_2x_dqs_clk>; - clk-gate = <0xd8 1>; - }; - - ddr_dq_clk_gate: ddr_dq_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_dq_clk>; - clk-gate = <0xd8 2>; - }; - - h2f_user2_clk: h2f_user2_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr2_clk>; - clk-gate = <0xd8 3>; - }; - - }; - }; - - fpga_bridge0: fpga_bridge@ff400000 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; - resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - status = "disabled"; - }; - - fpga_bridge1: fpga_bridge@ff500000 { - compatible = "altr,socfpga-hps2fpga-bridge"; - reg = <0xff500000 0x10000>; - resets = <&rst HPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - status = "disabled"; - }; - - fpga_bridge2: fpga-bridge@ff600000 { - compatible = "altr,socfpga-fpga2hps-bridge"; - reg = <0xff600000 0x100000>; - resets = <&rst FPGA2HPS_RESET>; - clocks = <&l4_main_clk>; - status = "disabled"; - }; - - fpga_bridge3: fpga-bridge@ffc25080 { - compatible = "altr,socfpga-fpga2sdram-bridge"; - reg = <0xffc25080 0x4>; - status = "disabled"; - }; - - fpgamgr0: fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000 - 0xffb90000 0x4>; - interrupts = <0 175 4>; - }; - - socfpga_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <0xf>; - snps,rd_osr_lmt = <0xf>; - snps,blen = <0 0 0 0 16 0 0>; - }; - - gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_0_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <4096>; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gmac1: ethernet@ff702000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 2>; - reg = <0xff702000 0x2000>; - interrupts = <0 120 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_1_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <4096>; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gpio0: gpio@ff708000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff708000 0x1000>; - clocks = <&l4_mp_clk>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 164 4>; - }; - }; - - gpio1: gpio@ff709000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff709000 0x1000>; - clocks = <&l4_mp_clk>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 165 4>; - }; - }; - - gpio2: gpio@ff70a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff70a000 0x1000>; - clocks = <&l4_mp_clk>; - resets = <&rst GPIO2_RESET>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 166 4>; - }; - }; - - i2c0: i2c@ffc04000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc04000 0x1000>; - resets = <&rst I2C0_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 158 0x4>; - status = "disabled"; - }; - - i2c1: i2c@ffc05000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc05000 0x1000>; - resets = <&rst I2C1_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 159 0x4>; - status = "disabled"; - }; - - i2c2: i2c@ffc06000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc06000 0x1000>; - resets = <&rst I2C2_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 160 0x4>; - status = "disabled"; - }; - - i2c3: i2c@ffc07000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc07000 0x1000>; - resets = <&rst I2C3_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 161 0x4>; - status = "disabled"; - }; - - eccmgr: eccmgr { - compatible = "altr,socfpga-ecc-manager"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l2-ecc@ffd08140 { - compatible = "altr,socfpga-l2-ecc"; - reg = <0xffd08140 0x4>; - interrupts = <0 36 1>, <0 37 1>; - }; - - ocram-ecc@ffd08144 { - compatible = "altr,socfpga-ocram-ecc"; - reg = <0xffd08144 0x4>; - iram = <&ocram>; - interrupts = <0 178 1>, <0 179 1>; - }; - }; - - L2: cache-controller@fffef000 { - compatible = "arm,pl310-cache"; - reg = <0xfffef000 0x1000>; - interrupts = <0 38 0x04>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <2 1 1>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,shared-override; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <0>; - arm,prefetch-offset = <7>; - }; - - l3regs@ff800000 { - compatible = "altr,l3regs", "syscon"; - reg = <0xff800000 0x1000>; - }; - - mmc: mmc@ff704000 { - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff704000 0x1000>; - interrupts = <0 139 4>; - fifo-depth = <0x400>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; - clock-names = "biu", "ciu"; - resets = <&rst SDMMC_RESET>; - altr,sysmgr-syscon = <&sysmgr 0x108 3>; - status = "disabled"; - }; - - nand0: nand@ff900000 { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x100000>, - <0xffb80000 0x10000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0x0 0x90 0x4>; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>; - status = "disabled"; - }; - - ocram: sram@ffff0000 { - compatible = "mmio-sram"; - reg = <0xffff0000 0x10000>; - }; - - qspi: spi@ff705000 { - compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - resets = <&rst QSPI_RESET>; - status = "disabled"; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - altr,modrst-offset = <0x10>; - }; - - scu: snoop-control-unit@fffec000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffec000 0x100>; - }; - - sdr: sdr@ffc25000 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; - resets = <&rst SDR_RESET>; - }; - - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; - - spi0: spi@fff00000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff00000 0x1000>; - interrupts = <0 154 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - resets = <&rst SPIM0_RESET>; - reset-names = "spi"; - status = "disabled"; - }; - - spi1: spi@fff01000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff01000 0x1000>; - interrupts = <0 155 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - resets = <&rst SPIM1_RESET>; - reset-names = "spi"; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; - - /* Local timer */ - timer@fffec600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf01>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc08000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 167 4>; - reg = <0xffc08000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER0_RESET>; - reset-names = "timer"; - }; - - timer1: timer1@ffc09000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 168 4>; - reg = <0xffc09000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER1_RESET>; - reset-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 169 4>; - reg = <0xffd00000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - resets = <&rst OSC1TIMER0_RESET>; - reset-names = "timer"; - }; - - timer3: timer3@ffd01000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffd01000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - resets = <&rst OSC1TIMER1_RESET>; - reset-names = "timer"; - }; - - uart0: serial@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x1000>; - interrupts = <0 162 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - dmas = <&pdma 28>, - <&pdma 29>; - dma-names = "tx", "rx"; - resets = <&rst UART0_RESET>; - }; - - uart1: serial@ffc03000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc03000 0x1000>; - interrupts = <0 163 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - dmas = <&pdma 30>, - <&pdma 31>; - dma-names = "tx", "rx"; - resets = <&rst UART1_RESET>; - }; - - usbphy0: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 125 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - resets = <&rst USB0_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 128 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - resets = <&rst USB1_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&osc1>; - resets = <&rst L4WD0_RESET>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd03000 { - compatible = "snps,dw-wdt"; - reg = <0xffd03000 0x1000>; - interrupts = <0 172 4>; - clocks = <&osc1>; - resets = <&rst L4WD1_RESET>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi deleted file mode 100644 index 72c55e5187ca..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ /dev/null @@ -1,920 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright Altera Corporation (C) 2014. All rights reserved. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "altr,socfpga-a10-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - pmu: pmu@ff111000 { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 124 4>, <0 125 4>; - interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; - }; - - intc: interrupt-controller@ffffd000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xffffd000 0x1000>, - <0xffffc100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffda1000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda1000 0x1000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, - <0 84 IRQ_TYPE_LEVEL_HIGH>, - <0 85 IRQ_TYPE_LEVEL_HIGH>, - <0 86 IRQ_TYPE_LEVEL_HIGH>, - <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>, - <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>, - <0 91 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - }; - }; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb_intosc_ls_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s_free_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll@40 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>; - reg = <0x40>; - - main_mpu_base_clk: main_mpu_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x140 0 11>; - }; - - main_noc_base_clk: main_noc_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x144 0 11>; - }; - - main_emaca_clk: main_emaca_clk@68 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x68>; - }; - - main_emacb_clk: main_emacb_clk@6c { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x6C>; - }; - - main_emac_ptp_clk: main_emac_ptp_clk@70 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x70>; - }; - - main_gpio_db_clk: main_gpio_db_clk@74 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x74>; - }; - - main_sdmmc_clk: main_sdmmc_clk@78 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk" -; - clocks = <&main_pll>; - reg = <0x78>; - }; - - main_s2f_usr0_clk: main_s2f_usr0_clk@7c { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x7C>; - }; - - main_s2f_usr1_clk: main_s2f_usr1_clk@80 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x80>; - }; - - main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x84>; - }; - - main_periph_ref_clk: main_periph_ref_clk@9c { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x9C>; - }; - }; - - periph_pll: periph_pll@c0 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>, <&main_periph_ref_clk>; - reg = <0xC0>; - - peri_mpu_base_clk: peri_mpu_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x140 16 11>; - }; - - peri_noc_base_clk: peri_noc_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x144 16 11>; - }; - - peri_emaca_clk: peri_emaca_clk@e8 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xE8>; - }; - - peri_emacb_clk: peri_emacb_clk@ec { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xEC>; - }; - - peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF0>; - }; - - peri_gpio_db_clk: peri_gpio_db_clk@f4 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF4>; - }; - - peri_sdmmc_clk: peri_sdmmc_clk@f8 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF8>; - }; - - peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xFC>; - }; - - peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x100>; - }; - - peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x104>; - }; - }; - - mpu_free_clk: mpu_free_clk@60 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x60>; - }; - - noc_free_clk: noc_free_clk@64 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x64>; - }; - - s2f_user1_free_clk: s2f_user1_free_clk@104 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x104>; - }; - - sdmmc_free_clk: sdmmc_free_clk@f8 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - fixed-divider = <4>; - reg = <0xF8>; - }; - - l4_sys_free_clk: l4_sys_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&noc_free_clk>; - fixed-divider = <4>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 0 2>; - clk-gate = <0x48 1>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 8 2>; - clk-gate = <0x48 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 16 2>; - clk-gate = <0x48 3>; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&mpu_free_clk>; - fixed-divider = <4>; - clk-gate = <0x48 0>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&sdmmc_free_clk>; - clk-gate = <0xC8 5>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 11>; - }; - - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 10>; - }; - - nand_ecc_clk: nand_ecc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&nand_x_clk>; - clk-gate = <0xC8 10>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&nand_x_clk>; - fixed-divider = <4>; - clk-gate = <0xC8 10>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 9>; - }; - - usb_clk: usb_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 8>; - }; - - s2f_usr1_clk: s2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&peri_s2f_usr1_clk>; - clk-gate = <0xC8 6>; - }; - }; - }; - - socfpga_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <0xf>; - snps,rd_osr_lmt = <0xf>; - snps,blen = <0 0 0 0 16 0 0>; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - reg = <0xff800000 0x2000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; - clock-names = "stmmaceth", "ptp_ref"; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - reg = <0xff802000 0x2000>; - interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; - clock-names = "stmmaceth", "ptp_ref"; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x4C 16>; - reg = <0xff804000 0x2000>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; - clock-names = "stmmaceth", "ptp_ref"; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gpio0: gpio@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02900 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02a00 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio2: gpio@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02b00 0x100>; - resets = <&rst GPIO2_RESET>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - fpga_mgr: fpga-mgr@ffd03000 { - compatible = "altr,socfpga-a10-fpga-mgr"; - reg = <0xffd03000 0x100 - 0xffcfe400 0x20>; - clocks = <&l4_mp_clk>; - resets = <&rst FPGAMGR_RESET>; - reset-names = "fpgamgr"; - }; - - i2c0: i2c@ffc02200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02200 0x100>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C0_RESET>; - status = "disabled"; - }; - - i2c1: i2c@ffc02300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02300 0x100>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C1_RESET>; - status = "disabled"; - }; - - i2c2: i2c@ffc02400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02400 0x100>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C2_RESET>; - status = "disabled"; - }; - - i2c3: i2c@ffc02500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02500 0x100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C3_RESET>; - status = "disabled"; - }; - - i2c4: i2c@ffc02600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02600 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C4_RESET>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x100>; - interrupts = <0 101 4>; - num-cs = <4>; - /*32bit_access;*/ - clocks = <&spi_m_clk>; - resets = <&rst SPIM0_RESET>; - reset-names = "spi"; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x100>; - interrupts = <0 102 4>; - num-cs = <4>; - /*32bit_access;*/ - tx-dma-channel = <&pdma 16>; - rx-dma-channel = <&pdma 17>; - clocks = <&spi_m_clk>; - resets = <&rst SPIM1_RESET>; - reset-names = "spi"; - status = "disabled"; - }; - - sdr: sdr@ffcfb100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffcfb100 0x80>; - }; - - L2: cache-controller@fffff000 { - compatible = "arm,pl310-cache"; - reg = <0xfffff000 0x1000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,shared-override; - }; - - mmc: mmc@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; - clock-names = "biu", "ciu"; - resets = <&rst SDMMC_RESET>; - altr,sysmgr-syscon = <&sysmgr 0x28 4>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x72000>, - <0xffb80000 0x10000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 99 4>; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - eccmgr: eccmgr { - compatible = "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-a10"; - altr,sdr-syscon = <&sdr>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, - <49 IRQ_TYPE_LEVEL_HIGH>; - }; - - l2-ecc@ffd06010 { - compatible = "altr,socfpga-a10-l2-ecc"; - reg = <0xffd06010 0x4>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, - <32 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8c3000 { - compatible = "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8c3000 0x400>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, - <33 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-rx-ecc@ff8c0800 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0800 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, - <36 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0c00 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0c00 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, - <37 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c8000 { - compatible = "altr,socfpga-dma-ecc"; - reg = <0xff8c8000 0x400>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <42 IRQ_TYPE_LEVEL_HIGH>; - }; - - usb0-ecc@ff8c8800 { - compatible = "altr,socfpga-usb-ecc"; - reg = <0xff8c8800 0x400>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <34 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - qspi: spi@ff809000 { - compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff809000 0x100>, - <0xffa00000 0x100000>; - interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - status = "disabled"; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x100>; - altr,modrst-offset = <0x20>; - }; - - scu: snoop-control-unit@ffffc000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xffffc000 0x100>; - }; - - sysmgr: sysmgr@ffd06000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd06000 0x300>; - cpu1-start-addr = <0xffd06230>; - }; - - /* Local timer */ - timer@ffffc600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xffffc600 0x100>; - interrupts = <1 13 0xf01>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc02700 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02700 0x100>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER0_RESET>; - reset-names = "timer"; - }; - - timer1: timer1@ffc02800 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02800 0x100>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER1_RESET>; - reset-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd00000 0x100>; - clocks = <&l4_sys_free_clk>; - clock-names = "timer"; - resets = <&rst L4SYSTIMER0_RESET>; - reset-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd00100 0x100>; - clocks = <&l4_sys_free_clk>; - clock-names = "timer"; - resets = <&rst L4SYSTIMER1_RESET>; - reset-names = "timer"; - }; - - uart0: serial@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - resets = <&rst UART0_RESET>; - status = "disabled"; - }; - - uart1: serial@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - resets = <&rst UART1_RESET>; - status = "disabled"; - }; - - usbphy0: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk>; - clock-names = "otg"; - resets = <&rst USB0_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk>; - clock-names = "otg"; - resets = <&rst USB1_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sys_free_clk>; - resets = <&rst L4WD0_RESET>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sys_free_clk>; - resets = <&rst L4WD1_RESET>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts deleted file mode 100644 index 422d00cd4c74..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2022 Google LLC - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model = "Google Chameleon V3"; - compatible = "google,chameleon-v3", "enclustra,mercury-aa1", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - serial0 = &uart0; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; -}; - -&gmac0 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - ssm2603: audio-codec@1a { - compatible = "adi,ssm2603"; - reg = <0x1a>; - }; -}; - -&i2c1 { - status = "okay"; - - u80: gpio@21 { - compatible = "nxp,pca9535"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SOM_AUD_MUTE", - "DP1_OUT_CEC_EN", - "DP2_OUT_CEC_EN", - "DP1_SOM_PS8469_CAD", - "DPD_SOM_PS8469_CAD", - "DP_OUT_PWR_EN", - "STM32_RST_L", - "STM32_BOOT0", - - "FPGA_PROT", - "STM32_FPGA_COMM0", - "TP119", - "TP120", - "TP121", - "TP122", - "TP123", - "TP124"; - }; -}; - -&mmc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi deleted file mode 100644 index 41f865c8c098..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2022 Google LLC - */ - -#include "socfpga_arria10.dtsi" - -/ { - - model = "Enclustra Mercury AA1"; - compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial1 = &uart1; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x80000000>; /* 2GB */ - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - - max-frame-size = <3800>; - - phy-handle = <&phy3>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy3: ethernet-phy@3 { - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - reg = <3>; - }; - }; -}; - -&i2c1 { - atsha204a: crypto@64 { - compatible = "atmel,atsha204a"; - reg = <0x64>; - }; - - isl12022: isl12022@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; -}; - -/* Following mappings are taken from arria10 socdk dts */ -&mmc { - cap-sd-highspeed; - broken-cd; - bus-width = <4>; - clk-phase-sd-hs = <0>, <135>; -}; - -&osc1 { - clock-frequency = <33330000>; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a9fd..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model = "Enclustra Mercury+ PE1"; - compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart0; - serial1 = &uart1; - }; -}; - -&gmac0 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&mmc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi deleted file mode 100644 index ec7365444a3b..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Altera Corporation - */ -#include "socfpga_arria10.dtsi" - -/ { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart1; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - a10leds { - compatible = "gpio-leds"; - - a10sr_led0 { - label = "a10sr-led0"; - gpios = <&a10sr_gpio 0 1>; - }; - - a10sr_led1 { - label = "a10sr-led1"; - gpios = <&a10sr_gpio 1 1>; - }; - - a10sr_led2 { - label = "a10sr-led2"; - gpios = <&a10sr_gpio 2 1>; - }; - - a10sr_led3 { - label = "a10sr-led3"; - gpios = <&a10sr_gpio 3 1>; - }; - }; - - ref_033v: 033-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - - /* - * These skews assume the user's FPGA design is adding 600ps of delay - * for TX_CLK on Arria 10. - * - * All skews are offset since hardware skew values for the ksz9031 - * range from a negative skew to a positive skew. - * See the micrel-ksz90x1.txt Documentation file for details. - */ - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - max-frame-size = <3800>; - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - - resource-manager@0 { - compatible = "altr,a10sr"; - reg = <0>; - spi-max-frequency = <100000>; - /* low-level active IRQ at GPIO1_5 */ - interrupt-parent = <&portb>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - a10sr_gpio: gpio-controller { - compatible = "altr,a10sr-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - a10sr_rst: reset-controller { - compatible = "altr,a10sr-reset"; - #reset-cells = <1>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - clock-frequency = <100000>; - i2c-sda-falling-time-ns = <6000>; - i2c-scl-falling-time-ns = <6000>; - - adc@14 { - compatible = "lltc,ltc2497"; - reg = <0x14>; - vref-supply = <&ref_033v>; - }; - - adc@16 { - compatible = "lltc,ltc2497"; - reg = <0x16>; - vref-supply = <&ref_033v>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; - - ltc@5c { - compatible = "ltc2977"; - reg = <0x5c>; - }; - - temp@4c { - compatible = "maxim,max1619"; - reg = <0x4c>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts deleted file mode 100644 index a662df319a84..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Altera Corporation. All rights reserved. - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x02500000>; - }; - partition@1c00000 { - label = "Root Filesystem - JFFS2"; - reg = <0x02500000 0x05500000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts deleted file mode 100644 index 11ccdc6c2dc6..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 Intel. All rights reserved. - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&qspi { - status = "okay"; - - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <3>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - label = "Boot and fpga data"; - reg = <0x0 0x2720000>; - }; - - partition@qspi-rootfs { - label = "Root Filesystem - JFFS2"; - reg = <0x2720000 0x58E0000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts deleted file mode 100644 index d3969367f4b5..000000000000 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014-2015 Altera Corporation - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&mmc { - status = "okay"; - cap-sd-highspeed; - cap-mmc-highspeed; - broken-cd; - bus-width = <4>; - clk-phase-sd-hs = <0>, <135>; -}; - -&eccmgr { - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi deleted file mode 100644 index 40fecde65c54..000000000000 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013 Altera Corporation - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: mmc@ff704000 { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - clk-phase-sd-hs = <0>, <135>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts deleted file mode 100644 index c48385702a85..000000000000 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation - */ - -#include "socfpga_arria5.dtsi" - -/ { - model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - led-hps0 { - label = "hps_led0"; - gpios = <&porta 0 1>; - }; - - led-hps1 { - label = "hps_led1"; - gpios = <&portb 11 1>; - }; - - led-hps2 { - label = "hps_led2"; - gpios = <&porta 17 1>; - }; - - led-hps3 { - label = "hps_led3"; - gpios = <&porta 18 1>; - }; - }; - - regulator_3_3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - i2c-sda-falling-time-ns = <5000>; - i2c-scl-falling-time-ns = <5000>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - /* 8MB for raw data. */ - label = "Flash 0 Raw Data"; - reg = <0x0 0x800000>; - }; - - partition@qspi-rootfs { - /* 120MB for jffs2 data. */ - label = "Flash 0 jffs2 Filesystem"; - reg = <0x800000 0x7800000>; - }; - }; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi deleted file mode 100644 index 305fe207b237..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera Corporation - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: mmc@ff704000 { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - clk-phase-sd-hs = <0>, <135>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts deleted file mode 100644 index 76262f1e5e03..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Chameleon96 - * - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -#include - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Novetech Chameleon96"; - compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x20000000>; /* 512MB */ - }; - - regulator_3_3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "green:user1"; - gpios = <&porta 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - gpios = <&porta 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - user_led3 { - label = "green:user3"; - gpios = <&porta 25 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - user_led4 { - label = "green:user4"; - gpios = <&portb 3 GPIO_ACTIVE_LOW>; - panic-indicator; - linux,default-trigger = "none"; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&i2c1 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - /* On High speed expansion */ - label = "HS-I2C2"; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&spi0 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; -}; - -&spi1 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&uart0 { - /* On Low speed expansion */ - label = "LS-UART1"; - status = "okay"; -}; - -&uart1 { - /* On Low speed expansion */ - label = "LS-UART0"; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts deleted file mode 100644 index bedf577cb056..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic DE-0(Atlas)"; - compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - ethernet0 = &gmac1; - }; - - regulator_3_3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - led-hps0 { - label = "hps_led0"; - gpios = <&portb 24 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - - max-frame-size = <3800>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - adxl345: adxl345@53 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi deleted file mode 100644 index 3b9daddf91cd..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Aries/DENX MCV"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GiB */ - }; -}; - -&mmc0 { /* On-SoM eMMC */ - bus-width = <8>; - clk-phase-sd-hs = <0>, <135>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts deleted file mode 100644 index ceaec29770c6..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "socfpga_cyclone5_mcv.dtsi" - -/ { - model = "Aries/DENX MCV EVK"; - compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - stmpe-i2c0 = &stmpe1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&gmac0 { - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpio0 { /* GPIO 0 ... 28 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 29 ... 57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - stmpe1: stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */ - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <3>; - ts,settling = <4>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts deleted file mode 100644 index c7f5fa0ba0f2..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera Corporation - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - led-hps0 { - label = "hps_led0"; - gpios = <&portb 15 1>; - }; - - led-hps1 { - label = "hps_led1"; - gpios = <&portb 14 1>; - }; - - led-hps2 { - label = "hps_led2"; - gpios = <&portb 13 1>; - }; - - led-hps3 { - label = "hps_led3"; - gpios = <&portb 12 1>; - }; - }; - - regulator_3_3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - i2c-sda-falling-time-ns = <5000>; - i2c-scl-falling-time-ns = <5000>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - cd-gpios = <&portb 18 0>; - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <0>; /* chip select */ - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - /* 8MB for raw data. */ - label = "Flash 0 Raw Data"; - reg = <0x0 0x800000>; - }; - - partition@qspi-rootfs { - /* 120MB for jffs2 data. */ - label = "Flash 0 jffs2 Filesystem"; - reg = <0x800000 0x7800000>; - }; - }; -}; - -&spi0 { - status = "okay"; - - spidev@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts deleted file mode 100644 index 3dd99c7c95e0..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Steffen Trumtrar - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic SoCkit"; - compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:blue:led0"; - gpios = <&portb 24 0>; /* HPS_GPIO53 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led1 { - label = "hps:blue:led1"; - gpios = <&portb 25 0>; /* HPS_GPIO54 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led2 { - label = "hps:blue:led2"; - gpios = <&portb 26 0>; /* HPS_GPIO55 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led3 { - label = "hps:blue:led3"; - gpios = <&portb 27 0>; /* HPS_GPIO56 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - hps_sw0 { - label = "hps_sw0"; - gpios = <&portc 20 0>; /* HPS_GPI7 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0>; /* SW_LID */ - }; - - hps_sw1 { - label = "hps_sw1"; - gpios = <&portc 19 0>; /* HPS_GPI6 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x5>; /* SW_DOCK */ - }; - - hps_sw2 { - label = "hps_sw2"; - gpios = <&portc 18 0>; /* HPS_GPI5 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ - }; - - hps_sw3 { - label = "hps_sw3"; - gpios = <&portc 17 0>; /* HPS_GPI4 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0xc>; /* SW_ROTATE_LOCK */ - }; - - hps_hkey0 { - label = "hps_hkey0"; - gpios = <&portc 21 1>; /* HPS_GPI8 */ - linux,code = <187>; /* KEY_F17 */ - }; - - hps_hkey1 { - label = "hps_hkey1"; - gpios = <&portc 22 1>; /* HPS_GPI9 */ - linux,code = <188>; /* KEY_F18 */ - }; - - hps_hkey2 { - label = "hps_hkey2"; - gpios = <&portc 23 1>; /* HPS_GPI10 */ - linux,code = <189>; /* KEY_F19 */ - }; - - hps_hkey3 { - label = "hps_hkey3"; - gpios = <&portc 24 1>; /* HPS_GPI11 */ - linux,code = <190>; /* KEY_F20 */ - }; - }; - - regulator_3_3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "VCC3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { /* GPIO 0..29 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 30..57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - accel1: accelerometer@53 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts deleted file mode 100644 index ca18b959e655..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Steffen Trumtrar - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "EBV SOCrates"; - compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; - - aliases { - ethernet0 = &gmac1; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - leds: gpio-leds { - }; -}; - -&gmac1 { - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t82"; - reg = <0x68>; - }; -}; - -&leds { - compatible = "gpio-leds"; - - led0 { - label = "led:green:heartbeat"; - gpios = <&porta 28 1>; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "led:green:D7"; - gpios = <&portb 19 1>; - }; - - led2 { - label = "led:green:D8"; - gpios = <&portb 25 1>; - }; -}; - -&mmc { - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - m25p,fast-read; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts deleted file mode 100644 index 2564671fc1c6..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Nobuhiro Iwamatsu - */ - -#include "socfpga_cyclone5.dtsi" -#include -#include - -/ { - model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; - compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - aliases { - ethernet0 = &gmac1; - }; - - regulator_3_3v: regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:green:led0"; - gpios = <&portb 12 GPIO_ACTIVE_LOW>; - }; - - hps_led1 { - label = "hps:green:led1"; - gpios = <&portb 13 GPIO_ACTIVE_LOW>; - }; - - hps_led2 { - label = "hps:green:led2"; - gpios = <&portb 14 GPIO_ACTIVE_LOW>; - }; - - hps_led3 { - label = "hps:green:led3"; - gpios = <&portb 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - phy = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - cd-gpios = <&portb 18 0>; - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q512a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts deleted file mode 100644 index e0630b0eed03..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "socfpga_cyclone5.dtsi" -#include -#include - -/ { - model = "samtec VIN|ING FPGA"; - compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* - * This allow the ethaddr uboot environment variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - ethernet1 = &gmac0; - }; - - gpio-keys { - compatible = "gpio-keys"; - - hps_temp0 { - label = "BTN_0"; /* TEMP_OS */ - gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPI5 */ - linux,code = ; - }; - - hps_hkey0 { - label = "GP_SWITCH"; /* GP_SWITCH */ - gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPI6 */ - linux,code = ; - }; - - hps_hkey1 { - label = "RESET_SWITCH"; /* RESET_SWITCH */ - gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPI7 */ - linux,code = ; - }; - - hps_hkey2 { - label = "POWER_DOWN"; /* POWER_DOWN */ - gpios = <&portc 4 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ - linux,code = ; - }; - - hps_hkey3 { - label = "SENSE"; /* SENSE */ - gpios = <&porta 9 GPIO_ACTIVE_LOW>; /* HPS_GPIO9 */ - linux,code = ; - }; - }; - - regulator-usb-nrst { - compatible = "regulator-fixed"; - regulator-name = "usb_nrst"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <10000 10000 10000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <1860>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpio0 { /* GPIO 0..29 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 30..57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - gpio: pca9557@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - }; - - temp: lm75@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - at24@50 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c@6 { /* Backplane EEPROM */ - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - eeprom@51 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@7 { /* Power board EEPROM */ - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - eeprom@51 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <8>; - reg = <0x50>; - }; -}; - -&qspi { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128", "jedec,spi-nor"; - reg = <0>; /* chip select */ - spi-max-frequency = <100000000>; - m25p,fast-read; - - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <1>; /* chip select */ - spi-max-frequency = <100000000>; - m25p,fast-read; - - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; -}; - -&usb0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts deleted file mode 100644 index 845ab2cc5ce6..000000000000 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation - */ - -/dts-v1/; -#include "socfpga.dtsi" - -/ { - model = "Altera SOCFPGA VT"; - compatible = "altr,socfpga-vt", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <10000000>; - }; - }; - }; - - mmc@ff704000 { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - ethernet@ff700000 { - phy-mode = "gmii"; - status = "okay"; - }; - - timer0@ffc08000 { - clock-frequency = <7000000>; - }; - - timer1@ffc09000 { - clock-frequency = <7000000>; - }; - - timer2@ffd00000 { - clock-frequency = <7000000>; - }; - - timer3@ffd01000 { - clock-frequency = <7000000>; - }; - - serial@ffc02000 { - clock-frequency = <7372800>; - }; - - serial@ffc03000 { - clock-frequency = <7372800>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd08010>; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "gmii"; -}; diff --git a/arch/arm/boot/dts/socionext/Makefile b/arch/arm/boot/dts/socionext/Makefile new file mode 100644 index 000000000000..dab4275f6bd6 --- /dev/null +++ b/arch/arm/boot/dts/socionext/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb +dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ld4-ref.dtb \ + uniphier-ld6b-ref.dtb \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb \ + uniphier-pro5-epcore.dtb \ + uniphier-pro5-proex.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ + uniphier-sld8-ref.dtb diff --git a/arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts new file mode 100644 index 000000000000..614f60c6b0a2 --- /dev/null +++ b/arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "rootwait earlycon"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + +}; diff --git a/arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi b/arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi new file mode 100644 index 000000000000..75f0c0af2270 --- /dev/null +++ b/arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,milbeaut-m10v-smp"; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + clk: clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + + timer@1e000050 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + clocks = <&clk 4>; + }; + + uart1: serial@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + }; + + }; + + sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts b/arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts new file mode 100644 index 000000000000..e007db084787 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD4 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-ld4.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD4 Reference Board"; + compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serialsc; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +ðsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&gpio { + xirq1-hog { + gpio-hog; + gpios = ; + input; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-ld4.dtsi b/arch/arm/boot/dts/socionext/uniphier-ld4.dtsi new file mode 100644 index 000000000000..df2de7a40211 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-ld4.dtsi @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD4 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +#include +#include + +/ { + compatible = "socionext,uniphier-ld4"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + arm_timer_clk: arm-timer { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = , + ; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <136>; + socionext,interrupt-ranges = <0 48 13>, <14 62 2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; + clock-frequency = <100000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59801000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + syscon@59810000 { + compatible = "socionext,uniphier-ld4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock-controller { + compatible = "socionext,uniphier-ld4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset-controller { + compatible = "socionext,uniphier-ld4-mio-reset"; + #reset-cells = <1>; + }; + }; + + syscon@59820000 { + compatible = "socionext,uniphier-ld4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock-controller { + compatible = "socionext,uniphier-ld4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset-controller { + compatible = "socionext,uniphier-ld4-peri-reset"; + #reset-cells = <1>; + }; + }; + + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = , + , + , + , + , + , + ; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + + sd: mmc@5a400000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = ; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + }; + + emmc: mmc@5a500000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + non-removable; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, + <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + has-transaction-translator; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, + <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + has-transaction-translator; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, + <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + has-transaction-translator; + }; + + syscon@5f800000 { + compatible = "socionext,uniphier-ld4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld4-pinctrl"; + }; + }; + + syscon@5f900000 { + compatible = "socionext,uniphier-ld4-soc-glue-debug", + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + aidet: interrupt-controller@61830000 { + compatible = "socionext,uniphier-ld4-aidet"; + reg = <0x61830000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + syscon@61840000 { + compatible = "socionext,uniphier-ld4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock-controller { + compatible = "socionext,uniphier-ld4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset-controller { + compatible = "socionext,uniphier-ld4-reset"; + #reset-cells = <1>; + }; + }; + + nand: nand-controller@68000000 { + compatible = "socionext,uniphier-denali-nand-v5a"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; + reset-names = "nand", "reg"; + resets = <&sys_rst 2>, <&sys_rst 2>; + }; + }; +}; + +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts new file mode 100644 index 000000000000..223a78b4a761 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD6b Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-ld6b.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD6b Reference Board"; + compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serialsc; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +ðsc { + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&gpio { + xirq4-hog { + gpio-hog; + gpios = ; + input; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi b/arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi new file mode 100644 index 000000000000..4d07a94c6b34 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD6b SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/* + * LD6b consists of two silicon dies: D-chip and A-chip. + * The D-chip (digital chip) is the same as the PXs2 die. + * Reuse the PXs2 device tree with some properties overridden. + */ +#include "uniphier-pxs2.dtsi" + +/ { + compatible = "socionext,uniphier-ld6b"; +}; + +/* UART3 unavailable: the pads are not wired to the package balls */ +&serial3 { + status = "disabled"; +}; + +/* + * LD6b and PXs2 have completely different packages, + * which makes the pinctrl driver unshareable. + */ +&pinctrl { + compatible = "socionext,uniphier-ld6b-pinctrl"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi new file mode 100644 index 000000000000..f909ec2e5333 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier SoCs default pinctrl settings +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada + +&pinctrl { + pinctrl_aout: aout { + groups = "aout"; + function = "aout"; + }; + + pinctrl_ain1: ain1 { + groups = "ain1"; + function = "ain1"; + }; + + pinctrl_ain2: ain2 { + groups = "ain2"; + function = "ain2"; + }; + + pinctrl_ainiec1: ainiec1 { + groups = "ainiec1"; + function = "ainiec1"; + }; + + pinctrl_aout1: aout1 { + groups = "aout1"; + function = "aout1"; + }; + + pinctrl_aout2: aout2 { + groups = "aout2"; + function = "aout2"; + }; + + pinctrl_aout3: aout3 { + groups = "aout3"; + function = "aout3"; + }; + + pinctrl_aoutiec1: aoutiec1 { + groups = "aoutiec1"; + function = "aoutiec1"; + }; + + pinctrl_aoutiec2: aoutiec2 { + groups = "aoutiec2"; + function = "aoutiec2"; + }; + + pinctrl_emmc: emmc { + groups = "emmc", "emmc_dat8"; + function = "emmc"; + }; + + pinctrl_ether_mii: ether-mii { + groups = "ether_mii"; + function = "ether_mii"; + }; + + pinctrl_ether_rgmii: ether-rgmii { + groups = "ether_rgmii"; + function = "ether_rgmii"; + }; + + pinctrl_ether_rmii: ether-rmii { + groups = "ether_rmii"; + function = "ether_rmii"; + }; + + pinctrl_ether1_rgmii: ether1-rgmii { + groups = "ether1_rgmii"; + function = "ether1_rgmii"; + }; + + pinctrl_ether1_rmii: ether1-rmii { + groups = "ether1_rmii"; + function = "ether1_rmii"; + }; + + pinctrl_i2c0: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + pinctrl_i2c1: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + pinctrl_i2c2: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + pinctrl_i2c3: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + + pinctrl_i2c4: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + pinctrl_i2c5: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + pinctrl_i2c6: i2c6 { + groups = "i2c6"; + function = "i2c6"; + }; + + pinctrl_nand: nand { + groups = "nand"; + function = "nand"; + }; + + pinctrl_nand2cs: nand2cs { + groups = "nand", "nand_cs1"; + function = "nand"; + }; + + pinctrl_pcie: pcie { + groups = "pcie"; + function = "pcie"; + }; + + pinctrl_sd: sd { + groups = "sd"; + function = "sd"; + }; + + pinctrl_sd_uhs: sd-uhs { + groups = "sd"; + function = "sd"; + }; + + pinctrl_sd1: sd1 { + groups = "sd1"; + function = "sd1"; + }; + + pinctrl_spi0: spi0 { + groups = "spi0"; + function = "spi0"; + }; + + pinctrl_spi1: spi1 { + groups = "spi1"; + function = "spi1"; + }; + + pinctrl_spi2: spi2 { + groups = "spi2"; + function = "spi2"; + }; + + pinctrl_spi3: spi3 { + groups = "spi3"; + function = "spi3"; + }; + + pinctrl_system_bus: system-bus { + groups = "system_bus", "system_bus_cs1"; + function = "system_bus"; + }; + + pinctrl_uart0: uart0 { + groups = "uart0"; + function = "uart0"; + }; + + pinctrl_uart1: uart1 { + groups = "uart1"; + function = "uart1"; + }; + + pinctrl_uart2: uart2 { + groups = "uart2"; + function = "uart2"; + }; + + pinctrl_uart3: uart3 { + groups = "uart3"; + function = "uart3"; + }; + + pinctrl_usb0: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + pinctrl_usb0_device: usb0-device { + groups = "usb0_device"; + function = "usb0"; + }; + + pinctrl_usb1: usb1 { + groups = "usb1"; + function = "usb1"; + }; + + pinctrl_usb1_device: usb1-device { + groups = "usb1_device"; + function = "usb1"; + }; + + pinctrl_usb2: usb2 { + groups = "usb2"; + function = "usb2"; + }; + + pinctrl_usb3: usb3 { + groups = "usb3"; + function = "usb3"; + }; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts new file mode 100644 index 000000000000..6baee4410d9c --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Ace Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-pro4.dtsi" + +/ { + model = "UniPhier Pro4 Ace Board"; + compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts new file mode 100644 index 000000000000..d2ce5c039865 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-pro4.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier Pro4 Reference Board"; + compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serialsc; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +ðsc { + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&gpio { + xirq2-hog { + gpio-hog; + gpios = ; + input; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + }; +}; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts new file mode 100644 index 000000000000..7b6faf2e795e --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Sanji Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-pro4.dtsi" + +/ { + model = "UniPhier Pro4 Sanji Board"; + compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pro4.dtsi b/arch/arm/boot/dts/socionext/uniphier-pro4.dtsi new file mode 100644 index 000000000000..ba55af30e904 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro4.dtsi @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +#include +#include + +/ { + compatible = "socionext,uniphier-pro4"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + arm_timer_clk: arm-timer { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = , + ; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59801000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl: syscon@59810000 { + compatible = "socionext,uniphier-pro4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock-controller { + compatible = "socionext,uniphier-pro4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset-controller { + compatible = "socionext,uniphier-pro4-mio-reset"; + #reset-cells = <1>; + }; + }; + + syscon@59820000 { + compatible = "socionext,uniphier-pro4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock-controller { + compatible = "socionext,uniphier-pro4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset-controller { + compatible = "socionext,uniphier-pro4-peri-reset"; + #reset-cells = <1>; + }; + }; + + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + + sd: mmc@5a400000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = ; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&mioctrl 0>; + }; + + emmc: mmc@5a500000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 5>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + non-removable; + }; + + sd1: mmc@5a600000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a600000 0x200>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + clocks = <&mio_clk 2>; + reset-names = "host", "bridge"; + resets = <&mio_rst 2>, <&mio_rst 5>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; + bus-width = <4>; + cap-sd-highspeed; + }; + + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, + <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; + has-transaction-translator; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, + <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; + has-transaction-translator; + }; + + soc_glue: syscon@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + + usb-hub { + compatible = "socionext,uniphier-pro4-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + vbus-supply = <&usb0_vbus>; + }; + + usb_phy3: phy@3 { + reg = <3>; + #phy-cells = <0>; + vbus-supply = <&usb1_vbus>; + }; + }; + + sg_clk: clock-controller { + compatible = "socionext,uniphier-pro4-sg-clock"; + #clock-cells = <1>; + }; + }; + + syscon@5f900000 { + compatible = "socionext,uniphier-pro4-soc-glue-debug", + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x14>; + }; + }; + + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <2>; + }; + + aidet: interrupt-controller@5fc20000 { + compatible = "socionext,uniphier-pro4-aidet"; + reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + syscon@61840000 { + compatible = "socionext,uniphier-pro4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock-controller { + compatible = "socionext,uniphier-pro4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset-controller { + compatible = "socionext,uniphier-pro4-reset"; + #reset-cells = <1>; + }; + }; + + eth: ethernet@65000000 { + compatible = "socionext,uniphier-pro4-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clock-names = "gio", "ether", "ether-gb", "ether-phy"; + clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, + <&sys_clk 10>; + reset-names = "gio", "ether"; + resets = <&sys_rst 12>, <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + socionext,syscon-phy-mode = <&soc_glue 0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ahci0: sata@65600000 { + compatible = "socionext,uniphier-pro4-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = ; + clocks = <&sys_clk 12>, <&sys_clk 28>; + resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>; + ports-implemented = <1>; + phys = <&ahci0_phy>; + assigned-clocks = <&sg_clk 0>; + assigned-clock-rates = <25000000>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + reg = <0x65700000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci0_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro4-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 28>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci0_phy: phy@10 { + compatible = "socionext,uniphier-pro4-ahci-phy"; + reg = <0x10 0x40>; + clock-names = "link", "gio"; + clocks = <&sys_clk 28>, <&sys_clk 12>; + reset-names = "link", "gio", "phy", + "pm", "tx", "rx"; + resets = <&sys_rst 28>, <&sys_rst 12>, + <&sys_rst 30>, + <&ahci0_rst 0>, <&ahci0_rst 1>, + <&ahci0_rst 2>; + #phy-cells = <0>; + }; + }; + + ahci1: sata@65800000 { + compatible = "socionext,uniphier-pro4-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65800000 0x10000>; + interrupts = ; + clocks = <&sys_clk 12>, <&sys_clk 29>; + resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>; + ports-implemented = <1>; + phys = <&ahci1_phy>; + assigned-clocks = <&sg_clk 0>; + assigned-clock-rates = <25000000>; + }; + + sata-controller@65900000 { + compatible = "socionext,uniphier-pro4-ahci-glue", + "simple-mfd"; + reg = <0x65900000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65900000 0x100>; + + ahci1_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro4-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 29>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 29>; + #reset-cells = <1>; + }; + + ahci1_phy: phy@10 { + compatible = "socionext,uniphier-pro4-ahci-phy"; + reg = <0x10 0x40>; + clock-names = "link", "gio"; + clocks = <&sys_clk 29>, <&sys_clk 12>; + reset-names = "link", "gio", "phy", + "pm", "tx", "rx"; + resets = <&sys_rst 29>, <&sys_rst 12>, + <&sys_rst 30>, + <&ahci1_rst 0>, <&ahci1_rst 1>, + <&ahci1_rst 2>; + #phy-cells = <0>; + }; + }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = , + ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 4>; + phys = <&usb_phy2>, <&usb0_ssphy>; + dr_mode = "host"; + }; + + usb-controller@65b00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + reg = <0x65b00000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x100>; + + usb0_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_ssphy: phy@10 { + compatible = "socionext,uniphier-pro4-usb3-ssphy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus>; + }; + + usb0_rst: reset-controller@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = , + ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb1_rst 4>; + phys = <&usb_phy3>; + dr_mode = "host"; + }; + + usb-controller@65d00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + reg = <0x65d00000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x100>; + + usb1_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_rst: reset-controller@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + }; + + nand: nand-controller@68000000 { + compatible = "socionext,uniphier-denali-nand-v5a"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; + reset-names = "nand", "reg"; + resets = <&sys_rst 2>, <&sys_rst 2>; + }; + }; +}; + +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts new file mode 100644 index 000000000000..ed759dcc3216 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE) + * + * Copyright (C) 2021 Socionext Inc. + * Author: Kunihiko Hayashi + */ + +/dts-v1/; +#include "uniphier-pro5.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier Pro5 EP-CORE Board"; + compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +ðsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&pcie_ep { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts b/arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts new file mode 100644 index 000000000000..2cfb84f73cc0 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for UniPhier Pro5 ProEX Board + * + * Copyright (C) 2021 Socionext Inc. + * Author: Kunihiko Hayashi + */ + +/dts-v1/; +#include "uniphier-pro5.dtsi" + +/ { + model = "UniPhier Pro5 ProEX Board"; + compatible = "socionext,uniphier-pro5-proex", "socionext,uniphier-pro5"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&pcie_ep { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pro5.dtsi b/arch/arm/boot/dts/socionext/uniphier-pro5.dtsi new file mode 100644 index 000000000000..2d8591cdddb8 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pro5.dtsi @@ -0,0 +1,707 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro5 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +#include + +/ { + compatible = "socionext,uniphier-pro5"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&sys_clk 32>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clocks = <&sys_clk 32>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + }; + }; + + cpu_opp: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp-116667000 { + opp-hz = /bits/ 64 <116667000>; + clock-latency-ns = <300>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp-175000000 { + opp-hz = /bits/ 64 <175000000>; + clock-latency-ns = <300>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp-233334000 { + opp-hz = /bits/ 64 <233334000>; + clock-latency-ns = <300>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + clock-latency-ns = <300>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp-466667000 { + opp-hz = /bits/ 64 <466667000>; + clock-latency-ns = <300>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <300>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp-933334000 { + opp-hz = /bits/ 64 <933334000>; + clock-latency-ns = <300>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <300>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + arm_timer_clk: arm-timer { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = , + ; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: cache-controller@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + interrupts = , + ; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; + + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; /* common with spi0 */ + resets = <&peri_rst 12>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59801000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl: syscon@59810000 { + compatible = "socionext,uniphier-pro5-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x400>; + + sd_clk: clock-controller { + compatible = "socionext,uniphier-pro5-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset-controller { + compatible = "socionext,uniphier-pro5-sd-reset"; + #reset-cells = <1>; + }; + }; + + syscon@59820000 { + compatible = "socionext,uniphier-pro5-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock-controller { + compatible = "socionext,uniphier-pro5-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset-controller { + compatible = "socionext,uniphier-pro5-peri-reset"; + #reset-cells = <1>; + }; + }; + + syscon@5f800000 { + compatible = "socionext,uniphier-pro5-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro5-pinctrl"; + }; + }; + + syscon@5f900000 { + compatible = "socionext,uniphier-pro5-soc-glue-debug", + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x28>; + }; + + efuse@300 { + compatible = "socionext,uniphier-efuse"; + reg = <0x300 0x14>; + }; + + efuse@400 { + compatible = "socionext,uniphier-efuse"; + reg = <0x400 0x8>; + }; + }; + + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <2>; + }; + + aidet: interrupt-controller@5fc20000 { + compatible = "socionext,uniphier-pro5-aidet"; + reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + syscon@61840000 { + compatible = "socionext,uniphier-pro5-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock-controller { + compatible = "socionext,uniphier-pro5-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset-controller { + compatible = "socionext,uniphier-pro5-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_ssphy0>; + dr_mode = "host"; + }; + + usb-controller@65b00000 { + compatible = "socionext,uniphier-pro5-dwc3-glue", + "simple-mfd"; + reg = <0x65b00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro5-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pro5-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_hsphy0: phy@280 { + compatible = "socionext,uniphier-pro5-usb3-hsphy"; + reg = <0x280 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy0: phy@380 { + compatible = "socionext,uniphier-pro5-usb3-ssphy"; + reg = <0x380 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus0>; + }; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-controller@65d00000 { + compatible = "socionext,uniphier-pro5-dwc3-glue", + "simple-mfd"; + reg = <0x65d00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro5-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pro5-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pro5-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_hsphy0: phy@280 { + compatible = "socionext,uniphier-pro5-usb3-hsphy"; + reg = <0x280 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + vbus-supply = <&usb1_vbus0>; + }; + + usb1_hsphy1: phy@290 { + compatible = "socionext,uniphier-pro5-usb3-hsphy"; + reg = <0x290 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + vbus-supply = <&usb1_vbus1>; + }; + + usb1_ssphy0: phy@380 { + compatible = "socionext,uniphier-pro5-usb3-ssphy"; + reg = <0x380 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + pcie_ep: pcie-ep@66000000 { + compatible = "socionext,uniphier-pro5-pcie-ep"; + status = "disabled"; + reg-names = "dbi", "dbi2", "link", "addr_space"; + reg = <0x66000000 0x1000>, <0x66001000 0x1000>, + <0x66010000 0x10000>, <0x67000000 0x400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-lanes = <4>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-pro5-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + }; + + nand: nand-controller@68000000 { + compatible = "socionext,uniphier-denali-nand-v5b"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; + reset-names = "nand", "reg"; + resets = <&sys_rst 2>, <&sys_rst 2>; + }; + + emmc: mmc@68400000 { + compatible = "socionext,uniphier-sd-v3.1"; + status = "disabled"; + reg = <0x68400000 0x800>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&sd_clk 1>; + reset-names = "host", "hw"; + resets = <&sd_rst 1>, <&sd_rst 6>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + non-removable; + }; + + sd: mmc@68800000 { + compatible = "socionext,uniphier-sd-v3.1"; + status = "disabled"; + reg = <0x68800000 0x800>; + interrupts = ; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&sd_clk 0>; + reset-names = "host"; + resets = <&sd_rst 0>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&sdctrl 0>; + }; + }; +}; + +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts new file mode 100644 index 000000000000..5f18b926c50a --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 Gentil Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-pxs2.dtsi" + +/ { + model = "UniPhier PXs2 Gentil Board"; + compatible = "socionext,uniphier-pxs2-gentil", + "socionext,uniphier-pxs2"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier PXs2"; + dais = <&i2s_port2>; + }; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2s_aux { + dai-format = "i2s"; + remote-endpoint = <&wm_speaker>; +}; + +&i2c2 { + status = "okay"; + + wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + + port@0 { + wm_speaker: endpoint { + dai-format = "i2s"; + remote-endpoint = <&i2s_aux>; + }; + }; + }; +}; + +&emmc { + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&ahci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts new file mode 100644 index 000000000000..7e08a459f7d8 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 Vodka Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-pxs2.dtsi" + +/ { + model = "UniPhier PXs2 Vodka Board"; + compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier PXs2"; + dais = <&spdif_port0 + &comp_spdif_port0>; + }; + + spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + spdif_tx: endpoint { + remote-endpoint = <&spdif_hiecout1>; + }; + }; + }; + + comp-spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + comp_spdif_tx: endpoint { + remote-endpoint = <&comp_spdif_hiecout1>; + }; + }; + }; +}; + +&serial2 { + status = "okay"; +}; + +&spdif_hiecout1 { + remote-endpoint = <&spdif_tx>; +}; + +&comp_spdif_hiecout1 { + remote-endpoint = <&comp_spdif_tx>; +}; + +&i2c0 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi b/arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi new file mode 100644 index 000000000000..f97a57222101 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi @@ -0,0 +1,845 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +#include +#include +#include + +/ { + compatible = "socionext,uniphier-pxs2"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&sys_clk 32>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + clocks = <&sys_clk 32>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + clocks = <&sys_clk 32>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + clocks = <&sys_clk 32>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; + }; + }; + + cpu_opp: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + arm_timer_clk: arm-timer { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = , + , + , + ; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; + + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 12>; + resets = <&peri_rst 12>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1"; + ngpios = <232>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; + }; + + audio@56000000 { + compatible = "socionext,uniphier-pxs2-aio"; + reg = <0x56000000 0x80000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ain1>, + <&pinctrl_ain2>, + <&pinctrl_ainiec1>, + <&pinctrl_aout2>, + <&pinctrl_aout3>, + <&pinctrl_aoutiec1>, + <&pinctrl_aoutiec2>; + clock-names = "aio"; + clocks = <&sys_clk 40>; + reset-names = "aio"; + resets = <&sys_rst 40>; + #sound-dai-cells = <1>; + socionext,syscon = <&soc_glue>; + + i2s_port0: port@0 { + i2s_hdmi: endpoint { + }; + }; + + i2s_port1: port@1 { + i2s_line: endpoint { + }; + }; + + i2s_port2: port@2 { + i2s_aux: endpoint { + }; + }; + + spdif_port0: port@3 { + spdif_hiecout1: endpoint { + }; + }; + + spdif_port1: port@4 { + spdif_iecout1: endpoint { + }; + }; + + comp_spdif_port0: port@5 { + comp_spdif_hiecout1: endpoint { + }; + }; + + comp_spdif_port1: port@6 { + comp_spdif_iecout1: endpoint { + }; + }; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 8>; + resets = <&peri_rst 8>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59801000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl: syscon@59810000 { + compatible = "socionext,uniphier-pxs2-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x400>; + + sd_clk: clock-controller { + compatible = "socionext,uniphier-pxs2-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset-controller { + compatible = "socionext,uniphier-pxs2-sd-reset"; + #reset-cells = <1>; + }; + }; + + syscon@59820000 { + compatible = "socionext,uniphier-pxs2-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock-controller { + compatible = "socionext,uniphier-pxs2-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset-controller { + compatible = "socionext,uniphier-pxs2-peri-reset"; + #reset-cells = <1>; + }; + }; + + emmc: mmc@5a000000 { + compatible = "socionext,uniphier-sd-v3.1.1"; + status = "disabled"; + reg = <0x5a000000 0x800>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&sd_clk 1>; + reset-names = "host", "hw"; + resets = <&sd_rst 1>, <&sd_rst 6>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + non-removable; + }; + + sd: mmc@5a400000 { + compatible = "socionext,uniphier-sd-v3.1.1"; + status = "disabled"; + reg = <0x5a400000 0x800>; + interrupts = ; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&sd_clk 0>; + reset-names = "host"; + resets = <&sd_rst 0>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&sdctrl 0>; + }; + + soc_glue: syscon@5f800000 { + compatible = "socionext,uniphier-pxs2-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pxs2-pinctrl"; + }; + }; + + syscon@5f900000 { + compatible = "socionext,uniphier-pxs2-soc-glue-debug", + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x58>; + }; + }; + + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <2>; + }; + + aidet: interrupt-controller@5fc20000 { + compatible = "socionext,uniphier-pxs2-aidet"; + reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + syscon@61840000 { + compatible = "socionext,uniphier-pxs2-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock-controller { + compatible = "socionext,uniphier-pxs2-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset-controller { + compatible = "socionext,uniphier-pxs2-reset"; + #reset-cells = <1>; + }; + + pvtctl: thermal-sensor { + compatible = "socionext,uniphier-pxs2-thermal"; + interrupts = ; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f86 0x6844>; + }; + }; + + eth: ethernet@65000000 { + compatible = "socionext,uniphier-pxs2-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clock-names = "ether"; + clocks = <&sys_clk 6>; + reset-names = "ether"; + resets = <&sys_rst 6>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + socionext,syscon-phy-mode = <&soc_glue 0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ahci: sata@65600000 { + compatible = "socionext,uniphier-pxs2-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = ; + clocks = <&sys_clk 28>; + resets = <&sys_rst 28>, <&ahci_rst 0>; + ports-implemented = <1>; + phys = <&ahci_phy>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + reg = <0x65700000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci_rst: reset-controller@0 { + compatible = "socionext,uniphier-pxs2-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link"; + resets = <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci_phy: phy@10 { + compatible = "socionext,uniphier-pxs2-ahci-phy"; + reg = <0x10 0x10>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + #phy-cells = <0>; + }; + }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "dwc_usb3"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-controller@65b00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + reg = <0x65b00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset-controller@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_hsphy0: phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_hsphy1: phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + }; + + usb0_ssphy0: phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: phy@310 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "dwc_usb3"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-controller@65d00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + reg = <0x65d00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset-controller@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_hsphy0: phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + }; + + usb1_hsphy1: phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + }; + + usb1_ssphy0: phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 21>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + nand: nand-controller@68000000 { + compatible = "socionext,uniphier-denali-nand-v5b"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; + reset-names = "nand", "reg"; + resets = <&sys_rst 2>, <&sys_rst 2>; + }; + }; +}; + +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi new file mode 100644 index 000000000000..a11897669c26 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Reference Daughter Board +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada + +&i2c0 { + eeprom@50 { + compatible = "microchip,24lc128", "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts b/arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts new file mode 100644 index 000000000000..2446f9e15360 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier sLD8 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +/dts-v1/; +#include "uniphier-sld8.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier sLD8 Reference Board"; + compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serialsc; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +ðsc { + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&gpio { + xirq0-hog { + gpio-hog; + gpios = ; + input; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/socionext/uniphier-sld8.dtsi b/arch/arm/boot/dts/socionext/uniphier-sld8.dtsi new file mode 100644 index 000000000000..f876282760e9 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-sld8.dtsi @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier sLD8 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada + +#include +#include + +/ { + compatible = "socionext,uniphier-sld8"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + arm_timer_clk: arm-timer { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = , + ; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 104 0 0>, + <&pinctrl 112 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <136>; + socionext,interrupt-ranges = <0 48 13>, <14 62 2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; + clock-frequency = <100000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59801000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl: syscon@59810000 { + compatible = "socionext,uniphier-sld8-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock-controller { + compatible = "socionext,uniphier-sld8-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset-controller { + compatible = "socionext,uniphier-sld8-mio-reset"; + #reset-cells = <1>; + }; + }; + + syscon@59820000 { + compatible = "socionext,uniphier-sld8-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock-controller { + compatible = "socionext,uniphier-sld8-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset-controller { + compatible = "socionext,uniphier-sld8-peri-reset"; + #reset-cells = <1>; + }; + }; + + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = , + , + , + , + , + , + ; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + + sd: mmc@5a400000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = ; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&mioctrl 0>; + }; + + emmc: mmc@5a500000 { + compatible = "socionext,uniphier-sd-v2.91"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + non-removable; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, + <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + has-transaction-translator; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, + <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + has-transaction-translator; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, + <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + has-transaction-translator; + }; + + syscon@5f800000 { + compatible = "socionext,uniphier-sld8-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld8-pinctrl"; + }; + }; + + syscon@5f900000 { + compatible = "socionext,uniphier-sld8-soc-glue-debug", + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x14>; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + aidet: interrupt-controller@61830000 { + compatible = "socionext,uniphier-sld8-aidet"; + reg = <0x61830000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + syscon@61840000 { + compatible = "socionext,uniphier-sld8-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock-controller { + compatible = "socionext,uniphier-sld8-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset-controller { + compatible = "socionext,uniphier-sld8-reset"; + #reset-cells = <1>; + }; + }; + + nand: nand-controller@68000000 { + compatible = "socionext,uniphier-denali-nand-v5a"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; + reset-names = "nand", "reg"; + resets = <&sys_rst 2>, <&sys_rst 2>; + }; + }; +}; + +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm/boot/dts/socionext/uniphier-support-card.dtsi new file mode 100644 index 000000000000..97e7d5db8eb8 --- /dev/null +++ b/arch/arm/boot/dts/socionext/uniphier-support-card.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Support Card (Expansion Board) +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada + +&system_bus { + status = "okay"; + ranges = <1 0x00000000 0x42000000 0x02000000>; + + ethsc: ethernet@1,1f00000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <1 0x01f00000 0x1000>; + phy-mode = "mii"; + reg-io-width = <4>; + interrupt-parent = <&gpio>; + }; + + serialsc: serial@1,1fb0000 { + compatible = "ns16550a"; + reg = <1 0x01fb0000 0x20>; + clock-frequency = <12288000>; + reg-shift = <1>; + interrupt-parent = <&gpio>; + }; +}; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts deleted file mode 100644 index 05408df38203..000000000000 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr1310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear1310.dtsi" - -/ { - model = "ST SPEAr1310 Evaluation Board"; - compatible = "st,spear1310-evb", "st,spear1310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@e0700000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - i2s0 { - st,pins = "i2s0_grp"; - st,function = "i2s0"; - }; - i2s1 { - st,pins = "i2s1_grp"; - st,function = "i2s1"; - }; - gpio { - st,pins = "arm_gpio_grp"; - st,function = "arm_gpio"; - }; - clcd { - st,pins = "clcd_grp" , "clcd_high_res"; - st,function = "clcd"; - }; - eth { - st,pins = "gmii_grp"; - st,function = "gmii"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - kbd { - st,pins = "keyboard_6x6_grp"; - st,function = "keyboard"; - }; - sdhci { - st,pins = "sdhci_grp"; - st,function = "sdhci"; - }; - smi-pmx { - st,pins = "smi_2_chips_grp"; - st,function = "smi"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - rs485 { - st,pins = "rs485_0_1_tdm_0_1_grp"; - st,function = "rs485_0_1_tdm_0_1"; - }; - i2c1_2 { - st,pins = "i2c_1_2_grp"; - st,function = "i2c_1_2"; - }; - smii { - st,pins = "smii_0_1_2_grp"; - st,function = "smii_0_1_2"; - }; - nand { - st,pins = "nand_8bit_grp", - "nand_16bit_grp"; - st,function = "nand"; - }; - sata { - st,pins = "sata0_grp"; - st,function = "sata"; - }; - pcie { - st,pins = "pcie1_grp", "pcie2_grp"; - st,function = "pci_express"; - }; - }; - }; - - ahci@b1000000 { - status = "okay"; - }; - - miphy@eb800000 { - status = "okay"; - }; - - cf@b2800000 { - status = "okay"; - }; - - dma@ea800000 { - status = "okay"; - }; - - dma@eb000000 { - status = "okay"; - }; - - fsmc: flash@b0000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x80000>; - }; - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x140000>; - }; - partition@1C0000 { - label = "environment"; - reg = <0x1C0000 0x40000>; - }; - partition@200000 { - label = "dtb"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "linux"; - reg = <0x240000 0xC00000>; - }; - partition@E40000 { - label = "rootfs"; - reg = <0xE40000 0x0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "wakeup"; - linux,code = <0x100>; - gpios = <&gpio0 7 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - gmac0: eth@e2000000 { - phy-mode = "gmii"; - status = "okay"; - }; - - sdhci@b3000000 { - status = "okay"; - }; - - smi: flash@ea000000 { - status = "okay"; - clock-rate = <50000000>; - - flash@e6000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xe6000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - ehci@e4800000 { - status = "okay"; - }; - - ehci@e5800000 { - status = "okay"; - }; - - ohci@e4000000 { - status = "okay"; - }; - - ohci@e5000000 { - status = "okay"; - }; - - apb { - adc@e0080000 { - status = "okay"; - }; - - gpio0: gpio@e0600000 { - status = "okay"; - }; - - gpio1: gpio@e0680000 { - status = "okay"; - }; - - gpio@d8400000 { - status = "okay"; - }; - - i2c0: i2c@e0280000 { - status = "okay"; - }; - - kbd@e0300000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - suspended_rate = <2000000>; - status = "okay"; - }; - - rtc@e0580000 { - status = "okay"; - }; - - serial@e0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - spi0: spi@e0100000 { - status = "okay"; - num-cs = <3>; - cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>; - - stmpe610@0 { - compatible = "st,stmpe610"; - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x7>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - interrupts = <6 0x4>; - interrupt-parent = <&gpio1>; - irq-trigger = <0x2>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <2>; - ts,settling = <2>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - - flash@1 { - compatible = "st,m25p80"; - reg = <1>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - }; - - wdt@ec800620 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi deleted file mode 100644 index 2f746a9428a7..000000000000 --- a/arch/arm/boot/dts/spear1310.dtsi +++ /dev/null @@ -1,307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr1310 SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear13xx.dtsi" - -/ { - compatible = "st,spear1310"; - - ahb { - spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x3b0>; - st-spics,sw-enable-bit = <12>; - st-spics,cs-value-bit = <11>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <8>; - gpio-controller; - #gpio-cells = <2>; - }; - - miphy0: miphy@eb800000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb800000 0x4000>; - misc = <&misc>; - phy-id = <0>; - #phy-cells = <1>; - status = "disabled"; - }; - - miphy1: miphy@eb804000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb804000 0x4000>; - misc = <&misc>; - phy-id = <1>; - #phy-cells = <1>; - status = "disabled"; - }; - - miphy2: miphy@eb808000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb808000 0x4000>; - misc = <&misc>; - phy-id = <2>; - #phy-cells = <1>; - status = "disabled"; - }; - - ahci0: ahci@b1000000 { - compatible = "snps,spear-ahci"; - reg = <0xb1000000 0x10000>; - interrupts = <0 68 0x4>; - phys = <&miphy0 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - ahci1: ahci@b1800000 { - compatible = "snps,spear-ahci"; - reg = <0xb1800000 0x10000>; - interrupts = <0 69 0x4>; - phys = <&miphy1 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - ahci2: ahci@b4000000 { - compatible = "snps,spear-ahci"; - reg = <0xb4000000 0x10000>; - interrupts = <0 70 0x4>; - phys = <&miphy2 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - pcie0: pcie@b1000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 68 0x4>; - num-lanes = <1>; - phys = <&miphy0 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - pcie1: pcie@b1800000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 69 0x4>; - num-lanes = <1>; - phys = <&miphy1 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - pcie2: pcie@b4000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 70 0x4>; - num-lanes = <1>; - phys = <&miphy2 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - gmac1: eth@5c400000 { - compatible = "st,spear600-gmac"; - reg = <0x5c400000 0x8000>; - interrupts = <0 95 0x4>; - interrupt-names = "macirq"; - phy-mode = "mii"; - status = "disabled"; - }; - - gmac2: eth@5c500000 { - compatible = "st,spear600-gmac"; - reg = <0x5c500000 0x8000>; - interrupts = <0 96 0x4>; - interrupt-names = "macirq"; - phy-mode = "mii"; - status = "disabled"; - }; - - gmac3: eth@5c600000 { - compatible = "st,spear600-gmac"; - reg = <0x5c600000 0x8000>; - interrupts = <0 97 0x4>; - interrupt-names = "macirq"; - phy-mode = "rmii"; - status = "disabled"; - }; - - gmac4: eth@5c700000 { - compatible = "st,spear600-gmac"; - reg = <0x5c700000 0x8000>; - interrupts = <0 98 0x4>; - interrupt-names = "macirq"; - phy-mode = "rgmii"; - status = "disabled"; - }; - - pinmux: pinmux@e0700000 { - compatible = "st,spear1310-pinmux"; - reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; - }; - - apb { - i2c1: i2c@5cd00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5cd00000 0x1000>; - interrupts = <0 87 0x4>; - status = "disabled"; - }; - - i2c2: i2c@5ce00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5ce00000 0x1000>; - interrupts = <0 88 0x4>; - status = "disabled"; - }; - - i2c3: i2c@5cf00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5cf00000 0x1000>; - interrupts = <0 89 0x4>; - status = "disabled"; - }; - - i2c4: i2c@5d000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d000000 0x1000>; - interrupts = <0 90 0x4>; - status = "disabled"; - }; - - i2c5: i2c@5d100000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d100000 0x1000>; - interrupts = <0 91 0x4>; - status = "disabled"; - }; - - i2c6: i2c@5d200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d200000 0x1000>; - interrupts = <0 92 0x4>; - status = "disabled"; - }; - - i2c7: i2c@5d300000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d300000 0x1000>; - interrupts = <0 93 0x4>; - status = "disabled"; - }; - - spi1: spi@5d400000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x5d400000 0x1000>; - interrupts = <0 99 0x4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - serial@5c800000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5c800000 0x1000>; - interrupts = <0 82 0x4>; - status = "disabled"; - }; - - serial@5c900000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5c900000 0x1000>; - interrupts = <0 83 0x4>; - status = "disabled"; - }; - - serial@5ca00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5ca00000 0x1000>; - interrupts = <0 84 0x4>; - status = "disabled"; - }; - - serial@5cb00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5cb00000 0x1000>; - interrupts = <0 85 0x4>; - status = "disabled"; - }; - - serial@5cc00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5cc00000 0x1000>; - interrupts = <0 86 0x4>; - status = "disabled"; - }; - - thermal@e07008c4 { - st,thermal-flags = <0x7000>; - }; - - gpiopinctrl: gpio@d8400000 { - compatible = "st,spear-plgpio"; - reg = <0xd8400000 0x1000>; - interrupts = <0 100 0x4>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 246>; - status = "disabled"; - - st-plgpio,ngpio = <246>; - st-plgpio,enb-reg = <0xd0>; - st-plgpio,wdata-reg = <0x90>; - st-plgpio,dir-reg = <0xb0>; - st-plgpio,ie-reg = <0x30>; - st-plgpio,rdata-reg = <0x70>; - st-plgpio,mis-reg = <0x10>; - st-plgpio,eit-reg = <0x50>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts deleted file mode 100644 index 7700f2afc128..000000000000 --- a/arch/arm/boot/dts/spear1340-evb.dts +++ /dev/null @@ -1,503 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr1340 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear1340.dtsi" - -/ { - model = "ST SPEAr1340 Evaluation Board"; - compatible = "st,spear1340-evb", "st,spear1340"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@e0700000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pads_as_gpio { - st,pins = "pads_as_gpio_grp"; - st,function = "pads_as_gpio"; - }; - fsmc { - st,pins = "fsmc_8bit_grp"; - st,function = "fsmc"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - i2c1 { - st,pins = "i2c1_grp"; - st,function = "i2c1"; - }; - spdif-in { - st,pins = "spdif_in_grp"; - st,function = "spdif_in"; - }; - spdif-out { - st,pins = "spdif_out_grp"; - st,function = "spdif_out"; - }; - ssp0 { - st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp"; - st,function = "ssp0"; - }; - smi-pmx { - st,pins = "smi_grp"; - st,function = "smi"; - }; - i2s { - st,pins = "i2s_in_grp", "i2s_out_grp"; - st,function = "i2s"; - }; - gmac { - st,pins = "gmii_grp", "rgmii_grp"; - st,function = "gmac"; - }; - cam0 { - st,pins = "cam0_grp"; - st,function = "cam0"; - }; - cam1 { - st,pins = "cam1_grp"; - st,function = "cam1"; - }; - cam2 { - st,pins = "cam2_grp"; - st,function = "cam2"; - }; - cam3 { - st,pins = "cam3_grp"; - st,function = "cam3"; - }; - cec0 { - st,pins = "cec0_grp"; - st,function = "cec0"; - }; - cec1 { - st,pins = "cec1_grp"; - st,function = "cec1"; - }; - sdhci { - st,pins = "sdhci_grp"; - st,function = "sdhci"; - }; - clcd { - st,pins = "clcd_grp"; - st,function = "clcd"; - }; - sata { - st,pins = "sata_grp"; - st,function = "sata"; - }; - pcie { - st,pins = "pcie_grp"; - st,function = "pcie"; - }; - - }; - }; - - ahci@b1000000 { - status = "okay"; - }; - - miphy@eb800000 { - status = "okay"; - }; - - dma@ea800000 { - status = "okay"; - }; - - dma@eb000000 { - status = "okay"; - }; - - fsmc: flash@b0000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "u-boot"; - reg = <0x200000 0x200000>; - }; - partition@400000 { - label = "environment"; - reg = <0x400000 0x100000>; - }; - partition@500000 { - label = "dtb"; - reg = <0x500000 0x100000>; - }; - partition@600000 { - label = "linux"; - reg = <0x600000 0xC00000>; - }; - partition@1200000 { - label = "rootfs"; - reg = <0x1200000 0x0>; - }; - }; - - gmac0: eth@e2000000 { - phy-mode = "rgmii"; - status = "okay"; - }; - - sdhci@b3000000 { - status = "okay"; - }; - - smi: flash@ea000000 { - status = "okay"; - clock-rate = <50000000>; - - flash@e6000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xe6000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - ehci@e4800000 { - status = "okay"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "wakeup"; - linux,code = <0x100>; - gpios = <&gpio1 1 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - ehci@e5800000 { - status = "okay"; - }; - - i2s0: i2s-play@b2400000 { - status = "okay"; - }; - - i2s1: i2s-rec@b2000000 { - status = "okay"; - }; - - incodec: dir-hifi { - compatible = "dummy,dir-hifi"; - status = "okay"; - }; - - ohci@e4000000 { - status = "okay"; - }; - - ohci@e5000000 { - status = "okay"; - }; - - outcodec: dit-hifi { - compatible = "dummy,dit-hifi"; - status = "okay"; - }; - - sound { - compatible = "spear,spear-evb"; - audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>; - audio-codecs = <&incodec &outcodec &sta529 &sta529>; - codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio"; - stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap"; - dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm"; - nr_controllers = <4>; - status = "okay"; - }; - - spdif0: spdif-in@d0100000 { - status = "okay"; - }; - - spdif1: spdif-out@d0000000 { - status = "okay"; - }; - - apb { - adc@e0080000 { - status = "okay"; - }; - - i2s-play@b2400000 { - status = "okay"; - }; - - i2s-rec@b2000000 { - status = "okay"; - }; - - gpio0: gpio@e0600000 { - status = "okay"; - }; - - gpio1: gpio@e0680000 { - status = "okay"; - }; - - gpio@e2800000 { - status = "okay"; - }; - - i2c0: i2c@e0280000 { - status = "okay"; - - sta529: sta529@1a { - compatible = "st,sta529"; - reg = <0x1a>; - }; - }; - - i2c1: i2c@b4000000 { - status = "okay"; - - eeprom0@56 { - compatible = "st,eeprom"; - reg = <0x56>; - }; - - stmpe801@41 { - compatible = "st,stmpe801"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - interrupts = <4 0x4>; - interrupt-parent = <&gpio0>; - irq-trigger = <0x2>; - - stmpegpio: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - kbd@e0300000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - suspended_rate = <2000000>; - status = "okay"; - }; - - rtc@e0580000 { - status = "okay"; - }; - - serial@e0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b4100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - spi0: spi@e0100000 { - status = "okay"; - num-cs = <3>; - cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>, - <&gpiopinctrl 85 0>; - - flash@0 { - compatible = "m25p80"; - reg = <0>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - - stmpe610@1 { - compatible = "st,stmpe610"; - spi-max-frequency = <1000000>; - spi-cpha; - reg = <1>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x7>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - interrupts = <100 0>; - interrupt-parent = <&gpiopinctrl>; - irq-trigger = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <2>; - ts,settling = <2>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - }; - - timer@ec800600 { - status = "okay"; - }; - - wdt@ec800620 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi deleted file mode 100644 index 818886e11713..000000000000 --- a/arch/arm/boot/dts/spear1340.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr1340 SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear13xx.dtsi" - -/ { - compatible = "st,spear1340"; - - ahb { - - spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x42c>; - st-spics,sw-enable-bit = <21>; - st-spics,cs-value-bit = <20>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <18>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - miphy0: miphy@eb800000 { - compatible = "st,spear1340-miphy"; - reg = <0xeb800000 0x4000>; - misc = <&misc>; - #phy-cells = <1>; - status = "disabled"; - }; - - ahci0: ahci@b1000000 { - compatible = "snps,spear-ahci"; - reg = <0xb1000000 0x10000>; - interrupts = <0 72 0x4>; - phys = <&miphy0 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - pcie0: pcie@b1000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 68 0x4>; - num-lanes = <1>; - phys = <&miphy0 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - i2s-play@b2400000 { - compatible = "snps,designware-i2s"; - reg = <0xb2400000 0x10000>; - interrupt-names = "play_irq"; - interrupts = <0 98 0x4 - 0 99 0x4>; - play; - channel = <8>; - status = "disabled"; - }; - - i2s-rec@b2000000 { - compatible = "snps,designware-i2s"; - reg = <0xb2000000 0x10000>; - interrupt-names = "record_irq"; - interrupts = <0 100 0x4 - 0 101 0x4>; - record; - channel = <8>; - status = "disabled"; - }; - - pinmux: pinmux@e0700000 { - compatible = "st,spear1340-pinmux"; - reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; - }; - - pwm: pwm@e0180000 { - compatible = "st,spear13xx-pwm"; - reg = <0xe0180000 0x1000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - spdif-in@d0100000 { - compatible = "st,spdif-in"; - reg = < 0xd0100000 0x20000 - 0xd0110000 0x10000 >; - interrupts = <0 84 0x4>; - status = "disabled"; - }; - - spdif-out@d0000000 { - compatible = "st,spdif-out"; - reg = <0xd0000000 0x20000>; - interrupts = <0 85 0x4>; - status = "disabled"; - }; - - spi1: spi@5d400000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x5d400000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 99 0x4>; - status = "disabled"; - }; - - apb { - i2c1: i2c@b4000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xb4000000 0x1000>; - interrupts = <0 104 0x4>; - write-16bit; - status = "disabled"; - }; - - serial@b4100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb4100000 0x1000>; - interrupts = <0 105 0x4>; - status = "disabled"; - dmas = <&dwdma0 13 0 1>, - <&dwdma0 12 1 0>; - dma-names = "rx", "tx"; - }; - - thermal@e07008c4 { - st,thermal-flags = <0x2a00>; - }; - - gpiopinctrl: gpio@e2800000 { - compatible = "st,spear-plgpio"; - reg = <0xe2800000 0x1000>; - interrupts = <0 107 0x4>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 252>; - status = "disabled"; - - st-plgpio,ngpio = <250>; - st-plgpio,wdata-reg = <0x40>; - st-plgpio,dir-reg = <0x00>; - st-plgpio,ie-reg = <0x80>; - st-plgpio,rdata-reg = <0x20>; - st-plgpio,mis-reg = <0xa0>; - st-plgpio,eit-reg = <0x60>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi deleted file mode 100644 index 913553367687..000000000000 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ /dev/null @@ -1,339 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr13xx SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - gic: interrupt-controller@ec801000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0xec801000 0x1000 >, - < 0xec800100 0x0100 >; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 6 0x04 - 0 7 0x04>; - }; - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xed000000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAMA0,115200"; - }; - - cpufreq { - compatible = "st,cpufreq-spear"; - cpufreq_tbl = < 166000 - 200000 - 250000 - 300000 - 400000 - 500000 - 600000 >; - status = "disabled"; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x50000000 0x50000000 0x10000000 - 0x80000000 0x80000000 0x20000000 - 0xb0000000 0xb0000000 0x22000000 - 0xd8000000 0xd8000000 0x01000000 - 0xe0000000 0xe0000000 0x10000000>; - - sdhci@b3000000 { - compatible = "st,sdhci-spear"; - reg = <0xb3000000 0x100>; - interrupts = <0 28 0x4>; - status = "disabled"; - }; - - cf@b2800000 { - compatible = "arasan,cf-spear1340"; - reg = <0xb2800000 0x1000>; - interrupts = <0 29 0x4>; - status = "disabled"; - dmas = <&dwdma0 0 0 0>; - dma-names = "data"; - }; - - dwdma0: dma@ea800000 { - compatible = "snps,dma-spear1340"; - reg = <0xea800000 0x1000>; - interrupts = <0 19 0x4>; - status = "disabled"; - - dma-channels = <8>; - #dma-cells = <3>; - dma-requests = <32>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - dma-masters = <2>; - data-width = <8 8>; - multi-block = <1 1 1 1 1 1 1 1>; - }; - - dma@eb000000 { - compatible = "snps,dma-spear1340"; - reg = <0xeb000000 0x1000>; - interrupts = <0 59 0x4>; - status = "disabled"; - - dma-requests = <32>; - dma-channels = <8>; - dma-masters = <2>; - #dma-cells = <3>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - data-width = <8 8>; - multi-block = <1 1 1 1 1 1 1 1>; - }; - - fsmc: flash@b0000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xb0000000 0x1000 /* FSMC Register*/ - 0xb0800000 0x0010 /* NAND Base DATA */ - 0xb0820000 0x0010 /* NAND Base ADDR */ - 0xb0810000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - interrupts = <0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4>; - st,mode = <2>; - status = "disabled"; - }; - - gmac0: eth@e2000000 { - compatible = "st,spear600-gmac"; - reg = <0xe2000000 0x8000>; - interrupts = <0 33 0x4 - 0 34 0x4>; - interrupt-names = "macirq", "eth_wake_irq"; - status = "disabled"; - }; - - pcm { - compatible = "st,pcm-audio"; - #address-cells = <0>; - #size-cells = <0>; - status = "disabled"; - }; - - smi: flash@ea000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xea000000 0x1000>; - interrupts = <0 30 0x4>; - status = "disabled"; - }; - - ehci@e4800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe4800000 0x1000>; - interrupts = <0 64 0x4>; - usbh0_id = <0>; - status = "disabled"; - }; - - ehci@e5800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe5800000 0x1000>; - interrupts = <0 66 0x4>; - usbh1_id = <1>; - status = "disabled"; - }; - - ohci@e4000000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe4000000 0x1000>; - interrupts = <0 65 0x4>; - usbh0_id = <0>; - status = "disabled"; - }; - - ohci@e5000000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe5000000 0x1000>; - interrupts = <0 67 0x4>; - usbh1_id = <1>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 - 0xd8000000 0xd8000000 0x01000000 - 0xe0000000 0xe0000000 0x10000000>; - - misc: syscon@e0700000 { - compatible = "st,spear1340-misc", "syscon"; - reg = <0xe0700000 0x1000>; - }; - - gpio0: gpio@e0600000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xe0600000 0x1000>; - interrupts = <0 24 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@e0680000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xe0680000 0x1000>; - interrupts = <0 25 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - kbd@e0300000 { - compatible = "st,spear300-kbd"; - reg = <0xe0300000 0x1000>; - interrupts = <0 52 0x4>; - status = "disabled"; - }; - - i2c0: i2c@e0280000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xe0280000 0x1000>; - interrupts = <0 41 0x4>; - status = "disabled"; - }; - - i2s@e0180000 { - compatible = "st,designware-i2s"; - reg = <0xe0180000 0x1000>; - interrupt-names = "play_irq", "record_irq"; - interrupts = <0 10 0x4 - 0 11 0x4 >; - status = "disabled"; - }; - - i2s@e0200000 { - compatible = "st,designware-i2s"; - reg = <0xe0200000 0x1000>; - interrupt-names = "play_irq", "record_irq"; - interrupts = <0 26 0x4 - 0 53 0x4>; - status = "disabled"; - }; - - spi0: spi@e0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xe0100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 31 0x4>; - status = "disabled"; - dmas = <&dwdma0 5 0 0>, - <&dwdma0 4 0 0>; - dma-names = "rx", "tx"; - }; - - rtc@e0580000 { - compatible = "st,spear600-rtc"; - reg = <0xe0580000 0x1000>; - interrupts = <0 36 0x4>; - status = "disabled"; - }; - - serial@e0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xe0000000 0x1000>; - interrupts = <0 35 0x4>; - status = "disabled"; - }; - - adc@e0080000 { - compatible = "st,spear600-adc"; - reg = <0xe0080000 0x1000>; - interrupts = <0 12 0x4>; - status = "disabled"; - }; - - timer@e0380000 { - compatible = "st,spear-timer"; - reg = <0xe0380000 0x400>; - interrupts = <0 37 0x4>; - }; - - timer@ec800600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xec800600 0x20>; - interrupts = <1 13 0x4>; - status = "disabled"; - }; - - wdt@ec800620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xec800620 0x20>; - status = "disabled"; - }; - - thermal@e07008c4 { - compatible = "st,thermal-spear1340"; - reg = <0xe07008c4 0x4>; - thermal_flags = <0x7000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts deleted file mode 100644 index 303ef29fb805..000000000000 --- a/arch/arm/boot/dts/spear300-evb.dts +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr300 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear300.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@99000000 { - st,pinmux-mode = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_pfmode_grp"; - st,function = "clcd"; - }; - sdhci { - st,pins = "sdhci_4bit_grp"; - st,function = "sdhci"; - }; - gpio1 { - st,pins = "gpio1_4_to_7_grp", - "gpio1_0_to_3_grp"; - st,function = "gpio1"; - }; - }; - }; - - clcd@60000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@94000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - cd-gpios = <&gpio1 0 0>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate = <50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio1: gpio@a9000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - kbd@a0000000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi deleted file mode 100644 index f1135e887f7b..000000000000 --- a/arch/arm/boot/dts/spear300.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr300 SoC - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x60000000 0x60000000 0x50000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux@99000000 { - compatible = "st,spear300-pinmux"; - reg = <0x99000000 0x1000>; - }; - - clcd@60000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x60000000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - fsmc: flash@94000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x94000000 0x1000 /* FSMC Register */ - 0x80000000 0x0010 /* NAND Base DATA */ - 0x80020000 0x0010 /* NAND Base ADDR */ - 0x80010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <1>; - status = "disabled"; - }; - - shirq: interrupt-controller@50000000 { - compatible = "st,spear300-shirq"; - reg = <0x50000000 0x1000>; - interrupts = <28>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - gpio1: gpio@a9000000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xa9000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - kbd@a0000000 { - compatible = "st,spear300-kbd"; - reg = <0xa0000000 0x1000>; - interrupts = <7>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts deleted file mode 100644 index ea0b53036f7b..000000000000 --- a/arch/arm/boot/dts/spear310-evb.dts +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear310.dtsi" - -/ { - model = "ST SPEAr310 Evaluation Board"; - compatible = "st,spear310-evb", "st,spear310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b4000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - gpio0 { - st,pins = "gpio0_pin0_grp", - "gpio0_pin1_grp", - "gpio0_pin2_grp", - "gpio0_pin3_grp", - "gpio0_pin4_grp", - "gpio0_pin5_grp"; - st,function = "gpio0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - emi { - st,pins = "emi_cs_0_to_5_grp"; - st,function = "emi"; - }; - fsmc { - st,pins = "fsmc_grp"; - st,function = "fsmc"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - uart3 { - st,pins = "uart3_grp"; - st,function = "uart3"; - }; - uart4 { - st,pins = "uart4_grp"; - st,function = "uart4"; - }; - uart5 { - st,pins = "uart5_grp"; - st,function = "uart5"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@44000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate = <50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2080000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2180000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2200000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi deleted file mode 100644 index ce08d8820940..000000000000 --- a/arch/arm/boot/dts/spear310.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr310 SoC - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux: pinmux@b4000000 { - compatible = "st,spear310-pinmux"; - reg = <0xb4000000 0x1000>; - #gpio-range-cells = <3>; - }; - - fsmc: flash@44000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x44000000 0x1000 /* FSMC Register */ - 0x40000000 0x0010 /* NAND Base DATA */ - 0x40020000 0x0010 /* NAND Base ADDR */ - 0x40010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - shirq: interrupt-controller@b4000000 { - compatible = "st,spear310-shirq"; - reg = <0xb4000000 0x1000>; - interrupts = <28 29 30 1>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - serial@b2000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2080000 0x1000>; - interrupts = <9>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2100000 0x1000>; - interrupts = <10>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2180000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2180000 0x1000>; - interrupts = <11>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2200000 0x1000>; - interrupts = <12>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - gpiopinctrl: gpio@b4000000 { - compatible = "st,spear-plgpio"; - reg = <0xb4000000 0x1000>; - regmap = <&pinmux>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; - status = "disabled"; - - st-plgpio,ngpio = <102>; - st-plgpio,enb-reg = <0x10>; - st-plgpio,wdata-reg = <0x20>; - st-plgpio,dir-reg = <0x30>; - st-plgpio,ie-reg = <0x50>; - st-plgpio,rdata-reg = <0x40>; - st-plgpio,mis-reg = <0x60>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts deleted file mode 100644 index 3c026d021c92..000000000000 --- a/arch/arm/boot/dts/spear320-evb.dts +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr320 Evaluation Board"; - compatible = "st,spear320-evb", "st,spear320"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - sdhci { - st,pins = "sdhci_cd_51_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii2 { - st,pins = "mii2_grp"; - st,function = "mii2"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_37_38_grp"; - st,function = "pwm0_1"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpiopinctrl 61 1>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate = <50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio@b3000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a3000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a4000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts deleted file mode 100644 index 721e5ee7b680..000000000000 --- a/arch/arm/boot/dts/spear320-hmi.dts +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Shiraz Hashim - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr320 HMI Board"; - compatible = "st,spear320-hmi", "st,spear320"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_grp"; - st,function = "clcd"; - }; - fsmc { - st,pins = "fsmc_8bit_grp"; - st,function = "fsmc"; - }; - sdhci { - st,pins = "sdhci_cd_12_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii0_1 { - st,pins = "rmii0_1_grp"; - st,function = "mii0_1"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_37_38_grp"; - st,function = "pwm0_1"; - }; - pwm2 { - st,pins = "pwm2_pin_34_grp"; - st,function = "pwm2"; - }; - }; - }; - - clcd@90000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x80000>; - }; - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x140000>; - }; - partition@1C0000 { - label = "environment"; - reg = <0x1C0000 0x40000>; - }; - partition@200000 { - label = "dtb"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "linux"; - reg = <0x240000 0xC00000>; - }; - partition@E40000 { - label = "rootfs"; - reg = <0xE40000 0x0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "user button 1"; - linux,code = <0x100>; - gpios = <&stmpegpio 3 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - - button@2 { - label = "user button 2"; - linux,code = <0x200>; - gpios = <&stmpegpio 2 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - pwm: pwm@a8000000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpiopinctrl 50 1>; - power_always_enb; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate = <50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - usbd@e1100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio@b3000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - - stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - irq-gpios = <&gpiopinctrl 29 0x4>; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - - stmpegpio: stmpe-gpio { - compatible = "st,stmpe-gpio"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - gpio,norequest-mask = <0xF3>; - }; - - stmpe610-ts { - compatible = "stmpe,ts"; - reg = <0>; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <3>; - ts,settling = <4>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a3000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a4000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi deleted file mode 100644 index 56f141297ea3..000000000000 --- a/arch/arm/boot/dts/spear320.dtsi +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320 SoC - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x80000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux: pinmux@b3000000 { - compatible = "st,spear320-pinmux"; - reg = <0xb3000000 0x1000>; - #gpio-range-cells = <3>; - }; - - clcd@90000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x90000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - fsmc: flash@4c000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4c000000 0x1000 /* FSMC Register */ - 0x50000000 0x0010 /* NAND Base DATA */ - 0x50020000 0x0010 /* NAND Base ADDR */ - 0x50010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <10>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - shirq: interrupt-controller@b3000000 { - compatible = "st,spear320-shirq"; - reg = <0xb3000000 0x1000>; - interrupts = <30 28 29 1>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - spi1: spi@a5000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa5000000 0x1000>; - interrupts = <15>; - interrupt-parent = <&shirq>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@a6000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa6000000 0x1000>; - interrupts = <16>; - interrupt-parent = <&shirq>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@a8000000 { - compatible = "st,spear-pwm"; - reg = <0xa8000000 0x1000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x20000000 - 0xd0000000 0xd0000000 0x30000000>; - - i2c1: i2c@a7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xa7000000 0x1000>; - interrupts = <21>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@a3000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa3000000 0x1000>; - interrupts = <13>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@a4000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa4000000 0x1000>; - interrupts = <14>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - gpiopinctrl: gpio@b3000000 { - compatible = "st,spear-plgpio"; - reg = <0xb3000000 0x1000>; - regmap = <&pinmux>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; - status = "disabled"; - - st-plgpio,ngpio = <102>; - st-plgpio,enb-reg = <0x24>; - st-plgpio,wdata-reg = <0x34>; - st-plgpio,dir-reg = <0x44>; - st-plgpio,ie-reg = <0x64>; - st-plgpio,rdata-reg = <0x54>; - st-plgpio,mis-reg = <0x84>; - st-plgpio,eit-reg = <0x94>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/spear320s.dtsi deleted file mode 100644 index 133236dc190d..000000000000 --- a/arch/arm/boot/dts/spear320s.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320s SoC - * - * Copyright 2021 Herve Codina - */ - -/include/ "spear320.dtsi" - -/ { - ahb { - apb { - gpiopinctrl: gpio@b3000000 { - /* - * The "RM0321 SPEAr320s address and map - * registers" document mentions interrupt 6 - * (NPGIO_INTR) for the PL_GPIO interrupt. - */ - interrupts = <6>; - interrupt-parent = <&shirq>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi deleted file mode 100644 index cc88ebe7a60c..000000000000 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr3xx SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <8>; - status = "disabled"; - }; - - gmac: eth@e0800000 { - compatible = "snps,dwmac-3.40a"; - reg = <0xe0800000 0x8000>; - interrupts = <23 22>; - interrupt-names = "macirq", "eth_wake_irq"; - phy-mode = "mii"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - spi0: spi@d0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0100000 0x1000>; - interrupts = <20>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupts = <26>; - status = "disabled"; - }; - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupts = <25>; - status = "disabled"; - }; - - ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupts = <27>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - gpio0: gpio@fc980000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xfc980000 0x1000>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - i2c0: i2c@d0180000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0180000 0x1000>; - interrupts = <21>; - status = "disabled"; - }; - - rtc@fc900000 { - compatible = "st,spear600-rtc"; - reg = <0xfc900000 0x1000>; - interrupts = <10>; - status = "disabled"; - }; - - serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupts = <19>; - status = "disabled"; - }; - - wdt@fc880000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0xfc880000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts deleted file mode 100644 index a25b86d149ad..000000000000 --- a/arch/arm/boot/dts/spear600-evb.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Stefan Roese - */ - -/dts-v1/; -/include/ "spear600.dtsi" - -/ { - model = "ST SPEAr600 Evaluation Board"; - compatible = "st,spear600-evb", "st,spear600"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0 0x10000000>; - }; -}; - -&clcd { - status = "okay"; -}; - -&dmac { - status = "okay"; -}; - -&ehci_usb0 { - status = "okay"; -}; - -&ehci_usb1 { - status = "okay"; -}; - -&gmac { - phy-mode = "gmii"; - status = "okay"; -}; - -&ohci_usb0 { - status = "okay"; -}; - -&ohci_usb1 { - status = "okay"; -}; - -&smi { - status = "okay"; - clock-rate = <50000000>; - - flash@f8000000 { - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&i2c { - clock-frequency = <400000>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi deleted file mode 100644 index 6b67c0ceaed9..000000000000 --- a/arch/arm/boot/dts/spear600.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Stefan Roese - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,spear600"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic0: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@f1000000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1000000 0x1000>; - #interrupt-cells = <1>; - }; - - clcd: clcd@fc200000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0xfc200000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <13>; - status = "disabled"; - }; - - dmac: dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - status = "disabled"; - }; - - gmac: ethernet@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupt-parent = <&vic1>; - interrupts = <24 23>; - interrupt-names = "macirq", "eth_wake_irq"; - phy-mode = "gmii"; - status = "disabled"; - }; - - fsmc: flash@d1800000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd1800000 0x1000 /* FSMC Register */ - 0xd2000000 0x0010 /* NAND Base DATA */ - 0xd2020000 0x0010 /* NAND Base ADDR */ - 0xd2010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - status = "disabled"; - }; - - ehci_usb0: ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - status = "disabled"; - }; - - ehci_usb1: ehci@e2000000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe2000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <29>; - status = "disabled"; - }; - - ohci_usb0: ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - status = "disabled"; - }; - - ohci_usb1: ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <28>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - uart0: serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - status = "disabled"; - }; - - uart1: serial@d0080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0080000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <25>; - status = "disabled"; - }; - - /* local/cpu GPIO */ - gpio0: gpio@f0100000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xf0100000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <18>; - }; - - /* basic GPIO */ - gpio1: gpio@fc980000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfc980000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <19>; - }; - - /* appl GPIO */ - gpio2: gpio@d8100000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xd8100000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <4>; - }; - - i2c: i2c@d0200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <28>; - status = "disabled"; - }; - - rtc: rtc@fc900000 { - compatible = "st,spear600-rtc"; - reg = <0xfc900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - status = "disabled"; - }; - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupt-parent = <&vic0>; - interrupts = <16>; - }; - - adc: adc@d820b000 { - compatible = "st,spear600-adc"; - reg = <0xd820b000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <6>; - status = "disabled"; - }; - - ssp1: spi@d0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&vic0>; - interrupts = <26>; - status = "disabled"; - }; - - ssp2: spi@d0180000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0180000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&vic0>; - interrupts = <27>; - status = "disabled"; - }; - - ssp3: spi@d8180000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd8180000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&vic1>; - interrupts = <5>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h deleted file mode 100644 index d80551202292..000000000000 --- a/arch/arm/boot/dts/st-pincfg.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ST_PINCFG_H_ -#define _ST_PINCFG_H_ - -/* Alternate functions */ -#define ALT1 1 -#define ALT2 2 -#define ALT3 3 -#define ALT4 4 -#define ALT5 5 -#define ALT6 6 -#define ALT7 7 - -/* Output enable */ -#define OE (1 << 27) -/* Pull Up */ -#define PU (1 << 26) -/* Open Drain */ -#define OD (1 << 25) -#define RT (1 << 23) -#define INVERTCLK (1 << 22) -#define CLKNOTDATA (1 << 21) -#define DOUBLE_EDGE (1 << 20) -#define CLK_A (0 << 18) -#define CLK_B (1 << 18) -#define CLK_C (2 << 18) -#define CLK_D (3 << 18) - -/* User-frendly defines for Pin Direction */ - /* oe = 0, pu = 0, od = 0 */ -#define IN (0) - /* oe = 0, pu = 1, od = 0 */ -#define IN_PU (PU) - /* oe = 1, pu = 0, od = 0 */ -#define OUT (OE) - /* oe = 1, pu = 0, od = 1 */ -#define BIDIR (OE | OD) - /* oe = 1, pu = 1, od = 1 */ -#define BIDIR_PU (OE | PU | OD) - -/* RETIME_TYPE */ -/* - * B Mode - * Bypass retime with optional delay parameter - */ -#define BYPASS (0) -/* - * R0, R1, R0D, R1D modes - * single-edge data non inverted clock, retime data with clk - */ -#define SE_NICLK_IO (RT) -/* - * RIV0, RIV1, RIV0D, RIV1D modes - * single-edge data inverted clock, retime data with clk - */ -#define SE_ICLK_IO (RT | INVERTCLK) -/* - * R0E, R1E, R0ED, R1ED modes - * double-edge data, retime data with clk - */ -#define DE_IO (RT | DOUBLE_EDGE) -/* - * CIV0, CIV1 modes with inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define ICLK (RT | CLKNOTDATA | INVERTCLK) -/* - * CLK0, CLK1 modes with non-inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define NICLK (RT | CLKNOTDATA) -#endif /* _ST_PINCFG_H_ */ diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile new file mode 100644 index 000000000000..b3e9d29390e3 --- /dev/null +++ b/arch/arm/boot/dts/st/Makefile @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NOMADIK) += \ + ste-nomadik-s8815.dtb \ + ste-nomadik-nhk15.dtb +dtb-$(CONFIG_ARCH_SPEAR13XX) += \ + spear1310-evb.dtb \ + spear1340-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR3XX) += \ + spear300-evb.dtb \ + spear310-evb.dtb \ + spear320-evb.dtb \ + spear320-hmi.dtb +dtb-$(CONFIG_ARCH_SPEAR6XX) += \ + spear600-evb.dtb +dtb-$(CONFIG_ARCH_STI) += \ + stih407-b2120.dtb \ + stih410-b2120.dtb \ + stih410-b2260.dtb \ + stih418-b2199.dtb \ + stih418-b2264.dtb +dtb-$(CONFIG_ARCH_STM32) += \ + stm32f429-disco.dtb \ + stm32f469-disco.dtb \ + stm32f746-disco.dtb \ + stm32f769-disco.dtb \ + stm32429i-eval.dtb \ + stm32746g-eval.dtb \ + stm32h743i-eval.dtb \ + stm32h743i-disco.dtb \ + stm32h750i-art-pi.dtb \ + stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ + stm32mp151a-dhcor-testbench.dtb \ + stm32mp153c-dhcom-drc02.dtb \ + stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp157a-avenger96.dtb \ + stm32mp157a-dhcor-avenger96.dtb \ + stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ + stm32mp157a-iot-box.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ + stm32mp157a-stinger96.dtb \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp157c-dhcom-picoitx.dtb \ + stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ + stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ + stm32mp157c-emsbc-argon.dtb \ + stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp157c-phycore-stm32mp1-3.dtb +dtb-$(CONFIG_ARCH_U8500) += \ + ste-snowball.dtb \ + ste-hrefprev60-stuib.dtb \ + ste-hrefprev60-tvk.dtb \ + ste-hrefv60plus-stuib.dtb \ + ste-hrefv60plus-tvk.dtb \ + ste-href520-tvk.dtb \ + ste-ux500-samsung-golden.dtb \ + ste-ux500-samsung-janice.dtb \ + ste-ux500-samsung-gavini.dtb \ + ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ + ste-ux500-samsung-skomer.dtb \ + ste-ux500-samsung-kyle.dtb diff --git a/arch/arm/boot/dts/st/spear1310-evb.dts b/arch/arm/boot/dts/st/spear1310-evb.dts new file mode 100644 index 000000000000..05408df38203 --- /dev/null +++ b/arch/arm/boot/dts/st/spear1310-evb.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr1310 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + */ + +/dts-v1/; +/include/ "spear1310.dtsi" + +/ { + model = "ST SPEAr1310 Evaluation Board"; + compatible = "st,spear1310-evb", "st,spear1310"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@e0700000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + i2s0 { + st,pins = "i2s0_grp"; + st,function = "i2s0"; + }; + i2s1 { + st,pins = "i2s1_grp"; + st,function = "i2s1"; + }; + gpio { + st,pins = "arm_gpio_grp"; + st,function = "arm_gpio"; + }; + clcd { + st,pins = "clcd_grp" , "clcd_high_res"; + st,function = "clcd"; + }; + eth { + st,pins = "gmii_grp"; + st,function = "gmii"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + kbd { + st,pins = "keyboard_6x6_grp"; + st,function = "keyboard"; + }; + sdhci { + st,pins = "sdhci_grp"; + st,function = "sdhci"; + }; + smi-pmx { + st,pins = "smi_2_chips_grp"; + st,function = "smi"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + rs485 { + st,pins = "rs485_0_1_tdm_0_1_grp"; + st,function = "rs485_0_1_tdm_0_1"; + }; + i2c1_2 { + st,pins = "i2c_1_2_grp"; + st,function = "i2c_1_2"; + }; + smii { + st,pins = "smii_0_1_2_grp"; + st,function = "smii_0_1_2"; + }; + nand { + st,pins = "nand_8bit_grp", + "nand_16bit_grp"; + st,function = "nand"; + }; + sata { + st,pins = "sata0_grp"; + st,function = "sata"; + }; + pcie { + st,pins = "pcie1_grp", "pcie2_grp"; + st,function = "pci_express"; + }; + }; + }; + + ahci@b1000000 { + status = "okay"; + }; + + miphy@eb800000 { + status = "okay"; + }; + + cf@b2800000 { + status = "okay"; + }; + + dma@ea800000 { + status = "okay"; + }; + + dma@eb000000 { + status = "okay"; + }; + + fsmc: flash@b0000000 { + status = "okay"; + + partition@0 { + label = "xloader"; + reg = <0x0 0x80000>; + }; + partition@80000 { + label = "u-boot"; + reg = <0x80000 0x140000>; + }; + partition@1C0000 { + label = "environment"; + reg = <0x1C0000 0x40000>; + }; + partition@200000 { + label = "dtb"; + reg = <0x200000 0x40000>; + }; + partition@240000 { + label = "linux"; + reg = <0x240000 0xC00000>; + }; + partition@E40000 { + label = "rootfs"; + reg = <0xE40000 0x0>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "wakeup"; + linux,code = <0x100>; + gpios = <&gpio0 7 0x4>; + debounce-interval = <20>; + wakeup-source; + }; + }; + + gmac0: eth@e2000000 { + phy-mode = "gmii"; + status = "okay"; + }; + + sdhci@b3000000 { + status = "okay"; + }; + + smi: flash@ea000000 { + status = "okay"; + clock-rate = <50000000>; + + flash@e6000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe6000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; + + ehci@e4800000 { + status = "okay"; + }; + + ehci@e5800000 { + status = "okay"; + }; + + ohci@e4000000 { + status = "okay"; + }; + + ohci@e5000000 { + status = "okay"; + }; + + apb { + adc@e0080000 { + status = "okay"; + }; + + gpio0: gpio@e0600000 { + status = "okay"; + }; + + gpio1: gpio@e0680000 { + status = "okay"; + }; + + gpio@d8400000 { + status = "okay"; + }; + + i2c0: i2c@e0280000 { + status = "okay"; + }; + + kbd@e0300000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + suspended_rate = <2000000>; + status = "okay"; + }; + + rtc@e0580000 { + status = "okay"; + }; + + serial@e0000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + spi0: spi@e0100000 { + status = "okay"; + num-cs = <3>; + cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>; + + stmpe610@0 { + compatible = "st,stmpe610"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable; + pl022,com-mode = <0>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x7>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + interrupts = <6 0x4>; + interrupt-parent = <&gpio1>; + irq-trigger = <0x2>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + ts,sample-time = <4>; + ts,mod-12b = <1>; + ts,ref-sel = <0>; + ts,adc-freq = <1>; + ts,ave-ctrl = <1>; + ts,touch-det-delay = <2>; + ts,settling = <2>; + ts,fraction-z = <7>; + ts,i-drive = <1>; + }; + }; + + flash@1 { + compatible = "st,m25p80"; + reg = <1>; + spi-max-frequency = <12000000>; + spi-cpol; + spi-cpha; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable; + pl022,com-mode = <0x2>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; + }; + + wdt@ec800620 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear1310.dtsi b/arch/arm/boot/dts/st/spear1310.dtsi new file mode 100644 index 000000000000..2f746a9428a7 --- /dev/null +++ b/arch/arm/boot/dts/st/spear1310.dtsi @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for all SPEAr1310 SoCs + * + * Copyright 2012 Viresh Kumar + */ + +/include/ "spear13xx.dtsi" + +/ { + compatible = "st,spear1310"; + + ahb { + spics: spics@e0700000{ + compatible = "st,spear-spics-gpio"; + reg = <0xe0700000 0x1000>; + st-spics,peripcfg-reg = <0x3b0>; + st-spics,sw-enable-bit = <12>; + st-spics,cs-value-bit = <11>; + st-spics,cs-enable-mask = <3>; + st-spics,cs-enable-shift = <8>; + gpio-controller; + #gpio-cells = <2>; + }; + + miphy0: miphy@eb800000 { + compatible = "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy@eb804000 { + compatible = "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy@eb808000 { + compatible = "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { + compatible = "snps,spear-ahci"; + reg = <0xb1000000 0x10000>; + interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + ahci1: ahci@b1800000 { + compatible = "snps,spear-ahci"; + reg = <0xb1800000 0x10000>; + interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + ahci2: ahci@b4000000 { + compatible = "snps,spear-ahci"; + reg = <0xb4000000 0x10000>; + interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; + reg-names = "dbi", "config"; + interrupts = <0 68 0x4>; + num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; + status = "disabled"; + }; + + pcie1: pcie@b1800000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; + reg-names = "dbi", "config"; + interrupts = <0 69 0x4>; + num-lanes = <1>; + phys = <&miphy1 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; + status = "disabled"; + }; + + pcie2: pcie@b4000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; + reg-names = "dbi", "config"; + interrupts = <0 70 0x4>; + num-lanes = <1>; + phys = <&miphy2 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; + status = "disabled"; + }; + + gmac1: eth@5c400000 { + compatible = "st,spear600-gmac"; + reg = <0x5c400000 0x8000>; + interrupts = <0 95 0x4>; + interrupt-names = "macirq"; + phy-mode = "mii"; + status = "disabled"; + }; + + gmac2: eth@5c500000 { + compatible = "st,spear600-gmac"; + reg = <0x5c500000 0x8000>; + interrupts = <0 96 0x4>; + interrupt-names = "macirq"; + phy-mode = "mii"; + status = "disabled"; + }; + + gmac3: eth@5c600000 { + compatible = "st,spear600-gmac"; + reg = <0x5c600000 0x8000>; + interrupts = <0 97 0x4>; + interrupt-names = "macirq"; + phy-mode = "rmii"; + status = "disabled"; + }; + + gmac4: eth@5c700000 { + compatible = "st,spear600-gmac"; + reg = <0x5c700000 0x8000>; + interrupts = <0 98 0x4>; + interrupt-names = "macirq"; + phy-mode = "rgmii"; + status = "disabled"; + }; + + pinmux: pinmux@e0700000 { + compatible = "st,spear1310-pinmux"; + reg = <0xe0700000 0x1000>; + #gpio-range-cells = <3>; + }; + + apb { + i2c1: i2c@5cd00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5cd00000 0x1000>; + interrupts = <0 87 0x4>; + status = "disabled"; + }; + + i2c2: i2c@5ce00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5ce00000 0x1000>; + interrupts = <0 88 0x4>; + status = "disabled"; + }; + + i2c3: i2c@5cf00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5cf00000 0x1000>; + interrupts = <0 89 0x4>; + status = "disabled"; + }; + + i2c4: i2c@5d000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d000000 0x1000>; + interrupts = <0 90 0x4>; + status = "disabled"; + }; + + i2c5: i2c@5d100000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d100000 0x1000>; + interrupts = <0 91 0x4>; + status = "disabled"; + }; + + i2c6: i2c@5d200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d200000 0x1000>; + interrupts = <0 92 0x4>; + status = "disabled"; + }; + + i2c7: i2c@5d300000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d300000 0x1000>; + interrupts = <0 93 0x4>; + status = "disabled"; + }; + + spi1: spi@5d400000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x5d400000 0x1000>; + interrupts = <0 99 0x4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial@5c800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5c800000 0x1000>; + interrupts = <0 82 0x4>; + status = "disabled"; + }; + + serial@5c900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5c900000 0x1000>; + interrupts = <0 83 0x4>; + status = "disabled"; + }; + + serial@5ca00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5ca00000 0x1000>; + interrupts = <0 84 0x4>; + status = "disabled"; + }; + + serial@5cb00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5cb00000 0x1000>; + interrupts = <0 85 0x4>; + status = "disabled"; + }; + + serial@5cc00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5cc00000 0x1000>; + interrupts = <0 86 0x4>; + status = "disabled"; + }; + + thermal@e07008c4 { + st,thermal-flags = <0x7000>; + }; + + gpiopinctrl: gpio@d8400000 { + compatible = "st,spear-plgpio"; + reg = <0xd8400000 0x1000>; + interrupts = <0 100 0x4>; + #interrupt-cells = <1>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinmux 0 0 246>; + status = "disabled"; + + st-plgpio,ngpio = <246>; + st-plgpio,enb-reg = <0xd0>; + st-plgpio,wdata-reg = <0x90>; + st-plgpio,dir-reg = <0xb0>; + st-plgpio,ie-reg = <0x30>; + st-plgpio,rdata-reg = <0x70>; + st-plgpio,mis-reg = <0x10>; + st-plgpio,eit-reg = <0x50>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts new file mode 100644 index 000000000000..7700f2afc128 --- /dev/null +++ b/arch/arm/boot/dts/st/spear1340-evb.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr1340 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + */ + +/dts-v1/; +/include/ "spear1340.dtsi" + +/ { + model = "ST SPEAr1340 Evaluation Board"; + compatible = "st,spear1340-evb", "st,spear1340"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@e0700000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pads_as_gpio { + st,pins = "pads_as_gpio_grp"; + st,function = "pads_as_gpio"; + }; + fsmc { + st,pins = "fsmc_8bit_grp"; + st,function = "fsmc"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + i2c1 { + st,pins = "i2c1_grp"; + st,function = "i2c1"; + }; + spdif-in { + st,pins = "spdif_in_grp"; + st,function = "spdif_in"; + }; + spdif-out { + st,pins = "spdif_out_grp"; + st,function = "spdif_out"; + }; + ssp0 { + st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp"; + st,function = "ssp0"; + }; + smi-pmx { + st,pins = "smi_grp"; + st,function = "smi"; + }; + i2s { + st,pins = "i2s_in_grp", "i2s_out_grp"; + st,function = "i2s"; + }; + gmac { + st,pins = "gmii_grp", "rgmii_grp"; + st,function = "gmac"; + }; + cam0 { + st,pins = "cam0_grp"; + st,function = "cam0"; + }; + cam1 { + st,pins = "cam1_grp"; + st,function = "cam1"; + }; + cam2 { + st,pins = "cam2_grp"; + st,function = "cam2"; + }; + cam3 { + st,pins = "cam3_grp"; + st,function = "cam3"; + }; + cec0 { + st,pins = "cec0_grp"; + st,function = "cec0"; + }; + cec1 { + st,pins = "cec1_grp"; + st,function = "cec1"; + }; + sdhci { + st,pins = "sdhci_grp"; + st,function = "sdhci"; + }; + clcd { + st,pins = "clcd_grp"; + st,function = "clcd"; + }; + sata { + st,pins = "sata_grp"; + st,function = "sata"; + }; + pcie { + st,pins = "pcie_grp"; + st,function = "pcie"; + }; + + }; + }; + + ahci@b1000000 { + status = "okay"; + }; + + miphy@eb800000 { + status = "okay"; + }; + + dma@ea800000 { + status = "okay"; + }; + + dma@eb000000 { + status = "okay"; + }; + + fsmc: flash@b0000000 { + status = "okay"; + + partition@0 { + label = "xloader"; + reg = <0x0 0x200000>; + }; + partition@200000 { + label = "u-boot"; + reg = <0x200000 0x200000>; + }; + partition@400000 { + label = "environment"; + reg = <0x400000 0x100000>; + }; + partition@500000 { + label = "dtb"; + reg = <0x500000 0x100000>; + }; + partition@600000 { + label = "linux"; + reg = <0x600000 0xC00000>; + }; + partition@1200000 { + label = "rootfs"; + reg = <0x1200000 0x0>; + }; + }; + + gmac0: eth@e2000000 { + phy-mode = "rgmii"; + status = "okay"; + }; + + sdhci@b3000000 { + status = "okay"; + }; + + smi: flash@ea000000 { + status = "okay"; + clock-rate = <50000000>; + + flash@e6000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe6000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; + + ehci@e4800000 { + status = "okay"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "wakeup"; + linux,code = <0x100>; + gpios = <&gpio1 1 0x4>; + debounce-interval = <20>; + wakeup-source; + }; + }; + + ehci@e5800000 { + status = "okay"; + }; + + i2s0: i2s-play@b2400000 { + status = "okay"; + }; + + i2s1: i2s-rec@b2000000 { + status = "okay"; + }; + + incodec: dir-hifi { + compatible = "dummy,dir-hifi"; + status = "okay"; + }; + + ohci@e4000000 { + status = "okay"; + }; + + ohci@e5000000 { + status = "okay"; + }; + + outcodec: dit-hifi { + compatible = "dummy,dit-hifi"; + status = "okay"; + }; + + sound { + compatible = "spear,spear-evb"; + audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>; + audio-codecs = <&incodec &outcodec &sta529 &sta529>; + codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio"; + stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap"; + dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm"; + nr_controllers = <4>; + status = "okay"; + }; + + spdif0: spdif-in@d0100000 { + status = "okay"; + }; + + spdif1: spdif-out@d0000000 { + status = "okay"; + }; + + apb { + adc@e0080000 { + status = "okay"; + }; + + i2s-play@b2400000 { + status = "okay"; + }; + + i2s-rec@b2000000 { + status = "okay"; + }; + + gpio0: gpio@e0600000 { + status = "okay"; + }; + + gpio1: gpio@e0680000 { + status = "okay"; + }; + + gpio@e2800000 { + status = "okay"; + }; + + i2c0: i2c@e0280000 { + status = "okay"; + + sta529: sta529@1a { + compatible = "st,sta529"; + reg = <0x1a>; + }; + }; + + i2c1: i2c@b4000000 { + status = "okay"; + + eeprom0@56 { + compatible = "st,eeprom"; + reg = <0x56>; + }; + + stmpe801@41 { + compatible = "st,stmpe801"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <4 0x4>; + interrupt-parent = <&gpio0>; + irq-trigger = <0x2>; + + stmpegpio: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + kbd@e0300000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + suspended_rate = <2000000>; + status = "okay"; + }; + + rtc@e0580000 { + status = "okay"; + }; + + serial@e0000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@b4100000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + spi0: spi@e0100000 { + status = "okay"; + num-cs = <3>; + cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>, + <&gpiopinctrl 85 0>; + + flash@0 { + compatible = "m25p80"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-cpol; + spi-cpha; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable; + pl022,com-mode = <0x2>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; + + stmpe610@1 { + compatible = "st,stmpe610"; + spi-max-frequency = <1000000>; + spi-cpha; + reg = <1>; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable; + pl022,com-mode = <0>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x7>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + interrupts = <100 0>; + interrupt-parent = <&gpiopinctrl>; + irq-trigger = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + ts,sample-time = <4>; + ts,mod-12b = <1>; + ts,ref-sel = <0>; + ts,adc-freq = <1>; + ts,ave-ctrl = <1>; + ts,touch-det-delay = <2>; + ts,settling = <2>; + ts,fraction-z = <7>; + ts,i-drive = <1>; + }; + }; + }; + + timer@ec800600 { + status = "okay"; + }; + + wdt@ec800620 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear1340.dtsi b/arch/arm/boot/dts/st/spear1340.dtsi new file mode 100644 index 000000000000..818886e11713 --- /dev/null +++ b/arch/arm/boot/dts/st/spear1340.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for all SPEAr1340 SoCs + * + * Copyright 2012 Viresh Kumar + */ + +/include/ "spear13xx.dtsi" + +/ { + compatible = "st,spear1340"; + + ahb { + + spics: spics@e0700000{ + compatible = "st,spear-spics-gpio"; + reg = <0xe0700000 0x1000>; + st-spics,peripcfg-reg = <0x42c>; + st-spics,sw-enable-bit = <21>; + st-spics,cs-value-bit = <20>; + st-spics,cs-enable-mask = <3>; + st-spics,cs-enable-shift = <18>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + miphy0: miphy@eb800000 { + compatible = "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { + compatible = "snps,spear-ahci"; + reg = <0xb1000000 0x10000>; + interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; + reg-names = "dbi", "config"; + interrupts = <0 68 0x4>; + num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; + status = "disabled"; + }; + + i2s-play@b2400000 { + compatible = "snps,designware-i2s"; + reg = <0xb2400000 0x10000>; + interrupt-names = "play_irq"; + interrupts = <0 98 0x4 + 0 99 0x4>; + play; + channel = <8>; + status = "disabled"; + }; + + i2s-rec@b2000000 { + compatible = "snps,designware-i2s"; + reg = <0xb2000000 0x10000>; + interrupt-names = "record_irq"; + interrupts = <0 100 0x4 + 0 101 0x4>; + record; + channel = <8>; + status = "disabled"; + }; + + pinmux: pinmux@e0700000 { + compatible = "st,spear1340-pinmux"; + reg = <0xe0700000 0x1000>; + #gpio-range-cells = <3>; + }; + + pwm: pwm@e0180000 { + compatible = "st,spear13xx-pwm"; + reg = <0xe0180000 0x1000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + spdif-in@d0100000 { + compatible = "st,spdif-in"; + reg = < 0xd0100000 0x20000 + 0xd0110000 0x10000 >; + interrupts = <0 84 0x4>; + status = "disabled"; + }; + + spdif-out@d0000000 { + compatible = "st,spdif-out"; + reg = <0xd0000000 0x20000>; + interrupts = <0 85 0x4>; + status = "disabled"; + }; + + spi1: spi@5d400000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x5d400000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + + apb { + i2c1: i2c@b4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xb4000000 0x1000>; + interrupts = <0 104 0x4>; + write-16bit; + status = "disabled"; + }; + + serial@b4100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb4100000 0x1000>; + interrupts = <0 105 0x4>; + status = "disabled"; + dmas = <&dwdma0 13 0 1>, + <&dwdma0 12 1 0>; + dma-names = "rx", "tx"; + }; + + thermal@e07008c4 { + st,thermal-flags = <0x2a00>; + }; + + gpiopinctrl: gpio@e2800000 { + compatible = "st,spear-plgpio"; + reg = <0xe2800000 0x1000>; + interrupts = <0 107 0x4>; + #interrupt-cells = <1>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinmux 0 0 252>; + status = "disabled"; + + st-plgpio,ngpio = <250>; + st-plgpio,wdata-reg = <0x40>; + st-plgpio,dir-reg = <0x00>; + st-plgpio,ie-reg = <0x80>; + st-plgpio,rdata-reg = <0x20>; + st-plgpio,mis-reg = <0xa0>; + st-plgpio,eit-reg = <0x60>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi new file mode 100644 index 000000000000..913553367687 --- /dev/null +++ b/arch/arm/boot/dts/st/spear13xx.dtsi @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for all SPEAr13xx SoCs + * + * Copyright 2012 Viresh Kumar + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + gic: interrupt-controller@ec801000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0xec801000 0x1000 >, + < 0xec800100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 6 0x04 + 0 7 0x04>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xed000000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyAMA0,115200"; + }; + + cpufreq { + compatible = "st,cpufreq-spear"; + cpufreq_tbl = < 166000 + 200000 + 250000 + 300000 + 400000 + 500000 + 600000 >; + status = "disabled"; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x50000000 0x50000000 0x10000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 + 0xd8000000 0xd8000000 0x01000000 + 0xe0000000 0xe0000000 0x10000000>; + + sdhci@b3000000 { + compatible = "st,sdhci-spear"; + reg = <0xb3000000 0x100>; + interrupts = <0 28 0x4>; + status = "disabled"; + }; + + cf@b2800000 { + compatible = "arasan,cf-spear1340"; + reg = <0xb2800000 0x1000>; + interrupts = <0 29 0x4>; + status = "disabled"; + dmas = <&dwdma0 0 0 0>; + dma-names = "data"; + }; + + dwdma0: dma@ea800000 { + compatible = "snps,dma-spear1340"; + reg = <0xea800000 0x1000>; + interrupts = <0 19 0x4>; + status = "disabled"; + + dma-channels = <8>; + #dma-cells = <3>; + dma-requests = <32>; + chan_allocation_order = <1>; + chan_priority = <1>; + block_size = <0xfff>; + dma-masters = <2>; + data-width = <8 8>; + multi-block = <1 1 1 1 1 1 1 1>; + }; + + dma@eb000000 { + compatible = "snps,dma-spear1340"; + reg = <0xeb000000 0x1000>; + interrupts = <0 59 0x4>; + status = "disabled"; + + dma-requests = <32>; + dma-channels = <8>; + dma-masters = <2>; + #dma-cells = <3>; + chan_allocation_order = <1>; + chan_priority = <1>; + block_size = <0xfff>; + data-width = <8 8>; + multi-block = <1 1 1 1 1 1 1 1>; + }; + + fsmc: flash@b0000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000000 0x1000 /* FSMC Register*/ + 0xb0800000 0x0010 /* NAND Base DATA */ + 0xb0820000 0x0010 /* NAND Base ADDR */ + 0xb0810000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + interrupts = <0 20 0x4 + 0 21 0x4 + 0 22 0x4 + 0 23 0x4>; + st,mode = <2>; + status = "disabled"; + }; + + gmac0: eth@e2000000 { + compatible = "st,spear600-gmac"; + reg = <0xe2000000 0x8000>; + interrupts = <0 33 0x4 + 0 34 0x4>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + pcm { + compatible = "st,pcm-audio"; + #address-cells = <0>; + #size-cells = <0>; + status = "disabled"; + }; + + smi: flash@ea000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xea000000 0x1000>; + interrupts = <0 30 0x4>; + status = "disabled"; + }; + + ehci@e4800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe4800000 0x1000>; + interrupts = <0 64 0x4>; + usbh0_id = <0>; + status = "disabled"; + }; + + ehci@e5800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe5800000 0x1000>; + interrupts = <0 66 0x4>; + usbh1_id = <1>; + status = "disabled"; + }; + + ohci@e4000000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe4000000 0x1000>; + interrupts = <0 65 0x4>; + usbh0_id = <0>; + status = "disabled"; + }; + + ohci@e5000000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe5000000 0x1000>; + interrupts = <0 67 0x4>; + usbh1_id = <1>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x50000000 0x50000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x02000000 + 0xd8000000 0xd8000000 0x01000000 + 0xe0000000 0xe0000000 0x10000000>; + + misc: syscon@e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + + gpio0: gpio@e0600000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xe0600000 0x1000>; + interrupts = <0 24 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@e0680000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xe0680000 0x1000>; + interrupts = <0 25 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + kbd@e0300000 { + compatible = "st,spear300-kbd"; + reg = <0xe0300000 0x1000>; + interrupts = <0 52 0x4>; + status = "disabled"; + }; + + i2c0: i2c@e0280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xe0280000 0x1000>; + interrupts = <0 41 0x4>; + status = "disabled"; + }; + + i2s@e0180000 { + compatible = "st,designware-i2s"; + reg = <0xe0180000 0x1000>; + interrupt-names = "play_irq", "record_irq"; + interrupts = <0 10 0x4 + 0 11 0x4 >; + status = "disabled"; + }; + + i2s@e0200000 { + compatible = "st,designware-i2s"; + reg = <0xe0200000 0x1000>; + interrupt-names = "play_irq", "record_irq"; + interrupts = <0 26 0x4 + 0 53 0x4>; + status = "disabled"; + }; + + spi0: spi@e0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xe0100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 31 0x4>; + status = "disabled"; + dmas = <&dwdma0 5 0 0>, + <&dwdma0 4 0 0>; + dma-names = "rx", "tx"; + }; + + rtc@e0580000 { + compatible = "st,spear600-rtc"; + reg = <0xe0580000 0x1000>; + interrupts = <0 36 0x4>; + status = "disabled"; + }; + + serial@e0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xe0000000 0x1000>; + interrupts = <0 35 0x4>; + status = "disabled"; + }; + + adc@e0080000 { + compatible = "st,spear600-adc"; + reg = <0xe0080000 0x1000>; + interrupts = <0 12 0x4>; + status = "disabled"; + }; + + timer@e0380000 { + compatible = "st,spear-timer"; + reg = <0xe0380000 0x400>; + interrupts = <0 37 0x4>; + }; + + timer@ec800600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xec800600 0x20>; + interrupts = <1 13 0x4>; + status = "disabled"; + }; + + wdt@ec800620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xec800620 0x20>; + status = "disabled"; + }; + + thermal@e07008c4 { + compatible = "st,thermal-spear1340"; + reg = <0xe07008c4 0x4>; + thermal_flags = <0x7000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear300-evb.dts b/arch/arm/boot/dts/st/spear300-evb.dts new file mode 100644 index 000000000000..303ef29fb805 --- /dev/null +++ b/arch/arm/boot/dts/st/spear300-evb.dts @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr300 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + */ + +/dts-v1/; +/include/ "spear300.dtsi" + +/ { + model = "ST SPEAr300 Evaluation Board"; + compatible = "st,spear300-evb", "st,spear300"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@99000000 { + st,pinmux-mode = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + clcd { + st,pins = "clcd_pfmode_grp"; + st,function = "clcd"; + }; + sdhci { + st,pins = "sdhci_4bit_grp"; + st,function = "sdhci"; + }; + gpio1 { + st,pins = "gpio1_4_to_7_grp", + "gpio1_0_to_3_grp"; + st,function = "gpio1"; + }; + }; + }; + + clcd@60000000 { + status = "okay"; + }; + + dma@fc400000 { + status = "okay"; + }; + + fsmc: flash@94000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + sdhci@70000000 { + cd-gpios = <&gpio1 0 0>; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate = <50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + gpio1: gpio@a9000000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + kbd@a0000000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear300.dtsi b/arch/arm/boot/dts/st/spear300.dtsi new file mode 100644 index 000000000000..f1135e887f7b --- /dev/null +++ b/arch/arm/boot/dts/st/spear300.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr300 SoC + * + * Copyright 2012 Viresh Kumar + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x50000000 + 0xd0000000 0xd0000000 0x30000000>; + + pinmux@99000000 { + compatible = "st,spear300-pinmux"; + reg = <0x99000000 0x1000>; + }; + + clcd@60000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x60000000 0x1000>; + interrupts = <30>; + status = "disabled"; + }; + + fsmc: flash@94000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x94000000 0x1000 /* FSMC Register */ + 0x80000000 0x0010 /* NAND Base DATA */ + 0x80020000 0x0010 /* NAND Base ADDR */ + 0x80010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + status = "disabled"; + }; + + sdhci@70000000 { + compatible = "st,sdhci-spear"; + reg = <0x70000000 0x100>; + interrupts = <1>; + status = "disabled"; + }; + + shirq: interrupt-controller@50000000 { + compatible = "st,spear300-shirq"; + reg = <0x50000000 0x1000>; + interrupts = <28>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xa0000000 0xa0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + gpio1: gpio@a9000000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xa9000000 0x1000>; + interrupts = <8>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + kbd@a0000000 { + compatible = "st,spear300-kbd"; + reg = <0xa0000000 0x1000>; + interrupts = <7>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear310-evb.dts b/arch/arm/boot/dts/st/spear310-evb.dts new file mode 100644 index 000000000000..ea0b53036f7b --- /dev/null +++ b/arch/arm/boot/dts/st/spear310-evb.dts @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr310 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + */ + +/dts-v1/; +/include/ "spear310.dtsi" + +/ { + model = "ST SPEAr310 Evaluation Board"; + compatible = "st,spear310-evb", "st,spear310"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@b4000000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + gpio0 { + st,pins = "gpio0_pin0_grp", + "gpio0_pin1_grp", + "gpio0_pin2_grp", + "gpio0_pin3_grp", + "gpio0_pin4_grp", + "gpio0_pin5_grp"; + st,function = "gpio0"; + }; + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + emi { + st,pins = "emi_cs_0_to_5_grp"; + st,function = "emi"; + }; + fsmc { + st,pins = "fsmc_grp"; + st,function = "fsmc"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + uart3 { + st,pins = "uart3_grp"; + st,function = "uart3"; + }; + uart4 { + st,pins = "uart4_grp"; + st,function = "uart4"; + }; + uart5 { + st,pins = "uart5_grp"; + st,function = "uart5"; + }; + }; + }; + + dma@fc400000 { + status = "okay"; + }; + + fsmc: flash@44000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate = <50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@b2000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@b2080000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@b2100000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@b2180000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@b2200000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear310.dtsi b/arch/arm/boot/dts/st/spear310.dtsi new file mode 100644 index 000000000000..ce08d8820940 --- /dev/null +++ b/arch/arm/boot/dts/st/spear310.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr310 SoC + * + * Copyright 2012 Viresh Kumar + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + pinmux: pinmux@b4000000 { + compatible = "st,spear310-pinmux"; + reg = <0xb4000000 0x1000>; + #gpio-range-cells = <3>; + }; + + fsmc: flash@44000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x44000000 0x1000 /* FSMC Register */ + 0x40000000 0x0010 /* NAND Base DATA */ + 0x40020000 0x0010 /* NAND Base ADDR */ + 0x40010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + status = "disabled"; + }; + + shirq: interrupt-controller@b4000000 { + compatible = "st,spear310-shirq"; + reg = <0xb4000000 0x1000>; + interrupts = <28 29 30 1>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + serial@b2000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2000000 0x1000>; + interrupts = <8>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + serial@b2080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2080000 0x1000>; + interrupts = <9>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + serial@b2100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2100000 0x1000>; + interrupts = <10>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + serial@b2180000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2180000 0x1000>; + interrupts = <11>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + serial@b2200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2200000 0x1000>; + interrupts = <12>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + gpiopinctrl: gpio@b4000000 { + compatible = "st,spear-plgpio"; + reg = <0xb4000000 0x1000>; + regmap = <&pinmux>; + #interrupt-cells = <1>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinmux 0 0 102>; + status = "disabled"; + + st-plgpio,ngpio = <102>; + st-plgpio,enb-reg = <0x10>; + st-plgpio,wdata-reg = <0x20>; + st-plgpio,dir-reg = <0x30>; + st-plgpio,ie-reg = <0x50>; + st-plgpio,rdata-reg = <0x40>; + st-plgpio,mis-reg = <0x60>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear320-evb.dts b/arch/arm/boot/dts/st/spear320-evb.dts new file mode 100644 index 000000000000..3c026d021c92 --- /dev/null +++ b/arch/arm/boot/dts/st/spear320-evb.dts @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + */ + +/dts-v1/; +/include/ "spear320.dtsi" + +/ { + model = "ST SPEAr320 Evaluation Board"; + compatible = "st,spear320-evb", "st,spear320"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@b3000000 { + st,pinmux-mode = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + sdhci { + st,pins = "sdhci_cd_51_grp"; + st,function = "sdhci"; + }; + i2s { + st,pins = "i2s_grp"; + st,function = "i2s"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + can0 { + st,pins = "can0_grp"; + st,function = "can0"; + }; + can1 { + st,pins = "can1_grp"; + st,function = "can1"; + }; + mii2 { + st,pins = "mii2_grp"; + st,function = "mii2"; + }; + pwm0_1 { + st,pins = "pwm0_1_pin_37_38_grp"; + st,function = "pwm0_1"; + }; + }; + }; + + dma@fc400000 { + status = "okay"; + }; + + fsmc: flash@4c000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + sdhci@70000000 { + power-gpio = <&gpiopinctrl 61 1>; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate = <50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + spi1: spi@a5000000 { + status = "okay"; + }; + + spi2: spi@a6000000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + gpio@b3000000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + i2c1: i2c@a7000000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@a3000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@a4000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear320-hmi.dts b/arch/arm/boot/dts/st/spear320-hmi.dts new file mode 100644 index 000000000000..721e5ee7b680 --- /dev/null +++ b/arch/arm/boot/dts/st/spear320-hmi.dts @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320 Evaluation Baord + * + * Copyright 2012 Shiraz Hashim + */ + +/dts-v1/; +/include/ "spear320.dtsi" + +/ { + model = "ST SPEAr320 HMI Board"; + compatible = "st,spear320-hmi", "st,spear320"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@b3000000 { + st,pinmux-mode = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + clcd { + st,pins = "clcd_grp"; + st,function = "clcd"; + }; + fsmc { + st,pins = "fsmc_8bit_grp"; + st,function = "fsmc"; + }; + sdhci { + st,pins = "sdhci_cd_12_grp"; + st,function = "sdhci"; + }; + i2s { + st,pins = "i2s_grp"; + st,function = "i2s"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + can0 { + st,pins = "can0_grp"; + st,function = "can0"; + }; + can1 { + st,pins = "can1_grp"; + st,function = "can1"; + }; + mii0_1 { + st,pins = "rmii0_1_grp"; + st,function = "mii0_1"; + }; + pwm0_1 { + st,pins = "pwm0_1_pin_37_38_grp"; + st,function = "pwm0_1"; + }; + pwm2 { + st,pins = "pwm2_pin_34_grp"; + st,function = "pwm2"; + }; + }; + }; + + clcd@90000000 { + status = "okay"; + }; + + dma@fc400000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + fsmc: flash@4c000000 { + status = "okay"; + + partition@0 { + label = "xloader"; + reg = <0x0 0x80000>; + }; + partition@80000 { + label = "u-boot"; + reg = <0x80000 0x140000>; + }; + partition@1C0000 { + label = "environment"; + reg = <0x1C0000 0x40000>; + }; + partition@200000 { + label = "dtb"; + reg = <0x200000 0x40000>; + }; + partition@240000 { + label = "linux"; + reg = <0x240000 0xC00000>; + }; + partition@E40000 { + label = "rootfs"; + reg = <0xE40000 0x0>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "user button 1"; + linux,code = <0x100>; + gpios = <&stmpegpio 3 0x4>; + debounce-interval = <20>; + wakeup-source; + }; + + button@2 { + label = "user button 2"; + linux,code = <0x200>; + gpios = <&stmpegpio 2 0x4>; + debounce-interval = <20>; + wakeup-source; + }; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + pwm: pwm@a8000000 { + status = "okay"; + }; + + sdhci@70000000 { + power-gpio = <&gpiopinctrl 50 1>; + power_always_enb; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate = <50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + spi1: spi@a5000000 { + status = "okay"; + }; + + spi2: spi@a6000000 { + status = "okay"; + }; + + usbd@e1100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + gpio@b3000000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + + stmpe811@41 { + compatible = "st,stmpe811"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + irq-gpios = <&gpiopinctrl 29 0x4>; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + + stmpegpio: stmpe-gpio { + compatible = "st,stmpe-gpio"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + gpio,norequest-mask = <0xF3>; + }; + + stmpe610-ts { + compatible = "stmpe,ts"; + reg = <0>; + ts,sample-time = <4>; + ts,mod-12b = <1>; + ts,ref-sel = <0>; + ts,adc-freq = <1>; + ts,ave-ctrl = <1>; + ts,touch-det-delay = <3>; + ts,settling = <4>; + ts,fraction-z = <7>; + ts,i-drive = <1>; + }; + }; + }; + + i2c1: i2c@a7000000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@a3000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + serial@a4000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear320.dtsi b/arch/arm/boot/dts/st/spear320.dtsi new file mode 100644 index 000000000000..56f141297ea3 --- /dev/null +++ b/arch/arm/boot/dts/st/spear320.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320 SoC + * + * Copyright 2012 Viresh Kumar + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x80000000 + 0xd0000000 0xd0000000 0x30000000>; + + pinmux: pinmux@b3000000 { + compatible = "st,spear320-pinmux"; + reg = <0xb3000000 0x1000>; + #gpio-range-cells = <3>; + }; + + clcd@90000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x90000000 0x1000>; + interrupts = <8>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + fsmc: flash@4c000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x4c000000 0x1000 /* FSMC Register */ + 0x50000000 0x0010 /* NAND Base DATA */ + 0x50020000 0x0010 /* NAND Base ADDR */ + 0x50010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + status = "disabled"; + }; + + sdhci@70000000 { + compatible = "st,sdhci-spear"; + reg = <0x70000000 0x100>; + interrupts = <10>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + shirq: interrupt-controller@b3000000 { + compatible = "st,spear320-shirq"; + reg = <0xb3000000 0x1000>; + interrupts = <30 28 29 1>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + spi1: spi@a5000000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xa5000000 0x1000>; + interrupts = <15>; + interrupt-parent = <&shirq>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@a6000000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xa6000000 0x1000>; + interrupts = <16>; + interrupt-parent = <&shirq>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@a8000000 { + compatible = "st,spear-pwm"; + reg = <0xa8000000 0x1000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xa0000000 0xa0000000 0x20000000 + 0xd0000000 0xd0000000 0x30000000>; + + i2c1: i2c@a7000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xa7000000 0x1000>; + interrupts = <21>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + serial@a3000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xa3000000 0x1000>; + interrupts = <13>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + serial@a4000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xa4000000 0x1000>; + interrupts = <14>; + interrupt-parent = <&shirq>; + status = "disabled"; + }; + + gpiopinctrl: gpio@b3000000 { + compatible = "st,spear-plgpio"; + reg = <0xb3000000 0x1000>; + regmap = <&pinmux>; + #interrupt-cells = <1>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinmux 0 0 102>; + status = "disabled"; + + st-plgpio,ngpio = <102>; + st-plgpio,enb-reg = <0x24>; + st-plgpio,wdata-reg = <0x34>; + st-plgpio,dir-reg = <0x44>; + st-plgpio,ie-reg = <0x64>; + st-plgpio,rdata-reg = <0x54>; + st-plgpio,mis-reg = <0x84>; + st-plgpio,eit-reg = <0x94>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear320s.dtsi b/arch/arm/boot/dts/st/spear320s.dtsi new file mode 100644 index 000000000000..133236dc190d --- /dev/null +++ b/arch/arm/boot/dts/st/spear320s.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320s SoC + * + * Copyright 2021 Herve Codina + */ + +/include/ "spear320.dtsi" + +/ { + ahb { + apb { + gpiopinctrl: gpio@b3000000 { + /* + * The "RM0321 SPEAr320s address and map + * registers" document mentions interrupt 6 + * (NPGIO_INTR) for the PL_GPIO interrupt. + */ + interrupts = <6>; + interrupt-parent = <&shirq>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear3xx.dtsi b/arch/arm/boot/dts/st/spear3xx.dtsi new file mode 100644 index 000000000000..cc88ebe7a60c --- /dev/null +++ b/arch/arm/boot/dts/st/spear3xx.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for all SPEAr3xx SoCs + * + * Copyright 2012 Viresh Kumar + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <8>; + status = "disabled"; + }; + + gmac: eth@e0800000 { + compatible = "snps,dwmac-3.40a"; + reg = <0xe0800000 0x8000>; + interrupts = <23 22>; + interrupt-names = "macirq", "eth_wake_irq"; + phy-mode = "mii"; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + spi0: spi@d0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0100000 0x1000>; + interrupts = <20>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupts = <26>; + status = "disabled"; + }; + + ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupts = <25>; + status = "disabled"; + }; + + ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + gpio0: gpio@fc980000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xfc980000 0x1000>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + i2c0: i2c@d0180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0180000 0x1000>; + interrupts = <21>; + status = "disabled"; + }; + + rtc@fc900000 { + compatible = "st,spear600-rtc"; + reg = <0xfc900000 0x1000>; + interrupts = <10>; + status = "disabled"; + }; + + serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupts = <19>; + status = "disabled"; + }; + + wdt@fc880000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0xfc880000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/spear600-evb.dts b/arch/arm/boot/dts/st/spear600-evb.dts new file mode 100644 index 000000000000..a25b86d149ad --- /dev/null +++ b/arch/arm/boot/dts/st/spear600-evb.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Stefan Roese + */ + +/dts-v1/; +/include/ "spear600.dtsi" + +/ { + model = "ST SPEAr600 Evaluation Board"; + compatible = "st,spear600-evb", "st,spear600"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0 0x10000000>; + }; +}; + +&clcd { + status = "okay"; +}; + +&dmac { + status = "okay"; +}; + +&ehci_usb0 { + status = "okay"; +}; + +&ehci_usb1 { + status = "okay"; +}; + +&gmac { + phy-mode = "gmii"; + status = "okay"; +}; + +&ohci_usb0 { + status = "okay"; +}; + +&ohci_usb1 { + status = "okay"; +}; + +&smi { + status = "okay"; + clock-rate = <50000000>; + + flash@f8000000 { + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x50000>; + }; + partition@60000 { + label = "environment"; + reg = <0x60000 0x10000>; + }; + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; + }; + partition@80000 { + label = "linux"; + reg = <0x80000 0x310000>; + }; + partition@390000 { + label = "rootfs"; + reg = <0x390000 0x0>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&i2c { + clock-frequency = <400000>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/spear600.dtsi b/arch/arm/boot/dts/st/spear600.dtsi new file mode 100644 index 000000000000..6b67c0ceaed9 --- /dev/null +++ b/arch/arm/boot/dts/st/spear600.dtsi @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Stefan Roese + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,spear600"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic0: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@f1000000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1000000 0x1000>; + #interrupt-cells = <1>; + }; + + clcd: clcd@fc200000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0xfc200000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <13>; + status = "disabled"; + }; + + dmac: dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + status = "disabled"; + }; + + gmac: ethernet@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupt-parent = <&vic1>; + interrupts = <24 23>; + interrupt-names = "macirq", "eth_wake_irq"; + phy-mode = "gmii"; + status = "disabled"; + }; + + fsmc: flash@d1800000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd1800000 0x1000 /* FSMC Register */ + 0xd2000000 0x0010 /* NAND Base DATA */ + 0xd2020000 0x0010 /* NAND Base ADDR */ + 0xd2010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <12>; + status = "disabled"; + }; + + ehci_usb0: ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <27>; + status = "disabled"; + }; + + ehci_usb1: ehci@e2000000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe2000000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <29>; + status = "disabled"; + }; + + ohci_usb0: ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <26>; + status = "disabled"; + }; + + ohci_usb1: ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <28>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + uart0: serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + status = "disabled"; + }; + + uart1: serial@d0080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0080000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <25>; + status = "disabled"; + }; + + /* local/cpu GPIO */ + gpio0: gpio@f0100000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xf0100000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <18>; + }; + + /* basic GPIO */ + gpio1: gpio@fc980000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfc980000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <19>; + }; + + /* appl GPIO */ + gpio2: gpio@d8100000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xd8100000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <4>; + }; + + i2c: i2c@d0200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0200000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <28>; + status = "disabled"; + }; + + rtc: rtc@fc900000 { + compatible = "st,spear600-rtc"; + reg = <0xfc900000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <10>; + status = "disabled"; + }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupt-parent = <&vic0>; + interrupts = <16>; + }; + + adc: adc@d820b000 { + compatible = "st,spear600-adc"; + reg = <0xd820b000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <6>; + status = "disabled"; + }; + + ssp1: spi@d0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&vic0>; + interrupts = <26>; + status = "disabled"; + }; + + ssp2: spi@d0180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0180000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&vic0>; + interrupts = <27>; + status = "disabled"; + }; + + ssp3: spi@d8180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd8180000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&vic1>; + interrupts = <5>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/st-pincfg.h b/arch/arm/boot/dts/st/st-pincfg.h new file mode 100644 index 000000000000..d80551202292 --- /dev/null +++ b/arch/arm/boot/dts/st/st-pincfg.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ST_PINCFG_H_ +#define _ST_PINCFG_H_ + +/* Alternate functions */ +#define ALT1 1 +#define ALT2 2 +#define ALT3 3 +#define ALT4 4 +#define ALT5 5 +#define ALT6 6 +#define ALT7 7 + +/* Output enable */ +#define OE (1 << 27) +/* Pull Up */ +#define PU (1 << 26) +/* Open Drain */ +#define OD (1 << 25) +#define RT (1 << 23) +#define INVERTCLK (1 << 22) +#define CLKNOTDATA (1 << 21) +#define DOUBLE_EDGE (1 << 20) +#define CLK_A (0 << 18) +#define CLK_B (1 << 18) +#define CLK_C (2 << 18) +#define CLK_D (3 << 18) + +/* User-frendly defines for Pin Direction */ + /* oe = 0, pu = 0, od = 0 */ +#define IN (0) + /* oe = 0, pu = 1, od = 0 */ +#define IN_PU (PU) + /* oe = 1, pu = 0, od = 0 */ +#define OUT (OE) + /* oe = 1, pu = 0, od = 1 */ +#define BIDIR (OE | OD) + /* oe = 1, pu = 1, od = 1 */ +#define BIDIR_PU (OE | PU | OD) + +/* RETIME_TYPE */ +/* + * B Mode + * Bypass retime with optional delay parameter + */ +#define BYPASS (0) +/* + * R0, R1, R0D, R1D modes + * single-edge data non inverted clock, retime data with clk + */ +#define SE_NICLK_IO (RT) +/* + * RIV0, RIV1, RIV0D, RIV1D modes + * single-edge data inverted clock, retime data with clk + */ +#define SE_ICLK_IO (RT | INVERTCLK) +/* + * R0E, R1E, R0ED, R1ED modes + * double-edge data, retime data with clk + */ +#define DE_IO (RT | DOUBLE_EDGE) +/* + * CIV0, CIV1 modes with inverted clock + * Retiming the clk pins will park clock & reduce the noise within the core. + */ +#define ICLK (RT | CLKNOTDATA | INVERTCLK) +/* + * CLK0, CLK1 modes with non-inverted clock + * Retiming the clk pins will park clock & reduce the noise within the core. + */ +#define NICLK (RT | CLKNOTDATA) +#endif /* _ST_PINCFG_H_ */ diff --git a/arch/arm/boot/dts/st/ste-ab8500.dtsi b/arch/arm/boot/dts/st/ste-ab8500.dtsi new file mode 100644 index 000000000000..dd30d08ccb9b --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ab8500.dtsi @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include + +/ { + /* Essential housekeeping hardware monitors */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&gpadc 0x02>, /* Battery temperature */ + <&gpadc 0x03>, /* Main charger voltage */ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0a>, /* Main charger current */ + <&gpadc 0x0b>, /* USB charger current */ + <&gpadc 0x0c>, /* Backup battery voltage */ + <&gpadc 0x0d>, /* Die temperature */ + <&gpadc 0x12>; /* Crystal temperature */ + }; + + soc { + prcmu@80157000 { + ab8500 { + compatible = "stericsson,ab8500"; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ab8500_clock: clock-controller { + compatible = "stericsson,ab8500-clk"; + #clock-cells = <1>; + }; + + ab8500_gpio: gpio { + compatible = "stericsson,ab8500-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: adc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* GPADC channels */ + bat_ctrl: channel@1 { + reg = <0x01>; + }; + btemp_ball: channel@2 { + reg = <0x02>; + }; + main_charger_v: channel@3 { + reg = <0x03>; + }; + acc_detect1: channel@4 { + reg = <0x04>; + }; + acc_detect2: channel@5 { + reg = <0x05>; + }; + adc_aux1: channel@6 { + reg = <0x06>; + }; + adc_aux2: channel@7 { + reg = <0x07>; + }; + main_batt_v: channel@8 { + reg = <0x08>; + }; + vbus_v: channel@9 { + reg = <0x09>; + }; + main_charger_c: channel@a { + reg = <0x0a>; + }; + usb_charger_c: channel@b { + reg = <0x0b>; + }; + bk_bat_v: channel@c { + reg = <0x0c>; + }; + die_temp: channel@d { + reg = <0x0d>; + }; + usb_id: channel@e { + reg = <0x0e>; + }; + xtal_temp: channel@12 { + reg = <0x12>; + }; + vbat_true_meas: channel@13 { + reg = <0x13>; + }; + bat_ctrl_and_ibat: channel@1c { + reg = <0x1c>; + }; + vbat_meas_and_ibat: channel@1d { + reg = <0x1d>; + }; + vbat_true_meas_and_ibat: channel@1e { + reg = <0x1e>; + }; + bat_temp_and_ibat: channel@1f { + reg = <0x1f>; + }; + }; + + thermal { + compatible = "stericsson,abx500-temp"; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ABX500_TEMP_WARM"; + }; + + ab8500_fg { + compatible = "stericsson,ab8500-fg"; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "NCONV_ACCU", + "BATT_OVV", + "LOW_BAT_F", + "CC_INT_CALIB", + "CCEOC"; + monitored-battery = <&battery>; + io-channels = <&gpadc 0x08>; + io-channel-names = "main_bat_v"; + }; + + ab8500_btemp { + compatible = "stericsson,ab8500-btemp"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "BAT_CTRL_INDB", + "BTEMP_LOW", + "BTEMP_HIGH", + "BTEMP_LOW_MEDIUM", + "BTEMP_MEDIUM_HIGH"; + monitored-battery = <&battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; + io-channel-names = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + compatible = "stericsson,ab8500-charger"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TYPE_LEVEL_HIGH>, + <107 IRQ_TYPE_LEVEL_HIGH>, + <106 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <105 IRQ_TYPE_LEVEL_HIGH>, + <104 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <21 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "MAIN_CH_UNPLUG_DET", + "MAIN_CHARGE_PLUG_DET", + "MAIN_EXT_CH_NOT_OK", + "MAIN_CH_TH_PROT_R", + "MAIN_CH_TH_PROT_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_CH_TH_PROT_R", + "USB_CH_TH_PROT_F", + "USB_CHARGER_NOT_OKR", + "VBUS_OVV", + "CH_WD_EXP", + "VBUS_CH_DROP_END"; + monitored-battery = <&battery>; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + io-channels = <&gpadc 0x03>, + <&gpadc 0x0a>, + <&gpadc 0x09>, + <&gpadc 0x0b>; + io-channel-names = "main_charger_v", + "main_charger_c", + "vbus_v", + "usb_charger_c"; + }; + + ab8500_chargalg { + compatible = "stericsson,ab8500-chargalg"; + monitored-battery = <&battery>; + }; + + ab8500_usb: phy { + compatible = "stericsson,ab8500-usb"; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + + key { + compatible = "stericsson,ab8500-poweron-key"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + pwm@1 { + compatible = "stericsson,ab8500-pwm"; + reg = <1>; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + #pwm-cells = <1>; + }; + + pwm@2 { + compatible = "stericsson,ab8500-pwm"; + reg = <2>; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + #pwm-cells = <1>; + }; + + pwm@3 { + compatible = "stericsson,ab8500-pwm"; + reg = <3>; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + #pwm-cells = <1>; + }; + + codec: codec { + compatible = "stericsson,ab8500-codec"; + + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + V-DMIC-supply = <&ab8500_ldo_dmic_reg>; + + clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; + clock-names = "audioclk"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + + ext_regulators: regulator-external { + compatible = "stericsson,ab8500-ext-regulator"; + + ab8500_ext1_reg: ab8500_ext1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext2_reg: ab8500_ext2 { + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext3_reg: ab8500_ext3 { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + }; + + regulator { + compatible = "stericsson,ab8500-regulator"; + vin-supply = <&ab8500_ext3_reg>; + + // supplies to the display/camera + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + /* BUG: If turned off MMC will be affected. */ + regulator-always-on; + }; + + // supplies to the on-board eMMC + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for VAUX3; SDcard slots + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + }; + + // supply for tvout; gpadc; TVOUT LDO + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + }; + + // supply for v-anamic1 VAMIC1 LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + }; + + // supply for v-dmic; VDMIC LDO + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + }; + }; + }; + }; + + sound { + stericsson,audio-codec = <&codec>; + clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "sysclk", "ulpclk", "intclk"; + }; + + mcde@a0350000 { + vana-supply = <&ab8500_ldo_ana_reg>; + + dsi@a0351000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0352000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0353000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; + + usb_per5@a03e0000 { + phys = <&ab8500_usb>; + phy-names = "usb"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ab8505.dtsi b/arch/arm/boot/dts/st/ste-ab8505.dtsi new file mode 100644 index 000000000000..131c82508e82 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ab8505.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include + +/ { + /* Essential housekeeping hardware monitors */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&gpadc 0x02>, /* Battery temperature */ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0b>, /* Charger current */ + <&gpadc 0x0c>, /* Backup battery voltage */ + <&gpadc 0x0d>; /* Die temperature */ + }; + + soc { + prcmu@80157000 { + ab8505 { + compatible = "stericsson,ab8505"; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ab8500_clock: clock-controller { + compatible = "stericsson,ab8500-clk"; + #clock-cells = <1>; + }; + + ab8505_gpio: gpio { + compatible = "stericsson,ab8505-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: adc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_adc_reg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* GPADC channels */ + bat_ctrl: channel@1 { + reg = <0x01>; + }; + btemp_ball: channel@2 { + reg = <0x02>; + }; + acc_detect1: channel@4 { + reg = <0x04>; + }; + acc_detect2: channel@5 { + reg = <0x05>; + }; + adc_aux1: channel@6 { + reg = <0x06>; + }; + adc_aux2: channel@7 { + reg = <0x07>; + }; + main_batt_v: channel@8 { + reg = <0x08>; + }; + vbus_v: channel@9 { + reg = <0x09>; + }; + charger_c: channel@b { + reg = <0x0b>; + }; + bk_bat_v: channel@c { + reg = <0x0c>; + }; + die_temp: channel@d { + reg = <0x0d>; + }; + usb_id: channel@e { + reg = <0x0e>; + }; + }; + + thermal { + compatible = "stericsson,abx500-temp"; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ABX500_TEMP_WARM"; + }; + + ab8500_fg { + compatible = "stericsson,ab8500-fg"; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "NCONV_ACCU", + "BATT_OVV", + "LOW_BAT_F", + "CC_INT_CALIB", + "CCEOC"; + monitored-battery = <&battery>; + io-channels = <&gpadc 0x08>; + io-channel-names = "main_bat_v"; + }; + + ab8500_btemp { + compatible = "stericsson,ab8500-btemp"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "BAT_CTRL_INDB", + "BTEMP_LOW", + "BTEMP_HIGH", + "BTEMP_LOW_MEDIUM", + "BTEMP_MEDIUM_HIGH"; + monitored-battery = <&battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; + io-channel-names = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + compatible = "stericsson,ab8500-charger"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TYPE_LEVEL_HIGH>, + <107 IRQ_TYPE_LEVEL_HIGH>, + <106 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <105 IRQ_TYPE_LEVEL_HIGH>, + <104 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <21 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "MAIN_CH_UNPLUG_DET", + "MAIN_CHARGE_PLUG_DET", + "MAIN_EXT_CH_NOT_OK", + "MAIN_CH_TH_PROT_R", + "MAIN_CH_TH_PROT_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_CH_TH_PROT_R", + "USB_CH_TH_PROT_F", + "USB_CHARGER_NOT_OKR", + "VBUS_OVV", + "CH_WD_EXP", + "VBUS_CH_DROP_END"; + monitored-battery = <&battery>; + vddadc-supply = <&ab8500_ldo_adc_reg>; + io-channels = <&gpadc 0x09>, + <&gpadc 0x0b>; + io-channel-names = "vbus_v", + "usb_charger_c"; + }; + + ab8500_chargalg { + compatible = "stericsson,ab8500-chargalg"; + monitored-battery = <&battery>; + }; + + ab8500_usb: phy { + compatible = "stericsson,ab8500-usb"; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + + key { + compatible = "stericsson,ab8500-poweron-key"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + pwm@1 { + compatible = "stericsson,ab8500-pwm"; + reg = <1>; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + #pwm-cells = <1>; + }; + + codec: codec { + compatible = "stericsson,ab8500-codec"; + + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + + clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; + clock-names = "audioclk"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + + regulator { + compatible = "stericsson,ab8505-regulator"; + + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux4_reg: ab8500_ldo_aux4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5_reg: ab8500_ldo_aux5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + ab8500_ldo_aux6_reg: ab8500_ldo_aux6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + }; + + // supply for gpadc; ADC LDO + ab8500_ldo_adc_reg: ab8500_ldo_adc { + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + }; + + // supply for v-anamic1 VAMIC1 LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + }; + + // supply for v-aux8; VAUX8 LDO + ab8500_ldo_aux8_reg: ab8500_ldo_aux8 { + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + }; + }; + }; + }; + + sound { + stericsson,audio-codec = <&codec>; + clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "sysclk", "ulpclk", "intclk"; + }; + + mcde@a0350000 { + vana-supply = <&ab8500_ldo_ana_reg>; + + dsi@a0351000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0352000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0353000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; + + usb_per5@a03e0000 { + phys = <&ab8500_usb>; + phy-names = "usb"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-db8500.dtsi b/arch/arm/boot/dts/st/ste-db8500.dtsi new file mode 100644 index 000000000000..f1ff3f4835d7 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-db8500.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "ste-dbx5x0.dtsi" + +/ { + cpus { + cpu@300 { + operating-points = <998400 0 + 798720 0 + 399360 0 + 199680 0>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Modem trace memory */ + ram@6000000 { + reg = <0x06000000 0x00f00000>; + no-map; + }; + + /* Modem shared memory */ + ram@6f00000 { + reg = <0x06f00000 0x00100000>; + no-map; + }; + + /* Modem private memory */ + ram@7000000 { + reg = <0x07000000 0x01000000>; + no-map; + }; + + /* + * Initial Secure Software ISSW memory + * + * This is probably only used if the kernel tries + * to actually call into trustzone to run secure + * applications, which the mainline kernel probably + * will not do on this old chipset. But you can never + * be too careful, so reserve this memory anyway. + */ + ram@17f00000 { + reg = <0x17f00000 0x00100000>; + no-map; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-db8520.dtsi b/arch/arm/boot/dts/st/ste-db8520.dtsi new file mode 100644 index 000000000000..e4e8d5fc1f8a --- /dev/null +++ b/arch/arm/boot/dts/st/ste-db8520.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "ste-dbx5x0.dtsi" + +/ { + cpus { + cpu@300 { + operating-points = <1152000 0 + 798720 0 + 399360 0 + 199680 0>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Modem trace memory */ + ram@6000000 { + reg = <0x06000000 0x00f00000>; + no-map; + }; + + /* Modem shared memory */ + ram@6f00000 { + reg = <0x06f00000 0x00100000>; + no-map; + }; + + /* Modem private memory */ + ram@7000000 { + reg = <0x07000000 0x01000000>; + no-map; + }; + + /* + * Initial Secure Software ISSW memory + * + * This is probably only used if the kernel tries + * to actually call into trustzone to run secure + * applications, which the mainline kernel probably + * will not do on this old chipset. But you can never + * be too careful, so reserve this memory anyway. + */ + ram@17f00000 { + reg = <0x17f00000 0x00100000>; + no-map; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-db9500.dtsi b/arch/arm/boot/dts/st/ste-db9500.dtsi new file mode 100644 index 000000000000..4273d36e881d --- /dev/null +++ b/arch/arm/boot/dts/st/ste-db9500.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "ste-dbx5x0.dtsi" + +/ { + cpus { + cpu@300 { + operating-points = <998400 0 + 798720 0 + 399360 0 + 199680 0>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * Initial Secure Software ISSW memory + * + * This is probably only used if the kernel tries + * to actually call into trustzone to run secure + * applications, which the mainline kernel probably + * will not do on this old chipset. But you can never + * be too careful, so reserve this memory anyway. + */ + ram@17f00000 { + reg = <0x17f00000 0x00100000>; + no-map; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi new file mode 100644 index 000000000000..31a86606beda --- /dev/null +++ b/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Linaro Ltd. + */ + +#include "ste-nomadik-pinctrl.dtsi" + +&pinctrl { + /* Settings for all UART default and sleep states */ + uart0 { + u0_a_1_default: u0_a_1_default { + default_mux { + function = "u0"; + groups = "u0_a_1"; + }; + default_cfg1 { + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&in_pu>; + }; + default_cfg2 { + pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ + ste,config = <&out_hi>; + }; + }; + + u0_a_1_sleep: u0_a_1_sleep { + sleep_cfg1 { + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO1_AJ3"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg3 { + pins = "GPIO3_AH3"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart1 { + u1rxtx_a_1_default: u1rxtx_a_1_default { + default_mux { + function = "u1"; + groups = "u1rxtx_a_1"; + }; + default_cfg1 { + pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&in_pu>; + }; + default_cfg2 { + pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + u1rxtx_a_1_sleep: u1rxtx_a_1_sleep { + sleep_cfg1 { + pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + + u1ctsrts_a_1_default: u1ctsrts_a_1_default { + default_mux { + function = "u1"; + groups = "u1ctsrts_a_1"; + }; + default_cfg1 { + pins = "GPIO6_AF6"; /* CTS */ + ste,config = <&in_pu>; + }; + default_cfg2 { + pins = "GPIO7_AG5"; /* RTS */ + ste,config = <&out_hi>; + }; + }; + + u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep { + sleep_cfg1 { + pins = "GPIO6_AF6"; /* CTS */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO7_AG5"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + }; + }; + + uart2 { + u2rxtx_c_1_default: u2rxtx_c_1_default { + default_mux { + function = "u2"; + groups = "u2rxtx_c_1"; + }; + default_cfg1 { + pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_pu>; + }; + default_cfg2 { + pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + u2rxtx_c_1_sleep: u2rxtx_c_1_sleep { + sleep_cfg1 { + pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_wkup_pdis>; + }; + }; + }; + + /* Settings for all I2C default and sleep states */ + i2c0 { + i2c0_a_1_default: i2c0_a_1_default { + default_mux { + function = "i2c0"; + groups = "i2c0_a_1"; + }; + default_cfg1 { + pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + ste,config = <&in_nopull>; + }; + }; + + i2c0_a_1_sleep: i2c0_a_1_sleep { + sleep_cfg1 { + pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c1 { + i2c1_b_2_default: i2c1_b_2_default { + default_mux { + function = "i2c1"; + groups = "i2c1_b_2"; + }; + default_cfg1 { + pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + ste,config = <&in_nopull>; + }; + }; + + i2c1_b_2_sleep: i2c1_b_2_sleep { + sleep_cfg1 { + pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c2 { + i2c2_b_1_default: i2c2_b_1_default { + default_mux { + function = "i2c2"; + groups = "i2c2_b_1"; + }; + default_cfg1 { + pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */ + ste,config = <&in_nopull>; + }; + }; + + i2c2_b_1_sleep: i2c2_b_1_sleep { + sleep_cfg1 { + pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + + i2c2_b_2_default: i2c2_b_2_default { + default_mux { + function = "i2c2"; + groups = "i2c2_b_2"; + }; + default_cfg1 { + pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + ste,config = <&in_nopull>; + }; + }; + + i2c2_b_2_sleep: i2c2_b_2_sleep { + sleep_cfg1 { + pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c3 { + i2c3_c_2_default: i2c3_c_2_default { + default_mux { + function = "i2c3"; + groups = "i2c3_c_2"; + }; + default_cfg1 { + pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + ste,config = <&in_nopull>; + }; + }; + + i2c3_c_2_sleep: i2c3_c_2_sleep { + sleep_cfg1 { + pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* + * Activating I2C4 will conflict with UART1 about the same pins so do not + * enable I2C4 and UART1 at the same time. + */ + i2c4 { + i2c4_b_1_default: i2c4_b_1_default { + default_mux { + function = "i2c4"; + groups = "i2c4_b_1"; + }; + default_cfg1 { + pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + ste,config = <&in_nopull>; + }; + }; + + i2c4_b_1_sleep: i2c4_b_1_sleep { + sleep_cfg1 { + pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* Settings for all MMC/SD/SDIO default and sleep states */ + sdi0 { + /* This is the external SD card slot, 4 bits wide */ + mc0_a_1_default: mc0_a_1_default { + default_mux { + function = "mc0"; + groups = "mc0_a_1"; + }; + default_cfg1 { + pins = + "GPIO18_AC2", /* CMDDIR */ + "GPIO19_AC1", /* DAT0DIR */ + "GPIO20_AB4"; /* DAT2DIR */ + ste,config = <&out_hi>; + }; + default_cfg2 { + pins = "GPIO22_AA3"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg4 { + pins = + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + mc0_a_1_sleep: mc0_a_1_sleep { + sleep_cfg1 { + pins = + "GPIO18_AC2", /* CMDDIR */ + "GPIO19_AC1", /* DAT0DIR */ + "GPIO20_AB4"; /* DAT2DIR */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg2 { + pins = + "GPIO22_AA3", /* FBCLK */ + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg3 { + pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + }; + + mc0_a_2_default: mc0_a_2_default { + default_mux { + function = "mc0"; + groups = "mc0_a_2"; + }; + default_cfg1 { + pins = "GPIO22_AA3"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg2 { + pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg3 { + pins = + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + mc0_a_2_sleep: mc0_a_2_sleep { + sleep_cfg1 { + pins = + "GPIO22_AA3", /* FBCLK */ + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + }; + }; + + sdi1 { + /* This is the WLAN SDIO 4 bits wide */ + mc1_a_1_default: mc1_a_1_default { + default_mux { + function = "mc1"; + groups = "mc1_a_1"; + }; + default_cfg1 { + pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + pins = "GPIO209_AG15"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + pins = + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + mc1_a_1_sleep: mc1_a_1_sleep { + sleep_cfg1 { + pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg2 { + pins = + "GPIO209_AG15", /* FBCLK */ + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + + mc1_a_2_default: mc1_a_2_default { + default_mux { + function = "mc1"; + groups = "mc1_a_2"; + }; + default_cfg1 { + pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + pins = + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + mc1_a_2_sleep: mc1_a_2_sleep { + sleep_cfg1 { + pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg2 { + pins = + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + sdi2 { + /* This is the eMMC 8 bits wide, usually PoP eMMC */ + mc2_a_1_default: mc2_a_1_default { + default_mux { + function = "mc2"; + groups = "mc2_a_1"; + }; + default_cfg1 { + pins = "GPIO128_A5"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + pins = + "GPIO129_B4", /* CMD */ + "GPIO131_A12", /* DAT0 */ + "GPIO132_C10", /* DAT1 */ + "GPIO133_B10", /* DAT2 */ + "GPIO134_B9", /* DAT3 */ + "GPIO135_A9", /* DAT4 */ + "GPIO136_C7", /* DAT5 */ + "GPIO137_A7", /* DAT6 */ + "GPIO138_C5"; /* DAT7 */ + ste,config = <&in_pu>; + }; + }; + + mc2_a_1_sleep: mc2_a_1_sleep { + sleep_cfg1 { + pins = "GPIO128_A5"; /* CLK */ + ste,config = <&out_lo_wkup_pdis>; + }; + sleep_cfg2 { + pins = + "GPIO130_C8", /* FBCLK */ + "GPIO129_B4"; /* CMD */ + ste,config = <&in_wkup_pdis_en>; + }; + sleep_cfg3 { + pins = + "GPIO131_A12", /* DAT0 */ + "GPIO132_C10", /* DAT1 */ + "GPIO133_B10", /* DAT2 */ + "GPIO134_B9", /* DAT3 */ + "GPIO135_A9", /* DAT4 */ + "GPIO136_C7", /* DAT5 */ + "GPIO137_A7", /* DAT6 */ + "GPIO138_C5"; /* DAT7 */ + ste,config = <&in_wkup_pdis>; + }; + }; + }; + + sdi4 { + /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ + mc4_a_1_default: mc4_a_1_default { + default_mux { + function = "mc4"; + groups = "mc4_a_1"; + }; + default_cfg1 { + pins = "GPIO203_AE23"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + pins = "GPIO202_AF25"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + pins = + "GPIO201_AF24", /* CMD */ + "GPIO200_AH26", /* DAT0 */ + "GPIO199_AH23", /* DAT1 */ + "GPIO198_AG25", /* DAT2 */ + "GPIO197_AH24", /* DAT3 */ + "GPIO207_AJ23", /* DAT4 */ + "GPIO206_AG24", /* DAT5 */ + "GPIO205_AG23", /* DAT6 */ + "GPIO204_AF23"; /* DAT7 */ + ste,config = <&in_pu>; + }; + }; + + mc4_a_1_sleep: mc4_a_1_sleep { + sleep_cfg1 { + pins = "GPIO203_AE23"; /* CLK */ + ste,config = <&out_lo_wkup_pdis>; + }; + sleep_cfg2 { + pins = + "GPIO202_AF25", /* FBCLK */ + "GPIO201_AF24", /* CMD */ + "GPIO200_AH26", /* DAT0 */ + "GPIO199_AH23", /* DAT1 */ + "GPIO198_AG25", /* DAT2 */ + "GPIO197_AH24", /* DAT3 */ + "GPIO207_AJ23", /* DAT4 */ + "GPIO206_AG24", /* DAT5 */ + "GPIO205_AG23", /* DAT6 */ + "GPIO204_AF23"; /* DAT7 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* + * Multi-rate serial ports (MSPs) - MSP3 output is internal and + * cannot be muxed onto any pins. + */ + msp0 { + msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default { + default_msp0_mux { + function = "msp0"; + groups = "msp0txrx_a_1", "msp0tfstck_a_1"; + }; + default_msp0_cfg { + pins = + "GPIO12_AC4", /* TXD */ + "GPIO15_AC3", /* RXD */ + "GPIO13_AF3", /* TFS */ + "GPIO14_AE3"; /* TCK */ + ste,config = <&in_nopull>; + }; + }; + }; + + msp1 { + msp1txrx_a_1_default: msp1txrx_a_1_default { + default_mux { + function = "msp1"; + groups = "msp1txrx_a_1", "msp1_a_1"; + }; + default_cfg1 { + pins = "GPIO33_AF2"; + ste,config = <&out_lo>; + }; + default_cfg2 { + pins = + "GPIO34_AE1", + "GPIO35_AE2", + "GPIO36_AG2"; + ste,config = <&in_nopull>; + }; + }; + }; + + msp2 { + msp2_a_1_default: msp2_a_1_default { + /* MSP2 usually used for HDMI audio */ + default_mux { + function = "msp2"; + groups = "msp2_a_1"; + }; + default_cfg1 { + pins = + "GPIO193_AH27", /* TXD */ + "GPIO194_AF27", /* TCK */ + "GPIO195_AG28"; /* TFS */ + ste,config = <&in_pd>; + }; + default_cfg2 { + pins = "GPIO196_AG26"; /* RXD */ + ste,config = <&out_lo>; + }; + }; + }; + + musb { + usb_a_1_default: usb_a_1_default { + default_mux { + function = "usb"; + groups = "usb_a_1"; + }; + default_cfg1 { + pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29", /* DIR */ + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&in_nopull>; + }; + default_cfg2 { + pins = "GPIO257_AE29"; /* STP */ + ste,config = <&out_hi>; + }; + }; + + usb_a_1_sleep: usb_a_1_sleep { + sleep_cfg1 { + pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29"; /* DIR */ + ste,config = <&slpm_wkup_pdis_en>; + }; + sleep_cfg2 { + pins = "GPIO257_AE29"; /* STP */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg3 { + pins = + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&slpm_in_wkup_pdis_en>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi new file mode 100644 index 000000000000..d5d88771ef97 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi @@ -0,0 +1,1238 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + /* This stablilizes the device enumeration */ + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "ste,dbx500-smp"; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + CPU0: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x300>; + clocks = <&prcmu_clk PRCMU_ARMSS>; + clock-names = "cpu"; + clock-latency = <20000>; + #cooling-cells = <2>; + }; + CPU1: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x301>; + }; + }; + + thermal-zones { + /* + * Thermal zone for the SoC, using the thermal sensor in the + * PRCMU for temperature and the cpufreq driver for passive + * cooling. + */ + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + /* + * This sensor fires interrupts to update the thermal + * zone, so no polling is needed. + */ + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu_alert: cpu-alert { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu-crit { + temperature = <85000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + trip = <&cpu_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <100>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500", "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + /* + * 640KB ESRAM (embedded static random access memory), divided + * into 5 banks of 128 KB each. This is a fast memory usually + * used by different accelerators. We group these according to + * their power domains: ESRAM0 (always on) ESRAM 1+2 and + * ESRAM 3+4. + */ + sram@40000000 { + /* The first (always on) ESRAM 0, 128 KB */ + compatible = "mmio-sram"; + reg = <0x40000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x20000>; + + sram@0 { + compatible = "stericsson,u8500-esram"; + reg = <0x0 0x10000>; + pool; + }; + lcpa: sram@10000 { + /* + * This eSRAM is used by the DMA40 DMA controller + * for Logical Channel Paramers (LCP), the address + * where these parameters are stored is called "LCPA". + * This is addressed directly by the driver so no + * pool is used. + */ + compatible = "stericsson,u8500-esram"; + label = "DMA40-LCPA"; + reg = <0x10000 0x800>; + }; + sram@10800 { + compatible = "stericsson,u8500-esram"; + reg = <0x10800 0xf800>; + pool; + }; + }; + sram@40020000 { + /* ESRAM 1+2, 256 KB */ + compatible = "mmio-sram"; + reg = <0x40020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x40000>; + }; + sram@40060000 { + /* ESRAM 3+4, 256 KB */ + compatible = "mmio-sram"; + reg = <0x40060000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40060000 0x40000>; + + lcla: sram@20000 { + /* + * This eSRAM is used by the DMA40 DMA controller + * for Logical Channel Logical Addresses (LCLA), the address + * where these parameters are stored is called "LCLA". + * This is addressed directly by the driver so no + * pool is used. + */ + compatible = "stericsson,u8500-esram"; + label = "DMA40-LCLA"; + reg = <0x20000 0x2000>; + }; + }; + + ptm@801ae000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801ae000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@801af000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801af000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + + funnel@801a6000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x801a6000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "atclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + tpiu@80190000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x80190000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + etb@801a4000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x801a4000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + scu@a0410000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + /* + * The backup RAM is used for retention during sleep + * and various things like spin tables + */ + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + pm_domains: pm_domains0 { + compatible = "stericsson,ux500-pm-domains"; + #power-domain-cells = <1>; + }; + + clocks { + compatible = "stericsson,u8500-clks"; + /* + * Registers for the CLKRST block on peripheral + * groups 1, 2, 3, 5, 6, + */ + reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, + <0x8000f000 0x1000>, <0xa03ff000 0x1000>, + <0xa03cf000 0x1000>; + + prcmu_clk: prcmu-clock { + #clock-cells = <1>; + }; + + prcc_pclk: prcc-periph-clock { + #clock-cells = <2>; + }; + + prcc_kclk: prcc-kernel-clock { + #clock-cells = <2>; + }; + + prcc_reset: prcc-reset-controller { + #reset-cells = <2>; + }; + + rtc_clk: rtc32k-clock { + #clock-cells = <0>; + }; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + + clkout_clk: clkout-clock { + /* Cell 1 id, cell 2 source, cell 3 div */ + #clock-cells = <3>; + }; + }; + + mtu@a03c6000 { + /* Nomadik System Timer */ + compatible = "st,nomadik-mtu"; + reg = <0xa03c6000 0x1000>; + interrupts = ; + + clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; + clock-names = "timclk", "apb_pclk"; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = ; + + clocks = <&smp_twd_clk>; + }; + + watchdog@a0410620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xa0410620 0x20>; + interrupts = ; + clocks = <&smp_twd_clk>; + }; + + rtc@80154000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x80154000 0x1000>; + interrupts = ; + + clocks = <&rtc_clk>; + clock-names = "apb_pclk"; + }; + + gpio0: gpio@8012e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + clocks = <&prcc_pclk 1 9>; + }; + + gpio1: gpio@8012e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 5>; + clocks = <&prcc_pclk 1 9>; + }; + + gpio2: gpio@8000e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio3: gpio@8000e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e080 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <3>; + gpio-ranges = <&pinctrl 0 96 2>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio4: gpio@8000e100 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e100 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <4>; + gpio-ranges = <&pinctrl 0 128 32>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio5: gpio@8000e180 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e180 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <5>; + gpio-ranges = <&pinctrl 0 160 12>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio6: gpio@8011e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <6>; + gpio-ranges = <&pinctrl 0 192 32>; + clocks = <&prcc_pclk 2 11>; + }; + + gpio7: gpio@8011e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e080 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <7>; + gpio-ranges = <&pinctrl 0 224 7>; + clocks = <&prcc_pclk 2 11>; + }; + + gpio8: gpio@a03fe000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0xa03fe000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <8>; + gpio-ranges = <&pinctrl 0 256 12>; + clocks = <&prcc_pclk 5 1>; + }; + + pinctrl: pinctrl { + compatible = "stericsson,db8500-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, + <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, + <&gpio8>; + prcm = <&prcmu>; + }; + + usb_per5@a03e0000 { + compatible = "stericsson,db8500-musb"; + reg = <0xa03e0000 0x10000>; + interrupts = ; + interrupt-names = "mc"; + + dr_mode = "otg"; + + dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ + <&dma 38 0 0x0>, /* Logical - MemToDev */ + <&dma 37 0 0x2>, /* Logical - DevToMem */ + <&dma 37 0 0x0>, /* Logical - MemToDev */ + <&dma 36 0 0x2>, /* Logical - DevToMem */ + <&dma 36 0 0x0>, /* Logical - MemToDev */ + <&dma 19 0 0x2>, /* Logical - DevToMem */ + <&dma 19 0 0x0>, /* Logical - MemToDev */ + <&dma 18 0 0x2>, /* Logical - DevToMem */ + <&dma 18 0 0x0>, /* Logical - MemToDev */ + <&dma 17 0 0x2>, /* Logical - DevToMem */ + <&dma 17 0 0x0>, /* Logical - MemToDev */ + <&dma 16 0 0x2>, /* Logical - DevToMem */ + <&dma 16 0 0x0>, /* Logical - MemToDev */ + <&dma 39 0 0x2>, /* Logical - DevToMem */ + <&dma 39 0 0x0>; /* Logical - MemToDev */ + + dma-names = "iep_1_9", "oep_1_9", + "iep_2_10", "oep_2_10", + "iep_3_11", "oep_3_11", + "iep_4_12", "oep_4_12", + "iep_5_13", "oep_5_13", + "iep_6_14", "oep_6_14", + "iep_7_15", "oep_7_15", + "iep_8", "oep_8"; + + clocks = <&prcc_pclk 5 0>; + }; + + dma: dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", "stericsson,dma40"; + reg = <0x801C0000 0x1000>; + reg-names = "base"; + interrupts = ; + sram = <&lcpa>, <&lcla>; + + #dma-cells = <3>; + memcpy-channels = <56 57 58 59 60>; + + clocks = <&prcmu_clk PRCMU_DMACLK>; + }; + + prcmu: prcmu@80157000 { + compatible = "stericsson,db8500-prcmu", "syscon"; + reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + prcmu-timer-4@80157450 { + compatible = "stericsson,db8500-prcmu-timer-4"; + reg = <0x80157450 0xC>; + }; + + thermal: thermal@801573c0 { + compatible = "stericsson,db8500-thermal"; + reg = <0x801573c0 0x40>; + interrupt-parent = <&prcmu>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; + #thermal-sensor-cells = <0>; + }; + + db8500-prcmu-regulators { + compatible = "stericsson,db8500-prcmu-regulator"; + + // DB8500_REGULATOR_VAPE + db8500_vape_reg: db8500_vape { + regulator-always-on; + }; + + // DB8500_REGULATOR_VARM + db8500_varm_reg: db8500_varm { + }; + + // DB8500_REGULATOR_VMODEM + db8500_vmodem_reg: db8500_vmodem { + }; + + // DB8500_REGULATOR_VPLL + db8500_vpll_reg: db8500_vpll { + }; + + // DB8500_REGULATOR_VSMPS1 + db8500_vsmps1_reg: db8500_vsmps1 { + }; + + // DB8500_REGULATOR_VSMPS2 + db8500_vsmps2_reg: db8500_vsmps2 { + }; + + // DB8500_REGULATOR_VSMPS3 + db8500_vsmps3_reg: db8500_vsmps3 { + }; + + // DB8500_REGULATOR_VRF1 + db8500_vrf1_reg: db8500_vrf1 { + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSP + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSPRET + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + }; + + // DB8500_REGULATOR_SWITCH_SVAPIPE + db8500_sva_pipe_reg: db8500_sva_pipe { + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSP + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSPRET + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + }; + + // DB8500_REGULATOR_SWITCH_SIAPIPE + db8500_sia_pipe_reg: db8500_sia_pipe { + }; + + // DB8500_REGULATOR_SWITCH_SGA + db8500_sga_reg: db8500_sga { + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_B2R2_MCDE + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12 + db8500_esram12_reg: db8500_esram12 { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12RET + db8500_esram12_ret_reg: db8500_esram12_ret { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34 + db8500_esram34_reg: db8500_esram34 { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34RET + db8500_esram34_ret_reg: db8500_esram34_ret { + }; + }; + }; + + i2c0: i2c@80004000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80004000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; + + status = "disabled"; + }; + + i2c1: i2c@80122000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80122000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; + + status = "disabled"; + }; + + i2c2: i2c@80128000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80128000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; + + status = "disabled"; + }; + + i2c3: i2c@80110000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80110000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; + + status = "disabled"; + }; + + i2c4: i2c@8012a000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x8012a000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; + + status = "disabled"; + }; + + ssp0: spi@80002000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80002000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; + clock-names = "sspclk", "apb_pclk"; + dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ + <&dma 8 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; + + status = "disabled"; + }; + + ssp1: spi@80003000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80003000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; + clock-names = "sspclk", "apb_pclk"; + dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ + <&dma 9 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; + + status = "disabled"; + }; + + spi0: spi@8011a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8011a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; + clock-names = "sspclk", "apb_pclk"; + dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ + <&dma 0 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi1: spi@80112000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80112000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; + clock-names = "sspclk", "apb_pclk"; + dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ + <&dma 35 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi2: spi@80111000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80111000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; + clock-names = "sspclk", "apb_pclk"; + dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ + <&dma 33 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi3: spi@80129000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80129000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; + clock-names = "sspclk", "apb_pclk"; + dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ + <&dma 40 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; + + status = "disabled"; + }; + + serial0: serial@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = ; + + dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ + <&dma 13 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; + clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; + + status = "disabled"; + }; + + serial1: serial@80121000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80121000 0x1000>; + interrupts = ; + + dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ + <&dma 12 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; + clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; + + status = "disabled"; + }; + + serial2: serial@80007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80007000 0x1000>; + interrupts = ; + + dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ + <&dma 11 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; + clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; + + status = "disabled"; + }; + + mmc@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = ; + + dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ + <&dma 29 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; + + status = "disabled"; + }; + + mmc@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = ; + + dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ + <&dma 32 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; + + status = "disabled"; + }; + + mmc@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = ; + + dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ + <&dma 28 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; + + status = "disabled"; + }; + + mmc@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = ; + + dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ + <&dma 41 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; + + status = "disabled"; + }; + + mmc@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = ; + + dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ + <&dma 42 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; + + status = "disabled"; + }; + + mmc@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80008000 0x1000>; + interrupts = ; + + dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ + <&dma 43 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; + + status = "disabled"; + }; + + sound { + compatible = "stericsson,snd-soc-mop500"; + stericsson,cpu-dai = <&msp1 &msp3>; + }; + + msp0: msp@80123000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80123000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; + clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; + + status = "disabled"; + }; + + msp1: msp@80124000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80124000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + /* This DMA channel only exist on DB8500 v1 */ + dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "tx"; + + clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; + clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; + + status = "disabled"; + }; + + // HDMI sound + msp2: msp@80117000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80117000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev + HighPrio - Fixed */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; + clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; + + status = "disabled"; + }; + + msp3: msp@80125000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80125000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + /* This DMA channel only exist on DB8500 v2 */ + dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ + dma-names = "rx"; + + clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; + clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; + + status = "disabled"; + }; + + external-bus@50000000 { + compatible = "simple-bus"; + reg = <0x50000000 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000000>; + status = "disabled"; + }; + + gpu@a0300000 { + /* + * This block is referred to as "Smart Graphics Adapter SGA500" + * in documentation but is in practice a pretty straight-forward + * MALI-400 GPU block. + */ + compatible = "stericsson,db8500-mali", "arm,mali-400"; + reg = <0xa0300000 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "combined"; + clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; + clock-names = "bus", "core"; + mali-supply = <&db8500_sga_reg>; + power-domains = <&pm_domains DOMAIN_VAPE>; + }; + + mcde@a0350000 { + compatible = "ste,mcde"; + reg = <0xa0350000 0x1000>; + interrupts = ; + epod-supply = <&db8500_b2r2_mcde_reg>; + clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ + <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ + <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ + clock-names = "mcde", "lcd", "hdmi"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dsi0: dsi@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi1: dsi@a0352000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0352000 0x1000>; + clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi2: dsi@a0353000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0353000 0x1000>; + /* This DSI port only has the Low Power / Energy Save clock */ + clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; + clock-names = "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cryp@a03cb000 { + compatible = "stericsson,ux500-cryp"; + reg = <0xa03cb000 0x1000>; + interrupts = ; + clocks = <&prcc_pclk 6 1>; + power-domains = <&pm_domains DOMAIN_VAPE>; + }; + + hash@a03c2000 { + compatible = "stericsson,ux500-hash"; + reg = <0xa03c2000 0x1000>; + clocks = <&prcc_pclk 6 2>; + power-domains = <&pm_domains DOMAIN_VAPE>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href-ab8500.dtsi b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi new file mode 100644 index 000000000000..e1de9d389a01 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Linaro Ltd. + */ + +#include "ste-ab8500.dtsi" + +/ { + soc { + prcmu@80157000 { + ab8500 { + gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_default_mode>, + <&gpio4_default_mode>, + <&gpio10_default_mode>, + <&gpio11_default_mode>, + <&gpio12_default_mode>, + <&gpio13_default_mode>, + <&gpio16_default_mode>, + <&gpio24_default_mode>, + <&gpio25_default_mode>, + <&gpio36_default_mode>, + <&gpio37_default_mode>, + <&gpio38_default_mode>, + <&gpio39_default_mode>, + <&gpio42_default_mode>, + <&gpio26_default_mode>, + <&gpio35_default_mode>, + <&ycbcr_default_mode>, + <&pwm_default_mode>, + <&adi1_default_mode>, + <&usbuicc_default_mode>, + <&dmic_default_mode>, + <&extcpena_default_mode>, + <&modsclsda_default_mode>; + + /* + * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 + * are muxed in as GPIO, and configured as INPUT PULL DOWN + */ + gpio2 { + gpio2_default_mode: gpio2_default { + default_mux { + function = "gpio"; + groups = "gpio2_a_1"; + }; + default_cfg { + pins = "GPIO2_T9"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio4 { + gpio4_default_mode: gpio4_default { + default_mux { + function = "gpio"; + groups = "gpio4_a_1"; + }; + default_cfg { + pins = "GPIO4_W2"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio10 { + gpio10_default_mode: gpio10_default { + default_mux { + function = "gpio"; + groups = "gpio10_d_1"; + }; + default_cfg { + pins = "GPIO10_U17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio11 { + gpio11_default_mode: gpio11_default { + default_mux { + function = "gpio"; + groups = "gpio11_d_1"; + }; + default_cfg { + pins = "GPIO11_AA18"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio12 { + gpio12_default_mode: gpio12_default { + default_mux { + function = "gpio"; + groups = "gpio12_d_1"; + }; + default_cfg { + pins = "GPIO12_U16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio13 { + gpio13_default_mode: gpio13_default { + default_mux { + function = "gpio"; + groups = "gpio13_d_1"; + }; + default_cfg { + pins = "GPIO13_W17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio16 { + gpio16_default_mode: gpio16_default { + default_mux { + function = "gpio"; + groups = "gpio16_a_1"; + }; + default_cfg { + pins = "GPIO16_F15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio24 { + gpio24_default_mode: gpio24_default { + default_mux { + function = "gpio"; + groups = "gpio24_a_1"; + }; + default_cfg { + pins = "GPIO24_T14"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio25 { + gpio25_default_mode: gpio25_default { + default_mux { + function = "gpio"; + groups = "gpio25_a_1"; + }; + default_cfg { + pins = "GPIO25_R16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio36 { + gpio36_default_mode: gpio36_default { + default_mux { + function = "gpio"; + groups = "gpio36_a_1"; + }; + default_cfg { + pins = "GPIO36_A17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio37 { + gpio37_default_mode: gpio37_default { + default_mux { + function = "gpio"; + groups = "gpio37_a_1"; + }; + default_cfg { + pins = "GPIO37_E15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio38 { + gpio38_default_mode: gpio38_default { + default_mux { + function = "gpio"; + groups = "gpio38_a_1"; + }; + default_cfg { + pins = "GPIO38_C17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio39 { + gpio39_default_mode: gpio39_default { + default_mux { + function = "gpio"; + groups = "gpio39_a_1"; + }; + default_cfg { + pins = "GPIO39_E16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio42 { + gpio42_default_mode: gpio42_default { + default_mux { + function = "gpio"; + groups = "gpio42_a_1"; + }; + default_cfg { + pins = "GPIO42_U2"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW + */ + gpio26 { + gpio26_default_mode: gpio26_default { + default_mux { + function = "gpio"; + groups = "gpio26_d_1"; + }; + default_cfg { + pins = "GPIO26_M16"; + output-low; + }; + }; + }; + gpio35 { + gpio35_default_mode: gpio35_default { + default_mux { + function = "gpio"; + groups = "gpio35_d_1"; + }; + default_cfg { + pins = "GPIO35_W15"; + output-low; + }; + }; + }; + /* + * This sets up the YCBCR connector pins, i.e. analog video out. + * Set as input with no bias. + */ + ycbcr { + ycbcr_default_mode: ycbcr_default { + default_mux { + function = "ycbcr"; + groups = "ycbcr0123_d_1"; + }; + default_cfg { + pins = "GPIO6_Y18", + "GPIO7_AA20", + "GPIO8_W18", + "GPIO9_AA19"; + input-enable; + bias-disable; + }; + }; + }; + /* This sets up the PWM pins 14 and 15 */ + pwm { + pwm_default_mode: pwm_default { + default_mux { + function = "pwmout"; + groups = "pwmout1_d_1", "pwmout2_d_1"; + }; + default_cfg { + pins = "GPIO14_F14", + "GPIO15_B17"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up audio interface 1 */ + adi1 { + adi1_default_mode: adi1_default { + default_mux { + function = "adi1"; + groups = "adi1_d_1"; + }; + default_cfg { + pins = "GPIO17_P5", + "GPIO18_R5", + "GPIO19_U5", + "GPIO20_T5"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up the USB UICC pins */ + usbuicc { + usbuicc_default_mode: usbuicc_default { + default_mux { + function = "usbuicc"; + groups = "usbuicc_d_1"; + }; + default_cfg { + pins = "GPIO21_H19", + "GPIO22_G20", + "GPIO23_G19"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up the microphone pins */ + dmic { + dmic_default_mode: dmic_default { + default_mux { + function = "dmic"; + groups = "dmic12_d_1", + "dmic34_d_1", + "dmic56_d_1"; + }; + default_cfg { + pins = "GPIO27_J6", + "GPIO28_K6", + "GPIO29_G6", + "GPIO30_H6", + "GPIO31_F5", + "GPIO32_G5"; + input-enable; + bias-pull-down; + }; + }; + }; + extcpena { + extcpena_default_mode: extcpena_default { + default_mux { + function = "extcpena"; + groups = "extcpena_d_1"; + }; + default_cfg { + pins = "GPIO34_R17"; + input-enable; + bias-pull-down; + }; + }; + }; + /* Modem I2C setup (SCL and SDA pins) */ + modsclsda { + modsclsda_default_mode: modsclsda_default { + default_mux { + function = "modsclsda"; + groups = "modsclsda_d_1"; + }; + default_cfg { + pins = "GPIO40_T19", + "GPIO41_U19"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Clock output pins associated with regulators. + */ + sysclkreq2 { + sysclkreq2_default_mode: sysclkreq2_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq2_d_1"; + }; + default_cfg { + pins = "GPIO1_T10"; + input-enable; + bias-disable; + }; + }; + sysclkreq2_sleep_mode: sysclkreq2_sleep { + default_mux { + function = "gpio"; + groups = "gpio1_a_1"; + }; + default_cfg { + pins = "GPIO1_T10"; + input-enable; + bias-pull-down; + }; + }; + }; + sysclkreq4 { + sysclkreq4_default_mode: sysclkreq4_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq4_d_1"; + }; + default_cfg { + pins = "GPIO3_U9"; + input-enable; + bias-disable; + }; + }; + sysclkreq4_sleep_mode: sysclkreq4_sleep { + default_mux { + function = "gpio"; + groups = "gpio3_a_1"; + }; + default_cfg { + pins = "GPIO3_U9"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + /* + * Charging is not working on the HREF unless an actual battery is + * mounted, most HREFs have a DC cable in to the "battery power" + * which means this will only be cofusing. So do not enable charging + * of the HREFs. + */ + ab8500_fg { + status = "disabled"; + }; + ab8500_btemp { + status = "disabled"; + }; + ab8500_charger { + status = "disabled"; + }; + ab8500_chargalg { + status = "disabled"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi new file mode 100644 index 000000000000..434fa6baf71f --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Linaro Ltd. + */ + +#include "ste-dbx5x0-pinctrl.dtsi" + +/ { + soc { + pinctrl { + /* Settings for all SPI default and sleep states */ + spi2 { + spi2_default_mode: spi_default { + default_mux { + function = "spi2"; + groups = "spi2_oc1_2"; + }; + default_cfg1 { + pins = "GPIO216_AG12"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + default_cfg2 { + pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&in_pd>; + }; + default_cfg3 { + pins = + "GPIO215_AH13", /* TXD */ + "GPIO217_AH12"; /* CLK */ + ste,config = <&out_lo>; + }; + }; + + spi2_idle_mode: spi_idle { + /* + * The idle mode is basically sleep mode sans wakeups. Also + * note that we have muxes the pins off the function here + * as we do not state any muxing. + */ + idle_cfg1 { + pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_pdis>; + }; + idle_cfg2 { + pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_pdis>; + }; + idle_cfg3 { + pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_pdis>; + }; + }; + + spi2_sleep_mode: spi_sleep { + sleep_cfg1 { + pins = + "GPIO216_AG12", /* FRM */ + "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg3 { + pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_wkup_pdis>; + }; + }; + }; + + mcde { + lcd_default_mode: lcd_default { + default_mux1 { + /* Mux in VSI0 and all the data lines */ + function = "lcd"; + groups = + "lcdvsi0_a_1", /* VSI0 for LCD */ + "lcd_d0_d7_a_1", /* Data lines */ + "lcdvsi1_a_1"; /* VSI1 for HDMI */ + }; + default_mux2 { + function = "lcda"; + groups = + "lcdaclk_b_1"; /* Clock line for TV-out */ + }; + default_cfg1 { + pins = + "GPIO68_E1", /* VSI0 */ + "GPIO69_E2"; /* VSI1 */ + ste,config = <&in_pu>; + }; + }; + lcd_sleep_mode: lcd_sleep { + sleep_cfg1 { + pins = "GPIO69_E2"; /* VSI1 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + ske { + /* SKE keys on position 2 in an 8x8 matrix */ + ske_kpa2_default_mode: ske_kpa2_default { + default_mux { + function = "kp"; + groups = "kp_a_2"; + }; + default_cfg1 { + pins = + "GPIO153_B17", /* I7 */ + "GPIO154_C16", /* I6 */ + "GPIO155_C19", /* I5 */ + "GPIO156_C17", /* I4 */ + "GPIO161_D21", /* I3 */ + "GPIO162_D20", /* I2 */ + "GPIO163_C20", /* I1 */ + "GPIO164_B21"; /* I0 */ + ste,config = <&in_pd>; + }; + default_cfg2 { + pins = + "GPIO157_A18", /* O7 */ + "GPIO158_C18", /* O6 */ + "GPIO159_B19", /* O5 */ + "GPIO160_B20", /* O4 */ + "GPIO165_C21", /* O3 */ + "GPIO166_A22", /* O2 */ + "GPIO167_B24", /* O1 */ + "GPIO168_C22"; /* O0 */ + ste,config = <&out_lo>; + }; + }; + ske_kpa2_sleep_mode: ske_kpa2_sleep { + sleep_cfg1 { + pins = + "GPIO153_B17", /* I7 */ + "GPIO154_C16", /* I6 */ + "GPIO155_C19", /* I5 */ + "GPIO156_C17", /* I4 */ + "GPIO161_D21", /* I3 */ + "GPIO162_D20", /* I2 */ + "GPIO163_C20", /* I1 */ + "GPIO164_B21"; /* I0 */ + ste,config = <&slpm_in_pu_wkup_pdis_en>; + }; + sleep_cfg2 { + pins = + "GPIO157_A18", /* O7 */ + "GPIO158_C18", /* O6 */ + "GPIO159_B19", /* O5 */ + "GPIO160_B20", /* O4 */ + "GPIO165_C21", /* O3 */ + "GPIO166_A22", /* O2 */ + "GPIO167_B24", /* O1 */ + "GPIO168_C22"; /* O0 */ + ste,config = <&slpm_out_lo_pdis>; + }; + }; + /* + * SKE keys on position 1 and "other C1" combi giving + * six rows of six keys. + */ + ske_kpaoc1_default_mode: ske_kpaoc1_default { + default_mux { + function = "kp"; + groups = "kp_a_1", "kp_oc1_1"; + }; + default_cfg1 { + pins = + "GPIO91_B6", /* KP_O0 */ + "GPIO90_A3", /* KP_O1 */ + "GPIO87_B3", /* KP_O2 */ + "GPIO86_C6", /* KP_O3 */ + "GPIO96_D8", /* KP_O6 */ + "GPIO94_D7"; /* KP_O7 */ + ste,config = <&out_lo>; + }; + default_cfg2 { + pins = + "GPIO93_B7", /* KP_I0 */ + "GPIO92_D6", /* KP_I1 */ + "GPIO89_E6", /* KP_I2 */ + "GPIO88_C4", /* KP_I3 */ + "GPIO97_D9", /* KP_I6 */ + "GPIO95_E8"; /* KP_I7 */ + ste,config = <&in_pu>; + }; + }; + }; + + wlan { + wlan_default_mode: wlan_default { + /* + * Activate this mode with the WLAN chip. + * These are plain GPIO pins used by WLAN + */ + default_cfg1 { + pins = + "GPIO226_AF8", /* WLAN_PMU_EN */ + "GPIO85_D5"; /* WLAN_ENA */ + ste,config = <&gpio_out_lo>; + }; + default_cfg2 { + pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href-stuib.dtsi b/arch/arm/boot/dts/st/ste-href-stuib.dtsi new file mode 100644 index 000000000000..79c2be36acae --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href-stuib.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + */ + +#include + +/ { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; + + button@139 { + /* Proximity sensor */ + gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; + linux,code = <11>; /* SW_FRONT_PROXIMITY */ + label = "SFH7741 Proximity Sensor"; + }; + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + + soc { + i2c@80004000 { + stmpe1601: port-expander@40 { + compatible = "st,stmpe1601"; + reg = <0x40>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio6>; + vcc-supply = <&db8500_vsmps2_reg>; + vio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe_stuib_mode>; + + wakeup-source; + st,autosleep-timeout = <1024>; + + keyboard-controller { + compatible = "st,stmpe-keypad"; + + debounce-interval = <64>; + st,scan-count = <8>; + st,no-autorepeat; + + linux,keymap = <0x205006b + 0x4010074 + 0x3050072 + 0x1030004 + 0x502006a + 0x500000a + 0x5008b + 0x706001c + 0x405000b + 0x6070003 + 0x3040067 + 0x303006c + 0x60400e7 + 0x602009e + 0x4020073 + 0x5050002 + 0x4030069 + 0x3020008>; + }; + }; + }; + + /* Sensors mounted on this board variant */ + i2c@80128000 { + lis331dl@1c { + /* Accelerometer */ + compatible = "st,lis331dl-accel"; + st,drdy-int-pin = <1>; + reg = <0x1c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_stuib_mode>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>, + <19 IRQ_TYPE_EDGE_RISING>; + }; + ak8974@f { + /* Magnetometer */ + compatible = "asahi-kasei,ak8974"; + reg = <0x0f>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_stuib_mode>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c@80110000 { + bu21013_tp@5c { + compatible = "rohm,bu21013_tp"; + reg = <0x5c>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; + pinctrl-names = "default"; + pinctrl-0 = <&touch_rohm_mode>; + }; + + bu21013_tp@5d { + compatible = "rohm,bu21013_tp"; + reg = <0x5d>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; + pinctrl-names = "default"; + pinctrl-0 = <&touch_rohm_mode>; + }; + }; + + pinctrl { + /* Pull up this GPIO pin */ + stmpe { + stmpe_stuib_mode: stmpe_stuib { + stuib_cfg { + ste,pins = "GPIO218_AH11"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + prox { + prox_stuib_mode: prox_stuib { + stuib_cfg { + pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + hall { + hall_stuib_mode: stuib_tvk { + stuib_cfg { + pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + accelerometer { + accel_stuib_mode: accel_stuib { + /* Accelerometer interrupt lines 1 & 2 */ + stuib_cfg { + pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_stuib_mode: magneto_stuib { + /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ + stuib_cfg1 { + pins = "GPIO31_V3"; + ste,config = <&gpio_in_pu>; + }; + stuib_cfg2 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + touch { + touch_rohm_mode: touch_rohm { + /* + * ROHM touch screen uses GPIO 143 for + * RST1, GPIO 146 for RST2 and + * GPIO 67 for interrupts. Pull-up + * the IRQ line and drive both + * reset signals low. + */ + stuib_cfg1 { + pins = "GPIO143_D12", "GPIO146_D13"; + ste,config = <&gpio_out_lo>; + }; + stuib_cfg2 { + pins = "GPIO67_G2"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; + + mcde@a0350000 { + status = "okay"; + + dsi@a0351000 { + panel { + compatible = "samsung,s6d16d0"; + reg = <0>; + vdd1-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi new file mode 100644 index 000000000000..37e59403c01f --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree for the TVK1281618 R2 user interface board (UIB) + */ + +#include +#include + +/ { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; + + button@139 { + /* Proximity sensor */ + gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; + linux,code = <11>; /* SW_FRONT_PROXIMITY */ + label = "SFH7741 Proximity Sensor"; + }; + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + + soc { + i2c@80004000 { + tc35893@44 { + compatible = "toshiba,tc35893"; + reg = <0x44>; + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35893_tvk_mode>; + + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + + tc3589x_gpio { + compatible = "toshiba,tc3589x-gpio"; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + tc3589x_keypad { + compatible = "toshiba,tc3589x-keypad"; + interrupts = <6>; + debounce-delay-ms = <4>; + keypad,num-columns = <8>; + keypad,num-rows = <8>; + linux,no-autorepeat; + wakeup-source; + linux,keymap = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + }; + + i2c@80128000 { + accelerometer@18 { + /* Accelerometer */ + compatible = "st,lsm303dlh-accel"; + st,drdy-int-pin = <1>; + drive-open-drain; + reg = <0x18>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_tvk_mode>; + /* + * These interrupts cannot be used: the other component + * ST-Micro L3D4200D gyro that is connected to the same lines + * cannot set its DRDY line to open drain, so it cannot be + * shared with other peripherals. The should be defined for + * the falling edge if they could be wired together. + * + * interrupts-extended = + * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, + * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; + */ + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + magnetometer@1e { + /* Magnetometer */ + compatible = "st,lsm303dlh-magn"; + reg = <0x1e>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + /* + * These interrupts cannot be used: the other component + * ST-Micro L3D4200D gyro that is connected to the same lines + * cannot set its DRDY line to open drain, so it cannot be + * shared with other peripherals. The should be defined for + * the falling edge if they could be wired together. + * + * interrupts-extended = + * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, + * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; + */ + }; + accelerometer@1c { + /* Accelerometer */ + compatible = "st,lis331dl-accel"; + st,drdy-int-pin = <1>; + reg = <0x1c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_tvk_mode>; + interrupt-parent = <&gpio2>; + /* INT2 would need to be open drain */ + interrupts = <18 IRQ_TYPE_EDGE_RISING>, + <19 IRQ_TYPE_EDGE_RISING>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + magnetometer@f { + /* Magnetometer */ + compatible = "asahi-kasei,ak8974"; + reg = <0x0f>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gyro_magn_tvk_mode>; + /* + * These interrupts cannot be used: the other component + * ST-Micro L3D4200D gyro that is connected to the same lines + * cannot set its DRDY line to open drain, so it cannot be + * shared with other peripherals. The should be defined for + * the falling edge if they could be wired together. + * + * interrupts-extended = + * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, + * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>; + */ + }; + gyroscope@68 { + /* Gyroscope */ + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x68>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gyro_magn_tvk_mode>; + interrupts-extended = + <&gpio1 0 IRQ_TYPE_EDGE_RISING>, + <&gpio0 31 IRQ_TYPE_EDGE_RISING>; + }; + pressure@5c { + /* Barometer/pressure sensor */ + compatible = "st,lps001wp-press"; + reg = <0x5c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + }; + i2c@80110000 { + synaptics@4b { + /* Synaptics RMI4 TM1217 touchscreen */ + compatible = "syna,rmi4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4b>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&synaptics_tvk_mode>; + interrupt-parent = <&gpio2>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep = <1>; + }; + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + /* This is a landscape display */ + touchscreen-swapped-x-y; + }; + }; + }; + mcde@a0350000 { + status = "okay"; + + dsi@a0351000 { + panel { + compatible = "samsung,s6d16d0"; + reg = <0>; + vdd1-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + }; + pinctrl { + prox { + prox_tvk_mode: prox_tvk { + tvk_cfg { + pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + hall { + hall_tvk_mode: hall_tvk { + tvk_cfg { + pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + tc35893 { + /* IRQ from the TC35893 */ + tc35893_tvk_mode: tc35893_tvk { + tvk_cfg { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + accelerometer { + accel_tvk_mode: accel_tvk { + /* Accelerometer interrupt lines 1 & 2 */ + tvk_cfg { + pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + gyroscope { + /* + * These lines are shared between Gyroscope l3g400dh + * and AK8974 magnetometer. + */ + gyro_magn_tvk_mode: gyro_magn_tvk { + /* GPIO 31 used for INT pull down the line */ + tvk_cfg1 { + pins = "GPIO31_V3"; + ste,config = <&gpio_in_pd>; + }; + /* GPIO 32 used for DRDY, pull this down */ + tvk_cfg2 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + synaptics { + synaptics_tvk_mode: synaptics_tvk { + /* Touchscreen uses GPIO 84 */ + tvk_cfg1 { + pins = "GPIO84_C2"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi new file mode 100644 index 000000000000..00ce9d79f540 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree for the TVK1281618 R3 user interface board (UIB) + * also known as the "CYTTSP board" + */ + +#include +#include + +/ { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&hall_tvk_mode>; + + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + + soc { + i2c@80004000 { + tc35893@44 { + compatible = "toshiba,tc35893"; + reg = <0x44>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35893_tvk_mode>; + + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + + tc3589x_gpio { + compatible = "toshiba,tc3589x-gpio"; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + tc3589x_keypad { + compatible = "toshiba,tc3589x-keypad"; + interrupts = <6>; + debounce-delay-ms = <4>; + keypad,num-columns = <8>; + keypad,num-rows = <8>; + linux,no-autorepeat; + wakeup-source; + linux,keymap = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + }; + + i2c@80128000 { + accelerometer@19 { + compatible = "st,lsm303dlhc-accel"; + st,drdy-int-pin = <1>; + reg = <0x19>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>, + <19 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_tvk_mode>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + magnetometer@1e { + compatible = "st,lsm303dlm-magn"; + reg = <0x1e>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + // This interrupt is not properly working with the driver + // interrupt-parent = <&gpio1>; + // interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&magn_tvk_mode>; + }; + gyroscope@68 { + /* Gyroscope */ + compatible = "st,l3g4200d-gyro"; + reg = <0x68>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + pressure@5c { + /* Barometer/pressure sensor */ + compatible = "st,lps001wp-press"; + reg = <0x5c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + }; + + spi@80111000 { + num-cs = <1>; + cs-gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_default_mode>; + status = "okay"; + + touchscreen@0 { + compatible = "cypress,cy8ctma340"; + /* + * Actually the max frequency is 6 MHz, but over 2 MHz the + * data rate needs to be restricted to max 2Mbps which the + * SPI framework cannot handle. + */ + spi-max-frequency = <2000000>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + vcpin-supply = <&ab8500_ldo_aux1_reg>; + vdd-supply = <&db8500_vsmps2_reg>; + reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <480>; + touchscreen-size-y = <854>; + active-interval-ms = <0>; + touch-timeout-ms = <255>; + lowpower-interval-ms = <10>; + bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; + pinctrl-names = "default"; + pinctrl-0 = <&cyttsp_tvk_mode>; + }; + }; + + mcde@a0350000 { + status = "okay"; + + dsi@a0351000 { + panel { + compatible = "sony,acx424akp"; + reg = <0>; + vddi-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + }; + + pinctrl { + hall { + hall_tvk_mode: hall_tvk { + tvk_cfg { + pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + tc35893 { + /* IRQ from the TC35893 */ + tc35893_tvk_mode: tc35893_tvk { + tvk_cfg { + pins = "GPIO64_F3"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + accelerometer { + accel_tvk_mode: accel_tvk { + /* Accelerometer interrupt lines 1 & 2 */ + tvk_cfg { + pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + magnetometer { + magn_tvk_mode: magn_tvk { + /* GPIO 32 used for DRDY, pull this down */ + tvk_cfg { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + cyttsp { + cyttsp_tvk_mode: cyttsp_tvk { + /* Touchscreen uses GPIO84 for IRQ */ + tvk_cfg1 { + pins = "GPIO84_C2"; + ste,config = <&gpio_in_pu>; + }; + /* GPIO143 is reset */ + tvk_cfg2 { + pins = "GPIO143_D12"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href.dtsi b/arch/arm/boot/dts/st/ste-href.dtsi new file mode 100644 index 000000000000..13b11dbeba1c --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href.dtsi @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + */ + +#include +#include +#include "ste-href-family-pinctrl.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + battery: battery { + compatible = "simple-battery"; + battery-type = "lithium-ion-polymer"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + soc { + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + }; + + /* This UART is unused and thus left disabled */ + serial@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + }; + + serial@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + status = "okay"; + }; + + i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + status = "okay"; + }; + + i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_b_2_default>; + pinctrl-1 = <&i2c1_b_2_sleep>; + status = "okay"; + }; + + i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + status = "okay"; + lp5521@33 { + compatible = "national,lp5521"; + reg = <0x33>; + label = "lp5521_pri"; + clock-mode = /bits/ 8 <2>; + #address-cells = <1>; + #size-cells = <0>; + led@0 { + reg = <0>; + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + color = ; + linux,default-trigger = "heartbeat"; + }; + led@1 { + reg = <1>; + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + color = ; + }; + led@2 { + reg = <2>; + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + color = ; + }; + }; + lp5521@34 { + compatible = "national,lp5521"; + reg = <0x34>; + label = "lp5521_sec"; + clock-mode = /bits/ 8 <2>; + #address-cells = <1>; + #size-cells = <0>; + led@0 { + reg = <0>; + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + color = ; + }; + led@1 { + reg = <1>; + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + color = ; + }; + led@2 { + reg = <2>; + led-cur = /bits/ 8 <0x2f>; + max-cur = /bits/ 8 <0x5f>; + color = ; + }; + }; + bh1780@29 { + compatible = "rohm,bh1780gli"; + reg = <0x29>; + }; + }; + + i2c@80110000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + status = "okay"; + }; + + // External Micro SD slot + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + full-pwr-cycle; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-cmd; + st,sig-pin-fbclk; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&vmmci>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; + pinctrl-1 = <&mc0_a_1_sleep>; + + status = "okay"; + }; + + // WLAN SDIO channel + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + non-removable; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_1_default>; + pinctrl-1 = <&mc1_a_1_sleep>; + + status = "okay"; + }; + + // PoP:ed eMMC + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + no-sdio; + no-sd; + vmmc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + + status = "okay"; + }; + + // On-board eMMC + mmc@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + no-sdio; + no-sd; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc4_a_1_default>; + pinctrl-1 = <&mc4_a_1_sleep>; + + status = "okay"; + }; + + msp0: msp@80123000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp0txrxtfstck_a_1_default>; + status = "okay"; + }; + + msp1: msp@80124000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp1txrx_a_1_default>; + status = "okay"; + }; + + msp2: msp@80117000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp2_a_1_default>; + }; + + msp3: msp@80125000 { + status = "okay"; + }; + + prcmu@80157000 { + ab8500 { + gpio { + }; + + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + regulator { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; + + pinctrl { + sdi0 { + sdi0_default_mode: sdi0_default { + /* Some boards set additional settings here */ + }; + }; + }; + + mcde@a0350000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_default_mode>; + pinctrl-1 = <&lcd_sleep_mode>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-href520-tvk.dts b/arch/arm/boot/dts/st/ste-href520-tvk.dts new file mode 100644 index 000000000000..4201547c5988 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-href520-tvk.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree for the HREF520 version with the TVK1281618 R3 UIB + */ + +/dts-v1/; +#include "ste-db8520.dtsi" +#include "ste-hrefv60plus.dtsi" +#include "ste-href-tvk1281618-r3.dtsi" + +/ { + model = "ST-Ericsson HREF520 and TVK1281618 R3 UIB"; + compatible = "st-ericsson,href520", "st-ericsson,u8500"; + + + /* ST6G3244ME level translator for 1.8/2.9 V */ + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + + states = <1800000 0x1 + 2900000 0x0>; + + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&vmmci_default_mode>; + }; +}; + +&pinctrl { + vmmci { + vmmci_default_mode: vmmc_default { + /* VMMCI level-shifter enable */ + default_href520_cfg1 { + pins = "GPIO78_F4"; + ste,config = <&gpio_out_hi>; + }; + /* VMMCI level-shifter voltage select */ + default_href520_cfg2 { + pins = "GPIO5_AG6"; + ste,config = <&gpio_out_hi>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts new file mode 100644 index 000000000000..dfc933214c1a --- /dev/null +++ b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-hrefprev60.dtsi" +#include "ste-href-stuib.dtsi" + +/ { + model = "ST-Ericsson HREF (pre-v60) and ST UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + + /* ST6G3244ME level translator for 1.8/2.9 V */ + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + + states = <1800000 0x1 + 2900000 0x0>; + + gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + soc { + /* Reset line for the BU21013 touchscreen */ + i2c@80110000 { + /* Only one of these will be used */ + bu21013_tp@5c { + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; + }; + bu21013_tp@5d { + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts new file mode 100644 index 000000000000..75506339a93c --- /dev/null +++ b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-hrefprev60.dtsi" +#include "ste-href-tvk1281618-r2.dtsi" + +/ { + model = "ST-Ericsson HREF (pre-v60) and TVK1281618 R2 UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + + /* ST6G3244ME level translator for 1.8/2.9 V */ + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + + states = <1800000 0x1 + 2900000 0x0>; + + gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-hrefprev60.dtsi b/arch/arm/boot/dts/st/ste-hrefprev60.dtsi new file mode 100644 index 000000000000..9859ee91a15e --- /dev/null +++ b/arch/arm/boot/dts/st/ste-hrefprev60.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + * + * Device Tree for the HREF+ prior to the v60 variant. + */ + +#include "ste-href-ab8500.dtsi" +#include "ste-href.dtsi" + +/ { + gpio_keys { + button@1 { + gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; + }; + }; + + soc { + /* Enable UART1 on this board */ + serial@80121000 { + status = "okay"; + }; + + i2c@80004000 { + tps61052@33 { + compatible = "ti,tps61052"; + reg = <0x33>; + }; + + tc35892@42 { + compatible = "toshiba,tc35892"; + reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35892_hrefprev60_mode>; + + interrupt-controller; + #interrupt-cells = <1>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + spi@80002000 { + /* + * On the first generation boards, this SSP/SPI port was connected + * to the AB8500. + */ + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_hrefprev60_mode>; + status = "okay"; + }; + + // External Micro SD slot + mmc@80126000 { + cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; + }; + + pinctrl { + /* Set this up using hogs */ + pinctrl-names = "default"; + pinctrl-0 = <&ipgpio_hrefprev60_mode>; + + ssp0 { + ssp0_hrefprev60_mode: ssp0_hrefprev60_default { + hrefprev60_mux { + function = "ssp0"; + groups = "ssp0_a_1"; + }; + hrefprev60_cfg1 { + pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + + }; + }; + sdi0 { + /* This additional pin needed on early MOP500 and HREFs previous to v60 */ + sdi0_default_mode: sdi0_default { + hrefprev60_mux { + function = "mc0"; + groups = "mc0dat31dir_a_1"; + }; + hrefprev60_cfg1 { + pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + + }; + }; + tc35892 { + tc35892_hrefprev60_mode: tc35892_hrefprev60 { + hrefprev60_cfg { + pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + ipgpio { + ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { + hrefprev60_mux { + function = "ipgpio"; + groups = "ipgpio0_c_1", "ipgpio1_c_1"; + }; + hrefprev60_cfg1 { + pins = "GPIO6_AF6", "GPIO7_AG5"; + ste,config = <&in_pu>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts new file mode 100644 index 000000000000..52c56ed17ae6 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + * + * Device Tree for the HREF version 60 or later with the ST UIB + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-hrefv60plus.dtsi" +#include "ste-href-stuib.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) and ST UIB"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; + + /* ST6G3244ME level translator for 1.8/2.9 V */ + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + + states = <1800000 0x1 + 2900000 0x0>; + + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&vmmci_default_mode>; + }; + + soc { + /* Reset line for the BU21013 touchscreen */ + i2c@80110000 { + /* Only one of these will be used */ + bu21013_tp@5c { + interrupt-parent = <&gpio2>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; + }; + bu21013_tp@5d { + interrupt-parent = <&gpio2>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; + }; + }; + }; +}; + +&pinctrl { + vmmci { + vmmci_default_mode: vmmc_default { + /* VMMCI level-shifter enable */ + default_hrefv60_cfg2 { + pins = "GPIO169_D22"; + ste,config = <&gpio_out_hi>; + }; + /* VMMCI level-shifter voltage select */ + default_hrefv60_cfg3 { + pins = "GPIO5_AG6"; + ste,config = <&gpio_out_hi>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts new file mode 100644 index 000000000000..2db2f8be8b03 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + * + * Device Tree for the HREF version 60 or later with the TVK1281618 R2 UIB + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-hrefv60plus.dtsi" +#include "ste-href-tvk1281618-r2.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) and TVK1281618 R2 UIB"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; + + /* ST6G3244ME level translator for 1.8/2.9 V */ + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + + states = <1800000 0x1 + 2900000 0x0>; + + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&vmmci_default_mode>; + }; +}; + +&pinctrl { + vmmci { + vmmci_default_mode: vmmc_default { + /* VMMCI level-shifter enable */ + default_hrefv60_cfg2 { + pins = "GPIO169_D22"; + ste,config = <&gpio_out_hi>; + }; + /* VMMCI level-shifter voltage select */ + default_hrefv60_cfg3 { + pins = "GPIO5_AG6"; + ste,config = <&gpio_out_hi>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi new file mode 100644 index 000000000000..e66fa59c2de6 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson AB + */ + +#include "ste-href-ab8500.dtsi" +#include "ste-href.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) platform with Device Tree"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; + + thermal-zones { + chassis-thermal { + /* Poll every 20 seconds */ + polling-delay = <20000>; + /* Poll every 2nd second when cooling */ + polling-delay-passive = <2000>; + + thermal-sensors = <&therm1>, <&therm2>; + + /* Tripping points made from rough guess about operating conditions */ + trips { + chassis_alert: chassis-alert { + /* At 50 degrees take down the CPU frequency */ + temperature = <50000>; + hysteresis = <3000>; + type = "active"; + }; + chassis_crit: chassis-crit { + /* Just shut down at 70 degrees */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + /* Push down the operating frequency of the SoC when it gets hot */ + cooling-maps { + map0 { + trip = <&chassis_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <100>; + }; + }; + }; + }; + + /* + * Thermistors on the board, formally to monitor battery temperatures + * but what they measure is the board temperature. + */ + therm1: thermistor@0 { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x06>; /* AUX1 */ + pullup-uv = <1800000>; + pullup-ohm = <220000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + therm2: thermistor@1 { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x07>; /* AUX2 */ + pullup-uv = <1800000>; + pullup-ohm = <220000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + soc { + /* Name the GPIO muxed rails on the HREF boards */ + gpio@8012e000 { + /* GPIOs 0 - 31 */ + gpio-line-names = + /* GPIO0,1 used for UART0 BT RX/TX */ + "", "", + "UART_WAKE", + "BT_WAKE", + "", + "SDMMC_1V8_3V_SEL", + "FLASH_LED_SYNC (FLASH_CTRL_0)", + "XENON_READY (FLASH_CTRL_1)", + "", "", "", "", "", "", "", "", + "", "", "", "", + "", + "FLASH_LED_EN (FLASH_CTRL_3)", + "", "", + "", "", "", "", "", + /* Used by UART2 (console) */ + "", "", + "MAGNETOMETER_INT"; + }; + + gpio@8012e080 { + /* GPIOs 32 - 63 */ + gpio-line-names = + "MAGNETOMETER_DRDY", + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e000 { + /* GPIOs 64 - 95 */ + gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)", + "DISP1_RST", + "DISP2_RST", + "TOUCH_INT2", + "LCD_VSI0_A", + "LCD_VSI1_A", + /* GPIO 70-77 used for ETM */ + "", "", "", "", "", "", "", "", + /* GPIO 78-81 used for YCBCR */ + "", "", "", "", + "ACCELEROMETER_INT1_RDY", + "ACCELEROMETER_INT2", + "TOUCH_INT", + "WLAN_ENA", + "", "", "", "", "", + "FORCE_SENSING_INT", + "FORCE_SENSING_RESET", + "", "", + "SDMMC_CD"; + }; + + gpio@8000e080 { + /* GPIOs 96 - 127 */ + gpio-line-names = "", + "FORCE_SENSING_WU", + "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e100 { + /* GPIOs 128 - 159 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", + "DIPRO_INT", /* GPIO139 */ + "XSHUTDOWN_SECONDARY_SENSOR", + "XSHUTDOWN_PRIMARY_SENSOR", + "NFC_RST (NFC_CTRL_", + "TOUCH_RST", + "NFC_IRQ (NFC_CTRL_1)", + "HAL_SW", + "TOUCH_RST2", + "", "", + "VAUDIO_HF_EN", /* GPIO149 */ + "", "", "", "", "", "", "", "", "", ""; + }; + + gpio@8000e180 { + /* GPIOs 160 - 191 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", + "SDMMC_EN", + "XENON_CHARGE (FLASH_CONTROL_5)", + "GBF_ENA_RESET", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8011e000 { + /* GPIOs 192 - 223 */ + gpio-line-names = "HDTV_INTN", + "", "", "", + "HDTV_RSTN", + "", "", "", + "", /* GPIO200 */ + "", "", "", "", "", "", "", + /* GPIO208-216 used for WGBF_MC1 */ + "", "", "", "", "", "", "", "", "", + "SW_FRONT_PROXIMITY", /* GPIO217 */ + "KPD_CTRL_INT", /* Keypad controller */ + "", "", "", "", ""; + }; + + gpio@8011e080 { + /* GPIOs 224 - 255 */ + gpio-line-names = "", "", + "HSIT_ACWAKE0", + "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + // External Micro SD slot + mmc@80126000 { + cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 + }; + + pinctrl { + /* + * Set this up using hogs, as time goes by and as seems fit, these + * can be moved over to being controlled by respective device. + */ + pinctrl-names = "default"; + pinctrl-0 = <&ipgpio_hrefv60_mode>, + <&etm_hrefv60_mode>, + <&nahj_hrefv60_mode>, + <&nfc_hrefv60_mode>, + <&force_hrefv60_mode>, + <&dipro_hrefv60_mode>, + <&vaudio_hf_hrefv60_mode>, + <&gbf_hrefv60_mode>, + <&hdtv_hrefv60_mode>, + <&gpios_hrefv60_mode>; + + sdi0 { + sdi0_default_mode: sdi0_default { + /* SD card detect GPIO pin, extend default state */ + default_hrefv60_cfg1 { + pins = "GPIO95_E8"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + ipgpio { + /* + * XENON Flashgun on image processor GPIO (controlled from image + * processor firmware), mux in these image processor GPIO lines 0 + * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant + * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias + * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. + */ + ipgpio_hrefv60_mode: ipgpio_hrefv60 { + hrefv60_mux { + function = "ipgpio"; + groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; + }; + hrefv60_cfg1 { + pins = "GPIO6_AF6", "GPIO7_AG5"; + ste,config = <&in_pu>; + }; + hrefv60_cfg2 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg3 { + pins = "GPIO64_F3"; + ste,config = <&out_lo>; + }; + }; + }; + etm { + /* + * Drive D19-D23 for the ETM PTM trace interface low, + * (presumably pins are unconnected therefore grounded here, + * the "other alt C1" setting enables these pins) + */ + etm_hrefv60_mode: etm_hrefv60 { + hrefv60_cfg1 { + pins = + "GPIO70_G5", + "GPIO71_G4", + "GPIO72_H4", + "GPIO73_H3", + "GPIO74_J3"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + nahj { + nahj_hrefv60_mode: nahj_hrefv60 { + /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ + hrefv60_cfg1 { + pins = "GPIO76_J2"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + nfc { + nfc_hrefv60_mode: nfc_hrefv60 { + /* NFC ENA and RESET to low, pulldown IRQ line */ + hrefv60_cfg1 { + pins = + "GPIO77_H1", /* NFC_ENA */ + "GPIO142_C11"; /* NFC_RESET */ + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + pins = "GPIO144_B13"; /* NFC_IRQ */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + force { + force_hrefv60_mode: force_hrefv60 { + hrefv60_cfg1 { + pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ + ste,config = <&gpio_in_pu>; + }; + hrefv60_cfg2 { + pins = + "GPIO92_D6", /* FORCE_SENSING_RST */ + "GPIO97_D9"; /* FORCE_SENSING_WU */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + dipro { + dipro_hrefv60_mode: dipro_hrefv60 { + hrefv60_cfg1 { + pins = "GPIO139_C9"; /* DIPRO_INT */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + vaudio_hf { + vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { + /* Audio Amplifier HF enable GPIO */ + hrefv60_cfg1 { + pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + gbf { + gbf_hrefv60_mode: gbf_hrefv60 { + /* + * GBF (GPS, Bluetooth, FM-radio) interface, + * pull low to reset state + */ + hrefv60_cfg1 { + pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + hdtv { + hdtv_hrefv60_mode: hdtv_hrefv60 { + /* MSP : HDTV INTERFACE GPIO line */ + hrefv60_cfg1 { + pins = "GPIO192_AJ27"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + mcde { + lcd_hrefv60_mode: lcd_hrefv60 { + /* + * Display Interface 1 uses GPIO 65 for RST (reset). + * Display Interface 2 uses GPIO 66 for RST (reset). + * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) + */ + hrefv60_cfg1 { + pins = "GPIO65_F1"; + ste,config = <&gpio_out_hi>; + }; + hrefv60_cfg2 { + pins = "GPIO66_G3"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + gpios { + /* Dangling GPIO pins */ + gpios_hrefv60_mode: gpios_hrefv60 { + default_cfg1 { + /* Normally UART1 RXD, now dangling */ + pins = "GPIO4_AH6"; + ste,config = <&in_pu>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/st/ste-nomadik-nhk15.dts new file mode 100644 index 000000000000..cdff33063d6f --- /dev/null +++ b/arch/arm/boot/dts/st/ste-nomadik-nhk15.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ST Microelectronics Nomadik NHK8815 board + */ + +/dts-v1/; +#include +#include +#include "ste-nomadik-stn8815.dtsi" + +/ { + model = "Nomadik STN8815NHK"; + compatible = "st,nomadik-nhk-15"; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + stmpe-i2c0 = &stmpe0; + stmpe-i2c1 = &stmpe1; + }; + + pinctrl { + uart0 { + uart0_nhk_mode: uart0_mux { + u0_default_mux { + function = "u0"; + groups = "u0txrx_a_1", "u0ctsrts_a_1"; + }; + }; + }; + + stmpe2401_1 { + stmpe2401_1_nhk_mode: stmpe2401_1_nhk { + nhk_cfg1 { + pins = "GPIO76_B20"; // IRQ line + ste,input = <0>; + }; + nhk_cfg2 { + pins = "GPIO77_B8"; // reset line + ste,output = <1>; + }; + }; + }; + stmpe2401_2 { + stmpe2401_2_nhk_mode: stmpe2401_2_nhk { + nhk_cfg1 { + pins = "GPIO78_A8"; // IRQ line + ste,input = <0>; + }; + nhk_cfg2 { + pins = "GPIO79_C9"; // reset line + ste,output = <1>; + }; + }; + }; + lis3lv02dl { + lis3lv02dl_nhk_mode: lis3lv02dl_nhk { + nhk_cfg1 { + pins = "GPIO82_C10"; // IRQ line + ste,input = <0>; + }; + }; + }; + }; + src@101e0000 { + /* These chrystal outputs are not used on this board */ + disable-sxtalo; + disable-mxtalo; + }; + + /* This is where the interrupt is routed on the NHK-15 debug board */ + external-bus@34000000 { + compatible = "simple-bus"; + reg = <0x34000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x34000000 0x1000000>; + ethernet@300 { + compatible = "smsc,lan91c111"; + reg = <0x300 0x0fd00>; + reg-io-width = <2>; + reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&stmpe_gpio44>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c0 { + lis3lv02dl@1d { + /* Accelerometer */ + compatible = "st,lis3lv02dl-accel"; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 + pinctrl-0 = <&lis3lv02dl_nhk_mode>; + pinctrl-names = "default"; + reg = <0x1d>; + }; + stmpe0: port-expander@43 { + compatible = "st,stmpe2401"; + reg = <0x43>; + reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 + interrupt-parent = <&gpio2>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe2401_1_nhk_mode>; + stmpe_gpio43: gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* Some pins in alternate functions */ + st,norequest-mask = <0xf0f002>; + }; + keyboard-controller { + compatible = "st,stmpe-keypad"; + debounce-interval = <64>; + st,scan-count = <8>; + st,no-autorepeat; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00020072 // Vol down + 0x00030073 // Vol up + 0x0100009e // Back + 0x010100e3 // TV out + 0x01020098 // Lock + 0x0103013b // Start + 0x020000a3 // Next + 0x020100a4 // Play + 0x020200a5 // Prev + 0x02030160 // OK + 0x03000069 // Left + 0x0301006a // Right + 0x03020067 // Up + 0x0303006c>; // Down + }; + stmpe0_pwm: pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; + }; + }; + stmpe1: port-expander@44 { + compatible = "st,stmpe2401"; + reg = <0x44>; + reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 + interrupt-parent = <&gpio2>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe2401_2_nhk_mode>; + stmpe_gpio44: gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* + * This will turn off SATA so that MMC/SD + * can thrive + */ + mmcsd-hog { + gpio-hog; + gpios = <2 0x0>; + output-low; + line-name = "SATA EN"; + }; + }; + }; + }; + + amba { + clcd@10120000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&clcd_24bit_mux>; + port { + nomadik_clcd: endpoint { + remote-endpoint = <&nomadik_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <16 8 0>; + }; + }; + + }; + + /* Activate RX/TX and CTS/RTS on UART 0 */ + uart0: serial@101fd000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_nhk_mode>; + status = "okay"; + }; + mmcsd: mmc@101f6000 { + cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* + * As we're dealing with 3wire SPI, we only define SCK + * and MOSI (in the spec MOSI is called "SDA"). + */ + sck-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + /* + * WVGA connector 21 + * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB + * with TPO touch screen. + */ + panel: display@0 { + /* + * The TPO display driver is connected to a + * 5.7" OSD OSD057VA01CT TFT display. + */ + compatible = "tpo,tpg110"; + reg = <0>; + spi-3wire; + /* 320 ns min period ~= 3 MHz */ + spi-max-frequency = <3000000>; + /* Width and height from the OSD data sheet */ + width-mm = <116>; + height-mm = <87>; + grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; + backlight = <&bl>; + + port { + nomadik_clcd_panel: endpoint { + remote-endpoint = <&nomadik_clcd>; + }; + }; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pwms = <&stmpe0_pwm 0 500000>; + pwm-names = "backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi new file mode 100644 index 000000000000..bfdb5d9a014f --- /dev/null +++ b/arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 ST-Ericsson + */ +#include + +/ { + in_nopull: in_nopull { + ste,input = ; + }; + + in_pu: input_pull_up { + ste,input = ; + }; + + in_pd: input_pull_down { + ste,input = ; + }; + + out_hi: output_high { + ste,output = ; + }; + + out_lo: output_low { + ste,output = ; + }; + + gpio_in_nopull: gpio_input_nopull { + ste,gpio = ; + ste,input = ; + }; + + gpio_in_pu: gpio_input_pull_up { + ste,gpio = ; + ste,input = ; + }; + + gpio_in_pd: gpio_input_pull_down { + ste,gpio = ; + ste,input = ; + }; + + gpio_out_lo: gpio_output_low { + ste,gpio = ; + ste,output = ; + }; + + gpio_out_hi: gpio_output_high { + ste,gpio = ; + ste,output = ; + }; + + slpm_pdis: slpm_pdis { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_wkup_pdis: slpm_wkup_pdis { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_wkup_pdis_en: slpm_wkup_pdis_en { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_in_pu: slpm_in_pu { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + }; + + slpm_in_pdis: slpm_in_pdis { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_in_wkup_pdis: slpm_in_wkup_pdis { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_out_lo: slpm_out_lo { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + }; + + slpm_out_hi: slpm_out_hi { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + }; + + slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_out_lo_pdis: slpm_out_lo_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_out_wkup_pdis: slpm_out_wkup_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + in_wkup_pdis: in_wkup_pdis { + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + in_wkup_pdis_en: in_wkup_pdis_en { + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + out_lo_wkup_pdis: out_lo_wkup_pdis { + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + out_hi_wkup_pdis: out_hi_wkup_pdis { + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + out_wkup_pdis: out_wkup_pdis { + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-nomadik-s8815.dts b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts new file mode 100644 index 000000000000..c905c2643a12 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ST-Ericsson Nomadik S8815 board + * Produced by Calao Systems + */ + +/dts-v1/; +#include +#include "ste-nomadik-stn8815.dtsi" + +/ { + model = "Calao Systems USB-S8815"; + compatible = "calaosystems,usb-s8815"; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + gpio3: gpio@101e7000 { + /* This hog will bias the MMC/SD card detect line */ + mmcsd-gpio { + gpio-hog; + gpios = <16 0x0>; + output-low; + line-name = "card detect bias"; + }; + }; + + src@101e0000 { + /* These chrystal drivers are not used on this board */ + disable-sxtalo; + disable-mxtalo; + }; + + pinctrl { + /* Hog CD pins */ + pinctrl-names = "default"; + pinctrl-0 = <&cd_default_mode>; + + uart0 { + /* Only use RX/TX pins */ + uart0_s8815_mode: uart0_mux { + u0_default_mux { + function = "u0"; + groups = "u0txrx_a_1"; + }; + }; + }; + mmcsd-cd { + cd_default_mode: cd_default { + cd_default_cfg1 { + /* CD input GPIO */ + pins = "GPIO111_H21"; + ste,input = <0>; + }; + cd_default_cfg2 { + /* CD GPIO biasing */ + pins = "GPIO112_J21"; + ste,output = <0>; + }; + }; + }; + gpioi2c { + gpioi2c_default_mode: gpioi2c_default { + gpioi2c_default_cfg { + pins = "GPIO73_C21", "GPIO74_C20"; + ste,input = <0>; + }; + }; + }; + user-led { + user_led_default_mode: user_led_default { + user_led_default_cfg { + pins = "GPIO2_C5"; + ste,output = <1>; + }; + }; + }; + user-button { + user_button_default_mode: user_button_default { + user_button_default_cfg { + pins = "GPIO3_A4"; + ste,input = <0>; + }; + }; + }; + }; + + /* Ethernet */ + external-bus@34000000 { + compatible = "simple-bus"; + reg = <0x34000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x34000000 0x1000000>; + ethernet@300 { + compatible = "smsc,lan91c111"; + reg = <0x300 0x0fd00>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c1 { + lis3lv02dl@1d { + /* Accelerometer */ + compatible = "st,lis3lv02dl-accel"; + reg = <0x1d>; + }; + }; + + /* GPIO I2C connected to the USB portions of the STw4811 only */ + gpio-i2c { + compatible = "i2c-gpio"; + gpios = <&gpio2 10 0>, /* sda */ + <&gpio2 9 0>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpioi2c_default_mode>; + + stw4811@2d { + compatible = "st,stw4811-usb"; + reg = <0x2d>; + }; + }; + + + amba { + /* Activate RXTX on UART 0 */ + uart0: serial@101fd000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_s8815_mode>; + status = "okay"; + }; + /* Configure card detect for the uSD slot */ + mmc@101f6000 { + cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + }; + + /* The user LED on the board is set up to be used for heartbeat */ + leds { + compatible = "gpio-leds"; + user-led { + label = "user_led"; + gpios = <&gpio0 2 0x1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_default_mode>; + }; + }; + + /* User key mapped in as "escape" */ + gpio-keys { + compatible = "gpio-keys"; + user-button { + label = "user_button"; + gpios = <&gpio0 3 0x1>; + linux,code = <1>; /* KEY_ESC */ + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&user_button_default_mode>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi new file mode 100644 index 000000000000..6816eef39d45 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi @@ -0,0 +1,884 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0x00000000 0x04000000>, + <0x08000000 0x04000000>; + }; + + L2: cache-controller { + compatible = "arm,l210-cache"; + reg = <0x10210000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <30>; + cache-unified; + cache-level = <2>; + cache-size = <131072>; + cache-sets = <512>; + cache-line-size = <32>; + /* At full speed latency must be >=2 */ + arm,tag-latency = <8>; + arm,data-latency = <8 8>; + arm,dirty-latency = <8>; + }; + + mtu0: mtu@101e2000 { + /* Nomadik system timer */ + compatible = "st,nomadik-mtu"; + reg = <0x101e2000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <4>; + clocks = <&timclk>, <&pclk>; + clock-names = "timclk", "apb_pclk"; + }; + + mtu1: mtu@101e3000 { + /* Secondary timer */ + reg = <0x101e3000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <5>; + clocks = <&timclk>, <&pclk>; + clock-names = "timclk", "apb_pclk"; + }; + + gpio0: gpio@101e4000 { + compatible = "st,nomadik-gpio"; + reg = <0x101e4000 0x80>; + interrupt-parent = <&vica>; + interrupts = <6>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + clocks = <&pclk>; + }; + + gpio1: gpio@101e5000 { + compatible = "st,nomadik-gpio"; + reg = <0x101e5000 0x80>; + interrupt-parent = <&vica>; + interrupts = <7>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 32>; + clocks = <&pclk>; + }; + + gpio2: gpio@101e6000 { + compatible = "st,nomadik-gpio"; + reg = <0x101e6000 0x80>; + interrupt-parent = <&vica>; + interrupts = <8>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + clocks = <&pclk>; + }; + + gpio3: gpio@101e7000 { + compatible = "st,nomadik-gpio"; + reg = <0x101e7000 0x80>; + ngpio = <28>; + interrupt-parent = <&vica>; + interrupts = <9>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <3>; + gpio-ranges = <&pinctrl 0 96 28>; + clocks = <&pclk>; + }; + + pinctrl: pinctrl { + compatible = "stericsson,stn8815-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; + /* Pin configurations */ + uart1 { + uart1_default_mux: uart1_mux { + u1_default_mux { + function = "u1"; + groups = "u1_a_1"; + }; + }; + }; + mmcsd { + mmcsd_default_mux: mmcsd_mux { + mmcsd_default_mux { + function = "mmcsd"; + groups = "mmcsd_a_1", "mmcsd_b_1"; + }; + }; + mmcsd_default_mode: mmcsd_default { + mmcsd_default_cfg1 { + /* + * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 + * MCCMD, MCDAT3-0, MCMSFBCLK + */ + pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", + "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", + "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; + ste,output = <2>; + }; + }; + }; + i2c0 { + i2c0_default_mux: i2c0_mux { + i2c0_default_mux { + function = "i2c0"; + groups = "i2c0_a_1"; + }; + }; + i2c0_default_mode: i2c0_default { + i2c0_default_cfg { + pins = "GPIO62_D3", "GPIO63_D2"; + ste,input = <0>; + }; + }; + }; + i2c1 { + i2c1_default_mux: i2c1_mux { + i2c1_default_mux { + function = "i2c1"; + groups = "i2c1_a_1"; + }; + }; + i2c1_default_mode: i2c1_default { + i2c1_default_cfg { + pins = "GPIO53_L4", "GPIO54_L3"; + ste,input = <0>; + }; + }; + }; + clcd { + /* + * This should be activated to use the additional + * 8 lines for bits 16 thru 23 from the CLCD block. + */ + clcd_24bit_mux: clcd_mux { + clcd_24bit_mux { + function = "clcd"; + groups = "clcd_16_23_b_1"; + }; + }; + }; + }; + + /* Power Management Unit */ + pmu: pmu@101e9000 { + compatible = "stericsson,nomadik-pmu", "syscon"; + reg = <0x101e0000 0x1000>; + }; + + src: src@101e0000 { + compatible = "stericsson,nomadik-src"; + reg = <0x101e0000 0x1000>; + + /* + * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz + * that is parent of TIMCLK, PLL1 and PLL2 + */ + mxtal: mxtal@19.2M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + /* + * The 2.4 MHz TIMCLK reference clock is active at + * boot time, this is actually the MXTALCLK @19.2 MHz + * divided by 8. This clock is used by the timers and + * watchdog. See page 105 ff. + */ + timclk: timclk@2.4M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <8>; + clock-mult = <1>; + clocks = <&mxtal>; + }; + + /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ + pll1: pll1@0 { + #clock-cells = <0>; + compatible = "st,nomadik-pll-clock"; + pll-id = <1>; + clocks = <&mxtal>; + }; + + /* HCLK divides the PLL1 with 1,2,3 or 4 */ + hclk: hclk@0 { + #clock-cells = <0>; + compatible = "st,nomadik-hclk-clock"; + clocks = <&pll1>; + }; + /* The PCLK domain uses HCLK right off */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&hclk>; + }; + + /* PLL2 is usually 864 MHz and divided into a few fixed rates */ + pll2: pll2@0 { + #clock-cells = <0>; + compatible = "st,nomadik-pll-clock"; + pll-id = <2>; + clocks = <&mxtal>; + }; + clk216: clk216@216M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll2>; + }; + clk108: clk108@108M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&clk216>; + }; + clk72: clk72@72M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + /* The data sheet does not say how this is derived */ + clock-div = <12>; + clock-mult = <1>; + clocks = <&pll2>; + }; + clk48: clk48@48M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + /* The data sheet does not say how this is derived */ + clock-div = <18>; + clock-mult = <1>; + clocks = <&pll2>; + }; + clk27: clk27@27M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&clk108>; + }; + + /* This apparently exists as well */ + ulpiclk: ulpiclk@60M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + /* + * IP AMBA bus clocks, driving the bus side of the + * peripheral clocking, clock gates. + */ + + hclkdma0: hclkdma0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <0>; + clocks = <&hclk>; + }; + hclksmc: hclksmc@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <1>; + clocks = <&hclk>; + }; + hclksdram: hclksdram@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <2>; + clocks = <&hclk>; + }; + hclkdma1: hclkdma1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <3>; + clocks = <&hclk>; + }; + hclkclcd: hclkclcd@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <4>; + clocks = <&hclk>; + }; + pclkirda: pclkirda@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <5>; + clocks = <&pclk>; + }; + pclkssp: pclkssp@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <6>; + clocks = <&pclk>; + }; + pclkuart0: pclkuart0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <7>; + clocks = <&pclk>; + }; + pclksdi: pclksdi@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <8>; + clocks = <&pclk>; + }; + pclki2c0: pclki2c0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <9>; + clocks = <&pclk>; + }; + pclki2c1: pclki2c1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <10>; + clocks = <&pclk>; + }; + pclkuart1: pclkuart1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <11>; + clocks = <&pclk>; + }; + pclkmsp0: pclkmsp0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <12>; + clocks = <&pclk>; + }; + hclkusb: hclkusb@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <13>; + clocks = <&hclk>; + }; + hclkdif: hclkdif@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <14>; + clocks = <&hclk>; + }; + hclksaa: hclksaa@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <15>; + clocks = <&hclk>; + }; + hclksva: hclksva@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <16>; + clocks = <&hclk>; + }; + pclkhsi: pclkhsi@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <17>; + clocks = <&pclk>; + }; + pclkxti: pclkxti@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <18>; + clocks = <&pclk>; + }; + pclkuart2: pclkuart2@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <19>; + clocks = <&pclk>; + }; + pclkmsp1: pclkmsp1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <20>; + clocks = <&pclk>; + }; + pclkmsp2: pclkmsp2@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <21>; + clocks = <&pclk>; + }; + pclkowm: pclkowm@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <22>; + clocks = <&pclk>; + }; + hclkhpi: hclkhpi@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <23>; + clocks = <&hclk>; + }; + pclkske: pclkske@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <24>; + clocks = <&pclk>; + }; + pclkhsem: pclkhsem@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <25>; + clocks = <&pclk>; + }; + hclk3d: hclk3d@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <26>; + clocks = <&hclk>; + }; + hclkhash: hclkhash@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <27>; + clocks = <&hclk>; + }; + hclkcryp: hclkcryp@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <28>; + clocks = <&hclk>; + }; + pclkmshc: pclkmshc@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <29>; + clocks = <&pclk>; + }; + hclkusbm: hclkusbm@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <30>; + clocks = <&hclk>; + }; + hclkrng: hclkrng@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <31>; + clocks = <&hclk>; + }; + + /* IP kernel clocks */ + clcdclk: clcdclk@0 { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <36>; + clocks = <&clk72 &clk48>; + }; + irdaclk: irdaclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <37>; + clocks = <&clk48>; + }; + sspiclk: sspiclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <38>; + clocks = <&clk48>; + }; + uart0clk: uart0clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <39>; + clocks = <&clk48>; + }; + sdiclk: sdiclk@48M { + /* Also called MCCLK in some documents */ + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <40>; + clocks = <&clk48>; + }; + i2c0clk: i2c0clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <41>; + clocks = <&clk48>; + }; + i2c1clk: i2c1clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <42>; + clocks = <&clk48>; + }; + uart1clk: uart1clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <43>; + clocks = <&clk48>; + }; + mspclk0: mspclk0@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <44>; + clocks = <&clk48>; + }; + usbclk: usbclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <45>; + clocks = <&clk48>; /* 48 MHz not ULPI */ + }; + difclk: difclk@72M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <46>; + clocks = <&clk72>; + }; + ipi2cclk: ipi2cclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <47>; + clocks = <&clk48>; /* Guess */ + }; + ipbmcclk: ipbmcclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <48>; + clocks = <&clk48>; /* Guess */ + }; + hsiclkrx: hsiclkrx@216M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <49>; + clocks = <&clk216>; + }; + hsiclktx: hsiclktx@108M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <50>; + clocks = <&clk108>; + }; + uart2clk: uart2clk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <51>; + clocks = <&clk48>; + }; + mspclk1: mspclk1@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <52>; + clocks = <&clk48>; + }; + mspclk2: mspclk2@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <53>; + clocks = <&clk48>; + }; + owmclk: owmclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <54>; + clocks = <&clk48>; /* Guess */ + }; + skeclk: skeclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <56>; + clocks = <&clk48>; /* Guess */ + }; + x3dclk: x3dclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <58>; + clocks = <&clk48>; /* Guess */ + }; + pclkmsp3: pclkmsp3@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <59>; + clocks = <&pclk>; + }; + mspclk3: mspclk3@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <60>; + clocks = <&clk48>; + }; + mshcclk: mshcclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <61>; + clocks = <&clk48>; /* Guess */ + }; + usbmclk: usbmclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <62>; + /* Stated as "48 MHz not ULPI clock" */ + clocks = <&clk48>; + }; + rngcclk: rngcclk@48M { + #clock-cells = <0>; + compatible = "st,nomadik-src-clock"; + clock-id = <63>; + clocks = <&clk48>; /* Guess */ + }; + }; + + /* A NAND flash of 128 MiB */ + fsmc: flash@40000000 { + compatible = "stericsson,fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10100000 0x1000>, /* FSMC Register*/ + <0x40000000 0x2000>, /* NAND Base DATA */ + <0x41000000 0x2000>, /* NAND Base ADDR */ + <0x40800000 0x2000>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + clocks = <&hclksmc>; + status = "okay"; + + partition@0 { + label = "X-Loader(NAND)"; + reg = <0x0 0x40000>; + }; + partition@40000 { + label = "MemInit(NAND)"; + reg = <0x40000 0x40000>; + }; + partition@80000 { + label = "BootLoader(NAND)"; + reg = <0x80000 0x200000>; + }; + partition@280000 { + label = "Kernel zImage(NAND)"; + reg = <0x280000 0x300000>; + }; + partition@580000 { + label = "Root Filesystem(NAND)"; + reg = <0x580000 0x1600000>; + }; + partition@1b80000 { + label = "User Filesystem(NAND)"; + reg = <0x1b80000 0x6480000>; + }; + }; + + /* I2C0 connected to the STw4811 power management chip */ + i2c0 { + compatible = "st,nomadik-i2c", "arm,primecell"; + reg = <0x101f8000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <20>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c0clk>, <&pclki2c0>; + clock-names = "mclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; + + stw4811@2d { + compatible = "st,stw4811"; + reg = <0x2d>; + vmmc_regulator: vmmc { + compatible = "st,stw481x-vmmc"; + regulator-name = "VMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + /* I2C1 connected to various sensors */ + i2c1 { + compatible = "st,nomadik-i2c", "arm,primecell"; + reg = <0x101f7000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <21>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c1clk>, <&pclki2c1>; + clock-names = "mclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; + + camera@2d { + compatible = "st,camera"; + reg = <0x10>; + }; + stw5095@1a { + compatible = "st,stw5095"; + reg = <0x1a>; + }; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clcd@10120000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x10120000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + interrupt-parent = <&vica>; + clocks = <&clcdclk>, <&hclkclcd>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + + vica: interrupt-controller@10140000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10140000 0x20>; + }; + + vicb: interrupt-controller@10140020 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10140020 0x20>; + }; + + uart0: serial@101fd000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101fd000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <12>; + clocks = <&uart0clk>, <&pclkuart0>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + dmas = <&dmac0 14 1>, + <&dmac0 15 1>; + dma-names = "rx", "tx"; + }; + + uart1: serial@101fb000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101fb000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <17>; + clocks = <&uart1clk>, <&pclkuart1>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_default_mux>; + dmas = <&dmac1 22 1>, + <&dmac1 23 1>; + dma-names = "rx", "tx"; + }; + + uart2: serial@101f2000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f2000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <28>; + clocks = <&uart2clk>, <&pclkuart2>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + dmas = <&dmac1 30 1>, + <&dmac1 31 1>; + dma-names = "rx", "tx"; + }; + + rng: rng@101b0000 { + compatible = "arm,primecell"; + reg = <0x101b0000 0x1000>; + clocks = <&rngcclk>, <&hclkrng>; + clock-names = "rng", "apb_pclk"; + }; + + rtc: rtc@101e8000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x101e8000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + interrupt-parent = <&vica>; + interrupts = <10>; + }; + + mmcsd: mmc@101f6000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x101f6000 0x1000>; + clocks = <&sdiclk>, <&pclksdi>; + clock-names = "mclk", "apb_pclk"; + interrupt-parent = <&vica>; + interrupts = <22>; + max-frequency = <400000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + full-pwr-cycle; + /* + * The STw4811 circuit used with the Nomadik strictly + * requires that all of these signal direction pins be + * routed and used for its 4-bit levelshifter. + */ + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-dat31; + st,sig-dir-cmd; + st,sig-pin-fbclk; + pinctrl-names = "default"; + pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; + vmmc-supply = <&vmmc_regulator>; + }; + + dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + dmac1: dma-controller@10150000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10150000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <13>; + clocks = <&hclkdma1>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-snowball.dts b/arch/arm/boot/dts/st/ste-snowball.dts new file mode 100644 index 000000000000..9a3d6546399d --- /dev/null +++ b/arch/arm/boot/dts/st/ste-snowball.dts @@ -0,0 +1,657 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2011 ST-Ericsson AB + */ + +/dts-v1/; +#include "ste-db9500.dtsi" +#include "ste-href-ab8500.dtsi" +#include "ste-href-family-pinctrl.dtsi" + +/ { + model = "Calao Systems Snowball platform with device tree"; + compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + battery: battery { + compatible = "simple-battery"; + battery-type = "lithium-ion-polymer"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + en_3v3_reg: en_3v3 { + compatible = "regulator-fixed"; + regulator-name = "en-3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */ + gpio = <&ab8500_gpio 25 0x4>; + startup-delay-us = <5000>; + enable-active-high; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce-interval = <50>; + wakeup-source; + linux,code = <2>; + label = "userpb"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce-interval = <50>; + wakeup-source; + linux,code = <3>; + label = "extkb1"; + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce-interval = <50>; + wakeup-source; + linux,code = <4>; + label = "extkb2"; + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce-interval = <50>; + wakeup-source; + linux,code = <5>; + label = "extkb3"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + button@5 { + debounce-interval = <50>; + wakeup-source; + linux,code = <6>; + label = "extkb4"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpioled_snowball_mode>; + used-led { + label = "user_led"; + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + soc { + /* Name the GPIO muxed rails on the Snowball board */ + gpio@8012e000 { + /* GPIOs 0 - 31 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "AP_GPIO31"; + }; + + gpio@8012e080 { + /* GPIOs 32 - 63 */ + gpio-line-names = "USR PB", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e000 { + /* GPIOs 64 - 95 */ + gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e100 { + /* GPIOs 128 - 159 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "IRQ_LAN", "RSTn_LAN", + "USR_LED", "", "", "", "", "", "", + "", "", "AP_GPIO151", "AP_GPIO152", + "", "", "", "", "", "", ""; + }; + + gpio@8000e180 { + /* GPIOs 160 - 191 */ + gpio-line-names = "", "AP_GPIO161", "AP_GPIO162", + "ACCELEROMETER_INT1_RDY", + "ACCELEROMETER_INT2", "MAG_DRDY", + "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC", + "GYRO_INT", "UART_WAKE", "GBF_RESET", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8011e000 { + /* GPIOs 192 - 223 */ + gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST", + "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", + "WLAN_RESETN", "WLAN_IRQ", "MMC_EN", + "MMC_CD", "", "", "", "", ""; + }; + + gpio@8011e080 { + /* GPIOs 224 - 255 */ + gpio-line-names = "", "", "", "", "SD_SEL", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + msp0: msp@80123000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp0txrxtfstck_a_1_default>; + status = "okay"; + }; + + msp1: msp@80124000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp1txrx_a_1_default>; + status = "okay"; + }; + + msp2: msp@80117000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp2_a_1_default>; + }; + + msp3: msp@80125000 { + status = "okay"; + }; + + external-bus@50000000 { + status = "okay"; + + ethernet@0 { + compatible = "smsc,lan9115"; + reg = <0 0x10000>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio4>; + vdd33a-supply = <&en_3v3_reg>; + vddvario-supply = <&db8500_vape_reg>; + pinctrl-names = "default"; + pinctrl-0 = <ð_snowball_mode>; + + reg-shift = <1>; + reg-io-width = <2>; + smsc,force-internal-phy; + smsc,irq-active-high; + smsc,irq-push-pull; + + clocks = <&prcc_pclk 3 0>; + }; + }; + + /* ST6G3244ME level translator for 1.8/2.9 V */ + vmmci: regulator-gpio { + compatible = "regulator-gpio"; + + /* GPIO228 SD_SEL */ + gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + /* GPIO217 MMC_EN */ + enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-name = "mmci-reg"; + regulator-type = "voltage"; + + startup-delay-us = <100>; + + states = <1800000 0x1 + 2900000 0x0>; + }; + + // External Micro SD slot + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + /* All direction control is used */ + st,sig-dir-cmd; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-dat31; + st,sig-pin-fbclk; + full-pwr-cycle; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&vmmci>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; + pinctrl-1 = <&mc0_a_1_sleep>; + + /* GPIO218 MMC_CD */ + cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; + + status = "okay"; + }; + + // WLAN SDIO channel + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_1_default>; + pinctrl-1 = <&mc1_a_1_sleep>; + + status = "okay"; + }; + + // Unused PoP eMMC - register and put it to sleep by default */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + pinctrl-names = "default"; + pinctrl-0 = <&mc2_a_1_sleep>; + + status = "okay"; + }; + + // On-board eMMC + mmc@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + cap-mmc-highspeed; + no-sdio; + no-sd; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc4_a_1_default>; + pinctrl-1 = <&mc4_a_1_sleep>; + + status = "okay"; + }; + + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + }; + + /* This UART is unused and thus left disabled */ + serial@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + }; + + serial@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + status = "okay"; + }; + + i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + status = "okay"; + }; + + i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_b_2_default>; + pinctrl-1 = <&i2c1_b_2_sleep>; + status = "okay"; + }; + + i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + status = "okay"; + lsm303dlh@18 { + /* Accelerometer */ + compatible = "st,lsm303dlh-accel"; + st,drdy-int-pin = <1>; + reg = <0x18>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_snowball_mode>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>, /* INT1 */ + <4 IRQ_TYPE_EDGE_RISING>; /* INT2 */ + }; + lsm303dlh@1e { + /* Magnetometer */ + compatible = "st,lsm303dlh-magn"; + reg = <0x1e>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_snowball_mode>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; /* DRDY line */ + }; + l3g4200d@68 { + /* Gyroscope */ + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x68>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gyro_snowball_mode>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ + <9 IRQ_TYPE_EDGE_RISING>; /* INT1 */ + }; + lsp001wm@5c { + /* Barometer/pressure sensor */ + compatible = "st,lps001wp-press"; + reg = <0x5c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + }; + }; + + i2c@80110000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + status = "okay"; + }; + + spi@80002000 { + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_snowball_mode>; + status = "okay"; + }; + + prcmu@80157000 { + ab8500 { + gpio { + /* + * AB8500 GPIOs are numbered starting from 1, so the first + * index 0 is what in the datasheet is called "GPIO1", and + * the second is "GPIO2" and so forth. Confusingly, the + * Snowball schematic then names the "GPIO2" line "PM_GPIO1". + * while later naming "GPIO4" as "PM_GPIO4". + */ + gpio-line-names = "", /* AB8500 GPIO1 */ + "PM_GPIO1", /* AB8500 GPIO2 */ + "WLAN_CLK_REQ", /* AB8500 GPIO3 */ + "PM_GPIO4", /* AB8500 GPIO4 */ + "", "", "", "", "", "", "", "", "", "", "", + "EN_3V6", /* AB8500 GPIO16 */ + "", "", "", "" ,"", "", "", "", "", + "EN_3V3", /* AB8500 GPIO26 */ + "", "", "", "", "", "", "", "", "", "", "", "", "", + "PM_GPIO40", /* AB8500 GPIO40 */ + "PM_GPIO41", /* AB8500 GPIO41 */ + "PM_GPIO42"; /* AB8500 GPIO42 */ + }; + + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ext_regulators: regulator-external { + ab8500_ext1_reg: ab8500_ext1 { + regulator-name = "ab8500-ext-supply1"; + }; + + ab8500_ext2_reg_reg: ab8500_ext2 { + regulator-name = "ab8500-ext-supply2"; + }; + + ab8500_ext3_reg_reg: ab8500_ext3 { + regulator-name = "ab8500-ext-supply3"; + }; + }; + + regulator { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; + + pinctrl { + /* + * Set this up using hogs, as time goes by and as seems fit, these + * can be moved over to being controlled by respective device. + */ + pinctrl-names = "default"; + pinctrl-0 = <&gbf_snowball_mode>, + <&wlan_snowball_mode>; + + ethernet { + /* + * Mux in "SM" which is used for the + * SMSC911x Ethernet adapter + */ + eth_snowball_mode: eth_snowball { + snowball_mux { + function = "sm"; + groups = "sm_b_1"; + }; + /* LAN IRQ pin */ + snowball_cfg1 { + pins = "GPIO140_B11"; + ste,config = <&in_nopull>; + }; + /* LAN reset pin */ + snowball_cfg2 { + pins = "GPIO141_C12"; + ste,config = <&gpio_out_hi>; + }; + + }; + }; + sdi0 { + sdi0_default_mode: sdi0_default { + snowball_mux { + function = "mc0"; + /* Add the DAT31 pin even if it is not really used */ + groups = "mc0dat31dir_a_1"; + }; + snowball_cfg1 { + pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + /* SD card detect GPIO pin, extend default state */ + snowball_cfg2 { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_pu>; + }; + /* VMMCI level-shifter enable */ + snowball_cfg3 { + pins = "GPIO217_AH12"; + ste,config = <&gpio_out_hi>; + }; + /* VMMCI level-shifter voltage select */ + snowball_cfg4 { + pins = "GPIO228_AJ6"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + ssp0 { + ssp0_snowball_mode: ssp0_snowball_default { + snowball_mux { + function = "ssp0"; + groups = "ssp0_a_1"; + }; + snowball_cfg1 { + pins = "GPIO144_B13"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + snowball_cfg2 { + pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + snowball_cfg3 { + pins = + "GPIO146_D13", /* TXD */ + "GPIO143_D12"; /* CLK */ + ste,config = <&out_lo>; + }; + + }; + }; + gpio_led { + gpioled_snowball_mode: gpioled_default { + snowball_cfg1 { + pins = "GPIO142_C11"; + ste,config = <&gpio_out_hi>; + }; + + }; + }; + accelerometer { + accel_snowball_mode: accel_snowball { + /* Accelerometer lines */ + snowball_cfg1 { + pins = + "GPIO163_C20", /* ACCEL_IRQ1 */ + "GPIO164_B21"; /* ACCEL_IRQ2 */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + gyro { + gyro_snowball_mode: gyro_snowball { + snowball_cfg1 { + pins = + "GPIO166_A22", /* DRDY */ + "GPIO169_D22"; /* INT */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_snowball_mode: magneto_snowball { + snowball_cfg1 { + pins = "GPIO165_C21"; /* MAG_DRDY */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + gbf { + gbf_snowball_mode: gbf_snowball { + /* + * GBF (GPS, Bluetooth, FM-radio) interface, + * pull low to reset state + */ + snowball_cfg1 { + pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + wlan { + wlan_snowball_mode: wlan_snowball { + /* + * Activate this mode with the WLAN chip. + * These are plain GPIO pins used by WLAN + */ + snowball_cfg1 { + pins = + "GPIO161_D21", /* WLAN_PMU_EN */ + "GPIO215_AH13"; /* WLAN_ENA */ + ste,config = <&gpio_out_lo>; + }; + snowball_cfg2 { + pins = "GPIO216_AG12"; /* WLAN_IRQ */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; + + mcde@a0350000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_default_mode>; + pinctrl-1 = <&lcd_sleep_mode>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts new file mode 100644 index 000000000000..463942ae755e --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts @@ -0,0 +1,793 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO, + * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively + * for T-Mobile in the United States. + * + * This phone is closely related to the Codina, but has: + * - No CPU speed cap, full ~1GHz rate + * - Different power management IC, AB8505 + * - As AB8505 has a micro USB phy, no TI TSU6111 + * - Different power routing such as the removal of the external LDO for the + * touchscreen in favor of using the AB8505 + * - Using a regulator for the key backlight LED + * - Using the Samsung S6D27A1 panel by default + * - The panel is using one of the ordinary AB8505 regulators for 1.8V + * - WiFi/Bluetooth combi chip upgraded to BCM4334 + * - GPIO for backlight control moved from 68 to 69 + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy Exhibit (SGH-T599)"; + compatible = "samsung,codina-tmo", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both the 3.0V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 "MOT_EN" */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + led-touchkeys { + compatible = "regulator-led"; + vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V + default-state = "on"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO69 is used on Codina R0.4 and Codina TMO */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd253_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: this should also be used by the SM5103 Camera power management unit */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + clock-frequency = <400000>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + }; + }; + + spi { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO201 */ + cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6d27a1"; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&ab8500_ldo_aux6_reg>; + + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd253>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + /* + * GPIO130 will be set to input no pull-up resulting in a resistor + * pulling the reset high and taking the memory out of reset. + */ + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + serial@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + /* FIXME: add a device for the GPS here */ + }; + + /* Debugging console UART connected to AB8505 */ + serial@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + /* This is mostly identical to the Codina v0.4 regulators */ + regulator { + ab8500_ldo_aux1 { + regulator-name = "v-sensors-vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + regulator-name = "v-aux2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + regulator-name = "v-mmc-sd"; + }; + + ab8500_ldo_aux4 { + regulator-name = "v-aux4"; + /* + * Providing some span here makes the touchkey + * LEDs actually dimmable. + */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "v-aux5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + /* 1.8 V to the display */ + regulator-name = "v-aux6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + regulator-name = "v-sensors-vio"; + }; + }; + }; + }; + + /* I2C0 also known as "AGC I2C" */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@39 { + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; + clock-frequency = <400000>; + reg = <0x39>; + + /* IRQ on GPIO146 "PS_INT" */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tmd2672_codina_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + /* Bosch BMA254 accelerometer */ + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* TODO: write bindings and driver for this touchscreen */ + + /* Zinitix BT404 ISP part */ + isp@50 { + compatible = "zinitix,bt404-isp"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + + /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ + touchscreen@20 { + compatible = "zinitix,bt404"; + reg = <0x20>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V + vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V + zinitix,mode = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + sdi2 { + /* + * GPIO130 should be set in GPIO mode and + * pulled down. (Not connected.) + */ + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + codina_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + codina_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIOs for panel control */ + panel { + panel_default_mode: panel_default { + codina_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + codina_cfg2 { + /* ESD IRQ line "LCD detect" */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + codina_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + codina_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Backlight GPIO */ + backlight { + ktd253_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + codina_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Zinitix BT404 touchscreen */ + tsp { + tsp_default: tsp_default { + codina_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for light/proximity sensor TMD2672 */ + tmd2672 { + tmd2672_codina_default: tmd2672_codina { + codina_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for subpmu */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + codina_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + codina_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + codina_cfg2 { + pins = "GPIO225_AG8"; + /* Needs pull down, no pull down resistor on board */ + ste,config = <&gpio_in_pd>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + codina_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + codina_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + codina_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts new file mode 100644 index 000000000000..c1ae0e23fe45 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts @@ -0,0 +1,953 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Ace 2 GT-I8160 also known as Codina. + * + * NOTE: this is the most common variant according to the vendor tree, known + * as "R0.0". There appears to be a "R0.4" variant with backlight on GPIO69, + * AB8505 and other changes. There is also talk about some variants having a + * Samsung S6D27A1 display, indicated by passing a different command line from + * the boot loader. + * + * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). + * The GT-I8160 plain is known as the "europe" variant. + * The GT-I8160P is the CDMA version and it appears to not use the ST + * Microelectronics accelerometer and reportedly has NFC mounted. + * The GT-I8160chn appears to be the same as the europe variant. + * + * There is also the Codina-TMO, Samsung SGH-T599, which has its own device + * tree. + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8500.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy Ace 2 (GT-I8160)"; + compatible = "samsung,codina", "st-ericsson,u8500"; + + cpus { + cpu@300 { + /* + * This has a frequency cap at ~800 MHz in the firmware. + * (Changing this number here will not overclock it.) + */ + operating-points = <798720 0 + 399360 0 + 199680 0>; + }; + }; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh "TSP" regulator for the touchscreen. + * One GPIO line controls two voltages of 3.3V and 1.8V + * this line is known as "TSP_LDO_ON1" in the schematics. + */ + ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "LDO_TSP_A3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* GPIO94 controls this regulator */ + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_en_default_mode>; + }; + ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_TSP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO94 controls this regulator */ + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both a 3.0V and 1.8V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + lcd_1v8_reg: regulator-gpio-lcd-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 controls this regulator too */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 "MOT_EN" */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds_default_mode>; + touchkey-led { + label = "touchkeys"; + /* + * GPIO194 on R0.0, R0.4 does not use this at all, it + * will instead turn LDO AUX4 on/off for key led backlighy. + * (Line is pulled down on R0.4) + */ + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* + * GPIO68 is for R0.0, the board file talks about a TMO variant + * (R0.4) using GPIO69. + */ + enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd253_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + clock-frequency = <400000>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + dvdd-supply = <&ab8500_ldo_aux2_reg>; // 1.8V + }; + /* TODO: this should also be used by the SM5103 Camera power management unit */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + nfc@2b { + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; + /* NFC IRQ on GPIO32 */ + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + /* GPIO 31 */ + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + /* GPIO88 */ + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pn544_codina_default>; + }; + }; + + spi { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO201 */ + cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Some Codinas (90%) have a WideChips WS2401-based LMS380KF01 + * display mounted and some 10% has a Samsung S6D27A1 instead. + * The boot loader needs to modify this compatible to + * correspond to whatever is passed from the early Samsung boot. + */ + panel@0 { + compatible = "samsung,lms380kf01"; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&lcd_1v8_reg>; + + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd253>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + /* Actually BRCM4330 */ + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + /* + * GPIO130 will be set to input no pull-up resulting in a resistor + * pulling the reset high and taking the memory out of reset. + */ + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + serial@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + compatible = "brcm,bcm4751"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + enable-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&bcm4751_codina_default>; + }; + }; + + /* Debugging console UART connected to TSU6111RSVR (FSA880) */ + serial@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8500 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + regulator { + ab8500_ldo_aux1 { + /* Used for VDD for sensors */ + regulator-name = "V-SENSORS-VDD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux2 { + /* Used for VIO for sensors */ + regulator-name = "V-SENSORS-VIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux3 { + /* Used for voltage for external MMC/SD card */ + regulator-name = "V-MMC-SD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2910000>; + }; + }; + }; + }; + + /* I2C0 also known as "AGC I2C" */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@39 { + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; + clock-frequency = <400000>; + reg = <0x39>; + + /* IRQ on GPIO146 "PS_INT" */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + /* FIXME: needs a VDDIO supply that is connected to a pull-up resistor */ + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tms2672_codina_default>; + }; + }; + + /* I2C1 on GPIO16 and GPIO17 also called "MUS I2C" */ + i2c@80122000 { + status = "okay"; + pinctrl-names = "default","sleep"; + /* FIXME: If it doesn't work try what we use on Gavini */ + pinctrl-0 = <&i2c1_b_2_default>; + pinctrl-1 = <&i2c1_b_2_sleep>; + + /* Texas Instruments TSU6111 micro USB switch */ + usb-switch@25 { + compatible = "ti,tsu6111"; + reg = <0x25>; + /* Interrupt JACK_INT_N on GPIO95 */ + interrupt-parent = <&gpio2>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&tsu6111_codina_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + lisd3dh@19 { + /* ST Microelectronics Accelerometer */ + compatible = "st,lis3dh-accel"; + st,drdy-int-pin = <1>; + reg = <0x19>; + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* TODO: write bindings and driver for this touchscreen */ + + /* Zinitix BT404 ISP part */ + isp@50 { + compatible = "zinitix,bt404-isp"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + + /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ + touchscreen@20 { + compatible = "zinitix,bt404"; + reg = <0x20>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vcca-supply = <&ldo_tsp_3v3_reg>; + vdd-supply = <&ldo_tsp_1v8_reg>; + zinitix,mode = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + sdi2 { + /* + * This will make the resistor mounted in R0.0 pull up + * the reset line and take the eMMC out of reset. On + * R0.4 variants, GPIO130 should be set in GPIO mode and + * pulled down. (Not connected.) + */ + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + codina_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + codina_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIOs for panel control */ + panel { + panel_default_mode: panel_default { + codina_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + codina_cfg2 { + /* ESD IRQ line "LCD detect" */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the touchscreen */ + tsp-ldo { + tsp_ldo_en_default_mode: tsp_ldo_default { + /* LDO enable on GPIO94 */ + gavini_cfg1 { + pins = "GPIO94_D7"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + codina_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the key LED */ + key-led { + gpio_leds_default_mode: en_led_ldo_default { + /* EN_LED_LDO on GPIO194 */ + codina_cfg1 { + pins = "GPIO194_AF27"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + codina_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Backlight GPIO */ + backlight { + ktd253_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO68_E1"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + codina_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Zinitix BT404 touchscreen */ + tsp { + tsp_default: tsp_default { + codina_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for light/proximity sensor TMS2672 */ + tms2672 { + tms2672_codina_default: tms2672_codina { + codina_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for subpmu */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + codina_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + codina_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + codina_cfg2 { + pins = "GPIO225_AG8"; + /* Needs pull down, no pull down resistor on board */ + ste,config = <&gpio_in_pd>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + codina_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + codina_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* Interrupt line for TI TSU6111 Micro USB switch */ + tsu6111 { + tsu6111_codina_default: tsu6111_codina { + codina_cfg1 { + /* GPIO95 used for IRQ */ + pins = "GPIO95_E8"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + nfc { + pn544_codina_default: pn544_codina { + /* Interrupt line */ + codina_cfg1 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_nopull>; + }; + /* Enable and firmware GPIOs */ + codina_cfg2 { + pins = "GPIO31_V3", "GPIO88_C4"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + bcm4751 { + bcm4751_codina_default: bcm4751_codina { + /* Reset line, start out asserted */ + codina_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + codina_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + codina_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts new file mode 100644 index 000000000000..b21e40da3dfd --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts @@ -0,0 +1,887 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Beam GT-I8530 also known as Gavini. + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8500.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy Beam (GT-I8530)"; + compatible = "samsung,gavini", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb585157lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO193 EN */ + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; // FIXME + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh "TSP" regulator for the touchscreen. + * One GPIO line controls two voltages of 3.3V and 1.8V + * this line is known as "TSP_LDO_ON1" in the schematics. + */ + ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "LDO_TSP_A3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* GPIO94 controls this regulator */ + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_en_default_mode>; + }; + ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_TSP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO94 controls this regulator */ + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both a 3.0V and 1.8V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + lcd_1v8_reg: regulator-gpio-lcd-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 controls this regulator too */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-projector { + linux,code = ; + label = "Projector"; + /* GPIO32 "Projector On HotKey" */ + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds_default_mode>; + used-led { + label = "touchkeys"; + /* GPIO68 */ + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + ktd259: backlight { + compatible = "kinetic,ktd259"; + /* GPIO20 */ + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd259_backlight_default_mode>; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* Yamaha YAS530 magnetometer */ + magnetometer@2e { + compatible = "yamaha,yas530"; + reg = <0x2e>; + /* VDD 3V */ + vdd-supply = <&ab8500_ldo_aux1_reg>; + /* IOVDD 1.8V */ + iovdd-supply = <&ab8500_ldo_aux2_reg>; + /* GPIO204 COMPASS_RST_N */ + reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&yas530_default>; + }; + /* TODO: this should also be used by the NCP6914 Camera power management unit */ + }; + + /* + * TODO: See if we can use the PL023 for this instead. + */ + spi { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO223 */ + cs-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,lms397kf04"; + /* 300 ns at read cycle -> 3 MHz max speed */ + //spi-max-frequency = <3000000>; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&lcd_1v8_reg>; + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd259>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + /* Bit-banged I2C on GPIO201 and GPIO202 also called "MOT_I2C" */ + i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio6 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio6 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_2_default>; + #address-cells = <1>; + #size-cells = <0>; + /* TODO: add the Immersion ISA1200 I2C device here */ + }; + + /* Bit-banged I2C on GPIO196 and GPIO197 also called "MPR_I2C" */ + i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio6 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio6 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_3_default>; + #address-cells = <1>; + #size-cells = <0>; + /* TODO: add the DPP2601 projector I2C device 0x1b here */ + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + /* "flash detect" actually card detect */ + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + serial@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + /* FIXME: add a device for the GPS here */ + }; + + /* Debugging console UART connected to TSU6111RSVR (FSA880) */ + serial@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8500 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <43000>; + }; + + regulator { + ab8500_ldo_aux1 { + /* Used for VDD for sensors */ + regulator-name = "V-SENSORS-VDD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux2 { + /* Used for VIO for sensors */ + regulator-name = "V-SENSORS-VIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux3 { + /* Used for voltage for external MMC/SD card */ + regulator-name = "V-MMC-SD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2910000>; + }; + }; + }; + }; + + /* I2C0 */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + /* FIXME: fix the proximity sensor bindings and driver */ + proximity@39 { + /* Gavini has the GP2A030S00F proximity sensor */ + compatible = "sharp,gp2a030s00f"; + clock-frequency = <400000>; + reg = <0x39>; + /* FIXME: GPIO146 provides power on, IR LED? */ + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + /* GPIO226 interrupt */ + interrupt-parent = <&gpio7>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "1"; + vlogic-supply = <&ab8500_ldo_aux2_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + pinctrl-names = "default"; + pinctrl-0 = <&mpu3050_default>; + + /* + * The MPU-3050 acts as a hub for the + * accelerometer. + */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + /* Bosch BMA222E accelerometer */ + accelerometer@18 { + compatible = "bosch,bma222e"; + reg = <0x18>; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + }; + }; + + /* I2C2 "AGC I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_1_default>; + pinctrl-1 = <&i2c2_b_1_sleep>; + + /* Texas Instruments TSU6111 micro USB switch */ + usb-switch@25 { + compatible = "ti,tsu6111"; + reg = <0x25>; + /* Interrupt JACK_INT_N on GPIO95 */ + interrupt-parent = <&gpio2>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&tsu6111_default>; + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* Melfas MMS136 touchscreen */ + touchscreen@48 { + compatible = "melfas,mms136"; + reg = <0x48>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + /* AVDD is "analog supply", 2.57-3.47 V */ + avdd-supply = <&ldo_tsp_3v3_reg>; + /* VDD is "digital supply" 1.71-3.47V */ + vdd-supply = <&ldo_tsp_1v8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; + /* GPIO for panel reset control */ + panel { + panel_default_mode: panel_default { + gavini_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO6 */ + gavini_cfg1 { + pins = "GPIO6_AF6"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the touchscreen */ + tsp-ldo { + tsp_ldo_en_default_mode: tsp_ldo_default { + /* LDO enable on GPIO94 */ + gavini_cfg1 { + pins = "GPIO94_D7"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* Reset line for the Yamaha YAS530 magnetometer */ + yas530 { + yas530_default: yas530_janice { + janice_cfg1 { + pins = "GPIO204_AF23"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + janice_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the key LED */ + gpio-leds { + gpio_leds_default_mode: gpio_leds_default { + /* EN_LED_LDO on GPIO68 */ + gavini_cfg1 { + pins = "GPIO68_E1"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + backlight { + ktd259_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO20_AB4"; /* LCD_BL_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the touchkeys */ + touchkey-ldo { + tsp_ldo_on2_default_mode: tsp_ldo_on2_default { + /* TSP_LDO_ON2 on GPIO89 */ + gavini_cfg1 { + pins = "GPIO89_E6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + touchkey { + touchkey_default_mode: touchkey_default { + gavini_cfg1 { + /* Interrupt */ + pins = "GPIO198_AG25"; + ste,config = <&gpio_in_nopull>; + }; + gavini_cfg2 { + /* Reset, actually completely unused (not routed) */ + pins = "GPIO205_AG23"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + gavini_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + gavini_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO193 */ + skomer_cfg1 { + pins = "GPIO193_AH27"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO32_V2", /* Projector On HotKey */ + "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Atmel MXT228 touchscreen */ + tsp { + tsp_default: tsp_default { + gavini_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for Invensense MPU3050 gyroscope */ + mpu3050 { + mpu3050_default: mpu3050 { + gavini_cfg1 { + /* GPIO226 used for IRQ */ + pins = "GPIO226_AF8"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for magnetometer and NCP6914 */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + gavini_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the Immersion ISA1200 */ + i2c-gpio-2 { + i2c_gpio_2_default: i2c_gpio_2 { + gavini_cfg1 { + pins = "GPIO201_AF24", "GPIO202_AF25"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the TI DPP2601 */ + i2c-gpio-3 { + i2c_gpio_3_default: i2c_gpio_3 { + gavini_cfg1 { + pins = "GPIO196_AG26", "GPIO197_AH24"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + gavini_cfg1 { + pins = "GPIO220_AH10", "GPIO223_AH9", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + gavini_cfg2 { + pins = "GPIO225_AG8"; + ste,config = <&gpio_in_nopull>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + gavini_cfg1 { + pins = "GPIO220_AH10", "GPIO223_AH9", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + gavini_cfg2 { + pins = "GPIO225_AG8"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + gavini_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + gavini_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + gavini_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + gavini_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* Interrupt line for TI TSU6111 Micro USB switch */ + tsu6111 { + tsu6111_default: tsu6111 { + gavini_cfg1 { + /* GPIO95 used for IRQ */ + pins = "GPIO95_E8"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts new file mode 100644 index 000000000000..f736888474e7 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/* + * Note: This device tree cannot be booted directly with the Samsung bootloader. + * You need an intermediate, device-tree compatible bootloader + * that locks the L2 cache. Otherwise the kernel will crash after decompression. + * + * There is a port of (mainline) U-Boot, see + * https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500#U-Boot + */ +/ { + model = "Samsung Galaxy S III mini (GT-I8190)"; + compatible = "samsung,golden", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb-l1m7flu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + vdd-supply = <&ab8500_ldo_aux4_reg>; + vcc-supply = <&ab8500_ldo_aux6_reg>; + + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_default>; + linux,keycodes = ; + }; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; + }; + + soc { + /* External Micro SD card slot */ + mmc@80126000 { + status = "okay"; + + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + + non-removable; + /* + * Unfortunately, there is no way to enable the UHS + * modes due to a limitation of the SD level translator: + * It will either translate to 2.9V or disconnect the + * DATA lines, so switching to 1.8V signal voltage fails. + */ + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + + vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&sd_level_translator>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + }; + + /* WLAN SDIO */ + mmc@80118000 { + status = "okay"; + + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + + non-removable; + cap-sd-highspeed; + + vmmc-supply = <&wl_reg_on>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + /* GPIO216 (WLAN_HOST_WAKE) */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default>; + }; + }; + + /* eMMC */ + mmc@80005000 { + status = "okay"; + + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + + vmmc-supply = <&vmem_3v3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + }; + + /* BT UART */ + serial@80120000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 (BT_VREG_ON) */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* GPIO199 (BT_WAKE) */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* GPIO97 (BT_HOST_WAKE) */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default>; + }; + }; + + /* GPF UART */ + serial@80121000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + }; + + /* Debugging console UART */ + serial@80007000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + reg = <0x44>; + + /* GPIO146 (PS_INT) */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux8_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&proximity_default>; + + sharp,proximity-far-hysteresis = <0x40>; + sharp,proximity-close-hysteresis = <0x0f>; + }; + }; + + i2c@80128000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + /* GPIO206 (ACC_INT) */ + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_EDGE_RISING>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_default>; + }; + }; + + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + /* VDDA is "analog supply", 2.57-3.47 V */ + vdda-supply = <&ab8500_ldo_aux2_reg>; + /* VDD is "digital supply" 1.71-3.47V */ + vdd-supply = <&ab8500_ldo_aux5_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + regulator { + ab8500_ldo_aux1 { + regulator-name = "sensor_3v"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux2 { + regulator-name = "vreg_tsp_a3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + regulator-name = "vdd_tf_2v91"; + }; + + ab8500_ldo_aux4 { + regulator-name = "key_led_3.3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "vreg_tsp_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + regulator-name = "touch_key_2.2v"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + ab8500_ldo_aux8 { + regulator-name = "sensor_1v8"; + }; + }; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_default_mode>; + + dsi@a0351000 { + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + max-brightness = <15>; + vdd3-supply = <&panel_reg_3v0>; + vci-supply = <&panel_reg_1v8>; + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* ESD (electrostatic discharge) detection interrupt */ + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "esd"; + pinctrl-names = "default"; + pinctrl-0 = <&display_default_mode>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + /* GPIO67 (VOL_UP) */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + /* GPIO92 (VOL_DOWN) */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + /* GPIO91 (HOME_KEY) */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 (MOT_EN) */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + /* External LDO for eMMC */ + vmem_3v3: regulator-vmem { + compatible = "regulator-fixed"; + + regulator-name = "vmem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + startup-delay-us = <200>; + + /* GPIO223 (MEM_LDO_EN) */ + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&mem_ldo_default>; + }; + + /* TI TXS0206-29 level translator for 2.9 V */ + sd_level_translator: regulator-sd-level-translator { + compatible = "regulator-fixed"; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + + startup-delay-us = <200>; + + /* GPIO87 (TXS0206-29_EN) */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* + * WL_REG_ON takes WLAN out of reset and enables the internal regulators. + * The voltage specified here is only used to determine the OCR mask, + * the BCM chip is actually connected directly to VBAT. + */ + wl_reg_on: regulator-wl-reg-on { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg-on"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + startup-delay-us = <100000>; + + /* GPIO215 (WLAN_EN) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_default>; + }; + + /* MIC5366 GPIO-controlled regulator */ + panel_reg_1v8: regulator-panel-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "panel-fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <200>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reg_default_mode>; + }; + + /* MIC5366 GPIO-controlled regulator */ + panel_reg_3v0: regulator-panel-3v0 { + compatible = "regulator-fixed"; + + regulator-name = "panel-fixed-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <200>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reg_default_mode>; + }; +}; + +&pinctrl { + gpio-keys { + gpio_keys_default: gpio_keys_default { + golden_cfg1 { + pins = "GPIO67", /* VOL_UP */ + "GPIO91", /* HOME_KEY */ + "GPIO92"; /* VOL_DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + golden_cfg1 { + pins = "GPIO77", /* TOUCHKEY_SCL */ + "GPIO78"; /* TOUCHKEY_SDA */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + + flash { + gpio_flash_default_mode: flash_default { + golden_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + golden_cfg1 { + pins = "GPIO151", /* COMP_SCL */ + "GPIO152"; /* COMP_SDA */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + + touchkey { + touchkey_default: touchkey_default { + golden_cfg1 { + pins = "GPIO79"; /* TOUCHKEY_INT */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + + sdi0 { + sd_level_translator_default: sd_level_translator_default { + golden_cfg1 { + pins = "GPIO87_B3"; /* TXS0206-29_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + + sdi2 { + mem_ldo_default: mem_ldo_default { + golden_cfg1 { + pins = "GPIO223_AH9"; /* MEM_LDO_EN */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + + mcde { + dsi_default_mode: dsi_default { + default_mux1 { + /* Mux in VSI0 used for DSI TE */ + function = "lcd"; + groups = + "lcdvsi0_a_1"; /* VSI0 for LCD */ + }; + default_cfg1 { + pins = + "GPIO68_E1"; /* VSI0 */ + ste,config = <&in_nopull>; + }; + }; + }; + + display { + display_default_mode: display_default { + golden_cfg1 { + pins = "GPIO139_C9"; /* MIPI_DSI0_RESET_N */ + ste,config = <&gpio_out_lo>; + }; + golden_cfg2 { + pins = "GPIO82_C1"; /* LDI_ESD_DET */ + ste,config = <&gpio_in_pu>; + }; + }; + panel_reg_default_mode: panel_reg_default { + golden_cfg1 { + pins = "GPIO219_AG10"; /* LCD_PWR_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + + proximity { + proximity_default: proximity_default { + golden_cfg1 { + pins = "GPIO146_D13"; /* PS_INT */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + + imu { + imu_default: imu_default { + golden_cfg1 { + pins = "GPIO206_AG24"; /* ACC_INT */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + + tsp { + tsp_default: tsp_default { + golden_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + + wlan { + wlan_default: wlan_default { + golden_cfg1 { + pins = "GPIO216_AG12"; /* WLAN_HOST_WAKE */ + ste,config = <&gpio_in_pd>; + }; + }; + + wlan_en_default: wlan_en_default { + golden_cfg1 { + pins = "GPIO215_AH13"; /* WLAN_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + + bluetooth { + bluetooth_default: bluetooth_default { + golden_cfg1 { + pins = "GPIO199_AH23", /* BT_WAKE */ + "GPIO222_AJ9"; /* BT_VREG_ON */ + ste,config = <&gpio_out_lo>; + }; + golden_cfg2 { + pins = "GPIO97_D9"; /* BT_HOST_WAKE */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + + vibrator { + vibrator_default: vibrator_default { + golden_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; +}; + +&ab8505_gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio_default>; + + gpio { + gpio_default: gpio_default { + golden_mux { + /* Change unused pins to GPIO mode */ + function = "gpio"; + groups = "gpio3_a_1", /* default: SysClkReq4 */ + "gpio14_a_1"; /* default: PWMOut1 */ + }; + golden_cfg1 { + pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts new file mode 100644 index 000000000000..6e586e875565 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts @@ -0,0 +1,998 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy S Advance GT-I9070 also known as Janice. + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8500.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy S Advance (GT-I9070)"; + compatible = "samsung,janice", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb535151vu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; // FIXME + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh "TSP" regulator for the touchscreen. + * One GPIO line controls two voltages of 3.3V and 1.8V + * this line is known as "TSP_LDO_ON1" in the schematics. + */ + ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "LDO_TSP_A3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* GPIO94 controls this regulator */ + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_en_default_mode>; + }; + ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_TSP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO94 controls this regulator */ + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_en_default_mode>; + }; + + /* + * External Ricoh "TSP" regulator for the touchkeys. + * Two GPIO lines controls two voltages of 3.3V and 1.8V + * TSP_LDO_ON2 controls VREG_TOUCHKEY_1V8 + * EN_LED_LDO controls VREG_KLED_3V3 (key LED) + */ + ldo_kled_3v3_reg: regulator-gpio-vreg-kled-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_KLED_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* GPIO68 controls this regulator */ + gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_led_ldo_default_mode>; + }; + ldo_touchkey_1v8_reg: regulator-gpio-vreg-touchkey-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_TOUCHKEY_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO89 controls this regulator */ + gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; + /* 70 ms power-on delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_ldo_on2_default_mode>; + }; + + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls a 3.0V and 1.8V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + lcd_1v8_reg: regulator-gpio-lcd-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* Yamaha YAS530 magnetometer */ + magnetometer@2e { + compatible = "yamaha,yas530"; + reg = <0x2e>; + /* VDD 3V */ + vdd-supply = <&ab8500_ldo_aux1_reg>; + /* IOVDD 1.8V */ + iovdd-supply = <&ab8500_ldo_aux2_reg>; + /* GPIO204 COMPASS_RST_N */ + reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&yas529_default>; + }; + /* TODO: this should also be used by the NCP6914 Camera power management unit */ + }; + + /* + * These pins do have an spi controller, however the controller on + * these pins is not the fully featured PL022 SSP/SPI block but the + * ST Micro diet "PL023" version. One of the lacking features in + * this derivative is 3wire support, so it cannot be used to drive + * this panel interface. We have to use GPIO bit-banging instead. + */ + spi { + compatible = "spi-gpio"; + /* Clock on GPIO220 */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MISO/MOSI on GPIO224 (no separate MISO pin) */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO223 */ + cs-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + vdd3-supply = <&lcd_3v0_reg>; + vci-supply = <&lcd_1v8_reg>; + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + spi-3wire; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + /* + * Current sense amplifier on the light sensor to convert current to + * voltage. We do not know if this is the actual configuration. The + * sense resistor value was found by calibrating in a room ambient + * light with a second mobile phone light sensor as reference. If you + * pry a Janice phone apart and inspect it you may figure this out. + */ + gp2a_shunt: current-sense-shunt { + compatible = "current-sense-shunt"; + io-channels = <&gpadc 0x07>; + shunt-resistor-micro-ohms = <15000000>; /* 15 ohms c:a */ + #io-channel-cells = <0>; + io-channel-ranges; + }; + + /* Bit-banged I2C on GPIO196 and GPIO197 also called "TOUCHKEY_I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio6 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio6 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + vdd-supply = <&ldo_kled_3v3_reg>; + vcc-supply = <&ldo_touchkey_1v8_reg>; + vddio-supply = <&ldo_touchkey_1v8_reg>; + + /* Interrupt on GPIO 198 */ + interrupt-parent = <&gpio6>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_default_mode>; + linux,keycodes = ; + }; + }; + + /* Bit-banged I2C on GPIO201 and GPIO202 also called "MOT_I2C" */ + i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio6 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio6 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_2_default>; + #address-cells = <1>; + #size-cells = <0>; + /* TODO: add the Immersion ISA1200 I2C device here */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC_I2C" */ + i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_3_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* This is only mounted on the GT-I9070P */ + nfc@2b { /* 0x30? */ + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; + /* NFC IRQ on GPIO32 */ + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + /* GPIO 31 */ + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + /* GPIO88 */ + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pn544_janice_default>; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-dir-cmd; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&ab8500_ldo_aux3_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4330B1 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + serial@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + + gnss { + /* + * The Low Noise Amplifier (LNA) power and enablement is controlled + * autonomously by the GSD4t. + * Janice has a SiRFstarIV-based GSD4t + * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R. + */ + compatible = "csr,gsd4t"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO96 */ + sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gsd4t_janice_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; + }; + + /* Debugging console UART connected to TSU6111RSVR (FSA880) */ + serial@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8500 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <15000>; + }; + + regulator { + ab8500_ldo_aux1 { + /* Used for VDD for sensors */ + regulator-name = "V-SENSORS-VDD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux2 { + /* Used for VIO for sensors */ + regulator-name = "V-SENSORS-VIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux3 { + /* Used for voltage for external MMC/SD card */ + regulator-name = "V-MMC-SD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2910000>; + }; + }; + }; + }; + + /* I2C0 */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + /* Janice has the GP2AP002A00F with light sensor */ + compatible = "sharp,gp2ap002a00f"; + clock-frequency = <400000>; + reg = <0x44>; + + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux2_reg>; + /* ADC channel AUX2 to read ALSOUT ambient light sensor out */ + io-channels = <&gp2a_shunt>; + io-channel-names = "alsout"; + pinctrl-names = "default"; + pinctrl-0 = <&gp2ap002_janice_default>; + /* B1 mode (arch/arm/mach-ux500/include/mach/gp2a.h) */ + sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; + }; + }; + + /* I2C1 on GPIO16 and GPIO17 also called "MUS I2C" */ + i2c@80122000 { + status = "okay"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_b_2_default>; + pinctrl-1 = <&i2c1_b_2_sleep>; + + /* Texas Instruments TSU6111 micro USB switch */ + usb-switch@25 { + compatible = "ti,tsu6111"; + reg = <0x25>; + /* Interrupt JACK_INT_N on GPIO95 */ + interrupt-parent = <&gpio2>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&tsu6111_janice_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + /* GPIO226 interrupt */ + interrupt-parent = <&gpio7>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + /* FIXME: no idea about this */ + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + vlogic-supply = <&ab8500_ldo_aux2_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + pinctrl-names = "default"; + pinctrl-0 = <&mpu3050_janice_default>; + + /* + * The MPU-3050 acts as a hub for the + * accelerometer. + */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + /* Bosch BMA222 accelerometer */ + accelerometer@8 { + compatible = "bosch,bma222"; + reg = <0x08>; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* Atmel mXT224E touchscreen */ + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + /* VDDA is "analog supply", 2.57-3.47 V */ + vdda-supply = <&ldo_tsp_3v3_reg>; + /* VDD is "digital supply" 1.71-3.47V */ + vdd-supply = <&ldo_tsp_1v8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; + /* GPIO for panel reset control */ + panel { + panel_default_mode: panel_default { + janice_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO6 */ + janice_cfg1 { + pins = "GPIO6_AF6"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the touchscreen */ + tsp-ldo { + tsp_ldo_en_default_mode: tsp_ldo_default { + /* LDO enable on GPIO94 */ + janice_cfg1 { + pins = "GPIO94_D7"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the key LED */ + key-led { + en_led_ldo_default_mode: en_led_ldo_default { + /* EN_LED_LDO on GPIO68 */ + janice_cfg1 { + pins = "GPIO68_E1"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the touchkeys */ + touchkey-ldo { + tsp_ldo_on2_default_mode: tsp_ldo_on2_default { + /* TSP_LDO_ON2 on GPIO89 */ + janice_cfg1 { + pins = "GPIO89_E6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + touchkey { + touchkey_default_mode: touchkey_default { + janice_cfg1 { + /* Interrupt */ + pins = "GPIO198_AG25"; + ste,config = <&gpio_in_nopull>; + }; + janice_cfg2 { + /* Reset, actually completely unused (not routed) */ + pins = "GPIO205_AG23"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enabled the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + janice_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + janice_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + janice_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Atmel MXT228 touchscreen */ + tsp { + tsp_default: tsp_default { + janice_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Reset line for the Yamaha YAS529 magnetometer */ + yas529 { + yas529_default: yas529_janice { + janice_cfg1 { + pins = "GPIO204_AF23"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* Interrupt line for light/proximity sensor GP2AP002 */ + gp2ap002 { + gp2ap002_janice_default: gp2ap002_janice { + janice_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for Invensense MPU3050 gyroscope */ + mpu3050 { + mpu3050_janice_default: mpu3050_janice { + janice_cfg1 { + /* GPIO226 used for IRQ */ + pins = "GPIO226_AF8"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for magnetometer and NCP6914 */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + janice_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the Cypress touchkeys */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + janice_cfg1 { + pins = "GPIO196_AG26", "GPIO197_AH24"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the Immersion ISA1200 */ + i2c-gpio-2 { + i2c_gpio_2_default: i2c_gpio_2 { + janice_cfg1 { + pins = "GPIO201_AF24", "GPIO202_AF25"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-3 { + i2c_gpio_3_default: i2c_gpio_3 { + janice_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0 { + janice_cfg1 { + pins = "GPIO220_AH10", "GPIO223_AH9", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + /* This pin is unused but belongs with this SPI block */ + janice_cfg2 { + pins = "GPIO225_AG8"; + ste,config = <&in_pd>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + janice_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + janice_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + janice_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + janice_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* Interrupt line for TI TSU6111 Micro USB switch */ + tsu6111 { + tsu6111_janice_default: tsu6111_janice { + janice_cfg1 { + /* GPIO95 used for IRQ */ + pins = "GPIO95_E8"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + nfc { + pn544_janice_default: pn544_janice { + /* Interrupt line */ + janice_cfg1 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_nopull>; + }; + /* Enable and firmware GPIOs */ + janice_cfg2 { + pins = "GPIO31_V3", "GPIO88_C4"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + gsd4t { + gsd4t_janice_default: gsd4t_janice { + /* Reset line, start out asserted */ + janice_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + janice_cfg2 { + pins = "GPIO96_D8"; + ste,config = <&gpio_out_lo>; + }; + /* Unused power enablement line, used in R0.0 and R0.1 boards */ + janice_cfg3 { + pins = "GPIO86_C6"; + ste,config = <&gpio_in_pd>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts new file mode 100644 index 000000000000..ba4421080b2a --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Amp SGH-I407 also known as Kyle. + * + * The code also refers to "Kyle AT&T" reflecting that this mobile phone + * was customized for the AT&T subsidiary Aio Wireless (All In One) and + * offered by the company in 2013. + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy Amp (SGH-I407)"; + compatible = "samsung,kyle", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161la"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + regulator-name = "en-3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both a 3.0V and 1.8V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + lcd_1v8_reg: regulator-gpio-lcd-1v8 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 controls this regulator too */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + wlan_en: regulator-gpio-wlan-en { + compatible = "regulator-fixed"; + regulator-name = "wl-reg-on"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <200000>; + /* GPIO215 WLAN_EN */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_default_mode>; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO 69 */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + /* TODO: this should be used by the NCP6914 Camera power management unit */ + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux6_reg>; + }; + }; + + soc { + // External Micro SD slot + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_1_default>; + pinctrl-1 = <&mc0_a_1_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + // WLAN SDIO channel + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* + * eMMC seems to be mostly Samsung KLM4G1YE4C "4YMD1R" + */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + /* From datasheet page 26 figure 9: 300 ms set-up time for 4GB */ + post-power-on-delay-ms = <300>; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPF UART */ + serial@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_kyle_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; + }; + + /* Debugging console UART connected to AB8505 USB */ + serial@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + regulator { + ab8500_ldo_aux1 { + /* Used for VDD for sensors */ + regulator-name = "AUX1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + /* Supplies the MMS touchscreen only with 3.3V */ + regulator-name = "AUX2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + /* Used for voltage for external MMC/SD card */ + regulator-name = "AUX3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux4 { + regulator-name = "AUX4"; + /* Hammer to 3.3V for the touchscreen */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "AUX5"; + /* 1.8V for the touchscreen */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + regulator-name = "AUX6"; + /* Used by sensors for 1.8 V in R0.1+ */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + /* Unused */ + regulator-name = "AUX8"; + }; + }; + }; + }; + + /* I2C0 */ + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + clock-frequency = <400000>; + reg = <0x44>; + + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux6_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gp2ap002_kyle_default>; + sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; + }; + }; + + /* I2C2 */ + i2c@80128000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + accel@18 { + compatible = "bosch,bma254"; + clock-frequency = <400000>; + reg = <0x18>; + + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux6_reg>; + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* Melfas MMS134S touchscreen */ + touchscreen@48 { + compatible = "melfas,mms134s"; + reg = <0x48>; + /* GPIO218 for IRQ */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + /* AVDD is "analog supply", 2.57-3.47 V */ + avdd-supply = <&ab8500_ldo_aux2_reg>; + /* VDD is "digital supply" 1.71-3.47V */ + vdd-supply = <&ab8500_ldo_aux5_reg>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + + pinctrl-names = "default"; + pinctrl-0 = <&mms134s_kyle_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_default_mode>; + + dsi@a0351000 { + panel { + /* + * NT35510-based Hydis HVA40WV1 + * Apparently some Kyle models can have a NT35512 fitted + * here instead. In that case the boot loader needs to + * modify this compatible. + */ + compatible = "hydis,hva40wv1", "novatek,nt35510"; + reg = <0>; + /* v_lcd_3v0 2.3-4.8V */ + vdd-supply = <&lcd_3v0_reg>; + /* v_lcd_1v8 1.65-3.3V */ + vddi-supply = <&lcd_1v8_reg>; + /* GPIO 139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&display_default_mode>; + backlight = <&ktd253>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_1 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_1_default { + default_cfg1 { + /* GPIO18, 19 & 20 unused so pull down */ + ste,config = <&gpio_in_pd>; + }; + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + + mcde { + dsi_default_mode: dsi_default { + default_mux1 { + /* Mux in VSI0 used for DSI TE */ + function = "lcd"; + groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ + }; + default_cfg1 { + pins = "GPIO68_E1"; /* VSI0 */ + ste,config = <&in_nopull>; + }; + }; + }; + + /* Two GPIO lines used by the display */ + display { + display_default_mode: display_default { + kyle_cfg1 { + /* + * OLED DETECT or check_pba, this appears to be high + * on "PBA" which I guess is "prototype board A". + */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + kyle_cfg2 { + pins = "GPIO139_C9"; + /* + * MIPI_DSI0_RESET_N resets the display, leave high + * (de-asserted) so we only assert reset explicitly + * from the display driver. + */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + kyle_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + + backlight { + gpio_backlight_default_mode: backlight_default { + kyle_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + flash { + gpio_flash_default_mode: flash_default { + kyle_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + kyle_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + kyle_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + kyle_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for light/proximity sensor GP2AP002 */ + gp2ap002 { + gp2ap002_kyle_default: gp2ap002_kyle { + kyle_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for NCP6914 */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + kyle_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for ALPS HSCD compass */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + kyle_cfg1 { + pins = "GPIO151_B17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + kyle_cfg1 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + wlan_en_default_mode: wlan_en_default { + kyle_cfg2 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + kyle_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + kyle_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + kyle_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Interrupt line for the Melfas MMS134S touchscreen */ + touchscreen { + mms134s_kyle_default: mms134s_kyle { + kyle_cfg1 { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + g05ta03 { + g05ta03_kyle_default: g05ta03 { + /* Reset line, start out de-asserted */ + kyle_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + kyle_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; +}; + +&ab8505_gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio_default>; + + gpio { + gpio_default: gpio_default { + kyle_mux { + /* Change unused pins to GPIO mode */ + function = "gpio"; + groups = "gpio3_a_1", /* default: SysClkReq4 */ + "gpio14_a_1"; /* default: PWMOut1 */ + }; + kyle_cfg1 { + pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts new file mode 100644 index 000000000000..064d6fee8821 --- /dev/null +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts @@ -0,0 +1,714 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer. + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung XCover 2 (GT-S7710)"; + compatible = "samsung,skomer", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb485159lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + regulator-name = "en-3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + wlan_en: regulator-gpio-wlan-en { + compatible = "regulator-fixed"; + regulator-name = "wl-reg-on"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <200000>; + /* GPIO215 WLAN_EN */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_default_mode>; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + button-menu { + linux,code = ; + label = "MENU"; + /* GPIO204 */ + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + }; + button-back { + linux,code = ; + label = "BACK"; + /* GPIO205 */ + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + }; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO 69 */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + /* TODO: this should be used by the NCP6914 Camera power management unit */ + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; + }; + + soc { + // External Micro SD slot + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + /* All direction control is used */ + st,sig-pin-fbclk; + full-pwr-cycle; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_1_default>; + pinctrl-1 = <&mc0_a_1_sleep>; + status = "okay"; + }; + + // WLAN SDIO channel + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* + * eMMC seems to be mostly Samsung KLM4G1YE4C "4YMD1R" + */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + /* From datasheet page 26 figure 9: 300 ms set-up time for 4GB */ + post-power-on-delay-ms = <300>; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + serial@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + /* FIXME: not quite working yet, probably needs regulators */ + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + serial@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_skomer_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; + }; + + /* Debugging console UART connected to AB8505 USB */ + serial@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <16000>; + }; + + regulator { + ab8500_ldo_aux1 { + /* Used for VDD for sensors */ + regulator-name = "AUX1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + /* Supplies the Cypress TMA140 touchscreen only with 3.0V */ + regulator-name = "AUX2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux3 { + /* Used for voltage for external MMC/SD card */ + regulator-name = "AUX3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux4 { + regulator-name = "AUX4"; + /* Hammer to 3.0V for the display */ + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "AUX5"; + /* Intended for 1V8 for touchscreen but actually left unused */ + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + ab8500_ldo_aux6 { + regulator-name = "AUX6"; + /* Hammer to 1.8V for the display */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + /* Mostly VIO for sensors */ + regulator-name = "AUX8"; + }; + }; + }; + }; + + /* I2C0 */ + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + clock-frequency = <400000>; + reg = <0x44>; + + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gp2ap002_skomer_default>; + sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; + }; + }; + + + /* I2C2 */ + i2c@80128000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + accel@18 { + compatible = "bosch,bma254"; + clock-frequency = <400000>; + reg = <0x18>; + + /* GPIO224 used as "smart alert" interrupt */ + interrupt-parent = <&gpio7>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&bma254_skomer_default>; + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* Cypress CY8CTMA140 touchscreen */ + touchscreen@20 { + compatible = "cypress,cy8ctma140"; + clock-frequency = <400000>; + reg = <0x20>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-max-pressure = <255>; + + /* GPIO218 for IRQ */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + /* VDD is "digital supply" nominally 1.71-3.6V */ + vdd-supply = <&ab8500_ldo_aux2_reg>; + /* VCPIN is "analog supply", 2.7-3.6 V */ + vcpin-supply = <&ab8500_ldo_aux2_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tma140_skomer_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_default_mode>; + + dsi@a0351000 { + panel { + /* NT35510-based Hydis HVA40WV1 */ + compatible = "hydis,hva40wv1", "novatek,nt35510"; + reg = <0>; + /* v_lcd_3v0 2.3-4.8V */ + vdd-supply = <&ab8500_ldo_aux4_reg>; + /* v_lcd_1v8 1.65-3.3V */ + vddi-supply = <&ab8500_ldo_aux6_reg>; + /* GPIO 139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&display_default_mode>; + backlight = <&ktd253>; + }; + }; + }; + }; +}; + +&pinctrl { + sdi0 { + mc0_a_1_default { + default_cfg1 { + /* GPIO18, 19 & 20 unused so pull down */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + + /* This is a reset line for the eMMC */ + sdi2 { + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + + mcde { + dsi_default_mode: dsi_default { + default_mux1 { + /* Mux in VSI0 used for DSI TE */ + function = "lcd"; + groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ + }; + default_cfg1 { + pins = "GPIO68_E1"; /* VSI0 */ + ste,config = <&in_nopull>; + }; + }; + }; + + /* Two GPIO lines used by the display */ + display { + display_default_mode: display_default { + skomer_cfg1 { + /* + * OLED DETECT or check_pba, this appears to be high + * on "PBA" which I guess is "prototype board A". + */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + skomer_cfg2 { + pins = "GPIO139_C9"; + /* + * MIPI_DSI0_RESET_N resets the display, leave high + * (de-asserted) so we only assert reset explicitly + * from the display driver. + */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + backlight { + gpio_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + flash { + gpio_flash_default_mode: flash_default { + skomer_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + skomer_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + skomer_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6", /* VOL DOWN */ + "GPIO204_AF23", /* MENU */ + "GPIO205_AG23"; /* BACK */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for BMA254 */ + bma254 { + bma254_skomer_default: bma254_skomer { + skomer_cfg1 { + pins = "GPIO224_AG9"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* Interrupt line for light/proximity sensor GP2AP002 */ + gp2ap002 { + gp2ap002_skomer_default: gp2ap002_skomer { + skomer_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for NCP6914 */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + skomer_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for ALPS HSCD compass */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + skomer_cfg1 { + pins = "GPIO151_B17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + skomer_cfg1 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + wlan_en_default_mode: wlan_en_default { + skomer_cfg2 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + skomer_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + skomer_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + skomer_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Interrupt line for the Cypress TMA140 touchscreen */ + touchscreen { + tma140_skomer_default: tma140_skomer { + skomer_cfg1 { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + g05ta03 { + g05ta03_skomer_default: g05ta03 { + /* Reset line, start out de-asserted */ + skomer_cfg1 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + skomer_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; +}; + +&ab8505_gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio_default>; + + gpio { + gpio_default: gpio_default { + skomer_mux { + /* Change unused pins to GPIO mode */ + function = "gpio"; + groups = "gpio3_a_1", /* default: SysClkReq4 */ + "gpio14_a_1"; /* default: PWMOut1 */ + }; + skomer_cfg1 { + pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih407-b2120.dts b/arch/arm/boot/dts/st/stih407-b2120.dts new file mode 100644 index 000000000000..9c79982ee7ba --- /dev/null +++ b/arch/arm/boot/dts/st/stih407-b2120.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Giuseppe Cavallaro + */ +/dts-v1/; +#include "stih407.dtsi" +#include "stihxxx-b2120.dtsi" +/ { + model = "STiH407 B2120"; + compatible = "st,stih407-b2120", "st,stih407"; + + chosen { + stdout-path = &sbc_serial0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + serial0 = &sbc_serial0; + ethernet0 = ðernet0; + }; + +}; diff --git a/arch/arm/boot/dts/st/stih407-clock.dtsi b/arch/arm/boot/dts/st/stih407-clock.dtsi new file mode 100644 index 000000000000..350bcfcf498b --- /dev/null +++ b/arch/arm/boot/dts/st/stih407-clock.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics R&D Limited + */ +#include +/ { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0x10000>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-clkgen-plla9"; + + clocks = <&clk_sysin>; + }; + + clk_m_a9: clk-m-a9 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + }; + + clockgen-a@90ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,clkgen-pll0-a0"; + + clocks = <&clk_sysin>; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen", "st,flexgen-stih407-a0"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + }; + }; + + clk_s_c0: clockgen-c@9103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,clkgen-pll0-c0"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,clkgen-pll1-c0"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-c0"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; + }; + }; + + clockgen-d0@9104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-d0"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + }; + }; + + clockgen-d2@9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-d2"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + }; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-d3"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi new file mode 100644 index 000000000000..5ebb77947fd9 --- /dev/null +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -0,0 +1,991 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Giuseppe Cavallaro + */ +#include "stih407-pinctrl.dtsi" +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gp0_reserved: rproc@45000000 { + compatible = "shared-dma-pool"; + reg = <0x45000000 0x00400000>; + no-map; + }; + + delta_reserved: rproc@44000000 { + compatible = "shared-dma-pool"; + reg = <0x44000000 0x01000000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; + + /* kHz uV */ + operating-points = <1500000 0 + 1200000 0 + 800000 0 + 500000 0>; + + clocks = <&clk_m_a9>; + clock-names = "cpu"; + clock-latency = <100000>; + cpu0-supply = <&pwm_regulator>; + st,syscfg = <&syscfg_core 0x8e0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; + + /* kHz uV */ + operating-points = <1500000 0 + 1200000 0 + 800000 0 + 500000 0>; + }; + }; + + intc: interrupt-controller@8761000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x08761000 0x1000>, <0x08760100 0x100>; + }; + + scu@8760000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x08760000 0x1000>; + }; + + timer@8760200 { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-global-timer"; + reg = <0x08760200 0x100>; + interrupts = ; + clocks = <&arm_periph_clk>; + }; + + l2: cache-controller@8762000 { + compatible = "arm,pl310-cache"; + reg = <0x08762000 0x1000>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + arm-pmu { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + pwm_regulator: pwm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 3 8448>; + regulator-name = "CPU_1V0_AVS"; + regulator-min-microvolt = <784000>; + regulator-max-microvolt = <1299000>; + regulator-always-on; + max-duty-cycle = <255>; + status = "okay"; + }; + + restart: restart-controller { + compatible = "st,stih407-restart"; + st,syscfg = <&syscfg_sbc_reg>; + status = "okay"; + }; + + powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; + #reset-cells = <1>; + }; + + softreset: softreset-controller { + compatible = "st,stih407-softreset"; + #reset-cells = <1>; + }; + + picophyreset: picophyreset-controller { + compatible = "st,stih407-picophyreset"; + #reset-cells = <1>; + }; + + irq-syscfg { + compatible = "st,stih407-irq-syscfg"; + st,syscfg = <&syscfg_core>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + + usb2_picophy0: phy1 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0x100 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY2_RESET>; + reset-names = "global", "port"; + }; + + miphy28lp_phy: miphy28lp { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>; + reg-names = "sata-up", + "pcie-up", + "pipew"; + + st,syscfg = <0x114 0x818 0xe0 0xec>; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port@9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>; + reg-names = "sata-up", + "pcie-up", + "pipew"; + + st,syscfg = <0x118 0x81c 0xe4 0xf0>; + + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port@8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>; + reg-names = "pipew", + "usb3-up"; + + st,syscfg = <0x11c 0x820>; + + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; + + st231_gp0: st231-gp0 { + compatible = "st,st231-rproc"; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; + }; + + st231_delta: st231-delta { + compatible = "st,st231-rproc"; + memory-region = <&delta_reserved>; + resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x224>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; + }; + + delta0 { + compatible = "st,st-delta"; + clock-names = "delta", + "delta-st231", + "delta-flash-promip"; + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; + + syscfg_sbc: sbc-syscfg@9620000 { + compatible = "st,stih407-sbc-syscfg", "syscon"; + reg = <0x9620000 0x1000>; + }; + + syscfg_front: front-syscfg@9280000 { + compatible = "st,stih407-front-syscfg", "syscon"; + reg = <0x9280000 0x1000>; + }; + + syscfg_rear: rear-syscfg@9290000 { + compatible = "st,stih407-rear-syscfg", "syscon"; + reg = <0x9290000 0x1000>; + }; + + syscfg_flash: flash-syscfg@92a0000 { + compatible = "st,stih407-flash-syscfg", "syscon"; + reg = <0x92a0000 0x1000>; + }; + + syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { + compatible = "st,stih407-sbc-reg-syscfg", "syscon"; + reg = <0x9600000 0x1000>; + }; + + syscfg_core: core-syscfg@92b0000 { + compatible = "st,stih407-core-syscfg", "syscon"; + reg = <0x92b0000 0x1000>; + + sti_sasg_codec: sti-sasg-codec { + compatible = "st,stih407-sas-codec"; + #sound-dai-cells = <1>; + status = "disabled"; + st,syscfg = <&syscfg_core>; + }; + }; + + syscfg_lpm: lpm-syscfg@94b5100 { + compatible = "st,stih407-lpm-syscfg", "syscon"; + reg = <0x94b5100 0x1000>; + }; + + /* Display */ + vtg_main: sti-vtg-main@8d02800 { + compatible = "st,vtg"; + reg = <0x8d02800 0x200>; + interrupts = ; + }; + + vtg_aux: sti-vtg-aux@8d00200 { + compatible = "st,vtg"; + reg = <0x8d00200 0x100>; + interrupts = ; + }; + + serial@9830000 { + compatible = "st,asc"; + reg = <0x9830000 0x2c>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + /* Pinctrl moved out to a per-board configuration */ + + status = "disabled"; + }; + + serial@9831000 { + compatible = "st,asc"; + reg = <0x9831000 0x2c>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial1>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + + status = "disabled"; + }; + + serial@9832000 { + compatible = "st,asc"; + reg = <0x9832000 0x2c>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial2>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + + status = "disabled"; + }; + + /* SBC_ASC0 - UART10 */ + sbc_serial0: serial@9530000 { + compatible = "st,asc"; + reg = <0x9530000 0x2c>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial0>; + clocks = <&clk_sysin>; + + status = "disabled"; + }; + + serial@9531000 { + compatible = "st,asc"; + reg = <0x9531000 0x2c>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial1>; + clocks = <&clk_sysin>; + + status = "disabled"; + }; + + i2c@9840000 { + compatible = "st,comms-ssc4-i2c"; + interrupts = ; + reg = <0x9840000 0x110>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c@9841000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9841000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c@9842000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9842000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c@9843000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9843000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c@9844000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9844000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c@9845000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9845000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + + /* SSCs on SBC */ + i2c@9540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9540000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c@9541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9541000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9840000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9840000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-0 = <&pinctrl_spi0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9841000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9841000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9842000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9842000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9843000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9843000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9844000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9844000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + /* SBC SSC */ + spi@9540000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9540000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi10_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9541000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9541000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi11_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9542000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9542000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi12_default>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + mmc0: sdhci@9060000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + status = "disabled"; + reg = <0x09060000 0x7ff>, <0x9061008 0x20>; + reg-names = "mmc", "top-mmc-delay"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc", "icn"; + clocks = <&clk_s_c0_flexgen CLK_MMC_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; + bus-width = <8>; + }; + + mmc1: sdhci@9080000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + status = "disabled"; + reg = <0x09080000 0x7ff>; + reg-names = "mmc"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + clock-names = "mmc", "icn"; + clocks = <&clk_s_c0_flexgen CLK_MMC_1>, + <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; + resets = <&softreset STIH407_MMC1_SOFTRESET>; + bus-width = <4>; + }; + + /* Watchdog and Real-Time Clock */ + lpc@8787000 { + compatible = "st,stih407-lpc"; + reg = <0x8787000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + timeout-sec = <120>; + st,syscfg = <&syscfg_core>; + st,lpc-mode = ; + }; + + lpc@8788000 { + compatible = "st,stih407-lpc"; + reg = <0x8788000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_1>; + st,lpc-mode = ; + }; + + spifsm: spifsm@9022000{ + compatible = "st,spi-fsm"; + reg = <0x9022000 0x1000>; + reg-names = "spi-fsm"; + clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; + clock-names = "emi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsm>; + st,syscfg = <&syscfg_core>; + st,boot-device-reg = <0x8c4>; + st,boot-device-spi = <0x68>; + + status = "disabled"; + }; + + sata0: sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + ports-implemented = <0x1>; + + status = "disabled"; + }; + + sata1: sata@9b28000 { + compatible = "st,ahci"; + reg = <0x9b28000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port1 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA1_POWERDOWN>, + <&softreset STIH407_SATA1_SOFTRESET>, + <&softreset STIH407_SATA1_PWR_SOFTRESET>; + reset-names = "pwr-dwn", + "sw-rst", + "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + ports-implemented = <0x1>; + + status = "disabled"; + }; + + + st_dwc3: dwc3@8f94000 { + compatible = "st,stih407-dwc3"; + reg = <0x08f94000 0x1000>, <0x110 0x4>; + reg-names = "reg-glue", "syscfg-reg"; + st,syscfg = <&syscfg_core>; + resets = <&powerdown STIH407_USB3_POWERDOWN>, + <&softreset STIH407_MIPHY2_SOFTRESET>; + reset-names = "powerdown", "softreset"; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + ranges; + + status = "disabled"; + + dwc3: usb@9900000 { + compatible = "snps,dwc3"; + reg = <0x09900000 0x100000>; + interrupts = ; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy0>, + <&phy_port2 PHY_TYPE_USB3>; + snps,dis_u3_susphy_quirk; + }; + }; + + /* COMMS PWM Module */ + pwm0: pwm@9810000 { + compatible = "st,sti-pwm"; + #pwm-cells = <2>; + reg = <0x9810000 0x68>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <1>; + + status = "disabled"; + }; + + /* SBC PWM Module */ + pwm1: pwm@9510000 { + compatible = "st,sti-pwm"; + #pwm-cells = <2>; + reg = <0x9510000 0x68>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <4>; + + status = "disabled"; + }; + + rng10: rng@8a89000 { + compatible = "st,rng"; + reg = <0x08a89000 0x1000>; + clocks = <&clk_sysin>; + status = "okay"; + }; + + rng11: rng@8a8a000 { + compatible = "st,rng"; + reg = <0x08a8a000 0x1000>; + clocks = <&clk_sysin>; + status = "okay"; + }; + + ethernet0: dwmac@9630000 { + device_type = "network"; + status = "disabled"; + compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; + reg = <0x9630000 0x8000>, <0x80 0x4>; + reg-names = "stmmaceth", "sti-ethconf"; + + st,syscon = <&syscfg_sbc_reg 0x80>; + st,gmac_en; + resets = <&softreset STIH407_ETH1_SOFTRESET>; + reset-names = "stmmaceth"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + + /* DMA Bus Mode */ + snps,pbl = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + + clock-names = "stmmaceth", "sti-ethclk"; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_ETH_PHY>; + }; + + mailbox0: mailbox@8f00000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f00000 0x1000>; + interrupts = ; + #mbox-cells = <2>; + mbox-name = "a9"; + status = "okay"; + }; + + mailbox1: mailbox@8f01000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f01000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_1"; + status = "okay"; + }; + + mailbox2: mailbox@8f02000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f02000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_0"; + status = "okay"; + }; + + mailbox3: mailbox@8f03000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f03000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_audio_video"; + status = "okay"; + }; + + /* fdma audio */ + fdma0: dma-controller@8e20000 { + compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; + reg = <0x8e20000 0x8000>, + <0x8e30000 0x3000>, + <0x8e37000 0x1000>, + <0x8e38000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + }; + + /* fdma app */ + fdma1: dma-controller@8e40000 { + compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; + reg = <0x8e40000 0x8000>, + <0x8e50000 0x3000>, + <0x8e57000 0x1000>, + <0x8e58000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + + status = "disabled"; + }; + + /* fdma free running */ + fdma2: dma-controller@8e60000 { + compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; + reg = <0x8e60000 0x8000>, + <0x8e70000 0x3000>, + <0x8e77000 0x1000>, + <0x8e78000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + + status = "disabled"; + }; + + sti_uni_player0: sti-uni-player@8d80000 { + compatible = "st,stih407-uni-player-hdmi"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; + assigned-clock-rates = <50000000>; + reg = <0x8d80000 0x158>; + interrupts = ; + dmas = <&fdma0 2 0 1>; + dma-names = "tx"; + + status = "disabled"; + }; + + sti_uni_player1: sti-uni-player@8d81000 { + compatible = "st,stih407-uni-player-pcm-out"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_1>; + assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; + assigned-clock-rates = <50000000>; + reg = <0x8d81000 0x158>; + interrupts = ; + dmas = <&fdma0 3 0 1>; + dma-names = "tx"; + + status = "disabled"; + }; + + sti_uni_player2: sti-uni-player@8d82000 { + compatible = "st,stih407-uni-player-dac"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; + assigned-clock-rates = <50000000>; + reg = <0x8d82000 0x158>; + interrupts = ; + dmas = <&fdma0 4 0 1>; + dma-names = "tx"; + + status = "disabled"; + }; + + sti_uni_player3: sti-uni-player@8d85000 { + compatible = "st,stih407-uni-player-spdif"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; + assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; + assigned-clock-rates = <50000000>; + reg = <0x8d85000 0x158>; + interrupts = ; + dmas = <&fdma0 7 0 1>; + dma-names = "tx"; + + status = "disabled"; + }; + + sti_uni_reader0: sti-uni-reader@8d83000 { + compatible = "st,stih407-uni-reader-pcm_in"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8d83000 0x158>; + interrupts = ; + dmas = <&fdma0 5 0 1>; + dma-names = "rx"; + + status = "disabled"; + }; + + sti_uni_reader1: sti-uni-reader@8d84000 { + compatible = "st,stih407-uni-reader-hdmi"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8d84000 0x158>; + interrupts = ; + dmas = <&fdma0 6 0 1>; + dma-names = "rx"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih407-pinctrl.dtsi b/arch/arm/boot/dts/st/stih407-pinctrl.dtsi new file mode 100644 index 000000000000..2cf335714ca2 --- /dev/null +++ b/arch/arm/boot/dts/st/stih407-pinctrl.dtsi @@ -0,0 +1,1262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Giuseppe Cavallaro + */ +#include "st-pincfg.h" +#include +/ { + + aliases { + /* 0-5: PIO_SBC */ + gpio0 = &pio0; + gpio1 = &pio1; + gpio2 = &pio2; + gpio3 = &pio3; + gpio4 = &pio4; + gpio5 = &pio5; + /* 10-19: PIO_FRONT0 */ + gpio6 = &pio10; + gpio7 = &pio11; + gpio8 = &pio12; + gpio9 = &pio13; + gpio10 = &pio14; + gpio11 = &pio15; + gpio12 = &pio16; + gpio13 = &pio17; + gpio14 = &pio18; + gpio15 = &pio19; + /* 20: PIO_FRONT1 */ + gpio16 = &pio20; + /* 30-35: PIO_REAR */ + gpio17 = &pio30; + gpio18 = &pio31; + gpio19 = &pio32; + gpio20 = &pio33; + gpio21 = &pio34; + gpio22 = &pio35; + /* 40-42: PIO_FLASH */ + gpio23 = &pio40; + gpio24 = &pio41; + gpio25 = &pio42; + }; + + soc { + pin-controller-sbc@961f080 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + reg = <0x0961f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupt-names = "irqmux"; + ranges = <0 0x09610000 0x6000>; + + pio0: gpio@9610000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO0"; + }; + pio1: gpio@9611000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO1"; + }; + pio2: gpio@9612000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO2"; + }; + pio3: gpio@9613000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x100>; + st,bank-name = "PIO3"; + }; + pio4: gpio@9614000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x100>; + st,bank-name = "PIO4"; + }; + + pio5: gpio@9615000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x100>; + st,bank-name = "PIO5"; + st,retime-pin-mask = <0x3f>; + }; + + cec0 { + pinctrl_cec0_default: cec0-default { + st,pins { + hdmi_cec = <&pio2 4 ALT1 BIDIR>; + }; + }; + }; + + rc { + pinctrl_ir: ir0 { + st,pins { + ir = <&pio4 0 ALT2 IN>; + }; + }; + + pinctrl_uhf: uhf0 { + st,pins { + ir = <&pio4 1 ALT2 IN>; + }; + }; + + pinctrl_tx: tx0 { + st,pins { + tx = <&pio4 2 ALT2 OUT>; + }; + }; + + pinctrl_tx_od: tx_od0 { + st,pins { + tx_od = <&pio4 3 ALT2 OUT>; + }; + }; + }; + + /* SBC_ASC0 - UART10 */ + sbc_serial0 { + pinctrl_sbc_serial0: sbc_serial0-0 { + st,pins { + tx = <&pio3 4 ALT1 OUT>; + rx = <&pio3 5 ALT1 IN>; + }; + }; + }; + /* SBC_ASC1 - UART11 */ + sbc_serial1 { + pinctrl_sbc_serial1: sbc_serial1-0 { + st,pins { + tx = <&pio2 6 ALT3 OUT>; + rx = <&pio2 7 ALT3 IN>; + }; + }; + }; + + i2c10 { + pinctrl_i2c10_default: i2c10-default { + st,pins { + sda = <&pio4 6 ALT1 BIDIR>; + scl = <&pio4 5 ALT1 BIDIR>; + }; + }; + }; + + i2c11 { + pinctrl_i2c11_default: i2c11-default { + st,pins { + sda = <&pio5 1 ALT1 BIDIR>; + scl = <&pio5 0 ALT1 BIDIR>; + }; + }; + }; + + keyscan { + pinctrl_keyscan: keyscan { + st,pins { + keyin0 = <&pio4 0 ALT6 IN>; + keyin1 = <&pio4 5 ALT4 IN>; + keyin2 = <&pio0 4 ALT2 IN>; + keyin3 = <&pio2 6 ALT2 IN>; + + keyout0 = <&pio4 6 ALT4 OUT>; + keyout1 = <&pio1 7 ALT2 OUT>; + keyout2 = <&pio0 6 ALT2 OUT>; + keyout3 = <&pio2 7 ALT2 OUT>; + }; + }; + }; + + gmac1 { + /* + * Almost all the boards based on STiH407 SoC have an embedded + * switch where the mdio/mdc have been used for managing the SMI + * iface via I2C. For this reason these lines can be allocated + * by using dedicated configuration (in case of there will be a + * standard PHY transceiver on-board). + */ + pinctrl_rgmii1: rgmii1-0 { + st,pins { + + txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; + rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; + }; + }; + + pinctrl_rgmii1_mdio: rgmii1-mdio { + st,pins { + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + }; + }; + + pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { + st,pins { + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + + pinctrl_mii1: mii1 { + st,pins { + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&pio0 7 ALT1 IN BYPASS 1000>; + + mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&pio1 2 ALT1 IN BYPASS 1000>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + + pinctrl_rmii1: rmii1-0 { + st,pins { + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + + pinctrl_rmii1_phyclk: rmii1_phyclk { + st,pins { + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + + pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { + st,pins { + phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; + }; + }; + }; + + pwm1 { + pinctrl_pwm1_chan0_default: pwm1-0-default { + st,pins { + pwm-out = <&pio3 0 ALT1 OUT>; + pwm-capturein = <&pio3 2 ALT1 IN>; + }; + }; + pinctrl_pwm1_chan1_default: pwm1-1-default { + st,pins { + pwm-capturein = <&pio4 3 ALT1 IN>; + pwm-out = <&pio4 4 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan2_default: pwm1-2-default { + st,pins { + pwm-out = <&pio4 6 ALT3 OUT>; + }; + }; + pinctrl_pwm1_chan3_default: pwm1-3-default { + st,pins { + pwm-out = <&pio4 7 ALT3 OUT>; + }; + }; + }; + + spi10 { + pinctrl_spi10_default: spi10-4w-alt1-0 { + st,pins { + mtsr = <&pio4 6 ALT1 OUT>; + mrst = <&pio4 7 ALT1 IN>; + scl = <&pio4 5 ALT1 OUT>; + }; + }; + + pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { + st,pins { + mtsr = <&pio4 6 ALT1 BIDIR_PU>; + scl = <&pio4 5 ALT1 OUT>; + }; + }; + }; + + spi11 { + pinctrl_spi11_default: spi11-4w-alt2-0 { + st,pins { + mtsr = <&pio3 1 ALT2 OUT>; + mrst = <&pio3 0 ALT2 IN>; + scl = <&pio3 2 ALT2 OUT>; + }; + }; + + pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { + st,pins { + mtsr = <&pio3 1 ALT2 BIDIR_PU>; + scl = <&pio3 2 ALT2 OUT>; + }; + }; + }; + + spi12 { + pinctrl_spi12_default: spi12-4w-alt2-0 { + st,pins { + mtsr = <&pio3 6 ALT2 OUT>; + mrst = <&pio3 4 ALT2 IN>; + scl = <&pio3 7 ALT2 OUT>; + }; + }; + + pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { + st,pins { + mtsr = <&pio3 6 ALT2 BIDIR_PU>; + scl = <&pio3 7 ALT2 OUT>; + }; + }; + }; + }; + + pin-controller-front0@920f080 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-front-pinctrl"; + st,syscfg = <&syscfg_front>; + reg = <0x0920f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupt-names = "irqmux"; + ranges = <0 0x09200000 0x10000>; + + pio10: pio@9200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO10"; + }; + pio11: pio@9201000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO11"; + }; + pio12: pio@9202000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO12"; + }; + pio13: pio@9203000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x100>; + st,bank-name = "PIO13"; + }; + pio14: pio@9204000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x100>; + st,bank-name = "PIO14"; + }; + pio15: pio@9205000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x100>; + st,bank-name = "PIO15"; + }; + pio16: pio@9206000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x100>; + st,bank-name = "PIO16"; + }; + pio17: pio@9207000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x100>; + st,bank-name = "PIO17"; + }; + pio18: pio@9208000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x100>; + st,bank-name = "PIO18"; + }; + pio19: pio@9209000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x100>; + st,bank-name = "PIO19"; + }; + + /* Comms */ + serial0 { + pinctrl_serial0: serial0-0 { + st,pins { + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; + }; + }; + pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { + st,pins { + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; + cts = <&pio17 2 ALT1 IN>; + rts = <&pio17 3 ALT1 OUT>; + }; + }; + }; + + serial1 { + pinctrl_serial1: serial1-0 { + st,pins { + tx = <&pio16 0 ALT1 OUT>; + rx = <&pio16 1 ALT1 IN>; + }; + }; + }; + + serial2 { + pinctrl_serial2: serial2-0 { + st,pins { + tx = <&pio15 0 ALT1 OUT>; + rx = <&pio15 1 ALT1 IN>; + }; + }; + }; + + mmc1 { + pinctrl_sd1: sd1-0 { + st,pins { + sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; + sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; + sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; + sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; + sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; + sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; + sd_led = <&pio16 6 ALT6 OUT>; + sd_pwren = <&pio16 7 ALT6 OUT>; + sd_cd = <&pio19 0 ALT6 IN>; + sd_wp = <&pio19 1 ALT6 IN>; + }; + }; + }; + + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&pio10 6 ALT2 BIDIR>; + scl = <&pio10 5 ALT2 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&pio11 1 ALT2 BIDIR>; + scl = <&pio11 0 ALT2 BIDIR>; + }; + }; + }; + + i2c2 { + pinctrl_i2c2_default: i2c2-default { + st,pins { + sda = <&pio15 6 ALT2 BIDIR>; + scl = <&pio15 5 ALT2 BIDIR>; + }; + }; + + pinctrl_i2c2_alt2_1: i2c2-alt2-1 { + st,pins { + sda = <&pio12 6 ALT2 BIDIR>; + scl = <&pio12 5 ALT2 BIDIR>; + }; + }; + }; + + i2c3 { + pinctrl_i2c3_default: i2c3-alt1-0 { + st,pins { + sda = <&pio18 6 ALT1 BIDIR>; + scl = <&pio18 5 ALT1 BIDIR>; + }; + }; + pinctrl_i2c3_alt1_1: i2c3-alt1-1 { + st,pins { + sda = <&pio17 7 ALT1 BIDIR>; + scl = <&pio17 6 ALT1 BIDIR>; + }; + }; + pinctrl_i2c3_alt3_0: i2c3-alt3-0 { + st,pins { + sda = <&pio13 6 ALT3 BIDIR>; + scl = <&pio13 5 ALT3 BIDIR>; + }; + }; + }; + + spi0 { + pinctrl_spi0_default: spi0-4w-alt2-0 { + st,pins { + mtsr = <&pio10 6 ALT2 OUT>; + mrst = <&pio10 7 ALT2 IN>; + scl = <&pio10 5 ALT2 OUT>; + }; + }; + + pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { + st,pins { + mtsr = <&pio10 6 ALT2 BIDIR_PU>; + scl = <&pio10 5 ALT2 OUT>; + }; + }; + + pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { + st,pins { + mtsr = <&pio19 7 ALT1 OUT>; + mrst = <&pio19 5 ALT1 IN>; + scl = <&pio19 6 ALT1 OUT>; + }; + }; + + pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { + st,pins { + mtsr = <&pio19 7 ALT1 BIDIR_PU>; + scl = <&pio19 6 ALT1 OUT>; + }; + }; + }; + + spi1 { + pinctrl_spi1_default: spi1-4w-alt2-0 { + st,pins { + mtsr = <&pio11 1 ALT2 OUT>; + mrst = <&pio11 2 ALT2 IN>; + scl = <&pio11 0 ALT2 OUT>; + }; + }; + + pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { + st,pins { + mtsr = <&pio11 1 ALT2 BIDIR_PU>; + scl = <&pio11 0 ALT2 OUT>; + }; + }; + + pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { + st,pins { + mtsr = <&pio14 3 ALT1 OUT>; + mrst = <&pio14 4 ALT1 IN>; + scl = <&pio14 2 ALT1 OUT>; + }; + }; + + pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { + st,pins { + mtsr = <&pio14 3 ALT1 BIDIR_PU>; + scl = <&pio14 2 ALT1 OUT>; + }; + }; + }; + + spi2 { + pinctrl_spi2_default: spi2-4w-alt2-0 { + st,pins { + mtsr = <&pio12 6 ALT2 OUT>; + mrst = <&pio12 7 ALT2 IN>; + scl = <&pio12 5 ALT2 OUT>; + }; + }; + + pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { + st,pins { + mtsr = <&pio12 6 ALT2 BIDIR_PU>; + scl = <&pio12 5 ALT2 OUT>; + }; + }; + + pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { + st,pins { + mtsr = <&pio14 6 ALT1 OUT>; + mrst = <&pio14 7 ALT1 IN>; + scl = <&pio14 5 ALT1 OUT>; + }; + }; + + pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { + st,pins { + mtsr = <&pio14 6 ALT1 BIDIR_PU>; + scl = <&pio14 5 ALT1 OUT>; + }; + }; + + pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { + st,pins { + mtsr = <&pio15 6 ALT2 OUT>; + mrst = <&pio15 7 ALT2 IN>; + scl = <&pio15 5 ALT2 OUT>; + }; + }; + + pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { + st,pins { + mtsr = <&pio15 6 ALT2 BIDIR_PU>; + scl = <&pio15 5 ALT2 OUT>; + }; + }; + }; + + spi3 { + pinctrl_spi3_default: spi3-4w-alt3-0 { + st,pins { + mtsr = <&pio13 6 ALT3 OUT>; + mrst = <&pio13 7 ALT3 IN>; + scl = <&pio13 5 ALT3 OUT>; + }; + }; + + pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { + st,pins { + mtsr = <&pio13 6 ALT3 BIDIR_PU>; + scl = <&pio13 5 ALT3 OUT>; + }; + }; + + pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { + st,pins { + mtsr = <&pio17 7 ALT1 OUT>; + mrst = <&pio17 5 ALT1 IN>; + scl = <&pio17 6 ALT1 OUT>; + }; + }; + + pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { + st,pins { + mtsr = <&pio17 7 ALT1 BIDIR_PU>; + scl = <&pio17 6 ALT1 OUT>; + }; + }; + + pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { + st,pins { + mtsr = <&pio18 6 ALT1 OUT>; + mrst = <&pio18 7 ALT1 IN>; + scl = <&pio18 5 ALT1 OUT>; + }; + }; + + pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { + st,pins { + mtsr = <&pio18 6 ALT1 BIDIR_PU>; + scl = <&pio18 5 ALT1 OUT>; + }; + }; + }; + + tsin0 { + pinctrl_tsin0_parallel: tsin0_parallel { + st,pins { + DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin0_serial: tsin0_serial { + st,pins { + DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin1 { + pinctrl_tsin1_parallel: tsin1_parallel { + st,pins { + DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin1_serial: tsin1_serial { + st,pins { + DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin2 { + pinctrl_tsin2_parallel: tsin2_parallel { + st,pins { + DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin2_serial: tsin2_serial { + st,pins { + DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin3 { + pinctrl_tsin3_serial: tsin3_serial { + st,pins { + DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin4 { + pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { + st,pins { + DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; + ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; + PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin5 { + pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { + st,pins { + DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { + st,pins { + DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsout0 { + pinctrl_tsout0_parallel: tsout0_parallel { + st,pins { + DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; + VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsout0_serial: tsout0_serial { + st,pins { + DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; + VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsout1 { + pinctrl_tsout1_serial: tsout1_serial { + st,pins { + DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; + VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + mtsin0 { + pinctrl_mtsin0_parallel: mtsin0_parallel { + st,pins { + DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + systrace { + pinctrl_systrace_default: systrace-default { + st,pins { + trc_data0 = <&pio11 3 ALT5 OUT>; + trc_data1 = <&pio11 4 ALT5 OUT>; + trc_data2 = <&pio11 5 ALT5 OUT>; + trc_data3 = <&pio11 6 ALT5 OUT>; + trc_clk = <&pio11 7 ALT5 OUT>; + }; + }; + }; + }; + + pin-controller-front1@921f080 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-front-pinctrl"; + st,syscfg = <&syscfg_front>; + reg = <0x0921f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupt-names = "irqmux"; + ranges = <0 0x09210000 0x10000>; + + pio20: pio@9210000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO20"; + }; + + tsin4 { + pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { + st,pins { + DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + }; + + pin-controller-rear@922f080 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-rear-pinctrl"; + st,syscfg = <&syscfg_rear>; + reg = <0x0922f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupt-names = "irqmux"; + ranges = <0 0x09220000 0x6000>; + + pio30: gpio@9220000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO30"; + }; + pio31: gpio@9221000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO31"; + }; + pio32: gpio@9222000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO32"; + }; + pio33: gpio@9223000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x100>; + st,bank-name = "PIO33"; + }; + pio34: gpio@9224000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x100>; + st,bank-name = "PIO34"; + }; + pio35: gpio@9225000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x100>; + st,bank-name = "PIO35"; + st,retime-pin-mask = <0x7f>; + }; + + i2c4 { + pinctrl_i2c4_default: i2c4-default { + st,pins { + sda = <&pio30 1 ALT1 BIDIR>; + scl = <&pio30 0 ALT1 BIDIR>; + }; + }; + }; + + i2c5 { + pinctrl_i2c5_default: i2c5-default { + st,pins { + sda = <&pio34 4 ALT1 BIDIR>; + scl = <&pio34 3 ALT1 BIDIR>; + }; + }; + }; + + usb3 { + pinctrl_usb3: usb3-2 { + st,pins { + usb-oc-detect = <&pio35 4 ALT1 IN>; + usb-pwr-enable = <&pio35 5 ALT1 OUT>; + usb-vbus-valid = <&pio35 6 ALT1 IN>; + }; + }; + }; + + pwm0 { + pinctrl_pwm0_chan0_default: pwm0-0-default { + st,pins { + pwm-capturein = <&pio31 0 ALT1 IN>; + pwm-out = <&pio31 1 ALT1 OUT>; + }; + }; + }; + + spi4 { + pinctrl_spi4_default: spi4-4w-alt1-0 { + st,pins { + mtsr = <&pio30 1 ALT1 OUT>; + mrst = <&pio30 2 ALT1 IN>; + scl = <&pio30 0 ALT1 OUT>; + }; + }; + + pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { + st,pins { + mtsr = <&pio30 1 ALT1 BIDIR_PU>; + scl = <&pio30 0 ALT1 OUT>; + }; + }; + + pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { + st,pins { + mtsr = <&pio34 1 ALT3 OUT>; + mrst = <&pio34 2 ALT3 IN>; + scl = <&pio34 0 ALT3 OUT>; + }; + }; + + pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { + st,pins { + mtsr = <&pio34 1 ALT3 BIDIR_PU>; + scl = <&pio34 0 ALT3 OUT>; + }; + }; + }; + + i2s_out { + pinctrl_i2s_8ch_out: i2s_8ch_out{ + st,pins { + mclk = <&pio33 5 ALT1 OUT>; + lrclk = <&pio33 7 ALT1 OUT>; + sclk = <&pio33 6 ALT1 OUT>; + data0 = <&pio33 4 ALT1 OUT>; + data1 = <&pio34 0 ALT1 OUT>; + data2 = <&pio34 1 ALT1 OUT>; + data3 = <&pio34 2 ALT1 OUT>; + }; + }; + + pinctrl_i2s_2ch_out: i2s_2ch_out{ + st,pins { + mclk = <&pio33 5 ALT1 OUT>; + lrclk = <&pio33 7 ALT1 OUT>; + sclk = <&pio33 6 ALT1 OUT>; + data0 = <&pio33 4 ALT1 OUT>; + }; + }; + }; + + i2s_in { + pinctrl_i2s_8ch_in: i2s_8ch_in{ + st,pins { + mclk = <&pio32 5 ALT1 IN>; + lrclk = <&pio32 7 ALT1 IN>; + sclk = <&pio32 6 ALT1 IN>; + data0 = <&pio32 4 ALT1 IN>; + data1 = <&pio33 0 ALT1 IN>; + data2 = <&pio33 1 ALT1 IN>; + data3 = <&pio33 2 ALT1 IN>; + data4 = <&pio33 3 ALT1 IN>; + }; + }; + + pinctrl_i2s_2ch_in: i2s_2ch_in{ + st,pins { + mclk = <&pio32 5 ALT1 IN>; + lrclk = <&pio32 7 ALT1 IN>; + sclk = <&pio32 6 ALT1 IN>; + data0 = <&pio32 4 ALT1 IN>; + }; + }; + }; + + spdif_out { + pinctrl_spdif_out: spdif_out{ + st,pins { + spdif_out = <&pio34 7 ALT1 OUT>; + }; + }; + }; + + serial3 { + pinctrl_serial3: serial3-0 { + st,pins { + tx = <&pio31 3 ALT1 OUT>; + rx = <&pio31 4 ALT1 IN>; + }; + }; + }; + }; + + pin-controller-flash@923f080 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-flash-pinctrl"; + st,syscfg = <&syscfg_flash>; + reg = <0x0923f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupt-names = "irqmux"; + ranges = <0 0x09230000 0x3000>; + + pio40: gpio@9230000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x100>; + st,bank-name = "PIO40"; + }; + pio41: gpio@9231000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO41"; + }; + pio42: gpio@9232000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO42"; + }; + + mmc0 { + pinctrl_mmc0: mmc0-0 { + st,pins { + emmc_clk = <&pio40 6 ALT1 BIDIR>; + emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; + emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; + emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; + emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; + emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; + emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; + emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; + emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; + emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; + }; + }; + pinctrl_sd0: sd0-0 { + st,pins { + sd_clk = <&pio40 6 ALT1 BIDIR>; + sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; + sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; + sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; + sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; + sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; + sd_led = <&pio42 0 ALT2 OUT>; + sd_pwren = <&pio42 2 ALT2 OUT>; + sd_vsel = <&pio42 3 ALT2 OUT>; + sd_cd = <&pio42 4 ALT2 IN>; + sd_wp = <&pio42 5 ALT2 IN>; + }; + }; + }; + + fsm { + pinctrl_fsm: fsm { + st,pins { + spi-fsm-clk = <&pio40 1 ALT1 OUT>; + spi-fsm-cs = <&pio40 0 ALT1 OUT>; + spi-fsm-mosi = <&pio40 2 ALT1 OUT>; + spi-fsm-miso = <&pio40 3 ALT1 IN>; + spi-fsm-hol = <&pio40 5 ALT1 OUT>; + spi-fsm-wp = <&pio40 4 ALT1 OUT>; + }; + }; + }; + + nand { + pinctrl_nand: nand { + st,pins { + nand_cs1 = <&pio40 6 ALT3 OUT>; + nand_cs0 = <&pio40 7 ALT3 OUT>; + nand_d0 = <&pio41 0 ALT3 BIDIR>; + nand_d1 = <&pio41 1 ALT3 BIDIR>; + nand_d2 = <&pio41 2 ALT3 BIDIR>; + nand_d3 = <&pio41 3 ALT3 BIDIR>; + nand_d4 = <&pio41 4 ALT3 BIDIR>; + nand_d5 = <&pio41 5 ALT3 BIDIR>; + nand_d6 = <&pio41 6 ALT3 BIDIR>; + nand_d7 = <&pio41 7 ALT3 BIDIR>; + nand_we = <&pio42 0 ALT3 OUT>; + nand_dqs = <&pio42 1 ALT3 OUT>; + nand_ale = <&pio42 2 ALT3 OUT>; + nand_cle = <&pio42 3 ALT3 OUT>; + nand_rnb = <&pio42 4 ALT3 IN>; + nand_oe = <&pio42 5 ALT3 OUT>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih407.dtsi b/arch/arm/boot/dts/st/stih407.dtsi new file mode 100644 index 000000000000..aca43d2bdaad --- /dev/null +++ b/arch/arm/boot/dts/st/stih407.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 STMicroelectronics Limited. + * Author: Gabriel Fernandez + */ +#include "stih407-clock.dtsi" +#include "stih407-family.dtsi" +#include +/ { + soc { + sti-display-subsystem@0 { + compatible = "st,sti-display-subsystem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0>; + assigned-clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>; + + assigned-clock-parents = <0>, + <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; + + ranges; + + sti-compositor@9d11000 { + compatible = "st,stih407-compositor"; + reg = <0x9d11000 0x1000>; + + clock-names = "compo_main", + "compo_aux", + "pix_main", + "pix_aux", + "pix_gdp1", + "pix_gdp2", + "pix_gdp3", + "pix_gdp4", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + reset-names = "compo-main", "compo-aux"; + resets = <&softreset STIH407_COMPO_SOFTRESET>, + <&softreset STIH407_COMPO_SOFTRESET>; + st,vtg = <&vtg_main>, <&vtg_aux>; + }; + + sti-tvout@8d08000 { + compatible = "st,stih407-tvout"; + reg = <0x8d08000 0x1000>; + reg-names = "tvout-reg"; + reset-names = "tvout"; + resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + #address-cells = <1>; + #size-cells = <1>; + assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>; + + assigned-clock-parents = <&clk_s_d2_quadfs 0>, + <&clk_tmdsout_hdmi>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d0_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + }; + + sti_hdmi: sti-hdmi@8d04000 { + compatible = "st,stih407-hdmi"; + reg = <0x8d04000 0x1000>; + reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; + interrupts = ; + interrupt-names = "irq"; + clock-names = "pix", + "tmds", + "phy", + "audio", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; + reset-names = "hdmi"; + resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; + ddc = <&hdmiddc>; + }; + + sti-hda@8d02000 { + compatible = "st,stih407-hda"; + reg = <0x8d02000 0x400>, <0x92b0120 0x4>; + reg-names = "hda-reg", "video-dacs-ctrl"; + clock-names = "pix", + "hddac", + "main_parent", + "aux_parent"; + clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih410-b2120.dts b/arch/arm/boot/dts/st/stih410-b2120.dts new file mode 100644 index 000000000000..538ff98ca1b1 --- /dev/null +++ b/arch/arm/boot/dts/st/stih410-b2120.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Peter Griffin + */ +/dts-v1/; +#include "stih410.dtsi" +#include "stihxxx-b2120.dtsi" +/ { + model = "STiH410 B2120"; + compatible = "st,stih410-b2120", "st,stih410"; + + chosen { + stdout-path = &sbc_serial0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + serial0 = &sbc_serial0; + ethernet0 = ðernet0; + }; + + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + + soc { + + mmc0: sdhci@9060000 { + max-frequency = <200000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + }; + + ohci0: usb@9a03c00 { + status = "okay"; + }; + + ehci0: usb@9a03e00 { + status = "okay"; + }; + + ohci1: usb@9a83c00 { + status = "okay"; + }; + + ehci1: usb@9a83e00 { + status = "okay"; + }; + + sti-display-subsystem@0 { + sti-hda@8d02000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih410-b2260.dts b/arch/arm/boot/dts/st/stih410-b2260.dts new file mode 100644 index 000000000000..240b62040000 --- /dev/null +++ b/arch/arm/boot/dts/st/stih410-b2260.dts @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 STMicroelectronics (R&D) Limited. + * Author: Patrice Chotard + */ +/dts-v1/; +#include "stih410.dtsi" +#include + +/ { + model = "STiH410 B2260"; + compatible = "st,stih410-b2260", "st,stih410"; + + chosen { + stdout-path = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + serial1 = &uart1; + ethernet0 = ðernet0; + }; + + leds { + compatible = "gpio-leds"; + led-user-green-1 { + label = "User_green_1"; + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-user-green-2 { + label = "User_green_2"; + gpios = <&pio4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-user-green-3 { + label = "User_green_3"; + gpios = <&pio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-user-green-4 { + label = "User_green_4"; + gpios = <&pio2 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2260"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + /* DAC */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; + }; + }; + + miphy28lp_phy: miphy28lp { + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + + soc { + /* Low speed expansion connector */ + uart0: serial@9830000 { + label = "LS-UART0"; + pinctrl-names = "default", "no-hw-flowctrl"; + pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; + pinctrl-1 = <&pinctrl_serial0>; + rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; + }; + + /* Low speed expansion connector */ + uart1: serial@9831000 { + label = "LS-UART1"; + status = "okay"; + }; + + /* Low speed expansion connector */ + spi0: spi@9844000 { + label = "LS-SPI0"; + cs-gpios = <&pio30 3 0>; + status = "okay"; + }; + + /* Low speed expansion connector */ + i2c0: i2c@9840000 { + label = "LS-I2C0"; + status = "okay"; + }; + + /* Low speed expansion connector */ + i2c1: i2c@9841000 { + label = "LS-I2C1"; + status = "okay"; + }; + + /* high speed expansion connector */ + i2c2: i2c@9842000 { + label = "HS-I2C2"; + pinctrl-0 = <&pinctrl_i2c2_alt2_1>; + status = "okay"; + }; + + /* high speed expansion connector */ + i2c3: i2c@9843000 { + label = "HS-I2C3"; + pinctrl-0 = <&pinctrl_i2c3_alt3_0>; + status = "okay"; + }; + + mmc0: sdhci@9060000 { + pinctrl-0 = <&pinctrl_sd0>; + bus-width = <4>; + status = "okay"; + }; + + /* high speed expansion connector */ + mmc1: sdhci@9080000 { + status = "okay"; + }; + + pwm0: pwm@9810000 { + status = "okay"; + }; + + pwm1: pwm@9510000 { + status = "okay"; + }; + + ohci0: usb@9a03c00 { + status = "okay"; + }; + + ehci0: usb@9a03e00 { + status = "okay"; + }; + + ohci1: usb@9a83c00 { + status = "okay"; + }; + + ehci1: usb@9a83e00 { + status = "okay"; + }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + + ethernet0: dwmac@9630000 { + phy-mode = "rgmii"; + pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; + + snps,reset-gpio = <&pio0 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + + status = "okay"; + }; + + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; + /* SSC11 to HDMI */ + hdmiddc: i2c@9541000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + status = "okay"; + }; + + sata1: sata@9b28000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih410-clock.dtsi b/arch/arm/boot/dts/st/stih410-clock.dtsi new file mode 100644 index 000000000000..abac98a1810b --- /dev/null +++ b/arch/arm/boot/dts/st/stih410-clock.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics R&D Limited + */ +#include +/ { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "st,stih410-clk", "simple-bus"; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0x10000>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-clkgen-plla9"; + + clocks = <&clk_sysin>; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + }; + + clockgen-a@90ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,clkgen-pll0-a0"; + + clocks = <&clk_sysin>; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen", "st,flexgen-stih410-a0"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + }; + }; + + clk_s_c0: clockgen-c@9103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,clkgen-pll0-c0"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,clkgen-pll1-c0"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih410-c0"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; + }; + }; + + clockgen-d0@9104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih410-d0"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + }; + }; + + clockgen-d2@9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-d2"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + }; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-d3"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih410-pinctrl.dtsi b/arch/arm/boot/dts/st/stih410-pinctrl.dtsi new file mode 100644 index 000000000000..e6eadd124416 --- /dev/null +++ b/arch/arm/boot/dts/st/stih410-pinctrl.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin + */ +#include "st-pincfg.h" +/ { + + soc { + pin-controller-rear@922f080 { + + usb0 { + pinctrl_usb0: usb2-0 { + st,pins { + usb-oc-detect = <&pio35 0 ALT1 IN>; + usb-pwr-enable = <&pio35 1 ALT1 OUT>; + }; + }; + }; + + usb1 { + pinctrl_usb1: usb2-1 { + st,pins { + usb-oc-detect = <&pio35 2 ALT1 IN>; + usb-pwr-enable = <&pio35 3 ALT1 OUT>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi new file mode 100644 index 000000000000..29e95e9d3229 --- /dev/null +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin + */ +#include "stih410-clock.dtsi" +#include "stih407-family.dtsi" +#include "stih410-pinctrl.dtsi" +#include +/ { + aliases { + bdisp0 = &bdisp0; + }; + + usb2_picophy1: phy2 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xf8 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names = "global", "port"; + + status = "disabled"; + }; + + usb2_picophy2: phy3 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xfc 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names = "global", "port"; + + status = "disabled"; + }; + + soc { + ohci0: usb@9a03c00 { + compatible = "st,st-ohci-300x"; + reg = <0x9a03c00 0x100>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, + <&softreset STIH407_USB2_PORT0_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy1>; + phy-names = "usb"; + + status = "disabled"; + }; + + ehci0: usb@9a03e00 { + compatible = "st,st-ehci-300x"; + reg = <0x9a03e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, + <&softreset STIH407_USB2_PORT0_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy1>; + phy-names = "usb"; + + status = "disabled"; + }; + + ohci1: usb@9a83c00 { + compatible = "st,st-ohci-300x"; + reg = <0x9a83c00 0x100>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, + <&softreset STIH407_USB2_PORT1_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy2>; + phy-names = "usb"; + + status = "disabled"; + }; + + ehci1: usb@9a83e00 { + compatible = "st,st-ehci-300x"; + reg = <0x9a83e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, + <&softreset STIH407_USB2_PORT1_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy2>; + phy-names = "usb"; + + status = "disabled"; + }; + + sti-display-subsystem@0 { + compatible = "st,sti-display-subsystem"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0 0>; + assigned-clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>; + + assigned-clock-parents = <0>, + <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + + assigned-clock-rates = <297000000>, + <297000000>, + <0>, + <400000000>, + <400000000>; + + ranges; + + sti-compositor@9d11000 { + compatible = "st,stih407-compositor"; + reg = <0x9d11000 0x1000>; + + clock-names = "compo_main", + "compo_aux", + "pix_main", + "pix_aux", + "pix_gdp1", + "pix_gdp2", + "pix_gdp3", + "pix_gdp4", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + reset-names = "compo-main", "compo-aux"; + resets = <&softreset STIH407_COMPO_SOFTRESET>, + <&softreset STIH407_COMPO_SOFTRESET>; + st,vtg = <&vtg_main>, <&vtg_aux>; + }; + + sti-tvout@8d08000 { + compatible = "st,stih407-tvout"; + reg = <0x8d08000 0x1000>; + reg-names = "tvout-reg"; + reset-names = "tvout"; + resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + #address-cells = <1>; + #size-cells = <1>; + assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>; + + assigned-clock-parents = <&clk_s_d2_quadfs 0>, + <&clk_tmdsout_hdmi>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d0_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + }; + + sti_hdmi: sti-hdmi@8d04000 { + compatible = "st,stih407-hdmi"; + reg = <0x8d04000 0x1000>; + reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; + interrupts = ; + interrupt-names = "irq"; + clock-names = "pix", + "tmds", + "phy", + "audio", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; + reset-names = "hdmi"; + resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; + ddc = <&hdmiddc>; + }; + + sti-hda@8d02000 { + compatible = "st,stih407-hda"; + status = "disabled"; + reg = <0x8d02000 0x400>, <0x92b0120 0x4>; + reg-names = "hda-reg", "video-dacs-ctrl"; + clock-names = "pix", + "hddac", + "main_parent", + "aux_parent"; + clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + }; + + sti-hqvdp@9c00000 { + compatible = "st,stih407-hqvdp"; + reg = <0x9C00000 0x100000>; + clock-names = "hqvdp", "pix_main"; + clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; + reset-names = "hqvdp"; + resets = <&softreset STIH407_HDQVDP_SOFTRESET>; + st,vtg = <&vtg_main>; + }; + }; + + bdisp0:bdisp@9f10000 { + compatible = "st,stih407-bdisp"; + reg = <0x9f10000 0x1000>; + interrupts = ; + clock-names = "bdisp"; + clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; + }; + + hva@8c85000 { + compatible = "st,st-hva"; + reg = <0x8c85000 0x400>, <0x6000000 0x40000>; + reg-names = "hva_registers", "hva_esram"; + interrupts = , + ; + clock-names = "clk_hva"; + clocks = <&clk_s_c0_flexgen CLK_HVA>; + }; + + thermal@91a0000 { + compatible = "st,stih407-thermal"; + reg = <0x91a0000 0x28>; + clock-names = "thermal"; + clocks = <&clk_sysin>; + interrupts = ; + }; + + cec@94a087c { + compatible = "st,stih-cec"; + reg = <0x94a087c 0x64>; + clocks = <&clk_sysin>; + clock-names = "cec-clk"; + interrupts = ; + interrupt-names = "cec-irq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cec0_default>; + resets = <&softreset STIH407_LPM_SOFTRESET>; + hdmi-phandle = <&sti_hdmi>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih418-b2199.dts b/arch/arm/boot/dts/st/stih418-b2199.dts new file mode 100644 index 000000000000..53ac6c2b7b7d --- /dev/null +++ b/arch/arm/boot/dts/st/stih418-b2199.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 STMicroelectronics (R&D) Limited. + * Author: Maxime Coquelin + */ +/dts-v1/; +#include "stih418.dtsi" +#include +/ { + model = "STiH418 B2199"; + compatible = "st,stih418-b2199", "st,stih418"; + + chosen { + stdout-path = &sbc_serial0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0xc0000000>; + }; + + aliases { + serial0 = &sbc_serial0; + ethernet0 = ðernet0; + }; + + leds { + compatible = "gpio-leds"; + led-red { + label = "Front Panel LED"; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + led-green { + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + soc { + sbc_serial0: serial@9530000 { + status = "okay"; + }; + + i2c@9842000 { + status = "okay"; + }; + + i2c@9843000 { + status = "okay"; + }; + + i2c@9844000 { + status = "okay"; + }; + + i2c@9845000 { + status = "okay"; + }; + + i2c@9540000 { + status = "okay"; + }; + + /* SSC11 to HDMI */ + i2c@9541000 { + status = "okay"; + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + + mmc1: sdhci@9080000 { + status = "okay"; + }; + + mmc0: sdhci@9060000 { + status = "okay"; + max-frequency = <200000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + non-removable; + }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + + ethernet0: dwmac@9630000 { + st,tx-retime-src = "clkgen"; + status = "okay"; + phy-mode = "rgmii"; + fixed-link = <0 1 1000 0 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih418-b2264.dts b/arch/arm/boot/dts/st/stih418-b2264.dts new file mode 100644 index 000000000000..fc32a03073b6 --- /dev/null +++ b/arch/arm/boot/dts/st/stih418-b2264.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 STMicroelectronics + * Author: Alain Volmat + */ +/dts-v1/; +#include "stih418.dtsi" +#include +/ { + model = "STiH418 B2264"; + compatible = "st,stih418-b2264", "st,stih418"; + + chosen { + stdout-path = &sbc_serial0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0xc0000000>; + }; + + cpus { + cpu@0 { + operating-points-v2 = <&cpu_opp_table>; + /* u-boot puts hpen in SBC dmem at 0xb8 offset */ + cpu-release-addr = <0x94100b8>; + }; + cpu@1 { + operating-points-v2 = <&cpu_opp_table>; + /* u-boot puts hpen in SBC dmem at 0xb8 offset */ + cpu-release-addr = <0x94100b8>; + }; + cpu@2 { + operating-points-v2 = <&cpu_opp_table>; + /* u-boot puts hpen in SBC dmem at 0xb8 offset */ + cpu-release-addr = <0x94100b8>; + }; + cpu@3 { + operating-points-v2 = <&cpu_opp_table>; + /* u-boot puts hpen in SBC dmem at 0xb8 offset */ + cpu-release-addr = <0x94100b8>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <784000>; + }; + opp01 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <784000>; + }; + opp02 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <784000>; + }; + opp03 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <784000>; + }; + opp04 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <784000>; + }; + }; + + aliases { + ttyAS0 = &sbc_serial0; + ethernet0 = ðernet0; + }; + + soc { + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pin-controller-sbc@961f080 { + gmac1 { + rgmii1-0 { + st,pins { + rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>; + rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>; + }; + }; + }; + }; + + }; +}; + +&ehci0 { + status = "okay"; +}; + +ðernet0 { + phy-mode = "rgmii"; + pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; + st,tx-retime-src = "clkgen"; + + snps,reset-gpio = <&pio0 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + + status = "okay"; +}; + +&miphy28lp_phy { + phy_port0: port@9b22000 { + st,sata-gen = <2>; /* SATA GEN3 */ + st,osc-rdy; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sbc_serial0 { + status = "okay"; +}; + +&spifsm { + status = "okay"; +}; + +&st_dwc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stih418-clock.dtsi b/arch/arm/boot/dts/st/stih418-clock.dtsi new file mode 100644 index 000000000000..e1749e92a2e7 --- /dev/null +++ b/arch/arm/boot/dts/st/stih418-clock.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 STMicroelectronics R&D Limited + */ +#include +/ { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "st,stih418-clk", "simple-bus"; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0x10000>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih418-clkgen-plla9"; + + clocks = <&clk_sysin>; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + }; + + clockgen-a@90ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,clkgen-pll0-a0"; + + clocks = <&clk_sysin>; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen", "st,flexgen-stih410-a0"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + }; + }; + + clk_s_c0: clockgen-c@9103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,clkgen-pll0-c0"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,clkgen-pll1-c0"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih418-c0"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; + }; + }; + + clockgen-d0@9104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih410-d0"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + }; + }; + + clockgen-d2@9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih418-d2"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + }; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen", "st,flexgen-stih407-d3"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi new file mode 100644 index 000000000000..b35b9b7a7ccc --- /dev/null +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin + */ +#include "stih418-clock.dtsi" +#include "stih407-family.dtsi" +#include "stih410-pinctrl.dtsi" +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; + }; + }; + + usb2_picophy1: phy2 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xf8 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names = "global", "port"; + }; + + usb2_picophy2: phy3 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xfc 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names = "global", "port"; + }; + + soc { + rng11: rng@8a8a000 { + status = "disabled"; + }; + + ohci0: usb@9a03c00 { + compatible = "st,st-ohci-300x"; + reg = <0x9a03c00 0x100>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, + <&softreset STIH407_USB2_PORT0_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy1>; + phy-names = "usb"; + }; + + ehci0: usb@9a03e00 { + compatible = "st,st-ehci-300x"; + reg = <0x9a03e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, + <&softreset STIH407_USB2_PORT0_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy1>; + phy-names = "usb"; + }; + + ohci1: usb@9a83c00 { + compatible = "st,st-ohci-300x"; + reg = <0x9a83c00 0x100>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, + <&softreset STIH407_USB2_PORT1_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy2>; + phy-names = "usb"; + }; + + ehci1: usb@9a83e00 { + compatible = "st,st-ehci-300x"; + reg = <0x9a83e00 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, + <&softreset STIH407_USB2_PORT1_SOFTRESET>; + reset-names = "power", "softreset"; + phys = <&usb2_picophy2>; + phy-names = "usb"; + }; + + mmc0: sdhci@9060000 { + assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; + assigned-clock-parents = <&clk_s_c0_pll1 0>; + assigned-clock-rates = <200000000>; + }; + + thermal@91a0000 { + compatible = "st,stih407-thermal"; + reg = <0x91a0000 0x28>; + clock-names = "thermal"; + clocks = <&clk_sysin>; + interrupts = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stihxxx-b2120.dtsi b/arch/arm/boot/dts/st/stihxxx-b2120.dtsi new file mode 100644 index 000000000000..8d9a2dfa76f1 --- /dev/null +++ b/arch/arm/boot/dts/st/stihxxx-b2120.dtsi @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Giuseppe Cavallaro + */ +#include +#include +#include +/ { + leds { + compatible = "gpio-leds"; + led-red { + label = "Front Panel LED"; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + led-green { + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2120"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + /* HDMI */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + /* DAC */ + format = "i2s"; + mclk-fs = <256>; + frame-inversion; + cpu { + sound-dai = <&sti_uni_player2>; + }; + + codec { + sound-dai = <&sti_sasg_codec 1>; + }; + }; + + simple-audio-card,dai-link@2 { + reg = <2>; + /* SPDIF */ + format = "left_j"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player3>; + }; + + codec { + sound-dai = <&sti_sasg_codec 0>; + }; + }; + }; + + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + soc { + sbc_serial0: serial@9530000 { + status = "okay"; + }; + + pwm0: pwm@9810000 { + status = "okay"; + }; + + pwm1: pwm@9510000 { + status = "okay"; + }; + + ssc2: i2c@9842000 { + status = "okay"; + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + + ssc3: i2c@9843000 { + status = "okay"; + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + + i2c@9844000 { + status = "okay"; + }; + + i2c@9845000 { + status = "okay"; + }; + + i2c@9540000 { + status = "okay"; + }; + + mmc0: sdhci@9060000 { + non-removable; + status = "okay"; + }; + + mmc1: sdhci@9080000 { + status = "okay"; + }; + + /* SSC11 to HDMI */ + hdmiddc: i2c@9541000 { + status = "okay"; + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + + ethernet0: dwmac@9630000 { + st,tx-retime-src = "clkgen"; + status = "okay"; + phy-mode = "rgmii"; + fixed-link = <0 1 1000 0 0>; + }; + + demux@8a20000 { + compatible = "st,stih407-c8sectpfe"; + status = "okay"; + reg = <0x08a20000 0x10000>, + <0x08a00000 0x4000>; + reg-names = "c8sectpfe", "c8sectpfe-ram"; + interrupts = , + ; + interrupt-names = "c8sectpfe-error-irq", + "c8sectpfe-idle-irq"; + pinctrl-0 = <&pinctrl_tsin0_serial>; + pinctrl-1 = <&pinctrl_tsin0_parallel>; + pinctrl-2 = <&pinctrl_tsin3_serial>; + pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; + pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; + pinctrl-names = "tsin0-serial", + "tsin0-parallel", + "tsin3-serial", + "tsin4-serial", + "tsin5-serial"; + clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; + clock-names = "c8sectpfe"; + + /* tsin0 is TSA on NIMA */ + tsin0: port { + tsin-num = <0>; + serial-not-parallel; + i2c-bus = <&ssc2>; + reset-gpios = <&pio15 4 GPIO_ACTIVE_LOW>; + dvb-card = ; + }; + }; + + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; + + sti_uni_player2: sti-uni-player@8d82000 { + status = "okay"; + }; + + sti_uni_player3: sti-uni-player@8d85000 { + status = "okay"; + }; + + syscfg_core: core-syscfg@92b0000 { + sti_sasg_codec: sti-sasg-codec { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_out>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts new file mode 100644 index 000000000000..576235ec3c51 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -0,0 +1,337 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f429.dtsi" +#include "stm32f429-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "STMicroelectronics STM32429i-EVAL board"; + compatible = "st,stm32429i-eval", "st,stm32f429"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; + + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; + + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "vref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_panel: vdd-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&gpiog 6 1>; + linux,default-trigger = "heartbeat"; + }; + led-orange { + gpios = <&gpiog 7 1>; + }; + led-red { + gpios = <&gpiog 10 1>; + }; + led-blue { + gpios = <&gpiog 12 1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "Wake up"; + linux,code = ; + gpios = <&gpioa 0 0>; + }; + button-1 { + label = "Tamper"; + linux,code = ; + gpios = <&gpioc 13 0>; + }; + }; + + usbotg_hs_phy: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + panel_rgb: panel-rgb { + compatible = "ampire,am-480272h3tmqw-t01h"; + power-supply = <&vdd_panel>; + status = "okay"; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc3_in8_pin>; + vdda-supply = <&vdda>; + vref-supply = <&vref>; + status = "okay"; + adc3: adc@200 { + st,adc-channels = <8>; + status = "okay"; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&crc { + status = "okay"; +}; + +&dcmi { + status = "okay"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-type = ; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; + clocks = <&clk_ext_camera>; + clock-names = "xvclk"; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&dcmi_0>; + }; + }; + }; + + stmpe1600: stmpe1600@42 { + compatible = "st,stmpe1600"; + reg = <0x42>; + interrupts = <8 3>; + interrupt-parent = <&gpioi>; + interrupt-controller; + wakeup-source; + + stmpegpio: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&iwdg { + status = "okay"; + timeout-sec = <32>; +}; + +<dc { + status = "okay"; + pinctrl-0 = <<dc_pins_a>; + pinctrl-names = "default"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + +&mac { + status = "okay"; + pinctrl-0 = <ðernet_mii>; + pinctrl-names = "default"; + phy-mode = "mii"; + phy-handle = <&phy1>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sdio { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; + max-frequency = <12500000>; +}; + +&timers1 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@0 { + status = "okay"; + }; +}; + +&timers3 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@2 { + status = "okay"; + }; +}; + +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts new file mode 100644 index 000000000000..a293e65141c6 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -0,0 +1,222 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include "stm32f746-pinctrl.dtsi" +#include +#include + +/ { + model = "STMicroelectronics STM32746g-EVAL board"; + compatible = "st,stm32746g-eval", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; + + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&gpiof 10 1>; + linux,default-trigger = "heartbeat"; + }; + led-orange { + gpios = <&stmfx_pinctrl 17 1>; + }; + led-red { + gpios = <&gpiob 7 1>; + }; + led-blue { + gpios = <&stmfx_pinctrl 19 1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "Wake up"; + linux,code = ; + gpios = <&gpioc 13 0>; + }; + }; + + joystick { + compatible = "gpio-keys"; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + button-1 { + label = "JoyDown"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + button-3 { + label = "JoyRight"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + button-4 { + label = "JoyUp"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&crc { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + stmfx: stmfx@42 { + compatible = "st,stmfx-0300"; + reg = <0x42>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpioi>; + + stmfx_pinctrl: pinctrl { + compatible = "st,stmfx-0300-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&stmfx_pinctrl 0 0 24>; + + joystick_pins: joystick { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + drive-push-pull; + bias-pull-up; + }; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sdio1 { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + broken-cd; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; + bus-width = <4>; +}; + +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi new file mode 100644 index 000000000000..3bb812d6399e --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi @@ -0,0 +1,482 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + soc { + pinctrl: pinctrl@40020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; + st,bank-name = "GPIOK"; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = ; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usbotg_fs_pins_a: usbotg-fs-0 { + pins { + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_b: usbotg-fs-1 { + pins { + pinmux = , /* OTG_HS_ID */ + , /* OTG_HS_DM */ + ; /* OTG_HS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT*/ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ethernet_mii: mii-0 { + pins { + pinmux = , /* ETH_MII_TXD0_ETH_RMII_TXD0 */ + , /* ETH_MII_TXD1_ETH_RMII_TXD1 */ + , /* ETH_MII_TXD2 */ + , /* ETH_MII_TXD3 */ + , /* ETH_MII_TX_CLK */ + , /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ + , /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ + , /* ETH_MII_RXD0_ETH_RMII_RXD0 */ + , /* ETH_MII_RXD1_ETH_RMII_RXD1 */ + , /* ETH_MII_RXD2 */ + ; /* ETH_MII_RXD3 */ + slew-rate = <2>; + }; + }; + + adc3_in8_pin: adc-200 { + pins { + pinmux = ; + }; + }; + + pwm1_pins: pwm1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH1N */ + ; /* TIM1_BKIN */ + }; + }; + + pwm3_pins: pwm3-0 { + pins { + pinmux = , /* TIM3_CH1 */ + ; /* TIM3_CH2 */ + }; + }; + + i2c1_pins: i2c1-0 { + pins { + pinmux = , /* I2C1_SDA */ + ; /* I2C1_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; + + ltdc_pins_a: ltdc-0 { + pins { + pinmux = , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_CLK */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6*/ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3*/ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + , /* LCD_B7 */ + ; /* LCD_DE */ + slew-rate = <2>; + }; + }; + + ltdc_pins_b: ltdc-1 { + pins { + pinmux = , + /* LCD_HSYNC */ + , + /* LCD_VSYNC */ + , + /* LCD_CLK */ + , + /* LCD_R2 */ + , + /* LCD_R3 */ + , + /* LCD_R4 */ + , + /* LCD_R5 */ + , + /* LCD_R6*/ + , + /* LCD_R7 */ + , + /* LCD_G2 */ + , + /* LCD_G3 */ + , + /* LCD_G4 */ + , + /* LCD_B2 */ + , + /* LCD_B3*/ + , + /* LCD_G5 */ + , + /* LCD_G6 */ + , + /* LCD_G7 */ + , + /* LCD_B4 */ + , + /* LCD_B5 */ + , + /* LCD_B6 */ + , + /* LCD_B7 */ + ; + /* LCD_DE */ + slew-rate = <2>; + }; + }; + + spi5_pins: spi5-0 { + pins1 { + pinmux = , + /* SPI5_CLK */ + ; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + /* SPI5_MISO */ + bias-disable; + }; + }; + + i2c3_pins: i2c3-0 { + pins { + pinmux = , + /* I2C3_SDA */ + ; + /* I2C3_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; + + dcmi_pins: dcmi-0 { + pins { + pinmux = , /* DCMI_HSYNC */ + , /* DCMI_VSYNC */ + , /* DCMI_PIXCLK */ + , /* DCMI_D0 */ + , /* DCMI_D1 */ + , /* DCMI_D2 */ + , /* DCMI_D3 */ + , /*DCMI_D4 */ + , /* DCMI_D5 */ + , /* DCMI_D6 */ + , /* DCMI_D7 */ + , /* DCMI_D8 */ + , /* DCMI_D9 */ + , /* DCMI_D10 */ + ; /* DCMI_D11 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + sdio_pins: sdio-pins-0 { + pins { + pinmux = , /* SDIO_D0 */ + , /* SDIO_D1 */ + , /* SDIO_D2 */ + , /* SDIO_D3 */ + , /* SDIO_CK */ + ; /* SDIO_CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od: sdio-pins-od-0 { + pins1 { + pinmux = , /* SDIO_D0 */ + , /* SDIO_D1 */ + , /* SDIO_D2 */ + , /* SDIO_D3 */ + ; /* SDIO_CK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDIO_CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts new file mode 100644 index 000000000000..3b81228d46a2 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -0,0 +1,232 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f429.dtsi" +#include "stm32f429-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "STMicroelectronics STM32F429i-DISCO board"; + compatible = "st,stm32f429i-disco", "st,stm32f429"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x800000>; + }; + + aliases { + serial0 = &usart1; + }; + + leds { + compatible = "gpio-leds"; + led-red { + gpios = <&gpiog 14 0>; + }; + led-green { + gpios = <&gpiog 13 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 0>; + }; + }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpioc 4 0>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; +}; + +&clk_hse { + clock-frequency = <8000000>; +}; + +&crc { + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; + + stmpe811@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioa>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + }; +}; + +<dc { + status = "okay"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-names = "default"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + +&rtc { + assigned-clocks = <&rcc 1 CLK_RTC>; + assigned-clock-parents = <&rcc 1 CLK_LSI>; + status = "okay"; +}; + +&spi5 { + status = "okay"; + pinctrl-0 = <&spi5_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>; + + l3gd20: l3gd20@0 { + compatible = "st,l3gd20-gyro"; + spi-max-frequency = <10000000>; + st,drdy-int-pin = <2>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>, + <2 IRQ_TYPE_EDGE_RISING>; + reg = <0>; + status = "okay"; + }; + + display: display@1{ + /* Connect panel-ilitek-9341 to ltdc */ + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; + reg = <1>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; +}; + +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + compatible = "st,stm32f4x9-fsotg"; + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi new file mode 100644 index 000000000000..e10d7a1f3207 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi @@ -0,0 +1,91 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "stm32f4-pinctrl.dtsi" + +&pinctrl { + compatible = "st,stm32f429-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi new file mode 100644 index 000000000000..8efcda9ef8ae --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -0,0 +1,799 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "../armv7-m.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_i2s_ckin: i2s-ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + + soc { + romem: efuse@1fff7800 { + compatible = "st,stm32f4-otp"; + reg = <0x1fff7800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ts_cal1: calib@22c { + reg = <0x22c 0x2>; + }; + ts_cal2: calib@22e { + reg = <0x22e 0x2>; + }; + }; + + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + + timers3: timers@40000400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timers@40001c00 { + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timers14: timers@40002000 { + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + rtc: rtc@40002800 { + compatible = "st,stm32-rtc"; + reg = <0x40002800 0x400>; + clocks = <&rcc 1 CLK_RTC>; + assigned-clocks = <&rcc 1 CLK_RTC>; + assigned-clock-parents = <&rcc 1 CLK_LSE>; + interrupt-parent = <&exti>; + interrupts = <17 1>; + st,syscfg = <&pwrcfg 0x00 0x100>; + status = "disabled"; + }; + + iwdg: watchdog@40003000 { + compatible = "st,stm32-iwdg"; + reg = <0x40003000 0x400>; + clocks = <&clk_lsi>; + clock-names = "lsi"; + status = "disabled"; + }; + + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; + status = "disabled"; + dmas = <&dma1 1 4 0x400 0x0>, + <&dma1 3 4 0x400 0x0>; + dma-names = "rx", "tx"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; + status = "disabled"; + }; + + i2c1: i2c@40005400 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F4_APB1_RESET(I2C1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@40005c00 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005c00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32F4_APB1_RESET(I2C3)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,can-secondary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + dac: dac@40007400 { + compatible = "st,stm32f4-dac-core"; + reg = <0x40007400 0x400>; + resets = <&rcc STM32F4_APB1_RESET(DAC)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + status = "disabled"; + }; + + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + status = "disabled"; + }; + }; + + usart7: serial@40007800 { + compatible = "st,stm32-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; + status = "disabled"; + }; + + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + + usart1: serial@40011000 { + compatible = "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; + status = "disabled"; + dmas = <&dma2 2 4 0x400 0x0>, + <&dma2 7 4 0x400 0x0>; + dma-names = "rx", "tx"; + }; + + usart6: serial@40011400 { + compatible = "st,stm32-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; + status = "disabled"; + }; + + adc: adc@40012000 { + compatible = "st,stm32f4-adc-core"; + reg = <0x40012000 0x400>; + interrupts = <18>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; + clock-names = "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32f4-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dma2 0 0 0x400 0x0>; + dma-names = "rx"; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32f4-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dma2 3 1 0x400 0x0>; + dma-names = "rx"; + status = "disabled"; + }; + + adc3: adc@200 { + compatible = "st,stm32f4-adc"; + #io-channel-cells = <1>; + reg = <0x200>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; + interrupt-parent = <&adc>; + interrupts = <2>; + dmas = <&dma2 1 2 0x400 0x0>; + dma-names = "rx"; + status = "disabled"; + }; + }; + + sdio: mmc@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; + clock-names = "apb_pclk"; + interrupts = <49>; + max-frequency = <48000000>; + status = "disabled"; + }; + + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; + status = "disabled"; + }; + + syscfg: syscon@40013800 { + compatible = "st,stm32-syscfg", "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + dmas = <&dma2 3 2 0x400 0x0>, + <&dma2 4 2 0x400 0x0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi6: spi@40015400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015400 0x400>; + interrupts = <86>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; + status = "disabled"; + }; + + pwrcfg: power-config@40007000 { + compatible = "st,stm32-power-config", "syscon"; + reg = <0x40007000 0x400>; + }; + + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F4_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + status = "disabled"; + }; + + crc: crc@40023000 { + compatible = "st,stm32f4-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; + status = "disabled"; + }; + + rcc: rcc@40023800 { + #reset-cells = <1>; + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; + assigned-clocks = <&rcc 1 CLK_HSE_RTC>; + assigned-clock-rates = <1000000>; + }; + + dma1: dma-controller@40026000 { + compatible = "st,stm32-dma"; + reg = <0x40026000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; + #dma-cells = <4>; + }; + + dma2: dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; + #dma-cells = <4>; + st,mem2mem; + }; + + mac: ethernet@40028000 { + compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + interrupts = <61>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, + <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, + <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <8>; + snps,mixed-burst; + status = "disabled"; + }; + + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + + usbotg_hs: usb@40040000 { + compatible = "snps,dwc2"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + status = "disabled"; + }; + + usbotg_fs: usb@50000000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 39>; + clock-names = "otg"; + status = "disabled"; + }; + + dcmi: dcmi@50050000 { + compatible = "st,stm32-dcmi"; + reg = <0x50050000 0x400>; + interrupts = <78>; + resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; + clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&dcmi_pins>; + dmas = <&dma2 1 1 0x414 0x3>; + dma-names = "tx"; + status = "disabled"; + }; + + rng: rng@50060800 { + compatible = "st,stm32-rng"; + reg = <0x50060800 0x400>; + clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; + + }; + }; +}; + +&systick { + clocks = <&rcc 1 SYSTICK>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts new file mode 100644 index 000000000000..cbbd521bf010 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -0,0 +1,254 @@ +/* + * Copyright 2016 - Lee Jones + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f469.dtsi" +#include "stm32f469-pinctrl.dtsi" +#include +#include + +/ { + model = "STMicroelectronics STM32F469i-DISCO board"; + compatible = "st,stm32f469i-disco", "st,stm32f469"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x1000000>; + }; + + aliases { + serial0 = &usart3; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_dsi: vdd-dsi { + compatible = "regulator-fixed"; + regulator-name = "vdd_dsi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + led-orange { + gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; + }; + led-red { + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + }; + led-blue { + gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; +}; + +&rcc { + compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; +}; + +&clk_hse { + clock-frequency = <8000000>; +}; + +&dma2d { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; + power-supply = <&vdd_dsi>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&timers1 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@0 { + status = "okay"; + }; +}; + +&timers3 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@2 { + status = "okay"; + }; +}; + +&sdio { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + broken-cd; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; +}; + +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + +&usart3 { + pinctrl-0 = <&usart3_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi new file mode 100644 index 000000000000..6bf60263dff8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "stm32f4-pinctrl.dtsi" + +&pinctrl { + compatible = "st,stm32f469-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 3 163 5>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32f469.dtsi b/arch/arm/boot/dts/st/stm32f469.dtsi new file mode 100644 index 000000000000..be002e8a78ac --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f469.dtsi @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ + +#include "stm32f429.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + resets = <&rcc STM32F4_APB2_RESET(DSI)>; + reset-names = "apb"; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi new file mode 100644 index 000000000000..9f65403295ca --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include +#include + +/ { + soc { + pinctrl: pinctrl@40020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; + st,bank-name = "GPIOK"; + }; + + cec_pins_a: cec-0 { + pins { + pinmux = ; /* HDMI CEC */ + slew-rate = <0>; + drive-open-drain; + bias-disable; + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1-0 { + pins { + pinmux = , /* I2C1 SDA */ + ; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs-1 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs-0 { + pins { + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_a: sdio-pins-a-0 { + pins { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + , /* SDMMC1 CLK */ + ; /* SDMMC1 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_a: sdio-pins-od-a-0 { + pins1 { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + ; /* SDMMC1 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC1 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + + sdio_pins_b: sdio-pins-b-0 { + pins { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + , /* SDMMC2 CLK */ + ; /* SDMMC2 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_b: sdio-pins-od-b-0 { + pins1 { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + ; /* SDMMC2 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC2 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_b: can1-1 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_c: can1-2 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can1_pins_d: can1-3 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can3_pins_a: can3-0 { + pins1 { + pinmux = ; /* CAN3_TX */ + }; + pins2 { + pinmux = ; /* CAN3_RX */ + bias-pull-up; + }; + }; + + can3_pins_b: can3-1 { + pins1 { + pinmux = ; /* CAN3_TX */ + }; + pins2 { + pinmux = ; /* CAN3_RX */ + bias-pull-up; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts new file mode 100644 index 000000000000..c11616ed5fc6 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -0,0 +1,144 @@ +/* + * Copyright 2017 - Vikas MANOCHA + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include "stm32f746-pinctrl.dtsi" +#include +#include + +/ { + model = "STMicroelectronics STM32F746-DISCO board"; + compatible = "st,stm32f746-disco", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x800000>; + }; + + aliases { + serial0 = &usart1; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + /* This turns on vbus for otg fs for host mode (dwc2) */ + vcc5v_otg_fs: vcc5v-otg-fs-regulator { + compatible = "regulator-fixed"; + gpio = <&gpiod 5 0>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&sdio1 { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; + bus-width = <4>; +}; + +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi new file mode 100644 index 000000000000..fcfd2ac7239b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f746-pinctrl"; +}; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi new file mode 100644 index 000000000000..d1802efd067c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -0,0 +1,592 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "../armv7-m.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_i2s_ckin: clk-i2s-ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + }; + + soc { + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + + timers3: timers@40000400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timers@40001c00 { + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timers14: timers@40002000 { + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + rtc: rtc@40002800 { + compatible = "st,stm32-rtc"; + reg = <0x40002800 0x400>; + clocks = <&rcc 1 CLK_RTC>; + assigned-clocks = <&rcc 1 CLK_RTC>; + assigned-clock-parents = <&rcc 1 CLK_LSE>; + interrupt-parent = <&exti>; + interrupts = <17 1>; + st,syscfg = <&pwrcfg 0x00 0x100>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32f7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 1 CLK_USART2>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32f7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 1 CLK_USART3>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 1 CLK_UART4>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32f7-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 1 CLK_UART5>; + status = "disabled"; + }; + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F7_APB1_RESET(I2C1)>; + clocks = <&rcc 1 CLK_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005800 0x400>; + interrupts = <33>, + <34>; + resets = <&rcc STM32F7_APB1_RESET(I2C2)>; + clocks = <&rcc 1 CLK_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@40005c00 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005c00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32F7_APB1_RESET(I2C3)>; + clocks = <&rcc 1 CLK_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@40006000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40006000 0x400>; + interrupts = <95>, + <96>; + resets = <&rcc STM32F7_APB1_RESET(I2C4)>; + clocks = <&rcc 1 CLK_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32f7-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 1 CLK_UART7>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 1 CLK_UART8>; + status = "disabled"; + }; + + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + + usart1: serial@40011000 { + compatible = "st,stm32f7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 1 CLK_USART1>; + status = "disabled"; + }; + + usart6: serial@40011400 { + compatible = "st,stm32f7-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 1 CLK_USART6>; + status = "disabled"; + }; + + sdio2: mmc@40011c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40011c00 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; + clock-names = "apb_pclk"; + interrupts = <103>; + max-frequency = <48000000>; + status = "disabled"; + }; + + sdio1: mmc@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; + clock-names = "apb_pclk"; + interrupts = <49>; + max-frequency = <48000000>; + status = "disabled"; + }; + + syscfg: syscon@40013800 { + compatible = "st,stm32-syscfg", "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + pwrcfg: power-config@40007000 { + compatible = "st,stm32-power-config", "syscon"; + reg = <0x40007000 0x400>; + }; + + crc: crc@40023000 { + compatible = "st,stm32f7-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; + status = "disabled"; + }; + + rcc: rcc@40023800 { + #reset-cells = <1>; + #clock-cells = <2>; + compatible = "st,stm32f746-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; + assigned-clocks = <&rcc 1 CLK_HSE_RTC>; + assigned-clock-rates = <1000000>; + }; + + dma1: dma-controller@40026000 { + compatible = "st,stm32-dma"; + reg = <0x40026000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; + #dma-cells = <4>; + status = "disabled"; + }; + + dma2: dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; + #dma-cells = <4>; + st,mem2mem; + status = "disabled"; + }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + usbotg_fs: usb@50000000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; + clock-names = "otg"; + status = "disabled"; + }; + }; +}; + +&systick { + clocks = <&rcc 1 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts new file mode 100644 index 000000000000..b038d0ed39e8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -0,0 +1,165 @@ +/* + * Copyright 2017 - Vikas MANOCHA + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include "stm32f769-pinctrl.dtsi" +#include +#include + +/ { + model = "STMicroelectronics STM32F769-DISCO board"; + compatible = "st,stm32f769-disco", "st,stm32f769"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x1000000>; + }; + + aliases { + serial0 = &usart1; + }; + + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + led-red { + gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&rcc { + compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; +}; + +&cec { + pinctrl-0 = <&cec_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdio2 { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + broken-cd; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_b>; + pinctrl-1 = <&sdio_pins_od_b>; + bus-width = <4>; +}; + +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi new file mode 100644 index 000000000000..31005dd9929c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f769-pinctrl"; +}; diff --git a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi new file mode 100644 index 000000000000..aa1bc3e10a49 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi @@ -0,0 +1,275 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +&pinctrl { + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet_rmii: rmii-0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + spi1_pins: spi1-0 { + pins1 { + pinmux = , + /* SPI1_CLK */ + ; + /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; + /* SPI1_MISO */ + bias-disable; + }; + }; + + uart4_pins: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + usart1_pins: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart3_pins: usart3-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi new file mode 100644 index 000000000000..b8d4c44c8a82 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -0,0 +1,730 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "../armv7-m.dtsi" +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_i2s: i2s_ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + + soc { + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc TIM5_CK>; + }; + + lptimer1: timer@40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + clocks = <&rcc LPTIM1_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; + clocks = <&rcc SPI2_CK>; + status = "disabled"; + + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; + clocks = <&rcc SPI3_CK>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32h7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + status = "disabled"; + clocks = <&rcc USART2_CK>; + }; + + usart3: serial@40004800 { + compatible = "st,stm32h7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + status = "disabled"; + clocks = <&rcc USART3_CK>; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + status = "disabled"; + clocks = <&rcc UART4_CK>; + }; + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; + clocks = <&rcc I2C1_CK>; + status = "disabled"; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005800 0x400>; + interrupts = <33>, + <34>; + resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; + clocks = <&rcc I2C2_CK>; + status = "disabled"; + }; + + i2c3: i2c@40005c00 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005C00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; + clocks = <&rcc I2C3_CK>; + status = "disabled"; + }; + + dac: dac@40007400 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40007400 0x400>; + clocks = <&rcc DAC12_CK>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + status = "disabled"; + }; + + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + status = "disabled"; + }; + }; + + usart1: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + status = "disabled"; + clocks = <&rcc USART1_CK>; + }; + + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + resets = <&rcc STM32H7_APB2_RESET(SPI1)>; + clocks = <&rcc SPI1_CK>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + resets = <&rcc STM32H7_APB2_RESET(SPI4)>; + clocks = <&rcc SPI4_CK>; + status = "disabled"; + }; + + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + resets = <&rcc STM32H7_APB2_RESET(SPI5)>; + clocks = <&rcc SPI5_CK>; + status = "disabled"; + }; + + dma1: dma-controller@40020000 { + compatible = "st,stm32-dma"; + reg = <0x40020000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc DMA1_CK>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + status = "disabled"; + }; + + dma2: dma-controller@40020400 { + compatible = "st,stm32-dma"; + reg = <0x40020400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc DMA2_CK>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + status = "disabled"; + }; + + dmamux1: dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x40>; + #dma-cells = <3>; + dma-channels = <16>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + clocks = <&rcc DMA1_CK>; + }; + + adc_12: adc@40022000 { + compatible = "st,stm32h7-adc-core"; + reg = <0x40022000 0x400>; + interrupts = <18>; + clocks = <&rcc ADC12_CK>; + clock-names = "bus"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc_12>; + interrupts = <0>; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupt-parent = <&adc_12>; + interrupts = <1>; + status = "disabled"; + }; + }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc USB1OTG_CK>; + clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + usbotg_fs: usb@40080000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x40080000 0x40000>; + interrupts = <101>; + clocks = <&rcc USB2OTG_CK>; + clock-names = "otg"; + status = "disabled"; + }; + + ltdc: display-controller@50001000 { + compatible = "st,stm32-ltdc"; + reg = <0x50001000 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32H7_APB3_RESET(LTDC)>; + clocks = <&rcc LTDC_CK>; + clock-names = "lcd"; + status = "disabled"; + }; + + mdma1: dma-controller@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&rcc MDMA_CK>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + }; + + sdmmc1: mmc@52007000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x52007000 0x1000>; + interrupts = <49>; + clocks = <&rcc SDMMC1_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + + sdmmc2: mmc@48022400 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48022400 0x400>; + interrupts = <124>; + clocks = <&rcc SDMMC2_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + exti: interrupt-controller@58000000 { + compatible = "st,stm32h7-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x58000000 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; + }; + + syscfg: syscon@58000400 { + compatible = "st,stm32-syscfg", "syscon"; + reg = <0x58000400 0x400>; + }; + + spi6: spi@58001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x58001400 0x400>; + interrupts = <86>; + resets = <&rcc STM32H7_APB4_RESET(SPI6)>; + clocks = <&rcc SPI6_CK>; + status = "disabled"; + }; + + i2c4: i2c@58001c00 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58001C00 0x400>; + interrupts = <95>, + <96>; + resets = <&rcc STM32H7_APB4_RESET(I2C4)>; + clocks = <&rcc I2C4_CK>; + status = "disabled"; + }; + + lptimer2: timer@58002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002400 0x400>; + clocks = <&rcc LPTIM2_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@58002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002800 0x400>; + clocks = <&rcc LPTIM3_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@58002c00 { + compatible = "st,stm32-lptimer"; + reg = <0x58002c00 0x400>; + clocks = <&rcc LPTIM4_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@58003000 { + compatible = "st,stm32-lptimer"; + reg = <0x58003000 0x400>; + clocks = <&rcc LPTIM5_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + vrefbuf: regulator@58003c00 { + compatible = "st,stm32-vrefbuf"; + reg = <0x58003C00 0x8>; + clocks = <&rcc VREF_CK>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + status = "disabled"; + }; + + rtc: rtc@58004000 { + compatible = "st,stm32h7-rtc"; + reg = <0x58004000 0x400>; + clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; + clock-names = "pclk", "rtc_ck"; + assigned-clocks = <&rcc RTC_CK>; + assigned-clock-parents = <&rcc LSE_CK>; + interrupt-parent = <&exti>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + st,syscfg = <&pwrcfg 0x00 0x100>; + status = "disabled"; + }; + + rcc: reset-clock-controller@58024400 { + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; + }; + + pwrcfg: power-config@58024800 { + compatible = "st,stm32-power-config", "syscon"; + reg = <0x58024800 0x400>; + }; + + adc_3: adc@58026000 { + compatible = "st,stm32h7-adc-core"; + reg = <0x58026000 0x400>; + interrupts = <127>; + clocks = <&rcc ADC3_CK>; + clock-names = "bus"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc3: adc@0 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc_3>; + interrupts = <0>; + status = "disabled"; + }; + }; + + mac: ethernet@40028000 { + compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + interrupts = <61>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <8>; + status = "disabled"; + }; + + pinctrl: pinctrl@58020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32h743-pinctrl"; + ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + + gpioa: gpio@58020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA_CK>; + st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@58020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc GPIOB_CK>; + st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@58020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc GPIOC_CK>; + st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@58020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc GPIOD_CK>; + st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@58021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOE_CK>; + st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@58021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc GPIOF_CK>; + st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@58021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc GPIOG_CK>; + st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@58021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc GPIOH_CK>; + st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@58022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOI_CK>; + st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@58022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc GPIOJ_CK>; + st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@58022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc GPIOK_CK>; + st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + }; + }; +}; + +&systick { + clock-frequency = <250000000>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts new file mode 100644 index 000000000000..2b452883a708 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -0,0 +1,111 @@ +/* + * Copyright 2017 - Patrice Chotard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32h743.dtsi" +#include "stm32h7-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32H743i-Discovery board"; + compatible = "st,stm32h743i-disco", "st,stm32h743"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@d0000000 { + device_type = "memory"; + reg = <0xd0000000 0x2000000>; + }; + + aliases { + serial0 = &usart2; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts new file mode 100644 index 000000000000..5c5d8059bdc7 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -0,0 +1,160 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32h743.dtsi" +#include "stm32h7-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32H743i-EVAL board"; + compatible = "st,stm32h743i-eval", "st,stm32h743"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@d0000000 { + device_type = "memory"; + reg = <0xd0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; + + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2v9_sd: regulator-v2v9_sd { + compatible = "regulator-fixed"; + regulator-name = "v2v9_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc USB1ULPI_CK>; + clock-names = "main_clk"; + }; +}; + +&adc_12 { + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + adc1: adc@0 { + /* potentiometer */ + st,adc-channels = <0>; + status = "okay"; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&v2v9_sd>; + status = "okay"; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32h750.dtsi b/arch/arm/boot/dts/st/stm32h750.dtsi new file mode 100644 index 000000000000..41e3b1e3a874 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h750.dtsi @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ + +#include "stm32h743.dtsi" + + diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts new file mode 100644 index 000000000000..44c307f8b09c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -0,0 +1,229 @@ +/* + * Copyright 2021 - Dillon Min + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * For art-pi board resources, you can refer to link: + * https://art-pi.gitee.io/website/ + */ + +/dts-v1/; +#include "stm32h750.dtsi" +#include "stm32h7-pinctrl.dtsi" +#include +#include + +/ { + model = "RT-Thread STM32H750i-ART-PI board"; + compatible = "st,stm32h750i-art-pi", "st,stm32h750"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:2000000n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x2000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + no-map; + size = <0x100000>; + linux,dma-default; + }; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; + + leds { + compatible = "gpio-leds"; + led-red { + gpios = <&gpioi 8 0>; + }; + led-green { + gpios = <&gpioc 15 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + + partition@0 { + label = "root filesystem"; + reg = <0 0x1000000>; + }; + }; +}; + +&usart2 { + pinctrl-0 = <&usart2_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins>; + dmas = <&dmamux1 45 0x400 0x05>, + <&dmamux1 46 0x400 0x05>; + dma-names = "rx", "tx"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + max-speed = <115200>; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + + diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi new file mode 100644 index 000000000000..27e0c3826789 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue + */ +#include + +&pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC1 in12 */ + }; + }; + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + + mcp23017_pins_a: mcp23017-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + pwm3_pins_a: pwm3-0 { + pins { + pinmux = ; /* TIM3_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = ; /* TIM3_CH4 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = ; /* TIM8_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = ; /* TIM8_CH3 */ + }; + }; + + pwm14_pins_a: pwm14-0 { + pins { + pinmux = ; /* TIM14_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm14_sleep_pins_a: pwm14-sleep-0 { + pins { + pinmux = ; /* TIM14_CH1 */ + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + spi5_pins_a: spi5-0 { + pins1 { + pinmux = , /* SPI5_SCK */ + ; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = , /* SPI5_SCK */ + , /* SPI5_MISO */ + ; /* SPI5_MOSI */ + }; + }; + + stm32g0_intn_pins_a: stm32g0-intn-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = ; /* UART8_TX */ + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + ; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi new file mode 100644 index 000000000000..d163c267e34c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -0,0 +1,1510 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + always-on; + }; + + /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ + reg11: reg11 { + compatible = "regulator-fixed"; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + compatible = "regulator-fixed"; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000b000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi2: spi@4000b000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000c000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x4000d000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x5>, + <&dmamux1 46 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x5>, + <&dmamux1 64 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x5>, + <&dmamux1 66 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c1: i2c@40012000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + i2c-analog-filter; + status = "disabled"; + }; + + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x5>, + <&dmamux1 80 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x5>, + <&dmamux1 82 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x5>, + <&dmamux1 72 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + reg = <0x44004000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@44004000 { + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + ranges = <0 0x4400a000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + ranges = <0 0x4400b000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + reg = <0>; + #io-channel-cells = <1>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + reg = <1>; + #io-channel-cells = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + clocks = <&rcc DMAMUX1>; + resets = <&rcc DMAMUX1_R>; + #dma-cells = <3>; + dma-masters = <&dma1 &dma2>; + dma-requests = <128>; + dma-channels = <16>; + }; + + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + mdma: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&rcc MDMA>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + + fmc: memory-controller@58002000 { + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + nand-controller@4,0 { + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, + <&mdma 24 0x2 0x12000a08 0x0 0x0>, + <&mdma 25 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_RTCAPB>, + <&scmi_clk CK_SCMI_RTC>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + + bsec: efuse@5c005000 { + compatible = "st,stm32mp13-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp: part_number_otp@4 { + reg = <0x4 0x2>; + bits = <0 12>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + }; + + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pinctrl@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp135-pinctrl"; + ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOB>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOC>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc GPIOD>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc GPIOE>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc GPIOF>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc GPIOG>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc GPIOH>; + st,bank-name = "GPIOH"; + ngpios = <15>; + gpio-ranges = <&pinctrl 0 112 15>; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc GPIOI>; + st,bank-name = "GPIOI"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 128 8>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi new file mode 100644 index 000000000000..df451c3c2a26 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp131.dtsi" + +/ { + soc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = ; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp135.dtsi b/arch/arm/boot/dts/st/stm32mp135.dtsi new file mode 100644 index 000000000000..abf2acd37b4e --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp135.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp133.dtsi" + +/ { + soc { + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts new file mode 100644 index 000000000000..f0900ca672b5 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user { + label = "User-PA13"; + linux,code = ; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + v3v3_sw: v3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_adc: vdd-adc { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_sd: vdd-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + vdd_usb: vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_usb_cc_pins_a>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <1000000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + mcp23017: pinctrl@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23017_pins_a>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,irq-mirror; + }; + + typec@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; + /* Alert pin on PI2 */ + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + /* Internal pull-up on PI2 */ + pinctrl-names = "default"; + pinctrl-0 = <&stm32g0_intn_pins_a>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + con_usb_c_g0_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <170>; + i2c-scl-falling-time-ns = <5>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers14 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm14_pins_a>; + pinctrl-1 = <&pwm14_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@13 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3_sw>; + }; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usb_c_g0_ep>; + }; + }; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; diff --git a/arch/arm/boot/dts/st/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi new file mode 100644 index 000000000000..4d00e7592882 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi new file mode 100644 index 000000000000..4d00e7592882 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi new file mode 100644 index 000000000000..06e969aa5fdb --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -0,0 +1,2697 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +#include + +&pinctrl { + adc1_in6_pins_a: adc1-in6-0 { + pins { + pinmux = ; + }; + }; + + adc12_ain_pins_a: adc12-ain-0 { + pins { + pinmux = , /* ADC1 in13 */ + , /* ADC1 in6 */ + , /* ADC2 in2 */ + ; /* ADC2 in6 */ + }; + }; + + adc12_ain_pins_b: adc12-ain-1 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC2 in2 */ + }; + }; + + adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { + pins { + pinmux = , /* ADC12 in18 */ + ; /* ADC12 in19 */ + }; + }; + + cec_pins_a: cec-0 { + pins { + pinmux = ; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + cec_sleep_pins_a: cec-sleep-0 { + pins { + pinmux = ; /* HDMI_CEC */ + }; + }; + + cec_pins_b: cec-1 { + pins { + pinmux = ; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + cec_sleep_pins_b: cec-sleep-1 { + pins { + pinmux = ; /* HDMI_CEC */ + }; + }; + + dac_ch1_pins_a: dac-ch1-0 { + pins { + pinmux = ; + }; + }; + + dac_ch2_pins_a: dac-ch2-0 { + pins { + pinmux = ; + }; + }; + + dcmi_pins_a: dcmi-0 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ,/* DCMI_D9 */ + ,/* DCMI_D10 */ + ;/* DCMI_D11 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_a: dcmi-sleep-0 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ,/* DCMI_D9 */ + ,/* DCMI_D10 */ + ;/* DCMI_D11 */ + }; + }; + + dcmi_pins_b: dcmi-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_b: dcmi-sleep-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + }; + }; + + dcmi_pins_c: dcmi-2 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + }; + }; + + ethernet0_rgmii_pins_a: rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rgmii_pins_c: rgmii-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rgmii_pins_d: rgmii-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rmii_pins_a: rmii-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_CLK */ + , /* ETH1_MDC */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH1_CRS_DV */ + , /* ETH1_RXD0 */ + ; /* ETH1_RXD1 */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH1_TX_EN */ + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_MDIO */ + , /* ETH1_CRS_DV */ + , /* ETH1_CLK */ + , /* ETH1_TX_EN */ + , /* ETH1_MDC */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + }; + }; + + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + + fmc_pins_a: fmc-0 { + pins1 { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_A16_FMC_CLE */ + , /* FMC_A17_FMC_ALE */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + ; /* FMC_NE2_FMC_NCE */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* FMC_NWAIT */ + bias-pull-up; + }; + }; + + fmc_sleep_pins_a: fmc-sleep-0 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_A16_FMC_CLE */ + , /* FMC_A17_FMC_ALE */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_NWAIT */ + ; /* FMC_NE2_FMC_NCE */ + }; + }; + + fmc_pins_b: fmc-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + fmc_sleep_pins_b: fmc-sleep-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + }; + }; + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2c1_pins_b: i2c1-1 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_b: i2c1-sleep-1 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2c2_pins_a: i2c2-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_a: i2c2-sleep-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + i2c2_pins_b1: i2c2-1 { + pins { + pinmux = ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_b1: i2c2-sleep-1 { + pins { + pinmux = ; /* I2C2_SDA */ + }; + }; + + i2c2_pins_c: i2c2-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_c: i2c2-sleep-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + + }; + }; + + i2c5_pins_b: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + + i2s2_pins_a: i2s2-0 { + pins { + pinmux = , /* I2S2_SDO */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + i2s2_sleep_pins_a: i2s2-sleep-0 { + pins { + pinmux = , /* I2S2_SDO */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + }; + }; + + ltdc_pins_a: ltdc-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + ltdc_pins_b: ltdc-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_b: ltdc-sleep-1 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + ltdc_pins_c: ltdc-2 { + pins1 { + pinmux = , /* LTDC_R6 */ + , /* LTDC_B7 */ + , /* LTDC_R5 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_G3 */ + , /* LTDC_B4 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_G5 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G4 */ + , /* LTDC_G6 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_VSYNC */ + ; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_c: ltdc-sleep-2 { + pins1 { + pinmux = , /* LTDC_R6 */ + , /* LTDC_B7 */ + , /* LTDC_R5 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_G3 */ + , /* LTDC_B4 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_G5 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G4 */ + , /* LTDC_G6 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_VSYNC */ + , /* LTDC_HSYNC */ + ; /* LTDC_CLK */ + }; + }; + + ltdc_pins_d: ltdc-3 { + pins1 { + pinmux = ; /* LCD_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ltdc_sleep_pins_d: ltdc-sleep-3 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + mco1_pins_a: mco1-0 { + pins { + pinmux = ; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = ; /* MCO1 */ + }; + }; + + mco2_pins_a: mco2-0 { + pins { + pinmux = ; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = ; /* MCO2 */ + }; + }; + + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_a: m_can1-sleep-0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m_can1_pins_b: m-can1-1 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_b: m_can1-sleep-1 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m_can1_pins_c: m-can1-2 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_c: m_can1-sleep-2 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = , /* CAN2_TX */ + ; /* CAN2_RX */ + }; + }; + + pwm1_pins_a: pwm1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH4 */ + }; + }; + + pwm1_pins_b: pwm1-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_b: pwm1-sleep-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + }; + }; + + pwm2_pins_a: pwm2-0 { + pins { + pinmux = ; /* TIM2_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm2_sleep_pins_a: pwm2-sleep-0 { + pins { + pinmux = ; /* TIM2_CH4 */ + }; + }; + + pwm3_pins_a: pwm3-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + + pwm3_pins_b: pwm3-1 { + pins { + pinmux = ; /* TIM3_CH2 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_b: pwm3-sleep-1 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = , /* TIM4_CH3 */ + ; /* TIM4_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = , /* TIM4_CH3 */ + ; /* TIM4_CH4 */ + }; + }; + + pwm4_pins_b: pwm4-1 { + pins { + pinmux = ; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_b: pwm4-sleep-1 { + pins { + pinmux = ; /* TIM4_CH2 */ + }; + }; + + pwm5_pins_a: pwm5-0 { + pins { + pinmux = ; /* TIM5_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = ; /* TIM5_CH2 */ + }; + }; + + pwm5_pins_b: pwm5-1 { + pins { + pinmux = , /* TIM5_CH2 */ + , /* TIM5_CH3 */ + ; /* TIM5_CH4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_b: pwm5-sleep-1 { + pins { + pinmux = , /* TIM5_CH2 */ + , /* TIM5_CH3 */ + ; /* TIM5_CH4 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = ; /* TIM8_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = ; /* TIM8_CH4 */ + }; + }; + + pwm12_pins_a: pwm12-0 { + pins { + pinmux = ; /* TIM12_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm12_sleep_pins_a: pwm12-sleep-0 { + pins { + pinmux = ; /* TIM12_CH1 */ + }; + }; + + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = ; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = ; /* QSPI_CLK */ + }; + }; + + qspi_bk1_pins_a: qspi-bk1-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + }; + }; + + qspi_bk2_pins_a: qspi-bk2-0 { + pins { + pinmux = , /* QSPI_BK2_IO0 */ + , /* QSPI_BK2_IO1 */ + , /* QSPI_BK2_IO2 */ + ; /* QSPI_BK2_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = , /* QSPI_BK2_IO0 */ + , /* QSPI_BK2_IO1 */ + , /* QSPI_BK2_IO2 */ + ; /* QSPI_BK2_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + }; + }; + + qspi_cs2_pins_a: qspi-cs2-0 { + pins { + pinmux = ; /* QSPI_BK2_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { + pins { + pinmux = ; /* QSPI_BK2_NCS */ + }; + }; + + sai2a_pins_a: sai2a-0 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + , /* SAI2_FS_A */ + ; /* SAI2_MCLK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_a: sai2a-sleep-0 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + , /* SAI2_FS_A */ + ; /* SAI2_MCLK_A */ + }; + }; + + sai2a_pins_b: sai2a-1 { + pins1 { + pinmux = , /* SAI2_SD_A */ + , /* SAI2_FS_A */ + ; /* SAI2_SCK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_b: sai2a-sleep-1 { + pins { + pinmux = , /* SAI2_SD_A */ + , /* SAI2_FS_A */ + ; /* SAI2_SCK_A */ + }; + }; + + sai2a_pins_c: sai2a-2 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_c: sai2a-sleep-2 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + }; + }; + + sai2b_pins_a: sai2b-0 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + ; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_a: sai2b-sleep-0 { + pins { + pinmux = , /* SAI2_SD_B */ + , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + ; /* SAI2_MCLK_B */ + }; + }; + + sai2b_pins_b: sai2b-1 { + pins { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_b: sai2b-sleep-1 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + + sai2b_pins_c: sai2b-2 { + pins1 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_c: sai2b-sleep-2 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + + sai2b_pins_d: sai2b-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + ; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_d: sai2b-sleep-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + , /* SAI2_MCLK_B */ + ; /* SAI2_SD_B */ + }; + }; + + sai4a_pins_a: sai4a-0 { + pins { + pinmux = ; /* SAI4_SD_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai4a_sleep_pins_a: sai4a-sleep-0 { + pins { + pinmux = ; /* SAI4_SD_A */ + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_b4_pins_b: sdmmc2-b4-1 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_e: sdmmc2-d47-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + + spdifrx_pins_a: spdifrx-0 { + pins { + pinmux = ; /* SPDIF_IN1 */ + bias-disable; + }; + }; + + spdifrx_sleep_pins_a: spdifrx-sleep-0 { + pins { + pinmux = ; /* SPDIF_IN1 */ + }; + }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + + spi2_pins_a: spi2-0 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_pins_b: spi2-1 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; + + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_pins_c: uart4-2 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_pins_d: uart4-3 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_d: uart4-idle-3 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_d: uart4-sleep-3 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart5_pins_a: uart5-0 { + pins1 { + pinmux = ; /* UART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART5_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART7_RX */ + , /* UART7_CTS */ + ; /* UART7_RTS */ + bias-disable; + }; + }; + + uart7_pins_b: uart7-1 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_pins_c: uart7-2 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_idle_pins_c: uart7-idle-2 { + pins1 { + pinmux = ; /* UART7_TX */ + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_sleep_pins_c: uart7-sleep-2 { + pins { + pinmux = , /* UART7_TX */ + ; /* UART7_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-disable; + }; + }; + + uart8_rtscts_pins_a: uart8rtscts-0 { + pins { + pinmux = , /* UART8_RTS */ + ; /* UART8_CTS */ + bias-disable; + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_CTS_NSS */ + bias-disable; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_c: usart2-2 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_c: usart2-idle-2 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_c: usart2-sleep-2 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = ; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_idle_pins_a: usart3-idle-0 { + pins1 { + pinmux = ; /* USART3_TX */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_a: usart3-sleep-0 { + pins { + pinmux = , /* USART3_TX */ + ; /* USART3_RX */ + }; + }; + + usart3_pins_b: usart3-1 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-pull-up; + }; + }; + + usart3_idle_pins_b: usart3-idle-1 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART3_RX */ + bias-pull-up; + }; + }; + + usart3_sleep_pins_b: usart3-sleep-1 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + + usart3_pins_c: usart3-2 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-pull-up; + }; + }; + + usart3_idle_pins_c: usart3-idle-2 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART3_RX */ + bias-pull-up; + }; + }; + + usart3_sleep_pins_c: usart3-sleep-2 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + + usart3_pins_d: usart3-3 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_d: usart3-idle-3 { + pins1 { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_d: usart3-sleep-3 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + + usart3_pins_e: usart3-4 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-pull-up; + }; + }; + + usart3_idle_pins_e: usart3-idle-4 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART3_RX */ + bias-pull-up; + }; + }; + + usart3_sleep_pins_e: usart3-sleep-4 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = ; /* OTG_ID */ + }; + }; + + usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { + pins { + pinmux = , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + }; + }; +}; + +&pinctrl_z { + i2c2_pins_b2: i2c2-0 { + pins { + pinmux = ; /* I2C2_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_b2: i2c2-sleep-0 { + pins { + pinmux = ; /* I2C2_SCL */ + }; + }; + + i2c4_pins_a: i2c4-0 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_sleep_pins_a: i2c4-sleep-0 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + }; + }; + + i2c6_pins_a: i2c6-0 { + pins { + pinmux = , /* I2C6_SCL */ + ; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c6_sleep_pins_a: i2c6-sleep-0 { + pins { + pinmux = , /* I2C6_SCL */ + ; /* I2C6_SDA */ + }; + }; + + spi1_pins_a: spi1-0 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + + spi1_sleep_pins_a: spi1-sleep-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MISO */ + ; /* SPI1_MOSI */ + }; + }; + + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = ; /* USART1_TX */ + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi new file mode 100644 index 000000000000..543f24c2f4f6 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: reg11@0 { + reg = <0>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + scmi_reg18: reg18@1 { + voltd-name = "reg18"; + reg = <1>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + scmi_usb33: usb33@2 { + reg = <2>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + }; + + soc { + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + }; +}; + +®11 { + status = "disabled"; +}; + +®18 { + status = "disabled"; +}; + +&usb33 { + status = "disabled"; +}; + +&usbotg_hs { + usb33d-supply = <&scmi_usb33>; +}; + +&usbphyc { + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; +}; + +/delete-node/ &clk_hse; +/delete-node/ &clk_hsi; +/delete-node/ &clk_lse; +/delete-node/ &clk_lsi; +/delete-node/ &clk_csi; diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi new file mode 100644 index 000000000000..61508917521c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -0,0 +1,1846 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + clock-frequency = <650000000>; + device_type = "cpu"; + reg = <0>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + }; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + booster: regulator-booster { + compatible = "st,stm32mp1-booster"; + st,syscfg = <&syscfg>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timer@40006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40006000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@40007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@40008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + interrupts = ; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000c000 0x400>; + interrupts = ; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + + usart2: serial@4000e000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000e000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART4_K>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c1: i2c@40012000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c3: i2c@40014000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40014000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@40015000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40015000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + cec: cec@40016000 { + compatible = "st,stm32-cec"; + reg = <0x40016000 0x400>; + interrupts = ; + clocks = <&rcc CEC_K>, <&rcc CEC>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + status = "disabled"; + }; + + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + status = "disabled"; + }; + }; + + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@44004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x44004000 0x400>; + interrupts = ; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@44005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44005000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@44007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44009000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400a000 0x400>; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = ; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = ; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + sai3: sai@4400c000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400c000 0x400>; + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = ; + resets = <&rcc SAI3_R>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; + status = "disabled"; + }; + + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <0>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <2>; + interrupts = ; + dmas = <&dmamux1 103 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <3>; + interrupts = ; + dmas = <&dmamux1 104 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm4: filter@4 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <4>; + interrupts = ; + dmas = <&dmamux1 91 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm5: filter@5 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <5>; + interrupts = ; + dmas = <&dmamux1 92 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; + }; + + adc: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = , + ; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + interrupt-controller; + st,syscfg = <&syscfg>; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dmamux1 10 0x400 0x01>; + dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + }; + }; + + sdmmc3: mmc@48004000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + clocks = <&rcc IPCC>; + wakeup-source; + status = "disabled"; + }; + + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = ; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x01>; + dma-names = "tx"; + status = "disabled"; + }; + + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + pwr_mcu: pwr_mcu@50001014 { + compatible = "st,stm32mp151-pwr-mcu", "syscon"; + reg = <0x50001014 0x4>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + status = "disabled"; + }; + + sai4: sai@50027000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50027000 0x400>; + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = ; + resets = <&rcc SAI4_R>; + status = "disabled"; + + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; + status = "disabled"; + }; + + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; + status = "disabled"; + }; + }; + + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = ; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + status = "disabled"; + }; + + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + + mdma1: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x58005000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x58007000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4>; + snps,mixed-burst; + snps,pbl = <2>; + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; + + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + }; + + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + + usart1: serial@5c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x5c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + wakeup-source; + status = "disabled"; + }; + + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = ; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + clocks = <&rcc RTCAPB>, <&rcc RTC>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + bsec: efuse@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + part_number_otp: part-number-otp@4 { + reg = <0x4 0x1>; + }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + }; + + i2c6: i2c@5c009000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + }; + + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pinctrl@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp157-pinctrl"; + ranges = <0 0x50002000 0xa400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOB>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOC>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc GPIOD>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc GPIOE>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc GPIOF>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc GPIOG>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc GPIOH>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc GPIOI>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@5000b000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x400>; + clocks = <&rcc GPIOJ>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@5000c000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa000 0x400>; + clocks = <&rcc GPIOK>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@54004000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp157-z-pinctrl"; + ranges = <0 0x54004000 0x400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; + + gpioz: gpio@54004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&rcc GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + }; + }; + + mlahb: ahb { + compatible = "st,mlahb", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@10000000 { + compatible = "st,stm32mp1-m4"; + reg = <0x10000000 0x40000>, + <0x30000000 0x40000>, + <0x38000000 0x10000>; + resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; + st,syscfg-holdboot = <&rcc 0x10C 0x1>; + st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts new file mode 100644 index 000000000000..e0f828ecc2fa --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-testbench.dtsi" + +/ { + model = "DH electronics STM32MP151A DHCOR Testbench"; + compatible = "dh,stm32mp151a-dhcor-testbench", + "dh,stm32mp151a-dhcor-som", + "st,stm32mp151"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts new file mode 100644 index 000000000000..75874eafde11 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1A"; + compatible = "prt,prtt1a", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; + +&pwm5_pins_a { + pins { + pinmux = ; /* TIM5_CH1 */ + }; +}; + +&pwm5_sleep_pins_a { + pins { + pinmux = ; /* TIM5_CH1 */ + }; +}; + +&timers5 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts new file mode 100644 index 000000000000..7ecf31263abc --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1C"; + compatible = "prt,prtt1c", "st,stm32mp151"; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + }; +}; + +ðernet0 { + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", + "", "", "", "", "", "", "", "SPI1_nSS"; +}; + +&gpiod { + gpio-line-names = + "", "", "", "", "", "", "", "", + "WFM_RESET", "", "", "", "", "", "", ""; +}; + +&gpioe { + gpio-line-names = + "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", + "", "", "", "", "WFM_nIRQ", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "PHY3_nINT", + "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", + "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; +}; + +&mdio0 { + /* All this DP83TD510E PHYs can't be probed before switch@0 is + * probed so we need to use compatible with PHYid + */ + /* TI DP83TD510E */ + t1l0_phy: ethernet-phy@6 { + compatible = "ethernet-phy-id2000.0181"; + reg = <6>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.0181"; + reg = <7>; + interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l2_phy: ethernet-phy@10 { + compatible = "ethernet-phy-id2000.0181"; + reg = <10>; + interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* Micrel KSZ9031 */ + rj45_phy: ethernet-phy@2 { + reg = <2>; + interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc2_b4_od_pins_a { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + }; +}; + +&sdmmc2_b4_pins_a { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_b4_sleep_pins_a { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_d47_pins_a { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2_d47_sleep_pins_a { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + non-removable; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmc@1 { + compatible = "prt,prtt1c-wfm200", "silabs,wf200"; + reg = <1>; + }; +}; + +&sdmmc3_b4_od_pins_b { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + }; +}; + +&sdmmc3_b4_pins_b { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + }; +}; + +&sdmmc3_b4_sleep_pins_b { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins_b>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "t1l0"; + phy-mode = "rmii"; + phy-handle = <&t1l0_phy>; + }; + + port@1 { + reg = <1>; + label = "t1l1"; + phy-mode = "rmii"; + phy-handle = <&t1l1_phy>; + }; + + port@2 { + reg = <2>; + label = "t1l2"; + phy-mode = "rmii"; + phy-handle = <&t1l2_phy>; + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rj45_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <ðernet0>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi new file mode 100644 index 000000000000..dd23de85100c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxad-pinctrl.dtsi" +#include +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + mdio-gpio0 = &mdio0; + serial0 = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + status = "okay"; +}; + +ðernet0_rmii_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + ; /* ETH1_RMII_TX_EN */ + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK input */ + ; /* ETH1_RMII_CRS_DV */ + }; +}; + +ðernet0_rmii_sleep_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; +}; + +&iwdg2 { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&qspi_bk1_pins_a { + pins1 { + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_od_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc1_b4_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart4_idle_pins_a { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_pins_a { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_sleep_pins_a { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <®_3v3>; +}; + +&usbphyc_port1 { + phy-supply = <®_3v3>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts new file mode 100644 index 000000000000..ad25929e64e6 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1S"; + compatible = "prt,prtt1s", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + humidity-sensor@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + }; +}; + +&i2c1_pins_a { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; +}; + +&i2c1_sleep_pins_a { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi new file mode 100644 index 000000000000..486084e0b80b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp151.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + clock-frequency = <650000000>; + device_type = "cpu"; + reg = <1>; + }; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + timer { + interrupts = , + , + , + ; + }; + + soc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts new file mode 100644 index 000000000000..b4e504f026ce --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2 + * DHCOM PCB number: 587-200 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-drc02.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOM DRC02"; + compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som", + "st,stm32mp153"; +}; + +&cryp1 { + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts new file mode 100644 index 000000000000..c8b9818499ea --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG + * DHCOR PCB number: 586-100 or newer + * DRC Compact PCB number: 627-100 or newer + */ + +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-drc-compact.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOR DRC Compact"; + compatible = "dh,stm32mp153c-dhcor-drc-compact", + "dh,stm32mp153c-dhcor-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_c>; + pinctrl-1 = <&m_can1_sleep_pins_c>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157.dtsi b/arch/arm/boot/dts/st/stm32mp157.dtsi new file mode 100644 index 000000000000..5e733cd16ff9 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp153.dtsi" + +/ { + soc { + gpu: gpu@59000000 { + compatible = "vivante,gc"; + reg = <0x59000000 0x800>; + interrupts = ; + clocks = <&rcc GPU>, <&rcc GPU_K>; + clock-names = "bus" ,"core"; + resets = <&rcc GPU_R>; + }; + + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/st/stm32mp157a-avenger96.dts new file mode 100644 index 000000000000..8a6eaca994d1 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-avenger96.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/dts-v1/; + +/* This DT is here only for backward compatibility */ +#include "stm32mp157a-dhcor-avenger96.dts" diff --git a/arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts new file mode 100644 index 000000000000..275167f26fd9 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG + * DHCOR PCB number: 586-100 or newer + * Avenger96 PCB number: 588-200 or newer + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "disabled"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts new file mode 100644 index 000000000000..afcd6285890c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts new file mode 100644 index 000000000000..0da3667ab1e0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; + compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts new file mode 100644 index 000000000000..4279b26547df --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,icore-stm32mp1-ctouch2-of10", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts new file mode 100644 index 000000000000..60ce4425a7fd --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0"; + compatible = "engicam,icore-stm32mp1-ctouch2", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts new file mode 100644 index 000000000000..efba54289820 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit"; + compatible = "engicam,icore-stm32mp1-edimm2.2", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in_ltdc: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in_ltdc>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi new file mode 100644 index 000000000000..9de893101b40 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + compatible = "engicam,icore-stm32mp1", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + vddcore: regulator-vddcore { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_usb: regulator-vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ddr: regulator-vdd-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vtt_ddr: regulator-vtt-ddr { + compatible = "regulator-fixed"; + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + regulator-always-on; + vin-supply = <&vdd>; + }; + + vref_ddr: regulator-vref-ddr { + compatible = "regulator-fixed"; + regulator-name = "vref_ddr"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + regulator-always-on; + vin-supply = <&vdd>; + }; + + vdd_sd: regulator-vdd-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2v8: regulator-v2v8 { + compatible = "regulator-fixed"; + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + v1v8: regulator-v1v8 { + compatible = "regulator-fixed"; + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; +}; + +&dts { + status = "okay"; +}; + +&i2c2 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2{ + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts new file mode 100644 index 000000000000..6a5a4af25bd9 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A IoT Box"; + compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c2 { + ccs811@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; +}; + +/* WiFi */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <1>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ +&uart4 { + /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ + /delete-property/st,hw-flow-ctrl; + cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts new file mode 100644 index 000000000000..5116a7785201 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-microgea-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame"; + compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", + "engicam,microgea-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + power-supply = <&panel_pwr>; + }; + + panel_pwr: regulator-panel-pwr { + compatible = "regulator-fixed"; + regulator-name = "panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + panel { + compatible = "auo,b101aw03"; + backlight = <&backlight>; + enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; + power-supply = <&lcd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; +}; + +&i2c2 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; +}; + +<dc { + pinctrl-names = "default"; + pinctrl-0 = <<dc_pins>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pinctrl { + ltdc_pins: ltdc-0 { + pins { + pinmux = , /* LTDC_B2 */ + , /* LTDC_R6 */ + , /* LTDC_R5 */ + , /* LTDC_B3 */ + , /* LTDC_B0 */ + , /* LTDC_G0 */ + , /* LTDC_G1 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_CLK */ + , /* LTDC_B1 */ + , /* LTDC_R0 */ + , /* LTDC_R1 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G3 */ + , /* LTDC_G4 */ + , /* LTDC_G5 */ + , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B4 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_VSYNC */ + ; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&vdd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* J31: RS323 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts new file mode 100644 index 000000000000..d949559be020 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-microgea-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board"; + compatible = "engicam,microgea-stm32mp1-microdev2.0", + "engicam,microgea-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&vdd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* J31: RS323 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi new file mode 100644 index 000000000000..fb4600a59869 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + compatible = "engicam,microgea-stm32mp1", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddcore: regulator-vddcore { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <&vin>; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vin>; + }; + + vddq_ddr: regulator-vddq-ddr { + compatible = "regulator-fixed"; + regulator-name = "vddq_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vin>; + }; +}; + +&dts { + status = "okay"; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "okay"; + + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2{ + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dts new file mode 100644 index 000000000000..249a53877512 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A Stinger96 board"; + compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi new file mode 100644 index 000000000000..5f85598cc7c6 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &spi4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + led { + compatible = "gpio-leds"; + + led1 { + label = "green:user1"; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +/* Only headless mode is supported */ +&gpu { + status = "disabled"; +}; + +/* LS-I2C0 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <1000>; + i2c-scl-falling-time-ns = <300>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v2v9: ldo2 { + regulator-name = "v2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + broken-cd; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +/* LS-SPI0 */ +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* BG96 */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* LS-UART0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_c>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Debug console */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts new file mode 100644 index 000000000000..6dd8216c235e --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 + * DHCOM PCB number: 587-200 or newer + * PDK2 PCB number: 516-400 or newer + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-pdk2.dtsi" + +/ { + model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; +}; + +&cryp1 { + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts b/arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts new file mode 100644 index 000000000000..7067a860aaff --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E-CAN2-SD-RTC-T-DSI-I-01D2 + * DHCOM PCB number: 587-200 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-picoitx.dtsi" + +/ { + model = "DH electronics STM32MP157C DHCOM PicoITX"; + compatible = "dh,stm32mp157c-dhcom-picoitx", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; +}; + +&cryp1 { + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts new file mode 100644 index 000000000000..39358d902000 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts new file mode 100644 index 000000000000..4bef2300ed7c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; + compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&i2c1 { + touchscreen@38 { + compatible = "focaltech,ft6236"; + reg = <0x38>; + interrupts = <2 2>; + interrupt-parent = <&gpiof>; + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + status = "okay"; + }; +}; + +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts new file mode 100644 index 000000000000..07ea765a4553 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts new file mode 100644 index 000000000000..66ed5f9921ba --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include +#include + +/ { + model = "STMicroelectronics STM32MP157C eval daughter"; + compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&adc { + /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ + pinctrl-0 = <&adc1_in6_pins_a>; + pinctrl-names = "default"; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "disabled"; + adc1: adc@0 { + status = "okay"; + channel@0 { + reg = <0>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-ns = <400>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <400>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <400>; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "disabled"; + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +&hash1 { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&timers6 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + timer@5 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts new file mode 100644 index 000000000000..33b3f11d24bb --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller . +// + +/dts-v1/; + +#include "stm32mp157c-emstamp-argon.dtsi" + +/ { + model = "emtrion STM32MP157C emSBC-Argon Developer Board"; + compatible = "emtrion,stm32mp157c-emsbc-argon", "emtrion,stm32mp157c-emstamp-argon", + "st,stm32mp157"; + + led: gpio_leds { + compatible = "gpio-leds"; + led-2 { + label = "red"; + gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + led-3 { + label = "green"; + gpios = <&gpioe 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; +}; + +&dac { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi new file mode 100644 index 000000000000..94e38141af67 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller . +// + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &usart2; + serial2 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x2000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10044000 { + compatible = "shared-dma-pool"; + reg = <0x10044000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + led: gpio_leds { + compatible = "gpio-leds"; + led-0 { + label = "panic"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + led-1 { + label = "heartbeat"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in6_pins_a>; + status = "disabled"; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + }; + + adc2: adc@100 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + channel@12 { + reg = <12>; + label = "sense_temp"; + st,min-sample-time-ns = <9000>; + }; + channel@15 { + reg = <15>; + label = "vbat"; + st,min-sample-time-ns = <9000>; + }; + channel@16 { + reg = <16>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + channel@17 { + reg = <17>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "disabled"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + status = "okay"; + snps,reset-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 30000 50000>; + pinctrl-0 = <ðernet0_rmii_pins_b>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + regulator-always-on; + }; + + vdda: ldo6 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + regulator-boot-on; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_usbh: pwr_sw2 { + regulator-name = "usbh_vbus"; + interrupts = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + interrupt-names = "wdg"; + recovery; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "disabled"; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm1_pins_b>; + pinctrl-1 = <&pwm1_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@0 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm4_pins_b>; + pinctrl-1 = <&pwm4_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_d>; + pinctrl-1 = <&usart3_sleep_pins_d>; + pinctrl-2 = <&usart3_idle_pins_d>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_hs_pins_a>; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts new file mode 100644 index 000000000000..813086ec2489 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts new file mode 100644 index 000000000000..af3800501875 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157c-ed1.dts" +#include +#include +#include + +/ { + model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; + + aliases { + serial1 = &usart3; + ethernet0 = ðernet0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + joystick { + compatible = "gpio-keys"; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + button-1 { + label = "JoyDown"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + button-3 { + label = "JoyRight"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + button-4 { + label = "JoyUp"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + }; + }; + + panel_backlight: panel-backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + default-on; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +&dcmi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_a>; + pinctrl-1 = <&dcmi_sleep_pins_a>; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov5640_0>; + bus-type = ; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; +}; + +&dsi { + phy-dsi-supply = <®18>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel@0 { + compatible = "raydium,rm68200"; + reg = <0>; + reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; + backlight = <&panel_backlight>; + power-supply = <&v3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "okay"; + + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + clock-names = "xclk"; + AVDD-supply = <&v2v8>; + DOVDD-supply = <&v2v8>; + DVDD-supply = <&v2v8>; + powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; + reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + rotation = <180>; + status = "okay"; + + port { + ov5640_0: endpoint { + remote-endpoint = <&dcmi_0>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; + + stmfx: stmfx@42 { + compatible = "st,stmfx-0300"; + reg = <0x42>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpioi>; + vdd-supply = <&v3v3>; + + stmfx_pinctrl: pinctrl { + compatible = "st,stmfx-0300-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&stmfx_pinctrl 0 0 24>; + + joystick_pins: joystick-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + bias-pull-down; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a + &qspi_bk2_pins_a + &qspi_cs2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a + &qspi_bk2_sleep_pins_a + &qspi_cs2_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + flash1: flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "disabled"; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-1 = <&pwm2_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers12 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm12_pins_a>; + pinctrl-1 = <&pwm12_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@11 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_b>; + pinctrl-1 = <&usart3_sleep_pins_b>; + pinctrl-2 = <&usart3_idle_pins_b>; + /* + * HW flow control USART3_RTS is optional, and isn't default wired to + * the connector. SB23 needs to be soldered in order to use it, and R77 + * (ETH_CLK) should be removed. + */ + uart-has-rtscts; + status = "disabled"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; + + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts new file mode 100644 index 000000000000..eada9cf257be --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include +#include + +/ { + model = "Linux Automation MC-1 board"; + compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ + }; + + chosen { + stdout-path = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + label = "mc1:green:act"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-controller-1 { + compatible = "pwm-leds"; + + /* led-1 to led-3 are part of a single RGB led */ + led-1 { + label = "mc1:red:rgb"; + pwms = <&leds_pwm 1 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-2 { + label = "mc1:green:rgb"; + pwms = <&leds_pwm 2 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-3 { + label = "mc1:blue:rgb"; + pwms = <&leds_pwm 3 1000000 0>; + max-brightness = <255>; + active-low; + }; + }; + + panel: panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&backlight>; + enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + + port { + panel_input: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + + reg_3v3: regulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + /* supplied by either debug board or PoE */ + reg_5v2: regulator_5v2 { + compatible = "regulator-fixed"; + regulator-name = "5V2"; + regulator-min-microvolt = <5200000>; + regulator-max-microvolt = <5200000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", + "HWID4", "HWID5"; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + interrupt-parent = <&gpiod>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ + vcc-supply = <®_3v3>; + reg = <0x38>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + wakeup-source; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_c>; + pinctrl-1 = <<dc_sleep_pins_c>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&panel_input>; + }; + }; +}; + +&pmic { + regulators { + buck4-supply = <®_5v2>; /* VIN */ + ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ + ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ + boost-supply = <®_5v2>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_pins_a { + /* + * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to + * work, thus enable internal pull-ups. + */ + pins1 { + /delete-property/ bias-disable; + bias-pull-up; + }; + pins2 { + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers3 { + status = "okay"; + + backlight_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm3_pins_b>; + pinctrl-1 = <&pwm3_sleep_pins_b>; + status = "okay"; + }; +}; + +&timers5 { + status = "okay"; + + leds_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm5_pins_b>; + pinctrl-1 = <&pwm5_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi new file mode 100644 index 000000000000..e22871dc580c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski . + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Seeed Studio Odyssey-STM32MP157C SOM"; + compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + led { + compatible = "gpio-leds"; + led-blue { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts new file mode 100644 index 000000000000..a8b3f7a54703 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski . + */ + +/dts-v1/; + +#include "stm32mp157c-odyssey-som.dtsi" + +/ { + model = "Seeed Studio Odyssey-STM32MP157C Board"; + compatible = "seeed,stm32mp157c-odyssey", + "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_b>; + pinctrl-1 = <&dcmi_sleep_pins_b>; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ + st,eth-clk-sel; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { /* KSZ9031RN */ + reg = <7>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts new file mode 100644 index 000000000000..28d7203264ce --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +/dts-v1/; + +#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp157c-phycore-stm32mp15-som.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; + compatible = "phytec,phycore-stm32mp1-3", + "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &usart1; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +&fmc { + status = "disabled"; +}; + +&gpu { + status = "okay"; +}; + +&i2c4_eeprom { + status = "okay"; +}; + +&i2c4_rtc { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&sdmmc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi new file mode 100644 index 000000000000..4e8b2d2b30c7 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi @@ -0,0 +1,577 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp15-pinctrl.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP15 SOM"; + compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + rtc0 = &i2c4_rtc; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-enter { + label = "Enter"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-PHYCORE"; + routing = + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ + "Capture", "MCLK"; + dais = <&sai2b_port>, + <&sai2a_port>; + }; + + regulator_vin: regulator { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rgmii_pins_d>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + st,eth-clk-sel; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + + codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + + ai3x-micbias-vg = <2>; + + AVDD-supply = <&v3v3>; + IOVDD-supply = <&v3v3>; + DRVDD-supply = <&v3v3>; + DVDD-supply = <&v1v8_audio>; + + clocks = <&sai2b>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tlv320_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + + tlv320_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touch@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + vio-supply = <&v3v3>; + vcc-supply = <&v3v3>; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + type = ; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <®ulator_vin>; + buck2-supply = <®ulator_vin>; + buck3-supply = <®ulator_vin>; + buck4-supply = <®ulator_vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <®ulator_vin>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + boost-supply = <®ulator_vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + vdd_eth_2v5: ldo2 { + regulator-name = "dd_eth_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + vdd_eth_1v0: ldo6 { + regulator-name = "vdd_eth_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , + ; + interrupt-names = "onkey-falling", + "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + }; + }; + + i2c4_eeprom: eeprom@50 { + compatible = "microchip,24c32", + "atmel,24c32"; + reg = <0x50>; + }; + + i2c4_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + status = "okay"; + + flash0: flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; + pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; + status = "okay"; +}; + +&sai2a { + dma-names = "rx"; + st,sync = <&sai2b 2>; + clocks = <&rcc SAI2_K>, <&sai2b>; + clock-names = "sai_ck", "MCLK"; + #clock-cells = <0>; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&tlv320_rx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sai2b { + dma-names = "tx"; + #clock-cells = <0>; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&tlv320_tx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; + cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + pinctrl-3 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_a>; + pinctrl-1 = <&usart3_sleep_pins_a>; + pinctrl-2 = <&usart3_idle_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi new file mode 100644 index 000000000000..b06a55a2fa18 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + soc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi new file mode 100644 index 000000000000..35b1034aa3cf --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpiob { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the STM32 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "rs485-rx-en"; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-B", "", + "", "", "", "DRC02-Out1", + "DRC02-Out2", "", "", ""; +}; + +&gpioi { + gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", + "DHCOM-R", "DHCOM-M", "", "", + "DRC02-In2", "", "", "", + "", "", "", ""; + + /* + * NOTE: The USB Hub on the DRC02 needs a reset signal to be + * pulled high in order to be detected by the USB Controller. + * This signal should be handled by USB power sequencing in + * order to reset the Hub when USB bus is powered down, but + * so far there is no such functionality. + */ + usb-hub-hog { + gpio-hog; + gpios = <2 0>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c4 { + touchscreen@49 { + status = "disabled"; + }; +}; + +&i2c5 { /* TP7/TP8 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc3 { + /* + * On DRC02, the SoM does not have SDIO WiFi. The pins + * are used for on-board microSD slot instead. + */ + /delete-property/broken-cd; + cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; + disable-wp; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + /* Use PIO for the display */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; /* Enable once there is display driver */ + /* + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are + * also connected to the display board connector. + */ +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), + * however the STM32MP1 pinmux cannot map them to UART4 . + */ + +&uart8 { /* RS485 */ + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi new file mode 100644 index 000000000000..46b87a27d8b3 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_panel_bl>; + status = "okay"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + /* + * The EXTi IRQ line 3 is shared with ethernet, + * so mark this as polled GPIO key. + */ + button-0 { + label = "TA1-GPIO-A"; + linux,code = ; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + }; + + /* + * The EXTi IRQ line 6 is shared with touchscreen, + * so mark this as polled GPIO key. + */ + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + }; + + /* + * The EXTi IRQ line 0 is shared with PMIC, + * so mark this as polled GPIO key. + */ + button-2 { + label = "TA3-GPIO-C"; + linux,code = ; + gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-3 { + label = "TA4-GPIO-D"; + linux,code = ; + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "green:led5"; + gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + status = "disabled"; + }; + + led-1 { + label = "green:led6"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "green:led7"; + gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "green:led8"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + power-supply = <®_panel_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_panel_bl: regulator-panel-bl { + compatible = "regulator-fixed"; + regulator-name = "panel_backlight"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_panel_supply>; + }; + + reg_panel_supply: regulator-panel-supply { + compatible = "regulator-fixed"; + regulator-name = "panel_supply"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; + + sound { + compatible = "audio-graph-card"; + widgets = "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Microphone", "Microphone Jack"; + routing = "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + dais = <&sai2a_port &sai2b_port>; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +&i2c2 { /* Header X22 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&i2c5 { /* Header X21 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <&v3v3>; + VDDIO-supply = <&vdd>; + + sgtl5000_port: port { + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master = <&sgtl5000_tx_endpoint>; + bitclock-master = <&sgtl5000_tx_endpoint>; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master = <&sgtl5000_rx_endpoint>; + bitclock-master = <&sgtl5000_rx_endpoint>; + }; + }; + + }; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpioc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&sgtl5000_tx_endpoint>; + dai-format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&sgtl5000_rx_endpoint>; + dai-format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + pwm2: pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi new file mode 100644 index 000000000000..abc595350e71 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "yellow:led"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&fmc { + status = "disabled"; +}; + +&gpioa { + /* + * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable + * port power. This signal should be handled by USB power sequencing + * in order to turn on port power when USB bus is powered up, but so + * far there is no such functionality. + */ + usb-port-power-hog { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "usb-port-power"; + }; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "PicoITX-In1", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-B", "", + "", "", "", "PicoITX-Out1", + "PicoITX-Out2", "", "", ""; +}; + +&gpiog { + gpio-line-names = "PicoITX-In2", "", "", "", + "", "", "", "", + "DHCOM-L", "", "", "", + "", "", "", ""; +}; + +&i2c2 { /* On board-to-board connector (optional) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* On board-to-board connector */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&ksz8851 { + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi new file mode 100644 index 000000000000..e61df23d361a --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2019-2020 Marek Vasut + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &ksz8851; + rtc0 = &hwrtc; + rtc1 = &rtc; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; +}; + +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; +}; + +&adc2 { + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; +}; + +&crc1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "okay"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + /* LAN8710Ai */ + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + clocks = <&rcc CK_MCO2>; + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <500>; + smsc,disable-energy-detect; + interrupt-parent = <&gpioi>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ethernet@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-K", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "", "", "", + "DHCOM-Q", "", "", "", + "", "", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-E", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-B", "", + "", "", "", "DHCOM-F", + "DHCOM-D", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "", "DHCOM-P", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiof { + gpio-line-names = "", "", "", "DHCOM-A", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "DHCOM-C", "", "", "", + "", "", "", "", + "DHCOM-L", "", "", "", + "", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "", + "", "", "", "DHCOM-N", + "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", + "DHCOM-T", "", "DHCOM-S", ""; +}; + +&gpioi { + gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", + "DHCOM-R", "DHCOM-M", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + hwrtc: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-always-on; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + vio-supply = <&v3v3>; + interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep", "init"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; + cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&sdmmc1_b4_pins_a { + /* + * SD bus pull-up resistors: + * - optional on SoMs with SD voltage translator + * - mandatory on SoMs without SD voltage translator + */ + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi new file mode 100644 index 000000000000..0069ad75d55e --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +#include "stm32mp15xx-dhcor-io1v8.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &qspi; + }; + + /* XTal Q1 */ + cec_clock: clk-cec-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user0"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user1"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user2"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32-AV96-HDMI"; + dais = <&sai2a_port>; + status = "okay"; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpioz 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; +}; + +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; +}; + +&adc2 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; +}; + +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_c>; + pinctrl-1 = <&dcmi_sleep_pins_c>; + status = "disabled"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&stmipi_2>; + bus-type = <5>; + bus-width = <8>; + pclk-sample = <0>; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "AV96-K", + "AV96-I", "", "AV96-A", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "AV96-J", "", "", + "", "", "", "AV96-B", + "", "AV96-L", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "AV96-C", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "AV96-D", "", "", "", + "", "", "AV96-E", "AV96-F"; +}; + +&gpiof { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "AV96-G", "AV96-H", "", ""; +}; + +&i2c1 { /* X6 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { /* X6 I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + stmipi: stmipi@14 { + compatible = "st,st-mipid02"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mco1_pins_a>; + pinctrl-1 = <&mco1_sleep_pins_a>; + reg = <0x14>; + clocks = <&rcc CK_MCO1>; + clock-names = "xclk"; + assigned-clocks = <&rcc CK_MCO1>; + assigned-clock-parents = <&rcc CK_HSE>; + assigned-clock-rates = <24000000>; + VDDE-supply = <&v1v8>; + VDDIN-supply = <&v1v8>; + reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + stmipi_0: endpoint { + }; + }; + + port@2 { + reg = <2>; + stmipi_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmi_0>; + }; + }; + }; + }; + + hdmi-transmitter@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; + reg-names = "main", "edid", "cec", "packet"; + clocks = <&cec_clock>; + clock-names = "cec"; + + avdd-supply = <&v3v3>; + dvdd-supply = <&v3v3>; + pvdd-supply = <&v3v3>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v3v3>; + + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + + status = "okay"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + port@2 { + reg = <2>; + adv7513_i2s0: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; + }; + }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_d>; + pinctrl-1 = <<dc_sleep_pins_d>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&adv7513_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_c>; + pinctrl-1 = <&sai2a_sleep_pins_c>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&adv7513_i2s0>; + dai-format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi new file mode 100644 index 000000000000..92d906bfd5d7 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &ksz8851; + mmc0 = &sdmmc1; + rtc0 = &hwrtc; + rtc1 = &rtc; + serial0 = &uart4; + serial1 = &uart8; + serial2 = &usart3; + serial3 = &uart5; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "yellow:user0"; + gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "red:user1"; + gpios = <&gpioz 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpioh 2 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&adc { /* X11 ADC inputs */ + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + }; + + adc2: adc@100 { + status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ethernet@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "DRCC-VAR2", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "DRCC-GPIO0", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "DRCC-GPIO5", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "DRCC-HW2", + "DRCC-GPIO4", "", "", "", + "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1", + "DRCC-VAR0", "", "", "DRCC-GPIO6"; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "DRCC-GPIO2", + "", "DRCC-GPIO1", "", "", + "", "", "", ""; +}; + +&i2c1 { /* X11 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hwrtc: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&sdmmc1 { /* MicroSD */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc2 { /* eMMC */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc3 { /* SDIO Wi-Fi */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + bus-width = <4>; + mmc-ddr-3_3v; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi2 { /* X11 SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + label = "UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_d>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart5 { /* X11 UART */ + label = "X11-UART5"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + label = "RS485-1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart3 { /* RS485 or RS232 */ + label = "RS485-2"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart3_pins_e>; + pinctrl-1 = <&usart3_sleep_pins_e>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi new file mode 100644 index 000000000000..9937b28548c2 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/ { + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi new file mode 100644 index 000000000000..bba19f21e527 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi new file mode 100644 index 000000000000..ab7f0ba49639 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + }; + + adc2: adc@100 { + status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&i2c4 { + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi new file mode 100644 index 000000000000..511113f2e399 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -0,0 +1,741 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + led { + compatible = "gpio-leds"; + led-blue { + label = "heartbeat"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP15-DK"; + routing = + "Playback" , "MCLK", + "Capture" , "MCLK", + "MICL" , "Mic Bias"; + dais = <&sai2a_port &sai2b_port &i2s2_port>; + status = "okay"; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_usb_cc_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (56 + 47kOhms) * 5pF => 2.5us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; + }; + adc2: adc@100 { + status = "okay"; + /* USB Type-C CC1 & CC2 */ + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&cec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cec_pins_b>; + pinctrl-1 = <&cec_sleep_pins_b>; + status = "okay"; +}; + +&crc1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + hdmi-transmitter@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + #sound-dai-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@3 { + reg = <3>; + sii9022_tx_endpoint: endpoint { + remote-endpoint = <&i2s2_endpoint>; + }; + }; + }; + }; + + cs42l51: cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + #sound-dai-cells = <0>; + VL-supply = <&v3v3>; + VD-supply = <&v1v8_audio>; + VA-supply = <&v1v8_audio>; + VAHP-supply = <&v1v8_audio>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + clocks = <&sai2a>; + clock-names = "MCLK"; + status = "okay"; + + cs42l51_port: port { + #address-cells = <1>; + #size-cells = <0>; + + cs42l51_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master = <&cs42l51_tx_endpoint>; + bitclock-master = <&cs42l51_tx_endpoint>; + }; + + cs42l51_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master = <&cs42l51_rx_endpoint>; + bitclock-master = <&cs42l51_rx_endpoint>; + }; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + status = "okay"; + vdd-supply = <&vin>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&i2s2 { + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_a>; + pinctrl-1 = <&i2s2_sleep_pins_a>; + status = "okay"; + + i2s2_port: port { + i2s2_endpoint: endpoint { + remote-endpoint = <&sii9022_tx_endpoint>; + dai-format = "i2s"; + mclk-fs = <256>; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_a>; + pinctrl-1 = <<dc_sleep_pins_a>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&cs42l51_tx_endpoint>; + dai-format = "i2s"; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&cs42l51_rx_endpoint>; + dai-format = "i2s"; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm1_pins_a>; + pinctrl-1 = <&pwm1_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@0 { + status = "okay"; + }; +}; + +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; + pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&timers6 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + timer@5 { + status = "okay"; + }; +}; + +&timers12 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm12_pins_a>; + pinctrl-1 = <&pwm12_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@11 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_c>; + pinctrl-1 = <&uart7_sleep_pins_c>; + pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_c>; + pinctrl-1 = <&usart3_sleep_pins_c>; + pinctrl-2 = <&usart3_idle_pins_c>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi new file mode 100644 index 000000000000..a43965c86fe8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +#include "stm32mp15-pinctrl.dtsi" + +#include + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + }; + + pmic_watchdog: watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + sip_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + vcc-supply = <&vdd>; + reg = <0x50>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi new file mode 100644 index 000000000000..04f7a43ad66f --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@5000b000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@5000c000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + st,package = ; + + gpioz: gpio@54004000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi new file mode 100644 index 000000000000..328dad140e9b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <6>; + gpio-ranges = <&pinctrl 6 86 6>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl 6 102 10>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <2>; + gpio-ranges = <&pinctrl 0 112 2>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi new file mode 100644 index 000000000000..7eaa245f44db --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + st,package = ; + + gpioz: gpio@54004000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi new file mode 100644 index 000000000000..b63e207de216 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <6>; + gpio-ranges = <&pinctrl 6 86 6>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl 6 102 10>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <2>; + gpio-ranges = <&pinctrl 0 112 2>; + }; +}; diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi deleted file mode 100644 index dd30d08ccb9b..000000000000 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ /dev/null @@ -1,392 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Linaro Ltd - */ - -#include - -/ { - /* Essential housekeeping hardware monitors */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&gpadc 0x02>, /* Battery temperature */ - <&gpadc 0x03>, /* Main charger voltage */ - <&gpadc 0x08>, /* Main battery voltage */ - <&gpadc 0x09>, /* VBUS */ - <&gpadc 0x0a>, /* Main charger current */ - <&gpadc 0x0b>, /* USB charger current */ - <&gpadc 0x0c>, /* Backup battery voltage */ - <&gpadc 0x0d>, /* Die temperature */ - <&gpadc 0x12>; /* Crystal temperature */ - }; - - soc { - prcmu@80157000 { - ab8500 { - compatible = "stericsson,ab8500"; - interrupt-parent = <&intc>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ab8500_clock: clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; - }; - - ab8500_gpio: gpio { - compatible = "stericsson,ab8500-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, - <18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "60S", "ALARM"; - }; - - gpadc: adc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, - <39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - /* GPADC channels */ - bat_ctrl: channel@1 { - reg = <0x01>; - }; - btemp_ball: channel@2 { - reg = <0x02>; - }; - main_charger_v: channel@3 { - reg = <0x03>; - }; - acc_detect1: channel@4 { - reg = <0x04>; - }; - acc_detect2: channel@5 { - reg = <0x05>; - }; - adc_aux1: channel@6 { - reg = <0x06>; - }; - adc_aux2: channel@7 { - reg = <0x07>; - }; - main_batt_v: channel@8 { - reg = <0x08>; - }; - vbus_v: channel@9 { - reg = <0x09>; - }; - main_charger_c: channel@a { - reg = <0x0a>; - }; - usb_charger_c: channel@b { - reg = <0x0b>; - }; - bk_bat_v: channel@c { - reg = <0x0c>; - }; - die_temp: channel@d { - reg = <0x0d>; - }; - usb_id: channel@e { - reg = <0x0e>; - }; - xtal_temp: channel@12 { - reg = <0x12>; - }; - vbat_true_meas: channel@13 { - reg = <0x13>; - }; - bat_ctrl_and_ibat: channel@1c { - reg = <0x1c>; - }; - vbat_meas_and_ibat: channel@1d { - reg = <0x1d>; - }; - vbat_true_meas_and_ibat: channel@1e { - reg = <0x1e>; - }; - bat_temp_and_ibat: channel@1f { - reg = <0x1f>; - }; - }; - - thermal { - compatible = "stericsson,abx500-temp"; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ABX500_TEMP_WARM"; - }; - - ab8500_fg { - compatible = "stericsson,ab8500-fg"; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, - <8 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <27 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "NCONV_ACCU", - "BATT_OVV", - "LOW_BAT_F", - "CC_INT_CALIB", - "CCEOC"; - monitored-battery = <&battery>; - io-channels = <&gpadc 0x08>; - io-channel-names = "main_bat_v"; - }; - - ab8500_btemp { - compatible = "stericsson,ab8500-btemp"; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, - <80 IRQ_TYPE_LEVEL_HIGH>, - <83 IRQ_TYPE_LEVEL_HIGH>, - <81 IRQ_TYPE_LEVEL_HIGH>, - <82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "BAT_CTRL_INDB", - "BTEMP_LOW", - "BTEMP_HIGH", - "BTEMP_LOW_MEDIUM", - "BTEMP_MEDIUM_HIGH"; - monitored-battery = <&battery>; - io-channels = <&gpadc 0x02>, - <&gpadc 0x01>; - io-channel-names = "btemp_ball", - "bat_ctrl"; - }; - - ab8500_charger { - compatible = "stericsson,ab8500-charger"; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <11 IRQ_TYPE_LEVEL_HIGH>, - <0 IRQ_TYPE_LEVEL_HIGH>, - <107 IRQ_TYPE_LEVEL_HIGH>, - <106 IRQ_TYPE_LEVEL_HIGH>, - <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>, - <105 IRQ_TYPE_LEVEL_HIGH>, - <104 IRQ_TYPE_LEVEL_HIGH>, - <89 IRQ_TYPE_LEVEL_HIGH>, - <22 IRQ_TYPE_LEVEL_HIGH>, - <21 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "MAIN_CH_UNPLUG_DET", - "MAIN_CHARGE_PLUG_DET", - "MAIN_EXT_CH_NOT_OK", - "MAIN_CH_TH_PROT_R", - "MAIN_CH_TH_PROT_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_CH_TH_PROT_R", - "USB_CH_TH_PROT_F", - "USB_CHARGER_NOT_OKR", - "VBUS_OVV", - "CH_WD_EXP", - "VBUS_CH_DROP_END"; - monitored-battery = <&battery>; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - io-channels = <&gpadc 0x03>, - <&gpadc 0x0a>, - <&gpadc 0x09>, - <&gpadc 0x0b>; - io-channel-names = "main_charger_v", - "main_charger_c", - "vbus_v", - "usb_charger_c"; - }; - - ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - monitored-battery = <&battery>; - }; - - ab8500_usb: phy { - compatible = "stericsson,ab8500-usb"; - interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, - <96 IRQ_TYPE_LEVEL_HIGH>, - <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>, - <74 IRQ_TYPE_LEVEL_HIGH>, - <75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - clocks = <&prcmu_clk PRCMU_SYSCLK>; - clock-names = "sysclk"; - #phy-cells = <0>; - }; - - key { - compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, - <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - pwm@1 { - compatible = "stericsson,ab8500-pwm"; - reg = <1>; - clocks = <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "intclk"; - #pwm-cells = <1>; - }; - - pwm@2 { - compatible = "stericsson,ab8500-pwm"; - reg = <2>; - clocks = <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "intclk"; - #pwm-cells = <1>; - }; - - pwm@3 { - compatible = "stericsson,ab8500-pwm"; - reg = <3>; - clocks = <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "intclk"; - #pwm-cells = <1>; - }; - - codec: codec { - compatible = "stericsson,ab8500-codec"; - - V-AUD-supply = <&ab8500_ldo_audio_reg>; - V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; - V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; - V-DMIC-supply = <&ab8500_ldo_dmic_reg>; - - clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; - clock-names = "audioclk"; - - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; - - ext_regulators: regulator-external { - compatible = "stericsson,ab8500-ext-regulator"; - - ab8500_ext1_reg: ab8500_ext1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ab8500_ext2_reg: ab8500_ext2 { - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-boot-on; - regulator-always-on; - }; - - ab8500_ext3_reg: ab8500_ext3 { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - }; - }; - - regulator { - compatible = "stericsson,ab8500-regulator"; - vin-supply = <&ab8500_ext3_reg>; - - // supplies to the display/camera - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* BUG: If turned off MMC will be affected. */ - regulator-always-on; - }; - - // supplies to the on-board eMMC - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for VAUX3; SDcard slots - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - }; - - // supply for tvout; gpadc; TVOUT LDO - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - }; - - // supply for ab8500-vaudio; VAUDIO LDO - ab8500_ldo_audio_reg: ab8500_ldo_audio { - }; - - // supply for v-anamic1 VAMIC1 LDO - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - }; - - // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - }; - - // supply for v-dmic; VDMIC LDO - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - }; - - // supply for U8500 CSI/DSI; VANA LDO - ab8500_ldo_ana_reg: ab8500_ldo_ana { - }; - }; - }; - }; - - sound { - stericsson,audio-codec = <&codec>; - clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "sysclk", "ulpclk", "intclk"; - }; - - mcde@a0350000 { - vana-supply = <&ab8500_ldo_ana_reg>; - - dsi@a0351000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0352000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0353000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - }; - - usb_per5@a03e0000 { - phys = <&ab8500_usb>; - phy-names = "usb"; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi deleted file mode 100644 index 131c82508e82..000000000000 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Linaro Ltd - */ - -#include - -/ { - /* Essential housekeeping hardware monitors */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&gpadc 0x02>, /* Battery temperature */ - <&gpadc 0x08>, /* Main battery voltage */ - <&gpadc 0x09>, /* VBUS */ - <&gpadc 0x0b>, /* Charger current */ - <&gpadc 0x0c>, /* Backup battery voltage */ - <&gpadc 0x0d>; /* Die temperature */ - }; - - soc { - prcmu@80157000 { - ab8505 { - compatible = "stericsson,ab8505"; - interrupt-parent = <&intc>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ab8500_clock: clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; - }; - - ab8505_gpio: gpio { - compatible = "stericsson,ab8505-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, - <18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "60S", "ALARM"; - }; - - gpadc: adc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_adc_reg>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - /* GPADC channels */ - bat_ctrl: channel@1 { - reg = <0x01>; - }; - btemp_ball: channel@2 { - reg = <0x02>; - }; - acc_detect1: channel@4 { - reg = <0x04>; - }; - acc_detect2: channel@5 { - reg = <0x05>; - }; - adc_aux1: channel@6 { - reg = <0x06>; - }; - adc_aux2: channel@7 { - reg = <0x07>; - }; - main_batt_v: channel@8 { - reg = <0x08>; - }; - vbus_v: channel@9 { - reg = <0x09>; - }; - charger_c: channel@b { - reg = <0x0b>; - }; - bk_bat_v: channel@c { - reg = <0x0c>; - }; - die_temp: channel@d { - reg = <0x0d>; - }; - usb_id: channel@e { - reg = <0x0e>; - }; - }; - - thermal { - compatible = "stericsson,abx500-temp"; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ABX500_TEMP_WARM"; - }; - - ab8500_fg { - compatible = "stericsson,ab8500-fg"; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, - <8 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <27 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "NCONV_ACCU", - "BATT_OVV", - "LOW_BAT_F", - "CC_INT_CALIB", - "CCEOC"; - monitored-battery = <&battery>; - io-channels = <&gpadc 0x08>; - io-channel-names = "main_bat_v"; - }; - - ab8500_btemp { - compatible = "stericsson,ab8500-btemp"; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, - <80 IRQ_TYPE_LEVEL_HIGH>, - <83 IRQ_TYPE_LEVEL_HIGH>, - <81 IRQ_TYPE_LEVEL_HIGH>, - <82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "BAT_CTRL_INDB", - "BTEMP_LOW", - "BTEMP_HIGH", - "BTEMP_LOW_MEDIUM", - "BTEMP_MEDIUM_HIGH"; - monitored-battery = <&battery>; - io-channels = <&gpadc 0x02>, - <&gpadc 0x01>; - io-channel-names = "btemp_ball", - "bat_ctrl"; - }; - - ab8500_charger { - compatible = "stericsson,ab8500-charger"; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <11 IRQ_TYPE_LEVEL_HIGH>, - <0 IRQ_TYPE_LEVEL_HIGH>, - <107 IRQ_TYPE_LEVEL_HIGH>, - <106 IRQ_TYPE_LEVEL_HIGH>, - <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>, - <105 IRQ_TYPE_LEVEL_HIGH>, - <104 IRQ_TYPE_LEVEL_HIGH>, - <89 IRQ_TYPE_LEVEL_HIGH>, - <22 IRQ_TYPE_LEVEL_HIGH>, - <21 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "MAIN_CH_UNPLUG_DET", - "MAIN_CHARGE_PLUG_DET", - "MAIN_EXT_CH_NOT_OK", - "MAIN_CH_TH_PROT_R", - "MAIN_CH_TH_PROT_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_CH_TH_PROT_R", - "USB_CH_TH_PROT_F", - "USB_CHARGER_NOT_OKR", - "VBUS_OVV", - "CH_WD_EXP", - "VBUS_CH_DROP_END"; - monitored-battery = <&battery>; - vddadc-supply = <&ab8500_ldo_adc_reg>; - io-channels = <&gpadc 0x09>, - <&gpadc 0x0b>; - io-channel-names = "vbus_v", - "usb_charger_c"; - }; - - ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - monitored-battery = <&battery>; - }; - - ab8500_usb: phy { - compatible = "stericsson,ab8500-usb"; - interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, - <96 IRQ_TYPE_LEVEL_HIGH>, - <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>, - <74 IRQ_TYPE_LEVEL_HIGH>, - <75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - clocks = <&prcmu_clk PRCMU_SYSCLK>; - clock-names = "sysclk"; - #phy-cells = <0>; - }; - - key { - compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, - <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - pwm@1 { - compatible = "stericsson,ab8500-pwm"; - reg = <1>; - clocks = <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "intclk"; - #pwm-cells = <1>; - }; - - codec: codec { - compatible = "stericsson,ab8500-codec"; - - V-AUD-supply = <&ab8500_ldo_audio_reg>; - V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; - V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; - - clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; - clock-names = "audioclk"; - - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; - - regulator { - compatible = "stericsson,ab8505-regulator"; - - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux4_reg: ab8500_ldo_aux4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux5_reg: ab8500_ldo_aux5 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <2790000>; - }; - - ab8500_ldo_aux6_reg: ab8500_ldo_aux6 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <2790000>; - }; - - // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - // supply for gpadc; ADC LDO - ab8500_ldo_adc_reg: ab8500_ldo_adc { - }; - - // supply for ab8500-vaudio; VAUDIO LDO - ab8500_ldo_audio_reg: ab8500_ldo_audio { - }; - - // supply for v-anamic1 VAMIC1 LDO - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - }; - - // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - }; - - // supply for v-aux8; VAUX8 LDO - ab8500_ldo_aux8_reg: ab8500_ldo_aux8 { - }; - - // supply for U8500 CSI/DSI; VANA LDO - ab8500_ldo_ana_reg: ab8500_ldo_ana { - }; - }; - }; - }; - - sound { - stericsson,audio-codec = <&codec>; - clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "sysclk", "ulpclk", "intclk"; - }; - - mcde@a0350000 { - vana-supply = <&ab8500_ldo_ana_reg>; - - dsi@a0351000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0352000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0353000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - }; - - usb_per5@a03e0000 { - phys = <&ab8500_usb>; - phy-names = "usb"; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/ste-db8500.dtsi deleted file mode 100644 index f1ff3f4835d7..000000000000 --- a/arch/arm/boot/dts/ste-db8500.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ste-dbx5x0.dtsi" - -/ { - cpus { - cpu@300 { - operating-points = <998400 0 - 798720 0 - 399360 0 - 199680 0>; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Modem trace memory */ - ram@6000000 { - reg = <0x06000000 0x00f00000>; - no-map; - }; - - /* Modem shared memory */ - ram@6f00000 { - reg = <0x06f00000 0x00100000>; - no-map; - }; - - /* Modem private memory */ - ram@7000000 { - reg = <0x07000000 0x01000000>; - no-map; - }; - - /* - * Initial Secure Software ISSW memory - * - * This is probably only used if the kernel tries - * to actually call into trustzone to run secure - * applications, which the mainline kernel probably - * will not do on this old chipset. But you can never - * be too careful, so reserve this memory anyway. - */ - ram@17f00000 { - reg = <0x17f00000 0x00100000>; - no-map; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/ste-db8520.dtsi deleted file mode 100644 index e4e8d5fc1f8a..000000000000 --- a/arch/arm/boot/dts/ste-db8520.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ste-dbx5x0.dtsi" - -/ { - cpus { - cpu@300 { - operating-points = <1152000 0 - 798720 0 - 399360 0 - 199680 0>; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Modem trace memory */ - ram@6000000 { - reg = <0x06000000 0x00f00000>; - no-map; - }; - - /* Modem shared memory */ - ram@6f00000 { - reg = <0x06f00000 0x00100000>; - no-map; - }; - - /* Modem private memory */ - ram@7000000 { - reg = <0x07000000 0x01000000>; - no-map; - }; - - /* - * Initial Secure Software ISSW memory - * - * This is probably only used if the kernel tries - * to actually call into trustzone to run secure - * applications, which the mainline kernel probably - * will not do on this old chipset. But you can never - * be too careful, so reserve this memory anyway. - */ - ram@17f00000 { - reg = <0x17f00000 0x00100000>; - no-map; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-db9500.dtsi b/arch/arm/boot/dts/ste-db9500.dtsi deleted file mode 100644 index 4273d36e881d..000000000000 --- a/arch/arm/boot/dts/ste-db9500.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ste-dbx5x0.dtsi" - -/ { - cpus { - cpu@300 { - operating-points = <998400 0 - 798720 0 - 399360 0 - 199680 0>; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Initial Secure Software ISSW memory - * - * This is probably only used if the kernel tries - * to actually call into trustzone to run secure - * applications, which the mainline kernel probably - * will not do on this old chipset. But you can never - * be too careful, so reserve this memory anyway. - */ - ram@17f00000 { - reg = <0x17f00000 0x00100000>; - no-map; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi deleted file mode 100644 index 31a86606beda..000000000000 --- a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi +++ /dev/null @@ -1,650 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Linaro Ltd. - */ - -#include "ste-nomadik-pinctrl.dtsi" - -&pinctrl { - /* Settings for all UART default and sleep states */ - uart0 { - u0_a_1_default: u0_a_1_default { - default_mux { - function = "u0"; - groups = "u0_a_1"; - }; - default_cfg1 { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ - ste,config = <&out_hi>; - }; - }; - - u0_a_1_sleep: u0_a_1_sleep { - sleep_cfg1 { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO1_AJ3"; /* RTS */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO3_AH3"; /* TXD */ - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - }; - - uart1 { - u1rxtx_a_1_default: u1rxtx_a_1_default { - default_mux { - function = "u1"; - groups = "u1rxtx_a_1"; - }; - default_cfg1 { - pins = "GPIO4_AH6"; /* RXD */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO5_AG6"; /* TXD */ - ste,config = <&out_hi>; - }; - }; - - u1rxtx_a_1_sleep: u1rxtx_a_1_sleep { - sleep_cfg1 { - pins = "GPIO4_AH6"; /* RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO5_AG6"; /* TXD */ - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - - u1ctsrts_a_1_default: u1ctsrts_a_1_default { - default_mux { - function = "u1"; - groups = "u1ctsrts_a_1"; - }; - default_cfg1 { - pins = "GPIO6_AF6"; /* CTS */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO7_AG5"; /* RTS */ - ste,config = <&out_hi>; - }; - }; - - u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep { - sleep_cfg1 { - pins = "GPIO6_AF6"; /* CTS */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO7_AG5"; /* RTS */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - }; - }; - - uart2 { - u2rxtx_c_1_default: u2rxtx_c_1_default { - default_mux { - function = "u2"; - groups = "u2rxtx_c_1"; - }; - default_cfg1 { - pins = "GPIO29_W2"; /* RXD */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO30_W3"; /* TXD */ - ste,config = <&out_hi>; - }; - }; - - u2rxtx_c_1_sleep: u2rxtx_c_1_sleep { - sleep_cfg1 { - pins = "GPIO29_W2"; /* RXD */ - ste,config = <&in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO30_W3"; /* TXD */ - ste,config = <&out_wkup_pdis>; - }; - }; - }; - - /* Settings for all I2C default and sleep states */ - i2c0 { - i2c0_a_1_default: i2c0_a_1_default { - default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - default_cfg1 { - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c0_a_1_sleep: i2c0_a_1_sleep { - sleep_cfg1 { - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c1 { - i2c1_b_2_default: i2c1_b_2_default { - default_mux { - function = "i2c1"; - groups = "i2c1_b_2"; - }; - default_cfg1 { - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c1_b_2_sleep: i2c1_b_2_sleep { - sleep_cfg1 { - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c2 { - i2c2_b_1_default: i2c2_b_1_default { - default_mux { - function = "i2c2"; - groups = "i2c2_b_1"; - }; - default_cfg1 { - pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c2_b_1_sleep: i2c2_b_1_sleep { - sleep_cfg1 { - pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - - i2c2_b_2_default: i2c2_b_2_default { - default_mux { - function = "i2c2"; - groups = "i2c2_b_2"; - }; - default_cfg1 { - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c2_b_2_sleep: i2c2_b_2_sleep { - sleep_cfg1 { - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c3 { - i2c3_c_2_default: i2c3_c_2_default { - default_mux { - function = "i2c3"; - groups = "i2c3_c_2"; - }; - default_cfg1 { - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c3_c_2_sleep: i2c3_c_2_sleep { - sleep_cfg1 { - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* - * Activating I2C4 will conflict with UART1 about the same pins so do not - * enable I2C4 and UART1 at the same time. - */ - i2c4 { - i2c4_b_1_default: i2c4_b_1_default { - default_mux { - function = "i2c4"; - groups = "i2c4_b_1"; - }; - default_cfg1 { - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c4_b_1_sleep: i2c4_b_1_sleep { - sleep_cfg1 { - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* Settings for all MMC/SD/SDIO default and sleep states */ - sdi0 { - /* This is the external SD card slot, 4 bits wide */ - mc0_a_1_default: mc0_a_1_default { - default_mux { - function = "mc0"; - groups = "mc0_a_1"; - }; - default_cfg1 { - pins = - "GPIO18_AC2", /* CMDDIR */ - "GPIO19_AC1", /* DAT0DIR */ - "GPIO20_AB4"; /* DAT2DIR */ - ste,config = <&out_hi>; - }; - default_cfg2 { - pins = "GPIO22_AA3"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg4 { - pins = - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc0_a_1_sleep: mc0_a_1_sleep { - sleep_cfg1 { - pins = - "GPIO18_AC2", /* CMDDIR */ - "GPIO19_AC1", /* DAT0DIR */ - "GPIO20_AB4"; /* DAT2DIR */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO22_AA3", /* FBCLK */ - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - }; - - mc0_a_2_default: mc0_a_2_default { - default_mux { - function = "mc0"; - groups = "mc0_a_2"; - }; - default_cfg1 { - pins = "GPIO22_AA3"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg2 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg3 { - pins = - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc0_a_2_sleep: mc0_a_2_sleep { - sleep_cfg1 { - pins = - "GPIO22_AA3", /* FBCLK */ - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - }; - }; - - sdi1 { - /* This is the WLAN SDIO 4 bits wide */ - mc1_a_1_default: mc1_a_1_default { - default_mux { - function = "mc1"; - groups = "mc1_a_1"; - }; - default_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO209_AG15"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc1_a_1_sleep: mc1_a_1_sleep { - sleep_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO209_AG15", /* FBCLK */ - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - - mc1_a_2_default: mc1_a_2_default { - default_mux { - function = "mc1"; - groups = "mc1_a_2"; - }; - default_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc1_a_2_sleep: mc1_a_2_sleep { - sleep_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - sdi2 { - /* This is the eMMC 8 bits wide, usually PoP eMMC */ - mc2_a_1_default: mc2_a_1_default { - default_mux { - function = "mc2"; - groups = "mc2_a_1"; - }; - default_cfg1 { - pins = "GPIO128_A5"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO130_C8"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO129_B4", /* CMD */ - "GPIO131_A12", /* DAT0 */ - "GPIO132_C10", /* DAT1 */ - "GPIO133_B10", /* DAT2 */ - "GPIO134_B9", /* DAT3 */ - "GPIO135_A9", /* DAT4 */ - "GPIO136_C7", /* DAT5 */ - "GPIO137_A7", /* DAT6 */ - "GPIO138_C5"; /* DAT7 */ - ste,config = <&in_pu>; - }; - }; - - mc2_a_1_sleep: mc2_a_1_sleep { - sleep_cfg1 { - pins = "GPIO128_A5"; /* CLK */ - ste,config = <&out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO130_C8", /* FBCLK */ - "GPIO129_B4"; /* CMD */ - ste,config = <&in_wkup_pdis_en>; - }; - sleep_cfg3 { - pins = - "GPIO131_A12", /* DAT0 */ - "GPIO132_C10", /* DAT1 */ - "GPIO133_B10", /* DAT2 */ - "GPIO134_B9", /* DAT3 */ - "GPIO135_A9", /* DAT4 */ - "GPIO136_C7", /* DAT5 */ - "GPIO137_A7", /* DAT6 */ - "GPIO138_C5"; /* DAT7 */ - ste,config = <&in_wkup_pdis>; - }; - }; - }; - - sdi4 { - /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ - mc4_a_1_default: mc4_a_1_default { - default_mux { - function = "mc4"; - groups = "mc4_a_1"; - }; - default_cfg1 { - pins = "GPIO203_AE23"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO202_AF25"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO201_AF24", /* CMD */ - "GPIO200_AH26", /* DAT0 */ - "GPIO199_AH23", /* DAT1 */ - "GPIO198_AG25", /* DAT2 */ - "GPIO197_AH24", /* DAT3 */ - "GPIO207_AJ23", /* DAT4 */ - "GPIO206_AG24", /* DAT5 */ - "GPIO205_AG23", /* DAT6 */ - "GPIO204_AF23"; /* DAT7 */ - ste,config = <&in_pu>; - }; - }; - - mc4_a_1_sleep: mc4_a_1_sleep { - sleep_cfg1 { - pins = "GPIO203_AE23"; /* CLK */ - ste,config = <&out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO202_AF25", /* FBCLK */ - "GPIO201_AF24", /* CMD */ - "GPIO200_AH26", /* DAT0 */ - "GPIO199_AH23", /* DAT1 */ - "GPIO198_AG25", /* DAT2 */ - "GPIO197_AH24", /* DAT3 */ - "GPIO207_AJ23", /* DAT4 */ - "GPIO206_AG24", /* DAT5 */ - "GPIO205_AG23", /* DAT6 */ - "GPIO204_AF23"; /* DAT7 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* - * Multi-rate serial ports (MSPs) - MSP3 output is internal and - * cannot be muxed onto any pins. - */ - msp0 { - msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default { - default_msp0_mux { - function = "msp0"; - groups = "msp0txrx_a_1", "msp0tfstck_a_1"; - }; - default_msp0_cfg { - pins = - "GPIO12_AC4", /* TXD */ - "GPIO15_AC3", /* RXD */ - "GPIO13_AF3", /* TFS */ - "GPIO14_AE3"; /* TCK */ - ste,config = <&in_nopull>; - }; - }; - }; - - msp1 { - msp1txrx_a_1_default: msp1txrx_a_1_default { - default_mux { - function = "msp1"; - groups = "msp1txrx_a_1", "msp1_a_1"; - }; - default_cfg1 { - pins = "GPIO33_AF2"; - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO34_AE1", - "GPIO35_AE2", - "GPIO36_AG2"; - ste,config = <&in_nopull>; - }; - }; - }; - - msp2 { - msp2_a_1_default: msp2_a_1_default { - /* MSP2 usually used for HDMI audio */ - default_mux { - function = "msp2"; - groups = "msp2_a_1"; - }; - default_cfg1 { - pins = - "GPIO193_AH27", /* TXD */ - "GPIO194_AF27", /* TCK */ - "GPIO195_AG28"; /* TFS */ - ste,config = <&in_pd>; - }; - default_cfg2 { - pins = "GPIO196_AG26"; /* RXD */ - ste,config = <&out_lo>; - }; - }; - }; - - musb { - usb_a_1_default: usb_a_1_default { - default_mux { - function = "usb"; - groups = "usb_a_1"; - }; - default_cfg1 { - pins = - "GPIO256_AF28", /* NXT */ - "GPIO258_AD29", /* XCLK */ - "GPIO259_AC29", /* DIR */ - "GPIO260_AD28", /* DAT7 */ - "GPIO261_AD26", /* DAT6 */ - "GPIO262_AE26", /* DAT5 */ - "GPIO263_AG29", /* DAT4 */ - "GPIO264_AE27", /* DAT3 */ - "GPIO265_AD27", /* DAT2 */ - "GPIO266_AC28", /* DAT1 */ - "GPIO267_AC27"; /* DAT0 */ - ste,config = <&in_nopull>; - }; - default_cfg2 { - pins = "GPIO257_AE29"; /* STP */ - ste,config = <&out_hi>; - }; - }; - - usb_a_1_sleep: usb_a_1_sleep { - sleep_cfg1 { - pins = - "GPIO256_AF28", /* NXT */ - "GPIO258_AD29", /* XCLK */ - "GPIO259_AC29"; /* DIR */ - ste,config = <&slpm_wkup_pdis_en>; - }; - sleep_cfg2 { - pins = "GPIO257_AE29"; /* STP */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg3 { - pins = - "GPIO260_AD28", /* DAT7 */ - "GPIO261_AD26", /* DAT6 */ - "GPIO262_AE26", /* DAT5 */ - "GPIO263_AG29", /* DAT4 */ - "GPIO264_AE27", /* DAT3 */ - "GPIO265_AD27", /* DAT2 */ - "GPIO266_AC28", /* DAT1 */ - "GPIO267_AC27"; /* DAT0 */ - ste,config = <&slpm_in_wkup_pdis_en>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi deleted file mode 100644 index d5d88771ef97..000000000000 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ /dev/null @@ -1,1238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Linaro Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - /* This stablilizes the device enumeration */ - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "ste,dbx500-smp"; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - }; - }; - CPU0: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x300>; - clocks = <&prcmu_clk PRCMU_ARMSS>; - clock-names = "cpu"; - clock-latency = <20000>; - #cooling-cells = <2>; - }; - CPU1: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x301>; - }; - }; - - thermal-zones { - /* - * Thermal zone for the SoC, using the thermal sensor in the - * PRCMU for temperature and the cpufreq driver for passive - * cooling. - */ - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - /* - * This sensor fires interrupts to update the thermal - * zone, so no polling is needed. - */ - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu_alert: cpu-alert { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-crit { - temperature = <85000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - trip = <&cpu_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <100>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "stericsson,db8500", "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - /* - * 640KB ESRAM (embedded static random access memory), divided - * into 5 banks of 128 KB each. This is a fast memory usually - * used by different accelerators. We group these according to - * their power domains: ESRAM0 (always on) ESRAM 1+2 and - * ESRAM 3+4. - */ - sram@40000000 { - /* The first (always on) ESRAM 0, 128 KB */ - compatible = "mmio-sram"; - reg = <0x40000000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x20000>; - - sram@0 { - compatible = "stericsson,u8500-esram"; - reg = <0x0 0x10000>; - pool; - }; - lcpa: sram@10000 { - /* - * This eSRAM is used by the DMA40 DMA controller - * for Logical Channel Paramers (LCP), the address - * where these parameters are stored is called "LCPA". - * This is addressed directly by the driver so no - * pool is used. - */ - compatible = "stericsson,u8500-esram"; - label = "DMA40-LCPA"; - reg = <0x10000 0x800>; - }; - sram@10800 { - compatible = "stericsson,u8500-esram"; - reg = <0x10800 0xf800>; - pool; - }; - }; - sram@40020000 { - /* ESRAM 1+2, 256 KB */ - compatible = "mmio-sram"; - reg = <0x40020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x40000>; - }; - sram@40060000 { - /* ESRAM 3+4, 256 KB */ - compatible = "mmio-sram"; - reg = <0x40060000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40060000 0x40000>; - - lcla: sram@20000 { - /* - * This eSRAM is used by the DMA40 DMA controller - * for Logical Channel Logical Addresses (LCLA), the address - * where these parameters are stored is called "LCLA". - * This is addressed directly by the driver so no - * pool is used. - */ - compatible = "stericsson,u8500-esram"; - label = "DMA40-LCLA"; - reg = <0x20000 0x2000>; - }; - }; - - ptm@801ae000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x801ae000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - cpu = <&CPU0>; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@801af000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x801af000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - cpu = <&CPU1>; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - funnel@801a6000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x801a6000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - out-ports { - port { - funnel_out_port: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "atclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port>; - }; - }; - }; - }; - - tpiu@80190000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x80190000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - etb@801a4000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x801a4000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - intc: interrupt-controller@a0411000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xa0411000 0x1000>, - <0xa0410100 0x100>; - }; - - scu@a0410000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xa0410000 0x100>; - }; - - /* - * The backup RAM is used for retention during sleep - * and various things like spin tables - */ - backupram@80150000 { - compatible = "ste,dbx500-backupram"; - reg = <0x80150000 0x2000>; - }; - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xa0412000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - pm_domains: pm_domains0 { - compatible = "stericsson,ux500-pm-domains"; - #power-domain-cells = <1>; - }; - - clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - prcc_reset: prcc-reset-controller { - #reset-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; - - clkout_clk: clkout-clock { - /* Cell 1 id, cell 2 source, cell 3 div */ - #clock-cells = <3>; - }; - }; - - mtu@a03c6000 { - /* Nomadik System Timer */ - compatible = "st,nomadik-mtu"; - reg = <0xa03c6000 0x1000>; - interrupts = ; - - clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; - clock-names = "timclk", "apb_pclk"; - }; - - timer@a0410600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xa0410600 0x20>; - interrupts = ; - - clocks = <&smp_twd_clk>; - }; - - watchdog@a0410620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xa0410620 0x20>; - interrupts = ; - clocks = <&smp_twd_clk>; - }; - - rtc@80154000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x80154000 0x1000>; - interrupts = ; - - clocks = <&rtc_clk>; - clock-names = "apb_pclk"; - }; - - gpio0: gpio@8012e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - clocks = <&prcc_pclk 1 9>; - }; - - gpio1: gpio@8012e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 5>; - clocks = <&prcc_pclk 1 9>; - }; - - gpio2: gpio@8000e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio3: gpio@8000e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - gpio-ranges = <&pinctrl 0 96 2>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio4: gpio@8000e100 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e100 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <4>; - gpio-ranges = <&pinctrl 0 128 32>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio5: gpio@8000e180 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e180 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <5>; - gpio-ranges = <&pinctrl 0 160 12>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio6: gpio@8011e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <6>; - gpio-ranges = <&pinctrl 0 192 32>; - clocks = <&prcc_pclk 2 11>; - }; - - gpio7: gpio@8011e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <7>; - gpio-ranges = <&pinctrl 0 224 7>; - clocks = <&prcc_pclk 2 11>; - }; - - gpio8: gpio@a03fe000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0xa03fe000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <8>; - gpio-ranges = <&pinctrl 0 256 12>; - clocks = <&prcc_pclk 5 1>; - }; - - pinctrl: pinctrl { - compatible = "stericsson,db8500-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, - <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, - <&gpio8>; - prcm = <&prcmu>; - }; - - usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb"; - reg = <0xa03e0000 0x10000>; - interrupts = ; - interrupt-names = "mc"; - - dr_mode = "otg"; - - dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ - <&dma 38 0 0x0>, /* Logical - MemToDev */ - <&dma 37 0 0x2>, /* Logical - DevToMem */ - <&dma 37 0 0x0>, /* Logical - MemToDev */ - <&dma 36 0 0x2>, /* Logical - DevToMem */ - <&dma 36 0 0x0>, /* Logical - MemToDev */ - <&dma 19 0 0x2>, /* Logical - DevToMem */ - <&dma 19 0 0x0>, /* Logical - MemToDev */ - <&dma 18 0 0x2>, /* Logical - DevToMem */ - <&dma 18 0 0x0>, /* Logical - MemToDev */ - <&dma 17 0 0x2>, /* Logical - DevToMem */ - <&dma 17 0 0x0>, /* Logical - MemToDev */ - <&dma 16 0 0x2>, /* Logical - DevToMem */ - <&dma 16 0 0x0>, /* Logical - MemToDev */ - <&dma 39 0 0x2>, /* Logical - DevToMem */ - <&dma 39 0 0x0>; /* Logical - MemToDev */ - - dma-names = "iep_1_9", "oep_1_9", - "iep_2_10", "oep_2_10", - "iep_3_11", "oep_3_11", - "iep_4_12", "oep_4_12", - "iep_5_13", "oep_5_13", - "iep_6_14", "oep_6_14", - "iep_7_15", "oep_7_15", - "iep_8", "oep_8"; - - clocks = <&prcc_pclk 5 0>; - }; - - dma: dma-controller@801C0000 { - compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000>; - reg-names = "base"; - interrupts = ; - sram = <&lcpa>, <&lcla>; - - #dma-cells = <3>; - memcpy-channels = <56 57 58 59 60>; - - clocks = <&prcmu_clk PRCMU_DMACLK>; - }; - - prcmu: prcmu@80157000 { - compatible = "stericsson,db8500-prcmu", "syscon"; - reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; - reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - prcmu-timer-4@80157450 { - compatible = "stericsson,db8500-prcmu-timer-4"; - reg = <0x80157450 0xC>; - }; - - thermal: thermal@801573c0 { - compatible = "stericsson,db8500-thermal"; - reg = <0x801573c0 0x40>; - interrupt-parent = <&prcmu>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, - <22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; - #thermal-sensor-cells = <0>; - }; - - db8500-prcmu-regulators { - compatible = "stericsson,db8500-prcmu-regulator"; - - // DB8500_REGULATOR_VAPE - db8500_vape_reg: db8500_vape { - regulator-always-on; - }; - - // DB8500_REGULATOR_VARM - db8500_varm_reg: db8500_varm { - }; - - // DB8500_REGULATOR_VMODEM - db8500_vmodem_reg: db8500_vmodem { - }; - - // DB8500_REGULATOR_VPLL - db8500_vpll_reg: db8500_vpll { - }; - - // DB8500_REGULATOR_VSMPS1 - db8500_vsmps1_reg: db8500_vsmps1 { - }; - - // DB8500_REGULATOR_VSMPS2 - db8500_vsmps2_reg: db8500_vsmps2 { - }; - - // DB8500_REGULATOR_VSMPS3 - db8500_vsmps3_reg: db8500_vsmps3 { - }; - - // DB8500_REGULATOR_VRF1 - db8500_vrf1_reg: db8500_vrf1 { - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSP - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSPRET - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - }; - - // DB8500_REGULATOR_SWITCH_SVAPIPE - db8500_sva_pipe_reg: db8500_sva_pipe { - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSP - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSPRET - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - }; - - // DB8500_REGULATOR_SWITCH_SIAPIPE - db8500_sia_pipe_reg: db8500_sia_pipe { - }; - - // DB8500_REGULATOR_SWITCH_SGA - db8500_sga_reg: db8500_sga { - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_B2R2_MCDE - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12 - db8500_esram12_reg: db8500_esram12 { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12RET - db8500_esram12_ret_reg: db8500_esram12_ret { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34 - db8500_esram34_reg: db8500_esram34 { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34RET - db8500_esram34_ret_reg: db8500_esram34_ret { - }; - }; - }; - - i2c0: i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80004000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - clock-frequency = <400000>; - clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; - - status = "disabled"; - }; - - i2c1: i2c@80122000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80122000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; - - status = "disabled"; - }; - - i2c2: i2c@80128000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80128000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; - - status = "disabled"; - }; - - i2c3: i2c@80110000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80110000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; - - status = "disabled"; - }; - - i2c4: i2c@8012a000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x8012a000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; - - status = "disabled"; - }; - - ssp0: spi@80002000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80002000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "sspclk", "apb_pclk"; - dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ - <&dma 8 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; - - status = "disabled"; - }; - - ssp1: spi@80003000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80003000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "sspclk", "apb_pclk"; - dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ - <&dma 9 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; - - status = "disabled"; - }; - - spi0: spi@8011a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8011a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "sspclk", "apb_pclk"; - dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ - <&dma 0 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi1: spi@80112000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80112000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "sspclk", "apb_pclk"; - dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ - <&dma 35 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi2: spi@80111000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80111000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "sspclk", "apb_pclk"; - dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ - <&dma 33 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi3: spi@80129000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80129000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "sspclk", "apb_pclk"; - dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ - <&dma 40 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; - - status = "disabled"; - }; - - serial0: serial@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = ; - - dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ - <&dma 13 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; - clock-names = "uart", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; - - status = "disabled"; - }; - - serial1: serial@80121000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80121000 0x1000>; - interrupts = ; - - dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ - <&dma 12 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; - clock-names = "uart", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; - - status = "disabled"; - }; - - serial2: serial@80007000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80007000 0x1000>; - interrupts = ; - - dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ - <&dma 11 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; - clock-names = "uart", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; - - status = "disabled"; - }; - - mmc@80126000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80126000 0x1000>; - interrupts = ; - - dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ - <&dma 29 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; - - status = "disabled"; - }; - - mmc@80118000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80118000 0x1000>; - interrupts = ; - - dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ - <&dma 32 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; - - status = "disabled"; - }; - - mmc@80005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80005000 0x1000>; - interrupts = ; - - dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ - <&dma 28 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; - - status = "disabled"; - }; - - mmc@80119000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80119000 0x1000>; - interrupts = ; - - dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ - <&dma 41 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; - - status = "disabled"; - }; - - mmc@80114000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80114000 0x1000>; - interrupts = ; - - dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ - <&dma 42 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; - - status = "disabled"; - }; - - mmc@80008000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80008000 0x1000>; - interrupts = ; - - dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ - <&dma 43 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; - - status = "disabled"; - }; - - sound { - compatible = "stericsson,snd-soc-mop500"; - stericsson,cpu-dai = <&msp1 &msp3>; - }; - - msp0: msp@80123000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80123000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ - <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; - clock-names = "msp", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; - - status = "disabled"; - }; - - msp1: msp@80124000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80124000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - /* This DMA channel only exist on DB8500 v1 */ - dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ - dma-names = "tx"; - - clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; - clock-names = "msp", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; - - status = "disabled"; - }; - - // HDMI sound - msp2: msp@80117000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80117000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ - <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev - HighPrio - Fixed */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; - clock-names = "msp", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; - - status = "disabled"; - }; - - msp3: msp@80125000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80125000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - /* This DMA channel only exist on DB8500 v2 */ - dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ - dma-names = "rx"; - - clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; - clock-names = "msp", "apb_pclk"; - resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; - - status = "disabled"; - }; - - external-bus@50000000 { - compatible = "simple-bus"; - reg = <0x50000000 0x4000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000000>; - status = "disabled"; - }; - - gpu@a0300000 { - /* - * This block is referred to as "Smart Graphics Adapter SGA500" - * in documentation but is in practice a pretty straight-forward - * MALI-400 GPU block. - */ - compatible = "stericsson,db8500-mali", "arm,mali-400"; - reg = <0xa0300000 0x10000>; - interrupts = , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "combined"; - clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; - clock-names = "bus", "core"; - mali-supply = <&db8500_sga_reg>; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - mcde@a0350000 { - compatible = "ste,mcde"; - reg = <0xa0350000 0x1000>; - interrupts = ; - epod-supply = <&db8500_b2r2_mcde_reg>; - clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ - <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ - <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ - clock-names = "mcde", "lcd", "hdmi"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - dsi0: dsi@a0351000 { - compatible = "ste,mcde-dsi"; - reg = <0xa0351000 0x1000>; - clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; - clock-names = "hs", "lp"; - #address-cells = <1>; - #size-cells = <0>; - }; - dsi1: dsi@a0352000 { - compatible = "ste,mcde-dsi"; - reg = <0xa0352000 0x1000>; - clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; - clock-names = "hs", "lp"; - #address-cells = <1>; - #size-cells = <0>; - }; - dsi2: dsi@a0353000 { - compatible = "ste,mcde-dsi"; - reg = <0xa0353000 0x1000>; - /* This DSI port only has the Low Power / Energy Save clock */ - clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; - clock-names = "lp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cryp@a03cb000 { - compatible = "stericsson,ux500-cryp"; - reg = <0xa03cb000 0x1000>; - interrupts = ; - clocks = <&prcc_pclk 6 1>; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - hash@a03c2000 { - compatible = "stericsson,ux500-hash"; - reg = <0xa03c2000 0x1000>; - clocks = <&prcc_pclk 6 2>; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi deleted file mode 100644 index e1de9d389a01..000000000000 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ /dev/null @@ -1,442 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Linaro Ltd. - */ - -#include "ste-ab8500.dtsi" - -/ { - soc { - prcmu@80157000 { - ab8500 { - gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_default_mode>, - <&gpio4_default_mode>, - <&gpio10_default_mode>, - <&gpio11_default_mode>, - <&gpio12_default_mode>, - <&gpio13_default_mode>, - <&gpio16_default_mode>, - <&gpio24_default_mode>, - <&gpio25_default_mode>, - <&gpio36_default_mode>, - <&gpio37_default_mode>, - <&gpio38_default_mode>, - <&gpio39_default_mode>, - <&gpio42_default_mode>, - <&gpio26_default_mode>, - <&gpio35_default_mode>, - <&ycbcr_default_mode>, - <&pwm_default_mode>, - <&adi1_default_mode>, - <&usbuicc_default_mode>, - <&dmic_default_mode>, - <&extcpena_default_mode>, - <&modsclsda_default_mode>; - - /* - * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 - * are muxed in as GPIO, and configured as INPUT PULL DOWN - */ - gpio2 { - gpio2_default_mode: gpio2_default { - default_mux { - function = "gpio"; - groups = "gpio2_a_1"; - }; - default_cfg { - pins = "GPIO2_T9"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio4 { - gpio4_default_mode: gpio4_default { - default_mux { - function = "gpio"; - groups = "gpio4_a_1"; - }; - default_cfg { - pins = "GPIO4_W2"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio10 { - gpio10_default_mode: gpio10_default { - default_mux { - function = "gpio"; - groups = "gpio10_d_1"; - }; - default_cfg { - pins = "GPIO10_U17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio11 { - gpio11_default_mode: gpio11_default { - default_mux { - function = "gpio"; - groups = "gpio11_d_1"; - }; - default_cfg { - pins = "GPIO11_AA18"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio12 { - gpio12_default_mode: gpio12_default { - default_mux { - function = "gpio"; - groups = "gpio12_d_1"; - }; - default_cfg { - pins = "GPIO12_U16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio13 { - gpio13_default_mode: gpio13_default { - default_mux { - function = "gpio"; - groups = "gpio13_d_1"; - }; - default_cfg { - pins = "GPIO13_W17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio16 { - gpio16_default_mode: gpio16_default { - default_mux { - function = "gpio"; - groups = "gpio16_a_1"; - }; - default_cfg { - pins = "GPIO16_F15"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio24 { - gpio24_default_mode: gpio24_default { - default_mux { - function = "gpio"; - groups = "gpio24_a_1"; - }; - default_cfg { - pins = "GPIO24_T14"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio25 { - gpio25_default_mode: gpio25_default { - default_mux { - function = "gpio"; - groups = "gpio25_a_1"; - }; - default_cfg { - pins = "GPIO25_R16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio36 { - gpio36_default_mode: gpio36_default { - default_mux { - function = "gpio"; - groups = "gpio36_a_1"; - }; - default_cfg { - pins = "GPIO36_A17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio37 { - gpio37_default_mode: gpio37_default { - default_mux { - function = "gpio"; - groups = "gpio37_a_1"; - }; - default_cfg { - pins = "GPIO37_E15"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio38 { - gpio38_default_mode: gpio38_default { - default_mux { - function = "gpio"; - groups = "gpio38_a_1"; - }; - default_cfg { - pins = "GPIO38_C17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio39 { - gpio39_default_mode: gpio39_default { - default_mux { - function = "gpio"; - groups = "gpio39_a_1"; - }; - default_cfg { - pins = "GPIO39_E16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio42 { - gpio42_default_mode: gpio42_default { - default_mux { - function = "gpio"; - groups = "gpio42_a_1"; - }; - default_cfg { - pins = "GPIO42_U2"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW - */ - gpio26 { - gpio26_default_mode: gpio26_default { - default_mux { - function = "gpio"; - groups = "gpio26_d_1"; - }; - default_cfg { - pins = "GPIO26_M16"; - output-low; - }; - }; - }; - gpio35 { - gpio35_default_mode: gpio35_default { - default_mux { - function = "gpio"; - groups = "gpio35_d_1"; - }; - default_cfg { - pins = "GPIO35_W15"; - output-low; - }; - }; - }; - /* - * This sets up the YCBCR connector pins, i.e. analog video out. - * Set as input with no bias. - */ - ycbcr { - ycbcr_default_mode: ycbcr_default { - default_mux { - function = "ycbcr"; - groups = "ycbcr0123_d_1"; - }; - default_cfg { - pins = "GPIO6_Y18", - "GPIO7_AA20", - "GPIO8_W18", - "GPIO9_AA19"; - input-enable; - bias-disable; - }; - }; - }; - /* This sets up the PWM pins 14 and 15 */ - pwm { - pwm_default_mode: pwm_default { - default_mux { - function = "pwmout"; - groups = "pwmout1_d_1", "pwmout2_d_1"; - }; - default_cfg { - pins = "GPIO14_F14", - "GPIO15_B17"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up audio interface 1 */ - adi1 { - adi1_default_mode: adi1_default { - default_mux { - function = "adi1"; - groups = "adi1_d_1"; - }; - default_cfg { - pins = "GPIO17_P5", - "GPIO18_R5", - "GPIO19_U5", - "GPIO20_T5"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up the USB UICC pins */ - usbuicc { - usbuicc_default_mode: usbuicc_default { - default_mux { - function = "usbuicc"; - groups = "usbuicc_d_1"; - }; - default_cfg { - pins = "GPIO21_H19", - "GPIO22_G20", - "GPIO23_G19"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up the microphone pins */ - dmic { - dmic_default_mode: dmic_default { - default_mux { - function = "dmic"; - groups = "dmic12_d_1", - "dmic34_d_1", - "dmic56_d_1"; - }; - default_cfg { - pins = "GPIO27_J6", - "GPIO28_K6", - "GPIO29_G6", - "GPIO30_H6", - "GPIO31_F5", - "GPIO32_G5"; - input-enable; - bias-pull-down; - }; - }; - }; - extcpena { - extcpena_default_mode: extcpena_default { - default_mux { - function = "extcpena"; - groups = "extcpena_d_1"; - }; - default_cfg { - pins = "GPIO34_R17"; - input-enable; - bias-pull-down; - }; - }; - }; - /* Modem I2C setup (SCL and SDA pins) */ - modsclsda { - modsclsda_default_mode: modsclsda_default { - default_mux { - function = "modsclsda"; - groups = "modsclsda_d_1"; - }; - default_cfg { - pins = "GPIO40_T19", - "GPIO41_U19"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Clock output pins associated with regulators. - */ - sysclkreq2 { - sysclkreq2_default_mode: sysclkreq2_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq2_d_1"; - }; - default_cfg { - pins = "GPIO1_T10"; - input-enable; - bias-disable; - }; - }; - sysclkreq2_sleep_mode: sysclkreq2_sleep { - default_mux { - function = "gpio"; - groups = "gpio1_a_1"; - }; - default_cfg { - pins = "GPIO1_T10"; - input-enable; - bias-pull-down; - }; - }; - }; - sysclkreq4 { - sysclkreq4_default_mode: sysclkreq4_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq4_d_1"; - }; - default_cfg { - pins = "GPIO3_U9"; - input-enable; - bias-disable; - }; - }; - sysclkreq4_sleep_mode: sysclkreq4_sleep { - default_mux { - function = "gpio"; - groups = "gpio3_a_1"; - }; - default_cfg { - pins = "GPIO3_U9"; - input-enable; - bias-pull-down; - }; - }; - }; - }; - /* - * Charging is not working on the HREF unless an actual battery is - * mounted, most HREFs have a DC cable in to the "battery power" - * which means this will only be cofusing. So do not enable charging - * of the HREFs. - */ - ab8500_fg { - status = "disabled"; - }; - ab8500_btemp { - status = "disabled"; - }; - ab8500_charger { - status = "disabled"; - }; - ab8500_chargalg { - status = "disabled"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi deleted file mode 100644 index 434fa6baf71f..000000000000 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Linaro Ltd. - */ - -#include "ste-dbx5x0-pinctrl.dtsi" - -/ { - soc { - pinctrl { - /* Settings for all SPI default and sleep states */ - spi2 { - spi2_default_mode: spi_default { - default_mux { - function = "spi2"; - groups = "spi2_oc1_2"; - }; - default_cfg1 { - pins = "GPIO216_AG12"; /* FRM */ - ste,config = <&gpio_out_hi>; - }; - default_cfg2 { - pins = "GPIO218_AH11"; /* RXD */ - ste,config = <&in_pd>; - }; - default_cfg3 { - pins = - "GPIO215_AH13", /* TXD */ - "GPIO217_AH12"; /* CLK */ - ste,config = <&out_lo>; - }; - }; - - spi2_idle_mode: spi_idle { - /* - * The idle mode is basically sleep mode sans wakeups. Also - * note that we have muxes the pins off the function here - * as we do not state any muxing. - */ - idle_cfg1 { - pins = "GPIO218_AH11"; /* RXD */ - ste,config = <&slpm_in_pdis>; - }; - idle_cfg2 { - pins = "GPIO215_AH13"; /* TXD */ - ste,config = <&slpm_out_lo_pdis>; - }; - idle_cfg3 { - pins = "GPIO217_AH12"; /* CLK */ - ste,config = <&slpm_pdis>; - }; - }; - - spi2_sleep_mode: spi_sleep { - sleep_cfg1 { - pins = - "GPIO216_AG12", /* FRM */ - "GPIO218_AH11"; /* RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO215_AH13"; /* TXD */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO217_AH12"; /* CLK */ - ste,config = <&slpm_wkup_pdis>; - }; - }; - }; - - mcde { - lcd_default_mode: lcd_default { - default_mux1 { - /* Mux in VSI0 and all the data lines */ - function = "lcd"; - groups = - "lcdvsi0_a_1", /* VSI0 for LCD */ - "lcd_d0_d7_a_1", /* Data lines */ - "lcdvsi1_a_1"; /* VSI1 for HDMI */ - }; - default_mux2 { - function = "lcda"; - groups = - "lcdaclk_b_1"; /* Clock line for TV-out */ - }; - default_cfg1 { - pins = - "GPIO68_E1", /* VSI0 */ - "GPIO69_E2"; /* VSI1 */ - ste,config = <&in_pu>; - }; - }; - lcd_sleep_mode: lcd_sleep { - sleep_cfg1 { - pins = "GPIO69_E2"; /* VSI1 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - ske { - /* SKE keys on position 2 in an 8x8 matrix */ - ske_kpa2_default_mode: ske_kpa2_default { - default_mux { - function = "kp"; - groups = "kp_a_2"; - }; - default_cfg1 { - pins = - "GPIO153_B17", /* I7 */ - "GPIO154_C16", /* I6 */ - "GPIO155_C19", /* I5 */ - "GPIO156_C17", /* I4 */ - "GPIO161_D21", /* I3 */ - "GPIO162_D20", /* I2 */ - "GPIO163_C20", /* I1 */ - "GPIO164_B21"; /* I0 */ - ste,config = <&in_pd>; - }; - default_cfg2 { - pins = - "GPIO157_A18", /* O7 */ - "GPIO158_C18", /* O6 */ - "GPIO159_B19", /* O5 */ - "GPIO160_B20", /* O4 */ - "GPIO165_C21", /* O3 */ - "GPIO166_A22", /* O2 */ - "GPIO167_B24", /* O1 */ - "GPIO168_C22"; /* O0 */ - ste,config = <&out_lo>; - }; - }; - ske_kpa2_sleep_mode: ske_kpa2_sleep { - sleep_cfg1 { - pins = - "GPIO153_B17", /* I7 */ - "GPIO154_C16", /* I6 */ - "GPIO155_C19", /* I5 */ - "GPIO156_C17", /* I4 */ - "GPIO161_D21", /* I3 */ - "GPIO162_D20", /* I2 */ - "GPIO163_C20", /* I1 */ - "GPIO164_B21"; /* I0 */ - ste,config = <&slpm_in_pu_wkup_pdis_en>; - }; - sleep_cfg2 { - pins = - "GPIO157_A18", /* O7 */ - "GPIO158_C18", /* O6 */ - "GPIO159_B19", /* O5 */ - "GPIO160_B20", /* O4 */ - "GPIO165_C21", /* O3 */ - "GPIO166_A22", /* O2 */ - "GPIO167_B24", /* O1 */ - "GPIO168_C22"; /* O0 */ - ste,config = <&slpm_out_lo_pdis>; - }; - }; - /* - * SKE keys on position 1 and "other C1" combi giving - * six rows of six keys. - */ - ske_kpaoc1_default_mode: ske_kpaoc1_default { - default_mux { - function = "kp"; - groups = "kp_a_1", "kp_oc1_1"; - }; - default_cfg1 { - pins = - "GPIO91_B6", /* KP_O0 */ - "GPIO90_A3", /* KP_O1 */ - "GPIO87_B3", /* KP_O2 */ - "GPIO86_C6", /* KP_O3 */ - "GPIO96_D8", /* KP_O6 */ - "GPIO94_D7"; /* KP_O7 */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO93_B7", /* KP_I0 */ - "GPIO92_D6", /* KP_I1 */ - "GPIO89_E6", /* KP_I2 */ - "GPIO88_C4", /* KP_I3 */ - "GPIO97_D9", /* KP_I6 */ - "GPIO95_E8"; /* KP_I7 */ - ste,config = <&in_pu>; - }; - }; - }; - - wlan { - wlan_default_mode: wlan_default { - /* - * Activate this mode with the WLAN chip. - * These are plain GPIO pins used by WLAN - */ - default_cfg1 { - pins = - "GPIO226_AF8", /* WLAN_PMU_EN */ - "GPIO85_D5"; /* WLAN_ENA */ - ste,config = <&gpio_out_lo>; - }; - default_cfg2 { - pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi deleted file mode 100644 index 79c2be36acae..000000000000 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; - - button@139 { - /* Proximity sensor */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - linux,code = <11>; /* SW_FRONT_PROXIMITY */ - label = "SFH7741 Proximity Sensor"; - }; - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - stmpe1601: port-expander@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio6>; - vcc-supply = <&db8500_vsmps2_reg>; - vio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe_stuib_mode>; - - wakeup-source; - st,autosleep-timeout = <1024>; - - keyboard-controller { - compatible = "st,stmpe-keypad"; - - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - - linux,keymap = <0x205006b - 0x4010074 - 0x3050072 - 0x1030004 - 0x502006a - 0x500000a - 0x5008b - 0x706001c - 0x405000b - 0x6070003 - 0x3040067 - 0x303006c - 0x60400e7 - 0x602009e - 0x4020073 - 0x5050002 - 0x4030069 - 0x3020008>; - }; - }; - }; - - /* Sensors mounted on this board variant */ - i2c@80128000 { - lis331dl@1c { - /* Accelerometer */ - compatible = "st,lis331dl-accel"; - st,drdy-int-pin = <1>; - reg = <0x1c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_stuib_mode>; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - }; - ak8974@f { - /* Magnetometer */ - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_stuib_mode>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c@80110000 { - bu21013_tp@5c { - compatible = "rohm,bu21013_tp"; - reg = <0x5c>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - pinctrl-names = "default"; - pinctrl-0 = <&touch_rohm_mode>; - }; - - bu21013_tp@5d { - compatible = "rohm,bu21013_tp"; - reg = <0x5d>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - pinctrl-names = "default"; - pinctrl-0 = <&touch_rohm_mode>; - }; - }; - - pinctrl { - /* Pull up this GPIO pin */ - stmpe { - stmpe_stuib_mode: stmpe_stuib { - stuib_cfg { - ste,pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - prox { - prox_stuib_mode: prox_stuib { - stuib_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - hall { - hall_stuib_mode: stuib_tvk { - stuib_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_stuib_mode: accel_stuib { - /* Accelerometer interrupt lines 1 & 2 */ - stuib_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_stuib_mode: magneto_stuib { - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - stuib_cfg1 { - pins = "GPIO31_V3"; - ste,config = <&gpio_in_pu>; - }; - stuib_cfg2 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - touch { - touch_rohm_mode: touch_rohm { - /* - * ROHM touch screen uses GPIO 143 for - * RST1, GPIO 146 for RST2 and - * GPIO 67 for interrupts. Pull-up - * the IRQ line and drive both - * reset signals low. - */ - stuib_cfg1 { - pins = "GPIO143_D12", "GPIO146_D13"; - ste,config = <&gpio_out_lo>; - }; - stuib_cfg2 { - pins = "GPIO67_G2"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - - mcde@a0350000 { - status = "okay"; - - dsi@a0351000 { - panel { - compatible = "samsung,s6d16d0"; - reg = <0>; - vdd1-supply = <&ab8500_ldo_aux1_reg>; - reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi deleted file mode 100644 index 37e59403c01f..000000000000 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for the TVK1281618 R2 user interface board (UIB) - */ - -#include -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; - - button@139 { - /* Proximity sensor */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - linux,code = <11>; /* SW_FRONT_PROXIMITY */ - label = "SFH7741 Proximity Sensor"; - }; - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - tc35893@44 { - compatible = "toshiba,tc35893"; - reg = <0x44>; - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35893_tvk_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - status = "disabled"; - - tc3589x_gpio { - compatible = "toshiba,tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - tc3589x_keypad { - compatible = "toshiba,tc3589x-keypad"; - interrupts = <6>; - debounce-delay-ms = <4>; - keypad,num-columns = <8>; - keypad,num-rows = <8>; - linux,no-autorepeat; - wakeup-source; - linux,keymap = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - }; - - i2c@80128000 { - accelerometer@18 { - /* Accelerometer */ - compatible = "st,lsm303dlh-accel"; - st,drdy-int-pin = <1>; - drive-open-drain; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; - */ - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; - }; - magnetometer@1e { - /* Magnetometer */ - compatible = "st,lsm303dlh-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; - */ - }; - accelerometer@1c { - /* Accelerometer */ - compatible = "st,lis331dl-accel"; - st,drdy-int-pin = <1>; - reg = <0x1c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - interrupt-parent = <&gpio2>; - /* INT2 would need to be open drain */ - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; - }; - magnetometer@f { - /* Magnetometer */ - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - dvdd-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_magn_tvk_mode>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>; - */ - }; - gyroscope@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_magn_tvk_mode>; - interrupts-extended = - <&gpio1 0 IRQ_TYPE_EDGE_RISING>, - <&gpio0 31 IRQ_TYPE_EDGE_RISING>; - }; - pressure@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - i2c@80110000 { - synaptics@4b { - /* Synaptics RMI4 TM1217 touchscreen */ - compatible = "syna,rmi4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4b>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&synaptics_tvk_mode>; - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - rmi4-f11@11 { - reg = <0x11>; - syna,sensor-type = <1>; - /* This is a landscape display */ - touchscreen-swapped-x-y; - }; - }; - }; - mcde@a0350000 { - status = "okay"; - - dsi@a0351000 { - panel { - compatible = "samsung,s6d16d0"; - reg = <0>; - vdd1-supply = <&ab8500_ldo_aux1_reg>; - reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - }; - pinctrl { - prox { - prox_tvk_mode: prox_tvk { - tvk_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - hall { - hall_tvk_mode: hall_tvk { - tvk_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - tc35893 { - /* IRQ from the TC35893 */ - tc35893_tvk_mode: tc35893_tvk { - tvk_cfg { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_tvk_mode: accel_tvk { - /* Accelerometer interrupt lines 1 & 2 */ - tvk_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - gyroscope { - /* - * These lines are shared between Gyroscope l3g400dh - * and AK8974 magnetometer. - */ - gyro_magn_tvk_mode: gyro_magn_tvk { - /* GPIO 31 used for INT pull down the line */ - tvk_cfg1 { - pins = "GPIO31_V3"; - ste,config = <&gpio_in_pd>; - }; - /* GPIO 32 used for DRDY, pull this down */ - tvk_cfg2 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - synaptics { - synaptics_tvk_mode: synaptics_tvk { - /* Touchscreen uses GPIO 84 */ - tvk_cfg1 { - pins = "GPIO84_C2"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi deleted file mode 100644 index 00ce9d79f540..000000000000 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for the TVK1281618 R3 user interface board (UIB) - * also known as the "CYTTSP board" - */ - -#include -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&hall_tvk_mode>; - - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - tc35893@44 { - compatible = "toshiba,tc35893"; - reg = <0x44>; - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35893_tvk_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - status = "disabled"; - - tc3589x_gpio { - compatible = "toshiba,tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - tc3589x_keypad { - compatible = "toshiba,tc3589x-keypad"; - interrupts = <6>; - debounce-delay-ms = <4>; - keypad,num-columns = <8>; - keypad,num-rows = <8>; - linux,no-autorepeat; - wakeup-source; - linux,keymap = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - }; - - i2c@80128000 { - accelerometer@19 { - compatible = "st,lsm303dlhc-accel"; - st,drdy-int-pin = <1>; - reg = <0x19>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; - }; - magnetometer@1e { - compatible = "st,lsm303dlm-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - // This interrupt is not properly working with the driver - // interrupt-parent = <&gpio1>; - // interrupts = <0 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&magn_tvk_mode>; - }; - gyroscope@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - pressure@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - - spi@80111000 { - num-cs = <1>; - cs-gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_default_mode>; - status = "okay"; - - touchscreen@0 { - compatible = "cypress,cy8ctma340"; - /* - * Actually the max frequency is 6 MHz, but over 2 MHz the - * data rate needs to be restricted to max 2Mbps which the - * SPI framework cannot handle. - */ - spi-max-frequency = <2000000>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - vcpin-supply = <&ab8500_ldo_aux1_reg>; - vdd-supply = <&db8500_vsmps2_reg>; - reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <480>; - touchscreen-size-y = <854>; - active-interval-ms = <0>; - touch-timeout-ms = <255>; - lowpower-interval-ms = <10>; - bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; - pinctrl-names = "default"; - pinctrl-0 = <&cyttsp_tvk_mode>; - }; - }; - - mcde@a0350000 { - status = "okay"; - - dsi@a0351000 { - panel { - compatible = "sony,acx424akp"; - reg = <0>; - vddi-supply = <&ab8500_ldo_aux1_reg>; - reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - }; - - pinctrl { - hall { - hall_tvk_mode: hall_tvk { - tvk_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - tc35893 { - /* IRQ from the TC35893 */ - tc35893_tvk_mode: tc35893_tvk { - tvk_cfg { - pins = "GPIO64_F3"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_tvk_mode: accel_tvk { - /* Accelerometer interrupt lines 1 & 2 */ - tvk_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - magnetometer { - magn_tvk_mode: magn_tvk { - /* GPIO 32 used for DRDY, pull this down */ - tvk_cfg { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - cyttsp { - cyttsp_tvk_mode: cyttsp_tvk { - /* Touchscreen uses GPIO84 for IRQ */ - tvk_cfg1 { - pins = "GPIO84_C2"; - ste,config = <&gpio_in_pu>; - }; - /* GPIO143 is reset */ - tvk_cfg2 { - pins = "GPIO143_D12"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi deleted file mode 100644 index 13b11dbeba1c..000000000000 --- a/arch/arm/boot/dts/ste-href.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -#include -#include -#include "ste-href-family-pinctrl.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - battery: battery { - compatible = "simple-battery"; - battery-type = "lithium-ion-polymer"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "murata,ncp18wb473"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - soc { - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - }; - - /* This UART is unused and thus left disabled */ - serial@80121000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - }; - - serial@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - status = "okay"; - }; - - i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - status = "okay"; - }; - - i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_b_2_default>; - pinctrl-1 = <&i2c1_b_2_sleep>; - status = "okay"; - }; - - i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - status = "okay"; - lp5521@33 { - compatible = "national,lp5521"; - reg = <0x33>; - label = "lp5521_pri"; - clock-mode = /bits/ 8 <2>; - #address-cells = <1>; - #size-cells = <0>; - led@0 { - reg = <0>; - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - color = ; - linux,default-trigger = "heartbeat"; - }; - led@1 { - reg = <1>; - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - color = ; - }; - led@2 { - reg = <2>; - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - color = ; - }; - }; - lp5521@34 { - compatible = "national,lp5521"; - reg = <0x34>; - label = "lp5521_sec"; - clock-mode = /bits/ 8 <2>; - #address-cells = <1>; - #size-cells = <0>; - led@0 { - reg = <0>; - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - color = ; - }; - led@1 { - reg = <1>; - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - color = ; - }; - led@2 { - reg = <2>; - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - color = ; - }; - }; - bh1780@29 { - compatible = "rohm,bh1780gli"; - reg = <0x29>; - }; - }; - - i2c@80110000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - status = "okay"; - }; - - // External Micro SD slot - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - full-pwr-cycle; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-cmd; - st,sig-pin-fbclk; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; - pinctrl-1 = <&mc0_a_1_sleep>; - - status = "okay"; - }; - - // WLAN SDIO channel - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - non-removable; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_1_default>; - pinctrl-1 = <&mc1_a_1_sleep>; - - status = "okay"; - }; - - // PoP:ed eMMC - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - no-sdio; - no-sd; - vmmc-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - - status = "okay"; - }; - - // On-board eMMC - mmc@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - no-sdio; - no-sd; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc4_a_1_default>; - pinctrl-1 = <&mc4_a_1_sleep>; - - status = "okay"; - }; - - msp0: msp@80123000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp0txrxtfstck_a_1_default>; - status = "okay"; - }; - - msp1: msp@80124000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp1txrx_a_1_default>; - status = "okay"; - }; - - msp2: msp@80117000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp2_a_1_default>; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - prcmu@80157000 { - ab8500 { - gpio { - }; - - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - regulator { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - pinctrl { - sdi0 { - sdi0_default_mode: sdi0_default { - /* Some boards set additional settings here */ - }; - }; - }; - - mcde@a0350000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_default_mode>; - pinctrl-1 = <&lcd_sleep_mode>; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href520-tvk.dts b/arch/arm/boot/dts/ste-href520-tvk.dts deleted file mode 100644 index 4201547c5988..000000000000 --- a/arch/arm/boot/dts/ste-href520-tvk.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for the HREF520 version with the TVK1281618 R3 UIB - */ - -/dts-v1/; -#include "ste-db8520.dtsi" -#include "ste-hrefv60plus.dtsi" -#include "ste-href-tvk1281618-r3.dtsi" - -/ { - model = "ST-Ericsson HREF520 and TVK1281618 R3 UIB"; - compatible = "st-ericsson,href520", "st-ericsson,u8500"; - - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&vmmci_default_mode>; - }; -}; - -&pinctrl { - vmmci { - vmmci_default_mode: vmmc_default { - /* VMMCI level-shifter enable */ - default_href520_cfg1 { - pins = "GPIO78_F4"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - default_href520_cfg2 { - pins = "GPIO5_AG6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts deleted file mode 100644 index dfc933214c1a..000000000000 --- a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefprev60.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and ST UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - - gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; - }; - bu21013_tp@5d { - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts deleted file mode 100644 index 75506339a93c..000000000000 --- a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefprev60.dtsi" -#include "ste-href-tvk1281618-r2.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and TVK1281618 R2 UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - - gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi deleted file mode 100644 index 9859ee91a15e..000000000000 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the HREF+ prior to the v60 variant. - */ - -#include "ste-href-ab8500.dtsi" -#include "ste-href.dtsi" - -/ { - gpio_keys { - button@1 { - gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; - }; - }; - - soc { - /* Enable UART1 on this board */ - serial@80121000 { - status = "okay"; - }; - - i2c@80004000 { - tps61052@33 { - compatible = "ti,tps61052"; - reg = <0x33>; - }; - - tc35892@42 { - compatible = "toshiba,tc35892"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35892_hrefprev60_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - spi@80002000 { - /* - * On the first generation boards, this SSP/SPI port was connected - * to the AB8500. - */ - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_hrefprev60_mode>; - status = "okay"; - }; - - // External Micro SD slot - mmc@80126000 { - cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; - }; - - pinctrl { - /* Set this up using hogs */ - pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefprev60_mode>; - - ssp0 { - ssp0_hrefprev60_mode: ssp0_hrefprev60_default { - hrefprev60_mux { - function = "ssp0"; - groups = "ssp0_a_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO145_C13"; /* RXD */ - ste,config = <&in_pd>; - }; - - }; - }; - sdi0 { - /* This additional pin needed on early MOP500 and HREFs previous to v60 */ - sdi0_default_mode: sdi0_default { - hrefprev60_mux { - function = "mc0"; - groups = "mc0dat31dir_a_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO21_AB3"; /* DAT31DIR */ - ste,config = <&out_hi>; - }; - - }; - }; - tc35892 { - tc35892_hrefprev60_mode: tc35892_hrefprev60 { - hrefprev60_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - ipgpio { - ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { - hrefprev60_mux { - function = "ipgpio"; - groups = "ipgpio0_c_1", "ipgpio1_c_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO6_AF6", "GPIO7_AG5"; - ste,config = <&in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts deleted file mode 100644 index 52c56ed17ae6..000000000000 --- a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the HREF version 60 or later with the ST UIB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefv60plus.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and ST UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&vmmci_default_mode>; - }; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; - }; - bu21013_tp@5d { - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; - }; - }; - }; -}; - -&pinctrl { - vmmci { - vmmci_default_mode: vmmc_default { - /* VMMCI level-shifter enable */ - default_hrefv60_cfg2 { - pins = "GPIO169_D22"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - default_hrefv60_cfg3 { - pins = "GPIO5_AG6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts deleted file mode 100644 index 2db2f8be8b03..000000000000 --- a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the HREF version 60 or later with the TVK1281618 R2 UIB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefv60plus.dtsi" -#include "ste-href-tvk1281618-r2.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and TVK1281618 R2 UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&vmmci_default_mode>; - }; -}; - -&pinctrl { - vmmci { - vmmci_default_mode: vmmc_default { - /* VMMCI level-shifter enable */ - default_hrefv60_cfg2 { - pins = "GPIO169_D22"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - default_hrefv60_cfg3 { - pins = "GPIO5_AG6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi deleted file mode 100644 index e66fa59c2de6..000000000000 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ /dev/null @@ -1,377 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -#include "ste-href-ab8500.dtsi" -#include "ste-href.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) platform with Device Tree"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - thermal-zones { - chassis-thermal { - /* Poll every 20 seconds */ - polling-delay = <20000>; - /* Poll every 2nd second when cooling */ - polling-delay-passive = <2000>; - - thermal-sensors = <&therm1>, <&therm2>; - - /* Tripping points made from rough guess about operating conditions */ - trips { - chassis_alert: chassis-alert { - /* At 50 degrees take down the CPU frequency */ - temperature = <50000>; - hysteresis = <3000>; - type = "active"; - }; - chassis_crit: chassis-crit { - /* Just shut down at 70 degrees */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - /* Push down the operating frequency of the SoC when it gets hot */ - cooling-maps { - map0 { - trip = <&chassis_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <100>; - }; - }; - }; - }; - - /* - * Thermistors on the board, formally to monitor battery temperatures - * but what they measure is the board temperature. - */ - therm1: thermistor@0 { - compatible = "murata,ncp18wb473"; - io-channels = <&gpadc 0x06>; /* AUX1 */ - pullup-uv = <1800000>; - pullup-ohm = <220000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - therm2: thermistor@1 { - compatible = "murata,ncp18wb473"; - io-channels = <&gpadc 0x07>; /* AUX2 */ - pullup-uv = <1800000>; - pullup-ohm = <220000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - soc { - /* Name the GPIO muxed rails on the HREF boards */ - gpio@8012e000 { - /* GPIOs 0 - 31 */ - gpio-line-names = - /* GPIO0,1 used for UART0 BT RX/TX */ - "", "", - "UART_WAKE", - "BT_WAKE", - "", - "SDMMC_1V8_3V_SEL", - "FLASH_LED_SYNC (FLASH_CTRL_0)", - "XENON_READY (FLASH_CTRL_1)", - "", "", "", "", "", "", "", "", - "", "", "", "", - "", - "FLASH_LED_EN (FLASH_CTRL_3)", - "", "", - "", "", "", "", "", - /* Used by UART2 (console) */ - "", "", - "MAGNETOMETER_INT"; - }; - - gpio@8012e080 { - /* GPIOs 32 - 63 */ - gpio-line-names = - "MAGNETOMETER_DRDY", - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e000 { - /* GPIOs 64 - 95 */ - gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)", - "DISP1_RST", - "DISP2_RST", - "TOUCH_INT2", - "LCD_VSI0_A", - "LCD_VSI1_A", - /* GPIO 70-77 used for ETM */ - "", "", "", "", "", "", "", "", - /* GPIO 78-81 used for YCBCR */ - "", "", "", "", - "ACCELEROMETER_INT1_RDY", - "ACCELEROMETER_INT2", - "TOUCH_INT", - "WLAN_ENA", - "", "", "", "", "", - "FORCE_SENSING_INT", - "FORCE_SENSING_RESET", - "", "", - "SDMMC_CD"; - }; - - gpio@8000e080 { - /* GPIOs 96 - 127 */ - gpio-line-names = "", - "FORCE_SENSING_WU", - "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e100 { - /* GPIOs 128 - 159 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", - "DIPRO_INT", /* GPIO139 */ - "XSHUTDOWN_SECONDARY_SENSOR", - "XSHUTDOWN_PRIMARY_SENSOR", - "NFC_RST (NFC_CTRL_", - "TOUCH_RST", - "NFC_IRQ (NFC_CTRL_1)", - "HAL_SW", - "TOUCH_RST2", - "", "", - "VAUDIO_HF_EN", /* GPIO149 */ - "", "", "", "", "", "", "", "", "", ""; - }; - - gpio@8000e180 { - /* GPIOs 160 - 191 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", - "SDMMC_EN", - "XENON_CHARGE (FLASH_CONTROL_5)", - "GBF_ENA_RESET", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8011e000 { - /* GPIOs 192 - 223 */ - gpio-line-names = "HDTV_INTN", - "", "", "", - "HDTV_RSTN", - "", "", "", - "", /* GPIO200 */ - "", "", "", "", "", "", "", - /* GPIO208-216 used for WGBF_MC1 */ - "", "", "", "", "", "", "", "", "", - "SW_FRONT_PROXIMITY", /* GPIO217 */ - "KPD_CTRL_INT", /* Keypad controller */ - "", "", "", "", ""; - }; - - gpio@8011e080 { - /* GPIOs 224 - 255 */ - gpio-line-names = "", "", - "HSIT_ACWAKE0", - "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - // External Micro SD slot - mmc@80126000 { - cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 - }; - - pinctrl { - /* - * Set this up using hogs, as time goes by and as seems fit, these - * can be moved over to being controlled by respective device. - */ - pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefv60_mode>, - <&etm_hrefv60_mode>, - <&nahj_hrefv60_mode>, - <&nfc_hrefv60_mode>, - <&force_hrefv60_mode>, - <&dipro_hrefv60_mode>, - <&vaudio_hf_hrefv60_mode>, - <&gbf_hrefv60_mode>, - <&hdtv_hrefv60_mode>, - <&gpios_hrefv60_mode>; - - sdi0 { - sdi0_default_mode: sdi0_default { - /* SD card detect GPIO pin, extend default state */ - default_hrefv60_cfg1 { - pins = "GPIO95_E8"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - ipgpio { - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant - * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias - * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. - */ - ipgpio_hrefv60_mode: ipgpio_hrefv60 { - hrefv60_mux { - function = "ipgpio"; - groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; - }; - hrefv60_cfg1 { - pins = "GPIO6_AF6", "GPIO7_AG5"; - ste,config = <&in_pu>; - }; - hrefv60_cfg2 { - pins = "GPIO21_AB3"; - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg3 { - pins = "GPIO64_F3"; - ste,config = <&out_lo>; - }; - }; - }; - etm { - /* - * Drive D19-D23 for the ETM PTM trace interface low, - * (presumably pins are unconnected therefore grounded here, - * the "other alt C1" setting enables these pins) - */ - etm_hrefv60_mode: etm_hrefv60 { - hrefv60_cfg1 { - pins = - "GPIO70_G5", - "GPIO71_G4", - "GPIO72_H4", - "GPIO73_H3", - "GPIO74_J3"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - nahj { - nahj_hrefv60_mode: nahj_hrefv60 { - /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ - hrefv60_cfg1 { - pins = "GPIO76_J2"; - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - nfc { - nfc_hrefv60_mode: nfc_hrefv60 { - /* NFC ENA and RESET to low, pulldown IRQ line */ - hrefv60_cfg1 { - pins = - "GPIO77_H1", /* NFC_ENA */ - "GPIO142_C11"; /* NFC_RESET */ - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg2 { - pins = "GPIO144_B13"; /* NFC_IRQ */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - force { - force_hrefv60_mode: force_hrefv60 { - hrefv60_cfg1 { - pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ - ste,config = <&gpio_in_pu>; - }; - hrefv60_cfg2 { - pins = - "GPIO92_D6", /* FORCE_SENSING_RST */ - "GPIO97_D9"; /* FORCE_SENSING_WU */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - dipro { - dipro_hrefv60_mode: dipro_hrefv60 { - hrefv60_cfg1 { - pins = "GPIO139_C9"; /* DIPRO_INT */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - vaudio_hf { - vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { - /* Audio Amplifier HF enable GPIO */ - hrefv60_cfg1 { - pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - gbf { - gbf_hrefv60_mode: gbf_hrefv60 { - /* - * GBF (GPS, Bluetooth, FM-radio) interface, - * pull low to reset state - */ - hrefv60_cfg1 { - pins = "GPIO171_D23"; /* GBF_ENA_RESET */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - hdtv { - hdtv_hrefv60_mode: hdtv_hrefv60 { - /* MSP : HDTV INTERFACE GPIO line */ - hrefv60_cfg1 { - pins = "GPIO192_AJ27"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - mcde { - lcd_hrefv60_mode: lcd_hrefv60 { - /* - * Display Interface 1 uses GPIO 65 for RST (reset). - * Display Interface 2 uses GPIO 66 for RST (reset). - * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) - */ - hrefv60_cfg1 { - pins = "GPIO65_F1"; - ste,config = <&gpio_out_hi>; - }; - hrefv60_cfg2 { - pins = "GPIO66_G3"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - gpios { - /* Dangling GPIO pins */ - gpios_hrefv60_mode: gpios_hrefv60 { - default_cfg1 { - /* Normally UART1 RXD, now dangling */ - pins = "GPIO4_AH6"; - ste,config = <&in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts deleted file mode 100644 index cdff33063d6f..000000000000 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST Microelectronics Nomadik NHK8815 board - */ - -/dts-v1/; -#include -#include -#include "ste-nomadik-stn8815.dtsi" - -/ { - model = "Nomadik STN8815NHK"; - compatible = "st,nomadik-nhk-15"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - stmpe-i2c0 = &stmpe0; - stmpe-i2c1 = &stmpe1; - }; - - pinctrl { - uart0 { - uart0_nhk_mode: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0txrx_a_1", "u0ctsrts_a_1"; - }; - }; - }; - - stmpe2401_1 { - stmpe2401_1_nhk_mode: stmpe2401_1_nhk { - nhk_cfg1 { - pins = "GPIO76_B20"; // IRQ line - ste,input = <0>; - }; - nhk_cfg2 { - pins = "GPIO77_B8"; // reset line - ste,output = <1>; - }; - }; - }; - stmpe2401_2 { - stmpe2401_2_nhk_mode: stmpe2401_2_nhk { - nhk_cfg1 { - pins = "GPIO78_A8"; // IRQ line - ste,input = <0>; - }; - nhk_cfg2 { - pins = "GPIO79_C9"; // reset line - ste,output = <1>; - }; - }; - }; - lis3lv02dl { - lis3lv02dl_nhk_mode: lis3lv02dl_nhk { - nhk_cfg1 { - pins = "GPIO82_C10"; // IRQ line - ste,input = <0>; - }; - }; - }; - }; - src@101e0000 { - /* These chrystal outputs are not used on this board */ - disable-sxtalo; - disable-mxtalo; - }; - - /* This is where the interrupt is routed on the NHK-15 debug board */ - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - reg-io-width = <2>; - reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&stmpe_gpio44>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c0 { - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 - pinctrl-0 = <&lis3lv02dl_nhk_mode>; - pinctrl-names = "default"; - reg = <0x1d>; - }; - stmpe0: port-expander@43 { - compatible = "st,stmpe2401"; - reg = <0x43>; - reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 - interrupt-parent = <&gpio2>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe2401_1_nhk_mode>; - stmpe_gpio43: gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - /* Some pins in alternate functions */ - st,norequest-mask = <0xf0f002>; - }; - keyboard-controller { - compatible = "st,stmpe-keypad"; - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x00020072 // Vol down - 0x00030073 // Vol up - 0x0100009e // Back - 0x010100e3 // TV out - 0x01020098 // Lock - 0x0103013b // Start - 0x020000a3 // Next - 0x020100a4 // Play - 0x020200a5 // Prev - 0x02030160 // OK - 0x03000069 // Left - 0x0301006a // Right - 0x03020067 // Up - 0x0303006c>; // Down - }; - stmpe0_pwm: pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; - }; - }; - stmpe1: port-expander@44 { - compatible = "st,stmpe2401"; - reg = <0x44>; - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 - interrupt-parent = <&gpio2>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe2401_2_nhk_mode>; - stmpe_gpio44: gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - /* - * This will turn off SATA so that MMC/SD - * can thrive - */ - mmcsd-hog { - gpio-hog; - gpios = <2 0x0>; - output-low; - line-name = "SATA EN"; - }; - }; - }; - }; - - amba { - clcd@10120000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&clcd_24bit_mux>; - port { - nomadik_clcd: endpoint { - remote-endpoint = <&nomadik_clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <16 8 0>; - }; - }; - - }; - - /* Activate RX/TX and CTS/RTS on UART 0 */ - uart0: serial@101fd000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_nhk_mode>; - status = "okay"; - }; - mmcsd: mmc@101f6000 { - cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * As we're dealing with 3wire SPI, we only define SCK - * and MOSI (in the spec MOSI is called "SDA"). - */ - sck-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - /* - * WVGA connector 21 - * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB - * with TPO touch screen. - */ - panel: display@0 { - /* - * The TPO display driver is connected to a - * 5.7" OSD OSD057VA01CT TFT display. - */ - compatible = "tpo,tpg110"; - reg = <0>; - spi-3wire; - /* 320 ns min period ~= 3 MHz */ - spi-max-frequency = <3000000>; - /* Width and height from the OSD data sheet */ - width-mm = <116>; - height-mm = <87>; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - backlight = <&bl>; - - port { - nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd>; - }; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pwms = <&stmpe0_pwm 0 500000>; - pwm-names = "backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; -}; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi deleted file mode 100644 index bfdb5d9a014f..000000000000 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson - */ -#include - -/ { - in_nopull: in_nopull { - ste,input = ; - }; - - in_pu: input_pull_up { - ste,input = ; - }; - - in_pd: input_pull_down { - ste,input = ; - }; - - out_hi: output_high { - ste,output = ; - }; - - out_lo: output_low { - ste,output = ; - }; - - gpio_in_nopull: gpio_input_nopull { - ste,gpio = ; - ste,input = ; - }; - - gpio_in_pu: gpio_input_pull_up { - ste,gpio = ; - ste,input = ; - }; - - gpio_in_pd: gpio_input_pull_down { - ste,gpio = ; - ste,input = ; - }; - - gpio_out_lo: gpio_output_low { - ste,gpio = ; - ste,output = ; - }; - - gpio_out_hi: gpio_output_high { - ste,gpio = ; - ste,output = ; - }; - - slpm_pdis: slpm_pdis { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_wkup_pdis: slpm_wkup_pdis { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_wkup_pdis_en: slpm_wkup_pdis_en { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_pu: slpm_in_pu { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - }; - - slpm_in_pdis: slpm_in_pdis { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_wkup_pdis: slpm_in_wkup_pdis { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo: slpm_out_lo { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - }; - - slpm_out_hi: slpm_out_hi { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - }; - - slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo_pdis: slpm_out_lo_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_wkup_pdis: slpm_out_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - in_wkup_pdis: in_wkup_pdis { - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - in_wkup_pdis_en: in_wkup_pdis_en { - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_lo_wkup_pdis: out_lo_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_hi_wkup_pdis: out_hi_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_wkup_pdis: out_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; -}; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts deleted file mode 100644 index c905c2643a12..000000000000 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST-Ericsson Nomadik S8815 board - * Produced by Calao Systems - */ - -/dts-v1/; -#include -#include "ste-nomadik-stn8815.dtsi" - -/ { - model = "Calao Systems USB-S8815"; - compatible = "calaosystems,usb-s8815"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - gpio3: gpio@101e7000 { - /* This hog will bias the MMC/SD card detect line */ - mmcsd-gpio { - gpio-hog; - gpios = <16 0x0>; - output-low; - line-name = "card detect bias"; - }; - }; - - src@101e0000 { - /* These chrystal drivers are not used on this board */ - disable-sxtalo; - disable-mxtalo; - }; - - pinctrl { - /* Hog CD pins */ - pinctrl-names = "default"; - pinctrl-0 = <&cd_default_mode>; - - uart0 { - /* Only use RX/TX pins */ - uart0_s8815_mode: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0txrx_a_1"; - }; - }; - }; - mmcsd-cd { - cd_default_mode: cd_default { - cd_default_cfg1 { - /* CD input GPIO */ - pins = "GPIO111_H21"; - ste,input = <0>; - }; - cd_default_cfg2 { - /* CD GPIO biasing */ - pins = "GPIO112_J21"; - ste,output = <0>; - }; - }; - }; - gpioi2c { - gpioi2c_default_mode: gpioi2c_default { - gpioi2c_default_cfg { - pins = "GPIO73_C21", "GPIO74_C20"; - ste,input = <0>; - }; - }; - }; - user-led { - user_led_default_mode: user_led_default { - user_led_default_cfg { - pins = "GPIO2_C5"; - ste,output = <1>; - }; - }; - }; - user-button { - user_button_default_mode: user_button_default { - user_button_default_cfg { - pins = "GPIO3_A4"; - ste,input = <0>; - }; - }; - }; - }; - - /* Ethernet */ - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c1 { - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - reg = <0x1d>; - }; - }; - - /* GPIO I2C connected to the USB portions of the STw4811 only */ - gpio-i2c { - compatible = "i2c-gpio"; - gpios = <&gpio2 10 0>, /* sda */ - <&gpio2 9 0>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&gpioi2c_default_mode>; - - stw4811@2d { - compatible = "st,stw4811-usb"; - reg = <0x2d>; - }; - }; - - - amba { - /* Activate RXTX on UART 0 */ - uart0: serial@101fd000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_s8815_mode>; - status = "okay"; - }; - /* Configure card detect for the uSD slot */ - mmc@101f6000 { - cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - }; - - /* The user LED on the board is set up to be used for heartbeat */ - leds { - compatible = "gpio-leds"; - user-led { - label = "user_led"; - gpios = <&gpio0 2 0x1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_default_mode>; - }; - }; - - /* User key mapped in as "escape" */ - gpio-keys { - compatible = "gpio-keys"; - user-button { - label = "user_button"; - gpios = <&gpio0 3 0x1>; - linux,code = <1>; /* KEY_ESC */ - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&user_button_default_mode>; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi deleted file mode 100644 index 6816eef39d45..000000000000 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ /dev/null @@ -1,884 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>, - <0x08000000 0x04000000>; - }; - - L2: cache-controller { - compatible = "arm,l210-cache"; - reg = <0x10210000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <30>; - cache-unified; - cache-level = <2>; - cache-size = <131072>; - cache-sets = <512>; - cache-line-size = <32>; - /* At full speed latency must be >=2 */ - arm,tag-latency = <8>; - arm,data-latency = <8 8>; - arm,dirty-latency = <8>; - }; - - mtu0: mtu@101e2000 { - /* Nomadik system timer */ - compatible = "st,nomadik-mtu"; - reg = <0x101e2000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <4>; - clocks = <&timclk>, <&pclk>; - clock-names = "timclk", "apb_pclk"; - }; - - mtu1: mtu@101e3000 { - /* Secondary timer */ - reg = <0x101e3000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <5>; - clocks = <&timclk>, <&pclk>; - clock-names = "timclk", "apb_pclk"; - }; - - gpio0: gpio@101e4000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e4000 0x80>; - interrupt-parent = <&vica>; - interrupts = <6>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - clocks = <&pclk>; - }; - - gpio1: gpio@101e5000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e5000 0x80>; - interrupt-parent = <&vica>; - interrupts = <7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 32>; - clocks = <&pclk>; - }; - - gpio2: gpio@101e6000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e6000 0x80>; - interrupt-parent = <&vica>; - interrupts = <8>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - clocks = <&pclk>; - }; - - gpio3: gpio@101e7000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e7000 0x80>; - ngpio = <28>; - interrupt-parent = <&vica>; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - gpio-ranges = <&pinctrl 0 96 28>; - clocks = <&pclk>; - }; - - pinctrl: pinctrl { - compatible = "stericsson,stn8815-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; - /* Pin configurations */ - uart1 { - uart1_default_mux: uart1_mux { - u1_default_mux { - function = "u1"; - groups = "u1_a_1"; - }; - }; - }; - mmcsd { - mmcsd_default_mux: mmcsd_mux { - mmcsd_default_mux { - function = "mmcsd"; - groups = "mmcsd_a_1", "mmcsd_b_1"; - }; - }; - mmcsd_default_mode: mmcsd_default { - mmcsd_default_cfg1 { - /* - * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 - * MCCMD, MCDAT3-0, MCMSFBCLK - */ - pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", - "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", - "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; - ste,output = <2>; - }; - }; - }; - i2c0 { - i2c0_default_mux: i2c0_mux { - i2c0_default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - }; - i2c0_default_mode: i2c0_default { - i2c0_default_cfg { - pins = "GPIO62_D3", "GPIO63_D2"; - ste,input = <0>; - }; - }; - }; - i2c1 { - i2c1_default_mux: i2c1_mux { - i2c1_default_mux { - function = "i2c1"; - groups = "i2c1_a_1"; - }; - }; - i2c1_default_mode: i2c1_default { - i2c1_default_cfg { - pins = "GPIO53_L4", "GPIO54_L3"; - ste,input = <0>; - }; - }; - }; - clcd { - /* - * This should be activated to use the additional - * 8 lines for bits 16 thru 23 from the CLCD block. - */ - clcd_24bit_mux: clcd_mux { - clcd_24bit_mux { - function = "clcd"; - groups = "clcd_16_23_b_1"; - }; - }; - }; - }; - - /* Power Management Unit */ - pmu: pmu@101e9000 { - compatible = "stericsson,nomadik-pmu", "syscon"; - reg = <0x101e0000 0x1000>; - }; - - src: src@101e0000 { - compatible = "stericsson,nomadik-src"; - reg = <0x101e0000 0x1000>; - - /* - * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz - * that is parent of TIMCLK, PLL1 and PLL2 - */ - mxtal: mxtal@19.2M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - /* - * The 2.4 MHz TIMCLK reference clock is active at - * boot time, this is actually the MXTALCLK @19.2 MHz - * divided by 8. This clock is used by the timers and - * watchdog. See page 105 ff. - */ - timclk: timclk@2.4M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&mxtal>; - }; - - /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ - pll1: pll1@0 { - #clock-cells = <0>; - compatible = "st,nomadik-pll-clock"; - pll-id = <1>; - clocks = <&mxtal>; - }; - - /* HCLK divides the PLL1 with 1,2,3 or 4 */ - hclk: hclk@0 { - #clock-cells = <0>; - compatible = "st,nomadik-hclk-clock"; - clocks = <&pll1>; - }; - /* The PCLK domain uses HCLK right off */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&hclk>; - }; - - /* PLL2 is usually 864 MHz and divided into a few fixed rates */ - pll2: pll2@0 { - #clock-cells = <0>; - compatible = "st,nomadik-pll-clock"; - pll-id = <2>; - clocks = <&mxtal>; - }; - clk216: clk216@216M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk108: clk108@108M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&clk216>; - }; - clk72: clk72@72M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - /* The data sheet does not say how this is derived */ - clock-div = <12>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk48: clk48@48M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - /* The data sheet does not say how this is derived */ - clock-div = <18>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk27: clk27@27M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&clk108>; - }; - - /* This apparently exists as well */ - ulpiclk: ulpiclk@60M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - /* - * IP AMBA bus clocks, driving the bus side of the - * peripheral clocking, clock gates. - */ - - hclkdma0: hclkdma0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <0>; - clocks = <&hclk>; - }; - hclksmc: hclksmc@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <1>; - clocks = <&hclk>; - }; - hclksdram: hclksdram@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <2>; - clocks = <&hclk>; - }; - hclkdma1: hclkdma1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <3>; - clocks = <&hclk>; - }; - hclkclcd: hclkclcd@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <4>; - clocks = <&hclk>; - }; - pclkirda: pclkirda@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <5>; - clocks = <&pclk>; - }; - pclkssp: pclkssp@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <6>; - clocks = <&pclk>; - }; - pclkuart0: pclkuart0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <7>; - clocks = <&pclk>; - }; - pclksdi: pclksdi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <8>; - clocks = <&pclk>; - }; - pclki2c0: pclki2c0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <9>; - clocks = <&pclk>; - }; - pclki2c1: pclki2c1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <10>; - clocks = <&pclk>; - }; - pclkuart1: pclkuart1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <11>; - clocks = <&pclk>; - }; - pclkmsp0: pclkmsp0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <12>; - clocks = <&pclk>; - }; - hclkusb: hclkusb@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <13>; - clocks = <&hclk>; - }; - hclkdif: hclkdif@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <14>; - clocks = <&hclk>; - }; - hclksaa: hclksaa@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <15>; - clocks = <&hclk>; - }; - hclksva: hclksva@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <16>; - clocks = <&hclk>; - }; - pclkhsi: pclkhsi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <17>; - clocks = <&pclk>; - }; - pclkxti: pclkxti@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <18>; - clocks = <&pclk>; - }; - pclkuart2: pclkuart2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <19>; - clocks = <&pclk>; - }; - pclkmsp1: pclkmsp1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <20>; - clocks = <&pclk>; - }; - pclkmsp2: pclkmsp2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <21>; - clocks = <&pclk>; - }; - pclkowm: pclkowm@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <22>; - clocks = <&pclk>; - }; - hclkhpi: hclkhpi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <23>; - clocks = <&hclk>; - }; - pclkske: pclkske@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <24>; - clocks = <&pclk>; - }; - pclkhsem: pclkhsem@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <25>; - clocks = <&pclk>; - }; - hclk3d: hclk3d@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <26>; - clocks = <&hclk>; - }; - hclkhash: hclkhash@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <27>; - clocks = <&hclk>; - }; - hclkcryp: hclkcryp@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <28>; - clocks = <&hclk>; - }; - pclkmshc: pclkmshc@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <29>; - clocks = <&pclk>; - }; - hclkusbm: hclkusbm@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <30>; - clocks = <&hclk>; - }; - hclkrng: hclkrng@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <31>; - clocks = <&hclk>; - }; - - /* IP kernel clocks */ - clcdclk: clcdclk@0 { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <36>; - clocks = <&clk72 &clk48>; - }; - irdaclk: irdaclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <37>; - clocks = <&clk48>; - }; - sspiclk: sspiclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <38>; - clocks = <&clk48>; - }; - uart0clk: uart0clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <39>; - clocks = <&clk48>; - }; - sdiclk: sdiclk@48M { - /* Also called MCCLK in some documents */ - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <40>; - clocks = <&clk48>; - }; - i2c0clk: i2c0clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <41>; - clocks = <&clk48>; - }; - i2c1clk: i2c1clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <42>; - clocks = <&clk48>; - }; - uart1clk: uart1clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <43>; - clocks = <&clk48>; - }; - mspclk0: mspclk0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <44>; - clocks = <&clk48>; - }; - usbclk: usbclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <45>; - clocks = <&clk48>; /* 48 MHz not ULPI */ - }; - difclk: difclk@72M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <46>; - clocks = <&clk72>; - }; - ipi2cclk: ipi2cclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <47>; - clocks = <&clk48>; /* Guess */ - }; - ipbmcclk: ipbmcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <48>; - clocks = <&clk48>; /* Guess */ - }; - hsiclkrx: hsiclkrx@216M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <49>; - clocks = <&clk216>; - }; - hsiclktx: hsiclktx@108M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <50>; - clocks = <&clk108>; - }; - uart2clk: uart2clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <51>; - clocks = <&clk48>; - }; - mspclk1: mspclk1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <52>; - clocks = <&clk48>; - }; - mspclk2: mspclk2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <53>; - clocks = <&clk48>; - }; - owmclk: owmclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <54>; - clocks = <&clk48>; /* Guess */ - }; - skeclk: skeclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <56>; - clocks = <&clk48>; /* Guess */ - }; - x3dclk: x3dclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <58>; - clocks = <&clk48>; /* Guess */ - }; - pclkmsp3: pclkmsp3@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <59>; - clocks = <&pclk>; - }; - mspclk3: mspclk3@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <60>; - clocks = <&clk48>; - }; - mshcclk: mshcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <61>; - clocks = <&clk48>; /* Guess */ - }; - usbmclk: usbmclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <62>; - /* Stated as "48 MHz not ULPI clock" */ - clocks = <&clk48>; - }; - rngcclk: rngcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <63>; - clocks = <&clk48>; /* Guess */ - }; - }; - - /* A NAND flash of 128 MiB */ - fsmc: flash@40000000 { - compatible = "stericsson,fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10100000 0x1000>, /* FSMC Register*/ - <0x40000000 0x2000>, /* NAND Base DATA */ - <0x41000000 0x2000>, /* NAND Base ADDR */ - <0x40800000 0x2000>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - clocks = <&hclksmc>; - status = "okay"; - - partition@0 { - label = "X-Loader(NAND)"; - reg = <0x0 0x40000>; - }; - partition@40000 { - label = "MemInit(NAND)"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "BootLoader(NAND)"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "Kernel zImage(NAND)"; - reg = <0x280000 0x300000>; - }; - partition@580000 { - label = "Root Filesystem(NAND)"; - reg = <0x580000 0x1600000>; - }; - partition@1b80000 { - label = "User Filesystem(NAND)"; - reg = <0x1b80000 0x6480000>; - }; - }; - - /* I2C0 connected to the STw4811 power management chip */ - i2c0 { - compatible = "st,nomadik-i2c", "arm,primecell"; - reg = <0x101f8000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <20>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&i2c0clk>, <&pclki2c0>; - clock-names = "mclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; - - stw4811@2d { - compatible = "st,stw4811"; - reg = <0x2d>; - vmmc_regulator: vmmc { - compatible = "st,stw481x-vmmc"; - regulator-name = "VMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - /* I2C1 connected to various sensors */ - i2c1 { - compatible = "st,nomadik-i2c", "arm,primecell"; - reg = <0x101f7000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <21>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&i2c1clk>, <&pclki2c1>; - clock-names = "mclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; - - camera@2d { - compatible = "st,camera"; - reg = <0x10>; - }; - stw5095@1a { - compatible = "st,stw5095"; - reg = <0x1a>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clcd@10120000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x10120000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - interrupt-parent = <&vica>; - clocks = <&clcdclk>, <&hclkclcd>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - vica: interrupt-controller@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x20>; - }; - - vicb: interrupt-controller@10140020 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140020 0x20>; - }; - - uart0: serial@101fd000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101fd000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <12>; - clocks = <&uart0clk>, <&pclkuart0>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - dmas = <&dmac0 14 1>, - <&dmac0 15 1>; - dma-names = "rx", "tx"; - }; - - uart1: serial@101fb000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101fb000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <17>; - clocks = <&uart1clk>, <&pclkuart1>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_default_mux>; - dmas = <&dmac1 22 1>, - <&dmac1 23 1>; - dma-names = "rx", "tx"; - }; - - uart2: serial@101f2000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f2000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <28>; - clocks = <&uart2clk>, <&pclkuart2>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - dmas = <&dmac1 30 1>, - <&dmac1 31 1>; - dma-names = "rx", "tx"; - }; - - rng: rng@101b0000 { - compatible = "arm,primecell"; - reg = <0x101b0000 0x1000>; - clocks = <&rngcclk>, <&hclkrng>; - clock-names = "rng", "apb_pclk"; - }; - - rtc: rtc@101e8000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x101e8000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - interrupt-parent = <&vica>; - interrupts = <10>; - }; - - mmcsd: mmc@101f6000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x101f6000 0x1000>; - clocks = <&sdiclk>, <&pclksdi>; - clock-names = "mclk", "apb_pclk"; - interrupt-parent = <&vica>; - interrupts = <22>; - max-frequency = <400000>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - full-pwr-cycle; - /* - * The STw4811 circuit used with the Nomadik strictly - * requires that all of these signal direction pins be - * routed and used for its 4-bit levelshifter. - */ - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; - st,sig-dir-cmd; - st,sig-pin-fbclk; - pinctrl-names = "default"; - pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; - vmmc-supply = <&vmmc_regulator>; - }; - - dmac0: dma-controller@10130000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <15>; - clocks = <&hclkdma0>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - dmac1: dma-controller@10150000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10150000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <13>; - clocks = <&hclkdma1>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts deleted file mode 100644 index 9a3d6546399d..000000000000 --- a/arch/arm/boot/dts/ste-snowball.dts +++ /dev/null @@ -1,657 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2011 ST-Ericsson AB - */ - -/dts-v1/; -#include "ste-db9500.dtsi" -#include "ste-href-ab8500.dtsi" -#include "ste-href-family-pinctrl.dtsi" - -/ { - model = "Calao Systems Snowball platform with device tree"; - compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - battery: battery { - compatible = "simple-battery"; - battery-type = "lithium-ion-polymer"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "murata,ncp18wb473"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - en_3v3_reg: en_3v3 { - compatible = "regulator-fixed"; - regulator-name = "en-3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */ - gpio = <&ab8500_gpio 25 0x4>; - startup-delay-us = <5000>; - enable-active-high; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - debounce-interval = <50>; - wakeup-source; - linux,code = <2>; - label = "userpb"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - button@2 { - debounce-interval = <50>; - wakeup-source; - linux,code = <3>; - label = "extkb1"; - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - button@3 { - debounce-interval = <50>; - wakeup-source; - linux,code = <4>; - label = "extkb2"; - gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - }; - button@4 { - debounce-interval = <50>; - wakeup-source; - linux,code = <5>; - label = "extkb3"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; - button@5 { - debounce-interval = <50>; - wakeup-source; - linux,code = <6>; - label = "extkb4"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpioled_snowball_mode>; - used-led { - label = "user_led"; - gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - soc { - /* Name the GPIO muxed rails on the Snowball board */ - gpio@8012e000 { - /* GPIOs 0 - 31 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "AP_GPIO31"; - }; - - gpio@8012e080 { - /* GPIOs 32 - 63 */ - gpio-line-names = "USR PB", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e000 { - /* GPIOs 64 - 95 */ - gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e100 { - /* GPIOs 128 - 159 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "IRQ_LAN", "RSTn_LAN", - "USR_LED", "", "", "", "", "", "", - "", "", "AP_GPIO151", "AP_GPIO152", - "", "", "", "", "", "", ""; - }; - - gpio@8000e180 { - /* GPIOs 160 - 191 */ - gpio-line-names = "", "AP_GPIO161", "AP_GPIO162", - "ACCELEROMETER_INT1_RDY", - "ACCELEROMETER_INT2", "MAG_DRDY", - "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC", - "GYRO_INT", "UART_WAKE", "GBF_RESET", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8011e000 { - /* GPIOs 192 - 223 */ - gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST", - "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", - "WLAN_RESETN", "WLAN_IRQ", "MMC_EN", - "MMC_CD", "", "", "", "", ""; - }; - - gpio@8011e080 { - /* GPIOs 224 - 255 */ - gpio-line-names = "", "", "", "", "SD_SEL", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - msp0: msp@80123000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp0txrxtfstck_a_1_default>; - status = "okay"; - }; - - msp1: msp@80124000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp1txrx_a_1_default>; - status = "okay"; - }; - - msp2: msp@80117000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp2_a_1_default>; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - external-bus@50000000 { - status = "okay"; - - ethernet@0 { - compatible = "smsc,lan9115"; - reg = <0 0x10000>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio4>; - vdd33a-supply = <&en_3v3_reg>; - vddvario-supply = <&db8500_vape_reg>; - pinctrl-names = "default"; - pinctrl-0 = <ð_snowball_mode>; - - reg-shift = <1>; - reg-io-width = <2>; - smsc,force-internal-phy; - smsc,irq-active-high; - smsc,irq-push-pull; - - clocks = <&prcc_pclk 3 0>; - }; - }; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - /* GPIO228 SD_SEL */ - gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - /* GPIO217 MMC_EN */ - enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - }; - - // External Micro SD slot - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - /* All direction control is used */ - st,sig-dir-cmd; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; - st,sig-pin-fbclk; - full-pwr-cycle; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; - pinctrl-1 = <&mc0_a_1_sleep>; - - /* GPIO218 MMC_CD */ - cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; - - status = "okay"; - }; - - // WLAN SDIO channel - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_1_default>; - pinctrl-1 = <&mc1_a_1_sleep>; - - status = "okay"; - }; - - // Unused PoP eMMC - register and put it to sleep by default */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - pinctrl-names = "default"; - pinctrl-0 = <&mc2_a_1_sleep>; - - status = "okay"; - }; - - // On-board eMMC - mmc@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - no-sdio; - no-sd; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc4_a_1_default>; - pinctrl-1 = <&mc4_a_1_sleep>; - - status = "okay"; - }; - - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - }; - - /* This UART is unused and thus left disabled */ - serial@80121000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - }; - - serial@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - status = "okay"; - }; - - i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - status = "okay"; - }; - - i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_b_2_default>; - pinctrl-1 = <&i2c1_b_2_sleep>; - status = "okay"; - }; - - i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - status = "okay"; - lsm303dlh@18 { - /* Accelerometer */ - compatible = "st,lsm303dlh-accel"; - st,drdy-int-pin = <1>; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>, /* INT1 */ - <4 IRQ_TYPE_EDGE_RISING>; /* INT2 */ - }; - lsm303dlh@1e { - /* Magnetometer */ - compatible = "st,lsm303dlh-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; /* DRDY line */ - }; - l3g4200d@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <9 IRQ_TYPE_EDGE_RISING>; /* INT1 */ - }; - lsp001wm@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - - i2c@80110000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - status = "okay"; - }; - - spi@80002000 { - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_snowball_mode>; - status = "okay"; - }; - - prcmu@80157000 { - ab8500 { - gpio { - /* - * AB8500 GPIOs are numbered starting from 1, so the first - * index 0 is what in the datasheet is called "GPIO1", and - * the second is "GPIO2" and so forth. Confusingly, the - * Snowball schematic then names the "GPIO2" line "PM_GPIO1". - * while later naming "GPIO4" as "PM_GPIO4". - */ - gpio-line-names = "", /* AB8500 GPIO1 */ - "PM_GPIO1", /* AB8500 GPIO2 */ - "WLAN_CLK_REQ", /* AB8500 GPIO3 */ - "PM_GPIO4", /* AB8500 GPIO4 */ - "", "", "", "", "", "", "", "", "", "", "", - "EN_3V6", /* AB8500 GPIO16 */ - "", "", "", "" ,"", "", "", "", "", - "EN_3V3", /* AB8500 GPIO26 */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "PM_GPIO40", /* AB8500 GPIO40 */ - "PM_GPIO41", /* AB8500 GPIO41 */ - "PM_GPIO42"; /* AB8500 GPIO42 */ - }; - - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ext_regulators: regulator-external { - ab8500_ext1_reg: ab8500_ext1 { - regulator-name = "ab8500-ext-supply1"; - }; - - ab8500_ext2_reg_reg: ab8500_ext2 { - regulator-name = "ab8500-ext-supply2"; - }; - - ab8500_ext3_reg_reg: ab8500_ext3 { - regulator-name = "ab8500-ext-supply3"; - }; - }; - - regulator { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - pinctrl { - /* - * Set this up using hogs, as time goes by and as seems fit, these - * can be moved over to being controlled by respective device. - */ - pinctrl-names = "default"; - pinctrl-0 = <&gbf_snowball_mode>, - <&wlan_snowball_mode>; - - ethernet { - /* - * Mux in "SM" which is used for the - * SMSC911x Ethernet adapter - */ - eth_snowball_mode: eth_snowball { - snowball_mux { - function = "sm"; - groups = "sm_b_1"; - }; - /* LAN IRQ pin */ - snowball_cfg1 { - pins = "GPIO140_B11"; - ste,config = <&in_nopull>; - }; - /* LAN reset pin */ - snowball_cfg2 { - pins = "GPIO141_C12"; - ste,config = <&gpio_out_hi>; - }; - - }; - }; - sdi0 { - sdi0_default_mode: sdi0_default { - snowball_mux { - function = "mc0"; - /* Add the DAT31 pin even if it is not really used */ - groups = "mc0dat31dir_a_1"; - }; - snowball_cfg1 { - pins = "GPIO21_AB3"; /* DAT31DIR */ - ste,config = <&out_hi>; - }; - /* SD card detect GPIO pin, extend default state */ - snowball_cfg2 { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - /* VMMCI level-shifter enable */ - snowball_cfg3 { - pins = "GPIO217_AH12"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - snowball_cfg4 { - pins = "GPIO228_AJ6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - ssp0 { - ssp0_snowball_mode: ssp0_snowball_default { - snowball_mux { - function = "ssp0"; - groups = "ssp0_a_1"; - }; - snowball_cfg1 { - pins = "GPIO144_B13"; /* FRM */ - ste,config = <&gpio_out_hi>; - }; - snowball_cfg2 { - pins = "GPIO145_C13"; /* RXD */ - ste,config = <&in_pd>; - }; - snowball_cfg3 { - pins = - "GPIO146_D13", /* TXD */ - "GPIO143_D12"; /* CLK */ - ste,config = <&out_lo>; - }; - - }; - }; - gpio_led { - gpioled_snowball_mode: gpioled_default { - snowball_cfg1 { - pins = "GPIO142_C11"; - ste,config = <&gpio_out_hi>; - }; - - }; - }; - accelerometer { - accel_snowball_mode: accel_snowball { - /* Accelerometer lines */ - snowball_cfg1 { - pins = - "GPIO163_C20", /* ACCEL_IRQ1 */ - "GPIO164_B21"; /* ACCEL_IRQ2 */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - gyro { - gyro_snowball_mode: gyro_snowball { - snowball_cfg1 { - pins = - "GPIO166_A22", /* DRDY */ - "GPIO169_D22"; /* INT */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_snowball_mode: magneto_snowball { - snowball_cfg1 { - pins = "GPIO165_C21"; /* MAG_DRDY */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - gbf { - gbf_snowball_mode: gbf_snowball { - /* - * GBF (GPS, Bluetooth, FM-radio) interface, - * pull low to reset state - */ - snowball_cfg1 { - pins = "GPIO171_D23"; /* GBF_ENA_RESET */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - wlan { - wlan_snowball_mode: wlan_snowball { - /* - * Activate this mode with the WLAN chip. - * These are plain GPIO pins used by WLAN - */ - snowball_cfg1 { - pins = - "GPIO161_D21", /* WLAN_PMU_EN */ - "GPIO215_AH13"; /* WLAN_ENA */ - ste,config = <&gpio_out_lo>; - }; - snowball_cfg2 { - pins = "GPIO216_AG12"; /* WLAN_IRQ */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - - mcde@a0350000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_default_mode>; - pinctrl-1 = <&lcd_sleep_mode>; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts deleted file mode 100644 index 463942ae755e..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ /dev/null @@ -1,793 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO, - * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively - * for T-Mobile in the United States. - * - * This phone is closely related to the Codina, but has: - * - No CPU speed cap, full ~1GHz rate - * - Different power management IC, AB8505 - * - As AB8505 has a micro USB phy, no TI TSU6111 - * - Different power routing such as the removal of the external LDO for the - * touchscreen in favor of using the AB8505 - * - Using a regulator for the key backlight LED - * - Using the Samsung S6D27A1 panel by default - * - The panel is using one of the ordinary AB8505 regulators for 1.8V - * - WiFi/Bluetooth combi chip upgraded to BCM4334 - * - GPIO for backlight control moved from 68 to 69 - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-ab8505.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "Samsung Galaxy Exhibit (SGH-T599)"; - compatible = "samsung,codina-tmo", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb425161lu"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - /* TI TXS0206 level translator for 2.9 V */ - sd_level_translator: regulator-gpio { - compatible = "regulator-fixed"; - - /* GPIO87 EN */ - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - - startup-delay-us = <200>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* External LDO MIC5366-3.3YMT for eMMC */ - ldo_3v3_reg: regulator-gpio-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VMEM_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_ldo_en_default_mode>; - }; - - /* - * External Ricoh RP152L010B-TR LCD LDO regulator for the display. - * LCD_PWR_EN controls both the 3.0V output. - */ - lcd_3v0_reg: regulator-gpio-lcd-3v0 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* GPIO219 controls this regulator */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - - /* - * This regulator is a GPIO line that drives the Broadcom WLAN - * line WL_REG_ON high and enables the internal regulators - * inside the chip. Unfortunatley it is erroneously named - * WLAN_RST_N on the schematic but it is not a reset line. - * - * The voltage specified here is only used to determine the OCR mask, - * the for the SDIO connector, the chip is actually connected - * directly to VBAT. - */ - wl_reg: regulator-gpio-wlan { - compatible = "regulator-fixed"; - regulator-name = "WL_REG_ON"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - startup-delay-us = <100000>; - /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_ldo_en_default>; - }; - - vibrator { - compatible = "gpio-vibrator"; - /* GPIO195 "MOT_EN" */ - enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default_mode>; - - button-home { - linux,code = ; - label = "HOME"; - /* GPIO91 */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - }; - button-volup { - linux,code = ; - label = "VOL+"; - /* GPIO67 */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - button-voldown { - linux,code = ; - label = "VOL-"; - /* GPIO92 */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - }; - - led-touchkeys { - compatible = "regulator-led"; - vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V - default-state = "on"; - function = LED_FUNCTION_KBD_BACKLIGHT; - color = ; - }; - - ktd253: backlight { - compatible = "kinetic,ktd253"; - /* GPIO69 is used on Codina R0.4 and Codina TMO */ - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - /* Default to 13/32 brightness */ - default-brightness = <13>; - pinctrl-names = "default"; - pinctrl-0 = <&ktd253_backlight_default_mode>; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - /* TODO: this should also be used by the SM5103 Camera power management unit */ - }; - - /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */ - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_1_default>; - #address-cells = <1>; - #size-cells = <0>; - - magnetometer@c { - compatible = "alps,hscdtd008a"; - reg = <0x0c>; - clock-frequency = <400000>; - - avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V - }; - }; - - spi { - compatible = "spi-gpio"; - /* Clock on GPIO220, pin SCL */ - sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; - /* MOSI on GPIO224, pin SDI "slave data in" */ - mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - /* MISO on GPIO225, pin SDO "slave data out" */ - miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - /* Chip select on GPIO201 */ - cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - panel@0 { - compatible = "samsung,s6d27a1"; - spi-max-frequency = <1200000>; - /* TYPE 3: inverse clock polarity and phase */ - spi-cpha; - spi-cpol; - - reg = <0>; - vci-supply = <&lcd_3v0_reg>; - vccio-supply = <&ab8500_ldo_aux6_reg>; - - /* Reset on GPIO139 */ - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ - interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_default_mode>; - backlight = <&ktd253>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - }; - - soc { - /* External Micro SD slot */ - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-pin-fbclk; - full-pwr-cycle; - /* MMC is powered by AUX3 1.2V .. 2.91V */ - vmmc-supply = <&ab8500_ldo_aux3_reg>; - /* 2.9 V level translator is using AUX3 at 2.9 V as well */ - vqmmc-supply = <&sd_level_translator>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_2_default>; - pinctrl-1 = <&mc0_a_2_sleep>; - cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 - status = "okay"; - }; - - /* WLAN SDIO channel */ - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - non-removable; - cap-sd-highspeed; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - /* - * GPIO-controlled voltage enablement: this drives - * the WL_REG_ON line high when we use this device. - * Represented as regulator to fill OCR mask. - */ - vmmc-supply = <&wl_reg>; - - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - /* GPIO216 WL_HOST_WAKE */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_mode>; - }; - }; - - /* eMMC */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - vmmc-supply = <&ldo_3v3_reg>; - pinctrl-names = "default", "sleep"; - /* - * GPIO130 will be set to input no pull-up resulting in a resistor - * pulling the reset high and taking the memory out of reset. - */ - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - status = "okay"; - }; - - /* GBF (Bluetooth) UART */ - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - - bluetooth { - /* BCM4334B0 actually */ - compatible = "brcm,bcm4330-bt"; - /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - /* BT_WAKE on GPIO199 */ - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - /* BT_HOST_WAKE on GPIO97 */ - /* FIXME: convert to interrupt */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - /* BT_RST_N on GPIO209 */ - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_mode>; - }; - }; - - /* GPS UART */ - serial@80121000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - /* CTS/RTS is not used, CTS is repurposed as GPIO */ - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ - }; - - /* Debugging console UART connected to AB8505 */ - serial@80007000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - prcmu@80157000 { - ab8505 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <36000>; - }; - - /* This is mostly identical to the Codina v0.4 regulators */ - regulator { - ab8500_ldo_aux1 { - regulator-name = "v-sensors-vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux2 { - regulator-name = "v-aux2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux3 { - regulator-name = "v-mmc-sd"; - }; - - ab8500_ldo_aux4 { - regulator-name = "v-aux4"; - /* - * Providing some span here makes the touchkey - * LEDs actually dimmable. - */ - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux5 { - regulator-name = "v-aux5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux6 { - /* 1.8 V to the display */ - regulator-name = "v-aux6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux8 { - regulator-name = "v-sensors-vio"; - }; - }; - }; - }; - - /* I2C0 also known as "AGC I2C" */ - i2c@80004000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - proximity@39 { - /* Codina has the Amstaos TMD2672 */ - compatible = "amstaos,tmd2672"; - clock-frequency = <400000>; - reg = <0x39>; - - /* IRQ on GPIO146 "PS_INT" */ - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&ab8500_ldo_aux8_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&tmd2672_codina_default>; - }; - }; - - /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ - i2c@80128000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - /* Bosch BMA254 accelerometer */ - accelerometer@18 { - compatible = "bosch,bma254"; - reg = <0x18>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; - vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V - vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - }; - }; - - /* I2C3 */ - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - /* TODO: write bindings and driver for this touchscreen */ - - /* Zinitix BT404 ISP part */ - isp@50 { - compatible = "zinitix,bt404-isp"; - reg = <0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - - /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ - touchscreen@20 { - compatible = "zinitix,bt404"; - reg = <0x20>; - /* GPIO218 (TSP_INT_1V8) */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V - vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V - zinitix,mode = <2>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dpi_default_mode>; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&pinctrl { - /* - * This extends the MC0_A_2 default config to include - * the card detect GPIO217 line. - */ - sdi0 { - mc0_a_2_default { - default_cfg4 { - pins = "GPIO217_AH12"; /* card detect */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - sdi2 { - /* - * GPIO130 should be set in GPIO mode and - * pulled down. (Not connected.) - */ - mc2_a_1_default { - default_cfg2 { - pins = "GPIO130_C8"; /* FBCLK */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - /* GPIO that enables the 2.9V SD card level translator */ - sd-level-translator { - sd_level_translator_default: sd_level_translator_default { - /* level shifter on GPIO87 */ - codina_cfg1 { - pins = "GPIO87_B3"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the eMMC */ - emmc-ldo { - emmc_ldo_en_default_mode: emmc_ldo_default { - /* LDO enable on GPIO223 */ - codina_cfg1 { - pins = "GPIO223_AH9"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIOs for panel control */ - panel { - panel_default_mode: panel_default { - codina_cfg1 { - /* Reset line */ - pins = "GPIO139_C9"; - ste,config = <&gpio_out_lo>; - }; - codina_cfg2 { - /* ESD IRQ line "LCD detect" */ - pins = "GPIO93_B7"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the LCD display */ - lcd-ldo { - lcd_pwr_en_default_mode: lcd_pwr_en_default { - /* LCD_PWR_EN on GPIO219 */ - codina_cfg1 { - pins = "GPIO219_AG10"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the WLAN internal LDO regulators */ - wlan-ldo { - wlan_ldo_en_default: wlan_ldo_default { - /* GPIO215 named WLAN_RST_N */ - codina_cfg1 { - pins = "GPIO215_AH13"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Backlight GPIO */ - backlight { - ktd253_backlight_default_mode: backlight_default { - skomer_cfg1 { - pins = "GPIO69_E2"; /* LCD_BL_CTRL */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Flash and torch */ - flash { - gpio_flash_default_mode: flash_default { - codina_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO keys */ - gpio-keys { - gpio_keys_default_mode: gpio_keys_default { - skomer_cfg1 { - pins = "GPIO67_G2", /* VOL UP */ - "GPIO91_B6", /* HOME */ - "GPIO92_D6"; /* VOL DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - /* Interrupt line for the Zinitix BT404 touchscreen */ - tsp { - tsp_default: tsp_default { - codina_cfg1 { - pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* Interrupt line for light/proximity sensor TMD2672 */ - tmd2672 { - tmd2672_codina_default: tmd2672_codina { - codina_cfg1 { - pins = "GPIO146_D13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for subpmu */ - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - codina_cfg1 { - pins = "GPIO143_D12", "GPIO144_B13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the NFC */ - i2c-gpio-1 { - i2c_gpio_1_default: i2c_gpio_1 { - codina_cfg1 { - pins = "GPIO151_D17", "GPIO152_D16"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based SPI bus for the display */ - spi-gpio-0 { - spi_gpio_0_default: spi_gpio_0_d { - codina_cfg1 { - pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; - ste,config = <&gpio_out_hi>; - }; - codina_cfg2 { - pins = "GPIO225_AG8"; - /* Needs pull down, no pull down resistor on board */ - ste,config = <&gpio_in_pd>; - }; - }; - spi_gpio_0_sleep: spi_gpio_0_s { - codina_cfg1 { - pins = "GPIO220_AH10", "GPIO201_AF24", - "GPIO224_AG9", "GPIO225_AG8"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - wlan { - wlan_default_mode: wlan_default { - /* GPIO216 for WL_HOST_WAKE */ - codina_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - bluetooth { - bluetooth_default_mode: bluetooth_default { - /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ - codina_cfg1 { - pins = "GPIO199_AH23", "GPIO222_AJ9"; - ste,config = <&gpio_out_lo>; - }; - /* GPIO97 BT_HOST_WAKE */ - codina_cfg2 { - pins = "GPIO97_D9"; - ste,config = <&gpio_in_nopull>; - }; - /* GPIO209 BT_RST_N */ - codina_cfg3 { - pins = "GPIO209_AG15"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - vibrator { - vibrator_default: vibrator_default { - codina_cfg1 { - pins = "GPIO195_AG28"; /* MOT_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - mcde { - dpi_default_mode: dpi_default { - default_mux1 { - /* Mux in all the data lines */ - function = "lcd"; - groups = - /* Data lines D0-D7 GPIO70..GPIO77 */ - "lcd_d0_d7_a_1", - /* Data lines D8-D11 GPIO78..GPIO81 */ - "lcd_d8_d11_a_1", - /* Data lines D12-D15 GPIO82..GPIO85 */ - "lcd_d12_d15_a_1", - /* Data lines D16-D23 GPIO161..GPIO168 */ - "lcd_d16_d23_b_1"; - }; - default_mux2 { - function = "lcda"; - /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ - groups = "lcdaclk_b_1", "lcda_b_1"; - }; - /* Input, no pull-up is the default state for pins used for an alt function */ - default_cfg1 { - pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; - ste,config = <&in_nopull>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts deleted file mode 100644 index c1ae0e23fe45..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ /dev/null @@ -1,953 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Devicetree for the Samsung Galaxy Ace 2 GT-I8160 also known as Codina. - * - * NOTE: this is the most common variant according to the vendor tree, known - * as "R0.0". There appears to be a "R0.4" variant with backlight on GPIO69, - * AB8505 and other changes. There is also talk about some variants having a - * Samsung S6D27A1 display, indicated by passing a different command line from - * the boot loader. - * - * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). - * The GT-I8160 plain is known as the "europe" variant. - * The GT-I8160P is the CDMA version and it appears to not use the ST - * Microelectronics accelerometer and reportedly has NFC mounted. - * The GT-I8160chn appears to be the same as the europe variant. - * - * There is also the Codina-TMO, Samsung SGH-T599, which has its own device - * tree. - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-ab8500.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "Samsung Galaxy Ace 2 (GT-I8160)"; - compatible = "samsung,codina", "st-ericsson,u8500"; - - cpus { - cpu@300 { - /* - * This has a frequency cap at ~800 MHz in the firmware. - * (Changing this number here will not overclock it.) - */ - operating-points = <798720 0 - 399360 0 - 199680 0>; - }; - }; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb425161lu"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - /* TI TXS0206 level translator for 2.9 V */ - sd_level_translator: regulator-gpio { - compatible = "regulator-fixed"; - - /* GPIO87 EN */ - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - - startup-delay-us = <200>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* External LDO MIC5366-3.3YMT for eMMC */ - ldo_3v3_reg: regulator-gpio-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VMEM_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_ldo_en_default_mode>; - }; - - /* - * External Ricoh "TSP" regulator for the touchscreen. - * One GPIO line controls two voltages of 3.3V and 1.8V - * this line is known as "TSP_LDO_ON1" in the schematics. - */ - ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "LDO_TSP_A3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* GPIO94 controls this regulator */ - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_en_default_mode>; - }; - ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_TSP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO94 controls this regulator */ - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_en_default_mode>; - }; - - /* - * External Ricoh RP152L010B-TR LCD LDO regulator for the display. - * LCD_PWR_EN controls both a 3.0V and 1.8V output. - */ - lcd_3v0_reg: regulator-gpio-lcd-3v0 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* GPIO219 controls this regulator */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - lcd_1v8_reg: regulator-gpio-lcd-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO219 controls this regulator too */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - - /* - * This regulator is a GPIO line that drives the Broadcom WLAN - * line WL_REG_ON high and enables the internal regulators - * inside the chip. Unfortunatley it is erroneously named - * WLAN_RST_N on the schematic but it is not a reset line. - * - * The voltage specified here is only used to determine the OCR mask, - * the for the SDIO connector, the chip is actually connected - * directly to VBAT. - */ - wl_reg: regulator-gpio-wlan { - compatible = "regulator-fixed"; - regulator-name = "WL_REG_ON"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - startup-delay-us = <100000>; - /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_ldo_en_default>; - }; - - vibrator { - compatible = "gpio-vibrator"; - /* GPIO195 "MOT_EN" */ - enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default_mode>; - - button-home { - linux,code = ; - label = "HOME"; - /* GPIO91 */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - }; - button-volup { - linux,code = ; - label = "VOL+"; - /* GPIO67 */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - button-voldown { - linux,code = ; - label = "VOL-"; - /* GPIO92 */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds_default_mode>; - touchkey-led { - label = "touchkeys"; - /* - * GPIO194 on R0.0, R0.4 does not use this at all, it - * will instead turn LDO AUX4 on/off for key led backlighy. - * (Line is pulled down on R0.4) - */ - gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - ktd253: backlight { - compatible = "kinetic,ktd253"; - /* - * GPIO68 is for R0.0, the board file talks about a TMO variant - * (R0.4) using GPIO69. - */ - enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - /* Default to 13/32 brightness */ - default-brightness = <13>; - pinctrl-names = "default"; - pinctrl-0 = <&ktd253_backlight_default_mode>; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - magnetometer@c { - compatible = "alps,hscdtd008a"; - reg = <0x0c>; - clock-frequency = <400000>; - - avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - dvdd-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - }; - /* TODO: this should also be used by the SM5103 Camera power management unit */ - }; - - /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC I2C" */ - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_1_default>; - #address-cells = <1>; - #size-cells = <0>; - - nfc@2b { - /* NXP NFC circuit PN544 C1 marked NXP 44501 */ - compatible = "nxp,pn544-i2c"; - /* IF0, IF1 high, gives I2C address 0x2B */ - reg = <0x2b>; - clock-frequency = <400000>; - /* NFC IRQ on GPIO32 */ - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - /* GPIO 31 */ - firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - /* GPIO88 */ - enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pn544_codina_default>; - }; - }; - - spi { - compatible = "spi-gpio"; - /* Clock on GPIO220, pin SCL */ - sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; - /* MOSI on GPIO224, pin SDI "slave data in" */ - mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - /* MISO on GPIO225, pin SDO "slave data out" */ - miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - /* Chip select on GPIO201 */ - cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - /* - * Some Codinas (90%) have a WideChips WS2401-based LMS380KF01 - * display mounted and some 10% has a Samsung S6D27A1 instead. - * The boot loader needs to modify this compatible to - * correspond to whatever is passed from the early Samsung boot. - */ - panel@0 { - compatible = "samsung,lms380kf01"; - spi-max-frequency = <1200000>; - /* TYPE 3: inverse clock polarity and phase */ - spi-cpha; - spi-cpol; - - reg = <0>; - vci-supply = <&lcd_3v0_reg>; - vccio-supply = <&lcd_1v8_reg>; - - /* Reset on GPIO139 */ - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ - interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_default_mode>; - backlight = <&ktd253>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - }; - - soc { - /* External Micro SD slot */ - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-pin-fbclk; - full-pwr-cycle; - /* MMC is powered by AUX3 1.2V .. 2.91V */ - vmmc-supply = <&ab8500_ldo_aux3_reg>; - /* 2.9 V level translator is using AUX3 at 2.9 V as well */ - vqmmc-supply = <&sd_level_translator>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_2_default>; - pinctrl-1 = <&mc0_a_2_sleep>; - cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 - status = "okay"; - }; - - /* WLAN SDIO channel */ - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - non-removable; - cap-sd-highspeed; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - /* - * GPIO-controlled voltage enablement: this drives - * the WL_REG_ON line high when we use this device. - * Represented as regulator to fill OCR mask. - */ - vmmc-supply = <&wl_reg>; - - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - /* Actually BRCM4330 */ - compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - /* GPIO216 WL_HOST_WAKE */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_mode>; - }; - }; - - /* eMMC */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - vmmc-supply = <&ldo_3v3_reg>; - pinctrl-names = "default", "sleep"; - /* - * GPIO130 will be set to input no pull-up resulting in a resistor - * pulling the reset high and taking the memory out of reset. - */ - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - status = "okay"; - }; - - /* GBF (Bluetooth) UART */ - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - /* BT_WAKE on GPIO199 */ - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - /* BT_HOST_WAKE on GPIO97 */ - /* FIXME: convert to interrupt */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - /* BT_RST_N on GPIO209 */ - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_mode>; - }; - }; - - /* GPS UART */ - serial@80121000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; - - gnss { - compatible = "brcm,bcm4751"; - /* GPS_RSTN on GPIO21 */ - reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - /* GPS_ON_OFF on GPIO86 */ - enable-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - /* GPS_1V8 (VSMPS2) */ - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&bcm4751_codina_default>; - }; - }; - - /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - serial@80007000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - prcmu@80157000 { - ab8500 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <36000>; - }; - - regulator { - ab8500_ldo_aux1 { - /* Used for VDD for sensors */ - regulator-name = "V-SENSORS-VDD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux2 { - /* Used for VIO for sensors */ - regulator-name = "V-SENSORS-VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux3 { - /* Used for voltage for external MMC/SD card */ - regulator-name = "V-MMC-SD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2910000>; - }; - }; - }; - }; - - /* I2C0 also known as "AGC I2C" */ - i2c@80004000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - proximity@39 { - /* Codina has the Amstaos TMD2672 */ - compatible = "amstaos,tmd2672"; - clock-frequency = <400000>; - reg = <0x39>; - - /* IRQ on GPIO146 "PS_INT" */ - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - /* FIXME: needs a VDDIO supply that is connected to a pull-up resistor */ - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&tms2672_codina_default>; - }; - }; - - /* I2C1 on GPIO16 and GPIO17 also called "MUS I2C" */ - i2c@80122000 { - status = "okay"; - pinctrl-names = "default","sleep"; - /* FIXME: If it doesn't work try what we use on Gavini */ - pinctrl-0 = <&i2c1_b_2_default>; - pinctrl-1 = <&i2c1_b_2_sleep>; - - /* Texas Instruments TSU6111 micro USB switch */ - usb-switch@25 { - compatible = "ti,tsu6111"; - reg = <0x25>; - /* Interrupt JACK_INT_N on GPIO95 */ - interrupt-parent = <&gpio2>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&tsu6111_codina_default>; - }; - }; - - /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ - i2c@80128000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - lisd3dh@19 { - /* ST Microelectronics Accelerometer */ - compatible = "st,lis3dh-accel"; - st,drdy-int-pin = <1>; - reg = <0x19>; - vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; - }; - }; - - /* I2C3 */ - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - /* TODO: write bindings and driver for this touchscreen */ - - /* Zinitix BT404 ISP part */ - isp@50 { - compatible = "zinitix,bt404-isp"; - reg = <0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - - /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ - touchscreen@20 { - compatible = "zinitix,bt404"; - reg = <0x20>; - /* GPIO218 (TSP_INT_1V8) */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - vcca-supply = <&ldo_tsp_3v3_reg>; - vdd-supply = <&ldo_tsp_1v8_reg>; - zinitix,mode = <2>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dpi_default_mode>; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&pinctrl { - /* - * This extends the MC0_A_2 default config to include - * the card detect GPIO217 line. - */ - sdi0 { - mc0_a_2_default { - default_cfg4 { - pins = "GPIO217_AH12"; /* card detect */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - sdi2 { - /* - * This will make the resistor mounted in R0.0 pull up - * the reset line and take the eMMC out of reset. On - * R0.4 variants, GPIO130 should be set in GPIO mode and - * pulled down. (Not connected.) - */ - mc2_a_1_default { - default_cfg2 { - pins = "GPIO130_C8"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - }; - }; - /* GPIO that enables the 2.9V SD card level translator */ - sd-level-translator { - sd_level_translator_default: sd_level_translator_default { - /* level shifter on GPIO87 */ - codina_cfg1 { - pins = "GPIO87_B3"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the eMMC */ - emmc-ldo { - emmc_ldo_en_default_mode: emmc_ldo_default { - /* LDO enable on GPIO223 */ - codina_cfg1 { - pins = "GPIO223_AH9"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIOs for panel control */ - panel { - panel_default_mode: panel_default { - codina_cfg1 { - /* Reset line */ - pins = "GPIO139_C9"; - ste,config = <&gpio_out_lo>; - }; - codina_cfg2 { - /* ESD IRQ line "LCD detect" */ - pins = "GPIO93_B7"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the touchscreen */ - tsp-ldo { - tsp_ldo_en_default_mode: tsp_ldo_default { - /* LDO enable on GPIO94 */ - gavini_cfg1 { - pins = "GPIO94_D7"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the LCD display */ - lcd-ldo { - lcd_pwr_en_default_mode: lcd_pwr_en_default { - /* LCD_PWR_EN on GPIO219 */ - codina_cfg1 { - pins = "GPIO219_AG10"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the key LED */ - key-led { - gpio_leds_default_mode: en_led_ldo_default { - /* EN_LED_LDO on GPIO194 */ - codina_cfg1 { - pins = "GPIO194_AF27"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the WLAN internal LDO regulators */ - wlan-ldo { - wlan_ldo_en_default: wlan_ldo_default { - /* GPIO215 named WLAN_RST_N */ - codina_cfg1 { - pins = "GPIO215_AH13"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Backlight GPIO */ - backlight { - ktd253_backlight_default_mode: backlight_default { - skomer_cfg1 { - pins = "GPIO68_E1"; /* LCD_BL_CTRL */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Flash and torch */ - flash { - gpio_flash_default_mode: flash_default { - codina_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO keys */ - gpio-keys { - gpio_keys_default_mode: gpio_keys_default { - skomer_cfg1 { - pins = "GPIO67_G2", /* VOL UP */ - "GPIO91_B6", /* HOME */ - "GPIO92_D6"; /* VOL DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - /* Interrupt line for the Zinitix BT404 touchscreen */ - tsp { - tsp_default: tsp_default { - codina_cfg1 { - pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* Interrupt line for light/proximity sensor TMS2672 */ - tms2672 { - tms2672_codina_default: tms2672_codina { - codina_cfg1 { - pins = "GPIO146_D13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for subpmu */ - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - codina_cfg1 { - pins = "GPIO143_D12", "GPIO144_B13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the NFC */ - i2c-gpio-1 { - i2c_gpio_1_default: i2c_gpio_1 { - codina_cfg1 { - pins = "GPIO151_D17", "GPIO152_D16"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based SPI bus for the display */ - spi-gpio-0 { - spi_gpio_0_default: spi_gpio_0_d { - codina_cfg1 { - pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; - ste,config = <&gpio_out_hi>; - }; - codina_cfg2 { - pins = "GPIO225_AG8"; - /* Needs pull down, no pull down resistor on board */ - ste,config = <&gpio_in_pd>; - }; - }; - spi_gpio_0_sleep: spi_gpio_0_s { - codina_cfg1 { - pins = "GPIO220_AH10", "GPIO201_AF24", - "GPIO224_AG9", "GPIO225_AG8"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - wlan { - wlan_default_mode: wlan_default { - /* GPIO216 for WL_HOST_WAKE */ - codina_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - bluetooth { - bluetooth_default_mode: bluetooth_default { - /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ - codina_cfg1 { - pins = "GPIO199_AH23", "GPIO222_AJ9"; - ste,config = <&gpio_out_lo>; - }; - /* GPIO97 BT_HOST_WAKE */ - codina_cfg2 { - pins = "GPIO97_D9"; - ste,config = <&gpio_in_nopull>; - }; - /* GPIO209 BT_RST_N */ - codina_cfg3 { - pins = "GPIO209_AG15"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* Interrupt line for TI TSU6111 Micro USB switch */ - tsu6111 { - tsu6111_codina_default: tsu6111_codina { - codina_cfg1 { - /* GPIO95 used for IRQ */ - pins = "GPIO95_E8"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - nfc { - pn544_codina_default: pn544_codina { - /* Interrupt line */ - codina_cfg1 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_nopull>; - }; - /* Enable and firmware GPIOs */ - codina_cfg2 { - pins = "GPIO31_V3", "GPIO88_C4"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - bcm4751 { - bcm4751_codina_default: bcm4751_codina { - /* Reset line, start out asserted */ - codina_cfg1 { - pins = "GPIO21_AB3"; - ste,config = <&gpio_out_lo>; - }; - /* GPS_ON_OFF, start out deasserted (off) */ - codina_cfg2 { - pins = "GPIO86_C6"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - vibrator { - vibrator_default: vibrator_default { - codina_cfg1 { - pins = "GPIO195_AG28"; /* MOT_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - mcde { - dpi_default_mode: dpi_default { - default_mux1 { - /* Mux in all the data lines */ - function = "lcd"; - groups = - /* Data lines D0-D7 GPIO70..GPIO77 */ - "lcd_d0_d7_a_1", - /* Data lines D8-D11 GPIO78..GPIO81 */ - "lcd_d8_d11_a_1", - /* Data lines D12-D15 GPIO82..GPIO85 */ - "lcd_d12_d15_a_1", - /* Data lines D16-D23 GPIO161..GPIO168 */ - "lcd_d16_d23_b_1"; - }; - default_mux2 { - function = "lcda"; - /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ - groups = "lcdaclk_b_1", "lcda_b_1"; - }; - /* Input, no pull-up is the default state for pins used for an alt function */ - default_cfg1 { - pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; - ste,config = <&in_nopull>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts deleted file mode 100644 index b21e40da3dfd..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ /dev/null @@ -1,887 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Devicetree for the Samsung Galaxy Beam GT-I8530 also known as Gavini. - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-ab8500.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "Samsung Galaxy Beam (GT-I8530)"; - compatible = "samsung,gavini", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb585157lu"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - /* TI TXS0206 level translator for 2.9 V */ - sd_level_translator: regulator-gpio { - compatible = "regulator-fixed"; - - /* GPIO193 EN */ - gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - - startup-delay-us = <200>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ - ldo_3v3_reg: regulator-gpio-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VMEM_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; // FIXME - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_ldo_en_default_mode>; - }; - - /* - * External Ricoh "TSP" regulator for the touchscreen. - * One GPIO line controls two voltages of 3.3V and 1.8V - * this line is known as "TSP_LDO_ON1" in the schematics. - */ - ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "LDO_TSP_A3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* GPIO94 controls this regulator */ - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_en_default_mode>; - }; - ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_TSP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO94 controls this regulator */ - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_en_default_mode>; - }; - - /* - * External Ricoh RP152L010B-TR LCD LDO regulator for the display. - * LCD_PWR_EN controls both a 3.0V and 1.8V output. - */ - lcd_3v0_reg: regulator-gpio-lcd-3v0 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* GPIO219 controls this regulator */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - lcd_1v8_reg: regulator-gpio-lcd-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO219 controls this regulator too */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - - /* - * This regulator is a GPIO line that drives the Broadcom WLAN - * line WL_REG_ON high and enables the internal regulators - * inside the chip. Unfortunatley it is erroneously named - * WLAN_RST_N on the schematic but it is not a reset line. - * - * The voltage specified here is only used to determine the OCR mask, - * the for the SDIO connector, the chip is actually connected - * directly to VBAT. - */ - wl_reg: regulator-gpio-wlan { - compatible = "regulator-fixed"; - regulator-name = "WL_REG_ON"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - startup-delay-us = <100000>; - /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_ldo_en_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default_mode>; - - button-projector { - linux,code = ; - label = "Projector"; - /* GPIO32 "Projector On HotKey" */ - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - button-home { - linux,code = ; - label = "HOME"; - /* GPIO91 */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - }; - button-volup { - linux,code = ; - label = "VOL+"; - /* GPIO67 */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - button-voldown { - linux,code = ; - label = "VOL-"; - /* GPIO92 */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds_default_mode>; - used-led { - label = "touchkeys"; - /* GPIO68 */ - gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - ktd259: backlight { - compatible = "kinetic,ktd259"; - /* GPIO20 */ - enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - /* Default to 13/32 brightness */ - default-brightness = <13>; - pinctrl-names = "default"; - pinctrl-0 = <&ktd259_backlight_default_mode>; - }; - - /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - /* Yamaha YAS530 magnetometer */ - magnetometer@2e { - compatible = "yamaha,yas530"; - reg = <0x2e>; - /* VDD 3V */ - vdd-supply = <&ab8500_ldo_aux1_reg>; - /* IOVDD 1.8V */ - iovdd-supply = <&ab8500_ldo_aux2_reg>; - /* GPIO204 COMPASS_RST_N */ - reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&yas530_default>; - }; - /* TODO: this should also be used by the NCP6914 Camera power management unit */ - }; - - /* - * TODO: See if we can use the PL023 for this instead. - */ - spi { - compatible = "spi-gpio"; - /* Clock on GPIO220, pin SCL */ - sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; - /* MOSI on GPIO224, pin SDI "slave data in" */ - mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - /* MISO on GPIO225, pin SDO "slave data out" */ - miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - /* Chip select on GPIO223 */ - cs-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - panel@0 { - compatible = "samsung,lms397kf04"; - /* 300 ns at read cycle -> 3 MHz max speed */ - //spi-max-frequency = <3000000>; - spi-max-frequency = <1200000>; - /* TYPE 3: inverse clock polarity and phase */ - spi-cpha; - spi-cpol; - - reg = <0>; - vci-supply = <&lcd_3v0_reg>; - vccio-supply = <&lcd_1v8_reg>; - /* Reset on GPIO139 */ - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_default_mode>; - backlight = <&ktd259>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - }; - - /* Bit-banged I2C on GPIO201 and GPIO202 also called "MOT_I2C" */ - i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio6 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio6 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_2_default>; - #address-cells = <1>; - #size-cells = <0>; - /* TODO: add the Immersion ISA1200 I2C device here */ - }; - - /* Bit-banged I2C on GPIO196 and GPIO197 also called "MPR_I2C" */ - i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio6 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio6 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_3_default>; - #address-cells = <1>; - #size-cells = <0>; - /* TODO: add the DPP2601 projector I2C device 0x1b here */ - }; - - soc { - /* External Micro SD slot */ - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-pin-fbclk; - full-pwr-cycle; - /* MMC is powered by AUX3 1.2V .. 2.91V */ - vmmc-supply = <&ab8500_ldo_aux3_reg>; - /* 2.9 V level translator */ - vqmmc-supply = <&sd_level_translator>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_2_default>; - pinctrl-1 = <&mc0_a_2_sleep>; - /* "flash detect" actually card detect */ - cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - /* WLAN SDIO channel */ - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - non-removable; - cap-sd-highspeed; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - /* - * GPIO-controlled voltage enablement: this drives - * the WL_REG_ON line high when we use this device. - * Represented as regulator to fill OCR mask. - */ - vmmc-supply = <&wl_reg>; - - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - /* GPIO216 WL_HOST_WAKE */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_mode>; - }; - }; - - /* eMMC */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - vmmc-supply = <&ldo_3v3_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - status = "okay"; - }; - - /* GBF (Bluetooth) UART */ - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - /* BT_WAKE on GPIO199 */ - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - /* BT_HOST_WAKE on GPIO97 */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - /* BT_RST_N on GPIO209 */ - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_mode>; - }; - }; - - /* GPS UART */ - serial@80121000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - /* CTS/RTS is not used, CTS is repurposed as GPIO */ - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ - }; - - /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - serial@80007000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - prcmu@80157000 { - ab8500 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <43000>; - }; - - regulator { - ab8500_ldo_aux1 { - /* Used for VDD for sensors */ - regulator-name = "V-SENSORS-VDD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux2 { - /* Used for VIO for sensors */ - regulator-name = "V-SENSORS-VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux3 { - /* Used for voltage for external MMC/SD card */ - regulator-name = "V-MMC-SD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2910000>; - }; - }; - }; - }; - - /* I2C0 */ - i2c@80004000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - /* FIXME: fix the proximity sensor bindings and driver */ - proximity@39 { - /* Gavini has the GP2A030S00F proximity sensor */ - compatible = "sharp,gp2a030s00f"; - clock-frequency = <400000>; - reg = <0x39>; - /* FIXME: GPIO146 provides power on, IR LED? */ - }; - - gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - /* GPIO226 interrupt */ - interrupt-parent = <&gpio7>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "1"; - vlogic-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - pinctrl-names = "default"; - pinctrl-0 = <&mpu3050_default>; - - /* - * The MPU-3050 acts as a hub for the - * accelerometer. - */ - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - /* Bosch BMA222E accelerometer */ - accelerometer@18 { - compatible = "bosch,bma222e"; - reg = <0x18>; - mount-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - }; - }; - }; - }; - - /* I2C2 "AGC I2C" */ - i2c@80128000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_1_default>; - pinctrl-1 = <&i2c2_b_1_sleep>; - - /* Texas Instruments TSU6111 micro USB switch */ - usb-switch@25 { - compatible = "ti,tsu6111"; - reg = <0x25>; - /* Interrupt JACK_INT_N on GPIO95 */ - interrupt-parent = <&gpio2>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&tsu6111_default>; - }; - }; - - /* I2C3 */ - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - /* Melfas MMS136 touchscreen */ - touchscreen@48 { - compatible = "melfas,mms136"; - reg = <0x48>; - /* GPIO218 (TSP_INT_1V8) */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - /* AVDD is "analog supply", 2.57-3.47 V */ - avdd-supply = <&ldo_tsp_3v3_reg>; - /* VDD is "digital supply" 1.71-3.47V */ - vdd-supply = <&ldo_tsp_1v8_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dpi_default_mode>; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&pinctrl { - /* - * This extends the MC0_A_2 default config to include - * the card detect GPIO217 line. - */ - sdi0 { - mc0_a_2_default { - default_cfg4 { - pins = "GPIO217_AH12"; /* card detect */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - mcde { - dpi_default_mode: dpi_default { - default_mux1 { - /* Mux in all the data lines */ - function = "lcd"; - groups = - /* Data lines D0-D7 GPIO70..GPIO77 */ - "lcd_d0_d7_a_1", - /* Data lines D8-D11 GPIO78..GPIO81 */ - "lcd_d8_d11_a_1", - /* Data lines D12-D15 GPIO82..GPIO85 */ - "lcd_d12_d15_a_1", - /* Data lines D16-D23 GPIO161..GPIO168 */ - "lcd_d16_d23_b_1"; - }; - default_mux2 { - function = "lcda"; - /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ - groups = "lcdaclk_b_1", "lcda_b_1"; - }; - /* Input, no pull-up is the default state for pins used for an alt function */ - default_cfg1 { - pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; - ste,config = <&in_nopull>; - }; - }; - }; - /* GPIO for panel reset control */ - panel { - panel_default_mode: panel_default { - gavini_cfg1 { - /* Reset line */ - pins = "GPIO139_C9"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the eMMC */ - emmc-ldo { - emmc_ldo_en_default_mode: emmc_ldo_default { - /* LDO enable on GPIO6 */ - gavini_cfg1 { - pins = "GPIO6_AF6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the touchscreen */ - tsp-ldo { - tsp_ldo_en_default_mode: tsp_ldo_default { - /* LDO enable on GPIO94 */ - gavini_cfg1 { - pins = "GPIO94_D7"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* Reset line for the Yamaha YAS530 magnetometer */ - yas530 { - yas530_default: yas530_janice { - janice_cfg1 { - pins = "GPIO204_AF23"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* Flash and torch */ - flash { - gpio_flash_default_mode: flash_default { - janice_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the key LED */ - gpio-leds { - gpio_leds_default_mode: gpio_leds_default { - /* EN_LED_LDO on GPIO68 */ - gavini_cfg1 { - pins = "GPIO68_E1"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - backlight { - ktd259_backlight_default_mode: backlight_default { - skomer_cfg1 { - pins = "GPIO20_AB4"; /* LCD_BL_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the touchkeys */ - touchkey-ldo { - tsp_ldo_on2_default_mode: tsp_ldo_on2_default { - /* TSP_LDO_ON2 on GPIO89 */ - gavini_cfg1 { - pins = "GPIO89_E6"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - touchkey { - touchkey_default_mode: touchkey_default { - gavini_cfg1 { - /* Interrupt */ - pins = "GPIO198_AG25"; - ste,config = <&gpio_in_nopull>; - }; - gavini_cfg2 { - /* Reset, actually completely unused (not routed) */ - pins = "GPIO205_AG23"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the LCD display */ - lcd-ldo { - lcd_pwr_en_default_mode: lcd_pwr_en_default { - /* LCD_PWR_EN on GPIO219 */ - gavini_cfg1 { - pins = "GPIO219_AG10"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the WLAN internal LDO regulators */ - wlan-ldo { - wlan_ldo_en_default: wlan_ldo_default { - /* GPIO215 named WLAN_RST_N */ - gavini_cfg1 { - pins = "GPIO215_AH13"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the 2.9V SD card level translator */ - sd-level-translator { - sd_level_translator_default: sd_level_translator_default { - /* level shifter on GPIO193 */ - skomer_cfg1 { - pins = "GPIO193_AH27"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO keys */ - gpio-keys { - gpio_keys_default_mode: gpio_keys_default { - skomer_cfg1 { - pins = "GPIO32_V2", /* Projector On HotKey */ - "GPIO67_G2", /* VOL UP */ - "GPIO91_B6", /* HOME */ - "GPIO92_D6"; /* VOL DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - /* Interrupt line for the Atmel MXT228 touchscreen */ - tsp { - tsp_default: tsp_default { - gavini_cfg1 { - pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* Interrupt line for Invensense MPU3050 gyroscope */ - mpu3050 { - mpu3050_default: mpu3050 { - gavini_cfg1 { - /* GPIO226 used for IRQ */ - pins = "GPIO226_AF8"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for magnetometer and NCP6914 */ - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - gavini_cfg1 { - pins = "GPIO143_D12", "GPIO144_B13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the Immersion ISA1200 */ - i2c-gpio-2 { - i2c_gpio_2_default: i2c_gpio_2 { - gavini_cfg1 { - pins = "GPIO201_AF24", "GPIO202_AF25"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the TI DPP2601 */ - i2c-gpio-3 { - i2c_gpio_3_default: i2c_gpio_3 { - gavini_cfg1 { - pins = "GPIO196_AG26", "GPIO197_AH24"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based SPI bus for the display */ - spi-gpio-0 { - spi_gpio_0_default: spi_gpio_0_d { - gavini_cfg1 { - pins = "GPIO220_AH10", "GPIO223_AH9", "GPIO224_AG9"; - ste,config = <&gpio_out_hi>; - }; - gavini_cfg2 { - pins = "GPIO225_AG8"; - ste,config = <&gpio_in_nopull>; - }; - }; - spi_gpio_0_sleep: spi_gpio_0_s { - gavini_cfg1 { - pins = "GPIO220_AH10", "GPIO223_AH9", - "GPIO224_AG9", "GPIO225_AG8"; - ste,config = <&gpio_out_hi>; - }; - gavini_cfg2 { - pins = "GPIO225_AG8"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - wlan { - wlan_default_mode: wlan_default { - /* GPIO216 for WL_HOST_WAKE */ - gavini_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - bluetooth { - bluetooth_default_mode: bluetooth_default { - /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ - gavini_cfg1 { - pins = "GPIO199_AH23", "GPIO222_AJ9"; - ste,config = <&gpio_out_lo>; - }; - /* GPIO97 BT_HOST_WAKE */ - gavini_cfg2 { - pins = "GPIO97_D9"; - ste,config = <&gpio_in_nopull>; - }; - /* GPIO209 BT_RST_N */ - gavini_cfg3 { - pins = "GPIO209_AG15"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* Interrupt line for TI TSU6111 Micro USB switch */ - tsu6111 { - tsu6111_default: tsu6111 { - gavini_cfg1 { - /* GPIO95 used for IRQ */ - pins = "GPIO95_E8"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts deleted file mode 100644 index f736888474e7..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "ste-db8500.dtsi" -#include "ste-ab8505.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/* - * Note: This device tree cannot be booted directly with the Samsung bootloader. - * You need an intermediate, device-tree compatible bootloader - * that locks the L2 cache. Otherwise the kernel will crash after decompression. - * - * There is a port of (mainline) U-Boot, see - * https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500#U-Boot - */ -/ { - model = "Samsung Galaxy S III mini (GT-I8190)"; - compatible = "samsung,golden", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb-l1m7flu"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - - #address-cells = <1>; - #size-cells = <0>; - - touchkey@20 { - compatible = "coreriver,tc360-touchkey"; - reg = <0x20>; - vdd-supply = <&ab8500_ldo_aux4_reg>; - vcc-supply = <&ab8500_ldo_aux6_reg>; - - interrupt-parent = <&gpio2>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_default>; - linux,keycodes = ; - }; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_1_default>; - - #address-cells = <1>; - #size-cells = <0>; - - magnetometer@c { - compatible = "alps,hscdtd008a"; - reg = <0x0c>; - - avdd-supply = <&ab8500_ldo_aux1_reg>; - dvdd-supply = <&ab8500_ldo_aux8_reg>; - }; - }; - - soc { - /* External Micro SD card slot */ - mmc@80126000 { - status = "okay"; - - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - non-removable; - /* - * Unfortunately, there is no way to enable the UHS - * modes due to a limitation of the SD level translator: - * It will either translate to 2.9V or disconnect the - * DATA lines, so switching to 1.8V signal voltage fails. - */ - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-pin-fbclk; - full-pwr-cycle; - - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&sd_level_translator>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_2_default>; - pinctrl-1 = <&mc0_a_2_sleep>; - }; - - /* WLAN SDIO */ - mmc@80118000 { - status = "okay"; - - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - - non-removable; - cap-sd-highspeed; - - vmmc-supply = <&wl_reg_on>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - /* GPIO216 (WLAN_HOST_WAKE) */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default>; - }; - }; - - /* eMMC */ - mmc@80005000 { - status = "okay"; - - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - - vmmc-supply = <&vmem_3v3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - }; - - /* BT UART */ - serial@80120000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - - bluetooth { - /* BCM4334B0 actually */ - compatible = "brcm,bcm4330-bt"; - /* GPIO222 (BT_VREG_ON) */ - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - /* GPIO199 (BT_WAKE) */ - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - /* GPIO97 (BT_HOST_WAKE) */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default>; - }; - }; - - /* GPF UART */ - serial@80121000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; - }; - - /* Debugging console UART */ - serial@80007000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - i2c@80004000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - proximity@44 { - compatible = "sharp,gp2ap002s00f"; - reg = <0x44>; - - /* GPIO146 (PS_INT) */ - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - - vdd-supply = <&ab8500_ldo_aux1_reg>; - vio-supply = <&ab8500_ldo_aux8_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&proximity_default>; - - sharp,proximity-far-hysteresis = <0x40>; - sharp,proximity-close-hysteresis = <0x0f>; - }; - }; - - i2c@80128000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - imu@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - - /* GPIO206 (ACC_INT) */ - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_EDGE_RISING>; - - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; - - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&ab8500_ldo_aux8_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&imu_default>; - }; - }; - - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - - /* GPIO218 (TSP_INT_1V8) */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - - /* VDDA is "analog supply", 2.57-3.47 V */ - vdda-supply = <&ab8500_ldo_aux2_reg>; - /* VDD is "digital supply" 1.71-3.47V */ - vdd-supply = <&ab8500_ldo_aux5_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - }; - - prcmu@80157000 { - ab8505 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <36000>; - }; - - regulator { - ab8500_ldo_aux1 { - regulator-name = "sensor_3v"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux2 { - regulator-name = "vreg_tsp_a3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux3 { - regulator-name = "vdd_tf_2v91"; - }; - - ab8500_ldo_aux4 { - regulator-name = "key_led_3.3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux5 { - regulator-name = "vreg_tsp_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux6 { - regulator-name = "touch_key_2.2v"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - ab8500_ldo_aux8 { - regulator-name = "sensor_1v8"; - }; - }; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dsi_default_mode>; - - dsi@a0351000 { - panel@0 { - compatible = "samsung,s6e63m0"; - reg = <0>; - max-brightness = <15>; - vdd3-supply = <&panel_reg_3v0>; - vci-supply = <&panel_reg_1v8>; - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - /* ESD (electrostatic discharge) detection interrupt */ - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "esd"; - pinctrl-names = "default"; - pinctrl-0 = <&display_default_mode>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - volume-up { - label = "Volume Up"; - /* GPIO67 (VOL_UP) */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - /* GPIO92 (VOL_DOWN) */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - /* GPIO91 (HOME_KEY) */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - vibrator { - compatible = "gpio-vibrator"; - /* GPIO195 (MOT_EN) */ - enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_default>; - }; - - /* External LDO for eMMC */ - vmem_3v3: regulator-vmem { - compatible = "regulator-fixed"; - - regulator-name = "vmem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - startup-delay-us = <200>; - - /* GPIO223 (MEM_LDO_EN) */ - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&mem_ldo_default>; - }; - - /* TI TXS0206-29 level translator for 2.9 V */ - sd_level_translator: regulator-sd-level-translator { - compatible = "regulator-fixed"; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - - startup-delay-us = <200>; - - /* GPIO87 (TXS0206-29_EN) */ - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* - * WL_REG_ON takes WLAN out of reset and enables the internal regulators. - * The voltage specified here is only used to determine the OCR mask, - * the BCM chip is actually connected directly to VBAT. - */ - wl_reg_on: regulator-wl-reg-on { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg-on"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - startup-delay-us = <100000>; - - /* GPIO215 (WLAN_EN) */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_default>; - }; - - /* MIC5366 GPIO-controlled regulator */ - panel_reg_1v8: regulator-panel-1v8 { - compatible = "regulator-fixed"; - - regulator-name = "panel-fixed-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO219 */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - - startup-delay-us = <200>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_reg_default_mode>; - }; - - /* MIC5366 GPIO-controlled regulator */ - panel_reg_3v0: regulator-panel-3v0 { - compatible = "regulator-fixed"; - - regulator-name = "panel-fixed-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* GPIO219 */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - - startup-delay-us = <200>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_reg_default_mode>; - }; -}; - -&pinctrl { - gpio-keys { - gpio_keys_default: gpio_keys_default { - golden_cfg1 { - pins = "GPIO67", /* VOL_UP */ - "GPIO91", /* HOME_KEY */ - "GPIO92"; /* VOL_DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - golden_cfg1 { - pins = "GPIO77", /* TOUCHKEY_SCL */ - "GPIO78"; /* TOUCHKEY_SDA */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - flash { - gpio_flash_default_mode: flash_default { - golden_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - - i2c-gpio-1 { - i2c_gpio_1_default: i2c_gpio_1 { - golden_cfg1 { - pins = "GPIO151", /* COMP_SCL */ - "GPIO152"; /* COMP_SDA */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - touchkey { - touchkey_default: touchkey_default { - golden_cfg1 { - pins = "GPIO79"; /* TOUCHKEY_INT */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - sdi0 { - sd_level_translator_default: sd_level_translator_default { - golden_cfg1 { - pins = "GPIO87_B3"; /* TXS0206-29_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - - sdi2 { - mem_ldo_default: mem_ldo_default { - golden_cfg1 { - pins = "GPIO223_AH9"; /* MEM_LDO_EN */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - - mcde { - dsi_default_mode: dsi_default { - default_mux1 { - /* Mux in VSI0 used for DSI TE */ - function = "lcd"; - groups = - "lcdvsi0_a_1"; /* VSI0 for LCD */ - }; - default_cfg1 { - pins = - "GPIO68_E1"; /* VSI0 */ - ste,config = <&in_nopull>; - }; - }; - }; - - display { - display_default_mode: display_default { - golden_cfg1 { - pins = "GPIO139_C9"; /* MIPI_DSI0_RESET_N */ - ste,config = <&gpio_out_lo>; - }; - golden_cfg2 { - pins = "GPIO82_C1"; /* LDI_ESD_DET */ - ste,config = <&gpio_in_pu>; - }; - }; - panel_reg_default_mode: panel_reg_default { - golden_cfg1 { - pins = "GPIO219_AG10"; /* LCD_PWR_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - - proximity { - proximity_default: proximity_default { - golden_cfg1 { - pins = "GPIO146_D13"; /* PS_INT */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - imu { - imu_default: imu_default { - golden_cfg1 { - pins = "GPIO206_AG24"; /* ACC_INT */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - - tsp { - tsp_default: tsp_default { - golden_cfg1 { - pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - wlan { - wlan_default: wlan_default { - golden_cfg1 { - pins = "GPIO216_AG12"; /* WLAN_HOST_WAKE */ - ste,config = <&gpio_in_pd>; - }; - }; - - wlan_en_default: wlan_en_default { - golden_cfg1 { - pins = "GPIO215_AH13"; /* WLAN_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - - bluetooth { - bluetooth_default: bluetooth_default { - golden_cfg1 { - pins = "GPIO199_AH23", /* BT_WAKE */ - "GPIO222_AJ9"; /* BT_VREG_ON */ - ste,config = <&gpio_out_lo>; - }; - golden_cfg2 { - pins = "GPIO97_D9"; /* BT_HOST_WAKE */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - vibrator { - vibrator_default: vibrator_default { - golden_cfg1 { - pins = "GPIO195_AG28"; /* MOT_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; -}; - -&ab8505_gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio_default>; - - gpio { - gpio_default: gpio_default { - golden_mux { - /* Change unused pins to GPIO mode */ - function = "gpio"; - groups = "gpio3_a_1", /* default: SysClkReq4 */ - "gpio14_a_1"; /* default: PWMOut1 */ - }; - golden_cfg1 { - pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; - bias-disable; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts deleted file mode 100644 index 6e586e875565..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ /dev/null @@ -1,998 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Devicetree for the Samsung Galaxy S Advance GT-I9070 also known as Janice. - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-ab8500.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "Samsung Galaxy S Advance (GT-I9070)"; - compatible = "samsung,janice", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb535151vu"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ - ldo_3v3_reg: regulator-gpio-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VMEM_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; // FIXME - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_ldo_en_default_mode>; - }; - - /* - * External Ricoh "TSP" regulator for the touchscreen. - * One GPIO line controls two voltages of 3.3V and 1.8V - * this line is known as "TSP_LDO_ON1" in the schematics. - */ - ldo_tsp_3v3_reg: regulator-gpio-tsp-ldo-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "LDO_TSP_A3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* GPIO94 controls this regulator */ - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_en_default_mode>; - }; - ldo_tsp_1v8_reg: regulator-gpio-tsp-ldo-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_TSP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO94 controls this regulator */ - gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_en_default_mode>; - }; - - /* - * External Ricoh "TSP" regulator for the touchkeys. - * Two GPIO lines controls two voltages of 3.3V and 1.8V - * TSP_LDO_ON2 controls VREG_TOUCHKEY_1V8 - * EN_LED_LDO controls VREG_KLED_3V3 (key LED) - */ - ldo_kled_3v3_reg: regulator-gpio-vreg-kled-3v3 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_KLED_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* GPIO68 controls this regulator */ - gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_led_ldo_default_mode>; - }; - ldo_touchkey_1v8_reg: regulator-gpio-vreg-touchkey-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_TOUCHKEY_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO89 controls this regulator */ - gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - /* 70 ms power-on delay */ - startup-delay-us = <70000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_ldo_on2_default_mode>; - }; - - - /* - * External Ricoh RP152L010B-TR LCD LDO regulator for the display. - * LCD_PWR_EN controls a 3.0V and 1.8V output. - */ - lcd_3v0_reg: regulator-gpio-lcd-3v0 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* GPIO219 controls this regulator */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - lcd_1v8_reg: regulator-gpio-lcd-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO219 controls this regulator */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - - /* - * This regulator is a GPIO line that drives the Broadcom WLAN - * line WL_REG_ON high and enables the internal regulators - * inside the chip. Unfortunatley it is erroneously named - * WLAN_RST_N on the schematic but it is not a reset line. - * - * The voltage specified here is only used to determine the OCR mask, - * the for the SDIO connector, the chip is actually connected - * directly to VBAT. - */ - wl_reg: regulator-gpio-wlan { - compatible = "regulator-fixed"; - regulator-name = "WL_REG_ON"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - startup-delay-us = <100000>; - /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_ldo_en_default>; - }; - - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default_mode>; - - button-home { - linux,code = ; - label = "HOME"; - /* GPIO91 */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - }; - button-volup { - linux,code = ; - label = "VOL+"; - /* GPIO67 */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - button-voldown { - linux,code = ; - label = "VOL-"; - /* GPIO92 */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - /* Yamaha YAS530 magnetometer */ - magnetometer@2e { - compatible = "yamaha,yas530"; - reg = <0x2e>; - /* VDD 3V */ - vdd-supply = <&ab8500_ldo_aux1_reg>; - /* IOVDD 1.8V */ - iovdd-supply = <&ab8500_ldo_aux2_reg>; - /* GPIO204 COMPASS_RST_N */ - reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&yas529_default>; - }; - /* TODO: this should also be used by the NCP6914 Camera power management unit */ - }; - - /* - * These pins do have an spi controller, however the controller on - * these pins is not the fully featured PL022 SSP/SPI block but the - * ST Micro diet "PL023" version. One of the lacking features in - * this derivative is 3wire support, so it cannot be used to drive - * this panel interface. We have to use GPIO bit-banging instead. - */ - spi { - compatible = "spi-gpio"; - /* Clock on GPIO220 */ - sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; - /* MISO/MOSI on GPIO224 (no separate MISO pin) */ - mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - /* Chip select on GPIO223 */ - cs-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - - panel@0 { - compatible = "samsung,s6e63m0"; - reg = <0>; - vdd3-supply = <&lcd_3v0_reg>; - vci-supply = <&lcd_1v8_reg>; - /* Reset on GPIO139 */ - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_default_mode>; - spi-3wire; - /* TYPE 3: inverse clock polarity and phase */ - spi-cpha; - spi-cpol; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - }; - - /* - * Current sense amplifier on the light sensor to convert current to - * voltage. We do not know if this is the actual configuration. The - * sense resistor value was found by calibrating in a room ambient - * light with a second mobile phone light sensor as reference. If you - * pry a Janice phone apart and inspect it you may figure this out. - */ - gp2a_shunt: current-sense-shunt { - compatible = "current-sense-shunt"; - io-channels = <&gpadc 0x07>; - shunt-resistor-micro-ohms = <15000000>; /* 15 ohms c:a */ - #io-channel-cells = <0>; - io-channel-ranges; - }; - - /* Bit-banged I2C on GPIO196 and GPIO197 also called "TOUCHKEY_I2C" */ - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio6 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio6 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_1_default>; - #address-cells = <1>; - #size-cells = <0>; - - touchkey@20 { - compatible = "coreriver,tc360-touchkey"; - reg = <0x20>; - vdd-supply = <&ldo_kled_3v3_reg>; - vcc-supply = <&ldo_touchkey_1v8_reg>; - vddio-supply = <&ldo_touchkey_1v8_reg>; - - /* Interrupt on GPIO 198 */ - interrupt-parent = <&gpio6>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_default_mode>; - linux,keycodes = ; - }; - }; - - /* Bit-banged I2C on GPIO201 and GPIO202 also called "MOT_I2C" */ - i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio6 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio6 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_2_default>; - #address-cells = <1>; - #size-cells = <0>; - /* TODO: add the Immersion ISA1200 I2C device here */ - }; - - /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC_I2C" */ - i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_3_default>; - #address-cells = <1>; - #size-cells = <0>; - - /* This is only mounted on the GT-I9070P */ - nfc@2b { /* 0x30? */ - /* NXP NFC circuit PN544 C1 marked NXP 44501 */ - compatible = "nxp,pn544-i2c"; - /* IF0, IF1 high, gives I2C address 0x2B */ - reg = <0x2b>; - clock-frequency = <400000>; - /* NFC IRQ on GPIO32 */ - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - /* GPIO 31 */ - firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - /* GPIO88 */ - enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pn544_janice_default>; - }; - }; - - soc { - /* External Micro SD slot */ - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-dir-cmd; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-pin-fbclk; - full-pwr-cycle; - /* MMC is powered by AUX3 1.2V .. 2.91V */ - vmmc-supply = <&ab8500_ldo_aux3_reg>; - /* 2.9 V level translator is using AUX3 at 2.9 V as well */ - vqmmc-supply = <&ab8500_ldo_aux3_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_2_default>; - pinctrl-1 = <&mc0_a_2_sleep>; - cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 - status = "okay"; - }; - - /* WLAN SDIO channel */ - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - non-removable; - cap-sd-highspeed; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - /* - * GPIO-controlled voltage enablement: this drives - * the WL_REG_ON line high when we use this device. - * Represented as regulator to fill OCR mask. - */ - vmmc-supply = <&wl_reg>; - - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - /* GPIO216 WL_HOST_WAKE */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_mode>; - }; - }; - - /* eMMC */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - vmmc-supply = <&ldo_3v3_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - status = "okay"; - }; - - /* GBF (Bluetooth) UART */ - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - - bluetooth { - /* BCM4330B1 actually */ - compatible = "brcm,bcm4330-bt"; - /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - /* BT_WAKE on GPIO199 */ - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - /* BT_HOST_WAKE on GPIO97 */ - /* FIXME: convert to interrupt */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - /* BT_RST_N on GPIO209 */ - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_mode>; - }; - }; - - /* GPS UART */ - serial@80121000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - /* CTS/RTS is not used, CTS is repurposed as GPIO */ - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - - gnss { - /* - * The Low Noise Amplifier (LNA) power and enablement is controlled - * autonomously by the GSD4t. - * Janice has a SiRFstarIV-based GSD4t - * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R. - */ - compatible = "csr,gsd4t"; - /* GPS_RSTN on GPIO21 */ - reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - /* GPS_ON_OFF on GPIO96 */ - sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - /* GPS_1V8 (VSMPS2) */ - vcc-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gsd4t_janice_default>; - /* According to /etc/sirfgps.conf */ - current-speed = <460800>; - }; - }; - - /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - serial@80007000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - prcmu@80157000 { - ab8500 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <15000>; - }; - - regulator { - ab8500_ldo_aux1 { - /* Used for VDD for sensors */ - regulator-name = "V-SENSORS-VDD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux2 { - /* Used for VIO for sensors */ - regulator-name = "V-SENSORS-VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux3 { - /* Used for voltage for external MMC/SD card */ - regulator-name = "V-MMC-SD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2910000>; - }; - }; - }; - }; - - /* I2C0 */ - i2c@80004000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - proximity@44 { - /* Janice has the GP2AP002A00F with light sensor */ - compatible = "sharp,gp2ap002a00f"; - clock-frequency = <400000>; - reg = <0x44>; - - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vio-supply = <&ab8500_ldo_aux2_reg>; - /* ADC channel AUX2 to read ALSOUT ambient light sensor out */ - io-channels = <&gp2a_shunt>; - io-channel-names = "alsout"; - pinctrl-names = "default"; - pinctrl-0 = <&gp2ap002_janice_default>; - /* B1 mode (arch/arm/mach-ux500/include/mach/gp2a.h) */ - sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; - sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; - }; - }; - - /* I2C1 on GPIO16 and GPIO17 also called "MUS I2C" */ - i2c@80122000 { - status = "okay"; - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_b_2_default>; - pinctrl-1 = <&i2c1_b_2_sleep>; - - /* Texas Instruments TSU6111 micro USB switch */ - usb-switch@25 { - compatible = "ti,tsu6111"; - reg = <0x25>; - /* Interrupt JACK_INT_N on GPIO95 */ - interrupt-parent = <&gpio2>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&tsu6111_janice_default>; - }; - }; - - /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ - i2c@80128000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - /* GPIO226 interrupt */ - interrupt-parent = <&gpio7>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - /* FIXME: no idea about this */ - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "1"; - vlogic-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - pinctrl-names = "default"; - pinctrl-0 = <&mpu3050_janice_default>; - - /* - * The MPU-3050 acts as a hub for the - * accelerometer. - */ - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - /* Bosch BMA222 accelerometer */ - accelerometer@8 { - compatible = "bosch,bma222"; - reg = <0x08>; - mount-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V - }; - }; - }; - }; - - /* I2C3 */ - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - /* Atmel mXT224E touchscreen */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - /* GPIO218 (TSP_INT_1V8) */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - /* VDDA is "analog supply", 2.57-3.47 V */ - vdda-supply = <&ldo_tsp_3v3_reg>; - /* VDD is "digital supply" 1.71-3.47V */ - vdd-supply = <&ldo_tsp_1v8_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dpi_default_mode>; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&pinctrl { - /* - * This extends the MC0_A_2 default config to include - * the card detect GPIO217 line. - */ - sdi0 { - mc0_a_2_default { - default_cfg4 { - pins = "GPIO217_AH12"; /* card detect */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - mcde { - dpi_default_mode: dpi_default { - default_mux1 { - /* Mux in all the data lines */ - function = "lcd"; - groups = - /* Data lines D0-D7 GPIO70..GPIO77 */ - "lcd_d0_d7_a_1", - /* Data lines D8-D11 GPIO78..GPIO81 */ - "lcd_d8_d11_a_1", - /* Data lines D12-D15 GPIO82..GPIO85 */ - "lcd_d12_d15_a_1", - /* Data lines D16-D23 GPIO161..GPIO168 */ - "lcd_d16_d23_b_1"; - }; - default_mux2 { - function = "lcda"; - /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ - groups = "lcdaclk_b_1", "lcda_b_1"; - }; - /* Input, no pull-up is the default state for pins used for an alt function */ - default_cfg1 { - pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; - ste,config = <&in_nopull>; - }; - }; - }; - /* GPIO for panel reset control */ - panel { - panel_default_mode: panel_default { - janice_cfg1 { - /* Reset line */ - pins = "GPIO139_C9"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the eMMC */ - emmc-ldo { - emmc_ldo_en_default_mode: emmc_ldo_default { - /* LDO enable on GPIO6 */ - janice_cfg1 { - pins = "GPIO6_AF6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the touchscreen */ - tsp-ldo { - tsp_ldo_en_default_mode: tsp_ldo_default { - /* LDO enable on GPIO94 */ - janice_cfg1 { - pins = "GPIO94_D7"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the key LED */ - key-led { - en_led_ldo_default_mode: en_led_ldo_default { - /* EN_LED_LDO on GPIO68 */ - janice_cfg1 { - pins = "GPIO68_E1"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the touchkeys */ - touchkey-ldo { - tsp_ldo_on2_default_mode: tsp_ldo_on2_default { - /* TSP_LDO_ON2 on GPIO89 */ - janice_cfg1 { - pins = "GPIO89_E6"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - touchkey { - touchkey_default_mode: touchkey_default { - janice_cfg1 { - /* Interrupt */ - pins = "GPIO198_AG25"; - ste,config = <&gpio_in_nopull>; - }; - janice_cfg2 { - /* Reset, actually completely unused (not routed) */ - pins = "GPIO205_AG23"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - /* GPIO that enabled the LDO regulator for the LCD display */ - lcd-ldo { - lcd_pwr_en_default_mode: lcd_pwr_en_default { - /* LCD_PWR_EN on GPIO219 */ - janice_cfg1 { - pins = "GPIO219_AG10"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the WLAN internal LDO regulators */ - wlan-ldo { - wlan_ldo_en_default: wlan_ldo_default { - /* GPIO215 named WLAN_RST_N */ - janice_cfg1 { - pins = "GPIO215_AH13"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Flash and torch */ - flash { - gpio_flash_default_mode: flash_default { - janice_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO keys */ - gpio-keys { - gpio_keys_default_mode: gpio_keys_default { - skomer_cfg1 { - pins = "GPIO67_G2", /* VOL UP */ - "GPIO91_B6", /* HOME */ - "GPIO92_D6"; /* VOL DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - /* Interrupt line for the Atmel MXT228 touchscreen */ - tsp { - tsp_default: tsp_default { - janice_cfg1 { - pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* Reset line for the Yamaha YAS529 magnetometer */ - yas529 { - yas529_default: yas529_janice { - janice_cfg1 { - pins = "GPIO204_AF23"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* Interrupt line for light/proximity sensor GP2AP002 */ - gp2ap002 { - gp2ap002_janice_default: gp2ap002_janice { - janice_cfg1 { - pins = "GPIO146_D13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* Interrupt line for Invensense MPU3050 gyroscope */ - mpu3050 { - mpu3050_janice_default: mpu3050_janice { - janice_cfg1 { - /* GPIO226 used for IRQ */ - pins = "GPIO226_AF8"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for magnetometer and NCP6914 */ - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - janice_cfg1 { - pins = "GPIO143_D12", "GPIO144_B13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the Cypress touchkeys */ - i2c-gpio-1 { - i2c_gpio_1_default: i2c_gpio_1 { - janice_cfg1 { - pins = "GPIO196_AG26", "GPIO197_AH24"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the Immersion ISA1200 */ - i2c-gpio-2 { - i2c_gpio_2_default: i2c_gpio_2 { - janice_cfg1 { - pins = "GPIO201_AF24", "GPIO202_AF25"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for the NFC */ - i2c-gpio-3 { - i2c_gpio_3_default: i2c_gpio_3 { - janice_cfg1 { - pins = "GPIO151_D17", "GPIO152_D16"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based SPI bus for the display */ - spi-gpio-0 { - spi_gpio_0_default: spi_gpio_0 { - janice_cfg1 { - pins = "GPIO220_AH10", "GPIO223_AH9", "GPIO224_AG9"; - ste,config = <&gpio_out_hi>; - }; - /* This pin is unused but belongs with this SPI block */ - janice_cfg2 { - pins = "GPIO225_AG8"; - ste,config = <&in_pd>; - }; - }; - }; - wlan { - wlan_default_mode: wlan_default { - /* GPIO216 for WL_HOST_WAKE */ - janice_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - bluetooth { - bluetooth_default_mode: bluetooth_default { - /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ - janice_cfg1 { - pins = "GPIO199_AH23", "GPIO222_AJ9"; - ste,config = <&gpio_out_lo>; - }; - /* GPIO97 BT_HOST_WAKE */ - janice_cfg2 { - pins = "GPIO97_D9"; - ste,config = <&gpio_in_nopull>; - }; - /* GPIO209 BT_RST_N */ - janice_cfg3 { - pins = "GPIO209_AG15"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* Interrupt line for TI TSU6111 Micro USB switch */ - tsu6111 { - tsu6111_janice_default: tsu6111_janice { - janice_cfg1 { - /* GPIO95 used for IRQ */ - pins = "GPIO95_E8"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - nfc { - pn544_janice_default: pn544_janice { - /* Interrupt line */ - janice_cfg1 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_nopull>; - }; - /* Enable and firmware GPIOs */ - janice_cfg2 { - pins = "GPIO31_V3", "GPIO88_C4"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - gsd4t { - gsd4t_janice_default: gsd4t_janice { - /* Reset line, start out asserted */ - janice_cfg1 { - pins = "GPIO21_AB3"; - ste,config = <&gpio_out_lo>; - }; - /* GPS_ON_OFF, start out deasserted (off) */ - janice_cfg2 { - pins = "GPIO96_D8"; - ste,config = <&gpio_out_lo>; - }; - /* Unused power enablement line, used in R0.0 and R0.1 boards */ - janice_cfg3 { - pins = "GPIO86_C6"; - ste,config = <&gpio_in_pd>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts deleted file mode 100644 index ba4421080b2a..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ /dev/null @@ -1,727 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Devicetree for the Samsung Galaxy Amp SGH-I407 also known as Kyle. - * - * The code also refers to "Kyle AT&T" reflecting that this mobile phone - * was customized for the AT&T subsidiary Aio Wireless (All In One) and - * offered by the company in 2013. - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-ab8505.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "Samsung Galaxy Amp (SGH-I407)"; - compatible = "samsung,kyle", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb425161la"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - /* TI TXS0206 level translator for 2.9 V */ - sd_level_translator: regulator-gpio { - compatible = "regulator-fixed"; - - /* GPIO87 EN */ - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - - startup-delay-us = <200>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* External LDO MIC5366-3.3YMT for eMMC */ - ldo_3v3_reg: regulator-gpio-ldo-3v3 { - compatible = "regulator-fixed"; - regulator-name = "en-3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_ldo_en_default_mode>; - }; - - /* - * External Ricoh RP152L010B-TR LCD LDO regulator for the display. - * LCD_PWR_EN controls both a 3.0V and 1.8V output. - */ - lcd_3v0_reg: regulator-gpio-lcd-3v0 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_3V0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* GPIO219 controls this regulator */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - lcd_1v8_reg: regulator-gpio-lcd-1v8 { - compatible = "regulator-fixed"; - /* Supplied in turn by VBAT */ - regulator-name = "VREG_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* GPIO219 controls this regulator too */ - gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwr_en_default_mode>; - }; - - wlan_en: regulator-gpio-wlan-en { - compatible = "regulator-fixed"; - regulator-name = "wl-reg-on"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - startup-delay-us = <200000>; - /* GPIO215 WLAN_EN */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_default_mode>; - }; - - vibrator { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default_mode>; - - button-home { - linux,code = ; - label = "HOME"; - /* GPIO91 */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - }; - button-volup { - linux,code = ; - label = "VOL+"; - /* GPIO67 */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - button-voldown { - linux,code = ; - label = "VOL-"; - /* GPIO92 */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - }; - - ktd253: backlight { - compatible = "kinetic,ktd253"; - /* GPIO 69 */ - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - /* Default to 13/32 brightness */ - default-brightness = <13>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_backlight_default_mode>; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - /* TODO: this should be used by the NCP6914 Camera power management unit */ - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_1_default>; - #address-cells = <1>; - #size-cells = <0>; - magnetometer@c { - compatible = "alps,hscdtd008a"; - reg = <0x0c>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - dvdd-supply = <&ab8500_ldo_aux6_reg>; - }; - }; - - soc { - // External Micro SD slot - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-pin-fbclk; - full-pwr-cycle; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&sd_level_translator>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_1_default>; - pinctrl-1 = <&mc0_a_1_sleep>; - cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 - status = "okay"; - }; - - // WLAN SDIO channel - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - non-removable; - cap-sd-highspeed; - vmmc-supply = <&wlan_en>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - /* GPIO216 WL_HOST_WAKE */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_mode>; - }; - }; - - /* - * eMMC seems to be mostly Samsung KLM4G1YE4C "4YMD1R" - */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - /* From datasheet page 26 figure 9: 300 ms set-up time for 4GB */ - post-power-on-delay-ms = <300>; - vmmc-supply = <&ldo_3v3_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - - status = "okay"; - }; - - /* GBF (Bluetooth) UART */ - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - - bluetooth { - /* BCM4334B0 actually */ - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_mode>; - }; - }; - - /* GPF UART */ - serial@80121000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; - - gnss { - /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ - compatible = "csr,csrg05ta03-icje-r"; - /* GPS_RSTN on GPIO21 */ - reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - /* GPS_ON_OFF on GPIO86 */ - sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - /* GPS_1V8 (VSMPS2) */ - vcc-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&g05ta03_kyle_default>; - /* According to /etc/sirfgps.conf */ - current-speed = <460800>; - }; - }; - - /* Debugging console UART connected to AB8505 USB */ - serial@80007000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - prcmu@80157000 { - ab8505 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <36000>; - }; - - regulator { - ab8500_ldo_aux1 { - /* Used for VDD for sensors */ - regulator-name = "AUX1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux2 { - /* Supplies the MMS touchscreen only with 3.3V */ - regulator-name = "AUX2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux3 { - /* Used for voltage for external MMC/SD card */ - regulator-name = "AUX3"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux4 { - regulator-name = "AUX4"; - /* Hammer to 3.3V for the touchscreen */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux5 { - regulator-name = "AUX5"; - /* 1.8V for the touchscreen */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux6 { - regulator-name = "AUX6"; - /* Used by sensors for 1.8 V in R0.1+ */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux8 { - /* Unused */ - regulator-name = "AUX8"; - }; - }; - }; - }; - - /* I2C0 */ - i2c@80004000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - proximity@44 { - compatible = "sharp,gp2ap002s00f"; - clock-frequency = <400000>; - reg = <0x44>; - - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vio-supply = <&ab8500_ldo_aux6_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gp2ap002_kyle_default>; - sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; - sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; - }; - }; - - /* I2C2 */ - i2c@80128000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - accel@18 { - compatible = "bosch,bma254"; - clock-frequency = <400000>; - reg = <0x18>; - - mount-matrix = "-1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&ab8500_ldo_aux6_reg>; - }; - }; - - /* I2C3 */ - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - /* Melfas MMS134S touchscreen */ - touchscreen@48 { - compatible = "melfas,mms134s"; - reg = <0x48>; - /* GPIO218 for IRQ */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - /* AVDD is "analog supply", 2.57-3.47 V */ - avdd-supply = <&ab8500_ldo_aux2_reg>; - /* VDD is "digital supply" 1.71-3.47V */ - vdd-supply = <&ab8500_ldo_aux5_reg>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - - pinctrl-names = "default"; - pinctrl-0 = <&mms134s_kyle_default>; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dsi_default_mode>; - - dsi@a0351000 { - panel { - /* - * NT35510-based Hydis HVA40WV1 - * Apparently some Kyle models can have a NT35512 fitted - * here instead. In that case the boot loader needs to - * modify this compatible. - */ - compatible = "hydis,hva40wv1", "novatek,nt35510"; - reg = <0>; - /* v_lcd_3v0 2.3-4.8V */ - vdd-supply = <&lcd_3v0_reg>; - /* v_lcd_1v8 1.65-3.3V */ - vddi-supply = <&lcd_1v8_reg>; - /* GPIO 139 */ - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&display_default_mode>; - backlight = <&ktd253>; - }; - }; - }; - }; -}; - -&pinctrl { - /* - * This extends the MC0_A_1 default config to include - * the card detect GPIO217 line. - */ - sdi0 { - mc0_a_1_default { - default_cfg1 { - /* GPIO18, 19 & 20 unused so pull down */ - ste,config = <&gpio_in_pd>; - }; - default_cfg4 { - pins = "GPIO217_AH12"; /* card detect */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - - mcde { - dsi_default_mode: dsi_default { - default_mux1 { - /* Mux in VSI0 used for DSI TE */ - function = "lcd"; - groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ - }; - default_cfg1 { - pins = "GPIO68_E1"; /* VSI0 */ - ste,config = <&in_nopull>; - }; - }; - }; - - /* Two GPIO lines used by the display */ - display { - display_default_mode: display_default { - kyle_cfg1 { - /* - * OLED DETECT or check_pba, this appears to be high - * on "PBA" which I guess is "prototype board A". - */ - pins = "GPIO93_B7"; - ste,config = <&gpio_in_nopull>; - }; - kyle_cfg2 { - pins = "GPIO139_C9"; - /* - * MIPI_DSI0_RESET_N resets the display, leave high - * (de-asserted) so we only assert reset explicitly - * from the display driver. - */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - - /* GPIO that enables the LDO regulator for the LCD display */ - lcd-ldo { - lcd_pwr_en_default_mode: lcd_pwr_en_default { - /* LCD_PWR_EN on GPIO219 */ - kyle_cfg1 { - pins = "GPIO219_AG10"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - - backlight { - gpio_backlight_default_mode: backlight_default { - kyle_cfg1 { - pins = "GPIO69_E2"; /* LCD_BL_CTRL */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - flash { - gpio_flash_default_mode: flash_default { - kyle_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the 2.9V SD card level translator */ - sd-level-translator { - sd_level_translator_default: sd_level_translator_default { - /* level shifter on GPIO87 */ - kyle_cfg1 { - pins = "GPIO87_B3"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the eMMC */ - emmc-ldo { - emmc_ldo_en_default_mode: emmc_ldo_default { - /* LDO enable on GPIO223 */ - kyle_cfg1 { - pins = "GPIO223_AH9"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO keys */ - gpio-keys { - gpio_keys_default_mode: gpio_keys_default { - kyle_cfg1 { - pins = "GPIO67_G2", /* VOL UP */ - "GPIO91_B6", /* HOME */ - "GPIO92_D6"; /* VOL DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - /* Interrupt line for light/proximity sensor GP2AP002 */ - gp2ap002 { - gp2ap002_kyle_default: gp2ap002_kyle { - kyle_cfg1 { - pins = "GPIO146_D13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for NCP6914 */ - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - kyle_cfg1 { - pins = "GPIO143_D12", "GPIO144_B13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for ALPS HSCD compass */ - i2c-gpio-1 { - i2c_gpio_1_default: i2c_gpio_1 { - kyle_cfg1 { - pins = "GPIO151_B17", "GPIO152_D16"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - wlan { - wlan_default_mode: wlan_default { - kyle_cfg1 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_in_pd>; - }; - }; - wlan_en_default_mode: wlan_en_default { - kyle_cfg2 { - pins = "GPIO215_AH13"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - bluetooth { - bluetooth_default_mode: bluetooth_default { - kyle_cfg1 { - pins = "GPIO199_AH23", "GPIO222_AJ9"; - ste,config = <&gpio_out_lo>; - }; - kyle_cfg2 { - pins = "GPIO97_D9"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - vibrator { - vibrator_default: vibrator_default { - kyle_cfg1 { - pins = "GPIO195_AG28"; /* MOT_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Interrupt line for the Melfas MMS134S touchscreen */ - touchscreen { - mms134s_kyle_default: mms134s_kyle { - kyle_cfg1 { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - g05ta03 { - g05ta03_kyle_default: g05ta03 { - /* Reset line, start out de-asserted */ - kyle_cfg1 { - pins = "GPIO21_AB3"; - ste,config = <&gpio_out_hi>; - }; - /* GPS_ON_OFF, start out deasserted (off) */ - kyle_cfg2 { - pins = "GPIO86_C6"; - ste,config = <&gpio_out_lo>; - }; - }; - }; -}; - -&ab8505_gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio_default>; - - gpio { - gpio_default: gpio_default { - kyle_mux { - /* Change unused pins to GPIO mode */ - function = "gpio"; - groups = "gpio3_a_1", /* default: SysClkReq4 */ - "gpio14_a_1"; /* default: PWMOut1 */ - }; - kyle_cfg1 { - pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; - bias-disable; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts deleted file mode 100644 index 064d6fee8821..000000000000 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ /dev/null @@ -1,714 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer. - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-ab8505.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "Samsung XCover 2 (GT-S7710)"; - compatible = "samsung,skomer", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - battery: battery { - compatible = "samsung,eb485159lu"; - }; - - thermal-zones { - battery-thermal { - /* This zone will be polled by the battery temperature code */ - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&bat_therm>; - - trips { - battery-crit-hi { - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - bat_therm: thermistor { - compatible = "samsung,1404-001221"; - io-channels = <&gpadc 0x02>; /* BatTemp */ - pullup-uv = <1800000>; - pullup-ohm = <230000>; - pulldown-ohm = <0>; - #thermal-sensor-cells = <0>; - }; - - /* TI TXS0206 level translator for 2.9 V */ - sd_level_translator: regulator-gpio { - compatible = "regulator-fixed"; - - /* GPIO87 EN */ - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - - startup-delay-us = <200>; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* External LDO MIC5366-3.3YMT for eMMC */ - ldo_3v3_reg: regulator-gpio-ldo-3v3 { - compatible = "regulator-fixed"; - regulator-name = "en-3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_ldo_en_default_mode>; - }; - - wlan_en: regulator-gpio-wlan-en { - compatible = "regulator-fixed"; - regulator-name = "wl-reg-on"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - startup-delay-us = <200000>; - /* GPIO215 WLAN_EN */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_default_mode>; - }; - - vibrator { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default_mode>; - - button-home { - linux,code = ; - label = "HOME"; - /* GPIO91 */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - }; - button-volup { - linux,code = ; - label = "VOL+"; - /* GPIO67 */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - }; - button-voldown { - linux,code = ; - label = "VOL-"; - /* GPIO92 */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - button-menu { - linux,code = ; - label = "MENU"; - /* GPIO204 */ - gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - }; - button-back { - linux,code = ; - label = "BACK"; - /* GPIO205 */ - gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; - }; - }; - - ktd253: backlight { - compatible = "kinetic,ktd253"; - /* GPIO 69 */ - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - /* Default to 13/32 brightness */ - default-brightness = <13>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_backlight_default_mode>; - }; - - /* Richtek RT8515GQW Flash LED Driver IC */ - flash { - compatible = "richtek,rt8515"; - /* GPIO 140 */ - enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - /* GPIO 141 */ - ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - /* - * RFS is 16 kOhm and RTS is 100 kOhm giving - * the flash max current 343mA and torch max - * current 55 mA. - */ - richtek,rfs-ohms = <16000>; - richtek,rts-ohms = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_flash_default_mode>; - - led { - function = LED_FUNCTION_FLASH; - color = ; - flash-max-timeout-us = <250000>; - flash-max-microamp = <343750>; - led-max-microamp = <55000>; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_0_default>; - #address-cells = <1>; - #size-cells = <0>; - /* TODO: this should be used by the NCP6914 Camera power management unit */ - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_gpio_1_default>; - #address-cells = <1>; - #size-cells = <0>; - magnetometer@c { - compatible = "alps,hscdtd008a"; - reg = <0x0c>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - dvdd-supply = <&ab8500_ldo_aux8_reg>; - }; - }; - - soc { - // External Micro SD slot - mmc@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - /* All direction control is used */ - st,sig-pin-fbclk; - full-pwr-cycle; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&sd_level_translator>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_1_default>; - pinctrl-1 = <&mc0_a_1_sleep>; - status = "okay"; - }; - - // WLAN SDIO channel - mmc@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - non-removable; - cap-sd-highspeed; - vmmc-supply = <&wlan_en>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - /* GPIO216 WL_HOST_WAKE */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_mode>; - }; - }; - - /* - * eMMC seems to be mostly Samsung KLM4G1YE4C "4YMD1R" - */ - mmc@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - no-sdio; - no-sd; - /* From datasheet page 26 figure 9: 300 ms set-up time for 4GB */ - post-power-on-delay-ms = <300>; - vmmc-supply = <&ldo_3v3_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - - status = "okay"; - }; - - /* GBF (Bluetooth) UART */ - serial@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - - /* FIXME: not quite working yet, probably needs regulators */ - bluetooth { - /* BCM4334B0 actually */ - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default_mode>; - }; - }; - - /* GPS UART */ - serial@80121000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; - - gnss { - /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ - compatible = "csr,csrg05ta03-icje-r"; - /* GPS_RSTN on GPIO209 */ - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; - /* GPS_ON_OFF on GPIO86 */ - sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - /* GPS_1V8 (VSMPS2) */ - vcc-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&g05ta03_skomer_default>; - /* According to /etc/sirfgps.conf */ - current-speed = <460800>; - }; - }; - - /* Debugging console UART connected to AB8505 USB */ - serial@80007000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - prcmu@80157000 { - ab8505 { - phy { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500_fg { - line-impedance-micro-ohms = <16000>; - }; - - regulator { - ab8500_ldo_aux1 { - /* Used for VDD for sensors */ - regulator-name = "AUX1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux2 { - /* Supplies the Cypress TMA140 touchscreen only with 3.0V */ - regulator-name = "AUX2"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux3 { - /* Used for voltage for external MMC/SD card */ - regulator-name = "AUX3"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux4 { - regulator-name = "AUX4"; - /* Hammer to 3.0V for the display */ - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux5 { - regulator-name = "AUX5"; - /* Intended for 1V8 for touchscreen but actually left unused */ - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <2790000>; - }; - - ab8500_ldo_aux6 { - regulator-name = "AUX6"; - /* Hammer to 1.8V for the display */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ab8500_ldo_aux8 { - /* Mostly VIO for sensors */ - regulator-name = "AUX8"; - }; - }; - }; - }; - - /* I2C0 */ - i2c@80004000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - - proximity@44 { - compatible = "sharp,gp2ap002s00f"; - clock-frequency = <400000>; - reg = <0x44>; - - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vio-supply = <&ab8500_ldo_aux8_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gp2ap002_skomer_default>; - sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; - sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; - }; - }; - - - /* I2C2 */ - i2c@80128000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - accel@18 { - compatible = "bosch,bma254"; - clock-frequency = <400000>; - reg = <0x18>; - - /* GPIO224 used as "smart alert" interrupt */ - interrupt-parent = <&gpio7>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - - mount-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&ab8500_ldo_aux8_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&bma254_skomer_default>; - }; - }; - - /* I2C3 */ - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - /* Cypress CY8CTMA140 touchscreen */ - touchscreen@20 { - compatible = "cypress,cy8ctma140"; - clock-frequency = <400000>; - reg = <0x20>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - touchscreen-max-pressure = <255>; - - /* GPIO218 for IRQ */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - - /* VDD is "digital supply" nominally 1.71-3.6V */ - vdd-supply = <&ab8500_ldo_aux2_reg>; - /* VCPIN is "analog supply", 2.7-3.6 V */ - vcpin-supply = <&ab8500_ldo_aux2_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&tma140_skomer_default>; - }; - }; - - mcde@a0350000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dsi_default_mode>; - - dsi@a0351000 { - panel { - /* NT35510-based Hydis HVA40WV1 */ - compatible = "hydis,hva40wv1", "novatek,nt35510"; - reg = <0>; - /* v_lcd_3v0 2.3-4.8V */ - vdd-supply = <&ab8500_ldo_aux4_reg>; - /* v_lcd_1v8 1.65-3.3V */ - vddi-supply = <&ab8500_ldo_aux6_reg>; - /* GPIO 139 */ - reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&display_default_mode>; - backlight = <&ktd253>; - }; - }; - }; - }; -}; - -&pinctrl { - sdi0 { - mc0_a_1_default { - default_cfg1 { - /* GPIO18, 19 & 20 unused so pull down */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - - /* This is a reset line for the eMMC */ - sdi2 { - mc2_a_1_default { - default_cfg2 { - pins = "GPIO130_C8"; /* FBCLK */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - - mcde { - dsi_default_mode: dsi_default { - default_mux1 { - /* Mux in VSI0 used for DSI TE */ - function = "lcd"; - groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ - }; - default_cfg1 { - pins = "GPIO68_E1"; /* VSI0 */ - ste,config = <&in_nopull>; - }; - }; - }; - - /* Two GPIO lines used by the display */ - display { - display_default_mode: display_default { - skomer_cfg1 { - /* - * OLED DETECT or check_pba, this appears to be high - * on "PBA" which I guess is "prototype board A". - */ - pins = "GPIO93_B7"; - ste,config = <&gpio_in_nopull>; - }; - skomer_cfg2 { - pins = "GPIO139_C9"; - /* - * MIPI_DSI0_RESET_N resets the display, leave high - * (de-asserted) so we only assert reset explicitly - * from the display driver. - */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - backlight { - gpio_backlight_default_mode: backlight_default { - skomer_cfg1 { - pins = "GPIO69_E2"; /* LCD_BL_CTRL */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - flash { - gpio_flash_default_mode: flash_default { - skomer_cfg1 { - pins = "GPIO140_B11", "GPIO141_C12"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* GPIO that enables the 2.9V SD card level translator */ - sd-level-translator { - sd_level_translator_default: sd_level_translator_default { - /* level shifter on GPIO87 */ - skomer_cfg1 { - pins = "GPIO87_B3"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO that enables the LDO regulator for the eMMC */ - emmc-ldo { - emmc_ldo_en_default_mode: emmc_ldo_default { - /* LDO enable on GPIO223 */ - skomer_cfg1 { - pins = "GPIO223_AH9"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - /* GPIO keys */ - gpio-keys { - gpio_keys_default_mode: gpio_keys_default { - skomer_cfg1 { - pins = "GPIO67_G2", /* VOL UP */ - "GPIO91_B6", /* HOME */ - "GPIO92_D6", /* VOL DOWN */ - "GPIO204_AF23", /* MENU */ - "GPIO205_AG23"; /* BACK */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - /* Interrupt line for BMA254 */ - bma254 { - bma254_skomer_default: bma254_skomer { - skomer_cfg1 { - pins = "GPIO224_AG9"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - /* Interrupt line for light/proximity sensor GP2AP002 */ - gp2ap002 { - gp2ap002_skomer_default: gp2ap002_skomer { - skomer_cfg1 { - pins = "GPIO146_D13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for NCP6914 */ - i2c-gpio-0 { - i2c_gpio_0_default: i2c_gpio_0 { - skomer_cfg1 { - pins = "GPIO143_D12", "GPIO144_B13"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - /* GPIO-based I2C bus for ALPS HSCD compass */ - i2c-gpio-1 { - i2c_gpio_1_default: i2c_gpio_1 { - skomer_cfg1 { - pins = "GPIO151_B17", "GPIO152_D16"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - wlan { - wlan_default_mode: wlan_default { - skomer_cfg1 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_in_pd>; - }; - }; - wlan_en_default_mode: wlan_en_default { - skomer_cfg2 { - pins = "GPIO215_AH13"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - bluetooth { - bluetooth_default_mode: bluetooth_default { - skomer_cfg1 { - pins = "GPIO199_AH23", "GPIO222_AJ9"; - ste,config = <&gpio_out_lo>; - }; - skomer_cfg2 { - pins = "GPIO97_D9"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - vibrator { - vibrator_default: vibrator_default { - skomer_cfg1 { - pins = "GPIO195_AG28"; /* MOT_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - /* Interrupt line for the Cypress TMA140 touchscreen */ - touchscreen { - tma140_skomer_default: tma140_skomer { - skomer_cfg1 { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_nopull>; - }; - }; - }; - g05ta03 { - g05ta03_skomer_default: g05ta03 { - /* Reset line, start out de-asserted */ - skomer_cfg1 { - pins = "GPIO209_AG15"; - ste,config = <&gpio_out_hi>; - }; - /* GPS_ON_OFF, start out deasserted (off) */ - skomer_cfg2 { - pins = "GPIO86_C6"; - ste,config = <&gpio_out_lo>; - }; - }; - }; -}; - -&ab8505_gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio_default>; - - gpio { - gpio_default: gpio_default { - skomer_mux { - /* Change unused pins to GPIO mode */ - function = "gpio"; - groups = "gpio3_a_1", /* default: SysClkReq4 */ - "gpio14_a_1"; /* default: PWMOut1 */ - }; - skomer_cfg1 { - pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; - bias-disable; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts deleted file mode 100644 index 9c79982ee7ba..000000000000 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - */ -/dts-v1/; -#include "stih407.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH407 B2120"; - compatible = "st,stih407-b2120", "st,stih407"; - - chosen { - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - -}; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi deleted file mode 100644 index 350bcfcf498b..000000000000 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0x10000>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - }; - - clk_m_a9: clk-m-a9 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-a0"; - - clocks = <&clk_sysin>; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen", "st,flexgen-stih407-a0"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - }; - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-c0"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_quadfs: clk-s-d0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - - clocks = <&clk_sysin>; - }; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d0"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - }; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_quadfs: clk-s-d2-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - - clocks = <&clk_sysin>; - }; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d2"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - }; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_quadfs: clk-s-d3-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - - clocks = <&clk_sysin>; - }; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d3"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi deleted file mode 100644 index 5ebb77947fd9..000000000000 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ /dev/null @@ -1,991 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro - */ -#include "stih407-pinctrl.dtsi" -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gp0_reserved: rproc@45000000 { - compatible = "shared-dma-pool"; - reg = <0x45000000 0x00400000>; - no-map; - }; - - delta_reserved: rproc@44000000 { - compatible = "shared-dma-pool"; - reg = <0x44000000 0x01000000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - - clocks = <&clk_m_a9>; - clock-names = "cpu"; - clock-latency = <100000>; - cpu0-supply = <&pwm_regulator>; - st,syscfg = <&syscfg_core 0x8e0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - }; - }; - - intc: interrupt-controller@8761000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x08761000 0x1000>, <0x08760100 0x100>; - }; - - scu@8760000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x08760000 0x1000>; - }; - - timer@8760200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0x08760200 0x100>; - interrupts = ; - clocks = <&arm_periph_clk>; - }; - - l2: cache-controller@8762000 { - compatible = "arm,pl310-cache"; - reg = <0x08762000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - pwm_regulator: pwm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 3 8448>; - regulator-name = "CPU_1V0_AVS"; - regulator-min-microvolt = <784000>; - regulator-max-microvolt = <1299000>; - regulator-always-on; - max-duty-cycle = <255>; - status = "okay"; - }; - - restart: restart-controller { - compatible = "st,stih407-restart"; - st,syscfg = <&syscfg_sbc_reg>; - status = "okay"; - }; - - powerdown: powerdown-controller { - compatible = "st,stih407-powerdown"; - #reset-cells = <1>; - }; - - softreset: softreset-controller { - compatible = "st,stih407-softreset"; - #reset-cells = <1>; - }; - - picophyreset: picophyreset-controller { - compatible = "st,stih407-picophyreset"; - #reset-cells = <1>; - }; - - irq-syscfg { - compatible = "st,stih407-irq-syscfg"; - st,syscfg = <&syscfg_core>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - - usb2_picophy0: phy1 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names = "global", "port"; - }; - - miphy28lp_phy: miphy28lp { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - - st231_gp0: st231-gp0 { - compatible = "st,st231-rproc"; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; - }; - - st231_delta: st231-delta { - compatible = "st,st231-rproc"; - memory-region = <&delta_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; - }; - - delta0 { - compatible = "st,st-delta"; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - syscfg_sbc: sbc-syscfg@9620000 { - compatible = "st,stih407-sbc-syscfg", "syscon"; - reg = <0x9620000 0x1000>; - }; - - syscfg_front: front-syscfg@9280000 { - compatible = "st,stih407-front-syscfg", "syscon"; - reg = <0x9280000 0x1000>; - }; - - syscfg_rear: rear-syscfg@9290000 { - compatible = "st,stih407-rear-syscfg", "syscon"; - reg = <0x9290000 0x1000>; - }; - - syscfg_flash: flash-syscfg@92a0000 { - compatible = "st,stih407-flash-syscfg", "syscon"; - reg = <0x92a0000 0x1000>; - }; - - syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { - compatible = "st,stih407-sbc-reg-syscfg", "syscon"; - reg = <0x9600000 0x1000>; - }; - - syscfg_core: core-syscfg@92b0000 { - compatible = "st,stih407-core-syscfg", "syscon"; - reg = <0x92b0000 0x1000>; - - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; - status = "disabled"; - st,syscfg = <&syscfg_core>; - }; - }; - - syscfg_lpm: lpm-syscfg@94b5100 { - compatible = "st,stih407-lpm-syscfg", "syscon"; - reg = <0x94b5100 0x1000>; - }; - - /* Display */ - vtg_main: sti-vtg-main@8d02800 { - compatible = "st,vtg"; - reg = <0x8d02800 0x200>; - interrupts = ; - }; - - vtg_aux: sti-vtg-aux@8d00200 { - compatible = "st,vtg"; - reg = <0x8d00200 0x100>; - interrupts = ; - }; - - serial@9830000 { - compatible = "st,asc"; - reg = <0x9830000 0x2c>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - /* Pinctrl moved out to a per-board configuration */ - - status = "disabled"; - }; - - serial@9831000 { - compatible = "st,asc"; - reg = <0x9831000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial1>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - serial@9832000 { - compatible = "st,asc"; - reg = <0x9832000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0: serial@9530000 { - compatible = "st,asc"; - reg = <0x9530000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial0>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - serial@9531000 { - compatible = "st,asc"; - reg = <0x9531000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - i2c@9840000 { - compatible = "st,comms-ssc4-i2c"; - interrupts = ; - reg = <0x9840000 0x110>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9841000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9841000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9842000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9842000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9843000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9843000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9844000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9844000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9845000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9845000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - - /* SSCs on SBC */ - i2c@9540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9841000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9841000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9842000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9842000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9843000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9843000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9844000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9844000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - /* SBC SSC */ - spi@9540000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9541000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9542000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9542000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi12_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - mmc0: sdhci@9060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - bus-width = <8>; - }; - - mmc1: sdhci@9080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; - }; - - /* Watchdog and Real-Time Clock */ - lpc@8787000 { - compatible = "st,stih407-lpc"; - reg = <0x8787000 0x1000>; - interrupts = ; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - timeout-sec = <120>; - st,syscfg = <&syscfg_core>; - st,lpc-mode = ; - }; - - lpc@8788000 { - compatible = "st,stih407-lpc"; - reg = <0x8788000 0x1000>; - interrupts = ; - clocks = <&clk_s_d3_flexgen CLK_LPC_1>; - st,lpc-mode = ; - }; - - spifsm: spifsm@9022000{ - compatible = "st,spi-fsm"; - reg = <0x9022000 0x1000>; - reg-names = "spi-fsm"; - clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - clock-names = "emi_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsm>; - st,syscfg = <&syscfg_core>; - st,boot-device-reg = <0x8c4>; - st,boot-device-spi = <0x68>; - - status = "disabled"; - }; - - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - - interrupts = ; - interrupt-names = "hostc"; - - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - sata1: sata@9b28000 { - compatible = "st,ahci"; - reg = <0x9b28000 0x1000>; - - interrupts = ; - interrupt-names = "hostc"; - - phys = <&phy_port1 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA1_POWERDOWN>, - <&softreset STIH407_SATA1_SOFTRESET>, - <&softreset STIH407_SATA1_PWR_SOFTRESET>; - reset-names = "pwr-dwn", - "sw-rst", - "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - - st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - ranges; - - status = "disabled"; - - dwc3: usb@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = ; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy0>, - <&phy_port2 PHY_TYPE_USB3>; - snps,dis_u3_susphy_quirk; - }; - }; - - /* COMMS PWM Module */ - pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <1>; - - status = "disabled"; - }; - - /* SBC PWM Module */ - pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <4>; - - status = "disabled"; - }; - - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - device_type = "network"; - status = "disabled"; - compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - reg = <0x9630000 0x8000>, <0x80 0x4>; - reg-names = "stmmaceth", "sti-ethconf"; - - st,syscon = <&syscfg_sbc_reg 0x80>; - st,gmac_en; - resets = <&softreset STIH407_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - - /* DMA Bus Mode */ - snps,pbl = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_ETH_PHY>; - }; - - mailbox0: mailbox@8f00000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f00000 0x1000>; - interrupts = ; - #mbox-cells = <2>; - mbox-name = "a9"; - status = "okay"; - }; - - mailbox1: mailbox@8f01000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f01000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_1"; - status = "okay"; - }; - - mailbox2: mailbox@8f02000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f02000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_0"; - status = "okay"; - }; - - mailbox3: mailbox@8f03000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f03000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_audio_video"; - status = "okay"; - }; - - /* fdma audio */ - fdma0: dma-controller@8e20000 { - compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; - reg = <0x8e20000 0x8000>, - <0x8e30000 0x3000>, - <0x8e37000 0x1000>, - <0x8e38000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - }; - - /* fdma app */ - fdma1: dma-controller@8e40000 { - compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; - reg = <0x8e40000 0x8000>, - <0x8e50000 0x3000>, - <0x8e57000 0x1000>, - <0x8e58000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - - status = "disabled"; - }; - - /* fdma free running */ - fdma2: dma-controller@8e60000 { - compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; - reg = <0x8e60000 0x8000>, - <0x8e70000 0x3000>, - <0x8e77000 0x1000>, - <0x8e78000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,stih407-uni-player-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; - assigned-clock-rates = <50000000>; - reg = <0x8d80000 0x158>; - interrupts = ; - dmas = <&fdma0 2 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,stih407-uni-player-pcm-out"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; - assigned-clock-rates = <50000000>; - reg = <0x8d81000 0x158>; - interrupts = ; - dmas = <&fdma0 3 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,stih407-uni-player-dac"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; - assigned-clock-rates = <50000000>; - reg = <0x8d82000 0x158>; - interrupts = ; - dmas = <&fdma0 4 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,stih407-uni-player-spdif"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; - assigned-clock-rates = <50000000>; - reg = <0x8d85000 0x158>; - interrupts = ; - dmas = <&fdma0 7 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,stih407-uni-reader-pcm_in"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d83000 0x158>; - interrupts = ; - dmas = <&fdma0 5 0 1>; - dma-names = "rx"; - - status = "disabled"; - }; - - sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,stih407-uni-reader-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d84000 0x158>; - interrupts = ; - dmas = <&fdma0 6 0 1>; - dma-names = "rx"; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi deleted file mode 100644 index 2cf335714ca2..000000000000 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ /dev/null @@ -1,1262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - /* 0-5: PIO_SBC */ - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - /* 10-19: PIO_FRONT0 */ - gpio6 = &pio10; - gpio7 = &pio11; - gpio8 = &pio12; - gpio9 = &pio13; - gpio10 = &pio14; - gpio11 = &pio15; - gpio12 = &pio16; - gpio13 = &pio17; - gpio14 = &pio18; - gpio15 = &pio19; - /* 20: PIO_FRONT1 */ - gpio16 = &pio20; - /* 30-35: PIO_REAR */ - gpio17 = &pio30; - gpio18 = &pio31; - gpio19 = &pio32; - gpio20 = &pio33; - gpio21 = &pio34; - gpio22 = &pio35; - /* 40-42: PIO_FLASH */ - gpio23 = &pio40; - gpio24 = &pio41; - gpio25 = &pio42; - }; - - soc { - pin-controller-sbc@961f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0x0961f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09610000 0x6000>; - - pio0: gpio@9610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@9611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@9612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@9613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@9614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - pio5: gpio@9615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO5"; - st,retime-pin-mask = <0x3f>; - }; - - cec0 { - pinctrl_cec0_default: cec0-default { - st,pins { - hdmi_cec = <&pio2 4 ALT1 BIDIR>; - }; - }; - }; - - rc { - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - - pinctrl_uhf: uhf0 { - st,pins { - ir = <&pio4 1 ALT2 IN>; - }; - }; - - pinctrl_tx: tx0 { - st,pins { - tx = <&pio4 2 ALT2 OUT>; - }; - }; - - pinctrl_tx_od: tx_od0 { - st,pins { - tx_od = <&pio4 3 ALT2 OUT>; - }; - }; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0 { - pinctrl_sbc_serial0: sbc_serial0-0 { - st,pins { - tx = <&pio3 4 ALT1 OUT>; - rx = <&pio3 5 ALT1 IN>; - }; - }; - }; - /* SBC_ASC1 - UART11 */ - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1-0 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - i2c10 { - pinctrl_i2c10_default: i2c10-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - i2c11 { - pinctrl_i2c11_default: i2c11-default { - st,pins { - sda = <&pio5 1 ALT1 BIDIR>; - scl = <&pio5 0 ALT1 BIDIR>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio4 0 ALT6 IN>; - keyin1 = <&pio4 5 ALT4 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio4 6 ALT4 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - gmac1 { - /* - * Almost all the boards based on STiH407 SoC have an embedded - * switch where the mdio/mdc have been used for managing the SMI - * iface via I2C. For this reason these lines can be allocated - * by using dedicated configuration (in case of there will be a - * standard PHY transceiver on-board). - */ - pinctrl_rgmii1: rgmii1-0 { - st,pins { - - txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; - }; - }; - - pinctrl_rgmii1_mdio: rgmii1-mdio { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - }; - }; - - pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1: rmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk: rmii1_phyclk { - st,pins { - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { - st,pins { - phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-capturein = <&pio4 3 ALT1 IN>; - pwm-out = <&pio4 4 ALT1 OUT>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - - spi10 { - pinctrl_spi10_default: spi10-4w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 OUT>; - mrst = <&pio4 7 ALT1 IN>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - - pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 BIDIR_PU>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - }; - - spi11 { - pinctrl_spi11_default: spi11-4w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 OUT>; - mrst = <&pio3 0 ALT2 IN>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - - pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 BIDIR_PU>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - }; - - spi12 { - pinctrl_spi12_default: spi12-4w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 OUT>; - mrst = <&pio3 4 ALT2 IN>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - - pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 BIDIR_PU>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - }; - }; - - pin-controller-front0@920f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0920f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09200000 0x10000>; - - pio10: pio@9200000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO10"; - }; - pio11: pio@9201000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: pio@9202000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO12"; - }; - pio13: pio@9203000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO13"; - }; - pio14: pio@9204000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: pio@9205000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: pio@9206000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: pio@9207000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: pio@9208000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO18"; - }; - pio19: pio@9209000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO19"; - }; - - /* Comms */ - serial0 { - pinctrl_serial0: serial0-0 { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - }; - }; - pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - cts = <&pio17 2 ALT1 IN>; - rts = <&pio17 3 ALT1 OUT>; - }; - }; - }; - - serial1 { - pinctrl_serial1: serial1-0 { - st,pins { - tx = <&pio16 0 ALT1 OUT>; - rx = <&pio16 1 ALT1 IN>; - }; - }; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio15 0 ALT1 OUT>; - rx = <&pio15 1 ALT1 IN>; - }; - }; - }; - - mmc1 { - pinctrl_sd1: sd1-0 { - st,pins { - sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; - sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; - sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; - sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; - sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; - sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; - sd_led = <&pio16 6 ALT6 OUT>; - sd_pwren = <&pio16 7 ALT6 OUT>; - sd_cd = <&pio19 0 ALT6 IN>; - sd_wp = <&pio19 1 ALT6 IN>; - }; - }; - }; - - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio10 6 ALT2 BIDIR>; - scl = <&pio10 5 ALT2 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio11 1 ALT2 BIDIR>; - scl = <&pio11 0 ALT2 BIDIR>; - }; - }; - }; - - i2c2 { - pinctrl_i2c2_default: i2c2-default { - st,pins { - sda = <&pio15 6 ALT2 BIDIR>; - scl = <&pio15 5 ALT2 BIDIR>; - }; - }; - - pinctrl_i2c2_alt2_1: i2c2-alt2-1 { - st,pins { - sda = <&pio12 6 ALT2 BIDIR>; - scl = <&pio12 5 ALT2 BIDIR>; - }; - }; - }; - - i2c3 { - pinctrl_i2c3_default: i2c3-alt1-0 { - st,pins { - sda = <&pio18 6 ALT1 BIDIR>; - scl = <&pio18 5 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt1_1: i2c3-alt1-1 { - st,pins { - sda = <&pio17 7 ALT1 BIDIR>; - scl = <&pio17 6 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt3_0: i2c3-alt3-0 { - st,pins { - sda = <&pio13 6 ALT3 BIDIR>; - scl = <&pio13 5 ALT3 BIDIR>; - }; - }; - }; - - spi0 { - pinctrl_spi0_default: spi0-4w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 OUT>; - mrst = <&pio10 7 ALT2 IN>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 BIDIR_PU>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 OUT>; - mrst = <&pio19 5 ALT1 IN>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - - pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 BIDIR_PU>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - }; - - spi1 { - pinctrl_spi1_default: spi1-4w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 OUT>; - mrst = <&pio11 2 ALT2 IN>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 BIDIR_PU>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 OUT>; - mrst = <&pio14 4 ALT1 IN>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - - pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 BIDIR_PU>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - }; - - spi2 { - pinctrl_spi2_default: spi2-4w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 OUT>; - mrst = <&pio12 7 ALT2 IN>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 BIDIR_PU>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 OUT>; - mrst = <&pio14 7 ALT1 IN>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 BIDIR_PU>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 OUT>; - mrst = <&pio15 7 ALT2 IN>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 BIDIR_PU>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - }; - - spi3 { - pinctrl_spi3_default: spi3-4w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 OUT>; - mrst = <&pio13 7 ALT3 IN>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 BIDIR_PU>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 OUT>; - mrst = <&pio17 5 ALT1 IN>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 BIDIR_PU>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 OUT>; - mrst = <&pio18 7 ALT1 IN>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 BIDIR_PU>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - }; - - tsin0 { - pinctrl_tsin0_parallel: tsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin0_serial: tsin0_serial { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin1 { - pinctrl_tsin1_parallel: tsin1_parallel { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin1_serial: tsin1_serial { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin2 { - pinctrl_tsin2_parallel: tsin2_parallel { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin2_serial: tsin2_serial { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin3 { - pinctrl_tsin3_serial: tsin3_serial { - st,pins { - DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin4 { - pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { - st,pins { - DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; - ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; - PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin5 { - pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { - st,pins { - DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { - st,pins { - DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout0 { - pinctrl_tsout0_parallel: tsout0_parallel { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsout0_serial: tsout0_serial { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout1 { - pinctrl_tsout1_serial: tsout1_serial { - st,pins { - DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; - VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - mtsin0 { - pinctrl_mtsin0_parallel: mtsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - systrace { - pinctrl_systrace_default: systrace-default { - st,pins { - trc_data0 = <&pio11 3 ALT5 OUT>; - trc_data1 = <&pio11 4 ALT5 OUT>; - trc_data2 = <&pio11 5 ALT5 OUT>; - trc_data3 = <&pio11 6 ALT5 OUT>; - trc_clk = <&pio11 7 ALT5 OUT>; - }; - }; - }; - }; - - pin-controller-front1@921f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0921f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09210000 0x10000>; - - pio20: pio@9210000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO20"; - }; - - tsin4 { - pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { - st,pins { - DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-rear@922f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0x0922f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09220000 0x6000>; - - pio30: gpio@9220000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@9221000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO31"; - }; - pio32: gpio@9222000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO32"; - }; - pio33: gpio@9223000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO33"; - }; - pio34: gpio@9224000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO34"; - }; - pio35: gpio@9225000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO35"; - st,retime-pin-mask = <0x7f>; - }; - - i2c4 { - pinctrl_i2c4_default: i2c4-default { - st,pins { - sda = <&pio30 1 ALT1 BIDIR>; - scl = <&pio30 0 ALT1 BIDIR>; - }; - }; - }; - - i2c5 { - pinctrl_i2c5_default: i2c5-default { - st,pins { - sda = <&pio34 4 ALT1 BIDIR>; - scl = <&pio34 3 ALT1 BIDIR>; - }; - }; - }; - - usb3 { - pinctrl_usb3: usb3-2 { - st,pins { - usb-oc-detect = <&pio35 4 ALT1 IN>; - usb-pwr-enable = <&pio35 5 ALT1 OUT>; - usb-vbus-valid = <&pio35 6 ALT1 IN>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-capturein = <&pio31 0 ALT1 IN>; - pwm-out = <&pio31 1 ALT1 OUT>; - }; - }; - }; - - spi4 { - pinctrl_spi4_default: spi4-4w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 OUT>; - mrst = <&pio30 2 ALT1 IN>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 BIDIR_PU>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 OUT>; - mrst = <&pio34 2 ALT3 IN>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - - pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 BIDIR_PU>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - }; - - i2s_out { - pinctrl_i2s_8ch_out: i2s_8ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - data1 = <&pio34 0 ALT1 OUT>; - data2 = <&pio34 1 ALT1 OUT>; - data3 = <&pio34 2 ALT1 OUT>; - }; - }; - - pinctrl_i2s_2ch_out: i2s_2ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - }; - }; - }; - - i2s_in { - pinctrl_i2s_8ch_in: i2s_8ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - data1 = <&pio33 0 ALT1 IN>; - data2 = <&pio33 1 ALT1 IN>; - data3 = <&pio33 2 ALT1 IN>; - data4 = <&pio33 3 ALT1 IN>; - }; - }; - - pinctrl_i2s_2ch_in: i2s_2ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - }; - }; - }; - - spdif_out { - pinctrl_spdif_out: spdif_out{ - st,pins { - spdif_out = <&pio34 7 ALT1 OUT>; - }; - }; - }; - - serial3 { - pinctrl_serial3: serial3-0 { - st,pins { - tx = <&pio31 3 ALT1 OUT>; - rx = <&pio31 4 ALT1 IN>; - }; - }; - }; - }; - - pin-controller-flash@923f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-flash-pinctrl"; - st,syscfg = <&syscfg_flash>; - reg = <0x0923f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09230000 0x3000>; - - pio40: gpio@9230000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO40"; - }; - pio41: gpio@9231000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO41"; - }; - pio42: gpio@9232000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO42"; - }; - - mmc0 { - pinctrl_mmc0: mmc0-0 { - st,pins { - emmc_clk = <&pio40 6 ALT1 BIDIR>; - emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; - emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; - emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; - emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; - emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; - emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; - emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; - emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; - emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; - }; - }; - pinctrl_sd0: sd0-0 { - st,pins { - sd_clk = <&pio40 6 ALT1 BIDIR>; - sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; - sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; - sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; - sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; - sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; - sd_led = <&pio42 0 ALT2 OUT>; - sd_pwren = <&pio42 2 ALT2 OUT>; - sd_vsel = <&pio42 3 ALT2 OUT>; - sd_cd = <&pio42 4 ALT2 IN>; - sd_wp = <&pio42 5 ALT2 IN>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio40 1 ALT1 OUT>; - spi-fsm-cs = <&pio40 0 ALT1 OUT>; - spi-fsm-mosi = <&pio40 2 ALT1 OUT>; - spi-fsm-miso = <&pio40 3 ALT1 IN>; - spi-fsm-hol = <&pio40 5 ALT1 OUT>; - spi-fsm-wp = <&pio40 4 ALT1 OUT>; - }; - }; - }; - - nand { - pinctrl_nand: nand { - st,pins { - nand_cs1 = <&pio40 6 ALT3 OUT>; - nand_cs0 = <&pio40 7 ALT3 OUT>; - nand_d0 = <&pio41 0 ALT3 BIDIR>; - nand_d1 = <&pio41 1 ALT3 BIDIR>; - nand_d2 = <&pio41 2 ALT3 BIDIR>; - nand_d3 = <&pio41 3 ALT3 BIDIR>; - nand_d4 = <&pio41 4 ALT3 BIDIR>; - nand_d5 = <&pio41 5 ALT3 BIDIR>; - nand_d6 = <&pio41 6 ALT3 BIDIR>; - nand_d7 = <&pio41 7 ALT3 BIDIR>; - nand_we = <&pio42 0 ALT3 OUT>; - nand_dqs = <&pio42 1 ALT3 OUT>; - nand_ale = <&pio42 2 ALT3 OUT>; - nand_cle = <&pio42 3 ALT3 OUT>; - nand_rnb = <&pio42 4 ALT3 IN>; - nand_oe = <&pio42 5 ALT3 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi deleted file mode 100644 index aca43d2bdaad..000000000000 --- a/arch/arm/boot/dts/stih407.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics Limited. - * Author: Gabriel Fernandez - */ -#include "stih407-clock.dtsi" -#include "stih407-family.dtsi" -#include -/ { - soc { - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <108000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts deleted file mode 100644 index 538ff98ca1b1..000000000000 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Peter Griffin - */ -/dts-v1/; -#include "stih410.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH410 B2120"; - compatible = "st,stih410-b2120", "st,stih410"; - - chosen { - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - usb2_picophy1: phy2 { - status = "okay"; - }; - - usb2_picophy2: phy3 { - status = "okay"; - }; - - soc { - - mmc0: sdhci@9060000 { - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - sti-display-subsystem@0 { - sti-hda@8d02000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts deleted file mode 100644 index 240b62040000..000000000000 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 STMicroelectronics (R&D) Limited. - * Author: Patrice Chotard - */ -/dts-v1/; -#include "stih410.dtsi" -#include - -/ { - model = "STiH410 B2260"; - compatible = "st,stih410-b2260", "st,stih410"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - serial1 = &uart1; - ethernet0 = ðernet0; - }; - - leds { - compatible = "gpio-leds"; - led-user-green-1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led-user-green-2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-user-green-3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-user-green-4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2260"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - /* DAC */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - }; - - miphy28lp_phy: miphy28lp { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - usb2_picophy1: phy2 { - status = "okay"; - }; - - usb2_picophy2: phy3 { - status = "okay"; - }; - - soc { - /* Low speed expansion connector */ - uart0: serial@9830000 { - label = "LS-UART0"; - pinctrl-names = "default", "no-hw-flowctrl"; - pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; - pinctrl-1 = <&pinctrl_serial0>; - rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - }; - - /* Low speed expansion connector */ - uart1: serial@9831000 { - label = "LS-UART1"; - status = "okay"; - }; - - /* Low speed expansion connector */ - spi0: spi@9844000 { - label = "LS-SPI0"; - cs-gpios = <&pio30 3 0>; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c0: i2c@9840000 { - label = "LS-I2C0"; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c1: i2c@9841000 { - label = "LS-I2C1"; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c2: i2c@9842000 { - label = "HS-I2C2"; - pinctrl-0 = <&pinctrl_i2c2_alt2_1>; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c3: i2c@9843000 { - label = "HS-I2C3"; - pinctrl-0 = <&pinctrl_i2c3_alt3_0>; - status = "okay"; - }; - - mmc0: sdhci@9060000 { - pinctrl-0 = <&pinctrl_sd0>; - bus-width = <4>; - status = "okay"; - }; - - /* high speed expansion connector */ - mmc1: sdhci@9080000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - phy-mode = "rgmii"; - pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - - snps,reset-gpio = <&pio0 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - - status = "okay"; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - status = "okay"; - }; - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - status = "okay"; - }; - - sata1: sata@9b28000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi deleted file mode 100644 index abac98a1810b..000000000000 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih410-clk", "simple-bus"; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0x10000>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-a0"; - - clocks = <&clk_sysin>; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen", "st,flexgen-stih410-a0"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - }; - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih410-c0"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_quadfs: clk-s-d0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - - clocks = <&clk_sysin>; - }; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih410-d0"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - }; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_quadfs: clk-s-d2-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - - clocks = <&clk_sysin>; - }; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d2"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - }; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_quadfs: clk-s-d3-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - - clocks = <&clk_sysin>; - }; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d3"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi deleted file mode 100644 index e6eadd124416..000000000000 --- a/arch/arm/boot/dts/stih410-pinctrl.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - */ -#include "st-pincfg.h" -/ { - - soc { - pin-controller-rear@922f080 { - - usb0 { - pinctrl_usb0: usb2-0 { - st,pins { - usb-oc-detect = <&pio35 0 ALT1 IN>; - usb-pwr-enable = <&pio35 1 ALT1 OUT>; - }; - }; - }; - - usb1 { - pinctrl_usb1: usb2-1 { - st,pins { - usb-oc-detect = <&pio35 2 ALT1 IN>; - usb-pwr-enable = <&pio35 3 ALT1 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi deleted file mode 100644 index 29e95e9d3229..000000000000 --- a/arch/arm/boot/dts/stih410.dtsi +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - */ -#include "stih410-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -#include -/ { - aliases { - bdisp0 = &bdisp0; - }; - - usb2_picophy1: phy2 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - usb2_picophy2: phy3 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - soc { - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - status = "disabled"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - - sti-hqvdp@9c00000 { - compatible = "st,stih407-hqvdp"; - reg = <0x9C00000 0x100000>; - clock-names = "hqvdp", "pix_main"; - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names = "hqvdp"; - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg = <&vtg_main>; - }; - }; - - bdisp0:bdisp@9f10000 { - compatible = "st,stih407-bdisp"; - reg = <0x9f10000 0x1000>; - interrupts = ; - clock-names = "bdisp"; - clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; - }; - - hva@8c85000 { - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = , - ; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; - }; - - thermal@91a0000 { - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = ; - }; - - cec@94a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = ; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - hdmi-phandle = <&sti_hdmi>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts deleted file mode 100644 index 53ac6c2b7b7d..000000000000 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics (R&D) Limited. - * Author: Maxime Coquelin - */ -/dts-v1/; -#include "stih418.dtsi" -#include -/ { - model = "STiH418 B2199"; - compatible = "st,stih418-b2199", "st,stih418"; - - chosen { - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0xc0000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - leds { - compatible = "gpio-leds"; - led-red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - led-green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - miphy28lp_phy: miphy28lp { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - i2c@9842000 { - status = "okay"; - }; - - i2c@9843000 { - status = "okay"; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - mmc1: sdhci@9080000 { - status = "okay"; - }; - - mmc0: sdhci@9060000 { - status = "okay"; - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - non-removable; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/stih418-b2264.dts deleted file mode 100644 index fc32a03073b6..000000000000 --- a/arch/arm/boot/dts/stih418-b2264.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2021 STMicroelectronics - * Author: Alain Volmat - */ -/dts-v1/; -#include "stih418.dtsi" -#include -/ { - model = "STiH418 B2264"; - compatible = "st,stih418-b2264", "st,stih418"; - - chosen { - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0xc0000000>; - }; - - cpus { - cpu@0 { - operating-points-v2 = <&cpu_opp_table>; - /* u-boot puts hpen in SBC dmem at 0xb8 offset */ - cpu-release-addr = <0x94100b8>; - }; - cpu@1 { - operating-points-v2 = <&cpu_opp_table>; - /* u-boot puts hpen in SBC dmem at 0xb8 offset */ - cpu-release-addr = <0x94100b8>; - }; - cpu@2 { - operating-points-v2 = <&cpu_opp_table>; - /* u-boot puts hpen in SBC dmem at 0xb8 offset */ - cpu-release-addr = <0x94100b8>; - }; - cpu@3 { - operating-points-v2 = <&cpu_opp_table>; - /* u-boot puts hpen in SBC dmem at 0xb8 offset */ - cpu-release-addr = <0x94100b8>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <784000>; - }; - opp01 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <784000>; - }; - opp02 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <784000>; - }; - opp03 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <784000>; - }; - opp04 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <784000>; - }; - }; - - aliases { - ttyAS0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - soc { - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pin-controller-sbc@961f080 { - gmac1 { - rgmii1-0 { - st,pins { - rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>; - rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>; - }; - }; - }; - }; - - }; -}; - -&ehci0 { - status = "okay"; -}; - -ðernet0 { - phy-mode = "rgmii"; - pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - st,tx-retime-src = "clkgen"; - - snps,reset-gpio = <&pio0 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - - status = "okay"; -}; - -&miphy28lp_phy { - phy_port0: port@9b22000 { - st,sata-gen = <2>; /* SATA GEN3 */ - st,osc-rdy; - }; -}; - -&mmc0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sbc_serial0 { - status = "okay"; -}; - -&spifsm { - status = "okay"; -}; - -&st_dwc3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi deleted file mode 100644 index e1749e92a2e7..000000000000 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih418-clk", "simple-bus"; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0x10000>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih418-clkgen-plla9"; - - clocks = <&clk_sysin>; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-a0"; - - clocks = <&clk_sysin>; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen", "st,flexgen-stih410-a0"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - }; - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih418-c0"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_quadfs: clk-s-d0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - - clocks = <&clk_sysin>; - }; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih410-d0"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - }; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_quadfs: clk-s-d2-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - - clocks = <&clk_sysin>; - }; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih418-d2"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - }; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_quadfs: clk-s-d3-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - - clocks = <&clk_sysin>; - }; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d3"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi deleted file mode 100644 index b35b9b7a7ccc..000000000000 --- a/arch/arm/boot/dts/stih418.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - */ -#include "stih418-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - }; - }; - - usb2_picophy1: phy2 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - }; - - usb2_picophy2: phy3 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - }; - - soc { - rng11: rng@8a8a000 { - status = "disabled"; - }; - - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - }; - - mmc0: sdhci@9060000 { - assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; - assigned-clock-parents = <&clk_s_c0_pll1 0>; - assigned-clock-rates = <200000000>; - }; - - thermal@91a0000 { - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = ; - }; - }; -}; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi deleted file mode 100644 index 8d9a2dfa76f1..000000000000 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - */ -#include -#include -#include -/ { - leds { - compatible = "gpio-leds"; - led-red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - led-green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2120"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - /* HDMI */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - /* DAC */ - format = "i2s"; - mclk-fs = <256>; - frame-inversion; - cpu { - sound-dai = <&sti_uni_player2>; - }; - - codec { - sound-dai = <&sti_sasg_codec 1>; - }; - }; - - simple-audio-card,dai-link@2 { - reg = <2>; - /* SPDIF */ - format = "left_j"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player3>; - }; - - codec { - sound-dai = <&sti_sasg_codec 0>; - }; - }; - }; - - miphy28lp_phy: miphy28lp { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - ssc2: i2c@9842000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - ssc3: i2c@9843000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - mmc0: sdhci@9060000 { - non-removable; - status = "okay"; - }; - - mmc1: sdhci@9080000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - - demux@8a20000 { - compatible = "st,stih407-c8sectpfe"; - status = "okay"; - reg = <0x08a20000 0x10000>, - <0x08a00000 0x4000>; - reg-names = "c8sectpfe", "c8sectpfe-ram"; - interrupts = , - ; - interrupt-names = "c8sectpfe-error-irq", - "c8sectpfe-idle-irq"; - pinctrl-0 = <&pinctrl_tsin0_serial>; - pinctrl-1 = <&pinctrl_tsin0_parallel>; - pinctrl-2 = <&pinctrl_tsin3_serial>; - pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; - pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; - pinctrl-names = "tsin0-serial", - "tsin0-parallel", - "tsin3-serial", - "tsin4-serial", - "tsin5-serial"; - clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; - clock-names = "c8sectpfe"; - - /* tsin0 is TSA on NIMA */ - tsin0: port { - tsin-num = <0>; - serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_LOW>; - dvb-card = ; - }; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - status = "okay"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - status = "okay"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - status = "okay"; - }; - - syscfg_core: core-syscfg@92b0000 { - sti_sasg_codec: sti-sasg-codec { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_out>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts deleted file mode 100644 index 576235ec3c51..000000000000 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" -#include "stm32f429-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "STMicroelectronics STM32429i-EVAL board"; - compatible = "st,stm32429i-eval", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_panel: vdd-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpiog 6 1>; - linux,default-trigger = "heartbeat"; - }; - led-orange { - gpios = <&gpiog 7 1>; - }; - led-red { - gpios = <&gpiog 10 1>; - }; - led-blue { - gpios = <&gpiog 12 1>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "Wake up"; - linux,code = ; - gpios = <&gpioa 0 0>; - }; - button-1 { - label = "Tamper"; - linux,code = ; - gpios = <&gpioc 13 0>; - }; - }; - - usbotg_hs_phy: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - panel_rgb: panel-rgb { - compatible = "ampire,am-480272h3tmqw-t01h"; - power-supply = <&vdd_panel>; - status = "okay"; - port { - panel_in_rgb: endpoint { - remote-endpoint = <<dc_out_rgb>; - }; - }; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc3_in8_pin>; - vdda-supply = <&vdda>; - vref-supply = <&vref>; - status = "okay"; - adc3: adc@200 { - st,adc-channels = <8>; - status = "okay"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&crc { - status = "okay"; -}; - -&dcmi { - status = "okay"; - - port { - dcmi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-type = ; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_ext_camera>; - clock-names = "xvclk"; - status = "okay"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&dcmi_0>; - }; - }; - }; - - stmpe1600: stmpe1600@42 { - compatible = "st,stmpe1600"; - reg = <0x42>; - interrupts = <8 3>; - interrupt-parent = <&gpioi>; - interrupt-controller; - wakeup-source; - - stmpegpio: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -&iwdg { - status = "okay"; - timeout-sec = <32>; -}; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins_a>; - pinctrl-names = "default"; - - port { - ltdc_out_rgb: endpoint { - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - pinctrl-names = "default"; - phy-mode = "mii"; - phy-handle = <&phy1>; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdio { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - bus-width = <4>; - max-frequency = <12500000>; -}; - -&timers1 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@2 { - status = "okay"; - }; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts deleted file mode 100644 index a293e65141c6..000000000000 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f746-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32746g-EVAL board"; - compatible = "st,stm32746g-eval", "st,stm32f746"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpiof 10 1>; - linux,default-trigger = "heartbeat"; - }; - led-orange { - gpios = <&stmfx_pinctrl 17 1>; - }; - led-red { - gpios = <&gpiob 7 1>; - }; - led-blue { - gpios = <&stmfx_pinctrl 19 1>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "Wake up"; - linux,code = ; - gpios = <&gpioc 13 0>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; - button-1 { - label = "JoyDown"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - button-3 { - label = "JoyRight"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - button-4 { - label = "JoyUp"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&crc { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - - stmfx_pinctrl: pinctrl { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - drive-push-pull; - bias-pull-up; - }; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdio1 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_a>; - pinctrl-1 = <&sdio_pins_od_a>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi deleted file mode 100644 index 3bb812d6399e..000000000000 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - soc { - pinctrl: pinctrl@40020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = ; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART3_RX */ - bias-disable; - }; - }; - - usbotg_fs_pins_a: usbotg-fs-0 { - pins { - pinmux = , /* OTG_FS_ID */ - , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_b: usbotg-fs-1 { - pins { - pinmux = , /* OTG_HS_ID */ - , /* OTG_HS_DM */ - ; /* OTG_HS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT*/ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ethernet_mii: mii-0 { - pins { - pinmux = , /* ETH_MII_TXD0_ETH_RMII_TXD0 */ - , /* ETH_MII_TXD1_ETH_RMII_TXD1 */ - , /* ETH_MII_TXD2 */ - , /* ETH_MII_TXD3 */ - , /* ETH_MII_TX_CLK */ - , /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ - , /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ - , /* ETH_MII_RXD0_ETH_RMII_RXD0 */ - , /* ETH_MII_RXD1_ETH_RMII_RXD1 */ - , /* ETH_MII_RXD2 */ - ; /* ETH_MII_RXD3 */ - slew-rate = <2>; - }; - }; - - adc3_in8_pin: adc-200 { - pins { - pinmux = ; - }; - }; - - pwm1_pins: pwm1-0 { - pins { - pinmux = , /* TIM1_CH1 */ - , /* TIM1_CH1N */ - ; /* TIM1_BKIN */ - }; - }; - - pwm3_pins: pwm3-0 { - pins { - pinmux = , /* TIM3_CH1 */ - ; /* TIM3_CH2 */ - }; - }; - - i2c1_pins: i2c1-0 { - pins { - pinmux = , /* I2C1_SDA */ - ; /* I2C1_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <3>; - }; - }; - - ltdc_pins_a: ltdc-0 { - pins { - pinmux = , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_CLK */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6*/ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3*/ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - , /* LCD_B7 */ - ; /* LCD_DE */ - slew-rate = <2>; - }; - }; - - ltdc_pins_b: ltdc-1 { - pins { - pinmux = , - /* LCD_HSYNC */ - , - /* LCD_VSYNC */ - , - /* LCD_CLK */ - , - /* LCD_R2 */ - , - /* LCD_R3 */ - , - /* LCD_R4 */ - , - /* LCD_R5 */ - , - /* LCD_R6*/ - , - /* LCD_R7 */ - , - /* LCD_G2 */ - , - /* LCD_G3 */ - , - /* LCD_G4 */ - , - /* LCD_B2 */ - , - /* LCD_B3*/ - , - /* LCD_G5 */ - , - /* LCD_G6 */ - , - /* LCD_G7 */ - , - /* LCD_B4 */ - , - /* LCD_B5 */ - , - /* LCD_B6 */ - , - /* LCD_B7 */ - ; - /* LCD_DE */ - slew-rate = <2>; - }; - }; - - spi5_pins: spi5-0 { - pins1 { - pinmux = , - /* SPI5_CLK */ - ; - /* SPI5_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; - /* SPI5_MISO */ - bias-disable; - }; - }; - - i2c3_pins: i2c3-0 { - pins { - pinmux = , - /* I2C3_SDA */ - ; - /* I2C3_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <3>; - }; - }; - - dcmi_pins: dcmi-0 { - pins { - pinmux = , /* DCMI_HSYNC */ - , /* DCMI_VSYNC */ - , /* DCMI_PIXCLK */ - , /* DCMI_D0 */ - , /* DCMI_D1 */ - , /* DCMI_D2 */ - , /* DCMI_D3 */ - , /*DCMI_D4 */ - , /* DCMI_D5 */ - , /* DCMI_D6 */ - , /* DCMI_D7 */ - , /* DCMI_D8 */ - , /* DCMI_D9 */ - , /* DCMI_D10 */ - ; /* DCMI_D11 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - sdio_pins: sdio-pins-0 { - pins { - pinmux = , /* SDIO_D0 */ - , /* SDIO_D1 */ - , /* SDIO_D2 */ - , /* SDIO_D3 */ - , /* SDIO_CK */ - ; /* SDIO_CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od: sdio-pins-od-0 { - pins1 { - pinmux = , /* SDIO_D0 */ - , /* SDIO_D1 */ - , /* SDIO_D2 */ - , /* SDIO_D3 */ - ; /* SDIO_CK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; /* SDIO_CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - can1_pins_a: can1-0 { - pins1 { - pinmux = ; /* CAN1_TX */ - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-pull-up; - }; - }; - - can2_pins_a: can2-0 { - pins1 { - pinmux = ; /* CAN2_TX */ - }; - pins2 { - pinmux = ; /* CAN2_RX */ - bias-pull-up; - }; - }; - - can2_pins_b: can2-1 { - pins1 { - pinmux = ; /* CAN2_TX */ - }; - pins2 { - pinmux = ; /* CAN2_RX */ - bias-pull-up; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts deleted file mode 100644 index 3b81228d46a2..000000000000 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" -#include "stm32f429-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "STMicroelectronics STM32F429i-DISCO board"; - compatible = "st,stm32f429i-disco", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x800000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - led-red { - gpios = <&gpiog 14 0>; - }; - led-green { - gpios = <&gpiog 13 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "User"; - linux,code = ; - gpios = <&gpioa 0 0>; - }; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - gpio = <&gpioc 4 0>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&crc { - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - status = "okay"; - - stmpe811@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioa>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; -}; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-names = "default"; - - port { - ltdc_out_rgb: endpoint { - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&rtc { - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSI>; - status = "okay"; -}; - -&spi5 { - status = "okay"; - pinctrl-0 = <&spi5_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>; - - l3gd20: l3gd20@0 { - compatible = "st,l3gd20-gyro"; - spi-max-frequency = <10000000>; - st,drdy-int-pin = <2>; - interrupt-parent = <&gpioa>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>, - <2 IRQ_TYPE_EDGE_RISING>; - reg = <0>; - status = "okay"; - }; - - display: display@1{ - /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; - reg = <1>; - spi-3wire; - spi-max-frequency = <10000000>; - dc-gpios = <&gpiod 13 0>; - port { - panel_in_rgb: endpoint { - remote-endpoint = <<dc_out_rgb>; - }; - }; - }; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - compatible = "st,stm32f4x9-fsotg"; - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi deleted file mode 100644 index e10d7a1f3207..000000000000 --- a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "stm32f4-pinctrl.dtsi" - -&pinctrl { - compatible = "st,stm32f429-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; -}; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi deleted file mode 100644 index 00bf53f99c29..000000000000 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ /dev/null @@ -1,799 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_i2s_ckin: i2s-ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - romem: efuse@1fff7800 { - compatible = "st,stm32f4-otp"; - reg = <0x1fff7800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ts_cal1: calib@22c { - reg = <0x22c 0x2>; - }; - ts_cal2: calib@22e { - reg = <0x22e 0x2>; - }; - }; - - timers2: timers@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - }; - - timers3: timers@40000400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000400 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - timers4: timers@40000800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000800 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - }; - - timers5: timers@40000c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000C00 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - }; - - timers6: timers@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - clock-names = "int"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timers@40001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001400 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - clock-names = "int"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timers@40001800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001800 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timers@40001c00 { - compatible = "st,stm32-timers"; - reg = <0x40001C00 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers14: timers@40002000 { - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - iwdg: watchdog@40003000 { - compatible = "st,stm32-iwdg"; - reg = <0x40003000 0x400>; - clocks = <&clk_lsi>; - clock-names = "lsi"; - status = "disabled"; - }; - - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; - status = "disabled"; - }; - - spi3: spi@40003c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40003c00 0x400>; - interrupts = <51>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; - status = "disabled"; - dmas = <&dma1 1 4 0x400 0x0>, - <&dma1 3 4 0x400 0x0>; - dma-names = "rx", "tx"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; - status = "disabled"; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f4-i2c"; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F4_APB1_RESET(I2C1)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@40005c00 { - compatible = "st,stm32f4-i2c"; - reg = <0x40005c00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32F4_APB1_RESET(I2C3)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@40006400 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40006400 0x200>; - interrupts = <19>, <20>, <21>, <22>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F4_APB1_RESET(CAN1)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; - st,can-primary; - st,gcan = <&gcan>; - status = "disabled"; - }; - - gcan: gcan@40006600 { - compatible = "st,stm32f4-gcan", "syscon"; - reg = <0x40006600 0x200>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; - }; - - can2: can@40006800 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40006800 0x200>; - interrupts = <63>, <64>, <65>, <66>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F4_APB1_RESET(CAN2)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; - st,can-secondary; - st,gcan = <&gcan>; - status = "disabled"; - }; - - dac: dac@40007400 { - compatible = "st,stm32f4-dac-core"; - reg = <0x40007400 0x400>; - resets = <&rcc STM32F4_APB1_RESET(DAC)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - usart7: serial@40007800 { - compatible = "st,stm32-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; - status = "disabled"; - }; - - timers1: timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - }; - - timers8: timers@40010400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010400 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; - status = "disabled"; - dmas = <&dma2 2 4 0x400 0x0>, - <&dma2 7 4 0x400 0x0>; - dma-names = "rx", "tx"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; - status = "disabled"; - }; - - adc: adc@40012000 { - compatible = "st,stm32f4-adc-core"; - reg = <0x40012000 0x400>; - interrupts = <18>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; - clock-names = "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dma2 0 0 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dma2 3 1 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - - adc3: adc@200 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x200>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; - interrupt-parent = <&adc>; - interrupts = <2>; - dmas = <&dma2 1 2 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - sdio: mmc@40012c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; - clock-names = "apb_pclk"; - interrupts = <49>; - max-frequency = <48000000>; - status = "disabled"; - }; - - spi1: spi@40013000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40013000 0x400>; - interrupts = <35>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; - status = "disabled"; - }; - - spi4: spi@40013400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40013400 0x400>; - interrupts = <84>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; - status = "disabled"; - }; - - syscfg: syscon@40013800 { - compatible = "st,stm32-syscfg", "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - timers9: timers@40014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014000 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@8 { - compatible = "st,stm32-timer-trigger"; - reg = <8>; - status = "disabled"; - }; - }; - - timers10: timers@40014400 { - compatible = "st,stm32-timers"; - reg = <0x40014400 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers11: timers@40014800 { - compatible = "st,stm32-timers"; - reg = <0x40014800 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - spi5: spi@40015000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40015000 0x400>; - interrupts = <85>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; - dmas = <&dma2 3 2 0x400 0x0>, - <&dma2 4 2 0x400 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi6: spi@40015400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40015400 0x400>; - interrupts = <86>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; - status = "disabled"; - }; - - pwrcfg: power-config@40007000 { - compatible = "st,stm32-power-config", "syscon"; - reg = <0x40007000 0x400>; - }; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - status = "disabled"; - }; - - crc: crc@40023000 { - compatible = "st,stm32f4-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; - status = "disabled"; - }; - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - st,syscfg = <&pwrcfg>; - assigned-clocks = <&rcc 1 CLK_HSE_RTC>; - assigned-clock-rates = <1000000>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; - #dma-cells = <4>; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; - #dma-cells = <4>; - st,mem2mem; - }; - - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - snps,mixed-burst; - status = "disabled"; - }; - - dma2d: dma2d@4002b000 { - compatible = "st,stm32-dma2d"; - reg = <0x4002b000 0xc00>; - interrupts = <90>; - resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; - clock-names = "dma2d"; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "snps,dwc2"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; - clock-names = "otg"; - status = "disabled"; - }; - - usbotg_fs: usb@50000000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x50000000 0x40000>; - interrupts = <67>; - clocks = <&rcc 0 39>; - clock-names = "otg"; - status = "disabled"; - }; - - dcmi: dcmi@50050000 { - compatible = "st,stm32-dcmi"; - reg = <0x50050000 0x400>; - interrupts = <78>; - resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&dcmi_pins>; - dmas = <&dma2 1 1 0x414 0x3>; - dma-names = "tx"; - status = "disabled"; - }; - - rng: rng@50060800 { - compatible = "st,stm32-rng"; - reg = <0x50060800 0x400>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; - - }; - }; -}; - -&systick { - clocks = <&rcc 1 SYSTICK>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts deleted file mode 100644 index cbbd521bf010..000000000000 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright 2016 - Lee Jones - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f469.dtsi" -#include "stm32f469-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32F469i-DISCO board"; - compatible = "st,stm32f469i-disco", "st,stm32f469"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x1000000>; - }; - - aliases { - serial0 = &usart3; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_dsi: vdd-dsi { - compatible = "regulator-fixed"; - regulator-name = "vdd_dsi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - led-orange { - gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; - }; - led-red { - gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; - }; - led-blue { - gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "User"; - linux,code = ; - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - }; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; -}; - -&rcc { - compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&dma2d { - status = "okay"; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - - panel@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; /* dsi virtual channel (0..3) */ - reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; - power-supply = <&vdd_dsi>; - status = "okay"; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -<dc { - status = "okay"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&timers1 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@2 { - status = "okay"; - }; -}; - -&sdio { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart3 { - pinctrl-0 = <&usart3_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_fs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi deleted file mode 100644 index 6bf60263dff8..000000000000 --- a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "stm32f4-pinctrl.dtsi" - -&pinctrl { - compatible = "st,stm32f469-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; -}; diff --git a/arch/arm/boot/dts/stm32f469.dtsi b/arch/arm/boot/dts/stm32f469.dtsi deleted file mode 100644 index be002e8a78ac..000000000000 --- a/arch/arm/boot/dts/stm32f469.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ - -#include "stm32f429.dtsi" - -/ { - soc { - dsi: dsi@40016c00 { - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi deleted file mode 100644 index 9f65403295ca..000000000000 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ /dev/null @@ -1,370 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include -#include - -/ { - soc { - pinctrl: pinctrl@40020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - cec_pins_a: cec-0 { - pins { - pinmux = ; /* HDMI CEC */ - slew-rate = <0>; - drive-open-drain; - bias-disable; - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_pins_b: usart1-1 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - i2c1_pins_b: i2c1-0 { - pins { - pinmux = , /* I2C1 SDA */ - ; /* I2C1 SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_b: usbotg-hs-1 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_a: usbotg-fs-0 { - pins { - pinmux = , /* OTG_FS_ID */ - , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_a: sdio-pins-a-0 { - pins { - pinmux = , /* SDMMC1 D0 */ - , /* SDMMC1 D1 */ - , /* SDMMC1 D2 */ - , /* SDMMC1 D3 */ - , /* SDMMC1 CLK */ - ; /* SDMMC1 CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od_a: sdio-pins-od-a-0 { - pins1 { - pinmux = , /* SDMMC1 D0 */ - , /* SDMMC1 D1 */ - , /* SDMMC1 D2 */ - , /* SDMMC1 D3 */ - ; /* SDMMC1 CLK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; /* SDMMC1 CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - sdio_pins_b: sdio-pins-b-0 { - pins { - pinmux = , /* SDMMC2 D0 */ - , /* SDMMC2 D1 */ - , /* SDMMC2 D2 */ - , /* SDMMC2 D3 */ - , /* SDMMC2 CLK */ - ; /* SDMMC2 CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od_b: sdio-pins-od-b-0 { - pins1 { - pinmux = , /* SDMMC2 D0 */ - , /* SDMMC2 D1 */ - , /* SDMMC2 D2 */ - , /* SDMMC2 D3 */ - ; /* SDMMC2 CLK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; /* SDMMC2 CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - can1_pins_a: can1-0 { - pins1 { - pinmux = ; /* CAN1_TX */ - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-pull-up; - }; - }; - - can1_pins_b: can1-1 { - pins1 { - pinmux = ; /* CAN1_TX */ - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-pull-up; - }; - }; - - can1_pins_c: can1-2 { - pins1 { - pinmux = ; /* CAN1_TX */ - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-pull-up; - - }; - }; - - can1_pins_d: can1-3 { - pins1 { - pinmux = ; /* CAN1_TX */ - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-pull-up; - - }; - }; - - can2_pins_a: can2-0 { - pins1 { - pinmux = ; /* CAN2_TX */ - }; - pins2 { - pinmux = ; /* CAN2_RX */ - bias-pull-up; - }; - }; - - can2_pins_b: can2-1 { - pins1 { - pinmux = ; /* CAN2_TX */ - }; - pins2 { - pinmux = ; /* CAN2_RX */ - bias-pull-up; - }; - }; - - can3_pins_a: can3-0 { - pins1 { - pinmux = ; /* CAN3_TX */ - }; - pins2 { - pinmux = ; /* CAN3_RX */ - bias-pull-up; - }; - }; - - can3_pins_b: can3-1 { - pins1 { - pinmux = ; /* CAN3_TX */ - }; - pins2 { - pinmux = ; /* CAN3_RX */ - bias-pull-up; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts deleted file mode 100644 index c11616ed5fc6..000000000000 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2017 - Vikas MANOCHA - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f746-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32F746-DISCO board"; - compatible = "st,stm32f746-disco", "st,stm32f746"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x800000>; - }; - - aliases { - serial0 = &usart1; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - /* This turns on vbus for otg fs for host mode (dwc2) */ - vcc5v_otg_fs: vcc5v-otg-fs-regulator { - compatible = "regulator-fixed"; - gpio = <&gpiod 5 0>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&sdio1 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_a>; - pinctrl-1 = <&sdio_pins_od_a>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_fs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi deleted file mode 100644 index fcfd2ac7239b..000000000000 --- a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32f7-pinctrl.dtsi" - -&pinctrl{ - compatible = "st,stm32f746-pinctrl"; -}; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi deleted file mode 100644 index e3564b74a779..000000000000 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_i2s_ckin: clk-i2s-ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - }; - - soc { - timers2: timers@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - }; - - timers3: timers@40000400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000400 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - timers4: timers@40000800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000800 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - }; - - timers5: timers@40000c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000C00 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - }; - - timers6: timers@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - clock-names = "int"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timers@40001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001400 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - clock-names = "int"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timers@40001800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001800 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timers@40001c00 { - compatible = "st,stm32-timers"; - reg = <0x40001C00 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers14: timers@40002000 { - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 1 CLK_USART2>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32f7-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 1 CLK_USART3>; - status = "disabled"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32f7-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 1 CLK_UART4>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32f7-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 1 CLK_UART5>; - status = "disabled"; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F7_APB1_RESET(I2C1)>; - clocks = <&rcc 1 CLK_I2C1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@40005800 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005800 0x400>; - interrupts = <33>, - <34>; - resets = <&rcc STM32F7_APB1_RESET(I2C2)>; - clocks = <&rcc 1 CLK_I2C2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@40005c00 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005c00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32F7_APB1_RESET(I2C3)>; - clocks = <&rcc 1 CLK_I2C3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@40006000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40006000 0x400>; - interrupts = <95>, - <96>; - resets = <&rcc STM32F7_APB1_RESET(I2C4)>; - clocks = <&rcc 1 CLK_I2C4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - cec: cec@40006c00 { - compatible = "st,stm32-cec"; - reg = <0x40006C00 0x400>; - interrupts = <94>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - usart7: serial@40007800 { - compatible = "st,stm32f7-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 1 CLK_UART7>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32f7-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 1 CLK_UART8>; - status = "disabled"; - }; - - timers1: timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - }; - - timers8: timers@40010400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010400 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 1 CLK_USART1>; - status = "disabled"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32f7-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 1 CLK_USART6>; - status = "disabled"; - }; - - sdio2: mmc@40011c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40011c00 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; - clock-names = "apb_pclk"; - interrupts = <103>; - max-frequency = <48000000>; - status = "disabled"; - }; - - sdio1: mmc@40012c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; - clock-names = "apb_pclk"; - interrupts = <49>; - max-frequency = <48000000>; - status = "disabled"; - }; - - syscfg: syscon@40013800 { - compatible = "st,stm32-syscfg", "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - timers9: timers@40014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014000 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@8 { - compatible = "st,stm32-timer-trigger"; - reg = <8>; - status = "disabled"; - }; - }; - - timers10: timers@40014400 { - compatible = "st,stm32-timers"; - reg = <0x40014400 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers11: timers@40014800 { - compatible = "st,stm32-timers"; - reg = <0x40014800 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - pwrcfg: power-config@40007000 { - compatible = "st,stm32-power-config", "syscon"; - reg = <0x40007000 0x400>; - }; - - crc: crc@40023000 { - compatible = "st,stm32f7-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; - status = "disabled"; - }; - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f746-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - st,syscfg = <&pwrcfg>; - assigned-clocks = <&rcc 1 CLK_HSE_RTC>; - assigned-clock-rates = <1000000>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; - #dma-cells = <4>; - status = "disabled"; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; - #dma-cells = <4>; - st,mem2mem; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "st,stm32f7-hsotg"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; - clock-names = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - usbotg_fs: usb@50000000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x50000000 0x40000>; - interrupts = <67>; - clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; - clock-names = "otg"; - status = "disabled"; - }; - }; -}; - -&systick { - clocks = <&rcc 1 0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts deleted file mode 100644 index b038d0ed39e8..000000000000 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright 2017 - Vikas MANOCHA - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f769-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f769"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x1000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - led-red { - gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "User"; - linux,code = ; - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - }; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&rcc { - compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - -&cec { - pinctrl-0 = <&cec_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdio2 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_b>; - pinctrl-1 = <&sdio_pins_od_b>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi deleted file mode 100644 index 31005dd9929c..000000000000 --- a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32f7-pinctrl.dtsi" - -&pinctrl{ - compatible = "st,stm32f769-pinctrl"; -}; diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi deleted file mode 100644 index aa1bc3e10a49..000000000000 --- a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -&pinctrl { - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - spi1_pins: spi1-0 { - pins1 { - pinmux = , - /* SPI1_CLK */ - ; - /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; - /* SPI1_MISO */ - bias-disable; - }; - }; - - uart4_pins: uart4-0 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = ; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usart3_pins: usart3-0 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_RTS_DE */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART3_RX */ - ; /* USART3_CTS_NSS */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* ULPI_NXT */ - , /* ULPI_DIR> */ - , /* ULPI_STP> */ - , /* ULPI_CK> */ - , /* ULPI_D0> */ - , /* ULPI_D1> */ - , /* ULPI_D2> */ - , /* ULPI_D3> */ - , /* ULPI_D4> */ - , /* ULPI_D5> */ - , /* ULPI_D6> */ - ; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi deleted file mode 100644 index f30796f7adf3..000000000000 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ /dev/null @@ -1,730 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_i2s: i2s_ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; - }; - - lptimer1: timer@40002400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40002400 0x400>; - clocks = <&rcc LPTIM1_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; - clocks = <&rcc SPI2_CK>; - status = "disabled"; - - }; - - spi3: spi@40003c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003c00 0x400>; - interrupts = <51>; - resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; - clocks = <&rcc SPI3_CK>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32h7-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - status = "disabled"; - clocks = <&rcc USART2_CK>; - }; - - usart3: serial@40004800 { - compatible = "st,stm32h7-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - status = "disabled"; - clocks = <&rcc USART3_CK>; - }; - - uart4: serial@40004c00 { - compatible = "st,stm32h7-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - status = "disabled"; - clocks = <&rcc UART4_CK>; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; - clocks = <&rcc I2C1_CK>; - status = "disabled"; - }; - - i2c2: i2c@40005800 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005800 0x400>; - interrupts = <33>, - <34>; - resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; - clocks = <&rcc I2C2_CK>; - status = "disabled"; - }; - - i2c3: i2c@40005c00 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005C00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; - clocks = <&rcc I2C3_CK>; - status = "disabled"; - }; - - dac: dac@40007400 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40007400 0x400>; - clocks = <&rcc DAC12_CK>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - status = "disabled"; - clocks = <&rcc USART1_CK>; - }; - - spi1: spi@40013000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40013000 0x400>; - interrupts = <35>; - resets = <&rcc STM32H7_APB2_RESET(SPI1)>; - clocks = <&rcc SPI1_CK>; - status = "disabled"; - }; - - spi4: spi@40013400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40013400 0x400>; - interrupts = <84>; - resets = <&rcc STM32H7_APB2_RESET(SPI4)>; - clocks = <&rcc SPI4_CK>; - status = "disabled"; - }; - - spi5: spi@40015000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40015000 0x400>; - interrupts = <85>; - resets = <&rcc STM32H7_APB2_RESET(SPI5)>; - clocks = <&rcc SPI5_CK>; - status = "disabled"; - }; - - dma1: dma-controller@40020000 { - compatible = "st,stm32-dma"; - reg = <0x40020000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc DMA1_CK>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dma2: dma-controller@40020400 { - compatible = "st,stm32-dma"; - reg = <0x40020400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc DMA2_CK>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dmamux1: dma-router@40020800 { - compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x40>; - #dma-cells = <3>; - dma-channels = <16>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - clocks = <&rcc DMA1_CK>; - }; - - adc_12: adc@40022000 { - compatible = "st,stm32h7-adc-core"; - reg = <0x40022000 0x400>; - interrupts = <18>; - clocks = <&rcc ADC12_CK>; - clock-names = "bus"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc_12>; - interrupts = <0>; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - interrupt-parent = <&adc_12>; - interrupts = <1>; - status = "disabled"; - }; - }; - - usbotg_hs: usb@40040000 { - compatible = "st,stm32f7-hsotg"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc USB1OTG_CK>; - clock-names = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - usbotg_fs: usb@40080000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x40080000 0x40000>; - interrupts = <101>; - clocks = <&rcc USB2OTG_CK>; - clock-names = "otg"; - status = "disabled"; - }; - - ltdc: display-controller@50001000 { - compatible = "st,stm32-ltdc"; - reg = <0x50001000 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32H7_APB3_RESET(LTDC)>; - clocks = <&rcc LTDC_CK>; - clock-names = "lcd"; - status = "disabled"; - }; - - mdma1: dma-controller@52000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x52000000 0x1000>; - interrupts = <122>; - clocks = <&rcc MDMA_CK>; - #dma-cells = <5>; - dma-channels = <16>; - dma-requests = <32>; - }; - - sdmmc1: mmc@52007000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x52007000 0x1000>; - interrupts = <49>; - clocks = <&rcc SDMMC1_CK>; - clock-names = "apb_pclk"; - resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - }; - - sdmmc2: mmc@48022400 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x48022400 0x400>; - interrupts = <124>; - clocks = <&rcc SDMMC2_CK>; - clock-names = "apb_pclk"; - resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - exti: interrupt-controller@58000000 { - compatible = "st,stm32h7-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x58000000 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; - }; - - syscfg: syscon@58000400 { - compatible = "st,stm32-syscfg", "syscon"; - reg = <0x58000400 0x400>; - }; - - spi6: spi@58001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x58001400 0x400>; - interrupts = <86>; - resets = <&rcc STM32H7_APB4_RESET(SPI6)>; - clocks = <&rcc SPI6_CK>; - status = "disabled"; - }; - - i2c4: i2c@58001c00 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x58001C00 0x400>; - interrupts = <95>, - <96>; - resets = <&rcc STM32H7_APB4_RESET(I2C4)>; - clocks = <&rcc I2C4_CK>; - status = "disabled"; - }; - - lptimer2: timer@58002400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002400 0x400>; - clocks = <&rcc LPTIM2_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@58002800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002800 0x400>; - clocks = <&rcc LPTIM3_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@58002c00 { - compatible = "st,stm32-lptimer"; - reg = <0x58002c00 0x400>; - clocks = <&rcc LPTIM4_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@58003000 { - compatible = "st,stm32-lptimer"; - reg = <0x58003000 0x400>; - clocks = <&rcc LPTIM5_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: regulator@58003c00 { - compatible = "st,stm32-vrefbuf"; - reg = <0x58003C00 0x8>; - clocks = <&rcc VREF_CK>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - status = "disabled"; - }; - - rtc: rtc@58004000 { - compatible = "st,stm32h7-rtc"; - reg = <0x58004000 0x400>; - clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; - clock-names = "pclk", "rtc_ck"; - assigned-clocks = <&rcc RTC_CK>; - assigned-clock-parents = <&rcc LSE_CK>; - interrupt-parent = <&exti>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - rcc: reset-clock-controller@58024400 { - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; - st,syscfg = <&pwrcfg>; - }; - - pwrcfg: power-config@58024800 { - compatible = "st,stm32-power-config", "syscon"; - reg = <0x58024800 0x400>; - }; - - adc_3: adc@58026000 { - compatible = "st,stm32h7-adc-core"; - reg = <0x58026000 0x400>; - interrupts = <127>; - clocks = <&rcc ADC3_CK>; - clock-names = "bus"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc3: adc@0 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc_3>; - interrupts = <0>; - status = "disabled"; - }; - }; - - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - status = "disabled"; - }; - - pinctrl: pinctrl@58020000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; - }; -}; - -&systick { - clock-frequency = <250000000>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts deleted file mode 100644 index 2b452883a708..000000000000 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2017 - Patrice Chotard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32h743.dtsi" -#include "stm32h7-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32H743i-Discovery board"; - compatible = "st,stm32h743i-disco", "st,stm32h743"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@d0000000 { - device_type = "memory"; - reg = <0xd0000000 0x2000000>; - }; - - aliases { - serial0 = &usart2; - }; - - v3v3: regulator-v3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&usart2 { - pinctrl-0 = <&usart2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts deleted file mode 100644 index 5c5d8059bdc7..000000000000 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32h743.dtsi" -#include "stm32h7-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32H743i-EVAL board"; - compatible = "st,stm32h743i-eval", "st,stm32h743"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@d0000000 { - device_type = "memory"; - reg = <0xd0000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2v9_sd: regulator-v2v9_sd { - compatible = "regulator-fixed"; - regulator-name = "v2v9_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc USB1ULPI_CK>; - clock-names = "main_clk"; - }; -}; - -&adc_12 { - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - adc1: adc@0 { - /* potentiometer */ - st,adc-channels = <0>; - status = "okay"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&v2v9_sd>; - status = "okay"; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - dr_mode = "otg"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/stm32h750.dtsi deleted file mode 100644 index 41e3b1e3a874..000000000000 --- a/arch/arm/boot/dts/stm32h750.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ - -#include "stm32h743.dtsi" - - diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts deleted file mode 100644 index 44c307f8b09c..000000000000 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2021 - Dillon Min - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * For art-pi board resources, you can refer to link: - * https://art-pi.gitee.io/website/ - */ - -/dts-v1/; -#include "stm32h750.dtsi" -#include "stm32h7-pinctrl.dtsi" -#include -#include - -/ { - model = "RT-Thread STM32H750i-ART-PI board"; - compatible = "st,stm32h750i-art-pi", "st,stm32h750"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:2000000n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x2000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - no-map; - size = <0x100000>; - linux,dma-default; - }; - }; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - }; - - leds { - compatible = "gpio-leds"; - led-red { - gpios = <&gpioi 8 0>; - }; - led-green { - gpios = <&gpioc 15 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - v3v3: regulator-v3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - wlan_pwr: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&dma1 { - status = "okay"; -}; - -&dma2 { - status = "okay"; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; - broken-cd; - non-removable; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&wlan_pwr>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - - partition@0 { - label = "root filesystem"; - reg = <0 0x1000000>; - }; - }; -}; - -&usart2 { - pinctrl-0 = <&usart2_pins>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins>; - dmas = <&dmamux1 45 0x400 0x05>, - <&dmamux1 46 0x400 0x05>; - dma-names = "rx", "tx"; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; - max-speed = <115200>; - }; -}; - -&uart4 { - pinctrl-0 = <&uart4_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - - diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi deleted file mode 100644 index 27e0c3826789..000000000000 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue - */ -#include - -&pinctrl { - adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { - pins { - pinmux = , /* ADC1 in6 */ - ; /* ADC1 in12 */ - }; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_sleep_pins_a: i2c1-sleep-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; - }; - - i2c5_pins_a: i2c5-0 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_a: i2c5-sleep-0 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - }; - }; - - mcp23017_pins_a: mcp23017-0 { - pins { - pinmux = ; - bias-pull-up; - }; - }; - - pwm3_pins_a: pwm3-0 { - pins { - pinmux = ; /* TIM3_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_a: pwm3-sleep-0 { - pins { - pinmux = ; /* TIM3_CH4 */ - }; - }; - - pwm4_pins_a: pwm4-0 { - pins { - pinmux = ; /* TIM4_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_a: pwm4-sleep-0 { - pins { - pinmux = ; /* TIM4_CH2 */ - }; - }; - - pwm8_pins_a: pwm8-0 { - pins { - pinmux = ; /* TIM8_CH3 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm8_sleep_pins_a: pwm8-sleep-0 { - pins { - pinmux = ; /* TIM8_CH3 */ - }; - }; - - pwm14_pins_a: pwm14-0 { - pins { - pinmux = ; /* TIM14_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm14_sleep_pins_a: pwm14-sleep-0 { - pins { - pinmux = ; /* TIM14_CH1 */ - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - ; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_clk_pins_a: sdmmc1-clk-0 { - pins { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - , /* SDMMC2_CK */ - ; /* SDMMC2_CMD */ - }; - }; - - sdmmc2_clk_pins_a: sdmmc2-clk-0 { - pins { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - spi5_pins_a: spi5-0 { - pins1 { - pinmux = , /* SPI5_SCK */ - ; /* SPI5_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI5_MISO */ - bias-disable; - }; - }; - - spi5_sleep_pins_a: spi5-sleep-0 { - pins { - pinmux = , /* SPI5_SCK */ - , /* SPI5_MISO */ - ; /* SPI5_MOSI */ - }; - }; - - stm32g0_intn_pins_a: stm32g0-intn-0 { - pins { - pinmux = ; - bias-pull-up; - }; - }; - - uart4_pins_a: uart4-0 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_sleep_pins_a: uart4-sleep-0 { - pins { - pinmux = , /* UART4_TX */ - ; /* UART4_RX */ - }; - }; - - uart8_pins_a: uart8-0 { - pins1 { - pinmux = ; /* UART8_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART8_RX */ - bias-pull-up; - }; - }; - - uart8_idle_pins_a: uart8-idle-0 { - pins1 { - pinmux = ; /* UART8_TX */ - }; - pins2 { - pinmux = ; /* UART8_RX */ - bias-pull-up; - }; - }; - - uart8_sleep_pins_a: uart8-sleep-0 { - pins { - pinmux = , /* UART8_TX */ - ; /* UART8_RX */ - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = , /* USART1_TX */ - ; /* USART1_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART1_RX */ - ; /* USART1_CTS_NSS */ - bias-pull-up; - }; - }; - - usart1_idle_pins_a: usart1-idle-0 { - pins1 { - pinmux = , /* USART1_TX */ - ; /* USART1_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART1_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = ; /* USART1_RX */ - bias-pull-up; - }; - }; - - usart1_sleep_pins_a: usart1-sleep-0 { - pins { - pinmux = , /* USART1_TX */ - , /* USART1_RTS */ - , /* USART1_CTS_NSS */ - ; /* USART1_RX */ - }; - }; - - usart2_pins_a: usart2-0 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_idle_pins_a: usart2-idle-0 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = , /* USART2_TX */ - , /* USART2_RTS */ - , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi deleted file mode 100644 index d163c267e34c..000000000000 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ /dev/null @@ -1,1510 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>; - interrupt-parent = <&intc>; - }; - - firmware { - optee { - method = "smc"; - compatible = "linaro,optee-tz"; - }; - - scmi: scmi { - compatible = "linaro,scmi-optee"; - #address-cells = <1>; - #size-cells = <0>; - linaro,optee-channel-id = <0>; - shmem = <&scmi_shm>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - intc: interrupt-controller@a0021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xa0021000 0x1000>, - <0xa0022000 0x2000>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&intc>; - always-on; - }; - - /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ - reg11: reg11 { - compatible = "regulator-fixed"; - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - compatible = "regulator-fixed"; - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - compatible = "regulator-fixed"; - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi-sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4000b000 0x400>; - #sound-dai-cells = <0>; - interrupts = ; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi2: spi@4000b000 { - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = ; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4000c000 0x400>; - #sound-dai-cells = <0>; - interrupts = ; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi3: spi@4000c000 { - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = ; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - reg = <0x4000d000 0x400>; - #sound-dai-cells = <0>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = ; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; - - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - resets = <&rcc USART3_R>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x5>, - <&dmamux1 46 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - resets = <&rcc UART4_R>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x5>, - <&dmamux1 64 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - resets = <&rcc UART5_R>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x5>, - <&dmamux1 66 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c1: i2c@40012000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 33 0x400 0x1>, - <&dmamux1 34 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c2: i2c@40013000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 35 0x400 0x1>, - <&dmamux1 36 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - i2c-analog-filter; - status = "disabled"; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - resets = <&rcc UART7_R>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x5>, - <&dmamux1 80 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - resets = <&rcc UART8_R>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x5>, - <&dmamux1 82 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - resets = <&rcc USART6_R>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x5>, - <&dmamux1 72 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - reg = <0x44004000 0x400>; - #sound-dai-cells = <0>; - interrupts = ; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = ; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - ranges = <0 0x4400a000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = ; - resets = <&rcc SAI1_R>; - status = "disabled"; - - sai1a: audio-controller@4400a004 { - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; - - sai1b: audio-controller@4400a024 { - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; - }; - }; - - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - ranges = <0 0x4400b000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = ; - resets = <&rcc SAI2_R>; - status = "disabled"; - - sai2a: audio-controller@4400b004 { - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; - - sai2b: audio-controller@4400b024 { - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; - }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - reg = <0>; - #io-channel-cells = <1>; - interrupts = ; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - reg = <1>; - #io-channel-cells = <1>; - interrupts = ; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - clocks = <&rcc DMAMUX1>; - resets = <&rcc DMAMUX1_R>; - #dma-cells = <3>; - dma-masters = <&dma1 &dma2>; - dma-requests = <128>; - dma-channels = <16>; - }; - - adc_2: adc@48004000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48004000 0x400>; - interrupts = ; - clocks = <&rcc ADC2>, <&rcc ADC2_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc2: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_2>; - interrupts = <0>; - dmas = <&dmamux1 10 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - channel@16 { - reg = <16>; - label = "vddcpu"; - }; - channel@17 { - reg = <17>; - label = "vddq_ddr"; - }; - }; - }; - - usbotg_hs: usb@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x40000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; - - usart1: serial@4c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - resets = <&rcc USART1_R>; - wakeup-source; - dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart2: serial@4c001000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c001000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - resets = <&rcc USART2_R>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s4: audio-controller@4c002000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4c002000 0x400>; - #sound-dai-cells = <0>; - interrupts = ; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@4c002000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c002000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi5: spi@4c003000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c003000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 85 0x400 0x01>, - <&dmamux1 86 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c3: i2c@4c004000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c004000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 73 0x400 0x1>, - <&dmamux1 74 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c4: i2c@4c005000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c005000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 75 0x400 0x1>, - <&dmamux1 76 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@4c006000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c006000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 115 0x400 0x1>, - <&dmamux1 116 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - i2c-analog-filter; - status = "disabled"; - }; - - timers12: timer@4c007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@4c008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@4c009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c009000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - timers15: timer@4c00a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00a000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@4c00b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00b000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@4c00c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00c000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - - rcc: rcc@50000000 { - compatible = "st,stm32mp13-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; - }; - - exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp13-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; - - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - mdma: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = ; - clocks = <&rcc MDMA>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; - - fmc: memory-controller@58002000 { - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - #address-cells = <2>; - #size-cells = <1>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - nand-controller@4,0 { - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, - <&mdma 24 0x2 0x12000a08 0x0 0x0>, - <&mdma 25 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, - <&mdma 26 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - usbh_ohci: usb@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - status = "disabled"; - }; - - usbh_ehci: usb@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scmi_clk CK_SCMI_RTCAPB>, - <&scmi_clk CK_SCMI_RTC>; - clock-names = "pclk", "rtc_ck"; - status = "disabled"; - }; - - bsec: efuse@5c005000 { - compatible = "st,stm32mp13-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - part_number_otp: part_number_otp@4 { - reg = <0x4 0x2>; - bits = <0 12>; - }; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; - }; - - /* - * Break node order to solve dependency probe issue between - * pinctrl and exti. - */ - pinctrl: pinctrl@50002000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp135-pinctrl"; - ranges = <0 0x50002000 0x8400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioa: gpio@50002000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA>; - st,bank-name = "GPIOA"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOB>; - st,bank-name = "GPIOB"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOC>; - st,bank-name = "GPIOC"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x400>; - clocks = <&rcc GPIOD>; - st,bank-name = "GPIOD"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x400>; - clocks = <&rcc GPIOE>; - st,bank-name = "GPIOE"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x400>; - clocks = <&rcc GPIOF>; - st,bank-name = "GPIOF"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x400>; - clocks = <&rcc GPIOG>; - st,bank-name = "GPIOG"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x400>; - clocks = <&rcc GPIOH>; - st,bank-name = "GPIOH"; - ngpios = <15>; - gpio-ranges = <&pinctrl 0 112 15>; - }; - - gpioi: gpio@5000a000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x400>; - clocks = <&rcc GPIOI>; - st,bank-name = "GPIOI"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 128 8>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi deleted file mode 100644 index df451c3c2a26..000000000000 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32mp131.dtsi" - -/ { - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - adc_1: adc@48003000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48003000 0x400>; - interrupts = ; - clocks = <&rcc ADC1>, <&rcc ADC1_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_1>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@18 { - reg = <18>; - label = "vrefint"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp135.dtsi b/arch/arm/boot/dts/stm32mp135.dtsi deleted file mode 100644 index abf2acd37b4e..000000000000 --- a/arch/arm/boot/dts/stm32mp135.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32mp133.dtsi" - -/ { - soc { - }; -}; diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts deleted file mode 100644 index f0900ca672b5..000000000000 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ /dev/null @@ -1,370 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include -#include -#include -#include "stm32mp135.dtsi" -#include "stm32mp13xf.dtsi" -#include "stm32mp13-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32MP135F-DK Discovery Board"; - compatible = "st,stm32mp135f-dk", "st,stm32mp135"; - - aliases { - serial0 = &uart4; - serial1 = &usart1; - serial2 = &uart8; - serial3 = &usart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - optee@dd000000 { - reg = <0xdd000000 0x3000000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-user { - label = "User-PA13"; - linux,code = ; - gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - v3v3_sw: v3v3-sw { - compatible = "regulator-fixed"; - regulator-name = "v3v3_sw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_adc: vdd-adc { - compatible = "regulator-fixed"; - regulator-name = "vdd_adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd: vdd-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - vdd_usb: vdd-usb { - compatible = "regulator-fixed"; - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&adc_1 { - pinctrl-names = "default"; - pinctrl-0 = <&adc1_usb_cc_pins_a>; - vdda-supply = <&vdd_adc>; - vref-supply = <&vdd_adc>; - status = "okay"; - adc1: adc@0 { - status = "okay"; - /* - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: - * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. - * Use arbitrary margin here (e.g. 5us). - */ - channel@6 { - reg = <6>; - st,min-sample-time-ns = <5000>; - }; - channel@12 { - reg = <12>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <96>; - i2c-scl-falling-time-ns = <3>; - clock-frequency = <1000000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - mcp23017: pinctrl@21 { - compatible = "microchip,mcp23017"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpiog>; - pinctrl-names = "default"; - pinctrl-0 = <&mcp23017_pins_a>; - interrupt-controller; - #interrupt-cells = <2>; - microchip,irq-mirror; - }; - - typec@53 { - compatible = "st,stm32g0-typec"; - reg = <0x53>; - /* Alert pin on PI2 */ - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioi>; - /* Internal pull-up on PI2 */ - pinctrl-names = "default"; - pinctrl-0 = <&stm32g0_intn_pins_a>; - firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - - port { - con_usb_c_g0_ep: endpoint { - remote-endpoint = <&usbotg_hs_ep>; - }; - }; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <170>; - i2c-scl-falling-time-ns = <5>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&spi5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_pins_a>; - pinctrl-1 = <&spi5_sleep_pins_a>; - status = "disabled"; -}; - -&timers3 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm3_pins_a>; - pinctrl-1 = <&pwm3_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@2 { - status = "okay"; - }; -}; - -&timers4 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm4_pins_a>; - pinctrl-1 = <&pwm4_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@3 { - status = "okay"; - }; -}; - -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-1 = <&pwm8_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@7 { - status = "okay"; - }; -}; - -&timers14 { - status = "disabled"; - pwm { - pinctrl-0 = <&pwm14_pins_a>; - pinctrl-1 = <&pwm14_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@13 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart8_pins_a>; - pinctrl-1 = <&uart8_sleep_pins_a>; - pinctrl-2 = <&uart8_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; -}; - -&usart1 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart1_pins_a>; - pinctrl-1 = <&usart1_sleep_pins_a>; - pinctrl-2 = <&usart1_idle_pins_a>; - uart-has-rtscts; - status = "disabled"; -}; - -/* Bluetooth */ -&usart2 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_sleep_pins_a>; - pinctrl-2 = <&usart2_idle_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - /* onboard HUB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - vdd-supply = <&v3v3_sw>; - }; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - usb-role-switch; - status = "okay"; - port { - usbotg_hs_ep: endpoint { - remote-endpoint = <&con_usb_c_g0_ep>; - }; - }; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - st,current-boost-microamp = <1000>; - st,decrease-hs-slew-rate; - st,tune-hs-dc-level = <2>; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <11>; - st,trim-hs-impedance = <2>; - st,tune-squelch-level = <1>; - st,enable-hs-rx-gain-eq; - st,no-hs-ftime-ctrl; - st,no-lsfs-sc; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - st,current-boost-microamp = <1000>; - st,decrease-hs-slew-rate; - st,tune-hs-dc-level = <2>; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <11>; - st,trim-hs-impedance = <2>; - st,tune-squelch-level = <1>; - st,enable-hs-rx-gain-eq; - st,no-hs-ftime-ctrl; - st,no-lsfs-sc; -}; diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi deleted file mode 100644 index 4d00e7592882..000000000000 --- a/arch/arm/boot/dts/stm32mp13xc.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi deleted file mode 100644 index 4d00e7592882..000000000000 --- a/arch/arm/boot/dts/stm32mp13xf.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi deleted file mode 100644 index 06e969aa5fdb..000000000000 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ /dev/null @@ -1,2697 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -#include - -&pinctrl { - adc1_in6_pins_a: adc1-in6-0 { - pins { - pinmux = ; - }; - }; - - adc12_ain_pins_a: adc12-ain-0 { - pins { - pinmux = , /* ADC1 in13 */ - , /* ADC1 in6 */ - , /* ADC2 in2 */ - ; /* ADC2 in6 */ - }; - }; - - adc12_ain_pins_b: adc12-ain-1 { - pins { - pinmux = , /* ADC1 in6 */ - ; /* ADC2 in2 */ - }; - }; - - adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { - pins { - pinmux = , /* ADC12 in18 */ - ; /* ADC12 in19 */ - }; - }; - - cec_pins_a: cec-0 { - pins { - pinmux = ; - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - cec_sleep_pins_a: cec-sleep-0 { - pins { - pinmux = ; /* HDMI_CEC */ - }; - }; - - cec_pins_b: cec-1 { - pins { - pinmux = ; - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - cec_sleep_pins_b: cec-sleep-1 { - pins { - pinmux = ; /* HDMI_CEC */ - }; - }; - - dac_ch1_pins_a: dac-ch1-0 { - pins { - pinmux = ; - }; - }; - - dac_ch2_pins_a: dac-ch2-0 { - pins { - pinmux = ; - }; - }; - - dcmi_pins_a: dcmi-0 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ,/* DCMI_D7 */ - ,/* DCMI_D8 */ - ,/* DCMI_D9 */ - ,/* DCMI_D10 */ - ;/* DCMI_D11 */ - bias-disable; - }; - }; - - dcmi_sleep_pins_a: dcmi-sleep-0 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ,/* DCMI_D7 */ - ,/* DCMI_D8 */ - ,/* DCMI_D9 */ - ,/* DCMI_D10 */ - ;/* DCMI_D11 */ - }; - }; - - dcmi_pins_b: dcmi-1 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ;/* DCMI_D7 */ - bias-disable; - }; - }; - - dcmi_sleep_pins_b: dcmi-sleep-1 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ;/* DCMI_D7 */ - }; - }; - - dcmi_pins_c: dcmi-2 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ,/* DCMI_D7 */ - ,/* DCMI_D8 */ - ;/* DCMI_D9 */ - bias-pull-up; - }; - }; - - dcmi_sleep_pins_c: dcmi-sleep-2 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ,/* DCMI_D7 */ - ,/* DCMI_D8 */ - ;/* DCMI_D9 */ - }; - }; - - ethernet0_rgmii_pins_a: rgmii-0 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_b: rgmii-1 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - , /* ETH_MDC */ - , /* ETH_MDIO */ - , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_c: rgmii-2 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_d: rgmii-3 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rmii_pins_a: rmii-0 { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_RMII_REF_CLK */ - , /* ETH1_MDIO */ - ; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - ; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_MDIO */ - , /* ETH1_MDC */ - , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK */ - ; /* ETH1_RMII_CRS_DV */ - }; - }; - - ethernet0_rmii_pins_b: rmii-1 { - pins1 { - pinmux = , /* ETH1_CLK */ - , /* ETH1_MDC */ - , /* ETH1_TXD0 */ - ; /* ETH1_TXD1 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* ETH1_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = , /* ETH1_CRS_DV */ - , /* ETH1_RXD0 */ - ; /* ETH1_RXD1 */ - bias-disable; - }; - pins4 { - pinmux = ; /* ETH1_TX_EN */ - }; - }; - - ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { - pins1 { - pinmux = , /* ETH1_MDIO */ - , /* ETH1_CRS_DV */ - , /* ETH1_CLK */ - , /* ETH1_TX_EN */ - , /* ETH1_MDC */ - , /* ETH1_RXD0 */ - , /* ETH1_RXD1 */ - , /* ETH1_TXD0 */ - ; /* ETH1_TXD1 */ - }; - }; - - ethernet0_rmii_pins_c: rmii-2 { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_RMII_REF_CLK */ - , /* ETH1_MDIO */ - ; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - ; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_MDIO */ - , /* ETH1_MDC */ - , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK */ - ; /* ETH1_RMII_CRS_DV */ - }; - }; - - fmc_pins_a: fmc-0 { - pins1 { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_A16_FMC_CLE */ - , /* FMC_A17_FMC_ALE */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - ; /* FMC_NE2_FMC_NCE */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* FMC_NWAIT */ - bias-pull-up; - }; - }; - - fmc_sleep_pins_a: fmc-sleep-0 { - pins { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_A16_FMC_CLE */ - , /* FMC_A17_FMC_ALE */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - , /* FMC_NWAIT */ - ; /* FMC_NE2_FMC_NCE */ - }; - }; - - fmc_pins_b: fmc-1 { - pins { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_NL */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - , /* FMC_D8 */ - , /* FMC_D9 */ - , /* FMC_D10 */ - , /* FMC_D11 */ - , /* FMC_D12 */ - , /* FMC_D13 */ - , /* FMC_D14 */ - , /* FMC_D15 */ - , /* FMC_NE2_FMC_NCE */ - ; /* FMC_NE4 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - fmc_sleep_pins_b: fmc-sleep-1 { - pins { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_NL */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - , /* FMC_D8 */ - , /* FMC_D9 */ - , /* FMC_D10 */ - , /* FMC_D11 */ - , /* FMC_D12 */ - , /* FMC_D13 */ - , /* FMC_D14 */ - , /* FMC_D15 */ - , /* FMC_NE2_FMC_NCE */ - ; /* FMC_NE4 */ - }; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_sleep_pins_a: i2c1-sleep-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; - }; - - i2c1_pins_b: i2c1-1 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_sleep_pins_b: i2c1-sleep-1 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; - }; - - i2c2_pins_a: i2c2-0 { - pins { - pinmux = , /* I2C2_SCL */ - ; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_sleep_pins_a: i2c2-sleep-0 { - pins { - pinmux = , /* I2C2_SCL */ - ; /* I2C2_SDA */ - }; - }; - - i2c2_pins_b1: i2c2-1 { - pins { - pinmux = ; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_sleep_pins_b1: i2c2-sleep-1 { - pins { - pinmux = ; /* I2C2_SDA */ - }; - }; - - i2c2_pins_c: i2c2-2 { - pins { - pinmux = , /* I2C2_SCL */ - ; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_pins_sleep_c: i2c2-sleep-2 { - pins { - pinmux = , /* I2C2_SCL */ - ; /* I2C2_SDA */ - }; - }; - - i2c5_pins_a: i2c5-0 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_a: i2c5-sleep-0 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - - }; - }; - - i2c5_pins_b: i2c5-1 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_b: i2c5-sleep-1 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - }; - }; - - i2s2_pins_a: i2s2-0 { - pins { - pinmux = , /* I2S2_SDO */ - , /* I2S2_WS */ - ; /* I2S2_CK */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - i2s2_sleep_pins_a: i2s2-sleep-0 { - pins { - pinmux = , /* I2S2_SDO */ - , /* I2S2_WS */ - ; /* I2S2_CK */ - }; - }; - - ltdc_pins_a: ltdc-0 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_sleep_pins_a: ltdc-sleep-0 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - }; - }; - - ltdc_pins_b: ltdc-1 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_sleep_pins_b: ltdc-sleep-1 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - }; - }; - - ltdc_pins_c: ltdc-2 { - pins1 { - pinmux = , /* LTDC_R6 */ - , /* LTDC_B7 */ - , /* LTDC_R5 */ - , /* LTDC_G7 */ - , /* LTDC_B2 */ - , /* LTDC_B3 */ - , /* LTDC_G3 */ - , /* LTDC_B4 */ - , /* LTDC_DE */ - , /* LTDC_R7 */ - , /* LTDC_G5 */ - , /* LTDC_R2 */ - , /* LTDC_R3 */ - , /* LTDC_R4 */ - , /* LTDC_G2 */ - , /* LTDC_G4 */ - , /* LTDC_G6 */ - , /* LTDC_B5 */ - , /* LTDC_B6 */ - , /* LTDC_VSYNC */ - ; /* LTDC_HSYNC */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* LTDC_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_sleep_pins_c: ltdc-sleep-2 { - pins1 { - pinmux = , /* LTDC_R6 */ - , /* LTDC_B7 */ - , /* LTDC_R5 */ - , /* LTDC_G7 */ - , /* LTDC_B2 */ - , /* LTDC_B3 */ - , /* LTDC_G3 */ - , /* LTDC_B4 */ - , /* LTDC_DE */ - , /* LTDC_R7 */ - , /* LTDC_G5 */ - , /* LTDC_R2 */ - , /* LTDC_R3 */ - , /* LTDC_R4 */ - , /* LTDC_G2 */ - , /* LTDC_G4 */ - , /* LTDC_G6 */ - , /* LTDC_B5 */ - , /* LTDC_B6 */ - , /* LTDC_VSYNC */ - , /* LTDC_HSYNC */ - ; /* LTDC_CLK */ - }; - }; - - ltdc_pins_d: ltdc-3 { - pins1 { - pinmux = ; /* LCD_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - pins2 { - pinmux = , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ltdc_sleep_pins_d: ltdc-sleep-3 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - }; - }; - - mco1_pins_a: mco1-0 { - pins { - pinmux = ; /* MCO1 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - mco1_sleep_pins_a: mco1-sleep-0 { - pins { - pinmux = ; /* MCO1 */ - }; - }; - - mco2_pins_a: mco2-0 { - pins { - pinmux = ; /* MCO2 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - mco2_sleep_pins_a: mco2-sleep-0 { - pins { - pinmux = ; /* MCO2 */ - }; - }; - - m_can1_pins_a: m-can1-0 { - pins1 { - pinmux = ; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_a: m_can1-sleep-0 { - pins { - pinmux = , /* CAN1_TX */ - ; /* CAN1_RX */ - }; - }; - - m_can1_pins_b: m-can1-1 { - pins1 { - pinmux = ; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_b: m_can1-sleep-1 { - pins { - pinmux = , /* CAN1_TX */ - ; /* CAN1_RX */ - }; - }; - - m_can1_pins_c: m-can1-2 { - pins1 { - pinmux = ; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_c: m_can1-sleep-2 { - pins { - pinmux = , /* CAN1_TX */ - ; /* CAN1_RX */ - }; - }; - - m_can2_pins_a: m-can2-0 { - pins1 { - pinmux = ; /* CAN2_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* CAN2_RX */ - bias-disable; - }; - }; - - m_can2_sleep_pins_a: m_can2-sleep-0 { - pins { - pinmux = , /* CAN2_TX */ - ; /* CAN2_RX */ - }; - }; - - pwm1_pins_a: pwm1-0 { - pins { - pinmux = , /* TIM1_CH1 */ - , /* TIM1_CH2 */ - ; /* TIM1_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_sleep_pins_a: pwm1-sleep-0 { - pins { - pinmux = , /* TIM1_CH1 */ - , /* TIM1_CH2 */ - ; /* TIM1_CH4 */ - }; - }; - - pwm1_pins_b: pwm1-1 { - pins { - pinmux = ; /* TIM1_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_sleep_pins_b: pwm1-sleep-1 { - pins { - pinmux = ; /* TIM1_CH1 */ - }; - }; - - pwm2_pins_a: pwm2-0 { - pins { - pinmux = ; /* TIM2_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm2_sleep_pins_a: pwm2-sleep-0 { - pins { - pinmux = ; /* TIM2_CH4 */ - }; - }; - - pwm3_pins_a: pwm3-0 { - pins { - pinmux = ; /* TIM3_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_a: pwm3-sleep-0 { - pins { - pinmux = ; /* TIM3_CH2 */ - }; - }; - - pwm3_pins_b: pwm3-1 { - pins { - pinmux = ; /* TIM3_CH2 */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_b: pwm3-sleep-1 { - pins { - pinmux = ; /* TIM3_CH2 */ - }; - }; - - pwm4_pins_a: pwm4-0 { - pins { - pinmux = , /* TIM4_CH3 */ - ; /* TIM4_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_a: pwm4-sleep-0 { - pins { - pinmux = , /* TIM4_CH3 */ - ; /* TIM4_CH4 */ - }; - }; - - pwm4_pins_b: pwm4-1 { - pins { - pinmux = ; /* TIM4_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_b: pwm4-sleep-1 { - pins { - pinmux = ; /* TIM4_CH2 */ - }; - }; - - pwm5_pins_a: pwm5-0 { - pins { - pinmux = ; /* TIM5_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_sleep_pins_a: pwm5-sleep-0 { - pins { - pinmux = ; /* TIM5_CH2 */ - }; - }; - - pwm5_pins_b: pwm5-1 { - pins { - pinmux = , /* TIM5_CH2 */ - , /* TIM5_CH3 */ - ; /* TIM5_CH4 */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_sleep_pins_b: pwm5-sleep-1 { - pins { - pinmux = , /* TIM5_CH2 */ - , /* TIM5_CH3 */ - ; /* TIM5_CH4 */ - }; - }; - - pwm8_pins_a: pwm8-0 { - pins { - pinmux = ; /* TIM8_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm8_sleep_pins_a: pwm8-sleep-0 { - pins { - pinmux = ; /* TIM8_CH4 */ - }; - }; - - pwm12_pins_a: pwm12-0 { - pins { - pinmux = ; /* TIM12_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm12_sleep_pins_a: pwm12-sleep-0 { - pins { - pinmux = ; /* TIM12_CH1 */ - }; - }; - - qspi_clk_pins_a: qspi-clk-0 { - pins { - pinmux = ; /* QSPI_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { - pins { - pinmux = ; /* QSPI_CLK */ - }; - }; - - qspi_bk1_pins_a: qspi-bk1-0 { - pins { - pinmux = , /* QSPI_BK1_IO0 */ - , /* QSPI_BK1_IO1 */ - , /* QSPI_BK1_IO2 */ - ; /* QSPI_BK1_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { - pins { - pinmux = , /* QSPI_BK1_IO0 */ - , /* QSPI_BK1_IO1 */ - , /* QSPI_BK1_IO2 */ - ; /* QSPI_BK1_IO3 */ - }; - }; - - qspi_bk2_pins_a: qspi-bk2-0 { - pins { - pinmux = , /* QSPI_BK2_IO0 */ - , /* QSPI_BK2_IO1 */ - , /* QSPI_BK2_IO2 */ - ; /* QSPI_BK2_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { - pins { - pinmux = , /* QSPI_BK2_IO0 */ - , /* QSPI_BK2_IO1 */ - , /* QSPI_BK2_IO2 */ - ; /* QSPI_BK2_IO3 */ - }; - }; - - qspi_cs1_pins_a: qspi-cs1-0 { - pins { - pinmux = ; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { - pins { - pinmux = ; /* QSPI_BK1_NCS */ - }; - }; - - qspi_cs2_pins_a: qspi-cs2-0 { - pins { - pinmux = ; /* QSPI_BK2_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { - pins { - pinmux = ; /* QSPI_BK2_NCS */ - }; - }; - - sai2a_pins_a: sai2a-0 { - pins { - pinmux = , /* SAI2_SCK_A */ - , /* SAI2_SD_A */ - , /* SAI2_FS_A */ - ; /* SAI2_MCLK_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_a: sai2a-sleep-0 { - pins { - pinmux = , /* SAI2_SCK_A */ - , /* SAI2_SD_A */ - , /* SAI2_FS_A */ - ; /* SAI2_MCLK_A */ - }; - }; - - sai2a_pins_b: sai2a-1 { - pins1 { - pinmux = , /* SAI2_SD_A */ - , /* SAI2_FS_A */ - ; /* SAI2_SCK_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_b: sai2a-sleep-1 { - pins { - pinmux = , /* SAI2_SD_A */ - , /* SAI2_FS_A */ - ; /* SAI2_SCK_A */ - }; - }; - - sai2a_pins_c: sai2a-2 { - pins { - pinmux = , /* SAI2_SCK_A */ - , /* SAI2_SD_A */ - ; /* SAI2_FS_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_c: sai2a-sleep-2 { - pins { - pinmux = , /* SAI2_SCK_A */ - , /* SAI2_SD_A */ - ; /* SAI2_FS_A */ - }; - }; - - sai2b_pins_a: sai2b-0 { - pins1 { - pinmux = , /* SAI2_SCK_B */ - , /* SAI2_FS_B */ - ; /* SAI2_MCLK_B */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_a: sai2b-sleep-0 { - pins { - pinmux = , /* SAI2_SD_B */ - , /* SAI2_SCK_B */ - , /* SAI2_FS_B */ - ; /* SAI2_MCLK_B */ - }; - }; - - sai2b_pins_b: sai2b-1 { - pins { - pinmux = ; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_b: sai2b-sleep-1 { - pins { - pinmux = ; /* SAI2_SD_B */ - }; - }; - - sai2b_pins_c: sai2b-2 { - pins1 { - pinmux = ; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_c: sai2b-sleep-2 { - pins { - pinmux = ; /* SAI2_SD_B */ - }; - }; - - sai2b_pins_d: sai2b-3 { - pins1 { - pinmux = , /* SAI2_SCK_B */ - , /* SAI2_FS_B */ - ; /* SAI2_MCLK_B */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_d: sai2b-sleep-3 { - pins1 { - pinmux = , /* SAI2_SCK_B */ - , /* SAI2_FS_B */ - , /* SAI2_MCLK_B */ - ; /* SAI2_SD_B */ - }; - }; - - sai4a_pins_a: sai4a-0 { - pins { - pinmux = ; /* SAI4_SD_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai4a_sleep_pins_a: sai4a-sleep-0 { - pins { - pinmux = ; /* SAI4_SD_A */ - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - ; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - ; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_b4_pins_b: sdmmc1-b4-1 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - ; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - sdmmc1_dir_pins_b: sdmmc1-dir-1 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - , /* SDMMC2_CK */ - ; /* SDMMC2_CMD */ - }; - }; - - sdmmc2_b4_pins_b: sdmmc2-b4-1 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc2_d47_pins_a: sdmmc2-d47-0 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_b: sdmmc2-d47-1 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_c: sdmmc2-d47-2 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_d: sdmmc2-d47-3 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_e: sdmmc2-d47-4 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc3_b4_pins_a: sdmmc3-b4-0 { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - ; /* SDMMC3_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - ; /* SDMMC3_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { - pins { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - , /* SDMMC3_CK */ - ; /* SDMMC3_CMD */ - }; - }; - - sdmmc3_b4_pins_b: sdmmc3-b4-1 { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - ; /* SDMMC3_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - ; /* SDMMC3_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { - pins { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - , /* SDMMC3_CK */ - ; /* SDMMC3_CMD */ - }; - }; - - spdifrx_pins_a: spdifrx-0 { - pins { - pinmux = ; /* SPDIF_IN1 */ - bias-disable; - }; - }; - - spdifrx_sleep_pins_a: spdifrx-sleep-0 { - pins { - pinmux = ; /* SPDIF_IN1 */ - }; - }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; - - spi2_pins_a: spi2-0 { - pins1 { - pinmux = , /* SPI2_SCK */ - ; /* SPI2_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI2_MISO */ - bias-disable; - }; - }; - - spi2_pins_b: spi2-1 { - pins1 { - pinmux = , /* SPI2_SCK */ - ; /* SPI2_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI2_MISO */ - bias-disable; - }; - }; - - spi4_pins_a: spi4-0 { - pins { - pinmux = , /* SPI4_SCK */ - ; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* SPI4_MISO */ - bias-disable; - }; - }; - - stusb1600_pins_a: stusb1600-0 { - pins { - pinmux = ; - bias-pull-up; - }; - }; - - uart4_pins_a: uart4-0 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_sleep_pins_a: uart4-sleep-0 { - pins { - pinmux = , /* UART4_TX */ - ; /* UART4_RX */ - }; - }; - - uart4_pins_b: uart4-1 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_pins_c: uart4-2 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_pins_d: uart4-3 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_idle_pins_d: uart4-idle-3 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_sleep_pins_d: uart4-sleep-3 { - pins { - pinmux = , /* UART4_TX */ - ; /* UART4_RX */ - }; - }; - - uart5_pins_a: uart5-0 { - pins1 { - pinmux = ; /* UART5_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART5_RX */ - bias-disable; - }; - }; - - uart7_pins_a: uart7-0 { - pins1 { - pinmux = ; /* UART7_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* UART7_RX */ - , /* UART7_CTS */ - ; /* UART7_RTS */ - bias-disable; - }; - }; - - uart7_pins_b: uart7-1 { - pins1 { - pinmux = ; /* UART7_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART7_RX */ - bias-disable; - }; - }; - - uart7_pins_c: uart7-2 { - pins1 { - pinmux = ; /* UART7_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART7_RX */ - bias-pull-up; - }; - }; - - uart7_idle_pins_c: uart7-idle-2 { - pins1 { - pinmux = ; /* UART7_TX */ - }; - pins2 { - pinmux = ; /* UART7_RX */ - bias-pull-up; - }; - }; - - uart7_sleep_pins_c: uart7-sleep-2 { - pins { - pinmux = , /* UART7_TX */ - ; /* UART7_RX */ - }; - }; - - uart8_pins_a: uart8-0 { - pins1 { - pinmux = ; /* UART8_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART8_RX */ - bias-disable; - }; - }; - - uart8_rtscts_pins_a: uart8rtscts-0 { - pins { - pinmux = , /* UART8_RTS */ - ; /* UART8_CTS */ - bias-disable; - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = ; /* USART1_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_CTS_NSS */ - bias-disable; - }; - }; - - usart1_idle_pins_a: usart1-idle-0 { - pins1 { - pinmux = , /* USART1_RTS */ - ; /* USART1_CTS_NSS */ - }; - }; - - usart1_sleep_pins_a: usart1-sleep-0 { - pins { - pinmux = , /* USART1_RTS */ - ; /* USART1_CTS_NSS */ - }; - }; - - usart2_pins_a: usart2-0 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = , /* USART2_TX */ - , /* USART2_RTS */ - , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_b: usart2-1 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_b: usart2-sleep-1 { - pins { - pinmux = , /* USART2_TX */ - , /* USART2_RTS */ - , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_c: usart2-2 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_idle_pins_c: usart2-idle-2 { - pins1 { - pinmux = , /* USART2_TX */ - ; /* USART2_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_sleep_pins_c: usart2-sleep-2 { - pins { - pinmux = , /* USART2_TX */ - , /* USART2_RTS */ - , /* USART2_RX */ - ; /* USART2_CTS_NSS */ - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = ; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART3_RX */ - bias-disable; - }; - }; - - usart3_idle_pins_a: usart3-idle-0 { - pins1 { - pinmux = ; /* USART3_TX */ - }; - pins2 { - pinmux = ; /* USART3_RX */ - bias-disable; - }; - }; - - usart3_sleep_pins_a: usart3-sleep-0 { - pins { - pinmux = , /* USART3_TX */ - ; /* USART3_RX */ - }; - }; - - usart3_pins_b: usart3-1 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART3_RX */ - ; /* USART3_CTS_NSS */ - bias-pull-up; - }; - }; - - usart3_idle_pins_b: usart3-idle-1 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = ; /* USART3_RX */ - bias-pull-up; - }; - }; - - usart3_sleep_pins_b: usart3-sleep-1 { - pins { - pinmux = , /* USART3_TX */ - , /* USART3_RTS */ - , /* USART3_CTS_NSS */ - ; /* USART3_RX */ - }; - }; - - usart3_pins_c: usart3-2 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART3_RX */ - ; /* USART3_CTS_NSS */ - bias-pull-up; - }; - }; - - usart3_idle_pins_c: usart3-idle-2 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = ; /* USART3_RX */ - bias-pull-up; - }; - }; - - usart3_sleep_pins_c: usart3-sleep-2 { - pins { - pinmux = , /* USART3_TX */ - , /* USART3_RTS */ - , /* USART3_CTS_NSS */ - ; /* USART3_RX */ - }; - }; - - usart3_pins_d: usart3-3 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART3_RX */ - ; /* USART3_CTS_NSS */ - bias-disable; - }; - }; - - usart3_idle_pins_d: usart3-idle-3 { - pins1 { - pinmux = , /* USART3_TX */ - , /* USART3_RTS */ - ; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART3_RX */ - bias-disable; - }; - }; - - usart3_sleep_pins_d: usart3-sleep-3 { - pins { - pinmux = , /* USART3_TX */ - , /* USART3_RTS */ - , /* USART3_CTS_NSS */ - ; /* USART3_RX */ - }; - }; - - usart3_pins_e: usart3-4 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* USART3_RX */ - ; /* USART3_CTS_NSS */ - bias-pull-up; - }; - }; - - usart3_idle_pins_e: usart3-idle-4 { - pins1 { - pinmux = , /* USART3_TX */ - ; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = ; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = ; /* USART3_RX */ - bias-pull-up; - }; - }; - - usart3_sleep_pins_e: usart3-sleep-4 { - pins { - pinmux = , /* USART3_TX */ - , /* USART3_RTS */ - , /* USART3_CTS_NSS */ - ; /* USART3_RX */ - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = ; /* OTG_ID */ - }; - }; - - usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { - pins { - pinmux = , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - }; - }; -}; - -&pinctrl_z { - i2c2_pins_b2: i2c2-0 { - pins { - pinmux = ; /* I2C2_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_sleep_pins_b2: i2c2-sleep-0 { - pins { - pinmux = ; /* I2C2_SCL */ - }; - }; - - i2c4_pins_a: i2c4-0 { - pins { - pinmux = , /* I2C4_SCL */ - ; /* I2C4_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c4_sleep_pins_a: i2c4-sleep-0 { - pins { - pinmux = , /* I2C4_SCL */ - ; /* I2C4_SDA */ - }; - }; - - i2c6_pins_a: i2c6-0 { - pins { - pinmux = , /* I2C6_SCL */ - ; /* I2C6_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c6_sleep_pins_a: i2c6-sleep-0 { - pins { - pinmux = , /* I2C6_SCL */ - ; /* I2C6_SDA */ - }; - }; - - spi1_pins_a: spi1-0 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; - - spi1_sleep_pins_a: spi1-sleep-0 { - pins { - pinmux = , /* SPI1_SCK */ - , /* SPI1_MISO */ - ; /* SPI1_MOSI */ - }; - }; - - usart1_pins_b: usart1-1 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_idle_pins_b: usart1-idle-1 { - pins1 { - pinmux = ; /* USART1_TX */ - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_sleep_pins_b: usart1-sleep-1 { - pins { - pinmux = , /* USART1_TX */ - ; /* USART1_RX */ - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi deleted file mode 100644 index 543f24c2f4f6..000000000000 --- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "linaro,scmi-optee"; - #address-cells = <1>; - #size-cells = <0>; - linaro,optee-channel-id = <0>; - shmem = <&scmi_shm>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - - scmi_voltd: protocol@17 { - reg = <0x17>; - - scmi_reguls: regulators { - #address-cells = <1>; - #size-cells = <0>; - - scmi_reg11: reg11@0 { - reg = <0>; - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - scmi_reg18: reg18@1 { - voltd-name = "reg18"; - reg = <1>; - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - scmi_usb33: usb33@2 { - reg = <2>; - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - }; - - soc { - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi-sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - }; -}; - -®11 { - status = "disabled"; -}; - -®18 { - status = "disabled"; -}; - -&usb33 { - status = "disabled"; -}; - -&usbotg_hs { - usb33d-supply = <&scmi_usb33>; -}; - -&usbphyc { - vdda1v1-supply = <&scmi_reg11>; - vdda1v8-supply = <&scmi_reg18>; -}; - -/delete-node/ &clk_hse; -/delete-node/ &clk_hsi; -/delete-node/ &clk_lse; -/delete-node/ &clk_lsi; -/delete-node/ &clk_csi; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi deleted file mode 100644 index 61508917521c..000000000000 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ /dev/null @@ -1,1846 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - clock-frequency = <650000000>; - device_type = "cpu"; - reg = <0>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - intc: interrupt-controller@a0021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xa0021000 0x1000>, - <0xa0022000 0x2000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&intc>; - }; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&dts>; - - trips { - cpu_alert1: cpu-alert1 { - temperature = <85000>; - hysteresis = <0>; - type = "passive"; - }; - - cpu-crit { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - booster: regulator-booster { - compatible = "st,stm32mp1-booster"; - st,syscfg = <&syscfg>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timer@40006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40006000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@40007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@40008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = ; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000b000 0x400>; - interrupts = ; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi3: spi@4000c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = ; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000c000 0x400>; - interrupts = ; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - #sound-dai-cells = <0>; - reg = <0x4000d000 0x400>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = ; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; - - usart2: serial@4000e000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000e000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x15>, - <&dmamux1 44 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x15>, - <&dmamux1 46 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x15>, - <&dmamux1 64 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x15>, - <&dmamux1 66 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c1: i2c@40012000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c2: i2c@40013000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c3: i2c@40014000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40014000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@40015000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40015000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - cec: cec@40016000 { - compatible = "st,stm32-cec"; - reg = <0x40016000 0x400>; - interrupts = ; - clocks = <&rcc CEC_K>, <&rcc CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - dac: dac@40017000 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40017000 0x400>; - clocks = <&rcc DAC12>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x15>, - <&dmamux1 80 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x15>, - <&dmamux1 82 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = ; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x44004000 0x400>; - interrupts = ; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@44005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44005000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers15: timer@44006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44006000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@44007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@44008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - - spi5: spi@44009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44009000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400a000 0x400>; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - interrupts = ; - resets = <&rcc SAI1_R>; - status = "disabled"; - - sai1a: audio-controller@4400a004 { - #sound-dai-cells = <0>; - - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; - - sai1b: audio-controller@4400a024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; - }; - }; - - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400b000 0x400>; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - interrupts = ; - resets = <&rcc SAI2_R>; - status = "disabled"; - - sai2a: audio-controller@4400b004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; - - sai2b: audio-controller@4400b024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; - }; - }; - - sai3: sai@4400c000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400c000 0x400>; - reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; - interrupts = ; - resets = <&rcc SAI3_R>; - status = "disabled"; - - sai3a: audio-controller@4400c004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 113 0x400 0x01>; - status = "disabled"; - }; - - sai3b: audio-controller@4400c024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 114 0x400 0x01>; - status = "disabled"; - }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = ; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <1>; - interrupts = ; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <2>; - interrupts = ; - dmas = <&dmamux1 103 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm3: filter@3 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <3>; - interrupts = ; - dmas = <&dmamux1 104 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm4: filter@4 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <4>; - interrupts = ; - dmas = <&dmamux1 91 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm5: filter@5 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <5>; - interrupts = ; - dmas = <&dmamux1 92 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - #dma-cells = <3>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - dma-channels = <16>; - clocks = <&rcc DMAMUX>; - resets = <&rcc DMAMUX_R>; - }; - - adc: adc@48003000 { - compatible = "st,stm32mp1-adc-core"; - reg = <0x48003000 0x400>; - interrupts = , - ; - clocks = <&rcc ADC12>, <&rcc ADC12_K>; - clock-names = "bus", "adc"; - interrupt-controller; - st,syscfg = <&syscfg>; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; - dma-names = "rx"; - nvmem-cells = <&vrefint>; - nvmem-cell-names = "vrefint"; - status = "disabled"; - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - }; - }; - - sdmmc3: mmc@48004000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x48004000 0x400>; - interrupts = ; - clocks = <&rcc SDMMC3_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC3_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>, <&usbphyc>; - clock-names = "otg", "utmi"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; - - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = - <&exti 61 1>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "rx", "tx"; - clocks = <&rcc IPCC>; - wakeup-source; - status = "disabled"; - }; - - dcmi: dcmi@4c006000 { - compatible = "st,stm32-dcmi"; - reg = <0x4c006000 0x400>; - interrupts = ; - resets = <&rcc CAMITF_R>; - clocks = <&rcc DCMI>; - clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x01>; - dma-names = "tx"; - status = "disabled"; - }; - - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; - - reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - pwr_mcu: pwr_mcu@50001014 { - compatible = "st,stm32mp151-pwr-mcu", "syscon"; - reg = <0x50001014 0x4>; - }; - - exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp1-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; - - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; - - sai4: sai@50027000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50027000 0x400>; - reg = <0x50027000 0x4>, <0x500273f0 0x10>; - interrupts = ; - resets = <&rcc SAI4_R>; - status = "disabled"; - - sai4a: audio-controller@50027004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 99 0x400 0x01>; - status = "disabled"; - }; - - sai4b: audio-controller@50027024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 100 0x400 0x01>; - status = "disabled"; - }; - }; - - dts: thermal@50028000 { - compatible = "st,stm32-thermal"; - reg = <0x50028000 0x100>; - interrupts = ; - clocks = <&rcc TMPSENS>; - clock-names = "pclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - hash1: hash@54002000 { - compatible = "st,stm32f756-hash"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; - dma-names = "in"; - dma-maxburst = <2>; - status = "disabled"; - }; - - rng1: rng@54003000 { - compatible = "st,stm32-rng"; - reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - - mdma1: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = ; - clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; - - fmc: memory-controller@58002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - - nand-controller@4,0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - interrupts = ; - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = ; - dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, - <&mdma1 22 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58005000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58007000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - crc1: crc@58009000 { - compatible = "st,stm32f7-crc"; - reg = <0x58009000 0x400>; - clocks = <&rcc CRC1>; - status = "disabled"; - }; - - ethernet0: ethernet@5800a000 { - compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "eth-ck", - "ptp_ref", - "ethstp"; - clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHCK_K>, - <&rcc ETHPTP_K>, - <&rcc ETHSTP>; - st,syscon = <&syscfg 0x4>; - snps,mixed-burst; - snps,pbl = <2>; - snps,en-tx-lpi-clockgating; - snps,axi-config = <&stmmac_axi_config_0>; - snps,tso; - status = "disabled"; - - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - }; - - usbh_ohci: usb@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - status = "disabled"; - }; - - usbh_ehci: usb@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - ltdc: display-controller@5a001000 { - compatible = "st,stm32-ltdc"; - reg = <0x5a001000 0x400>; - interrupts = , - ; - clocks = <&rcc LTDC_PX>; - clock-names = "lcd"; - resets = <&rcc LTDC_R>; - status = "disabled"; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - - usart1: serial@5c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x5c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - wakeup-source; - status = "disabled"; - }; - - spi6: spi@5c001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x5c001000 0x400>; - interrupts = ; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@5c002000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c002000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - part_number_otp: part-number-otp@4 { - reg = <0x4 0x1>; - }; - vrefint: vrefin-cal@52 { - reg = <0x52 0x2>; - }; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; - }; - - i2c6: i2c@5c009000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c009000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x20>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - tamp: tamp@5c00a000 { - compatible = "st,stm32-tamp", "syscon", "simple-mfd"; - reg = <0x5c00a000 0x400>; - }; - - /* - * Break node order to solve dependency probe issue between - * pinctrl and exti. - */ - pinctrl: pinctrl@50002000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-pinctrl"; - ranges = <0 0x50002000 0xa400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioa: gpio@50002000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA>; - st,bank-name = "GPIOA"; - status = "disabled"; - }; - - gpiob: gpio@50003000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOB>; - st,bank-name = "GPIOB"; - status = "disabled"; - }; - - gpioc: gpio@50004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOC>; - st,bank-name = "GPIOC"; - status = "disabled"; - }; - - gpiod: gpio@50005000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x400>; - clocks = <&rcc GPIOD>; - st,bank-name = "GPIOD"; - status = "disabled"; - }; - - gpioe: gpio@50006000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x400>; - clocks = <&rcc GPIOE>; - st,bank-name = "GPIOE"; - status = "disabled"; - }; - - gpiof: gpio@50007000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x400>; - clocks = <&rcc GPIOF>; - st,bank-name = "GPIOF"; - status = "disabled"; - }; - - gpiog: gpio@50008000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x400>; - clocks = <&rcc GPIOG>; - st,bank-name = "GPIOG"; - status = "disabled"; - }; - - gpioh: gpio@50009000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x400>; - clocks = <&rcc GPIOH>; - st,bank-name = "GPIOH"; - status = "disabled"; - }; - - gpioi: gpio@5000a000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x400>; - clocks = <&rcc GPIOI>; - st,bank-name = "GPIOI"; - status = "disabled"; - }; - - gpioj: gpio@5000b000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x400>; - clocks = <&rcc GPIOJ>; - st,bank-name = "GPIOJ"; - status = "disabled"; - }; - - gpiok: gpio@5000c000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xa000 0x400>; - clocks = <&rcc GPIOK>; - st,bank-name = "GPIOK"; - status = "disabled"; - }; - }; - - pinctrl_z: pinctrl@54004000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-z-pinctrl"; - ranges = <0 0x54004000 0x400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioz: gpio@54004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x400>; - clocks = <&rcc GPIOZ>; - st,bank-name = "GPIOZ"; - st,bank-ioport = <11>; - status = "disabled"; - }; - }; - }; - - mlahb: ahb { - compatible = "st,mlahb", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - dma-ranges = <0x00000000 0x38000000 0x10000>, - <0x10000000 0x10000000 0x60000>, - <0x30000000 0x30000000 0x60000>; - - m4_rproc: m4@10000000 { - compatible = "st,stm32mp1-m4"; - reg = <0x10000000 0x40000>, - <0x30000000 0x40000>, - <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - reset-names = "mcu_rst"; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; - st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; - st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts deleted file mode 100644 index e0f828ecc2fa..000000000000 --- a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut - */ - -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15xx-dhcor-som.dtsi" -#include "stm32mp15xx-dhcor-testbench.dtsi" - -/ { - model = "DH electronics STM32MP151A DHCOR Testbench"; - compatible = "dh,stm32mp151a-dhcor-testbench", - "dh,stm32mp151a-dhcor-som", - "st,stm32mp151"; -}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts deleted file mode 100644 index 75874eafde11..000000000000 --- a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) Protonic Holland - * Author: David Jander - */ -/dts-v1/; - -#include "stm32mp151a-prtt1l.dtsi" - -/ { - model = "Protonic PRTT1A"; - compatible = "prt,prtt1a", "st,stm32mp151"; -}; - -ðernet0 { - phy-handle = <&phy0>; -}; - -&mdio0 { - /* TI DP83TD510E */ - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id2000.0181"; - reg = <0>; - interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <35>; - }; -}; - -&pwm5_pins_a { - pins { - pinmux = ; /* TIM5_CH1 */ - }; -}; - -&pwm5_sleep_pins_a { - pins { - pinmux = ; /* TIM5_CH1 */ - }; -}; - -&timers5 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm5_pins_a>; - pinctrl-1 = <&pwm5_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts deleted file mode 100644 index 7ecf31263abc..000000000000 --- a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) Protonic Holland - * Author: David Jander - */ -/dts-v1/; - -#include "stm32mp151a-prtt1l.dtsi" - -/ { - model = "Protonic PRTT1C"; - compatible = "prt,prtt1c", "st,stm32mp151"; - - clock_ksz9031: clock-ksz9031 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - clock_sja1105: clock-sja1105 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&gpioc 1 GPIO_ACTIVE_HIGH - &gpioa 2 GPIO_ACTIVE_HIGH>; - - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; - }; -}; - -ðernet0 { - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&gpioa { - gpio-line-names = - "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", - "", "", "", "", "", "", "", "SPI1_nSS"; -}; - -&gpiod { - gpio-line-names = - "", "", "", "", "", "", "", "", - "WFM_RESET", "", "", "", "", "", "", ""; -}; - -&gpioe { - gpio-line-names = - "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", - "", "", "", "", "WFM_nIRQ", "", "", ""; -}; - -&gpiog { - gpio-line-names = - "", "", "", "", "", "", "", "PHY3_nINT", - "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", - "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; -}; - -&mdio0 { - /* All this DP83TD510E PHYs can't be probed before switch@0 is - * probed so we need to use compatible with PHYid - */ - /* TI DP83TD510E */ - t1l0_phy: ethernet-phy@6 { - compatible = "ethernet-phy-id2000.0181"; - reg = <6>; - interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <35>; - }; - - /* TI DP83TD510E */ - t1l1_phy: ethernet-phy@7 { - compatible = "ethernet-phy-id2000.0181"; - reg = <7>; - interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <35>; - }; - - /* TI DP83TD510E */ - t1l2_phy: ethernet-phy@10 { - compatible = "ethernet-phy-id2000.0181"; - reg = <10>; - interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <35>; - }; - - /* Micrel KSZ9031 */ - rj45_phy: ethernet-phy@2 { - reg = <2>; - interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <1000>; - - clocks = <&clock_ksz9031>; - }; -}; - -&qspi { - status = "disabled"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - no-1-8-v; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_3v3>; - status = "okay"; -}; - -&sdmmc2_b4_od_pins_a { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - }; -}; - -&sdmmc2_b4_pins_a { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - }; -}; - -&sdmmc2_b4_sleep_pins_a { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - , /* SDMMC2_CK */ - ; /* SDMMC2_CMD */ - }; -}; - -&sdmmc2_d47_pins_a { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; -}; - -&sdmmc2_d47_sleep_pins_a { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_b>; - pinctrl-1 = <&sdmmc3_b4_od_pins_b>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; - non-removable; - no-1-8-v; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - mmc@1 { - compatible = "prt,prtt1c-wfm200", "silabs,wf200"; - reg = <1>; - }; -}; - -&sdmmc3_b4_od_pins_b { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - ; /* SDMMC3_D3 */ - }; -}; - -&sdmmc3_b4_pins_b { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - ; /* SDMMC3_CMD */ - }; -}; - -&sdmmc3_b4_sleep_pins_b { - pins { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - , /* SDMMC3_CK */ - ; /* SDMMC3_CMD */ - }; -}; - -&spi1 { - pinctrl-0 = <&spi1_pins_b>; - pinctrl-names = "default"; - cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - switch@0 { - compatible = "nxp,sja1105q"; - reg = <0>; - spi-max-frequency = <4000000>; - spi-rx-delay-us = <1>; - spi-tx-delay-us = <1>; - spi-cpha; - - reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; - - clocks = <&clock_sja1105>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "t1l0"; - phy-mode = "rmii"; - phy-handle = <&t1l0_phy>; - }; - - port@1 { - reg = <1>; - label = "t1l1"; - phy-mode = "rmii"; - phy-handle = <&t1l1_phy>; - }; - - port@2 { - reg = <2>; - label = "t1l2"; - phy-mode = "rmii"; - phy-handle = <&t1l2_phy>; - }; - - port@3 { - reg = <3>; - label = "rj45"; - phy-handle = <&rj45_phy>; - phy-mode = "rgmii-id"; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <ðernet0>; - phy-mode = "rmii"; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi deleted file mode 100644 index dd23de85100c..000000000000 --- a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) Protonic Holland - * Author: David Jander - */ -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxad-pinctrl.dtsi" -#include -#include -#include - -/ { - aliases { - ethernet0 = ðernet0; - mdio-gpio0 = &mdio0; - serial0 = &uart4; - }; - - led-controller-0 { - compatible = "gpio-leds"; - - led-0 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - }; - - led-1 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - - /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce - * stmmac MDC clock without reducing system bus rate, we need to use - * gpio based MDIO bus. - */ - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&gpioc 1 GPIO_ACTIVE_HIGH - &gpioa 2 GPIO_ACTIVE_HIGH>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dts { - status = "okay"; -}; - -ðernet0 { - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - status = "okay"; -}; - -ðernet0_rmii_pins_a { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - ; /* ETH1_RMII_TX_EN */ - }; - pins2 { - pinmux = , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK input */ - ; /* ETH1_RMII_CRS_DV */ - }; -}; - -ðernet0_rmii_sleep_pins_a { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK */ - ; /* ETH1_RMII_CRS_DV */ - }; -}; - -&iwdg2 { - status = "okay"; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <104000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&qspi_bk1_pins_a { - pins1 { - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_3v3>; - status = "okay"; -}; - -&sdmmc1_b4_od_pins_a { - pins1 { - bias-pull-up; - }; - pins2 { - bias-pull-up; - }; -}; - -&sdmmc1_b4_pins_a { - pins1 { - bias-pull-up; - }; - pins2 { - bias-pull-up; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart4_idle_pins_a { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-pull-up; - }; -}; - -&uart4_pins_a { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-pull-up; - }; -}; - -&uart4_sleep_pins_a { - pins { - pinmux = , /* UART4_TX */ - ; /* UART4_RX */ - }; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <®_3v3>; -}; - -&usbphyc_port1 { - phy-supply = <®_3v3>; -}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts deleted file mode 100644 index ad25929e64e6..000000000000 --- a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) Protonic Holland - * Author: David Jander - */ -/dts-v1/; - -#include "stm32mp151a-prtt1l.dtsi" - -/ { - model = "Protonic PRTT1S"; - compatible = "prt,prtt1s", "st,stm32mp151"; -}; - -ðernet0 { - phy-handle = <&phy0>; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - clock-frequency = <100000>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - humidity-sensor@40 { - compatible = "ti,hdc1080"; - reg = <0x40>; - }; - - co2-sensor@62 { - compatible = "sensirion,scd41"; - reg = <0x62>; - }; -}; - -&i2c1_pins_a { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; -}; - -&i2c1_sleep_pins_a { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; -}; - -&mdio0 { - /* TI DP83TD510E */ - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id2000.0181"; - reg = <0>; - interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <35>; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi deleted file mode 100644 index 486084e0b80b..000000000000 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32mp151.dtsi" - -/ { - cpus { - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - clock-frequency = <650000000>; - device_type = "cpu"; - reg = <1>; - }; - }; - - arm-pmu { - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - timer { - interrupts = , - , - , - ; - }; - - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts deleted file mode 100644 index b4e504f026ce..000000000000 --- a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut - * - * DHCOM STM32MP1 variant: - * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2 - * DHCOM PCB number: 587-200 or newer - * DRC02 PCB number: 568-100 or newer - */ -/dts-v1/; - -#include "stm32mp153.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcom-som.dtsi" -#include "stm32mp15xx-dhcom-drc02.dtsi" - -/ { - model = "DH electronics STM32MP153C DHCOM DRC02"; - compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som", - "st,stm32mp153"; -}; - -&cryp1 { - status = "okay"; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts deleted file mode 100644 index c8b9818499ea..000000000000 --- a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut - * - * DHCOR STM32MP1 variant: - * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG - * DHCOR PCB number: 586-100 or newer - * DRC Compact PCB number: 627-100 or newer - */ - -/dts-v1/; - -#include "stm32mp153.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcor-som.dtsi" -#include "stm32mp15xx-dhcor-drc-compact.dtsi" - -/ { - model = "DH electronics STM32MP153C DHCOR DRC Compact"; - compatible = "dh,stm32mp153c-dhcor-drc-compact", - "dh,stm32mp153c-dhcor-som", - "st,stm32mp153"; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_c>; - pinctrl-1 = <&m_can1_sleep_pins_c>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi deleted file mode 100644 index 5e733cd16ff9..000000000000 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32mp153.dtsi" - -/ { - soc { - gpu: gpu@59000000 { - compatible = "vivante,gc"; - reg = <0x59000000 0x800>; - interrupts = ; - clocks = <&rcc GPU>, <&rcc GPU_K>; - clock-names = "bus" ,"core"; - resets = <&rcc GPU_R>; - }; - - dsi: dsi@5a000000 { - compatible = "st,stm32-dsi"; - reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; - clock-names = "pclk", "ref", "px_clk"; - resets = <&rcc DSI_R>; - reset-names = "apb"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts deleted file mode 100644 index 8a6eaca994d1..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - * Copyright (C) 2020 Marek Vasut - */ - -/dts-v1/; - -/* This DT is here only for backward compatibility */ -#include "stm32mp157a-dhcor-avenger96.dts" diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts deleted file mode 100644 index 275167f26fd9..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - * Copyright (C) 2020 Marek Vasut - * - * DHCOR STM32MP1 variant: - * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG - * DHCOR PCB number: 586-100 or newer - * Avenger96 PCB number: 588-200 or newer - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xx-dhcor-som.dtsi" -#include "stm32mp15xx-dhcor-avenger96.dtsi" - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", - "st,stm32mp157"; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_b>; - pinctrl-1 = <&m_can1_sleep_pins_b>; - status = "disabled"; -}; - -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts deleted file mode 100644 index afcd6285890c..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157a-dk1.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; - compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; - - reserved-memory { - optee@de000000 { - reg = <0xde000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts deleted file mode 100644 index 0da3667ab1e0..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp15xx-dkx.dtsi" - -/ { - model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; - compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts deleted file mode 100644 index 4279b26547df..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-icore-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include - -/ { - model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; - compatible = "engicam,icore-stm32mp1-ctouch2-of10", - "engicam,icore-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; - default-on; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - panel { - compatible = "ampire,am-1280800n3tzqw-t00h"; - backlight = <&backlight>; - power-supply = <&v3v3>; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; -}; - -&dsi { - status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&i2c6 { - i2c-scl-falling-time-ns = <20>; - i2c-scl-rising-time-ns = <185>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_pins_a>; - pinctrl-1 = <&i2c6_sleep_pins_a>; - status = "okay"; - - bridge@2c { - compatible = "ti,sn65dsi84"; - reg = <0x2c>; - enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&dsi_out>; - data-lanes = <1 2>; - }; - }; - - port@2 { - reg = <2>; - bridge_out: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; - }; -}; - -<dc { - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts deleted file mode 100644 index 60ce4425a7fd..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-icore-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include - -/ { - model = "Engicam i.Core STM32MP1 C.TOUCH 2.0"; - compatible = "engicam,icore-stm32mp1-ctouch2", - "engicam,icore-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts deleted file mode 100644 index efba54289820..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-icore-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include - -/ { - model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit"; - compatible = "engicam,icore-stm32mp1-edimm2.2", - "engicam,icore-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; - default-on; - }; - - panel { - compatible = "yes-optoelectronics,ytc700tlag-05-201c"; - backlight = <&backlight>; - power-supply = <&v3v3>; - - port { - panel_out_bridge: endpoint { - remote-endpoint = <&bridge_out_panel>; - }; - }; - }; -}; - -&dsi { - status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in_ltdc: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out_bridge: endpoint { - remote-endpoint = <&bridge_in_dsi>; - }; - }; - }; -}; - -&i2c6 { - i2c-scl-falling-time-ns = <20>; - i2c-scl-rising-time-ns = <185>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_pins_a>; - pinctrl-1 = <&i2c6_sleep_pins_a>; - status = "okay"; - - bridge@2c { - compatible = "ti,sn65dsi84"; - reg = <0x2c>; - enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in_dsi: endpoint { - remote-endpoint = <&dsi_out_bridge>; - data-lanes = <1 2>; - }; - }; - - port@2 { - reg = <2>; - bridge_out_panel: endpoint { - remote-endpoint = <&panel_out_bridge>; - }; - }; - }; - }; -}; - -<dc { - status = "okay"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in_ltdc>; - }; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi deleted file mode 100644 index 9de893101b40..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/ { - compatible = "engicam,icore-stm32mp1", "st,stm32mp157"; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - vddcore: regulator-vddcore { - compatible = "regulator-fixed"; - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd: regulator-vdd { - compatible = "regulator-fixed"; - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_usb: regulator-vdd-usb { - compatible = "regulator-fixed"; - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ddr: regulator-vdd-ddr { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vtt_ddr: regulator-vtt-ddr { - compatible = "regulator-fixed"; - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <675000>; - regulator-always-on; - vin-supply = <&vdd>; - }; - - vref_ddr: regulator-vref-ddr { - compatible = "regulator-fixed"; - regulator-name = "vref_ddr"; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <675000>; - regulator-always-on; - vin-supply = <&vdd>; - }; - - vdd_sd: regulator-vdd-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v3v3: regulator-v3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2v8: regulator-v2v8 { - compatible = "regulator-fixed"; - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&v3v3>; - }; - - v1v8: regulator-v1v8 { - compatible = "regulator-fixed"; - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&v3v3>; - }; -}; - -&dts { - status = "okay"; -}; - -&i2c2 { - i2c-scl-falling-time-ns = <20>; - i2c-scl-rising-time-ns = <185>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_sleep_pins_a>; - status = "okay"; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2{ - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc{ - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&rng1 { - status = "okay"; -}; - -&rtc{ - status = "okay"; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts deleted file mode 100644 index 6a5a4af25bd9..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-iot-box.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Manivannan Sadhasivam - */ - -/dts-v1/; -#include "stm32mp157a-stinger96.dtsi" - -/ { - model = "Shiratech STM32MP157A IoT Box"; - compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; - - wlan_pwr: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&i2c2 { - ccs811@5b { - compatible = "ams,ccs811"; - reg = <0x5b>; - wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; - }; -}; - -/* WiFi */ -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; - broken-cd; - non-removable; - st,neg-edge; - bus-width = <1>; - vmmc-supply = <&wlan_pwr>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* Bluetooth */ -&uart4 { - /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ - /delete-property/st,hw-flow-ctrl; - cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - bluetooth { - shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; - compatible = "brcm,bcm43438-bt"; - max-speed = <115200>; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts deleted file mode 100644 index 5116a7785201..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-microgea-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include - -/ { - model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame"; - compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", - "engicam,microgea-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - serial1 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; - default-on; - }; - - lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - power-supply = <&panel_pwr>; - }; - - panel_pwr: regulator-panel-pwr { - compatible = "regulator-fixed"; - regulator-name = "panel_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - panel { - compatible = "auo,b101aw03"; - backlight = <&backlight>; - enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; - power-supply = <&lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - }; -}; - -&i2c2 { - i2c-scl-falling-time-ns = <20>; - i2c-scl-rising-time-ns = <185>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_sleep_pins_a>; - status = "okay"; -}; - -<dc { - pinctrl-names = "default"; - pinctrl-0 = <<dc_pins>; - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pinctrl { - ltdc_pins: ltdc-0 { - pins { - pinmux = , /* LTDC_B2 */ - , /* LTDC_R6 */ - , /* LTDC_R5 */ - , /* LTDC_B3 */ - , /* LTDC_B0 */ - , /* LTDC_G0 */ - , /* LTDC_G1 */ - , /* LTDC_DE */ - , /* LTDC_R7 */ - , /* LTDC_CLK */ - , /* LTDC_B1 */ - , /* LTDC_R0 */ - , /* LTDC_R1 */ - , /* LTDC_R2 */ - , /* LTDC_R3 */ - , /* LTDC_R4 */ - , /* LTDC_G2 */ - , /* LTDC_G3 */ - , /* LTDC_G4 */ - , /* LTDC_G5 */ - , /* LTDC_G6 */ - , /* LTDC_G7 */ - , /* LTDC_B4 */ - , /* LTDC_B5 */ - , /* LTDC_B6 */ - , /* LTDC_B7 */ - , /* LTDC_VSYNC */ - ; /* LTDC_HSYNC */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&vdd>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* J31: RS323 */ -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts deleted file mode 100644 index d949559be020..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-microgea-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include - -/ { - model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board"; - compatible = "engicam,microgea-stm32mp1-microdev2.0", - "engicam,microgea-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - serial1 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&vdd>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* J31: RS323 */ -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi deleted file mode 100644 index fb4600a59869..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/ { - compatible = "engicam,microgea-stm32mp1", "st,stm32mp157"; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x10000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - vin: regulator-vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddcore: regulator-vddcore { - compatible = "regulator-fixed"; - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - vin-supply = <&vin>; - }; - - vdd: regulator-vdd { - compatible = "regulator-fixed"; - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vin>; - }; - - vddq_ddr: regulator-vddq-ddr { - compatible = "regulator-fixed"; - regulator-name = "vddq_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vin>; - }; -}; - -&dts { - status = "okay"; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; - - nand-controller@4,0 { - status = "okay"; - - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2{ - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc{ - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&rng1 { - status = "okay"; -}; - -&rtc{ - status = "okay"; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/stm32mp157a-stinger96.dts deleted file mode 100644 index 249a53877512..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Manivannan Sadhasivam - */ - -/dts-v1/; -#include "stm32mp157a-stinger96.dtsi" - -/ { - model = "Shiratech STM32MP157A Stinger96 board"; - compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; -}; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi deleted file mode 100644 index 5f85598cc7c6..000000000000 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include - -/ { - aliases { - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - serial2 = &usart2; - spi0 = &spi4; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x10000000>; - }; - - led { - compatible = "gpio-leds"; - - led1 { - label = "green:user1"; - gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user4"; - gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; -}; - -/* Only headless mode is supported */ -&gpu { - status = "disabled"; -}; - -/* LS-I2C0 */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <1000>; - i2c-scl-falling-time-ns = <300>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - }; - - v2v9: ldo2 { - regulator-name = "v2v9"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - broken-cd; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -/* LS-SPI0 */ -&spi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins_a>; - cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -/* BG96 */ -&usart2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart2_pins_b>; - pinctrl-1 = <&usart2_sleep_pins_b>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* LS-UART0 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_c>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* Debug console */ -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts deleted file mode 100644 index 6dd8216c235e..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2019-2020 Marek Vasut - * - * DHCOM STM32MP1 variant: - * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 - * DHCOM PCB number: 587-200 or newer - * PDK2 PCB number: 516-400 or newer - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcom-som.dtsi" -#include "stm32mp15xx-dhcom-pdk2.dtsi" - -/ { - model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; - compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", - "st,stm32mp157"; -}; - -&cryp1 { - status = "okay"; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts deleted file mode 100644 index 7067a860aaff..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut - * - * DHCOM STM32MP1 variant: - * DHCM-STM32MP157C-C065-R102-F0819-SPI-E-CAN2-SD-RTC-T-DSI-I-01D2 - * DHCOM PCB number: 587-200 or newer - * PicoITX PCB number: 487-600 or newer - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcom-som.dtsi" -#include "stm32mp15xx-dhcom-picoitx.dtsi" - -/ { - model = "DH electronics STM32MP157C DHCOM PicoITX"; - compatible = "dh,stm32mp157c-dhcom-picoitx", "dh,stm32mp157c-dhcom-som", - "st,stm32mp157"; -}; - -&cryp1 { - status = "okay"; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts deleted file mode 100644 index 39358d902000..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157c-dk2.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; - compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; - - reserved-memory { - optee@de000000 { - reg = <0xde000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cryp1 { - clocks = <&scmi_clk CK_SCMI_CRYP1>; - resets = <&scmi_reset RST_SCMI_CRYP1>; -}; - -&dsi { - phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts deleted file mode 100644 index 4bef2300ed7c..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp15xx-dkx.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; - compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial3 = &usart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cryp1 { - status = "okay"; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; - reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; - power-supply = <&v3v3>; - status = "okay"; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&i2c1 { - touchscreen@38 { - compatible = "focaltech,ft6236"; - reg = <0x38>; - interrupts = <2 2>; - interrupt-parent = <&gpiof>; - interrupt-controller; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - status = "okay"; - }; -}; - -<dc { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep1_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&usart2 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart2_pins_c>; - pinctrl-1 = <&usart2_sleep_pins_c>; - pinctrl-2 = <&usart2_idle_pins_c>; - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts deleted file mode 100644 index 07ea765a4553..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157c-ed1.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; - compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; - - reserved-memory { - optee@fe000000 { - reg = <0xfe000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cryp1 { - clocks = <&scmi_clk CK_SCMI_CRYP1>; - resets = <&scmi_reset RST_SCMI_CRYP1>; -}; - -&dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts deleted file mode 100644 index 66ed5f9921ba..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32MP157C eval daughter"; - compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - vin: vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&adc { - /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ - pinctrl-0 = <&adc1_in6_pins_a>; - pinctrl-names = "default"; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "disabled"; - adc1: adc@0 { - status = "okay"; - channel@0 { - reg = <0>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-ns = <400>; - }; - channel@1 { - reg = <1>; - st,min-sample-time-ns = <400>; - }; - channel@6 { - reg = <6>; - st,min-sample-time-ns = <400>; - }; - }; -}; - -&crc1 { - status = "okay"; -}; - -&cryp1 { - status = "okay"; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "disabled"; - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -&hash1 { - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <&vin>; - buck2-supply = <&vin>; - buck3-supply = <&vin>; - buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <&vin>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - vref_ddr-supply = <&vin>; - boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names = "vq0", "vq1", "shutdown", "detach"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&timers6 { - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - timer@5 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbotg_hs { - vbus-supply = <&vbus_otg>; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts deleted file mode 100644 index 33b3f11d24bb..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (c) 2021 emtrion GmbH -// Author: Reinhold Müller . -// - -/dts-v1/; - -#include "stm32mp157c-emstamp-argon.dtsi" - -/ { - model = "emtrion STM32MP157C emSBC-Argon Developer Board"; - compatible = "emtrion,stm32mp157c-emsbc-argon", "emtrion,stm32mp157c-emstamp-argon", - "st,stm32mp157"; - - led: gpio_leds { - compatible = "gpio-leds"; - led-2 { - label = "red"; - gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "off"; - }; - led-3 { - label = "green"; - gpios = <&gpioe 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "off"; - }; - }; -}; - -&dac { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi deleted file mode 100644 index 94e38141af67..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ /dev/null @@ -1,543 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (c) 2021 emtrion GmbH -// Author: Reinhold Müller . -// - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include - -/ { - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart2; - serial2 = &usart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x2000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x2000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10044000 { - compatible = "shared-dma-pool"; - reg = <0x10044000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - led: gpio_leds { - compatible = "gpio-leds"; - led-0 { - label = "panic"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - led-1 { - label = "heartbeat"; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - }; -}; - -&adc { - vdd-supply = <&vdd>; - vdda-supply = <&vdd>; - vref-supply = <&vrefbuf>; - status = "okay"; - - adc1: adc@0 { - pinctrl-names = "default"; - pinctrl-0 = <&adc1_in6_pins_a>; - status = "disabled"; - channel@6 { - reg = <6>; - st,min-sample-time-ns = <5000>; - }; - }; - - adc2: adc@100 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - channel@12 { - reg = <12>; - label = "sense_temp"; - st,min-sample-time-ns = <9000>; - }; - channel@15 { - reg = <15>; - label = "vbat"; - st,min-sample-time-ns = <9000>; - }; - channel@16 { - reg = <16>; - label = "dac_out1"; - st,min-sample-time-ns = <9000>; - }; - channel@17 { - reg = <17>; - label = "dac_out1"; - st,min-sample-time-ns = <9000>; - }; - }; -}; - -&crc1 { - status = "okay"; -}; - -&cryp1 { - status = "okay"; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "disabled"; - - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -ðernet0 { - status = "okay"; - snps,reset-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 30000 50000>; - pinctrl-0 = <ðernet0_rmii_pins_b>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_b>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth-ref-clk-sel; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&hash1 { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "disabled"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - regulator-always-on; - }; - - vdda: ldo6 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - interrupts = ; - regulator-boot-on; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - regulator-active-discharge; - }; - - vbus_usbh: pwr_sw2 { - regulator-name = "usbh_vbus"; - interrupts = ; - regulator-always-on; - regulator-boot-on; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - interrupt-names = "wdg"; - recovery; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <133000000>; - spi-rx-bus-width = <1>; - spi-tx-bus-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc2 { - arm,primecell-periphid = <0x10153180>; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; - non-removable; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - cs-gpios = <&gpioz 3 0>; - status = "disabled"; -}; - -&timers1 { - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - pwm { - pinctrl-0 = <&pwm1_pins_b>; - pinctrl-1 = <&pwm1_sleep_pins_b>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@0 { - status = "okay"; - }; -}; - -&timers4 { - /delete-property/dmas; - /delete-property/dma-names; - pwm { - pinctrl-0 = <&pwm4_pins_b>; - pinctrl-1 = <&pwm4_sleep_pins_b>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@3 { - status = "okay"; - }; -}; - -&timers5 { - /delete-property/dmas; - /delete-property/dma-names; - pwm { - pinctrl-0 = <&pwm5_pins_a>; - pinctrl-1 = <&pwm5_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@4 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - status = "okay"; -}; - -&usart2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_sleep_pins_a>; - status = "okay"; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_d>; - pinctrl-1 = <&usart3_sleep_pins_d>; - pinctrl-2 = <&usart3_idle_pins_d>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_hs_pins_a>; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts deleted file mode 100644 index 813086ec2489..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157c-ev1.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; - compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", - "st,stm32mp157"; - - reserved-memory { - optee@fe000000 { - reg = <0xfe000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cryp1 { - clocks = <&scmi_clk CK_SCMI_CRYP1>; - resets = <&scmi_reset RST_SCMI_CRYP1>; -}; - -&dsi { - phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&m_can1 { - clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts deleted file mode 100644 index af3800501875..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -/dts-v1/; - -#include "stm32mp157c-ed1.dts" -#include -#include -#include - -/ { - model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; - compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - - aliases { - serial1 = &usart3; - ethernet0 = ðernet0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - button-1 { - label = "JoyDown"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - }; - button-3 { - label = "JoyRight"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; - button-4 { - label = "JoyUp"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - }; - }; - - panel_backlight: panel-backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; - default-on; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -&dcmi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_a>; - pinctrl-1 = <&dcmi_sleep_pins_a>; - - port { - dcmi_0: endpoint { - remote-endpoint = <&ov5640_0>; - bus-type = ; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -&dsi { - phy-dsi-supply = <®18>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - - panel@0 { - compatible = "raydium,rm68200"; - reg = <0>; - reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; - backlight = <&panel_backlight>; - power-supply = <&v3v3>; - status = "okay"; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; - - nand-controller@4,0 { - status = "okay"; - - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - AVDD-supply = <&v2v8>; - DOVDD-supply = <&v2v8>; - DVDD-supply = <&v2v8>; - powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; - reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; - rotation = <180>; - status = "okay"; - - port { - ov5640_0: endpoint { - remote-endpoint = <&dcmi_0>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - vdd-supply = <&v3v3>; - - stmfx_pinctrl: pinctrl { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - bias-pull-down; - }; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -<dc { - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a - &qspi_bk2_pins_a - &qspi_cs2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a - &qspi_bk2_sleep_pins_a - &qspi_cs2_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - flash1: flash@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "disabled"; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-1 = <&pwm2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-1 = <&pwm8_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@7 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_b>; - pinctrl-1 = <&usart3_sleep_pins_b>; - pinctrl-2 = <&usart3_idle_pins_b>; - /* - * HW flow control USART3_RTS is optional, and isn't default wired to - * the connector. SB23 needs to be soldered in order to use it, and R77 - * (ETH_CLK) should be removed. - */ - uart-has-rtscts; - status = "disabled"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - /* onboard HUB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - vdd-supply = <&v3v3>; - }; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; - - connector { - compatible = "usb-a-connector"; - vbus-supply = <&vbus_sw>; - }; -}; - -&usbphyc_port1 { - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts deleted file mode 100644 index eada9cf257be..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ -/* - * Copyright (C) 2020 STMicroelectronics - All Rights Reserved - * Copyright (C) 2020 Ahmad Fatoum, Pengutronix - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xx-osd32.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" - -#include -#include - -/ { - model = "Linux Automation MC-1 board"; - compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - serial0 = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 31 63 95 127 159 191 223 255>; - default-brightness-level = <7>; - power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ - }; - - chosen { - stdout-path = &uart4; - }; - - led-controller-0 { - compatible = "gpio-leds"; - - led-0 { - label = "mc1:green:act"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-controller-1 { - compatible = "pwm-leds"; - - /* led-1 to led-3 are part of a single RGB led */ - led-1 { - label = "mc1:red:rgb"; - pwms = <&leds_pwm 1 1000000 0>; - max-brightness = <255>; - active-low; - }; - - led-2 { - label = "mc1:green:rgb"; - pwms = <&leds_pwm 2 1000000 0>; - max-brightness = <255>; - active-low; - }; - - led-3 { - label = "mc1:blue:rgb"; - pwms = <&leds_pwm 3 1000000 0>; - max-brightness = <255>; - active-low; - }; - }; - - panel: panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&backlight>; - enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - - port { - panel_input: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - }; - - reg_3v3: regulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&v3v3>; - }; - - /* supplied by either debug board or PoE */ - reg_5v2: regulator_5v2 { - compatible = "regulator-fixed"; - regulator-name = "5V2"; - regulator-min-microvolt = <5200000>; - regulator-max-microvolt = <5200000>; - regulator-always-on; - }; -}; - -ðernet0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ðernet0_rgmii_pins_b>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { /* KSZ9031RN */ - reg = <3>; - reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ - interrupt-parent = <&gpioa>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ - reset-assert-us = <10000>; - reset-deassert-us = <300>; - micrel,force-master; - }; - }; -}; - -&gpioz { - gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", - "HWID4", "HWID5"; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_b>; - pinctrl-1 = <&i2c5_sleep_pins_b>; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - interrupt-parent = <&gpiod>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ - vcc-supply = <®_3v3>; - reg = <0x38>; - reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ - touchscreen-size-x = <1792>; - touchscreen-size-y = <1024>; - wakeup-source; - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_c>; - pinctrl-1 = <<dc_sleep_pins_c>; - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&panel_input>; - }; - }; -}; - -&pmic { - regulators { - buck4-supply = <®_5v2>; /* VIN */ - ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ - ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ - boost-supply = <®_5v2>; /* PMIC_BSTIN */ - pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - bus-width = <4>; - cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; - disable-wp; - no-1-8-v; - st,neg-edge; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -&sdmmc1_b4_pins_a { - /* - * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to - * work, thus enable internal pull-ups. - */ - pins1 { - /delete-property/ bias-disable; - bias-pull-up; - }; - pins2 { - /delete-property/ bias-disable; - bias-pull-up; - }; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; - bus-width = <8>; - mmc-ddr-3_3v; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -&timers3 { - status = "okay"; - - backlight_pwm: pwm { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pwm3_pins_b>; - pinctrl-1 = <&pwm3_sleep_pins_b>; - status = "okay"; - }; -}; - -&timers5 { - status = "okay"; - - leds_pwm: pwm { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pwm5_pins_b>; - pinctrl-1 = <&pwm5_sleep_pins_b>; - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi deleted file mode 100644 index e22871dc580c..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2020 Marcin Sloniewski . - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "Seeed Studio Odyssey-STM32MP157C SOM"; - compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - led { - compatible = "gpio-leds"; - led-blue { - color = ; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v2_hdmi: ldo6 { - regulator-name = "v1v2_hdmi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; - mmc-ddr-3_3v; - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts deleted file mode 100644 index a8b3f7a54703..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2020 Marcin Sloniewski . - */ - -/dts-v1/; - -#include "stm32mp157c-odyssey-som.dtsi" - -/ { - model = "Seeed Studio Odyssey-STM32MP157C Board"; - compatible = "seeed,stm32mp157c-odyssey", - "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&dcmi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_b>; - pinctrl-1 = <&dcmi_sleep_pins_b>; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; - assigned-clock-parents = <&rcc PLL4_P>; - assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ - st,eth-clk-sel; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { /* KSZ9031RN */ - reg = <7>; - reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts deleted file mode 100644 index 28d7203264ce..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved - * Author: Dom VOVARD . - */ - -/dts-v1/; - -#include -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp157c-phycore-stm32mp15-som.dtsi" - -/ { - model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; - compatible = "phytec,phycore-stm32mp1-3", - "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; - - aliases { - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - mmc2 = &sdmmc3; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &usart1; - }; -}; - -&cryp1 { - status = "okay"; -}; - -&dts { - status = "okay"; -}; - -&fmc { - status = "disabled"; -}; - -&gpu { - status = "okay"; -}; - -&i2c4_eeprom { - status = "okay"; -}; - -&i2c4_rtc { - status = "okay"; -}; - -&qspi { - status = "okay"; -}; - -&sdmmc2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi deleted file mode 100644 index 4e8b2d2b30c7..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi +++ /dev/null @@ -1,577 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2022-2023 Steffen Trumtrar - * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved - * Author: Dom VOVARD . - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "stm32mp15-pinctrl.dtsi" - -/ { - model = "PHYTEC phyCORE-STM32MP15 SOM"; - compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - rtc0 = &i2c4_rtc; - rtc1 = &rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-home { - label = "Home"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-enter { - label = "Enter"; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32MP1-PHYCORE"; - routing = - "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ - "Capture", "MCLK"; - dais = <&sai2b_port>, - <&sai2a_port>; - }; - - regulator_vin: regulator { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -ðernet0 { - pinctrl-0 = <ðernet0_rgmii_pins_d>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_d>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - st,eth-clk-sel; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpiog>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - enet-phy-lane-no-swap; - ti,clk-output-sel = ; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-1 = <&i2c1_sleep_pins_b>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; - - codec@18 { - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - #sound-dai-cells = <0>; - - ai3x-micbias-vg = <2>; - - AVDD-supply = <&v3v3>; - IOVDD-supply = <&v3v3>; - DRVDD-supply = <&v3v3>; - DVDD-supply = <&v1v8_audio>; - - clocks = <&sai2b>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tlv320_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2b_endpoint>; - frame-master; - bitclock-master; - }; - - tlv320_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2a_endpoint>; - frame-master; - bitclock-master; - }; - }; - }; - - touch@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioi>; - vio-supply = <&v3v3>; - vcc-supply = <&v3v3>; - - touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - leds@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led-0 { - color = ; - function = LED_FUNCTION_POWER; - type = ; - }; - - led-1 { - color = ; - function = LED_FUNCTION_POWER; - type = ; - }; - - led-2 { - color = ; - function = LED_FUNCTION_HEARTBEAT; - type = ; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - pmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <®ulator_vin>; - buck2-supply = <®ulator_vin>; - buck3-supply = <®ulator_vin>; - buck4-supply = <®ulator_vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <®ulator_vin>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - boost-supply = <®ulator_vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - - }; - - vdd_eth_2v5: ldo2 { - regulator-name = "dd_eth_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - interrupts = ; - - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - vdd_eth_1v0: ldo6 { - regulator-name = "vdd_eth_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - interrupts = ; - - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , - ; - interrupt-names = "onkey-falling", - "onkey-rising"; - power-off-time-sec = <10>; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - }; - }; - - i2c4_eeprom: eeprom@50 { - compatible = "microchip,24c32", - "atmel,24c32"; - reg = <0x50>; - }; - - i2c4_rtc: rtc@52 { - compatible = "microcrystal,rv3028"; - reg = <0x52>; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names = "vq0", "vq1", "shutdown", "detach"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - status = "okay"; - - flash0: flash@0 { - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <50000000>; - m25p,fast-read; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; - pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; - status = "okay"; -}; - -&sai2a { - dma-names = "rx"; - st,sync = <&sai2b 2>; - clocks = <&rcc SAI2_K>, <&sai2b>; - clock-names = "sai_ck", "MCLK"; - #clock-cells = <0>; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&tlv320_rx_endpoint>; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; -}; - -&sai2b { - dma-names = "tx"; - #clock-cells = <0>; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&tlv320_tx_endpoint>; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; - cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; -}; - -&spi1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_a>; - pinctrl-1 = <&spi1_sleep_pins_a>; - cs-gpios = <&gpioz 3 0>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - pinctrl-3 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usart1 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; - pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; - pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_a>; - pinctrl-1 = <&usart3_sleep_pins_a>; - pinctrl-2 = <&usart3_idle_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi deleted file mode 100644 index b06a55a2fa18..000000000000 --- a/arch/arm/boot/dts/stm32mp15xc.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { - soc { - cryp1: cryp@54001000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54001000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi deleted file mode 100644 index 35b1034aa3cf..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut - */ - -#include -#include - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&adc { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&gpiob { - /* - * NOTE: On DRC02, the RS485_RX_En is controlled by a separate - * GPIO line, however the STM32 UART driver assumes RX happens - * during TX anyway and that it only controls drive enable DE - * line. Hence, the RX is always enabled here. - */ - rs485-rx-en-hog { - gpio-hog; - gpios = <8 0>; - output-low; - line-name = "rs485-rx-en"; - }; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-B", "", - "", "", "", "DRC02-Out1", - "DRC02-Out2", "", "", ""; -}; - -&gpioi { - gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", - "DHCOM-R", "DHCOM-M", "", "", - "DRC02-In2", "", "", "", - "", "", "", ""; - - /* - * NOTE: The USB Hub on the DRC02 needs a reset signal to be - * pulled high in order to be detected by the USB Controller. - * This signal should be handled by USB power sequencing in - * order to reset the Hub when USB bus is powered down, but - * so far there is no such functionality. - */ - usb-hub-hog { - gpio-hog; - gpios = <2 0>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c4 { - touchscreen@49 { - status = "disabled"; - }; -}; - -&i2c5 { /* TP7/TP8 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&sdmmc3 { - /* - * On DRC02, the SoM does not have SDIO WiFi. The pins - * are used for on-board microSD slot instead. - */ - /delete-property/broken-cd; - cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; - disable-wp; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - cs-gpios = <&gpioz 3 0>; - /* Use PIO for the display */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; /* Enable once there is display driver */ - /* - * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are - * also connected to the display board connector. - */ -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* - * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), - * however the STM32MP1 pinmux cannot map them to UART4 . - */ - -&uart8 { /* RS485 */ - linux,rs485-enabled-at-boot-time; - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi deleted file mode 100644 index 46b87a27d8b3..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ /dev/null @@ -1,332 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2019-2020 Marek Vasut - */ - -#include -#include - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - display_bl: display-bl { - compatible = "pwm-backlight"; - pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; - power-supply = <®_panel_bl>; - status = "okay"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - /* - * The EXTi IRQ line 3 is shared with ethernet, - * so mark this as polled GPIO key. - */ - button-0 { - label = "TA1-GPIO-A"; - linux,code = ; - gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; - }; - - /* - * The EXTi IRQ line 6 is shared with touchscreen, - * so mark this as polled GPIO key. - */ - button-1 { - label = "TA2-GPIO-B"; - linux,code = ; - gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; - }; - - /* - * The EXTi IRQ line 0 is shared with PMIC, - * so mark this as polled GPIO key. - */ - button-2 { - label = "TA3-GPIO-C"; - linux,code = ; - gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-3 { - label = "TA4-GPIO-D"; - linux,code = ; - gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - label = "green:led5"; - gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - status = "disabled"; - }; - - led-1 { - label = "green:led6"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "green:led7"; - gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "green:led8"; - gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - power-supply = <®_panel_bl>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_panel_bl: regulator-panel-bl { - compatible = "regulator-fixed"; - regulator-name = "panel_backlight"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_panel_supply>; - }; - - reg_panel_supply: regulator-panel-supply { - compatible = "regulator-fixed"; - regulator-name = "panel_supply"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - - sound { - compatible = "audio-graph-card"; - widgets = "Headphone", "Headphone Jack", - "Line", "Line In Jack", - "Microphone", "Microphone Jack"; - routing = "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias"; - dais = <&sai2a_port &sai2b_port>; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -&i2c2 { /* Header X22 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&i2c5 { /* Header X21 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <&v3v3>; - VDDIO-supply = <&vdd>; - - sgtl5000_port: port { - #address-cells = <1>; - #size-cells = <0>; - - sgtl5000_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master = <&sgtl5000_tx_endpoint>; - bitclock-master = <&sgtl5000_tx_endpoint>; - }; - - sgtl5000_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master = <&sgtl5000_rx_endpoint>; - bitclock-master = <&sgtl5000_rx_endpoint>; - }; - }; - - }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpioc>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_sleep_pins_b>; - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&sgtl5000_tx_endpoint>; - dai-format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&sgtl5000_rx_endpoint>; - dai-format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm2: pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi deleted file mode 100644 index abc595350e71..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut - */ - -#include -#include - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - label = "yellow:led"; - gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&adc { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&fmc { - status = "disabled"; -}; - -&gpioa { - /* - * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable - * port power. This signal should be handled by USB power sequencing - * in order to turn on port power when USB bus is powered up, but so - * far there is no such functionality. - */ - usb-port-power-hog { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "usb-port-power"; - }; -}; - -&gpioc { - gpio-line-names = "", "", "", "", - "", "", "PicoITX-In1", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-B", "", - "", "", "", "PicoITX-Out1", - "PicoITX-Out2", "", "", ""; -}; - -&gpiog { - gpio-line-names = "PicoITX-In2", "", "", "", - "", "", "", "", - "DHCOM-L", "", "", "", - "", "", "", ""; -}; - -&i2c2 { /* On board-to-board connector (optional) */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c5 { /* On board-to-board connector */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&ksz8851 { - status = "disabled"; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi deleted file mode 100644 index e61df23d361a..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ /dev/null @@ -1,546 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2019-2020 Marek Vasut - */ - -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include -#include - -/ { - aliases { - ethernet0 = ðernet0; - ethernet1 = &ksz8851; - rtc0 = &hwrtc; - rtc1 = &rtc; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -&adc { - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; -}; - -&adc1 { - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; -}; - -&adc2 { - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; -}; - -&crc1 { - status = "okay"; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "okay"; - - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - /* LAN8710Ai */ - compatible = "ethernet-phy-id0007.c0f0", - "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc CK_MCO2>; - reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; - reset-assert-us = <500>; - reset-deassert-us = <500>; - smsc,disable-energy-detect; - interrupt-parent = <&gpioi>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_b>; - pinctrl-1 = <&fmc_sleep_pins_b>; - status = "okay"; - - ksz8851: ethernet@1,0 { - compatible = "micrel,ks8851-mll"; - reg = <1 0x0 0x2>, <1 0x2 0x20000>; - interrupt-parent = <&gpioc>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - bank-width = <2>; - - /* Timing values are in nS */ - st,fmc2-ebi-cs-mux-enable; - st,fmc2-ebi-cs-transaction-type = <4>; - st,fmc2-ebi-cs-buswidth = <16>; - st,fmc2-ebi-cs-address-setup-ns = <5>; - st,fmc2-ebi-cs-address-hold-ns = <5>; - st,fmc2-ebi-cs-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-data-setup-ns = <45>; - st,fmc2-ebi-cs-data-hold-ns = <1>; - st,fmc2-ebi-cs-write-address-setup-ns = <5>; - st,fmc2-ebi-cs-write-address-hold-ns = <5>; - st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-write-data-setup-ns = <45>; - st,fmc2-ebi-cs-write-data-hold-ns = <1>; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-K", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiob { - gpio-line-names = "", "", "", "", - "", "", "", "", - "DHCOM-Q", "", "", "", - "", "", "", ""; -}; - -&gpioc { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-E", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-B", "", - "", "", "", "DHCOM-F", - "DHCOM-D", "", "", ""; -}; - -&gpioe { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-P", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiof { - gpio-line-names = "", "", "", "DHCOM-A", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiog { - gpio-line-names = "DHCOM-C", "", "", "", - "", "", "", "", - "DHCOM-L", "", "", "", - "", "", "", ""; -}; - -&gpioh { - gpio-line-names = "", "", "", "", - "", "", "", "DHCOM-N", - "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", - "DHCOM-T", "", "DHCOM-S", ""; -}; - -&gpioi { - gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", - "DHCOM-R", "DHCOM-M", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - hwrtc: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-always-on; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - touchscreen@49 { - compatible = "ti,tsc2004"; - reg = <0x49>; - vio-supply = <&v3v3>; - interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rcc { - /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ - clocks = <&rcc CK_MCO2>; - clock-names = "ETH_RX_CLK/ETH_REF_CLK"; - - /* - * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, - * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, - * so that MCO2 behaves as a divider for the ETHRX clock here. - */ - assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; - assigned-clock-parents = <&rcc PLL4_P>; - assigned-clock-rates = <50000000>, <100000000>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep", "init"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; - cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - st,cmd-gpios = <&gpiod 2 0>; - st,ck-gpios = <&gpioc 12 0>; - st,ckin-gpios = <&gpioe 4 0>; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&sdmmc1_b4_pins_a { - /* - * SD bus pull-up resistors: - * - optional on SoMs with SD voltage translator - * - mandatory on SoMs without SD voltage translator - */ - pins1 { - bias-pull-up; - }; - pins2 { - bias-pull-up; - }; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi deleted file mode 100644 index 0069ad75d55e..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - * Copyright (C) 2020 Marek Vasut - */ - -/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ -#include "stm32mp15xx-dhcor-io1v8.dtsi" - -/ { - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - serial2 = &usart2; - spi0 = &qspi; - }; - - /* XTal Q1 */ - cec_clock: clk-cec-fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7513_out>; - }; - }; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user0"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user1"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user2"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - panic-indicator; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32-AV96-HDMI"; - dais = <&sai2a_port>; - status = "okay"; - }; - - wlan_pwr: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpioz 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; -}; - -&adc1 { - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; - - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; - - channel@6 { - reg = <6>; - st,min-sample-time-ns = <5000>; - }; -}; - -&adc2 { - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; - - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; - - channel@2 { - reg = <2>; - st,min-sample-time-ns = <5000>; - }; -}; - -&dcmi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_c>; - pinctrl-1 = <&dcmi_sleep_pins_c>; - status = "disabled"; - - port { - dcmi_0: endpoint { - remote-endpoint = <&stmipi_2>; - bus-type = <5>; - bus-width = <8>; - pclk-sample = <0>; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "AV96-K", - "AV96-I", "", "AV96-A", ""; -}; - -&gpiob { - gpio-line-names = "", "", "", "", - "", "AV96-J", "", "", - "", "", "", "AV96-B", - "", "AV96-L", "", ""; -}; - -&gpioc { - gpio-line-names = "", "", "", "AV96-C", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "", "", - "AV96-D", "", "", "", - "", "", "AV96-E", "AV96-F"; -}; - -&gpiof { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "", - "AV96-G", "AV96-H", "", ""; -}; - -&i2c1 { /* X6 I2C1 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { /* X6 I2C2 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_c>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - stmipi: stmipi@14 { - compatible = "st,st-mipid02"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mco1_pins_a>; - pinctrl-1 = <&mco1_sleep_pins_a>; - reg = <0x14>; - clocks = <&rcc CK_MCO1>; - clock-names = "xclk"; - assigned-clocks = <&rcc CK_MCO1>; - assigned-clock-parents = <&rcc CK_HSE>; - assigned-clock-rates = <24000000>; - VDDE-supply = <&v1v8>; - VDDIN-supply = <&v1v8>; - reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stmipi_0: endpoint { - }; - }; - - port@2 { - reg = <2>; - stmipi_2: endpoint { - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <0>; - remote-endpoint = <&dcmi_0>; - }; - }; - }; - }; - - hdmi-transmitter@3d { - compatible = "adi,adv7513"; - reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; - reg-names = "main", "edid", "cec", "packet"; - clocks = <&cec_clock>; - clock-names = "cec"; - - avdd-supply = <&v3v3>; - dvdd-supply = <&v3v3>; - pvdd-supply = <&v3v3>; - dvdd-3v-supply = <&v3v3>; - bgvdd-supply = <&v3v3>; - - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpiog>; - - status = "okay"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7513_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - - port@2 { - reg = <2>; - adv7513_i2s0: endpoint { - remote-endpoint = <&sai2a_endpoint>; - }; - }; - }; - }; - - dh_mac_eeprom: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_d>; - pinctrl-1 = <<dc_sleep_pins_d>; - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&adv7513_in>; - }; - }; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_c>; - pinctrl-1 = <&sai2a_sleep_pins_c>; - clock-names = "pclk", "x8k", "x11k"; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&adv7513_i2s0>; - dai-format = "i2s"; - mclk-fs = <256>; - }; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; - bus-width = <8>; - mmc-ddr-1_8v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd_io>; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_b>; - pinctrl-1 = <&sdmmc3_b4_od_pins_b>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; - broken-cd; - non-removable; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&wlan_pwr>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - cs-gpios = <&gpioi 0 0>; - status = "disabled"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* Bluetooth */ -&usart2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_sleep_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - status = "okay"; - vbus-supply = <&vbus_otg>; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi deleted file mode 100644 index 92d906bfd5d7..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ /dev/null @@ -1,348 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut - */ - -/ { - aliases { - ethernet0 = ðernet0; - ethernet1 = &ksz8851; - mmc0 = &sdmmc1; - rtc0 = &hwrtc; - rtc1 = &rtc; - serial0 = &uart4; - serial1 = &uart8; - serial2 = &usart3; - serial3 = &uart5; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "yellow:user0"; - gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "red:user1"; - gpios = <&gpioz 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpioh 2 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -&adc { /* X11 ADC inputs */ - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - status = "okay"; - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; - channel@6 { - reg = <6>; - st,min-sample-time-ns = <5000>; - }; - }; - - adc2: adc@100 { - status = "okay"; - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; - channel@2 { - reg = <2>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_b>; - pinctrl-1 = <&fmc_sleep_pins_b>; - status = "okay"; - - ksz8851: ethernet@1,0 { - compatible = "micrel,ks8851-mll"; - reg = <1 0x0 0x2>, <1 0x2 0x20000>; - interrupt-parent = <&gpioc>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - bank-width = <2>; - - /* Timing values are in nS */ - st,fmc2-ebi-cs-mux-enable; - st,fmc2-ebi-cs-transaction-type = <4>; - st,fmc2-ebi-cs-buswidth = <16>; - st,fmc2-ebi-cs-address-setup-ns = <5>; - st,fmc2-ebi-cs-address-hold-ns = <5>; - st,fmc2-ebi-cs-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-data-setup-ns = <45>; - st,fmc2-ebi-cs-data-hold-ns = <1>; - st,fmc2-ebi-cs-write-address-setup-ns = <5>; - st,fmc2-ebi-cs-write-address-hold-ns = <5>; - st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-write-data-setup-ns = <45>; - st,fmc2-ebi-cs-write-data-hold-ns = <1>; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "DRCC-VAR2", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpioe { - gpio-line-names = "", "", "", "", - "", "DRCC-GPIO0", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiog { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "", - "DRCC-GPIO5", "", "", ""; -}; - -&gpioh { - gpio-line-names = "", "", "", "DRCC-HW2", - "DRCC-GPIO4", "", "", "", - "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1", - "DRCC-VAR0", "", "", "DRCC-GPIO6"; -}; - -&gpioi { - gpio-line-names = "", "", "", "", - "", "", "", "DRCC-GPIO2", - "", "DRCC-GPIO1", "", "", - "", "", "", ""; -}; - -&i2c1 { /* X11 I2C1 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - hwrtc: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; - - dh_mac_eeprom: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&sdmmc1 { /* MicroSD */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&vdd>; - vqmmc-supply = <&vdd>; - status = "okay"; -}; - -&sdmmc2 { /* eMMC */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; - status = "okay"; -}; - -&sdmmc3 { /* SDIO Wi-Fi */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - bus-width = <4>; - mmc-ddr-3_3v; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - status = "okay"; -}; - -&spi2 { /* X11 SPI */ - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b>; - cs-gpios = <&gpioi 0 0>; - status = "disabled"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&uart4 { - label = "UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_d>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart5 { /* X11 UART */ - label = "X11-UART5"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - label = "RS485-1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usart3 { /* RS485 or RS232 */ - label = "RS485-2"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart3_pins_e>; - pinctrl-1 = <&usart3_sleep_pins_e>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - connector { - compatible = "usb-a-connector"; - vbus-supply = <&vbus_sw>; - }; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi deleted file mode 100644 index 9937b28548c2..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - * Copyright (C) 2020 Marek Vasut - */ - -/ { - /* Enpirion EP3A8LQI U2 on the DHCOR */ - vdd_io: regulator-buck-io { - compatible = "regulator-fixed"; - regulator-name = "buck-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -&vdd { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; -}; - -&pwr_regulators { - vdd-supply = <&vdd_io>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi deleted file mode 100644 index bba19f21e527..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - * Copyright (C) 2020 Marek Vasut - */ - -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include - -/ { - aliases { - spi0 = &qspi; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; -}; - -&crc1 { - status = "okay"; -}; - -&dts { - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x200000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi deleted file mode 100644 index ab7f0ba49639..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut - */ - -/ { - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - serial0 = &uart4; - serial1 = &uart7; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - status = "okay"; - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; - channel@6 { - reg = <6>; - st,min-sample-time-ns = <5000>; - }; - }; - - adc2: adc@100 { - status = "okay"; - channel@0 { - reg = <0>; - st,min-sample-time-ns = <5000>; - }; - channel@1 { - reg = <1>; - st,min-sample-time-ns = <5000>; - }; - channel@2 { - reg = <2>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&i2c4 { - dh_mac_eeprom: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; - bus-width = <8>; - mmc-ddr-1_8v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - status = "okay"; - vbus-supply = <&vbus_otg>; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi deleted file mode 100644 index 511113f2e399..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ /dev/null @@ -1,741 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include -#include - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - led { - compatible = "gpio-leds"; - led-blue { - label = "heartbeat"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32MP15-DK"; - routing = - "Playback" , "MCLK", - "Capture" , "MCLK", - "MICL" , "Mic Bias"; - dais = <&sai2a_port &sai2b_port &i2s2_port>; - status = "okay"; - }; - - vin: vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_usb_cc_pins_a>; - vdd-supply = <&vdd>; - vdda-supply = <&vdd>; - vref-supply = <&vrefbuf>; - status = "okay"; - adc1: adc@0 { - status = "okay"; - /* - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: - * 5 * (56 + 47kOhms) * 5pF => 2.5us. - * Use arbitrary margin here (e.g. 5us). - */ - channel@18 { - reg = <18>; - st,min-sample-time-ns = <5000>; - }; - channel@19 { - reg = <19>; - st,min-sample-time-ns = <5000>; - }; - }; - adc2: adc@100 { - status = "okay"; - /* USB Type-C CC1 & CC2 */ - channel@18 { - reg = <18>; - st,min-sample-time-ns = <5000>; - }; - channel@19 { - reg = <19>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -&cec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_sleep_pins_b>; - status = "okay"; -}; - -&crc1 { - status = "okay"; -}; - -&dts { - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&hash1 { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - hdmi-transmitter@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - iovcc-supply = <&v3v3_hdmi>; - cvcc12-supply = <&v1v2_hdmi>; - reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpiog>; - #sound-dai-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sii9022_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@3 { - reg = <3>; - sii9022_tx_endpoint: endpoint { - remote-endpoint = <&i2s2_endpoint>; - }; - }; - }; - }; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - VL-supply = <&v3v3>; - VD-supply = <&v1v8_audio>; - VA-supply = <&v1v8_audio>; - VAHP-supply = <&v1v8_audio>; - reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; - clocks = <&sai2a>; - clock-names = "MCLK"; - status = "okay"; - - cs42l51_port: port { - #address-cells = <1>; - #size-cells = <0>; - - cs42l51_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master = <&cs42l51_tx_endpoint>; - bitclock-master = <&cs42l51_tx_endpoint>; - }; - - cs42l51_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master = <&cs42l51_rx_endpoint>; - bitclock-master = <&cs42l51_rx_endpoint>; - }; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - stusb1600@28 { - compatible = "st,stusb1600"; - reg = <0x28>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpioi>; - pinctrl-names = "default"; - pinctrl-0 = <&stusb1600_pins_a>; - status = "okay"; - vdd-supply = <&vin>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - typec-power-opmode = "default"; - - port { - con_usbotg_hs_ep: endpoint { - remote-endpoint = <&usbotg_hs_ep>; - }; - }; - }; - }; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <&vin>; - buck2-supply = <&vin>; - buck3-supply = <&vin>; - buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&vin>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <&vin>; - ldo5-supply = <&vin>; - ldo6-supply = <&v3v3>; - vref_ddr-supply = <&vin>; - boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v2_hdmi: ldo6 { - regulator-name = "v1v2_hdmi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; -}; - -&i2s2 { - clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "i2sclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_sleep_pins_a>; - status = "okay"; - - i2s2_port: port { - i2s2_endpoint: endpoint { - remote-endpoint = <&sii9022_tx_endpoint>; - dai-format = "i2s"; - mclk-fs = <256>; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_sleep_pins_a>; - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&sii9022_in>; - }; - }; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names = "vq0", "vq1", "shutdown", "detach"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&cs42l51_tx_endpoint>; - dai-format = "i2s"; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&cs42l51_rx_endpoint>; - dai-format = "i2s"; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&timers1 { - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm1_pins_a>; - pinctrl-1 = <&pwm1_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm3_pins_a>; - pinctrl-1 = <&pwm3_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@2 { - status = "okay"; - }; -}; - -&timers4 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; - pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@3 { - status = "okay"; - }; -}; - -&timers5 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm5_pins_a>; - pinctrl-1 = <&pwm5_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@4 { - status = "okay"; - }; -}; - -&timers6 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - timer@5 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart7_pins_c>; - pinctrl-1 = <&uart7_sleep_pins_c>; - pinctrl-2 = <&uart7_idle_pins_c>; - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_c>; - pinctrl-1 = <&usart3_sleep_pins_c>; - pinctrl-2 = <&usart3_idle_pins_c>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - /* onboard HUB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - vdd-supply = <&v3v3>; - }; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - usb-role-switch; - status = "okay"; - - port { - usbotg_hs_ep: endpoint { - remote-endpoint = <&con_usbotg_hs_ep>; - }; - }; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi deleted file mode 100644 index a43965c86fe8..000000000000 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ -/* - * Copyright (C) 2020 STMicroelectronics - All Rights Reserved - * Copyright (C) 2020 Ahmad Fatoum, Pengutronix - */ - -#include "stm32mp15-pinctrl.dtsi" - -#include - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = ; - - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v2_hdmi: ldo6 { - regulator-name = "v1v2_hdmi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - interrupts = ; - - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - }; - - pmic_watchdog: watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - sip_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - vcc-supply = <&vdd>; - reg = <0x50>; - }; -}; - -&ipcc { - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names = "vq0", "vq1", "shutdown", "detach"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&rng1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi deleted file mode 100644 index 04f7a43ad66f..000000000000 --- a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@5000a000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@5000b000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@5000c000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; - }; -}; - -&pinctrl_z { - st,package = ; - - gpioz: gpio@54004000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi deleted file mode 100644 index 328dad140e9b..000000000000 --- a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi deleted file mode 100644 index 7eaa245f44db..000000000000 --- a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@5000a000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - st,package = ; - - gpioz: gpio@54004000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; - }; -}; diff --git a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi deleted file mode 100644 index b63e207de216..000000000000 --- a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts deleted file mode 100644 index 20f9ed244851..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2013 Emilio López - * - * Emilio López - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele A1000"; - compatible = "mele,a1000", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "a1000:red:usr"; - gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "a1000:blue:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts deleted file mode 100644 index 816d534ac093..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "BA10 tvbox"; - compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts deleted file mode 100644 index 74262988881c..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "Chuwi V7 CW0825"; - compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ft5306de4: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-800 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts deleted file mode 100644 index 0645d6064235..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Cubietech Cubieboard"; - compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard>; - - led-0 { - label = "cubieboard:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */ - }; - - led-1 { - label = "cubieboard:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_cubieboard: led-pins { - pins = "PH20", "PH21"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts deleted file mode 100644 index 63e77c05bfda..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "Dserve DSRV9703C"; - compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <®_motor>; - min-microvolt = <3000000>; - max-microvolt = <3000000>; - }; - - reg_motor: reg-motor { - compatible = "regulator-fixed"; - regulator-name = "vcc-motor"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button-800 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts deleted file mode 100644 index ea7a59dcf8f9..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2015 Priit Laes - * - * Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "Gemei G9 Tablet"; - compatible = "gemei,g9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* - * TODO: - * 2x cameras via CSI - * AXP battery management - * NAND - * OTG - * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 - */ -&codec { - /* PH15 controls power to external amplifier (ft2012q) */ - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */ - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - - status = "okay"; - - button-158 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; - - button-1142 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1142856>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts deleted file mode 100644 index 47dea0922501..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Miniand Hackberry"; - compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy0>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts deleted file mode 100644 index bf2044bac42f..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Hyundai A7HD"; - compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts deleted file mode 100644 index 60e432a0ef1c..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "iNet-1"; - compatible = "inet-tek,inet1", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - status = "okay"; - - ft5x: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ - touchscreen-size-x = <600>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-1000 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts deleted file mode 100644 index 76016f2ca29d..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2014 Open Source Support GmbH - * - * David Lanzendörfer - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "INet-97F Rev 02"; - compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-600 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts deleted file mode 100644 index 62e7aa587f89..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "iNet-9F Rev 03"; - compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - event-left-joystick-left { - label = "Left Joystick Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ - }; - - event-left-joystick-right { - label = "Left Joystick Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ - }; - - event-left-joystick-up { - label = "Left Joystick Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ - }; - - event-left-joystick-down { - label = "Left Joystick Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ - }; - - event-right-joystick-left { - label = "Right Joystick Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ - }; - - event-right-joystick-right { - label = "Right Joystick Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ - }; - - event-right-joystick-up { - label = "Right Joystick Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ - }; - - event-right-joystick-down { - label = "Right Joystick Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ - }; - - event-dpad-left { - label = "DPad Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ - }; - - event-dpad-right { - label = "DPad Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ - }; - - event-dpad-up { - label = "DPad Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ - }; - - event-dpad-down { - label = "DPad Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ - }; - - event-x { - label = "Button X"; - linux,code = ; - gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ - }; - - event-y { - label = "Button Y"; - linux,code = ; - gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ - }; - - event-a { - label = "Button A"; - linux,code = ; - gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ - }; - - event-b { - label = "Button B"; - linux,code = ; - gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ - }; - - event-select { - label = "Select Button"; - linux,code = ; - gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ - }; - - event-start { - label = "Start Button"; - linux,code = ; - gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ - }; - - event-top-left { - label = "Top Left Button"; - linux,code = ; - gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ - }; - - event-top-right { - label = "Top Right Button"; - linux,code = ; - gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-600 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts deleted file mode 100644 index d4e319d16aae..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2015 Josef Gajdusek - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Iteaduino Plus A10"; - compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - axp209: pmic@34 { - interrupts = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts deleted file mode 100644 index 1aeb0bd5519e..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2015 Gábor Nyers - * - * Gábor Nyers - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Jesurun Q5"; - compatible = "jesurun,q5", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "q5:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ - }; - - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts deleted file mode 100644 index 81fdb217d339..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "HAOYU Electronics Marsboard A10"; - compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "marsboard:red1:usr"; - gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "marsboard:red2:usr"; - gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "marsboard:red3:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "marsboard:red4:usr"; - gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts deleted file mode 100644 index f9d74e21031d..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "PineRiver Mini X-Plus"; - compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&ir0_rx_pins { - /* The ir receiver is not always populated */ - bias-pull-up; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts deleted file mode 100644 index 059fe9c5d024..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802"; - compatible = "allwinner,mk802", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts deleted file mode 100644 index 17dcdf031118..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802ii"; - compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts deleted file mode 100644 index 83d283cf6633..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright 2014 - Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Olimex A10-OLinuXino-LIME"; - compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - led { - label = "a10-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&cpu0 { - /* - * The A10-Lime is known to be unstable when running at 1008 MHz - */ - operating-points = - /* kHz uV */ - <912000 1350000>, - <864000 1300000>, - <624000 1250000>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinolime: led-pin { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts deleted file mode 100644 index a332d61fd561..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "LinkSprite pcDuino"; - compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "pcduino:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "pcduino:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-back { - label = "Key Back"; - linux,code = ; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - - key-home { - label = "Key Home"; - linux,code = ; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - - key-menu { - label = "Key Menu"; - linux,code = ; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ - usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts deleted file mode 100644 index bc4f128965ed..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2015 Siarhei Siamashka - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The LinkSprite pcDuino2 board is almost identical to the older - * LinkSprite pcDuino1 board. The only software visible difference - * is that the pcDuino2 board got a USB VBUS voltage regulator, which - * is controlled by the PD2 pin (pulled-up by default). Also one of - * the USB host ports has been replaced with a USB WIFI chip. - */ - -#include "sun4i-a10-pcduino.dts" - -/ { - model = "LinkSprite pcDuino2"; - compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; -}; - -®_usb2_vbus { - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */ - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts deleted file mode 100644 index c32596947647..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "Point of View Protab2-IPS9"; - compatible = "pov,protab2-ips9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - status = "okay"; - - touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ - enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-400 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10-topwise-a721.dts b/arch/arm/boot/dts/sun4i-a10-topwise-a721.dts deleted file mode 100644 index 3628f12d2521..000000000000 --- a/arch/arm/boot/dts/sun4i-a10-topwise-a721.dts +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 Pascal Roeleven - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "Topwise A721"; - compatible = "topwise,a721", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>; - power-supply = <®_vbat>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - panel { - compatible = "starry,kr070pe2t"; - backlight = <&backlight>; - power-supply = <®_lcd_power>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; - }; - - reg_lcd_power: reg-lcd-power { - compatible = "regulator-fixed"; - regulator-name = "reg-lcd-power"; - gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - enable-active-high; - }; - - reg_vbat: reg-vbat { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - accelerometer@4c { - compatible = "fsl,mma7660"; - reg = <0x4c>; - }; -}; - -&i2c2 { - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - vcc-supply = <®_vcc3v3>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-571 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <571428>; - }; - - button-761 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <761904>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vcc-pb-supply = <®_vcc3v3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-ph-supply = <®_vcc3v3>; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&tcon0_out { - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi deleted file mode 100644 index 51a6464aab9a..000000000000 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ /dev/null @@ -1,1271 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1400000>, - <912000 1350000>, - <864000 1300000>, - <624000 1250000>; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu-alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun4i-a10-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x40000000 0x10000000>; - reusable; - linux,cma-default; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun4i-a10-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&ccu RST_TCON0>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD0>, - <&ccu CLK_TCON0_CH0>, - <&ccu CLK_TCON0_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - - tcon0_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun4i-a10-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = <45>; - resets = <&ccu RST_TCON1>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD1>, - <&ccu CLK_TCON1_CH0>, - <&ccu CLK_TCON1_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 15>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon1>; - }; - - tcon1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun4i-a10-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = <53>; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - interrupts = <32>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; - clock-names = "ahb", "mmc"; - interrupts = <35>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&ccu CLK_USB_PHY>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ccu CLK_AHB_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <64>; - clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <86>; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun4i-a10-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; - status = "disabled"; - }; - - ehci1: usb@1c1c000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = <40>; - clocks = <&ccu CLK_AHB_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1c400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = <65>; - clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - csi1: csi@1c1d000 { - compatible = "allwinner,sun4i-a10-csi1"; - reg = <0x01c1d000 0x1000>; - interrupts = <43>; - clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; - clock-names = "bus", "ram"; - resets = <&ccu RST_CSI1>; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = <50>; - clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun4i-a10-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun4i-a10-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - can0_ph_pins: can0-ph-pins { - pins = "PH20", "PH21"; - function = "can"; - }; - - /omit-if-no-ref/ - csi1_8bits_pg_pins: csi1-8bits-pg-pins { - pins = "PG0", "PG2", "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8", "PG9", "PG10", - "PG11"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_24bits_ph_pins: csi1-24bits-ph-pins { - pins = "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH8", "PH9", - "PH10", "PH11", "PH12", "PH13", "PH14", - "PH15", "PH16", "PH17", "PH18", "PH19", - "PH20", "PH21", "PH22", "PH23", "PH24", - "PH25", "PH26", "PH27"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_clk_pg_pin: csi1-clk-pg-pin { - pins = "PG1"; - function = "csi1"; - }; - - emac_pins: emac0-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - ir0_rx_pins: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - ir0_tx_pins: ir0-tx-pin { - pins = "PB3"; - function = "ir0"; - }; - - ir1_rx_pins: ir1-rx-pin { - pins = "PB23"; - function = "ir1"; - }; - - ir1_tx_pins: ir1-tx-pin { - pins = "PB22"; - function = "ir1"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - ps2_ch0_pins: ps2-ch0-pins { - pins = "PI20", "PI21"; - function = "ps2"; - }; - - ps2_ch1_ph_pins: ps2-ch1-ph-pins { - pins = "PH12", "PH13"; - function = "ps2"; - }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - pwm1_pin: pwm1-pin { - pins = "PI3"; - function = "pwm"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PB13"; - function = "spdif"; - bias-pull-up; - }; - - spi0_pi_pins: spi0-pi-pins { - pins = "PI11", "PI12", "PI13"; - function = "spi0"; - }; - - spi0_cs0_pi_pin: spi0-cs0-pi-pin { - pins = "PI10"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - spi1_cs0_pin: spi1-cs0-pin { - pins = "PI16"; - function = "spi1"; - }; - - spi2_pb_pins: spi2-pb-pins { - pins = "PB15", "PB16", "PB17"; - function = "spi2"; - }; - - spi2_pc_pins: spi2-pc-pins { - pins = "PC20", "PC21", "PC22"; - function = "spi2"; - }; - - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB14"; - function = "spi2"; - }; - - spi2_cs0_pc_pins: spi2-cs0-pc-pin { - pins = "PC19"; - function = "spi2"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PA10", "PA11"; - function = "uart1"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>, - <23>, - <24>, - <25>, - <67>, - <68>; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = <24>; - clocks = <&osc24M>; - }; - - rtc: rtc@1c20d00 { - compatible = "allwinner,sun4i-a10-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = <24>; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun4i-a10-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@1c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; - clock-names = "apb", "ir"; - interrupts = <6>; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = <17>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = <18>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = <19>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = <20>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART7>; - status = "disabled"; - }; - - ps20: ps2@1c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <62>; - clocks = <&ccu CLK_APB1_PS20>; - status = "disabled"; - }; - - ps21: ps2@1c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = <63>; - clocks = <&ccu CLK_APB1_PS21>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@1c2bc00 { - compatible = "allwinner,sun4i-a10-can"; - reg = <0x01c2bc00 0x400>; - interrupts = <26>; - clocks = <&ccu CLK_APB1_CAN>; - status = "disabled"; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = <69>, - <70>, - <71>, - <72>, - <73>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun4i-a10-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_DRAM_DE_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun4i-a10-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = <48>; - clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, - <&ccu CLK_DRAM_DE_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun4i-a10-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = <48>; - clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, - <&ccu CLK_DRAM_DE_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be1>; - }; - - be1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun4i-a10-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DRAM_DE_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - - be0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts deleted file mode 100644 index 04b0e6d28769..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Auxtek t003 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t003>; - - led { - label = "t003-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_t003: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts deleted file mode 100644 index 667bc2dc1ea9..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Auxtek t004 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t004>; - - led { - label = "t004-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; - - reg_vmmc1: vmmc1 { - compatible = "regulator-fixed"; - regulator-name = "vmmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vmmc1>; - bus-width = <4>; - non-removable; - cap-sdio-irq; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_t004: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts deleted file mode 100644 index d0219404c231..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802-A10s"; - compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "mk802:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts deleted file mode 100644 index 5832bb31fc51..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A10s-Olinuxino Micro"; - compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - led { - label = "a10s-olinuxino-micro:green:usr"; - gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pa_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - reg = <0x30>; - interrupts = <0>; - }; -}; - -#include "axp152.dtsi" - -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - read-only; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxino: led-pin { - pins = "PE3"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pb_pins>, - <&spi2_cs0_pb_pin>; - status = "okay"; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pc_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts deleted file mode 100644 index 964360f0610a..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "R7 A10s hdmi tv-stick"; - compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_r7>; - - led { - label = "r7-tv-dongle:green:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - led_pins_r7: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts deleted file mode 100644 index ef8baa992687..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2015 Jelle van der Waa - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "A10s-Wobo i5"; - compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "a10s-wobo-i5:blue:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pd_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_ldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi2"; -}; - -®_usb1_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi deleted file mode 100644 index 09c486b608b2..000000000000 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include - -/ { - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, - <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, - <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a10s-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun5i-a10s-ccu"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&pio { - compatible = "allwinner,sun5i-a10s-pinctrl"; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB19", "PB20"; - function = "uart0"; - }; - - uart2_pc_pins: uart2-pc-pins { - pins = "PC18", "PC19"; - function = "uart2"; - }; - - emac_pa_pins: emac-pa-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - mmc1_pins: mmc1-pins { - pins = "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8"; - function = "mmc1"; - drive-strength = <30>; - }; - - spi2_pb_pins: spi2-pb-pins { - pins = "PB12", "PB13", "PB14"; - function = "spi2"; - }; - - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB11"; - function = "spi2"; - }; -}; - -&tcon0_out { - tcon0_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts deleted file mode 100644 index 894c4c4f9a1f..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Difrnce DIT4350"; - compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts deleted file mode 100644 index d059388d7252..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "Empire Electronix D709 tablet"; - compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - power-supply = <®_vcc3v3>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts deleted file mode 100644 index b1e2afd9de52..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include - -/ { - model = "Empire Electronix M712 tablet"; - compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts deleted file mode 100644 index 9b9f2a574851..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "HSG H702"; - compatible = "hsg,h702", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts deleted file mode 100644 index 439ae3b537df..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "INet-98V Rev 02"; - compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts deleted file mode 100644 index 3a6c4bd0a44f..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2016 Icenowy Zheng - * - * Based on sun5i-a13-olinuxino.dts, which is - * Copyright 2012 Maxime Ripard - * Copyright 2013 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Lichee Pi One"; - compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "licheepi:red:usr"; - gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "licheepi:green:usr"; - gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led-2 { - label = "licheepi:blue:usr"; - gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; - }; - - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-984 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <984126>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pc_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "csi-1.8v"; -}; - -®_ldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "csi-2.8v"; -}; - -®_usb0_vbus { - gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts deleted file mode 100644 index bfe1075e62cc..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * Copyright 2013 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Olimex A13-Olinuxino Micro"; - compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinom>; - - led { - label = "a13-olinuxino-micro:green:power"; - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinom: led-pin { - pins = "PG9"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts deleted file mode 100644 index fadeae3cd8bb..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A13-Olinuxino"; - compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - led { - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - bridge { - compatible = "dumb-vga-dac"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxino: led-pin { - pins = "PG9"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - status = "okay"; - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; - -®_usb1_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_vga: endpoint@0 { - reg = <0>; - remote-endpoint = <&vga_bridge_in>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts deleted file mode 100644 index d60407772e5d..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2019 Ondrej Jirman - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "PocketBook Touch Lux 3"; - compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - label = "GPIO Keys"; - - key-right { - label = "Right"; - linux,code = ; - gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */ - }; - - key-left { - label = "Left"; - linux,code = ; - gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */ - }; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd-1v8-nor-ctp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_1v8_nor: regulator-nor { - compatible = "regulator-fixed"; - regulator-name = "vdd-nor"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_1v8>; - regulator-always-on; - }; - - reg_1v8_ctp: regulator-ctp { - compatible = "regulator-fixed"; - regulator-name = "vdd-ctp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_1v8>; - }; - - reg_3v3_mmc0: regulator-mmc0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-mmc0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */ - vin-supply = <®_vcc3v3>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; - - /* Touchpanel is connected here. */ -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_3v3_mmc0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pc_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - /* We need this otherwise the LDO3 would overload */ - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; - status = "okay"; - - epd_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "macronix,mx25u4033", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts deleted file mode 100644 index f9fc1c8b60b8..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Q8 A13 Tablet"; - compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; - - panel: panel { - compatible = "bananapi,s070wv20-ct16"; - power-supply = <®_vcc3v3>; - enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts deleted file mode 100644 index be486d28d04f..000000000000 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include - -/ { - model = "Utoo P66"; - compatible = "utoo,p66", "allwinner,sun5i-a13"; - - /* The P66 uses the uart pins as gpios */ - aliases { - /delete-property/serial0; - }; - - chosen { - /delete-property/stdout-path; - }; - - i2c_lcd: i2c { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */ - i2c-gpio,delay-us = <5>; - }; -}; - -&backlight { - /* Note levels of 10 / 20% result in backlight off */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <6>; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; - -®_usb0_vbus { - gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ -}; - -&touchscreen { - compatible = "chipone,icn8318"; - reg = <0x40>; - /* The P66 uses a different EINT then the reference design */ - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - /* The icn8318 binding expects wake-gpios instead of power-gpios */ - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "okay"; -}; - -&uart1 { - /* The P66 uses the uart pins as gpios */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi deleted file mode 100644 index 3325ab07094a..000000000000 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include - -/ { - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a13-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - - }; -}; - -&ccu { - compatible = "allwinner,sun5i-a13-ccu"; -}; - -&cpu0 { - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1400000>, - <912000 1350000>, - <864000 1300000>, - <624000 1200000>, - <576000 1200000>, - <432000 1200000>; - #cooling-cells = <2>; -}; - -&pio { - compatible = "allwinner,sun5i-a13-pinctrl"; -}; diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts deleted file mode 100644 index 5c3562b85a5b..000000000000 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "NextThing C.H.I.P. Pro"; - compatible = "nextthing,chip-pro", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "chip-pro:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc0_pwrseq: mmc0_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ - }; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "disabled"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; - status = "disabled"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc0_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - status = "okay"; - - nand@0 { - reg = <0>; - allwinner,rb = <0>; - nand-ecc-mode = "hw"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>; - status = "disabled"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -/* - * Both LDO3 and LDO4 are used in parallel to power up the - * WiFi/BT chip. - */ -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - regulator-always-on; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - regulator-always-on; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * The CHIP Pro doesn't have a controllable VBUS, nor does it - * have any 5v rail on the board itself. - * - * If one wants to use it as a true OTG port, it should be - * done in the baseboard, and its DT / overlay will add it. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts deleted file mode 100644 index f4fe258ef06d..000000000000 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Mylène Josserand - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "NextThing GR8-EVB"; - compatible = "nextthing,gr8-evb", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 10000 0>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; - power-supply = <®_vcc3v3>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - }; - - sound-analog { - compatible = "simple-audio-card"; - simple-audio-card,name = "gr8-evb-wm8978"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - }; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-980 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <980000>; - }; - - button-1180 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1180000>; - }; - - button-1400 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - - /* MLC Support sucks for now */ - status = "disabled"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&rtp { - allwinner,ts-attached; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * The GR8-EVB has a somewhat interesting design. There's a - * pin supposed to control VBUS, an ID pin, a VBUS detect pin, - * so everything should work just fine. - * - * Except that the pin supposed to control VBUS is not - * connected to any controllable output, neither to the SoC - * through a GPIO or to the PMIC, and it is pulled down, - * meaning that we will never be able to enable VBUS on this - * board. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi deleted file mode 100644 index 98a8fd5e89e8..000000000000 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2016 Mylène Josserand - * - * Mylène Josserand - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include -#include -#include - -/ { - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "nextthing,gr8-ccu"; -}; - -&pio { - compatible = "nextthing,gr8-pinctrl"; - - i2s0_data_pins: i2s0-data-pins { - pins = "PB6", "PB7", "PB8", "PB9"; - function = "i2s0"; - }; - - i2s0_mclk_pin: i2s0-mclk-pin { - pins = "PB5"; - function = "i2s0"; - }; - - pwm1_pins: pwm1-pin { - pins = "PG13"; - function = "pwm1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PB10"; - function = "spdif"; - bias-pull-up; - }; - - uart1_cts_rts_pins: uart1-cts-rts-pins { - pins = "PG5", "PG6"; - function = "uart1"; - }; -}; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts deleted file mode 100644 index 4192c23848c3..000000000000 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-r8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "NextThing C.H.I.P."; - compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart3; - spi0 = &spi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "chip:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc0_pwrseq: mmc0_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */ - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - xio: gpio@38 { - compatible = "nxp,pcf8574a"; - reg = <0x38>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&pio>; - interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmc0_pins { - bias-pull-up; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc0_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "cpuvdd"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "corevdd"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "rtcvdd"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -/* - * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT - * Chip. - * - * If those are not enabled, the SDIO part will not enumerate, and - * since there's no way currently to pass DT infos to an SDIO device, - * we cannot really do better than this ugly hack for now. - */ -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - regulator-always-on; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - regulator-always-on; -}; - -®_ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_usb0_vbus { - vin-supply = <®_vcc5v0>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pe_pins>; - status = "disabled"; -}; - -&tcon0 { - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, - <&uart3_cts_rts_pg_pins>; - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; - - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; -}; diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi deleted file mode 100644 index de35dbcd1191..000000000000 --- a/arch/arm/boot/dts/sun5i-r8.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i-a13.dtsi" - diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi deleted file mode 100644 index 6847f66699ac..000000000000 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include -#include - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ - power-supply = <®_vcc3v0>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - /* - * The gsl1680 is rated at 400KHz and it will not work reliable at - * 100KHz, this has been confirmed on multiple different q8 tablets. - * All other devices on this bus are also rated for 400KHz. - */ - clock-frequency = <400000>; - - touchscreen: touchscreen@40 { - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - /* Tablet dts must provide reg and compatible */ - status = "disabled"; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi deleted file mode 100644 index d7c7b454a11a..000000000000 --- a/arch/arm/boot/dts/sun5i.dtsi +++ /dev/null @@ -1,819 +0,0 @@ -/* - * Copyright 2012-2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; - status = "disabled"; - }; - - framebuffer-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, - <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; - status = "disabled"; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x40000000 0x10000000>; - reusable; - linux,cma-default; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun5i-a13-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun5i-a13-sram-a3-a4", - "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun5i-a13-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun5i-a13-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - mbus: dram-controller@1c01000 { - compatible = "allwinner,sun5i-a13-mbus"; - reg = <0x01c01000 0x1000>; - clocks = <&ccu CLK_MBUS>; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x40000000 0x20000000>; - #interconnect-cells = <1>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tve0: tv-encoder@1c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ccu CLK_AHB_TVE>; - resets = <&ccu RST_TVE>; - status = "disabled"; - - port { - - tve0_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - resets = <&ccu RST_LCD>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD>, - <&ccu CLK_TCON_CH0>, - <&ccu CLK_TCON_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_be0: endpoint { - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun5i-a13-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = <53>; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - interrupts = <32>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ccu CLK_AHB_EHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun5i-a13-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <54>; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - emac_pd_pins: emac-pd-pins { - pins = "PD6", "PD7", "PD10", - "PD11", "PD12", "PD13", "PD14", - "PD15", "PD18", "PD19", "PD20", - "PD21", "PD22", "PD23", "PD24", - "PD25", "PD26", "PD27"; - function = "emac"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB15", "PB16"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB17", "PB18"; - function = "i2c2"; - }; - - ir0_rx_pin: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - lcd_rgb565_pins: lcd-rgb565-pins { - pins = "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc2_4bit_pe_pins: mmc2-4bit-pe-pins { - pins = "PE4", "PE5", "PE6", "PE7", - "PE8", "PE9"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - nand_pins: nand-pins { - pins = "PC0", "PC1", "PC2", - "PC5", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14", - "PC15"; - function = "nand0"; - }; - - nand_cs0_pin: nand-cs0-pin { - pins = "PC4"; - function = "nand0"; - }; - - nand_rb0_pin: nand-rb0-pin { - pins = "PC6"; - function = "nand0"; - }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - spi2_pe_pins: spi2-pe-pins { - pins = "PE1", "PE2", "PE3"; - function = "spi2"; - }; - - spi2_cs0_pe_pin: spi2-cs0-pe-pin { - pins = "PE0"; - function = "spi2"; - }; - - uart1_pe_pins: uart1-pe-pins { - pins = "PE10", "PE11"; - function = "uart1"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG3", "PG4"; - function = "uart1"; - }; - - uart2_pd_pins: uart2-pd-pins { - pins = "PD2", "PD3"; - function = "uart2"; - }; - - uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { - pins = "PD4", "PD5"; - function = "uart2"; - }; - - uart3_pg_pins: uart3-pg-pins { - pins = "PG9", "PG10"; - function = "uart3"; - }; - - uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { - pins = "PG11", "PG12"; - function = "uart3"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>, - <23>, - <24>, - <25>, - <67>, - <68>; - clocks = <&ccu CLK_HOSC>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = <24>; - clocks = <&osc24M>; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = <69>, <70>, <71>, <72>, <73>; - interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <320000000>; - }; - - timer@1c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ccu CLK_AHB_HSTIMER>; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE>; - interconnects = <&mbus 19>; - interconnect-names = "dma-mem"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE>; - interconnects = <&mbus 18>; - interconnect-names = "dma-mem"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - reg = <0>; - - be0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts deleted file mode 100644 index 32d22025ac99..000000000000 --- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2014 Boris Brezillon - * - * Boris Brezillon - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Allwinner A31 APP4 EVB1 Evaluation Board"; - compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts deleted file mode 100644 index 93a15eaaa8cb..000000000000 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "WITS A31 Colombus Evaluation Board"; - compatible = "wits,colombus", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2c_lcd: i2c { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */ - scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */ - i2c-gpio,delay-us = <5>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c0 { - status = "fail"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PA9 */ - }; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts deleted file mode 100644 index 236ebfc06192..000000000000 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Merrii A31 Hummingbird"; - compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; - - aliases { - rtc0 = &pcf8563; - rtc1 = &rtc; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vga-connector { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_dac_out>; - }; - }; - }; - - vga-dac { - compatible = "dumb-vga-dac"; - vdd-supply = <®_vga_3v3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_dac_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_dac_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - reg_vga_3v3: vga_3v3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vga-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ - }; -}; - -&codec { - allwinner,audio-routing = - "Headphone", "HP", - "Speaker", "LINEOUT", - "LINEIN", "Line In", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - /* pull-ups and devices require AXP221 DLDO3 */ - status = "failed"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd0_rgb888_pins>; -}; - -&tcon0_out { - tcon0_out_vga: endpoint@0 { - reg = <0>; - remote-endpoint = <&vga_dac_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts deleted file mode 100644 index 744723d956f0..000000000000 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2015 Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele I7 Quad top set box"; - compatible = "mele,i7", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "i7:blue:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&codec { - allwinner,audio-routing = - "Headphone", "HP"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts deleted file mode 100644 index 7d2eaaf5c33e..000000000000 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele M9 top set box"; - compatible = "mele,m9", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "m9:blue:pwr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ethernet-phy"; -}; - -/* - * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached - * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is - * marked as regulator-always-on. - */ -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-hub"; -}; - -®_usb1_vbus { - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_aldo1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts deleted file mode 100644 index 83611434270c..000000000000 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele A1000G Quad top set box"; - compatible = "mele,a1000g-quad", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "a1000g:blue:pwr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ethernet-phy"; -}; - -/* - * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached - * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is - * marked as regulator-always-on. - */ -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-hub"; -}; - -®_usb1_vbus { - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_aldo1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi deleted file mode 100644 index 5cce4918f84c..000000000000 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ /dev/null @@ -1,1422 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_hdmi: framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, - <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, - <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - - simplefb_lcd: framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, - <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - cpus { - enable-method = "allwinner,sun6i-a31"; - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1200000>, - <864000 1200000>, - <720000 1100000>, - <480000 1000000>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1200000>, - <864000 1200000>, - <720000 1100000>, - <480000 1000000>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1200000>, - <864000 1200000>, - <720000 1100000>, - <480000 1000000>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1200000>, - <864000 1200000>, - <720000 1100000>, - <480000 1000000>; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext_osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c200d0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c200d0 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun6i-a31-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun6i-a31-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DMA>; - resets = <&ccu RST_AHB1_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun6i-a31-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - dmas = <&dma 11>; - resets = <&ccu RST_AHB1_LCD0>, - <&ccu RST_AHB1_LVDS>; - reset-names = "lcd", - "lvds"; - clocks = <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_LCD0_CH0>, - <&ccu CLK_LCD0_CH1>, - <&ccu 15>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1", - "lvds-alt"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon0>; - }; - - tcon0_in_drc1: endpoint@1 { - reg = <1>; - remote-endpoint = <&drc1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun6i-a31-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - dmas = <&dma 12>; - resets = <&ccu RST_AHB1_LCD1>, - <&ccu RST_AHB1_LVDS>; - reset-names = "lcd", "lvds"; - clocks = <&ccu CLK_AHB1_LCD1>, - <&ccu CLK_LCD1_CH0>, - <&ccu CLK_LCD1_CH1>, - <&ccu 15>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1", - "lvds-alt"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon1>; - }; - - tcon1_in_drc1: endpoint@1 { - reg = <1>; - remote-endpoint = <&drc1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC3>, - <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun6i-a31-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_HDMI_DDC>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; - resets = <&ccu RST_AHB1_HDMI>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - dmas = <&dma 13>, <&dma 13>, <&dma 14>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun6i-a31-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_AHB1_OTG>; - resets = <&ccu RST_AHB1_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun6i-a31-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>; - reg-names = "phy_ctrl", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_EHCI0>; - resets = <&ccu RST_AHB1_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_AHB1_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_EHCI1>; - resets = <&ccu RST_AHB1_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1b400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_AHB1_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@1c1c400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_AHB1_OHCI2>; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun6i-a31-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun6i-a31-pinctrl"; - reg = <0x01c20800 0x400>; - interrupt-parent = <&r_intc>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - gmac_gmii_pins: gmac-gmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA15", - "PA16", "PA17", "PA18", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA25", "PA26", "PA27"; - function = "gmac"; - /* - * data lines in GMII mode run at 125MHz and - * might need a higher signal drive strength - */ - drive-strength = <30>; - }; - - gmac_mii_pins: gmac-mii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA8", "PA9", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA26", "PA27"; - function = "gmac"; - }; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA25", "PA26", "PA27"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PH14", "PH15"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH16", "PH17"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PH18", "PH19"; - function = "i2c2"; - }; - - lcd0_rgb888_pins: lcd0-rgb888-pins { - pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD6", "PD7", - "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD14", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_4bit_pins: mmc2-4bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC24"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC24"; - function = "mmc3"; - drive-strength = <40>; - bias-pull-up; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH28"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH20", "PH21"; - function = "uart0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt1: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_APB1_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>, <&dma 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; - resets = <&ccu RST_APB1_DAUDIO0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; - resets = <&ccu RST_APB1_DAUDIO1>; - clock-names = "apb", "mod"; - dmas = <&dma 4>, <&dma 4>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun6i-a31-ts"; - reg = <0x01c25000 0x100>; - interrupts = ; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART0>; - resets = <&ccu RST_APB2_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART1>; - resets = <&ccu RST_APB2_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART2>; - resets = <&ccu RST_APB2_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART3>; - resets = <&ccu RST_APB2_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART4>; - resets = <&ccu RST_APB2_UART4>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART5>; - resets = <&ccu RST_APB2_UART5>; - dmas = <&dma 22>, <&dma 22>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C0>; - resets = <&ccu RST_APB2_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C1>; - resets = <&ccu RST_APB2_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C2>; - resets = <&ccu RST_APB2_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@1c2b800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C3>; - resets = <&ccu RST_APB2_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gmac: ethernet@1c30000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c30000 0x1054>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ccu RST_AHB1_EMAC>; - reset-names = "stmmaceth"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun6i-a31-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_AHB1_SS>; - reset-names = "ahb"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - resets = <&ccu RST_APB1_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timer@1c60000 { - compatible = "allwinner,sun6i-a31-hstimer", - "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_AHB1_HSTIMER>; - resets = <&ccu RST_AHB1_HSTIMER>; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c69000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@1c6a000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6a000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma 25>, <&dma 25>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi3: spi@1c6b000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6b000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma 26>, <&dma 26>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun6i-a31-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, - <&ccu CLK_DRAM_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun6i-a31-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, - <&ccu CLK_DRAM_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun6i-a31-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, - <&ccu CLK_DRAM_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_drc1: endpoint@1 { - reg = <1>; - remote-endpoint = <&drc1_in_be1>; - }; - }; - }; - }; - - drc1: drc@1e50000 { - compatible = "allwinner,sun6i-a31-drc"; - reg = <0x01e50000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, - <&ccu CLK_DRAM_DRC1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_DRC1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - drc1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_drc1>; - }; - }; - - drc1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc1>; - }; - - drc1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_drc1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun6i-a31-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, - <&ccu CLK_DRAM_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@1e70000 { - compatible = "allwinner,sun6i-a31-drc"; - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, - <&ccu CLK_DRAM_DRC0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_DRC0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc0>; - }; - - drc0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_drc0>; - }; - }; - }; - }; - - rtc: rtc@1f00000 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&osc32k>; - clock-output-names = "osc32k"; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - prcm@1f01400 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "allwinner,sun6i-a31-ar100-clk"; - #clock-cells = <0>; - clocks = <&rtc CLK_OSC32K>, <&osc24M>, - <&ccu CLK_PLL_PERIPH>, - <&ccu CLK_PLL_PERIPH>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun6i-a31-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun6i-a31-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_ir", - "apb0_timer", "apb0_p2wi", - "apb0_uart", "apb0_1wire", - "apb0_i2c"; - }; - - ir_clk: ir_clk { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&rtc CLK_OSC32K>, <&osc24M>; - clock-output-names = "ir"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; - - cpucfg@1f01c00 { - compatible = "allwinner,sun6i-a31-cpuconfig"; - reg = <0x01f01c00 0x300>; - }; - - ir: ir@1f02000 { - compatible = "allwinner,sun6i-a31-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; - clock-names = "apb", "ir"; - resets = <&apb0_rst 1>; - interrupts = ; - reg = <0x01f02000 0x40>; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun6i-a31-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - s_ir_rx_pin: s-ir-rx-pin { - pins = "PL4"; - function = "s_ir"; - }; - - s_p2wi_pins: s-p2wi-pins { - pins = "PL0", "PL1"; - function = "s_p2wi"; - }; - }; - - p2wi: i2c@1f03400 { - compatible = "allwinner,sun6i-a31-p2wi"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <100000>; - resets = <&apb0_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&s_p2wi_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts deleted file mode 100644 index a2ef7846e2c8..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sun6i-reference-design-tablet.dtsi" - -/ { - model = "Colorfly E708 Q1 tablet"; - compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; -}; - -®_dldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pg"; -}; - -&simplefb_lcd { - vcc-pg-supply = <®_dldo2>; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts deleted file mode 100644 index 1d15e15011c6..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-cs908.dts +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" - -/ { - model = "CSQ CS908 top set box"; - compatible = "csq,cs908", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts deleted file mode 100644 index c5e2c55cdc63..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sun6i-reference-design-tablet.dtsi" - -/ { - model = "iNet Q972 tablet"; - compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ - touchscreen-size-x = <768>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-200 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-900 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <900000>; - }; - - button-1200 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&ohci1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts deleted file mode 100644 index b32b70ada7fd..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2014 Siarhei Siamashka - * Copyright 2015 Karsten Merker - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "MSI Primo81 tablet"; - compatible = "msi,primo81", "allwinner,sun6i-a31s"; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* rtl8188etv wifi is connected here */ - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - /* pull-ups and device VDDIO use AXP221 DLDO3 */ - status = "failed"; -}; - -&i2c1 { - status = "okay"; - - ctp@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ - touchscreen-swapped-x-y; - }; -}; - -&i2c2 { - status = "okay"; - - accelerometer@1c { - pinctrl-names = "default"; - pinctrl-0 = <&mma8452_int_primo81>; - compatible = "fsl,mma8452"; - reg = <0x1c>; - interrupt-parent = <&pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */ - }; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-158 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&pio { - mma8452_int_primo81: mma8452-int-pin { - pins = "PA9"; - function = "gpio_in"; - bias-pull-up; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -&battery_power_supply { - status = "okay"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo3 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-mipi-bridge"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; - vdd-mipi-bridge-supply = <®_eldo3>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi deleted file mode 100644 index 227ad489731c..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Sinlinx SinA31s Core Board"; - compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -/* eMMC on core board */ -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -/* AXP221s PMIC on core board */ -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -/* UART0 pads available on core board */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts deleted file mode 100644 index 56956352914d..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The SinA31s development board has the SinA31s core board soldered on */ -#include "sun6i-a31s-sina31s-core.dtsi" - -#include - -/ { - model = "Sinlinx SinA31s Development Board"; - compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "sina31s:status:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* USB 2.0 4 port hub IC */ - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-158 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts deleted file mode 100644 index 96554ab4f6d3..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include - -/ { - model = "Sinovoip BPI-M2"; - compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "bpi-m2:blue:usr"; - gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - }; - - led-1 { - label = "bpi-m2:green:usr"; - gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - }; - - led-2 { - label = "bpi-m2:red:usr"; - gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */ - }; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */ - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-gmac"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vdd-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-mac"; -}; - -®_dldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pb"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-csi"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pm-cpus"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&pio { - gpio-line-names = - /* PA */ - "ETXD0", "ETXD1", "ETXD2", "ETXD3", "SDC0-DET", "", "", - "", "ETXCLK", "ETXEN", "EGTXCLK", "ERXD0", "ERXD1", - "ERXD2", "ERXD3", "", "", "", "", "ERXDV", "ERXCK", - "ETXERR", "ERXERR", "ECOL", "ECRS", "ECLKIN", "EMDC", - "EMDIO", "", "", "", "", - - /* PB */ - "CN7-P29", "CN7-P31", "CN7-P33", "CN7-P35", "CN7-P37", - "CN7-P28", "CN7-P27", "CN7-P32", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", - - /* PC */ - "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK", - "WL-SDIO-D0", "WL-SDIO-D2", "WL-SDIO-D2", "WL-SDIO-D3", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "USB-DRV", "", "", "", "", - - /* PD */ - "CN9-P09", "CN9-P11", "CN9-P13", "CN9-P15", "CN9-P17", - "CN9-P19", "CN9-P21", "CN9-P23", "CN9-P25", "CN9-P27", - "CN9-P29", "CN9-P31", "CN9-P33", "CN9-P35", "CN9-P37", - "CN9-P39", "CN9-P40", "CN9-P38", "CN9-P36", "CN9-P34", - "CN9-P32", "CN9-P30", "CN9-P28", "CN9-P26", "CN9-P22", - "CN9-P14", "CN9-P18", "CN9-P16", "", "", "", "", - - /* PE */ - "CN6-P20", "CN6-P24", "CN6-P30", "CN6-P28", "CN7-P08", - "CN7-P10", "CN7-P36", "CN7-P38", "CN6-P17", "CN6-P19", - "CN6-P21", "CN6-P23", "CN6-P25", "CN6-P27", "CN6-P29", - "CN6-P31", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", - - /* PF */ - "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", - "SDC0-D2", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", - - /* PG */ - "CN9-P06", "CN9-P08", "CN9-P20", "CN9-P12", "CN9-P07", - "LED-PWR", "CN7-P13", "CN7-P11", "CN7-P22", "CN7-P15", - "LED-G", "LED-B", "CN7-P26", "CN7-P24", "CN7-P23", - "CN7-P19", "CN7-P21", "HCEC", "CN6-P22", "", "", "", "", - "", "", "", "", "", "", "", "", "", - - /* PH */ - "", "", "", "", "", "", "", "", "", "CN7-P07", - "CN7-P12", "CN7-P16", "CN7-P18", "CN9-P10", "CN6-P16", - "CN6-P14", "CN9-P04", "CN9-P02", "CN7-P05", "CN7-P03", - "CN8-P03", "CN8-P02", "", "", "CN6-P34", "CN6-P32", - "CN6-P26", "CN6-P18", "", "", "", ""; -}; - -&r_pio { - gpio-line-names = - /* PL */ - "PMU-SCK", "PMU-SDA", "VBAT-EN", "", "IR-RX", - "WL-WAKE-HOST", "BT-WAKE_HOST", "BT-ENABLE", - "WL-PMU-EN", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - - /* PM */ - "CN6-P12", "CN6-P35", "CN7-P40", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", ""; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts deleted file mode 100644 index 0b61f5368d44..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2015 Lawrence Yu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Yones TopTech BS1078 v2 Tablet"; - compatible = "yones-toptech,bs1078-v2", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd-usb2"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -/* Voltage source for I2C pullup resistors for I2C Bus 0 */ -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; - usb2_vbus-supply = <®_dc1sw>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi deleted file mode 100644 index 97e2c51d0aea..000000000000 --- a/arch/arm/boot/dts/sun6i-a31s.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The A31s is the same die as the A31 in a different package, this is - * reflected by it having different pinctrl compatible everything else is - * identical. - */ - -#include "sun6i-a31.dtsi" - -&de { - compatible = "allwinner,sun6i-a31s-display-engine"; -}; - -&pio { - compatible = "allwinner,sun6i-a31s-pinctrl"; -}; - -&tcon0 { - compatible = "allwinner,sun6i-a31s-tcon"; -}; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi deleted file mode 100644 index f38d19c6be8c..000000000000 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* Wifi is connected here */ - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; - interrupts = ; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts deleted file mode 100644 index caa935ca4f19..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2016 Luo Yi - * - * Thanks to the original work by Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "Banana Pi BPI-M1-Plus"; - compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "bananapi-m1-plus:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "bananapi-m1-plus:pwr:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&mmc3 { - #address-cells = <1>; - #size-cells = <0>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - wakeup-source; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - /* VBUS on usb host ports are tied to DC5V and therefore always on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts deleted file mode 100644 index 46ecf9db2324..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "LeMaker Banana Pi"; - compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart3; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "bananapi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; - operating-points = - /* kHz uV */ - <960000 1400000>, - <912000 1400000>, - <864000 1350000>, - <720000 1250000>, - <528000 1150000>, - <312000 1100000>, - <144000 1050000>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_vcc3v3>; - vcc-pc-supply = <®_vcc3v3>; - vcc-pe-supply = <®_vcc3v3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-pg-supply = <®_vcc3v3>; - gpio-line-names = - /* PA */ - "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", - "ETXD2", "ETXD1", "ETXD0", - "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", - "ETXEN", "ETXCK", "ECRS", - "ECOL", "ETXERR", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PB */ - "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", - "", "USB0-DRV", "", "", "", "", "", "", - "", "", "", "", "SCL", "SDA", "", "", - "", "", "", "", "", "", "", "", - /* PC */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PD */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PE */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PF */ - "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", - "SD0-D2", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PG */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PH */ - "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", - "", "", "SD0-DET", "", "", "", "", "", - "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", - "LED1", "", "", "", "", "", "", "", - /* PI */ - "", "", "", "IO-GCLK", "", "", "", "", - "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", - "SPI-MISO", "SPI-CE1", "", - "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>, - <&spi0_cs1_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts deleted file mode 100644 index e22f0e8bb17a..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "LeMaker Banana Pro"; - compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "bananapro:blue:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "bananapro:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>, - <&spi0_cs1_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts deleted file mode 100644 index e35e6990c4b2..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Cubietech Cubieboard2"; - compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "cubieboard2:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "cubieboard2:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts deleted file mode 100644 index 52160e368304..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright 2013 Oliver Schinagl - * - * Oliver Schinagl - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Cubietech Cubietruck"; - compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "cubietruck:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "cubietruck:orange:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "cubietruck:white:usr"; - gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "cubietruck:green:usr"; - gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ - clocks = <&ccu CLK_OUT_A>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - /* Pin outputs low power clock for WiFi and BT */ - pinctrl-0 = <&clk_out_a_pin>; - pinctrl-names = "default"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm20702a1"; - clocks = <&ccu CLK_OUT_A>; - clock-names = "lpo"; - device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ - host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ - shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ - max-speed = <1500000>; - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts deleted file mode 100644 index 097e479c2772..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Conley Lee - * Conley Lee - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "HAOYU Electronics Marsboard A20"; - compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; - phy-handle = <&phy0>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&gmac_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - gmac_txerr: gmac-txerr-pin { - pins = "PA17"; - function = "gmac"; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts deleted file mode 100644 index 3def2a330598..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright 2013 Wills Wang - * - * Wills Wang - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Merrii A20 Hummingbird"; - compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_mmc3_vdd: mmc3_vdd { - compatible = "regulator-fixed"; - regulator-name = "mmc3_vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - }; - - reg_gmac_vdd: gmac_vdd { - compatible = "regulator-fixed"; - regulator-name = "gmac_vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_vdd>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ - reset-assert-us = <10000>; - /* wait 1s after reset, otherwise fail to read phy id */ - reset-deassert-us = <1000000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_mmc3_vdd>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pb_pins>, - <&spi2_cs0_pb_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pg_pins>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pi_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts deleted file mode 100644 index b21ddd0ec1c2..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "I12 / Q5 / QT840A A20 tvbox"; - compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "i12_tvbox:red:usr"; - gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "i12_tvbox:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - }; - - reg_vmmc3_io: vmmc3-io { - compatible = "regulator-fixed"; - regulator-name = "vmmc3-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* This controls VCC-PI, must be always on! */ - regulator-always-on; - enable-active-high; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - enable-active-high; - gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts deleted file mode 100644 index 577ead1d02a0..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// Copyright (C) 2023 In-Circuit GmbH - -/dts-v1/; - -#include "sun7i-a20-icnova-a20.dtsi" - -#include -#include - -/ { - model = "In-Circuit ICnova A20 ADB4006"; - compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20", - "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -&ac_power_supply { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi b/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi deleted file mode 100644 index 46616c6bc899..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// Copyright (C) 2023 In-Circuit GmbH - -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts deleted file mode 100644 index 413505f45a81..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2015 Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "ICnova-A20 SWAC"; - compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20", - "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts deleted file mode 100644 index 8ff83016ff5a..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Itead Ibox A20"; - compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_itead_core>; - - led-0 { - label = "itead_core:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-1 { - label = "itead_core:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - axp209: pmic@34 { - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&pio { - led_pins_itead_core: led-pins { - pins = "PH20","PH21"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts deleted file mode 100644 index 97518afe4658..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2015 Jelle de Jong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Lamobo R1"; - compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart3; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "lamobo_r1:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - switch: ethernet-switch@1e { - compatible = "brcm,bcm53125"; - reg = <30>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port0: port@0 { - reg = <0>; - label = "lan2"; - }; - - port1: port@1 { - reg = <1>; - label = "lan3"; - }; - - port2: port@2 { - reg = <2>; - label = "lan4"; - }; - - port3: port@3 { - reg = <3>; - label = "wan"; - }; - - port4: port@4 { - reg = <4>; - label = "lan1"; - }; - - port8: port@8 { - reg = <8>; - label = "cpu"; - ethernet = <&gmac>; - phy-mode = "rgmii-txid"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>, - <&spi0_cs1_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts deleted file mode 100644 index da5a2eea4ce3..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2020 Linutronix GmbH - * Author: Benedikt Spranger - */ - -/dts-v1/; -#include "sun7i-a20-lamobo-r1.dts" - -/ { - model = "Lamobo R1"; - compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20"; - - leds { - led-opto1 { - label = "lamobo_r1:opto:powerswitch"; - gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>; - }; - - led-opto2 { - label = "lamobo_r1:opto:relay"; - gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - status = "okay"; - }; - - atecc508a@60 { - compatible = "atmel,atecc508a"; - reg = <0x60>; - }; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts deleted file mode 100644 index f161d5238860..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Mele M3"; - compatible = "mele,m3", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "m3:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts deleted file mode 100644 index 1491c603f661..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 2015 Marcus Cooper - * - * Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "mk808c"; - compatible = "allwinner,mk808c", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts deleted file mode 100644 index 20bf09b2226c..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board - * - * Copyright (C) 2018 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -/dts-v1/; -#include "sun7i-a20-olimex-som-evb.dts" - -/ { - - model = "Olimex A20-Olimex-SOM-EVB-eMMC"; - compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts deleted file mode 100644 index f05ee32bc9cb..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * Copyright 2015 - Karsten Merker - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A20-Olimex-SOM-EVB"; - compatible = "olimex,a20-olimex-som-evb", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "a20-olimex-som-evb:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&codec { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-980 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <980000>; - }; - - button-1180 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1180000>; - }; - - button-1400 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1400000>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olimex_som_evb: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pi_pins>, - <&spi1_cs0_pi_pin>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pc_pins>, - <&spi2_cs0_pc_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pi_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts deleted file mode 100644 index a59755a2e7a9..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for A20-SOM204-EVB-eMMC Board - * - * Copyright (C) 2018 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -/dts-v1/; -#include "sun7i-a20-olimex-som204-evb.dts" - -/ { - model = "Olimex A20-SOM204-EVB-eMMC"; - compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts deleted file mode 100644 index 54af6c18075b..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for A20-SOM204-EVB Board - * - * Copyright (C) 2018 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - - -#include -#include -#include - -/ { - model = "Olimex A20-SOM204-EVB"; - compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - serial2 = &uart7; - spi0 = &spi1; - spi1 = &spi2; - ethernet1 = &rtl8723bs; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "a20-som204-evb:green:stat"; - gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-1 { - label = "a20-som204-evb:green:led1"; - gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-2 { - label = "a20-som204-evb:yellow:led2"; - gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - rtl_pwrseq: rtl_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can_ph_pins>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy3>; - phy-mode = "rgmii"; - phy-supply = <®_vcc3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* Exposed to UEXT1 */ -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* Exposed to UEXT2 */ -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy3: ethernet-phy@3 { - reg = <3>; - reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ - reset-assert-us = <10000>; - /* wait 1s after reset, otherwise fail to read phy id */ - reset-deassert-us = <1000000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&rtl_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - uart3_rts_pin: uart3-rts-pin { - pins = "PG8"; - function = "uart3"; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pg"; -}; - -®_usb0_vbus { - gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -/* Exposed to UEXT1 */ -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pi_pins>, - <&spi1_cs0_pi_pin>; - status = "okay"; -}; - -/* Exposed to UEXT2 */ -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pc_pins>, - <&spi2_cs0_pc_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* Used for RTL8723BS bluetooth */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>; - status = "okay"; -}; - -/* Exposed to UEXT1 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pg_pins>; - status = "okay"; -}; - -/* Exposed to UEXT2 */ -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts deleted file mode 100644 index 033cab3443f8..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -#include "sun7i-a20-olinuxino-lime.dts" - -/ { - model = "Olimex A20-OLinuXino-LIME-eMMC"; - compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&mmc2_pwrseq>; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts deleted file mode 100644 index 92938d022295..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This is based on sun4i-a10-olinuxino-lime.dts - * - * Copyright 2014 - Hans de Goede - * Copyright (c) 2014 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A20-OLinuXino-LIME"; - compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - led { - label = "a20-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinolime: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts deleted file mode 100644 index decb014a382b..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts +++ /dev/null @@ -1,69 +0,0 @@ - /* - * Copyright 2015 - Ultimaker B.V. - * Author Olliver Schinagl - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun7i-a20-olinuxino-lime2.dts" - -/ { - model = "Olimex A20-OLinuXino-LIME2-eMMC"; - compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&mmc2_pwrseq>; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts deleted file mode 100644 index ecb91fb899ff..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright 2014 - Iain Paton - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A20-OLinuXino-LIME2"; - compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - led { - label = "a20-olinuxino-lime2:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_axp_ipsout: axp_ipsout { - compatible = "regulator-fixed"; - regulator-name = "axp-ipsout"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_vcc3v3>; - vcc-pc-supply = <®_vcc3v3>; - vcc-pe-supply = <®_ldo3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-pg-supply = <®_ldo4>; - - led_pins_olinuxinolime: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi0"; - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -®_ldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi1"; -}; - -®_usb0_vbus { - gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts deleted file mode 100644 index 2337b44a88aa..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts +++ /dev/null @@ -1,68 +0,0 @@ - /* - * Copyright 2017 Olimex Ltd. - * Stefan Mavrodiev - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun7i-a20-olinuxino-micro.dts" - -/ { - model = "Olimex A20-OLinuXino-MICRO-eMMC"; - compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&mmc2_pwrseq>; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts deleted file mode 100644 index a1b89b2a2999..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A20-Olinuxino Micro"; - compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart6; - serial2 = &uart7; - spi0 = &spi1; - spi1 = &spi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - led { - label = "a20-olinuxino-micro:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - - button-1184 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1184678>; - }; - - button-1398 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1398804>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - gmac_txerr: gmac-txerr-pin { - pins = "PA17"; - function = "gmac"; - }; - - led_pins_olinuxino: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ahci_5v { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pi_pins>, - <&spi1_cs0_pi_pin>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pc_pins>, - <&spi2_cs0_pc_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pi_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts deleted file mode 100644 index 84efa01e7cba..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Orange Pi Mini"; - compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "orangepi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - }; - - led-1 { - label = "orangepi:blue:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts deleted file mode 100644 index 5d77f1d9818f..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Orange Pi"; - compatible = "xunlong,orangepi", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "orangepi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts deleted file mode 100644 index e40ecb48d726..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright 2015-2020 Adam Sampson - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "LinkSprite pcDuino3 Nano"; - compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-3 { - label = "pcduino3-nano:green:usr1"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ - }; - - led-4 { - label = "pcduino3-nano:green:usr2"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -/* A single regulator (U24) powers both USB host ports. */ -®_usb1_vbus { - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts deleted file mode 100644 index 928b86a95f34..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "LinkSprite pcDuino3"; - compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "pcduino3:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "pcduino3:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-back { - label = "Key Back"; - linux,code = ; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - - key-home { - label = "Key Home"; - linux,code = ; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - - key-menu { - label = "Key Menu"; - linux,code = ; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts deleted file mode 100644 index fef02fcbbdf8..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "Wexler TAB7200"; - compatible = "wexler,tab7200", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - gt911: touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */ - reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */ - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-571 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <571428>; - }; - - button-761 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <761904>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts deleted file mode 100644 index 3bfae98f3cc3..000000000000 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2015 Jelle de Jong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Wits Pro A20 DKT"; - compatible = "wits,pro-a20-dkt", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -#include "axp209.dtsi" - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi deleted file mode 100644 index 5574299685ab..000000000000 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ /dev/null @@ -1,1710 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, - <&ccu CLK_HDMI>; - status = "disabled"; - }; - - framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, - <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, - <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, - <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <960000 1400000>, - <912000 1400000>, - <864000 1300000>, - <720000 1200000>, - <528000 1100000>, - <312000 1000000>, - <144000 1000000>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <960000 1400000>, - <912000 1400000>, - <864000 1300000>, - <720000 1200000>, - <528000 1100000>, - <312000 1000000>, - <144000 1000000>; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x40000000 0x10000000>; - reusable; - linux,cma-default; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - }; - - - de: display-engine { - compatible = "allwinner,sun7i-a20-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun7i-a20-system-control", - "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun7i-a20-sram-a3-a4", - "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun7i-a20-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun7i-a20-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - nmi_intc: interrupt-controller@1c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupts = ; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <4>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - }; - - csi0: csi@1c09000 { - compatible = "allwinner,sun7i-a20-csi0"; - reg = <0x01c09000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; - clock-names = "bus", "isp", "ram"; - resets = <&ccu RST_CSI0>; - status = "disabled"; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun7i-a20-tcon0", - "allwinner,sun7i-a20-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>; - reset-names = "lcd", "lvds"; - clocks = <&ccu CLK_AHB_LCD0>, - <&ccu CLK_TCON0_CH0>, - <&ccu CLK_TCON0_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - - tcon0_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun7i-a20-tcon1", - "allwinner,sun7i-a20-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - resets = <&ccu RST_TCON1>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD1>, - <&ccu CLK_TCON1_CH0>, - <&ccu CLK_TCON1_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 15>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon1>; - }; - - tcon1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun7i-a20-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB_MMC3>, - <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun7i-a20-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&ccu CLK_USB_PHY>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = ; - clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun7i-a20-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun7i-a20-hdmi", - "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; - status = "disabled"; - }; - - ehci1: usb@1c1c000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1c400 { - compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - csi1: csi@1c1d000 { - compatible = "allwinner,sun7i-a20-csi1", - "allwinner,sun4i-a10-csi1"; - reg = <0x01c1d000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; - clock-names = "bus", "ram"; - resets = <&ccu RST_CSI1>; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun7i-a20-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun7i-a20-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - /omit-if-no-ref/ - can_pa_pins: can-pa-pins { - pins = "PA16", "PA17"; - function = "can"; - }; - - /omit-if-no-ref/ - can_ph_pins: can-ph-pins { - pins = "PH20", "PH21"; - function = "can"; - }; - - /omit-if-no-ref/ - clk_out_a_pin: clk-out-a-pin { - pins = "PI12"; - function = "clk_out_a"; - }; - - /omit-if-no-ref/ - clk_out_b_pin: clk-out-b-pin { - pins = "PI13"; - function = "clk_out_b"; - }; - - /omit-if-no-ref/ - csi0_8bits_pins: csi-8bits-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", - "PE6", "PE7", "PE8", "PE9", "PE10", - "PE11"; - function = "csi0"; - }; - - /omit-if-no-ref/ - csi0_clk_pin: csi-clk-pin { - pins = "PE1"; - function = "csi0"; - }; - - /omit-if-no-ref/ - csi1_8bits_pg_pins: csi1-8bits-pg-pins { - pins = "PG0", "PG2", "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8", "PG9", "PG10", - "PG11"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_24bits_ph_pins: csi1-24bits-ph-pins { - pins = "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH8", "PH9", - "PH10", "PH11", "PH12", "PH13", "PH14", - "PH15", "PH16", "PH17", "PH18", "PH19", - "PH20", "PH21", "PH22", "PH23", "PH24", - "PH25", "PH26", "PH27"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_clk_pg_pin: csi1-clk-pg-pin { - pins = "PG1"; - function = "csi1"; - }; - - /omit-if-no-ref/ - emac_pa_pins: emac-pa-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - /omit-if-no-ref/ - emac_ph_pins: emac-ph-pins { - pins = "PH8", "PH9", "PH10", "PH11", - "PH14", "PH15", "PH16", "PH17", - "PH18", "PH19", "PH20", "PH21", - "PH22", "PH23", "PH24", "PH25", - "PH26"; - function = "emac"; - }; - - /omit-if-no-ref/ - gmac_mii_pins: gmac-mii-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "gmac"; - }; - - /omit-if-no-ref/ - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA10", - "PA11", "PA12", "PA13", - "PA15", "PA16"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - /omit-if-no-ref/ - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - /omit-if-no-ref/ - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - /omit-if-no-ref/ - i2c3_pins: i2c3-pins { - pins = "PI0", "PI1"; - function = "i2c3"; - }; - - /omit-if-no-ref/ - ir0_rx_pin: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - /omit-if-no-ref/ - ir0_tx_pin: ir0-tx-pin { - pins = "PB3"; - function = "ir0"; - }; - - /omit-if-no-ref/ - ir1_rx_pin: ir1-rx-pin { - pins = "PB23"; - function = "ir1"; - }; - - /omit-if-no-ref/ - ir1_tx_pin: ir1-tx-pin { - pins = "PB22"; - function = "ir1"; - }; - - /omit-if-no-ref/ - lcd_lvds0_pins: lcd-lvds0-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD6", "PD7", "PD8", "PD9"; - function = "lvds0"; - }; - - /omit-if-no-ref/ - lcd_lvds1_pins: lcd-lvds1-pins { - pins = "PD10", "PD11", "PD12", "PD13", "PD14", - "PD15", "PD16", "PD17", "PD18", "PD19"; - function = "lvds1"; - }; - - /omit-if-no-ref/ - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc2_pins: mmc2-pins { - pins = "PC6", "PC7", "PC8", - "PC9", "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc3_pins: mmc3-pins { - pins = "PI4", "PI5", "PI6", - "PI7", "PI8", "PI9"; - function = "mmc3"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - ps2_0_pins: ps2-0-pins { - pins = "PI20", "PI21"; - function = "ps2"; - }; - - /omit-if-no-ref/ - ps2_1_ph_pins: ps2-1-ph-pins { - pins = "PH12", "PH13"; - function = "ps2"; - }; - - /omit-if-no-ref/ - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - /omit-if-no-ref/ - pwm1_pin: pwm1-pin { - pins = "PI3"; - function = "pwm"; - }; - - /omit-if-no-ref/ - spdif_tx_pin: spdif-tx-pin { - pins = "PB13"; - function = "spdif"; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pi_pins: spi0-pi-pins { - pins = "PI11", "PI12", "PI13"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pi_pin: spi0-cs0-pi-pin { - pins = "PI10"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs1_pi_pin: spi0-cs1-pi-pin { - pins = "PI14"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pi_pins: spi1-pi-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pi_pin: spi1-cs0-pi-pin { - pins = "PI16"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi2_pb_pins: spi2-pb-pins { - pins = "PB15", "PB16", "PB17"; - function = "spi2"; - }; - - /omit-if-no-ref/ - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB14"; - function = "spi2"; - }; - - /omit-if-no-ref/ - spi2_pc_pins: spi2-pc-pins { - pins = "PC20", "PC21", "PC22"; - function = "spi2"; - }; - - /omit-if-no-ref/ - spi2_cs0_pc_pin: spi2-cs0-pc-pin { - pins = "PC19"; - function = "spi2"; - }; - - /omit-if-no-ref/ - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pa_pins: uart1-pa-pins { - pins = "PA10", "PA11"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { - pins = "PA12", "PA13"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart2_pa_pins: uart2-pa-pins { - pins = "PA2", "PA3"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { - pins = "PA0", "PA1"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_pi_pins: uart2-pi-pins { - pins = "PI18", "PI19"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { - pins = "PI16", "PI17"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart3_pg_pins: uart3-pg-pins { - pins = "PG6", "PG7"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { - pins = "PG8", "PG9"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_ph_pins: uart3-ph-pins { - pins = "PH0", "PH1"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { - pins = "PH2", "PH3"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart4_pg_pins: uart4-pg-pins { - pins = "PG10", "PG11"; - function = "uart4"; - }; - - /omit-if-no-ref/ - uart4_ph_pins: uart4-ph-pins { - pins = "PH4", "PH5"; - function = "uart4"; - }; - - /omit-if-no-ref/ - uart5_ph_pins: uart5-ph-pins { - pins = "PH6", "PH7"; - function = "uart5"; - }; - - /omit-if-no-ref/ - uart5_pi_pins: uart5-pi-pins { - pins = "PI10", "PI11"; - function = "uart5"; - }; - - /omit-if-no-ref/ - uart6_pa_pins: uart6-pa-pins { - pins = "PA12", "PA13"; - function = "uart6"; - }; - - /omit-if-no-ref/ - uart6_pi_pins: uart6-pi-pins { - pins = "PI12", "PI13"; - function = "uart6"; - }; - - /omit-if-no-ref/ - uart7_pa_pins: uart7-pa-pins { - pins = "PA14", "PA15"; - function = "uart7"; - }; - - /omit-if-no-ref/ - uart7_pi_pins: uart7-pi-pins { - pins = "PI20", "PI21"; - function = "uart7"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = , - , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = ; - clocks = <&osc24M>; - }; - - rtc: rtc@1c20d00 { - compatible = "allwinner,sun7i-a20-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = ; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; - clock-names = "apb", "ir"; - interrupts = ; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@1c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; - clock-names = "apb", "ir"; - interrupts = ; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - i2s1: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 4>, - <&dma SUN4I_DMA_NORMAL 4>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun7i-a20-codec"; - reg = <0x01c22c00 0x40>; - interrupts = ; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200>; - }; - - i2s2: i2s@1c24400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c24400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 6>, - <&dma SUN4I_DMA_NORMAL 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = ; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART7>; - status = "disabled"; - }; - - ps20: ps2@1c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_PS20>; - status = "disabled"; - }; - - ps21: ps2@1c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_PS21>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@1c2b800 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@1c2bc00 { - compatible = "allwinner,sun7i-a20-can", - "allwinner,sun4i-a10-can"; - reg = <0x01c2bc00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_CAN>; - status = "disabled"; - }; - - i2c4: i2c@1c2c000 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2c000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - gmac: ethernet@1c50000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c50000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - gmac_mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - hstimer@1c60000 { - compatible = "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_AHB_HSTIMER>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun7i-a20-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_DRAM_DE_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun7i-a20-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, - <&ccu CLK_DRAM_DE_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun7i-a20-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, - <&ccu CLK_DRAM_DE_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be1>; - }; - - be1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun7i-a20-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DRAM_DE_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - - be0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi deleted file mode 100644 index cd4bf60dbb3c..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ /dev/null @@ -1,855 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_lcd: framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, - <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; - status = "disabled"; - }; - }; - - de: display-engine { - /* compatible gets set in SoC specific dtsi file */ - allwinner,pipelines = <&fe0>; - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - cpus { - enable-method = "allwinner,sun8i-a23"; - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext-osc32k"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun8i-a23-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0x80000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun8i-a23-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-a23-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun8i-a23-nand-controller"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_NAND>; - reset-names = "ahb"; - dmas = <&dma 5>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c0c000 0x1000>; - interrupts = ; - dmas = <&dma 12>; - clocks = <&ccu CLK_BUS_LCD>, - <&ccu CLK_LCD_CH0>, - <&ccu 13>; - clock-names = "ahb", - "tcon-ch0", - "lvds-alt"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_LCD>, - <&ccu RST_BUS_LVDS>; - reset-names = "lcd", - "lvds"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_drc0: endpoint { - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c19000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - /* - * compatible and address regions get set in - * SoC specific dtsi file - */ - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI>; - resets = <&ccu RST_BUS_EHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; - resets = <&ccu RST_BUS_OHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c20800 0x400>; - interrupt-parent = <&r_intc>; - /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - i2c0_pins: i2c0-pins { - pins = "PH2", "PH3"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH4", "PH5"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PE12", "PE13"; - function = "i2c2"; - }; - - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pg_pins: mmc1-pg-pins { - pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - nand_pins: nand-pins { - pins = "PC0", "PC1", "PC2", "PC5", - "PC8", "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", "PC15"; - function = "nand0"; - }; - - nand_cs0_pin: nand-cs0-pin { - pins = "PC4"; - function = "nand0"; - bias-pull-up; - }; - - nand_cs1_pin: nand-cs1-pin { - pins = "PC3"; - function = "nand0"; - bias-pull-up; - }; - - nand_rb0_pin: nand-rb0-pin { - pins = "PC6"; - function = "nand0"; - bias-pull-up; - }; - - nand_rb1_pin: nand-rb1-pin { - pins = "PC7"; - function = "nand0"; - bias-pull-up; - }; - - pwm0_pin: pwm0-pin { - pins = "PH0"; - function = "pwm0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-a23-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c21400 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun8i-a23-mali", - "allwinner,sun7i-a20-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - #cooling-cells = <2>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - fe0: display-frontend@1e00000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_FE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01e60000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_BE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - reg = <0>; - - be0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@1e70000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, - <&ccu CLK_DRAM_DRC>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_DRC>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - reg = <1>; - - drc0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; - - rtc: rtc@1f00000 { - compatible = "allwinner,sun8i-a23-rtc"; - reg = <0x01f00000 0x400>; - interrupt-parent = <&r_intc>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out"; - clocks = <&ext_osc32k>; - #clock-cells = <1>; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - prcm@1f01400 { - compatible = "allwinner,sun8i-a23-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun8i-a23-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun8i-a23-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_timer", - "apb0_rsb", "apb0_uart", - "apb0_i2c"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - codec_analog: codec-analog { - compatible = "allwinner,sun8i-a23-codec-analog"; - }; - }; - - cpucfg@1f01c00 { - compatible = "allwinner,sun8i-a23-cpuconfig"; - reg = <0x01f01c00 0x300>; - }; - - r_uart: serial@1f02800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01f02800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb0_gates 4>; - resets = <&apb0_rst 4>; - status = "disabled"; - }; - - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun8i-a23-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01f02400 0x400>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pins>; - clocks = <&apb0_gates 6>; - resets = <&apb0_rst 6>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-a23-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - bias-pull-up; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - - r_uart_pins_a: r-uart-pins { - pins = "PL2", "PL3"; - function = "s_uart"; - }; - }; - - r_rsb: rsb@1f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <3000000>; - resets = <&apb0_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts deleted file mode 100644 index 53fb1be0401a..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-evb.dts +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Allwinner A23 Evaluation Board"; - compatible = "allwinner,sun8i-a23-evb", "allwinner,sun8i-a23"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &r_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -/* - * The RX line has a non-populated resistance. In order to use it, you - * need to solder R207 on the back of the board in order to close the - * line and get a working UART. - */ -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts deleted file mode 100644 index bcbc9b0758f9..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Allwinner GT90H Dual Core Tablet (v4)"; - compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3675"; - firmware-name = "gsl3675-gt90h.fw"; - touchscreen-size-x = <1792>; - touchscreen-size-y = <1024>; - status = "okay"; -}; - -&lradc { - button-600 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts deleted file mode 100644 index d4405752a414..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "INet-86DZ Rev 01"; - compatible = "primux,inet86dz", "allwinner,sun8i-a23"; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl1680"; - firmware-name = "gsl1680-inet86dz.fw"; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts deleted file mode 120000 index c2f22fc33811..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts deleted file mode 120000 index c2f22fc33811..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts deleted file mode 100644 index d5f6aebd7216..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Polaroid MID2407PXE03 tablet"; - compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; - - aliases { - ethernet0 = &esp8089; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&i2c1 { - mma7660: accelerometer@4c { - reg = <0x4c>; - compatible = "fsl,mma7660"; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl1680"; - firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - touchscreen-inverted-x; - touchscreen-inverted-y; - vddio-supply = <®_ldo_io1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts deleted file mode 100644 index 9f9232a2fefb..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Polaroid MID2809PXE04 tablet"; - compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; - - aliases { - ethernet0 = &esp8089; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3670"; - firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; - touchscreen-size-x = <1660>; - touchscreen-size-y = <890>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts deleted file mode 100644 index 51097c77a152..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi deleted file mode 100644 index a5e884a8b2ae..000000000000 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-a23-a33.dtsi" - -/ { - soc { - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a23-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - }; -}; - -&be0 { - compatible = "allwinner,sun8i-a23-display-backend"; -}; - -&ccu { - compatible = "allwinner,sun8i-a23-ccu"; -}; - -&de { - compatible = "allwinner,sun8i-a23-display-engine"; -}; - -&drc0 { - compatible = "allwinner,sun8i-a23-drc"; -}; - -&fe0 { - compatible = "allwinner,sun8i-a23-display-frontend"; -}; - -&pio { - compatible = "allwinner,sun8i-a23-pinctrl"; - interrupts = , - , - ; -}; - -&tcon0 { - compatible = "allwinner,sun8i-a23-tcon"; -}; - -&usb_otg { - compatible = "allwinner,sun6i-a31-musb"; -}; - -&usbphy { - compatible = "allwinner,sun8i-a23-usb-phy"; - reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; - reg-names = "phy_ctrl", "pmu1"; -}; diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts deleted file mode 120000 index 4519fd791a8f..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts deleted file mode 100644 index 2dfdd0a3151e..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Allwinner GA10H Quad Core Tablet (v1.1)"; - compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; - - aliases { - /* Make u-boot set mac-address for rtl8703as (no eeprom) */ - ethernet0 = &rtl8703as; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3675"; - firmware-name = "gsl3675-ga10h.fw"; - touchscreen-size-x = <1630>; - touchscreen-size-y = <990>; - touchscreen-inverted-y; - status = "okay"; -}; - -&lradc { - button-600 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8703as: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts deleted file mode 100644 index 065cb620aa99..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * Copyright 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "INet-D978 Rev 02"; - compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart1; - }; - - chosen { - /* Delete debug UART as serial0 is the UART for bluetooth */ - /delete-property/stdout-path; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_d978>; - - led { - label = "d978:blue:home"; - gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - }; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: sdio_wifi@1 { - reg = <1>; - }; -}; - -&r_pio { - led_pin_d978: led-pin { - pins = "PL5"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -&r_uart { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, - <&uart1_cts_rts_pg_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts deleted file mode 120000 index 4519fd791a8f..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts deleted file mode 100644 index 6fee8f133508..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright 2016 - Stefan Mavrodiev - * Olimex LTD. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" - -#include -#include - -/ { - model = "Olimex A33-OLinuXino"; - compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "a33-olinuxino:green:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&sound { - /* Board level jack widgets */ - simple-audio-card,widgets = "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - /* Board level routing. First 2 routes copied from SoC level */ - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "HP", "HPCOM", - "Headphone Jack", "HP", - "MIC1", "Microphone Jack", - "Microphone Jack", "MBIAS"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts deleted file mode 100644 index 9c5750c25613..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts deleted file mode 100644 index 0c82ff3c7cb4..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Sinlinx SinA33"; - compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - panel { - compatible = "netron-dy,e231732"; - power-supply = <®_vcc3v3>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&cpu0_opp_table { - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; -}; - -&de { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_dcdc1>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191011>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <391304>; - }; - - button-600 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&sound { - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ -}; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi deleted file mode 100644 index 30fdd2703b1f..000000000000 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-a23-a33.dtsi" -#include - -/ { - cpu0_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-240000000 { - opp-hz = /bits/ 64 <240000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - cpus { - cpu@0 { - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&ths>; - }; - - mali_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-144000000 { - opp-hz = /bits/ 64 <144000000>; - }; - - opp-240000000 { - opp-hz = /bits/ 64 <240000000>; - }; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun8i-a33-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&link_codec>; - simple-audio-card,bitclock-master = <&link_codec>; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&dai>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&codec 0>; - }; - }; - - soc { - video-codec@1c0e000 { - compatible = "allwinner,sun8i-a33-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun8i-a33-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SS>; - reset-names = "ahb"; - }; - - dai: dai@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-i2s"; - reg = <0x01c22c00 0x200>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - codec: codec@1c22e00 { - #sound-dai-cells = <1>; - compatible = "allwinner,sun8i-a33-codec"; - reg = <0x01c22e00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "bus", "mod"; - status = "disabled"; - }; - - ths: ths@1c25000 { - compatible = "allwinner,sun8i-a33-ths"; - reg = <0x01c25000 0x100>; - #thermal-sensor-cells = <0>; - #io-channel-cells = <0>; - }; - - dsi: dsi@1ca0000 { - compatible = "allwinner,sun6i-a31-mipi-dsi"; - reg = <0x01ca0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_SCLK>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - phys = <&dphy>; - phy-names = "dphy"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - port { - dsi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_dsi>; - }; - }; - }; - - dphy: d-phy@1ca1000 { - compatible = "allwinner,sun6i-a31-mipi-dphy"; - reg = <0x01ca1000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - status = "disabled"; - #phy-cells = <0>; - }; - }; - - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&ths>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&gpu_alert0>; - cooling-device = <&mali 1 THERMAL_NO_LIMIT>; - }; - - map3 { - trip = <&gpu_alert1>; - cooling-device = <&mali 2 THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu_alert0: gpu_alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: cpu_alert1 { - /* milliCelsius */ - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - gpu_alert1: gpu_alert1 { - /* milliCelsius */ - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&be0 { - compatible = "allwinner,sun8i-a33-display-backend"; - /* A33 has an extra "SAT" module packed inside the display backend */ - reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; - reg-names = "be", "sat"; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; - clock-names = "ahb", "mod", - "ram", "sat"; - resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; - reset-names = "be", "sat"; -}; - -&ccu { - compatible = "allwinner,sun8i-a33-ccu"; -}; - -&de { - compatible = "allwinner,sun8i-a33-display-engine"; -}; - -&drc0 { - compatible = "allwinner,sun8i-a33-drc"; -}; - -&fe0 { - compatible = "allwinner,sun8i-a33-display-frontend"; -}; - -&mali { - operating-points-v2 = <&mali_opp_table>; -}; - -&pio { - compatible = "allwinner,sun8i-a33-pinctrl"; - interrupts = , - ; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB0", "PB1"; - function = "uart0"; - }; - -}; - -&tcon0 { - compatible = "allwinner,sun8i-a33-tcon"; -}; - -&tcon0_out { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon0>; - }; -}; - -&usb_otg { - compatible = "allwinner,sun8i-a33-musb"; -}; - -&usbphy { - compatible = "allwinner,sun8i-a33-usb-phy"; - reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; - reg-names = "phy_ctrl", "pmu1"; -}; diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts deleted file mode 100644 index c31c97d16024..000000000000 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include - -/ { - model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; - compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_usb0_vbus: reg-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - }; - - reg_usb1_vbus: reg-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp818", "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - swin-supply = <®_dcdc1>; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp81x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dram-pll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-sys"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo4 { - /* - * The PHY requires 20ms after all voltages are applied until core - * logic is ready and 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ephy"; -}; - -®_fldo1 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd12-hsic"; -}; - -®_fldo2 { - /* - * Despite the embedded CPUs core not being used in any way, - * this must remain on or the system will hang. - */ - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -®_sw { - regulator-name = "vcc-wifi"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts deleted file mode 100644 index 8d56b103f063..000000000000 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ /dev/null @@ -1,422 +0,0 @@ -/* - * Copyright 2017 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include - -/ { - model = "Banana Pi BPI-M3"; - compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "bananapi-m3:blue:usr"; - gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "bananapi-m3:green:usr"; - gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb1_vbus: reg-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* The WiFi low power clock must be 32768 Hz */ - assigned-clocks = <&ac100_rtc 1>; - assigned-clock-rates = <32768>; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; - - /* - * Power supply for the SATA disk, behind a USB-SATA bridge. - * Since it is a USB device, there is no consumer in the DT, so we - * have to keep this always on. - */ - regulator-sata-disk-pwr { - compatible = "regulator-fixed"; - regulator-name = "sata-disk-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - enable-active-high; - gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ - status = "okay"; - - /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_sw>; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-id"; - allwinner,rx-delay-ps = <700>; - allwinner,tx-delay-ps = <700>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&r_cir { - clock-frequency = <3000000>; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - fldoin-supply = <®_dcdc5>; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp81x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dram-pll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - /* schematics says 3.1V but FEX file says 3.3V */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - /* - * This powers both the WiFi/BT module's main power, I/O supply, - * and external pull-ups on all the data lines. It should be set - * to the same voltage as the I/O supply (DCDC1 in this case) to - * avoid any leakage or mismatch. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pd"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_fldo1 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd12-hsic"; -}; - -®_fldo2 { - /* - * Despite the embedded CPUs core not being used in any way, - * this must remain on or the system will hang. - */ - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -®_sw { - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-ephy"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&ac100_rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo1>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts deleted file mode 100644 index 870993393fc2..000000000000 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include - -/ { - model = "Cubietech Cubietruck Plus"; - compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "cubietruck-plus:blue:usr"; - gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ - }; - - led-1 { - label = "cubietruck-plus:orange:usr"; - gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ - }; - - led-2 { - label = "cubietruck-plus:white:usr"; - gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ - }; - - led-3 { - label = "cubietruck-plus:green:usr"; - gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ - }; - }; - - usb-hub { - /* I2C is not connected */ - compatible = "smsc,usb3503"; - initial-mode = <1>; /* initialize in HUB mode */ - disabled-ports = <1>; - intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ - connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - refclk-frequency = <19200000>; - }; - - reg_usb1_vbus: reg-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ - }; - - reg_usb2_vbus: reg-usb2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb2-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* The WiFi low power clock must be 32768 Hz */ - assigned-clocks = <&ac100_rtc 1>; - assigned-clock-rates = <32768>; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* GL830 USB-to-SATA bridge here */ - status = "okay"; -}; - -&ehci1 { - /* USB3503 HSIC USB 2.0 hub here */ - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_dldo4>; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_sw>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp818", "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp81x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dram-pll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - /* - * The schematics say this should be 3.3V, but the FEX file says - * it should be 3V. The latter makes sense, as the WiFi module's - * I/O is indirectly powered from DCDC1, through SW. It is rated - * at 2.98V maximum. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-sys"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "dp-pwr"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "ephy-io"; -}; - -®_dldo4 { - /* - * The PHY requires 20ms after all voltages are applied until core - * logic is ready and 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ephy"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "dp-bridge-1"; -}; - -®_eldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "dp-bridge-2"; -}; - -®_fldo1 { - /* TODO should be handled by USB PHY */ - regulator-always-on; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd12-hsic"; -}; - -®_fldo2 { - /* - * Despite the embedded CPUs core not being used in any way, - * this must remain on or the system will hang. - */ - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -®_sw { - regulator-name = "vcc-wifi-io"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - clocks = <&ac100_rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dcdc1>; - vddio-supply = <®_sw>; - device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts deleted file mode 100644 index a7d4ca308990..000000000000 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ /dev/null @@ -1,506 +0,0 @@ -/* - * Copyright (C) 2017 Touchless Biometric Systems AG - * Tomas Novotny - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include -#include -#include - -/ { - model = "TBS A711 Tablet"; - compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_sw>; - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - }; - - panel { - compatible = "tbs,a711-panel", "panel-lvds"; - backlight = <&backlight>; - power-supply = <®_sw>; - - width-mm = <153>; - height-mm = <90>; - data-mapping = "vesa-24"; - - panel-timing { - /* 1024x600 @60Hz */ - clock-frequency = <52000000>; - hactive = <1024>; - vactive = <600>; - hsync-len = <20>; - hfront-porch = <180>; - hback-porch = <160>; - vfront-porch = <12>; - vback-porch = <23>; - vsync-len = <5>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; - - reg_gps: reg-gps { - compatible = "regulator-fixed"; - regulator-name = "gps"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - reg_vbat: reg-vbat { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - reg_vmain: reg-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vbat>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - - /* - * This is actually Bluetooth's clock, but we have to - * hook it up somewheere - */ - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -/* - * An USB-2 hub is connected here, which also means we don't need to - * enable the OHCI controller. - */ -&ehci0 { - status = "okay"; -}; - -/* - * There's a modem connected here that needs to be initialised before - * being able to be enumerated. - */ -&ehci1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5206"; - reg = <0x38>; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */ - reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */ - vcc-supply = <®_ldo_io0>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - accelerometer@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */ - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_dldo1>; - non-removable; - wakeup-source; - keep-power-in-suspend; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - pinctrl-names = "default"; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pin>; - status = "okay"; -}; - -&r_lradc { - vref-supply = <®_aldo2>; - status = "okay"; - - button-210 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <210000>; - }; - - button-410 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <410000>; - }; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; - -}; - -#include "axp81x.dtsi" - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1.8"; -}; - -®_aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-name = "vdd-drampll"; -}; - -®_aldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - regulator-name = "vcc-io"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-name = "vdd-cpu-A"; -}; - -®_dcdc3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-name = "vdd-cpu-B"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-wifi-io"; -}; - -®_dldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <4200000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi-r"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dsi"; -}; - -®_eldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi-f"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-hsic"; -}; - -®_fldo2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-ctp"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-vb"; - status = "okay"; -}; - -®_sw { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-lcd"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_lvds_pins>; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* There's the BT part of the AP6210 connected to that UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm20702a1"; - clocks = <&ac100_rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vbat>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - max-speed = <1500000>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pb_pins>; - status = "okay"; - - gnss { - compatible = "u-blox,neo-6m"; - - v-bckp-supply = <®_rtc_ldo>; - vcc-supply = <®_gps>; - current-speed = <9600>; - }; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_vmain>; - usb2_vbus-supply = <®_vmain>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi deleted file mode 100644 index 94eb3bfc989e..000000000000 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ /dev/null @@ -1,1274 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <1>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <3>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x100>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x101>; - #cooling-cells = <2>; - }; - - cpu102: cpu@102 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x102>; - #cooling-cells = <2>; - }; - - cpu103: cpu@103 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x103>; - #cooling-cells = <2>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* TODO: PRCM block has a mux for this. */ - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - /* - * This is called "internal OSC" in some places. - * It is an internal RC-based oscillator. - * TODO: Its controls are in the PRCM block. - */ - osc16M: osc16M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "osc16M"; - }; - - osc16Md512: osc16Md512_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <512>; - clock-mult = <1>; - clocks = <&osc16M>; - clock-output-names = "osc16M-d512"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-a83t-display-engine"; - allwinner,pipelines = <&mixer0>, <&mixer1>; - status = "disabled"; - }; - - cpu0_opp_table: opp-table-cluster0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1128000000 { - opp-hz = /bits/ 64 <1128000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - cpu1_opp_table: opp-table-cluster1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1128000000 { - opp-hz = /bits/ 64 <1128000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-a83t-de2-clk"; - reg = <0x01000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_PLL_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rotate: rotate@1020000 { - compatible = "allwinner,sun8i-a83t-de2-rotate"; - reg = <0x1020000 0x10000>; - interrupts = ; - clocks = <&display_clocks CLK_BUS_ROT>, - <&display_clocks CLK_ROT>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_ROT>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-a83t-de2-mixer-0"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer0>; - }; - - mixer0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@1200000 { - compatible = "allwinner,sun8i-a83t-de2-mixer-1"; - reg = <0x01200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_WB>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer1>; - }; - - mixer1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer1>; - }; - }; - }; - }; - - cpucfg@1700000 { - compatible = "allwinner,sun8i-a83t-cpucfg"; - reg = <0x01700000 0x400>; - }; - - cci@1790000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01790000 0x10000>; - ranges = <0x0 0x01790000 0x10000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - , - , - , - ; - }; - }; - - syscon: syscon@1c00000 { - compatible = "allwinner,sun8i-a83t-system-controller", - "syscon"; - reg = <0x01c00000 0x1000>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-a83t-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-a83t-tcon-lcd"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; - reset-names = "lcd", "lvds"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon0>; - }; - - tcon0_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun8i-a83t-tcon-tv"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON1>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon1>; - }; - - tcon1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - }; - }; - }; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun8i-a83t-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun8i-a83t-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun8i-a83t-emmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sid: eeprom@1c14000 { - compatible = "allwinner,sun8i-a83t-sid"; - reg = <0x1c14000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@34 { - reg = <0x34 8>; - }; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun8i-a83t-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - resets = <&ccu RST_BUS_SS>; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "bus", "mod"; - }; - - msgbox: mailbox@1c17000 { - compatible = "allwinner,sun8i-a83t-msgbox", - "allwinner,sun6i-a31-msgbox"; - reg = <0x01c17000 0x1000>; - clocks = <&ccu CLK_BUS_MSGBOX>; - resets = <&ccu RST_BUS_MSGBOX>; - interrupts = ; - #mbox-cells = <1>; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-a83t-musb", - "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-a83t-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x14>, - <0x01c1b800 0x14>; - reg-names = "phy_ctrl", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_HSIC>, - <&ccu CLK_USB_HSIC_12M>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb2_hsic_12M"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_HSIC>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun8i-a83t-ehci", - "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI0>; - resets = <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun8i-a83t-ohci", - "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun8i-a83t-ehci", - "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>; - resets = <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-a83t-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc16Md512>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-a83t-pinctrl"; - interrupt-parent = <&r_intc>; - interrupts = , - , - ; - reg = <0x01c20800 0x400>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - /omit-if-no-ref/ - csi_8bit_parallel_pins: csi-8bit-parallel-pins { - pins = "PE0", "PE2", "PE3", "PE6", "PE7", - "PE8", "PE9", "PE10", "PE11", - "PE12", "PE13"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi_mclk_pin: csi-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - emac_rgmii_pins: emac-rgmii-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD11", "PD12", "PD13", "PD14", "PD18", - "PD19", "PD21", "PD22", "PD23"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - hdmi_pins: hdmi-pins { - pins = "PH6", "PH7", "PH8"; - function = "hdmi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PH0", "PH1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH2", "PH3"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c2_pe_pins: i2c2-pe-pins { - pins = "PE14", "PE15"; - function = "i2c2"; - }; - - i2c2_ph_pins: i2c2-ph-pins { - pins = "PH4", "PH5"; - function = "i2c2"; - }; - - i2s1_pins: i2s1-pins { - /* I2S1 does not have external MCLK pin */ - pins = "PG10", "PG11", "PG12", "PG13"; - function = "i2s1"; - }; - - lcd_lvds_pins: lcd-lvds-pins { - pins = "PD18", "PD19", "PD20", "PD21", "PD22", - "PD23", "PD24", "PD25", "PD26", "PD27"; - function = "lvds0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { - pins = "PC5", "PC6", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - pwm_pin: pwm-pin { - pins = "PD28"; - function = "pwm"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PE18"; - function = "spdif"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB9", "PB10"; - function = "uart0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart2_pb_pins: uart2-pb-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-a23-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-spdif", - "allwinner,sun8i-h3-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_BUS_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - resets = <&ccu RST_BUS_I2S0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - dmas = <&dma 4>, <&dma 4>; - resets = <&ccu RST_BUS_I2S1>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_pins>; - status = "disabled"; - }; - - i2s2: i2s@1c22800 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-i2s"; - reg = <0x01c22800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - dmas = <&dma 27>; - resets = <&ccu RST_BUS_I2S2>; - dma-names = "tx"; - status = "disabled"; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-a83t-pwm", - "allwinner,sun8i-h3-pwm"; - reg = <0x01c21400 0x400>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun8i-a83t-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun8i-a83t-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun8i-a83t-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-a83t-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x104>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - csi: camera@1cb0000 { - compatible = "allwinner,sun8i-a83t-csi"; - reg = <0x01cb0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - status = "disabled"; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon1: endpoint { - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-a83t-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun8i-a83t-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - r_ccu: clock@1f01400 { - compatible = "allwinner,sun8i-a83t-r-ccu"; - reg = <0x01f01400 0x400>; - clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, - <&ccu CLK_PLL_PERIPH>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - r_cpucfg@1f01c00 { - compatible = "allwinner,sun8i-a83t-r-cpucfg"; - reg = <0x1f01c00 0x400>; - }; - - r_cir: ir@1f02000 { - compatible = "allwinner,sun8i-a83t-ir", - "allwinner,sun6i-a31-ir"; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; - interrupts = ; - reg = <0x01f02000 0x400>; - pinctrl-names = "default"; - pinctrl-0 = <&r_cir_pin>; - status = "disabled"; - }; - - r_lradc: lradc@1f03c00 { - compatible = "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01f03c00 0x100>; - interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-a83t-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, - <&osc16Md512>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_cir_pin: r-cir-pin { - pins = "PL12"; - function = "s_cir_rx"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - }; - - r_rsb: rsb@1f03400 { - compatible = "allwinner,sun8i-a83t-rsb", - "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_RSB>; - clock-frequency = <3000000>; - resets = <&r_ccu RST_APB0_RSB>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ths: thermal-sensor@1f04000 { - compatible = "allwinner,sun8i-a83t-ths"; - reg = <0x01f04000 0x100>; - interrupts = ; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - - trips { - cpu0_hot: cpu-hot { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_very_hot: cpu-very-hot { - temperature = <100000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - cpu-hot-limit { - trip = <&cpu0_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1_thermal: cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - - trips { - cpu1_hot: cpu-hot { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_very_hot: cpu-very-hot { - temperature = <100000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - cpu-hot-limit { - trip = <&cpu1_hot>; - cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts deleted file mode 100644 index d729b7c705db..000000000000 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Icenowy Zheng - * - * Based on sun8i-h3-bananapi-m2-plus.dts, which is: - * Copyright (C) 2016 Chen-Yu Tsai - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Banana Pi BPI-M2-Zero"; - compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "bananapi-m2-zero:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - switch-4 { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - - gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ - enable-active-high; - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - vin-supply = <®_vcc5v0>; - }; - - reg_vcc1v2: vcc1v2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - vin-supply = <®_vcc5v0>; - }; - - poweroff { - compatible = "regulator-poweroff"; - cpu-supply = <®_vcc1v2>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - /* - * On the production batch of this board the card detect GPIO is - * high active (card inserted), although on the early samples it's - * low active. - */ - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <1500000>; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - }; - -}; - -&pio { - gpio-line-names = - /* PA */ - "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", - "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", - "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", - "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", - "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", - "CON2-P40", "CON2-P38", "", "", - "", "", "", "", "", "", "", "", - - /* PB */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - - /* PC */ - "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", - "CON2-P18", "", "", "CON2-P26", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - - /* PD */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "CSI-PWR-EN", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - - /* PE */ - "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", - "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", - "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", - "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - - /* PF */ - "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", - "SDC0-D2", "SDC0-DET", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - - /* PG */ - "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", - "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", - "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", - "BT-RST-N", "AP-WAKE-BT", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&r_pio { - gpio-line-names = - /* PL */ - "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", - "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", - "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - /* - * There're two micro-USB connectors, one is power-only and another is - * OTG. The Vbus of these two connectors are connected together, so - * the external USB device will be powered just by the power input - * from the power-only USB port. - */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts deleted file mode 100644 index 4db0d4bb65eb..000000000000 --- a/arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Chen-Yu Tsai - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-libretech-all-h3-cc.dtsi" - -/ { - model = "Libre Computer Board ALL-H3-CC H2+"; - compatible = "libretech,all-h3-cc-h2-plus", "allwinner,sun8i-h2-plus"; -}; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts deleted file mode 100644 index 3356f4210d45..000000000000 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* Orange Pi R1 is based on Orange Pi Zero design */ -#include "sun8i-h2-plus-orangepi-zero.dts" - -/ { - model = "Xunlong Orange Pi R1"; - compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; - - /delete-node/ reg_vcc_wifi; - - /* - * Ths pin of this regulator is the same with the Wi-Fi extra - * regulator on the original Zero. However it's used for USB - * Ethernet rather than the Wi-Fi now. - */ - reg_vcc_usb_eth: reg-vcc-usb-ethernet { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-ethernet"; - enable-active-high; - gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - - aliases { - ethernet1 = &rtl8189etv; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - }; -}; - -&ohci1 { - /* - * RTL8152B USB-Ethernet adapter is connected to USB1, - * and it's a USB 2.0 device. So the OHCI1 controller - * can be left disabled. - */ - status = "disabled"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - - rtl8189etv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc_usb_eth>; -}; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts deleted file mode 100644 index 3706216ffb40..000000000000 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * Based on sun8i-h3-orangepi-one.dts, which is: - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi Zero"; - compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus"; - - aliases { - serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet0 = &emac; - ethernet1 = &xr819; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc_wifi: reg_vcc_wifi { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - enable-active-high; - gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - enable-active-high; - gpios-states = <1>; - states = <1100000 0>, <1300000 1>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - xr819: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&spi0 { - /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - /* - * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only - * power up the board; when it's used as OTG port, this VBUS is - * always off even if the board is powered via GPIO pins. - */ - status = "okay"; - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts deleted file mode 100644 index fc4a8c3d084d..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Chen-Yu Tsai - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-bananapi-m2-plus-v1.2.dtsi" - -/ { - model = "Banana Pi BPI-M2-Plus v1.2 H3"; - compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts deleted file mode 100644 index 195a75da13f1..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-bananapi-m2-plus.dtsi" - -/ { - model = "Banana Pi BPI-M2-Plus H3"; - compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts deleted file mode 100644 index a6d38ecee141..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (C) 2017 Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Beelink X2"; - compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - ethernet0 = &emac; - ethernet1 = &sdiowifi; - }; - - cec { - compatible = "cec-gpio"; - cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ - hdmi-phandle = <&hdmi>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "beelink-x2:blue:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - led-1 { - label = "beelink-x2:red:standby"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - sound_spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - linux,rc-map-name = "rc-tanix-tx3mini"; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - sdiowifi: sdio_wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on except for the OTG port */ - status = "okay"; - usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ - usb0_vbus-supply = <®_usb0_vbus>; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts deleted file mode 100644 index 02fbe00cde97..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * DTS for Emlid Neutis N5 Dev board. - * - * Copyright (C) 2019 Georgii Staroselskii - */ - -/dts-v1/; - -#include "sun8i-h3-emlid-neutis-n5h3.dtsi" - -/ { - model = "Emlid Neutis N5H3 Developer board"; - compatible = "emlid,neutis-n5h3-devboard", - "emlid,neutis-n5h3", - "allwinner,sun8i-h3"; - - vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0x0>, <1300000 0x1>; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - -}; - -&cpu0 { - cpu-supply = <&vdd_cpux>; -}; - -&codec { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi deleted file mode 100644 index 35e71f46c197..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * DTSI for Emlid Neutis N5 SoM. - * - * Copyright (C) 2019 Georgii Staroselskii - */ - -/dts-v1/; - -#include "sun8i-h3.dtsi" -#include "sunxi-h3-h5-emlid-neutis.dtsi" diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts deleted file mode 100644 index a8b2f0f1c11d..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-libretech-all-h3-cc.dtsi" - -/ { - model = "Libre Computer Board ALL-H3-CC H3"; - compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts deleted file mode 100644 index f5c8ccc5b872..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 Centrum Embedded Systems, Jia-Bin Huang - * Copyright (C) 2018 Jonathan McDowell - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "MapleBoard MP130"; - compatible = "mapleboard,mp130", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "mp130:orange:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "mp130:orange:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ - }; - - key-user { - label = "user"; - linux,code = ; - gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "LINEIN", "Line In"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts deleted file mode 100644 index 343b02b97155..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Karl Palsson - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "FriendlyARM NanoPi Duo2"; - compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "nanopi:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - led-1 { - label = "nanopi:green:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-0 { - label = "k1"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50>; /* 4ms */ - - enable-active-high; - enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - vin-supply = <®_vcc5v0>; - }; - - reg_vdd_sys: vdd-sys { - compatible = "regulator-fixed"; - regulator-name = "vdd-sys"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - vin-supply = <®_vcc5v0>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; - -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - }; -}; - -&usb_otg { - status = "okay"; - dr_mode = "otg"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts deleted file mode 100644 index 4ba533b0340f..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (C) 2017 Jagan Teki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyArm NanoPi M1 Plus"; - compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; - - aliases { - serial1 = &uart3; - ethernet0 = &emac; - ethernet1 = &sdio_wifi; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts deleted file mode 100644 index 69243dcb30a6..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyArm NanoPi M1"; - compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts deleted file mode 100644 index 9e1a33f94cad..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2017 Jelle van der Waa - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "FriendlyARM NanoPi NEO Air"; - compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - led-1 { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - }; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts deleted file mode 100644 index df71fab3cf4e..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2016 James Pettigrew - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyARM NanoPi NEO"; - compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts deleted file mode 100644 index 42cd1131adf3..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Igor Pecovnik - * Copyright (C) 2020 Jayantajit Gogoi - * Copyright (C) 2020 Yu-Tung Chang -*/ - -#include "sun8i-h3-nanopi.dtsi" -#include - -/ { - model = "FriendlyARM NanoPi R1"; - compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; - - aliases { - serial1 = &uart1; - ethernet0 = &emac; - ethernet1 = &wifi; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; - - reg_vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0x0>, - <1300000 0x1>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; - - leds { - led-2 { - function = LED_FUNCTION_WAN; - color = ; - gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - }; - - led-3 { - function = LED_FUNCTION_LAN; - color = ; - gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */ - }; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - wifi: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - }; -}; - -&usb_otg { - status = "okay"; - dr_mode = "otg"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi deleted file mode 100644 index cf8413fba6c1..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (C) 2016 James Pettigrew - * Copyright (C) 2016 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-0 { - label = "k1"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts deleted file mode 100644 index f1f9dbead32a..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi 2"; - compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet0 = &emac; - ethernet1 = &rtl8189; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - switch-2 { - label = "sw2"; - linux,code = ; - gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; - }; - - switch-4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ - allwinner,audio-routing = - "Speaker", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189: sdio_wifi@1 { - reg = <1>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts deleted file mode 100644 index 305b34a321f5..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi Lite"; - compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; - - aliases { - /* The H3 emac is not used so the wifi is ethernet0 */ - ethernet0 = &rtl8189ftv; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - switch-4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts deleted file mode 100644 index 59f6f6d5e7ca..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi One"; - compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - switch-4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - enable-active-high; - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A port's VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts deleted file mode 100644 index babf4cf1b2f6..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The Orange Pi PC Plus is an extended version of the regular PC */ -#include "sun8i-h3-orangepi-pc.dts" - -/ { - model = "Xunlong Orange Pi PC Plus"; - compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; - - aliases { - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet1 = &rtl8189ftv; - }; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; - /* eMMC is missing pull-ups */ - bias-pull-up; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts deleted file mode 100644 index b96e015f54ee..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (C) 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi PC"; - compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - switch-4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - reg_vdd_cpux: regulator@65 { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "vdd-cpux"; - silergy,fixed-microvolt = <1200000>; - /* - * The datasheet uses 1.1V as the minimum value of VDD-CPUX, - * however both the Armbian DVFS table and the official one - * have operating points with voltage under 1.1V, and both - * DVFS table are known to work properly at the lowest - * operating point. - * - * Use 1.0V as the minimum voltage instead. - */ - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - /* VBUS on USB host ports are always on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts deleted file mode 100644 index d05fa679dcd3..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ -#include "sun8i-h3-orangepi-2.dts" - -/ { - model = "Xunlong Orange Pi Plus / Plus 2"; - compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; - /* eMMC is missing pull-ups */ - bias-pull-up; -}; - -&r_i2c { - status = "okay"; - - reg_vdd_cpux: regulator@65 { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "vdd-cpux"; - silergy,fixed-microvolt = <1200000>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <200>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&usbphy { - usb3_vbus-supply = <®_usb3_vbus>; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts deleted file mode 100644 index b6ca45d18e51..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, - * with 2G RAM and an external gbit ethernet phy. - */ - -#include "sun8i-h3-orangepi-pc-plus.dts" - -/ { - model = "Xunlong Orange Pi Plus 2E"; - compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts deleted file mode 100644 index 561ea1d2f861..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2017 Jagan Teki - * Copyright (C) 2018 Diego Rondini - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "sun8i-h3.dtsi" - -#include - -/ { - model = "OrangePi Zero Plus2 H3"; - compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-1 { - label = "orangepi:red:status"; - gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - post-power-on-delay-ms = <200>; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * According to schematics CN1 MicroUSB port can be used to take - * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB - * port cannot provide power externally even if the board is powered - * via GPIO pins. It thus makes sense to force peripheral mode. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts deleted file mode 100644 index 4738f3a9efe4..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Bootlin - * Author: Paul Kocialkowski - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "RerVision H3-DVK"; - compatible = "rervision,h3-dvk", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/sun8i-h3-zeropi.dts deleted file mode 100644 index 7d3e7323b661..000000000000 --- a/arch/arm/boot/dts/sun8i-h3-zeropi.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2020 Yu-Tung Chang - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyARM ZeroPi"; - compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - - allwinner,leds-active-low; - status = "okay"; -}; - -&usb_otg { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi deleted file mode 100644 index eac2349a2380..000000000000 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-h3-h5.dtsi" -#include - -/ { - cpu0_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000 1040000 1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1100000 1100000 1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000 1200000 1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - gpu_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - }; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - }; - - opp-432000000 { - opp-hz = /bits/ 64 <432000000>; - }; - - opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - soc { - deinterlace: deinterlace@1400000 { - compatible = "allwinner,sun8i-h3-deinterlace"; - reg = <0x01400000 0x20000>; - clocks = <&ccu CLK_BUS_DEINTERLACE>, - <&ccu CLK_DEINTERLACE>, - <&ccu CLK_DRAM_DEINTERLACE>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_DEINTERLACE>; - interrupts = ; - interconnects = <&mbus 9>; - interconnect-names = "dma-mem"; - }; - - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0x80000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun8i-h3-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun8i-h3-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun8i-h3-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - operating-points-v2 = <&gpu_opp_table>; - }; - - ths: thermal-sensor@1c25000 { - compatible = "allwinner,sun8i-h3-ths"; - reg = <0x01c25000 0x400>; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <0>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths>; - - trips { - cpu_hot_trip: cpu-hot { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_very_hot_trip: cpu-very-hot { - temperature = <100000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - cpu-hot-limit { - trip = <&cpu_hot_trip>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-h3-ccu"; -}; - -&display_clocks { - compatible = "allwinner,sun8i-h3-de2-clk"; -}; - -&mbus { - compatible = "allwinner,sun8i-h3-mbus"; -}; - -&mmc0 { - compatible = "allwinner,sun7i-a20-mmc"; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; -}; - -&mmc1 { - compatible = "allwinner,sun7i-a20-mmc"; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; -}; - -&mmc2 { - compatible = "allwinner,sun7i-a20-mmc"; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; -}; - -&pio { - compatible = "allwinner,sun8i-h3-pinctrl"; -}; - -&rtc { - compatible = "allwinner,sun8i-h3-rtc"; -}; - -&sid { - compatible = "allwinner,sun8i-h3-sid"; -}; diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi deleted file mode 100644 index 3d9a1524e17e..000000000000 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - aliases { - serial0 = &r_uart; - /* Make u-boot set mac-address for wifi without an eeprom */ - ethernet0 = &sdio_wifi; - }; - - panel: panel { - /* Tablet dts should provide panel compatible */ - backlight = <&backlight>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_dc1sw>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - /* - * Q8 boards use various PL# pins as wifi-en. On other boards - * these may be connected to a wifi module output pin. To avoid - * short-circuits we configure these as inputs with pull-ups via - * pinctrl, instead of listing them as active-low reset-gpios. - */ - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_q8>; - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - }; -}; - -&r_pio { - wifi_pwrseq_pin_q8: wifi-pwrseq-pins { - pins = "PL6", "PL7", "PL11"; - function = "gpio_in"; - bias-pull-up; - }; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts deleted file mode 100644 index bc394686fedb..000000000000 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2017 Free Electrons - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" - -#include - -/ { - model = "BananaPi M2 Magic"; - compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "bpi-m2m:blue:usr"; - gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "bpi-m2m:green:usr"; - gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; - }; - - led-2 { - label = "bpi-m2m:red:power"; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&cpu0_opp_table { - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -/* - * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same - * time, with the two being in sync. Since this is not really - * supported right now, just use the two as always on, and we will fix - * it later. - */ -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi0"; -}; - -®_dldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&sound { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_dldo1>; - vddio-supply = <®_aldo3>; - device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts deleted file mode 100644 index 246dec5846a4..000000000000 --- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* Copyright (c) 2016 FUKAUMI Naoki */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Nintendo NES Classic Edition"; - compatible = "nintendo,nes-classic", "allwinner,sun8i-r16", - "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - /* - * UART0 is available on two ports: PB and PF, both are accessible. - * PF can also be used for the SD card so PB is preferred. - */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pf_pins>; - status = "okay"; -}; - -&nfc { - status = "okay"; - - /* 2Gb Macronix MX30LF2G18AC (3V) */ - nand@0 { - reg = <0>; - allwinner,rb = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <16>; - nand-ecc-step-size = <1024>; - }; -}; - -&usb_otg { - status = "okay"; - dr_mode = "otg"; -}; - -&usbphy { - /* VBUS is always on because it is wired to the power supply */ - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts deleted file mode 100644 index 80761d7904ec..000000000000 --- a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* Copyright (c) 2018 Miquèl RAYNAL */ - -/dts-v1/; -#include "sun8i-r16-nintendo-nes-classic.dts" - -/ { - model = "Nintendo SuperNES Classic Edition"; - compatible = "nintendo,super-nes-classic", "nintendo,nes-classic", - "allwinner,sun8i-r16", "allwinner,sun8i-a33"; -}; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts deleted file mode 100644 index 95543a9c2118..000000000000 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright 2016 Quentin Schulz - * - * Quentin Schulz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Allwinner R16 EVB (Parrot)"; - compatible = "allwinner,parrot", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - label = "parrot:led1:usr"; - gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; - - led-2 { - label = "parrot:led2:usr"; - gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - }; - -}; - -&codec { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - /* - * FIXME: An as-yet-unknown accelerometer is connected to this - * i2c bus. - */ -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-190 { - label = "V+"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "V-"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - /* - * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. - * Remove next line once it is possible to sync two regulators. - */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi0"; -}; - -®_dldo2 { - /* - * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. - * Remove next line once it is possible to sync two regulators. - */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_dldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_eldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-dsp"; -}; - -®_eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "eldo3"; -}; - -®_usb1_vbus { - gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb0_vbus-supply = <®_drivevbus>; - usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; -}; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts deleted file mode 100644 index 28197bbcb1d5..000000000000 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-r40.dtsi" -#include "sun8i-r40-cpu-opp.dtsi" - -#include - -/ { - model = "Banana Pi BPI-M2-Ultra"; - compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; - - aliases { - ethernet0 = &gmac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-led { - label = "bananapi:red:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user-led-green { - label = "bananapi:green:user"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - user-led-blue { - label = "bananapi:blue:user"; - gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ - clocks = <&ccu CLK_OUTA>; - clock-names = "ext_clock"; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo3>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&ir0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&clk_out_a_pin>; - vcc-pa-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo1>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo1>; -}; - -®_aldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -/* - * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same - * time, with the two being in sync, to be able to meet maximum power - * consumption during transmits. Since this is not really supported - * right now, just use the two as always on, and we will fix it later. - */ - -®_dldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; -}; - -®_dldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd2v5-sata"; -}; - -®_eldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd1v2-sata"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&ccu CLK_OUTA>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - /* TODO host wake line connected to PMIC GPIO pins */ - shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - max-speed = <1500000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi deleted file mode 100644 index 649928b361af..000000000000 --- a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/{ - cpu0_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1000000 1000000 1300000>; - clock-latency-ns = <2000000>; - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <1100000 1100000 1300000>; - clock-latency-ns = <2000000>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1160000 1160000 1300000>; - clock-latency-ns = <2000000>; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1240000 1240000 1300000>; - clock-latency-ns = <2000000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1300000 1300000 1300000>; - clock-latency-ns = <2000000>; - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu0_opp_table>; -}; diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi deleted file mode 100644 index 9f39b5a2bb35..000000000000 --- a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// Copyright (C) 2021 Ivan Uvarov -// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: -// Copyright (C) 2017 Chen-Yu Tsai -// Copyright (C) 2017 Icenowy Zheng - -#include "sun8i-r40.dtsi" -#include "sun8i-r40-cpu-opp.dtsi" - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&mmc2 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_aldo2>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&clk_out_a_pin>; - vcc-pa-supply = <®_dcdc1>; - vcc-pc-supply = <®_aldo2>; - vcc-pd-supply = <®_dcdc1>; - vcc-pf-supply = <®_dldo4>; - vcc-pg-supply = <®_dldo1>; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd2v5-sata"; -}; - -®_eldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd1v2-sata"; -}; - -®_eldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts deleted file mode 100644 index 0bd1336206b8..000000000000 --- a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// Copyright (C) 2021 Ivan Uvarov -// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: -// Copyright (C) 2017 Chen-Yu Tsai -// Copyright (C) 2017 Icenowy Zheng - -/dts-v1/; -#include "sun8i-r40-feta40i.dtsi" - -#include -#include - -/ { - model = "Forlinx OKA40i-C"; - compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; - - aliases { - ethernet0 = &gmac; - serial0 = &uart0; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; /* RS485 */ - serial7 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-5 { /* this is how the leds are labeled on the board */ - gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-6 { - gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ - color = ; - function = LED_FUNCTION_STATUS; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN - clocks = <&ccu CLK_OUTA>; - clock-names = "ext_clock"; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo2>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_dcdc1>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -®_dc1sw { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-lcd"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pg_pins>; - status = "okay"; -}; - -&uart5 { /* RS485 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart5_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi deleted file mode 100644 index 4ef26d8f5340..000000000000 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ /dev/null @@ -1,1326 +0,0 @@ -/* - * Copyright 2017 Chen-Yu Tsai - * Copyright 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <20000>; - clock-output-names = "ext-osc32k"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPU>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPU>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPU>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-r40-display-engine"; - allwinner,pipelines = <&mixer0>, <&mixer1>; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu0-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - - trips { - cpu_hot_trip: cpu-hot { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_very_hot_trip: cpu-very-hot { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - cpu-hot-limit { - trip = <&cpu_hot_trip>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-r40-de2-clk", - "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-r40-de2-mixer-0"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - mixer0_out_tcon_top: endpoint { - remote-endpoint = <&tcon_top_mixer0_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@1200000 { - compatible = "allwinner,sun8i-r40-de2-mixer-1"; - reg = <0x01200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_WB>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - reg = <1>; - mixer1_out_tcon_top: endpoint { - remote-endpoint = <&tcon_top_mixer1_in_mixer1>; - }; - }; - }; - }; - - deinterlace: deinterlace@1400000 { - compatible = "allwinner,sun8i-r40-deinterlace", - "allwinner,sun8i-h3-deinterlace"; - reg = <0x01400000 0x20000>; - clocks = <&ccu CLK_BUS_DEINTERLACE>, - <&ccu CLK_DEINTERLACE>, - /* - * NOTE: Contrary to what datasheet claims, - * DRAM deinterlace gate doesn't exist and - * it's shared with CSI1. - */ - <&ccu CLK_DRAM_CSI1>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_DEINTERLACE>; - interrupts = ; - interconnects = <&mbus 9>; - interconnect-names = "dma-mem"; - }; - - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-r40-system-control", - "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun8i-r40-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - nmi_intc: interrupt-controller@1c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupts = ; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-r40-dma", - "allwinner,sun50i-a64-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - dma-channels = <16>; - dma-requests = <31>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c05000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c06000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - csi0: csi@1c09000 { - compatible = "allwinner,sun8i-r40-csi0", - "allwinner,sun7i-a20-csi0"; - reg = <0x01c09000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI0>; - clock-names = "bus", "isp", "ram"; - resets = <&ccu RST_BUS_CSI0>; - interconnects = <&mbus 5>; - interconnect-names = "dma-mem"; - status = "disabled"; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun8i-r40-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun8i-r40-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun8i-r40-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun8i-r40-emmc", - "allwinner,sun50i-a64-emmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - pinctrl-0 = <&mmc2_pins>; - pinctrl-names = "default"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun8i-r40-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC3>; - reset-names = "ahb"; - pinctrl-0 = <&mmc3_pins>; - pinctrl-names = "default"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbphy: phy@1c13400 { - compatible = "allwinner,sun8i-r40-usb-phy"; - reg = <0x01c13400 0x14>, - <0x01c14800 0x4>, - <0x01c19800 0x4>, - <0x01c1c800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun8i-r40-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c17000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun8i-r40-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; - resets = <&ccu RST_BUS_SATA>; - reset-names = "ahci"; - status = "disabled"; - }; - - ehci1: usb@1c19000 { - compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; - reg = <0x01c19000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>; - resets = <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c19400 { - compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; - reg = <0x01c19400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@1c1c000 { - compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>; - resets = <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@1c1c400 { - compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-r40-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@1c20400 { - compatible = "allwinner,sun8i-r40-rtc"; - reg = <0x01c20400 0x400>; - interrupts = ; - clock-output-names = "osc32k", "osc32k-out"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-r40-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - can_ph_pins: can-ph-pins { - pins = "PH20", "PH21"; - function = "can"; - }; - - can_pa_pins: can-pa-pins { - pins = "PA16", "PA17"; - function = "can"; - }; - - clk_out_a_pin: clk-out-a-pin { - pins = "PI12"; - function = "clk_out_a"; - }; - - /omit-if-no-ref/ - csi0_8bits_pins: csi0-8bits-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", - "PE6", "PE7", "PE8", "PE9", "PE10", - "PE11"; - function = "csi0"; - }; - - /omit-if-no-ref/ - csi0_mclk_pin: csi0-mclk-pin { - pins = "PE1"; - function = "csi0"; - }; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA10", "PA11", "PA12", - "PA13", "PA15", "PA16"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - i2c3_pins: i2c3-pins { - pins = "PI0", "PI1"; - function = "i2c3"; - }; - - i2c4_pins: i2c4-pins { - pins = "PI2", "PI3"; - function = "i2c4"; - }; - - ir0_pins: ir0-pins { - pins = "PB4"; - function = "ir0"; - }; - - ir1_pins: ir1-pins { - pins = "PB23"; - function = "ir1"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pg_pins: mmc1-pg-pins { - pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC5", "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", "PC14", - "PC15", "PC24"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc3_pins: mmc3-pins { - pins = "PI4", "PI5", "PI6", - "PI7", "PI8", "PI9"; - function = "mmc3"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pc_pins: spi0-pc-pins { - pins = "PC0", "PC1", "PC2"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pc_pin: spi0-cs0-pc-pin { - pins = "PC23"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pi_pins: spi1-pi-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pi_pin: spi1-cs0-pi-pin { - pins = "PI16"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs1_pi_pin: spi1-cs1-pi-pin { - pins = "PI15"; - function = "spi1"; - }; - - /omit-if-no-ref/ - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart2_pi_pins: uart2-pi-pins { - pins = "PI18", "PI19"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ - pins = "PI16", "PI17"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart3_pg_pins: uart3-pg-pins { - pins = "PG6", "PG7"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { - pins = "PG8", "PG9"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart4_pg_pins: uart4-pg-pins { - pins = "PG10", "PG11"; - function = "uart4"; - }; - - /omit-if-no-ref/ - uart5_ph_pins: uart5-ph-pins { - pins = "PH6", "PH7"; - function = "uart5"; - }; - - /omit-if-no-ref/ - uart7_pi_pins: uart7-pi-pins { - pins = "PI20", "PI21"; - function = "uart7"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = , - , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = ; - clocks = <&osc24M>; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun8i-r40-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x01c21800 0x400>; - pinctrl-0 = <&ir0_pins>; - pinctrl-names = "default"; - clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; - clock-names = "apb", "ir"; - interrupts = ; - resets = <&ccu RST_BUS_IR0>; - status = "disabled"; - }; - - ir1: ir@1c21c00 { - compatible = "allwinner,sun8i-r40-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x01c21c00 0x400>; - pinctrl-0 = <&ir1_pins>; - pinctrl-names = "default"; - clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; - clock-names = "apb", "ir"; - interrupts = ; - resets = <&ccu RST_BUS_IR1>; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-r40-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S0>; - dmas = <&dma 3>, <&dma 3>; - dma-names = "rx", "tx"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-r40-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S1>; - dmas = <&dma 4>, <&dma 4>; - dma-names = "rx", "tx"; - }; - - i2s2: i2s@1c22800 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-r40-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S2>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - }; - - ths: thermal-sensor@1c24c00 { - compatible = "allwinner,sun8i-r40-ths"; - reg = <0x01c24c00 0x100>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - /* TODO: add nvmem-cells for calibration */ - #thermal-sensor-cells = <1>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART6>; - resets = <&ccu RST_BUS_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART7>; - resets = <&ccu RST_BUS_UART7>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@1c2b800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@1c2bc00 { - compatible = "allwinner,sun8i-r40-can"; - reg = <0x01c2bc00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CAN>; - resets = <&ccu RST_BUS_CAN>; - status = "disabled"; - }; - - i2c4: i2c@1c2c000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2c000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C4>; - resets = <&ccu RST_BUS_I2C4>; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - }; - - gmac: ethernet@1c50000 { - compatible = "allwinner,sun8i-r40-gmac"; - syscon = <&ccu>; - reg = <0x01c50000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_GMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_GMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - gmac_mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-r40-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu 155>; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x40000000 0x80000000>; - #interconnect-cells = <1>; - }; - - tcon_top: tcon-top@1c70000 { - compatible = "allwinner,sun8i-r40-tcon-top"; - reg = <0x01c70000 0x1000>; - clocks = <&ccu CLK_BUS_TCON_TOP>, - <&ccu CLK_TCON_TV0>, - <&ccu CLK_TVE0>, - <&ccu CLK_TCON_TV1>, - <&ccu CLK_TVE1>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", - "tcon-tv0", - "tve0", - "tcon-tv1", - "tve1", - "dsi"; - clock-output-names = "tcon-top-tv0", - "tcon-top-tv1", - "tcon-top-dsi"; - resets = <&ccu RST_BUS_TCON_TOP>; - #clock-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer0_in: port@0 { - reg = <0>; - - tcon_top_mixer0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon_top>; - }; - }; - - tcon_top_mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { - reg = <0>; - }; - - tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { - reg = <1>; - }; - - tcon_top_mixer0_out_tcon_tv0: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; - }; - - tcon_top_mixer0_out_tcon_tv1: endpoint@3 { - reg = <3>; - remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; - }; - }; - - tcon_top_mixer1_in: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - tcon_top_mixer1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon_top>; - }; - }; - - tcon_top_mixer1_out: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { - reg = <0>; - }; - - tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { - reg = <1>; - }; - - tcon_top_mixer1_out_tcon_tv0: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; - }; - - tcon_top_mixer1_out_tcon_tv1: endpoint@3 { - reg = <3>; - remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; - }; - }; - - tcon_top_hdmi_in: port@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - tcon_top_hdmi_in_tcon_tv0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_tv0_out_tcon_top>; - }; - - tcon_top_hdmi_in_tcon_tv1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_tv1_out_tcon_top>; - }; - }; - - tcon_top_hdmi_out: port@5 { - reg = <5>; - - tcon_top_hdmi_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_tcon_top>; - }; - }; - }; - }; - - tcon_tv0: lcd-controller@1c73000 { - compatible = "allwinner,sun8i-r40-tcon-tv"; - reg = <0x01c73000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV0>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon_tv0_in_tcon_top_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; - }; - - tcon_tv0_in_tcon_top_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; - }; - }; - - tcon_tv0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_tv0_out_tcon_top: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; - }; - }; - }; - }; - - tcon_tv1: lcd-controller@1c74000 { - compatible = "allwinner,sun8i-r40-tcon-tv"; - reg = <0x01c74000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV1>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon_tv1_in_tcon_top_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; - }; - - tcon_tv1_in_tcon_top_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; - }; - }; - - tcon_tv1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_tv1_out_tcon_top: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; - }; - }; - }; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun8i-r40-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; - clock-names = "iahb", "isfr", "tmds", "cec"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon_top: endpoint { - remote-endpoint = <&tcon_top_hdmi_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-r40-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; - clock-names = "bus", "mod", "pll-0", "pll-1"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi deleted file mode 100644 index 872d56caa9ce..000000000000 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include - -/ { - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - power-supply = <®_dc1sw>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - /* - * The gsl1680 is rated at 400KHz and it will not work reliable at - * 100KHz, this has been confirmed on multiple different q8 tablets. - * The gsl1680 is the only device on this bus. - */ - clock-frequency = <400000>; - - touchscreen: touchscreen@40 { - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ - power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - /* Tablet dts must provide reg and compatible */ - status = "disabled"; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = ; - eldoin-supply = <®_dcdc1>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi deleted file mode 100644 index 052b010a5607..000000000000 --- a/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Matteo Scordino - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Elimo Impetus SoM"; - compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts b/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts deleted file mode 100644 index 039677c2cc65..000000000000 --- a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Matteo Scordino - */ - -/dts-v1/; -#include "sun8i-s3-elimo-impetus.dtsi" - -/ { - model = "Elimo Initium"; - compatible = "elimo,initium", "elimo,impetus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial1 = &uart1; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pg_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts deleted file mode 100644 index d18192d51d1b..000000000000 --- a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" - -#include - -/ { - model = "Sipeed Lichee Zero Plus"; - compatible = "sipeed,lichee-zero-plus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts deleted file mode 100644 index 20966e954eda..000000000000 --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2019 Icenowy Zheng - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" -#include -#include - -/ { - model = "PineCube IP Camera"; - compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "pine64:ir:led1"; - gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ - }; - - led2 { - label = "pine64:ir:led2"; - gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vcc_wifi: vcc-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ - vin-supply = <®_dcdc3>; - startup-delay-us = <200000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ - post-power-on-delay-ms = <200>; - }; -}; - -&csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&csi1_8bit_pins>; - status = "okay"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pe_pins>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&csi1_mclk_pin>; - clocks = <&ccu CLK_CSI1_MCLK>; - clock-names = "xclk"; - - AVDD-supply = <®_ldo3>; - DOVDD-supply = <®_ldo3>; - DVDD-supply = <®_ldo4>; - reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ - powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ - - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi1_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Setup"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc_wifi>; - vqmmc-supply = <®_dcdc3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_dcdc3>; - vcc-pe-supply = <®_ldo3>; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-sys-cpu-ephy"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-dovdd-2v8-csi"; - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -®_ldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-1v8-csi"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts deleted file mode 100644 index 94e24b5926dd..000000000000 --- a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -// Copyright (C) 2022 Arm Ltd. - -#include - -/dts-v1/; - -#include "sun8i-t113s.dtsi" -#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" - -/ { - model = "MangoPi MQ-R-T113"; - compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; - - aliases { - ethernet0 = &rtl8189ftv; - }; -}; - -&cpu0 { - cpu-supply = <®_vcc_core>; -}; - -&cpu1 { - cpu-supply = <®_vcc_core>; -}; - -&mmc1 { - rtl8189ftv: wifi@1 { - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ - interrupt-names = "host-wake"; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi deleted file mode 100644 index 804aa197a24f..000000000000 --- a/arch/arm/boot/dts/sun8i-t113s.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -// Copyright (C) 2022 Arm Ltd. - -#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - }; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts deleted file mode 100644 index 9f472521f4a4..000000000000 --- a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2017 Chen-Yu Tsai - * Copyright (C) 2017 Icenowy Zheng - * Copyright (C) 2018 Hao Zhang - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-r40.dtsi" -#include "sun8i-r40-cpu-opp.dtsi" - -#include - -/ { - model = "t3-cqa3t-bv3"; - compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3", - "allwinner,sun8i-r40"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - enable-active-high; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo3>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pg"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-dldo3"; -}; - -®_eldo3 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts deleted file mode 100644 index 117aeece4e55..000000000000 --- a/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2020 Paul Kocialkowski - */ - -#include "sun8i-v3-sl631.dtsi" - -/ { - model = "SL631 Action Camera with IMX179"; - compatible = "allwinner,sl631-imx179", "allwinner,sl631", - "allwinner,sun8i-v3"; -}; diff --git a/arch/arm/boot/dts/sun8i-v3-sl631.dtsi b/arch/arm/boot/dts/sun8i-v3-sl631.dtsi deleted file mode 100644 index 6f93f8c49f84..000000000000 --- a/arch/arm/boot/dts/sun8i-v3-sl631.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2020 Paul Kocialkowski - */ - -/dts-v1/; - -#include "sun8i-v3.dtsi" - -#include -#include - -/ { - model = "SL631 Action Camera"; - compatible = "allwinner,sl631", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pb_pins>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-174 { - label = "Down"; - linux,code = ; - channel = <0>; - voltage = <174603>; - }; - - button-384 { - label = "Up"; - linux,code = ; - channel = <0>; - voltage = <384126>; - }; - - button-593 { - label = "OK"; - linux,code = ; - channel = <0>; - voltage = <593650>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - vmmc-supply = <®_dcdc3>; - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_dcdc3>; - vcc-pe-supply = <®_dcdc3>; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-sys-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vdd-3v3"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pg_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi deleted file mode 100644 index 186c30cbe6ee..000000000000 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng - * Copyright (C) 2021 Tobias Schramm - */ - -#include "sun8i-v3s.dtsi" - -/ { - soc { - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-v3-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins>; - resets = <&ccu RST_BUS_I2S0>; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-v3-ccu"; -}; - -&codec_analog { - compatible = "allwinner,sun8i-v3-codec-analog", - "allwinner,sun8i-h3-codec-analog"; -}; - -&emac { - /delete-property/ phy-handle; - /delete-property/ phy-mode; -}; - -&mdio_mux { - external_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&pio { - compatible = "allwinner,sun8i-v3-pinctrl"; - - i2s0_pins: i2s0-pins { - pins = "PG10", "PG11", "PG12", "PG13"; - function = "i2s"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts deleted file mode 100644 index 752ad05c8f83..000000000000 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-v3s-licheepi-zero.dts" - -#include - -/ { - model = "Lichee Pi Zero with Dock"; - compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", - "allwinner,sun8i-v3s"; - - aliases { - ethernet0 = &emac; - }; - - leds { - /* The LEDs use PG0~2 pins, which conflict with MMC1 */ - status = "disabled"; - }; -}; - -&emac { - allwinner,leds-active-low; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button-600 { - label = "Select"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Start"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts deleted file mode 100644 index 2e4587d26ce5..000000000000 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-v3s.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Lichee Pi Zero"; - compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue_led { - label = "licheepi:blue:usr"; - gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - }; - - green_led { - label = "licheepi:green:usr"; - gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - default-state = "on"; - }; - - red_led { - label = "licheepi:red:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi deleted file mode 100644 index 3b9a282c2746..000000000000 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ /dev/null @@ -1,621 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * Copyright (C) 2021 Tobias Schramm - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0"; - clocks = <&display_clocks CLK_MIXER0>, - <&ccu CLK_TCON0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-v3s-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext-osc32k"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-v3s-de2-clk"; - reg = <0x01000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-v3s-de2-mixer"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks 0>, - <&display_clocks 6>; - clock-names = "bus", - "mod"; - resets = <&display_clocks 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_mixer0>; - }; - }; - }; - }; - - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-v3s-system-control", - "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0xd0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - nmi_intc: interrupt-controller@1c000d0 { - compatible = "allwinner,sun8i-v3s-nmi", - "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c000d0 0x0c>; - interrupts = ; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-v3s-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-v3s-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, - <&ccu CLK_TCON0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - crypto@1c15000 { - compatible = "allwinner,sun8i-v3s-crypto", - "allwinner,sun8i-a33-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "ahb", "mod"; - dmas = <&dma 16>, <&dma 16>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_CE>; - reset-names = "ahb"; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-h3-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-v3s-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu0"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb0_phy"; - resets = <&ccu RST_USB_PHY0>; - reset-names = "usb0_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-v3s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@1c20400 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-v3-rtc"; - reg = <0x01c20400 0x54>; - interrupts = , - ; - clocks = <&osc32k>; - clock-output-names = "osc32k", "osc32k-out"; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-v3s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - /omit-if-no-ref/ - csi0_mclk_pin: csi0-mclk-pin { - pins = "PE20"; - function = "csi_mipi"; - }; - - /omit-if-no-ref/ - csi1_8bit_pins: csi1-8bit-pins { - pins = "PE0", "PE2", "PE3", "PE8", "PE9", - "PE10", "PE11", "PE12", "PE13", "PE14", - "PE15"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi1_mclk_pin: csi1-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB6", "PB7"; - function = "i2c0"; - }; - - /omit-if-no-ref/ - i2c1_pb_pins: i2c1-pb-pins { - pins = "PB8", "PB9"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c1_pe_pins: i2c1-pe-pins { - pins = "PE21", "PE22"; - function = "i2c1"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB8", "PB9"; - function = "uart0"; - }; - - uart2_pins: uart2-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-v3s-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-v3s-pwm", - "allwinner,sun7i-a20-pwm"; - reg = <0x01c21400 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x400>; - interrupts = ; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-v3s-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - - codec_analog: codec-analog@1c23000 { - compatible = "allwinner,sun8i-v3s-codec-analog"; - reg = <0x01c23000 0x4>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART2>; - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-v3s-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio_mux: mdio-mux { - compatible = "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - /* Only one MDIO is usable at the time */ - internal_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - }; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - csi1: camera@1cb4000 { - compatible = "allwinner,sun8i-v3s-csi"; - reg = <0x01cb4000 0x3000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts deleted file mode 100644 index 434871040aca..000000000000 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-r40.dtsi" -#include "sun8i-r40-cpu-opp.dtsi" - -#include - -/ { - model = "Banana Pi M2 Berry"; - compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; - - aliases { - ethernet0 = &gmac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-led { - label = "bananapi:red:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user-led { - label = "bananapi:green:user"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ - clocks = <&ccu CLK_OUTA>; - clock-names = "ext_clock"; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo3>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&clk_out_a_pin>; - vcc-pa-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo1>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo1>; -}; - -®_aldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -/* - * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same - * time, with the two being in sync, to be able to meet maximum power - * consumption during transmits. Since this is not really supported - * right now, just use the two as always on, and we will fix it later. - */ - -®_dldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; -}; - -®_dldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd2v5-sata"; -}; - -®_eldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd1v2-sata"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&ccu CLK_OUTA>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - /* TODO host wake line connected to PMIC GPIO pins */ - shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - max-speed = <1500000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts deleted file mode 100644 index c8ca8cb7f5c9..000000000000 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2015 Tyler Baker - * - * Tyler Baker - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include - -/ { - model = "Cubietech Cubieboard4"; - compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "cubieboard4:green:usr"; - gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ - }; - - led-1 { - label = "cubieboard4:red:usr"; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - }; - - vga-connector { - compatible = "vga-connector"; - label = "vga"; - ddc-i2c-bus = <&i2c3>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_dac_out>; - }; - }; - }; - - vga-dac { - compatible = "corpro,gm7123", "adi,adv7123"; - vdd-supply = <®_dcdc1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_dac_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_dac_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&de { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_cldo1>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_cldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc1_pins { - bias-pull-up; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - vcc-pa-supply = <®_ldo_io1>; - vcc-pb-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dc1sw>; - vcc-pe-supply = <®_eldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_ldo_io0>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pl-supply = <®_dldo2>; - vcc-pm-supply = <®_eldo3>; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc1sw: dc1sw { - regulator-name = "vcc-pd"; - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd0_rgb888_pins>; -}; - -&tcon0_out { - tcon0_out_vga: endpoint { - remote-endpoint = <&vga_dac_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts deleted file mode 100644 index 5c3580d712e4..000000000000 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include - -/ { - model = "Merrii A80 Optimus Board"; - compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - /* The LED names match those found on the board */ - led2 { - label = "optimus:led2:usr"; - gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; - }; - - led3 { - label = "optimus:led3:usr"; - gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ - }; - - led4 { - label = "optimus:led4:usr"; - gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&ehci2 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_cldo1>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_cldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc1_pins { - bias-pull-up; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - vcc-pa-supply = <®_ldo_io1>; - vcc-pb-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_ldo_io0>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pl-supply = <®_dldo2>; - vcc-pm-supply = <®_eldo3>; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - dc1sw { - /* unused */ - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy1 { - phy-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy2 { - phy-supply = <®_bldo4>; - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&usbphy3 { - phy-supply = <®_usb3_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi deleted file mode 100644 index 7d3f3300f431..000000000000 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ /dev/null @@ -1,1253 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x3>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x103>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - /* - * This clock is actually configurable from the PRCM address - * space. The external 24M oscillator can be turned off, and - * the clock switched to an internal 16M RC oscillator. Under - * normal operation there's no reason to do this, and the - * default is to use the external good one, so just model this - * as a fixed clock. Also it is not entirely clear if the - * osc24M mux in the PRCM affects the entire clock tree, which - * would also throw all the PLL clock rates off, or just the - * downstream clocks in the PRCM. - */ - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - /* - * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This serves as a placeholder for - * board dts files to specify the source. - */ - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: mii_phy_tx_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: gmac_int_tx_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@800030 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x00800030 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - - cpus_clk: clk@8001410 { - compatible = "allwinner,sun9i-a80-cpus-clk"; - reg = <0x08001410 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, - <&ccu CLK_PLL_PERIPH0>, - <&ccu CLK_PLL_AUDIO>; - clock-output-names = "cpus"; - }; - - ahbs: clk-ahbs { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&cpus_clk>; - clock-output-names = "ahbs"; - }; - - apbs: clk@800141c { - compatible = "allwinner,sun8i-a23-apb0-clk"; - reg = <0x0800141c 0x4>; - #clock-cells = <0>; - clocks = <&ahbs>; - clock-output-names = "apbs"; - }; - - apbs_gates: clk@8001428 { - compatible = "allwinner,sun9i-a80-apbs-gates-clk"; - reg = <0x08001428 0x4>; - #clock-cells = <1>; - clocks = <&apbs>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, - <6>, <7>, - <12>, <13>, - <16>, <17>, - <18>, <20>; - clock-output-names = "apbs_pio", "apbs_ir", - "apbs_timer", "apbs_rsb", - "apbs_uart", "apbs_1wire", - "apbs_i2c0", "apbs_i2c1", - "apbs_ps2_0", "apbs_ps2_1", - "apbs_dma", "apbs_i2s0", - "apbs_i2s1", "apbs_twd"; - }; - - r_1wire_clk: clk@8001450 { - reg = <0x08001450 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_1wire"; - }; - - r_ir_clk: clk@8001454 { - reg = <0x08001454 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_ir"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun9i-a80-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc@20000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - sram_b: sram@20000 { - /* 256 KiB secure SRAM at 0x20000 */ - compatible = "mmio-sram"; - reg = <0x00020000 0x40000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00020000 0x40000>; - - smp-sram@1000 { - /* - * This is checked by BROM to determine if - * cpu0 should jump to SMP entry vector - */ - compatible = "allwinner,sun9i-a80-smp-sram"; - reg = <0x1000 0x8>; - }; - }; - - gmac: ethernet@830000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x00830000 0x1054>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ccu RST_BUS_GMAC>; - reset-names = "stmmaceth"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ehci0: usb@a00000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a00000 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI0>; - resets = <&usb_clocks RST_USB0_HCI>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@a00400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a00400 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI0>, - <&usb_clocks CLK_USB_OHCI0>; - resets = <&usb_clocks RST_USB0_HCI>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy1: phy@a00800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a00800 0x4>; - clocks = <&usb_clocks CLK_USB0_PHY>; - clock-names = "phy"; - resets = <&usb_clocks RST_USB0_PHY>; - reset-names = "phy"; - status = "disabled"; - #phy-cells = <0>; - }; - - ehci1: usb@a01000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a01000 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI1>; - resets = <&usb_clocks RST_USB1_HCI>; - phys = <&usbphy2>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy2: phy@a01800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a01800 0x4>; - clocks = <&usb_clocks CLK_USB1_PHY>, - <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB1_HSIC>; - clock-names = "phy", - "hsic_12M", - "hsic_480M"; - resets = <&usb_clocks RST_USB1_PHY>, - <&usb_clocks RST_USB1_HSIC>; - reset-names = "phy", - "hsic"; - status = "disabled"; - #phy-cells = <0>; - /* usb1 is always used with HSIC */ - phy_type = "hsic"; - }; - - ehci2: usb@a02000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a02000 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI2>; - resets = <&usb_clocks RST_USB2_HCI>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@a02400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a02400 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI2>, - <&usb_clocks CLK_USB_OHCI2>; - resets = <&usb_clocks RST_USB2_HCI>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy3: phy@a02800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a02800 0x4>; - clocks = <&usb_clocks CLK_USB2_PHY>, - <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB2_HSIC>; - clock-names = "phy", - "hsic_12M", - "hsic_480M"; - resets = <&usb_clocks RST_USB2_PHY>, - <&usb_clocks RST_USB2_HSIC>; - reset-names = "phy", - "hsic"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb_clocks: clock@a08000 { - compatible = "allwinner,sun9i-a80-usb-clks"; - reg = <0x00a08000 0x8>; - clocks = <&ccu CLK_BUS_USB>, <&osc24M>; - clock-names = "bus", "hosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cpucfg@1700000 { - compatible = "allwinner,sun9i-a80-cpucfg"; - reg = <0x01700000 0x100>; - }; - - crypto: crypto@1c02000 { - compatible = "allwinner,sun9i-a80-crypto"; - reg = <0x01c02000 0x1000>; - interrupts = ; - resets = <&ccu RST_BUS_SS>; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "bus", "mod"; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ccu CLK_BUS_MMC>; - resets = <&ccu RST_BUS_MMC>; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; - }; - - gic: interrupt-controller@1c41000 { - compatible = "arm,gic-400"; - reg = <0x01c41000 0x1000>, - <0x01c42000 0x2000>, - <0x01c44000 0x2000>, - <0x01c46000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - cci: cci@1c90000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01c90000 0x1000>; - ranges = <0x0 0x01c90000 0x10000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - ; - }; - }; - - de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_SDRAM>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "dram", - "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - fe0: display-frontend@3100000 { - compatible = "allwinner,sun9i-a80-display-frontend"; - reg = <0x03100000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, - <&de_clocks CLK_DRAM_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_deu0: endpoint { - remote-endpoint = <&deu0_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@3140000 { - compatible = "allwinner,sun9i-a80-display-frontend"; - reg = <0x03140000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, - <&de_clocks CLK_DRAM_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - reg = <1>; - - fe1_out_deu1: endpoint { - remote-endpoint = <&deu1_in_fe1>; - }; - }; - }; - }; - - be0: display-backend@3200000 { - compatible = "allwinner,sun9i-a80-display-backend"; - reg = <0x03200000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, - <&de_clocks CLK_DRAM_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_deu0: endpoint@0 { - reg = <0>; - remote-endpoint = <&deu0_out_be0>; - }; - - be0_in_deu1: endpoint@1 { - reg = <1>; - remote-endpoint = <&deu1_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - be1: display-backend@3240000 { - compatible = "allwinner,sun9i-a80-display-backend"; - reg = <0x03240000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, - <&de_clocks CLK_DRAM_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_deu0: endpoint@0 { - reg = <0>; - remote-endpoint = <&deu0_out_be1>; - }; - - be1_in_deu1: endpoint@1 { - reg = <1>; - remote-endpoint = <&deu1_out_be1>; - }; - }; - - be1_out: port@1 { - reg = <1>; - - be1_out_drc1: endpoint { - remote-endpoint = <&drc1_in_be1>; - }; - }; - }; - }; - - deu0: deu@3300000 { - compatible = "allwinner,sun9i-a80-deu"; - reg = <0x03300000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DEU0>, - <&de_clocks CLK_IEP_DEU0>, - <&de_clocks CLK_DRAM_DEU0>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DEU0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - deu0_in: port@0 { - reg = <0>; - - deu0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_deu0>; - }; - }; - - deu0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - deu0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_deu0>; - }; - - deu0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_deu0>; - }; - }; - }; - }; - - deu1: deu@3340000 { - compatible = "allwinner,sun9i-a80-deu"; - reg = <0x03340000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DEU1>, - <&de_clocks CLK_IEP_DEU1>, - <&de_clocks CLK_DRAM_DEU1>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DEU1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - deu1_in: port@0 { - reg = <0>; - - deu1_in_fe1: endpoint { - remote-endpoint = <&fe1_out_deu1>; - }; - }; - - deu1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - deu1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_deu1>; - }; - - deu1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_deu1>; - }; - }; - }; - }; - - drc0: drc@3400000 { - compatible = "allwinner,sun9i-a80-drc"; - reg = <0x03400000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DRC0>, - <&de_clocks CLK_IEP_DRC0>, - <&de_clocks CLK_DRAM_DRC0>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DRC0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - reg = <1>; - - drc0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; - - drc1: drc@3440000 { - compatible = "allwinner,sun9i-a80-drc"; - reg = <0x03440000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DRC1>, - <&de_clocks CLK_IEP_DRC1>, - <&de_clocks CLK_DRAM_DRC1>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DRC1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc1_in: port@0 { - reg = <0>; - - drc1_in_be1: endpoint { - remote-endpoint = <&be1_out_drc1>; - }; - }; - - drc1_out: port@1 { - reg = <1>; - - drc1_out_tcon1: endpoint { - remote-endpoint = <&tcon1_in_drc1>; - }; - }; - }; - }; - - tcon0: lcd-controller@3c00000 { - compatible = "allwinner,sun9i-a80-tcon-lcd"; - reg = <0x03c00000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; - clock-names = "ahb", "tcon-ch0"; - resets = <&ccu RST_BUS_LCD0>, - <&ccu RST_BUS_EDP>, - <&ccu RST_BUS_LVDS>; - reset-names = "lcd", - "edp", - "lvds"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_drc0: endpoint { - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - tcon1: lcd-controller@3c10000 { - compatible = "allwinner,sun9i-a80-tcon-tv"; - reg = <0x03c10000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; - reset-names = "lcd", "edp"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - reg = <0>; - - tcon1_in_drc1: endpoint { - remote-endpoint = <&drc1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - reg = <1>; - }; - }; - }; - - ccu: clock@6000000 { - compatible = "allwinner,sun9i-a80-ccu"; - reg = <0x06000000 0x800>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - timer@6000c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x06000c00 0xa0>; - interrupts = , - , - , - , - , - ; - - clocks = <&osc24M>; - }; - - wdt: watchdog@6000ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x06000ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - pio: pinctrl@6000800 { - compatible = "allwinner,sun9i-a80-pinctrl"; - reg = <0x06000800 0x400>; - interrupts = , - , - , - , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", - "PA7", "PA8", "PA9", "PA10", "PA12", - "PA13", "PA15", "PA16", "PA17"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c3_pins: i2c3-pins { - pins = "PG10", "PG11"; - function = "i2c3"; - }; - - lcd0_rgb888_pins: lcd0-rgb888-pins { - pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD6", "PD7", - "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD14", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1" ,"PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1" ,"PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH12", "PH13"; - function = "uart0"; - }; - - uart4_pins: uart4-pins { - pins = "PG12", "PG13", "PG14", "PG15"; - function = "uart4"; - }; - }; - - uart0: serial@7000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@7000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@7000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@7000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@7001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@7001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - i2c0: i2c@7002800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@7002c00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@7003000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@7003400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@7003800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C4>; - resets = <&ccu RST_BUS_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_wdt: watchdog@8001000 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x08001000 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - prcm@8001400 { - compatible = "allwinner,sun9i-a80-prcm"; - reg = <0x08001400 0x200>; - }; - - apbs_rst: reset@80014b0 { - reg = <0x080014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@80015a0 { - compatible = "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x080015a0 0xc>; - interrupts = ; - }; - - r_ir: ir@8002000 { - compatible = "allwinner,sun6i-a31-ir"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_pins>; - clocks = <&apbs_gates 1>, <&r_ir_clk>; - clock-names = "apb", "ir"; - resets = <&apbs_rst 1>; - reg = <0x08002000 0x40>; - status = "disabled"; - }; - - r_uart: serial@8002800 { - compatible = "snps,dw-apb-uart"; - reg = <0x08002800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apbs_gates 4>; - resets = <&apbs_rst 4>; - status = "disabled"; - }; - - r_pio: pinctrl@8002c00 { - compatible = "allwinner,sun9i-a80-r-pinctrl"; - reg = <0x08002c00 0x400>; - interrupts = , - ; - clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_ir_pins: r-ir-pins { - pins = "PL6"; - function = "s_cir_rx"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PN0", "PN1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - }; - - r_rsb: rsb@8003400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x08003400 0x400>; - interrupts = ; - clocks = <&apbs_gates 3>; - clock-frequency = <3000000>; - resets = <&apbs_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts deleted file mode 100644 index 43896723a994..000000000000 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2018 Icenowy Zheng - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -#include - -/ { - model = "Lichee Pi Nano"; - compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; - - aliases { - mmc0 = &mmc0; - serial0 = &uart0; - spi0 = &spi0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - disable-wp; - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pc_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&otg_sram { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pe_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi deleted file mode 100644 index 3c61d59ab5f8..000000000000 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2018 Icenowy Zheng - * Copyright 2018 Mesih Kilinc - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - clocks { - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@1c00000 { - compatible = "allwinner,suniv-f1c100s-system-control", - "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,suniv-f1c100s-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,suniv-f1c100s-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,suniv-f1c100s-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,suniv-f1c100s-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <23>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,suniv-f1c100s-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <24>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,suniv-f1c100s-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <26>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - compatible = "allwinner,suniv-f1c100s-usb-phy"; - reg = <0x01c13400 0x10>; - reg-names = "phy_ctrl"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb0_phy"; - resets = <&ccu RST_USB_PHY0>; - reset-names = "usb0_reset"; - #phy-cells = <1>; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,suniv-f1c100s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,suniv-f1c100s-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,suniv-f1c100s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <38>, <39>, <40>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - }; - - /omit-if-no-ref/ - i2c0_pd_pins: i2c0-pd-pins { - pins = "PD0", "PD12"; - function = "i2c0"; - }; - - spi0_pc_pins: spi0-pc-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - - uart0_pe_pins: uart0-pe-pins { - pins = "PE0", "PE1"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pa_pins: uart1-pa-pins { - pins = "PA2", "PA3"; - function = "uart1"; - }; - }; - - i2c0: i2c@1c27000 { - compatible = "allwinner,suniv-f1c100s-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c27000 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1c27400 { - compatible = "allwinner,suniv-f1c100s-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c27400 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1c27800 { - compatible = "allwinner,suniv-f1c100s-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c27800 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer@1c20c00 { - compatible = "allwinner,suniv-f1c100s-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <13>, <14>, <15>; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20ca0 { - compatible = "allwinner,suniv-f1c100s-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = <16>; - clocks = <&osc32k>; - }; - - pwm: pwm@1c21000 { - compatible = "allwinner,suniv-f1c100s-pwm", - "allwinner,sun7i-a20-pwm"; - reg = <0x01c21000 0x400>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@1c22c00 { - compatible = "allwinner,suniv-f1c100s-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x01c22c00 0x400>; - clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&ccu RST_BUS_IR>; - interrupts = <6>; - status = "disabled"; - }; - - lradc: lradc@1c23400 { - compatible = "allwinner,suniv-f1c100s-lradc", - "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01c23400 0x400>; - interrupts = <22>; - status = "disabled"; - }; - - uart0: serial@1c25000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c25400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c25800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts deleted file mode 100644 index 2d2a3f026df3..000000000000 --- a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Arm Ltd, - * based on work: - * Copyright 2022 Icenowy Zheng - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -#include - -/ { - model = "Lctech Pi F1C200s"; - compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", - "allwinner,suniv-f1c100s"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - disable-wp; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pc_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pa_pins>; - status = "okay"; -}; - -/* - * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected - * to Vin, which supplies the board. Host mode works (if the board is powered - * otherwise), but peripheral is probably the intention. - */ -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts deleted file mode 100644 index 184c245041a6..000000000000 --- a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Icenowy Zheng - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -#include -#include - -/ { - model = "Popcorn Computer PopStick v1.1"; - compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick", - "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */ - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ - bus-width = <4>; - disable-wp; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pc_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pe_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi deleted file mode 100644 index 493d32357e4e..000000000000 --- a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Sunplus SP7021 - * - * Copyright (C) 2021 Sunplus Technology Co. - */ - -#include "sunplus-sp7021.dtsi" -#include - -/ { - compatible = "sunplus,sp7021-achip", "sunplus,sp7021"; - model = "Sunplus SP7021 (CA7)"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <931000000>; - }; - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <931000000>; - }; - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clock-frequency = <931000000>; - }; - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clock-frequency = <931000000>; - }; - }; - - gic: interrupt-controller@9f101000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x9f101000 0x1000>, - <0x9f102000 0x2000>, - <0x9f104000 0x2000>, - <0x9f106000 0x2000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = ; - arm,cpu-registers-not-fw-configured; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - soc@9c000000 { - intc: interrupt-controller@780 { - interrupt-parent = <&gic>; - interrupts = , /* EXT_INT0 */ - ; /* EXT_INT1 */ - }; - }; -}; diff --git a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts deleted file mode 100644 index d5c5ffc20565..000000000000 --- a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Sunplus SP7021 Demo V3 SBC board - * - * Copyright (C) Sunplus Technology Co. - */ - -/dts-v1/; - -#include "sunplus-sp7021-achip.dtsi" - -/ { - compatible = "sunplus,sp7021-demo-v3", "sunplus,sp7021"; - model = "Sunplus SP7021/CA7/Demo_V3"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; -}; diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus-sp7021.dtsi deleted file mode 100644 index ae9bbe0320b8..000000000000 --- a/arch/arm/boot/dts/sunplus-sp7021.dtsi +++ /dev/null @@ -1,307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Sunplus SP7021 - * - * Copyright (C) 2021 Sunplus Technology Co. - */ - -#include -#include -#include -#include -#include - -#define XTAL 27000000 - -/ { - compatible = "sunplus,sp7021"; - model = "Sunplus SP7021"; - - clocks { - extclk: osc0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - clock-output-names = "extclk"; - }; - }; - - soc@9c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x9c000000 0x400000>; - interrupt-parent = <&intc>; - - clkc: clock-controller@4 { - compatible = "sunplus,sp7021-clkc"; - reg = <0x4 0x28>, - <0x200 0x44>, - <0x268 0x04>; - clocks = <&extclk>; - #clock-cells = <1>; - }; - - intc: interrupt-controller@780 { - compatible = "sunplus,sp7021-intc"; - reg = <0x780 0x80>, <0xa80 0x80>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - otp: otp@af00 { - compatible = "sunplus,sp7021-ocotp"; - reg = <0xaf00 0x34>, <0xaf80 0x58>; - reg-names = "hb_gpio", "otprx"; - clocks = <&clkc CLK_OTPRX>; - resets = <&rstc RST_OTPRX>; - #address-cells = <1>; - #size-cells = <1>; - - therm_calib: thermal-calibration@14 { - reg = <0x14 0x3>; - }; - disc_vol: disconnect-voltage@18 { - reg = <0x18 0x2>; - }; - mac_addr0: mac-address0@34 { - reg = <0x34 0x6>; - }; - mac_addr1: mac-address1@3a { - reg = <0x3a 0x6>; - }; - }; - - pctl: pinctrl@100 { - compatible = "sunplus,sp7021-pctl"; - reg = <0x100 0x100>, - <0x300 0x100>, - <0x32e4 0x1C>, - <0x80 0x20>; - reg-names = "moon2", "gpioxt", "first", "moon1"; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clkc CLK_GPIO>; - resets = <&rstc RST_GPIO>; - - emac_pins: pinmux-emac-pins { - sunplus,pins = < - SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) - SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) - SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) - SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) - SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) - SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) - SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) - SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) - SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) - SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0) - SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0) - SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0) - SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0) - SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0) - SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0) - SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0) - SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0) - >; - sunplus,zerofunc = < - MUXF_L2SW_LED_FLASH0 - MUXF_L2SW_LED_FLASH1 - MUXF_L2SW_LED_ON0 - MUXF_L2SW_LED_ON1 - MUXF_DAISY_MODE - >; - }; - - emmc_pins: pinmux-emmc-pins { - function = "CARD0_EMMC"; - groups = "CARD0_EMMC"; - }; - - leds_pins: pinmux-leds-pins { - sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >; - }; - - sdcard_pins: pinmux-sdcard-pins { - function = "SD_CARD"; - groups = "SD_CARD"; - sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; - }; - - spi0_pins: pinmux-spi0-pins { - sunplus,pins = < - SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0) - SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0) - SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0) - SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0) - SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0) - >; - }; - - uart0_pins: pinmux-uart0-pins { - function = "UA0"; - groups = "UA0"; - }; - - uart1_pins: pinmux-uart1-pins { - sunplus,pins = < - SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0) - SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0) - >; - }; - - uart2_pins: pinmux-uart2-pins { - sunplus,pins = < - SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0) - SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0) - SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0) - SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0) - >; - }; - - uart4_pins: pinmux-uart4-pins { - sunplus,pins = < - SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0) - SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0) - SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0) - SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0) - >; - }; - }; - - rstc: reset@54 { - compatible = "sunplus,sp7021-reset"; - reg = <0x54 0x28>; - #reset-cells = <1>; - }; - - rtc: rtc@3a00 { - compatible = "sunplus,sp7021-rtc"; - reg = <0x3a00 0x80>; - reg-names = "rtc"; - clocks = <&clkc CLK_RTC>; - resets = <&rstc RST_RTC>; - interrupts = <163 IRQ_TYPE_EDGE_RISING>; - }; - - spi_controller0: spi@2d80 { - compatible = "sunplus,sp7021-spi"; - reg = <0x2d80 0x80>, <0x2e00 0x80>; - reg-names = "master", "slave"; - interrupts = <144 IRQ_TYPE_LEVEL_HIGH>, - <146 IRQ_TYPE_LEVEL_HIGH>, - <145 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dma_w", "master_risc", "slave_risc"; - clocks = <&clkc CLK_SPI_COMBO_0>; - resets = <&rstc RST_SPI_COMBO_0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>, - <&pctl 28 GPIO_ACTIVE_LOW>; - }; - - spi_controller1: spi@f480 { - compatible = "sunplus,sp7021-spi"; - reg = <0xf480 0x80>, <0xf500 0x80>; - reg-names = "master", "slave"; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>, - <69 IRQ_TYPE_LEVEL_HIGH>, - <68 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dma_w", "master_risc", "slave_risc"; - clocks = <&clkc CLK_SPI_COMBO_1>; - resets = <&rstc RST_SPI_COMBO_1>; - status = "disabled"; - }; - - spi_controller2: spi@f600 { - compatible = "sunplus,sp7021-spi"; - reg = <0xf600 0x80>, <0xf680 0x80>; - reg-names = "master", "slave"; - interrupts = <70 IRQ_TYPE_LEVEL_HIGH>, - <72 IRQ_TYPE_LEVEL_HIGH>, - <71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dma_w", "master_risc", "slave_risc"; - clocks = <&clkc CLK_SPI_COMBO_2>; - resets = <&rstc RST_SPI_COMBO_2>; - status = "disabled"; - }; - - spi_controller3: spi@f780 { - compatible = "sunplus,sp7021-spi"; - reg = <0xf780 0x80>, <0xf800 0x80>; - reg-names = "master", "slave"; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>, - <75 IRQ_TYPE_LEVEL_HIGH>, - <74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dma_w", "master_risc", "slave_risc"; - clocks = <&clkc CLK_SPI_COMBO_3>; - resets = <&rstc RST_SPI_COMBO_3>; - status = "disabled"; - }; - - uart0: serial@900 { - compatible = "sunplus,sp7021-uart"; - reg = <0x900 0x80>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLK_UA0>; - resets = <&rstc RST_UA0>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - }; - - uart1: serial@980 { - compatible = "sunplus,sp7021-uart"; - reg = <0x980 0x80>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLK_UA1>; - resets = <&rstc RST_UA1>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; - }; - - uart2: serial@800 { - compatible = "sunplus,sp7021-uart"; - reg = <0x800 0x80>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLK_UA2>; - resets = <&rstc RST_UA2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; - }; - - uart3: serial@880 { - compatible = "sunplus,sp7021-uart"; - reg = <0x880 0x80>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLK_UA3>; - resets = <&rstc RST_UA3>; - status = "disabled"; - }; - - uart4: serial@8780 { - compatible = "sunplus,sp7021-uart"; - reg = <0x8780 0x80>; - interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLK_UA4>; - resets = <&rstc RST_UA4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - system-led { - label = "system-led"; - gpios = <&pctl 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile new file mode 100644 index 000000000000..868f2ea0c127 --- /dev/null +++ b/arch/arm/boot/dts/sunplus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi new file mode 100644 index 000000000000..493d32357e4e --- /dev/null +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Sunplus SP7021 + * + * Copyright (C) 2021 Sunplus Technology Co. + */ + +#include "sunplus-sp7021.dtsi" +#include + +/ { + compatible = "sunplus,sp7021-achip", "sunplus,sp7021"; + model = "Sunplus SP7021 (CA7)"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <931000000>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <931000000>; + }; + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + clock-frequency = <931000000>; + }; + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + clock-frequency = <931000000>; + }; + }; + + gic: interrupt-controller@9f101000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x9f101000 0x1000>, + <0x9f102000 0x2000>, + <0x9f104000 0x2000>, + <0x9f106000 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = ; + arm,cpu-registers-not-fw-configured; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + soc@9c000000 { + intc: interrupt-controller@780 { + interrupt-parent = <&gic>; + interrupts = , /* EXT_INT0 */ + ; /* EXT_INT1 */ + }; + }; +}; diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts new file mode 100644 index 000000000000..d5c5ffc20565 --- /dev/null +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Sunplus SP7021 Demo V3 SBC board + * + * Copyright (C) Sunplus Technology Co. + */ + +/dts-v1/; + +#include "sunplus-sp7021-achip.dtsi" + +/ { + compatible = "sunplus,sp7021-demo-v3", "sunplus,sp7021"; + model = "Sunplus SP7021/CA7/Demo_V3"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi new file mode 100644 index 000000000000..ae9bbe0320b8 --- /dev/null +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Sunplus SP7021 + * + * Copyright (C) 2021 Sunplus Technology Co. + */ + +#include +#include +#include +#include +#include + +#define XTAL 27000000 + +/ { + compatible = "sunplus,sp7021"; + model = "Sunplus SP7021"; + + clocks { + extclk: osc0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "extclk"; + }; + }; + + soc@9c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x9c000000 0x400000>; + interrupt-parent = <&intc>; + + clkc: clock-controller@4 { + compatible = "sunplus,sp7021-clkc"; + reg = <0x4 0x28>, + <0x200 0x44>, + <0x268 0x04>; + clocks = <&extclk>; + #clock-cells = <1>; + }; + + intc: interrupt-controller@780 { + compatible = "sunplus,sp7021-intc"; + reg = <0x780 0x80>, <0xa80 0x80>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + otp: otp@af00 { + compatible = "sunplus,sp7021-ocotp"; + reg = <0xaf00 0x34>, <0xaf80 0x58>; + reg-names = "hb_gpio", "otprx"; + clocks = <&clkc CLK_OTPRX>; + resets = <&rstc RST_OTPRX>; + #address-cells = <1>; + #size-cells = <1>; + + therm_calib: thermal-calibration@14 { + reg = <0x14 0x3>; + }; + disc_vol: disconnect-voltage@18 { + reg = <0x18 0x2>; + }; + mac_addr0: mac-address0@34 { + reg = <0x34 0x6>; + }; + mac_addr1: mac-address1@3a { + reg = <0x3a 0x6>; + }; + }; + + pctl: pinctrl@100 { + compatible = "sunplus,sp7021-pctl"; + reg = <0x100 0x100>, + <0x300 0x100>, + <0x32e4 0x1C>, + <0x80 0x20>; + reg-names = "moon2", "gpioxt", "first", "moon1"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clkc CLK_GPIO>; + resets = <&rstc RST_GPIO>; + + emac_pins: pinmux-emac-pins { + sunplus,pins = < + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) + SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0) + SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0) + SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0) + >; + sunplus,zerofunc = < + MUXF_L2SW_LED_FLASH0 + MUXF_L2SW_LED_FLASH1 + MUXF_L2SW_LED_ON0 + MUXF_L2SW_LED_ON1 + MUXF_DAISY_MODE + >; + }; + + emmc_pins: pinmux-emmc-pins { + function = "CARD0_EMMC"; + groups = "CARD0_EMMC"; + }; + + leds_pins: pinmux-leds-pins { + sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >; + }; + + sdcard_pins: pinmux-sdcard-pins { + function = "SD_CARD"; + groups = "SD_CARD"; + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + + spi0_pins: pinmux-spi0-pins { + sunplus,pins = < + SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0) + SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0) + SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0) + SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0) + SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0) + >; + }; + + uart0_pins: pinmux-uart0-pins { + function = "UA0"; + groups = "UA0"; + }; + + uart1_pins: pinmux-uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0) + SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0) + >; + }; + + uart2_pins: pinmux-uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0) + SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0) + SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0) + SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0) + >; + }; + + uart4_pins: pinmux-uart4-pins { + sunplus,pins = < + SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0) + SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0) + SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0) + SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0) + >; + }; + }; + + rstc: reset@54 { + compatible = "sunplus,sp7021-reset"; + reg = <0x54 0x28>; + #reset-cells = <1>; + }; + + rtc: rtc@3a00 { + compatible = "sunplus,sp7021-rtc"; + reg = <0x3a00 0x80>; + reg-names = "rtc"; + clocks = <&clkc CLK_RTC>; + resets = <&rstc RST_RTC>; + interrupts = <163 IRQ_TYPE_EDGE_RISING>; + }; + + spi_controller0: spi@2d80 { + compatible = "sunplus,sp7021-spi"; + reg = <0x2d80 0x80>, <0x2e00 0x80>; + reg-names = "master", "slave"; + interrupts = <144 IRQ_TYPE_LEVEL_HIGH>, + <146 IRQ_TYPE_LEVEL_HIGH>, + <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_0>; + resets = <&rstc RST_SPI_COMBO_0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>, + <&pctl 28 GPIO_ACTIVE_LOW>; + }; + + spi_controller1: spi@f480 { + compatible = "sunplus,sp7021-spi"; + reg = <0xf480 0x80>, <0xf500 0x80>; + reg-names = "master", "slave"; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>, + <69 IRQ_TYPE_LEVEL_HIGH>, + <68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_1>; + resets = <&rstc RST_SPI_COMBO_1>; + status = "disabled"; + }; + + spi_controller2: spi@f600 { + compatible = "sunplus,sp7021-spi"; + reg = <0xf600 0x80>, <0xf680 0x80>; + reg-names = "master", "slave"; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>, + <72 IRQ_TYPE_LEVEL_HIGH>, + <71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_2>; + resets = <&rstc RST_SPI_COMBO_2>; + status = "disabled"; + }; + + spi_controller3: spi@f780 { + compatible = "sunplus,sp7021-spi"; + reg = <0xf780 0x80>, <0xf800 0x80>; + reg-names = "master", "slave"; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_3>; + resets = <&rstc RST_SPI_COMBO_3>; + status = "disabled"; + }; + + uart0: serial@900 { + compatible = "sunplus,sp7021-uart"; + reg = <0x900 0x80>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA0>; + resets = <&rstc RST_UA0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + }; + + uart1: serial@980 { + compatible = "sunplus,sp7021-uart"; + reg = <0x980 0x80>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA1>; + resets = <&rstc RST_UA1>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; + }; + + uart2: serial@800 { + compatible = "sunplus,sp7021-uart"; + reg = <0x800 0x80>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA2>; + resets = <&rstc RST_UA2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; + }; + + uart3: serial@880 { + compatible = "sunplus,sp7021-uart"; + reg = <0x880 0x80>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA3>; + resets = <&rstc RST_UA3>; + status = "disabled"; + }; + + uart4: serial@8780 { + compatible = "sunplus,sp7021-uart"; + reg = <0x8780 0x80>; + interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA4>; + resets = <&rstc RST_UA4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "disabled"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + system-led { + label = "system-led"; + gpios = <&pctl 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi deleted file mode 100644 index 235994a4a2eb..000000000000 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Chen-Yu Tsai - */ - -#include "sunxi-bananapi-m2-plus.dtsi" - -/ { - /* - * Bananapi M2+ v1.2 uses a GPIO line to change the effective - * resistance on the CPU regulator's feedback pin. - */ - reg_vdd_cpux: vdd-cpux { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1108475>; - regulator-max-microvolt = <1308475>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ - gpios-states = <0x1>; - states = <1108475 0>, <1308475 1>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu1 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu2 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu3 { - cpu-supply = <®_vdd_cpux>; -}; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi deleted file mode 100644 index 1d1d127cf38f..000000000000 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "bananapi-m2-plus:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - switch-4 { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <1500000>; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - usb0_vbus-supply = <®_usb0_vbus>; - /* USB host VBUS is on as long as VCC-IO is on */ - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi deleted file mode 100644 index d8e5826fb3de..000000000000 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/* - * sunxi boards common regulator (ahci target power supply, usb-vbus) code - * - * Copyright 2014 - Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - reg_ahci_5v: ahci-5v { - compatible = "regulator-fixed"; - regulator-name = "ahci-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb2_vbus: usb2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb2-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_vcc3v0: vcc3v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; diff --git a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi deleted file mode 100644 index e9bc749488bb..000000000000 --- a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -// Copyright (C) 2022 Arm Ltd. -/* - * Common peripherals and configurations for MangoPi MQ-R boards. - */ - -#include -#include - -/ { - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ - }; - }; - - /* board wide 5V supply directly from the USB-C socket */ - reg_vcc5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - /* SY8008 DC/DC regulator on the board */ - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v>; - }; - - /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ - reg_vcc_core: regulator-core { - compatible = "regulator-fixed"; - regulator-name = "vcc-core"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - vin-supply = <®_vcc5v>; - }; - - /* XC6206 LDO on the board */ - reg_avdd2v8: regulator-avdd { - compatible = "regulator-fixed"; - regulator-name = "avdd2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <®_3v3>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ - }; -}; - -&dcxo { - clock-frequency = <24000000>; -}; - -&ehci1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - vmmc-supply = <®_3v3>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - vmmc-supply = <®_3v3>; - non-removable; - bus-width = <4>; - mmc-pwrseq = <&wifi_pwrseq>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pb-supply = <®_3v3>; - vcc-pd-supply = <®_3v3>; - vcc-pe-supply = <®_avdd2v8>; - vcc-pf-supply = <®_3v3>; - vcc-pg-supply = <®_3v3>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pb_pins>; - status = "okay"; -}; - -/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi deleted file mode 100644 index 60804b0e6c56..000000000000 --- a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * DTSI for Emlid Neutis SoMs. - * - * Copyright (C) 2019 Georgii Staroselskii - */ - -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ - post-power-on-delay-ms = <200>; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpux>; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - status = "okay"; -}; - - -&de { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ - device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "LINEIN", "Line In", - "MIC1", "Mic", - "MIC2", "Mic", - "Mic", "MBIAS"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi deleted file mode 100644 index ade1cd50e445..000000000000 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ /dev/null @@ -1,979 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0-hdmi"; - clocks = <&display_clocks CLK_MIXER0>, - <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - - framebuffer-tve { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer1-lcd1-tve"; - clocks = <&display_clocks CLK_MIXER1>, - <&ccu CLK_TVE>; - status = "disabled"; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext_osc32k"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-h3-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges; - ranges; - - display_clocks: clock@1000000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-h3-de2-mixer-0"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_mixer0>; - }; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-h3-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-h3-tcon-tv", - "allwinner,sun8i-a83t-tcon-tv"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON0>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - }; - }; - }; - }; - - mmc0: mmc@1c0f000 { - /* compatible and clocks are in per SoC .dtsi file */ - reg = <0x01c0f000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - /* compatible and clocks are in per SoC .dtsi file */ - reg = <0x01c10000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - /* compatible and clocks are in per SoC .dtsi file */ - reg = <0x01c11000 0x1000>; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sid: eeprom@1c14000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x1c14000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@34 { - reg = <0x34 4>; - }; - }; - - msgbox: mailbox@1c17000 { - compatible = "allwinner,sun8i-h3-msgbox", - "allwinner,sun6i-a31-msgbox"; - reg = <0x01c17000 0x1000>; - clocks = <&ccu CLK_BUS_MSGBOX>; - resets = <&ccu RST_BUS_MSGBOX>; - interrupts = ; - #mbox-cells = <1>; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-h3-musb"; - reg = <0x01c19000 0x400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-h3-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>, - <0x01c1c800 0x4>, - <0x01c1d800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1b400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@1c1c000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@1c1c400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@1c1d000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1d000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@1c1d400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1d400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01c20800 0x400>; - interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - csi_pins: csi-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", - "PE6", "PE7", "PE8", "PE9", "PE10", - "PE11"; - function = "csi"; - }; - - emac_rgmii_pins: emac-rgmii-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD7", "PD8", "PD9", "PD10", - "PD12", "PD13", "PD15", "PD16", "PD17"; - function = "emac"; - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PA11", "PA12"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PA18", "PA19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PE12", "PE13"; - function = "i2c2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PA17"; - function = "spdif"; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PA15", "PA16", "PA14", "PA13"; - function = "spi1"; - }; - - uart0_pa_pins: uart0-pa-pins { - pins = "PA4", "PA5"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - uart2_pins: uart2-pins { - pins = "PA0", "PA1"; - function = "uart2"; - }; - - uart2_rts_cts_pins: uart2-rts-cts-pins { - pins = "PA2", "PA3"; - function = "uart2"; - }; - - uart3_pins: uart3-pins { - pins = "PA13", "PA14"; - function = "uart3"; - }; - - uart3_rts_cts_pins: uart3-rts-cts-pins { - pins = "PA15", "PA16"; - function = "uart3"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-a23-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-h3-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio-mux { - compatible = "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - /* Only one MDIO is usable at the time */ - internal_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - - external_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - mbus: dram-controller@1c62000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01c62000 0x1000>, - <0x01c63000 0x1000>; - reg-names = "mbus", "dram"; - clocks = <&ccu CLK_MBUS>, - <&ccu CLK_DRAM>, - <&ccu CLK_BUS_DRAM>; - clock-names = "mbus", "dram", "bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x40000000 0xc0000000>; - #interconnect-cells = <1>; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c69000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_BUS_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>; - dma-names = "tx"; - status = "disabled"; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-h3-pwm"; - reg = <0x01c21400 0x8>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - resets = <&ccu RST_BUS_I2S0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - dmas = <&dma 4>, <&dma 4>; - resets = <&ccu RST_BUS_I2S1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s2: i2s@1c22800 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-i2s"; - reg = <0x01c22800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - dmas = <&dma 27>; - resets = <&ccu RST_BUS_I2S2>; - dma-names = "tx"; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - csi: camera@1cb0000 { - compatible = "allwinner,sun8i-h3-csi"; - reg = <0x01cb0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_pins>; - status = "disabled"; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun8i-h3-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; - clock-names = "iahb", "isfr", "tmds", "cec"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-h3-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_PLL_VIDEO>; - clock-names = "bus", "mod", "pll-0"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - rtc: rtc@1f00000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01f00000 0x400>; - interrupt-parent = <&r_intc>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun8i-h3-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - r_ccu: clock@1f01400 { - compatible = "allwinner,sun8i-h3-r-ccu"; - reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - codec_analog: codec-analog@1f015c0 { - compatible = "allwinner,sun8i-h3-codec-analog"; - reg = <0x01f015c0 0x4>; - }; - - ir: ir@1f02000 { - compatible = "allwinner,sun6i-a31-ir"; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; - interrupts = ; - reg = <0x01f02000 0x400>; - status = "disabled"; - }; - - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01f02400 0x400>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pins>; - clocks = <&r_ccu CLK_APB0_I2C>; - resets = <&r_ccu RST_APB0_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_uart: serial@1f02800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01f02800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&r_ccu CLK_APB0_UART>; - resets = <&r_ccu RST_APB0_UART>; - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins>; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-h3-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_ir_rx_pin: r-ir-rx-pin { - pins = "PL11"; - function = "s_cir_rx"; - }; - - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - - r_pwm_pin: r-pwm-pin { - pins = "PL10"; - function = "s_pwm"; - }; - - r_uart_pins: r-uart-pins { - pins = "PL2", "PL3"; - function = "s_uart"; - }; - }; - - r_pwm: pwm@1f03800 { - compatible = "allwinner,sun8i-h3-pwm"; - reg = <0x01f03800 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&r_pwm_pin>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi deleted file mode 100644 index 0d002f83a259..000000000000 --- a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi deleted file mode 100644 index 89731bb34c6b..000000000000 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Chen-Yu Tsai - */ - -#include -#include - -/ { - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "librecomputer:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status_led { - label = "librecomputer:blue:status"; - gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - wakeup-source; - }; - }; - - reg_vcc1v2: vcc1v2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - enable-active-high; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v0>; - }; - - /* This represents the board's 5V input */ - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - enable-active-high; - }; - - reg_vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc3v3>; - gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ - }; - - reg_vdd_cpux: vdd-cpux { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - enable-active-high; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu1 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu2 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu3 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc_io>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc_io>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - /* VBUS on USB ports are always on */ - usb0_vbus-supply = <®_vcc5v0>; - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - usb3_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi deleted file mode 100644 index 50d328c2a84d..000000000000 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Chen-Yu Tsai - -#include -#include - -/ { - aliases { - serial0 = &uart0; - spi0 = &spi0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "d"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status_led { - label = "librecomputer:blue:status"; - gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - }; - - /* This represents the board's 5V input */ - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - enable-active-high; - }; - - reg_vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-io"; - /* This is simply a MOSFET switch */ - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc3v3>; - gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ - }; - - reg_vcc_usbwifi: vcc-usbwifi { - compatible = "regulator-fixed"; - regulator-name = "vcc-usbwifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v0>; - gpio = <&pio 6 4 GPIO_ACTIVE_HIGH>; /* PG4 */ - enable-active-high; - }; - - reg_vdd_cpux: vdd-cpux { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - enable-active-high; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu1 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu2 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu3 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc_io>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_vcc_io>; - vcc-pc-supply = <®_vcc_io>; - vcc-pd-supply = <®_vcc_io>; - vcc-pe-supply = <®_vcc_io>; - vcc-pf-supply = <®_vcc_io>; - vcc-pg-supply = <®_vcc_io>; -}; - -&r_pio { - vcc-pl-supply = <®_vcc3v3>; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc_usbwifi>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi deleted file mode 100644 index 117198c52e1f..000000000000 --- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "sunxi-common-regulators.dtsi" - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/synaptics/Makefile b/arch/arm/boot/dts/synaptics/Makefile new file mode 100644 index 000000000000..0ecccd156d18 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BERLIN) += \ + berlin2-sony-nsz-gs7.dtb \ + berlin2cd-google-chromecast.dtb \ + berlin2cd-valve-steamlink.dtb \ + berlin2q-marvell-dmp.dtb diff --git a/arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts new file mode 100644 index 000000000000..64a297759eb9 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Sony NSZ-GS7 + * + * Sebastian Hesselbarth + */ + +/dts-v1/; + +#include "berlin2.dtsi" + +/ { + model = "Sony NSZ-GS7"; + compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; +}; + +&ahci { status = "okay"; }; + +ð1 { status = "okay"; }; + +/* Unpopulated SATA plug on solder side */ +&sata0 { status = "okay"; }; + +&sata_phy { status = "okay"; }; + +/* Samsung M8G2FA 8GB eMMC */ +&sdhci2 { + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/synaptics/berlin2.dtsi b/arch/arm/boot/dts/synaptics/berlin2.dtsi new file mode 100644 index 000000000000..1114c592e461 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2.dtsi @@ -0,0 +1,540 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC + * + * Sebastian Hesselbarth + * + * based on GPL'ed 2.6 kernel sources + * (c) Marvell International Ltd. + */ + +#include +#include + +/ { + model = "Marvell Armada 1500 (BG2) SoC"; + compatible = "marvell,berlin2", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,berlin-smp"; + + cpu@0 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; + }; + + cpu@1 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; + }; + }; + + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + soc@f7000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + ranges = <0 0xf7000000 0x1000000>; + + sdhci0: mmc@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci1: mmc@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci2: mmc@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = ; + clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; + clock-names = "io", "core"; + pinctrl-0 = <&emmc_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + l2: cache-controller@ac0000 { + compatible = "marvell,tauros3-cache", "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu: snoop-control-unit@ad0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xad0000 0x58>; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + interrupts = ; + clocks = <&chip_clk CLKID_TWD>; + }; + + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip_clk CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip_clk CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + gpio0: gpio@400 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0>; + }; + }; + + gpio1: gpio@800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <1>; + }; + }; + + gpio2: gpio@c00 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <2>; + }; + }; + + gpio3: gpio@1000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <3>; + }; + }; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + interrupts = <8>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "okay"; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + interrupts = <9>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "okay"; + }; + + timer2: timer@2c28 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c28 0x14>; + interrupts = <10>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer@2c3c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c3c 0x14>; + interrupts = <11>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer4: timer@2c50 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c50 0x14>; + interrupts = <12>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer5: timer@2c64 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c64 0x14>; + interrupts = <13>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer6: timer@2c78 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c78 0x14>; + interrupts = <14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer7: timer@2c8c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c8c 0x14>; + interrupts = <15>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + aic: interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + ahci: sata@e90000 { + compatible = "marvell,berlin2-ahci", "generic-ahci"; + reg = <0xe90000 0x1000>; + interrupts = ; + clocks = <&chip_clk CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + status = "disabled"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + status = "disabled"; + }; + }; + + sata_phy: phy@e900a0 { + compatible = "marvell,berlin2-sata-phy"; + reg = <0xe900a0 0x200>; + clocks = <&chip_clk CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + sata-phy@0 { + reg = <0>; + }; + + sata-phy@1 { + reg = <1>; + }; + }; + + chip: chip-control@ea0000 { + compatible = "simple-mfd", "syscon"; + reg = <0xea0000 0x400>; + + chip_clk: clock { + compatible = "marvell,berlin2-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + soc_pinctrl: pin-controller { + compatible = "marvell,berlin2-soc-pinctrl"; + + emmc_pmux: emmc-pmux { + groups = "G26"; + function = "emmc"; + }; + }; + + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; + }; + }; + + pwm: pwm@f20000 { + compatible = "marvell,berlin-pwm"; + reg = <0xf20000 0x40>; + clocks = <&chip_clk CLKID_CFG>; + #pwm-cells = <3>; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + wdt0: watchdog@1000 { + compatible = "snps,dw-wdt"; + reg = <0x1000 0x100>; + clocks = <&refclk>; + interrupts = <0>; + }; + + wdt1: watchdog@2000 { + compatible = "snps,dw-wdt"; + reg = <0x2000 0x100>; + clocks = <&refclk>; + interrupts = <1>; + }; + + wdt2: watchdog@3000 { + compatible = "snps,dw-wdt"; + reg = <0x3000 0x100>; + clocks = <&refclk>; + interrupts = <2>; + }; + + sm_gpio1: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + }; + }; + + sm_gpio0: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <11>; + }; + }; + + uart0: serial@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <8>; + clocks = <&refclk>; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: serial@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <9>; + clocks = <&refclk>; + pinctrl-0 = <&uart1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart2: serial@b000 { + compatible = "snps,dw-apb-uart"; + reg = <0xb000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <10>; + clocks = <&refclk>; + pinctrl-0 = <&uart2_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sysctrl: system-controller@d000 { + compatible = "simple-mfd", "syscon"; + reg = <0xd000 0x100>; + + sys_pinctrl: pin-controller { + compatible = "marvell,berlin2-system-pinctrl"; + uart0_pmux: uart0-pmux { + groups = "GSM4"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM5"; + function = "uart1"; + }; + uart2_pmux: uart2-pmux { + groups = "GSM3"; + function = "uart2"; + }; + }; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts new file mode 100644 index 000000000000..c1d91424e658 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Google Chromecast + * + * Sebastian Hesselbarth + */ + +/dts-v1/; + +#include "berlin2cd.dtsi" +#include + +/ { + model = "Google Chromecast"; + compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + + /* + * We're using "linux,usable-memory" instead of "reg" here + * because the (signed and encrypted) bootloader that shipped + * with this device provides an incorrect memory range in + * ATAG_MEM. Linux helpfully overrides the "reg" property with + * data from the ATAG, so we can't specify the proper range + * normally. Fortunately, this alternate property is checked + * first by the OF driver, so we can (ab)use it instead. + */ + linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */ + }; + + led-controller { + compatible = "pwm-leds"; + pinctrl-0 = <&ledpwm_pmux>; + pinctrl-names = "default"; + + led-1 { + label = "white"; + pwms = <&pwm 0 600000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + led-2 { + label = "red"; + pwms = <&pwm 1 600000 0>; + max-brightness = <255>; + }; + }; +}; + +/* + * AzureWave AW-NH387 (Marvell 88W8787) + * 802.11b/g/n + Bluetooth 2.1 + */ +&sdhci0 { + non-removable; + status = "okay"; +}; + +&uart0 { status = "okay"; }; + +&usb_phy1 { status = "okay"; }; + +&usb1 { status = "okay"; }; + +&soc_pinctrl { + ledpwm_pmux: ledpwm-pmux { + groups = "G0"; + function = "pwm"; + }; +}; diff --git a/arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts new file mode 100644 index 000000000000..79ac842ae461 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Alexander Monakov + */ +/dts-v1/; + +#include "berlin2cd.dtsi" +#include + +/ { + model = "Valve Steam Link"; + compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&porta 6 GPIO_ACTIVE_HIGH>; + active-delay = <100>; + inactive-delay = <10>; + wait-delay = <100>; + priority = <200>; + }; +}; + +&cpu { + cpu-supply = <&vcpu>; + operating-points = < + /* kHz uV */ + 1000000 1325000 + >; +}; + +&i2c0 { + status = "okay"; + + /* There are two regulators on the board. One is accessible via I2C, + * with buck1 providing SoC power (set up by bootloader to 1.325V or + * less depending on leakage value in OTP), and buck2 likely used for + * DRAM (providing 1.35V). The other regulator on the opposite side + * of the board is probably supplying SDIO and NAND fixed voltages. */ + regulator@19 { + compatible = "marvell,88pg868"; + reg = <0x19>; + + vcpu: buck1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1325000>; + }; + }; +}; + +/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */ +&sdhci0 { + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&uart0 { + /* RX/TX are routed to TP50/TP51 on the board. */ + status = "okay"; +}; + +/* The SoC is connected to on-board USB hub that in turn has one downstream + * port wired to the on-board Steam Controller wireless receiver chip. */ +&usb_phy1 { status = "okay"; }; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +ð1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/synaptics/berlin2cd.dtsi b/arch/arm/boot/dts/synaptics/berlin2cd.dtsi new file mode 100644 index 000000000000..b2768f7a3185 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2cd.dtsi @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC + * + * Sebastian Hesselbarth + * + * based on GPL'ed 2.6 kernel sources + * (c) Marvell International Ltd. + */ + +#include +#include + +/ { + model = "Marvell Armada 1500-mini (BG2CD) SoC"; + compatible = "marvell,berlin2cd", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + operating-points = < + /* kHz uV */ + 800000 1200000 + 600000 1200000 + >; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + soc@f7000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + ranges = <0 0xf7000000 0x1000000>; + + sdhci0: mmc@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + l2: cache-controller@ac0000 { + compatible = "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + snoop-control-unit@ad0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xad0000 0x100>; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + global-timer@ad0200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xad0200 0x20>; + interrupts = ; + clocks = <&chip_clk CLKID_TWD>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + interrupts = ; + clocks = <&chip_clk CLKID_TWD>; + }; + + local-wdt@ad0620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xad0620 0x20>; + interrupts = ; + clocks = <&chip_clk CLKID_TWD>; + }; + + usb_phy0: usb-phy@b74000 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xb74000 0x128>; + #phy-cells = <0>; + resets = <&chip_rst 0x178 23>; + status = "disabled"; + }; + + usb_phy1: usb-phy@b78000 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xb78000 0x128>; + #phy-cells = <0>; + resets = <&chip_rst 0x178 24>; + status = "disabled"; + }; + + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip_clk CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip_clk CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + gpio0: gpio@400 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0>; + }; + }; + + gpio1: gpio@800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <1>; + }; + }; + + gpio2: gpio@c00 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <2>; + }; + }; + + gpio3: gpio@1000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <3>; + }; + }; + + i2c0: i2c@1400 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + interrupts = <16>; + clocks = <&chip_clk CLKID_CFG>; + status = "disabled"; + }; + + i2c1: i2c@1800 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800 0x100>; + interrupts = <17>; + clocks = <&chip_clk CLKID_CFG>; + status = "disabled"; + }; + + spi0: spi@1c00 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1c00 0x100>; + interrupts = <4>; + clocks = <&chip_clk CLKID_CFG>; + status = "disabled"; + }; + + wdt4: watchdog@2000 { + compatible = "snps,dw-wdt"; + reg = <0x2000 0x100>; + clocks = <&chip_clk CLKID_CFG>; + interrupts = <5>; + status = "disabled"; + }; + + wdt5: watchdog@2400 { + compatible = "snps,dw-wdt"; + reg = <0x2400 0x100>; + clocks = <&chip_clk CLKID_CFG>; + interrupts = <6>; + status = "disabled"; + }; + + wdt6: watchdog@2800 { + compatible = "snps,dw-wdt"; + reg = <0x2800 0x100>; + clocks = <&chip_clk CLKID_CFG>; + interrupts = <7>; + status = "disabled"; + }; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + interrupts = <8>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "okay"; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + interrupts = <9>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "okay"; + }; + + timer2: timer@2c28 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c28 0x14>; + interrupts = <10>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer@2c3c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c3c 0x14>; + interrupts = <11>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer4: timer@2c50 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c50 0x14>; + interrupts = <12>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer5: timer@2c64 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c64 0x14>; + interrupts = <13>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer6: timer@2c78 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c78 0x14>; + interrupts = <14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer7: timer@2c8c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c8c 0x14>; + interrupts = <15>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + aic: interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + chip: chip-control@ea0000 { + compatible = "simple-mfd", "syscon"; + reg = <0xea0000 0x400>; + + chip_clk: clock { + compatible = "marvell,berlin2-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + soc_pinctrl: pin-controller { + compatible = "marvell,berlin2cd-soc-pinctrl"; + + uart0_pmux: uart0-pmux { + groups = "G6"; + function = "uart0"; + }; + }; + + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; + }; + }; + + usb0: usb@ed0000 { + compatible = "chipidea,usb2"; + reg = <0xed0000 0x200>; + interrupts = ; + clocks = <&chip_clk CLKID_USB0>; + phys = <&usb_phy0>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + usb1: usb@ee0000 { + compatible = "chipidea,usb2"; + reg = <0xee0000 0x200>; + interrupts = ; + clocks = <&chip_clk CLKID_USB1>; + phys = <&usb_phy1>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + pwm: pwm@f20000 { + compatible = "marvell,berlin-pwm"; + reg = <0xf20000 0x40>; + clocks = <&chip_clk CLKID_CFG>; + #pwm-cells = <3>; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + wdt0: watchdog@1000 { + compatible = "snps,dw-wdt"; + reg = <0x1000 0x100>; + clocks = <&refclk>; + interrupts = <0>; + }; + + wdt1: watchdog@2000 { + compatible = "snps,dw-wdt"; + reg = <0x2000 0x100>; + clocks = <&refclk>; + interrupts = <1>; + status = "disabled"; + }; + + wdt2: watchdog@3000 { + compatible = "snps,dw-wdt"; + reg = <0x3000 0x100>; + clocks = <&refclk>; + interrupts = <2>; + status = "disabled"; + }; + + sm_gpio1: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + }; + }; + + spi1: spi@6000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6000 0x100>; + clocks = <&refclk>; + interrupts = <5>; + status = "disabled"; + }; + + i2c2: i2c@7000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x100>; + interrupts = <6>; + clocks = <&refclk>; + status = "disabled"; + }; + + i2c3: i2c@8000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8000 0x100>; + interrupts = <7>; + clocks = <&refclk>; + status = "disabled"; + }; + + sm_gpio0: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0>; + }; + }; + + uart0: serial@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <8>; + clocks = <&refclk>; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: serial@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <9>; + clocks = <&refclk>; + status = "disabled"; + }; + + uart2: serial@b000 { + compatible = "snps,dw-apb-uart"; + reg = <0xb000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <10>; + clocks = <&refclk>; + status = "disabled"; + }; + + sysctrl: system-controller@d000 { + compatible = "simple-mfd", "syscon"; + reg = <0xd000 0x100>; + + sys_pinctrl: pin-controller { + compatible = "marvell,berlin2cd-system-pinctrl"; + }; + + adc: adc { + compatible = "marvell,berlin2-adc"; + interrupts = <12>, <14>; + interrupt-names = "adc", "tsen"; + }; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts new file mode 100644 index 000000000000..c162f98cb8e8 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2014 Antoine Ténart + */ + +/dts-v1/; + +#include +#include "berlin2q.dtsi" + +/ { + model = "Marvell BG2-Q DMP"; + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x80000000>; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator_usb0 { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_vbus: regulator_usb1 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator_usb2 { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sdio1_vmmc: regulator_sdio1_vmmc { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "sdio1_vmmc"; + enable-active-high; + regulator-boot-on; + gpio = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + + reg_sdio1_vqmmc: regulator_sido1_vqmmc { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "sdio1_vqmmc"; + regulator-type = "voltage"; + enable-active-high; + gpios = <&portb 16 GPIO_ACTIVE_HIGH>; + states = <3300000 0x1 + 1800000 0x0>; + }; + }; +}; + +&soc_pinctrl { + sd1gpio_pmux: sd1pwr-pmux { + groups = "G23", "G32"; + function = "gpio"; + }; +}; + +&sdhci1 { + vmmc-supply = <®_sdio1_vmmc>; + vqmmc-supply = <®_sdio1_vqmmc>; + cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>; + wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci2 { + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy2 { + status = "okay"; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb2 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +ð0 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/synaptics/berlin2q.dtsi b/arch/arm/boot/dts/synaptics/berlin2q.dtsi new file mode 100644 index 000000000000..6edaefa617a5 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/berlin2q.dtsi @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2014 Antoine Ténart + */ + +#include +#include + +/ { + model = "Marvell Armada 1500 pro (BG2-Q) SoC"; + compatible = "marvell,berlin2q", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,berlin-smp"; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <2>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <3>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + soc@f7000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xf7000000 0x1000000>; + interrupt-parent = <&gic>; + + sdhci0: mmc@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci1: mmc@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci2: mmc@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = ; + clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; + clock-names = "io", "core"; + status = "disabled"; + }; + + l2: cache-controller@ac0000 { + compatible = "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <2 2 2>; + arm,tag-latency = <2 2 2>; + }; + + scu: snoop-control-unit@ad0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xad0000 0x58>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + clocks = <&chip_clk CLKID_TWD>; + interrupts = ; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + usb_phy2: phy@a2f400 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xa2f400 0x128>; + #phy-cells = <0>; + resets = <&chip_rst 0x104 14>; + status = "disabled"; + }; + + usb2: usb@a30000 { + compatible = "chipidea,usb2"; + reg = <0xa30000 0x10000>; + interrupts = ; + clocks = <&chip_clk CLKID_USB2>; + phys = <&usb_phy2>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + usb_phy0: phy@b74000 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xb74000 0x128>; + #phy-cells = <0>; + resets = <&chip_rst 0x104 12>; + status = "disabled"; + }; + + usb_phy1: phy@b78000 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xb78000 0x128>; + #phy-cells = <0>; + resets = <&chip_rst 0x104 13>; + status = "disabled"; + }; + + eth0: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip_clk CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + gpio0: gpio@400 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0>; + }; + }; + + gpio1: gpio@800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <1>; + }; + }; + + gpio2: gpio@c00 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <2>; + }; + }; + + gpio3: gpio@1000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <3>; + }; + }; + + i2c0: i2c@1400 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + interrupts = <4>; + clocks = <&chip_clk CLKID_CFG>; + pinctrl-0 = <&twsi0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c1: i2c@1800 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800 0x100>; + interrupts = <5>; + clocks = <&chip_clk CLKID_CFG>; + pinctrl-0 = <&twsi1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + interrupts = <8>; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + }; + + timer2: timer@2c28 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c28 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer@2c3c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c3c 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer4: timer@2c50 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c50 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer5: timer@2c64 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c64 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer6: timer@2c78 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c78 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer7: timer@2c8c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c8c 0x14>; + clocks = <&chip_clk CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + aic: interrupt-controller@3800 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3800 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + chip: chip-control@ea0000 { + compatible = "simple-mfd", "syscon"; + reg = <0xea0000 0x400>, <0xdd0170 0x10>; + + chip_clk: clock { + compatible = "marvell,berlin2q-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + soc_pinctrl: pin-controller { + compatible = "marvell,berlin2q-soc-pinctrl"; + + sd1_pmux: sd1-pmux { + groups = "G31"; + function = "sd1"; + }; + + twsi0_pmux: twsi0-pmux { + groups = "G6"; + function = "twsi0"; + }; + + twsi1_pmux: twsi1-pmux { + groups = "G7"; + function = "twsi1"; + }; + }; + + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; + }; + }; + + ahci: sata@e90000 { + compatible = "marvell,berlin2q-ahci", "generic-ahci"; + reg = <0xe90000 0x1000>; + interrupts = ; + clocks = <&chip_clk CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + status = "disabled"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + status = "disabled"; + }; + }; + + sata_phy: phy@e900a0 { + compatible = "marvell,berlin2q-sata-phy"; + reg = <0xe900a0 0x200>; + clocks = <&chip_clk CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + sata-phy@0 { + reg = <0>; + }; + + sata-phy@1 { + reg = <1>; + }; + }; + + usb0: usb@ed0000 { + compatible = "chipidea,usb2"; + reg = <0xed0000 0x10000>; + interrupts = ; + clocks = <&chip_clk CLKID_USB0>; + phys = <&usb_phy0>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + usb1: usb@ee0000 { + compatible = "chipidea,usb2"; + reg = <0xee0000 0x10000>; + interrupts = ; + clocks = <&chip_clk CLKID_USB1>; + phys = <&usb_phy1>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + pwm: pwm@f20000 { + compatible = "marvell,berlin-pwm"; + reg = <0xf20000 0x40>; + clocks = <&chip_clk CLKID_CFG>; + #pwm-cells = <3>; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + wdt0: watchdog@1000 { + compatible = "snps,dw-wdt"; + reg = <0x1000 0x100>; + clocks = <&refclk>; + interrupts = <0>; + }; + + wdt1: watchdog@2000 { + compatible = "snps,dw-wdt"; + reg = <0x2000 0x100>; + clocks = <&refclk>; + interrupts = <1>; + }; + + wdt2: watchdog@3000 { + compatible = "snps,dw-wdt"; + reg = <0x3000 0x100>; + clocks = <&refclk>; + interrupts = <2>; + }; + + sm_gpio1: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + }; + }; + + i2c2: i2c@7000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x100>; + interrupts = <6>; + clocks = <&refclk>; + pinctrl-0 = <&twsi2_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c3: i2c@8000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8000 0x100>; + interrupts = <7>; + clocks = <&refclk>; + pinctrl-0 = <&twsi3_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart0: serial@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + interrupts = <8>; + clocks = <&refclk>; + reg-shift = <2>; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: serial@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + interrupts = <9>; + clocks = <&refclk>; + reg-shift = <2>; + pinctrl-0 = <&uart1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sm_gpio0: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + }; + }; + + sysctrl: pin-controller@d000 { + compatible = "simple-mfd", "syscon"; + reg = <0xd000 0x100>; + + sys_pinctrl: pin-controller { + compatible = "marvell,berlin2q-system-pinctrl"; + + uart0_pmux: uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM14"; + function = "uart1"; + }; + + twsi2_pmux: twsi2-pmux { + groups = "GSM13"; + function = "twsi2"; + }; + + twsi3_pmux: twsi3-pmux { + groups = "GSM14"; + function = "twsi3"; + }; + }; + + adc: adc { + compatible = "marvell,berlin2-adc"; + interrupts = <12>, <14>; + interrupt-names = "adc", "tsen"; + }; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts deleted file mode 100644 index 84a3eb38e71d..000000000000 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ /dev/null @@ -1,807 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include -#include - -#include "tegra114.dtsi" - -/ { - model = "Asus Transformer Pad TF701T"; - compatible = "asus,tf701t", "nvidia,tegra114"; - chassis-type = "convertible"; - - aliases { - mmc0 = "/mmc@78000600"; /* eMMC */ - mmc1 = "/mmc@78000400"; /* uSD slot */ - mmc2 = "/mmc@78000000"; /* WiFi */ - - rtc0 = &palmas; - rtc1 = "/rtc@7000e000"; - - serial0 = &uartd; /* Console */ - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma@80000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x80000000 0x30000000>; - size = <0x10000000>; - linux,cma-default; - reusable; - }; - - trustzone@bfe00000 { - reg = <0xbfe00000 0x200000>; - no-map; - }; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&tps65913_ldo2>; - - nvidia,ganged-mode = <&dsib>; - - panel_primary: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - - link2 = <&panel_secondary>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - - dsi@54400000 { - status = "okay"; - - avdd-dsi-csi-supply = <&tps65913_ldo2>; - - panel_secondary: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - }; - }; - }; - - pinmux@70000868 { - asus_pad_ec_default: pinmux-asus-pad-ec-default { - ec-interrupt { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ec-request { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - backlight_default: pinmux-backlight-default { - backlight-enable { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - codec_default: pinmux-codec-default { - interrupt { - nvidia,pins = "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ldo1-en { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - gpio_keys_default: pinmux-gpio-keys-default { - power { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - volume { - nvidia,pins = "kb_row1_pr1", - "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - hp_det_default: pinmux-hp-det-default { - gmi_iordy_pi5 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - imu_default: pinmux-imu-default { - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - pwm_default: pinmux-pwm-default { - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - /* XXX make this something more sensible */ - pwm_sleep: pinmux-pwm-sleep { - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - sdmmc3_default: pinmux-sdmmc3-default { - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - - vdd_lcd_default: pinmux-vdd-lcd-default { - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - /* GPS */ - }; - - serial@70006200 { - /* Bluetooth */ - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pwm_default>; - pinctrl-1 = <&pwm_sleep>; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - magnetometer@c { - compatible = "asahi-kasei,ak09911"; - reg = <0xc>; - - vdd-supply = <&vdd_3v3_sys>; - }; - - rt5639: audio-codec@1c { - compatible = "realtek,rt5639"; - reg = <0x1c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&codec_default>; - }; - - temp_sensor: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - - motion-tracker@68 { - compatible = "invensense,mpu6500"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - mount-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - - pinctrl-names = "default"; - pinctrl-0 = <&imu_default>; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - power-sensor@44 { - compatible = "ti,ina230"; - reg = <0x44>; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - light-sensor@1c { - compatible = "dynaimage,al3320a"; - reg = <0x1c>; - - vdd-supply = <&vdd_3v3_sys>; - }; - }; - - i2c@7000c700 { - /* HDMI DDC */ - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - palmas: pmic@58 { - compatible = "ti,tps65913", "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - ti,palmas-enable-dvfs1; - - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "gpio"; - }; - - pin_gpio2 { - pins = "gpio2"; - function = "gpio"; - }; - - pin_gpio3 { - pins = "gpio3"; - function = "gpio"; - }; - - pin_gpio4 { - pins = "gpio4"; - function = "gpio"; - }; - - pin_gpio5 { - pins = "gpio5"; - function = "gpio"; - }; - - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - - pin_gpio7 { - pins = "gpio7"; - function = "gpio"; - }; - - pin_powergood { - pins = "powergood"; - function = "powergood"; - }; - - pin_vac { - pins = "vac"; - function = "vac"; - }; - }; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - ldo1-in-supply = <&tps65913_smps7>; - ldo2-in-supply = <&tps65913_smps7>; - ldo4-in-supply = <&tps65913_smps8>; - ldo5-in-supply = <&tps65913_smps9>; - ldo6-in-supply = <&tps65913_smps9>; - ldo7-in-supply = <&tps65913_smps9>; - ldo9-in-supply = <&tps65913_smps9>; - - regulators { - tps65913_smps123: smps123 { - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - ti,roof-floor = <1>; - ti,mode-sleep = <3>; - }; - - tps65913_smps45: smps45 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - ti,roof-floor = <3>; - }; - - smps6 { - regulator-name = "va-lcd-hv"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - tps65913_smps7: smps7 { - regulator-name = "vdd-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - tps65913_smps8: smps8 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - tps65913_smps9: smps9 { - regulator-name = "vdd-sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - tps65913_smps10_out1: smps10_out1 { - regulator-name = "vd-smps10-out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - tps65913_smps10_out2: smps10_out2 { - regulator-name = "vd-smps10-out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - tps65913_ldo1: ldo1 { - regulator-name = "vdd-hdmi-pll"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - ti,roof-floor = <3>; - }; - - tps65913_ldo2: ldo2 { - regulator-name = "vdd-2v8-dsi-csi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo4 { - regulator-name = "vdd-1v2-cam"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo5 { - regulator-name = "vdd-cam"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6 { - regulator-name = "vdd-dev"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-boot-on; - }; - - ldo7 { - regulator-name = "vdd-2v8-cam"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - tps65913_ldo8: ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - tps65913_ldo9: ldo9 { - regulator-name = "vdd-sdmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - }; - - tps65913_ldoln: ldoln { - regulator-name = "vdd-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "vdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - }; - }; - - ahub@70080000 { - i2s@70080300 { - status = "okay"; - }; - }; - - mmc@78000000 { - /* WiFi */ - }; - - /* MicroSD card */ - mmc@78000400 { - status = "okay"; - - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - - nvidia,default-tap = <0x3>; - nvidia,default-trim = <0x3>; - - vmmc-supply = <&vdd_usd>; - vqmmc-supply = <&tps65913_ldo9>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc3_default>; - }; - - mmc@78000600 { - /* eMMC */ - }; - - usb@7d000000 { - compatible = "nvidia,tegra114-udc"; - status = "okay"; - dr_mode = "peripheral"; - - /* Peripheral USB via ASUS connector */ - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - - /* Host USB via dock */ - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_5v0_sys>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_5v0_sys>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <1 255>; - num-interpolated-steps = <254>; - default-brightness-level = <224>; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_default>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - label = "GPIO Hall Effect Sensor"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_hall_sensor_default>; - - switch-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - linux,can-disable; - wakeup-source; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - label = "GPIO Buttons"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - button-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - button-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - - button-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - }; - - sound { - compatible = "asus,tegra-audio-rt5639-tf701t", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "Asus Transformer Pad TF701T RT5639"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Speakers", "SPORP", - "Speakers", "SPORN", - "Speakers", "SPOLP", - "Speakers", "SPOLN", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s0>; - nvidia,audio-codec = <&rt5639>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA114_CLK_PLL_A>, - <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA114_CLK_EXTERN1>; - - pinctrl-names = "default"; - pinctrl-0 = <&hp_det_default>; - }; - - vdd_5v0_sys: regulator-5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regulator-3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_lcd: regulator-vdd-lcd { - compatible = "regulator-fixed"; - regulator-name = "vdd_lcd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&tps65913_smps8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - - pinctrl-names = "default"; - pinctrl-0 = <&vdd_lcd_default>; - }; - - vdd_usd: regulator-vdd-usd { - compatible = "regulator-fixed"; - regulator-name = "vdd_sd_slot"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - vin-supply = <&tps65913_smps9>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc3_vdd_default>; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts deleted file mode 100644 index a685fcb129d0..000000000000 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ /dev/null @@ -1,1287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This dts file supports Dalmore A04. - * Other board revisions are not supported - */ - -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "NVIDIA Tegra114 Dalmore evaluation board"; - compatible = "nvidia,dalmore", "nvidia,tegra114"; - - aliases { - rtc0 = "/i2c@7000d000/tps65913@58"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&vdd_hdmi_reg>; - pll-supply = <&palmas_smps3_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&avdd_1v2_reg>; - - panel@0 { - compatible = "panasonic,vvx10f004b00"; - reg = <0>; - - power-supply = <&avdd_lcd_reg>; - backlight = <&backlight>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_cs6_n_pi3", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1", - "dap3_sclk_pp3"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0", - "gmi_cs0_n_pj0", - "gmi_cs2_n_pk3", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_iordy_pi5", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3", - "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5", - "pu6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2", - "usb_vbus_en1_pn5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - battery: smart-battery@b { - compatible = "ti,bq20z45", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <100>; - power-supplies = <&charger>; - }; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&palmas_ldo6_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - tps51632@43 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-boot-on; - regulator-always-on; - }; - - tps65090@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = ; - - vsys1-supply = <&vdd_ac_bat_reg>; - vsys2-supply = <&vdd_ac_bat_reg>; - vsys3-supply = <&vdd_ac_bat_reg>; - infet1-supply = <&vdd_ac_bat_reg>; - infet2-supply = <&vdd_ac_bat_reg>; - infet3-supply = <&tps65090_dcdc2_reg>; - infet4-supply = <&tps65090_dcdc2_reg>; - infet5-supply = <&tps65090_dcdc2_reg>; - infet6-supply = <&tps65090_dcdc2_reg>; - infet7-supply = <&tps65090_dcdc2_reg>; - vsys-l1-supply = <&vdd_ac_bat_reg>; - vsys-l2-supply = <&vdd_ac_bat_reg>; - - charger: charger { - compatible = "ti,tps65090-charger"; - ti,enable-low-current-chrg; - }; - - regulators { - tps65090_dcdc1_reg: dcdc1 { - regulator-name = "vdd-sys-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc2_reg: dcdc2 { - regulator-name = "vdd-sys-3v3"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc3_reg: dcdc3 { - regulator-name = "vdd-ao"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bl_reg: fet1 { - regulator-name = "vdd-lcd-bl"; - }; - - fet3 { - regulator-name = "vdd-modem-3v3"; - }; - - avdd_lcd_reg: fet4 { - regulator-name = "avdd-lcd"; - }; - - fet5 { - regulator-name = "vdd-lvds"; - }; - - fet6 { - regulator-name = "vdd-sd-slot"; - regulator-always-on; - regulator-boot-on; - }; - - fet7 { - regulator-name = "vdd-com-3v3"; - }; - - ldo1 { - regulator-name = "vdd-sby-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-sby-3v3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas: tps65913@58 { - compatible = "ti,tps65913", "ti,palmas"; - reg = <0x58>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - smps1-in-supply = <&tps65090_dcdc3_reg>; - smps3-in-supply = <&tps65090_dcdc3_reg>; - smps4-in-supply = <&tps65090_dcdc2_reg>; - smps7-in-supply = <&tps65090_dcdc2_reg>; - smps8-in-supply = <&tps65090_dcdc2_reg>; - smps9-in-supply = <&tps65090_dcdc2_reg>; - ldo1-in-supply = <&tps65090_dcdc2_reg>; - ldo2-in-supply = <&tps65090_dcdc2_reg>; - ldo3-in-supply = <&palmas_smps3_reg>; - ldo4-in-supply = <&tps65090_dcdc2_reg>; - ldo5-in-supply = <&vdd_ac_bat_reg>; - ldo6-in-supply = <&tps65090_dcdc2_reg>; - ldo7-in-supply = <&tps65090_dcdc2_reg>; - ldo8-in-supply = <&tps65090_dcdc3_reg>; - ldo9-in-supply = <&palmas_smps9_reg>; - ldoln-in-supply = <&tps65090_dcdc1_reg>; - ldousb-in-supply = <&tps65090_dcdc1_reg>; - - regulators { - smps12 { - regulator-name = "vddio-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas_smps3_reg: smps3 { - regulator-name = "vddio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps457 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8 { - regulator-name = "avdd-pll"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas_smps9_reg: smps9 { - regulator-name = "sdhci-vdd-sd-slot"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo1 { - regulator-name = "avdd-cam1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo2 { - regulator-name = "avdd-cam2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - avdd_1v2_reg: ldo3 { - regulator-name = "avdd-dsi-csi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - palmas_ldo6_reg: ldo6 { - regulator-name = "vdd-sensor-2v85"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo7 { - regulator-name = "vdd-af-cam1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - ldo9 { - regulator-name = "vddio-sdmmc-2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln { - regulator-name = "hvdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "avdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1 { - regulator-name = "rail-3v3"; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen2 { - regulator-name = "rail-5v0"; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - mmc@78000400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - status = "okay"; - }; - - mmc@78000600 { - bus-width = <8>; - status = "okay"; - non-removable; - }; - - usb@7d000000 { - compatible = "nvidia,tegra114-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&usb3_vbus_reg>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-home { - label = "Home"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - vdd_ac_bat_reg: regulator-acbat { - compatible = "regulator-fixed"; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - dvdd_ts_reg: regulator-ts { - compatible = "regulator-fixed"; - regulator-name = "dvdd_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_hdmi_reg: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vdd_hdmi_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_cam_1v8_reg: regulator-cam { - compatible = "regulator-fixed"; - regulator-name = "vdd_cam_1v8_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&palmas_gpio 6 0>; - }; - - vdd_5v0_hdmi: regulator-hdmicon { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-dalmore", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Dalmore"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Speakers", "SPORP", - "Speakers", "SPORN", - "Speakers", "SPOLP", - "Speakers", "SPOLN", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA114_CLK_PLL_A>, - <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA114_CLK_EXTERN1>; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts deleted file mode 100644 index b9d00009d1f4..000000000000 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ /dev/null @@ -1,1108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "NVIDIA SHIELD"; - compatible = "nvidia,roth", "nvidia,tegra114"; - - chosen { - /* SHIELD's bootloader's arguments need to be overridden */ - bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; - /* SHIELD's bootloader will place initrd at this address */ - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; - - aliases { - serial0 = &uartd; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - /* memory >= 0x79600000 is reserved for firmware usage */ - reg = <0x80000000 0x79600000>; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&vdd_1v2_ap>; - - panel@0 { - compatible = "lg,lh500wx1-sd03"; - reg = <0>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs6_n_pi13 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_cd_n_pv2", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad12_ph4", - "gmi_ad15_ph7", - "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1", - "gmi_cs2_n_pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6", - "gmi_cs0_n_pj0", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - /* Usable on reworked devices only */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - regulator@43 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas: pmic@58 { - compatible = "ti,tps65913", "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - regulators { - smps12 { - regulator-name = "vdd-ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: smps3 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - smps457 { - regulator-name = "vdd-soc"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8 { - regulator-name = "avdd-pll-1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9 { - regulator-name = "vdd-2v85-emmc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - smps10_out1 { - regulator-name = "vdd-fan"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out2 { - regulator-name = "vdd-5v0-sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-2v8-display"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v2_ap: ldo3 { - regulator-name = "avdd-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5 { - regulator-name = "avdd-hdmi-pll"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo6 { - regulator-name = "vdd-sensor-2v8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - vddio_sdmmc3: ldo9 { - regulator-name = "vddio-sdmmc3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "avdd-usb-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regen1 { - regulator-name = "rail-3v3"; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen2 { - regulator-name = "rail-5v0"; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* SD card */ - mmc@78000400 { - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - }; - - /* eMMC */ - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* External USB port (must be powered) */ - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - interrupts = ; - /* Should be changed to "otg" once we have vbus_supply */ - /* As of now, USB devices need to be powered externally */ - dr_mode = "host"; - }; - - /* SHIELD controller */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 1 40000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&lcd_bl_en>; - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-back { - label = "Back"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-home { - label = "Home"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - lcd_bl_en: regulator-lcden { - compatible = "regulator-fixed"; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vdd_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "vdd_lcd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator-1v8ts { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; - - regulator-3v3ts { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_ts"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator-1v8com { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_com"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator-3v3com { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_sys>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts deleted file mode 100644 index f02d8c79eee7..000000000000 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "Tegra Note 7"; - compatible = "nvidia,tn7", "nvidia,tegra114"; - - chosen { - /* TN7's bootloader's arguments need to be overridden */ - bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; - /* TN7's bootloader will place initrd at this address */ - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; - - aliases { - serial0 = &uartd; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - /* memory >= 0x37e00000 is reserved for firmware usage */ - reg = <0x80000000 0x37e00000>; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&vdd_1v2_ap>; - - panel@0 { - compatible = "lg,ld070wx3-sl01"; - reg = <0>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - palmas: pmic@58 { - compatible = "ti,tps65913", "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - ldoln-in-supply = <&vdd_smps10_out2>; - - regulators { - smps123 { - regulator-name = "vd-cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45 { - regulator-name = "vd-soc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6 { - regulator-name = "va-lcd-hv"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7 { - regulator-name = "vd-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: smps8 { - regulator-name = "vs-pmu-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_2v9_sys: smps9 { - regulator-name = "vs-sys-2v9"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_smps10_out1: smps10_out1 { - regulator-name = "vd-smps10-out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_smps10_out2: smps10_out2 { - regulator-name = "vd-smps10-out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1 { - regulator-name = "va-pllx"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v2_ap: ldo2 { - regulator-name = "va-ap-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "vd-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4 { - regulator-name = "vd-ts-hv"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo5 { - regulator-name = "va-cam2-hv"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo6 { - regulator-name = "va-sns-hv"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo7 { - regulator-name = "va-cam1-hv"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo8 { - regulator-name = "va-ap-rtc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - ti,enable-ldo8-tracking; - regulator-always-on; - regulator-boot-on; - }; - - ldo9 { - regulator-name = "vi-sdcard"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - ldousb { - regulator-name = "avdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln { - regulator-name = "va-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* eMMC */ - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - interrupts = ; - /* Should be changed to "otg" once we have vbus_supply */ - /* As of now, USB devices need to be powered externally */ - dr_mode = "host"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 1 40000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&lcd_bl_en>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - /* FIXME: output of BQ24192 */ - vs_sys: regulator-vs { - compatible = "regulator-fixed"; - regulator-name = "VS_SYS"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; - - lcd_bl_en: regulator-lcden { - compatible = "regulator-fixed"; - regulator-name = "VDD_LCD_BL"; - regulator-min-microvolt = <16500000>; - regulator-max-microvolt = <16500000>; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vs_sys>; - regulator-boot-on; - }; - - vdd_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "VD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - regulator-boot-on; - }; -}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi deleted file mode 100644 index 09996acad639..000000000000 --- a/arch/arm/boot/dts/tegra114.dtsi +++ /dev/null @@ -1,850 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra114"; - interrupt-parent = <&lic>; - #address-cells = <1>; - #size-cells = <1>; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x0>; - }; - - sram@40000000 { - compatible = "mmio-sram"; - reg = <0x40000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000>; - - vde_pool: sram@400 { - reg = <0x400 0x3fc00>; - pool; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra114-host1x"; - reg = <0x50000000 0x00028000>; - interrupts = , /* syncpt */ - ; /* general */ - interrupt-names = "syncpt", "host1x"; - clocks = <&tegra_car TEGRA114_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; - reset-names = "host1x", "mc"; - iommus = <&mc TEGRA_SWGROUP_HC>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x01000000>; - - gr2d@54140000 { - compatible = "nvidia,tegra114-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_GR2D>; - resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; - reset-names = "2d", "mc"; - - iommus = <&mc TEGRA_SWGROUP_G2>; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra114-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_GR3D>; - resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; - reset-names = "3d", "mc"; - - iommus = <&mc TEGRA_SWGROUP_NV>; - }; - - dc@54200000 { - compatible = "nvidia,tegra114-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP1>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra114-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP2>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra114-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_HDMI>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - dsia: dsi@54300000 { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_DSIA>, - <&tegra_car TEGRA114_CLK_DSIALP>, - <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - dsib: dsi@54400000 { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54400000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_DSIB>, - <&tegra_car TEGRA114_CLK_DSIBLP>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 82>; - reset-names = "dsi"; - nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x50041000 0x1000>, - <0x50042000 0x1000>, - <0x50044000 0x2000>, - <0x50046000 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>, - <0x60004400 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; - reg = <0x60005000 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA114_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra114-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra114-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA114_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb: ahb@6000c000 { - compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; - reg = <0x6000c000 0x150>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-ranges = <&pinmux 0 0 246>; - }; - - vde@6001a000 { - compatible = "nvidia,tegra114-vde"; - reg = <0x6001a000 0x1000>, /* Syntax Engine */ - <0x6001b000 0x1000>, /* Video Bitstream Engine */ - <0x6001c000 0x100>, /* Macroblock Engine */ - <0x6001c200 0x100>, /* Post-processing Engine */ - <0x6001c400 0x100>, /* Motion Compensation Engine */ - <0x6001c600 0x100>, /* Transform Engine */ - <0x6001c800 0x100>, /* Pixel prediction block */ - <0x6001ca00 0x100>, /* Video DMA */ - <0x6001d800 0x400>; /* Video frame controls */ - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA114_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; - iommus = <&mc TEGRA_SWGROUP_VDE>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64>, /* Chip revision */ - <0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra114-pinmux"; - reg = <0x70000868 0x148>, /* Pad control registers */ - <0x70003000 0x40c>; /* Mux registers */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA114_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000dc00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000de00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_RTC>; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra114-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra114-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra114-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA114_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra114-mc"; - reg = <0x70019000 0x1000>; - clocks = <&tegra_car TEGRA114_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #reset-cells = <1>; - #iommu-cells = <1>; - }; - - ahub@70080000 { - compatible = "nvidia,tegra114-ahub"; - reg = <0x70080000 0x200>, - <0x70080200 0x100>, - <0x70081000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, - <&tegra_car TEGRA114_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 154>; /* adx */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "adx"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA114_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA114_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA114_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA114_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA114_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra114-mipi"; - reg = <0x700e3000 0x100>; - clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; - #nvidia,mipi-calibrate-cells = <1>; - }; - - mmc@78000000 { - compatible = "nvidia,tegra114-sdhci"; - reg = <0x78000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@78000200 { - compatible = "nvidia,tegra114-sdhci"; - reg = <0x78000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@78000400 { - compatible = "nvidia,tegra114-sdhci"; - reg = <0x78000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@78000600 { - compatible = "nvidia,tegra114-sdhci"; - reg = <0x78000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; - reg = <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000>, - <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USBD>, - <&tegra_car TEGRA114_CLK_PLL_U>, - <&tegra_car TEGRA114_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - nvidia,pmc = <&tegra_pmc 0>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; - reg = <0x7d008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000>, - <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USB3>, - <&tegra_car TEGRA114_CLK_PLL_U>, - <&tegra_car TEGRA114_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,pmc = <&tegra_pmc 2>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi deleted file mode 100644 index 970f33dd9101..000000000000 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ /dev/null @@ -1,1487 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016-2019 Toradex AG - * - */ - -#include - -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-924000000 { - clock-frequency = <924000000>; - nvidia,parent-clock-frequency = <924000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 0x8000000a - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x77e30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 0x80000012 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x76230303 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 0x80000017 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74a30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 0x8000001e - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74230403 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 0x80000026 - 0x00000001 0x00000001 - 0x00000003 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0503 - 0x73c30504 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 0x80000040 - 0x00000001 0x00000001 - 0x00000004 0x00000002 - 0x00000003 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000004 0x00000006 - 0x06040203 0x000a0504 - 0x73840a05 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 0x80000040 - 0x00000001 0x00000002 - 0x00000007 0x00000004 - 0x00000004 0x00000001 - 0x00000002 0x00000007 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000b0607 - 0x77450e08 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 0x80000040 - 0x00000001 0x00000002 - 0x00000009 0x00000005 - 0x00000006 0x00000001 - 0x00000002 0x00000008 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000d0709 - 0x7586120a 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 0x80000040 - 0x00000002 0x00000003 - 0x0000000c 0x00000007 - 0x00000008 0x00000001 - 0x00000002 0x00000009 - 0x00000002 0x00000002 - 0x00000005 0x00000006 - 0x06050202 0x0010090c - 0x7428180d 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 0x80000040 - 0x00000003 0x00000004 - 0x0000000e 0x00000009 - 0x0000000a 0x00000001 - 0x00000003 0x0000000b - 0x00000002 0x00000002 - 0x00000005 0x00000007 - 0x07050202 0x00130b0e - 0x73a91b0f 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b 0x80000040 - 0x00000004 0x00000005 - 0x00000013 0x0000000c - 0x0000000d 0x00000002 - 0x00000003 0x0000000c - 0x00000002 0x00000002 - 0x00000006 0x00000008 - 0x08060202 0x00170e13 - 0x736c2414 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d 0x80000040 - 0x00000005 0x00000006 - 0x00000016 0x0000000e - 0x0000000f 0x00000002 - 0x00000004 0x0000000e - 0x00000002 0x00000002 - 0x00000006 0x00000009 - 0x09060202 0x001a1016 - 0x734e2a17 0x70000f02 - 0x001f0000 - >; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 0x00000003 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000060 - 0x00000000 0x00000018 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000007 0x0000000f - 0x00000005 0x00000005 - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x00000064 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000007 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 0x00000005 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x0000009a - 0x00000000 0x00000026 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000007 0x0000000f - 0x00000006 0x00000006 - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x000000a0 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x0000000b 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 0x0000000a - 0x00000000 0x00000001 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000134 - 0x00000000 0x0000004d - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000008 0x0000000f - 0x0000000c 0x0000000c - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x0000013f - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000015 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 0x00000011 - 0x00000000 0x00000002 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000202 - 0x00000000 0x00000080 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x0000000f 0x0000000f - 0x00000013 0x00000013 - 0x00000004 0x00000005 - 0x00000004 0x00000001 - 0x00000000 0x00000005 - 0x00000005 0x00000213 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000022 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 0x0000001a - 0x00000000 0x00000003 - 0x00000001 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000001 - 0x00000001 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000304 - 0x00000000 0x000000c1 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000018 0x0000000f - 0x0000001c 0x0000001c - 0x00000004 0x00000005 - 0x00000004 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x0000031c - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000033 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 0x00000035 - 0x00000000 0x00000006 - 0x00000002 0x00000005 - 0x0000000a 0x00000005 - 0x0000000b 0x00000002 - 0x00000002 0x00000003 - 0x00000003 0x00000000 - 0x00000005 0x00000005 - 0x00000006 0x00000002 - 0x00000000 0x00000004 - 0x00000006 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000003 - 0x0000000d 0x0000000f - 0x00000011 0x00000607 - 0x00000000 0x00000181 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000032 0x0000000f - 0x00000038 0x00000038 - 0x00000004 0x00000005 - 0x00000004 0x00000006 - 0x00000000 0x00000005 - 0x00000005 0x00000638 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00008000 0x00000000 - 0x00000000 0x00008000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00090000 0x00090000 - 0x00090000 0x00090000 - 0x00009000 0x00009000 - 0x00009000 0x00009000 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000707 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000066 0x00000000 - 0x00000100 0x000e000e - 0x00000000 0x00000003 - 0x0000d2b3 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d 0x0000004d - 0x00000000 0x00000009 - 0x00000003 0x00000004 - 0x00000008 0x00000002 - 0x00000009 0x00000003 - 0x00000003 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000005 0x00000002 - 0x00000000 0x00000002 - 0x00000007 0x00020000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x0000000e 0x00000010 - 0x00000012 0x000008e4 - 0x00000000 0x00000239 - 0x00000001 0x00000008 - 0x00000001 0x00000000 - 0x0000004b 0x0000000e - 0x00000052 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000008 - 0x00000000 0x00000005 - 0x00000005 0x00000924 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0x002c00a0 0x00008000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00098000 0x00098000 - 0x00000000 0x00098000 - 0x00098000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00050000 0x00050000 - 0x00050000 0x00050000 - 0x00005000 0x00005000 - 0x00005000 0x00005000 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000096 0x00000000 - 0x00000100 0x0173000e - 0x00000000 0x00000003 - 0x000052a3 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 0x00000066 - 0x00000000 0x0000000c - 0x00000004 0x00000004 - 0x00000008 0x00000002 - 0x0000000a 0x00000004 - 0x00000004 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000005 0x00000002 - 0x00000000 0x00000001 - 0x00000008 0x00020000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000f 0x00000010 - 0x00000012 0x00000bd1 - 0x00000000 0x000002f4 - 0x00000001 0x00000008 - 0x00000001 0x00000000 - 0x00000063 0x0000000f - 0x0000006c 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x0000000b - 0x00000000 0x00000005 - 0x00000005 0x00000c11 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0x002c00a0 0x00008000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00070000 0x00070000 - 0x00000000 0x00070000 - 0x00070000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00038000 0x00038000 - 0x00038000 0x00038000 - 0x00003800 0x00003800 - 0x00003800 0x00003800 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x000000c6 0x00000000 - 0x00000100 0x015b000e - 0x00000000 0x00000003 - 0x000052a3 0x8000188b - 0x00000009 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 0x00000088 - 0x00000000 0x00000010 - 0x00000006 0x00000006 - 0x00000009 0x00000002 - 0x0000000d 0x00000006 - 0x00000006 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000006 0x00000002 - 0x00000000 0x00000001 - 0x00000009 0x00030000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000010 0x00000012 - 0x00000014 0x00000fd6 - 0x00000000 0x000003f5 - 0x00000002 0x0000000b - 0x00000001 0x00000000 - 0x00000085 0x00000012 - 0x00000090 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000010 - 0x00000000 0x00000006 - 0x00000006 0x00001017 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe01200b1 0x00008000 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00054000 0x00054000 - 0x00000000 0x00054000 - 0x00054000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x0139000e - 0x00000000 0x00000003 - 0x000042a0 0x80002062 - 0x0000000a - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b 0x0000009b - 0x00000000 0x00000013 - 0x00000007 0x00000007 - 0x0000000b 0x00000003 - 0x00000010 0x00000007 - 0x00000007 0x00000002 - 0x00000002 0x00000000 - 0x00000005 0x00000005 - 0x0000000a 0x00000002 - 0x00000000 0x00000003 - 0x0000000b 0x00070000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000002 - 0x00000012 0x00000016 - 0x00000018 0x00001208 - 0x00000000 0x00000482 - 0x00000002 0x0000000d - 0x00000001 0x00000000 - 0x00000097 0x00000015 - 0x000000a3 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000013 - 0x00000000 0x00000006 - 0x00000006 0x00001248 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe00e00b1 0x00008000 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00048000 0x00048000 - 0x00000000 0x00048000 - 0x00048000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x0127000e - 0x00000000 0x00000003 - 0x000040a0 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 0x000000cd - 0x00000000 0x00000019 - 0x0000000a 0x00000008 - 0x0000000d 0x00000004 - 0x00000013 0x0000000a - 0x0000000a 0x00000004 - 0x00000002 0x00000000 - 0x00000006 0x00000006 - 0x0000000b 0x00000002 - 0x00000000 0x00000002 - 0x0000000d 0x00080000 - 0x00000004 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x00000014 0x00000018 - 0x0000001a 0x000017e2 - 0x00000000 0x000005f8 - 0x00000003 0x00000011 - 0x00000001 0x00000000 - 0x000000c7 0x00000018 - 0x000000d7 0x00000200 - 0x00000005 0x00000006 - 0x00000005 0x00000019 - 0x00000000 0x00000008 - 0x00000008 0x00001822 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe00700b1 0x00008000 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00034000 0x00034000 - 0x00000000 0x00034000 - 0x00034000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000000 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x61861820 - 0x00514514 0x00514514 - 0x61861800 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x00f7000e - 0x00000000 0x00000004 - 0x00004080 0x80003012 - 0x0000000f - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emc-auto-cal-config = <0xa1430303>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000002b 0x000000f0 - 0x00000000 0x0000001e - 0x0000000b 0x00000009 - 0x0000000f 0x00000005 - 0x00000016 0x0000000b - 0x0000000b 0x00000004 - 0x00000002 0x00000000 - 0x00000007 0x00000007 - 0x0000000d 0x00000002 - 0x00000000 0x00000002 - 0x0000000f 0x000a0000 - 0x00000004 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x00000016 0x0000001a - 0x0000001c 0x00001be7 - 0x00000000 0x000006f9 - 0x00000004 0x00000015 - 0x00000001 0x00000000 - 0x000000e7 0x0000001b - 0x000000fb 0x00000200 - 0x00000006 0x00000007 - 0x00000006 0x0000001e - 0x00000000 0x0000000a - 0x0000000a 0x00001c28 - 0x00000000 0x00000000 - 0x00000000 0x104ab898 - 0xe00400b1 0x00008000 - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0002c000 0x0002c000 - 0x00000000 0x0002c000 - 0x0002c000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000000 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x5d75d720 - 0x00514514 0x00514514 - 0x5d75d700 0x0606003f - 0x00000000 0x00000000 - 0x00000128 0x00cd000e - 0x00000000 0x00000004 - 0x00004080 0x800037ea - 0x00000011 - >; - }; - }; - }; - - opp-table-actmon { - /delete-node/ opp-1200000000; - }; - - opp-table-emc { - /delete-node/ opp-1200000000-1100; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts deleted file mode 100644 index 2df2d8a6b552..000000000000 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016-2019 Toradex AG - */ - -/dts-v1/; - -#include -#include "tegra124-apalis.dtsi" - -/ { - model = "Toradex Apalis TK1 on Apalis Evaluation Board"; - compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", - "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@40"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@1003000 { - pci@1,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - gpio: gpio@6000d000 { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* - * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) - */ - i2c@7000c400 { - status = "okay"; - }; - - /* - * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor - * on carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* I2C4 (DDC): unused */ - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* SPI4: Apalis SPI2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* Apalis Serial ATA */ - sata@70020000 { - status = "okay"; - target-5v-supply = <®_5v0>; - target-12v-supply = <®_12v0>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - status = "okay"; - }; - - /* Apalis MMC1 */ - mmc@700b0000 { - status = "okay"; - bus-width = <4>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* Apalis SD1 */ - mmc@700b0400 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 3 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_12v0: regulator-12v0 { - compatible = "regulator-fixed"; - regulator-name = "12V_SW"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts deleted file mode 100644 index f4521fd15f6a..000000000000 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2016-2018 Toradex AG - */ - -/dts-v1/; - -#include -#include "tegra124-apalis-v1.2.dtsi" - -/ { - model = "Toradex Apalis TK1 on Apalis Evaluation Board"; - compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", - "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", - "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@40"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@1003000 { - pci@1,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - gpio@6000d000 { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor - * on carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* - * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 - * (e.g. display EDID) - */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* SPI4: Apalis SPI2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* Apalis Serial ATA */ - sata@70020000 { - status = "okay"; - target-5v-supply = <®_5v0>; - target-12v-supply = <®_12v0>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - status = "okay"; - }; - - /* Apalis MMC1 */ - mmc@700b0000 { - status = "okay"; - bus-width = <4>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* Apalis SD1 */ - mmc@700b0400 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 3 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_12v0: regulator-12v0 { - compatible = "regulator-fixed"; - regulator-name = "12V_SW"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi deleted file mode 100644 index 75cfe718737c..000000000000 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ /dev/null @@ -1,2076 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2016-2018 Toradex AG - */ - -#include "tegra124.dtsi" -#include "tegra124-apalis-emc.dtsi" - -/* - * Toradex Apalis TK1 Module Device Tree - * Compatible for Revisions 2GB: V1.2A - */ -/ { - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie@1003000 { - status = "okay"; - - avddio-pex-supply = <®_1v05_vdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - - /* Apalis PCIe (additional lane Apalis type specific) */ - pci@1,0 { - /* PCIE1_RX/TX and TS_DIFF1/2 */ - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1"; - }; - - /* I210 Gigabit Ethernet Controller (On-module) */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - - ethernet@0,0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - gpu@57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <®_vdd_gpu>; - }; - - gpio@6000d000 { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-din-pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-dout-pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-sclk-pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_ON */ - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAM1_MCLK */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-sclk-pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-din-pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-dout-pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { /* DAP1_RESET */ - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-out-pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis GPIO */ - usb-vbus-en0-pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb-vbus-en1-pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-rst-n-pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-clkreq-n-pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp-hpd-pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis HDMI1_CEC */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis HDMI1_HPD */ - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1-i2c-sda-pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam-i2c-sda-pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C4 (DDC) */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc-sda-pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis MMC1 */ - sdmmc1-cd-n-pv3 { /* CD# GPIO */ - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-out-pw5 { /* D5 GPIO */ - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat3-py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat2-py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat1-py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat0-py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-req-pcc5 { /* D4 GPIO */ - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb-vbus-en2-pff1 { /* D7 GPIO */ - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM */ - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SATA1_ACT# */ - dap1-dout-pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cmd-pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat3-pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat2-pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat1-pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cd-n-pv2 { /* CD# GPIO */ - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-dir-py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-nxt-py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-stp-py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI2 */ - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - pb1 { /* DCD GPIO */ - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { /* RI GPIO */ - nvidia,pins = "pk7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-txd-pu0 { - nvidia,pins = "pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rxd-pu1 { - nvidia,pins = "pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-cts-n-pu2 { - nvidia,pins = "pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rts-n-pu3 { - nvidia,pins = "pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-cts-n-pa1 { /* DSR GPIO */ - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rts-n-pc0 { /* DTR GPIO */ - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART2 */ - uart2-txd-pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rts-n-pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART3 */ - uart3-txd-pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART4 */ - uart4-rxd-pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart4-txd-pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_EN */ - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBH_OC# */ - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBO1_OC# */ - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CORE_PWR_REQ */ - core-pwr-req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CPU_PWR_REQ */ - cpu-pwr-req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* DVFS */ - dvfs-pwm-px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs-clk-px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC */ - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat1-paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat2-paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat3-paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat4-paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat5-paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat6-paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat7-paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-cmd-pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* JTAG_RTCK */ - jtag-rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_DEV_OFF# */ - ulpi-data5-po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_RESET# */ - kb-row10-ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_WAKE# */ - ulpi-data4-po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT1# */ - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT2# */ - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT3# */ - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT4# */ - pj0 { - nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_RESET */ - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU SPI */ - gpio-x4-aud-px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x5-aud-px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x6-aud-px6 { /* MCU_CS */ - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x7-aud-px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-w2-aud-pw2 { /* MCU_CSEZP */ - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CLK_32K */ - clk-32k-in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CPU_OC_INT */ - clk-32k-out-pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PWR_I2C */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr-i2c-sda-pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* PWR_INT_N */ - pwr-int-n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_MOCI_CTRL */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_OUT_N */ - reset-out-n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_IN */ - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row1-pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Configure level-shifter as output for HDA */ - kb-row11-ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_OUT */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col7-pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_OE */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col1-pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col4-pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row2-pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_INT */ - gpio-w3-aud-pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pc7 { /* NC */ - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { /* NC */ - nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { /* NC */ - nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { /* NC */ - nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { /* NC */ - nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { /* NC */ - nvidia,pins = "pg4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { /* NC */ - nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { /* NC */ - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { /* NC */ - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { /* NC */ - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { /* NC */ - nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { /* NC */ - nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { /* NC */ - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { /* NC */ - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { /* NC */ - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { /* NC */ - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { /* NC */ - nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { /* NC */ - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { /* NC */ - nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { /* NC */ - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-din-pn1 { /* NC */ - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-sclk-pn3 { /* NC */ - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data7-po0 { /* NC */ - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data0-po1 { /* NC */ - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data1-po2 { /* NC */ - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data2-po3 { /* NC */ - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data3-po4 { /* NC */ - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data6-po7 { /* NC */ - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-fs-pp4 { /* NC */ - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-din-pp5 { /* NC */ - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-dout-pp6 { /* NC */ - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-sclk-pp7 { /* NC */ - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col3-pq3 { /* NC */ - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row3-pr3 { /* NC */ - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row4-pr4 { /* NC */ - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { /* NC */ - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row6-pr6 { /* NC */ - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row7-pr7 { /* NC */ - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row8-ps0 { /* NC */ - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row9-ps1 { /* NC */ - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row12-ps4 { /* NC */ - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row13-ps5 { /* NC */ - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row14-ps6 { /* NC */ - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row15-ps7 { /* NC */ - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row16-pt0 { /* NC */ - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row17-pt1 { /* NC */ - nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { /* NC */ - nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * PCB Version Indication: V1.2 and later have GPIO_PV0 - * wired to GND, was NC before - */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { /* NC */ - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x1-aud-px1 { /* NC */ - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x3-aud-px3 { /* NC */ - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { /* NC */ - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { /* NC */ - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { /* NC */ - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-req-pee1 { /* NC */ - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-req-pee2 { /* NC */ - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output - * driver enabled aka not tristated and input driver - * enabled as well as it features some magic properties - * even though the external loopback is disabled and the - * internal loopback used as per - * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 - * bits being set to 0xfffd according to the TRM! - */ - sdmmc3-clk-lb-out-pee4 { /* NC */ - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006200 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006300 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vddio>; - VDDIO-supply = <®_1v8_vddio>; - clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; - - gpio2-7 { - pins = "gpio2", /* PWR_EN_+V3.3 */ - "gpio7"; /* +V1.6_LPO */ - function = "gpio"; - bias-pull-up; - }; - }; - - regulators { - vsup-sd2-supply = <®_module_3v3>; - vsup-sd3-supply = <®_module_3v3>; - vsup-sd4-supply = <®_module_3v3>; - vsup-sd5-supply = <®_module_3v3>; - vin-ldo0-supply = <®_1v35_vddio_ddr>; - vin-ldo1-6-supply = <®_module_3v3>; - vin-ldo2-5-7-supply = <®_1v8_vddio>; - vin-ldo3-4-supply = <®_module_3v3>; - vin-ldo9-10-supply = <®_module_3v3>; - vin-ldo11-supply = <®_module_3v3>; - - reg_vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - reg_1v35_vddio_ddr: sd2 { - regulator-name = - "+V1.35_VDDIO_DDR(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = - "+V1.35_VDDIO_DDR(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_1v05_vdd: sd4 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - reg_1v8_vddio: sd5 { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1v05_avdd: ldo0 { - regulator-name = "+V1.05_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - vddio_sdmmc1: ldo1 { - regulator-name = "VDDIO_SDMMC1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "+V1.2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+V1.05_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - /* 1.8V for LVDS, 3.3V for eDP */ - ldo4 { - regulator-name = "AVDD_LVDS0_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* LDO5 not used */ - - vddio_sdmmc3: ldo6 { - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* LDO7 not used */ - - ldo9 { - regulator-name = "+V3.3_ETH(ldo9)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo10 { - regulator-name = "+V3.3_ETH(ldo10)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo11 { - regulator-name = "+V1.8_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - /* - * TMP451 temperature sensor - * Note: THERM_N directly connected to AS3722 PMIC THERM - */ - temp-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; - vcc-supply = <®_module_3v3>; - }; - }; - - /* SPI2: MCU SPI */ - spi@7000d600 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set power_off bit in ResetControl register of AS3722 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - sata@70020000 { - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - avdd-supply = <®_1v05_vdd>; - hvdd-supply = <®_module_3v3>; - vddio-supply = <®_1v05_vdd>; - }; - - usb@70090000 { - /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-usb-ss-pll-supply = <®_1v05_vdd>; - avdd-usb-supply = <®_module_3v3>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-usb-ss-pll-e-supply = <®_module_3v3>; - hvdd-usb-ss-supply = <®_module_3v3>; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-1 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-2 { - status = "okay"; - nvidia,function = "xusb"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-1 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-2 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-3 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-4 { - status = "okay"; - nvidia,function = "pcie"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - status = "okay"; - nvidia,function = "sata"; - }; - }; - }; - }; - - ports { - /* USBO1 */ - usb2-0 { - status = "okay"; - mode = "otg"; - usb-role-switch; - vbus-supply = <®_usbo1_vbus>; - }; - - /* USBH2 */ - usb2-1 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - /* USBH4 */ - usb2-2 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-0 { - status = "okay"; - nvidia,usb2-companion = <2>; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-1 { - status = "okay"; - nvidia,usb2-companion = <0>; - vbus-supply = <®_usbo1_vbus>; - }; - }; - }; - - /* eMMC */ - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - nvidia,i2c-fs-rate = <400000>; - vdd-cpu-supply = <®_vdd_cpu>; - }; - - ahub@70300000 { - i2s@70301200 { - status = "okay"; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <®_vdd_cpu>; - }; - }; - - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.05_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <®_1v05_vdd>; - }; - - reg_3v3_mxm: regulator-3v3-mxm { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_MXM"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_1v05_vdd>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - /* PWR_EN_+V3.3 */ - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3_mxm>; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis TK1"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - thermal-zones { - cpu-thermal { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem-thermal { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu-thermal { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi deleted file mode 100644 index 554c8089491c..000000000000 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ /dev/null @@ -1,2068 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016-2019 Toradex AG - */ - -#include "tegra124.dtsi" -#include "tegra124-apalis-emc.dtsi" - -/* - * Toradex Apalis TK1 Module Device Tree - * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A - */ -/ { - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie@1003000 { - status = "okay"; - avddio-pex-supply = <®_1v05_vdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - - /* Apalis PCIe (additional lane Apalis type specific) */ - pci@1,0 { - /* PCIE1_RX/TX and TS_DIFF1/2 */ - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1"; - }; - - /* I210 Gigabit Ethernet Controller (On-module) */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - - ethernet@0,0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - gpu@57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <®_vdd_gpu>; - }; - - gpio@6000d000 { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-din-pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-dout-pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-sclk-pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_ON */ - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAM1_MCLK */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-sclk-pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-din-pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-dout-pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { /* DAP1_RESET */ - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-out-pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis GPIO */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc-sda-pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-rst-n-pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-clkreq-n-pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp-hpd-pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis HDMI1_CEC */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis HDMI1_HPD */ - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1-i2c-sda-pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam-i2c-sda-pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis MMC1 */ - sdmmc1-cd-n-pv3 { /* CD# GPIO */ - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-out-pw5 { /* D5 GPIO */ - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat3-py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat2-py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat1-py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat0-py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-req-pcc5 { /* D4 GPIO */ - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb-vbus-en2-pff1 { /* D7 GPIO */ - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM */ - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SATA1_ACT# */ - dap1-dout-pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cmd-pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat3-pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat2-pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat1-pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cd-n-pv2 { /* CD# GPIO */ - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-dir-py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-nxt-py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-stp-py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI2 */ - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - pb1 { /* DCD GPIO */ - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { /* RI GPIO */ - nvidia,pins = "pk7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-txd-pu0 { - nvidia,pins = "pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rxd-pu1 { - nvidia,pins = "pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-cts-n-pu2 { - nvidia,pins = "pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rts-n-pu3 { - nvidia,pins = "pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-cts-n-pa1 { /* DSR GPIO */ - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rts-n-pc0 { /* DTR GPIO */ - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART2 */ - uart2-txd-pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rts-n-pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART3 */ - uart3-txd-pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART4 */ - uart4-rxd-pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart4-txd-pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_EN */ - usb-vbus-en1-pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBH_OC# */ - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - usb-vbus-en0-pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBO1_OC# */ - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CORE_PWR_REQ */ - core-pwr-req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CPU_PWR_REQ */ - cpu-pwr-req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* DVFS */ - dvfs-pwm-px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs-clk-px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC */ - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat1-paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat2-paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat3-paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat4-paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat5-paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat6-paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat7-paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-cmd-pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* JTAG_RTCK */ - jtag-rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_DEV_OFF# */ - ulpi-data5-po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_RESET# */ - kb-row10-ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_WAKE# */ - ulpi-data4-po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT1# */ - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT2# */ - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT3# */ - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT4# */ - pj0 { - nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_RESET */ - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU SPI */ - gpio-x4-aud-px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x5-aud-px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x6-aud-px6 { /* MCU_CS */ - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x7-aud-px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-w2-aud-pw2 { /* MCU_CSEZP */ - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CLK_32K */ - clk-32k-in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CPU_OC_INT */ - clk-32k-out-pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PWR_I2C */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr-i2c-sda-pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* PWR_INT_N */ - pwr-int-n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_MOCI_CTRL */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_OUT_N */ - reset-out-n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_IN */ - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row1-pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Configure level-shifter as output for HDA */ - kb-row11-ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_OUT */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col7-pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_OE */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col1-pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col4-pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row2-pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_INT */ - gpio-w3-aud-pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pc7 { /* NC */ - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { /* NC */ - nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { /* NC */ - nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { /* NC */ - nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { /* NC */ - nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { /* NC */ - nvidia,pins = "pg4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { /* NC */ - nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { /* NC */ - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { /* NC */ - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { /* NC */ - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { /* NC */ - nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { /* NC */ - nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { /* NC */ - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { /* NC */ - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { /* NC */ - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { /* NC */ - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { /* NC */ - nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { /* NC */ - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { /* NC */ - nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { /* NC */ - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-din-pn1 { /* NC */ - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-sclk-pn3 { /* NC */ - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data7-po0 { /* NC */ - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data0-po1 { /* NC */ - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data1-po2 { /* NC */ - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data2-po3 { /* NC */ - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data3-po4 { /* NC */ - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data6-po7 { /* NC */ - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-fs-pp4 { /* NC */ - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-din-pp5 { /* NC */ - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-dout-pp6 { /* NC */ - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-sclk-pp7 { /* NC */ - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col3-pq3 { /* NC */ - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row3-pr3 { /* NC */ - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row4-pr4 { /* NC */ - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { /* NC */ - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row6-pr6 { /* NC */ - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row7-pr7 { /* NC */ - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row8-ps0 { /* NC */ - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row9-ps1 { /* NC */ - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row12-ps4 { /* NC */ - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row13-ps5 { /* NC */ - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row14-ps6 { /* NC */ - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row15-ps7 { /* NC */ - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row16-pt0 { /* NC */ - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row17-pt1 { /* NC */ - nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { /* NC */ - nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { /* NC */ - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { /* NC */ - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x1-aud-px1 { /* NC */ - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x3-aud-px3 { /* NC */ - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { /* NC */ - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { /* NC */ - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { /* NC */ - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-req-pee1 { /* NC */ - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-req-pee2 { /* NC */ - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output - * driver enabled aka not tristated and input driver - * enabled as well as it features some magic properties - * even though the external loopback is disabled and the - * internal loopback used as per - * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 - * bits being set to 0xfffd according to the TRM! - */ - sdmmc3-clk-lb-out-pee4 { /* NC */ - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006200 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006300 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - hdmi_ddc: i2c@7000c400 { - clock-frequency = <10000>; - }; - - /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vddio>; - VDDIO-supply = <®_1v8_vddio>; - clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; - - gpio2-7 { - pins = "gpio2", /* PWR_EN_+V3.3 */ - "gpio7"; /* +V1.6_LPO */ - function = "gpio"; - bias-pull-up; - }; - }; - - regulators { - vsup-sd2-supply = <®_module_3v3>; - vsup-sd3-supply = <®_module_3v3>; - vsup-sd4-supply = <®_module_3v3>; - vsup-sd5-supply = <®_module_3v3>; - vin-ldo0-supply = <®_1v35_vddio_ddr>; - vin-ldo1-6-supply = <®_module_3v3>; - vin-ldo2-5-7-supply = <®_1v8_vddio>; - vin-ldo3-4-supply = <®_module_3v3>; - vin-ldo9-10-supply = <®_module_3v3>; - vin-ldo11-supply = <®_module_3v3>; - - reg_vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - reg_1v35_vddio_ddr: sd2 { - regulator-name = - "+V1.35_VDDIO_DDR(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = - "+V1.35_VDDIO_DDR(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_1v05_vdd: sd4 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - reg_1v8_vddio: sd5 { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1v05_avdd: ldo0 { - regulator-name = "+V1.05_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - vddio_sdmmc1: ldo1 { - regulator-name = "VDDIO_SDMMC1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "+V1.2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+V1.05_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - /* 1.8V for LVDS, 3.3V for eDP */ - ldo4 { - regulator-name = "AVDD_LVDS0_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* LDO5 not used */ - - vddio_sdmmc3: ldo6 { - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* LDO7 not used */ - - ldo9 { - regulator-name = "+V3.3_ETH(ldo9)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo10 { - regulator-name = "+V3.3_ETH(ldo10)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo11 { - regulator-name = "+V1.8_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - /* - * TMP451 temperature sensor - * Note: THERM_N directly connected to AS3722 PMIC THERM - */ - temp-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; - vcc-supply = <®_module_3v3>; - }; - }; - - /* SPI2: MCU SPI */ - spi@7000d600 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set power_off bit in ResetControl register of AS3722 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - sata@70020000 { - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - avdd-supply = <®_1v05_vdd>; - hvdd-supply = <®_module_3v3>; - vddio-supply = <®_1v05_vdd>; - }; - - usb@70090000 { - /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-usb-ss-pll-supply = <®_1v05_vdd>; - avdd-usb-supply = <®_module_3v3>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-usb-ss-pll-e-supply = <®_module_3v3>; - hvdd-usb-ss-supply = <®_module_3v3>; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-1 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-2 { - status = "okay"; - nvidia,function = "xusb"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-1 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-2 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-3 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-4 { - status = "okay"; - nvidia,function = "pcie"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - status = "okay"; - nvidia,function = "sata"; - }; - }; - }; - }; - - ports { - /* USBO1 */ - usb2-0 { - status = "okay"; - mode = "otg"; - usb-role-switch; - vbus-supply = <®_usbo1_vbus>; - }; - - /* USBH2 */ - usb2-1 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - /* USBH4 */ - usb2-2 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-0 { - status = "okay"; - nvidia,usb2-companion = <2>; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-1 { - status = "okay"; - nvidia,usb2-companion = <0>; - vbus-supply = <®_usbo1_vbus>; - }; - }; - }; - - /* eMMC */ - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - nvidia,i2c-fs-rate = <400000>; - vdd-cpu-supply = <®_vdd_cpu>; - }; - - ahub@70300000 { - i2s@70301200 { - status = "okay"; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <®_vdd_cpu>; - }; - }; - - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.05_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <®_1v05_vdd>; - }; - - reg_3v3_mxm: regulator-3v3-mxm { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_MXM"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_1v05_vdd>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - /* PWR_EN_+V3.3 */ - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3_mxm>; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis TK1"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - thermal-zones { - cpu-thermal { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem-thermal { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu-thermal { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi deleted file mode 100644 index d10e5334a6c6..000000000000 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ /dev/null @@ -1,2443 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -/ { - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-924000000 { - clock-frequency = <924000000>; - nvidia,parent-clock-frequency = <924000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0503 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000004 - 0x00000002 - 0x00000003 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0504 - 0x73840a05 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000006 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000007 - 0x00000008 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090c - 0x7428180d - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000a - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000d - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00170e13 - 0x736c2414 - 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d - 0x80000040 - 0x00000005 - 0x00000006 - 0x00000016 - 0x0000000e - 0x0000000f - 0x00000002 - 0x00000004 - 0x0000000e - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000009 - 0x09060202 - 0x001a1016 - 0x734e2a17 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000006 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000006 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00008000 - 0x00000000 - 0x00000000 - 0x00008000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000707 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004d - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004b - 0x0000000e - 0x00000052 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000008 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0173000e - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 - 0x00000066 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006c - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000b - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00003800 - 0x00003800 - 0x00003800 - 0x00003800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000e - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 - 0x00000088 - 0x00000000 - 0x00000010 - 0x00000006 - 0x00000006 - 0x00000009 - 0x00000002 - 0x0000000d - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000009 - 0x00030000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000010 - 0x00000012 - 0x00000014 - 0x00000fd6 - 0x00000000 - 0x000003f5 - 0x00000002 - 0x0000000b - 0x00000001 - 0x00000000 - 0x00000085 - 0x00000012 - 0x00000090 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000010 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001017 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe01200b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00054000 - 0x00054000 - 0x00000000 - 0x00054000 - 0x00054000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0139000e - 0x00000000 - 0x00000003 - 0x000042a0 - 0x80002062 - 0x0000000a - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b - 0x0000009b - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000097 - 0x00000015 - 0x000000a3 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000013 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0127000e - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 - 0x000000cd - 0x00000000 - 0x00000019 - 0x0000000a - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x0000000a - 0x0000000a - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c7 - 0x00000018 - 0x000000d7 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x00000019 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00700b1 - 0x00008000 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000000 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00514514 - 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f7000e - 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emc-auto-cal-config = <0xa1430303>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000002b - 0x000000f0 - 0x00000000 - 0x0000001e - 0x0000000b - 0x00000009 - 0x0000000f - 0x00000005 - 0x00000016 - 0x0000000b - 0x0000000b - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000007 - 0x00000007 - 0x0000000d - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000f - 0x000a0000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000016 - 0x0000001a - 0x0000001c - 0x00001be7 - 0x00000000 - 0x000006f9 - 0x00000004 - 0x00000015 - 0x00000001 - 0x00000000 - 0x000000e7 - 0x0000001b - 0x000000fb - 0x00000200 - 0x00000006 - 0x00000007 - 0x00000006 - 0x0000001e - 0x00000000 - 0x0000000a - 0x0000000a - 0x00001c28 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab898 - 0xe00400b1 - 0x00008000 - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000000 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x5d75d720 - 0x00514514 - 0x00514514 - 0x5d75d700 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000128 - 0x00cd000e - 0x00000000 - 0x00000004 - 0x00004080 - 0x800037ea - 0x00000011 - >; - }; - }; - }; - - opp-table-actmon { - /delete-node/ opp-1200000000; - }; - - opp-table-emc { - /delete-node/ opp-1200000000-1100; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts deleted file mode 100644 index 4196f2401c90..000000000000 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ /dev/null @@ -1,2080 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra124.dtsi" - -#include "tegra124-jetson-tk1-emc.dtsi" - -/ { - model = "NVIDIA Tegra124 Jetson TK1"; - compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - - /* This order keeps the mapping DB9 connector <-> ttyS0 */ - serial0 = &uartd; - serial1 = &uarta; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie@1003000 { - status = "okay"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-supply = <&vdd_3v3_lp0>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - vddio-pex-ctl-supply = <&vdd_3v3_lp0>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - - /* Mini PCIe */ - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - - /* Gigabit Ethernet */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - vdd-supply = <&vdd_3v3_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - gpu@57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vimclk2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dsi_b { - nvidia,pins = "mipi_pad_ctrl_dsi_b"; - nvidia,function = "dsi_b"; - }; - }; - }; - - /* - * First high speed UART, exposed on the expansion connector J3A2 - * Pin 41: BR_UART1_TXD - * Pin 44: BR_UART1_RXD - */ - serial@70006000 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - }; - - /* - * Second high speed UART, exposed on the expansion connector J3A2 - * Pin 65: UART2_RXD - * Pin 68: UART2_TXD - * Pin 71: UART2_CTS_L - * Pin 74: UART2_RTS_L - */ - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - }; - - /* DB9 serial port */ - serial@70006300 { - status = "okay"; - }; - - /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - rt5639: audio-codec@1c { - compatible = "realtek,rt5639"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - pagesize = <8>; - }; - }; - - /* Expansion GEN2_I2C_* */ - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion CAM_I2C_* */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion PWR_I2C_*, on-board components */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_5_6 { - pins = "gpio3", "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.05V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - ldo4 { - regulator-name = "+2.8V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+3.3V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - /* Expansion TS_SPI_* */ - spi@7000d400 { - status = "okay"; - }; - - /* Internal SPI */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - cec@70015000 { - status = "okay"; - }; - - /* Serial ATA */ - sata@70020000 { - status = "okay"; - - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - - hvdd-supply = <&vdd_3v3_lp0>; - vddio-supply = <&vdd_1v05_run>; - avdd-supply = <&vdd_1v05_run>; - - target-5v-supply = <&vdd_5v0_sata>; - target-12v-supply = <&vdd_12v0_sata>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "snps"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "host"; - }; - - /* Mini PCIe */ - usb2-1 { - status = "okay"; - mode = "host"; - }; - - /* USB3 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - /* SD card */ - mmc@700b0400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* eMMC */ - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - /* mini-PCIe USB */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - }; - - /* USB A connector */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - vdd_mux: regulator-mux { - compatible = "regulator-fixed"; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator-5v0sys { - compatible = "regulator-fixed"; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator-3v3sys { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator-3v3run { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator-3v3hdmi { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "+USB0_VBUS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_lp0: regulator-lp0 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator-hdmipll { - compatible = "regulator-fixed"; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator-hdmicon { - compatible = "regulator-fixed"; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - /* Molex power connector */ - vdd_5v0_sata: regulator-5v0sata { - compatible = "regulator-fixed"; - regulator-name = "+5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_12v0_sata: regulator-12v0sata { - compatible = "regulator-fixed"; - regulator-name = "+12V_SATA"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Jetson TK1"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5639>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - thermal-zones { - cpu-thermal { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem-thermal { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu-thermal { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi deleted file mode 100644 index cadb1969f1cc..000000000000 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ /dev/null @@ -1,6694 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - apbmisc@70000800 { - nvidia,long-ram-code; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77430303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75430403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ - 0x7488180d /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x74691b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ - 0x746c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000005 /* EMC_DLL_XFORM_DQS0 */ - 0x00000005 /* EMC_DLL_XFORM_DQS1 */ - 0x00000005 /* EMC_DLL_XFORM_DQS2 */ - 0x00000005 /* EMC_DLL_XFORM_DQS3 */ - 0x00000005 /* EMC_DLL_XFORM_DQS4 */ - 0x00000005 /* EMC_DLL_XFORM_DQS5 */ - 0x00000005 /* EMC_DLL_XFORM_DQS6 */ - 0x00000005 /* EMC_DLL_XFORM_DQS7 */ - 0x00000005 /* EMC_DLL_XFORM_DQS8 */ - 0x00000005 /* EMC_DLL_XFORM_DQS9 */ - 0x00000005 /* EMC_DLL_XFORM_DQS10 */ - 0x00000005 /* EMC_DLL_XFORM_DQS11 */ - 0x00000005 /* EMC_DLL_XFORM_DQS12 */ - 0x00000005 /* EMC_DLL_XFORM_DQS13 */ - 0x00000005 /* EMC_DLL_XFORM_DQS14 */ - 0x00000005 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x0000000a /* EMC_DLL_XFORM_DQ4 */ - 0x0000000a /* EMC_DLL_XFORM_DQ5 */ - 0x0000000a /* EMC_DLL_XFORM_DQ6 */ - 0x0000000a /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000004 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000e /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000f /* EMC_TXSR */ - 0x0000000f /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000017 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000015 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000019 /* EMC_TXSR */ - 0x00000019 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x00000023 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000021 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000025 /* EMC_TXSR */ - 0x00000025 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000047 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000006 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000044 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000004a /* EMC_TXSR */ - 0x0000004a /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000321>; - nvidia,emc-mrs-wait-cnt = <0x0117000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x00000067 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000065 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0117000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000521>; - nvidia,emc-mrs-wait-cnt = <0x00f5000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 /* EMC_RC */ - 0x00000089 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000087 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000941>; - nvidia,emc-mrs-wait-cnt = <0x00c8000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x000000b7 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000010 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000b4 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x000000bf /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000b61>; - nvidia,emc-mrs-wait-cnt = <0x00b0000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b /* EMC_RC */ - 0x000000d0 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000cc /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000d71>; - nvidia,emc-mrs-wait-cnt = <0x006f000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 /* EMC_RC */ - 0x00000114 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000019 /* EMC_RAS */ - 0x0000000a /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x0000000a /* EMC_RD_RCD */ - 0x0000000a /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000010d /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x0000011e /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ - 0x007f400c /* EMC_DLL_XFORM_DQS2 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ - 0x007f400c /* EMC_DLL_XFORM_DQS10 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00492492 /* EMC_XM2DQSPADCTRL4 */ - 0x00492492 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x006f000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000009 /* EMC_DLL_XFORM_DQS0 */ - 0x00000009 /* EMC_DLL_XFORM_DQS1 */ - 0x00000009 /* EMC_DLL_XFORM_DQS2 */ - 0x00000007 /* EMC_DLL_XFORM_DQS3 */ - 0x00000006 /* EMC_DLL_XFORM_DQS4 */ - 0x00000006 /* EMC_DLL_XFORM_DQS5 */ - 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ - 0x00000006 /* EMC_DLL_XFORM_DQS7 */ - 0x00000009 /* EMC_DLL_XFORM_DQS8 */ - 0x00000009 /* EMC_DLL_XFORM_DQS9 */ - 0x00000009 /* EMC_DLL_XFORM_DQS10 */ - 0x00000007 /* EMC_DLL_XFORM_DQS11 */ - 0x00000006 /* EMC_DLL_XFORM_DQS12 */ - 0x00000007 /* EMC_DLL_XFORM_DQS13 */ - 0x00000009 /* EMC_DLL_XFORM_DQS14 */ - 0x00000007 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - }; - - opp-table-actmon { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; - }; - - opp-table-emc { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts deleted file mode 100644 index 4db43324dafa..000000000000 --- a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra124-nyan-big.dts" - -/ { - /* Version of Nyan Big with 1080p panel */ - host1x@50000000 { - dpaux@545c0000 { - aux-bus { - panel: panel { - compatible = "auo,b133htn01"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts deleted file mode 100644 index 8bca9599ad6e..000000000000 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ /dev/null @@ -1,1348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra124-nyan.dtsi" - -#include "tegra124-nyan-big-emc.dtsi" - -/ { - model = "Acer Chromebook 13 CB5-311"; - compatible = "google,nyan-big-rev7", "google,nyan-big-rev6", - "google,nyan-big-rev5", "google,nyan-big-rev4", - "google,nyan-big-rev3", "google,nyan-big-rev2", - "google,nyan-big-rev1", "google,nyan-big-rev0", - "google,nyan-big", "google,nyan", "nvidia,tegra124"; - - host1x@50000000 { - dpaux@545c0000 { - aux-bus { - panel: panel { - compatible = "auo,b133xtn01"; - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - }; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - mmc@700b0400 { /* SD Card on this bus */ - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi deleted file mode 100644 index e8dcc4f51fc5..000000000000 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ /dev/null @@ -1,2071 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - - /* TODO: Add 528MHz frequency */ - - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000d - 0x00000008 - 0x0000000a - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090d - 0x7428180e - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000007 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000007 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004c - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004a - 0x0000000e - 0x00000051 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000009 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0174000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 - 0x00000065 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006b - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000d - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00068000 - 0x00068000 - 0x00000000 - 0x00068000 - 0x00068000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00058000 - 0x00058000 - 0x00058000 - 0x00058000 - 0x00005800 - 0x00005800 - 0x00005800 - 0x00005800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c - 0x0000009a - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000096 - 0x00000015 - 0x000000a2 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000015 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00040000 - 0x00040000 - 0x00000000 - 0x00040000 - 0x00040000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000005 - 0x00000007 - 0x00000004 - 0x00000006 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000005 - 0x00000007 - 0x00000004 - 0x00000006 - 0x00000007 - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0128000c - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024a9 - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 - 0x000000cc - 0x00000000 - 0x0000001a - 0x00000009 - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x00000009 - 0x00000009 - 0x00000003 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c6 - 0x00000018 - 0x000000d6 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x0000001d - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00700b1 - 0x00008000 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000008 - 0x0000000a - 0x00000008 - 0x0000000a - 0x0000000a - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000008 - 0x0000000a - 0x00000008 - 0x0000000a - 0x0000000a - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00492492 - 0x00492492 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f8000c - 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - }; - }; - - opp-table-actmon { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; - }; - - opp-table-emc { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts deleted file mode 100644 index 432540c10065..000000000000 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ /dev/null @@ -1,1346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra124-nyan.dtsi" - -#include "tegra124-nyan-blaze-emc.dtsi" - -/ { - model = "HP Chromebook 14"; - compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9", - "google,nyan-blaze-rev8", "google,nyan-blaze-rev7", - "google,nyan-blaze-rev6", "google,nyan-blaze-rev5", - "google,nyan-blaze-rev4", "google,nyan-blaze-rev3", - "google,nyan-blaze-rev2", "google,nyan-blaze-rev1", - "google,nyan-blaze-rev0", "google,nyan-blaze", - "google,nyan", "nvidia,tegra124"; - - host1x@50000000 { - dpaux@545c0000 { - aux-bus { - panel: panel { - compatible = "samsung,ltn140at29-301"; - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - }; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-blaze", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBlaze"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi deleted file mode 100644 index 56952333ae28..000000000000 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ /dev/null @@ -1,836 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include "tegra124.dtsi" - -/ { - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* - * Note that recent version of the device tree compiler (starting with - * version 1.4.2) warn about this node containing a reg property, but - * missing a unit-address. However, the bootloader on these Chromebook - * devices relies on the full name of this node to be exactly /memory. - * Adding the unit-address causes the bootloader to create a /memory - * node and write the memory bank configuration to that node, which in - * turn leads the kernel to believe that the device has 2 GiB of - * memory instead of the amount detected by the bootloader. - * - * The name of this node is effectively ABI and must not be changed. - */ - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - /delete-node/ memory@80000000; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; - vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - gpu@57000000 { - status = "okay"; - - vdd-supply = <&vdd_gpu>; - }; - - serial@70006000 { - /* Debug connector on the bottom of the board near SD card. */ - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - tmp451: temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio>; - interrupts = ; - wakeup-source; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - ti,external-control; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&charger>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <0>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - cec@70015000 { - status = "okay"; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - vbus-supply = <&vdd_usb1_vbus>; - status = "okay"; - mode = "otg"; - usb-role-switch; - }; - - usb2-1 { - vbus-supply = <&vdd_run_cam>; - status = "okay"; - mode = "host"; - }; - - usb2-2 { - vbus-supply = <&vdd_usb3_vbus>; - status = "okay"; - mode = "host"; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - }; - }; - - mmc@700b0000 { /* WiFi/BT on this bus */ - status = "okay"; - bus-width = <4>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&sdhci0_pwrseq>; - vmmc-supply = <&vdd_3v3_lp0>; - vqmmc-supply = <&vddio_1v8>; - keep-power-in-suspend; - }; - - mmc@700b0400 { /* SD Card on this bus */ - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - no-1-8-v; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - mmc@700b0600 { /* eMMC on this bus */ - status = "okay"; - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - default-brightness-level = <224>; - brightness-levels = - < 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - 256>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - #cooling-cells = <2>; - vdd-cpu-supply = <&vdd_cpu>; - }; - - cpu1: cpu@1 { - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - #cooling-cells = <2>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; - - switch-lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = ; - debounce-interval = <1>; - wakeup-source; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - priority = <200>; - }; - - sdhci0_pwrseq: pwrseq-sdhci0 { - compatible = "mmc-pwrseq-simple"; - - reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - - vdd_mux: regulator-mux { - compatible = "regulator-fixed"; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator-5v0sys { - compatible = "regulator-fixed"; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator-3v3sys { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator-3v3run { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator-3v3hdmi { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator-led { - compatible = "regulator-fixed"; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator-ts { - compatible = "regulator-fixed"; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator-lp0 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator-hdmipll { - compatible = "regulator-fixed"; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator-hdmicon { - compatible = "regulator-fixed"; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "DMICL", "Int Mic", - "DMICR", "Int Mic", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; - nvidia,mic-det-gpios = - <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - }; - - thermal-zones { - cpu-skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tmp451 0>; - - trips { - cpu_passive_trip: cpu-alert0 { - /* throttle at 70C until temperature drops to 69.8C */ - temperature = <70000>; - hysteresis = <200>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_passive_trip>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi deleted file mode 100644 index b262c1289da5..000000000000 --- a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - emc_icc_dvfs_opp_table: opp-table-emc { - compatible = "operating-points-v2"; - - opp-12750000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0003>; - }; - - opp-12750000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0008>; - }; - - opp-12750000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0010>; - }; - - opp-12750000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0004>; - }; - - opp-20400000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <20400000>; - opp-supported-hw = <0x0003>; - }; - - opp-20400000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <20400000>; - opp-supported-hw = <0x0008>; - }; - - opp-20400000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <20400000>; - opp-supported-hw = <0x0010>; - }; - - opp-20400000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <20400000>; - opp-supported-hw = <0x0004>; - }; - - opp-40800000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <40800000>; - opp-supported-hw = <0x0003>; - }; - - opp-40800000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <40800000>; - opp-supported-hw = <0x0008>; - }; - - opp-40800000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <40800000>; - opp-supported-hw = <0x0010>; - }; - - opp-40800000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <40800000>; - opp-supported-hw = <0x0004>; - }; - - opp-68000000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <68000000>; - opp-supported-hw = <0x0003>; - }; - - opp-68000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <68000000>; - opp-supported-hw = <0x0008>; - }; - - opp-68000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <68000000>; - opp-supported-hw = <0x0010>; - }; - - opp-68000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <68000000>; - opp-supported-hw = <0x0004>; - }; - - opp-102000000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0003>; - }; - - opp-102000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0008>; - }; - - opp-102000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0010>; - }; - - opp-102000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0004>; - }; - - opp-204000000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x0003>; - opp-suspend; - }; - - opp-204000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x0008>; - opp-suspend; - }; - - opp-204000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x0010>; - opp-suspend; - }; - - opp-204000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x0004>; - opp-suspend; - }; - - opp-264000000-800 { - opp-microvolt = <800000 800000 1150000>; - opp-hz = /bits/ 64 <264000000>; - opp-supported-hw = <0x0003>; - }; - - opp-264000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <264000000>; - opp-supported-hw = <0x0008>; - }; - - opp-264000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <264000000>; - opp-supported-hw = <0x0010>; - }; - - opp-264000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <264000000>; - opp-supported-hw = <0x0004>; - }; - - opp-300000000-850 { - opp-microvolt = <850000 850000 1150000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0003>; - }; - - opp-300000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0008>; - }; - - opp-300000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0010>; - }; - - opp-300000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0004>; - }; - - opp-348000000-850 { - opp-microvolt = <850000 850000 1150000>; - opp-hz = /bits/ 64 <348000000>; - opp-supported-hw = <0x0003>; - }; - - opp-348000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <348000000>; - opp-supported-hw = <0x0008>; - }; - - opp-348000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <348000000>; - opp-supported-hw = <0x0010>; - }; - - opp-348000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <348000000>; - opp-supported-hw = <0x0004>; - }; - - opp-396000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <396000000>; - opp-supported-hw = <0x0008>; - }; - - opp-396000000-1000 { - opp-microvolt = <1000000 1000000 1150000>; - opp-hz = /bits/ 64 <396000000>; - opp-supported-hw = <0x0003>; - }; - - opp-396000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <396000000>; - opp-supported-hw = <0x0010>; - }; - - opp-396000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <396000000>; - opp-supported-hw = <0x0004>; - }; - - opp-528000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <528000000>; - opp-supported-hw = <0x0008>; - }; - - opp-528000000-1000 { - opp-microvolt = <1000000 1000000 1150000>; - opp-hz = /bits/ 64 <528000000>; - opp-supported-hw = <0x0003>; - }; - - opp-528000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <528000000>; - opp-supported-hw = <0x0010>; - }; - - opp-528000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <528000000>; - opp-supported-hw = <0x0004>; - }; - - opp-600000000-950 { - opp-microvolt = <950000 950000 1150000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0008>; - }; - - opp-600000000-1000 { - opp-microvolt = <1000000 1000000 1150000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0003>; - }; - - opp-600000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0010>; - }; - - opp-600000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0004>; - }; - - opp-792000000-1000 { - opp-microvolt = <1000000 1000000 1150000>; - opp-hz = /bits/ 64 <792000000>; - opp-supported-hw = <0x000B>; - }; - - opp-792000000-1050 { - opp-microvolt = <1050000 1050000 1150000>; - opp-hz = /bits/ 64 <792000000>; - opp-supported-hw = <0x0010>; - }; - - opp-792000000-1110 { - opp-microvolt = <1110000 1110000 1150000>; - opp-hz = /bits/ 64 <792000000>; - opp-supported-hw = <0x0004>; - }; - - opp-924000000-1100 { - opp-microvolt = <1100000 1100000 1150000>; - opp-hz = /bits/ 64 <924000000>; - opp-supported-hw = <0x0013>; - }; - - opp-1200000000-1100 { - opp-microvolt = <1100000 1100000 1150000>; - opp-hz = /bits/ 64 <1200000000>; - opp-supported-hw = <0x0003>; - }; - }; - - emc_bw_dfs_opp_table: opp-table-actmon { - compatible = "operating-points-v2"; - - opp-12750000 { - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <204000>; - }; - - opp-20400000 { - opp-hz = /bits/ 64 <20400000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <326400>; - }; - - opp-40800000 { - opp-hz = /bits/ 64 <40800000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <652800>; - }; - - opp-68000000 { - opp-hz = /bits/ 64 <68000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <1088000>; - }; - - opp-102000000 { - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <1632000>; - }; - - opp-204000000 { - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <3264000>; - opp-suspend; - }; - - opp-264000000 { - opp-hz = /bits/ 64 <264000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <4224000>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <4800000>; - }; - - opp-348000000 { - opp-hz = /bits/ 64 <348000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <5568000>; - }; - - opp-396000000 { - opp-hz = /bits/ 64 <396000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <6336000>; - }; - - opp-528000000 { - opp-hz = /bits/ 64 <528000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <8448000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <9600000>; - }; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-supported-hw = <0x001F>; - opp-peak-kBps = <12672000>; - }; - - opp-924000000 { - opp-hz = /bits/ 64 <924000000>; - opp-supported-hw = <0x0013>; - opp-peak-kBps = <14784000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-supported-hw = <0x0003>; - opp-peak-kBps = <19200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts deleted file mode 100644 index 7e739879c00c..000000000000 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ /dev/null @@ -1,1256 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra124.dtsi" - -/ { - model = "NVIDIA Tegra124 Venice2"; - compatible = "nvidia,venice2", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; - vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - - aux-bus { - panel: panel { - compatible = "lg,lp129qe"; - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - }; - }; - }; - }; - - gpu@57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "boot"; - pinctrl-0 = <&pinmux_boot>; - - pinmux_boot: pinmux { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5", - "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - pj7 { - nvidia,pins = "pj7", - "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0", - "pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <32>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <20>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <1>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - als_irq_l { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_bl_en { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_irq_l { - nvidia,pins = "pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ac_ok { - nvidia,pins = "pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sensor_irq_l { - nvidia,pins = "pi6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_rst_l { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hp_det_l { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio>; - interrupts = ; - linux,gpio-keymap = <0 0 0 BTN_LEFT>; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <4000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - usb-role-switch; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_run_cam>; - }; - - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - mmc@700b0400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - vdd_mux: regulator-mux { - compatible = "regulator-fixed"; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator-5v0sys { - compatible = "regulator-fixed"; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator-3v3sys { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator-3v3run { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator-led { - compatible = "regulator-fixed"; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator-ts { - compatible = "regulator-fixed"; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator-lp0 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator-hdmipll { - compatible = "regulator-fixed"; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator-hdmicon { - compatible = "regulator-fixed"; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-venice2", - "nvidia,tegra-audio-max98090"; - nvidia,model = "NVIDIA Tegra Venice2"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi deleted file mode 100644 index b3fbecf5c818..000000000000 --- a/arch/arm/boot/dts/tegra124.dtsi +++ /dev/null @@ -1,1366 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tegra124-peripherals-opp.dtsi" - -/ { - compatible = "nvidia,tegra124"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pcie@1003000 { - compatible = "nvidia,tegra124-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ - <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ - <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ - <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ - <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ - <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ - <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra124-host1x"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - interrupt-names = "syncpt", "host1x"; - clocks = <&tegra_car TEGRA124_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; - reset-names = "host1x", "mc"; - iommus = <&mc TEGRA_SWGROUP_HC>; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - - dc@54200000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>; - clock-names = "dc"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, - <&mc TEGRA124_MC_DISPLAY0B &emc>, - <&mc TEGRA124_MC_DISPLAY0C &emc>, - <&mc TEGRA124_MC_DISPLAYHC &emc>, - <&mc TEGRA124_MC_DISPLAYD &emc>, - <&mc TEGRA124_MC_DISPLAYT &emc>; - interconnect-names = "wina", - "winb", - "winc", - "cursor", - "wind", - "wint"; - }; - - dc@54240000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>; - clock-names = "dc"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, - <&mc TEGRA124_MC_DISPLAY0BB &emc>, - <&mc TEGRA124_MC_DISPLAY0CB &emc>, - <&mc TEGRA124_MC_DISPLAYHCB &emc>; - interconnect-names = "wina", - "winb", - "winc", - "cursor"; - }; - - hdmi: hdmi@54280000 { - compatible = "nvidia,tegra124-hdmi"; - reg = <0x0 0x54280000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDMI>, - <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - vic@54340000 { - compatible = "nvidia,tegra124-vic"; - reg = <0x0 0x54340000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_VIC03>; - clock-names = "vic"; - resets = <&tegra_car 178>; - reset-names = "vic"; - - iommus = <&mc TEGRA_SWGROUP_VIC>; - }; - - sor@54540000 { - compatible = "nvidia,tegra124-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SOR0>, - <&tegra_car TEGRA124_CLK_SOR0_OUT>, - <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA124_CLK_PLL_DP>, - <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DPAUX>, - <&tegra_car TEGRA124_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - status = "disabled"; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x1000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gpu@57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - - iommus = <&mc TEGRA_SWGROUP_GPU>; - - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x0 0x60004000 0x0 0x100>, - <0x0 0x60004100 0x0 0x100>, - <0x0 0x60004200 0x0 0x100>, - <0x0 0x60004300 0x0 0x100>, - <0x0 0x60004400 0x0 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra124-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - actmon: actmon@6000c800 { - compatible = "nvidia,tegra124-actmon"; - reg = <0x0 0x6000c800 0x0 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_ACTMON>, - <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car 119>; - reset-names = "actmon"; - operating-points-v2 = <&emc_bw_dfs_opp_table>; - interconnects = <&mc TEGRA124_MC_MPCORER &emc>; - interconnect-names = "cpu-read"; - #cooling-cells = <2>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-ranges = <&pinmux 0 0 251>; - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra124-pinmux"; - reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>, /* Mux registers */ - <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA124_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra124-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra124-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000dc00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000de00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_RTC>; - }; - - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra124-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra124-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - hdmi-phandle = <&hdmi>; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - #reset-cells = <1>; - #interconnect-cells = <1>; - }; - - emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra124-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "emc"; - - nvidia,memory-controller = <&mc>; - operating-points-v2 = <&emc_icc_dvfs_opp_table>; - - #interconnect-cells = <0>; - }; - - sata@70020000 { - compatible = "nvidia,tegra124-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>; /* SATA */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>; - clock-names = "sata", "sata-oob"; - resets = <&tegra_car 124>, - <&tegra_car 129>, - <&tegra_car 123>; - reset-names = "sata", "sata-cold", "sata-oob"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDA>, - <&tegra_car TEGRA124_CLK_HDA2HDMI>, - <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - usb@70090000 { - compatible = "nvidia,tegra124-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, - <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA124_CLK_PLL_U_480M>, - <&tegra_car TEGRA124_CLK_CLK_M>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", - "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", - "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, - <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - ulpi-0 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - - mmc@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@700b0200 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@700b0400 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@700b0600 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ - <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = , - ; - interrupt-names = "thermal", "edp"; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - nvidia,gpu-throt-level = ; - - #cooling-cells = <2>; - }; - }; - }; - - dfll: clock@70110000 { - compatible = "nvidia,tegra124-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, - <&tegra_car TEGRA124_CLK_DFLL_REF>, - <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - nvidia,sample-rate = <12500>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,cf = <10>; - nvidia,ci = <0>; - nvidia,cg = <2>; - status = "disabled"; - }; - - ahub@70300000 { - compatible = "nvidia,tegra124-ahub"; - reg = <0x0 0x70300000 0x0 0x200>, - <0x0 0x70300800 0x0 0x800>, - <0x0 0x70300200 0x0 0x600>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, - <&tegra_car TEGRA124_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 185>, /* amx1 */ - <&tegra_car 154>, /* adx */ - <&tegra_car 180>, /* adx1 */ - <&tegra_car 186>, /* afc0 */ - <&tegra_car 187>, /* afc1 */ - <&tegra_car 188>, /* afc2 */ - <&tegra_car 189>, /* afc3 */ - <&tegra_car 190>, /* afc4 */ - <&tegra_car 191>; /* afc5 */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "amx1", "adx", "adx1", - "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - tegra_i2s0: i2s@70301000 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA124_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70301100 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA124_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70301200 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA124_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70301300 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA124_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70301400 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA124_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - nvidia,pmc = <&tegra_pmc 0>; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,pmc = <&tegra_pmc 1>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; - reg = <0x0 0x7d008000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d008000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,pmc = <&tegra_pmc 2>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, - <&tegra_car TEGRA124_CLK_PLL_X>, - <&tegra_car TEGRA124_CLK_PLL_P>, - <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; - /* FIXME: what's the actual transition time? */ - clock-latency = <300000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>, - <&{/cpus/cpu@2}>, - <&{/cpus/cpu@3}>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - cpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - mem-throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - pllx-throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts deleted file mode 100644 index 08b42952f4de..000000000000 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ /dev/null @@ -1,1525 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include - -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" -#include "tegra20-cpu-opp-microvolt.dtsi" - -/ { - model = "Acer Iconia Tab A500"; - compatible = "acer,picasso", "nvidia,tegra20"; - - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc3; /* MicroSD */ - mmc2 = &sdmmc1; /* WiFi */ - - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - - serial0 = &uartd; /* Docking station */ - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@2ffe0000 { - compatible = "ramoops"; - reg = <0x2ffe0000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - linux,cma@30000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x30000000 0x10000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - port@0 { - lcd_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <18>; - }; - }; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - hdmi-supply = <&vdd_5v0_sys>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lsc0", - "lsc1", "lsck", "lsda", "lspi", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "csus", "dap1", - "dap4", "dte", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "gpv", "i2cp", - "irrx", "irtx", "pta", "rm", - "sdc", "sdd", "slxc", "slxd", "slxk", - "spdi", "spdo", "uac", "uad", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "dap2", "dap3", - "gmd", "owc", "spia", "spib", "spic", - "spid", "spie"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spig", - "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", - "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", - "uab", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0"; - nvidia,pull = ; - }; - drive_ddc { - nvidia,pins = "drive_ddc", - "drive_vi1", - "drive_sdio1"; - nvidia,pull-up-strength = <31>; - nvidia,pull-down-strength = <31>; - nvidia,schmitt = ; - nvidia,high-speed-mode = ; - nvidia,low-power-mode = ; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_dbg { - nvidia,pins = "drive_dbg", - "drive_vi2", - "drive_at1", - "drive_ao1"; - nvidia,pull-up-strength = <31>; - nvidia,pull-down-strength = <31>; - nvidia,schmitt = ; - nvidia,high-speed-mode = ; - nvidia,low-power-mode = ; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux-i2cmux-ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_idle: pinmux-i2cmux-idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux-i2cmux-pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - }; - - tegra_spdif: spdif@70002400 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - tegra_i2s1: i2s@70002800 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra20-hsuart"; - /delete-property/ reg-shift; - /* GPS BCM4751 */ - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra20-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - /* Azurewave AW-NH665 BCM4329B1 */ - bluetooth { - compatible = "brcm,bcm4329-bt"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - /* PLLP 216MHz / 16 / 4 */ - max-speed = <3375000>; - - clocks = <&rtc_32k_wifi>; - clock-names = "txco"; - - vbat-supply = <&vdd_3v3_sys>; - vddio-supply = <&vdd_1v8_sys>; - - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - uartd: serial@70006300 { - /* Docking station */ - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - status = "okay"; - - wm8903: audio-codec@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - - gpio-cfg = < - 0x0000 /* MIC_LR_OUT# GPIO, output, low */ - 0x0000 /* FM2018-enable GPIO, output, low */ - 0x0000 /* Speaker-enable GPIO, output, low */ - 0x0200 /* Interrupt, output */ - 0x01a0 /* BCLK, input, active high */ - >; - - AVDD-supply = <&vdd_1v8_sys>; - CPVDD-supply = <&vdd_1v8_sys>; - DBVDD-supply = <&vdd_1v8_sys>; - DCVDD-supply = <&vdd_1v8_sys>; - }; - - touchscreen@4c { - compatible = "atmel,maxtouch"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - - vdda-supply = <&vdd_3v3_sys>; - vdd-supply = <&vdd_3v3_sys>; - - atmel,wakeup-method = ; - }; - - gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - vlogic-supply = <&vdd_1v8_sys>; - - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - accelerometer@f { - compatible = "kionix,kxtf9"; - reg = <0x0f>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_1v8_sys>; - vddio-supply = <&vdd_1v8_sys>; - - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; - }; - }; - }; - }; - - i2c@7000c400 { - clock-frequency = <10000>; - status = "okay"; - }; - - i2c@7000d000 { - clock-frequency = <100000>; - status = "okay"; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - vid-supply = <&vdd_1v8_sys>; - - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; - }; - - pmic: pmic@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_sys>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&rtc_vdd &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-core-regulator; - }; - - vdd_cpu: sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1125000>; - regulator-coupled-with = <&vdd_core &rtc_vdd>; - regulator-coupled-max-spread = <550000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-cpu-regulator; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - rtc_vdd: ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&vdd_core &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-rtc-regulator; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vcore_emmc: ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - avdd_vdac_reg: ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - nct1008: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&vdd_3v3_sys>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@0 { - nvidia,ram-code = <0>; /* elpida-8gb */ - reg = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dd510 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e1510 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - emc-tables@1 { - nvidia,ram-code = <1>; /* elpida-4gb */ - reg = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007e4010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - emc-tables@2 { - nvidia,ram-code = <2>; /* hynix-8gb */ - reg = <2>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dd010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e2010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - emc-tables@3 { - nvidia,ram-code = <3>; /* hynix-4gb */ - reg = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00078000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007e4010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - }; - - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@c5000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; - - sdmmc1: mmc@c8000000 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; - assigned-clock-rates = <50000000>; - - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_1v8_sys>; - - /* Azurewave AW-NH611 BCM4329 */ - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - sdmmc3: mmc@c8000400 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; - }; - - sdmmc4: mmc@c8000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_3v3_sys>; - non-removable; - }; - - mains: ac-adapter-detect { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_3v3_sys>; - pwms = <&pwm 2 41667>; - - brightness-levels = <7 255>; - num-interpolated-steps = <248>; - default-brightness-level = <20>; - }; - - bat1010: battery-2s1p { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <3260000>; - energy-full-design-microwatt-hours = <24000000>; - operating-range-celsius = <0 40>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k-in { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "tps658621-out32k"; - }; - - /* - * This standalone onboard fixed-clock always-ON 32KHz - * oscillator is used as a reference clock-source by the - * Azurewave WiFi/BT module. - */ - rtc_32k_wifi: clock-32k-wifi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "kk3270032"; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - display-panel { - compatible = "auo,b101ew05", "panel-lvds"; - - ddc-i2c-bus = <&panel_ddc>; - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - - width-mm = <218>; - height-mm = <135>; - - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <71200000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <8>; - hback-porch = <18>; - hsync-len = <184>; - vsync-len = <3>; - vfront-porch = <4>; - vback-porch = <8>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-rotation-lock { - label = "Rotate-lock"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - debounce-interval = <10>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - haptic-feedback { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - vcc-supply = <&vdd_3v3_sys>; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - panel_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@58 { - compatible = "acer,a500-iconia-ec", "ene,kb930"; - reg = <0x58>; - - system-power-controller; - - monitored-battery = <&bat1010>; - power-supplies = <&mains>; - }; - }; - }; - - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - opp-table-emc { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_vs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_1v8_sys: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_vs"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <300000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-picasso", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Acer Iconia Tab A500 WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "LINEOUTL", - "Int Spk", "LINEOUTR", - "Mic Jack", "MICBIAS", - "IN2L", "Mic Jack", - "IN2R", "Mic Jack", - "IN1L", "Int Mic", - "IN1R", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; - nvidia,headset; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - /* - * NCT1008 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents A500 from - * getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 0>; - - trips { - trip0: skin-alert { - /* start throttling at 60C */ - temperature = <60000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 70C */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&rtc_32k_wifi>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts deleted file mode 100644 index c2a9c3fb5b33..000000000000 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ /dev/null @@ -1,1291 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include - -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" -#include "tegra20-cpu-opp-microvolt.dtsi" - -/ { - model = "ASUS EeePad Transformer TF101"; - compatible = "asus,tf101", "nvidia,tegra20"; - chassis-type = "convertible"; - - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc3; /* MicroSD */ - mmc2 = &sdmmc1; /* WiFi */ - - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - - serial0 = &uartd; - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@2ffe0000 { - compatible = "ramoops"; - reg = <0x2ffe0000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - linux,cma@30000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x30000000 0x10000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - port@0 { - lcd_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <18>; - }; - }; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - hdmi-supply = <&vdd_hdmi_en>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - gpio@6000d000 { - charging-enable-hog { - gpio-hog; - gpios = ; - output-low; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - - lm1 { - nvidia,pins = "lm1"; - nvidia,function = "rsvd3"; - }; - - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - - gpv { - nvidia,pins = "gpv", "slxa"; - nvidia,function = "pcie"; - }; - - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", "lsda", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; - nvidia,function = "sdio3"; - }; - - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap4", - "dte", "ddc", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "gpv", "i2cp", - "irrx", "irtx", "pta", "rm", "sdc", - "sdd", "slxc", "slxd", "slxk", "spdi", - "spdo", "uac", "uad", - "uda", "csus"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_ate { - nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", - "owc", "spia", "spib", "spic", - "spid", "spie", "spig", "slxa"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - - conf_crtp { - nvidia,pins = "crtp", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_spif { - nvidia,pins = "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = ; - }; - - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", "uab", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_csus { - nvidia,pins = "drive_csus"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux-i2cmux-ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_idle: pinmux-i2cmux-idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux-i2cmux-pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - }; - - spdif@70002400 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - i2s@70002800 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - serial@70006040 { - compatible = "nvidia,tegra20-hsuart"; - /delete-property/ reg-shift; - /* GPS BCM4751 */ - }; - - serial@70006200 { - compatible = "nvidia,tegra20-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - /* Azurewave AW-NH615 BCM4329B1 */ - bluetooth { - compatible = "brcm,bcm4329-bt"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - /* PLLP 216MHz / 16 / 4 */ - max-speed = <3375000>; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; - - vbat-supply = <&vdd_3v3_sys>; - vddio-supply = <&vdd_1v8_sys>; - - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* Aichi AMI306 digital compass */ - magnetometer@e { - compatible = "asahi-kasei,ak8974"; - reg = <0xe>; - - avdd-supply = <&vdd_3v3_sys>; - dvdd-supply = <&vdd_1v8_sys>; - - mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - }; - - wm8903: audio-codec@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0x83>; - micdet-delay = <100>; - - gpio-cfg = < - 0x00000600 /* DMIC_LR, output */ - 0x00000680 /* DMIC_DAT, input */ - 0x00000000 /* Speaker-enable GPIO, output, low */ - 0xffffffff /* don't touch */ - 0xffffffff /* don't touch */ - >; - - AVDD-supply = <&vdd_1v8_sys>; - CPVDD-supply = <&vdd_1v8_sys>; - DBVDD-supply = <&vdd_1v8_sys>; - DCVDD-supply = <&vdd_1v8_sys>; - }; - - /* Atmel MXT1386 Touchscreen */ - touchscreen@5b { - compatible = "atmel,maxtouch"; - reg = <0x5b>; - - interrupt-parent = <&gpio>; - interrupts = ; - - reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - - vdda-supply = <&vdd_3v3_sys>; - vdd-supply = <&vdd_3v3_sys>; - - atmel,wakeup-method = ; - }; - - gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - vlogic-supply = <&vdd_1v8_sys>; - - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - accelerometer@f { - compatible = "kionix,kxtf9"; - reg = <0xf>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_1v8_sys>; - vddio-supply = <&vdd_1v8_sys>; - - mount-matrix = "-1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; - }; - }; - }; - }; - - i2c2: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_sys>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&rtc_vdd &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-core-regulator; - }; - - vdd_cpu: sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1125000>; - regulator-coupled-with = <&vdd_core &rtc_vdd>; - regulator-coupled-max-spread = <550000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-cpu-regulator; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - rtc_vdd: ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&vdd_core &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-rtc-regulator; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcore_emmc: ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - nct1008: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&vdd_3v3_sys>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@3 { - reg = <0x3>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dc010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e0 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - lpddr2 { - compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id = <1 0>; - density = <2048>; - io-width = <16>; - }; - }; - }; - - /* Peripheral USB via ASUS connector */ - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@c5000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; - - /* Dock's USB port */ - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - nvidia,xcvr-setup-use-fuses; - vbus-supply = <&vdd_5v0_sys>; - }; - - sdmmc1: mmc@c8000000 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; - assigned-clock-rates = <40000000>; - - max-frequency = <40000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; - - /* Azurewave AW-NH615 BCM4329B1 */ - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - sdmmc3: mmc@c8000400 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; - }; - - sdmmc4: mmc@c8000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_3v3_sys>; - non-removable; - }; - - mains: ac-adapter-detect { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_3v3_sys>; - pwms = <&pwm 2 4000000>; - - brightness-levels = <7 255>; - num-interpolated-steps = <248>; - default-brightness-level = <20>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k-in { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - display-panel { - compatible = "auo,b101ew05", "panel-lvds"; - - /* AUO B101EW05 using custom timings */ - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - power-supply = <&vdd_pnl_reg>; - - width-mm = <218>; - height-mm = <135>; - - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <71200000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <8>; - hback-porch = <18>; - hsync-len = <184>; - vsync-len = <3>; - vfront-porch = <4>; - vback-porch = <8>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - switch-dock-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c2>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&mains>; - }; - }; - }; - - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - opp-table-emc { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_vs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pcie_vdd"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - vdd_pnl_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_1v8_sys: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_vs"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hdmi_en: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_hdmi_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "asus,tegra-audio-wm8903-tf101", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Asus EeePad Transformer WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "IN2L", "Mic Jack", - "DMICDAT", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; - nvidia,coupled-mic-hp-det; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - /* - * NCT1008 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents TF101 from - * getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 0>; - - trips { - trip0: skin-alert { - /* start throttling at 60C */ - temperature = <60000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 70C */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - power-off-delay-us = <200>; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts deleted file mode 100644 index 612f4e54cb20..000000000000 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/dts-v1/; - -#include -#include "tegra20-colibri.dtsi" - -/ { - model = "Toradex Colibri T20 on Colibri Evaluation Board"; - compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20", - "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@34"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartd; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - bl-on { - nvidia,tristate = ; - }; - - ddc { - nvidia,tristate = ; - }; - - hotplug-detect { - nvidia,tristate = ; - }; - - i2c { - nvidia,tristate = ; - }; - - lcd { - nvidia,tristate = ; - }; - - lm1 { - nvidia,tristate = ; - }; - - mmc { - nvidia,tristate = ; - }; - - mmccd { - nvidia,tristate = ; - }; - - sdc { - nvidia,tristate = ; - }; - - sdb_sdd { - nvidia,tristate = ; - }; - - ssp { - nvidia,tristate = ; - }; - - uart-a { - nvidia,tristate = ; - }; - - uart-b { - nvidia,tristate = ; - }; - - uart-c { - nvidia,tristate = ; - }; - - usbh-pen { - nvidia,tristate = ; - }; - }; - }; - - /* Colibri UART-A */ - serial@70006000 { - status = "okay"; - }; - - /* Colibri UART-C */ - serial@70006040 { - status = "okay"; - }; - - /* Colibri UART-B */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* CAM_I2C (I2C3): unused */ - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c@7000c400 { - status = "okay"; - }; - - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = ; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <®_usbc_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* SD/MMC */ - mmc@c8000600 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ - no-1-8-v; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* PWM */ - }; - - clk16m: clock-osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbc_vbus: regulator-usbc-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB5"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - }; - - /* USBH_PEN resp. USB_P_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts deleted file mode 100644 index 25a9f5dfe62d..000000000000 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20-colibri.dtsi" - -/ { - model = "Toradex Colibri T20 on Iris"; - compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20", - "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@34"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartd; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - bl-on { - nvidia,tristate = ; - }; - - ddc { - nvidia,tristate = ; - }; - - hotplug-detect { - nvidia,tristate = ; - }; - - i2c { - nvidia,tristate = ; - }; - - lcd { - nvidia,tristate = ; - }; - - lm1 { - nvidia,tristate = ; - }; - - mmc { - nvidia,tristate = ; - }; - - mmccd { - nvidia,tristate = ; - }; - - sdc { - nvidia,tristate = ; - }; - - sdb_sdd { - nvidia,tristate = ; - }; - - ssp { - nvidia,tristate = ; - }; - - uart-a { - nvidia,tristate = ; - }; - - uart-b { - nvidia,tristate = ; - }; - - uart-c { - nvidia,tristate = ; - }; - - usbh-pen { - nvidia,tristate = ; - }; - }; - }; - - /* Colibri UART-A */ - serial@70006000 { - status = "okay"; - }; - - /* Colibri UART-C */ - serial@70006040 { - status = "okay"; - }; - - /* Colibri UART-B */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* CAM_I2C (I2C3): unused */ - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c@7000c400 { - status = "okay"; - }; - - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <®_usbc_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* SD/MMC */ - mmc@c8000600 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ - no-1-8-v; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbc_vbus: regulator-usbc-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - }; - - /* USBH_PEN resp. USB_P_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi deleted file mode 100644 index 0e03910abbe6..000000000000 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ /dev/null @@ -1,776 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra20.dtsi" - -/* - * Toradex Colibri T20 Module Device Tree - * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; - * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; - * Colibri T20 512MB IT V1.2A - */ -/ { - memory@0 { - /* - * Set memory to 256 MB to be safe as this could be used on - * 256 or 512 MB module. It is expected from bootloader - * to fix this up for 512 MB version. - */ - reg = <0x00000000 0x10000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - gpio@6000d000 { - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; - - /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "Tri-state nPWE"; - }; - - /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr-hog { - gpio-hog; - gpios = ; - output-low; - line-name = "Not tri-state RDnWR"; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio AC97 to WM9712 (On-module) */ - audio-refclk { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ - * (All on-module), SODIMM Pin 45 Wakeup - */ - gpio-uac { - nvidia,pins = "uac"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Buffer Enables for nPWE and RDnWR (On-module, - * see GPIO hogging further down below) - */ - gpio-pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, - * SYS_CLK_REQ (All on-module) - */ - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - nvidia,tristate = ; - }; - - /* - * Colibri Address/Data Bus (GMI) - * Note: spid and spie optionally used for SPI1 - */ - gmi { - nvidia,pins = "atc", "atd", "ate", "dap1", - "dap2", "dap4", "gmd", "gpu", - "irrx", "irtx", "spia", "spib", - "spic", "spid", "spie", "uca", - "ucb"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Further pins may be used as GPIOs */ - gmi-gpio1 { - nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - gmi-gpio2 { - nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; - nvidia,function = "rsvd4"; - nvidia,tristate = ; - }; - - /* Colibri BL_ON */ - bl-on { - nvidia,pins = "dta"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Backlight PWM, PWM */ - sdc { - nvidia,pins = "sdc"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - - /* Colibri DDC */ - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri EXT_IO* - * Note: dtf optionally used for I2C3 - */ - ext-io { - nvidia,pins = "dtf", "spdi"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri Ethernet (On-module) - * ULPI EHCI instance 1 USB2_DP/N -> AX88772B - */ - ulpi { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi-refclk { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri HOTPLUG_DETECT (HDMI) */ - hotplug-detect { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - - /* Colibri I2C */ - i2c { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE - * today's display need DE, disable LCD_M1 - */ - lm1 { - nvidia,pins = "lm1"; - nvidia,function = "rsvd3"; - nvidia,tristate = ; - }; - - /* Colibri LCD (L_* resp. LDD<*>) */ - lcd { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", - "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", - "ld12", "ld13", "ld14", "ld15", - "ld16", "ld17", "lhs", "lsc0", - "lspi", "lvs"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - /* Colibri LCD (Optional 24 BPP Support) */ - lcd-24 { - nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", - "lpp", "lvp1"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - - /* Colibri MMC */ - mmc { - nvidia,pins = "atb", "gma"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri MMCCD */ - mmccd { - nvidia,pins = "gmb"; - nvidia,function = "gmi_int"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri MMC (Optional 8-bit) */ - mmc-8bit { - nvidia,pins = "gme"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri Parallel Camera (Optional) - * pins multiplexed with others and therefore disabled - * Note: dta used for BL_ON by default - */ - cif-mclk { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - nvidia,pull = ; - nvidia,tristate = ; - }; - cif { - nvidia,pins = "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri PWM, PWM */ - sdb_sdd { - nvidia,pins = "sdb", "sdd"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - - /* Colibri SSP */ - ssp { - nvidia,pins = "slxa", "slxc", "slxd", "slxk"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-A */ - uart-a { - nvidia,pins = "sdio1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart-a-dsr { - nvidia,pins = "lpw1"; - nvidia,function = "rsvd3"; - nvidia,tristate = ; - }; - uart-a-dcd { - nvidia,pins = "lpw2"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - - /* Colibri UART-B */ - uart-b { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-C */ - uart-c { - nvidia,pins = "uad"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USB_CDET */ - usb-cdet { - nvidia,pins = "spdo"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBH_OC */ - usbh-oc { - nvidia,pins = "spih"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBH_PEN */ - usbh-pen { - nvidia,pins = "spig"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri VGA not supported */ - vga { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* I2C3 (Optional) */ - i2c3 { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* JTAG_RTCK */ - jtag-rtck { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME - * (All On-module) - */ - gpio-gpv { - nvidia,pins = "gpv"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN - * (All On-module); Colibri CAN_INT - */ - gpio-dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* NAND (On-module) */ - nand { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Onewire (Optional) */ - owr { - nvidia,pins = "owc"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Power I2C (On-module) */ - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* RESET_OUT */ - reset-out { - nvidia,pins = "ata"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * SPI1 (Optional) - * Note: spid and spie used for Colibri Address/Data - * Bus (GMI) - */ - spi1 { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * THERMD_ALERT# (On-module), unlatched I2C address pin - * of LM95245 temperature sensor therefore requires - * disabling for now - */ - lvp0 { - nvidia,pins = "lvp0"; - nvidia,function = "rsvd3"; - nvidia,tristate = ; - }; - }; - }; - - tegra_ac97: ac97@70002000 { - status = "okay"; - nvidia,codec-reset-gpio = - <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = - <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; - }; - - serial@70006040 { - compatible = "nvidia,tegra20-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006300 { - compatible = "nvidia,tegra20-hsuart"; - /delete-property/ reg-shift; - }; - - nand-controller@70008000 { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-on-flash-bbt; - nand-ecc-algo = "bch"; - nand-is-boot-medium; - nand-ecc-maximize; - wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - clock-frequency = <400000>; - }; - - /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ - hdmi_ddc: i2c@7000c400 { - clock-frequency = <10000>; - }; - - /* GEN2_I2C: unused */ - - /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ - - /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - pmic@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - ti,system-power-controller; - #gpio-cells = <2>; - gpio-controller; - sys-supply = <®_module_3v3>; - vin-sm0-supply = <®_3v3_vsys>; - vin-sm1-supply = <®_3v3_vsys>; - vin-sm2-supply = <®_3v3_vsys>; - vinldo01-supply = <®_1v8_vdd_ddr2>; - vinldo23-supply = <®_module_3v3>; - vinldo4-supply = <®_module_3v3>; - vinldo678-supply = <®_module_3v3>; - vinldo9-supply = <®_module_3v3>; - - regulators { - reg_3v3_vsys: sys { - regulator-name = "VSYS_3.3V"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "VDD_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "VDD_CPU_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_1v8_vdd_ddr2: sm2 { - regulator-name = "VDD_DDR2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - /* - * +3.3V_ENABLE_N switching via FET: - * AVDD_AUDIO_S and +3.3V - * see also +3.3V fixed supply - */ - ldo1 { - regulator-name = "AVDD_PLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "VDD_RTC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4 { - regulator-name = "VDDIO_SYS_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* Switched via FET from regular +3.3V */ - ldo5 { - regulator-name = "+3.3V_USB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "AVDD_VDAC_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - reg_3v3_avdd_hdmi: ldo7 { - regulator-name = "AVDD_HDMI_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_1v8_avdd_hdmi_pll: ldo8 { - regulator-name = "AVDD_HDMI_PLL_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "VDDIO_RX_DDR_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "VCC_BATT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - /* LM95245 temperature sensor */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - - /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <3>; - nvidia,bus-addr = <0x34>; - nvidia,reg-addr = <0x14>; - nvidia,reg-data = <0x8>; - }; - }; - - memory-controller@7000f400 { - emc-table@83250 { - reg = <83250>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <83250>; - nvidia,emc-registers = <0x00000005 0x00000011 - 0x00000004 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000001 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000025f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000005 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00520006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@133200 { - reg = <133200>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <133200>; - nvidia,emc-registers = <0x00000008 0x00000019 - 0x00000006 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000039f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000007 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00510006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000021 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000a 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x00000009 0x000000c8 - 0x00000003 0x00000009 0x00000004 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x004f0006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000014 0x00000041 - 0x0000000f 0x00000005 0x00000004 0x00000005 - 0x00000003 0x0000000a 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000009ff - 0x00000000 0x00000003 0x00000003 0x00000005 - 0x00000005 0x00000001 0x0000000e 0x000000c8 - 0x00000003 0x00000011 0x00000006 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00380006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ - usb@c5004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet@1 { - compatible = "usbb95,772b"; - reg = <1>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = - <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - vbus-supply = <®_lan_v_bus>; - }; - - clk32k_in: clock-xtal3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - opp-table-emc { - /delete-node/ opp-760000000; - }; - - reg_lan_v_bus: regulator-lan-v-bus { - compatible = "regulator-fixed"; - regulator-name = "LAN_V_BUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Toradex Colibri T20"; - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - nvidia,ac97-controller = <&tegra_ac97>; - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi deleted file mode 100644 index 7330c1b13d93..000000000000 --- a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: opp-table-cpu0 { - opp-216000000-750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp-216000000-800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp-312000000-750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp-312000000-800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp-456000000-750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp-456000000-800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp-456000000-825 { - opp-microvolt = <825000 825000 1125000>; - }; - - opp-608000000-750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp-608000000-800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp-608000000-825 { - opp-microvolt = <825000 825000 1125000>; - }; - - opp-608000000-850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp-608000000-900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp-760000000-775 { - opp-microvolt = <775000 775000 1125000>; - }; - - opp-760000000-800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp-760000000-850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp-760000000-875 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp-760000000-900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp-760000000-975 { - opp-microvolt = <975000 975000 1125000>; - }; - - opp-816000000-800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp-816000000-850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp-816000000-875 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp-816000000-950 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp-816000000-1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp-912000000-850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp-912000000-900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp-912000000-925 { - opp-microvolt = <925000 925000 1125000>; - }; - - opp-912000000-950 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp-912000000-1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp-912000000-1050 { - opp-microvolt = <1050000 1050000 1125000>; - }; - - opp-1000000000-875 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp-1000000000-900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp-1000000000-950 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp-1000000000-975 { - opp-microvolt = <975000 975000 1125000>; - }; - - opp-1000000000-1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp-1000000000-1025 { - opp-microvolt = <1025000 1025000 1125000>; - }; - - opp-1000000000-1100 { - opp-microvolt = <1100000 1100000 1125000>; - }; - - opp-1200000000-1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp-1200000000-1050 { - opp-microvolt = <1050000 1050000 1125000>; - }; - - opp-1200000000-1100 { - opp-microvolt = <1100000 1100000 1125000>; - }; - - opp-1200000000-1125 { - opp-microvolt = <1125000 1125000 1125000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi deleted file mode 100644 index 47c8e78ca958..000000000000 --- a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: opp-table-cpu0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-216000000-750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0003>; - opp-hz = /bits/ 64 <216000000>; - opp-suspend; - }; - - opp-216000000-800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0004>; - opp-hz = /bits/ 64 <216000000>; - opp-suspend; - }; - - opp-312000000-750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0003>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp-312000000-800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0004>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp-456000000-750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0C 0x0003>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp-456000000-800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>, - <0x08 0x0004>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp-456000000-825 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp-608000000-750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0003>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-608000000-800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-608000000-825 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-608000000-850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0006>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-608000000-900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-760000000-775 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0003>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0006>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-875 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>, - <0x01 0x0004>, <0x02 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-975 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-816000000-800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0007>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-816000000-850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-816000000-875 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0005>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-816000000-950 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0006>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-816000000-1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-912000000-850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0007>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp-912000000-900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp-912000000-925 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp-912000000-950 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>, - <0x04 0x0004>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp-912000000-1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp-912000000-1050 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp-1000000000-875 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0007>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-950 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-975 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-1025 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-1100 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1200000000-1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1050 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1100 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1125 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts deleted file mode 100644 index 11f21aeba8e9..000000000000 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Harmony evaluation board"; - compatible = "nvidia,harmony", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", - "gpv", "i2cp", "pta", "rm", "slxa", - "slxk", "spia", "spib", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "sdd", "spic", - "spie", "spih", "uaa", "uab", "uad", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - pci_clk_reg: ldo0 { - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <2>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - pcie@80003000 { - status = "okay"; - - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - mmc@c8000200 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - mmc@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "auo,b101aw03"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator-1v5 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator-1v2 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pci_vdd_reg: regulator-1v05 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_pnl_reg: regulator-pn1 { - compatible = "regulator-fixed"; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_5v0_hdmi: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-harmony", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Harmony"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_LOW>; - nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) - GPIO_ACTIVE_HIGH>; - nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts deleted file mode 100644 index 8c657182fff3..000000000000 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Medcom-Wide board"; - compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; - - aliases { - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - /* close enough */ - power-supply = <&vdd_3v3_reg>; - }; - - panel: panel { - compatible = "innolux,n156bge-l21"; - - power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - sound { - compatible = "ad,tegra-audio-wm8903-medcom-wide", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design Medcom-Wide"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - vcc_24v_reg: regulator-24v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts deleted file mode 100644 index e995f428dc2e..000000000000 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ /dev/null @@ -1,721 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" -#include "tegra20-cpu-opp-microvolt.dtsi" - -/ { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; - - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc1; /* MicroSD */ - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap2", "gmb", "gmc", "gmd", "spia", - "spib", "spic", "spid", "spie"; - nvidia,function = "gmi"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "pllc_out1"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gpu { - nvidia,pins = "gpu", "sdb", "sdd"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdc { - nvidia,pins = "sdc"; - nvidia,function = "twc"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spi4"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spif { - nvidia,pins = "spif", "uac"; - nvidia,function = "rsvd4"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "spdif"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dap2", "dtf", - "gma", "gmb", "gmc", "gmd", "gme", - "gpu", "gpu7", "gpv", "i2cp", "pta", - "rm", "sdio1", "slxk", "spdo", "uac", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap3", "dap4", "dtb", - "dtc", "dte", "slxa", "slxc", "slxd", - "spdi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", "spid", - "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "irrx", "irtx", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "spic", "spig", "uaa", "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", - "spie", "spih", "uad", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhs", "lsc0", "lspi", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_lcsn { - nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", - "lm0", "lm1", "lpp", "lpw0", "lpw1", - "lpw2", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "lvp1", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - }; - - spdif@70002400 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - i2s@70002800 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006200 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - lvds_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - alc5632: alc5632@1e { - compatible = "realtek,alc5632"; - reg = <0x1e>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - nvec@7000c500 { - compatible = "nvidia,nvec"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <80000>; - request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - slave-addr = <138>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&p5valw_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - core_vdd_reg: sm0 { - regulator-name = "+1.2vs_sm0,vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - - nvidia,tegra-core-regulator; - }; - - cpu_vdd_reg: sm1 { - regulator-name = "+1.0vs_sm1,vdd_cpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1100000>; - regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; - regulator-coupled-max-spread = <550000 550000>; - regulator-always-on; - - nvidia,tegra-cpu-regulator; - }; - - sm2_reg: sm2 { - regulator-name = "+3.7vs_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "+1.1vs_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - rtc_vdd_reg: ldo2 { - regulator-name = "+1.2vs_ldo2,vdd_rtc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - - nvidia,tegra-rtc-regulator; - }; - - ldo3 { - regulator-name = "+3.3vs_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "+2.85vs_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - /* - * Research indicates this should be - * 1.8v; other boards that use this - * rail for the same purpose need it - * set to 1.8v. The schematic signal - * name is incorrect; perhaps copied - * from an incorrect NVIDIA reference. - */ - regulator-name = "+2.85vs_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "+3.3vs_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "+3.3vs_rtc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - adt7461: temperature-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,sys-clock-req-active-high; - core-supply = <&core_vdd_reg>; - }; - - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@0 { - nvidia,ram-code = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000016 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000a 0x000000c8 - 0x00000003 0x00000006 0x00000004 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe03b0323 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000018 0x00000033 - 0x00000012 0x00000004 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000bff - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xf0440303 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - }; - - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdmmc1: mmc@c8000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdmmc4: mmc@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; - default-brightness-level = <10>; - - /* close enough */ - power-supply = <&vdd_pnl_reg>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "Wakeup"; - gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-0 { - label = "wifi-led"; - gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "rfkill0"; - }; - }; - - opp-table-emc { - /delete-node/ opp-760000000; - }; - - panel: panel { - compatible = "samsung,ltn101nt05"; - - ddc-i2c-bus = <&lvds_ddc>; - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - p5valw_reg: regulator-5v0alw { - compatible = "regulator-fixed"; - regulator-name = "+5valw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_pnl_reg: regulator-3v0 { - compatible = "regulator-fixed"; - regulator-name = "+3VS,vdd_pnl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "nvidia,tegra-audio-alc5632-paz00", - "nvidia,tegra-audio-alc5632"; - - nvidia,model = "Compal PAZ00"; - - nvidia,audio-routing = - "Int Spk", "SPKOUT", - "Int Spk", "SPKOUTN", - "Headset Mic", "MICBIAS1", - "MIC1", "Headset Mic", - "Headset Stereophone", "HPR", - "Headset Stereophone", "HPL", - "DMICDAT", "Digital Mic"; - - nvidia,audio-codec = <&alc5632>; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <500>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - thermal-sensors = <&adt7461 1>; - - trips { - trip0: cpu-alert0 { - /* start throttling at 80C */ - temperature = <80000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: cpu-crit { - /* shut down at 85C */ - temperature = <85000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi deleted file mode 100644 index 1b808233a933..000000000000 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ /dev/null @@ -1,1022 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - core_opp_table: opp-table-core { - compatible = "operating-points-v2"; - opp-shared; - - core_opp_950: opp-950000 { - opp-microvolt = <950000 950000 1300000>; - opp-level = <950000>; - }; - - core_opp_1000: opp-1000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-level = <1000000>; - }; - - core_opp_1100: opp-1100000 { - opp-microvolt = <1100000 1100000 1300000>; - opp-level = <1100000>; - }; - - core_opp_1200: opp-1200000 { - opp-microvolt = <1200000 1200000 1300000>; - opp-level = <1200000>; - }; - - core_opp_1225: opp-1225000 { - opp-microvolt = <1225000 1225000 1300000>; - opp-level = <1225000>; - }; - - core_opp_1275: opp-1275000 { - opp-microvolt = <1275000 1275000 1300000>; - opp-level = <1275000>; - }; - - core_opp_1300: opp-1300000 { - opp-microvolt = <1300000 1300000 1300000>; - opp-level = <1300000>; - }; - }; - - emc_icc_dvfs_opp_table: opp-table-emc { - compatible = "operating-points-v2"; - - opp-36000000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <36000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-47500000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <47500000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-50000000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <50000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-54000000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <54000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-57000000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <57000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-100000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-108000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <108000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-126666000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <126666000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-150000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <150000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-190000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-216000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <216000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - opp-suspend; - }; - - opp-300000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-333000000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <333000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-380000000 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - - opp-600000000 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - - opp-666000000 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <666000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - - opp-760000000 { - opp-microvolt = <1300000 1300000 1300000>; - opp-hz = /bits/ 64 <760000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1300>; - }; - }; - - host1x_dvfs_opp_table: opp-table-host1x { - compatible = "operating-points-v2"; - - opp-104500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <104500000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-133000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-166000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <166000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; - - mpe_dvfs_opp_table: opp-table-mpe { - compatible = "operating-points-v2"; - - opp-104500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <104500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_950>; - }; - - opp-142500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <142500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_950>; - }; - - opp-152000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <152000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-190000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1000>; - }; - - opp-190000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_950>; - }; - - opp-228000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <228000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1100>; - }; - - opp-228000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <228000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_950>; - }; - - opp-237500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <237500000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-266000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <266000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1000>; - }; - - opp-275500000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <275500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1100>; - }; - - opp-300000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1200>; - }; - - opp-300000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x000C>; - required-opps = <&core_opp_1100>; - }; - }; - - vi_dvfs_opp_table: opp-table-vi { - compatible = "operating-points-v2"; - - opp-85000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <85000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-100000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-150000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <150000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; - - epp_dvfs_opp_table: opp-table-epp { - compatible = "operating-points-v2"; - - opp-133000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-171000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <171000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-247000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - - opp-300000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - gr2d_dvfs_opp_table: opp-table-gr2d { - compatible = "operating-points-v2"; - - opp-133000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-171000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <171000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-247000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - - opp-300000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - gr3d_dvfs_opp_table: opp-table-gr3d { - compatible = "operating-points-v2"; - - opp-114000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <114000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_950>; - }; - - opp-161500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <161500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-161500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <161500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_950>; - }; - - opp-209000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <209000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1000>; - }; - - opp-218500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <218500000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_950>; - }; - - opp-247000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1100>; - }; - - opp-247000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_950>; - }; - - opp-256500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <256500000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-285000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1100>; - }; - - opp-285000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1000>; - }; - - opp-304000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <304000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1200>; - }; - - opp-323000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <323000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-333500000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <333500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1275>; - }; - - opp-333500000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <333500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1200>; - }; - - opp-351500000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <351500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1100>; - }; - - opp-361000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <361000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1275>; - }; - - opp-380000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>; - }; - - opp-400000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1275>; - }; - - opp-400000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1200>; - }; - }; - - disp1_dvfs_opp_table: opp-table-disp1 { - compatible = "operating-points-v2"; - - opp-158000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <158000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-190000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; - - disp2_dvfs_opp_table: opp-table-disp2 { - compatible = "operating-points-v2"; - - opp-158000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <158000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-190000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; - - dsi_dvfs_opp_table: opp-table-dsi { - compatible = "operating-points-v2"; - - opp-100000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-500000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <500000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - hdmi_dvfs_opp_table: opp-table-hdmi { - compatible = "operating-points-v2"; - - opp-148500000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <148500000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - tvo_dvfs_opp_table: opp-table-tvo { - compatible = "operating-points-v2"; - - opp-250000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <250000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sclk_dvfs_opp_table: opp-table-sclk { - compatible = "operating-points-v2"; - - opp-95000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <95000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_950>; - }; - - opp-123500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <123500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_950>; - }; - - opp-133000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-152000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <152000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_950>; - }; - - opp-159500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <159500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1000>; - }; - - opp-171000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <171000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_950>; - }; - - opp-180500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <180500000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-190000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1100>; - }; - - opp-207000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <207000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1100>; - }; - - opp-218500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <218500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1000>; - }; - - opp-222500000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <222500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1200>; - }; - - opp-229500000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <229500000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-240000000-1225 { - opp-microvolt = <1225000 1225000 1300000>; - opp-hz = /bits/ 64 <240000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1225>; - }; - - opp-240000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <240000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1200>; - }; - - opp-247000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1275>; - }; - - opp-256500000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <256500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1100>; - }; - - opp-260000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <260000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>; - }; - - opp-262000000-1300 { - opp-microvolt = <1300000 1300000 1300000>; - opp-hz = /bits/ 64 <262000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1300>; - }; - - opp-264000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <264000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1275>; - }; - - opp-277500000-1300 { - opp-microvolt = <1300000 1300000 1300000>; - opp-hz = /bits/ 64 <277500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1300>; - }; - - opp-285000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1275>; - }; - - opp-292500000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <292500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1200>; - }; - - opp-300000000-1300 { - opp-microvolt = <1300000 1300000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-300000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1275>; - }; - }; - - vde_dvfs_opp_table: opp-table-vde { - compatible = "operating-points-v2"; - - opp-95000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <95000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_950>; - }; - - opp-123500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <123500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-123500000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <123500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_950>; - }; - - opp-152000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <152000000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1000>; - }; - - opp-152000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <152000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_950>; - }; - - opp-171000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <171000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_950>; - }; - - opp-209000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <209000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1100>; - }; - - opp-209000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <209000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-218500000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <218500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1000>; - }; - - opp-237500000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <237500000>; - opp-supported-hw = <0x0002>; - required-opps = <&core_opp_1100>; - }; - - opp-275500000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <275500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1200>; - }; - - opp-285000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-300000000-1275 { - opp-microvolt = <1275000 1275000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1275>; - }; - - opp-300000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1200>; - }; - - opp-300000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1100>; - }; - }; - - ndflash_dvfs_opp_table: opp-table-ndflash { - compatible = "operating-points-v2"; - - opp-130000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <130000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-150000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <150000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-158000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <158000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - - opp-164000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <164000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - nor_dvfs_opp_table: opp-table-nor { - compatible = "operating-points-v2"; - - opp-92000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <92000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { - compatible = "operating-points-v2"; - - opp-44000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <44000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - sdmmc2_dvfs_opp_table: opp-table-sdmmc2 { - compatible = "operating-points-v2"; - - opp-44000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <44000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { - compatible = "operating-points-v2"; - - opp-44000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <44000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { - compatible = "operating-points-v2"; - - opp-44000000-950 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <44000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1300000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - pcie_dvfs_opp_table: opp-table-pcie { - compatible = "operating-points-v2"; - - opp-250000000-1200 { - opp-microvolt = <1200000 1200000 1300000>; - opp-hz = /bits/ 64 <250000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - usbd_dvfs_opp_table: opp-table-usbd { - compatible = "operating-points-v2"; - - opp-480000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; - - usb2_dvfs_opp_table: opp-table-usb2 { - compatible = "operating-points-v2"; - - opp-480000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; - - usb3_dvfs_opp_table: opp-table-usb3 { - compatible = "operating-points-v2"; - - opp-480000000-1100 { - opp-microvolt = <1100000 1100000 1300000>; - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts deleted file mode 100644 index 71a8236491df..000000000000 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Plutux board"; - compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - sound { - compatible = "ad,tegra-audio-plutux", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design Plutux"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - vcc_24v_reg: regulator-24v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts deleted file mode 100644 index bd4ff8b40b20..000000000000 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ /dev/null @@ -1,920 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Seaboard"; - compatible = "nvidia,seaboard", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", - "lsck", "lsda"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lsc0", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", "gmd", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxd", "slxk", "spdi", "spdo", "uac", - "uad", "uca", "ucb", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", - "gpv", "owc", "slxc", "spib", "spid", - "spie"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spia", - "spig", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "spic", "uaa", - "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux-i2cmux-ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_idle: pinmux-i2cmux-idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux-i2cmux-pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - /* ALS and proximity sensor */ - isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - gyrometer@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0xc>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <32>; - nvidia,repeat-delay-ms = <160>; - nvidia,ghost-filter; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - memory-controller@7000f400 { - emc-table@190000 { - reg = <190000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <190000>; - nvidia,emc-registers = <0x0000000c 0x00000026 - 0x00000009 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x0000059f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000b 0x000000c8 - 0x00000003 0x00000007 0x00000004 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xa06204ae - 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@380000 { - reg = <380000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <380000>; - nvidia,emc-registers = <0x00000017 0x0000004b - 0x00000012 0x00000006 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000b5f - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe044048b - 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - dr_mode = "otg"; - }; - - usb@c5004000 { - status = "okay"; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - mmc@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - mmc@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - mmc@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 2 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - switch-lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - }; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wa01a"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator-1v5 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator-1v2 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_reg: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "vdd_vbus_wup1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) 0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_pnl_reg: regulator-pnl { - compatible = "regulator-fixed"; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_hdmi: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-seaboard", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Seaboard"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1R", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi deleted file mode 100644 index ddb84e4a9f8b..000000000000 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra20.dtsi" - -/ { - model = "Avionic Design Tamonten SOM"; - compatible = "ad,tamonten", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "dtf", - "gma", "gmb", "gmc", "gmd", "gme", "gpu7", - "gpv", "i2cp", "irrx", "irtx", "pta", - "rm", "slxa", "slxk", "spia", "spib", - "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc", "uad", "uca"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = ; - }; - conf_sdd { - nvidia,pins = "sdd", "spic", "spie", "spih", - "uaa", "uab", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - - state_i2cmux_ddc: pinmux-i2cmux-ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_idle: pinmux-i2cmux-idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux-i2cmux-pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - status = "okay"; - }; - - i2c@7000c400 { - clock-frequency = <100000>; - status = "okay"; - }; - - i2c@7000d000 { - clock-frequency = <400000>; - status = "okay"; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - /* vdd_5v0_reg must be provided by the base board */ - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sys_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sys_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sys_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - pci_clk_reg: ldo0 { - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - /* - * According to the Tegra 2 Automotive - * DataSheet, a typical value for this - * would be 2.8V, but the PMIC only - * supports 2.85V. - */ - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; - /* - * According to the Tegra 2 Automotive - * DataSheet, a typical value for this - * would be 2.8V, but the PMIC only - * supports 2.85V. - */ - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - pcie@80003000 { - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - mmc@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - status = "okay"; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pci_vdd_reg: regulator-1v05 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; - enable-active-high; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts deleted file mode 100644 index 4f41c74384b2..000000000000 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Tamonten Evaluation Carrier"; - compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - pcie@80003000 { - status = "okay"; - - pci@1,0 { - status = "okay"; - }; - }; - - sound { - compatible = "ad,tegra-audio-wm8903-tec", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design TEC"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - vcc_24v_reg: regulator-24v { - compatible = "regulator-fixed"; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts deleted file mode 100644 index 1944121e2dd6..000000000000 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" - -/ { - model = "Compulab TrimSlice board"; - compatible = "compulab,trimslice", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c500/rtc@56"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc", "gmb"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gme", "pta"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc", "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "uarta"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "sdio3"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "spdif"; - }; - spia { - nvidia,pins = "spia", "spib", "spic"; - nvidia,function = "spi2"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "crtp", "dap2", "dap3", "dap4", "dta", - "dtb", "dtc", "dtd", "dte", "gmb", - "gme", "i2cp", "pta", "slxc", "slxd", - "spdi", "spdo", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atb { - nvidia,pins = "atb", "cdev1", "cdev2", "dap1", - "gma", "gmc", "gmd", "gpu", "gpu7", - "gpv", "sdio1", "slxa", "slxk", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", - "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "pmc"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "kbca", "kbcb", - "kbcc", "kbcd", "kbce", "kbcf", "owc", - "spic", "spie", "spig", "spih", "uaa", - "uab", "uad", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - conf_spif { - nvidia,pins = "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - dvi_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - spi@7000c380 { - status = "okay"; - spi-max-frequency = <48000000>; - - flash@0 { - compatible = "winbond,w25q80bl", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <48000000>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - codec: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; - - rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - pcie@80003000 { - status = "okay"; - - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - - pci@1,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - }; - - usb@c5004000 { - status = "okay"; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - mmc@c8000000 { - status = "okay"; - broken-cd; - bus-width = <4>; - }; - - mmc@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - - hdmi_vdd_reg: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hdmi_pll_reg: regulator-hdmipll { - compatible = "regulator-fixed"; - regulator-name = "avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vbus_reg: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(V, 2) 0>; - regulator-always-on; - regulator-boot-on; - }; - - pci_clk_reg: regulator-pciclk { - compatible = "regulator-fixed"; - regulator-name = "pci_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pci_vdd_reg: regulator-pcivdd { - compatible = "regulator-fixed"; - regulator-name = "pci_vdd"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - vdd_core: regulator-core { - compatible = "regulator-fixed"; - regulator-name = "vdd_core"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - sound { - compatible = "nvidia,tegra-audio-trimslice"; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts deleted file mode 100644 index 433575a6ad38..000000000000 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ /dev/null @@ -1,755 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" -#include "tegra20-cpu-opp-microvolt.dtsi" - -/ { - model = "NVIDIA Tegra20 Ventana evaluation board"; - compatible = "nvidia,ventana", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", "lsda", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxc", "slxd", "slxk", "spdi", "spdo", - "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", "gmd", - "gpv", "owc", "spia", "spib", "spic", - "spid", "spie", "spig"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux-i2cmux-ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_idle: pinmux-i2cmux-idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux-i2cmux-pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - /* ALS and proximity sensor */ - isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&rtc_vdd &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-core-regulator; - }; - - vdd_cpu: sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1125000>; - regulator-coupled-with = <&vdd_core &rtc_vdd>; - regulator-coupled-max-spread = <550000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-cpu-regulator; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - rtc_vdd: ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&vdd_core &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-rtc-regulator; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - nct1008: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - #thermal-sensor-cells = <1>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - mmc@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - mmc@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - mmc@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 2 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wa01a"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator-1v5 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator-1v2 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_pnl_reg: regulator-pnl { - compatible = "regulator-fixed"; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-ventana", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Ventana"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) - GPIO_ACTIVE_HIGH>; - nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip0: cpu-alert0 { - /* start throttling at 50C */ - temperature = <50000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: cpu-crit { - /* shut down at 60C */ - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi deleted file mode 100644 index 4177d04265d8..000000000000 --- a/arch/arm/boot/dts/tegra20.dtsi +++ /dev/null @@ -1,1061 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include - -#include "tegra20-peripherals-opp.dtsi" - -/ { - compatible = "nvidia,tegra20"; - interrupt-parent = <&lic>; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - sram@40000000 { - compatible = "mmio-sram"; - reg = <0x40000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000>; - - vde_pool: sram@400 { - reg = <0x400 0x3fc00>; - pool; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra20-host1x"; - reg = <0x50000000 0x00024000>; - interrupts = , /* syncpt */ - ; /* general */ - interrupt-names = "syncpt", "host1x"; - clocks = <&tegra_car TEGRA20_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; - reset-names = "host1x", "mc"; - power-domains = <&pd_core>; - operating-points-v2 = <&host1x_dvfs_opp_table>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe@54040000 { - compatible = "nvidia,tegra20-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - power-domains = <&pd_mpe>; - operating-points-v2 = <&mpe_dvfs_opp_table>; - status = "disabled"; - }; - - vi@54080000 { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 20>; - reset-names = "vi"; - power-domains = <&pd_venc>; - operating-points-v2 = <&vi_dvfs_opp_table>; - status = "disabled"; - }; - - epp@540c0000 { - compatible = "nvidia,tegra20-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - power-domains = <&pd_core>; - operating-points-v2 = <&epp_dvfs_opp_table>; - status = "disabled"; - }; - - isp@54100000 { - compatible = "nvidia,tegra20-isp"; - reg = <0x54100000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - power-domains = <&pd_venc>; - status = "disabled"; - }; - - gr2d@54140000 { - compatible = "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; - reset-names = "2d", "mc"; - power-domains = <&pd_core>; - operating-points-v2 = <&gr2d_dvfs_opp_table>; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; - reset-names = "3d", "mc"; - power-domains = <&pd_3d>; - operating-points-v2 = <&gr3d_dvfs_opp_table>; - }; - - dc@54200000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP1>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - power-domains = <&pd_core>; - operating-points-v2 = <&disp1_dvfs_opp_table>; - - nvidia,head = <0>; - - interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, - <&mc TEGRA20_MC_DISPLAY0B &emc>, - <&mc TEGRA20_MC_DISPLAY1B &emc>, - <&mc TEGRA20_MC_DISPLAY0C &emc>, - <&mc TEGRA20_MC_DISPLAYHC &emc>; - interconnect-names = "wina", - "winb", - "winb-vfilter", - "winc", - "cursor"; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP2>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - power-domains = <&pd_core>; - operating-points-v2 = <&disp2_dvfs_opp_table>; - - nvidia,head = <1>; - - interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, - <&mc TEGRA20_MC_DISPLAY0BB &emc>, - <&mc TEGRA20_MC_DISPLAY1BB &emc>, - <&mc TEGRA20_MC_DISPLAY0CB &emc>, - <&mc TEGRA20_MC_DISPLAYHCB &emc>; - interconnect-names = "wina", - "winb", - "winb-vfilter", - "winc", - "cursor"; - - rgb { - status = "disabled"; - }; - }; - - tegra_hdmi: hdmi@54280000 { - compatible = "nvidia,tegra20-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_HDMI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - power-domains = <&pd_core>; - operating-points-v2 = <&hdmi_dvfs_opp_table>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - tvo@542c0000 { - compatible = "nvidia,tegra20-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_TVO>; - power-domains = <&pd_core>; - operating-points-v2 = <&tvo_dvfs_opp_table>; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "dsi", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - power-domains = <&pd_core>; - operating-points-v2 = <&dsi_dvfs_opp_table>; - status = "disabled"; - }; - }; - - timer@50040600 { - compatible = "arm,cortex-a9-twd-timer"; - interrupt-parent = <&intc>; - reg = <0x50040600 0x20>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_TWD>; - }; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000>, - <0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <5 5 2>; - arm,tag-latency = <4 4 2>; - cache-unified; - cache-level = <2>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra20-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - timer@60005000 { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = , - , - , - ; - clocks = <&tegra_car TEGRA20_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - sclk { - compatible = "nvidia,tegra20-sclk"; - clocks = <&tegra_car TEGRA20_CLK_SCLK>; - power-domains = <&pd_core>; - operating-points-v2 = <&sclk_dvfs_opp_table>; - }; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra20-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA20_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb@6000c000 { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra20-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-ranges = <&pinmux 0 0 224>; - }; - - vde@6001a000 { - compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000>, /* Syntax Engine */ - <0x6001b000 0x1000>, /* Video Bitstream Engine */ - <0x6001c000 0x100>, /* Macroblock Engine */ - <0x6001c200 0x100>, /* Post-processing Engine */ - <0x6001c400 0x100>, /* Motion Compensation Engine */ - <0x6001c600 0x100>, /* Transform Engine */ - <0x6001c800 0x100>, /* Pixel prediction block */ - <0x6001ca00 0x100>, /* Video DMA */ - <0x6001d800 0x300>; /* Video frame controls */ - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA20_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; - power-domains = <&pd_vde>; - operating-points-v2 = <&vde_dvfs_opp_table>; - }; - - pinmux: pinmux@70000014 { - compatible = "nvidia,tegra20-pinmux"; - reg = <0x70000014 0x10>, /* Tri-state registers */ - <0x70000080 0x20>, /* Mux registers */ - <0x700000a0 0x14>, /* Pull-up/down registers */ - <0x70000868 0xa8>; /* Pad control registers */ - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64>, /* Chip revision */ - <0x70000008 0x04>; /* Strapping options */ - }; - - das@70000c00 { - compatible = "nvidia,tegra20-das"; - reg = <0x70000c00 0x80>; - }; - - tegra_ac97: ac97@70002000 { - compatible = "nvidia,tegra20-ac97"; - reg = <0x70002000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_AC97>; - resets = <&tegra_car 3>; - reset-names = "ac97"; - dmas = <&apbdma 12>, <&apbdma 12>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tegra_spdif: spdif@70002400 { - compatible = "nvidia,tegra20-spdif"; - reg = <0x70002400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, - <&tegra_car TEGRA20_CLK_SPDIF_IN>; - clock-names = "out", "in"; - resets = <&tegra_car 10>; - dmas = <&apbdma 3>, <&apbdma 3>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - - assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; - }; - - tegra_i2s1: i2s@70002800 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002800 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - dmas = <&apbdma 2>, <&apbdma 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70002a00 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002a00 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - dmas = <&apbdma 1>, <&apbdma 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra20-uart" and to enable the APB DMA based serial - * driver, the compatible is "nvidia,tegra20-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uarte: serial@70006400 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - nand-controller@70008000 { - compatible = "nvidia,tegra20-nand"; - reg = <0x70008000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names = "nand"; - resets = <&tegra_car 13>; - reset-names = "nand"; - assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - assigned-clock-rates = <150000000>; - power-domains = <&pd_core>; - operating-points-v2 = <&ndflash_dvfs_opp_table>; - status = "disabled"; - }; - - gmi@70009000 { - compatible = "nvidia,tegra20-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xd0000000 0xfffffff>; - clocks = <&tegra_car TEGRA20_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - power-domains = <&pd_core>; - operating-points-v2 = <&nor_dvfs_opp_table>; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA20_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C1>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000c380 { - compatible = "nvidia,tegra20-sflash"; - reg = <0x7000c380 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SPI>; - resets = <&tegra_car 43>; - reset-names = "spi"; - dmas = <&apbdma 11>, <&apbdma 11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c2: i2c@7000c400 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C2>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra20-i2c-dvc"; - reg = <0x7000d000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_DVC>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC1>; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC2>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC3>; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC4>; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_RTC>; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - - pd_core: core-domain { - #power-domain-cells = <0>; - operating-points-v2 = <&core_opp_table>; - }; - - powergates { - pd_mpe: mpe { - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&mc TEGRA20_MC_RESET_MPEA>, - <&mc TEGRA20_MC_RESET_MPEB>, - <&mc TEGRA20_MC_RESET_MPEC>, - <&tegra_car TEGRA20_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_3d: td { - clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&mc TEGRA20_MC_RESET_3D>, - <&tegra_car TEGRA20_CLK_GR3D>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA20_CLK_VDE>; - resets = <&mc TEGRA20_MC_RESET_VDE>, - <&tegra_car TEGRA20_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_venc: venc { - clocks = <&tegra_car TEGRA20_CLK_ISP>, - <&tegra_car TEGRA20_CLK_VI>, - <&tegra_car TEGRA20_CLK_CSI>; - resets = <&mc TEGRA20_MC_RESET_ISP>, - <&mc TEGRA20_MC_RESET_VI>, - <&tegra_car TEGRA20_CLK_ISP>, - <&tegra_car 20 /* VI */>, - <&tegra_car TEGRA20_CLK_CSI>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - }; - }; - - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x00000400>, /* controller registers */ - <0x58000000 0x02000000>; /* GART aperture */ - clocks = <&tegra_car TEGRA20_CLK_MC>; - clock-names = "mc"; - interrupts = ; - #reset-cells = <1>; - #iommu-cells = <0>; - #interconnect-cells = <1>; - }; - - emc: memory-controller@7000f400 { - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - power-domains = <&pd_core>; - #address-cells = <1>; - #size-cells = <0>; - #interconnect-cells = <0>; - - nvidia,memory-controller = <&mc>; - operating-points-v2 = <&emc_icc_dvfs_opp_table>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - pcie@80003000 { - compatible = "nvidia,tegra20-pcie"; - device_type = "pci"; - reg = <0x80003000 0x00000800>, /* PADS registers */ - <0x80003800 0x00000200>, /* AFI registers */ - <0x90000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ - <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ - <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ - <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ - <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA20_CLK_PEX>, - <&tegra_car TEGRA20_CLK_AFI>, - <&tegra_car TEGRA20_CLK_PLL_E>; - clock-names = "pex", "afi", "pll_e"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - power-domains = <&pd_core>; - operating-points-v2 = <&pcie_dvfs_opp_table>; - - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - - usb@c5000000 { - compatible = "nvidia,tegra20-ehci"; - reg = <0xc5000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,needs-double-reset; - nvidia,phy = <&phy1>; - power-domains = <&pd_core>; - operating-points-v2 = <&usbd_dvfs_opp_table>; - status = "disabled"; - }; - - phy1: usb-phy@c5000000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000000 0x4000>, - <0xc5000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USBD>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CLK_M>, - <&tegra_car TEGRA20_CLK_USBD>; - clock-names = "reg", "pll_u", "timer", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,has-legacy-mode; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <1>; - nvidia,xcvr-lsrslew = <1>; - nvidia,has-utmi-pad-registers; - nvidia,pmc = <&tegra_pmc 0>; - status = "disabled"; - }; - - usb@c5004000 { - compatible = "nvidia,tegra20-ehci"; - reg = <0xc5004000 0x4000>; - interrupts = ; - phy_type = "ulpi"; - clocks = <&tegra_car TEGRA20_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - power-domains = <&pd_core>; - operating-points-v2 = <&usb2_dvfs_opp_table>; - status = "disabled"; - }; - - phy2: usb-phy@c5004000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004000 0x4000>; - interrupts = ; - phy_type = "ulpi"; - clocks = <&tegra_car TEGRA20_CLK_USB2>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CDEV2>; - clock-names = "reg", "pll_u", "ulpi-link"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,pmc = <&tegra_pmc 1>; - status = "disabled"; - }; - - usb@c5008000 { - compatible = "nvidia,tegra20-ehci"; - reg = <0xc5008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - power-domains = <&pd_core>; - operating-points-v2 = <&usb3_dvfs_opp_table>; - status = "disabled"; - }; - - phy3: usb-phy@c5008000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008000 0x4000>, - <0xc5000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USB3>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CLK_M>, - <&tegra_car TEGRA20_CLK_USBD>; - clock-names = "reg", "pll_u", "timer", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,pmc = <&tegra_pmc 2>; - status = "disabled"; - }; - - mmc@c8000000 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - power-domains = <&pd_core>; - operating-points-v2 = <&sdmmc1_dvfs_opp_table>; - status = "disabled"; - }; - - mmc@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - power-domains = <&pd_core>; - operating-points-v2 = <&sdmmc2_dvfs_opp_table>; - status = "disabled"; - }; - - mmc@c8000400 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - power-domains = <&pd_core>; - operating-points-v2 = <&sdmmc3_dvfs_opp_table>; - status = "disabled"; - }; - - mmc@c8000600 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - power-domains = <&pd_core>; - operating-points-v2 = <&sdmmc4_dvfs_opp_table>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&tegra_car TEGRA20_CLK_CCLK>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&tegra_car TEGRA20_CLK_CCLK>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>; - }; - - sound-hdmi { - compatible = "simple-audio-card"; - simple-audio-card,name = "NVIDIA Tegra20 HDMI"; - - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - - codec { - sound-dai = <&tegra_hdmi>; - }; - - cpu { - sound-dai = <&tegra_spdif>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts deleted file mode 100644 index 842b5faba285..000000000000 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra30-apalis.dtsi" - -/ { - model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", - "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@3000 { - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - gpio@6000d000 { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on - * carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* SPI5: Apalis SPI2 */ - spi@7000dc00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* Apalis SD1 */ - mmc@78000000 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* Apalis MMC1 */ - mmc@78000400 { - status = "okay"; - bus-width = <8>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts deleted file mode 100644 index ca277bf1df78..000000000000 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/dts-v1/; - -#include -#include "tegra30-apalis-v1.1.dtsi" - -/ { - model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval", - "toradex,apalis_t30-v1.1", "toradex,apalis_t30", - "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@3000 { - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - gpio@6000d000 { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on - * carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* SPI5: Apalis SPI2 */ - spi@7000dc00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* Apalis SD1 */ - mmc@78000000 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* Apalis MMC1 */ - mmc@78000400 { - status = "okay"; - bus-width = <8>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - vqmmc-supply = <®_vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* - * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on - * EN_+3.3_SDMMC3 GPIO - */ - reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-type = "voltage"; - gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - startup-delay-us = <100000>; - vin-supply = <&vddio_sdmmc_1v8_reg>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi deleted file mode 100644 index a4b7fe5c3d23..000000000000 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ /dev/null @@ -1,1202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -#include "tegra30.dtsi" - -/* - * Toradex Apalis T30 Module Device Tree - * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; - * 2GB: V1.1A, V1.1B - */ -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - pcie@3000 { - status = "okay"; - avdd-pexa-supply = <&vdd2_reg>; - avdd-pexb-supply = <&vdd2_reg>; - avdd-pex-pll-supply = <&vdd2_reg>; - avdd-plle-supply = <&ldo6_reg>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - vdd-pexa-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; - - /* Apalis type specific */ - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - /* Apalis PCIe */ - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - /* I210/I211 Gigabit Ethernet Controller (on-module) */ - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - - ethernet@0,0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - clk1-out-pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis BKL1_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - uart3-rts-n-pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ - uart3-cts-n-pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN1 on SPI6 */ - spi2-cs0-n-px3 { - nvidia,pins = "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* CAN_INT1 */ - spi2-cs1-n-pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN2 on SPI4 */ - gmi-a16-pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* CAN_INT2 */ - spi2-cs2-n-pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - clk1-req-pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk2-out-pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis GPIO */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis HDMI1 */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis LCD1 */ - lcd-d0-pe0 { - nvidia,pins = "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_pclk_pb3", - "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis MMC1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis MMC1_CD# */ - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Parallel Camera */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi-vsync-pd6 { - nvidia,pins = "vi_d0_pt4", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_pclk_pt0", - "vi_vsync_pd6"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_row4_pr4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { - nvidia,pins = "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * VI level-shifter direction - * (pull-down => default direction input) - */ - vi-mclk-pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM1 */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM2 */ - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM3 */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM4 */ - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis RESET_MOCI# */ - gmi-rst-n-pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SATA1_ACT# */ - pex-l0-prsnt-n-pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis SD1_CD# */ - clk2-req-pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF1 */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5", - "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - spi1-sck-px5 { - nvidia,pins = "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_miso_px7", - "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SPI2 */ - lcd-sck-pz4 { - nvidia,pins = "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_sdin_pz2", - "lcd_cs0_n_pn4"; - nvidia,function = "spi5"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Apalis TS (Low-speed type specific) - * pins may be used as GPIOs - */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7", - "kb_row8_ps0", - "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - ulpi-data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART2 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART3 */ - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART4 */ - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBH_EN */ - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_OC# */ - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBO1_OC# */ - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis VGA1 not supported and therefore disabled */ - crt-hsync-pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* EN_+3.3_SDMMC3 */ - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ - pex-l2-prsnt-n-pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 SMB_ALERT_N (On-module) */ - sys-clk-req-pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LVDS Transceiver Configuration */ - pbb0 { - nvidia,pins = "pbb0", - "pbb7", - "pcc1", - "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Not connected and therefore disabled */ - clk-32k-out-pa0 { - nvidia,pins = "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_out_pa0", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "lcd_dc0_pn6", - "lcd_m1_pw1", - "lcd_pwr1_pc1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-ad0-pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "lcd_cs1_n_pw0", - "pu0", - "pu1", - "pu2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs0-n-pj0 { - nvidia,pins = "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs6-n-pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs7-n-pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr0-pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pwr2_pc6", - "lcd_wr_n_pz3"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rts-n-pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Power I2C (On-module) */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd-dc1-pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# (On-module) */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vio>; - VDDIO-supply = <®_module_3v3>; - clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <®_module_3v3>; - vcc2-supply = <®_module_3v3>; - vcc3-supply = <®_1v8_vio>; - vcc4-supply = <®_module_3v3>; - vcc5-supply = <®_module_3v3>; - vcc6-supply = <®_1v8_vio>; - vcc7-supply = <®_5v0_charge_pump>; - vccio-supply = <®_module_3v3>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "+V1.35_VDDIO_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddctrl_reg: vddctrl { - regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - reg_1v8_vio: vio { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* - * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3 - * is off - */ - vddio_sdmmc_1v8_reg: ldo1 { - regulator-name = "+VDDIO_SDMMC3_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 - * see also +V3.3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "EN_+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "+V1.2_CSI"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4_reg: ldo4 { - regulator-name = "+V1.2_VDD_RTC"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for (unsupported) analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "+V2.8_AVDD_VDAC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "+V1.05_AVDD_PLLE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "+V1.2_AVDD_PLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "+V1.0_VDD_DDR_HS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - regulator@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - /* SPI4: CAN2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - /* SPI6: CAN1 */ - spi@7000de00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x1>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080500 { - status = "okay"; - }; - }; - - /* eMMC */ - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - clk16m: clock-osc4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - clk32k_in: clock-xtal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_1v8_vio>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_module_3v3>; - }; - - reg_5v0_charge_pump: regulator-5v0-charge-pump { - compatible = "regulator-fixed"; - regulator-name = "+V5.0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi deleted file mode 100644 index d73103884000..000000000000 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ /dev/null @@ -1,1185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra30.dtsi" - -/* - * Toradex Apalis T30 Module Device Tree - * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E - */ -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - pcie@3000 { - status = "okay"; - avdd-pexa-supply = <&vdd2_reg>; - avdd-pexb-supply = <&vdd2_reg>; - avdd-pex-pll-supply = <&vdd2_reg>; - avdd-plle-supply = <&ldo6_reg>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - vdd-pexa-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; - - /* Apalis type specific */ - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - /* Apalis PCIe */ - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - /* I210/I211 Gigabit Ethernet Controller (on-module) */ - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - - ethernet@0,0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - clk1-out-pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis BKL1_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - uart3-rts-n-pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ - uart3-cts-n-pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN1 on SPI6 */ - spi2-cs0-n-px3 { - nvidia,pins = "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* CAN_INT1 */ - spi2-cs1-n-pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN2 on SPI4 */ - gmi-a16-pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* CAN_INT2 */ - spi2-cs2-n-pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - clk1-req-pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk2-out-pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis GPIO */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis HDMI1 */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis LCD1 */ - lcd-d0-pe0 { - nvidia,pins = "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_pclk_pb3", - "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis MMC1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis MMC1_CD# */ - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Parallel Camera */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi-vsync-pd6 { - nvidia,pins = "vi_d0_pt4", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_pclk_pt0", - "vi_vsync_pd6"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_row4_pr4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { - nvidia,pins = "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * VI level-shifter direction - * (pull-down => default direction input) - */ - vi-mclk-pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM1 */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM2 */ - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM3 */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM4 */ - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis RESET_MOCI# */ - gmi-rst-n-pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SATA1_ACT# */ - pex-l0-prsnt-n-pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis SD1_CD# */ - clk2-req-pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF1 */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5", - "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - spi1-sck-px5 { - nvidia,pins = "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_miso_px7", - "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SPI2 */ - lcd-sck-pz4 { - nvidia,pins = "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_sdin_pz2", - "lcd_cs0_n_pn4"; - nvidia,function = "spi5"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Apalis TS (Low-speed type specific) - * pins may be used as GPIOs - */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7", - "kb_row8_ps0", - "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - ulpi-data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART2 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART3 */ - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART4 */ - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBH_EN */ - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_OC# */ - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBO1_OC# */ - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis VGA1 not supported and therefore disabled */ - crt-hsync-pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ - pex-l2-prsnt-n-pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 SMB_ALERT_N (On-module) */ - sys-clk-req-pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LVDS Transceiver Configuration */ - pbb0 { - nvidia,pins = "pbb0", - "pbb7", - "pcc1", - "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Not connected and therefore disabled */ - clk-32k-out-pa0 { - nvidia,pins = "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_out_pa0", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "lcd_dc0_pn6", - "lcd_m1_pw1", - "lcd_pwr1_pc1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-ad0-pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "lcd_cs1_n_pw0", - "pu0", - "pu1", - "pu2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs0-n-pj0 { - nvidia,pins = "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs6-n-pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs7-n-pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr0-pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pwr2_pc6", - "lcd_wr_n_pz3"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5", - "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Power I2C (On-module) */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd-dc1-pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# (On-module) */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vio>; - VDDIO-supply = <®_module_3v3>; - clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <®_module_3v3>; - vcc2-supply = <®_module_3v3>; - vcc3-supply = <®_1v8_vio>; - vcc4-supply = <®_module_3v3>; - vcc5-supply = <®_module_3v3>; - vcc6-supply = <®_1v8_vio>; - vcc7-supply = <®_5v0_charge_pump>; - vccio-supply = <®_module_3v3>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "+V1.35_VDDIO_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddctrl_reg: vddctrl { - regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - reg_1v8_vio: vio { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO1: unused */ - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 - * see also +V3.3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "EN_+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "+V1.2_CSI"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4_reg: ldo4 { - regulator-name = "+V1.2_VDD_RTC"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for (unsupported) analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "+V2.8_AVDD_VDAC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "+V1.05_AVDD_PLLE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "+V1.2_AVDD_PLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "+V1.0_VDD_DDR_HS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - regulator@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - /* SPI4: CAN2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - /* SPI6: CAN1 */ - spi@7000de00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x1>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080500 { - status = "okay"; - }; - }; - - /* eMMC */ - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - clk16m: clock-osc4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - clk32k_in: clock-xtal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_1v8_vio>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_module_3v3>; - }; - - reg_5v0_charge_pump: regulator-5v0-charge-pump { - compatible = "regulator-fixed"; - regulator-name = "+V5.0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi deleted file mode 100644 index bae09d82594d..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ - -#include - -/ { - host1x@50000000 { - lcd: dc@54200000 { - rgb { - status = "okay"; - - port@0 { - dpi_output: endpoint { - remote-endpoint = <&bridge_input>; - bus-width = <24>; - }; - }; - }; - }; - }; - - display-panel { - power-supply = <&vdd_pnl>; - ddc-i2c-bus = <&lcd_ddc>; - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&bridge_output>; - }; - }; - }; - - /* Texas Instruments SN75LVDS83B LVDS Transmitter */ - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_input: endpoint { - remote-endpoint = <&dpi_output>; - }; - }; - - port@1 { - reg = <1>; - - bridge_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts deleted file mode 100644 index a25b8560b0cd..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" -#include "tegra30-asus-nexus7-grouper.dtsi" - -/ { - model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts deleted file mode 100644 index 06ef13ea5df8..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-nexus7-grouper-ti-pmic.dtsi" -#include "tegra30-asus-nexus7-grouper.dtsi" - -/ { - model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi deleted file mode 100644 index c0062353c1f1..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ /dev/null @@ -1,1320 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include - -#include "tegra30.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" -#include "tegra30-asus-lvds-display.dtsi" - -/ { - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc3; /* WiFi */ - - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma@80000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x80000000 0x30000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - - ramoops@bfdf0000 { - compatible = "ramoops"; - reg = <0xbfdf0000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - trustzone@bfe00000 { - reg = <0xbfe00000 0x200000>; - no-map; - }; - }; - - gpio@6000d000 { - init-low-power-mode-hog { - gpio-hog; - gpios = ; - input; - }; - - init-mode-hog { - gpio-hog; - gpios = , - , - ; - output-low; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat3_pb4", - "sdmmc3_dat2_pb5", - "sdmmc3_dat1_pb6", - "sdmmc3_dat0_pb7", - "sdmmc3_dat4_pd1", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pwr1_pc1", - "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_vsync_pj4", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_cs0_n_pn4", - "lcd_sdout_pn5", - "lcd_dc0_pn6", - "lcd_cs1_n_pw0", - "lcd_sdin_pz2", - "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2", - "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7", - "gmi_wait_pi7", - "gmi_cs4_n_pk2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad14_ph6", - "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4", - "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5", - "gmi_wr_n_pi0", - "gmi_oe_n_pi1", - "gmi_adv_n_pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad15_ph7 { - nvidia,pins = "gmi_ad15_ph7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2", - "pu2", - "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6", - "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2", - "kb_col3_pq3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4", - "kb_col5_pq5", - "kb_col7_pq7", - "kb_row2_pr2", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6", - "kb_row8_ps0", - "kb_row9_ps1", - "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3", - "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0", - "pu6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2", - "spi2_miso_px1", - "spi2_sck_px2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs0_n_px3 { - nvidia,pins = "spi2_cs0_n_px3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4", - "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4", - "sdmmc1_dat2_py5", - "sdmmc1_dat1_py6", - "sdmmc1_dat0_py7", - "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb0 { - nvidia,pins = "pbb0", - "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7", - "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3", - "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - drive_dap1 { - nvidia,pins = "drive_dap1", - "drive_dap2", - "drive_dbg", - "drive_at5", - "drive_gme", - "drive_ddc", - "drive_ao1", - "drive_uart3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1", - "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - /* GPS BCM4751 */ - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>, - <1000000 4000000 136>; - - /* Azurewave AW-NH665 BCM4330B1 */ - bluetooth { - compatible = "brcm,bcm4330-bt"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - max-speed = <4000000>; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; - - vbat-supply = <&vdd_3v3_sys>; - vddio-supply = <&vdd_1v8>; - - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c400 { - clock-frequency = <400000>; - status = "okay"; - - touchscreen@10 { - compatible = "elan,ektf3624"; - reg = <0x10>; - - interrupt-parent = <&gpio>; - interrupts = ; - - reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; - - vcc33-supply = <&vcc_3v3_ts>; - vccio-supply = <&vcc_3v3_ts>; - - touchscreen-size-x = <2112>; - touchscreen-size-y = <1280>; - touchscreen-swapped-x-y; - touchscreen-inverted-x; - }; - }; - - i2c@7000c500 { - clock-frequency = <100000>; - status = "okay"; - - compass@e { - compatible = "asahi-kasei,ak8974"; - reg = <0x0e>; - - interrupt-parent = <&gpio>; - interrupts = ; - - avdd-supply = <&vdd_3v3_sys>; - dvdd-supply = <&vdd_1v8>; - - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; - }; - - light-sensor@1c { - compatible = "dynaimage,al3010"; - reg = <0x1c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - }; - - accelerometer@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - vddio-supply = <&vdd_1v8>; - - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; - }; - }; - - i2c@7000d000 { - clock-frequency = <100000>; - status = "okay"; - - rt5640: audio-codec@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - - realtek,dmic1-data-pin = <1>; - }; - - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&vdd_3v3_sys>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - - fuel-gauge@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - power-supplies = <&power_supply>; - }; - - power_supply: charger@6a { - compatible = "summit,smb347"; - reg = <0x6a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - summit,enable-charge-control = ; - summit,inok-polarity = ; - summit,enable-usb-charging; - - monitored-battery = <&battery_cell>; - - usb_vbus: usb-vbus { - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-min-microamp = <750000>; - regulator-max-microamp = <750000>; - - /* - * SMB347 INOK input pin is connected to PMIC's - * ACOK output, which is fixed to ACTIVE_LOW as - * long as battery voltage is in a good range. - * - * Active INOK disables SMB347 output, so polarity - * needs to be toggled when we want to get the - * output. - */ - summit,needs-inok-toggle; - }; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdmmc3: mmc@78000400 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; - assigned-clock-rates = <50000000>; - - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_1v8>; - - /* Azurewave AW-NH665 BCM4330 */ - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - sdmmc4: mmc@78000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_1v8>; - non-removable; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usb_vbus>; - }; - - usb-phy@7d000000 { - status = "okay"; - dr_mode = "otg"; - nvidia,hssync-start-delay = <0>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - power-supply = <&vdd_5v0_sys>; - pwms = <&pwm 0 50000>; - - brightness-levels = <1 255>; - num-interpolated-steps = <254>; - default-brightness-level = <15>; - }; - - battery_cell: battery-cell { - compatible = "simple-battery"; - constant-charge-current-max-microamp = <1800000>; - operating-range-celsius = <0 45>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - display-panel { - /* - * Nexus 7 supports two compatible panel models: - * - * 1. hydis,hv070wx2-1e0 - * 2. chunghwa,claa070wp03xg - * - * We want to use timing which is optimized for Nexus 7, - * hence we need to customize the timing. - */ - compatible = "panel-lvds"; - - width-mm = <94>; - height-mm = <150>; - rotation = <180>; - - data-mapping = "jeida-24"; - - /* DDC unconnected on Nexus 7 */ - /delete-property/ ddc-i2c-bus; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - switch-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - brcm_wifi_pwrseq: pwrseq-wifi { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <300000>; - gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vcc_3v3_ts: regulator-ts { - compatible = "regulator-fixed"; - regulator-name = "ldo_s-1167_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-grouper", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "ASUS Google Nexus 7 ALC5642"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Speakers", "SPORP", - "Speakers", "SPORN", - "Speakers", "SPOLP", - "Speakers", "SPOLN", - "DMIC1", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - thermal-zones { - /* - * NCT72 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents Nexus 7 - * from getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct72 0>; - - trips { - trip0: skin-alert { - /* throttle at 57C until temperature drops to 56.8C */ - temperature = <57000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 65C */ - temperature = <65000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct72 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi deleted file mode 100644 index 694c7fe37eb8..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include - -/ { - i2c@7000d000 { - pmic: pmic@3c { - compatible = "maxim,max77663"; - reg = <0x3c>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - system-power-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - cpu-pwr-req-hog { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - input; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - }; - - fps1 { - maxim,fps-event-source = ; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - max77620_default: pinmux { - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - in-sd4-supply = <&vdd_5v0_sys>; - - in-ldo0-1-supply = <&vdd_1v35>; - in-ldo2-supply = <&vdd_3v3_sys>; - in-ldo3-5-supply = <&vdd_3v3_sys>; - in-ldo4-6-supply = <&vdd_5v0_sys>; - in-ldo7-8-supply = <&vdd_1v35>; - - vdd_cpu: sd0 { - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-cpu-regulator; - }; - - vdd_core: sd1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-core-regulator; - }; - - vdd_1v8: sd2 { - regulator-name = "vdd_gen1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v35: sd3 { - regulator-name = "vdd_ddr3l_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo0 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd_ddr_rx"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - vcore_emmc: ldo3 { - regulator-name = "vcore_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo5 { - regulator-name = "vdd_camera"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6 { - regulator-name = "vddio_sdmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7 { - regulator-name = "avdd_dsi_csi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo8 { - regulator-name = "avdd_pll"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; - - vdd_3v3_sys: regulator-3v3 { - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - regulator-usb { - compatible = "regulator-fixed"; - regulator-name = "avdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - pmc@7000e400 { - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x3c>; - nvidia,reg-addr = <0x41>; - nvidia,reg-data = <0xe0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi deleted file mode 100644 index 8944a4a5a8d7..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ /dev/null @@ -1,1577 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - memory-controller@7000f000 { - emc-timings-0 { - nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < - 0x00020001 /* MC_EMEM_ARB_CFG */ - 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < - 0x00010001 /* MC_EMEM_ARB_CFG */ - 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x73430303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x72830504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x72440a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < - 0x00000005 /* MC_EMEM_ARB_CFG */ - 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ - 0x70850f09 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < - 0x0000000a /* MC_EMEM_ARB_CFG */ - 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ - 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < - 0x00020001 /* MC_EMEM_ARB_CFG */ - 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < - 0x00010001 /* MC_EMEM_ARB_CFG */ - 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x73430303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x72830504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x72440a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < - 0x00000005 /* MC_EMEM_ARB_CFG */ - 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ - 0x70850f09 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < - 0x0000000a /* MC_EMEM_ARB_CFG */ - 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ - 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000004 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x00000008 /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000009 /* EMC_TXSR */ - 0x00000009 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000005 /* EMC_RC */ - 0x00000010 /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000012 /* EMC_TXSR */ - 0x00000012 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000004 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x0000000a /* EMC_RC */ - 0x00000020 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000023 /* EMC_TXSR */ - 0x00000023 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < - 0x0000000f /* EMC_RC */ - 0x00000034 /* EMC_RFC */ - 0x0000000a /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x000009e9 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000039 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x0000000a /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000a2a /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x002600a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x00014000 /* EMC_DLL_XFORM_DQS4 */ - 0x00014000 /* EMC_DLL_XFORM_DQS5 */ - 0x00014000 /* EMC_DLL_XFORM_DQS6 */ - 0x00014000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x018b000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x0000001f /* EMC_RC */ - 0x00000069 /* EMC_RFC */ - 0x00000017 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000c /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000011 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000b /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001412 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000e /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x00000016 /* EMC_RW2PDEN */ - 0x00000072 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000007 /* EMC_TCLKSTOP */ - 0x00001453 /* EMC_TREFBW */ - 0x0000000c /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf00b0191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008 /* EMC_DLL_XFORM_DQS0 */ - 0x00000008 /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x00000008 /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000c /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0156000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ - 0xf8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000004 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x00000008 /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000009 /* EMC_TXSR */ - 0x00000009 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000005 /* EMC_RC */ - 0x00000010 /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000012 /* EMC_TXSR */ - 0x00000012 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000004 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x0000000a /* EMC_RC */ - 0x00000020 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000023 /* EMC_TXSR */ - 0x00000023 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < - 0x0000000f /* EMC_RC */ - 0x00000034 /* EMC_RFC */ - 0x0000000a /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x000009e9 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000039 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x0000000a /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000a2a /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x002600a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x00014000 /* EMC_DLL_XFORM_DQS4 */ - 0x00014000 /* EMC_DLL_XFORM_DQS5 */ - 0x00014000 /* EMC_DLL_XFORM_DQS6 */ - 0x00014000 /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x018b000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ - 0xf8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000020 /* EMC_RC */ - 0x0000006a /* EMC_RFC */ - 0x00000017 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000c /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000011 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001412 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000e /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x00000016 /* EMC_RW2PDEN */ - 0x00000072 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000007 /* EMC_TCLKSTOP */ - 0x00001453 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf00b0191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000c /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0400013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0155000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - }; - - opp-table-actmon { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; - }; - - opp-table-emc { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi deleted file mode 100644 index ee4a3f482769..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include - -/ { - i2c@7000d000 { - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; - ti,system-power-controller; - ti,sleep-keep-ck32k; - ti,sleep-enable; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v0_sys>; - vcc2-supply = <&vdd_5v0_sys>; - vcc3-supply = <&vdd_1v8>; - vcc4-supply = <&vdd_5v0_sys>; - vcc5-supply = <&vdd_5v0_sys>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v0_sys>; - vccio-supply = <&vdd_5v0_sys>; - - regulators { - vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <8>; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd2_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_cpu: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - ti,regulator-ext-sleep-control = <1>; - - nvidia,tegra-cpu-regulator; - }; - - vdd_1v8: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vcore_emmc: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <8>; - }; - - ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - ti,regulator-ext-sleep-control = <8>; - }; - }; - }; - - vdd_core: core-regulator@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,enable-vout-discharge; - ti,vsel0-state-high; - ti,vsel1-state-high; - - nvidia,tegra-core-regulator; - }; - }; - - vdd_3v3_sys: regulator-3v3 { - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pmc@7000e400 { - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x80>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi deleted file mode 100644 index c19a0419112a..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra30-asus-nexus7-grouper-common.dtsi" -#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" - -/ { - compatible = "asus,grouper", "nvidia,tegra30"; - - pinmux@70000868 { - state_default: pinmux { - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs2_n_pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_mosi_px0 { - nvidia,pins = "spi2_mosi_px0"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7", - "gmi_wait_pi7", - "gmi_cs4_n_pk2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - i2c@7000c500 { - nfc@28 { - compatible = "nxp,pn544-i2c"; - reg = <0x28>; - - interrupt-parent = <&gpio>; - interrupts = ; - - enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; - }; - }; - - display-panel { - panel-timing { - clock-frequency = <68000000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <24>; - hback-porch = <32>; - hsync-len = <24>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <32>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts deleted file mode 100644 index f1c63feb4af9..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" -#include "tegra30-asus-nexus7-tilapia.dtsi" - -/ { - model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi deleted file mode 100644 index 9169de34fa00..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" - -/ { - /* - * Tilapia's memory timings are pretty much the same as the Grouper's - * ones. There are few minor tunings made for a higher clock rates, - * these differentiating timings are overridden here for Tilapia. - */ - - memory-controller@7000f400 { - emc-timings-0 { - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x0000001f /* EMC_RC */ - 0x00000069 /* EMC_RFC */ - 0x00000017 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000c /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000011 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000b /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001412 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000e /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x00000016 /* EMC_RW2PDEN */ - 0x00000072 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000007 /* EMC_TCLKSTOP */ - 0x00001453 /* EMC_TREFBW */ - 0x0000000c /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf00b0191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008 /* EMC_DLL_XFORM_DQS0 */ - 0x00000008 /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x00000008 /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000c /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0156000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - - emc-timings-1 { - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < - 0x0000000f /* EMC_RC */ - 0x00000034 /* EMC_RFC */ - 0x0000000a /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x000009e9 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000039 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x0000000a /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000a2a /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x002600a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x00014000 /* EMC_DLL_XFORM_DQS4 */ - 0x00014000 /* EMC_DLL_XFORM_DQS5 */ - 0x00014000 /* EMC_DLL_XFORM_DQS6 */ - 0x00014000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x018b000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < - 0x00000020 /* EMC_RC */ - 0x0000006a /* EMC_RFC */ - 0x00000017 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000c /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000011 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001412 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000e /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x00000016 /* EMC_RW2PDEN */ - 0x00000072 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000007 /* EMC_TCLKSTOP */ - 0x00001453 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf00b0191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008 /* EMC_DLL_XFORM_DQS0 */ - 0x00000008 /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x00000008 /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0155000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi deleted file mode 100644 index 94c80134574e..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra30-asus-nexus7-grouper-common.dtsi" -#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi" - -/ { - compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; - - gpio@6000d000 { - init-mode-3g-hog { - gpio-hog; - gpios = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - output-low; - }; - }; - - pinmux@70000868 { - state_default: pinmux { - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs2_n_pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_mosi_px0 { - nvidia,pins = "spi2_mosi_px0"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7", - "gmi_wait_pi7", - "gmi_cs4_n_pk2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - i2c@7000c500 { - proximity-sensor@28 { - compatible = "microchip,cap1106"; - reg = <0x28>; - - /* - * Binding doesn't support specifying linux,input-type - * and this results in unwanted key-presses handled by - * applications, hence keep it disabled for now. - */ - status = "disabled"; - - interrupt-parent = <&gpio>; - interrupts = ; - - linux,keycodes = , - , - , - , - , - ; - }; - - nfc@2a { - compatible = "nxp,pn544-i2c"; - reg = <0x2a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; - }; - }; - - display-panel { - enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <81750000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <64>; - hback-porch = <128>; - hsync-len = <64>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts deleted file mode 100644 index 0406c5a69c12..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-tf201.dts +++ /dev/null @@ -1,644 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-transformer-common.dtsi" -#include "tegra30-asus-lvds-display.dtsi" - -/ { - model = "Asus Transformer Prime TF201"; - compatible = "asus,tf201", "nvidia,tegra30"; - - pinmux@70000868 { - state_default: pinmux { - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6", - "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006200 { - /* Azurewave AW-NH615 BCM4329B1 */ - bluetooth { - compatible = "brcm,bcm4329-bt"; - }; - }; - - i2c@7000c400 { - /* Atmel MXT768E touchscreen */ - touchscreen@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - - interrupt-parent = <&gpio>; - interrupts = ; - reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; - - vdda-supply = <&vdd_3v3_sys>; - vdd-supply = <&vdd_3v3_sys>; - }; - }; - - i2c@7000c500 { - clock-frequency = <100000>; - - magnetometer@e { - mount-matrix = "-1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; - }; - - gyroscope@68 { - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; - - /* External I2C interface */ - i2c-gate { - accelerometer@f { - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "1"; - }; - }; - }; - }; - - i2c@7000d000 { - /* Realtek ALC5631 audio codec */ - rt5631: audio-codec@1a { - compatible = "realtek,rt5631"; - reg = <0x1a>; - }; - }; - - memory-controller@7000f000 { - emc-timings-0 { - /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0x80000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x73e30303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0x80000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x72c30303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0x80000018 - 0x00000001 0x00000001 0x00000003 0x00000001 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060403 0x72430504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0x80000025 - 0x00000001 0x00000001 0x00000006 0x00000003 - 0x00000005 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000003 0x00000002 - 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emem-configuration = < 0x00000006 0x80000048 - 0x00000002 0x00000003 0x0000000c 0x00000007 - 0x00000009 0x00000001 0x00000002 0x00000006 - 0x00000001 0x00000000 0x00000004 0x00000004 - 0x04040001 0x000d090c 0x71c6120d 0x001f0000 >; - }; - }; - - emc-timings-1 { - /* TF201 Unknown 1GB LPDDR2 500MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0x80000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x73e30303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0x80000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x72c30303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0x80000018 - 0x00000001 0x00000001 0x00000003 0x00000001 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060403 0x72430504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0x80000025 - 0x00000001 0x00000001 0x00000006 0x00000003 - 0x00000005 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000003 0x00000002 - 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; - }; - - timing-500000000 { - clock-frequency = <500000000>; - - nvidia,emem-configuration = < 0x00000007 0x8000005a - 0x00000003 0x00000004 0x0000000e 0x00000009 - 0x0000000c 0x00000002 0x00000002 0x00000008 - 0x00000001 0x00000000 0x00000004 0x00000005 - 0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000003 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000060 0x00000000 0x00000018 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000004 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x0000006b 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x00780084 - 0x00008000 0x00098000 0x00098000 0x00098000 - 0x00098000 0x00000010 0x00000010 0x00000010 - 0x00000010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000008 0x00000008 0x00000008 - 0x00000008 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00000000 - 0x00000009 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000003 - 0x00000006 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x000000c0 0x00000000 0x00000030 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000008 0x00000008 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000000d5 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x00780084 - 0x00008000 0x00098000 0x00098000 0x00098000 - 0x00098000 0x00000010 0x00000010 0x00000010 - 0x00000010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000018 0x00000018 0x00000018 - 0x00000018 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00000000 - 0x00000009 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000000a>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000006 - 0x0000000d 0x00000004 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000181 0x00000000 0x00000060 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x0000000f 0x0000000f - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000001a9 0x00000004 0x00000006 - 0x00000000 0x00000000 0x00004282 0x00780084 - 0x00008000 0x000a0000 0x000a0000 0x000a0000 - 0x000a0000 0x00000010 0x00000010 0x00000010 - 0x00000010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000008 0x00000008 0x00000008 - 0x00000008 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00120220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00000000 - 0x0000000a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010042>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000013>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000c - 0x0000001a 0x00000008 0x00000003 0x00000005 - 0x00000004 0x00000001 0x00000006 0x00000003 - 0x00000003 0x00000002 0x00000002 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000c - 0x0000000a 0x00000303 0x00000000 0x000000c0 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000007 0x0000001d 0x0000001d - 0x00000004 0x0000000b 0x00000005 0x00000004 - 0x00000002 0x00000351 0x00000004 0x00000006 - 0x00000000 0x00000000 0x00004282 0x00440084 - 0x00008000 0x00074000 0x00074000 0x00074000 - 0x00074000 0x00000010 0x00000010 0x00000010 - 0x00000010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000018 0x00000018 0x00000018 - 0x00000018 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00078000 0x00078000 0x00078000 - 0x00078000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00000000 - 0x00000013 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010082>; - nvidia,emc-mode-2 = <0x00020004>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000024>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000017 - 0x00000033 0x00000010 0x00000007 0x00000007 - 0x00000007 0x00000002 0x0000000a 0x00000007 - 0x00000007 0x00000003 0x00000002 0x00000000 - 0x00000003 0x00000007 0x00000004 0x0000000d - 0x0000000e 0x000005e9 0x00000000 0x0000017a - 0x00000002 0x00000002 0x00000007 0x00000000 - 0x00000001 0x0000000c 0x00000038 0x00000038 - 0x00000006 0x00000014 0x00000009 0x00000004 - 0x00000002 0x00000680 0x00000000 0x00000006 - 0x00000000 0x00000000 0x00006282 0x001d0084 - 0x00008000 0x0002c000 0x0002c000 0x0002c000 - 0x0002c000 0x00000010 0x00000010 0x00000010 - 0x00000010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000008 0x00000008 0x00000008 - 0x00000008 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000c0220 0x0800003d 0x00000000 - 0x77ffc004 0x01f1f408 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00000000 - 0x00000024 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; - }; - }; - - emc-timings-1 { - /* TF201 Unknown 1GB LPDDR2 500MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000003 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x00000060 0x00000000 0x00000018 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000004 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x0000006b 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x00780084 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000000a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000003 - 0x00000006 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x000000c0 0x00000000 0x00000030 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000008 0x00000008 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000000d5 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x00780084 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000013 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000000a>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000006 - 0x0000000d 0x00000004 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x00000181 0x00000000 0x00000060 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x0000000f 0x0000000f - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000001a9 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x00780084 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000025 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010042>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000013>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000c - 0x0000001a 0x00000008 0x00000003 0x00000005 - 0x00000004 0x00000001 0x00000006 0x00000003 - 0x00000003 0x00000002 0x00000002 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000c - 0x0000000a 0x00000303 0x00000000 0x000000c0 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000007 0x0000001d 0x0000001d - 0x00000004 0x0000000b 0x00000005 0x00000004 - 0x00000002 0x00000351 0x00000004 0x00000006 - 0x00000000 0x00000000 0x00004282 0x00440084 - 0x00008000 0x00060000 0x00060000 0x00060000 - 0x00060000 0x00072000 0x00072000 0x00072000 - 0x00072000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000d0000 0x000d0000 0x000d0000 - 0x000d0000 0x000e0220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000004a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; - }; - - timing-500000000 { - clock-frequency = <500000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x000100c2>; - nvidia,emc-mode-2 = <0x00020005>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000002d>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001d - 0x00000040 0x00000014 0x00000008 0x00000007 - 0x00000009 0x00000003 0x0000000d 0x00000008 - 0x00000008 0x00000004 0x00000002 0x00000000 - 0x00000004 0x00000008 0x00000005 0x0000000d - 0x0000000f 0x00000763 0x00000000 0x000001d8 - 0x00000003 0x00000003 0x00000008 0x00000000 - 0x00000001 0x0000000e 0x00000046 0x00000046 - 0x00000008 0x00000019 0x0000000b 0x00000004 - 0x00000002 0x00000820 0x00000000 0x00000006 - 0x00000000 0x00000000 0x00006282 0xf0140091 - 0x00008000 0x00000008 0x00000008 0x00000008 - 0x00000008 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x00080220 0x0800003d 0x00000000 - 0x77ffc004 0x01f1f408 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x000000b4 0x000d000d 0xa0f10404 0x00000000 - 0x00000000 0x80000fde 0xe0000000 0xff00ff88 >; - }; - }; - }; - - usb-phy@7d000000 { - /delete-property/ nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ - }; - - usb-phy@7d008000 { - /delete-property/ nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ - }; - - display-panel { - compatible = "hannstar,hsd101pww2"; - }; - - haptic-feedback { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - vcc-supply = <&vdd_3v3_sys>; - }; - - opp-table-actmon { - /delete-node/ opp-533000000; - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; - }; - - opp-table-emc { - /delete-node/ opp-533000000-1200; - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; - }; - - sound { - compatible = "asus,tegra-audio-rt5631-tf201", - "nvidia,tegra-audio-rt5631"; - nvidia,model = "Asus Transformer Prime TF201 RT5631"; - - nvidia,audio-routing = - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR", - "Int Spk", "SPOL", - "Int Spk", "SPOR", - "MIC1", "MIC Bias1", - "MIC Bias1", "Mic Jack", - "DMIC", "Int Mic"; - - nvidia,audio-codec = <&rt5631>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts deleted file mode 100644 index 970a1f08dc8c..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-tf300t.dts +++ /dev/null @@ -1,1032 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-transformer-common.dtsi" -#include "tegra30-asus-lvds-display.dtsi" - -/ { - model = "Asus Transformer Pad TF300T"; - compatible = "asus,tf300t", "nvidia,tegra30"; - - gpio@6000d000 { - tf300t-init-hog { - gpio-hog; - gpios = ; - output-low; - }; - }; - - pinmux@70000868 { - state_default: pinmux { - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6", - "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006200 { - /* Azurewave AW-NH615 BCM4329B1 */ - bluetooth { - compatible = "brcm,bcm4329-bt"; - }; - }; - - i2c@7000c400 { - /* Elantech EKTH1036 touchscreen */ - touchscreen@10 { - compatible = "elan,ektf3624"; - reg = <0x10>; - - interrupt-parent = <&gpio>; - interrupts = ; - reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; - - vcc33-supply = <&vdd_3v3_sys>; - vccio-supply = <&vdd_3v3_sys>; - - touchscreen-size-x = <2240>; - touchscreen-size-y = <1408>; - touchscreen-inverted-y; - }; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - - magnetometer@e { - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "-1"; - }; - - gyroscope@68 { - mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - - /* External I2C interface */ - i2c-gate { - accelerometer@f { - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "1"; - }; - }; - }; - }; - - i2c@7000d000 { - /* Wolfson Microelectronics WM8903 audio codec */ - wm8903: audio-codec@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - - gpio-cfg = < - 0x00000600 /* DMIC_LR, output */ - 0x00000680 /* DMIC_DAT, input */ - 0x00000000 /* Speaker-enable GPIO, output, low */ - 0xffffffff /* don't touch */ - 0xffffffff /* don't touch */ - >; - - AVDD-supply = <&vdd_1v8_vio>; - CPVDD-supply = <&vdd_1v8_vio>; - DBVDD-supply = <&vdd_1v8_vio>; - DCVDD-supply = <&vdd_1v8_vio>; - }; - }; - - memory-controller@7000f000 { - emc-timings-0 { - /* Elpida 1GB 667MHZ */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00030003 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010003 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x73430303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x72830504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000006 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000003 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < 0x0000000a 0xc000003d - 0x00000001 0x00000002 0x00000008 0x00000004 - 0x00000004 0x00000001 0x00000002 0x00000007 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < 0x00000014 0xc0000079 - 0x00000003 0x00000004 0x00000010 0x0000000b - 0x0000000a 0x00000001 0x00000003 0x0000000b - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; - }; - }; - - emc-timings-1 { - /* Hynix 1GB 667MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00030003 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010003 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x73430303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x72830504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000006 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000003 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0605 0x72440a06 0x001f0000 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < 0x0000000a 0xc000003d - 0x00000001 0x00000002 0x00000008 0x00000005 - 0x00000004 0x00000001 0x00000002 0x00000007 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < 0x00000014 0xc0000079 - 0x00000003 0x00000004 0x00000011 0x0000000b - 0x0000000a 0x00000001 0x00000003 0x0000000b - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00140b11 0x70ea1f12 0x001f0000 >; - }; - }; - - emc-timings-2 { - /* Micron 1GB 667MHZ */ - nvidia,ram-code = <2>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x73430303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x72830504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000003 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < 0x00000005 0xc000003d - 0x00000001 0x00000002 0x00000008 0x00000004 - 0x00000004 0x00000001 0x00000002 0x00000007 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < 0x0000000a 0xc0000079 - 0x00000003 0x00000004 0x00000010 0x0000000a - 0x0000000a 0x00000001 0x00000003 0x0000000b - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00140b10 0x70ea1f11 0x001f0000 >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - /* Elpida 1GB 667MHZ */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000004 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x00000008 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000009 0x00000009 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000004 - 0x00000010 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000012 0x00000012 - 0x00000004 0x00000004 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000a - 0x00000020 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000023 0x00000023 - 0x00000004 0x00000007 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000006 0x00000006 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x0000000f - 0x00000034 0x0000000a 0x00000003 0x00000003 - 0x00000008 0x00000002 0x00000009 0x00000003 - 0x00000003 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x000009e9 0x00000000 0x0000027a - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000007 0x0000000e 0x00000039 0x00000200 - 0x00000004 0x0000000a 0x00000000 0x00000004 - 0x00000005 0x00000a2a 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x002600a4 - 0x00008000 0x0003c000 0x0003c000 0x0003c000 - 0x0003c000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000002a0 0x0800013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x018b000c 0xa0f10000 0x00000000 - 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001f - 0x00000069 0x00000017 0x00000007 0x00000005 - 0x0000000c 0x00000003 0x00000011 0x00000007 - 0x00000007 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000a 0x00000009 0x0000000a - 0x00000011 0x00001412 0x00000000 0x00000504 - 0x00000002 0x0000000e 0x00000001 0x00000000 - 0x0000000c 0x00000016 0x00000072 0x00000200 - 0x00000005 0x00000015 0x00000000 0x00000006 - 0x00000007 0x00001453 0x0000000b 0x00000006 - 0x00000000 0x00000000 0x00005088 0xf00b0191 - 0x00008000 0x00000008 0x00000008 0x00000008 - 0x00000008 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x000002a0 0x0800013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x0f000021 0x00000802 0x00020000 - 0x00000100 0x0156000c 0xa0f10000 0x00000000 - 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; - }; - }; - - emc-timings-1 { - /* Hynix 1GB 667MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000004 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x00000008 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000009 0x00000009 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000005 - 0x00000010 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000012 0x00000012 - 0x00000004 0x00000004 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000a - 0x00000020 0x00000007 0x00000003 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000023 0x00000023 - 0x00000004 0x00000007 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000006 0x00000006 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x0000000f - 0x00000034 0x0000000b 0x00000003 0x00000003 - 0x00000008 0x00000002 0x00000009 0x00000003 - 0x00000003 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x000009e9 0x00000000 0x0000027a - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000007 0x0000000e 0x00000039 0x00000200 - 0x00000004 0x0000000a 0x00000000 0x00000004 - 0x00000005 0x00000a2a 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x002600a4 - 0x00008000 0x0003c000 0x0003c000 0x0003c000 - 0x0003c000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000002a0 0x0800013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x018b000c 0xa0f10000 0x00000000 - 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000020 - 0x0000006a 0x00000018 0x00000008 0x00000005 - 0x0000000c 0x00000003 0x00000011 0x00000007 - 0x00000007 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000a 0x00000009 0x0000000a - 0x00000011 0x00001412 0x00000000 0x00000504 - 0x00000002 0x0000000e 0x00000001 0x00000000 - 0x0000000c 0x00000016 0x00000072 0x00000200 - 0x00000005 0x00000015 0x00000000 0x00000006 - 0x00000007 0x00001453 0x0000000b 0x00000006 - 0x00000000 0x00000000 0x00005088 0xf00b0191 - 0x00008000 0x00000008 0x00000008 0x00000008 - 0x00000008 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x000002a0 0x0800013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x0155000c 0xa0f10000 0x00000000 - 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; - }; - }; - - emc-timings-2 { - /* Micron 1GB 667MHZ */ - nvidia,ram-code = <2>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000004 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x00000008 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x00000009 - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000009 0x00000009 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000004 - 0x00000010 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000012 0x00000012 - 0x00000004 0x00000004 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xd8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000009 - 0x00000020 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000023 0x00000023 - 0x00000004 0x00000007 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000006 0x00000006 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xd8000000 0xff00ff00 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200040>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x0000000f - 0x00000034 0x0000000a 0x00000003 0x00000003 - 0x00000008 0x00000002 0x00000009 0x00000003 - 0x00000003 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x000009e9 0x00000000 0x0000027a - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000007 0x0000000e 0x00000039 0x00000200 - 0x00000004 0x0000000a 0x00000000 0x00000004 - 0x00000005 0x00000a2a 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x002600a4 - 0x00008000 0x0003c000 0x0003c000 0x0003c000 - 0x0003c000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000002a0 0x0800013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x018b000c 0xa0f10000 0x00000000 - 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200058>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001f - 0x00000069 0x00000016 0x00000007 0x00000005 - 0x0000000c 0x00000003 0x00000011 0x00000008 - 0x00000008 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000a 0x00000009 0x0000000b - 0x00000011 0x00001412 0x00000000 0x00000504 - 0x00000002 0x0000000e 0x00000001 0x00000000 - 0x0000000c 0x00000016 0x00000072 0x00000200 - 0x00000005 0x00000015 0x00000000 0x00000006 - 0x00000007 0x00001453 0x0000000b 0x00000006 - 0x00000000 0x00000000 0x00005088 0xf00b0191 - 0x00008000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x000002a0 0x0800013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x0156000c 0xa0f10000 0x00000000 - 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >; - }; - }; - }; - - display-panel { - compatible = "innolux,g101ice-l01"; - }; - - opp-table-emc { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; - }; - - opp-table-actmon { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; - }; - - sound { - compatible = "asus,tegra-audio-wm8903-tf300t", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Asus Transformer Pad TF300T WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "IN2L", "Mic Jack", - "DMICDAT", "Int Mic"; - - nvidia,audio-codec = <&wm8903>; - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts deleted file mode 100644 index 4861db8e1e59..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts +++ /dev/null @@ -1,1104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-transformer-common.dtsi" -#include "tegra30-asus-lvds-display.dtsi" - -/ { - model = "Asus Transformer Pad 3G TF300TG"; - compatible = "asus,tf300tg", "nvidia,tegra30"; - - gpio@6000d000 { - tf300tg-init-hog { - gpio-hog; - gpios = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - output-low; - }; - }; - - pinmux@70000868 { - state_default: pinmux { - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6", - "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_cs2_n_pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi2"; - nvidia,tristate = ; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_mosi_px0 { - nvidia,pins = "spi2_mosi_px0"; - nvidia,function = "spi2"; - }; - - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006200 { - /* Azurewave AW-NH615 BCM4329B1 */ - bluetooth { - compatible = "brcm,bcm4329-bt"; - }; - }; - - i2c@7000c400 { - /* Elantech EKTH1036 touchscreen */ - touchscreen@10 { - compatible = "elan,ektf3624"; - reg = <0x10>; - - interrupt-parent = <&gpio>; - interrupts = ; - reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; - - vcc33-supply = <&vdd_3v3_sys>; - vccio-supply = <&vdd_3v3_sys>; - - touchscreen-size-x = <2240>; - touchscreen-size-y = <1408>; - touchscreen-inverted-y; - }; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - - magnetometer@e { - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; - }; - - gyroscope@68 { - mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - - /* External I2C interface */ - i2c-gate { - accelerometer@f { - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "1"; - }; - }; - }; - }; - - i2c@7000d000 { - /* Realtek ALC5631 audio codec */ - rt5631: audio-codec@1a { - compatible = "realtek,rt5631"; - reg = <0x1a>; - }; - }; - - memory-controller@7000f000 { - emc-timings-0 { - /* Elpida 1GB 667MHZ */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x73430303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x72830504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000003 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < 0x00000005 0xc000003d - 0x00000001 0x00000002 0x00000008 0x00000004 - 0x00000004 0x00000001 0x00000002 0x00000007 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < 0x0000000a 0xc0000079 - 0x00000003 0x00000004 0x00000010 0x0000000b - 0x0000000a 0x00000001 0x00000003 0x0000000b - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; - }; - }; - - emc-timings-1 { - /* Hynix 1GB 667MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x73430303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x72830504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000003 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < 0x00000005 0xc000003d - 0x00000001 0x00000002 0x00000008 0x00000004 - 0x00000004 0x00000001 0x00000002 0x00000007 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < 0x0000000a 0xc0000079 - 0x00000003 0x00000004 0x00000010 0x0000000b - 0x0000000a 0x00000001 0x00000003 0x0000000b - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; - }; - }; - - emc-timings-2 { - /* Micron 1GB 667MHZ */ - nvidia,ram-code = <2>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x73430303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x72830504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000003 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emem-configuration = < 0x00000005 0x8000003d - 0x00000001 0x00000002 0x00000008 0x00000004 - 0x00000004 0x00000001 0x00000002 0x00000007 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emem-configuration = < 0x0000000a 0x80000079 - 0x00000003 0x00000004 0x00000010 0x0000000a - 0x0000000a 0x00000001 0x00000003 0x0000000b - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - /* Elpida 1GB 667MHZ */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000004 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x00000008 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000009 0x00000009 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000005 - 0x00000010 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000012 0x00000012 - 0x00000004 0x00000004 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000a - 0x00000020 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000006 0x00000004 0x0000000a - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000023 0x00000023 - 0x00000004 0x00000007 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000007 0x00000004 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200040>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x0000000f - 0x00000034 0x0000000a 0x00000003 0x00000003 - 0x00000008 0x00000002 0x00000009 0x00000003 - 0x00000003 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x000009e9 0x00000000 0x0000027a - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000007 0x0000000e 0x00000039 0x00000200 - 0x00000004 0x0000000a 0x00000000 0x00000004 - 0x00000005 0x00000a2a 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x002600a4 - 0x00008000 0x0003c000 0x0003c000 0x0003c000 - 0x0003c000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00050000 0x00050000 0x00050000 - 0x00050000 0x000002a0 0x0800013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x018b000c 0xa0f10000 0x00000000 - 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200058>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001f - 0x00000069 0x00000017 0x00000007 0x00000005 - 0x0000000c 0x00000003 0x00000011 0x00000007 - 0x00000007 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000b 0x00000009 0x0000000b - 0x00000011 0x00001412 0x00000000 0x00000504 - 0x00000002 0x0000000e 0x00000001 0x00000000 - 0x0000000c 0x00000016 0x00000072 0x00000200 - 0x00000005 0x00000015 0x00000000 0x00000006 - 0x00000007 0x00001453 0x0000000c 0x00000004 - 0x00000000 0x00000000 0x00005088 0xf00b0191 - 0x00008000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00018000 0x00018000 0x00018000 - 0x00018000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x000002a0 0x0a00013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x0a000021 0x00000802 0x00020000 - 0x00000100 0x0156000c 0xa0f10000 0x00000000 - 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; - }; - }; - - emc-timings-1 { - /* Hynix 1GB 667MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000004 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x00000008 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000009 0x00000009 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000005 - 0x00000010 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000012 0x00000012 - 0x00000004 0x00000004 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200048>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000a - 0x00000020 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000006 0x00000004 0x0000000a - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000023 0x00000023 - 0x00000004 0x00000007 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000007 0x00000004 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200040>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x0000000f - 0x00000034 0x0000000a 0x00000003 0x00000003 - 0x00000008 0x00000002 0x00000009 0x00000003 - 0x00000003 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x000009e9 0x00000000 0x0000027a - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000007 0x0000000e 0x00000039 0x00000200 - 0x00000004 0x0000000a 0x00000000 0x00000004 - 0x00000005 0x00000a2a 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x002600a4 - 0x00008000 0x0003c000 0x0003c000 0x0003c000 - 0x0003c000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000002a0 0x0800013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x018b000c 0xa0f10000 0x00000000 - 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200058>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000020 - 0x00000069 0x00000017 0x00000007 0x00000005 - 0x0000000c 0x00000003 0x00000011 0x00000007 - 0x00000007 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000b 0x00000009 0x0000000b - 0x00000011 0x00001412 0x00000000 0x00000504 - 0x00000002 0x0000000e 0x00000001 0x00000000 - 0x0000000c 0x00000016 0x00000072 0x00000200 - 0x00000005 0x00000015 0x00000000 0x00000006 - 0x00000007 0x00001453 0x0000000c 0x00000004 - 0x00000000 0x00000000 0x00005088 0xf00b0191 - 0x00008000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00018000 0x00018000 0x00018000 - 0x00018000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x000002a0 0x0800013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x0156000c 0xa0f10000 0x00000000 - 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; - }; - }; - - emc-timings-2 { - /* Micron 1GB 667MHZ */ - nvidia,ram-code = <2>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000004 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x00000008 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000009 0x00000009 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000004 - 0x00000010 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000012 0x00000012 - 0x00000004 0x00000004 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000009 - 0x00000020 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000006 0x00000004 0x0000000a - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000023 0x00000023 - 0x00000004 0x00000007 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000007 0x00000004 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-333500000 { - clock-frequency = <333500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x0000000f - 0x00000034 0x0000000a 0x00000003 0x00000003 - 0x00000008 0x00000002 0x00000009 0x00000003 - 0x00000003 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x000009e9 0x00000000 0x0000027a - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000007 0x0000000e 0x00000039 0x00000200 - 0x00000004 0x0000000a 0x00000000 0x00000004 - 0x00000005 0x00000a2a 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x002600a4 - 0x00008000 0x0003c000 0x0003c000 0x0003c000 - 0x0003c000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00040000 0x00040000 0x00040000 - 0x00040000 0x000002a0 0x0800013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x018b000c 0xa0f10000 0x00000000 - 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; - }; - - timing-667000000 { - clock-frequency = <667000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000b71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001f - 0x00000069 0x00000016 0x00000007 0x00000005 - 0x0000000c 0x00000003 0x00000011 0x00000007 - 0x00000007 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000b 0x00000009 0x0000000b - 0x00000011 0x00001412 0x00000000 0x00000504 - 0x00000002 0x0000000e 0x00000001 0x00000000 - 0x0000000c 0x00000016 0x00000072 0x00000200 - 0x00000005 0x00000015 0x00000000 0x00000006 - 0x00000007 0x00001453 0x0000000c 0x00000004 - 0x00000000 0x00000000 0x00005088 0xf00b0191 - 0x00008000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x000002a0 0x0600013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x0156000c 0xa0f10000 0x00000000 - 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; - }; - }; - }; - - display-panel { - compatible = "innolux,g101ice-l01"; - }; - - opp-table-emc { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; - }; - - opp-table-actmon { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; - }; - - sound { - compatible = "asus,tegra-audio-rt5631-tf300tg", - "nvidia,tegra-audio-rt5631"; - nvidia,model = "Asus Transformer Pad TF300TG RT5631"; - - nvidia,audio-routing = - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR", - "Int Spk", "SPOL", - "Int Spk", "SPOR", - "MIC1", "MIC Bias1", - "MIC Bias1", "Mic Jack", - "DMIC", "Int Mic"; - - nvidia,audio-codec = <&rt5631>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts deleted file mode 100644 index efde7dad718a..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ /dev/null @@ -1,840 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-asus-transformer-common.dtsi" - -/ { - model = "Asus Transformer Infinity TF700T"; - compatible = "asus,tf700t", "nvidia,tegra30"; - - host1x@50000000 { - lcd: dc@54200000 { - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; - - rgb { - status = "okay"; - - port@0 { - dpi_output: endpoint { - remote-endpoint = <&bridge_input>; - bus-width = <24>; - }; - }; - }; - }; - }; - - pinmux@70000868 { - state_default: pinmux { - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6", - "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_mosi_px0 { - nvidia,pins = "spi2_mosi_px0"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006200 { - /* Azurewave AW-NH665 BCM4330B1 */ - bluetooth { - compatible = "brcm,bcm4330-bt"; - }; - }; - - i2c@7000c400 { - /* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */ - touchscreen@10 { - compatible = "elan,ektf3624"; - reg = <0x10>; - - interrupt-parent = <&gpio>; - interrupts = ; - reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; - - vcc33-supply = <&vdd_3v3_sys>; - vccio-supply = <&vdd_3v3_sys>; - - touchscreen-size-x = <2944>; - touchscreen-size-y = <1856>; - touchscreen-inverted-y; - }; - }; - - i2c@7000c500 { - clock-frequency = <100000>; - - magnetometer@e { - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; - }; - - gyroscope@68 { - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; - - /* External I2C interface */ - i2c-gate { - accelerometer@f { - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "1"; - }; - }; - }; - }; - - i2c@7000d000 { - /* Realtek ALC5631 audio codec */ - rt5631: audio-codec@1a { - compatible = "realtek,rt5631"; - reg = <0x1a>; - }; - }; - - memory-controller@7000f000 { - emc-timings-0 { - /* Micron 1GB 800MHZ */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x75830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74630303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000002 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000004 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emem-configuration = < 0x00000006 0xc0000048 - 0x00000001 0x00000002 0x00000009 0x00000005 - 0x00000007 0x00000001 0x00000002 0x00000008 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - - nvidia,emem-configuration = < 0x0000000c 0xc0000090 - 0x00000004 0x00000005 0x00000013 0x0000000c - 0x0000000f 0x00000002 0x00000003 0x0000000c - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; - }; - }; - - emc-timings-1 { - /* Elpida 1GB 800MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x75830303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000020 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0502 0x74630303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000030 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000002 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000005 0x00000002 - 0x00000004 0x00000001 0x00000003 0x00000008 - 0x00000002 0x00000001 0x00000002 0x00000006 - 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emem-configuration = < 0x00000006 0xc0000048 - 0x00000001 0x00000002 0x00000009 0x00000005 - 0x00000007 0x00000001 0x00000002 0x00000008 - 0x00000002 0x00000002 0x00000003 0x00000006 - 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - - nvidia,emem-configuration = < 0x0000000c 0xc0000090 - 0x00000004 0x00000005 0x00000013 0x0000000c - 0x0000000f 0x00000002 0x00000003 0x0000000c - 0x00000002 0x00000002 0x00000004 0x00000008 - 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - /* Micron 1GB 800MHZ */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000006 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000007 0x00000007 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x0000000d 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x0000000e 0x0000000e - 0x00000004 0x00000003 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000004 - 0x0000001a 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x0000001c 0x0000001c - 0x00000004 0x00000005 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000009 - 0x00000035 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000006 0x00000004 0x0000000a - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000038 0x00000038 - 0x00000004 0x00000009 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000007 0x00000004 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x00000012 - 0x00000066 0x0000000c 0x00000004 0x00000003 - 0x00000008 0x00000002 0x0000000a 0x00000004 - 0x00000004 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x00000bf0 0x00000000 0x000002fc - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000008 0x0000000f 0x0000006c 0x00000200 - 0x00000004 0x00000010 0x00000000 0x00000004 - 0x00000005 0x00000c30 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x001d0084 - 0x00008000 0x00044000 0x00044000 0x00044000 - 0x00044000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000002a0 0x0600013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x0158000c 0xa0f10000 0x00000000 - 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000025 - 0x000000ce 0x0000001a 0x00000009 0x00000005 - 0x0000000d 0x00000004 0x00000013 0x00000009 - 0x00000009 0x00000004 0x00000001 0x00000000 - 0x00000007 0x0000000a 0x00000009 0x0000000a - 0x00000011 0x00001820 0x00000000 0x00000608 - 0x00000003 0x00000012 0x00000001 0x00000000 - 0x0000000f 0x00000018 0x000000d8 0x00000200 - 0x00000005 0x00000020 0x00000000 0x00000007 - 0x00000008 0x00001860 0x0000000b 0x00000006 - 0x00000000 0x00000000 0x00005088 0xf0070191 - 0x00008000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00018000 0x00018000 0x00018000 - 0x00018000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x000002a0 0x0800013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x00f0000c 0xa0f10000 0x00000000 - 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; - }; - }; - - emc-timings-1 { - /* Elpida 1GB 800MHZ */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000006 0x00000000 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x000000c0 0x00000000 0x00000030 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000007 0x00000007 - 0x00000004 0x00000002 0x00000000 0x00000004 - 0x00000005 0x000000c7 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000002 - 0x0000000d 0x00000001 0x00000000 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000000 - 0x00000000 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000181 0x00000000 0x00000060 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x0000000e 0x0000000e - 0x00000004 0x00000003 0x00000000 0x00000004 - 0x00000005 0x0000018e 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000004 - 0x0000001a 0x00000003 0x00000001 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000001 - 0x00000001 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000005 0x00000004 0x0000000a - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x0000001c 0x0000001c - 0x00000004 0x00000005 0x00000000 0x00000004 - 0x00000005 0x0000031c 0x00000006 0x00000004 - 0x00000000 0x00000000 0x00004288 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00000000 - 0x00000040 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000009 - 0x00000035 0x00000007 0x00000002 0x00000002 - 0x0000000a 0x00000005 0x0000000b 0x00000002 - 0x00000002 0x00000003 0x00000001 0x00000000 - 0x00000005 0x00000006 0x00000004 0x0000000a - 0x0000000b 0x00000607 0x00000000 0x00000181 - 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000007 0x0000000f 0x00000038 0x00000038 - 0x00000004 0x00000009 0x00000000 0x00000004 - 0x00000005 0x00000638 0x00000007 0x00000004 - 0x00000000 0x00000000 0x00004288 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000002a0 0x0800211c 0x00000000 - 0x77fff884 0x01f1f108 0x05057404 0x54000007 - 0x08000168 0x08000000 0x00000802 0x00020000 - 0x00000100 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - - nvidia,emc-configuration = < 0x00000012 - 0x00000066 0x0000000c 0x00000004 0x00000003 - 0x00000008 0x00000002 0x0000000a 0x00000004 - 0x00000004 0x00000002 0x00000001 0x00000000 - 0x00000004 0x00000006 0x00000004 0x0000000a - 0x0000000c 0x00000bf0 0x00000000 0x000002fc - 0x00000001 0x00000008 0x00000001 0x00000000 - 0x00000008 0x0000000f 0x0000006c 0x00000200 - 0x00000004 0x00000010 0x00000000 0x00000004 - 0x00000005 0x00000c30 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00007088 0x001d0084 - 0x00008000 0x00044000 0x00044000 0x00044000 - 0x00044000 0x00014000 0x00014000 0x00014000 - 0x00014000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x000002a0 0x0600013d 0x00000000 - 0x77fff884 0x01f1f508 0x05057404 0x54000007 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x0158000c 0xa0f10000 0x00000000 - 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000025 - 0x000000ce 0x0000001a 0x00000009 0x00000005 - 0x0000000d 0x00000004 0x00000013 0x00000009 - 0x00000009 0x00000004 0x00000001 0x00000000 - 0x00000007 0x0000000a 0x00000009 0x0000000a - 0x00000011 0x00001820 0x00000000 0x00000608 - 0x00000003 0x00000012 0x00000001 0x00000000 - 0x0000000f 0x00000018 0x000000d8 0x00000200 - 0x00000005 0x00000020 0x00000000 0x00000007 - 0x00000008 0x00001860 0x0000000b 0x00000006 - 0x00000000 0x00000000 0x00005088 0xf0070191 - 0x00008000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00018000 0x00018000 0x00018000 - 0x00018000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x000002a0 0x0a00013d 0x22220000 - 0x77fff884 0x01f1f501 0x07077404 0x54000000 - 0x080001e8 0x08000021 0x00000802 0x00020000 - 0x00000100 0x00f0000c 0xa0f10000 0x00000000 - 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; - }; - }; - }; - - tc358768_refclk: clock-tc358768 { - compatible = "fixed-clock"; - clock-frequency = <23100000>; - clock-accuracy = <100>; - #clock-cells = <0>; - }; - - tc358768_osc: clock-tc358768-osc-gate { - compatible = "gpio-gate-clock"; - enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; - clocks = <&tc358768_refclk>; - #clock-cells = <0>; - }; - - haptic-feedback { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - vcc-supply = <&vdd_3v3_sys>; - }; - - i2c-mux { - compatible = "i2c-mux-gpio"; - - mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; - i2c-parent = <&lcd_ddc>; - idle-state = <0x0>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dsi@7 { - compatible = "toshiba,tc358768"; - reg = <0x7>; - - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&tc358768_osc>; - clock-names = "refclk"; - - reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; - - vddc-supply = <&vdd_1v2_mipi>; - vddio-supply = <&vdd_1v8_vio>; - vddmipi-supply = <&vdd_1v2_mipi>; - - /* - * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 - * LCD SuperIPS+ Full HD panel. - */ - panel@1 { - compatible = "panasonic,vvx10f004b00"; - reg = <1>; - - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&bridge_output>; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_input: endpoint { - remote-endpoint = <&dpi_output>; - data-lines = <24>; - }; - }; - - port@1 { - reg = <1>; - - bridge_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - }; - }; - - opp-table-actmon { - /delete-node/ opp-900000000; - }; - - opp-table-emc { - /delete-node/ opp-900000000-1350; - }; - - vdd_1v2_mipi: regulator-mipi { - compatible = "regulator-fixed"; - regulator-name = "tc358768_1v2_vdd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <10000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - sound { - compatible = "asus,tegra-audio-rt5631-tf700t", - "nvidia,tegra-audio-rt5631"; - nvidia,model = "Asus Transformer Infinity TF700T RT5631"; - - nvidia,audio-routing = - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR", - "Int Spk", "SPOL", - "Int Spk", "SPOR", - "MIC1", "MIC Bias1", - "MIC Bias1", "Mic Jack", - "DMIC", "Int Mic"; - - nvidia,audio-codec = <&rt5631>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi deleted file mode 100644 index bdb898ad6262..000000000000 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ /dev/null @@ -1,1788 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include - -#include "tegra30.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" - -/ { - chassis-type = "convertible"; - - aliases { - mmc0 = "/mmc@78000600"; /* eMMC */ - mmc1 = "/mmc@78000000"; /* uSD slot */ - mmc2 = "/mmc@78000400"; /* WiFi */ - - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - - display0 = &lcd; - display1 = &hdmi; - - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma@80000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x80000000 0x30000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - - ramoops@beb00000 { - compatible = "ramoops"; - reg = <0xbeb00000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - trustzone@bfe00000 { - reg = <0xbfe00000 0x200000>; /* 2MB */ - no-map; - }; - }; - - host1x@50000000 { - hdmi: hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&hdmi_5v0_sys>; - pll-supply = <&vdd_1v8_vio>; - vdd-supply = <&vdd_3v3_sys>; - - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - }; - }; - - gpio@6000d000 { - init-lpm-in-hog { - gpio-hog; - gpios = , - ; - input; - }; - - init-lpm-out-hog { - gpio-hog; - gpios = , - ; - output-low; - }; - - usb-charge-limit-hog { - gpio-hog; - gpios = ; - output-high; - }; - }; - - vde@6001a000 { - assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; - assigned-clock-rates = <408000000>; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* SDMMC1 pinmux */ - sdmmc1_clk { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_cmd { - nvidia,pins = "sdmmc1_dat3_py4", - "sdmmc1_dat2_py5", - "sdmmc1_dat1_py6", - "sdmmc1_dat0_py7", - "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_cd { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_wp { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SDMMC2 pinmux */ - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d5_pl3", - "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6", - "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - /* SDMMC3 pinmux */ - sdmmc3_clk { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_cmd { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SDMMC4 pinmux */ - sdmmc4_clk { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc4_cmd { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc4_rst_n { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - cam_mclk { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdmmc4 { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - /* I2C pinmux */ - gen1_i2c { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - gen2_i2c { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - cam_i2c { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - ddc_i2c { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - }; - - pwr_i2c { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - hotplug_i2c { - nvidia,pins = "pu4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* HDMI pinmux */ - hdmi_cec { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - hdmi_hpd { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-A */ - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-B */ - uartb_txd_rts { - nvidia,pins = "uart2_txd_pc2", - "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uartb_rxd_cts { - nvidia,pins = "uart2_rxd_pc3", - "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-C */ - uartc_rxd_cts { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uartc_txd_rts { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-D */ - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* I2S pinmux */ - dap_i2s0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap_i2s1 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_fs { - nvidia,pins = "dap3_fs_pp0", - "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_dout { - nvidia,pins = "dap3_dout_pp2", - "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap_i2s3 { - nvidia,pins = "dap4_fs_pp4", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Sensors pinmux */ - nct_irq { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Asus EC pinmux */ - ec_irqs { - nvidia,pins = "kb_row10_ps2", - "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ec_reqs { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Memory type bootstrap */ - mem_boostraps { - nvidia,pins = "gmi_ad4_pg4", - "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PCI-e pinmux */ - pex_l2_rst_n { - nvidia,pins = "pex_l2_rst_n_pcc6", - "pex_l0_rst_n_pdd1", - "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l2_clkreq_n { - nvidia,pins = "pex_l2_clkreq_n_pcc7", - "pex_l0_prsnt_n_pdd0", - "pex_l0_clkreq_n_pdd2", - "pex_wake_n_pdd3", - "pex_l1_prsnt_n_pdd4", - "pex_l1_clkreq_n_pdd6", - "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SPI pinmux */ - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4", - "spi1_sck_px5", - "spi1_cs0_n_px6", - "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - hp_detect { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - mic_detect { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Display A pinmux */ - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pclk_pb3", - "lcd_pwr1_pc1", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_vsync_pj4", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_dc0_pn6", - "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4", - "lcd_sdout_pn5", - "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - blink { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* KBC keys */ - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_row1_pr1", - "kb_row3_pr3", - "kb_row8_ps0", - "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4", - "kb_col5_pq5", - "kb_col7_pq7", - "kb_row2_pr2", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row12_ps4", - "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7", - "gmi_wait_pi7", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - /* GPIO keys pinmux */ - power_key { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vol_keys { - nvidia,pins = "kb_col2_pq2", - "kb_col3_pq3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Bluetooth */ - bt_shutdown { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - bt_dev_wake { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - bt_host_wake { - nvidia,pins = "pu6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6", - "vi_hsync_pd7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2", - "vi_d0_pt4", "pbb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_wr_n_pi0", - "gmi_oe_n_pi1", - "gmi_dqs_pi2", - "gmi_adv_n_pk0", - "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4", - "gmi_rst_n_pi4", - "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Vibrator control */ - vibrator { - nvidia,pins = "gmi_ad15_ph7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PWM pimnmux */ - pwm_0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pwm_2 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Spdif pinmux */ - spdif_out { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spdif_in { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - jtag_rtck { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk1_out { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk2_out { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_out { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sys_clk_req { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5", - "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO power/drive control */ - drive_dap1 { - nvidia,pins = "drive_dap1", - "drive_dap2", - "drive_dbg", - "drive_at5", - "drive_gme", - "drive_ddc", - "drive_ao1", - "drive_uart3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1", - "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - /* Broadcom GPS BCM47511 */ - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>, - <1000000 4000000 136>; - - bluetooth { - max-speed = <4000000>; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - - vbat-supply = <&vdd_3v3_com>; - vddio-supply = <&vdd_1v8_vio>; - }; - }; - - pwm@7000a000 { - status = "okay"; - }; - - lcd_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000c500 { - status = "okay"; - - /* Aichi AMI306 digital compass */ - magnetometer@e { - compatible = "asahi-kasei,ak8974"; - reg = <0x0e>; - - avdd-supply = <&vdd_3v3_sys>; - dvdd-supply = <&vdd_1v8_vio>; - }; - - /* Dynaimage ambient light sensor */ - light-sensor@1c { - compatible = "dynaimage,al3010"; - reg = <0x1c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - }; - - gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - vlogic-supply = <&vdd_1v8_vio>; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - accelerometer@f { - compatible = "kionix,kxtf9"; - reg = <0x0f>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_1v8_vio>; - vddio-supply = <&vdd_1v8_vio>; - }; - }; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <93750>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* Texas Instruments TPS659110 PMIC */ - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; - ti,system-power-controller; - ti,sleep-keep-ck32k; - ti,sleep-enable; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v0_bat>; - vcc2-supply = <&vdd_5v0_bat>; - vcc3-supply = <&vdd_1v8_vio>; - vcc4-supply = <&vdd_5v0_sys>; - vcc5-supply = <&vdd_5v0_bat>; - vcc6-supply = <&vdd_3v3_sys>; - vcc7-supply = <&vdd_5v0_bat>; - vccio-supply = <&vdd_5v0_bat>; - - pmic-sleep-hog { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - }; - - regulators { - /* VDD1 is not used by Transformers */ - - vddio_ddr: vdd2 { - regulator-name = "vddio_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_cpu: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <1>; - - nvidia,tegra-cpu-regulator; - }; - - vdd_1v8_vio: vio { - regulator-name = "vdd_1v8_gen"; - /* FIXME: eMMC won't work, if set to 1.8 V */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* eMMC VDD */ - vcore_emmc: ldo1 { - regulator-name = "vdd_emmc_core"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* uSD slot VDD */ - vdd_usd: ldo2 { - regulator-name = "vdd_usd"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - /* FIXME: Without this, voltage switching fails */ - regulator-always-on; - }; - - /* uSD slot VDDIO */ - vddio_usd: ldo3 { - regulator-name = "vddio_usd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3100000>; - }; - - ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* LDO5 is not used by Transformers */ - - ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <8>; - }; - - ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - ti,regulator-ext-sleep-control = <8>; - }; - }; - }; - - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - - vdd_core: core-regulator@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1770000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,enable-vout-discharge; - ti,vsel0-state-high; - ti,vsel1-state-high; - - nvidia,tegra-core-regulator; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - /* FIXME: LP1 doesn't work at the moment */ - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - - /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x81>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080400 { /* i2s1 */ - status = "okay"; - }; - - /* BT SCO */ - i2s@70080600 { /* i2s3 */ - status = "okay"; - }; - }; - - mmc@78000000 { - status = "okay"; - - /* FIXME: Full 208Mhz clock rate doesn't work reliably */ - max-frequency = <104000000>; - - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - bus-width = <4>; - - vmmc-supply = <&vdd_usd>; /* ldo2 */ - vqmmc-supply = <&vddio_usd>; /* ldo3 */ - }; - - mmc@78000400 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; - assigned-clock-rates = <50000000>; - - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_com>; - vqmmc-supply = <&vdd_1v8_vio>; - - /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */ - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - mmc@78000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_1v8_vio>; - mmc-ddr-3_3v; - non-removable; - }; - - /* USB via ASUS connector */ - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,hssync-start-delay = <0>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; - - /* Dock's USB port */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_5v0_bat>; - }; - - mains: ac-adapter-detect { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_5v0_bl>; - pwms = <&pwm 0 4000000>; - - brightness-levels = <1 255>; - num-interpolated-steps = <254>; - default-brightness-level = <40>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - cpu2: cpu@2 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - cpu3: cpu@3 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - extcon-keys { - compatible = "gpio-keys"; - - switch-dock-hall-sensor { - label = "Lid sensor"; - gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - - switch-lineout-detect { - label = "Audio dock line-out detect"; - gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - vdd_5v0_bat: regulator-bat { - compatible = "regulator-fixed"; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_cp: regulator-sby { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_sby"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_bat>; - }; - - vdd_5v0_sys: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_bat>; - }; - - vdd_1v5_ddr: regulator-ddr { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_bat>; - }; - - vdd_3v3_sys: regulator-3v { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_bat>; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <20000>; - gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_com: regulator-com { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_5v0_bl: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_bat>; - }; - - hdmi_5v0_sys: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "hdmi_5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - nvidia,i2s-controller = <&tegra_i2s1>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; - nvidia,coupled-mic-hp-det; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - thermal-zones { - /* - * NCT72 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone exists as a simpler solution which prevents - * Transformers from getting too hot from a user's - * tactile perspective. The CPU zone is intended to - * protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct72 0>; - - trips { - trip0: skin-alert { - /* throttle at 57C until temperature drops to 56.8C */ - temperature = <57000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 65C */ - temperature = <65000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct72 1>; - - trips { - trip2: cpu-alert { - /* throttle at 75C until temperature drops to 74.8C */ - temperature = <75000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts deleted file mode 100644 index 51769d5132ae..000000000000 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ /dev/null @@ -1,2138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" - -/ { - model = "NVIDIA Tegra30 Beaver evaluation board"; - compatible = "nvidia,beaver", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x80000000 0x7ff00000>; - }; - - pcie@3000 { - status = "okay"; - - avdd-pexa-supply = <&ldo1_reg>; - vdd-pexa-supply = <&ldo1_reg>; - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - avdd-plle-supply = <&ldo1_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - hvdd-pex-supply = <&sys_3v3_pexs_reg>; - - pci@1,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&sys_3v3_reg>; - pll-supply = <&vio_reg>; - - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; - }; - gpv { - nvidia,pins = "drive_gpv"; - nvidia,pull-up-strength = <16>; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - hdmiddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v_in_reg>; - vcc2-supply = <&vdd_5v_in_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v_in_reg>; - vcc5-supply = <&vdd_5v_in_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v_in_reg>; - vccio-supply = <&vdd_5v_in_reg>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-coupled-with = <&core_vdd_reg>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - - nvidia,tegra-cpu-regulator; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - core_vdd_reg: tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-coupled-with = <&vddctrl_reg>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - - nvidia,tegra-core-regulator; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@1 { - compatible = "winbond,w25q32", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&core_vdd_reg>; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - mmc@78000000 { - status = "okay"; - vqmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - usb@7d004000 { - status = "okay"; - }; - - phy2: usb-phy@7d004000 { - vbus-supply = <&sys_3v3_reg>; - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - gpled1 { - label = "LED1"; /* CR5A1 (blue) */ - gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; - }; - gpled2 { - label = "LED2"; /* CR4A2 (green) */ - gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - vdd_5v_in_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v_in"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - chargepump_5v_reg: regulator-chargepump { - compatible = "regulator-fixed"; - regulator-name = "chargepump_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - ddr_reg: regulator-ddr { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - vdd_5v_sata_reg: regulator-sata { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v_sata"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - usb1_vbus_reg: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; - - sys_3v3_reg: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3,vdd_3v3_alw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - sys_3v3_pexs_reg: regulator-pexs { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3_pexs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_5v0_hdmi: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+VDD_5V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&sys_3v3_reg>; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-beaver", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Beaver"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts deleted file mode 100644 index 247185314f46..000000000000 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-cardhu.dtsi" - -/* This dts file support the cardhu A02 version of board */ - -/ { - model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; - compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; - - mmc@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - ddr_reg: regulator-ddr { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; - - sys_3v3_reg: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_bl_reg: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; - }; -}; - diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts deleted file mode 100644 index 2911f08863a0..000000000000 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-cardhu.dtsi" - -/* This dts file support the cardhu A04 and later versions of board */ - -/ { - model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; - compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; - - mmc@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - ddr_reg: regulator-ddr { - compatible = "regulator-fixed"; - regulator-name = "ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; - - sys_3v3_reg: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - vdd_5v0_reg: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_bl_reg: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; - - vdd_bl2_reg: regulator-bl2 { - compatible = "regulator-fixed"; - regulator-name = "vdd_bl2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi deleted file mode 100644 index 37a9c5a0ca30..000000000000 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ /dev/null @@ -1,711 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include "tegra30.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" - -/** - * This file contains common DT entry for all fab version of Cardhu. - * There is multiple fab version of Cardhu starting from A01 to A07. - * Cardhu fab version A01 and A03 are not supported. Cardhu fab version - * A02 will have different sets of GPIOs for fixed regulator compare to - * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are - * compatible with fab version A04. Based on Cardhu fab version, the - * related dts file need to be chosen like for Cardhu fab version A02, - * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use - * tegra30-cardhu-a04.dts. - * The identification of board is done in two ways, by looking the sticker - * on PCB and by reading board id eeprom. - * The sticker will have number like 600-81291-1000-002 C.3. In this 4th - * number is the fab version like here it is 002 and hence fab version A02. - * The (downstream internal) U-Boot of Cardhu display the board-id as - * follows: - * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 - * In this Fab version is 02 i.e. A02. - * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). - * The location 0x8 of this eeprom contains the Fab version. It is 1 byte - * wide. - */ - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - pcie@3000 { - status = "okay"; - - /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - hvdd-pex-supply = <&pex_hvdd_3v3_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - avdd-plle-supply = <&ldo2_reg>; - - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - panelddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - /* ALS and Proximity sensor */ - isl29028@44 { - compatible = "isil,isl29028"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - i2cmux@70 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; - }; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_ac_bat_reg>; - vcc2-supply = <&vdd_ac_bat_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v0_reg>; - vcc5-supply = <&vdd_ac_bat_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_ac_bat_reg>; - vccio-supply = <&vdd_ac_bat_reg>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - - nvidia,tegra-cpu-regulator; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - nct1008: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - vdd_core: tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-coupled-with = <&vddctrl_reg>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - - nvidia,tegra-core-regulator; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@1 { - compatible = "winbond,w25q32", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - mmc@78000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clk32k_in: clock-32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - interrupt-parent = <&pmic>; - interrupts = <2 0>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wb01"; - ddc-i2c-bus = <&panelddc>; - - power-supply = <&vdd_pnl1_reg>; - enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - vdd_ac_bat_reg: regulator-acbat { - compatible = "regulator-fixed"; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - cam_1v8_reg: regulator-cam { - compatible = "regulator-fixed"; - regulator-name = "cam_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; - - cp_5v_reg: regulator-5v0cp { - compatible = "regulator-fixed"; - regulator-name = "cp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - emmc_3v3_reg: regulator-emmc { - compatible = "regulator-fixed"; - regulator-name = "emmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - modem_3v3_reg: regulator-modem { - compatible = "regulator-fixed"; - regulator-name = "modem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - }; - - pex_hvdd_3v3_reg: regulator-pex { - compatible = "regulator-fixed"; - regulator-name = "pex_hvdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam1_ldo_reg: regulator-cam1 { - compatible = "regulator-fixed"; - regulator-name = "vdd_cam1_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam2_ldo_reg: regulator-cam2 { - compatible = "regulator-fixed"; - regulator-name = "vdd_cam2_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam3_ldo_reg: regulator-cam3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_cam3_ldo"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_com_reg: regulator-com { - compatible = "regulator-fixed"; - regulator-name = "vdd_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_fuse_3v3_reg: regulator-fuse { - compatible = "regulator-fixed"; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_pnl1_reg: regulator-pnl1 { - compatible = "regulator-fixed"; - regulator-name = "vdd_pnl1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_vid_reg: regulator-vid { - compatible = "regulator-fixed"; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-cardhu", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Cardhu"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip0: cpu-alert0 { - /* throttle at 57C until temperature drops to 56.8C */ - temperature = <57000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: cpu-crit { - /* shut down at 60C */ - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts deleted file mode 100644 index 36615c5fda2c..000000000000 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra30-colibri.dtsi" - -/ { - model = "Toradex Colibri T30 on Colibri Evaluation Board"; - compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", - "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - /* Colibri UART-A */ - serial@70006000 { - status = "okay"; - }; - - /* Colibri UART-C */ - serial@70006040 { - status = "okay"; - }; - - /* Colibri UART-B */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* CAM_I2C (I2C3): unused */ - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Colibri SSP */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = ; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - - /* SD/MMC */ - mmc@78000200 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ - no-1-8-v; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbc_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* PWM */ - }; - - clk16m: clock-osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbc_vbus: regulator-usbc-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB5"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - }; - - /* USBH_PEN resp. USB_P_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi deleted file mode 100644 index ed6106f1bea1..000000000000 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ /dev/null @@ -1,1064 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra30.dtsi" - -/* - * Toradex Colibri T30 Module Device Tree - * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B - */ -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - gpio: gpio@6000d000 { - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - clk1-out-pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Address/Data Bus (GMI) */ - gmi-ad0-pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_cs0_n_px6", - "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2", - "uart2_cts_n_pj5", - "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Further pins may be used as GPIOs */ - dap4-din-pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7", - "pbb7", - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat3_py4", - "uart3_cts_n_pa1", - "uart3_txd_pw6", - "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-d18-pm2 { - nvidia,pins = "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_dc0_pn6", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-cs0-n-pn4 { - nvidia,pins = "lcd_cs0_n_pn4", - "lcd_sdin_pz2", - "pu0", - "pu1", - "pu2", - "pu3", - "pu4", - "pu5", - "pu6", - "spi1_miso_px7", - "uart3_rts_n_pc0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr0-pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_wr_n_pz3"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed RDnWR and therefore disabled */ - lcd-cs1-n-pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed GMI_CLK and therefore disabled */ - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */ - sdmmc3-dat4-pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */ - sdmmc3-dat5-pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri BL_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Backlight PWM */ - sdmmc3-dat3-pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri CAN_INT */ - kb-row8-ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri DDC */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri EXT_IO* */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri GPIO */ - clk2-out-pw5 { - nvidia,pins = "clk2_out_pw5", - "pcc2", - "pv3", - "sdmmc1_dat2_py5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr1-pc1 { - nvidia,pins = "lcd_pwr1_pc1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri HOTPLUG_DETECT (HDMI) */ - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri I2C */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Colibri LCD (L_* resp. LDD<*>) */ - lcd-d0-pe0 { - nvidia,pins = "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_pclk_pb3", - "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE - * today's display need DE, disable LCD_M1 - */ - lcd-m1-pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri MMC */ - kb-row10-ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - kb-row11-ps3 { - nvidia,pins = "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Colibri MMC_CD */ - gmi-wp-n-pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb0 { - nvidia,pins = "pbb0", - "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri nRESET_OUT */ - gmi-rst-n-pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri Parallel Camera (Optional) - * pins multiplexed with others and therefore disabled - */ - vi-vsync-pd6 { - nvidia,pins = "vi_d0_pt4", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_mclk_pt1", - "vi_pclk_pt0", - "vi_vsync_pd6"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri PWM */ - sdmmc3-dat2-pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri PWM */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri PWM */ - sdmmc3-cmd-pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri SSP */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Multiplexed SSPFRM, SSPTXD and therefore disabled */ - sdmmc3-dat6-pd3 { - nvidia,pins = "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri UART-A */ - ulpi-data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-B */ - gmi-a16-pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-C */ - uart2-rxd { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBC_DET */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri USBH_PEN */ - spi2-cs1-n-pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBH_OC */ - spi2-cs2-n-pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri VGA not supported and therefore disabled */ - crt-hsync-pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */ - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1", - "pex_wake_n_pdd3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN_V_BUS, LAN_RESET# (On-module) */ - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2", - "pex_l0_prsnt_n_pdd0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */ - pex-l2-rst-n-pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6", - "pex_l2_prsnt_n_pdd7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Not connected and therefore disabled */ - clk1-req-pee2 { - nvidia,pins = "clk1_req_pee2", - "pex_l1_prsnt_n_pdd4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-req-pcc5 { - nvidia,pins = "clk2_req_pcc5", - "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_out_pa0", - "hdmi_cec_pee3", - "sys_clk_req_pz5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-dqs-pi2 { - nvidia,pins = "gmi_dqs_pi2", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_row4_pr4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col6_pq6", - "kb_col7_pq7", - "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr2-pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Power I2C (On-module) */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd-dc1-pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# (On-module) */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller (On-module) - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vio>; - VDDIO-supply = <®_module_3v3>; - clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <®_module_3v3>; - vcc2-supply = <®_module_3v3>; - vcc3-supply = <®_1v8_vio>; - vcc4-supply = <®_module_3v3>; - vcc5-supply = <®_module_3v3>; - vcc6-supply = <®_1v8_vio>; - vcc7-supply = <®_5v0_charge_pump>; - vccio-supply = <®_module_3v3>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "+V1.35_VDDIO_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - /* SW2: unused */ - - vddctrl_reg: vddctrl { - regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - - nvidia,tegra-cpu-regulator; - }; - - reg_1v8_vio: vio { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO1: unused */ - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN - * see also +V3.3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "EN_+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* LDO3: unused */ - - ldo4_reg: ldo4 { - regulator-name = "+V1.2_VDD_RTC"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for (unsupported) analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "+V2.8_AVDD_VDAC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "+V1.05_AVDD_PLLE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "+V1.2_AVDD_PLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "+V1.0_VDD_DDR_HS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - /* forbid to use ADC channels 3-0 (touch) */ - - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; - }; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - vdd_core: regulator@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-coupled-with = <&vddctrl_reg>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - - nvidia,tegra-core-regulator; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - - /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x1>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080500 { - status = "okay"; - }; - }; - - /* eMMC */ - mmc@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */ - usb@7d004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet@1 { - compatible = "usbb95,772b"; - reg = <1>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_lan_v_bus>; - }; - - clk32k_in: clock-xtal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_1v8_vio>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_module_3v3>; - }; - - reg_5v0_charge_pump: regulator-5v0-charge-pump { - compatible = "regulator-fixed"; - regulator-name = "+V5.0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_lan_v_bus: regulator-lan-v-bus { - compatible = "regulator-fixed"; - regulator-name = "LAN_V_BUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Colibri T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi deleted file mode 100644 index b8e0e9117021..000000000000 --- a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: opp-table-cpu0 { - opp-51000000-800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp-51000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-51000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-102000000-800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp-102000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-102000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-204000000-800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp-204000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-204000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-312000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-312000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-340000000-800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp-340000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-370000000-800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp-456000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-456000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-475000000-800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp-475000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-608000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-608000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-620000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-640000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-640000000-900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp-760000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-760000000-900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp-760000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-760000000-975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp-816000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-816000000-912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp-860000000-850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp-860000000-900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp-860000000-975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp-860000000-1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp-910000000-900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp-1000000000-900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp-1000000000-975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp-1000000000-1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp-1000000000-1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp-1100000000-900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp-1100000000-975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp-1100000000-1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp-1100000000-1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp-1100000000-1075 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp-1150000000-975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp-1200000000-975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp-1200000000-1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp-1200000000-1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp-1200000000-1050 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp-1200000000-1075 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp-1200000000-1100 { - opp-microvolt = <1100000 1100000 1250000>; - }; - - opp-1300000000-1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp-1300000000-1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp-1300000000-1050 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp-1300000000-1075 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp-1300000000-1100 { - opp-microvolt = <1100000 1100000 1250000>; - }; - - opp-1300000000-1125 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp-1300000000-1150 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp-1300000000-1175 { - opp-microvolt = <1175000 1175000 1250000>; - }; - - opp-1400000000-1100 { - opp-microvolt = <1100000 1100000 1250000>; - }; - - opp-1400000000-1125 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp-1400000000-1150 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp-1400000000-1175 { - opp-microvolt = <1175000 1175000 1250000>; - }; - - opp-1400000000-1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - - opp-1500000000-1125 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp-1500000000-1150 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp-1500000000-1200 { - opp-microvolt = <1200000 1200000 1250000>; - }; - - opp-1500000000-1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - - opp-1600000000-1212 { - opp-microvolt = <1212000 1212000 1250000>; - }; - - opp-1600000000-1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - - opp-1700000000-1212 { - opp-microvolt = <1212000 1212000 1250000>; - }; - - opp-1700000000-1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi deleted file mode 100644 index 5b9ebb75a09f..000000000000 --- a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi +++ /dev/null @@ -1,499 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: opp-table-cpu0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-51000000-800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x31FE>; - opp-hz = /bits/ 64 <51000000>; - }; - - opp-51000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C01>; - opp-hz = /bits/ 64 <51000000>; - }; - - opp-51000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <51000000>; - }; - - opp-102000000-800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x31FE>; - opp-hz = /bits/ 64 <102000000>; - }; - - opp-102000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C01>; - opp-hz = /bits/ 64 <102000000>; - }; - - opp-102000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <102000000>; - }; - - opp-204000000-800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x31FE>; - opp-hz = /bits/ 64 <204000000>; - opp-suspend; - }; - - opp-204000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C01>; - opp-hz = /bits/ 64 <204000000>; - opp-suspend; - }; - - opp-204000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <204000000>; - opp-suspend; - }; - - opp-312000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C00>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp-312000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp-340000000-800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0192>; - opp-hz = /bits/ 64 <340000000>; - }; - - opp-340000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0F 0x0001>; - opp-hz = /bits/ 64 <340000000>; - }; - - opp-370000000-800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x306C>; - opp-hz = /bits/ 64 <370000000>; - }; - - opp-456000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C00>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp-456000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp-475000000-800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x31FE>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp-475000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>, - <0x01 0x0010>, <0x01 0x0080>, - <0x01 0x0100>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp-608000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0400>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-608000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp-620000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x306C>; - opp-hz = /bits/ 64 <620000000>; - }; - - opp-640000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>, - <0x04 0x0002>, <0x08 0x0002>, - <0x02 0x0010>, <0x04 0x0010>, - <0x08 0x0010>, <0x02 0x0080>, - <0x04 0x0080>, <0x08 0x0080>, - <0x10 0x0080>, <0x02 0x0100>, - <0x04 0x0100>, <0x08 0x0100>, - <0x10 0x0100>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp-640000000-900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp-760000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>, - <0x08 0x0004>, <0x08 0x0008>, - <0x08 0x0010>, <0x08 0x0080>, - <0x10 0x0080>, <0x08 0x0100>, - <0x10 0x0100>, <0x01 0x0400>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, - <0x04 0x0002>, <0x02 0x0004>, - <0x04 0x0004>, <0x02 0x0008>, - <0x04 0x0008>, <0x02 0x0010>, - <0x04 0x0010>, <0x02 0x0080>, - <0x04 0x0080>, <0x02 0x0100>, - <0x04 0x0100>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-760000000-975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp-816000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0400>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-816000000-912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp-860000000-850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0C 0x0001>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp-860000000-900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, - <0x08 0x0002>, <0x04 0x0004>, - <0x08 0x0004>, <0x04 0x0008>, - <0x08 0x0008>, <0x04 0x0010>, - <0x08 0x0010>, <0x04 0x0080>, - <0x08 0x0080>, <0x10 0x0080>, - <0x04 0x0100>, <0x08 0x0100>, - <0x10 0x0100>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp-860000000-975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, - <0x02 0x0004>, <0x02 0x0008>, - <0x02 0x0010>, <0x02 0x0080>, - <0x02 0x0100>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp-860000000-1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp-910000000-900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x18 0x3060>; - opp-hz = /bits/ 64 <910000000>; - }; - - opp-1000000000-900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0C 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>, - <0x08 0x0002>, <0x04 0x0004>, - <0x08 0x0004>, <0x04 0x0008>, - <0x08 0x0008>, <0x04 0x0010>, - <0x08 0x0010>, <0x04 0x0080>, - <0x08 0x0080>, <0x10 0x0080>, - <0x04 0x0100>, <0x08 0x0100>, - <0x10 0x0100>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x019E>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1000000000-1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp-1100000000-900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0001>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp-1100000000-975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>, - <0x08 0x0004>, <0x08 0x0008>, - <0x08 0x0010>, <0x08 0x0080>, - <0x10 0x0080>, <0x08 0x0100>, - <0x10 0x0100>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp-1100000000-1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>, - <0x04 0x0004>, <0x04 0x0008>, - <0x04 0x0010>, <0x04 0x0080>, - <0x04 0x0100>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp-1100000000-1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x019E>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp-1100000000-1075 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp-1150000000-975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x18 0x3060>; - opp-hz = /bits/ 64 <1150000000>; - }; - - opp-1200000000-975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0001>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, - <0x08 0x0004>, <0x08 0x0008>, - <0x08 0x0010>, <0x08 0x0080>, - <0x10 0x0080>, <0x08 0x0100>, - <0x10 0x0100>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, - <0x04 0x0004>, <0x04 0x0008>, - <0x04 0x0010>, <0x04 0x0080>, - <0x04 0x0100>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1050 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x019E>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1075 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1200000000-1100 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp-1300000000-1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>, - <0x10 0x0100>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, - <0x08 0x0080>, <0x08 0x0100>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1050 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>, - <0x08 0x0004>, <0x08 0x0008>, - <0x08 0x0010>, <0x08 0x0020>, - <0x08 0x0040>, <0x04 0x0080>, - <0x04 0x0100>, <0x08 0x1000>, - <0x08 0x2000>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1075 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>, - <0x04 0x0008>, <0x04 0x0010>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1100 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x001C>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1125 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1150 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0182>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1300000000-1175 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp-1400000000-1100 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x18 0x307C>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp-1400000000-1125 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x000C>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp-1400000000-1150 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp-1400000000-1175 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp-1400000000-1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp-1500000000-1125 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>, - <0x10 0x0040>, <0x10 0x1000>, - <0x10 0x2000>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp-1500000000-1150 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>, - <0x08 0x0040>, <0x08 0x1000>, - <0x08 0x2000>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp-1500000000-1200 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp-1500000000-1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp-1600000000-1212 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x3060>; - opp-hz = /bits/ 64 <1600000000>; - }; - - opp-1600000000-1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x3060>; - opp-hz = /bits/ 64 <1600000000>; - }; - - opp-1700000000-1212 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x3060>; - opp-hz = /bits/ 64 <1700000000>; - }; - - opp-1700000000-1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x3060>; - opp-hz = /bits/ 64 <1700000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts deleted file mode 100644 index eef27c82987b..000000000000 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ /dev/null @@ -1,4795 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -#include "tegra30.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" - -/ { - model = "Ouya Game Console"; - compatible = "ouya,ouya", "nvidia,tegra30"; - - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc3; /* WiFi */ - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; /* Debug Port */ - serial1 = &uartc; /* Bluetooth */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma@80000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x80000000 0x30000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - - ramoops@bfdf0000 { - compatible = "ramoops"; - reg = <0xbfdf0000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - trustzone@bfe00000 { - reg = <0xbfe00000 0x200000>; - no-map; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - vdd-supply = <&vdd_vid_reg>; - pll-supply = <&ldo7_reg>; - hdmi-supply = <&sys_3v3_reg>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_groups { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>, - <1000000 4000000 136>; - - /* Azurewave AW-NH660 BCM4330B1 */ - bluetooth { - compatible = "brcm,bcm4330-bt"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - max-speed = <4000000>; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; - - vbat-supply = <&sys_3v3_reg>; - vddio-supply = <&vdd_1v8>; - - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - uartd: serial@70006300 { - status = "okay"; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; - ti,system-power-controller; - ti,sleep-keep-ck32k; - ti,sleep-enable; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v0_reg>; - vcc2-supply = <&vdd_5v0_reg>; - vcc3-supply = <&vdd_1v8>; - vcc4-supply = <&vdd_5v0_reg>; - vcc5-supply = <&vdd_5v0_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v0_reg>; - vccio-supply = <&vdd_5v0_reg>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_cpu: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1270000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - - nvidia,tegra-cpu-regulator; - }; - - vdd_1v8: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - cpu_temp: nct1008@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - - vdd_core: tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - ti,enable-vout-discharge; - - nvidia,tegra-core-regulator; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - memory-controller@7000f000 { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74430504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x74040a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000f /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000010 /* EMC_TXSR */ - 0x00000010 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001e /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000020 /* EMC_TXSR */ - 0x00000020 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x0000003d /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000040 /* EMC_TXSR */ - 0x00000040 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000076 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000007c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00044000 /* EMC_DLL_XFORM_DQS0 */ - 0x00044000 /* EMC_DLL_XFORM_DQS1 */ - 0x00044000 /* EMC_DLL_XFORM_DQS2 */ - 0x00044000 /* EMC_DLL_XFORM_DQS3 */ - 0x00044000 /* EMC_DLL_XFORM_DQS4 */ - 0x00044000 /* EMC_DLL_XFORM_DQS5 */ - 0x00044000 /* EMC_DLL_XFORM_DQS6 */ - 0x00044000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00058000 /* EMC_DLL_XFORM_DQ0 */ - 0x00058000 /* EMC_DLL_XFORM_DQ1 */ - 0x00058000 /* EMC_DLL_XFORM_DQ2 */ - 0x00058000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0148000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ee /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000f8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000c /* EMC_DLL_XFORM_DQS0 */ - 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00d0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - sdmmc3: mmc@78000400 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; - assigned-clock-rates = <50000000>; - - max-frequency = <50000000>; - keep-power-in-suspend; - - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&wifi_pwrseq>; - vmmc-supply = <&sdmmc_3v3_reg>; - vqmmc-supply = <&vdd_1v8>; - - /* Azurewave AW-NH660 BCM4330 */ - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - sdmmc4: mmc@78000600 { - status = "okay"; - - keep-power-in-suspend; - bus-width = <8>; - non-removable; - vmmc-supply = <&sys_3v3_reg>; - vqmmc-supply = <&vdd_1v8>; - nvidia,default-tap = <0x0F>; - max-frequency = <25500000>; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - usb@7d004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet@2 { /* SMSC 10/100T Ethernet Controller */ - compatible = "usb424,9e00"; - reg = <2>; - local-mac-address = [00 11 22 33 44 55]; - }; - }; - - usb-phy@7d004000 { - vbus-supply = <&vdd_smsc>; - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; - }; - - fan: fan { - compatible = "gpio-fan"; - gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - debounce-interval = <10>; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - label = "power-led"; - gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - retain-state-suspended; - }; - }; - - opp-table-actmon { - /delete-node/ opp-900000000; - }; - - opp-table-emc { - /delete-node/ opp-900000000-1350; - }; - - wifi_pwrseq: pwrseq-wifi { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - - vdd_12v_in: regulator-vdd-12v-in { - compatible = "regulator-fixed"; - regulator-name = "vdd_12v_in"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - sdmmc_3v3_reg: regulator-sdmmc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "sdmmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - regulator-always-on; - }; - - vdd_vid_reg: regulator-vdd-vid { - compatible = "regulator-fixed"; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_reg>; - regulator-boot-on; - }; - - ddr_reg: regulator-ddr { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; - - sys_3v3_reg: regulator-sys-3v3 { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; - - vdd_5v0_reg: regulator-vdd-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; - - vdd_smsc: regulator-vdd-smsc { - compatible = "regulator-fixed"; - regulator-name = "vdd_smsc"; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; - }; - - usb3_vbus_reg: regulator-usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_reg>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <5000>; - polling-delay-passive = <5000>; - - thermal-sensors = <&cpu_temp 1>; - - trips { - cpu_alert0: cpu-alert0 { - temperature = <50000>; - hysteresis = <10000>; - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <70000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts deleted file mode 100644 index 8d10eb8b48b9..000000000000 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ /dev/null @@ -1,2858 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -#include "tegra30.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" -#include "tegra30-asus-lvds-display.dtsi" - -/ { - model = "Pegatron Chagall"; - compatible = "pegatron,chagall", "nvidia,tegra30"; - chassis-type = "tablet"; - - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc1; /* uSD slot */ - mmc2 = &sdmmc3; /* WiFi */ - - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - - display0 = &lcd; - display1 = &hdmi; - - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma@80000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x80000000 0x30000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - - ramoops@beb00000 { - compatible = "ramoops"; - reg = <0xbeb00000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - trustzone@bfe00000 { - reg = <0xbfe00000 0x200000>; /* 2MB */ - no-map; - }; - }; - - host1x@50000000 { - hdmi: hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&hdmi_5v0_sys>; - pll-supply = <&vdd_1v8_vio>; - vdd-supply = <&vdd_3v3_sys>; - - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - }; - }; - - vde@6001a000 { - assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; - assigned-clock-rates = <408000000>; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* SDMMC1 pinmux */ - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4", - "sdmmc1_dat2_py5", - "sdmmc1_dat1_py6", - "sdmmc1_dat0_py7", - "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SDMMC2 pinmux */ - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d5_pl3", - "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6", - "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - /* SDMMC3 pinmux */ - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat3_pb4", - "sdmmc3_dat2_pb5", - "sdmmc3_dat1_pb6", - "sdmmc3_dat0_pb7", - "sdmmc3_dat5_pd0", - "sdmmc3_dat4_pd1", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SDMMC4 pinmux */ - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* I2C pinmux */ - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - /* HDMI-CEC pinmux */ - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,lock = <0>; - }; - - /* UART-A */ - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-B */ - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2", - "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-C */ - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* UART-D */ - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* I2S pinmux */ - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PCI-e pinmux */ - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6", - "pex_l0_rst_n_pdd1", - "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7", - "pex_l0_prsnt_n_pdd0", - "pex_l0_clkreq_n_pdd2", - "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SPI pinmux */ - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4", - "spi1_sck_px5", - "spi1_cs0_n_px6", - "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2", - "spi2_cs2_n_pw3"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spi2_mosi_px0 { - nvidia,pins = "spi2_mosi_px0"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Display A pinmux */ - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pclk_pb3", - "lcd_pwr1_pc1", - "lcd_pwr2_pc6", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_vsync_pj4", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_cs0_n_pn4", - "lcd_sdout_pn5", - "lcd_dc0_pn6", - "lcd_sdin_pz2", - "lcd_wr_n_pz3", - "lcd_sck_pz4", - "lcd_cs1_n_pw0", - "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* KBC keys */ - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3", - "kb_row8_ps0", - "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4", - "kb_row7_pr7", - "kb_row10_ps2", - "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3", - "kb_row12_ps4", - "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6", - "vi_hsync_pd7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2", - "vi_d0_pt4", "pbb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4", - "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs4_n_pk2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_wr_n_pi0", - "gmi_oe_n_pi1", - "gmi_dqs_pi2", - "gmi_adv_n_pk0", - "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5", - "gmi_ad12_ph4", - "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = <0>; - nvidia,io-reset = <0>; - }; - - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* HDMI hot-plug-detect */ - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pv2 { - nvidia,pins = "pv2", - "kb_row5_pr5"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO power/drive control */ - drive_dap1 { - nvidia,pins = "drive_dap1", - "drive_dap2", - "drive_dbg", - "drive_at5", - "drive_gme", - "drive_ddc", - "drive_ao1", - "drive_uart3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = ; - nvidia,pull-down-strength = <5>; - nvidia,pull-up-strength = <5>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_gma { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_lcd2 { - nvidia,pins = "drive_lcd2"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <20>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - /* Broadcom GPS BCM47511 */ - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; - - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>, - <1000000 4000000 136>; - - /* Azurewave AW-AH663 BCM4330B1 */ - bluetooth { - compatible = "brcm,bcm4330-bt"; - max-speed = <4000000>; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - - vbat-supply = <&vdd_3v3_sys>; - vddio-supply = <&vdd_1v8_vio>; - }; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - lcd_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* Wolfson Microelectronics WM8903 audio codec */ - wm8903: audio-codec@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - - AVDD-supply = <&vdd_1v8_vio>; - CPVDD-supply = <&vdd_1v8_vio>; - DBVDD-supply = <&vdd_1v8_vio>; - DCVDD-supply = <&vdd_1v8_vio>; - }; - }; - - i2c2: i2c@7000c400 { - status = "okay"; - clock-frequency = <400000>; - - /* Atmel touchscreen */ - touchscreen@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - - interrupt-parent = <&gpio>; - interrupts = ; - reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; - - vdda-supply = <&vdd_3v3_sys>; - vdd-supply = <&vdd_3v3_sys>; - }; - }; - - i2c3: i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - /* AsahiKASEI AK8975 magnetometer sensor */ - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - - vdd-supply = <&vdd_3v3_sen>; - vid-supply = <&vdd_1v8_vio>; - - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; - }; - - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sen>; - }; - - gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sen>; - vlogic-supply = <&vdd_1v8_vio>; - - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; - - /* External I2C interface */ - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - accelerometer@f { - compatible = "kionix,kxtf9"; - reg = <0x0f>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_1v8_vio>; - vddio-supply = <&vdd_1v8_vio>; - - mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "1"; - }; - }; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <93750>; - }; - - i2c5: i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* Texas Instruments TPS659110 PMIC */ - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; - - ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; - ti,system-power-controller; - ti,sleep-keep-ck32k; - ti,sleep-enable; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v0_sys>; - vcc2-supply = <&vdd_5v0_sys>; - vcc3-supply = <&vdd_1v8_vio>; - vcc4-supply = <&vdd_1v8_vio>; - vcc5-supply = <&vdd_5v0_sys>; - vcc6-supply = <&vddio_1v2_ddr>; - vcc7-supply = <&vdd_5v0_sys>; - vccio-supply = <&vdd_5v0_sys>; - - pmic-sleep-hog { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>, - <2 GPIO_ACTIVE_HIGH>, - <6 GPIO_ACTIVE_HIGH>, - <8 GPIO_ACTIVE_HIGH>; - output-high; - }; - - regulators { - /* VDD1 is not used by Chagall */ - - vddio_1v2_ddr: vdd2 { - regulator-name = "vddio_1v2_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_cpu: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <1>; - - nvidia,tegra-cpu-regulator; - }; - - vdd_1v8_vio: vio { - regulator-name = "vdd_1v8_gen"; - /* FIXME: eMMC won't work, if set to 1.8 V */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* eMMC VDD */ - vcore_emmc: ldo1 { - regulator-name = "vdd_emmc_core"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* uSD slot VDD */ - vdd_usd: ldo2 { - regulator-name = "vdd_usd"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - }; - - /* uSD slot VDDIO */ - vddio_usd: ldo3 { - regulator-name = "vddio_usd"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <3200000>; - }; - - ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_1v3_cam_isp"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <8>; - }; - - ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - ti,regulator-ext-sleep-control = <8>; - }; - }; - }; - - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - - vdd_core: core-regulator@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1770000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,enable-vout-discharge; - ti,vsel0-state-high; - ti,vsel1-state-high; - - nvidia,tegra-core-regulator; - }; - }; - - vdd_5v0_sys: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regulator-3v { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <300000>; - gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_sen: regulator-sensors { - compatible = "regulator-fixed"; - regulator-name = "sen_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_5v0_bl: regulator-bl { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - hdmi_5v0_sys: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "hdmi_5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_vbus_usb1: regulator-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vdd_vbus_micro_usb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_vbus_usb3: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_vbus_typea_usb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - - /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x81>; - }; - }; - - memory-controller@7000f000 { - emc-timings-0 { - /* SAMSUNG K4P8G304EB FGC1 */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x73e30303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x72c30303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000018 - 0x00000001 0x00000001 0x00000003 0x00000001 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060403 0x72430504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000006 0x00000003 - 0x00000005 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000003 0x00000002 - 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emem-configuration = < 0x00000006 0xc0000048 - 0x00000002 0x00000003 0x0000000c 0x00000007 - 0x00000009 0x00000001 0x00000002 0x00000006 - 0x00000001 0x00000000 0x00000004 0x00000004 - 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; - }; - }; - - emc-timings-1 { - /* ELPIDA EDB8132B2MA 8D_F */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x73e30303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x72c30303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000018 - 0x00000001 0x00000001 0x00000003 0x00000001 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060403 0x72430504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000006 0x00000003 - 0x00000005 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000003 0x00000002 - 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emem-configuration = < 0x00000006 0xc0000048 - 0x00000002 0x00000003 0x0000000c 0x00000007 - 0x00000009 0x00000001 0x00000002 0x00000006 - 0x00000001 0x00000000 0x00000004 0x00000004 - 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; - }; - }; - - emc-timings-2 { - /* SAMSUNG K4P8G304EB FGC2 */ - nvidia,ram-code = <2>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x73e30303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x72c30303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000018 - 0x00000001 0x00000001 0x00000003 0x00000001 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060403 0x72430504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000006 0x00000003 - 0x00000005 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000003 0x00000002 - 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; - }; - - timing-533000000 { - clock-frequency = <533000000>; - - nvidia,emem-configuration = < 0x00000008 0xc0000060 - 0x00000003 0x00000004 0x00000010 0x0000000a - 0x0000000d 0x00000002 0x00000002 0x00000008 - 0x00000002 0x00000000 0x00000004 0x00000005 - 0x05040002 0x00110b10 0x70281811 0x001f0000 >; - }; - }; - - emc-timings-3 { - /* HYNIX H9TCNNN8JDMMPR NGM */ - nvidia,ram-code = <3>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emem-configuration = < 0x00020001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x73e30303 0x001f0000 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emem-configuration = < 0x00010001 0xc0000010 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060402 0x72c30303 0x001f0000 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < 0x00000001 0xc0000018 - 0x00000001 0x00000001 0x00000003 0x00000001 - 0x00000003 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000002 0x00000002 - 0x02020001 0x00060403 0x72430504 0x001f0000 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < 0x00000003 0xc0000025 - 0x00000001 0x00000001 0x00000006 0x00000003 - 0x00000005 0x00000001 0x00000002 0x00000004 - 0x00000001 0x00000000 0x00000003 0x00000002 - 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; - }; - - timing-533000000 { - clock-frequency = <533000000>; - - nvidia,emem-configuration = < 0x00000008 0xc0000060 - 0x00000003 0x00000004 0x00000010 0x0000000a - 0x0000000d 0x00000002 0x00000002 0x00000008 - 0x00000002 0x00000000 0x00000004 0x00000005 - 0x05040002 0x00110b10 0x70281811 0x001f0000 >; - }; - }; - }; - - memory-controller@7000f400 { - emc-timings-0 { - /* SAMSUNG K4P8G304EB FGC1 */ - nvidia,ram-code = <0>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000003 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x00000060 0x00000000 0x00000018 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000004 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x0000006b 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000000a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000003 - 0x00000006 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x000000c0 0x00000000 0x00000030 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000008 0x00000008 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000000d5 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000013 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000000a>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000006 - 0x0000000d 0x00000004 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x00000181 0x00000000 0x00000060 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x0000000f 0x0000000f - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000001a9 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000025 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010042>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000013>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000c - 0x0000001a 0x00000008 0x00000003 0x00000005 - 0x00000004 0x00000001 0x00000006 0x00000003 - 0x00000003 0x00000002 0x00000002 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000c - 0x0000000a 0x00000303 0x00000000 0x000000c0 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000007 0x0000001d 0x0000001d - 0x00000004 0x0000000b 0x00000005 0x00000004 - 0x00000002 0x00000351 0x00000004 0x00000006 - 0x00000000 0x00000000 0x00004282 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000e0220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000004a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010082>; - nvidia,emc-mode-2 = <0x00020004>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000024>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000017 - 0x00000033 0x00000010 0x00000007 0x00000007 - 0x00000007 0x00000002 0x0000000a 0x00000007 - 0x00000007 0x00000003 0x00000002 0x00000000 - 0x00000003 0x00000007 0x00000004 0x0000000d - 0x0000000e 0x000005e9 0x00000000 0x0000017a - 0x00000002 0x00000002 0x00000007 0x00000000 - 0x00000001 0x0000000c 0x00000038 0x00000038 - 0x00000006 0x00000014 0x00000009 0x00000004 - 0x00000002 0x00000680 0x00000000 0x00000006 - 0x00000000 0x00000000 0x00006282 0x001d0084 - 0x00008000 0x00034000 0x00034000 0x00034000 - 0x00034000 0x00034000 0x00034000 0x00034000 - 0x00034000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00038000 0x00038000 0x00038000 - 0x00038000 0x00080220 0x0800003d 0x00000000 - 0x77ffc004 0x01f1f408 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000090 0x000c000c 0xa0f10404 0x00000000 - 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; - }; - }; - - emc-timings-1 { - /* ELPIDA EDB8132B2MA 8D_F */ - nvidia,ram-code = <1>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000003 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000060 0x00000000 0x00000018 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000004 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x0000006b 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000000a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000003 - 0x00000006 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x000000c0 0x00000000 0x00000030 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000008 0x00000008 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000000d5 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000013 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000000a>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000006 - 0x0000000d 0x00000004 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000181 0x00000000 0x00000060 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x0000000f 0x0000000f - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000001a9 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000025 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010042>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000013>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000c - 0x0000001a 0x00000008 0x00000003 0x00000005 - 0x00000004 0x00000001 0x00000006 0x00000003 - 0x00000003 0x00000002 0x00000002 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000c - 0x0000000a 0x00000303 0x00000000 0x000000c0 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000007 0x0000001d 0x0000001d - 0x00000004 0x0000000b 0x00000005 0x00000004 - 0x00000002 0x00000351 0x00000004 0x00000006 - 0x00000000 0x00000000 0x00004282 0x004400a4 - 0x00008000 0x00070000 0x00070000 0x00070000 - 0x00070000 0x00070000 0x00070000 0x00070000 - 0x00070000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000e0220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000004a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; - }; - - timing-400000000 { - clock-frequency = <400000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010082>; - nvidia,emc-mode-2 = <0x00020004>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000024>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000017 - 0x00000033 0x00000010 0x00000007 0x00000007 - 0x00000007 0x00000002 0x0000000a 0x00000007 - 0x00000007 0x00000003 0x00000002 0x00000000 - 0x00000003 0x00000007 0x00000004 0x0000000d - 0x0000000e 0x000005e9 0x00000000 0x0000017a - 0x00000002 0x00000002 0x00000007 0x00000000 - 0x00000001 0x0000000c 0x00000038 0x00000038 - 0x00000006 0x00000014 0x00000009 0x00000004 - 0x00000002 0x00000680 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00006282 0x001d0084 - 0x00008000 0x00034000 0x00034000 0x00034000 - 0x00034000 0x00034000 0x00034000 0x00034000 - 0x00034000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00048000 0x00048000 0x00048000 - 0x00048000 0x00060220 0x0800003d 0x00000000 - 0x77ffc004 0x01f1f408 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000090 0x000c000c 0xa0f10000 0x00000000 - 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; - }; - }; - - emc-timings-2 { - /* SAMSUNG K4P8G304EB FGC2 */ - nvidia,ram-code = <2>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000003 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000060 0x00000000 0x00000018 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000004 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x0000006b 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000000a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000003 - 0x00000006 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x000000c0 0x00000000 0x00000030 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000008 0x00000008 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000000d5 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000013 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000000a>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000006 - 0x0000000d 0x00000004 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x00000009 0x00000181 0x00000000 0x00000060 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x0000000f 0x0000000f - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000001a9 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000025 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010042>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000013>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000c - 0x0000001a 0x00000008 0x00000003 0x00000005 - 0x00000004 0x00000001 0x00000006 0x00000003 - 0x00000003 0x00000002 0x00000002 0x00000000 - 0x00000001 0x00000004 0x00000001 0x0000000c - 0x0000000a 0x00000303 0x00000000 0x000000c0 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000007 0x0000001d 0x0000001d - 0x00000004 0x0000000b 0x00000005 0x00000004 - 0x00000002 0x00000351 0x00000005 0x00000004 - 0x00000000 0x00000000 0x00004282 0x004400a4 - 0x00008000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000e0220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000004a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; - }; - - timing-533000000 { - clock-frequency = <533000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x000100c2>; - nvidia,emc-mode-2 = <0x00020006>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000030>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001f - 0x00000045 0x00000016 0x00000009 0x00000008 - 0x00000009 0x00000003 0x0000000d 0x00000009 - 0x00000009 0x00000005 0x00000003 0x00000000 - 0x00000004 0x0000000a 0x00000006 0x0000000d - 0x00000010 0x000007df 0x00000000 0x000001f7 - 0x00000003 0x00000003 0x00000009 0x00000000 - 0x00000001 0x0000000f 0x0000004b 0x0000004b - 0x00000008 0x0000001b 0x0000000c 0x00000004 - 0x00000002 0x000008aa 0x00000000 0x00000004 - 0x00000000 0x00000000 0x00006282 0xf0120091 - 0x00008000 0x007f8008 0x007f8008 0x007f8008 - 0x007f8008 0x007f8008 0x007f8008 0x007f8008 - 0x007f8008 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x00080220 0x0200003d 0x00000000 - 0x77ffc004 0x01f1f408 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x000000c0 0x000e000e 0xa0f10000 0x00000000 - 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; - }; - }; - - emc-timings-3 { - /* HYNIX H9TCNNN8JDMMPR NGM */ - nvidia,ram-code = <3>; - - timing-25500000 { - clock-frequency = <25500000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000001 - 0x00000003 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000060 0x00000000 0x00000018 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000004 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x0000006b 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000000a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; - }; - - timing-51000000 { - clock-frequency = <51000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000009>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000003 - 0x00000006 0x00000002 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x000000c0 0x00000000 0x00000030 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x00000008 0x00000008 - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000000d5 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000013 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010022>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x0000000a>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x00000006 - 0x0000000d 0x00000004 0x00000002 0x00000004 - 0x00000004 0x00000001 0x00000005 0x00000002 - 0x00000002 0x00000001 0x00000001 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000b - 0x0000000a 0x00000181 0x00000000 0x00000060 - 0x00000001 0x00000001 0x00000002 0x00000000 - 0x00000001 0x00000007 0x0000000f 0x0000000f - 0x00000003 0x00000008 0x00000004 0x00000004 - 0x00000002 0x000001a9 0x00000004 0x00000004 - 0x00000000 0x00000000 0x00004282 0x007800a4 - 0x00008000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x000fc000 0x000fc000 0x000fc000 - 0x000fc000 0x00100220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x00000025 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x00010042>; - nvidia,emc-mode-2 = <0x00020001>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000013>; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000000c - 0x0000001a 0x00000008 0x00000003 0x00000005 - 0x00000004 0x00000001 0x00000006 0x00000003 - 0x00000003 0x00000002 0x00000002 0x00000000 - 0x00000001 0x00000003 0x00000001 0x0000000c - 0x0000000b 0x00000303 0x00000000 0x000000c0 - 0x00000001 0x00000001 0x00000003 0x00000000 - 0x00000001 0x00000007 0x0000001d 0x0000001d - 0x00000004 0x0000000b 0x00000005 0x00000004 - 0x00000002 0x00000351 0x00000004 0x00000006 - 0x00000000 0x00000000 0x00004282 0x004400a4 - 0x00008000 0x00072000 0x00072000 0x00072000 - 0x00072000 0x00072000 0x00072000 0x00072000 - 0x00072000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00080000 0x00080000 0x00080000 - 0x00080000 0x000e0220 0x0800201c 0x00000000 - 0x77ffc004 0x01f1f008 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x0000004a 0x00090009 0xa0f10000 0x00000000 - 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; - }; - - timing-533000000 { - clock-frequency = <533000000>; - - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x000100c2>; - nvidia,emc-mode-2 = <0x00020006>; - nvidia,emc-mode-reset = <0x00000000>; - nvidia,emc-zcal-cnt-long = <0x00000030>; - nvidia,emc-cfg-periodic-qrst; - - nvidia,emc-configuration = < 0x0000001f - 0x00000045 0x00000016 0x00000009 0x00000008 - 0x00000009 0x00000003 0x0000000d 0x00000009 - 0x00000009 0x00000005 0x00000003 0x00000000 - 0x00000004 0x00000009 0x00000006 0x0000000d - 0x00000010 0x000007df 0x00000000 0x000001f7 - 0x00000003 0x00000003 0x00000009 0x00000000 - 0x00000001 0x0000000f 0x0000004b 0x0000004b - 0x00000008 0x0000001b 0x0000000c 0x00000004 - 0x00000002 0x000008aa 0x00000000 0x00000006 - 0x00000000 0x00000000 0x00006282 0xf0120091 - 0x00008000 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x0000000a 0x0000000a 0x0000000a - 0x0000000a 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0x0000000c 0x0000000c 0x0000000c - 0x0000000c 0x000a0220 0x0800003d 0x00000000 - 0x77ffc004 0x01f1f408 0x00000000 0x00000007 - 0x08000068 0x08000000 0x00000802 0x00064000 - 0x000000c0 0x000e000e 0xa0f10000 0x00000000 - 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; - }; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080400 { /* i2s1 */ - status = "okay"; - }; - - /* BT SCO */ - i2s@70080600 { /* i2s3 */ - status = "okay"; - }; - }; - - sdmmc1: mmc@78000000 { - status = "okay"; - - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - bus-width = <4>; - - vmmc-supply = <&vdd_usd>; /* ldo2 */ - vqmmc-supply = <&vddio_usd>; /* ldo3 */ - }; - - sdmmc3: mmc@78000400 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; - assigned-clock-rates = <50000000>; - - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_1v8_vio>; - - /* Azurewave AW-AH663 BCM4330B1 */ - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - sdmmc4: mmc@78000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_1v8_vio>; - non-removable; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&vdd_vbus_usb1>; - }; - - usb-phy@7d000000 { - status = "okay"; - dr_mode = "otg"; - nvidia,hssync-start-delay = <0>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_vbus_usb3>; - }; - - mains: ac-adapter-detect { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_5v0_bl>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <1 255>; - num-interpolated-steps = <254>; - default-brightness-level = <15>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - cpu2: cpu@2 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - cpu3: cpu@3 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - display-panel { - compatible = "panel-lvds"; - - width-mm = <217>; - height-mm = <136>; - - data-mapping = "jeida-24"; - - panel-timing { - /* 1280x800@60Hz */ - clock-frequency = <68000000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <48>; - hback-porch = <18>; - hsync-len = <30>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <12>; - }; - }; - - extcon-keys { - compatible = "gpio-keys"; - - switch-dock-insert { - label = "Chagall Dock"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - switch-lineout-detect { - label = "Audio dock line-out detect"; - gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - haptic-feedback { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - vcc-supply = <&vdd_3v3_sys>; - }; - - opp-table-actmon { - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; - }; - - opp-table-emc { - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; - }; - - brcm_wifi_pwrseq: pwrseq-wifi { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - - sound { - compatible = "pegatron,tegra-audio-wm8903-chagall", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Pegatron Chagall WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "IN1R", "Mic Jack", - "DMICDAT", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,headset; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, - <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; - - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - thermal-zones { - /* - * NCT72 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone exists as a simpler solution which prevents - * Chagall from getting too hot from a user's tactile - * perspective. The CPU zone is intended to protect - * silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct72 0>; - - trips { - trip0: skin-alert { - /* throttle at 57C until temperature drops to 56.8C */ - temperature = <57000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 65C */ - temperature = <65000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct72 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi deleted file mode 100644 index a2d557155114..000000000000 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ /dev/null @@ -1,1648 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - core_opp_table: opp-table-core { - compatible = "operating-points-v2"; - opp-shared; - - core_opp_950: opp-950000 { - opp-microvolt = <950000 950000 1350000>; - opp-level = <950000>; - }; - - core_opp_1000: opp-1000000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-level = <1000000>; - }; - - core_opp_1050: opp-1050000 { - opp-microvolt = <1050000 1050000 1350000>; - opp-level = <1050000>; - }; - - core_opp_1100: opp-1100000 { - opp-microvolt = <1100000 1100000 1350000>; - opp-level = <1100000>; - }; - - core_opp_1150: opp-1150000 { - opp-microvolt = <1150000 1150000 1350000>; - opp-level = <1150000>; - }; - - core_opp_1200: opp-1200000 { - opp-microvolt = <1200000 1200000 1350000>; - opp-level = <1200000>; - }; - - core_opp_1250: opp-1250000 { - opp-microvolt = <1250000 1250000 1350000>; - opp-level = <1250000>; - }; - - core_opp_1300: opp-1300000 { - opp-microvolt = <1300000 1300000 1350000>; - opp-level = <1300000>; - }; - - core_opp_1350: opp-1350000 { - opp-microvolt = <1350000 1350000 1350000>; - opp-level = <1350000>; - }; - }; - - emc_icc_dvfs_opp_table: opp-table-emc { - compatible = "operating-points-v2"; - - opp-12750000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-12750000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-12750000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-25500000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <25500000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-25500000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <25500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-25500000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <25500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-27000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <27000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-27000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <27000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-27000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <27000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-51000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <51000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-51000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <51000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-51000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <51000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-54000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <54000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-54000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <54000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-54000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <54000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-102000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-102000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-102000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-108000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <108000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - }; - - opp-108000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <108000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-204000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - opp-suspend; - }; - - opp-204000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - opp-suspend; - }; - - opp-266500000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <266500000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - }; - - opp-266500000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <266500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-333500000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <333500000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1000>; - }; - - opp-333500000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <333500000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1200>; - }; - - opp-333500000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <333500000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-375000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <375000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1000>; - }; - - opp-375000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <375000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1200>; - }; - - opp-375000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <375000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-400000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1000>; - }; - - opp-400000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1200>; - }; - - opp-400000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-416000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1200>; - }; - - opp-416000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-450000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <450000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1200>; - }; - - opp-450000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <450000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-500000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <500000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1200>; - }; - - opp-500000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <500000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-533000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <533000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1200>; - }; - - opp-533000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <533000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-625000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <625000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1200>; - }; - - opp-625000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <625000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-667000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <667000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1200>; - }; - - opp-750000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <750000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-800000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <800000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-900000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <900000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>; - }; - }; - - emc_bw_dfs_opp_table: opp-table-actmon { - compatible = "operating-points-v2"; - - opp-12750000 { - opp-hz = /bits/ 64 <12750000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <102000>; - }; - - opp-25500000 { - opp-hz = /bits/ 64 <25500000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <204000>; - }; - - opp-27000000 { - opp-hz = /bits/ 64 <27000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <216000>; - }; - - opp-51000000 { - opp-hz = /bits/ 64 <51000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <408000>; - }; - - opp-54000000 { - opp-hz = /bits/ 64 <54000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <432000>; - }; - - opp-102000000 { - opp-hz = /bits/ 64 <102000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <816000>; - }; - - opp-108000000 { - opp-hz = /bits/ 64 <108000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <864000>; - }; - - opp-204000000 { - opp-hz = /bits/ 64 <204000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <1632000>; - opp-suspend; - }; - - opp-266500000 { - opp-hz = /bits/ 64 <266500000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <2132000>; - }; - - opp-333500000 { - opp-hz = /bits/ 64 <333500000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <2668000>; - }; - - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <3000000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <3200000>; - }; - - opp-416000000 { - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <3328000>; - }; - - opp-450000000 { - opp-hz = /bits/ 64 <450000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <3600000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <4000000>; - }; - - opp-533000000 { - opp-hz = /bits/ 64 <533000000>; - opp-supported-hw = <0x000F>; - opp-peak-kBps = <4264000>; - }; - - opp-625000000 { - opp-hz = /bits/ 64 <625000000>; - opp-supported-hw = <0x000E>; - opp-peak-kBps = <5000000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-supported-hw = <0x0006>; - opp-peak-kBps = <5336000>; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - opp-supported-hw = <0x0004>; - opp-peak-kBps = <6000000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-supported-hw = <0x0004>; - opp-peak-kBps = <6400000>; - }; - - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-supported-hw = <0x0004>; - opp-peak-kBps = <7200000>; - }; - }; - - pcie_dvfs_opp_table: opp-table-pcie { - compatible = "operating-points-v2"; - - opp-250000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <250000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - host1x_dvfs_opp_table: opp-table-host1x { - compatible = "operating-points-v2"; - - opp-152000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <152000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - }; - - opp-188000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <188000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1050>; - }; - - opp-222000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <222000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1100>; - }; - - opp-242000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <242000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-254000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <254000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1150>; - }; - - opp-267000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <267000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1200>; - }; - - opp-300000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>; - }; - }; - - mpe_dvfs_opp_table: opp-table-mpe { - compatible = "operating-points-v2"; - - opp-234000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <234000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1000>; - }; - - opp-247000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-285000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1050>; - }; - - opp-304000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <304000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1050>; - }; - - opp-332000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <332000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1100>; - }; - - opp-361000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <361000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-380000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1150>; - }; - - opp-408000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <408000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1150>; - }; - - opp-416000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1200>; - }; - - opp-446000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <446000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>; - }; - - opp-484000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <484000000>; - opp-supported-hw = <0x000C>; - required-opps = <&core_opp_1250>; - }; - - opp-520000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <520000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-600000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>; - }; - }; - - vi_dvfs_opp_table: opp-table-vi { - compatible = "operating-points-v2"; - - opp-216000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <216000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1000>; - }; - - opp-219000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <219000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-267000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <267000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1050>; - }; - - opp-285000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1050>; - }; - - opp-300000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <300000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1100>; - }; - - opp-371000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <371000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1150>; - }; - - opp-409000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <409000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1200>; - }; - - opp-425000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <425000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1250>; - }; - - opp-470000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <470000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - }; - - epp_dvfs_opp_table: opp-table-epp { - compatible = "operating-points-v2"; - - opp-267000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <267000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - }; - - opp-285000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1050>; - }; - - opp-304000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <304000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1050>; - }; - - opp-332000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <332000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1100>; - }; - - opp-361000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <361000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-380000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1150>; - }; - - opp-408000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <408000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1150>; - }; - - opp-416000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1200>; - }; - - opp-446000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <446000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>; - }; - - opp-484000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <484000000>; - opp-supported-hw = <0x000C>; - required-opps = <&core_opp_1250>; - }; - - opp-520000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <520000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-600000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>; - }; - }; - - gr2d_dvfs_opp_table: opp-table-gr2d { - compatible = "operating-points-v2"; - - opp-267000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <267000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - }; - - opp-285000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1050>; - }; - - opp-304000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <304000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1050>; - }; - - opp-332000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <332000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1100>; - }; - - opp-361000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <361000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-380000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1150>; - }; - - opp-408000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <408000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1150>; - }; - - opp-416000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1200>; - }; - - opp-446000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <446000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>; - }; - - opp-484000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <484000000>; - opp-supported-hw = <0x000C>; - required-opps = <&core_opp_1250>; - }; - - opp-520000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <520000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-600000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>; - }; - }; - - gr3d_dvfs_opp_table: opp-table-gr3d { - compatible = "operating-points-v2"; - - opp-234000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <234000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1000>, <&core_opp_1000>; - }; - - opp-247000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>, <&core_opp_1000>; - }; - - opp-285000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <285000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1050>, <&core_opp_1050>; - }; - - opp-304000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <304000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1050>, <&core_opp_1050>; - }; - - opp-332000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <332000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1100>, <&core_opp_1100>; - }; - - opp-361000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <361000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>, <&core_opp_1100>; - }; - - opp-380000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1150>, <&core_opp_1150>; - }; - - opp-408000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <408000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1150>, <&core_opp_1150>; - }; - - opp-416000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1200>, <&core_opp_1200>; - }; - - opp-446000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <446000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>, <&core_opp_1200>; - }; - - opp-484000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <484000000>; - opp-supported-hw = <0x000C>; - required-opps = <&core_opp_1250>, <&core_opp_1250>; - }; - - opp-520000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <520000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>, <&core_opp_1300>; - }; - - opp-600000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>, <&core_opp_1350>; - }; - }; - - disp1_dvfs_opp_table: opp-table-disp1 { - compatible = "operating-points-v2"; - - opp-120000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <120000000>; - opp-supported-hw = <0x0009>; - required-opps = <&core_opp_1000>; - }; - - opp-155000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <155000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1000>; - }; - - opp-190000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x0009>; - required-opps = <&core_opp_1200>; - }; - - opp-268000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <268000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1050>; - }; - }; - - disp2_dvfs_opp_table: opp-table-disp2 { - compatible = "operating-points-v2"; - - opp-120000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <120000000>; - opp-supported-hw = <0x0009>; - required-opps = <&core_opp_1000>; - }; - - opp-155000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <155000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1000>; - }; - - opp-190000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <190000000>; - opp-supported-hw = <0x0009>; - required-opps = <&core_opp_1200>; - }; - - opp-268000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <268000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1050>; - }; - }; - - hdmi_dvfs_opp_table: opp-table-hdmi { - compatible = "operating-points-v2"; - - opp-148500000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <148500000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - tvo_dvfs_opp_table: opp-table-tvo { - compatible = "operating-points-v2"; - - opp-297000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <297000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - }; - - dsia_dvfs_opp_table: opp-table-dsia { - compatible = "operating-points-v2"; - - opp-275000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <275000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - dsib_dvfs_opp_table: opp-table-dsib { - compatible = "operating-points-v2"; - - opp-275000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <275000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - sclk_dvfs_opp_table: opp-table-sclk { - compatible = "operating-points-v2"; - - opp-51000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <51000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_950>; - }; - - opp-136000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <136000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1000>; - }; - - opp-164000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <164000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1050>; - }; - - opp-191000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <191000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1100>; - }; - - opp-205000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <205000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1000>; - }; - - opp-216000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <216000000>; - opp-supported-hw = <0x0001>; - required-opps = <&core_opp_1150>; - }; - - opp-227000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <227000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1100>; - }; - - opp-267000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <267000000>; - opp-supported-hw = <0x0006>; - required-opps = <&core_opp_1200>; - }; - - opp-334000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <334000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1250>; - }; - - opp-378000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <378000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - }; - - pll_c_dvfs_opp_table: opp-table-pllc { - compatible = "operating-points-v2"; - - opp-533000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <533000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-667000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <667000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-800000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <800000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - - opp-1066000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <1066000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - - opp-1200000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <1200000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1350>; - }; - }; - - pll_e_dvfs_opp_table: opp-table-plle { - compatible = "operating-points-v2"; - - opp-100000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - pll_m_dvfs_opp_table: opp-table-pllm { - compatible = "operating-points-v2"; - - opp-533000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <533000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-667000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <667000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-800000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <800000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1100>; - }; - - opp-1066000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <1066000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - vde_dvfs_opp_table: opp-table-vde { - compatible = "operating-points-v2"; - - opp-228000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <228000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1000>; - }; - - opp-247000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <247000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1000>; - }; - - opp-275000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <275000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1050>; - }; - - opp-304000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <304000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1050>; - }; - - opp-332000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <332000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1100>; - }; - - opp-352000000-1100 { - opp-microvolt = <1100000 1100000 1350000>; - opp-hz = /bits/ 64 <352000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1100>; - }; - - opp-380000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <380000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1150>; - }; - - opp-400000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1150>; - }; - - opp-416000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <416000000>; - opp-supported-hw = <0x0003>; - required-opps = <&core_opp_1200>; - }; - - opp-437000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <437000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1200>; - }; - - opp-484000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <484000000>; - opp-supported-hw = <0x000C>; - required-opps = <&core_opp_1250>; - }; - - opp-520000000-1300 { - opp-microvolt = <1300000 1300000 1350000>; - opp-hz = /bits/ 64 <520000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1300>; - }; - - opp-600000000-1350 { - opp-microvolt = <1350000 1350000 1350000>; - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x0004>; - required-opps = <&core_opp_1350>; - }; - }; - - fuse_burn_dvfs_opp_table: opp-table-fuseburn { - compatible = "operating-points-v2"; - - opp-26000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <26000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1150>; - }; - }; - - nor_dvfs_opp_table: opp-table-nor { - compatible = "operating-points-v2"; - - opp-108000000-1250 { - opp-microvolt = <1250000 1250000 1350000>; - opp-hz = /bits/ 64 <108000000>; - opp-supported-hw = <0x0008>; - required-opps = <&core_opp_1250>; - }; - - opp-115000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <115000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1000>; - }; - - opp-130000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <130000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1050>; - }; - - opp-133000000-1150 { - opp-microvolt = <1150000 1150000 1350000>; - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0x0007>; - required-opps = <&core_opp_1150>; - }; - }; - - pwm_dvfs_opp_table: opp-table-pwm { - compatible = "operating-points-v2"; - - opp-408000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <408000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - sbc1_dvfs_opp_table: opp-table-sbc1 { - compatible = "operating-points-v2"; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-60000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <60000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - - opp-100000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sbc2_dvfs_opp_table: opp-table-sbc2 { - compatible = "operating-points-v2"; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-60000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <60000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - - opp-100000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sbc3_dvfs_opp_table: opp-table-sbc3 { - compatible = "operating-points-v2"; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-60000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <60000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - - opp-100000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sbc4_dvfs_opp_table: opp-table-sbc4 { - compatible = "operating-points-v2"; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-60000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <60000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - - opp-100000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sbc5_dvfs_opp_table: opp-table-sbc5 { - compatible = "operating-points-v2"; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-60000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <60000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - - opp-100000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sbc6_dvfs_opp_table: opp-table-sbc6 { - compatible = "operating-points-v2"; - - opp-52000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <52000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - - opp-60000000-1050 { - opp-microvolt = <1050000 1050000 1350000>; - opp-hz = /bits/ 64 <60000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1050>; - }; - - opp-100000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <100000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { - compatible = "operating-points-v2"; - - opp-104000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <104000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-208000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <208000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { - compatible = "operating-points-v2"; - - opp-104000000-950 { - opp-microvolt = <950000 950000 1350000>; - opp-hz = /bits/ 64 <104000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_950>; - }; - - opp-208000000-1200 { - opp-microvolt = <1200000 1200000 1350000>; - opp-hz = /bits/ 64 <208000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1200>; - }; - }; - - usbd_dvfs_opp_table: opp-table-usbd { - compatible = "operating-points-v2"; - - opp-480000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - usb2_dvfs_opp_table: opp-table-usb2 { - compatible = "operating-points-v2"; - - opp-480000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; - - usb3_dvfs_opp_table: opp-table-usb3 { - compatible = "operating-points-v2"; - - opp-480000000-1000 { - opp-microvolt = <1000000 1000000 1350000>; - opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x000F>; - required-opps = <&core_opp_1000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi deleted file mode 100644 index 9cba67b54111..000000000000 --- a/arch/arm/boot/dts/tegra30.dtsi +++ /dev/null @@ -1,1348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -#include "tegra30-peripherals-opp.dtsi" - -/ { - compatible = "nvidia,tegra30"; - interrupt-parent = <&lic>; - #address-cells = <1>; - #size-cells = <1>; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x0>; - }; - - pcie@3000 { - compatible = "nvidia,tegra30-pcie"; - device_type = "pci"; - reg = <0x00003000 0x00000800>, /* PADS registers */ - <0x00003800 0x00000200>, /* AFI registers */ - <0x10000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ - <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ - <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ - <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ - <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ - <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA30_CLK_PCIE>, - <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PLL_E>, - <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - power-domains = <&pd_core>; - operating-points-v2 = <&pcie_dvfs_opp_table>; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - - sram@40000000 { - compatible = "mmio-sram"; - reg = <0x40000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000>; - - vde_pool: sram@400 { - reg = <0x400 0x3fc00>; - pool; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra30-host1x"; - reg = <0x50000000 0x00024000>; - interrupts = , /* syncpt */ - ; /* general */ - interrupt-names = "syncpt", "host1x"; - clocks = <&tegra_car TEGRA30_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; - reset-names = "host1x", "mc"; - iommus = <&mc TEGRA_SWGROUP_HC>; - power-domains = <&pd_heg>; - operating-points-v2 = <&host1x_dvfs_opp_table>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe@54040000 { - compatible = "nvidia,tegra30-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - power-domains = <&pd_mpe>; - operating-points-v2 = <&mpe_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_MPE>; - - status = "disabled"; - }; - - vi@54080000 { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_VI>; - resets = <&tegra_car 20>; - reset-names = "vi"; - power-domains = <&pd_venc>; - operating-points-v2 = <&vi_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_VI>; - - status = "disabled"; - }; - - epp@540c0000 { - compatible = "nvidia,tegra30-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - power-domains = <&pd_heg>; - operating-points-v2 = <&epp_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_EPP>; - - status = "disabled"; - }; - - isp@54100000 { - compatible = "nvidia,tegra30-isp"; - reg = <0x54100000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - power-domains = <&pd_venc>; - - iommus = <&mc TEGRA_SWGROUP_ISP>; - - status = "disabled"; - }; - - gr2d@54140000 { - compatible = "nvidia,tegra30-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_GR2D>; - resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; - reset-names = "2d", "mc"; - power-domains = <&pd_heg>; - operating-points-v2 = <&gr2d_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_G2>; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra30-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D>, - <&tegra_car TEGRA30_CLK_GR3D2>; - clock-names = "3d", "3d2"; - resets = <&tegra_car 24>, - <&tegra_car 98>, - <&mc TEGRA30_MC_RESET_3D>, - <&mc TEGRA30_MC_RESET_3D2>; - reset-names = "3d", "3d2", "mc", "mc2"; - power-domains = <&pd_3d0>, <&pd_3d1>; - power-domain-names = "3d0", "3d1"; - operating-points-v2 = <&gr3d_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_NV>, - <&mc TEGRA_SWGROUP_NV2>; - }; - - dc@54200000 { - compatible = "nvidia,tegra30-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - power-domains = <&pd_core>; - operating-points-v2 = <&disp1_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, - <&mc TEGRA30_MC_DISPLAY0B &emc>, - <&mc TEGRA30_MC_DISPLAY1B &emc>, - <&mc TEGRA30_MC_DISPLAY0C &emc>, - <&mc TEGRA30_MC_DISPLAYHC &emc>; - interconnect-names = "wina", - "winb", - "winb-vfilter", - "winc", - "cursor"; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra30-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP2>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - power-domains = <&pd_core>; - operating-points-v2 = <&disp2_dvfs_opp_table>; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, - <&mc TEGRA30_MC_DISPLAY0BB &emc>, - <&mc TEGRA30_MC_DISPLAY1BB &emc>, - <&mc TEGRA30_MC_DISPLAY0CB &emc>, - <&mc TEGRA30_MC_DISPLAYHCB &emc>; - interconnect-names = "wina", - "winb", - "winb-vfilter", - "winc", - "cursor"; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra30-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_HDMI>, - <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - power-domains = <&pd_core>; - operating-points-v2 = <&hdmi_dvfs_opp_table>; - status = "disabled"; - }; - - tvo@542c0000 { - compatible = "nvidia,tegra30-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TVO>; - power-domains = <&pd_core>; - operating-points-v2 = <&tvo_dvfs_opp_table>; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra30-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>, - <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; - clock-names = "dsi", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - power-domains = <&pd_core>; - operating-points-v2 = <&dsia_dvfs_opp_table>; - status = "disabled"; - }; - - dsi@54400000 { - compatible = "nvidia,tegra30-dsi"; - reg = <0x54400000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIB>, - <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; - clock-names = "dsi", "parent"; - resets = <&tegra_car 84>; - reset-names = "dsi"; - power-domains = <&pd_core>; - operating-points-v2 = <&dsib_dvfs_opp_table>; - status = "disabled"; - }; - }; - - timer@50040600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x50040600 0x20>; - interrupt-parent = <&intc>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TWD>; - }; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000>, - <0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <6 6 2>; - arm,tag-latency = <5 5 2>; - cache-unified; - cache-level = <2>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra30-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>, - <0x60004400 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - timer@60005000 { - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA30_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - pll-c { - compatible = "nvidia,tegra30-pllc"; - clocks = <&tegra_car TEGRA30_CLK_PLL_C>; - power-domains = <&pd_core>; - operating-points-v2 = <&pll_c_dvfs_opp_table>; - }; - - pll-e { - compatible = "nvidia,tegra30-plle"; - clocks = <&tegra_car TEGRA30_CLK_PLL_E>; - power-domains = <&pd_core>; - operating-points-v2 = <&pll_e_dvfs_opp_table>; - }; - - pll-m { - compatible = "nvidia,tegra30-pllm"; - clocks = <&tegra_car TEGRA30_CLK_PLL_M>; - power-domains = <&pd_core>; - operating-points-v2 = <&pll_m_dvfs_opp_table>; - }; - - sclk { - compatible = "nvidia,tegra30-sclk"; - clocks = <&tegra_car TEGRA30_CLK_SCLK>; - power-domains = <&pd_core>; - operating-points-v2 = <&sclk_dvfs_opp_table>; - }; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra30-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA30_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb: ahb@6000c000 { - compatible = "nvidia,tegra30-ahb"; - reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ - }; - - actmon: actmon@6000c800 { - compatible = "nvidia,tegra30-actmon"; - reg = <0x6000c800 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_ACTMON>, - <&tegra_car TEGRA30_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car TEGRA30_CLK_ACTMON>; - reset-names = "actmon"; - operating-points-v2 = <&emc_bw_dfs_opp_table>; - interconnects = <&mc TEGRA30_MC_MPCORER &emc>; - interconnect-names = "cpu-read"; - #cooling-cells = <2>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-ranges = <&pinmux 0 0 248>; - }; - - vde@6001a000 { - compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000>, /* Syntax Engine */ - <0x6001b000 0x1000>, /* Video Bitstream Engine */ - <0x6001c000 0x100>, /* Macroblock Engine */ - <0x6001c200 0x100>, /* Post-processing Engine */ - <0x6001c400 0x100>, /* Motion Compensation Engine */ - <0x6001c600 0x100>, /* Transform Engine */ - <0x6001c800 0x100>, /* Pixel prediction block */ - <0x6001ca00 0x100>, /* Video DMA */ - <0x6001d800 0x400>; /* Video frame controls */ - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA30_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; - iommus = <&mc TEGRA_SWGROUP_VDE>; - power-domains = <&pd_vde>; - operating-points-v2 = <&vde_dvfs_opp_table>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64>, /* Chip revision */ - <0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra30-pinmux"; - reg = <0x70000868 0x0d4>, /* Pad control registers */ - <0x70003000 0x3e4>; /* Mux registers */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uarte: serial@70006400 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gmi@70009000 { - compatible = "nvidia,tegra30-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x48000000 0x7ffffff>; - clocks = <&tegra_car TEGRA30_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - power-domains = <&pd_core>; - operating-points-v2 = <&nor_dvfs_opp_table>; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA30_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - power-domains = <&pd_core>; - operating-points-v2 = <&pwm_dvfs_opp_table>; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C1>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C2>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C3>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c700 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C4>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - resets = <&tegra_car 103>; - reset-names = "i2c"; - clock-names = "div-clk", "fast-clk"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000d000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C5>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra30-slink"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC1>; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - power-domains = <&pd_core>; - operating-points-v2 = <&sbc1_dvfs_opp_table>; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra30-slink"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC2>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - power-domains = <&pd_core>; - operating-points-v2 = <&sbc2_dvfs_opp_table>; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra30-slink"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC3>; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - power-domains = <&pd_core>; - operating-points-v2 = <&sbc3_dvfs_opp_table>; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra30-slink"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC4>; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - power-domains = <&pd_core>; - operating-points-v2 = <&sbc4_dvfs_opp_table>; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra30-slink"; - reg = <0x7000dc00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC5>; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - power-domains = <&pd_core>; - operating-points-v2 = <&sbc5_dvfs_opp_table>; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra30-slink"; - reg = <0x7000de00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC6>; - resets = <&tegra_car 106>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - power-domains = <&pd_core>; - operating-points-v2 = <&sbc6_dvfs_opp_table>; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_RTC>; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra30-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - - pd_core: core-domain { - #power-domain-cells = <0>; - operating-points-v2 = <&core_opp_table>; - }; - - powergates { - pd_heg: heg { - clocks = <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - resets = <&mc TEGRA30_MC_RESET_2D>, - <&mc TEGRA30_MC_RESET_EPP>, - <&mc TEGRA30_MC_RESET_HC>, - <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&mc TEGRA30_MC_RESET_MPE>, - <&tegra_car TEGRA30_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_3d0: td { - clocks = <&tegra_car TEGRA30_CLK_GR3D>; - resets = <&mc TEGRA30_MC_RESET_3D>, - <&tegra_car TEGRA30_CLK_GR3D>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_3d1: td2 { - clocks = <&tegra_car TEGRA30_CLK_GR3D2>; - resets = <&mc TEGRA30_MC_RESET_3D2>, - <&tegra_car TEGRA30_CLK_GR3D2>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA30_CLK_VDE>; - resets = <&mc TEGRA30_MC_RESET_VDE>, - <&tegra_car TEGRA30_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_venc: venc { - clocks = <&tegra_car TEGRA30_CLK_ISP>, - <&tegra_car TEGRA30_CLK_VI>, - <&tegra_car TEGRA30_CLK_CSI>; - resets = <&mc TEGRA30_MC_RESET_ISP>, - <&mc TEGRA30_MC_RESET_VI>, - <&tegra_car TEGRA30_CLK_ISP>, - <&tegra_car 20 /* VI */>, - <&tegra_car TEGRA30_CLK_CSI>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - }; - }; - - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x400>; - clocks = <&tegra_car TEGRA30_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - #reset-cells = <1>; - #interconnect-cells = <1>; - }; - - emc: memory-controller@7000f400 { - compatible = "nvidia,tegra30-emc"; - reg = <0x7000f400 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_EMC>; - power-domains = <&pd_core>; - - nvidia,memory-controller = <&mc>; - operating-points-v2 = <&emc_icc_dvfs_opp_table>; - - #interconnect-cells = <0>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra30-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA30_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - power-domains = <&pd_core>; - operating-points-v2 = <&fuse_burn_dvfs_opp_table>; - }; - - tsensor: tsensor@70014000 { - compatible = "nvidia,tegra30-tsensor"; - reg = <0x70014000 0x500>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; - resets = <&tegra_car TEGRA30_CLK_TSENSOR>; - - assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; - assigned-clock-rates = <500000>; - - #thermal-sensor-cells = <1>; - }; - - hda@70030000 { - compatible = "nvidia,tegra30-hda"; - reg = <0x70030000 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_HDA>, - <&tegra_car TEGRA30_CLK_HDA2HDMI>, - <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - ahub@70080000 { - compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200>, - <0x70080200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, - <&tegra_car TEGRA30_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>; /* spdif */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA30_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA30_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA30_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA30_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA30_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - mmc@78000000 { - compatible = "nvidia,tegra30-sdhci"; - reg = <0x78000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - power-domains = <&pd_core>; - operating-points-v2 = <&sdmmc1_dvfs_opp_table>; - status = "disabled"; - }; - - mmc@78000200 { - compatible = "nvidia,tegra30-sdhci"; - reg = <0x78000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@78000400 { - compatible = "nvidia,tegra30-sdhci"; - reg = <0x78000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - power-domains = <&pd_core>; - operating-points-v2 = <&sdmmc3_dvfs_opp_table>; - status = "disabled"; - }; - - mmc@78000600 { - compatible = "nvidia,tegra30-sdhci"; - reg = <0x78000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-ehci"; - reg = <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,needs-double-reset; - nvidia,phy = <&phy1>; - power-domains = <&pd_core>; - operating-points-v2 = <&usbd_dvfs_opp_table>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000>, - <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USBD>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <1>; - nvidia,xcvr-lsrslew = <1>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,has-utmi-pad-registers; - nvidia,pmc = <&tegra_pmc 0>; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra30-ehci"; - reg = <0x7d004000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - power-domains = <&pd_core>; - operating-points-v2 = <&usb2_dvfs_opp_table>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000>, - <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB2>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,pmc = <&tegra_pmc 2>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra30-ehci"; - reg = <0x7d008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - power-domains = <&pd_core>; - operating-points-v2 = <&usb3_dvfs_opp_table>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000>, - <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB3>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,pmc = <&tegra_pmc 1>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - #cooling-cells = <2>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - thermal-zones { - tsensor0-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsensor 0>; - - trips { - level1_trip: dvfs-alert { - /* throttle at 80C until temperature drops to 79.8C */ - temperature = <80000>; - hysteresis = <200>; - type = "passive"; - }; - - level2_trip: cpu-div2-throttle { - /* hardware CPU x2 freq throttle at 85C */ - temperature = <85000>; - hysteresis = <200>; - type = "hot"; - }; - - level3_trip: soc-critical { - /* hardware shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&level1_trip>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - tsensor1-thermal { - status = "disabled"; - - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <0>; /* milliseconds */ - - thermal-sensors = <&tsensor 1>; - - trips { - dvfs-alert { - temperature = <80000>; - hysteresis = <200>; - type = "passive"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ti/Makefile b/arch/arm/boot/dts/ti/Makefile new file mode 100644 index 000000000000..871079a7bc3b --- /dev/null +++ b/arch/arm/boot/dts/ti/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += davinci +subdir-y += keystone +subdir-y += omap diff --git a/arch/arm/boot/dts/ti/davinci/Makefile b/arch/arm/boot/dts/ti/davinci/Makefile new file mode 100644 index 000000000000..c0e388eb3dd1 --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_DAVINCI) += \ + da850-lcdk.dtb \ + da850-enbw-cmc.dtb \ + da850-evm.dtb \ + da850-lego-ev3.dtb diff --git a/arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts b/arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts new file mode 100644 index 000000000000..d4a5237cee0a --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree for AM1808 EnBW CMC board + * + * Copyright 2012 DENX Software Engineering GmbH + * Heiko Schocher + */ +/dts-v1/; +#include "da850.dtsi" + +/ { + compatible = "enbw,cmc", "ti,da850"; + model = "EnBW CMC"; + + soc@1c00000 { + serial0: serial@42000 { + status = "okay"; + }; + serial1: serial@10c000 { + status = "okay"; + }; + serial2: serial@10d000 { + status = "okay"; + }; + mdio: mdio@224000 { + status = "okay"; + }; + eth0: ethernet@220000 { + status = "okay"; + }; + }; +}; + +&ref_clk { + clock-frequency = <24000000>; +}; + +&edma0 { + ti,edma-reserved-slot-ranges = <32 50>; +}; + +&edma1 { + ti,edma-reserved-slot-ranges = <32 90>; +}; diff --git a/arch/arm/boot/dts/ti/davinci/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts new file mode 100644 index 000000000000..111708d992ca --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree for DA850 EVM board + * + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; +#include "da850.dtsi" +#include + +/ { + compatible = "ti,da850-evm", "ti,da850"; + model = "DA850/AM1808/OMAP-L138 EVM"; + + chosen { + stdout-path = &serial2; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + ethernet0 = ð0; + spi0 = &spi1; + }; + + backlight: backlight-pwm { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + power-supply = <&backlight_lcd>; + compatible = "pwm-backlight"; + /* + * The PWM here corresponds to production hardware. The + * schematic needs to be 1015171 (15 March 2010), Rev A + * or newer. + */ + pwms = <&ecap2 0 50000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; + default-brightness-level = <7>; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, change the status below to 'disabled' then + * then change the status of the vpif below to 'okay' + */ + status = "okay"; + enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <4>; + vsync-len = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + baseboard_3v3: fixedregulator-3v3 { + /* TPS73701DCQ */ + compatible = "regulator-fixed"; + regulator-name = "baseboard_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbat>; + regulator-always-on; + regulator-boot-on; + }; + + baseboard_1v8: fixedregulator-1v8 { + /* TPS73701DCQ */ + compatible = "regulator-fixed"; + regulator-name = "baseboard_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vbat>; + regulator-always-on; + regulator-boot-on; + }; + + backlight_lcd: backlight-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850-OMAPL138 EVM"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; +}; + +&ecap2 { + status = "okay"; +}; + +&ref_clk { + clock-frequency = <24000000>; +}; + +&pmx_core { + status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* + * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, + * AFSR, AMUTE + */ + 0x00 0x11111111 0xffffffff + /* AXR11, AXR12 */ + 0x04 0x00011000 0x000ff000 + >; + }; + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ + 0x1c 0x10110110 0xf0ff0ff0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; +}; + +&cpu { + cpu-supply = <&vdcdc3_reg>; +}; + +/* + * The standard da850-evm kits and SOM's are 375MHz so enable this operating + * point by default. Higher frequencies must be enabled for custom boards with + * other variants of the SoC. + */ +&opp_375 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&lcdc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + tps: tps@48 { + reg = <0x48>; + }; + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&vdcdc2_reg>; + AVDD-supply = <&baseboard_3v3>; + DRVDD-supply = <&baseboard_3v3>; + DVDD-supply = <&baseboard_1v8>; + }; + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + tca6416_bb: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&wdt { + status = "okay"; +}; + +&mmc0 { + max-frequency = <50000000>; + bus-width = <4>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <30000000>; + m25p,fast-read; + reg = <0>; + partition@0 { + label = "U-Boot-SPL"; + reg = <0x00000000 0x00010000>; + read-only; + }; + partition@1 { + label = "U-Boot"; + reg = <0x00010000 0x00080000>; + read-only; + }; + partition@2 { + label = "U-Boot-Env"; + reg = <0x00090000 0x00010000>; + read-only; + }; + partition@3 { + label = "Kernel"; + reg = <0x000a0000 0x00280000>; + }; + partition@4 { + label = "Filesystem"; + reg = <0x00320000 0x00400000>; + }; + partition@5 { + label = "MAC-Address"; + reg = <0x007f0000 0x00010000>; + read-only; + }; + }; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; +}; + +&gpio { + status = "okay"; +}; + +/include/ "../../tps6507x.dtsi" + +&tps { + vdcdc1_2-supply = <&vbat>; + vdcdc3-supply = <&vbat>; + vldo1_2-supply = <&vbat>; + + regulators { + vdcdc1_reg: regulator@0 { + regulator-name = "VDCDC1_3.3V"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3450000>; + regulator-always-on; + regulator-boot-on; + }; + + vdcdc2_reg: regulator@1 { + regulator-name = "VDCDC2_3.3V"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3450000>; + regulator-always-on; + regulator-boot-on; + ti,defdcdc_default = <1>; + }; + + vdcdc3_reg: regulator@2 { + regulator-name = "VDCDC3_1.2V"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + ti,defdcdc_default = <1>; + }; + + ldo1_reg: regulator@3 { + regulator-name = "LDO1_1.8V"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "LDO2_1.2V"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1320000>; + regulator-always-on; + regulator-boot-on; + }; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 1 + 2 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&edma0 { + ti,edma-reserved-slot-ranges = <32 50>; +}; + +&edma1 { + ti,edma-reserved-slot-ranges = <32 90>; +}; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "okay"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&vpif { + pinctrl-names = "default"; + pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, disable the ti,tilcdc,panel then + * change the status below to 'okay' + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts new file mode 100644 index 000000000000..e379d6e7ad49 --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016 BayLibre, Inc. + */ +/dts-v1/; +#include "da850.dtsi" +#include +#include + +/ { + model = "DA850/AM1808/OMAP-L138 LCDK"; + compatible = "ti,da850-lcdk", "ti,da850"; + + aliases { + serial2 = &serial2; + ethernet0 = ð0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@c0000000 { + /* 128 MB DDR2 SDRAM @ 0xc0000000 */ + reg = <0xc0000000 0x08000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@c3000000 { + compatible = "shared-dma-pool"; + reg = <0xc3000000 0x1000000>; + reusable; + status = "okay"; + }; + }; + + vcc_5vd: fixedregulator-vcc_5vd { + compatible = "regulator-fixed"; + regulator-name = "vcc_5vd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vcc_3v3d: fixedregulator-vcc_3v3d { + /* TPS650250 - VDCDC1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5vd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_1v8d: fixedregulator-vcc_1v8d { + /* TPS650250 - VDCDC2 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5vd>; + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850-OMAPL138 LCDK"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + user1 { + label = "GPIO Key USER1"; + linux,code = ; + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + }; + + user2 { + label = "GPIO Key USER2"; + linux,code = ; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; + }; + + vga-bridge { + compatible = "ti,ths8135"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&lcdc_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + ddc-i2c-bus = <&i2c0>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + cvdd: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "cvdd"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&ref_clk { + clock-frequency = <24000000>; +}; + +&cpu { + cpu-supply = <&cvdd>; +}; + +/* + * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are + * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we + * can't enable more than one OPP by default, since the controller sometimes + * becomes unresponsive after a transition. Fix the frequency at 456 MHz. + */ + +&opp_100 { + status = "disabled"; +}; + +&opp_200 { + status = "disabled"; +}; + +&opp_300 { + status = "disabled"; +}; + +&opp_456 { + status = "okay"; +}; + +&pmx_core { + status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* AHCLKX AFSX ACLKX */ + 0x00 0x00101010 0x00f0f0f0 + /* ARX13 ARX14 */ + 0x04 0x00000110 0x00000ff0 + >; + }; + + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ + 0x1c 0x10110010 0xf0ff00f0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* + * EMA_D[8], EMA_D[9], EMA_D[10], + * EMA_D[11], EMA_D[12], EMA_D[13], + * EMA_D[14], EMA_D[15] + */ + 0x20 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; +}; + +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&sata_refclk { + status = "okay"; + clock-frequency = <100000000>; +}; + +&sata { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + status = "okay"; +}; + +&mmc0 { + max-frequency = <50000000>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&vcc_3v3d>; + AVDD-supply = <&vcc_3v3d>; + DRVDD-supply = <&vcc_3v3d>; + DVDD-supply = <&vcc_1v8d>; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 1 2 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "okay"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + + ti,davinci-nand-buswidth = <16>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + + /* + * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: + * "To boot from NAND Flash, the AIS should be written + * to NAND block 1 (NAND block 0 is not used by default)". + * The same doc mentions that for ROM "Silicon Revision 2.1", + * "Updated NAND boot mode to offer boot from block 0 or block 1". + * However the limitaion is left here by default for compatibility + * with older silicon and because it needs new boot pin settings + * not possible in stock LCDK. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot env"; + reg = <0 0x020000>; + }; + partition@20000 { + /* The LCDK defaults to booting from this partition */ + label = "u-boot"; + reg = <0x020000 0x080000>; + }; + partition@a0000 { + label = "free space"; + reg = <0x0a0000 0>; + }; + }; + }; + }; +}; + +&prictrl { + status = "okay"; +}; + +&memctrl { + status = "okay"; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + port { + lcdc_out_vga: endpoint { + remote-endpoint = <&vga_bridge_in>; + }; + }; +}; + +&vpif { + pinctrl-names = "default"; + pinctrl-0 = <&vpif_capture_pins>; + status = "okay"; +}; + +&dsp { + memory-region = <&dsp_memory_region>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts new file mode 100644 index 000000000000..afd04a423856 --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device tree for LEGO MINDSTORMS EV3 + * + * Copyright (C) 2017 David Lechner + */ + +/dts-v1/; +#include +#include +#include + +#include "da850.dtsi" + +/ { + compatible = "lego,ev3", "ti,da850"; + model = "LEGO MINDSTORMS EV3"; + + aliases { + serial1 = &serial1; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x04000000>; + }; + + /* + * The buttons on the EV3 are mapped to keyboard keys. + */ + gpio_keys { + compatible = "gpio-keys"; + label = "EV3 Brick Buttons"; + pinctrl-names = "default"; + pinctrl-0 = <&button_bias>; + + center { + label = "Center"; + linux,code = ; + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + left { + label = "Left"; + linux,code = ; + gpios = <&gpio 102 GPIO_ACTIVE_HIGH>; + }; + + back { + label = "Back"; + linux,code = ; + gpios = <&gpio 106 GPIO_ACTIVE_HIGH>; + }; + + right { + label = "Right"; + linux,code = ; + gpios = <&gpio 124 GPIO_ACTIVE_HIGH>; + }; + + down { + label = "Down"; + linux,code = ; + gpios = <&gpio 126 GPIO_ACTIVE_HIGH>; + }; + + up { + label = "Up"; + linux,code = ; + gpios = <&gpio 127 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * The EV3 has two built-in bi-color LEDs behind the buttons. + */ + leds { + compatible = "gpio-leds"; + + left_green { + label = "led0:green:brick-status"; + /* GP6[13] */ + gpios = <&gpio 103 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + right_red { + label = "led1:red:brick-status"; + /* GP6[7] */ + gpios = <&gpio 108 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + left_red { + label = "led0:red:brick-status"; + /* GP6[12] */ + gpios = <&gpio 109 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + right_green { + label = "led1:green:brick-status"; + /* GP6[14] */ + gpios = <&gpio 110 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + /* + * The EV3 is powered down by turning off the main 5V supply. + */ + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 107 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "pwm-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm0b_pins>; + pwms = <&ehrpwm0 1 1000000 0>; + amp-supply = <&>; + }; + + cvdd: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "cvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * This is a 5V current limiting regulator that is shared by USB, + * the sensor (input) ports, the motor (output) ports and the A/DC. + */ + vcc5v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 101 0>; + over-current-gpios = <&gpio 99 GPIO_ACTIVE_LOW>; + enable-active-high; + regulator-boot-on; + }; + + /* + * This is a simple voltage divider on VCC5V to provide a 2.5V + * reference signal to the ADC. + */ + adc_ref: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "adc ref"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + vin-supply = <&vcc5v>; + }; + + /* + * This is the amplifier for the speaker. + */ + amp: regulator3 { + compatible = "regulator-fixed"; + regulator-name = "amp"; + gpio = <&gpio 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* + * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack. + */ + battery { + compatible = "lego,ev3-battery"; + io-channels = <&adc 4>, <&adc 3>; + io-channel-names = "voltage", "current"; + rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; + }; + + bt_slow_clk: bt-clock { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>; + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&ecap2 0 30518 0>; + }; + + /* ARM local RAM */ + memory@ffff0000 { + compatible = "syscon", "simple-mfd"; + reg = <0xffff0000 0x2000>; /* 8k */ + + /* + * The I2C bootloader looks for this magic value to either + * boot normally or boot into a firmware update mode. + */ + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x1ffc>; + mode-normal = <0x00000000>; + mode-loader = <0x5555aaaa>; + }; + }; +}; + +&ref_clk { + clock-frequency = <24000000>; +}; + +&cpu { + cpu-supply = <&cvdd>; +}; + +/* since we have a fixed regulator, we can't run at these points */ +&opp_100 { + status = "disabled"; +}; + +&opp_200 { + status = "disabled"; +}; + +/* + * The SoC is actually the 456MHz version, but because of the fixed regulator + * This is the fastest we can go. + */ +&opp_375 { + status = "okay"; +}; + +&pmx_core { + status = "okay"; + + ev3_lcd_pins: pinmux_lcd { + pinctrl-single,bits = < + /* SIMO, CLK */ + 0x14 0x00100100 0x00f00f00 + >; + }; +}; + +&pinconf { + status = "okay"; + + /* Buttons have external pulldown resistors */ + button_bias: button-bias-groups { + disable { + groups = "cp5", "cp24", "cp25", "cp28"; + bias-disable; + }; + }; + + bt_clock_bias: bt-clock-bias-groups { + disable { + groups = "cp2"; + bias-disable; + }; + }; + + bt_pic_bias: bt-pic-bias-groups { + disable { + groups = "cp20"; + bias-disable; + }; + }; +}; + +/* Input port 1 */ +&serial1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&serial1_rxtx_pins>; +}; + +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>; + status = "okay"; + + bluetooth { + compatible = "ti,cc2560"; + clocks = <&bt_slow_clk>; + clock-names = "ext_clock"; + enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + nvmem-cells = <&bdaddr>; + nvmem-cell-names = "bd-address"; + }; +}; + +&rtc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + /* + * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC. + */ + eeprom@50 { + compatible = "microchip,24c128", "atmel,24c128"; + pagesize = <64>; + read-only; + reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + bdaddr: bdaddr@3f06 { + reg = <0x3f06 0x06>; + }; + }; +}; + +&wdt { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + max-frequency = <50000000>; + bus-width = <4>; + cd-gpios = <&gpio 94 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>; + + flash@0 { + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + ti,spi-wdelay = <8>; + + /* Partitions are based on the official firmware from LEGO */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x40000>; + }; + + partition@40000 { + label = "U-Boot Env"; + reg = <0x40000 0x10000>; + }; + + partition@50000 { + label = "Kernel"; + reg = <0x50000 0x200000>; + }; + + partition@250000 { + label = "Filesystem"; + reg = <0x250000 0xa50000>; + }; + + partition@cb0000 { + label = "Storage"; + reg = <0xcb0000 0x2f0000>; + }; + }; + }; + + adc: adc@3 { + compatible = "ti,ads7957"; + reg = <3>; + #io-channel-cells = <1>; + spi-max-frequency = <1000000>; + ti,spi-wdelay = <63>; + vref-supply = <&adc_ref>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&ev3_lcd_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + + display@0{ + compatible = "lego,ev3-lcd"; + reg = <0>; + spi-max-frequency = <10000000>; + a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; + }; +}; + +&ecap2 { + status = "okay"; +}; + +&ehrpwm0 { + status = "okay"; +}; + +&gpio { + status = "okay"; + + /* Don't pull down battery voltage adc io channel */ + batt_volt_en { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + }; + + /* Don't impede Bluetooth clock signal */ + bt_clock_en { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + }; + + /* + * There is a PIC microcontroller for interfacing with an Apple MFi + * chip. This interferes with normal Bluetooth operation, so we need + * to make sure it is turned off. Note: The publicly available + * schematics from LEGO don't show that these pins are connected to + * anything, but they are present in the source code from LEGO. + */ + + bt_pic_en { + gpio-hog; + gpios = <51 GPIO_ACTIVE_HIGH>; + output-low; + }; + + bt_pic_rst { + gpio-hog; + gpios = <78 GPIO_ACTIVE_HIGH>; + output-high; + }; + + bt_pic_cts { + gpio-hog; + gpios = <87 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&vcc5v>; +}; diff --git a/arch/arm/boot/dts/ti/davinci/da850.dtsi b/arch/arm/boot/dts/ti/davinci/da850.dtsi new file mode 100644 index 000000000000..e46e4d22db39 --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/da850.dtsi @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 DENX Software Engineering GmbH + * Heiko Schocher + */ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + clocks = <&psc0 14>; + operating-points-v2 = <&opp_table>; + }; + }; + + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp_100: opp100-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000 950000 1050000>; + }; + + opp_200: opp110-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000 1050000 1160000>; + }; + + opp_300: opp120-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1200000 1140000 1320000>; + }; + + /* + * Original silicon was 300MHz max, so higher frequencies + * need to be enabled on a per-board basis if the chip is + * capable. + */ + + opp_375: opp120-375000000 { + status = "disabled"; + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <1200000 1140000 1320000>; + }; + + opp_456: opp130-456000000 { + status = "disabled"; + opp-hz = /bits/ 64 <456000000>; + opp-microvolt = <1300000 1250000 1350000>; + }; + }; + + arm { + #address-cells = <1>; + #size-cells = <1>; + ranges; + intc: interrupt-controller@fffee000 { + compatible = "ti,cp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <101>; + reg = <0xfffee000 0x2000>; + }; + }; + clocks: clocks { + ref_clk: ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref_clk"; + }; + sata_refclk: sata_refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sata_refclk"; + status = "disabled"; + }; + usb_refclkin: usb_refclkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "usb_refclkin"; + status = "disabled"; + }; + }; + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + clocks = <&psc0 15>; + resets = <&psc0 15>; + status = "disabled"; + }; + soc@1c00000 { + compatible = "simple-bus"; + model = "da850"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x01c00000 0x400000>; + interrupt-parent = <&intc>; + + psc0: clock-controller@10000 { + compatible = "ti,da850-psc0"; + reg = <0x10000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, + <&pll0_sysclk 4>, <&pll0_sysclk 6>, + <&async1_clk>; + clock-names = "pll0_sysclk1", "pll0_sysclk2", + "pll0_sysclk4", "pll0_sysclk6", + "async1"; + }; + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>, <&pll1_sysclk 3>; + clock-names = "clksrc", "extclksrc"; + + pll0_pllout: pllout { + #clock-cells = <0>; + }; + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + pll0_auxclk: auxclk { + #clock-cells = <0>; + }; + pll0_obsclk: obsclk { + #clock-cells = <0>; + }; + }; + pmx_core: pinmux@14120 { + compatible = "pinctrl-single"; + reg = <0x14120 0x50>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xf>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 17 0x8>, + <&range 17 8 0x4>, + <&range 26 8 0x4>, + <&range 34 80 0x8>, + <&range 129 31 0x8>; + status = "disabled"; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + serial0_rtscts_pins: pinmux_serial0_rtscts_pins { + pinctrl-single,bits = < + /* UART0_RTS UART0_CTS */ + 0x0c 0x22000000 0xff000000 + >; + }; + serial0_rxtx_pins: pinmux_serial0_rxtx_pins { + pinctrl-single,bits = < + /* UART0_TXD UART0_RXD */ + 0x0c 0x00220000 0x00ff0000 + >; + }; + serial1_rtscts_pins: pinmux_serial1_rtscts_pins { + pinctrl-single,bits = < + /* UART1_CTS UART1_RTS */ + 0x00 0x00440000 0x00ff0000 + >; + }; + serial1_rxtx_pins: pinmux_serial1_rxtx_pins { + pinctrl-single,bits = < + /* UART1_TXD UART1_RXD */ + 0x10 0x22000000 0xff000000 + >; + }; + serial2_rtscts_pins: pinmux_serial2_rtscts_pins { + pinctrl-single,bits = < + /* UART2_CTS UART2_RTS */ + 0x00 0x44000000 0xff000000 + >; + }; + serial2_rxtx_pins: pinmux_serial2_rxtx_pins { + pinctrl-single,bits = < + /* UART2_TXD UART2_RXD */ + 0x10 0x00220000 0x00ff0000 + >; + }; + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,bits = < + /* I2C0_SDA,I2C0_SCL */ + 0x10 0x00002200 0x0000ff00 + >; + }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,bits = < + /* I2C1_SDA, I2C1_SCL */ + 0x10 0x00440000 0x00ff0000 + >; + }; + mmc0_pins: pinmux_mmc_pins { + pinctrl-single,bits = < + /* MMCSD0_DAT[3] MMCSD0_DAT[2] + * MMCSD0_DAT[1] MMCSD0_DAT[0] + * MMCSD0_CMD MMCSD0_CLK + */ + 0x28 0x00222222 0x00ffffff + >; + }; + ehrpwm0a_pins: pinmux_ehrpwm0a_pins { + pinctrl-single,bits = < + /* EPWM0A */ + 0xc 0x00000002 0x0000000f + >; + }; + ehrpwm0b_pins: pinmux_ehrpwm0b_pins { + pinctrl-single,bits = < + /* EPWM0B */ + 0xc 0x00000020 0x000000f0 + >; + }; + ehrpwm1a_pins: pinmux_ehrpwm1a_pins { + pinctrl-single,bits = < + /* EPWM1A */ + 0x14 0x00000002 0x0000000f + >; + }; + ehrpwm1b_pins: pinmux_ehrpwm1b_pins { + pinctrl-single,bits = < + /* EPWM1B */ + 0x14 0x00000020 0x000000f0 + >; + }; + ecap0_pins: pinmux_ecap0_pins { + pinctrl-single,bits = < + /* ECAP0_APWM0 */ + 0x8 0x20000000 0xf0000000 + >; + }; + ecap1_pins: pinmux_ecap1_pins { + pinctrl-single,bits = < + /* ECAP1_APWM1 */ + 0x4 0x40000000 0xf0000000 + >; + }; + ecap2_pins: pinmux_ecap2_pins { + pinctrl-single,bits = < + /* ECAP2_APWM2 */ + 0x4 0x00000004 0x0000000f + >; + }; + spi0_pins: pinmux_spi0_pins { + pinctrl-single,bits = < + /* SIMO, SOMI, CLK */ + 0xc 0x00001101 0x0000ff0f + >; + }; + spi0_cs0_pin: pinmux_spi0_cs0 { + pinctrl-single,bits = < + /* CS0 */ + 0x10 0x00000010 0x000000f0 + >; + }; + spi0_cs3_pin: pinmux_spi0_cs3_pin { + pinctrl-single,bits = < + /* CS3 */ + 0xc 0x01000000 0x0f000000 + >; + }; + spi1_pins: pinmux_spi1_pins { + pinctrl-single,bits = < + /* SIMO, SOMI, CLK */ + 0x14 0x00110100 0x00ff0f00 + >; + }; + spi1_cs0_pin: pinmux_spi1_cs0 { + pinctrl-single,bits = < + /* CS0 */ + 0x14 0x00000010 0x000000f0 + >; + }; + mdio_pins: pinmux_mdio_pins { + pinctrl-single,bits = < + /* MDIO_CLK, MDIO_D */ + 0x10 0x00000088 0x000000ff + >; + }; + mii_pins: pinmux_mii_pins { + pinctrl-single,bits = < + /* + * MII_TXEN, MII_TXCLK, MII_COL + * MII_TXD_3, MII_TXD_2, MII_TXD_1 + * MII_TXD_0 + */ + 0x8 0x88888880 0xfffffff0 + /* + * MII_RXER, MII_CRS, MII_RXCLK + * MII_RXDV, MII_RXD_3, MII_RXD_2 + * MII_RXD_1, MII_RXD_0 + */ + 0xc 0x88888888 0xffffffff + >; + }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,bits = < + /* + * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], + * LCD_D[6], LCD_D[7] + */ + 0x40 0x22222200 0xffffff00 + /* + * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], + * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] + */ + 0x44 0x22222222 0xffffffff + /* LCD_D[8], LCD_D[9] */ + 0x48 0x00000022 0x000000ff + + /* LCD_PCLK */ + 0x48 0x02000000 0x0f000000 + /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ + 0x4c 0x02000022 0x0f0000ff + >; + }; + vpif_capture_pins: vpif_capture_pins { + pinctrl-single,bits = < + /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ + 0x38 0x11111111 0xffffffff + /* VP_DIN[10..15,0..1] */ + 0x3c 0x11111111 0xffffffff + /* VP_DIN[8..9] */ + 0x40 0x00000011 0x000000ff + >; + }; + vpif_display_pins: vpif_display_pins { + pinctrl-single,bits = < + /* VP_DOUT[2..7] */ + 0x40 0x11111100 0xffffff00 + /* VP_DOUT[10..15,0..1] */ + 0x44 0x11111111 0xffffffff + /* VP_DOUT[8..9] */ + 0x48 0x00000011 0x000000ff + /* + * VP_CLKOUT3, VP_CLKIN3, + * VP_CLKOUT2, VP_CLKIN2 + */ + 0x4c 0x00111100 0x00ffff00 + >; + }; + }; + prictrl: priority-controller@14110 { + compatible = "ti,da850-mstpri"; + reg = <0x14110 0x0c>; + status = "disabled"; + }; + cfgchip: chip-controller@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + usb_phy: usb-phy { + compatible = "ti,da830-usb-phy"; + #phy-cells = <1>; + clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; + clock-names = "usb0_clk48", "usb1_clk48"; + status = "disabled"; + }; + usb_phy_clk: usb-phy-clocks { + compatible = "ti,da830-usb-phy-clocks"; + #clock-cells = <1>; + clocks = <&psc1 1>, <&usb_refclkin>, + <&pll0_auxclk>; + clock-names = "fck", "usb_refclkin", "auxclk"; + }; + ehrpwm_tbclk: ehrpwm_tbclk { + compatible = "ti,da830-tbclksync"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-names = "fck"; + }; + div4p5_clk: div4.5 { + compatible = "ti,da830-div4p5ena"; + #clock-cells = <0>; + clocks = <&pll0_pllout>; + clock-names = "pll0_pllout"; + }; + async1_clk: async1 { + compatible = "ti,da850-async1-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 3>, <&div4p5_clk>; + clock-names = "pll0_sysclk3", "div4.5"; + }; + async3_clk: async3 { + compatible = "ti,da850-async3-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + }; + }; + edma0: edma@0 { + compatible = "ti,edma3-tpcc"; + /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ + reg = <0x0 0x8000>; + reg-names = "edma3_cc"; + interrupts = <11 12>; + interrupt-names = "edma3_ccint", "edma3_ccerrint"; + #dma-cells = <2>; + + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + power-domains = <&psc0 0>; + }; + edma0_tptc0: tptc@8000 { + compatible = "ti,edma3-tptc"; + reg = <0x8000 0x400>; + interrupts = <13>; + interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 1>; + }; + edma0_tptc1: tptc@8400 { + compatible = "ti,edma3-tptc"; + reg = <0x8400 0x400>; + interrupts = <32>; + interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 2>; + }; + edma1: edma@230000 { + compatible = "ti,edma3-tpcc"; + /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ + reg = <0x230000 0x8000>; + reg-names = "edma3_cc"; + interrupts = <93 94>; + interrupt-names = "edma3_ccint", "edma3_ccerrint"; + #dma-cells = <2>; + + ti,tptcs = <&edma1_tptc0 7>; + power-domains = <&psc1 0>; + }; + edma1_tptc0: tptc@238000 { + compatible = "ti,edma3-tptc"; + reg = <0x238000 0x400>; + interrupts = <95>; + interrupt-names = "edm3_tcerrint"; + power-domains = <&psc1 21>; + }; + serial0: serial@42000 { + compatible = "ti,da830-uart", "ns16550a"; + reg = <0x42000 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <25>; + clocks = <&psc0 9>; + power-domains = <&psc0 9>; + status = "disabled"; + }; + serial1: serial@10c000 { + compatible = "ti,da830-uart", "ns16550a"; + reg = <0x10c000 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <53>; + clocks = <&psc1 12>; + power-domains = <&psc1 12>; + status = "disabled"; + }; + serial2: serial@10d000 { + compatible = "ti,da830-uart", "ns16550a"; + reg = <0x10d000 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <61>; + clocks = <&psc1 13>; + power-domains = <&psc1 13>; + status = "disabled"; + }; + rtc0: rtc@23000 { + compatible = "ti,da830-rtc"; + reg = <0x23000 0x1000>; + interrupts = <19 + 19>; + clocks = <&pll0_auxclk>; + clock-names = "int-clk"; + status = "disabled"; + }; + i2c0: i2c@22000 { + compatible = "ti,davinci-i2c"; + reg = <0x22000 0x1000>; + interrupts = <15>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pll0_auxclk>; + status = "disabled"; + }; + i2c1: i2c@228000 { + compatible = "ti,davinci-i2c"; + reg = <0x228000 0x1000>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&psc1 11>; + power-domains = <&psc1 11>; + status = "disabled"; + }; + clocksource: timer@20000 { + compatible = "ti,da830-timer"; + reg = <0x20000 0x1000>; + interrupts = <21>, <22>; + interrupt-names = "tint12", "tint34"; + clocks = <&pll0_auxclk>; + }; + wdt: wdt@21000 { + compatible = "ti,davinci-wdt"; + reg = <0x21000 0x1000>; + clocks = <&pll0_auxclk>; + status = "disabled"; + }; + mmc0: mmc@40000 { + compatible = "ti,da830-mmc"; + reg = <0x40000 0x1000>; + cap-sd-highspeed; + cap-mmc-highspeed; + interrupts = <16>; + dmas = <&edma0 16 0>, <&edma0 17 0>; + dma-names = "rx", "tx"; + clocks = <&psc0 5>; + status = "disabled"; + }; + vpif: video@217000 { + compatible = "ti,da850-vpif"; + reg = <0x217000 0x1000>; + interrupts = <92>; + power-domains = <&psc1 9>; + status = "disabled"; + + /* VPIF capture port */ + port@0 { + #address-cells = <1>; + #size-cells = <0>; + }; + + /* VPIF display port */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mmc1: mmc@21b000 { + compatible = "ti,da830-mmc"; + reg = <0x21b000 0x1000>; + cap-sd-highspeed; + cap-mmc-highspeed; + interrupts = <72>; + dmas = <&edma1 28 0>, <&edma1 29 0>; + dma-names = "rx", "tx"; + clocks = <&psc1 18>; + status = "disabled"; + }; + ehrpwm0: pwm@300000 { + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x300000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; + status = "disabled"; + }; + ehrpwm1: pwm@302000 { + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x302000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; + status = "disabled"; + }; + ecap0: pwm@306000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x306000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; + status = "disabled"; + }; + ecap1: pwm@307000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x307000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; + status = "disabled"; + }; + ecap2: pwm@308000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x308000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; + status = "disabled"; + }; + spi0: spi@41000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,da830-spi"; + reg = <0x41000 0x1000>; + num-cs = <6>; + ti,davinci-spi-intr-line = <1>; + interrupts = <20>; + dmas = <&edma0 14 0>, <&edma0 15 0>; + dma-names = "rx", "tx"; + clocks = <&psc0 4>; + power-domains = <&psc0 4>; + status = "disabled"; + }; + spi1: spi@30e000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,da830-spi"; + reg = <0x30e000 0x1000>; + num-cs = <4>; + ti,davinci-spi-intr-line = <1>; + interrupts = <56>; + dmas = <&edma0 18 0>, <&edma0 19 0>; + dma-names = "rx", "tx"; + clocks = <&psc1 10>; + power-domains = <&psc1 10>; + status = "disabled"; + }; + usb0: usb@200000 { + compatible = "ti,da830-musb"; + reg = <0x200000 0x1000>; + ranges; + interrupts = <58>; + interrupt-names = "mc"; + dr_mode = "otg"; + phys = <&usb_phy 0>; + phy-names = "usb-phy"; + clocks = <&psc1 1>; + clock-ranges; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 0 1 &cppi41dma 1 1 + &cppi41dma 2 1 &cppi41dma 3 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", + "tx1", "tx2", "tx3", "tx4"; + + cppi41dma: dma-controller@201000 { + compatible = "ti,da830-cppi41"; + reg = <0x201000 0x1000 + 0x202000 0x1000 + 0x204000 0x4000>; + reg-names = "controller", + "scheduler", "queuemgr"; + interrupts = <58>; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <4>; + dma-channels = <4>; + power-domains = <&psc1 1>; + status = "okay"; + }; + }; + sata: sata@218000 { + compatible = "ti,da850-ahci"; + reg = <0x218000 0x2000>, <0x22c018 0x4>; + interrupts = <67>; + clocks = <&psc1 8>, <&sata_refclk>; + clock-names = "fck", "refclk"; + status = "disabled"; + }; + pll1: clock-controller@21a000 { + compatible = "ti,da850-pll1"; + reg = <0x21a000 0x1000>; + clocks = <&ref_clk>; + clock-names = "clksrc"; + + pll1_sysclk: sysclk { + #clock-cells = <1>; + }; + pll1_obsclk: obsclk { + #clock-cells = <0>; + }; + }; + mdio: mdio@224000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x224000 0x1000>; + clocks = <&psc1 5>; + clock-names = "fck"; + power-domains = <&psc1 5>; + status = "disabled"; + }; + eth0: ethernet@220000 { + compatible = "ti,davinci-dm6467-emac"; + reg = <0x220000 0x4000>; + ti,davinci-ctrl-reg-offset = <0x3000>; + ti,davinci-ctrl-mod-reg-offset = <0x2000>; + ti,davinci-ctrl-ram-offset = <0>; + ti,davinci-ctrl-ram-size = <0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <33 + 34 + 35 + 36 + >; + clocks = <&psc1 5>; + power-domains = <&psc1 5>; + status = "disabled"; + }; + usb1: usb@225000 { + compatible = "ti,da830-ohci"; + reg = <0x225000 0x1000>; + interrupts = <59>; + phys = <&usb_phy 1>; + phy-names = "usb-phy"; + clocks = <&psc1 2>; + status = "disabled"; + }; + gpio: gpio@226000 { + compatible = "ti,dm6441-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x226000 0x1000>; + interrupts = <42 43 44 45 46 47 48 49 50>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&psc1 3>; + clock-names = "gpio"; + status = "disabled"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pmx_core 0 15 1>, + <&pmx_core 1 14 1>, + <&pmx_core 2 13 1>, + <&pmx_core 3 12 1>, + <&pmx_core 4 11 1>, + <&pmx_core 5 10 1>, + <&pmx_core 6 9 1>, + <&pmx_core 7 8 1>, + <&pmx_core 8 7 1>, + <&pmx_core 9 6 1>, + <&pmx_core 10 5 1>, + <&pmx_core 11 4 1>, + <&pmx_core 12 3 1>, + <&pmx_core 13 2 1>, + <&pmx_core 14 1 1>, + <&pmx_core 15 0 1>, + <&pmx_core 16 39 1>, + <&pmx_core 17 38 1>, + <&pmx_core 18 37 1>, + <&pmx_core 19 36 1>, + <&pmx_core 20 35 1>, + <&pmx_core 21 34 1>, + <&pmx_core 22 33 1>, + <&pmx_core 23 32 1>, + <&pmx_core 24 24 1>, + <&pmx_core 25 22 1>, + <&pmx_core 26 21 1>, + <&pmx_core 27 20 1>, + <&pmx_core 28 19 1>, + <&pmx_core 29 18 1>, + <&pmx_core 30 17 1>, + <&pmx_core 31 16 1>, + <&pmx_core 32 55 1>, + <&pmx_core 33 54 1>, + <&pmx_core 34 53 1>, + <&pmx_core 35 52 1>, + <&pmx_core 36 51 1>, + <&pmx_core 37 50 1>, + <&pmx_core 38 49 1>, + <&pmx_core 39 48 1>, + <&pmx_core 40 47 1>, + <&pmx_core 41 46 1>, + <&pmx_core 42 45 1>, + <&pmx_core 43 44 1>, + <&pmx_core 44 43 1>, + <&pmx_core 45 42 1>, + <&pmx_core 46 41 1>, + <&pmx_core 47 40 1>, + <&pmx_core 48 71 1>, + <&pmx_core 49 70 1>, + <&pmx_core 50 69 1>, + <&pmx_core 51 68 1>, + <&pmx_core 52 67 1>, + <&pmx_core 53 66 1>, + <&pmx_core 54 65 1>, + <&pmx_core 55 64 1>, + <&pmx_core 56 63 1>, + <&pmx_core 57 62 1>, + <&pmx_core 58 61 1>, + <&pmx_core 59 60 1>, + <&pmx_core 60 59 1>, + <&pmx_core 61 58 1>, + <&pmx_core 62 57 1>, + <&pmx_core 63 56 1>, + <&pmx_core 64 87 1>, + <&pmx_core 65 86 1>, + <&pmx_core 66 85 1>, + <&pmx_core 67 84 1>, + <&pmx_core 68 83 1>, + <&pmx_core 69 82 1>, + <&pmx_core 70 81 1>, + <&pmx_core 71 80 1>, + <&pmx_core 72 70 1>, + <&pmx_core 73 78 1>, + <&pmx_core 74 77 1>, + <&pmx_core 75 76 1>, + <&pmx_core 76 75 1>, + <&pmx_core 77 74 1>, + <&pmx_core 78 73 1>, + <&pmx_core 79 72 1>, + <&pmx_core 80 103 1>, + <&pmx_core 81 102 1>, + <&pmx_core 82 101 1>, + <&pmx_core 83 100 1>, + <&pmx_core 84 99 1>, + <&pmx_core 85 98 1>, + <&pmx_core 86 97 1>, + <&pmx_core 87 96 1>, + <&pmx_core 88 95 1>, + <&pmx_core 89 94 1>, + <&pmx_core 90 93 1>, + <&pmx_core 91 92 1>, + <&pmx_core 92 91 1>, + <&pmx_core 93 90 1>, + <&pmx_core 94 89 1>, + <&pmx_core 95 88 1>, + <&pmx_core 96 158 1>, + <&pmx_core 97 157 1>, + <&pmx_core 98 156 1>, + <&pmx_core 99 155 1>, + <&pmx_core 100 154 1>, + <&pmx_core 101 129 1>, + <&pmx_core 102 113 1>, + <&pmx_core 103 112 1>, + <&pmx_core 104 111 1>, + <&pmx_core 105 110 1>, + <&pmx_core 106 109 1>, + <&pmx_core 107 108 1>, + <&pmx_core 108 107 1>, + <&pmx_core 109 106 1>, + <&pmx_core 110 105 1>, + <&pmx_core 111 104 1>, + <&pmx_core 112 145 1>, + <&pmx_core 113 144 1>, + <&pmx_core 114 143 1>, + <&pmx_core 115 142 1>, + <&pmx_core 116 141 1>, + <&pmx_core 117 140 1>, + <&pmx_core 118 139 1>, + <&pmx_core 119 138 1>, + <&pmx_core 120 137 1>, + <&pmx_core 121 136 1>, + <&pmx_core 122 135 1>, + <&pmx_core 123 134 1>, + <&pmx_core 124 133 1>, + <&pmx_core 125 132 1>, + <&pmx_core 126 131 1>, + <&pmx_core 127 130 1>, + <&pmx_core 128 159 1>, + <&pmx_core 129 31 1>, + <&pmx_core 130 30 1>, + <&pmx_core 131 20 1>, + <&pmx_core 132 28 1>, + <&pmx_core 133 27 1>, + <&pmx_core 134 26 1>, + <&pmx_core 135 23 1>, + <&pmx_core 136 153 1>, + <&pmx_core 137 152 1>, + <&pmx_core 138 151 1>, + <&pmx_core 139 150 1>, + <&pmx_core 140 149 1>, + <&pmx_core 141 148 1>, + <&pmx_core 142 147 1>, + <&pmx_core 143 146 1>; + }; + psc1: clock-controller@227000 { + compatible = "ti,da850-psc1"; + reg = <0x227000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, + <&async3_clk>; + clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; + assigned-clocks = <&async3_clk>; + assigned-clock-parents = <&pll1_sysclk 2>; + }; + pinconf: pin-controller@22c00c { + compatible = "ti,da850-pupd"; + reg = <0x22c00c 0x8>; + status = "disabled"; + }; + + mcasp0: mcasp@100000 { + compatible = "ti,da830-mcasp-audio"; + reg = <0x100000 0x2000>, + <0x102000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <54>; + interrupt-names = "common"; + power-domains = <&psc1 7>; + status = "disabled"; + dmas = <&edma0 1 1>, + <&edma0 0 1>; + dma-names = "tx", "rx"; + }; + + lcdc: display@213000 { + compatible = "ti,da850-tilcdc"; + reg = <0x213000 0x1000>; + interrupts = <52>; + max-pixelclock = <37500>; + clocks = <&psc1 16>; + clock-names = "fck"; + power-domains = <&psc1 16>; + status = "disabled"; + }; + }; + aemif: aemif@68000000 { + compatible = "ti,da850-aemif"; + #address-cells = <2>; + #size-cells = <1>; + + reg = <0x68000000 0x00008000>; + ranges = <0 0 0x60000000 0x08000000 + 1 0 0x68000000 0x00008000>; + clocks = <&psc0 3>; + clock-names = "aemif"; + clock-ranges; + status = "disabled"; + }; + memctrl: memory-controller@b0000000 { + compatible = "ti,da850-ddr-controller"; + reg = <0xb0000000 0xe8>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/Makefile b/arch/arm/boot/dts/ti/keystone/Makefile new file mode 100644 index 000000000000..4b18d08fa57c --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_KEYSTONE) += \ + keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ + keystone-k2g-evm.dtb \ + keystone-k2g-ice.dtb diff --git a/arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi new file mode 100644 index 000000000000..0397c3423d2d --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Keystone 2 clock tree + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mainmuxclk: mainmuxclk@2310108 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-mux-clock"; + clocks = <&mainpllclk>, <&refclksys>; + reg = <0x02310108 4>; + bit-shift = <23>; + bit-mask = <1>; + clock-output-names = "mainmuxclk"; + }; + + chipclk1: chipclk1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mainmuxclk>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "chipclk1"; + }; + + chipclk1rstiso: chipclk1rstiso { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mainmuxclk>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso"; + }; + + gemtraceclk: gemtraceclk@2310120 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-divider-clock"; + clocks = <&mainmuxclk>; + reg = <0x02310120 4>; + bit-shift = <0>; + bit-mask = <8>; + clock-output-names = "gemtraceclk"; + }; + + chipstmxptclk: chipstmxptclk@2310164 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-divider-clock"; + clocks = <&mainmuxclk>; + reg = <0x02310164 4>; + bit-shift = <0>; + bit-mask = <8>; + clock-output-names = "chipstmxptclk"; + }; + + chipclk12: chipclk12 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "chipclk12"; + }; + + chipclk13: chipclk13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "chipclk13"; + }; + + paclk13: paclk13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&papllclk>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "paclk13"; + }; + + chipclk14: chipclk14 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "chipclk14"; + }; + + chipclk16: chipclk16 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "chipclk16"; + }; + + chipclk112: chipclk112 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "chipclk112"; + }; + + chipclk124: chipclk124 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "chipclk114"; + }; + + chipclk1rstiso13: chipclk1rstiso13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso13"; + }; + + chipclk1rstiso14: chipclk1rstiso14 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso14"; + }; + + chipclk1rstiso16: chipclk1rstiso16 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso16"; + }; + + chipclk1rstiso112: chipclk1rstiso112 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso112"; + }; + + clkmodrst0: clkmodrst0@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "modrst0"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + + clkusb: clkusb@2350008 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "usb"; + reg = <0x02350008 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkaemifspi: clkaemifspi@235000c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "aemif-spi"; + reg = <0x0235000c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + + clkdebugsstrc: clkdebugsstrc@2350014 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "debugss-trc"; + reg = <0x02350014 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <1>; + }; + + clktetbtrc: clktetbtrc@2350018 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tetb-trc"; + reg = <0x02350018 0xb00>, <0x02350004 0x400>; + reg-names = "control", "domain"; + domain-id = <1>; + }; + + clkpa: clkpa@235001c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&paclk13>; + clock-output-names = "pa"; + reg = <0x0235001c 0xb00>, <0x02350008 0x400>; + reg-names = "control", "domain"; + domain-id = <2>; + }; + + clkcpgmac: clkcpgmac@2350020 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkpa>; + clock-output-names = "cpgmac"; + reg = <0x02350020 0xb00>, <0x02350008 0x400>; + reg-names = "control", "domain"; + domain-id = <2>; + }; + + clksa: clksa@2350024 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkpa>; + clock-output-names = "sa"; + reg = <0x02350024 0xb00>, <0x02350008 0x400>; + reg-names = "control", "domain"; + domain-id = <2>; + }; + + clkpcie: clkpcie@2350028 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x02350028 0xb00>, <0x0235000c 0x400>; + reg-names = "control", "domain"; + domain-id = <3>; + }; + + clksr: clksr@2350034 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1rstiso112>; + clock-output-names = "sr"; + reg = <0x02350034 0xb00>, <0x02350018 0x400>; + reg-names = "control", "domain"; + domain-id = <6>; + }; + + clkgem0: clkgem0@235003c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem0"; + reg = <0x0235003c 0xb00>, <0x02350020 0x400>; + reg-names = "control", "domain"; + domain-id = <8>; + }; + + clkddr30: clkddr30@235005c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "ddr3-0"; + reg = <0x0235005c 0xb00>, <0x02350040 0x400>; + reg-names = "control", "domain"; + domain-id = <16>; + }; + + clkwdtimer0: clkwdtimer0@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer0"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkwdtimer1: clkwdtimer1@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer1"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkwdtimer2: clkwdtimer2@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer2"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkwdtimer3: clkwdtimer3@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer3"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clktimer15: clktimer15@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer15"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart0: clkuart0@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart0"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart1: clkuart1@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart1"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkaemif: clkaemif@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkaemifspi>; + clock-output-names = "aemif"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkusim: clkusim@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "usim"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clki2c: clki2c@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "i2c"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkspi: clkspi@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkaemifspi>; + clock-output-names = "spi"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkgpio: clkgpio@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "gpio"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkkeymgr: clkkeymgr@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "keymgr"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + /* + * Below are set of fixed, input clocks definitions, + * for which real frequencies have to be defined in board files. + * Those clocks can be used as reference clocks for some HW modules + * (as cpts, for example) by configuring corresponding clock muxes. + */ + timi0: timi0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "timi0"; + }; + + timi1: timi1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "timi1"; + }; + + tsrefclk: tsrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "tsrefclk"; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi new file mode 100644 index 000000000000..cf30e007fea3 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Edison SoC specific device tree + * + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +clocks { + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkusb1: clkusb1@2350004 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "usb1"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkhyperlink0: clkhyperlink0@2350030 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkpcie1: clkpcie1@235006c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie1"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkxge: clkxge@23500c8 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; + + /* + * Below are set of fixed, input clocks definitions, + * for which real frequencies have to be defined in board files. + * Those clocks can be used as reference clocks for some HW modules + * (as cpts, for example) by configuring corresponding clock muxes. + */ + tsipclka: tsipclka { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "tsipclka"; + }; + + tsipclkb: tsipclkb { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "tsipclkb"; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts new file mode 100644 index 000000000000..6978d6a362f3 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Edison EVM device tree + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "keystone-k2e.dtsi" + +/ { + compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; + model = "Texas Instruments Keystone 2 Edison EVM"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_memory: dsp-common-memory@81f800000 { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + status = "okay"; + }; + }; +}; + +&soc0 { + + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-pass"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1_phy { + status = "okay"; +}; + +&keystone_usb1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; +}; + +&i2c0 { + eeprom@50 { + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1fe80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&dsp0 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi new file mode 100644 index 000000000000..bff73a0ed10b --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Keystone 2 Edison Netcp driver + * + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + accumulator { + acc-low-0 { + qrange = <480 32>; + accumulator = <0 47 16 2 50>; + interrupts = <0 226 0xf01>; + multi-queue; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; + + pdsps { + #address-cells = <1>; + #size-cells = <1>; + ranges; + pdsp0@2a10000 { + reg = <0x2a10000 0x1000 /*iram */ + 0x2a0f000 0x100 /*reg*/ + 0x2a0c000 0x3c8 /*intd */ + 0x2a20000 0x4000>; /*cmd*/ + id = <0>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x24186000 0x100>, + <0x24187000 0x2a0>, + <0x24188000 0xb60>, + <0x24186100 0x80>, + <0x24189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@24000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x24000000 0x1000000>; + + clocks = <&clkpa>, <&clkcpgmac>; + clock-names = "pa_clk", "ethss_clk"; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-9"; + reg = <0x200000 0x900>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + + cpts { + clocks = <&cpts_refclk_mux>; + clock-names = "cpts"; + + cpts_refclk_mux: cpts-refclk-mux { + #clock-cells = <0>; + clocks = <&chipclk12>, <&chipclk13>, + <&timi0>, <&timi1>, + <&tsipclka>, <&tsrefclk>, + <&tsipclkb>; + ti,mux-tbl = <0x0>, <0x1>, <0x2>, + <0x3>, <0x4>, <0x8>, <0xc>; + assigned-clocks = <&cpts_refclk_mux>; + assigned-clock-parents = <&chipclk12>; + }; + }; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + port-4 { + slave-port = <4>; + link-interface = <2>; + }; + port-5 { + slave-port = <5>; + link-interface = <2>; + }; + port-6 { + slave-port = <6>; + link-interface = <2>; + }; + port-7 { + slave-port = <7>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 00]; + netcp-gbe = <&gbe1>; + }; + }; +}; + +sa_subsys: subsys@24080000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x24080000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi new file mode 100644 index 000000000000..65c32946c522 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Edison soc device tree + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include + +/ { + compatible = "ti,k2e", "ti,keystone"; + model = "Texas Instruments Keystone 2 Edison SoC"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + aliases { + rproc0 = &dsp0; + }; +}; + +&soc0 { + /include/ "keystone-k2e-clocks.dtsi" + + usb: usb@2680000 { + interrupts = ; + usb@2690000 { + interrupts = ; + }; + }; + + usb1_phy: usb_phy@2620750 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620750 24>; + status = "disabled"; + }; + + keystone_usb1: usb@25000000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x25000000 0x10000>; + clocks = <&clkusb1>; + clock-names = "usb"; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + + usb1: usb@25010000 { + compatible = "snps,dwc3"; + reg = <0x25010000 0x70000>; + interrupts = ; + usb-phy = <&usb1_phy>, <&usb1_phy>; + }; + }; + + msm_ram: sram@c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x200000>; + ranges = <0x0 0x0c000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + + bm-sram@1f0000 { + reg = <0x001f0000 0x8000>; + }; + }; + + psc: power-sleep-controller@2350000 { + pscrst: reset-controller { + compatible = "ti,k2e-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + >; + }; + }; + + devctrl: device-state-control@2620000 { + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + }; + + dsp0: dsp@10800000 { + compatible = "ti,k2e-dsp"; + reg = <0x10800000 0x00080000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x844>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio0 27 0>; + status = "disabled"; + }; + + pcie1: pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + ranges = <0x82000000 0 0x60000000 0x60000000 + 0 0x10000000>; + + status = "disabled"; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x00 0xff>; + + /* error interrupt */ + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ + <0 0 0 2 &pcie_intc1 1>, /* INT B */ + <0 0 0 3 &pcie_intc1 2>, /* INT C */ + <0 0 0 4 &pcie_intc1 3>; /* INT D */ + + pcie_msi_intc1: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc1: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + mdio: mdio@24200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x24200f00 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "keystone-k2e-netcp.dtsi" +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts new file mode 100644 index 000000000000..7bfc80f1af26 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for K2G EVM + * + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "keystone-k2g.dtsi" + +/ { + compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; + model = "Texas Instruments K2G General Purpose EVM"; + + memory@800000000 { + device_type = "memory"; + reg = <0x00000008 0x00000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_memory: dsp-common-memory@81f800000 { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + status = "okay"; + }; + }; + + vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { + compatible = "regulator-fixed"; + regulator-name = "mmc0_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { + compatible = "regulator-fixed"; + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 { + compatible = "regulator-fixed"; + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + aud_mclk: aud_mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "K2G-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + bitclock-master = <&sound0_0_master>; + frame-master = <&sound0_0_master>; + sound0_0_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks 0x6 1>; + system-clock-direction-out; + }; + + codec { + sound-dai = <&tlv320aic3106>; + clocks = <&aud_mclk>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master = <&sound0_1_master>; + frame-master = <&sound0_1_master>; + sound0_1_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks 0x6 1>; + system-clock-direction-out; + }; + + codec { + sound-dai = <&sii9022>; + clocks = <&aud_mclk>; + }; + }; + }; +}; + +&k2g_pinctrl { + uart0_pins: uart0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + mmc0_pins: mmc0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ + K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ + K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ + K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ + K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ + K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ + K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ + K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ + K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ + K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ + K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + ecap0_pins: ecap0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ + >; + }; + + spi1_pins: spi1-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ + K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ + K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ + K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ + >; + }; + + qspi_pins: qspi-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ + K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ + K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ + K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ + K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ + K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ + K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ + K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ + >; + }; + + dcan0_pins: dcan0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ + K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ + >; + }; + + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ + K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ + >; + }; + + emac_pins: emac-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ + K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ + K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ + K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ + K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ + K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ + K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ + >; + }; + + mdio_pins: mdio-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ + >; + }; + + vout_pins: vout-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ + K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ + K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ + K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ + K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ + K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ + K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ + K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ + K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ + K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ + K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ + K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ + K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ + K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ + K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ + K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ + K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ + K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ + K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ + K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ + K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ + K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ + K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ + K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ + K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ + >; + }; + + mcasp2_pins: mcasp2-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ + K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ + K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */ + K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&vcc3v3_dcin_reg>; + vqmmc-supply = <&vcc3v3_dcin_reg>; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ + vqmmc-supply = <&vcc1v8_ldo1_reg>; + ti,non-removable; + status = "okay"; +}; + +&dsp0 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&keystone_usb1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <5000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x100000 0xf00000>; + }; + }; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + cdns,rclk-en; + + flash0: flash@0 { + compatible = "s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + cdns,read-delay = <5>; + cdns,tshsl-ns = <500>; + cdns,tsd2d-ns = <500>; + cdns,tchsh-ns = <119>; + cdns,tslch-ns = <119>; + + partition@0 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001c0000 0x0800000>; + }; + partition@5 { + label = "QSPI.file-system"; + reg = <0x009c0000 0x3640000>; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&qmss { + status = "okay"; +}; + +&knav_dmas { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&netcp { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + sil,i2s-data-lanes = < 0 >; + clocks = <&aud_mclk>; + clock-names = "mclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vcc3v3_dcin_reg>; + IOVDD-supply = <&vcc3v3_dcin_reg>; + DRVDD-supply = <&vcc3v3_dcin_reg>; + DVDD-supply = <&vcc1v8_ldo2_reg>; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&vout_pins>; + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; + }; + }; +}; + +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcasp2_pins>; + + assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>; + assigned-clock-parents = <0>, <&k2g_clks 0x6 2>; + assigned-clock-rates = <22579200>, <0>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 6 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 0 0 // AXR2: TX, AXR3: rx + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts new file mode 100644 index 000000000000..6ceb0d5c6388 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for K2G Industrial Communication Engine EVM + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "keystone-k2g.dtsi" +#include + +/ { + compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; + model = "Texas Instruments K2G Industrial Communication EVM"; + + memory@800000000 { + device_type = "memory"; + reg = <0x00000008 0x00000000 0x00000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_memory: dsp-common-memory@81f800000 { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + status = "okay"; + }; + }; + + vmain: fixedregulator-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain_fixed"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; + + v5_0: fixedregulator-v5_0 { + /* TPS54531 */ + compatible = "regulator-fixed"; + regulator-name = "v5_0_fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain>; + regulator-always-on; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + /* TLV62084 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vdd_1v8: fixedregulator-vdd_1v8 { + /* TLV62084 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vdds_ddr: fixedregulator-vdds_ddr { + /* TLV62080 */ + compatible = "regulator-fixed"; + regulator-name = "vdds_ddr_fixed"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vref_ddr: fixedregulator-vref_ddr { + /* LP2996A */ + compatible = "regulator-fixed"; + regulator-name = "vref_ddr_fixed"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + vtt_ddr: fixedregulator-vtt_ddr { + /* LP2996A */ + compatible = "regulator-fixed"; + regulator-name = "vtt_ddr_fixed"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + vdd_0v9: fixedregulator-vdd_0v9 { + /* TPS62180 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_fixed"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&v5_0>; + regulator-always-on; + }; + + vddb: fixedregulator-vddb { + /* TPS22945 */ + compatible = "regulator-fixed"; + regulator-name = "vddb_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-decoder { + compatible = "gpio-decoder"; + gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, + <&pca9536 2 GPIO_ACTIVE_HIGH>, + <&pca9536 1 GPIO_ACTIVE_HIGH>, + <&pca9536 0 GPIO_ACTIVE_HIGH>; + linux,axis = <0>; /* ABS_X */ + decoder-max-value = <9>; + }; + + leds1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led1 { + label = "status0:green:usr"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "status0:yellow:usr"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "status1:red:mmc0"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led4 { + label = "status1:green:usr"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led6 { + label = "status2:red:usr"; + gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led7 { + label = "status2:green:usr"; + gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led8 { + label = "status2:yellow:usr"; + gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led9 { + label = "status3:red:usr"; + gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led10 { + label = "status3:green:usr"; + gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led11 { + label = "status3:yellow:usr"; + gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led12 { + label = "status4:green:heartbeat"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&k2g_pinctrl { + uart0_pins: uart0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + qspi_pins: qspi-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ + K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ + K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ + K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ + K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ + K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ + K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ + K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ + K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + user_leds: user-leds-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ + K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ + K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */ + K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */ + K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */ + K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */ + K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */ + K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */ + K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ + >; + }; + + emac_pins: emac-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ + K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ + K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ + K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ + K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ + K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ + K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ + >; + }; + + mdio_pins: mdio-pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&dsp0 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + cdns,rclk-en; + status = "okay"; + + flash0: flash@0 { + compatible = "s25fl256s1", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + cdns,read-delay = <5>; + cdns,tshsl-ns = <500>; + cdns,tsd2d-ns = <500>; + cdns,tchsh-ns = <119>; + cdns,tslch-ns = <119>; + + partition@0 { + label = "QSPI.u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001c0000 0x0800000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x009c0000 0x0040000>; + }; + partition@6 { + label = "QSPI.file-system"; + reg = <0x00a00000 0x1600000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vdd_3v3>; + cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + pca9536: gpio@41 { + compatible = "ti,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_3v3>; + }; +}; + +&qmss { + status = "okay"; +}; + +&knav_dmas { + status = "okay"; +}; + +&netcp { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi new file mode 100644 index 000000000000..f6306933ff42 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for K2G Netcp driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +qmss: qmss@4020000 { + compatible = "ti,66ak2g-navss-qm"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 0>; + clock-names = "nss_vclk"; + ranges; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; + status = "disabled"; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x80>; + reg = <0x4100000 0x800>, + <0x4040000 0x100>, + <0x4080000 0x800>, + <0x40c0000 0x800>; + reg-names = "peek", "config", + "region", "push"; + }; + + }; + queue-pools { + qpend { + qpend-0 { + qrange = <77 8>; + interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 + 0 311 0xf04 0 312 0xf04 0 313 0xf04 + 0 314 0xf04 0 315 0xf04>; + qalloc-by-id; + }; + }; + general-purpose { + gp-0 { + qrange = <112 8>; + }; + netcp-tx { + qrange = <5 8>; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <1023 128>; /* num_desc desc_size */ + link-index = <0x400>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 0>; + clock-names = "nss_vclk"; + ranges; + ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x4010000 0x100>, + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; + +}; + +netcp: netcp@4000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>; + clock-names = "ethss_clk", "cpts"; + + /* NetCP address range */ + ranges = <0 0x4000000 0x1000000>; + + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; + ti,navigator-dma-names = "netrx0", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe: gbe@200000 { + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-2"; + reg = <0x200000 0x20>, <0x220000 0x20000>; + enable-ale; + tx-queue = <5>; + tx-channel = "nettx"; + cpts-rftclk-sel = <0>; + cpts-ext-ts-inputs = <8>; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <5>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <512 12>; + tx-pool = <511 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <77>; + tx-completion-queue = <78>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi new file mode 100644 index 000000000000..102d59694d90 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for K2G SOC + * + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include + +/ { + compatible = "ti,k2g","ti,keystone"; + model = "Texas Instruments K2G SoC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + chosen { }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + rproc0 = &dsp0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + }; + + gic: interrupt-controller@2561000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>, + <0x0 0x02564000 0x0 0x2000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = ; + }; + + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + usb0_phy: usb-phy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + status = "disabled"; + }; + + usb1_phy: usb-phy@1 { + compatible = "usb-nop-xceiv"; + reg = <1>; + status = "disabled"; + }; + }; + + soc0: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + compatible = "ti,keystone","simple-bus"; + ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; + + msm_ram: sram@c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x100000>; + ranges = <0x0 0x0c000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + + bm-sram@f7000 { + reg = <0x000f7000 0x8000>; + }; + }; + + k2g_pinctrl: pinmux@2621000 { + compatible = "pinctrl-single"; + reg = <0x02621000 0x410>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x001b0007>; + }; + + devctrl: device-state-control@2620000 { + compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; + reg = <0x02620000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x02620000 0x1000>; + + kirq0: keystone_irq@2a0 { + compatible = "ti,keystone-irq"; + reg = <0x2a0 0x10>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + }; + + uart0: serial@2530c00 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + interrupts = ; + clocks = <&k2g_clks 0x2c 0>; + power-domains = <&k2g_pds 0x2c>; + status = "disabled"; + }; + + uart1: serial@2531000 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + interrupts = ; + clocks = <&k2g_clks 0x2d 0>; + power-domains = <&k2g_pds 0x2d>; + status = "disabled"; + }; + + uart2: serial@2531400 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531400 0x100>; + interrupts = ; + clocks = <&k2g_clks 0x2e 0>; + power-domains = <&k2g_pds 0x2e>; + status = "disabled"; + }; + + dcan0: can@260b200 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0260b200 0x200>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds 0x0008>; + clocks = <&k2g_clks 0x0008 1>; + }; + + dcan1: can@260b400 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0260b400 0x200>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds 0x0009>; + clocks = <&k2g_clks 0x0009 1>; + }; + + i2c0: i2c@2530000 { + compatible = "ti,keystone-i2c"; + reg = <0x02530000 0x400>; + clocks = <&k2g_clks 0x003a 0>; + power-domains = <&k2g_pds 0x003a>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2530400 { + compatible = "ti,keystone-i2c"; + reg = <0x02530400 0x400>; + clocks = <&k2g_clks 0x003b 0>; + power-domains = <&k2g_pds 0x003b>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@2530800 { + compatible = "ti,keystone-i2c"; + reg = <0x02530800 0x400>; + clocks = <&k2g_clks 0x003c 0>; + power-domains = <&k2g_pds 0x003c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dsp0: dsp@10800000 { + compatible = "ti,k2g-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + power-domains = <&k2g_pds 0x0046>; + ti,syscon-dev = <&devctrl 0x844>; + resets = <&k2g_reset 0x0046 0x1>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio0 27 0>; + status = "disabled"; + }; + + msgmgr: mailbox@2a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; + reg-names = "queue_proxy_region", + "queue_state_debug_region"; + reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; + interrupt-names = "rx_005", + "rx_057"; + interrupts = , + ; + }; + + pmmc: system-controller@2921c00 { + compatible = "ti,k2g-sci"; + /* + * In case of rare platforms that does not use k2g as + * system master, use /delete-property/ + */ + ti,system-reboot-controller; + mbox-names = "rx", "tx"; + mboxes = <&msgmgr 5 2>, + <&msgmgr 0 0>; + reg-names = "debug_messages"; + reg = <0x02921c00 0x400>; + + k2g_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <1>; + }; + + k2g_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k2g_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + gpio0: gpio@2603000 { + compatible = "ti,k2g-gpio", "ti,keystone-gpio"; + reg = <0x02603000 0x100>; + gpio-controller; + #gpio-cells = <2>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k2g_clks 0x001b 0x0>; + clock-names = "gpio"; + }; + + gpio1: gpio@260a000 { + compatible = "ti,k2g-gpio", "ti,keystone-gpio"; + reg = <0x0260a000 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <68>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k2g_clks 0x001c 0x0>; + clock-names = "gpio"; + }; + + dss: dss@02540000 { + compatible = "ti,k2g-dss"; + reg = <0x02540000 0x400>, + <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; + clocks = <&k2g_clks 0x2 0>, + <&k2g_clks 0x2 1>; + clock-names = "fck", "vp1"; + interrupts = ; + + power-domains = <&k2g_pds 0x2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + max-memory-bandwidth = <230000000>; + }; + + edma0: edma@2700000 { + compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; + reg = <0x02700000 0x8000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + + ti,edma-memcpy-channels = <32 33 34 35>; + + power-domains = <&k2g_pds 0x3f>; + }; + + edma0_tptc0: tptc@2760000 { + compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; + reg = <0x02760000 0x400>; + power-domains = <&k2g_pds 0x3f>; + }; + + edma0_tptc1: tptc@2768000 { + compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; + reg = <0x02768000 0x400>; + power-domains = <&k2g_pds 0x3f>; + }; + + edma1: edma@2728000 { + compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; + reg = <0x02728000 0x8000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; + + /* + * memcpy is disabled, can be enabled with: + * ti,edma-memcpy-channels = <12 13 14 15>; + * for example. + */ + + power-domains = <&k2g_pds 0x4f>; + }; + + edma1_tptc0: tptc@27b0000 { + compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; + reg = <0x027b0000 0x400>; + power-domains = <&k2g_pds 0x4f>; + }; + + edma1_tptc1: tptc@27b8000 { + compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; + reg = <0x027b8000 0x400>; + power-domains = <&k2g_pds 0x4f>; + }; + + mmc0: mmc@23000000 { + compatible = "ti,k2g-sdhci"; + reg = <0x23000000 0x400>; + interrupts = ; + bus-width = <4>; + no-1-8-v; + max-frequency = <96000000>; + power-domains = <&k2g_pds 0xb>; + clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; + clock-names = "fck", "mmchsdb_fck"; + status = "disabled"; + }; + + mmc1: mmc@23100000 { + compatible = "ti,k2g-sdhci"; + reg = <0x23100000 0x400>; + interrupts = ; + bus-width = <8>; + no-1-8-v; + non-removable; + max-frequency = <96000000>; + power-domains = <&k2g_pds 0xc>; + clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; + clock-names = "fck", "mmchsdb_fck"; + }; + + qspi: spi@2940000 { + compatible = "ti,k2g-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02940000 0x1000>, + <0x24000000 0x4000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x24000000>; + clocks = <&k2g_clks 0x43 0x0>; + power-domains = <&k2g_pds 0x43>; + status = "disabled"; + }; + + mcasp0: mcasp@2340000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02340000 0x2000>, + <0x21804000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma0 24 1>, <&edma0 25 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x4>; + clocks = <&k2g_clks 0x4 0>; + clock-names = "fck"; + status = "disabled"; + }; + + mcasp1: mcasp@2342000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02342000 0x2000>, + <0x21804400 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma1 48 1>, <&edma1 49 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x5>; + clocks = <&k2g_clks 0x5 0>; + clock-names = "fck"; + status = "disabled"; + }; + + mcasp2: mcasp@2344000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02344000 0x2000>, + <0x21804800 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma1 50 1>, <&edma1 51 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x6>; + clocks = <&k2g_clks 0x6 0>; + clock-names = "fck"; + status = "disabled"; + }; + + keystone_usb0: keystone-dwc3@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds 0x0016>; + + usb0: usb@2690000 { + compatible = "snps,dwc3"; + reg = <0x2690000 0x10000>; + interrupts = ; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb0_phy>; + status = "disabled"; + }; + }; + + keystone_usb1: keystone-dwc3@2580000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2580000 0x10000>; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds 0x0017>; + + usb1: usb@2590000 { + compatible = "snps,dwc3"; + reg = <0x2590000 0x10000>; + interrupts = ; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb1_phy>; + status = "disabled"; + }; + }; + + ecap0: pwm@21d1800 { + compatible = "ti,k2g-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x021d1800 0x60>; + power-domains = <&k2g_pds 0x38>; + clocks = <&k2g_clks 0x38 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@21d1c00 { + compatible = "ti,k2g-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x021d1c00 0x60>; + power-domains = <&k2g_pds 0x39>; + clocks = <&k2g_clks 0x39 0x0>; + clock-names = "fck"; + status = "disabled"; + }; + + spi0: spi@21805400 { + compatible = "ti,keystone-spi"; + reg = <0x21805400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0010>; + clocks = <&k2g_clks 0x0010 0>; + }; + + spi1: spi@21805800 { + compatible = "ti,keystone-spi"; + reg = <0x21805800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0011>; + clocks = <&k2g_clks 0x0011 0>; + }; + + spi2: spi@21805c00 { + compatible = "ti,keystone-spi"; + reg = <0x21805c00 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0012>; + clocks = <&k2g_clks 0x0012 0>; + }; + + spi3: spi@21806000 { + compatible = "ti,keystone-spi"; + reg = <0x21806000 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0013>; + clocks = <&k2g_clks 0x0013 0>; + }; + + wdt: wdt@02250000 { + compatible = "ti,keystone-wdt", "ti,davinci-wdt"; + reg = <0x02250000 0x80>; + power-domains = <&k2g_pds 0x22>; + clocks = <&k2g_clks 0x22 0>; + }; + + emif: emif@21010000 { + compatible = "ti,emif-keystone"; + reg = <0x21010000 0x200>; + interrupts = ; + }; + + mdio: mdio@4200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + reg = <0x04200f00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k2g_clks 0x0018 3>; + clock-names = "fck"; + power-domains = <&k2g_pds 0x0018>; + status = "disabled"; + bus_freq = <2500000>; + }; + #include "keystone-k2g-netcp.dtsi" + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi new file mode 100644 index 000000000000..4ba6912176ef --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Kepler/Hawking SoC clock nodes + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkarm>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + ddr3bpllclk: ddr3bpllclk@2620368 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3b>; + clock-output-names = "ddr-3b-pll-clk"; + reg = <0x02620368 4>; + reg-names = "control"; + }; + + clktsip: clktsip@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "tsip"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clksrio: clksrio@235002c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1rstiso13>; + clock-output-names = "srio"; + reg = <0x0235002c 0xb00>, <0x02350010 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkhyperlink0: clkhyperlink0@2350030 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkgem1: clkgem1@2350040 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2@2350044 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3@2350048 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clkgem4: clkgem4@235004c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem4"; + reg = <0x0235004c 0xb00>, <0x02350030 0x400>; + reg-names = "control", "domain"; + domain-id = <12>; + }; + + clkgem5: clkgem5@2350050 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem5"; + reg = <0x02350050 0xb00>, <0x02350034 0x400>; + reg-names = "control", "domain"; + domain-id = <13>; + }; + + clkgem6: clkgem6@2350054 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem6"; + reg = <0x02350054 0xb00>, <0x02350038 0x400>; + reg-names = "control", "domain"; + domain-id = <14>; + }; + + clkgem7: clkgem7@2350058 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem7"; + reg = <0x02350058 0xb00>, <0x0235003c 0x400>; + reg-names = "control", "domain"; + domain-id = <15>; + }; + + clkddr31: clkddr31@2350060 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "ddr3-1"; + reg = <0x02350060 0xb00>, <0x02350040 0x400>; + reg-names = "control", "domain"; + domain-id = <16>; + }; + + clktac: clktac@2350064 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac01: clkrac01@2350068 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-01"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac23: clkrac23@235006c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-23"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0@2350070 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc1: clkfftc1@2350074 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x02350074 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc2: clkfftc2@2350078 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-2"; + reg = <0x02350078 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc3: clkfftc3@235007c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-3"; + reg = <0x0235007c 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc4: clkfftc4@2350080 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-4"; + reg = <0x02350080 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc5: clkfftc5@2350084 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-5"; + reg = <0x02350084 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkaif: clkaif@2350088 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "aif"; + reg = <0x02350088 0xb00>, <0x02350054 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0@235008c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1@2350090 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350090 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d2: clktcp3d2@2350094 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-2"; + reg = <0x02350094 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clktcp3d3: clktcp3d3@2350098 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-3"; + reg = <0x02350098 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0@235009c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1@23500a0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2@23500a4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3@23500a8 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp4: clkvcp4@23500ac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-4"; + reg = <0x023500ac 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp5: clkvcp5@23500b0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-5"; + reg = <0x023500b0 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp6: clkvcp6@23500b4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-6"; + reg = <0x023500b4 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp7: clkvcp7@23500b8 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-7"; + reg = <0x023500b8 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkbcp: clkbcp@23500bc { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdxb: clkdxb@23500c0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dxb"; + reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkhyperlink1: clkhyperlink1@23500c4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-1"; + reg = <0x023500c4 0xb00>, <0x02350070 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkxge: clkxge@23500c8 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts new file mode 100644 index 000000000000..206df8a8d9dd --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Kepler/Hawking EVM device tree + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "keystone-k2hk.dtsi" + +/ { + compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_memory: dsp-common-memory@81f800000 { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + led-debug-1-1 { + label = "keystone:green:debug1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ + }; + + led-debug-1-2 { + label = "keystone:red:debug1"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ + }; + + led-debug-2 { + label = "keystone:blue:debug2"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ + }; + + led-debug-3 { + label = "keystone:blue:debug3"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ + }; + }; +}; + +&soc0 { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-pass"; + }; + + refclkarm: refclkarm { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "refclk-arm"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + + refclkddr3b: refclkddr3b { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3b"; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1fe80000>; + }; + }; + }; +}; + +&i2c0 { + eeprom@50 { + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + +&spi0 { + nor_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&dsp0 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp1 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp2 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp3 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp4 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp5 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp6 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp7 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi new file mode 100644 index 000000000000..8a421c65f920 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Keystone 2 Hawking Netcp driver + * + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + + qmgr1 { + managed-queues = <0x2000 0x2000>; + reg = <0x2a60000 0x20000>, + <0x2a06400 0x400>, + <0x2a04000 0x1000>, + <0x2a05000 0x1000>, + <0x23aa0000 0x20000>, + <0x2aa0000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <8704 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <8720 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <640 9>; + qalloc-by-id; + }; + netcpx-tx { + qrange = <8752 8>; + qalloc-by-id; + }; + }; + accumulator { + acc-low-0 { + qrange = <480 32>; + accumulator = <0 47 16 2 50>; + interrupts = <0 226 0xf01>; + multi-queue; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; + + pdsps { + #address-cells = <1>; + #size-cells = <1>; + ranges; + pdsp0@2a10000 { + reg = <0x2a10000 0x1000 /*iram */ + 0x2a0f000 0x100 /*reg*/ + 0x2a0c000 0x3c8 /*intd */ + 0x2a20000 0x4000>; /*cmd*/ + id = <0>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23aa0000 0x23ab0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x2004000 0x100>, + <0x2004400 0x120>, + <0x2004800 0x300>, + <0x2004c00 0x120>, + <0x2005000 0x400>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@2000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x2000000 0x100000>; + + clocks = <&clkpa>, <&clkcpgmac>; + clock-names = "pa_clk", "ethss_clk"; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 22>, + <&dma_gbe 23>, + <&dma_gbe 8>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + ranges; + #address-cells = <1>; + #size-cells = <1>; + gbe@90000 { /* ETHSS */ + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-gbe"; + compatible = "ti,netcp-gbe"; + reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; + /* enable-ale; */ + tx-queue = <648>; + tx-channel = "nettx"; + + cpts { + clocks = <&cpts_refclk_mux>; + clock-names = "cpts"; + + cpts_refclk_mux: cpts-refclk-mux { + #clock-cells = <0>; + clocks = <&chipclk12>, <&chipclk13>, + <&timi0>, <&timi1>, + <&tsrefclk>; + ti,mux-tbl = <0x0>, <0x1>, <0x2>, + <0x3>, <0x8>; + assigned-clocks = <&cpts_refclk_mux>; + assigned-clock-parents = <&chipclk12>; + }; + }; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8704>; + tx-completion-queue = <8706>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8705>; + tx-completion-queue = <8707>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 6f]; + netcp-gbe = <&gbe1>; + }; + }; +}; + +sa_subsys: subsys@20c0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x20c0000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi new file mode 100644 index 000000000000..da6d3934c2e8 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Kepler/Hawking soc specific device tree + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include + +/ { + compatible = "ti,k2hk", "ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + aliases { + rproc0 = &dsp0; + rproc1 = &dsp1; + rproc2 = &dsp2; + rproc3 = &dsp3; + rproc4 = &dsp4; + rproc5 = &dsp5; + rproc6 = &dsp6; + rproc7 = &dsp7; + }; +}; + +&soc0 { + /include/ "keystone-k2hk-clocks.dtsi" + + msm_ram: sram@c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x600000>; + ranges = <0x0 0x0c000000 0x600000>; + #address-cells = <1>; + #size-cells = <1>; + + bm-sram@5f0000 { + reg = <0x5f0000 0x8000>; + }; + }; + + psc: power-sleep-controller@2350000 { + pscrst: reset-controller { + compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ + 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ + 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ + 0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */ + 0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */ + 0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */ + 0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */ + >; + }; + }; + + devctrl: device-state-control@2620000 { + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@244 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x244 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@248 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x248 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@24c { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x24c 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + dspgpio4: keystone_dsp_gpio@250 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x250 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x250>; + }; + + dspgpio5: keystone_dsp_gpio@254 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x254 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x254>; + }; + + dspgpio6: keystone_dsp_gpio@258 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x258 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x258>; + }; + + dspgpio7: keystone_dsp_gpio@25c { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x25c 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x25c>; + }; + }; + + dsp0: dsp@10800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x40>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio0 27 0>; + status = "disabled"; + }; + + dsp1: dsp@11800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x11800000 0x00100000>, + <0x11e00000 0x00008000>, + <0x11f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem1>; + ti,syscon-dev = <&devctrl 0x44>; + resets = <&pscrst 1>; + interrupt-parent = <&kirq0>; + interrupts = <1 9>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio1 27 0>; + status = "disabled"; + }; + + dsp2: dsp@12800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x12800000 0x00100000>, + <0x12e00000 0x00008000>, + <0x12f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem2>; + ti,syscon-dev = <&devctrl 0x48>; + resets = <&pscrst 2>; + interrupt-parent = <&kirq0>; + interrupts = <2 10>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio2 27 0>; + status = "disabled"; + }; + + dsp3: dsp@13800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x13800000 0x00100000>, + <0x13e00000 0x00008000>, + <0x13f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem3>; + ti,syscon-dev = <&devctrl 0x4c>; + resets = <&pscrst 3>; + interrupt-parent = <&kirq0>; + interrupts = <3 11>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio3 27 0>; + status = "disabled"; + }; + + dsp4: dsp@14800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x14800000 0x00100000>, + <0x14e00000 0x00008000>, + <0x14f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem4>; + ti,syscon-dev = <&devctrl 0x50>; + resets = <&pscrst 4>; + interrupt-parent = <&kirq0>; + interrupts = <4 12>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio4 27 0>; + status = "disabled"; + }; + + dsp5: dsp@15800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x15800000 0x00100000>, + <0x15e00000 0x00008000>, + <0x15f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem5>; + ti,syscon-dev = <&devctrl 0x54>; + resets = <&pscrst 5>; + interrupt-parent = <&kirq0>; + interrupts = <5 13>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio5 27 0>; + status = "disabled"; + }; + + dsp6: dsp@16800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x16800000 0x00100000>, + <0x16e00000 0x00008000>, + <0x16f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem6>; + ti,syscon-dev = <&devctrl 0x58>; + resets = <&pscrst 6>; + interrupt-parent = <&kirq0>; + interrupts = <6 14>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio6 27 0>; + status = "disabled"; + }; + + dsp7: dsp@17800000 { + compatible = "ti,k2hk-dsp"; + reg = <0x17800000 0x00100000>, + <0x17e00000 0x00008000>, + <0x17f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem7>; + ti,syscon-dev = <&devctrl 0x5c>; + resets = <&pscrst 7>; + interrupt-parent = <&kirq0>; + interrupts = <7 15>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio7 27 0>; + status = "disabled"; + }; + + mdio: mdio@2090300 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02090300 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "keystone-k2hk-netcp.dtsi" +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi new file mode 100644 index 000000000000..635528064dea --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 lamarr SoC clock nodes + * + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkdfeiqnsys: clkdfeiqnsys@2350004 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "dfe"; + reg-names = "control", "domain"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + domain-id = <0>; + }; + + clkpcie1: clkpcie1@235002c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x0235002c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkgem1: clkgem1@2350040 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2@2350044 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3@2350048 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clktac: clktac@2350064 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac: clkrac@2350068 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkdfepd0: clkdfepd0@235006c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd0"; + reg = <0x0235006c 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0@2350070 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkosr: clkosr@2350088 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "osr"; + reg = <0x02350088 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0@235008c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1@2350094 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350094 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0@235009c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1@23500a0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2@23500a4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3@23500a8 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkbcp: clkbcp@23500bc { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdfepd1: clkdfepd1@23500c0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd1"; + reg = <0x023500c0 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkfftc1: clkfftc1@23500c4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkiqnail: clkiqnail@23500c8 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "iqn-ail"; + reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; + + clkuart2: clkuart2@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart2"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart3: clkuart3@2350000 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart3"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts new file mode 100644 index 000000000000..be619e39a16f --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Lamarr EVM device tree + * + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "keystone-k2l.dtsi" + +/ { + compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr EVM"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_memory: dsp-common-memory@81f800000 { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + status = "okay"; + }; + }; +}; + +&soc0 { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; + +&i2c0 { + eeprom@50 { + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x7fe80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&dsp0 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp1 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp2 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; + +&dsp3 { + memory-region = <&dsp_common_memory>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi new file mode 100644 index 000000000000..5ec6680a533d --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Keystone 2 Lamarr Netcp driver + * + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + accumulator { + acc-low-0 { + qrange = <480 32>; + accumulator = <0 47 16 2 50>; + interrupts = <0 226 0xf01>; + multi-queue; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; + + pdsps { + #address-cells = <1>; + #size-cells = <1>; + ranges; + pdsp0@2a10000 { + reg = <0x2a10000 0x1000 /*iram */ + 0x2a0f000 0x100 /*reg*/ + 0x2a0c000 0x3c8 /*intd */ + 0x2a20000 0x4000>; /*cmd*/ + id = <0>; + }; + }; + +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x26186000 0x100>, + <0x26187000 0x2a0>, + <0x26188000 0xb60>, + <0x26186100 0x80>, + <0x26189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@26000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x26000000 0x1000000>; + + clocks = <&clkpa>, <&clkcpgmac>; + clock-names = "pa_clk", "ethss_clk"; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-5"; + reg = <0x200000 0x900>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + + cpts { + clocks = <&cpts_refclk_mux>; + clock-names = "cpts"; + + cpts_refclk_mux: cpts-refclk-mux { + #clock-cells = <0>; + clocks = <&chipclk12>, <&chipclk13>, + <&timi0>, <&timi1>, + <&tsrefclk>; + ti,mux-tbl = <0x0>, <0x1>, <0x2>, + <0x3>, <0x8>; + assigned-clocks = <&cpts_refclk_mux>; + assigned-clock-parents = <&chipclk12>; + }; + }; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 7f]; + netcp-gbe = <&gbe1>; + }; + }; +}; + +sa_subsys: subsys@26080000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x26080000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi new file mode 100644 index 000000000000..8949578e62e8 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Keystone 2 Lamarr SoC specific device tree + * + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include + +/ { + compatible = "ti,k2l", "ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr SoC"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + }; + + aliases { + rproc0 = &dsp0; + rproc1 = &dsp1; + rproc2 = &dsp2; + rproc3 = &dsp3; + }; +}; + +&soc0 { + /include/ "keystone-k2l-clocks.dtsi" + + uart2: serial@2348400 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348400 0x100>; + clocks = <&clkuart2>; + interrupts = ; + }; + + uart3: serial@2348800 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348800 0x100>; + clocks = <&clkuart3>; + interrupts = ; + }; + + gpio1: gpio@2348000 { + compatible = "ti,keystone-gpio"; + reg = <0x02348000 0x100>; + gpio-controller; + #gpio-cells = <2>; + /* HW Interrupts mapped to GPIO pins */ + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clkgpio>; + clock-names = "gpio"; + ti,ngpio = <32>; + ti,davinci-gpio-unbanked = <32>; + }; + + k2l_pmx: pinmux@2620690 { + compatible = "pinctrl-single"; + reg = <0x02620690 0xc>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1>; + status = "disabled"; + + uart3_emifa_pins: uart3-emifa-pins { + pinctrl-single,bits = < + /* UART3_EMIFA_SEL */ + 0x0 0x0 0xc0 + >; + }; + + uart2_emifa_pins: uart2-emifa-pins { + pinctrl-single,bits = < + /* UART2_EMIFA_SEL */ + 0x0 0x0 0x30 + >; + }; + + uart01_spi2_pins: uart01-spi2-pins { + pinctrl-single,bits = < + /* UART01_SPI2_SEL */ + 0x0 0x0 0x4 + >; + }; + + dfesync_rp1_pins: dfesync-rp1-pins{ + pinctrl-single,bits = < + /* DFESYNC_RP1_SEL */ + 0x0 0x0 0x2 + >; + }; + + avsif_pins: avsif-pins { + pinctrl-single,bits = < + /* AVSIF_SEL */ + 0x0 0x0 0x1 + >; + }; + + gpio_emu_pins: gpio-emu-pins { + pinctrl-single,bits = < + /* + * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 + * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 + * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 + * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 + * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 + * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 + * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 + * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 + * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 + * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 + * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 + * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 + * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 + * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 + * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 + */ + 0x4 0x0000 0xfffe0000 + >; + }; + + gpio_timio_pins: gpio-timio-pins { + pinctrl-single,bits = < + /* + * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 + * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 + * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 + * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 + * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 + * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 + * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 + * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 + * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 + * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 + * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 + * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 + */ + 0x4 0x0 0xfff0 + >; + }; + + gpio_spi2cs_pins: gpio-spi2cs-pins { + pinctrl-single,bits = < + /* + * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 + * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 + * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 + * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 + */ + 0x4 0x0 0xf + >; + }; + + gpio_dfeio_pins: gpio-dfeio-pins { + pinctrl-single,bits = < + /* + * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 + * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 + * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 + * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 + * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 + * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 + * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 + * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 + * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 + * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 + * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 + * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 + * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 + * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 + * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 + * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 + */ + 0x8 0x0 0xffff0000 + >; + }; + + gpio_emifa_pins: gpio-emifa-pins { + pinctrl-single,bits = < + /* + * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 + * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 + * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 + * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 + * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 + * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 + * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 + * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 + * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 + * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 + * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 + * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 + * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 + * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 + * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 + * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 + */ + 0x8 0x0 0xffff + >; + }; + }; + + msm_ram: sram@c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x200000>; + ranges = <0x0 0x0c000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + + bm-sram@1f8000 { + reg = <0x001f8000 0x8000>; + }; + }; + + psc: power-sleep-controller@2350000 { + pscrst: reset-controller { + compatible = "ti,k2l-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ + 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ + 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ + >; + }; + }; + + osr: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x70000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clkosr>; + }; + + devctrl: device-state-control@2620000 { + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@244 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x244 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@248 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x248 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@24c { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x24c 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + }; + + dsp0: dsp@10800000 { + compatible = "ti,k2l-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x844>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio0 27 0>; + status = "disabled"; + }; + + dsp1: dsp@11800000 { + compatible = "ti,k2l-dsp"; + reg = <0x11800000 0x00100000>, + <0x11e00000 0x00008000>, + <0x11f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem1>; + ti,syscon-dev = <&devctrl 0x848>; + resets = <&pscrst 1>; + interrupt-parent = <&kirq0>; + interrupts = <1 9>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio1 27 0>; + status = "disabled"; + }; + + dsp2: dsp@12800000 { + compatible = "ti,k2l-dsp"; + reg = <0x12800000 0x00100000>, + <0x12e00000 0x00008000>, + <0x12f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem2>; + ti,syscon-dev = <&devctrl 0x84c>; + resets = <&pscrst 2>; + interrupt-parent = <&kirq0>; + interrupts = <2 10>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio2 27 0>; + status = "disabled"; + }; + + dsp3: dsp@13800000 { + compatible = "ti,k2l-dsp"; + reg = <0x13800000 0x00100000>, + <0x13e00000 0x00008000>, + <0x13f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem3>; + ti,syscon-dev = <&devctrl 0x850>; + resets = <&pscrst 3>; + interrupt-parent = <&kirq0>; + interrupts = <3 11>; + interrupt-names = "vring", "exception"; + kick-gpios = <&dspgpio3 27 0>; + status = "disabled"; + }; + + mdio: mdio@26200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x26200f00 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "keystone-k2l-netcp.dtsi" +}; + +&spi0 { + ti,davinci-spi-num-cs = <5>; +}; + +&spi1 { + ti,davinci-spi-num-cs = <3>; +}; + +&spi2 { + ti,davinci-spi-num-cs = <5>; + /* Pin muxed. Enabled and configured by Bootloader */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/keystone/keystone.dtsi b/arch/arm/boot/dts/ti/keystone/keystone.dtsi new file mode 100644 index 000000000000..1fd04bb37a15 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/keystone.dtsi @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include + +/ { + compatible = "ti,keystone"; + model = "Texas Instruments Keystone 2 SoC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + chosen { }; + + memory: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + gic: interrupt-controller@2561000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>, + <0x0 0x02564000 0x0 0x2000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + + soc0: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; + + pllctrl: pll-controller@2310000 { + compatible = "ti,keystone-pllctrl", "syscon"; + reg = <0x02310000 0x200>; + }; + + psc: power-sleep-controller@2350000 { + compatible = "syscon", "simple-mfd"; + reg = <0x02350000 0x1000>; + }; + + devctrl: device-state-control@2620000 { + compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; + reg = <0x02620000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x02620000 0x1000>; + + kirq0: keystone_irq@2a0 { + compatible = "ti,keystone-irq"; + reg = <0x2a0 0x4>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + rstctrl: reset-controller@328 { + compatible = "ti,keystone-reset"; + reg = <0x328 0x10>; + ti,syscon-pll = <&pllctrl 0xe4>; + ti,syscon-dev = <&devctrl 0x328>; + ti,wdt-list = <0>; + }; + }; + + /include/ "keystone-clocks.dtsi" + + uart0: serial@2530c00 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clocks = <&clkuart0>; + interrupts = ; + }; + + uart1: serial@2531000 { + compatible = "ti,da830-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clocks = <&clkuart1>; + interrupts = ; + }; + + i2c0: i2c@2530000 { + compatible = "ti,davinci-i2c"; + reg = <0x02530000 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@2530400 { + compatible = "ti,davinci-i2c"; + reg = <0x02530400 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@2530800 { + compatible = "ti,davinci-i2c"; + reg = <0x02530800 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@21000400 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21000400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@21000600 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21000600 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@21000800 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21000800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_phy: usb_phy@2620738 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620738 24>; + status = "disabled"; + }; + + keystone_usb0: usb@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + clocks = <&clkusb>; + clock-names = "usb"; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + + usb0: usb@2690000 { + compatible = "snps,dwc3"; + reg = <0x2690000 0x70000>; + interrupts = ; + usb-phy = <&usb_phy>, <&usb_phy>; + }; + }; + + wdt: wdt@22f0080 { + compatible = "ti,keystone-wdt","ti,davinci-wdt"; + reg = <0x022f0080 0x80>; + clocks = <&clkwdtimer0>; + }; + + clock_event: timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = ; + clocks = <&clktimer15>; + }; + + gpio0: gpio@260bf00 { + compatible = "ti,keystone-gpio"; + reg = <0x0260bf00 0x100>; + gpio-controller; + #gpio-cells = <2>; + /* HW Interrupts mapped to GPIO pins */ + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clkgpio>; + clock-names = "gpio"; + ti,ngpio = <32>; + ti,davinci-gpio-unbanked = <32>; + }; + + aemif: aemif@21000a00 { + compatible = "ti,keystone-aemif", "ti,davinci-aemif"; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clkaemif>; + clock-names = "aemif"; + clock-ranges; + + reg = <0x21000a00 0x00000100>; + ranges = <0 0 0x30000000 0x10000000 + 1 0 0x21000a00 0x00000100>; + }; + + pcie0: pcie@21800000 { + compatible = "ti,keystone-pcie", "snps,dw-pcie"; + clocks = <&clkpcie>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + ranges = <0x82000000 0 0x50000000 0x50000000 + 0 0x10000000>; + + status = "disabled"; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x00 0xff>; + + /* error interrupt */ + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ + <0 0 0 2 &pcie_intc0 1>, /* INT B */ + <0 0 0 3 &pcie_intc0 2>, /* INT C */ + <0 0 0 4 &pcie_intc0 3>; /* INT D */ + + pcie_msi_intc0: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc0: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + emif: emif@21010000 { + compatible = "ti,emif-keystone"; + reg = <0x21010000 0x200>; + interrupts = ; + interrupt-parent = <&gic>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile new file mode 100644 index 000000000000..d2b590004fed --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_OMAP2) += \ + omap2420-h4.dtb \ + omap2420-n800.dtb \ + omap2420-n810.dtb \ + omap2420-n810-wimax.dtb \ + omap2430-sdp.dtb +dtb-$(CONFIG_ARCH_OMAP3) += \ + am3517-craneboard.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb \ + logicpd-torpedo-35xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit-28.dtb \ + logicpd-som-lv-35xx-devkit.dtb \ + logicpd-som-lv-37xx-devkit.dtb \ + omap3430-sdp.dtb \ + omap3-beagle.dtb \ + omap3-beagle-ab4.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle-xm-ab.dtb \ + omap3-cm-t3517.dtb \ + omap3-cm-t3530.dtb \ + omap3-cm-t3730.dtb \ + omap3-devkit8000.dtb \ + omap3-devkit8000-lcd43.dtb \ + omap3-devkit8000-lcd70.dtb \ + omap3-echo.dtb \ + omap3-evm.dtb \ + omap3-evm-37xx.dtb \ + omap3-gta04a3.dtb \ + omap3-gta04a4.dtb \ + omap3-gta04a5.dtb \ + omap3-gta04a5one.dtb \ + omap3-ha.dtb \ + omap3-ha-lcd.dtb \ + omap3-igep0020.dtb \ + omap3-igep0020-rev-f.dtb \ + omap3-igep0030.dtb \ + omap3-igep0030-rev-g.dtb \ + omap3-ldp.dtb \ + omap3-lilly-dbb056.dtb \ + omap3-n900.dtb \ + omap3-n9.dtb \ + omap3-n950.dtb \ + omap3-overo-alto35.dtb \ + omap3-overo-chestnut43.dtb \ + omap3-overo-gallop43.dtb \ + omap3-overo-palo35.dtb \ + omap3-overo-palo43.dtb \ + omap3-overo-storm-alto35.dtb \ + omap3-overo-storm-chestnut43.dtb \ + omap3-overo-storm-gallop43.dtb \ + omap3-overo-storm-palo35.dtb \ + omap3-overo-storm-palo43.dtb \ + omap3-overo-storm-summit.dtb \ + omap3-overo-storm-tobi.dtb \ + omap3-overo-storm-tobiduo.dtb \ + omap3-overo-summit.dtb \ + omap3-overo-tobi.dtb \ + omap3-overo-tobiduo.dtb \ + omap3-pandora-600mhz.dtb \ + omap3-pandora-1ghz.dtb \ + omap3-sbc-t3517.dtb \ + omap3-sbc-t3530.dtb \ + omap3-sbc-t3730.dtb \ + omap3-sniper.dtb \ + omap3-thunder.dtb \ + omap3-zoom3.dtb +dtb-$(CONFIG_ARCH_OMAP4) += \ + omap4-droid-bionic-xt875.dtb \ + omap4-droid4-xt894.dtb \ + omap4-duovero-parlor.dtb \ + omap4-epson-embt2ws.dtb \ + omap4-kc1.dtb \ + omap4-panda.dtb \ + omap4-panda-a4.dtb \ + omap4-panda-es.dtb \ + omap4-sdp.dtb \ + omap4-sdp-es23plus.dtb \ + omap4-var-dvk-om44.dtb \ + omap4-var-stk-om44.dtb +dtb-$(CONFIG_SOC_AM33XX) += \ + am335x-baltos-ir2110.dtb \ + am335x-baltos-ir3220.dtb \ + am335x-baltos-ir5221.dtb \ + am335x-base0033.dtb \ + am335x-bone.dtb \ + am335x-boneblack.dtb \ + am335x-boneblack-wireless.dtb \ + am335x-boneblue.dtb \ + am335x-bonegreen.dtb \ + am335x-bonegreen-wireless.dtb \ + am335x-chiliboard.dtb \ + am335x-cm-t335.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-guardian.dtb \ + am335x-icev2.dtb \ + am335x-lxm.dtb \ + am335x-moxa-uc-2101.dtb \ + am335x-moxa-uc-8100-me-t.dtb \ + am335x-myirtech-myd.dtb \ + am335x-nano.dtb \ + am335x-netcan-plus-1xx.dtb \ + am335x-netcom-plus-2xx.dtb \ + am335x-netcom-plus-8xx.dtb \ + am335x-pdu001.dtb \ + am335x-pepper.dtb \ + am335x-phycore-rdk.dtb \ + am335x-pocketbeagle.dtb \ + am335x-regor-rdk.dtb \ + am335x-sancloud-bbe.dtb \ + am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ + am335x-shc.dtb \ + am335x-sbc-t335.dtb \ + am335x-sl50.dtb \ + am335x-wega-rdk.dtb \ + am335x-osd3358-sm-red.dtb +dtb-$(CONFIG_SOC_AM43XX) += \ + am43x-epos-evm.dtb \ + am437x-cm-t43.dtb \ + am437x-gp-evm.dtb \ + am437x-idk-evm.dtb \ + am437x-sbc-t43.dtb \ + am437x-sk-evm.dtb + +am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo +am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo + +dtb-$(CONFIG_SOC_DRA7XX) += \ + am57xx-beagle-x15.dtb \ + am57xx-beagle-x15-revb1.dtb \ + am57xx-beagle-x15-revc.dtb \ + am57xx-evm.dtb \ + am57xx-evm-reva3.dtb \ + am5729-beagleboneai.dtb \ + am57xx-cl-som-am57x.dtb \ + am57xx-sbc-am57x.dtb \ + am572x-idk.dtb \ + am572x-idk-touchscreen.dtbo \ + am571x-idk.dtb \ + am571x-idk-touchscreen.dtbo \ + am574x-idk.dtb \ + am57xx-idk-lcd-osd101t2045.dtbo \ + am57xx-idk-lcd-osd101t2587.dtbo \ + dra7-evm.dtb \ + dra72-evm.dtb \ + dra72-evm-revc.dtb \ + dra71-evm.dtb \ + dra76-evm.dtb +dtb-$(CONFIG_SOC_OMAP5) += \ + omap5-cm-t54.dtb \ + omap5-igep0050.dtb \ + omap5-sbc-t54.dtb \ + omap5-uevm.dtb +dtb-$(CONFIG_SOC_TI81XX) += \ + am3874-iceboard.dtb \ + dm8148-evm.dtb \ + dm8148-t410.dtb \ + dm8168-evm.dtb \ + dra62x-j5eco-evm.dtb diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts new file mode 100644 index 000000000000..ea5882ed7010 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" +#include "am335x-baltos-leds.dtsi" + +/ { + model = "OnRISC Baltos iR 2110"; +}; + +&am33xx_pinmux { + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&davinci_mdio_sw { + phy0: ethernet-phy@0 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; + phy-handle = <&phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +}; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "NC", + "NC", + "NC", + "SD_CD", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "NC", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts new file mode 100644 index 000000000000..ea4f8dde6424 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" +#include "am335x-baltos-leds.dtsi" + +/ { + model = "OnRISC Baltos iR 3220"; +}; + +&am33xx_pinmux { + tca6416_pins: tca6416-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ + + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&i2c1 { + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; + }; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +}; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "WLAN_BTN", + "W_DISABLE", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "TCA6416_INT", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SD_CD", + "SD_WP", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "3G_PWR_EN", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "USB1_DRVVBUS", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts new file mode 100644 index 000000000000..ec914f27d11d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" +#include "am335x-baltos-leds.dtsi" + +/ { + model = "OnRISC Baltos iR 5221"; +}; + +&am33xx_pinmux { + tca6416_pins: tca6416-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ + + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&i2c1 { + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; + }; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +}; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "WLAN_BTN", + "W_DISABLE", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "TCA6416_INT", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "DCAN1_TX", + "DCAN1_RX", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SD_CD", + "SD_WP", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "3G_PWR_EN", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "USB1_DRVVBUS", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi new file mode 100644 index 000000000000..6a52e42b9e81 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/*#include "am33xx.dtsi"*/ + +/ { + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + compatible = "gpio-leds"; + + led-power { + label = "onrisc:red:power"; + linux,default-trigger = "default-on"; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + led-wlan { + label = "onrisc:blue:wlan"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-app { + label = "onrisc:green:app"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + user_leds: user-leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi new file mode 100644 index 000000000000..c14d5b70c72f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +#include "am33xx.dtsi" +#include +#include + +/ { + compatible = "vscom,onrisc", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + wl12xx_vmmc: fixedregulator2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 8 0>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ + >; + }; + + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ + >; + }; + + tps65910_pins: tps65910-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + + + /* Slave 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + + /* Slave 2 reset value*/ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + nandflash_pins_s0: nandflash-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + status = "okay"; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "prefetch-dma"; + + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + ti,elm-id = <&elm>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65910_pins>; + }; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; + }; +}; + +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + ti,en-ck32k-xtal = <1>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + + status = "okay"; +}; + +&davinci_mdio_sw { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + phy1: ethernet-phy@1 { + reg = <7>; + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + status = "okay"; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0_target { + ti,no-reset-on-init; +}; + +&gpio3_target { + ti,no-reset-on-init; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts new file mode 100644 index 000000000000..eba843e22ea1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION + * + * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + */ + +#include "am335x-igep0033.dtsi" + +/ { + model = "IGEP COM AM335x on AQUILA Expansion"; + compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; + + hdmi { + compatible = "ti,tilcdc,slave"; + i2c = <&i2c0>; + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_pins>; + pinctrl-1 = <&nxp_hdmi_off_pins>; + status = "okay"; + }; + + leds_base { + pinctrl-names = "default"; + pinctrl-0 = <&leds_base_pins>; + + compatible = "gpio-leds"; + + led0 { + label = "base:red:user"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ + default-state = "off"; + }; + + led1 { + label = "base:green:user"; + gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + nxp_hdmi_pins: nxp-hdmi-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + nxp_hdmi_off_pins: nxp-hdmi-off-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ + >; + }; + + leds_base_pins: leds-base-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ + >; + }; +}; + +&lcdc { + status = "okay"; +}; + +&i2c0 { + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi new file mode 100644 index 000000000000..b958607c71dc --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led2 { + label = "beaglebone:green:heartbeat"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:mmc0"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user-leds-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + clkout2_pin: clkout2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + emmc_pins: emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + + #address-cells = <1>; + #size-cells = <1>; + baseboard_data: baseboard_data@0 { + reg = <0 0x100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; + + cape_eeprom0: cape_eeprom0@54 { + compatible = "atmel,24c256"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + cape0_data: cape_data@0 { + reg = <0 0x100>; + }; + }; + + cape_eeprom1: cape_eeprom1@55 { + compatible = "atmel,24c256"; + reg = <0x55>; + #address-cells = <1>; + #size-cells = <1>; + cape1_data: cape_data@0 { + reg = <0 0x100>; + }; + }; + + cape_eeprom2: cape_eeprom2@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + #address-cells = <1>; + #size-cells = <1>; + cape2_data: cape_data@0 { + reg = <0 0x100>; + }; + }; + + cape_eeprom3: cape_eeprom3@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + #address-cells = <1>; + #size-cells = <1>; + cape3_data: cape_data@0 { + reg = <0 0x100>; + }; + }; +}; + + +/include/ "../../tps65217.dtsi" + +&tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ + + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + + ti,pmic-shutdown-controller; + + charger { + status = "okay"; + }; + + pwrbutton { + status = "okay"; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "mii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; + system-power-controller; +}; + +&pruss_tm { + status = "okay"; +}; + +&wkup_m3_ipc { + firmware-name = "am335x-bone-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone.dts b/arch/arm/boot/dts/ti/omap/am335x-bone.dts new file mode 100644 index 000000000000..b5d85ef51a02 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-bone.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" + +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&ldo3_reg>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi new file mode 100644 index 000000000000..a7a8c61ef9b2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; + non-removable; +}; + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi new file mode 100644 index 000000000000..109f08fd174d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; +}; + +&lcdc { + status = "okay"; + + /* If you want to get 24 bit RGB and 16 BGR mode instead of + * current 16 bit RGB and 24 BGR modes, set the propety + * below to "crossed" and uncomment the video-ports -property + * in tda19988 node. + */ + blue-and-red-wiring = "straight"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: tda19988@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + nxp,calib-gpios = <&gpio1 25 0>; + interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ + /* video-ports = <0x234501>; */ + + #sound-dai-cells = <0>; + audio-ports = < TDA998x_I2S 0x03>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts new file mode 100644 index 000000000000..b4b4b80df08c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" +#include + +/ { + model = "TI AM335x BeagleBone Black Wireless"; + compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <70000>; + + /* WL_EN */ + gpio = <&gpio3 9 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + bt_pins: bt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: wl18xx-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ + >; + }; +}; + +&mac_sw { + status = "disabled"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio3 { + ls-buf-en-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LS_BUF_EN"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts new file mode 100644 index 000000000000..b956e2f60fe0 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&cpu0_opp_table { + /* + * All PG 2.0 silicon may not support 1GHz but some of the early + * BeagleBone Blacks have PG 2.0 silicon which is guaranteed + * to support 1GHz OPP so enable it for PG 2.0 on this board. + */ + oppnitro-1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + +&gpio0 { + gpio-line-names = + "[mdio_data]", + "[mdio_clk]", + "P9_22 [spi0_sclk]", + "P9_21 [spi0_d0]", + "P9_18 [spi0_d1]", + "P9_17 [spi0_cs0]", + "[mmc0_cd]", + "P8_42A [ecappwm0]", + "P8_35 [lcd d12]", + "P8_33 [lcd d13]", + "P8_31 [lcd d14]", + "P8_32 [lcd d15]", + "P9_20 [i2c2_sda]", + "P9_19 [i2c2_scl]", + "P9_26 [uart1_rxd]", + "P9_24 [uart1_txd]", + "[rmii1_txd3]", + "[rmii1_txd2]", + "[usb0_drvvbus]", + "[hdmi cec]", + "P9_41B", + "[rmii1_txd1]", + "P8_19 [ehrpwm2a]", + "P8_13 [ehrpwm2b]", + "NC", + "NC", + "P8_14", + "P8_17", + "[rmii1_txd0]", + "[rmii1_refclk]", + "P9_11 [uart4_rxd]", + "P9_13 [uart4_txd]"; +}; + +&gpio1 { + gpio-line-names = + "P8_25 [mmc1_dat0]", + "[mmc1_dat1]", + "P8_5 [mmc1_dat2]", + "P8_6 [mmc1_dat3]", + "P8_23 [mmc1_dat4]", + "P8_22 [mmc1_dat5]", + "P8_3 [mmc1_dat6]", + "P8_4 [mmc1_dat7]", + "NC", + "NC", + "NC", + "NC", + "P8_12", + "P8_11", + "P8_16", + "P8_15", + "P9_15A", + "P9_23", + "P9_14 [ehrpwm1a]", + "P9_16 [ehrpwm1b]", + "[emmc rst]", + "[usr0 led]", + "[usr1 led]", + "[usr2 led]", + "[usr3 led]", + "[hdmi irq]", + "[usb vbus oc]", + "[hdmi audio]", + "P9_12", + "P8_26", + "P8_21 [emmc]", + "P8_20 [emmc]"; +}; + +&gpio2 { + gpio-line-names = + "P9_15B", + "P8_18", + "P8_7", + "P8_8", + "P8_10", + "P8_9", + "P8_45 [hdmi]", + "P8_46 [hdmi]", + "P8_43 [hdmi]", + "P8_44 [hdmi]", + "P8_41 [hdmi]", + "P8_42 [hdmi]", + "P8_39 [hdmi]", + "P8_40 [hdmi]", + "P8_37 [hdmi]", + "P8_38 [hdmi]", + "P8_36 [hdmi]", + "P8_34 [hdmi]", + "[rmii1_rxd3]", + "[rmii1_rxd2]", + "[rmii1_rxd1]", + "[rmii1_rxd0]", + "P8_27 [hdmi]", + "P8_29 [hdmi]", + "P8_28 [hdmi]", + "P8_30 [hdmi]", + "[mmc0_dat3]", + "[mmc0_dat2]", + "[mmc0_dat1]", + "[mmc0_dat0]", + "[mmc0_clk]", + "[mmc0_cmd]"; +}; + +&gpio3 { + gpio-line-names = + "[mii col]", + "[mii crs]", + "[mii rx err]", + "[mii tx en]", + "[mii rx dv]", + "[i2c0 sda]", + "[i2c0 scl]", + "[jtag emu0]", + "[jtag emu1]", + "[mii tx clk]", + "[mii rx clk]", + "NC", + "NC", + "[usb vbus en]", + "P9_31 [spi1_sclk]", + "P9_29 [spi1_d0]", + "P9_30 [spi1_d1]", + "P9_28 [spi1_cs0]", + "P9_42B [ecappwm0]", + "P9_27", + "P9_41A", + "P9_25", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; + +&baseboard_eeprom { + vcc-supply = <&ldo4_reg>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts new file mode 100644 index 000000000000..801399702547 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" +#include + +/ { + model = "TI AM335x BeagleBone Blue"; + compatible = "ti,am335x-bone-blue", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + usr_0_led { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + usr_1_led { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + usr_2_led { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + usr_3_led { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + wifi_led { + label = "wifi"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "phy0assoc"; + }; + + red_led { + label = "red"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green_led { + label = "green"; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_1_led { + label = "bat25"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_2_led { + label = "bat50"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_3_led { + label = "bat75"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_4_led { + label = "bat100"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <70000>; + + /* WL_EN */ + gpio = <&gpio3 9 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + user_leds_s0: user-leds-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ + + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + >; + }; + + /* UT0 */ + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + /* UT1 */ + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + /* GPS */ + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ + >; + }; + + /* DSM2 */ + uart4_pins: uart4-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + >; + }; + + /* UT5 */ + uart5_pins: uart5-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + bt_pins: bt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: wl18xx-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ + >; + }; + + /* DCAN */ + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + >; + }; + + /* E1 */ + eqep0_pins: eqep0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ + >; + }; + + /* E2 */ + eqep1_pins: eqep1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ + >; + }; + + /* E3 */ + eqep2_pins: eqep2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&i2c0 { + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + + #address-cells = <1>; + #size-cells = <1>; + baseboard_data: baseboard_data@0 { + reg = <0 0x100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; + + mpu9250@68 { + compatible = "invensense,mpu9250"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ax8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + }; + }; + }; + + pressure@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + }; +}; + +/include/ "../../tps65217.dtsi" + +&tps { + /delete-property/ ti,pmic-shutdown-controller; + + charger { + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; + status = "okay"; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&rtc { + system-power-controller; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + "UART3_CTS", /* M17 */ + "UART3_RTS", /* M18 */ + "UART2_RX", /* A17 */ + "UART2_TX", /* B17 */ + "I2C1_SDA", /* B16 */ + "I2C1_SCL", /* A16 */ + "MMC0_CD", /* C15 */ + "SPI1_SS2", /* C18 */ + "EQEP_1A", /* V2 */ + "EQEP_1B", /* V3 */ + "MDIR_2B", /* V4 */ + "BATT_LED_2", /* T5 */ + "I2C2_SDA", /* D18 */ + "I2C2_SCL", /* D17 */ + "UART1_RX", /* D16 */ + "UART1_TX", /* D15 */ + "MMC2_DAT1", /* J18 */ + "MMC2_DAT2", /* K15 */ + "NC", /* F16 */ + "WIFI_LED", /* A15 */ + "MOT_STBY", /* D14 */ + "WLAN_IRQ", /* K16 */ + "PWM_2A", /* U10 */ + "PWM_2B", /* T10 */ + "", + "", + "BATT_LED_4", /* T11 */ + "BATT_LED_1", /* U12 */ + "BT_EN", /* K17 */ + "SPI1_SS1", /* H18 */ + "UART4_RX", /* T17 */ + "MDIR_1B"; /* U17 */ +}; + +&gpio1 { + gpio-line-names = + "MMC1_DAT0", /* U7 */ + "MMC1_DAT1", /* V7 */ + "MMC1_DAT2", /* R8 */ + "MMC1_DAT3", /* T8 */ + "MMC1_DAT4", /* U8 */ + "MMC1_DAT5", /* V8 */ + "MMC1_DAT6", /* R9 */ + "MMC1_DAT7", /* T9 */ + "DCAN1_TX", /* E18 */ + "DCAN1_RX", /* E17 */ + "UART0_RX", /* E15 */ + "UART0_TX", /* E16 */ + "EQEP_2A", /* T12 */ + "EQEP_2B", /* R12 */ + "PRU_E_A", /* V13 */ + "PRU_E_B", /* U13 */ + "MDIR_2A", /* R13 */ + "GPIO1_17", /* V14 */ + "PWM_1A", /* U14 */ + "PWM_1B", /* T14 */ + "EMMC_RST", /* R14 */ + "USR_LED_0", /* V15 */ + "USR_LED_1", /* U15 */ + "USR_LED_2", /* T15 */ + "USR_LED_3", /* V16 */ + "GPIO1_25", /* U16 */ + "MCASP0_AXR0", /* T16 */ + "MCASP0_AXR1", /* V17 */ + "MCASP0_ACLKR", /* U18 */ + "BATT_LED_3", /* V6 */ + "MMC1_CLK", /* U9 */ + "MMC1_CMD"; /* V9 */ +}; + +&gpio2 { + gpio-line-names = + "MDIR_1A", /* T13 */ + "MCASP0_FSR", /* V12 */ + "LED_RED", /* R7 */ + "LED_GREEN", /* T7 */ + "MODE_BTN", /* U6 */ + "PAUSE_BTN", /* T6 */ + "MDIR_4A", /* R1 */ + "MDIR_4B", /* R2 */ + "MDIR_3B", /* R3 */ + "MDIR_3A", /* R4 */ + "SVO7", /* T1 */ + "SVO8", /* T2 */ + "SVO5", /* T3 */ + "SVO6", /* T4 */ + "UART5_TX", /* U1 */ + "UART5_RX", /* U2 */ + "SERVO_EN", /* U3 */ + "NC", /* U4 */ + "UART3_RX", /* L17 */ + "UART3_TX", /* L16 */ + "MMC2_CLK", /* L15 */ + "DCAN1_SILENT", /* M16 */ + "SVO1", /* U5 */ + "SVO3", /* R5 */ + "SVO2", /* V5 */ + "SVO4", /* R6 */ + "MMC0_DAT3", /* F17 */ + "MMC0_DAT2", /* F18 */ + "MMC0_DAT1", /* G15 */ + "MMC0_DAT0", /* G16 */ + "MMC0_CLK", /* G17 */ + "MMC0_CMD"; /* G18 */ +}; + +&gpio3 { + gpio-line-names = + "MMC2_DAT3", /* H16 */ + "GPIO3_1", /* H17 */ + "GPIO3_2", /* J15 */ + "MMC2_CMD", /* J16 */ + "MMC2_DAT0", /* J17 */ + "I2C0_SDA", /* C17 */ + "I2C0_SCL", /* C16 */ + "EMU1", /* C14 */ + "EMU0", /* B14 */ + "WL_EN", /* K18 */ + "WL_BT_OE", /* L18 */ + "", + "", + "NC", /* F15 */ + "SPI1_SCK", /* A13 */ + "SPI1_MISO", /* B13 */ + "SPI1_MOSI", /* D12 */ + "GPIO3_17", /* C12 */ + "EQEP_0A", /* B12 */ + "EQEP_0B", /* C13 */ + "GPIO3_20", /* D13 */ + "IMU_INT", /* A14 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + + ls-buf-en-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&eqep0 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep0_pins>; + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&eqep1 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep1_pins>; + status = "okay"; +}; + +&epwmss2 { + status = "okay"; +}; + +&eqep2 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep2_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi new file mode 100644 index 000000000000..383beeddf595 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&am33xx_pinmux { + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&rtc { + system-power-controller; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts new file mode 100644 index 000000000000..a4f5b5262645 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-bonegreen-common.dtsi" +#include + +/ { + model = "TI AM335x BeagleBone Green Wireless"; + compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <70000>; + + /* WL_EN */ + gpio = <&gpio0 26 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + bt_pins: bt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: wl18xx-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ + >; + }; +}; + +&mac_sw { + status = "disabled"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio1 { + ls-buf-en-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LS_BUF_EN"; + }; +}; + +/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/ +/* in case it isn't, wilink8 ends up in one of the test modes that */ +/* intruces various issues (elp wkaeup timeouts etc.) */ +/* On the BBGW this pin is routed through the level shifter (U21) that */ +/* introduces a pullup on the line and wilink8 ends up in a bad state. */ +/* use a gpio hog to force this pin low. An alternative may be adding */ +/* an external pulldown on U21 pin 4. */ + +&gpio3 { + bt-aud-in-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "MCASP0_AHCLKR"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts new file mode 100644 index 000000000000..18cc0f49e999 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-bonegreen-common.dtsi" + +/ { + model = "TI AM335x BeagleBone Green"; + compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts new file mode 100644 index 000000000000..648e97fe1dfd --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ + * Author: Rostislav Lisovy + */ +/dts-v1/; +#include "am335x-chilisom.dtsi" + +/ { + model = "AM335x Chiliboard"; + compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", + "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_gpio_pins>; + + led0 { + label = "led0"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led1"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&am33xx_pinmux { + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* mdio_data.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + usb1_drvvbus: usb1-drvvbus-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + sd_pins: sd-card-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + led_gpio_pins: led-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&ldo4_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* Ethernet */ +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +/* USB */ +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_drvvbus>; + dr_mode = "host"; +}; + +/* microSD */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + vmmc-supply = <&ldo4_reg>; + bus-width = <0x4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&tps { + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + charger { + status = "okay"; + }; + + pwrbutton { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi b/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi new file mode 100644 index 000000000000..bd43da6356b6 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ + * Author: Rostislav Lisovy + */ +#include "am33xx.dtsi" +#include + +/ { + model = "Grinn AM335x ChiliSOM"; + compatible = "grinn,am335x-chilisom", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + nandflash_pins: nandflash-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + +/include/ "../../tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3d"; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&rtc { + system-power-controller; + + pinctrl-0 = <&ext_wakeup>; + pinctrl-names = "default"; + + ext_wakeup: ext-wakeup { + pins = "ext_wakeup0"; + input-enable; + }; +}; + +/* NAND Flash */ +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts new file mode 100644 index 000000000000..72990e7ffe10 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 + * + * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include + +/ { + model = "CompuLab CM-T335"; + compatible = "compulab,cm-t335", "ti,am33xx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_led_pins>; + led0 { + label = "cm_t335:green"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ + linux,default-trigger = "heartbeat"; + }; + }; + + /* regulator for mmc */ + vmmc_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* Regulator for WiFi */ + vwlan_fixed: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "vwlan_fixed"; + gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ + enable-active-high; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 0>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "cm-t335"; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Headphone", "Headphone Jack"; + + simple-audio-card,routing = + "Headphone Jack", "LHPOUT", + "Headphone Jack", "RHPOUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic Jack"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic23>; + system-clock-frequency = <12000000>; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_pins>; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + /* uart0_ctsn.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) + /* uart0_rtsn.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + gpio_led_pins: gpio-led-pins { + pinctrl-single,pins = < + /* gpmc_csn3.gpio2_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) + >; + }; + + nandflash_pins: nandflash-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + dcan0_pins: dcan0-pins { + pinctrl-single,pins = < + /* uart1_ctsn.dcan0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) + /* uart1_rtsn.dcan0_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) + >; + }; + + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + /* uart1_rxd.dcan1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) + /* uart1_txd.dcan1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) + >; + }; + + ecap0_pins: ecap0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + /* mii1_tx_en.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) + >; + }; + + /* wl1271 bluetooth */ + bluetooth_pins: bluetooth-pins { + pinctrl-single,pins = < + /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) + >; + }; + + /* TLV320AIC23B codec */ + mcasp1_pins: mcasp1-pins { + pinctrl-single,pins = < + /* MII1_CRS.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) + /* MII1_RX_ER.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) + /* MII1_COL.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) + /* RMII1_REF_CLK.mcasp1_axr3 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) + >; + }; + + /* wl1271 WiFi */ + wifi_pins: wifi-pins { + pinctrl-single,pins = < + /* EMU1.gpio3_8 - WiFi IRQ */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) + /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +/* WLS1271 bluetooth */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + +status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + /* CM-T335 board EEPROM */ + eeprom: 24c02@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + /* Real Time Clock */ + ext_rtc: em3027@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; + /* Audio codec */ + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + #sound-dai-cells = <0>; + status = "okay"; + }; +}; + +&epwmss0 { + status = "okay"; + + ecap0: pwm@100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; + }; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "spl"; + reg = <0x00000000 0x00200000>; + }; + partition@1 { + label = "uboot"; + reg = <0x00200000 0x00100000>; + }; + partition@2 { + label = "uboot environment"; + reg = <0x00300000 0x00100000>; + }; + partition@3 { + label = "dtb"; + reg = <0x00400000 0x00100000>; + }; + partition@4 { + label = "splash"; + reg = <0x00500000 0x00400000>; + }; + partition@5 { + label = "linux"; + reg = <0x00900000 0x00600000>; + }; + partition@6 { + label = "rootfs"; + reg = <0x00F00000 0>; + }; + }; +}; + +&elm { + status = "okay"; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-txid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; +}; + +&dcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; +}; + +/* Touschscreen and analog digital converter */ +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x01 0x10 0x23 0x32>; + ti,charge-delay = <0x400>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +/* CPU audio */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 16 serializers */ + num-serializer = <16>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; + + #sound-dai-cells = <0>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + ti,pindir-d0-out-d1-in; + /* WLS1271 WiFi */ + wlcore: wlcore@1 { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins>; + reg = <1>; + spi-max-frequency = <48000000>; + clock-xtal; + ref-clock-frequency = <38400000>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + vwlan-supply = <&vwlan_fixed>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-evm.dts b/arch/arm/boot/dts/ti/omap/am335x-evm.dts new file mode 100644 index 000000000000..61bf8bcd4c4e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-evm.dts @@ -0,0 +1,786 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include + +/ { + model = "TI AM335x EVM"; + compatible = "ti,am335x-evm", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + chosen { + stdout-path = &uart0; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + wlan_en_reg: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* WLAN_EN GPIO for this board - Bank1, pin16 */ + gpio = <&gpio1 16 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* TPS79501 */ + v1_8d_reg: fixedregulator-v1_8d { + compatible = "regulator-fixed"; + regulator-name = "v1_8d"; + vin-supply = <&vbat>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* TPS79501 */ + v3_3d_reg: fixedregulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "v3_3d"; + vin-supply = <&vbat>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + matrix_keypad: matrix_keypad0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ + &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ + &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ + + col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ + &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ + + linux,keymap = <0x0000008b /* MENU */ + 0x0100009e /* BACK */ + 0x02000069 /* LEFT */ + 0x0001006a /* RIGHT */ + 0x0101001c /* ENTER */ + 0x0201006c>; /* DOWN */ + }; + + gpio_keys: volume-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-9 { + label = "volume-up"; + linux,code = <115>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-10 { + label = "volume-down"; + linux,code = <114>; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 0>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + panel { + compatible = "tfc,s9700rtwv43tr-01b"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins_s0>; + backlight = <&backlight>; + + port { + panel_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM335x-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <12000000>; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; + + matrix_keypad_s0: matrix-keypad-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; + + volume_keys_s0: volume-keys-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + clkout2_pin: clkout2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + nandflash_pins_s0: nandflash-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) + >; + }; + + ecap0_pins: backlight-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ + >; + }; + + wlan_pins: wlan-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ + >; + }; + + lcd_pins_s0: lcd-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + mcasp1_pins: mcasp1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_pins_sleep: mcasp1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + dcan1_pins_default: dcan1-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&usb1 { + dr_mode = "host"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + + tsl2550: tsl2550@39 { + compatible = "taos,tsl2550"; + reg = <0x39>; + }; + + tmp275: tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&v3_3d_reg>; + IOVDD-supply = <&v3_3d_reg>; + DRVDD-supply = <&v3_3d_reg>; + DVDD-supply = <&v1_8d_reg>; + }; +}; + +&lcdc { + status = "okay"; + + blue-and-red-wiring = "crossed"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&panel_0>; + }; + }; +}; + +&elm { + status = "okay"; +}; + +&epwmss0 { + status = "okay"; + + ecap0: pwm@100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; + }; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000C0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001C0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001E0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00A00000 0x0F600000>; + }; + }; +}; + +#include "../../tps65910.dtsi" + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + ti,charge-delay = <0x400>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc3 { + /* these are on the crossbar and are outlined in the + xbar-event-map element */ + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wlan_pins>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&dcan1 { + status = "disabled"; /* Enable only if Profile 1 is selected */ + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins_default>; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; + +&pruss_tm { + status = "okay"; +}; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts new file mode 100644 index 000000000000..57f78846c42d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * AM335x Starter Kit + * http://www.ti.com/tool/tmdssk3358 + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "TI AM335x EVM-SK"; + compatible = "ti,am335x-evmsk", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + chosen { + stdout-path = &uart0; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + wl12xx_vmmc: fixedregulator2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 29 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + /* TPS79518 */ + v1_8d_reg: fixedregulator-v1_8d { + compatible = "regulator-fixed"; + regulator-name = "v1_8d"; + vin-supply = <&vbat>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* TPS78633 */ + v3_3d_reg: fixedregulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "v3_3d"; + vin-supply = <&vbat>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led1 { + label = "evmsk:green:usr0"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "evmsk:green:usr1"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "evmsk:green:mmc0"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led4 { + label = "evmsk:green:heartbeat"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + gpio_buttons: gpio_buttons0 { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + switch1 { + label = "button0"; + linux,code = <0x100>; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + }; + + switch2 { + label = "button1"; + linux,code = <0x101>; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + }; + + switch3 { + label = "button2"; + linux,code = <0x102>; + gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + switch4 { + label = "button3"; + linux,code = <0x103>; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 58 61 66 75 90 125 170 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM335x-EVMSK"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24000000>; + }; + }; + + panel { + compatible = "newhaven,nhd-4.3-480272ef-atxl"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + backlight = <&lcd_bl>; + + port { + panel_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + + lcd_pins_default: lcd-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + lcd_pins_sleep: lcd-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + + user_leds_s0: user-leds-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + >; + }; + + gpio_keys_s0: gpio-keys-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + clkout2_pin: clkout2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + ecap2_pins: backlight-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + + /* Slave 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + + /* Slave 2 reset value*/ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ + >; + }; + + mcasp1_pins: mcasp1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_pins_sleep: mcasp1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + >; + }; + + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&v3_3d_reg>; + IOVDD-supply = <&v3_3d_reg>; + DRVDD-supply = <&v3_3d_reg>; + DVDD-supply = <&v1_8d_reg>; + }; +}; + +&usb1 { + dr_mode = "host"; +}; + +&epwmss2 { + status = "okay"; + + ecap2: pwm@100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + }; +}; + +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0_target { + ti,no-reset-on-init; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ + ref-clock-frequency = <38400000>; + }; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; +}; + +&lcdc { + status = "okay"; + + blue-and-red-wiring = "crossed"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&panel_0>; + }; + }; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; + +&pruss_tm { + status = "okay"; +}; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts new file mode 100644 index 000000000000..205fe0ed7352 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -0,0 +1,745 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "Bosch AM335x Guardian"; + compatible = "bosch,am335x-guardian", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + guardian_buttons: gpio-keys { + pinctrl-names = "default"; + pinctrl-0 = <&guardian_button_pins>; + compatible = "gpio-keys"; + + select-button { + label = "guardian-select-button"; + linux,code = ; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + power-button { + label = "guardian-power-button"; + linux,code = ; + gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + guardian_leds: gpio-leds { + pinctrl-names = "default"; + pinctrl-0 = <&guardian_led_pins>; + compatible = "gpio-leds"; + + life-led { + label = "guardian:life-led"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; + pinctrl-1 = <&lcd_pins_sleep>; + + display-timings { + 320x240 { + hactive = <320>; + vactive = <240>; + hback-porch = <68>; + hfront-porch = <20>; + hsync-len = <1>; + vback-porch = <18>; + vfront-porch = <4>; + vsync-len = <1>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <24>; + bus-width = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + }; + + guardian_beeper: pwm-7 { + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer7>; + pinctrl-names = "default"; + pinctrl-0 = <&guardian_beeper_pins>; + ti,clock-source = <0x01>; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + mt_keypad: mt_keypad@0 { + compatible = "gpio-mt-keypad"; + debounce-delay-ms = <10>; + col-scan-delay-us = <2>; + keypad,num-lines = <5>; + linux,no-autorepeat; + gpio-activelow; + line-gpios = < + &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/ + &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/ + &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/ + &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/ + &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ + status = "okay"; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <15>; + gpmc,oe-on-ns = <1>; + gpmc,oe-off-ns = <15>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + + /* + * MTD partition table + * + * All SPL-* partitions are sized to minimal length which can + * be independently programmable. For NAND flash this is equal + * to size of erase-block. + */ + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0x0 0x40000>; + }; + + partition@1 { + label = "SPL.backup1"; + reg = <0x40000 0x40000>; + }; + + partition@2 { + label = "SPL.backup2"; + reg = <0x80000 0x40000>; + }; + + partition@3 { + label = "SPL.backup3"; + reg = <0xc0000 0x40000>; + }; + + partition@4 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + + partition@5 { + label = "u-boot.backup1"; + reg = <0x200000 0x100000>; + }; + + partition@6 { + label = "u-boot-2"; + reg = <0x300000 0x100000>; + }; + + partition@7 { + label = "u-boot-2.backup1"; + reg = <0x400000 0x100000>; + }; + + partition@8 { + label = "u-boot-env"; + reg = <0x500000 0x40000>; + }; + + partition@9 { + label = "u-boot-env.backup1"; + reg = <0x540000 0x40000>; + }; + + partition@10 { + label = "splash-screen"; + reg = <0x580000 0x40000>; + }; + + partition@11 { + label = "UBI"; + reg = <0x5c0000 0x1fa40000>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tps: tps@24 { + reg = <0x24>; + }; +}; + +&lcdc { + blue-and-red-wiring = "crossed"; + status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <0>; + }; + }; +}; + +&mmc1 { + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vmmcsd_fixed>; + status = "okay"; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; + +&spi0 { + ti,pindir-d0-out-d1-in; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; +}; + +#include "../../tps65217.dtsi" + +&tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ + ti,pmic-shutdown-controller; + interrupt-parent = <&intc>; + interrupts = <7>; /* NMI */ + + backlight { + isel = <1>; /* 1 - ISET1, 2 ISET2 */ + fdim = <500>; /* TPS65217_BL_FDIM_500HZ */ + default-brightness = <50>; + /* 1(on) - enable current sink, while initialization */ + /* 0(off) - disable current sink, while initialization */ + isink-en = <1>; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&gpio0 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MirxWakeup", + "", + ""; +}; + +&gpio3 { + ti,gpio-always-on; + ti,no-reset-on-init; + gpio-line-names = + "", + "MirxBtReset", + "", + "CcVolAdcEn", + "MirxBlePause", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AspEn", + "", + "", + "", + "", + "", + "", + "BatVolAdcEn", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usb1 { + dr_mode = "host"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; + + clkout2_pin: clkout2-pins { + pinctrl-single,pins = < + /* xdma_event_intr1.clkout2 */ + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; + + guardian_interface_pins: interface-pins { + pinctrl-single,pins = < + /* ADC_BATSENSE_EN */ + /* (A14) MCASP0_AHCLKx.gpio3[21] */ + AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ADC_COINCELL_EN */ + /* (J16) MII1_TX_EN.gpio3[3] */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ASP_ENABLE */ + /* (A13) MCASP0_ACLKx.gpio3[14] */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* (D16) uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) + /* (D15) uart1_txd.uart1_txd */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) + /*SWITCH-OFF_3V6*/ + /* (M18) gpio0[1] */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* MIRACULIX */ + /* (H17) gmii1_crs.gpio3[1] */ + AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (H18) rmii1_refclk.gpio0[29] */ + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 ) + /* (J17) gmii1_rxdv.gpio3[4] */ + AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + >; + }; + + guardian_beeper_pins: dmtimer7-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ + >; + }; + + guardian_button_pins: guardian-button-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ + >; + }; + + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + led_bl_pins: gpio-led-bl-pins { + pinctrl-single,pins = < + /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) + >; + }; + + lcd_disen_pins: lcd-disen-pins { + pinctrl-single,pins = < + /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ + AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) + >; + }; + + lcd_pins_default: lcd-default-pins { + pinctrl-single,pins = < + /* (U10) gpmc_ad8.lcd_data23 */ + AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T10) gpmc_ad9.lcd_data22 */ + AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T11) gpmc_ad10.lcd_data21 */ + AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U12) gpmc_ad11.lcd_data20 */ + AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T12) gpmc_ad12.lcd_data19 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (R12) gpmc_ad13.lcd_data18 */ + AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (V13) gpmc_ad14.lcd_data17 */ + AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U13) gpmc_ad15.lcd_data16 */ + AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + >; + }; + + lcd_pins_sleep: lcd-sleep-pins { + pinctrl-single,pins = < + /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + >; + }; + + guardian_led_pins: guardian-led-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + /* SPI0_CLK - spi0_clk.spi */ + AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + /* SPI0_MOSI - spi0_d0.spi0 */ + AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + /* SPI0_MISO - spi0_d1.spi0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) + /* SPI0_CS0 - spi */ + AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart0_txd.uart0_txd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + /* K18 uart2_rxd.mirx_txd */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) + /* L18 uart2_txd.mirx_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) + >; + }; + + nandflash_pins: nandflash-pins { + pinctrl-single,pins = < + /* (U7) gpmc_ad0.gpmc_ad0 */ + AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) + /* (V7) gpmc_ad1.gpmc_ad1 */ + AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) + /* (R8) gpmc_ad2.gpmc_ad2 */ + AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) + /* (T8) gpmc_ad3.gpmc_ad3 */ + AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) + /* (U8) gpmc_ad4.gpmc_ad4 */ + AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) + /* (V8) gpmc_ad5.gpmc_ad5 */ + AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) + /* (R9) gpmc_ad6.gpmc_ad6 */ + AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) + /* (T9) gpmc_ad7.gpmc_ad7 */ + AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) + /* (T17) gpmc_wait0.gpmc_wait0 */ + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) + /* (U17) gpmc_wpn.gpmc_wpn */ + AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) + /* (V6) gpmc_csn0.gpmc_csn0 */ + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) + /* (R7) gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) + /* (T7) gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) + /* (U6) gpmc_wen.gpmc_wen */ + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) + /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-icev2.dts b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts new file mode 100644 index 000000000000..3c4228927f56 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "TI AM3359 ICE-V2"; + compatible = "ti,am3359-icev2", "ti,am33xx"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + chosen { + stdout-path = &uart3; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + /* Tricolor status LEDs */ + leds1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led1 { + label = "status0:green:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "status0:yellow:usr"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "status1:red:mmc0"; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led4 { + label = "status1:green:usr"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + gpio-decoder { + compatible = "gpio-decoder"; + gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, + <&pca9536 2 GPIO_ACTIVE_HIGH>, + <&pca9536 1 GPIO_ACTIVE_HIGH>, + <&pca9536 0 GPIO_ACTIVE_HIGH>; + linux,axis = <0>; /* ABS_X */ + decoder-max-value = <9>; + }; +}; + +&am33xx_pinmux { + user_leds: user-leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ + >; + }; + + mmc0_pins_default: mmc0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) + >; + }; + + spi0_pins_default: spi0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ + >; + }; + + uart3_pins_default: uart3-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1, RMII mode */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ + /* Slave 2, RMII mode */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + + /* Slave 2 reset value */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + + status = "okay"; + clock-frequency = <400000>; + + tps: power-controller@2d { + reg = <0x2d>; + }; + + tpic2810: gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9536: gpio@41 { + compatible = "ti,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* osd9616p0899-10 */ + display@3c { + compatible = "solomon,ssd1306fb-i2c"; + reg = <0x3c>; + solomon,height = <16>; + solomon,width = <96>; + solomon,com-seq; + solomon,com-invdir; + solomon,page-offset = <0>; + solomon,prechargep1 = <2>; + solomon,prechargep2 = <13>; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_default>; + + sn65hvs882@1 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + + reg = <1>; + spi-max-frequency = <1000000>; + spi-cpol; + }; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "u-boot"; + reg = <0x80000 0x100000>; + read-only; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + read-only; + }; + + partition@3 { + label = "misc"; + reg = <0x1A0000 0x660000>; + }; + }; + +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <1 2 3 4 5 6 7>; + }; +}; + +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1326000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; +}; + +&gpio0_target { + /* Do not idle the GPIO used for holding the VTT regulator */ + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; + status = "okay"; +}; + +&gpio3 { + pr1-mii-ctl-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PR1_MII_CTRL"; + }; + + mux-mii-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ + output-high; + line-name = "MUX_MII_CTL1"; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <2>; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + + ethphy0: ethernet-phy@1 { + reg = <1>; + }; + + ethphy1: ethernet-phy@3 { + reg = <3>; + }; +}; + +&pruss_tm { + status = "okay"; +}; + +&rtc { + system-power-controller; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi new file mode 100644 index 000000000000..e85c33fd42f0 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x + * + * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + compatible = "gpio-leds"; + + led0 { + label = "com:green:user"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vmmc: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + nandflash_pins: nandflash-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + leds_pins: leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + >; + }; +}; + +&mac_sw { + status = "okay"; +}; + +&davinci_mdio_sw { + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <2>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + ti,elm-id = <&elm>; + + /* MTD partition table */ + partition@0 { + label = "SPL"; + reg = <0x00000000 0x00080000>; + }; + + partition@1 { + label = "U-boot"; + reg = <0x00080000 0x001e0000>; + }; + + partition@2 { + label = "U-Boot Env"; + reg = <0x00260000 0x00020000>; + }; + + partition@3 { + label = "Kernel"; + reg = <0x00280000 0x00500000>; + }; + + partition@4 { + label = "File System"; + reg = <0x00780000 0x07880000>; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc>; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&usb1 { + dr_mode = "host"; +}; + +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-always-on; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/am335x-lxm.dts b/arch/arm/boot/dts/ti/omap/am335x-lxm.dts new file mode 100644 index 000000000000..be27b5a21b2c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-lxm.dts @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "NovaTech OrionLXm"; + compatible = "novatech,am335x-lxm", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + /* Power supply provides a fixed 5V @2A */ + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* Slave 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ + + /* Slave 2 reset value*/ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + emmc_pins: emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + serial_config1: serial_config1@20 { + compatible = "nxp,pca9539"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + serial_config2: serial_config2@21 { + compatible = "nxp,pca9539"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + tps: tps@2d { + compatible = "ti,tps65910"; + reg = <0x2d>; + }; +}; + +/include/ "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + /* vrtc - unused */ + + vio_reg: regulator@1 { + regulator-name = "vio_1v5,ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd1,mpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd2_1v1,core"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd3 - unused */ + + /* vdig1 - unused */ + + vdig2_reg: regulator@6 { + regulator-name = "vdig2_1v8,vdds_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vpll - unused */ + + vdac_reg: regulator@8 { + regulator-name = "vdac_1v8,vdds"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-name = "vaux1_1v8,usb"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-name = "vaux2_3v3,io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-name = "vaux33_3v3,usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-name = "vmmc_3v3,io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <2>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <3>; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@5 { + reg = <5>; + }; + + ethphy1: ethernet-phy@4 { + reg = <4>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi new file mode 100644 index 000000000000..b8730aa52ce6 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ + * + * Authors: SZ Lin (林上智) + * Wes Huang (黃淵河) + * Fero JD Zhou (周俊達) + */ + +#include "am33xx.dtsi" + +/ { + vbat: vbat-regulator { + compatible = "regulator-fixed"; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: vmmcsd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + buttons: push_button { + compatible = "gpio-keys"; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + push_button_pins: push-button-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc1_pins_default: mmc1-pins { + pinctrl-single,pins = < + /* eMMC */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&uart0 { + /* Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + pagesize = <16>; + reg = <0x50>; + }; + + rtc_wdt: rtc_wdt@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&usb0 { + dr_mode = "host"; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; +}; + +&cpsw_port1 { + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + ti,dual-emac-pvid = <2>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0_target { + ti,no-reset-on-init; +}; + +&mmc2 { + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-0 = <&mmc1_pins_default>; + non-removable; + status = "okay"; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&push_button_pins>; + + button-0 { + label = "push_button"; + linux,code = <0x100>; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + flash@0 { + compatible = "mx25l6405d"; + spi-max-frequency = <40000000>; + + reg = <0>; + spi-cpol; + spi-cpha; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* reg : The partition's offset and size within the mtd bank. */ + partitions@0 { + label = "MLO"; + reg = <0x0 0x80000>; + }; + + partitions@1 { + label = "U-Boot"; + reg = <0x80000 0x100000>; + }; + + partitions@2 { + label = "U-Boot Env"; + reg = <0x180000 0x40000>; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + + tpm_spi_tis@0 { + compatible = "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts new file mode 100644 index 000000000000..e986945ac1b5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ + * + * Authors: SZ Lin (林上智) + * Wes Huang (黃淵河) + * Fero JD Zhou (周俊達) + */ + +/dts-v1/; + +#include "am335x-moxa-uc-2100-common.dtsi" + +/ { + model = "Moxa UC-2101"; + compatible = "moxa,uc-2101", "ti,am33xx"; + + leds { + compatible = "gpio-leds"; + led1 { + label = "UC2100:GREEN:USER"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + spi1_pins: spi1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ + >; + }; +}; + +&davinci_mdio_sw { + phy0: ethernet-phy@4 { + reg = <4>; + }; +}; + +&cpsw_port1 { + phy-handle = <&phy0>; + phy-mode = "rmii"; +}; + +&cpsw_port2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi new file mode 100644 index 000000000000..daaa5eee0f0d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/ + * + * Author: Johnson Chen + */ + +#include "am33xx.dtsi" + +/ { + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: vmmcsd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + buttons: push_button { + compatible = "gpio-keys"; + }; + +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins>; + + minipcie_pins: minipcie-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ + >; + }; + + push_button_pins: push-button-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* Slave 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ + + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc0_pins_default: mmc0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ + >; + }; + + mmc2_pins_default: mmc2-pins { + pinctrl-single,pins = < + /* eMMC */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + +}; + +&uart0 { + /* Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* UART 1 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart5 { + /* UART 2 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + compatible = "ti,tps65910"; + reg = <0x2d>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + pagesize = <16>; + reg = <0x50>; + }; + + rtc_wdt: rtc_wdt@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + gpio_xten: gpio_xten@27 { + compatible = "nxp,pca9535"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x27>; + }; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + dr_mode = "host"; +}; + + +#include "../../tps65910.dtsi" +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vmmc_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + + ethphy0: ethernet-phy@4 { + reg = <4>; + }; + + ethphy1: ethernet-phy@5 { + reg = <5>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <2>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0_target { + ti,no-reset-on-init; +}; + +&mmc1 { + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-0 = <&mmc0_pins_default>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-0 = <&mmc2_pins_default>; + ti,non-removable; + status = "okay"; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&push_button_pins>; + + button-0 { + label = "push_button"; + linux,code = <0x100>; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + flash@0 { + compatible = "mx25l6405d"; + spi-max-frequency = <40000000>; + + reg = <0>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* reg : The partition's offset and size within the mtd bank. */ + partitions@0 { + label = "MLO"; + reg = <0x0 0x80000>; + }; + + partitions@1 { + label = "U-Boot"; + reg = <0x80000 0x100000>; + }; + + partitions@2 { + label = "U-Boot Env"; + reg = <0x180000 0x20000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts new file mode 100644 index 000000000000..0c7949d21bd9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ + * + * Author: SZ Lin (林上智) + */ +/dts-v1/; + +#include "am335x-moxa-uc-8100-common.dtsi" + +/ { + model = "Moxa UC-8100-ME-T"; + compatible = "moxa,uc-8100-me-t", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "uc8100me:CEL1"; + gpios = <&gpio_xten 8 0>; + default-state = "off"; + }; + + led2 { + label = "uc8100me:CEL2"; + gpios = <&gpio_xten 9 0>; + default-state = "off"; + }; + + led3 { + label = "uc8100me:CEL3"; + gpios = <&gpio_xten 10 0>; + default-state = "off"; + }; + + led4 { + label = "uc8100me:DIA1"; + gpios = <&gpio_xten 11 0>; + default-state = "off"; + }; + led5 { + label = "uc8100me:DIA2"; + gpios = <&gpio_xten 12 0>; + default-state = "off"; + }; + led6 { + label = "uc8100me:DIA3"; + gpios = <&gpio_xten 13 0>; + default-state = "off"; + }; + led7 { + label = "uc8100me:SD"; + gpios = <&gpio_xten 14 0>; + default-state = "off"; + }; + led8 { + label = "uc8100me:USB"; + gpios = <&gpio_xten 15 0>; + default-state = "off"; + }; + led9 { + label = "uc8100me:USER"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&i2c0 { + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&tps { + regulators { + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi new file mode 100644 index 000000000000..584599269217 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* SPDX-FileCopyrightText: Alexander Shiyan, */ + +/* Based on code by myc_c335x.dts, MYiRtech.com */ +/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ + +/dts-v1/; + +#include "am33xx.dtsi" + +#include +#include + +/ { + model = "MYIR MYC-AM335X"; + compatible = "myir,myc-am335x", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd_core>; + voltage-tolerance = <2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + clk32k: clk32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + + #clock-cells = <0>; + }; + + vdd_mod: vdd_mod_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd-mod"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: vdd_core_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd-core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mod>; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_mod_pins>; + + led_mod: led_mod { + label = "module:user"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + color = ; + default-state = "off"; + panic-indicator; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_slave1_pins_default>; + pinctrl-1 = <ð_slave1_pins_sleep>; + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdio_pins_default>; + pinctrl-1 = <&mdio_pins_sleep>; + + phy0: ethernet-phy@4 { + reg = <4>; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&nand_pins_default>; + pinctrl-1 = <&nand_pins_sleep>; + ranges = <0 0 0x8000000 0x1000000>; + status = "okay"; + + nand0: nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>; + nand-bus-width = <8>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-pin = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + ti,elm-id = <&elm>; + ti,nand-ecc-opt = "bch8"; + }; +}; + +&i2c0 { + pinctrl-names = "default", "gpio", "sleep"; + pinctrl-0 = <&i2c0_pins_default>; + pinctrl-1 = <&i2c0_pins_gpio>; + pinctrl-2 = <&i2c0_pins_sleep>; + clock-frequency = <400000>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&vdd_mod>; + }; +}; + +&rtc { + clocks = <&clk32k>; + clock-names = "ext-clk"; + system-power-controller; +}; + +&am33xx_pinmux { + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */ + >; + }; + + mdio_pins_sleep: mdio-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + eth_slave1_pins_default: eth-slave1-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */ + >; + }; + + eth_slave1_pins_sleep: eth-slave1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */ + >; + }; + + i2c0_pins_gpio: i2c0-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */ + >; + }; + + i2c0_pins_sleep: i2c0-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + led_mod_pins: led-mod-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */ + >; + }; + + nand_pins_default: nand-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */ + >; + }; + + nand_pins_sleep: nand-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts new file mode 100644 index 000000000000..d3bba79b9358 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* SPDX-FileCopyrightText: Alexander Shiyan, */ +/* Based on code by myd_c335x.dts, MYiRtech.com */ +/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ + +/dts-v1/; + +#include "am335x-myirtech-myc.dtsi" + +#include +#include + +/ { + model = "MYIR MYD-AM335X"; + compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + clk12m: clk12m { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + + #clock-cells = <0>; + }; + + gpio_buttons: gpio_buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_buttons_pins>; + #address-cells = <1>; + #size-cells = <0>; + + button1: button@0 { + reg = <0>; + label = "button1"; + linux,code = ; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + }; + + button2: button@1 { + reg = <1>; + label = "button2"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&master_codec>; + simple-audio-card,frame-master = <&master_codec>; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + + master_codec: simple-audio-card,codec@1 { + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,codec@2 { + sound-dai = <&tda9988>; + }; + }; + + vdd_5v0: vdd_5v0_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3: vdd_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0>; + }; +}; + +&cpsw_port2 { + status = "okay"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + phy1: ethernet-phy@6 { + reg = <6>; + eee-broken-1000t; + }; +}; + +&mac_sw { + pinctrl-0 = <ð_slave1_pins_default>, <ð_slave2_pins_default>; + pinctrl-1 = <ð_slave1_pins_sleep>, <ð_slave2_pins_sleep>; + slaves = <2>; +}; + +&dcan0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan0_pins_default>; + pinctrl-1 = <&dcan0_pins_sleep>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan1_pins_default>; + pinctrl-1 = <&dcan1_pins_sleep>; + status = "okay"; +}; + +&ehrpwm0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ehrpwm0_pins_default>; + pinctrl-1 = <&ehrpwm0_pins_sleep>; + status = "okay"; +}; + +&epwmss0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio", "sleep"; + pinctrl-0 = <&i2c1_pins_default>; + pinctrl-1 = <&i2c1_pins_gpio>; + pinctrl-2 = <&i2c1_pins_sleep>; + clock-frequency = <400000>; + scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sgtl5000: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg =<0xa>; + clocks = <&clk12m>; + micbias-resistor-k-ohms = <4>; + micbias-voltage-m-volts = <2250>; + VDDA-supply = <&vdd_3v3>; + VDDIO-supply = <&vdd_3v3>; + + #sound-dai-cells = <0>; + }; + + tda9988: tda9988@70 { + compatible = "nxp,tda998x"; + reg =<0x70>; + audio-ports = ; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; +}; + +&lcdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_pins_default>; + pinctrl-1 = <&lcdc_pins_sleep>; + blue-and-red-wiring = "straight"; + status = "okay"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&leds { + pinctrl-0 = <&led_mod_pins &leds_pins>; + + led1: led1 { + label = "base:user1"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + color = ; + default-state = "off"; + }; + + led2: led2 { + label = "base:user2"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + color = ; + default-state = "off"; + }; +}; + +&mcasp0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp0_pins_default>; + pinctrl-1 = <&mcasp0_pins_sleep>; + op-mode = <0>; + tdm-slots = <2>; + serial-dir = <0 1 2 0>; + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; + + #sound-dai-cells = <0>; +}; + +&mmc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; + cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <&vdd_3v3>; + status = "okay"; +}; + +&nand0 { + nand_parts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MLO"; + reg = <0x00000 0x20000>; + }; + + partition@80000 { + label = "boot"; + reg = <0x80000 0x100000>; + }; + }; +}; + +&tscadc { + status = "okay"; + + adc: adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_pins_default>; + pinctrl-1 = <&uart1_pins_sleep>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_pins_default>; + pinctrl-1 = <&uart2_pins_sleep>; + status = "okay"; +}; + +&usb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; +}; + +&usb0 { + dr_mode = "otg"; +}; + +&usb0_phy { + vcc-supply = <&vdd_5v0>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&usb1_phy { + vcc-supply = <&vdd_5v0>; +}; + +&vdd_mod { + vin-supply = <&vdd_3v3>; +}; + +&am33xx_pinmux { + dcan0_pins_default: dcan0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ + >; + }; + + dcan0_pins_sleep: dcan0-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + dcan1_pins_default: dcan1-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ + >; + }; + + dcan1_pins_sleep: dcan1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + ehrpwm0_pins_default: ehrpwm0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ + >; + }; + + ehrpwm0_pins_sleep: ehrpwm0-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + eth_slave2_pins_default: eth-slave2-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */) + >; + }; + + eth_slave2_pins_sleep: eth-slave2-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + gpio_buttons_pins: gpio-buttons-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ + >; + }; + + i2c1_pins_default: i2c1-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ + >; + }; + + i2c1_pins_gpio: i2c1-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ + >; + }; + + i2c1_pins_sleep: i2c1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + lcdc_pins_default: lcdc-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */ + >; + }; + + lcdc_pins_sleep: lcdc-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + leds_pins: leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ + >; + }; + + mcasp0_pins_default: mcasp0-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */ + >; + }; + + mcasp0_pins_sleep: mcasp0-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */ + >; + }; + + mmc1_pins_sleep: mmc1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ + >; + }; + + uart1_pins_default: uart1-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ + >; + }; + + uart1_pins_sleep: uart1-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + uart2_pins_default: uart2-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ + >; + }; + + uart2_pins_sleep: uart2-sleep-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + usb_pins: usb-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ + AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-nano.dts b/arch/arm/boot/dts/ti/omap/am335x-nano.dts new file mode 100644 index 000000000000..a475c0d91306 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-nano.dts @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "Newflow AM335x NanoBone"; + compatible = "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "nanobone:green:usr1"; + gpios = <&gpio1 5 0>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&misc_pins>; + + misc_pins: misc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ + >; + }; + + gpmc_pins: gpmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ + + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ + >; + }; + + uart5_pins: uart5-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; + rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + gpio@20 { + compatible = "microchip,mcp23017"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + + tps: tps@24 { + reg = <0x24>; + }; + + temperature-sensor@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + pagesize = <8>; + }; + + rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + compatible = "ti,am3352-gpmc"; + status = "okay"; + gpmc,num-waitpins = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */ + <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */ + + nor@0,0 { + reg = <0 0x00000000 0x08000000>; + compatible = "cfi-flash"; + linux,mtd-name = "spansion,s29gl010p11t"; + bank-width = <2>; + + gpmc,mux-add-data = <2>; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <160>; + gpmc,cs-wr-off-ns = <160>; + gpmc,adv-on-ns = <10>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,oe-on-ns = <40>; + gpmc,oe-off-ns = <160>; + gpmc,we-on-ns = <40>; + gpmc,we-off-ns = <160>; + gpmc,rd-cycle-ns = <160>; + gpmc,wr-cycle-ns = <160>; + gpmc,access-ns = <150>; + gpmc,page-burst-access-ns = <10>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-delay-ns = <20>; + gpmc,wr-data-mux-bus-ns = <70>; + gpmc,wr-access-ns = <80>; + + #address-cells = <1>; + #size-cells = <1>; + + /* + MTD partition table + =================== + +------------+-->0x00000000-> U-Boot start + | | + | |-->0x000BFFFF-> U-Boot end + | |-->0x000C0000-> ENV1 start + | | + | |-->0x000DFFFF-> ENV1 end + | |-->0x000E0000-> ENV2 start + | | + | |-->0x000FFFFF-> ENV2 end + | |-->0x00100000-> Kernel start + | | + | |-->0x004FFFFF-> Kernel end + | |-->0x00500000-> File system start + | | + | |-->0x01FFFFFF-> File system end + | |-->0x02000000-> User data start + | | + | |-->0x03FFFFFF-> User data end + | |-->0x04000000-> Data storage start + | | + +------------+-->0x08000000-> NOR end (Free end) + */ + partition@0 { + label = "boot"; + reg = <0x00000000 0x000c0000>; /* 768KB */ + }; + + partition@1 { + label = "env1"; + reg = <0x000c0000 0x00020000>; /* 128KB */ + }; + + partition@2 { + label = "env2"; + reg = <0x000e0000 0x00020000>; /* 128KB */ + }; + + partition@3 { + label = "kernel"; + reg = <0x00100000 0x00400000>; /* 4MB */ + }; + + partition@4 { + label = "rootfs"; + reg = <0x00500000 0x01b00000>; /* 27MB */ + }; + + partition@5 { + label = "user"; + reg = <0x02000000 0x02000000>; /* 32MB */ + }; + + partition@6 { + label = "data"; + reg = <0x04000000 0x04000000>; /* 64MB */ + }; + }; + + fram@1,0 { + reg = <1 0x00000000 0x01000000>; + bank-width = <2>; + + gpmc,mux-add-data = <2>; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <160>; + gpmc,cs-wr-off-ns = <160>; + gpmc,adv-on-ns = <10>; + gpmc,adv-rd-off-ns = <20>; + gpmc,adv-wr-off-ns = <20>; + gpmc,oe-on-ns = <30>; + gpmc,oe-off-ns = <150>; + gpmc,we-on-ns = <30>; + gpmc,we-off-ns = <150>; + gpmc,rd-cycle-ns = <160>; + gpmc,wr-cycle-ns = <160>; + gpmc,access-ns = <130>; + gpmc,page-burst-access-ns = <10>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cycle2cycle-delay-ns = <10>; + gpmc,wr-data-mux-bus-ns = <30>; + gpmc,wr-access-ns = <0>; + }; +}; + +&mac_sw { + status = "okay"; +}; + +&davinci_mdio_sw { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "mii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "mii"; + ti,dual-emac-pvid = <2>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo4_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; + cd-debounce-delay-ms = <5>; + cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&usb0 { + dr_mode = "host"; +}; + +#include "../../tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + /* +1.5V voltage with ±4% tolerance */ + regulator-min-microvolt = <1450000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <915000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <915000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + /* +1.8V voltage with ±4% tolerance */ + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1870000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + /* +3.3V voltage with ±4% tolerance */ + regulator-min-microvolt = <3175000>; + regulator-max-microvolt = <3430000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + /* +1.8V voltage with ±4% tolerance */ + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1870000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + /* +3.3V voltage with ±4% tolerance */ + regulator-min-microvolt = <3175000>; + regulator-max-microvolt = <3430000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts new file mode 100644 index 000000000000..f7fad48e36ed --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" +#include "am335x-baltos-leds.dtsi" + +/ { + model = "NetCAN"; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@1 { + label = "can_data"; + linux,default-trigger = "netdev"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@2 { + label = "can_error"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + user_leds_s0: user-leds-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */ + >; + }; + + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */ + >; + }; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&davinci_mdio_sw { + phy0: ethernet-phy@0 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; + phy-handle = <&phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "can_data", + "can_error", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "DCAN1_TX", + "DCAN1_RX", + "CONSOLE_RX", + "CONSOLE_TX", + "NC", + "NC", + "NC", + "NC", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts new file mode 100644 index 000000000000..76751a324ad7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" +#include "am335x-baltos-leds.dtsi" + +/ { + model = "NetCom Plus"; +}; + +&am33xx_pinmux { + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ + >; + }; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&davinci_mdio_sw { + phy0: ethernet-phy@0 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; + phy-handle = <&phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; +}; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "NC", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts new file mode 100644 index 000000000000..5a9fcec040fa --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" + +/ { + model = "NetCom Plus"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&dip_switches>; + + dip_switches: dip-switches-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + tca6416_pins: tca6416-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) + >; + }; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&i2c1 { + tca6416a: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_IN4", "GP_IN5", "GP_IN6", "GP_IN7", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "GP_OUT4", "GP_OUT5", "GP_OUT6", "GP_OUT7"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tca6416b: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CH1_M0", "CH1_M1", "CH1_M2", "CH1_M3", + "CH2_M0", "CH2_M1", "CH2_M2", "CH2_M3", + "CH3_M0", "CH3_M1", "CH3_M2", "CH3_M3", + "CH4_M0", "CH4_M1", "CH4_M2", "CH4_M3"; + }; + + tca6416c: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CH5_M0", "CH5_M1", "CH5_M2", "CH5_M3", + "CH6_M0", "CH6_M1", "CH6_M2", "CH6_M3", + "CH7_M0", "CH7_M1", "CH7_M2", "CH7_M3", + "CH8_M0", "CH8_M1", "CH8_M2", "CH8_M3"; + }; +}; + +&davinci_mdio_sw { + phy0: ethernet-phy@0 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; + phy-handle = <&phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; +}; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "I2C2_SDA", + "I2C2_SCL", + "NC", + "NC", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "SW2_0_alt", + "SW2_1_alt", + "SW2_2_alt", + "SW2_3_alt", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "3G_PWR_EN", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts new file mode 100644 index 000000000000..d28d39728847 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts @@ -0,0 +1,434 @@ +//SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" +#include + +#include + +/ { + model = "Octavo Systems OSD3358-SM-RED"; + compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&lcdc { + status = "okay"; + + /* If you want to get 24 bit RGB and 16 BGR mode instead of + * current 16 bit RGB and 24 BGR modes, set the propety + * below to "crossed" and uncomment the video-ports -property + * in tda19988 node. + * AM335x errata for wiring: + * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf + */ + + blue-and-red-wiring = "straight"; + + port { + lcdc_0: endpoint { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: hdmi-encoder@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ + /* video-ports = <0x234501>; */ + + #sound-dai-cells = <0>; + audio-ports = < TDA998x_I2S 0x03>; + + port { + hdmi_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + + mpu9250: imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ax8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + }; + }; + /*invensense,int_config = <0x10>; + invensense,level_shifter = <0>; + invensense,orientation = [01 00 00 00 01 00 00 00 01]; + invensense,sec_slave_type = <0>; + invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ + }; + + bmp280: pressure@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk-mcasp0-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk-mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led2 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + flash_enable: flash-enable-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + >; + }; + + imu_interrupt: imu-interrupt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + >; + }; + + ethernet_interrupt: ethernet-interrupt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + + user_leds_s0: user-leds-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + clkout2_pin: pinmux-clkout2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + emmc_pins: pinmux-emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-txid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@4 { + reg = <4>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&rtc { + system-power-controller; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi new file mode 100644 index 000000000000..9863bf499a39 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author: Robert Nelson + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&cpu0_opp_table { + /* + * Octavo Systems: + * The EFUSE_SMA register is not programmed for any of the AM335x wafers + * we get and we are not programming them during our production test. + * Therefore, from a DEVICE_ID revision point of view, the silicon looks + * like it is Revision 2.1. However, from an EFUSE_SMA point of view for + * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the + * EFUSE_SMA register reads as all zeros). + */ + oppnitro-1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux-i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; +}; + +/include/ "../../tps65217.dtsi" + +&tps { + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + + ti,pmic-shutdown-controller; + + pwrbutton { + interrupts = <2>; + status = "okay"; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi b/arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi new file mode 100644 index 000000000000..75efe1cf1dd2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2017 Phytec Messtechnik GmbH + * Author: Wadim Egorov + * Teresa Remmet + */ + +#include + +/ { + model = "Phytec AM335x PCM-953"; + compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"; + + /* Power */ + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + vcc1v8: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* User IO */ + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + user-led0 { + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led1 { + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + user_buttons: user-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_buttons_pins>; + + button-0 { + label = "home"; + linux,code = ; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + button-1 { + label = "menu"; + linux,code = ; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + }; +}; + +&am33xx_pinmux { + user_buttons_pins: pinmux-user-buttons-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ + >; + }; + + user_leds_pins: pinmux-user-leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ + >; + }; +}; + +/* CAN */ +&am33xx_pinmux { + dcan1_pins: pinmux-dcan1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: ethernet1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; +}; + +&cpsw_port2 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + status = "okay"; +}; + +&davinci_mdio_sw { + phy1: ethernet-phy@2 { + reg = <2>; + }; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; +}; + +/* Misc */ +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&cb_gpio_pins>; + + cb_gpio_pins: pinmux-cb-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + >; + }; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: pinmux-uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart2_pins: pinmux-uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + >; + }; + + uart3_pins: pinmux-uart3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +/* USB */ +&usb1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts new file mode 100644 index 000000000000..3c9444e98c14 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -0,0 +1,573 @@ +/* + * pdu001.dts + * + * EETS GmbH PDU001 board device tree file + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "EETS,PDU001"; + compatible = "ti,am33xx"; + + chosen { + stdout-path = &uart3; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + panel { + compatible = "ti,tilcdc,panel"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins_s0>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + 240x320p16 { + clock-frequency = <6500000>; + hactive = <240>; + vactive = <320>; + hfront-porch = <6>; + hback-porch = <6>; + hsync-len = <1>; + vback-porch = <6>; + vfront-porch = <6>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + de-active = <0>; + }; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ + >; + }; + + spi1_pins: spi1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + >; + }; + + clkout2_pin: clkout2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Port 1 (emac0) */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) + + /* Port 2 (emac1) */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc1_pins: mmc1-pins { + /* eMMC */ + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc2_pins: mmc2-pins { + /* SD cardcage */ + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + /* card change signal for frontpanel SD cardcage */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + >; + }; + + lcd_pins_s0: lcd-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + dcan0_pins: dcan0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rts-delay = <0 0>; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + m2_eeprom: m2_eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + board_24aa025e48: board_24aa025e48@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + backplane_24aa025e48: backplane_24aa025e48@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + reg = <0x60>; + psc0 = <0x97>; + pwm0 = <0x80>; + psc1 = <0x97>; + pwm1 = <0x10>; + + run.red@0 { + type = ; + }; + run.green@1 { + type = ; + default-state = "on"; + }; + s2.red@2 { + type = ; + }; + s2.green@3 { + type = ; + }; + s1.yellow@4 { + type = ; + }; + s1.green@5 { + type = ; + }; + }; + + pca9530: pca9530@61 { + compatible = "nxp,pca9530"; + reg = <0x61>; + + tft-panel@0 { + type = ; + linux,default-trigger = "backlight"; + default-state = "on"; + }; + }; + + mcp79400: rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + display-controller@0 { + compatible = "orisetech,otm3225a"; + reg = <0>; + spi-max-frequency = <1000000>; + // SPI mode 3 + spi-cpol; + spi-cpha; + status = "okay"; + }; +}; + +/* + * Disable soc's rtc as we have no VBAT for it. This makes the board + * rtc (Microchip MCP79400) the default rtc device 'rtc0'. + */ +&rtc { + status = "disabled"; +}; + +&lcdc { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-name = "ldo_vrtc"; + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-name = "buck_vdd_ddr"; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits */ + regulator-name = "buck_vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits */ + regulator-name = "buck_vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-name = "boost_res"; + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-name = "ldo_vdig1"; + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-name = "ldo_vdig2"; + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-name = "ldo_vpll"; + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-name = "ldo_vdac"; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-name = "ldo_vaux1"; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-name = "ldo_vaux2"; + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-name = "ldo_vaux33"; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-name = "ldo_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vbb_reg: regulator@13 { + regulator-name = "bat_vbb"; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "mii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "mii"; + ti,dual-emac-pvid = <2>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x01 0x10 0x22 0x33>; + ti,charge-delay = <0x400>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + non-removable; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts new file mode 100644 index 000000000000..d5a4a21889d1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ + */ +/dts-v1/; + +#include +#include "am33xx.dtsi" + +/ { + model = "Gumstix Pepper"; + compatible = "gumstix,am335x-pepper", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc3_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + buttons: user_buttons { + compatible = "gpio-keys"; + }; + + leds: user-leds-pins { + compatible = "gpio-leds"; + }; + + panel: lcd_panel { + compatible = "ti,tilcdc,panel"; + }; + + sound: sound_iface { + compatible = "ti,da830-evm-audio"; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + }; + + v3v3c_reg: fixedregulator1 { + compatible = "regulator-fixed"; + }; + + vdd5_reg: fixedregulator2 { + compatible = "regulator-fixed"; + }; +}; + +/* I2C Busses */ +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + audio_codec: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <0x2>; + }; + + accel: lis331dlh@1d { + compatible = "st,lis3lv02d"; + reg = <0x1d>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; +}; + +&am33xx_pinmux { + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ + >; + }; +}; + +/* Accelerometer */ +&accel { + pinctrl-names = "default"; + pinctrl-0 = <&accel_pins>; + + Vdd-supply = <&ldo3_reg>; + Vdd_IO-supply = <&ldo3_reg>; + st,irq1-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <92>; + st,max-limit-x = <14>; + st,min-limit-y = <14>; + st,max-limit-y = <92>; + st,min-limit-z = <92>; + st,max-limit-z = <14>; +}; + +&am33xx_pinmux { + accel_pins: accel-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ + >; + }; +}; + +/* Audio */ +&audio_codec { + status = "okay"; + + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + AVDD-supply = <&ldo3_reg>; + IOVDD-supply = <&ldo3_reg>; + DRVDD-supply = <&ldo3_reg>; + DVDD-supply = <&dcdc1_reg>; +}; + +&sound { + ti,model = "AM335x-EVM"; + ti,audio-codec = <&audio_codec>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3L", "Mic3L Switch"; +}; + +&mcasp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; + + op-mode = <0>; /* MCASP_ISS_MODE */ + tdm-slots = <2>; + serial-dir = < + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&am33xx_pinmux { + audio_pins: audio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) /* gpmc_a0.gpio1_16 */ + >; + }; +}; + +/* Display: 24-bit LCD Screen */ +&panel { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <18400000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vfront-porch = <4>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; +}; + +&lcdc { + status = "okay"; +}; + +&am33xx_pinmux { + lcd_pins: lcd-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + /* Display Enable */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; +}; + +/* Ethernet */ +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac_sw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; +}; + +&am33xx_pinmux { + ethernet_pins: ethernet-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2) + /* ethernet interrupt */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7) /* rmii2_refclk.gpio0_29 */ + /* ethernet PHY nReset */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + + mdio_pins: mdio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +/* MMC */ +&mmc1 { + /* Bootable SD card slot */ + status = "okay"; + vmmc-supply = <&ldo3_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc2 { + /* eMMC (not populated) on MMC #2 */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&ldo3_reg>; + bus-width = <8>; + non-removable; +}; + +&mmc3 { + /* Wifi & Bluetooth on MMC #3 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wireless_pins>; + vmmmc-supply = <&v3v3c_reg>; + bus-width = <4>; + non-removable; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; +}; + + +&am33xx_pinmux { + sd_pins: sd-card-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + emmc_pins: emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + /* EMMC nReset */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + >; + }; + wireless_pins: wireless-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc1_clk */ + /* WLAN nReset */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ + /* WLAN nPower down */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + /* 32kHz Clock */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&v3v3c_reg { + regulator-name = "v3v3c_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbat>; +}; + +&vdd5_reg { + regulator-name = "vdd5_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbat>; +}; + +/include/ "../../tps65217.dtsi" + +&tps { + backlight { + isel = <1>; /* ISET1 */ + fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ + default-brightness = <80>; + }; + + regulators { + dcdc1_reg: regulator@0 { + /* VDD_1V8 system supply */ + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + /* VRTC 1.8V always-on supply */ + regulator-name = "vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + /* 3.3V rail */ + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + /* VDD_3V3A 3.3V rail */ + regulator-name = "vdd_3v3a"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_reg: regulator@6 { + /* VDD_3V3B 3.3V rail */ + regulator-name = "vdd_3v3b"; + regulator-always-on; + }; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&am33xx_pinmux { + spi0_pins: spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +/* Touch Screen */ +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +/* UARTs */ +&uart0 { + /* Serial Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* Broken out to J6 header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&am33xx_pinmux { + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +/* USB */ +&usb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&am33xx_pinmux { + usb_pins: usb-pins { + pinctrl-single,pins = < + /* USB0 Over-Current (active low) */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ + /* USB1 Over-Current (active low) */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ + >; + }; +}; + +/* User IO */ +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + led0 { + label = "pepper:user0:blue"; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led1 { + label = "pepper:user1:red"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&user_buttons_pins>; + + button-0 { + label = "home"; + linux,code = ; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-1 { + label = "menu"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-2 { + label = "power"; + linux,code = ; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; +}; + +&am33xx_pinmux { + user_leds_pins: user-leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + >; + }; + + user_buttons_pins: user-buttons-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio0_7 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts new file mode 100644 index 000000000000..43907d03e675 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-pcm-953.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&serial_flash { + status = "okay"; + +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi b/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi new file mode 100644 index 000000000000..84c15a44df6a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include "am33xx.dtsi" +#include + +/ { + model = "Phytec AM335x phyCORE"; + compatible = "phytec,am335x-phycore-som", "ti,am33xx"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &rtc; + rtc2 = &tps; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vcc5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +/* Crypto Module */ +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +/* EMMC */ +&am33xx_pinmux { + emmc_pins: pinmux-emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&vmmc_reg>; + bus-width = <8>; + non-removable; + status = "disabled"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet0_pins: ethernet0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + mdio_pins: mdio-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&cpsw_port1 { + phy-handle = <&phy0>; + phy-mode = "rmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins>; + status = "okay"; +}; + +/* I2C Busses */ +&am33xx_pinmux { + i2c0_pins: pinmux-i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tps: pmic@2d { + reg = <0x2d>; + }; + + i2c_tmp102: temp@4b { + compatible = "ti,tmp102"; + reg = <0x4b>; + status = "disabled"; + }; + + i2c_eeprom: eeprom@52 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x52>; + status = "disabled"; + }; + + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + status = "disabled"; + }; +}; + +/* NAND memory */ +&am33xx_pinmux { + nandflash_pins: pinmux-nandflash-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ + nandflash: nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,cycle2cycle-diffcsen; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <30>; + gpmc,wr-data-mux-bus-ns = <0>; + + ti,elm-id = <&elm>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* Power */ +#include "../../tps65910.dtsi" + +&tps { + vcc1-supply = <&vcc5v>; + vcc2-supply = <&vcc5v>; + vcc3-supply = <&vcc5v>; + vcc4-supply = <&vcc5v>; + vcc5-supply = <&vcc5v>; + vcc6-supply = <&vcc5v>; + vcc7-supply = <&vcc5v>; + vccio-supply = <&vcc5v>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-name = "vdig1_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* SPI Busses */ +&am33xx_pinmux { + spi0_pins: pinmux-spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <48000000>; + reg = <0x0>; + m25p,fast-read; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts new file mode 100644 index 000000000000..5dfe4d4bab93 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author: Robert Nelson + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" + +/ { + model = "TI AM335x PocketBeagle"; + compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&usr_leds_pins>; + + compatible = "gpio-leds"; + + led-usr0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-usr1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led-usr2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led-usr3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gpio0 { + gpio-line-names = + "NC", + "NC", + "P1.08 [SPI0_CLK]", + "P1.10 [SPI0_MISO]", + "P1.12 [SPI0_MOSI]", + "P1.06 [SPI0_CS]", + "[MMC0_CD]", + "P2.29 [SPI1_CLK]", + "[SYSBOOT 12]", + "[SYSBOOT 13]", + "[SYSBOOT 14]", + "[SYSBOOT 15]", + "P1.26 [I2C2_SDA]", + "P1.28 [I2C2_SCL]", + "P2.11 [I2C1_SDA]", + "P2.09 [I2C1_SCL]", + "NC", + "NC", + "NC", + "P2.31 [SPI1_CS]", + "P1.20 [PRU0.16]", + "NC", + "NC", + "P2.03", + "NC", + "NC", + "P1.34", + "P2.19", + "NC", + "NC", + "P2.05 [UART4_RX]", + "P2.07 [UART4_TX]"; +}; + +&gpio1 { + gpio-line-names = + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "P2.25 [SPI1_MOSI]", + "P1.32 [UART0_RX]", + "P1.30 [UART0_TX]", + "P2.24", + "P2.33", + "P2.22", + "P2.18", + "NC", + "NC", + "P2.01 [PWM1A]", + "NC", + "P2.10", + "[USR LED 0]", + "[USR LED 1]", + "[USR LED 2]", + "[USR LED 3]", + "P2.06", + "P2.04", + "P2.02", + "P2.08", + "NC", + "NC", + "NC"; +}; + +&gpio2 { + gpio-line-names = + "P2.20", + "P2.17", + "NC", + "NC", + "NC", + "[EEPROM_WP]", + "[SYSBOOT 0]", + "[SYSBOOT 1]", + "[SYSBOOT 2]", + "[SYSBOOT 3]", + "[SYSBOOT 4]", + "[SYSBOOT 5]", + "[SYSBOOT 6]", + "[SYSBOOT 7]", + "[SYSBOOT 8]", + "[SYSBOOT 9]", + "[SYSBOOT 10]", + "[SYSBOOT 11]", + "NC", + "NC", + "NC", + "NC", + "P2.35 [AIN5]", + "P1.02 [AIN6]", + "P1.35 [PRU1.10]", + "P1.04 [PRU1.11]", + "[MMC0_DAT3]", + "[MMC0_DAT2]", + "[MMC0_DAT1]", + "[MMC0_DAT0]", + "[MMC0_CLK]", + "[MMC0_CMD]"; +}; + +&gpio3 { + gpio-line-names = + "NC", + "NC", + "NC", + "NC", + "NC", + "[I2C0_SDA]", + "[I2C0_SCL]", + "[JTAG EMU0]", + "[JTAG EMU1]", + "NC", + "NC", + "NC", + "NC", + "P1.03 [USB1]", + "P1.36 [PWM0A]", + "P1.33 [PRU0.1]", + "P2.32 [PRU0.2]", + "P2.30 [PRU0.3]", + "P1.31 [PRU0.4]", + "P2.34 [PRU0.5]", + "P2.28 [PRU0.6]", + "P1.29 [PRU0.7]", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; + +&am33xx_pinmux { + + compatible = "pinconf-single"; + pinctrl-names = "default"; + + pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio + &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio + &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio + &P2_17_gpio >; + + /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ + P2_03_gpio: P2-03-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ + P1_34_gpio: P1-34-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ + P2_19_gpio: P2-19-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ + P2_24_gpio: P2-24-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ + P2_33_gpio: P2-33-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ + P2_22_gpio: P2-22-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ + P2_18_gpio: P2-18-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ + P2_10_gpio: P2-10-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ + P2_06_gpio: P2-06-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ + P2_04_gpio: P2-04-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ + P2_02_gpio: P2-02-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ + P2_08_gpio: P2-08-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>; + }; + + /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ + P2_17_gpio: P2-17-gpio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + >; + }; + + ehrpwm0_pins: pinmux-ehrpwm0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ + >; + }; + + ehrpwm1_pins: pinmux-ehrpwm1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ + >; + }; + + mmc0_pins: pinmux-mmc0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + spi0_pins: pinmux-spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + spi1_pins: pinmux-spi1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ + >; + }; + + usr_leds_pins: pinmux-usr-leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + >; + }; + + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart4_pins: pinmux-uart4-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ + >; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ehrpwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm0_pins>; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm1_pins>; +}; + +&i2c0 { + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&rtc { + system-power-controller; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + ti,chan-step-avg = <16 16 16 16 16 16 16 16>; + ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; + ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&usb0 { + dr_mode = "otg"; +}; + +&usb1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts new file mode 100644 index 000000000000..66a1360b83d5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet + * + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-regor.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&serial_flash { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi new file mode 100644 index 000000000000..625db3bcd365 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet + * + */ + +/ { + model = "Phytec AM335x phyBOARD-REGOR"; + compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; + + vcc3v3: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* User IO */ + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + run_stop-led { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + error-led { + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + }; +}; + +/* User Leds */ +&am33xx_pinmux { + user_leds_pins: pinmux-user-leds-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ + >; + }; +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux-dcan1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux-ethernet1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_port2 { + status = "okay"; + phy-handle = <&phy1>; + phy-mode = "mii"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; +}; + +/* GPIOs */ +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&user_gpios_pins>; + + user_gpios_pins: pinmux-user-gpios-pins { + pinctrl-single,pins = < + /* DIGIN 1-4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ + /* DIGOUT 1-4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + >; + }; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* RTC */ +&i2c_rtc { + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart2_pins: pinmux-uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +/* RS485 - UART1 */ +&am33xx_pinmux { + uart1_rs485_pins: pinmux-uart1-rs485-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rs485_pins>; + status = "okay"; + linux,rs485-enabled-at-boot-time; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi new file mode 100644 index 000000000000..a138eb356874 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&am33xx_pinmux { + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + usb_hub_ctrl: usb-hub-ctrl-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ + >; + }; +}; + +&mac_sw { + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-id"; +}; + +&i2c0 { + usb2512b: usb-hub@2c { + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_ctrl>; + compatible = "microchip,usb2512b"; + reg = <0x2c>; + reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts new file mode 100644 index 000000000000..5522759def26 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Sancloud Ltd + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" +#include + +/ { + model = "SanCloud BeagleBone Enhanced Extended WiFi"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + }; +}; + +&am33xx_pinmux { + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + /* gpmc_a9.gpio1_25: RADIO_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) + + /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_clk.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + bluetooth_pins: bluetooth-pins { + pinctrl-single,pins = < + /* event_intr0.gpio0_19 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + /* uart1_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + + /* uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + + /* uart1_ctsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&mmc3 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + ti,needs-special-hs-handling; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + clock-frequency = <50000000>; + max-frequency = <50000000>; +}; + +&uart1 { + status = "okay"; + + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins &bluetooth_pins>; + compatible = "qcom,qca6174-bt"; + enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; + interrupt-parent = <&gpio0>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts new file mode 100644 index 000000000000..b1b400226d83 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 SanCloud Ltd + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" + +/ { + model = "SanCloud BeagleBone Enhanced Lite"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; +}; + +&am33xx_pinmux { + bb_spi0_pins: bb-spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) + >; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bb_spi0_pins>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "micron,spi-authenta"; + + reg = <0>; + spi-max-frequency = <16000000>; + spi-cpha; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts new file mode 100644 index 000000000000..32669346cefe --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" +#include + +/ { + model = "SanCloud BeagleBone Enhanced"; + compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&am33xx_pinmux { + mpu6050_pins: mpu6050-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ + >; + }; + + lps3331ap_pins: lps3331ap-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ + >; + }; +}; + +&i2c0 { + lps331ap: barometer@5c { + pinctrl-names = "default"; + pinctrl-0 = <&lps3331ap_pins>; + compatible = "st,lps331ap-press"; + st,drdy-int-pin = <1>; + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + }; + + mpu6050: accelerometer@68 { + pinctrl-names = "default"; + pinctrl-0 = <&mpu6050_pins>; + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + orientation = <0xff 0 0 0 1 0 0 0 0xff>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts new file mode 100644 index 000000000000..596774c84744 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 + * + * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + */ + +#include "am335x-cm-t335.dts" + +/ { + model = "CompuLab CM-T335 on SB-T335"; + compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"; + + /* DRM display driver */ + panel { + compatible = "ti,tilcdc,panel"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + /* Timing selection performed by U-Boot */ + timing0: lcd {/* 800x480p62 */ + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <39>; + hback-porch = <39>; + hsync-len = <47>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + timing1: dvi { /* 1024x768p60 */ + clock-frequency = <65000000>; + hactive = <1024>; + hfront-porch = <24>; + hback-porch = <160>; + hsync-len = <136>; + vactive = <768>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; +}; + +&am33xx_pinmux { + /* Display */ + lcd_pins_default: lcd-default-pins { + pinctrl-single,pins = < + /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + lcd_pins_sleep: lcd-sleep-pins { + pinctrl-single,pins = < + /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; +}; + +&i2c0 { + /* GPIO extender */ + gpio_ext: pca9555@26 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x26>; + dvi-ena-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "dvi-enable"; + }; + lcd-ena-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "lcd-enable"; + }; + }; +}; + +/* Display */ +&lcdc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-shc.dts b/arch/arm/boot/dts/ti/omap/am335x-shc.dts new file mode 100644 index 000000000000..9297cb1efcd4 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-shc.dts @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * support for the bosch am335x based shc c3 board + * + * Copyright, C) 2015 Heiko Schocher + * + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include + +/ { + model = "Bosch SHC"; + compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx"; + + aliases { + mmcblk0 = &mmc1; + mmcblk1 = &mmc2; + }; + + cpus { + cpu@0 { + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 594000 1225000 + 294000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ + cpu0-supply = <&dcdc2_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + back-button { + label = "Back Button"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <1000>; + wakeup-source; + }; + + front-button { + label = "Front Button"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <1000>; + wakeup-source; + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led1 { + label = "shc:power:red"; + gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "shc:power:bl"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + default-state = "on"; + }; + + led3 { + label = "shc:lan:red"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led4 { + label = "shc:lan:bl"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led5 { + label = "shc:cloud:red"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led6 { + label = "shc:cloud:bl"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&aes { + status = "okay"; +}; + +&epwmss1 { + status = "okay"; + + ehrpwm1: pwm@200 { + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm1_pins>; + status = "okay"; + }; +}; + +&gpio1 { + hmtc-rst-hog { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + output-high; + line-name = "homematic_reset"; + }; + + hmtc-prog-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_LOW>; + output-high; + line-name = "homematic_program"; + }; +}; + +&gpio3 { + zgb-rst-hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_LOW>; + output-low; + line-name = "zigbee_reset"; + }; + + zgb-boot-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "zigbee_boot"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + at24@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&cpsw_port1 { + phy-mode = "mii"; + phy-handle = <ðernetphy0>; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethernetphy0: ethernet-phy@0 { + reg = <0>; + smsc,disable-energy-detect; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <0x4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + cd-inverted; + max-frequency = <26000000>; + vmmc-supply = <&vmmcsd_fixed>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + max-frequency = <26000000>; + sd-uhs-sdr25; + vmmc-supply = <&vmmcsd_fixed>; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + bus-width = <4>; + cap-power-off-card; + max-frequency = <26000000>; + sd-uhs-sdr25; + vmmc-supply = <&vmmcsd_fixed>; + status = "okay"; +}; + +&rtc { + ti,no-init; +}; + +&sham { + status = "okay"; +}; + +&tps { + compatible = "ti,tps65217"; + ti,pmic-shutdown-controller; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-name = "vdds_dpr"; + regulator-compatible = "dcdc1"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1450000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + /* + * VDD_MPU voltage limits 0.95V - 1.26V with + * +/-4% tolerance + */ + regulator-compatible = "dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <70000>; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + /* + * VDD_CORE voltage limits 0.95V - 1.1V with + * +/-4% tolerance + */ + regulator-name = "vdd_core"; + regulator-compatible = "dcdc3"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1125000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-name = "vio,vrtc,vdds"; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-name = "vdd_3v3aux"; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-name = "vdd_1v8"; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-name = "vdd_3v3a"; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + clkout2_pin: clkout2-pins { + pinctrl-single,pins = < + /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + ehrpwm1_pins: ehrpwm1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ + >; + }; + + emmc_pins: emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) + >; + }; + + user_leds_s0: user-leds-s0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts new file mode 100644 index 000000000000..1115c812f6c8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -0,0 +1,721 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "Toby Churchill SL50 Series"; + compatible = "tcl,am335x-sl50", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + chosen { + stdout-path = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led0 { + label = "sl50:red:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led1 { + label = "sl50:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "sl50:red:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "sl50:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + backlight0: disp0 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight0_pins>; + pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_sys_reg>; + }; + + backlight1: disp1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight1_pins>; + pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_sys_reg>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* audio external oscillator */ + audio_mclk_fixed: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; /* 24.576MHz */ + }; + + audio_mclk: audio_mclk_gate@0 { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_mclk_pins>; + clocks = <&audio_mclk_fixed>; + enable-gpios = <&gpio1 27 0>; + }; + }; + + panel: lcd_panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + tft-alt-mode = <0>; + mono-8bit-mode = <0>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 960x128 { + clock-frequency = <18000000>; + hactive = <960>; + vactive = <272>; + + hback-porch = <40>; + hfront-porch = <16>; + hsync-len = <24>; + hsync-active = <0>; + + vback-porch = <3>; + vfront-porch = <8>; + vsync-len = <4>; + vsync-active = <0>; + }; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "sound-card"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pa_pins>; + + widgets = "Headphone", "Headphone Jack", + "Speaker", "Speaker External", + "Line", "Line In", + "Microphone", "Microphone Jack"; + + routing = "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Amplifier", "MONO_LOUT", + "Speaker External", "Amplifier", + "LINE1R", "Line In", + "LINE1L", "Line In", + "MIC3L", "Microphone Jack", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + dais = <&cpu_port>; + + pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + emmc_pwrseq: pwrseq@0 { + compatible = "mmc-pwrseq-emmc"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pwrseq_pins>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; + + vdd_sys_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_sys_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&lwb_pins>; + + audio_pins: audio-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + >; + }; + + audio_pa_pins: audio-pa-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ + >; + }; + + audio_mclk_pins: audio-mclk-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; + + backlight0_pins: backlight0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ + >; + }; + + backlight1_pins: backlight1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + led_pins: led-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + /* Ethernet */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + >; + }; + + emmc_pwrseq_pins: emmc-pwrseq-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ + >; + }; + + emmc_pins: emmc-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; + + ehrpwm1_pins: ehrpwm1a-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ + >; + }; + + rtc0_irq_pins: rtc0-irq-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ + >; + }; + + lwb_pins: lwb-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ + /* PDI Bus - Battery system */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ + /* FPGA */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc0_irq_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ + wakeup-source; + trickle-resistor-ohms = <2000>; + reg = <0x68>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + gpio_exp: mcp23017@20 { + compatible = "microchip,mcp23017"; + reg = <0x20>; + }; + +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; + + audio_codec: tlv320aic3106@1b { + status = "okay"; + compatible = "ti,tlv320aic3106"; + #sound-dai-cells = <0>; + reg = <0x1b>; + ai3x-micbias-vg = <2>; /* 2.5V */ + + AVDD-supply = <&ldo4_reg>; + IOVDD-supply = <&ldo4_reg>; + DRVDD-supply = <&ldo4_reg>; + DVDD-supply = <&ldo3_reg>; + + codec_port: port { + codec_endpoint: endpoint { + remote-endpoint = <&cpu_endpoint>; + clocks = <&audio_mclk>; + }; + }; + }; + + /* Ambient Light Sensor */ + als: isl29023@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + }; +}; + +&rtc { + status = "disabled"; +}; + +&usb0 { + dr_mode = "otg"; +}; + +&usb1 { + dr_mode = "host"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; + cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + vmmc-supply = <&vmmcsd_fixed>; + mmc-pwrseq = <&emmc_pwrseq>; +}; + +&mcasp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; + #sound-dai-cells = <0>; + op-mode = <0>; /* MCASP_ISS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; + + cpu_port: port { + cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + + dai-format = "dsp_b"; + bitclock-master = <&codec_port>; + frame-master = <&codec_port>; + bitclock-inversion; + clocks = <&audio_mclk>; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + flash: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q032"; + reg = <1>; + spi-max-frequency = <5000000>; + }; +}; + +#include "../../tps65217.dtsi" + +&tps { + ti,pmic-shutdown-controller; + + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + regulators { + dcdc1_reg: regulator@0 { + /* VDDS_DDR */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + /* VRTC / VIO / VDDS*/ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2_reg: regulator@4 { + /* VDD_3V3AUX */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo3_reg: regulator@5 { + /* VDD_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + /* VDD_3V3A */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&cpsw_port1 { + phy-mode = "mii"; + phy-handle = <ðphy0>; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mac_sw { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <100>; /* PHY datasheet states 100us min */ + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm1_pins>; +}; + +&lcdc { + status = "okay"; +}; + +&tscadc { + status = "okay"; +}; + +&am335x_adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts new file mode 100644 index 000000000000..866b5f0cbfbc --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-wega.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-wega.dtsi b/arch/arm/boot/dts/ti/omap/am335x-wega.dtsi new file mode 100644 index 000000000000..cb27ff464dbe --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-wega.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet + */ + +/ { + model = "Phytec AM335x phyBOARD-WEGA"; + compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-wega"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_iface_main>; + simple-audio-card,frame-master = <&sound_iface_main>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + + sound_iface_main: simple-audio-card,codec { + sound-dai = <&tlv320aic3007>; + clocks = <&mcasp0_fck>; + }; + + }; + + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +/* Audio */ +&am33xx_pinmux { + mcasp0_pins: pinmux-mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c0 { + tlv320aic3007: tlv320aic3007@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + AVDD-supply = <&vcc3v3>; + IOVDD-supply = <&vcc3v3>; + DRVDD-supply = <&vcc3v3>; + DVDD-supply = <&vdig1_reg>; + status = "okay"; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < + 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ + >; + tx-num-evt = <16>; + rx-num-evt = <16>; + status = "okay"; +}; + + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux-dcan1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux-ethernet1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_port2 { + status = "okay"; + phy-handle = <&phy1>; + phy-mode = "mii"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Power */ +&vdig1_reg { + regulator-boot-on; + regulator-always-on; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: pinmux-uart1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi new file mode 100644 index 000000000000..d34483ae1778 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for AM33xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&scm_clocks { + sys_clkin_ck: clock-sys-clkin-22@40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <22>; + reg = <0x0040>; + }; + + adc_tsc_fck: clock-adc-tsc-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan0_fck: clock-dcan0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan1_fck: clock-dcan1-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp0_fck: clock-mcasp0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp1_fck: clock-mcasp1-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex0_fck: clock-smartreflex0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex1_fck: clock-smartreflex1-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sha0_fck: clock-sha0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes0_fck: clock-aes0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + rng_fck: clock-rng-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + clock@664 { + compatible = "ti,clksel"; + reg = <0x664>; + #clock-cells = <2>; + #address-cells = <0>; + + ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + }; + + ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + }; + + ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + }; + }; +}; +&prcm_clocks { + clk_32768_ck: clock-clk-32768 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; + clock-frequency = <32768>; + }; + + clk_rc32k_ck: clock-clk-rc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; + clock-frequency = <32000>; + }; + + virt_19200000_ck: clock-virt-19200000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; + clock-frequency = <19200000>; + }; + + virt_24000000_ck: clock-virt-24000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; + clock-frequency = <24000000>; + }; + + virt_25000000_ck: clock-virt-25000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; + clock-frequency = <25000000>; + }; + + virt_26000000_ck: clock-virt-26000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; + clock-frequency = <26000000>; + }; + + tclkin_ck: clock-tclkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; + clock-frequency = <12000000>; + }; + + dpll_core_ck: clock@490 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; + }; + + dpll_core_x2_ck: clock-dpll-core-x2 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m4_ck: clock-dpll-core-m4@480 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0480>; + ti,index-starts-at-one; + }; + + dpll_core_m5_ck: clock-dpll-core-m5@484 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0484>; + ti,index-starts-at-one; + }; + + dpll_core_m6_ck: clock-dpll-core-m6@4d8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x04d8>; + ti,index-starts-at-one; + }; + + dpll_mpu_ck: clock@488 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; + }; + + dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + reg = <0x04a8>; + ti,index-starts-at-one; + }; + + dpll_ddr_ck: clock@494 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_ddr_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; + }; + + dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + reg = <0x04a0>; + ti,index-starts-at-one; + }; + + dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_ddr_m2_div2_ck"; + clocks = <&dpll_ddr_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_disp_ck: clock@498 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_disp_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; + }; + + dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; + clocks = <&dpll_disp_ck>; + ti,max-div = <31>; + reg = <0x04a4>; + ti,index-starts-at-one; + ti,set-rate-parent; + }; + + dpll_per_ck: clock@48c { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-j-type-clock"; + clock-output-names = "dpll_per_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; + }; + + dpll_per_m2_ck: clock-dpll-per-m2@4ac { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + reg = <0x04ac>; + ti,index-starts-at-one; + }; + + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + clk_24mhz: clock-clk-24mhz { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + clkdiv32k_ck: clock-clkdiv32k { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; + clocks = <&clk_24mhz>; + clock-mult = <1>; + clock-div = <732>; + }; + + l3_gclk: clock-l3-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; + clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; + reg = <0x0530>; + }; + + mmu_fck: clock-mmu-fck-1@914 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "mmu_fck"; + clocks = <&dpll_core_m4_ck>; + ti,bit-shift = <1>; + reg = <0x0914>; + }; + + timer1_fck: clock-timer1-fck@528 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; + clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; + reg = <0x0528>; + }; + + timer2_fck: clock-timer2-fck@508 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x0508>; + }; + + timer3_fck: clock-timer3-fck@50c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x050c>; + }; + + timer4_fck: clock-timer4-fck@510 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x0510>; + }; + + timer5_fck: clock-timer5-fck@518 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x0518>; + }; + + timer6_fck: clock-timer6-fck@51c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x051c>; + }; + + timer7_fck: clock-timer7-fck@504 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x0504>; + }; + + usbotg_fck: clock-usbotg-fck-8@47c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usbotg_fck"; + clocks = <&dpll_per_ck>; + ti,bit-shift = <8>; + reg = <0x047c>; + }; + + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + ieee5000_fck: clock-ieee5000-fck-1@e4 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ieee5000_fck"; + clocks = <&dpll_core_m4_div2_ck>; + ti,bit-shift = <1>; + reg = <0x00e4>; + }; + + wdt1_fck: clock-wdt1-fck@538 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; + clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x0538>; + }; + + l4_rtc_gclk: clock-l4-rtc-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4_rtc_gclk"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + l4hs_gclk: clock-l4hs-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3s_gclk: clock-l3s-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4fw_gclk: clock-l4fw-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4fw_gclk"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4ls_gclk: clock-l4ls-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sysclk_div_ck: clock-sysclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div_ck"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; + clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; + reg = <0x0520>; + }; + + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + reg = <0x053c>; + }; + + lcd_gclk: clock-lcd-gclk@534 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "lcd_gclk"; + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; + reg = <0x0534>; + ti,set-rate-parent; + }; + + mmc_clk: clock-mmc { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + clock@52c { + compatible = "ti,clksel"; + reg = <0x52c>; + #clock-cells = <2>; + #address-cells = <0>; + + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + }; + + gfx_fck_div_ck: clock-gfx-fck-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; + clocks = <&gfx_fclk_clksel_ck>; + ti,max-div = <2>; + }; + }; + + clock@700 { + compatible = "ti,clksel"; + reg = <0x700>; + #clock-cells = <2>; + #address-cells = <0>; + + sysclkout_pre_ck: clock-sysclkout-pre { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sysclkout_pre_ck"; + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; + }; + + clkout2_div_ck: clock-clkout2-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout2_div_ck"; + clocks = <&sysclkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + }; + + clkout2_ck: clock-clkout2 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkout2_ck"; + clocks = <&clkout2_div_ck>; + ti,bit-shift = <7>; + }; + }; +}; + +&prcm { + per_cm: clock@0 { + compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; + reg = <0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x400>; + + l4ls_clkctrl: clock@38 { + compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; + reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; + #clock-cells = <2>; + }; + + l3s_clkctrl: clock@1c { + compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; + reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; + #clock-cells = <2>; + }; + + l3_clkctrl: clock@24 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; + reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; + #clock-cells = <2>; + }; + + l4hs_clkctrl: clock@120 { + compatible = "ti,clkctrl"; + clock-output-names = "l4hs_clkctrl"; + reg = <0x120 0x4>; + #clock-cells = <2>; + }; + + pruss_ocp_clkctrl: clock@e8 { + compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; + reg = <0xe8 0x4>; + #clock-cells = <2>; + }; + + cpsw_125mhz_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; + reg = <0x0 0x18>; + #clock-cells = <2>; + }; + + lcdc_clkctrl: clock@18 { + compatible = "ti,clkctrl"; + clock-output-names = "lcdc_clkctrl"; + reg = <0x18 0x4>; + #clock-cells = <2>; + }; + + clk_24mhz_clkctrl: clock@14c { + compatible = "ti,clkctrl"; + clock-output-names = "clk_24mhz_clkctrl"; + reg = <0x14c 0x4>; + #clock-cells = <2>; + }; + }; + + wkup_cm: clock@400 { + compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + l4_wkup_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; + reg = <0x0 0x10>, <0xb4 0x24>; + #clock-cells = <2>; + }; + + l3_aon_clkctrl: clock@14 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_aon_clkctrl"; + reg = <0x14 0x4>; + #clock-cells = <2>; + }; + + l4_wkup_aon_clkctrl: clock@b0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; + reg = <0xb0 0x4>; + #clock-cells = <2>; + }; + }; + + mpu_cm: clock@600 { + compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + mpu_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; + reg = <0x0 0x8>; + #clock-cells = <2>; + }; + }; + + l4_rtc_cm: clock@800 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l4_rtc_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; + reg = <0x0 0x4>; + #clock-cells = <2>; + }; + }; + + gfx_l3_cm: clock@900 { + compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + gfx_l3_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; + reg = <0x0 0x8>; + #clock-cells = <2>; + }; + }; + + l4_cefuse_cm: clock@a00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_cefuse_cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + l4_cefuse_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_cefuse_clkctrl"; + reg = <0x0 0x24>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi new file mode 100644 index 000000000000..7e50fe633d8a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -0,0 +1,2322 @@ +&l4_wkup { /* 0x44c00000 */ + compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkup>; + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x44c00000 0x800>, + <0x44c00800 0x800>, + <0x44c01000 0x400>, + <0x44c01400 0x400>; + reg-names = "ap", "la", "ia0", "ia1"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ + <0x00100000 0x44d00000 0x100000>, /* segment 1 */ + <0x00200000 0x44e00000 0x100000>; /* segment 2 */ + + segment@0 { /* 0x44c00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>; /* ap 3 */ + }; + + segment@100000 { /* 0x44d00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ + <0x00004000 0x00104000 0x001000>, /* ap 5 */ + <0x00080000 0x00180000 0x002000>, /* ap 6 */ + <0x00082000 0x00182000 0x001000>; /* ap 7 */ + + target-module@0 { /* 0x44d00000, ap 4 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>; + reg-names = "rev"; + clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x4000>, + <0x00080000 0x00080000 0x2000>; + + wkup_m3: cpu@0 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x00000000 0x4000>, + <0x00080000 0x2000>; + reg-names = "umem", "dmem"; + resets = <&prm_wkup 3>; + reset-names = "rstctrl"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + }; + }; + + segment@200000 { /* 0x44e00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ + <0x00002000 0x00202000 0x001000>, /* ap 9 */ + <0x00003000 0x00203000 0x001000>, /* ap 10 */ + <0x00004000 0x00204000 0x001000>, /* ap 11 */ + <0x00005000 0x00205000 0x001000>, /* ap 12 */ + <0x00006000 0x00206000 0x001000>, /* ap 13 */ + <0x00007000 0x00207000 0x001000>, /* ap 14 */ + <0x00008000 0x00208000 0x001000>, /* ap 15 */ + <0x00009000 0x00209000 0x001000>, /* ap 16 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ + <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ + <0x00010000 0x00210000 0x010000>, /* ap 22 */ + <0x00020000 0x00220000 0x010000>, /* ap 23 */ + <0x00030000 0x00230000 0x001000>, /* ap 24 */ + <0x00031000 0x00231000 0x001000>, /* ap 25 */ + <0x00032000 0x00232000 0x001000>, /* ap 26 */ + <0x00033000 0x00233000 0x001000>, /* ap 27 */ + <0x00034000 0x00234000 0x001000>, /* ap 28 */ + <0x00035000 0x00235000 0x001000>, /* ap 29 */ + <0x00036000 0x00236000 0x001000>, /* ap 30 */ + <0x00037000 0x00237000 0x001000>, /* ap 31 */ + <0x00038000 0x00238000 0x001000>, /* ap 32 */ + <0x00039000 0x00239000 0x001000>, /* ap 33 */ + <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ + <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ + <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ + <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ + <0x00040000 0x00240000 0x040000>, /* ap 38 */ + <0x00080000 0x00280000 0x001000>; /* ap 39 */ + + target-module@0 { /* 0x44e00000, ap 8 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2000>; + + prcm: prcm@0 { + compatible = "ti,am3-prcm", "simple-bus"; + reg = <0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + }; + + target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + + target-module@5000 { /* 0x44e05000, ap 12 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x7000 0x4>, + <0x7010 0x4>, + <0x7114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + + gpio0: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 82 8>, + <&am33xx_pinmux 8 52 4>, + <&am33xx_pinmux 12 94 4>, + <&am33xx_pinmux 16 71 2>, + <&am33xx_pinmux 18 135 1>, + <&am33xx_pinmux 19 108 2>, + <&am33xx_pinmux 21 73 1>, + <&am33xx_pinmux 22 8 2>, + <&am33xx_pinmux 26 10 2>, + <&am33xx_pinmux 28 74 1>, + <&am33xx_pinmux 29 81 1>, + <&am33xx_pinmux 30 28 2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <96>; + }; + }; + + target-module@9000 { /* 0x44e09000, ap 16 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9050 0x4>, + <0x9054 0x4>, + <0x9058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9000 0x1000>; + + uart0: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x1000>; + interrupts = <72>; + status = "disabled"; + dmas = <&edma 26 0>, <&edma 27 0>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xb000 0x8>, + <0xb010 0x8>, + <0xb090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000 0x1000>; + + i2c0: i2c@0 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1000>; + interrupts = <70>; + status = "disabled"; + }; + }; + + target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd000 0x4>, + <0xd010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x0000d000 0x00001000>, + <0x00001000 0x0000e000 0x00001000>; + + tscadc: tscadc@0 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x1000>; + interrupts = <16>; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + am335x_adc: adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + }; + + target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x10000 0x4>; + reg-names = "rev"; + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x00010000>, + <0x00010000 0x00020000 0x00010000>; + + scm: scm@0 { + compatible = "ti,am3-scm", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + ranges = <0 0 0x2000>; + + am33xx_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x238>; + #pinctrl-cells = <2>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800>; + + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am3352-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + usb_ctrl_mod: control@620 { + compatible = "ti,am335x-usb-ctrl-module"; + reg = <0x620 0x10>, + <0x648 0x4>; + reg-names = "phy_ctrl", "wakeup"; + }; + + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am3352-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <32>; + dma-masters = <&edma>; + }; + + scm_clockdomains: clockdomains { + }; + }; + }; + + timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x31000 0x4>, + <0x31010 0x4>, + <0x31014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x31000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; + }; + + target-module@33000 { /* 0x44e33000, ap 27 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x33000 0x1000>; + }; + + target-module@35000 { /* 0x44e35000, ap 29 50.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x35000 0x4>, + <0x35010 0x4>, + <0x35014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x35000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap3-wdt"; + reg = <0x0 0x1000>; + interrupts = <91>; + }; + }; + + target-module@37000 { /* 0x44e37000, ap 31 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x37000 0x1000>; + }; + + target-module@39000 { /* 0x44e39000, ap 33 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x39000 0x1000>; + }; + + target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x3e074 0x4>, + <0x3e078 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ + power-domains = <&prm_rtc>; + clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + rtc: rtc@0 { + compatible = "ti,am3352-rtc", "ti,da830-rtc"; + reg = <0x0 0x1000>; + interrupts = <75 + 76>; + }; + }; + + target-module@40000 { /* 0x44e40000, ap 38 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x40000>; + }; + }; +}; + +&l4_fw { /* 0x47c00000 */ + compatible = "ti,am33xx-l4-fw", "simple-bus"; + reg = <0x47c00000 0x800>, + <0x47c00800 0x800>, + <0x47c01000 0x400>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ + + segment@0 { /* 0x47c00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ + <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ + <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ + <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ + <0x00010000 0x00010000 0x001000>, /* ap 7 */ + <0x00011000 0x00011000 0x001000>, /* ap 8 */ + <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ + <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ + <0x00024000 0x00024000 0x001000>, /* ap 11 */ + <0x00025000 0x00025000 0x001000>, /* ap 12 */ + <0x00026000 0x00026000 0x001000>, /* ap 13 */ + <0x00027000 0x00027000 0x001000>, /* ap 14 */ + <0x00030000 0x00030000 0x001000>, /* ap 15 */ + <0x00031000 0x00031000 0x001000>, /* ap 16 */ + <0x00038000 0x00038000 0x001000>, /* ap 17 */ + <0x00039000 0x00039000 0x001000>, /* ap 18 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ + <0x00040000 0x00040000 0x001000>, /* ap 24 */ + <0x00046000 0x00046000 0x001000>, /* ap 25 */ + <0x00047000 0x00047000 0x001000>, /* ap 26 */ + <0x00044000 0x00044000 0x001000>, /* ap 27 */ + <0x00045000 0x00045000 0x001000>, /* ap 28 */ + <0x00028000 0x00028000 0x001000>, /* ap 29 */ + <0x00029000 0x00029000 0x001000>, /* ap 30 */ + <0x00032000 0x00032000 0x001000>, /* ap 31 */ + <0x00033000 0x00033000 0x001000>, /* ap 32 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ + <0x00041000 0x00041000 0x001000>, /* ap 34 */ + <0x00042000 0x00042000 0x001000>, /* ap 35 */ + <0x00043000 0x00043000 0x001000>, /* ap 36 */ + <0x00014000 0x00014000 0x001000>, /* ap 37 */ + <0x00015000 0x00015000 0x001000>; /* ap 38 */ + + target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + }; + + target-module@10000 { /* 0x47c10000, ap 7 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + target-module@24000 { /* 0x47c24000, ap 11 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x47c26000, ap 13 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x47c28000, ap 29 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@30000 { /* 0x47c30000, ap 15 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + }; + + target-module@32000 { /* 0x47c32000, ap 31 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + }; + + target-module@38000 { /* 0x47c38000, ap 17 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>; + }; + + target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>; + }; + + target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>; + }; + + target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x47c40000, ap 24 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + }; + + target-module@42000 { /* 0x47c42000, ap 35 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + }; + + target-module@44000 { /* 0x47c44000, ap 27 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + }; + + target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + }; +}; + +&l4_fast { /* 0x4a000000 */ + compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x400>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00100000 0x00100000 0x008000>, /* ap 3 */ + <0x00108000 0x00108000 0x001000>, /* ap 4 */ + <0x00180000 0x00180000 0x020000>, /* ap 5 */ + <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ + <0x00200000 0x00200000 0x080000>, /* ap 7 */ + <0x00280000 0x00280000 0x001000>, /* ap 8 */ + <0x00300000 0x00300000 0x080000>, /* ap 9 */ + <0x00380000 0x00380000 0x001000>; /* ap 10 */ + + target-module@100000 { /* 0x4a100000, ap 3 08.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x101200 0x4>, + <0x101208 0x4>, + <0x101204 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x8000>; + + mac: ethernet@0 { + compatible = "ti,am335x-cpsw","ti,cpsw"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x0 0x800 + 0x1200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges = <0 0 0x8000>; + syscon = <&scm_conf>; + status = "disabled"; + + davinci_mdio: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + status = "disabled"; + }; + + cpsw_emac0: slave@200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 1>; + }; + + cpsw_emac1: slave@300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 1>; + }; + }; + + mac_sw: switch@0 { + compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + status = "disabled"; + + interrupts = <40 41 42 43>; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 1>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "port2"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 1>; + }; + }; + + davinci_mdio_sw: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + }; + + cpts { + clocks = <&cpsw_cpts_rft_clk>; + clock-names = "cpts"; + }; + }; + }; + + target-module@180000 { /* 0x4a180000, ap 5 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x180000 0x20000>; + }; + + target-module@200000 { /* 0x4a200000, ap 7 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200000 0x80000>; + }; + + pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x326000 0x4>, + <0x326004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_per 1>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x300000 0x80000>; + status = "disabled"; + + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&l3_gclk>, /* icss_iep_gclk */ + <&pruss_ocp_gclk>; /* icss_ocp_gclk */ + }; + }; + }; + + pruss_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + interrupt-controller; + #interrupt-cells = <3>; + }; + + pru0: pru@34000 { + compatible = "ti,am3356-pru"; + reg = <0x34000 0x2000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@38000 { + compatible = "ti,am3356-pru"; + reg = <0x38000 0x2000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + + pruss_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + }; + }; +}; + +&l4_mpuss { /* 0x4b140000 */ + compatible = "ti,am33xx-l4-mpuss", "simple-bus"; + reg = <0x4b144400 0x100>, + <0x4b144800 0x400>; + reg-names = "la", "ap"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ + + segment@0 { /* 0x4b140000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00002000 0x00002000 0x001000>, /* ap 2 */ + <0x00004000 0x00004000 0x000400>, /* ap 3 */ + <0x00005000 0x00005000 0x000400>, /* ap 4 */ + <0x00000000 0x00000000 0x001000>, /* ap 5 */ + <0x00003000 0x00003000 0x001000>, /* ap 6 */ + <0x00000800 0x00000800 0x000800>; /* ap 7 */ + + target-module@0 { /* 0x4b140000, ap 5 02.2 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00001000>, + <0x00001000 0x00001000 0x00001000>, + <0x00002000 0x00002000 0x00001000>; + }; + + target-module@3000 { /* 0x4b143000, ap 6 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,am33xx-l4-per", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ + <0x00100000 0x48100000 0x100000>, /* segment 1 */ + <0x00200000 0x48200000 0x100000>, /* segment 2 */ + <0x00300000 0x48300000 0x100000>, /* segment 3 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>, /* ap 3 */ + <0x00001800 0x00001800 0x000400>, /* ap 4 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ + <0x00008000 0x00008000 0x001000>, /* ap 6 */ + <0x00009000 0x00009000 0x001000>, /* ap 7 */ + <0x00016000 0x00016000 0x001000>, /* ap 8 */ + <0x00017000 0x00017000 0x001000>, /* ap 9 */ + <0x00022000 0x00022000 0x001000>, /* ap 10 */ + <0x00023000 0x00023000 0x001000>, /* ap 11 */ + <0x00024000 0x00024000 0x001000>, /* ap 12 */ + <0x00025000 0x00025000 0x001000>, /* ap 13 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ + <0x00038000 0x00038000 0x002000>, /* ap 16 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ + <0x00014000 0x00014000 0x001000>, /* ap 18 */ + <0x00015000 0x00015000 0x001000>, /* ap 19 */ + <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ + <0x00040000 0x00040000 0x001000>, /* ap 22 */ + <0x00041000 0x00041000 0x001000>, /* ap 23 */ + <0x00042000 0x00042000 0x001000>, /* ap 24 */ + <0x00043000 0x00043000 0x001000>, /* ap 25 */ + <0x00044000 0x00044000 0x001000>, /* ap 26 */ + <0x00045000 0x00045000 0x001000>, /* ap 27 */ + <0x00046000 0x00046000 0x001000>, /* ap 28 */ + <0x00047000 0x00047000 0x001000>, /* ap 29 */ + <0x00048000 0x00048000 0x001000>, /* ap 30 */ + <0x00049000 0x00049000 0x001000>, /* ap 31 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ + <0x00050000 0x00050000 0x002000>, /* ap 34 */ + <0x00052000 0x00052000 0x001000>, /* ap 35 */ + <0x00060000 0x00060000 0x001000>, /* ap 36 */ + <0x00061000 0x00061000 0x001000>, /* ap 37 */ + <0x00080000 0x00080000 0x010000>, /* ap 38 */ + <0x00090000 0x00090000 0x001000>, /* ap 39 */ + <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ + <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ + <0x00030000 0x00030000 0x001000>, /* ap 77 */ + <0x00031000 0x00031000 0x001000>, /* ap 78 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ + <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ + <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ + <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ + <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ + <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ + <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ + + target-module@8000 { /* 0x48008000, ap 6 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@14000 { /* 0x48014000, ap 18 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x48016000, ap 8 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@22000 { /* 0x48022000, ap 10 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x22050 0x4>, + <0x22054 0x4>, + <0x22058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + + uart1: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x1000>; + interrupts = <73>; + status = "disabled"; + dmas = <&edma 28 0>, <&edma 29 0>; + dma-names = "tx", "rx"; + }; + }; + + target-module@24000 { /* 0x48024000, ap 12 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x24050 0x4>, + <0x24054 0x4>, + <0x24058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + uart2: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x1000>; + interrupts = <74>; + status = "disabled"; + dmas = <&edma 30 0>, <&edma 31 0>; + dma-names = "tx", "rx"; + }; + }; + + target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2a000 0x8>, + <0x2a010 0x8>, + <0x2a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1000>; + interrupts = <71>; + status = "disabled"; + }; + }; + + target-module@30000 { /* 0x48030000, ap 77 08.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x30000 0x4>, + <0x30110 0x4>, + <0x30114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + + spi0: spi@0 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x400>; + interrupts = <65>; + ti,spi-num-cs = <2>; + dmas = <&edma 16 0 + &edma 17 0 + &edma 18 0 + &edma 19 0>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; + }; + + target-module@38000 { /* 0x48038000, ap 16 02.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x38000 0x4>, + <0x38004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x2000>, + <0x46000000 0x46000000 0x400000>; + + mcasp0: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; + }; + }; + + target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x3c000 0x4>, + <0x3c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x2000>, + <0x46400000 0x46400000 0x400000>; + + mcasp1: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <82>, <83>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10 2>, + <&edma 11 2>; + dma-names = "tx", "rx"; + }; + }; + + timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>, + <0x40014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <68>; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; + }; + + target-module@42000 { /* 0x48042000, ap 24 1c.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x42000 0x4>, + <0x42010 0x4>, + <0x42014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + + timer3: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <69>; + }; + }; + + target-module@44000 { /* 0x48044000, ap 26 26.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x44000 0x4>, + <0x44010 0x4>, + <0x44014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + + timer4: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <92>; + ti,timer-pwm; + }; + }; + + target-module@46000 { /* 0x48046000, ap 28 28.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x46000 0x4>, + <0x46010 0x4>, + <0x46014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + + timer5: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <93>; + ti,timer-pwm; + }; + }; + + target-module@48000 { /* 0x48048000, ap 30 22.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x48000 0x4>, + <0x48010 0x4>, + <0x48014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + + timer6: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <94>; + ti,timer-pwm; + }; + }; + + target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x4a000 0x4>, + <0x4a010 0x4>, + <0x4a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + + timer7: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <95>; + ti,timer-pwm; + }; + }; + + target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>, + <0x4c114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 0 8>, + <&am33xx_pinmux 8 90 4>, + <&am33xx_pinmux 12 12 16>, + <&am33xx_pinmux 28 30 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <98>; + }; + }; + + target-module@50000 { /* 0x48050000, ap 34 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000 0x2000>; + }; + + target-module@60000 { /* 0x48060000, ap 36 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x602fc 0x4>, + <0x60110 0x4>, + <0x60114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,am335-sdhci"; + ti,needs-special-reset; + dmas = <&edma 24 0>, <&edma 25 0>; + dma-names = "tx", "rx"; + interrupts = <64>; + reg = <0x0 0x1000>; + status = "disabled"; + }; + }; + + target-module@80000 { /* 0x48080000, ap 38 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x80000 0x4>, + <0x80010 0x4>, + <0x80014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x10000>; + }; + + target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc8000 0x4>, + <0xc8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = <77>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + mbox_wkupm3: mbox-wkup-m3 { + ti,mbox-send-noirq; + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; + }; + }; + + target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xca000 0x4>, + <0xca010 0x4>, + <0xca014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xca000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + + target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xcc000 0x1000>; + }; + }; + + segment@100000 { /* 0x48100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ + <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ + <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ + <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ + <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ + <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ + <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ + <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ + <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ + <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ + <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ + <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ + <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ + <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ + <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ + <0x000af000 0x001af000 0x001000>, /* ap 57 */ + <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ + <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ + <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ + <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ + <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ + <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ + <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ + <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ + <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ + <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ + <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ + <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ + <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ + <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ + + target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8c000 0x1000>; + }; + + target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8e000 0x1000>; + }; + + target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9c000 0x8>, + <0x9c010 0x8>, + <0x9c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1000>; + interrupts = <30>; + status = "disabled"; + }; + }; + + target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa0000 0x4>, + <0xa0110 0x4>, + <0xa0114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x1000>; + + spi1: spi@0 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x400>; + interrupts = <125>; + ti,spi-num-cs = <2>; + dmas = <&edma 42 0 + &edma 43 0 + &edma 44 0 + &edma 45 0>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; + }; + + target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa4000 0x1000>; + }; + + target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa6050 0x4>, + <0xa6054 0x4>, + <0xa6058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa6000 0x1000>; + + uart3: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x1000>; + interrupts = <44>; + status = "disabled"; + }; + }; + + target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa8050 0x4>, + <0xa8054 0x4>, + <0xa8058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x1000>; + + uart4: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x1000>; + interrupts = <45>; + status = "disabled"; + }; + }; + + target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xaa050 0x4>, + <0xaa054 0x4>, + <0xaa058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xaa000 0x1000>; + + uart5: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x1000>; + interrupts = <46>; + status = "disabled"; + }; + }; + + target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xac000 0x4>, + <0xac010 0x4>, + <0xac114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xac000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 34 18>, + <&am33xx_pinmux 18 77 4>, + <&am33xx_pinmux 22 56 10>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <32>; + }; + }; + + gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xae000 0x4>, + <0xae010 0x4>, + <0xae114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xae000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 66 5>, + <&am33xx_pinmux 5 98 2>, + <&am33xx_pinmux 7 75 2>, + <&am33xx_pinmux 13 141 1>, + <&am33xx_pinmux 14 100 8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <62>; + }; + }; + + target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb0000 0x10000>; + }; + + target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xcc020 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, + <&dcan0_fck>; + clock-names = "fck", "osc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xcc000 0x2000>; + + dcan0: can@0 { + compatible = "ti,am3352-d_can"; + reg = <0x0 0x2000>; + clocks = <&dcan0_fck>; + clock-names = "fck"; + syscon-raminit = <&scm_conf 0x644 0>; + interrupts = <52>; + status = "disabled"; + }; + }; + + target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd0020 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, + <&dcan1_fck>; + clock-names = "fck", "osc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000 0x2000>; + + dcan1: can@0 { + compatible = "ti,am3352-d_can"; + reg = <0x0 0x2000>; + clocks = <&dcan1_fck>; + clock-names = "fck"; + syscon-raminit = <&scm_conf 0x644 1>; + interrupts = <55>; + status = "disabled"; + }; + }; + + target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xd82fc 0x4>, + <0xd8110 0x4>, + <0xd8114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd8000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,am335-sdhci"; + ti,needs-special-reset; + dmas = <&edma 2 0 + &edma 3 0>; + dma-names = "tx", "rx"; + interrupts = <28>; + reg = <0x0 0x1000>; + status = "disabled"; + }; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x010000>; + + target-module@0 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10000>; + + mpu@0 { + compatible = "ti,omap3-mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; + }; + }; + }; + + segment@300000 { /* 0x48300000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ + <0x00001000 0x00301000 0x001000>, /* ap 67 */ + <0x00002000 0x00302000 0x001000>, /* ap 68 */ + <0x00003000 0x00303000 0x001000>, /* ap 69 */ + <0x00004000 0x00304000 0x001000>, /* ap 70 */ + <0x00005000 0x00305000 0x001000>, /* ap 71 */ + <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ + <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ + <0x00018000 0x00318000 0x004000>, /* ap 74 */ + <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ + <0x00010000 0x00310000 0x002000>, /* ap 76 */ + <0x00012000 0x00312000 0x001000>, /* ap 93 */ + <0x00015000 0x00315000 0x001000>, /* ap 94 */ + <0x00016000 0x00316000 0x001000>, /* ap 95 */ + <0x00017000 0x00317000 0x001000>, /* ap 96 */ + <0x00013000 0x00313000 0x001000>, /* ap 97 */ + <0x00014000 0x00314000 0x001000>, /* ap 98 */ + <0x00020000 0x00320000 0x001000>, /* ap 99 */ + <0x00021000 0x00321000 0x001000>, /* ap 100 */ + <0x00022000 0x00322000 0x001000>, /* ap 101 */ + <0x00023000 0x00323000 0x001000>, /* ap 102 */ + <0x00024000 0x00324000 0x001000>, /* ap 103 */ + <0x00025000 0x00325000 0x001000>; /* ap 104 */ + + target-module@0 { /* 0x48300000, ap 66 48.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>, + <0x4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + epwmss0: epwmss@0 { + compatible = "ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap0: pwm@100 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + eqep0: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <79>; + status = "disabled"; + }; + + ehrpwm0: pwm@200 { + compatible = "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@2000 { /* 0x48302000, ap 68 52.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + epwmss1: epwmss@0 { + compatible = "ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap1: pwm@100 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + eqep1: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <88>; + status = "disabled"; + }; + + ehrpwm1: pwm@200 { + compatible = "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@4000 { /* 0x48304000, ap 70 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + epwmss2: epwmss@0 { + compatible = "ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap2: pwm@100 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + eqep2: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <89>; + status = "disabled"; + }; + + ehrpwm2: pwm@200 { + compatible = "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xe000 0x4>, + <0xe054 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, lcdc_clkdm */ + clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + + lcdc: lcdc@0 { + compatible = "ti,am33xx-tilcdc"; + reg = <0x0 0x1000>; + interrupts = <36>; + status = "disabled"; + }; + }; + + target-module@10000 { /* 0x48310000, ap 76 4e.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x11fe0 0x4>, + <0x11fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = <111>; + }; + }; + + target-module@13000 { /* 0x48313000, ap 97 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x13000 0x1000>; + }; + + target-module@15000 { /* 0x48315000, ap 94 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00015000 0x00001000>, + <0x00001000 0x00016000 0x00001000>; + }; + + target-module@18000 { /* 0x48318000, ap 74 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x4000>; + }; + + target-module@20000 { /* 0x48320000, ap 99 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x48322000, ap 101 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x48324000, ap 103 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi new file mode 100644 index 000000000000..32d397b3950b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -0,0 +1,714 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +/ { + compatible = "ti,am33xx"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + d-can0 = &dcan0; + d-can1 = &dcan1; + usb0 = &usb0; + usb1 = &usb1; + phy0 = &usb0_phy; + phy1 = &usb1_phy; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + spi0 = &spi0; + spi1 = &spi1; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + enable-method = "ti,am3352"; + device_type = "cpu"; + reg = <0>; + + operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + cpu-idle-states = <&mpu_gate>; + }; + + idle-states { + mpu_gate: mpu_gate { + compatible = "arm,idle-state"; + entry-latency-us = <40>; + exit-latency-us = <90>; + min-residency-us = <300>; + ti,idle-wkup-m3; + }; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100-275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + + target-module@4b000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b000000 0x1000000>; + + target-module@140000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x140000 0xec0000>; + + pmu@0 { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + }; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + }; + + /* + * XXX: Use a flat representation of the AM33XX interconnect. + * The real AM33XX interconnect network is quite complex. Since + * it will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp: ocp { + compatible = "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + l4_wkup: interconnect@44c00000 { + }; + l4_per: interconnect@48000000 { + }; + l4_fw: interconnect@47c00000 { + }; + l4_fast: interconnect@4a000000 { + }; + l4_mpuss: interconnect@4b140000 { + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,am33xx-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + }; + + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@47810000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x478102fc 0x4>, + <0x47810110 0x4>, + <0x47810114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47810000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,am335-sdhci"; + ti,needs-special-reset; + interrupts = <29>; + reg = <0x0 0x1000>; + status = "disabled"; + }; + }; + + usb: target-module@47400000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x47400000 0x4>, + <0x47400010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47400000 0x8000>; + + usb0_phy: usb-phy@1300 { + compatible = "ti,am335x-usb-phy"; + reg = <0x1300 0x100>; + reg-names = "phy"; + ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; + }; + + usb0: usb@1400 { + compatible = "ti,musb-am33xx"; + reg = <0x1400 0x400>, + <0x1000 0x200>; + reg-names = "mc", "control"; + + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb0_phy>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1_phy: usb-phy@1b00 { + compatible = "ti,am335x-usb-phy"; + reg = <0x1b00 0x100>; + reg-names = "phy"; + ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; + }; + + usb1: usb@1800 { + compatible = "ti,musb-am33xx"; + reg = <0x1c00 0x400>, + <0x1800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb1_phy>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@2000 { + compatible = "ti,am3359-cppi41"; + reg = <0x0000 0x1000>, + <0x2000 0x1000>, + <0x3000 0x1000>, + <0x4000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <30>; + dma-channels = <30>; + #dma-requests = <256>; + dma-requests = <256>; + }; + }; + + target-module@40300000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40300000 0x10000>; + + ocmcram: sram@0 { + compatible = "mmio-sram"; + reg = <0 0x10000>; /* 64k */ + ranges = <0 0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + pm_sram_code: pm-code-sram@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-data-sram@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; + }; + }; + + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif: emif@0 { + compatible = "ti,emif-am3352"; + reg = <0 0x1000000>; + interrupts = <101>; + sram = <&pm_sram_code + &pm_sram_data>; + }; + }; + + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + sham_target: target-module@53100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x53100100 0x4>, + <0x53100110 0x4>, + <0x53100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x200>; + interrupts = <109>; + dmas = <&edma 36 0>; + dma-names = "rx"; + }; + }; + + aes_target: target-module@53500000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x53500080 0x4>, + <0x53500084 0x4>, + <0x53500088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53500000 0x1000>; + + aes: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <103>; + dmas = <&edma 6 0>, + <&edma 5 0>; + dma-names = "tx", "rx"; + }; + }; + + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; + clock-names = "fck"; + power-domains = <&prm_gfx>; + resets = <&prm_gfx 0>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x1000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + }; +}; + +#include "am33xx-l4.dtsi" +#include "am33xx-clocks.dtsi" + +&prcm { + prm_per: prm@c00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xc00 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_wkup: prm@d00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xd00 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_mpu: prm@e00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xe00 0x100>; + #power-domain-cells = <0>; + }; + + prm_device: prm@f00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + }; + + prm_rtc: prm@1000 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0x1000 0x100>; + #power-domain-cells = <0>; + }; + + prm_gfx: prm@1100 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x100>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + prm_cefuse: prm@1200 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #power-domain-cells = <0>; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer1_target { + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck", "ick"; + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck", "ick"; + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts b/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts new file mode 100644 index 000000000000..d035c888731f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * See craneboard.org for more details + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am3517.dtsi" + +/ { + model = "TI AM3517 CraneBoard (TMDSEVM3517)"; + compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&davinci_emac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <2600000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + /* goes to expansion connector */ + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + /* goes to expansion connector */ + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <&vdd2_reg>; + bus-width = <8>; +}; + +&mmc2 { + /* goes to expansion connector */ + status = "disabled"; +}; + +&mmc3 { + /* goes to expansion connector */ + status = "disabled"; +}; + +#include "../../tps65910.dtsi" + +&omap3_pmx_core { + tps_pins: tps-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ + >; + }; +}; + +&tps { + pinctrl-names = "default"; + pinctrl-0 = <&tps_pins>; + + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + ti,en-ck32k-xtal; + + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + /* + * Unused: + * VDIG1=2.7V,300mA max + * VDIG2=1.8V,300mA max + */ + + vpll_reg: regulator@7 { + /* VDDS_DPLL_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + /* VDDS_SRAM_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + /* VDDA1P8V_USBPHY */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* VAUX33 unused */ + + vdac_reg: regulator@8 { + /* VDDA_DAC_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + /* VDDA3P3V_USBPHY */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_CORE */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDDSHV_3V3 */ + regulator-name = "vdd_shv"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* VDD3 unused */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi b/arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi new file mode 100644 index 000000000000..16b8968d5be8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/ + */ + +#include + +/ { + codec1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "tlv320aic23-hifi"; + + simple-audio-card,widgets = + "Microphone", "Mic In", + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "Line Out", "LOUT", + "Line Out", "ROUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic In"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcbsp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic23_1>; + system-clock-frequency = <12000000>; + }; + }; + + codec2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "tlv320aic23-hifi"; + + simple-audio-card,widgets = + "Microphone", "Mic In", + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "Line Out", "LOUT", + "Line Out", "ROUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic In"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master2>; + simple-audio-card,frame-master = <&sound_master2>; + + simple-audio-card,cpu { + sound-dai = <&mcbsp2>; + }; + + sound_master2: simple-audio-card,codec { + sound-dai = <&tlv320aic23_2>; + system-clock-frequency = <12000000>; + }; + }; + + expander-keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + key-record { + label = "Record"; + /* linux,code = ; */ + gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; + }; + + key-play { + label = "Play"; + linux,code = ; + gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; + }; + + key-stop { + label = "Stop"; + linux,code = ; + gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; + }; + + key-fwd { + label = "FWD"; + linux,code = ; + gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; + }; + + key-rwd { + label = "RWD"; + linux,code = ; + gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; + }; + + key-shift { + label = "Shift"; + linux,code = ; + gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; + }; + + key-mode { + label = "Mode"; + linux,code = ; + gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; + }; + + key-menu { + label = "Menu"; + linux,code = ; + gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; + }; + + key-up { + label = "Up"; + linux,code = ; + gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; + }; + + key-down { + label = "Down"; + linux,code = ; + gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c2 { + /* Audio codecs */ + tlv320aic23_1: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + #sound-dai-cells = <0>; + status = "okay"; + }; + + tlv320aic23_2: codec@1b { + compatible = "ti,tlv320aic23"; + reg = <0x1b>; + #sound-dai-cells = <0>; + status = "okay"; + }; +}; + +&i2c3 { + /* Audio codecs */ + tlv320aic23_3: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + #sound-dai-cells = <0>; + status = "okay"; + }; + + /* GPIO Expanders */ + tca6416_2: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; + }; + + tca6416_3: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; + }; + + /* TVP5146 Analog Video decoder input */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&mcbsp1 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; +}; + +&mcbsp2 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; + +&omap3_pmx_core { + mcbsp1_pins: mcbsp1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ + OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ + OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ + OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts new file mode 100644 index 000000000000..af9df15274be --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am3517.dtsi" +#include "am3517-som.dtsi" +#include "am3517-evm-ui.dtsi" +#include + +/ { + model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; + compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vmmc_fixed: vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-user { + label = "User Push Button"; + linux,code = ; + gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; + }; + + switch-1 { + label = "User Switch 1"; + linux,code = ; + gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; + }; + + switch-2 { + label = "User Switch 2"; + linux,code = ; + gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; + }; + + switch-3 { + label = "User Switch 3"; + linux,code = ; + gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; + }; + + switch-4 { + label = "User Switch 4"; + linux,code = ; + gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; + }; + + switch-5 { + label = "User Switch 5"; + linux,code = ; + gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; + }; + + switch-6 { + label = "User Switch 6"; + linux,code = ; + gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; + }; + + switch-7 { + label = "User Switch 7"; + linux,code = ; + gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; + }; + + switch-8 { + label = "User Switch 8"; + linux,code = ; + gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + user_led_1 { + label = "am3517evm:green:user_led_1"; + gpios = <&tca6416 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + user_led_2 { + label = "am3517evm:green:user_led_2"; + gpios = <&tca6416 6 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + user_led_3 { + label = "am3517evm:green:user_led_3"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; /* SD/MMC card activity */ + }; + + user_led_4 { + label = "am3517evm:green:user_led_4"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + lcd0: display@0 { + /* This isn't the exact LCD, but the timings meet spec */ + /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ + compatible = "newhaven,nhd-4.3-480272ef-atxl"; + label = "15"; + backlight = <&bl>; + enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ + vcc-supply = <&vdd_io_reg>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + power-supply = <&vdd_io_reg>; + pinctrl-0 = <&backlight_pins>; + pwms = <&pwm11 0 5000000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ + }; + + pwm11: pwm-11 { + compatible = "ti,omap-dmtimer-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + ti,timers = <&timer11>; + #pwm-cells = <3>; + ti,clock-source = <0x01>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ + #phy-cells = <0>; + }; +}; + +&davinci_emac { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + vdds_dsi-supply = <&vdd_io_reg>; + vdda_video-supply = <&vdd_io_reg>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <16>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + /* User DIP swithes [1:8] / User LEDS [1:2] */ + tca6416: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc_fixed>; + bus-width = <4>; + wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ + cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */ +}; + +&mmc3 { + status = "disabled"; +}; + +&usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + +&omap3_pmx_core { + + ethernet_pins: ethernet-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ + OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ + OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */ + OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */ + OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */ + OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */ + OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */ + OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */ + OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */ + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + leds_pins: leds-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ + OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */ + >; + }; + + pwm_pins: pwm-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + >; + }; + + hsusb1_rst_pins: hsusb1-rst-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; +}; + +&omap3_pmx_core2 { + + hsusb1_pins: hsusb1-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517-som.dtsi b/arch/arm/boot/dts/ti/omap/am3517-som.dtsi new file mode 100644 index 000000000000..bd0a6c95afa1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3517-som.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Derald D. Woods + * + * Based on am3517-evm.dts + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vdd_core_reg>; + }; + }; + + wl12xx_buffer: wl12xx_buf { + compatible = "regulator-fixed"; + regulator-name = "wl1271_buf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_buffer_pins>; + gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ + regulator-always-on; + vin-supply = <&vdd_1v8_reg>; + }; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_wkup_pins>; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + vin-supply = <&wl12xx_buffer>; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + linux,mtd-name = "micron,mt29f4g16abchch"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins>; + interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */ + }; + + tps: tps65023@48 { + compatible = "ti,tps65023"; + reg = <0x48>; + + regulators { + vdd_core_reg: VDCDC1 { + regulator-name = "vdd_core"; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vdd_io_reg: VDCDC2 { + regulator-name = "vdd_io"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_1v8_reg: VDCDC3 { + regulator-name = "vdd_1v8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdd_usb18_reg: LDO1 { + regulator-name = "vdd_usb18"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdd_usb33_reg: LDO2 { + regulator-name = "vdd_usb33"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + touchscreen: tsc2004@4b { + compatible = "ti,tsc2004"; + reg = <0x4b>; + + vio-supply = <&vdd_io_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tsc2004_pins>; + interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */ + + touchscreen-fuzz-x = <4>; + touchscreen-fuzz-y = <7>; + touchscreen-fuzz-pressure = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + touchscreen-max-pressure = <2048>; + + ti,x-plate-ohms = <280>; + ti,esd-recovery-timeout-ms = <8000>; + }; +}; + +&mmc2 { + interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + bluetooth { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ + max-speed = <3000000>; + }; +}; + +&omap3_pmx_core { + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + wl12xx_buffer_pins: wl12xx-buffer-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + rtc_pins: rtc-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ + >; + }; + + tsc2004_pins: tsc2004-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ + >; + }; +}; + +&omap3_pmx_wkup { + + wl12xx_wkup_pins: wl12xx-wkup-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi new file mode 100644 index 000000000000..823f63502e9f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3517.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for am3517 SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "omap3.dtsi" + +/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ +/delete-node/ &aes1_target; +/delete-node/ &aes2_target; + +/ { + aliases { + serial3 = &uart4; + can = &hecc; + }; + + cpus { + cpu: cpu@0 { + /* Based on OMAP3630 variants OPP50 and OPP100 */ + operating-points-v2 = <&cpu0_opp_table>; + + clock-latency = <300000>; /* From legacy driver */ + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + /* + * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx + * appear to operate at 300MHz as well. Since AM3517 only + * lists one operating voltage, it will remain fixed at 1.2V + */ + opp50-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0xffffffff 0xffffffff>; + opp-suspend; + }; + + opp100-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0xffffffff 0xffffffff>; + }; + }; + + ocp@68000000 { + target-module@5c040000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5c040400 0x4>, + <0x5c040404 0x4>, + <0x5c040408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&hsotgusb_ick_am35xx>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5c040000 0x1000>; + + am35x_otg_hs: am35x_otg_hs@0 { + compatible = "ti,omap3-musb"; + status = "disabled"; + reg = <0 0x1000>; + interrupts = <71>; + interrupt-names = "mc"; + }; + }; + + davinci_emac: ethernet@5c000000 { + compatible = "ti,am3517-emac"; + ti,hwmods = "davinci_emac"; + status = "disabled"; + reg = <0x5c000000 0x30000>; + interrupts = <67 68 69 70>; + syscon = <&scm_conf>; + ti,davinci-ctrl-reg-offset = <0x10000>; + ti,davinci-ctrl-mod-reg-offset = <0>; + ti,davinci-ctrl-ram-offset = <0x20000>; + ti,davinci-ctrl-ram-size = <0x2000>; + ti,davinci-rmii-en = /bits/ 8 <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + clocks = <&emac_ick>; + clock-names = "ick"; + }; + + davinci_mdio: mdio@5c030000 { + compatible = "ti,davinci_mdio"; + ti,hwmods = "davinci_mdio"; + status = "disabled"; + reg = <0x5c030000 0x1000>; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&emac_fck>; + clock-names = "fck"; + }; + + uart4: serial@4809e000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + status = "disabled"; + reg = <0x4809e000 0x400>; + interrupts = <84>; + dmas = <&sdma 55 &sdma 54>; + dma-names = "tx", "rx"; + clock-frequency = <48000000>; + }; + + omap3_pmx_core2: pinmux@480025d8 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025d8 0x24>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + hecc: can@5c050000 { + compatible = "ti,am3517-hecc"; + status = "disabled"; + reg = <0x5c050000 0x80>, + <0x5c053000 0x180>, + <0x5c052000 0x200>; + reg-names = "hecc", "hecc-ram", "mbx"; + interrupts = <24>; + clocks = <&hecc_ck>; + }; + + /* + * On am3517 the OCP registers do not seem to be accessible + * similar to the omap34xx. Maybe SGX is permanently set to + * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is + * write-only at 0x50000e10. We detect SGX based on the SGX + * revision register instead of the unreadable OCP revision + * register. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000014 0x4>; + reg-names = "rev"; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + }; +}; + +/* Not currently working, probably needs at least different clocks */ +&rng_target { + status = "disabled"; + /delete-property/ clocks; +}; + +/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ +&usb_otg_target { + status = "disabled"; +}; + +&iva { + status = "disabled"; +}; + +&mailbox { + status = "disabled"; +}; + +&mmu_isp { + status = "disabled"; +}; + +#include "am35xx-clocks.dtsi" +#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts b/arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts new file mode 100644 index 000000000000..e7d7124a34ba --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Ilya Yanok, EmCraft Systems + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "TeeJet Mt.Ventoux"; + compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* AM35xx doesn't have IVA */ + soc { + iva { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi new file mode 100644 index 000000000000..0ee7afaa0e8e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP3 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&scm_clocks { + emac_ick: emac_ick@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x032c>; + ti,bit-shift = <1>; + }; + + emac_fck: emac_fck@32c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&rmii_ck>; + reg = <0x032c>; + ti,bit-shift = <9>; + }; + + vpfe_ick: vpfe_ick@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x032c>; + ti,bit-shift = <2>; + }; + + vpfe_fck: vpfe_fck@32c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pclk_ck>; + reg = <0x032c>; + ti,bit-shift = <10>; + }; + + hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x032c>; + ti,bit-shift = <0>; + }; + + hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x032c>; + ti,bit-shift = <8>; + }; + + hecc_ck: hecc_ck@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&sys_ck>; + reg = <0x032c>; + ti,bit-shift = <3>; + }; +}; +&cm_clocks { + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + ipss_ick: clock-ipss-ick { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clock-output-names = "ipss_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + uart4_ick_am35xx: clock-uart4-ick-am35xx { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick_am35xx"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; + }; + + rmii_ck: rmii_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + pclk_ck: pclk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck_am35xx: clock-uart4-fck-am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck_am35xx"; + clocks = <&core_48m_fck>; + ti,bit-shift = <23>; + }; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, + <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, + <&hecc_ck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, + <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3703.dtsi b/arch/arm/boot/dts/ti/omap/am3703.dtsi new file mode 100644 index 000000000000..2b994ae790c9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3703.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 André Hentschel + */ + +#include "omap36xx.dtsi" + +&iva { + status = "disabled"; +}; + +&sgx_module { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3715.dtsi b/arch/arm/boot/dts/ti/omap/am3715.dtsi new file mode 100644 index 000000000000..ab328e8c0bd8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3715.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 André Hentschel + */ + +#include "omap36xx.dtsi" + +&iva { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts b/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts new file mode 100644 index 000000000000..ac082e83a9a2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Winterland IceBoard + * + * https://mcgillcosmology.com + * https://threespeedlogic.com + * + * This is an ARM + FPGA instrumentation board used at telescopes in + * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO + * observatory in British Columbia (CHIME). + * + * Copyright (c) 2019 Three-Speed Logic, Inc. + */ + +/dts-v1/; + +#include "dm814x.dtsi" +#include + +/ { + model = "Winterland IceBoard"; + compatible = "ti,dm8148", "ti,dm814"; + + chosen { + stdout-path = "serial1:115200n8"; + bootargs = "earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* The MAC provides internal delay for the transmit path ONLY, which is enabled + * provided no -id/-txid/-rxid suffix is provided to "phy-mode". + * + * The receive path is delayed at the PHY. The recommended register settings + * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the + * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, + * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to + * obtain the correct register settings. + */ +&mac { dual_emac = <1>; }; +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; +&cpsw_emac1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + ethphy0: ethernet-phy@0 { + reg = <0x2>; + + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + + rxd3-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd0-skew-ps = <0>; + + phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@1 { + reg = <0x1>; + + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + + rxd3-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd0-skew-ps = <0>; + + phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc1 { status = "disabled"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; +&mmc3 { status = "disabled"; }; + +&i2c1 { + /* Most I2C activity happens through this port, with the sole exception + * of the backplane. Since there are multiply assigned addresses, the + * "i2c-mux-idle-disconnect" is important. + */ + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + /* FMC A */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + /* FMC B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + /* QSFP A */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + /* QSFP B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c@4 { + /* SFP */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; + ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; + ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; + + ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; + ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; + ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; + + ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; + ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; + ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; + ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; + ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; + ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; + ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; + ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; + ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; + }; + + i2c@6 { + /* Backplane */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + u41: pca9575@20 { + compatible = "nxp,pca9575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", + "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", + "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", + "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u42: pca9575@21 { + compatible = "nxp,pca9575"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", + "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", + "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", + "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u48: pca9575@22 { + compatible = "nxp,pca9575"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, + <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; + led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, + <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; + + gpio-line-names = + "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", + "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", + "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", + "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u59: pca9575@23 { + compatible = "nxp,pca9575"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", + "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", + "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", + "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; + tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; + tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; + tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; + + /* EEPROM bank and serial number are treated as separate devices */ + at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; + at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; + }; + }; +}; + +&i2c2 { + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@6 { + /* Backplane */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + multi-master; + + /* All backplanes should have this -- it's how we know they're there. */ + at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; + at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; + + /* 16 slot backplane */ + tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; + tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; + ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; + amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; + + /* Single slot backplane */ + }; + }; +}; + +&pincntl { + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ + DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ + DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ + DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ + DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ + DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ + DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ + DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ + DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ + >; + }; + + usb0_pins: usb0-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: usb1-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ + >; + }; + + gpio1_pins: gpio1-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ + DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ + DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ + + DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ + DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ + DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ + DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ + DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ + + DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ + DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ + DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ + DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ + DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ + + DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ + DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ + DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ + DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ + >; + }; + + gpio2_pins: gpio2-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ + DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ + DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ + DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ + + //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ + //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ + DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ + >; + }; + + gpio4_pins: gpio4-pins { + pinctrl-single,pins = < + /* The PLL doesn't react well to the SPI controller reset, so + * we force the CS lines to pull up as GPIOs until we're ready. + * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 + */ + DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ + DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ + DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ + DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ + DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ + DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ + >; + }; + + spi2_pins: spi2-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ + DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ + >; + }; + + spi4_pins: spi4-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0a7c, 0x20) + DM814X_IOPAD(0x0b74, 0x20) + DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) + DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) + DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) + >; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; + gpio-line-names = + "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ + "", "", "", "FMCA_TRST", /* 12-15 */ + "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ + "FMCB_TRST", "", "", "", /* 20-23 */ + "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ + "", "", "", ""; /* 28-31 */ +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_pins>; + gpio-line-names = + "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ + "", "", "", "PHYB_IRQ_N", /* 4-7 */ + "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ +}; + +&gpio3 { + pinctrl-names = "default"; + /*pinctrl-0 = <&gpio3_pins>;*/ + gpio-line-names = + "", "", "ARMClkSel0", "", /* 0-3 */ + "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio4_pins>; + gpio-line-names = + "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", + "BP_ARM_GPIO4", "BP_ARM_GPIO5"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; +}; + +&mcspi1 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + + fsbl@0 { + /* 256 kB */ + label = "U-Boot-min"; + reg = <0 0x40000>; + }; + ssbl@1 { + /* 512 kB */ + label = "U-Boot"; + reg = <0x40000 0x80000>; + }; + bootenv@2 { + /* 256 kB */ + label = "U-Boot Env"; + reg = <0xc0000 0x40000>; + }; + kernel@3 { + /* 4 MB */ + label = "Kernel"; + reg = <0x100000 0x400000>; + }; + ipmi@4 { + label = "IPMI FRU"; + reg = <0x500000 0x40000>; + }; + fs@5 { + label = "File System"; + reg = <0x540000 0x1ac0000>; + }; + }; +}; + +&mcspi3 { + /* DMA event numbers stolen from MCASP */ + dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 + &edma_xbar 10 0 18 &edma_xbar 11 0 19>; + dma-names = "tx0", "rx0", "tx1", "rx1"; +}; + +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + + /* DMA event numbers stolen from MCASP, MCBSP */ + dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; + dma-names = "tx0", "rx0"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi new file mode 100644 index 000000000000..8613355bbd5e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for AM4372 SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +/ { + compatible = "ti,am4372", "ti,am43"; + interrupt-parent = <&wakeupgen>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + spi0 = &qspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu: cpu@0 { + compatible = "arm,cortex-a9"; + enable-method = "ti,am4372"; + device_type = "cpu"; + reg = <0>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + operating-points-v2 = <&cpu0_opp_table>; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + cpu-idle-states = <&mpu_gate>; + }; + + idle-states { + mpu_gate: mpu_gate { + compatible = "arm,idle-state"; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <300>; + local-timer-stop; + }; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + opp50-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp100-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0xFF 0x04>; + }; + + opp120-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0xFF 0x08>; + }; + + oppturbo-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0xFF 0x10>; + }; + + oppnitro-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0xFF 0x20>; + }; + }; + + soc { + compatible = "ti,omap-infra"; + }; + + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller@48281000 { + compatible = "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; + }; + + scu: scu@48240000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x48240000 0x100>; + }; + + global_timer: timer@48240200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x48240200 0x100>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&mpu_periphclk>; + }; + + local_timer: timer@48240600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x48240600 0x100>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&mpu_periphclk>; + }; + + cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + ocp@44000000 { + compatible = "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,no-idle; + + l3-noc@44000000 { + compatible = "ti,am4372-l3-noc"; + reg = <0x44000000 0x400000>, + <0x44800000 0x400000>; + interrupts = , + ; + }; + + l4_wkup: interconnect@44c00000 { + }; + l4_per: interconnect@48000000 { + }; + l4_fast: interconnect@4a000000 { + }; + + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif: emif@0 { + compatible = "ti,emif-am4372"; + reg = <0 0x1000000>; + interrupts = ; + sram = <&pm_sram_code + &pm_sram_data>; + }; + }; + + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <58 59>; + }; + }; + + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@47810000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x478102fc 0x4>, + <0x47810110 0x4>, + <0x47810114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47810000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,am437-sdhci"; + ti,needs-special-reset; + interrupts = ; + reg = <0x0 0x1000>; + status = "disabled"; + }; + }; + + sham_target: target-module@53100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x53100100 0x4>, + <0x53100110 0x4>, + <0x53100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + dmas = <&edma 36 0>; + dma-names = "rx"; + interrupts = ; + }; + }; + + aes_target: target-module@53501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x53501080 0x4>, + <0x53501084 0x4>, + <0x53501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53501000 0x1000>; + + aes: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&edma 6 0>, + <&edma 5 0>; + dma-names = "tx", "rx"; + }; + }; + + des_target: target-module@53701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x53701030 0x4>, + <0x53701034 0x4>, + <0x53701038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x53701000 0x1000>; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&edma 34 0>, + <&edma 33 0>; + dma-names = "tx", "rx"; + }; + }; + + pruss_tm: target-module@54400000 { + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x54426000 0x4>, + <0x54426004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_per 1>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54400000 0x80000>; + + pruss1: pruss@0 { + compatible = "ti,am4376-pruss1"; + reg = <0x0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&sysclk_div>, /* icss_iep_gclk */ + <&pruss_ocp_gclk>; /* icss_ocp_gclk */ + }; + }; + }; + + pruss1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss1_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", + "host_intr6", "host_intr7"; + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ + }; + + pru1_0: pru@34000 { + compatible = "ti,am4376-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,am4376-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru1_1-fw"; + }; + + pruss1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pruss0: pruss@40000 { + compatible = "ti,am4376-pruss0"; + reg = <0x40000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss0_mem: memories@40000 { + reg = <0x40000 0x1000>, + <0x42000 0x1000>; + reg-names = "dram0", "dram1"; + }; + + pruss0_cfg: cfg@66000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x66000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss0_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&sysclk_div>, /* icss_iep_gclk */ + <&pruss_ocp_gclk>; /* icss_ocp_gclk */ + }; + }; + }; + + pruss0_mii_rt: mii-rt@72000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x72000 0x58>; + status = "disabled"; + }; + + pruss0_intc: interrupt-controller@60000 { + compatible = "ti,pruss-intc"; + reg = <0x60000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", + "host_intr6", "host_intr7"; + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ + }; + + pru0_0: pru@74000 { + compatible = "ti,am4376-pru"; + reg = <0x74000 0x1000>, + <0x62000 0x400>, + <0x62400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru0_0-fw"; + }; + + pru0_1: pru@78000 { + compatible = "ti,am4376-pru"; + reg = <0x78000 0x1000>, + <0x64000 0x400>, + <0x64400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru0_1-fw"; + }; + }; + }; + + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = ; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + target-module@47900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x47900000 0x4>, + <0x47900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47900000 0x1000>, + <0x30000000 0x30000000 0x4000000>; + + qspi: spi@0 { + compatible = "ti,am4372-qspi"; + reg = <0 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; + clocks = <&dpll_per_m2_div4_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 138 0x4>; + num-cs = <4>; + }; + }; + + target-module@40300000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40300000 0x40000>; + + ocmcram: sram@0 { + compatible = "mmio-sram"; + reg = <0 0x40000>; /* 256k */ + ranges = <0 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + + pm_sram_code: pm-code-sram@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-data-sram@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; + }; + }; + + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; + clock-names = "fck"; + power-domains = <&prm_gfx>; + resets = <&prm_gfx 0>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x1000000>; + }; + }; +}; + +#include "am437x-l4.dtsi" +#include "am43xx-clocks.dtsi" + +&prcm { + prm_mpu: prm@300 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + + prm_gfx: prm@400 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x400 0x100>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + prm_rtc: prm@500 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #power-domain-cells = <0>; + }; + + prm_tamper: prm@600 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x600 0x100>; + #power-domain-cells = <0>; + }; + + prm_cefuse: prm@700 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x700 0x100>; + #power-domain-cells = <0>; + }; + + prm_per: prm@800 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x800 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_wkup: prm@2000 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x2000 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_device: prm@4000 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x4000 0x100>; + #reset-cells = <1>; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck", "ick"; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck", "ick"; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts new file mode 100644 index 000000000000..9ec75d03eaff --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + */ + +/dts-v1/; + +#include +#include +#include +#include "am4372.dtsi" + +/ { + model = "CompuLab CM-T43"; + compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; + + leds { + compatible = "gpio-leds"; + + ledb { + label = "cm-t43:green"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vmmc_3v3: fixedregulator-v3_3 { + compatible = "regulator-fixed"; + regulator-name = "vmmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + enable-active-high; + }; +}; + +&am43xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&cm_t43_led_pins>; + + cm_t43_led_pins: cm-t43-led-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa78, MUX_MODE7) + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + emmc_pins: emmc-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ + AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ + AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */ + AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */ + AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */ + AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */ + AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */ + AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */ + AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ + AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ + AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; + + nand_flash_x8: nand-flash-x8-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) + AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ + AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ + AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + AM4372_IOPAD(0xa74, MUX_MODE3) + /* Slave 2 */ + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */ + AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */ + AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */ + AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */ + AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */ + AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */ + AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */ + AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */ + AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */ + AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */ + AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */ + AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */ + AM4372_IOPAD(0xa38, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0x08000000 0x1000000>; + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + /* MTD partition table */ + partition@0 { + label = "kernel"; + reg = <0x0 0x00980000>; + }; + partition@980000 { + label = "dtb"; + reg = <0x00980000 0x00080000>; + }; + partition@a00000 { + label = "rootfs"; + reg = <0x00a00000 0x0>; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps65218: tps65218@24 { + compatible = "ti,tps65218"; + reg = <0x24>; + interrupts = ; /* NMIn */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + regulator-name = "vdcdc3"; + regulator-suspend-enable; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc6: regulator-dcdc6 { + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + eeprom_module: at24@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&vmmc_3v3>; + bus-width = <8>; + non-removable; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + dmas = <&edma 16 0 + &edma 17 0>; + dma-names = "tx0", "rx0"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + partition@0 { + label = "uboot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "uboot environment"; + reg = <0xc0000 0x40000>; + }; + + partition@100000 { + label = "reserved"; + reg = <0x100000 0x100000>; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-txid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-txid"; + ti,dual-emac-pvid = <2>; +}; + +&dwc3_1 { + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +&dwc3_2 { + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; + interrupts = , + , + ; + interrupt-names = "peripheral", "host", "otg"; +}; + +&elm { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +&cpu { + cpu0-supply = <&dcdc2>; + operating-points = <1000000 1330000>, + <800000 1260000>, + <720000 1200000>, + <600000 1100000>, + <300000 950000>; +}; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts new file mode 100644 index 000000000000..f7aad0323d19 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts @@ -0,0 +1,1137 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* AM437x GP EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include + +/ { + model = "TI AM437x GP EVM"; + compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart0; + }; + + evm_v3_3d: fixedregulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "evm_v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + matrix_keypad: matrix_keypad0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&matrix_keypad_default>; + pinctrl-1 = <&matrix_keypad_sleep>; + + wakeup-source; + + row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ + &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ + &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ + + col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ + &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x00010202 /* P2 */ + 0x01000067 /* UP */ + 0x0101006a /* RIGHT */ + 0x02000069 /* LEFT */ + 0x0201006c>; /* DOWN */ + }; + + lcd0: display { + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + /* fixed 12MHz oscillator */ + refclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM437x-GP-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <12000000>; + }; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&beeper_pins_default>; + pinctrl-1 = <&beeper_pins_sleep>; + gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + }; +}; + +&am43xx_pinmux { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; + pinctrl-1 = <&wlan_pins_sleep>; + + ddr3_vtt_toggle_default: ddr-vtt-toggle-default-pins { + pinctrl-single,pins = < + 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + pixcir_ts_pins: pixcir-ts-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ + AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ + AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nand_flash_x8: nand-flash-x8-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + dss_pins: dss-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + display_mux_pins: display-mux-pins { + pinctrl-single,pins = < + /* GPIO 5_8 to select LCD / HDMI */ + AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + dcan0_default: dcan0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + >; + }; + + dcan0_sleep: dcan0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ + AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ + >; + }; + + dcan1_default: dcan1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ + AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ + >; + }; + + dcan1_sleep: dcan1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ + AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ + >; + }; + + vpfe0_pins_default: vpfe0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ + AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ + AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ + AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ + AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ + AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ + AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ + AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ + AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ + AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ + AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ + >; + }; + + vpfe0_pins_sleep: vpfe0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ + AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ + AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ + AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ + AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ + AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ + AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ + AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ + AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ + AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ + AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ + AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ + AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ + >; + }; + + vpfe1_pins_default: vpfe1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ + AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ + AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ + AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ + AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ + >; + }; + + vpfe1_pins_sleep: vpfe1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ + AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ + AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ + AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ + AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ + AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ + AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ + AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ + AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ + AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ + AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ + AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ + AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ + >; + }; + + mmc3_pins_default: mmc3-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: mmc3-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ + AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ + AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ + AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ + AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ + AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ + >; + }; + + wlan_pins_default: wlan-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + >; + }; + + wlan_pins_sleep: wlan-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ + AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ + AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ + AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ + >; + }; + + mcasp1_pins: mcasp1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_sleep_pins: mcasp1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + gpio0_pins: gpio0-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ + >; + }; + + emmc_pins_default: emmc-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + >; + }; + + emmc_pins_sleep: emmc-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ + AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ + AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ + AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ + AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ + AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ + >; + }; + + beeper_pins_default: beeper-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ + >; + }; + + beeper_pins_sleep: beeper-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ + >; + }; + + unused_pins: unused-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) + AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) + AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) + AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) + AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + debugss_pins: debugss-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) + >; + }; + + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart0_pins_sleep: uart0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + matrix_keypad_default: matrix-keypad-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) + AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) + AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + matrix_keypad_sleep: matrix-keypad-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) + AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) + AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_pins_default>; + pinctrl-1 = <&uart0_pins_sleep>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + regulator-name = "vdcdc3"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + dcdc5: regulator-dcdc5 { + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc6: regulator-dcdc6 { + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo1: regulator-ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&refclk 0>; + clock-names = "xvclk"; + + port { + ov2659_0: endpoint { + remote-endpoint = <&vpfe1_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; + reg = <0x5c>; + + attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + + /* + * 0x264 represents the offset of padconf register of + * gpio3_22 from am43xx_pinmux base. + */ + interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, + <&am43xx_pinmux 0x264>; + interrupt-names = "tsc", "wakeup"; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + wakeup-source; + }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&refclk 0>; + clock-names = "xvclk"; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe0_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> EN: V1_8D -> VBAT */ + AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ + DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ + DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&magadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins>; + status = "okay"; + + sel-emmc-nand-hog { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + /* SelEMMCorNAND selects between eMMC and NAND: + * Low: NAND + * High: eMMC + * When changing this line make sure the newly + * selected device node is enabled and the previously + * selected device node is disabled. + */ + output-low; + line-name = "SelEMMCorNAND"; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5_target { + ti,no-reset-on-init; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&display_mux_pins>; + status = "okay"; + + sel-lcd-hdmi-hog { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SelLCDorHDMI"; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&evm_v3_3d>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +/* eMMC sits on mmc2 */ +&mmc2 { + /* + * When enabling eMMC, disable GPMC/NAND and set + * SelEMMCorNAND to output-high + */ + status = "disabled"; + vmmc-supply = <&evm_v3_3d>; + bus-width = <8>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&emmc_pins_default>; + pinctrl-1 = <&emmc_pins_sleep>; + non-removable; +}; + +&mmc3 { + status = "okay"; + /* these are on the crossbar and are outlined in the + xbar-event-map element */ + dmas = <&edma_xbar 30 0 1>, + <&edma_xbar 31 0 2>; + dma-names = "tx", "rx"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_sleep>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + /* + * When enabling GPMC, disable eMMC and set + * SelEMMCorNAND to output-low + */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000c0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002c0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x1f600000>; + }; + }; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&dcan0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan0_default>; + pinctrl-1 = <&dcan0_sleep>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan1_default>; + pinctrl-1 = <&dcan1_sleep>; + status = "okay"; +}; + +&vpfe0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe0_pins_default>; + pinctrl-1 = <&vpfe0_pins_sleep>; + + port { + vpfe0_ep: endpoint { + remote-endpoint = <&ov2659_1>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&vpfe1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe1_pins_default>; + pinctrl-1 = <&vpfe1_pins_sleep>; + + port { + vpfe1_ep: endpoint { + remote-endpoint = <&ov2659_0>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; + status = "okay"; +}; + +&cpu { + cpu0-supply = <&dcdc2>; +}; + +&wkup_m3_ipc { + ti,set-io-isolation; + firmware-name = "am43x-evm-scale-data.bin"; +}; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts new file mode 100644 index 000000000000..863552393c07 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include + +/ { + model = "TI AM437x Industrial Development Kit"; + compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; + + chosen { + stdout-path = &uart0; + }; + + v24_0d: fixed-regulator-v24_0d { + compatible = "regulator-fixed"; + regulator-name = "V24_0D"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + regulator-boot-on; + }; + + v3_3d: fixed-regulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "V3_3D"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + vdd_corereg: fixed-regulator-vdd_corereg { + compatible = "regulator-fixed"; + regulator-name = "VDD_COREREG"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + vdd_core: fixed-regulator-vdd_core { + compatible = "regulator-fixed"; + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_corereg>; + }; + + v1_8dreg: fixed-regulator-v1_8dreg{ + compatible = "regulator-fixed"; + regulator-name = "V1_8DREG"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + v1_8d: fixed-regulator-v1_8d{ + compatible = "regulator-fixed"; + regulator-name = "V1_8D"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v1_8dreg>; + }; + + v1_5dreg: fixed-regulator-v1_5dreg{ + compatible = "regulator-fixed"; + regulator-name = "V1_5DREG"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + v1_5d: fixed-regulator-v1_5d{ + compatible = "regulator-fixed"; + regulator-name = "V1_5D"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v1_5dreg>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + switch-0 { + label = "power-button"; + linux,code = ; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + }; + }; + + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am43xx_pinmux { + gpio_keys_pins_default: gpio-keys-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ + >; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c0_pins_sleep: i2c0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c2_pins_default: i2c2-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ + AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ + >; + }; + + i2c2_pins_sleep: i2c2-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mmc1_pins_sleep: mmc1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + spi1_pins_default: spi1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ + AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ + AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ + AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ + >; + }; + + spi1_pins_sleep: spi1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + ecap0_pins_default: backlight-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + qspi_pins_default: qspi-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + >; + }; + + qspi_pins_sleep: qspi-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_pins_default>; + pinctrl-1 = <&i2c0_pins_sleep>; + clock-frequency = <400000>; + + at24@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + tps: tps62362@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1330000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + vin-supply = <&v3_3d>; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_default>; + pinctrl-1 = <&i2c2_pins_sleep>; + clock-frequency = <100000>; + + tpic2810: tpic2810@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins_default>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; + vmmc-supply = <&v3_3d>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_pins_default>; + pinctrl-1 = <&qspi_pins_sleep>; + + spi-max-frequency = <48000000>; + flash@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * MTD partition table. The ROM checks the first 512KiB for a + * valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x00080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&cpu { + cpu0-supply = <&tps>; +}; + +&cpu0_opp_table { + /* + * Supply voltage supervisor on board will not allow opp50 so + * disable it and set opp100 as suspend OPP. + */ + opp50-300000000 { + status = "disabled"; + }; + + opp100-600000000 { + opp-suspend; + }; +}; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi new file mode 100644 index 000000000000..415210b034ef --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi @@ -0,0 +1,2584 @@ +&l4_wkup { /* 0x44c00000 */ + compatible = "ti,am4-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkup>; + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x44c00000 0x800>, + <0x44c00800 0x800>, + <0x44c01000 0x400>, + <0x44c01400 0x400>; + reg-names = "ap", "la", "ia0", "ia1"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ + <0x00100000 0x44d00000 0x100000>, /* segment 1 */ + <0x00200000 0x44e00000 0x100000>; /* segment 2 */ + + segment@0 { /* 0x44c00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>; /* ap 3 */ + }; + + segment@100000 { /* 0x44d00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ + <0x00004000 0x00104000 0x001000>, /* ap 5 */ + <0x00080000 0x00180000 0x002000>, /* ap 6 */ + <0x00082000 0x00182000 0x001000>, /* ap 7 */ + <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ + + target-module@0 { /* 0x44d00000, ap 4 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>; + reg-names = "rev"; + clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x4000>, + <0x00080000 0x00080000 0x2000>; + + wkup_m3: cpu@0 { + compatible = "ti,am4372-wkup-m3"; + reg = <0x00000000 0x4000>, + <0x00080000 0x2000>; + reg-names = "umem", "dmem"; + resets = <&prm_wkup 3>; + reset-names = "rstctrl"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + }; + + target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xf0000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0000 0x10000>; + + prcm: prcm@0 { + compatible = "ti,am4-prcm", "simple-bus"; + reg = <0x0 0x11000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + }; + }; + + segment@200000 { /* 0x44e00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ + <0x00003000 0x00203000 0x001000>, /* ap 10 */ + <0x00004000 0x00204000 0x001000>, /* ap 11 */ + <0x00005000 0x00205000 0x001000>, /* ap 12 */ + <0x00006000 0x00206000 0x001000>, /* ap 13 */ + <0x00007000 0x00207000 0x001000>, /* ap 14 */ + <0x00008000 0x00208000 0x001000>, /* ap 15 */ + <0x00009000 0x00209000 0x001000>, /* ap 16 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ + <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ + <0x00010000 0x00210000 0x010000>, /* ap 22 */ + <0x00030000 0x00230000 0x001000>, /* ap 23 */ + <0x00031000 0x00231000 0x001000>, /* ap 24 */ + <0x00032000 0x00232000 0x001000>, /* ap 25 */ + <0x00033000 0x00233000 0x001000>, /* ap 26 */ + <0x00034000 0x00234000 0x001000>, /* ap 27 */ + <0x00035000 0x00235000 0x001000>, /* ap 28 */ + <0x00036000 0x00236000 0x001000>, /* ap 29 */ + <0x00037000 0x00237000 0x001000>, /* ap 30 */ + <0x00038000 0x00238000 0x001000>, /* ap 31 */ + <0x00039000 0x00239000 0x001000>, /* ap 32 */ + <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ + <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ + <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ + <0x00040000 0x00240000 0x040000>, /* ap 36 */ + <0x00080000 0x00280000 0x001000>, /* ap 37 */ + <0x00088000 0x00288000 0x008000>, /* ap 38 */ + <0x00092000 0x00292000 0x001000>, /* ap 39 */ + <0x00086000 0x00286000 0x001000>, /* ap 40 */ + <0x00087000 0x00287000 0x001000>, /* ap 41 */ + <0x00090000 0x00290000 0x001000>, /* ap 42 */ + <0x00091000 0x00291000 0x001000>; /* ap 43 */ + + target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + + target-module@5000 { /* 0x44e05000, ap 12 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + target-module@7000 { /* 0x44e07000, ap 14 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x7000 0x4>, + <0x7010 0x4>, + <0x7114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + + gpio0: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; + + target-module@9000 { /* 0x44e09000, ap 16 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9050 0x4>, + <0x9054 0x4>, + <0x9058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9000 0x1000>; + + uart0: serial@0 { + compatible = "ti,am4372-uart"; + reg = <0x0 0x2000>; + interrupts = ; + }; + }; + + target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xb000 0x8>, + <0xb010 0x8>, + <0xb090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000 0x1000>; + + i2c0: i2c@0 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd000 0x4>, + <0xd010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ + clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd000 0x1000>; + + tscadc: tscadc@0 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + + }; + }; + + target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x10000 0x4>; + reg-names = "rev"; + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x10000>; + + scm: scm@0 { + compatible = "ti,am4-scm", "simple-bus"; + reg = <0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4000>; + + am43xx_pinmux: pinmux@800 { + compatible = "ti,am437-padconf", + "pinctrl-single"; + reg = <0x800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am43xx-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am4372-wkup-m3-ipc"; + reg = <0x1324 0x44>; + interrupts = ; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <64>; + dma-masters = <&edma>; + }; + + scm_clockdomains: clockdomains { + }; + }; + }; + + timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x31000 0x4>, + <0x31010 0x4>, + <0x31014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x31000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; + }; + + target-module@33000 { /* 0x44e33000, ap 26 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x33000 0x1000>; + }; + + target-module@35000 { /* 0x44e35000, ap 28 50.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x35000 0x4>, + <0x35010 0x4>, + <0x35014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x35000 0x1000>; + + wdt: wdt@0 { + compatible = "ti,am4372-wdt","ti,omap3-wdt"; + reg = <0x0 0x1000>; + interrupts = ; + }; + }; + + target-module@37000 { /* 0x44e37000, ap 30 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x37000 0x1000>; + }; + + target-module@39000 { /* 0x44e39000, ap 32 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x39000 0x1000>; + }; + + rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x3e074 0x4>, + <0x3e078 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ + power-domains = <&prm_rtc>; + clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + rtc: rtc@0 { + compatible = "ti,am4372-rtc", "ti,am3352-rtc", + "ti,da830-rtc"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&clk_32768_ck>; + clock-names = "int-clk"; + system-power-controller; + status = "disabled"; + }; + }; + + target-module@40000 { /* 0x44e40000, ap 36 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x40000>; + }; + + target-module@86000 { /* 0x44e86000, ap 40 70.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x86000 0x4>, + <0x86004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ + clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,am4372-counter32k","ti,omap-counter32k"; + reg = <0x0 0x40>; + }; + }; + + target-module@88000 { /* 0x44e88000, ap 38 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00088000 0x00008000>, + <0x00008000 0x00090000 0x00001000>, + <0x00009000 0x00091000 0x00001000>; + }; + }; +}; + +&l4_fast { /* 0x4a000000 */ + compatible = "ti,am4-l4-fast", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x400>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00100000 0x00100000 0x008000>, /* ap 3 */ + <0x00108000 0x00108000 0x001000>, /* ap 4 */ + <0x00400000 0x00400000 0x002000>, /* ap 5 */ + <0x00402000 0x00402000 0x001000>, /* ap 6 */ + <0x00200000 0x00200000 0x080000>, /* ap 7 */ + <0x00280000 0x00280000 0x001000>; /* ap 8 */ + + target-module@100000 { /* 0x4a100000, ap 3 04.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x101200 0x4>, + <0x101208 0x4>, + <0x101204 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x8000>; + + mac_sw: switch@0 { + compatible = "ti,am4372-cpsw-switch", "ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>; + clock-names = "fck", "50mclk"; + assigned-clocks = <&dpll_clksel_mac_clk>; + assigned-clock-rates = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + status = "disabled"; + + interrupts = ; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "port2"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; + }; + }; + + davinci_mdio_sw: mdio@1000 { + compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + }; + + cpts { + clocks = <&cpsw_cpts_rft_clk>; + clock-names = "cpts"; + }; + }; + }; + + target-module@200000 { /* 0x4a200000, ap 7 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200000 0x80000>; + }; + + target-module@400000 { /* 0x4a400000, ap 5 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x400000 0x2000>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,am4-l4-per", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ + <0x00100000 0x48100000 0x100000>, /* segment 1 */ + <0x00200000 0x48200000 0x100000>, /* segment 2 */ + <0x00300000 0x48300000 0x100000>, /* segment 3 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>, /* ap 3 */ + <0x00001800 0x00001800 0x000400>, /* ap 4 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ + <0x00008000 0x00008000 0x001000>, /* ap 6 */ + <0x00009000 0x00009000 0x001000>, /* ap 7 */ + <0x00022000 0x00022000 0x001000>, /* ap 8 */ + <0x00023000 0x00023000 0x001000>, /* ap 9 */ + <0x00024000 0x00024000 0x001000>, /* ap 10 */ + <0x00025000 0x00025000 0x001000>, /* ap 11 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ + <0x00038000 0x00038000 0x002000>, /* ap 14 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ + <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ + <0x00040000 0x00040000 0x001000>, /* ap 18 */ + <0x00041000 0x00041000 0x001000>, /* ap 19 */ + <0x00042000 0x00042000 0x001000>, /* ap 20 */ + <0x00043000 0x00043000 0x001000>, /* ap 21 */ + <0x00044000 0x00044000 0x001000>, /* ap 22 */ + <0x00045000 0x00045000 0x001000>, /* ap 23 */ + <0x00046000 0x00046000 0x001000>, /* ap 24 */ + <0x00047000 0x00047000 0x001000>, /* ap 25 */ + <0x00048000 0x00048000 0x001000>, /* ap 26 */ + <0x00049000 0x00049000 0x001000>, /* ap 27 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ + <0x00060000 0x00060000 0x001000>, /* ap 30 */ + <0x00061000 0x00061000 0x001000>, /* ap 31 */ + <0x00080000 0x00080000 0x010000>, /* ap 32 */ + <0x00090000 0x00090000 0x001000>, /* ap 33 */ + <0x00030000 0x00030000 0x001000>, /* ap 65 */ + <0x00031000 0x00031000 0x001000>, /* ap 66 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ + <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ + <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ + <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ + <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ + <0x00034000 0x00034000 0x001000>, /* ap 80 */ + <0x00035000 0x00035000 0x001000>, /* ap 81 */ + <0x00036000 0x00036000 0x001000>, /* ap 84 */ + <0x00037000 0x00037000 0x001000>, /* ap 85 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ + + target-module@8000 { /* 0x48008000, ap 6 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@22000 { /* 0x48022000, ap 8 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x22050 0x4>, + <0x22054 0x4>, + <0x22058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + + uart1: serial@0 { + compatible = "ti,am4372-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@24000 { /* 0x48024000, ap 10 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x24050 0x4>, + <0x24054 0x4>, + <0x24058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + uart2: serial@0 { + compatible = "ti,am4372-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2a000 0x8>, + <0x2a010 0x8>, + <0x2a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@30000 { /* 0x48030000, ap 65 08.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x30000 0x4>, + <0x30110 0x4>, + <0x30114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + + spi0: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@34000 { /* 0x48034000, ap 80 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + }; + + target-module@36000 { /* 0x48036000, ap 84 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@38000 { /* 0x48038000, ap 14 04.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x38000 0x4>, + <0x38004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x2000>, + <0x46000000 0x46000000 0x400000>; + + mcasp0: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; + }; + }; + + target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x3c000 0x4>, + <0x3c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x2000>, + <0x46400000 0x46400000 0x400000>; + + mcasp1: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10 2>, + <&edma 11 2>; + dma-names = "tx", "rx"; + }; + }; + + timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>, + <0x40014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; + }; + + target-module@42000 { /* 0x48042000, ap 20 24.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x42000 0x4>, + <0x42010 0x4>, + <0x42014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + + timer3: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@44000 { /* 0x48044000, ap 22 26.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x44000 0x4>, + <0x44010 0x4>, + <0x44014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + + timer4: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; + }; + + target-module@46000 { /* 0x48046000, ap 24 28.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x46000 0x4>, + <0x46010 0x4>, + <0x46014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + + timer5: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; + }; + + target-module@48000 { /* 0x48048000, ap 26 1a.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x48000 0x4>, + <0x48010 0x4>, + <0x48014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + + timer6: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; + }; + + target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x4a000 0x4>, + <0x4a010 0x4>, + <0x4a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + + timer7: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; + }; + + target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>, + <0x4c114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; + + target-module@60000 { /* 0x48060000, ap 30 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x602fc 0x4>, + <0x60110 0x4>, + <0x60114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,am437-sdhci"; + reg = <0x0 0x1000>; + ti,needs-special-reset; + dmas = <&edma 24 0>, + <&edma 25 0>; + dma-names = "tx", "rx"; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@80000 { /* 0x48080000, ap 32 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x80000 0x4>, + <0x80010 0x4>, + <0x80014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc8000 0x4>, + <0xc8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + mbox_wkupm3: mbox-wkup-m3 { + ti,mbox-send-noirq; + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; + }; + }; + + target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xca000 0x4>, + <0xca010 0x4>, + <0xca014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xca000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + }; + + segment@100000 { /* 0x48100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ + <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ + <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ + <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ + <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ + <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ + <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ + <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ + <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ + <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ + <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ + <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ + <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ + <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ + <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ + <0x000af000 0x001af000 0x001000>, /* ap 49 */ + <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ + <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ + <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ + <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ + <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ + <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ + <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ + <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ + <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ + <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ + <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ + <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ + <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ + <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ + + target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8c000 0x1000>; + }; + + target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8e000 0x1000>; + }; + + target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9c000 0x8>, + <0x9c010 0x8>, + <0x9c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa0000 0x4>, + <0xa0110 0x4>, + <0xa0114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x1000>; + + spi1: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa2000 0x4>, + <0xa2110 0x4>, + <0xa2114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + + spi2: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa4000 0x4>, + <0xa4110 0x4>, + <0xa4114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa4000 0x1000>; + + spi3: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa6050 0x4>, + <0xa6054 0x4>, + <0xa6058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa6000 0x1000>; + + uart3: serial@0 { + compatible = "ti,am4372-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa8050 0x4>, + <0xa8054 0x4>, + <0xa8058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x1000>; + + uart4: serial@0 { + compatible = "ti,am4372-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xaa050 0x4>, + <0xaa054 0x4>, + <0xaa058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xaa000 0x1000>; + + uart5: serial@0 { + compatible = "ti,am4372-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xac000 0x4>, + <0xac010 0x4>, + <0xac114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xac000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; + + target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xae000 0x4>, + <0xae010 0x4>, + <0xae114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xae000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; + + target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0xc1000 0x4>, + <0xc1010 0x4>, + <0xc1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc1000 0x1000>; + + timer8: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xcc020 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, + <&dcan0_fck>; + clock-names = "fck", "osc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xcc000 0x2000>; + + dcan0: can@0 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0 0x2000>; + clocks = <&dcan0_fck>; + clock-names = "fck"; + syscon-raminit = <&scm_conf 0x644 0>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd0020 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, + <&dcan1_fck>; + clock-names = "fck", "osc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000 0x2000>; + + dcan1: can@0 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0 0x2000>; + clocks = <&dcan1_fck>; + clock-names = "fck"; + syscon-raminit = <&scm_conf 0x644 1>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xd82fc 0x4>, + <0xd8110 0x4>, + <0xd8114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd8000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,am437-sdhci"; + reg = <0x0 0x1000>; + ti,needs-special-reset; + dmas = <&edma 2 0>, + <&edma 3 0>; + dma-names = "tx", "rx"; + interrupts = ; + status = "disabled"; + }; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x010000>; + + target-module@0 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10000>; + + mpu@0 { + compatible = "ti,omap4-mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; + }; + }; + }; + + segment@300000 { /* 0x48300000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ + <0x00001000 0x00301000 0x001000>, /* ap 57 */ + <0x00002000 0x00302000 0x001000>, /* ap 58 */ + <0x00003000 0x00303000 0x001000>, /* ap 59 */ + <0x00004000 0x00304000 0x001000>, /* ap 60 */ + <0x00005000 0x00305000 0x001000>, /* ap 61 */ + <0x00018000 0x00318000 0x004000>, /* ap 62 */ + <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ + <0x00010000 0x00310000 0x002000>, /* ap 64 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00012000 0x00312000 0x001000>, /* ap 79 */ + <0x00020000 0x00320000 0x001000>, /* ap 82 */ + <0x00021000 0x00321000 0x001000>, /* ap 83 */ + <0x00026000 0x00326000 0x001000>, /* ap 86 */ + <0x00027000 0x00327000 0x001000>, /* ap 87 */ + <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ + <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ + <0x00013000 0x00313000 0x001000>, /* ap 90 */ + <0x00014000 0x00314000 0x001000>, /* ap 91 */ + <0x00006000 0x00306000 0x001000>, /* ap 96 */ + <0x00007000 0x00307000 0x001000>, /* ap 97 */ + <0x00008000 0x00308000 0x001000>, /* ap 98 */ + <0x00009000 0x00309000 0x001000>, /* ap 99 */ + <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ + <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ + <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ + <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ + <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ + <0x00040000 0x00340000 0x001000>, /* ap 105 */ + <0x00041000 0x00341000 0x001000>, /* ap 106 */ + <0x00042000 0x00342000 0x001000>, /* ap 107 */ + <0x00045000 0x00345000 0x001000>, /* ap 108 */ + <0x00046000 0x00346000 0x001000>, /* ap 109 */ + <0x00047000 0x00347000 0x001000>, /* ap 110 */ + <0x00048000 0x00348000 0x001000>, /* ap 111 */ + <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ + <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ + <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ + <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ + <0x00022000 0x00322000 0x001000>, /* ap 116 */ + <0x00023000 0x00323000 0x001000>, /* ap 117 */ + <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ + <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ + <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ + <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ + <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ + <0x00080000 0x00380000 0x020000>, /* ap 123 */ + <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ + <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ + <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ + <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ + <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ + <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ + + target-module@0 { /* 0x48300000, ap 56 40.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>, + <0x4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + epwmss0: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ecap0: pwm@100 { + compatible = "ti,am4372-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm0: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@2000 { /* 0x48302000, ap 58 4a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + epwmss1: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ecap1: pwm@100 { + compatible = "ti,am4372-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm1: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@4000 { /* 0x48304000, ap 60 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + epwmss2: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ecap2: pwm@100 { + compatible = "ti,am4372-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm2: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@6000 { /* 0x48306000, ap 96 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>, + <0x6004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + + epwmss3: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ehrpwm3: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@8000 { /* 0x48308000, ap 98 54.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>, + <0x8004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + + epwmss4: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ehrpwm4: pwm@48308200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@a000 { /* 0x4830a000, ap 100 60.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>, + <0xa004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + epwmss5: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ehrpwm5: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@10000 { /* 0x48310000, ap 64 4e.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x11fe0 0x4>, + <0x11fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; + }; + + target-module@13000 { /* 0x48313000, ap 90 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x13000 0x1000>; + }; + + target-module@18000 { /* 0x48318000, ap 62 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x4000>; + }; + + target-module@20000 { /* 0x48320000, ap 82 34.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20010 0x4>, + <0x20114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; + + gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x22000 0x4>, + <0x22010 0x4>, + <0x22114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; + + target-module@26000 { /* 0x48326000, ap 86 66.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x26000 0x4>, + <0x26104 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + + vpfe0: vpfe@0 { + compatible = "ti,am437x-vpfe"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@28000 { /* 0x48328000, ap 75 0e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x28000 0x4>, + <0x28104 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + + vpfe1: vpfe@0 { + compatible = "ti,am437x-vpfe"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2a000 0x4>, + <0x2a010 0x4>, + <0x2a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, dss_clkdm */ + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x0002a000 0x00000400>, + <0x00000400 0x0002a400 0x00000400>, + <0x00000800 0x0002a800 0x00000400>, + <0x00000c00 0x0002ac00 0x00000400>, + <0x00001000 0x0002b000 0x00001000>; + + dss: dss@0 { + compatible = "ti,omap3-dss"; + reg = <0 0x200>; + status = "disabled"; + clocks = <&disp_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00000400>, + <0x00000400 0x00000400 0x00000400>, + <0x00000800 0x00000800 0x00000400>, + <0x00000c00 0x00000c00 0x00000400>, + <0x00001000 0x00001000 0x00001000>; + + target-module@400 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x400 0x4>, + <0x410 0x4>, + <0x414 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-midle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x400>; + + dispc: dispc@0 { + compatible = "ti,omap3-dispc"; + reg = <0 0x400>; + interrupts = ; + clocks = <&disp_clk>; + clock-names = "fck"; + + max-memory-bandwidth = <230000000>; + }; + }; + + target-module@800 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x800 0x4>, + <0x810 0x4>, + <0x814 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x400>; + + rfbi: rfbi@0 { + compatible = "ti,omap3-rfbi"; + reg = <0 0x100>; + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + status = "disabled"; + }; + }; + }; + }; + + target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3d000 0x4>, + <0x3d010 0x4>, + <0x3d014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3d000 0x1000>; + + timer9: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3f000 0x4>, + <0x3f010 0x4>, + <0x3f014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3f000 0x1000>; + + timer10: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@41000 { /* 0x48341000, ap 106 76.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x41000 0x4>, + <0x41010 0x4>, + <0x41014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x41000 0x1000>; + + timer11: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@45000 { /* 0x48345000, ap 108 6a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x45000 0x4>, + <0x45110 0x4>, + <0x45114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x45000 0x1000>; + + spi4: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@47000 { /* 0x48347000, ap 110 70.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x47000 0x4>, + <0x47014 0x4>, + <0x47018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47000 0x1000>; + + hdq: hdq@0 { + compatible = "ti,am4372-hdq"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&func_12m_clk>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x2000>; + + magadc: magadc@0 { + compatible = "ti,am4372-magadc"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&adc_mag_fck>; + clock-names = "fck"; + dmas = <&edma 54 0>, <&edma 55 0>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + mag { + compatible = "ti,am4372-mag"; + }; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am4372-adc"; + }; + }; + }; + + target-module@80000 { /* 0x48380000, ap 123 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x80000 0x4>, + <0x80010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x20000>; + + dwc3_1: omap_dwc3@0 { + compatible = "ti,am437x-dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges = <0 0 0x20000>; + + usb1: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy1>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; + }; + + target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa8000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x8000>; + + ocp2scp0: ocp2scp@0 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + + usb2_phy1: phy@8000 { + compatible = "ti,am437x-usb2"; + reg = <0x0 0x8000>; + syscon-phy-power = <&scm_conf 0x620>; + clocks = <&usb_phy0_always_on_clk32k>, + <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc0000 0x4>, + <0xc0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x20000>; + + dwc3_2: omap_dwc3@0 { + compatible = "ti,am437x-dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges = <0 0 0x20000>; + + usb2: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; + }; + + target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xe8000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe8000 0x8000>; + + ocp2scp1: ocp2scp@0 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + + usb2_phy2: phy@8000 { + compatible = "ti,am437x-usb2"; + reg = <0x0 0x8000>; + syscon-phy-power = <&scm_conf 0x628>; + clocks = <&usb_phy1_always_on_clk32k>, + <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf2000 0x2000>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts new file mode 100644 index 000000000000..34a5407bee15 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + */ + +#include "am437x-cm-t43.dts" +#include "compulab-sb-som.dtsi" + +/ { + model = "CompuLab CM-T43 on SB-SOM-T43"; + compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; + + aliases { + display0 = &lcd0; + }; +}; + +&am43xx_pinmux { + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ + >; + }; + + dss_pinctrl_default: dss-pinctrl-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ + AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x9b8, PIN_OUTPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x9bc, PIN_OUTPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x9c0, PIN_OUTPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x9c4, PIN_OUTPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x9c8, PIN_OUTPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam1 data 9 -> DSS DATA 16 */ + + AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ + AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + usb2_phy1_default: usb2-phy1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy2_default: usb2-phy2-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + pca9555: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom_base: at24@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&mmc1 { + status = "okay"; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vsb_3v3>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pinctrl_default>; + + port { + dpi_lcd_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_default>; +}; + +&dwc3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_phy1_default>; +}; + +&dwc3_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_phy2_default>; +}; + +&lcd0 { + enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH + &gpio4 28 GPIO_ACTIVE_HIGH>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + data-lines = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts new file mode 100644 index 000000000000..9c97006ffd5b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts @@ -0,0 +1,902 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* AM437x SK EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "TI AM437x SK EVM"; + compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart0; + }; + + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM437x-SK-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24000000>; + }; + }; + + matrix_keypad: matrix_keypad0 { + compatible = "gpio-matrix-keypad"; + + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_pins>; + + debounce-delay-ms = <5>; + col-scan-delay-us = <5>; + + row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ + &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ + + col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ + &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ + + linux,keymap = < + MATRIX_KEY(0, 0, KEY_DOWN) + MATRIX_KEY(0, 1, KEY_RIGHT) + MATRIX_KEY(1, 0, KEY_LEFT) + MATRIX_KEY(1, 1, KEY_UP) + >; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + led0 { + label = "am437x-sk:red:heartbeat"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "am437x-sk:green:mmc1"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "am437x-sk:blue:cpu0"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led3 { + label = "am437x-sk:blue:usr3"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ + default-state = "off"; + }; + }; + + lcd0: display { + compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + backlight = <&lcd_bl>; + + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + /* + * WL_EN is not SDIO standard compliant. It is an out of band + * signal and hard to be dealt with in a standard way by the + * SDIO core driver. + * So modelling the WL_EN line as a regulator was a natural + * choice as the MMC core already deals with MMC supplies. + */ + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&am43xx_pinmux { + matrix_keypad_pins: matrix-keypad-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ + AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ + AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ + AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ + >; + }; + + leds_pins: leds-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ + AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ + AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ + AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + >; + }; + + edt_ft5306_ts_pins: edt-ft5306-ts-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ + >; + }; + + vpfe0_pins_default: vpfe0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ + AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ + AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ + AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ + AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ + AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ + AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ + AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ + AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ + AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ + AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ + AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ + AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ + >; + }; + + vpfe0_pins_sleep: vpfe0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + >; + }; + + clkout1_pin: clkout1-pins { + pinctrl-single,pins = < + 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + + /* Slave 2 */ + AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ + AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value */ + AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + dss_pins: dss-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + qspi_pins: qspi-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + >; + }; + + mcasp1_pins: mcasp1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_pins_sleep: mcasp1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ + >; + }; + + usb1_pins: usb1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + >; + }; + + usb2_pins: usb2-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + >; + }; + + mmc3_pins_default: mmc3-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: mmc3-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */ + >; + }; + + wlan_pins_default: wlan-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ + AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ + >; + }; + + wlan_pins_sleep: wlan-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ + AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ + >; + }; + + uart1_bt_pins_default: uart1-bt-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ + >; + }; + + uart1_bt_pins_sleep: uart1-bt-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ + AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ + AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ + AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ + AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps@24 { + compatible = "ti,tps65218"; + reg = <0x24>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + /* VDD_CORE limits min of OPP50 and max of OPP100 */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + regulator-name = "vdds_ddr"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + dcdc4: regulator-dcdc4 { + regulator-name = "v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo1: regulator-ldo1 { + regulator-name = "v1_8d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + power-button { + compatible = "ti,tps65218-pwrbutton"; + status = "okay"; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + at24@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&clkout1_pin>; + + clocks = <&clkout1_mux_ck>; + clock-names = "xvclk"; + assigned-clocks = <&clkout1_mux_ck>; + assigned-clock-parents = <&clkout1_osc_div_ck>; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe0_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; + + edt-ft5306@38 { + status = "okay"; + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; + pinctrl-names = "default"; + pinctrl-0 = <&edt_ft5306_ts_pins>; + + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + + wakeup-source; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&dcdc4>; + IOVDD-supply = <&dcdc4>; + DRVDD-supply = <&dcdc4>; + DVDD-supply = <&ldo1>; + }; + + lis331dlh@18 { + compatible = "st,lis331dlh"; + reg = <0x18>; + status = "okay"; + + Vdd-supply = <&dcdc4>; + Vdd_IO-supply = <&dcdc4>; + interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&dcdc4>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_bt_pins_default>; + pinctrl-1 = <&uart1_bt_pins_sleep>; +}; + +&mmc3 { + status = "okay"; + /* + * these are on the crossbar and are outlined in the + * xbar-event-map element + */ + dmas = <&edma_xbar 30 0 1>, + <&edma_xbar 31 0 2>; + dma-names = "tx", "rx"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_sleep>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wlan_pins_default>; + pinctrl-1 = <&wlan_pins_sleep>; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + spi-max-frequency = <48000000>; + flash@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x00080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@4 { + reg = <4>; + }; + + ethphy1: ethernet-phy@5 { + reg = <5>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <2>; +}; + +&elm { + status = "okay"; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; + + status = "okay"; + + op-mode = <0>; + tdm-slots = <2>; + serial-dir = < + 0 0 1 2 + >; + + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&cpu { + cpu0-supply = <&dcdc2>; +}; + +&vpfe0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe0_pins_default>; + pinctrl-1 = <&vpfe0_pins_sleep>; + + /* Camera port */ + port { + vpfe0_ep: endpoint { + remote-endpoint = <&ov2659_1>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts b/arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts new file mode 100644 index 000000000000..9193a4cfba78 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts @@ -0,0 +1,1028 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* AM43x EPOS EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include + +/ { + model = "TI AM43x EPOS EVM"; + compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart0; + }; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lcd0: display { + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + matrix_keypad: matrix_keypad0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&matrix_keypad_default>; + pinctrl-1 = <&matrix_keypad_sleep>; + wakeup-source; + + row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ + &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ + &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ + &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ + + col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ + &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ + &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ + &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x01000204 /* P4 */ + 0x02000207 /* P7 */ + 0x0300020a /* NUMERIC_STAR */ + 0x00010202 /* P2 */ + 0x01010205 /* P5 */ + 0x02010208 /* P8 */ + 0x03010200 /* P0 */ + 0x00020203 /* P3 */ + 0x01020206 /* P6 */ + 0x02020209 /* P9 */ + 0x0302020b /* NUMERIC_POUND */ + 0x00030067 /* UP */ + 0x0103006a /* RIGHT */ + 0x0203006c /* DOWN */ + 0x03030069>; /* LEFT */ + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM43-EPOS-EVM"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MIC1LP", "Microphone Jack", + "MIC1RP", "Microphone Jack", + "MIC1LP", "MICBIAS", + "MIC1RP", "MICBIAS", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPL", + "Speaker", "SPR"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3111>; + system-clock-frequency = <12000000>; + }; + }; + + audio_mstrclk: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&am43xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&unused_pins>; + + unused_pins: unused-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + cpsw_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave 1 */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + cpsw_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + nand_flash_x8_default: nand-flash-x8-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ + AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + nand_flash_x8_sleep: nand-flash-x8-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + ecap0_pins_default: backlight-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + ecap0_pins_sleep: backlight-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ + >; + }; + + spi0_pins_default: spi0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ + AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ + AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; + + spi0_pins_sleep: spi0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + spi1_pins_default: spi1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ + AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + spi1_pins_sleep: spi1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mmc1_pins_sleep: mmc1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) + >; + }; + + matrix_keypad_default: matrix-keypad-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ + AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ + AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ + AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ + AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ + AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ + AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ + AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ + >; + }; + + matrix_keypad_sleep: matrix-keypad-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + qspi1_pins_default: qspi1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + qspi1_pins_sleep: qspi1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + pixcir_ts_pins_default: pixcir-ts-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + + pixcir_ts_pins_sleep: pixcir-ts-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + + hdq_pins: hdq-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ + >; + }; + + dss_pins: dss-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + >; + }; + + display_mux_pins: display-mux-pins { + pinctrl-single,pins = < + /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ + AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + vpfe1_pins_default: vpfe1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ + AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ + AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ + AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ + AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ + >; + }; + + vpfe1_pins_sleep: vpfe1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + >; + }; + + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart0_pins_sleep: uart0-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) + AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) + >; + }; + + usb2_phy1_default: usb2-phy1-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy1_sleep: usb2-phy1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb2_phy2_default: usb2-phy2-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy2_sleep: usb2-phy2-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mcasp1_pins: mcasp1-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ + AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ + AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ + AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ + >; + }; + + mcasp1_sleep_pins: mcasp1-sleep-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + ethphy0: ethernet-phy@16 { + reg = <16>; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phys = <&phy_gmii_sel 1 1>; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + regulator-name = "vdcdc3"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + dcdc4: regulator-dcdc4 { + regulator-name = "vdcdc4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc6: regulator-dcdc6 { + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + at24@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pixcir_ts_pins_default>; + pinctrl-1 = <&pixcir_ts_pins_sleep>; + + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + + attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; + + tlv320aic3111: tlv320aic3111@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3111"; + reg = <0x18>; + status = "okay"; + + ai31xx-micbias-vg = ; + + /* Regulators */ + HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + SPRVDD-supply = <&vbat>; /* vbat */ + SPLVDD-supply = <&vbat>; /* vbat */ + AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ + DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ + }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&audio_mstrclk>; + clock-names = "xvclk"; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe1_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&display_mux_pins>; + status = "okay"; + + sel-lcd-hdmi-hog { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SelLCDorHDMI"; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&nand_flash_x8_default>; + pinctrl-1 = <&nand_flash_x8_sleep>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; /* cs-on-ns */ + gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,we-on-ns = <0>; /* cs-on-ns */ + gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ + gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ + gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ + gpmc,access-ns = <30>; /* tCEA + 4*/ + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000C0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002C0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x1f600000>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&rtc_target { + status = "disabled"; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ecap0_pins_default>; + pinctrl-1 = <&ecap0_pins_sleep>; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi0_pins_default>; + pinctrl-1 = <&spi0_pins_sleep>; + ti,pindir-d0-out-d1-in; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; + ti,pindir-d0-out-d1-in; +}; + +&usb2_phy1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb2_phy1_default>; + pinctrl-1 = <&usb2_phy1_sleep>; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb2_phy2_default>; + pinctrl-1 = <&usb2_phy2_sleep>; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&qspi { + status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi1_pins_default>; + pinctrl-1 = <&qspi1_pins_sleep>; + + spi-max-frequency = <48000000>; + flash@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x00080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&hdq { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&vpfe1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe1_pins_default>; + pinctrl-1 = <&vpfe1_pins_sleep>; + + port { + vpfe1_ep: endpoint { + remote-endpoint = <&ov2659_1>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_pins_default>; + pinctrl-1 = <&uart0_pins_sleep>; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mux_synctimer32k_ck { + assigned-clocks = <&mux_synctimer32k_ck>; + assigned-clock-parents = <&clkdiv32k_ick>; +}; + +&cpu { + cpu0-supply = <&dcdc2>; +}; + +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi new file mode 100644 index 000000000000..9a5437b3d6a8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi @@ -0,0 +1,1003 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for AM43xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&scm_clocks { + sys_clkin_ck: clock-sys-clkin-31@40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; + clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; + ti,bit-shift = <31>; + reg = <0x0040>; + }; + + crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "crystal_freq_sel_ck"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <29>; + reg = <0x0040>; + }; + + sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sysboot_freq_sel_ck"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <22>; + reg = <0x0040>; + }; + + adc_tsc_fck: clock-adc-tsc-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan0_fck: clock-dcan0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan1_fck: clock-dcan1-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp0_fck: clock-mcasp0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp1_fck: clock-mcasp1-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex0_fck: clock-smartreflex0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex1_fck: clock-smartreflex1-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sha0_fck: clock-sha0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes0_fck: clock-aes0-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + rng_fck: clock-rng-fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm3_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <4>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm4_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <5>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm5_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <6>; + reg = <0x0664>; + }; +}; +&prcm_clocks { + clk_32768_ck: clock-clk-32768 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; + clock-frequency = <32768>; + }; + + clk_rc32k_ck: clock-clk-rc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; + clock-frequency = <32768>; + }; + + virt_19200000_ck: clock-virt-19200000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; + clock-frequency = <19200000>; + }; + + virt_24000000_ck: clock-virt-24000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; + clock-frequency = <24000000>; + }; + + virt_25000000_ck: clock-virt-25000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; + clock-frequency = <25000000>; + }; + + virt_26000000_ck: clock-virt-26000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; + clock-frequency = <26000000>; + }; + + tclkin_ck: clock-tclkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; + clock-frequency = <26000000>; + }; + + dpll_core_ck: clock@2d20 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; + }; + + dpll_core_x2_ck: clock-dpll-core-x2 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d38>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d3c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d40>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_mpu_ck: clock@2d60 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; + }; + + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d70>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mpu_periphclk: clock-mpu-periphclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; + clocks = <&dpll_mpu_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_ddr_ck: clock@2da0 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; + }; + + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2db0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_disp_ck: clock@2e20 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_disp_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; + }; + + dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; + clocks = <&dpll_disp_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2e30>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + ti,set-rate-parent; + }; + + dpll_per_ck: clock@2de0 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-j-type-clock"; + clock-output-names = "dpll_per_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; + }; + + dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; + clocks = <&dpll_per_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x2df0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + clk_24mhz: clock-clk-24mhz { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + clkdiv32k_ck: clock-clkdiv32k { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; + clocks = <&clk_24mhz>; + clock-mult = <1>; + clock-div = <732>; + }; + + clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkdiv32k_ick"; + clocks = <&clkdiv32k_ck>; + ti,bit-shift = <8>; + reg = <0x2a38>; + }; + + sysclk_div: clock-sysclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; + clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; + reg = <0x4248>; + }; + + clk_32k_tpm_ck: clock-clk-32k-tpm { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "clk_32k_tpm_ck"; + clock-frequency = <32768>; + }; + + timer1_fck: clock-timer1-fck@4200 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; + reg = <0x4200>; + }; + + timer2_fck: clock-timer2-fck@4204 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4204>; + }; + + timer3_fck: clock-timer3-fck@4208 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4208>; + }; + + timer4_fck: clock-timer4-fck@420c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x420c>; + }; + + timer5_fck: clock-timer5-fck@4210 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4210>; + }; + + timer6_fck: clock-timer6-fck@4214 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4214>; + }; + + timer7_fck: clock-timer7-fck@4218 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4218>; + }; + + wdt1_fck: clock-wdt1-fck@422c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; + reg = <0x422c>; + }; + + adc_mag_fck: adc_mag_fck@424c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; + reg = <0x424c>; + }; + + l3_gclk: clock-l3-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; + clocks = <&sysclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + + l4hs_gclk: clock-l4hs-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3s_gclk: clock-l3s-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4ls_gclk: clock-l4ls-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; + clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; + reg = <0x4238>; + }; + + dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_clksel_mac_clk"; + clocks = <&dpll_core_m5_ck>; + reg = <0x4234>; + ti,bit-shift = <2>; + ti,dividers = <2>, <5>; + }; + + clk_32k_mosc_ck: clock-clk-32k-mosc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "clk_32k_mosc_ck"; + clock-frequency = <32768>; + }; + + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; + reg = <0x4240>; + }; + + mmc_clk: clock-mmc { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; + clocks = <&sysclk_div>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x423c>; + }; + + gfx_fck_div_ck: clock-gfx-fck-div@423c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; + clocks = <&gfx_fclk_clksel_ck>; + reg = <0x423c>; + ti,max-div = <2>; + }; + + disp_clk: clock-disp@4244 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "disp_clk"; + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; + reg = <0x4244>; + ti,set-rate-parent; + }; + + dpll_extdev_ck: clock@2e60 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_extdev_ck"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; + }; + + dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_extdev_m2_ck"; + clocks = <&dpll_extdev_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x2e70>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "mux_synctimer32k_ck"; + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; + reg = <0x4230>; + }; + + timer8_fck: clock-timer8-fck@421c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer8_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x421c>; + }; + + timer9_fck: clock-timer9-fck@4220 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer9_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4220>; + }; + + timer10_fck: clock-timer10-fck@4224 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer10_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4224>; + }; + + timer11_fck: clock-timer11-fck@4228 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "timer11_fck"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4228>; + }; + + cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_50m_clkdiv"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_5m_clkdiv"; + clocks = <&cpsw_50m_clkdiv>; + clock-mult = <1>; + clock-div = <10>; + }; + + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; + clocks = <&dpll_ddr_ck>; + }; + + dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m4_ck"; + clocks = <&dpll_ddr_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2db8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_per_clkdcoldo"; + clocks = <&dpll_per_ck>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x2e14>; + ti,invert-autoidle-bit; + }; + + dll_aging_clk_div: clock-dll-aging-clk-div@4250 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dll_aging_clk_div"; + clocks = <&sys_clkin_ck>; + reg = <0x4250>; + ti,dividers = <8>, <16>, <32>; + }; + + div_core_25m_ck: clock-div-core-25m { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "div_core_25m_ck"; + clocks = <&sysclk_div>; + clock-mult = <1>; + clock-div = <8>; + }; + + func_12m_clk: clock-func-12m { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_clk"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + vtp_clk_div: clock-vtp-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "vtp_clk_div"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "usbphy_32khz_clkmux"; + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; + reg = <0x4260>; + }; + + usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy0_always_on_clk32k"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a40>; + }; + + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a48>; + }; + + clkout1_osc_div_ck: clock-clkout1-osc-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout1_osc_div_ck"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <20>; + ti,max-div = <4>; + reg = <0x4100>; + }; + + clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "clkout1_src2_mux_ck"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>; + reg = <0x4100>; + }; + + clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_pre_div_ck"; + clocks = <&clkout1_src2_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4100>; + }; + + clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_post_div_ck"; + clocks = <&clkout1_src2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4100>; + }; + + clkout1_mux_ck: clock-clkout1-mux-ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "clkout1_mux_ck"; + clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, + <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; + ti,bit-shift = <16>; + reg = <0x4100>; + }; + + clkout1_ck: clock-clkout1-ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkout1_ck"; + clocks = <&clkout1_mux_ck>; + ti,bit-shift = <23>; + reg = <0x4100>; + }; +}; + +&prcm { + wkup_cm: clock@2800 { + compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; + reg = <0x2800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2800 0x400>; + + l3s_tsc_clkctrl: clock@120 { + compatible = "ti,clkctrl"; + clock-output-names = "l3s_tsc_clkctrl"; + reg = <0x120 0x4>; + #clock-cells = <2>; + }; + + l4_wkup_aon_clkctrl: clock@228 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; + reg = <0x228 0xc>; + #clock-cells = <2>; + }; + + l4_wkup_clkctrl: clock@220 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; + reg = <0x220 0x4>, <0x328 0x44>; + #clock-cells = <2>; + }; + + }; + + mpu_cm: clock@8300 { + compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; + reg = <0x8300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8300 0x100>; + + mpu_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + gfx_l3_cm: clock@8400 { + compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; + reg = <0x8400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8400 0x100>; + + gfx_l3_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l4_rtc_cm: clock@8500 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; + reg = <0x8500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8500 0x100>; + + l4_rtc_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + per_cm: clock@8800 { + compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; + reg = <0x8800 0xc00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8800 0xc00>; + + l3_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; + reg = <0x20 0x3c>, <0x78 0x2c>; + #clock-cells = <2>; + }; + + l3s_clkctrl: clock@68 { + compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; + reg = <0x68 0xc>, <0x220 0x4c>; + #clock-cells = <2>; + }; + + pruss_ocp_clkctrl: clock@320 { + compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; + reg = <0x320 0x4>; + #clock-cells = <2>; + }; + + l4ls_clkctrl: clock@420 { + compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; + reg = <0x420 0x1a4>; + #clock-cells = <2>; + }; + + emif_clkctrl: clock@720 { + compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; + reg = <0x720 0x4>; + #clock-cells = <2>; + }; + + dss_clkctrl: clock@a20 { + compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; + reg = <0xa20 0x4>; + #clock-cells = <2>; + }; + + cpsw_125mhz_clkctrl: clock@b20 { + compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; + reg = <0xb20 0x4>; + #clock-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi b/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi new file mode 100644 index 000000000000..46c5383f0eee --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * + * Common PRUSS data for TI AM57xx platforms + */ + +&ocp { + pruss1_tm: target-module@4b226000 { + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x4b226000 0x4>, + <0x4b226004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4b200000 0x80000>; + + pruss1: pruss@0 { + compatible = "ti,am5728-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ + <&dpll_gmac_h13x2_ck>; /* icss_clk */ + }; + }; + }; + + pruss1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss1_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru1_0: pru@34000 { + compatible = "ti,am5728-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,am5728-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru1_1-fw"; + }; + + pruss1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&dpll_gmac_h13x2_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + reg = <0x32400 0x90>; + }; + }; + }; + + pruss2_tm: target-module@4b2a6000 { + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x4b2a6000 0x4>, + <0x4b2a6004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4b280000 0x80000>; + + pruss2: pruss@0 { + compatible = "ti,am5728-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss2_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss2_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss2_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ + <&dpll_gmac_h13x2_ck>; /* icss_clk */ + }; + }; + }; + + pruss2_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss2_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru2_0: pru@34000 { + compatible = "ti,am5728-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru2_0-fw"; + }; + + pru2_1: pru@38000 { + compatible = "ti,am5728-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru2_1-fw"; + }; + + pruss2_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&dpll_gmac_h13x2_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + reg = <0x32400 0x90>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am5718.dtsi b/arch/arm/boot/dts/ti/omap/am5718.dtsi new file mode 100644 index 000000000000..6d7530a48c73 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am5718.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "dra72x.dtsi" +#include "am57-pruss.dtsi" + +/ { + compatible = "ti,am5718", "ti,dra7"; +}; + +/* + * These modules are not present on AM5718 + * + * ATL + * VCP1, VCP2 + * MLB + * ISS + * USB3 + */ + +&usb3_tm { + status = "disabled"; +}; + +&atl_tm { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso b/arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso new file mode 100644 index 000000000000..c051ee6c1130 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: edt-ft5506@38 { + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am571x-idk.dts b/arch/arm/boot/dts/ti/omap/am571x-idk.dts new file mode 100644 index 000000000000..48425020281a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am571x-idk.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am5718.dtsi" +#include +#include +#include "dra7-mmc-iodelay.dtsi" +#include "dra72x-mmc-iodelay.dtsi" +#include "am57xx-idk-common.dtsi" +#include "dra7-ipu-dsp-common.dtsi" + +/ { + model = "TI AM5718 IDK"; + compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + usr1-led { + label = "status1:red:usr"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + usr2-led { + label = "status1:green:usr"; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + idk-leds { + status = "disabled"; + compatible = "gpio-leds"; + red0-led { + label = "idk:red0"; + gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green0-led { + label = "idk:green0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue0-led { + label = "idk:blue0"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red1-led { + label = "idk:red1"; + gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green1-led { + label = "idk:green1"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue1-led { + label = "idk:blue1"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red2-led { + label = "idk:red2"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green2-led { + label = "idk:green2"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue2-led { + label = "idk:blue2"; + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red3-led { + label = "idk:red3"; + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green3-led { + label = "idk:green3"; + gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue3-led { + label = "idk:blue3"; + gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&extcon_usb2 { + id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; +}; + +&sn65hvs882 { + load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&pcie1_rc { + status = "okay"; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; +}; + +&mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; + pinctrl-1 = <&mmc1_pins_hs>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +}; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am5728.dtsi b/arch/arm/boot/dts/ti/omap/am5728.dtsi new file mode 100644 index 000000000000..5e0bdf16d485 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am5728.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "dra74x.dtsi" +#include "am57-pruss.dtsi" + +/ { + compatible = "ti,am5728", "ti,dra7"; +}; + +/* + * These modules are not present on AM5728 + * + * EVE1, EVE2 + * ATL + * VCP1, VCP2 + * MLB + * ISS + * USB3, USB4 + */ + +&usb3_tm { + status = "disabled"; +}; + +&usb4_tm { + status = "disabled"; +}; + +&atl_tm { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts new file mode 100644 index 000000000000..149cfafb90bf --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -0,0 +1,704 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "dra74x.dtsi" +#include "am57xx-commercial-grade.dtsi" +#include "dra74x-mmc-iodelay.dtsi" +#include "dra74-ipu-dsp-common.dtsi" +#include +#include +#include + +/ { + model = "BeagleBoard.org BeagleBone AI"; + compatible = "beagle,am5729-beagleboneai", "ti,am5728", + "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + display0 = &hdmi_conn; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + + }; + + vdd_adc: gpioregulator-vdd_adc { + compatible = "regulator-gpio"; + regulator-name = "vdd_adc"; + vin-supply = <&vdd_5v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + states = <1800000 0 + 3300000 1>; + }; + + vdd_5v: fixedregulator-vdd_5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&vdd_ddr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr4"; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + default-state = "off"; + }; + }; + + hdmi_conn: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_encoder_out>; + }; + }; + }; + + hdmi_enc: encoder@0 { + /* "ti,tpd12s016" software compatible with "ti,tpd12s015" + * no need for individual driver + */ + compatible = "ti,tpd12s015"; + gpios = <0>, + <0>, + <&gpio7 12 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + hdmi_encoder_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <0x1>; + + hdmi_encoder_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + emmc_pwrseq: emmc_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + }; + + brcmf_pwrseq: brcmf_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ + <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + ti,enable-id-detection; + id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + ti,palmas-override-powerhold; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + smps12-in-supply = <&vdd_5v>; + smps3-in-supply = <&vdd_5v>; + smps45-in-supply = <&vdd_5v>; + smps6-in-supply = <&vdd_5v>; + smps7-in-supply = <&vdd_5v>; + mps3-in-supply = <&vdd_5v>; + smps8-in-supply = <&vdd_5v>; + smps9-in-supply = <&vdd_5v>; + ldo1-in-supply = <&vdd_5v>; + ldo2-in-supply = <&vdd_5v>; + ldo3-in-supply = <&vdd_5v>; + ldo4-in-supply = <&vdd_5v>; + ldo9-in-supply = <&vdd_5v>; + ldoln-in-supply = <&vdd_5v>; + ldousb-in-supply = <&vdd_5v>; + ldortc-in-supply = <&vdd_5v>; + + regulators { + vdd_mpu: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ddr: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_dspeve: smps45 { + /* VDD_DSPEVE on AM572 */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_gpu: smps6 { + /* VDD_GPU */ + regulator-name = "smps6"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: smps7 { + /* VDD_CORE */ + regulator-name = "smps7"; + regulator-min-microvolt = < 850000>; /*** 1.15V */ + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_iva: smps8 { + /* VDD_IVAHD */ /*** 1.06V */ + regulator-name = "smps8"; + }; + + vdd_3v3: smps9 { + /* VDD_3V3 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_sd: ldo1 { + /* VDDSHV8 - VSDMMC */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_1v8: ldo2 { + /* VDDSH18V */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo3: ldo3 { + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo4: ldo4 { + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + vdd_rtc: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = < 840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_pll: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC */ + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio2>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */ + adc0: iio-device@0 { + #io-channel-cells = <1>; + iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>; + iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38", + "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35"; + }; + }; + + stmpe_touchscreen { + status = "disabled"; + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + + stmpe_gpio { + compatible = "st,stmpe-gpio"; + }; + + stmpe_pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&cpu0 { + vdd-supply = <&vdd_mpu>; + voltage-tolerance = <1>; +}; + +&uart1 { + status = "okay"; +}; + +&davinci_mdio_sw { + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@4 { + reg = <4>; + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&ocp { + pruss1_shmem: pruss_shmem@4b200000 { + status = "okay"; + compatible = "ti,pruss-shmem"; + reg = <0x4b200000 0x020000>; + }; + + pruss2_shmem: pruss_shmem@4b280000 { + status = "okay"; + compatible = "ti,pruss-shmem"; + reg = <0x4b280000 0x020000>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_sd>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vdd_1v8>; + vqmmc-supply = <&vdd_1v8>; + bus-width = <8>; + ti,non-removable; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + + ti,needs-special-reset; + dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; + dma-names = "tx", "rx"; + +}; + +&mmc4 { + /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ + /* HS: High speed up to 50 MHz (3.3 V signaling). */ + /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ + /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ + /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ + /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ + /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ + status = "okay"; + + ti,needs-special-reset; + vmmc-supply = <&vdd_3v3>; + cap-power-off-card; + keep-power-in-suspend; + bus-width = <4>; + ti,non-removable; + non-removable; + no-1-8-v; + max-frequency = <24000000>; + + #address-cells = <1>; + #size-cells = <0>; + mmc-pwrseq = <&brcmf_pwrseq>; + + brcmf: wifi@1 { + status = "okay"; + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + brcm,sd-head-align = <4>; + brcm,sd_head_align = <4>; + brcm,sd_sgentry_align = <512>; + + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + status = "okay"; + dr_mode = "otg"; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&usb2 { + status = "okay"; + dr_mode = "host"; +}; + +&dss { + status = "okay"; + vdda_video-supply = <&vdd_1v8_pll>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdd_1v8_phy_ldo4>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_encoder_in>; + }; + }; +}; + +&bandgap { + status = "okay"; +}; + +&cpu_alert0 { + temperature = <55000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +/* bluetooth */ +&uart6 { + status = "okay"; +}; + +/* cape header stuff */ +&i2c4 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cpu0_opp_table { + opp_slow-500000000 { + opp-shared; + }; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi new file mode 100644 index 000000000000..1d66278c3a72 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include "am57xx-idk-common.dtsi" +#include "dra74-ipu-dsp-common.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + status-leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + cpu1-led { + label = "status1:red:cpu1"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu1"; + }; + + usr1-led { + label = "status1:green:usr"; + gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + idk-leds { + status = "disabled"; + compatible = "gpio-leds"; + red0-led { + label = "idk:red0"; + gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green0-led { + label = "idk:green0"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue0-led { + label = "idk:blue0"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red1-led { + label = "idk:red1"; + gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green1-led { + label = "idk:green1"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue1-led { + label = "idk:blue1"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red2-led { + label = "idk:red2"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green2-led { + label = "idk:green2"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue2-led { + label = "idk:blue2"; + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red3-led { + label = "idk:red3"; + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green3-led { + label = "idk:green3"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue3-led { + label = "idk:blue3"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&extcon_usb2 { + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +}; + +&sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie1_rc { + status = "okay"; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso b/arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso new file mode 100644 index 000000000000..573e932b1239 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: edt-ft5506@38 { + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am572x-idk.dts b/arch/arm/boot/dts/ti/omap/am572x-idk.dts new file mode 100644 index 000000000000..94a738cb0a4d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am572x-idk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "am5728.dtsi" +#include "dra7-mmc-iodelay.dtsi" +#include "dra74x-mmc-iodelay.dtsi" +#include "am572x-idk-common.dtsi" + +/ { + model = "TI AM5728 IDK"; + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7"; +}; + +&mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; + pinctrl-1 = <&mmc1_pins_hs>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20>; +}; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am5748.dtsi b/arch/arm/boot/dts/ti/omap/am5748.dtsi new file mode 100644 index 000000000000..a1f029e9d1f3 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am5748.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "dra74x-p.dtsi" +#include "am57-pruss.dtsi" + +/ { + compatible = "ti,am5748", "ti,dra762", "ti,dra7"; +}; + +/* + * These modules are not present on AM5748 + * + * EVE1, EVE2 + * ATL + * VCP1, VCP2 + * MLB + * ISS + * USB3, USB4 + */ + +&usb3_tm { + status = "disabled"; +}; + +&usb4_tm { + status = "disabled"; +}; + +&atl_tm { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am574x-idk.dts b/arch/arm/boot/dts/ti/omap/am574x-idk.dts new file mode 100644 index 000000000000..47b9174d2353 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am574x-idk.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + + +/dts-v1/; + +#include "am5748.dtsi" +#include "dra7-mmc-iodelay.dtsi" +#include "dra76x-mmc-iodelay.dtsi" +#include "am572x-idk-common.dtsi" + +/ { + model = "TI AM5748 IDK"; + compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; +}; + +&qspi { + spi-max-frequency = <96000000>; + flash@0 { + spi-max-frequency = <96000000>; + }; +}; + +&mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; + pinctrl-1 = <&mmc1_pins_hs>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_default>; + pinctrl-2 = <&mmc2_pins_default>; +}; + +&emif1 { + status = "okay"; +}; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi new file mode 100644 index 000000000000..994e69ab38d7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi @@ -0,0 +1,647 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "am5728.dtsi" +#include "am57xx-commercial-grade.dtsi" +#include "dra74x-mmc-iodelay.dtsi" +#include "dra74-ipu-dsp-common.dtsi" +#include +#include + +/ { + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + rtc2 = &rtc; + display0 = &hdmi0; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + main_12v0: fixedregulator-main_12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "main_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + evm_5v0: fixedregulator-evm_5v0 { + /* Output of TPS54531D */ + compatible = "regulator-fixed"; + regulator-name = "evm_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&main_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd_fixed"; + vin-supply = <&vdd_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + default-state = "off"; + }; + }; + + gpio_fan: gpio_fan { + /* Based on 5v 500mA AFB02505HHB */ + compatible = "gpio-fan"; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, + <13000 1>; + #cooling-cells = <2>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "BeagleBoard-X15"; + simple-audio-card,widgets = + "Line", "Line Out", + "Line", "Line In"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC2L", "Line In", + "MIC2R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp3>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3104>; + clocks = <&clkout2_clk>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + ti,palmas-override-powerhold; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD / VDDSHV8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHYA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_1V8_PHYB */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + extcon_usb2: tps659038_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + tlv320aic3104: tlv320aic3104@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3104"; + reg = <0x18>; + assigned-clocks = <&clkoutmux2_clk_mux>; + assigned-clock-parents = <&sys_clk2_dclk_div>; + + status = "okay"; + adc-settle-ms = <40>; + + AVDD-supply = <&vdd_3v3>; + IOVDD-supply = <&vdd_3v3>; + DRVDD-supply = <&vdd_3v3>; + DVDD-supply = <&aic_dvdd>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, + <&dra7_pmx_core 0x424>; + interrupt-names = "irq", "wakeup"; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7_target { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + vdd-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3f8>; +}; + +&davinci_mdio_sw { + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + }; +}; + +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <2>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + no-1-8-v; +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + bus-width = <8>; + non-removable; + no-1-8-v; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + /* + * Stand alone usage is peripheral only. + * However, with some resistor modifications + * this port can be used via expansion connectors + * as "host" or "dual-role". If so, provide + * the necessary dr_mode override in the expansion + * board's DT. + */ + dr_mode = "peripheral"; +}; + +&cpu_trips { + cpu_alert1: cpu_alert1 { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; +}; + +&cpu_cooling_maps { + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&thermal_zones { + board_thermal: board_thermal { + polling-delay-passive = <1250>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tmp102 0>; + + board_trips: trips { + board_alert0: board_alert { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + board_crit: board_crit { + temperature = <105000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + board_cooling_maps: cooling-maps { + map0 { + trip = <&board_alert0>; + cooling-device = + <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dss { + status = "okay"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&ldo4_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&pcie1_rc { + status = "okay"; + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + assigned-clock-parents = <&sys_clkin2>; + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts new file mode 100644 index 000000000000..83e174e053c7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "am57xx-beagle-x15-common.dtsi" + +/ { + model = "TI AM5728 BeagleBoard-X15 rev B1"; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +}; + +&mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&ldo1_reg>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; +}; + +/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ +&phy1 { + max-speed = <100>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts new file mode 100644 index 000000000000..656dd84460d2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "am57xx-beagle-x15-common.dtsi" + +/ { + model = "TI AM5728 BeagleBoard-X15 rev C"; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +}; + +&mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&ldo1_reg>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts new file mode 100644 index 000000000000..0a8b16505ed9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "am57xx-beagle-x15-common.dtsi" + +/ { + /* NOTE: This describes the "original" pre-production A2 revision */ + model = "TI AM5728 BeagleBoard-X15"; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +}; + +&mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + + vmmc-supply = <&ldo1_reg>; + no-1-8-v; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_3_3v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; +}; + +/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ +&phy1 { + max-speed = <100>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts new file mode 100644 index 000000000000..4774aa05f101 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts @@ -0,0 +1,628 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Support for CompuLab CL-SOM-AM57x System-on-Module + * + * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Author: Dmitry Lifshitz + */ + +/dts-v1/; + +#include +#include +#include "am5728.dtsi" + +/ { + model = "CompuLab CL-SOM-AM57x"; + compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led0 { + label = "cl-som-am57x:green"; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ads7846reg: fixedregulator-ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "CL-SOM-AM57x-Sound-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack", + "Line", "Line Jack"; + simple-audio-card,routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line Jack", + "MICIN", "Mic Bias", + "Mic Bias", "Microphone Jack"; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8731>; + system-clock-frequency = <12000000>; + }; + }; +}; + +&dra7_pmx_core { + leds_pins_default: leds-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ + >; + }; + + i2c1_pins_default: i2c1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ + DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ + >; + }; + + i2c3_pins_default: i2c3-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ + DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ + >; + }; + + i2c4_pins_default: i2c4-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ + DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ + >; + }; + + tps659038_pins_default: tps659038-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ + >; + }; + + mmc2_pins_default: mmc2-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + qspi1_pins: qspi1-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ + DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ + DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */ + DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ + DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ + DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ + >; + }; + + cpsw_pins_default: cpsw-default-pins { + pinctrl-single,pins = < + /* Slave at addr 0x0 */ + DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ + DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */ + DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */ + DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */ + DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */ + DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */ + DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */ + DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */ + DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */ + DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */ + DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */ + DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */ + + /* Slave at addr 0x1 */ + DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */ + DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + }; + + cpsw_pins_sleep: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Slave 1 */ + DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) + + /* Slave 2 */ + DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) + >; + }; + + davinci_mdio_pins_default: davinci-mdio-default-pins { + pinctrl-single,pins = < + /* MDIO */ + DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ + DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */ + >; + }; + + davinci_mdio_pins_sleep: davinci-mdio-sleep-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) + >; + }; + + ads7846_pins: ads7846-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ + >; + }; + + mcasp3_pins_default: mcasp3-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ + DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ + DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ + DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ + >; + }; + + mcasp3_pins_sleep: mcasp3-sleep-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_default>; + clock-frequency = <400000>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_default>; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tps659038_pins_default>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU */ + regulator-name = "smps6"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDD_CORE */ + regulator-name = "smps7"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_IVA */ + regulator-name = "smps8"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* PMIC_3V3 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + + ldo1_reg: ldo1 { + /* VDD_SD / VDDSHV8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDD_1V8 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* regen1 not used */ + }; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + rtc0: rtc@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; + + eeprom_module: atmel@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + wm8731: wm8731@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8731"; + reg = <0x1a>; + status = "okay"; + }; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&sata { + status = "okay"; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { + status = "okay"; + }; +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_pins>; + + spi-max-frequency = <48000000>; + + spi_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80", "jedec,spi-nor"; + reg = <0>; /* CS0 */ + spi-max-frequency = <48000000>; + + partition@0 { + label = "uboot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "uboot environment"; + reg = <0xc0000 0x40000>; + }; + + partition@100000 { + label = "reserved"; + reg = <0x100000 0x0>; + }; + }; + + /* touch controller */ + touchscreen@1 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <1>; /* CS1 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio1>; + interrupts = <31 0>; + pendown-gpio = <&gpio1 31 0>; + + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + ti,debounce-max = /bits/ 16 <30>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <1>; + + wakeup-source; + }; +}; + +&mac_sw { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_pins_default>; + pinctrl-1 = <&cpsw_pins_sleep>; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-txid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-txid"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_pins_default>; + pinctrl-1 = <&davinci_mdio_pins_sleep>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&usb2 { + dr_mode = "host"; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp3_pins_default>; + pinctrl-1 = <&mcasp3_pins_sleep>; + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; +}; + +&gpio3_target { + ti,no-reset-on-init; +}; + +&gpio2_target { + status = "okay"; + ti,no-reset-on-init; +}; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi new file mode 100644 index 000000000000..3eed6e09c884 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +&cpu_alert0 { + temperature = <80000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <90000>; /* milliCelsius */ +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-evm.dtso b/arch/arm/boot/dts/ti/omap/am57xx-evm.dtso new file mode 100644 index 000000000000..12385a31061e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-evm.dtso @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT overlay for AM57xx GP EVM boards + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + model = "TI AM5728 EVM"; + + aliases { + display0 = "/display"; + display1 = "/connector"; // Fixme: &lcd0 and &hdmi0 could be + // resolved here correcly based on + // information in the base dtb symbol + // table with a fix in dtc + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user1 { + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + label = "USER1"; + linux,code = ; + }; + + button-user2 { + gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + label = "USER2"; + linux,code = ; + }; + + button-user3 { + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + label = "USER3"; + linux,code = ; + }; + + button-user4 { + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + label = "USER4"; + linux,code = ; + }; + + button-user5 { + gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + label = "USER5"; + linux,code = ; + }; + }; + + lcd0: display { + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + backlight = <&lcd_bl>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + label = "lcd"; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 243 245 247 249 251 252 253 255>; + default-brightness-level = <8>; + pwms = <&ehrpwm1 0 50000 0>; + }; +}; + +&ehrpwm1 { + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + attb-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reg = <0x5c>; + reset-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&dss { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + data-lines = <24>; + remote-endpoint = <&lcd_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi new file mode 100644 index 000000000000..43e3623f079c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "am57xx-industrial-grade.dtsi" + +/ { + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + display0 = &hdmi0; + }; + + chosen { + stdout-path = &uart3; + }; + + vmain: fixedregulator-vmain { + compatible = "regulator-fixed"; + regulator-name = "VMAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + v3_3d: fixedregulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "V3_3D"; + vin-supply = <&smps9_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + v1_2d: fixedregulator-v1_2d { + compatible = "regulator-fixed"; + regulator-name = "V1_2D"; + vin-supply = <&vmain>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&v3_3d>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + hdmi0: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder@0 { + compatible = "ti,tpd12s016", "ti,tpd12s015"; + + gpios = <0>, /* optional CT_CP_HPD */ + <0>, /* optional LS_OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + src_clk_x1: src_clk_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; +}; + +&dra7_pmx_core { + dcan1_pins_default: dcan1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1-sleep-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH + &dra7_pmx_core 0x418>; + #interrupt-cells = <2>; + interrupt-controller; + ti,system-power-controller; + ti,palmas-override-powerhold; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + smps12-in-supply = <&vmain>; + smps3-in-supply = <&vmain>; + smps45-in-supply = <&vmain>; + smps6-in-supply = <&vmain>; + smps7-in-supply = <&vmain>; + smps8-in-supply = <&vmain>; + smps9-in-supply = <&vmain>; + ldo1-in-supply = <&vmain>; + ldo2-in-supply = <&vmain>; + ldo3-in-supply = <&vmain>; + ldo4-in-supply = <&vmain>; + ldo9-in-supply = <&vmain>; + ldoln-in-supply = <&vmain>; + ldousb-in-supply = <&vmain>; + ldortc-in-supply = <&vmain>; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE on AM572 */ + /* VDD_IVA + VDD_DSP on AM571 */ + regulator-name = "smps45"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDD_CORE */ + regulator-name = "smps7"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* 5728 - VDD_IVAHD */ + /* 5718 - N.C. test point */ + regulator-name = "smps8"; + }; + + smps9_reg: smps9 { + /* VDD_3_3D */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + /* VDDSHV8 - VSDMMC */ + /* NOTE: on rev 1.3a, data supply */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDDSH18V */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC */ + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + extcon_usb2: tps659038_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + /* ID & VBUS GPIOs provided in board dts */ + }; + }; + + tpic2810: tpic2810@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; + + dsi_bridge: tc358778@e { + compatible = "toshiba,tc358778", "toshiba,tc358768"; + reg = <0xe>; + status = "disabled"; + + clocks = <&src_clk_x1>; + clock-names = "refclk"; + + vddc-supply = <&v1_2d>; + vddmipi-supply = <&v1_2d>; + vddio-supply = <&v3_3d>; + + dsi_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rgb_in: endpoint { + remote-endpoint = <&dpi_out>; + data-lines = <24>; + }; + }; + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH + &dra7_pmx_core 0x248>; +}; + +&rtc { + status = "okay"; + ext-clk-src; +}; + +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + extcon = <&extcon_usb2>; + dr_mode = "otg"; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&v3_3d>; + vqmmc-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + no-1-8-v; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&v3_3d>; + vqmmc-supply = <&v3_3d>; + bus-width = <8>; + non-removable; + max-frequency = <96000000>; + no-1-8-v; +}; + +&dcan1 { + status = "okay"; + pinctrl-names = "default", "sleep", "active"; + pinctrl-0 = <&dcan1_pins_sleep>; + pinctrl-1 = <&dcan1_pins_sleep>; + pinctrl-2 = <&dcan1_pins_default>; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + flash@0 { + compatible = "s25fl256s1", "jedec,spi-nor"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@2 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@3 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@5 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@6 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&cpu0 { + vdd-supply = <&smps12_reg>; +}; + +&hdmi { + status = "okay"; + + vdda-supply = <&ldo4_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&dss { + status = "okay"; + + vdda_video-supply = <&ldoln_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&rgb_in>; + data-lines = <24>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso new file mode 100644 index 000000000000..25d74e9f3c9e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + aliases { + display0 = "/display"; + display1 = "/connector"; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&dsi_bridge { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + lcd: display { + compatible = "osddisplays,osd101t2045-53ts"; + reg = <0>; + + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&lcd_in>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso new file mode 100644 index 000000000000..8cea7ba32487 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + aliases { + display0 = "/display"; + display1 = "/connector"; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&dsi_bridge { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + lcd: display { + compatible = "osddisplays,osd101t2587-53ts"; + reg = <0>; + + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&lcd_in>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi new file mode 100644 index 000000000000..422f953fc8d8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +&cpu_alert0 { + temperature = <90000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <105000>; /* milliCelsius */ +}; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts new file mode 100644 index 000000000000..363115afb0a4 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Support for CompuLab SBC-AM57x single board computer + * + * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Author: Dmitry Lifshitz + */ + +#include "am57xx-cl-som-am57x.dts" +#include "compulab-sb-som.dtsi" + +/ { + model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x"; + compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + display0 = &lcd0; + display1 = &hdmi; + }; +}; + +&dra7_pmx_core { + uart3_pins_default: uart3-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ + DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ + >; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */ + DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */ + >; + }; + + usb1_pins: usb1-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + i2c5_pins_default: i2c5-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ + DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ + >; + }; + + lcd_pins_default: lcd-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ + >; + }; + + hdmi_pins: hdmi-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ + DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ + >; + }; + + hdmi_conn_pins: hdmi-conn-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ + >; + }; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3f8>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_default>; + clock-frequency = <400000>; + + eeprom_base: atmel@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; + + pca9555: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dss { + status = "okay"; + + vdda_video-supply = <&ldoln_reg>; + + port { + dpi_lcd_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&lcd0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins_default>; + + enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH + &gpio4 0 GPIO_ACTIVE_HIGH>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + data-lines = <24>; + }; + }; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&ldo4_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + lanes = <1 0 3 2 5 4 7 6>; + }; + }; +}; + +&hdmi_conn { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_conn_pins>; + + hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi b/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi new file mode 100644 index 000000000000..f5e6216718d8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + */ + +/ { + model = "CompuLab SB-SOM"; + compatible = "compulab,sb-som"; + + vsb_3v3: fixedregulator-v3_3 { + compatible = "regulator-fixed"; + regulator-name = "vsb_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + enable-active-high; + }; + + lcd0: display { + compatible = "startek,startek-kd050c", "panel-dpi"; + label = "lcd"; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <43>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + hdmi_conn: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm3725.dtsi b/arch/arm/boot/dts/ti/omap/dm3725.dtsi new file mode 100644 index 000000000000..d24e906a14b1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm3725.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 André Hentschel + */ + +#include "omap36xx.dtsi" + +&sgx_module { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm8148-evm.dts b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts new file mode 100644 index 000000000000..ae8d9fa09d16 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "dm814x.dtsi" +#include + +/ { + model = "DM8148 EVM"; + compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + /* MIC94060YC6 controlled by SD1_POW pin */ + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; +}; + +&cpsw_emac1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +&davinci_mdio { + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f2g16aadwp"; + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "bch8"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x780000 0xf880000>; + }; + }; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +}; + +&mmc3 { + status = "disabled"; +}; + +&pincntl { + sd1_pins: sd1-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ + DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ + DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ + DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ + DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ + DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ + DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ + DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ + >; + }; + + usb0_pins: usb0-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: usb1-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ + >; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm8148-t410.dts b/arch/arm/boot/dts/ti/omap/dm8148-t410.dts new file mode 100644 index 000000000000..f3e2ecf6d723 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm8148-t410.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "dm814x.dtsi" + +/ { + model = "HP t410 Smart Zero Client"; + compatible = "hp,t410", "ti,dm8148", "ti,dm814"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + /* gpio9 seems to control USB VBUS regulator and/or hub power */ + usb_power: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "usb_power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; +}; + +&cpsw_emac1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +&davinci_mdio { + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&sd2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ + &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ + dma-names = "tx", "rx"; + non-removable; +}; + +&pincntl { + sd2_pins: sd2-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ + DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ + DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[5] */ + DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[4] */ + DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[3] */ + DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[2] */ + DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[1] */ + DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[0] */ + DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1) /* SD2_CLK */ + DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2) /* SD2_CMD */ + DM814X_IOPAD(0x0920, PIN_INPUT | 0x40) /* SD2_SDCD */ + >; + }; + + usb0_pins: usb0-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: usb1-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ + >; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi new file mode 100644 index 000000000000..f7939f43413b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&pllss { + /* + * See TRM "2.6.10 Connected outputso DPLLS" and + * "2.6.11 Connected Outputs of DPLLJ". Only clkout is + * connected except for hdmi and usb. + */ + adpll_mpu_ck: adpll@40 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-s-clock"; + reg = <0x40 0x40>; + clocks = <&devosc_ck &devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow", "clkinphif"; + clock-output-names = "481c5040.adpll.dcoclkldo", + "481c5040.adpll.clkout", + "481c5040.adpll.clkoutx2", + "481c5040.adpll.clkouthif"; + }; + + adpll_dsp_ck: adpll@80 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x80 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5080.adpll.dcoclkldo", + "481c5080.adpll.clkout", + "481c5080.adpll.clkoutldo"; + }; + + adpll_sgx_ck: adpll@b0 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0xb0 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c50b0.adpll.dcoclkldo", + "481c50b0.adpll.clkout", + "481c50b0.adpll.clkoutldo"; + }; + + adpll_hdvic_ck: adpll@e0 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0xe0 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c50e0.adpll.dcoclkldo", + "481c50e0.adpll.clkout", + "481c50e0.adpll.clkoutldo"; + }; + + adpll_l3_ck: adpll@110 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x110 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5110.adpll.dcoclkldo", + "481c5110.adpll.clkout", + "481c5110.adpll.clkoutldo"; + }; + + adpll_isp_ck: adpll@140 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x140 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5140.adpll.dcoclkldo", + "481c5140.adpll.clkout", + "481c5140.adpll.clkoutldo"; + }; + + adpll_dss_ck: adpll@170 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x170 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5170.adpll.dcoclkldo", + "481c5170.adpll.clkout", + "481c5170.adpll.clkoutldo"; + }; + + adpll_video0_ck: adpll@1a0 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x1a0 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c51a0.adpll.dcoclkldo", + "481c51a0.adpll.clkout", + "481c51a0.adpll.clkoutldo"; + }; + + adpll_video1_ck: adpll@1d0 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x1d0 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c51d0.adpll.dcoclkldo", + "481c51d0.adpll.clkout", + "481c51d0.adpll.clkoutldo"; + }; + + adpll_hdmi_ck: adpll@200 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x200 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5200.adpll.dcoclkldo", + "481c5200.adpll.clkout", + "481c5200.adpll.clkoutldo"; + }; + + adpll_audio_ck: adpll@230 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x230 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5230.adpll.dcoclkldo", + "481c5230.adpll.clkout", + "481c5230.adpll.clkoutldo"; + }; + + adpll_usb_ck: adpll@260 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x260 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5260.adpll.dcoclkldo", + "481c5260.adpll.clkout", + "481c5260.adpll.clkoutldo"; + }; + + adpll_ddr_ck: adpll@290 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x290 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-output-names = "481c5290.adpll.dcoclkldo", + "481c5290.adpll.clkout", + "481c5290.adpll.clkoutldo"; + }; +}; + +&pllss_clocks { + timer1_fck: timer1_fck@2e0 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <3>; + reg = <0x2e0>; + }; + + timer2_fck: timer2_fck@2e0 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <6>; + reg = <0x2e0>; + }; + + /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */ + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&adpll_video0_ck 1 + &adpll_video1_ck 1 + &adpll_audio_ck 1>; + ti,bit-shift = <1>; + reg = <0x2e8>; + }; + + /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */ + cpsw_125mhz_gclk: cpsw_125mhz_gclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + sysclk18_ck: sysclk18_ck@2f0 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&rtcosc_ck>, <&rtcdivider_ck>; + ti,bit-shift = <0>; + reg = <0x02f0>; + }; +}; + +&scm_clocks { + devosc_ck: devosc_ck@40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; + ti,bit-shift = <21>; + reg = <0x0040>; + }; + + /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ + auxosc_ck: auxosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <22572900>; + }; + + /* Optional 32768Hz crystal or clock on RTCOSC pins */ + rtcosc_ck: rtcosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + /* Optional external clock on TCLKIN pin, set rate in baord dts file */ + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + virt_20000000_ck: virt_20000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + mpu_ck: mpu_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000000>; + }; +}; + +&prcm_clocks { + osc_src_ck: osc_src_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&devosc_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mpu_clksrc_ck: mpu_clksrc_ck@40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&devosc_ck>, <&rtcdivider_ck>; + ti,bit-shift = <0>; + reg = <0x0040>; + }; + + /* Fixed divider clock 0.0016384 * devosc */ + rtcdivider_ck: rtcdivider_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&devosc_ck>; + clock-mult = <128>; + clock-div = <78125>; + }; + + /* L4_HS 220 MHz*/ + sysclk4_ck: sysclk4_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&adpll_l3_ck 1>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + }; + + /* L4_FWCFG */ + sysclk5_ck: sysclk5_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&adpll_l3_ck 1>; + ti,clock-mult = <1>; + ti,clock-div = <2>; + }; + + /* L4_LS 110 MHz */ + sysclk6_ck: sysclk6_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&adpll_l3_ck 1>; + ti,clock-mult = <1>; + ti,clock-div = <2>; + }; + + sysclk8_ck: sysclk8_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&adpll_usb_ck 1>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + }; + + sysclk10_ck: sysclk10_ck { + compatible = "ti,divider-clock"; + reg = <0x324>; + ti,max-div = <7>; + #clock-cells = <0>; + clocks = <&adpll_usb_ck 1>; + }; + + aud_clkin0_ck: aud_clkin0_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + aud_clkin1_ck: aud_clkin1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + aud_clkin2_ck: aud_clkin2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; +}; + +&prcm { + default_cm: default_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + default_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x5c>; + #clock-cells = <2>; + }; + }; + + alwon_cm: alwon_cm@1400 { + compatible = "ti,omap4-cm"; + reg = <0x1400 0x300>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x300>; + + alwon_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x228>; + #clock-cells = <2>; + }; + }; + + alwon_ethernet_cm: alwon_ethernet_cm@15d4 { + compatible = "ti,omap4-cm"; + reg = <0x15d4 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15d4 0x4>; + + alwon_ethernet_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0 0x4>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm814x.dtsi b/arch/arm/boot/dts/ti/omap/dm814x.dtsi new file mode 100644 index 000000000000..a8cd724ce4bc --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm814x.dtsi @@ -0,0 +1,788 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +/ { + compatible = "ti,dm814"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; + usb0 = &usb0; + usb1 = &usb1; + phy0 = &usb0_phy; + phy1 = &usb1_phy; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + usb: usb@47400000 { + compatible = "ti,am33xx-usb"; + reg = <0x47400000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + ti,hwmods = "usb_otg_hs"; + + usb0_phy: usb-phy@47401300 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401300 0x100>; + reg-names = "phy"; + ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; + }; + + usb0: usb@47401000 { + compatible = "ti,musb-am33xx"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; + reg-names = "mc", "control"; + + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb0_phy>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1: usb@47401800 { + compatible = "ti,musb-am33xx"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb1_phy>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@47402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <30>; + dma-channels = <30>; + #dma-requests = <256>; + dma-requests = <256>; + }; + }; + + /* + * See TRM "Table 1-317. L4LS Instance Summary" for hints. + * It shows the module target agent registers though, so the + * actual device is typically 0x1000 before the target agent + * except in cases where the module is larger than 0x1000. + */ + l4ls: l4ls@48000000 { + compatible = "ti,dm814-l4ls", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x2000000>; + + i2c1: i2c@28000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + reg = <0x28000 0x1000>; + interrupts = <70>; + }; + + elm: elm@80000 { + compatible = "ti,814-elm"; + ti,hwmods = "elm"; + reg = <0x80000 0x2000>; + interrupts = <4>; + }; + + gpio1: gpio@32000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + reg = <0x32000 0x2000>; + interrupts = <96>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@4c000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + ti,gpio-always-on; + reg = <0x4c000 0x2000>; + interrupts = <98>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@1ac000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + ti,gpio-always-on; + reg = <0x1ac000 0x2000>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@1ae000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + ti,gpio-always-on; + reg = <0x1ae000 0x2000>; + interrupts = <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c2: i2c@2a000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + reg = <0x2a000 0x1000>; + interrupts = <71>; + }; + + mcspi1: spi@30000 { + compatible = "ti,omap4-mcspi"; + reg = <0x30000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <65>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi1"; + dmas = <&edma 16 0 &edma 17 0 + &edma 18 0 &edma 19 0 + &edma 20 0 &edma 21 0 + &edma 22 0 &edma 23 0>; + + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mcspi2: spi@1a0000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <125>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi2"; + dmas = <&edma 42 0 &edma 43 0 + &edma 44 0 &edma 45 0>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + /* Board must configure dmas with edma_xbar for EDMA */ + mcspi3: spi@1a2000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a2000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <126>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi3"; + }; + + mcspi4: spi@1a4000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <127>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi4"; + }; + + timer1_target: target-module@2e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&timer1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; + }; + + uart1: serial@20000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart1"; + reg = <0x20000 0x2000>; + clock-frequency = <48000000>; + interrupts = <72>; + dmas = <&edma 26 0 &edma 27 0>; + dma-names = "tx", "rx"; + }; + + uart2: serial@22000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart2"; + reg = <0x22000 0x2000>; + clock-frequency = <48000000>; + interrupts = <73>; + dmas = <&edma 28 0 &edma 29 0>; + dma-names = "tx", "rx"; + }; + + uart3: serial@24000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart3"; + reg = <0x24000 0x2000>; + clock-frequency = <48000000>; + interrupts = <74>; + dmas = <&edma 30 0 &edma 31 0>; + dma-names = "tx", "rx"; + }; + + timer2_target: target-module@40000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&timer2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm814-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; + }; + + timer3: timer@42000 { + compatible = "ti,dm814-timer"; + reg = <0x42000 0x2000>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + mmc1: mmc@60000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc1"; + dmas = <&edma 24 0 + &edma 25 0>; + dma-names = "tx", "rx"; + interrupts = <64>; + interrupt-parent = <&intc>; + reg = <0x60000 0x1000>; + }; + + rtc: rtc@c0000 { + compatible = "ti,am3352-rtc", "ti,da830-rtc"; + reg = <0xc0000 0x1000>; + interrupts = <75 76>; + ti,hwmods = "rtc"; + }; + + mmc2: mmc@1d8000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc2"; + dmas = <&edma 2 0 + &edma 3 0>; + dma-names = "tx", "rx"; + interrupts = <28>; + interrupt-parent = <&intc>; + reg = <0x1d8000 0x1000>; + }; + + control: control@140000 { + compatible = "ti,dm814-scm", "simple-bus"; + reg = <0x140000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x140000 0x20000>; + + scm_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800>; + + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dm814-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <1>; + }; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scm_clockdomains: clockdomains { + }; + }; + + usb_ctrl_mod: control@620 { + compatible = "ti,am335x-usb-ctrl-module"; + reg = <0x620 0x10 + 0x648 0x4>; + reg-names = "phy_ctrl", "wakeup"; + }; + + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <32>; + dma-masters = <&edma>; + }; + + /* + * Note that silicon revision 2.1 and older + * require input enabled (bit 18 set) for all + * 3.3V I/Os to avoid cumulative hardware damage. + * For more info, see errata advisory 2.1.87. + * We leave bit 18 out of function-mask and rely + * on the bootloader for it. + */ + pincntl: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x438>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x307ff>; + }; + + usb1_phy: usb-phy@1b00 { + compatible = "ti,am335x-usb-phy"; + reg = <0x1b00 0x100>; + reg-names = "phy"; + ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; + }; + }; + + prcm: prcm@180000 { + compatible = "ti,dm814-prcm", "simple-bus"; + reg = <0x180000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x180000 0x2000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ + pllss: pllss@1c5000 { + compatible = "ti,dm814-pllss", "simple-bus"; + reg = <0x1c5000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1c5000 0x1000>; + + pllss_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + pllss_clockdomains: clockdomains { + }; + }; + + wdt1: wdt@1c7000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer"; + reg = <0x1c7000 0x1000>; + interrupts = <91>; + }; + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,dm814-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + /* Board must configure evtmux with edma_xbar for EDMA */ + mmc3: mmc@47810000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc3"; + interrupts = <29>; + interrupt-parent = <&intc>; + reg = <0x47810000 0x1000>; + }; + + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 3>, <&edma_tptc3 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + }; + + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49b00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49b00000 0x4>, + <0x49b00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49b00000 0x100000>; + + edma_tptc3: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <115>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + /* See TRM "Table 1-318. L4HS Instance Summary" */ + l4hs: l4hs@4a000000 { + compatible = "ti,dm814-l4hs", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x1b4040>; + + target-module@100000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x100900 0x4>, + <0x100908 0x4>, + <0x100904 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x100000 0x8000>; + + mac: ethernet@0 { + compatible = "ti,cpsw"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0 0x800>, + <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges = <0 0 0x8000>; + syscon = <&scm_conf>; + + davinci_mdio: mdio@800 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x800 0x100>; + }; + + cpsw_emac0: slave@200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + }; + + cpsw_emac1: slave@300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; + }; + }; + }; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + ti,no-idle-on-init; + reg = <0x50000000 0x2000>; + interrupts = <100>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +#include "dm814x-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm8168-evm.dts b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts new file mode 100644 index 000000000000..1d80288f6ba5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "dm816x.dtsi" +#include + +/ { + model = "DM8168 EVM"; + compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000 /* 1 GB */ + 0xc0000000 0x40000000>; /* 1 GB */ + }; + + /* FDC6331L controlled by SD_POW pin */ + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sata_refclk: fixedclock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; + +&dm816x_pinmux { + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ + DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ + DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ + DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ + >; + }; + + mmc_pins: mmc-pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ + DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ + DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ + DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ + DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ + DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ + DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ + DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ + DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ + >; + }; + + usb0_pins: usb0-pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: usb1-pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ + >; + }; + + nandflash_pins: nandflash-pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ + DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ + DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ + DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ + DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ + DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ + DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ + DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ + DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ + DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ + DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ + DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ + DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ + DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ + DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ + DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ + DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ + DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ + DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ + DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ + DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ + DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ + DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ + >; + }; +}; + +&i2c1 { + extgpio0: pcf8575@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + extgpio1: pcf8575@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + + nand@0,0 { + compatible = "ti,omap2-nand"; + linux,mtd-name = "micron,mt29f2g16aadwp"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x780000 0xf880000>; + }; + }; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + flash@0 { + compatible = "w25x32"; + spi-max-frequency = <48000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +}; + +/* At least dm8168-evm rev c won't support multipoint, later may */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + mentor,multipoint = <0>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + mentor,multipoint = <0>; +}; + +&sata { + clocks = <&sysclk5_ck>, <&sata_refclk>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi new file mode 100644 index 000000000000..338449b32a18 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&scrm { + main_fapll: main_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x400 0x40>; + clocks = <&sys_clkin_ck &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>, <4>, <5>, + <6>, <7>; + clock-output-names = "main_pll_clk1", + "main_pll_clk2", + "main_pll_clk3", + "main_pll_clk4", + "main_pll_clk5", + "main_pll_clk6", + "main_pll_clk7"; + }; + + ddr_fapll: ddr_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x440 0x30>; + clocks = <&sys_clkin_ck &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>, <4>; + clock-output-names = "ddr_pll_clk1", + "ddr_pll_clk2", + "ddr_pll_clk3", + "ddr_pll_clk4"; + }; + + video_fapll: video_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x470 0x30>; + clocks = <&sys_clkin_ck &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>; + clock-output-names = "video_pll_clk1", + "video_pll_clk2", + "video_pll_clk3"; + }; + + audio_fapll: audio_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x4a0 0x30>; + clocks = <&main_fapll 7>, < &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>, <4>, <5>; + clock-output-names = "audio_pll_clk1", + "audio_pll_clk2", + "audio_pll_clk3", + "audio_pll_clk4", + "audio_pll_clk5"; + }; +}; + +&scrm_clocks { + secure_32k_ck: secure_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sys_clkin_ck: sys_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; +}; + +/* 0x48180000 */ +&prcm_clocks { + clkout_pre_ck: clkout_pre_ck@100 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 + &audio_fapll 1>; + reg = <0x100>; + }; + + clkout_div_ck: clkout_div_ck@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + reg = <0x100>; + }; + + clkout_ck: clkout_ck@100 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout_div_ck>; + ti,bit-shift = <7>; + reg = <0x100>; + }; + + /* CM_DPLL clocks p1795 */ + sysclk1_ck: sysclk1_ck@300 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 1>; + ti,max-div = <7>; + reg = <0x0300>; + }; + + sysclk2_ck: sysclk2_ck@304 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 2>; + ti,max-div = <7>; + reg = <0x0304>; + }; + + sysclk3_ck: sysclk3_ck@308 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 3>; + ti,max-div = <7>; + reg = <0x0308>; + }; + + sysclk4_ck: sysclk4_ck@30c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 4>; + ti,max-div = <1>; + reg = <0x030c>; + }; + + sysclk5_ck: sysclk5_ck@310 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sysclk4_ck>; + ti,max-div = <1>; + reg = <0x0310>; + }; + + sysclk6_ck: sysclk6_ck@314 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 4>; + ti,dividers = <2>, <4>; + reg = <0x0314>; + }; + + sysclk10_ck: sysclk10_ck@324 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&ddr_fapll 2>; + ti,max-div = <7>; + reg = <0x0324>; + }; + + sysclk24_ck: sysclk24_ck@3b4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 5>; + ti,max-div = <7>; + reg = <0x03b4>; + }; + + mpu_ck: mpu_ck@15dc { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sysclk2_ck>; + ti,bit-shift = <1>; + reg = <0x15dc>; + }; + + audio_pll_a_ck: audio_pll_a_ck@35c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&audio_fapll 1>; + ti,max-div = <7>; + reg = <0x035c>; + }; + + sysclk18_ck: sysclk18_ck@378 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; + reg = <0x0378>; + }; + + timer1_fck: timer1_fck@390 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x0390>; + }; + + timer2_fck: timer2_fck@394 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x0394>; + }; + + timer3_fck: timer3_fck@398 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x0398>; + }; + + timer4_fck: timer4_fck@39c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x039c>; + }; + + timer5_fck: timer5_fck@3a0 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x03a0>; + }; + + timer6_fck: timer6_fck@3a4 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x03a4>; + }; + + timer7_fck: timer7_fck@3a8 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x03a8>; + }; +}; + +&prcm { + default_cm: default_cm@500 { + compatible = "ti,omap4-cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + default_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x5c>; + #clock-cells = <2>; + }; + }; + + alwon_cm: alwon_cm@1400 { + compatible = "ti,omap4-cm"; + reg = <0x1400 0x300>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x300>; + + alwon_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x208>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dm816x.dtsi b/arch/arm/boot/dts/ti/omap/dm816x.dtsi new file mode 100644 index 000000000000..b68686f0643b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dm816x.dtsi @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +/ { + compatible = "ti,dm816"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the dm816x interconnect. + * The real dm816x interconnect network is quite complex. Since + * it will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + reg = <0x44000000 0x10000>; + interrupts = <9 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + prcm: prcm@48180000 { + compatible = "ti,dm816-prcm", "simple-bus"; + reg = <0x48180000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48180000 0x4000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@48140000 { + compatible = "ti,dm816-scrm", "simple-bus"; + reg = <0x48140000 0x21000>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + ranges = <0 0x48140000 0x21000>; + + dm816x_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x50a>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xf>; + }; + + /* Device Configuration Registers */ + scm_conf: syscon@600 { + compatible = "syscon", "simple-bus"; + reg = <0x600 0x110>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x110>; + + usb_phy0: usb-phy@20 { + compatible = "ti,dm8168-usb-phy"; + reg = <0x20 0x8>; + reg-names = "phy"; + clocks = <&main_fapll 6>; + clock-names = "refclk"; + #phy-cells = <0>; + syscon = <&scm_conf>; + }; + + usb_phy1: usb-phy@28 { + compatible = "ti,dm8168-usb-phy"; + reg = <0x28 0x8>; + reg-names = "phy"; + clocks = <&main_fapll 6>; + clock-names = "refclk"; + #phy-cells = <0>; + syscon = <&scm_conf>; + }; + }; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 3>, <&edma_tptc3 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + }; + + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49b00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49b00000 0x4>, + <0x49b00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = ; + ti,sysc-sidle = , + ; + clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49b00000 0x100000>; + + edma_tptc3: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <115>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + elm: elm@48080000 { + compatible = "ti,am3352-elm"; + ti,hwmods = "elm"; + reg = <0x48080000 0x2000>; + interrupts = <4>; + }; + + gpio1: gpio@48032000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + reg = <0x48032000 0x1000>; + interrupts = <96>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@4804c000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + ti,gpio-always-on; + reg = <0x4804c000 0x1000>; + interrupts = <98>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = <100>; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + gpmc,num-cs = <6>; + gpmc,num-waitpins = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c1: i2c@48028000 { + compatible = "ti,omap4-i2c"; + ti,hwmods = "i2c1"; + reg = <0x48028000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <70>; + }; + + i2c2: i2c@4802a000 { + compatible = "ti,omap4-i2c"; + ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <71>; + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,dm816-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + rtc: rtc@480c0000 { + compatible = "ti,am3352-rtc", "ti,da830-rtc"; + reg = <0x480c0000 0x1000>; + interrupts = <75 76>; + ti,hwmods = "rtc"; + }; + + mailbox: mailbox@480c8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480c8000 0x2000>; + interrupts = <77>; + ti,hwmods = "mailbox"; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <0 0 0>; + }; + }; + + spinbox: spinbox@480ca000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x480ca000 0x2000>; + ti,hwmods = "spinbox"; + #hwlock-cells = <1>; + }; + + mdio: mdio@4a100800 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4a100800 0x100>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + phy0: ethernet-phy@0 { + reg = <1>; + }; + phy1: ethernet-phy@1 { + reg = <2>; + }; + }; + + eth0: ethernet@4a100000 { + compatible = "ti,dm816-emac"; + ti,hwmods = "emac0"; + reg = <0x4a100000 0x800 + 0x4a100900 0x3700>; + clocks = <&sysclk24_ck>; + syscon = <&scm_conf>; + ti,davinci-ctrl-reg-offset = <0>; + ti,davinci-ctrl-mod-reg-offset = <0x900>; + ti,davinci-ctrl-ram-offset = <0x2000>; + ti,davinci-ctrl-ram-size = <0x2000>; + interrupts = <40 41 42 43>; + phy-handle = <&phy0>; + }; + + eth1: ethernet@4a120000 { + compatible = "ti,dm816-emac"; + ti,hwmods = "emac1"; + reg = <0x4a120000 0x4000>; + clocks = <&sysclk24_ck>; + syscon = <&scm_conf>; + ti,davinci-ctrl-reg-offset = <0>; + ti,davinci-ctrl-mod-reg-offset = <0x900>; + ti,davinci-ctrl-ram-offset = <0x2000>; + ti,davinci-ctrl-ram-size = <0x2000>; + interrupts = <44 45 46 47>; + phy-handle = <&phy1>; + }; + + sata: sata@4a140000 { + compatible = "ti,dm816-ahci"; + reg = <0x4a140000 0x10000>; + interrupts = <16>; + ti,hwmods = "sata"; + }; + + mcspi1: spi@48030000 { + compatible = "ti,omap4-mcspi"; + reg = <0x48030000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <65>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi1"; + dmas = <&edma 16 0 &edma 17 0 + &edma 18 0 &edma 19 0 + &edma 20 0 &edma 21 0 + &edma 22 0 &edma 23 0>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mmc1: mmc@48060000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x48060000 0x11000>; + ti,hwmods = "mmc1"; + interrupts = <64>; + dmas = <&edma 24 0 &edma 25 0>; + dma-names = "tx", "rx"; + }; + + timer1_target: target-module@4802e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x4802e000 0x4>, + <0x4802e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + }; + }; + + timer2_target: target-module@48040000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x48040000 0x4>, + <0x48040010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48040000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + }; + }; + + timer3: timer@48042000 { + compatible = "ti,dm816-timer"; + reg = <0x48042000 0x2000>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48044000 { + compatible = "ti,dm816-timer"; + reg = <0x48044000 0x2000>; + interrupts = <92>; + ti,hwmods = "timer4"; + ti,timer-pwm; + }; + + timer5: timer@48046000 { + compatible = "ti,dm816-timer"; + reg = <0x48046000 0x2000>; + interrupts = <93>; + ti,hwmods = "timer5"; + ti,timer-pwm; + }; + + timer6: timer@48048000 { + compatible = "ti,dm816-timer"; + reg = <0x48048000 0x2000>; + interrupts = <94>; + ti,hwmods = "timer6"; + ti,timer-pwm; + }; + + timer7: timer@4804a000 { + compatible = "ti,dm816-timer"; + reg = <0x4804a000 0x2000>; + interrupts = <95>; + ti,hwmods = "timer7"; + ti,timer-pwm; + }; + + uart1: serial@48020000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart1"; + reg = <0x48020000 0x2000>; + clock-frequency = <48000000>; + interrupts = <72>; + dmas = <&edma 26 0 &edma 27 0>; + dma-names = "tx", "rx"; + }; + + uart2: serial@48022000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart2"; + reg = <0x48022000 0x2000>; + clock-frequency = <48000000>; + interrupts = <73>; + dmas = <&edma 28 0 &edma 29 0>; + dma-names = "tx", "rx"; + }; + + uart3: serial@48024000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart3"; + reg = <0x48024000 0x2000>; + clock-frequency = <48000000>; + interrupts = <74>; + dmas = <&edma 30 0 &edma 31 0>; + dma-names = "tx", "rx"; + }; + + /* NOTE: USB needs a transceiver driver for phys to work */ + usb: usb_otg_hs@47401000 { + compatible = "ti,am33xx-usb"; + reg = <0x47401000 0x400000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + ti,hwmods = "usb_otg_hs"; + + usb0: usb@47401000 { + compatible = "ti,musb-dm816"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; + reg-names = "mc", "control"; + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "host"; + interface-type = <0>; + phys = <&usb_phy0>; + phy-names = "usb2-phy"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1: usb@47401800 { + compatible = "ti,musb-dm816"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "host"; + interface-type = <0>; + phys = <&usb_phy1>; + phy-names = "usb2-phy"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@47402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <30>; + dma-channels = <30>; + #dma-requests = <256>; + dma-requests = <256>; + }; + }; + + wd_timer2: wd_timer@480c2000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer"; + reg = <0x480c2000 0x1000>; + interrupts = <0>; + }; + }; +}; + +#include "dm816x-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi new file mode 100644 index 000000000000..11d1241b0e13 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "dm814x-clocks.dtsi" + +/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ +&adpll_hdvic_ck { + status = "disabled"; +}; + +&adpll_l3_ck { + status = "disabled"; +}; + +&adpll_dss_ck { + status = "disabled"; +}; + +/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ +&sysclk4_ck { + clocks = <&adpll_isp_ck 1>; +}; + +&sysclk5_ck { + clocks = <&adpll_isp_ck 1>; +}; + +&sysclk6_ck { + clocks = <&adpll_isp_ck 1>; +}; + +/* + * Compared to dm814x, dra62x has different shifts and more mux options. + * Please add the extra options for ysclk_14 and 16 if really needed. + */ +&timer1_fck { + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <4>; +}; + +&timer2_fck { + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <8>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts new file mode 100644 index 000000000000..2f6ac267fc15 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "dra62x.dtsi" +#include + +/ { + model = "DRA62x J5 Eco EVM"; + compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + /* MIC94060YC6 controlled by SD1_POW pin */ + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; +}; + +&cpsw_emac1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +&davinci_mdio { + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f2g16aadwp"; + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "bch8"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x780000 0xf880000>; + }; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; +}; + +&pincntl { + sd1_pins: sd1-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ + DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ + DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ + DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ + DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ + DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ + DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ + DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ + >; + }; + + usb0_pins: usb0-pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ + >; + }; +}; + +/* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "otg"; +}; + +&usb1_phy { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra62x.dtsi b/arch/arm/boot/dts/ti/omap/dra62x.dtsi new file mode 100644 index 000000000000..cfefa670515c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra62x.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "dm814x.dtsi" + +/ { + compatible = "ti,dra62x"; +}; + +/* Compared to dm814x, dra62x has different offsets for Ethernet */ +&mac { + reg = <0 0x800>, + <0x1200 0x100>; +}; + +&davinci_mdio { + reg = <0x1000 0x100>; +}; + +#include "dra62x-clocks.dtsi" diff --git a/arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi new file mode 100644 index 000000000000..747ff0db90c7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for DRA7x SoC DSPEVE thermal + * + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +dspeve_thermal: dspeve_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 3>; + + trips { + dspeve_crit: dspeve_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi new file mode 100644 index 000000000000..4cdffd6db740 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "dra74-ipu-dsp-common.dtsi" +#include +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "DRA7xx-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out", + "Microphone", "Mic Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + sound0_master: simple-audio-card,cpu { + sound-dai = <&mcasp3>; + system-clock-frequency = <5644800>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&atl_clkin2_ck>; + }; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "dra7:usr1"; + gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led1 { + label = "dra7:usr2"; + gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "dra7:usr3"; + gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "dra7:usr4"; + gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + USER1 { + label = "btnUser1"; + linux,code = ; + gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; + }; + + USER2 { + label = "btnUser2"; + linux,code = ; + gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; +}; + +&mcspi1 { + status = "okay"; +}; + +&mcspi2 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + flash@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x00010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&usb1 { + dr_mode = "otg"; + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + dr_mode = "host"; + extcon = <&extcon_usb2>; +}; + +&atl { + assigned-clocks = <&abe_dpll_sys_clk_mux>, + <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, + <&dpll_abe_ck>, + <&dpll_abe_m2x2_ck>, + <&atl_clkin2_ck>; + assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; + assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; + + status = "okay"; + + atl2 { + bws = ; + aws = ; + }; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + assigned-clock-parents = <&atl_clkin2_ck>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&pcie1_rc { + status = "okay"; +}; + +&mmc4 { + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + wifi@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-evm.dts b/arch/arm/boot/dts/ti/omap/dra7-evm.dts new file mode 100644 index 000000000000..46efbaa67a8e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-evm.dts @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include "dra7-evm-common.dtsi" +#include "dra74x-mmc-iodelay.dtsi" + +/ { + model = "TI DRA742"; + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ + }; + + evm_12v0: fixedregulator-evm_12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + vin-supply = <&smps9_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + + evm_3v3_sw: fixedregulator-evm_3v3_sw { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sw"; + vin-supply = <&sysen1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + /* TPS77018DBVT */ + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd"; + vin-supply = <&evm_3v3_sw>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + evm_5v0: fixedregulator-evm_5v0 { + /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */ + compatible = "regulator-fixed"; + regulator-name = "evm_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + evm_3v6: fixedregulator-evm_3v6 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v6"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + vin-supply = <&evm_5v0>; + regulator-always-on; + regulator-boot-on; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 8 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + vin-supply = <&sysen2>; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + +}; + +&dra7_pmx_core { + dcan1_pins_default: dcan1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1-sleep-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + ti,palmas-override-powerhold; + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps123_reg: smps123 { + /* VDD_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* CORE_VDD */ + regulator-name = "smps7"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_IVAHD */ + regulator-name = "smps8"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDS1V8 */ + regulator-name = "smps9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* VDD_RTCIO */ + /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* REGEN1 is unused */ + + regen2: regen2 { + /* Needed for PMIC internal resources */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + + /* REGEN3 is unused */ + + sysen1: sysen1 { + /* PMIC_REGEN_3V3 */ + regulator-name = "sysen1"; + regulator-boot-on; + regulator-always-on; + }; + + sysen2: sysen2 { + /* PMIC_REGEN_DDR */ + regulator-name = "sysen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; + + pcf_lcd: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcf_gpio_21: gpio@21 { + compatible = "nxp,pcf8575"; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tlv320aic3106: tlv320aic3106@19 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x19>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + AVDD-supply = <&evm_3v3_sw>; + IOVDD-supply = <&evm_3v3_sw>; + DRVDD-supply = <&evm_3v3_sw>; + DVDD-supply = <&aic_dvdd>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + pcf_hdmi: gpio@26 { + compatible = "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + hdmi-audio-hog { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&evm_3v3_sd>; + vqmmc-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is always hardwired. + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; + pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&evm_1v8_sw>; + vqmmc-supply = <&evm_1v8_sw>; + bus-width = <8>; + non-removable; + pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; + pinctrl-3 = <&mmc2_pins_ddr_rev20>; + pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; + pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; +}; + +&mmc4 { + status = "okay"; + vmmc-supply = <&evm_3v6>; + vqmmc-supply = <&vmmcwl_fixed>; + pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25"; + pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>; + pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>; + pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; + pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; + pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; + pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; + pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; + pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; +}; + +&cpu0 { + vdd-supply = <&smps123_reg>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra7-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&gpio7_target { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + ethphy0: ethernet-phy@2 { + reg = <2>; + }; + + ethphy1: ethernet-phy@3 { + reg = <3>; + }; +}; + +&dcan1 { + status = "okay"; + pinctrl-names = "default", "sleep", "active"; + pinctrl-0 = <&dcan1_pins_sleep>; + pinctrl-1 = <&dcan1_pins_sleep>; + pinctrl-2 = <&dcan1_pins_default>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..a5bdc6431d8d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA7xx/AM57xx platforms + */ + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { + status = "okay"; + }; +}; + +&ipu2 { + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + ti,timers = <&timer11>; + ti,watchdog-timers = <&timer7>, <&timer8>; +}; + +&dsp1 { + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer10>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi new file mode 100644 index 000000000000..0a31313065df --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for DRA7x SoC IVA thermal + * + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +iva_thermal: iva_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 4>; + + trips { + iva_crit: iva_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi new file mode 100644 index 000000000000..5733e3a4ea8e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -0,0 +1,4606 @@ +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; + power-domains = <&prm_coreaon>; + clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ + <0x00100000 0x4a100000 0x100000>, /* segment 1 */ + <0x00200000 0x4a200000 0x100000>; /* segment 2 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x001000>, /* ap 2 */ + <0x00002000 0x00002000 0x002000>, /* ap 3 */ + <0x00004000 0x00004000 0x001000>, /* ap 4 */ + <0x00005000 0x00005000 0x001000>, /* ap 5 */ + <0x00006000 0x00006000 0x001000>, /* ap 6 */ + <0x00008000 0x00008000 0x002000>, /* ap 7 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ + <0x00056000 0x00056000 0x001000>, /* ap 9 */ + <0x00057000 0x00057000 0x001000>, /* ap 10 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ + <0x00060000 0x00060000 0x001000>, /* ap 12 */ + <0x00080000 0x00080000 0x008000>, /* ap 13 */ + <0x00088000 0x00088000 0x001000>, /* ap 14 */ + <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ + <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ + <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ + <0x000da000 0x000da000 0x001000>, /* ap 18 */ + <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ + <0x000de000 0x000de000 0x001000>, /* ap 20 */ + <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ + <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ + <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ + <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ + <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ + <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ + <0x00090000 0x00090000 0x008000>, /* ap 59 */ + <0x00098000 0x00098000 0x001000>; /* ap 60 */ + + target-module@2000 { /* 0x4a002000, ap 3 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x2000>; + + scm: scm@0 { + compatible = "ti,dra7-scm-core", "simple-bus"; + reg = <0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + scm_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x1400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x1400>; + + pbias_regulator: pbias_regulator@e00 { + compatible = "ti,pbias-dra7", "ti,pbias-omap"; + reg = <0xe00 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dra7xx-phy-gmii-sel"; + reg = <0x554 0x4>; + #phy-cells = <1>; + }; + + scm_conf_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dra7_pmx_core: pinmux@1400 { + compatible = "ti,dra7-padconf", + "pinctrl-single"; + reg = <0x1400 0x0468>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; + + scm_conf1: scm_conf@1c04 { + compatible = "syscon"; + reg = <0x1c04 0x0020>; + #syscon-cells = <2>; + }; + + scm_conf_pcie: scm_conf@1c24 { + compatible = "syscon"; + reg = <0x1c24 0x0024>; + }; + + sdma_xbar: dma-router@b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xb78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; + + edma_xbar: dma-router@c78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xc78 0x7c>; + #dma-cells = <2>; + dma-requests = <204>; + ti,dma-safe-map = <0>; + dma-masters = <&edma>; + }; + }; + }; + + target-module@5000 { /* 0x4a005000, ap 5 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + + cm_core_aon: cm_core_aon@0 { + compatible = "ti,dra7-cm-core-aon", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2000>; + ranges = <0 0 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + }; + + target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + + cm_core: cm_core@0 { + compatible = "ti,dra7-cm-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x3000>; + ranges = <0 0 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; + }; + + target-module@56000 { /* 0x4a056000, ap 9 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): core_pwrdm, dma_clkdm */ + clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma", "ti,omap-sdma"; + reg = <0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; + }; + + target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@80000 { /* 0x4a080000, ap 13 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x80000 0x4>, + <0x80010 0x4>, + <0x80014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x8000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + reg = <0x0 0x20>; + + usb2_phy1: phy@4000 { + compatible = "ti,dra7x-usb2", "ti,omap-usb2"; + reg = <0x4000 0x400>; + syscon-phy-power = <&scm_conf 0x300>; + clocks = <&usb_phy1_always_on_clk32k>, + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb2_phy2: phy@5000 { + compatible = "ti,dra7x-usb2-phy2", + "ti,omap-usb2"; + reg = <0x5000 0x400>; + syscon-phy-power = <&scm_conf 0xe74>; + clocks = <&usb_phy2_always_on_clk32k>, + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb3_phy1: phy@4400 { + compatible = "ti,omap-usb3"; + reg = <0x4400 0x80>, + <0x4800 0x64>, + <0x4c00 0x40>; + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x370>; + clocks = <&usb_phy3_always_on_clk32k>, + <&sys_clkin1>, + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; + clock-names = "wkupclk", + "sysclk", + "refclk"; + #phy-cells = <0>; + }; + }; + }; + + target-module@90000 { /* 0x4a090000, ap 59 42.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x90000 0x4>, + <0x90010 0x4>, + <0x90014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x8000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + reg = <0x0 0x20>; + + pcie1_phy: pciephy@4000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4000 0x80>, /* phy_rx */ + <0x4400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + syscon-phy-power = <&scm_conf_pcie 0x1c>; + syscon-pcs = <&scm_conf_pcie 0x10>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, + <&optfclk_pciephy_div>, + <&sys_clkin1>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div", "sysclk"; + #phy-cells = <0>; + }; + + pcie2_phy: pciephy@5000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x5000 0x80>, /* phy_rx */ + <0x5400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + syscon-phy-power = <&scm_conf_pcie 0x20>; + syscon-pcs = <&scm_conf_pcie 0x10>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, + <&optfclk_pciephy_div>, + <&sys_clkin1>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div", "sysclk"; + #phy-cells = <0>; + status = "disabled"; + }; + + sata_phy: phy@6000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x6000 0x80>, /* phy_rx */ + <0x6400 0x64>, /* phy_tx */ + <0x6800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x374>; + clocks = <&sys_clkin1>, + <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; + clock-names = "sysclk", "refclk"; + syscon-pllreset = <&scm_conf 0x3fc>; + #phy-cells = <0>; + }; + }; + }; + + target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x8000>; + }; + + target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + reg = <0xd9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd9000 0x1000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + + target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + reg = <0xdd038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xdd000 0x1000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + + target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0000 0x1000>; + }; + + target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xf4000 0x4>, + <0xf4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf4000 0x1000>; + + mailbox1: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + status = "disabled"; + }; + }; + + target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xf6000 0x4>, + <0xf6010 0x4>, + <0xf6014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf6000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ + <0x00003000 0x00103000 0x001000>, /* ap 28 */ + <0x00008000 0x00108000 0x001000>, /* ap 29 */ + <0x00009000 0x00109000 0x001000>, /* ap 30 */ + <0x00040000 0x00140000 0x010000>, /* ap 31 */ + <0x00050000 0x00150000 0x001000>, /* ap 32 */ + <0x00051000 0x00151000 0x001000>, /* ap 33 */ + <0x00052000 0x00152000 0x001000>, /* ap 34 */ + <0x00053000 0x00153000 0x001000>, /* ap 35 */ + <0x00054000 0x00154000 0x001000>, /* ap 36 */ + <0x00055000 0x00155000 0x001000>, /* ap 37 */ + <0x00056000 0x00156000 0x001000>, /* ap 38 */ + <0x00057000 0x00157000 0x001000>, /* ap 39 */ + <0x00058000 0x00158000 0x001000>, /* ap 40 */ + <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ + <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ + <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ + <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ + <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ + <0x00060000 0x00160000 0x001000>, /* ap 48 */ + <0x00061000 0x00161000 0x001000>, /* ap 49 */ + <0x00062000 0x00162000 0x001000>, /* ap 50 */ + <0x00063000 0x00163000 0x001000>, /* ap 51 */ + <0x00064000 0x00164000 0x001000>, /* ap 52 */ + <0x00065000 0x00165000 0x001000>, /* ap 53 */ + <0x00066000 0x00166000 0x001000>, /* ap 54 */ + <0x00067000 0x00167000 0x001000>, /* ap 55 */ + <0x00068000 0x00168000 0x001000>, /* ap 56 */ + <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ + <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ + <0x00071000 0x00171000 0x001000>, /* ap 61 */ + <0x00072000 0x00172000 0x001000>, /* ap 62 */ + <0x00073000 0x00173000 0x001000>, /* ap 63 */ + <0x00074000 0x00174000 0x001000>, /* ap 64 */ + <0x00075000 0x00175000 0x001000>, /* ap 65 */ + <0x00076000 0x00176000 0x001000>, /* ap 66 */ + <0x00077000 0x00177000 0x001000>, /* ap 67 */ + <0x00078000 0x00178000 0x001000>, /* ap 68 */ + <0x00081000 0x00181000 0x001000>, /* ap 69 */ + <0x00082000 0x00182000 0x001000>, /* ap 70 */ + <0x00083000 0x00183000 0x001000>, /* ap 71 */ + <0x00084000 0x00184000 0x001000>, /* ap 72 */ + <0x00085000 0x00185000 0x001000>, /* ap 73 */ + <0x00086000 0x00186000 0x001000>, /* ap 74 */ + <0x00087000 0x00187000 0x001000>, /* ap 75 */ + <0x00088000 0x00188000 0x001000>, /* ap 76 */ + <0x00069000 0x00169000 0x001000>, /* ap 103 */ + <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ + <0x00079000 0x00179000 0x001000>, /* ap 105 */ + <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ + <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ + <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ + <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ + <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ + <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ + <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ + <0x00059000 0x00159000 0x001000>, /* ap 125 */ + <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ + + target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@40000 { /* 0x4a140000, ap 31 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x400fc 4>, + <0x41100 4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + power-domains = <&prm_l3init>; + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>; + clock-names = "fck"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + + sata: sata@0 { + compatible = "snps,dwc-ahci"; + reg = <0 0x1100>, <0x1100 0x8>; + interrupts = ; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; + ports-implemented = <0x1>; + }; + }; + + target-module@51000 { /* 0x4a151000, ap 33 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x51000 0x1000>; + }; + + target-module@53000 { /* 0x4a153000, ap 35 54.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000 0x1000>; + }; + + target-module@55000 { /* 0x4a155000, ap 37 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + }; + + target-module@57000 { /* 0x4a157000, ap 39 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + }; + + target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f000 0x1000>; + }; + + target-module@61000 { /* 0x4a161000, ap 49 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x61000 0x1000>; + }; + + target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x63000 0x1000>; + }; + + target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x65000 0x1000>; + }; + + target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x67000 0x1000>; + }; + + target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x69000 0x1000>; + }; + + target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6b000 0x1000>; + }; + + target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6d000 0x1000>; + }; + + target-module@71000 { /* 0x4a171000, ap 61 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x71000 0x1000>; + }; + + target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x73000 0x1000>; + }; + + target-module@75000 { /* 0x4a175000, ap 65 64.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x75000 0x1000>; + }; + + target-module@77000 { /* 0x4a177000, ap 67 66.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x77000 0x1000>; + }; + + target-module@79000 { /* 0x4a179000, ap 105 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x79000 0x1000>; + }; + + target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7b000 0x1000>; + }; + + target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7d000 0x1000>; + }; + + target-module@81000 { /* 0x4a181000, ap 69 26.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x81000 0x1000>; + }; + + target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x83000 0x1000>; + }; + + target-module@85000 { /* 0x4a185000, ap 73 36.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x85000 0x1000>; + }; + + target-module@87000 { /* 0x4a187000, ap 75 74.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x87000 0x1000>; + }; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ + <0x00019000 0x00219000 0x001000>, /* ap 44 */ + <0x00000000 0x00200000 0x001000>, /* ap 77 */ + <0x00001000 0x00201000 0x001000>, /* ap 78 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ + <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ + <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ + <0x00010000 0x00210000 0x001000>, /* ap 85 */ + <0x00011000 0x00211000 0x001000>, /* ap 86 */ + <0x00012000 0x00212000 0x001000>, /* ap 87 */ + <0x00013000 0x00213000 0x001000>, /* ap 88 */ + <0x00014000 0x00214000 0x001000>, /* ap 89 */ + <0x00015000 0x00215000 0x001000>, /* ap 90 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ + <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ + <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ + <0x00020000 0x00220000 0x001000>, /* ap 97 */ + <0x00021000 0x00221000 0x001000>, /* ap 98 */ + <0x00024000 0x00224000 0x001000>, /* ap 99 */ + <0x00025000 0x00225000 0x001000>, /* ap 100 */ + <0x00026000 0x00226000 0x001000>, /* ap 101 */ + <0x00027000 0x00227000 0x001000>, /* ap 102 */ + <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ + <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ + <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ + <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ + <0x00030000 0x00230000 0x001000>, /* ap 113 */ + <0x00031000 0x00231000 0x001000>, /* ap 114 */ + <0x00032000 0x00232000 0x001000>, /* ap 115 */ + <0x00033000 0x00233000 0x001000>, /* ap 116 */ + <0x00034000 0x00234000 0x001000>, /* ap 117 */ + <0x00035000 0x00235000 0x001000>, /* ap 118 */ + <0x00036000 0x00236000 0x001000>, /* ap 119 */ + <0x00037000 0x00237000 0x001000>, /* ap 120 */ + <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ + <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ + + target-module@0 { /* 0x4a200000, ap 77 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 85 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 87 16.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 43 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 97 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@24000 { /* 0x4a224000, ap 99 44.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + + target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c000 0x1000>; + }; + + target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + }; + + target-module@30000 { /* 0x4a230000, ap 113 70.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + }; + + target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + }; + + target-module@34000 { /* 0x4a234000, ap 117 76.1 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + }; + + target-module@36000 { /* 0x4a236000, ap 119 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + }; +}; + +&l4_per1 { /* 0x48000000 */ + compatible = "ti,dra7-l4-per1", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00055000 0x00055000 0x001000>, /* ap 13 */ + <0x00056000 0x00056000 0x001000>, /* ap 14 */ + <0x00057000 0x00057000 0x001000>, /* ap 15 */ + <0x00058000 0x00058000 0x001000>, /* ap 16 */ + <0x00059000 0x00059000 0x001000>, /* ap 17 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ + <0x00060000 0x00060000 0x001000>, /* ap 23 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ + <0x00070000 0x00070000 0x001000>, /* ap 30 */ + <0x00071000 0x00071000 0x001000>, /* ap 31 */ + <0x00072000 0x00072000 0x001000>, /* ap 32 */ + <0x00073000 0x00073000 0x001000>, /* ap 33 */ + <0x00061000 0x00061000 0x001000>, /* ap 34 */ + <0x00053000 0x00053000 0x001000>, /* ap 35 */ + <0x00054000 0x00054000 0x001000>, /* ap 36 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ + <0x00078000 0x00078000 0x001000>, /* ap 39 */ + <0x00079000 0x00079000 0x001000>, /* ap 40 */ + <0x00086000 0x00086000 0x001000>, /* ap 41 */ + <0x00087000 0x00087000 0x001000>, /* ap 42 */ + <0x00088000 0x00088000 0x001000>, /* ap 43 */ + <0x00089000 0x00089000 0x001000>, /* ap 44 */ + <0x00051000 0x00051000 0x001000>, /* ap 45 */ + <0x00052000 0x00052000 0x001000>, /* ap 46 */ + <0x00098000 0x00098000 0x001000>, /* ap 47 */ + <0x00099000 0x00099000 0x001000>, /* ap 48 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ + <0x00068000 0x00068000 0x001000>, /* ap 53 */ + <0x00069000 0x00069000 0x001000>, /* ap 54 */ + <0x00090000 0x00090000 0x002000>, /* ap 55 */ + <0x00092000 0x00092000 0x001000>, /* ap 56 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ + <0x00066000 0x00066000 0x001000>, /* ap 63 */ + <0x00067000 0x00067000 0x001000>, /* ap 64 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ + <0x00001400 0x00001400 0x000400>, /* ap 77 */ + <0x00001800 0x00001800 0x000400>, /* ap 78 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ + <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ + <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ + <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ + <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ + <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; + dma-names = "tx", "rx"; + }; + }; + + target-module@32000 { /* 0x48032000, ap 5 3e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x51000 0x4>, + <0x51010 0x4>, + <0x51114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x51000 0x1000>; + + gpio7: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@53000 { /* 0x48053000, ap 35 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x53000 0x4>, + <0x53010 0x4>, + <0x53114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000 0x1000>; + + gpio8: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@59000 { /* 0x48059000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@60000 { /* 0x48060000, ap 23 32.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@66000 { /* 0x48066000, ap 63 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x66050 0x4>, + <0x66054 0x4>, + <0x66058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + uart5: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; + dma-names = "tx", "rx"; + }; + }; + + target-module@68000 { /* 0x48068000, ap 53 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x68050 0x4>, + <0x68054 0x4>, + <0x68058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x68000 0x1000>; + + uart6: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; + dma-names = "tx", "rx"; + }; + }; + + target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; + dma-names = "tx", "rx"; + }; + }; + + target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; + dma-names = "tx", "rx"; + }; + }; + + target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; + dma-names = "tx", "rx"; + }; + }; + + target-module@70000 { /* 0x48070000, ap 30 22.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@72000 { /* 0x48072000, ap 32 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@78000 { /* 0x48078000, ap 39 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x78000 0x4>, + <0x78010 0x4>, + <0x78014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0xfc0>; /* device IO registers */ + interrupts = ; + status = "disabled"; + }; + }; + + target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x7a000 0x8>, + <0x7a010 0x8>, + <0x7a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7a000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x7c000 0x8>, + <0x7c010 0x8>, + <0x7c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7c000 0x1000>; + + i2c5: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + target-module@86000 { /* 0x48086000, ap 41 5e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x86000 0x4>, + <0x86010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@88000 { /* 0x48088000, ap 43 66.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@90000 { /* 0x48090000, ap 55 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + + target-module@98000 { /* 0x48098000, ap 47 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma_xbar 35>, + <&sdma_xbar 36>, + <&sdma_xbar 37>, + <&sdma_xbar 38>, + <&sdma_xbar 39>, + <&sdma_xbar 40>, + <&sdma_xbar 41>, + <&sdma_xbar 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + status = "disabled"; + }; + }; + + target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma_xbar 43>, + <&sdma_xbar 44>, + <&sdma_xbar 45>, + <&sdma_xbar 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; + }; + + target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + pbias-supply = <&pbias_mmc_reg>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + }; + }; + + target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + + target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ + max-frequency = <64000000>; + /* SDMA is not supported */ + sdhci-caps-mask = <0x0 0x400000>; + }; + }; + + target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xb2000 0x4>, + <0xb2014 0x4>, + <0xb2018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + ti,no-reset-on-init; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + + hdqw1w: 1w@0 { + compatible = "ti,omap3-1w"; + reg = <0x0 0x1000>; + interrupts = ; + }; + }; + + target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + max-frequency = <192000000>; + /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ + sdhci-caps-mask = <0x7 0x0>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + }; + }; + + target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; + dma-names = "tx0", "rx0"; + status = "disabled"; + }; + }; + + target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; + dma-names = "tx0", "rx0"; + status = "disabled"; + }; + }; + + target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + max-frequency = <192000000>; + /* SDMA is not supported */ + sdhci-caps-mask = <0x0 0x400000>; + }; + }; + + target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&l4_per2 { /* 0x48400000 */ + compatible = "ti,dra7-l4-per2", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48400000 0x800>, + <0x48400800 0x800>, + <0x48401000 0x400>, + <0x48401400 0x400>, + <0x48401800 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ + <0x45800000 0x45800000 0x400000>, /* L3 data port */ + <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ + <0x46000000 0x46000000 0x400000>, /* L3 data port */ + <0x48436000 0x48436000 0x400000>, /* L3 data port */ + <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ + <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ + <0x48450000 0x48450000 0x400000>, /* L3 data port */ + <0x48454000 0x48454000 0x400000>; /* L3 data port */ + + segment@0 { /* 0x48400000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00084000 0x00084000 0x004000>, /* ap 3 */ + <0x00001400 0x00001400 0x000400>, /* ap 4 */ + <0x00001800 0x00001800 0x000400>, /* ap 5 */ + <0x00088000 0x00088000 0x001000>, /* ap 6 */ + <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ + <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ + <0x00060000 0x00060000 0x002000>, /* ap 9 */ + <0x00062000 0x00062000 0x001000>, /* ap 10 */ + <0x00064000 0x00064000 0x002000>, /* ap 11 */ + <0x00066000 0x00066000 0x001000>, /* ap 12 */ + <0x00068000 0x00068000 0x002000>, /* ap 13 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ + <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ + <0x00036000 0x00036000 0x001000>, /* ap 17 */ + <0x00037000 0x00037000 0x001000>, /* ap 18 */ + <0x00070000 0x00070000 0x002000>, /* ap 19 */ + <0x00072000 0x00072000 0x001000>, /* ap 20 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ + <0x00040000 0x00040000 0x001000>, /* ap 27 */ + <0x00041000 0x00041000 0x001000>, /* ap 28 */ + <0x00042000 0x00042000 0x001000>, /* ap 29 */ + <0x00043000 0x00043000 0x001000>, /* ap 30 */ + <0x00080000 0x00080000 0x002000>, /* ap 31 */ + <0x00082000 0x00082000 0x001000>, /* ap 32 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ + <0x00074000 0x00074000 0x002000>, /* ap 35 */ + <0x00076000 0x00076000 0x001000>, /* ap 36 */ + <0x00050000 0x00050000 0x001000>, /* ap 37 */ + <0x00051000 0x00051000 0x001000>, /* ap 38 */ + <0x00078000 0x00078000 0x002000>, /* ap 39 */ + <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ + <0x00054000 0x00054000 0x001000>, /* ap 41 */ + <0x00055000 0x00055000 0x001000>, /* ap 42 */ + <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ + <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ + <0x00020000 0x00020000 0x001000>, /* ap 47 */ + <0x00021000 0x00021000 0x001000>, /* ap 48 */ + <0x00022000 0x00022000 0x001000>, /* ap 49 */ + <0x00023000 0x00023000 0x001000>, /* ap 50 */ + <0x00024000 0x00024000 0x001000>, /* ap 51 */ + <0x00025000 0x00025000 0x001000>, /* ap 52 */ + <0x00046000 0x00046000 0x001000>, /* ap 53 */ + <0x00047000 0x00047000 0x001000>, /* ap 54 */ + <0x00048000 0x00048000 0x001000>, /* ap 55 */ + <0x00049000 0x00049000 0x001000>, /* ap 56 */ + <0x00058000 0x00058000 0x002000>, /* ap 57 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ + <0x45800000 0x45800000 0x400000>, /* L3 data port */ + <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ + <0x46000000 0x46000000 0x400000>, /* L3 data port */ + <0x48436000 0x48436000 0x400000>, /* L3 data port */ + <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ + <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ + <0x48450000 0x48450000 0x400000>, /* L3 data port */ + <0x48454000 0x48454000 0x400000>; /* L3 data port */ + + target-module@20000 { /* 0x48420000, ap 47 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + uart7: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; + }; + + target-module@22000 { /* 0x48422000, ap 49 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x22050 0x4>, + <0x22054 0x4>, + <0x22058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + + uart8: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; + }; + + target-module@24000 { /* 0x48424000, ap 51 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x24050 0x4>, + <0x24054 0x4>, + <0x24058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + uart9: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; + }; + + target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c000 0x1000>; + }; + + target-module@36000 { /* 0x48436000, ap 17 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>; + }; + + atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x3c000 0x4>; + reg-names = "rev"; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>; + + atl: atl@0 { + compatible = "ti,dra7-atl"; + reg = <0x0 0x3ff>; + ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, + <&atl_clkin2_ck>, <&atl_clkin3_ck>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + epwmss0: epwmss@0 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap0: pwm@100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm0: pwm@200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@40000 { /* 0x48440000, ap 27 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + epwmss1: epwmss@0 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap1: pwm@100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm1: pwm@200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@42000 { /* 0x48442000, ap 29 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x42000 0x4>, + <0x42004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + + epwmss2: epwmss@0 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap2: pwm@100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm2: pwm@200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; + }; + + target-module@46000 { /* 0x48446000, ap 53 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + + target-module@48000 { /* 0x48448000, ap 55 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + }; + + target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + }; + + target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + }; + + target-module@50000 { /* 0x48450000, ap 37 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000 0x1000>; + }; + + target-module@54000 { /* 0x48454000, ap 41 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54000 0x1000>; + }; + + target-module@58000 { /* 0x48458000, ap 57 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x2000>; + }; + + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x48460000, ap 9 0e.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x60000 0x4>, + <0x60004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x2000>, + <0x45800000 0x45800000 0x400000>; + + mcasp1: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x45800000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; + dma-names = "tx", "rx"; + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; + }; + + target-module@64000 { /* 0x48464000, ap 11 1e.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x64000 0x4>, + <0x64004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x2000>, + <0x45c00000 0x45c00000 0x400000>; + + mcasp2: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x45c00000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; + }; + + target-module@68000 { /* 0x48468000, ap 13 26.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x68000 0x4>, + <0x68004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x68000 0x2000>, + <0x46000000 0x46000000 0x400000>; + + mcasp3: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + }; + + target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x6c000 0x4>, + <0x6c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x2000>, + <0x48436000 0x48436000 0x400000>; + + mcasp4: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x48436000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + }; + + target-module@70000 { /* 0x48470000, ap 19 36.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x70000 0x4>, + <0x70004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x2000>, + <0x4843a000 0x4843a000 0x400000>; + + mcasp5: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x4843a000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + }; + + target-module@74000 { /* 0x48474000, ap 35 14.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x74000 0x4>, + <0x74004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x2000>, + <0x4844c000 0x4844c000 0x400000>; + + mcasp6: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x4844c000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + }; + + target-module@78000 { /* 0x48478000, ap 39 0c.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x78000 0x4>, + <0x78004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x2000>, + <0x48450000 0x48450000 0x400000>; + + mcasp7: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x48450000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + }; + + target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; + reg = <0x7c000 0x4>, + <0x7c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7c000 0x2000>, + <0x48454000 0x48454000 0x400000>; + + mcasp8: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x48454000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + }; + + target-module@80000 { /* 0x48480000, ap 31 16.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x80020 0x4>; + reg-names = "rev"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x2000>; + + dcan2: can@0 { + compatible = "ti,dra7-d_can"; + reg = <0x0 0x2000>; + syscon-raminit = <&scm_conf 0x558 1>; + interrupts = ; + clocks = <&sys_clkin1>; + status = "disabled"; + }; + }; + + target-module@84000 { /* 0x48484000, ap 3 10.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x85200 0x4>, + <0x85208 0x4>, + <0x85204 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x84000 0x4000>; + /* + * Do not allow gating of cpsw clock as workaround + * for errata i877. Keeping internal clock disabled + * causes the device switching characteristics + * to degrade over time and eventually fail to meet + * the data manual delay time/skew specs. + */ + ti,no-idle; + + mac_sw: switch@0 { + compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&gmac_main_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + status = "disabled"; + + interrupts = , + , + , + ; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "port2"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; + }; + }; + + davinci_mdio_sw: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&gmac_main_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + }; + + cpts { + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; + clock-names = "cpts"; + }; + }; + }; + }; +}; + +&l4_per3 { /* 0x48800000 */ + compatible = "ti,dra7-l4-per3", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48800000 0x800>, + <0x48800800 0x800>, + <0x48801000 0x400>, + <0x48801400 0x400>, + <0x48801800 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ + + segment@0 { /* 0x48800000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>, /* ap 3 */ + <0x00001800 0x00001800 0x000400>, /* ap 4 */ + <0x00020000 0x00020000 0x001000>, /* ap 5 */ + <0x00021000 0x00021000 0x001000>, /* ap 6 */ + <0x00022000 0x00022000 0x001000>, /* ap 7 */ + <0x00023000 0x00023000 0x001000>, /* ap 8 */ + <0x00024000 0x00024000 0x001000>, /* ap 9 */ + <0x00025000 0x00025000 0x001000>, /* ap 10 */ + <0x00026000 0x00026000 0x001000>, /* ap 11 */ + <0x00027000 0x00027000 0x001000>, /* ap 12 */ + <0x00028000 0x00028000 0x001000>, /* ap 13 */ + <0x00029000 0x00029000 0x001000>, /* ap 14 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ + <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ + <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ + <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ + <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ + <0x00170000 0x00170000 0x010000>, /* ap 21 */ + <0x00180000 0x00180000 0x001000>, /* ap 22 */ + <0x00190000 0x00190000 0x010000>, /* ap 23 */ + <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ + <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ + <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ + <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ + <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ + <0x00038000 0x00038000 0x001000>, /* ap 29 */ + <0x00039000 0x00039000 0x001000>, /* ap 30 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ + <0x00040000 0x00040000 0x001000>, /* ap 39 */ + <0x00041000 0x00041000 0x001000>, /* ap 40 */ + <0x00042000 0x00042000 0x001000>, /* ap 41 */ + <0x00043000 0x00043000 0x001000>, /* ap 42 */ + <0x00044000 0x00044000 0x001000>, /* ap 43 */ + <0x00045000 0x00045000 0x001000>, /* ap 44 */ + <0x00046000 0x00046000 0x001000>, /* ap 45 */ + <0x00047000 0x00047000 0x001000>, /* ap 46 */ + <0x00048000 0x00048000 0x001000>, /* ap 47 */ + <0x00049000 0x00049000 0x001000>, /* ap 48 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ + <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ + <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ + <0x00050000 0x00050000 0x001000>, /* ap 55 */ + <0x00051000 0x00051000 0x001000>, /* ap 56 */ + <0x00052000 0x00052000 0x001000>, /* ap 57 */ + <0x00053000 0x00053000 0x001000>, /* ap 58 */ + <0x00054000 0x00054000 0x001000>, /* ap 59 */ + <0x00055000 0x00055000 0x001000>, /* ap 60 */ + <0x00056000 0x00056000 0x001000>, /* ap 61 */ + <0x00057000 0x00057000 0x001000>, /* ap 62 */ + <0x00058000 0x00058000 0x001000>, /* ap 63 */ + <0x00059000 0x00059000 0x001000>, /* ap 64 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ + <0x00064000 0x00064000 0x001000>, /* ap 67 */ + <0x00065000 0x00065000 0x001000>, /* ap 68 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ + <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ + <0x00060000 0x00060000 0x001000>, /* ap 71 */ + <0x00061000 0x00061000 0x001000>, /* ap 72 */ + <0x00062000 0x00062000 0x001000>, /* ap 73 */ + <0x00063000 0x00063000 0x001000>, /* ap 74 */ + <0x00140000 0x00140000 0x020000>, /* ap 75 */ + <0x00160000 0x00160000 0x001000>, /* ap 76 */ + <0x00016000 0x00016000 0x001000>, /* ap 77 */ + <0x00017000 0x00017000 0x001000>, /* ap 78 */ + <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ + <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ + <0x00004000 0x00004000 0x001000>, /* ap 81 */ + <0x00005000 0x00005000 0x001000>, /* ap 82 */ + <0x00080000 0x00080000 0x020000>, /* ap 83 */ + <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ + <0x00100000 0x00100000 0x020000>, /* ap 85 */ + <0x00120000 0x00120000 0x001000>, /* ap 86 */ + <0x00010000 0x00010000 0x001000>, /* ap 87 */ + <0x00011000 0x00011000 0x001000>, /* ap 88 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ + <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ + <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ + <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ + <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ + <0x00002000 0x00002000 0x001000>, /* ap 95 */ + <0x00003000 0x00003000 0x001000>; /* ap 96 */ + + target-module@2000 { /* 0x48802000, ap 95 7c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + mailbox13: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@4000 { /* 0x48804000, ap 81 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@a000 { /* 0x4880a000, ap 89 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@10000 { /* 0x48810000, ap 87 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@16000 { /* 0x48816000, ap 77 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x48820000, ap 5 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + timer5: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@22000 { /* 0x48822000, ap 7 24.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x22000 0x4>, + <0x22010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + + timer6: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@24000 { /* 0x48824000, ap 9 26.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x24000 0x4>, + <0x24010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + timer7: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@26000 { /* 0x48826000, ap 11 0c.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x26000 0x4>, + <0x26010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + + timer8: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@28000 { /* 0x48828000, ap 13 16.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x28000 0x4>, + <0x28010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + + timer13: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2a000 0x4>, + <0x2a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + + timer14: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2c000 0x4>, + <0x2c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c000 0x1000>; + + timer15: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + + timer16: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x38074 0x4>, + <0x38078 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ + clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>; + + rtc: rtc@0 { + compatible = "ti,am3352-rtc"; + reg = <0x0 0x100>; + interrupts = , + ; + clocks = <&sys_32k_ck>; + }; + }; + + target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x3a000 0x4>, + <0x3a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>; + + mailbox2: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x3c000 0x4>, + <0x3c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>; + + mailbox3: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + mailbox4: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@40000 { /* 0x48840000, ap 39 64.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + mailbox5: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@42000 { /* 0x48842000, ap 41 4e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x42000 0x4>, + <0x42010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + + mailbox6: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@44000 { /* 0x48844000, ap 43 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x44000 0x4>, + <0x44010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + + mailbox7: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@46000 { /* 0x48846000, ap 45 48.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x46000 0x4>, + <0x46010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + + mailbox8: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@48000 { /* 0x48848000, ap 47 36.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + }; + + target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + }; + + target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + }; + + target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4e000 0x1000>; + }; + + target-module@50000 { /* 0x48850000, ap 55 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000 0x1000>; + }; + + target-module@52000 { /* 0x48852000, ap 57 54.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x52000 0x1000>; + }; + + target-module@54000 { /* 0x48854000, ap 59 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54000 0x1000>; + }; + + target-module@56000 { /* 0x48856000, ap 61 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + }; + + target-module@58000 { /* 0x48858000, ap 63 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x1000>; + }; + + target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5a000 0x1000>; + }; + + target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5c000 0x1000>; + }; + + target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5e000 0x4>, + <0x5e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x1000>; + + mailbox9: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@60000 { /* 0x48860000, ap 71 4a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x60000 0x4>, + <0x60010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + mailbox10: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@62000 { /* 0x48862000, ap 73 74.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x62000 0x4>, + <0x62010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + + mailbox11: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@64000 { /* 0x48864000, ap 67 52.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x64000 0x4>, + <0x64010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + + mailbox12: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + }; + + target-module@80000 { /* 0x48880000, ap 83 0e.1 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x80000 0x4>, + <0x80010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x20000>; + + omap_dwc3_1: omap_dwc3_1@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + + usb1: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; + }; + + target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc0000 0x4>, + <0xc0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x20000>; + + omap_dwc3_2: omap_dwc3_2@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + + usb2: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_metastability_quirk; + }; + }; + }; + + usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x100000 0x4>, + <0x100010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x20000>; + + omap_dwc3_3: omap_dwc3_3@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + status = "disabled"; + + usb3: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; + }; + + target-module@170000 { /* 0x48970000, ap 21 0a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x170010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x170000 0x10000>; + status = "disabled"; + }; + + target-module@190000 { /* 0x48990000, ap 23 2e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x190010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x190000 0x10000>; + status = "disabled"; + }; + + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + status = "disabled"; + }; + + target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1d0010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + , + ; + power-domains = <&prm_vpe>; + clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d0000 0x10000>; + + vpe: vpe@0 { + compatible = "ti,dra7-vpe"; + reg = <0x0000 0x120>, + <0x0700 0x80>, + <0x5700 0x18>, + <0xd000 0x400>; + reg-names = "vpe_top", + "sc", + "csc", + "vpdma"; + interrupts = ; + }; + }; + }; +}; + +&l4_wkup { /* 0x4ae00000 */ + compatible = "ti,dra7-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkupaon>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4ae00000 0x800>, + <0x4ae00800 0x800>, + <0x4ae01000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ + <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ + <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ + <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ + + segment@0 { /* 0x4ae00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 15 */ + <0x00005000 0x00005000 0x001000>, /* ap 16 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ + + target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x40>; + }; + }; + + target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,dra7-prm", "simple-bus"; + reg = <0 0x3000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x3000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + }; + + target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + scm_wkup: scm_conf@0 { + compatible = "syscon"; + reg = <0 0x1000>; + }; + }; + }; + + segment@10000 { /* 0x4ae10000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ + + target-module@0 { /* 0x4ae10000, ap 5 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, + <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x8000 0x4>, + <0x8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-alwon; + }; + }; + + target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + }; + + segment@20000 { /* 0x4ae20000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 19 */ + <0x00001000 0x00021000 0x001000>, /* ap 20 */ + <0x00002000 0x00022000 0x001000>, /* ap 21 */ + <0x00003000 0x00023000 0x001000>, /* ap 22 */ + <0x00007000 0x00027000 0x000400>, /* ap 23 */ + <0x00008000 0x00028000 0x000800>, /* ap 24 */ + <0x00009000 0x00029000 0x000100>, /* ap 25 */ + <0x00008800 0x00028800 0x000200>, /* ap 26 */ + <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ + <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ + <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ + <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ + + target-module@0 { /* 0x4ae20000, ap 19 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x0 0x4>, + <0x10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + timer12: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + interrupts = ; + ti,timer-alwon; + ti,timer-secure; + }; + }; + + target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00002800 0x00008800 0x00000200>, + <0x00002a00 0x00008a00 0x00000100>, + <0x00003000 0x00009000 0x00000100>; + }; + + target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xb050 0x4>, + <0xb054 0x4>, + <0xb058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000 0x1000>; + + uart10: serial@0 { + compatible = "ti,dra742-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; + }; + + target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf000 0x1000>; + }; + }; + + segment@30000 { /* 0x4ae30000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ + <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ + <0x00000000 0x00030000 0x001000>, /* ap 33 */ + <0x00001000 0x00031000 0x001000>, /* ap 34 */ + <0x00002000 0x00032000 0x001000>, /* ap 35 */ + <0x00003000 0x00033000 0x001000>, /* ap 36 */ + <0x00004000 0x00034000 0x001000>, /* ap 37 */ + <0x00005000 0x00035000 0x001000>, /* ap 38 */ + <0x00006000 0x00036000 0x001000>, /* ap 39 */ + <0x00007000 0x00037000 0x001000>, /* ap 40 */ + <0x00008000 0x00038000 0x001000>, /* ap 41 */ + <0x00009000 0x00039000 0x001000>, /* ap 42 */ + <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ + + target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1000 0x1000>; + }; + + target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + + target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9000 0x1000>; + }; + + target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc020 0x4>; + reg-names = "rev"; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x2000>; + + dcan1: can@0 { + compatible = "ti,dra7-d_can"; + reg = <0x0 0x2000>; + syscon-raminit = <&scm_conf 0x558 0>; + interrupts = ; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; + status = "disabled"; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi new file mode 100644 index 000000000000..cb1a682c26cd --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MMC IOdelay values for TI's DRA7xx SoCs. + * Copyright (C) 2018 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +&dra7_pmx_core { + mmc1_pins_default_no_clk_pu: mmc1-default-no-clk-pu-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi new file mode 100644 index 000000000000..97ce0c4f1df7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi @@ -0,0 +1,1358 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + * + * Based on "omap4.dtsi" + */ + +#include +#include +#include +#include +#include + +#define MAX_SOURCES 400 + +/ { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "ti,dra7xx"; + interrupt-parent = <&crossbar_mpu>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + i2c4 = &i2c5; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + serial9 = &uart10; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + d_can0 = &dcan1; + d_can1 = &dcan2; + spi0 = &qspi; + }; + + timer { + compatible = "arm,armv7-timer"; + status = "disabled"; /* See ARM architected timer wrap erratum i940 */ + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x48211000 0x0 0x1000>, + <0x0 0x48212000 0x0 0x2000>, + <0x0 0x48214000 0x0 0x2000>, + <0x0 0x48216000 0x0 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller@48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x48281000 0x0 0x1000>; + interrupt-parent = <&gic>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + + vbb-supply = <&abb_mpu>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_wkup>; + + opp_nom-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>, + <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od-1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>, + <1160000 885000 1160000>; + + opp-supported-hw = <0xFF 0x02>; + }; + + opp_high@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1210000 950000 1250000>, + <1210000 950000 1250000>; + opp-supported-hw = <0xFF 0x04>; + }; + }; + + /* + * XXX: Use a flat representation of the SOC interconnect. + * The real OMAP interconnect network is quite complex. + * Since it will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp: ocp { + compatible = "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>, + <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; + + l3-noc@44000000 { + compatible = "ti,dra7-l3-noc"; + reg = <0x44000000 0x1000>, + <0x45000000 0x1000>; + interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + l4_cfg: interconnect@4a000000 { + }; + l4_wkup: interconnect@4ae00000 { + }; + l4_per1: interconnect@48000000 { + }; + + target-module@48210000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48210000 0x1f0000>; + + mpu { + compatible = "ti,omap5-mpu"; + }; + }; + + l4_per2: interconnect@48400000 { + }; + l4_per3: interconnect@48800000 { + }; + + /* + * Register access seems to have complex dependencies and also + * seems to need an enabled phy. See the TRM chapter for "Table + * 26-678. Main Sequence PCIe Controller Global Initialization" + * and also dra7xx_pcie_probe(). + */ + axi0: target-module@51000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + power-domains = <&prm_l3init>; + resets = <&prm_l3init 0>; + reset-names = "rstctrl"; + clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>; + clock-names = "fck", "phy-clk", "phy-clk-div"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51000000 0x51000000 0x3000>, + <0x20000000 0x20000000 0x10000000>; + dma-ranges; + /** + * To enable PCI endpoint mode, disable the pcie1_rc + * node and enable pcie1_ep mode. + */ + pcie1_rc: pcie@51000000 { + reg = <0x51000000 0x2000>, + <0x51002000 0x14c>, + <0x20001000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 232 0x4>, <0 233 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>, + <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + num-lanes = <1>; + linux,pci-domain = <0>; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 1>, + <0 0 0 2 &pcie1_intc 2>, + <0 0 0 3 &pcie1_intc 3>, + <0 0 0 4 &pcie1_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; + status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1_ep: pcie_ep@51000000 { + reg = <0x51000000 0x28>, + <0x51002000 0x14c>, + <0x51001000 0x28>, + <0x20001000 0x10000000>; + reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; + interrupts = <0 232 0x4>; + num-lanes = <1>; + num-ib-windows = <4>; + num-ob-windows = <16>; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; + status = "disabled"; + }; + }; + + /* + * Register access seems to have complex dependencies and also + * seems to need an enabled phy. See the TRM chapter for "Table + * 26-678. Main Sequence PCIe Controller Global Initialization" + * and also dra7xx_pcie_probe(). + */ + axi1: target-module@51800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>; + clock-names = "fck", "phy-clk", "phy-clk-div"; + power-domains = <&prm_l3init>; + resets = <&prm_l3init 1>; + reset-names = "rstctrl"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51800000 0x51800000 0x3000>, + <0x30000000 0x30000000 0x10000000>; + dma-ranges; + status = "disabled"; + pcie2_rc: pcie@51800000 { + reg = <0x51800000 0x2000>, + <0x51802000 0x14c>, + <0x30001000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 355 0x4>, <0 356 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, + <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + num-lanes = <1>; + linux,pci-domain = <1>; + phys = <&pcie2_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 1>, + <0 0 0 2 &pcie2_intc 2>, + <0 0 0 3 &pcie2_intc 3>, + <0 0 0 4 &pcie2_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + pcie2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + ocmcram1: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x80000>; + ranges = <0x0 0x40300000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + /* + * This is a placeholder for an optional reserved + * region for use by secure software. The size + * of this region is not known until runtime so it + * is set as zero to either be updated to reserve + * space or left unchanged to leave all SRAM for use. + * On HS parts that that require the reserved region + * either the bootloader can update the size to + * the required amount or the node can be overridden + * from the board dts file for the secure platform. + */ + sram-hs@0 { + compatible = "ti,secure-ram"; + reg = <0x0 0x0>; + }; + }; + + /* + * NOTE: ocmcram2 and ocmcram3 are not available on all + * DRA7xx and AM57xx variants. Confirm availability in + * the data manual for the exact part number in use + * before enabling these nodes in the board dts file. + */ + ocmcram2: ocmcram@40400000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40400000 0x100000>; + ranges = <0x0 0x40400000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ocmcram3: ocmcram@40500000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40500000 0x100000>; + ranges = <0x0 0x40500000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + bandgap: bandgap@4a0021e0 { + reg = <0x4a0021e0 0xc + 0x4a00232c 0xc + 0x4a002380 0x2c + 0x4a0023C0 0x3c + 0x4a002564 0x8 + 0x4a002574 0x50>; + compatible = "ti,dra752-bandgap"; + interrupts = ; + #thermal-sensor-cells = <1>; + }; + + dsp1_system: dsp_system@40d00000 { + compatible = "syscon"; + reg = <0x40d00000 0x100>; + }; + + dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + }; + + target-module@43300000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x43300000 0x4>, + <0x43300010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43300000 0x100000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x100000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; + + /* + * memcpy is disabled, can be enabled with: + * ti,edma-memcpy-channels = <20 21>; + * for example. Note that these channels need to be + * masked in the xbar as well. + */ + }; + }; + + target-module@43400000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x43400000 0x4>, + <0x43400010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43400000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@43500000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x43500000 0x4>, + <0x43500010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43500000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@4e000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4e000000 0x4>, + <0x4e000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + ranges = <0x0 0x4e000000 0x2000000>; + #size-cells = <1>; + #address-cells = <1>; + + dmm@0 { + compatible = "ti,omap5-dmm"; + reg = <0 0x800>; + interrupts = ; + }; + }; + + ipu1: ipu@58820000 { + compatible = "ti,dra7-ipu"; + reg = <0x58820000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu1>; + status = "disabled"; + resets = <&prm_ipu 0>, <&prm_ipu 1>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + firmware-name = "dra7-ipu1-fw.xem4"; + }; + + ipu2: ipu@55020000 { + compatible = "ti,dra7-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu2>; + status = "disabled"; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + firmware-name = "dra7-ipu2-fw.xem4"; + }; + + dsp1: dsp@40800000 { + compatible = "ti,dra7-dsp"; + reg = <0x40800000 0x48000>, + <0x40e00000 0x8000>, + <0x40f00000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x55c 10>; + iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; + status = "disabled"; + resets = <&prm_dsp1 0>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + firmware-name = "dra7-dsp1-fw.xe66"; + }; + + target-module@40d01000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x40d01000 0x4>, + <0x40d01010 0x4>, + <0x40d01014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp1 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x40d01000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu0_dsp1: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x0>; + }; + }; + + target-module@40d02000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x40d02000 0x4>, + <0x40d02010 0x4>, + <0x40d02014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp1 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x40d02000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu1_dsp1: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x1>; + }; + }; + + target-module@58882000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58882000 0x4>, + <0x58882010 0x4>, + <0x58882014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_ipu 2>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58882000 0x100>; + + mmu_ipu1: mmu@0 { + compatible = "ti,dra7-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; + }; + + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55082000 0x100>; + + mmu_ipu2: mmu@0 { + compatible = "ti,dra7-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; + }; + + abb_mpu: regulator-abb-mpu { + compatible = "ti,abb-v3"; + regulator-name = "abb_mpu"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, + <0x4ae06014 0x4>, <0x4a003b20 0xc>, + <0x4ae0c158 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x80>; + /* LDOVBBMPU_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBMPU_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1060000 0 0x0 0 0x02000000 0x01F00000 + 1160000 0 0x4 0 0x02000000 0x01F00000 + 1210000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + abb_ivahd: regulator-abb-ivahd { + compatible = "ti,abb-v3"; + regulator-name = "abb_ivahd"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, + <0x4ae06010 0x4>, <0x4a0025cc 0xc>, + <0x4a002470 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x40000000>; + /* LDOVBBIVA_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBIVA_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1055000 0 0x0 0 0x02000000 0x01F00000 + 1150000 0 0x4 0 0x02000000 0x01F00000 + 1250000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + abb_dspeve: regulator-abb-dspeve { + compatible = "ti,abb-v3"; + regulator-name = "abb_dspeve"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, + <0x4ae06010 0x4>, <0x4a0025e0 0xc>, + <0x4a00246c 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x20000000>; + /* LDOVBBDSPEVE_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBDSPEVE_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1055000 0 0x0 0 0x02000000 0x01F00000 + 1150000 0 0x4 0 0x02000000 0x01F00000 + 1250000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + abb_gpu: regulator-abb-gpu { + compatible = "ti,abb-v3"; + regulator-name = "abb_gpu"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, + <0x4ae06010 0x4>, <0x4a003b08 0xc>, + <0x4ae0c154 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x10000000>; + /* LDOVBBGPU_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBGPU_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1090000 0 0x0 0 0x02000000 0x01F00000 + 1210000 0 0x4 0 0x02000000 0x01F00000 + 1280000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + target-module@4b300000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4b300000 0x4>, + <0x4b300010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b300000 0x1000>, + <0x5c000000 0x5c000000 0x4000000>; + + qspi: spi@0 { + compatible = "ti,dra7xxx-qspi"; + reg = <0 0x100>, + <0x5c000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; + syscon-chipselects = <&scm_conf 0x558>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; + clock-names = "fck"; + num-cs = <4>; + interrupts = ; + status = "disabled"; + }; + }; + + /* OCP2SCP1 */ + /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ + + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + reg = <0x50000000 0x37c>; /* device IO registers */ + interrupts = ; + dmas = <&edma_xbar 4 0>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + }; + + crossbar_mpu: crossbar@4a002a48 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + interrupt-controller; + interrupt-parent = <&wakeupgen>; + #interrupt-cells = <3>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = ; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + ti,irqs-safe-map = <0>; + }; + + target-module@58000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000000 4>, + <0x58000014 4>; + reg-names = "rev", "syss"; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x58000000 0x800000>; + + dss: dss@0 { + compatible = "ti,dra7-dss"; + /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ + /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ + status = "disabled"; + /* CTRL_CORE_DSS_PLL_CONTROL */ + syscon-pll-ctrl = <&scm_conf 0x538>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800000>; + + target-module@1000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x1000 0x4>, + <0x1010 0x4>, + <0x1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-midle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x1000>; + + dispc@0 { + compatible = "ti,dra7-dispc"; + reg = <0 0x1000>; + interrupts = ; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + }; + }; + + target-module@40000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; + clock-names = "fck", "dss_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000 0x40000>; + + hdmi: encoder@0 { + compatible = "ti,dra7-hdmi"; + reg = <0 0x200>, + <0x200 0x80>, + <0x300 0x80>, + <0x20000 0x19000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = ; + status = "disabled"; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + dmas = <&sdma_xbar 76>; + dma-names = "audio_tx"; + }; + }; + }; + }; + + target-module@59000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x59000020 0x4>; + reg-names = "rev"; + clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000000 0x1000>; + + bb2d: gpu@0 { + compatible = "vivante,gc"; + reg = <0x0 0x700>; + interrupts = ; + clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; + clock-names = "core"; + }; + }; + + aes1_target: target-module@4b500000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b500080 0x4>, + <0x4b500084 0x4>, + <0x4b500088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b500000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + + aes2_target: target-module@4b700000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b700080 0x4>, + <0x4b700084 0x4>, + <0x4b700088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b700000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + + sham1_target: target-module@4b101000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b101100 0x4>, + <0x4b101110 0x4>, + <0x4b101114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b101000 0x1000>; + + sham1: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&edma_xbar 119 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + + sham2_target: target-module@42701000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x42701100 0x4>, + <0x42701110 0x4>, + <0x42701114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42701000 0x1000>; + + sham2: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&edma_xbar 165 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + + iva_hd_target: target-module@5a000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5a05a400 0x4>, + <0x5a05a410 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + power-domains = <&prm_iva>; + resets = <&prm_iva 2>; + reset-names = "rstctrl"; + clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x5a000000 0x1000000>, + <0x5b000000 0x5b000000 0x1000000>; + + iva { + compatible = "ti,ivahd"; + }; + }; + + opp_supply_mpu: opp-supply@4a003b20 { + compatible = "ti,omap5-opp-supply"; + reg = <0x4a003b20 0xc>; + ti,efuse-settings = < + /* uV offset */ + 1060000 0x0 + 1160000 0x4 + 1210000 0x8 + >; + ti,absolute-max-voltage-uv = <1500000>; + }; + + }; + + thermal_zones: thermal-zones { + #include "omap4-cpu-thermal.dtsi" + #include "omap5-gpu-thermal.dtsi" + #include "omap5-core-thermal.dtsi" + #include "dra7-dspeve-thermal.dtsi" + #include "dra7-iva-thermal.dtsi" + }; + +}; + +&cpu_thermal { + polling-delay = <500>; /* milliseconds */ + coefficients = <0 2000>; +}; + +&gpu_thermal { + coefficients = <0 2000>; +}; + +&core_thermal { + coefficients = <0 2000>; +}; + +&dspeve_thermal { + coefficients = <0 2000>; +}; + +&iva_thermal { + coefficients = <0 2000>; +}; + +&cpu_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&core_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&gpu_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&dspeve_crit { + temperature = <120000>; /* milli Celsius */ +}; + +&iva_crit { + temperature = <120000>; /* milli Celsius */ +}; + +#include "dra7-l4.dtsi" +#include "dra7xx-clocks.dtsi" + +&prm { + prm_mpu: prm@300 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + + prm_dsp1: prm@400 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_ipu: prm@500 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_coreaon: prm@628 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x628 0xd8>; + #power-domain-cells = <0>; + }; + + prm_core: prm@700 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x700 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_iva: prm@f00 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_cam: prm@1000 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1000 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1100 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x100>; + #power-domain-cells = <0>; + }; + + prm_gpu: prm@1200 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #power-domain-cells = <0>; + }; + + prm_l3init: prm@1300 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1300 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_l4per: prm@1400 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1400 0x100>; + #power-domain-cells = <0>; + }; + + prm_custefuse: prm@1600 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1600 0x100>; + #power-domain-cells = <0>; + }; + + prm_wkupaon: prm@1724 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1724 0x100>; + #power-domain-cells = <0>; + }; + + prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_eve1: prm@1b40 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1b40 0x40>; + #power-domain-cells = <0>; + }; + + prm_eve2: prm@1b80 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1b80 0x40>; + #power-domain-cells = <0>; + }; + + prm_eve3: prm@1bc0 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1bc0 0x40>; + #power-domain-cells = <0>; + }; + + prm_eve4: prm@1c00 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1c00 0x60>; + #power-domain-cells = <0>; + }; + + prm_rtc: prm@1c60 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1c60 0x20>; + #power-domain-cells = <0>; + }; + + prm_vpe: prm@1c80 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1c80 0x80>; + #power-domain-cells = <0>; + }; +}; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; + +/* Local timers, see ARM architected timer wrap erratum i940 */ +&timer15_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; + assigned-clock-parents = <&timer_sys_clk_div>; + }; +}; + +&timer16_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; + assigned-clock-parents = <&timer_sys_clk_div>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra71-evm.dts b/arch/arm/boot/dts/ti/omap/dra71-evm.dts new file mode 100644 index 000000000000..a64364443031 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra71-evm.dts @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "dra71x.dtsi" +#include "dra7-mmc-iodelay.dtsi" +#include "dra72x-mmc-iodelay.dtsi" +#include + +/ { + compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; + model = "TI DRA718 EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + + vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { + compatible = "regulator-gpio"; + + regulator-name = "vddshv8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&evm_5v0>; + + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&lp8732_buck0_reg>; + regulator-always-on; + regulator-boot-on; + }; + + poweroff: gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + lp8733: lp8733@60 { + compatible = "ti,lp8733"; + reg = <0x60>; + + buck0-in-supply =<&vsys_3v3>; + buck1-in-supply =<&vsys_3v3>; + ldo0-in-supply =<&evm_5v0>; + ldo1-in-supply =<&evm_5v0>; + + lp8733_regulators: regulators { + lp8733_buck0_reg: buck0 { + /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ + regulator-name = "lp8733-buck0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8733_buck1_reg: buck1 { + /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ + regulator-name = "lp8733-buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8733_ldo0_reg: ldo0 { + /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ + regulator-name = "lp8733-ldo0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8733_ldo1_reg: ldo1 { + /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ + regulator-name = "lp8733-ldo1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + lp8732: lp8732@61 { + compatible = "ti,lp8732"; + reg = <0x61>; + + buck0-in-supply =<&vsys_3v3>; + buck1-in-supply =<&vsys_3v3>; + ldo0-in-supply =<&vsys_3v3>; + ldo1-in-supply =<&vsys_3v3>; + + lp8732_regulators: regulators { + lp8732_buck0_reg: buck0 { + /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ + regulator-name = "lp8732-buck0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8732_buck1_reg: buck1 { + /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ + regulator-name = "lp8732-buck1"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8732_ldo0_reg: ldo0 { + /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ + regulator-name = "lp8732-ldo0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8732_ldo1_reg: ldo1 { + /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ + regulator-name = "lp8732-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pcf_lcd { + interrupt-parent = <&gpio7>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio7>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +}; + +&pcf_hdmi { + hdmi-i2c-disable-hog { + /* + * PM_OEn to High: Disable routing I2C3 to PM_I2C + * With this PM_SEL(p3) should not matter + */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pm_oe_n"; + }; +}; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; + vqmmc-supply = <&vpo_sd_1v8_3v3>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; + vmmc-supply = <&evm_1v8_sw>; + vqmmc-supply = <&evm_1v8_sw>; +}; + +&mac_sw { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <&dp83867_0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <&dp83867_1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +/* No Sata on this device */ +&sata_phy { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +/* No RTC on this device */ +&rtc { + status = "disabled"; +}; + +&usb2_phy1 { + phy-supply = <&lp8733_ldo1_reg>; +}; + +&usb2_phy2 { + phy-supply = <&lp8733_ldo1_reg>; +}; + +&dss { + /* Supplied by VDA_1V8_PLL */ + vdda_video-supply = <&lp8732_ldo0_reg>; +}; + +&hdmi { + /* Supplied by VDA_1V8_PHY */ + vdda_video-supply = <&lp8732_ldo1_reg>; +}; + +&extcon_usb1 { + vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +}; + +&extcon_usb2 { + vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra71x.dtsi b/arch/arm/boot/dts/ti/omap/dra71x.dtsi new file mode 100644 index 000000000000..9c270d8f75d5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra71x.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra72-evm-common.dtsi" + +&rtctarget { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi new file mode 100644 index 000000000000..31ab0c60ca75 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include "dra7-ipu-dsp-common.dtsi" +#include +#include + +/ { + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + aliases { + display0 = &hdmi0; + }; + + chosen { + stdout-path = &uart1; + }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + evm_5v0: fixedregulator-evm5v0 { + /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ + /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ + compatible = "regulator-fixed"; + regulator-name = "evm_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + evm_3v6: fixedregulator-evm_3v6 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v6"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + vin-supply = <&evm_5v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ + /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + evm_3v3_sw: fixedregulator-evm_3v3 { + /* TPS22965DSG */ + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + /* TPS77018DBVT */ + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd"; + vin-supply = <&evm_3v3_sw>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_3v3_sw>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "DRA7xx-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out", + "Microphone", "Mic Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + sound0_master: simple-audio-card,cpu { + sound-dai = <&mcasp3>; + system-clock-frequency = <5644800>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&atl_clkin2_ck>; + }; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + clk_ov5640_fixed: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&dra7_pmx_core { + dcan1_pins_default: dcan1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1-sleep-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + pcf_lcd: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcf_gpio_21: gpio@21 { + compatible = "nxp,pcf8575"; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tlv320aic3106: tlv320aic3106@19 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x19>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + AVDD-supply = <&evm_3v3_sw>; + IOVDD-supply = <&evm_3v3_sw>; + DRVDD-supply = <&evm_3v3_sw>; + DVDD-supply = <&aic_dvdd>; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + pcf_hdmi: pcf8575@26 { + compatible = "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + /* + * initial state is used here to keep the mdio interface + * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and + * VIN2_S0 driven high otherwise Ethernet stops working + * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 + */ + lines-initial-states = <0x0f2b>; + + hdmi-audio-hog { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra72-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb1 { + dr_mode = "otg"; + extcon = <&extcon_usb1>; +}; + +&usb2 { + dr_mode = "host"; + extcon = <&extcon_usb2>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + vmmc-supply = <&evm_3v3_sd>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + max-frequency = <192000000>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + bus-width = <8>; + non-removable; + max-frequency = <192000000>; +}; + +&mmc4 { + status = "okay"; + vmmc-supply = <&evm_3v6>; + vqmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "hs", "sdr12", "sdr25"; + pinctrl-0 = <&mmc4_pins_default>; + pinctrl-1 = <&mmc4_pins_default>; + pinctrl-2 = <&mmc4_pins_default>; + pinctrl-3 = <&mmc4_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + wifi@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&dcan1 { + status = "okay"; + pinctrl-names = "default", "sleep", "active"; + pinctrl-0 = <&dcan1_pins_sleep>; + pinctrl-1 = <&dcan1_pins_sleep>; + pinctrl-2 = <&dcan1_pins_default>; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + flash@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x00010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&hdmi { + status = "okay"; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&atl { + assigned-clocks = <&abe_dpll_sys_clk_mux>, + <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, + <&dpll_abe_ck>, + <&dpll_abe_m2x2_ck>, + <&atl_clkin2_ck>; + assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; + assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; + + status = "okay"; + + atl2 { + bws = ; + aws = ; + }; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + assigned-clock-parents = <&atl_clkin2_ck>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&pcie1_rc { + status = "okay"; +}; + +&csi2_0 { + csi2_phy0: endpoint { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts b/arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts new file mode 100644 index 000000000000..f242b937f88c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include "dra72-evm-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" +#include + +/ { + model = "TI DRA722 Rev C EVM"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&smps4_reg>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c1 { + tps65917: tps65917@58 { + reg = <0x58>; + + interrupts = ; /* IRQ_SYS_1N */ + }; +}; + +#include "dra72-evm-tps65917.dtsi" + +&ldo2_reg { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-always-on; + regulator-boot-on; +}; + +&hdmi { + vdda-supply = <&ldo2_reg>; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; +}; + +&mac_sw { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <&dp83867_0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <&dp83867_1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,dp83867-rxctrl-strap-quirk; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; + vqmmc-supply = <&ldo1_reg>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; + vmmc-supply = <&evm_1v8_sw>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi new file mode 100644 index 000000000000..7b433f549239 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * Integrated Power Management Chip + * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf + */ + +&tps65917 { + compatible = "ti,tps65917"; + + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + smps1-in-supply = <&vsys_3v3>; + smps2-in-supply = <&vsys_3v3>; + smps3-in-supply = <&vsys_3v3>; + smps4-in-supply = <&vsys_3v3>; + smps5-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; + ldo2-in-supply = <&vsys_3v3>; + ldo3-in-supply = <&vsys_3v3>; + ldo4-in-supply = <&evm_5v0>; + ldo5-in-supply = <&vsys_3v3>; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&dss { + vdda_video-supply = <&ldo5_reg>; +}; + +&mmc1 { + vqmmc-supply = <&ldo1_reg>; +}; + +&cpu0 { + vdd-supply = <&smps1_reg>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra72-evm.dts b/arch/arm/boot/dts/ti/omap/dra72-evm.dts new file mode 100644 index 000000000000..5f62f92eb96c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra72-evm.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include "dra72-evm-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" +/ { + model = "TI DRA722"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&smps4_reg>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c1 { + tps65917: tps65917@58 { + reg = <0x58>; + + interrupts = ; /* IRQ_SYS_1N */ + }; +}; + +#include "dra72-evm-tps65917.dtsi" + +&hdmi { + vdda-supply = <&ldo3_reg>; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; +}; + +&mac_sw { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&davinci_mdio_sw { + ethphy0: ethernet-phy@3 { + reg = <3>; + }; +}; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev10>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>; + vqmmc-supply = <&ldo1_reg>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev10>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; + vmmc-supply = <&evm_1v8_sw>; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi new file mode 100644 index 000000000000..d006f1dfdeb5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. + * + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and + * 'dra72_' tag to entries. Both the new and old entries should gain a tag. + * + * Datamanual Revisions: + * + * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 + * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 + * DRA71x : SPRS960B, Revised February 2017 + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: mmc1-sdr12-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr25: mmc1-sdr25-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1-sdr50-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + >; + }; + + mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr104: mmc1-sdr104-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_rev10: mmc2-ddr-rev10-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + >; + }; + + mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2-hs200-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc4_pins_default: mmc4-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_MANUAL1 in datamanual */ + mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ + 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + /* Corresponds to MMC1_MANUAL2 in datamanual */ + mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + /* Corresponds to MMC1_MANUAL2 in datamanual */ + mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + /* Corresponds to MMC2_MANUAL1 in datamanual */ + mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + >; + }; + + /* Corresponds to MMC2_MANUAL3 in datamanual */ + mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { + pinctrl-pin-array = < + 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ + 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ + 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + >; + }; + + /* Corresponds to MMC2_MANUAL3 in datamanual */ + mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { + pinctrl-pin-array = < + 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ + 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra72x.dtsi b/arch/arm/boot/dts/ti/omap/dra72x.dtsi new file mode 100644 index 000000000000..90617261373c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra72x.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ + * + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra722", "ti,dra72", "ti,dra7"; + + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&wakeupgen>; + interrupts = ; + }; +}; + +&l4_per2 { + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + cal: cal@0 { + compatible = "ti,dra72-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + ti,camerrx-control = <&scm_conf 0xE94>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + +&dss { + reg = <0 0x80>, + <0x4054 0x4>, + <0x4300 0x20>; + reg-names = "dss", "pll1_clkctrl", "pll1"; + + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; + clock-names = "fck", "video1_clk"; +}; + +&mailbox5 { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +}; + +&mailbox6 { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; +}; + +&pcie1_rc { + compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +}; + +&pcie1_ep { + compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; +}; + +&pcie2_rc { + compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..3256631510c5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms + */ + +#include "dra7-ipu-dsp-common.dtsi" + +&mailbox6 { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { + status = "okay"; + }; +}; + +&dsp2 { + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + ti,timers = <&timer6>; + ti,watchdog-timers = <&timer13>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi new file mode 100644 index 000000000000..e2fdb0702f5c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi @@ -0,0 +1,639 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. + * + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * + * Datamanual Revisions: + * + * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019 + * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 + * + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: mmc1-sdr12-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr25: mmc1-sdr25-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1-sdr50-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: mmc1-ddr50-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr104: mmc1-sdr104-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_3_3v_rev11: mmc2-ddr-3-3v-rev11-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_1_8v_rev11: mmc2-ddr-1-8v-rev11-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2-hs200-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc4_pins_default: mmc4-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; + + mmc4_pins_hs: mmc4-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; + + mmc3_pins_default: mmc3-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_hs: mmc3-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_sdr12: mmc3-sdr12-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_sdr25: mmc3-sdr25-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_sdr50: mmc3-sdr50-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc4_pins_sdr12: mmc4-sdr12-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; + + mmc4_pins_sdr25: mmc4-sdr25-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ + 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ + 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ + mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ + 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ + mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ + 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ + 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ + 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ + 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ + 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ + 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ + 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi new file mode 100644 index 000000000000..006189dad7a7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra74x.dtsi" + +/ { + compatible = "ti,dra762", "ti,dra7"; + + ocp { + emif1: emif@4c000000 { + compatible = "ti,emif-dra7xx"; + reg = <0x4c000000 0x200>; + interrupts = ; + status = "disabled"; + }; + }; +}; + +/* MCAN interrupts are hard-wired to irqs 67, 68 */ +&crossbar_mpu { + ti,irqs-skip = <10 67 68 133 139 140>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra74x.dtsi b/arch/arm/boot/dts/ti/omap/dra74x.dtsi new file mode 100644 index 000000000000..cfb39dde4930 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra74x.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ + * + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra742", "ti,dra74", "ti,dra7"; + + cpus { + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + + vbb-supply = <&abb_mpu>; + }; + }; + + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + rproc3 = &dsp2; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&wakeupgen>; + interrupts = , + ; + }; + + ocp { + dsp2_system: dsp_system@41500000 { + compatible = "syscon"; + reg = <0x41500000 0x100>; + }; + + + target-module@41501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x41501000 0x4>, + <0x41501010 0x4>, + <0x41501014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp2 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x41501000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu0_dsp2: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + }; + }; + + target-module@41502000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x41502000 0x4>, + <0x41502010 0x4>, + <0x41502014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp2 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x41502000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu1_dsp2: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + }; + }; + + dsp2: dsp@41000000 { + compatible = "ti,dra7-dsp"; + reg = <0x41000000 0x48000>, + <0x41600000 0x8000>, + <0x41700000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x560 10>; + iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; + status = "disabled"; + resets = <&prm_dsp2 0>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + firmware-name = "dra7-dsp2-fw.xe66"; + }; + }; +}; + +&cpu0_opp_table { + opp-shared; +}; + +&dss { + reg = <0 0x80>, + <0x4054 0x4>, + <0x4300 0x20>, + <0x9054 0x4>, + <0x9300 0x20>; + reg-names = "dss", "pll1_clkctrl", "pll1", + "pll2_clkctrl", "pll2"; + + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>; + clock-names = "fck", "video1_clk", "video2_clk"; +}; + +&mailbox5 { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +}; + +&mailbox6 { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +}; + +&pcie1_rc { + compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +}; + +&pcie1_ep { + compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; +}; + +&pcie2_rc { + compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +}; + +&l4_per3 { + segment@0 { + usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x140000 0x4>, + <0x140010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x140000 0x20000>; + + omap_dwc3_4: omap_dwc3_4@0 { + compatible = "ti,dwc3"; + reg = <0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra76-evm.dts b/arch/arm/boot/dts/ti/omap/dra76-evm.dts new file mode 100644 index 000000000000..57868ac60d29 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra76-evm.dts @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "dra76x.dtsi" +#include "dra7-evm-common.dtsi" +#include "dra76x-mmc-iodelay.dtsi" +#include + +/ { + model = "TI DRA762 EVM"; + compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; + + aliases { + display0 = &hdmi0; + + sound0 = &sound0; + sound1 = &hdmi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + vsys_12v0: fixedregulator-vsys12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "vsys_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vsys_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vio_3v6: fixedregulator-vio_3v6 { + compatible = "regulator-fixed"; + regulator-name = "vio_3v6"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + vin-supply = <&vsys_5v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vio_3v3: fixedregulator-vio_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + vio_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vio_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vio_3v3>; + enable-active-high; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + vio_1v8: fixedregulator-vio_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&smps5_reg>; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 8 0>; /* gpio5_8 */ + startup-delay-us = <70000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + /* TPS77018DBVT */ + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd"; + vin-supply = <&vio_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ + <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + ti,system-power-controller; + ti,palmas-override-powerhold; + interrupt-controller; + #interrupt-cells = <2>; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + smps12-in-supply = <&vsys_3v3>; + smps3-in-supply = <&vsys_3v3>; + smps4-in-supply = <&vsys_3v3>; + smps5-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; + ldo2-in-supply = <&vsys_3v3>; + ldo3-in-supply = <&vsys_5v0>; + ldo4-in-supply = <&vsys_5v0>; + ldo5-in-supply = <&vsys_3v3>; + + tps65917_regulators: regulators { + smps12_reg: smps12 { + /* VDD_DSPEVE */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_CORE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDD_IVA */ + regulator-name = "smps4"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDDS1V8 */ + regulator-name = "smps5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> VDA_PHY1_1V8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDA_PHY2_1V8 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-bypass; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + /* VDA_USB_3V3 */ + regulator-name = "ldo3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDD_SDIO_DV */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; + + lp87565: lp87565@60 { + compatible = "ti,lp87565-q1"; + reg = <0x60>; + + buck10-in-supply =<&vsys_3v3>; + buck23-in-supply =<&vsys_3v3>; + + regulators: regulators { + buck10_reg: buck10 { + /*VDD_MPU*/ + regulator-name = "buck10"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + buck23_reg: buck23 { + /* VDD_GPU*/ + regulator-name = "buck23"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcf_lcd: pcf8757@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + + pcf_gpio_21: pcf8757@21 { + compatible = "nxp,pcf8575"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcf_hdmi: pcf8575@26 { + compatible = "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + hdmi-audio-hog { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; + + tlv320aic3106: tlv320aic3106@19 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x19>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vio_3v3>; + IOVDD-supply = <&vio_3v3>; + DRVDD-supply = <&vio_3v3>; + DVDD-supply = <&aic_dvdd>; + }; +}; + +&cpu0 { + vdd-supply = <&buck10_reg>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vio_3v3_sd>; + vqmmc-supply = <&ldo4_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is always hardwired. + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vio_1v8>; + vqmmc-supply = <&vio_1v8>; + bus-width = <8>; + non-removable; + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_default>; + pinctrl-2 = <&mmc2_pins_default>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; +}; + +&mmc4 { + status = "okay"; + vmmc-supply = <&vio_3v6>; + vqmmc-supply = <&vmmcwl_fixed>; + pinctrl-names = "default", "hs", "sdr12", "sdr25"; + pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; + pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; + pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; + pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; +}; + +/* No RTC on this device */ +&rtc { + status = "disabled"; +}; + +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { + phy-handle = <&dp83867_0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <&dp83867_1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo3_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo3_reg>; +}; + +&dss { + status = "okay"; + vdda_video-supply = <&ldo5_reg>; +}; + +&hdmi { + status = "okay"; + + vdda-supply = <&ldo1_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&qspi { + spi-max-frequency = <96000000>; + flash@0 { + spi-max-frequency = <96000000>; + }; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; + +&pcie1_ep { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; + +&extcon_usb1 { + vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +}; + +&extcon_usb2 { + vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +}; + +&m_can0 { + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi new file mode 100644 index 000000000000..4690554dfa6e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Texas Instruments +// MMC IOdelay values for TI's DRA76x and AM576x SoCs. +// Author: Sekhar Nori + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * + * Datamanual Revisions: + * + * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018 + * + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1-sdr50-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: mmc1-ddr50-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2-hs200-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc3_pins_default: mmc3-default-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc4_pins_hs: mmc4-hs-pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ + 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL2 in datamanual */ + mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi new file mode 100644 index 000000000000..931db7932c11 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra76x.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "dra74x.dtsi" + +/ { + compatible = "ti,dra762", "ti,dra7"; + + ocp { + target-module@42c01900 { + compatible = "ti,sysc-dra7-mcan", "ti,sysc"; + ranges = <0x0 0x42c00000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x42c01900 0x4>, + <0x42c01904 0x4>, + <0x42c01908 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | + SYSC_DRA7_MCAN_ENAWAKEUP)>; + ti,syss-mask = <1>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; + clock-names = "fck"; + + m_can0: mcan@1a00 { + compatible = "bosch,m_can"; + reg = <0x1a00 0x4000>, <0x0 0x18FC>; + reg-names = "m_can", "message_ram"; + interrupt-parent = <&gic>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&l3_iclk_div>, <&mcan_clk>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; + }; + }; + }; + +}; + +&l4_per3 { + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + + cal: cal@0 { + compatible = "ti,dra76-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + ti,camerrx-control = <&scm_conf 0x6dc>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + +&scm_conf_clocks { + dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + reg = <0x03fc>; + ti,bit-shift = <20>; + ti,latch-bit = <26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; + assigned-clock-rates = <80000000>; + }; + + dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; + reg = <0x3fc>; + ti,bit-shift = <29>; + ti,latch-bit = <26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; + }; + + mcan_clk: mcan_clk@3fc { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + ti,bit-shift = <27>; + reg = <0x3fc>; + }; +}; + +&rtctarget { + status = "disabled"; +}; + +&usb4_tm { + status = "disabled"; +}; + +&mmc3 { + /* dra76x is not affected by i887 */ + max-frequency = <96000000>; +}; + +&cpu0_opp_table { + opp_plus@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000 950000 1250000>, + <1250000 950000 1250000>; + opp-supported-hw = <0xFF 0x08>; + }; +}; + +&opp_supply_mpu { + ti,efuse-settings = < + /* uV offset */ + 1060000 0x0 + 1160000 0x4 + 1210000 0x8 + 1250000 0xC + >; +}; + +&abb_mpu { + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1060000 0 0x0 0 0x02000000 0x01F00000 + 1160000 0 0x4 0 0x02000000 0x01F00000 + 1210000 0 0x8 0 0x02000000 0x01F00000 + 1250000 0 0xC 0 0x02000000 0x01F00000 + >; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi new file mode 100644 index 000000000000..04a7a6d1d529 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -0,0 +1,2094 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for DRA7xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm_core_aon_clocks { + atl_clkin0_ck: clock-atl-clkin0 { + #clock-cells = <0>; + compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin0_ck"; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; + }; + + atl_clkin1_ck: clock-atl-clkin1 { + #clock-cells = <0>; + compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin1_ck"; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; + }; + + atl_clkin2_ck: clock-atl-clkin2 { + #clock-cells = <0>; + compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin2_ck"; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; + }; + + atl_clkin3_ck: clock-atl-clkin3 { + #clock-cells = <0>; + compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin3_ck"; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; + }; + + hdmi_clkin_ck: clock-hdmi-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "hdmi_clkin_ck"; + clock-frequency = <0>; + }; + + mlb_clkin_ck: clock-mlb-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "mlb_clkin_ck"; + clock-frequency = <0>; + }; + + mlbp_clkin_ck: clock-mlbp-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "mlbp_clkin_ck"; + clock-frequency = <0>; + }; + + pciesref_acs_clk_ck: clock-pciesref-acs { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "pciesref_acs_clk_ck"; + clock-frequency = <100000000>; + }; + + ref_clkin0_ck: clock-ref-clkin0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "ref_clkin0_ck"; + clock-frequency = <0>; + }; + + ref_clkin1_ck: clock-ref-clkin1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "ref_clkin1_ck"; + clock-frequency = <0>; + }; + + ref_clkin2_ck: clock-ref-clkin2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "ref_clkin2_ck"; + clock-frequency = <0>; + }; + + ref_clkin3_ck: clock-ref-clkin3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "ref_clkin3_ck"; + clock-frequency = <0>; + }; + + rmii_clk_ck: clock-rmii { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "rmii_clk_ck"; + clock-frequency = <0>; + }; + + sdvenc_clkin_ck: clock-sdvenc-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "sdvenc_clkin_ck"; + clock-frequency = <0>; + }; + + secure_32k_clk_src_ck: clock-secure-32k-clk-src { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; + clock-frequency = <32768>; + }; + + sys_clk32_crystal_ck: clock-sys-clk32-crystal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "sys_clk32_crystal_ck"; + clock-frequency = <32768>; + }; + + sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "sys_clk32_pseudo_ck"; + clocks = <&sys_clkin1>; + clock-mult = <1>; + clock-div = <610>; + }; + + virt_12000000_ck: clock-virt-12000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; + clock-frequency = <12000000>; + }; + + virt_13000000_ck: clock-virt-13000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; + clock-frequency = <13000000>; + }; + + virt_16800000_ck: clock-virt-16800000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; + clock-frequency = <16800000>; + }; + + virt_19200000_ck: clock-virt-19200000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; + clock-frequency = <19200000>; + }; + + virt_20000000_ck: clock-virt-20000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_20000000_ck"; + clock-frequency = <20000000>; + }; + + virt_26000000_ck: clock-virt-26000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; + clock-frequency = <26000000>; + }; + + virt_27000000_ck: clock-virt-27000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; + clock-frequency = <27000000>; + }; + + virt_38400000_ck: clock-virt-38400000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; + clock-frequency = <38400000>; + }; + + sys_clkin2: clock-sys-clkin2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "sys_clkin2"; + clock-frequency = <22579200>; + }; + + usb_otg_clkin_ck: clock-usb-otg-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "usb_otg_clkin_ck"; + clock-frequency = <0>; + }; + + video1_clkin_ck: clock-video1-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "video1_clkin_ck"; + clock-frequency = <0>; + }; + + video1_m2_clkin_ck: clock-video1-m2-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "video1_m2_clkin_ck"; + clock-frequency = <0>; + }; + + video2_clkin_ck: clock-video2-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "video2_clkin_ck"; + clock-frequency = <0>; + }; + + video2_m2_clkin_ck: clock-video2-m2-clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "video2_m2_clkin_ck"; + clock-frequency = <0>; + }; + + dpll_abe_ck: clock@1e0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; + clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; + reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; + }; + + dpll_abe_x2_ck: clock-dpll-abe-x2 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; + clocks = <&dpll_abe_ck>; + }; + + dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + abe_clk: clock-abe@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; + clocks = <&dpll_abe_m2x2_ck>; + ti,max-div = <4>; + reg = <0x0108>; + ti,index-power-of-two; + }; + + dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; + clocks = <&dpll_abe_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x012c>; + }; + + dpll_core_ck: clock@120 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; + clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; + reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; + }; + + dpll_core_x2_ck: clock-dpll-core-x2 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x013c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_mpu_ck: clock@160 { + #clock-cells = <0>; + compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; + clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; + reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; + }; + + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0170>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mpu_dclk_div: clock-mpu-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dclk_div"; + clocks = <&dpll_mpu_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dsp_dpll_hs_clk_div"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_dsp_byp_mux"; + clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x0240>; + }; + + dpll_dsp_ck: clock@234 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_dsp_ck"; + clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; + reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; + }; + + dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m2_ck"; + clocks = <&dpll_dsp_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0244>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; + }; + + iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x01ac>; + }; + + dpll_iva_ck: clock@1a0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; + clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; + reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; + }; + + dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m2_ck"; + clocks = <&dpll_iva_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01b0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m2_ck>; + assigned-clock-rates = <388333334>; + }; + + iva_dclk: clock-iva-dclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "iva_dclk"; + clocks = <&dpll_iva_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_gpu_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x02e4>; + }; + + dpll_gpu_ck: clock@2d8 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gpu_ck"; + clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; + reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; + assigned-clocks = <&dpll_gpu_ck>; + assigned-clock-rates = <1277000000>; + }; + + dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_gpu_m2_ck"; + clocks = <&dpll_gpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x02e8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + assigned-clocks = <&dpll_gpu_m2_ck>; + assigned-clock-rates = <425666667>; + }; + + dpll_core_m2_ck: clock-dpll-core-m2-8@130 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; + clocks = <&dpll_core_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0130>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "core_dpll_out_dclk_div"; + clocks = <&dpll_core_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_ddr_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x021c>; + }; + + dpll_ddr_ck: clock@210 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; + clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; + reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; + }; + + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0220>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_gmac_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x02b4>; + }; + + dpll_gmac_ck: clock@2a8 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gmac_ck"; + clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; + reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; + }; + + dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m2_ck"; + clocks = <&dpll_gmac_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x02b8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + video2_dclk_div: clock-video2-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "video2_dclk_div"; + clocks = <&video2_m2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video1_dclk_div: clock-video1-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "video1_dclk_div"; + clocks = <&video1_m2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + hdmi_dclk_div: clock-hdmi-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_dclk_div"; + clocks = <&hdmi_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "eve_dpll_hs_clk_div"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_eve_byp_mux"; + clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x0290>; + }; + + dpll_eve_ck: clock@284 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_eve_ck"; + clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; + reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; + }; + + dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_eve_m2_ck"; + clocks = <&dpll_eve_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0294>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + eve_dclk_div: clock-eve-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "eve_dclk_div"; + clocks = <&dpll_eve_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0140>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0144>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0154>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; + clocks = <&dpll_ddr_ck>; + }; + + dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_h11x2_ck"; + clocks = <&dpll_ddr_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0228>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_dsp_x2_ck: clock-dpll-dsp-x2 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_dsp_x2_ck"; + clocks = <&dpll_dsp_ck>; + }; + + dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m3x2_ck"; + clocks = <&dpll_dsp_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0248>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; + }; + + dpll_gmac_x2_ck: clock-dpll-gmac-x2 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_gmac_x2_ck"; + clocks = <&dpll_gmac_ck>; + }; + + dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h11x2_ck"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x02c0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h12x2_ck"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x02c4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h13x2_ck"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x02c8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m3x2_ck"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x02bc>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + gmii_m_clk_div: clock-gmii-m-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "gmii_m_clk_div"; + clocks = <&dpll_gmac_h11x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + hdmi_clk2_div: clock-hdmi-clk2-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_clk2_div"; + clocks = <&hdmi_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + hdmi_div_clk: clock-hdmi-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_div_clk"; + clocks = <&hdmi_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3_iclk_div: clock-l3-iclk-div-4@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; + ti,max-div = <2>; + ti,bit-shift = <4>; + reg = <0x0100>; + clocks = <&dpll_core_h12x2_ck>; + ti,index-power-of-two; + }; + + l4_root_clk_div: clock-l4-root-clk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l4_root_clk_div"; + clocks = <&l3_iclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + + video1_clk2_div: clock-video1-clk2-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "video1_clk2_div"; + clocks = <&video1_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video1_div_clk: clock-video1-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "video1_div_clk"; + clocks = <&video1_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video2_clk2_div: clock-video2-clk2-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "video2_clk2_div"; + clocks = <&video2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video2_div_clk: clock-video2-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "video2_div_clk"; + clocks = <&video2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dummy_ck: clock-dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; + clock-frequency = <0>; + }; +}; +&prm_clocks { + sys_clkin1: clock-sys-clkin1@110 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin1"; + clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; + }; + + abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_sys_clk_mux"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x0118>; + }; + + abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; + clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; + reg = <0x0114>; + }; + + abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; + clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; + reg = <0x010c>; + }; + + abe_24m_fclk: clock-abe-24m@11c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_24m_fclk"; + clocks = <&dpll_abe_m2x2_ck>; + reg = <0x011c>; + ti,dividers = <8>, <16>; + }; + + aess_fclk: clock-aess@178 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; + clocks = <&abe_clk>; + reg = <0x0178>; + ti,max-div = <2>; + }; + + abe_giclk_div: clock-abe-giclk-div@174 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_giclk_div"; + clocks = <&aess_fclk>; + reg = <0x0174>; + ti,max-div = <2>; + }; + + abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_lp_clk_div"; + clocks = <&dpll_abe_m2x2_ck>; + reg = <0x01d8>; + ti,dividers = <16>, <32>; + }; + + abe_sys_clk_div: clock-abe-sys-clk-div@120 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_sys_clk_div"; + clocks = <&sys_clkin1>; + reg = <0x0120>; + ti,max-div = <2>; + }; + + adc_gfclk_mux: clock-adc-gfclk-mux@1dc { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "adc_gfclk_mux"; + clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; + reg = <0x01dc>; + }; + + sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clk1_dclk_div"; + clocks = <&sys_clkin1>; + ti,max-div = <64>; + reg = <0x01c8>; + ti,index-power-of-two; + }; + + sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clk2_dclk_div"; + clocks = <&sys_clkin2>; + ti,max-div = <64>; + reg = <0x01cc>; + ti,index-power-of-two; + }; + + per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_dclk_div"; + clocks = <&dpll_abe_m2_ck>; + ti,max-div = <64>; + reg = <0x01bc>; + ti,index-power-of-two; + }; + + dsp_gclk_div: clock-dsp-gclk-div@18c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dsp_gclk_div"; + clocks = <&dpll_dsp_m2_ck>; + ti,max-div = <64>; + reg = <0x018c>; + ti,index-power-of-two; + }; + + gpu_dclk: clock-gpu-dclk@1a0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gpu_dclk"; + clocks = <&dpll_gpu_m2_ck>; + ti,max-div = <64>; + reg = <0x01a0>; + ti,index-power-of-two; + }; + + emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "emif_phy_dclk_div"; + clocks = <&dpll_ddr_m2_ck>; + ti,max-div = <64>; + reg = <0x0190>; + ti,index-power-of-two; + }; + + gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gmac_250m_dclk_div"; + clocks = <&dpll_gmac_m2_ck>; + ti,max-div = <64>; + reg = <0x019c>; + ti,index-power-of-two; + }; + + gmac_main_clk: clock-gmac-main { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "gmac_main_clk"; + clocks = <&gmac_250m_dclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + + l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3init_480m_dclk_div"; + clocks = <&dpll_usb_m2_ck>; + ti,max-div = <64>; + reg = <0x01ac>; + ti,index-power-of-two; + }; + + usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "usb_otg_dclk_div"; + clocks = <&usb_otg_clkin_ck>; + ti,max-div = <64>; + reg = <0x0184>; + ti,index-power-of-two; + }; + + sata_dclk_div: clock-sata-dclk-div@1c0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sata_dclk_div"; + clocks = <&sys_clkin1>; + ti,max-div = <64>; + reg = <0x01c0>; + ti,index-power-of-two; + }; + + pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pcie2_dclk_div"; + clocks = <&dpll_pcie_ref_m2_ck>; + ti,max-div = <64>; + reg = <0x01b8>; + ti,index-power-of-two; + }; + + pcie_dclk_div: clock-pcie-dclk-div@1b4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pcie_dclk_div"; + clocks = <&apll_pcie_m2_ck>; + ti,max-div = <64>; + reg = <0x01b4>; + ti,index-power-of-two; + }; + + emu_dclk_div: clock-emu-dclk-div@194 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "emu_dclk_div"; + clocks = <&sys_clkin1>; + ti,max-div = <64>; + reg = <0x0194>; + ti,index-power-of-two; + }; + + secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "secure_32k_dclk_div"; + clocks = <&secure_32k_clk_src_ck>; + ti,max-div = <64>; + reg = <0x01c4>; + ti,index-power-of-two; + }; + + clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux0_clk_mux"; + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; + reg = <0x0158>; + }; + + clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux1_clk_mux"; + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; + reg = <0x015c>; + }; + + clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux2_clk_mux"; + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; + reg = <0x0160>; + }; + + custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; + clocks = <&sys_clkin1>; + clock-mult = <1>; + clock-div = <2>; + }; + + eve_clk: clock-eve@180 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "eve_clk"; + clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; + reg = <0x0180>; + }; + + hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "hdmi_dpll_clk_mux"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x0164>; + }; + + mlb_clk: clock-mlb@134 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "mlb_clk"; + clocks = <&mlb_clkin_ck>; + ti,max-div = <64>; + reg = <0x0134>; + ti,index-power-of-two; + }; + + mlbp_clk: clock-mlbp@130 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "mlbp_clk"; + clocks = <&mlbp_clkin_ck>; + ti,max-div = <64>; + reg = <0x0130>; + ti,index-power-of-two; + }; + + per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_gfclk2_div"; + clocks = <&dpll_abe_m2_ck>; + ti,max-div = <64>; + reg = <0x0138>; + ti,index-power-of-two; + }; + + timer_sys_clk_div: clock-timer-sys-clk-div@144 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "timer_sys_clk_div"; + clocks = <&sys_clkin1>; + reg = <0x0144>; + ti,max-div = <2>; + }; + + video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "video1_dpll_clk_mux"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x0168>; + }; + + video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "video2_dpll_clk_mux"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x016c>; + }; + + wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; + clocks = <&sys_clkin1>, <&abe_lp_clk_div>; + reg = <0x0108>; + }; +}; + +&cm_core_clocks { + dpll_pcie_ref_ck: clock@200 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_pcie_ref_ck"; + clocks = <&sys_clkin1>, <&sys_clkin1>; + reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + }; + + dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2ldo_ck"; + clocks = <&dpll_pcie_ref_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0210>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { + compatible = "ti,mux-clock"; + clock-output-names = "apll_pcie_in_clk_mux"; + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; + #clock-cells = <0>; + reg = <0x021c 0x4>; + ti,bit-shift = <7>; + }; + + apll_pcie_ck: clock@21c { + #clock-cells = <0>; + compatible = "ti,dra7-apll-clock"; + clock-output-names = "apll_pcie_ck"; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x021c>, <0x0220>; + }; + + optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { + compatible = "ti,divider-clock"; + clock-output-names = "optfclk_pciephy_div"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x021c>; + ti,dividers = <2>, <1>; + ti,bit-shift = <8>; + ti,max-div = <2>; + }; + + apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo"; + clocks = <&apll_pcie_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo_div"; + clocks = <&apll_pcie_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + apll_pcie_m2_ck: clock-apll-pcie-m2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_m2_ck"; + clocks = <&apll_pcie_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; + clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x014c>; + }; + + dpll_per_ck: clock@140 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; + clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; + reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; + }; + + dpll_per_m2_ck: clock-dpll-per-m2-8@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_aon_dclk_div"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; + clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x018c>; + }; + + dpll_usb_ck: clock@180 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; + clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; + reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; + }; + + dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0190>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2_ck"; + clocks = <&dpll_pcie_ref_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0210>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_x2_ck: clock-dpll-per-x2 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; + clocks = <&dpll_per_ck>; + }; + + dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h13x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0160>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0164>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; + clocks = <&dpll_usb_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + func_128m_clk: clock-func-128m { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; + clocks = <&dpll_per_h11x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + func_12m_fclk: clock-func-12m-fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + func_24m_clk: clock-func-24m { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_48m_fclk: clock-func-48m-fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_96m_fclk: clock-func-96m-fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + l3init_60m_fclk: clock-l3init-60m@104 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x0104>; + ti,dividers = <1>, <8>; + }; + + clkout2_clk: clock-clkout2-8@6b0 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkout2_clk"; + clocks = <&clkoutmux2_clk_mux>; + ti,bit-shift = <8>; + reg = <0x06b0>; + }; + + l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "l3init_960m_gfclk"; + clocks = <&dpll_usb_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x06c0>; + }; + + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0640>; + }; + + usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy2_always_on_clk32k"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0688>; + }; + + usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy3_always_on_clk32k"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0698>; + }; + + gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; + ti,bit-shift = <24>; + reg = <0x1220>; + assigned-clocks = <&gpu_core_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; + }; + + gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; + ti,bit-shift = <26>; + reg = <0x1220>; + assigned-clocks = <&gpu_hyd_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; + }; + + l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3instr_ts_gclk_div"; + clocks = <&wkupaon_iclk_mux>; + ti,bit-shift = <24>; + reg = <0x0e50>; + ti,dividers = <8>, <16>, <32>; + }; + + vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "vip1_gclk_mux"; + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; + ti,bit-shift = <24>; + reg = <0x1020>; + }; + + vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "vip2_gclk_mux"; + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; + ti,bit-shift = <24>; + reg = <0x1028>; + }; + + vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "vip3_gclk_mux"; + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; + ti,bit-shift = <24>; + reg = <0x1030>; + }; +}; + +&cm_core_clockdomains { + coreaon_clkdm: clock-coreaon-clkdm { + compatible = "ti,clockdomain"; + clock-output-names = "coreaon_clkdm"; + clocks = <&dpll_usb_ck>; + }; +}; + +&scm_conf_clocks { + dss_deshdcp_clk: clock-dss-deshdcp-0@558 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_deshdcp_clk"; + clocks = <&l3_iclk_div>; + ti,bit-shift = <0>; + reg = <0x558>; + }; + + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <20>; + reg = <0x0558>; + }; + + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <21>; + reg = <0x0558>; + }; + + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <22>; + reg = <0x0558>; + }; + + sys_32k_ck: clock-sys-32k { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sys_32k_ck"; + clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; + ti,bit-shift = <8>; + reg = <0x6c4>; + }; +}; + +&cm_core_aon { + mpu_cm: clock@300 { + compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; + reg = <0x300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300 0x100>; + + mpu_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + + }; + + dsp1_cm: clock@400 { + compatible = "ti,omap4-cm"; + clock-output-names = "dsp1_cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + dsp1_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dsp1_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + + }; + + ipu_cm: clock@500 { + compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + ipu1_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "ipu1_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; + }; + + ipu_clkctrl: clock@50 { + compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; + reg = <0x50 0x34>; + #clock-cells = <2>; + }; + + }; + + dsp2_cm: clock@600 { + compatible = "ti,omap4-cm"; + clock-output-names = "dsp2_cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + dsp2_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dsp2_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + + }; + + rtc_cm: clock@700 { + compatible = "ti,omap4-cm"; + clock-output-names = "rtc_cm"; + reg = <0x700 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x60>; + + rtc_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "rtc_clkctrl"; + reg = <0x20 0x28>; + #clock-cells = <2>; + }; + }; + + vpe_cm: clock@760 { + compatible = "ti,omap4-cm"; + clock-output-names = "vpe_cm"; + reg = <0x760 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x760 0xc>; + + vpe_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "vpe_clkctrl"; + reg = <0x0 0xc>; + #clock-cells = <2>; + }; + }; + +}; + +&cm_core { + coreaon_cm: clock@600 { + compatible = "ti,omap4-cm"; + clock-output-names = "coreaon_cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + coreaon_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "coreaon_clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + l3main1_cm: clock@700 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + l3main1_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; + reg = <0x20 0x74>; + #clock-cells = <2>; + }; + + }; + + ipu2_cm: clock@900 { + compatible = "ti,omap4-cm"; + clock-output-names = "ipu2_cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + ipu2_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "ipu2_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + + }; + + dma_cm: clock@a00 { + compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + dma_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + emif_cm: clock@b00 { + compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb00 0x100>; + + emif_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + atl_cm: clock@c00 { + compatible = "ti,omap4-cm"; + clock-output-names = "atl_cm"; + reg = <0xc00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xc00 0x100>; + + atl_clkctrl: clock@0 { + compatible = "ti,clkctrl"; + clock-output-names = "atl_clkctrl"; + reg = <0x0 0x4>; + #clock-cells = <2>; + }; + }; + + l4cfg_cm: clock@d00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; + reg = <0xd00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd00 0x100>; + + l4cfg_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; + reg = <0x20 0x84>; + #clock-cells = <2>; + }; + }; + + l3instr_cm: clock@e00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; + reg = <0xe00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe00 0x100>; + + l3instr_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + iva_cm: clock@f00 { + compatible = "ti,omap4-cm"; + clock-output-names = "iva_cm"; + reg = <0xf00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xf00 0x100>; + + iva_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "iva_clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + cam_cm: clock@1000 { + compatible = "ti,omap4-cm"; + clock-output-names = "cam_cm"; + reg = <0x1000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x100>; + + cam_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "cam_clkctrl"; + reg = <0x20 0x2c>; + #clock-cells = <2>; + }; + }; + + dss_cm: clock@1100 { + compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; + reg = <0x1100 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1100 0x100>; + + dss_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + gpu_cm: clock@1200 { + compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; + reg = <0x1200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1200 0x100>; + + gpu_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3init_cm: clock@1300 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; + reg = <0x1300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1300 0x100>; + + l3init_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; + reg = <0x20 0x6c>, <0xe0 0x14>; + #clock-cells = <2>; + }; + + pcie_clkctrl: clock@b0 { + compatible = "ti,clkctrl"; + clock-output-names = "pcie_clkctrl"; + reg = <0xb0 0xc>; + #clock-cells = <2>; + }; + + gmac_clkctrl: clock@d0 { + compatible = "ti,clkctrl"; + clock-output-names = "gmac_clkctrl"; + reg = <0xd0 0x4>; + #clock-cells = <2>; + }; + + }; + + l4per_cm: clock@1700 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; + reg = <0x1700 0x300>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1700 0x300>; + + l4per_clkctrl: clock@28 { + compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; + reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; + #clock-cells = <2>; + + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + assigned-clock-parents = <&abe_24m_fclk>; + }; + + l4sec_clkctrl: clock@1a0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; + reg = <0x1a0 0x2c>; + #clock-cells = <2>; + }; + + l4per2_clkctrl: clock@c { + compatible = "ti,clkctrl"; + clock-output-names = "l4per2_clkctrl"; + reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; + #clock-cells = <2>; + }; + + l4per3_clkctrl: clock@14 { + compatible = "ti,clkctrl"; + clock-output-names = "l4per3_clkctrl"; + reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; + #clock-cells = <2>; + }; + }; + +}; + +&prm { + wkupaon_cm: clock@1800 { + compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; + reg = <0x1800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1800 0x100>; + + wkupaon_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; + reg = <0x20 0x6c>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi new file mode 100644 index 000000000000..9698801cbcfb --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common devices used in different OMAP boards + */ + +/ { + elpida_ECB240ABACN: lpddr2 { + compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts new file mode 100644 index 000000000000..c1705f6f3d10 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "logicpd-som-lv.dtsi" +#include "logicpd-som-lv-baseboard.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts new file mode 100644 index 000000000000..9dbbcc7ced7c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "logicpd-som-lv.dtsi" +#include "logicpd-som-lv-baseboard.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi new file mode 100644 index 000000000000..690f2ad50c65 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/ { + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + + sysboot2 { + label = "gpio3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ + linux,code = ; + wakeup-source; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3logic"; + ti,mcbsp = <&mcbsp2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &led_pins_wkup>; + + led1 { + label = "led1"; + gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ + linux,default-trigger = "cpu0"; + }; + + led2 { + label = "led2"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ + linux,default-trigger = "none"; + }; + }; +}; + +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vaux4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcbsp2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ + 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ + reg = <1 0 0xff>; + }; +}; + +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&video_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins1>; + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <16>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + video_reg: video_reg { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lcd0: display { + /* This isn't the exact LCD, but the timings meet spec */ + compatible = "logicpd,type28"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_pin>; + backlight = <&bl>; + enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&twl_pwm 0 5000000>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ + cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +}; + +&omap3_pmx_core { + gpio_key_pins: gpio-key-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ + >; + }; + + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ + >; + }; + + lan9221_pins: lan9221-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ + OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ + >; + }; + + lcd_enable_pin: lcd-enable-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ + >; + }; + + dss_dpi_pins1: dss-dpi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ + >; + }; +}; + +&omap3_pmx_wkup { + led_pins_wkup: led-wkup-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ + >; + }; +}; + + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi new file mode 100644 index 000000000000..c0e6b73fa472 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + wl12xx_vmmc: wl12xx_vmmc { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 3 0>; /* gpio_3 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vaux3>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb2_phy: hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_reset_pin>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ + #phy-cells = <0>; + }; + + /* fixed 26MHz oscillator */ + hfclk_26m: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f4g16abbda3w"; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + clocks = <&hfclk_26m>; + clock-names = "fck"; + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + + touchscreen: tsc2004@48 { + compatible = "ti,tsc2004"; + reg = <0x48>; + vio-supply = <&vaux1>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2004_pins>; + interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ + + touchscreen-fuzz-x = <4>; + touchscreen-fuzz-y = <7>; + touchscreen-fuzz-pressure = <2>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + touchscreen-max-pressure = <2048>; + + ti,x-plate-ohms = <280>; + ti,esd-recovery-timeout-ms = <8000>; + }; +}; + +&mmc3 { + interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; + pinctrl-0 = <&mmc3_pins &wl127x_gpio>; + pinctrl-names = "default"; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1273"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ + ref-clock-frequency = <26000000>; + }; +}; + +&usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&omap3_pmx_core { + + mmc3_pins: mm3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ + OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ + >; + }; + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ + >; + }; + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ + >; + }; + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + hsusb_otg_pins: hsusb-otg-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + + tsc2004_pins: tsc2004-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ + >; + }; +}; + +&omap3_pmx_wkup { + + hsusb2_reset_pin: hsusb1-reset-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ + >; + }; + wl127x_gpio: wl127x-gpio-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&vaux3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&twl { + twl_power: power { + compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; + ti,use_poweroff; + }; +}; + +&twl_gpio { + ti,use-leds; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts new file mode 100644 index 000000000000..eaa583fdc3d6 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "logicpd-torpedo-som.dtsi" +#include "logicpd-torpedo-baseboard.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core { + isp1763_pins: isp1763-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts new file mode 100644 index 000000000000..b5536132971f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +/* + * There are two types of 4.3" LCD, Type 15 and Type 28. + * By default, type 15 was used. This device tree file + * uses the timing for the type 28 LCD + */ + +#include "logicpd-torpedo-37xx-devkit.dts" + +&lcd0 { + compatible = "logicpd,type28"; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts new file mode 100644 index 000000000000..533ce7ce387a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "logicpd-torpedo-som.dtsi" +#include "omap-gpmc-smsc9221.dtsi" +#include "logicpd-torpedo-baseboard.dtsi" + +/ { + model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; + + wl12xx_vmmc: wl12xx_vmmc { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 29 0>; /* gpio157 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vmmc2>; + }; +}; + +/* + * Only found on the wireless SOM. For the SOM without wireless, the pins for + * MMC3 can be routed with jumpers to the second MMC slot on the devkit and + * gpio157 is not connected. So this should be OK to keep common for now, + * probably device tree overlays is the way to go with the various SOM and + * jumpering combinations for the long run. + */ +&mmc3 { + interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; + pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; + pinctrl-names = "default"; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&uart2 { + /delete-property/dma-names; + bluetooth { + compatible = "ti,wl1283-st"; + enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */ + max-speed = <3000000>; + }; +}; + +/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */ +&mt9p031_out { + pixel-clock-frequency = <90000000>; +}; + +&omap3_pmx_core { + mmc3_pins: mm3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ + >; + }; +}; + +&omap3_pmx_core2 { + mmc3_core2_pins: mmc3-core2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + >; + }; +}; + +/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ +&omap3_pmx_wkup { + isp1763_pins: isp1763-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi new file mode 100644 index 000000000000..e0caed539810 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/ { + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; + + sysboot2 { + label = "sysboot2"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ + linux,code = ; + wakeup-source; + }; + + sysboot5 { + label = "sysboot5"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ + linux,code = ; + wakeup-source; + }; + + gpio1 { + label = "gpio1"; + gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ + linux,code = ; + wakeup-source; + }; + + gpio2 { + label = "gpio2"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ + linux,code = ; + wakeup-source; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3logic"; + ti,mcbsp = <&mcbsp2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + label = "led1"; + gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ + linux,default-trigger = "cpu0"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ + linux,default-trigger = "none"; + }; + }; + + pwm10: pwm-10 { + compatible = "ti,omap-dmtimer-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + ti,timers = <&timer10>; + #pwm-cells = <3>; + ti,clock-source = <0x01>; + }; + +}; + +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vaux4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ + 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ + reg = <1 0 0xff>; + }; + + usb@6,0 { + pinctrl-names = "default"; + pinctrl-0 = <&isp1763_pins>; + compatible = "nxp,usb-isp1763"; + reg = <0x6 0x0 0xff>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host"; + bus-width = <16>; + dr_mode = "host"; + gpmc,mux-add-data = <0>; + gpmc,device-width = <2>; + gpmc,wait-pin = <0>; + gpmc,burst-length = <4>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <45>; + gpmc,cs-wr-off-ns = <45>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <45>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <25>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <45>; + gpmc,access-ns = <35>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <60>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <5>; + gpmc,wr-access-ns = <20>; + }; +}; + +&hdqw1w { + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; + + +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&vpll2>; + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins1>; + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <16>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display { + /* This isn't the exact LCD, but the timings meet spec */ + compatible = "newhaven,nhd-4.3-480272ef-atxl"; + label = "15"; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pwr_pins>; + backlight = <&bl>; + enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&pwm10 0 5000000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1_cd>; + cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +}; + +&omap3_pmx_core { + gpio_key_pins: gpio-key-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ + >; + }; + + hdq_pins: hdq-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ + >; + }; + + pwm_pins: pwm-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ + >; + }; + + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + tsc2004_pins: tsc2004-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ + >; + }; + + isp_pins: isp-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ + OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ + + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ + >; + }; + + panel_pwr_pins: panel-pwr-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ + >; + }; + + dss_dpi_pins1: dss-dpi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; +}; + +&omap3_pmx_wkup { + gpio_key_pins_wkup: gpio-key-wkup-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ + >; + }; + + lan9221_pins: lan9221-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ + >; + }; + + mmc1_cd: mmc1-cd-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ + >; + }; +}; + +&i2c2 { + mt9p031@48 { + compatible = "aptina,mt9p031"; + reg = <0x48>; + clocks = <&isp 0>; + vaa-supply = <&vaux4>; + vdd-supply = <&vaux4>; + vdd_io-supply = <&vaux4>; + port { + mt9p031_out: endpoint { + input-clock-frequency = <24000000>; + pixel-clock-frequency = <72000000>; + remote-endpoint = <&ccdc_ep>; + }; + }; + }; +}; + +&i2c3 { + touchscreen: tsc2004@48 { + compatible = "ti,tsc2004"; + reg = <0x48>; + vio-supply = <&vaux1>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2004_pins>; + interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ + + touchscreen-fuzz-x = <4>; + touchscreen-fuzz-y = <7>; + touchscreen-fuzz-pressure = <2>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + touchscreen-max-pressure = <2048>; + + ti,x-plate-ohms = <280>; + ti,esd-recovery-timeout-ms = <8000>; + }; +}; + +&mcspi1 { + at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; +}; + +&isp { + pinctrl-names = "default"; + pinctrl-0 = <&isp_pins>; + ports { + port@0 { + reg = <0>; + ccdc_ep: endpoint { + remote-endpoint = <&mt9p031_out>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; +}; + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi new file mode 100644 index 000000000000..227699890890 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + leds { + compatible = "gpio-leds"; + led-user0 { + label = "user0"; + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ + linux,default-trigger = "none"; + }; + }; + + /* fixed 26MHz oscillator */ + hfclk_26m: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; +}; + +/* The Torpedo doesn't route the USB host pins */ +&usbhshost { + status = "disabled"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f4g16abbda3w"; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + clocks = <&hfclk_26m>; + clock-names = "fck"; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + at24@50 { + compatible = "atmel,24c64"; + readonly; + reg = <0x50>; + }; +}; + +&omap3_pmx_core { + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ + >; + }; + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ + >; + }; + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + hsusb_otg_pins: hsusb-otg-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl { + twl_power: power { + compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; + ti,use_poweroff; + }; +}; + +&twl_gpio { + ti,use-leds; +}; + +&twl_keypad { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi new file mode 100644 index 000000000000..ea02fd403a9b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common CPCAP configuration used on Motorola phones + */ + +&mcspi1 { + cpcap: pmic@0 { + compatible = "motorola,cpcap", "st,6556002"; + reg = <0>; /* cs0 */ + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <9600000>; + spi-cs-high; + spi-cpol; + spi-cpha; + + cpcap_adc: adc { + compatible = "motorola,mapphone-cpcap-adc"; + interrupts-extended = <&cpcap 8 0>; + interrupt-names = "adcdone"; + #io-channel-cells = <1>; + }; + + cpcap_battery: battery { + compatible = "motorola,cpcap-battery"; + interrupts-extended = + <&cpcap 6 0>, <&cpcap 5 0>, <&cpcap 3 0>, + <&cpcap 20 0>, <&cpcap 54 0>, <&cpcap 57 0>; + interrupt-names = + "eol", "lowbph", "lowbpl", + "chrgcurr1", "battdetb", "cccal"; + io-channels = <&cpcap_adc 0>, <&cpcap_adc 1>, + <&cpcap_adc 5>, <&cpcap_adc 6>; + io-channel-names = "battdetb", "battp", + "chg_isense", "batti"; + power-supplies = <&cpcap_charger>; + }; + + cpcap_charger: charger { + compatible = "motorola,mapphone-cpcap-charger"; + interrupts-extended = + <&cpcap 13 0>, <&cpcap 12 0>, <&cpcap 29 0>, + <&cpcap 28 0>, <&cpcap 22 0>, <&cpcap 21 0>, + <&cpcap 20 0>, <&cpcap 19 0>, <&cpcap 54 0>; + interrupt-names = + "chrg_det", "rvrs_chrg", "chrg_se1b", + "se0conn", "rvrs_mode", "chrgcurr2", + "chrgcurr1", "vbusvld", "battdetb"; + mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>, + <&gpio3 23 GPIO_ACTIVE_LOW>; + io-channels = <&cpcap_adc 0>, <&cpcap_adc 1>, + <&cpcap_adc 2>, <&cpcap_adc 5>, + <&cpcap_adc 6>; + io-channel-names = "battdetb", "battp", + "vbus", "chg_isense", + "batti"; + }; + + cpcap_regulator: regulator { + compatible = "motorola,mapphone-cpcap-regulator"; + + cpcap_regulators: regulators { + }; + }; + + cpcap_audio: audio-codec { + #sound-dai-cells = <1>; + + port@0 { + cpcap_audio_codec0: endpoint { + }; + }; + port@1 { + cpcap_audio_codec1: endpoint { + }; + }; + }; + + cpcap_rtc: rtc { + compatible = "motorola,cpcap-rtc"; + + interrupt-parent = <&cpcap>; + interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>; + }; + + power_button: button { + compatible = "motorola,cpcap-pwrbutton"; + + interrupts = <23 IRQ_TYPE_NONE>; + }; + + cpcap_usb2_phy: phy { + compatible = "motorola,mapphone-cpcap-usb-phy"; + pinctrl-0 = <&usb_gpio_mux_sel1>, <&usb_gpio_mux_sel2>; + pinctrl-1 = <&usb_ulpi_pins>; + pinctrl-2 = <&usb_utmi_pins>; + pinctrl-3 = <&uart3_pins>; + pinctrl-names = "default", "ulpi", "utmi", "uart"; + #phy-cells = <0>; + interrupts-extended = + <&cpcap 15 0>, <&cpcap 14 0>, <&cpcap 28 0>, + <&cpcap 19 0>, <&cpcap 18 0>, <&cpcap 17 0>, + <&cpcap 16 0>, <&cpcap 49 0>, <&cpcap 48 0>; + interrupt-names = + "id_ground", "id_float", "se0conn", + "vbusvld", "sessvld", "sessend", + "se1", "dm", "dp"; + mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, + <&gpio1 0 GPIO_ACTIVE_HIGH>; + io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>; + io-channel-names = "vbus", "id"; + vusb-supply = <&vusb>; + }; + + led_red: led-red { + compatible = "motorola,cpcap-led-red"; + vdd-supply = <&sw5>; + label = "status-led:red"; + }; + + led_green: led-green { + compatible = "motorola,cpcap-led-green"; + vdd-supply = <&sw5>; + label = "status-led:green"; + }; + + led_blue: led-blue { + compatible = "motorola,cpcap-led-blue"; + vdd-supply = <&sw5>; + label = "status-led:blue"; + }; + + led_adl: led-adl { + compatible = "motorola,cpcap-led-adl"; + vdd-supply = <&sw5>; + label = "button-backlight"; + }; + + led_cp: led-cp { + compatible = "motorola,cpcap-led-cp"; + vdd-supply = <&sw5>; + label = "shift-key-light"; + }; + }; +}; + +&cpcap_regulators { + sw5: SW5 { + regulator-min-microvolt = <5050000>; + regulator-max-microvolt = <5050000>; + regulator-enable-ramp-delay = <50000>; + regulator-boot-on; + }; + + vcam: VCAM { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-enable-ramp-delay = <1000>; + }; + + /* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */ + vcsi: VCSI { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-always-on; + }; + + vdac: VDAC { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + }; + + vdig: VDIG { + regulator-min-microvolt = <1875000>; + regulator-max-microvolt = <1875000>; + regulator-enable-ramp-delay = <1000>; + }; + + vfuse: VFUSE { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3150000>; + regulator-enable-ramp-delay = <1000>; + }; + + vhvio: VHVIO { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-enable-ramp-delay = <1000>; + regulator-always-on; + }; + + /* Used by eMMC at mmc2 */ + vsdio: VSDIO { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-enable-ramp-delay = <1000>; + }; + + vpll: VPLL { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <100>; + }; + + vrf1: VRF1 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-enable-ramp-delay = <1000>; + }; + + vrf2: VRF2 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-enable-ramp-delay = <1000>; + }; + + vrfref: VRFREF { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2775000>; + regulator-enable-ramp-delay = <100>; + }; + + vwlan1: VWLAN1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <1000>; + }; + + /* Used by micro-SDIO at mmc1 */ + vwlan2: VWLAN2 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <1000>; + }; + + vsim: VSIM { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-enable-ramp-delay = <1000>; + }; + + vsimcard: VSIMCARD { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-enable-ramp-delay = <1000>; + }; + + vvib: VVIB { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <500>; + }; + + vusb: VUSB { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <1000>; + }; + + vaudio: VAUDIO { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-enable-ramp-delay = <1000>; + regulator-initial-mode = <0x00>; /* NORMAL */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi new file mode 100644 index 000000000000..091ba310053e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include +#include "omap443x.dtsi" +#include "motorola-cpcap-mapphone.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + aliases { + display0 = &lcd0; + display1 = &hdmi0; + }; + + /* + * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, + * then 1023 - 1024 seems to contain mbm. + */ + memory { + device_type = "memory"; + reg = <0x80000000 0x3fd00000>; /* 1021 MB */ + }; + + /* Poweroff GPIO probably connected to CPCAP */ + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff_gpio>; + pinctrl-names = "default"; + gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */ + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + pinctrl-0 = <&hdmi_hpd_gpio>; + pinctrl-names = "default"; + label = "hdmi"; + type = "d"; + + hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + + /* + * HDMI 5V regulator probably sourced from battery. Let's keep + * keep this as always enabled for HDMI to work until we've + * figured what the encoder chip is. + */ + hdmi_regulator: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */ + enable-active-high; + regulator-always-on; + }; + + /* FS USB Host PHY on port 1 for mdm6600 */ + fsusb1_phy: usb-phy@1 { + compatible = "motorola,mapphone-mdm6600"; + pinctrl-0 = <&usb_mdm6600_pins>; + pinctrl-names = "default"; + enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ + power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ + reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ + /* mode: gpio_148 gpio_149 */ + motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, + <&gpio5 21 GPIO_ACTIVE_HIGH>; + /* cmd: gpio_103 gpio_104 gpio_142 */ + motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, + <&gpio4 8 GPIO_ACTIVE_HIGH>, + <&gpio5 14 GPIO_ACTIVE_HIGH>; + /* status: gpio_52 gpio_53 gpio_55 */ + motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, + <&gpio2 21 GPIO_ACTIVE_HIGH>, + <&gpio2 23 GPIO_ACTIVE_HIGH>; + #phy-cells = <0>; + }; + + /* HS USB host TLL nop-phy on port 2 for w3glte */ + hsusb2_phy: usb-phy@2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + /* LCD regulator from sw5 source */ + lcd_regulator: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd"; + regulator-min-microvolt = <5050000>; + regulator-max-microvolt = <5050000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ + enable-active-high; + vin-supply = <&sw5>; + }; + + /* This is probably coming straight from the battery.. */ + wl12xx_vmmc: regulator-wl12xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ + startup-delay-us = <70000>; + enable-active-high; + }; + + soundcard { + compatible = "audio-graph-card"; + label = "Mapphone Audio"; + + widgets = + "Speaker", "Earpiece", + "Speaker", "Loudspeaker", + "Headphone", "Headphone Jack", + "Microphone", "Internal Mic"; + + routing = + "Earpiece", "EP", + "Loudspeaker", "SPKR", + "Headphone Jack", "HSL", + "Headphone Jack", "HSR", + "MICR", "Internal Mic"; + + dais = <&mcbsp2_port>, <&mcbsp3_port>; + }; + + pwm8: pwm-8 { + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_direction_pin>; + + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer8>; + ti,clock-source = <0x01>; + }; + + pwm9: pwm-9 { + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_enable_pin>; + + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer9>; + ti,clock-source = <0x01>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; + pwm-names = "enable", "direction"; + direction-duty-cycle-ns = <10000000>; + }; + + backlight: backlight { + compatible = "led-backlight"; + + leds = <&backlight_led>; + brightness-levels = <31 63 95 127 159 191 223 255>; + default-brightness-level = <6>; + }; +}; + +&cpu_thermal { + polling-delay = <10000>; /* milliseconds */ +}; + +&cpu_alert0 { + temperature = <80000>; /* millicelsius */ +}; + +&cpu0 { + /* + * Note that the 1.2GiHz mode is enabled for all SoC variants for + * the Motorola Android Linux v3.0.8 based kernel. + */ + operating-points = < + /* kHz uV */ + 300000 1025000 + 600000 1200000 + 800000 1313000 + 1008000 1375000 + 1200000 1375000 + >; +}; + +&dss { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + vdd-supply = <&vcsi>; + + port { + dsi1_out_ep: endpoint { + remote-endpoint = <&lcd0_in>; + lanes = <0 1 2 3 4 5>; + }; + }; + + lcd0: panel@0 { + compatible = "motorola,droid4-panel", "panel-dsi-cm"; + reg = <0>; + label = "lcd0"; + vddi-supply = <&lcd_regulator>; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ + + backlight = <&backlight>; + + width-mm = <50>; + height-mm = <89>; + rotation = <90>; + + panel-timing { + clock-frequency = <0>; /* Calculated by dsi */ + + hback-porch = <2>; + hactive = <540>; + hfront-porch = <0>; + hsync-len = <2>; + + vback-porch = <1>; + vactive = <960>; + vfront-porch = <0>; + vsync-len = <1>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd0_in: endpoint { + remote-endpoint = <&dsi1_out_ep>; + }; + }; + }; +}; + +&hdmi { + status = "okay"; + pinctrl-0 = <&dss_hdmi_pins>; + pinctrl-names = "default"; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + lanes = <1 0 3 2 5 4 7 6>; + }; + }; +}; + +/* Battery NVRAM on 1-wire handled by w1_ds250x driver */ +&hdqw1w { + pinctrl-0 = <&hdq_pins>; + pinctrl-names = "default"; + ti,mode = "1w"; +}; + +&i2c1 { + tmp105@48 { + compatible = "ti,tmp105"; + reg = <0x48>; + pinctrl-0 = <&tmp105_irq>; + pinctrl-names = "default"; + /* kpd_row0.gpio_178 */ + interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING + &omap4_pmx_core 0x14e>; + interrupt-names = "irq", "wakeup"; + wakeup-source; + }; +}; + +&mmc1 { + vmmc-supply = <&vwlan2>; + bus-width = <4>; + cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */ +}; + +&mmc2 { + vmmc-supply = <&vsdio>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + vmmc-supply = <&wl12xx_vmmc>; + /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0xde>; + interrupt-names = "irq", "wakeup"; + non-removable; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1285"; + reg = <2>; + /* gpio_100 with gpmc_wait2 pad as wakeirq */ + interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, + <&omap4_pmx_core 0x4e>; + interrupt-names = "irq", "wakeup"; + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&i2c2 { + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; /* gpio173 */ + + /* gpio_183 with sys_nirq2 pad as wakeup */ + interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, + <&omap4_pmx_core 0x160>; + interrupt-names = "irq", "wakeup"; + wakeup-source; + }; + + isl29030@44 { + compatible = "isil,isl29030"; + reg = <0x44>; + + pinctrl-names = "default"; + pinctrl-0 = <&als_proximity_pins>; + + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ + }; +}; + +&omap4_pmx_core { + + /* hdmi_hpd.gpio_63 */ + hdmi_hpd_gpio: hdmi-hpd-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) + >; + }; + + hdq_pins: hdq-pins { + pinctrl-single,pins = < + /* 0x4a100120 hdq_sio.hdq_sio aa27 */ + OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) + >; + }; + + /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) + >; + }; + + /* + * Android uses PIN_OFF_INPUT_PULLDOWN | PIN_INPUT_PULLUP | MUX_MODE3 + * for gpio_100, but the internal pull makes wlan flakey on some + * devices. Off mode value should be tested if we have off mode working + * later on. + */ + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + /* 0x4a10008e gpmc_wait2.gpio_100 d23 */ + OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3) + + /* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */ + OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */ + OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */ + OMAP4_IOPAD(0x118, PIN_INPUT | MUX_MODE1) + + /* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */ + OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */ + OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1) + >; + }; + + /* gpmc_ncs0.gpio_50 */ + poweroff_gpio: poweroff-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) + >; + }; + + /* kpd_row0.gpio_178 */ + tmp105_irq: tmp105-irq-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + usb_gpio_mux_sel1: usb-gpio-mux-sel1-pins { + /* gpio_60 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) + >; + }; + + touchscreen_pins: touchscreen-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) + OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + als_proximity_pins: als-proximity-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + usb_mdm6600_pins: usb-mdm6600-pins { + pinctrl-single,pins = < + /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) + + /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ + OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) + + /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ + OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) + + /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ + OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) + + /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ + OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) + + /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ + OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) + + /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) + + /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ + OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) + + /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ + OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) + + /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ + OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) + + /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) + >; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + /* usb0_otg_dp and usb0_otg_dm */ + usb_utmi_pins: usb-utmi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; + + /* + * Note that the v3.0.8 stock userspace dynamically remuxes uart1 + * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 + * when not used. If needed, we can add rts pin remux later based + * on power measurements. + */ + uart1_pins: uart1-pins { + pinctrl-single,pins = < + /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ + OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ + OMAP4_IOPAD(0x13e, MUX_MODE1) + + /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ + OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) + + /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ + OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) + >; + }; + + /* uart3_tx_irtx and uart3_rx_irrx */ + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, MUX_MODE2) + OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ + OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ + OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ + OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ + >; + }; + + mcbsp3_pins: mcbsp3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ + OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ + OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ + OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ + >; + }; + + vibrator_direction_pin: vibrator-direction-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ + >; + }; + + vibrator_enable_pin: vibrator-enable-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ + >; + }; +}; + +&omap4_pmx_wkup { + usb_gpio_mux_sel2: usb-gpio-mux-sel2-pins { + /* gpio_wk0 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +/* RNG is used by secure mode and not accessible */ +&rng_target { + status = "disabled"; +}; + +/* Configure pwm clock source for timers 8 & 9 */ +&timer8 { + assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; + assigned-clock-parents = <&sys_clkin_ck>; +}; + +&timer9 { + assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; + assigned-clock-parents = <&sys_clkin_ck>; +}; + +/* + * The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149 + * for wake-up events for both the USB PHY and the UART. We can use gpio_149 + * pad as the shared wakeirq for the UART rather than the RX or CTS pad as we + * have gpio_149 trigger before the UART transfer starts. + */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x110>; + uart-has-rtscts; + current-speed = <115200>; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x17c>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + bluetooth { + compatible = "ti,wl1285-st"; + enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ + max-speed = <3686400>; + }; +}; + +&usbhsohci { + phys = <&fsusb1_phy>; + phy-names = "usb"; +}; + +&usbhsehci { + phys = <&hsusb2_phy>; +}; + +&usbhshost { + port1-mode = "ohci-phy-4pin-dpdm"; + port2-mode = "ehci-tll"; +}; + +/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + + /* + * Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4. + * VBUS Regulator Main Characteristics". Binding uses 2 mA units. + */ + power = <150>; +}; + +&i2c4 { + ak8975: magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */ + + rotation-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + }; +}; + +&mcbsp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; + + mcbsp2_port: port { + cpu_dai2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&cpcap_audio_codec0>; + frame-master = <&cpcap_audio_codec0>; + bitclock-master = <&cpcap_audio_codec0>; + }; + }; +}; + +&mcbsp3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; + status = "okay"; + + mcbsp3_port: port { + cpu_dai3: endpoint { + dai-format = "dsp_a"; + frame-master = <&cpcap_audio_codec1>; + bitclock-master = <&cpcap_audio_codec1>; + remote-endpoint = <&cpcap_audio_codec1>; + }; + }; +}; + +&cpcap_audio_codec0 { + remote-endpoint = <&cpu_dai2>; +}; + +&cpcap_audio_codec1 { + remote-endpoint = <&cpu_dai3>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi new file mode 100644 index 000000000000..3046ec572632 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common file for GPMC connected smsc911x on omaps + * + * Note that the board specifc DTS file needs to specify + * ranges, pinctrl, reg, interrupt parent and interrupts. + */ + +/ { + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&gpmc { + ethernet@gpmc { + compatible = "smsc,lan9221", "smsc,lan9115"; + bank-width = <2>; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <150>; + gpmc,cs-wr-off-ns = <150>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <140>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <140>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <120>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <75>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi new file mode 100644 index 000000000000..bc8961f3690f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common file for GPMC connected smsc9221 on omaps + * + * Compared to smsc911x, smsc9221 (and others like smsc9217 + * or smsc 9218) has faster timings, leading to higher + * bandwidth. + * + * Note that the board specifc DTS file needs to specify + * ranges, pinctrl, reg, interrupt parent and interrupts. + */ + +/ { + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&gpmc { + ethernet@gpmc { + compatible = "smsc,lan9221","smsc,lan9115"; + bank-width = <2>; + + gpmc,mux-add-data = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <42>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <42>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <36>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <54>; + gpmc,access-ns = <36>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wr-data-mux-bus-ns = <18>; + gpmc,wr-access-ns = <42>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi b/arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi new file mode 100644 index 000000000000..8adc0ef01f6c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common features on the Zoom debug board + */ + +#include "omap-gpmc-smsc911x.dtsi" + +&gpmc { + ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ + <7 0 0x2c000000 0x01000000>; + + /* + * Four port TL16CP754C serial port on GPMC, + * they probably share the same GPIO IRQ + * REVISIT: Add timing support from slls644g.pdf + */ + serial@3,0 { + compatible = "ns16550a"; + reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <1>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <155>; + gpmc,cs-wr-off-ns = <155>; + gpmc,adv-on-ns = <15>; + gpmc,adv-rd-off-ns = <40>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <145>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <145>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <145>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <20>; + gpmc,cycle2cycle-delay-ns = <20>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <45>; + gpmc,wr-access-ns = <145>; + }; + serial@3,1 { + compatible = "ns16550a"; + reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + serial@3,2 { + compatible = "ns16550a"; + reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + serial@3,3 { + compatible = "ns16550a"; + reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + ethernet@gpmc { + reg = <7 0 0xff>; + interrupt-parent = <&gpio5>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2.dtsi b/arch/arm/boot/dts/ti/omap/omap2.dtsi new file mode 100644 index 000000000000..afabb36a8ac1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2.dtsi @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP2 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +/ { + compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &i2c1; + i2c1 = &i2c2; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm1136jf-s"; + device_type = "cpu"; + }; + }; + + pmu { + compatible = "arm,arm1136-pmu"; + interrupts = <3>; + }; + + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap2-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + aes: aes@480a6000 { + compatible = "ti,omap2-aes"; + ti,hwmods = "aes"; + reg = <0x480a6000 0x50>; + dmas = <&sdma 9 &sdma 10>; + dma-names = "tx", "rx"; + }; + + hdq1w: 1w@480b2000 { + compatible = "ti,omap2420-1w"; + ti,hwmods = "hdq1w"; + reg = <0x480b2000 0x1000>; + interrupts = <58>; + }; + + intc: interrupt-controller@1 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x480FE000 0x1000>; + }; + + target-module@48056000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x48056000 0x4>, + <0x4805602c 0x4>, + <0x48056028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,syss-mask = <1>; + clocks = <&core_l3_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48056000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap2420-sdma", "ti,omap-sdma"; + reg = <0 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <64>; + }; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap2-i2c"; + ti,hwmods = "i2c1"; + reg = <0x48070000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <56>; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap2-i2c"; + ti,hwmods = "i2c2"; + reg = <0x48072000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <57>; + }; + + mcspi1: spi@48098000 { + compatible = "ti,omap2-mcspi"; + ti,hwmods = "mcspi1"; + reg = <0x48098000 0x100>; + interrupts = <65>; + dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 + &sdma 39 &sdma 40 &sdma 41 &sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mcspi2: spi@4809a000 { + compatible = "ti,omap2-mcspi"; + ti,hwmods = "mcspi2"; + reg = <0x4809a000 0x100>; + interrupts = <66>; + dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + rng: rng@480a0000 { + compatible = "ti,omap2-rng"; + ti,hwmods = "rng"; + reg = <0x480a0000 0x50>; + interrupts = <52>; + }; + + sham: sham@480a4000 { + compatible = "ti,omap2-sham"; + ti,hwmods = "sham"; + reg = <0x480a4000 0x64>; + interrupts = <51>; + dmas = <&sdma 13>; + dma-names = "rx"; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart1"; + reg = <0x4806a000 0x2000>; + interrupts = <72>; + dmas = <&sdma 49 &sdma 50>; + dma-names = "tx", "rx"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart2"; + reg = <0x4806c000 0x400>; + interrupts = <73>; + dmas = <&sdma 51 &sdma 52>; + dma-names = "tx", "rx"; + clock-frequency = <48000000>; + }; + + uart3: serial@4806e000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart3"; + reg = <0x4806e000 0x400>; + interrupts = <74>; + dmas = <&sdma 53 &sdma 54>; + dma-names = "tx", "rx"; + clock-frequency = <48000000>; + }; + + timer2_target: target-module@4802a000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x4802a000 0x4>, + <0x4802a010 0x4>, + <0x4802a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802a000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; + }; + + timer3: timer@48078000 { + compatible = "ti,omap2420-timer"; + reg = <0x48078000 0x400>; + interrupts = <39>; + ti,hwmods = "timer3"; + }; + + timer4: timer@4807a000 { + compatible = "ti,omap2420-timer"; + reg = <0x4807a000 0x400>; + interrupts = <40>; + ti,hwmods = "timer4"; + }; + + timer5: timer@4807c000 { + compatible = "ti,omap2420-timer"; + reg = <0x4807c000 0x400>; + interrupts = <41>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4807e000 { + compatible = "ti,omap2420-timer"; + reg = <0x4807e000 0x400>; + interrupts = <42>; + ti,hwmods = "timer6"; + ti,timer-dsp; + }; + + timer7: timer@48080000 { + compatible = "ti,omap2420-timer"; + reg = <0x48080000 0x400>; + interrupts = <43>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@48082000 { + compatible = "ti,omap2420-timer"; + reg = <0x48082000 0x400>; + interrupts = <44>; + ti,hwmods = "timer8"; + ti,timer-dsp; + }; + + timer9: timer@48084000 { + compatible = "ti,omap2420-timer"; + reg = <0x48084000 0x400>; + interrupts = <45>; + ti,hwmods = "timer9"; + ti,timer-pwm; + }; + + timer10: timer@48086000 { + compatible = "ti,omap2420-timer"; + reg = <0x48086000 0x400>; + interrupts = <46>; + ti,hwmods = "timer10"; + ti,timer-pwm; + }; + + timer11: timer@48088000 { + compatible = "ti,omap2420-timer"; + reg = <0x48088000 0x400>; + interrupts = <47>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; + + timer12: timer@4808a000 { + compatible = "ti,omap2420-timer"; + reg = <0x4808a000 0x400>; + interrupts = <48>; + ti,hwmods = "timer12"; + ti,timer-pwm; + }; + + dss: dss@48050000 { + compatible = "ti,omap2-dss"; + reg = <0x48050000 0x400>; + status = "disabled"; + ti,hwmods = "dss_core"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@48050400 { + compatible = "ti,omap2-dispc"; + reg = <0x48050400 0x400>; + interrupts = <25>; + ti,hwmods = "dss_dispc"; + }; + + rfbi: encoder@48050800 { + compatible = "ti,omap2-rfbi"; + reg = <0x48050800 0x400>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + }; + + venc: encoder@48050c00 { + compatible = "ti,omap2-venc"; + reg = <0x48050c00 0x400>; + status = "disabled"; + ti,hwmods = "dss_venc"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi new file mode 100644 index 000000000000..00a7a199a91c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP2420 clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + */ + +&prcm_clocks { + sys_clkout2_src_gate: sys_clkout2_src_gate@70 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <15>; + reg = <0x0070>; + }; + + sys_clkout2_src_mux: sys_clkout2_src_mux@70 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; + ti,bit-shift = <8>; + reg = <0x0070>; + }; + + sys_clkout2_src: sys_clkout2_src { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; + }; + + sys_clkout2: sys_clkout2@70 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkout2_src>; + ti,bit-shift = <11>; + ti,max-div = <64>; + reg = <0x0070>; + ti,index-power-of-two; + }; + + dsp_gate_ick: dsp_gate_ick@810 { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <1>; + reg = <0x0810>; + }; + + dsp_div_ick: dsp_div_ick@840 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0840>; + ti,index-starts-at-one; + }; + + dsp_ick: dsp_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dsp_gate_ick>, <&dsp_div_ick>; + }; + + iva1_gate_ifck: iva1_gate_ifck@800 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <10>; + reg = <0x0800>; + }; + + iva1_div_ifck: iva1_div_ifck@840 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <8>; + reg = <0x0840>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; + }; + + iva1_ifck: iva1_ifck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; + }; + + iva1_ifck_div: iva1_ifck_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&iva1_ifck>; + clock-mult = <1>; + clock-div = <2>; + }; + + iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&iva1_ifck_div>; + ti,bit-shift = <8>; + reg = <0x0800>; + }; + + wdt3_ick: wdt3_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <28>; + reg = <0x0210>; + }; + + wdt3_fck: wdt3_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <28>; + reg = <0x0200>; + }; + + mmc_ick: mmc_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <26>; + reg = <0x0210>; + }; + + mmc_fck: mmc_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <26>; + reg = <0x0200>; + }; + + eac_ick: eac_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <24>; + reg = <0x0210>; + }; + + eac_fck: eac_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <24>; + reg = <0x0200>; + }; + + i2c1_fck: i2c1_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <19>; + reg = <0x0200>; + }; + + i2c2_fck: i2c2_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <20>; + reg = <0x0200>; + }; + + vlynq_ick: vlynq_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <3>; + reg = <0x0210>; + }; + + vlynq_gate_fck: vlynq_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <3>; + reg = <0x0200>; + }; + + core_d18_ck: core_d18_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <18>; + }; + + vlynq_mux_fck: vlynq_mux_fck@240 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; + ti,bit-shift = <15>; + reg = <0x0240>; + }; + + vlynq_fck: vlynq_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; + }; +}; + +&prcm_clockdomains { + gfx_clkdm: gfx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_ick>; + }; + + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, + <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, + <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; + }; + + iva1_clkdm: iva1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&iva1_mpu_int_ifck>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_ick>, <&dss_54m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, + <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, + <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, + <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, + <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, + <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, + <&uart3_ick>, <&uart3_fck>, <&cam_ick>, + <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, + <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, + <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, + <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, + <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, + <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, + <&pka_ick>; + }; +}; + +&func_96m_ck { + compatible = "fixed-factor-clock"; + clocks = <&apll96_ck>; + clock-mult = <1>; + clock-div = <1>; +}; + +&dsp_div_fck { + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; +}; + +&ssi_ssr_sst_div_fck { + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts new file mode 100644 index 000000000000..5acf5dd87c59 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap2420.dtsi" + +/ { + model = "TI OMAP2420 H4 board"; + compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; /* 64 MB */ + }; +}; + +&gpmc { + ranges = <0 0 0x08000000 0x04000000>; + + nor@0,0 { + compatible = "cfi-flash"; + linux,mtd-name = "intel,ge28f256l18b85"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x04000000>; + bank-width = <2>; + + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <160>; + gpmc,cs-wr-off-ns = <160>; + gpmc,adv-on-ns = <20>; + gpmc,adv-rd-off-ns = <50>; + gpmc,adv-wr-off-ns = <50>; + gpmc,oe-on-ns = <60>; + gpmc,oe-off-ns = <120>; + gpmc,we-on-ns = <60>; + gpmc,we-off-ns = <120>; + gpmc,rd-cycle-ns = <170>; + gpmc,wr-cycle-ns = <170>; + gpmc,access-ns = <150>; + gpmc,page-burst-access-ns = <10>; + + partition@0 { + label = "bootloader"; + reg = <0 0x20000>; + }; + partition@20000 { + label = "params"; + reg = <0x20000 0x20000>; + }; + partition@40000 { + label = "kernel"; + reg = <0x40000 0x200000>; + }; + partition@240000 { + label = "file-system"; + reg = <0x240000 0x3dc0000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts new file mode 100644 index 000000000000..f06d767e818b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "omap2420-n8x0-common.dtsi" + +/ { + model = "Nokia N800"; + compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts new file mode 100644 index 000000000000..ac9acbd609b6 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "omap2420-n8x0-common.dtsi" + +/ { + model = "Nokia N810 WiMax"; + compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts new file mode 100644 index 000000000000..3bf8175d85a8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "omap2420-n8x0-common.dtsi" + +/ { + model = "Nokia N810"; + compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; + + vio_ape: vio_ape { + compatible = "regulator-fixed"; + regulator-name = "vio_ape"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + v28_aic: v28_aic { + compatible = "regulator-fixed"; + regulator-name = "v28_aic"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; +}; + +&omap2420_pmx { + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */ + OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */ + OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */ + OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ + >; + }; + + aic33_pins: aic33-pins { + pinctrl-single,pins = < + OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ + OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ + >; + }; +}; + +&i2c2 { + aic33@18 { + compatible = "ti,tlv320aic33"; + reg = <0x18>; + + pinctrl-names = "default"; + pinctrl-0 = <&aic33_pins>; + + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ + + ai3x-gpio-func = < + 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */ + 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ + >; + ai3x-micbias-vg = <1>; /* 2V */ + + AVDD-supply = <&v28_aic>; + DRVDD-supply = <&v28_aic>; + IOVDD-supply = <&vio_ape>; + DVDD-supply = <&vio_ape>; + + assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>; + assigned-clock-parents = <&func_96m_ck>; + assigned-clock-rates = <0>, <12000000>; + }; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi new file mode 100644 index 000000000000..63b0b4921e4e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "omap2420.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + chosen { + stdout-path = &uart3; + }; + + ocp { + i2c0 { + compatible = "i2c-cbus-gpio"; + gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */ + &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */ + &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */ + >; + #address-cells = <1>; + #size-cells = <0>; + retu: retu@1 { + compatible = "nokia,retu"; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + reg = <0x1>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + pmic@72 { + compatible = "menelaus"; + reg = <0x72>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ + + /* gpio-irq for dma: 26 */ + + onenand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + + gpmc,sync-read; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <127>; + gpmc,cs-wr-off-ns = <109>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <18>; + gpmc,oe-on-ns = <27>; + gpmc,oe-off-ns = <127>; + gpmc,we-on-ns = <27>; + gpmc,we-off-ns = <72>; + gpmc,rd-cycle-ns = <145>; + gpmc,wr-cycle-ns = <136>; + gpmc,access-ns = <118>; + gpmc,page-burst-access-ns = <27>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <9>; + gpmc,sync-clk-ps = <27000>; + + /* MTD partition table corresponding to old board-n8x0 file. */ + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@1 { + label = "config"; + reg = <0x00020000 0x00060000>; + }; + partition@2 { + label = "kernel"; + reg = <0x00080000 0x00200000>; + }; + partition@3 { + label = "initfs"; + reg = <0x00280000 0x00400000>; + }; + partition@4 { + label = "rootfs"; + reg = <0x00680000 0x0f980000>; + }; + partition@5 { + label = "omap2-onenand"; + reg = <0x00000000 0x10000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2420.dtsi b/arch/arm/boot/dts/ti/omap/omap2420.dtsi new file mode 100644 index 000000000000..821da51cb870 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2420.dtsi @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP2420 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "omap2.dtsi" + +/ { + compatible = "ti,omap2420", "ti,omap2"; + + ocp { + l4: l4@48000000 { + compatible = "ti,omap2-l4", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; + + prcm: prcm@8000 { + compatible = "ti,omap2-prcm"; + reg = <0x8000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@0 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + ranges = <0 0x0 0x1000>; + + omap2420_pmx: pinmux@30 { + compatible = "ti,omap2420-padconf", + "pinctrl-single"; + reg = <0x30 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + }; + + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; + }; + }; + + gpio1: gpio@48018000 { + compatible = "ti,omap2-gpio"; + reg = <0x48018000 0x200>; + interrupts = <29>; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@4801a000 { + compatible = "ti,omap2-gpio"; + reg = <0x4801a000 0x200>; + interrupts = <30>; + ti,hwmods = "gpio2"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@4801c000 { + compatible = "ti,omap2-gpio"; + reg = <0x4801c000 0x200>; + interrupts = <31>; + ti,hwmods = "gpio3"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@4801e000 { + compatible = "ti,omap2-gpio"; + reg = <0x4801e000 0x200>; + interrupts = <32>; + ti,hwmods = "gpio4"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpmc: gpmc@6800a000 { + compatible = "ti,omap2420-gpmc"; + reg = <0x6800a000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + ti,hwmods = "gpmc"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + ti,hwmods = "mcbsp1"; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + ti,hwmods = "mcbsp2"; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + msdi1: mmc@4809c000 { + compatible = "ti,omap2420-mmc"; + ti,hwmods = "msdi1"; + reg = <0x4809c000 0x80>; + interrupts = <83>; + dmas = <&sdma 61 &sdma 62>; + dma-names = "tx", "rx"; + }; + + mailbox: mailbox@48094000 { + compatible = "ti,omap2-mailbox"; + reg = <0x48094000 0x200>; + interrupts = <26>, <34>; + ti,hwmods = "mailbox"; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <6>; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_iva: mbox-iva { + ti,mbox-tx = <2 1 3>; + ti,mbox-rx = <3 1 3>; + }; + }; + + timer1_target: target-module@48028000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48028000 0x4>, + <0x48028010 0x4>, + <0x48028014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48028000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; + }; + + wd_timer2: wdt@48022000 { + compatible = "ti,omap2-wdt"; + ti,hwmods = "wd_timer2"; + reg = <0x48022000 0x80>; + }; + }; +}; + +&i2c1 { + compatible = "ti,omap2420-i2c"; +}; + +&i2c2 { + compatible = "ti,omap2420-i2c"; +}; + +#include "omap24xx-clocks.dtsi" +#include "omap2420-clocks.dtsi" + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi new file mode 100644 index 000000000000..4e5ab5189476 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP2430 clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + */ + +&scm_clocks { + mcbsp3_mux_fck: mcbsp3_mux_fck@78 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + reg = <0x78>; + }; + + mcbsp3_fck: mcbsp3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; + }; + + mcbsp4_mux_fck: mcbsp4_mux_fck@78 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x78>; + }; + + mcbsp4_fck: mcbsp4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; + }; + + mcbsp5_mux_fck: mcbsp5_mux_fck@78 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x78>; + }; + + mcbsp5_fck: mcbsp5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; + }; +}; + +&prcm_clocks { + iva2_1_gate_ick: iva2_1_gate_ick@800 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <0>; + reg = <0x0800>; + }; + + iva2_1_div_ick: iva2_1_div_ick@840 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0840>; + ti,index-starts-at-one; + }; + + iva2_1_ick: iva2_1_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; + }; + + mdm_gate_ick: mdm_gate_ick@c10 { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&core_ck>; + ti,bit-shift = <0>; + reg = <0x0c10>; + }; + + mdm_div_ick: mdm_div_ick@c40 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + reg = <0x0c40>; + ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; + }; + + mdm_ick: mdm_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mdm_gate_ick>, <&mdm_div_ick>; + }; + + mdm_osc_ck: mdm_osc_ck@c00 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&osc_ck>; + ti,bit-shift = <1>; + reg = <0x0c00>; + }; + + mcbsp3_ick: mcbsp3_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <3>; + reg = <0x0214>; + }; + + mcbsp3_gate_fck: mcbsp3_gate_fck@204 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <3>; + reg = <0x0204>; + }; + + mcbsp4_ick: mcbsp4_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <4>; + reg = <0x0214>; + }; + + mcbsp4_gate_fck: mcbsp4_gate_fck@204 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x0204>; + }; + + mcbsp5_ick: mcbsp5_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <5>; + reg = <0x0214>; + }; + + mcbsp5_gate_fck: mcbsp5_gate_fck@204 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <5>; + reg = <0x0204>; + }; + + mcspi3_ick: mcspi3_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <9>; + reg = <0x0214>; + }; + + mcspi3_fck: mcspi3_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <9>; + reg = <0x0204>; + }; + + icr_ick: icr_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x0410>; + }; + + i2chs1_fck: i2chs1_fck@204 { + #clock-cells = <0>; + compatible = "ti,omap2430-interface-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <19>; + reg = <0x0204>; + }; + + i2chs2_fck: i2chs2_fck@204 { + #clock-cells = <0>; + compatible = "ti,omap2430-interface-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <20>; + reg = <0x0204>; + }; + + usbhs_ick: usbhs_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <6>; + reg = <0x0214>; + }; + + mmchs1_ick: mmchs1_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <7>; + reg = <0x0214>; + }; + + mmchs1_fck: mmchs1_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <7>; + reg = <0x0204>; + }; + + mmchs2_ick: mmchs2_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <8>; + reg = <0x0214>; + }; + + mmchs2_fck: mmchs2_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <8>; + reg = <0x0204>; + }; + + gpio5_ick: gpio5_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <10>; + reg = <0x0214>; + }; + + gpio5_fck: gpio5_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <10>; + reg = <0x0204>; + }; + + mdm_intc_ick: mdm_intc_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <11>; + reg = <0x0214>; + }; + + mmchsdb1_fck: mmchsdb1_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <16>; + reg = <0x0204>; + }; + + mmchsdb2_fck: mmchsdb2_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <17>; + reg = <0x0204>; + }; +}; + +&prcm_clockdomains { + gfx_clkdm: gfx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_ick>; + }; + + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, + <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, + <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, + <&icr_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_ick>, <&dss_54m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, + <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, + <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, + <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, + <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, + <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, + <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, + <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, + <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, + <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, + <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, + <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, + <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, + <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, + <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, + <&mmchsdb2_fck>; + }; + + mdm_clkdm: mdm_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mdm_osc_ck>; + }; +}; + +&func_96m_ck { + compatible = "ti,mux-clock"; + clocks = <&apll96_ck>, <&alt_ck>; + ti,bit-shift = <4>; + reg = <0x0540>; +}; + +&dsp_div_fck { + ti,max-div = <4>; + ti,index-starts-at-one; +}; + +&ssi_ssr_sst_div_fck { + ti,max-div = <5>; + ti,index-starts-at-one; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts new file mode 100644 index 000000000000..207070677e3a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap2430.dtsi" + +/ { + model = "TI OMAP2430 SDP"; + compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; +}; + +&i2c2 { + clock-frequency = <100000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + }; +}; + +#include "twl4030.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +&gpmc { + ranges = <5 0 0x08000000 0x01000000>; + ethernet@gpmc { + compatible = "smsc,lan91c94"; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ + reg = <5 0x300 0xf>; + bank-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,mux-add-data = <2>; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cs-on-ns = <6>; + gpmc,cs-rd-off-ns = <187>; + gpmc,cs-wr-off-ns = <187>; + gpmc,adv-on-ns = <18>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <60>; + gpmc,oe-off-ns = <169>; + gpmc,we-on-ns = <66>; + gpmc,we-off-ns = <169>; + gpmc,rd-cycle-ns = <187>; + gpmc,wr-cycle-ns = <187>; + gpmc,access-ns = <187>; + gpmc,page-burst-access-ns = <24>; + gpmc,bus-turnaround-ns = <24>; + gpmc,cycle2cycle-delay-ns = <24>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi new file mode 100644 index 000000000000..b9a9e6e45266 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap2430.dtsi @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP243x SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "omap2.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2"; + + ocp { + l4_wkup: l4_wkup@49000000 { + compatible = "ti,omap2-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x49000000 0x31000>; + + prcm: prcm@6000 { + compatible = "ti,omap2-prcm"; + reg = <0x6000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@2000 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + ranges = <0 0x2000 0x1000>; + + omap2430_pmx: pinmux@30 { + compatible = "ti,omap2430-padconf", + "pinctrl-single"; + reg = <0x30 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon", + "simple-bus"; + reg = <0x270 0x240>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x270 0x240>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + pbias_regulator: pbias_regulator@230 { + compatible = "ti,pbias-omap2", "ti,pbias-omap"; + reg = <0x230 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + scm_clockdomains: clockdomains { + }; + }; + + target-module@20000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; + }; + }; + + gpio1: gpio@4900c000 { + compatible = "ti,omap2-gpio"; + reg = <0x4900c000 0x200>; + interrupts = <29>; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@4900e000 { + compatible = "ti,omap2-gpio"; + reg = <0x4900e000 0x200>; + interrupts = <30>; + ti,hwmods = "gpio2"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@49010000 { + compatible = "ti,omap2-gpio"; + reg = <0x49010000 0x200>; + interrupts = <31>; + ti,hwmods = "gpio3"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@49012000 { + compatible = "ti,omap2-gpio"; + reg = <0x49012000 0x200>; + interrupts = <32>; + ti,hwmods = "gpio4"; + ti,gpio-always-on; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio5: gpio@480b6000 { + compatible = "ti,omap2-gpio"; + reg = <0x480b6000 0x200>; + interrupts = <33>; + ti,hwmods = "gpio5"; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpmc: gpmc@6e000000 { + compatible = "ti,omap2430-gpmc"; + reg = <0x6e000000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + ti,hwmods = "gpmc"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <64>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>, /* RX interrupt */ + <61>; /* RX overflow interrupt */ + interrupt-names = "common", "tx", "rx", "rx_overflow"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mcbsp3: mcbsp@4808c000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808c000 0xff>; + reg-names = "mpu"; + interrupts = <17>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mcbsp4: mcbsp@4808e000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808e000 0xff>; + reg-names = "mpu"; + interrupts = <18>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <19>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + dmas = <&sdma 21>, + <&sdma 22>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap2-hsmmc"; + reg = <0x4809c000 0x200>; + interrupts = <83>; + ti,hwmods = "mmc1"; + ti,dual-volt; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap2-hsmmc"; + reg = <0x480b4000 0x200>; + interrupts = <86>; + ti,hwmods = "mmc2"; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + + mailbox: mailbox@48094000 { + compatible = "ti,omap2-mailbox"; + reg = <0x48094000 0x200>; + interrupts = <26>; + ti,hwmods = "mailbox"; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <6>; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + }; + + timer1_target: target-module@49018000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49018000 0x4>, + <0x49018010 0x4>, + <0x49018014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49018000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; + }; + + mcspi3: spi@480b8000 { + compatible = "ti,omap2-mcspi"; + ti,hwmods = "mcspi3"; + reg = <0x480b8000 0x100>; + interrupts = <91>; + dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + usb_otg_hs: usb_otg_hs@480ac000 { + compatible = "ti,omap2-musb"; + ti,hwmods = "usb_otg_hs"; + reg = <0x480ac000 0x1000>; + interrupts = <93>; + }; + + wd_timer2: wdt@49016000 { + compatible = "ti,omap2-wdt"; + ti,hwmods = "wd_timer2"; + reg = <0x49016000 0x80>; + }; + }; +}; + +&sdma { + compatible = "ti,omap2430-sdma", "ti,omap-sdma"; +}; + +&i2c1 { + compatible = "ti,omap2430-i2c"; +}; + +&i2c2 { + compatible = "ti,omap2430-i2c"; +}; + +#include "omap24xx-clocks.dtsi" +#include "omap2430-clocks.dtsi" + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi new file mode 100644 index 000000000000..07af87edf0e2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi @@ -0,0 +1,1241 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP24xx clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + */ +&scm_clocks { + mcbsp1_mux_fck: mcbsp1_mux_fck@4 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x4>; + }; + + mcbsp1_fck: mcbsp1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; + }; + + mcbsp2_mux_fck: mcbsp2_mux_fck@4 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + reg = <0x4>; + }; + + mcbsp2_fck: mcbsp2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; + }; +}; + +&prcm_clocks { + func_32k_ck: func_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + secure_32k_ck: secure_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12m_ck: virt_12m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13m_ck: virt_13m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26m_ck: virt_26m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + aplls_clkin_ck: aplls_clkin_ck@540 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; + ti,bit-shift = <23>; + reg = <0x0540>; + }; + + aplls_clkin_x2_ck: aplls_clkin_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&aplls_clkin_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + osc_ck: osc_ck@60 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; + ti,bit-shift = <6>; + reg = <0x0060>; + ti,index-starts-at-one; + }; + + sys_ck: sys_ck@60 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&osc_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x0060>; + ti,index-starts-at-one; + }; + + alt_ck: alt_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; + + mcbsp_clks: mcbsp_clks { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + dpll_ck: dpll_ck@500 { + #clock-cells = <0>; + compatible = "ti,omap2-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0500>, <0x0540>; + }; + + apll96_ck: apll96_ck@500 { + #clock-cells = <0>; + compatible = "ti,omap2-apll-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <2>; + ti,idlest-shift = <8>; + ti,clock-frequency = <96000000>; + reg = <0x0500>, <0x0530>, <0x0520>; + }; + + apll54_ck: apll54_ck@500 { + #clock-cells = <0>; + compatible = "ti,omap2-apll-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + ti,idlest-shift = <9>; + ti,clock-frequency = <54000000>; + reg = <0x0500>, <0x0530>, <0x0520>; + }; + + func_54m_ck: func_54m_ck@540 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&apll54_ck>, <&alt_ck>; + ti,bit-shift = <5>; + reg = <0x0540>; + }; + + core_ck: core_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + func_96m_ck: func_96m_ck@540 { + #clock-cells = <0>; + }; + + apll96_d2_ck: apll96_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&apll96_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + func_48m_ck: func_48m_ck@540 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&apll96_d2_ck>, <&alt_ck>; + ti,bit-shift = <3>; + reg = <0x0540>; + }; + + func_12m_ck: func_12m_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&func_48m_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + sys_clkout_src_gate: sys_clkout_src_gate@70 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + reg = <0x0070>; + }; + + sys_clkout_src_mux: sys_clkout_src_mux@70 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; + reg = <0x0070>; + }; + + sys_clkout_src: sys_clkout_src { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; + }; + + sys_clkout: sys_clkout@70 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkout_src>; + ti,bit-shift = <3>; + ti,max-div = <64>; + reg = <0x0070>; + ti,index-power-of-two; + }; + + emul_ck: emul_ck@78 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_54m_ck>; + ti,bit-shift = <0>; + reg = <0x0078>; + }; + + mpu_ck: mpu_ck@140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,max-div = <31>; + reg = <0x0140>; + ti,index-starts-at-one; + }; + + dsp_gate_fck: dsp_gate_fck@800 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <0>; + reg = <0x0800>; + }; + + dsp_div_fck: dsp_div_fck@840 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + reg = <0x0840>; + }; + + dsp_fck: dsp_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dsp_gate_fck>, <&dsp_div_fck>; + }; + + core_l3_ck: core_l3_ck@240 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,max-div = <31>; + reg = <0x0240>; + ti,index-starts-at-one; + }; + + gfx_3d_gate_fck: gfx_3d_gate_fck@300 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <2>; + reg = <0x0300>; + }; + + gfx_3d_div_fck: gfx_3d_div_fck@340 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_l3_ck>; + ti,max-div = <4>; + reg = <0x0340>; + ti,index-starts-at-one; + }; + + gfx_3d_fck: gfx_3d_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; + }; + + gfx_2d_gate_fck: gfx_2d_gate_fck@300 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <1>; + reg = <0x0300>; + }; + + gfx_2d_div_fck: gfx_2d_div_fck@340 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_l3_ck>; + ti,max-div = <4>; + reg = <0x0340>; + ti,index-starts-at-one; + }; + + gfx_2d_fck: gfx_2d_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; + }; + + gfx_ick: gfx_ick@310 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <0>; + reg = <0x0310>; + }; + + l4_ck: l4_ck@240 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0240>; + ti,index-starts-at-one; + }; + + dss_ick: dss_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <0>; + reg = <0x0210>; + }; + + dss1_gate_fck: dss1_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <0>; + reg = <0x0200>; + }; + + core_d2_ck: core_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + core_d3_ck: core_d3_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + core_d4_ck: core_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + core_d5_ck: core_d5_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <5>; + }; + + core_d6_ck: core_d6_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <6>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + core_d8_ck: core_d8_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + core_d9_ck: core_d9_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <9>; + }; + + core_d12_ck: core_d12_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <12>; + }; + + core_d16_ck: core_d16_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dss1_mux_fck: dss1_mux_fck@240 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; + ti,bit-shift = <8>; + reg = <0x0240>; + }; + + dss1_fck: dss1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; + }; + + dss2_gate_fck: dss2_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <1>; + reg = <0x0200>; + }; + + dss2_mux_fck: dss2_mux_fck@240 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_ck>, <&func_48m_ck>; + ti,bit-shift = <13>; + reg = <0x0240>; + }; + + dss2_fck: dss2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; + }; + + dss_54m_fck: dss_54m_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_54m_ck>; + ti,bit-shift = <2>; + reg = <0x0200>; + }; + + ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <1>; + reg = <0x0204>; + }; + + ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <20>; + reg = <0x0240>; + }; + + ssi_ssr_sst_fck: ssi_ssr_sst_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; + }; + + usb_l4_gate_ick: usb_l4_gate_ick@214 { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <0>; + reg = <0x0214>; + }; + + usb_l4_div_ick: usb_l4_div_ick@240 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <25>; + reg = <0x0240>; + ti,dividers = <0>, <1>, <2>, <0>, <4>; + }; + + usb_l4_ick: usb_l4_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; + }; + + ssi_l4_ick: ssi_l4_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <1>; + reg = <0x0214>; + }; + + gpt1_ick: gpt1_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + reg = <0x0410>; + }; + + gpt1_gate_fck: gpt1_gate_fck@400 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <0>; + reg = <0x0400>; + }; + + gpt1_mux_fck: gpt1_mux_fck@440 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + reg = <0x0440>; + }; + + gpt1_fck: gpt1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; + }; + + gpt2_ick: gpt2_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <4>; + reg = <0x0210>; + }; + + gpt2_gate_fck: gpt2_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <4>; + reg = <0x0200>; + }; + + gpt2_mux_fck: gpt2_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <2>; + reg = <0x0244>; + }; + + gpt2_fck: gpt2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; + }; + + gpt3_ick: gpt3_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <5>; + reg = <0x0210>; + }; + + gpt3_gate_fck: gpt3_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <5>; + reg = <0x0200>; + }; + + gpt3_mux_fck: gpt3_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <4>; + reg = <0x0244>; + }; + + gpt3_fck: gpt3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; + }; + + gpt4_ick: gpt4_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <6>; + reg = <0x0210>; + }; + + gpt4_gate_fck: gpt4_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <6>; + reg = <0x0200>; + }; + + gpt4_mux_fck: gpt4_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <6>; + reg = <0x0244>; + }; + + gpt4_fck: gpt4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; + }; + + gpt5_ick: gpt5_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <7>; + reg = <0x0210>; + }; + + gpt5_gate_fck: gpt5_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <7>; + reg = <0x0200>; + }; + + gpt5_mux_fck: gpt5_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <8>; + reg = <0x0244>; + }; + + gpt5_fck: gpt5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; + }; + + gpt6_ick: gpt6_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <8>; + reg = <0x0210>; + }; + + gpt6_gate_fck: gpt6_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0200>; + }; + + gpt6_mux_fck: gpt6_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <10>; + reg = <0x0244>; + }; + + gpt6_fck: gpt6_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; + }; + + gpt7_ick: gpt7_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <9>; + reg = <0x0210>; + }; + + gpt7_gate_fck: gpt7_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <9>; + reg = <0x0200>; + }; + + gpt7_mux_fck: gpt7_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <12>; + reg = <0x0244>; + }; + + gpt7_fck: gpt7_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; + }; + + gpt8_ick: gpt8_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <10>; + reg = <0x0210>; + }; + + gpt8_gate_fck: gpt8_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <10>; + reg = <0x0200>; + }; + + gpt8_mux_fck: gpt8_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <14>; + reg = <0x0244>; + }; + + gpt8_fck: gpt8_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; + }; + + gpt9_ick: gpt9_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <11>; + reg = <0x0210>; + }; + + gpt9_gate_fck: gpt9_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <11>; + reg = <0x0200>; + }; + + gpt9_mux_fck: gpt9_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <16>; + reg = <0x0244>; + }; + + gpt9_fck: gpt9_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; + }; + + gpt10_ick: gpt10_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <12>; + reg = <0x0210>; + }; + + gpt10_gate_fck: gpt10_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <12>; + reg = <0x0200>; + }; + + gpt10_mux_fck: gpt10_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <18>; + reg = <0x0244>; + }; + + gpt10_fck: gpt10_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; + }; + + gpt11_ick: gpt11_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <13>; + reg = <0x0210>; + }; + + gpt11_gate_fck: gpt11_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <13>; + reg = <0x0200>; + }; + + gpt11_mux_fck: gpt11_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <20>; + reg = <0x0244>; + }; + + gpt11_fck: gpt11_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; + }; + + gpt12_ick: gpt12_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <14>; + reg = <0x0210>; + }; + + gpt12_gate_fck: gpt12_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <14>; + reg = <0x0200>; + }; + + gpt12_mux_fck: gpt12_mux_fck@244 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <22>; + reg = <0x0244>; + }; + + gpt12_fck: gpt12_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; + }; + + mcbsp1_ick: mcbsp1_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <15>; + reg = <0x0210>; + }; + + mcbsp1_gate_fck: mcbsp1_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <15>; + reg = <0x0200>; + }; + + mcbsp2_ick: mcbsp2_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <16>; + reg = <0x0210>; + }; + + mcbsp2_gate_fck: mcbsp2_gate_fck@200 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <16>; + reg = <0x0200>; + }; + + mcspi1_ick: mcspi1_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <17>; + reg = <0x0210>; + }; + + mcspi1_fck: mcspi1_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <17>; + reg = <0x0200>; + }; + + mcspi2_ick: mcspi2_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <18>; + reg = <0x0210>; + }; + + mcspi2_fck: mcspi2_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <18>; + reg = <0x0200>; + }; + + uart1_ick: uart1_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <21>; + reg = <0x0210>; + }; + + uart1_fck: uart1_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <21>; + reg = <0x0200>; + }; + + uart2_ick: uart2_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <22>; + reg = <0x0210>; + }; + + uart2_fck: uart2_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <22>; + reg = <0x0200>; + }; + + uart3_ick: uart3_ick@214 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <2>; + reg = <0x0214>; + }; + + uart3_fck: uart3_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <2>; + reg = <0x0204>; + }; + + gpios_ick: gpios_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <2>; + reg = <0x0410>; + }; + + gpios_fck: gpios_fck@400 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <2>; + reg = <0x0400>; + }; + + mpu_wdt_ick: mpu_wdt_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + reg = <0x0410>; + }; + + mpu_wdt_fck: mpu_wdt_fck@400 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <3>; + reg = <0x0400>; + }; + + sync_32k_ick: sync_32k_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + reg = <0x0410>; + }; + + wdt1_ick: wdt1_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + reg = <0x0410>; + }; + + omapctrl_ick: omapctrl_ick@410 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + reg = <0x0410>; + }; + + cam_fck: cam_fck@200 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <31>; + reg = <0x0200>; + }; + + cam_ick: cam_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <31>; + reg = <0x0210>; + }; + + mailboxes_ick: mailboxes_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <30>; + reg = <0x0210>; + }; + + wdt4_ick: wdt4_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <29>; + reg = <0x0210>; + }; + + wdt4_fck: wdt4_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <29>; + reg = <0x0200>; + }; + + mspro_ick: mspro_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <27>; + reg = <0x0210>; + }; + + mspro_fck: mspro_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <27>; + reg = <0x0200>; + }; + + fac_ick: fac_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <25>; + reg = <0x0210>; + }; + + fac_fck: fac_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <25>; + reg = <0x0200>; + }; + + hdq_ick: hdq_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <23>; + reg = <0x0210>; + }; + + hdq_fck: hdq_fck@200 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <23>; + reg = <0x0200>; + }; + + i2c1_ick: i2c1_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <19>; + reg = <0x0210>; + }; + + i2c2_ick: i2c2_ick@210 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <20>; + reg = <0x0210>; + }; + + gpmc_fck: gpmc_fck@238 { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&core_l3_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <1>; + reg = <0x0238>; + ti,clock-mult = <1>; + }; + + sdma_fck: sdma_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_l3_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sdma_ick: sdma_ick@238 { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&core_l3_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <0>; + reg = <0x0238>; + ti,clock-mult = <1>; + }; + + sdrc_ick: sdrc_ick@238 { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&core_l3_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <2>; + reg = <0x0238>; + ti,clock-mult = <1>; + }; + + des_ick: des_ick@21c { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <0>; + reg = <0x021c>; + }; + + sha_ick: sha_ick@21c { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <1>; + reg = <0x021c>; + }; + + rng_ick: rng_ick@21c { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <2>; + reg = <0x021c>; + }; + + aes_ick: aes_ick@21c { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <3>; + reg = <0x021c>; + }; + + pka_ick: pka_ick@21c { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <4>; + reg = <0x021c>; + }; + + usb_fck: usb_fck@204 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <0>; + reg = <0x0204>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts new file mode 100644 index 000000000000..990ff2d84686 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "omap3-beagle.dts" + +/ { + model = "TI OMAP3 BeagleBoard A to B4"; + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; +}; + +/* + * Workaround for capacitor C70 issue, see "Boards revision A and < B5" + * section at https://elinux.org/BeagleBoard_Community + */ + +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because of unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts new file mode 100644 index 000000000000..cb6968a8bce8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "omap3-beagle-xm.dts" + +/ { + /* HS USB Port 2 Power enable was inverted with the xM C */ + hsusb2_power: hsusb2_power_reg { + enable-active-high; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts new file mode 100644 index 000000000000..08ee0f8ea68f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap36xx.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard xM"; + compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &dvi0; + display1 = &tv0; + ethernet = ðernet; + }; + + /* fixed 26MHz oscillator */ + hfclk_26m: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + led-controller-1 { + compatible = "gpio-leds"; + + led-1 { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + led-controller-2 { + compatible = "pwm-leds"; + + led-3 { + label = "beagleboard::pmu_stat"; + pwms = <&twl_pwmled 1 7812500>; + max-brightness = <127>; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + linux,code = <0x114>; + wakeup-source; + }; + + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; + + /* XXX pinctrl from twl */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + etb@5401b000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x5401b000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in: endpoint { + remote-endpoint = <&etm_out>; + }; + }; + }; + }; + + etm@54010000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x54010000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + out-ports { + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: gpio1-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ + >; + }; + + dss_dpi_pins2: dss-dpi1-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; + + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + dss_dpi_pins1: dss-dpi2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + clocks = <&hfclk_26m>; + clock-names = "fck"; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + + twl_power: power { + compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; + ti,use_poweroff; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + hub@2 { + compatible = "usb424,9514"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; + +&vaux2 { + regulator-name = "usb_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mcbsp2 { + status = "okay"; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins1 + &dss_dpi_pins2 + >; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-beagle.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle.dts new file mode 100644 index 000000000000..4d9a8eab6abf --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle.dts @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard"; + compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; + + leds { + compatible = "gpio-leds"; + led-pmu-stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + }; + + led-heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + led-mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,code = <0x114>; + wakeup-source; + }; + + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + pinctrl-names = "default"; + pinctrl-0 = <&tfp410_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + etb@540000000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x5401b000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in: endpoint { + remote-endpoint = <&etm_out>; + }; + }; + }; + }; + + etm@54010000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x54010000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + out-ports { + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: gpio1-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + tfp410_pins: tfp410-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&vaux2 { + regulator-name = "vdd_ehci"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mcbsp2 { + status = "okay"; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&gpmc { + status = "okay"; + ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ + + /* Chip select 0 */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* NAND I/O window, 4 bytes */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-ecc-opt = "ham1"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <16>; + #address-cells = <1>; + #size-cells = <1>; + + gpmc,device-width = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + partition@1c0000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x680000 0xf980000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts new file mode 100644 index 000000000000..f776e0527049 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for CompuLab CM-T3517 + */ +/dts-v1/; + +#include "am3517.dtsi" +#include "omap3-cm-t3x.dtsi" + +/ { + model = "CompuLab CM-T3517"; + compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; + + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vw1271"; + pinctrl-names = "default"; + pinctrl-0 = < + &wl12xx_wkup_pins + &wl12xx_core_pins + >; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ + startup-delay-us = <20000>; + enable-active-high; + }; + + wl12xx_vaux2: wl12xx_vaux2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271_vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&omap3_pmx_wkup { + + wl12xx_wkup_pins: wl12xx-wkup-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ + >; + }; +}; + +&omap3_pmx_core { + + phy1_reset_pins: hsusb1-phy-reset-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ + >; + }; + + phy2_reset_pins: hsusb2-phy-reset-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ + >; + }; + + otg_drv_vbus: otg-drv-vbus-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + wl12xx_core_pins: wl12xx-core-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ + OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ + >; + }; + + usb_hub_pins: usb-hub-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ + >; + }; +}; + +&hsusb1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&phy1_reset_pins>; + reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; +}; + +&hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&phy2_reset_pins>; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; +}; + +&davinci_emac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&am35x_otg_hs { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv_vbus>; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + vqmmc-supply = <&wl12xx_vaux2>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */ + ref-clock-frequency = <38400000>; + }; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t35x + >; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts new file mode 100644 index 000000000000..0c6f14963e5e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for CompuLab CM-T3530 + */ +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap3-cm-t3x30.dtsi" + +/ { + model = "CompuLab CM-T3530"; + compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + + /* Regulator to trigger the reset signal of the Wifi module */ + mmc2_sdio_reset: regulator-mmc2-sdio-reset { + compatible = "regulator-fixed"; + regulator-name = "regulator-mmc2-sdio-reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&omap3_pmx_core { + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&mmc2_sdio_reset>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t35x + >; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts new file mode 100644 index 000000000000..f1a8f0fd7a83 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for CompuLab CM-T3730 + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-cm-t3x30.dtsi" + +/ { + model = "CompuLab CM-T3730"; + compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3"; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vw1271"; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ + startup-delay-us = <20000>; + enable-active-high; + }; + + wl12xx_vaux2: wl12xx_vaux2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271_vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vaux2>; + }; +}; + +&omap3_pmx_wkup { + dss_dpi_pins_cm_t3730: dss-dpi-cm-t3730-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core { + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + vqmmc-supply = <&wl12xx_vaux2>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ + ref-clock-frequency = <38400000>; + }; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t3730 + >; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi new file mode 100644 index 000000000000..f6cd7a3aef1f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common support for CompuLab CM-T3x CoMs + */ + +/ { + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&green_led_pins>; + ledb { + label = "cm-t3x:green"; + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ + linux,default-trigger = "heartbeat"; + }; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&hsusb1_power>; + #phy-cells = <0>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + tv0: svideo-connector { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; +}; + +&omap3_pmx_core { + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + green_led_pins: green-led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ + >; + }; + + dss_dpi_pins_common: dss-dpi-common-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + dss_dpi_pins_cm_t35x: dss-dpi-cm-t35x-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + >; + }; + + ads7846_pins: ads7846-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; + + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; +}; + +&mmc3 { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy &hsusb2_phy>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio2>; + interrupts = <25 0>; /* gpio_57 */ + pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + ti,debounce-max = /bits/ 16 <30>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <1>; + + wakeup-source; + }; +}; + +&venc { + status = "okay"; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&mcbsp2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <8>; + gpmc,device-width = <1>; + ti,nand-ecc-opt = "sw"; + + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <120>; + gpmc,cs-wr-off-ns = <120>; + + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <120>; + gpmc,adv-wr-off-ns = <120>; + + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <90>; + + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <90>; + + gpmc,page-burst-access-ns = <6>; + gpmc,access-ns = <72>; + gpmc,cycle2cycle-delay-ns = <60>; + + gpmc,rd-cycle-ns = <120>; + gpmc,wr-cycle-ns = <120>; + gpmc,wr-access-ns = <186>; + gpmc,wr-data-mux-bus-ns = <90>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "xloader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "uboot"; + reg = <0x80000 0x1e0000>; + }; + partition@260000 { + label = "uboot environment"; + reg = <0x260000 0x40000>; + }; + partition@2a0000 { + label = "linux"; + reg = <0x2a0000 0x400000>; + }; + partition@6a0000 { + label = "rootfs"; + reg = <0x6a0000 0x1f880000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi new file mode 100644 index 000000000000..0e942513560d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common support for CompuLab CM-T3x30 CoMs + */ + +#include "omap3-cm-t3x.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "cm-t35"; + + ti,mcbsp = <&mcbsp2>; + }; +}; + +&omap3_pmx_core { + + smsc1_pins: smsc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ + >; + }; + + hsusb0_pins: hsusb0-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; +}; + +#include "omap-gpmc-smsc911x.dtsi" + +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ + <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ + + smsc1: ethernet@gpmc { + compatible = "smsc,lan9221", "smsc,lan9115"; + pinctrl-names = "default"; + pinctrl-0 = <&smsc1_pins>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + reg = <5 0 0xff>; + }; +}; + +&i2c1 { + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" +#include + +&venc { + vdda-supply = <&vdac>; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(0) */ + ti,pullups = <0x000001>; +}; + +&twl_keypad { + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_A) + MATRIX_KEY(0x00, 0x02, KEY_B) + MATRIX_KEY(0x00, 0x03, KEY_LEFT) + + MATRIX_KEY(0x01, 0x01, KEY_UP) + MATRIX_KEY(0x01, 0x02, KEY_ENTER) + MATRIX_KEY(0x01, 0x03, KEY_DOWN) + + MATRIX_KEY(0x02, 0x01, KEY_RIGHT) + MATRIX_KEY(0x02, 0x02, KEY_C) + MATRIX_KEY(0x02, 0x03, KEY_D) + >; +}; + +&hsusb1_phy { + reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; +}; + +&hsusb2_phy { + reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb0_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi new file mode 100644 index 000000000000..0da759f8e2c2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP3 SoC CPU thermal + * + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + coefficients = <0 20000>; + + /* sensor ID */ + thermal-sensors = <&bandgap 0>; + + cpu_trips: trips { + cpu_alert0: cpu_alert { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi new file mode 100644 index 000000000000..3b9838f1bb6b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Anil Kumar + */ + +#include + +#include "omap34xx.dtsi" +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + + led-heartbeat { + label = "devkit8000::led1"; + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-mmc { + label = "devkit8000::led2"; + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ + default-state = "on"; + linux,default-trigger = "none"; + }; + + led-usr { + label = "devkit8000::led3"; + gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ + default-state = "on"; + linux,default-trigger = "usr"; + }; + + led-pmu-stat { + label = "devkit8000::pmu_stat"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "devkit8000"; + + ti,mcbsp = <&mcbsp2>; + ti,audio-routing = + "Ext Spk", "PREDRIVEL", + "Ext Spk", "PREDRIVER", + "MAINMIC", "Main Mic", + "Main Mic", "Mic Bias 1"; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_dvi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c2>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + status = "disabled"; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred timer for clockevent */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +&twl_gpio { + ti,use-leds; + /* + * pulldowns: + * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c6>; +}; + +&twl_keypad { + linux,keymap = ; +}; + +&wdt2 { + status = "disabled"; +}; + +&mcbsp2 { + status = "okay"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "sw"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; + + ethernet@6,0 { + compatible = "davicom,dm9000"; + reg = <6 0x000 2 + 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ + bank-width = <2>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + davicom,no-eeprom; + + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <0>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + gpmc,cs-on-ns = <6>; + gpmc,cs-rd-off-ns = <180>; + gpmc,cs-wr-off-ns = <180>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <144>; + gpmc,page-burst-access-ns = <24>; + gpmc,bus-turnaround-ns = <90>; + gpmc,cycle2cycle-delay-ns = <90>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; +}; + +&omap3_pmx_core { + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&vpll1 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + vdds_dsi-supply = <&vpll1>; + vdda_dac-supply = <&vdac>; + + port { + #address-cells = <1>; + #size-cells = <0>; + dpi_dvi_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + + endpoint@1 { + reg = <1>; + }; + }; +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi new file mode 100644 index 000000000000..3decc2d78a6c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Anthoine Bourgeois + */ + +#include "omap3-devkit8000-common.dtsi" +/ { + aliases { + display0 = &lcd0; + display1 = &dvi0; + display2 = &tv0; + }; + + lcd0: display { + compatible = "panel-dpi"; + label = "lcd"; + + enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + }; + }; + }; +}; + +&dss { + port { + #address-cells = <1>; + #size-cells = <0>; + dpi_lcd_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&vio { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcspi2 { + + /* touch controller */ + ads7846@0 { + compatible = "ti,ads7846"; + vcc-supply = <&vio>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio1>; + interrupts = <27 0>; /* gpio_27 */ + pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <5>; + ti,debounce-rep = /bits/ 16 <1>; + ti,keep-vref-on = <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts new file mode 100644 index 000000000000..afed85078ad8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Anthoine Bourgeois + */ +/dts-v1/; + +/* + * 4.3'' LCD panel sold with devkit8000 board + */ + +#include "omap3-devkit8000-lcd-common.dtsi" +/ { + model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; + compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + + lcd0: display { + panel-timing { + clock-frequency = <10164705>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts new file mode 100644 index 000000000000..07c51a105c0d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Anthoine Bourgeois + */ +/dts-v1/; + +/* + * 7.0'' LCD panel sold with some devkit8000 board + */ + +#include "omap3-devkit8000-lcd-common.dtsi" +/ { + model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; + compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + + lcd0: display { + panel-timing { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <1>; + hback-porch = <1>; + hsync-len = <48>; + vback-porch = <25>; + vfront-porch = <12>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts new file mode 100644 index 000000000000..162d0726b008 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Anthoine Bourgeois + */ +/dts-v1/; + +#include "omap3-devkit8000-common.dtsi" +/ { + model = "TimLL OMAP3 Devkit8000"; + compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + + aliases { + display1 = &dvi0; + display2 = &tv0; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-echo.dts b/arch/arm/boot/dts/ti/omap/omap3-echo.dts new file mode 100644 index 000000000000..96011c976f5b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-echo.dts @@ -0,0 +1,724 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 André Hentschel + */ +/dts-v1/; + +#include "dm3725.dtsi" + +#include +#include + +/ { + model = "Amazon Echo (first generation)"; + compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0xc600000>; /* 198 MB */ + }; + + vcc5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc1v8: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <40>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + mute-button { + label = "mute"; + linux,code = ; + gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */ + wakeup-source; + }; + + help-button { + label = "help"; + linux,code = ; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */ + wakeup-source; + }; + }; + + rotary: rotary-encoder { + compatible = "rotary-encoder"; + gpios = < + &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */ + &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */ + >; + linux,axis = ; + rotary-encoder,relative-axis; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* gpio_129 */ + sound-name-prefix = "Speaker Amp"; + VCC-supply = <&vcc1v8>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Misto Speaker"; + simple-audio-card,widgets = + "Speaker", "Speaker"; + simple-audio-card,routing = + "Speaker Amp INL", "HPL", + "Speaker Amp INR", "HPR", + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,aux-devs = <&speaker_amp>; + + simple-audio-card,cpu { + sound-dai = <&mcbsp2>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&codec0>; + system-clock-frequency = <19200000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&mcbsp2 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; + +&i2c2 { + clock-frequency = <400000>; + + lp5523A: lp5523A@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "national,lp5523"; + label = "q1"; + reg = <0x32>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + enable-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + color = ; + + led@0 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x0>; + color = ; + }; + + led@1 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x1>; + color = ; + }; + + led@6 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x6>; + color = ; + }; + }; + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + color = ; + + led@2 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x2>; + color = ; + }; + + led@3 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x3>; + color = ; + }; + + led@7 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x7>; + color = ; + }; + }; + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + color = ; + + led@4 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x4>; + color = ; + }; + + led@5 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x5>; + color = ; + }; + + led@8 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x8>; + color = ; + }; + }; + }; + + lp5523B: lp5523B@33 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "national,lp5523"; + label = "q3"; + reg = <0x33>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + color = ; + + led@0 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x0>; + color = ; + }; + + led@1 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x1>; + color = ; + }; + + led@6 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x6>; + color = ; + }; + }; + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + color = ; + + led@2 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x2>; + color = ; + }; + + led@3 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x3>; + color = ; + }; + + led@7 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x7>; + color = ; + }; + }; + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + color = ; + + led@4 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x4>; + color = ; + }; + + led@5 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x5>; + color = ; + }; + + led@8 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x8>; + color = ; + }; + }; + }; + + lp5523C: lp5523C@34 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "national,lp5523"; + label = "q4"; + reg = <0x34>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + color = ; + + led@0 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x0>; + color = ; + }; + + led@1 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x1>; + color = ; + }; + + led@6 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x6>; + color = ; + }; + }; + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + color = ; + + led@2 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x2>; + color = ; + }; + + led@3 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x3>; + color = ; + }; + + led@7 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x7>; + color = ; + }; + }; + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + color = ; + + led@4 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x4>; + color = ; + }; + + led@5 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x5>; + color = ; + }; + + led@8 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x8>; + color = ; + }; + }; + }; + + lp5523D: lp552D@35 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "national,lp5523"; + label = "q2"; + reg = <0x35>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + color = ; + + led@0 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x0>; + color = ; + }; + + led@1 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x1>; + color = ; + }; + + led@6 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x6>; + color = ; + }; + }; + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + color = ; + + led@2 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x2>; + color = ; + }; + + led@3 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x3>; + color = ; + }; + + led@7 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x7>; + color = ; + }; + }; + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + color = ; + + led@4 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x4>; + color = ; + }; + + led@5 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x5>; + color = ; + }; + + led@8 { + led-cur = /bits/ 8 <12>; + max-cur = /bits/ 8 <15>; + reg = <0x8>; + color = ; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + codec0: codec@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&sys_clkout1>; + clock-names = "mclk"; + ldoin-supply = <&vcc1v8>; + iov-supply = <&vcc1v8>; + reset-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; /* gpio_74 */ + }; +}; + + +#include "../../tps65910.dtsi" + +&omap3_pmx_core { + tps_pins: tps-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* dss_data4.gpio_74 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data15.gpio_85 */ + OMAP3_CORE1_IOPAD(0x2a1a, PIN_OUTPUT | MUX_MODE0) /* sys_clkout1.sys_clkout1 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ + >; + }; +}; + +&omap3_pmx_core2 { + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; +}; + +&mmc1 { + status = "okay"; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc_reg>; +}; + +&mmc2 { + status = "okay"; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmc_reg>; +}; + +&mmc3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + non-removable; + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vcc3v3>; + vqmmc-supply = <&vcc1v8>; + atheros@0 { + compatible = "atheros,ath6kl"; + reg = <0>; + bus-width = <4>; + }; +}; + +&tps { + pinctrl-names = "default"; + pinctrl-0 = <&tps_pins>; + + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + ti,en-ck32k-xtal; + ti,system-power-controller; + + vcc1-supply = <&vcc5v>; + vcc2-supply = <&vcc5v>; + vcc3-supply = <&vcc5v>; + vcc4-supply = <&vcc5v>; + vcc5-supply = <&vcc5v>; + vcc6-supply = <&vcc5v>; + vcc7-supply = <&vcc5v>; + vccio-supply = <&vcc5v>; + + regulators { + + vio_reg: regulator@1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd_dsp"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts b/arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts new file mode 100644 index 000000000000..e0346bf842fc --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-evm-common.dtsi" +#include "omap3-evm-processor-common.dtsi" + +/ { + model = "TI OMAP37XX EVM (TMDSEVM3730)"; + compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + + ehci_phy_pins: ehci-phy-pins { + pinctrl-single,pins = < + + /* EHCI PHY reset GPIO etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) + + /* EHCI VBUS etk_d8.gpio_22 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + + /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) + + /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) + + /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d15.hsusb2_data1 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +&gpmc { + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "hynix,h8kds0un0mer-4em"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x780000 0x1f880000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi new file mode 100644 index 000000000000..1b6023c4cdf3 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common support for omap3 EVM boards + */ + +#include +#include "omap-gpmc-smsc911x.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "omap3evm::ledb"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + linux,default-trigger = "default-on"; + }; + }; + + wl12xx_vmmc: wl12xx_vmmc { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vmmc2>; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" +#include "omap3-panel-sharp-ls037v7dw01.dtsi" + +&backlight0 { + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; +}; + +&twl { + twl_power: power { + compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle"; + ti,use_poweroff; + }; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&lcd_3v3 { + gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ +}; + +&lcd0 { + enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ + reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ + mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ + &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ + &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ +}; + +&mcspi1 { + tsc2046@0 { + interrupt-parent = <&gpio6>; + interrupts = <15 0>; /* gpio175 */ + pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + /* gpio_149 with uart1_rts pad as wakeirq */ + interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, + <&omap3_pmx_core 0x14e>; + interrupt-names = "irq", "wakeup"; + ref-clock-frequency = <38400000>; + }; +}; + +&twl_gpio { + ti,use-leds; +}; + +&twl_keypad { + linux,keymap = < + MATRIX_KEY(2, 2, KEY_1) + MATRIX_KEY(1, 1, KEY_2) + MATRIX_KEY(0, 0, KEY_3) + MATRIX_KEY(3, 2, KEY_4) + MATRIX_KEY(2, 1, KEY_5) + MATRIX_KEY(1, 0, KEY_6) + MATRIX_KEY(1, 3, KEY_7) + MATRIX_KEY(3, 1, KEY_8) + MATRIX_KEY(2, 0, KEY_9) + MATRIX_KEY(2, 3, KEY_KPASTERISK) + MATRIX_KEY(0, 2, KEY_0) + MATRIX_KEY(3, 0, KEY_KPDOT) + /* s4 not wired */ + MATRIX_KEY(1, 2, KEY_BACKSPACE) + MATRIX_KEY(0, 1, KEY_ENTER) + >; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&gpmc { + ethernet@gpmc { + interrupt-parent = <&gpio6>; + interrupts = <16 8>; + reg = <5 0 0xff>; + }; +}; + +&vaux2 { + regulator-name = "usb_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi new file mode 100644 index 000000000000..e27837093e43 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi @@ -0,0 +1,224 @@ +/* + * Common support for omap3 EVM 35xx/37xx processor modules + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + }; +}; + +&dss { + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&lcd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins1 + &dss_dpi_pins2 + >; +}; + +&hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&ehci_phy_pins>; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; + + dss_dpi_pins1: dss-dpi2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ + on_board_gpio_61: ehci-port-select-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + + /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; + + /* + * Note that gpio_150 pulled high with internal pull to prevent wlcore + * reset on return from off mode in idle. + */ + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ + >; + }; + + smsc911x_pins: smsc911x-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ + >; + }; +}; + +&omap3_pmx_wkup { + dss_dpi_pins2: dss-dpi1-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +/* + * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface + * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. + */ +&gpio2 { + en-usb2-port-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ + output-low; + line-name = "enable usb2 port"; + }; +}; + +/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ +&twl_gpio { + en_on_board_gpio_61 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "en_hsusb2_clk"; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ + <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc911x_pins>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-evm.dts b/arch/arm/boot/dts/ti/omap/omap3-evm.dts new file mode 100644 index 000000000000..a2a1613c45c3 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-evm.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap3-evm-common.dtsi" +#include "omap3-evm-processor-common.dtsi" + +/ { + model = "TI OMAP35XX EVM (TMDSEVM3530)"; + compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + + ehci_phy_pins: ehci-phy-pins { + pinctrl-single,pins = < + + /* EHCI PHY reset GPIO etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) + + /* EHCI VBUS etk_d8.gpio_22 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + + /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) + + /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) + + /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d15.hsusb2_data1 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +&gpmc { + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f2g16abdhc"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi new file mode 100644 index 000000000000..b6b27e93857f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi @@ -0,0 +1,893 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Marek Belisko + * + * Based on omap3-beagle-xm.dts + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include + +/ { + model = "OMAP3 GTA04"; + compatible = "goldelico,gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + chosen { + stdout-path = &uart3; + }; + + aliases { + display0 = &lcd; + display1 = &tv0; + /delete-property/ mmc2; + /delete-property/ mmc3; + }; + + ldo_3v3: fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "ldo_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* fixed 26MHz oscillator */ + hfclk_26m: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + aux-button { + label = "aux"; + linux,code = ; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + }; + + antenna-detect { + compatible = "gpio-keys"; + + gps_antenna_button: gps-antenna-button { + label = "GPS_EXT_ANT"; + linux,input-type = ; + linux,code = ; + gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* GPIO144 */ + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_EDGE_BOTH>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "gta04"; + + ti,mcbsp = <&mcbsp2>; + }; + + /* GSM audio */ + sound_telephony { + compatible = "simple-audio-card"; + simple-audio-card,name = "GTA04 voice"; + simple-audio-card,bitclock-master = <&telephony_link_master>; + simple-audio-card,frame-master = <&telephony_link_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-inversion; + simple-audio-card,cpu { + sound-dai = <&mcbsp4>; + }; + + telephony_link_master: simple-audio-card,codec { + sound-dai = <>m601_codec>; + }; + }; + + gtm601_codec: gsm_codec { + compatible = "option,gtm601"; + #sound-dai-cells = <0>; + }; + + spi_lcd: spi { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_pins>; + + sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + /* lcd panel */ + lcd: td028ttec1@0 { + compatible = "tpo,td028ttec1"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + backlight = <&backlight>; + label = "lcd"; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm11 0 12000000 0>; + pwm-names = "backlight"; + brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <9>; /* => 90 */ + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + }; + + pwm11: pwm-11 { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer11>; + #pwm-cells = <3>; + ti,clock-source = <0x01>; + }; + + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + #phy-cells = <0>; + }; + + tv0: connector { + compatible = "composite-video-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&opa_out>; + }; + }; + }; + + tv_amp: opa362 { + compatible = "ti,opa362"; + enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; /* GPIO_23 to enable video out amplifier */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + opa_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + + port@1 { + reg = <1>; + opa_out: endpoint { + remote-endpoint = <&tv_connector_in>; + }; + }; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ + }; + + /* devconf0 setup for mcbsp1 clock pins */ + pinmux@48002274 { + compatible = "pinctrl-single"; + reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; /* MCBSP1 CLK pinmux */ + #pinctrl-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_devconf0_pins>; + mcbsp1_devconf0_pins: mcbsp1-devconf0-pins { + /* offset bits mask */ + pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ + }; + }; + + /* devconf1 setup for tvout pins */ + pinmux@480022d8 { + compatible = "pinctrl-single"; + reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x81>; /* TV out pin control */ + #pinctrl-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&tv_acbias_devconf1_pins>; + tv_acbias_devconf1_pins: tv-acbias-devconf1-pins { + /* offset bits mask */ + pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ + }; + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: gpio1-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ + OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + backlight_pins: backlight-pinmux-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + gps_pins: gps-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ + >; + }; + + hdq_pins: hdq-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ + >; + }; + + bmp085_pins: bmp085-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ + >; + }; + + bma180_pins: bma180-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ + >; + }; + + itg3200_pins: itg3200-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ + >; + }; + + hmc5843_pins: hmc5843-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ + >; + }; + + penirq_pins: penirq-pins { + pinctrl-single,pins = < + /* here we could enable to wakeup the cpu from suspend by a pen touch */ + OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ + >; + }; + + camera_pins: camera-pins { + pinctrl-single,pins = < + /* set up parallel camera interface */ + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ + OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_vs */ + OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_pclk */ + OMAP3_CORE1_IOPAD(0x2114, PIN_OUTPUT | MUX_MODE4) /* cam_fld = gpio_98 */ + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d0 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d1 */ + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d2 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d3 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d4 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d5 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d6 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d7 */ + OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d8 */ + OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d9 */ + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ + OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ + OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE0) /* cam_xclkb */ + OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* cam_wen = gpio_167 */ + OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */ + >; + }; + + mcbsp1_pins: mcbsp1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ + OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ + /* mcbsp_clks is used as PENIRQ */ + /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) mcbsp_clks.mcbsp_clks */ + OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ + OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dx */ + >; + }; + + mcbsp3_pins: mcbsp3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ + OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ + OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_clkx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_fsx */ + >; + }; + + mcbsp4_pins: mcbsp4-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ + OMAP3_CORE1_IOPAD(0x218a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_dx.mcbsp4_fsx */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + spi_gpio_pins: spi-gpio-pinmux-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + clocks = <&hfclk_26m>; + clock-names = "fck"; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + ti,enable-vibra = <1>; + codec { + ti,ramp_delay_value = <3>; + }; + }; + + twl_power: power { + compatible = "ti,twl4030-power-idle"; + ti,system-power-controller; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; + + /* pressure sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + pinctrl-names = "default"; + pinctrl-0 = <&bmp085_pins>; + interrupt-parent = <&gpio4>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */ + vdda-supply = <&vio>; + vddd-supply = <&vio>; + }; + + /* accelerometer */ + bma180@41 { + compatible = "bosch,bma180"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&bma180_pins>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ + }; + + /* gyroscope */ + itg3200@68 { + compatible = "invensense,itg3200"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&itg3200_pins>; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ + }; + + /* leds + gpios */ + tca6507: tca6507@45 { + compatible = "ti,tca6507"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x45>; + + gpio-controller; + #gpio-cells = <2>; + + gta04_led0: led@0 { + label = "gta04:red:aux"; + reg = <0x0>; + }; + + gta04_led1: led@1 { + label = "gta04:green:aux"; + reg = <0x1>; + }; + + gta04_led3: led@3 { + label = "gta04:red:power"; + reg = <0x3>; + linux,default-trigger = "default-on"; + }; + + gta04_led4: led@4 { + label = "gta04:green:power"; + reg = <0x4>; + }; + + wifi_reset: led@6 { + /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */ + reg = <0x6>; + compatible = "gpio"; + }; + }; + + /* compass aka magnetometer */ + hmc5843@1e { + compatible = "honeywell,hmc5883l"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&hmc5843_pins>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ + }; + + /* touchscreen */ + tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&penirq_pins>; + interrupt-parent = <&gpio6>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* GPIO_160 */ + ti,x-plate-ohms = <600>; + touchscreen-size-x = <480>; + touchscreen-size-y = <640>; + touchscreen-max-pressure = <1000>; + touchscreen-fuzz-x = <3>; + touchscreen-fuzz-y = <8>; + touchscreen-fuzz-pressure = <10>; + touchscreen-inverted-y; + }; + + /* RFID EEPROM */ + m24lr64@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mcspi1 { + status = "disabled"; +}; + +&mcspi2 { + status = "disabled"; +}; + +&mcspi3 { + status = "disabled"; +}; + +&mcspi4 { + status = "disabled"; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + ti,non-removable; + broken-cd; /* hardware has no CD */ +}; + +&mmc2 { + vmmc-supply = <&vaux4>; + bus-width = <4>; + ti,non-removable; + cap-power-off-card; + mmc-pwrseq = <&wifi_pwrseq>; +}; + +&mmc3 { + status = "disabled"; +}; + +#define BIT(x) (1 << (x)) +&twl_gpio { + /* pullups: BIT(2) */ + ti,pullups = ; + /* + * pulldowns: + * BIT(0), BIT(1), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | + BIT(13) | BIT(15) | BIT(16) | BIT(17))>; +}; + +&twl_keypad { + status = "disabled"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + gnss: gnss { + compatible = "wi2wi,w2sg0004"; + pinctrl-names = "default"; + pinctrl-0 = <&gps_pins>; + sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + lna-supply = <&vsim>; + vcc-supply = <&ldo_3v3>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +/* spare */ +&vaux1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; +}; + +/* sensors */ +&vaux2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; /* we should never switch off while vio is on! */ +}; + +/* camera */ +&vaux3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; +}; + +/* WLAN/BT */ +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + +/* GPS LNA */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + +/* Needed to power the DPI pins */ + +&vpll2 { + regulator-always-on; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "okay"; + vdds_dsi-supply = <&vpll2>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&opa_in>; + ti,channels = <1>; + ti,invert-polarity; + }; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-ecc-opt = "ham1"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <16>; + #address-cells = <1>; + #size-cells = <1>; + + gpmc,device-width = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,oe-off-ns = <54>; + gpmc,we-off-ns = <40>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,sync-clk-ps = <0>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + + bootloaders_env@240000 { + label = "U-Boot Env"; + reg = <0x240000 0x40000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x600000>; + }; + + filesystem@880000 { + label = "File System"; + reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + }; +}; + +&mcbsp1 { /* FM Transceiver PCM */ + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; +}; + +&mcbsp2 { /* TPS65950 I2S */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; + +&mcbsp3 { /* Bluetooth PCM */ + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; +}; + +&mcbsp4 { /* GSM voice PCM */ + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp4_pins>; +}; + +&hdqw1w { + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; + +/* image signal processor within OMAP3 SoC */ +&isp { + ports { + port@0 { + reg = <0>; + parallel_ep: endpoint { + ti,isp-clock-divisor = <1>; + ti,strobe-mode; + bus-width = <8>;/* Used data lines */ + data-shift = <2>; /* Lines 9:2 are used */ + hsync-active = <0>; /* Active low */ + vsync-active = <1>; /* Active high */ + data-active = <1>;/* Active high */ + pclk-sample = <1>;/* Falling */ + }; + }; + /* port@1 and port@2 are not used by GTA04 */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts new file mode 100644 index 000000000000..bfae1a9ceeac --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 H. Nikolaus Schaller + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A3/Letux 2804"; +}; + +&i2c2 { + + /* alternate accelerometer that might be installed on some GTA04A3 boards */ + lis302@1d { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x1d>; + interrupt-parent = <&gpio3>; + interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + Vdd-supply = <&vaux2>; + Vdd_IO-supply = <&vaux2>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <8>; + st,click-thresh-y = <8>; + st,click-thresh-z = <10>; + st,click-click-time-limit = <9>; + st,click-latency = <50>; + st,irq1-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <32>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + st,max-limit-x = <3>; + st,max-limit-y = <32>; + st,max-limit-z = <32>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts new file mode 100644 index 000000000000..f1cf24d55e6f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Marek Belisko + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A4/Letux 2804"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts new file mode 100644 index 000000000000..8bd6b4b1f30b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-18 H. Nikolaus Schaller + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A5/Letux 2804"; + + sound { + ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; /* GTA04A5 only */ + }; + + wlan_en: wlan_en_regulator { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pins>; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* GPIO_138 */ + + startup-delay-us = <70000>; + enable-active-high; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pps_pins>; + + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; /* GPIN_114 */ + }; + +}; + +&gpio5 { + irda-en-hog { + gpio-hog; + gpios = <(175-160) GPIO_ACTIVE_HIGH>; + output-high; /* activate gpio_175 to disable IrDA receiver */ + }; +}; + +&omap3_pmx_core { + bt_pins: bt-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat5 = mmc3_dat1 = gpio137 */ + >; + }; + + wlan_pins: wlan-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat6 = mmc3_dat2 = gpio138 */ + >; + }; + + wlan_irq_pin: wlan-irq-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */ + >; + }; + + irda_pins: irda-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4) /* mcspi1_cs1 = gpio175 */ + >; + }; + + pps_pins: pps-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */ + >; + }; + + bno050_pins: pinmux-bno050-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT | MUX_MODE4) /* gpin113 */ + >; + }; +}; + +/* + * for WL183x module see + * Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml + */ + +&wifi_pwrseq { + /delete-property/ reset-gpios; +}; + +&mmc2 { + vmmc-supply = <&wlan_en>; + bus-width = <4>; + cap-power-off-card; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_irq_pin>; + + #address-cells = <1>; + #size-cells = <0>; + + /delete-property/ mmc-pwrseq; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_139 */ + ref-clock-frequency = <26000000>; + }; +}; + +&i2c2 { + /delete-node/ bmp085@77; + /delete-node/ bma180@41; + /delete-node/ itg3200@68; + /delete-node/ hmc5843@1e; + + gyrometer@69 { + compatible = "bosch,bmg160"; + reg = <0x69>; + }; + + accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + }; + + bme280@76 { + compatible = "bosch,bme280"; + reg = <0x76>; + vdda-supply = <&vio>; + vddd-supply = <&vio>; + }; + + imu@29 { + compatible = "bosch,bno055"; + reg = <0x29>; + pinctrl-names = "default"; + pinctrl-0 = <&bno050_pins>; + /* interrupt at &gpio4 17 */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts new file mode 100644 index 000000000000..1e5703d1b02e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-18 H. Nikolaus Schaller + */ + +#include "omap3-gta04a5.dts" + +/ { + model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; +}; + +&omap3_pmx_core { + gpmc_pins: gpmc-pins { + pinctrl-single,pins = < + + /* address lines */ + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + + /* data lines, gpmc_d0..d7 not muxable according to TRM */ + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + + /* + * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable + * according to TRM. OneNAND seems to require PIN_INPUT on clock. + */ + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; + }; +}; + +&gpmc { + /* switch inherited setup to OneNAND */ + + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + + /delete-node/ nand@0,0; + + onenand@0,0 { + + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,burst-write; + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <87>; + gpmc,cs-wr-off-ns = <87>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <15>; + gpmc,oe-off-ns = <87>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <87>; + gpmc,rd-cycle-ns = <112>; + gpmc,wr-cycle-ns = <112>; + gpmc,access-ns = <81>; + gpmc,page-burst-access-ns = <15>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <5>; + gpmc,wr-data-mux-bus-ns = <30>; + gpmc,wr-access-ns = <81>; + gpmc,sync-clk-ps = <15000>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + + bootloaders_env@240000 { + label = "U-Boot Env"; + reg = <0x240000 0x40000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x600000>; + }; + + filesystem@880000 { + label = "File System"; + reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi new file mode 100644 index 000000000000..3a258a692757 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + */ + +#include "omap3-tao3530.dtsi" + +/ { + gpio_poweroff { + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_pins>; + + compatible = "gpio-poweroff"; + gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ + }; +}; + +&omap3_pmx_core { + sound2_pins: sound2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ + >; + }; + + led_blue_pins: led-blue-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ + >; + }; + + led_green_pins: led-green-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ + >; + }; + + led_red_pins: led-red-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ + >; + }; + + poweroff_pins: poweroff-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ + >; + }; + + powerdown_input_pins: powerdown-input-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ + >; + }; + + fpga_boot0_pins: fpga-boot0-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ + >; + }; + + fpga_boot1_pins: fpga-boot1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ + >; + }; +}; + +/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts b/arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts new file mode 100644 index 000000000000..94f6b7931e33 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + */ + +#include "omap3-ha-common.dtsi" + +/ { + model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; + compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + &powerdown_input_pins + &fpga_boot0_pins + &fpga_boot1_pins + &led_blue_pins + &led_green_pins + &led_red_pins + &touchscreen_wake_pins + >; + + touchscreen_irq_pins: touchscreen-irq-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ + >; + }; + + touchscreen_wake_pins: touchscreen-wake-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: lte430-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ + >; + }; +}; + +/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display { + compatible = "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <31250000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <86>; + hsync-len = <1>; + vback-porch = <30>; + vfront-porch = <13>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ + + default-on; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-ha.dts b/arch/arm/boot/dts/ti/omap/omap3-ha.dts new file mode 100644 index 000000000000..19e471eb3b4e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-ha.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + */ + +#include "omap3-ha-common.dtsi" + +/ { + model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; + compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + &powerdown_input_pins + &fpga_boot0_pins + &fpga_boot1_pins + &led_blue_pins + &led_green_pins + &led_red_pins + >; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep.dtsi new file mode 100644 index 000000000000..e068ecf86b8f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common device tree for IGEP boards based on AM/DM37x + * + * Copyright (C) 2012 Javier Martinez Canillas + * Copyright (C) 2012 Enric Balletbo i Serra + */ +/dts-v1/; + +#include "omap36xx.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + chosen { + stdout-path = &uart3; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "igep2"; + ti,mcbsp = <&mcbsp2>; + }; + + vdd33: regulator-vdd33 { + compatible = "regulator-fixed"; + regulator-name = "vdd33"; + regulator-always-on; + }; + +}; + +&omap3_pmx_core { + gpmc_pins: gpmc-pins { + pinctrl-single,pins = < + /* OneNAND seems to require PIN_INPUT on clock. */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29c4g96maz"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + status = "okay"; + }; + + onenand@0,0 { + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-wrap; + gpmc,burst-read; + gpmc,burst-write; + gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ + gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <96>; + gpmc,cs-wr-off-ns = <96>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <18>; + gpmc,oe-off-ns = <96>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <96>; + gpmc,rd-cycle-ns = <114>; + gpmc,wr-cycle-ns = <114>; + gpmc,access-ns = <90>; + gpmc,page-burst-access-ns = <12>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <6>; + gpmc,wr-data-mux-bus-ns = <30>; + gpmc,wr-access-ns = <90>; + gpmc,sync-clk-ps = <12000>; + + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <4>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&twl_gpio { + ti,use-leds; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi new file mode 100644 index 000000000000..13f434625407 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common Device Tree Source for IGEPv2 + * + * Copyright (C) 2014 Javier Martinez Canillas + * Copyright (C) 2014 Enric Balletbo i Serra + */ + +#include "omap3-igep.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + compatible = "gpio-leds"; + + boot { + label = "omap3:green:boot"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user0 { + label = "omap3:red:user0"; + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user1 { + label = "omap3:red:user1"; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user2 { + label = "omap3:green:user1"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; + }; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ + vcc-supply = <&hsusb1_power>; + #phy-cells = <0>; + }; + + tfp410: encoder { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &tfp410_pins + &dss_dpi_pins + >; + + tfp410_pins: tfp410-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + >; + }; + + smsc9221_pins: smsc9221-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins + >; + + hsusbb1_pins: hsusbb1-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + >; + }; + + leds_pins: leds-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ + >; + }; + + mmc1_wp_pins: mmc1-cd-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ + >; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + /* + * Display monitor features are burnt in the EEPROM + * as EDID data. + */ + eeprom@50 { + compatible = "ti,eeprom"; + reg = <0x50>; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ + <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc9221_pins>; + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + +&vpll2 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; +}; + +&dss { + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&mmc1 { + pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; + wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts new file mode 100644 index 000000000000..316e8e6b39cd --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) + * + * Copyright (C) Javier Martinez Canillas + * Copyright (C) 2012 Enric Balletbo i Serra + */ + +#include "omap3-igep0020-common.dtsi" + +/ { + model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap3"; + + /* Regulator to trigger the WL_EN signal of the Wifi module */ + lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbep5clwmc-wlen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ + enable-active-high; + }; +}; + +&omap3_pmx_core { + lbep5clwmc_pins: lbep5clwmc-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; + vmmc-supply = <&lbep5clwmc_wlen>; + bus-width = <4>; + non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ + }; +}; + +&uart2 { + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ + max-speed = <300000>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep0020.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0020.dts new file mode 100644 index 000000000000..232cf9187822 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0020.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) + * + * Copyright (C) 2012 Javier Martinez Canillas + * Copyright (C) 2012 Enric Balletbo i Serra + */ + +#include "omap3-igep0020-common.dtsi" + +/ { + model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap3"; + + vmmcsdio_fixed: fixedregulator-mmcsdio { + compatible = "regulator-fixed"; + regulator-name = "vmmcsdio_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ + <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ + }; +}; + +&omap3_pmx_core { + lbee1usjyc_pins: lbee1usjyc-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ + >; + }; +}; + +/* On board Wifi module */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; + vmmc-supply = <&vmmcsdio_fixed>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi new file mode 100644 index 000000000000..d434f75aadac --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common Device Tree Source for IGEP COM MODULE + * + * Copyright (C) 2014 Javier Martinez Canillas + * Copyright (C) 2014 Enric Balletbo i Serra + */ + +#include "omap3-igep.dtsi" + +/ { + leds: gpio_leds { + compatible = "gpio-leds"; + + user0 { + label = "omap3:red:user0"; + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ + default-state = "off"; + }; + + user1 { + label = "omap3:green:user1"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ + default-state = "off"; + }; + + user2 { + label = "omap3:red:user1"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ + default-state = "off"; + }; + }; + + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + #phy-cells = <0>; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; + + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_core2_pins>; + + hsusb2_core2_pins: hsusb2-core2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + leds_core2_pins: leds-core2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts new file mode 100644 index 000000000000..fddd7c86fec4 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) + * + * Copyright (C) 2014 Javier Martinez Canillas + * Copyright (C) 2014 Enric Balletbo i Serra + */ + +#include "omap3-igep0030-common.dtsi" + +/ { + model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap3"; + + /* Regulator to trigger the WL_EN signal of the Wifi module */ + lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbep5clwmc-wlen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ + enable-active-high; + }; +}; + +&omap3_pmx_core { + lbep5clwmc_pins: lbep5clwmc-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ + >; + }; + + leds_pins: leds-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ + >; + }; + +}; + +&i2c2 { + status = "disabled"; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins &leds_core2_pins>; + + boot { + label = "omap3:green:boot"; + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; + vmmc-supply = <&lbep5clwmc_wlen>; + bus-width = <4>; + non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ + }; +}; + +&uart2 { + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */ + max-speed = <300000>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-igep0030.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0030.dts new file mode 100644 index 000000000000..e3f99dbef2a1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0030.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) + * + * Copyright (C) 2012 Javier Martinez Canillas + * Copyright (C) 2012 Enric Balletbo i Serra + */ + +#include "omap3-igep0030-common.dtsi" + +/ { + model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap3"; + + vmmcsdio_fixed: fixedregulator-mmcsdio { + compatible = "regulator-fixed"; + regulator-name = "vmmcsdio_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ + <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ + }; +}; + +&omap3_pmx_core { + lbee1usjyc_pins: lbee1usjyc-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_core2_pins>; + + boot { + label = "omap3:green:boot"; + gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ + default-state = "on"; + }; +}; + +/* On board Wifi module */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; + vmmc-supply = <&vmmcsdio_fixed>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-ldp.dts b/arch/arm/boot/dts/ti/omap/omap3-ldp.dts new file mode 100644 index 000000000000..bb6fab9fa47d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-ldp.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include +#include "omap34xx.dtsi" +#include "omap-gpmc-smsc911x.dtsi" + +/ { + model = "TI OMAP3430 LDP (Zoom1 Labrador)"; + compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + + key_enter { + label = "enter"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ + linux,code = ; + wakeup-source; + }; + + key_f1 { + label = "f1"; + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ + linux,code = ; + wakeup-source; + }; + + key_f2 { + label = "f2"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ + linux,code = ; + wakeup-source; + }; + + key_f3 { + label = "f3"; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ + linux,code = ; + wakeup-source; + }; + + key_f4 { + label = "f4"; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ + linux,code = ; + wakeup-source; + }; + + key_left { + label = "left"; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ + linux,code = ; + wakeup-source; + }; + + key_right { + label = "right"; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ + linux,code = ; + wakeup-source; + }; + + key_up { + label = "up"; + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ + linux,code = ; + wakeup-source; + }; + + key_down { + label = "down"; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ + linux,code = ; + wakeup-source; + }; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ + <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,nand"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x140000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x1c0000 0x40000>; + }; + partition@200000 { + label = "Kernel"; + reg = <0x200000 0x1e00000>; + }; + partition@2000000 { + label = "Filesystem"; + reg = <0x2000000 0x6000000>; + }; + }; + + ethernet@gpmc { + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + reg = <1 0 0xff>; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_power: power { + compatible = "ti,twl4030-power-idle"; + ti,use_poweroff; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" +#include "omap3-panel-sharp-ls037v7dw01.dtsi" + +&backlight0 { + gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; + +/* tps61130rsa enabled by twl4030 regen */ +&lcd_3v3 { + regulator-always-on; +}; + +&lcd0 { + enable-gpios = <&twl_gpio 15 GPIO_ACTIVE_HIGH>; /* lcd INI */ + reset-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; /* gpio55, lcd RESB */ + mode-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio56, lcd MO */ +}; + +&mcspi1 { + tsc2046@0 { + interrupt-parent = <&gpio2>; + interrupts = <22 0>; /* gpio54 */ + pendown-gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc1 { + /* See 35xx errata 2.1.1.128 in SPRZ278F */ + compatible = "ti,omap3-pre-es3-hsmmc"; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&omap3_pmx_core { + gpio_key_pins: gpio-key-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ + OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ + OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ + >; + }; + + musb_pins: musb-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + >; + }; +}; + +&twl_keypad { + linux,keymap = ; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&musb_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; + +&vaux1 { + /* Needed for ads7846 */ + regulator-name = "vcc"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi new file mode 100644 index 000000000000..005a3d67f3ed --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Christoph Fritz + */ + +#include "omap36xx.dtsi" + +/ { + model = "INCOstartec LILLY-A83X module (DM3730)"; + compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + + chosen { + bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "lilly-a83x::led1"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "lilly-a83x"; + + ti,mcbsp = <&mcbsp2>; + }; + + reg_vcc3: vcc3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_vcc3>; + #phy-cells = <0>; + }; +}; + +&omap3_pmx_wkup { + pinctrl-names = "default"; + + lan9221_pins: lan9221-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ + >; + }; + + tsc2048_pins: tsc2048-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ + >; + }; + + mmc1cd_pins: mmc1cd-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + hsusb1_pins: hsusb1-pins { + pinctrl-single,pins = < + + /* GPIO 182 controls USB-Hub reset. But USB-Phy its + * reset can't be controlled. So we clamp this GPIO to + * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. + */ + + OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ + >; + }; + + hsusb_otg_pins: hsusb-otg-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + spi2_pins: spi2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + + hsusb1_2_pins: hsusb1-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + >; + }; + + gpio1_pins: gpio1-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ + >; + }; + +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&gpio6 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; +}; + +&i2c1 { + clock-frequency = <2600000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl { + vmmc1: regulator-vmmc1 { + regulator-always-on; + }; + + vdd1: regulator-vdd1 { + regulator-always-on; + }; + + vdd2: regulator-vdd2 { + regulator-always-on; + }; +}; + +&i2c2 { + clock-frequency = <2600000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + clock-frequency = <2600000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + gpiom1: gpio@20 { + compatible = "microchip,mcp23017"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + status = "disabled"; +}; + +&mmc1 { + cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + cd-inverted; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mcspi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + + tsc2046@0 { + reg = <0>; /* CS0 */ + compatible = "ti,tsc2046"; + interrupt-parent = <&gpio1>; + interrupts = <8 0>; /* boot6 / gpio_8 */ + spi-max-frequency = <1000000>; + pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_vcc3>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2048_pins>; + + ti,x-min = /bits/ 16 <300>; + ti,x-max = /bits/ 16 <3000>; + ti,y-min = /bits/ 16 <600>; + ti,y-max = /bits/ 16 <3600>; + ti,x-plate-ohms = /bits/ 16 <80>; + ti,pressure-max = /bits/ 16 <255>; + ti,swap-xy; + + wakeup-source; + }; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + +&usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_2_pins>; + num-ports = <2>; + port1-mode = "ehci-phy"; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&mcbsp2 { + status = "okay"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, + <7 0 0x15000000 0x01000000>; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + /* no elm on omap3 */ + + gpmc,mux-add-data = <0>; + gpmc,device-width = <2>; + gpmc,wait-pin = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,burst-length = <4>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <100>; + gpmc,cs-wr-off-ns = <100>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <100>; + gpmc,adv-wr-off-ns = <100>; + gpmc,oe-on-ns = <5>; + gpmc,oe-off-ns = <75>; + gpmc,we-on-ns = <5>; + gpmc,we-off-ns = <75>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <60>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,wr-data-mux-bus-ns = <75>; + gpmc,wr-access-ns = <155>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MLO"; + reg = <0 0x80000>; + }; + + partition@80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + + partition@260000 { + label = "u-boot-environment"; + reg = <0x260000 0x20000>; + }; + + partition@280000 { + label = "kernel"; + reg = <0x280000 0x500000>; + }; + + partition@780000 { + label = "filesystem"; + reg = <0x780000 0xf880000>; + }; + }; + + ethernet@7,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + bank-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <60>; + gpmc,cs-wr-off-ns = <60>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <60>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <50>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wr-data-mux-bus-ns = <15>; + gpmc,wr-access-ns = <75>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <®_vcc3>; + vdd33a-supply = <®_vcc3>; + reg-io-width = <4>; + interrupt-parent = <&gpio5>; + interrupts = <1 0x2>; + reg = <7 0 0xff>; + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + phy-mode = "mii"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts new file mode 100644 index 000000000000..0891c6682a67 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Christoph Fritz + */ +/dts-v1/; + +#include "omap3-lilly-a83x.dtsi" + +/ { + model = "INCOstartec LILLY-DBB056 (DM3730)"; + compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap3"; +}; + +&twl { + vaux2: regulator-vaux2 { + compatible = "ti,twl4030-vaux2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + lan9117_pins: lan9117-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ + >; + }; + + gpio4_pins: gpio4-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ + >; + }; + + gpio5_pins: gpio5-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ + OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ + >; + }; + + spi1_pins: spi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio4_pins>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio5_pins>; +}; + +&mmc2 { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc1>; + cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ + wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + ti,dual-volt; +}; + +&mcspi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ + <4 0 0x20000000 0x01000000>, + <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + bank-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <65>; + gpmc,cs-wr-off-ns = <65>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <65>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <65>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <60>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wr-data-mux-bus-ns = <15>; + gpmc,wr-access-ns = <75>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <®_vcc3>; + vdd33a-supply = <®_vcc3>; + reg-io-width = <4>; + interrupt-parent = <&gpio4>; + interrupts = <2 0x2>; + reg = <4 0 0xff>; + pinctrl-names = "default"; + pinctrl-0 = <&lan9117_pins>; + phy-mode = "mii"; + smsc,force-internal-phy; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-n9.dts b/arch/arm/boot/dts/ti/omap/omap3-n9.dts new file mode 100644 index 000000000000..a3cf3f443785 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-n9.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * omap3-n9.dts - Device Tree file for Nokia N9 + * + * Written by: Aaro Koskinen + */ + +/dts-v1/; + +#include "omap3-n950-n9.dtsi" +#include + +/ { + model = "Nokia N9"; + compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap3"; +}; + +&i2c2 { + smia_1: camera@10 { + compatible = "nokia,smia"; + reg = <0x10>; + /* No reset gpio */ + vana-supply = <&vaux3>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + flash-leds = <&as3645a_flash &as3645a_indicator>; + port { + smia_1_1: endpoint { + link-frequencies = /bits/ 64 <199200000 210000000 499200000>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + }; + }; + }; +}; + +&i2c3 { + ak8975@f { + compatible = "asahi-kasei,ak8975"; + reg = <0x0f>; + }; +}; + +&isp { + vdd-csiphy1-supply = <&vaux2>; + vdd-csiphy2-supply = <&vaux2>; + ports { + port@2 { + reg = <2>; + csi2a_ep: endpoint { + remote-endpoint = <&smia_1_1>; + clock-lanes = <2>; + data-lanes = <1 3>; + crc = <1>; + lane-polarities = <1 1 1>; + }; + }; + }; +}; + +&modem { + compatible = "nokia,n9-modem"; +}; + +&lis302 { + st,axis-x = <1>; /* LIS3_DEV_X */ + st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ + st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ + + st,min-limit-x = <(-46)>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + + st,max-limit-x = <(-3)>; + st,max-limit-y = <46>; + st,max-limit-z = <46>; +}; + +&twl_keypad { + linux,keymap = < MATRIX_KEY(6, 8, KEY_VOLUMEUP) + MATRIX_KEY(7, 8, KEY_VOLUMEDOWN) + >; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts new file mode 100644 index 000000000000..d33485341251 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-n900.dts @@ -0,0 +1,1159 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2013 Pavel Machek + * Copyright (C) 2013-2014 Aaro Koskinen + */ + +/dts-v1/; + +#include "omap34xx.dtsi" +#include +#include +#include + +/* + * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall + * for omap AES HW crypto support. When linux kernel try to access memory of AES + * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" + * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no + * crash anymore) omap AES support will be disabled for all Nokia N900 devices. + * There is "unofficial" version of bootloader which enables AES in L3 firewall + * but it is not widely used and to prevent kernel crash rather AES is disabled. + * There is also no runtime detection code if AES is disabled in L3 firewall... + */ +&aes1_target { + status = "disabled"; +}; + +&aes2_target { + status = "disabled"; +}; + +/ { + model = "Nokia N900"; + compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; + + aliases { + i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + display0 = &lcd; + display1 = &tv; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-heartbeat { + label = "debug::sleep"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */ + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&debug_leds>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + gpio_keys { + compatible = "gpio-keys"; + + camera_lens_cover { + label = "Camera Lens Cover"; + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + + camera_focus { + label = "Camera Focus"; + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ + linux,code = ; + linux,can-disable; + }; + + camera_capture { + label = "Camera Capture"; + gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ + linux,code = ; + linux,can-disable; + }; + + lock_button { + label = "Lock Button"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ + linux,code = ; + linux,can-disable; + }; + + keypad_slide { + label = "Keypad Slide"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + + proximity_sensor { + label = "Proximity Sensor"; + gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + + machine_cover { + label = "Machine Cover"; + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + + isp1707: isp1707 { + compatible = "nxp,isp1707"; + nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + usb-phy = <&usb2_phy>; + }; + + tv: connector { + compatible = "composite-video-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + sound: n900-audio { + compatible = "nokia,n900-audio"; + + nokia,cpu-dai = <&mcbsp2>; + nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; + nokia,headphone-amplifier = <&tpa6130a2>; + + tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ + jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ + eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ + speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; + }; + + battery: n900-battery { + compatible = "nokia,n900-battery"; + io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; + io-channel-names = "temp", "bsi", "vbat"; + }; + + pwm9: pwm-9 { + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer9>; + ti,clock-source = <0x00>; /* timer_sys_ck */ + }; + + ir: n900-ir { + compatible = "nokia,n900-ir"; + pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ + }; + + rom_rng: rng { + compatible = "nokia,n900-rom-rng"; + clocks = <&rng_ick>; + clock-names = "ick"; + }; + + /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */ + vctcxo: vctcxo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&isp { + vdds_csib-supply = <&vaux2>; + + pinctrl-names = "default"; + pinctrl-0 = <&camera_pins>; + + ports { + port@1 { + reg = <1>; + + csi_isp: endpoint { + remote-endpoint = <&csi_cam1>; + bus-type = ; + clock-lanes = <1>; + data-lanes = <0>; + lane-polarity = <0 0>; + /* Select strobe = <1> for back camera, <0> for front camera */ + strobe = <1>; + }; + }; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ + >; + }; + + ethernet_pins: ethernet-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ + >; + }; + + gpmc_pins: gpmc-pins { + pinctrl-single,pins = < + + /* address lines */ + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + + /* data lines, gpmc_d0..d7 not muxable according to TRM */ + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + + /* + * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable + * according to TRM. OneNAND seems to require PIN_INPUT on clock. + */ + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + + debug_leds: debug-led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ + >; + }; + + mcspi4_pins: mcspi4-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ + OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ + OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ + >; + }; + + acx565akm_pins: acx565akm-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ + >; + }; + + dss_sdi_pins: dss-sdi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ + + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ + >; + }; + + wl1251_pins: wl1251-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ + OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ + >; + }; + + ssi_pins: ssi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ + >; + }; + + modem_pins: modem-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ + >; + }; + + camera_pins: camera-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ + OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ + OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ + OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */ + OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */ + OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */ + OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */ + OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */ + OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <2200000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&vaux1 { + regulator-name = "V28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ + regulator-always-on; /* due to battery cover sensor */ +}; + +&vaux2 { + regulator-name = "VCSI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +}; + +&vaux3 { + regulator-name = "VMMC2_30"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +}; + +&vaux4 { + regulator-name = "VCAM_ANA_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +}; + +&vmmc1 { + regulator-name = "VMMC1"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +}; + +&vmmc2 { + regulator-name = "V28_A"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ + regulator-always-on; /* due VIO leak to AIC34 VDDs */ +}; + +&vpll1 { + regulator-name = "VPLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ + regulator-always-on; +}; + +&vpll2 { + regulator-name = "VSDI_CSI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ + regulator-always-on; +}; + +&vsim { + regulator-name = "VMMC2_IO_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ +}; + +&vio { + regulator-name = "VIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vintana1 { + regulator-name = "VINTANA1"; + /* fixed to 1500000 */ + regulator-always-on; +}; + +&vintana2 { + regulator-name = "VINTANA2"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; +}; + +&vintdig { + regulator-name = "VINTDIG"; + /* fixed to 1500000 */ + regulator-always-on; +}; + +/* First two dma channels are reserved on secure omap3 */ +&sdma { + dma-channel-mask = <0xfffffffc>; +}; + +&twl { + twl_audio: audio { + compatible = "ti,twl4030-audio"; + ti,enable-vibra = <1>; + }; + + twl_power: power { + compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; + ti,use_poweroff; + }; +}; + +&twl_keypad { + linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) + MATRIX_KEY(0x00, 0x01, KEY_O) + MATRIX_KEY(0x00, 0x02, KEY_P) + MATRIX_KEY(0x00, 0x03, KEY_COMMA) + MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) + MATRIX_KEY(0x00, 0x06, KEY_A) + MATRIX_KEY(0x00, 0x07, KEY_S) + + MATRIX_KEY(0x01, 0x00, KEY_W) + MATRIX_KEY(0x01, 0x01, KEY_D) + MATRIX_KEY(0x01, 0x02, KEY_F) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_H) + MATRIX_KEY(0x01, 0x05, KEY_J) + MATRIX_KEY(0x01, 0x06, KEY_K) + MATRIX_KEY(0x01, 0x07, KEY_L) + + MATRIX_KEY(0x02, 0x00, KEY_E) + MATRIX_KEY(0x02, 0x01, KEY_DOT) + MATRIX_KEY(0x02, 0x02, KEY_UP) + MATRIX_KEY(0x02, 0x03, KEY_ENTER) + MATRIX_KEY(0x02, 0x05, KEY_Z) + MATRIX_KEY(0x02, 0x06, KEY_X) + MATRIX_KEY(0x02, 0x07, KEY_C) + MATRIX_KEY(0x02, 0x08, KEY_F9) + + MATRIX_KEY(0x03, 0x00, KEY_R) + MATRIX_KEY(0x03, 0x01, KEY_V) + MATRIX_KEY(0x03, 0x02, KEY_B) + MATRIX_KEY(0x03, 0x03, KEY_N) + MATRIX_KEY(0x03, 0x04, KEY_M) + MATRIX_KEY(0x03, 0x05, KEY_SPACE) + MATRIX_KEY(0x03, 0x06, KEY_SPACE) + MATRIX_KEY(0x03, 0x07, KEY_LEFT) + + MATRIX_KEY(0x04, 0x00, KEY_T) + MATRIX_KEY(0x04, 0x01, KEY_DOWN) + MATRIX_KEY(0x04, 0x02, KEY_RIGHT) + MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) + MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) + MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) + MATRIX_KEY(0x04, 0x08, KEY_F10) + + MATRIX_KEY(0x05, 0x00, KEY_Y) + MATRIX_KEY(0x05, 0x08, KEY_F11) + + MATRIX_KEY(0x06, 0x00, KEY_U) + + MATRIX_KEY(0x07, 0x00, KEY_I) + MATRIX_KEY(0x07, 0x01, KEY_F7) + MATRIX_KEY(0x07, 0x02, KEY_F8) + >; +}; + +&twl_gpio { + ti,pullups = <0x0>; + ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <100000>; + + tlv320aic3x: tlv320aic3x@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ + ai3x-gpio-func = < + 0 /* AIC3X_GPIO1_FUNC_DISABLED */ + 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ + >; + + AVDD-supply = <&vmmc2>; + DRVDD-supply = <&vmmc2>; + IOVDD-supply = <&vio>; + DVDD-supply = <&vio>; + + ai3x-micbias-vg = <1>; + }; + + tlv320aic3x_aux: tlv320aic3x@19 { + compatible = "ti,tlv320aic3x"; + reg = <0x19>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ + + AVDD-supply = <&vmmc2>; + DRVDD-supply = <&vmmc2>; + IOVDD-supply = <&vio>; + DVDD-supply = <&vio>; + + ai3x-micbias-vg = <2>; + }; + + tsl2563: tsl2563@29 { + compatible = "amstaos,tsl2563"; + reg = <0x29>; + + amstaos,cover-comp-gain = <16>; + }; + + adp1653: led-controller@30 { + compatible = "adi,adp1653"; + reg = <0x30>; + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ + + flash { + flash-timeout-us = <500000>; + flash-max-microamp = <320000>; + led-max-microamp = <50000>; + }; + indicator { + led-max-microamp = <17500>; + }; + }; + + lp5523: lp5523@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "national,lp5523"; + reg = <0x32>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + enable-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ + + led@0 { + reg = <0>; + chan-name = "lp5523:kb1"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + + led@1 { + reg = <1>; + chan-name = "lp5523:kb2"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + + led@2 { + reg = <2>; + chan-name = "lp5523:kb3"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + + led@3 { + reg = <3>; + chan-name = "lp5523:kb4"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + + led@4 { + reg = <4>; + chan-name = "lp5523:b"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led@5 { + reg = <5>; + chan-name = "lp5523:g"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led@6 { + reg = <6>; + chan-name = "lp5523:r"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led@7 { + reg = <7>; + chan-name = "lp5523:kb5"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + + led@8 { + reg = <8>; + chan-name = "lp5523:kb6"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + }; + + bq27200: bq27200@55 { + compatible = "ti,bq27200"; + reg = <0x55>; + power-supplies = <&bq24150a>; + }; + + /* Stereo headphone amplifier */ + tpa6130a2: tpa6130a2@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + + Vdd-supply = <&vmmc2>; + + power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ + }; + + si4713: si4713@63 { + compatible = "silabs,si4713"; + reg = <0x63>; + + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ + reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ + vio-supply = <&vio>; + vdd-supply = <&vaux1>; + }; + + bq24150a: bq24150a@6b { + compatible = "ti,bq24150a"; + reg = <0x6b>; + + ti,current-limit = <100>; + ti,weak-battery-voltage = <3400>; + ti,battery-regulation-voltage = <4200>; + ti,charge-current = <650>; + ti,termination-current = <100>; + ti,resistor-sense = <68>; + + ti,usb-charger-detection = <&isp1707>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; + + accelerometer@1d { + compatible = "st,lis302dl"; + reg = <0x1d>; + + vdd-supply = <&vaux1>; + vddio-supply = <&vio>; + + interrupt-parent = <&gpio6>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>, + <20 IRQ_TYPE_EDGE_RISING>; /* 181 and 180 */ + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + + cam1: camera@3e { + compatible = "toshiba,et8ek8"; + reg = <0x3e>; + + vana-supply = <&vaux4>; + + clocks = <&isp 0>; + clock-names = "extclk"; + clock-frequency = <9600000>; + + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ + + lens-focus = <&ad5820>; + + port { + csi_cam1: endpoint { + bus-type = ; + strobe = <1>; + clock-inv = <0>; + crc = <1>; + + remote-endpoint = <&csi_isp>; + }; + }; + }; + + /* D/A converter for auto-focus */ + ad5820: dac@c { + compatible = "adi,ad5820"; + reg = <0x0c>; + + VANA-supply = <&vaux4>; + + #io-channel-cells = <0>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +/* most boards use vaux3, only some old versions use vmmc2 instead */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vaux3>; + vqmmc-supply = <&vsim>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; +}; + +&mmc3 { + status = "disabled"; +}; + +&gpmc { + ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ + <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + + /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ + onenand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + + /* + * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported + * bootloader set values when booted with v5.1 + * (OneNAND Manufacturer: Samsung): + * + * cs0 GPMC_CS_CONFIG1: 0xfb001202 + * cs0 GPMC_CS_CONFIG2: 0x00111100 + * cs0 GPMC_CS_CONFIG3: 0x00020200 + * cs0 GPMC_CS_CONFIG4: 0x11001102 + * cs0 GPMC_CS_CONFIG5: 0x03101616 + * cs0 GPMC_CS_CONFIG6: 0x90060000 + */ + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,burst-write; + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <102>; + gpmc,cs-wr-off-ns = <102>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <102>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <102>; + gpmc,rd-cycle-ns = <132>; + gpmc,wr-cycle-ns = <132>; + gpmc,access-ns = <96>; + gpmc,page-burst-access-ns = <18>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <6>; + gpmc,wr-data-mux-bus-ns = <36>; + gpmc,wr-access-ns = <96>; + gpmc,sync-clk-ps = <15000>; + + /* + * MTD partition table corresponding to Nokia's + * Maemo 5 (Fremantle) release. + */ + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@1 { + label = "config"; + reg = <0x00020000 0x00060000>; + }; + partition@2 { + label = "log"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "kernel"; + reg = <0x000c0000 0x00200000>; + }; + partition@4 { + label = "initfs"; + reg = <0x002c0000 0x00200000>; + }; + partition@5 { + label = "rootfs"; + reg = <0x004c0000 0x0fb40000>; + }; + }; + + /* Ethernet is on some early development boards and qemu */ + ethernet@gpmc { + compatible = "smsc,lan91c94"; + interrupt-parent = <&gpio2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ + reg = <1 0 0xf>; /* 16 byte IO range */ + bank-width = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ + reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <48>; + gpmc,cs-wr-off-ns = <24>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,we-on-ns = <12>; + gpmc,we-off-ns = <18>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <48>; + gpmc,page-burst-access-ns = <0>; + gpmc,access-ns = <42>; + gpmc,rd-cycle-ns = <180>; + gpmc,wr-cycle-ns = <180>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <12>; + }; +}; + +&mcspi1 { + /* + * For some reason, touchscreen is necessary for screen to work at + * all on real hw. It works well without it on emulator. + * + * Also... order in the device tree actually matters here. + */ + tsc2005@0 { + compatible = "ti,tsc2005"; + spi-max-frequency = <6000000>; + reg = <0>; + + vio-supply = <&vio>; + + reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ + interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ + + touchscreen-fuzz-x = <4>; + touchscreen-fuzz-y = <7>; + touchscreen-fuzz-pressure = <2>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + touchscreen-max-pressure = <2048>; + + ti,x-plate-ohms = <280>; + ti,esd-recovery-timeout-ms = <8000>; + }; + + lcd: acx565akm@2 { + compatible = "sony,acx565akm"; + spi-max-frequency = <6000000>; + reg = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&acx565akm_pins>; + + label = "lcd"; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&sdi_out>; + }; + }; + }; +}; + +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi4_pins>; + + wl1251@0 { + pinctrl-names = "default"; + pinctrl-0 = <&wl1251_pins>; + + vio-supply = <&vio>; + + compatible = "ti,wl1251"; + reg = <0>; + spi-max-frequency = <48000000>; + + spi-cpol; + spi-cpha; + + ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ + + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ + + clocks = <&vctcxo>; + }; +}; + +/* RNG not directly accessible on n900, see omap3-rom-rng instead */ +&rng_target { + status = "disabled"; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <2>; + power = <50>; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + bcm2048: bluetooth { + compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth"; + reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */ + host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ + bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ + clocks = <&vctcxo>; + clock-names = "sysclk"; + }; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_sdi_pins>; + + vdds_sdi-supply = <&vaux1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + sdi_out: endpoint { + remote-endpoint = <&lcd_in>; + datapairs = <2>; + }; + }; + }; +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <1>; + }; + }; +}; + +&mcbsp2 { + status = "okay"; +}; + +&ssi_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&ssi_pins>; + + ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ + + modem: hsi-client { + compatible = "nokia,n900-modem"; + + pinctrl-names = "default"; + pinctrl-0 = <&modem_pins>; + + hsi-channel-ids = <0>, <1>, <2>, <3>; + hsi-channel-names = "mcsaab-control", + "speech-control", + "speech-data", + "mcsaab-data"; + hsi-speed-kbps = <55000>; + hsi-mode = "frame"; + hsi-flow = "synchronized"; + hsi-arb-mode = "round-robin"; + + interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ + + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ + <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ + <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ + <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ + <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ + gpio-names = "cmt_apeslpx", + "cmt_rst_rq", + "cmt_en", + "cmt_rst", + "cmt_bsi"; + }; +}; + +&ssi_port2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi new file mode 100644 index 000000000000..aa4fcdbedd8f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) + * + * Written by: Aaro Koskinen + */ + +#include "omap36xx.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vemmc: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "VEMMC"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */ + startup-delay-us = <150>; + enable-active-high; + }; + + vwlan_fixed: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "VWLAN"; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "debug::sleep"; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&debug_leds>; + }; + }; + + /* controlled (enabled/disabled) directly by wl1271 */ + vctcxo: vctcxo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&omap3_pmx_core { + accelerator_pins: accelerator-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ + >; + }; + + debug_leds: debug-led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ + >; + }; + + wlan_pins: wlan-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ + OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ + >; + }; + + ssi_pins: ssi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ + >; + }; + + ssi_pins_idle: ssi-idle-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ + >; + }; + + modem_pins1: modem-core1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ + >; + }; +}; + +&omap3_pmx_core2 { + modem_pins2: modem-core2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2900000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +&twl { + compatible = "ti,twl5031"; + + twl_power: power { + compatible = "ti,twl4030-power"; + ti,use_poweroff; + }; +}; + +&twl_gpio { + ti,pullups = <0x000001>; /* BIT(0) */ + ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ +}; + +&vdac { + regulator-name = "vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vpll1 { + regulator-name = "vpll1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vpll2 { + regulator-name = "vpll2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vaux1 { + regulator-name = "vaux1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* CSI-2 receiver */ +&vaux2 { + regulator-name = "vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +/* Cameras */ +&vaux3 { + regulator-name = "vaux3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&vaux4 { + regulator-name = "vaux4"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&vmmc1 { + regulator-name = "vmmc1"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; +}; + +&vmmc2 { + regulator-name = "vmmc2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vintana1 { + regulator-name = "vintana1"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; + +&vintana2 { + regulator-name = "vintana2"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; +}; + +&vintdig { + regulator-name = "vintdig"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; + +&vsim { + regulator-name = "vsim"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vio { + regulator-name = "vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&i2c2 { + clock-frequency = <400000>; + + as3645a@30 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30>; + compatible = "ams,as3645a"; + as3645a_flash: flash@0 { + reg = <0x0>; + flash-timeout-us = <150000>; + flash-max-microamp = <320000>; + led-max-microamp = <60000>; + ams,input-max-microamp = <1750000>; + }; + as3645a_indicator: indicator@1 { + reg = <0x1>; + led-max-microamp = <10000>; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + lis302: lis302@1d { + compatible = "st,lis3lv02d"; + reg = <0x1d>; + + Vdd-supply = <&vaux1>; + Vdd_IO-supply = <&vio>; + + pinctrl-names = "default"; + pinctrl-0 = <&accelerator_pins>; + + interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ + + /* click flags */ + st,click-single-x; + st,click-single-y; + st,click-single-z; + + /* Limits are 0.5g * value */ + st,click-threshold-x = <8>; + st,click-threshold-y = <8>; + st,click-threshold-z = <10>; + + /* Click must be longer than time limit */ + st,click-time-limit = <9>; + + /* Kind of debounce filter */ + st,click-latency = <50>; + + st,wakeup-x-hi; + st,wakeup-y-hi; + st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ + + st,wakeup2-z-hi; + st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ + + st,highpass-cutoff-hz = <2>; + + /* Interrupt line 1 for thresholds */ + st,irq1-ff-wu-1; + st,irq1-ff-wu-2; + /* Interrupt line 2 for click detection */ + st,irq2-click; + + st,wu-duration-1 = <8>; + st,wu-duration-2 = <8>; + }; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vemmc>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc3 { + status = "disabled"; +}; + +/* RNG not directly accessible on N950/N9. */ +&rng_target { + status = "disabled"; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ + + onenand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + + /* + * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported + * bootloader set values when booted with v4.19 using both N950 + * and N9 devices (OneNAND Manufacturer: Samsung): + * + * gpmc cs0 before gpmc_cs_program_settings: + * cs0 GPMC_CS_CONFIG1: 0xfd001202 + * cs0 GPMC_CS_CONFIG2: 0x00181800 + * cs0 GPMC_CS_CONFIG3: 0x00030300 + * cs0 GPMC_CS_CONFIG4: 0x18001804 + * cs0 GPMC_CS_CONFIG5: 0x03171d1d + * cs0 GPMC_CS_CONFIG6: 0x97080000 + */ + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,burst-write; + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <122>; + gpmc,cs-wr-off-ns = <122>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <15>; + gpmc,oe-on-ns = <20>; + gpmc,oe-off-ns = <122>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <122>; + gpmc,rd-cycle-ns = <148>; + gpmc,wr-cycle-ns = <148>; + gpmc,access-ns = <117>; + gpmc,page-burst-access-ns = <15>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <10>; + gpmc,wr-data-mux-bus-ns = <40>; + gpmc,wr-access-ns = <117>; + + gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */ + + /* + * MTD partition table corresponding to Nokia's MeeGo 1.2 + * Harmattan release. + */ + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "config"; + reg = <0x00100000 0x002c0000>; + }; + partition@2 { + label = "kernel"; + reg = <0x003c0000 0x01000000>; + }; + partition@3 { + label = "log"; + reg = <0x013c0000 0x00200000>; + }; + partition@4 { + label = "var"; + reg = <0x015c0000 0x1ca40000>; + }; + partition@5 { + label = "moslo"; + reg = <0x1e000000 0x02000000>; + }; + partition@6 { + label = "omap2-onenand"; + reg = <0x00000000 0x20000000>; + }; + }; +}; + +&ssi_port1 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&ssi_pins>; + pinctrl-1 = <&ssi_pins_idle>; + + ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ + + modem: hsi-client { + pinctrl-names = "default"; + pinctrl-0 = <&modem_pins1 &modem_pins2>; + + hsi-channel-ids = <0>, <1>, <2>, <3>; + hsi-channel-names = "mcsaab-control", + "speech-control", + "speech-data", + "mcsaab-data"; + hsi-speed-kbps = <96000>; + hsi-mode = "frame"; + hsi-flow = "synchronized"; + hsi-arb-mode = "round-robin"; + + interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ + + gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ + <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ + <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ + gpio-names = "cmt_apeslpx", + "cmt_rst_rq", + "cmt_en"; + }; +}; + +&ssi_port2 { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + bluetooth { + compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth"; + + reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */ + host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ + bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ + + clocks = <&vctcxo>; + clock-names = "sysclk"; + }; +}; + +&aes1_target { + status = "disabled"; +}; + +&aes2_target { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-n950.dts b/arch/arm/boot/dts/ti/omap/omap3-n950.dts new file mode 100644 index 000000000000..b99f97880204 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-n950.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * omap3-n950.dts - Device Tree file for Nokia N950 + * + * Written by: Aaro Koskinen + */ + +/dts-v1/; + +#include "omap3-n950-n9.dtsi" +#include + +/ { + model = "Nokia N950"; + compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap3"; + + keys { + compatible = "gpio-keys"; + + keypad_slide { + label = "Keypad Slide"; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ + linux,input-type = ; + linux,code = ; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_slide_pins>; + }; + }; +}; + +&omap3_pmx_core { + keypad_slide_pins: debug-led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ + >; + }; +}; + +&omap3_pmx_core { + spi4_pins: spi4-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ + OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ + OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ + >; + }; +}; + +&omap3_pmx_core { + dsi_pins: dsi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - data1+ */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ + >; + }; + + display_pins: display-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ + >; + }; +}; + +&i2c2 { + smia_1: camera@10 { + compatible = "nokia,smia"; + reg = <0x10>; + /* No reset gpio */ + vana-supply = <&vaux3>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + flash-leds = <&as3645a_flash &as3645a_indicator>; + port { + smia_1_1: endpoint { + link-frequencies = /bits/ 64 <210000000 333600000 398400000>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + }; + }; + }; +}; + +&isp { + vdd-csiphy1-supply = <&vaux2>; + vdd-csiphy2-supply = <&vaux2>; + ports { + port@2 { + reg = <2>; + csi2a_ep: endpoint { + remote-endpoint = <&smia_1_1>; + clock-lanes = <2>; + data-lanes = <3 1>; + crc = <1>; + lane-polarities = <1 1 1>; + }; + }; + }; +}; + +&mcspi4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + + wlcore: wlcore@0 { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pins>; + reg = <0>; + spi-max-frequency = <48000000>; + clock-xtal; + ref-clock-frequency = <38400000>; + interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ + vwlan-supply = <&vwlan_fixed>; + }; +}; + +&modem { + compatible = "nokia,n950-modem"; +}; + +&twl { + twl_audio: audio { + compatible = "ti,twl4030-audio"; + ti,enable-vibra = <1>; + }; +}; + +&twl_keypad { + linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) + MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) + MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) + MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) + MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) + + MATRIX_KEY(0x03, 0x01, KEY_Z) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x05, 0x01, KEY_Q) + MATRIX_KEY(0x06, 0x01, KEY_W) + MATRIX_KEY(0x07, 0x01, KEY_E) + + MATRIX_KEY(0x03, 0x02, KEY_X) + MATRIX_KEY(0x04, 0x02, KEY_S) + MATRIX_KEY(0x05, 0x02, KEY_D) + MATRIX_KEY(0x06, 0x02, KEY_C) + MATRIX_KEY(0x07, 0x02, KEY_V) + + MATRIX_KEY(0x03, 0x03, KEY_O) + MATRIX_KEY(0x04, 0x03, KEY_I) + MATRIX_KEY(0x05, 0x03, KEY_U) + MATRIX_KEY(0x06, 0x03, KEY_L) + MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) + + MATRIX_KEY(0x03, 0x04, KEY_Y) + MATRIX_KEY(0x04, 0x04, KEY_K) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x06, 0x04, KEY_H) + MATRIX_KEY(0x07, 0x04, KEY_G) + + MATRIX_KEY(0x03, 0x05, KEY_B) + MATRIX_KEY(0x04, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x05, KEY_M) + MATRIX_KEY(0x06, 0x05, KEY_N) + MATRIX_KEY(0x07, 0x05, KEY_DOT) + + MATRIX_KEY(0x00, 0x06, KEY_SPACE) + MATRIX_KEY(0x03, 0x06, KEY_T) + MATRIX_KEY(0x04, 0x06, KEY_UP) + MATRIX_KEY(0x05, 0x06, KEY_LEFT) + MATRIX_KEY(0x06, 0x06, KEY_RIGHT) + MATRIX_KEY(0x07, 0x06, KEY_DOWN) + + MATRIX_KEY(0x03, 0x07, KEY_P) + MATRIX_KEY(0x04, 0x07, KEY_ENTER) + MATRIX_KEY(0x05, 0x07, KEY_SLASH) + MATRIX_KEY(0x06, 0x07, KEY_F) + MATRIX_KEY(0x07, 0x07, KEY_R) + >; +}; + +&lis302 { + st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ + st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ + st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ + + st,min-limit-x = <(-32)>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + + st,max-limit-x = <(-3)>; + st,max-limit-y = <32>; + st,max-limit-z = <32>; +}; + +&dss { + status = "okay"; + + vdda_video-supply = <&vdac>; +}; + +&dsi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dsi_pins>; + + vdd-supply = <&vpll2>; + + port { + dsi_out_ep: endpoint { + remote-endpoint = <&lcd0_in>; + lanes = <2 3 0 1 4 5>; + }; + }; + + lcd0: panel@0 { + compatible = "nokia,himalaya", "panel-dsi-cm"; + reg = <0>; + label = "lcd0"; + + pinctrl-names = "default"; + pinctrl-0 = <&display_pins>; + + vpnl-supply = <&vmmc2>; + vddi-supply = <&vio>; + + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ + te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ + + width-mm = <49>; /* 48.960 mm */ + height-mm = <88>; /* 88.128 mm */ + + /* TODO: + * - panel is upside-down + * - top + bottom 5px are not visible + */ + panel-timing { + clock-frequency = <0>; /* Calculated by dsi */ + + hback-porch = <2>; + hactive = <480>; + hfront-porch = <0>; + hsync-len = <2>; + + vback-porch = <1>; + vactive = <864>; + vfront-porch = <0>; + vsync-len = <1>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd0_in: endpoint { + remote-endpoint = <&dsi_out_ep>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi new file mode 100644 index 000000000000..7f1671bf3dfa --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Alto35 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-lcd35.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + led-gpio148 { + label = "overo:red:gpio148"; + gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ + }; + led-gpio150 { + label = "overo:yellow:gpio150"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ + }; + led-gpio151 { + label = "overo:blue:gpio151"; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ + }; + led-gpio170 { + label = "overo:green:gpio170"; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + button0 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ + wakeup-source; + }; + }; +}; + +&omap3_pmx_core { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ + OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ + OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; +}; + +&omap3_pmx_wkup { + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ + >; + }; +}; + +&usbhshost { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts new file mode 100644 index 000000000000..37c64dd5f672 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Alto35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-alto35-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Alto35"; + compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi new file mode 100644 index 000000000000..cc57626ea607 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + */ + +/* + * The Gumstix Overo must be combined with an expansion board. + */ + +/ { + + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + label = "overo:blue:COM"; + pwms = <&twl_pwmled 1 7812500>; + max-brightness = <127>; + linux,default-trigger = "mmc0"; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "overo"; + + ti,mcbsp = <&mcbsp2>; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + /* Regulator to trigger the nPoweron signal of the Wifi module */ + w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { + compatible = "regulator-fixed"; + regulator-name = "regulator-w3cbw003c-npoweron"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */ + enable-active-high; + }; + + /* Regulator to trigger the nReset signal of the Wifi module */ + w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset { + pinctrl-names = "default"; + pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>; + compatible = "regulator-fixed"; + regulator-name = "regulator-w3cbw003c-wifi-nreset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ + startup-delay-us = <10000>; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + /* WiFi/BT combo */ + w3cbw003c_pins: w3cbw003c-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ + >; + }; + + hsusb2_pins: hsusb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +/* i2c2 pins are used for gpio */ +&i2c2 { + status = "disabled"; +}; + +/* on board microSD slot */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +/* optional on board WiFi */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&w3cbw003c_npoweron>; + vqmmc-supply = <&w3cbw003c_wifi_nreset>; + bus-width = <4>; + cap-sdio-irq; + non-removable; +}; + +&twl_gpio { + ti,use-leds; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&mcbsp2 { + status = "okay"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* CS0 */ + <4 0 0x2b000000 0x1000000>, /* CS4 */ + <5 0 0x2c000000 0x1000000>; /* CS5 */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + linux,mtd-name = "micron,mt29c4g96maz"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0 0x80000>; /* 512KiB */ + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1C0000>; /* 1792KiB */ + }; + partition@1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x800000>; /* 8192KiB */ + }; + partition@780000 { + label = "Filesystem"; + reg = <0xA80000 0>; + /* HACK: MTDPART_SIZ_FULL=0 so fill to end */ + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi new file mode 100644 index 000000000000..0d0e62c00916 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Chestnut43 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-lcd43.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + led-heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + led-gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + wakeup-source; + }; + button1 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + wakeup-source; + }; + }; +}; + +#include "omap-gpmc-smsc9221.dtsi" + +&gpmc { + ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ + }; +}; + +&lis33de { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts new file mode 100644 index 000000000000..bb53c76fff6c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Chestnut43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-chestnut43-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Chestnut43"; + compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi new file mode 100644 index 000000000000..b1a800f2e940 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * DVI output for some Gumstix Overo boards (Tobi and Summit) + */ + +&omap3_pmx_core { + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &dvi0; + }; + + tfp410: encoder { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi new file mode 100644 index 000000000000..5a8cb309c71a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) + */ + +&omap3_pmx_core { + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lb035_pins: lb035-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ + >; + }; + + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ + >; + }; + + ads7846_pins: ads7846-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ + >; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ + + default-on; + }; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + lcd0: display@1 { + compatible = "lgphilips,lb035q02"; + label = "lcd35"; + + reg = <1>; /* CS1 */ + spi-max-frequency = <500000>; + spi-cpol; + spi-cpha; + + pinctrl-names = "default"; + pinctrl-0 = <&lb035_pins>; + enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio4>; + interrupts = <18 0>; /* gpio_114 */ + pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi new file mode 100644 index 000000000000..c489c06f6cc7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) + */ + +&omap3_pmx_core { + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: lte430-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ + >; + }; + + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + ads7846_pins: ads7846-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ + >; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display { + compatible = "samsung,lte430wq-f0c", "panel-dpi"; + label = "lcd43"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ + + default-on; + }; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio4>; + interrupts = <18 0>; /* gpio_114 */ + pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + wakeup-source; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi new file mode 100644 index 000000000000..00369f699e20 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) + */ + +/ { + lis33_3v3: lis33-3v3-reg { + compatible = "regulator-fixed"; + regulator-name = "lis33-3v3-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lis33_1v8: lis33-1v8-reg { + compatible = "regulator-fixed"; + regulator-name = "lis33-1v8-reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&omap3_pmx_core { + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + + /* optional 1K EEPROM with revision information */ + eeprom@51 { + compatible = "atmel,24c01"; + reg = <0x51>; + pagesize = <8>; + }; + + lis33de: lis33de@1d { + compatible = "st,lis33de", "st,lis3lv02d"; + reg = <0x1d>; + Vdd-supply = <&lis33_1v8>; + Vdd_IO-supply = <&lis33_3v3>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi new file mode 100644 index 000000000000..5f6721326f86 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Gallop43 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-lcd43.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + led-heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + led-gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + wakeup-source; + }; + button1 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + wakeup-source; + }; + }; +}; + +&usbhshost { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts new file mode 100644 index 000000000000..d882a58028c1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Gallop43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-gallop43-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Gallop43"; + compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi new file mode 100644 index 000000000000..4b66f622ac13 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Ash Charles, Gumstix Inc. + */ + +/* + * Palo35 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-lcd35.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + led-heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + led-gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + wakeup-source; + }; + button1 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts new file mode 100644 index 000000000000..39c8e9ce5776 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Ash Charles, Gumstix Inc. + */ + +/* + * Palo35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-palo35-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Palo35"; + compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi new file mode 100644 index 000000000000..a8f163a899f0 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Palo43 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-lcd43.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + led-heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + led-gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + wakeup-source; + }; + button1 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + wakeup-source; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts new file mode 100644 index 000000000000..2c0f755ec8cc --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Palo43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-palo43-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Palo43"; + compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts new file mode 100644 index 000000000000..3eb935df04dc --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Alto35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-alto35-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; + compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts new file mode 100644 index 000000000000..25e82efe4f3b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Chestnut43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-chestnut43-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; + compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts new file mode 100644 index 000000000000..0c93ea3f9774 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Gallop43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-gallop43-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; + compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts new file mode 100644 index 000000000000..9468ef9f9742 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + */ + +/* + * Palo35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-palo35-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; + compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts new file mode 100644 index 000000000000..9feead584479 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Palo43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-palo43-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; + compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts new file mode 100644 index 000000000000..92f56b9d009d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Summit expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-summit-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; + compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts new file mode 100644 index 000000000000..6d14466c180a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + */ + +/* + * Tobi expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-tobi-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; + compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts new file mode 100644 index 000000000000..bcf20ff3f281 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + */ + +/* + * TobiDuo expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-tobiduo-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; + compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi new file mode 100644 index 000000000000..da583b47ed8d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +#include "omap36xx.dtsi" +#include "omap3-overo-base.dtsi" + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + w3cbw003c_2_pins: w3cbw003c-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi new file mode 100644 index 000000000000..ec03ca17e98b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Summit expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-dvi.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + led-heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&lis33de { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts new file mode 100644 index 000000000000..da5ca80430ae --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +/* + * Summit expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-summit-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Summit"; + compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: led-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + >; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi new file mode 100644 index 000000000000..5432e4e16ab5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + */ + +/* + * Tobi expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-dvi.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + led-heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +#include "omap-gpmc-smsc9221.dtsi" + +&gpmc { + ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ + }; +}; + +&lis33de { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts new file mode 100644 index 000000000000..ce3f2404f329 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + */ + +/* + * Tobi expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-tobi-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Tobi"; + compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi new file mode 100644 index 000000000000..218a10c0d815 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + */ + +/* + * TobiDuo expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +#include "omap-gpmc-smsc9221.dtsi" + +&gpmc { + smsc1: ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ + }; + + smsc2: ethernet@4,0 { + compatible = "smsc,lan9221","smsc,lan9115"; + bank-width = <2>; + + gpmc,mux-add-data = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <42>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <42>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <36>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <54>; + gpmc,access-ns = <36>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wr-data-mux-bus-ns = <18>; + gpmc,wr-access-ns = <42>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + + reg = <4 0 0xff>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* GPIO 65 */ + }; +}; + +&lis33de { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts new file mode 100644 index 000000000000..fc6163eae45e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + */ + +/* + * TobiDuo expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-tobiduo-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on TobiDuo"; + compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo.dtsi new file mode 100644 index 000000000000..7dc044e87226 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-overo.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +#include "omap34xx.dtsi" +#include "omap3-overo-base.dtsi" + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + w3cbw003c_2_pins: w3cbw003c-2-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts new file mode 100644 index 000000000000..8d8c9085e6ff --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 + * Nikolaus Schaller + */ + +/* + * device tree for OpenPandora 1GHz with DM3730 + */ + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-pandora-common.dtsi" + +/ { + model = "Pandora Handheld Console 1GHz"; + + compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap3"; +}; + +&omap3_pmx_core2 { + + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + &control_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; + + control_pins: control-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ + OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ + OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ + OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ + OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ + + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts new file mode 100644 index 000000000000..2d5eac3ffc6c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 + * Nikolaus Schaller + */ + +/* + * device tree for OpenPandora with OMAP3530 + */ + +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap3-pandora-common.dtsi" + +/ { + model = "Pandora Handheld Console"; + + compatible = "openpandora,omap3-pandora-600mhz", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + &control_pins + >; + + hsusb2_2_pins: hsusb2-2-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + >; + }; + + control_pins: control-pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi new file mode 100644 index 000000000000..e91000f5f304 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi @@ -0,0 +1,730 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 + * Nikolaus Schaller + * + * Common device tree include for OpenPandora devices. + */ + +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &lcd; + }; + + /* fixed 26MHz oscillator */ + hfclk_26m: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + tv: connector { + compatible = "connector-analog-tv"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + gpio-leds { + + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + label = "pandora::sd1"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "pandora::sd2"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led3 { + label = "pandora::bluetooth"; + gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led4 { + label = "pandora::wifi"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ + linux,default-trigger = "mmc2"; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + up-button { + label = "up"; + linux,code = ; + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ + wakeup-source; + }; + + down-button { + label = "down"; + linux,code = ; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ + wakeup-source; + }; + + left-button { + label = "left"; + linux,code = ; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ + wakeup-source; + }; + + right-button { + label = "right"; + linux,code = ; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ + wakeup-source; + }; + + pageup-button { + label = "game 1"; + linux,code = ; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ + wakeup-source; + }; + + pagedown-button { + label = "game 3"; + linux,code = ; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ + wakeup-source; + }; + + home-button { + label = "game 4"; + linux,code = ; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ + wakeup-source; + }; + + end-button { + label = "game 2"; + linux,code = ; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ + wakeup-source; + }; + + right-shift { + label = "l"; + linux,code = ; + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ + wakeup-source; + }; + + kp-plus { + label = "l2"; + linux,code = ; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ + wakeup-source; + }; + + right-ctrl { + label = "r"; + linux,code = ; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ + wakeup-source; + }; + + kp-minus { + label = "r2"; + linux,code = ; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ + wakeup-source; + }; + + left-ctrl { + label = "ctrl"; + linux,code = ; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ + wakeup-source; + }; + + menu { + label = "menu"; + linux,code = ; + gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ + wakeup-source; + }; + + hold { + label = "hold"; + linux,code = ; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ + wakeup-source; + }; + + left-alt { + label = "alt"; + linux,code = ; + gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ + wakeup-source; + }; + + lid { + label = "lid"; + linux,code = <0x00>; /* SW_LID lid shut */ + linux,input-type = <0x05>; /* EV_SW */ + gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ + }; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ + vcc-supply = <&vaux2>; + #phy-cells = <0>; + }; + + /* HS USB Host VBUS supply + * disabling this regulator causes current leakage, and LCD flicker + * on earlier (CC) board revisions, so keep it always on */ + usb_host_5v: fixed-regulator-usb_host_5v { + compatible = "regulator-fixed"; + regulator-name = "usb_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */ + }; + + /* wl1251 wifi+bt module */ + wlan_en: fixed-regulator-wg7210_en { + compatible = "regulator-fixed"; + regulator-name = "vwlan"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <50000>; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + /* wg7210 (wifi+bt module) 32k clock buffer */ + wg7210_32k: fixed-regulator-wg7210_32k { + compatible = "regulator-fixed"; + regulator-name = "wg7210_32k"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + enable-active-high; + gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&omap3_pmx_core { + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + led_pins: leds-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ + OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ + OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ + OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ + OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ + >; + }; + + penirq_pins: penirq-pins { + pinctrl-single,pins = < + /* here we could enable to wakeup the cpu from suspend by a pen touch */ + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ + >; + }; + +}; + +&omap3_pmx_core2 { + /* define in CPU specific file that includes this one + * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() + */ +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + clocks = <&hfclk_26m>; + clock-names = "fck"; + + twl_power: power { + compatible = "ti,twl4030-power-reset"; + ti,use_poweroff; + }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + + codec { + ti,ramp_delay_value = <3>; + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl_keypad { + keypad,num-rows = <8>; + keypad,num-columns = <6>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(0, 1, KEY_8) + MATRIX_KEY(0, 2, KEY_I) + MATRIX_KEY(0, 3, KEY_J) + MATRIX_KEY(0, 4, KEY_N) + MATRIX_KEY(0, 5, KEY_M) + MATRIX_KEY(1, 0, KEY_0) + MATRIX_KEY(1, 1, KEY_7) + MATRIX_KEY(1, 2, KEY_U) + MATRIX_KEY(1, 3, KEY_H) + MATRIX_KEY(1, 4, KEY_B) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(2, 0, KEY_BACKSPACE) + MATRIX_KEY(2, 1, KEY_6) + MATRIX_KEY(2, 2, KEY_Y) + MATRIX_KEY(2, 3, KEY_G) + MATRIX_KEY(2, 4, KEY_V) + MATRIX_KEY(2, 5, KEY_FN) + MATRIX_KEY(3, 0, KEY_O) + MATRIX_KEY(3, 1, KEY_5) + MATRIX_KEY(3, 2, KEY_T) + MATRIX_KEY(3, 3, KEY_F) + MATRIX_KEY(3, 4, KEY_C) + MATRIX_KEY(4, 0, KEY_P) + MATRIX_KEY(4, 1, KEY_4) + MATRIX_KEY(4, 2, KEY_R) + MATRIX_KEY(4, 3, KEY_D) + MATRIX_KEY(4, 4, KEY_X) + MATRIX_KEY(5, 0, KEY_K) + MATRIX_KEY(5, 1, KEY_3) + MATRIX_KEY(5, 2, KEY_E) + MATRIX_KEY(5, 3, KEY_S) + MATRIX_KEY(5, 4, KEY_Z) + MATRIX_KEY(6, 0, KEY_L) + MATRIX_KEY(6, 1, KEY_2) + MATRIX_KEY(6, 2, KEY_W) + MATRIX_KEY(6, 3, KEY_A) + MATRIX_KEY(6, 4, KEY_RIGHTBRACE) + MATRIX_KEY(7, 0, KEY_ENTER) + MATRIX_KEY(7, 1, KEY_1) + MATRIX_KEY(7, 2, KEY_Q) + MATRIX_KEY(7, 3, KEY_LEFTSHIFT) + MATRIX_KEY(7, 4, KEY_LEFTBRACE ) + >; +}; + +/* backup battery charger */ +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +/* MMC2 */ +&vmmc2 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; +}; + +/* LCD */ +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +/* USB Host PHY */ +&vaux2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +/* available on expansion connector */ +&vaux3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* ADS7846 and nubs */ +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +/* power audio DAC and LID sensor */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +&i2c2 { + clock-frequency = <100000>; + /* no clients so we should disable clock */ +}; + +&i2c3 { + clock-frequency = <100000>; + + bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; + +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +/* + * Many pandora boards have been produced with defective write-protect switches + * on either slot, so it was decided not to use this feature. If you know + * your board has good switches, feel free to uncomment wp-gpios below. + */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmc2>; + bus-width = <4>; + cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; + /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ +}; + +&mmc3 { + vmmc-supply = <&wlan_en>; + + bus-width = <4>; + non-removable; + ti,non-removable; + cap-power-off-card; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + + #address-cells = <1>; + #size-cells = <0>; + + wlan: wifi@1 { + compatible = "ti,wl1251"; + + reg = <1>; + + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */ + + ti,wl1251-has-eeprom; + }; +}; + +/* bluetooth*/ +&uart1 { +}; + +/* spare (expansion connector) */ +&uart2 { +}; + +/* console (expansion connector) */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "sw"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ + + x-loader@0 { + label = "xloader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "uboot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "uboot-env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "boot"; + reg = <0x280000 0xa00000>; + }; + + filesystem@c80000 { + label = "rootfs"; + reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + }; +}; + +&mcspi1 { + tsc2046@0 { + reg = <0>; /* CS0 */ + compatible = "ti,tsc2046"; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&penirq_pins>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */ + pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + vcc-supply = <&vaux4>; + + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <8000>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4800>; + ti,x-plate-ohms = /bits/ 16 <40>; + ti,pressure-max = /bits/ 16 <255>; + + wakeup-source; + }; + + lcd: lcd@1 { + reg = <1>; /* CS1 */ + compatible = "tpo,td043mtea1"; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ + vcc-supply = <&vaux1>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + +}; + +/* n/a - used as GPIOs */ +&mcbsp1 { +}; + +/* audio DAC */ +&mcbsp2 { +}; + +/* bluetooth */ +&mcbsp3 { +}; + +/* to twl4030*/ +&mcbsp4 { +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "okay"; + vdds_dsi-supply = <&vpll2>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi new file mode 100644 index 000000000000..2dbb687d4df2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common file for omap dpi panels with QVGA and reset pins + * + * Note that the board specifc DTS file needs to specify + * at minimum the GPIO enable-gpios for display, and + * gpios for gpio-backlight. + */ + +/ { + aliases { + display0 = &lcd0; + }; + + backlight0: backlight { + compatible = "gpio-backlight"; + default-on; + }; + + /* 3.3V GPIO controlled regulator for LCD_ENVDD */ + lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + + lcd0: display { + compatible = "sharp,ls037v7dw01"; + label = "lcd"; + power-supply = <&lcd_3v3>; + envdd-supply = <&lcd_3v3>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <18>; + }; + }; +}; + +&mcspi1 { + tsc2046@0 { + reg = <0>; /* CS0 */ + compatible = "ti,tsc2046"; + spi-max-frequency = <1000000>; + vcc-supply = <&lcd_3v3>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <8000>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4800>; + ti,x-plate-ohms = /bits/ 16 <40>; + ti,pressure-max = /bits/ 16 <255>; + ti,swap-xy; + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi new file mode 100644 index 000000000000..6730c749d5ea --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 + */ + +/ { + tfp410: encoder { + compatible = "ti,tfp410"; + + powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + + pinctrl-names = "default"; + pinctrl-0 = <&tfp410_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: dvi-connector { + compatible = "dvi-connector"; + label = "dvi"; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + audio_amp: audio_amp { + compatible = "regulator-fixed"; + regulator-name = "audio_amp"; + pinctrl-names = "default"; + pinctrl-0 = <&sb_t35_audio_amp>; + gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ + regulator-always-on; + }; +}; + +&omap3_pmx_core { + smsc2_pins: smsc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ + OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ + >; + }; + + tfp410_pins: tfp410-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + sb_t35_audio_amp: sb-t35-audio-amp-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ + >; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +&gpmc { + ranges = <4 0 0x2d000000 0x01000000>; + + smsc2: ethernet@4,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + pinctrl-names = "default"; + pinctrl-0 = <&smsc2_pins>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + reg = <4 0 0xff>; + bank-width = <2>; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <150>; + gpmc,cs-wr-off-ns = <150>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <140>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <140>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <120>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <75>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts new file mode 100644 index 000000000000..07bec48dc441 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Suppport for CompuLab SBC-T3517 with CM-T3517 + */ + +#include "omap3-cm-t3517.dts" +#include "omap3-sb-t35.dtsi" + +/ { + model = "CompuLab SBC-T3517 with CM-T3517"; + compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; + + /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ + vddvario: regulator-vddvario-sb-t35 { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a-sb-t35 { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &sb_t35_usb_hub_pins + &usb_hub_pins + >; + + mmc1_aux_pins: mmc1-aux-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ + >; + }; + + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc1_pins + &mmc1_aux_pins + >; + + wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ + cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ +}; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&gpmc { + ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ + <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts new file mode 100644 index 000000000000..1beefc319422 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Suppport for CompuLab SBC-T3530 with CM-T3530 + */ + +#include "omap3-cm-t3530.dts" +#include "omap3-sb-t35.dtsi" + +/ { + model = "CompuLab SBC-T3530 with CM-T3530"; + compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&sb_t35_usb_hub_pins>; + + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ + >; + }; +}; + +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ + <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ + <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +}; + +&mmc1 { + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; +}; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts new file mode 100644 index 000000000000..aefc1187ebc9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Suppport for CompuLab SBC-T3730 with CM-T3730 + */ + +#include "omap3-cm-t3730.dts" +#include "omap3-sb-t35.dtsi" + +/ { + model = "CompuLab SBC-T3730 with CM-T3730"; + compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3"; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&sb_t35_usb_hub_pins>; + + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ + >; + }; +}; + +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ + <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ + <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ +}; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap3-sniper.dts b/arch/arm/boot/dts/ti/omap/omap3-sniper.dts new file mode 100644 index 000000000000..79e004057482 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-sniper.dts @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015-2016 Paul Kocialkowski + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include + +/ { + model = "LG Optimus Black"; + compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ + >; + }; + + dp3t_sel_pins: dp3t-sel-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + + lp8720_en_pin: lp8720-en-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ + >; + }; + + usb_otg_hs_pins: usb-otg-hs-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ + >; + }; +}; + +&omap3_pmx_wkup { + pinctrl-names = "default"; + + mmc1_cd_pin: mmc1-cd-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ + >; + }; +}; + +&gpio2 { + ti,no-reset-on-init; +}; + +&gpio5 { + ti,no-reset-on-init; +}; + +&gpio6 { + ti,no-reset-on-init; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &dp3t_sel_pins>; + + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + power { + compatible = "ti,twl4030-power"; + ti,use_poweroff; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; + + lp8720@7d { + pinctrl-names = "default"; + pinctrl-0 = <&lp8720_en_pin>; + + compatible = "ti,lp8720"; + reg = <0x7d>; + + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */ + + lp8720_ldo1: ldo1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>; + + vmmc-supply = <&lp8720_ldo1>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */ + bus-width = <4>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + vmmc-supply = <&vmmc2>; + ti,non-removable; + bus-width = <8>; +}; + +&mmc3 { + status = "disabled"; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_hs_pins>; + + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl_keypad { + linux,keymap = < + MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP) + MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN) + MATRIX_KEY(0x02, 0x00, KEY_SELECT) + >; +}; + +/* + * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3. + * When not powered, these sensors cause the I2C3 clock to stay low at all times, + * making it impossible to reach other devices on I2C3. + */ + +&vaux2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +&vdac { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi b/arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi new file mode 100644 index 000000000000..92a5846048bd --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/* Secure omaps have some devices inaccessible depending on the firmware */ +&aes1_target { + status = "disabled"; +}; + +&aes2_target { + status = "disabled"; +}; + +&sham { + status = "disabled"; +}; + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + /* McBSP2 is used for onboard sound, same as on beagle */ + ti,mcbsp = <&mcbsp2>; + }; + + /* Regulator to enable/switch the vcc of the Wifi module */ + mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { + compatible = "regulator-fixed"; + regulator-name = "regulator-mmc2-sdio-poweron"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ + startup-delay-us = <10000>; + }; +}; + +&omap3_pmx_core { + hsusbb2_pins: hsusbb2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + /* wlan GPIO output for WLAN_EN */ + wlan_gpio: wlan-gpio-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + mcspi3_pins: mcspi3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ + >; + }; + + mcbsp3_pins: mcbsp3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ + >; + }; +}; + +/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ +&mcbsp1 { + status = "disabled"; +}; + +&mcbsp2 { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + +&mcspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi3_pins>; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + bus-width = <8>; +}; + +// WiFi (Marvell 88W8686) on MMC2/SDIO +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&mmc2_sdio_poweron>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; + +&mmc3 { + status = "disabled"; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&mcbsp3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <16>; + gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ + ti,nand-ecc-opt = "sw"; + + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&vaux2 { + regulator-name = "vdd_ehci"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-thunder.dts b/arch/arm/boot/dts/ti/omap/omap3-thunder.dts new file mode 100644 index 000000000000..c87956c59b08 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-thunder.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + */ + +#include "omap3-tao3530.dtsi" + +/ { + model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; + compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: lte430-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ + >; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display { + compatible = "samsung,lte430wq-f0c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <2>; + vfront-porch = <3>; + vsync-len = <11>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ + + default-on; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3-zoom3.dts b/arch/arm/boot/dts/ti/omap/omap3-zoom3.dts new file mode 100644 index 000000000000..9f1e125fd77b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3-zoom3.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap-zoom-common.dtsi" + +/ { + model = "TI Zoom3"; + compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; + + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&omap3_pmx_core { + /* REVISIT: twl gpio0 is mmc0_cd */ + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ + OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ + OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + /* wl12xx GPIO output for WLAN_EN */ + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ + >; + }; +}; + +&omap3_pmx_core2 { + mmc3_2_pins: mmc3-2-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + >; + }; +}; + +&omap3_pmx_wkup { + wlan_host_wkup: wlan-host-wkup-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&twl_gpio { + ti,use-leds; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; +/* +&mmc2 { + vmmc-supply = <&vmmc2>; + ti,non-removable; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; +*/ +&mmc3 { + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ + ref-clock-frequency = <26000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + status = "disabled"; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi new file mode 100644 index 000000000000..92cd4c99dae7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3.dtsi @@ -0,0 +1,1039 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +/ { + compatible = "ti,omap3430", "ti,omap3"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0x0>; + + clocks = <&dpll1_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + }; + + pmu@54000000 { + compatible = "arm,cortex-a8-pmu"; + reg = <0x54000000 0x800000>; + interrupts = <3>; + ti,hwmods = "debugss"; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + + iva: iva { + compatible = "ti,iva2.2"; + ti,hwmods = "iva"; + + dsp { + compatible = "ti,omap3-c64"; + }; + }; + }; + + /* + * XXX: Use a flat representation of the OMAP3 interconnect. + * The real OMAP interconnect network is quite complex. + * Since it will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp@68000000 { + compatible = "ti,omap3-l3-smx", "simple-bus"; + reg = <0x68000000 0x10000>; + interrupts = <9 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + l4_core: l4@48000000 { + compatible = "ti,omap3-l4-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x1000000>; + + scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x238>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon", "simple-bus"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x270 0x330>; + + pbias_regulator: pbias_regulator@2b0 { + compatible = "ti,pbias-omap3", "ti,pbias-omap"; + reg = <0x2b0 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + + omap3_pmx_wkup: pinmux@a00 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0xa00 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + }; + }; + + aes1_target: target-module@480a6000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480a6044 0x4>, + <0x480a6048 0x4>, + <0x480a604c 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&aes1_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480a6000 0x2000>; + + aes1: aes1@0 { + compatible = "ti,omap3-aes"; + reg = <0 0x50>; + interrupts = <0>; + dmas = <&sdma 9 &sdma 10>; + dma-names = "tx", "rx"; + }; + }; + + aes2_target: target-module@480c5000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480c5044 0x4>, + <0x480c5048 0x4>, + <0x480c504c 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&aes2_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c5000 0x2000>; + + aes2: aes2@0 { + compatible = "ti,omap3-aes"; + reg = <0 0x50>; + interrupts = <0>; + dmas = <&sdma 65 &sdma 66>; + dma-names = "tx", "rx"; + }; + }; + + prm: prm@48306000 { + compatible = "ti,omap3-prm"; + reg = <0x48306000 0x4000>; + interrupts = <11>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + cm: cm@48004000 { + compatible = "ti,omap3-cm"; + reg = <0x48004000 0x4000>; + + cm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_clockdomains: clockdomains { + }; + }; + + target-module@48320000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x48320000 0x4>, + <0x48320004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48320000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap3-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + target-module@48056000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x48056000 0x4>, + <0x4805602c 0x4>, + <0x48056028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ + clocks = <&core_l3_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48056000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap3430-sdma", "ti,omap-sdma"; + reg = <0x0 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <96>; + }; + }; + + gpio1: gpio@48310000 { + compatible = "ti,omap3-gpio"; + reg = <0x48310000 0x200>; + interrupts = <29>; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@49050000 { + compatible = "ti,omap3-gpio"; + reg = <0x49050000 0x200>; + interrupts = <30>; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@49052000 { + compatible = "ti,omap3-gpio"; + reg = <0x49052000 0x200>; + interrupts = <31>; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@49054000 { + compatible = "ti,omap3-gpio"; + reg = <0x49054000 0x200>; + interrupts = <32>; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@49056000 { + compatible = "ti,omap3-gpio"; + reg = <0x49056000 0x200>; + interrupts = <33>; + ti,hwmods = "gpio5"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@49058000 { + compatible = "ti,omap3-gpio"; + reg = <0x49058000 0x200>; + interrupts = <34>; + ti,hwmods = "gpio6"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap3-uart"; + reg = <0x4806a000 0x2000>; + interrupts-extended = <&intc 72>; + dmas = <&sdma 49 &sdma 50>; + dma-names = "tx", "rx"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap3-uart"; + reg = <0x4806c000 0x400>; + interrupts-extended = <&intc 73>; + dmas = <&sdma 51 &sdma 52>; + dma-names = "tx", "rx"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@49020000 { + compatible = "ti,omap3-uart"; + reg = <0x49020000 0x400>; + interrupts-extended = <&intc 74>; + dmas = <&sdma 53 &sdma 54>; + dma-names = "tx", "rx"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap3-i2c"; + reg = <0x48070000 0x80>; + interrupts = <56>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap3-i2c"; + reg = <0x48072000 0x80>; + interrupts = <57>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap3-i2c"; + reg = <0x48060000 0x80>; + interrupts = <61>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + mailbox: mailbox@48094000 { + compatible = "ti,omap3-mailbox"; + ti,hwmods = "mailbox"; + reg = <0x48094000 0x200>; + interrupts = <26>; + #mbox-cells = <1>; + ti,mbox-num-users = <2>; + ti,mbox-num-fifos = <2>; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + }; + + mcspi1: spi@48098000 { + compatible = "ti,omap2-mcspi"; + reg = <0x48098000 0x100>; + interrupts = <65>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi1"; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mcspi2: spi@4809a000 { + compatible = "ti,omap2-mcspi"; + reg = <0x4809a000 0x100>; + interrupts = <66>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi2"; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + mcspi3: spi@480b8000 { + compatible = "ti,omap2-mcspi"; + reg = <0x480b8000 0x100>; + interrupts = <91>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi3"; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, + <&sdma 16>, + <&sdma 23>, + <&sdma 24>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + mcspi4: spi@480ba000 { + compatible = "ti,omap2-mcspi"; + reg = <0x480ba000 0x100>; + interrupts = <48>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi4"; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; + + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <58>; + ti,hwmods = "hdq1w"; + }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap3-hsmmc"; + reg = <0x4809c000 0x200>; + interrupts = <83>; + ti,hwmods = "mmc1"; + ti,dual-volt; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap3-hsmmc"; + reg = <0x480b4000 0x200>; + interrupts = <86>; + ti,hwmods = "mmc2"; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + + mmc3: mmc@480ad000 { + compatible = "ti,omap3-hsmmc"; + reg = <0x480ad000 0x200>; + interrupts = <94>; + ti,hwmods = "mmc3"; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; + + mmu_isp: mmu@480bd400 { + #iommu-cells = <0>; + compatible = "ti,omap2-iommu"; + reg = <0x480bd400 0x80>; + interrupts = <24>; + ti,hwmods = "mmu_isp"; + ti,#tlb-entries = <8>; + }; + + mmu_iva: mmu@5d000000 { + #iommu-cells = <0>; + compatible = "ti,omap2-iommu"; + reg = <0x5d000000 0x80>; + interrupts = <28>; + ti,hwmods = "mmu_iva"; + status = "disabled"; + }; + + wdt2: wdt@48314000 { + compatible = "ti,omap3-wdt"; + reg = <0x48314000 0x80>; + ti,hwmods = "wd_timer2"; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + clocks = <&mcbsp1_fck>; + clock-names = "fck"; + status = "disabled"; + }; + + /* Likely needs to be tagged disabled on HS devices */ + rng_target: target-module@480a0000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480a003c 0x4>, + <0x480a0040 0x4>, + <0x480a0044 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&rng_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480a0000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap2-rng"; + reg = <0x0 0x2000>; + interrupts = <52>; + }; + }; + + mcbsp2: mcbsp@49022000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49022000 0xff>, + <0x49028000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <17>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>, /* RX interrupt */ + <4>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + ti,buffer-size = <1280>; + ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; + clock-names = "fck", "ick"; + status = "disabled"; + }; + + mcbsp3: mcbsp@49024000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49024000 0xff>, + <0x4902a000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <22>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>, /* RX interrupt */ + <5>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; + clock-names = "fck", "ick"; + status = "disabled"; + }; + + mcbsp4: mcbsp@49026000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49026000 0xff>; + reg-names = "mpu"; + interrupts = <23>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + clocks = <&mcbsp4_fck>; + clock-names = "fck"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <27>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + dmas = <&sdma 21>, + <&sdma 22>; + dma-names = "tx", "rx"; + clocks = <&mcbsp5_fck>; + clock-names = "fck"; + status = "disabled"; + }; + + sham: sham@480c3000 { + compatible = "ti,omap3-sham"; + ti,hwmods = "sham"; + reg = <0x480c3000 0x64>; + interrupts = <49>; + dmas = <&sdma 69>; + dma-names = "rx"; + }; + + timer1_target: target-module@48318000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48318000 0x4>, + <0x48318010 0x4>, + <0x48318014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48318000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&gpt1_fck>; + clock-names = "fck"; + interrupts = <37>; + ti,timer-alwon; + }; + }; + + timer2_target: target-module@49032000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49032000 0x4>, + <0x49032010 0x4>, + <0x49032014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49032000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; + }; + + timer3: timer@49034000 { + compatible = "ti,omap3430-timer"; + reg = <0x49034000 0x400>; + interrupts = <39>; + ti,hwmods = "timer3"; + }; + + timer4: timer@49036000 { + compatible = "ti,omap3430-timer"; + reg = <0x49036000 0x400>; + interrupts = <40>; + ti,hwmods = "timer4"; + }; + + timer5: timer@49038000 { + compatible = "ti,omap3430-timer"; + reg = <0x49038000 0x400>; + interrupts = <41>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4903a000 { + compatible = "ti,omap3430-timer"; + reg = <0x4903a000 0x400>; + interrupts = <42>; + ti,hwmods = "timer6"; + ti,timer-dsp; + }; + + timer7: timer@4903c000 { + compatible = "ti,omap3430-timer"; + reg = <0x4903c000 0x400>; + interrupts = <43>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@4903e000 { + compatible = "ti,omap3430-timer"; + reg = <0x4903e000 0x400>; + interrupts = <44>; + ti,hwmods = "timer8"; + ti,timer-pwm; + ti,timer-dsp; + }; + + timer9: timer@49040000 { + compatible = "ti,omap3430-timer"; + reg = <0x49040000 0x400>; + interrupts = <45>; + ti,hwmods = "timer9"; + ti,timer-pwm; + }; + + timer10: timer@48086000 { + compatible = "ti,omap3430-timer"; + reg = <0x48086000 0x400>; + interrupts = <46>; + ti,hwmods = "timer10"; + ti,timer-pwm; + }; + + timer11: timer@48088000 { + compatible = "ti,omap3430-timer"; + reg = <0x48088000 0x400>; + interrupts = <47>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; + + timer12_target: target-module@48304000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48304000 0x4>, + <0x48304010 0x4>, + <0x48304014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt12_fck>, <&gpt12_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48304000 0x1000>; + + timer12: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <95>; + ti,timer-alwon; + ti,timer-secure; + }; + }; + + usbhstll: usbhstll@48062000 { + compatible = "ti,usbhs-tll"; + reg = <0x48062000 0x1000>; + interrupts = <78>; + ti,hwmods = "usb_tll_hs"; + }; + + usbhshost: usbhshost@48064000 { + compatible = "ti,usbhs-host"; + reg = <0x48064000 0x400>; + ti,hwmods = "usb_host_hs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbhsohci: ohci@48064400 { + compatible = "ti,ohci-omap3"; + reg = <0x48064400 0x400>; + interrupts = <76>; + remote-wakeup-connected; + }; + + usbhsehci: ehci@48064800 { + compatible = "ti,ehci-omap"; + reg = <0x48064800 0x400>; + interrupts = <77>; + }; + }; + + gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x02d0>; + interrupts = <20>; + dmas = <&sdma 4>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + usb_otg_target: target-module@480ab000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480ab400 0x4>, + <0x480ab404 0x4>, + <0x480ab408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Clock defined in the SoC specific dtsi file */ + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x480ab000 0x1000>; + + usb_otg_hs: usb@0 { + compatible = "ti,omap3-musb"; + reg = <0 0x1000>; + interrupts = <92>, <93>; + interrupt-names = "mc", "dma"; + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + }; + }; + + dss: dss@48050000 { + compatible = "ti,omap3-dss"; + reg = <0x48050000 0x200>; + status = "disabled"; + ti,hwmods = "dss_core"; + clocks = <&dss1_alwon_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@48050400 { + compatible = "ti,omap3-dispc"; + reg = <0x48050400 0x400>; + interrupts = <25>; + ti,hwmods = "dss_dispc"; + clocks = <&dss1_alwon_fck>; + clock-names = "fck"; + }; + + dsi: encoder@4804fc00 { + compatible = "ti,omap3-dsi"; + reg = <0x4804fc00 0x200>, + <0x4804fe00 0x40>, + <0x4804ff00 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = <25>; + status = "disabled"; + ti,hwmods = "dss_dsi1"; + clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; + clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + rfbi: encoder@48050800 { + compatible = "ti,omap3-rfbi"; + reg = <0x48050800 0x100>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + clocks = <&dss1_alwon_fck>, <&dss_ick>; + clock-names = "fck", "ick"; + }; + + venc: encoder@48050c00 { + compatible = "ti,omap3-venc"; + reg = <0x48050c00 0x100>; + status = "disabled"; + ti,hwmods = "dss_venc"; + clocks = <&dss_tv_fck>; + clock-names = "fck"; + }; + }; + + ssi: ssi-controller@48058000 { + compatible = "ti,omap3-ssi"; + ti,hwmods = "ssi"; + + status = "disabled"; + + reg = <0x48058000 0x1000>, + <0x48059000 0x1000>; + reg-names = "sys", + "gdd"; + + interrupts = <71>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ssi_port1: ssi-port@4805a000 { + compatible = "ti,omap3-ssi-port"; + + reg = <0x4805a000 0x800>, + <0x4805a800 0x800>; + reg-names = "tx", + "rx"; + + interrupts = <67>, + <68>; + }; + + ssi_port2: ssi-port@4805b000 { + compatible = "ti,omap3-ssi-port"; + + reg = <0x4805b000 0x800>, + <0x4805b800 0x800>; + reg-names = "tx", + "rx"; + + interrupts = <69>, + <70>; + }; + }; + }; +}; + +#include "omap3xxx-clocks.dtsi" + +/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&omap_32k_fck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap3430-sdp.dts new file mode 100644 index 000000000000..258ecd9e4519 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3430-sdp.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "TI OMAP3430 SDP"; + compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + /* + * S6-3 must be in ON position for 8 bit mode to function + * Else, use 4 bit mode + */ + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&gpmc { + ranges = <0 0 0x10000000 0x08000000>, + <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ + <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ + + nor@0,0 { + compatible = "cfi-flash"; + linux,mtd-name = "intel,pf48f6000m0y1be"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x08000000>; + bank-width = <2>; + + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + partition@0 { + label = "bootloader-nor"; + reg = <0 0x40000>; + }; + partition@40000 { + label = "params-nor"; + reg = <0x40000 0x40000>; + }; + partition@80000 { + label = "kernel-nor"; + reg = <0x80000 0x200000>; + }; + partition@280000 { + label = "filesystem-nor"; + reg = <0x240000 0x7d80000>; + }; + }; + + nand@1,0 { + compatible = "ti,omap2-nand"; + reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f1g08abb"; + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "sw"; + nand-bus-width = <8>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + partition@0 { + label = "xloader-nand"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "bootloader-nand"; + reg = <0x80000 0x140000>; + }; + partition@1c0000 { + label = "params-nand"; + reg = <0x1c0000 0xc0000>; + }; + partition@280000 { + label = "kernel-nand"; + reg = <0x280000 0x500000>; + }; + partition@780000 { + label = "filesystem-nand"; + reg = <0x780000 0x7880000>; + }; + }; + + onenand@2,0 { + linux,mtd-name = "samsung,kfm2g16q2m-deb8"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,omap2-onenand"; + reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ + + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <84>; + gpmc,cs-wr-off-ns = <72>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <18>; + gpmc,oe-on-ns = <30>; + gpmc,oe-off-ns = <84>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <42>; + gpmc,rd-cycle-ns = <108>; + gpmc,wr-cycle-ns = <96>; + gpmc,access-ns = <78>; + gpmc,wr-data-mux-bus-ns = <30>; + + partition@0 { + label = "xloader-onenand"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "bootloader-onenand"; + reg = <0x80000 0x40000>; + }; + partition@c0000 { + label = "params-onenand"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { + label = "kernel-onenand"; + reg = <0xe0000 0x200000>; + }; + partition@2e0000 { + label = "filesystem-onenand"; + reg = <0x2e0000 0xfd20000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi new file mode 100644 index 000000000000..24adfac26be0 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP3430 ES1 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm_clocks { + gfx_l3_ck: gfx_l3_ck@b10 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&l3_ick>; + reg = <0x0b10>; + ti,bit-shift = <0>; + }; + + gfx_l3_fck: gfx_l3_fck@b40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l3_ick>; + ti,max-div = <7>; + reg = <0x0b40>; + ti,index-starts-at-one; + }; + + gfx_l3_ick: gfx_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&gfx_l3_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gfx_cg1_ck: gfx_cg1_ck@b00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&gfx_l3_fck>; + reg = <0x0b00>; + ti,bit-shift = <1>; + }; + + gfx_cg2_ck: gfx_cg2_ck@b00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&gfx_l3_fck>; + reg = <0x0b00>; + ti,bit-shift = <2>; + }; + + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + d2d_26m_fck: clock-d2d-26m-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "d2d_26m_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + fshostusb_fck: clock-fshostusb-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "fshostusb_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <5>; + }; + + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; + }; + + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + usb_l4_div_ick: clock-usb-l4-div-ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "usb_l4_div_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + ti,index-starts-at-one; + }; + }; + + ssi_ssr_fck: ssi_ssr_fck_3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; + }; + + ssi_sst_fck: ssi_sst_fck_3430es1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&ssi_ssr_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es1"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + fac_ick: clock-fac-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "fac_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <8>; + }; + + ssi_ick: clock-ssi-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "ssi_ick_3430es1"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; + + usb_l4_gate_ick: clock-usb-l4-gate-ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clock-output-names = "usb_l4_gate_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + }; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + usb_l4_ick: usb_l4_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; + }; + + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es1"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + }; + + dss_ick: dss_ick_3430es1@e10 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0e10>; + ti,bit-shift = <0>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; + }; + + gfx_3430es1_clkdm: gfx_3430es1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, + <&dss1_alwon_fck>, <&dss_ick>; + }; + + d2d_clkdm: d2d_clkdm { + compatible = "ti,clockdomain"; + clocks = <&d2d_26m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi new file mode 100644 index 000000000000..8374532f20e2 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP34XX/OMAP36XX clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm_clocks { + security_l4_ick2: security_l4_ick2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + clock@a14 { + compatible = "ti,clksel"; + reg = <0xa14>; + #clock-cells = <2>; + #address-cells = <0>; + + aes1_ick: clock-aes1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + }; + + rng_ick: clock-rng-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "rng_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <2>; + }; + + sha11_ick: clock-sha11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha11_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <1>; + }; + + des1_ick: clock-des1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <0>; + }; + + pka_ick: clock-pka-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "pka_ick"; + clocks = <&security_l3_ick>; + ti,bit-shift = <4>; + }; + }; + + /* CM_FCLKEN_CAM */ + clock@f00 { + compatible = "ti,clksel"; + reg = <0xf00>; + #clock-cells = <2>; + #address-cells = <0>; + + cam_mclk: clock-cam-mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "cam_mclk"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + + csi2_96m_fck: clock-csi2-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "csi2_96m_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <1>; + }; + }; + + cam_ick: cam_ick@f10 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0f10>; + ti,bit-shift = <0>; + }; + + security_l3_ick: security_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + icr_ick: clock-icr-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "icr_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <29>; + }; + + des2_ick: clock-des2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <26>; + }; + + mspro_ick: clock-mspro-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mspro_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; + + mailboxes_ick: clock-mailboxes-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mailboxes_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <7>; + }; + + sad2d_ick: clock-sad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + sr1_fck: clock-sr1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr1_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + sr2_fck: clock-sr2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr2_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; + }; + + sr_l4_ick: sr_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll2_fck: dpll2_fck@40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <19>; + ti,max-div = <7>; + reg = <0x0040>; + ti,index-starts-at-one; + }; + + dpll2_ck: dpll2_ck@4 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll2_fck>; + reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; + ti,low-power-stop; + ti,lock; + ti,low-power-bypass; + }; + + dpll2_m2_ck: dpll2_m2_ck@44 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll2_ck>; + ti,max-div = <31>; + reg = <0x0044>; + ti,index-starts-at-one; + }; + + iva2_ck: iva2_ck@0 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&dpll2_m2_ck>; + reg = <0x0000>; + ti,bit-shift = <0>; + }; + + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + modem_fck: clock-modem-fck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "modem_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <31>; + }; + + mspro_fck: clock-mspro-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mspro_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <23>; + }; + }; + + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + mad2d_ick: clock-mad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; + }; + +}; + +&cm_clockdomains { + cam_clkdm: cam_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_ick>, <&csi2_96m_fck>; + }; + + iva2_clkdm: iva2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&iva2_ck>; + }; + + dpll2_clkdm: dpll2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll2_ck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; + }; + + d2d_clkdm: d2d_clkdm { + compatible = "ti,clockdomain"; + clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, + <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, + <&rng_ick>, <&mspro_fck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi new file mode 100644 index 000000000000..9dbf62797f0f --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP34xx/OMAP35xx SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include + +#include "omap3.dtsi" + +/ { + cpus { + cpu: cpu@0 { + /* OMAP343x/OMAP35xx variants OPP1-6 */ + operating-points-v2 = <&cpu0_opp_table>; + + clock-latency = <300000>; /* From legacy driver */ + #cooling-cells = <2>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + opp1-125000000 { + opp-hz = /bits/ 64 <125000000>; + /* + * we currently only select the max voltage from table + * Table 3-3 of the omap3530 Data sheet (SPRS507F). + * Format is: + */ + opp-microvolt = <975000 975000 975000>; + /* + * first value is silicon revision bit mask + * second one 720MHz Device Identification bit mask + */ + opp-supported-hw = <0xffffffff 3>; + }; + + opp2-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1075000 1075000 1075000>; + opp-supported-hw = <0xffffffff 3>; + opp-suspend; + }; + + opp3-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000 1200000 1200000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp4-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-microvolt = <1275000 1275000 1275000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp5-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp6-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1350000 1350000 1350000>; + /* only high-speed grade omap3530 devices */ + opp-supported-hw = <0xffffffff 2>; + turbo-mode; + }; + }; + + ocp@68000000 { + omap3_pmx_core2: pinmux@480025d8 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025d8 0x24>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x017c>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0x6c>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + bandgap: bandgap@48002524 { + reg = <0x48002524 0x4>; + compatible = "ti,omap34xx-bandgap"; + #thermal-sensor-cells = <0>; + }; + + target-module@480cb000 { + compatible = "ti,sysc-omap3430-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb024 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + clocks = <&sr2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480cb000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap3-smartreflex-core"; + reg = <0 0x400>; + interrupts = <19>; + }; + }; + + target-module@480c9000 { + compatible = "ti,sysc-omap3430-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9024 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + clocks = <&sr1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c9000 0x001000>; + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-mpu-iva"; + reg = <0 0x400>; + interrupts = <18>; + }; + }; + + /* + * On omap34xx the OCP registers do not seem to be accessible + * at all unlike on 36xx. Maybe SGX is permanently set to + * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is + * write-only at 0x50000e10. We detect SGX based on the SGX + * revision register instead of the unreadable OCP revision + * register. Also note that on early 34xx es1 revision there + * are also different clocks, but we do not have any dts users + * for it. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000014 0x4>; + reg-names = "rev"; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + }; + + thermal_zones: thermal-zones { + #include "omap3-cpu-thermal.dtsi" + }; +}; + +&ssi { + status = "okay"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + +&usb_otg_target { + clocks = <&hsotgusb_ick_3430es2>; +}; + +/include/ "omap34xx-omap36xx-clocks.dtsi" +/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi new file mode 100644 index 000000000000..dcc5cfcd1fe6 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&prm_clocks { + corex2_d3_fck: corex2_d3_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&corex2_fck>; + clock-mult = <1>; + clock-div = <3>; + }; + + corex2_d5_fck: corex2_d5_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&corex2_fck>; + clock-mult = <1>; + clock-div = <5>; + }; +}; +&cm_clocks { + dpll5_ck: dpll5_ck@d04 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; + ti,low-power-stop; + ti,lock; + }; + + dpll5_m2_ck: dpll5_m2_ck@d50 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll5_ck>; + ti,max-div = <31>; + reg = <0x0d50>; + ti,index-starts-at-one; + }; + + sgx_gate_fck: sgx_gate_fck@b00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <1>; + reg = <0x0b00>; + }; + + core_d3_ck: core_d3_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + core_d4_ck: core_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + core_d6_ck: core_d6_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <6>; + }; + + omap_192m_alwon_fck: omap_192m_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_d2_ck: core_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + sgx_mux_fck: sgx_mux_fck@b40 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; + reg = <0x0b40>; + }; + + sgx_fck: sgx_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; + }; + + sgx_ick: sgx_ick@b10 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&l3_ick>; + reg = <0x0b10>; + ti,bit-shift = <0>; + }; + + cpefuse_fck: cpefuse_fck@a08 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x0a08>; + ti,bit-shift = <0>; + }; + + ts_fck: ts_fck@a08 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_32k_fck>; + reg = <0x0a08>; + ti,bit-shift = <1>; + }; + + usbtll_fck: usbtll_fck@a08 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&dpll5_m2_ck>; + reg = <0x0a08>; + ti,bit-shift = <2>; + }; + + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + usbtll_ick: clock-usbtll-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usbtll_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <2>; + }; + }; + + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_ick: clock-mmchs3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <30>; + }; + }; + + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_fck: clock-mmchs3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <30>; + }; + }; + + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es2"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + }; + + dss_ick: dss_ick_3430es2@e10 { + #clock-cells = <0>; + compatible = "ti,omap3-dss-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0e10>; + ti,bit-shift = <0>; + }; + + usbhost_120m_fck: usbhost_120m_fck@1400 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll5_m2_ck>; + reg = <0x1400>; + ti,bit-shift = <1>; + }; + + usbhost_48m_fck: usbhost_48m_fck@1400 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clocks = <&omap_48m_fck>; + reg = <0x1400>; + ti,bit-shift = <0>; + }; + + usbhost_ick: usbhost_ick@1410 { + #clock-cells = <0>; + compatible = "ti,omap3-dss-interface-clock"; + clocks = <&l4_ick>; + reg = <0x1410>; + ti,bit-shift = <0>; + }; +}; + +&cm_clockdomains { + dpll5_clkdm: dpll5_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll5_ck>; + }; + + sgx_clkdm: sgx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sgx_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, + <&dss1_alwon_fck>, <&dss_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; + }; + + usbhost_clkdm: usbhost_clkdm { + compatible = "ti,clockdomain"; + clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, + <&usbhost_ick>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi new file mode 100644 index 000000000000..c5fdb2bd765d --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP36xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm_clocks { + dpll4_ck: dpll4_ck@d00 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-per-j-type-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; + }; + + dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m5x2_mul_ck>; + ti,bit-shift = <0x1e>; + reg = <0x0d00>; + ti,set-rate-parent; + ti,set-bit-to-disable; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll3_m3x2_mul_ck>; + ti,bit-shift = <0xc>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m3x2_mul_ck>; + ti,bit-shift = <0x1c>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m6x2_mul_ck>; + ti,bit-shift = <0x1f>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + clock@1000 { + compatible = "ti,clksel"; + reg = <0x1000>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck: clock-uart4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <18>; + }; + }; +}; + +&dpll4_m2x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m3x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m4x2_mul_ck { + ti,clock-mult = <1>; +}; + +&dpll4_m5x2_mul_ck { + ti,clock-mult = <1>; +}; + +&dpll4_m6x2_mul_ck { + clock-mult = <1>; +}; + +&cm_clockdomains { + dpll4_clkdm: dpll4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll4_ck>; + }; + + per_clkdm: per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, + <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, + <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, + <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, + <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, + <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, + <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>, <&uart4_fck>; + }; +}; + +&dpll4_m4_ck { + ti,max-div = <31>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi new file mode 100644 index 000000000000..c94eb86d3da7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP34xx/OMAP36xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm_clocks { + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; + }; + + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + }; + + ssi_ssr_fck: ssi_ssr_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; + }; + + ssi_sst_fck: ssi_sst_fck_3430es2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&ssi_ssr_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es2"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + ssi_ick: clock-ssi-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clock-output-names = "ssi_ick_3430es2"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_gate_fck: clock-usim-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "usim_gate_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + }; + }; + + sys_d2_ck: sys_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_96m_d2_fck: omap_96m_d2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_96m_d4_fck: omap_96m_d4_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <4>; + }; + + omap_96m_d8_fck: omap_96m_d8_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <8>; + }; + + omap_96m_d10_fck: omap_96m_d10_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <10>; + }; + + dpll5_m2_d4_ck: dpll5_m2_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll5_m2_d8_ck: dpll5_m2_d8_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + dpll5_m2_d16_ck: dpll5_m2_d16_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dpll5_m2_d20_ck: dpll5_m2_d20_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <20>; + }; + + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_mux_fck: clock-usim-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "usim_mux_fck"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + ti,index-starts-at-one; + }; + }; + + usim_fck: usim_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usim_gate_fck>, <&usim_mux_fck>; + }; + + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_ick: clock-usim-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usim_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <9>; + }; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>, <&usim_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, + <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&ssi_ick>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi new file mode 100644 index 000000000000..fff9c3d34193 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include + +#include "omap3.dtsi" + +/ { + aliases { + serial3 = &uart4; + }; + + cpus { + /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */ + cpu: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + + vbb-supply = <&abb_mpu_iva>; + clock-latency = <300000>; /* From omap-cpufreq driver */ + #cooling-cells = <2>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + opp50-300000000 { + opp-hz = /bits/ 64 <300000000>; + /* + * we currently only select the max voltage from table + * Table 4-19 of the DM3730 Data sheet (SPRS685B) + * Format is: cpu0-supply: + * vbb-supply: + */ + opp-microvolt = <1012500 1012500 1012500>, + <1012500 1012500 1012500>; + /* + * first value is silicon revision bit mask + * second one is "speed binned" bit mask + */ + opp-supported-hw = <0xffffffff 3>; + opp-suspend; + }; + + opp100-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1200000 1200000>, + <1200000 1200000 1200000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp130-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1325000 1325000 1325000>, + <1325000 1325000 1325000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp1g-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1375000 1375000 1375000>, + <1375000 1375000 1375000>; + /* only on am/dm37x with speed-binned bit set */ + opp-supported-hw = <0xffffffff 2>; + }; + }; + + opp_supply_mpu_iva: opp_supply { + compatible = "ti,omap-opp-supply"; + ti,absolute-max-voltage-uv = <1375000>; + }; + + ocp@68000000 { + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + abb_mpu_iva: regulator-abb-mpu { + compatible = "ti,abb-v1"; + regulator-name = "abb_mpu_iva"; + #address-cells = <0>; + #size-cells = <0>; + reg = <0x483072f0 0x8>, <0x48306818 0x4>; + reg-names = "base-address", "int-address"; + ti,tranxdone-status-mask = <0x4000000>; + clocks = <&sys_ck>; + ti,settling-time = <30>; + ti,clock-cycles = <8>; + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1012500 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1325000 0 0 0 0 0 + 1375000 1 0 0 0 0 + >; + }; + + omap3_pmx_core2: pinmux@480025a0 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025a0 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x0600>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0x2f0>; + ti,phy-type = ; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + bandgap: bandgap@48002524 { + reg = <0x48002524 0x4>; + compatible = "ti,omap36xx-bandgap"; + #thermal-sensor-cells = <0>; + }; + + target-module@480cb000 { + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + clocks = <&sr2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480cb000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap3-smartreflex-core"; + reg = <0 0x400>; + interrupts = <19>; + }; + }; + + target-module@480c9000 { + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + clocks = <&sr1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c9000 0x001000>; + + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-mpu-iva"; + reg = <0 0x400>; + interrupts = <18>; + }; + }; + + /* + * Note that the sysconfig register layout is a subset of the + * "ti,sysc-omap4" type register with just sidle and midle bits + * available while omap34xx has "ti,sysc-omap2" type sysconfig. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5000fe00 0x4>, + <0x5000fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + }; + + thermal_zones: thermal-zones { + #include "omap3-cpu-thermal.dtsi" + }; +}; + +&sdma { + compatible = "ti,omap3630-sdma", "ti,omap-sdma"; +}; + +/* OMAP3630 needs dss_96m_fck for VENC */ +&venc { + clocks = <&dss_tv_fck>, <&dss_96m_fck>; + clock-names = "fck", "tv_dac_clk"; +}; + +&ssi { + status = "okay"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + +&usb_otg_target { + clocks = <&hsotgusb_ick_3430es2>; +}; + +/include/ "omap34xx-omap36xx-clocks.dtsi" +/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi new file mode 100644 index 000000000000..2e13ca11ceea --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi @@ -0,0 +1,1790 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP3 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&prm_clocks { + virt_16_8m_ck: virt_16_8m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; + }; + + osc_sys_ck: osc_sys_ck@d40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; + reg = <0x0d40>; + }; + + sys_ck: sys_ck@1270 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&osc_sys_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x1270>; + ti,index-starts-at-one; + }; + + sys_clkout1: sys_clkout1@d70 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&osc_sys_ck>; + reg = <0x0d70>; + ti,bit-shift = <7>; + }; + + dpll3_x2_ck: dpll3_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll3_m2x2_ck: dpll3_m2x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_x2_ck: dpll4_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + corex2_fck: corex2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + wkup_l4_ick: wkup_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_ck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; + +&scm_clocks { + /* CONTROL_DEVCONF1 */ + clock@68 { + compatible = "ti,clksel"; + reg = <0x68>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp5_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + + mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp3_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + }; + + mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp4_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + }; + + mcbsp5_fck: mcbsp5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; + }; + + /* CONTROL_DEVCONF0 */ + clock@4 { + compatible = "ti,clksel"; + reg = <0x4>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp1_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + + mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp2_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + }; + }; + + mcbsp1_fck: mcbsp1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; + }; + + mcbsp2_fck: mcbsp2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; + }; + + mcbsp3_fck: mcbsp3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; + }; + + mcbsp4_fck: mcbsp4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; + }; +}; +&cm_clocks { + dummy_apb_pclk: dummy_apb_pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + omap_32k_fck: omap_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12m_ck: virt_12m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13m_ck: virt_13m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + virt_38_4m_ck: virt_38_4m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; + }; + + dpll4_ck: dpll4_ck@d00 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-per-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; + }; + + dpll4_m2_ck: dpll4_m2_ck@d48 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <63>; + reg = <0x0d48>; + ti,index-starts-at-one; + }; + + dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + omap_96m_alwon_fck: omap_96m_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll3_ck: dpll3_ck@d00 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; + }; + + /* CM_CLKSEL1_EMU */ + clock@1140 { + compatible = "ti,clksel"; + reg = <0x1140>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m3_ck: clock-dpll3-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m3_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + dpll4_m6_ck: clock-dpll4-m6 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m6_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + ti,index-starts-at-one; + }; + + emu_src_mux_ck: clock-emu-src-mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "emu_src_mux_ck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + }; + + pclk_fck: clock-pclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + + pclkx2_fck: clock-pclkx2-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclkx2_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + atclk_fck: clock-atclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "atclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: clock-traceclk-src-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "traceclk_src_fck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + }; + + traceclk_fck: clock-traceclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "traceclk_fck"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + }; + + dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll3_m3x2_mul_ck>; + ti,bit-shift = <0xc>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + emu_core_alwon_ck: emu_core_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m3x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sys_altclk: sys_altclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + mcbsp_clks: mcbsp_clks { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + core_ck: core_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll1_fck: dpll1_fck@940 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <19>; + ti,max-div = <7>; + reg = <0x0940>; + ti,index-starts-at-one; + }; + + dpll1_ck: dpll1_ck@904 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll1_fck>; + reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; + }; + + dpll1_x2_ck: dpll1_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll1_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll1_x2m2_ck: dpll1_x2m2_ck@944 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll1_x2_ck>; + ti,max-div = <31>; + reg = <0x0944>; + ti,index-starts-at-one; + }; + + cm_96m_fck: cm_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_alwon_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_CLKSEL1_PLL */ + clock@d40 { + compatible = "ti,clksel"; + reg = <0xd40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m2_ck: clock-dpll3-m2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m2_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + omap_96m_fck: clock-omap-96m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_96m_fck"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + omap_54m_fck: clock-omap-54m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_54m_fck"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + }; + + omap_48m_fck: clock-omap-48m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_48m_fck"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + }; + }; + + /* CM_CLKSEL_DSS */ + clock@e40 { + compatible = "ti,clksel"; + reg = <0xe40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll4_m3_ck: clock-dpll4-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m3_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-starts-at-one; + }; + + dpll4_m4_ck: clock-dpll4-m4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m4_ck"; + clocks = <&dpll4_ck>; + ti,max-div = <16>; + ti,index-starts-at-one; + }; + }; + + dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m3x2_mul_ck>; + ti,bit-shift = <0x1c>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + cm_96m_d2_fck: cm_96m_d2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cm_96m_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_12m_fck: omap_12m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll4_m4_ck>; + ti,clock-mult = <2>; + ti,clock-div = <1>; + ti,set-rate-parent; + }; + + dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m4x2_mul_ck>; + ti,bit-shift = <0x1d>; + reg = <0x0d00>; + ti,set-bit-to-disable; + ti,set-rate-parent; + }; + + dpll4_m5_ck: dpll4_m5_ck@f40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <63>; + reg = <0x0f40>; + ti,index-starts-at-one; + }; + + dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll4_m5_ck>; + ti,clock-mult = <2>; + ti,clock-div = <1>; + ti,set-rate-parent; + }; + + dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m5x2_mul_ck>; + ti,bit-shift = <0x1e>; + reg = <0x0d00>; + ti,set-bit-to-disable; + ti,set-rate-parent; + }; + + dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m6_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m6x2_mul_ck>; + ti,bit-shift = <0x1f>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + emu_per_alwon_ck: emu_per_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m6x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_CLKOUT_CTRL */ + clock@d70 { + compatible = "ti,clksel"; + reg = <0xd70>; + #clock-cells = <2>; + #address-cells = <0>; + + clkout2_src_gate_ck: clock-clkout2-src-gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "clkout2_src_gate_ck"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + }; + + clkout2_src_mux_ck: clock-clkout2-src-mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "clkout2_src_mux_ck"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + }; + + sys_clkout2: clock-sys-clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clkout2"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + ti,index-power-of-two; + }; + }; + + clkout2_src_ck: clkout2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; + }; + + mpu_ck: mpu_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll1_x2m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + arm_fck: arm_fck@924 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mpu_ck>; + reg = <0x0924>; + ti,max-div = <2>; + }; + + emu_mpu_alwon_ck: emu_mpu_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mpu_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_CLKSEL_CORE */ + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + l3_ick: clock-l3-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_ick"; + clocks = <&core_ck>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + l4_ick: clock-l4-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt10_mux_fck: clock-gpt10-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt10_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt11_mux_fck: clock-gpt11-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt11_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; + }; + + /* CM_CLKSEL_WKUP */ + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + rm_ick: clock-rm-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "rm_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt1_mux_fck: clock-gpt1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt1_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + }; + + /* CM_FCLKEN1_CORE */ + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt10_gate_fck: clock-gpt10-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt10_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + }; + + gpt11_gate_fck: clock-gpt11-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt11_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + }; + + mmchs2_fck: clock-mmchs2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: clock-mmchs1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <24>; + }; + + i2c3_fck: clock-i2c3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <17>; + }; + + i2c2_fck: clock-i2c2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <16>; + }; + + i2c1_fck: clock-i2c1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp5_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + }; + + mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp1_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + }; + + mcspi4_fck: clock-mcspi4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi4_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: clock-mcspi3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi3_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: clock-mcspi2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: clock-mcspi1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <18>; + }; + + uart2_fck: clock-uart2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <14>; + }; + + uart1_fck: clock-uart1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <13>; + }; + + hdq_fck: clock-hdq-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "hdq_fck"; + clocks = <&core_12m_fck>; + ti,bit-shift = <22>; + }; + }; + + gpt10_fck: gpt10_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; + }; + + gpt11_fck: gpt11_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; + }; + + core_96m_fck: core_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_48m_fck: core_48m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_12m_fck: core_12m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_12m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_l3_ick: core_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_ICLKEN1_CORE */ + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + sdrc_ick: clock-sdrc-ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sdrc_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <1>; + }; + + mmchs2_ick: clock-mmchs2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: clock-mmchs1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <24>; + }; + + hdq_ick: clock-hdq-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "hdq_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: clock-mcspi4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi4_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: clock-mcspi3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: clock-mcspi2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: clock-mcspi1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <18>; + }; + + i2c3_ick: clock-i2c3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <17>; + }; + + i2c2_ick: clock-i2c2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <16>; + }; + + i2c1_ick: clock-i2c1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <15>; + }; + + uart2_ick: clock-uart2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <14>; + }; + + uart1_ick: clock-uart1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <13>; + }; + + gpt11_ick: clock-gpt11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt11_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <12>; + }; + + gpt10_ick: clock-gpt10-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt10_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: clock-mcbsp5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp5_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: clock-mcbsp1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: clock-omapctrl-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omapctrl_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <6>; + }; + + aes2_ick: clock-aes2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + }; + + sha12_ick: clock-sha12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha12_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <27>; + }; + }; + + gpmc_fck: gpmc_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_l4_ick: core_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_FCLKEN_DSS */ + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss_tv_fck: clock-dss-tv-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_tv_fck"; + clocks = <&omap_54m_fck>; + ti,bit-shift = <2>; + }; + + dss_96m_fck: clock-dss-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_96m_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: clock-dss2-alwon-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss2_alwon_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + }; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + /* CM_FCLKEN_WKUP */ + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt1_gate_fck: clock-gpt1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt1_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + }; + + gpio1_dbck: clock-gpio1-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio1_dbck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <3>; + }; + + wdt2_fck: clock-wdt2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt2_fck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <5>; + }; + }; + + gpt1_fck: gpt1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; + }; + + wkup_32k_fck: wkup_32k_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_ICLKEN_WKUP */ + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + wdt2_ick: clock-wdt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt2_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <5>; + }; + + wdt1_ick: clock-wdt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <4>; + }; + + gpio1_ick: clock-gpio1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <3>; + }; + + omap_32ksync_ick: clock-omap-32ksync-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omap_32ksync_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <2>; + }; + + gpt12_ick: clock-gpt12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt12_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <1>; + }; + + gpt1_ick: clock-gpt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <0>; + }; + }; + + per_96m_fck: per_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_alwon_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + per_48m_fck: per_48m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_FCLKEN_PER */ + clock@1000 { + compatible = "ti,clksel"; + reg = <0x1000>; + #clock-cells = <2>; + #address-cells = <0>; + + uart3_fck: clock-uart3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart3_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: clock-gpt2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt2_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt3_gate_fck: clock-gpt3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt3_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt4_gate_fck: clock-gpt4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt4_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt5_gate_fck: clock-gpt5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt5_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt6_gate_fck: clock-gpt6-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt6_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; + + gpt7_gate_fck: clock-gpt7-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt7_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + }; + + gpt8_gate_fck: clock-gpt8-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt8_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + }; + + gpt9_gate_fck: clock-gpt9-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt9_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + }; + + gpio6_dbck: clock-gpio6-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio6_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: clock-gpio5-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio5_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: clock-gpio4-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio4_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: clock-gpio3-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio3_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: clock-gpio2-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio2_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <13>; + }; + + wdt3_fck: clock-wdt3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt3_fck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <12>; + }; + + mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp2_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + }; + + mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp3_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + }; + + mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp4_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + }; + + /* CM_CLKSEL_PER */ + clock@1040 { + compatible = "ti,clksel"; + reg = <0x1040>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt2_mux_fck: clock-gpt2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt2_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + + gpt3_mux_fck: clock-gpt3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt3_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + }; + + gpt4_mux_fck: clock-gpt4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt4_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + }; + + gpt5_mux_fck: clock-gpt5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt5_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt6_mux_fck: clock-gpt6-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt6_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt7_mux_fck: clock-gpt7-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt7_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt8_mux_fck: clock-gpt8-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt8_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt9_mux_fck: clock-gpt9-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt9_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; + }; + + gpt2_fck: gpt2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; + }; + + gpt3_fck: gpt3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; + }; + + gpt4_fck: gpt4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; + }; + + gpt5_fck: gpt5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; + }; + + gpt6_fck: gpt6_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; + }; + + gpt7_fck: gpt7_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; + }; + + gpt8_fck: gpt8_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; + }; + + gpt9_fck: gpt9_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; + }; + + per_32k_alwon_fck: per_32k_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + per_l4_ick: per_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + /* CM_ICLKEN_PER */ + clock@1010 { + compatible = "ti,clksel"; + reg = <0x1010>; + #clock-cells = <2>; + #address-cells = <0>; + + gpio6_ick: clock-gpio6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <17>; + }; + + gpio5_ick: clock-gpio5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <16>; + }; + + gpio4_ick: clock-gpio4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <15>; + }; + + gpio3_ick: clock-gpio3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <14>; + }; + + gpio2_ick: clock-gpio2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <13>; + }; + + wdt3_ick: clock-wdt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <12>; + }; + + uart3_ick: clock-uart3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <11>; + }; + + uart4_ick: clock-uart4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <18>; + }; + + gpt9_ick: clock-gpt9-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt9_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <10>; + }; + + gpt8_ick: clock-gpt8-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt8_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <9>; + }; + + gpt7_ick: clock-gpt7-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt7_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <8>; + }; + + gpt6_ick: clock-gpt6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <7>; + }; + + gpt5_ick: clock-gpt5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <6>; + }; + + gpt4_ick: clock-gpt4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <5>; + }; + + gpt3_ick: clock-gpt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <4>; + }; + + gpt2_ick: clock-gpt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <3>; + }; + + mcbsp2_ick: clock-mcbsp2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <0>; + }; + + mcbsp3_ick: clock-mcbsp3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: clock-mcbsp4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <2>; + }; + }; + + emu_src_ck: emu_src_ck { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clocks = <&emu_src_mux_ck>; + }; + + secure_32k_fck: secure_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + gpt12_fck: gpt12_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&secure_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + wdt1_fck: wdt1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&secure_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>; + }; + + dpll3_clkdm: dpll3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll3_ck>; + }; + + dpll1_clkdm: dpll1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll1_ck>; + }; + + per_clkdm: per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, + <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, + <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, + <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, + <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, + <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, + <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>; + }; + + emu_clkdm: emu_clkdm { + compatible = "ti,clockdomain"; + clocks = <&emu_src_ck>; + }; + + dpll4_clkdm: dpll4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll4_ck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi new file mode 100644 index 000000000000..801b4f10350c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP4/5 SoC CPU thermal + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + * Contact: Eduardo Valentin + */ + +#include + +cpu_thermal: cpu_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 0>; + + cpu_trips: trips { + cpu_alert0: cpu_alert { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <125000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts new file mode 100644 index 000000000000..ccf03a743678 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "motorola-mapphone-common.dtsi" + +/ { + model = "Motorola Droid Bionic XT875"; + compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4"; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + MATRIX_KEY(3, 0, KEY_VOLUMEDOWN) + >; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + backlight_led: led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + }; + }; +}; + +&i2c4 { + kxtf9: accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts b/arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts new file mode 100644 index 000000000000..e833c21f1c01 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "motorola-mapphone-common.dtsi" + +/ { + gpio_keys { + compatible = "gpio-keys"; + + volume_down { + label = "Volume Down"; + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + + /* + * We use pad 0x4a100116 abe_dmic_din3.gpio_122 as the irq instead + * of the gpio interrupt to avoid lost events in deeper idle states. + */ + slider { + label = "Keypad Slide"; + interrupts-extended = <&omap4_pmx_core 0xd6>; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + }; +}; + +/ { + model = "Motorola Droid 4 XT894"; + compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + + /* Row 1 */ + MATRIX_KEY(0, 2, KEY_1) + MATRIX_KEY(0, 6, KEY_2) + MATRIX_KEY(2, 3, KEY_3) + MATRIX_KEY(0, 7, KEY_4) + MATRIX_KEY(0, 4, KEY_5) + MATRIX_KEY(5, 5, KEY_6) + MATRIX_KEY(0, 1, KEY_7) + MATRIX_KEY(0, 5, KEY_8) + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(1, 6, KEY_0) + + /* Row 2 */ + MATRIX_KEY(3, 4, KEY_APOSTROPHE) + MATRIX_KEY(7, 6, KEY_Q) + MATRIX_KEY(7, 7, KEY_W) + MATRIX_KEY(7, 2, KEY_E) + MATRIX_KEY(1, 0, KEY_R) + MATRIX_KEY(4, 4, KEY_T) + MATRIX_KEY(1, 2, KEY_Y) + MATRIX_KEY(6, 7, KEY_U) + MATRIX_KEY(2, 2, KEY_I) + MATRIX_KEY(5, 6, KEY_O) + MATRIX_KEY(3, 7, KEY_P) + MATRIX_KEY(6, 5, KEY_BACKSPACE) + + /* Row 3 */ + MATRIX_KEY(5, 4, KEY_TAB) + MATRIX_KEY(5, 7, KEY_A) + MATRIX_KEY(2, 7, KEY_S) + MATRIX_KEY(7, 0, KEY_D) + MATRIX_KEY(2, 6, KEY_F) + MATRIX_KEY(6, 2, KEY_G) + MATRIX_KEY(6, 6, KEY_H) + MATRIX_KEY(1, 4, KEY_J) + MATRIX_KEY(3, 1, KEY_K) + MATRIX_KEY(2, 1, KEY_L) + MATRIX_KEY(4, 6, KEY_ENTER) + + /* Row 4 */ + MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ + MATRIX_KEY(6, 1, KEY_Z) + MATRIX_KEY(7, 4, KEY_X) + MATRIX_KEY(5, 1, KEY_C) + MATRIX_KEY(1, 7, KEY_V) + MATRIX_KEY(2, 4, KEY_B) + MATRIX_KEY(4, 1, KEY_N) + MATRIX_KEY(1, 1, KEY_M) + MATRIX_KEY(3, 5, KEY_COMMA) + MATRIX_KEY(5, 2, KEY_DOT) + MATRIX_KEY(6, 3, KEY_UP) + MATRIX_KEY(7, 3, KEY_OK) + + /* Row 5 */ + MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ + MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ + MATRIX_KEY(6, 0, KEY_MINUS) + MATRIX_KEY(4, 7, KEY_EQUAL) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(3, 2, KEY_SLASH) + MATRIX_KEY(4, 3, KEY_LEFT) + MATRIX_KEY(5, 3, KEY_DOWN) + MATRIX_KEY(3, 3, KEY_RIGHT) + + /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + >; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + backlight_led: led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + ti,led-mode = <0>; + label = ":kbd_backlight"; + }; + }; +}; + +&i2c4 { + lis3dh: accelerometer@18 { + compatible = "st,lis3dh-accel"; + reg = <0x18>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts b/arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts new file mode 100644 index 000000000000..6d1beb453234 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ +/dts-v1/; + +#include "omap4-duovero.dtsi" + +#include + +/ { + model = "OMAP4430 Gumstix Duovero on Parlor"; + compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; + + aliases { + display0 = &hdmi0; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "duovero:blue:led0"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button0 { + label = "button0"; + linux,code = ; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + wakeup-source; + }; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "d"; + + hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; +}; + +&omap4_pmx_core { + pinctrl-0 = < + &led_pins + &button_pins + &smsc_pins + >; + + led_pins: led-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + smsc_pins: smsc-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ + OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ + OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ + >; + }; + + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ + >; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <100000>; + + /* optional 1K EEPROM with revision information */ + eeprom@51 { + compatible = "atmel,24c01"; + reg = <0x51>; + pagesize = <8>; + }; +}; + +&mmc3 { + status = "disabled"; +}; + +#include "omap-gpmc-smsc911x.dtsi" + +&gpmc { + ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ + + ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ + + phy-mode = "mii"; + + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <50>; + gpmc,cs-wr-off-ns = <50>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <15>; + gpmc,oe-off-ns = <50>; + gpmc,we-on-ns = <15>; + gpmc,we-off-ns = <50>; + gpmc,rd-cycle-ns = <50>; + gpmc,wr-cycle-ns = <50>; + gpmc,access-ns = <50>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <35>; + gpmc,cycle2cycle-delay-ns = <35>; + gpmc,wr-data-mux-bus-ns = <35>; + gpmc,wr-access-ns = <50>; + + gpmc,mux-add-data = <2>; + gpmc,sync-read; + gpmc,sync-write; + gpmc,clk-activation-ns = <5>; + gpmc,sync-clk-ps = <20000>; + }; +}; + +&dss { + status = "okay"; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdac>; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi b/arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi new file mode 100644 index 000000000000..b8af455b411a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + */ + +#include "omap443x.dtsi" +#include "omap4-mcpdm.dtsi" + +/ { + model = "Gumstix Duovero"; + compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; + + chosen { + stdout-path = &uart3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + sound { + compatible = "ti,abe-twl6040"; + ti,model = "DuoVero"; + + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias"; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + #phy-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1phy_pins>; + + clocks = <&auxclk3_ck>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + + /* regulator for w2cbw0015 on sdio5 */ + w2cbw0015_vmmc: w2cbw0015_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&w2cbw0015_pins>; + compatible = "regulator-fixed"; + regulator-name = "w2cbw0015"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &hsusbb1_pins + >; + + twl6040_pins: twl6040-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ + OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + >; + }; + + mcbsp1_pins: mcbsp1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ + >; + }; + + hsusbb1_pins: hsusbb1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ + >; + }; + + hsusb1phy_pins: hsusb1phy-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ + >; + }; + + w2cbw0015_pins: w2cbw0015-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ + OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ + OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ + OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ + OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ + OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ + >; + }; + + mmc5_pins: mmc5-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ + >; + }; +}; + +/* PMIC */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + #clock-cells = <0>; + reg = <0x4b>; + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +/* on-board bluetooth / WiFi module */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; +}; + +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&vmmc>; + ti,bus-width = <4>; + ti,non-removable; /* FIXME: use PMIC_MMC detect */ +}; + +&mmc2 { + status = "disabled"; +}; + +/* mmc3 is available to the expansion board */ + +&mmc4 { + status = "disabled"; +}; + +/* on-board WiFi module */ +&mmc5 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc5_pins>; + + vmmc-supply = <&w2cbw0015_vmmc>; + ti,bus-width = <4>; + ti,non-removable; + cap-power-off-card; + keep-power-in-suspend; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts new file mode 100644 index 000000000000..e119e2cccc4e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Andreas Kemnade + */ +/dts-v1/; + +#include +#include "omap4460.dtsi" + +/ { + model = "Epson Moverio BT-200"; + compatible = "epson,embt2ws", "ti,omap4460", "ti,omap4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1024M */ + }; + + backlight-left { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 1 7812500>; + power-supply = <&unknown_supply>; + }; + + backlight-right { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 0 7812500>; + power-supply = <&unknown_supply>; + }; + + chosen { + stdout-path = &uart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-lock { + label = "Lock"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; /* SW_TOUCHPAD_LOCK */ + linux,input-type = ; + }; + }; + + unknown_supply: unknown-supply { + compatible = "regulator-fixed"; + regulator-name = "unknown"; + }; + + /* regulator for wl12xx on sdio2 */ + wl12xx_vmmc: wl12xx-vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: pmic@48 { + compatible = "ti,twl6032"; + reg = <0x48>; + /* IRQ# = 7 */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + interrupt-controller; + #interrupt-cells = <1>; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + ldo2: regulator-ldo2 { + compatible = "ti,twl6032-ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo4: regulator-ldo4 { + compatible = "ti,twl6032-ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + }; + + ldo3: regulator-ldo3 { + compatible = "ti,twl6032-ldo3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo5: regulator-ldo5 { + compatible = "ti,twl6032-ldo5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + ti,retain-on-reset; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,twl6032-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + }; + + ldo7: regulator-ldo7 { + compatible = "ti,twl6032-ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2900000>; + }; + + ldoln: regulator-ldoln { + compatible = "ti,twl6032-ldoln"; + regulator-always-on; + }; + + ldo6: regulator-ldo6 { + compatible = "ti,twl6032-ldo6"; + regulator-always-on; + }; + + ldousb: regulator-ldousb { + compatible = "ti,twl6032-ldousb"; + regulator-always-on; + }; + + vio: regulator-vio { + compatible = "ti,twl6032-vio"; + regulator-always-on; + }; + + twl_usb_comparator: usb-comparator { + compatible = "ti,twl6030-usb"; + interrupts = <4>, <10>; + }; + + twl_pwm: pwm { + /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + twl_pwmled: pwmled { + /* provides one PWM (id 0 for Charging indicator LED) */ + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; + + gpadc { + compatible = "ti,twl6032-gpadc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; + + }; +}; + +#include "twl6030_omap4.dtsi" + +&twl_usb_comparator { + usb-supply = <&ldousb>; +}; + + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <200000>; + + /* at head/glasses */ + mpu9150h: imu@68 { + compatible = "invensense,mpu9150"; + reg = <0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&mpu9150h_pins>; + interrupt-parent = <&gpio2>; + interrupt = <19 IRQ_TYPE_LEVEL_HIGH>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <100000>; + + /* TODO: BD2606MVV at 0x66 */ +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <360000>; + + /* TODO: KXTI9 at 0xf */ + + tlv320aic3x: codec@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&tlv320aic3x_pins>; + #sound-dai-cells = <0>; + + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + /* TODO: mpu9150 at control unit, seems to require quirks */ +}; + +&keypad { + pinctrl-names = "default"; + pinctrl-0 = <&keypad_pins>; + keypad,num-rows = <2>; + keypad,num-columns = <3>; + linux,keymap = ; + linux,input-no-autorepeat; +}; + +&mcbsp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + + +&mmc1 { + /* sdcard */ + vmmc-supply = <&ldo5>; + broken-cd; + bus-width = <4>; +}; + +&mmc2 { + /* emmc */ + vmmc-supply = <&ldo2>; + bus-width = <8>; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_pins>; + vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x12e>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupts-extended = <&gpio1 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq"; + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&omap4_pmx_core { + bt_pins: pinmux-bt-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE3) /* gpio25 */ + >; + }; + + gpio_keys_pins: pinmux-gpio-key-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x56, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio35 */ + >; + }; + + i2c1_pins: pinmux-i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux-i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: pinmux-i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ + >; + }; + + keypad_pins: pinmux-keypad-pins { + pinctrl-single,pins = < + /* kpd_row0 */ + OMAP4_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_row1 */ + OMAP4_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_row2 */ + OMAP4_IOPAD(0x0054, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_col0 */ + OMAP4_IOPAD(0x0058, PIN_OUTPUT | MUX_MODE1) + /* kpd_col1 */ + OMAP4_IOPAD(0x005a, PIN_OUTPUT | MUX_MODE1) + /* kpd_col2 */ + OMAP4_IOPAD(0x005c, PIN_OUTPUT | MUX_MODE1) + >; + }; + + mcbsp2_pins: pinmux-mcbsp2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ + >; + }; + + mpu9150h_pins: pinmux-mpu9150h-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x76, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + tlv320aic3x_pins: pinmux-tlv320aic3x-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x7e, PIN_OUTPUT | MUX_MODE3) + >; + }; + + uart2_pins: pinmux-uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux-uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ + >; + }; + + usb_otg_hs_pins: pinmux-usb-otg-hs-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ + >; + }; + + wl12xx_pins: pinmux-wl12xx-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1c6, PIN_INPUT | MUX_MODE3) /* gpio_23 / IRQ */ + OMAP4_IOPAD(0x16c, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat2 */ + OMAP4_IOPAD(0x16e, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat1 */ + OMAP4_IOPAD(0x170, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat0 */ + OMAP4_IOPAD(0x172, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat3 */ + OMAP4_IOPAD(0x174, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_cmd */ + OMAP4_IOPAD(0x176, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_clk */ + >; + }; + + wl12xx_gpio: pinmux-wl12xx-gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE3) /* gpio_24 / WLAN_EN */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins &bt_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; + + /* + * BT + GPS in WL1283 in WG7500 requiring CLK32KAUDIO of pmic + * which does not have a driver + */ +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_hs_pins>; + + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-kc1.dts b/arch/arm/boot/dts/ti/omap/omap4-kc1.dts new file mode 100644 index 000000000000..c6b79ba8bbc9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-kc1.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2016 Paul Kocialkowski + */ +/dts-v1/; + +#include "omap443x.dtsi" + +/ { + model = "Amazon Kindle Fire (first generation)"; + compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + led-controller { + compatible = "pwm-leds"; + + led-1 { + label = "green"; + pwms = <&twl_pwm 0 7812500>; + max-brightness = <127>; + }; + + led-2 { + label = "orange"; + pwms = <&twl_pwm 1 7812500>; + max-brightness = <127>; + }; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ + OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ + OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */ + OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */ + OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */ + OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */ + OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */ + OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */ + OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */ + OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ + >; + }; + + usb_otg_hs_pins: usb-otg-hs-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* IRQ# = 7 */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + + twl_power: power { + compatible = "ti,twl6030-power"; + ti,system-power-controller; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + vmmc-supply = <&vaux1>; + ti,non-removable; + bus-width = <8>; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_hs_pins>; + + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi new file mode 100644 index 000000000000..7ae8b620515c --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi @@ -0,0 +1,497 @@ +&l4_abe { /* 0x40100000 */ + compatible = "ti,omap4-l4-abe", "simple-pm-bus"; + reg = <0x40100000 0x400>, + <0x40100400 0x400>; + reg-names = "la", "ap"; + power-domains = <&prm_abe>; + /* OMAP4_L4_ABE_CLKCTRL is read-only */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ + <0x49000000 0x49000000 0x100000>; + segment@0 { /* 0x40100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = + /* CPU to L4 ABE mapping */ + <0x00000000 0x00000000 0x000400>, /* ap 0 */ + <0x00000400 0x00000400 0x000400>, /* ap 1 */ + <0x00022000 0x00022000 0x001000>, /* ap 2 */ + <0x00023000 0x00023000 0x001000>, /* ap 3 */ + <0x00024000 0x00024000 0x001000>, /* ap 4 */ + <0x00025000 0x00025000 0x001000>, /* ap 5 */ + <0x00026000 0x00026000 0x001000>, /* ap 6 */ + <0x00027000 0x00027000 0x001000>, /* ap 7 */ + <0x00028000 0x00028000 0x001000>, /* ap 8 */ + <0x00029000 0x00029000 0x001000>, /* ap 9 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ + <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ + <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ + <0x00030000 0x00030000 0x001000>, /* ap 14 */ + <0x00031000 0x00031000 0x001000>, /* ap 15 */ + <0x00032000 0x00032000 0x001000>, /* ap 16 */ + <0x00033000 0x00033000 0x001000>, /* ap 17 */ + <0x00038000 0x00038000 0x001000>, /* ap 18 */ + <0x00039000 0x00039000 0x001000>, /* ap 19 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ + <0x00080000 0x00080000 0x010000>, /* ap 26 */ + <0x00080000 0x00080000 0x001000>, /* ap 27 */ + <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ + <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ + <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ + <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ + <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ + <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ + + /* L3 to L4 ABE mapping */ + <0x49000000 0x49000000 0x000400>, /* ap 0 */ + <0x49000400 0x49000400 0x000400>, /* ap 1 */ + <0x49022000 0x49022000 0x001000>, /* ap 2 */ + <0x49023000 0x49023000 0x001000>, /* ap 3 */ + <0x49024000 0x49024000 0x001000>, /* ap 4 */ + <0x49025000 0x49025000 0x001000>, /* ap 5 */ + <0x49026000 0x49026000 0x001000>, /* ap 6 */ + <0x49027000 0x49027000 0x001000>, /* ap 7 */ + <0x49028000 0x49028000 0x001000>, /* ap 8 */ + <0x49029000 0x49029000 0x001000>, /* ap 9 */ + <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ + <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ + <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ + <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ + <0x49030000 0x49030000 0x001000>, /* ap 14 */ + <0x49031000 0x49031000 0x001000>, /* ap 15 */ + <0x49032000 0x49032000 0x001000>, /* ap 16 */ + <0x49033000 0x49033000 0x001000>, /* ap 17 */ + <0x49038000 0x49038000 0x001000>, /* ap 18 */ + <0x49039000 0x49039000 0x001000>, /* ap 19 */ + <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ + <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ + <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ + <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ + <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ + <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ + <0x49080000 0x49080000 0x010000>, /* ap 26 */ + <0x49080000 0x49080000 0x001000>, /* ap 27 */ + <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ + <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ + <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ + <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ + <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ + <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ + + target-module@22000 { /* 0x40122000, ap 2 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2208c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>, + <0x49022000 0x49022000 0x1000>; + + mcbsp1: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@24000 { /* 0x40124000, ap 4 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2408c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>, + <0x49024000 0x49024000 0x1000>; + + mcbsp2: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@26000 { /* 0x40126000, ap 6 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>, + <0x49026000 0x49026000 0x1000>; + + mcbsp3: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@28000 { /* 0x40128000, ap 8 08.0 */ + /* 0x4012a000, ap 10 0a.0 */ + compatible = "ti,sysc-mcasp", "ti,sysc"; + reg = <0x28000 0x4>, + <0x28004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>, + <0x49028000 0x49028000 0x1000>, + <0x2000 0x2a000 0x1000>, + <0x4902a000 0x4902a000 0x1000>; + + mcasp0: mcasp@0 { + compatible = "ti,omap4-mcasp-audio"; + reg = <0x0 0x2000>, + <0x4902a000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = ; + interrupt-names = "tx"; + dmas = <&sdma 8>; + dma-names = "tx"; + clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; + clock-names = "fck"; + op-mode = <1>; /* MCASP_DIT_MODE */ + serial-dir = < 1 >; /* 1 TX serializers */ + status = "disabled"; + }; + }; + + target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>, + <0x4902e000 0x4902e000 0x1000>; + + dmic: dmic@0 { + compatible = "ti,omap4-dmic"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 67>; + dma-names = "up_link"; + status = "disabled"; + }; + }; + + target-module@30000 { /* 0x40130000, ap 14 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x30000 0x4>, + <0x30010 0x4>, + <0x30014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>, + <0x49030000 0x49030000 0x1000>; + + wdt3: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>, + <0x49032000 0x49032000 0x1000>; + + /* Must be only enabled for boards with pdmclk wired */ + status = "disabled"; + + mcpdm: mcpdm@0 { + compatible = "ti,omap4-mcpdm"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 65>, + <&sdma 66>; + dma-names = "up_link", "dn_link"; + }; + }; + + target-module@38000 { /* 0x40138000, ap 18 12.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x38000 0x4>, + <0x38010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>, + <0x49038000 0x49038000 0x1000>; + + timer5: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x49038000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3a000 0x4>, + <0x3a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>, + <0x4903a000 0x4903a000 0x1000>; + + timer6: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x4903a000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3c000 0x4>, + <0x3c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>, + <0x4903c000 0x4903c000 0x1000>; + + timer7: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x4903c000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>, + <0x4903e000 0x4903e000 0x1000>; + + timer8: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x00000000 0x80>, + <0x4903e000 0x80>; + clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + ti,timer-dsp; + }; + }; + + target-module@80000 { /* 0x40180000, ap 26 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>, + <0x49080000 0x49080000 0x10000>; + }; + + target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x10000>, + <0x490a0000 0x490a0000 0x10000>; + }; + + target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x10000>, + <0x490c0000 0x490c0000 0x10000>; + }; + + target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xf1000 0x4>, + <0xf1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf1000 0x1000>, + <0x490f1000 0x490f1000 0x1000>; + + /* + * No child device binding or driver in mainline. + * See Android tree and related upstreaming efforts + * for the old driver. + */ + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi new file mode 100644 index 000000000000..46b8f9efd413 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -0,0 +1,2483 @@ +// SPDX-License-Identifier: GPL-2.0 +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,omap4-l4-cfg", "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ + <0x00080000 0x4a080000 0x080000>, /* segment 1 */ + <0x00100000 0x4a100000 0x080000>, /* segment 2 */ + <0x00180000 0x4a180000 0x080000>, /* segment 3 */ + <0x00200000 0x4a200000 0x080000>, /* segment 4 */ + <0x00280000 0x4a280000 0x080000>, /* segment 5 */ + <0x00300000 0x4a300000 0x080000>; /* segment 6 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00002000 0x00002000 0x001000>, /* ap 3 */ + <0x00003000 0x00003000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 5 */ + <0x00005000 0x00005000 0x001000>, /* ap 6 */ + <0x00056000 0x00056000 0x001000>, /* ap 7 */ + <0x00057000 0x00057000 0x001000>, /* ap 8 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ + <0x00058000 0x00058000 0x004000>, /* ap 10 */ + <0x00062000 0x00062000 0x001000>, /* ap 11 */ + <0x00063000 0x00063000 0x001000>, /* ap 12 */ + <0x00008000 0x00008000 0x002000>, /* ap 23 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ + <0x00066000 0x00066000 0x001000>, /* ap 25 */ + <0x00067000 0x00067000 0x001000>, /* ap 26 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ + <0x00060000 0x00060000 0x001000>, /* ap 81 */ + <0x00064000 0x00064000 0x001000>, /* ap 86 */ + <0x00065000 0x00065000 0x001000>; /* ap 87 */ + + target-module@2000 { /* 0x4a002000, ap 3 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + omap4_scm_core: scm@0 { + compatible = "ti,omap4-scm-core", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + + omap_control_usb2phy: control-phy@300 { + compatible = "ti,control-phy-usb2"; + reg = <0x300 0x4>; + reg-names = "power"; + }; + + omap_control_usbotg: control-phy@33c { + compatible = "ti,control-phy-otghs"; + reg = <0x33c 0x4>; + reg-names = "otghs_control"; + }; + }; + }; + + target-module@4000 { /* 0x4a004000, ap 5 02.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + cm1: cm1@0 { + compatible = "ti,omap4-cm1", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm1_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm1_clockdomains: clockdomains { + }; + }; + }; + + target-module@8000 { /* 0x4a008000, ap 23 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + + cm2: cm2@0 { + compatible = "ti,omap4-cm2", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm2_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm2_clockdomains: clockdomains { + }; + }; + }; + + target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ + clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma", "ti,omap-sdma"; + reg = <0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; + }; + + target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000 0x4>, + <0x58010 0x4>, + <0x58014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x5000>; + + hsi: hsi@0 { + compatible = "ti,omap4-hsi"; + reg = <0x0 0x4000>, + <0x5000 0x1000>; + reg-names = "sys", "gdd"; + + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "hsi_fck"; + + interrupts = ; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + }; + }; + + target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@62000 { /* 0x4a062000, ap 11 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x62000 0x4>, + <0x62010 0x4>, + <0x62014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + + usbhstll: usbhstll@0 { + compatible = "ti,usbhs-tll"; + reg = <0x0 0x1000>; + interrupts = ; + }; + }; + + target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x64000 0x4>, + <0x64010 0x4>, + <0x64014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + + usbhshost: usbhshost@0 { + compatible = "ti,usbhs-host"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + clocks = <&init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; + + usbhsohci: ohci@800 { + compatible = "ti,ohci-omap3"; + reg = <0x800 0x400>; + interrupts = ; + remote-wakeup-connected; + }; + + usbhsehci: ehci@c00 { + compatible = "ti,ehci-omap"; + reg = <0xc00 0x400>; + interrupts = ; + }; + }; + }; + + target-module@66000 { /* 0x4a066000, ap 25 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x66000 0x4>, + <0x66010 0x4>, + <0x66014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + clock-names = "fck"; + power-domains = <&prm_tesla>; + resets = <&prm_tesla 1>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + mmu_dsp: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + }; + }; + }; + + segment@80000 { /* 0x4a080000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ + <0x0005a000 0x000da000 0x001000>, /* ap 14 */ + <0x0005b000 0x000db000 0x001000>, /* ap 15 */ + <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ + <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ + <0x0005e000 0x000de000 0x001000>, /* ap 18 */ + <0x00060000 0x000e0000 0x001000>, /* ap 19 */ + <0x00061000 0x000e1000 0x001000>, /* ap 20 */ + <0x00074000 0x000f4000 0x001000>, /* ap 27 */ + <0x00075000 0x000f5000 0x001000>, /* ap 28 */ + <0x00076000 0x000f6000 0x001000>, /* ap 29 */ + <0x00077000 0x000f7000 0x001000>, /* ap 30 */ + <0x00036000 0x000b6000 0x001000>, /* ap 69 */ + <0x00037000 0x000b7000 0x001000>, /* ap 70 */ + <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ + <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ + <0x00029000 0x000a9000 0x001000>, /* ap 82 */ + <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ + <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ + <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ + <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ + <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ + + target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x29000 0x1000>; + }; + + target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2b000 0x1000>; + + usb_otg_hs: usb_otg_hs@0 { + compatible = "ti,omap4-musb"; + reg = <0x0 0x7ff>; + interrupts = , ; + interrupt-names = "mc", "dma"; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + ctrl-module = <&omap_control_usbotg>; + }; + }; + + target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2d000 0x4>, + <0x2d010 0x4>, + <0x2d014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2d000 0x1000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + reg = <0x0 0x1f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + usb2_phy: usb2phy@80 { + compatible = "ti,omap-usb2"; + reg = <0x80 0x58>; + ctrl-module = <&omap_control_usb2phy>; + clocks = <&usb_phy_cm_clk32k>; + clock-names = "wkupclk"; + #phy-cells = <0>; + }; + }; + }; + + /* d2d mdm */ + target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x36000 0x4>, + <0x36010 0x4>, + <0x36014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ + clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + /* d2d mpu */ + target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4d000 0x4>, + <0x4d010 0x4>, + <0x4d014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ + clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000 0x1000>; + }; + + target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + reg = <0x59038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + smartreflex_mpu: smartreflex@0 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + reg = <0x5b038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + smartreflex_iva: smartreflex@0 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + reg = <0x5d038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x74000 0x4>, + <0x74010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + mbox_ipu: mbox-ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; + }; + }; + + target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x76000 0x4>, + <0x76010 0x4>, + <0x76014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ + <0x00001000 0x00101000 0x001000>, /* ap 22 */ + <0x00002000 0x00102000 0x001000>, /* ap 61 */ + <0x00003000 0x00103000 0x001000>, /* ap 62 */ + <0x00008000 0x00108000 0x001000>, /* ap 63 */ + <0x00009000 0x00109000 0x001000>, /* ap 64 */ + <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ + <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ + + target-module@0 { /* 0x4a100000, ap 21 2a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>, + <0x10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + omap4_pmx_core: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_padconf_global: omap4_padconf_global@5a0 { + compatible = "syscon", + "simple-bus"; + reg = <0x5a0 0x170>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5a0 0x170>; + + pbias_regulator: pbias_regulator@60 { + compatible = "ti,pbias-omap4", "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap4_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap4 { + regulator-name = "pbias_mmc_omap4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + }; + + target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 63 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>, + <0xa010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,sysc-delay-us = <2>; + /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ + clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + }; + + segment@180000 { /* 0x4a180000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ + <0x00004000 0x00204000 0x001000>, /* ap 35 */ + <0x00005000 0x00205000 0x001000>, /* ap 36 */ + <0x00006000 0x00206000 0x001000>, /* ap 37 */ + <0x00007000 0x00207000 0x001000>, /* ap 38 */ + <0x00012000 0x00212000 0x001000>, /* ap 39 */ + <0x00013000 0x00213000 0x001000>, /* ap 40 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ + <0x00010000 0x00210000 0x001000>, /* ap 43 */ + <0x00011000 0x00211000 0x001000>, /* ap 44 */ + <0x00016000 0x00216000 0x001000>, /* ap 45 */ + <0x00017000 0x00217000 0x001000>, /* ap 46 */ + <0x00014000 0x00214000 0x001000>, /* ap 47 */ + <0x00015000 0x00215000 0x001000>, /* ap 48 */ + <0x00018000 0x00218000 0x001000>, /* ap 49 */ + <0x00019000 0x00219000 0x001000>, /* ap 50 */ + <0x00020000 0x00220000 0x001000>, /* ap 51 */ + <0x00021000 0x00221000 0x001000>, /* ap 52 */ + <0x00026000 0x00226000 0x001000>, /* ap 53 */ + <0x00027000 0x00227000 0x001000>, /* ap 54 */ + <0x00028000 0x00228000 0x001000>, /* ap 55 */ + <0x00029000 0x00229000 0x001000>, /* ap 56 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ + <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ + + target-module@4000 { /* 0x4a204000, ap 35 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 43 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 39 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 47 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x4a216000, ap 45 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 49 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 51 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 53 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + }; + + segment@280000 { /* 0x4a280000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ + <0x00040000 0x00340000 0x001000>, /* ap 68 */ + <0x00020000 0x00320000 0x004000>, /* ap 71 */ + <0x00024000 0x00324000 0x002000>, /* ap 72 */ + <0x00026000 0x00326000 0x001000>, /* ap 73 */ + <0x00027000 0x00327000 0x001000>, /* ap 74 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00030000 0x00330000 0x010000>, /* ap 77 */ + <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ + <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ + + l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00020000>, + <0x00020000 0x00020000 0x00004000>, + <0x00024000 0x00024000 0x00002000>, + <0x00026000 0x00026000 0x00001000>, + <0x00027000 0x00027000 0x00001000>, + <0x00028000 0x00028000 0x00001000>, + <0x00029000 0x00029000 0x00001000>, + <0x0002a000 0x0002a000 0x00002000>, + <0x0002c000 0x0002c000 0x00004000>, + <0x00030000 0x00030000 0x00010000>; + }; + }; +}; + +&l4_wkup { /* 0x4a300000 */ + compatible = "ti,omap4-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkup>; + clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4a300000 0x800>, + <0x4a300800 0x800>, + <0x4a301000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ + <0x00010000 0x4a310000 0x010000>, /* segment 1 */ + <0x00020000 0x4a320000 0x010000>; /* segment 2 */ + + segment@0 { /* 0x4a300000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ + <0x00004000 0x00004000 0x001000>, /* ap 17 */ + <0x00005000 0x00005000 0x001000>, /* ap 18 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ + + target-module@4000 { /* 0x4a304000, ap 17 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; + }; + + target-module@6000 { /* 0x4a306000, ap 3 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,omap4-prm", "simple-bus"; + reg = <0x0 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + }; + + target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + scrm: scrm@0 { + compatible = "ti,omap4-scrm"; + reg = <0x0 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + }; + + target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc000 0x4>, + <0xc010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + }; + }; + }; + + segment@10000 { /* 0x4a310000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ + <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ + <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ + + gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@4000 { /* 0x4a314000, ap 7 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x8000 0x4>, + <0x8010 0x4>, + <0x8014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-alwon; + }; + }; + + target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xc000 0x4>, + <0xc010 0x4>, + <0xc014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + keypad: keypad@0 { + compatible = "ti,omap4-keypad"; + reg = <0x0 0x80>; + interrupts = ; + reg-names = "mpu"; + }; + }; + + target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xe000 0x4>, + <0xe010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + }; + }; + + segment@20000 { /* 0x4a320000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 23 */ + <0x00001000 0x00021000 0x001000>, /* ap 24 */ + <0x00002000 0x00022000 0x001000>, /* ap 25 */ + <0x00003000 0x00023000 0x001000>, /* ap 26 */ + <0x00004000 0x00024000 0x001000>, /* ap 27 */ + <0x00005000 0x00025000 0x001000>, /* ap 28 */ + <0x00007000 0x00027000 0x000400>, /* ap 29 */ + <0x00008000 0x00028000 0x000800>, /* ap 30 */ + <0x00009000 0x00029000 0x000400>; /* ap 31 */ + + target-module@0 { /* 0x4a320000, ap 23 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x4a324000, ap 27 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a326000, ap 13 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00003000 0x00009000 0x00000400>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,omap4-l4-per", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00040000 0x00040000 0x010000>, /* ap 13 */ + <0x00050000 0x00050000 0x001000>, /* ap 14 */ + <0x00055000 0x00055000 0x001000>, /* ap 15 */ + <0x00056000 0x00056000 0x001000>, /* ap 16 */ + <0x00057000 0x00057000 0x001000>, /* ap 17 */ + <0x00058000 0x00058000 0x001000>, /* ap 18 */ + <0x00059000 0x00059000 0x001000>, /* ap 19 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ + <0x00060000 0x00060000 0x001000>, /* ap 25 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ + <0x00070000 0x00070000 0x001000>, /* ap 32 */ + <0x00071000 0x00071000 0x001000>, /* ap 33 */ + <0x00072000 0x00072000 0x001000>, /* ap 34 */ + <0x00073000 0x00073000 0x001000>, /* ap 35 */ + <0x00061000 0x00061000 0x001000>, /* ap 36 */ + <0x00096000 0x00096000 0x001000>, /* ap 37 */ + <0x00097000 0x00097000 0x001000>, /* ap 38 */ + <0x00076000 0x00076000 0x001000>, /* ap 39 */ + <0x00077000 0x00077000 0x001000>, /* ap 40 */ + <0x00078000 0x00078000 0x001000>, /* ap 41 */ + <0x00079000 0x00079000 0x001000>, /* ap 42 */ + <0x00086000 0x00086000 0x001000>, /* ap 43 */ + <0x00087000 0x00087000 0x001000>, /* ap 44 */ + <0x00088000 0x00088000 0x001000>, /* ap 45 */ + <0x00089000 0x00089000 0x001000>, /* ap 46 */ + <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ + <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ + <0x00098000 0x00098000 0x001000>, /* ap 49 */ + <0x00099000 0x00099000 0x001000>, /* ap 50 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ + <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ + <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ + <0x00090000 0x00090000 0x002000>, /* ap 57 */ + <0x00092000 0x00092000 0x001000>, /* ap 58 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ + <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ + <0x00001400 0x00001400 0x000400>, /* ap 81 */ + <0x00001800 0x00001800 0x000400>, /* ap 82 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ + <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@32000 { /* 0x48032000, ap 5 02.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x32000 0x4>, + <0x32010 0x4>, + <0x32014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@34000 { /* 0x48034000, ap 7 04.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@36000 { /* 0x48036000, ap 9 0e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + /* Unused DSS L4 access, see L3 instead */ + target-module@40000 { /* 0x48040000, ap 13 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + }; + + target-module@55000 { /* 0x48055000, ap 15 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@57000 { /* 0x48057000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@59000 { /* 0x48059000, ap 19 10.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@60000 { /* 0x48060000, ap 25 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@70000 { /* 0x48070000, ap 32 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@72000 { /* 0x48072000, ap 34 30.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@76000 { /* 0x48076000, ap 39 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x76000 0x4>, + <0x76010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + + target-module@78000 { /* 0x48078000, ap 41 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x78000 0x4>, + <0x78010 0x4>, + <0x78014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + }; + + target-module@86000 { /* 0x48086000, ap 43 24.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x86000 0x4>, + <0x86010 0x4>, + <0x86014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@88000 { /* 0x48088000, ap 45 2e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; + }; + + target-module@96000 { /* 0x48096000, ap 37 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x96000 0x1000>; + + mcbsp4: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@98000 { /* 0x48098000, ap 49 22.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + }; + + target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + }; + + target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + }; + + target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9e000 0x1000>; + }; + + target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + + target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb0000 0x1000>; + }; + + target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xb2000 0x4>, + <0xb2014 0x4>, + <0xb2018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + ti,no-reset-on-init; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + + hdqw1w: 1w@0 { + compatible = "ti,omap3-1w"; + reg = <0x0 0x1000>; + interrupts = ; + }; + }; + + target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, <&sdma 16>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 57>, <&sdma 58>; + dma-names = "tx", "rx"; + }; + }; + + target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd5000 0x4>, + <0xd5010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + + mmc5: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 59>, <&sdma 60>; + dma-names = "tx", "rx"; + }; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ + <0x00151000 0x00351000 0x001000>; /* ap 78 */ + + target-module@150000 { /* 0x48350000, ap 77 4c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x150000 0x8>, + <0x150010 0x8>, + <0x150090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x150000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi b/arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi new file mode 100644 index 000000000000..03ade47431fb --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common omap4 mcpdm configuration + * + * Only include this file if your board has pdmclk wired from the + * pmic to ABE as mcpdm uses an external clock for the module. + */ + +&omap4_pmx_core { + mcpdm_pins: mcpdm-pins { + pinctrl-single,pins = < + /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ + OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) + + /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */ + OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) + + /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */ + OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) + + /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */ + OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) + + /* 0x4a10010e abe_clks.abe_clks ah26 */ + OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; +}; + +&mcpdm_module { + /* + * McPDM pads must be muxed at the interconnect target module + * level as the module on the SoC needs external clock from + * the PMIC + */ + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; + +&mcpdm { + clocks = <&twl6040>; + clock-names = "pdmclk"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts new file mode 100644 index 000000000000..8fd076e5d1b0 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap443x.dtsi" +#include "omap4-panda-common.dtsi" + +/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ +&dss_hdmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi new file mode 100644 index 000000000000..f528511c2537 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include +#include "elpida_ecb240abacn.dtsi" +#include "omap4-mcpdm.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@98000000 { + compatible = "shared-dma-pool"; + reg = <0x98000000 0x800000>; + reusable; + status = "okay"; + }; + + ipu_memory_region: ipu-memory@98800000 { + compatible = "shared-dma-pool"; + reg = <0x98800000 0x7000000>; + reusable; + status = "okay"; + }; + }; + + chosen { + stdout-path = &uart3; + }; + + aliases { + display0 = &dvi0; + display1 = &hdmi0; + ethernet = ðernet; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = < + &led_wkgpio_pins + >; + + led-heartbeat { + label = "pandaboard::status1"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-mmc { + label = "pandaboard::status2"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = < + &button_pins + >; + + buttonS2 { + label = "button S2"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + linux,code = ; + wakeup-source; + }; + }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "PandaBoard"; + + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */ + startup-delay-us = <70000>; + enable-active-high; + /* + * boot-on is required along with always-on as the + * regulator framework doesn't enable the regulator + * if boot-on is not there. + */ + regulator-always-on; + regulator-boot-on; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + #phy-cells = <0>; + vcc-supply = <&hsusb1_power>; + clocks = <&auxclk3_ck>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + + /* regulator for wl12xx on sdio5 */ + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tpd12s015: encoder1 { + compatible = "ti,tpd12s015"; + + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ + <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ + <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi0: connector1 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins + &tfp410_pins + &dss_hdmi_pins + &tpd12s015_pins + &hsusbb1_pins + >; + + twl6040_pins: twl6040-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ + OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + >; + }; + + mcbsp1_pins: mcbsp1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ + OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ + OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ + OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ + OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ + OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ + OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ + OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ + OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ + OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ + OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ + + OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ + OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ + OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ + OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ + OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ + OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ + OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ + OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ + OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ + OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ + OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ + OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ + OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ + OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ + + OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ + OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ + OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ + >; + }; + + tfp410_pins: tfp410-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ + >; + }; + + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; + }; + + tpd12s015_pins: tpd12s015-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ + OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ + OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ + >; + }; + + hsusbb1_pins: hsusbb1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + /* + * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP + * REVISIT: Are the pull-ups needed for GPIO 48 and 49? + */ + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ + OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ + >; + }; + + /* wl12xx GPIO inputs and SDIO pins */ + wl12xx_pins: wl12xx-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ + OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ + >; + }; +}; + +&omap4_pmx_wkup { + led_wkgpio_pins: leds-wkpins-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ + OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* IRQ# = 7 */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + #clock-cells = <0>; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + /* IRQ# = 119 */ + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <100000>; + + /* + * Display monitor features are burnt in their EEPROM as EDID data. + * The EEPROM is connected as I2C slave device. + */ + eeprom@50 { + compatible = "ti,eeprom"; + reg = <0x50>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_pins>; + vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x10e>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + /* gpio_53 with gpmc_ncs3 pad as wakeup */ + interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>, + <&omap4_pmx_core 0x3a>; + interrupt-names = "irq", "wakeup"; + ref-clock-frequency = <38400000>; + }; +}; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; + +&uart2 { + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&uart4 { + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART4_RX>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; + +&dss { + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "okay"; + vdd-supply = <&vcxio>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&dsp { + status = "okay"; + memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer9>, <&timer11>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts new file mode 100644 index 000000000000..fe7b156d10ed --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap4460.dtsi" +#include "omap4-panda-common.dtsi" + +/ { + model = "TI OMAP4 PandaBoard-ES"; + compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; +}; + +/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ +&sound { + ti,model = "PandaBoardES"; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "AFML", "Line In", + "AFMR", "Line In"; +}; + +/* PandaboardES has external pullups on SCL & SDA */ +&dss_hdmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +}; + +&omap4_pmx_core { + led_gpio_pins: gpio-led-pmx-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ + >; + }; + + button_pins: button-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ + >; + }; + + bt_pins: bt-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ + OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; +}; + +&led_wkgpio_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ + >; +}; + +&leds { + pinctrl-0 = < + &led_gpio_pins + &led_wkgpio_pins + >; + + led-heartbeat { + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + }; + led-mmc { + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio_keys { + buttonS2 { + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */ + }; +}; + +&gpio1_target { + ti,no-reset-on-init; +}; + +&wl12xx_gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ + >; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins &bt_pins>; + bluetooth: tiwi { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda.dts b/arch/arm/boot/dts/ti/omap/omap4-panda.dts new file mode 100644 index 000000000000..529d5bcceaaf --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-panda.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap443x.dtsi" +#include "omap4-panda-common.dtsi" + +/ { + model = "TI OMAP4 PandaBoard"; + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts new file mode 100644 index 000000000000..869f6279b5be --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include "omap4-sdp.dts" + +/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ +&dss_hdmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-sdp.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts new file mode 100644 index 000000000000..b2cb93edbc3a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap443x.dtsi" +#include "elpida_ecb240abacn.dtsi" +#include "omap4-mcpdm.dtsi" + +/ { + model = "TI OMAP4 SDP board"; + compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + aliases { + display0 = &lcd0; + display1 = &lcd1; + display2 = &hdmi0; + }; + + vdd_eth: fixedregulator-vdd-eth { + pinctrl-names = "default"; + pinctrl-0 = <&enet_enable_gpio>; + + compatible = "regulator-fixed"; + regulator-name = "VDD_ETH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */ + enable-active-high; + regulator-boot-on; + startup-delay-us = <25000>; + }; + + vbat: fixedregulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + regulator-min-microvolt = <3750000>; + regulator-max-microvolt = <3750000>; + regulator-boot-on; + }; + + led-controller-1 { + compatible = "gpio-leds"; + + led-1 { + label = "omap4:green:debug0"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ + }; + + led-2 { + label = "omap4:green:debug1"; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ + }; + + led-3 { + label = "omap4:green:debug2"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ + }; + + led-4 { + label = "omap4:green:debug3"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ + }; + + led-5 { + label = "omap4:green:debug4"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ + }; + + led-6 { + label = "omap4:blue:user"; + gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ + }; + + led-7 { + label = "omap4:red:user"; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ + }; + + led-8 { + label = "omap4:green:user"; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ + }; + }; + + led-controller-2 { + compatible = "pwm-leds"; + + led-9 { + label = "omap4::keypad"; + pwms = <&twl_pwm 0 7812500>; + max-brightness = <127>; + }; + + led-10 { + label = "omap4:green:chrg"; + pwms = <&twl_pwmled 0 7812500>; + max-brightness = <255>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 1 7812500>; + brightness-levels = < + 0 10 20 30 40 + 50 60 70 80 90 + 100 110 120 127 + >; + default-brightness-level = <13>; + }; + + sound { + compatible = "ti,abe-twl6040"; + ti,model = "SDP4430"; + + ti,jack-detection = <1>; + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + ti,dmic = <&dmic>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Earphone Spk", "EP", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "Vibrator", "VIBRAL", + "Vibrator", "VIBRAR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "MAINMIC", "Main Handset Mic", + "Main Handset Mic", "Main Mic Bias", + "SUBMIC", "Sub Handset Mic", + "Sub Handset Mic", "Main Mic Bias", + "AFML", "Line In", + "AFMR", "Line In", + "DMic", "Digital Mic", + "Digital Mic", "Digital Mic1 Bias"; + }; + + /* regulator for wl12xx on sdio5 */ + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ + <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ + <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "c"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &dss_hdmi_pins + &tpd12s015_pins + >; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ + OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ + >; + }; + + twl6040_pins: twl6040-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ + OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + >; + }; + + dmic_pins: dmic-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ + OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ + OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ + OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ + >; + }; + + mcbsp1_pins: mcbsp1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ + >; + }; + + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; + }; + + tpd12s015_pins: tpd12s015-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ + OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ + OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + /* wl12xx GPIO output for WLAN_EN */ + wl12xx_gpio: wl12xx-gpio-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ + >; + }; + + /* wl12xx GPIO inputs and SDIO pins */ + wl12xx_pins: wl12xx-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ + OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ + >; + }; + + /* gpio_48 for ENET_ENABLE */ + enet_enable_gpio: enet-enable-gpio-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ + >; + }; + + ks8851_pins: ks8851-pins { + pinctrl-single,pins = < + /* ENET_INT */ + OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ + /* + * Misterious pin which makes the ethernet working + * The legacy board file requested this pin on boot + * (ETH_KS8851_QUART) and set it to high, similarly to + * the ENET_ENABLE pin. + * We could use gpio-hog to keep it high, but let's use + * it as a reset GPIO for ks8851. + */ + OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + #clock-cells = <0>; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + + /* regulators for vibra motor */ + vddvibl-supply = <&vbat>; + vddvibr-supply = <&vbat>; + + vibra { + /* Vibra driver, motor resistance parameters */ + ti,vibldrv-res = <8>; + ti,vibrdrv-res = <3>; + ti,viblmotor-res = <10>; + ti,vibrmotor-res = <10>; + }; + }; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; + + /* + * Temperature Sensor + * https://www.ti.com/lit/ds/symlink/tmp105.pdf + */ + tmp105@48 { + compatible = "ti,tmp105"; + reg = <0x48>; + }; + + /* + * Ambient Light Sensor + * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf + */ + bh1780@29 { + compatible = "rohm,bh1780"; + reg = <0x29>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; + + /* + * 3-Axis Digital Compass + * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf + */ + hmc5843@1e { + compatible = "honeywell,hmc5843"; + reg = <0x1e>; + }; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + eth@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ks8851_pins>; + + compatible = "ks8851"; + spi-max-frequency = <24000000>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ + vdd-supply = <&vdd_eth>; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + bus-width = <8>; +}; + +&mmc2 { + vmmc-supply = <&vaux1>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_pins>; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1281"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00000012 /* KEY_E */ + 0x00010013 /* KEY_R */ + 0x00020014 /* KEY_T */ + 0x00030066 /* KEY_HOME */ + 0x0004003f /* KEY_F5 */ + 0x000500f0 /* KEY_UNKNOWN */ + 0x00060017 /* KEY_I */ + 0x0007002a /* KEY_LEFTSHIFT */ + 0x01000020 /* KEY_D*/ + 0x01010021 /* KEY_F */ + 0x01020022 /* KEY_G */ + 0x010300e7 /* KEY_SEND */ + 0x01040040 /* KEY_F6 */ + 0x010500f0 /* KEY_UNKNOWN */ + 0x01060025 /* KEY_K */ + 0x0107001c /* KEY_ENTER */ + 0x0200002d /* KEY_X */ + 0x0201002e /* KEY_C */ + 0x0202002f /* KEY_V */ + 0x0203006b /* KEY_END */ + 0x02040041 /* KEY_F7 */ + 0x020500f0 /* KEY_UNKNOWN */ + 0x02060034 /* KEY_DOT */ + 0x0207003a /* KEY_CAPSLOCK */ + 0x0300002c /* KEY_Z */ + 0x0301004e /* KEY_KPLUS */ + 0x03020030 /* KEY_B */ + 0x0303003b /* KEY_F1 */ + 0x03040042 /* KEY_F8 */ + 0x030500f0 /* KEY_UNKNOWN */ + 0x03060018 /* KEY_O */ + 0x03070039 /* KEY_SPACE */ + 0x04000011 /* KEY_W */ + 0x04010015 /* KEY_Y */ + 0x04020016 /* KEY_U */ + 0x0403003c /* KEY_F2 */ + 0x04040073 /* KEY_VOLUMEUP */ + 0x040500f0 /* KEY_UNKNOWN */ + 0x04060026 /* KEY_L */ + 0x04070069 /* KEY_LEFT */ + 0x0500001f /* KEY_S */ + 0x05010023 /* KEY_H */ + 0x05020024 /* KEY_J */ + 0x0503003d /* KEY_F3 */ + 0x05040043 /* KEY_F9 */ + 0x05050072 /* KEY_VOLUMEDOWN */ + 0x05060032 /* KEY_M */ + 0x0507006a /* KEY_RIGHT */ + 0x06000010 /* KEY_Q */ + 0x0601001e /* KEY_A */ + 0x06020031 /* KEY_N */ + 0x0603009e /* KEY_BACK */ + 0x0604000e /* KEY_BACKSPACE */ + 0x060500f0 /* KEY_UNKNOWN */ + 0x06060019 /* KEY_P */ + 0x06070067 /* KEY_UP */ + 0x07000094 /* KEY_PROG1 */ + 0x07010095 /* KEY_PROG2 */ + 0x070200ca /* KEY_PROG3 */ + 0x070300cb /* KEY_PROG4 */ + 0x0704003e /* KEY_F4 */ + 0x070500f0 /* KEY_UNKNOWN */ + 0x07060160 /* KEY_OK */ + 0x0707006c>; /* KEY_DOWN */ + linux,input-no-autorepeat; +}; + +&uart2 { + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART4_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; +}; + +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + +&dmic { + pinctrl-names = "default"; + pinctrl-0 = <&dmic_pins>; + status = "okay"; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&dss { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + vdd-supply = <&vcxio>; + + port { + dsi1_out_ep: endpoint { + remote-endpoint = <&lcd0_in>; + lanes = <0 1 2 3 4 5>; + }; + }; + + lcd0: panel@0 { + compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; + label = "lcd0"; + + reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ + + port { + lcd0_in: endpoint { + remote-endpoint = <&dsi1_out_ep>; + }; + }; + }; +}; + +&dsi2 { + status = "okay"; + vdd-supply = <&vcxio>; + + port { + dsi2_out_ep: endpoint { + remote-endpoint = <&lcd1_in>; + lanes = <0 1 2 3 4 5>; + }; + }; + + lcd1: panel@0 { + compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; + label = "lcd1"; + + reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ + + port { + lcd1_in: endpoint { + remote-endpoint = <&dsi2_out_ep>; + }; + }; + }; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts new file mode 100644 index 000000000000..84fd17fb0822 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Joachim Eastwood + */ +/dts-v1/; + +#include "omap4-var-som-om44.dtsi" +#include "omap4-var-som-om44-wlan.dtsi" +#include "omap4-var-om44customboard.dtsi" + +/ { + model = "Variscite VAR-DVK-OM44"; + compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + + aliases { + display0 = &lcd0; + display1 = &hdmi0; + }; + + lcd0: display { + compatible = "innolux,at070tn83", "panel-dpi"; + label = "lcd"; + panel-timing { + clock-frequency = <33333333>; + + hback-porch = <40>; + hactive = <800>; + hfront-porch = <40>; + hsync-len = <48>; + + vback-porch = <29>; + vactive = <480>; + vfront-porch = <13>; + vsync-len = <3>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "okay"; + vdd-supply = <&vcxio>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi new file mode 100644 index 000000000000..cadc7e02592b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Joachim Eastwood + */ + +#include + +/ { + aliases { + display0 = &hdmi0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_led_pins>; + + led0 { + label = "var:green:led0"; + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "var:green:led1"; + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + #address-cells = <1>; + #size-cells = <0>; + + user-key@184 { + label = "user"; + gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ + linux,code = ; + wakeup-source; + }; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins>; + label = "hdmi"; + type = "a"; + + hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; +}; + +&omap4_pmx_core { + uart1_pins: uart1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ + OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ + OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ + >; + }; + + mcspi1_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + mcasp_pins: mcsasp-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ + OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ + OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ + OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ + OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ + OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ + OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ + OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ + OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ + OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ + OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ + OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ + OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ + OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ + OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ + OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ + OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ + OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ + OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ + OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ + OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ + OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ + OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ + OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ + OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ + OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ + OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ + OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ + >; + }; + + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; + }; + + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc5_pins: mmc5-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ + OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ + >; + }; + + gpio_led_pins: gpio-led-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ + OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ + >; + }; + + gpio_key_pins: gpio-key-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ + >; + }; + + ks8851_irq_pins: ks8851-irq-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ + >; + }; + + hdmi_hpd_pins: hdmi-hpd-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ + >; + }; + + backlight_pins: backlight-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ + >; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + status = "okay"; + + eth@0 { + compatible = "ks8851"; + pinctrl-names = "default"; + pinctrl-0 = <&ks8851_irq_pins>; + spi-max-frequency = <24000000>; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ + }; +}; + +&mmc5 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc5_pins>; + vmmc-supply = <&vbat>; + bus-width = <4>; + cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ + status = "okay"; +}; + +&dss { + status = "okay"; +}; + +&hdmi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi new file mode 100644 index 000000000000..de779d2d7c3e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Joachim Eastwood + */ + +/ { + /* regulator for wl12xx on sdio4 */ + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_ctrl_pins>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* gpio 43 */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&omap4_pmx_core { + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + wl12xx_ctrl_pins: wl12xx-ctrl-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ + OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ + >; + }; + + mmc4_pins: mmc4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ + OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ + OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ + OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ + OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ + OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&mmc4 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc4_pins>; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ + ref-clock-frequency = <38400000>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi new file mode 100644 index 000000000000..37d56b3010cf --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Joachim Eastwood + * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com + */ +#include "omap4460.dtsi" +#include "omap4-mcpdm.dtsi" + +/ { + model = "Variscite VAR-SOM-OM44"; + compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "VAR-SOM-OM44"; + + ti,mclk-freq = <38400000>; + ti,mcpdm = <&mcpdm>; + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "AFML", "Line In", + "AFMR", "Line In"; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_phy_clk_pins + &hsusbb1_phy_rst_pins + >; + + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ + vcc-supply = <&vbat>; + #phy-cells = <0>; + + clocks = <&auxclk3_ck>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + + vbat: fixedregulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins + >; + + twl6040_pins: twl6040-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ + OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + >; + }; + + tsc2004_pins: tsc2004-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ + OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + hsusbb1_pins: hsusbb1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ + >; + }; + + hsusbb1_phy_rst_pins: hsusbb1-phy-rst-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; +}; + +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_hub_rst_pins + &lan7500_rst_pins + >; + + hsusbb1_phy_clk_pins: hsusbb1-phy-clk-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ + >; + }; + + hsusbb1_hub_rst_pins: hsusbb1-hub-rst-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ + >; + }; + + lan7500_rst_pins: lan7500-rst-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + #clock-cells = <0>; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + ti,audpwron-gpio = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio 182 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +&vusim { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + clock-frequency = <400000>; + + touchscreen: tsc2004@48 { + compatible = "ti,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2004_pins>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ + status = "disabled"; + }; + + tmp105@49 { + compatible = "ti,tmp105"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "microchip,24c32", "atmel,24c32"; + reg = <0x50>; + }; +}; + +&i2c4 { + status = "disabled"; +}; + +&gpmc { + status = "disabled"; +}; + +&mcspi1 { + status = "disabled"; +}; + +&mcspi2 { + status = "disabled"; +}; + +&mcspi3 { + status = "disabled"; +}; + +&mcspi4 { + status = "disabled"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc>; + bus-width = <4>; + ti,non-removable; + status = "okay"; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&keypad { + status = "disabled"; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts b/arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts new file mode 100644 index 000000000000..656fb29c2a15 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Joachim Eastwood + */ +/dts-v1/; + +#include "omap4-var-som-om44.dtsi" +#include "omap4-var-som-om44-wlan.dtsi" +#include "omap4-var-om44customboard.dtsi" + +/ { + model = "Variscite VAR-STK-OM44"; + compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4.dtsi b/arch/arm/boot/dts/ti/omap/omap4.dtsi new file mode 100644 index 000000000000..2bbff9032be3 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4.dtsi @@ -0,0 +1,868 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include +#include + +/ { + compatible = "ti,omap4430", "ti,omap4"; + interrupt-parent = <&wakeupgen>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + mmc3 = &mmc4; + mmc4 = &mmc5; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + rproc0 = &dsp; + rproc1 = &ipu; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&L2>; + reg = <0x0>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + /* + * Needed early by omap4_sram_init() for barrier, do not move to l3 + * interconnect as simple-pm-bus probes at module_init() time. + */ + ocmcram: sram@40304000 { + compatible = "mmio-sram"; + reg = <0x40304000 0xa000>; /* 40k */ + }; + + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + interrupt-parent = <&gic>; + }; + + L2: cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@48240600 { + compatible = "arm,cortex-a9-twd-timer"; + clocks = <&mpu_periphclk>; + reg = <0x48240600 0x20>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller@48281000 { + compatible = "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; + }; + + /* + * XXX: Use a flat representation of the OMAP4 interconnect. + * The real OMAP interconnect network is quite complex. + * Since it will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>, + <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>, + <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + l3-noc@44000000 { + compatible = "ti,omap4-l3-noc"; + reg = <0x44000000 0x1000>, + <0x44800000 0x2000>, + <0x45000000 0x1000>; + interrupts = , + ; + }; + + l4_wkup: interconnect@4a300000 { + }; + + l4_cfg: interconnect@4a000000 { + }; + + l4_per: interconnect@48000000 { + }; + + target-module@48210000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48210000 0x1f0000>; + + mpu { + compatible = "ti,omap4-mpu"; + sram = <&ocmcram>; + }; + }; + + l4_abe: interconnect@40100000 { + }; + + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + ti,no-idle-on-init; + clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,omap4430-gpmc"; + reg = <0x50000000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = ; + dmas = <&sdma 4>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + clocks = <&l3_div_ck>; + clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + target-module@52000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x52000000 0x4>, + <0x52000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,sysc-delay-us = <2>; + power-domains = <&prm_cam>; + clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x52000000 0x1000000>; + + /* No child device binding, driver in staging */ + }; + + /* + * Note that 4430 needs cross trigger interface (CTI) supported + * before we can configure the interrupts. This means sampling + * events are not supported for pmu. Note that 4460 does not use + * CTI, see also 4460.dtsi. + */ + target-module@54000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_emu>; + clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54000000 0x1000000>; + + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + }; + }; + + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + ranges = <0x0 0x55082000 0x100>; + #size-cells = <1>; + #address-cells = <1>; + + mmu_ipu: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; + }; + + target-module@4012c000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4012c000 0x4>, + <0x4012c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ + <0x4902c000 0x4902c000 0x1000>; /* L3 */ + + /* No child device binding or driver in mainline */ + }; + + target-module@4e000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4e000000 0x4>, + <0x4e000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + ranges = <0x0 0x4e000000 0x2000000>; + #size-cells = <1>; + #address-cells = <1>; + + dmm@0 { + compatible = "ti,omap4-dmm"; + reg = <0 0x800>; + interrupts = ; + }; + }; + + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif1: emif@0 { + compatible = "ti,emif-4d"; + reg = <0 0x100>; + interrupts = ; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + }; + + target-module@4d000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4d000000 0x4>; + reg-names = "rev"; + clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000000 0x1000000>; + + emif2: emif@0 { + compatible = "ti,emif-4d"; + reg = <0 0x100>; + interrupts = ; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + }; + + dsp: dsp { + compatible = "ti,omap4-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + resets = <&prm_tesla 0>; + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + firmware-name = "omap4-dsp-fw.xe64T"; + mboxes = <&mailbox &mbox_dsp>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap4-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + firmware-name = "omap4-ipu-fw.xem3"; + mboxes = <&mailbox &mbox_ipu>; + status = "disabled"; + }; + + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; + }; + + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + }; + + abb_mpu: regulator-abb-mpu { + compatible = "ti,abb-v2"; + regulator-name = "abb_mpu"; + #address-cells = <0>; + #size-cells = <0>; + ti,tranxdone-status-mask = <0x80>; + clocks = <&sys_clkin_ck>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + status = "disabled"; + }; + + abb_iva: regulator-abb-iva { + compatible = "ti,abb-v2"; + regulator-name = "abb_iva"; + #address-cells = <0>; + #size-cells = <0>; + ti,tranxdone-status-mask = <0x80000000>; + clocks = <&sys_clkin_ck>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + status = "disabled"; + }; + + sgx_module: target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + power-domains = <&prm_gfx>; + clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + + /* + * DSS is only using l3 mapping without l4 as noted in the TRM + * "10.1.3 DSS Register Manual" for omap4460. + */ + target-module@58000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000000 4>, + <0x58000014 4>; + reg-names = "rev", "syss"; + ti,syss-mask = <1>; + power-domains = <&prm_dss>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x58000000 0x1000000>; + + dss: dss@0 { + compatible = "ti,omap4-dss"; + reg = <0 0x80>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000000>; + + target-module@1000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x1000 0x4>, + <0x1010 0x4>, + <0x1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-midle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x1000>; + + dispc@0 { + compatible = "ti,omap4-dispc"; + reg = <0 0x1000>; + interrupts = ; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + }; + }; + + target-module@2000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2010 0x4>, + <0x2014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + rfbi: encoder@0 { + reg = <0 0x1000>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; + clock-names = "fck", "ick"; + }; + }; + + target-module@3000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x3000 0x4>; + reg-names = "rev"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "sys_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x3000 0x1000>; + + venc: encoder@0 { + compatible = "ti,omap4-venc"; + reg = <0 0x1000>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; + clock-names = "fck"; + }; + }; + + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4000 0x1000>; + + dsi1: encoder@0 { + compatible = "ti,omap4-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = ; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@5000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5000 0x4>, + <0x5010 0x4>, + <0x5014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5000 0x1000>; + + dsi2: encoder@0 { + compatible = "ti,omap4-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = ; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@6000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>, + <0x6010 0x4>; + reg-names = "rev", "sysc"; + /* + * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP + * but HDMI audio will fail with them. + */ + ti,sysc-sidle = , + ; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; + clock-names = "fck", "dss_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x6000 0x2000>; + + hdmi: encoder@0 { + compatible = "ti,omap4-hdmi"; + reg = <0 0x200>, + <0x200 0x100>, + <0x300 0x100>, + <0x400 0x1000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = ; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + dmas = <&sdma 76>; + dma-names = "audio_tx"; + }; + }; + }; + }; + + iva_hd_target: target-module@5a000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5a05a400 0x4>, + <0x5a05a410 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + power-domains = <&prm_ivahd>; + resets = <&prm_ivahd 2>; + reset-names = "rstctrl"; + clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x5a000000 0x1000000>, + <0x5b000000 0x5b000000 0x1000000>; + + iva { + compatible = "ti,ivahd"; + }; + }; + }; +}; + +#include "omap4-l4.dtsi" +#include "omap4-l4-abe.dtsi" +#include "omap44xx-clocks.dtsi" + +&prm { + prm_mpu: prm@300 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + + prm_tesla: prm@400 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_abe: prm@500 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #power-domain-cells = <0>; + }; + + prm_always_on_core: prm@600 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x600 0x100>; + #power-domain-cells = <0>; + }; + + prm_core: prm@700 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x700 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_ivahd: prm@f00 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_cam: prm@1000 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1000 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1100 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x100>; + #power-domain-cells = <0>; + }; + + prm_gfx: prm@1200 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #power-domain-cells = <0>; + }; + + prm_l3init: prm@1300 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1300 0x100>; + #power-domain-cells = <0>; + }; + + prm_l4per: prm@1400 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1400 0x100>; + #power-domain-cells = <0>; + }; + + prm_cefuse: prm@1600 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1600 0x100>; + #power-domain-cells = <0>; + }; + + prm_wkup: prm@1700 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1700 0x100>; + #power-domain-cells = <0>; + }; + + prm_emu: prm@1900 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1900 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1100 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x40>; + #power-domain-cells = <0>; + }; + + prm_device: prm@1b00 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + }; +}; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi new file mode 100644 index 000000000000..581e088231b5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&prm_clocks { + bandgap_fclk: bandgap_fclk@1888 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "bandgap_fclk"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1888>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap443x.dtsi b/arch/arm/boot/dts/ti/omap/omap443x.dtsi new file mode 100644 index 000000000000..238aceb799f8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap443x.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP443x SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "omap4.dtsi" + +/ { + cpus { + cpu0: cpu@0 { + /* OMAP443x variants OPP50-OPPNT */ + operating-points = < + /* kHz uV */ + 300000 1025000 + 600000 1200000 + 800000 1313000 + 1008000 1375000 + >; + clock-latency = <300000>; /* From legacy driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + thermal-zones { + #include "omap4-cpu-thermal.dtsi" + }; + + ocp { + /* 4430 has only gpio_86 tshut and no talert interrupt */ + bandgap: bandgap@4a002260 { + reg = <0x4a002260 0x4 + 0x4a00232C 0x4>; + compatible = "ti,omap4430-bandgap"; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + + #thermal-sensor-cells = <0>; + }; + }; + + ocp { + abb_mpu: regulator-abb-mpu { + status = "okay"; + + reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; + reg-names = "base-address", "int-address"; + + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1025000 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1313000 0 0 0 0 0 + 1375000 1 0 0 0 0 + 1389000 1 0 0 0 0 + >; + }; + + /* Default unused, just provide register info for record */ + abb_iva: regulator-abb-iva { + reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; + reg-names = "base-address", "int-address"; + }; + + }; + +}; + +&cpu_thermal { + coefficients = <0 20000>; +}; + +/include/ "omap443x-clocks.dtsi" + +/* + * Use dpll_per for sgx at 307.2MHz like droid4 stock v3.0.8 Android kernel + */ +&sgx_module { + assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>, + <&dpll_per_m7x2_ck>; + assigned-clock-rates = <0>, <307200000>; + assigned-clock-parents = <&dpll_per_m7x2_ck>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4460.dtsi b/arch/arm/boot/dts/ti/omap/omap4460.dtsi new file mode 100644 index 000000000000..1b27a862ae81 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4460.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP4460 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include "omap4.dtsi" + +/ { + cpus { + /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 350000 1025000 + 700000 1200000 + 920000 1313000 + >; + clock-latency = <300000>; /* From legacy driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + thermal-zones { + #include "omap4-cpu-thermal.dtsi" + }; + + ocp { + bandgap: bandgap@4a002260 { + reg = <0x4a002260 0x4 + 0x4a00232C 0x4 + 0x4a002378 0x18>; + compatible = "ti,omap4460-bandgap"; + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */ + + #thermal-sensor-cells = <0>; + }; + + abb_mpu: regulator-abb-mpu { + status = "okay"; + + reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, + <0x4A002268 0x4>; + reg-names = "base-address", "int-address", + "efuse-address"; + + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1025000 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1313000 0 0 0x100000 0x40000 0 + 1375000 1 0 0 0 0 + 1389000 1 0 0 0 0 + >; + }; + + abb_iva: regulator-abb-iva { + status = "okay"; + + reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, + <0x4A002268 0x4>; + reg-names = "base-address", "int-address", + "efuse-address"; + + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 950000 0 0 0 0 0 + 1140000 0 0 0 0 0 + 1291000 0 0 0x200000 0 0 + 1375000 1 0 0 0 0 + 1376000 1 0 0 0 0 + >; + }; + }; + +}; + +&cpu_thermal { + coefficients = <348 (-9301)>; +}; + +/* Only some L4 CFG interconnect ranges are different on 4460 */ +&l4_cfg_segment_300000 { + ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ + <0x00040000 0x00340000 0x001000>, /* ap 68 */ + <0x00020000 0x00320000 0x004000>, /* ap 71 */ + <0x00024000 0x00324000 0x002000>, /* ap 72 */ + <0x00026000 0x00326000 0x001000>, /* ap 73 */ + <0x00027000 0x00327000 0x001000>, /* ap 74 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00030000 0x00330000 0x010000>, /* ap 77 */ + <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ + <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ + <0x00010000 0x00310000 0x008000>, /* ap 92 */ + <0x00018000 0x00318000 0x004000>, /* ap 93 */ + <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ + <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ +}; + +&l4_cfg_target_0 { + ranges = <0x00000000 0x00000000 0x00010000>, + <0x00010000 0x00010000 0x00008000>, + <0x00018000 0x00018000 0x00004000>, + <0x0001c000 0x0001c000 0x00002000>, + <0x0001e000 0x0001e000 0x00002000>, + <0x00020000 0x00020000 0x00004000>, + <0x00024000 0x00024000 0x00002000>, + <0x00026000 0x00026000 0x00001000>, + <0x00027000 0x00027000 0x00001000>, + <0x00028000 0x00028000 0x00001000>, + <0x00029000 0x00029000 0x00001000>, + <0x0002a000 0x0002a000 0x00002000>, + <0x0002c000 0x0002c000 0x00004000>, + <0x00030000 0x00030000 0x00010000>; +}; + +&pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + ; +}; + +/include/ "omap446x-clocks.dtsi" diff --git a/arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi new file mode 100644 index 000000000000..d9362fef6720 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&prm_clocks { + div_ts_ck: div_ts_ck@1888 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "div_ts_ck"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <24>; + reg = <0x1888>; + ti,dividers = <8>, <16>, <32>; + }; + + bandgap_ts_fclk: bandgap_ts_fclk@1888 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "bandgap_ts_fclk"; + clocks = <&div_ts_ck>; + ti,bit-shift = <8>; + reg = <0x1888>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi new file mode 100644 index 000000000000..8df73d285638 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi @@ -0,0 +1,1483 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm1_clocks { + extalt_clkin_ck: extalt_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "extalt_clkin_ck"; + clock-frequency = <59000000>; + }; + + pad_clks_src_ck: pad_clks_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; + clock-frequency = <12000000>; + }; + + pad_clks_ck: pad_clks_ck@108 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; + clocks = <&pad_clks_src_ck>; + ti,bit-shift = <8>; + reg = <0x0108>; + }; + + pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "pad_slimbus_core_clks_ck"; + clock-frequency = <12000000>; + }; + + secure_32k_clk_src_ck: secure_32k_clk_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; + clock-frequency = <32768>; + }; + + slimbus_src_clk: slimbus_src_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; + clock-frequency = <12000000>; + }; + + slimbus_clk: slimbus_clk@108 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; + clocks = <&slimbus_src_clk>; + ti,bit-shift = <10>; + reg = <0x0108>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; + clock-frequency = <32768>; + }; + + virt_12000000_ck: virt_12000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; + clock-frequency = <12000000>; + }; + + virt_13000000_ck: virt_13000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; + clock-frequency = <13000000>; + }; + + virt_16800000_ck: virt_16800000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; + clock-frequency = <16800000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; + clock-frequency = <26000000>; + }; + + virt_27000000_ck: virt_27000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; + clock-frequency = <27000000>; + }; + + virt_38400000_ck: virt_38400000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; + clock-frequency = <38400000>; + }; + + tie_low_clock_ck: tie_low_clock_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "tie_low_clock_ck"; + clock-frequency = <0>; + }; + + utmi_phy_clkout_ck: utmi_phy_clkout_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "utmi_phy_clkout_ck"; + clock-frequency = <60000000>; + }; + + xclk60mhsp1_ck: xclk60mhsp1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; + clock-frequency = <60000000>; + }; + + xclk60mhsp2_ck: xclk60mhsp2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; + clock-frequency = <60000000>; + }; + + xclk60motg_ck: xclk60motg_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xclk60motg_ck"; + clock-frequency = <60000000>; + }; + + dpll_abe_ck: dpll_abe_ck@1e0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; + clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; + reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; + }; + + dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; + clocks = <&dpll_abe_ck>; + reg = <0x01f0>; + }; + + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + abe_24m_fclk: abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + abe_clk: abe_clk@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; + clocks = <&dpll_abe_m2x2_ck>; + ti,max-div = <4>; + reg = <0x0108>; + ti,index-power-of-two; + }; + + + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "core_hsd_byp_clk_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x012c>; + }; + + dpll_core_ck: dpll_core_ck@120 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; + clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; + reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0140>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m2_ck: dpll_core_m2_ck@130 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; + clocks = <&dpll_core_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0130>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + ddrphy_ck: ddrphy_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "ddrphy_ck"; + clocks = <&dpll_core_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x013c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + div_core_ck: div_core_ck@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "div_core_ck"; + clocks = <&dpll_core_m5x2_ck>; + reg = <0x0100>; + ti,max-div = <2>; + }; + + div_iva_hs_clk: div_iva_hs_clk@1dc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "div_iva_hs_clk"; + clocks = <&dpll_core_m5x2_ck>; + ti,max-div = <4>; + reg = <0x01dc>; + ti,index-power-of-two; + }; + + div_mpu_hs_clk: div_mpu_hs_clk@19c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "div_mpu_hs_clk"; + clocks = <&dpll_core_m5x2_ck>; + ti,max-div = <4>; + reg = <0x019c>; + ti,index-power-of-two; + }; + + dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0138>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dll_clk_div_ck: dll_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dll_clk_div_ck"; + clocks = <&dpll_core_m4x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; + clocks = <&dpll_abe_ck>; + ti,max-div = <31>; + reg = <0x01f0>; + ti,index-starts-at-one; + }; + + dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_core_m3x2_gate_ck"; + clocks = <&dpll_core_x2_ck>; + ti,bit-shift = <8>; + reg = <0x0134>; + }; + + dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_core_m3x2_div_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0134>; + ti,index-starts-at-one; + }; + + dpll_core_m3x2_ck: dpll_core_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "dpll_core_m3x2_ck"; + clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; + }; + + dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m7x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0144>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "iva_hsd_byp_clk_mux_ck"; + clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; + ti,bit-shift = <23>; + reg = <0x01ac>; + }; + + dpll_iva_ck: dpll_iva_ck@1a0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; + clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; + reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <931200000>; + }; + + dpll_iva_x2_ck: dpll_iva_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; + clocks = <&dpll_iva_ck>; + }; + + dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m4x2_ck"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01b8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m4x2_ck>; + assigned-clock-rates = <465600000>; + }; + + dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m5x2_ck"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01bc>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m5x2_ck>; + assigned-clock-rates = <266100000>; + }; + + dpll_mpu_ck: dpll_mpu_ck@160 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; + clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; + reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0170>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + per_hs_clk_div_ck: per_hs_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "per_hs_clk_div_ck"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usb_hs_clk_div_ck: usb_hs_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "usb_hs_clk_div_ck"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + l3_div_ck: l3_div_ck@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_div_ck"; + clocks = <&div_core_ck>; + ti,bit-shift = <4>; + ti,max-div = <2>; + reg = <0x0100>; + }; + + l4_div_ck: l4_div_ck@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_div_ck"; + clocks = <&l3_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <2>; + reg = <0x0100>; + }; + + lp_clk_div_ck: lp_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "lp_clk_div_ck"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + mpu_periphclk: mpu_periphclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; + clocks = <&dpll_mpu_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + ocp_abe_iclk: ocp_abe_iclk@528 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "ocp_abe_iclk"; + clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; + ti,bit-shift = <24>; + reg = <0x0528>; + ti,dividers = <2>, <1>; + }; + + per_abe_24m_fclk: per_abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "per_abe_24m_fclk"; + clocks = <&dpll_abe_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; + clock-frequency = <0>; + }; +}; + +&prm_clocks { + sys_clkin_ck: sys_clkin_ck@110 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; + }; + + abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux_ck"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0108>; + }; + + abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_refclk_mux_ck"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + reg = <0x010c>; + }; + + dbgclk_mux_ck: dbgclk_mux_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dbgclk_mux_ck"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "l4_wkup_clk_mux_ck"; + clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; + reg = <0x0108>; + }; + + syc_clk_div_ck: syc_clk_div_ck@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "syc_clk_div_ck"; + clocks = <&sys_clkin_ck>; + reg = <0x0100>; + ti,max-div = <2>; + }; + + usim_ck: usim_ck@1858 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "usim_ck"; + clocks = <&dpll_per_m4x2_ck>; + ti,bit-shift = <24>; + reg = <0x1858>; + ti,dividers = <14>, <18>; + }; + + usim_fclk: usim_fclk@1858 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usim_fclk"; + clocks = <&usim_ck>; + ti,bit-shift = <8>; + reg = <0x1858>; + }; + + trace_clk_div_ck: trace_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clock-output-names = "trace_clk_div_ck"; + clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; + }; +}; + +&prm_clockdomains { + emu_sys_clkdm: emu_sys_clkdm { + compatible = "ti,clockdomain"; + clock-output-names = "emu_sys_clkdm"; + clocks = <&trace_clk_div_ck>; + }; +}; + +&cm2_clocks { + per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "per_hsd_byp_clk_mux_ck"; + clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; + ti,bit-shift = <23>; + reg = <0x014c>; + }; + + dpll_per_ck: dpll_per_ck@140 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; + clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; + reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; + }; + + dpll_per_m2_ck: dpll_per_m2_ck@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + reg = <0x0150>; + ti,index-starts-at-one; + }; + + dpll_per_x2_ck: dpll_per_x2_ck@150 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; + clocks = <&dpll_per_ck>; + reg = <0x0150>; + }; + + dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_per_m3x2_gate_ck"; + clocks = <&dpll_per_x2_ck>; + ti,bit-shift = <8>; + reg = <0x0154>; + }; + + dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_per_m3x2_div_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + reg = <0x0154>; + ti,index-starts-at-one; + }; + + dpll_per_m3x2_ck: dpll_per_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "dpll_per_m3x2_ck"; + clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; + }; + + dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m4x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m5x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m6x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0160>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m7x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0164>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_usb_ck: dpll_usb_ck@180 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; + clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; + reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; + }; + + dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo_ck"; + clocks = <&dpll_usb_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x01b4>; + ti,clock-mult = <1>; + ti,invert-autoidle-bit; + }; + + dpll_usb_m2_ck: dpll_usb_m2_ck@190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0190>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + ducati_clk_mux_ck: ducati_clk_mux_ck@100 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "ducati_clk_mux_ck"; + clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; + reg = <0x0100>; + }; + + func_12m_fclk: func_12m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + func_24m_clk: func_24m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_24mc_fclk: func_24mc_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_24mc_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + func_48m_fclk: func_48m_fclk@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "func_48m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + reg = <0x0108>; + ti,dividers = <4>, <8>; + }; + + func_48mc_fclk: func_48mc_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_48mc_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_64m_fclk: func_64m_fclk@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "func_64m_fclk"; + clocks = <&dpll_per_m4x2_ck>; + reg = <0x0108>; + ti,dividers = <2>, <4>; + }; + + func_96m_fclk: func_96m_fclk@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "func_96m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + reg = <0x0108>; + ti,dividers = <2>, <4>; + }; + + init_60m_fclk: init_60m_fclk@104 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "init_60m_fclk"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x0104>; + ti,dividers = <1>, <8>; + }; + + per_abe_nc_fclk: per_abe_nc_fclk@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "per_abe_nc_fclk"; + clocks = <&dpll_abe_m2_ck>; + reg = <0x0108>; + ti,max-div = <2>; + }; + + usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0640>; + }; +}; + +&cm2_clockdomains { + l3_init_clkdm: l3_init_clkdm { + compatible = "ti,clockdomain"; + clock-output-names = "l3_init_clkdm"; + clocks = <&dpll_usb_ck>; + }; +}; + +&scrm_clocks { + auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0310>; + }; + + auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0310>; + }; + + auxclk0_src_ck: auxclk0_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; + clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; + }; + + auxclk0_ck: auxclk0_ck@310 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; + clocks = <&auxclk0_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0310>; + }; + + auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0314>; + }; + + auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0314>; + }; + + auxclk1_src_ck: auxclk1_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; + clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; + }; + + auxclk1_ck: auxclk1_ck@314 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; + clocks = <&auxclk1_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0314>; + }; + + auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0318>; + }; + + auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0318>; + }; + + auxclk2_src_ck: auxclk2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; + clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; + }; + + auxclk2_ck: auxclk2_ck@318 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; + clocks = <&auxclk2_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0318>; + }; + + auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x031c>; + }; + + auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x031c>; + }; + + auxclk3_src_ck: auxclk3_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; + clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; + }; + + auxclk3_ck: auxclk3_ck@31c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; + clocks = <&auxclk3_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x031c>; + }; + + auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0320>; + }; + + auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0320>; + }; + + auxclk4_src_ck: auxclk4_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; + clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; + }; + + auxclk4_ck: auxclk4_ck@320 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; + clocks = <&auxclk4_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0320>; + }; + + auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk5_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0324>; + }; + + auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk5_src_mux_ck"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0324>; + }; + + auxclk5_src_ck: auxclk5_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk5_src_ck"; + clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; + }; + + auxclk5_ck: auxclk5_ck@324 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk5_ck"; + clocks = <&auxclk5_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0324>; + }; + + auxclkreq0_ck: auxclkreq0_ck@210 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0210>; + }; + + auxclkreq1_ck: auxclkreq1_ck@214 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0214>; + }; + + auxclkreq2_ck: auxclkreq2_ck@218 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0218>; + }; + + auxclkreq3_ck: auxclkreq3_ck@21c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x021c>; + }; + + auxclkreq4_ck: auxclkreq4_ck@220 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq4_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0220>; + }; + + auxclkreq5_ck: auxclkreq5_ck@224 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq5_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0224>; + }; +}; + +&cm1 { + mpuss_cm: mpuss_cm@300 { + compatible = "ti,omap4-cm"; + clock-output-names = "mpuss_cm"; + reg = <0x300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300 0x100>; + + mpuss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "mpuss_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + tesla_cm: tesla_cm@400 { + compatible = "ti,omap4-cm"; + clock-output-names = "tesla_cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + tesla_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "tesla_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + abe_cm: abe_cm@500 { + compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + abe_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; + reg = <0x20 0x6c>; + #clock-cells = <2>; + }; + }; + +}; + +&cm2 { + l4_ao_cm: l4_ao_cm@600 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_ao_cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + l4_ao_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_ao_clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + l3_1_cm: l3_1_cm@700 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_1_cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + l3_1_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_1_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_2_cm: l3_2_cm@800 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_2_cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l3_2_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_2_clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + ducati_cm: ducati_cm@900 { + compatible = "ti,omap4-cm"; + clock-output-names = "ducati_cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + ducati_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "ducati_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_dma_cm: l3_dma_cm@a00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_dma_cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + l3_dma_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_dma_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_emif_cm: l3_emif_cm@b00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_emif_cm"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb00 0x100>; + + l3_emif_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_emif_clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + d2d_cm: d2d_cm@c00 { + compatible = "ti,omap4-cm"; + clock-output-names = "d2d_cm"; + reg = <0xc00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xc00 0x100>; + + d2d_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "d2d_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l4_cfg_cm: l4_cfg_cm@d00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_cfg_cm"; + reg = <0xd00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd00 0x100>; + + l4_cfg_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_cfg_clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + l3_instr_cm: l3_instr_cm@e00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_instr_cm"; + reg = <0xe00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe00 0x100>; + + l3_instr_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_instr_clkctrl"; + reg = <0x20 0x24>; + #clock-cells = <2>; + }; + }; + + ivahd_cm: ivahd_cm@f00 { + compatible = "ti,omap4-cm"; + clock-output-names = "ivahd_cm"; + reg = <0xf00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xf00 0x100>; + + ivahd_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "ivahd_clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + iss_cm: iss_cm@1000 { + compatible = "ti,omap4-cm"; + clock-output-names = "iss_cm"; + reg = <0x1000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x100>; + + iss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "iss_clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + l3_dss_cm: l3_dss_cm@1100 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_dss_cm"; + reg = <0x1100 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1100 0x100>; + + l3_dss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_dss_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_gfx_cm: l3_gfx_cm@1200 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_gfx_cm"; + reg = <0x1200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1200 0x100>; + + l3_gfx_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_gfx_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3_init_cm: l3_init_cm@1300 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3_init_cm"; + reg = <0x1300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1300 0x100>; + + l3_init_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3_init_clkctrl"; + reg = <0x20 0xc4>; + #clock-cells = <2>; + }; + }; + + l4_per_cm: clock@1400 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_per_cm"; + reg = <0x1400 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x200>; + + l4_per_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_per_clkctrl"; + reg = <0x20 0x144>; + #clock-cells = <2>; + }; + + l4_secure_clkctrl: clock@1a0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_secure_clkctrl"; + reg = <0x1a0 0x3c>; + #clock-cells = <2>; + }; + }; +}; + +&prm { + l4_wkup_cm: l4_wkup_cm@1800 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4_wkup_cm"; + reg = <0x1800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1800 0x100>; + + l4_wkup_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; + reg = <0x20 0x5c>; + #clock-cells = <2>; + }; + }; + + emu_sys_cm: emu_sys_cm@1a00 { + compatible = "ti,omap4-cm"; + clock-output-names = "emu_sys_cm"; + reg = <0x1a00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1a00 0x100>; + + emu_sys_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "emu_sys_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi new file mode 100644 index 000000000000..6f46f1ecf1e5 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include "omap5.dtsi" +#include +#include + +/ { + aliases { + display0 = &hdmi0; + }; + + chosen { + stdout-path = &uart3; + }; + + vmain: fixedregulator-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vsys_cobra: fixedregulator-vsys_cobra { + compatible = "regulator-fixed"; + regulator-name = "vsys_cobra"; + vin-supply = <&vmain>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vmmcsd_fixed: fixedregulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + mmc3_pwrseq: sdhci0_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&clk32kgaudio>; + clock-names = "ext_clock"; + }; + + vmmcsdio_fixed: fixedregulator-mmcsdio { + compatible = "regulator-fixed"; + regulator-name = "vmmcsdio_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ + enable-active-high; + startup-delay-us = <70000>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pins>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ + clocks = <&auxclk1_ck>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + #phy-cells = <0>; + }; + + /* HS USB Host PHY on PORT 3 */ + hsusb3_phy: hsusb3_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ + #phy-cells = <0>; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + pinctrl-names = "default"; + pinctrl-0 = <&tpd12s015_pins>; + + /* gpios defined in the board specific dts */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "b"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "omap5-uevm"; + + ti,jack-detection; + ti,mclk-freq = <19200000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; +}; + +&gpio8 { + /* TI trees use GPIO instead of msecure, see also muxing */ + msecure-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "gpio8_234/msecure"; + }; +}; + +&omap5_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &usbhost_pins + &led_gpio_pins + >; + + twl6040_pins: twl6040-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ + >; + }; + + mcpdm_pins: mcpdm-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ + OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ + OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ + OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ + OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ + >; + }; + + mcbsp1_pins: mcbsp1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ + OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ + OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ + OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ + >; + }; + + mcbsp2_pins: mcbsp2-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ + OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ + OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ + OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + mcspi2_pins: mcspi2-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ + OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ + OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ + OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ + >; + }; + + mcspi3_pins: mcspi3-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ + OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ + OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ + OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ + OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ + OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ + OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ + OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ + OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ + >; + }; + + wlan_pins: wlan-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ + >; + }; + + /* TI trees use GPIO mode; msecure mode does not work reliably? */ + palmas_msecure_pins: palmas-msecure-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ + >; + }; + + usbhost_pins: usbhost-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ + OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ + + OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ + OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ + + OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ + OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ + >; + }; + + led_gpio_pins: led-gpio-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ + >; + }; + + uart1_pins: uart1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ + OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ + OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ + OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ + OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ + >; + }; + + uart5_pins: uart5-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ + OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ + OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ + OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ + >; + }; + + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ + OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ + >; + }; + + tpd12s015_pins: tpd12s015-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ + >; + }; +}; + +&omap5_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &usbhost_wkup_pins + >; + + palmas_sys_nirq_pins: palmas-sys-nirq-pins { + pinctrl-single,pins = < + /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ + OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + usbhost_wkup_pins: usbhost-wkup-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ + >; + }; + + wlcore_irq_pin: wlcore-irq-pin-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&ldo9_reg>; + bus-width = <4>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + vmmc-supply = <&vmmcsdio_fixed>; + mmc-pwrseq = <&mmc3_pwrseq>; + bus-width = <4>; + non-removable; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap5_pmx_core 0x16a>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&wlcore_irq_pin>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ + ref-clock-frequency = <26000000>; + }; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + palmas: palmas@48 { + compatible = "ti,palmas"; + /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ + interrupts = ; + reg = <0x48>; + interrupt-controller; + #interrupt-cells = <2>; + ti,system-power-controller; + ti,mux-pad1 = <0xa1>; + ti,mux-pad2 = <0x1b>; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + extcon_usb3: palmas_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + ti,wakeup; + id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; + }; + + clk32kgaudio: palmas_clk32k@1 { + compatible = "ti,palmas-clk32kgaudio"; + #clock-cells = <0>; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + ti,backup-battery-chargeable; + ti,backup-battery-charge-high-current; + }; + + gpadc: gpadc { + compatible = "ti,palmas-gpadc"; + interrupts = <18 0 + 16 0 + 17 0>; + #io-channel-cells = <1>; + ti,channel0-current-microamp = <5>; + ti,channel3-current-microamp = <10>; + }; + + palmas_pmic { + compatible = "ti,palmas-pmic"; + interrupt-parent = <&palmas>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupt-names = "short-irq"; + + ti,ldo6-vibrator; + + smps123-in-supply = <&vsys_cobra>; + smps45-in-supply = <&vsys_cobra>; + smps6-in-supply = <&vsys_cobra>; + smps7-in-supply = <&vsys_cobra>; + smps8-in-supply = <&vsys_cobra>; + smps9-in-supply = <&vsys_cobra>; + smps10_out2-in-supply = <&vsys_cobra>; + smps10_out1-in-supply = <&vsys_cobra>; + ldo1-in-supply = <&vsys_cobra>; + ldo2-in-supply = <&vsys_cobra>; + ldo3-in-supply = <&vdds_1v8_main>; + ldo4-in-supply = <&vdds_1v8_main>; + ldo5-in-supply = <&vsys_cobra>; + ldo6-in-supply = <&vdds_1v8_main>; + ldo7-in-supply = <&vsys_cobra>; + ldo8-in-supply = <&vsys_cobra>; + ldo9-in-supply = <&vmmcsd_fixed>; + ldoln-in-supply = <&vsys_cobra>; + ldousb-in-supply = <&vsys_cobra>; + + regulators { + smps123_reg: smps123 { + /* VDD_OPP_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_OPP_MM */ + regulator-name = "smps45"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_DDR3 - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdds_1v8_main: + smps7_reg: smps7 { + /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ + regulator-name = "smps7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_OPP_CORE */ + regulator-name = "smps8"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDA_2v1_AUD over VDD_2v1 */ + regulator-name = "smps9"; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + ti,smps-range = <0x80>; + }; + + smps10_out2_reg: smps10_out2 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1_reg: smps10_out1 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ldo1_reg: ldo1 { + /* VDDAPHY_CAM: vdda_csiport */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2_reg: ldo2 { + /* VCC_2V8_DISP: Does not go anywhere */ + regulator-name = "ldo2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + /* Unused */ + status = "disabled"; + }; + + ldo3_reg: ldo3 { + /* VDDAPHY_MDM: vdda_lli */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + /* Only if Modem is used */ + status = "disabled"; + }; + + ldo4_reg: ldo4 { + /* VDDAPHY_DISP: vdda_dsiport/hdmi */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PHY: usb/sata/hdmi.. */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: ldo6 { + /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7_reg: ldo7 { + /* VDD_VPP: vpp1 */ + regulator-name = "ldo7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + /* Only for efuse reprograming! */ + status = "disabled"; + }; + + ldo8_reg: ldo8 { + /* VDD_3v0: Does not go anywhere */ + regulator-name = "ldo8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + /* Unused */ + status = "disabled"; + }; + + ldo9_reg: ldo9 { + /* VCC_DV_SDIO: vdds_sdcard */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3250000>; + regulator-always-on; + regulator-boot-on; + }; + + regen3_reg: regen3 { + /* REGEN3 controls LDO9 supply to card */ + regulator-name = "regen3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + palmas_power_button: palmas_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&palmas>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + #clock-cells = <0>; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ + interrupts = ; + + /* audpwron gpio defined in the board specific dts */ + + vio-supply = <&smps7_reg>; + v2v1-supply = <&smps9_reg>; + enable-active-high; + + clocks = <&clk32kgaudio>, <&fref_xtal_ck>; + clock-names = "clk32k", "mclk"; + }; +}; + +&mcpdm_module { + /* Module on the SoC needs external clock from the PMIC */ + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; + +&mcpdm { + clocks = <&twl6040>; + clock-names = "pdmclk"; +}; + +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + +&usbhshost { + port2-mode = "ehci-hsic"; + port3-mode = "ehci-hsic"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy &hsusb3_phy>; +}; + +&usb3 { + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; +}; + +&dwc3 { + extcon = <&extcon_usb3>; + dr_mode = "otg"; +}; + +&mcspi1 { + +}; + +&mcspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; +}; + +&mcspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi3_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&omap5_pmx_core 0x19c>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; +}; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; + +&dss { + status = "okay"; +}; + +&hdmi { + status = "okay"; + + /* vdda-supply populated in board specific dts file */ + + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts b/arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts new file mode 100644 index 000000000000..abe0b389ad76 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts @@ -0,0 +1,697 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for CompuLab CM-T54 + */ +/dts-v1/; + +#include "omap5.dtsi" +#include +#include + +/ { + model = "CompuLab CM-T54"; + compatible = "compulab,omap5-cm-t54", "ti,omap5"; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ + }; + + aliases { + display0 = &hdmi0; + display1 = &dvi0; + display2 = &lcd0; + }; + + vmmcsd_fixed: fixed-regulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { + compatible = "regulator-fixed"; + regulator-name = "vwlan_pdn_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ldo2_reg>; + gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ + startup-delay-us = <1000>; + enable-active-high; + }; + + vwlan_fixed: fixed-regulator-vwlan { + compatible = "regulator-fixed"; + regulator-name = "vwlan_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vwlan_pdn_fixed>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ + startup-delay-us = <1000>; + enable-active-high; + }; + + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2-phy-pins { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ + #phy-cells = <0>; + }; + + /* HS USB Host PHY on PORT 3 */ + hsusb3_phy: hsusb3_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ + #phy-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "Heartbeat"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + lcd0: display { + compatible = "startek,startek-kd050c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <43>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + }; + }; + }; + + hdmi0: connector0 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_conn_pins>; + + hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_dvi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector1 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c2>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + +&omap5_pmx_wkup { + + ads7846_pins: ads7846-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ + >; + }; + + palmas_sys_nirq_pins: palmas-sys-nirq-pins { + pinctrl-single,pins = < + /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ + OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; +}; + +&omap5_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &led_gpio_pins + &usbhost_pins + >; + + led_gpio_pins: led-gpio-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ + OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ + >; + }; + + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ + OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ + OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ + OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ + OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ + OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ + OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ + OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ + OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ + OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ + OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ + OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ + OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ + OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ + OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ + >; + }; + + mmc3_pins: mmc3-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ + OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ + OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ + OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ + OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ + OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ + >; + }; + + wlan_gpios_pins: wlan-gpios-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ + OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ + >; + }; + + usbhost_pins: usbhost-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ + OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ + + OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ + OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ + + OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ + OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ + >; + }; + + dss_hdmi_pins: dss-hdmi-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ + OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ + OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ + >; + }; + + hdmi_conn_pins: hdmi-conn-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ + >; + }; + + dss_dpi_pins: dss-dpi-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ + OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ + OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ + OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ + OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ + OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ + OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ + OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ + OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ + OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ + OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ + OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ + OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ + OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ + OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ + OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ + OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ + OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ + OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ + OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ + OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ + OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ + OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ + OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ + OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ + OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ + OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ + OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ + >; + }; + + mcspi2_pins: mcspi1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ + OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ + OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ + OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ + >; + }; +}; + +&mcspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio1>; + interrupts = <15 0>; /* gpio1_wk15 */ + pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; + + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + ti,debounce-max = /bits/ 16 <30>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <1>; + + wakeup-source; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&ldo9_reg>; + bus-width = <4>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc3_pins + &wlan_gpios_pins + >; + vmmc-supply = <&vwlan_fixed>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + palmas: palmas@48 { + compatible = "ti,palmas"; + reg = <0x48>; + pinctrl-0 = <&palmas_sys_nirq_pins>; + pinctrl-names = "default"; + /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + ti,system-power-controller; + + extcon_usb3: palmas_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + ti,wakeup; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + }; + + palmas_pmic { + compatible = "ti,palmas-pmic"; + interrupt-parent = <&palmas>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupt-names = "short-irq"; + + ti,ldo6-vibrator; + + regulators { + smps123_reg: smps123 { + /* VDD_OPP_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_OPP_MM */ + regulator-name = "smps45"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_DDR3 - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ + regulator-name = "smps7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_OPP_CORE */ + regulator-name = "smps8"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDA_2v1_AUD over VDD_2v1 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + ti,smps-range = <0x80>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out2_reg: smps10_out2 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1_reg: smps10_out1 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ldo1_reg: ldo1 { + /* VDDAPHY_CAM: vdda_csiport */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2_reg: ldo2 { + /* VDD_3V3_WLAN */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <1000>; + }; + + ldo3_reg: ldo3 { + /* VCC_1V5_AUD */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDAPHY_DISP: vdda_dsiport/hdmi */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PHY: usb/sata/hdmi.. */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: ldo6 { + /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7_reg: ldo7 { + /* VDD_VPP: vpp1 */ + regulator-name = "ldo7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + /* Only for efuse reprograming! */ + status = "disabled"; + }; + + ldo8_reg: ldo8 { + /* VDD_3V_GP: act led/serial console */ + regulator-name = "ldo8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VCC_DV_SDIO: vdds_sdcard */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3250000>; + regulator-always-on; + regulator-boot-on; + }; + + regen3_reg: regen3 { + /* REGEN3 controls LDO9 supply to card */ + regulator-name = "regen3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <100000>; +}; + +&usbhshost { + port2-mode = "ehci-hsic"; + port3-mode = "ehci-hsic"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy &hsusb3_phy>; +}; + +&usb3 { + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; +}; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dpi_dvi_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + + dpi_lcd_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "okay"; + vdd-supply = <&ldo4_reg>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&ldo4_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + lanes = <1 0 3 2 5 4 7 6>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi new file mode 100644 index 000000000000..e0d8e39a0014 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP543x SoC CORE thermal + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + * Contact: Eduardo Valentin + */ + +#include + +core_thermal: core_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 2>; + + trips { + core_crit: core_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi new file mode 100644 index 000000000000..1b4b7d9136c8 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP543x SoC GPU thermal + * + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + * Contact: Eduardo Valentin + */ + +#include + +gpu_thermal: gpu_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 1>; + + trips { + gpu_crit: gpu_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts new file mode 100644 index 000000000000..d4ca2e3a14dd --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ + */ +/dts-v1/; + +#include +#include "omap5-board-common.dtsi" + +/ { + model = "IGEPv5"; + compatible = "isee,omap5-igep0050", "ti,omap5"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ + }; + + aliases { + ethernet = ðernet; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led@1 { + label = "board:green:usr0"; + gpios = <&tca6416 1 0>; + default-state = "off"; + }; + led@2 { + label = "board:red:usr1"; + gpios = <&tca6416 2 0>; + default-state = "off"; + }; + led@3 { + label = "board:blue:usr1"; + gpios = <&tca6416 3 0>; + default-state = "off"; + }; + }; +}; + +&hdmi { + vdda-supply = <&ldo7_reg>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + tca6416: tca6416@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +/* LDO4 is VPP1 - ball AD9 */ +&ldo4_reg { + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; +}; + +/* + * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, + * VDDA_HDMI - ball AN25 + */ +&ldo7_reg { + status = "okay"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&omap5_pmx_core { + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ + OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ + >; + }; + + power_button_pin: power-button-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ + >; + }; +}; + +&tpd12s015 { + gpios = <&tca6416 11 0>, /* TCA6416 P01, CT_CP_HDP */ + <&tca6416 12 0>, /* TCA6416 P00, LS_OE*/ + <&gpio7 1 0>, /* 193, HPD */ + <&gpio7 2 0>, /* 194, SCL */ + <&gpio7 3 0>; /* 195, SDA */ +}; + +&twl6040 { + ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ +}; + +&twl6040_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ + OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ + >; +}; + +&usbhsehci { + #address-cells = <1>; + #size-cells = <0>; + + hub@2 { + compatible = "usb424,3503"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@3 { + compatible = "usb424,7500"; + reg = <3>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi new file mode 100644 index 000000000000..a03bca5a3584 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi @@ -0,0 +1,456 @@ +&l4_abe { /* 0x40100000 */ + compatible = "ti,omap5-l4-abe", "simple-pm-bus"; + reg = <0x40100000 0x400>, + <0x40100400 0x400>; + reg-names = "la", "ap"; + power-domains = <&prm_abe>; + /* OMAP5_L4_ABE_CLKCTRL is read-only */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ + <0x49000000 0x49000000 0x100000>; + segment@0 { /* 0x40100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = + /* CPU to L4 ABE mapping */ + <0x00000000 0x00000000 0x000400>, /* ap 0 */ + <0x00000400 0x00000400 0x000400>, /* ap 1 */ + <0x00022000 0x00022000 0x001000>, /* ap 2 */ + <0x00023000 0x00023000 0x001000>, /* ap 3 */ + <0x00024000 0x00024000 0x001000>, /* ap 4 */ + <0x00025000 0x00025000 0x001000>, /* ap 5 */ + <0x00026000 0x00026000 0x001000>, /* ap 6 */ + <0x00027000 0x00027000 0x001000>, /* ap 7 */ + <0x00028000 0x00028000 0x001000>, /* ap 8 */ + <0x00029000 0x00029000 0x001000>, /* ap 9 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ + <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ + <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ + <0x00030000 0x00030000 0x001000>, /* ap 14 */ + <0x00031000 0x00031000 0x001000>, /* ap 15 */ + <0x00032000 0x00032000 0x001000>, /* ap 16 */ + <0x00033000 0x00033000 0x001000>, /* ap 17 */ + <0x00038000 0x00038000 0x001000>, /* ap 18 */ + <0x00039000 0x00039000 0x001000>, /* ap 19 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ + <0x00080000 0x00080000 0x010000>, /* ap 26 */ + <0x00080000 0x00080000 0x001000>, /* ap 27 */ + <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ + <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ + <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ + <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ + <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ + <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ + + /* L3 to L4 ABE mapping */ + <0x49000000 0x49000000 0x000400>, /* ap 0 */ + <0x49000400 0x49000400 0x000400>, /* ap 1 */ + <0x49022000 0x49022000 0x001000>, /* ap 2 */ + <0x49023000 0x49023000 0x001000>, /* ap 3 */ + <0x49024000 0x49024000 0x001000>, /* ap 4 */ + <0x49025000 0x49025000 0x001000>, /* ap 5 */ + <0x49026000 0x49026000 0x001000>, /* ap 6 */ + <0x49027000 0x49027000 0x001000>, /* ap 7 */ + <0x49028000 0x49028000 0x001000>, /* ap 8 */ + <0x49029000 0x49029000 0x001000>, /* ap 9 */ + <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ + <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ + <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ + <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ + <0x49030000 0x49030000 0x001000>, /* ap 14 */ + <0x49031000 0x49031000 0x001000>, /* ap 15 */ + <0x49032000 0x49032000 0x001000>, /* ap 16 */ + <0x49033000 0x49033000 0x001000>, /* ap 17 */ + <0x49038000 0x49038000 0x001000>, /* ap 18 */ + <0x49039000 0x49039000 0x001000>, /* ap 19 */ + <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ + <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ + <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ + <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ + <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ + <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ + <0x49080000 0x49080000 0x010000>, /* ap 26 */ + <0x49080000 0x49080000 0x001000>, /* ap 27 */ + <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ + <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ + <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ + <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ + <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ + <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ + + target-module@22000 { /* 0x40122000, ap 2 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2208c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>, + <0x49022000 0x49022000 0x1000>; + + mcbsp1: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@24000 { /* 0x40124000, ap 4 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2408c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>, + <0x49024000 0x49024000 0x1000>; + + mcbsp2: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@26000 { /* 0x40126000, ap 6 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>, + <0x49026000 0x49026000 0x1000>; + + mcbsp3: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@28000 { /* 0x40128000, ap 8 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>, + <0x49028000 0x49028000 0x1000>; + }; + + target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>, + <0x4902a000 0x4902a000 0x1000>; + }; + + target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>, + <0x4902e000 0x4902e000 0x1000>; + + dmic: dmic@0 { + compatible = "ti,omap4-dmic"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 67>; + dma-names = "up_link"; + status = "disabled"; + }; + }; + + target-module@30000 { /* 0x40130000, ap 14 0e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>, + <0x49030000 0x49030000 0x1000>; + }; + + mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>, + <0x49032000 0x49032000 0x1000>; + + /* Must be only enabled for boards with pdmclk wired */ + status = "disabled"; + + mcpdm: mcpdm@0 { + compatible = "ti,omap4-mcpdm"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = ; + dmas = <&sdma 65>, + <&sdma 66>; + dma-names = "up_link", "dn_link"; + }; + }; + + target-module@38000 { /* 0x40138000, ap 18 12.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x38000 0x4>, + <0x38010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>, + <0x49038000 0x49038000 0x1000>; + + timer5: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x49038000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + ti,timer-pwm; + }; + }; + + target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3a000 0x4>, + <0x3a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>, + <0x4903a000 0x4903a000 0x1000>; + + timer6: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x4903a000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + ti,timer-pwm; + }; + }; + + target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3c000 0x4>, + <0x3c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>, + <0x4903c000 0x4903c000 0x1000>; + + timer7: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x4903c000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + }; + }; + + target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>, + <0x4903e000 0x4903e000 0x1000>; + + timer8: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>, + <0x4903e000 0x80>; + clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-dsp; + ti,timer-pwm; + }; + }; + + target-module@80000 { /* 0x40180000, ap 26 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>, + <0x49080000 0x49080000 0x10000>; + }; + + target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x10000>, + <0x490a0000 0x490a0000 0x10000>; + }; + + target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x10000>, + <0x490c0000 0x490c0000 0x10000>; + }; + + target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xf1000 0x4>, + <0xf1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf1000 0x1000>, + <0x490f1000 0x490f1000 0x1000>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi new file mode 100644 index 000000000000..3b505fe415ed --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -0,0 +1,2502 @@ +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,omap5-l4-cfg", "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ + <0x00080000 0x4a080000 0x080000>, /* segment 1 */ + <0x00100000 0x4a100000 0x080000>, /* segment 2 */ + <0x00180000 0x4a180000 0x080000>, /* segment 3 */ + <0x00200000 0x4a200000 0x080000>, /* segment 4 */ + <0x00280000 0x4a280000 0x080000>, /* segment 5 */ + <0x00300000 0x4a300000 0x080000>; /* segment 6 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00002000 0x00002000 0x001000>, /* ap 3 */ + <0x00003000 0x00003000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 5 */ + <0x00005000 0x00005000 0x001000>, /* ap 6 */ + <0x00056000 0x00056000 0x001000>, /* ap 7 */ + <0x00057000 0x00057000 0x001000>, /* ap 8 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ + <0x00058000 0x00058000 0x001000>, /* ap 10 */ + <0x00062000 0x00062000 0x001000>, /* ap 11 */ + <0x00063000 0x00063000 0x001000>, /* ap 12 */ + <0x00008000 0x00008000 0x002000>, /* ap 21 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ + <0x00066000 0x00066000 0x001000>, /* ap 23 */ + <0x00067000 0x00067000 0x001000>, /* ap 24 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ + <0x00060000 0x00060000 0x001000>, /* ap 70 */ + <0x00064000 0x00064000 0x001000>, /* ap 71 */ + <0x00065000 0x00065000 0x001000>, /* ap 72 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ + <0x00070000 0x00070000 0x004000>, /* ap 79 */ + <0x00074000 0x00074000 0x001000>, /* ap 80 */ + <0x00075000 0x00075000 0x001000>, /* ap 81 */ + <0x00076000 0x00076000 0x001000>, /* ap 82 */ + <0x00020000 0x00020000 0x020000>, /* ap 109 */ + <0x00040000 0x00040000 0x001000>, /* ap 110 */ + <0x00059000 0x00059000 0x001000>; /* ap 111 */ + + target-module@2000 { /* 0x4a002000, ap 3 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + scm_core: scm@0 { + compatible = "ti,omap5-scm-core", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + scm_padconf_core: scm@800 { + compatible = "ti,omap5-scm-padconf-core", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x800>; + + omap5_pmx_core: pinmux@40 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0x40 0x01b6>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap5_padconf_global: omap5_padconf_global@5a0 { + compatible = "syscon", + "simple-bus"; + reg = <0x5a0 0xec>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5a0 0xec>; + + pbias_regulator: pbias_regulator@60 { + compatible = "ti,pbias-omap5", "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap5_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + }; + + target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + cm_core_aon: cm_core_aon@0 { + compatible = "ti,omap5-cm-core-aon", + "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + }; + + target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + + cm_core: cm_core@0 { + compatible = "ti,omap5-cm-core", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; + }; + + target-module@20000 { /* 0x4a020000, ap 109 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x20000>; + + usb3: omap_dwc3@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + dwc3: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "peripheral"; + }; + }; + }; + + target-module@56000 { /* 0x4a056000, ap 7 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ + clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma", "ti,omap-sdma"; + reg = <0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; + }; + + target-module@58000 { /* 0x4a058000, ap 10 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00058000 0x00001000>, + <0x00001000 0x00059000 0x00001000>, + <0x00002000 0x0005a000 0x00001000>, + <0x00003000 0x0005b000 0x00001000>; + }; + + target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x62000 0x4>, + <0x62010 0x4>, + <0x62014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + + usbhstll: usbhstll@0 { + compatible = "ti,usbhs-tll"; + reg = <0x0 0x1000>; + interrupts = ; + }; + }; + + target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x64000 0x4>, + <0x64010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + + usbhshost: usbhshost@0 { + compatible = "ti,usbhs-host"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + clocks = <&l3init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; + + usbhsohci: ohci@800 { + compatible = "ti,ohci-omap3"; + reg = <0x800 0x400>; + interrupts = ; + remote-wakeup-connected; + }; + + usbhsehci: ehci@c00 { + compatible = "ti,ehci-omap"; + reg = <0xc00 0x400>; + interrupts = ; + }; + }; + }; + + target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x66000 0x4>, + <0x66010 0x4>, + <0x66014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp 1>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + mmu_dsp: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + }; + }; + + target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x4000>; + }; + + target-module@75000 { /* 0x4a075000, ap 81 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x75000 0x1000>; + }; + }; + + segment@80000 { /* 0x4a080000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ + <0x0005a000 0x000da000 0x001000>, /* ap 14 */ + <0x0005b000 0x000db000 0x001000>, /* ap 15 */ + <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ + <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ + <0x0005e000 0x000de000 0x001000>, /* ap 18 */ + <0x00060000 0x000e0000 0x001000>, /* ap 19 */ + <0x00061000 0x000e1000 0x001000>, /* ap 20 */ + <0x00074000 0x000f4000 0x001000>, /* ap 25 */ + <0x00075000 0x000f5000 0x001000>, /* ap 26 */ + <0x00076000 0x000f6000 0x001000>, /* ap 27 */ + <0x00077000 0x000f7000 0x001000>, /* ap 28 */ + <0x00036000 0x000b6000 0x001000>, /* ap 65 */ + <0x00037000 0x000b7000 0x001000>, /* ap 66 */ + <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ + <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ + <0x00000000 0x00080000 0x004000>, /* ap 83 */ + <0x00004000 0x00084000 0x001000>, /* ap 84 */ + <0x00005000 0x00085000 0x001000>, /* ap 85 */ + <0x00006000 0x00086000 0x001000>, /* ap 86 */ + <0x00007000 0x00087000 0x001000>, /* ap 87 */ + <0x00008000 0x00088000 0x001000>, /* ap 88 */ + <0x00010000 0x00090000 0x004000>, /* ap 89 */ + <0x00014000 0x00094000 0x001000>, /* ap 90 */ + <0x00015000 0x00095000 0x001000>, /* ap 91 */ + <0x00016000 0x00096000 0x001000>, /* ap 92 */ + <0x00017000 0x00097000 0x001000>, /* ap 93 */ + <0x00018000 0x00098000 0x001000>, /* ap 94 */ + <0x00020000 0x000a0000 0x004000>, /* ap 95 */ + <0x00024000 0x000a4000 0x001000>, /* ap 96 */ + <0x00025000 0x000a5000 0x001000>, /* ap 97 */ + <0x00026000 0x000a6000 0x001000>, /* ap 98 */ + <0x00027000 0x000a7000 0x001000>, /* ap 99 */ + <0x00028000 0x000a8000 0x001000>; /* ap 100 */ + + target-module@0 { /* 0x4a080000, ap 83 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x14 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00004000>, + <0x00004000 0x00004000 0x00001000>, + <0x00005000 0x00005000 0x00001000>, + <0x00006000 0x00006000 0x00001000>, + <0x00007000 0x00007000 0x00001000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x20>; + }; + + usb2_phy: usb2phy@4000 { + compatible = "ti,omap-usb2"; + reg = <0x4000 0x7c>; + syscon-phy-power = <&scm_conf 0x300>; + clocks = <&usb_phy_cm_clk32k>, + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + }; + + usb3_phy: usb3phy@4400 { + compatible = "ti,omap-usb3"; + reg = <0x4400 0x80>, + <0x4800 0x64>, + <0x4c00 0x40>; + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x370>; + clocks = <&usb_phy_cm_clk32k>, + <&sys_clkin>, + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; + clock-names = "wkupclk", + "sysclk", + "refclk"; + #phy-cells = <0>; + }; + }; + + target-module@10000 { /* 0x4a090000, ap 89 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x10000 0x4>, + <0x10010 0x4>, + <0x10014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x00004000>, + <0x00004000 0x00014000 0x00001000>, + <0x00005000 0x00015000 0x00001000>, + <0x00006000 0x00016000 0x00001000>, + <0x00007000 0x00017000 0x00001000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x20>; + }; + + sata_phy: phy@6000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x6000 0x80>, /* phy_rx */ + <0x6400 0x64>, /* phy_tx */ + <0x6800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x374>; + clocks = <&sys_clkin>, + <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; + clock-names = "sysclk", "refclk"; + #phy-cells = <0>; + }; + }; + + target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00020000 0x00004000>, + <0x00004000 0x00024000 0x00001000>, + <0x00005000 0x00025000 0x00001000>, + <0x00006000 0x00026000 0x00001000>, + <0x00007000 0x00027000 0x00001000>; + }; + + target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000 0x1000>; + }; + + target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x74000 0x4>, + <0x74010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + mbox_ipu: mbox-ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox-dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; + }; + }; + + target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x76000 0x4>, + <0x76010 0x4>, + <0x76014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ + <0x00003000 0x00103000 0x001000>, /* ap 60 */ + <0x00008000 0x00108000 0x001000>, /* ap 61 */ + <0x00009000 0x00109000 0x001000>, /* ap 62 */ + <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ + <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ + <0x00040000 0x00140000 0x010000>, /* ap 101 */ + <0x00050000 0x00150000 0x001000>; /* ap 102 */ + + target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 61 26.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@40000 { /* 0x4a140000, ap 101 16.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x400fc 4>, + <0x41100 4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + power-domains = <&prm_l3init>; + clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>; + clock-names = "fck"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + + sata: sata@0 { + compatible = "snps,dwc-ahci"; + reg = <0 0x1100>, <0x1100 0x8>; + interrupts = ; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; + ports-implemented = <0x1>; + }; + }; + }; + + segment@180000 { /* 0x4a180000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ + <0x00006000 0x00206000 0x001000>, /* ap 33 */ + <0x00007000 0x00207000 0x001000>, /* ap 34 */ + <0x00004000 0x00204000 0x001000>, /* ap 35 */ + <0x00005000 0x00205000 0x001000>, /* ap 36 */ + <0x00012000 0x00212000 0x001000>, /* ap 37 */ + <0x00013000 0x00213000 0x001000>, /* ap 38 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ + <0x00010000 0x00210000 0x001000>, /* ap 41 */ + <0x00011000 0x00211000 0x001000>, /* ap 42 */ + <0x00016000 0x00216000 0x001000>, /* ap 43 */ + <0x00017000 0x00217000 0x001000>, /* ap 44 */ + <0x00014000 0x00214000 0x001000>, /* ap 45 */ + <0x00015000 0x00215000 0x001000>, /* ap 46 */ + <0x00018000 0x00218000 0x001000>, /* ap 47 */ + <0x00019000 0x00219000 0x001000>, /* ap 48 */ + <0x00020000 0x00220000 0x001000>, /* ap 49 */ + <0x00021000 0x00221000 0x001000>, /* ap 50 */ + <0x00026000 0x00226000 0x001000>, /* ap 51 */ + <0x00027000 0x00227000 0x001000>, /* ap 52 */ + <0x00028000 0x00228000 0x001000>, /* ap 53 */ + <0x00029000 0x00229000 0x001000>, /* ap 54 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ + <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ + <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ + <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ + <0x00024000 0x00224000 0x001000>, /* ap 75 */ + <0x00025000 0x00225000 0x001000>, /* ap 76 */ + <0x00002000 0x00202000 0x001000>, /* ap 103 */ + <0x00003000 0x00203000 0x001000>, /* ap 104 */ + <0x00008000 0x00208000 0x001000>, /* ap 105 */ + <0x00009000 0x00209000 0x001000>, /* ap 106 */ + <0x00022000 0x00222000 0x001000>, /* ap 107 */ + <0x00023000 0x00223000 0x001000>; /* ap 108 */ + + target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x4a204000, ap 35 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + }; + + target-module@8000 { /* 0x4a208000, ap 105 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 41 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 37 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x4a216000, ap 43 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x4a224000, ap 75 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 51 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x4a228000, ap 53 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + }; + + segment@280000 { /* 0x4a280000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@300000 { /* 0x4a300000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,omap5-l4-per", "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00055000 0x00055000 0x001000>, /* ap 13 */ + <0x00056000 0x00056000 0x001000>, /* ap 14 */ + <0x00057000 0x00057000 0x001000>, /* ap 15 */ + <0x00058000 0x00058000 0x001000>, /* ap 16 */ + <0x00059000 0x00059000 0x001000>, /* ap 17 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ + <0x00060000 0x00060000 0x001000>, /* ap 23 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ + <0x00070000 0x00070000 0x001000>, /* ap 30 */ + <0x00071000 0x00071000 0x001000>, /* ap 31 */ + <0x00072000 0x00072000 0x001000>, /* ap 32 */ + <0x00073000 0x00073000 0x001000>, /* ap 33 */ + <0x00061000 0x00061000 0x001000>, /* ap 34 */ + <0x00053000 0x00053000 0x001000>, /* ap 35 */ + <0x00054000 0x00054000 0x001000>, /* ap 36 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ + <0x00078000 0x00078000 0x001000>, /* ap 39 */ + <0x00079000 0x00079000 0x001000>, /* ap 40 */ + <0x00086000 0x00086000 0x001000>, /* ap 41 */ + <0x00087000 0x00087000 0x001000>, /* ap 42 */ + <0x00088000 0x00088000 0x001000>, /* ap 43 */ + <0x00089000 0x00089000 0x001000>, /* ap 44 */ + <0x00051000 0x00051000 0x001000>, /* ap 45 */ + <0x00052000 0x00052000 0x001000>, /* ap 46 */ + <0x00098000 0x00098000 0x001000>, /* ap 47 */ + <0x00099000 0x00099000 0x001000>, /* ap 48 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ + <0x00068000 0x00068000 0x001000>, /* ap 53 */ + <0x00069000 0x00069000 0x001000>, /* ap 54 */ + <0x00090000 0x00090000 0x002000>, /* ap 55 */ + <0x00092000 0x00092000 0x001000>, /* ap 56 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a5000 0x000a5000 0x001000>, + <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ + <0x00066000 0x00066000 0x001000>, /* ap 63 */ + <0x00067000 0x00067000 0x001000>, /* ap 64 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ + <0x00001400 0x00001400 0x000400>, /* ap 77 */ + <0x00001800 0x00001800 0x000400>, /* ap 78 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ + <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ + <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ + <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ + <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ + <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@32000 { /* 0x48032000, ap 5 3e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@34000 { /* 0x48034000, ap 7 46.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@36000 { /* 0x48036000, ap 9 4e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + }; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@51000 { /* 0x48051000, ap 45 2e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x51000 0x4>, + <0x51010 0x4>, + <0x51114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x51000 0x1000>; + + gpio7: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@53000 { /* 0x48053000, ap 35 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x53000 0x4>, + <0x53010 0x4>, + <0x53114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000 0x1000>; + + gpio8: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@57000 { /* 0x48057000, ap 15 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@59000 { /* 0x48059000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@60000 { /* 0x48060000, ap 23 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@66000 { /* 0x48066000, ap 63 4c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x66050 0x4>, + <0x66054 0x4>, + <0x66058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + uart5: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@68000 { /* 0x48068000, ap 53 54.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x68050 0x4>, + <0x68054 0x4>, + <0x68058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x68000 0x1000>; + + uart6: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@70000 { /* 0x48070000, ap 30 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@72000 { /* 0x48072000, ap 32 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@78000 { /* 0x48078000, ap 39 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + }; + + target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x7a000 0x8>, + <0x7a010 0x8>, + <0x7a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7a000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x7c000 0x8>, + <0x7c010 0x8>, + <0x7c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7c000 0x1000>; + + i2c5: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@86000 { /* 0x48086000, ap 41 5e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x86000 0x4>, + <0x86010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@88000 { /* 0x48088000, ap 43 66.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; + }; + + target-module@98000 { /* 0x48098000, ap 47 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + }; + + target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + }; + + target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + }; + + target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + status = "disabled"; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + }; + + target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, <&sdma 16>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 57>, <&sdma 58>; + dma-names = "tx", "rx"; + }; + }; + + target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xd5000 0x4>, + <0xd5010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + + mmc5: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 59>, <&sdma 60>; + dma-names = "tx", "rx"; + }; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&l4_wkup { /* 0x4ae00000 */ + compatible = "ti,omap5-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkupaon>; + clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; + reg = <0x4ae00000 0x800>, + <0x4ae00800 0x800>, + <0x4ae01000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ + <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ + <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ + + segment@0 { /* 0x4ae00000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ + <0x00004000 0x00004000 0x001000>, /* ap 17 */ + <0x00005000 0x00005000 0x001000>, /* ap 18 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ + + target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x40>; + }; + }; + + target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,omap5-prm", "simple-bus"; + reg = <0x0 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + }; + + target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + scrm: scrm@0 { + compatible = "ti,omap5-scrm"; + reg = <0x0 0x1000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + }; + + target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + omap5_pmx_wkup: pinmux@840 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0x840 0x003c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { + compatible = "ti,omap5-scm-wkup-pad-conf", + "simple-bus"; + reg = <0xda0 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60>; + + scm_wkup_pad_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x60>; + + scm_wkup_pad_conf_clocks: clocks@0 { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + segment@10000 { /* 0x4ae10000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ + + target-module@0 { /* 0x4ae10000, ap 5 10.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, + <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap5-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x8000 0x4>, + <0x8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; + interrupts = ; + ti,timer-alwon; + }; + }; + + target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xc000 0x4>, + <0xc010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + keypad: keypad@0 { + compatible = "ti,omap4-keypad"; + reg = <0x0 0x400>; + }; + }; + }; + + segment@20000 { /* 0x4ae20000 */ + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 21 */ + <0x00001000 0x00021000 0x001000>, /* ap 22 */ + <0x00002000 0x00022000 0x001000>, /* ap 23 */ + <0x00003000 0x00023000 0x001000>, /* ap 24 */ + <0x00007000 0x00027000 0x000400>, /* ap 25 */ + <0x00008000 0x00028000 0x000800>, /* ap 26 */ + <0x00009000 0x00029000 0x000100>, /* ap 27 */ + <0x00008800 0x00028800 0x000200>, /* ap 28 */ + <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ + + target-module@0 { /* 0x4ae20000, ap 21 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00002800 0x00008800 0x00000200>, + <0x00002a00 0x00008a00 0x00000100>, + <0x00003000 0x00009000 0x00000100>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts b/arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts new file mode 100644 index 000000000000..02716fb796bd --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Suppport for CompuLab CM-T54 on SB-T54 baseboard + */ + +#include "omap5-cm-t54.dts" + +/ { + model = "CompuLab CM-T54 on SB-T54"; + compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; +}; + +&omap5_pmx_core { + i2c4_pins: i2c4-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc1_aux_pins: mmc1-aux-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ + OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc1_pins + &mmc1_aux_pins + >; + cd-inverted; + wp-inverted; + cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ + wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-uevm.dts b/arch/arm/boot/dts/ti/omap/omap5-uevm.dts new file mode 100644 index 000000000000..933de05d3ca1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5-uevm.dts @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "omap5-board-common.dtsi" + +/ { + model = "TI OMAP5 uEVM board"; + compatible = "ti,omap5-uevm", "ti,omap5"; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_memory_region: dsp-memory@95000000 { + compatible = "shared-dma-pool"; + reg = <0 0x95000000 0 0x800000>; + reusable; + status = "okay"; + }; + + ipu_memory_region: ipu-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0 0x95800000 0 0x3800000>; + reusable; + status = "okay"; + }; + }; + + aliases { + ethernet = ðernet; + }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "omap5:blue:usr1"; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + evm_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&evm_keys_pins>; + + #address-cells = <7>; + #size-cells = <0>; + + btn1 { + label = "BTN1"; + linux,code = <169>; + gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ + wakeup-source; + autorepeat; + debounce-interval = <50>; + }; + }; + + evm_leds { + compatible = "gpio-leds"; + + led1 { + label = "omap5:red:led"; + gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "omap5:green:led"; + gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led3 { + label = "omap5:blue:led"; + gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + default-state = "off"; + }; + + led4 { + label = "omap5:green:led1"; + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led5 { + label = "omap5:green:led2"; + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "off"; + }; + + led6 { + label = "omap5:green:led3"; + gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led7 { + label = "omap5:green:led4"; + gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "off"; + }; + + led8 { + label = "omap5:green:led5"; + gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; +}; + +&hdmi { + vdda-supply = <&ldo4_reg>; +}; + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + + clock-frequency = <400000>; + + gpio9: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ +}; + +&omap5_pmx_core { + evm_keys_pins: evm-keys-gpio-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ + >; + }; + + i2c5_pins: i2c5-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ + OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ + >; + }; +}; + +&tpd12s015 { + gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ + <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ + <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ +}; + +&twl6040 { + ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ +}; + +&twl6040_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ + >; +}; + +&usbhsehci { + #address-cells = <1>; + #size-cells = <0>; + + hub@2 { + compatible = "usb424,3503"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + ethernet: ethernet@3 { + compatible = "usb424,9730"; + reg = <3>; + }; +}; + +&wlcore { + compatible = "ti,wl1837"; +}; + +&dsp { + status = "okay"; + memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer9>, <&timer11>; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi new file mode 100644 index 000000000000..bac6fa838793 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap5.dtsi @@ -0,0 +1,831 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * + * Based on "omap4.dtsi" + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "ti,omap5"; + interrupt-parent = <&wakeupgen>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + i2c4 = &i2c5; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + mmc3 = &mmc4; + mmc4 = &mmc5; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + rproc0 = &dsp; + rproc1 = &ipu; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1500000 1250000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1500000 1250000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + thermal-zones { + #include "omap4-cpu-thermal.dtsi" + #include "omap5-gpu-thermal.dtsi" + #include "omap5-core-thermal.dtsi" + }; + + timer { + compatible = "arm,armv7-timer"; + /* PPI secure/nonsecure IRQ */ + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + ; + }; + + /* + * Needed early by omap4_sram_init() for barrier, do not move to l3 + * interconnect as simple-pm-bus probes at module_init() time. + */ + ocmcram: sram@40300000 { + compatible = "mmio-sram"; + reg = <0 0x40300000 0 0x20000>; /* 128k */ + }; + + gic: interrupt-controller@48211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x48211000 0 0x1000>, + <0 0x48212000 0 0x2000>, + <0 0x48214000 0 0x2000>, + <0 0x48216000 0 0x2000>; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller@48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x48281000 0 0x1000>; + interrupt-parent = <&gic>; + }; + + /* + * XXX: Use a flat representation of the OMAP3 interconnect. + * The real OMAP interconnect network is quite complex. + * Since it will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>, + <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>, + <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; + + l3-noc@44000000 { + compatible = "ti,omap5-l3-noc"; + reg = <0x44000000 0x2000>, + <0x44800000 0x3000>, + <0x45000000 0x4000>; + interrupts = , + ; + }; + + l4_wkup: interconnect@4ae00000 { + }; + + l4_cfg: interconnect@4a000000 { + }; + + l4_per: interconnect@48000000 { + }; + + target-module@48210000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48210000 0x1f0000>; + + mpu { + compatible = "ti,omap4-mpu"; + sram = <&ocmcram>; + }; + }; + + l4_abe: interconnect@40100000 { + }; + + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + ti,no-idle-on-init; + clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,omap4430-gpmc"; + reg = <0x50000000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = ; + dmas = <&sdma 4>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + ranges = <0x0 0x55082000 0x100>; + #size-cells = <1>; + #address-cells = <1>; + + mmu_ipu: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; + }; + + dsp: dsp { + compatible = "ti,omap5-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + resets = <&prm_dsp 0>; + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; + firmware-name = "omap5-dsp-fw.xe64T"; + mboxes = <&mailbox &mbox_dsp>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap5-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + firmware-name = "omap5-ipu-fw.xem4"; + mboxes = <&mailbox &mbox_ipu>; + status = "disabled"; + }; + + target-module@4e000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4e000000 0x4>, + <0x4e000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + ranges = <0x0 0x4e000000 0x2000000>; + #size-cells = <1>; + #address-cells = <1>; + + dmm@0 { + compatible = "ti,omap5-dmm"; + reg = <0 0x800>; + interrupts = ; + }; + }; + + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif1: emif@0 { + compatible = "ti,emif-4d5"; + reg = <0 0x400>; + interrupts = ; + phy-type = <2>; /* DDR PHY type: Intelli PHY */ + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + }; + + target-module@4d000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4d000000 0x4>; + reg-names = "rev"; + clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000000 0x1000000>; + + emif2: emif@0 { + compatible = "ti,emif-4d5"; + reg = <0 0x400>; + interrupts = ; + phy-type = <2>; /* DDR PHY type: Intelli PHY */ + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + }; + + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; + }; + + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + }; + + bandgap: bandgap@4a0021e0 { + reg = <0x4a0021e0 0xc + 0x4a00232c 0xc + 0x4a002380 0x2c + 0x4a0023C0 0x3c>; + interrupts = ; + compatible = "ti,omap5430-bandgap"; + + #thermal-sensor-cells = <1>; + }; + + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + + target-module@58000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000000 4>, + <0x58000014 4>; + reg-names = "rev", "syss"; + ti,syss-mask = <1>; + power-domains = <&prm_dss>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x58000000 0x1000000>; + + dss: dss@0 { + compatible = "ti,omap5-dss"; + reg = <0 0x80>; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000000>; + + target-module@1000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x1000 0x4>, + <0x1010 0x4>, + <0x1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-midle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x1000>; + + dispc@0 { + compatible = "ti,omap5-dispc"; + reg = <0 0x1000>; + interrupts = ; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + }; + }; + + target-module@2000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2010 0x4>, + <0x2014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + rfbi: encoder@0 { + compatible = "ti,omap5-rfbi"; + reg = <0 0x100>; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; + clock-names = "fck", "ick"; + }; + }; + + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4000 0x1000>; + + dsi1: encoder@0 { + compatible = "ti,omap5-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x40>; + reg-names = "proto", "phy", "pll"; + interrupts = ; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@9000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9000 0x4>, + <0x9010 0x4>, + <0x9014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x9000 0x1000>; + + dsi2: encoder@0 { + compatible = "ti,omap5-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x40>; + reg-names = "proto", "phy", "pll"; + interrupts = ; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@40000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck", "dss_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000 0x40000>; + + hdmi: encoder@0 { + compatible = "ti,omap5-hdmi"; + reg = <0 0x200>, + <0x200 0x80>, + <0x300 0x80>, + <0x20000 0x19000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = ; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + dmas = <&sdma 76>; + dma-names = "audio_tx"; + }; + }; + }; + }; + + abb_mpu: regulator-abb-mpu { + compatible = "ti,abb-v2"; + regulator-name = "abb_mpu"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, + <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; + reg-names = "base-address", "int-address", + "efuse-address", "ldo-address"; + ti,tranxdone-status-mask = <0x80>; + /* LDOVBBMPU_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBMPU_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1060000 0 0x0 0 0x02000000 0x01F00000 + 1250000 0 0x4 0 0x02000000 0x01F00000 + >; + }; + + abb_mm: regulator-abb-mm { + compatible = "ti,abb-v2"; + regulator-name = "abb_mm"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, + <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; + reg-names = "base-address", "int-address", + "efuse-address", "ldo-address"; + ti,tranxdone-status-mask = <0x80000000>; + /* LDOVBBMM_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBMM_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1025000 0 0x0 0 0x02000000 0x01F00000 + 1120000 0 0x4 0 0x02000000 0x01F00000 + >; + }; + }; +}; + +&cpu_thermal { + polling-delay = <500>; /* milliseconds */ + coefficients = <65 (-1791)>; +}; + +#include "omap5-l4.dtsi" +#include "omap54xx-clocks.dtsi" + +&gpu_thermal { + coefficients = <117 (-2992)>; +}; + +&core_thermal { + coefficients = <0 2000>; +}; + +#include "omap5-l4-abe.dtsi" +#include "omap54xx-clocks.dtsi" + +&prm { + prm_mpu: prm@300 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + + prm_dsp: prm@400 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_abe: prm@500 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #power-domain-cells = <0>; + }; + + prm_coreaon: prm@600 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x600 0x100>; + #power-domain-cells = <0>; + }; + + prm_core: prm@700 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x700 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_iva: prm@1200 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_cam: prm@1300 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1300 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1400 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1400 0x100>; + #power-domain-cells = <0>; + }; + + prm_gpu: prm@1500 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1500 0x100>; + #power-domain-cells = <0>; + }; + + prm_l3init: prm@1600 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1600 0x100>; + #power-domain-cells = <0>; + }; + + prm_custefuse: prm@1700 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1700 0x100>; + #power-domain-cells = <0>; + }; + + prm_wkupaon: prm@1800 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1800 0x100>; + #power-domain-cells = <0>; + }; + + prm_emu: prm@1a00 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1a00 0x100>; + #power-domain-cells = <0>; + }; + + prm_device: prm@1c00 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1c00 0x100>; + #reset-cells = <1>; + }; +}; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi new file mode 100644 index 000000000000..5cf3b0e78c15 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi @@ -0,0 +1,1362 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP5 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + */ +&cm_core_aon_clocks { + pad_clks_src_ck: pad_clks_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; + clock-frequency = <12000000>; + }; + + pad_clks_ck: pad_clks_ck@108 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; + clocks = <&pad_clks_src_ck>; + ti,bit-shift = <8>; + reg = <0x0108>; + }; + + secure_32k_clk_src_ck: secure_32k_clk_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; + clock-frequency = <32768>; + }; + + slimbus_src_clk: slimbus_src_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; + clock-frequency = <12000000>; + }; + + slimbus_clk: slimbus_clk@108 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; + clocks = <&slimbus_src_clk>; + ti,bit-shift = <10>; + reg = <0x0108>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; + clock-frequency = <32768>; + }; + + virt_12000000_ck: virt_12000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; + clock-frequency = <12000000>; + }; + + virt_13000000_ck: virt_13000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; + clock-frequency = <13000000>; + }; + + virt_16800000_ck: virt_16800000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; + clock-frequency = <16800000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; + clock-frequency = <26000000>; + }; + + virt_27000000_ck: virt_27000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; + clock-frequency = <27000000>; + }; + + virt_38400000_ck: virt_38400000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; + clock-frequency = <38400000>; + }; + + xclk60mhsp1_ck: xclk60mhsp1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; + clock-frequency = <60000000>; + }; + + xclk60mhsp2_ck: xclk60mhsp2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; + clock-frequency = <60000000>; + }; + + dpll_abe_ck: dpll_abe_ck@1e0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; + clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; + reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; + }; + + dpll_abe_x2_ck: dpll_abe_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; + clocks = <&dpll_abe_ck>; + }; + + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + reg = <0x01f0>; + ti,index-starts-at-one; + }; + + abe_24m_fclk: abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + abe_clk: abe_clk@108 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; + clocks = <&dpll_abe_m2x2_ck>; + ti,max-div = <4>; + reg = <0x0108>; + ti,index-power-of-two; + }; + + abe_iclk: abe_iclk@528 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "abe_iclk"; + clocks = <&aess_fclk>; + ti,bit-shift = <24>; + reg = <0x0528>; + ti,dividers = <2>, <1>; + }; + + abe_lp_clk_div: abe_lp_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "abe_lp_clk_div"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + reg = <0x01f4>; + ti,index-starts-at-one; + }; + + dpll_core_byp_mux: dpll_core_byp_mux@12c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; + clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x012c>; + }; + + dpll_core_ck: dpll_core_ck@120 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; + clocks = <&sys_clkin>, <&dpll_core_byp_mux>; + reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h21x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x0150>; + ti,index-starts-at-one; + }; + + c2c_fclk: c2c_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "c2c_fclk"; + clocks = <&dpll_core_h21x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + c2c_iclk: c2c_iclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "c2c_iclk"; + clocks = <&c2c_fclk>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h11x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x0138>; + ti,index-starts-at-one; + }; + + dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x013c>; + ti,index-starts-at-one; + }; + + dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x0140>; + ti,index-starts-at-one; + }; + + dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x0144>; + ti,index-starts-at-one; + }; + + dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x0154>; + ti,index-starts-at-one; + }; + + dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x0158>; + ti,index-starts-at-one; + }; + + dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + reg = <0x015c>; + ti,index-starts-at-one; + }; + + dpll_core_m2_ck: dpll_core_m2_ck@130 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; + clocks = <&dpll_core_ck>; + ti,max-div = <31>; + reg = <0x0130>; + ti,index-starts-at-one; + }; + + dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m3x2_ck"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0134>; + ti,index-starts-at-one; + }; + + iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; + clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x01ac>; + }; + + dpll_iva_ck: dpll_iva_ck@1a0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; + clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; + reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; + }; + + dpll_iva_x2_ck: dpll_iva_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; + clocks = <&dpll_iva_ck>; + }; + + dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h11x2_ck"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <63>; + reg = <0x01b8>; + ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; + }; + + dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h12x2_ck"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <63>; + reg = <0x01bc>; + ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; + }; + + mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_mpu_ck: dpll_mpu_ck@160 { + #clock-cells = <0>; + compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; + clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; + reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + reg = <0x0170>; + ti,index-starts-at-one; + }; + + per_dpll_hs_clk_div: per_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + l3_iclk_div: l3_iclk_div@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; + ti,max-div = <2>; + ti,bit-shift = <4>; + reg = <0x100>; + clocks = <&dpll_core_h12x2_ck>; + ti,index-power-of-two; + }; + + gpu_l3_iclk: gpu_l3_iclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "gpu_l3_iclk"; + clocks = <&l3_iclk_div>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4_root_clk_div: l4_root_clk_div@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_root_clk_div"; + ti,max-div = <2>; + ti,bit-shift = <8>; + reg = <0x100>; + clocks = <&l3_iclk_div>; + ti,index-power-of-two; + }; + + slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "slimbus1_slimbus_clk"; + clocks = <&slimbus_clk>; + ti,bit-shift = <11>; + reg = <0x0560>; + }; + + aess_fclk: aess_fclk@528 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; + clocks = <&abe_clk>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x0528>; + }; + + mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "mcasp_sync_mux_ck"; + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; + ti,bit-shift = <26>; + reg = <0x0540>; + }; + + mcasp_gfclk: mcasp_gfclk@540 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "mcasp_gfclk"; + clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0540>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; + clock-frequency = <0>; + }; +}; +&prm_clocks { + sys_clkin: sys_clkin@110 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin"; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; + }; + + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + reg = <0x0108>; + }; + + abe_dpll_clk_mux: abe_dpll_clk_mux@10c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + reg = <0x010c>; + }; + + custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; + clocks = <&sys_clkin>; + clock-mult = <1>; + clock-div = <2>; + }; + + dss_syc_gfclk_div: dss_syc_gfclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dss_syc_gfclk_div"; + clocks = <&sys_clkin>; + clock-mult = <1>; + clock-div = <1>; + }; + + wkupaon_iclk_mux: wkupaon_iclk_mux@108 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; + clocks = <&sys_clkin>, <&abe_lp_clk_div>; + reg = <0x0108>; + }; + + l3instr_ts_gclk_div: l3instr_ts_gclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "l3instr_ts_gclk_div"; + clocks = <&wkupaon_iclk_mux>; + clock-mult = <1>; + clock-div = <1>; + }; +}; + +&cm_core_clocks { + + dpll_per_byp_mux: dpll_per_byp_mux@14c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; + clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x014c>; + }; + + dpll_per_ck: dpll_per_ck@140 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; + clocks = <&sys_clkin>, <&dpll_per_byp_mux>; + reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; + }; + + dpll_per_x2_ck: dpll_per_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; + clocks = <&dpll_per_ck>; + }; + + dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + reg = <0x0158>; + ti,index-starts-at-one; + }; + + dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + reg = <0x015c>; + ti,index-starts-at-one; + }; + + dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + reg = <0x0164>; + ti,index-starts-at-one; + }; + + dpll_per_m2_ck: dpll_per_m2_ck@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + reg = <0x0150>; + ti,index-starts-at-one; + }; + + dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + reg = <0x0150>; + ti,index-starts-at-one; + }; + + dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m3x2_ck"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + reg = <0x0154>; + ti,index-starts-at-one; + }; + + dpll_unipro1_ck: dpll_unipro1_ck@200 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro1_ck"; + clocks = <&sys_clkin>, <&sys_clkin>; + reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + }; + + dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro1_clkdcoldo"; + clocks = <&dpll_unipro1_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro1_m2_ck"; + clocks = <&dpll_unipro1_ck>; + ti,max-div = <127>; + reg = <0x0210>; + ti,index-starts-at-one; + }; + + dpll_unipro2_ck: dpll_unipro2_ck@1c0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro2_ck"; + clocks = <&sys_clkin>, <&sys_clkin>; + reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; + }; + + dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro2_clkdcoldo"; + clocks = <&dpll_unipro2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro2_m2_ck"; + clocks = <&dpll_unipro2_ck>; + ti,max-div = <127>; + reg = <0x01d0>; + ti,index-starts-at-one; + }; + + dpll_usb_byp_mux: dpll_usb_byp_mux@18c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; + clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; + ti,bit-shift = <23>; + reg = <0x018c>; + }; + + dpll_usb_ck: dpll_usb_ck@180 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; + clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; + reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; + }; + + dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; + clocks = <&dpll_usb_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_usb_m2_ck: dpll_usb_m2_ck@190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + reg = <0x0190>; + ti,index-starts-at-one; + }; + + func_128m_clk: func_128m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; + clocks = <&dpll_per_h11x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + func_12m_fclk: func_12m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + func_24m_clk: func_24m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_48m_fclk: func_48m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_96m_fclk: func_96m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + l3init_60m_fclk: l3init_60m_fclk@104 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x0104>; + ti,dividers = <1>, <8>; + }; + + iss_ctrlclk: iss_ctrlclk@1320 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "iss_ctrlclk"; + clocks = <&func_96m_fclk>; + ti,bit-shift = <8>; + reg = <0x1320>; + }; + + lli_txphy_clk: lli_txphy_clk@f20 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_clk"; + clocks = <&dpll_unipro1_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x0f20>; + }; + + lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_ls_clk"; + clocks = <&dpll_unipro1_m2_ck>; + ti,bit-shift = <9>; + reg = <0x0f20>; + }; + + usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0640>; + }; + + fdif_fclk: fdif_fclk@1328 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "fdif_fclk"; + clocks = <&dpll_per_h11x2_ck>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x1328>; + }; + + gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; + ti,bit-shift = <24>; + reg = <0x1520>; + }; + + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; + ti,bit-shift = <25>; + reg = <0x1520>; + }; + + hsi_fclk: hsi_fclk@1638 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "hsi_fclk"; + clocks = <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x1638>; + }; +}; + +&cm_core_clockdomains { + l3init_clkdm: l3init_clkdm { + compatible = "ti,clockdomain"; + clock-output-names = "l3init_clkdm"; + clocks = <&dpll_usb_ck>; + }; +}; + +&scrm_clocks { + auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0310>; + }; + + auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0310>; + }; + + auxclk0_src_ck: auxclk0_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; + clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; + }; + + auxclk0_ck: auxclk0_ck@310 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; + clocks = <&auxclk0_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0310>; + }; + + auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0314>; + }; + + auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0314>; + }; + + auxclk1_src_ck: auxclk1_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; + clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; + }; + + auxclk1_ck: auxclk1_ck@314 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; + clocks = <&auxclk1_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0314>; + }; + + auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0318>; + }; + + auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0318>; + }; + + auxclk2_src_ck: auxclk2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; + clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; + }; + + auxclk2_ck: auxclk2_ck@318 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; + clocks = <&auxclk2_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0318>; + }; + + auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x031c>; + }; + + auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x031c>; + }; + + auxclk3_src_ck: auxclk3_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; + clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; + }; + + auxclk3_ck: auxclk3_ck@31c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; + clocks = <&auxclk3_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x031c>; + }; + + auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0320>; + }; + + auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0320>; + }; + + auxclk4_src_ck: auxclk4_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; + clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; + }; + + auxclk4_ck: auxclk4_ck@320 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; + clocks = <&auxclk4_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0320>; + }; + + auxclkreq0_ck: auxclkreq0_ck@210 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x0210>; + }; + + auxclkreq1_ck: auxclkreq1_ck@214 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x0214>; + }; + + auxclkreq2_ck: auxclkreq2_ck@218 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x0218>; + }; + + auxclkreq3_ck: auxclkreq3_ck@21c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x021c>; + }; +}; + +&cm_core_aon { + mpu_cm: mpu_cm@300 { + compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; + reg = <0x300 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300 0x100>; + + mpu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + dsp_cm: dsp_cm@400 { + compatible = "ti,omap4-cm"; + clock-output-names = "dsp_cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + dsp_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dsp_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + abe_cm: abe_cm@500 { + compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; + reg = <0x500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x500 0x100>; + + abe_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; + reg = <0x20 0x64>; + #clock-cells = <2>; + }; + }; + +}; + +&cm_core { + l3main1_cm: l3main1_cm@700 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; + reg = <0x700 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x700 0x100>; + + l3main1_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3main2_cm: l3main2_cm@800 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3main2_cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l3main2_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3main2_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + ipu_cm: ipu_cm@900 { + compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + ipu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + dma_cm: dma_cm@a00 { + compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + dma_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + emif_cm: emif_cm@b00 { + compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb00 0x100>; + + emif_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; + reg = <0x20 0x1c>; + #clock-cells = <2>; + }; + }; + + l4cfg_cm: l4cfg_cm@d00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; + reg = <0xd00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd00 0x100>; + + l4cfg_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; + reg = <0x20 0x14>; + #clock-cells = <2>; + }; + }; + + l3instr_cm: l3instr_cm@e00 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; + reg = <0xe00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe00 0x100>; + + l3instr_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + + l4per_cm: clock@1000 { + compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; + reg = <0x1000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x200>; + + l4per_clkctrl: clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; + reg = <0x20 0x15c>; + #clock-cells = <2>; + }; + + l4sec_clkctrl: clock@1a0 { + compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; + reg = <0x1a0 0x3c>; + #clock-cells = <2>; + }; + }; + + dss_cm: dss_cm@1400 { + compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; + reg = <0x1400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1400 0x100>; + + dss_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + gpu_cm: gpu_cm@1500 { + compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; + reg = <0x1500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1500 0x100>; + + gpu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + + l3init_cm: l3init_cm@1600 { + compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; + reg = <0x1600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1600 0x100>; + + l3init_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; + reg = <0x20 0xd4>; + #clock-cells = <2>; + }; + }; +}; + +&prm { + wkupaon_cm: wkupaon_cm@1900 { + compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; + reg = <0x1900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1900 0x100>; + + wkupaon_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; + reg = <0x20 0x5c>; + #clock-cells = <2>; + }; + }; +}; + +&scm_wkup_pad_conf_clocks { + fref_xtal_ck: fref_xtal_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "fref_xtal_ck"; + clocks = <&sys_clkin>; + ti,bit-shift = <28>; + reg = <0x14>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/twl4030.dtsi b/arch/arm/boot/dts/ti/omap/twl4030.dtsi new file mode 100644 index 000000000000..93e07c18781b --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/twl4030.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* + * Integrated Power Management Chip + */ +&twl { + compatible = "ti,twl4030"; + interrupt-controller; + #interrupt-cells = <1>; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + charger: bci { + compatible = "ti,twl4030-bci"; + interrupts = <9>, <2>; + bci3v1-supply = <&vusb3v1>; + io-channels = <&twl_madc 11>; + io-channel-names = "vac"; + }; + + watchdog { + compatible = "ti,twl4030-wdt"; + }; + + vaux1: regulator-vaux1 { + compatible = "ti,twl4030-vaux1"; + }; + + vaux2: regulator-vaux2 { + compatible = "ti,twl4030-vaux2"; + }; + + vaux3: regulator-vaux3 { + compatible = "ti,twl4030-vaux3"; + }; + + vaux4: regulator-vaux4 { + compatible = "ti,twl4030-vaux4"; + }; + + vcc: regulator-vdd1 { + compatible = "ti,twl4030-vdd1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1450000>; + }; + + vdac: regulator-vdac { + compatible = "ti,twl4030-vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vio: regulator-vio { + compatible = "ti,twl4030-vio"; + }; + + vintana1: regulator-vintana1 { + compatible = "ti,twl4030-vintana1"; + }; + + vintana2: regulator-vintana2 { + compatible = "ti,twl4030-vintana2"; + }; + + vintdig: regulator-vintdig { + compatible = "ti,twl4030-vintdig"; + }; + + vmmc1: regulator-vmmc1 { + compatible = "ti,twl4030-vmmc1"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; + }; + + vmmc2: regulator-vmmc2 { + compatible = "ti,twl4030-vmmc2"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; + }; + + vusb1v5: regulator-vusb1v5 { + compatible = "ti,twl4030-vusb1v5"; + }; + + vusb1v8: regulator-vusb1v8 { + compatible = "ti,twl4030-vusb1v8"; + }; + + vusb3v1: regulator-vusb3v1 { + compatible = "ti,twl4030-vusb3v1"; + }; + + vpll1: regulator-vpll1 { + compatible = "ti,twl4030-vpll1"; + }; + + vpll2: regulator-vpll2 { + compatible = "ti,twl4030-vpll2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vsim: regulator-vsim { + compatible = "ti,twl4030-vsim"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + twl_gpio: gpio { + compatible = "ti,twl4030-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + usb2_phy: twl4030-usb { + compatible = "ti,twl4030-usb"; + interrupts = <10>, <4>; + usb1v5-supply = <&vusb1v5>; + usb1v8-supply = <&vusb1v8>; + usb3v1-supply = <&vusb3v1>; + usb_mode = <1>; + #phy-cells = <0>; + }; + + twl_pwm: pwm { + compatible = "ti,twl4030-pwm"; + #pwm-cells = <2>; + }; + + twl_pwmled: pwmled { + compatible = "ti,twl4030-pwmled"; + #pwm-cells = <2>; + }; + + twl_pwrbutton: pwrbutton { + compatible = "ti,twl4030-pwrbutton"; + interrupts = <8>; + }; + + twl_keypad: keypad { + compatible = "ti,twl4030-keypad"; + interrupts = <1>; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + }; + + twl_madc: madc { + compatible = "ti,twl4030-madc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi b/arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi new file mode 100644 index 000000000000..89433f251df0 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Linaro, Ltd. + */ + +&twl { + pinctrl-names = "default"; + pinctrl-0 = <&twl4030_pins &twl4030_vpins>; +}; + +&omap3_pmx_core { + /* + * On most OMAP3 platforms, the twl4030 IRQ line is connected + * to the SYS_NIRQ line on OMAP. Therefore, configure the + * defaults for the SYS_NIRQ pin here. + */ + twl4030_pins: twl4030-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ + >; + }; +}; + +/* + * If your board is not using the I2C4 pins with twl4030, then don't include + * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode + * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and + * sys_nvmode2 signaling. + */ +&omap3_pmx_wkup { + twl4030_vpins: twl4030-vpins-pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ + OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ + OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ + OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ + >; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/twl6030.dtsi b/arch/arm/boot/dts/ti/omap/twl6030.dtsi new file mode 100644 index 000000000000..9d588cfaa5cb --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/twl6030.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/twl6030.pdf + */ +&twl { + compatible = "ti,twl6030"; + interrupt-controller; + #interrupt-cells = <1>; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + vaux1: regulator-vaux1 { + compatible = "ti,twl6030-vaux1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + vaux2: regulator-vaux2 { + compatible = "ti,twl6030-vaux2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + }; + + vaux3: regulator-vaux3 { + compatible = "ti,twl6030-vaux3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + vmmc: regulator-vmmc { + compatible = "ti,twl6030-vmmc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + }; + + vpp: regulator-vpp { + compatible = "ti,twl6030-vpp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + }; + + vusim: regulator-vusim { + compatible = "ti,twl6030-vusim"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2900000>; + }; + + vdac: regulator-vdac { + compatible = "ti,twl6030-vdac"; + }; + + vana: regulator-vana { + compatible = "ti,twl6030-vana"; + }; + + vcxio: regulator-vcxio { + compatible = "ti,twl6030-vcxio"; + regulator-always-on; + }; + + vusb: regulator-vusb { + compatible = "ti,twl6030-vusb"; + }; + + v1v8: regulator-v1v8 { + compatible = "ti,twl6030-v1v8"; + regulator-always-on; + }; + + v2v1: regulator-v2v1 { + compatible = "ti,twl6030-v2v1"; + regulator-always-on; + }; + + twl_usb_comparator: usb-comparator { + compatible = "ti,twl6030-usb"; + interrupts = <4>, <10>; + }; + + twl_pwm: pwm { + /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + twl_pwmled: pwmled { + /* provides one PWM (id 0 for Charging indicator LED) */ + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; + + gpadc { + compatible = "ti,twl6030-gpadc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi b/arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi new file mode 100644 index 000000000000..64e38c7c8be7 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&twl { + /* + * On most OMAP4 platforms, the twl6030 IRQ line is connected + * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is + * connected to the fref_clk0_out.sys_drm_msecure line. + * Therefore, configure the defaults for the SYS_NIRQ1 and + * fref_clk0_out.sys_drm_msecure pins here. + */ + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_pins + &twl6030_wkup_pins + >; +}; + +&omap4_pmx_wkup { + twl6030_wkup_pins: twl6030-wkup-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ + >; + }; +}; + +&omap4_pmx_core { + twl6030_pins: twl6030-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts deleted file mode 100644 index ef6d586ce887..000000000000 --- a/arch/arm/boot/dts/tny_a9260.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include "tny_a9260_common.dtsi" - -/ { - model = "Calao TNY A9260"; - compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9"; -}; diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi deleted file mode 100644 index 70e5635c78ed..000000000000 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts deleted file mode 100644 index 62b7d9f9a926..000000000000 --- a/arch/arm/boot/dts/tny_a9263.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Calao TNY A9263"; - compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - ebi0: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts deleted file mode 100644 index 118d766a1265..000000000000 --- a/arch/arm/boot/dts/tny_a9g20.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g20.dtsi" -#include "tny_a9260_common.dtsi" - -/ { - model = "Calao TNY A9G20"; - compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; -}; diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi deleted file mode 100644 index 93e07c18781b..000000000000 --- a/arch/arm/boot/dts/twl4030.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - */ -&twl { - compatible = "ti,twl4030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - charger: bci { - compatible = "ti,twl4030-bci"; - interrupts = <9>, <2>; - bci3v1-supply = <&vusb3v1>; - io-channels = <&twl_madc 11>; - io-channel-names = "vac"; - }; - - watchdog { - compatible = "ti,twl4030-wdt"; - }; - - vaux1: regulator-vaux1 { - compatible = "ti,twl4030-vaux1"; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl4030-vaux3"; - }; - - vaux4: regulator-vaux4 { - compatible = "ti,twl4030-vaux4"; - }; - - vcc: regulator-vdd1 { - compatible = "ti,twl4030-vdd1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1450000>; - }; - - vdac: regulator-vdac { - compatible = "ti,twl4030-vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vio: regulator-vio { - compatible = "ti,twl4030-vio"; - }; - - vintana1: regulator-vintana1 { - compatible = "ti,twl4030-vintana1"; - }; - - vintana2: regulator-vintana2 { - compatible = "ti,twl4030-vintana2"; - }; - - vintdig: regulator-vintdig { - compatible = "ti,twl4030-vintdig"; - }; - - vmmc1: regulator-vmmc1 { - compatible = "ti,twl4030-vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; - - vmmc2: regulator-vmmc2 { - compatible = "ti,twl4030-vmmc2"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; - - vusb1v5: regulator-vusb1v5 { - compatible = "ti,twl4030-vusb1v5"; - }; - - vusb1v8: regulator-vusb1v8 { - compatible = "ti,twl4030-vusb1v8"; - }; - - vusb3v1: regulator-vusb3v1 { - compatible = "ti,twl4030-vusb3v1"; - }; - - vpll1: regulator-vpll1 { - compatible = "ti,twl4030-vpll1"; - }; - - vpll2: regulator-vpll2 { - compatible = "ti,twl4030-vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vsim: regulator-vsim { - compatible = "ti,twl4030-vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - twl_gpio: gpio { - compatible = "ti,twl4030-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - usb2_phy: twl4030-usb { - compatible = "ti,twl4030-usb"; - interrupts = <10>, <4>; - usb1v5-supply = <&vusb1v5>; - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; - #phy-cells = <0>; - }; - - twl_pwm: pwm { - compatible = "ti,twl4030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - compatible = "ti,twl4030-pwmled"; - #pwm-cells = <2>; - }; - - twl_pwrbutton: pwrbutton { - compatible = "ti,twl4030-pwrbutton"; - interrupts = <8>; - }; - - twl_keypad: keypad { - compatible = "ti,twl4030-keypad"; - interrupts = <1>; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - }; - - twl_madc: madc { - compatible = "ti,twl4030-madc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi deleted file mode 100644 index 89433f251df0..000000000000 --- a/arch/arm/boot/dts/twl4030_omap3.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Linaro, Ltd. - */ - -&twl { - pinctrl-names = "default"; - pinctrl-0 = <&twl4030_pins &twl4030_vpins>; -}; - -&omap3_pmx_core { - /* - * On most OMAP3 platforms, the twl4030 IRQ line is connected - * to the SYS_NIRQ line on OMAP. Therefore, configure the - * defaults for the SYS_NIRQ pin here. - */ - twl4030_pins: twl4030-pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; -}; - -/* - * If your board is not using the I2C4 pins with twl4030, then don't include - * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode - * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and - * sys_nvmode2 signaling. - */ -&omap3_pmx_wkup { - twl4030_vpins: twl4030-vpins-pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ - OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ - OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ - OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ - >; - }; -}; diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi deleted file mode 100644 index 9d588cfaa5cb..000000000000 --- a/arch/arm/boot/dts/twl6030.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf - */ -&twl { - compatible = "ti,twl6030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - vaux1: regulator-vaux1 { - compatible = "ti,twl6030-vaux1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl6030-vaux2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl6030-vaux3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vmmc: regulator-vmmc { - compatible = "ti,twl6030-vmmc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - }; - - vpp: regulator-vpp { - compatible = "ti,twl6030-vpp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - }; - - vusim: regulator-vusim { - compatible = "ti,twl6030-vusim"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2900000>; - }; - - vdac: regulator-vdac { - compatible = "ti,twl6030-vdac"; - }; - - vana: regulator-vana { - compatible = "ti,twl6030-vana"; - }; - - vcxio: regulator-vcxio { - compatible = "ti,twl6030-vcxio"; - regulator-always-on; - }; - - vusb: regulator-vusb { - compatible = "ti,twl6030-vusb"; - }; - - v1v8: regulator-v1v8 { - compatible = "ti,twl6030-v1v8"; - regulator-always-on; - }; - - v2v1: regulator-v2v1 { - compatible = "ti,twl6030-v2v1"; - regulator-always-on; - }; - - twl_usb_comparator: usb-comparator { - compatible = "ti,twl6030-usb"; - interrupts = <4>, <10>; - }; - - twl_pwm: pwm { - /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - /* provides one PWM (id 0 for Charging indicator LED) */ - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; - }; - - gpadc { - compatible = "ti,twl6030-gpadc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi deleted file mode 100644 index 64e38c7c8be7..000000000000 --- a/arch/arm/boot/dts/twl6030_omap4.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&twl { - /* - * On most OMAP4 platforms, the twl6030 IRQ line is connected - * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is - * connected to the fref_clk0_out.sys_drm_msecure line. - * Therefore, configure the defaults for the SYS_NIRQ1 and - * fref_clk0_out.sys_drm_msecure pins here. - */ - pinctrl-names = "default"; - pinctrl-0 = < - &twl6030_pins - &twl6030_wkup_pins - >; -}; - -&omap4_pmx_wkup { - twl6030_wkup_pins: twl6030-wkup-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ - >; - }; -}; - -&omap4_pmx_core { - twl6030_pins: twl6030-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts deleted file mode 100644 index e007db084787..000000000000 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD4 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld4.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD4 Reference Board"; - compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serialsc; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -ðsc { - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; -}; - -&serialsc { - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio { - xirq1-hog { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi deleted file mode 100644 index df2de7a40211..000000000000 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD4 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-ld4"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = , - ; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <136>; - socionext,interrupt-ranges = <0 48 13>, <14 62 2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - syscon@59810000 { - compatible = "socionext,uniphier-ld4-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock-controller { - compatible = "socionext,uniphier-ld4-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset-controller { - compatible = "socionext,uniphier-ld4-mio-reset"; - #reset-cells = <1>; - }; - }; - - syscon@59820000 { - compatible = "socionext,uniphier-ld4-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock-controller { - compatible = "socionext,uniphier-ld4-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset-controller { - compatible = "socionext,uniphier-ld4-peri-reset"; - #reset-cells = <1>; - }; - }; - - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = , - , - , - , - , - , - ; - clocks = <&mio_clk 7>; - resets = <&mio_rst 7>; - #dma-cells = <1>; - }; - - sd: mmc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = ; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - emmc: mmc@5a500000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge", "hw"; - resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; - dma-names = "rx-tx"; - dmas = <&dmac 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - has-transaction-translator; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - has-transaction-translator; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, - <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - has-transaction-translator; - }; - - syscon@5f800000 { - compatible = "socionext,uniphier-ld4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; - }; - }; - - syscon@5f900000 { - compatible = "socionext,uniphier-ld4-soc-glue-debug", - "simple-mfd", "syscon"; - reg = <0x5f900000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@130 { - compatible = "socionext,uniphier-efuse"; - reg = <0x130 0x8>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - aidet: interrupt-controller@61830000 { - compatible = "socionext,uniphier-ld4-aidet"; - reg = <0x61830000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - syscon@61840000 { - compatible = "socionext,uniphier-ld4-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock-controller { - compatible = "socionext,uniphier-ld4-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset-controller { - compatible = "socionext,uniphier-ld4-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts deleted file mode 100644 index 223a78b4a761..000000000000 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD6b Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld6b.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD6b Reference Board"; - compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serialsc; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -ðsc { - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; -}; - -&serialsc { - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&gpio { - xirq4-hog { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi deleted file mode 100644 index 4d07a94c6b34..000000000000 --- a/arch/arm/boot/dts/uniphier-ld6b.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD6b SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/* - * LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the PXs2 die. - * Reuse the PXs2 device tree with some properties overridden. - */ -#include "uniphier-pxs2.dtsi" - -/ { - compatible = "socionext,uniphier-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * LD6b and PXs2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,uniphier-ld6b-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi deleted file mode 100644 index f909ec2e5333..000000000000 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier SoCs default pinctrl settings -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada - -&pinctrl { - pinctrl_aout: aout { - groups = "aout"; - function = "aout"; - }; - - pinctrl_ain1: ain1 { - groups = "ain1"; - function = "ain1"; - }; - - pinctrl_ain2: ain2 { - groups = "ain2"; - function = "ain2"; - }; - - pinctrl_ainiec1: ainiec1 { - groups = "ainiec1"; - function = "ainiec1"; - }; - - pinctrl_aout1: aout1 { - groups = "aout1"; - function = "aout1"; - }; - - pinctrl_aout2: aout2 { - groups = "aout2"; - function = "aout2"; - }; - - pinctrl_aout3: aout3 { - groups = "aout3"; - function = "aout3"; - }; - - pinctrl_aoutiec1: aoutiec1 { - groups = "aoutiec1"; - function = "aoutiec1"; - }; - - pinctrl_aoutiec2: aoutiec2 { - groups = "aoutiec2"; - function = "aoutiec2"; - }; - - pinctrl_emmc: emmc { - groups = "emmc", "emmc_dat8"; - function = "emmc"; - }; - - pinctrl_ether_mii: ether-mii { - groups = "ether_mii"; - function = "ether_mii"; - }; - - pinctrl_ether_rgmii: ether-rgmii { - groups = "ether_rgmii"; - function = "ether_rgmii"; - }; - - pinctrl_ether_rmii: ether-rmii { - groups = "ether_rmii"; - function = "ether_rmii"; - }; - - pinctrl_ether1_rgmii: ether1-rgmii { - groups = "ether1_rgmii"; - function = "ether1_rgmii"; - }; - - pinctrl_ether1_rmii: ether1-rmii { - groups = "ether1_rmii"; - function = "ether1_rmii"; - }; - - pinctrl_i2c0: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - pinctrl_i2c1: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - pinctrl_i2c2: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - pinctrl_i2c3: i2c3 { - groups = "i2c3"; - function = "i2c3"; - }; - - pinctrl_i2c4: i2c4 { - groups = "i2c4"; - function = "i2c4"; - }; - - pinctrl_i2c5: i2c5 { - groups = "i2c5"; - function = "i2c5"; - }; - - pinctrl_i2c6: i2c6 { - groups = "i2c6"; - function = "i2c6"; - }; - - pinctrl_nand: nand { - groups = "nand"; - function = "nand"; - }; - - pinctrl_nand2cs: nand2cs { - groups = "nand", "nand_cs1"; - function = "nand"; - }; - - pinctrl_pcie: pcie { - groups = "pcie"; - function = "pcie"; - }; - - pinctrl_sd: sd { - groups = "sd"; - function = "sd"; - }; - - pinctrl_sd_uhs: sd-uhs { - groups = "sd"; - function = "sd"; - }; - - pinctrl_sd1: sd1 { - groups = "sd1"; - function = "sd1"; - }; - - pinctrl_spi0: spi0 { - groups = "spi0"; - function = "spi0"; - }; - - pinctrl_spi1: spi1 { - groups = "spi1"; - function = "spi1"; - }; - - pinctrl_spi2: spi2 { - groups = "spi2"; - function = "spi2"; - }; - - pinctrl_spi3: spi3 { - groups = "spi3"; - function = "spi3"; - }; - - pinctrl_system_bus: system-bus { - groups = "system_bus", "system_bus_cs1"; - function = "system_bus"; - }; - - pinctrl_uart0: uart0 { - groups = "uart0"; - function = "uart0"; - }; - - pinctrl_uart1: uart1 { - groups = "uart1"; - function = "uart1"; - }; - - pinctrl_uart2: uart2 { - groups = "uart2"; - function = "uart2"; - }; - - pinctrl_uart3: uart3 { - groups = "uart3"; - function = "uart3"; - }; - - pinctrl_usb0: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - pinctrl_usb0_device: usb0-device { - groups = "usb0_device"; - function = "usb0"; - }; - - pinctrl_usb1: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - pinctrl_usb1_device: usb1-device { - groups = "usb1_device"; - function = "usb1"; - }; - - pinctrl_usb2: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - pinctrl_usb3: usb3 { - groups = "usb3"; - function = "usb3"; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts deleted file mode 100644 index 6baee4410d9c..000000000000 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 Ace Board -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pro4.dtsi" - -/ { - model = "UniPhier Pro4 Ace Board"; - compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&ahci0 { - status = "okay"; -}; - -&ahci1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts deleted file mode 100644 index d2ce5c039865..000000000000 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pro4.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier Pro4 Reference Board"; - compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serialsc; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -ðsc { - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; -}; - -&serialsc { - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&gpio { - xirq2-hog { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; - -&ahci0 { - status = "okay"; -}; - -&ahci1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts deleted file mode 100644 index 7b6faf2e795e..000000000000 --- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 Sanji Board -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pro4.dtsi" - -/ { - model = "UniPhier Pro4 Sanji Board"; - compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi deleted file mode 100644 index ba55af30e904..000000000000 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ /dev/null @@ -1,734 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-pro4"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = , - ; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl: syscon@59810000 { - compatible = "socionext,uniphier-pro4-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock-controller { - compatible = "socionext,uniphier-pro4-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset-controller { - compatible = "socionext,uniphier-pro4-mio-reset"; - #reset-cells = <1>; - }; - }; - - syscon@59820000 { - compatible = "socionext,uniphier-pro4-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock-controller { - compatible = "socionext,uniphier-pro4-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset-controller { - compatible = "socionext,uniphier-pro4-peri-reset"; - #reset-cells = <1>; - }; - }; - - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mio_clk 7>; - resets = <&mio_rst 7>; - #dma-cells = <1>; - }; - - sd: mmc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = ; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - socionext,syscon-uhs-mode = <&mioctrl 0>; - }; - - emmc: mmc@5a500000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge", "hw"; - resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; - dma-names = "rx-tx"; - dmas = <&dmac 5>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - sd1: mmc@5a600000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a600000 0x200>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clocks = <&mio_clk 2>; - reset-names = "host", "bridge"; - resets = <&mio_rst 2>, <&mio_rst 5>; - dma-names = "rx-tx"; - dmas = <&dmac 6>; - bus-width = <4>; - cap-sd-highspeed; - }; - - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - phy-names = "usb"; - phys = <&usb_phy0>; - has-transaction-translator; - }; - - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - phy-names = "usb"; - phys = <&usb_phy1>; - has-transaction-translator; - }; - - soc_glue: syscon@5f800000 { - compatible = "socionext,uniphier-pro4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; - }; - - usb-hub { - compatible = "socionext,uniphier-pro4-usb2-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usb_phy0: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - usb_phy1: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - - usb_phy2: phy@2 { - reg = <2>; - #phy-cells = <0>; - vbus-supply = <&usb0_vbus>; - }; - - usb_phy3: phy@3 { - reg = <3>; - #phy-cells = <0>; - vbus-supply = <&usb1_vbus>; - }; - }; - - sg_clk: clock-controller { - compatible = "socionext,uniphier-pro4-sg-clock"; - #clock-cells = <1>; - }; - }; - - syscon@5f900000 { - compatible = "socionext,uniphier-pro4-soc-glue-debug", - "simple-mfd", "syscon"; - reg = <0x5f900000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@130 { - compatible = "socionext,uniphier-efuse"; - reg = <0x130 0x8>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x14>; - }; - }; - - xdmac: dma-controller@5fc10000 { - compatible = "socionext,uniphier-xdmac"; - reg = <0x5fc10000 0x5300>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <2>; - }; - - aidet: interrupt-controller@5fc20000 { - compatible = "socionext,uniphier-pro4-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - syscon@61840000 { - compatible = "socionext,uniphier-pro4-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock-controller { - compatible = "socionext,uniphier-pro4-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset-controller { - compatible = "socionext,uniphier-pro4-reset"; - #reset-cells = <1>; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-pro4-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "gio", "ether", "ether-gb", "ether-phy"; - clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, - <&sys_clk 10>; - reset-names = "gio", "ether"; - resets = <&sys_rst 12>, <&sys_rst 6>; - phy-mode = "rgmii"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ahci0: sata@65600000 { - compatible = "socionext,uniphier-pro4-ahci", - "generic-ahci"; - status = "disabled"; - reg = <0x65600000 0x10000>; - interrupts = ; - clocks = <&sys_clk 12>, <&sys_clk 28>; - resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>; - ports-implemented = <1>; - phys = <&ahci0_phy>; - assigned-clocks = <&sg_clk 0>; - assigned-clock-rates = <25000000>; - }; - - sata-controller@65700000 { - compatible = "socionext,uniphier-pxs2-ahci-glue", - "simple-mfd"; - reg = <0x65700000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65700000 0x100>; - - ahci0_rst: reset-controller@0 { - compatible = "socionext,uniphier-pro4-ahci-reset"; - reg = <0x0 0x4>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 28>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 28>; - #reset-cells = <1>; - }; - - ahci0_phy: phy@10 { - compatible = "socionext,uniphier-pro4-ahci-phy"; - reg = <0x10 0x40>; - clock-names = "link", "gio"; - clocks = <&sys_clk 28>, <&sys_clk 12>; - reset-names = "link", "gio", "phy", - "pm", "tx", "rx"; - resets = <&sys_rst 28>, <&sys_rst 12>, - <&sys_rst 30>, - <&ahci0_rst 0>, <&ahci0_rst 1>, - <&ahci0_rst 2>; - #phy-cells = <0>; - }; - }; - - ahci1: sata@65800000 { - compatible = "socionext,uniphier-pro4-ahci", - "generic-ahci"; - status = "disabled"; - reg = <0x65800000 0x10000>; - interrupts = ; - clocks = <&sys_clk 12>, <&sys_clk 29>; - resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>; - ports-implemented = <1>; - phys = <&ahci1_phy>; - assigned-clocks = <&sg_clk 0>; - assigned-clock-rates = <25000000>; - }; - - sata-controller@65900000 { - compatible = "socionext,uniphier-pro4-ahci-glue", - "simple-mfd"; - reg = <0x65900000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65900000 0x100>; - - ahci1_rst: reset-controller@0 { - compatible = "socionext,uniphier-pro4-ahci-reset"; - reg = <0x0 0x4>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 29>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 29>; - #reset-cells = <1>; - }; - - ahci1_phy: phy@10 { - compatible = "socionext,uniphier-pro4-ahci-phy"; - reg = <0x10 0x40>; - clock-names = "link", "gio"; - clocks = <&sys_clk 29>, <&sys_clk 12>; - reset-names = "link", "gio", "phy", - "pm", "tx", "rx"; - resets = <&sys_rst 29>, <&sys_rst 12>, - <&sys_rst 30>, - <&ahci1_rst 0>, <&ahci1_rst 1>, - <&ahci1_rst 2>; - #phy-cells = <0>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = , - ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb0_rst 4>; - phys = <&usb_phy2>, <&usb0_ssphy>; - dr_mode = "host"; - }; - - usb-controller@65b00000 { - compatible = "socionext,uniphier-pro4-dwc3-glue", - "simple-mfd"; - reg = <0x65b00000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x100>; - - usb0_vbus: regulator@0 { - compatible = "socionext,uniphier-pro4-usb3-regulator"; - reg = <0 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - }; - - usb0_ssphy: phy@10 { - compatible = "socionext,uniphier-pro4-usb3-ssphy"; - reg = <0x10 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - vbus-supply = <&usb0_vbus>; - }; - - usb0_rst: reset-controller@40 { - compatible = "socionext,uniphier-pro4-usb3-reset"; - reg = <0x40 0x4>; - #reset-cells = <1>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = , - ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb1_rst 4>; - phys = <&usb_phy3>; - dr_mode = "host"; - }; - - usb-controller@65d00000 { - compatible = "socionext,uniphier-pro4-dwc3-glue", - "simple-mfd"; - reg = <0x65d00000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x100>; - - usb1_vbus: regulator@0 { - compatible = "socionext,uniphier-pro4-usb3-regulator"; - reg = <0 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - - usb1_rst: reset-controller@40 { - compatible = "socionext,uniphier-pro4-usb3-reset"; - reg = <0x40 0x4>; - #reset-cells = <1>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/uniphier-pro5-epcore.dts deleted file mode 100644 index ed759dcc3216..000000000000 --- a/arch/arm/boot/dts/uniphier-pro5-epcore.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE) - * - * Copyright (C) 2021 Socionext Inc. - * Author: Kunihiko Hayashi - */ - -/dts-v1/; -#include "uniphier-pro5.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier Pro5 EP-CORE Board"; - compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -ðsc { - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; -}; - -&serialsc { - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&pcie_ep { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pro5-proex.dts b/arch/arm/boot/dts/uniphier-pro5-proex.dts deleted file mode 100644 index 2cfb84f73cc0..000000000000 --- a/arch/arm/boot/dts/uniphier-pro5-proex.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Device Tree Source for UniPhier Pro5 ProEX Board - * - * Copyright (C) 2021 Socionext Inc. - * Author: Kunihiko Hayashi - */ - -/dts-v1/; -#include "uniphier-pro5.dtsi" - -/ { - model = "UniPhier Pro5 ProEX Board"; - compatible = "socionext,uniphier-pro5-proex", "socionext,uniphier-pro5"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&pcie_ep { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi deleted file mode 100644 index 2d8591cdddb8..000000000000 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ /dev/null @@ -1,707 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro5 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include - -/ { - compatible = "socionext,uniphier-pro5"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - }; - }; - - cpu_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - clock-latency-ns = <300>; - }; - opp-116667000 { - opp-hz = /bits/ 64 <116667000>; - clock-latency-ns = <300>; - }; - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - clock-latency-ns = <300>; - }; - opp-175000000 { - opp-hz = /bits/ 64 <175000000>; - clock-latency-ns = <300>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - clock-latency-ns = <300>; - }; - opp-233334000 { - opp-hz = /bits/ 64 <233334000>; - clock-latency-ns = <300>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - clock-latency-ns = <300>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - clock-latency-ns = <300>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - clock-latency-ns = <300>; - }; - opp-466667000 { - opp-hz = /bits/ 64 <466667000>; - clock-latency-ns = <300>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - clock-latency-ns = <300>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - clock-latency-ns = <300>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <300>; - }; - opp-933334000 { - opp-hz = /bits/ 64 <933334000>; - clock-latency-ns = <300>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <300>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - interrupts = , - ; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: cache-controller@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - interrupts = , - ; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; /* common with spi0 */ - resets = <&peri_rst 12>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl: syscon@59810000 { - compatible = "socionext,uniphier-pro5-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock-controller { - compatible = "socionext,uniphier-pro5-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset-controller { - compatible = "socionext,uniphier-pro5-sd-reset"; - #reset-cells = <1>; - }; - }; - - syscon@59820000 { - compatible = "socionext,uniphier-pro5-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock-controller { - compatible = "socionext,uniphier-pro5-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset-controller { - compatible = "socionext,uniphier-pro5-peri-reset"; - #reset-cells = <1>; - }; - }; - - syscon@5f800000 { - compatible = "socionext,uniphier-pro5-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; - }; - }; - - syscon@5f900000 { - compatible = "socionext,uniphier-pro5-soc-glue-debug", - "simple-mfd", "syscon"; - reg = <0x5f900000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@130 { - compatible = "socionext,uniphier-efuse"; - reg = <0x130 0x8>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x28>; - }; - - efuse@300 { - compatible = "socionext,uniphier-efuse"; - reg = <0x300 0x14>; - }; - - efuse@400 { - compatible = "socionext,uniphier-efuse"; - reg = <0x400 0x8>; - }; - }; - - xdmac: dma-controller@5fc10000 { - compatible = "socionext,uniphier-xdmac"; - reg = <0x5fc10000 0x5300>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <2>; - }; - - aidet: interrupt-controller@5fc20000 { - compatible = "socionext,uniphier-pro5-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - syscon@61840000 { - compatible = "socionext,uniphier-pro5-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock-controller { - compatible = "socionext,uniphier-pro5-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset-controller { - compatible = "socionext,uniphier-pro5-reset"; - #reset-cells = <1>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb0_rst 15>; - phys = <&usb0_hsphy0>, <&usb0_ssphy0>; - dr_mode = "host"; - }; - - usb-controller@65b00000 { - compatible = "socionext,uniphier-pro5-dwc3-glue", - "simple-mfd"; - reg = <0x65b00000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb0_rst: reset-controller@0 { - compatible = "socionext,uniphier-pro5-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - }; - - usb0_vbus0: regulator@100 { - compatible = "socionext,uniphier-pro5-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - }; - - usb0_hsphy0: phy@280 { - compatible = "socionext,uniphier-pro5-usb3-hsphy"; - reg = <0x280 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_ssphy0: phy@380 { - compatible = "socionext,uniphier-pro5-usb3-ssphy"; - reg = <0x380 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - vbus-supply = <&usb0_vbus0>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "host"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb1_rst 15>; - phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; - dr_mode = "host"; - }; - - usb-controller@65d00000 { - compatible = "socionext,uniphier-pro5-dwc3-glue", - "simple-mfd"; - reg = <0x65d00000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x400>; - - usb1_rst: reset-controller@0 { - compatible = "socionext,uniphier-pro5-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - - usb1_vbus0: regulator@100 { - compatible = "socionext,uniphier-pro5-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - - usb1_vbus1: regulator@110 { - compatible = "socionext,uniphier-pro5-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - - usb1_hsphy0: phy@280 { - compatible = "socionext,uniphier-pro5-usb3-hsphy"; - reg = <0x280 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - vbus-supply = <&usb1_vbus0>; - }; - - usb1_hsphy1: phy@290 { - compatible = "socionext,uniphier-pro5-usb3-hsphy"; - reg = <0x290 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - vbus-supply = <&usb1_vbus1>; - }; - - usb1_ssphy0: phy@380 { - compatible = "socionext,uniphier-pro5-usb3-ssphy"; - reg = <0x380 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - vbus-supply = <&usb1_vbus0>; - }; - }; - - pcie_ep: pcie-ep@66000000 { - compatible = "socionext,uniphier-pro5-pcie-ep"; - status = "disabled"; - reg-names = "dbi", "dbi2", "link", "addr_space"; - reg = <0x66000000 0x1000>, <0x66001000 0x1000>, - <0x66010000 0x10000>, <0x67000000 0x400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 24>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 24>; - num-ib-windows = <16>; - num-ob-windows = <16>; - num-lanes = <4>; - phy-names = "pcie-phy"; - phys = <&pcie_phy>; - }; - - pcie_phy: phy@66038000 { - compatible = "socionext,uniphier-pro5-pcie-phy"; - reg = <0x66038000 0x4000>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 24>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 24>; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - - emmc: mmc@68400000 { - compatible = "socionext,uniphier-sd-v3.1"; - status = "disabled"; - reg = <0x68400000 0x800>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sd_clk 1>; - reset-names = "host", "hw"; - resets = <&sd_rst 1>, <&sd_rst 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - sd: mmc@68800000 { - compatible = "socionext,uniphier-sd-v3.1"; - status = "disabled"; - reg = <0x68800000 0x800>; - interrupts = ; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - socionext,syscon-uhs-mode = <&sdctrl 0>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts deleted file mode 100644 index 5f18b926c50a..000000000000 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs2 Gentil Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pxs2.dtsi" - -/ { - model = "UniPhier PXs2 Gentil Board"; - compatible = "socionext,uniphier-pxs2-gentil", - "socionext,uniphier-pxs2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier PXs2"; - dais = <&i2s_port2>; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2s_aux { - dai-format = "i2s"; - remote-endpoint = <&wm_speaker>; -}; - -&i2c2 { - status = "okay"; - - wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - #sound-dai-cells = <0>; - - port@0 { - wm_speaker: endpoint { - dai-format = "i2s"; - remote-endpoint = <&i2s_aux>; - }; - }; - }; -}; - -&emmc { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&ahci { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts deleted file mode 100644 index 7e08a459f7d8..000000000000 --- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs2 Vodka Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pxs2.dtsi" - -/ { - model = "UniPhier PXs2 Vodka Board"; - compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier PXs2"; - dais = <&spdif_port0 - &comp_spdif_port0>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; -}; - -&serial2 { - status = "okay"; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi deleted file mode 100644 index f97a57222101..000000000000 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ /dev/null @@ -1,845 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs2 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include -#include - -/ { - compatible = "socionext,uniphier-pxs2"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - }; - - cpu_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - clock-latency-ns = <300>; - }; - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - clock-latency-ns = <300>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - clock-latency-ns = <300>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - clock-latency-ns = <300>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - clock-latency-ns = <300>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - clock-latency-ns = <300>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <300>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu-crit { - temperature = <95000>; /* 95C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu-alert { - temperature = <85000>; /* 85C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_alert>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - interrupts = , - , - , - ; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 12>; - resets = <&peri_rst 12>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 96 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1"; - ngpios = <232>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - audio@56000000 { - compatible = "socionext,uniphier-pxs2-aio"; - reg = <0x56000000 0x80000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ain1>, - <&pinctrl_ain2>, - <&pinctrl_ainiec1>, - <&pinctrl_aout2>, - <&pinctrl_aout3>, - <&pinctrl_aoutiec1>, - <&pinctrl_aoutiec2>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - socionext,syscon = <&soc_glue>; - - i2s_port0: port@0 { - i2s_hdmi: endpoint { - }; - }; - - i2s_port1: port@1 { - i2s_line: endpoint { - }; - }; - - i2s_port2: port@2 { - i2s_aux: endpoint { - }; - }; - - spdif_port0: port@3 { - spdif_hiecout1: endpoint { - }; - }; - - spdif_port1: port@4 { - spdif_iecout1: endpoint { - }; - }; - - comp_spdif_port0: port@5 { - comp_spdif_hiecout1: endpoint { - }; - }; - - comp_spdif_port1: port@6 { - comp_spdif_iecout1: endpoint { - }; - }; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 8>; - resets = <&peri_rst 8>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl: syscon@59810000 { - compatible = "socionext,uniphier-pxs2-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock-controller { - compatible = "socionext,uniphier-pxs2-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset-controller { - compatible = "socionext,uniphier-pxs2-sd-reset"; - #reset-cells = <1>; - }; - }; - - syscon@59820000 { - compatible = "socionext,uniphier-pxs2-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock-controller { - compatible = "socionext,uniphier-pxs2-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset-controller { - compatible = "socionext,uniphier-pxs2-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: mmc@5a000000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a000000 0x800>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sd_clk 1>; - reset-names = "host", "hw"; - resets = <&sd_rst 1>, <&sd_rst 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - sd: mmc@5a400000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = ; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - socionext,syscon-uhs-mode = <&sdctrl 0>; - }; - - soc_glue: syscon@5f800000 { - compatible = "socionext,uniphier-pxs2-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; - }; - }; - - syscon@5f900000 { - compatible = "socionext,uniphier-pxs2-soc-glue-debug", - "simple-mfd", "syscon"; - reg = <0x5f900000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x58>; - }; - }; - - xdmac: dma-controller@5fc10000 { - compatible = "socionext,uniphier-xdmac"; - reg = <0x5fc10000 0x5300>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <2>; - }; - - aidet: interrupt-controller@5fc20000 { - compatible = "socionext,uniphier-pxs2-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - syscon@61840000 { - compatible = "socionext,uniphier-pxs2-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock-controller { - compatible = "socionext,uniphier-pxs2-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset-controller { - compatible = "socionext,uniphier-pxs2-reset"; - #reset-cells = <1>; - }; - - pvtctl: thermal-sensor { - compatible = "socionext,uniphier-pxs2-thermal"; - interrupts = ; - #thermal-sensor-cells = <0>; - socionext,tmod-calibration = <0x0f86 0x6844>; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-pxs2-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ahci: sata@65600000 { - compatible = "socionext,uniphier-pxs2-ahci", - "generic-ahci"; - status = "disabled"; - reg = <0x65600000 0x10000>; - interrupts = ; - clocks = <&sys_clk 28>; - resets = <&sys_rst 28>, <&ahci_rst 0>; - ports-implemented = <1>; - phys = <&ahci_phy>; - }; - - sata-controller@65700000 { - compatible = "socionext,uniphier-pxs2-ahci-glue", - "simple-mfd"; - reg = <0x65700000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65700000 0x100>; - - ahci_rst: reset-controller@0 { - compatible = "socionext,uniphier-pxs2-ahci-reset"; - reg = <0x0 0x4>; - clock-names = "link"; - clocks = <&sys_clk 28>; - reset-names = "link"; - resets = <&sys_rst 28>; - #reset-cells = <1>; - }; - - ahci_phy: phy@10 { - compatible = "socionext,uniphier-pxs2-ahci-phy"; - reg = <0x10 0x10>; - clock-names = "link"; - clocks = <&sys_clk 28>; - reset-names = "link", "phy"; - resets = <&sys_rst 28>, <&sys_rst 30>; - #phy-cells = <0>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "dwc_usb3"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; - resets = <&usb0_rst 15>; - phys = <&usb0_hsphy0>, <&usb0_hsphy1>, - <&usb0_ssphy0>, <&usb0_ssphy1>; - dr_mode = "host"; - }; - - usb-controller@65b00000 { - compatible = "socionext,uniphier-pxs2-dwc3-glue", - "simple-mfd"; - reg = <0x65b00000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb0_rst: reset-controller@0 { - compatible = "socionext,uniphier-pxs2-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb0_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb0_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb0_hsphy0: phy@200 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_hsphy1: phy@210 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus1>; - }; - - usb0_ssphy0: phy@300 { - compatible = "socionext,uniphier-pxs2-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 17>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_ssphy1: phy@310 { - compatible = "socionext,uniphier-pxs2-usb3-ssphy"; - reg = <0x310 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 18>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 18>; - vbus-supply = <&usb0_vbus1>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "dwc_usb3"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; - resets = <&usb1_rst 15>; - phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; - dr_mode = "host"; - }; - - usb-controller@65d00000 { - compatible = "socionext,uniphier-pxs2-dwc3-glue", - "simple-mfd"; - reg = <0x65d00000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x400>; - - usb1_rst: reset-controller@0 { - compatible = "socionext,uniphier-pxs2-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 15>; - reset-names = "link"; - resets = <&sys_rst 15>; - }; - - usb1_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 15>; - reset-names = "link"; - resets = <&sys_rst 15>; - }; - - usb1_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 15>; - reset-names = "link"; - resets = <&sys_rst 15>; - }; - - usb1_hsphy0: phy@200 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 15>, <&sys_clk 20>; - reset-names = "link", "phy"; - resets = <&sys_rst 15>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus0>; - }; - - usb1_hsphy1: phy@210 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 15>, <&sys_clk 20>; - reset-names = "link", "phy"; - resets = <&sys_rst 15>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus1>; - }; - - usb1_ssphy0: phy@300 { - compatible = "socionext,uniphier-pxs2-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 15>, <&sys_clk 21>; - reset-names = "link", "phy"; - resets = <&sys_rst 15>, <&sys_rst 21>; - vbus-supply = <&usb1_vbus0>; - }; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi deleted file mode 100644 index a11897669c26..000000000000 --- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Reference Daughter Board -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada - -&i2c0 { - eeprom@50 { - compatible = "microchip,24lc128", "atmel,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts deleted file mode 100644 index 2446f9e15360..000000000000 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier sLD8 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-sld8.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier sLD8 Reference Board"; - compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serialsc; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -ðsc { - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -}; - -&serialsc { - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio { - xirq0-hog { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi deleted file mode 100644 index f876282760e9..000000000000 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ /dev/null @@ -1,436 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier sLD8 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-sld8"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = , - ; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 104 0 0>, - <&pinctrl 112 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2"; - ngpios = <136>; - socionext,interrupt-ranges = <0 48 13>, <14 62 2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl: syscon@59810000 { - compatible = "socionext,uniphier-sld8-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock-controller { - compatible = "socionext,uniphier-sld8-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset-controller { - compatible = "socionext,uniphier-sld8-mio-reset"; - #reset-cells = <1>; - }; - }; - - syscon@59820000 { - compatible = "socionext,uniphier-sld8-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock-controller { - compatible = "socionext,uniphier-sld8-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset-controller { - compatible = "socionext,uniphier-sld8-peri-reset"; - #reset-cells = <1>; - }; - }; - - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = , - , - , - , - , - , - ; - clocks = <&mio_clk 7>; - resets = <&mio_rst 7>; - #dma-cells = <1>; - }; - - sd: mmc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = ; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - socionext,syscon-uhs-mode = <&mioctrl 0>; - }; - - emmc: mmc@5a500000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge", "hw"; - resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; - dma-names = "rx-tx"; - dmas = <&dmac 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - has-transaction-translator; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - has-transaction-translator; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, - <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - has-transaction-translator; - }; - - syscon@5f800000 { - compatible = "socionext,uniphier-sld8-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; - }; - }; - - syscon@5f900000 { - compatible = "socionext,uniphier-sld8-soc-glue-debug", - "simple-mfd", "syscon"; - reg = <0x5f900000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x14>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = ; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - aidet: interrupt-controller@61830000 { - compatible = "socionext,uniphier-sld8-aidet"; - reg = <0x61830000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - syscon@61840000 { - compatible = "socionext,uniphier-sld8-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock-controller { - compatible = "socionext,uniphier-sld8-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset-controller { - compatible = "socionext,uniphier-sld8-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi deleted file mode 100644 index 97e7d5db8eb8..000000000000 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Support Card (Expansion Board) -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada - -&system_bus { - status = "okay"; - ranges = <1 0x00000000 0x42000000 0x02000000>; - - ethsc: ethernet@1,1f00000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <1 0x01f00000 0x1000>; - phy-mode = "mii"; - reg-io-width = <4>; - interrupt-parent = <&gpio>; - }; - - serialsc: serial@1,1fb0000 { - compatible = "ns16550a"; - reg = <1 0x01fb0000 0x20>; - clock-frequency = <12288000>; - reg-shift = <1>; - interrupt-parent = <&gpio>; - }; -}; diff --git a/arch/arm/boot/dts/unisoc/Makefile b/arch/arm/boot/dts/unisoc/Makefile new file mode 100644 index 000000000000..dba5cd874ee7 --- /dev/null +++ b/arch/arm/boot/dts/unisoc/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_RDA) += \ + rda8810pl-orangepi-2g-iot.dtb \ + rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts new file mode 100644 index 000000000000..98e34248ae80 --- /dev/null +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "rda8810pl.dtsi" + +/ { + compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; + model = "Orange Pi 2G-IoT"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial2:921600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart_clk>; +}; diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts new file mode 100644 index 000000000000..728f76931b99 --- /dev/null +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "rda8810pl.dtsi" + +/ { + compatible = "xunlong,orangepi-i96", "rda,8810pl"; + model = "Orange Pi i96"; + + aliases { + serial0 = &uart2; + serial1 = &uart1; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial2:921600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart_clk>; +}; diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi new file mode 100644 index 000000000000..f30d6ece49fb --- /dev/null +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RDA8810PL SoC + * + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include + +/ { + compatible = "rda,8810pl"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0x0>; + }; + }; + + sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + modem@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0xfffffff>; + + gpioc@1a08000 { + compatible = "rda,8810pl-gpio"; + reg = <0x1a08000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + }; + }; + + apb@20800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20800000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "rda,8810pl-intc"; + reg = <0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + apb@20900000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20900000 0x100000>; + + timer@10000 { + compatible = "rda,8810pl-timer"; + reg = <0x10000 0x1000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, + <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hwtimer", "ostimer"; + }; + + gpioa@30000 { + compatible = "rda,8810pl-gpio"; + reg = <0x30000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpiob@31000 { + compatible = "rda,8810pl-gpio"; + reg = <0x31000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpiod@32000 { + compatible = "rda,8810pl-gpio"; + reg = <0x32000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + apb@20a00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20a00000 0x100000>; + + uart1: serial@0 { + compatible = "rda,8810pl-uart"; + reg = <0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@10000 { + compatible = "rda,8810pl-uart"; + reg = <0x10000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart3: serial@90000 { + compatible = "rda,8810pl-uart"; + reg = <0x90000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + l2: cache-controller@21100000 { + compatible = "arm,pl310-cache"; + reg = <0x21100000 0x1000>; + cache-unified; + cache-level = <2>; + }; +}; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts deleted file mode 100644 index 6cfa83921ac2..000000000000 --- a/arch/arm/boot/dts/usb_a9260.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9260.dts - Device Tree file for Caloa USB A9260 board - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - model = "Calao USB A9260"; - compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - ahb { - apb { - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi deleted file mode 100644 index 8744b5f6f792..000000000000 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a926x.dts - Device Tree file for Caloa USB A926x board - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts deleted file mode 100644 index b6cb9cdf8197..000000000000 --- a/arch/arm/boot/dts/usb_a9263.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Calao USB A9263"; - compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffa4000 { - cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <0>; - spi-max-frequency = <15000000>; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - - ebi0: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@a00000 { - num-ports = <2>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi deleted file mode 100644 index 08d58081201a..000000000000 --- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - ahb { - apb { - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - }; - }; - - i2c-gpio@0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "user_led1"; - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - }; - -/* -* led already used by mother board but active as high -* user_led2 { -* label = "user_led2"; -* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; -* }; -*/ - user_led3 { - label = "user_led3"; - gpios = <&pioB 22 GPIO_ACTIVE_LOW>; - }; - - user_led4 { - label = "user_led4"; - gpios = <&pioB 23 GPIO_ACTIVE_LOW>; - }; - - red { - label = "red"; - gpios = <&pioB 24 GPIO_ACTIVE_LOW>; - }; - - orange { - label = "orange"; - gpios = <&pioB 30 GPIO_ACTIVE_LOW>; - }; - - green { - label = "green"; - gpios = <&pioB 31 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb1 { - label = "user_pb1"; - gpios = <&pioB 25 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - }; - - user_pb2 { - label = "user_pb2"; - gpios = <&pioB 13 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - }; - - user_pb3 { - label = "user_pb3"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - }; - - user_pb4 { - label = "user_pb4"; - gpios = <&pioC 9 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - }; - }; -}; diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts deleted file mode 100644 index 2f667b083e81..000000000000 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "usb_a9g20_common.dtsi" - -/ { - model = "Calao USB A9G20"; - compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; -}; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi deleted file mode 100644 index 7d10b36db1ee..000000000000 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9g20.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - i2c-gpio-0 { - rtc@56 { - compatible = "microcrystal,rv3029"; - reg = <0x56>; - }; - }; -}; diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts deleted file mode 100644 index f65712015d40..000000000000 --- a/arch/arm/boot/dts/usb_a9g20_lpw.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "usb_a9g20_common.dtsi" - -/ { - model = "Calao USB A9G20 Low Power"; - compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; - - ahb { - apb { - spi1: spi@fffcc000 { - cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - mmc-slot@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - voltage-ranges = <3200 3400>; - spi-max-frequency = <25000000>; - interrupt-parent = <&pioC>; - interrupts = <4 IRQ_TYPE_EDGE_BOTH>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts deleted file mode 100644 index 7ebb0dfd0467..000000000000 --- a/arch/arm/boot/dts/versatile-ab-ib2.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The Versatile AB with the IB2 expansion board mounted. - * This works as a superset of the Versatile AB. - */ - -#include "versatile-ab.dts" - -/ { - model = "ARM Versatile AB + IB2 board"; - - /* Special IB2 control register */ - syscon@27000000 { - compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; - reg = <0x27000000 0x4>; - ranges = <0x0 0x27000000 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - led@0,4 { - compatible = "register-bit-led"; - reg = <0x00 0x04>; - offset = <0x00>; - mask = <0x10>; - label = "versatile-ib2:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - }; -}; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts deleted file mode 100644 index f31dcf7e5862..000000000000 --- a/arch/arm/boot/dts/versatile-ab.dts +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -/ { - model = "ARM Versatile AB"; - compatible = "arm,versatile-ab"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - }; - - chosen { - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - bridge { - compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads_vga_dac>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - core-module@10000000 { - compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; - reg = <0x10000000 0x200>; - ranges = <0x0 0x10000000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - - led@8,0 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8,1 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8,2 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8,3 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8,4 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8,5 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8,6 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8,7 { - compatible = "register-bit-led"; - reg = <0x08 0x04>; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - - /* OSC1 on AB, OSC4 on PB */ - osc1: cm_aux_osc@24M { - #clock-cells = <0>; - compatible = "arm,versatile-cm-auxosc"; - clocks = <&xtal24mhz>; - }; - - /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - pclk: pclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - }; - - flash@34000000 { - /* 64 MiB NOR flash in non-interleaved chips */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x34000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - net@10010000 { - compatible = "smsc,lan91c111"; - reg = <0x10010000 0x10000>; - interrupts = <25>; - }; - - lcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic: interrupt-controller@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x1000>; - valid-mask = <0xffffffff>; - }; - - sic: interrupt-controller@10003000 { - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10003000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <31>; /* Cascaded to vic */ - clear-mask = <0xffffffff>; - /* - * Valid interrupt lines mask according to - * table 4-36 page 4-50 of ARM DUI 0225D - */ - valid-mask = <0x0760031b>; - }; - - dma@10130000 { - compatible = "arm,pl081", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupts = <17>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart0: serial@101f1000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f1000 0x1000>; - interrupts = <12>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: serial@101f2000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f2000 0x1000>; - interrupts = <13>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart2: serial@101f3000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f3000 0x1000>; - interrupts = <14>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - smc@10100000 { - compatible = "arm,primecell"; - reg = <0x10100000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mpmc@10110000 { - compatible = "arm,primecell"; - reg = <0x10110000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - display@10120000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x10120000 0x1000>; - interrupts = <16>; - clocks = <&osc1>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @ 36MHz works fine */ - max-memory-bandwidth = <54000000>; - - /* - * This port is routed through a PLD (Programmable - * Logic Device) that routes the output from the CLCD - * (after transformations) to the VGA DAC and also an - * external panel connector. The PLD is essential for - * supporting RGB565/BGR565. - * - * The signals from the port thus reaches two endpoints. - * The PLD is managed through a few special bits in the - * FPGA "sysreg". - * - * This arrangement can be clearly seen in - * ARM DUI 0225D, page 3-41, figure 3-19. - */ - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - clcd_pads_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - clcd_pads_vga_dac: endpoint@1 { - reg = <1>; - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - sctl@101e0000 { - compatible = "arm,primecell"; - reg = <0x101e0000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - watchdog@101e1000 { - compatible = "arm,primecell"; - reg = <0x101e1000 0x1000>; - interrupts = <0>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer@101e2000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x101e2000 0x1000>; - interrupts = <4>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0", "timer1", "apb_pclk"; - }; - - timer@101e3000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x101e3000 0x1000>; - interrupts = <5>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0", "timer1", "apb_pclk"; - }; - - gpio0: gpio@101e4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e4000 0x1000>; - gpio-controller; - interrupts = <6>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@101e5000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e5000 0x1000>; - interrupts = <7>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@101e8000 { - compatible = "arm,pl030", "arm,primecell"; - reg = <0x101e8000 0x1000>; - interrupts = <10>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - sci@101f0000 { - compatible = "arm,primecell"; - reg = <0x101f0000 0x1000>; - interrupts = <15>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - spi@101f4000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x101f4000 0x1000>; - interrupts = <11>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "sspclk", "apb_pclk"; - }; - - fpga { - compatible = "arm,versatile-fpga", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000000 0x10000>; - - sysreg@0 { - compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; - reg = <0x00000 0x1000>; - - panel: display@0 { - compatible = "arm,versatile-tft-panel"; - - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads_panel>; - }; - }; - }; - }; - - aaci@4000 { - compatible = "arm,primecell"; - reg = <0x4000 0x1000>; - interrupts = <24>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - mmc@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x5000 0x1000>; - interrupts-extended = <&vic 22 &sic 1>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x6000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <3>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x7000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <4>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts deleted file mode 100644 index fc21ce54b33a..000000000000 --- a/arch/arm/boot/dts/versatile-pb.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "versatile-ab.dts" - -/ { - model = "ARM Versatile PB"; - compatible = "arm,versatile-pb"; - - amba { - /* The Versatile PB is using more SIC IRQ lines than the AB */ - sic: interrupt-controller@10003000 { - clear-mask = <0xffffffff>; - /* - * Valid interrupt lines mask according to - * figure 3-30 page 3-74 of ARM DUI 0224B - */ - valid-mask = <0x7fe003ff>; - }; - - gpio2: gpio@101e6000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e6000 0x1000>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@101e7000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e7000 0x1000>; - interrupts = <9>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pci@10001000 { - compatible = "arm,versatile-pci"; - device_type = "pci"; - reg = <0x10001000 0x1000 - 0x41000000 0x10000 - 0x42000000 0x100000>; - bus-range = <0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ - 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ - 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ - - interrupt-map-mask = <0x1800 0 0 7>; - interrupt-map = <0x1800 0 0 1 &sic 28 - 0x1800 0 0 2 &sic 29 - 0x1800 0 0 3 &sic 30 - 0x1800 0 0 4 &sic 27 - - 0x1000 0 0 1 &sic 27 - 0x1000 0 0 2 &sic 28 - 0x1000 0 0 3 &sic 29 - 0x1000 0 0 4 &sic 30 - - 0x0800 0 0 1 &sic 30 - 0x0800 0 0 2 &sic 27 - 0x0800 0 0 3 &sic 28 - 0x0800 0 0 4 &sic 29 - - 0x0000 0 0 1 &sic 29 - 0x0000 0 0 2 &sic 30 - 0x0000 0 0 3 &sic 27 - 0x0000 0 0 4 &sic 28>; - }; - - fpga { - mmc@5000 { - /* - * Overrides the interrupt assignment from - * the Versatile AB board file. - */ - interrupts-extended = <&sic 22 &sic 23>; - }; - serial@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x9000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <6>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - sci@a000 { - compatible = "arm,primecell"; - reg = <0xa000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <5>; - clocks = <&xtal24mhz>; - clock-names = "apb_pclk"; - }; - mmc@b000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0xb000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <1>, <2>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi deleted file mode 100644 index 8af4b77fe655..000000000000 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,494 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ -#include - -/ { - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "disk-activity"; - }; - - led-3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - led-4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - led-5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - led-6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - led-7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - led-8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - bus@8000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 63>; - interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - - motherboard-bus@8000000 { - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - nor_flash: flash@0 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - psram@100000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@202000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@203000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - dr_mode = "peripheral"; - }; - - iofpga-bus@300000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@30000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmc@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: serial@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: serial@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: serial@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: serial@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - watchdog@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dvi_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&dvi_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi deleted file mode 100644 index c5e92f6d2fcd..000000000000 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ /dev/null @@ -1,509 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ -#include - -/ { - bus@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x10000000>, - <0x10000000 0x10000000 0x00020000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 63>; - interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - - motherboard-bus@40000000 { - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - dr_mode = "peripheral"; - }; - - iofpga@7,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - v2m_sysreg: sysreg@0 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@1000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@2000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@4000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: serial@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: serial@a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: serial@b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: serial@c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Both the core tile and the motherboard routes their output - * pads to this transmitter. The motherboard system controller - * can select one of them as input using a mux register in - * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is - * the only platform with this specific set-up. - */ - port@0 { - reg = <0>; - dvi_bridge_in_ct: endpoint { - remote-endpoint = <&clcd_pads_ct>; - }; - }; - port@1 { - reg = <1>; - dvi_bridge_in_mb: endpoint { - remote-endpoint = <&clcd_pads_mb>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads_mb: endpoint { - remote-endpoint = <&dvi_bridge_in_mb>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - led-user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - led-user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - led-user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - led-user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - led-user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - led-user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - led-user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - led-user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts deleted file mode 100644 index 679537e17ff5..000000000000 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 (version with Test Chip 1) - * Cortex-A15 MPCore (V2P-CA15) - * - * HBI-0237A - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA15"; - arm,hbi = <0x237>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - wdt@2b060000 { - compatible = "arm,sp805", "arm,primecell"; - status = "disabled"; - reg = <0 0x2b060000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&sys_pll>, <&sys_pll>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - dma@7ffb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ffb0000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* CPU PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk4 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - sys_pll: oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <20000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <40000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-cores { - /* CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "Cores"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "Cores"; - }; - - amp-cores { - /* Total current for the two cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "Cores"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-cores { - /* Total power */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "Cores"; - }; - - energy { - /* Total energy */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>; - label = "Cores"; - }; - }; - - bus@8000000 { - ranges = <0x8000000 0 0x8000000 0x18000000>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts deleted file mode 100644 index 511e87cc2bc5..000000000000 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ /dev/null @@ -1,636 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 A7x3 - * Cortex-A15_A7 MPCore (V2P-CA15_A7) - * - * HBI-0249A - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA15_CA7"; - arm,hbi = <0x249>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu4: cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - idle-states { - CLUSTER_SLEEP_BIG: cluster-sleep-big { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_LITTLE: cluster-sleep-little { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <500>; - min-residency-us = <2500>; - }; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - wdt@2a490000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0 0x2a490000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r0"; - reg = <0x9000 0x5000>; - interrupts = <0 105 4>, - <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>; - }; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ff00000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - scc@7fff0000 { - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - reg = <0 0x7fff0000 0 0x1000>; - interrupts = <0 95 4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu-a15 { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>; - }; - - pmu-a7 { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 128 4>, - <0 129 4>, - <0 130 4>; - interrupt-affinity = <&cpu2>, - <&cpu3>, - <&cpu4>; - }; - - oscclk6a: oscclk6a { - /* Reference 24MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "oscclk6a"; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* A15 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk1 { - /* A15 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* A7 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - oscclk3 { - /* A7 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* External AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* Static memory controller clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-a15 { - /* A15 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "A15 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A15 Vcore"; - }; - - volt-a7 { - /* A7 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "A7 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A7 Vcore"; - }; - - amp-a15 { - /* Total current for the two A15 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "A15 Icore"; - }; - - amp-a7 { - /* Total current for the three A7 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "A7 Icore"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-a15 { - /* Total power for the two A15 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "A15 Pcore"; - }; - - power-a7 { - /* Total power for the three A7 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "A7 Pcore"; - }; - - energy-a15 { - /* Total energy for the two A15 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - label = "A15 Jcore"; - }; - - energy-a7 { - /* Total energy for the three A7 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 2>, <13 3>; - label = "A7 Jcore"; - }; - }; - - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* Input port #3 is for ITM, not supported here */ - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@5 { - reg = <5>; - funnel_in_port5: endpoint { - remote-endpoint = <&etm2_out_port>; - }; - }; - }; - }; - - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - etm@2203c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203c000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - }; - - etm@2203d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203d000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - }; - - etm@2203e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203e000 0 0x1000>; - - cpu = <&cpu4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm2_out_port: endpoint { - remote-endpoint = <&funnel_in_port5>; - }; - }; - }; - }; - - smb: bus@8000000 { - ranges = <0x8000000 0 0x8000000 0x18000000>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; - -&nor_flash { - /* - * Unfortunately, accessing the flash disturbs the CPU idle states - * (suspend) and CPU hotplug of this platform. For this reason, flash - * hardware access is disabled by default on this platform alone. - */ - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts deleted file mode 100644 index 3b88209bacea..000000000000 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x18000000 0x00800000>; - no-map; - }; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0x304>; - }; - - timer@2c000200 { - compatible = "arm,cortex-a5-global-timer", - "arm,cortex-a9-global-timer"; - reg = <0x2c000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&cpu_clk>; - }; - - watchdog@2c000620 { - compatible = "arm,cortex-a5-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - cpu_clk: oscclk0 { - /* CPU and internal AXI reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 100000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - axi_clk: oscclk1 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <5000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* DDR2 */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <80000000 120000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - hdlcd_clk: oscclk3 { - /* HDLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* Test chip gate configuration */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <80000000 80000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - smbclk: oscclk5 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - temp-dcc { - /* DCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - }; - - smb: bus@8000000 { - ranges = <0 0x8000000 0x18000000>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts deleted file mode 100644 index 5916e4877eac..000000000000 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,310 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; -#include "vexpress-v2m.dtsi" - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 3 is physically at 0x4c000000 */ - vram: vram@4c000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x4c000000 0x00800000>; - no-map; - }; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads_ct: endpoint { - remote-endpoint = <&dvi_bridge_in_ct>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1e000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e000620 0x20>; - interrupts = <1 14 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; - - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0: extsaxiclk { - /* ACLK clock to the AXI master port on the test chip */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <30000000 50000000>; - #clock-cells = <0>; - clock-output-names = "extsaxiclk"; - }; - - oscclk1: clcdclk { - /* Reference clock for the CLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <10000000 80000000>; - #clock-cells = <0>; - clock-output-names = "clcdclk"; - }; - - smbclk: oscclk2: tcrefclk { - /* Reference clock for the test chip internal PLLs */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <33000000 100000000>; - #clock-cells = <0>; - clock-output-names = "tcrefclk"; - }; - - volt-vd10 { - /* Test Chip internal logic voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VD10"; - regulator-always-on; - label = "VD10"; - }; - - volt-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "VD10_S2"; - regulator-always-on; - label = "VD10_S2"; - }; - - volt-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 2>; - regulator-name = "VD10_S3"; - regulator-always-on; - label = "VD10_S3"; - }; - - volt-vcc1v8 { - /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 3>; - regulator-name = "VCC1V8"; - regulator-always-on; - label = "VCC1V8"; - }; - - volt-ddr2vtt { - /* DDR2 SDRAM VTT termination voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 4>; - regulator-name = "DDR2VTT"; - regulator-always-on; - label = "DDR2VTT"; - }; - - volt-vcc3v3 { - /* Local board supply for miscellaneous logic external to the Test Chip */ - arm,vexpress-sysreg,func = <2 5>; - compatible = "arm,vexpress-volt"; - regulator-name = "VCC3V3"; - regulator-always-on; - label = "VCC3V3"; - }; - - amp-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "VD10_S2"; - }; - - amp-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "VD10_S3"; - }; - - power-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "PVD10_S2"; - }; - - power-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "PVD10_S3"; - }; - }; - - site2: hsb@e0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe0000000 0x20000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi deleted file mode 100644 index 14c411f146f5..000000000000 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2020 Toradex - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - - port { - panel_in: endpoint { - remote-endpoint = <&dcu_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */ - vin-supply = <®_5v0>; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - status = "okay"; -}; - -&dcu0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dcu0_1>; - status = "okay"; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&dspi1 { - status = "okay"; - - mcp2515can: can@0 { - compatible = "microchip,mcp2515"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - clocks = <&clk16m>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_module_3v3 { - vin-supply = <®_3v3>; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh_vbus>; -}; - -&iomuxc { - vf610-colibri { - pinctrl_can_int: can_int { - fsl,pins = < - VF610_PAD_PTB21__GPIO_43 0x22ed - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi deleted file mode 100644 index cc1e069c44e6..000000000000 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ /dev/null @@ -1,350 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2020 Toradex - * - */ - -/ { - aliases { - ethernet0 = &fec1; - ethernet1 = &fec0; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm0 0 5000000 0>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc0 { - status = "okay"; - vref-supply = <®_module_3v3_avdd>; -}; - -&adc1 { - status = "okay"; - vref-supply = <®_module_3v3_avdd>; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan0>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&clks { - assigned-clocks = <&clks VF610_CLK_ENET_SEL>, - <&clks VF610_CLK_ENET_TS_SEL>; - assigned-clock-parents = <&clks VF610_CLK_ENET_50M>, - <&clks VF610_CLK_ENET_50M>; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - disable-wp; -}; - -&fec1 { - phy-mode = "rmii"; - phy-supply = <®_module_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; -}; - -&i2c0 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <32>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_flexcan0: can0grp { - fsl,pins = < - VF610_PAD_PTB14__CAN0_RX 0x31F1 - VF610_PAD_PTB15__CAN0_TX 0x31F2 - >; - }; - - pinctrl_flexcan1: can1grp { - fsl,pins = < - VF610_PAD_PTB16__CAN1_RX 0x31F1 - VF610_PAD_PTB17__CAN1_TX 0x31F2 - >; - }; - - pinctrl_gpio_ext: gpio_ext { - fsl,pins = < - VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ - VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ - VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ - >; - }; - - pinctrl_dcu0_1: dcu0grp_1 { - fsl,pins = < - VF610_PAD_PTE0__DCU0_HSYNC 0x1902 - VF610_PAD_PTE1__DCU0_VSYNC 0x1902 - VF610_PAD_PTE2__DCU0_PCLK 0x1902 - VF610_PAD_PTE4__DCU0_DE 0x1902 - VF610_PAD_PTE5__DCU0_R0 0x1902 - VF610_PAD_PTE6__DCU0_R1 0x1902 - VF610_PAD_PTE7__DCU0_R2 0x1902 - VF610_PAD_PTE8__DCU0_R3 0x1902 - VF610_PAD_PTE9__DCU0_R4 0x1902 - VF610_PAD_PTE10__DCU0_R5 0x1902 - VF610_PAD_PTE11__DCU0_R6 0x1902 - VF610_PAD_PTE12__DCU0_R7 0x1902 - VF610_PAD_PTE13__DCU0_G0 0x1902 - VF610_PAD_PTE14__DCU0_G1 0x1902 - VF610_PAD_PTE15__DCU0_G2 0x1902 - VF610_PAD_PTE16__DCU0_G3 0x1902 - VF610_PAD_PTE17__DCU0_G4 0x1902 - VF610_PAD_PTE18__DCU0_G5 0x1902 - VF610_PAD_PTE19__DCU0_G6 0x1902 - VF610_PAD_PTE20__DCU0_G7 0x1902 - VF610_PAD_PTE21__DCU0_B0 0x1902 - VF610_PAD_PTE22__DCU0_B1 0x1902 - VF610_PAD_PTE23__DCU0_B2 0x1902 - VF610_PAD_PTE24__DCU0_B3 0x1902 - VF610_PAD_PTE25__DCU0_B4 0x1902 - VF610_PAD_PTE26__DCU0_B5 0x1902 - VF610_PAD_PTE27__DCU0_B6 0x1902 - VF610_PAD_PTE28__DCU0_B7 0x1902 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x33e2 - VF610_PAD_PTD6__DSPI1_SIN 0x33e1 - VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 - VF610_PAD_PTD8__DSPI1_SCK 0x33e2 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB20__GPIO_42 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_bl_on: gpio_bl_on { - fsl,pins = < - VF610_PAD_PTC0__GPIO_45 0x22ef - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c0_gpio: i2c0gpiogrp { - fsl,pins = < - VF610_PAD_PTB14__GPIO_36 0x37ff - VF610_PAD_PTB15__GPIO_37 0x37ff - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1182 - VF610_PAD_PTB1__FTM0_CH1 0x1182 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - VF610_PAD_PTB8__FTM1_CH0 0x1182 - VF610_PAD_PTB9__FTM1_CH1 0x1182 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - VF610_PAD_PTB12__UART0_RTS 0x21a2 - VF610_PAD_PTB13__UART0_CTS 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - - pinctrl_usbh1_reg: gpio_usb_vbus { - fsl,pins = < - VF610_PAD_PTD4__GPIO_83 0x22ed - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts deleted file mode 100644 index 088964f8dc4b..000000000000 --- a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2020 Toradex - */ - -/dts-v1/; -#include "vf500-colibri.dtsi" -#include "vf-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri VF50 on Colibri Evaluation Board"; - compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500"; -}; - -&touchscreen { - vf50-ts-min-pressure = <200>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi deleted file mode 100644 index 8af7ed56e653..000000000000 --- a/arch/arm/boot/dts/vf500-colibri.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2020 Toradex - */ - -#include "vf500.dtsi" -#include "vf-colibri.dtsi" - -/ { - model = "Toradex Colibri VF50 COM"; - compatible = "toradex,vf500-colibri_vf50", "fsl,vf500"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - touchscreen: vf50-touchscreen { - compatible = "toradex,vf50-touchscreen"; - io-channels = <&adc1 0>,<&adc0 0>, - <&adc0 1>,<&adc1 2>; - xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "idle","default","gpios"; - pinctrl-0 = <&pinctrl_touchctrl_idle>; - pinctrl-1 = <&pinctrl_touchctrl_default>; - pinctrl-2 = <&pinctrl_touchctrl_gpios>; - vf50-ts-min-pressure = <200>; - status = "disabled"; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; -}; - -&iomuxc { - vf610-colibri { - pinctrl_touchctrl_idle: touchctrl_idle { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x006d - VF610_PAD_PTA19__GPIO_9 0x006c - >; - }; - - pinctrl_touchctrl_default: touchctrl_default { - fsl,pins = < - VF610_PAD_PTA18__ADC0_SE0 0x0040 - VF610_PAD_PTA19__ADC0_SE1 0x0040 - VF610_PAD_PTA16__ADC1_SE0 0x0040 - VF610_PAD_PTB2__ADC1_SE2 0x0040 - >; - }; - - pinctrl_touchctrl_gpios: touchctrl_gpios { - fsl,pins = < - VF610_PAD_PTA23__GPIO_13 0x22e9 - VF610_PAD_PTB23__GPIO_93 0x22e9 - VF610_PAD_PTA22__GPIO_12 0x22e9 - VF610_PAD_PTA11__GPIO_4 0x22e9 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi deleted file mode 100644 index 0c0dd442300a..000000000000 --- a/arch/arm/boot/dts/vf500.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include "vfxxx.dtsi" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a5_cpu: cpu@0 { - compatible = "arm,cortex-a5"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - soc { - bus@40000000 { - - intc: interrupt-controller@40003000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x40003000 0x1000>, - <0x40002100 0x100>; - }; - - global_timer: timer@40002200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x40002200 0x20>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&clks VF610_CLK_PLATFORM_BUS>; - }; - }; - - bus@40080000 { - pmu@40089000 { - compatible = "arm,cortex-a5-pmu"; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a5_cpu>; - reg = <0x40089000 0x1000>; - }; - }; - - }; -}; - -&mscm_ir { - interrupt-parent = <&intc>; -}; - -&wdoga5 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts deleted file mode 100644 index e4f691d601cc..000000000000 --- a/arch/arm/boot/dts/vf610-bk4.dts +++ /dev/null @@ -1,537 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "Liebherr BK4 controller"; - compatible = "lwn,bk4", "fsl,vf610"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - audio_ext: oscillator-audio { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - enet_ext: oscillator-ethernet { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - /* LED D5 */ - led0: led-heartbeat { - label = "heartbeat"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vcc_3v3_mcu: regulator-vcc3v3mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - spi { - compatible = "spi-gpio"; - pinctrl-0 = <&pinctrl_gpio_spi>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - /* PTD12 ->RPIO[91] */ - sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - /* PTD10 ->RPIO[89] */ - miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - num-chipselects = <0>; - - gpio@0 { - compatible = "pisosr-gpio"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - /* PTB18 -> RGPIO[40] */ - load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - spi-max-frequency = <100000>; - }; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; - clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; -}; - -&dspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - bus-num = <0>; - status = "okay"; - - spidev0@0 { - compatible = "lwn,bk4"; - spi-max-frequency = <30000000>; - reg = <0>; - fsl,spi-cs-sck-delay = <200>; - fsl,spi-sck-cs-delay = <400>; - }; -}; - -&dspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi3>; - bus-num = <3>; - status = "okay"; - spi-slave; - #address-cells = <0>; - - slave { - compatible = "lwn,bk4"; - spi-max-frequency = <30000000>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - reg = <1>; - clocks = <&clks VF610_CLK_ENET_50M>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec1 { - phy-mode = "rmii"; - phy-handle = <ðphy1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - clocks = <&clks VF610_CLK_ENET_50M>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24c256: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - m41t62: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - status = "okay"; - - n25q128a13_4: flash@0 { - compatible = "n25q128a13", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - reg = <0>; - }; - - n25q128a13_2: flash@2 { - compatible = "n25q128a13", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <2>; - reg = <2>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - /delete-property/dma-names; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - /delete-property/dma-names; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - /delete-property/dma-names; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - /delete-property/dma-names; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* One_Wire_PSU_EN */ - VF610_PAD_PTC29__GPIO_102 0x1183 - /* SPI ENABLE */ - VF610_PAD_PTB26__GPIO_96 0x1183 - /* EB control */ - VF610_PAD_PTE14__GPIO_119 0x1183 - VF610_PAD_PTE4__GPIO_109 0x1181 - /* Feedback_Lines */ - VF610_PAD_PTC31__GPIO_104 0x1181 - VF610_PAD_PTA7__GPIO_134 0x1181 - VF610_PAD_PTD9__GPIO_88 0x1181 - VF610_PAD_PTE1__GPIO_106 0x1183 - VF610_PAD_PTB2__GPIO_24 0x1181 - VF610_PAD_PTB3__GPIO_25 0x1181 - VF610_PAD_PTB1__GPIO_23 0x1181 - /* SDHC Enable */ - VF610_PAD_PTE19__GPIO_124 0x1183 - /* SDHC Overcurrent */ - VF610_PAD_PTB23__GPIO_93 0x1181 - /* GPI */ - VF610_PAD_PTE2__GPIO_107 0x1181 - VF610_PAD_PTE3__GPIO_108 0x1181 - VF610_PAD_PTE5__GPIO_110 0x1181 - VF610_PAD_PTE6__GPIO_111 0x1181 - /* GPO */ - VF610_PAD_PTE0__GPIO_105 0x1183 - VF610_PAD_PTE7__GPIO_112 0x1183 - /* RS485 Control */ - VF610_PAD_PTB8__GPIO_30 0x1183 - VF610_PAD_PTB9__GPIO_31 0x1183 - VF610_PAD_PTE8__GPIO_113 0x1183 - /* MPBUS MPB_EN */ - VF610_PAD_PTE28__GPIO_133 0x1183 - /* MISC */ - VF610_PAD_PTE10__GPIO_115 0x1183 - VF610_PAD_PTE11__GPIO_116 0x1183 - VF610_PAD_PTE17__GPIO_122 0x1183 - VF610_PAD_PTC30__GPIO_103 0x1183 - VF610_PAD_PTB0__GPIO_22 0x1181 - /* RESETINFO */ - VF610_PAD_PTE26__GPIO_131 0x1183 - VF610_PAD_PTD6__GPIO_85 0x1181 - VF610_PAD_PTE27__GPIO_132 0x1181 - VF610_PAD_PTE13__GPIO_118 0x1181 - VF610_PAD_PTE21__GPIO_126 0x1181 - VF610_PAD_PTE22__GPIO_127 0x1181 - /* EE_5V_EN */ - VF610_PAD_PTE18__GPIO_123 0x1183 - /* EE_5V_OC_N */ - VF610_PAD_PTE25__GPIO_130 0x1181 - >; - }; - - pinctrl_can0: can0grp { - fsl,pins = < - VF610_PAD_PTB14__CAN0_RX 0x1181 - VF610_PAD_PTB15__CAN0_TX 0x1182 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - VF610_PAD_PTB16__CAN1_RX 0x1181 - VF610_PAD_PTB17__CAN1_TX 0x1182 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi3: dspi3grp { - fsl,pins = < - VF610_PAD_PTD10__DSPI3_CS0 0x1181 - VF610_PAD_PTD11__DSPI3_SIN 0x1181 - VF610_PAD_PTD12__DSPI3_SOUT 0x1182 - VF610_PAD_PTD13__DSPI3_SCK 0x1181 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30dd - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - /* Heart bit LED */ - VF610_PAD_PTE12__GPIO_117 0x1183 - /* LEDS */ - VF610_PAD_PTE15__GPIO_120 0x1183 - VF610_PAD_PTA12__GPIO_5 0x1183 - VF610_PAD_PTA16__GPIO_6 0x1183 - VF610_PAD_PTE9__GPIO_114 0x1183 - VF610_PAD_PTE20__GPIO_125 0x1183 - VF610_PAD_PTE23__GPIO_128 0x1183 - VF610_PAD_PTE16__GPIO_121 0x1183 - >; - }; - - pinctrl_gpio_spi: pinctrl-gpio-spi { - fsl,pins = < - VF610_PAD_PTB18__GPIO_40 0x1183 - VF610_PAD_PTD10__GPIO_89 0x1183 - VF610_PAD_PTD12__GPIO_91 0x1183 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x34df - VF610_PAD_PTA23__I2C2_SDA 0x34df - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f - VF610_PAD_PTD1__QSPI0_A_CS0 0x397f - VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f - VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f - VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f - VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f - VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f - VF610_PAD_PTD8__QSPI0_B_CS0 0x397f - VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f - VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTB6__UART2_TX 0x21a2 - VF610_PAD_PTB7__UART2_RX 0x21a1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts deleted file mode 100644 index fb661e8a2dc6..000000000000 --- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2020 Toradex - */ - -/dts-v1/; -#include "vf610-colibri.dtsi" -#include "vf-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri VF61 on Colibri Evaluation Board"; - compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; -}; diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi deleted file mode 100644 index 607cec2df861..000000000000 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2014-2020 Toradex - */ - -#include "vf610.dtsi" -#include "vf-colibri.dtsi" - -/ { - model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <50000000>; -}; diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts deleted file mode 100644 index 703f375d7e24..000000000000 --- a/arch/arm/boot/dts/vf610-cosmic.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2013 Linaro Limited - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "PHYTEC Cosmic/Cosmic+ Board"; - compatible = "phytec,vf610-cosmic", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - enet_ext: enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>; - clock-names = "sxosc", "fxosc", "enet_ext"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&iomuxc { - vf610-cosmic { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h deleted file mode 100644 index b7b7322a2d1b..000000000000 --- a/arch/arm/boot/dts/vf610-pinfunc.h +++ /dev/null @@ -1,856 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_VF610_PINFUNC_H -#define __DTS_VF610_PINFUNC_H - -/* - * The pin function ID for VF610 is a tuple of: - * - */ - -#define ALT0 0x0 -#define ALT1 0x1 -#define ALT2 0x2 -#define ALT3 0x3 -#define ALT4 0x4 -#define ALT5 0x5 -#define ALT6 0x6 -#define ALT7 0x7 - - -#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 -#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 -#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 -#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 -#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 -#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 -#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 -#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 -#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 -#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 -#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 -#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 -#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 -#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 -#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 -#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 -#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 -#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 -#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 -#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 -#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 -#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 -#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 -#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 -#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 -#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 -#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 -#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 -#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 -#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 -#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 -#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 -#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 -#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 -#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 -#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 -#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 -#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 -#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 -#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 -#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 -#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 -#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 -#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 -#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 -#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 -#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 -#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 -#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 -#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 -#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 -#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 -#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 -#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 -#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 -#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 -#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 -#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 -#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 -#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 -#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 -#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 -#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 -#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 -#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 -#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 -#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 -#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 -#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 -#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 -#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 -#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 -#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 -#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 -#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 -#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 -#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 -#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 -#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 -#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 -#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 -#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 -#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 -#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 -#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 -#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 -#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 -#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 -#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 -#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 -#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 -#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 -#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 -#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 -#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 -#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 -#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 -#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 -#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 -#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 -#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 -#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 -#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 -#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 -#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 -#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 -#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 -#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 -#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 -#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 -#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 -#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 -#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 -#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 -#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 -#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 -#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 -#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 -#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 -#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 -#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 -#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 -#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 -#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 -#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 -#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 -#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 -#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 -#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 -#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 -#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 -#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 -#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 -#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 -#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 -#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 -#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 -#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 -#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 -#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 -#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 -#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 -#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 -#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 -#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 -#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 -#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 -#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 -#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 -#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 -#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 -#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 -#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 -#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 -#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 -#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 -#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 -#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 -#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 -#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 -#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 -#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 -#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 -#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 -#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 -#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 -#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 -#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 -#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 -#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 -#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 -#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 -#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 -#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 -#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 -#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 -#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 -#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 -#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 -#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 -#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 -#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 -#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 -#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 -#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 -#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 -#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 -#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 -#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 -#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 -#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 -#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 -#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 -#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 -#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 -#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 -#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 -#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 -#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 -#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 -#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 -#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 -#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 -#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 -#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 -#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 -#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 -#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 -#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 -#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 -#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 -#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 -#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 -#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 -#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 -#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 -#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 -#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 -#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 -#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 -#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 -#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 -#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 -#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 -#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 -#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 -#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 -#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 -#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 -#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 -#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 -#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 -#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 -#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 -#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 -#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 -#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 -#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 -#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 -#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 -#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 -#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 -#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 -#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 -#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 -#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 -#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 -#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 -#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 -#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 -#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 -#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 -#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 -#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 -#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 -#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 -#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 -#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 -#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 -#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 -#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 -#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 -#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 -#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 -#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 -#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 -#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 -#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 -#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 -#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 -#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 -#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 -#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 -#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 -#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 -#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 -#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 -#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 -#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 -#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 -#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 -#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 -#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 -#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 -#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 -#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 -#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 -#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 -#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 -#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 -#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 -#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 -#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 -#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 -#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 -#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 -#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 -#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 -#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 -#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 -#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 -#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 -#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 -#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 -#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 -#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 -#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 -#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 -#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 -#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 -#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 -#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 -#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 -#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 -#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 -#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 -#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 -#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 -#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 -#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 -#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 -#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 -#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 -#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 -#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 -#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 -#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 -#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 -#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 -#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 -#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 -#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 -#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 -#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 -#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 -#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 -#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 -#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 -#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 -#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 -#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 -#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 -#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 -#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 -#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 -#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 -#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 -#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 -#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 -#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 -#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 -#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 -#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 -#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 -#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 -#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 -#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 -#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 -#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 -#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 -#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 -#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 -#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 -#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 -#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 -#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 -#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 -#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 -#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 -#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 -#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 -#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 -#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 -#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 -#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 -#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 -#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 -#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 -#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 -#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 -#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 -#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 -#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 -#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 -#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 -#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 -#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 -#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 -#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 -#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 -#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 -#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 -#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 -#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 -#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 -#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 -#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 -#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 -#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 -#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 -#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 -#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 -#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 -#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 -#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 -#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 -#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 -#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 -#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 -#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 -#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 -#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 -#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 -#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 -#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 -#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 -#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 -#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 -#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 -#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 -#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 -#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 -#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 -#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 -#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 -#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 -#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 -#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 -#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 -#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 -#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 -#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 -#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 -#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 -#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 -#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 -#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 -#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 -#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 -#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 -#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 -#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 -#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 -#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 -#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 -#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 -#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 -#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 -#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 -#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 -#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 -#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 -#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 -#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 -#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 -#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 -#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 -#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 -#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 -#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 -#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 -#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 -#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 -#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 -#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 -#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 -#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 -#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 -#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 -#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 -#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 -#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 -#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 -#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 -#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 -#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 -#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 -#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 -#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 -#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 -#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 -#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 -#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 -#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 -#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 -#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 -#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 -#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 -#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 -#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 -#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 -#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 -#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 -#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 -#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 -#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 -#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 -#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 -#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 -#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 -#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 -#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 -#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 -#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 -#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 -#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 -#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 -#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 -#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 -#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 -#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 -#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 -#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 -#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 -#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 -#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 -#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 -#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 -#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 -#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 -#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 -#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 -#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 -#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 -#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 -#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 -#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 -#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 -#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 -#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 -#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 -#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 -#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 -#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 -#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 -#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 -#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 -#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 -#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 -#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 -#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 -#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 -#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 -#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 -#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 -#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 -#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 -#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 -#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 -#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 -#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 -#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 -#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 -#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 -#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 -#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 -#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 -#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 -#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 -#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 -#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 -#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 -#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 -#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 -#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 -#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 -#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 -#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 -#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 -#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 -#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 -#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 -#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 -#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 -#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 -#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 -#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 -#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 -#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 -#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 -#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 -#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 -#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 -#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 -#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 -#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 -#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 -#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 -#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 -#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 -#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 -#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 -#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 -#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 -#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 -#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 -#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 -#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 -#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 -#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 -#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 -#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 -#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 -#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 -#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 -#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 -#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 -#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 -#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 -#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 -#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 -#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 -#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 -#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 -#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 -#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 -#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 -#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 -#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 -#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 -#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 -#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 -#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 -#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 -#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 -#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 -#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 -#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 -#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 -#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 -#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 -#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 -#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 -#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 -#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 -#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 -#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 -#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 -#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 -#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 -#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 -#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 -#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 -#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 -#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 -#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 -#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 -#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 -#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 -#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 -#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 -#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 -#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 -#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 -#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 -#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 -#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 -#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 -#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 -#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 -#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 -#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 -#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 -#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 -#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 -#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 -#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 -#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 -#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 -#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 -#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 -#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 -#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 -#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 -#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 -#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 -#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 -#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 -#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 -#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 -#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 -#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 -#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 -#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 -#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 -#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 -#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 -#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 -#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 -#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 -#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 -#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 -#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 -#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 -#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 -#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 -#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 -#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 -#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 -#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 -#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 -#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 -#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 -#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 -#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 -#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 -#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 -#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 -#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 -#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 -#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 -#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 -#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 -#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 -#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 -#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 -#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 -#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 -#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 -#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 -#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 -#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 -#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 -#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 -#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 -#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 -#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 -#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 -#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 -#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 -#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 -#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 -#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 -#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 -#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 -#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 -#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 -#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 -#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 -#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 -#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 -#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 -#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 -#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 -#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 -#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 -#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 -#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 -#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 -#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 -#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 -#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 -#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 -#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 -#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 -#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 -#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 -#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 -#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 -#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 -#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 -#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 -#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 -#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 -#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 -#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 -#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 -#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 -#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 -#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 -#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 -#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 -#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 -#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 -#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 -#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 -#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 -#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 - -#endif diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts deleted file mode 100644 index 6c246d5aa032..000000000000 --- a/arch/arm/boot/dts/vf610-twr.dts +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "VF610 Tower Board"; - compatible = "fsl,vf610-twr", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - audio_ext: mclk_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - enet_ext: eth_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vcc_3v3_mcu: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; -}; - -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; - clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; - assigned-clocks = <&clks VF610_CLK_ENET_SEL>, - <&clks VF610_CLK_ENET_TS_SEL>; - assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, - <&clks VF610_CLK_ENET_EXT>; -}; - -&dspi0 { - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - status = "okay"; - - sflash: at26df081a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at26df081a"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec1 { - phy-mode = "rmii"; - phy-handle = <ðphy1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&clks VF610_CLK_SAI2>; - }; -}; - -&iomuxc { - vf610-twr { - pinctrl_adc0_ad5: adc0ad5grp { - fsl,pins = < - VF610_PAD_PTC30__ADC0_SE5 0xa1 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x30d3 - VF610_PAD_PTB15__I2C0_SDA 0x30d3 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD31__NF_IO15 0x28df - VF610_PAD_PTD30__NF_IO14 0x28df - VF610_PAD_PTD29__NF_IO13 0x28df - VF610_PAD_PTD28__NF_IO12 0x28df - VF610_PAD_PTD27__NF_IO11 0x28df - VF610_PAD_PTD26__NF_IO10 0x28df - VF610_PAD_PTD25__NF_IO9 0x28df - VF610_PAD_PTD24__NF_IO8 0x28df - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1582 - VF610_PAD_PTB1__FTM0_CH1 0x1582 - VF610_PAD_PTB2__FTM0_CH2 0x1582 - VF610_PAD_PTB3__FTM0_CH3 0x1582 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed - VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee - VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed - VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed - VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed - VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed - VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTB6__UART2_TX 0x21a2 - VF610_PAD_PTB7__UART2_RX 0x21a1 - >; - }; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; - status = "okay"; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts deleted file mode 100644 index 1a19aec8957b..000000000000 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 CFU1 Board"; - compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-fail { - label = "zii:red:fail"; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-status { - label = "zii:green:status"; - gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-debug-a { - label = "zii:green:debug_a"; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-debug-b { - label = "zii:green:debug_b"; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sff: sfp { - compatible = "sff,sff"; - pinctrl-0 = <&pinctrl_optical>; - pinctrl-names = "default"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - }; - - supply-voltage-monitor { - compatible = "iio-hwmon"; - io-channels = <&adc0 8>, /* 28VDC_IN */ - <&adc0 9>, /* +3.3V */ - <&adc1 8>, /* VCC_1V5 */ - <&adc1 9>; /* VCC_1V2 */ - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - /* - * Some CFU1s come with SPI-NOR chip DNPed, so we leave this - * node disabled by default and rely on bootloader to enable - * it when appropriate. - */ - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6085"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - reg = <0>; - eeprom-length = <512>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "eth_cu_1000_1"; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_2"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_1000_3"; - }; - - port@5 { - reg = <5>; - label = "eth_fc_1000_1"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff>; - }; - - port@6 { - reg = <6>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - label = "nvm"; - }; - - eeprom@54 { - compatible = "atmel,24c04"; - reg = <0x54>; - label = "nameplate"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - VF610_PAD_PTE3__GPIO_108 0x31c2 - VF610_PAD_PTE4__GPIO_109 0x31c2 - VF610_PAD_PTE5__GPIO_110 0x31c2 - VF610_PAD_PTE6__GPIO_111 0x31c2 - >; - }; - - pinctrl_optical: optical-grp { - fsl,pins = < - /* SFF SD input */ - VF610_PAD_PTE27__GPIO_132 0x3061 - - /* SFF Transmit disable output */ - VF610_PAD_PTE13__GPIO_118 0x3043 - >; - }; - - pinctrl_switch: switch-grp { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x3061 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts deleted file mode 100644 index 16b4e06c4efa..000000000000 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ /dev/null @@ -1,444 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 Development Board, Rev B"; - compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH - &gpio0 9 GPIO_ACTIVE_HIGH - &gpio0 24 GPIO_ACTIVE_HIGH - &gpio0 25 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - eeprom-length = <512>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-handle = <&switch0phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - switch0port5: port@5 { - reg = <5>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch1port6 - &switch2port9>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - switch0phy0: switch0phy0@0 { - reg = <0>; - interrupt-parent = <&switch0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - switch0phy1: switch1phy0@1 { - reg = <1>; - interrupt-parent = <&switch0>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - switch0phy2: switch1phy0@2 { - reg = <2>; - interrupt-parent = <&switch0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_gpio_switch1>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 1>; - interrupt-parent = <&gpio0>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - eeprom-length = <512>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&switch1phy0>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <2>; - label = "lan5"; - phy-handle = <&switch1phy2>; - }; - - switch1port5: port@5 { - reg = <5>; - label = "dsa"; - link = <&switch2port9>; - phy-mode = "1000base-x"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch1port6: port@6 { - reg = <6>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy0: switch1phy0@0 { - reg = <0>; - interrupt-parent = <&switch1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy1: switch1phy0@1 { - reg = <1>; - interrupt-parent = <&switch1>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy2: switch1phy0@2 { - reg = <2>; - interrupt-parent = <&switch1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - switch2: switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan6"; - phy-handle = <&switch2phy0>; - phy-mode = "sgmii"; - }; - - port@1 { - reg = <1>; - label = "lan7"; - phy-handle = <&switch2phy1>; - phy-mode = "sgmii"; - }; - - port@2 { - reg = <2>; - label = "lan8"; - phy-handle = <&switch2phy2>; - }; - - port@3 { - reg = <3>; - label = "optical3"; - - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 2 - GPIO_ACTIVE_HIGH>; - }; - }; - - port@4 { - reg = <4>; - label = "optical4"; - - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 3 - GPIO_ACTIVE_HIGH>; - }; - }; - - switch2port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "1000base-x"; - link = <&switch1port5 - &switch0port5>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch2phy0: phy@0 { - reg = <0>; - }; - switch2phy1: phy@1 { - reg = <1>; - }; - switch2phy2: phy@2 { - reg = <2>; - }; - }; - }; - }; - - mdio_mux_8: mdio@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spi-0 { - compatible = "spi-gpio"; - pinctrl-0 = <&pinctrl_gpio_spi0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW - &gpio1 8 GPIO_ACTIVE_HIGH>; - num-chipselects = <2>; - - flash@0 { - compatible = "m25p128", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - at93c46d@1 { - compatible = "atmel,at93c46d"; - pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; - pinctrl-names = "default"; - reg = <1>; - spi-max-frequency = <500000>; - spi-cs-high; - data-size = <16>; - select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&i2c0 { - gpio5: io-expander@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - - }; - - gpio6: io-expander@22 { - compatible = "nxp,pca9554"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9554_22>; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - i2c-mux@70 { - compatible = "nxp,pca9548"; - pinctrl-0 = <&pinctrl_i2c_mux_reset>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - sfp1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - sfp2: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - sfp3: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - sfp4: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - }; -}; - -&mdio1 { - clock-frequency = <5000000>; -}; - -&iomuxc { - pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { - fsl,pins = < - VF610_PAD_PTE27__GPIO_132 0x33e2 - >; - }; - - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { - fsl,pins = < - VF610_PAD_PTB22__GPIO_44 0x33e2 - VF610_PAD_PTB21__GPIO_43 0x33e2 - VF610_PAD_PTB20__GPIO_42 0x33e1 - VF610_PAD_PTB19__GPIO_41 0x33e2 - VF610_PAD_PTB18__GPIO_40 0x33e2 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x31c2 - VF610_PAD_PTA19__GPIO_9 0x31c2 - VF610_PAD_PTB2__GPIO_24 0x31c2 - VF610_PAD_PTB3__GPIO_25 0x31c2 - >; - }; - - pinctrl_pca9554_22: pinctrl-pca95540-22 { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts deleted file mode 100644 index 6f9878f124c4..000000000000 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 Development Board, Rev C"; - compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610"; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH - &gpio0 9 GPIO_ACTIVE_HIGH - &gpio0 25 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <65536>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@4 { - reg = <4>; - label = "lan4"; - phy-handle = <&switch0phy4>; - }; - - switch0port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xaui"; - link = <&switch1port10>; - - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: switch0phy@1 { - reg = <1>; - interrupt-parent = <&switch0>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch0phy2: switch0phy@2 { - reg = <2>; - interrupt-parent = <&switch0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch0phy3: switch0phy@3 { - reg = <3>; - interrupt-parent = <&switch0>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch0phy4: switch0phy@4 { - reg = <4>; - interrupt-parent = <&switch0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch1>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 1>; - eeprom-length = <65536>; - interrupt-parent = <&gpio0>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan5"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <2>; - label = "lan6"; - phy-handle = <&switch1phy2>; - }; - - port@3 { - reg = <3>; - label = "lan7"; - phy-handle = <&switch1phy3>; - }; - - port@4 { - reg = <4>; - label = "lan8"; - phy-handle = <&switch1phy4>; - }; - - port@9 { - reg = <9>; - label = "sff2"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff2>; - }; - - switch1port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xaui"; - link = <&switch0port10>; - - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy1: switch1phy@1 { - reg = <1>; - interrupt-parent = <&switch1>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy2: switch1phy@2 { - reg = <2>; - interrupt-parent = <&switch1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy3: switch1phy@3 { - reg = <3>; - interrupt-parent = <&switch1>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy4: switch1phy@4 { - reg = <4>; - interrupt-parent = <&switch1>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sff2: sff2 { - /* lower */ - compatible = "sff,sff"; - i2c-bus = <&sff2_i2c>; - los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - }; - - sff3: sff3 { - /* upper */ - compatible = "sff,sff"; - i2c-bus = <&sff3_i2c>; - los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&dspi0 { - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - status = "okay"; - spi-num-chipselects = <2>; - - flash@0 { - compatible = "m25p128", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - atzb-rf-233@1 { - compatible = "atmel,at86rf233"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctr_atzb_rf_233>; - - spi-max-frequency = <7500000>; - reg = <1>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpio3>; - xtal-trim = /bits/ 8 <0x06>; - - sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio6 10 GPIO_ACTIVE_LOW>; - - fsl,spi-cs-sck-delay = <180>; - fsl,spi-sck-cs-delay = <250>; - }; -}; - -&i2c0 { - /* - * U712 - * - * Exposed signals: - * P1 - WE2_CMD - * P2 - WE2_CLK - */ - gpio5: io-expander@18 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* - * U121 - * - * Exposed signals: - * I/O0 - ENET_SWR_EN - * I/O1 - ESW1_RESETn - * I/O2 - ARINC_RESET - * I/O3 - DD1_IO_RESET - * I/O4 - ESW2_RESETn - * I/O5 - ESW3_RESETn - * I/O6 - ESW4_RESETn - * I/O8 - TP909 - * I/O9 - FEM_SEL - * I/O10 - WIFI_RESETn - * I/O11 - PHY_RSTn - * I/O12 - OPT1_SD - * I/O13 - OPT2_SD - * I/O14 - OPT1_TX_DIS - * I/O15 - OPT2_TX_DIS - */ - gpio6: sx1503@20 { - compatible = "semtech,sx1503q"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sx1503_20>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - interrupt-controller; - }; - - /* - * U715 - * - * Exposed signals: - * IO0 - WE1_CLK - * IO1 - WE1_CMD - */ - gpio7: io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - }; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - read-only; - }; -}; - -&i2c2 { - i2c-mux@70 { - compatible = "nxp,pca9548"; - pinctrl-0 = <&pinctrl_i2c_mux_reset>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - sff2_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - sff3_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&gpio0 { - eth0_intrp { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - input; - line-name = "sx1503-irq"; - }; -}; - -&gpio3 { - eth0_intrp { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - input; - line-name = "eth0-intrp"; - }; -}; - -&fec0 { - mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0_phy_int>; - - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reg = <0>; - }; - }; -}; - -&iomuxc { - pinctr_atzb_rf_233: pinctrl-atzb-rf-233 { - fsl,pins = < - VF610_PAD_PTB2__GPIO_24 0x31c2 - VF610_PAD_PTE27__GPIO_132 0x33e2 - >; - }; - - - pinctrl_sx1503_20: pinctrl-sx1503-20 { - fsl,pins = < - VF610_PAD_PTB1__GPIO_23 0x219d - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x31c2 - VF610_PAD_PTA19__GPIO_9 0x31c2 - VF610_PAD_PTB3__GPIO_25 0x31c2 - >; - }; - - pinctrl_fec0_phy_int: pinctrl-fec0-phy-int { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi deleted file mode 100644 index ce5e52896b19..000000000000 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf610.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_usb_vbus>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 6 0>; - }; - - supply-voltage-monitor { - compatible = "iio-hwmon"; - io-channels = <&adc0 8>, /* VCC_1V5 */ - <&adc0 9>, /* VCC_1V8 */ - <&adc1 8>, /* VCC_1V0 */ - <&adc1 9>; /* VCC_1V2 */ - }; -}; - -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; - - ds1682@6b { - compatible = "dallas,ds1682"; - reg = <0x6b>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - status = "okay"; - - /* - * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR - * modes, so, spi-max-frequency is limited to 90MHz - */ - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <90000000>; - spi-rx-bus-width = <4>; - reg = <0>; - m25p,fast-read; - }; - - flash@2 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <90000000>; - spi-rx-bus-width = <4>; - reg = <2>; - m25p,fast-read; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - vbus-supply = <&usb0_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&tempsensor { - io-channels = <&adc0 16>; -}; - -&iomuxc { - pinctrl_adc0_ad5: adc0ad5grp { - fsl,pins = < - VF610_PAD_PTC30__ADC0_SE5 0x00a1 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi2: dspi2grp { - fsl,pins = < - VF610_PAD_PTD31__DSPI2_CS1 0x1182 - VF610_PAD_PTD30__DSPI2_CS0 0x1182 - VF610_PAD_PTD29__DSPI2_SIN 0x1181 - VF610_PAD_PTD28__DSPI2_SOUT 0x1182 - VF610_PAD_PTD27__DSPI2_SCK 0x1182 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { - fsl,pins = < - VF610_PAD_PTB22__GPIO_44 0x33e2 - VF610_PAD_PTB21__GPIO_43 0x33e2 - VF610_PAD_PTB20__GPIO_42 0x33e1 - VF610_PAD_PTB19__GPIO_41 0x33e2 - VF610_PAD_PTB18__GPIO_40 0x33e2 - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTB5__GPIO_27 0x219d - >; - }; - - pinctrl_gpio_switch1: pinctrl-gpio-switch1 { - fsl,pins = < - VF610_PAD_PTB4__GPIO_26 0x219d - >; - }; - - pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { - fsl,pins = < - VF610_PAD_PTE14__GPIO_119 0x31c2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c0_gpio: i2c0grp-gpio { - fsl,pins = < - VF610_PAD_PTB14__GPIO_36 0x31c2 - VF610_PAD_PTB15__GPIO_37 0x31c2 - >; - }; - - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x37ff - VF610_PAD_PTA23__I2C2_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD20__GPIO_74 0x31c2 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 - VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 - VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 - VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 - VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 - VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 - VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 - VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 - VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD23__UART2_TX 0x21a2 - VF610_PAD_PTD22__UART2_RX 0x21a1 - >; - }; - - pinctrl_usb_vbus: pinctrl-usb-vbus { - fsl,pins = < - VF610_PAD_PTA16__GPIO_6 0x31c2 - >; - }; - - pinctrl_usb0_host: usb0-host-grp { - fsl,pins = < - VF610_PAD_PTD6__GPIO_85 0x0062 - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts deleted file mode 100644 index df1335492a19..000000000000 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ /dev/null @@ -1,876 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright (C) 2016-2018 Zodiac Inflight Innovations - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SCU4 AIB"; - compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio4 4 GPIO_ACTIVE_HIGH - &gpio4 5 GPIO_ACTIVE_HIGH - &gpio3 30 GPIO_ACTIVE_HIGH - &gpio3 31 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "aib2main_1"; - }; - - port@2 { - reg = <2>; - label = "aib2main_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_1000_5"; - }; - - port@4 { - reg = <4>; - label = "eth_cu_1000_6"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_4"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_7"; - }; - - port@7 { - reg = <7>; - label = "modem_pic"; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - switch0port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch1port10 - &switch3port10 - &switch2port10>; - - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch1@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 1>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "eth_cu_1000_3"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_100_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_100_3"; - }; - - switch1port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch3port10 - &switch2port10>; - - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - - switch1port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch0port10>; - - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - switch2: switch2@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 2>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - label = "eth_fc_1000_2"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff1>; - }; - - port@3 { - reg = <3>; - label = "eth_fc_1000_3"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff2>; - }; - - port@4 { - reg = <4>; - label = "eth_fc_1000_4"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff3>; - }; - - port@5 { - reg = <5>; - label = "eth_fc_1000_5"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff4>; - }; - - port@6 { - reg = <6>; - label = "eth_fc_1000_6"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff5>; - }; - - port@7 { - reg = <7>; - label = "eth_fc_1000_7"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff6>; - }; - - port@9 { - reg = <9>; - label = "eth_fc_1000_1"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff0>; - }; - - switch2port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "2500base-x"; - link = <&switch3port9 - &switch1port9 - &switch0port10>; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - }; - }; - }; - - mdio_mux_8: mdio@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - - switch3: switch3@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 3>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - label = "eth_fc_1000_8"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff7>; - }; - - port@3 { - reg = <3>; - label = "eth_fc_1000_9"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff8>; - }; - - port@4 { - reg = <4>; - label = "eth_fc_1000_10"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff9>; - }; - - switch3port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "2500base-x"; - link = <&switch2port10>; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - switch3port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch1port9 - &switch0port10>; - - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - }; - }; - }; - }; - - sff0: sff0 { - compatible = "sff,sff"; - i2c-bus = <&sff0_i2c>; - los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - }; - - sff1: sff1 { - compatible = "sff,sff"; - i2c-bus = <&sff1_i2c>; - los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - }; - - sff2: sff2 { - compatible = "sff,sff"; - i2c-bus = <&sff2_i2c>; - los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - }; - - sff3: sff3 { - compatible = "sff,sff"; - i2c-bus = <&sff3_i2c>; - los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - }; - - sff4: sff4 { - compatible = "sff,sff"; - i2c-bus = <&sff4_i2c>; - los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - }; - - sff5: sff5 { - compatible = "sff,sff"; - i2c-bus = <&sff5_i2c>; - los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; - }; - - sff6: sff6 { - compatible = "sff,sff"; - i2c-bus = <&sff6_i2c>; - los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; - }; - - sff7: sff7 { - compatible = "sff,sff"; - i2c-bus = <&sff7_i2c>; - los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; - }; - - sff8: sff8 { - compatible = "sff,sff"; - i2c-bus = <&sff8_i2c>; - los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - }; - - sff9: sff9 { - compatible = "sff,sff"; - i2c-bus = <&sff9_i2c>; - los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dspi0 { - pinctrl-0 = <&pinctrl_dspi0>; - pinctrl-names = "default"; - bus-num = <0>; - status = "okay"; - - adc@5 { - compatible = "holt,hi8435"; - reg = <5>; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <1000000>; - }; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-1"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sd; - no-sdio; - keep-power-in-suspend; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio5: io-expander@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio6: io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - temp-sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; - - elapsed-time-recorder@6b { - compatible = "dallas,ds1682"; - reg = <0x6b>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; - - adc@4a { - compatible = "adi,adt7411"; - reg = <0x4a>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - gpio9: io-expander@20 { - compatible = "semtech,sx1503q"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sx1503_20>; - #gpio-cells = <2>; - reg = <0x20>; - gpio-controller; - interrupt-parent = <&gpio1>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; - - temp-sensor@4e { - compatible = "national,lm75"; - reg = <0x4e>; - }; - - temp-sensor@4f { - compatible = "national,lm75"; - reg = <0x4f>; - }; - - gpio7: io-expander@23 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x23>; - }; - - adc@4a { - compatible = "adi,adt7411"; - reg = <0x4a>; - }; - - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - sff0_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - sff1_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - sff2_i2c: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - sff3_i2c: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - sff4_i2c: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - }; - - i2c-mux@71 { - compatible = "nxp,pca9548"; - pinctrl-names = "default"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - sff5_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - sff6_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - sff7_i2c: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - sff8_i2c: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - sff9_i2c: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - linux,rs485-enabled-at-boot-time; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - linux,rs485-enabled-at-boot-time; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB13__DSPI0_CS4 0x1182 - VF610_PAD_PTB12__DSPI0_CS5 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_dspi2: dspi2gpio { - fsl,pins = < - VF610_PAD_PTD30__GPIO_64 0x33e2 - VF610_PAD_PTD29__GPIO_65 0x33e1 - VF610_PAD_PTD28__GPIO_66 0x33e2 - VF610_PAD_PTD27__GPIO_67 0x33e2 - VF610_PAD_PTD26__GPIO_68 0x31c2 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x37ff - VF610_PAD_PTA23__I2C2_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTB26__GPIO_96 0x31c2 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTE27__GPIO_132 0x31c2 - VF610_PAD_PTE28__GPIO_133 0x31c2 - VF610_PAD_PTE21__GPIO_126 0x31c2 - VF610_PAD_PTE22__GPIO_127 0x31c2 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 - >; - }; - - pinctrl_sx1503_20: pinctrl-sx1503-20 { - fsl,pins = < - VF610_PAD_PTD31__GPIO_63 0x219d - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts deleted file mode 100644 index 1461804ecaea..000000000000 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ /dev/null @@ -1,379 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Device tree file for ZII's SPB4 board - * - * SPB - Seat Power Box - * - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SPB4 Board"; - compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - supply-voltage-monitor { - compatible = "iio-hwmon"; - io-channels = <&adc0 8>, /* 28V_SW */ - <&adc0 9>, /* +3.3V */ - <&adc1 8>, /* VCC_1V5 */ - <&adc1 9>; /* VCC_1V2 */ - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - eeprom-length = <65536>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_1"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_1000_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_1000_3"; - }; - - port@4 { - reg = <4>; - label = "eth_cu_1000_4"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_5"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_6"; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - label = "nameplate"; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&wdoga5 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA30__UART3_TX 0x21a2 - VF610_PAD_PTA31__UART3_RX 0x21a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts deleted file mode 100644 index 463c2452b9b7..000000000000 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Device tree file for ZII's SSMB DTU board - * - * SSMB - SPU3 Switch Management Board - * DTU - Digital Tapping Unit - * - * Copyright (C) 2015-2019 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SSMB DTU Board"; - compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - supply-voltage-monitor { - compatible = "iio-hwmon"; - io-channels = <&adc0 8>, /* 12V_MAIN */ - <&adc0 9>, /* +3.3V */ - <&adc1 8>, /* VCC_1V5 */ - <&adc1 9>; /* VCC_1V2 */ - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - eeprom-length = <65536>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "eth_cu_100_3"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_4"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_5"; - }; - - port@8 { - reg = <8>; - label = "eth_cu_1000_1"; - }; - - port@9 { - reg = <9>; - label = "eth_cu_1000_2"; - phy-handle = <&phy9>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - }; - - mdio1 { - compatible = "marvell,mv88e6xxx-mdio-external"; - #address-cells = <1>; - #size-cells = <0>; - - phy9: phy9@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - pinctrl-0 = <&pinctrl_gpio_phy9>; - pinctrl-names = "default"; - interrupt-parent = <&gpio2>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - reg = <0>; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio6: gpio-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* On SSMB */ - temperature-sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - /* On DSB */ - temperature-sensor@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - label = "nameplate"; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_phy9: pinctrl-gpio-phy9 { - fsl,pins = < - VF610_PAD_PTB24__GPIO_94 0x219d - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts deleted file mode 100644 index f5ae0d5de315..000000000000 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Device tree file for ZII's SSMB SPU3 board - * - * SSMB - SPU3 Switch Management Board - * SPU - Seat Power Unit - * - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SSMB SPU3 Board"; - compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - supply-voltage-monitor { - compatible = "iio-hwmon"; - io-channels = <&adc0 8>, /* 12V_MAIN */ - <&adc0 9>, /* +3.3V */ - <&adc1 8>, /* VCC_1V5 */ - <&adc1 9>; /* VCC_1V2 */ - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - /* - * Some SPU3s come with SPI-NOR chip DNPed, so we leave this - * node disabled by default and rely on bootloader to enable - * it when appropriate. - */ - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - eeprom-length = <65536>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-mode = "rmii"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_1"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_1000_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_1000_3"; - }; - - port@4 { - reg = <4>; - label = "eth_cu_1000_4"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_5"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_6"; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio6: io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - label = "nameplate"; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; - - mcu { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&wdoga5 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; -}; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi deleted file mode 100644 index 2fba923821d0..000000000000 --- a/arch/arm/boot/dts/vf610.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include "vf500.dtsi" - -&a5_cpu { - next-level-cache = <&L2>; -}; - -&aips0 { - L2: cache-controller@40006000 { - compatible = "arm,pl310-cache"; - reg = <0x40006000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - }; -}; diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts deleted file mode 100644 index 2c2db47af441..000000000000 --- a/arch/arm/boot/dts/vf610m4-colibri.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Device tree for Colibri VF61 Cortex-M4 support - * - * Copyright (C) 2015 Stefan Agner - */ - -/dts-v1/; -#include "vf610m4.dtsi" - -/ { - model = "VF610 Cortex-M4"; - compatible = "fsl,vf610m4"; - - chosen { - bootargs = "clk_ignore_unused init=/linuxrc rw"; - stdout-path = "serial2:115200"; - }; - - memory@8c000000 { - device_type = "memory"; - reg = <0x8c000000 0x3000000>; - }; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&gpio3 { - status = "disabled"; -}; - -&gpio4 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/vf610m4-cosmic.dts b/arch/arm/boot/dts/vf610m4-cosmic.dts deleted file mode 100644 index f7474c11aabd..000000000000 --- a/arch/arm/boot/dts/vf610m4-cosmic.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Device tree for Cosmic+ VF6xx Cortex-M4 support - * - * Copyright (C) 2015 - * - * Based on vf610m4 Colibri - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610m4.dtsi" - -/ { - model = "VF610 Cortex-M4"; - compatible = "fsl,vf610m4"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&gpio3 { - status = "disabled"; -}; - -&gpio4 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&iomuxc { - vf610-cosmic { - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi deleted file mode 100644 index 76bbfd5e32b6..000000000000 --- a/arch/arm/boot/dts/vf610m4.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Device tree for VF6xx Cortex-M4 support - * - * Copyright (C) 2015 Stefan Agner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include "vfxxx.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; -}; - -&mscm_ir { - interrupt-parent = <&nvic>; -}; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi deleted file mode 100644 index 3f7dc787938e..000000000000 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ /dev/null @@ -1,751 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include "vf610-pinfunc.h" -#include -#include -#include - -/ { - aliases { - can0 = &can0; - can1 = &can1; - ethernet0 = &fec0; - ethernet1 = &fec1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - usbphy0 = &usbphy0; - usbphy1 = &usbphy1; - }; - - fxosc: fxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - sxosc: sxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&src>; - offset = <0x0>; - mask = <0x1000>; - }; - - tempsensor: iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 16>, <&adc1 16>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&mscm_ir>; - ranges; - - aips0: bus@40000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x00070000>; - ranges; - - mscm_cpucfg: cpucfg@40001000 { - compatible = "fsl,vf610-mscm-cpucfg", "syscon"; - reg = <0x40001000 0x800>; - }; - - mscm_ir: interrupt-controller@40001800 { - compatible = "fsl,vf610-mscm-ir"; - reg = <0x40001800 0x400>; - fsl,cpucfg = <&mscm_cpucfg>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - edma0: dma-controller@40018000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40018000 0x2000>, - <0x40024000 0x1000>, - <0x40025000 0x1000>; - dma-channels = <32>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, - <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX0>, - <&clks VF610_CLK_DMAMUX1>; - status = "disabled"; - }; - - can0: can@40020000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x40020000 0x4000>; - interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN0>, - <&clks VF610_CLK_FLEXCAN0>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart0: serial@40027000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40027000 0x1000>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART0>; - clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart1: serial@40028000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40028000 0x1000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; - dmas = <&edma0 0 4>, - <&edma0 0 5>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart2: serial@40029000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40029000 0x1000>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART2>; - clock-names = "ipg"; - dmas = <&edma0 0 6>, - <&edma0 0 7>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart3: serial@4002a000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x4002a000 0x1000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART3>; - clock-names = "ipg"; - dmas = <&edma0 0 8>, - <&edma0 0 9>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - dspi0: spi@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <6>; - dmas = <&edma1 1 12>, - <&edma1 1 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - dspi1: spi@4002d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002d000 0x1000>; - interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI1>; - clock-names = "dspi"; - spi-num-chipselects = <4>; - dmas = <&edma1 1 14>, - <&edma1 1 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai0: sai@4002f000 { - compatible = "fsl,vf610-sai"; - reg = <0x4002f000 0x1000>; - interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI0>, - <&clks VF610_CLK_SAI0_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&edma0 0 16>, <&edma0 0 17>; - status = "disabled"; - }; - - sai1: sai@40030000 { - compatible = "fsl,vf610-sai"; - reg = <0x40030000 0x1000>; - interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI1>, - <&clks VF610_CLK_SAI1_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&edma0 0 18>, <&edma0 0 19>; - status = "disabled"; - }; - - sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI2>, - <&clks VF610_CLK_SAI2_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&edma0 0 20>, <&edma0 0 21>; - status = "disabled"; - }; - - sai3: sai@40032000 { - compatible = "fsl,vf610-sai"; - reg = <0x40032000 0x1000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI3>, - <&clks VF610_CLK_SAI3_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&edma0 1 8>, <&edma0 1 9>; - status = "disabled"; - }; - - pit: pit@40037000 { - compatible = "fsl,vf610-pit"; - reg = <0x40037000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_PIT>; - clock-names = "pit"; - }; - - pwm0: pwm@40038000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40038000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM0>, - <&clks VF610_CLK_FTM0_EXT_SEL>, - <&clks VF610_CLK_FTM0_FIX_SEL>, - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; - status = "disabled"; - }; - - pwm1: pwm@40039000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40039000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM1>, - <&clks VF610_CLK_FTM1_EXT_SEL>, - <&clks VF610_CLK_FTM1_FIX_SEL>, - <&clks VF610_CLK_FTM1_EXT_FIX_EN>; - status = "disabled"; - }; - - adc0: adc@4003b000 { - compatible = "fsl,vf610-adc"; - reg = <0x4003b000 0x1000>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ADC0>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - }; - - tcon0: timing-controller@4003d000 { - compatible = "fsl,vf610-tcon"; - reg = <0x4003d000 0x1000>; - clocks = <&clks VF610_CLK_TCON0>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdoga5: watchdog@4003e000 { - compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; - reg = <0x4003e000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_WDT>; - status = "disabled"; - }; - - qspi0: spi@40044000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - iomuxc: iomuxc@40048000 { - compatible = "fsl,vf610-iomuxc"; - reg = <0x40048000 0x1000>; - }; - - gpio0: gpio@40049000 { - compatible = "fsl,vf610-gpio"; - reg = <0x40049000 0x1000 0x400ff000 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; - }; - - gpio1: gpio@4004a000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004a000 0x1000 0x400ff040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; - }; - - gpio2: gpio@4004b000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004b000 0x1000 0x400ff080 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 64 32>; - }; - - gpio3: gpio@4004c000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 96 32>; - }; - - gpio4: gpio@4004d000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004d000 0x1000 0x400ff100 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 128 7>; - }; - - anatop: anatop@40050000 { - compatible = "fsl,vf610-anatop", "syscon"; - reg = <0x40050000 0x400>; - }; - - usbphy0: usbphy@40050800 { - compatible = "fsl,vf610-usbphy"; - reg = <0x40050800 0x400>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBPHY0>; - fsl,anatop = <&anatop>; - status = "disabled"; - }; - - usbphy1: usbphy@40050c00 { - compatible = "fsl,vf610-usbphy"; - reg = <0x40050c00 0x400>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - status = "disabled"; - }; - - dcu0: dcu@40058000 { - compatible = "fsl,vf610-dcu"; - reg = <0x40058000 0x1200>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DCU0>, - <&clks VF610_CLK_DCU0_DIV>; - clock-names = "dcu", "pix"; - fsl,tcon = <&tcon0>; - status = "disabled"; - }; - - i2c0: i2c@40066000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40066000 0x1000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C0>; - clock-names = "ipg"; - dmas = <&edma0 0 50>, - <&edma0 0 51>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - i2c1: i2c@40067000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40067000 0x1000>; - interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C1>; - clock-names = "ipg"; - dmas = <&edma0 0 52>, - <&edma0 0 53>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - clocks = <&sxosc>, <&fxosc>; - clock-names = "sxosc", "fxosc"; - #clock-cells = <1>; - }; - - usbdev0: usb@40034000 { - compatible = "fsl,vf610-usb", "fsl,imx27-usb"; - reg = <0x40034000 0x800>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBC0>; - fsl,usbphy = <&usbphy0>; - fsl,usbmisc = <&usbmisc0 0>; - dr_mode = "peripheral"; - status = "disabled"; - }; - - usbmisc0: usb@40034800 { - #index-cells = <1>; - compatible = "fsl,vf610-usbmisc"; - reg = <0x40034800 0x200>; - clocks = <&clks VF610_CLK_USBC0>; - status = "disabled"; - }; - - src: src@4006e000 { - compatible = "fsl,vf610-src", "syscon"; - reg = <0x4006e000 0x1000>; - interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips1: bus@40080000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40080000 0x0007f000>; - ranges; - - edma1: dma-controller@40098000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40098000 0x2000>, - <0x400a1000 0x1000>, - <0x400a2000 0x1000>; - dma-channels = <32>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX2>, - <&clks VF610_CLK_DMAMUX3>; - status = "disabled"; - }; - - ocotp: ocotp@400a5000 { - compatible = "fsl,vf610-ocotp", "syscon"; - reg = <0x400a5000 0x1000>; - clocks = <&clks VF610_CLK_OCOTP>; - }; - - snvs0: snvs@400a7000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x400a7000 0x2000>; - - snvsrtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs0>; - offset = <0x34>; - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SNVS>; - clock-names = "snvs-rtc"; - }; - }; - - uart4: serial@400a9000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400a9000 0x1000>; - interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART4>; - clock-names = "ipg"; - status = "disabled"; - }; - - uart5: serial@400aa000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400aa000 0x1000>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART5>; - clock-names = "ipg"; - status = "disabled"; - }; - - dspi2: spi@400ac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x400ac000 0x1000>; - interrupts = <69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI2>; - clock-names = "dspi"; - spi-num-chipselects = <2>; - dmas = <&edma1 0 10>, - <&edma1 0 11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - dspi3: spi@400ad000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x400ad000 0x1000>; - interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI3>; - clock-names = "dspi"; - spi-num-chipselects = <2>; - dmas = <&edma1 0 12>, - <&edma1 0 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - adc1: adc@400bb000 { - compatible = "fsl,vf610-adc"; - reg = <0x400bb000 0x1000>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ADC1>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - }; - - esdhc0: esdhc@400b1000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b1000 0x1000>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC0>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc1: esdhc@400b2000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b2000 0x1000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC1>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - usbh1: usb@400b4000 { - compatible = "fsl,vf610-usb", "fsl,imx27-usb"; - reg = <0x400b4000 0x800>; - interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBC1>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc1: usb@400b4800 { - #index-cells = <1>; - compatible = "fsl,vf610-usbmisc"; - reg = <0x400b4800 0x200>; - clocks = <&clks VF610_CLK_USBC1>; - status = "disabled"; - }; - - ftm: ftm@400b8000 { - compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000 0x400b9000 0x1000>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "ftm-evt", "ftm-src", - "ftm-evt-counter-en", "ftm-src-counter-en"; - clocks = <&clks VF610_CLK_FTM2>, - <&clks VF610_CLK_FTM3>, - <&clks VF610_CLK_FTM2_EXT_FIX_EN>, - <&clks VF610_CLK_FTM3_EXT_FIX_EN>; - status = "disabled"; - }; - - qspi1: spi@400c4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI1_EN>, - <&clks VF610_CLK_QSPI1>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - dac0: dac@400cc000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cc000 1000>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC0>; - status = "disabled"; - }; - - dac1: dac@400cd000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cd000 1000>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC1>; - status = "disabled"; - }; - - fec0: ethernet@400d0000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d0000 0x1000>; - interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - fec1: ethernet@400d1000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d1000 0x1000>; - interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - can1: can@400d4000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x400d4000 0x4000>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN1>, - <&clks VF610_CLK_FLEXCAN1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - nfc: nand@400e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-nfc"; - reg = <0x400e0000 0x4000>; - interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_NFC>; - clock-names = "nfc"; - status = "disabled"; - }; - - i2c2: i2c@400e6000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x400e6000 0x1000>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C2>; - clock-names = "ipg"; - dmas = <&edma0 1 36>, - <&edma0 1 37>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - i2c3: i2c@400e7000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x400e7000 0x1000>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C3>; - clock-names = "ipg"; - dmas = <&edma0 1 38>, - <&edma0 1 39>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - crypto: crypto@400f0000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x400f0000 0x9000>; - ranges = <0 0x400f0000 0x9000>; - clocks = <&clks VF610_CLK_CAAM>; - clock-names = "ipg"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts deleted file mode 100644 index e9f55bd30bd4..000000000000 --- a/arch/arm/boot/dts/vt8500-bv07.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "vt8500.dtsi" - -/ { - model = "Benign BV07 Netbook"; -}; - -&fb { - bits-per-pixel = <16>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi deleted file mode 100644 index b7e09eff5bb2..000000000000 --- a/arch/arm/boot/dts/vt8500.dtsi +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * vt8500.dtsi - Device tree file for VIA VT8500 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "via,vt8500"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc>; - - intc: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "via,vt8500-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <3>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <4>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <43>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; - - fb: fb@d8050800 { - compatible = "via,vt8500-fb"; - reg = <0xd800e400 0x400>; - interrupts = <12>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/arch/arm/boot/dts/vt8500/Makefile b/arch/arm/boot/dts/vt8500/Makefile new file mode 100644 index 000000000000..255f4403af91 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VT8500) += \ + vt8500-bv07.dtb \ + wm8505-ref.dtb \ + wm8650-mid.dtb \ + wm8750-apc8750.dtb \ + wm8850-w70v2.dtb diff --git a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts new file mode 100644 index 000000000000..e9f55bd30bd4 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook + * + * Copyright (C) 2012 Tony Prisk + */ + +/dts-v1/; +/include/ "vt8500.dtsi" + +/ { + model = "Benign BV07 Netbook"; +}; + +&fb { + bits-per-pixel = <16>; + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <0>; /* unused but required */ + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi new file mode 100644 index 000000000000..b7e09eff5bb2 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/vt8500.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * vt8500.dtsi - Device tree file for VIA VT8500 SoC + * + * Copyright (C) 2012 Tony Prisk + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "via,vt8500"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc>; + + intc: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "via,vt8500-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <1>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <2>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <3>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <4>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <43>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <43>; + }; + + fb: fb@d8050800 { + compatible = "via,vt8500-fb"; + reg = <0xd800e400 0x400>; + interrupts = <12>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart0: serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + status = "disabled"; + }; + + uart1: serial@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + status = "disabled"; + }; + + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + status = "disabled"; + }; + + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + status = "disabled"; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + ethernet@d8004000 { + compatible = "via,vt8500-rhine"; + reg = <0xd8004000 0x100>; + interrupts = <10>; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8505-ref.dts b/arch/arm/boot/dts/vt8500/wm8505-ref.dts new file mode 100644 index 000000000000..2d77c087676e --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8505-ref.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook + * + * Copyright (C) 2012 Tony Prisk + */ + +/dts-v1/; +/include/ "wm8505.dtsi" + +/ { + model = "Wondermedia WM8505 Netbook"; +}; + +&fb { + bits-per-pixel = <32>; + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <0>; /* unused but required */ + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi new file mode 100644 index 000000000000..168cd12b07bc --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC + * + * Copyright (C) 2012 Tony Prisk + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "wm,wm8505"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "wm,wm8505-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + pllc: pllc { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <1>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <2>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <3>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <4>; + }; + + clkuart4: uart4 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <22>; + }; + + clkuart5: uart5 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <23>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x328>; + divisor-mask = <0x3f>; + enable-reg = <0x254>; + enable-bit = <18>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007100 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007100 0x200>; + interrupts = <1>; + }; + + uhci@d8007300 { + compatible = "platform-uhci"; + reg = <0xd8007300 0x200>; + interrupts = <0>; + }; + + fb: fb@d8050800 { + compatible = "wm,wm8505-fb"; + reg = <0xd8050800 0x200>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart0: serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + status = "disabled"; + }; + + uart1: serial@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + status = "disabled"; + }; + + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + status = "disabled"; + }; + + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + status = "disabled"; + }; + + uart4: serial@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <31>; + clocks = <&clkuart4>; + status = "disabled"; + }; + + uart5: serial@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <30>; + clocks = <&clkuart5>; + status = "disabled"; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x400>; + interrupts = <20>, <21>; + clocks = <&clksdhc>; + bus-width = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8650-mid.dts b/arch/arm/boot/dts/vt8500/wm8650-mid.dts new file mode 100644 index 000000000000..f6a42149a0a0 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8650-mid.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet + * + * Copyright (C) 2012 Tony Prisk + */ + +/dts-v1/; +/include/ "wm8650.dtsi" + +/ { + model = "Wondermedia WM8650-MID Tablet"; +}; + +&fb { + bits-per-pixel = <16>; + + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <0>; /* unused but required */ + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi new file mode 100644 index 000000000000..bc057b6f7d16 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC + * + * Copyright (C) 2012 Tony Prisk + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "wm,wm8650"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "wm,wm8650-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <1>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <2>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x328>; + divisor-mask = <0x3f>; + enable-reg = <0x254>; + enable-bit = <18>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <43>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <43>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x400>; + interrupts = <20>, <21>; + clocks = <&clksdhc>; + bus-width = <4>; + sdon-inverted; + }; + + fb: fb@d8050800 { + compatible = "wm,wm8505-fb"; + reg = <0xd8050800 0x200>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart0: serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + status = "disabled"; + }; + + uart1: serial@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + status = "disabled"; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + ethernet@d8004000 { + compatible = "via,vt8500-rhine"; + reg = <0xd8004000 0x100>; + interrupts = <10>; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts b/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts new file mode 100644 index 000000000000..136e812bc1e4 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8750-apc8750.dts + * - Device tree file for VIA APC8750 + * + * Copyright (C) 2012 Tony Prisk + */ + +/dts-v1/; +/include/ "wm8750.dtsi" + +/ { + model = "VIA APC8750"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&i2c>; + + i2c: i2c { + wm,pins = <168 169 170 171>; + wm,function = <2>; /* alt */ + wm,pull = <2>; /* pull-up */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi new file mode 100644 index 000000000000..33aeb37491f4 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC + * + * Copyright (C) 2012 Tony Prisk + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "wm,wm8750"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm1176jzf"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "wm,wm8750-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x20C>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <24>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <25>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; + + clkuart4: uart4 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <28>; + }; + + clkuart5: uart5 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <29>; + }; + + clkpwm: pwm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + enable-reg = <0x250>; + enable-bit = <17>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x330>; + divisor-mask = <0x3f>; + enable-reg = <0x250>; + enable-bit = <0>; + }; + + clki2c0: i2c0clk { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x3A0>; + enable-reg = <0x250>; + enable-bit = <8>; + }; + + clki2c1: i2c1clk { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x3A4>; + enable-reg = <0x250>; + enable-bit = <9>; + }; + }; + }; + + pwm: pwm@d8220000 { + #pwm-cells = <3>; + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x100>; + clocks = <&clkpwm>; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <26>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <26>; + }; + + uhci@d8008d00 { + compatible = "platform-uhci"; + reg = <0xd8008d00 0x200>; + interrupts = <26>; + }; + + uart0: serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + status = "disabled"; + }; + + uart1: serial@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + status = "disabled"; + }; + + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + status = "disabled"; + }; + + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + status = "disabled"; + }; + + uart4: serial@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <30>; + clocks = <&clkuart4>; + status = "disabled"; + }; + + uart5: serial@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <43>; + clocks = <&clkuart5>; + status = "disabled"; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20 21>; + clocks = <&clksdhc>; + bus-width = <4>; + sdon-inverted; + }; + + i2c_0: i2c@d8280000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8280000 0x1000>; + interrupts = <19>; + clocks = <&clki2c0>; + clock-frequency = <400000>; + }; + + i2c_1: i2c@d8320000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8320000 0x1000>; + interrupts = <18>; + clocks = <&clki2c1>; + clock-frequency = <400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts new file mode 100644 index 000000000000..c7a6fe0ce48f --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8850-w70v2.dts + * - Device tree file for Wondermedia WM8850 Tablet + * - 'W70-V2' mainboard + * - HongLianYing 'HLY070ML268-21A' 7" LCD panel + * + * Copyright (C) 2012 Tony Prisk + */ + +/dts-v1/; +/include/ "wm8850.dtsi" +#include + +/ { + model = "Wondermedia WM8850-W70v2 Tablet"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + + brightness-levels = <0 40 60 80 100 130 190 255>; + default-brightness-level = <5>; + }; +}; + +&fb { + bits-per-pixel = <16>; + display-timings { + native-mode = <&timing0>; + timing0: 800x480 { + clock-frequency = <0>; /* unused but required */ + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <88>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi new file mode 100644 index 000000000000..65c9271050e6 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC + * + * Copyright (C) 2012 Tony Prisk + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "wm,wm8850"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "wm,wm8850-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x204>; + }; + + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x20c>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x210>; + }; + + pllf: pllf { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x214>; + }; + + pllg: pllg { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref24>; + reg = <0x218>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <24>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <25>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; + + clkpwm: pwm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + enable-reg = <0x250>; + enable-bit = <17>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x330>; + divisor-mask = <0x3f>; + enable-reg = <0x250>; + enable-bit = <0>; + }; + }; + }; + + fb: fb@d8051700 { + compatible = "wm,wm8505-fb"; + reg = <0xd8051700 0x200>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + pwm: pwm@d8220000 { + #pwm-cells = <3>; + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x100>; + clocks = <&clkpwm>; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <26>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <26>; + }; + + uhci@d8008d00 { + compatible = "platform-uhci"; + reg = <0xd8008d00 0x200>; + interrupts = <26>; + }; + + uart0: serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + status = "disabled"; + }; + + uart1: serial@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + status = "disabled"; + }; + + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + status = "disabled"; + }; + + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + status = "disabled"; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20 21>; + clocks = <&clksdhc>; + bus-width = <4>; + sdon-inverted; + }; + + ethernet@d8004000 { + compatible = "via,vt8500-rhine"; + reg = <0xd8004000 0x100>; + interrupts = <10>; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts deleted file mode 100644 index 2d77c087676e..000000000000 --- a/arch/arm/boot/dts/wm8505-ref.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8505.dtsi" - -/ { - model = "Wondermedia WM8505 Netbook"; -}; - -&fb { - bits-per-pixel = <32>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi deleted file mode 100644 index 168cd12b07bc..000000000000 --- a/arch/arm/boot/dts/wm8505.dtsi +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8505"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8505-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x20c>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <3>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <4>; - }; - - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <22>; - }; - - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <23>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007100 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007100 0x200>; - interrupts = <1>; - }; - - uhci@d8007300 { - compatible = "platform-uhci"; - reg = <0xd8007300 0x200>; - interrupts = <0>; - }; - - fb: fb@d8050800 { - compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <31>; - clocks = <&clkuart4>; - status = "disabled"; - }; - - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <30>; - clocks = <&clkuart5>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x400>; - interrupts = <20>, <21>; - clocks = <&clksdhc>; - bus-width = <4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts deleted file mode 100644 index f6a42149a0a0..000000000000 --- a/arch/arm/boot/dts/wm8650-mid.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8650.dtsi" - -/ { - model = "Wondermedia WM8650-MID Tablet"; -}; - -&fb { - bits-per-pixel = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi deleted file mode 100644 index bc057b6f7d16..000000000000 --- a/arch/arm/boot/dts/wm8650.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8650"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8650-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x20c>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x210>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <43>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x400>; - interrupts = <20>, <21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - fb: fb@d8050800 { - compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts deleted file mode 100644 index 136e812bc1e4..000000000000 --- a/arch/arm/boot/dts/wm8750-apc8750.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8750-apc8750.dts - * - Device tree file for VIA APC8750 - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8750.dtsi" - -/ { - model = "VIA APC8750"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&i2c>; - - i2c: i2c { - wm,pins = <168 169 170 171>; - wm,function = <2>; /* alt */ - wm,pull = <2>; /* pull-up */ - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi deleted file mode 100644 index 33aeb37491f4..000000000000 --- a/arch/arm/boot/dts/wm8750.dtsi +++ /dev/null @@ -1,351 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8750"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm1176jzf"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8750-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x20C>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x210>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <24>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <25>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; - - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <28>; - }; - - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <29>; - }; - - clkpwm: pwm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - enable-reg = <0x250>; - enable-bit = <17>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x330>; - divisor-mask = <0x3f>; - enable-reg = <0x250>; - enable-bit = <0>; - }; - - clki2c0: i2c0clk { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x3A0>; - enable-reg = <0x250>; - enable-bit = <8>; - }; - - clki2c1: i2c1clk { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x3A4>; - enable-reg = <0x250>; - enable-bit = <9>; - }; - }; - }; - - pwm: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x100>; - clocks = <&clkpwm>; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <26>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <26>; - }; - - uhci@d8008d00 { - compatible = "platform-uhci"; - reg = <0xd8008d00 0x200>; - interrupts = <26>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <30>; - clocks = <&clkuart4>; - status = "disabled"; - }; - - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <43>; - clocks = <&clkuart5>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; - - i2c_1: i2c@d8320000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8320000 0x1000>; - interrupts = <18>; - clocks = <&clki2c1>; - clock-frequency = <400000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts deleted file mode 100644 index c7a6fe0ce48f..000000000000 --- a/arch/arm/boot/dts/wm8850-w70v2.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8850-w70v2.dts - * - Device tree file for Wondermedia WM8850 Tablet - * - 'W70-V2' mainboard - * - HongLianYing 'HLY070ML268-21A' 7" LCD panel - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8850.dtsi" -#include - -/ { - model = "Wondermedia WM8850-W70v2 Tablet"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - - brightness-levels = <0 40 60 80 100 130 190 255>; - default-brightness-level = <5>; - }; -}; - -&fb { - bits-per-pixel = <16>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi deleted file mode 100644 index 65c9271050e6..000000000000 --- a/arch/arm/boot/dts/wm8850.dtsi +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8850"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8850-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x20c>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x210>; - }; - - pllf: pllf { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x214>; - }; - - pllg: pllg { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x218>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <24>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <25>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; - - clkpwm: pwm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - enable-reg = <0x250>; - enable-bit = <17>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x330>; - divisor-mask = <0x3f>; - enable-reg = <0x250>; - enable-bit = <0>; - }; - }; - }; - - fb: fb@d8051700 { - compatible = "wm,wm8505-fb"; - reg = <0xd8051700 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - pwm: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x100>; - clocks = <&clkpwm>; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <26>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <26>; - }; - - uhci@d8008d00 { - compatible = "platform-uhci"; - reg = <0xd8008d00 0x200>; - interrupts = <26>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/arch/arm/boot/dts/xen/Makefile b/arch/arm/boot/dts/xen/Makefile new file mode 100644 index 000000000000..26c50f138952 --- /dev/null +++ b/arch/arm/boot/dts/xen/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VIRT) += \ + xenvm-4.2.dtb diff --git a/arch/arm/boot/dts/xen/xenvm-4.2.dts b/arch/arm/boot/dts/xen/xenvm-4.2.dts new file mode 100644 index 000000000000..384cd92f1f84 --- /dev/null +++ b/arch/arm/boot/dts/xen/xenvm-4.2.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xen Virtual Machine for unprivileged guests + * + * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) + * Cortex-A15 MPCore (V2P-CA15) + * + */ + +/dts-v1/; + +/ { + model = "XENVM-4.2"; + compatible = "xen,xenvm-4.2", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + /* this field is going to be adjusted by the hypervisor */ + bootargs = "console=hvc0 root=/dev/xvda"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; + + psci { + compatible = "arm,psci"; + method = "hvc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + memory@80000000 { + device_type = "memory"; + /* this field is going to be adjusted by the hypervisor */ + reg = <0 0x80000000 0 0x08000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x100>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + hypervisor { + compatible = "xen,xen-4.2", "xen,xen"; + /* this field is going to be adjusted by the hypervisor */ + reg = <0 0xb0000000 0 0x20000>; + /* this field is going to be adjusted by the hypervisor */ + interrupts = <1 15 0xf08>; + }; + + motherboard { + arm,v2m-memory-map = "rs1"; + }; +}; diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts deleted file mode 100644 index 384cd92f1f84..000000000000 --- a/arch/arm/boot/dts/xenvm-4.2.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Xen Virtual Machine for unprivileged guests - * - * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) - * Cortex-A15 MPCore (V2P-CA15) - * - */ - -/dts-v1/; - -/ { - model = "XENVM-4.2"; - compatible = "xen,xenvm-4.2", "xen,xenvm"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - /* this field is going to be adjusted by the hypervisor */ - bootargs = "console=hvc0 root=/dev/xvda"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "hvc"; - cpu_off = <1>; - cpu_on = <2>; - }; - - memory@80000000 { - device_type = "memory"; - /* this field is going to be adjusted by the hypervisor */ - reg = <0 0x80000000 0 0x08000000>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x100>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - hypervisor { - compatible = "xen,xen-4.2", "xen,xen"; - /* this field is going to be adjusted by the hypervisor */ - reg = <0 0xb0000000 0 0x20000>; - /* this field is going to be adjusted by the hypervisor */ - interrupts = <1 15 0xf08>; - }; - - motherboard { - arm,v2m-memory-map = "rs1"; - }; -}; diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile new file mode 100644 index 000000000000..9233e539b192 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ + zynq-microzed.dtb \ + zynq-parallella.dtb \ + zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb \ + zynq-zed.dtb \ + zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ + zynq-zybo.dtb \ + zynq-zybo-z7.dtb diff --git a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi new file mode 100644 index 000000000000..a7db3f3009f2 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2011 - 2014 Xilinx + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + clock-latency = <1000>; + cpu0-supply = <®ulator_vccpint>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + >; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&devcfg>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + pmu@f8891000 { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&intc>; + reg = <0xf8891000 0x1000>, + <0xf8893000 0x1000>; + }; + + regulator_vccpint: fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "VCCPINT"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + amba: axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + adc: adc@f8007100 { + compatible = "xlnx,zynq-xadc-1.00.a"; + reg = <0xf8007100 0x20>; + interrupts = <0 7 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 12>; + }; + + can0: can@e0008000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <&clkc 19>, <&clkc 36>; + clock-names = "can_clk", "pclk"; + reg = <0xe0008000 0x1000>; + interrupts = <0 28 4>; + interrupt-parent = <&intc>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can1: can@e0009000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <&clkc 20>, <&clkc 37>; + clock-names = "can_clk", "pclk"; + reg = <0xe0009000 0x1000>; + interrupts = <0 51 4>; + interrupt-parent = <&intc>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + gpio0: gpio@e000a000 { + compatible = "xlnx,zynq-gpio-1.0"; + #gpio-cells = <2>; + clocks = <&clkc 42>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + }; + + i2c0: i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 38>; + interrupt-parent = <&intc>; + interrupts = <0 25 4>; + clock-frequency = <400000>; + reg = <0xe0004000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 39>; + interrupt-parent = <&intc>; + interrupts = <0 48 4>; + clock-frequency = <400000>; + reg = <0xe0005000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller@f8f02000 { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + interrupts = <0 2 4>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + mc: memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; + + uart0: serial@e0000000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "uart_clk", "pclk"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + }; + + uart1: serial@e0001000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "uart_clk", "pclk"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + }; + + spi0: spi@e0006000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0006000 0x1000>; + status = "disabled"; + interrupt-parent = <&intc>; + interrupts = <0 26 4>; + clocks = <&clkc 25>, <&clkc 34>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@e0007000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0007000 0x1000>; + status = "disabled"; + interrupt-parent = <&intc>; + interrupts = <0 49 4>; + clocks = <&clkc 26>, <&clkc 35>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + qspi: spi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + reg = <0xe000d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + clocks = <&clkc 10>, <&clkc 43>; + clock-names = "ref_clk", "pclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gem0: ethernet@e000b000 { + compatible = "xlnx,zynq-gem", "cdns,gem"; + reg = <0xe000b000 0x1000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gem1: ethernet@e000c000 { + compatible = "xlnx,zynq-gem", "cdns,gem"; + reg = <0xe000c000 0x1000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + smcc: memory-controller@e000e000 { + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + reg = <0xe000e000 0x0001000>; + status = "disabled"; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ + 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ + 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ + #address-cells = <2>; + #size-cells = <1>; + + nfc0: nand-controller@0,0 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0 0 0x1000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sdhci0: mmc@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&intc>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + }; + + sdhci1: mmc@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + interrupt-parent = <&intc>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + }; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + + rstc: rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <1>; + syscon = <&slcr>; + }; + + pinctrl0: pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + }; + }; + + dmac_s: dma-controller@f8003000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xf8003000 0x1000>; + interrupt-parent = <&intc>; + /* + * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + * "dma4", "dma5", "dma6", "dma7"; + */ + interrupts = <0 13 4>, + <0 14 4>, <0 15 4>, + <0 16 4>, <0 17 4>, + <0 40 4>, <0 41 4>, + <0 42 4>, <0 43 4>; + #dma-cells = <1>; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; + }; + + devcfg: devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; + clocks = <&clkc 12>; + clock-names = "ref_clk"; + syscon = <&slcr>; + }; + + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + + ttc0: timer@f8001000 { + interrupt-parent = <&intc>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8001000 0x1000>; + }; + + ttc1: timer@f8002000 { + interrupt-parent = <&intc>; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8002000 0x1000>; + }; + + scutimer: timer@f8f00600 { + interrupt-parent = <&intc>; + interrupts = <1 13 0x301>; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clocks = <&clkc 4>; + }; + + usb0: usb@e0002000 { + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + status = "disabled"; + clocks = <&clkc 28>; + interrupt-parent = <&intc>; + interrupts = <0 21 4>; + reg = <0xe0002000 0x1000>; + phy_type = "ulpi"; + }; + + usb1: usb@e0003000 { + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + status = "disabled"; + clocks = <&clkc 29>; + interrupt-parent = <&intc>; + interrupts = <0 44 4>; + reg = <0xe0003000 0x1000>; + phy_type = "ulpi"; + }; + + watchdog0: watchdog@f8005000 { + clocks = <&clkc 45>; + compatible = "cdns,wdt-r1p2"; + interrupt-parent = <&intc>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + timeout-sec = <10>; + }; + + etb@f8801000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0xf8801000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@f8803000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xf8803000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel@f8804000 { + compatible = "arm,coresight-static-funnel", "arm,primecell"; + reg = <0xf8804000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel0_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel0_in_port2: endpoint { + }; + }; + /* The other input ports are not connect to anything */ + }; + }; + + ptm@f889c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xf889c000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + cpu = <&cpu0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; + }; + + ptm@f889d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xf889d000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + cpu = <&cpu1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel0_in_port1>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-cc108.dts b/arch/arm/boot/dts/xilinx/zynq-cc108.dts new file mode 100644 index 000000000000..8b9ab9bba23b --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-cc108.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CC108 board DTS + * + * (C) Copyright 2007-2018 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Xilinx CC108 board"; + compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci1 { + status = "okay"; + broken-cd ; + wp-inverted ; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts new file mode 100644 index 000000000000..53fa6dbfd8fd --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Michael Walle + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Ebang EBAZ4205"; + compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; + fclk-enable = <8>; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <&phy>; + + /* PHY clock */ + assigned-clocks = <&clkc 18>; + assigned-clock-rates = <25000000>; + + phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&nfc0 { + status = "okay"; + + nand@0 { + reg = <0>; + }; +}; + +&pinctrl0 { + pinctrl_gpio0_default: gpio0-default { + mux { + groups = "gpio0_20_grp", "gpio0_32_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_20_grp", "gpio0_32_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-pull-up { + pins = "MIO20", "MIO32"; + bias-disable; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_34_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_34_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-high-impedance; + bias-pull-up; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_4_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_4_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; +}; + +&smcc { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-microzed.dts b/arch/arm/boot/dts/xilinx/zynq-microzed.dts new file mode 100644 index 000000000000..6ed84fb15902 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-microzed.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2016 Jagan Teki + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Avnet MicroZed board"; + compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; + +&pinctrl0 { + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-parallella.dts b/arch/arm/boot/dts/xilinx/zynq-parallella.dts new file mode 100644 index 000000000000..54592aeb92b9 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-parallella.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * Derived from zynq-zed.dts: + * + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * Copyright (C) 2013 Xilinx + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Adapteva Parallella board"; + compatible = "adapteva,parallella", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + /* Marvell 88E1318 */ + compatible = "ethernet-phy-id0141.0e90", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + device_type = "ethernet-phy"; + marvell,reg-init = <0x3 0x10 0xff00 0x1e>, + <0x3 0x11 0xfff0 0xa>; + }; +}; + +&i2c0 { + status = "okay"; + + isl9305: isl9305@68 { + compatible = "isil,isl9305"; + reg = <0x68>; + + regulators { + dcd1 { + regulator-name = "VDD_DSP"; + regulator-always-on; + }; + dcd2 { + regulator-name = "1P35V"; + regulator-always-on; + }; + ldo1 { + regulator-name = "VDD_ADJ"; + }; + ldo2 { + regulator-name = "VDD_GPIO"; + regulator-always-on; + }; + }; + }; +}; + +&sdhci1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts new file mode 100644 index 000000000000..6efdbca9d3ef --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + */ +/dts-v1/; +#include "zynq-7000.dtsi" +#include + +/ { + model = "Xilinx ZC702 board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + serial0 = &uart1; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + switch-14 { + label = "sw14"; + gpios = <&gpio0 12 0>; + linux,code = <108>; /* down */ + wakeup-source; + autorepeat; + }; + switch-13 { + label = "sw13"; + gpios = <&gpio0 14 0>; + linux,code = <103>; /* up */ + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-ds23 { + label = "ds23"; + gpios = <&gpio0 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&amba { + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + adv7511: hdmi-tx@39 { + compatible = "adi,adv7511"; + reg = <0x39>; + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + adi,input-style = <3>; + adi,input-justification = "right"; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@34 { + compatible = "ti,ucd9248"; + reg = <0x34>; + }; + hwmon@35 { + compatible = "ti,ucd9248"; + reg = <0x35>; + }; + hwmon@36 { + compatible = "ti,ucd9248"; + reg = <0x36>; + }; + }; + }; +}; + +&pinctrl0 { + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_9_grp"; + }; + + conf { + groups = "can0_9_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO46"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO47"; + bias-disable; + }; + }; + + pinctrl_gem0_default: gem0-default { + mux { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + }; + + conf { + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + conf-rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + }; + + conf-mdio { + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: gpio0-default { + mux { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + }; + + conf { + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-pull-up { + pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO7", "MIO8"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_10_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_10_grp"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_50_grp", "gpio0_51_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_50_grp", "gpio0_51_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_0_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + mux-wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "gpio0_15_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts new file mode 100644 index 000000000000..77943c16d33f --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zc706.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Xilinx ZC706 board"; + compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + serial0 = &uart1; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + adv7511: hdmi-tx@39 { + compatible = "adi,adv7511"; + reg = <0x39>; + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + adi,input-style = <3>; + adi,input-justification = "evenly"; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + ucd90120@65 { + compatible = "ti,ucd90120"; + reg = <0x65>; + }; + }; + }; +}; + +&pinctrl0 { + pinctrl_gem0_default: gem0-default { + mux { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + }; + + conf { + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + conf-rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + low-power-enable; + bias-disable; + }; + + mux-mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + }; + + conf-mdio { + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: gpio0-default { + mux { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + }; + + conf { + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-pull-up { + pins = "MIO46", "MIO47"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO7"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_10_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_10_grp"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_14_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_14_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + mux-wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "gpio0_15_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts new file mode 100644 index 000000000000..0dd352289a45 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Xilinx ZC770 XM010 board"; + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + serial0 = &uart1; + spi1 = &spi1; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + +}; + +&sdhci0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@1 { + compatible = "sst25wf080", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <1000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "data"; + reg = <0x0 0x100000>; + }; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts new file mode 100644 index 000000000000..56732e8f6ca1 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM011 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Xilinx ZC770 XM011 board"; + compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c1; + serial0 = &uart1; + spi0 = &spi0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts new file mode 100644 index 000000000000..d2359b789eb8 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Xilinx ZC770 XM012 board"; + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart1; + spi0 = &spi1; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + eeprom0: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom1: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts new file mode 100644 index 000000000000..38d96adc870c --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Xilinx ZC770 XM013 board"; + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem1; + i2c0 = &i2c1; + serial0 = &uart0; + spi1 = &spi0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + si570: clock-generator@55 { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x55>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: eeprom@2 { + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + size = <8192>; + address-width = <16>; + pagesize = <32>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zed.dts b/arch/arm/boot/dts/xilinx/zynq-zed.dts new file mode 100644 index 000000000000..6a5a93aa6552 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zed.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Avnet ZedBoard board"; + compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi new file mode 100644 index 000000000000..dfb1fbafe3aa --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello + * Copyright (C) 2017 Alexander Graf + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + key { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + wakeup-source; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts b/arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts new file mode 100644 index 000000000000..536632a09a25 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +/include/ "zynq-zturn-common.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board V5"; + compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; +}; + +&gem0 { + ethernet_phy: ethernet-phy@0 { + reg = <0x3>; + }; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zturn.dts b/arch/arm/boot/dts/xilinx/zynq-zturn.dts new file mode 100644 index 000000000000..620b24a25e06 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zturn.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +/include/ "zynq-zturn-common.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board"; + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; +}; + +&gem0 { + ethernet_phy: ethernet-phy@0 { + reg = <0x0>; + }; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts new file mode 100644 index 000000000000..7b87e10d3953 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "zynq-7000.dtsi" +#include + +/ { + model = "Digilent Zybo Z7 board"; + compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-ld4 { + label = "zynq-zybo-z7:green:ld4"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_phy0: phy0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-zybo.dts b/arch/arm/boot/dts/xilinx/zynq-zybo.dts new file mode 100644 index 000000000000..755f6f109d5a --- /dev/null +++ b/arch/arm/boot/dts/xilinx/zynq-zybo.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Digilent Zybo board"; + compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 1>; + }; +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi deleted file mode 100644 index a7db3f3009f2..000000000000 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,zynq-7000"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - clocks = <&clkc 3>; - clock-latency = <1000>; - cpu0-supply = <®ulator_vccpint>; - operating-points = < - /* kHz uV */ - 666667 1000000 - 333334 1000000 - >; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - clocks = <&clkc 3>; - }; - }; - - fpga_full: fpga-full { - compatible = "fpga-region"; - fpga-mgr = <&devcfg>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - pmu@f8891000 { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 5 4>, <0 6 4>; - interrupt-parent = <&intc>; - reg = <0xf8891000 0x1000>, - <0xf8893000 0x1000>; - }; - - regulator_vccpint: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "VCCPINT"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - }; - in-ports { - /* replicator input port */ - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port>; - }; - }; - }; - }; - - amba: axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - adc: adc@f8007100 { - compatible = "xlnx,zynq-xadc-1.00.a"; - reg = <0xf8007100 0x20>; - interrupts = <0 7 4>; - interrupt-parent = <&intc>; - clocks = <&clkc 12>; - }; - - can0: can@e0008000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clocks = <&clkc 19>, <&clkc 36>; - clock-names = "can_clk", "pclk"; - reg = <0xe0008000 0x1000>; - interrupts = <0 28 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; - - can1: can@e0009000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clocks = <&clkc 20>, <&clkc 37>; - clock-names = "can_clk", "pclk"; - reg = <0xe0009000 0x1000>; - interrupts = <0 51 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; - - gpio0: gpio@e000a000 { - compatible = "xlnx,zynq-gpio-1.0"; - #gpio-cells = <2>; - clocks = <&clkc 42>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <0 20 4>; - reg = <0xe000a000 0x1000>; - }; - - i2c0: i2c@e0004000 { - compatible = "cdns,i2c-r1p10"; - status = "disabled"; - clocks = <&clkc 38>; - interrupt-parent = <&intc>; - interrupts = <0 25 4>; - clock-frequency = <400000>; - reg = <0xe0004000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@e0005000 { - compatible = "cdns,i2c-r1p10"; - status = "disabled"; - clocks = <&clkc 39>; - interrupt-parent = <&intc>; - interrupts = <0 48 4>; - clock-frequency = <400000>; - reg = <0xe0005000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - - L2: cache-controller@f8f02000 { - compatible = "arm,pl310-cache"; - reg = <0xF8F02000 0x1000>; - interrupts = <0 2 4>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - mc: memory-controller@f8006000 { - compatible = "xlnx,zynq-ddrc-a05"; - reg = <0xf8006000 0x1000>; - }; - - uart0: serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - status = "disabled"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; - }; - - uart1: serial@e0001000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - status = "disabled"; - clocks = <&clkc 24>, <&clkc 41>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0001000 0x1000>; - interrupts = <0 50 4>; - }; - - spi0: spi@e0006000 { - compatible = "xlnx,zynq-spi-r1p6"; - reg = <0xe0006000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 26 4>; - clocks = <&clkc 25>, <&clkc 34>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@e0007000 { - compatible = "xlnx,zynq-spi-r1p6"; - reg = <0xe0007000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 49 4>; - clocks = <&clkc 26>, <&clkc 35>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi: spi@e000d000 { - compatible = "xlnx,zynq-qspi-1.0"; - reg = <0xe000d000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <0 19 4>; - clocks = <&clkc 10>, <&clkc 43>; - clock-names = "ref_clk", "pclk"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gem0: ethernet@e000b000 { - compatible = "xlnx,zynq-gem", "cdns,gem"; - reg = <0xe000b000 0x1000>; - status = "disabled"; - interrupts = <0 22 4>; - clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gem1: ethernet@e000c000 { - compatible = "xlnx,zynq-gem", "cdns,gem"; - reg = <0xe000c000 0x1000>; - status = "disabled"; - interrupts = <0 45 4>; - clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - smcc: memory-controller@e000e000 { - compatible = "arm,pl353-smc-r2p1", "arm,primecell"; - reg = <0xe000e000 0x0001000>; - status = "disabled"; - clock-names = "memclk", "apb_pclk"; - clocks = <&clkc 11>, <&clkc 44>; - ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ - 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ - 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ - #address-cells = <2>; - #size-cells = <1>; - - nfc0: nand-controller@0,0 { - compatible = "arm,pl353-nand-r2p1"; - reg = <0 0 0x1000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sdhci0: mmc@e0100000 { - compatible = "arasan,sdhci-8.9a"; - status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 21>, <&clkc 32>; - interrupt-parent = <&intc>; - interrupts = <0 24 4>; - reg = <0xe0100000 0x1000>; - }; - - sdhci1: mmc@e0101000 { - compatible = "arasan,sdhci-8.9a"; - status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 22>, <&clkc 33>; - interrupt-parent = <&intc>; - interrupts = <0 47 4>; - reg = <0xe0101000 0x1000>; - }; - - slcr: slcr@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; - reg = <0xF8000000 0x1000>; - ranges; - clkc: clkc@100 { - #clock-cells = <1>; - compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", - "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", - "dci", "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", - "dma", "usb0_aper", "usb1_aper", "gem0_aper", - "gem1_aper", "sdio0_aper", "sdio1_aper", - "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", - "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", - "gpio_aper", "lqspi_aper", "smc_aper", "swdt", - "dbg_trc", "dbg_apb"; - reg = <0x100 0x100>; - }; - - rstc: rstc@200 { - compatible = "xlnx,zynq-reset"; - reg = <0x200 0x48>; - #reset-cells = <1>; - syscon = <&slcr>; - }; - - pinctrl0: pinctrl@700 { - compatible = "xlnx,pinctrl-zynq"; - reg = <0x700 0x200>; - syscon = <&slcr>; - }; - }; - - dmac_s: dma-controller@f8003000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xf8003000 0x1000>; - interrupt-parent = <&intc>; - /* - * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", - * "dma4", "dma5", "dma6", "dma7"; - */ - interrupts = <0 13 4>, - <0 14 4>, <0 15 4>, - <0 16 4>, <0 17 4>, - <0 40 4>, <0 41 4>, - <0 42 4>, <0 43 4>; - #dma-cells = <1>; - clocks = <&clkc 27>; - clock-names = "apb_pclk"; - }; - - devcfg: devcfg@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; - - global_timer: timer@f8f00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf8f00200 0x20>; - interrupts = <1 11 0x301>; - interrupt-parent = <&intc>; - clocks = <&clkc 4>; - }; - - ttc0: timer@f8001000 { - interrupt-parent = <&intc>; - interrupts = <0 10 4>, <0 11 4>, <0 12 4>; - compatible = "cdns,ttc"; - clocks = <&clkc 6>; - reg = <0xF8001000 0x1000>; - }; - - ttc1: timer@f8002000 { - interrupt-parent = <&intc>; - interrupts = <0 37 4>, <0 38 4>, <0 39 4>; - compatible = "cdns,ttc"; - clocks = <&clkc 6>; - reg = <0xF8002000 0x1000>; - }; - - scutimer: timer@f8f00600 { - interrupt-parent = <&intc>; - interrupts = <1 13 0x301>; - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf8f00600 0x20>; - clocks = <&clkc 4>; - }; - - usb0: usb@e0002000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; - status = "disabled"; - clocks = <&clkc 28>; - interrupt-parent = <&intc>; - interrupts = <0 21 4>; - reg = <0xe0002000 0x1000>; - phy_type = "ulpi"; - }; - - usb1: usb@e0003000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; - status = "disabled"; - clocks = <&clkc 29>; - interrupt-parent = <&intc>; - interrupts = <0 44 4>; - reg = <0xe0003000 0x1000>; - phy_type = "ulpi"; - }; - - watchdog0: watchdog@f8005000 { - clocks = <&clkc 45>; - compatible = "cdns,wdt-r1p2"; - interrupt-parent = <&intc>; - interrupts = <0 9 1>; - reg = <0xf8005000 0x1000>; - timeout-sec = <10>; - }; - - etb@f8801000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0xf8801000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - tpiu@f8803000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0xf8803000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - funnel@f8804000 { - compatible = "arm,coresight-static-funnel", "arm,primecell"; - reg = <0xf8804000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - - /* funnel output ports */ - out-ports { - port { - funnel_out_port: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - funnel0_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel0_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel0_in_port2: endpoint { - }; - }; - /* The other input ports are not connect to anything */ - }; - }; - - ptm@f889c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0xf889c000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - cpu = <&cpu0>; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel0_in_port0>; - }; - }; - }; - }; - - ptm@f889d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0xf889d000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - cpu = <&cpu1>; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel0_in_port1>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/zynq-cc108.dts deleted file mode 100644 index 8b9ab9bba23b..000000000000 --- a/arch/arm/boot/dts/zynq-cc108.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx CC108 board DTS - * - * (C) Copyright 2007-2018 Xilinx, Inc. - * (C) Copyright 2007-2013 Michal Simek - * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd - * - * Michal SIMEK - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Xilinx CC108 board"; - compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart0; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usb_phy1: phy1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci1 { - status = "okay"; - broken-cd ; - wp-inverted ; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy1>; -}; diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts deleted file mode 100644 index 53fa6dbfd8fd..000000000000 --- a/arch/arm/boot/dts/zynq-ebaz4205.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Michael Walle - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Ebang EBAZ4205"; - compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; - fclk-enable = <8>; -}; - -&gem0 { - status = "okay"; - phy-mode = "mii"; - phy-handle = <&phy>; - - /* PHY clock */ - assigned-clocks = <&clkc 18>; - assigned-clock-rates = <25000000>; - - phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&nfc0 { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; - -&pinctrl0 { - pinctrl_gpio0_default: gpio0-default { - mux { - groups = "gpio0_20_grp", "gpio0_32_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_20_grp", "gpio0_32_grp"; - io-standard = <3>; - slew-rate = <0>; - }; - - conf-pull-up { - pins = "MIO20", "MIO32"; - bias-disable; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - io-standard = <3>; - slew-rate = <0>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_34_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_34_grp"; - io-standard = <3>; - slew-rate = <0>; - bias-high-impedance; - bias-pull-up; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_4_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_4_grp"; - io-standard = <3>; - slew-rate = <0>; - }; - - conf-rx { - pins = "MIO25"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO24"; - bias-disable; - }; - }; -}; - -&smcc { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts deleted file mode 100644 index 6ed84fb15902..000000000000 --- a/arch/arm/boot/dts/zynq-microzed.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2016 Jagan Teki - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Avnet MicroZed board"; - compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; - -&pinctrl0 { - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts deleted file mode 100644 index 54592aeb92b9..000000000000 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 SUSE LINUX Products GmbH - * - * Derived from zynq-zed.dts: - * - * Copyright (C) 2011 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Adapteva Parallella board"; - compatible = "adapteva,parallella", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; - stdout-path = "serial0:115200n8"; - }; -}; - -&clkc { - fclk-enable = <0xf>; - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - /* Marvell 88E1318 */ - compatible = "ethernet-phy-id0141.0e90", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - device_type = "ethernet-phy"; - marvell,reg-init = <0x3 0x10 0xff00 0x1e>, - <0x3 0x11 0xfff0 0xa>; - }; -}; - -&i2c0 { - status = "okay"; - - isl9305: isl9305@68 { - compatible = "isil,isl9305"; - reg = <0x68>; - - regulators { - dcd1 { - regulator-name = "VDD_DSP"; - regulator-always-on; - }; - dcd2 { - regulator-name = "1P35V"; - regulator-always-on; - }; - ldo1 { - regulator-name = "VDD_ADJ"; - }; - ldo2 { - regulator-name = "VDD_GPIO"; - regulator-always-on; - }; - }; - }; -}; - -&sdhci1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts deleted file mode 100644 index 6efdbca9d3ef..000000000000 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" -#include - -/ { - model = "Xilinx ZC702 board"; - compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - switch-14 { - label = "sw14"; - gpios = <&gpio0 12 0>; - linux,code = <108>; /* down */ - wakeup-source; - autorepeat; - }; - switch-13 { - label = "sw13"; - gpios = <&gpio0 14 0>; - linux,code = <103>; /* up */ - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-ds23 { - label = "ds23"; - gpios = <&gpio0 10 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffc0000 0x10000>; - ocm-sram@0 { - reg = <0x0 0x10000>; - }; - }; -}; - -&can0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem0_default>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - i2c-mux@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - adv7511: hdmi-tx@39 { - compatible = "adi,adv7511"; - reg = <0x39>; - adi,input-depth = <8>; - adi,input-colorspace = "yuv422"; - adi,input-clock = "1x"; - adi,input-style = <3>; - adi,input-justification = "right"; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - hwmon@34 { - compatible = "ti,ucd9248"; - reg = <0x34>; - }; - hwmon@35 { - compatible = "ti,ucd9248"; - reg = <0x35>; - }; - hwmon@36 { - compatible = "ti,ucd9248"; - reg = <0x36>; - }; - }; - }; -}; - -&pinctrl0 { - pinctrl_can0_default: can0-default { - mux { - function = "can0"; - groups = "can0_9_grp"; - }; - - conf { - groups = "can0_9_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO46"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO47"; - bias-disable; - }; - }; - - pinctrl_gem0_default: gem0-default { - mux { - function = "ethernet0"; - groups = "ethernet0_0_grp"; - }; - - conf { - groups = "ethernet0_0_grp"; - slew-rate = <0>; - io-standard = <4>; - }; - - conf-rx { - pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio0"; - groups = "mdio0_0_grp"; - }; - - conf-mdio { - groups = "mdio0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - }; - - pinctrl_gpio0_default: gpio0-default { - mux { - function = "gpio0"; - groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", - "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", - "gpio0_13_grp", "gpio0_14_grp"; - }; - - conf { - groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", - "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", - "gpio0_13_grp", "gpio0_14_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-pull-up { - pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO7", "MIO8"; - bias-disable; - }; - }; - - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_10_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_10_grp"; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_i2c0_gpio: i2c0-gpio { - mux { - groups = "gpio0_50_grp", "gpio0_51_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_50_grp", "gpio0_51_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_0_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - - mux-wp { - groups = "gpio0_15_grp"; - function = "sdio0_wp"; - }; - - conf-wp { - groups = "gpio0_15_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts deleted file mode 100644 index 77943c16d33f..000000000000 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC706 board"; - compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem0_default>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - i2c-mux@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - adv7511: hdmi-tx@39 { - compatible = "adi,adv7511"; - reg = <0x39>; - adi,input-depth = <8>; - adi,input-colorspace = "yuv422"; - adi,input-clock = "1x"; - adi,input-style = <3>; - adi,input-justification = "evenly"; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - ucd90120@65 { - compatible = "ti,ucd90120"; - reg = <0x65>; - }; - }; - }; -}; - -&pinctrl0 { - pinctrl_gem0_default: gem0-default { - mux { - function = "ethernet0"; - groups = "ethernet0_0_grp"; - }; - - conf { - groups = "ethernet0_0_grp"; - slew-rate = <0>; - io-standard = <4>; - }; - - conf-rx { - pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; - low-power-enable; - bias-disable; - }; - - mux-mdio { - function = "mdio0"; - groups = "mdio0_0_grp"; - }; - - conf-mdio { - groups = "mdio0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - }; - - pinctrl_gpio0_default: gpio0-default { - mux { - function = "gpio0"; - groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; - }; - - conf { - groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-pull-up { - pins = "MIO46", "MIO47"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO7"; - bias-disable; - }; - }; - - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_10_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_10_grp"; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_14_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_14_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - - mux-wp { - groups = "gpio0_15_grp"; - function = "sdio0_wp"; - }; - - conf-wp { - groups = "gpio0_15_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts deleted file mode 100644 index 0dd352289a45..000000000000 --- a/arch/arm/boot/dts/zynq-zc770-xm010.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM010 board DTS - * - * Copyright (C) 2013-2018 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM010 board"; - compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - spi1 = &spi1; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&can0 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; - -}; - -&sdhci0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - flash@1 { - compatible = "sst25wf080", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <1000000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "data"; - reg = <0x0 0x100000>; - }; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts deleted file mode 100644 index 56732e8f6ca1..000000000000 --- a/arch/arm/boot/dts/zynq-zc770-xm011.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM011 board DTS - * - * Copyright (C) 2013-2018 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM011 board"; - compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; - - aliases { - i2c0 = &i2c1; - serial0 = &uart1; - spi0 = &spi0; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - usb_phy1: phy1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&can0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; -}; - -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - -&uart1 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy1>; -}; diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/zynq-zc770-xm012.dts deleted file mode 100644 index d2359b789eb8..000000000000 --- a/arch/arm/boot/dts/zynq-zc770-xm012.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM012 board DTS - * - * Copyright (C) 2013-2018 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM012 board"; - compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart1; - spi0 = &spi1; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&can1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - eeprom0: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - eeprom1: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; -}; - -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts deleted file mode 100644 index 38d96adc870c..000000000000 --- a/arch/arm/boot/dts/zynq-zc770-xm013.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM013 board DTS - * - * Copyright (C) 2013 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM013 board"; - compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem1; - i2c0 = &i2c1; - serial0 = &uart0; - spi1 = &spi0; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&can1 { - status = "okay"; -}; - -&gem1 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - si570: clock-generator@55 { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x55>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; -}; - -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - eeprom: eeprom@2 { - compatible = "atmel,at25"; - reg = <2>; - spi-max-frequency = <1000000>; - size = <8192>; - address-width = <16>; - pagesize = <32>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts deleted file mode 100644 index 6a5a93aa6552..000000000000 --- a/arch/arm/boot/dts/zynq-zed.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Avnet ZedBoard board"; - compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi deleted file mode 100644 index dfb1fbafe3aa..000000000000 --- a/arch/arm/boot/dts/zynq-zturn-common.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Andrea Merello - * Copyright (C) 2017 Alexander Graf - * - * Based on zynq-zed.dts which is: - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - */ - -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - compatible = "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - serial1 = &uart0; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - usr-led1 { - label = "usr-led1"; - gpios = <&gpio0 0x0 0x1>; - default-state = "off"; - }; - - usr-led2 { - label = "usr-led2"; - gpios = <&gpio0 0x9 0x1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - key { - label = "K1"; - gpios = <&gpio0 0x32 0x1>; - linux,code = <0x66>; - wakeup-source; - autorepeat; - }; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&can0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - stlm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; - - accelerometer@53 { - compatible = "adi,adxl345"; - reg = <0x53>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - }; -}; diff --git a/arch/arm/boot/dts/zynq-zturn-v5.dts b/arch/arm/boot/dts/zynq-zturn-v5.dts deleted file mode 100644 index 536632a09a25..000000000000 --- a/arch/arm/boot/dts/zynq-zturn-v5.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; -/include/ "zynq-zturn-common.dtsi" - -/ { - model = "Zynq Z-Turn MYIR Board V5"; - compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; -}; - -&gem0 { - ethernet_phy: ethernet-phy@0 { - reg = <0x3>; - }; -}; diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts deleted file mode 100644 index 620b24a25e06..000000000000 --- a/arch/arm/boot/dts/zynq-zturn.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; -/include/ "zynq-zturn-common.dtsi" - -/ { - model = "Zynq Z-Turn MYIR Board"; - compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; -}; - -&gem0 { - ethernet_phy: ethernet-phy@0 { - reg = <0x0>; - }; -}; diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts deleted file mode 100644 index 7b87e10d3953..000000000000 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "zynq-7000.dtsi" -#include - -/ { - model = "Digilent Zybo Z7 board"; - compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-ld4 { - label = "zynq-zybo-z7:green:ld4"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_phy0: phy0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts deleted file mode 100644 index 755f6f109d5a..000000000000 --- a/arch/arm/boot/dts/zynq-zybo.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Digilent Zybo board"; - compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 1>; - }; -}; - -&clkc { - ps-clk-frequency = <50000000>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts index 8857a3791593..6406a29c85f2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts @@ -4,7 +4,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" #include "sun50i-h5-cpu-opp.dtsi" -#include +#include / { model = "Banana Pi BPI-M2-Plus v1.2 H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts index 77661006dfba..cfb943e9ae85 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include / { model = "Banana Pi BPI-M2-Plus H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi index fc570011495f..2f4b46746f47 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi @@ -8,4 +8,4 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts index d811df332824..b79018c65cae 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts @@ -5,7 +5,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" #include "sun50i-h5-cpu-opp.dtsi" -#include +#include / { model = "Libre Computer Board ALL-H3-CC H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts index e59d68b525fc..dc657de2a1a4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include / { model = "Libre Computer Board ALL-H3-IT H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index a56fae761a1f..d3caf27b6a55 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2016 ARM Ltd. -#include +#include #include diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 796cd7d02eb5..3554201e94d6 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -13,7 +13,7 @@ /dts-v1/; #include -#include "vexpress-v2m-rs1.dtsi" +#include "arm/arm/vexpress-v2m-rs1.dtsi" / { model = "V2F-1XV7 Cortex-A53x2 SMM"; diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts index d24c53682e44..c7280bdefa8d 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-4-b.dts" +#include "arm/broadcom/bcm2711-rpi-4-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts index b9000f58beb5..d9d2852b794f 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-400.dts" +#include "arm/broadcom/bcm2711-rpi-400.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts index e36d395e3951..8810322aa66a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-cm4-io.dts" +#include "arm/broadcom/bcm2711-rpi-cm4-io.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts index f0ec56a1c4d7..17d778a7e0c9 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-a-plus.dts" +#include "arm/broadcom/bcm2837-rpi-3-a-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts index 46ad2023cccf..0cf6240b6bf0 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b-plus.dts" +#include "arm/broadcom/bcm2837-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts index 89b78d6c19bf..f429468fd86e 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b.dts" +#include "arm/broadcom/bcm2837-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts index b1c4ab212c64..3fa21bd16b49 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-cm3-io3.dts" +#include "arm/broadcom/bcm2837-rpi-cm3-io3.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts index 307ae693e4a0..363381a0cfb5 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-zero-2-w.dts" +#include "arm/broadcom/bcm2837-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index b1fa68835b09..5ea8bda2bfa6 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -734,4 +734,4 @@ }; #include "exynos7-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 23c2e0bb0a2c..d69fc2392bd0 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -452,4 +452,4 @@ }; #include "exynos7885-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts index 369de5dc0ebd..c58fb7658d7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include +#include #include "rk3399pro-vmarc-som.dtsi" / { diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi index 9caabbb8bae3..3e1132204c7d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi index e66d999d9f5d..8afbe5ce45f2 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi index 28c5b4ed1d95..6d0e3226a966 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi @@ -1 +1 @@ -#include +#include -- cgit v1.2.3